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[ARM] Add armelf_linux_fdpiceabi and armelfb_linux_fdpiceabi BFD backends
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
219d1afa 2 Copyright (C) 1998-2018 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
f3185997 59#define elf_info_to_howto NULL
07d6d2b8 60#define elf_info_to_howto_rel elf32_arm_info_to_howto
7f266840
DJ		 61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
07d6d2b8 240 HOWTO (R_ARM_THM_PC8, /* type */
7f266840
DJ		 241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
07d6d2b8
AM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
99059e56
RM		 334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
07d6d2b8 340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
07d6d2b8
AM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
99059e56
RM		 348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
07d6d2b8 354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
07d6d2b8
AM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
99059e56
RM		 362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
07d6d2b8 368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
07d6d2b8
AM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
99059e56
RM		 378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
07d6d2b8 384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
07d6d2b8
AM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
99059e56
RM		 392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
07d6d2b8 398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
07d6d2b8
AM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
99059e56
RM		 406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
07d6d2b8 412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
07d6d2b8
AM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
99059e56
RM		 420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
07d6d2b8 426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
07d6d2b8
AM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
99059e56
RM		 434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
07d6d2b8 440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
07d6d2b8
AM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
99059e56 446 TRUE, /* pc_relative */
07d6d2b8 447 0, /* bitpos */
99059e56
RM		 448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
07d6d2b8
AM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
99059e56 460 FALSE, /* pc_relative */
07d6d2b8 461 0, /* bitpos */
99059e56
RM		 462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
07d6d2b8
AM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
99059e56 474 TRUE, /* pc_relative */
07d6d2b8 475 0, /* bitpos */
99059e56
RM		 476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
07d6d2b8 909 HOWTO (R_ARM_ALU_PC_G0, /* type */
4962c51a
MS		 910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 917 "R_ARM_ALU_PC_G0", /* name */
4962c51a
MS		 918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
07d6d2b8 937 HOWTO (R_ARM_ALU_PC_G1, /* type */
4962c51a
MS		 938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 945 "R_ARM_ALU_PC_G1", /* name */
4962c51a
MS		 946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
07d6d2b8 951 HOWTO (R_ARM_ALU_PC_G2, /* type */
4962c51a
MS		 952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 959 "R_ARM_ALU_PC_G2", /* name */
4962c51a
MS		 960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
07d6d2b8 965 HOWTO (R_ARM_LDR_PC_G1, /* type */
4962c51a
MS		 966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 973 "R_ARM_LDR_PC_G1", /* name */
4962c51a
MS		 974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
07d6d2b8 979 HOWTO (R_ARM_LDR_PC_G2, /* type */
4962c51a
MS		 980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 987 "R_ARM_LDR_PC_G2", /* name */
4962c51a
MS		 988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
07d6d2b8 993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
4962c51a
MS		 994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1001 "R_ARM_LDRS_PC_G0", /* name */
4962c51a
MS		 1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
07d6d2b8 1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
4962c51a
MS		 1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1015 "R_ARM_LDRS_PC_G1", /* name */
4962c51a
MS		 1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
07d6d2b8 1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
4962c51a
MS		 1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1029 "R_ARM_LDRS_PC_G2", /* name */
4962c51a
MS		 1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
07d6d2b8 1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
4962c51a
MS		 1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1043 "R_ARM_LDC_PC_G0", /* name */
4962c51a
MS		 1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
07d6d2b8 1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
4962c51a
MS		 1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1057 "R_ARM_LDC_PC_G1", /* name */
4962c51a
MS		 1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
07d6d2b8 1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
4962c51a
MS		 1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1071 "R_ARM_LDC_PC_G2", /* name */
4962c51a
MS		 1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
07d6d2b8 1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
4962c51a
MS		 1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1085 "R_ARM_ALU_SB_G0_NC", /* name */
4962c51a
MS		 1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
07d6d2b8 1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
4962c51a
MS		 1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1099 "R_ARM_ALU_SB_G0", /* name */
4962c51a
MS		 1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
07d6d2b8 1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
4962c51a
MS		 1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1113 "R_ARM_ALU_SB_G1_NC", /* name */
4962c51a
MS		 1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
07d6d2b8 1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
4962c51a
MS		 1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1127 "R_ARM_ALU_SB_G1", /* name */
4962c51a
MS		 1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
07d6d2b8 1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
4962c51a
MS		 1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1141 "R_ARM_ALU_SB_G2", /* name */
4962c51a
MS		 1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
07d6d2b8 1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
4962c51a
MS		 1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1155 "R_ARM_LDR_SB_G0", /* name */
4962c51a
MS		 1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
07d6d2b8 1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
4962c51a
MS		 1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1169 "R_ARM_LDR_SB_G1", /* name */
4962c51a
MS		 1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
07d6d2b8 1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
4962c51a
MS		 1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1183 "R_ARM_LDR_SB_G2", /* name */
4962c51a
MS		 1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
07d6d2b8 1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
4962c51a
MS		 1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1197 "R_ARM_LDRS_SB_G0", /* name */
4962c51a
MS		 1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
07d6d2b8 1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
4962c51a
MS		 1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1211 "R_ARM_LDRS_SB_G1", /* name */
4962c51a
MS		 1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
07d6d2b8 1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
4962c51a
MS		 1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1225 "R_ARM_LDRS_SB_G2", /* name */
4962c51a
MS		 1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
07d6d2b8 1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
4962c51a
MS		 1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1239 "R_ARM_LDC_SB_G0", /* name */
4962c51a
MS		 1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
07d6d2b8 1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
4962c51a
MS		 1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1253 "R_ARM_LDC_SB_G1", /* name */
4962c51a
MS		 1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
07d6d2b8 1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
4962c51a
MS		 1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1267 "R_ARM_LDC_SB_G2", /* name */
4962c51a
MS		 1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
07d6d2b8 1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
c19d1205
ZW		 1486
1487 /* GNU extension to record C++ vtable member usage */
07d6d2b8
AM		 1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
99059e56 1494 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8
AM		 1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
07d6d2b8
AM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
99059e56 1509 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8 1510 NULL, /* special_function */
99059e56 1511 "R_ARM_GNU_VTINHERIT", /* name */
07d6d2b8
AM		 1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
07d6d2b8
AM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
99059e56
RM		 1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
07d6d2b8 1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
07d6d2b8
AM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
99059e56
RM		 1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
07d6d2b8 1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
07d6d2b8
AM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
99059e56
RM		 1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
07d6d2b8 1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
07d6d2b8
AM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
99059e56
RM		 1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
07d6d2b8 1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
07d6d2b8
AM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
99059e56 1608 complain_overflow_bitfield,/* complain_on_overflow */
07d6d2b8 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
07d6d2b8 1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92
RS		 1748/* 160 onwards: */
1749static reloc_howto_type elf32_arm_howto_table_2[1] =
1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
07d6d2b8
AM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
99059e56
RM		 1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
1763 FALSE) /* pcrel_offset */
34e77a92 1764};
c19d1205 1765
34e77a92
RS		 1766/* 249-255 extended, currently unused, relocations: */
1767static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1768{
1769 HOWTO (R_ARM_RREL32, /* type */
1770 0, /* rightshift */
1771 0, /* size (0 = byte, 1 = short, 2 = long) */
1772 0, /* bitsize */
1773 FALSE, /* pc_relative */
1774 0, /* bitpos */
1775 complain_overflow_dont,/* complain_on_overflow */
1776 bfd_elf_generic_reloc, /* special_function */
1777 "R_ARM_RREL32", /* name */
1778 FALSE, /* partial_inplace */
1779 0, /* src_mask */
1780 0, /* dst_mask */
1781 FALSE), /* pcrel_offset */
1782
1783 HOWTO (R_ARM_RABS32, /* type */
1784 0, /* rightshift */
1785 0, /* size (0 = byte, 1 = short, 2 = long) */
1786 0, /* bitsize */
1787 FALSE, /* pc_relative */
1788 0, /* bitpos */
1789 complain_overflow_dont,/* complain_on_overflow */
1790 bfd_elf_generic_reloc, /* special_function */
1791 "R_ARM_RABS32", /* name */
1792 FALSE, /* partial_inplace */
1793 0, /* src_mask */
1794 0, /* dst_mask */
1795 FALSE), /* pcrel_offset */
1796
1797 HOWTO (R_ARM_RPC24, /* type */
1798 0, /* rightshift */
1799 0, /* size (0 = byte, 1 = short, 2 = long) */
1800 0, /* bitsize */
1801 FALSE, /* pc_relative */
1802 0, /* bitpos */
1803 complain_overflow_dont,/* complain_on_overflow */
1804 bfd_elf_generic_reloc, /* special_function */
1805 "R_ARM_RPC24", /* name */
1806 FALSE, /* partial_inplace */
1807 0, /* src_mask */
1808 0, /* dst_mask */
1809 FALSE), /* pcrel_offset */
1810
1811 HOWTO (R_ARM_RBASE, /* type */
1812 0, /* rightshift */
1813 0, /* size (0 = byte, 1 = short, 2 = long) */
1814 0, /* bitsize */
1815 FALSE, /* pc_relative */
1816 0, /* bitpos */
1817 complain_overflow_dont,/* complain_on_overflow */
1818 bfd_elf_generic_reloc, /* special_function */
1819 "R_ARM_RBASE", /* name */
1820 FALSE, /* partial_inplace */
1821 0, /* src_mask */
1822 0, /* dst_mask */
1823 FALSE) /* pcrel_offset */
1824};
1825
1826static reloc_howto_type *
1827elf32_arm_howto_from_type (unsigned int r_type)
1828{
906e58ca 1829 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1830 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1831
34e77a92
RS		 1832 if (r_type == R_ARM_IRELATIVE)
1833 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1834
c19d1205 1835 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1836 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1837 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1838
c19d1205 1839 return NULL;
7f266840
DJ		 1840}
1841
f3185997
NC		 1842static bfd_boolean
1843elf32_arm_info_to_howto (bfd * abfd, arelent * bfd_reloc,
7f266840
DJ		 1844 Elf_Internal_Rela * elf_reloc)
1845{
1846 unsigned int r_type;
1847
1848 r_type = ELF32_R_TYPE (elf_reloc->r_info);
f3185997
NC		 1849 if ((bfd_reloc->howto = elf32_arm_howto_from_type (r_type)) == NULL)
1850 {
1851 /* xgettext:c-format */
1852 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
1853 abfd, r_type);
1854 bfd_set_error (bfd_error_bad_value);
1855 return FALSE;
1856 }
1857 return TRUE;
7f266840
DJ		 1858}
1859
1860struct elf32_arm_reloc_map
1861 {
1862 bfd_reloc_code_real_type bfd_reloc_val;
07d6d2b8 1863 unsigned char elf_reloc_val;
7f266840
DJ		 1864 };
1865
1866/* All entries in this list must also be present in elf32_arm_howto_table. */
1867static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1868 {
07d6d2b8 1869 {BFD_RELOC_NONE, R_ARM_NONE},
7f266840 1870 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1871 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1872 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
07d6d2b8
AM		 1873 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1874 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1875 {BFD_RELOC_32, R_ARM_ABS32},
1876 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1877 {BFD_RELOC_8, R_ARM_ABS8},
1878 {BFD_RELOC_16, R_ARM_ABS16},
1879 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
7f266840 1880 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1881 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1882 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1883 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1884 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1885 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1886 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
07d6d2b8
AM		 1887 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1888 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1889 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
1890 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
1891 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
1892 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
1893 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1894 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
7f266840
DJ		 1895 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1896 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1897 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1898 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac 1899 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
07d6d2b8
AM		 1900 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1901 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1902 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
0855e32b 1903 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
07d6d2b8 1904 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
0855e32b 1905 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
07d6d2b8 1906 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1907 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1908 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1909 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1910 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1911 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
07d6d2b8
AM		 1912 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1913 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1914 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
1915 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
c19d1205
ZW		 1916 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1917 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1918 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1919 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1920 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1921 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1922 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1923 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1924 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1925 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1926 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1927 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1928 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1929 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1930 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1931 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1932 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1933 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1934 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1935 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1936 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1937 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1938 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1939 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1940 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1941 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1942 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
1943 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
1944 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
1945 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
1946 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
1947 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
1948 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
1949 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
1950 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
1951 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
1952 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 1953 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 1954 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
1955 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
1956 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
1957 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
1958 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 1959 };
1960
1961static reloc_howto_type *
f1c71a59
ZW		 1962elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1963 bfd_reloc_code_real_type code)
7f266840
DJ		 1964{
1965 unsigned int i;
8029a119 1966
906e58ca 1967 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 1968 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
1969 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 1970
c19d1205 1971 return NULL;
7f266840
DJ		 1972}
1973
157090f7
AM		 1974static reloc_howto_type *
1975elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1976 const char *r_name)
1977{
1978 unsigned int i;
1979
906e58ca 1980 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 1981 if (elf32_arm_howto_table_1[i].name != NULL
1982 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
1983 return &elf32_arm_howto_table_1[i];
1984
906e58ca 1985 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 1986 if (elf32_arm_howto_table_2[i].name != NULL
1987 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
1988 return &elf32_arm_howto_table_2[i];
1989
34e77a92
RS		 1990 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
1991 if (elf32_arm_howto_table_3[i].name != NULL
1992 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
1993 return &elf32_arm_howto_table_3[i];
1994
157090f7
AM		 1995 return NULL;
1996}
1997
906e58ca
NC		 1998/* Support for core dump NOTE sections. */
1999
7f266840 2000static bfd_boolean
f1c71a59 2001elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2002{
2003 int offset;
2004 size_t size;
2005
2006 switch (note->descsz)
2007 {
2008 default:
2009 return FALSE;
2010
8029a119 2011 case 148: /* Linux/ARM 32-bit. */
7f266840 2012 /* pr_cursig */
228e534f 2013 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2014
2015 /* pr_pid */
228e534f 2016 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2017
2018 /* pr_reg */
2019 offset = 72;
2020 size = 72;
2021
2022 break;
2023 }
2024
2025 /* Make a ".reg/999" section. */
2026 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2027 size, note->descpos + offset);
2028}
2029
2030static bfd_boolean
f1c71a59 2031elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2032{
2033 switch (note->descsz)
2034 {
2035 default:
2036 return FALSE;
2037
8029a119 2038 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2039 elf_tdata (abfd)->core->pid
4395ee08 2040 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2041 elf_tdata (abfd)->core->program
7f266840 2042 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2043 elf_tdata (abfd)->core->command
7f266840
DJ		 2044 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2045 }
2046
2047 /* Note that for some reason, a spurious space is tacked
2048 onto the end of the args in some (at least one anyway)
2049 implementations, so strip it off if it exists. */
7f266840 2050 {
228e534f 2051 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2052 int n = strlen (command);
2053
2054 if (0 < n && command[n - 1] == ' ')
2055 command[n - 1] = '\0';
2056 }
2057
2058 return TRUE;
2059}
2060
1f20dca5
UW		 2061static char *
2062elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2063 int note_type, ...)
2064{
2065 switch (note_type)
2066 {
2067 default:
2068 return NULL;
2069
2070 case NT_PRPSINFO:
2071 {
2072 char data[124];
2073 va_list ap;
2074
2075 va_start (ap, note_type);
2076 memset (data, 0, sizeof (data));
2077 strncpy (data + 28, va_arg (ap, const char *), 16);
2078 strncpy (data + 44, va_arg (ap, const char *), 80);
2079 va_end (ap);
2080
2081 return elfcore_write_note (abfd, buf, bufsiz,
2082 "CORE", note_type, data, sizeof (data));
2083 }
2084
2085 case NT_PRSTATUS:
2086 {
2087 char data[148];
2088 va_list ap;
2089 long pid;
2090 int cursig;
2091 const void *greg;
2092
2093 va_start (ap, note_type);
2094 memset (data, 0, sizeof (data));
2095 pid = va_arg (ap, long);
2096 bfd_put_32 (abfd, pid, data + 24);
2097 cursig = va_arg (ap, int);
2098 bfd_put_16 (abfd, cursig, data + 12);
2099 greg = va_arg (ap, const void *);
2100 memcpy (data + 72, greg, 72);
2101 va_end (ap);
2102
2103 return elfcore_write_note (abfd, buf, bufsiz,
2104 "CORE", note_type, data, sizeof (data));
2105 }
2106 }
2107}
2108
07d6d2b8
AM		 2109#define TARGET_LITTLE_SYM arm_elf32_le_vec
2110#define TARGET_LITTLE_NAME "elf32-littlearm"
2111#define TARGET_BIG_SYM arm_elf32_be_vec
2112#define TARGET_BIG_NAME "elf32-bigarm"
7f266840
DJ		 2113
2114#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2115#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2116#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2117
252b5132
RH		 2118typedef unsigned long int insn32;
2119typedef unsigned short int insn16;
2120
3a4a14e9
PB		 2121/* In lieu of proper flags, assume all EABIv4 or later objects are
2122 interworkable. */
57e8b36a 2123#define INTERWORK_FLAG(abfd) \
3a4a14e9 2124 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2125 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2126 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2127
252b5132
RH		 2128/* The linker script knows the section names for placement.
2129 The entry_names are used to do simple name mangling on the stubs.
2130 Given a function name, and its type, the stub can be found. The
9b485d32 2131 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2132#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2133#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2134
2135#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2136#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2137
c7b8f16e
JB		 2138#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2139#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2140
a504d23a
LA		 2141#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2142#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2143
845b51d6
PB		 2144#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2145#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2146
7413f23f
DJ		 2147#define STUB_ENTRY_NAME "__%s_veneer"
2148
4ba2ef8f
TP		 2149#define CMSE_PREFIX "__acle_se_"
2150
252b5132
RH		 2151/* The name of the dynamic interpreter. This is put in the .interp
2152 section. */
2153#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2154
0855e32b 2155static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2156{
2157 0xe08e0000, /* add r0, lr, r0 */
2158 0xe5901004, /* ldr r1, [r0,#4] */
2159 0xe12fff11, /* bx r1 */
2160};
0855e32b
NS		 2161
2162static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2163{
2164 0xe52d2004, /* push {r2} */
2165 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2166 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2167 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2168 0xe081100f, /* 2: add r1, pc */
2169 0xe12fff12, /* bx r2 */
2170 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2171 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2172 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2173};
0855e32b 2174
5e681ec4
PB		 2175#ifdef FOUR_WORD_PLT
2176
252b5132
RH		 2177/* The first entry in a procedure linkage table looks like
2178 this. It is set up so that any shared library function that is
59f2c4e7 2179 called before the relocation has been set up calls the dynamic
9b485d32 2180 linker first. */
e5a52504 2181static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2182{
2183 0xe52de004, /* str lr, [sp, #-4]! */
2184 0xe59fe010, /* ldr lr, [pc, #16] */
2185 0xe08fe00e, /* add lr, pc, lr */
2186 0xe5bef008, /* ldr pc, [lr, #8]! */
2187};
5e681ec4
PB		 2188
2189/* Subsequent entries in a procedure linkage table look like
2190 this. */
e5a52504 2191static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2192{
2193 0xe28fc600, /* add ip, pc, #NN */
2194 0xe28cca00, /* add ip, ip, #NN */
2195 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2196 0x00000000, /* unused */
2197};
5e681ec4 2198
eed94f8f 2199#else /* not FOUR_WORD_PLT */
5e681ec4 2200
5e681ec4
PB		 2201/* The first entry in a procedure linkage table looks like
2202 this. It is set up so that any shared library function that is
2203 called before the relocation has been set up calls the dynamic
2204 linker first. */
e5a52504 2205static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb 2206{
07d6d2b8
AM		 2207 0xe52de004, /* str lr, [sp, #-4]! */
2208 0xe59fe004, /* ldr lr, [pc, #4] */
2209 0xe08fe00e, /* add lr, pc, lr */
2210 0xe5bef008, /* ldr pc, [lr, #8]! */
2211 0x00000000, /* &GOT[0] - . */
b38cadfb 2212};
252b5132 2213
1db37fe6
YG		 2214/* By default subsequent entries in a procedure linkage table look like
2215 this. Offsets that don't fit into 28 bits will cause link error. */
2216static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2217{
2218 0xe28fc600, /* add ip, pc, #0xNN00000 */
2219 0xe28cca00, /* add ip, ip, #0xNN000 */
2220 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2221};
5e681ec4 2222
1db37fe6
YG		 2223/* When explicitly asked, we'll use this "long" entry format
2224 which can cope with arbitrary displacements. */
2225static const bfd_vma elf32_arm_plt_entry_long [] =
2226{
07d6d2b8
AM		 2227 0xe28fc200, /* add ip, pc, #0xN0000000 */
2228 0xe28cc600, /* add ip, ip, #0xNN00000 */
1db37fe6
YG		 2229 0xe28cca00, /* add ip, ip, #0xNN000 */
2230 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2231};
2232
2233static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2234
eed94f8f
NC		 2235#endif /* not FOUR_WORD_PLT */
2236
2237/* The first entry in a procedure linkage table looks like this.
2238 It is set up so that any shared library function that is called before the
2239 relocation has been set up calls the dynamic linker first. */
2240static const bfd_vma elf32_thumb2_plt0_entry [] =
2241{
2242 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2243 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2244 0xf8dfb500, /* push {lr} */
2245 0x44fee008, /* ldr.w lr, [pc, #8] */
2246 /* add lr, pc */
eed94f8f 2247 0xff08f85e, /* ldr.w pc, [lr, #8]! */
07d6d2b8 2248 0x00000000, /* &GOT[0] - . */
eed94f8f
NC		 2249};
2250
2251/* Subsequent entries in a procedure linkage table for thumb only target
2252 look like this. */
2253static const bfd_vma elf32_thumb2_plt_entry [] =
2254{
2255 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2256 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2257 0x0c00f240, /* movw ip, #0xNNNN */
2258 0x0c00f2c0, /* movt ip, #0xNNNN */
2259 0xf8dc44fc, /* add ip, pc */
2260 0xbf00f000 /* ldr.w pc, [ip] */
2261 /* nop */
eed94f8f 2262};
252b5132 2263
00a97672
RS		 2264/* The format of the first entry in the procedure linkage table
2265 for a VxWorks executable. */
2266static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb 2267{
07d6d2b8
AM		 2268 0xe52dc008, /* str ip,[sp,#-8]! */
2269 0xe59fc000, /* ldr ip,[pc] */
2270 0xe59cf008, /* ldr pc,[ip,#8] */
2271 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
b38cadfb 2272};
00a97672
RS		 2273
2274/* The format of subsequent entries in a VxWorks executable. */
2275static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb 2276{
07d6d2b8
AM		 2277 0xe59fc000, /* ldr ip,[pc] */
2278 0xe59cf000, /* ldr pc,[ip] */
2279 0x00000000, /* .long @got */
2280 0xe59fc000, /* ldr ip,[pc] */
2281 0xea000000, /* b _PLT */
2282 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2283};
00a97672
RS		 2284
2285/* The format of entries in a VxWorks shared library. */
2286static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb 2287{
07d6d2b8
AM		 2288 0xe59fc000, /* ldr ip,[pc] */
2289 0xe79cf009, /* ldr pc,[ip,r9] */
2290 0x00000000, /* .long @got */
2291 0xe59fc000, /* ldr ip,[pc] */
2292 0xe599f008, /* ldr pc,[r9,#8] */
2293 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2294};
00a97672 2295
b7693d02
DJ		 2296/* An initial stub used if the PLT entry is referenced from Thumb code. */
2297#define PLT_THUMB_STUB_SIZE 4
2298static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2299{
2300 0x4778, /* bx pc */
2301 0x46c0 /* nop */
2302};
b7693d02 2303
e5a52504
MM		 2304/* The entries in a PLT when using a DLL-based target with multiple
2305 address spaces. */
906e58ca 2306static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb 2307{
07d6d2b8
AM		 2308 0xe51ff004, /* ldr pc, [pc, #-4] */
2309 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
b38cadfb
NC		 2310};
2311
2312/* The first entry in a procedure linkage table looks like
2313 this. It is set up so that any shared library function that is
2314 called before the relocation has been set up calls the dynamic
2315 linker first. */
2316static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2317{
2318 /* First bundle: */
2319 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2320 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2321 0xe08cc00f, /* add ip, ip, pc */
2322 0xe52dc008, /* str ip, [sp, #-8]! */
2323 /* Second bundle: */
edccdf7c
RM		 2324 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2325 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2326 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2327 0xe12fff1c, /* bx ip */
b38cadfb 2328 /* Third bundle: */
edccdf7c
RM		 2329 0xe320f000, /* nop */
2330 0xe320f000, /* nop */
2331 0xe320f000, /* nop */
b38cadfb
NC		 2332 /* .Lplt_tail: */
2333 0xe50dc004, /* str ip, [sp, #-4] */
2334 /* Fourth bundle: */
edccdf7c
RM		 2335 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2336 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2337 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2338 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2339};
2340#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2341
2342/* Subsequent entries in a procedure linkage table look like this. */
2343static const bfd_vma elf32_arm_nacl_plt_entry [] =
2344{
2345 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2346 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2347 0xe08cc00f, /* add ip, ip, pc */
2348 0xea000000, /* b .Lplt_tail */
2349};
e5a52504 2350
906e58ca
NC		 2351#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2352#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2353#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2354#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2355#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2356#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2357#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2358#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2359
461a49ca 2360enum stub_insn_type
b38cadfb
NC		 2361{
2362 THUMB16_TYPE = 1,
2363 THUMB32_TYPE,
2364 ARM_TYPE,
2365 DATA_TYPE
2366};
461a49ca 2367
48229727
JB		 2368#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2369/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2370 is inserted in arm_build_one_stub(). */
2371#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2372#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2373#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2374#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2375#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2376#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2377#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2378#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2379
2380typedef struct
2381{
07d6d2b8 2382 bfd_vma data;
b38cadfb 2383 enum stub_insn_type type;
07d6d2b8
AM		 2384 unsigned int r_type;
2385 int reloc_addend;
461a49ca
DJ		 2386} insn_sequence;
2387
fea2b4d6
CL		 2388/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2389 to reach the stub if necessary. */
461a49ca 2390static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb 2391{
07d6d2b8 2392 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2393 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2394};
906e58ca 2395
fea2b4d6
CL		 2396/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2397 available. */
461a49ca 2398static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb 2399{
07d6d2b8
AM		 2400 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2401 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2402 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2403};
906e58ca 2404
d3626fb0 2405/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2406static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb 2407{
07d6d2b8
AM		 2408 THUMB16_INSN (0xb401), /* push {r0} */
2409 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2410 THUMB16_INSN (0x4684), /* mov ip, r0 */
2411 THUMB16_INSN (0xbc01), /* pop {r0} */
2412 THUMB16_INSN (0x4760), /* bx ip */
2413 THUMB16_INSN (0xbf00), /* nop */
b38cadfb
NC		 2414 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2415};
906e58ca 2416
80c135e5
TP		 2417/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2418static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2419{
07d6d2b8 2420 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
80c135e5
TP		 2421 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2422};
2423
d5a67c02
AV		 2424/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2425 M-profile architectures. */
2426static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2427{
2428 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2429 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
07d6d2b8 2430 THUMB16_INSN (0x4760), /* bx ip */
d5a67c02
AV		 2431};
2432
d3626fb0
CL		 2433/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2434 allowed. */
2435static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb 2436{
07d6d2b8
AM		 2437 THUMB16_INSN (0x4778), /* bx pc */
2438 THUMB16_INSN (0x46c0), /* nop */
2439 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2440 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2441 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2442};
d3626fb0 2443
fea2b4d6
CL		 2444/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2445 available. */
461a49ca 2446static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb 2447{
07d6d2b8
AM		 2448 THUMB16_INSN (0x4778), /* bx pc */
2449 THUMB16_INSN (0x46c0), /* nop */
2450 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2451 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2452};
906e58ca 2453
fea2b4d6
CL		 2454/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2455 one, when the destination is close enough. */
461a49ca 2456static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb 2457{
07d6d2b8
AM		 2458 THUMB16_INSN (0x4778), /* bx pc */
2459 THUMB16_INSN (0x46c0), /* nop */
b38cadfb
NC		 2460 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2461};
c820be07 2462
cf3eccff 2463/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2464 blx to reach the stub if necessary. */
cf3eccff 2465static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb 2466{
07d6d2b8
AM		 2467 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2468 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
b38cadfb
NC		 2469 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2470};
906e58ca 2471
cf3eccff
DJ		 2472/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2473 blx to reach the stub if necessary. We can not add into pc;
2474 it is not guaranteed to mode switch (different in ARMv6 and
2475 ARMv7). */
2476static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb 2477{
07d6d2b8
AM		 2478 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2479 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2480 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2481 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2482};
cf3eccff 2483
ebe24dd4
CL		 2484/* V4T ARM -> ARM long branch stub, PIC. */
2485static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb 2486{
07d6d2b8
AM		 2487 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2488 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2489 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2490 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2491};
ebe24dd4
CL		 2492
2493/* V4T Thumb -> ARM long branch stub, PIC. */
2494static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb 2495{
07d6d2b8
AM		 2496 THUMB16_INSN (0x4778), /* bx pc */
2497 THUMB16_INSN (0x46c0), /* nop */
2498 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2499 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
b38cadfb
NC		 2500 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2501};
ebe24dd4 2502
d3626fb0
CL		 2503/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2504 architectures. */
ebe24dd4 2505static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb 2506{
07d6d2b8
AM		 2507 THUMB16_INSN (0xb401), /* push {r0} */
2508 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2509 THUMB16_INSN (0x46fc), /* mov ip, pc */
2510 THUMB16_INSN (0x4484), /* add ip, r0 */
2511 THUMB16_INSN (0xbc01), /* pop {r0} */
2512 THUMB16_INSN (0x4760), /* bx ip */
b38cadfb
NC		 2513 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2514};
ebe24dd4 2515
d3626fb0
CL		 2516/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2517 allowed. */
2518static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb 2519{
07d6d2b8
AM		 2520 THUMB16_INSN (0x4778), /* bx pc */
2521 THUMB16_INSN (0x46c0), /* nop */
2522 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2523 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2524 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2525 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2526};
d3626fb0 2527
0855e32b
NS		 2528/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2529 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2530static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2531{
07d6d2b8
AM		 2532 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2533 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
b38cadfb 2534 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2535};
2536
2537/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2538 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2539static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2540{
07d6d2b8
AM		 2541 THUMB16_INSN (0x4778), /* bx pc */
2542 THUMB16_INSN (0x46c0), /* nop */
2543 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2544 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
b38cadfb 2545 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2546};
2547
7a89b94e
NC		 2548/* NaCl ARM -> ARM long branch stub. */
2549static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2550{
2551 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2552 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2553 ARM_INSN (0xe12fff1c), /* bx ip */
2554 ARM_INSN (0xe320f000), /* nop */
2555 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2556 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2557 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2558 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2559};
2560
2561/* NaCl ARM -> ARM long branch stub, PIC. */
2562static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2563{
2564 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
07d6d2b8 2565 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
7a89b94e 2566 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2567 ARM_INSN (0xe12fff1c), /* bx ip */
2568 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2569 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2570 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2571 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2572};
2573
4ba2ef8f
TP		 2574/* Stub used for transition to secure state (aka SG veneer). */
2575static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2576{
2577 THUMB32_INSN (0xe97fe97f), /* sg. */
2578 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2579};
2580
7a89b94e 2581
48229727
JB		 2582/* Cortex-A8 erratum-workaround stubs. */
2583
2584/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2585 can't use a conditional branch to reach this stub). */
2586
2587static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb 2588{
07d6d2b8 2589 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
b38cadfb
NC		 2590 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2591 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2592};
48229727
JB		 2593
2594/* Stub used for b.w and bl.w instructions. */
2595
2596static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2597{
2598 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2599};
48229727
JB		 2600
2601static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2602{
2603 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2604};
48229727
JB		 2605
2606/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2607 instruction (which switches to ARM mode) to point to this stub. Jump to the
2608 real destination using an ARM-mode branch. */
2609
2610static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2611{
2612 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2613};
48229727 2614
9553db3c
NC		 2615/* For each section group there can be a specially created linker section
2616 to hold the stubs for that group. The name of the stub section is based
2617 upon the name of another section within that group with the suffix below
2618 applied.
2619
2620 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2621 create what appeared to be a linker stub section when it actually
2622 contained user code/data. For example, consider this fragment:
b38cadfb 2623
9553db3c
NC		 2624 const char * stubborn_problems[] = { "np" };
2625
2626 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2627 section called:
2628
2629 .data.rel.local.stubborn_problems
2630
2631 This then causes problems in arm32_arm_build_stubs() as it triggers:
2632
2633 // Ignore non-stub sections.
2634 if (!strstr (stub_sec->name, STUB_SUFFIX))
2635 continue;
2636
2637 And so the section would be ignored instead of being processed. Hence
2638 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2639 C identifier. */
2640#define STUB_SUFFIX ".__stub"
906e58ca 2641
738a79f6
CL		 2642/* One entry per long/short branch stub defined above. */
2643#define DEF_STUBS \
2644 DEF_STUB(long_branch_any_any) \
2645 DEF_STUB(long_branch_v4t_arm_thumb) \
2646 DEF_STUB(long_branch_thumb_only) \
2647 DEF_STUB(long_branch_v4t_thumb_thumb) \
2648 DEF_STUB(long_branch_v4t_thumb_arm) \
2649 DEF_STUB(short_branch_v4t_thumb_arm) \
2650 DEF_STUB(long_branch_any_arm_pic) \
2651 DEF_STUB(long_branch_any_thumb_pic) \
2652 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2653 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2654 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2655 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2656 DEF_STUB(long_branch_any_tls_pic) \
2657 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2658 DEF_STUB(long_branch_arm_nacl) \
2659 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2660 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2661 DEF_STUB(a8_veneer_b_cond) \
2662 DEF_STUB(a8_veneer_b) \
2663 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2664 DEF_STUB(a8_veneer_blx) \
2665 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2666 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2667
2668#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2669enum elf32_arm_stub_type
2670{
906e58ca 2671 arm_stub_none,
738a79f6 2672 DEF_STUBS
4f4faa4d 2673 max_stub_type
738a79f6
CL		 2674};
2675#undef DEF_STUB
2676
8d9d9490
TP		 2677/* Note the first a8_veneer type. */
2678const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2679
738a79f6
CL		 2680typedef struct
2681{
d3ce72d0 2682 const insn_sequence* template_sequence;
738a79f6
CL		 2683 int template_size;
2684} stub_def;
2685
2686#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2687static const stub_def stub_definitions[] =
2688{
738a79f6
CL		 2689 {NULL, 0},
2690 DEF_STUBS
906e58ca
NC		 2691};
2692
2693struct elf32_arm_stub_hash_entry
2694{
2695 /* Base hash table entry structure. */
2696 struct bfd_hash_entry root;
2697
2698 /* The stub section. */
2699 asection *stub_sec;
2700
2701 /* Offset within stub_sec of the beginning of this stub. */
2702 bfd_vma stub_offset;
2703
2704 /* Given the symbol's value and its section we can determine its final
2705 value when building the stubs (so the stub knows where to jump). */
2706 bfd_vma target_value;
2707 asection *target_section;
2708
8d9d9490
TP		 2709 /* Same as above but for the source of the branch to the stub. Used for
2710 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2711 such, source section does not need to be recorded since Cortex-A8 erratum
2712 workaround stubs are only generated when both source and target are in the
2713 same section. */
2714 bfd_vma source_value;
48229727
JB		 2715
2716 /* The instruction which caused this stub to be generated (only valid for
2717 Cortex-A8 erratum workaround stubs at present). */
2718 unsigned long orig_insn;
2719
461a49ca 2720 /* The stub type. */
906e58ca 2721 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2722 /* Its encoding size in bytes. */
2723 int stub_size;
2724 /* Its template. */
2725 const insn_sequence *stub_template;
2726 /* The size of the template (number of entries). */
2727 int stub_template_size;
906e58ca
NC		 2728
2729 /* The symbol table entry, if any, that this was derived from. */
2730 struct elf32_arm_link_hash_entry *h;
2731
35fc36a8
RS		 2732 /* Type of branch. */
2733 enum arm_st_branch_type branch_type;
906e58ca
NC		 2734
2735 /* Where this stub is being called from, or, in the case of combined
2736 stub sections, the first input section in the group. */
2737 asection *id_sec;
7413f23f
DJ		 2738
2739 /* The name for the local symbol at the start of this stub. The
2740 stub name in the hash table has to be unique; this does not, so
2741 it can be friendlier. */
2742 char *output_name;
906e58ca
NC		 2743};
2744
e489d0ae
PB		 2745/* Used to build a map of a section. This is required for mixed-endian
2746 code/data. */
2747
2748typedef struct elf32_elf_section_map
2749{
2750 bfd_vma vma;
2751 char type;
2752}
2753elf32_arm_section_map;
2754
c7b8f16e
JB		 2755/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2756
2757typedef enum
2758{
2759 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2760 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2761 VFP11_ERRATUM_ARM_VENEER,
2762 VFP11_ERRATUM_THUMB_VENEER
2763}
2764elf32_vfp11_erratum_type;
2765
2766typedef struct elf32_vfp11_erratum_list
2767{
2768 struct elf32_vfp11_erratum_list *next;
2769 bfd_vma vma;
2770 union
2771 {
2772 struct
2773 {
2774 struct elf32_vfp11_erratum_list *veneer;
2775 unsigned int vfp_insn;
2776 } b;
2777 struct
2778 {
2779 struct elf32_vfp11_erratum_list *branch;
2780 unsigned int id;
2781 } v;
2782 } u;
2783 elf32_vfp11_erratum_type type;
2784}
2785elf32_vfp11_erratum_list;
2786
a504d23a
LA		 2787/* Information about a STM32L4XX erratum veneer, or a branch to such a
2788 veneer. */
2789typedef enum
2790{
2791 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2792 STM32L4XX_ERRATUM_VENEER
2793}
2794elf32_stm32l4xx_erratum_type;
2795
2796typedef struct elf32_stm32l4xx_erratum_list
2797{
2798 struct elf32_stm32l4xx_erratum_list *next;
2799 bfd_vma vma;
2800 union
2801 {
2802 struct
2803 {
2804 struct elf32_stm32l4xx_erratum_list *veneer;
2805 unsigned int insn;
2806 } b;
2807 struct
2808 {
2809 struct elf32_stm32l4xx_erratum_list *branch;
2810 unsigned int id;
2811 } v;
2812 } u;
2813 elf32_stm32l4xx_erratum_type type;
2814}
2815elf32_stm32l4xx_erratum_list;
2816
2468f9c9
PB		 2817typedef enum
2818{
2819 DELETE_EXIDX_ENTRY,
2820 INSERT_EXIDX_CANTUNWIND_AT_END
2821}
2822arm_unwind_edit_type;
2823
2824/* A (sorted) list of edits to apply to an unwind table. */
2825typedef struct arm_unwind_table_edit
2826{
2827 arm_unwind_edit_type type;
2828 /* Note: we sometimes want to insert an unwind entry corresponding to a
2829 section different from the one we're currently writing out, so record the
2830 (text) section this edit relates to here. */
2831 asection *linked_section;
2832 unsigned int index;
2833 struct arm_unwind_table_edit *next;
2834}
2835arm_unwind_table_edit;
2836
8e3de13a 2837typedef struct _arm_elf_section_data
e489d0ae 2838{
2468f9c9 2839 /* Information about mapping symbols. */
e489d0ae 2840 struct bfd_elf_section_data elf;
8e3de13a 2841 unsigned int mapcount;
c7b8f16e 2842 unsigned int mapsize;
e489d0ae 2843 elf32_arm_section_map *map;
2468f9c9 2844 /* Information about CPU errata. */
c7b8f16e
JB		 2845 unsigned int erratumcount;
2846 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2847 unsigned int stm32l4xx_erratumcount;
2848 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2849 unsigned int additional_reloc_count;
2468f9c9
PB		 2850 /* Information about unwind tables. */
2851 union
2852 {
2853 /* Unwind info attached to a text section. */
2854 struct
2855 {
2856 asection *arm_exidx_sec;
2857 } text;
2858
2859 /* Unwind info attached to an .ARM.exidx section. */
2860 struct
2861 {
2862 arm_unwind_table_edit *unwind_edit_list;
2863 arm_unwind_table_edit *unwind_edit_tail;
2864 } exidx;
2865 } u;
8e3de13a
NC		 2866}
2867_arm_elf_section_data;
e489d0ae
PB		 2868
2869#define elf32_arm_section_data(sec) \
8e3de13a 2870 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2871
48229727
JB		 2872/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2873 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2874 so may be created multiple times: we use an array of these entries whilst
2875 relaxing which we can refresh easily, then create stubs for each potentially
2876 erratum-triggering instruction once we've settled on a solution. */
2877
b38cadfb
NC		 2878struct a8_erratum_fix
2879{
48229727
JB		 2880 bfd *input_bfd;
2881 asection *section;
2882 bfd_vma offset;
8d9d9490 2883 bfd_vma target_offset;
48229727
JB		 2884 unsigned long orig_insn;
2885 char *stub_name;
2886 enum elf32_arm_stub_type stub_type;
35fc36a8 2887 enum arm_st_branch_type branch_type;
48229727
JB		 2888};
2889
2890/* A table of relocs applied to branches which might trigger Cortex-A8
2891 erratum. */
2892
b38cadfb
NC		 2893struct a8_erratum_reloc
2894{
48229727
JB		 2895 bfd_vma from;
2896 bfd_vma destination;
92750f34
DJ		 2897 struct elf32_arm_link_hash_entry *hash;
2898 const char *sym_name;
48229727 2899 unsigned int r_type;
35fc36a8 2900 enum arm_st_branch_type branch_type;
48229727
JB		 2901 bfd_boolean non_a8_stub;
2902};
2903
ba93b8ac
DJ		 2904/* The size of the thread control block. */
2905#define TCB_SIZE 8
2906
34e77a92
RS		 2907/* ARM-specific information about a PLT entry, over and above the usual
2908 gotplt_union. */
b38cadfb
NC		 2909struct arm_plt_info
2910{
34e77a92
RS		 2911 /* We reference count Thumb references to a PLT entry separately,
2912 so that we can emit the Thumb trampoline only if needed. */
2913 bfd_signed_vma thumb_refcount;
2914
2915 /* Some references from Thumb code may be eliminated by BL->BLX
2916 conversion, so record them separately. */
2917 bfd_signed_vma maybe_thumb_refcount;
2918
2919 /* How many of the recorded PLT accesses were from non-call relocations.
2920 This information is useful when deciding whether anything takes the
2921 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2922 non-call references to the function should resolve directly to the
2923 real runtime target. */
2924 unsigned int noncall_refcount;
2925
2926 /* Since PLT entries have variable size if the Thumb prologue is
2927 used, we need to record the index into .got.plt instead of
2928 recomputing it from the PLT offset. */
2929 bfd_signed_vma got_offset;
2930};
2931
2932/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2933struct arm_local_iplt_info
2934{
34e77a92
RS		 2935 /* The information that is usually found in the generic ELF part of
2936 the hash table entry. */
2937 union gotplt_union root;
2938
2939 /* The information that is usually found in the ARM-specific part of
2940 the hash table entry. */
2941 struct arm_plt_info arm;
2942
2943 /* A list of all potential dynamic relocations against this symbol. */
2944 struct elf_dyn_relocs *dyn_relocs;
2945};
2946
0ffa91dd 2947struct elf_arm_obj_tdata
ba93b8ac
DJ		 2948{
2949 struct elf_obj_tdata root;
2950
2951 /* tls_type for each local got entry. */
2952 char *local_got_tls_type;
ee065d83 2953
0855e32b
NS		 2954 /* GOTPLT entries for TLS descriptors. */
2955 bfd_vma *local_tlsdesc_gotent;
2956
34e77a92
RS		 2957 /* Information for local symbols that need entries in .iplt. */
2958 struct arm_local_iplt_info **local_iplt;
2959
bf21ed78
MS		 2960 /* Zero to warn when linking objects with incompatible enum sizes. */
2961 int no_enum_size_warning;
a9dc9481
JM		 2962
2963 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2964 int no_wchar_size_warning;
ba93b8ac
DJ		 2965};
2966
0ffa91dd
NC		 2967#define elf_arm_tdata(bfd) \
2968 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 2969
0ffa91dd
NC		 2970#define elf32_arm_local_got_tls_type(bfd) \
2971 (elf_arm_tdata (bfd)->local_got_tls_type)
2972
0855e32b
NS		 2973#define elf32_arm_local_tlsdesc_gotent(bfd) \
2974 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2975
34e77a92
RS		 2976#define elf32_arm_local_iplt(bfd) \
2977 (elf_arm_tdata (bfd)->local_iplt)
2978
0ffa91dd
NC		 2979#define is_arm_elf(bfd) \
2980 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2981 && elf_tdata (bfd) != NULL \
4dfe6ac6 2982 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 2983
2984static bfd_boolean
2985elf32_arm_mkobject (bfd *abfd)
2986{
0ffa91dd 2987 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 2988 ARM_ELF_DATA);
ba93b8ac
DJ		 2989}
2990
ba93b8ac
DJ		 2991#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2992
ba96a88f 2993/* Arm ELF linker hash entry. */
252b5132 2994struct elf32_arm_link_hash_entry
b38cadfb
NC		 2995{
2996 struct elf_link_hash_entry root;
252b5132 2997
b38cadfb
NC		 2998 /* Track dynamic relocs copied for this symbol. */
2999 struct elf_dyn_relocs *dyn_relocs;
b7693d02 3000
b38cadfb
NC		 3001 /* ARM-specific PLT information. */
3002 struct arm_plt_info plt;
ba93b8ac
DJ		 3003
3004#define GOT_UNKNOWN 0
3005#define GOT_NORMAL 1
3006#define GOT_TLS_GD 2
3007#define GOT_TLS_IE 4
0855e32b
NS		 3008#define GOT_TLS_GDESC 8
3009#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3010 unsigned int tls_type : 8;
34e77a92 3011
b38cadfb
NC		 3012 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3013 unsigned int is_iplt : 1;
34e77a92 3014
b38cadfb 3015 unsigned int unused : 23;
a4fd1a8e 3016
b38cadfb
NC		 3017 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3018 starting at the end of the jump table. */
3019 bfd_vma tlsdesc_got;
0855e32b 3020
b38cadfb
NC		 3021 /* The symbol marking the real symbol location for exported thumb
3022 symbols with Arm stubs. */
3023 struct elf_link_hash_entry *export_glue;
906e58ca 3024
b38cadfb 3025 /* A pointer to the most recently used stub hash entry against this
8029a119 3026 symbol. */
b38cadfb
NC		 3027 struct elf32_arm_stub_hash_entry *stub_cache;
3028};
252b5132 3029
252b5132 3030/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3031#define elf32_arm_link_hash_traverse(table, func, info) \
3032 (elf_link_hash_traverse \
3033 (&(table)->root, \
b7693d02 3034 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3035 (info)))
3036
3037/* Get the ARM elf linker hash table from a link_info structure. */
3038#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3039 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3040 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3041
906e58ca
NC		 3042#define arm_stub_hash_lookup(table, string, create, copy) \
3043 ((struct elf32_arm_stub_hash_entry *) \
3044 bfd_hash_lookup ((table), (string), (create), (copy)))
3045
21d799b5
NC		 3046/* Array to keep track of which stub sections have been created, and
3047 information on stub grouping. */
3048struct map_stub
3049{
3050 /* This is the section to which stubs in the group will be
3051 attached. */
3052 asection *link_sec;
3053 /* The stub section. */
3054 asection *stub_sec;
3055};
3056
0855e32b
NS		 3057#define elf32_arm_compute_jump_table_size(htab) \
3058 ((htab)->next_tls_desc_index * 4)
3059
9b485d32 3060/* ARM ELF linker hash table. */
252b5132 3061struct elf32_arm_link_hash_table
906e58ca
NC		 3062{
3063 /* The main hash table. */
3064 struct elf_link_hash_table root;
252b5132 3065
906e58ca
NC		 3066 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3067 bfd_size_type thumb_glue_size;
252b5132 3068
906e58ca
NC		 3069 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3070 bfd_size_type arm_glue_size;
252b5132 3071
906e58ca
NC		 3072 /* The size in bytes of section containing the ARMv4 BX veneers. */
3073 bfd_size_type bx_glue_size;
845b51d6 3074
906e58ca
NC		 3075 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3076 veneer has been populated. */
3077 bfd_vma bx_glue_offset[15];
845b51d6 3078
906e58ca
NC		 3079 /* The size in bytes of the section containing glue for VFP11 erratum
3080 veneers. */
3081 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3082
a504d23a
LA		 3083 /* The size in bytes of the section containing glue for STM32L4XX erratum
3084 veneers. */
3085 bfd_size_type stm32l4xx_erratum_glue_size;
3086
48229727
JB		 3087 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3088 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3089 elf32_arm_write_section(). */
3090 struct a8_erratum_fix *a8_erratum_fixes;
3091 unsigned int num_a8_erratum_fixes;
3092
906e58ca
NC		 3093 /* An arbitrary input BFD chosen to hold the glue sections. */
3094 bfd * bfd_of_glue_owner;
ba96a88f 3095
906e58ca
NC		 3096 /* Nonzero to output a BE8 image. */
3097 int byteswap_code;
e489d0ae 3098
906e58ca
NC		 3099 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3100 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3101 int target1_is_rel;
9c504268 3102
906e58ca
NC		 3103 /* The relocation to use for R_ARM_TARGET2 relocations. */
3104 int target2_reloc;
eb043451 3105
906e58ca
NC		 3106 /* 0 = Ignore R_ARM_V4BX.
3107 1 = Convert BX to MOV PC.
3108 2 = Generate v4 interworing stubs. */
3109 int fix_v4bx;
319850b4 3110
48229727
JB		 3111 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3112 int fix_cortex_a8;
3113
2de70689
MGD		 3114 /* Whether we should fix the ARM1176 BLX immediate issue. */
3115 int fix_arm1176;
3116
906e58ca
NC		 3117 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3118 int use_blx;
33bfe774 3119
906e58ca
NC		 3120 /* What sort of code sequences we should look for which may trigger the
3121 VFP11 denorm erratum. */
3122 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3123
906e58ca
NC		 3124 /* Global counter for the number of fixes we have emitted. */
3125 int num_vfp11_fixes;
c7b8f16e 3126
a504d23a
LA		 3127 /* What sort of code sequences we should look for which may trigger the
3128 STM32L4XX erratum. */
3129 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3130
3131 /* Global counter for the number of fixes we have emitted. */
3132 int num_stm32l4xx_fixes;
3133
906e58ca
NC		 3134 /* Nonzero to force PIC branch veneers. */
3135 int pic_veneer;
27e55c4d 3136
906e58ca
NC		 3137 /* The number of bytes in the initial entry in the PLT. */
3138 bfd_size_type plt_header_size;
e5a52504 3139
906e58ca
NC		 3140 /* The number of bytes in the subsequent PLT etries. */
3141 bfd_size_type plt_entry_size;
e5a52504 3142
906e58ca
NC		 3143 /* True if the target system is VxWorks. */
3144 int vxworks_p;
00a97672 3145
906e58ca
NC		 3146 /* True if the target system is Symbian OS. */
3147 int symbian_p;
e5a52504 3148
b38cadfb
NC		 3149 /* True if the target system is Native Client. */
3150 int nacl_p;
3151
906e58ca 3152 /* True if the target uses REL relocations. */
f3185997 3153 bfd_boolean use_rel;
4e7fd91e 3154
54ddd295
TP		 3155 /* Nonzero if import library must be a secure gateway import library
3156 as per ARMv8-M Security Extensions. */
3157 int cmse_implib;
3158
0955507f
TP		 3159 /* The import library whose symbols' address must remain stable in
3160 the import library generated. */
3161 bfd *in_implib_bfd;
3162
0855e32b
NS		 3163 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3164 bfd_vma next_tls_desc_index;
3165
3166 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3167 bfd_vma num_tls_desc;
3168
906e58ca
NC		 3169 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3170 asection *srelplt2;
00a97672 3171
0855e32b
NS		 3172 /* The offset into splt of the PLT entry for the TLS descriptor
3173 resolver. Special values are 0, if not necessary (or not found
3174 to be necessary yet), and -1 if needed but not determined
3175 yet. */
3176 bfd_vma dt_tlsdesc_plt;
3177
3178 /* The offset into sgot of the GOT entry used by the PLT entry
3179 above. */
b38cadfb 3180 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3181
3182 /* Offset in .plt section of tls_arm_trampoline. */
3183 bfd_vma tls_trampoline;
3184
906e58ca
NC		 3185 /* Data for R_ARM_TLS_LDM32 relocations. */
3186 union
3187 {
3188 bfd_signed_vma refcount;
3189 bfd_vma offset;
3190 } tls_ldm_got;
b7693d02 3191
87d72d41
AM		 3192 /* Small local sym cache. */
3193 struct sym_cache sym_cache;
906e58ca
NC		 3194
3195 /* For convenience in allocate_dynrelocs. */
3196 bfd * obfd;
3197
0855e32b
NS		 3198 /* The amount of space used by the reserved portion of the sgotplt
3199 section, plus whatever space is used by the jump slots. */
3200 bfd_vma sgotplt_jump_table_size;
3201
906e58ca
NC		 3202 /* The stub hash table. */
3203 struct bfd_hash_table stub_hash_table;
3204
3205 /* Linker stub bfd. */
3206 bfd *stub_bfd;
3207
3208 /* Linker call-backs. */
6bde4c52
TP		 3209 asection * (*add_stub_section) (const char *, asection *, asection *,
3210 unsigned int);
906e58ca
NC		 3211 void (*layout_sections_again) (void);
3212
3213 /* Array to keep track of which stub sections have been created, and
3214 information on stub grouping. */
21d799b5 3215 struct map_stub *stub_group;
906e58ca 3216
4ba2ef8f
TP		 3217 /* Input stub section holding secure gateway veneers. */
3218 asection *cmse_stub_sec;
3219
0955507f
TP		 3220 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3221 start to be allocated. */
3222 bfd_vma new_cmse_stub_offset;
3223
fe33d2fa 3224 /* Number of elements in stub_group. */
7292b3ac 3225 unsigned int top_id;
fe33d2fa 3226
906e58ca
NC		 3227 /* Assorted information used by elf32_arm_size_stubs. */
3228 unsigned int bfd_count;
7292b3ac 3229 unsigned int top_index;
906e58ca 3230 asection **input_list;
617a5ada
CL		 3231
3232 /* True if the target system uses FDPIC. */
3233 int fdpic_p;
906e58ca 3234};
252b5132 3235
a504d23a
LA		 3236static inline int
3237ctz (unsigned int mask)
3238{
3239#if GCC_VERSION >= 3004
3240 return __builtin_ctz (mask);
3241#else
3242 unsigned int i;
3243
3244 for (i = 0; i < 8 * sizeof (mask); i++)
3245 {
3246 if (mask & 0x1)
3247 break;
3248 mask = (mask >> 1);
3249 }
3250 return i;
3251#endif
3252}
3253
3254static inline int
b25e998d 3255elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3256{
3257#if GCC_VERSION >= 3004
3258 return __builtin_popcount (mask);
3259#else
b25e998d
CG		 3260 unsigned int i;
3261 int sum = 0;
a504d23a
LA		 3262
3263 for (i = 0; i < 8 * sizeof (mask); i++)
3264 {
3265 if (mask & 0x1)
3266 sum++;
3267 mask = (mask >> 1);
3268 }
3269 return sum;
3270#endif
3271}
3272
780a67af
NC		 3273/* Create an entry in an ARM ELF linker hash table. */
3274
3275static struct bfd_hash_entry *
57e8b36a 3276elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3277 struct bfd_hash_table * table,
3278 const char * string)
780a67af
NC		 3279{
3280 struct elf32_arm_link_hash_entry * ret =
3281 (struct elf32_arm_link_hash_entry *) entry;
3282
3283 /* Allocate the structure if it has not already been allocated by a
3284 subclass. */
906e58ca 3285 if (ret == NULL)
21d799b5 3286 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3287 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3288 if (ret == NULL)
780a67af
NC		 3289 return (struct bfd_hash_entry *) ret;
3290
3291 /* Call the allocation method of the superclass. */
3292 ret = ((struct elf32_arm_link_hash_entry *)
3293 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3294 table, string));
57e8b36a 3295 if (ret != NULL)
b7693d02 3296 {
0bdcacaf 3297 ret->dyn_relocs = NULL;
ba93b8ac 3298 ret->tls_type = GOT_UNKNOWN;
0855e32b 3299 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3300 ret->plt.thumb_refcount = 0;
3301 ret->plt.maybe_thumb_refcount = 0;
3302 ret->plt.noncall_refcount = 0;
3303 ret->plt.got_offset = -1;
3304 ret->is_iplt = FALSE;
a4fd1a8e 3305 ret->export_glue = NULL;
906e58ca
NC		 3306
3307 ret->stub_cache = NULL;
b7693d02 3308 }
780a67af
NC		 3309
3310 return (struct bfd_hash_entry *) ret;
3311}
3312
34e77a92
RS		 3313/* Ensure that we have allocated bookkeeping structures for ABFD's local
3314 symbols. */
3315
3316static bfd_boolean
3317elf32_arm_allocate_local_sym_info (bfd *abfd)
3318{
3319 if (elf_local_got_refcounts (abfd) == NULL)
3320 {
3321 bfd_size_type num_syms;
3322 bfd_size_type size;
3323 char *data;
3324
3325 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3326 size = num_syms * (sizeof (bfd_signed_vma)
3327 + sizeof (struct arm_local_iplt_info *)
3328 + sizeof (bfd_vma)
3329 + sizeof (char));
3330 data = bfd_zalloc (abfd, size);
3331 if (data == NULL)
3332 return FALSE;
3333
3334 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3335 data += num_syms * sizeof (bfd_signed_vma);
3336
3337 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3338 data += num_syms * sizeof (struct arm_local_iplt_info *);
3339
3340 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3341 data += num_syms * sizeof (bfd_vma);
3342
3343 elf32_arm_local_got_tls_type (abfd) = data;
3344 }
3345 return TRUE;
3346}
3347
3348/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3349 to input bfd ABFD. Create the information if it doesn't already exist.
3350 Return null if an allocation fails. */
3351
3352static struct arm_local_iplt_info *
3353elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3354{
3355 struct arm_local_iplt_info **ptr;
3356
3357 if (!elf32_arm_allocate_local_sym_info (abfd))
3358 return NULL;
3359
3360 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3361 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3362 if (*ptr == NULL)
3363 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3364 return *ptr;
3365}
3366
3367/* Try to obtain PLT information for the symbol with index R_SYMNDX
3368 in ABFD's symbol table. If the symbol is global, H points to its
3369 hash table entry, otherwise H is null.
3370
3371 Return true if the symbol does have PLT information. When returning
3372 true, point *ROOT_PLT at the target-independent reference count/offset
3373 union and *ARM_PLT at the ARM-specific information. */
3374
3375static bfd_boolean
4ba2ef8f
TP		 3376elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3377 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3378 unsigned long r_symndx, union gotplt_union **root_plt,
3379 struct arm_plt_info **arm_plt)
3380{
3381 struct arm_local_iplt_info *local_iplt;
3382
4ba2ef8f
TP		 3383 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3384 return FALSE;
3385
34e77a92
RS		 3386 if (h != NULL)
3387 {
3388 *root_plt = &h->root.plt;
3389 *arm_plt = &h->plt;
3390 return TRUE;
3391 }
3392
3393 if (elf32_arm_local_iplt (abfd) == NULL)
3394 return FALSE;
3395
3396 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3397 if (local_iplt == NULL)
3398 return FALSE;
3399
3400 *root_plt = &local_iplt->root;
3401 *arm_plt = &local_iplt->arm;
3402 return TRUE;
3403}
3404
3405/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3406 before it. */
3407
3408static bfd_boolean
3409elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3410 struct arm_plt_info *arm_plt)
3411{
3412 struct elf32_arm_link_hash_table *htab;
3413
3414 htab = elf32_arm_hash_table (info);
3415 return (arm_plt->thumb_refcount != 0
3416 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3417}
3418
3419/* Return a pointer to the head of the dynamic reloc list that should
3420 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3421 ABFD's symbol table. Return null if an error occurs. */
3422
3423static struct elf_dyn_relocs **
3424elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3425 Elf_Internal_Sym *isym)
3426{
3427 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3428 {
3429 struct arm_local_iplt_info *local_iplt;
3430
3431 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3432 if (local_iplt == NULL)
3433 return NULL;
3434 return &local_iplt->dyn_relocs;
3435 }
3436 else
3437 {
3438 /* Track dynamic relocs needed for local syms too.
3439 We really need local syms available to do this
3440 easily. Oh well. */
3441 asection *s;
3442 void *vpp;
3443
3444 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3445 if (s == NULL)
3446 abort ();
3447
3448 vpp = &elf_section_data (s)->local_dynrel;
3449 return (struct elf_dyn_relocs **) vpp;
3450 }
3451}
3452
906e58ca
NC		 3453/* Initialize an entry in the stub hash table. */
3454
3455static struct bfd_hash_entry *
3456stub_hash_newfunc (struct bfd_hash_entry *entry,
3457 struct bfd_hash_table *table,
3458 const char *string)
3459{
3460 /* Allocate the structure if it has not already been allocated by a
3461 subclass. */
3462 if (entry == NULL)
3463 {
21d799b5 3464 entry = (struct bfd_hash_entry *)
99059e56 3465 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3466 if (entry == NULL)
3467 return entry;
3468 }
3469
3470 /* Call the allocation method of the superclass. */
3471 entry = bfd_hash_newfunc (entry, table, string);
3472 if (entry != NULL)
3473 {
3474 struct elf32_arm_stub_hash_entry *eh;
3475
3476 /* Initialize the local fields. */
3477 eh = (struct elf32_arm_stub_hash_entry *) entry;
3478 eh->stub_sec = NULL;
0955507f 3479 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3480 eh->source_value = 0;
906e58ca
NC		 3481 eh->target_value = 0;
3482 eh->target_section = NULL;
cedfb179 3483 eh->orig_insn = 0;
906e58ca 3484 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3485 eh->stub_size = 0;
3486 eh->stub_template = NULL;
0955507f 3487 eh->stub_template_size = -1;
906e58ca
NC		 3488 eh->h = NULL;
3489 eh->id_sec = NULL;
d8d2f433 3490 eh->output_name = NULL;
906e58ca
NC		 3491 }
3492
3493 return entry;
3494}
3495
00a97672 3496/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3497 shortcuts to them in our hash table. */
3498
3499static bfd_boolean
57e8b36a 3500create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3501{
3502 struct elf32_arm_link_hash_table *htab;
3503
e5a52504 3504 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3505 if (htab == NULL)
3506 return FALSE;
3507
e5a52504
MM		 3508 /* BPABI objects never have a GOT, or associated sections. */
3509 if (htab->symbian_p)
3510 return TRUE;
3511
5e681ec4
PB		 3512 if (! _bfd_elf_create_got_section (dynobj, info))
3513 return FALSE;
3514
5e681ec4
PB		 3515 return TRUE;
3516}
3517
34e77a92
RS		 3518/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3519
3520static bfd_boolean
3521create_ifunc_sections (struct bfd_link_info *info)
3522{
3523 struct elf32_arm_link_hash_table *htab;
3524 const struct elf_backend_data *bed;
3525 bfd *dynobj;
3526 asection *s;
3527 flagword flags;
b38cadfb 3528
34e77a92
RS		 3529 htab = elf32_arm_hash_table (info);
3530 dynobj = htab->root.dynobj;
3531 bed = get_elf_backend_data (dynobj);
3532 flags = bed->dynamic_sec_flags;
3533
3534 if (htab->root.iplt == NULL)
3535 {
3d4d4302
AM		 3536 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3537 flags | SEC_READONLY | SEC_CODE);
34e77a92 3538 if (s == NULL
a0f49396 3539 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3540 return FALSE;
3541 htab->root.iplt = s;
3542 }
3543
3544 if (htab->root.irelplt == NULL)
3545 {
3d4d4302
AM		 3546 s = bfd_make_section_anyway_with_flags (dynobj,
3547 RELOC_SECTION (htab, ".iplt"),
3548 flags | SEC_READONLY);
34e77a92 3549 if (s == NULL
a0f49396 3550 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3551 return FALSE;
3552 htab->root.irelplt = s;
3553 }
3554
3555 if (htab->root.igotplt == NULL)
3556 {
3d4d4302 3557 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3558 if (s == NULL
3559 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3560 return FALSE;
3561 htab->root.igotplt = s;
3562 }
3563 return TRUE;
3564}
3565
eed94f8f
NC		 3566/* Determine if we're dealing with a Thumb only architecture. */
3567
3568static bfd_boolean
3569using_thumb_only (struct elf32_arm_link_hash_table *globals)
3570{
2fd158eb
TP		 3571 int arch;
3572 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3573 Tag_CPU_arch_profile);
eed94f8f 3574
2fd158eb
TP		 3575 if (profile)
3576 return profile == 'M';
eed94f8f 3577
2fd158eb 3578 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3579
60a019a0 3580 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3581 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0 3582
2fd158eb
TP		 3583 if (arch == TAG_CPU_ARCH_V6_M
3584 || arch == TAG_CPU_ARCH_V6S_M
3585 || arch == TAG_CPU_ARCH_V7E_M
3586 || arch == TAG_CPU_ARCH_V8M_BASE
3587 || arch == TAG_CPU_ARCH_V8M_MAIN)
3588 return TRUE;
eed94f8f 3589
2fd158eb 3590 return FALSE;
eed94f8f
NC		 3591}
3592
3593/* Determine if we're dealing with a Thumb-2 object. */
3594
3595static bfd_boolean
3596using_thumb2 (struct elf32_arm_link_hash_table *globals)
3597{
60a019a0
TP		 3598 int arch;
3599 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3600 Tag_THUMB_ISA_use);
3601
3602 if (thumb_isa)
3603 return thumb_isa == 2;
3604
3605 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3606
3607 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3608 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0
TP		 3609
3610 return (arch == TAG_CPU_ARCH_V6T2
3611 || arch == TAG_CPU_ARCH_V7
3612 || arch == TAG_CPU_ARCH_V7E_M
3613 || arch == TAG_CPU_ARCH_V8
bff0500d 3614 || arch == TAG_CPU_ARCH_V8R
60a019a0 3615 || arch == TAG_CPU_ARCH_V8M_MAIN);
eed94f8f
NC		 3616}
3617
5e866f5a
TP		 3618/* Determine whether Thumb-2 BL instruction is available. */
3619
3620static bfd_boolean
3621using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3622{
3623 int arch =
3624 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3625
3626 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3627 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
5e866f5a
TP		 3628
3629 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3630 return (arch == TAG_CPU_ARCH_V6T2
3631 || arch >= TAG_CPU_ARCH_V7);
3632}
3633
00a97672
RS		 3634/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3635 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3636 hash table. */
3637
3638static bfd_boolean
57e8b36a 3639elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3640{
3641 struct elf32_arm_link_hash_table *htab;
3642
3643 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3644 if (htab == NULL)
3645 return FALSE;
3646
362d30a1 3647 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3648 return FALSE;
3649
3650 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3651 return FALSE;
3652
00a97672
RS		 3653 if (htab->vxworks_p)
3654 {
3655 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3656 return FALSE;
3657
0e1862bb 3658 if (bfd_link_pic (info))
00a97672
RS		 3659 {
3660 htab->plt_header_size = 0;
3661 htab->plt_entry_size
3662 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3663 }
3664 else
3665 {
3666 htab->plt_header_size
3667 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3668 htab->plt_entry_size
3669 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3670 }
aebf9be7
NC		 3671
3672 if (elf_elfheader (dynobj))
3673 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3674 }
eed94f8f
NC		 3675 else
3676 {
3677 /* PR ld/16017
3678 Test for thumb only architectures. Note - we cannot just call
3679 using_thumb_only() as the attributes in the output bfd have not been
3680 initialised at this point, so instead we use the input bfd. */
3681 bfd * saved_obfd = htab->obfd;
3682
3683 htab->obfd = dynobj;
3684 if (using_thumb_only (htab))
3685 {
3686 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3687 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3688 }
3689 htab->obfd = saved_obfd;
3690 }
5e681ec4 3691
362d30a1
RS		 3692 if (!htab->root.splt
3693 || !htab->root.srelplt
9d19e4fd
AM		 3694 || !htab->root.sdynbss
3695 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 3696 abort ();
3697
3698 return TRUE;
3699}
3700
906e58ca
NC		 3701/* Copy the extra info we tack onto an elf_link_hash_entry. */
3702
3703static void
3704elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3705 struct elf_link_hash_entry *dir,
3706 struct elf_link_hash_entry *ind)
3707{
3708 struct elf32_arm_link_hash_entry *edir, *eind;
3709
3710 edir = (struct elf32_arm_link_hash_entry *) dir;
3711 eind = (struct elf32_arm_link_hash_entry *) ind;
3712
0bdcacaf 3713 if (eind->dyn_relocs != NULL)
906e58ca 3714 {
0bdcacaf 3715 if (edir->dyn_relocs != NULL)
906e58ca 3716 {
0bdcacaf
RS		 3717 struct elf_dyn_relocs **pp;
3718 struct elf_dyn_relocs *p;
906e58ca
NC		 3719
3720 /* Add reloc counts against the indirect sym to the direct sym
3721 list. Merge any entries against the same section. */
0bdcacaf 3722 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3723 {
0bdcacaf 3724 struct elf_dyn_relocs *q;
906e58ca 3725
0bdcacaf
RS		 3726 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3727 if (q->sec == p->sec)
906e58ca
NC		 3728 {
3729 q->pc_count += p->pc_count;
3730 q->count += p->count;
3731 *pp = p->next;
3732 break;
3733 }
3734 if (q == NULL)
3735 pp = &p->next;
3736 }
0bdcacaf 3737 *pp = edir->dyn_relocs;
906e58ca
NC		 3738 }
3739
0bdcacaf
RS		 3740 edir->dyn_relocs = eind->dyn_relocs;
3741 eind->dyn_relocs = NULL;
906e58ca
NC		 3742 }
3743
3744 if (ind->root.type == bfd_link_hash_indirect)
3745 {
3746 /* Copy over PLT info. */
34e77a92
RS		 3747 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3748 eind->plt.thumb_refcount = 0;
3749 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3750 eind->plt.maybe_thumb_refcount = 0;
3751 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3752 eind->plt.noncall_refcount = 0;
3753
3754 /* We should only allocate a function to .iplt once the final
3755 symbol information is known. */
3756 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3757
3758 if (dir->got.refcount <= 0)
3759 {
3760 edir->tls_type = eind->tls_type;
3761 eind->tls_type = GOT_UNKNOWN;
3762 }
3763 }
3764
3765 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3766}
3767
68faa637
AM		 3768/* Destroy an ARM elf linker hash table. */
3769
3770static void
d495ab0d 3771elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3772{
3773 struct elf32_arm_link_hash_table *ret
d495ab0d 3774 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3775
3776 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3777 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3778}
3779
906e58ca
NC		 3780/* Create an ARM elf linker hash table. */
3781
3782static struct bfd_link_hash_table *
3783elf32_arm_link_hash_table_create (bfd *abfd)
3784{
3785 struct elf32_arm_link_hash_table *ret;
3786 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3787
7bf52ea2 3788 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3789 if (ret == NULL)
3790 return NULL;
3791
3792 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3793 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3794 sizeof (struct elf32_arm_link_hash_entry),
3795 ARM_ELF_DATA))
906e58ca
NC		 3796 {
3797 free (ret);
3798 return NULL;
3799 }
3800
906e58ca 3801 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3802 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3803#ifdef FOUR_WORD_PLT
3804 ret->plt_header_size = 16;
3805 ret->plt_entry_size = 16;
3806#else
3807 ret->plt_header_size = 20;
1db37fe6 3808 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3809#endif
f3185997 3810 ret->use_rel = TRUE;
906e58ca 3811 ret->obfd = abfd;
617a5ada 3812 ret->fdpic_p = 0;
906e58ca
NC		 3813
3814 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3815 sizeof (struct elf32_arm_stub_hash_entry)))
3816 {
d495ab0d 3817 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3818 return NULL;
3819 }
d495ab0d 3820 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3821
3822 return &ret->root.root;
3823}
3824
cd1dac3d
DG		 3825/* Determine what kind of NOPs are available. */
3826
3827static bfd_boolean
3828arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3829{
3830 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3831 Tag_CPU_arch);
cd1dac3d 3832
60a019a0 3833 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3834 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0
TP		 3835
3836 return (arch == TAG_CPU_ARCH_V6T2
3837 || arch == TAG_CPU_ARCH_V6K
3838 || arch == TAG_CPU_ARCH_V7
bff0500d
TP		 3839 || arch == TAG_CPU_ARCH_V8
3840 || arch == TAG_CPU_ARCH_V8R);
cd1dac3d
DG		 3841}
3842
f4ac8484
DJ		 3843static bfd_boolean
3844arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3845{
3846 switch (stub_type)
3847 {
fea2b4d6 3848 case arm_stub_long_branch_thumb_only:
80c135e5 3849 case arm_stub_long_branch_thumb2_only:
d5a67c02 3850 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 3851 case arm_stub_long_branch_v4t_thumb_arm:
3852 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3853 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3854 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3855 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 3856 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 3857 return TRUE;
3858 case arm_stub_none:
3859 BFD_FAIL ();
3860 return FALSE;
3861 break;
3862 default:
3863 return FALSE;
3864 }
3865}
3866
906e58ca
NC		 3867/* Determine the type of stub needed, if any, for a call. */
3868
3869static enum elf32_arm_stub_type
3870arm_type_of_stub (struct bfd_link_info *info,
3871 asection *input_sec,
3872 const Elf_Internal_Rela *rel,
34e77a92 3873 unsigned char st_type,
35fc36a8 3874 enum arm_st_branch_type *actual_branch_type,
906e58ca 3875 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3876 bfd_vma destination,
3877 asection *sym_sec,
3878 bfd *input_bfd,
3879 const char *name)
906e58ca
NC		 3880{
3881 bfd_vma location;
3882 bfd_signed_vma branch_offset;
3883 unsigned int r_type;
3884 struct elf32_arm_link_hash_table * globals;
5e866f5a 3885 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 3886 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3887 int use_plt = 0;
35fc36a8 3888 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3889 union gotplt_union *root_plt;
3890 struct arm_plt_info *arm_plt;
d5a67c02
AV		 3891 int arch;
3892 int thumb2_movw;
906e58ca 3893
35fc36a8 3894 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3895 return stub_type;
3896
906e58ca 3897 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3898 if (globals == NULL)
3899 return stub_type;
906e58ca
NC		 3900
3901 thumb_only = using_thumb_only (globals);
906e58ca 3902 thumb2 = using_thumb2 (globals);
5e866f5a 3903 thumb2_bl = using_thumb2_bl (globals);
906e58ca 3904
d5a67c02
AV		 3905 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3906
3907 /* True for architectures that implement the thumb2 movw instruction. */
3908 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
3909
906e58ca
NC		 3910 /* Determine where the call point is. */
3911 location = (input_sec->output_offset
3912 + input_sec->output_section->vma
3913 + rel->r_offset);
3914
906e58ca
NC		 3915 r_type = ELF32_R_TYPE (rel->r_info);
3916
39f21624
NC		 3917 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3918 are considering a function call relocation. */
c5423981 3919 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
07d6d2b8 3920 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3921 && branch_type == ST_BRANCH_TO_ARM)
3922 branch_type = ST_BRANCH_TO_THUMB;
3923
34e77a92
RS		 3924 /* For TLS call relocs, it is the caller's responsibility to provide
3925 the address of the appropriate trampoline. */
3926 if (r_type != R_ARM_TLS_CALL
3927 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 3928 && elf32_arm_get_plt_info (input_bfd, globals, hash,
3929 ELF32_R_SYM (rel->r_info), &root_plt,
3930 &arm_plt)
34e77a92 3931 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3932 {
34e77a92 3933 asection *splt;
fe33d2fa 3934
34e77a92
RS		 3935 if (hash == NULL || hash->is_iplt)
3936 splt = globals->root.iplt;
3937 else
3938 splt = globals->root.splt;
3939 if (splt != NULL)
b38cadfb 3940 {
34e77a92
RS		 3941 use_plt = 1;
3942
3943 /* Note when dealing with PLT entries: the main PLT stub is in
3944 ARM mode, so if the branch is in Thumb mode, another
3945 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 3946 PLT stub. If a long branch stub is needed, we'll add a
3947 Thumb->Arm one and branch directly to the ARM PLT entry.
3948 Here, we have to check if a pre-PLT Thumb->ARM stub
3949 is needed and if it will be close enough. */
34e77a92
RS		 3950
3951 destination = (splt->output_section->vma
3952 + splt->output_offset
3953 + root_plt->offset);
3954 st_type = STT_FUNC;
2df2751d
CL		 3955
3956 /* Thumb branch/call to PLT: it can become a branch to ARM
3957 or to Thumb. We must perform the same checks and
3958 corrections as in elf32_arm_final_link_relocate. */
3959 if ((r_type == R_ARM_THM_CALL)
3960 || (r_type == R_ARM_THM_JUMP24))
3961 {
3962 if (globals->use_blx
3963 && r_type == R_ARM_THM_CALL
3964 && !thumb_only)
3965 {
3966 /* If the Thumb BLX instruction is available, convert
3967 the BL to a BLX instruction to call the ARM-mode
3968 PLT entry. */
3969 branch_type = ST_BRANCH_TO_ARM;
3970 }
3971 else
3972 {
3973 if (!thumb_only)
3974 /* Target the Thumb stub before the ARM PLT entry. */
3975 destination -= PLT_THUMB_STUB_SIZE;
3976 branch_type = ST_BRANCH_TO_THUMB;
3977 }
3978 }
3979 else
3980 {
3981 branch_type = ST_BRANCH_TO_ARM;
3982 }
34e77a92 3983 }
5fa9e92f 3984 }
34e77a92
RS		 3985 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3986 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 3987
fe33d2fa
CL		 3988 branch_offset = (bfd_signed_vma)(destination - location);
3989
0855e32b 3990 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 3991 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 3992 {
5fa9e92f
CL		 3993 /* Handle cases where:
3994 - this call goes too far (different Thumb/Thumb2 max
99059e56 3995 distance)
155d87d7 3996 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 3997 Thumb->Arm branch (not bl). A stub is needed in this case,
3998 but only if this call is not through a PLT entry. Indeed,
695344c0 3999 PLT stubs handle mode switching already. */
5e866f5a 4000 if ((!thumb2_bl
906e58ca
NC		 4001 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
4002 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 4003 || (thumb2_bl
906e58ca
NC		 4004 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4005 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4006 || (thumb2
4007 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4008 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4009 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4010 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4011 && (((r_type == R_ARM_THM_CALL
4012 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981 4013 || (r_type == R_ARM_THM_JUMP24)
07d6d2b8 4014 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4015 && !use_plt))
906e58ca 4016 {
2df2751d
CL		 4017 /* If we need to insert a Thumb-Thumb long branch stub to a
4018 PLT, use one that branches directly to the ARM PLT
4019 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4020 stub, undo this now. */
695344c0
NC		 4021 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4022 {
4023 branch_type = ST_BRANCH_TO_ARM;
4024 branch_offset += PLT_THUMB_STUB_SIZE;
4025 }
2df2751d 4026
35fc36a8 4027 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4028 {
4029 /* Thumb to thumb. */
4030 if (!thumb_only)
4031 {
d5a67c02 4032 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4033 _bfd_error_handler
871b3ab2 4034 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4035 " section with SHF_ARM_PURECODE section"
4036 " attribute is only supported for M-profile"
90b6238f 4037 " targets that implement the movw instruction"),
10463f39 4038 input_bfd, input_sec);
d5a67c02 4039
0e1862bb 4040 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4041 /* PIC stubs. */
155d87d7 4042 ? ((globals->use_blx
9553db3c 4043 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4044 /* V5T and above. Stub starts with ARM code, so
4045 we must be able to switch mode before
4046 reaching it, which is only possible for 'bl'
4047 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4048 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4049 /* On V4T, use Thumb code only. */
d3626fb0 4050 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4051
4052 /* non-PIC stubs. */
155d87d7 4053 : ((globals->use_blx
9553db3c 4054 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4055 /* V5T and above. */
4056 ? arm_stub_long_branch_any_any
4057 /* V4T. */
d3626fb0 4058 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4059 }
4060 else
4061 {
d5a67c02
AV		 4062 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4063 stub_type = arm_stub_long_branch_thumb2_only_pure;
4064 else
4065 {
4066 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4067 _bfd_error_handler
871b3ab2 4068 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4069 " section with SHF_ARM_PURECODE section"
4070 " attribute is only supported for M-profile"
90b6238f 4071 " targets that implement the movw instruction"),
10463f39 4072 input_bfd, input_sec);
d5a67c02
AV		 4073
4074 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4075 /* PIC stub. */
4076 ? arm_stub_long_branch_thumb_only_pic
4077 /* non-PIC stub. */
4078 : (thumb2 ? arm_stub_long_branch_thumb2_only
4079 : arm_stub_long_branch_thumb_only);
4080 }
906e58ca
NC		 4081 }
4082 }
4083 else
4084 {
d5a67c02 4085 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4086 _bfd_error_handler
871b3ab2 4087 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4088 " section with SHF_ARM_PURECODE section"
4089 " attribute is only supported" " for M-profile"
90b6238f 4090 " targets that implement the movw instruction"),
10463f39 4091 input_bfd, input_sec);
d5a67c02 4092
906e58ca 4093 /* Thumb to arm. */
c820be07
NC		 4094 if (sym_sec != NULL
4095 && sym_sec->owner != NULL
4096 && !INTERWORK_FLAG (sym_sec->owner))
4097 {
4eca0228 4098 _bfd_error_handler
90b6238f
AM		 4099 (_("%pB(%s): warning: interworking not enabled;"
4100 " first occurrence: %pB: %s call to %s"),
4101 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
c820be07
NC		 4102 }
4103
0855e32b 4104 stub_type =
0e1862bb 4105 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4106 /* PIC stubs. */
0855e32b 4107 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4108 /* TLS PIC stubs. */
0855e32b
NS		 4109 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4110 : arm_stub_long_branch_v4t_thumb_tls_pic)
4111 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4112 /* V5T PIC and above. */
4113 ? arm_stub_long_branch_any_arm_pic
4114 /* V4T PIC stub. */
4115 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4116
4117 /* non-PIC stubs. */
0855e32b 4118 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4119 /* V5T and above. */
4120 ? arm_stub_long_branch_any_any
4121 /* V4T. */
4122 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4123
4124 /* Handle v4t short branches. */
fea2b4d6 4125 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4126 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4127 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4128 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4129 }
4130 }
4131 }
fe33d2fa
CL		 4132 else if (r_type == R_ARM_CALL
4133 || r_type == R_ARM_JUMP24
0855e32b
NS		 4134 || r_type == R_ARM_PLT32
4135 || r_type == R_ARM_TLS_CALL)
906e58ca 4136 {
d5a67c02 4137 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4138 _bfd_error_handler
871b3ab2 4139 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4140 " section with SHF_ARM_PURECODE section"
4141 " attribute is only supported for M-profile"
90b6238f 4142 " targets that implement the movw instruction"),
10463f39 4143 input_bfd, input_sec);
35fc36a8 4144 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4145 {
4146 /* Arm to thumb. */
c820be07
NC		 4147
4148 if (sym_sec != NULL
4149 && sym_sec->owner != NULL
4150 && !INTERWORK_FLAG (sym_sec->owner))
4151 {
4eca0228 4152 _bfd_error_handler
90b6238f
AM		 4153 (_("%pB(%s): warning: interworking not enabled;"
4154 " first occurrence: %pB: %s call to %s"),
4155 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
c820be07
NC		 4156 }
4157
4158 /* We have an extra 2-bytes reach because of
4159 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4160 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4161 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4162 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4163 || (r_type == R_ARM_JUMP24)
4164 || (r_type == R_ARM_PLT32))
906e58ca 4165 {
0e1862bb 4166 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4167 /* PIC stubs. */
ebe24dd4
CL		 4168 ? ((globals->use_blx)
4169 /* V5T and above. */
4170 ? arm_stub_long_branch_any_thumb_pic
4171 /* V4T stub. */
4172 : arm_stub_long_branch_v4t_arm_thumb_pic)
4173
c2b4a39d
CL		 4174 /* non-PIC stubs. */
4175 : ((globals->use_blx)
4176 /* V5T and above. */
4177 ? arm_stub_long_branch_any_any
4178 /* V4T. */
4179 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4180 }
4181 }
4182 else
4183 {
4184 /* Arm to arm. */
4185 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4186 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4187 {
0855e32b 4188 stub_type =
0e1862bb 4189 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4190 /* PIC stubs. */
0855e32b 4191 ? (r_type == R_ARM_TLS_CALL
6a631e86 4192 /* TLS PIC Stub. */
0855e32b 4193 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4194 : (globals->nacl_p
4195 ? arm_stub_long_branch_arm_nacl_pic
4196 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4197 /* non-PIC stubs. */
7a89b94e
NC		 4198 : (globals->nacl_p
4199 ? arm_stub_long_branch_arm_nacl
4200 : arm_stub_long_branch_any_any);
906e58ca
NC		 4201 }
4202 }
4203 }
4204
fe33d2fa
CL		 4205 /* If a stub is needed, record the actual destination type. */
4206 if (stub_type != arm_stub_none)
35fc36a8 4207 *actual_branch_type = branch_type;
fe33d2fa 4208
906e58ca
NC		 4209 return stub_type;
4210}
4211
4212/* Build a name for an entry in the stub hash table. */
4213
4214static char *
4215elf32_arm_stub_name (const asection *input_section,
4216 const asection *sym_sec,
4217 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4218 const Elf_Internal_Rela *rel,
4219 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4220{
4221 char *stub_name;
4222 bfd_size_type len;
4223
4224 if (hash)
4225 {
fe33d2fa 4226 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4227 stub_name = (char *) bfd_malloc (len);
906e58ca 4228 if (stub_name != NULL)
fe33d2fa 4229 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4230 input_section->id & 0xffffffff,
4231 hash->root.root.root.string,
fe33d2fa
CL		 4232 (int) rel->r_addend & 0xffffffff,
4233 (int) stub_type);
906e58ca
NC		 4234 }
4235 else
4236 {
fe33d2fa 4237 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4238 stub_name = (char *) bfd_malloc (len);
906e58ca 4239 if (stub_name != NULL)
fe33d2fa 4240 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4241 input_section->id & 0xffffffff,
4242 sym_sec->id & 0xffffffff,
0855e32b
NS		 4243 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4244 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4245 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4246 (int) rel->r_addend & 0xffffffff,
4247 (int) stub_type);
906e58ca
NC		 4248 }
4249
4250 return stub_name;
4251}
4252
4253/* Look up an entry in the stub hash. Stub entries are cached because
4254 creating the stub name takes a bit of time. */
4255
4256static struct elf32_arm_stub_hash_entry *
4257elf32_arm_get_stub_entry (const asection *input_section,
4258 const asection *sym_sec,
4259 struct elf_link_hash_entry *hash,
4260 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4261 struct elf32_arm_link_hash_table *htab,
4262 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4263{
4264 struct elf32_arm_stub_hash_entry *stub_entry;
4265 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4266 const asection *id_sec;
4267
4268 if ((input_section->flags & SEC_CODE) == 0)
4269 return NULL;
4270
4271 /* If this input section is part of a group of sections sharing one
4272 stub section, then use the id of the first section in the group.
4273 Stub names need to include a section id, as there may well be
4274 more than one stub used to reach say, printf, and we need to
4275 distinguish between them. */
c2abbbeb 4276 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4277 id_sec = htab->stub_group[input_section->id].link_sec;
4278
4279 if (h != NULL && h->stub_cache != NULL
4280 && h->stub_cache->h == h
fe33d2fa
CL		 4281 && h->stub_cache->id_sec == id_sec
4282 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4283 {
4284 stub_entry = h->stub_cache;
4285 }
4286 else
4287 {
4288 char *stub_name;
4289
fe33d2fa 4290 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4291 if (stub_name == NULL)
4292 return NULL;
4293
4294 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4295 stub_name, FALSE, FALSE);
4296 if (h != NULL)
4297 h->stub_cache = stub_entry;
4298
4299 free (stub_name);
4300 }
4301
4302 return stub_entry;
4303}
4304
daa4adae
TP		 4305/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4306 section. */
4307
4308static bfd_boolean
4309arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4310{
4311 if (stub_type >= max_stub_type)
4312 abort (); /* Should be unreachable. */
4313
4ba2ef8f
TP		 4314 switch (stub_type)
4315 {
4316 case arm_stub_cmse_branch_thumb_only:
4317 return TRUE;
4318
4319 default:
4320 return FALSE;
4321 }
4322
4323 abort (); /* Should be unreachable. */
daa4adae
TP		 4324}
4325
4326/* Required alignment (as a power of 2) for the dedicated section holding
4327 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4328 with input sections. */
4329
4330static int
4331arm_dedicated_stub_output_section_required_alignment
4332 (enum elf32_arm_stub_type stub_type)
4333{
4334 if (stub_type >= max_stub_type)
4335 abort (); /* Should be unreachable. */
4336
4ba2ef8f
TP		 4337 switch (stub_type)
4338 {
4339 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4340 boundary. */
4341 case arm_stub_cmse_branch_thumb_only:
4342 return 5;
4343
4344 default:
4345 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4346 return 0;
4347 }
4348
4349 abort (); /* Should be unreachable. */
daa4adae
TP		 4350}
4351
4352/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4353 NULL if veneers of this type are interspersed with input sections. */
4354
4355static const char *
4356arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4357{
4358 if (stub_type >= max_stub_type)
4359 abort (); /* Should be unreachable. */
4360
4ba2ef8f
TP		 4361 switch (stub_type)
4362 {
4363 case arm_stub_cmse_branch_thumb_only:
4364 return ".gnu.sgstubs";
4365
4366 default:
4367 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4368 return NULL;
4369 }
4370
4371 abort (); /* Should be unreachable. */
daa4adae
TP		 4372}
4373
4374/* If veneers of type STUB_TYPE should go in a dedicated output section,
4375 returns the address of the hash table field in HTAB holding a pointer to the
4376 corresponding input section. Otherwise, returns NULL. */
4377
4378static asection **
4ba2ef8f
TP		 4379arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4380 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4381{
4382 if (stub_type >= max_stub_type)
4383 abort (); /* Should be unreachable. */
4384
4ba2ef8f
TP		 4385 switch (stub_type)
4386 {
4387 case arm_stub_cmse_branch_thumb_only:
4388 return &htab->cmse_stub_sec;
4389
4390 default:
4391 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4392 return NULL;
4393 }
4394
4395 abort (); /* Should be unreachable. */
daa4adae
TP		 4396}
4397
4398/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4399 is the section that branch into veneer and can be NULL if stub should go in
4400 a dedicated output section. Returns a pointer to the stub section, and the
4401 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4402 LINK_SEC_P may be NULL. */
906e58ca 4403
48229727
JB		 4404static asection *
4405elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4406 struct elf32_arm_link_hash_table *htab,
4407 enum elf32_arm_stub_type stub_type)
906e58ca 4408{
daa4adae
TP		 4409 asection *link_sec, *out_sec, **stub_sec_p;
4410 const char *stub_sec_prefix;
4411 bfd_boolean dedicated_output_section =
4412 arm_dedicated_stub_output_section_required (stub_type);
4413 int align;
906e58ca 4414
daa4adae 4415 if (dedicated_output_section)
906e58ca 4416 {
daa4adae
TP		 4417 bfd *output_bfd = htab->obfd;
4418 const char *out_sec_name =
4419 arm_dedicated_stub_output_section_name (stub_type);
4420 link_sec = NULL;
4421 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4422 stub_sec_prefix = out_sec_name;
4423 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4424 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4425 if (out_sec == NULL)
906e58ca 4426 {
90b6238f 4427 _bfd_error_handler (_("no address assigned to the veneers output "
4eca0228 4428 "section %s"), out_sec_name);
daa4adae 4429 return NULL;
906e58ca 4430 }
daa4adae
TP		 4431 }
4432 else
4433 {
c2abbbeb 4434 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4435 link_sec = htab->stub_group[section->id].link_sec;
4436 BFD_ASSERT (link_sec != NULL);
4437 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4438 if (*stub_sec_p == NULL)
4439 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4440 stub_sec_prefix = link_sec->name;
4441 out_sec = link_sec->output_section;
4442 align = htab->nacl_p ? 4 : 3;
906e58ca 4443 }
b38cadfb 4444
daa4adae
TP		 4445 if (*stub_sec_p == NULL)
4446 {
4447 size_t namelen;
4448 bfd_size_type len;
4449 char *s_name;
4450
4451 namelen = strlen (stub_sec_prefix);
4452 len = namelen + sizeof (STUB_SUFFIX);
4453 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4454 if (s_name == NULL)
4455 return NULL;
4456
4457 memcpy (s_name, stub_sec_prefix, namelen);
4458 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4459 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4460 align);
4461 if (*stub_sec_p == NULL)
4462 return NULL;
4463
4464 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4465 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4466 | SEC_KEEP;
4467 }
4468
4469 if (!dedicated_output_section)
4470 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4471
48229727
JB		 4472 if (link_sec_p)
4473 *link_sec_p = link_sec;
b38cadfb 4474
daa4adae 4475 return *stub_sec_p;
48229727
JB		 4476}
4477
4478/* Add a new stub entry to the stub hash. Not all fields of the new
4479 stub entry are initialised. */
4480
4481static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4482elf32_arm_add_stub (const char *stub_name, asection *section,
4483 struct elf32_arm_link_hash_table *htab,
4484 enum elf32_arm_stub_type stub_type)
48229727
JB		 4485{
4486 asection *link_sec;
4487 asection *stub_sec;
4488 struct elf32_arm_stub_hash_entry *stub_entry;
4489
daa4adae
TP		 4490 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4491 stub_type);
48229727
JB		 4492 if (stub_sec == NULL)
4493 return NULL;
906e58ca
NC		 4494
4495 /* Enter this entry into the linker stub hash table. */
4496 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4497 TRUE, FALSE);
4498 if (stub_entry == NULL)
4499 {
6bde4c52
TP		 4500 if (section == NULL)
4501 section = stub_sec;
871b3ab2 4502 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 4503 section->owner, stub_name);
906e58ca
NC		 4504 return NULL;
4505 }
4506
4507 stub_entry->stub_sec = stub_sec;
0955507f 4508 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4509 stub_entry->id_sec = link_sec;
4510
906e58ca
NC		 4511 return stub_entry;
4512}
4513
4514/* Store an Arm insn into an output section not processed by
4515 elf32_arm_write_section. */
4516
4517static void
8029a119
NC		 4518put_arm_insn (struct elf32_arm_link_hash_table * htab,
4519 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4520{
4521 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4522 bfd_putl32 (val, ptr);
4523 else
4524 bfd_putb32 (val, ptr);
4525}
4526
4527/* Store a 16-bit Thumb insn into an output section not processed by
4528 elf32_arm_write_section. */
4529
4530static void
8029a119
NC		 4531put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4532 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4533{
4534 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4535 bfd_putl16 (val, ptr);
4536 else
4537 bfd_putb16 (val, ptr);
4538}
4539
a504d23a
LA		 4540/* Store a Thumb2 insn into an output section not processed by
4541 elf32_arm_write_section. */
4542
4543static void
4544put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4545 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4546{
4547 /* T2 instructions are 16-bit streamed. */
4548 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4549 {
4550 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4551 bfd_putl16 ((val & 0xffff), ptr + 2);
4552 }
4553 else
4554 {
4555 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4556 bfd_putb16 ((val & 0xffff), ptr + 2);
4557 }
4558}
4559
0855e32b
NS		 4560/* If it's possible to change R_TYPE to a more efficient access
4561 model, return the new reloc type. */
4562
4563static unsigned
b38cadfb 4564elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4565 struct elf_link_hash_entry *h)
4566{
4567 int is_local = (h == NULL);
4568
0e1862bb
L		 4569 if (bfd_link_pic (info)
4570 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4571 return r_type;
4572
b38cadfb 4573 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4574 switch (r_type)
4575 {
4576 case R_ARM_TLS_GOTDESC:
4577 case R_ARM_TLS_CALL:
4578 case R_ARM_THM_TLS_CALL:
4579 case R_ARM_TLS_DESCSEQ:
4580 case R_ARM_THM_TLS_DESCSEQ:
4581 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4582 }
4583
4584 return r_type;
4585}
4586
48229727
JB		 4587static bfd_reloc_status_type elf32_arm_final_link_relocate
4588 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4589 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4590 const char *, unsigned char, enum arm_st_branch_type,
4591 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4592
4563a860
JB		 4593static unsigned int
4594arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4595{
4596 switch (stub_type)
4597 {
4598 case arm_stub_a8_veneer_b_cond:
4599 case arm_stub_a8_veneer_b:
4600 case arm_stub_a8_veneer_bl:
4601 return 2;
4602
4603 case arm_stub_long_branch_any_any:
4604 case arm_stub_long_branch_v4t_arm_thumb:
4605 case arm_stub_long_branch_thumb_only:
80c135e5 4606 case arm_stub_long_branch_thumb2_only:
d5a67c02 4607 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4608 case arm_stub_long_branch_v4t_thumb_thumb:
4609 case arm_stub_long_branch_v4t_thumb_arm:
4610 case arm_stub_short_branch_v4t_thumb_arm:
4611 case arm_stub_long_branch_any_arm_pic:
4612 case arm_stub_long_branch_any_thumb_pic:
4613 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4614 case arm_stub_long_branch_v4t_arm_thumb_pic:
4615 case arm_stub_long_branch_v4t_thumb_arm_pic:
4616 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4617 case arm_stub_long_branch_any_tls_pic:
4618 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4619 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4620 case arm_stub_a8_veneer_blx:
4621 return 4;
b38cadfb 4622
7a89b94e
NC		 4623 case arm_stub_long_branch_arm_nacl:
4624 case arm_stub_long_branch_arm_nacl_pic:
4625 return 16;
4626
4563a860
JB		 4627 default:
4628 abort (); /* Should be unreachable. */
4629 }
4630}
4631
4f4faa4d
TP		 4632/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4633 veneering (TRUE) or have their own symbol (FALSE). */
4634
4635static bfd_boolean
4636arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4637{
4638 if (stub_type >= max_stub_type)
4639 abort (); /* Should be unreachable. */
4640
4ba2ef8f
TP		 4641 switch (stub_type)
4642 {
4643 case arm_stub_cmse_branch_thumb_only:
4644 return TRUE;
4645
4646 default:
4647 return FALSE;
4648 }
4649
4650 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4651}
4652
d7c5bd02
TP		 4653/* Returns the padding needed for the dedicated section used stubs of type
4654 STUB_TYPE. */
4655
4656static int
4657arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4658{
4659 if (stub_type >= max_stub_type)
4660 abort (); /* Should be unreachable. */
4661
4ba2ef8f
TP		 4662 switch (stub_type)
4663 {
4664 case arm_stub_cmse_branch_thumb_only:
4665 return 32;
4666
4667 default:
4668 return 0;
4669 }
4670
4671 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4672}
4673
0955507f
TP		 4674/* If veneers of type STUB_TYPE should go in a dedicated output section,
4675 returns the address of the hash table field in HTAB holding the offset at
4676 which new veneers should be layed out in the stub section. */
4677
4678static bfd_vma*
4679arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
4680 enum elf32_arm_stub_type stub_type)
4681{
4682 switch (stub_type)
4683 {
4684 case arm_stub_cmse_branch_thumb_only:
4685 return &htab->new_cmse_stub_offset;
4686
4687 default:
4688 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4689 return NULL;
4690 }
4691}
4692
906e58ca
NC		 4693static bfd_boolean
4694arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4695 void * in_arg)
4696{
7a89b94e 4697#define MAXRELOCS 3
0955507f 4698 bfd_boolean removed_sg_veneer;
906e58ca 4699 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4700 struct elf32_arm_link_hash_table *globals;
906e58ca 4701 struct bfd_link_info *info;
906e58ca
NC		 4702 asection *stub_sec;
4703 bfd *stub_bfd;
906e58ca
NC		 4704 bfd_byte *loc;
4705 bfd_vma sym_value;
4706 int template_size;
4707 int size;
d3ce72d0 4708 const insn_sequence *template_sequence;
906e58ca 4709 int i;
48229727
JB		 4710 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4711 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4712 int nrelocs = 0;
0955507f 4713 int just_allocated = 0;
906e58ca
NC		 4714
4715 /* Massage our args to the form they really have. */
4716 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4717 info = (struct bfd_link_info *) in_arg;
4718
4719 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4720 if (globals == NULL)
4721 return FALSE;
906e58ca 4722
906e58ca
NC		 4723 stub_sec = stub_entry->stub_sec;
4724
4dfe6ac6 4725 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4726 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4727 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4728 return TRUE;
fe33d2fa 4729
0955507f
TP		 4730 /* Assign a slot at the end of section if none assigned yet. */
4731 if (stub_entry->stub_offset == (bfd_vma) -1)
4732 {
4733 stub_entry->stub_offset = stub_sec->size;
4734 just_allocated = 1;
4735 }
906e58ca
NC		 4736 loc = stub_sec->contents + stub_entry->stub_offset;
4737
4738 stub_bfd = stub_sec->owner;
4739
906e58ca
NC		 4740 /* This is the address of the stub destination. */
4741 sym_value = (stub_entry->target_value
4742 + stub_entry->target_section->output_offset
4743 + stub_entry->target_section->output_section->vma);
4744
d3ce72d0 4745 template_sequence = stub_entry->stub_template;
461a49ca 4746 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4747
4748 size = 0;
461a49ca 4749 for (i = 0; i < template_size; i++)
906e58ca 4750 {
d3ce72d0 4751 switch (template_sequence[i].type)
461a49ca
DJ		 4752 {
4753 case THUMB16_TYPE:
48229727 4754 {
d3ce72d0
NC		 4755 bfd_vma data = (bfd_vma) template_sequence[i].data;
4756 if (template_sequence[i].reloc_addend != 0)
48229727 4757 {
99059e56
RM		 4758 /* We've borrowed the reloc_addend field to mean we should
4759 insert a condition code into this (Thumb-1 branch)
4760 instruction. See THUMB16_BCOND_INSN. */
4761 BFD_ASSERT ((data & 0xff00) == 0xd000);
4762 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4763 }
fe33d2fa 4764 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4765 size += 2;
4766 }
461a49ca 4767 break;
906e58ca 4768
48229727 4769 case THUMB32_TYPE:
fe33d2fa
CL		 4770 bfd_put_16 (stub_bfd,
4771 (template_sequence[i].data >> 16) & 0xffff,
4772 loc + size);
4773 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4774 loc + size + 2);
99059e56
RM		 4775 if (template_sequence[i].r_type != R_ARM_NONE)
4776 {
4777 stub_reloc_idx[nrelocs] = i;
4778 stub_reloc_offset[nrelocs++] = size;
4779 }
4780 size += 4;
4781 break;
48229727 4782
461a49ca 4783 case ARM_TYPE:
fe33d2fa
CL		 4784 bfd_put_32 (stub_bfd, template_sequence[i].data,
4785 loc + size);
461a49ca
DJ		 4786 /* Handle cases where the target is encoded within the
4787 instruction. */
d3ce72d0 4788 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4789 {
48229727
JB		 4790 stub_reloc_idx[nrelocs] = i;
4791 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4792 }
4793 size += 4;
4794 break;
4795
4796 case DATA_TYPE:
d3ce72d0 4797 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4798 stub_reloc_idx[nrelocs] = i;
4799 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4800 size += 4;
4801 break;
4802
4803 default:
4804 BFD_FAIL ();
4805 return FALSE;
4806 }
906e58ca 4807 }
461a49ca 4808
0955507f
TP		 4809 if (just_allocated)
4810 stub_sec->size += size;
906e58ca 4811
461a49ca
DJ		 4812 /* Stub size has already been computed in arm_size_one_stub. Check
4813 consistency. */
4814 BFD_ASSERT (size == stub_entry->stub_size);
4815
906e58ca 4816 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4817 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4818 sym_value |= 1;
4819
0955507f
TP		 4820 /* Assume non empty slots have at least one and at most MAXRELOCS entries
4821 to relocate in each stub. */
4822 removed_sg_veneer =
4823 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
4824 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 4825
48229727 4826 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 4827 {
4828 Elf_Internal_Rela rel;
4829 bfd_boolean unresolved_reloc;
4830 char *error_message;
4831 bfd_vma points_to =
4832 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
4833
4834 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4835 rel.r_info = ELF32_R_INFO (0,
4836 template_sequence[stub_reloc_idx[i]].r_type);
4837 rel.r_addend = 0;
4838
4839 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4840 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4841 template should refer back to the instruction after the original
4842 branch. We use target_section as Cortex-A8 erratum workaround stubs
4843 are only generated when both source and target are in the same
4844 section. */
4845 points_to = stub_entry->target_section->output_section->vma
4846 + stub_entry->target_section->output_offset
4847 + stub_entry->source_value;
4848
4849 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4850 (template_sequence[stub_reloc_idx[i]].r_type),
4851 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
4852 points_to, info, stub_entry->target_section, "", STT_FUNC,
4853 stub_entry->branch_type,
4854 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4855 &error_message);
4856 }
906e58ca
NC		 4857
4858 return TRUE;
48229727 4859#undef MAXRELOCS
906e58ca
NC		 4860}
4861
48229727
JB		 4862/* Calculate the template, template size and instruction size for a stub.
4863 Return value is the instruction size. */
906e58ca 4864
48229727
JB		 4865static unsigned int
4866find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4867 const insn_sequence **stub_template,
4868 int *stub_template_size)
906e58ca 4869{
d3ce72d0 4870 const insn_sequence *template_sequence = NULL;
48229727
JB		 4871 int template_size = 0, i;
4872 unsigned int size;
906e58ca 4873
d3ce72d0 4874 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4875 if (stub_template)
4876 *stub_template = template_sequence;
4877
48229727 4878 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4879 if (stub_template_size)
4880 *stub_template_size = template_size;
906e58ca
NC		 4881
4882 size = 0;
461a49ca
DJ		 4883 for (i = 0; i < template_size; i++)
4884 {
d3ce72d0 4885 switch (template_sequence[i].type)
461a49ca
DJ		 4886 {
4887 case THUMB16_TYPE:
4888 size += 2;
4889 break;
4890
4891 case ARM_TYPE:
48229727 4892 case THUMB32_TYPE:
461a49ca
DJ		 4893 case DATA_TYPE:
4894 size += 4;
4895 break;
4896
4897 default:
4898 BFD_FAIL ();
2a229407 4899 return 0;
461a49ca
DJ		 4900 }
4901 }
4902
48229727
JB		 4903 return size;
4904}
4905
4906/* As above, but don't actually build the stub. Just bump offset so
4907 we know stub section sizes. */
4908
4909static bfd_boolean
4910arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4911 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4912{
4913 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4914 const insn_sequence *template_sequence;
48229727
JB		 4915 int template_size, size;
4916
4917 /* Massage our args to the form they really have. */
4918 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4919
4920 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4921 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4922
d3ce72d0 4923 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4924 &template_size);
4925
0955507f
TP		 4926 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
4927 if (stub_entry->stub_template_size)
4928 {
4929 stub_entry->stub_size = size;
4930 stub_entry->stub_template = template_sequence;
4931 stub_entry->stub_template_size = template_size;
4932 }
4933
4934 /* Already accounted for. */
4935 if (stub_entry->stub_offset != (bfd_vma) -1)
4936 return TRUE;
461a49ca 4937
906e58ca
NC		 4938 size = (size + 7) & ~7;
4939 stub_entry->stub_sec->size += size;
461a49ca 4940
906e58ca
NC		 4941 return TRUE;
4942}
4943
4944/* External entry points for sizing and building linker stubs. */
4945
4946/* Set up various things so that we can make a list of input sections
4947 for each output section included in the link. Returns -1 on error,
4948 0 when no stubs will be needed, and 1 on success. */
4949
4950int
4951elf32_arm_setup_section_lists (bfd *output_bfd,
4952 struct bfd_link_info *info)
4953{
4954 bfd *input_bfd;
4955 unsigned int bfd_count;
7292b3ac 4956 unsigned int top_id, top_index;
906e58ca
NC		 4957 asection *section;
4958 asection **input_list, **list;
4959 bfd_size_type amt;
4960 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4961
4dfe6ac6
NC		 4962 if (htab == NULL)
4963 return 0;
906e58ca
NC		 4964 if (! is_elf_hash_table (htab))
4965 return 0;
4966
4967 /* Count the number of input BFDs and find the top input section id. */
4968 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
4969 input_bfd != NULL;
c72f2fb2 4970 input_bfd = input_bfd->link.next)
906e58ca
NC		 4971 {
4972 bfd_count += 1;
4973 for (section = input_bfd->sections;
4974 section != NULL;
4975 section = section->next)
4976 {
4977 if (top_id < section->id)
4978 top_id = section->id;
4979 }
4980 }
4981 htab->bfd_count = bfd_count;
4982
4983 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 4984 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 4985 if (htab->stub_group == NULL)
4986 return -1;
fe33d2fa 4987 htab->top_id = top_id;
906e58ca
NC		 4988
4989 /* We can't use output_bfd->section_count here to find the top output
4990 section index as some sections may have been removed, and
4991 _bfd_strip_section_from_output doesn't renumber the indices. */
4992 for (section = output_bfd->sections, top_index = 0;
4993 section != NULL;
4994 section = section->next)
4995 {
4996 if (top_index < section->index)
4997 top_index = section->index;
4998 }
4999
5000 htab->top_index = top_index;
5001 amt = sizeof (asection *) * (top_index + 1);
21d799b5 5002 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 5003 htab->input_list = input_list;
5004 if (input_list == NULL)
5005 return -1;
5006
5007 /* For sections we aren't interested in, mark their entries with a
5008 value we can check later. */
5009 list = input_list + top_index;
5010 do
5011 *list = bfd_abs_section_ptr;
5012 while (list-- != input_list);
5013
5014 for (section = output_bfd->sections;
5015 section != NULL;
5016 section = section->next)
5017 {
5018 if ((section->flags & SEC_CODE) != 0)
5019 input_list[section->index] = NULL;
5020 }
5021
5022 return 1;
5023}
5024
5025/* The linker repeatedly calls this function for each input section,
5026 in the order that input sections are linked into output sections.
5027 Build lists of input sections to determine groupings between which
5028 we may insert linker stubs. */
5029
5030void
5031elf32_arm_next_input_section (struct bfd_link_info *info,
5032 asection *isec)
5033{
5034 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5035
4dfe6ac6
NC		 5036 if (htab == NULL)
5037 return;
5038
906e58ca
NC		 5039 if (isec->output_section->index <= htab->top_index)
5040 {
5041 asection **list = htab->input_list + isec->output_section->index;
5042
a7470592 5043 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5044 {
5045 /* Steal the link_sec pointer for our list. */
5046#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5047 /* This happens to make the list in reverse order,
07d72278 5048 which we reverse later. */
906e58ca
NC		 5049 PREV_SEC (isec) = *list;
5050 *list = isec;
5051 }
5052 }
5053}
5054
5055/* See whether we can group stub sections together. Grouping stub
5056 sections may result in fewer stubs. More importantly, we need to
07d72278 5057 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5058 .fini output sections respectively, because glibc splits the
5059 _init and _fini functions into multiple parts. Putting a stub in
5060 the middle of a function is not a good idea. */
5061
5062static void
5063group_sections (struct elf32_arm_link_hash_table *htab,
5064 bfd_size_type stub_group_size,
07d72278 5065 bfd_boolean stubs_always_after_branch)
906e58ca 5066{
07d72278 5067 asection **list = htab->input_list;
906e58ca
NC		 5068
5069 do
5070 {
5071 asection *tail = *list;
07d72278 5072 asection *head;
906e58ca
NC		 5073
5074 if (tail == bfd_abs_section_ptr)
5075 continue;
5076
07d72278
DJ		 5077 /* Reverse the list: we must avoid placing stubs at the
5078 beginning of the section because the beginning of the text
5079 section may be required for an interrupt vector in bare metal
5080 code. */
5081#define NEXT_SEC PREV_SEC
e780aef2
CL		 5082 head = NULL;
5083 while (tail != NULL)
99059e56
RM		 5084 {
5085 /* Pop from tail. */
5086 asection *item = tail;
5087 tail = PREV_SEC (item);
e780aef2 5088
99059e56
RM		 5089 /* Push on head. */
5090 NEXT_SEC (item) = head;
5091 head = item;
5092 }
07d72278
DJ		 5093
5094 while (head != NULL)
906e58ca
NC		 5095 {
5096 asection *curr;
07d72278 5097 asection *next;
e780aef2
CL		 5098 bfd_vma stub_group_start = head->output_offset;
5099 bfd_vma end_of_next;
906e58ca 5100
07d72278 5101 curr = head;
e780aef2 5102 while (NEXT_SEC (curr) != NULL)
8cd931b7 5103 {
e780aef2
CL		 5104 next = NEXT_SEC (curr);
5105 end_of_next = next->output_offset + next->size;
5106 if (end_of_next - stub_group_start >= stub_group_size)
5107 /* End of NEXT is too far from start, so stop. */
8cd931b7 5108 break;
e780aef2
CL		 5109 /* Add NEXT to the group. */
5110 curr = next;
8cd931b7 5111 }
906e58ca 5112
07d72278 5113 /* OK, the size from the start to the start of CURR is less
906e58ca 5114 than stub_group_size and thus can be handled by one stub
07d72278 5115 section. (Or the head section is itself larger than
906e58ca
NC		 5116 stub_group_size, in which case we may be toast.)
5117 We should really be keeping track of the total size of
5118 stubs added here, as stubs contribute to the final output
7fb9f789 5119 section size. */
906e58ca
NC		 5120 do
5121 {
07d72278 5122 next = NEXT_SEC (head);
906e58ca 5123 /* Set up this stub group. */
07d72278 5124 htab->stub_group[head->id].link_sec = curr;
906e58ca 5125 }
07d72278 5126 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5127
5128 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5129 bytes after the stub section can be handled by it too. */
5130 if (!stubs_always_after_branch)
906e58ca 5131 {
e780aef2
CL		 5132 stub_group_start = curr->output_offset + curr->size;
5133
8cd931b7 5134 while (next != NULL)
906e58ca 5135 {
e780aef2
CL		 5136 end_of_next = next->output_offset + next->size;
5137 if (end_of_next - stub_group_start >= stub_group_size)
5138 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5139 break;
e780aef2 5140 /* Add NEXT to the stub group. */
07d72278
DJ		 5141 head = next;
5142 next = NEXT_SEC (head);
5143 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5144 }
5145 }
07d72278 5146 head = next;
906e58ca
NC		 5147 }
5148 }
07d72278 5149 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5150
5151 free (htab->input_list);
5152#undef PREV_SEC
07d72278 5153#undef NEXT_SEC
906e58ca
NC		 5154}
5155
48229727
JB		 5156/* Comparison function for sorting/searching relocations relating to Cortex-A8
5157 erratum fix. */
5158
5159static int
5160a8_reloc_compare (const void *a, const void *b)
5161{
21d799b5
NC		 5162 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5163 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5164
5165 if (ra->from < rb->from)
5166 return -1;
5167 else if (ra->from > rb->from)
5168 return 1;
5169 else
5170 return 0;
5171}
5172
5173static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5174 const char *, char **);
5175
5176/* Helper function to scan code for sequences which might trigger the Cortex-A8
5177 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5178 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5179 otherwise. */
5180
81694485
NC		 5181static bfd_boolean
5182cortex_a8_erratum_scan (bfd *input_bfd,
5183 struct bfd_link_info *info,
48229727
JB		 5184 struct a8_erratum_fix **a8_fixes_p,
5185 unsigned int *num_a8_fixes_p,
5186 unsigned int *a8_fix_table_size_p,
5187 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5188 unsigned int num_a8_relocs,
5189 unsigned prev_num_a8_fixes,
5190 bfd_boolean *stub_changed_p)
48229727
JB		 5191{
5192 asection *section;
5193 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5194 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5195 unsigned int num_a8_fixes = *num_a8_fixes_p;
5196 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5197
4dfe6ac6
NC		 5198 if (htab == NULL)
5199 return FALSE;
5200
48229727
JB		 5201 for (section = input_bfd->sections;
5202 section != NULL;
5203 section = section->next)
5204 {
5205 bfd_byte *contents = NULL;
5206 struct _arm_elf_section_data *sec_data;
5207 unsigned int span;
5208 bfd_vma base_vma;
5209
5210 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5211 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5212 || (section->flags & SEC_EXCLUDE) != 0
5213 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5214 || (section->output_section == bfd_abs_section_ptr))
5215 continue;
48229727
JB		 5216
5217 base_vma = section->output_section->vma + section->output_offset;
5218
5219 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5220 contents = elf_section_data (section)->this_hdr.contents;
48229727 5221 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5222 return TRUE;
48229727
JB		 5223
5224 sec_data = elf32_arm_section_data (section);
5225
5226 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5227 {
5228 unsigned int span_start = sec_data->map[span].vma;
5229 unsigned int span_end = (span == sec_data->mapcount - 1)
5230 ? section->size : sec_data->map[span + 1].vma;
5231 unsigned int i;
5232 char span_type = sec_data->map[span].type;
5233 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5234
5235 if (span_type != 't')
5236 continue;
5237
5238 /* Span is entirely within a single 4KB region: skip scanning. */
5239 if (((base_vma + span_start) & ~0xfff)
48229727 5240 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5241 continue;
5242
5243 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5244
5245 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5246 * The branch target is in the same 4KB region as the
5247 first half of the branch.
5248 * The instruction before the branch is a 32-bit
5249 length non-branch instruction. */
5250 for (i = span_start; i < span_end;)
5251 {
5252 unsigned int insn = bfd_getl16 (&contents[i]);
5253 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5254 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5255
99059e56
RM		 5256 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5257 insn_32bit = TRUE;
48229727
JB		 5258
5259 if (insn_32bit)
99059e56
RM		 5260 {
5261 /* Load the rest of the insn (in manual-friendly order). */
5262 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5263
5264 /* Encoding T4: B<c>.W. */
5265 is_b = (insn & 0xf800d000) == 0xf0009000;
5266 /* Encoding T1: BL<c>.W. */
5267 is_bl = (insn & 0xf800d000) == 0xf000d000;
5268 /* Encoding T2: BLX<c>.W. */
5269 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5270 /* Encoding T3: B<c>.W (not permitted in IT block). */
5271 is_bcc = (insn & 0xf800d000) == 0xf0008000
5272 && (insn & 0x07f00000) != 0x03800000;
5273 }
5274
5275 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5276
99059e56 5277 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5278 && insn_32bit
5279 && is_32bit_branch
5280 && last_was_32bit
5281 && ! last_was_branch)
99059e56
RM		 5282 {
5283 bfd_signed_vma offset = 0;
5284 bfd_boolean force_target_arm = FALSE;
48229727 5285 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5286 bfd_vma target;
5287 enum elf32_arm_stub_type stub_type = arm_stub_none;
5288 struct a8_erratum_reloc key, *found;
5289 bfd_boolean use_plt = FALSE;
48229727 5290
99059e56
RM		 5291 key.from = base_vma + i;
5292 found = (struct a8_erratum_reloc *)
5293 bsearch (&key, a8_relocs, num_a8_relocs,
5294 sizeof (struct a8_erratum_reloc),
5295 &a8_reloc_compare);
48229727
JB		 5296
5297 if (found)
5298 {
5299 char *error_message = NULL;
5300 struct elf_link_hash_entry *entry;
5301
5302 /* We don't care about the error returned from this
99059e56 5303 function, only if there is glue or not. */
48229727
JB		 5304 entry = find_thumb_glue (info, found->sym_name,
5305 &error_message);
5306
5307 if (entry)
5308 found->non_a8_stub = TRUE;
5309
92750f34 5310 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5311 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5312 && found->hash->root.plt.offset != (bfd_vma) -1)
5313 use_plt = TRUE;
5314
5315 if (found->r_type == R_ARM_THM_CALL)
5316 {
35fc36a8
RS		 5317 if (found->branch_type == ST_BRANCH_TO_ARM
5318 || use_plt)
92750f34
DJ		 5319 force_target_arm = TRUE;
5320 else
5321 force_target_thumb = TRUE;
5322 }
48229727
JB		 5323 }
5324
99059e56 5325 /* Check if we have an offending branch instruction. */
48229727
JB		 5326
5327 if (found && found->non_a8_stub)
5328 /* We've already made a stub for this instruction, e.g.
5329 it's a long branch or a Thumb->ARM stub. Assume that
5330 stub will suffice to work around the A8 erratum (see
5331 setting of always_after_branch above). */
5332 ;
99059e56
RM		 5333 else if (is_bcc)
5334 {
5335 offset = (insn & 0x7ff) << 1;
5336 offset |= (insn & 0x3f0000) >> 4;
5337 offset |= (insn & 0x2000) ? 0x40000 : 0;
5338 offset |= (insn & 0x800) ? 0x80000 : 0;
5339 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5340 if (offset & 0x100000)
5341 offset |= ~ ((bfd_signed_vma) 0xfffff);
5342 stub_type = arm_stub_a8_veneer_b_cond;
5343 }
5344 else if (is_b || is_bl || is_blx)
5345 {
5346 int s = (insn & 0x4000000) != 0;
5347 int j1 = (insn & 0x2000) != 0;
5348 int j2 = (insn & 0x800) != 0;
5349 int i1 = !(j1 ^ s);
5350 int i2 = !(j2 ^ s);
5351
5352 offset = (insn & 0x7ff) << 1;
5353 offset |= (insn & 0x3ff0000) >> 4;
5354 offset |= i2 << 22;
5355 offset |= i1 << 23;
5356 offset |= s << 24;
5357 if (offset & 0x1000000)
5358 offset |= ~ ((bfd_signed_vma) 0xffffff);
5359
5360 if (is_blx)
5361 offset &= ~ ((bfd_signed_vma) 3);
5362
5363 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5364 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5365 }
5366
5367 if (stub_type != arm_stub_none)
5368 {
5369 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5370
5371 /* The original instruction is a BL, but the target is
99059e56 5372 an ARM instruction. If we were not making a stub,
48229727
JB		 5373 the BL would have been converted to a BLX. Use the
5374 BLX stub instead in that case. */
5375 if (htab->use_blx && force_target_arm
5376 && stub_type == arm_stub_a8_veneer_bl)
5377 {
5378 stub_type = arm_stub_a8_veneer_blx;
5379 is_blx = TRUE;
5380 is_bl = FALSE;
5381 }
5382 /* Conversely, if the original instruction was
5383 BLX but the target is Thumb mode, use the BL
5384 stub. */
5385 else if (force_target_thumb
5386 && stub_type == arm_stub_a8_veneer_blx)
5387 {
5388 stub_type = arm_stub_a8_veneer_bl;
5389 is_blx = FALSE;
5390 is_bl = TRUE;
5391 }
5392
99059e56
RM		 5393 if (is_blx)
5394 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5395
99059e56
RM		 5396 /* If we found a relocation, use the proper destination,
5397 not the offset in the (unrelocated) instruction.
48229727
JB		 5398 Note this is always done if we switched the stub type
5399 above. */
99059e56
RM		 5400 if (found)
5401 offset =
81694485 5402 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5403
99059e56
RM		 5404 /* If the stub will use a Thumb-mode branch to a
5405 PLT target, redirect it to the preceding Thumb
5406 entry point. */
5407 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5408 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5409
99059e56 5410 target = pc_for_insn + offset;
48229727 5411
99059e56
RM		 5412 /* The BLX stub is ARM-mode code. Adjust the offset to
5413 take the different PC value (+8 instead of +4) into
48229727 5414 account. */
99059e56
RM		 5415 if (stub_type == arm_stub_a8_veneer_blx)
5416 offset += 4;
5417
5418 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5419 {
5420 char *stub_name = NULL;
5421
5422 if (num_a8_fixes == a8_fix_table_size)
5423 {
5424 a8_fix_table_size *= 2;
5425 a8_fixes = (struct a8_erratum_fix *)
5426 bfd_realloc (a8_fixes,
5427 sizeof (struct a8_erratum_fix)
5428 * a8_fix_table_size);
5429 }
48229727 5430
eb7c4339
NS		 5431 if (num_a8_fixes < prev_num_a8_fixes)
5432 {
5433 /* If we're doing a subsequent scan,
5434 check if we've found the same fix as
5435 before, and try and reuse the stub
5436 name. */
5437 stub_name = a8_fixes[num_a8_fixes].stub_name;
5438 if ((a8_fixes[num_a8_fixes].section != section)
5439 || (a8_fixes[num_a8_fixes].offset != i))
5440 {
5441 free (stub_name);
5442 stub_name = NULL;
5443 *stub_changed_p = TRUE;
5444 }
5445 }
5446
5447 if (!stub_name)
5448 {
21d799b5 5449 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5450 if (stub_name != NULL)
5451 sprintf (stub_name, "%x:%x", section->id, i);
5452 }
48229727 5453
99059e56
RM		 5454 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5455 a8_fixes[num_a8_fixes].section = section;
5456 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5457 a8_fixes[num_a8_fixes].target_offset =
5458 target - base_vma;
99059e56
RM		 5459 a8_fixes[num_a8_fixes].orig_insn = insn;
5460 a8_fixes[num_a8_fixes].stub_name = stub_name;
5461 a8_fixes[num_a8_fixes].stub_type = stub_type;
5462 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5463 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5464
99059e56
RM		 5465 num_a8_fixes++;
5466 }
5467 }
5468 }
48229727 5469
99059e56
RM		 5470 i += insn_32bit ? 4 : 2;
5471 last_was_32bit = insn_32bit;
48229727 5472 last_was_branch = is_32bit_branch;
99059e56
RM		 5473 }
5474 }
48229727
JB		 5475
5476 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5477 free (contents);
48229727 5478 }
fe33d2fa 5479
48229727
JB		 5480 *a8_fixes_p = a8_fixes;
5481 *num_a8_fixes_p = num_a8_fixes;
5482 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5483
81694485 5484 return FALSE;
48229727
JB		 5485}
5486
b715f643
TP		 5487/* Create or update a stub entry depending on whether the stub can already be
5488 found in HTAB. The stub is identified by:
5489 - its type STUB_TYPE
5490 - its source branch (note that several can share the same stub) whose
5491 section and relocation (if any) are given by SECTION and IRELA
5492 respectively
5493 - its target symbol whose input section, hash, name, value and branch type
5494 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5495 respectively
5496
5497 If found, the value of the stub's target symbol is updated from SYM_VALUE
5498 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5499 TRUE and the stub entry is initialized.
5500
0955507f
TP		 5501 Returns the stub that was created or updated, or NULL if an error
5502 occurred. */
b715f643 5503
0955507f 5504static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5505elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5506 enum elf32_arm_stub_type stub_type, asection *section,
5507 Elf_Internal_Rela *irela, asection *sym_sec,
5508 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5509 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5510 bfd_boolean *new_stub)
5511{
5512 const asection *id_sec;
5513 char *stub_name;
5514 struct elf32_arm_stub_hash_entry *stub_entry;
5515 unsigned int r_type;
4f4faa4d 5516 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5517
5518 BFD_ASSERT (stub_type != arm_stub_none);
5519 *new_stub = FALSE;
5520
4f4faa4d
TP		 5521 if (sym_claimed)
5522 stub_name = sym_name;
5523 else
5524 {
5525 BFD_ASSERT (irela);
5526 BFD_ASSERT (section);
c2abbbeb 5527 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5528
4f4faa4d
TP		 5529 /* Support for grouping stub sections. */
5530 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5531
4f4faa4d
TP		 5532 /* Get the name of this stub. */
5533 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5534 stub_type);
5535 if (!stub_name)
0955507f 5536 return NULL;
4f4faa4d 5537 }
b715f643
TP		 5538
5539 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5540 FALSE);
5541 /* The proper stub has already been created, just update its value. */
5542 if (stub_entry != NULL)
5543 {
4f4faa4d
TP		 5544 if (!sym_claimed)
5545 free (stub_name);
b715f643 5546 stub_entry->target_value = sym_value;
0955507f 5547 return stub_entry;
b715f643
TP		 5548 }
5549
daa4adae 5550 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5551 if (stub_entry == NULL)
5552 {
4f4faa4d
TP		 5553 if (!sym_claimed)
5554 free (stub_name);
0955507f 5555 return NULL;
b715f643
TP		 5556 }
5557
5558 stub_entry->target_value = sym_value;
5559 stub_entry->target_section = sym_sec;
5560 stub_entry->stub_type = stub_type;
5561 stub_entry->h = hash;
5562 stub_entry->branch_type = branch_type;
5563
4f4faa4d
TP		 5564 if (sym_claimed)
5565 stub_entry->output_name = sym_name;
5566 else
b715f643 5567 {
4f4faa4d
TP		 5568 if (sym_name == NULL)
5569 sym_name = "unnamed";
5570 stub_entry->output_name = (char *)
5571 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5572 + strlen (sym_name));
5573 if (stub_entry->output_name == NULL)
5574 {
5575 free (stub_name);
0955507f 5576 return NULL;
4f4faa4d 5577 }
b715f643 5578
4f4faa4d
TP		 5579 /* For historical reasons, use the existing names for ARM-to-Thumb and
5580 Thumb-to-ARM stubs. */
5581 r_type = ELF32_R_TYPE (irela->r_info);
5582 if ((r_type == (unsigned int) R_ARM_THM_CALL
5583 || r_type == (unsigned int) R_ARM_THM_JUMP24
5584 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5585 && branch_type == ST_BRANCH_TO_ARM)
5586 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5587 else if ((r_type == (unsigned int) R_ARM_CALL
5588 || r_type == (unsigned int) R_ARM_JUMP24)
5589 && branch_type == ST_BRANCH_TO_THUMB)
5590 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5591 else
5592 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5593 }
b715f643
TP		 5594
5595 *new_stub = TRUE;
0955507f 5596 return stub_entry;
b715f643
TP		 5597}
5598
4ba2ef8f
TP		 5599/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5600 gateway veneer to transition from non secure to secure state and create them
5601 accordingly.
5602
5603 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5604 defines the conditions that govern Secure Gateway veneer creation for a
5605 given symbol <SYM> as follows:
5606 - it has function type
5607 - it has non local binding
5608 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5609 same type, binding and value as <SYM> (called normal symbol).
5610 An entry function can handle secure state transition itself in which case
5611 its special symbol would have a different value from the normal symbol.
5612
5613 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5614 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5615 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5616 created.
4ba2ef8f 5617
0955507f 5618 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5619
5620static bfd_boolean
5621cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5622 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5623 int *cmse_stub_created)
4ba2ef8f
TP		 5624{
5625 const struct elf_backend_data *bed;
5626 Elf_Internal_Shdr *symtab_hdr;
5627 unsigned i, j, sym_count, ext_start;
5628 Elf_Internal_Sym *cmse_sym, *local_syms;
5629 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5630 enum arm_st_branch_type branch_type;
5631 char *sym_name, *lsym_name;
5632 bfd_vma sym_value;
5633 asection *section;
0955507f
TP		 5634 struct elf32_arm_stub_hash_entry *stub_entry;
5635 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5636
5637 bed = get_elf_backend_data (input_bfd);
5638 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5639 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5640 ext_start = symtab_hdr->sh_info;
5641 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5642 && out_attr[Tag_CPU_arch_profile].i == 'M');
5643
5644 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5645 if (local_syms == NULL)
5646 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5647 symtab_hdr->sh_info, 0, NULL, NULL,
5648 NULL);
5649 if (symtab_hdr->sh_info && local_syms == NULL)
5650 return FALSE;
5651
5652 /* Scan symbols. */
5653 for (i = 0; i < sym_count; i++)
5654 {
5655 cmse_invalid = FALSE;
5656
5657 if (i < ext_start)
5658 {
5659 cmse_sym = &local_syms[i];
5660 /* Not a special symbol. */
5661 if (!ARM_GET_SYM_CMSE_SPCL (cmse_sym->st_target_internal))
5662 continue;
5663 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5664 symtab_hdr->sh_link,
5665 cmse_sym->st_name);
5666 /* Special symbol with local binding. */
5667 cmse_invalid = TRUE;
5668 }
5669 else
5670 {
5671 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5672 sym_name = (char *) cmse_hash->root.root.root.string;
5673
5674 /* Not a special symbol. */
5675 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
5676 continue;
5677
5678 /* Special symbol has incorrect binding or type. */
5679 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5680 && cmse_hash->root.root.type != bfd_link_hash_defweak)
5681 || cmse_hash->root.type != STT_FUNC)
5682 cmse_invalid = TRUE;
5683 }
5684
5685 if (!is_v8m)
5686 {
90b6238f
AM		 5687 _bfd_error_handler (_("%pB: special symbol `%s' only allowed for "
5688 "ARMv8-M architecture or later"),
4eca0228 5689 input_bfd, sym_name);
4ba2ef8f
TP		 5690 is_v8m = TRUE; /* Avoid multiple warning. */
5691 ret = FALSE;
5692 }
5693
5694 if (cmse_invalid)
5695 {
90b6238f
AM		 5696 _bfd_error_handler (_("%pB: invalid special symbol `%s'; it must be"
5697 " a global or weak function symbol"),
4eca0228 5698 input_bfd, sym_name);
4ba2ef8f
TP		 5699 ret = FALSE;
5700 if (i < ext_start)
5701 continue;
5702 }
5703
5704 sym_name += strlen (CMSE_PREFIX);
5705 hash = (struct elf32_arm_link_hash_entry *)
5706 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5707
5708 /* No associated normal symbol or it is neither global nor weak. */
5709 if (!hash
5710 || (hash->root.root.type != bfd_link_hash_defined
5711 && hash->root.root.type != bfd_link_hash_defweak)
5712 || hash->root.type != STT_FUNC)
5713 {
5714 /* Initialize here to avoid warning about use of possibly
5715 uninitialized variable. */
5716 j = 0;
5717
5718 if (!hash)
5719 {
5720 /* Searching for a normal symbol with local binding. */
5721 for (; j < ext_start; j++)
5722 {
5723 lsym_name =
5724 bfd_elf_string_from_elf_section (input_bfd,
5725 symtab_hdr->sh_link,
5726 local_syms[j].st_name);
5727 if (!strcmp (sym_name, lsym_name))
5728 break;
5729 }
5730 }
5731
5732 if (hash || j < ext_start)
5733 {
4eca0228 5734 _bfd_error_handler
90b6238f
AM		 5735 (_("%pB: invalid standard symbol `%s'; it must be "
5736 "a global or weak function symbol"),
5737 input_bfd, sym_name);
4ba2ef8f
TP		 5738 }
5739 else
4eca0228 5740 _bfd_error_handler
90b6238f 5741 (_("%pB: absent standard symbol `%s'"), input_bfd, sym_name);
4ba2ef8f
TP		 5742 ret = FALSE;
5743 if (!hash)
5744 continue;
5745 }
5746
5747 sym_value = hash->root.root.u.def.value;
5748 section = hash->root.root.u.def.section;
5749
5750 if (cmse_hash->root.root.u.def.section != section)
5751 {
4eca0228 5752 _bfd_error_handler
90b6238f 5753 (_("%pB: `%s' and its special symbol are in different sections"),
4ba2ef8f
TP		 5754 input_bfd, sym_name);
5755 ret = FALSE;
5756 }
5757 if (cmse_hash->root.root.u.def.value != sym_value)
5758 continue; /* Ignore: could be an entry function starting with SG. */
5759
5760 /* If this section is a link-once section that will be discarded, then
5761 don't create any stubs. */
5762 if (section->output_section == NULL)
5763 {
4eca0228 5764 _bfd_error_handler
90b6238f 5765 (_("%pB: entry function `%s' not output"), input_bfd, sym_name);
4ba2ef8f
TP		 5766 continue;
5767 }
5768
5769 if (hash->root.size == 0)
5770 {
4eca0228 5771 _bfd_error_handler
90b6238f 5772 (_("%pB: entry function `%s' is empty"), input_bfd, sym_name);
4ba2ef8f
TP		 5773 ret = FALSE;
5774 }
5775
5776 if (!ret)
5777 continue;
5778 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 5779 stub_entry
4ba2ef8f
TP		 5780 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5781 NULL, NULL, section, hash, sym_name,
5782 sym_value, branch_type, &new_stub);
5783
0955507f 5784 if (stub_entry == NULL)
4ba2ef8f
TP		 5785 ret = FALSE;
5786 else
5787 {
5788 BFD_ASSERT (new_stub);
0955507f 5789 (*cmse_stub_created)++;
4ba2ef8f
TP		 5790 }
5791 }
5792
5793 if (!symtab_hdr->contents)
5794 free (local_syms);
5795 return ret;
5796}
5797
0955507f
TP		 5798/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
5799 code entry function, ie can be called from non secure code without using a
5800 veneer. */
5801
5802static bfd_boolean
5803cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
5804{
42484486 5805 bfd_byte contents[4];
0955507f
TP		 5806 uint32_t first_insn;
5807 asection *section;
5808 file_ptr offset;
5809 bfd *abfd;
5810
5811 /* Defined symbol of function type. */
5812 if (hash->root.root.type != bfd_link_hash_defined
5813 && hash->root.root.type != bfd_link_hash_defweak)
5814 return FALSE;
5815 if (hash->root.type != STT_FUNC)
5816 return FALSE;
5817
5818 /* Read first instruction. */
5819 section = hash->root.root.u.def.section;
5820 abfd = section->owner;
5821 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 5822 if (!bfd_get_section_contents (abfd, section, contents, offset,
5823 sizeof (contents)))
0955507f
TP		 5824 return FALSE;
5825
42484486
TP		 5826 first_insn = bfd_get_32 (abfd, contents);
5827
5828 /* Starts by SG instruction. */
0955507f
TP		 5829 return first_insn == 0xe97fe97f;
5830}
5831
5832/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
5833 secure gateway veneers (ie. the veneers was not in the input import library)
5834 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
5835
5836static bfd_boolean
5837arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
5838{
5839 struct elf32_arm_stub_hash_entry *stub_entry;
5840 struct bfd_link_info *info;
5841
5842 /* Massage our args to the form they really have. */
5843 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5844 info = (struct bfd_link_info *) gen_info;
5845
5846 if (info->out_implib_bfd)
5847 return TRUE;
5848
5849 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
5850 return TRUE;
5851
5852 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 5853 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 5854
5855 return TRUE;
5856}
5857
5858/* Set offset of each secure gateway veneers so that its address remain
5859 identical to the one in the input import library referred by
5860 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
5861 (present in input import library but absent from the executable being
5862 linked) or if new veneers appeared and there is no output import library
5863 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
5864 number of secure gateway veneers found in the input import library.
5865
5866 The function returns whether an error occurred. If no error occurred,
5867 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
5868 and this function and HTAB->new_cmse_stub_offset is set to the biggest
5869 veneer observed set for new veneers to be layed out after. */
5870
5871static bfd_boolean
5872set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
5873 struct elf32_arm_link_hash_table *htab,
5874 int *cmse_stub_created)
5875{
5876 long symsize;
5877 char *sym_name;
5878 flagword flags;
5879 long i, symcount;
5880 bfd *in_implib_bfd;
5881 asection *stub_out_sec;
5882 bfd_boolean ret = TRUE;
5883 Elf_Internal_Sym *intsym;
5884 const char *out_sec_name;
5885 bfd_size_type cmse_stub_size;
5886 asymbol **sympp = NULL, *sym;
5887 struct elf32_arm_link_hash_entry *hash;
5888 const insn_sequence *cmse_stub_template;
5889 struct elf32_arm_stub_hash_entry *stub_entry;
5890 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
5891 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
5892 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
5893
5894 /* No input secure gateway import library. */
5895 if (!htab->in_implib_bfd)
5896 return TRUE;
5897
5898 in_implib_bfd = htab->in_implib_bfd;
5899 if (!htab->cmse_implib)
5900 {
871b3ab2 5901 _bfd_error_handler (_("%pB: --in-implib only supported for Secure "
90b6238f 5902 "Gateway import libraries"), in_implib_bfd);
0955507f
TP		 5903 return FALSE;
5904 }
5905
5906 /* Get symbol table size. */
5907 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
5908 if (symsize < 0)
5909 return FALSE;
5910
5911 /* Read in the input secure gateway import library's symbol table. */
5912 sympp = (asymbol **) xmalloc (symsize);
5913 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
5914 if (symcount < 0)
5915 {
5916 ret = FALSE;
5917 goto free_sym_buf;
5918 }
5919
5920 htab->new_cmse_stub_offset = 0;
5921 cmse_stub_size =
5922 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
5923 &cmse_stub_template,
5924 &cmse_stub_template_size);
5925 out_sec_name =
5926 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
5927 stub_out_sec =
5928 bfd_get_section_by_name (htab->obfd, out_sec_name);
5929 if (stub_out_sec != NULL)
5930 cmse_stub_sec_vma = stub_out_sec->vma;
5931
5932 /* Set addresses of veneers mentionned in input secure gateway import
5933 library's symbol table. */
5934 for (i = 0; i < symcount; i++)
5935 {
5936 sym = sympp[i];
5937 flags = sym->flags;
5938 sym_name = (char *) bfd_asymbol_name (sym);
5939 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
5940
5941 if (sym->section != bfd_abs_section_ptr
5942 || !(flags & (BSF_GLOBAL | BSF_WEAK))
5943 || (flags & BSF_FUNCTION) != BSF_FUNCTION
5944 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
5945 != ST_BRANCH_TO_THUMB))
5946 {
90b6238f
AM		 5947 _bfd_error_handler (_("%pB: invalid import library entry: `%s'; "
5948 "symbol should be absolute, global and "
5949 "refer to Thumb functions"),
4eca0228 5950 in_implib_bfd, sym_name);
0955507f
TP		 5951 ret = FALSE;
5952 continue;
5953 }
5954
5955 veneer_value = bfd_asymbol_value (sym);
5956 stub_offset = veneer_value - cmse_stub_sec_vma;
5957 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
5958 FALSE, FALSE);
5959 hash = (struct elf32_arm_link_hash_entry *)
5960 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5961
5962 /* Stub entry should have been created by cmse_scan or the symbol be of
5963 a secure function callable from non secure code. */
5964 if (!stub_entry && !hash)
5965 {
5966 bfd_boolean new_stub;
5967
4eca0228 5968 _bfd_error_handler
90b6238f 5969 (_("entry function `%s' disappeared from secure code"), sym_name);
0955507f
TP		 5970 hash = (struct elf32_arm_link_hash_entry *)
5971 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
5972 stub_entry
5973 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5974 NULL, NULL, bfd_abs_section_ptr, hash,
5975 sym_name, veneer_value,
5976 ST_BRANCH_TO_THUMB, &new_stub);
5977 if (stub_entry == NULL)
5978 ret = FALSE;
5979 else
5980 {
5981 BFD_ASSERT (new_stub);
5982 new_cmse_stubs_created++;
5983 (*cmse_stub_created)++;
5984 }
5985 stub_entry->stub_template_size = stub_entry->stub_size = 0;
5986 stub_entry->stub_offset = stub_offset;
5987 }
5988 /* Symbol found is not callable from non secure code. */
5989 else if (!stub_entry)
5990 {
5991 if (!cmse_entry_fct_p (hash))
5992 {
90b6238f 5993 _bfd_error_handler (_("`%s' refers to a non entry function"),
4eca0228 5994 sym_name);
0955507f
TP		 5995 ret = FALSE;
5996 }
5997 continue;
5998 }
5999 else
6000 {
6001 /* Only stubs for SG veneers should have been created. */
6002 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
6003
6004 /* Check visibility hasn't changed. */
6005 if (!!(flags & BSF_GLOBAL)
6006 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6007 _bfd_error_handler
90b6238f 6008 (_("%pB: visibility of symbol `%s' has changed"), in_implib_bfd,
0955507f
TP		 6009 sym_name);
6010
6011 stub_entry->stub_offset = stub_offset;
6012 }
6013
6014 /* Size should match that of a SG veneer. */
6015 if (intsym->st_size != cmse_stub_size)
6016 {
90b6238f 6017 _bfd_error_handler (_("%pB: incorrect size for symbol `%s'"),
4eca0228 6018 in_implib_bfd, sym_name);
0955507f
TP		 6019 ret = FALSE;
6020 }
6021
6022 /* Previous veneer address is before current SG veneer section. */
6023 if (veneer_value < cmse_stub_sec_vma)
6024 {
6025 /* Avoid offset underflow. */
6026 if (stub_entry)
6027 stub_entry->stub_offset = 0;
6028 stub_offset = 0;
6029 ret = FALSE;
6030 }
6031
6032 /* Complain if stub offset not a multiple of stub size. */
6033 if (stub_offset % cmse_stub_size)
6034 {
4eca0228 6035 _bfd_error_handler
90b6238f
AM		 6036 (_("offset of veneer for entry function `%s' not a multiple of "
6037 "its size"), sym_name);
0955507f
TP		 6038 ret = FALSE;
6039 }
6040
6041 if (!ret)
6042 continue;
6043
6044 new_cmse_stubs_created--;
6045 if (veneer_value < cmse_stub_array_start)
6046 cmse_stub_array_start = veneer_value;
6047 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6048 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6049 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6050 }
6051
6052 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6053 {
6054 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6055 _bfd_error_handler
0955507f
TP		 6056 (_("new entry function(s) introduced but no output import library "
6057 "specified:"));
6058 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6059 }
6060
6061 if (cmse_stub_array_start != cmse_stub_sec_vma)
6062 {
4eca0228 6063 _bfd_error_handler
90b6238f 6064 (_("start address of `%s' is different from previous link"),
0955507f
TP		 6065 out_sec_name);
6066 ret = FALSE;
6067 }
6068
6069free_sym_buf:
6070 free (sympp);
6071 return ret;
6072}
6073
906e58ca
NC		 6074/* Determine and set the size of the stub section for a final link.
6075
6076 The basic idea here is to examine all the relocations looking for
6077 PC-relative calls to a target that is unreachable with a "bl"
6078 instruction. */
6079
6080bfd_boolean
6081elf32_arm_size_stubs (bfd *output_bfd,
6082 bfd *stub_bfd,
6083 struct bfd_link_info *info,
6084 bfd_signed_vma group_size,
7a89b94e 6085 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6086 asection *,
7a89b94e 6087 unsigned int),
906e58ca
NC		 6088 void (*layout_sections_again) (void))
6089{
0955507f 6090 bfd_boolean ret = TRUE;
4ba2ef8f 6091 obj_attribute *out_attr;
0955507f 6092 int cmse_stub_created = 0;
906e58ca 6093 bfd_size_type stub_group_size;
4ba2ef8f 6094 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6095 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6096 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6097 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6098 struct a8_erratum_reloc *a8_relocs = NULL;
6099 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6100
4dfe6ac6
NC		 6101 if (htab == NULL)
6102 return FALSE;
6103
48229727
JB		 6104 if (htab->fix_cortex_a8)
6105 {
21d799b5 6106 a8_fixes = (struct a8_erratum_fix *)
99059e56 6107 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6108 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6109 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6110 }
906e58ca
NC		 6111
6112 /* Propagate mach to stub bfd, because it may not have been
6113 finalized when we created stub_bfd. */
6114 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6115 bfd_get_mach (output_bfd));
6116
6117 /* Stash our params away. */
6118 htab->stub_bfd = stub_bfd;
6119 htab->add_stub_section = add_stub_section;
6120 htab->layout_sections_again = layout_sections_again;
07d72278 6121 stubs_always_after_branch = group_size < 0;
48229727 6122
4ba2ef8f
TP		 6123 out_attr = elf_known_obj_attributes_proc (output_bfd);
6124 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6125
48229727
JB		 6126 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6127 as the first half of a 32-bit branch straddling two 4K pages. This is a
6128 crude way of enforcing that. */
6129 if (htab->fix_cortex_a8)
6130 stubs_always_after_branch = 1;
6131
906e58ca
NC		 6132 if (group_size < 0)
6133 stub_group_size = -group_size;
6134 else
6135 stub_group_size = group_size;
6136
6137 if (stub_group_size == 1)
6138 {
6139 /* Default values. */
6140 /* Thumb branch range is +-4MB has to be used as the default
6141 maximum size (a given section can contain both ARM and Thumb
6142 code, so the worst case has to be taken into account).
6143
6144 This value is 24K less than that, which allows for 2025
6145 12-byte stubs. If we exceed that, then we will fail to link.
6146 The user will have to relink with an explicit group size
6147 option. */
6148 stub_group_size = 4170000;
6149 }
6150
07d72278 6151 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6152
3ae046cc
NS		 6153 /* If we're applying the cortex A8 fix, we need to determine the
6154 program header size now, because we cannot change it later --
6155 that could alter section placements. Notice the A8 erratum fix
6156 ends up requiring the section addresses to remain unchanged
6157 modulo the page size. That's something we cannot represent
6158 inside BFD, and we don't want to force the section alignment to
6159 be the page size. */
6160 if (htab->fix_cortex_a8)
6161 (*htab->layout_sections_again) ();
6162
906e58ca
NC		 6163 while (1)
6164 {
6165 bfd *input_bfd;
6166 unsigned int bfd_indx;
6167 asection *stub_sec;
d7c5bd02 6168 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6169 bfd_boolean stub_changed = FALSE;
6170 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6171
48229727 6172 num_a8_fixes = 0;
906e58ca
NC		 6173 for (input_bfd = info->input_bfds, bfd_indx = 0;
6174 input_bfd != NULL;
c72f2fb2 6175 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6176 {
6177 Elf_Internal_Shdr *symtab_hdr;
6178 asection *section;
6179 Elf_Internal_Sym *local_syms = NULL;
6180
99059e56
RM		 6181 if (!is_arm_elf (input_bfd))
6182 continue;
adbcc655 6183
48229727
JB		 6184 num_a8_relocs = 0;
6185
906e58ca
NC		 6186 /* We'll need the symbol table in a second. */
6187 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6188 if (symtab_hdr->sh_info == 0)
6189 continue;
6190
4ba2ef8f
TP		 6191 /* Limit scan of symbols to object file whose profile is
6192 Microcontroller to not hinder performance in the general case. */
6193 if (m_profile && first_veneer_scan)
6194 {
6195 struct elf_link_hash_entry **sym_hashes;
6196
6197 sym_hashes = elf_sym_hashes (input_bfd);
6198 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6199 &cmse_stub_created))
4ba2ef8f 6200 goto error_ret_free_local;
0955507f
TP		 6201
6202 if (cmse_stub_created != 0)
6203 stub_changed = TRUE;
4ba2ef8f
TP		 6204 }
6205
906e58ca
NC		 6206 /* Walk over each section attached to the input bfd. */
6207 for (section = input_bfd->sections;
6208 section != NULL;
6209 section = section->next)
6210 {
6211 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6212
6213 /* If there aren't any relocs, then there's nothing more
6214 to do. */
6215 if ((section->flags & SEC_RELOC) == 0
6216 || section->reloc_count == 0
6217 || (section->flags & SEC_CODE) == 0)
6218 continue;
6219
6220 /* If this section is a link-once section that will be
6221 discarded, then don't create any stubs. */
6222 if (section->output_section == NULL
6223 || section->output_section->owner != output_bfd)
6224 continue;
6225
6226 /* Get the relocs. */
6227 internal_relocs
6228 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6229 NULL, info->keep_memory);
6230 if (internal_relocs == NULL)
6231 goto error_ret_free_local;
6232
6233 /* Now examine each relocation. */
6234 irela = internal_relocs;
6235 irelaend = irela + section->reloc_count;
6236 for (; irela < irelaend; irela++)
6237 {
6238 unsigned int r_type, r_indx;
906e58ca
NC		 6239 asection *sym_sec;
6240 bfd_vma sym_value;
6241 bfd_vma destination;
6242 struct elf32_arm_link_hash_entry *hash;
7413f23f 6243 const char *sym_name;
34e77a92 6244 unsigned char st_type;
35fc36a8 6245 enum arm_st_branch_type branch_type;
48229727 6246 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6247
6248 r_type = ELF32_R_TYPE (irela->r_info);
6249 r_indx = ELF32_R_SYM (irela->r_info);
6250
6251 if (r_type >= (unsigned int) R_ARM_max)
6252 {
6253 bfd_set_error (bfd_error_bad_value);
6254 error_ret_free_internal:
6255 if (elf_section_data (section)->relocs == NULL)
6256 free (internal_relocs);
15dd01b1
TP		 6257 /* Fall through. */
6258 error_ret_free_local:
6259 if (local_syms != NULL
6260 && (symtab_hdr->contents
6261 != (unsigned char *) local_syms))
6262 free (local_syms);
6263 return FALSE;
906e58ca 6264 }
b38cadfb 6265
0855e32b
NS		 6266 hash = NULL;
6267 if (r_indx >= symtab_hdr->sh_info)
6268 hash = elf32_arm_hash_entry
6269 (elf_sym_hashes (input_bfd)
6270 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6271
0855e32b
NS		 6272 /* Only look for stubs on branch instructions, or
6273 non-relaxed TLSCALL */
906e58ca 6274 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6275 && (r_type != (unsigned int) R_ARM_THM_CALL)
6276 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6277 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6278 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6279 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6280 && (r_type != (unsigned int) R_ARM_PLT32)
6281 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6282 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6283 && r_type == elf32_arm_tls_transition
6284 (info, r_type, &hash->root)
6285 && ((hash ? hash->tls_type
6286 : (elf32_arm_local_got_tls_type
6287 (input_bfd)[r_indx]))
6288 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6289 continue;
6290
6291 /* Now determine the call target, its name, value,
6292 section. */
6293 sym_sec = NULL;
6294 sym_value = 0;
6295 destination = 0;
7413f23f 6296 sym_name = NULL;
b38cadfb 6297
0855e32b
NS		 6298 if (r_type == (unsigned int) R_ARM_TLS_CALL
6299 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6300 {
6301 /* A non-relaxed TLS call. The target is the
6302 plt-resident trampoline and nothing to do
6303 with the symbol. */
6304 BFD_ASSERT (htab->tls_trampoline > 0);
6305 sym_sec = htab->root.splt;
6306 sym_value = htab->tls_trampoline;
6307 hash = 0;
34e77a92 6308 st_type = STT_FUNC;
35fc36a8 6309 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6310 }
6311 else if (!hash)
906e58ca
NC		 6312 {
6313 /* It's a local symbol. */
6314 Elf_Internal_Sym *sym;
906e58ca
NC		 6315
6316 if (local_syms == NULL)
6317 {
6318 local_syms
6319 = (Elf_Internal_Sym *) symtab_hdr->contents;
6320 if (local_syms == NULL)
6321 local_syms
6322 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6323 symtab_hdr->sh_info, 0,
6324 NULL, NULL, NULL);
6325 if (local_syms == NULL)
6326 goto error_ret_free_internal;
6327 }
6328
6329 sym = local_syms + r_indx;
f6d250ce
TS		 6330 if (sym->st_shndx == SHN_UNDEF)
6331 sym_sec = bfd_und_section_ptr;
6332 else if (sym->st_shndx == SHN_ABS)
6333 sym_sec = bfd_abs_section_ptr;
6334 else if (sym->st_shndx == SHN_COMMON)
6335 sym_sec = bfd_com_section_ptr;
6336 else
6337 sym_sec =
6338 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6339
ffcb4889
NS		 6340 if (!sym_sec)
6341 /* This is an undefined symbol. It can never
6a631e86 6342 be resolved. */
ffcb4889 6343 continue;
fe33d2fa 6344
906e58ca
NC		 6345 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6346 sym_value = sym->st_value;
6347 destination = (sym_value + irela->r_addend
6348 + sym_sec->output_offset
6349 + sym_sec->output_section->vma);
34e77a92 6350 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6351 branch_type =
6352 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6353 sym_name
6354 = bfd_elf_string_from_elf_section (input_bfd,
6355 symtab_hdr->sh_link,
6356 sym->st_name);
906e58ca
NC		 6357 }
6358 else
6359 {
6360 /* It's an external symbol. */
906e58ca
NC		 6361 while (hash->root.root.type == bfd_link_hash_indirect
6362 || hash->root.root.type == bfd_link_hash_warning)
6363 hash = ((struct elf32_arm_link_hash_entry *)
6364 hash->root.root.u.i.link);
6365
6366 if (hash->root.root.type == bfd_link_hash_defined
6367 || hash->root.root.type == bfd_link_hash_defweak)
6368 {
6369 sym_sec = hash->root.root.u.def.section;
6370 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6371
6372 struct elf32_arm_link_hash_table *globals =
6373 elf32_arm_hash_table (info);
6374
6375 /* For a destination in a shared library,
6376 use the PLT stub as target address to
6377 decide whether a branch stub is
6378 needed. */
4dfe6ac6 6379 if (globals != NULL
362d30a1 6380 && globals->root.splt != NULL
4dfe6ac6 6381 && hash != NULL
022f8312
CL		 6382 && hash->root.plt.offset != (bfd_vma) -1)
6383 {
362d30a1 6384 sym_sec = globals->root.splt;
022f8312
CL		 6385 sym_value = hash->root.plt.offset;
6386 if (sym_sec->output_section != NULL)
6387 destination = (sym_value
6388 + sym_sec->output_offset
6389 + sym_sec->output_section->vma);
6390 }
6391 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6392 destination = (sym_value + irela->r_addend
6393 + sym_sec->output_offset
6394 + sym_sec->output_section->vma);
6395 }
69c5861e
CL		 6396 else if ((hash->root.root.type == bfd_link_hash_undefined)
6397 || (hash->root.root.type == bfd_link_hash_undefweak))
6398 {
6399 /* For a shared library, use the PLT stub as
6400 target address to decide whether a long
6401 branch stub is needed.
6402 For absolute code, they cannot be handled. */
6403 struct elf32_arm_link_hash_table *globals =
6404 elf32_arm_hash_table (info);
6405
4dfe6ac6 6406 if (globals != NULL
362d30a1 6407 && globals->root.splt != NULL
4dfe6ac6 6408 && hash != NULL
69c5861e
CL		 6409 && hash->root.plt.offset != (bfd_vma) -1)
6410 {
362d30a1 6411 sym_sec = globals->root.splt;
69c5861e
CL		 6412 sym_value = hash->root.plt.offset;
6413 if (sym_sec->output_section != NULL)
6414 destination = (sym_value
6415 + sym_sec->output_offset
6416 + sym_sec->output_section->vma);
6417 }
6418 else
6419 continue;
6420 }
906e58ca
NC		 6421 else
6422 {
6423 bfd_set_error (bfd_error_bad_value);
6424 goto error_ret_free_internal;
6425 }
34e77a92 6426 st_type = hash->root.type;
39d911fc
TP		 6427 branch_type =
6428 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6429 sym_name = hash->root.root.root.string;
906e58ca
NC		 6430 }
6431
48229727 6432 do
7413f23f 6433 {
b715f643 6434 bfd_boolean new_stub;
0955507f 6435 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6436
48229727
JB		 6437 /* Determine what (if any) linker stub is needed. */
6438 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6439 st_type, &branch_type,
6440 hash, destination, sym_sec,
48229727
JB		 6441 input_bfd, sym_name);
6442 if (stub_type == arm_stub_none)
6443 break;
6444
48229727
JB		 6445 /* We've either created a stub for this reloc already,
6446 or we are about to. */
0955507f 6447 stub_entry =
b715f643
TP		 6448 elf32_arm_create_stub (htab, stub_type, section, irela,
6449 sym_sec, hash,
6450 (char *) sym_name, sym_value,
6451 branch_type, &new_stub);
7413f23f 6452
0955507f 6453 created_stub = stub_entry != NULL;
b715f643
TP		 6454 if (!created_stub)
6455 goto error_ret_free_internal;
6456 else if (!new_stub)
6457 break;
99059e56 6458 else
b715f643 6459 stub_changed = TRUE;
99059e56
RM		 6460 }
6461 while (0);
6462
6463 /* Look for relocations which might trigger Cortex-A8
6464 erratum. */
6465 if (htab->fix_cortex_a8
6466 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6467 || r_type == (unsigned int) R_ARM_THM_JUMP19
6468 || r_type == (unsigned int) R_ARM_THM_CALL
6469 || r_type == (unsigned int) R_ARM_THM_XPC22))
6470 {
6471 bfd_vma from = section->output_section->vma
6472 + section->output_offset
6473 + irela->r_offset;
6474
6475 if ((from & 0xfff) == 0xffe)
6476 {
6477 /* Found a candidate. Note we haven't checked the
6478 destination is within 4K here: if we do so (and
6479 don't create an entry in a8_relocs) we can't tell
6480 that a branch should have been relocated when
6481 scanning later. */
6482 if (num_a8_relocs == a8_reloc_table_size)
6483 {
6484 a8_reloc_table_size *= 2;
6485 a8_relocs = (struct a8_erratum_reloc *)
6486 bfd_realloc (a8_relocs,
6487 sizeof (struct a8_erratum_reloc)
6488 * a8_reloc_table_size);
6489 }
6490
6491 a8_relocs[num_a8_relocs].from = from;
6492 a8_relocs[num_a8_relocs].destination = destination;
6493 a8_relocs[num_a8_relocs].r_type = r_type;
6494 a8_relocs[num_a8_relocs].branch_type = branch_type;
6495 a8_relocs[num_a8_relocs].sym_name = sym_name;
6496 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6497 a8_relocs[num_a8_relocs].hash = hash;
6498
6499 num_a8_relocs++;
6500 }
6501 }
906e58ca
NC		 6502 }
6503
99059e56
RM		 6504 /* We're done with the internal relocs, free them. */
6505 if (elf_section_data (section)->relocs == NULL)
6506 free (internal_relocs);
6507 }
48229727 6508
99059e56 6509 if (htab->fix_cortex_a8)
48229727 6510 {
99059e56
RM		 6511 /* Sort relocs which might apply to Cortex-A8 erratum. */
6512 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6513 sizeof (struct a8_erratum_reloc),
99059e56 6514 &a8_reloc_compare);
48229727 6515
99059e56
RM		 6516 /* Scan for branches which might trigger Cortex-A8 erratum. */
6517 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6518 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6519 a8_relocs, num_a8_relocs,
6520 prev_num_a8_fixes, &stub_changed)
6521 != 0)
48229727 6522 goto error_ret_free_local;
5e681ec4 6523 }
7f991970
AM		 6524
6525 if (local_syms != NULL
6526 && symtab_hdr->contents != (unsigned char *) local_syms)
6527 {
6528 if (!info->keep_memory)
6529 free (local_syms);
6530 else
6531 symtab_hdr->contents = (unsigned char *) local_syms;
6532 }
5e681ec4
PB		 6533 }
6534
0955507f
TP		 6535 if (first_veneer_scan
6536 && !set_cmse_veneer_addr_from_implib (info, htab,
6537 &cmse_stub_created))
6538 ret = FALSE;
6539
eb7c4339 6540 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6541 stub_changed = TRUE;
48229727 6542
906e58ca
NC		 6543 if (!stub_changed)
6544 break;
5e681ec4 6545
906e58ca
NC		 6546 /* OK, we've added some stubs. Find out the new size of the
6547 stub sections. */
6548 for (stub_sec = htab->stub_bfd->sections;
6549 stub_sec != NULL;
6550 stub_sec = stub_sec->next)
3e6b1042
DJ		 6551 {
6552 /* Ignore non-stub sections. */
6553 if (!strstr (stub_sec->name, STUB_SUFFIX))
6554 continue;
6555
6556 stub_sec->size = 0;
6557 }
b34b2d70 6558
0955507f
TP		 6559 /* Add new SG veneers after those already in the input import
6560 library. */
6561 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6562 stub_type++)
6563 {
6564 bfd_vma *start_offset_p;
6565 asection **stub_sec_p;
6566
6567 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6568 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6569 if (start_offset_p == NULL)
6570 continue;
6571
6572 BFD_ASSERT (stub_sec_p != NULL);
6573 if (*stub_sec_p != NULL)
6574 (*stub_sec_p)->size = *start_offset_p;
6575 }
6576
d7c5bd02 6577 /* Compute stub section size, considering padding. */
906e58ca 6578 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6579 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6580 stub_type++)
6581 {
6582 int size, padding;
6583 asection **stub_sec_p;
6584
6585 padding = arm_dedicated_stub_section_padding (stub_type);
6586 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6587 /* Skip if no stub input section or no stub section padding
6588 required. */
6589 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6590 continue;
6591 /* Stub section padding required but no dedicated section. */
6592 BFD_ASSERT (stub_sec_p);
6593
6594 size = (*stub_sec_p)->size;
6595 size = (size + padding - 1) & ~(padding - 1);
6596 (*stub_sec_p)->size = size;
6597 }
906e58ca 6598
48229727
JB		 6599 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6600 if (htab->fix_cortex_a8)
99059e56
RM		 6601 for (i = 0; i < num_a8_fixes; i++)
6602 {
48229727 6603 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6604 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6605
6606 if (stub_sec == NULL)
7f991970 6607 return FALSE;
48229727 6608
99059e56
RM		 6609 stub_sec->size
6610 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6611 NULL);
6612 }
48229727
JB		 6613
6614
906e58ca
NC		 6615 /* Ask the linker to do its stuff. */
6616 (*htab->layout_sections_again) ();
4ba2ef8f 6617 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6618 }
6619
48229727
JB		 6620 /* Add stubs for Cortex-A8 erratum fixes now. */
6621 if (htab->fix_cortex_a8)
6622 {
6623 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6624 {
6625 struct elf32_arm_stub_hash_entry *stub_entry;
6626 char *stub_name = a8_fixes[i].stub_name;
6627 asection *section = a8_fixes[i].section;
6628 unsigned int section_id = a8_fixes[i].section->id;
6629 asection *link_sec = htab->stub_group[section_id].link_sec;
6630 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6631 const insn_sequence *template_sequence;
6632 int template_size, size = 0;
6633
6634 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6635 TRUE, FALSE);
6636 if (stub_entry == NULL)
6637 {
871b3ab2 6638 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 6639 section->owner, stub_name);
99059e56
RM		 6640 return FALSE;
6641 }
6642
6643 stub_entry->stub_sec = stub_sec;
0955507f 6644 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6645 stub_entry->id_sec = link_sec;
6646 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6647 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6648 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6649 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6650 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6651 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6652
99059e56
RM		 6653 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6654 &template_sequence,
6655 &template_size);
48229727 6656
99059e56
RM		 6657 stub_entry->stub_size = size;
6658 stub_entry->stub_template = template_sequence;
6659 stub_entry->stub_template_size = template_size;
6660 }
48229727
JB		 6661
6662 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6663 elf32_arm_write_section(). */
48229727
JB		 6664 htab->a8_erratum_fixes = a8_fixes;
6665 htab->num_a8_erratum_fixes = num_a8_fixes;
6666 }
6667 else
6668 {
6669 htab->a8_erratum_fixes = NULL;
6670 htab->num_a8_erratum_fixes = 0;
6671 }
0955507f 6672 return ret;
5e681ec4
PB		 6673}
6674
906e58ca
NC		 6675/* Build all the stubs associated with the current output file. The
6676 stubs are kept in a hash table attached to the main linker hash
6677 table. We also set up the .plt entries for statically linked PIC
6678 functions here. This function is called via arm_elf_finish in the
6679 linker. */
252b5132 6680
906e58ca
NC		 6681bfd_boolean
6682elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 6683{
906e58ca
NC		 6684 asection *stub_sec;
6685 struct bfd_hash_table *table;
0955507f 6686 enum elf32_arm_stub_type stub_type;
906e58ca 6687 struct elf32_arm_link_hash_table *htab;
252b5132 6688
906e58ca 6689 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 6690 if (htab == NULL)
6691 return FALSE;
252b5132 6692
906e58ca
NC		 6693 for (stub_sec = htab->stub_bfd->sections;
6694 stub_sec != NULL;
6695 stub_sec = stub_sec->next)
252b5132 6696 {
906e58ca
NC		 6697 bfd_size_type size;
6698
8029a119 6699 /* Ignore non-stub sections. */
906e58ca
NC		 6700 if (!strstr (stub_sec->name, STUB_SUFFIX))
6701 continue;
6702
d7c5bd02 6703 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 6704 must at least be done for stub section requiring padding and for SG
6705 veneers to ensure that a non secure code branching to a removed SG
6706 veneer causes an error. */
906e58ca 6707 size = stub_sec->size;
21d799b5 6708 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 6709 if (stub_sec->contents == NULL && size != 0)
6710 return FALSE;
0955507f 6711
906e58ca 6712 stub_sec->size = 0;
252b5132
RH		 6713 }
6714
0955507f
TP		 6715 /* Add new SG veneers after those already in the input import library. */
6716 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
6717 {
6718 bfd_vma *start_offset_p;
6719 asection **stub_sec_p;
6720
6721 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6722 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6723 if (start_offset_p == NULL)
6724 continue;
6725
6726 BFD_ASSERT (stub_sec_p != NULL);
6727 if (*stub_sec_p != NULL)
6728 (*stub_sec_p)->size = *start_offset_p;
6729 }
6730
906e58ca
NC		 6731 /* Build the stubs as directed by the stub hash table. */
6732 table = &htab->stub_hash_table;
6733 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 6734 if (htab->fix_cortex_a8)
6735 {
6736 /* Place the cortex a8 stubs last. */
6737 htab->fix_cortex_a8 = -1;
6738 bfd_hash_traverse (table, arm_build_one_stub, info);
6739 }
252b5132 6740
906e58ca 6741 return TRUE;
252b5132
RH		 6742}
6743
9b485d32
NC		 6744/* Locate the Thumb encoded calling stub for NAME. */
6745
252b5132 6746static struct elf_link_hash_entry *
57e8b36a
NC		 6747find_thumb_glue (struct bfd_link_info *link_info,
6748 const char *name,
f2a9dd69 6749 char **error_message)
252b5132
RH		 6750{
6751 char *tmp_name;
6752 struct elf_link_hash_entry *hash;
6753 struct elf32_arm_link_hash_table *hash_table;
6754
6755 /* We need a pointer to the armelf specific hash table. */
6756 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6757 if (hash_table == NULL)
6758 return NULL;
252b5132 6759
21d799b5 6760 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6761 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6762
6763 BFD_ASSERT (tmp_name);
6764
6765 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
6766
6767 hash = elf_link_hash_lookup
b34976b6 6768 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6769
b1657152 6770 if (hash == NULL
90b6238f
AM		 6771 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
6772 "Thumb", tmp_name, name) == -1)
b1657152 6773 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6774
6775 free (tmp_name);
6776
6777 return hash;
6778}
6779
9b485d32
NC		 6780/* Locate the ARM encoded calling stub for NAME. */
6781
252b5132 6782static struct elf_link_hash_entry *
57e8b36a
NC		 6783find_arm_glue (struct bfd_link_info *link_info,
6784 const char *name,
f2a9dd69 6785 char **error_message)
252b5132
RH		 6786{
6787 char *tmp_name;
6788 struct elf_link_hash_entry *myh;
6789 struct elf32_arm_link_hash_table *hash_table;
6790
6791 /* We need a pointer to the elfarm specific hash table. */
6792 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6793 if (hash_table == NULL)
6794 return NULL;
252b5132 6795
21d799b5 6796 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6797 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6798
6799 BFD_ASSERT (tmp_name);
6800
6801 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6802
6803 myh = elf_link_hash_lookup
b34976b6 6804 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6805
b1657152 6806 if (myh == NULL
90b6238f
AM		 6807 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
6808 "ARM", tmp_name, name) == -1)
b1657152 6809 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6810
6811 free (tmp_name);
6812
6813 return myh;
6814}
6815
8f6277f5 6816/* ARM->Thumb glue (static images):
252b5132
RH		 6817
6818 .arm
6819 __func_from_arm:
6820 ldr r12, __func_addr
6821 bx r12
6822 __func_addr:
906e58ca 6823 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 6824
26079076
PB		 6825 (v5t static images)
6826 .arm
6827 __func_from_arm:
6828 ldr pc, __func_addr
6829 __func_addr:
906e58ca 6830 .word func @ behave as if you saw a ARM_32 reloc.
26079076 6831
8f6277f5
PB		 6832 (relocatable images)
6833 .arm
6834 __func_from_arm:
6835 ldr r12, __func_offset
6836 add r12, r12, pc
6837 bx r12
6838 __func_offset:
8029a119 6839 .word func - . */
8f6277f5
PB		 6840
6841#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 6842static const insn32 a2t1_ldr_insn = 0xe59fc000;
6843static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
6844static const insn32 a2t3_func_addr_insn = 0x00000001;
6845
26079076
PB		 6846#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
6847static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
6848static const insn32 a2t2v5_func_addr_insn = 0x00000001;
6849
8f6277f5
PB		 6850#define ARM2THUMB_PIC_GLUE_SIZE 16
6851static const insn32 a2t1p_ldr_insn = 0xe59fc004;
6852static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
6853static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
6854
07d6d2b8 6855/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 6856
07d6d2b8
AM		 6857 .thumb .thumb
6858 .align 2 .align 2
6859 __func_from_thumb: __func_from_thumb:
6860 bx pc push {r6, lr}
6861 nop ldr r6, __func_addr
6862 .arm mov lr, pc
6863 b func bx r6
99059e56
RM		 6864 .arm
6865 ;; back_to_thumb
6866 ldmia r13! {r6, lr}
6867 bx lr
6868 __func_addr:
07d6d2b8 6869 .word func */
252b5132
RH		 6870
6871#define THUMB2ARM_GLUE_SIZE 8
6872static const insn16 t2a1_bx_pc_insn = 0x4778;
6873static const insn16 t2a2_noop_insn = 0x46c0;
6874static const insn32 t2a3_b_insn = 0xea000000;
6875
c7b8f16e 6876#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 6877#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
6878#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 6879
845b51d6
PB		 6880#define ARM_BX_VENEER_SIZE 12
6881static const insn32 armbx1_tst_insn = 0xe3100001;
6882static const insn32 armbx2_moveq_insn = 0x01a0f000;
6883static const insn32 armbx3_bx_insn = 0xe12fff10;
6884
7e392df6 6885#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 6886static void
6887arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 6888{
6889 asection * s;
8029a119 6890 bfd_byte * contents;
252b5132 6891
8029a119 6892 if (size == 0)
3e6b1042
DJ		 6893 {
6894 /* Do not include empty glue sections in the output. */
6895 if (abfd != NULL)
6896 {
3d4d4302 6897 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 6898 if (s != NULL)
6899 s->flags |= SEC_EXCLUDE;
6900 }
6901 return;
6902 }
252b5132 6903
8029a119 6904 BFD_ASSERT (abfd != NULL);
252b5132 6905
3d4d4302 6906 s = bfd_get_linker_section (abfd, name);
8029a119 6907 BFD_ASSERT (s != NULL);
252b5132 6908
21d799b5 6909 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 6910
8029a119
NC		 6911 BFD_ASSERT (s->size == size);
6912 s->contents = contents;
6913}
906e58ca 6914
8029a119
NC		 6915bfd_boolean
6916bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
6917{
6918 struct elf32_arm_link_hash_table * globals;
906e58ca 6919
8029a119
NC		 6920 globals = elf32_arm_hash_table (info);
6921 BFD_ASSERT (globals != NULL);
906e58ca 6922
8029a119
NC		 6923 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6924 globals->arm_glue_size,
6925 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 6926
8029a119
NC		 6927 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6928 globals->thumb_glue_size,
6929 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 6930
8029a119
NC		 6931 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6932 globals->vfp11_erratum_glue_size,
6933 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 6934
a504d23a
LA		 6935 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6936 globals->stm32l4xx_erratum_glue_size,
6937 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6938
8029a119
NC		 6939 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6940 globals->bx_glue_size,
845b51d6
PB		 6941 ARM_BX_GLUE_SECTION_NAME);
6942
b34976b6 6943 return TRUE;
252b5132
RH		 6944}
6945
a4fd1a8e 6946/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 6947 returns the symbol identifying the stub. */
6948
a4fd1a8e 6949static struct elf_link_hash_entry *
57e8b36a
NC		 6950record_arm_to_thumb_glue (struct bfd_link_info * link_info,
6951 struct elf_link_hash_entry * h)
252b5132
RH		 6952{
6953 const char * name = h->root.root.string;
63b0f745 6954 asection * s;
252b5132
RH		 6955 char * tmp_name;
6956 struct elf_link_hash_entry * myh;
14a793b2 6957 struct bfd_link_hash_entry * bh;
252b5132 6958 struct elf32_arm_link_hash_table * globals;
dc810e39 6959 bfd_vma val;
2f475487 6960 bfd_size_type size;
252b5132
RH		 6961
6962 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 6963 BFD_ASSERT (globals != NULL);
6964 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6965
3d4d4302 6966 s = bfd_get_linker_section
252b5132
RH		 6967 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
6968
252b5132
RH		 6969 BFD_ASSERT (s != NULL);
6970
21d799b5 6971 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6972 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6973
6974 BFD_ASSERT (tmp_name);
6975
6976 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6977
6978 myh = elf_link_hash_lookup
b34976b6 6979 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 6980
6981 if (myh != NULL)
6982 {
9b485d32 6983 /* We've already seen this guy. */
252b5132 6984 free (tmp_name);
a4fd1a8e 6985 return myh;
252b5132
RH		 6986 }
6987
57e8b36a
NC		 6988 /* The only trick here is using hash_table->arm_glue_size as the value.
6989 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 6990 putting it. The +1 on the value marks that the stub has not been
6991 output yet - not that it is a Thumb function. */
14a793b2 6992 bh = NULL;
dc810e39
AM		 6993 val = globals->arm_glue_size + 1;
6994 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
6995 tmp_name, BSF_GLOBAL, s, val,
b34976b6 6996 NULL, TRUE, FALSE, &bh);
252b5132 6997
b7693d02
DJ		 6998 myh = (struct elf_link_hash_entry *) bh;
6999 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7000 myh->forced_local = 1;
7001
252b5132
RH		 7002 free (tmp_name);
7003
0e1862bb
L		 7004 if (bfd_link_pic (link_info)
7005 || globals->root.is_relocatable_executable
27e55c4d 7006 || globals->pic_veneer)
2f475487 7007 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7008 else if (globals->use_blx)
7009 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7010 else
2f475487
AM		 7011 size = ARM2THUMB_STATIC_GLUE_SIZE;
7012
7013 s->size += size;
7014 globals->arm_glue_size += size;
252b5132 7015
a4fd1a8e 7016 return myh;
252b5132
RH		 7017}
7018
845b51d6
PB		 7019/* Allocate space for ARMv4 BX veneers. */
7020
7021static void
7022record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7023{
7024 asection * s;
7025 struct elf32_arm_link_hash_table *globals;
7026 char *tmp_name;
7027 struct elf_link_hash_entry *myh;
7028 struct bfd_link_hash_entry *bh;
7029 bfd_vma val;
7030
7031 /* BX PC does not need a veneer. */
7032 if (reg == 15)
7033 return;
7034
7035 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7036 BFD_ASSERT (globals != NULL);
7037 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7038
7039 /* Check if this veneer has already been allocated. */
7040 if (globals->bx_glue_offset[reg])
7041 return;
7042
3d4d4302 7043 s = bfd_get_linker_section
845b51d6
PB		 7044 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7045
7046 BFD_ASSERT (s != NULL);
7047
7048 /* Add symbol for veneer. */
21d799b5
NC		 7049 tmp_name = (char *)
7050 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7051
845b51d6 7052 BFD_ASSERT (tmp_name);
906e58ca 7053
845b51d6 7054 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7055
845b51d6
PB		 7056 myh = elf_link_hash_lookup
7057 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7058
845b51d6 7059 BFD_ASSERT (myh == NULL);
906e58ca 7060
845b51d6
PB		 7061 bh = NULL;
7062 val = globals->bx_glue_size;
7063 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7064 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7065 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7066
7067 myh = (struct elf_link_hash_entry *) bh;
7068 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7069 myh->forced_local = 1;
7070
7071 s->size += ARM_BX_VENEER_SIZE;
7072 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7073 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7074}
7075
7076
c7b8f16e
JB		 7077/* Add an entry to the code/data map for section SEC. */
7078
7079static void
7080elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7081{
7082 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7083 unsigned int newidx;
906e58ca 7084
c7b8f16e
JB		 7085 if (sec_data->map == NULL)
7086 {
21d799b5 7087 sec_data->map = (elf32_arm_section_map *)
99059e56 7088 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7089 sec_data->mapcount = 0;
7090 sec_data->mapsize = 1;
7091 }
906e58ca 7092
c7b8f16e 7093 newidx = sec_data->mapcount++;
906e58ca 7094
c7b8f16e
JB		 7095 if (sec_data->mapcount > sec_data->mapsize)
7096 {
7097 sec_data->mapsize *= 2;
21d799b5 7098 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7099 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7100 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7101 }
7102
7103 if (sec_data->map)
7104 {
7105 sec_data->map[newidx].vma = vma;
7106 sec_data->map[newidx].type = type;
c7b8f16e 7107 }
c7b8f16e
JB		 7108}
7109
7110
7111/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7112 veneers are handled for now. */
7113
7114static bfd_vma
7115record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7116 elf32_vfp11_erratum_list *branch,
7117 bfd *branch_bfd,
7118 asection *branch_sec,
7119 unsigned int offset)
c7b8f16e
JB		 7120{
7121 asection *s;
7122 struct elf32_arm_link_hash_table *hash_table;
7123 char *tmp_name;
7124 struct elf_link_hash_entry *myh;
7125 struct bfd_link_hash_entry *bh;
7126 bfd_vma val;
7127 struct _arm_elf_section_data *sec_data;
c7b8f16e 7128 elf32_vfp11_erratum_list *newerr;
906e58ca 7129
c7b8f16e 7130 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7131 BFD_ASSERT (hash_table != NULL);
7132 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7133
3d4d4302 7134 s = bfd_get_linker_section
c7b8f16e 7135 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7136
c7b8f16e 7137 sec_data = elf32_arm_section_data (s);
906e58ca 7138
c7b8f16e 7139 BFD_ASSERT (s != NULL);
906e58ca 7140
21d799b5 7141 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7142 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7143
c7b8f16e 7144 BFD_ASSERT (tmp_name);
906e58ca 7145
c7b8f16e
JB		 7146 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7147 hash_table->num_vfp11_fixes);
906e58ca 7148
c7b8f16e
JB		 7149 myh = elf_link_hash_lookup
7150 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7151
c7b8f16e 7152 BFD_ASSERT (myh == NULL);
906e58ca 7153
c7b8f16e
JB		 7154 bh = NULL;
7155 val = hash_table->vfp11_erratum_glue_size;
7156 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7157 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7158 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7159
7160 myh = (struct elf_link_hash_entry *) bh;
7161 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7162 myh->forced_local = 1;
7163
7164 /* Link veneer back to calling location. */
c7e2358a 7165 sec_data->erratumcount += 1;
21d799b5
NC		 7166 newerr = (elf32_vfp11_erratum_list *)
7167 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7168
c7b8f16e
JB		 7169 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7170 newerr->vma = -1;
7171 newerr->u.v.branch = branch;
7172 newerr->u.v.id = hash_table->num_vfp11_fixes;
7173 branch->u.b.veneer = newerr;
7174
7175 newerr->next = sec_data->erratumlist;
7176 sec_data->erratumlist = newerr;
7177
7178 /* A symbol for the return from the veneer. */
7179 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7180 hash_table->num_vfp11_fixes);
7181
7182 myh = elf_link_hash_lookup
7183 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7184
c7b8f16e
JB		 7185 if (myh != NULL)
7186 abort ();
7187
7188 bh = NULL;
7189 val = offset + 4;
7190 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7191 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7192
c7b8f16e
JB		 7193 myh = (struct elf_link_hash_entry *) bh;
7194 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7195 myh->forced_local = 1;
7196
7197 free (tmp_name);
906e58ca 7198
c7b8f16e
JB		 7199 /* Generate a mapping symbol for the veneer section, and explicitly add an
7200 entry for that symbol to the code/data map for the section. */
7201 if (hash_table->vfp11_erratum_glue_size == 0)
7202 {
7203 bh = NULL;
7204 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7205 ever requires this erratum fix. */
c7b8f16e
JB		 7206 _bfd_generic_link_add_one_symbol (link_info,
7207 hash_table->bfd_of_glue_owner, "$a",
7208 BSF_LOCAL, s, 0, NULL,
99059e56 7209 TRUE, FALSE, &bh);
c7b8f16e
JB		 7210
7211 myh = (struct elf_link_hash_entry *) bh;
7212 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7213 myh->forced_local = 1;
906e58ca 7214
c7b8f16e 7215 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7216 BFDs. We must make a note of this generated mapping symbol
7217 ourselves so that code byteswapping works properly in
7218 elf32_arm_write_section. */
c7b8f16e
JB		 7219 elf32_arm_section_map_add (s, 'a', 0);
7220 }
906e58ca 7221
c7b8f16e
JB		 7222 s->size += VFP11_ERRATUM_VENEER_SIZE;
7223 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7224 hash_table->num_vfp11_fixes++;
906e58ca 7225
c7b8f16e
JB		 7226 /* The offset of the veneer. */
7227 return val;
7228}
7229
a504d23a
LA		 7230/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7231 veneers need to be handled because used only in Cortex-M. */
7232
7233static bfd_vma
7234record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7235 elf32_stm32l4xx_erratum_list *branch,
7236 bfd *branch_bfd,
7237 asection *branch_sec,
7238 unsigned int offset,
7239 bfd_size_type veneer_size)
7240{
7241 asection *s;
7242 struct elf32_arm_link_hash_table *hash_table;
7243 char *tmp_name;
7244 struct elf_link_hash_entry *myh;
7245 struct bfd_link_hash_entry *bh;
7246 bfd_vma val;
7247 struct _arm_elf_section_data *sec_data;
7248 elf32_stm32l4xx_erratum_list *newerr;
7249
7250 hash_table = elf32_arm_hash_table (link_info);
7251 BFD_ASSERT (hash_table != NULL);
7252 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7253
7254 s = bfd_get_linker_section
7255 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7256
7257 BFD_ASSERT (s != NULL);
7258
7259 sec_data = elf32_arm_section_data (s);
7260
7261 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7262 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7263
7264 BFD_ASSERT (tmp_name);
7265
7266 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7267 hash_table->num_stm32l4xx_fixes);
7268
7269 myh = elf_link_hash_lookup
7270 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7271
7272 BFD_ASSERT (myh == NULL);
7273
7274 bh = NULL;
7275 val = hash_table->stm32l4xx_erratum_glue_size;
7276 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7277 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7278 NULL, TRUE, FALSE, &bh);
7279
7280 myh = (struct elf_link_hash_entry *) bh;
7281 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7282 myh->forced_local = 1;
7283
7284 /* Link veneer back to calling location. */
7285 sec_data->stm32l4xx_erratumcount += 1;
7286 newerr = (elf32_stm32l4xx_erratum_list *)
7287 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7288
7289 newerr->type = STM32L4XX_ERRATUM_VENEER;
7290 newerr->vma = -1;
7291 newerr->u.v.branch = branch;
7292 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7293 branch->u.b.veneer = newerr;
7294
7295 newerr->next = sec_data->stm32l4xx_erratumlist;
7296 sec_data->stm32l4xx_erratumlist = newerr;
7297
7298 /* A symbol for the return from the veneer. */
7299 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7300 hash_table->num_stm32l4xx_fixes);
7301
7302 myh = elf_link_hash_lookup
7303 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7304
7305 if (myh != NULL)
7306 abort ();
7307
7308 bh = NULL;
7309 val = offset + 4;
7310 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7311 branch_sec, val, NULL, TRUE, FALSE, &bh);
7312
7313 myh = (struct elf_link_hash_entry *) bh;
7314 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7315 myh->forced_local = 1;
7316
7317 free (tmp_name);
7318
7319 /* Generate a mapping symbol for the veneer section, and explicitly add an
7320 entry for that symbol to the code/data map for the section. */
7321 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7322 {
7323 bh = NULL;
7324 /* Creates a THUMB symbol since there is no other choice. */
7325 _bfd_generic_link_add_one_symbol (link_info,
7326 hash_table->bfd_of_glue_owner, "$t",
7327 BSF_LOCAL, s, 0, NULL,
7328 TRUE, FALSE, &bh);
7329
7330 myh = (struct elf_link_hash_entry *) bh;
7331 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7332 myh->forced_local = 1;
7333
7334 /* The elf32_arm_init_maps function only cares about symbols from input
7335 BFDs. We must make a note of this generated mapping symbol
7336 ourselves so that code byteswapping works properly in
7337 elf32_arm_write_section. */
7338 elf32_arm_section_map_add (s, 't', 0);
7339 }
7340
7341 s->size += veneer_size;
7342 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7343 hash_table->num_stm32l4xx_fixes++;
7344
7345 /* The offset of the veneer. */
7346 return val;
7347}
7348
8029a119 7349#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7350 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7351 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7352
7353/* Create a fake section for use by the ARM backend of the linker. */
7354
7355static bfd_boolean
7356arm_make_glue_section (bfd * abfd, const char * name)
7357{
7358 asection * sec;
7359
3d4d4302 7360 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7361 if (sec != NULL)
7362 /* Already made. */
7363 return TRUE;
7364
3d4d4302 7365 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7366
7367 if (sec == NULL
7368 || !bfd_set_section_alignment (abfd, sec, 2))
7369 return FALSE;
7370
7371 /* Set the gc mark to prevent the section from being removed by garbage
7372 collection, despite the fact that no relocs refer to this section. */
7373 sec->gc_mark = 1;
7374
7375 return TRUE;
7376}
7377
1db37fe6
YG		 7378/* Set size of .plt entries. This function is called from the
7379 linker scripts in ld/emultempl/{armelf}.em. */
7380
7381void
7382bfd_elf32_arm_use_long_plt (void)
7383{
7384 elf32_arm_use_long_plt_entry = TRUE;
7385}
7386
8afb0e02
NC		 7387/* Add the glue sections to ABFD. This function is called from the
7388 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7389
b34976b6 7390bfd_boolean
57e8b36a
NC		 7391bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7392 struct bfd_link_info *info)
252b5132 7393{
a504d23a
LA		 7394 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7395 bfd_boolean dostm32l4xx = globals
7396 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7397 bfd_boolean addglue;
7398
8afb0e02
NC		 7399 /* If we are only performing a partial
7400 link do not bother adding the glue. */
0e1862bb 7401 if (bfd_link_relocatable (info))
b34976b6 7402 return TRUE;
252b5132 7403
a504d23a 7404 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7405 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7406 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7407 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7408
7409 if (!dostm32l4xx)
7410 return addglue;
7411
7412 return addglue
7413 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7414}
7415
daa4adae
TP		 7416/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7417 ensures they are not marked for deletion by
7418 strip_excluded_output_sections () when veneers are going to be created
7419 later. Not doing so would trigger assert on empty section size in
7420 lang_size_sections_1 (). */
7421
7422void
7423bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7424{
7425 enum elf32_arm_stub_type stub_type;
7426
7427 /* If we are only performing a partial
7428 link do not bother adding the glue. */
7429 if (bfd_link_relocatable (info))
7430 return;
7431
7432 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7433 {
7434 asection *out_sec;
7435 const char *out_sec_name;
7436
7437 if (!arm_dedicated_stub_output_section_required (stub_type))
7438 continue;
7439
7440 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7441 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7442 if (out_sec != NULL)
7443 out_sec->flags |= SEC_KEEP;
7444 }
7445}
7446
8afb0e02
NC		 7447/* Select a BFD to be used to hold the sections used by the glue code.
7448 This function is called from the linker scripts in ld/emultempl/
8029a119 7449 {armelf/pe}.em. */
8afb0e02 7450
b34976b6 7451bfd_boolean
57e8b36a 7452bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7453{
7454 struct elf32_arm_link_hash_table *globals;
7455
7456 /* If we are only performing a partial link
7457 do not bother getting a bfd to hold the glue. */
0e1862bb 7458 if (bfd_link_relocatable (info))
b34976b6 7459 return TRUE;
8afb0e02 7460
b7693d02
DJ		 7461 /* Make sure we don't attach the glue sections to a dynamic object. */
7462 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7463
8afb0e02 7464 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7465 BFD_ASSERT (globals != NULL);
7466
7467 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7468 return TRUE;
8afb0e02 7469
252b5132
RH		 7470 /* Save the bfd for later use. */
7471 globals->bfd_of_glue_owner = abfd;
cedb70c5 7472
b34976b6 7473 return TRUE;
252b5132
RH		 7474}
7475
906e58ca
NC		 7476static void
7477check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7478{
2de70689
MGD		 7479 int cpu_arch;
7480
b38cadfb 7481 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7482 Tag_CPU_arch);
7483
7484 if (globals->fix_arm1176)
7485 {
7486 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7487 globals->use_blx = 1;
7488 }
7489 else
7490 {
7491 if (cpu_arch > TAG_CPU_ARCH_V4T)
7492 globals->use_blx = 1;
7493 }
39b41c9c
PB		 7494}
7495
b34976b6 7496bfd_boolean
57e8b36a 7497bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7498 struct bfd_link_info *link_info)
252b5132
RH		 7499{
7500 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7501 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7502 Elf_Internal_Rela *irel, *irelend;
7503 bfd_byte *contents = NULL;
252b5132
RH		 7504
7505 asection *sec;
7506 struct elf32_arm_link_hash_table *globals;
7507
7508 /* If we are only performing a partial link do not bother
7509 to construct any glue. */
0e1862bb 7510 if (bfd_link_relocatable (link_info))
b34976b6 7511 return TRUE;
252b5132 7512
39ce1a6a
NC		 7513 /* Here we have a bfd that is to be included on the link. We have a
7514 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7515 globals = elf32_arm_hash_table (link_info);
252b5132 7516 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7517
7518 check_use_blx (globals);
252b5132 7519
d504ffc8 7520 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7521 {
90b6238f 7522 _bfd_error_handler (_("%pB: BE8 images only valid in big-endian mode"),
d003868e 7523 abfd);
e489d0ae
PB		 7524 return FALSE;
7525 }
f21f3fe0 7526
39ce1a6a
NC		 7527 /* PR 5398: If we have not decided to include any loadable sections in
7528 the output then we will not have a glue owner bfd. This is OK, it
7529 just means that there is nothing else for us to do here. */
7530 if (globals->bfd_of_glue_owner == NULL)
7531 return TRUE;
7532
252b5132
RH		 7533 /* Rummage around all the relocs and map the glue vectors. */
7534 sec = abfd->sections;
7535
7536 if (sec == NULL)
b34976b6 7537 return TRUE;
252b5132
RH		 7538
7539 for (; sec != NULL; sec = sec->next)
7540 {
7541 if (sec->reloc_count == 0)
7542 continue;
7543
2f475487
AM		 7544 if ((sec->flags & SEC_EXCLUDE) != 0)
7545 continue;
7546
0ffa91dd 7547 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7548
9b485d32 7549 /* Load the relocs. */
6cdc0ccc 7550 internal_relocs
906e58ca 7551 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7552
6cdc0ccc
AM		 7553 if (internal_relocs == NULL)
7554 goto error_return;
252b5132 7555
6cdc0ccc
AM		 7556 irelend = internal_relocs + sec->reloc_count;
7557 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7558 {
7559 long r_type;
7560 unsigned long r_index;
252b5132
RH		 7561
7562 struct elf_link_hash_entry *h;
7563
7564 r_type = ELF32_R_TYPE (irel->r_info);
7565 r_index = ELF32_R_SYM (irel->r_info);
7566
9b485d32 7567 /* These are the only relocation types we care about. */
ba96a88f 7568 if ( r_type != R_ARM_PC24
845b51d6 7569 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7570 continue;
7571
7572 /* Get the section contents if we haven't done so already. */
7573 if (contents == NULL)
7574 {
7575 /* Get cached copy if it exists. */
7576 if (elf_section_data (sec)->this_hdr.contents != NULL)
7577 contents = elf_section_data (sec)->this_hdr.contents;
7578 else
7579 {
7580 /* Go get them off disk. */
57e8b36a 7581 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7582 goto error_return;
7583 }
7584 }
7585
845b51d6
PB		 7586 if (r_type == R_ARM_V4BX)
7587 {
7588 int reg;
7589
7590 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7591 record_arm_bx_glue (link_info, reg);
7592 continue;
7593 }
7594
a7c10850 7595 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7596 h = NULL;
7597
9b485d32 7598 /* We don't care about local symbols. */
252b5132
RH		 7599 if (r_index < symtab_hdr->sh_info)
7600 continue;
7601
9b485d32 7602 /* This is an external symbol. */
252b5132
RH		 7603 r_index -= symtab_hdr->sh_info;
7604 h = (struct elf_link_hash_entry *)
7605 elf_sym_hashes (abfd)[r_index];
7606
7607 /* If the relocation is against a static symbol it must be within
7608 the current section and so cannot be a cross ARM/Thumb relocation. */
7609 if (h == NULL)
7610 continue;
7611
d504ffc8
DJ		 7612 /* If the call will go through a PLT entry then we do not need
7613 glue. */
362d30a1 7614 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7615 continue;
7616
252b5132
RH		 7617 switch (r_type)
7618 {
7619 case R_ARM_PC24:
7620 /* This one is a call from arm code. We need to look up
99059e56
RM		 7621 the target of the call. If it is a thumb target, we
7622 insert glue. */
39d911fc
TP		 7623 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7624 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7625 record_arm_to_thumb_glue (link_info, h);
7626 break;
7627
252b5132 7628 default:
c6596c5e 7629 abort ();
252b5132
RH		 7630 }
7631 }
6cdc0ccc
AM		 7632
7633 if (contents != NULL
7634 && elf_section_data (sec)->this_hdr.contents != contents)
7635 free (contents);
7636 contents = NULL;
7637
7638 if (internal_relocs != NULL
7639 && elf_section_data (sec)->relocs != internal_relocs)
7640 free (internal_relocs);
7641 internal_relocs = NULL;
252b5132
RH		 7642 }
7643
b34976b6 7644 return TRUE;
9a5aca8c 7645
252b5132 7646error_return:
6cdc0ccc
AM		 7647 if (contents != NULL
7648 && elf_section_data (sec)->this_hdr.contents != contents)
7649 free (contents);
7650 if (internal_relocs != NULL
7651 && elf_section_data (sec)->relocs != internal_relocs)
7652 free (internal_relocs);
9a5aca8c 7653
b34976b6 7654 return FALSE;
252b5132 7655}
7e392df6 7656#endif
252b5132 7657
eb043451 7658
c7b8f16e
JB		 7659/* Initialise maps of ARM/Thumb/data for input BFDs. */
7660
7661void
7662bfd_elf32_arm_init_maps (bfd *abfd)
7663{
7664 Elf_Internal_Sym *isymbuf;
7665 Elf_Internal_Shdr *hdr;
7666 unsigned int i, localsyms;
7667
af1f4419
NC		 7668 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7669 if (! is_arm_elf (abfd))
7670 return;
7671
c7b8f16e
JB		 7672 if ((abfd->flags & DYNAMIC) != 0)
7673 return;
7674
0ffa91dd 7675 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7676 localsyms = hdr->sh_info;
7677
7678 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7679 should contain the number of local symbols, which should come before any
7680 global symbols. Mapping symbols are always local. */
7681 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7682 NULL);
7683
7684 /* No internal symbols read? Skip this BFD. */
7685 if (isymbuf == NULL)
7686 return;
7687
7688 for (i = 0; i < localsyms; i++)
7689 {
7690 Elf_Internal_Sym *isym = &isymbuf[i];
7691 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
7692 const char *name;
906e58ca 7693
c7b8f16e 7694 if (sec != NULL
99059e56
RM		 7695 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
7696 {
7697 name = bfd_elf_string_from_elf_section (abfd,
7698 hdr->sh_link, isym->st_name);
906e58ca 7699
99059e56 7700 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 7701 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 7702 elf32_arm_section_map_add (sec, name[1], isym->st_value);
7703 }
c7b8f16e
JB		 7704 }
7705}
7706
7707
48229727
JB		 7708/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
7709 say what they wanted. */
7710
7711void
7712bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
7713{
7714 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7715 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7716
4dfe6ac6
NC		 7717 if (globals == NULL)
7718 return;
7719
48229727
JB		 7720 if (globals->fix_cortex_a8 == -1)
7721 {
7722 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
7723 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
7724 && (out_attr[Tag_CPU_arch_profile].i == 'A'
7725 || out_attr[Tag_CPU_arch_profile].i == 0))
7726 globals->fix_cortex_a8 = 1;
7727 else
7728 globals->fix_cortex_a8 = 0;
7729 }
7730}
7731
7732
c7b8f16e
JB		 7733void
7734bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
7735{
7736 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 7737 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 7738
4dfe6ac6
NC		 7739 if (globals == NULL)
7740 return;
c7b8f16e
JB		 7741 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
7742 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
7743 {
7744 switch (globals->vfp11_fix)
99059e56
RM		 7745 {
7746 case BFD_ARM_VFP11_FIX_DEFAULT:
7747 case BFD_ARM_VFP11_FIX_NONE:
7748 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7749 break;
7750
7751 default:
7752 /* Give a warning, but do as the user requests anyway. */
871b3ab2 7753 _bfd_error_handler (_("%pB: warning: selected VFP11 erratum "
99059e56
RM		 7754 "workaround is not necessary for target architecture"), obfd);
7755 }
c7b8f16e
JB		 7756 }
7757 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
7758 /* For earlier architectures, we might need the workaround, but do not
7759 enable it by default. If users is running with broken hardware, they
7760 must enable the erratum fix explicitly. */
7761 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7762}
7763
a504d23a
LA		 7764void
7765bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
7766{
7767 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7768 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7769
7770 if (globals == NULL)
7771 return;
7772
7773 /* We assume only Cortex-M4 may require the fix. */
7774 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
7775 || out_attr[Tag_CPU_arch_profile].i != 'M')
7776 {
7777 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
7778 /* Give a warning, but do as the user requests anyway. */
4eca0228 7779 _bfd_error_handler
871b3ab2 7780 (_("%pB: warning: selected STM32L4XX erratum "
a504d23a
LA		 7781 "workaround is not necessary for target architecture"), obfd);
7782 }
7783}
c7b8f16e 7784
906e58ca
NC		 7785enum bfd_arm_vfp11_pipe
7786{
c7b8f16e
JB		 7787 VFP11_FMAC,
7788 VFP11_LS,
7789 VFP11_DS,
7790 VFP11_BAD
7791};
7792
7793/* Return a VFP register number. This is encoded as RX:X for single-precision
7794 registers, or X:RX for double-precision registers, where RX is the group of
7795 four bits in the instruction encoding and X is the single extension bit.
7796 RX and X fields are specified using their lowest (starting) bit. The return
7797 value is:
7798
7799 0...31: single-precision registers s0...s31
7800 32...63: double-precision registers d0...d31.
906e58ca 7801
c7b8f16e
JB		 7802 Although X should be zero for VFP11 (encoding d0...d15 only), we might
7803 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 7804
c7b8f16e
JB		 7805static unsigned int
7806bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 7807 unsigned int x)
c7b8f16e
JB		 7808{
7809 if (is_double)
7810 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
7811 else
7812 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
7813}
7814
7815/* Set bits in *WMASK according to a register number REG as encoded by
7816 bfd_arm_vfp11_regno(). Ignore d16-d31. */
7817
7818static void
7819bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
7820{
7821 if (reg < 32)
7822 *wmask |= 1 << reg;
7823 else if (reg < 48)
7824 *wmask |= 3 << ((reg - 32) * 2);
7825}
7826
7827/* Return TRUE if WMASK overwrites anything in REGS. */
7828
7829static bfd_boolean
7830bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
7831{
7832 int i;
906e58ca 7833
c7b8f16e
JB		 7834 for (i = 0; i < numregs; i++)
7835 {
7836 unsigned int reg = regs[i];
7837
7838 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 7839 return TRUE;
906e58ca 7840
c7b8f16e
JB		 7841 reg -= 32;
7842
7843 if (reg >= 16)
99059e56 7844 continue;
906e58ca 7845
c7b8f16e 7846 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 7847 return TRUE;
c7b8f16e 7848 }
906e58ca 7849
c7b8f16e
JB		 7850 return FALSE;
7851}
7852
7853/* In this function, we're interested in two things: finding input registers
7854 for VFP data-processing instructions, and finding the set of registers which
7855 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
7856 hold the written set, so FLDM etc. are easy to deal with (we're only
7857 interested in 32 SP registers or 16 dp registers, due to the VFP version
7858 implemented by the chip in question). DP registers are marked by setting
7859 both SP registers in the write mask). */
7860
7861static enum bfd_arm_vfp11_pipe
7862bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 7863 int *numregs)
c7b8f16e 7864{
91d6fa6a 7865 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 7866 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
7867
7868 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
7869 {
7870 unsigned int pqrs;
7871 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7872 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
7873
7874 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 7875 | ((insn & 0x00300000) >> 19)
7876 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 7877
7878 switch (pqrs)
99059e56
RM		 7879 {
7880 case 0: /* fmac[sd]. */
7881 case 1: /* fnmac[sd]. */
7882 case 2: /* fmsc[sd]. */
7883 case 3: /* fnmsc[sd]. */
7884 vpipe = VFP11_FMAC;
7885 bfd_arm_vfp11_write_mask (destmask, fd);
7886 regs[0] = fd;
7887 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7888 regs[2] = fm;
7889 *numregs = 3;
7890 break;
7891
7892 case 4: /* fmul[sd]. */
7893 case 5: /* fnmul[sd]. */
7894 case 6: /* fadd[sd]. */
7895 case 7: /* fsub[sd]. */
7896 vpipe = VFP11_FMAC;
7897 goto vfp_binop;
7898
7899 case 8: /* fdiv[sd]. */
7900 vpipe = VFP11_DS;
7901 vfp_binop:
7902 bfd_arm_vfp11_write_mask (destmask, fd);
7903 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7904 regs[1] = fm;
7905 *numregs = 2;
7906 break;
7907
7908 case 15: /* extended opcode. */
7909 {
7910 unsigned int extn = ((insn >> 15) & 0x1e)
7911 | ((insn >> 7) & 1);
7912
7913 switch (extn)
7914 {
7915 case 0: /* fcpy[sd]. */
7916 case 1: /* fabs[sd]. */
7917 case 2: /* fneg[sd]. */
7918 case 8: /* fcmp[sd]. */
7919 case 9: /* fcmpe[sd]. */
7920 case 10: /* fcmpz[sd]. */
7921 case 11: /* fcmpez[sd]. */
7922 case 16: /* fuito[sd]. */
7923 case 17: /* fsito[sd]. */
7924 case 24: /* ftoui[sd]. */
7925 case 25: /* ftouiz[sd]. */
7926 case 26: /* ftosi[sd]. */
7927 case 27: /* ftosiz[sd]. */
7928 /* These instructions will not bounce due to underflow. */
7929 *numregs = 0;
7930 vpipe = VFP11_FMAC;
7931 break;
7932
7933 case 3: /* fsqrt[sd]. */
7934 /* fsqrt cannot underflow, but it can (perhaps) overwrite
7935 registers to cause the erratum in previous instructions. */
7936 bfd_arm_vfp11_write_mask (destmask, fd);
7937 vpipe = VFP11_DS;
7938 break;
7939
7940 case 15: /* fcvt{ds,sd}. */
7941 {
7942 int rnum = 0;
7943
7944 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 7945
7946 /* Only FCVTSD can underflow. */
99059e56
RM		 7947 if ((insn & 0x100) != 0)
7948 regs[rnum++] = fm;
c7b8f16e 7949
99059e56 7950 *numregs = rnum;
c7b8f16e 7951
99059e56
RM		 7952 vpipe = VFP11_FMAC;
7953 }
7954 break;
c7b8f16e 7955
99059e56
RM		 7956 default:
7957 return VFP11_BAD;
7958 }
7959 }
7960 break;
c7b8f16e 7961
99059e56
RM		 7962 default:
7963 return VFP11_BAD;
7964 }
c7b8f16e
JB		 7965 }
7966 /* Two-register transfer. */
7967 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
7968 {
7969 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 7970
c7b8f16e
JB		 7971 if ((insn & 0x100000) == 0)
7972 {
99059e56
RM		 7973 if (is_double)
7974 bfd_arm_vfp11_write_mask (destmask, fm);
7975 else
7976 {
7977 bfd_arm_vfp11_write_mask (destmask, fm);
7978 bfd_arm_vfp11_write_mask (destmask, fm + 1);
7979 }
c7b8f16e
JB		 7980 }
7981
91d6fa6a 7982 vpipe = VFP11_LS;
c7b8f16e
JB		 7983 }
7984 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
7985 {
7986 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7987 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 7988
c7b8f16e 7989 switch (puw)
99059e56
RM		 7990 {
7991 case 0: /* Two-reg transfer. We should catch these above. */
7992 abort ();
906e58ca 7993
99059e56
RM		 7994 case 2: /* fldm[sdx]. */
7995 case 3:
7996 case 5:
7997 {
7998 unsigned int i, offset = insn & 0xff;
c7b8f16e 7999
99059e56
RM		 8000 if (is_double)
8001 offset >>= 1;
c7b8f16e 8002
99059e56
RM		 8003 for (i = fd; i < fd + offset; i++)
8004 bfd_arm_vfp11_write_mask (destmask, i);
8005 }
8006 break;
906e58ca 8007
99059e56
RM		 8008 case 4: /* fld[sd]. */
8009 case 6:
8010 bfd_arm_vfp11_write_mask (destmask, fd);
8011 break;
906e58ca 8012
99059e56
RM		 8013 default:
8014 return VFP11_BAD;
8015 }
c7b8f16e 8016
91d6fa6a 8017 vpipe = VFP11_LS;
c7b8f16e
JB		 8018 }
8019 /* Single-register transfer. Note L==0. */
8020 else if ((insn & 0x0f100e10) == 0x0e000a10)
8021 {
8022 unsigned int opcode = (insn >> 21) & 7;
8023 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8024
8025 switch (opcode)
99059e56
RM		 8026 {
8027 case 0: /* fmsr/fmdlr. */
8028 case 1: /* fmdhr. */
8029 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8030 destination register. I don't know if this is exactly right,
8031 but it is the conservative choice. */
8032 bfd_arm_vfp11_write_mask (destmask, fn);
8033 break;
8034
8035 case 7: /* fmxr. */
8036 break;
8037 }
c7b8f16e 8038
91d6fa6a 8039 vpipe = VFP11_LS;
c7b8f16e
JB		 8040 }
8041
91d6fa6a 8042 return vpipe;
c7b8f16e
JB		 8043}
8044
8045
8046static int elf32_arm_compare_mapping (const void * a, const void * b);
8047
8048
8049/* Look for potentially-troublesome code sequences which might trigger the
8050 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8051 (available from ARM) for details of the erratum. A short version is
8052 described in ld.texinfo. */
8053
8054bfd_boolean
8055bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8056{
8057 asection *sec;
8058 bfd_byte *contents = NULL;
8059 int state = 0;
8060 int regs[3], numregs = 0;
8061 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8062 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8063
4dfe6ac6
NC		 8064 if (globals == NULL)
8065 return FALSE;
8066
c7b8f16e
JB		 8067 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8068 The states transition as follows:
906e58ca 8069
c7b8f16e 8070 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8071 A VFP FMAC-pipeline instruction has been seen. Fill
8072 regs[0]..regs[numregs-1] with its input operands. Remember this
8073 instruction in 'first_fmac'.
c7b8f16e
JB		 8074
8075 1 -> 2
99059e56
RM		 8076 Any instruction, except for a VFP instruction which overwrites
8077 regs[*].
906e58ca 8078
c7b8f16e
JB		 8079 1 -> 3 [ -> 0 ] or
8080 2 -> 3 [ -> 0 ]
99059e56
RM		 8081 A VFP instruction has been seen which overwrites any of regs[*].
8082 We must make a veneer! Reset state to 0 before examining next
8083 instruction.
906e58ca 8084
c7b8f16e 8085 2 -> 0
99059e56
RM		 8086 If we fail to match anything in state 2, reset to state 0 and reset
8087 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8088
8089 If the VFP11 vector mode is in use, there must be at least two unrelated
8090 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8091 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8092
8093 /* If we are only performing a partial link do not bother
8094 to construct any glue. */
0e1862bb 8095 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8096 return TRUE;
8097
0ffa91dd
NC		 8098 /* Skip if this bfd does not correspond to an ELF image. */
8099 if (! is_arm_elf (abfd))
8100 return TRUE;
906e58ca 8101
c7b8f16e
JB		 8102 /* We should have chosen a fix type by the time we get here. */
8103 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8104
8105 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8106 return TRUE;
2e6030b9 8107
33a7ffc2
JM		 8108 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8109 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8110 return TRUE;
8111
c7b8f16e
JB		 8112 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8113 {
8114 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8115 struct _arm_elf_section_data *sec_data;
8116
8117 /* If we don't have executable progbits, we're not interested in this
99059e56 8118 section. Also skip if section is to be excluded. */
c7b8f16e 8119 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8120 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8121 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8122 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8123 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8124 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8125 continue;
c7b8f16e
JB		 8126
8127 sec_data = elf32_arm_section_data (sec);
906e58ca 8128
c7b8f16e 8129 if (sec_data->mapcount == 0)
99059e56 8130 continue;
906e58ca 8131
c7b8f16e
JB		 8132 if (elf_section_data (sec)->this_hdr.contents != NULL)
8133 contents = elf_section_data (sec)->this_hdr.contents;
8134 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8135 goto error_return;
8136
8137 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8138 elf32_arm_compare_mapping);
8139
8140 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8141 {
8142 unsigned int span_start = sec_data->map[span].vma;
8143 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8144 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8145 char span_type = sec_data->map[span].type;
8146
8147 /* FIXME: Only ARM mode is supported at present. We may need to
8148 support Thumb-2 mode also at some point. */
8149 if (span_type != 'a')
8150 continue;
8151
8152 for (i = span_start; i < span_end;)
8153 {
8154 unsigned int next_i = i + 4;
8155 unsigned int insn = bfd_big_endian (abfd)
8156 ? (contents[i] << 24)
8157 | (contents[i + 1] << 16)
8158 | (contents[i + 2] << 8)
8159 | contents[i + 3]
8160 : (contents[i + 3] << 24)
8161 | (contents[i + 2] << 16)
8162 | (contents[i + 1] << 8)
8163 | contents[i];
8164 unsigned int writemask = 0;
8165 enum bfd_arm_vfp11_pipe vpipe;
8166
8167 switch (state)
8168 {
8169 case 0:
8170 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8171 &numregs);
8172 /* I'm assuming the VFP11 erratum can trigger with denorm
8173 operands on either the FMAC or the DS pipeline. This might
8174 lead to slightly overenthusiastic veneer insertion. */
8175 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8176 {
8177 state = use_vector ? 1 : 2;
8178 first_fmac = i;
8179 veneer_of_insn = insn;
8180 }
8181 break;
8182
8183 case 1:
8184 {
8185 int other_regs[3], other_numregs;
8186 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8187 other_regs,
99059e56
RM		 8188 &other_numregs);
8189 if (vpipe != VFP11_BAD
8190 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8191 numregs))
99059e56
RM		 8192 state = 3;
8193 else
8194 state = 2;
8195 }
8196 break;
8197
8198 case 2:
8199 {
8200 int other_regs[3], other_numregs;
8201 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8202 other_regs,
99059e56
RM		 8203 &other_numregs);
8204 if (vpipe != VFP11_BAD
8205 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8206 numregs))
99059e56
RM		 8207 state = 3;
8208 else
8209 {
8210 state = 0;
8211 next_i = first_fmac + 4;
8212 }
8213 }
8214 break;
8215
8216 case 3:
8217 abort (); /* Should be unreachable. */
8218 }
8219
8220 if (state == 3)
8221 {
8222 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8223 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8224
8225 elf32_arm_section_data (sec)->erratumcount += 1;
8226
8227 newerr->u.b.vfp_insn = veneer_of_insn;
8228
8229 switch (span_type)
8230 {
8231 case 'a':
8232 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8233 break;
8234
8235 default:
8236 abort ();
8237 }
8238
8239 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8240 first_fmac);
8241
99059e56 8242 newerr->vma = -1;
c7b8f16e 8243
99059e56
RM		 8244 newerr->next = sec_data->erratumlist;
8245 sec_data->erratumlist = newerr;
c7b8f16e 8246
99059e56
RM		 8247 state = 0;
8248 }
c7b8f16e 8249
99059e56
RM		 8250 i = next_i;
8251 }
8252 }
906e58ca 8253
c7b8f16e 8254 if (contents != NULL
99059e56
RM		 8255 && elf_section_data (sec)->this_hdr.contents != contents)
8256 free (contents);
c7b8f16e
JB		 8257 contents = NULL;
8258 }
8259
8260 return TRUE;
8261
8262error_return:
8263 if (contents != NULL
8264 && elf_section_data (sec)->this_hdr.contents != contents)
8265 free (contents);
906e58ca 8266
c7b8f16e
JB		 8267 return FALSE;
8268}
8269
8270/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8271 after sections have been laid out, using specially-named symbols. */
8272
8273void
8274bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8275 struct bfd_link_info *link_info)
8276{
8277 asection *sec;
8278 struct elf32_arm_link_hash_table *globals;
8279 char *tmp_name;
906e58ca 8280
0e1862bb 8281 if (bfd_link_relocatable (link_info))
c7b8f16e 8282 return;
2e6030b9
MS		 8283
8284 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8285 if (! is_arm_elf (abfd))
2e6030b9
MS		 8286 return;
8287
c7b8f16e 8288 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8289 if (globals == NULL)
8290 return;
906e58ca 8291
21d799b5 8292 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8293 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8294
8295 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8296 {
8297 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8298 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8299
c7b8f16e 8300 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8301 {
8302 struct elf_link_hash_entry *myh;
8303 bfd_vma vma;
8304
8305 switch (errnode->type)
8306 {
8307 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8308 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8309 /* Find veneer symbol. */
8310 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8311 errnode->u.b.veneer->u.v.id);
8312
99059e56
RM		 8313 myh = elf_link_hash_lookup
8314 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8315
a504d23a 8316 if (myh == NULL)
90b6238f
AM		 8317 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8318 abfd, "VFP11", tmp_name);
a504d23a
LA		 8319
8320 vma = myh->root.u.def.section->output_section->vma
8321 + myh->root.u.def.section->output_offset
8322 + myh->root.u.def.value;
8323
8324 errnode->u.b.veneer->vma = vma;
8325 break;
8326
8327 case VFP11_ERRATUM_ARM_VENEER:
8328 case VFP11_ERRATUM_THUMB_VENEER:
8329 /* Find return location. */
8330 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8331 errnode->u.v.id);
8332
8333 myh = elf_link_hash_lookup
8334 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8335
8336 if (myh == NULL)
90b6238f
AM		 8337 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8338 abfd, "VFP11", tmp_name);
a504d23a
LA		 8339
8340 vma = myh->root.u.def.section->output_section->vma
8341 + myh->root.u.def.section->output_offset
8342 + myh->root.u.def.value;
8343
8344 errnode->u.v.branch->vma = vma;
8345 break;
8346
8347 default:
8348 abort ();
8349 }
8350 }
8351 }
8352
8353 free (tmp_name);
8354}
8355
8356/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8357 return locations after sections have been laid out, using
8358 specially-named symbols. */
8359
8360void
8361bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8362 struct bfd_link_info *link_info)
8363{
8364 asection *sec;
8365 struct elf32_arm_link_hash_table *globals;
8366 char *tmp_name;
8367
8368 if (bfd_link_relocatable (link_info))
8369 return;
8370
8371 /* Skip if this bfd does not correspond to an ELF image. */
8372 if (! is_arm_elf (abfd))
8373 return;
8374
8375 globals = elf32_arm_hash_table (link_info);
8376 if (globals == NULL)
8377 return;
8378
8379 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8380 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8381
8382 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8383 {
8384 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8385 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8386
8387 for (; errnode != NULL; errnode = errnode->next)
8388 {
8389 struct elf_link_hash_entry *myh;
8390 bfd_vma vma;
8391
8392 switch (errnode->type)
8393 {
8394 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8395 /* Find veneer symbol. */
8396 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8397 errnode->u.b.veneer->u.v.id);
8398
8399 myh = elf_link_hash_lookup
8400 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8401
8402 if (myh == NULL)
90b6238f
AM		 8403 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8404 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8405
8406 vma = myh->root.u.def.section->output_section->vma
8407 + myh->root.u.def.section->output_offset
8408 + myh->root.u.def.value;
8409
8410 errnode->u.b.veneer->vma = vma;
8411 break;
8412
8413 case STM32L4XX_ERRATUM_VENEER:
8414 /* Find return location. */
8415 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8416 errnode->u.v.id);
8417
8418 myh = elf_link_hash_lookup
8419 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8420
8421 if (myh == NULL)
90b6238f
AM		 8422 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8423 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8424
8425 vma = myh->root.u.def.section->output_section->vma
8426 + myh->root.u.def.section->output_offset
8427 + myh->root.u.def.value;
8428
8429 errnode->u.v.branch->vma = vma;
8430 break;
8431
8432 default:
8433 abort ();
8434 }
8435 }
8436 }
8437
8438 free (tmp_name);
8439}
8440
8441static inline bfd_boolean
8442is_thumb2_ldmia (const insn32 insn)
8443{
8444 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8445 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8446 return (insn & 0xffd02000) == 0xe8900000;
8447}
8448
8449static inline bfd_boolean
8450is_thumb2_ldmdb (const insn32 insn)
8451{
8452 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8453 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8454 return (insn & 0xffd02000) == 0xe9100000;
8455}
8456
8457static inline bfd_boolean
8458is_thumb2_vldm (const insn32 insn)
8459{
8460 /* A6.5 Extension register load or store instruction
8461 A7.7.229
9239bbd3
CM		 8462 We look for SP 32-bit and DP 64-bit registers.
8463 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8464 <list> is consecutive 64-bit registers
8465 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8466 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8467 <list> is consecutive 32-bit registers
8468 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8469 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8470 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8471 return
9239bbd3
CM		 8472 (((insn & 0xfe100f00) == 0xec100b00) ||
8473 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8474 && /* (IA without !). */
8475 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8476 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8477 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8478 /* (DB with !). */
8479 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8480}
8481
8482/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8483 VLDM opcode and:
8484 - computes the number and the mode of memory accesses
8485 - decides if the replacement should be done:
8486 . replaces only if > 8-word accesses
8487 . or (testing purposes only) replaces all accesses. */
8488
8489static bfd_boolean
8490stm32l4xx_need_create_replacing_stub (const insn32 insn,
8491 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8492{
9239bbd3 8493 int nb_words = 0;
a504d23a
LA		 8494
8495 /* The field encoding the register list is the same for both LDMIA
8496 and LDMDB encodings. */
8497 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8498 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8499 else if (is_thumb2_vldm (insn))
9239bbd3 8500 nb_words = (insn & 0xff);
a504d23a
LA		 8501
8502 /* DEFAULT mode accounts for the real bug condition situation,
8503 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8504 return
9239bbd3 8505 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8506 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8507}
8508
8509/* Look for potentially-troublesome code sequences which might trigger
8510 the STM STM32L4XX erratum. */
8511
8512bfd_boolean
8513bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8514 struct bfd_link_info *link_info)
8515{
8516 asection *sec;
8517 bfd_byte *contents = NULL;
8518 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8519
8520 if (globals == NULL)
8521 return FALSE;
8522
8523 /* If we are only performing a partial link do not bother
8524 to construct any glue. */
8525 if (bfd_link_relocatable (link_info))
8526 return TRUE;
8527
8528 /* Skip if this bfd does not correspond to an ELF image. */
8529 if (! is_arm_elf (abfd))
8530 return TRUE;
8531
8532 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8533 return TRUE;
8534
8535 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8536 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8537 return TRUE;
8538
8539 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8540 {
8541 unsigned int i, span;
8542 struct _arm_elf_section_data *sec_data;
8543
8544 /* If we don't have executable progbits, we're not interested in this
8545 section. Also skip if section is to be excluded. */
8546 if (elf_section_type (sec) != SHT_PROGBITS
8547 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8548 || (sec->flags & SEC_EXCLUDE) != 0
8549 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8550 || sec->output_section == bfd_abs_section_ptr
8551 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8552 continue;
8553
8554 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8555
a504d23a
LA		 8556 if (sec_data->mapcount == 0)
8557 continue;
c7b8f16e 8558
a504d23a
LA		 8559 if (elf_section_data (sec)->this_hdr.contents != NULL)
8560 contents = elf_section_data (sec)->this_hdr.contents;
8561 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8562 goto error_return;
c7b8f16e 8563
a504d23a
LA		 8564 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8565 elf32_arm_compare_mapping);
c7b8f16e 8566
a504d23a
LA		 8567 for (span = 0; span < sec_data->mapcount; span++)
8568 {
8569 unsigned int span_start = sec_data->map[span].vma;
8570 unsigned int span_end = (span == sec_data->mapcount - 1)
8571 ? sec->size : sec_data->map[span + 1].vma;
8572 char span_type = sec_data->map[span].type;
8573 int itblock_current_pos = 0;
c7b8f16e 8574
a504d23a
LA		 8575 /* Only Thumb2 mode need be supported with this CM4 specific
8576 code, we should not encounter any arm mode eg span_type
8577 != 'a'. */
8578 if (span_type != 't')
8579 continue;
c7b8f16e 8580
a504d23a
LA		 8581 for (i = span_start; i < span_end;)
8582 {
8583 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8584 bfd_boolean insn_32bit = FALSE;
8585 bfd_boolean is_ldm = FALSE;
8586 bfd_boolean is_vldm = FALSE;
8587 bfd_boolean is_not_last_in_it_block = FALSE;
8588
8589 /* The first 16-bits of all 32-bit thumb2 instructions start
8590 with opcode[15..13]=0b111 and the encoded op1 can be anything
8591 except opcode[12..11]!=0b00.
8592 See 32-bit Thumb instruction encoding. */
8593 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8594 insn_32bit = TRUE;
c7b8f16e 8595
a504d23a
LA		 8596 /* Compute the predicate that tells if the instruction
8597 is concerned by the IT block
8598 - Creates an error if there is a ldm that is not
8599 last in the IT block thus cannot be replaced
8600 - Otherwise we can create a branch at the end of the
8601 IT block, it will be controlled naturally by IT
8602 with the proper pseudo-predicate
8603 - So the only interesting predicate is the one that
8604 tells that we are not on the last item of an IT
8605 block. */
8606 if (itblock_current_pos != 0)
8607 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8608
a504d23a
LA		 8609 if (insn_32bit)
8610 {
8611 /* Load the rest of the insn (in manual-friendly order). */
8612 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8613 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8614 is_vldm = is_thumb2_vldm (insn);
8615
8616 /* Veneers are created for (v)ldm depending on
8617 option flags and memory accesses conditions; but
8618 if the instruction is not the last instruction of
8619 an IT block, we cannot create a jump there, so we
8620 bail out. */
5025eb7c
AO		 8621 if ((is_ldm || is_vldm)
8622 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8623 (insn, globals->stm32l4xx_fix))
8624 {
8625 if (is_not_last_in_it_block)
8626 {
4eca0228 8627 _bfd_error_handler
695344c0 8628 /* xgettext:c-format */
871b3ab2 8629 (_("%pB(%pA+%#x): error: multiple load detected"
90b6238f
AM		 8630 " in non-last IT block instruction:"
8631 " STM32L4XX veneer cannot be generated; "
8632 "use gcc option -mrestrict-it to generate"
8633 " only one instruction per IT block"),
d42c267e 8634 abfd, sec, i);
a504d23a
LA		 8635 }
8636 else
8637 {
8638 elf32_stm32l4xx_erratum_list *newerr =
8639 (elf32_stm32l4xx_erratum_list *)
8640 bfd_zmalloc
8641 (sizeof (elf32_stm32l4xx_erratum_list));
8642
8643 elf32_arm_section_data (sec)
8644 ->stm32l4xx_erratumcount += 1;
8645 newerr->u.b.insn = insn;
8646 /* We create only thumb branches. */
8647 newerr->type =
8648 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8649 record_stm32l4xx_erratum_veneer
8650 (link_info, newerr, abfd, sec,
8651 i,
8652 is_ldm ?
8653 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8654 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8655 newerr->vma = -1;
8656 newerr->next = sec_data->stm32l4xx_erratumlist;
8657 sec_data->stm32l4xx_erratumlist = newerr;
8658 }
8659 }
8660 }
8661 else
8662 {
8663 /* A7.7.37 IT p208
8664 IT blocks are only encoded in T1
8665 Encoding T1: IT{x{y{z}}} <firstcond>
8666 1 0 1 1 - 1 1 1 1 - firstcond - mask
8667 if mask = '0000' then see 'related encodings'
8668 We don't deal with UNPREDICTABLE, just ignore these.
8669 There can be no nested IT blocks so an IT block
8670 is naturally a new one for which it is worth
8671 computing its size. */
5025eb7c
AO		 8672 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
8673 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 8674 /* If we have a new IT block we compute its size. */
8675 if (is_newitblock)
8676 {
8677 /* Compute the number of instructions controlled
8678 by the IT block, it will be used to decide
8679 whether we are inside an IT block or not. */
8680 unsigned int mask = insn & 0x000f;
8681 itblock_current_pos = 4 - ctz (mask);
8682 }
8683 }
8684
8685 i += insn_32bit ? 4 : 2;
99059e56
RM		 8686 }
8687 }
a504d23a
LA		 8688
8689 if (contents != NULL
8690 && elf_section_data (sec)->this_hdr.contents != contents)
8691 free (contents);
8692 contents = NULL;
c7b8f16e 8693 }
906e58ca 8694
a504d23a
LA		 8695 return TRUE;
8696
8697error_return:
8698 if (contents != NULL
8699 && elf_section_data (sec)->this_hdr.contents != contents)
8700 free (contents);
c7b8f16e 8701
a504d23a
LA		 8702 return FALSE;
8703}
c7b8f16e 8704
eb043451
PB		 8705/* Set target relocation values needed during linking. */
8706
8707void
68c39892 8708bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 8709 struct bfd_link_info *link_info,
68c39892 8710 struct elf32_arm_params *params)
eb043451
PB		 8711{
8712 struct elf32_arm_link_hash_table *globals;
8713
8714 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8715 if (globals == NULL)
8716 return;
eb043451 8717
68c39892
TP		 8718 globals->target1_is_rel = params->target1_is_rel;
8719 if (strcmp (params->target2_type, "rel") == 0)
eb043451 8720 globals->target2_reloc = R_ARM_REL32;
68c39892 8721 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 8722 globals->target2_reloc = R_ARM_ABS32;
68c39892 8723 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 8724 globals->target2_reloc = R_ARM_GOT_PREL;
8725 else
8726 {
90b6238f 8727 _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"),
68c39892 8728 params->target2_type);
eb043451 8729 }
68c39892
TP		 8730 globals->fix_v4bx = params->fix_v4bx;
8731 globals->use_blx |= params->use_blx;
8732 globals->vfp11_fix = params->vfp11_denorm_fix;
8733 globals->stm32l4xx_fix = params->stm32l4xx_fix;
8734 globals->pic_veneer = params->pic_veneer;
8735 globals->fix_cortex_a8 = params->fix_cortex_a8;
8736 globals->fix_arm1176 = params->fix_arm1176;
8737 globals->cmse_implib = params->cmse_implib;
8738 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 8739
0ffa91dd 8740 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 8741 elf_arm_tdata (output_bfd)->no_enum_size_warning
8742 = params->no_enum_size_warning;
8743 elf_arm_tdata (output_bfd)->no_wchar_size_warning
8744 = params->no_wchar_size_warning;
eb043451 8745}
eb043451 8746
12a0a0fd 8747/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 8748
12a0a0fd
PB		 8749static void
8750insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
8751{
8752 bfd_vma upper;
8753 bfd_vma lower;
8754 int reloc_sign;
8755
8756 BFD_ASSERT ((offset & 1) == 0);
8757
8758 upper = bfd_get_16 (abfd, insn);
8759 lower = bfd_get_16 (abfd, insn + 2);
8760 reloc_sign = (offset < 0) ? 1 : 0;
8761 upper = (upper & ~(bfd_vma) 0x7ff)
8762 | ((offset >> 12) & 0x3ff)
8763 | (reloc_sign << 10);
906e58ca 8764 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 8765 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
8766 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
8767 | ((offset >> 1) & 0x7ff);
8768 bfd_put_16 (abfd, upper, insn);
8769 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 8770}
8771
9b485d32
NC		 8772/* Thumb code calling an ARM function. */
8773
252b5132 8774static int
57e8b36a 8775elf32_thumb_to_arm_stub (struct bfd_link_info * info,
07d6d2b8
AM		 8776 const char * name,
8777 bfd * input_bfd,
8778 bfd * output_bfd,
8779 asection * input_section,
8780 bfd_byte * hit_data,
8781 asection * sym_sec,
8782 bfd_vma offset,
8783 bfd_signed_vma addend,
8784 bfd_vma val,
f2a9dd69 8785 char **error_message)
252b5132 8786{
bcbdc74c 8787 asection * s = 0;
dc810e39 8788 bfd_vma my_offset;
252b5132 8789 long int ret_offset;
bcbdc74c
NC		 8790 struct elf_link_hash_entry * myh;
8791 struct elf32_arm_link_hash_table * globals;
252b5132 8792
f2a9dd69 8793 myh = find_thumb_glue (info, name, error_message);
252b5132 8794 if (myh == NULL)
b34976b6 8795 return FALSE;
252b5132
RH		 8796
8797 globals = elf32_arm_hash_table (info);
252b5132
RH		 8798 BFD_ASSERT (globals != NULL);
8799 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8800
8801 my_offset = myh->root.u.def.value;
8802
3d4d4302
AM		 8803 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8804 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 8805
8806 BFD_ASSERT (s != NULL);
8807 BFD_ASSERT (s->contents != NULL);
8808 BFD_ASSERT (s->output_section != NULL);
8809
8810 if ((my_offset & 0x01) == 0x01)
8811 {
8812 if (sym_sec != NULL
8813 && sym_sec->owner != NULL
8814 && !INTERWORK_FLAG (sym_sec->owner))
8815 {
4eca0228 8816 _bfd_error_handler
90b6238f
AM		 8817 (_("%pB(%s): warning: interworking not enabled;"
8818 " first occurrence: %pB: %s call to %s"),
8819 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
252b5132 8820
b34976b6 8821 return FALSE;
252b5132
RH		 8822 }
8823
8824 --my_offset;
8825 myh->root.u.def.value = my_offset;
8826
52ab56c2
PB		 8827 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
8828 s->contents + my_offset);
252b5132 8829
52ab56c2
PB		 8830 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
8831 s->contents + my_offset + 2);
252b5132
RH		 8832
8833 ret_offset =
9b485d32
NC		 8834 /* Address of destination of the stub. */
8835 ((bfd_signed_vma) val)
252b5132 8836 - ((bfd_signed_vma)
57e8b36a
NC		 8837 /* Offset from the start of the current section
8838 to the start of the stubs. */
9b485d32
NC		 8839 (s->output_offset
8840 /* Offset of the start of this stub from the start of the stubs. */
8841 + my_offset
8842 /* Address of the start of the current section. */
8843 + s->output_section->vma)
8844 /* The branch instruction is 4 bytes into the stub. */
8845 + 4
8846 /* ARM branches work from the pc of the instruction + 8. */
8847 + 8);
252b5132 8848
52ab56c2
PB		 8849 put_arm_insn (globals, output_bfd,
8850 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
8851 s->contents + my_offset + 4);
252b5132
RH		 8852 }
8853
8854 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
8855
427bfd90
NC		 8856 /* Now go back and fix up the original BL insn to point to here. */
8857 ret_offset =
8858 /* Address of where the stub is located. */
8859 (s->output_section->vma + s->output_offset + my_offset)
8860 /* Address of where the BL is located. */
57e8b36a
NC		 8861 - (input_section->output_section->vma + input_section->output_offset
8862 + offset)
427bfd90
NC		 8863 /* Addend in the relocation. */
8864 - addend
8865 /* Biassing for PC-relative addressing. */
8866 - 8;
252b5132 8867
12a0a0fd 8868 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 8869
b34976b6 8870 return TRUE;
252b5132
RH		 8871}
8872
a4fd1a8e 8873/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 8874
a4fd1a8e
PB		 8875static struct elf_link_hash_entry *
8876elf32_arm_create_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 8877 const char * name,
8878 bfd * input_bfd,
8879 bfd * output_bfd,
8880 asection * sym_sec,
8881 bfd_vma val,
8882 asection * s,
8883 char ** error_message)
252b5132 8884{
dc810e39 8885 bfd_vma my_offset;
252b5132 8886 long int ret_offset;
bcbdc74c
NC		 8887 struct elf_link_hash_entry * myh;
8888 struct elf32_arm_link_hash_table * globals;
252b5132 8889
f2a9dd69 8890 myh = find_arm_glue (info, name, error_message);
252b5132 8891 if (myh == NULL)
a4fd1a8e 8892 return NULL;
252b5132
RH		 8893
8894 globals = elf32_arm_hash_table (info);
252b5132
RH		 8895 BFD_ASSERT (globals != NULL);
8896 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8897
8898 my_offset = myh->root.u.def.value;
252b5132
RH		 8899
8900 if ((my_offset & 0x01) == 0x01)
8901 {
8902 if (sym_sec != NULL
8903 && sym_sec->owner != NULL
8904 && !INTERWORK_FLAG (sym_sec->owner))
8905 {
4eca0228 8906 _bfd_error_handler
90b6238f
AM		 8907 (_("%pB(%s): warning: interworking not enabled;"
8908 " first occurrence: %pB: %s call to %s"),
8909 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
252b5132 8910 }
9b485d32 8911
252b5132
RH		 8912 --my_offset;
8913 myh->root.u.def.value = my_offset;
8914
0e1862bb
L		 8915 if (bfd_link_pic (info)
8916 || globals->root.is_relocatable_executable
27e55c4d 8917 || globals->pic_veneer)
8f6277f5
PB		 8918 {
8919 /* For relocatable objects we can't use absolute addresses,
8920 so construct the address from a relative offset. */
8921 /* TODO: If the offset is small it's probably worth
8922 constructing the address with adds. */
52ab56c2
PB		 8923 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
8924 s->contents + my_offset);
8925 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
8926 s->contents + my_offset + 4);
8927 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
8928 s->contents + my_offset + 8);
8f6277f5
PB		 8929 /* Adjust the offset by 4 for the position of the add,
8930 and 8 for the pipeline offset. */
8931 ret_offset = (val - (s->output_offset
8932 + s->output_section->vma
8933 + my_offset + 12))
8934 | 1;
8935 bfd_put_32 (output_bfd, ret_offset,
8936 s->contents + my_offset + 12);
8937 }
26079076
PB		 8938 else if (globals->use_blx)
8939 {
8940 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
8941 s->contents + my_offset);
8942
8943 /* It's a thumb address. Add the low order bit. */
8944 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
8945 s->contents + my_offset + 4);
8946 }
8f6277f5
PB		 8947 else
8948 {
52ab56c2
PB		 8949 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
8950 s->contents + my_offset);
252b5132 8951
52ab56c2
PB		 8952 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
8953 s->contents + my_offset + 4);
252b5132 8954
8f6277f5
PB		 8955 /* It's a thumb address. Add the low order bit. */
8956 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
8957 s->contents + my_offset + 8);
8029a119
NC		 8958
8959 my_offset += 12;
8f6277f5 8960 }
252b5132
RH		 8961 }
8962
8963 BFD_ASSERT (my_offset <= globals->arm_glue_size);
8964
a4fd1a8e
PB		 8965 return myh;
8966}
8967
8968/* Arm code calling a Thumb function. */
8969
8970static int
8971elf32_arm_to_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 8972 const char * name,
8973 bfd * input_bfd,
8974 bfd * output_bfd,
8975 asection * input_section,
8976 bfd_byte * hit_data,
8977 asection * sym_sec,
8978 bfd_vma offset,
8979 bfd_signed_vma addend,
8980 bfd_vma val,
f2a9dd69 8981 char **error_message)
a4fd1a8e
PB		 8982{
8983 unsigned long int tmp;
8984 bfd_vma my_offset;
8985 asection * s;
8986 long int ret_offset;
8987 struct elf_link_hash_entry * myh;
8988 struct elf32_arm_link_hash_table * globals;
8989
8990 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8991 BFD_ASSERT (globals != NULL);
8992 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8993
3d4d4302
AM		 8994 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8995 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8996 BFD_ASSERT (s != NULL);
8997 BFD_ASSERT (s->contents != NULL);
8998 BFD_ASSERT (s->output_section != NULL);
8999
9000 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 9001 sym_sec, val, s, error_message);
a4fd1a8e
PB		 9002 if (!myh)
9003 return FALSE;
9004
9005 my_offset = myh->root.u.def.value;
252b5132
RH		 9006 tmp = bfd_get_32 (input_bfd, hit_data);
9007 tmp = tmp & 0xFF000000;
9008
9b485d32 9009 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9010 ret_offset = (s->output_offset
9011 + my_offset
9012 + s->output_section->vma
9013 - (input_section->output_offset
9014 + input_section->output_section->vma
9015 + offset + addend)
9016 - 8);
9a5aca8c 9017
252b5132
RH		 9018 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9019
dc810e39 9020 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9021
b34976b6 9022 return TRUE;
252b5132
RH		 9023}
9024
a4fd1a8e
PB		 9025/* Populate Arm stub for an exported Thumb function. */
9026
9027static bfd_boolean
9028elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9029{
9030 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9031 asection * s;
9032 struct elf_link_hash_entry * myh;
9033 struct elf32_arm_link_hash_entry *eh;
9034 struct elf32_arm_link_hash_table * globals;
9035 asection *sec;
9036 bfd_vma val;
f2a9dd69 9037 char *error_message;
a4fd1a8e 9038
906e58ca 9039 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9040 /* Allocate stubs for exported Thumb functions on v4t. */
9041 if (eh->export_glue == NULL)
9042 return TRUE;
9043
9044 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9045 BFD_ASSERT (globals != NULL);
9046 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9047
3d4d4302
AM		 9048 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9049 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9050 BFD_ASSERT (s != NULL);
9051 BFD_ASSERT (s->contents != NULL);
9052 BFD_ASSERT (s->output_section != NULL);
9053
9054 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9055
9056 BFD_ASSERT (sec->output_section != NULL);
9057
a4fd1a8e
PB		 9058 val = eh->export_glue->root.u.def.value + sec->output_offset
9059 + sec->output_section->vma;
8029a119 9060
a4fd1a8e
PB		 9061 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9062 h->root.u.def.section->owner,
f2a9dd69
DJ		 9063 globals->obfd, sec, val, s,
9064 &error_message);
a4fd1a8e
PB		 9065 BFD_ASSERT (myh);
9066 return TRUE;
9067}
9068
845b51d6
PB		 9069/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9070
9071static bfd_vma
9072elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9073{
9074 bfd_byte *p;
9075 bfd_vma glue_addr;
9076 asection *s;
9077 struct elf32_arm_link_hash_table *globals;
9078
9079 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9080 BFD_ASSERT (globals != NULL);
9081 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9082
3d4d4302
AM		 9083 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9084 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9085 BFD_ASSERT (s != NULL);
9086 BFD_ASSERT (s->contents != NULL);
9087 BFD_ASSERT (s->output_section != NULL);
9088
9089 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9090
9091 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9092
9093 if ((globals->bx_glue_offset[reg] & 1) == 0)
9094 {
9095 p = s->contents + glue_addr;
9096 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9097 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9098 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9099 globals->bx_glue_offset[reg] |= 1;
9100 }
9101
9102 return glue_addr + s->output_section->vma + s->output_offset;
9103}
9104
a4fd1a8e
PB		 9105/* Generate Arm stubs for exported Thumb symbols. */
9106static void
906e58ca 9107elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9108 struct bfd_link_info *link_info)
9109{
9110 struct elf32_arm_link_hash_table * globals;
9111
8029a119
NC		 9112 if (link_info == NULL)
9113 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9114 return;
9115
9116 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9117 if (globals == NULL)
9118 return;
9119
84c08195
PB		 9120 /* If blx is available then exported Thumb symbols are OK and there is
9121 nothing to do. */
a4fd1a8e
PB		 9122 if (globals->use_blx)
9123 return;
9124
9125 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9126 link_info);
9127}
9128
47beaa6a
RS		 9129/* Reserve space for COUNT dynamic relocations in relocation selection
9130 SRELOC. */
9131
9132static void
9133elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9134 bfd_size_type count)
9135{
9136 struct elf32_arm_link_hash_table *htab;
9137
9138 htab = elf32_arm_hash_table (info);
9139 BFD_ASSERT (htab->root.dynamic_sections_created);
9140 if (sreloc == NULL)
9141 abort ();
9142 sreloc->size += RELOC_SIZE (htab) * count;
9143}
9144
34e77a92
RS		 9145/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9146 dynamic, the relocations should go in SRELOC, otherwise they should
9147 go in the special .rel.iplt section. */
9148
9149static void
9150elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9151 bfd_size_type count)
9152{
9153 struct elf32_arm_link_hash_table *htab;
9154
9155 htab = elf32_arm_hash_table (info);
9156 if (!htab->root.dynamic_sections_created)
9157 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9158 else
9159 {
9160 BFD_ASSERT (sreloc != NULL);
9161 sreloc->size += RELOC_SIZE (htab) * count;
9162 }
9163}
9164
47beaa6a
RS		 9165/* Add relocation REL to the end of relocation section SRELOC. */
9166
9167static void
9168elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9169 asection *sreloc, Elf_Internal_Rela *rel)
9170{
9171 bfd_byte *loc;
9172 struct elf32_arm_link_hash_table *htab;
9173
9174 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9175 if (!htab->root.dynamic_sections_created
9176 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9177 sreloc = htab->root.irelplt;
47beaa6a
RS		 9178 if (sreloc == NULL)
9179 abort ();
9180 loc = sreloc->contents;
9181 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9182 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9183 abort ();
9184 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9185}
9186
34e77a92
RS		 9187/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9188 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9189 to .plt. */
9190
9191static void
9192elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9193 bfd_boolean is_iplt_entry,
9194 union gotplt_union *root_plt,
9195 struct arm_plt_info *arm_plt)
9196{
9197 struct elf32_arm_link_hash_table *htab;
9198 asection *splt;
9199 asection *sgotplt;
9200
9201 htab = elf32_arm_hash_table (info);
9202
9203 if (is_iplt_entry)
9204 {
9205 splt = htab->root.iplt;
9206 sgotplt = htab->root.igotplt;
9207
99059e56
RM		 9208 /* NaCl uses a special first entry in .iplt too. */
9209 if (htab->nacl_p && splt->size == 0)
9210 splt->size += htab->plt_header_size;
9211
34e77a92
RS		 9212 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9213 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9214 }
9215 else
9216 {
9217 splt = htab->root.splt;
9218 sgotplt = htab->root.sgotplt;
9219
9220 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9221 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9222
9223 /* If this is the first .plt entry, make room for the special
9224 first entry. */
9225 if (splt->size == 0)
9226 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9227
9228 htab->next_tls_desc_index++;
34e77a92
RS		 9229 }
9230
9231 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9232 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9233 splt->size += PLT_THUMB_STUB_SIZE;
9234 root_plt->offset = splt->size;
9235 splt->size += htab->plt_entry_size;
9236
9237 if (!htab->symbian_p)
9238 {
9239 /* We also need to make an entry in the .got.plt section, which
9240 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9241 if (is_iplt_entry)
9242 arm_plt->got_offset = sgotplt->size;
9243 else
9244 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 9245 sgotplt->size += 4;
9246 }
9247}
9248
b38cadfb
NC		 9249static bfd_vma
9250arm_movw_immediate (bfd_vma value)
9251{
9252 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9253}
9254
9255static bfd_vma
9256arm_movt_immediate (bfd_vma value)
9257{
9258 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9259}
9260
34e77a92
RS		 9261/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9262 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9263 Otherwise, DYNINDX is the index of the symbol in the dynamic
9264 symbol table and SYM_VALUE is undefined.
9265
9266 ROOT_PLT points to the offset of the PLT entry from the start of its
9267 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9268 bookkeeping information.
34e77a92 9269
57460bcf
NC		 9270 Returns FALSE if there was a problem. */
9271
9272static bfd_boolean
34e77a92
RS		 9273elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9274 union gotplt_union *root_plt,
9275 struct arm_plt_info *arm_plt,
9276 int dynindx, bfd_vma sym_value)
9277{
9278 struct elf32_arm_link_hash_table *htab;
9279 asection *sgot;
9280 asection *splt;
9281 asection *srel;
9282 bfd_byte *loc;
9283 bfd_vma plt_index;
9284 Elf_Internal_Rela rel;
9285 bfd_vma plt_header_size;
9286 bfd_vma got_header_size;
9287
9288 htab = elf32_arm_hash_table (info);
9289
9290 /* Pick the appropriate sections and sizes. */
9291 if (dynindx == -1)
9292 {
9293 splt = htab->root.iplt;
9294 sgot = htab->root.igotplt;
9295 srel = htab->root.irelplt;
9296
9297 /* There are no reserved entries in .igot.plt, and no special
9298 first entry in .iplt. */
9299 got_header_size = 0;
9300 plt_header_size = 0;
9301 }
9302 else
9303 {
9304 splt = htab->root.splt;
9305 sgot = htab->root.sgotplt;
9306 srel = htab->root.srelplt;
9307
9308 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9309 plt_header_size = htab->plt_header_size;
9310 }
9311 BFD_ASSERT (splt != NULL && srel != NULL);
9312
9313 /* Fill in the entry in the procedure linkage table. */
9314 if (htab->symbian_p)
9315 {
9316 BFD_ASSERT (dynindx >= 0);
9317 put_arm_insn (htab, output_bfd,
9318 elf32_arm_symbian_plt_entry[0],
9319 splt->contents + root_plt->offset);
9320 bfd_put_32 (output_bfd,
9321 elf32_arm_symbian_plt_entry[1],
9322 splt->contents + root_plt->offset + 4);
9323
9324 /* Fill in the entry in the .rel.plt section. */
9325 rel.r_offset = (splt->output_section->vma
9326 + splt->output_offset
9327 + root_plt->offset + 4);
9328 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9329
9330 /* Get the index in the procedure linkage table which
9331 corresponds to this symbol. This is the index of this symbol
9332 in all the symbols for which we are making plt entries. The
9333 first entry in the procedure linkage table is reserved. */
9334 plt_index = ((root_plt->offset - plt_header_size)
9335 / htab->plt_entry_size);
9336 }
9337 else
9338 {
9339 bfd_vma got_offset, got_address, plt_address;
9340 bfd_vma got_displacement, initial_got_entry;
9341 bfd_byte * ptr;
9342
9343 BFD_ASSERT (sgot != NULL);
9344
9345 /* Get the offset into the .(i)got.plt table of the entry that
9346 corresponds to this function. */
9347 got_offset = (arm_plt->got_offset & -2);
9348
9349 /* Get the index in the procedure linkage table which
9350 corresponds to this symbol. This is the index of this symbol
9351 in all the symbols for which we are making plt entries.
9352 After the reserved .got.plt entries, all symbols appear in
9353 the same order as in .plt. */
9354 plt_index = (got_offset - got_header_size) / 4;
9355
9356 /* Calculate the address of the GOT entry. */
9357 got_address = (sgot->output_section->vma
9358 + sgot->output_offset
9359 + got_offset);
9360
9361 /* ...and the address of the PLT entry. */
9362 plt_address = (splt->output_section->vma
9363 + splt->output_offset
9364 + root_plt->offset);
9365
9366 ptr = splt->contents + root_plt->offset;
0e1862bb 9367 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9368 {
9369 unsigned int i;
9370 bfd_vma val;
9371
9372 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9373 {
9374 val = elf32_arm_vxworks_shared_plt_entry[i];
9375 if (i == 2)
9376 val |= got_address - sgot->output_section->vma;
9377 if (i == 5)
9378 val |= plt_index * RELOC_SIZE (htab);
9379 if (i == 2 || i == 5)
9380 bfd_put_32 (output_bfd, val, ptr);
9381 else
9382 put_arm_insn (htab, output_bfd, val, ptr);
9383 }
9384 }
9385 else if (htab->vxworks_p)
9386 {
9387 unsigned int i;
9388 bfd_vma val;
9389
9390 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9391 {
9392 val = elf32_arm_vxworks_exec_plt_entry[i];
9393 if (i == 2)
9394 val |= got_address;
9395 if (i == 4)
9396 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9397 if (i == 5)
9398 val |= plt_index * RELOC_SIZE (htab);
9399 if (i == 2 || i == 5)
9400 bfd_put_32 (output_bfd, val, ptr);
9401 else
9402 put_arm_insn (htab, output_bfd, val, ptr);
9403 }
9404
9405 loc = (htab->srelplt2->contents
9406 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9407
9408 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9409 referencing the GOT for this PLT entry. */
9410 rel.r_offset = plt_address + 8;
9411 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9412 rel.r_addend = got_offset;
9413 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9414 loc += RELOC_SIZE (htab);
9415
9416 /* Create the R_ARM_ABS32 relocation referencing the
9417 beginning of the PLT for this GOT entry. */
9418 rel.r_offset = got_address;
9419 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9420 rel.r_addend = 0;
9421 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9422 }
b38cadfb
NC		 9423 else if (htab->nacl_p)
9424 {
9425 /* Calculate the displacement between the PLT slot and the
9426 common tail that's part of the special initial PLT slot. */
6034aab8 9427 int32_t tail_displacement
b38cadfb
NC		 9428 = ((splt->output_section->vma + splt->output_offset
9429 + ARM_NACL_PLT_TAIL_OFFSET)
9430 - (plt_address + htab->plt_entry_size + 4));
9431 BFD_ASSERT ((tail_displacement & 3) == 0);
9432 tail_displacement >>= 2;
9433
9434 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9435 || (-tail_displacement & 0xff000000) == 0);
9436
9437 /* Calculate the displacement between the PLT slot and the entry
9438 in the GOT. The offset accounts for the value produced by
9439 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9440 got_displacement = (got_address
99059e56 9441 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9442
9443 /* NaCl does not support interworking at all. */
9444 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9445
9446 put_arm_insn (htab, output_bfd,
9447 elf32_arm_nacl_plt_entry[0]
9448 | arm_movw_immediate (got_displacement),
9449 ptr + 0);
9450 put_arm_insn (htab, output_bfd,
9451 elf32_arm_nacl_plt_entry[1]
9452 | arm_movt_immediate (got_displacement),
9453 ptr + 4);
9454 put_arm_insn (htab, output_bfd,
9455 elf32_arm_nacl_plt_entry[2],
9456 ptr + 8);
9457 put_arm_insn (htab, output_bfd,
9458 elf32_arm_nacl_plt_entry[3]
9459 | (tail_displacement & 0x00ffffff),
9460 ptr + 12);
9461 }
57460bcf
NC		 9462 else if (using_thumb_only (htab))
9463 {
eed94f8f 9464 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9465 if (!using_thumb2 (htab))
eed94f8f
NC		 9466 {
9467 /* FIXME: We ought to be able to generate thumb-1 PLT
9468 instructions... */
90b6238f 9469 _bfd_error_handler (_("%pB: warning: thumb-1 mode PLT generation not currently supported"),
eed94f8f
NC		 9470 output_bfd);
9471 return FALSE;
9472 }
57460bcf 9473
eed94f8f
NC		 9474 /* Calculate the displacement between the PLT slot and the entry in
9475 the GOT. The 12-byte offset accounts for the value produced by
9476 adding to pc in the 3rd instruction of the PLT stub. */
9477 got_displacement = got_address - (plt_address + 12);
9478
9479 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9480 instead of 'put_thumb_insn'. */
9481 put_arm_insn (htab, output_bfd,
9482 elf32_thumb2_plt_entry[0]
9483 | ((got_displacement & 0x000000ff) << 16)
9484 | ((got_displacement & 0x00000700) << 20)
9485 | ((got_displacement & 0x00000800) >> 1)
9486 | ((got_displacement & 0x0000f000) >> 12),
9487 ptr + 0);
9488 put_arm_insn (htab, output_bfd,
9489 elf32_thumb2_plt_entry[1]
9490 | ((got_displacement & 0x00ff0000) )
9491 | ((got_displacement & 0x07000000) << 4)
9492 | ((got_displacement & 0x08000000) >> 17)
9493 | ((got_displacement & 0xf0000000) >> 28),
9494 ptr + 4);
9495 put_arm_insn (htab, output_bfd,
9496 elf32_thumb2_plt_entry[2],
9497 ptr + 8);
9498 put_arm_insn (htab, output_bfd,
9499 elf32_thumb2_plt_entry[3],
9500 ptr + 12);
57460bcf 9501 }
34e77a92
RS		 9502 else
9503 {
9504 /* Calculate the displacement between the PLT slot and the
9505 entry in the GOT. The eight-byte offset accounts for the
9506 value produced by adding to pc in the first instruction
9507 of the PLT stub. */
9508 got_displacement = got_address - (plt_address + 8);
9509
34e77a92
RS		 9510 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9511 {
9512 put_thumb_insn (htab, output_bfd,
9513 elf32_arm_plt_thumb_stub[0], ptr - 4);
9514 put_thumb_insn (htab, output_bfd,
9515 elf32_arm_plt_thumb_stub[1], ptr - 2);
9516 }
9517
1db37fe6
YG		 9518 if (!elf32_arm_use_long_plt_entry)
9519 {
9520 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9521
9522 put_arm_insn (htab, output_bfd,
9523 elf32_arm_plt_entry_short[0]
9524 | ((got_displacement & 0x0ff00000) >> 20),
9525 ptr + 0);
9526 put_arm_insn (htab, output_bfd,
9527 elf32_arm_plt_entry_short[1]
9528 | ((got_displacement & 0x000ff000) >> 12),
9529 ptr+ 4);
9530 put_arm_insn (htab, output_bfd,
9531 elf32_arm_plt_entry_short[2]
9532 | (got_displacement & 0x00000fff),
9533 ptr + 8);
34e77a92 9534#ifdef FOUR_WORD_PLT
1db37fe6 9535 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9536#endif
1db37fe6
YG		 9537 }
9538 else
9539 {
9540 put_arm_insn (htab, output_bfd,
9541 elf32_arm_plt_entry_long[0]
9542 | ((got_displacement & 0xf0000000) >> 28),
9543 ptr + 0);
9544 put_arm_insn (htab, output_bfd,
9545 elf32_arm_plt_entry_long[1]
9546 | ((got_displacement & 0x0ff00000) >> 20),
9547 ptr + 4);
9548 put_arm_insn (htab, output_bfd,
9549 elf32_arm_plt_entry_long[2]
9550 | ((got_displacement & 0x000ff000) >> 12),
9551 ptr+ 8);
9552 put_arm_insn (htab, output_bfd,
9553 elf32_arm_plt_entry_long[3]
9554 | (got_displacement & 0x00000fff),
9555 ptr + 12);
9556 }
34e77a92
RS		 9557 }
9558
9559 /* Fill in the entry in the .rel(a).(i)plt section. */
9560 rel.r_offset = got_address;
9561 rel.r_addend = 0;
9562 if (dynindx == -1)
9563 {
9564 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9565 The dynamic linker or static executable then calls SYM_VALUE
9566 to determine the correct run-time value of the .igot.plt entry. */
9567 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9568 initial_got_entry = sym_value;
9569 }
9570 else
9571 {
9572 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9573 initial_got_entry = (splt->output_section->vma
9574 + splt->output_offset);
9575 }
9576
9577 /* Fill in the entry in the global offset table. */
9578 bfd_put_32 (output_bfd, initial_got_entry,
9579 sgot->contents + got_offset);
9580 }
9581
aba8c3de
WN		 9582 if (dynindx == -1)
9583 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9584 else
9585 {
9586 loc = srel->contents + plt_index * RELOC_SIZE (htab);
9587 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9588 }
57460bcf
NC		 9589
9590 return TRUE;
34e77a92
RS		 9591}
9592
eb043451
PB		 9593/* Some relocations map to different relocations depending on the
9594 target. Return the real relocation. */
8029a119 9595
eb043451
PB		 9596static int
9597arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
9598 int r_type)
9599{
9600 switch (r_type)
9601 {
9602 case R_ARM_TARGET1:
9603 if (globals->target1_is_rel)
9604 return R_ARM_REL32;
9605 else
9606 return R_ARM_ABS32;
9607
9608 case R_ARM_TARGET2:
9609 return globals->target2_reloc;
9610
9611 default:
9612 return r_type;
9613 }
9614}
eb043451 9615
ba93b8ac
DJ		 9616/* Return the base VMA address which should be subtracted from real addresses
9617 when resolving @dtpoff relocation.
9618 This is PT_TLS segment p_vaddr. */
9619
9620static bfd_vma
9621dtpoff_base (struct bfd_link_info *info)
9622{
9623 /* If tls_sec is NULL, we should have signalled an error already. */
9624 if (elf_hash_table (info)->tls_sec == NULL)
9625 return 0;
9626 return elf_hash_table (info)->tls_sec->vma;
9627}
9628
9629/* Return the relocation value for @tpoff relocation
9630 if STT_TLS virtual address is ADDRESS. */
9631
9632static bfd_vma
9633tpoff (struct bfd_link_info *info, bfd_vma address)
9634{
9635 struct elf_link_hash_table *htab = elf_hash_table (info);
9636 bfd_vma base;
9637
9638 /* If tls_sec is NULL, we should have signalled an error already. */
9639 if (htab->tls_sec == NULL)
9640 return 0;
9641 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
9642 return address - htab->tls_sec->vma + base;
9643}
9644
00a97672
RS		 9645/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
9646 VALUE is the relocation value. */
9647
9648static bfd_reloc_status_type
9649elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
9650{
9651 if (value > 0xfff)
9652 return bfd_reloc_overflow;
9653
9654 value |= bfd_get_32 (abfd, data) & 0xfffff000;
9655 bfd_put_32 (abfd, value, data);
9656 return bfd_reloc_ok;
9657}
9658
0855e32b
NS		 9659/* Handle TLS relaxations. Relaxing is possible for symbols that use
9660 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
9661 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
9662
9663 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
9664 is to then call final_link_relocate. Return other values in the
62672b10
NS		 9665 case of error.
9666
9667 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
9668 the pre-relaxed code. It would be nice if the relocs were updated
9669 to match the optimization. */
0855e32b 9670
b38cadfb 9671static bfd_reloc_status_type
0855e32b 9672elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 9673 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 9674 Elf_Internal_Rela *rel, unsigned long is_local)
9675{
9676 unsigned long insn;
b38cadfb 9677
0855e32b
NS		 9678 switch (ELF32_R_TYPE (rel->r_info))
9679 {
9680 default:
9681 return bfd_reloc_notsupported;
b38cadfb 9682
0855e32b
NS		 9683 case R_ARM_TLS_GOTDESC:
9684 if (is_local)
9685 insn = 0;
9686 else
9687 {
9688 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9689 if (insn & 1)
9690 insn -= 5; /* THUMB */
9691 else
9692 insn -= 8; /* ARM */
9693 }
9694 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9695 return bfd_reloc_continue;
9696
9697 case R_ARM_THM_TLS_DESCSEQ:
9698 /* Thumb insn. */
9699 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
9700 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
9701 {
9702 if (is_local)
9703 /* nop */
9704 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9705 }
9706 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
9707 {
9708 if (is_local)
9709 /* nop */
9710 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9711 else
9712 /* ldr rx,[ry] */
9713 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
9714 }
9715 else if ((insn & 0xff87) == 0x4780) /* blx rx */
9716 {
9717 if (is_local)
9718 /* nop */
9719 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9720 else
9721 /* mov r0, rx */
9722 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
9723 contents + rel->r_offset);
9724 }
9725 else
9726 {
9727 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
9728 /* It's a 32 bit instruction, fetch the rest of it for
9729 error generation. */
9730 insn = (insn << 16)
9731 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 9732 _bfd_error_handler
695344c0 9733 /* xgettext:c-format */
2dcf00ce 9734 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 9735 "unexpected %s instruction '%#lx' in TLS trampoline"),
9736 input_bfd, input_sec, (uint64_t) rel->r_offset,
9737 "Thumb", insn);
0855e32b
NS		 9738 return bfd_reloc_notsupported;
9739 }
9740 break;
b38cadfb 9741
0855e32b
NS		 9742 case R_ARM_TLS_DESCSEQ:
9743 /* arm insn. */
9744 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9745 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
9746 {
9747 if (is_local)
9748 /* mov rx, ry */
9749 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
9750 contents + rel->r_offset);
9751 }
9752 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
9753 {
9754 if (is_local)
9755 /* nop */
9756 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9757 else
9758 /* ldr rx,[ry] */
9759 bfd_put_32 (input_bfd, insn & 0xfffff000,
9760 contents + rel->r_offset);
9761 }
9762 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
9763 {
9764 if (is_local)
9765 /* nop */
9766 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9767 else
9768 /* mov r0, rx */
9769 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
9770 contents + rel->r_offset);
9771 }
9772 else
9773 {
4eca0228 9774 _bfd_error_handler
695344c0 9775 /* xgettext:c-format */
2dcf00ce 9776 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 9777 "unexpected %s instruction '%#lx' in TLS trampoline"),
9778 input_bfd, input_sec, (uint64_t) rel->r_offset,
9779 "ARM", insn);
0855e32b
NS		 9780 return bfd_reloc_notsupported;
9781 }
9782 break;
9783
9784 case R_ARM_TLS_CALL:
9785 /* GD->IE relaxation, turn the instruction into 'nop' or
9786 'ldr r0, [pc,r0]' */
9787 insn = is_local ? 0xe1a00000 : 0xe79f0000;
9788 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9789 break;
b38cadfb 9790
0855e32b 9791 case R_ARM_THM_TLS_CALL:
6a631e86 9792 /* GD->IE relaxation. */
0855e32b
NS		 9793 if (!is_local)
9794 /* add r0,pc; ldr r0, [r0] */
9795 insn = 0x44786800;
60a019a0 9796 else if (using_thumb2 (globals))
0855e32b
NS		 9797 /* nop.w */
9798 insn = 0xf3af8000;
9799 else
9800 /* nop; nop */
9801 insn = 0xbf00bf00;
b38cadfb 9802
0855e32b
NS		 9803 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
9804 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
9805 break;
9806 }
9807 return bfd_reloc_ok;
9808}
9809
4962c51a
MS		 9810/* For a given value of n, calculate the value of G_n as required to
9811 deal with group relocations. We return it in the form of an
9812 encoded constant-and-rotation, together with the final residual. If n is
9813 specified as less than zero, then final_residual is filled with the
9814 input value and no further action is performed. */
9815
9816static bfd_vma
9817calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
9818{
9819 int current_n;
9820 bfd_vma g_n;
9821 bfd_vma encoded_g_n = 0;
9822 bfd_vma residual = value; /* Also known as Y_n. */
9823
9824 for (current_n = 0; current_n <= n; current_n++)
9825 {
9826 int shift;
9827
9828 /* Calculate which part of the value to mask. */
9829 if (residual == 0)
99059e56 9830 shift = 0;
4962c51a 9831 else
99059e56
RM		 9832 {
9833 int msb;
9834
9835 /* Determine the most significant bit in the residual and
9836 align the resulting value to a 2-bit boundary. */
9837 for (msb = 30; msb >= 0; msb -= 2)
9838 if (residual & (3 << msb))
9839 break;
9840
9841 /* The desired shift is now (msb - 6), or zero, whichever
9842 is the greater. */
9843 shift = msb - 6;
9844 if (shift < 0)
9845 shift = 0;
9846 }
4962c51a
MS		 9847
9848 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
9849 g_n = residual & (0xff << shift);
9850 encoded_g_n = (g_n >> shift)
99059e56 9851 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 9852
9853 /* Calculate the residual for the next time around. */
9854 residual &= ~g_n;
9855 }
9856
9857 *final_residual = residual;
9858
9859 return encoded_g_n;
9860}
9861
9862/* Given an ARM instruction, determine whether it is an ADD or a SUB.
9863 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 9864
4962c51a 9865static int
906e58ca 9866identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 9867{
9868 int opcode = insn & 0x1e00000;
9869
9870 if (opcode == 1 << 23) /* ADD */
9871 return 1;
9872
9873 if (opcode == 1 << 22) /* SUB */
9874 return -1;
9875
9876 return 0;
9877}
9878
252b5132 9879/* Perform a relocation as part of a final link. */
9b485d32 9880
252b5132 9881static bfd_reloc_status_type
07d6d2b8
AM		 9882elf32_arm_final_link_relocate (reloc_howto_type * howto,
9883 bfd * input_bfd,
9884 bfd * output_bfd,
9885 asection * input_section,
9886 bfd_byte * contents,
9887 Elf_Internal_Rela * rel,
9888 bfd_vma value,
9889 struct bfd_link_info * info,
9890 asection * sym_sec,
9891 const char * sym_name,
9892 unsigned char st_type,
9893 enum arm_st_branch_type branch_type,
0945cdfd 9894 struct elf_link_hash_entry * h,
07d6d2b8
AM		 9895 bfd_boolean * unresolved_reloc_p,
9896 char ** error_message)
9897{
9898 unsigned long r_type = howto->type;
9899 unsigned long r_symndx;
9900 bfd_byte * hit_data = contents + rel->r_offset;
9901 bfd_vma * local_got_offsets;
9902 bfd_vma * local_tlsdesc_gotents;
9903 asection * sgot;
9904 asection * splt;
9905 asection * sreloc = NULL;
9906 asection * srelgot;
9907 bfd_vma addend;
9908 bfd_signed_vma signed_addend;
9909 unsigned char dynreloc_st_type;
9910 bfd_vma dynreloc_value;
ba96a88f 9911 struct elf32_arm_link_hash_table * globals;
34e77a92 9912 struct elf32_arm_link_hash_entry *eh;
07d6d2b8
AM		 9913 union gotplt_union *root_plt;
9914 struct arm_plt_info *arm_plt;
9915 bfd_vma plt_offset;
9916 bfd_vma gotplt_offset;
9917 bfd_boolean has_iplt_entry;
9918 bfd_boolean resolved_to_zero;
f21f3fe0 9919
9c504268 9920 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 9921 if (globals == NULL)
9922 return bfd_reloc_notsupported;
9c504268 9923
0ffa91dd 9924 BFD_ASSERT (is_arm_elf (input_bfd));
47aeb64c 9925 BFD_ASSERT (howto != NULL);
0ffa91dd
NC		 9926
9927 /* Some relocation types map to different relocations depending on the
9c504268 9928 target. We pick the right one here. */
eb043451 9929 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 9930
9931 /* It is possible to have linker relaxations on some TLS access
9932 models. Update our information here. */
9933 r_type = elf32_arm_tls_transition (info, r_type, h);
9934
eb043451
PB		 9935 if (r_type != howto->type)
9936 howto = elf32_arm_howto_from_type (r_type);
9c504268 9937
34e77a92 9938 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 9939 sgot = globals->root.sgot;
252b5132 9940 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 9941 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
9942
34e77a92
RS		 9943 if (globals->root.dynamic_sections_created)
9944 srelgot = globals->root.srelgot;
9945 else
9946 srelgot = NULL;
9947
252b5132
RH		 9948 r_symndx = ELF32_R_SYM (rel->r_info);
9949
4e7fd91e 9950 if (globals->use_rel)
ba96a88f 9951 {
4e7fd91e
PB		 9952 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
9953
9954 if (addend & ((howto->src_mask + 1) >> 1))
9955 {
9956 signed_addend = -1;
9957 signed_addend &= ~ howto->src_mask;
9958 signed_addend |= addend;
9959 }
9960 else
9961 signed_addend = addend;
ba96a88f
NC		 9962 }
9963 else
4e7fd91e 9964 addend = signed_addend = rel->r_addend;
f21f3fe0 9965
39f21624
NC		 9966 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
9967 are resolving a function call relocation. */
9968 if (using_thumb_only (globals)
9969 && (r_type == R_ARM_THM_CALL
9970 || r_type == R_ARM_THM_JUMP24)
9971 && branch_type == ST_BRANCH_TO_ARM)
9972 branch_type = ST_BRANCH_TO_THUMB;
9973
34e77a92
RS		 9974 /* Record the symbol information that should be used in dynamic
9975 relocations. */
9976 dynreloc_st_type = st_type;
9977 dynreloc_value = value;
9978 if (branch_type == ST_BRANCH_TO_THUMB)
9979 dynreloc_value |= 1;
9980
9981 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
9982 VALUE appropriately for relocations that we resolve at link time. */
9983 has_iplt_entry = FALSE;
4ba2ef8f
TP		 9984 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
9985 &arm_plt)
34e77a92
RS		 9986 && root_plt->offset != (bfd_vma) -1)
9987 {
9988 plt_offset = root_plt->offset;
9989 gotplt_offset = arm_plt->got_offset;
9990
9991 if (h == NULL || eh->is_iplt)
9992 {
9993 has_iplt_entry = TRUE;
9994 splt = globals->root.iplt;
9995
9996 /* Populate .iplt entries here, because not all of them will
9997 be seen by finish_dynamic_symbol. The lower bit is set if
9998 we have already populated the entry. */
9999 if (plt_offset & 1)
10000 plt_offset--;
10001 else
10002 {
57460bcf
NC		 10003 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
10004 -1, dynreloc_value))
10005 root_plt->offset |= 1;
10006 else
10007 return bfd_reloc_notsupported;
34e77a92
RS		 10008 }
10009
10010 /* Static relocations always resolve to the .iplt entry. */
10011 st_type = STT_FUNC;
10012 value = (splt->output_section->vma
10013 + splt->output_offset
10014 + plt_offset);
10015 branch_type = ST_BRANCH_TO_ARM;
10016
10017 /* If there are non-call relocations that resolve to the .iplt
10018 entry, then all dynamic ones must too. */
10019 if (arm_plt->noncall_refcount != 0)
10020 {
10021 dynreloc_st_type = st_type;
10022 dynreloc_value = value;
10023 }
10024 }
10025 else
10026 /* We populate the .plt entry in finish_dynamic_symbol. */
10027 splt = globals->root.splt;
10028 }
10029 else
10030 {
10031 splt = NULL;
10032 plt_offset = (bfd_vma) -1;
10033 gotplt_offset = (bfd_vma) -1;
10034 }
10035
95b03e4a
L		 10036 resolved_to_zero = (h != NULL
10037 && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
10038
252b5132
RH		 10039 switch (r_type)
10040 {
10041 case R_ARM_NONE:
28a094c2
DJ		 10042 /* We don't need to find a value for this symbol. It's just a
10043 marker. */
10044 *unresolved_reloc_p = FALSE;
252b5132
RH		 10045 return bfd_reloc_ok;
10046
00a97672
RS		 10047 case R_ARM_ABS12:
10048 if (!globals->vxworks_p)
10049 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10050 /* Fall through. */
00a97672 10051
252b5132
RH		 10052 case R_ARM_PC24:
10053 case R_ARM_ABS32:
bb224fc3 10054 case R_ARM_ABS32_NOI:
252b5132 10055 case R_ARM_REL32:
bb224fc3 10056 case R_ARM_REL32_NOI:
5b5bb741
PB		 10057 case R_ARM_CALL:
10058 case R_ARM_JUMP24:
dfc5f959 10059 case R_ARM_XPC25:
eb043451 10060 case R_ARM_PREL31:
7359ea65 10061 case R_ARM_PLT32:
7359ea65
DJ		 10062 /* Handle relocations which should use the PLT entry. ABS32/REL32
10063 will use the symbol's value, which may point to a PLT entry, but we
10064 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10065 branches in this object should go to it, except if the PLT is too
10066 far away, in which case a long branch stub should be inserted. */
bb224fc3 10067 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10068 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10069 && r_type != R_ARM_CALL
10070 && r_type != R_ARM_JUMP24
10071 && r_type != R_ARM_PLT32)
34e77a92 10072 && plt_offset != (bfd_vma) -1)
7359ea65 10073 {
34e77a92
RS		 10074 /* If we've created a .plt section, and assigned a PLT entry
10075 to this function, it must either be a STT_GNU_IFUNC reference
10076 or not be known to bind locally. In other cases, we should
10077 have cleared the PLT entry by now. */
10078 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10079
10080 value = (splt->output_section->vma
10081 + splt->output_offset
34e77a92 10082 + plt_offset);
0945cdfd 10083 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10084 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10085 contents, rel->r_offset, value,
00a97672 10086 rel->r_addend);
7359ea65
DJ		 10087 }
10088
67687978
PB		 10089 /* When generating a shared object or relocatable executable, these
10090 relocations are copied into the output file to be resolved at
10091 run time. */
0e1862bb
L		 10092 if ((bfd_link_pic (info)
10093 || globals->root.is_relocatable_executable)
7359ea65 10094 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10095 && !(globals->vxworks_p
3348747a
NS		 10096 && strcmp (input_section->output_section->name,
10097 ".tls_vars") == 0)
bb224fc3 10098 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10099 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10100 && !(input_bfd == globals->stub_bfd
10101 && strstr (input_section->name, STUB_SUFFIX))
7359ea65 10102 && (h == NULL
95b03e4a
L		 10103 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10104 && !resolved_to_zero)
7359ea65
DJ		 10105 || h->root.type != bfd_link_hash_undefweak)
10106 && r_type != R_ARM_PC24
5b5bb741
PB		 10107 && r_type != R_ARM_CALL
10108 && r_type != R_ARM_JUMP24
ee06dc07 10109 && r_type != R_ARM_PREL31
7359ea65 10110 && r_type != R_ARM_PLT32)
252b5132 10111 {
947216bf 10112 Elf_Internal_Rela outrel;
b34976b6 10113 bfd_boolean skip, relocate;
f21f3fe0 10114
52db4ec2
JW		 10115 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10116 && !h->def_regular)
10117 {
10118 char *v = _("shared object");
10119
0e1862bb 10120 if (bfd_link_executable (info))
52db4ec2
JW		 10121 v = _("PIE executable");
10122
4eca0228 10123 _bfd_error_handler
871b3ab2 10124 (_("%pB: relocation %s against external or undefined symbol `%s'"
52db4ec2
JW		 10125 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10126 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10127 return bfd_reloc_notsupported;
10128 }
10129
0945cdfd
DJ		 10130 *unresolved_reloc_p = FALSE;
10131
34e77a92 10132 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10133 {
83bac4b0
NC		 10134 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10135 ! globals->use_rel);
f21f3fe0 10136
83bac4b0 10137 if (sreloc == NULL)
252b5132 10138 return bfd_reloc_notsupported;
252b5132 10139 }
f21f3fe0 10140
b34976b6
AM		 10141 skip = FALSE;
10142 relocate = FALSE;
f21f3fe0 10143
00a97672 10144 outrel.r_addend = addend;
c629eae0
JJ		 10145 outrel.r_offset =
10146 _bfd_elf_section_offset (output_bfd, info, input_section,
10147 rel->r_offset);
10148 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10149 skip = TRUE;
0bb2d96a 10150 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10151 skip = TRUE, relocate = TRUE;
252b5132
RH		 10152 outrel.r_offset += (input_section->output_section->vma
10153 + input_section->output_offset);
f21f3fe0 10154
252b5132 10155 if (skip)
0bb2d96a 10156 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10157 else if (h != NULL
10158 && h->dynindx != -1
0e1862bb 10159 && (!bfd_link_pic (info)
1dcb9720
JW		 10160 || !(bfd_link_pie (info)
10161 || SYMBOLIC_BIND (info, h))
f5385ebf 10162 || !h->def_regular))
5e681ec4 10163 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10164 else
10165 {
a16385dc
MM		 10166 int symbol;
10167
5e681ec4 10168 /* This symbol is local, or marked to become local. */
34e77a92 10169 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 10170 if (globals->symbian_p)
6366ff1e 10171 {
74541ad4
AM		 10172 asection *osec;
10173
6366ff1e
MM		 10174 /* On Symbian OS, the data segment and text segement
10175 can be relocated independently. Therefore, we
10176 must indicate the segment to which this
10177 relocation is relative. The BPABI allows us to
10178 use any symbol in the right segment; we just use
10179 the section symbol as it is convenient. (We
10180 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10181 will not appear in the dynamic symbol table.)
10182
10183 Note that the dynamic linker ignores the section
10184 symbol value, so we don't subtract osec->vma
10185 from the emitted reloc addend. */
10dbd1f3 10186 if (sym_sec)
74541ad4 10187 osec = sym_sec->output_section;
10dbd1f3 10188 else
74541ad4
AM		 10189 osec = input_section->output_section;
10190 symbol = elf_section_data (osec)->dynindx;
10191 if (symbol == 0)
10192 {
10193 struct elf_link_hash_table *htab = elf_hash_table (info);
10194
10195 if ((osec->flags & SEC_READONLY) == 0
10196 && htab->data_index_section != NULL)
10197 osec = htab->data_index_section;
10198 else
10199 osec = htab->text_index_section;
10200 symbol = elf_section_data (osec)->dynindx;
10201 }
6366ff1e
MM		 10202 BFD_ASSERT (symbol != 0);
10203 }
a16385dc
MM		 10204 else
10205 /* On SVR4-ish systems, the dynamic loader cannot
10206 relocate the text and data segments independently,
10207 so the symbol does not matter. */
10208 symbol = 0;
34e77a92
RS		 10209 if (dynreloc_st_type == STT_GNU_IFUNC)
10210 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10211 to the .iplt entry. Instead, every non-call reference
10212 must use an R_ARM_IRELATIVE relocation to obtain the
10213 correct run-time address. */
10214 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
10215 else
10216 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10217 if (globals->use_rel)
10218 relocate = TRUE;
10219 else
34e77a92 10220 outrel.r_addend += dynreloc_value;
252b5132 10221 }
f21f3fe0 10222
47beaa6a 10223 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10224
f21f3fe0 10225 /* If this reloc is against an external symbol, we do not want to
252b5132 10226 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10227 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10228 if (! relocate)
10229 return bfd_reloc_ok;
9a5aca8c 10230
f21f3fe0 10231 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10232 contents, rel->r_offset,
10233 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10234 }
10235 else switch (r_type)
10236 {
00a97672
RS		 10237 case R_ARM_ABS12:
10238 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10239
dfc5f959 10240 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10241 case R_ARM_CALL:
10242 case R_ARM_JUMP24:
8029a119 10243 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10244 case R_ARM_PLT32:
906e58ca 10245 {
906e58ca
NC		 10246 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10247
dfc5f959 10248 if (r_type == R_ARM_XPC25)
252b5132 10249 {
dfc5f959
NC		 10250 /* Check for Arm calling Arm function. */
10251 /* FIXME: Should we translate the instruction into a BL
10252 instruction instead ? */
35fc36a8 10253 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10254 _bfd_error_handler
90b6238f
AM		 10255 (_("\%pB: warning: %s BLX instruction targets"
10256 " %s function '%s'"),
10257 input_bfd, "ARM",
10258 "ARM", h ? h->root.root.string : "(local)");
dfc5f959 10259 }
155d87d7 10260 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10261 {
10262 /* Check for Arm calling Thumb function. */
35fc36a8 10263 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10264 {
f2a9dd69
DJ		 10265 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10266 output_bfd, input_section,
10267 hit_data, sym_sec, rel->r_offset,
10268 signed_addend, value,
10269 error_message))
10270 return bfd_reloc_ok;
10271 else
10272 return bfd_reloc_dangerous;
dfc5f959 10273 }
252b5132 10274 }
ba96a88f 10275
906e58ca 10276 /* Check if a stub has to be inserted because the
8029a119 10277 destination is too far or we are changing mode. */
155d87d7
CL		 10278 if ( r_type == R_ARM_CALL
10279 || r_type == R_ARM_JUMP24
10280 || r_type == R_ARM_PLT32)
906e58ca 10281 {
fe33d2fa
CL		 10282 enum elf32_arm_stub_type stub_type = arm_stub_none;
10283 struct elf32_arm_link_hash_entry *hash;
10284
10285 hash = (struct elf32_arm_link_hash_entry *) h;
10286 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10287 st_type, &branch_type,
10288 hash, value, sym_sec,
fe33d2fa 10289 input_bfd, sym_name);
5fa9e92f 10290
fe33d2fa 10291 if (stub_type != arm_stub_none)
906e58ca
NC		 10292 {
10293 /* The target is out of reach, so redirect the
10294 branch to the local stub for this function. */
906e58ca
NC		 10295 stub_entry = elf32_arm_get_stub_entry (input_section,
10296 sym_sec, h,
fe33d2fa
CL		 10297 rel, globals,
10298 stub_type);
9cd3e4e5
NC		 10299 {
10300 if (stub_entry != NULL)
10301 value = (stub_entry->stub_offset
10302 + stub_entry->stub_sec->output_offset
10303 + stub_entry->stub_sec->output_section->vma);
10304
10305 if (plt_offset != (bfd_vma) -1)
10306 *unresolved_reloc_p = FALSE;
10307 }
906e58ca 10308 }
fe33d2fa
CL		 10309 else
10310 {
10311 /* If the call goes through a PLT entry, make sure to
10312 check distance to the right destination address. */
34e77a92 10313 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10314 {
10315 value = (splt->output_section->vma
10316 + splt->output_offset
34e77a92 10317 + plt_offset);
fe33d2fa
CL		 10318 *unresolved_reloc_p = FALSE;
10319 /* The PLT entry is in ARM mode, regardless of the
10320 target function. */
35fc36a8 10321 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10322 }
10323 }
906e58ca
NC		 10324 }
10325
dea514f5
PB		 10326 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10327 where:
10328 S is the address of the symbol in the relocation.
10329 P is address of the instruction being relocated.
10330 A is the addend (extracted from the instruction) in bytes.
10331
10332 S is held in 'value'.
10333 P is the base address of the section containing the
10334 instruction plus the offset of the reloc into that
10335 section, ie:
10336 (input_section->output_section->vma +
10337 input_section->output_offset +
10338 rel->r_offset).
10339 A is the addend, converted into bytes, ie:
10340 (signed_addend * 4)
10341
10342 Note: None of these operations have knowledge of the pipeline
10343 size of the processor, thus it is up to the assembler to
10344 encode this information into the addend. */
10345 value -= (input_section->output_section->vma
10346 + input_section->output_offset);
10347 value -= rel->r_offset;
4e7fd91e
PB		 10348 if (globals->use_rel)
10349 value += (signed_addend << howto->size);
10350 else
10351 /* RELA addends do not have to be adjusted by howto->size. */
10352 value += signed_addend;
23080146 10353
dcb5e6e6
NC		 10354 signed_addend = value;
10355 signed_addend >>= howto->rightshift;
9a5aca8c 10356
5ab79981 10357 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10358 the next instruction unless a PLT entry will be created.
77b4f08f 10359 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10360 The jump to the next instruction is optimized as a NOP depending
10361 on the architecture. */
ffcb4889 10362 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10363 && plt_offset == (bfd_vma) -1)
77b4f08f 10364 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10365 {
cd1dac3d
DG		 10366 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10367
10368 if (arch_has_arm_nop (globals))
10369 value |= 0x0320f000;
10370 else
10371 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10372 }
10373 else
59f2c4e7 10374 {
9b485d32 10375 /* Perform a signed range check. */
dcb5e6e6 10376 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10377 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10378 return bfd_reloc_overflow;
9a5aca8c 10379
5ab79981 10380 addend = (value & 2);
39b41c9c 10381
5ab79981
PB		 10382 value = (signed_addend & howto->dst_mask)
10383 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10384
5ab79981
PB		 10385 if (r_type == R_ARM_CALL)
10386 {
155d87d7 10387 /* Set the H bit in the BLX instruction. */
35fc36a8 10388 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10389 {
10390 if (addend)
10391 value |= (1 << 24);
10392 else
10393 value &= ~(bfd_vma)(1 << 24);
10394 }
10395
5ab79981 10396 /* Select the correct instruction (BL or BLX). */
906e58ca 10397 /* Only if we are not handling a BL to a stub. In this
8029a119 10398 case, mode switching is performed by the stub. */
35fc36a8 10399 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10400 value |= (1 << 28);
63e1a0fc 10401 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10402 {
10403 value &= ~(bfd_vma)(1 << 28);
10404 value |= (1 << 24);
10405 }
39b41c9c
PB		 10406 }
10407 }
906e58ca 10408 }
252b5132 10409 break;
f21f3fe0 10410
252b5132
RH		 10411 case R_ARM_ABS32:
10412 value += addend;
35fc36a8 10413 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10414 value |= 1;
10415 break;
f21f3fe0 10416
bb224fc3
MS		 10417 case R_ARM_ABS32_NOI:
10418 value += addend;
10419 break;
10420
252b5132 10421 case R_ARM_REL32:
a8bc6c78 10422 value += addend;
35fc36a8 10423 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10424 value |= 1;
252b5132 10425 value -= (input_section->output_section->vma
62efb346 10426 + input_section->output_offset + rel->r_offset);
252b5132 10427 break;
eb043451 10428
bb224fc3
MS		 10429 case R_ARM_REL32_NOI:
10430 value += addend;
10431 value -= (input_section->output_section->vma
10432 + input_section->output_offset + rel->r_offset);
10433 break;
10434
eb043451
PB		 10435 case R_ARM_PREL31:
10436 value -= (input_section->output_section->vma
10437 + input_section->output_offset + rel->r_offset);
10438 value += signed_addend;
10439 if (! h || h->root.type != bfd_link_hash_undefweak)
10440 {
8029a119 10441 /* Check for overflow. */
eb043451
PB		 10442 if ((value ^ (value >> 1)) & (1 << 30))
10443 return bfd_reloc_overflow;
10444 }
10445 value &= 0x7fffffff;
10446 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10447 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10448 value |= 1;
10449 break;
252b5132 10450 }
f21f3fe0 10451
252b5132
RH		 10452 bfd_put_32 (input_bfd, value, hit_data);
10453 return bfd_reloc_ok;
10454
10455 case R_ARM_ABS8:
fd0fd00c
MJ		 10456 /* PR 16202: Refectch the addend using the correct size. */
10457 if (globals->use_rel)
10458 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10459 value += addend;
4e67d4ca
DG		 10460
10461 /* There is no way to tell whether the user intended to use a signed or
10462 unsigned addend. When checking for overflow we accept either,
10463 as specified by the AAELF. */
10464 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10465 return bfd_reloc_overflow;
10466
10467 bfd_put_8 (input_bfd, value, hit_data);
10468 return bfd_reloc_ok;
10469
10470 case R_ARM_ABS16:
fd0fd00c
MJ		 10471 /* PR 16202: Refectch the addend using the correct size. */
10472 if (globals->use_rel)
10473 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10474 value += addend;
10475
4e67d4ca
DG		 10476 /* See comment for R_ARM_ABS8. */
10477 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10478 return bfd_reloc_overflow;
10479
10480 bfd_put_16 (input_bfd, value, hit_data);
10481 return bfd_reloc_ok;
10482
252b5132 10483 case R_ARM_THM_ABS5:
9b485d32 10484 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10485 if (globals->use_rel)
10486 {
10487 /* Need to refetch addend. */
10488 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10489 /* ??? Need to determine shift amount from operand size. */
10490 addend >>= howto->rightshift;
10491 }
252b5132
RH		 10492 value += addend;
10493
10494 /* ??? Isn't value unsigned? */
10495 if ((long) value > 0x1f || (long) value < -0x10)
10496 return bfd_reloc_overflow;
10497
10498 /* ??? Value needs to be properly shifted into place first. */
10499 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10500 bfd_put_16 (input_bfd, value, hit_data);
10501 return bfd_reloc_ok;
10502
2cab6cc3
MS		 10503 case R_ARM_THM_ALU_PREL_11_0:
10504 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10505 {
10506 bfd_vma insn;
10507 bfd_signed_vma relocation;
10508
10509 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10510 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10511
99059e56
RM		 10512 if (globals->use_rel)
10513 {
10514 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10515 | ((insn & (1 << 26)) >> 15);
10516 if (insn & 0xf00000)
10517 signed_addend = -signed_addend;
10518 }
2cab6cc3
MS		 10519
10520 relocation = value + signed_addend;
79f08007 10521 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10522 + input_section->output_offset
10523 + rel->r_offset);
2cab6cc3 10524
8c65b54f
CS		 10525 /* PR 21523: Use an absolute value. The user of this reloc will
10526 have already selected an ADD or SUB insn appropriately. */
e652757b 10527 value = labs (relocation);
2cab6cc3 10528
99059e56
RM		 10529 if (value >= 0x1000)
10530 return bfd_reloc_overflow;
2cab6cc3 10531
e645cf40
AG		 10532 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10533 if (branch_type == ST_BRANCH_TO_THUMB)
10534 value |= 1;
10535
2cab6cc3 10536 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10537 | ((value & 0x700) << 4)
10538 | ((value & 0x800) << 15);
10539 if (relocation < 0)
10540 insn |= 0xa00000;
2cab6cc3
MS		 10541
10542 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10543 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10544
99059e56 10545 return bfd_reloc_ok;
2cab6cc3
MS		 10546 }
10547
e1ec24c6
NC		 10548 case R_ARM_THM_PC8:
10549 /* PR 10073: This reloc is not generated by the GNU toolchain,
10550 but it is supported for compatibility with third party libraries
10551 generated by other compilers, specifically the ARM/IAR. */
10552 {
10553 bfd_vma insn;
10554 bfd_signed_vma relocation;
10555
10556 insn = bfd_get_16 (input_bfd, hit_data);
10557
99059e56 10558 if (globals->use_rel)
79f08007 10559 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 10560
10561 relocation = value + addend;
79f08007 10562 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10563 + input_section->output_offset
10564 + rel->r_offset);
e1ec24c6 10565
b6518b38 10566 value = relocation;
e1ec24c6
NC		 10567
10568 /* We do not check for overflow of this reloc. Although strictly
10569 speaking this is incorrect, it appears to be necessary in order
10570 to work with IAR generated relocs. Since GCC and GAS do not
10571 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10572 a problem for them. */
10573 value &= 0x3fc;
10574
10575 insn = (insn & 0xff00) | (value >> 2);
10576
10577 bfd_put_16 (input_bfd, insn, hit_data);
10578
99059e56 10579 return bfd_reloc_ok;
e1ec24c6
NC		 10580 }
10581
2cab6cc3
MS		 10582 case R_ARM_THM_PC12:
10583 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10584 {
10585 bfd_vma insn;
10586 bfd_signed_vma relocation;
10587
10588 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10589 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10590
99059e56
RM		 10591 if (globals->use_rel)
10592 {
10593 signed_addend = insn & 0xfff;
10594 if (!(insn & (1 << 23)))
10595 signed_addend = -signed_addend;
10596 }
2cab6cc3
MS		 10597
10598 relocation = value + signed_addend;
79f08007 10599 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10600 + input_section->output_offset
10601 + rel->r_offset);
2cab6cc3 10602
b6518b38 10603 value = relocation;
2cab6cc3 10604
99059e56
RM		 10605 if (value >= 0x1000)
10606 return bfd_reloc_overflow;
2cab6cc3
MS		 10607
10608 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 10609 if (relocation >= 0)
10610 insn |= (1 << 23);
2cab6cc3
MS		 10611
10612 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10613 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10614
99059e56 10615 return bfd_reloc_ok;
2cab6cc3
MS		 10616 }
10617
dfc5f959 10618 case R_ARM_THM_XPC22:
c19d1205 10619 case R_ARM_THM_CALL:
bd97cb95 10620 case R_ARM_THM_JUMP24:
dfc5f959 10621 /* Thumb BL (branch long instruction). */
252b5132 10622 {
b34976b6 10623 bfd_vma relocation;
99059e56 10624 bfd_vma reloc_sign;
b34976b6
AM		 10625 bfd_boolean overflow = FALSE;
10626 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10627 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 10628 bfd_signed_vma reloc_signed_max;
10629 bfd_signed_vma reloc_signed_min;
b34976b6 10630 bfd_vma check;
252b5132 10631 bfd_signed_vma signed_check;
e95de063 10632 int bitsize;
cd1dac3d 10633 const int thumb2 = using_thumb2 (globals);
5e866f5a 10634 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 10635
5ab79981 10636 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 10637 the next instruction unless a PLT entry will be created.
10638 The jump to the next instruction is optimized as a NOP.W for
10639 Thumb-2 enabled architectures. */
19540007 10640 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 10641 && plt_offset == (bfd_vma) -1)
5ab79981 10642 {
60a019a0 10643 if (thumb2)
cd1dac3d
DG		 10644 {
10645 bfd_put_16 (input_bfd, 0xf3af, hit_data);
10646 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
10647 }
10648 else
10649 {
10650 bfd_put_16 (input_bfd, 0xe000, hit_data);
10651 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
10652 }
5ab79981
PB		 10653 return bfd_reloc_ok;
10654 }
10655
e95de063 10656 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 10657 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 10658 if (globals->use_rel)
10659 {
99059e56
RM		 10660 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
10661 bfd_vma upper = upper_insn & 0x3ff;
10662 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 10663 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
10664 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 10665 bfd_vma i1 = j1 ^ s ? 0 : 1;
10666 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 10667
99059e56
RM		 10668 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
10669 /* Sign extend. */
10670 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 10671
4e7fd91e
PB		 10672 signed_addend = addend;
10673 }
cb1afa5c 10674
dfc5f959
NC		 10675 if (r_type == R_ARM_THM_XPC22)
10676 {
10677 /* Check for Thumb to Thumb call. */
10678 /* FIXME: Should we translate the instruction into a BL
10679 instruction instead ? */
35fc36a8 10680 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 10681 _bfd_error_handler
90b6238f
AM		 10682 (_("%pB: warning: %s BLX instruction targets"
10683 " %s function '%s'"),
10684 input_bfd, "Thumb",
10685 "Thumb", h ? h->root.root.string : "(local)");
dfc5f959
NC		 10686 }
10687 else
252b5132 10688 {
dfc5f959
NC		 10689 /* If it is not a call to Thumb, assume call to Arm.
10690 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 10691 function call at all, but rather a long jump. Calls through
10692 the PLT do not require stubs. */
34e77a92 10693 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 10694 {
bd97cb95 10695 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10696 {
10697 /* Convert BL to BLX. */
10698 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10699 }
155d87d7
CL		 10700 else if (( r_type != R_ARM_THM_CALL)
10701 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 10702 {
10703 if (elf32_thumb_to_arm_stub
10704 (info, sym_name, input_bfd, output_bfd, input_section,
10705 hit_data, sym_sec, rel->r_offset, signed_addend, value,
10706 error_message))
10707 return bfd_reloc_ok;
10708 else
10709 return bfd_reloc_dangerous;
10710 }
da5938a2 10711 }
35fc36a8
RS		 10712 else if (branch_type == ST_BRANCH_TO_THUMB
10713 && globals->use_blx
bd97cb95 10714 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10715 {
10716 /* Make sure this is a BL. */
10717 lower_insn |= 0x1800;
10718 }
252b5132 10719 }
f21f3fe0 10720
fe33d2fa 10721 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 10722 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 10723 {
10724 /* Check if a stub has to be inserted because the destination
8029a119 10725 is too far. */
fe33d2fa
CL		 10726 struct elf32_arm_stub_hash_entry *stub_entry;
10727 struct elf32_arm_link_hash_entry *hash;
10728
10729 hash = (struct elf32_arm_link_hash_entry *) h;
10730
10731 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10732 st_type, &branch_type,
10733 hash, value, sym_sec,
fe33d2fa
CL		 10734 input_bfd, sym_name);
10735
10736 if (stub_type != arm_stub_none)
906e58ca
NC		 10737 {
10738 /* The target is out of reach or we are changing modes, so
10739 redirect the branch to the local stub for this
10740 function. */
10741 stub_entry = elf32_arm_get_stub_entry (input_section,
10742 sym_sec, h,
fe33d2fa
CL		 10743 rel, globals,
10744 stub_type);
906e58ca 10745 if (stub_entry != NULL)
9cd3e4e5
NC		 10746 {
10747 value = (stub_entry->stub_offset
10748 + stub_entry->stub_sec->output_offset
10749 + stub_entry->stub_sec->output_section->vma);
10750
10751 if (plt_offset != (bfd_vma) -1)
10752 *unresolved_reloc_p = FALSE;
10753 }
906e58ca 10754
f4ac8484 10755 /* If this call becomes a call to Arm, force BLX. */
155d87d7 10756 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 10757 {
10758 if ((stub_entry
10759 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 10760 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 10761 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10762 }
906e58ca
NC		 10763 }
10764 }
10765
fe33d2fa 10766 /* Handle calls via the PLT. */
34e77a92 10767 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10768 {
10769 value = (splt->output_section->vma
10770 + splt->output_offset
34e77a92 10771 + plt_offset);
fe33d2fa 10772
eed94f8f
NC		 10773 if (globals->use_blx
10774 && r_type == R_ARM_THM_CALL
10775 && ! using_thumb_only (globals))
fe33d2fa
CL		 10776 {
10777 /* If the Thumb BLX instruction is available, convert
10778 the BL to a BLX instruction to call the ARM-mode
10779 PLT entry. */
10780 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 10781 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10782 }
10783 else
10784 {
eed94f8f
NC		 10785 if (! using_thumb_only (globals))
10786 /* Target the Thumb stub before the ARM PLT entry. */
10787 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 10788 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 10789 }
10790 *unresolved_reloc_p = FALSE;
10791 }
10792
ba96a88f 10793 relocation = value + signed_addend;
f21f3fe0 10794
252b5132 10795 relocation -= (input_section->output_section->vma
ba96a88f
NC		 10796 + input_section->output_offset
10797 + rel->r_offset);
9a5aca8c 10798
252b5132
RH		 10799 check = relocation >> howto->rightshift;
10800
10801 /* If this is a signed value, the rightshift just dropped
10802 leading 1 bits (assuming twos complement). */
10803 if ((bfd_signed_vma) relocation >= 0)
10804 signed_check = check;
10805 else
10806 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
10807
e95de063
MS		 10808 /* Calculate the permissable maximum and minimum values for
10809 this relocation according to whether we're relocating for
10810 Thumb-2 or not. */
10811 bitsize = howto->bitsize;
5e866f5a 10812 if (!thumb2_bl)
e95de063 10813 bitsize -= 2;
f6ebfac0 10814 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 10815 reloc_signed_min = ~reloc_signed_max;
10816
252b5132 10817 /* Assumes two's complement. */
ba96a88f 10818 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 10819 overflow = TRUE;
252b5132 10820
bd97cb95 10821 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 10822 /* For a BLX instruction, make sure that the relocation is rounded up
10823 to a word boundary. This follows the semantics of the instruction
10824 which specifies that bit 1 of the target address will come from bit
10825 1 of the base address. */
10826 relocation = (relocation + 2) & ~ 3;
cb1afa5c 10827
e95de063
MS		 10828 /* Put RELOCATION back into the insn. Assumes two's complement.
10829 We use the Thumb-2 encoding, which is safe even if dealing with
10830 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 10831 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 10832 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 10833 | ((relocation >> 12) & 0x3ff)
10834 | (reloc_sign << 10);
906e58ca 10835 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 10836 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
10837 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
10838 | ((relocation >> 1) & 0x7ff);
c62e1cc3 10839
252b5132
RH		 10840 /* Put the relocated value back in the object file: */
10841 bfd_put_16 (input_bfd, upper_insn, hit_data);
10842 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10843
10844 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10845 }
10846 break;
10847
c19d1205
ZW		 10848 case R_ARM_THM_JUMP19:
10849 /* Thumb32 conditional branch instruction. */
10850 {
10851 bfd_vma relocation;
10852 bfd_boolean overflow = FALSE;
10853 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10854 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 10855 bfd_signed_vma reloc_signed_max = 0xffffe;
10856 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 10857 bfd_signed_vma signed_check;
07d6d2b8 10858 enum elf32_arm_stub_type stub_type = arm_stub_none;
c5423981
TG		 10859 struct elf32_arm_stub_hash_entry *stub_entry;
10860 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 10861
10862 /* Need to refetch the addend, reconstruct the top three bits,
10863 and squish the two 11 bit pieces together. */
10864 if (globals->use_rel)
10865 {
10866 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 10867 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 10868 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
10869 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
10870 bfd_vma lower = (lower_insn & 0x07ff);
10871
a00a1f35
MS		 10872 upper |= J1 << 6;
10873 upper |= J2 << 7;
10874 upper |= (!S) << 8;
c19d1205
ZW		 10875 upper -= 0x0100; /* Sign extend. */
10876
10877 addend = (upper << 12) | (lower << 1);
10878 signed_addend = addend;
10879 }
10880
bd97cb95 10881 /* Handle calls via the PLT. */
34e77a92 10882 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 10883 {
10884 value = (splt->output_section->vma
10885 + splt->output_offset
34e77a92 10886 + plt_offset);
bd97cb95
DJ		 10887 /* Target the Thumb stub before the ARM PLT entry. */
10888 value -= PLT_THUMB_STUB_SIZE;
10889 *unresolved_reloc_p = FALSE;
10890 }
10891
c5423981
TG		 10892 hash = (struct elf32_arm_link_hash_entry *)h;
10893
10894 stub_type = arm_type_of_stub (info, input_section, rel,
07d6d2b8
AM		 10895 st_type, &branch_type,
10896 hash, value, sym_sec,
10897 input_bfd, sym_name);
c5423981
TG		 10898 if (stub_type != arm_stub_none)
10899 {
10900 stub_entry = elf32_arm_get_stub_entry (input_section,
07d6d2b8
AM		 10901 sym_sec, h,
10902 rel, globals,
10903 stub_type);
c5423981
TG		 10904 if (stub_entry != NULL)
10905 {
07d6d2b8
AM		 10906 value = (stub_entry->stub_offset
10907 + stub_entry->stub_sec->output_offset
10908 + stub_entry->stub_sec->output_section->vma);
c5423981
TG		 10909 }
10910 }
c19d1205 10911
99059e56 10912 relocation = value + signed_addend;
c19d1205
ZW		 10913 relocation -= (input_section->output_section->vma
10914 + input_section->output_offset
10915 + rel->r_offset);
a00a1f35 10916 signed_check = (bfd_signed_vma) relocation;
c19d1205 10917
c19d1205
ZW		 10918 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10919 overflow = TRUE;
10920
10921 /* Put RELOCATION back into the insn. */
10922 {
10923 bfd_vma S = (relocation & 0x00100000) >> 20;
10924 bfd_vma J2 = (relocation & 0x00080000) >> 19;
10925 bfd_vma J1 = (relocation & 0x00040000) >> 18;
10926 bfd_vma hi = (relocation & 0x0003f000) >> 12;
10927 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
10928
a00a1f35 10929 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 10930 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
10931 }
10932
10933 /* Put the relocated value back in the object file: */
10934 bfd_put_16 (input_bfd, upper_insn, hit_data);
10935 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10936
10937 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10938 }
10939
10940 case R_ARM_THM_JUMP11:
10941 case R_ARM_THM_JUMP8:
10942 case R_ARM_THM_JUMP6:
51c5503b
NC		 10943 /* Thumb B (branch) instruction). */
10944 {
6cf9e9fe 10945 bfd_signed_vma relocation;
51c5503b
NC		 10946 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
10947 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 10948 bfd_signed_vma signed_check;
10949
c19d1205
ZW		 10950 /* CZB cannot jump backward. */
10951 if (r_type == R_ARM_THM_JUMP6)
10952 reloc_signed_min = 0;
10953
4e7fd91e 10954 if (globals->use_rel)
6cf9e9fe 10955 {
4e7fd91e
PB		 10956 /* Need to refetch addend. */
10957 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10958 if (addend & ((howto->src_mask + 1) >> 1))
10959 {
10960 signed_addend = -1;
10961 signed_addend &= ~ howto->src_mask;
10962 signed_addend |= addend;
10963 }
10964 else
10965 signed_addend = addend;
10966 /* The value in the insn has been right shifted. We need to
10967 undo this, so that we can perform the address calculation
10968 in terms of bytes. */
10969 signed_addend <<= howto->rightshift;
6cf9e9fe 10970 }
6cf9e9fe 10971 relocation = value + signed_addend;
51c5503b
NC		 10972
10973 relocation -= (input_section->output_section->vma
10974 + input_section->output_offset
10975 + rel->r_offset);
10976
6cf9e9fe
NC		 10977 relocation >>= howto->rightshift;
10978 signed_check = relocation;
c19d1205
ZW		 10979
10980 if (r_type == R_ARM_THM_JUMP6)
10981 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
10982 else
10983 relocation &= howto->dst_mask;
51c5503b 10984 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 10985
51c5503b
NC		 10986 bfd_put_16 (input_bfd, relocation, hit_data);
10987
10988 /* Assumes two's complement. */
10989 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10990 return bfd_reloc_overflow;
10991
10992 return bfd_reloc_ok;
10993 }
cedb70c5 10994
8375c36b
PB		 10995 case R_ARM_ALU_PCREL7_0:
10996 case R_ARM_ALU_PCREL15_8:
10997 case R_ARM_ALU_PCREL23_15:
10998 {
10999 bfd_vma insn;
11000 bfd_vma relocation;
11001
11002 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 11003 if (globals->use_rel)
11004 {
11005 /* Extract the addend. */
11006 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
11007 signed_addend = addend;
11008 }
8375c36b
PB		 11009 relocation = value + signed_addend;
11010
11011 relocation -= (input_section->output_section->vma
11012 + input_section->output_offset
11013 + rel->r_offset);
11014 insn = (insn & ~0xfff)
11015 | ((howto->bitpos << 7) & 0xf00)
11016 | ((relocation >> howto->bitpos) & 0xff);
11017 bfd_put_32 (input_bfd, value, hit_data);
11018 }
11019 return bfd_reloc_ok;
11020
252b5132
RH		 11021 case R_ARM_GNU_VTINHERIT:
11022 case R_ARM_GNU_VTENTRY:
11023 return bfd_reloc_ok;
11024
c19d1205 11025 case R_ARM_GOTOFF32:
252b5132 11026 /* Relocation is relative to the start of the
99059e56 11027 global offset table. */
252b5132
RH		 11028
11029 BFD_ASSERT (sgot != NULL);
11030 if (sgot == NULL)
99059e56 11031 return bfd_reloc_notsupported;
9a5aca8c 11032
cedb70c5 11033 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11034 address by one, so that attempts to call the function pointer will
11035 correctly interpret it as Thumb code. */
35fc36a8 11036 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11037 value += 1;
11038
252b5132 11039 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11040 calculation. We always want the start of .got. If we
11041 define _GLOBAL_OFFSET_TABLE in a different way, as is
11042 permitted by the ABI, we might have to change this
11043 calculation. */
252b5132 11044 value -= sgot->output_section->vma;
f21f3fe0 11045 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11046 contents, rel->r_offset, value,
00a97672 11047 rel->r_addend);
252b5132
RH		 11048
11049 case R_ARM_GOTPC:
a7c10850 11050 /* Use global offset table as symbol value. */
252b5132 11051 BFD_ASSERT (sgot != NULL);
f21f3fe0 11052
252b5132 11053 if (sgot == NULL)
99059e56 11054 return bfd_reloc_notsupported;
252b5132 11055
0945cdfd 11056 *unresolved_reloc_p = FALSE;
252b5132 11057 value = sgot->output_section->vma;
f21f3fe0 11058 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11059 contents, rel->r_offset, value,
00a97672 11060 rel->r_addend);
f21f3fe0 11061
252b5132 11062 case R_ARM_GOT32:
eb043451 11063 case R_ARM_GOT_PREL:
252b5132 11064 /* Relocation is to the entry for this symbol in the
99059e56 11065 global offset table. */
252b5132
RH		 11066 if (sgot == NULL)
11067 return bfd_reloc_notsupported;
f21f3fe0 11068
34e77a92
RS		 11069 if (dynreloc_st_type == STT_GNU_IFUNC
11070 && plt_offset != (bfd_vma) -1
11071 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11072 {
11073 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11074 symbol, and the relocation resolves directly to the runtime
11075 target rather than to the .iplt entry. This means that any
11076 .got entry would be the same value as the .igot.plt entry,
11077 so there's no point creating both. */
11078 sgot = globals->root.igotplt;
11079 value = sgot->output_offset + gotplt_offset;
11080 }
11081 else if (h != NULL)
252b5132
RH		 11082 {
11083 bfd_vma off;
f21f3fe0 11084
252b5132
RH		 11085 off = h->got.offset;
11086 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11087 if ((off & 1) != 0)
252b5132 11088 {
b436d854
RS		 11089 /* We have already processsed one GOT relocation against
11090 this symbol. */
11091 off &= ~1;
11092 if (globals->root.dynamic_sections_created
11093 && !SYMBOL_REFERENCES_LOCAL (info, h))
11094 *unresolved_reloc_p = FALSE;
11095 }
11096 else
11097 {
11098 Elf_Internal_Rela outrel;
11099
6f820c85 11100 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11101 {
11102 /* If the symbol doesn't resolve locally in a static
11103 object, we have an undefined reference. If the
11104 symbol doesn't resolve locally in a dynamic object,
11105 it should be resolved by the dynamic linker. */
11106 if (globals->root.dynamic_sections_created)
11107 {
11108 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11109 *unresolved_reloc_p = FALSE;
11110 }
11111 else
11112 outrel.r_info = 0;
11113 outrel.r_addend = 0;
11114 }
252b5132
RH		 11115 else
11116 {
34e77a92 11117 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11118 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c
AO		 11119 else if (bfd_link_pic (info)
11120 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11121 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 11122 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11123 else
11124 outrel.r_info = 0;
34e77a92 11125 outrel.r_addend = dynreloc_value;
b436d854 11126 }
ee29b9fb 11127
b436d854
RS		 11128 /* The GOT entry is initialized to zero by default.
11129 See if we should install a different value. */
11130 if (outrel.r_addend != 0
11131 && (outrel.r_info == 0 || globals->use_rel))
11132 {
11133 bfd_put_32 (output_bfd, outrel.r_addend,
11134 sgot->contents + off);
11135 outrel.r_addend = 0;
252b5132 11136 }
f21f3fe0 11137
b436d854
RS		 11138 if (outrel.r_info != 0)
11139 {
11140 outrel.r_offset = (sgot->output_section->vma
11141 + sgot->output_offset
11142 + off);
11143 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11144 }
11145 h->got.offset |= 1;
11146 }
252b5132
RH		 11147 value = sgot->output_offset + off;
11148 }
11149 else
11150 {
11151 bfd_vma off;
f21f3fe0 11152
5025eb7c
AO		 11153 BFD_ASSERT (local_got_offsets != NULL
11154 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11155
252b5132 11156 off = local_got_offsets[r_symndx];
f21f3fe0 11157
252b5132
RH		 11158 /* The offset must always be a multiple of 4. We use the
11159 least significant bit to record whether we have already
9b485d32 11160 generated the necessary reloc. */
252b5132
RH		 11161 if ((off & 1) != 0)
11162 off &= ~1;
11163 else
11164 {
00a97672 11165 if (globals->use_rel)
34e77a92 11166 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 11167
0e1862bb 11168 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 11169 {
947216bf 11170 Elf_Internal_Rela outrel;
f21f3fe0 11171
34e77a92 11172 outrel.r_addend = addend + dynreloc_value;
252b5132 11173 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11174 + sgot->output_offset
252b5132 11175 + off);
34e77a92 11176 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11177 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 11178 else
11179 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 11180 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11181 }
f21f3fe0 11182
252b5132
RH		 11183 local_got_offsets[r_symndx] |= 1;
11184 }
f21f3fe0 11185
252b5132
RH		 11186 value = sgot->output_offset + off;
11187 }
eb043451
PB		 11188 if (r_type != R_ARM_GOT32)
11189 value += sgot->output_section->vma;
9a5aca8c 11190
f21f3fe0 11191 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11192 contents, rel->r_offset, value,
00a97672 11193 rel->r_addend);
f21f3fe0 11194
ba93b8ac
DJ		 11195 case R_ARM_TLS_LDO32:
11196 value = value - dtpoff_base (info);
11197
11198 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11199 contents, rel->r_offset, value,
11200 rel->r_addend);
ba93b8ac
DJ		 11201
11202 case R_ARM_TLS_LDM32:
11203 {
11204 bfd_vma off;
11205
362d30a1 11206 if (sgot == NULL)
ba93b8ac
DJ		 11207 abort ();
11208
11209 off = globals->tls_ldm_got.offset;
11210
11211 if ((off & 1) != 0)
11212 off &= ~1;
11213 else
11214 {
11215 /* If we don't know the module number, create a relocation
11216 for it. */
0e1862bb 11217 if (bfd_link_pic (info))
ba93b8ac
DJ		 11218 {
11219 Elf_Internal_Rela outrel;
ba93b8ac 11220
362d30a1 11221 if (srelgot == NULL)
ba93b8ac
DJ		 11222 abort ();
11223
00a97672 11224 outrel.r_addend = 0;
362d30a1
RS		 11225 outrel.r_offset = (sgot->output_section->vma
11226 + sgot->output_offset + off);
ba93b8ac
DJ		 11227 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11228
00a97672
RS		 11229 if (globals->use_rel)
11230 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11231 sgot->contents + off);
ba93b8ac 11232
47beaa6a 11233 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11234 }
11235 else
362d30a1 11236 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11237
11238 globals->tls_ldm_got.offset |= 1;
11239 }
11240
362d30a1 11241 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 11242 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
11243
11244 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11245 contents, rel->r_offset, value,
00a97672 11246 rel->r_addend);
ba93b8ac
DJ		 11247 }
11248
0855e32b
NS		 11249 case R_ARM_TLS_CALL:
11250 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 11251 case R_ARM_TLS_GD32:
11252 case R_ARM_TLS_IE32:
0855e32b
NS		 11253 case R_ARM_TLS_GOTDESC:
11254 case R_ARM_TLS_DESCSEQ:
11255 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11256 {
0855e32b
NS		 11257 bfd_vma off, offplt;
11258 int indx = 0;
ba93b8ac
DJ		 11259 char tls_type;
11260
0855e32b 11261 BFD_ASSERT (sgot != NULL);
ba93b8ac 11262
ba93b8ac
DJ		 11263 if (h != NULL)
11264 {
11265 bfd_boolean dyn;
11266 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11267 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11268 bfd_link_pic (info),
11269 h)
11270 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11271 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11272 {
11273 *unresolved_reloc_p = FALSE;
11274 indx = h->dynindx;
11275 }
11276 off = h->got.offset;
0855e32b 11277 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11278 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11279 }
11280 else
11281 {
0855e32b 11282 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11283 off = local_got_offsets[r_symndx];
0855e32b 11284 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11285 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11286 }
11287
0855e32b 11288 /* Linker relaxations happens from one of the
b38cadfb 11289 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11290 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11291 tls_type = GOT_TLS_IE;
0855e32b
NS		 11292
11293 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11294
11295 if ((off & 1) != 0)
11296 off &= ~1;
11297 else
11298 {
11299 bfd_boolean need_relocs = FALSE;
11300 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11301 int cur_off = off;
11302
11303 /* The GOT entries have not been initialized yet. Do it
11304 now, and emit any relocations. If both an IE GOT and a
11305 GD GOT are necessary, we emit the GD first. */
11306
0e1862bb 11307 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac 11308 && (h == NULL
95b03e4a
L		 11309 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11310 && !resolved_to_zero)
ba93b8ac
DJ		 11311 || h->root.type != bfd_link_hash_undefweak))
11312 {
11313 need_relocs = TRUE;
0855e32b 11314 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11315 }
11316
0855e32b
NS		 11317 if (tls_type & GOT_TLS_GDESC)
11318 {
47beaa6a
RS		 11319 bfd_byte *loc;
11320
0855e32b
NS		 11321 /* We should have relaxed, unless this is an undefined
11322 weak symbol. */
11323 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 11324 || bfd_link_pic (info));
0855e32b 11325 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11326 <= globals->root.sgotplt->size);
0855e32b
NS		 11327
11328 outrel.r_addend = 0;
11329 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11330 + globals->root.sgotplt->output_offset
11331 + offplt
11332 + globals->sgotplt_jump_table_size);
b38cadfb 11333
0855e32b
NS		 11334 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11335 sreloc = globals->root.srelplt;
11336 loc = sreloc->contents;
11337 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11338 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11339 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11340
11341 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11342
11343 /* For globals, the first word in the relocation gets
11344 the relocation index and the top bit set, or zero,
11345 if we're binding now. For locals, it gets the
11346 symbol's offset in the tls section. */
99059e56 11347 bfd_put_32 (output_bfd,
0855e32b
NS		 11348 !h ? value - elf_hash_table (info)->tls_sec->vma
11349 : info->flags & DF_BIND_NOW ? 0
11350 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11351 globals->root.sgotplt->contents + offplt
11352 + globals->sgotplt_jump_table_size);
11353
0855e32b 11354 /* Second word in the relocation is always zero. */
99059e56 11355 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11356 globals->root.sgotplt->contents + offplt
11357 + globals->sgotplt_jump_table_size + 4);
0855e32b 11358 }
ba93b8ac
DJ		 11359 if (tls_type & GOT_TLS_GD)
11360 {
11361 if (need_relocs)
11362 {
00a97672 11363 outrel.r_addend = 0;
362d30a1
RS		 11364 outrel.r_offset = (sgot->output_section->vma
11365 + sgot->output_offset
00a97672 11366 + cur_off);
ba93b8ac 11367 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11368
00a97672
RS		 11369 if (globals->use_rel)
11370 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11371 sgot->contents + cur_off);
00a97672 11372
47beaa6a 11373 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11374
11375 if (indx == 0)
11376 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11377 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11378 else
11379 {
00a97672 11380 outrel.r_addend = 0;
ba93b8ac
DJ		 11381 outrel.r_info = ELF32_R_INFO (indx,
11382 R_ARM_TLS_DTPOFF32);
11383 outrel.r_offset += 4;
00a97672
RS		 11384
11385 if (globals->use_rel)
11386 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11387 sgot->contents + cur_off + 4);
00a97672 11388
47beaa6a
RS		 11389 elf32_arm_add_dynreloc (output_bfd, info,
11390 srelgot, &outrel);
ba93b8ac
DJ		 11391 }
11392 }
11393 else
11394 {
11395 /* If we are not emitting relocations for a
11396 general dynamic reference, then we must be in a
11397 static link or an executable link with the
11398 symbol binding locally. Mark it as belonging
11399 to module 1, the executable. */
11400 bfd_put_32 (output_bfd, 1,
362d30a1 11401 sgot->contents + cur_off);
ba93b8ac 11402 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11403 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11404 }
11405
11406 cur_off += 8;
11407 }
11408
11409 if (tls_type & GOT_TLS_IE)
11410 {
11411 if (need_relocs)
11412 {
00a97672
RS		 11413 if (indx == 0)
11414 outrel.r_addend = value - dtpoff_base (info);
11415 else
11416 outrel.r_addend = 0;
362d30a1
RS		 11417 outrel.r_offset = (sgot->output_section->vma
11418 + sgot->output_offset
ba93b8ac
DJ		 11419 + cur_off);
11420 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11421
00a97672
RS		 11422 if (globals->use_rel)
11423 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11424 sgot->contents + cur_off);
ba93b8ac 11425
47beaa6a 11426 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11427 }
11428 else
11429 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11430 sgot->contents + cur_off);
ba93b8ac
DJ		 11431 cur_off += 4;
11432 }
11433
11434 if (h != NULL)
11435 h->got.offset |= 1;
11436 else
11437 local_got_offsets[r_symndx] |= 1;
11438 }
11439
11440 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
11441 off += 8;
0855e32b
NS		 11442 else if (tls_type & GOT_TLS_GDESC)
11443 off = offplt;
11444
11445 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11446 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11447 {
11448 bfd_signed_vma offset;
12352d3f
PB		 11449 /* TLS stubs are arm mode. The original symbol is a
11450 data object, so branch_type is bogus. */
11451 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11452 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11453 = arm_type_of_stub (info, input_section, rel,
11454 st_type, &branch_type,
0855e32b
NS		 11455 (struct elf32_arm_link_hash_entry *)h,
11456 globals->tls_trampoline, globals->root.splt,
11457 input_bfd, sym_name);
11458
11459 if (stub_type != arm_stub_none)
11460 {
11461 struct elf32_arm_stub_hash_entry *stub_entry
11462 = elf32_arm_get_stub_entry
11463 (input_section, globals->root.splt, 0, rel,
11464 globals, stub_type);
11465 offset = (stub_entry->stub_offset
11466 + stub_entry->stub_sec->output_offset
11467 + stub_entry->stub_sec->output_section->vma);
11468 }
11469 else
11470 offset = (globals->root.splt->output_section->vma
11471 + globals->root.splt->output_offset
11472 + globals->tls_trampoline);
11473
11474 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11475 {
11476 unsigned long inst;
b38cadfb
NC		 11477
11478 offset -= (input_section->output_section->vma
11479 + input_section->output_offset
11480 + rel->r_offset + 8);
0855e32b
NS		 11481
11482 inst = offset >> 2;
11483 inst &= 0x00ffffff;
11484 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11485 }
11486 else
11487 {
11488 /* Thumb blx encodes the offset in a complicated
11489 fashion. */
11490 unsigned upper_insn, lower_insn;
11491 unsigned neg;
11492
b38cadfb
NC		 11493 offset -= (input_section->output_section->vma
11494 + input_section->output_offset
0855e32b 11495 + rel->r_offset + 4);
b38cadfb 11496
12352d3f
PB		 11497 if (stub_type != arm_stub_none
11498 && arm_stub_is_thumb (stub_type))
11499 {
11500 lower_insn = 0xd000;
11501 }
11502 else
11503 {
11504 lower_insn = 0xc000;
6a631e86 11505 /* Round up the offset to a word boundary. */
12352d3f
PB		 11506 offset = (offset + 2) & ~2;
11507 }
11508
0855e32b
NS		 11509 neg = offset < 0;
11510 upper_insn = (0xf000
11511 | ((offset >> 12) & 0x3ff)
11512 | (neg << 10));
12352d3f 11513 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 11514 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 11515 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 11516 bfd_put_16 (input_bfd, upper_insn, hit_data);
11517 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11518 return bfd_reloc_ok;
11519 }
11520 }
11521 /* These relocations needs special care, as besides the fact
11522 they point somewhere in .gotplt, the addend must be
11523 adjusted accordingly depending on the type of instruction
6a631e86 11524 we refer to. */
0855e32b
NS		 11525 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
11526 {
11527 unsigned long data, insn;
11528 unsigned thumb;
b38cadfb 11529
0855e32b
NS		 11530 data = bfd_get_32 (input_bfd, hit_data);
11531 thumb = data & 1;
11532 data &= ~1u;
b38cadfb 11533
0855e32b
NS		 11534 if (thumb)
11535 {
11536 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
11537 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
11538 insn = (insn << 16)
11539 | bfd_get_16 (input_bfd,
11540 contents + rel->r_offset - data + 2);
11541 if ((insn & 0xf800c000) == 0xf000c000)
11542 /* bl/blx */
11543 value = -6;
11544 else if ((insn & 0xffffff00) == 0x4400)
11545 /* add */
11546 value = -5;
11547 else
11548 {
4eca0228 11549 _bfd_error_handler
695344c0 11550 /* xgettext:c-format */
2dcf00ce 11551 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 11552 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 11553 "referenced by TLS_GOTDESC"),
11554 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 11555 "Thumb", insn);
0855e32b
NS		 11556 return bfd_reloc_notsupported;
11557 }
11558 }
11559 else
11560 {
11561 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
11562
11563 switch (insn >> 24)
11564 {
11565 case 0xeb: /* bl */
11566 case 0xfa: /* blx */
11567 value = -4;
11568 break;
11569
11570 case 0xe0: /* add */
11571 value = -8;
11572 break;
b38cadfb 11573
0855e32b 11574 default:
4eca0228 11575 _bfd_error_handler
695344c0 11576 /* xgettext:c-format */
2dcf00ce 11577 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 11578 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 11579 "referenced by TLS_GOTDESC"),
11580 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 11581 "ARM", insn);
0855e32b
NS		 11582 return bfd_reloc_notsupported;
11583 }
11584 }
b38cadfb 11585
0855e32b
NS		 11586 value += ((globals->root.sgotplt->output_section->vma
11587 + globals->root.sgotplt->output_offset + off)
11588 - (input_section->output_section->vma
11589 + input_section->output_offset
11590 + rel->r_offset)
11591 + globals->sgotplt_jump_table_size);
11592 }
11593 else
11594 value = ((globals->root.sgot->output_section->vma
11595 + globals->root.sgot->output_offset + off)
11596 - (input_section->output_section->vma
11597 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 11598
11599 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11600 contents, rel->r_offset, value,
00a97672 11601 rel->r_addend);
ba93b8ac
DJ		 11602 }
11603
11604 case R_ARM_TLS_LE32:
3cbc1e5e 11605 if (bfd_link_dll (info))
ba93b8ac 11606 {
4eca0228 11607 _bfd_error_handler
695344c0 11608 /* xgettext:c-format */
2dcf00ce
AM		 11609 (_("%pB(%pA+%#" PRIx64 "): %s relocation not permitted "
11610 "in shared object"),
11611 input_bfd, input_section, (uint64_t) rel->r_offset, howto->name);
46691134 11612 return bfd_reloc_notsupported;
ba93b8ac
DJ		 11613 }
11614 else
11615 value = tpoff (info, value);
906e58ca 11616
ba93b8ac 11617 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11618 contents, rel->r_offset, value,
11619 rel->r_addend);
ba93b8ac 11620
319850b4
JB		 11621 case R_ARM_V4BX:
11622 if (globals->fix_v4bx)
845b51d6
PB		 11623 {
11624 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 11625
845b51d6
PB		 11626 /* Ensure that we have a BX instruction. */
11627 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 11628
845b51d6
PB		 11629 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
11630 {
11631 /* Branch to veneer. */
11632 bfd_vma glue_addr;
11633 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
11634 glue_addr -= input_section->output_section->vma
11635 + input_section->output_offset
11636 + rel->r_offset + 8;
11637 insn = (insn & 0xf0000000) | 0x0a000000
11638 | ((glue_addr >> 2) & 0x00ffffff);
11639 }
11640 else
11641 {
11642 /* Preserve Rm (lowest four bits) and the condition code
11643 (highest four bits). Other bits encode MOV PC,Rm. */
11644 insn = (insn & 0xf000000f) | 0x01a0f000;
11645 }
319850b4 11646
845b51d6
PB		 11647 bfd_put_32 (input_bfd, insn, hit_data);
11648 }
319850b4
JB		 11649 return bfd_reloc_ok;
11650
b6895b4f
PB		 11651 case R_ARM_MOVW_ABS_NC:
11652 case R_ARM_MOVT_ABS:
11653 case R_ARM_MOVW_PREL_NC:
11654 case R_ARM_MOVT_PREL:
92f5d02b
MS		 11655 /* Until we properly support segment-base-relative addressing then
11656 we assume the segment base to be zero, as for the group relocations.
11657 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
11658 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
11659 case R_ARM_MOVW_BREL_NC:
11660 case R_ARM_MOVW_BREL:
11661 case R_ARM_MOVT_BREL:
b6895b4f
PB		 11662 {
11663 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
11664
11665 if (globals->use_rel)
11666 {
11667 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 11668 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11669 }
92f5d02b 11670
b6895b4f 11671 value += signed_addend;
b6895b4f
PB		 11672
11673 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
11674 value -= (input_section->output_section->vma
11675 + input_section->output_offset + rel->r_offset);
11676
92f5d02b 11677 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 11678 return bfd_reloc_overflow;
92f5d02b 11679
35fc36a8 11680 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11681 value |= 1;
11682
11683 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 11684 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 11685 value >>= 16;
11686
11687 insn &= 0xfff0f000;
11688 insn |= value & 0xfff;
11689 insn |= (value & 0xf000) << 4;
11690 bfd_put_32 (input_bfd, insn, hit_data);
11691 }
11692 return bfd_reloc_ok;
11693
11694 case R_ARM_THM_MOVW_ABS_NC:
11695 case R_ARM_THM_MOVT_ABS:
11696 case R_ARM_THM_MOVW_PREL_NC:
11697 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 11698 /* Until we properly support segment-base-relative addressing then
11699 we assume the segment base to be zero, as for the above relocations.
11700 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
11701 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
11702 as R_ARM_THM_MOVT_ABS. */
11703 case R_ARM_THM_MOVW_BREL_NC:
11704 case R_ARM_THM_MOVW_BREL:
11705 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 11706 {
11707 bfd_vma insn;
906e58ca 11708
b6895b4f
PB		 11709 insn = bfd_get_16 (input_bfd, hit_data) << 16;
11710 insn |= bfd_get_16 (input_bfd, hit_data + 2);
11711
11712 if (globals->use_rel)
11713 {
11714 addend = ((insn >> 4) & 0xf000)
11715 | ((insn >> 15) & 0x0800)
11716 | ((insn >> 4) & 0x0700)
07d6d2b8 11717 | (insn & 0x00ff);
39623e12 11718 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11719 }
92f5d02b 11720
b6895b4f 11721 value += signed_addend;
b6895b4f
PB		 11722
11723 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
11724 value -= (input_section->output_section->vma
11725 + input_section->output_offset + rel->r_offset);
11726
92f5d02b 11727 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 11728 return bfd_reloc_overflow;
92f5d02b 11729
35fc36a8 11730 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11731 value |= 1;
11732
11733 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 11734 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 11735 value >>= 16;
11736
11737 insn &= 0xfbf08f00;
11738 insn |= (value & 0xf000) << 4;
11739 insn |= (value & 0x0800) << 15;
11740 insn |= (value & 0x0700) << 4;
11741 insn |= (value & 0x00ff);
11742
11743 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11744 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11745 }
11746 return bfd_reloc_ok;
11747
4962c51a
MS		 11748 case R_ARM_ALU_PC_G0_NC:
11749 case R_ARM_ALU_PC_G1_NC:
11750 case R_ARM_ALU_PC_G0:
11751 case R_ARM_ALU_PC_G1:
11752 case R_ARM_ALU_PC_G2:
11753 case R_ARM_ALU_SB_G0_NC:
11754 case R_ARM_ALU_SB_G1_NC:
11755 case R_ARM_ALU_SB_G0:
11756 case R_ARM_ALU_SB_G1:
11757 case R_ARM_ALU_SB_G2:
11758 {
11759 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11760 bfd_vma pc = input_section->output_section->vma
4962c51a 11761 + input_section->output_offset + rel->r_offset;
31a91d61 11762 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11763 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 11764 bfd_vma residual;
11765 bfd_vma g_n;
4962c51a 11766 bfd_signed_vma signed_value;
99059e56
RM		 11767 int group = 0;
11768
11769 /* Determine which group of bits to select. */
11770 switch (r_type)
11771 {
11772 case R_ARM_ALU_PC_G0_NC:
11773 case R_ARM_ALU_PC_G0:
11774 case R_ARM_ALU_SB_G0_NC:
11775 case R_ARM_ALU_SB_G0:
11776 group = 0;
11777 break;
11778
11779 case R_ARM_ALU_PC_G1_NC:
11780 case R_ARM_ALU_PC_G1:
11781 case R_ARM_ALU_SB_G1_NC:
11782 case R_ARM_ALU_SB_G1:
11783 group = 1;
11784 break;
11785
11786 case R_ARM_ALU_PC_G2:
11787 case R_ARM_ALU_SB_G2:
11788 group = 2;
11789 break;
11790
11791 default:
11792 abort ();
11793 }
11794
11795 /* If REL, extract the addend from the insn. If RELA, it will
11796 have already been fetched for us. */
4962c51a 11797 if (globals->use_rel)
99059e56
RM		 11798 {
11799 int negative;
11800 bfd_vma constant = insn & 0xff;
11801 bfd_vma rotation = (insn & 0xf00) >> 8;
11802
11803 if (rotation == 0)
11804 signed_addend = constant;
11805 else
11806 {
11807 /* Compensate for the fact that in the instruction, the
11808 rotation is stored in multiples of 2 bits. */
11809 rotation *= 2;
11810
11811 /* Rotate "constant" right by "rotation" bits. */
11812 signed_addend = (constant >> rotation) |
11813 (constant << (8 * sizeof (bfd_vma) - rotation));
11814 }
11815
11816 /* Determine if the instruction is an ADD or a SUB.
11817 (For REL, this determines the sign of the addend.) */
11818 negative = identify_add_or_sub (insn);
11819 if (negative == 0)
11820 {
4eca0228 11821 _bfd_error_handler
695344c0 11822 /* xgettext:c-format */
90b6238f 11823 (_("%pB(%pA+%#" PRIx64 "): only ADD or SUB instructions "
2dcf00ce
AM		 11824 "are allowed for ALU group relocations"),
11825 input_bfd, input_section, (uint64_t) rel->r_offset);
99059e56
RM		 11826 return bfd_reloc_overflow;
11827 }
11828
11829 signed_addend *= negative;
11830 }
4962c51a
MS		 11831
11832 /* Compute the value (X) to go in the place. */
99059e56
RM		 11833 if (r_type == R_ARM_ALU_PC_G0_NC
11834 || r_type == R_ARM_ALU_PC_G1_NC
11835 || r_type == R_ARM_ALU_PC_G0
11836 || r_type == R_ARM_ALU_PC_G1
11837 || r_type == R_ARM_ALU_PC_G2)
11838 /* PC relative. */
11839 signed_value = value - pc + signed_addend;
11840 else
11841 /* Section base relative. */
11842 signed_value = value - sb + signed_addend;
11843
11844 /* If the target symbol is a Thumb function, then set the
11845 Thumb bit in the address. */
35fc36a8 11846 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 11847 signed_value |= 1;
11848
99059e56
RM		 11849 /* Calculate the value of the relevant G_n, in encoded
11850 constant-with-rotation format. */
b6518b38
NC		 11851 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11852 group, &residual);
99059e56
RM		 11853
11854 /* Check for overflow if required. */
11855 if ((r_type == R_ARM_ALU_PC_G0
11856 || r_type == R_ARM_ALU_PC_G1
11857 || r_type == R_ARM_ALU_PC_G2
11858 || r_type == R_ARM_ALU_SB_G0
11859 || r_type == R_ARM_ALU_SB_G1
11860 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
11861 {
4eca0228 11862 _bfd_error_handler
695344c0 11863 /* xgettext:c-format */
90b6238f 11864 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 11865 "splitting %#" PRIx64 " for group relocation %s"),
11866 input_bfd, input_section, (uint64_t) rel->r_offset,
11867 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
11868 howto->name);
99059e56
RM		 11869 return bfd_reloc_overflow;
11870 }
11871
11872 /* Mask out the value and the ADD/SUB part of the opcode; take care
11873 not to destroy the S bit. */
11874 insn &= 0xff1ff000;
11875
11876 /* Set the opcode according to whether the value to go in the
11877 place is negative. */
11878 if (signed_value < 0)
11879 insn |= 1 << 22;
11880 else
11881 insn |= 1 << 23;
11882
11883 /* Encode the offset. */
11884 insn |= g_n;
4962c51a
MS		 11885
11886 bfd_put_32 (input_bfd, insn, hit_data);
11887 }
11888 return bfd_reloc_ok;
11889
11890 case R_ARM_LDR_PC_G0:
11891 case R_ARM_LDR_PC_G1:
11892 case R_ARM_LDR_PC_G2:
11893 case R_ARM_LDR_SB_G0:
11894 case R_ARM_LDR_SB_G1:
11895 case R_ARM_LDR_SB_G2:
11896 {
11897 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11898 bfd_vma pc = input_section->output_section->vma
4962c51a 11899 + input_section->output_offset + rel->r_offset;
31a91d61 11900 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11901 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11902 bfd_vma residual;
4962c51a 11903 bfd_signed_vma signed_value;
99059e56
RM		 11904 int group = 0;
11905
11906 /* Determine which groups of bits to calculate. */
11907 switch (r_type)
11908 {
11909 case R_ARM_LDR_PC_G0:
11910 case R_ARM_LDR_SB_G0:
11911 group = 0;
11912 break;
11913
11914 case R_ARM_LDR_PC_G1:
11915 case R_ARM_LDR_SB_G1:
11916 group = 1;
11917 break;
11918
11919 case R_ARM_LDR_PC_G2:
11920 case R_ARM_LDR_SB_G2:
11921 group = 2;
11922 break;
11923
11924 default:
11925 abort ();
11926 }
11927
11928 /* If REL, extract the addend from the insn. If RELA, it will
11929 have already been fetched for us. */
4962c51a 11930 if (globals->use_rel)
99059e56
RM		 11931 {
11932 int negative = (insn & (1 << 23)) ? 1 : -1;
11933 signed_addend = negative * (insn & 0xfff);
11934 }
4962c51a
MS		 11935
11936 /* Compute the value (X) to go in the place. */
99059e56
RM		 11937 if (r_type == R_ARM_LDR_PC_G0
11938 || r_type == R_ARM_LDR_PC_G1
11939 || r_type == R_ARM_LDR_PC_G2)
11940 /* PC relative. */
11941 signed_value = value - pc + signed_addend;
11942 else
11943 /* Section base relative. */
11944 signed_value = value - sb + signed_addend;
11945
11946 /* Calculate the value of the relevant G_{n-1} to obtain
11947 the residual at that stage. */
b6518b38
NC		 11948 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11949 group - 1, &residual);
99059e56
RM		 11950
11951 /* Check for overflow. */
11952 if (residual >= 0x1000)
11953 {
4eca0228 11954 _bfd_error_handler
695344c0 11955 /* xgettext:c-format */
90b6238f 11956 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 11957 "splitting %#" PRIx64 " for group relocation %s"),
11958 input_bfd, input_section, (uint64_t) rel->r_offset,
11959 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
11960 howto->name);
99059e56
RM		 11961 return bfd_reloc_overflow;
11962 }
11963
11964 /* Mask out the value and U bit. */
11965 insn &= 0xff7ff000;
11966
11967 /* Set the U bit if the value to go in the place is non-negative. */
11968 if (signed_value >= 0)
11969 insn |= 1 << 23;
11970
11971 /* Encode the offset. */
11972 insn |= residual;
4962c51a
MS		 11973
11974 bfd_put_32 (input_bfd, insn, hit_data);
11975 }
11976 return bfd_reloc_ok;
11977
11978 case R_ARM_LDRS_PC_G0:
11979 case R_ARM_LDRS_PC_G1:
11980 case R_ARM_LDRS_PC_G2:
11981 case R_ARM_LDRS_SB_G0:
11982 case R_ARM_LDRS_SB_G1:
11983 case R_ARM_LDRS_SB_G2:
11984 {
11985 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11986 bfd_vma pc = input_section->output_section->vma
4962c51a 11987 + input_section->output_offset + rel->r_offset;
31a91d61 11988 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11989 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11990 bfd_vma residual;
4962c51a 11991 bfd_signed_vma signed_value;
99059e56
RM		 11992 int group = 0;
11993
11994 /* Determine which groups of bits to calculate. */
11995 switch (r_type)
11996 {
11997 case R_ARM_LDRS_PC_G0:
11998 case R_ARM_LDRS_SB_G0:
11999 group = 0;
12000 break;
12001
12002 case R_ARM_LDRS_PC_G1:
12003 case R_ARM_LDRS_SB_G1:
12004 group = 1;
12005 break;
12006
12007 case R_ARM_LDRS_PC_G2:
12008 case R_ARM_LDRS_SB_G2:
12009 group = 2;
12010 break;
12011
12012 default:
12013 abort ();
12014 }
12015
12016 /* If REL, extract the addend from the insn. If RELA, it will
12017 have already been fetched for us. */
4962c51a 12018 if (globals->use_rel)
99059e56
RM		 12019 {
12020 int negative = (insn & (1 << 23)) ? 1 : -1;
12021 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
12022 }
4962c51a
MS		 12023
12024 /* Compute the value (X) to go in the place. */
99059e56
RM		 12025 if (r_type == R_ARM_LDRS_PC_G0
12026 || r_type == R_ARM_LDRS_PC_G1
12027 || r_type == R_ARM_LDRS_PC_G2)
12028 /* PC relative. */
12029 signed_value = value - pc + signed_addend;
12030 else
12031 /* Section base relative. */
12032 signed_value = value - sb + signed_addend;
12033
12034 /* Calculate the value of the relevant G_{n-1} to obtain
12035 the residual at that stage. */
b6518b38
NC		 12036 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12037 group - 1, &residual);
99059e56
RM		 12038
12039 /* Check for overflow. */
12040 if (residual >= 0x100)
12041 {
4eca0228 12042 _bfd_error_handler
695344c0 12043 /* xgettext:c-format */
90b6238f 12044 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12045 "splitting %#" PRIx64 " for group relocation %s"),
12046 input_bfd, input_section, (uint64_t) rel->r_offset,
12047 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12048 howto->name);
99059e56
RM		 12049 return bfd_reloc_overflow;
12050 }
12051
12052 /* Mask out the value and U bit. */
12053 insn &= 0xff7ff0f0;
12054
12055 /* Set the U bit if the value to go in the place is non-negative. */
12056 if (signed_value >= 0)
12057 insn |= 1 << 23;
12058
12059 /* Encode the offset. */
12060 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12061
12062 bfd_put_32 (input_bfd, insn, hit_data);
12063 }
12064 return bfd_reloc_ok;
12065
12066 case R_ARM_LDC_PC_G0:
12067 case R_ARM_LDC_PC_G1:
12068 case R_ARM_LDC_PC_G2:
12069 case R_ARM_LDC_SB_G0:
12070 case R_ARM_LDC_SB_G1:
12071 case R_ARM_LDC_SB_G2:
12072 {
12073 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12074 bfd_vma pc = input_section->output_section->vma
4962c51a 12075 + input_section->output_offset + rel->r_offset;
31a91d61 12076 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12077 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12078 bfd_vma residual;
4962c51a 12079 bfd_signed_vma signed_value;
99059e56
RM		 12080 int group = 0;
12081
12082 /* Determine which groups of bits to calculate. */
12083 switch (r_type)
12084 {
12085 case R_ARM_LDC_PC_G0:
12086 case R_ARM_LDC_SB_G0:
12087 group = 0;
12088 break;
12089
12090 case R_ARM_LDC_PC_G1:
12091 case R_ARM_LDC_SB_G1:
12092 group = 1;
12093 break;
12094
12095 case R_ARM_LDC_PC_G2:
12096 case R_ARM_LDC_SB_G2:
12097 group = 2;
12098 break;
12099
12100 default:
12101 abort ();
12102 }
12103
12104 /* If REL, extract the addend from the insn. If RELA, it will
12105 have already been fetched for us. */
4962c51a 12106 if (globals->use_rel)
99059e56
RM		 12107 {
12108 int negative = (insn & (1 << 23)) ? 1 : -1;
12109 signed_addend = negative * ((insn & 0xff) << 2);
12110 }
4962c51a
MS		 12111
12112 /* Compute the value (X) to go in the place. */
99059e56
RM		 12113 if (r_type == R_ARM_LDC_PC_G0
12114 || r_type == R_ARM_LDC_PC_G1
12115 || r_type == R_ARM_LDC_PC_G2)
12116 /* PC relative. */
12117 signed_value = value - pc + signed_addend;
12118 else
12119 /* Section base relative. */
12120 signed_value = value - sb + signed_addend;
12121
12122 /* Calculate the value of the relevant G_{n-1} to obtain
12123 the residual at that stage. */
b6518b38
NC		 12124 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12125 group - 1, &residual);
99059e56
RM		 12126
12127 /* Check for overflow. (The absolute value to go in the place must be
12128 divisible by four and, after having been divided by four, must
12129 fit in eight bits.) */
12130 if ((residual & 0x3) != 0 || residual >= 0x400)
12131 {
4eca0228 12132 _bfd_error_handler
695344c0 12133 /* xgettext:c-format */
90b6238f 12134 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12135 "splitting %#" PRIx64 " for group relocation %s"),
12136 input_bfd, input_section, (uint64_t) rel->r_offset,
12137 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12138 howto->name);
99059e56
RM		 12139 return bfd_reloc_overflow;
12140 }
12141
12142 /* Mask out the value and U bit. */
12143 insn &= 0xff7fff00;
12144
12145 /* Set the U bit if the value to go in the place is non-negative. */
12146 if (signed_value >= 0)
12147 insn |= 1 << 23;
12148
12149 /* Encode the offset. */
12150 insn |= residual >> 2;
4962c51a
MS		 12151
12152 bfd_put_32 (input_bfd, insn, hit_data);
12153 }
12154 return bfd_reloc_ok;
12155
72d98d16
MG		 12156 case R_ARM_THM_ALU_ABS_G0_NC:
12157 case R_ARM_THM_ALU_ABS_G1_NC:
12158 case R_ARM_THM_ALU_ABS_G2_NC:
12159 case R_ARM_THM_ALU_ABS_G3_NC:
12160 {
12161 const int shift_array[4] = {0, 8, 16, 24};
12162 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12163 bfd_vma addr = value;
12164 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12165
12166 /* Compute address. */
12167 if (globals->use_rel)
12168 signed_addend = insn & 0xff;
12169 addr += signed_addend;
12170 if (branch_type == ST_BRANCH_TO_THUMB)
12171 addr |= 1;
12172 /* Clean imm8 insn. */
12173 insn &= 0xff00;
12174 /* And update with correct part of address. */
12175 insn |= (addr >> shift) & 0xff;
12176 /* Update insn. */
12177 bfd_put_16 (input_bfd, insn, hit_data);
12178 }
12179
12180 *unresolved_reloc_p = FALSE;
12181 return bfd_reloc_ok;
12182
252b5132
RH		 12183 default:
12184 return bfd_reloc_notsupported;
12185 }
12186}
12187
98c1d4aa
NC		 12188/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
12189static void
07d6d2b8
AM		 12190arm_add_to_rel (bfd * abfd,
12191 bfd_byte * address,
57e8b36a 12192 reloc_howto_type * howto,
07d6d2b8 12193 bfd_signed_vma increment)
98c1d4aa 12194{
98c1d4aa
NC		 12195 bfd_signed_vma addend;
12196
bd97cb95
DJ		 12197 if (howto->type == R_ARM_THM_CALL
12198 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 12199 {
9a5aca8c
AM		 12200 int upper_insn, lower_insn;
12201 int upper, lower;
98c1d4aa 12202
9a5aca8c
AM		 12203 upper_insn = bfd_get_16 (abfd, address);
12204 lower_insn = bfd_get_16 (abfd, address + 2);
12205 upper = upper_insn & 0x7ff;
12206 lower = lower_insn & 0x7ff;
12207
12208 addend = (upper << 12) | (lower << 1);
ddda4409 12209 addend += increment;
9a5aca8c 12210 addend >>= 1;
98c1d4aa 12211
9a5aca8c
AM		 12212 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
12213 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
12214
dc810e39
AM		 12215 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
12216 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 12217 }
12218 else
12219 {
07d6d2b8 12220 bfd_vma contents;
9a5aca8c
AM		 12221
12222 contents = bfd_get_32 (abfd, address);
12223
12224 /* Get the (signed) value from the instruction. */
12225 addend = contents & howto->src_mask;
12226 if (addend & ((howto->src_mask + 1) >> 1))
12227 {
12228 bfd_signed_vma mask;
12229
12230 mask = -1;
12231 mask &= ~ howto->src_mask;
12232 addend |= mask;
12233 }
12234
12235 /* Add in the increment, (which is a byte value). */
12236 switch (howto->type)
12237 {
12238 default:
12239 addend += increment;
12240 break;
12241
12242 case R_ARM_PC24:
c6596c5e 12243 case R_ARM_PLT32:
5b5bb741
PB		 12244 case R_ARM_CALL:
12245 case R_ARM_JUMP24:
9a5aca8c 12246 addend <<= howto->size;
dc810e39 12247 addend += increment;
9a5aca8c
AM		 12248
12249 /* Should we check for overflow here ? */
12250
12251 /* Drop any undesired bits. */
12252 addend >>= howto->rightshift;
12253 break;
12254 }
12255
12256 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
12257
12258 bfd_put_32 (abfd, contents, address);
ddda4409 12259 }
98c1d4aa 12260}
252b5132 12261
ba93b8ac
DJ		 12262#define IS_ARM_TLS_RELOC(R_TYPE) \
12263 ((R_TYPE) == R_ARM_TLS_GD32 \
12264 || (R_TYPE) == R_ARM_TLS_LDO32 \
12265 || (R_TYPE) == R_ARM_TLS_LDM32 \
12266 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
12267 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
12268 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
12269 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 12270 || (R_TYPE) == R_ARM_TLS_IE32 \
12271 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
12272
12273/* Specific set of relocations for the gnu tls dialect. */
12274#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
12275 ((R_TYPE) == R_ARM_TLS_GOTDESC \
12276 || (R_TYPE) == R_ARM_TLS_CALL \
12277 || (R_TYPE) == R_ARM_THM_TLS_CALL \
12278 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
12279 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 12280
252b5132 12281/* Relocate an ARM ELF section. */
906e58ca 12282
b34976b6 12283static bfd_boolean
07d6d2b8 12284elf32_arm_relocate_section (bfd * output_bfd,
57e8b36a 12285 struct bfd_link_info * info,
07d6d2b8
AM		 12286 bfd * input_bfd,
12287 asection * input_section,
12288 bfd_byte * contents,
12289 Elf_Internal_Rela * relocs,
12290 Elf_Internal_Sym * local_syms,
12291 asection ** local_sections)
252b5132 12292{
b34976b6
AM		 12293 Elf_Internal_Shdr *symtab_hdr;
12294 struct elf_link_hash_entry **sym_hashes;
12295 Elf_Internal_Rela *rel;
12296 Elf_Internal_Rela *relend;
12297 const char *name;
b32d3aa2 12298 struct elf32_arm_link_hash_table * globals;
252b5132 12299
4e7fd91e 12300 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 12301 if (globals == NULL)
12302 return FALSE;
b491616a 12303
0ffa91dd 12304 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 12305 sym_hashes = elf_sym_hashes (input_bfd);
12306
12307 rel = relocs;
12308 relend = relocs + input_section->reloc_count;
12309 for (; rel < relend; rel++)
12310 {
07d6d2b8
AM		 12311 int r_type;
12312 reloc_howto_type * howto;
12313 unsigned long r_symndx;
12314 Elf_Internal_Sym * sym;
12315 asection * sec;
252b5132 12316 struct elf_link_hash_entry * h;
07d6d2b8
AM		 12317 bfd_vma relocation;
12318 bfd_reloc_status_type r;
12319 arelent bfd_reloc;
12320 char sym_type;
12321 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 12322 char *error_message = NULL;
f21f3fe0 12323
252b5132 12324 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 12325 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 12326 r_type = arm_real_reloc_type (globals, r_type);
252b5132 12327
ba96a88f 12328 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 12329 || r_type == R_ARM_GNU_VTINHERIT)
12330 continue;
252b5132 12331
47aeb64c
NC		 12332 howto = bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
12333
12334 if (howto == NULL)
12335 return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
252b5132 12336
252b5132
RH		 12337 h = NULL;
12338 sym = NULL;
12339 sec = NULL;
9b485d32 12340
252b5132
RH		 12341 if (r_symndx < symtab_hdr->sh_info)
12342 {
12343 sym = local_syms + r_symndx;
ba93b8ac 12344 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 12345 sec = local_sections[r_symndx];
ffcb4889
NS		 12346
12347 /* An object file might have a reference to a local
12348 undefined symbol. This is a daft object file, but we
12349 should at least do something about it. V4BX & NONE
12350 relocations do not use the symbol and are explicitly
77b4f08f
TS		 12351 allowed to use the undefined symbol, so allow those.
12352 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 12353 if (r_type != R_ARM_V4BX
12354 && r_type != R_ARM_NONE
77b4f08f 12355 && r_symndx != STN_UNDEF
ffcb4889
NS		 12356 && bfd_is_und_section (sec)
12357 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 12358 (*info->callbacks->undefined_symbol)
12359 (info, bfd_elf_string_from_elf_section
12360 (input_bfd, symtab_hdr->sh_link, sym->st_name),
12361 input_bfd, input_section,
12362 rel->r_offset, TRUE);
b38cadfb 12363
4e7fd91e 12364 if (globals->use_rel)
f8df10f4 12365 {
4e7fd91e
PB		 12366 relocation = (sec->output_section->vma
12367 + sec->output_offset
12368 + sym->st_value);
0e1862bb 12369 if (!bfd_link_relocatable (info)
ab96bf03
AM		 12370 && (sec->flags & SEC_MERGE)
12371 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 12372 {
4e7fd91e
PB		 12373 asection *msec;
12374 bfd_vma addend, value;
12375
39623e12 12376 switch (r_type)
4e7fd91e 12377 {
39623e12
PB		 12378 case R_ARM_MOVW_ABS_NC:
12379 case R_ARM_MOVT_ABS:
12380 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12381 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
12382 addend = (addend ^ 0x8000) - 0x8000;
12383 break;
f8df10f4 12384
39623e12
PB		 12385 case R_ARM_THM_MOVW_ABS_NC:
12386 case R_ARM_THM_MOVT_ABS:
12387 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
12388 << 16;
12389 value |= bfd_get_16 (input_bfd,
12390 contents + rel->r_offset + 2);
12391 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
12392 | ((value & 0x04000000) >> 15);
12393 addend = (addend ^ 0x8000) - 0x8000;
12394 break;
f8df10f4 12395
39623e12
PB		 12396 default:
12397 if (howto->rightshift
12398 || (howto->src_mask & (howto->src_mask + 1)))
12399 {
4eca0228 12400 _bfd_error_handler
695344c0 12401 /* xgettext:c-format */
2dcf00ce
AM		 12402 (_("%pB(%pA+%#" PRIx64 "): "
12403 "%s relocation against SEC_MERGE section"),
39623e12 12404 input_bfd, input_section,
2dcf00ce 12405 (uint64_t) rel->r_offset, howto->name);
39623e12
PB		 12406 return FALSE;
12407 }
12408
12409 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12410
12411 /* Get the (signed) value from the instruction. */
12412 addend = value & howto->src_mask;
12413 if (addend & ((howto->src_mask + 1) >> 1))
12414 {
12415 bfd_signed_vma mask;
12416
12417 mask = -1;
12418 mask &= ~ howto->src_mask;
12419 addend |= mask;
12420 }
12421 break;
4e7fd91e 12422 }
39623e12 12423
4e7fd91e
PB		 12424 msec = sec;
12425 addend =
12426 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
12427 - relocation;
12428 addend += msec->output_section->vma + msec->output_offset;
39623e12 12429
cc643b88 12430 /* Cases here must match those in the preceding
39623e12
PB		 12431 switch statement. */
12432 switch (r_type)
12433 {
12434 case R_ARM_MOVW_ABS_NC:
12435 case R_ARM_MOVT_ABS:
12436 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
12437 | (addend & 0xfff);
12438 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12439 break;
12440
12441 case R_ARM_THM_MOVW_ABS_NC:
12442 case R_ARM_THM_MOVT_ABS:
12443 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
12444 | (addend & 0xff) | ((addend & 0x0800) << 15);
12445 bfd_put_16 (input_bfd, value >> 16,
12446 contents + rel->r_offset);
12447 bfd_put_16 (input_bfd, value,
12448 contents + rel->r_offset + 2);
12449 break;
12450
12451 default:
12452 value = (value & ~ howto->dst_mask)
12453 | (addend & howto->dst_mask);
12454 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12455 break;
12456 }
f8df10f4 12457 }
f8df10f4 12458 }
4e7fd91e
PB		 12459 else
12460 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 12461 }
12462 else
12463 {
62d887d4 12464 bfd_boolean warned, ignored;
560e09e9 12465
b2a8e766
AM		 12466 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
12467 r_symndx, symtab_hdr, sym_hashes,
12468 h, sec, relocation,
62d887d4 12469 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 12470
12471 sym_type = h->type;
252b5132
RH		 12472 }
12473
dbaa2011 12474 if (sec != NULL && discarded_section (sec))
e4067dbb 12475 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 12476 rel, 1, relend, howto, 0, contents);
ab96bf03 12477
0e1862bb 12478 if (bfd_link_relocatable (info))
ab96bf03
AM		 12479 {
12480 /* This is a relocatable link. We don't have to change
12481 anything, unless the reloc is against a section symbol,
12482 in which case we have to adjust according to where the
12483 section symbol winds up in the output section. */
12484 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
12485 {
12486 if (globals->use_rel)
12487 arm_add_to_rel (input_bfd, contents + rel->r_offset,
12488 howto, (bfd_signed_vma) sec->output_offset);
12489 else
12490 rel->r_addend += sec->output_offset;
12491 }
12492 continue;
12493 }
12494
252b5132
RH		 12495 if (h != NULL)
12496 name = h->root.root.string;
12497 else
12498 {
12499 name = (bfd_elf_string_from_elf_section
12500 (input_bfd, symtab_hdr->sh_link, sym->st_name));
12501 if (name == NULL || *name == '\0')
12502 name = bfd_section_name (input_bfd, sec);
12503 }
f21f3fe0 12504
cf35638d 12505 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 12506 && r_type != R_ARM_NONE
12507 && (h == NULL
12508 || h->root.type == bfd_link_hash_defined
12509 || h->root.type == bfd_link_hash_defweak)
12510 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
12511 {
4eca0228 12512 _bfd_error_handler
ba93b8ac 12513 ((sym_type == STT_TLS
695344c0 12514 /* xgettext:c-format */
2dcf00ce 12515 ? _("%pB(%pA+%#" PRIx64 "): %s used with TLS symbol %s")
695344c0 12516 /* xgettext:c-format */
2dcf00ce 12517 : _("%pB(%pA+%#" PRIx64 "): %s used with non-TLS symbol %s")),
ba93b8ac
DJ		 12518 input_bfd,
12519 input_section,
2dcf00ce 12520 (uint64_t) rel->r_offset,
ba93b8ac
DJ		 12521 howto->name,
12522 name);
12523 }
12524
0855e32b 12525 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 12526 done, i.e., the relaxation produced the final output we want,
12527 and we won't let anybody mess with it. Also, we have to do
12528 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 12529 both in relaxed and non-relaxed cases. */
39d911fc
TP		 12530 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
12531 || (IS_ARM_TLS_GNU_RELOC (r_type)
12532 && !((h ? elf32_arm_hash_entry (h)->tls_type :
12533 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
12534 & GOT_TLS_GDESC)))
12535 {
12536 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
12537 contents, rel, h == NULL);
12538 /* This may have been marked unresolved because it came from
12539 a shared library. But we've just dealt with that. */
12540 unresolved_reloc = 0;
12541 }
12542 else
12543 r = bfd_reloc_continue;
b38cadfb 12544
39d911fc
TP		 12545 if (r == bfd_reloc_continue)
12546 {
12547 unsigned char branch_type =
12548 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
12549 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
12550
12551 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
12552 input_section, contents, rel,
12553 relocation, info, sec, name,
12554 sym_type, branch_type, h,
12555 &unresolved_reloc,
12556 &error_message);
12557 }
0945cdfd
DJ		 12558
12559 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
12560 because such sections are not SEC_ALLOC and thus ld.so will
12561 not process them. */
12562 if (unresolved_reloc
99059e56
RM		 12563 && !((input_section->flags & SEC_DEBUGGING) != 0
12564 && h->def_dynamic)
1d5316ab
AM		 12565 && _bfd_elf_section_offset (output_bfd, info, input_section,
12566 rel->r_offset) != (bfd_vma) -1)
0945cdfd 12567 {
4eca0228 12568 _bfd_error_handler
695344c0 12569 /* xgettext:c-format */
2dcf00ce
AM		 12570 (_("%pB(%pA+%#" PRIx64 "): "
12571 "unresolvable %s relocation against symbol `%s'"),
843fe662
L		 12572 input_bfd,
12573 input_section,
2dcf00ce 12574 (uint64_t) rel->r_offset,
843fe662
L		 12575 howto->name,
12576 h->root.root.string);
0945cdfd
DJ		 12577 return FALSE;
12578 }
252b5132
RH		 12579
12580 if (r != bfd_reloc_ok)
12581 {
252b5132
RH		 12582 switch (r)
12583 {
12584 case bfd_reloc_overflow:
cf919dfd
PB		 12585 /* If the overflowing reloc was to an undefined symbol,
12586 we have already printed one error message and there
12587 is no point complaining again. */
1a72702b
AM		 12588 if (!h || h->root.type != bfd_link_hash_undefined)
12589 (*info->callbacks->reloc_overflow)
12590 (info, (h ? &h->root : NULL), name, howto->name,
12591 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12592 break;
12593
12594 case bfd_reloc_undefined:
1a72702b
AM		 12595 (*info->callbacks->undefined_symbol)
12596 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 12597 break;
12598
12599 case bfd_reloc_outofrange:
f2a9dd69 12600 error_message = _("out of range");
252b5132
RH		 12601 goto common_error;
12602
12603 case bfd_reloc_notsupported:
f2a9dd69 12604 error_message = _("unsupported relocation");
252b5132
RH		 12605 goto common_error;
12606
12607 case bfd_reloc_dangerous:
f2a9dd69 12608 /* error_message should already be set. */
252b5132
RH		 12609 goto common_error;
12610
12611 default:
f2a9dd69 12612 error_message = _("unknown error");
8029a119 12613 /* Fall through. */
252b5132
RH		 12614
12615 common_error:
f2a9dd69 12616 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 12617 (*info->callbacks->reloc_dangerous)
12618 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12619 break;
12620 }
12621 }
12622 }
12623
b34976b6 12624 return TRUE;
252b5132
RH		 12625}
12626
91d6fa6a 12627/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 12628 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 12629 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 12630 maintaining that condition). */
12631
12632static void
12633add_unwind_table_edit (arm_unwind_table_edit **head,
12634 arm_unwind_table_edit **tail,
12635 arm_unwind_edit_type type,
12636 asection *linked_section,
91d6fa6a 12637 unsigned int tindex)
2468f9c9 12638{
21d799b5
NC		 12639 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
12640 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 12641
2468f9c9
PB		 12642 new_edit->type = type;
12643 new_edit->linked_section = linked_section;
91d6fa6a 12644 new_edit->index = tindex;
b38cadfb 12645
91d6fa6a 12646 if (tindex > 0)
2468f9c9
PB		 12647 {
12648 new_edit->next = NULL;
12649
12650 if (*tail)
12651 (*tail)->next = new_edit;
12652
12653 (*tail) = new_edit;
12654
12655 if (!*head)
12656 (*head) = new_edit;
12657 }
12658 else
12659 {
12660 new_edit->next = *head;
12661
12662 if (!*tail)
12663 *tail = new_edit;
12664
12665 *head = new_edit;
12666 }
12667}
12668
12669static _arm_elf_section_data *get_arm_elf_section_data (asection *);
12670
12671/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
12672static void
12673adjust_exidx_size(asection *exidx_sec, int adjust)
12674{
12675 asection *out_sec;
12676
12677 if (!exidx_sec->rawsize)
12678 exidx_sec->rawsize = exidx_sec->size;
12679
12680 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
12681 out_sec = exidx_sec->output_section;
12682 /* Adjust size of output section. */
12683 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
12684}
12685
12686/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
12687static void
12688insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
12689{
12690 struct _arm_elf_section_data *exidx_arm_data;
12691
12692 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12693 add_unwind_table_edit (
12694 &exidx_arm_data->u.exidx.unwind_edit_list,
12695 &exidx_arm_data->u.exidx.unwind_edit_tail,
12696 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
12697
491d01d3
YU		 12698 exidx_arm_data->additional_reloc_count++;
12699
2468f9c9
PB		 12700 adjust_exidx_size(exidx_sec, 8);
12701}
12702
12703/* Scan .ARM.exidx tables, and create a list describing edits which should be
12704 made to those tables, such that:
b38cadfb 12705
2468f9c9
PB		 12706 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
12707 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 12708 codes which have been inlined into the index).
2468f9c9 12709
85fdf906
AH		 12710 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
12711
2468f9c9 12712 The edits are applied when the tables are written
b38cadfb 12713 (in elf32_arm_write_section). */
2468f9c9
PB		 12714
12715bfd_boolean
12716elf32_arm_fix_exidx_coverage (asection **text_section_order,
12717 unsigned int num_text_sections,
85fdf906
AH		 12718 struct bfd_link_info *info,
12719 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 12720{
12721 bfd *inp;
12722 unsigned int last_second_word = 0, i;
12723 asection *last_exidx_sec = NULL;
12724 asection *last_text_sec = NULL;
12725 int last_unwind_type = -1;
12726
12727 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
12728 text sections. */
c72f2fb2 12729 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 12730 {
12731 asection *sec;
b38cadfb 12732
2468f9c9 12733 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 12734 {
2468f9c9
PB		 12735 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
12736 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 12737
dec9d5df 12738 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 12739 continue;
b38cadfb 12740
2468f9c9
PB		 12741 if (elf_sec->linked_to)
12742 {
12743 Elf_Internal_Shdr *linked_hdr
99059e56 12744 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 12745 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 12746 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 12747
12748 if (linked_sec_arm_data == NULL)
99059e56 12749 continue;
2468f9c9
PB		 12750
12751 /* Link this .ARM.exidx section back from the text section it
99059e56 12752 describes. */
2468f9c9
PB		 12753 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
12754 }
12755 }
12756 }
12757
12758 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
12759 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 12760 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 12761
12762 for (i = 0; i < num_text_sections; i++)
12763 {
12764 asection *sec = text_section_order[i];
12765 asection *exidx_sec;
12766 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
12767 struct _arm_elf_section_data *exidx_arm_data;
12768 bfd_byte *contents = NULL;
12769 int deleted_exidx_bytes = 0;
12770 bfd_vma j;
12771 arm_unwind_table_edit *unwind_edit_head = NULL;
12772 arm_unwind_table_edit *unwind_edit_tail = NULL;
12773 Elf_Internal_Shdr *hdr;
12774 bfd *ibfd;
12775
12776 if (arm_data == NULL)
99059e56 12777 continue;
2468f9c9
PB		 12778
12779 exidx_sec = arm_data->u.text.arm_exidx_sec;
12780 if (exidx_sec == NULL)
12781 {
12782 /* Section has no unwind data. */
12783 if (last_unwind_type == 0 || !last_exidx_sec)
12784 continue;
12785
12786 /* Ignore zero sized sections. */
12787 if (sec->size == 0)
12788 continue;
12789
12790 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12791 last_unwind_type = 0;
12792 continue;
12793 }
12794
22a8f80e
PB		 12795 /* Skip /DISCARD/ sections. */
12796 if (bfd_is_abs_section (exidx_sec->output_section))
12797 continue;
12798
2468f9c9
PB		 12799 hdr = &elf_section_data (exidx_sec)->this_hdr;
12800 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 12801 continue;
b38cadfb 12802
2468f9c9
PB		 12803 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12804 if (exidx_arm_data == NULL)
99059e56 12805 continue;
b38cadfb 12806
2468f9c9 12807 ibfd = exidx_sec->owner;
b38cadfb 12808
2468f9c9
PB		 12809 if (hdr->contents != NULL)
12810 contents = hdr->contents;
12811 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
12812 /* An error? */
12813 continue;
12814
ac06903d
YU		 12815 if (last_unwind_type > 0)
12816 {
12817 unsigned int first_word = bfd_get_32 (ibfd, contents);
12818 /* Add cantunwind if first unwind item does not match section
12819 start. */
12820 if (first_word != sec->vma)
12821 {
12822 insert_cantunwind_after (last_text_sec, last_exidx_sec);
12823 last_unwind_type = 0;
12824 }
12825 }
12826
2468f9c9
PB		 12827 for (j = 0; j < hdr->sh_size; j += 8)
12828 {
12829 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
12830 int unwind_type;
12831 int elide = 0;
12832
12833 /* An EXIDX_CANTUNWIND entry. */
12834 if (second_word == 1)
12835 {
12836 if (last_unwind_type == 0)
12837 elide = 1;
12838 unwind_type = 0;
12839 }
12840 /* Inlined unwinding data. Merge if equal to previous. */
12841 else if ((second_word & 0x80000000) != 0)
12842 {
85fdf906
AH		 12843 if (merge_exidx_entries
12844 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 12845 elide = 1;
12846 unwind_type = 1;
12847 last_second_word = second_word;
12848 }
12849 /* Normal table entry. In theory we could merge these too,
12850 but duplicate entries are likely to be much less common. */
12851 else
12852 unwind_type = 2;
12853
491d01d3 12854 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 12855 {
12856 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
12857 DELETE_EXIDX_ENTRY, NULL, j / 8);
12858
12859 deleted_exidx_bytes += 8;
12860 }
12861
12862 last_unwind_type = unwind_type;
12863 }
12864
12865 /* Free contents if we allocated it ourselves. */
12866 if (contents != hdr->contents)
99059e56 12867 free (contents);
2468f9c9
PB		 12868
12869 /* Record edits to be applied later (in elf32_arm_write_section). */
12870 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
12871 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 12872
2468f9c9
PB		 12873 if (deleted_exidx_bytes > 0)
12874 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
12875
12876 last_exidx_sec = exidx_sec;
12877 last_text_sec = sec;
12878 }
12879
12880 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 12881 if (!bfd_link_relocatable (info) && last_exidx_sec
12882 && last_unwind_type != 0)
2468f9c9
PB		 12883 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12884
12885 return TRUE;
12886}
12887
3e6b1042
DJ		 12888static bfd_boolean
12889elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
12890 bfd *ibfd, const char *name)
12891{
12892 asection *sec, *osec;
12893
3d4d4302 12894 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 12895 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
12896 return TRUE;
12897
12898 osec = sec->output_section;
12899 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
12900 return TRUE;
12901
12902 if (! bfd_set_section_contents (obfd, osec, sec->contents,
12903 sec->output_offset, sec->size))
12904 return FALSE;
12905
12906 return TRUE;
12907}
12908
12909static bfd_boolean
12910elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
12911{
12912 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 12913 asection *sec, *osec;
3e6b1042 12914
4dfe6ac6
NC		 12915 if (globals == NULL)
12916 return FALSE;
12917
3e6b1042
DJ		 12918 /* Invoke the regular ELF backend linker to do all the work. */
12919 if (!bfd_elf_final_link (abfd, info))
12920 return FALSE;
12921
fe33d2fa
CL		 12922 /* Process stub sections (eg BE8 encoding, ...). */
12923 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 12924 unsigned int i;
cdb21a0a
NS		 12925 for (i=0; i<htab->top_id; i++)
12926 {
12927 sec = htab->stub_group[i].stub_sec;
12928 /* Only process it once, in its link_sec slot. */
12929 if (sec && i == htab->stub_group[i].link_sec->id)
12930 {
12931 osec = sec->output_section;
12932 elf32_arm_write_section (abfd, info, sec, sec->contents);
12933 if (! bfd_set_section_contents (abfd, osec, sec->contents,
12934 sec->output_offset, sec->size))
12935 return FALSE;
12936 }
fe33d2fa 12937 }
fe33d2fa 12938
3e6b1042
DJ		 12939 /* Write out any glue sections now that we have created all the
12940 stubs. */
12941 if (globals->bfd_of_glue_owner != NULL)
12942 {
12943 if (! elf32_arm_output_glue_section (info, abfd,
12944 globals->bfd_of_glue_owner,
12945 ARM2THUMB_GLUE_SECTION_NAME))
12946 return FALSE;
12947
12948 if (! elf32_arm_output_glue_section (info, abfd,
12949 globals->bfd_of_glue_owner,
12950 THUMB2ARM_GLUE_SECTION_NAME))
12951 return FALSE;
12952
12953 if (! elf32_arm_output_glue_section (info, abfd,
12954 globals->bfd_of_glue_owner,
12955 VFP11_ERRATUM_VENEER_SECTION_NAME))
12956 return FALSE;
12957
a504d23a
LA		 12958 if (! elf32_arm_output_glue_section (info, abfd,
12959 globals->bfd_of_glue_owner,
12960 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
12961 return FALSE;
12962
3e6b1042
DJ		 12963 if (! elf32_arm_output_glue_section (info, abfd,
12964 globals->bfd_of_glue_owner,
12965 ARM_BX_GLUE_SECTION_NAME))
12966 return FALSE;
12967 }
12968
12969 return TRUE;
12970}
12971
5968a7b8
NC		 12972/* Return a best guess for the machine number based on the attributes. */
12973
12974static unsigned int
12975bfd_arm_get_mach_from_attributes (bfd * abfd)
12976{
12977 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
12978
12979 switch (arch)
12980 {
12981 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
12982 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
12983 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
12984
12985 case TAG_CPU_ARCH_V5TE:
12986 {
12987 char * name;
12988
12989 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
12990 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
12991
12992 if (name)
12993 {
12994 if (strcmp (name, "IWMMXT2") == 0)
12995 return bfd_mach_arm_iWMMXt2;
12996
12997 if (strcmp (name, "IWMMXT") == 0)
6034aab8 12998 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 12999
13000 if (strcmp (name, "XSCALE") == 0)
13001 {
13002 int wmmx;
13003
13004 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
13005 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
13006 switch (wmmx)
13007 {
13008 case 1: return bfd_mach_arm_iWMMXt;
13009 case 2: return bfd_mach_arm_iWMMXt2;
13010 default: return bfd_mach_arm_XScale;
13011 }
13012 }
5968a7b8
NC		 13013 }
13014
13015 return bfd_mach_arm_5TE;
13016 }
13017
13018 default:
13019 return bfd_mach_arm_unknown;
13020 }
13021}
13022
c178919b
NC		 13023/* Set the right machine number. */
13024
13025static bfd_boolean
57e8b36a 13026elf32_arm_object_p (bfd *abfd)
c178919b 13027{
5a6c6817 13028 unsigned int mach;
57e8b36a 13029
5a6c6817 13030 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 13031
5968a7b8
NC		 13032 if (mach == bfd_mach_arm_unknown)
13033 {
13034 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13035 mach = bfd_mach_arm_ep9312;
13036 else
13037 mach = bfd_arm_get_mach_from_attributes (abfd);
13038 }
c178919b 13039
5968a7b8 13040 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13041 return TRUE;
13042}
13043
fc830a83 13044/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13045
b34976b6 13046static bfd_boolean
57e8b36a 13047elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13048{
13049 if (elf_flags_init (abfd)
13050 && elf_elfheader (abfd)->e_flags != flags)
13051 {
fc830a83
NC		 13052 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13053 {
fd2ec330 13054 if (flags & EF_ARM_INTERWORK)
4eca0228 13055 _bfd_error_handler
90b6238f 13056 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
d003868e 13057 abfd);
fc830a83 13058 else
d003868e 13059 _bfd_error_handler
90b6238f 13060 (_("warning: clearing the interworking flag of %pB due to outside request"),
d003868e 13061 abfd);
fc830a83 13062 }
252b5132
RH		 13063 }
13064 else
13065 {
13066 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13067 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13068 }
13069
b34976b6 13070 return TRUE;
252b5132
RH		 13071}
13072
fc830a83 13073/* Copy backend specific data from one object module to another. */
9b485d32 13074
b34976b6 13075static bfd_boolean
57e8b36a 13076elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13077{
13078 flagword in_flags;
13079 flagword out_flags;
13080
0ffa91dd 13081 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13082 return TRUE;
252b5132 13083
fc830a83 13084 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13085 out_flags = elf_elfheader (obfd)->e_flags;
13086
fc830a83
NC		 13087 if (elf_flags_init (obfd)
13088 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13089 && in_flags != out_flags)
252b5132 13090 {
252b5132 13091 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 13092 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 13093 return FALSE;
252b5132
RH		 13094
13095 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 13096 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 13097 return FALSE;
252b5132
RH		 13098
13099 /* If the src and dest have different interworking flags
99059e56 13100 then turn off the interworking bit. */
fd2ec330 13101 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 13102 {
fd2ec330 13103 if (out_flags & EF_ARM_INTERWORK)
d003868e 13104 _bfd_error_handler
90b6238f 13105 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
d003868e 13106 obfd, ibfd);
252b5132 13107
fd2ec330 13108 in_flags &= ~EF_ARM_INTERWORK;
252b5132 13109 }
1006ba19
PB		 13110
13111 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 13112 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
13113 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 13114 }
13115
13116 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 13117 elf_flags_init (obfd) = TRUE;
252b5132 13118
e2349352 13119 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 13120}
13121
13122/* Values for Tag_ABI_PCS_R9_use. */
13123enum
13124{
13125 AEABI_R9_V6,
13126 AEABI_R9_SB,
13127 AEABI_R9_TLS,
13128 AEABI_R9_unused
13129};
13130
13131/* Values for Tag_ABI_PCS_RW_data. */
13132enum
13133{
13134 AEABI_PCS_RW_data_absolute,
13135 AEABI_PCS_RW_data_PCrel,
13136 AEABI_PCS_RW_data_SBrel,
13137 AEABI_PCS_RW_data_unused
13138};
13139
13140/* Values for Tag_ABI_enum_size. */
13141enum
13142{
13143 AEABI_enum_unused,
13144 AEABI_enum_short,
13145 AEABI_enum_wide,
13146 AEABI_enum_forced_wide
13147};
13148
104d59d1
JM		 13149/* Determine whether an object attribute tag takes an integer, a
13150 string or both. */
906e58ca 13151
104d59d1
JM		 13152static int
13153elf32_arm_obj_attrs_arg_type (int tag)
13154{
13155 if (tag == Tag_compatibility)
3483fe2e 13156 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 13157 else if (tag == Tag_nodefaults)
3483fe2e
AS		 13158 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
13159 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
13160 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 13161 else if (tag < 32)
3483fe2e 13162 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 13163 else
3483fe2e 13164 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 13165}
13166
5aa6ff7c
AS		 13167/* The ABI defines that Tag_conformance should be emitted first, and that
13168 Tag_nodefaults should be second (if either is defined). This sets those
13169 two positions, and bumps up the position of all the remaining tags to
13170 compensate. */
13171static int
13172elf32_arm_obj_attrs_order (int num)
13173{
3de4a297 13174 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 13175 return Tag_conformance;
3de4a297 13176 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 13177 return Tag_nodefaults;
13178 if ((num - 2) < Tag_nodefaults)
13179 return num - 2;
13180 if ((num - 1) < Tag_conformance)
13181 return num - 1;
13182 return num;
13183}
13184
e8b36cd1
JM		 13185/* Attribute numbers >=64 (mod 128) can be safely ignored. */
13186static bfd_boolean
13187elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
13188{
13189 if ((tag & 127) < 64)
13190 {
13191 _bfd_error_handler
90b6238f 13192 (_("%pB: unknown mandatory EABI object attribute %d"),
e8b36cd1
JM		 13193 abfd, tag);
13194 bfd_set_error (bfd_error_bad_value);
13195 return FALSE;
13196 }
13197 else
13198 {
13199 _bfd_error_handler
90b6238f 13200 (_("warning: %pB: unknown EABI object attribute %d"),
e8b36cd1
JM		 13201 abfd, tag);
13202 return TRUE;
13203 }
13204}
13205
91e22acd
AS		 13206/* Read the architecture from the Tag_also_compatible_with attribute, if any.
13207 Returns -1 if no architecture could be read. */
13208
13209static int
13210get_secondary_compatible_arch (bfd *abfd)
13211{
13212 obj_attribute *attr =
13213 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
13214
13215 /* Note: the tag and its argument below are uleb128 values, though
13216 currently-defined values fit in one byte for each. */
13217 if (attr->s
13218 && attr->s[0] == Tag_CPU_arch
13219 && (attr->s[1] & 128) != 128
13220 && attr->s[2] == 0)
13221 return attr->s[1];
13222
13223 /* This tag is "safely ignorable", so don't complain if it looks funny. */
13224 return -1;
13225}
13226
13227/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
13228 The tag is removed if ARCH is -1. */
13229
8e79c3df 13230static void
91e22acd 13231set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 13232{
91e22acd
AS		 13233 obj_attribute *attr =
13234 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 13235
91e22acd
AS		 13236 if (arch == -1)
13237 {
13238 attr->s = NULL;
13239 return;
8e79c3df 13240 }
91e22acd
AS		 13241
13242 /* Note: the tag and its argument below are uleb128 values, though
13243 currently-defined values fit in one byte for each. */
13244 if (!attr->s)
21d799b5 13245 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 13246 attr->s[0] = Tag_CPU_arch;
13247 attr->s[1] = arch;
13248 attr->s[2] = '\0';
8e79c3df
CM		 13249}
13250
91e22acd
AS		 13251/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
13252 into account. */
13253
13254static int
13255tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
13256 int newtag, int secondary_compat)
8e79c3df 13257{
91e22acd
AS		 13258#define T(X) TAG_CPU_ARCH_##X
13259 int tagl, tagh, result;
13260 const int v6t2[] =
13261 {
13262 T(V6T2), /* PRE_V4. */
13263 T(V6T2), /* V4. */
13264 T(V6T2), /* V4T. */
13265 T(V6T2), /* V5T. */
13266 T(V6T2), /* V5TE. */
13267 T(V6T2), /* V5TEJ. */
13268 T(V6T2), /* V6. */
13269 T(V7), /* V6KZ. */
13270 T(V6T2) /* V6T2. */
13271 };
13272 const int v6k[] =
13273 {
13274 T(V6K), /* PRE_V4. */
13275 T(V6K), /* V4. */
13276 T(V6K), /* V4T. */
13277 T(V6K), /* V5T. */
13278 T(V6K), /* V5TE. */
13279 T(V6K), /* V5TEJ. */
13280 T(V6K), /* V6. */
13281 T(V6KZ), /* V6KZ. */
13282 T(V7), /* V6T2. */
13283 T(V6K) /* V6K. */
13284 };
13285 const int v7[] =
13286 {
13287 T(V7), /* PRE_V4. */
13288 T(V7), /* V4. */
13289 T(V7), /* V4T. */
13290 T(V7), /* V5T. */
13291 T(V7), /* V5TE. */
13292 T(V7), /* V5TEJ. */
13293 T(V7), /* V6. */
13294 T(V7), /* V6KZ. */
13295 T(V7), /* V6T2. */
13296 T(V7), /* V6K. */
13297 T(V7) /* V7. */
13298 };
13299 const int v6_m[] =
13300 {
07d6d2b8
AM		 13301 -1, /* PRE_V4. */
13302 -1, /* V4. */
91e22acd
AS		 13303 T(V6K), /* V4T. */
13304 T(V6K), /* V5T. */
13305 T(V6K), /* V5TE. */
13306 T(V6K), /* V5TEJ. */
13307 T(V6K), /* V6. */
13308 T(V6KZ), /* V6KZ. */
13309 T(V7), /* V6T2. */
13310 T(V6K), /* V6K. */
13311 T(V7), /* V7. */
13312 T(V6_M) /* V6_M. */
13313 };
13314 const int v6s_m[] =
13315 {
07d6d2b8
AM		 13316 -1, /* PRE_V4. */
13317 -1, /* V4. */
91e22acd
AS		 13318 T(V6K), /* V4T. */
13319 T(V6K), /* V5T. */
13320 T(V6K), /* V5TE. */
13321 T(V6K), /* V5TEJ. */
13322 T(V6K), /* V6. */
13323 T(V6KZ), /* V6KZ. */
13324 T(V7), /* V6T2. */
13325 T(V6K), /* V6K. */
13326 T(V7), /* V7. */
13327 T(V6S_M), /* V6_M. */
13328 T(V6S_M) /* V6S_M. */
13329 };
9e3c6df6
PB		 13330 const int v7e_m[] =
13331 {
07d6d2b8
AM		 13332 -1, /* PRE_V4. */
13333 -1, /* V4. */
9e3c6df6
PB		 13334 T(V7E_M), /* V4T. */
13335 T(V7E_M), /* V5T. */
13336 T(V7E_M), /* V5TE. */
13337 T(V7E_M), /* V5TEJ. */
13338 T(V7E_M), /* V6. */
13339 T(V7E_M), /* V6KZ. */
13340 T(V7E_M), /* V6T2. */
13341 T(V7E_M), /* V6K. */
13342 T(V7E_M), /* V7. */
13343 T(V7E_M), /* V6_M. */
13344 T(V7E_M), /* V6S_M. */
13345 T(V7E_M) /* V7E_M. */
13346 };
bca38921
MGD		 13347 const int v8[] =
13348 {
13349 T(V8), /* PRE_V4. */
13350 T(V8), /* V4. */
13351 T(V8), /* V4T. */
13352 T(V8), /* V5T. */
13353 T(V8), /* V5TE. */
13354 T(V8), /* V5TEJ. */
13355 T(V8), /* V6. */
13356 T(V8), /* V6KZ. */
13357 T(V8), /* V6T2. */
13358 T(V8), /* V6K. */
13359 T(V8), /* V7. */
13360 T(V8), /* V6_M. */
13361 T(V8), /* V6S_M. */
13362 T(V8), /* V7E_M. */
13363 T(V8) /* V8. */
13364 };
bff0500d
TP		 13365 const int v8r[] =
13366 {
13367 T(V8R), /* PRE_V4. */
13368 T(V8R), /* V4. */
13369 T(V8R), /* V4T. */
13370 T(V8R), /* V5T. */
13371 T(V8R), /* V5TE. */
13372 T(V8R), /* V5TEJ. */
13373 T(V8R), /* V6. */
13374 T(V8R), /* V6KZ. */
13375 T(V8R), /* V6T2. */
13376 T(V8R), /* V6K. */
13377 T(V8R), /* V7. */
13378 T(V8R), /* V6_M. */
13379 T(V8R), /* V6S_M. */
13380 T(V8R), /* V7E_M. */
13381 T(V8), /* V8. */
13382 T(V8R), /* V8R. */
13383 };
2fd158eb
TP		 13384 const int v8m_baseline[] =
13385 {
13386 -1, /* PRE_V4. */
13387 -1, /* V4. */
13388 -1, /* V4T. */
13389 -1, /* V5T. */
13390 -1, /* V5TE. */
13391 -1, /* V5TEJ. */
13392 -1, /* V6. */
13393 -1, /* V6KZ. */
13394 -1, /* V6T2. */
13395 -1, /* V6K. */
13396 -1, /* V7. */
13397 T(V8M_BASE), /* V6_M. */
13398 T(V8M_BASE), /* V6S_M. */
13399 -1, /* V7E_M. */
13400 -1, /* V8. */
bff0500d 13401 -1, /* V8R. */
2fd158eb
TP		 13402 T(V8M_BASE) /* V8-M BASELINE. */
13403 };
13404 const int v8m_mainline[] =
13405 {
13406 -1, /* PRE_V4. */
13407 -1, /* V4. */
13408 -1, /* V4T. */
13409 -1, /* V5T. */
13410 -1, /* V5TE. */
13411 -1, /* V5TEJ. */
13412 -1, /* V6. */
13413 -1, /* V6KZ. */
13414 -1, /* V6T2. */
13415 -1, /* V6K. */
13416 T(V8M_MAIN), /* V7. */
13417 T(V8M_MAIN), /* V6_M. */
13418 T(V8M_MAIN), /* V6S_M. */
13419 T(V8M_MAIN), /* V7E_M. */
13420 -1, /* V8. */
bff0500d 13421 -1, /* V8R. */
2fd158eb
TP		 13422 T(V8M_MAIN), /* V8-M BASELINE. */
13423 T(V8M_MAIN) /* V8-M MAINLINE. */
13424 };
91e22acd
AS		 13425 const int v4t_plus_v6_m[] =
13426 {
13427 -1, /* PRE_V4. */
13428 -1, /* V4. */
13429 T(V4T), /* V4T. */
13430 T(V5T), /* V5T. */
13431 T(V5TE), /* V5TE. */
13432 T(V5TEJ), /* V5TEJ. */
13433 T(V6), /* V6. */
13434 T(V6KZ), /* V6KZ. */
13435 T(V6T2), /* V6T2. */
13436 T(V6K), /* V6K. */
13437 T(V7), /* V7. */
13438 T(V6_M), /* V6_M. */
13439 T(V6S_M), /* V6S_M. */
9e3c6df6 13440 T(V7E_M), /* V7E_M. */
bca38921 13441 T(V8), /* V8. */
bff0500d 13442 -1, /* V8R. */
2fd158eb
TP		 13443 T(V8M_BASE), /* V8-M BASELINE. */
13444 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 13445 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
13446 };
13447 const int *comb[] =
13448 {
13449 v6t2,
13450 v6k,
13451 v7,
13452 v6_m,
13453 v6s_m,
9e3c6df6 13454 v7e_m,
bca38921 13455 v8,
bff0500d 13456 v8r,
2fd158eb
TP		 13457 v8m_baseline,
13458 v8m_mainline,
91e22acd
AS		 13459 /* Pseudo-architecture. */
13460 v4t_plus_v6_m
13461 };
13462
13463 /* Check we've not got a higher architecture than we know about. */
13464
9e3c6df6 13465 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 13466 {
90b6238f 13467 _bfd_error_handler (_("error: %pB: unknown CPU architecture"), ibfd);
91e22acd
AS		 13468 return -1;
13469 }
13470
13471 /* Override old tag if we have a Tag_also_compatible_with on the output. */
13472
13473 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
13474 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
13475 oldtag = T(V4T_PLUS_V6_M);
13476
13477 /* And override the new tag if we have a Tag_also_compatible_with on the
13478 input. */
13479
13480 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
13481 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
13482 newtag = T(V4T_PLUS_V6_M);
13483
13484 tagl = (oldtag < newtag) ? oldtag : newtag;
13485 result = tagh = (oldtag > newtag) ? oldtag : newtag;
13486
13487 /* Architectures before V6KZ add features monotonically. */
13488 if (tagh <= TAG_CPU_ARCH_V6KZ)
13489 return result;
13490
4ed7ed8d 13491 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 13492
13493 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
13494 as the canonical version. */
13495 if (result == T(V4T_PLUS_V6_M))
13496 {
13497 result = T(V4T);
13498 *secondary_compat_out = T(V6_M);
13499 }
13500 else
13501 *secondary_compat_out = -1;
13502
13503 if (result == -1)
13504 {
90b6238f 13505 _bfd_error_handler (_("error: %pB: conflicting CPU architectures %d/%d"),
91e22acd
AS		 13506 ibfd, oldtag, newtag);
13507 return -1;
13508 }
13509
13510 return result;
13511#undef T
8e79c3df
CM		 13512}
13513
ac56ee8f
MGD		 13514/* Query attributes object to see if integer divide instructions may be
13515 present in an object. */
13516static bfd_boolean
13517elf32_arm_attributes_accept_div (const obj_attribute *attr)
13518{
13519 int arch = attr[Tag_CPU_arch].i;
13520 int profile = attr[Tag_CPU_arch_profile].i;
13521
13522 switch (attr[Tag_DIV_use].i)
13523 {
13524 case 0:
13525 /* Integer divide allowed if instruction contained in archetecture. */
13526 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
13527 return TRUE;
13528 else if (arch >= TAG_CPU_ARCH_V7E_M)
13529 return TRUE;
13530 else
13531 return FALSE;
13532
13533 case 1:
13534 /* Integer divide explicitly prohibited. */
13535 return FALSE;
13536
13537 default:
13538 /* Unrecognised case - treat as allowing divide everywhere. */
13539 case 2:
13540 /* Integer divide allowed in ARM state. */
13541 return TRUE;
13542 }
13543}
13544
13545/* Query attributes object to see if integer divide instructions are
13546 forbidden to be in the object. This is not the inverse of
13547 elf32_arm_attributes_accept_div. */
13548static bfd_boolean
13549elf32_arm_attributes_forbid_div (const obj_attribute *attr)
13550{
13551 return attr[Tag_DIV_use].i == 1;
13552}
13553
ee065d83
PB		 13554/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
13555 are conflicting attributes. */
906e58ca 13556
ee065d83 13557static bfd_boolean
50e03d47 13558elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 13559{
50e03d47 13560 bfd *obfd = info->output_bfd;
104d59d1
JM		 13561 obj_attribute *in_attr;
13562 obj_attribute *out_attr;
ee065d83
PB		 13563 /* Some tags have 0 = don't care, 1 = strong requirement,
13564 2 = weak requirement. */
91e22acd 13565 static const int order_021[3] = {0, 2, 1};
ee065d83 13566 int i;
91e22acd 13567 bfd_boolean result = TRUE;
9274e9de 13568 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 13569
3e6b1042
DJ		 13570 /* Skip the linker stubs file. This preserves previous behavior
13571 of accepting unknown attributes in the first input file - but
13572 is that a bug? */
13573 if (ibfd->flags & BFD_LINKER_CREATED)
13574 return TRUE;
13575
9274e9de
TG		 13576 /* Skip any input that hasn't attribute section.
13577 This enables to link object files without attribute section with
13578 any others. */
13579 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
13580 return TRUE;
13581
104d59d1 13582 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 13583 {
13584 /* This is the first object. Copy the attributes. */
104d59d1 13585 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 13586
cd21e546
MGD		 13587 out_attr = elf_known_obj_attributes_proc (obfd);
13588
004ae526
PB		 13589 /* Use the Tag_null value to indicate the attributes have been
13590 initialized. */
cd21e546 13591 out_attr[0].i = 1;
004ae526 13592
cd21e546
MGD		 13593 /* We do not output objects with Tag_MPextension_use_legacy - we move
13594 the attribute's value to Tag_MPextension_use. */
13595 if (out_attr[Tag_MPextension_use_legacy].i != 0)
13596 {
13597 if (out_attr[Tag_MPextension_use].i != 0
13598 && out_attr[Tag_MPextension_use_legacy].i
99059e56 13599 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 13600 {
13601 _bfd_error_handler
871b3ab2 13602 (_("Error: %pB has both the current and legacy "
cd21e546
MGD		 13603 "Tag_MPextension_use attributes"), ibfd);
13604 result = FALSE;
13605 }
13606
13607 out_attr[Tag_MPextension_use] =
13608 out_attr[Tag_MPextension_use_legacy];
13609 out_attr[Tag_MPextension_use_legacy].type = 0;
13610 out_attr[Tag_MPextension_use_legacy].i = 0;
13611 }
13612
13613 return result;
ee065d83
PB		 13614 }
13615
104d59d1
JM		 13616 in_attr = elf_known_obj_attributes_proc (ibfd);
13617 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 13618 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
13619 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
13620 {
5c294fee
TG		 13621 /* Ignore mismatches if the object doesn't use floating point or is
13622 floating point ABI independent. */
13623 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
13624 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13625 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 13626 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 13627 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13628 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 13629 {
13630 _bfd_error_handler
871b3ab2 13631 (_("error: %pB uses VFP register arguments, %pB does not"),
deddc40b
NS		 13632 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
13633 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 13634 result = FALSE;
ee065d83
PB		 13635 }
13636 }
13637
3de4a297 13638 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 13639 {
13640 /* Merge this attribute with existing attributes. */
13641 switch (i)
13642 {
13643 case Tag_CPU_raw_name:
13644 case Tag_CPU_name:
6a631e86 13645 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 13646 break;
13647
13648 case Tag_ABI_optimization_goals:
13649 case Tag_ABI_FP_optimization_goals:
13650 /* Use the first value seen. */
13651 break;
13652
13653 case Tag_CPU_arch:
91e22acd
AS		 13654 {
13655 int secondary_compat = -1, secondary_compat_out = -1;
13656 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 13657 int arch_attr;
13658 static const char *name_table[] =
13659 {
91e22acd
AS		 13660 /* These aren't real CPU names, but we can't guess
13661 that from the architecture version alone. */
13662 "Pre v4",
13663 "ARM v4",
13664 "ARM v4T",
13665 "ARM v5T",
13666 "ARM v5TE",
13667 "ARM v5TEJ",
13668 "ARM v6",
13669 "ARM v6KZ",
13670 "ARM v6T2",
13671 "ARM v6K",
13672 "ARM v7",
13673 "ARM v6-M",
bca38921 13674 "ARM v6S-M",
2fd158eb
TP		 13675 "ARM v8",
13676 "",
13677 "ARM v8-M.baseline",
13678 "ARM v8-M.mainline",
91e22acd
AS		 13679 };
13680
13681 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
13682 secondary_compat = get_secondary_compatible_arch (ibfd);
13683 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 13684 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
13685 &secondary_compat_out,
13686 in_attr[i].i,
13687 secondary_compat);
13688
13689 /* Return with error if failed to merge. */
13690 if (arch_attr == -1)
13691 return FALSE;
13692
13693 out_attr[i].i = arch_attr;
13694
91e22acd
AS		 13695 set_secondary_compatible_arch (obfd, secondary_compat_out);
13696
13697 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
13698 if (out_attr[i].i == saved_out_attr)
13699 ; /* Leave the names alone. */
13700 else if (out_attr[i].i == in_attr[i].i)
13701 {
13702 /* The output architecture has been changed to match the
13703 input architecture. Use the input names. */
13704 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
13705 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
13706 : NULL;
13707 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
13708 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
13709 : NULL;
13710 }
13711 else
13712 {
13713 out_attr[Tag_CPU_name].s = NULL;
13714 out_attr[Tag_CPU_raw_name].s = NULL;
13715 }
13716
13717 /* If we still don't have a value for Tag_CPU_name,
13718 make one up now. Tag_CPU_raw_name remains blank. */
13719 if (out_attr[Tag_CPU_name].s == NULL
13720 && out_attr[i].i < ARRAY_SIZE (name_table))
13721 out_attr[Tag_CPU_name].s =
13722 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
13723 }
13724 break;
13725
ee065d83
PB		 13726 case Tag_ARM_ISA_use:
13727 case Tag_THUMB_ISA_use:
ee065d83 13728 case Tag_WMMX_arch:
91e22acd
AS		 13729 case Tag_Advanced_SIMD_arch:
13730 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 13731 case Tag_ABI_FP_rounding:
ee065d83
PB		 13732 case Tag_ABI_FP_exceptions:
13733 case Tag_ABI_FP_user_exceptions:
13734 case Tag_ABI_FP_number_model:
75375b3e 13735 case Tag_FP_HP_extension:
91e22acd
AS		 13736 case Tag_CPU_unaligned_access:
13737 case Tag_T2EE_use:
91e22acd 13738 case Tag_MPextension_use:
ee065d83
PB		 13739 /* Use the largest value specified. */
13740 if (in_attr[i].i > out_attr[i].i)
13741 out_attr[i].i = in_attr[i].i;
13742 break;
13743
75375b3e 13744 case Tag_ABI_align_preserved:
91e22acd
AS		 13745 case Tag_ABI_PCS_RO_data:
13746 /* Use the smallest value specified. */
13747 if (in_attr[i].i < out_attr[i].i)
13748 out_attr[i].i = in_attr[i].i;
13749 break;
13750
75375b3e 13751 case Tag_ABI_align_needed:
91e22acd 13752 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 13753 && (in_attr[Tag_ABI_align_preserved].i == 0
13754 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 13755 {
91e22acd
AS		 13756 /* This error message should be enabled once all non-conformant
13757 binaries in the toolchain have had the attributes set
13758 properly.
ee065d83 13759 _bfd_error_handler
871b3ab2 13760 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
91e22acd
AS		 13761 obfd, ibfd);
13762 result = FALSE; */
ee065d83 13763 }
91e22acd
AS		 13764 /* Fall through. */
13765 case Tag_ABI_FP_denormal:
13766 case Tag_ABI_PCS_GOT_use:
13767 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
13768 value if greater than 2 (for future-proofing). */
13769 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
13770 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
13771 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 13772 out_attr[i].i = in_attr[i].i;
13773 break;
91e22acd 13774
75375b3e
MGD		 13775 case Tag_Virtualization_use:
13776 /* The virtualization tag effectively stores two bits of
13777 information: the intended use of TrustZone (in bit 0), and the
13778 intended use of Virtualization (in bit 1). */
13779 if (out_attr[i].i == 0)
13780 out_attr[i].i = in_attr[i].i;
13781 else if (in_attr[i].i != 0
13782 && in_attr[i].i != out_attr[i].i)
13783 {
13784 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
13785 out_attr[i].i = 3;
13786 else
13787 {
13788 _bfd_error_handler
871b3ab2
AM		 13789 (_("error: %pB: unable to merge virtualization attributes "
13790 "with %pB"),
75375b3e
MGD		 13791 obfd, ibfd);
13792 result = FALSE;
13793 }
13794 }
13795 break;
91e22acd
AS		 13796
13797 case Tag_CPU_arch_profile:
13798 if (out_attr[i].i != in_attr[i].i)
13799 {
13800 /* 0 will merge with anything.
13801 'A' and 'S' merge to 'A'.
13802 'R' and 'S' merge to 'R'.
99059e56 13803 'M' and 'A|R|S' is an error. */
91e22acd
AS		 13804 if (out_attr[i].i == 0
13805 || (out_attr[i].i == 'S'
13806 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
13807 out_attr[i].i = in_attr[i].i;
13808 else if (in_attr[i].i == 0
13809 || (in_attr[i].i == 'S'
13810 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 13811 ; /* Do nothing. */
91e22acd
AS		 13812 else
13813 {
13814 _bfd_error_handler
90b6238f 13815 (_("error: %pB: conflicting architecture profiles %c/%c"),
91e22acd
AS		 13816 ibfd,
13817 in_attr[i].i ? in_attr[i].i : '0',
13818 out_attr[i].i ? out_attr[i].i : '0');
13819 result = FALSE;
13820 }
13821 }
13822 break;
15afaa63
TP		 13823
13824 case Tag_DSP_extension:
13825 /* No need to change output value if any of:
13826 - pre (<=) ARMv5T input architecture (do not have DSP)
13827 - M input profile not ARMv7E-M and do not have DSP. */
13828 if (in_attr[Tag_CPU_arch].i <= 3
13829 || (in_attr[Tag_CPU_arch_profile].i == 'M'
13830 && in_attr[Tag_CPU_arch].i != 13
13831 && in_attr[i].i == 0))
13832 ; /* Do nothing. */
13833 /* Output value should be 0 if DSP part of architecture, ie.
13834 - post (>=) ARMv5te architecture output
13835 - A, R or S profile output or ARMv7E-M output architecture. */
13836 else if (out_attr[Tag_CPU_arch].i >= 4
13837 && (out_attr[Tag_CPU_arch_profile].i == 'A'
13838 || out_attr[Tag_CPU_arch_profile].i == 'R'
13839 || out_attr[Tag_CPU_arch_profile].i == 'S'
13840 || out_attr[Tag_CPU_arch].i == 13))
13841 out_attr[i].i = 0;
13842 /* Otherwise, DSP instructions are added and not part of output
13843 architecture. */
13844 else
13845 out_attr[i].i = 1;
13846 break;
13847
75375b3e 13848 case Tag_FP_arch:
62f3b8c8 13849 {
4547cb56
NC		 13850 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
13851 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
13852 when it's 0. It might mean absence of FP hardware if
99654aaf 13853 Tag_FP_arch is zero. */
4547cb56 13854
a715796b 13855#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 13856 static const struct
13857 {
13858 int ver;
13859 int regs;
bca38921 13860 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 13861 {
13862 {0, 0},
13863 {1, 16},
13864 {2, 16},
13865 {3, 32},
13866 {3, 16},
13867 {4, 32},
bca38921 13868 {4, 16},
a715796b
TG		 13869 {8, 32},
13870 {8, 16}
62f3b8c8
PB		 13871 };
13872 int ver;
13873 int regs;
13874 int newval;
13875
4547cb56
NC		 13876 /* If the output has no requirement about FP hardware,
13877 follow the requirement of the input. */
13878 if (out_attr[i].i == 0)
13879 {
4ec192e6
RE		 13880 /* This assert is still reasonable, we shouldn't
13881 produce the suspicious build attribute
13882 combination (See below for in_attr). */
4547cb56
NC		 13883 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
13884 out_attr[i].i = in_attr[i].i;
13885 out_attr[Tag_ABI_HardFP_use].i
13886 = in_attr[Tag_ABI_HardFP_use].i;
13887 break;
13888 }
13889 /* If the input has no requirement about FP hardware, do
13890 nothing. */
13891 else if (in_attr[i].i == 0)
13892 {
4ec192e6
RE		 13893 /* We used to assert that Tag_ABI_HardFP_use was
13894 zero here, but we should never assert when
13895 consuming an object file that has suspicious
13896 build attributes. The single precision variant
13897 of 'no FP architecture' is still 'no FP
13898 architecture', so we just ignore the tag in this
13899 case. */
4547cb56
NC		 13900 break;
13901 }
13902
13903 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 13904 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 13905
13906 /* If both the input and the output have zero Tag_ABI_HardFP_use,
13907 do nothing. */
13908 if (in_attr[Tag_ABI_HardFP_use].i == 0
13909 && out_attr[Tag_ABI_HardFP_use].i == 0)
13910 ;
13911 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 13912 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 13913 else if (in_attr[Tag_ABI_HardFP_use].i
13914 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 13915 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 13916
13917 /* Now we can handle Tag_FP_arch. */
13918
bca38921
MGD		 13919 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
13920 pick the biggest. */
13921 if (in_attr[i].i >= VFP_VERSION_COUNT
13922 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 13923 {
13924 out_attr[i] = in_attr[i];
13925 break;
13926 }
13927 /* The output uses the superset of input features
13928 (ISA version) and registers. */
13929 ver = vfp_versions[in_attr[i].i].ver;
13930 if (ver < vfp_versions[out_attr[i].i].ver)
13931 ver = vfp_versions[out_attr[i].i].ver;
13932 regs = vfp_versions[in_attr[i].i].regs;
13933 if (regs < vfp_versions[out_attr[i].i].regs)
13934 regs = vfp_versions[out_attr[i].i].regs;
13935 /* This assumes all possible supersets are also a valid
99059e56 13936 options. */
bca38921 13937 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 13938 {
13939 if (regs == vfp_versions[newval].regs
13940 && ver == vfp_versions[newval].ver)
13941 break;
13942 }
13943 out_attr[i].i = newval;
13944 }
b1cc4aeb 13945 break;
ee065d83
PB		 13946 case Tag_PCS_config:
13947 if (out_attr[i].i == 0)
13948 out_attr[i].i = in_attr[i].i;
b6009aca 13949 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 13950 {
13951 /* It's sometimes ok to mix different configs, so this is only
99059e56 13952 a warning. */
ee065d83 13953 _bfd_error_handler
90b6238f 13954 (_("warning: %pB: conflicting platform configuration"), ibfd);
ee065d83
PB		 13955 }
13956 break;
13957 case Tag_ABI_PCS_R9_use:
004ae526
PB		 13958 if (in_attr[i].i != out_attr[i].i
13959 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 13960 && in_attr[i].i != AEABI_R9_unused)
13961 {
13962 _bfd_error_handler
90b6238f 13963 (_("error: %pB: conflicting use of R9"), ibfd);
91e22acd 13964 result = FALSE;
ee065d83
PB		 13965 }
13966 if (out_attr[i].i == AEABI_R9_unused)
13967 out_attr[i].i = in_attr[i].i;
13968 break;
13969 case Tag_ABI_PCS_RW_data:
13970 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
13971 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
13972 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
13973 {
13974 _bfd_error_handler
871b3ab2 13975 (_("error: %pB: SB relative addressing conflicts with use of R9"),
ee065d83 13976 ibfd);
91e22acd 13977 result = FALSE;
ee065d83
PB		 13978 }
13979 /* Use the smallest value specified. */
13980 if (in_attr[i].i < out_attr[i].i)
13981 out_attr[i].i = in_attr[i].i;
13982 break;
ee065d83 13983 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 13984 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
13985 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 13986 {
13987 _bfd_error_handler
871b3ab2 13988 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
a9dc9481 13989 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 13990 }
a9dc9481 13991 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 13992 out_attr[i].i = in_attr[i].i;
13993 break;
ee065d83
PB		 13994 case Tag_ABI_enum_size:
13995 if (in_attr[i].i != AEABI_enum_unused)
13996 {
13997 if (out_attr[i].i == AEABI_enum_unused
13998 || out_attr[i].i == AEABI_enum_forced_wide)
13999 {
14000 /* The existing object is compatible with anything.
14001 Use whatever requirements the new object has. */
14002 out_attr[i].i = in_attr[i].i;
14003 }
14004 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 14005 && out_attr[i].i != in_attr[i].i
0ffa91dd 14006 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 14007 {
91e22acd 14008 static const char *aeabi_enum_names[] =
bf21ed78 14009 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 14010 const char *in_name =
14011 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14012 ? aeabi_enum_names[in_attr[i].i]
14013 : "<unknown>";
14014 const char *out_name =
14015 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14016 ? aeabi_enum_names[out_attr[i].i]
14017 : "<unknown>";
ee065d83 14018 _bfd_error_handler
871b3ab2 14019 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 14020 ibfd, in_name, out_name);
ee065d83
PB		 14021 }
14022 }
14023 break;
14024 case Tag_ABI_VFP_args:
14025 /* Aready done. */
14026 break;
14027 case Tag_ABI_WMMX_args:
14028 if (in_attr[i].i != out_attr[i].i)
14029 {
14030 _bfd_error_handler
871b3ab2 14031 (_("error: %pB uses iWMMXt register arguments, %pB does not"),
ee065d83 14032 ibfd, obfd);
91e22acd 14033 result = FALSE;
ee065d83
PB		 14034 }
14035 break;
7b86a9fa
AS		 14036 case Tag_compatibility:
14037 /* Merged in target-independent code. */
14038 break;
91e22acd 14039 case Tag_ABI_HardFP_use:
4547cb56 14040 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 14041 break;
14042 case Tag_ABI_FP_16bit_format:
14043 if (in_attr[i].i != 0 && out_attr[i].i != 0)
14044 {
14045 if (in_attr[i].i != out_attr[i].i)
14046 {
14047 _bfd_error_handler
871b3ab2 14048 (_("error: fp16 format mismatch between %pB and %pB"),
91e22acd
AS		 14049 ibfd, obfd);
14050 result = FALSE;
14051 }
14052 }
14053 if (in_attr[i].i != 0)
14054 out_attr[i].i = in_attr[i].i;
14055 break;
7b86a9fa 14056
cd21e546 14057 case Tag_DIV_use:
ac56ee8f
MGD		 14058 /* A value of zero on input means that the divide instruction may
14059 be used if available in the base architecture as specified via
14060 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
14061 the user did not want divide instructions. A value of 2
14062 explicitly means that divide instructions were allowed in ARM
14063 and Thumb state. */
14064 if (in_attr[i].i == out_attr[i].i)
14065 /* Do nothing. */ ;
14066 else if (elf32_arm_attributes_forbid_div (in_attr)
14067 && !elf32_arm_attributes_accept_div (out_attr))
14068 out_attr[i].i = 1;
14069 else if (elf32_arm_attributes_forbid_div (out_attr)
14070 && elf32_arm_attributes_accept_div (in_attr))
14071 out_attr[i].i = in_attr[i].i;
14072 else if (in_attr[i].i == 2)
14073 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 14074 break;
14075
14076 case Tag_MPextension_use_legacy:
14077 /* We don't output objects with Tag_MPextension_use_legacy - we
14078 move the value to Tag_MPextension_use. */
14079 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
14080 {
14081 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
14082 {
14083 _bfd_error_handler
871b3ab2 14084 (_("%pB has both the current and legacy "
b38cadfb 14085 "Tag_MPextension_use attributes"),
cd21e546
MGD		 14086 ibfd);
14087 result = FALSE;
14088 }
14089 }
14090
14091 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
14092 out_attr[Tag_MPextension_use] = in_attr[i];
14093
14094 break;
14095
91e22acd 14096 case Tag_nodefaults:
2d0bb761
AS		 14097 /* This tag is set if it exists, but the value is unused (and is
14098 typically zero). We don't actually need to do anything here -
14099 the merge happens automatically when the type flags are merged
14100 below. */
91e22acd
AS		 14101 break;
14102 case Tag_also_compatible_with:
14103 /* Already done in Tag_CPU_arch. */
14104 break;
14105 case Tag_conformance:
14106 /* Keep the attribute if it matches. Throw it away otherwise.
14107 No attribute means no claim to conform. */
14108 if (!in_attr[i].s || !out_attr[i].s
14109 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
14110 out_attr[i].s = NULL;
14111 break;
3cfad14c 14112
91e22acd 14113 default:
e8b36cd1
JM		 14114 result
14115 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 14116 }
14117
14118 /* If out_attr was copied from in_attr then it won't have a type yet. */
14119 if (in_attr[i].type && !out_attr[i].type)
14120 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 14121 }
14122
104d59d1 14123 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 14124 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 14125 return FALSE;
ee065d83 14126
104d59d1 14127 /* Check for any attributes not known on ARM. */
e8b36cd1 14128 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 14129
91e22acd 14130 return result;
252b5132
RH		 14131}
14132
3a4a14e9
PB		 14133
14134/* Return TRUE if the two EABI versions are incompatible. */
14135
14136static bfd_boolean
14137elf32_arm_versions_compatible (unsigned iver, unsigned over)
14138{
14139 /* v4 and v5 are the same spec before and after it was released,
14140 so allow mixing them. */
14141 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
14142 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
14143 return TRUE;
14144
14145 return (iver == over);
14146}
14147
252b5132
RH		 14148/* Merge backend specific data from an object file to the output
14149 object file when linking. */
9b485d32 14150
b34976b6 14151static bfd_boolean
50e03d47 14152elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 14153
9b485d32
NC		 14154/* Display the flags field. */
14155
b34976b6 14156static bfd_boolean
57e8b36a 14157elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 14158{
fc830a83
NC		 14159 FILE * file = (FILE *) ptr;
14160 unsigned long flags;
252b5132
RH		 14161
14162 BFD_ASSERT (abfd != NULL && ptr != NULL);
14163
14164 /* Print normal ELF private data. */
14165 _bfd_elf_print_private_bfd_data (abfd, ptr);
14166
fc830a83 14167 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 14168 /* Ignore init flag - it may not be set, despite the flags field
14169 containing valid data. */
252b5132 14170
9b485d32 14171 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 14172
fc830a83
NC		 14173 switch (EF_ARM_EABI_VERSION (flags))
14174 {
14175 case EF_ARM_EABI_UNKNOWN:
4cc11e76 14176 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 14177 official ARM ELF extended ABI. Hence they are only decoded if
14178 the EABI version is not set. */
fd2ec330 14179 if (flags & EF_ARM_INTERWORK)
9b485d32 14180 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 14181
fd2ec330 14182 if (flags & EF_ARM_APCS_26)
6c571f00 14183 fprintf (file, " [APCS-26]");
fc830a83 14184 else
6c571f00 14185 fprintf (file, " [APCS-32]");
9a5aca8c 14186
96a846ea
RE		 14187 if (flags & EF_ARM_VFP_FLOAT)
14188 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 14189 else if (flags & EF_ARM_MAVERICK_FLOAT)
14190 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 14191 else
14192 fprintf (file, _(" [FPA float format]"));
14193
fd2ec330 14194 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 14195 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 14196
fd2ec330 14197 if (flags & EF_ARM_PIC)
9b485d32 14198 fprintf (file, _(" [position independent]"));
fc830a83 14199
fd2ec330 14200 if (flags & EF_ARM_NEW_ABI)
9b485d32 14201 fprintf (file, _(" [new ABI]"));
9a5aca8c 14202
fd2ec330 14203 if (flags & EF_ARM_OLD_ABI)
9b485d32 14204 fprintf (file, _(" [old ABI]"));
9a5aca8c 14205
fd2ec330 14206 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 14207 fprintf (file, _(" [software FP]"));
9a5aca8c 14208
96a846ea
RE		 14209 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
14210 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 14211 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
14212 | EF_ARM_MAVERICK_FLOAT);
fc830a83 14213 break;
9a5aca8c 14214
fc830a83 14215 case EF_ARM_EABI_VER1:
9b485d32 14216 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 14217
fc830a83 14218 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 14219 fprintf (file, _(" [sorted symbol table]"));
fc830a83 14220 else
9b485d32 14221 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 14222
fc830a83
NC		 14223 flags &= ~ EF_ARM_SYMSARESORTED;
14224 break;
9a5aca8c 14225
fd2ec330
PB		 14226 case EF_ARM_EABI_VER2:
14227 fprintf (file, _(" [Version2 EABI]"));
14228
14229 if (flags & EF_ARM_SYMSARESORTED)
14230 fprintf (file, _(" [sorted symbol table]"));
14231 else
14232 fprintf (file, _(" [unsorted symbol table]"));
14233
14234 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
14235 fprintf (file, _(" [dynamic symbols use segment index]"));
14236
14237 if (flags & EF_ARM_MAPSYMSFIRST)
14238 fprintf (file, _(" [mapping symbols precede others]"));
14239
99e4ae17 14240 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 14241 | EF_ARM_MAPSYMSFIRST);
14242 break;
14243
d507cf36
PB		 14244 case EF_ARM_EABI_VER3:
14245 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 14246 break;
14247
14248 case EF_ARM_EABI_VER4:
14249 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 14250 goto eabi;
d507cf36 14251
3a4a14e9
PB		 14252 case EF_ARM_EABI_VER5:
14253 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 14254
14255 if (flags & EF_ARM_ABI_FLOAT_SOFT)
14256 fprintf (file, _(" [soft-float ABI]"));
14257
14258 if (flags & EF_ARM_ABI_FLOAT_HARD)
14259 fprintf (file, _(" [hard-float ABI]"));
14260
14261 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
14262
3a4a14e9 14263 eabi:
d507cf36
PB		 14264 if (flags & EF_ARM_BE8)
14265 fprintf (file, _(" [BE8]"));
14266
14267 if (flags & EF_ARM_LE8)
14268 fprintf (file, _(" [LE8]"));
14269
14270 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
14271 break;
14272
fc830a83 14273 default:
9b485d32 14274 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 14275 break;
14276 }
252b5132 14277
fc830a83 14278 flags &= ~ EF_ARM_EABIMASK;
252b5132 14279
fc830a83 14280 if (flags & EF_ARM_RELEXEC)
9b485d32 14281 fprintf (file, _(" [relocatable executable]"));
252b5132 14282
a5721edd 14283 flags &= ~EF_ARM_RELEXEC;
fc830a83
NC		 14284
14285 if (flags)
9b485d32 14286 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 14287
252b5132
RH		 14288 fputc ('\n', file);
14289
b34976b6 14290 return TRUE;
252b5132
RH		 14291}
14292
14293static int
57e8b36a 14294elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 14295{
2f0ca46a
NC		 14296 switch (ELF_ST_TYPE (elf_sym->st_info))
14297 {
14298 case STT_ARM_TFUNC:
14299 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 14300
2f0ca46a
NC		 14301 case STT_ARM_16BIT:
14302 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
14303 This allows us to distinguish between data used by Thumb instructions
14304 and non-data (which is probably code) inside Thumb regions of an
14305 executable. */
1a0eb693 14306 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 14307 return ELF_ST_TYPE (elf_sym->st_info);
14308 break;
9a5aca8c 14309
ce855c42
NC		 14310 default:
14311 break;
2f0ca46a
NC		 14312 }
14313
14314 return type;
252b5132 14315}
f21f3fe0 14316
252b5132 14317static asection *
07adf181
AM		 14318elf32_arm_gc_mark_hook (asection *sec,
14319 struct bfd_link_info *info,
14320 Elf_Internal_Rela *rel,
14321 struct elf_link_hash_entry *h,
14322 Elf_Internal_Sym *sym)
252b5132
RH		 14323{
14324 if (h != NULL)
07adf181 14325 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 14326 {
14327 case R_ARM_GNU_VTINHERIT:
14328 case R_ARM_GNU_VTENTRY:
07adf181
AM		 14329 return NULL;
14330 }
9ad5cbcf 14331
07adf181 14332 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 14333}
14334
780a67af
NC		 14335/* Look through the relocs for a section during the first phase. */
14336
b34976b6 14337static bfd_boolean
57e8b36a
NC		 14338elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
14339 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 14340{
b34976b6
AM		 14341 Elf_Internal_Shdr *symtab_hdr;
14342 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 14343 const Elf_Internal_Rela *rel;
14344 const Elf_Internal_Rela *rel_end;
14345 bfd *dynobj;
5e681ec4 14346 asection *sreloc;
5e681ec4 14347 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 14348 bfd_boolean call_reloc_p;
14349 bfd_boolean may_become_dynamic_p;
14350 bfd_boolean may_need_local_target_p;
ce98a316 14351 unsigned long nsyms;
9a5aca8c 14352
0e1862bb 14353 if (bfd_link_relocatable (info))
b34976b6 14354 return TRUE;
9a5aca8c 14355
0ffa91dd
NC		 14356 BFD_ASSERT (is_arm_elf (abfd));
14357
5e681ec4 14358 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14359 if (htab == NULL)
14360 return FALSE;
14361
5e681ec4 14362 sreloc = NULL;
9a5aca8c 14363
67687978
PB		 14364 /* Create dynamic sections for relocatable executables so that we can
14365 copy relocations. */
14366 if (htab->root.is_relocatable_executable
14367 && ! htab->root.dynamic_sections_created)
14368 {
14369 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
14370 return FALSE;
14371 }
14372
cbc704f3
RS		 14373 if (htab->root.dynobj == NULL)
14374 htab->root.dynobj = abfd;
34e77a92
RS		 14375 if (!create_ifunc_sections (info))
14376 return FALSE;
cbc704f3
RS		 14377
14378 dynobj = htab->root.dynobj;
14379
0ffa91dd 14380 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 14381 sym_hashes = elf_sym_hashes (abfd);
ce98a316 14382 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 14383
252b5132
RH		 14384 rel_end = relocs + sec->reloc_count;
14385 for (rel = relocs; rel < rel_end; rel++)
14386 {
34e77a92 14387 Elf_Internal_Sym *isym;
252b5132 14388 struct elf_link_hash_entry *h;
b7693d02 14389 struct elf32_arm_link_hash_entry *eh;
d42c267e 14390 unsigned int r_symndx;
eb043451 14391 int r_type;
9a5aca8c 14392
252b5132 14393 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 14394 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14395 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 14396
ce98a316
NC		 14397 if (r_symndx >= nsyms
14398 /* PR 9934: It is possible to have relocations that do not
14399 refer to symbols, thus it is also possible to have an
14400 object file containing relocations but no symbol table. */
cf35638d 14401 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 14402 {
871b3ab2 14403 _bfd_error_handler (_("%pB: bad symbol index: %d"), abfd,
4eca0228 14404 r_symndx);
ba93b8ac
DJ		 14405 return FALSE;
14406 }
14407
34e77a92
RS		 14408 h = NULL;
14409 isym = NULL;
14410 if (nsyms > 0)
973a3492 14411 {
34e77a92
RS		 14412 if (r_symndx < symtab_hdr->sh_info)
14413 {
14414 /* A local symbol. */
14415 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
14416 abfd, r_symndx);
14417 if (isym == NULL)
14418 return FALSE;
14419 }
14420 else
14421 {
14422 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14423 while (h->root.type == bfd_link_hash_indirect
14424 || h->root.type == bfd_link_hash_warning)
14425 h = (struct elf_link_hash_entry *) h->root.u.i.link;
14426 }
973a3492 14427 }
9a5aca8c 14428
b7693d02
DJ		 14429 eh = (struct elf32_arm_link_hash_entry *) h;
14430
f6e32f6d
RS		 14431 call_reloc_p = FALSE;
14432 may_become_dynamic_p = FALSE;
14433 may_need_local_target_p = FALSE;
14434
0855e32b
NS		 14435 /* Could be done earlier, if h were already available. */
14436 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 14437 switch (r_type)
99059e56 14438 {
5e681ec4 14439 case R_ARM_GOT32:
eb043451 14440 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14441 case R_ARM_TLS_GD32:
14442 case R_ARM_TLS_IE32:
0855e32b
NS		 14443 case R_ARM_TLS_GOTDESC:
14444 case R_ARM_TLS_DESCSEQ:
14445 case R_ARM_THM_TLS_DESCSEQ:
14446 case R_ARM_TLS_CALL:
14447 case R_ARM_THM_TLS_CALL:
5e681ec4 14448 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 14449 {
14450 int tls_type, old_tls_type;
5e681ec4 14451
ba93b8ac
DJ		 14452 switch (r_type)
14453 {
14454 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 14455
ba93b8ac 14456 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 14457
0855e32b
NS		 14458 case R_ARM_TLS_GOTDESC:
14459 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
14460 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
14461 tls_type = GOT_TLS_GDESC; break;
b38cadfb 14462
ba93b8ac
DJ		 14463 default: tls_type = GOT_NORMAL; break;
14464 }
252b5132 14465
0e1862bb 14466 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 14467 info->flags |= DF_STATIC_TLS;
14468
ba93b8ac
DJ		 14469 if (h != NULL)
14470 {
14471 h->got.refcount++;
14472 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
14473 }
14474 else
14475 {
ba93b8ac 14476 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 14477 if (!elf32_arm_allocate_local_sym_info (abfd))
14478 return FALSE;
14479 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 14480 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
14481 }
14482
0855e32b 14483 /* If a variable is accessed with both tls methods, two
99059e56 14484 slots may be created. */
0855e32b
NS		 14485 if (GOT_TLS_GD_ANY_P (old_tls_type)
14486 && GOT_TLS_GD_ANY_P (tls_type))
14487 tls_type |= old_tls_type;
14488
14489 /* We will already have issued an error message if there
14490 is a TLS/non-TLS mismatch, based on the symbol
14491 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 14492 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
14493 && tls_type != GOT_NORMAL)
14494 tls_type |= old_tls_type;
14495
0855e32b 14496 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 14497 method, we're able to relax. Turn off the GDESC flag,
14498 without messing up with any other kind of tls types
6a631e86 14499 that may be involved. */
0855e32b
NS		 14500 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
14501 tls_type &= ~GOT_TLS_GDESC;
14502
ba93b8ac
DJ		 14503 if (old_tls_type != tls_type)
14504 {
14505 if (h != NULL)
14506 elf32_arm_hash_entry (h)->tls_type = tls_type;
14507 else
14508 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
14509 }
14510 }
8029a119 14511 /* Fall through. */
ba93b8ac
DJ		 14512
14513 case R_ARM_TLS_LDM32:
14514 if (r_type == R_ARM_TLS_LDM32)
14515 htab->tls_ldm_got.refcount++;
8029a119 14516 /* Fall through. */
252b5132 14517
c19d1205 14518 case R_ARM_GOTOFF32:
5e681ec4 14519 case R_ARM_GOTPC:
cbc704f3
RS		 14520 if (htab->root.sgot == NULL
14521 && !create_got_section (htab->root.dynobj, info))
14522 return FALSE;
252b5132
RH		 14523 break;
14524
252b5132 14525 case R_ARM_PC24:
7359ea65 14526 case R_ARM_PLT32:
5b5bb741
PB		 14527 case R_ARM_CALL:
14528 case R_ARM_JUMP24:
eb043451 14529 case R_ARM_PREL31:
c19d1205 14530 case R_ARM_THM_CALL:
bd97cb95
DJ		 14531 case R_ARM_THM_JUMP24:
14532 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 14533 call_reloc_p = TRUE;
14534 may_need_local_target_p = TRUE;
14535 break;
14536
14537 case R_ARM_ABS12:
14538 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
14539 ldr __GOTT_INDEX__ offsets. */
14540 if (!htab->vxworks_p)
14541 {
14542 may_need_local_target_p = TRUE;
14543 break;
14544 }
aebf9be7 14545 else goto jump_over;
9eaff861 14546
f6e32f6d 14547 /* Fall through. */
39623e12 14548
96c23d59
JM		 14549 case R_ARM_MOVW_ABS_NC:
14550 case R_ARM_MOVT_ABS:
14551 case R_ARM_THM_MOVW_ABS_NC:
14552 case R_ARM_THM_MOVT_ABS:
0e1862bb 14553 if (bfd_link_pic (info))
96c23d59 14554 {
4eca0228 14555 _bfd_error_handler
871b3ab2 14556 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
96c23d59
JM		 14557 abfd, elf32_arm_howto_table_1[r_type].name,
14558 (h) ? h->root.root.string : "a local symbol");
14559 bfd_set_error (bfd_error_bad_value);
14560 return FALSE;
14561 }
14562
14563 /* Fall through. */
39623e12
PB		 14564 case R_ARM_ABS32:
14565 case R_ARM_ABS32_NOI:
aebf9be7 14566 jump_over:
0e1862bb 14567 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 14568 {
14569 h->pointer_equality_needed = 1;
14570 }
14571 /* Fall through. */
39623e12
PB		 14572 case R_ARM_REL32:
14573 case R_ARM_REL32_NOI:
b6895b4f
PB		 14574 case R_ARM_MOVW_PREL_NC:
14575 case R_ARM_MOVT_PREL:
b6895b4f
PB		 14576 case R_ARM_THM_MOVW_PREL_NC:
14577 case R_ARM_THM_MOVT_PREL:
39623e12 14578
b7693d02 14579 /* Should the interworking branches be listed here? */
0e1862bb 14580 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 14581 && (sec->flags & SEC_ALLOC) != 0)
14582 {
14583 if (h == NULL
469a3493 14584 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14585 {
14586 /* In shared libraries and relocatable executables,
14587 we treat local relative references as calls;
14588 see the related SYMBOL_CALLS_LOCAL code in
14589 allocate_dynrelocs. */
14590 call_reloc_p = TRUE;
14591 may_need_local_target_p = TRUE;
14592 }
14593 else
14594 /* We are creating a shared library or relocatable
14595 executable, and this is a reloc against a global symbol,
14596 or a non-PC-relative reloc against a local symbol.
14597 We may need to copy the reloc into the output. */
14598 may_become_dynamic_p = TRUE;
14599 }
f6e32f6d
RS		 14600 else
14601 may_need_local_target_p = TRUE;
252b5132
RH		 14602 break;
14603
99059e56
RM		 14604 /* This relocation describes the C++ object vtable hierarchy.
14605 Reconstruct it for later use during GC. */
14606 case R_ARM_GNU_VTINHERIT:
14607 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
14608 return FALSE;
14609 break;
14610
14611 /* This relocation describes which C++ vtable entries are actually
14612 used. Record for later use during GC. */
14613 case R_ARM_GNU_VTENTRY:
14614 BFD_ASSERT (h != NULL);
14615 if (h != NULL
14616 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
14617 return FALSE;
14618 break;
14619 }
f6e32f6d
RS		 14620
14621 if (h != NULL)
14622 {
14623 if (call_reloc_p)
14624 /* We may need a .plt entry if the function this reloc
14625 refers to is in a different object, regardless of the
14626 symbol's type. We can't tell for sure yet, because
14627 something later might force the symbol local. */
14628 h->needs_plt = 1;
14629 else if (may_need_local_target_p)
14630 /* If this reloc is in a read-only section, we might
14631 need a copy reloc. We can't check reliably at this
14632 stage whether the section is read-only, as input
14633 sections have not yet been mapped to output sections.
14634 Tentatively set the flag for now, and correct in
14635 adjust_dynamic_symbol. */
14636 h->non_got_ref = 1;
14637 }
14638
34e77a92
RS		 14639 if (may_need_local_target_p
14640 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 14641 {
34e77a92
RS		 14642 union gotplt_union *root_plt;
14643 struct arm_plt_info *arm_plt;
14644 struct arm_local_iplt_info *local_iplt;
14645
14646 if (h != NULL)
14647 {
14648 root_plt = &h->plt;
14649 arm_plt = &eh->plt;
14650 }
14651 else
14652 {
14653 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
14654 if (local_iplt == NULL)
14655 return FALSE;
14656 root_plt = &local_iplt->root;
14657 arm_plt = &local_iplt->arm;
14658 }
14659
f6e32f6d
RS		 14660 /* If the symbol is a function that doesn't bind locally,
14661 this relocation will need a PLT entry. */
a8c887dd
NC		 14662 if (root_plt->refcount != -1)
14663 root_plt->refcount += 1;
34e77a92
RS		 14664
14665 if (!call_reloc_p)
14666 arm_plt->noncall_refcount++;
f6e32f6d
RS		 14667
14668 /* It's too early to use htab->use_blx here, so we have to
14669 record possible blx references separately from
14670 relocs that definitely need a thumb stub. */
14671
14672 if (r_type == R_ARM_THM_CALL)
34e77a92 14673 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 14674
14675 if (r_type == R_ARM_THM_JUMP24
14676 || r_type == R_ARM_THM_JUMP19)
34e77a92 14677 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 14678 }
14679
14680 if (may_become_dynamic_p)
14681 {
14682 struct elf_dyn_relocs *p, **head;
14683
14684 /* Create a reloc section in dynobj. */
14685 if (sreloc == NULL)
14686 {
14687 sreloc = _bfd_elf_make_dynamic_reloc_section
14688 (sec, dynobj, 2, abfd, ! htab->use_rel);
14689
14690 if (sreloc == NULL)
14691 return FALSE;
14692
14693 /* BPABI objects never have dynamic relocations mapped. */
14694 if (htab->symbian_p)
14695 {
14696 flagword flags;
14697
14698 flags = bfd_get_section_flags (dynobj, sreloc);
14699 flags &= ~(SEC_LOAD | SEC_ALLOC);
14700 bfd_set_section_flags (dynobj, sreloc, flags);
14701 }
14702 }
14703
14704 /* If this is a global symbol, count the number of
14705 relocations we need for this symbol. */
14706 if (h != NULL)
14707 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
14708 else
14709 {
34e77a92
RS		 14710 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14711 if (head == NULL)
f6e32f6d 14712 return FALSE;
f6e32f6d
RS		 14713 }
14714
14715 p = *head;
14716 if (p == NULL || p->sec != sec)
14717 {
14718 bfd_size_type amt = sizeof *p;
14719
14720 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
14721 if (p == NULL)
14722 return FALSE;
14723 p->next = *head;
14724 *head = p;
14725 p->sec = sec;
14726 p->count = 0;
14727 p->pc_count = 0;
14728 }
14729
469a3493 14730 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 14731 p->pc_count += 1;
14732 p->count += 1;
14733 }
252b5132 14734 }
f21f3fe0 14735
b34976b6 14736 return TRUE;
252b5132
RH		 14737}
14738
9eaff861
AO		 14739static void
14740elf32_arm_update_relocs (asection *o,
14741 struct bfd_elf_section_reloc_data *reldata)
14742{
14743 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
14744 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
14745 const struct elf_backend_data *bed;
14746 _arm_elf_section_data *eado;
14747 struct bfd_link_order *p;
14748 bfd_byte *erela_head, *erela;
14749 Elf_Internal_Rela *irela_head, *irela;
14750 Elf_Internal_Shdr *rel_hdr;
14751 bfd *abfd;
14752 unsigned int count;
14753
14754 eado = get_arm_elf_section_data (o);
14755
14756 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
14757 return;
14758
14759 abfd = o->owner;
14760 bed = get_elf_backend_data (abfd);
14761 rel_hdr = reldata->hdr;
14762
14763 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
14764 {
14765 swap_in = bed->s->swap_reloc_in;
14766 swap_out = bed->s->swap_reloc_out;
14767 }
14768 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
14769 {
14770 swap_in = bed->s->swap_reloca_in;
14771 swap_out = bed->s->swap_reloca_out;
14772 }
14773 else
14774 abort ();
14775
14776 erela_head = rel_hdr->contents;
14777 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
14778 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
14779
14780 erela = erela_head;
14781 irela = irela_head;
14782 count = 0;
14783
14784 for (p = o->map_head.link_order; p; p = p->next)
14785 {
14786 if (p->type == bfd_section_reloc_link_order
14787 || p->type == bfd_symbol_reloc_link_order)
14788 {
14789 (*swap_in) (abfd, erela, irela);
14790 erela += rel_hdr->sh_entsize;
14791 irela++;
14792 count++;
14793 }
14794 else if (p->type == bfd_indirect_link_order)
14795 {
14796 struct bfd_elf_section_reloc_data *input_reldata;
14797 arm_unwind_table_edit *edit_list, *edit_tail;
14798 _arm_elf_section_data *eadi;
14799 bfd_size_type j;
14800 bfd_vma offset;
14801 asection *i;
14802
14803 i = p->u.indirect.section;
14804
14805 eadi = get_arm_elf_section_data (i);
14806 edit_list = eadi->u.exidx.unwind_edit_list;
14807 edit_tail = eadi->u.exidx.unwind_edit_tail;
14808 offset = o->vma + i->output_offset;
14809
14810 if (eadi->elf.rel.hdr &&
14811 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
14812 input_reldata = &eadi->elf.rel;
14813 else if (eadi->elf.rela.hdr &&
14814 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
14815 input_reldata = &eadi->elf.rela;
14816 else
14817 abort ();
14818
14819 if (edit_list)
14820 {
14821 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
14822 {
14823 arm_unwind_table_edit *edit_node, *edit_next;
14824 bfd_vma bias;
c48182bf 14825 bfd_vma reloc_index;
9eaff861
AO		 14826
14827 (*swap_in) (abfd, erela, irela);
c48182bf 14828 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 14829
14830 bias = 0;
14831 edit_node = edit_list;
14832 for (edit_next = edit_list;
c48182bf 14833 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 14834 edit_next = edit_node->next)
14835 {
14836 bias++;
14837 edit_node = edit_next;
14838 }
14839
14840 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 14841 || edit_node->index != reloc_index)
9eaff861
AO		 14842 {
14843 irela->r_offset -= bias * 8;
14844 irela++;
14845 count++;
14846 }
14847
14848 erela += rel_hdr->sh_entsize;
14849 }
14850
14851 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
14852 {
14853 /* New relocation entity. */
14854 asection *text_sec = edit_tail->linked_section;
14855 asection *text_out = text_sec->output_section;
14856 bfd_vma exidx_offset = offset + i->size - 8;
14857
14858 irela->r_addend = 0;
14859 irela->r_offset = exidx_offset;
14860 irela->r_info = ELF32_R_INFO
14861 (text_out->target_index, R_ARM_PREL31);
14862 irela++;
14863 count++;
14864 }
14865 }
14866 else
14867 {
14868 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
14869 {
14870 (*swap_in) (abfd, erela, irela);
14871 erela += rel_hdr->sh_entsize;
14872 irela++;
14873 }
14874
14875 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
14876 }
14877 }
14878 }
14879
14880 reldata->count = count;
14881 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
14882
14883 erela = erela_head;
14884 irela = irela_head;
14885 while (count > 0)
14886 {
14887 (*swap_out) (abfd, irela, erela);
14888 erela += rel_hdr->sh_entsize;
14889 irela++;
14890 count--;
14891 }
14892
14893 free (irela_head);
14894
14895 /* Hashes are no longer valid. */
14896 free (reldata->hashes);
14897 reldata->hashes = NULL;
14898}
14899
6a5bb875 14900/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 14901 required if the corresponding code section is marked. Similarly, ARMv8-M
14902 secure entry functions can only be referenced by SG veneers which are
14903 created after the GC process. They need to be marked in case they reside in
14904 their own section (as would be the case if code was compiled with
14905 -ffunction-sections). */
6a5bb875
PB		 14906
14907static bfd_boolean
906e58ca
NC		 14908elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
14909 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 14910{
14911 bfd *sub;
14912 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 14913 asection *cmse_sec;
14914 obj_attribute *out_attr;
14915 Elf_Internal_Shdr *symtab_hdr;
14916 unsigned i, sym_count, ext_start;
14917 const struct elf_backend_data *bed;
14918 struct elf_link_hash_entry **sym_hashes;
14919 struct elf32_arm_link_hash_entry *cmse_hash;
14920 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
6a5bb875 14921
7f6ab9f8
AM		 14922 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
14923
4ba2ef8f
TP		 14924 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
14925 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
14926 && out_attr[Tag_CPU_arch_profile].i == 'M';
14927
6a5bb875
PB		 14928 /* Marking EH data may cause additional code sections to be marked,
14929 requiring multiple passes. */
14930 again = TRUE;
14931 while (again)
14932 {
14933 again = FALSE;
c72f2fb2 14934 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 14935 {
14936 asection *o;
14937
0ffa91dd 14938 if (! is_arm_elf (sub))
6a5bb875
PB		 14939 continue;
14940
14941 elf_shdrp = elf_elfsections (sub);
14942 for (o = sub->sections; o != NULL; o = o->next)
14943 {
14944 Elf_Internal_Shdr *hdr;
0ffa91dd 14945
6a5bb875 14946 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 14947 if (hdr->sh_type == SHT_ARM_EXIDX
14948 && hdr->sh_link
14949 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 14950 && !o->gc_mark
14951 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
14952 {
14953 again = TRUE;
14954 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
14955 return FALSE;
14956 }
14957 }
4ba2ef8f
TP		 14958
14959 /* Mark section holding ARMv8-M secure entry functions. We mark all
14960 of them so no need for a second browsing. */
14961 if (is_v8m && first_bfd_browse)
14962 {
14963 sym_hashes = elf_sym_hashes (sub);
14964 bed = get_elf_backend_data (sub);
14965 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
14966 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
14967 ext_start = symtab_hdr->sh_info;
14968
14969 /* Scan symbols. */
14970 for (i = ext_start; i < sym_count; i++)
14971 {
14972 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
14973
14974 /* Assume it is a special symbol. If not, cmse_scan will
14975 warn about it and user can do something about it. */
14976 if (ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
14977 {
14978 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 14979 if (!cmse_sec->gc_mark
14980 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f
TP		 14981 return FALSE;
14982 }
14983 }
14984 }
6a5bb875 14985 }
4ba2ef8f 14986 first_bfd_browse = FALSE;
6a5bb875
PB		 14987 }
14988
14989 return TRUE;
14990}
14991
3c9458e9
NC		 14992/* Treat mapping symbols as special target symbols. */
14993
14994static bfd_boolean
14995elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
14996{
b0796911
PB		 14997 return bfd_is_arm_special_symbol_name (sym->name,
14998 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 14999}
15000
0367ecfb
NC		 15001/* This is a copy of elf_find_function() from elf.c except that
15002 ARM mapping symbols are ignored when looking for function names
15003 and STT_ARM_TFUNC is considered to a function type. */
252b5132 15004
0367ecfb 15005static bfd_boolean
07d6d2b8 15006arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 15007 asymbol ** symbols,
fb167eb2 15008 asection * section,
07d6d2b8 15009 bfd_vma offset,
0367ecfb
NC		 15010 const char ** filename_ptr,
15011 const char ** functionname_ptr)
15012{
15013 const char * filename = NULL;
15014 asymbol * func = NULL;
15015 bfd_vma low_func = 0;
15016 asymbol ** p;
252b5132
RH		 15017
15018 for (p = symbols; *p != NULL; p++)
15019 {
15020 elf_symbol_type *q;
15021
15022 q = (elf_symbol_type *) *p;
15023
252b5132
RH		 15024 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
15025 {
15026 default:
15027 break;
15028 case STT_FILE:
15029 filename = bfd_asymbol_name (&q->symbol);
15030 break;
252b5132
RH		 15031 case STT_FUNC:
15032 case STT_ARM_TFUNC:
9d2da7ca 15033 case STT_NOTYPE:
b0796911 15034 /* Skip mapping symbols. */
0367ecfb 15035 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 15036 && bfd_is_arm_special_symbol_name (q->symbol.name,
15037 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 15038 continue;
15039 /* Fall through. */
6b40fcba 15040 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 15041 && q->symbol.value >= low_func
15042 && q->symbol.value <= offset)
15043 {
15044 func = (asymbol *) q;
15045 low_func = q->symbol.value;
15046 }
15047 break;
15048 }
15049 }
15050
15051 if (func == NULL)
b34976b6 15052 return FALSE;
252b5132 15053
0367ecfb
NC		 15054 if (filename_ptr)
15055 *filename_ptr = filename;
15056 if (functionname_ptr)
15057 *functionname_ptr = bfd_asymbol_name (func);
15058
15059 return TRUE;
906e58ca 15060}
0367ecfb
NC		 15061
15062
15063/* Find the nearest line to a particular section and offset, for error
15064 reporting. This code is a duplicate of the code in elf.c, except
15065 that it uses arm_elf_find_function. */
15066
15067static bfd_boolean
07d6d2b8
AM		 15068elf32_arm_find_nearest_line (bfd * abfd,
15069 asymbol ** symbols,
15070 asection * section,
15071 bfd_vma offset,
0367ecfb
NC		 15072 const char ** filename_ptr,
15073 const char ** functionname_ptr,
fb167eb2
AM		 15074 unsigned int * line_ptr,
15075 unsigned int * discriminator_ptr)
0367ecfb
NC		 15076{
15077 bfd_boolean found = FALSE;
15078
fb167eb2 15079 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 15080 filename_ptr, functionname_ptr,
fb167eb2
AM		 15081 line_ptr, discriminator_ptr,
15082 dwarf_debug_sections, 0,
0367ecfb
NC		 15083 & elf_tdata (abfd)->dwarf2_find_line_info))
15084 {
15085 if (!*functionname_ptr)
fb167eb2 15086 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15087 *filename_ptr ? NULL : filename_ptr,
15088 functionname_ptr);
f21f3fe0 15089
0367ecfb
NC		 15090 return TRUE;
15091 }
15092
fb167eb2
AM		 15093 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
15094 uses DWARF1. */
15095
0367ecfb
NC		 15096 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
15097 & found, filename_ptr,
15098 functionname_ptr, line_ptr,
15099 & elf_tdata (abfd)->line_info))
15100 return FALSE;
15101
15102 if (found && (*functionname_ptr || *line_ptr))
15103 return TRUE;
15104
15105 if (symbols == NULL)
15106 return FALSE;
15107
fb167eb2 15108 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15109 filename_ptr, functionname_ptr))
15110 return FALSE;
15111
15112 *line_ptr = 0;
b34976b6 15113 return TRUE;
252b5132
RH		 15114}
15115
4ab527b0 15116static bfd_boolean
07d6d2b8 15117elf32_arm_find_inliner_info (bfd * abfd,
4ab527b0
FF		 15118 const char ** filename_ptr,
15119 const char ** functionname_ptr,
15120 unsigned int * line_ptr)
15121{
15122 bfd_boolean found;
15123 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
15124 functionname_ptr, line_ptr,
15125 & elf_tdata (abfd)->dwarf2_find_line_info);
15126 return found;
15127}
15128
63c1f59d
AM		 15129/* Find dynamic relocs for H that apply to read-only sections. */
15130
15131static asection *
15132readonly_dynrelocs (struct elf_link_hash_entry *h)
15133{
15134 struct elf_dyn_relocs *p;
15135
15136 for (p = elf32_arm_hash_entry (h)->dyn_relocs; p != NULL; p = p->next)
15137 {
15138 asection *s = p->sec->output_section;
15139
15140 if (s != NULL && (s->flags & SEC_READONLY) != 0)
15141 return p->sec;
15142 }
15143 return NULL;
15144}
15145
252b5132
RH		 15146/* Adjust a symbol defined by a dynamic object and referenced by a
15147 regular object. The current definition is in some section of the
15148 dynamic object, but we're not including those sections. We have to
15149 change the definition to something the rest of the link can
15150 understand. */
15151
b34976b6 15152static bfd_boolean
57e8b36a
NC		 15153elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
15154 struct elf_link_hash_entry * h)
252b5132
RH		 15155{
15156 bfd * dynobj;
5474d94f 15157 asection *s, *srel;
b7693d02 15158 struct elf32_arm_link_hash_entry * eh;
67687978 15159 struct elf32_arm_link_hash_table *globals;
252b5132 15160
67687978 15161 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15162 if (globals == NULL)
15163 return FALSE;
15164
252b5132
RH		 15165 dynobj = elf_hash_table (info)->dynobj;
15166
15167 /* Make sure we know what is going on here. */
15168 BFD_ASSERT (dynobj != NULL
f5385ebf 15169 && (h->needs_plt
34e77a92 15170 || h->type == STT_GNU_IFUNC
60d67dc8 15171 || h->is_weakalias
f5385ebf
AM		 15172 || (h->def_dynamic
15173 && h->ref_regular
15174 && !h->def_regular)));
252b5132 15175
b7693d02
DJ		 15176 eh = (struct elf32_arm_link_hash_entry *) h;
15177
252b5132
RH		 15178 /* If this is a function, put it in the procedure linkage table. We
15179 will fill in the contents of the procedure linkage table later,
15180 when we know the address of the .got section. */
34e77a92 15181 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 15182 {
34e77a92
RS		 15183 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
15184 symbol binds locally. */
5e681ec4 15185 if (h->plt.refcount <= 0
34e77a92
RS		 15186 || (h->type != STT_GNU_IFUNC
15187 && (SYMBOL_CALLS_LOCAL (info, h)
15188 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
15189 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 15190 {
15191 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 15192 file, but the symbol was never referred to by a dynamic
15193 object, or if all references were garbage collected. In
15194 such a case, we don't actually need to build a procedure
15195 linkage table, and we can just do a PC24 reloc instead. */
15196 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15197 eh->plt.thumb_refcount = 0;
15198 eh->plt.maybe_thumb_refcount = 0;
15199 eh->plt.noncall_refcount = 0;
f5385ebf 15200 h->needs_plt = 0;
252b5132
RH		 15201 }
15202
b34976b6 15203 return TRUE;
252b5132 15204 }
5e681ec4 15205 else
b7693d02
DJ		 15206 {
15207 /* It's possible that we incorrectly decided a .plt reloc was
15208 needed for an R_ARM_PC24 or similar reloc to a non-function sym
15209 in check_relocs. We can't decide accurately between function
15210 and non-function syms in check-relocs; Objects loaded later in
15211 the link may change h->type. So fix it now. */
15212 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15213 eh->plt.thumb_refcount = 0;
15214 eh->plt.maybe_thumb_refcount = 0;
15215 eh->plt.noncall_refcount = 0;
b7693d02 15216 }
252b5132
RH		 15217
15218 /* If this is a weak symbol, and there is a real definition, the
15219 processor independent code will have arranged for us to see the
15220 real definition first, and we can just use the same value. */
60d67dc8 15221 if (h->is_weakalias)
252b5132 15222 {
60d67dc8
AM		 15223 struct elf_link_hash_entry *def = weakdef (h);
15224 BFD_ASSERT (def->root.type == bfd_link_hash_defined);
15225 h->root.u.def.section = def->root.u.def.section;
15226 h->root.u.def.value = def->root.u.def.value;
b34976b6 15227 return TRUE;
252b5132
RH		 15228 }
15229
ba93b8ac
DJ		 15230 /* If there are no non-GOT references, we do not need a copy
15231 relocation. */
15232 if (!h->non_got_ref)
15233 return TRUE;
15234
252b5132
RH		 15235 /* This is a reference to a symbol defined by a dynamic object which
15236 is not a function. */
15237
15238 /* If we are creating a shared library, we must presume that the
15239 only references to the symbol are via the global offset table.
15240 For such cases we need not do anything here; the relocations will
67687978
PB		 15241 be handled correctly by relocate_section. Relocatable executables
15242 can reference data in shared objects directly, so we don't need to
15243 do anything here. */
0e1862bb 15244 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 15245 return TRUE;
252b5132
RH		 15246
15247 /* We must allocate the symbol in our .dynbss section, which will
15248 become part of the .bss section of the executable. There will be
15249 an entry for this symbol in the .dynsym section. The dynamic
15250 object will contain position independent code, so all references
15251 from the dynamic object to this symbol will go through the global
15252 offset table. The dynamic linker will use the .dynsym entry to
15253 determine the address it must put in the global offset table, so
15254 both the dynamic object and the regular object will refer to the
15255 same memory location for the variable. */
5522f910
NC		 15256 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
15257 linker to copy the initial value out of the dynamic object and into
15258 the runtime process image. We need to remember the offset into the
00a97672 15259 .rel(a).bss section we are going to use. */
5474d94f
AM		 15260 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
15261 {
15262 s = globals->root.sdynrelro;
15263 srel = globals->root.sreldynrelro;
15264 }
15265 else
15266 {
15267 s = globals->root.sdynbss;
15268 srel = globals->root.srelbss;
15269 }
5522f910
NC		 15270 if (info->nocopyreloc == 0
15271 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 15272 && h->size != 0)
252b5132 15273 {
47beaa6a 15274 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 15275 h->needs_copy = 1;
252b5132
RH		 15276 }
15277
6cabe1ea 15278 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 15279}
15280
5e681ec4
PB		 15281/* Allocate space in .plt, .got and associated reloc sections for
15282 dynamic relocs. */
15283
15284static bfd_boolean
47beaa6a 15285allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 15286{
15287 struct bfd_link_info *info;
15288 struct elf32_arm_link_hash_table *htab;
15289 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 15290 struct elf_dyn_relocs *p;
5e681ec4
PB		 15291
15292 if (h->root.type == bfd_link_hash_indirect)
15293 return TRUE;
15294
e6a6bb22
AM		 15295 eh = (struct elf32_arm_link_hash_entry *) h;
15296
5e681ec4
PB		 15297 info = (struct bfd_link_info *) inf;
15298 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15299 if (htab == NULL)
15300 return FALSE;
5e681ec4 15301
34e77a92 15302 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 15303 && h->plt.refcount > 0)
15304 {
15305 /* Make sure this symbol is output as a dynamic symbol.
15306 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 15307 if (h->dynindx == -1 && !h->forced_local
15308 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 15309 {
c152c796 15310 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15311 return FALSE;
15312 }
15313
34e77a92
RS		 15314 /* If the call in the PLT entry binds locally, the associated
15315 GOT entry should use an R_ARM_IRELATIVE relocation instead of
15316 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
15317 than the .plt section. */
15318 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
15319 {
15320 eh->is_iplt = 1;
15321 if (eh->plt.noncall_refcount == 0
15322 && SYMBOL_REFERENCES_LOCAL (info, h))
15323 /* All non-call references can be resolved directly.
15324 This means that they can (and in some cases, must)
15325 resolve directly to the run-time target, rather than
15326 to the PLT. That in turns means that any .got entry
15327 would be equal to the .igot.plt entry, so there's
15328 no point having both. */
15329 h->got.refcount = 0;
15330 }
15331
0e1862bb 15332 if (bfd_link_pic (info)
34e77a92 15333 || eh->is_iplt
7359ea65 15334 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 15335 {
34e77a92 15336 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 15337
5e681ec4
PB		 15338 /* If this symbol is not defined in a regular file, and we are
15339 not generating a shared library, then set the symbol to this
15340 location in the .plt. This is required to make function
15341 pointers compare as equal between the normal executable and
15342 the shared library. */
0e1862bb 15343 if (! bfd_link_pic (info)
f5385ebf 15344 && !h->def_regular)
5e681ec4 15345 {
34e77a92 15346 h->root.u.def.section = htab->root.splt;
5e681ec4 15347 h->root.u.def.value = h->plt.offset;
5e681ec4 15348
67d74e43
DJ		 15349 /* Make sure the function is not marked as Thumb, in case
15350 it is the target of an ABS32 relocation, which will
15351 point to the PLT entry. */
39d911fc 15352 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 15353 }
022f8312 15354
00a97672
RS		 15355 /* VxWorks executables have a second set of relocations for
15356 each PLT entry. They go in a separate relocation section,
15357 which is processed by the kernel loader. */
0e1862bb 15358 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 15359 {
15360 /* There is a relocation for the initial PLT entry:
15361 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
15362 if (h->plt.offset == htab->plt_header_size)
47beaa6a 15363 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 15364
15365 /* There are two extra relocations for each subsequent
15366 PLT entry: an R_ARM_32 relocation for the GOT entry,
15367 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 15368 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 15369 }
5e681ec4
PB		 15370 }
15371 else
15372 {
15373 h->plt.offset = (bfd_vma) -1;
f5385ebf 15374 h->needs_plt = 0;
5e681ec4
PB		 15375 }
15376 }
15377 else
15378 {
15379 h->plt.offset = (bfd_vma) -1;
f5385ebf 15380 h->needs_plt = 0;
5e681ec4
PB		 15381 }
15382
0855e32b
NS		 15383 eh = (struct elf32_arm_link_hash_entry *) h;
15384 eh->tlsdesc_got = (bfd_vma) -1;
15385
5e681ec4
PB		 15386 if (h->got.refcount > 0)
15387 {
15388 asection *s;
15389 bfd_boolean dyn;
ba93b8ac
DJ		 15390 int tls_type = elf32_arm_hash_entry (h)->tls_type;
15391 int indx;
5e681ec4
PB		 15392
15393 /* Make sure this symbol is output as a dynamic symbol.
15394 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 15395 if (h->dynindx == -1 && !h->forced_local
15396 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 15397 {
c152c796 15398 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15399 return FALSE;
15400 }
15401
e5a52504
MM		 15402 if (!htab->symbian_p)
15403 {
362d30a1 15404 s = htab->root.sgot;
e5a52504 15405 h->got.offset = s->size;
ba93b8ac
DJ		 15406
15407 if (tls_type == GOT_UNKNOWN)
15408 abort ();
15409
15410 if (tls_type == GOT_NORMAL)
15411 /* Non-TLS symbols need one GOT slot. */
15412 s->size += 4;
15413 else
15414 {
99059e56
RM		 15415 if (tls_type & GOT_TLS_GDESC)
15416 {
0855e32b 15417 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 15418 eh->tlsdesc_got
0855e32b
NS		 15419 = (htab->root.sgotplt->size
15420 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 15421 htab->root.sgotplt->size += 8;
15422 h->got.offset = (bfd_vma) -2;
34e77a92 15423 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15424 reloc in the middle of .got.plt. */
99059e56
RM		 15425 htab->num_tls_desc++;
15426 }
0855e32b 15427
ba93b8ac 15428 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 15429 {
15430 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
15431 the symbol is both GD and GDESC, got.offset may
15432 have been overwritten. */
15433 h->got.offset = s->size;
15434 s->size += 8;
15435 }
15436
ba93b8ac
DJ		 15437 if (tls_type & GOT_TLS_IE)
15438 /* R_ARM_TLS_IE32 needs one GOT slot. */
15439 s->size += 4;
15440 }
15441
e5a52504 15442 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 15443
15444 indx = 0;
0e1862bb
L		 15445 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
15446 bfd_link_pic (info),
15447 h)
15448 && (!bfd_link_pic (info)
ba93b8ac
DJ		 15449 || !SYMBOL_REFERENCES_LOCAL (info, h)))
15450 indx = h->dynindx;
15451
15452 if (tls_type != GOT_NORMAL
0e1862bb 15453 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 15454 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15455 || h->root.type != bfd_link_hash_undefweak))
15456 {
15457 if (tls_type & GOT_TLS_IE)
47beaa6a 15458 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 15459
15460 if (tls_type & GOT_TLS_GD)
47beaa6a 15461 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15462
b38cadfb 15463 if (tls_type & GOT_TLS_GDESC)
0855e32b 15464 {
47beaa6a 15465 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 15466 /* GDESC needs a trampoline to jump to. */
15467 htab->tls_trampoline = -1;
15468 }
15469
15470 /* Only GD needs it. GDESC just emits one relocation per
15471 2 entries. */
b38cadfb 15472 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 15473 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15474 }
6f820c85 15475 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 15476 {
15477 if (htab->root.dynamic_sections_created)
15478 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
15479 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
15480 }
34e77a92
RS		 15481 else if (h->type == STT_GNU_IFUNC
15482 && eh->plt.noncall_refcount == 0)
15483 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
15484 they all resolve dynamically instead. Reserve room for the
15485 GOT entry's R_ARM_IRELATIVE relocation. */
15486 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 15487 else if (bfd_link_pic (info)
15488 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15489 || h->root.type != bfd_link_hash_undefweak))
b436d854 15490 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 15491 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 15492 }
5e681ec4
PB		 15493 }
15494 else
15495 h->got.offset = (bfd_vma) -1;
15496
a4fd1a8e
PB		 15497 /* Allocate stubs for exported Thumb functions on v4t. */
15498 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 15499 && h->def_regular
39d911fc 15500 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 15501 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
15502 {
15503 struct elf_link_hash_entry * th;
15504 struct bfd_link_hash_entry * bh;
15505 struct elf_link_hash_entry * myh;
15506 char name[1024];
15507 asection *s;
15508 bh = NULL;
15509 /* Create a new symbol to regist the real location of the function. */
15510 s = h->root.u.def.section;
906e58ca 15511 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 15512 _bfd_generic_link_add_one_symbol (info, s->owner,
15513 name, BSF_GLOBAL, s,
15514 h->root.u.def.value,
15515 NULL, TRUE, FALSE, &bh);
15516
15517 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 15518 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 15519 myh->forced_local = 1;
39d911fc 15520 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 15521 eh->export_glue = myh;
15522 th = record_arm_to_thumb_glue (info, h);
15523 /* Point the symbol at the stub. */
15524 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 15525 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 15526 h->root.u.def.section = th->root.u.def.section;
15527 h->root.u.def.value = th->root.u.def.value & ~1;
15528 }
15529
0bdcacaf 15530 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 15531 return TRUE;
15532
15533 /* In the shared -Bsymbolic case, discard space allocated for
15534 dynamic pc-relative relocs against symbols which turn out to be
15535 defined in regular objects. For the normal shared case, discard
15536 space for pc-relative relocs that have become local due to symbol
15537 visibility changes. */
15538
0e1862bb 15539 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 15540 {
469a3493
RM		 15541 /* Relocs that use pc_count are PC-relative forms, which will appear
15542 on something like ".long foo - ." or "movw REG, foo - .". We want
15543 calls to protected symbols to resolve directly to the function
15544 rather than going via the plt. If people want function pointer
15545 comparisons to work as expected then they should avoid writing
15546 assembly like ".long foo - .". */
ba93b8ac
DJ		 15547 if (SYMBOL_CALLS_LOCAL (info, h))
15548 {
0bdcacaf 15549 struct elf_dyn_relocs **pp;
ba93b8ac 15550
0bdcacaf 15551 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 15552 {
15553 p->count -= p->pc_count;
15554 p->pc_count = 0;
15555 if (p->count == 0)
15556 *pp = p->next;
15557 else
15558 pp = &p->next;
15559 }
15560 }
15561
4dfe6ac6 15562 if (htab->vxworks_p)
3348747a 15563 {
0bdcacaf 15564 struct elf_dyn_relocs **pp;
3348747a 15565
0bdcacaf 15566 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 15567 {
0bdcacaf 15568 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 15569 *pp = p->next;
15570 else
15571 pp = &p->next;
15572 }
15573 }
15574
ba93b8ac 15575 /* Also discard relocs on undefined weak syms with non-default
99059e56 15576 visibility. */
0bdcacaf 15577 if (eh->dyn_relocs != NULL
5e681ec4 15578 && h->root.type == bfd_link_hash_undefweak)
22d606e9 15579 {
95b03e4a
L		 15580 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
15581 || UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
0bdcacaf 15582 eh->dyn_relocs = NULL;
22d606e9
AM		 15583
15584 /* Make sure undefined weak symbols are output as a dynamic
15585 symbol in PIEs. */
15586 else if (h->dynindx == -1
15587 && !h->forced_local)
15588 {
15589 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15590 return FALSE;
15591 }
15592 }
15593
67687978
PB		 15594 else if (htab->root.is_relocatable_executable && h->dynindx == -1
15595 && h->root.type == bfd_link_hash_new)
15596 {
15597 /* Output absolute symbols so that we can create relocations
15598 against them. For normal symbols we output a relocation
15599 against the section that contains them. */
15600 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15601 return FALSE;
15602 }
15603
5e681ec4
PB		 15604 }
15605 else
15606 {
15607 /* For the non-shared case, discard space for relocs against
15608 symbols which turn out to need copy relocs or are not
15609 dynamic. */
15610
f5385ebf
AM		 15611 if (!h->non_got_ref
15612 && ((h->def_dynamic
15613 && !h->def_regular)
5e681ec4
PB		 15614 || (htab->root.dynamic_sections_created
15615 && (h->root.type == bfd_link_hash_undefweak
15616 || h->root.type == bfd_link_hash_undefined))))
15617 {
15618 /* Make sure this symbol is output as a dynamic symbol.
15619 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 15620 if (h->dynindx == -1 && !h->forced_local
15621 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 15622 {
c152c796 15623 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15624 return FALSE;
15625 }
15626
15627 /* If that succeeded, we know we'll be keeping all the
15628 relocs. */
15629 if (h->dynindx != -1)
15630 goto keep;
15631 }
15632
0bdcacaf 15633 eh->dyn_relocs = NULL;
5e681ec4
PB		 15634
15635 keep: ;
15636 }
15637
15638 /* Finally, allocate space. */
0bdcacaf 15639 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 15640 {
0bdcacaf 15641 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 15642 if (h->type == STT_GNU_IFUNC
15643 && eh->plt.noncall_refcount == 0
15644 && SYMBOL_REFERENCES_LOCAL (info, h))
15645 elf32_arm_allocate_irelocs (info, sreloc, p->count);
15646 else
15647 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 15648 }
15649
15650 return TRUE;
15651}
15652
63c1f59d
AM		 15653/* Set DF_TEXTREL if we find any dynamic relocs that apply to
15654 read-only sections. */
08d1f311
DJ		 15655
15656static bfd_boolean
63c1f59d 15657maybe_set_textrel (struct elf_link_hash_entry *h, void *info_p)
08d1f311 15658{
63c1f59d 15659 asection *sec;
08d1f311 15660
63c1f59d
AM		 15661 if (h->root.type == bfd_link_hash_indirect)
15662 return TRUE;
08d1f311 15663
63c1f59d
AM		 15664 sec = readonly_dynrelocs (h);
15665 if (sec != NULL)
15666 {
15667 struct bfd_link_info *info = (struct bfd_link_info *) info_p;
08d1f311 15668
63c1f59d
AM		 15669 info->flags |= DF_TEXTREL;
15670 info->callbacks->minfo
c1c8c1ef 15671 (_("%pB: dynamic relocation against `%pT' in read-only section `%pA'\n"),
63c1f59d 15672 sec->owner, h->root.root.string, sec);
08d1f311 15673
63c1f59d
AM		 15674 /* Not an error, just cut short the traversal. */
15675 return FALSE;
08d1f311
DJ		 15676 }
15677 return TRUE;
15678}
15679
d504ffc8
DJ		 15680void
15681bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
15682 int byteswap_code)
15683{
15684 struct elf32_arm_link_hash_table *globals;
15685
15686 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15687 if (globals == NULL)
15688 return;
15689
d504ffc8
DJ		 15690 globals->byteswap_code = byteswap_code;
15691}
15692
252b5132
RH		 15693/* Set the sizes of the dynamic sections. */
15694
b34976b6 15695static bfd_boolean
57e8b36a
NC		 15696elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
15697 struct bfd_link_info * info)
252b5132
RH		 15698{
15699 bfd * dynobj;
15700 asection * s;
b34976b6
AM		 15701 bfd_boolean plt;
15702 bfd_boolean relocs;
5e681ec4
PB		 15703 bfd *ibfd;
15704 struct elf32_arm_link_hash_table *htab;
252b5132 15705
5e681ec4 15706 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15707 if (htab == NULL)
15708 return FALSE;
15709
252b5132
RH		 15710 dynobj = elf_hash_table (info)->dynobj;
15711 BFD_ASSERT (dynobj != NULL);
39b41c9c 15712 check_use_blx (htab);
252b5132
RH		 15713
15714 if (elf_hash_table (info)->dynamic_sections_created)
15715 {
15716 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 15717 if (bfd_link_executable (info) && !info->nointerp)
252b5132 15718 {
3d4d4302 15719 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 15720 BFD_ASSERT (s != NULL);
eea6121a 15721 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 15722 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
15723 }
15724 }
5e681ec4
PB		 15725
15726 /* Set up .got offsets for local syms, and space for local dynamic
15727 relocs. */
c72f2fb2 15728 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 15729 {
5e681ec4
PB		 15730 bfd_signed_vma *local_got;
15731 bfd_signed_vma *end_local_got;
34e77a92 15732 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 15733 char *local_tls_type;
0855e32b 15734 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 15735 bfd_size_type locsymcount;
15736 Elf_Internal_Shdr *symtab_hdr;
15737 asection *srel;
4dfe6ac6 15738 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 15739 unsigned int symndx;
5e681ec4 15740
0ffa91dd 15741 if (! is_arm_elf (ibfd))
5e681ec4
PB		 15742 continue;
15743
15744 for (s = ibfd->sections; s != NULL; s = s->next)
15745 {
0bdcacaf 15746 struct elf_dyn_relocs *p;
5e681ec4 15747
0bdcacaf 15748 for (p = (struct elf_dyn_relocs *)
99059e56 15749 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 15750 {
0bdcacaf
RS		 15751 if (!bfd_is_abs_section (p->sec)
15752 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 15753 {
15754 /* Input section has been discarded, either because
15755 it is a copy of a linkonce section or due to
15756 linker script /DISCARD/, so we'll be discarding
15757 the relocs too. */
15758 }
3348747a 15759 else if (is_vxworks
0bdcacaf 15760 && strcmp (p->sec->output_section->name,
3348747a
NS		 15761 ".tls_vars") == 0)
15762 {
15763 /* Relocations in vxworks .tls_vars sections are
15764 handled specially by the loader. */
15765 }
5e681ec4
PB		 15766 else if (p->count != 0)
15767 {
0bdcacaf 15768 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 15769 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 15770 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 15771 info->flags |= DF_TEXTREL;
15772 }
15773 }
15774 }
15775
15776 local_got = elf_local_got_refcounts (ibfd);
15777 if (!local_got)
15778 continue;
15779
0ffa91dd 15780 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 15781 locsymcount = symtab_hdr->sh_info;
15782 end_local_got = local_got + locsymcount;
34e77a92 15783 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 15784 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 15785 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 15786 symndx = 0;
362d30a1
RS		 15787 s = htab->root.sgot;
15788 srel = htab->root.srelgot;
0855e32b 15789 for (; local_got < end_local_got;
34e77a92
RS		 15790 ++local_got, ++local_iplt_ptr, ++local_tls_type,
15791 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 15792 {
0855e32b 15793 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 15794 local_iplt = *local_iplt_ptr;
15795 if (local_iplt != NULL)
15796 {
15797 struct elf_dyn_relocs *p;
15798
15799 if (local_iplt->root.refcount > 0)
15800 {
15801 elf32_arm_allocate_plt_entry (info, TRUE,
15802 &local_iplt->root,
15803 &local_iplt->arm);
15804 if (local_iplt->arm.noncall_refcount == 0)
15805 /* All references to the PLT are calls, so all
15806 non-call references can resolve directly to the
15807 run-time target. This means that the .got entry
15808 would be the same as the .igot.plt entry, so there's
15809 no point creating both. */
15810 *local_got = 0;
15811 }
15812 else
15813 {
15814 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
15815 local_iplt->root.offset = (bfd_vma) -1;
15816 }
15817
15818 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
15819 {
15820 asection *psrel;
15821
15822 psrel = elf_section_data (p->sec)->sreloc;
15823 if (local_iplt->arm.noncall_refcount == 0)
15824 elf32_arm_allocate_irelocs (info, psrel, p->count);
15825 else
15826 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
15827 }
15828 }
5e681ec4
PB		 15829 if (*local_got > 0)
15830 {
34e77a92
RS		 15831 Elf_Internal_Sym *isym;
15832
eea6121a 15833 *local_got = s->size;
ba93b8ac
DJ		 15834 if (*local_tls_type & GOT_TLS_GD)
15835 /* TLS_GD relocs need an 8-byte structure in the GOT. */
15836 s->size += 8;
0855e32b
NS		 15837 if (*local_tls_type & GOT_TLS_GDESC)
15838 {
15839 *local_tlsdesc_gotent = htab->root.sgotplt->size
15840 - elf32_arm_compute_jump_table_size (htab);
15841 htab->root.sgotplt->size += 8;
15842 *local_got = (bfd_vma) -2;
34e77a92 15843 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15844 reloc in the middle of .got.plt. */
99059e56 15845 htab->num_tls_desc++;
0855e32b 15846 }
ba93b8ac
DJ		 15847 if (*local_tls_type & GOT_TLS_IE)
15848 s->size += 4;
ba93b8ac 15849
0855e32b
NS		 15850 if (*local_tls_type & GOT_NORMAL)
15851 {
15852 /* If the symbol is both GD and GDESC, *local_got
15853 may have been overwritten. */
15854 *local_got = s->size;
15855 s->size += 4;
15856 }
15857
34e77a92
RS		 15858 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
15859 if (isym == NULL)
15860 return FALSE;
15861
15862 /* If all references to an STT_GNU_IFUNC PLT are calls,
15863 then all non-call references, including this GOT entry,
15864 resolve directly to the run-time target. */
15865 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
15866 && (local_iplt == NULL
15867 || local_iplt->arm.noncall_refcount == 0))
15868 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 15869 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 15870 {
0e1862bb 15871 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 15872 || *local_tls_type & GOT_TLS_GD)
15873 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 15874
0e1862bb 15875 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 15876 {
15877 elf32_arm_allocate_dynrelocs (info,
15878 htab->root.srelplt, 1);
15879 htab->tls_trampoline = -1;
15880 }
0855e32b 15881 }
5e681ec4
PB		 15882 }
15883 else
15884 *local_got = (bfd_vma) -1;
15885 }
252b5132
RH		 15886 }
15887
ba93b8ac
DJ		 15888 if (htab->tls_ldm_got.refcount > 0)
15889 {
15890 /* Allocate two GOT entries and one dynamic relocation (if necessary)
15891 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 15892 htab->tls_ldm_got.offset = htab->root.sgot->size;
15893 htab->root.sgot->size += 8;
0e1862bb 15894 if (bfd_link_pic (info))
47beaa6a 15895 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 15896 }
15897 else
15898 htab->tls_ldm_got.offset = -1;
15899
5e681ec4
PB		 15900 /* Allocate global sym .plt and .got entries, and space for global
15901 sym dynamic relocs. */
47beaa6a 15902 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 15903
d504ffc8 15904 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 15905 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 15906 {
0ffa91dd 15907 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 15908 continue;
15909
c7b8f16e
JB		 15910 /* Initialise mapping tables for code/data. */
15911 bfd_elf32_arm_init_maps (ibfd);
906e58ca 15912
c7b8f16e 15913 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 15914 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
15915 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
90b6238f 15916 _bfd_error_handler (_("errors encountered processing file %pB"), ibfd);
c7b8f16e 15917 }
d504ffc8 15918
3e6b1042
DJ		 15919 /* Allocate space for the glue sections now that we've sized them. */
15920 bfd_elf32_arm_allocate_interworking_sections (info);
15921
0855e32b
NS		 15922 /* For every jump slot reserved in the sgotplt, reloc_count is
15923 incremented. However, when we reserve space for TLS descriptors,
15924 it's not incremented, so in order to compute the space reserved
15925 for them, it suffices to multiply the reloc count by the jump
15926 slot size. */
15927 if (htab->root.srelplt)
15928 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
15929
15930 if (htab->tls_trampoline)
15931 {
15932 if (htab->root.splt->size == 0)
15933 htab->root.splt->size += htab->plt_header_size;
b38cadfb 15934
0855e32b
NS		 15935 htab->tls_trampoline = htab->root.splt->size;
15936 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 15937
0855e32b 15938 /* If we're not using lazy TLS relocations, don't generate the
99059e56 15939 PLT and GOT entries they require. */
0855e32b
NS		 15940 if (!(info->flags & DF_BIND_NOW))
15941 {
15942 htab->dt_tlsdesc_got = htab->root.sgot->size;
15943 htab->root.sgot->size += 4;
15944
15945 htab->dt_tlsdesc_plt = htab->root.splt->size;
15946 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
15947 }
15948 }
15949
252b5132
RH		 15950 /* The check_relocs and adjust_dynamic_symbol entry points have
15951 determined the sizes of the various dynamic sections. Allocate
15952 memory for them. */
b34976b6
AM		 15953 plt = FALSE;
15954 relocs = FALSE;
252b5132
RH		 15955 for (s = dynobj->sections; s != NULL; s = s->next)
15956 {
15957 const char * name;
252b5132
RH		 15958
15959 if ((s->flags & SEC_LINKER_CREATED) == 0)
15960 continue;
15961
15962 /* It's OK to base decisions on the section name, because none
15963 of the dynobj section names depend upon the input files. */
15964 name = bfd_get_section_name (dynobj, s);
15965
34e77a92 15966 if (s == htab->root.splt)
252b5132 15967 {
c456f082
AM		 15968 /* Remember whether there is a PLT. */
15969 plt = s->size != 0;
252b5132 15970 }
0112cd26 15971 else if (CONST_STRNEQ (name, ".rel"))
252b5132 15972 {
c456f082 15973 if (s->size != 0)
252b5132 15974 {
252b5132 15975 /* Remember whether there are any reloc sections other
00a97672 15976 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 15977 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 15978 relocs = TRUE;
252b5132
RH		 15979
15980 /* We use the reloc_count field as a counter if we need
15981 to copy relocs into the output file. */
15982 s->reloc_count = 0;
15983 }
15984 }
34e77a92
RS		 15985 else if (s != htab->root.sgot
15986 && s != htab->root.sgotplt
15987 && s != htab->root.iplt
15988 && s != htab->root.igotplt
5474d94f
AM		 15989 && s != htab->root.sdynbss
15990 && s != htab->root.sdynrelro)
252b5132
RH		 15991 {
15992 /* It's not one of our sections, so don't allocate space. */
15993 continue;
15994 }
15995
c456f082 15996 if (s->size == 0)
252b5132 15997 {
c456f082 15998 /* If we don't need this section, strip it from the
00a97672
RS		 15999 output file. This is mostly to handle .rel(a).bss and
16000 .rel(a).plt. We must create both sections in
c456f082
AM		 16001 create_dynamic_sections, because they must be created
16002 before the linker maps input sections to output
16003 sections. The linker does that before
16004 adjust_dynamic_symbol is called, and it is that
16005 function which decides whether anything needs to go
16006 into these sections. */
8423293d 16007 s->flags |= SEC_EXCLUDE;
252b5132
RH		 16008 continue;
16009 }
16010
c456f082
AM		 16011 if ((s->flags & SEC_HAS_CONTENTS) == 0)
16012 continue;
16013
252b5132 16014 /* Allocate memory for the section contents. */
21d799b5 16015 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 16016 if (s->contents == NULL)
b34976b6 16017 return FALSE;
252b5132
RH		 16018 }
16019
16020 if (elf_hash_table (info)->dynamic_sections_created)
16021 {
16022 /* Add some entries to the .dynamic section. We fill in the
16023 values later, in elf32_arm_finish_dynamic_sections, but we
16024 must add the entries now so that we get the correct size for
16025 the .dynamic section. The DT_DEBUG entry is filled in by the
16026 dynamic linker and used by the debugger. */
dc810e39 16027#define add_dynamic_entry(TAG, VAL) \
5a580b3a 16028 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 16029
0e1862bb 16030 if (bfd_link_executable (info))
252b5132 16031 {
dc810e39 16032 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 16033 return FALSE;
252b5132
RH		 16034 }
16035
16036 if (plt)
16037 {
dc810e39
AM		 16038 if ( !add_dynamic_entry (DT_PLTGOT, 0)
16039 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 16040 || !add_dynamic_entry (DT_PLTREL,
16041 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 16042 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 16043 return FALSE;
0855e32b 16044
5025eb7c
AO		 16045 if (htab->dt_tlsdesc_plt
16046 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
16047 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 16048 return FALSE;
252b5132
RH		 16049 }
16050
16051 if (relocs)
16052 {
00a97672
RS		 16053 if (htab->use_rel)
16054 {
16055 if (!add_dynamic_entry (DT_REL, 0)
16056 || !add_dynamic_entry (DT_RELSZ, 0)
16057 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
16058 return FALSE;
16059 }
16060 else
16061 {
16062 if (!add_dynamic_entry (DT_RELA, 0)
16063 || !add_dynamic_entry (DT_RELASZ, 0)
16064 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
16065 return FALSE;
16066 }
252b5132
RH		 16067 }
16068
08d1f311
DJ		 16069 /* If any dynamic relocs apply to a read-only section,
16070 then we need a DT_TEXTREL entry. */
16071 if ((info->flags & DF_TEXTREL) == 0)
63c1f59d 16072 elf_link_hash_traverse (&htab->root, maybe_set_textrel, info);
08d1f311 16073
99e4ae17 16074 if ((info->flags & DF_TEXTREL) != 0)
252b5132 16075 {
dc810e39 16076 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 16077 return FALSE;
252b5132 16078 }
7a2b07ff
NS		 16079 if (htab->vxworks_p
16080 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
16081 return FALSE;
252b5132 16082 }
8532796c 16083#undef add_dynamic_entry
252b5132 16084
b34976b6 16085 return TRUE;
252b5132
RH		 16086}
16087
0855e32b
NS		 16088/* Size sections even though they're not dynamic. We use it to setup
16089 _TLS_MODULE_BASE_, if needed. */
16090
16091static bfd_boolean
16092elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 16093 struct bfd_link_info *info)
0855e32b
NS		 16094{
16095 asection *tls_sec;
16096
0e1862bb 16097 if (bfd_link_relocatable (info))
0855e32b
NS		 16098 return TRUE;
16099
16100 tls_sec = elf_hash_table (info)->tls_sec;
16101
16102 if (tls_sec)
16103 {
16104 struct elf_link_hash_entry *tlsbase;
16105
16106 tlsbase = elf_link_hash_lookup
16107 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
16108
16109 if (tlsbase)
99059e56
RM		 16110 {
16111 struct bfd_link_hash_entry *bh = NULL;
0855e32b 16112 const struct elf_backend_data *bed
99059e56 16113 = get_elf_backend_data (output_bfd);
0855e32b 16114
99059e56 16115 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 16116 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
16117 tls_sec, 0, NULL, FALSE,
16118 bed->collect, &bh)))
16119 return FALSE;
b38cadfb 16120
99059e56
RM		 16121 tlsbase->type = STT_TLS;
16122 tlsbase = (struct elf_link_hash_entry *)bh;
16123 tlsbase->def_regular = 1;
16124 tlsbase->other = STV_HIDDEN;
16125 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 16126 }
16127 }
16128 return TRUE;
16129}
16130
252b5132
RH		 16131/* Finish up dynamic symbol handling. We set the contents of various
16132 dynamic sections here. */
16133
b34976b6 16134static bfd_boolean
906e58ca
NC		 16135elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
16136 struct bfd_link_info * info,
16137 struct elf_link_hash_entry * h,
16138 Elf_Internal_Sym * sym)
252b5132 16139{
e5a52504 16140 struct elf32_arm_link_hash_table *htab;
b7693d02 16141 struct elf32_arm_link_hash_entry *eh;
252b5132 16142
e5a52504 16143 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16144 if (htab == NULL)
16145 return FALSE;
16146
b7693d02 16147 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 16148
16149 if (h->plt.offset != (bfd_vma) -1)
16150 {
34e77a92 16151 if (!eh->is_iplt)
e5a52504 16152 {
34e77a92 16153 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 16154 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
16155 h->dynindx, 0))
16156 return FALSE;
e5a52504 16157 }
57e8b36a 16158
f5385ebf 16159 if (!h->def_regular)
252b5132
RH		 16160 {
16161 /* Mark the symbol as undefined, rather than as defined in
3a635617 16162 the .plt section. */
252b5132 16163 sym->st_shndx = SHN_UNDEF;
3a635617 16164 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 16165 Otherwise, the PLT entry would provide a definition for
16166 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 16167 and so the symbol would never be NULL. Leave the value if
16168 there were any relocations where pointer equality matters
16169 (this is a clue for the dynamic linker, to make function
16170 pointer comparisons work between an application and shared
16171 library). */
97323ad1 16172 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 16173 sym->st_value = 0;
252b5132 16174 }
34e77a92
RS		 16175 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
16176 {
16177 /* At least one non-call relocation references this .iplt entry,
16178 so the .iplt entry is the function's canonical address. */
16179 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 16180 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 16181 sym->st_shndx = (_bfd_elf_section_from_bfd_section
16182 (output_bfd, htab->root.iplt->output_section));
16183 sym->st_value = (h->plt.offset
16184 + htab->root.iplt->output_section->vma
16185 + htab->root.iplt->output_offset);
16186 }
252b5132
RH		 16187 }
16188
f5385ebf 16189 if (h->needs_copy)
252b5132
RH		 16190 {
16191 asection * s;
947216bf 16192 Elf_Internal_Rela rel;
252b5132
RH		 16193
16194 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 16195 BFD_ASSERT (h->dynindx != -1
16196 && (h->root.type == bfd_link_hash_defined
16197 || h->root.type == bfd_link_hash_defweak));
16198
00a97672 16199 rel.r_addend = 0;
252b5132
RH		 16200 rel.r_offset = (h->root.u.def.value
16201 + h->root.u.def.section->output_section->vma
16202 + h->root.u.def.section->output_offset);
16203 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 16204 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 16205 s = htab->root.sreldynrelro;
16206 else
16207 s = htab->root.srelbss;
47beaa6a 16208 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 16209 }
16210
00a97672
RS		 16211 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
16212 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
16213 to the ".got" section. */
9637f6ef 16214 if (h == htab->root.hdynamic
00a97672 16215 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 16216 sym->st_shndx = SHN_ABS;
16217
b34976b6 16218 return TRUE;
252b5132
RH		 16219}
16220
0855e32b
NS		 16221static void
16222arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16223 void *contents,
16224 const unsigned long *template, unsigned count)
16225{
16226 unsigned ix;
b38cadfb 16227
0855e32b
NS		 16228 for (ix = 0; ix != count; ix++)
16229 {
16230 unsigned long insn = template[ix];
16231
16232 /* Emit mov pc,rx if bx is not permitted. */
16233 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
16234 insn = (insn & 0xf000000f) | 0x01a0f000;
16235 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
16236 }
16237}
16238
99059e56
RM		 16239/* Install the special first PLT entry for elf32-arm-nacl. Unlike
16240 other variants, NaCl needs this entry in a static executable's
16241 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
16242 zero. For .iplt really only the last bundle is useful, and .iplt
16243 could have a shorter first entry, with each individual PLT entry's
16244 relative branch calculated differently so it targets the last
16245 bundle instead of the instruction before it (labelled .Lplt_tail
16246 above). But it's simpler to keep the size and layout of PLT0
16247 consistent with the dynamic case, at the cost of some dead code at
16248 the start of .iplt and the one dead store to the stack at the start
16249 of .Lplt_tail. */
16250static void
16251arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16252 asection *plt, bfd_vma got_displacement)
16253{
16254 unsigned int i;
16255
16256 put_arm_insn (htab, output_bfd,
16257 elf32_arm_nacl_plt0_entry[0]
16258 | arm_movw_immediate (got_displacement),
16259 plt->contents + 0);
16260 put_arm_insn (htab, output_bfd,
16261 elf32_arm_nacl_plt0_entry[1]
16262 | arm_movt_immediate (got_displacement),
16263 plt->contents + 4);
16264
16265 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
16266 put_arm_insn (htab, output_bfd,
16267 elf32_arm_nacl_plt0_entry[i],
16268 plt->contents + (i * 4));
16269}
16270
252b5132
RH		 16271/* Finish up the dynamic sections. */
16272
b34976b6 16273static bfd_boolean
57e8b36a 16274elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 16275{
16276 bfd * dynobj;
16277 asection * sgot;
16278 asection * sdyn;
4dfe6ac6
NC		 16279 struct elf32_arm_link_hash_table *htab;
16280
16281 htab = elf32_arm_hash_table (info);
16282 if (htab == NULL)
16283 return FALSE;
252b5132
RH		 16284
16285 dynobj = elf_hash_table (info)->dynobj;
16286
362d30a1 16287 sgot = htab->root.sgotplt;
894891db
NC		 16288 /* A broken linker script might have discarded the dynamic sections.
16289 Catch this here so that we do not seg-fault later on. */
16290 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
16291 return FALSE;
3d4d4302 16292 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 16293
16294 if (elf_hash_table (info)->dynamic_sections_created)
16295 {
16296 asection *splt;
16297 Elf32_External_Dyn *dyncon, *dynconend;
16298
362d30a1 16299 splt = htab->root.splt;
24a1ba0f 16300 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 16301 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 16302
16303 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 16304 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 16305
252b5132
RH		 16306 for (; dyncon < dynconend; dyncon++)
16307 {
16308 Elf_Internal_Dyn dyn;
16309 const char * name;
16310 asection * s;
16311
16312 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
16313
16314 switch (dyn.d_tag)
16315 {
229fcec5
MM		 16316 unsigned int type;
16317
252b5132 16318 default:
7a2b07ff
NS		 16319 if (htab->vxworks_p
16320 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
16321 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 16322 break;
16323
229fcec5
MM		 16324 case DT_HASH:
16325 name = ".hash";
16326 goto get_vma_if_bpabi;
16327 case DT_STRTAB:
16328 name = ".dynstr";
16329 goto get_vma_if_bpabi;
16330 case DT_SYMTAB:
16331 name = ".dynsym";
16332 goto get_vma_if_bpabi;
c0042f5d
MM		 16333 case DT_VERSYM:
16334 name = ".gnu.version";
16335 goto get_vma_if_bpabi;
16336 case DT_VERDEF:
16337 name = ".gnu.version_d";
16338 goto get_vma_if_bpabi;
16339 case DT_VERNEED:
16340 name = ".gnu.version_r";
16341 goto get_vma_if_bpabi;
16342
252b5132 16343 case DT_PLTGOT:
4ade44b7 16344 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 16345 goto get_vma;
16346 case DT_JMPREL:
00a97672 16347 name = RELOC_SECTION (htab, ".plt");
252b5132 16348 get_vma:
4ade44b7 16349 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 16350 if (s == NULL)
16351 {
4eca0228 16352 _bfd_error_handler
4ade44b7 16353 (_("could not find section %s"), name);
05456594
NC		 16354 bfd_set_error (bfd_error_invalid_operation);
16355 return FALSE;
16356 }
229fcec5 16357 if (!htab->symbian_p)
4ade44b7 16358 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 16359 else
16360 /* In the BPABI, tags in the PT_DYNAMIC section point
16361 at the file offset, not the memory address, for the
16362 convenience of the post linker. */
4ade44b7 16363 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 16364 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16365 break;
16366
229fcec5
MM		 16367 get_vma_if_bpabi:
16368 if (htab->symbian_p)
16369 goto get_vma;
16370 break;
16371
252b5132 16372 case DT_PLTRELSZ:
362d30a1 16373 s = htab->root.srelplt;
252b5132 16374 BFD_ASSERT (s != NULL);
eea6121a 16375 dyn.d_un.d_val = s->size;
252b5132
RH		 16376 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16377 break;
906e58ca 16378
252b5132 16379 case DT_RELSZ:
00a97672 16380 case DT_RELASZ:
229fcec5
MM		 16381 case DT_REL:
16382 case DT_RELA:
229fcec5
MM		 16383 /* In the BPABI, the DT_REL tag must point at the file
16384 offset, not the VMA, of the first relocation
16385 section. So, we use code similar to that in
16386 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 16387 relocation section, since relocation sections are
16388 never allocated under the BPABI. PLT relocs are also
16389 included. */
229fcec5
MM		 16390 if (htab->symbian_p)
16391 {
16392 unsigned int i;
16393 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
16394 ? SHT_REL : SHT_RELA);
16395 dyn.d_un.d_val = 0;
16396 for (i = 1; i < elf_numsections (output_bfd); i++)
16397 {
906e58ca 16398 Elf_Internal_Shdr *hdr
229fcec5
MM		 16399 = elf_elfsections (output_bfd)[i];
16400 if (hdr->sh_type == type)
16401 {
906e58ca 16402 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 16403 || dyn.d_tag == DT_RELASZ)
16404 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 16405 else if ((ufile_ptr) hdr->sh_offset
16406 <= dyn.d_un.d_val - 1)
229fcec5
MM		 16407 dyn.d_un.d_val = hdr->sh_offset;
16408 }
16409 }
16410 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16411 }
252b5132 16412 break;
88f7bcd5 16413
0855e32b 16414 case DT_TLSDESC_PLT:
99059e56 16415 s = htab->root.splt;
0855e32b
NS		 16416 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
16417 + htab->dt_tlsdesc_plt);
16418 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16419 break;
16420
16421 case DT_TLSDESC_GOT:
99059e56 16422 s = htab->root.sgot;
0855e32b 16423 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 16424 + htab->dt_tlsdesc_got);
0855e32b
NS		 16425 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16426 break;
16427
88f7bcd5
NC		 16428 /* Set the bottom bit of DT_INIT/FINI if the
16429 corresponding function is Thumb. */
16430 case DT_INIT:
16431 name = info->init_function;
16432 goto get_sym;
16433 case DT_FINI:
16434 name = info->fini_function;
16435 get_sym:
16436 /* If it wasn't set by elf_bfd_final_link
4cc11e76 16437 then there is nothing to adjust. */
88f7bcd5
NC		 16438 if (dyn.d_un.d_val != 0)
16439 {
16440 struct elf_link_hash_entry * eh;
16441
16442 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 16443 FALSE, FALSE, TRUE);
39d911fc
TP		 16444 if (eh != NULL
16445 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
16446 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 16447 {
16448 dyn.d_un.d_val |= 1;
b34976b6 16449 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 16450 }
16451 }
16452 break;
252b5132
RH		 16453 }
16454 }
16455
24a1ba0f 16456 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 16457 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 16458 {
00a97672
RS		 16459 const bfd_vma *plt0_entry;
16460 bfd_vma got_address, plt_address, got_displacement;
16461
16462 /* Calculate the addresses of the GOT and PLT. */
16463 got_address = sgot->output_section->vma + sgot->output_offset;
16464 plt_address = splt->output_section->vma + splt->output_offset;
16465
16466 if (htab->vxworks_p)
16467 {
16468 /* The VxWorks GOT is relocated by the dynamic linker.
16469 Therefore, we must emit relocations rather than simply
16470 computing the values now. */
16471 Elf_Internal_Rela rel;
16472
16473 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 16474 put_arm_insn (htab, output_bfd, plt0_entry[0],
16475 splt->contents + 0);
16476 put_arm_insn (htab, output_bfd, plt0_entry[1],
16477 splt->contents + 4);
16478 put_arm_insn (htab, output_bfd, plt0_entry[2],
16479 splt->contents + 8);
00a97672
RS		 16480 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
16481
8029a119 16482 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 16483 rel.r_offset = plt_address + 12;
16484 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16485 rel.r_addend = 0;
16486 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
16487 htab->srelplt2->contents);
16488 }
b38cadfb 16489 else if (htab->nacl_p)
99059e56
RM		 16490 arm_nacl_put_plt0 (htab, output_bfd, splt,
16491 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 16492 else if (using_thumb_only (htab))
16493 {
16494 got_displacement = got_address - (plt_address + 12);
16495
16496 plt0_entry = elf32_thumb2_plt0_entry;
16497 put_arm_insn (htab, output_bfd, plt0_entry[0],
16498 splt->contents + 0);
16499 put_arm_insn (htab, output_bfd, plt0_entry[1],
16500 splt->contents + 4);
16501 put_arm_insn (htab, output_bfd, plt0_entry[2],
16502 splt->contents + 8);
16503
16504 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
16505 }
00a97672
RS		 16506 else
16507 {
16508 got_displacement = got_address - (plt_address + 16);
16509
16510 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 16511 put_arm_insn (htab, output_bfd, plt0_entry[0],
16512 splt->contents + 0);
16513 put_arm_insn (htab, output_bfd, plt0_entry[1],
16514 splt->contents + 4);
16515 put_arm_insn (htab, output_bfd, plt0_entry[2],
16516 splt->contents + 8);
16517 put_arm_insn (htab, output_bfd, plt0_entry[3],
16518 splt->contents + 12);
5e681ec4 16519
5e681ec4 16520#ifdef FOUR_WORD_PLT
00a97672
RS		 16521 /* The displacement value goes in the otherwise-unused
16522 last word of the second entry. */
16523 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 16524#else
00a97672 16525 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 16526#endif
00a97672 16527 }
f7a74f8c 16528 }
252b5132
RH		 16529
16530 /* UnixWare sets the entsize of .plt to 4, although that doesn't
16531 really seem like the right value. */
74541ad4
AM		 16532 if (splt->output_section->owner == output_bfd)
16533 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 16534
0855e32b
NS		 16535 if (htab->dt_tlsdesc_plt)
16536 {
16537 bfd_vma got_address
16538 = sgot->output_section->vma + sgot->output_offset;
16539 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
16540 + htab->root.sgot->output_offset);
16541 bfd_vma plt_address
16542 = splt->output_section->vma + splt->output_offset;
16543
b38cadfb 16544 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16545 splt->contents + htab->dt_tlsdesc_plt,
16546 dl_tlsdesc_lazy_trampoline, 6);
16547
16548 bfd_put_32 (output_bfd,
16549 gotplt_address + htab->dt_tlsdesc_got
16550 - (plt_address + htab->dt_tlsdesc_plt)
16551 - dl_tlsdesc_lazy_trampoline[6],
16552 splt->contents + htab->dt_tlsdesc_plt + 24);
16553 bfd_put_32 (output_bfd,
16554 got_address - (plt_address + htab->dt_tlsdesc_plt)
16555 - dl_tlsdesc_lazy_trampoline[7],
16556 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
16557 }
16558
16559 if (htab->tls_trampoline)
16560 {
b38cadfb 16561 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16562 splt->contents + htab->tls_trampoline,
16563 tls_trampoline, 3);
16564#ifdef FOUR_WORD_PLT
16565 bfd_put_32 (output_bfd, 0x00000000,
16566 splt->contents + htab->tls_trampoline + 12);
b38cadfb 16567#endif
0855e32b
NS		 16568 }
16569
0e1862bb
L		 16570 if (htab->vxworks_p
16571 && !bfd_link_pic (info)
16572 && htab->root.splt->size > 0)
00a97672
RS		 16573 {
16574 /* Correct the .rel(a).plt.unloaded relocations. They will have
16575 incorrect symbol indexes. */
16576 int num_plts;
eed62c48 16577 unsigned char *p;
00a97672 16578
362d30a1 16579 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 16580 / htab->plt_entry_size);
16581 p = htab->srelplt2->contents + RELOC_SIZE (htab);
16582
16583 for (; num_plts; num_plts--)
16584 {
16585 Elf_Internal_Rela rel;
16586
16587 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16588 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16589 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16590 p += RELOC_SIZE (htab);
16591
16592 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16593 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
16594 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16595 p += RELOC_SIZE (htab);
16596 }
16597 }
252b5132
RH		 16598 }
16599
99059e56
RM		 16600 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
16601 /* NaCl uses a special first entry in .iplt too. */
16602 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
16603
252b5132 16604 /* Fill in the first three entries in the global offset table. */
229fcec5 16605 if (sgot)
252b5132 16606 {
229fcec5
MM		 16607 if (sgot->size > 0)
16608 {
16609 if (sdyn == NULL)
16610 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
16611 else
16612 bfd_put_32 (output_bfd,
16613 sdyn->output_section->vma + sdyn->output_offset,
16614 sgot->contents);
16615 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
16616 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
16617 }
252b5132 16618
229fcec5
MM		 16619 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
16620 }
252b5132 16621
b34976b6 16622 return TRUE;
252b5132
RH		 16623}
16624
ba96a88f 16625static void
57e8b36a 16626elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 16627{
9b485d32 16628 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 16629 struct elf32_arm_link_hash_table *globals;
ac4c9b04 16630 struct elf_segment_map *m;
ba96a88f
NC		 16631
16632 i_ehdrp = elf_elfheader (abfd);
16633
94a3258f
PB		 16634 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
16635 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
16636 else
7394f108 16637 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 16638 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 16639
93204d3a
PB		 16640 if (link_info)
16641 {
16642 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 16643 if (globals != NULL && globals->byteswap_code)
93204d3a
PB		 16644 i_ehdrp->e_flags |= EF_ARM_BE8;
16645 }
3bfcb652
NC		 16646
16647 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
16648 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
16649 {
16650 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 16651 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 16652 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
16653 else
16654 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
16655 }
ac4c9b04
MG		 16656
16657 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 16658 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 16659 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
16660 {
16661 unsigned int j;
16662
16663 if (m->count == 0)
16664 continue;
16665 for (j = 0; j < m->count; j++)
16666 {
f0728ee3 16667 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 16668 break;
16669 }
16670 if (j == m->count)
16671 {
16672 m->p_flags = PF_X;
16673 m->p_flags_valid = 1;
16674 }
16675 }
ba96a88f
NC		 16676}
16677
99e4ae17 16678static enum elf_reloc_type_class
7e612e98
AM		 16679elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
16680 const asection *rel_sec ATTRIBUTE_UNUSED,
16681 const Elf_Internal_Rela *rela)
99e4ae17 16682{
f51e552e 16683 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 16684 {
16685 case R_ARM_RELATIVE:
16686 return reloc_class_relative;
16687 case R_ARM_JUMP_SLOT:
16688 return reloc_class_plt;
16689 case R_ARM_COPY:
16690 return reloc_class_copy;
109575d7
JW		 16691 case R_ARM_IRELATIVE:
16692 return reloc_class_ifunc;
99e4ae17
AJ		 16693 default:
16694 return reloc_class_normal;
16695 }
16696}
16697
e489d0ae 16698static void
57e8b36a 16699elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 16700{
5a6c6817 16701 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 16702}
16703
40a18ebd
NC		 16704/* Return TRUE if this is an unwinding table entry. */
16705
16706static bfd_boolean
16707is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
16708{
0112cd26
NC		 16709 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
16710 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 16711}
16712
16713
16714/* Set the type and flags for an ARM section. We do this by
16715 the section name, which is a hack, but ought to work. */
16716
16717static bfd_boolean
16718elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
16719{
16720 const char * name;
16721
16722 name = bfd_get_section_name (abfd, sec);
16723
16724 if (is_arm_elf_unwind_section_name (abfd, name))
16725 {
16726 hdr->sh_type = SHT_ARM_EXIDX;
16727 hdr->sh_flags |= SHF_LINK_ORDER;
16728 }
ac4c9b04 16729
f0728ee3
AV		 16730 if (sec->flags & SEC_ELF_PURECODE)
16731 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 16732
40a18ebd
NC		 16733 return TRUE;
16734}
16735
6dc132d9
L		 16736/* Handle an ARM specific section when reading an object file. This is
16737 called when bfd_section_from_shdr finds a section with an unknown
16738 type. */
40a18ebd
NC		 16739
16740static bfd_boolean
16741elf32_arm_section_from_shdr (bfd *abfd,
16742 Elf_Internal_Shdr * hdr,
6dc132d9
L		 16743 const char *name,
16744 int shindex)
40a18ebd
NC		 16745{
16746 /* There ought to be a place to keep ELF backend specific flags, but
16747 at the moment there isn't one. We just keep track of the
16748 sections by their name, instead. Fortunately, the ABI gives
16749 names for all the ARM specific sections, so we will probably get
16750 away with this. */
16751 switch (hdr->sh_type)
16752 {
16753 case SHT_ARM_EXIDX:
0951f019
RE		 16754 case SHT_ARM_PREEMPTMAP:
16755 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 16756 break;
16757
16758 default:
16759 return FALSE;
16760 }
16761
6dc132d9 16762 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 16763 return FALSE;
16764
16765 return TRUE;
16766}
e489d0ae 16767
44444f50
NC		 16768static _arm_elf_section_data *
16769get_arm_elf_section_data (asection * sec)
16770{
47b2e99c
JZ		 16771 if (sec && sec->owner && is_arm_elf (sec->owner))
16772 return elf32_arm_section_data (sec);
44444f50
NC		 16773 else
16774 return NULL;
8e3de13a
NC		 16775}
16776
4e617b1e
PB		 16777typedef struct
16778{
57402f1e 16779 void *flaginfo;
4e617b1e 16780 struct bfd_link_info *info;
91a5743d
PB		 16781 asection *sec;
16782 int sec_shndx;
6e0b88f1
AM		 16783 int (*func) (void *, const char *, Elf_Internal_Sym *,
16784 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 16785} output_arch_syminfo;
16786
16787enum map_symbol_type
16788{
16789 ARM_MAP_ARM,
16790 ARM_MAP_THUMB,
16791 ARM_MAP_DATA
16792};
16793
16794
7413f23f 16795/* Output a single mapping symbol. */
4e617b1e
PB		 16796
16797static bfd_boolean
7413f23f
DJ		 16798elf32_arm_output_map_sym (output_arch_syminfo *osi,
16799 enum map_symbol_type type,
16800 bfd_vma offset)
4e617b1e
PB		 16801{
16802 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 16803 Elf_Internal_Sym sym;
16804
91a5743d
PB		 16805 sym.st_value = osi->sec->output_section->vma
16806 + osi->sec->output_offset
16807 + offset;
4e617b1e
PB		 16808 sym.st_size = 0;
16809 sym.st_other = 0;
16810 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 16811 sym.st_shndx = osi->sec_shndx;
35fc36a8 16812 sym.st_target_internal = 0;
fe33d2fa 16813 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 16814 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 16815}
16816
34e77a92
RS		 16817/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
16818 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 16819
16820static bfd_boolean
34e77a92
RS		 16821elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
16822 bfd_boolean is_iplt_entry_p,
16823 union gotplt_union *root_plt,
16824 struct arm_plt_info *arm_plt)
4e617b1e 16825{
4e617b1e 16826 struct elf32_arm_link_hash_table *htab;
34e77a92 16827 bfd_vma addr, plt_header_size;
4e617b1e 16828
34e77a92 16829 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 16830 return TRUE;
16831
4dfe6ac6
NC		 16832 htab = elf32_arm_hash_table (osi->info);
16833 if (htab == NULL)
16834 return FALSE;
16835
34e77a92
RS		 16836 if (is_iplt_entry_p)
16837 {
16838 osi->sec = htab->root.iplt;
16839 plt_header_size = 0;
16840 }
16841 else
16842 {
16843 osi->sec = htab->root.splt;
16844 plt_header_size = htab->plt_header_size;
16845 }
16846 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
16847 (osi->info->output_bfd, osi->sec->output_section));
16848
16849 addr = root_plt->offset & -2;
4e617b1e
PB		 16850 if (htab->symbian_p)
16851 {
7413f23f 16852 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16853 return FALSE;
7413f23f 16854 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 16855 return FALSE;
16856 }
16857 else if (htab->vxworks_p)
16858 {
7413f23f 16859 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16860 return FALSE;
7413f23f 16861 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 16862 return FALSE;
7413f23f 16863 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 16864 return FALSE;
7413f23f 16865 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 16866 return FALSE;
16867 }
b38cadfb
NC		 16868 else if (htab->nacl_p)
16869 {
16870 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
16871 return FALSE;
16872 }
eed94f8f
NC		 16873 else if (using_thumb_only (htab))
16874 {
16875 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
16876 return FALSE;
6a631e86 16877 }
4e617b1e
PB		 16878 else
16879 {
34e77a92 16880 bfd_boolean thumb_stub_p;
bd97cb95 16881
34e77a92
RS		 16882 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
16883 if (thumb_stub_p)
4e617b1e 16884 {
7413f23f 16885 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 16886 return FALSE;
16887 }
16888#ifdef FOUR_WORD_PLT
7413f23f 16889 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16890 return FALSE;
7413f23f 16891 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 16892 return FALSE;
16893#else
906e58ca 16894 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 16895 so only need to output a mapping symbol for the first PLT entry and
16896 entries with thumb thunks. */
34e77a92 16897 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 16898 {
7413f23f 16899 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 16900 return FALSE;
16901 }
16902#endif
16903 }
16904
16905 return TRUE;
16906}
16907
34e77a92
RS		 16908/* Output mapping symbols for PLT entries associated with H. */
16909
16910static bfd_boolean
16911elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
16912{
16913 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
16914 struct elf32_arm_link_hash_entry *eh;
16915
16916 if (h->root.type == bfd_link_hash_indirect)
16917 return TRUE;
16918
16919 if (h->root.type == bfd_link_hash_warning)
16920 /* When warning symbols are created, they **replace** the "real"
16921 entry in the hash table, thus we never get to see the real
16922 symbol in a hash traversal. So look at it now. */
16923 h = (struct elf_link_hash_entry *) h->root.u.i.link;
16924
16925 eh = (struct elf32_arm_link_hash_entry *) h;
16926 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
16927 &h->plt, &eh->plt);
16928}
16929
4f4faa4d
TP		 16930/* Bind a veneered symbol to its veneer identified by its hash entry
16931 STUB_ENTRY. The veneered location thus loose its symbol. */
16932
16933static void
16934arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
16935{
16936 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
16937
16938 BFD_ASSERT (hash);
16939 hash->root.root.u.def.section = stub_entry->stub_sec;
16940 hash->root.root.u.def.value = stub_entry->stub_offset;
16941 hash->root.size = stub_entry->stub_size;
16942}
16943
7413f23f
DJ		 16944/* Output a single local symbol for a generated stub. */
16945
16946static bfd_boolean
16947elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
16948 bfd_vma offset, bfd_vma size)
16949{
7413f23f
DJ		 16950 Elf_Internal_Sym sym;
16951
7413f23f
DJ		 16952 sym.st_value = osi->sec->output_section->vma
16953 + osi->sec->output_offset
16954 + offset;
16955 sym.st_size = size;
16956 sym.st_other = 0;
16957 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
16958 sym.st_shndx = osi->sec_shndx;
35fc36a8 16959 sym.st_target_internal = 0;
57402f1e 16960 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 16961}
4e617b1e 16962
da5938a2 16963static bfd_boolean
8029a119
NC		 16964arm_map_one_stub (struct bfd_hash_entry * gen_entry,
16965 void * in_arg)
da5938a2
NC		 16966{
16967 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 16968 asection *stub_sec;
16969 bfd_vma addr;
7413f23f 16970 char *stub_name;
9a008db3 16971 output_arch_syminfo *osi;
d3ce72d0 16972 const insn_sequence *template_sequence;
461a49ca
DJ		 16973 enum stub_insn_type prev_type;
16974 int size;
16975 int i;
16976 enum map_symbol_type sym_type;
da5938a2
NC		 16977
16978 /* Massage our args to the form they really have. */
16979 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 16980 osi = (output_arch_syminfo *) in_arg;
da5938a2 16981
da5938a2
NC		 16982 stub_sec = stub_entry->stub_sec;
16983
16984 /* Ensure this stub is attached to the current section being
7413f23f 16985 processed. */
da5938a2
NC		 16986 if (stub_sec != osi->sec)
16987 return TRUE;
16988
7413f23f 16989 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 16990 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 16991
16992 if (arm_stub_sym_claimed (stub_entry->stub_type))
16993 arm_stub_claim_sym (stub_entry);
16994 else
7413f23f 16995 {
4f4faa4d
TP		 16996 stub_name = stub_entry->output_name;
16997 switch (template_sequence[0].type)
16998 {
16999 case ARM_TYPE:
17000 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
17001 stub_entry->stub_size))
17002 return FALSE;
17003 break;
17004 case THUMB16_TYPE:
17005 case THUMB32_TYPE:
17006 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
17007 stub_entry->stub_size))
17008 return FALSE;
17009 break;
17010 default:
17011 BFD_FAIL ();
17012 return 0;
17013 }
7413f23f 17014 }
da5938a2 17015
461a49ca
DJ		 17016 prev_type = DATA_TYPE;
17017 size = 0;
17018 for (i = 0; i < stub_entry->stub_template_size; i++)
17019 {
d3ce72d0 17020 switch (template_sequence[i].type)
461a49ca
DJ		 17021 {
17022 case ARM_TYPE:
17023 sym_type = ARM_MAP_ARM;
17024 break;
17025
17026 case THUMB16_TYPE:
48229727 17027 case THUMB32_TYPE:
461a49ca
DJ		 17028 sym_type = ARM_MAP_THUMB;
17029 break;
17030
17031 case DATA_TYPE:
17032 sym_type = ARM_MAP_DATA;
17033 break;
17034
17035 default:
17036 BFD_FAIL ();
4e31c731 17037 return FALSE;
461a49ca
DJ		 17038 }
17039
d3ce72d0 17040 if (template_sequence[i].type != prev_type)
461a49ca 17041 {
d3ce72d0 17042 prev_type = template_sequence[i].type;
461a49ca
DJ		 17043 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
17044 return FALSE;
17045 }
17046
d3ce72d0 17047 switch (template_sequence[i].type)
461a49ca
DJ		 17048 {
17049 case ARM_TYPE:
48229727 17050 case THUMB32_TYPE:
461a49ca
DJ		 17051 size += 4;
17052 break;
17053
17054 case THUMB16_TYPE:
17055 size += 2;
17056 break;
17057
17058 case DATA_TYPE:
17059 size += 4;
17060 break;
17061
17062 default:
17063 BFD_FAIL ();
4e31c731 17064 return FALSE;
461a49ca
DJ		 17065 }
17066 }
17067
da5938a2
NC		 17068 return TRUE;
17069}
17070
33811162
DG		 17071/* Output mapping symbols for linker generated sections,
17072 and for those data-only sections that do not have a
17073 $d. */
4e617b1e
PB		 17074
17075static bfd_boolean
17076elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 17077 struct bfd_link_info *info,
57402f1e 17078 void *flaginfo,
6e0b88f1
AM		 17079 int (*func) (void *, const char *,
17080 Elf_Internal_Sym *,
17081 asection *,
17082 struct elf_link_hash_entry *))
4e617b1e
PB		 17083{
17084 output_arch_syminfo osi;
17085 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 17086 bfd_vma offset;
17087 bfd_size_type size;
33811162 17088 bfd *input_bfd;
4e617b1e
PB		 17089
17090 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17091 if (htab == NULL)
17092 return FALSE;
17093
906e58ca 17094 check_use_blx (htab);
91a5743d 17095
57402f1e 17096 osi.flaginfo = flaginfo;
4e617b1e
PB		 17097 osi.info = info;
17098 osi.func = func;
906e58ca 17099
33811162
DG		 17100 /* Add a $d mapping symbol to data-only sections that
17101 don't have any mapping symbol. This may result in (harmless) redundant
17102 mapping symbols. */
17103 for (input_bfd = info->input_bfds;
17104 input_bfd != NULL;
c72f2fb2 17105 input_bfd = input_bfd->link.next)
33811162
DG		 17106 {
17107 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
17108 for (osi.sec = input_bfd->sections;
17109 osi.sec != NULL;
17110 osi.sec = osi.sec->next)
17111 {
17112 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 17113 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
17114 != 0)
33811162
DG		 17115 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
17116 == SEC_HAS_CONTENTS
17117 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 17118 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 17119 && osi.sec->size > 0
17120 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 17121 {
17122 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17123 (output_bfd, osi.sec->output_section);
17124 if (osi.sec_shndx != (int)SHN_BAD)
17125 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
17126 }
17127 }
17128 }
17129
91a5743d
PB		 17130 /* ARM->Thumb glue. */
17131 if (htab->arm_glue_size > 0)
17132 {
3d4d4302
AM		 17133 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17134 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 17135
17136 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17137 (output_bfd, osi.sec->output_section);
0e1862bb 17138 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 17139 || htab->pic_veneer)
17140 size = ARM2THUMB_PIC_GLUE_SIZE;
17141 else if (htab->use_blx)
17142 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
17143 else
17144 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 17145
91a5743d
PB		 17146 for (offset = 0; offset < htab->arm_glue_size; offset += size)
17147 {
7413f23f
DJ		 17148 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
17149 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 17150 }
17151 }
17152
17153 /* Thumb->ARM glue. */
17154 if (htab->thumb_glue_size > 0)
17155 {
3d4d4302
AM		 17156 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17157 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 17158
17159 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17160 (output_bfd, osi.sec->output_section);
17161 size = THUMB2ARM_GLUE_SIZE;
17162
17163 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
17164 {
7413f23f
DJ		 17165 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
17166 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 17167 }
17168 }
17169
845b51d6
PB		 17170 /* ARMv4 BX veneers. */
17171 if (htab->bx_glue_size > 0)
17172 {
3d4d4302
AM		 17173 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17174 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 17175
17176 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17177 (output_bfd, osi.sec->output_section);
17178
7413f23f 17179 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 17180 }
17181
8029a119
NC		 17182 /* Long calls stubs. */
17183 if (htab->stub_bfd && htab->stub_bfd->sections)
17184 {
da5938a2 17185 asection* stub_sec;
8029a119 17186
da5938a2
NC		 17187 for (stub_sec = htab->stub_bfd->sections;
17188 stub_sec != NULL;
8029a119
NC		 17189 stub_sec = stub_sec->next)
17190 {
17191 /* Ignore non-stub sections. */
17192 if (!strstr (stub_sec->name, STUB_SUFFIX))
17193 continue;
da5938a2 17194
8029a119 17195 osi.sec = stub_sec;
da5938a2 17196
8029a119
NC		 17197 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17198 (output_bfd, osi.sec->output_section);
da5938a2 17199
8029a119
NC		 17200 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
17201 }
17202 }
da5938a2 17203
91a5743d 17204 /* Finally, output mapping symbols for the PLT. */
34e77a92 17205 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 17206 {
34e77a92
RS		 17207 osi.sec = htab->root.splt;
17208 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17209 (output_bfd, osi.sec->output_section));
17210
17211 /* Output mapping symbols for the plt header. SymbianOS does not have a
17212 plt header. */
17213 if (htab->vxworks_p)
17214 {
17215 /* VxWorks shared libraries have no PLT header. */
0e1862bb 17216 if (!bfd_link_pic (info))
34e77a92
RS		 17217 {
17218 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17219 return FALSE;
17220 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17221 return FALSE;
17222 }
17223 }
b38cadfb
NC		 17224 else if (htab->nacl_p)
17225 {
17226 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17227 return FALSE;
17228 }
eed94f8f
NC		 17229 else if (using_thumb_only (htab))
17230 {
17231 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
17232 return FALSE;
17233 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17234 return FALSE;
17235 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
17236 return FALSE;
17237 }
34e77a92 17238 else if (!htab->symbian_p)
4e617b1e 17239 {
7413f23f 17240 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 17241 return FALSE;
34e77a92
RS		 17242#ifndef FOUR_WORD_PLT
17243 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 17244 return FALSE;
34e77a92 17245#endif
4e617b1e
PB		 17246 }
17247 }
99059e56
RM		 17248 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
17249 {
17250 /* NaCl uses a special first entry in .iplt too. */
17251 osi.sec = htab->root.iplt;
17252 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17253 (output_bfd, osi.sec->output_section));
17254 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17255 return FALSE;
17256 }
34e77a92
RS		 17257 if ((htab->root.splt && htab->root.splt->size > 0)
17258 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 17259 {
34e77a92
RS		 17260 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
17261 for (input_bfd = info->input_bfds;
17262 input_bfd != NULL;
c72f2fb2 17263 input_bfd = input_bfd->link.next)
34e77a92
RS		 17264 {
17265 struct arm_local_iplt_info **local_iplt;
17266 unsigned int i, num_syms;
4e617b1e 17267
34e77a92
RS		 17268 local_iplt = elf32_arm_local_iplt (input_bfd);
17269 if (local_iplt != NULL)
17270 {
17271 num_syms = elf_symtab_hdr (input_bfd).sh_info;
17272 for (i = 0; i < num_syms; i++)
17273 if (local_iplt[i] != NULL
17274 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
17275 &local_iplt[i]->root,
17276 &local_iplt[i]->arm))
17277 return FALSE;
17278 }
17279 }
17280 }
0855e32b
NS		 17281 if (htab->dt_tlsdesc_plt != 0)
17282 {
17283 /* Mapping symbols for the lazy tls trampoline. */
17284 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
17285 return FALSE;
b38cadfb 17286
0855e32b
NS		 17287 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17288 htab->dt_tlsdesc_plt + 24))
17289 return FALSE;
17290 }
17291 if (htab->tls_trampoline != 0)
17292 {
17293 /* Mapping symbols for the tls trampoline. */
17294 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
17295 return FALSE;
17296#ifdef FOUR_WORD_PLT
17297 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17298 htab->tls_trampoline + 12))
17299 return FALSE;
b38cadfb 17300#endif
0855e32b 17301 }
b38cadfb 17302
4e617b1e
PB		 17303 return TRUE;
17304}
17305
54ddd295
TP		 17306/* Filter normal symbols of CMSE entry functions of ABFD to include in
17307 the import library. All SYMCOUNT symbols of ABFD can be examined
17308 from their pointers in SYMS. Pointers of symbols to keep should be
17309 stored continuously at the beginning of that array.
17310
17311 Returns the number of symbols to keep. */
17312
17313static unsigned int
17314elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17315 struct bfd_link_info *info,
17316 asymbol **syms, long symcount)
17317{
17318 size_t maxnamelen;
17319 char *cmse_name;
17320 long src_count, dst_count = 0;
17321 struct elf32_arm_link_hash_table *htab;
17322
17323 htab = elf32_arm_hash_table (info);
17324 if (!htab->stub_bfd || !htab->stub_bfd->sections)
17325 symcount = 0;
17326
17327 maxnamelen = 128;
17328 cmse_name = (char *) bfd_malloc (maxnamelen);
17329 for (src_count = 0; src_count < symcount; src_count++)
17330 {
17331 struct elf32_arm_link_hash_entry *cmse_hash;
17332 asymbol *sym;
17333 flagword flags;
17334 char *name;
17335 size_t namelen;
17336
17337 sym = syms[src_count];
17338 flags = sym->flags;
17339 name = (char *) bfd_asymbol_name (sym);
17340
17341 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
17342 continue;
17343 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
17344 continue;
17345
17346 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
17347 if (namelen > maxnamelen)
17348 {
17349 cmse_name = (char *)
17350 bfd_realloc (cmse_name, namelen);
17351 maxnamelen = namelen;
17352 }
17353 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
17354 cmse_hash = (struct elf32_arm_link_hash_entry *)
17355 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
17356
17357 if (!cmse_hash
17358 || (cmse_hash->root.root.type != bfd_link_hash_defined
17359 && cmse_hash->root.root.type != bfd_link_hash_defweak)
17360 || cmse_hash->root.type != STT_FUNC)
17361 continue;
17362
17363 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
17364 continue;
17365
17366 syms[dst_count++] = sym;
17367 }
17368 free (cmse_name);
17369
17370 syms[dst_count] = NULL;
17371
17372 return dst_count;
17373}
17374
17375/* Filter symbols of ABFD to include in the import library. All
17376 SYMCOUNT symbols of ABFD can be examined from their pointers in
17377 SYMS. Pointers of symbols to keep should be stored continuously at
17378 the beginning of that array.
17379
17380 Returns the number of symbols to keep. */
17381
17382static unsigned int
17383elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17384 struct bfd_link_info *info,
17385 asymbol **syms, long symcount)
17386{
17387 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
17388
046734ff
TP		 17389 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
17390 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
17391 library to be a relocatable object file. */
17392 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
54ddd295
TP		 17393 if (globals->cmse_implib)
17394 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
17395 else
17396 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
17397}
17398
e489d0ae
PB		 17399/* Allocate target specific section data. */
17400
17401static bfd_boolean
17402elf32_arm_new_section_hook (bfd *abfd, asection *sec)
17403{
f592407e
AM		 17404 if (!sec->used_by_bfd)
17405 {
17406 _arm_elf_section_data *sdata;
17407 bfd_size_type amt = sizeof (*sdata);
e489d0ae 17408
21d799b5 17409 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 17410 if (sdata == NULL)
17411 return FALSE;
17412 sec->used_by_bfd = sdata;
17413 }
e489d0ae
PB		 17414
17415 return _bfd_elf_new_section_hook (abfd, sec);
17416}
17417
17418
17419/* Used to order a list of mapping symbols by address. */
17420
17421static int
17422elf32_arm_compare_mapping (const void * a, const void * b)
17423{
7f6a71ff
JM		 17424 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
17425 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
17426
17427 if (amap->vma > bmap->vma)
17428 return 1;
17429 else if (amap->vma < bmap->vma)
17430 return -1;
17431 else if (amap->type > bmap->type)
17432 /* Ensure results do not depend on the host qsort for objects with
17433 multiple mapping symbols at the same address by sorting on type
17434 after vma. */
17435 return 1;
17436 else if (amap->type < bmap->type)
17437 return -1;
17438 else
17439 return 0;
e489d0ae
PB		 17440}
17441
2468f9c9
PB		 17442/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
17443
17444static unsigned long
17445offset_prel31 (unsigned long addr, bfd_vma offset)
17446{
17447 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
17448}
17449
17450/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
17451 relocations. */
17452
17453static void
17454copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
17455{
17456 unsigned long first_word = bfd_get_32 (output_bfd, from);
17457 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 17458
2468f9c9
PB		 17459 /* High bit of first word is supposed to be zero. */
17460 if ((first_word & 0x80000000ul) == 0)
17461 first_word = offset_prel31 (first_word, offset);
b38cadfb 17462
2468f9c9
PB		 17463 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
17464 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
17465 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
17466 second_word = offset_prel31 (second_word, offset);
b38cadfb 17467
2468f9c9
PB		 17468 bfd_put_32 (output_bfd, first_word, to);
17469 bfd_put_32 (output_bfd, second_word, to + 4);
17470}
e489d0ae 17471
48229727
JB		 17472/* Data for make_branch_to_a8_stub(). */
17473
b38cadfb
NC		 17474struct a8_branch_to_stub_data
17475{
48229727
JB		 17476 asection *writing_section;
17477 bfd_byte *contents;
17478};
17479
17480
17481/* Helper to insert branches to Cortex-A8 erratum stubs in the right
17482 places for a particular section. */
17483
17484static bfd_boolean
17485make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 17486 void *in_arg)
48229727
JB		 17487{
17488 struct elf32_arm_stub_hash_entry *stub_entry;
17489 struct a8_branch_to_stub_data *data;
17490 bfd_byte *contents;
17491 unsigned long branch_insn;
17492 bfd_vma veneered_insn_loc, veneer_entry_loc;
17493 bfd_signed_vma branch_offset;
17494 bfd *abfd;
8d9d9490 17495 unsigned int loc;
48229727
JB		 17496
17497 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
17498 data = (struct a8_branch_to_stub_data *) in_arg;
17499
17500 if (stub_entry->target_section != data->writing_section
4563a860 17501 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 17502 return TRUE;
17503
17504 contents = data->contents;
17505
8d9d9490
TP		 17506 /* We use target_section as Cortex-A8 erratum workaround stubs are only
17507 generated when both source and target are in the same section. */
48229727
JB		 17508 veneered_insn_loc = stub_entry->target_section->output_section->vma
17509 + stub_entry->target_section->output_offset
8d9d9490 17510 + stub_entry->source_value;
48229727
JB		 17511
17512 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
17513 + stub_entry->stub_sec->output_offset
17514 + stub_entry->stub_offset;
17515
17516 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
17517 veneered_insn_loc &= ~3u;
17518
17519 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
17520
17521 abfd = stub_entry->target_section->owner;
8d9d9490 17522 loc = stub_entry->source_value;
48229727
JB		 17523
17524 /* We attempt to avoid this condition by setting stubs_always_after_branch
17525 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
17526 This check is just to be on the safe side... */
17527 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
17528 {
871b3ab2 17529 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub is "
4eca0228 17530 "allocated in unsafe location"), abfd);
48229727
JB		 17531 return FALSE;
17532 }
17533
17534 switch (stub_entry->stub_type)
17535 {
17536 case arm_stub_a8_veneer_b:
17537 case arm_stub_a8_veneer_b_cond:
17538 branch_insn = 0xf0009000;
17539 goto jump24;
17540
17541 case arm_stub_a8_veneer_blx:
17542 branch_insn = 0xf000e800;
17543 goto jump24;
17544
17545 case arm_stub_a8_veneer_bl:
17546 {
17547 unsigned int i1, j1, i2, j2, s;
17548
17549 branch_insn = 0xf000d000;
17550
17551 jump24:
17552 if (branch_offset < -16777216 || branch_offset > 16777214)
17553 {
17554 /* There's not much we can do apart from complain if this
17555 happens. */
871b3ab2 17556 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub out "
4eca0228 17557 "of range (input file too large)"), abfd);
48229727
JB		 17558 return FALSE;
17559 }
17560
17561 /* i1 = not(j1 eor s), so:
17562 not i1 = j1 eor s
17563 j1 = (not i1) eor s. */
17564
17565 branch_insn |= (branch_offset >> 1) & 0x7ff;
17566 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
17567 i2 = (branch_offset >> 22) & 1;
17568 i1 = (branch_offset >> 23) & 1;
17569 s = (branch_offset >> 24) & 1;
17570 j1 = (!i1) ^ s;
17571 j2 = (!i2) ^ s;
17572 branch_insn |= j2 << 11;
17573 branch_insn |= j1 << 13;
17574 branch_insn |= s << 26;
17575 }
17576 break;
17577
17578 default:
17579 BFD_FAIL ();
17580 return FALSE;
17581 }
17582
8d9d9490
TP		 17583 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
17584 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 17585
17586 return TRUE;
17587}
17588
a504d23a
LA		 17589/* Beginning of stm32l4xx work-around. */
17590
17591/* Functions encoding instructions necessary for the emission of the
17592 fix-stm32l4xx-629360.
17593 Encoding is extracted from the
17594 ARM (C) Architecture Reference Manual
17595 ARMv7-A and ARMv7-R edition
17596 ARM DDI 0406C.b (ID072512). */
17597
17598static inline bfd_vma
82188b29 17599create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 17600{
17601 /* A8.8.18 B (A8-334)
17602 B target_address (Encoding T4). */
17603 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
17604 /* jump offset is: S:I1:I2:imm10:imm11:0. */
17605 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
17606
a504d23a
LA		 17607 int s = ((branch_offset & 0x1000000) >> 24);
17608 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
17609 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
17610
17611 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
17612 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
17613
17614 bfd_vma patched_inst = 0xf0009000
17615 | s << 26 /* S. */
17616 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
17617 | j1 << 13 /* J1. */
17618 | j2 << 11 /* J2. */
17619 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
17620
17621 return patched_inst;
17622}
17623
17624static inline bfd_vma
17625create_instruction_ldmia (int base_reg, int wback, int reg_mask)
17626{
17627 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
17628 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
17629 bfd_vma patched_inst = 0xe8900000
17630 | (/*W=*/wback << 21)
17631 | (base_reg << 16)
17632 | (reg_mask & 0x0000ffff);
17633
17634 return patched_inst;
17635}
17636
17637static inline bfd_vma
17638create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
17639{
17640 /* A8.8.60 LDMDB/LDMEA (A8-402)
17641 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
17642 bfd_vma patched_inst = 0xe9100000
17643 | (/*W=*/wback << 21)
17644 | (base_reg << 16)
17645 | (reg_mask & 0x0000ffff);
17646
17647 return patched_inst;
17648}
17649
17650static inline bfd_vma
17651create_instruction_mov (int target_reg, int source_reg)
17652{
17653 /* A8.8.103 MOV (register) (A8-486)
17654 MOV Rd, Rm (Encoding T1). */
17655 bfd_vma patched_inst = 0x4600
17656 | (target_reg & 0x7)
17657 | ((target_reg & 0x8) >> 3) << 7
17658 | (source_reg << 3);
17659
17660 return patched_inst;
17661}
17662
17663static inline bfd_vma
17664create_instruction_sub (int target_reg, int source_reg, int value)
17665{
17666 /* A8.8.221 SUB (immediate) (A8-708)
17667 SUB Rd, Rn, #value (Encoding T3). */
17668 bfd_vma patched_inst = 0xf1a00000
17669 | (target_reg << 8)
17670 | (source_reg << 16)
17671 | (/*S=*/0 << 20)
17672 | ((value & 0x800) >> 11) << 26
17673 | ((value & 0x700) >> 8) << 12
17674 | (value & 0x0ff);
17675
17676 return patched_inst;
17677}
17678
17679static inline bfd_vma
9239bbd3 17680create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 17681 int first_reg)
17682{
17683 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17684 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
17685 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 17686 | (/*W=*/wback << 21)
17687 | (base_reg << 16)
9239bbd3
CM		 17688 | (num_words & 0x000000ff)
17689 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 17690 | (first_reg & 0x00000001) << 22;
17691
17692 return patched_inst;
17693}
17694
17695static inline bfd_vma
9239bbd3
CM		 17696create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
17697 int first_reg)
a504d23a
LA		 17698{
17699 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17700 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
17701 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 17702 | (base_reg << 16)
9239bbd3
CM		 17703 | (num_words & 0x000000ff)
17704 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 17705 | (first_reg & 0x00000001) << 22;
17706
17707 return patched_inst;
17708}
17709
17710static inline bfd_vma
17711create_instruction_udf_w (int value)
17712{
17713 /* A8.8.247 UDF (A8-758)
17714 Undefined (Encoding T2). */
17715 bfd_vma patched_inst = 0xf7f0a000
17716 | (value & 0x00000fff)
17717 | (value & 0x000f0000) << 16;
17718
17719 return patched_inst;
17720}
17721
17722static inline bfd_vma
17723create_instruction_udf (int value)
17724{
17725 /* A8.8.247 UDF (A8-758)
17726 Undefined (Encoding T1). */
17727 bfd_vma patched_inst = 0xde00
17728 | (value & 0xff);
17729
17730 return patched_inst;
17731}
17732
17733/* Functions writing an instruction in memory, returning the next
17734 memory position to write to. */
17735
17736static inline bfd_byte *
17737push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
17738 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17739{
17740 put_thumb2_insn (htab, output_bfd, insn, pt);
17741 return pt + 4;
17742}
17743
17744static inline bfd_byte *
17745push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
17746 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17747{
17748 put_thumb_insn (htab, output_bfd, insn, pt);
17749 return pt + 2;
17750}
17751
17752/* Function filling up a region in memory with T1 and T2 UDFs taking
17753 care of alignment. */
17754
17755static bfd_byte *
17756stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
07d6d2b8
AM		 17757 bfd * output_bfd,
17758 const bfd_byte * const base_stub_contents,
17759 bfd_byte * const from_stub_contents,
17760 const bfd_byte * const end_stub_contents)
a504d23a
LA		 17761{
17762 bfd_byte *current_stub_contents = from_stub_contents;
17763
17764 /* Fill the remaining of the stub with deterministic contents : UDF
17765 instructions.
17766 Check if realignment is needed on modulo 4 frontier using T1, to
17767 further use T2. */
17768 if ((current_stub_contents < end_stub_contents)
17769 && !((current_stub_contents - base_stub_contents) % 2)
17770 && ((current_stub_contents - base_stub_contents) % 4))
17771 current_stub_contents =
17772 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17773 create_instruction_udf (0));
17774
17775 for (; current_stub_contents < end_stub_contents;)
17776 current_stub_contents =
17777 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17778 create_instruction_udf_w (0));
17779
17780 return current_stub_contents;
17781}
17782
17783/* Functions writing the stream of instructions equivalent to the
17784 derived sequence for ldmia, ldmdb, vldm respectively. */
17785
17786static void
17787stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
17788 bfd * output_bfd,
17789 const insn32 initial_insn,
17790 const bfd_byte *const initial_insn_addr,
17791 bfd_byte *const base_stub_contents)
17792{
17793 int wback = (initial_insn & 0x00200000) >> 21;
17794 int ri, rn = (initial_insn & 0x000F0000) >> 16;
17795 int insn_all_registers = initial_insn & 0x0000ffff;
17796 int insn_low_registers, insn_high_registers;
17797 int usable_register_mask;
b25e998d 17798 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 17799 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
17800 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
17801 bfd_byte *current_stub_contents = base_stub_contents;
17802
17803 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
17804
17805 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
17806 smaller than 8 registers load sequences that do not cause the
17807 hardware issue. */
17808 if (nb_registers <= 8)
17809 {
17810 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
17811 current_stub_contents =
17812 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17813 initial_insn);
17814
17815 /* B initial_insn_addr+4. */
17816 if (!restore_pc)
17817 current_stub_contents =
17818 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17819 create_instruction_branch_absolute
82188b29 17820 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17821
17822 /* Fill the remaining of the stub with deterministic contents. */
17823 current_stub_contents =
17824 stm32l4xx_fill_stub_udf (htab, output_bfd,
17825 base_stub_contents, current_stub_contents,
17826 base_stub_contents +
17827 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17828
17829 return;
17830 }
17831
17832 /* - reg_list[13] == 0. */
17833 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
17834
17835 /* - reg_list[14] & reg_list[15] != 1. */
17836 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
17837
17838 /* - if (wback==1) reg_list[rn] == 0. */
17839 BFD_ASSERT (!wback || !restore_rn);
17840
17841 /* - nb_registers > 8. */
b25e998d 17842 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 17843
17844 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
17845
17846 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
17847 - One with the 7 lowest registers (register mask 0x007F)
17848 This LDM will finally contain between 2 and 7 registers
17849 - One with the 7 highest registers (register mask 0xDF80)
17850 This ldm will finally contain between 2 and 7 registers. */
17851 insn_low_registers = insn_all_registers & 0x007F;
17852 insn_high_registers = insn_all_registers & 0xDF80;
17853
17854 /* A spare register may be needed during this veneer to temporarily
17855 handle the base register. This register will be restored with the
17856 last LDM operation.
17857 The usable register may be any general purpose register (that
17858 excludes PC, SP, LR : register mask is 0x1FFF). */
17859 usable_register_mask = 0x1FFF;
17860
17861 /* Generate the stub function. */
17862 if (wback)
17863 {
17864 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
17865 current_stub_contents =
17866 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17867 create_instruction_ldmia
17868 (rn, /*wback=*/1, insn_low_registers));
17869
17870 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
17871 current_stub_contents =
17872 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17873 create_instruction_ldmia
17874 (rn, /*wback=*/1, insn_high_registers));
17875 if (!restore_pc)
17876 {
17877 /* B initial_insn_addr+4. */
17878 current_stub_contents =
17879 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17880 create_instruction_branch_absolute
82188b29 17881 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17882 }
17883 }
17884 else /* if (!wback). */
17885 {
17886 ri = rn;
17887
17888 /* If Rn is not part of the high-register-list, move it there. */
17889 if (!(insn_high_registers & (1 << rn)))
17890 {
17891 /* Choose a Ri in the high-register-list that will be restored. */
17892 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
17893
17894 /* MOV Ri, Rn. */
17895 current_stub_contents =
17896 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17897 create_instruction_mov (ri, rn));
17898 }
17899
17900 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
17901 current_stub_contents =
17902 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17903 create_instruction_ldmia
17904 (ri, /*wback=*/1, insn_low_registers));
17905
17906 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
17907 current_stub_contents =
17908 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17909 create_instruction_ldmia
17910 (ri, /*wback=*/0, insn_high_registers));
17911
17912 if (!restore_pc)
17913 {
17914 /* B initial_insn_addr+4. */
17915 current_stub_contents =
17916 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17917 create_instruction_branch_absolute
82188b29 17918 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17919 }
17920 }
17921
17922 /* Fill the remaining of the stub with deterministic contents. */
17923 current_stub_contents =
17924 stm32l4xx_fill_stub_udf (htab, output_bfd,
17925 base_stub_contents, current_stub_contents,
17926 base_stub_contents +
17927 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17928}
17929
17930static void
17931stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
17932 bfd * output_bfd,
17933 const insn32 initial_insn,
17934 const bfd_byte *const initial_insn_addr,
17935 bfd_byte *const base_stub_contents)
17936{
17937 int wback = (initial_insn & 0x00200000) >> 21;
17938 int ri, rn = (initial_insn & 0x000f0000) >> 16;
17939 int insn_all_registers = initial_insn & 0x0000ffff;
17940 int insn_low_registers, insn_high_registers;
17941 int usable_register_mask;
17942 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
17943 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 17944 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 17945 bfd_byte *current_stub_contents = base_stub_contents;
17946
17947 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
17948
17949 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
17950 smaller than 8 registers load sequences that do not cause the
17951 hardware issue. */
17952 if (nb_registers <= 8)
17953 {
17954 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
17955 current_stub_contents =
17956 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17957 initial_insn);
17958
17959 /* B initial_insn_addr+4. */
17960 current_stub_contents =
17961 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17962 create_instruction_branch_absolute
82188b29 17963 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17964
17965 /* Fill the remaining of the stub with deterministic contents. */
17966 current_stub_contents =
17967 stm32l4xx_fill_stub_udf (htab, output_bfd,
17968 base_stub_contents, current_stub_contents,
17969 base_stub_contents +
17970 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17971
17972 return;
17973 }
17974
17975 /* - reg_list[13] == 0. */
17976 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
17977
17978 /* - reg_list[14] & reg_list[15] != 1. */
17979 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
17980
17981 /* - if (wback==1) reg_list[rn] == 0. */
17982 BFD_ASSERT (!wback || !restore_rn);
17983
17984 /* - nb_registers > 8. */
b25e998d 17985 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 17986
17987 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
17988
17989 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
17990 - One with the 7 lowest registers (register mask 0x007F)
17991 This LDM will finally contain between 2 and 7 registers
17992 - One with the 7 highest registers (register mask 0xDF80)
17993 This ldm will finally contain between 2 and 7 registers. */
17994 insn_low_registers = insn_all_registers & 0x007F;
17995 insn_high_registers = insn_all_registers & 0xDF80;
17996
17997 /* A spare register may be needed during this veneer to temporarily
17998 handle the base register. This register will be restored with
17999 the last LDM operation.
18000 The usable register may be any general purpose register (that excludes
18001 PC, SP, LR : register mask is 0x1FFF). */
18002 usable_register_mask = 0x1FFF;
18003
18004 /* Generate the stub function. */
18005 if (!wback && !restore_pc && !restore_rn)
18006 {
18007 /* Choose a Ri in the low-register-list that will be restored. */
18008 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18009
18010 /* MOV Ri, Rn. */
18011 current_stub_contents =
18012 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18013 create_instruction_mov (ri, rn));
18014
18015 /* LDMDB Ri!, {R-high-register-list}. */
18016 current_stub_contents =
18017 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18018 create_instruction_ldmdb
18019 (ri, /*wback=*/1, insn_high_registers));
18020
18021 /* LDMDB Ri, {R-low-register-list}. */
18022 current_stub_contents =
18023 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18024 create_instruction_ldmdb
18025 (ri, /*wback=*/0, insn_low_registers));
18026
18027 /* B initial_insn_addr+4. */
18028 current_stub_contents =
18029 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18030 create_instruction_branch_absolute
82188b29 18031 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18032 }
18033 else if (wback && !restore_pc && !restore_rn)
18034 {
18035 /* LDMDB Rn!, {R-high-register-list}. */
18036 current_stub_contents =
18037 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18038 create_instruction_ldmdb
18039 (rn, /*wback=*/1, insn_high_registers));
18040
18041 /* LDMDB Rn!, {R-low-register-list}. */
18042 current_stub_contents =
18043 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18044 create_instruction_ldmdb
18045 (rn, /*wback=*/1, insn_low_registers));
18046
18047 /* B initial_insn_addr+4. */
18048 current_stub_contents =
18049 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18050 create_instruction_branch_absolute
82188b29 18051 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18052 }
18053 else if (!wback && restore_pc && !restore_rn)
18054 {
18055 /* Choose a Ri in the high-register-list that will be restored. */
18056 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18057
18058 /* SUB Ri, Rn, #(4*nb_registers). */
18059 current_stub_contents =
18060 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18061 create_instruction_sub (ri, rn, (4 * nb_registers)));
18062
18063 /* LDMIA Ri!, {R-low-register-list}. */
18064 current_stub_contents =
18065 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18066 create_instruction_ldmia
18067 (ri, /*wback=*/1, insn_low_registers));
18068
18069 /* LDMIA Ri, {R-high-register-list}. */
18070 current_stub_contents =
18071 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18072 create_instruction_ldmia
18073 (ri, /*wback=*/0, insn_high_registers));
18074 }
18075 else if (wback && restore_pc && !restore_rn)
18076 {
18077 /* Choose a Ri in the high-register-list that will be restored. */
18078 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18079
18080 /* SUB Rn, Rn, #(4*nb_registers) */
18081 current_stub_contents =
18082 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18083 create_instruction_sub (rn, rn, (4 * nb_registers)));
18084
18085 /* MOV Ri, Rn. */
18086 current_stub_contents =
18087 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18088 create_instruction_mov (ri, rn));
18089
18090 /* LDMIA Ri!, {R-low-register-list}. */
18091 current_stub_contents =
18092 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18093 create_instruction_ldmia
18094 (ri, /*wback=*/1, insn_low_registers));
18095
18096 /* LDMIA Ri, {R-high-register-list}. */
18097 current_stub_contents =
18098 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18099 create_instruction_ldmia
18100 (ri, /*wback=*/0, insn_high_registers));
18101 }
18102 else if (!wback && !restore_pc && restore_rn)
18103 {
18104 ri = rn;
18105 if (!(insn_low_registers & (1 << rn)))
18106 {
18107 /* Choose a Ri in the low-register-list that will be restored. */
18108 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18109
18110 /* MOV Ri, Rn. */
18111 current_stub_contents =
18112 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18113 create_instruction_mov (ri, rn));
18114 }
18115
18116 /* LDMDB Ri!, {R-high-register-list}. */
18117 current_stub_contents =
18118 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18119 create_instruction_ldmdb
18120 (ri, /*wback=*/1, insn_high_registers));
18121
18122 /* LDMDB Ri, {R-low-register-list}. */
18123 current_stub_contents =
18124 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18125 create_instruction_ldmdb
18126 (ri, /*wback=*/0, insn_low_registers));
18127
18128 /* B initial_insn_addr+4. */
18129 current_stub_contents =
18130 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18131 create_instruction_branch_absolute
82188b29 18132 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18133 }
18134 else if (!wback && restore_pc && restore_rn)
18135 {
18136 ri = rn;
18137 if (!(insn_high_registers & (1 << rn)))
18138 {
18139 /* Choose a Ri in the high-register-list that will be restored. */
18140 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18141 }
18142
18143 /* SUB Ri, Rn, #(4*nb_registers). */
18144 current_stub_contents =
18145 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18146 create_instruction_sub (ri, rn, (4 * nb_registers)));
18147
18148 /* LDMIA Ri!, {R-low-register-list}. */
18149 current_stub_contents =
18150 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18151 create_instruction_ldmia
18152 (ri, /*wback=*/1, insn_low_registers));
18153
18154 /* LDMIA Ri, {R-high-register-list}. */
18155 current_stub_contents =
18156 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18157 create_instruction_ldmia
18158 (ri, /*wback=*/0, insn_high_registers));
18159 }
18160 else if (wback && restore_rn)
18161 {
18162 /* The assembler should not have accepted to encode this. */
18163 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
18164 "undefined behavior.\n");
18165 }
18166
18167 /* Fill the remaining of the stub with deterministic contents. */
18168 current_stub_contents =
18169 stm32l4xx_fill_stub_udf (htab, output_bfd,
18170 base_stub_contents, current_stub_contents,
18171 base_stub_contents +
18172 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18173
18174}
18175
18176static void
18177stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
18178 bfd * output_bfd,
18179 const insn32 initial_insn,
18180 const bfd_byte *const initial_insn_addr,
18181 bfd_byte *const base_stub_contents)
18182{
9239bbd3 18183 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 18184 bfd_byte *current_stub_contents = base_stub_contents;
18185
18186 BFD_ASSERT (is_thumb2_vldm (initial_insn));
18187
18188 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 18189 smaller than 8 words load sequences that do not cause the
a504d23a 18190 hardware issue. */
9239bbd3 18191 if (num_words <= 8)
a504d23a
LA		 18192 {
18193 /* Untouched instruction. */
18194 current_stub_contents =
18195 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18196 initial_insn);
18197
18198 /* B initial_insn_addr+4. */
18199 current_stub_contents =
18200 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18201 create_instruction_branch_absolute
82188b29 18202 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18203 }
18204 else
18205 {
9eaff861 18206 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 18207 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 18208 bfd_boolean is_ia_nobang = /* (IA without !). */
18209 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
18210 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
18211 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
18212 bfd_boolean is_db_bang = /* (DB with !). */
18213 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 18214 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 18215 /* d = UInt (Vd:D);. */
9239bbd3 18216 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 18217 | (((unsigned int)initial_insn << 9) >> 31);
18218
9239bbd3
CM		 18219 /* Compute the number of 8-words chunks needed to split. */
18220 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 18221 int chunk;
18222
18223 /* The test coverage has been done assuming the following
18224 hypothesis that exactly one of the previous is_ predicates is
18225 true. */
9239bbd3
CM		 18226 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
18227 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 18228
9239bbd3 18229 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 18230 cases, then we emit the adjustments:
18231
18232 vldm rx, {...}
18233 -> vldm rx!, {8_words_or_less} for each needed 8_word
18234 -> sub rx, rx, #size (list)
18235
18236 vldm rx!, {...}
18237 -> vldm rx!, {8_words_or_less} for each needed 8_word
18238 This also handles vpop instruction (when rx is sp)
18239
18240 vldmd rx!, {...}
18241 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 18242 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 18243 {
9239bbd3
CM		 18244 bfd_vma new_insn = 0;
18245
a504d23a
LA		 18246 if (is_ia_nobang || is_ia_bang)
18247 {
9239bbd3
CM		 18248 new_insn = create_instruction_vldmia
18249 (base_reg,
18250 is_dp,
18251 /*wback= . */1,
18252 chunks - (chunk + 1) ?
18253 8 : num_words - chunk * 8,
18254 first_reg + chunk * 8);
a504d23a
LA		 18255 }
18256 else if (is_db_bang)
18257 {
9239bbd3
CM		 18258 new_insn = create_instruction_vldmdb
18259 (base_reg,
18260 is_dp,
18261 chunks - (chunk + 1) ?
18262 8 : num_words - chunk * 8,
18263 first_reg + chunk * 8);
a504d23a 18264 }
9239bbd3
CM		 18265
18266 if (new_insn)
18267 current_stub_contents =
18268 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18269 new_insn);
a504d23a
LA		 18270 }
18271
18272 /* Only this case requires the base register compensation
18273 subtract. */
18274 if (is_ia_nobang)
18275 {
18276 current_stub_contents =
18277 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18278 create_instruction_sub
9239bbd3 18279 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 18280 }
18281
18282 /* B initial_insn_addr+4. */
18283 current_stub_contents =
18284 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18285 create_instruction_branch_absolute
82188b29 18286 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18287 }
18288
18289 /* Fill the remaining of the stub with deterministic contents. */
18290 current_stub_contents =
18291 stm32l4xx_fill_stub_udf (htab, output_bfd,
18292 base_stub_contents, current_stub_contents,
18293 base_stub_contents +
18294 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
18295}
18296
18297static void
18298stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
18299 bfd * output_bfd,
18300 const insn32 wrong_insn,
18301 const bfd_byte *const wrong_insn_addr,
18302 bfd_byte *const stub_contents)
18303{
18304 if (is_thumb2_ldmia (wrong_insn))
18305 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
18306 wrong_insn, wrong_insn_addr,
18307 stub_contents);
18308 else if (is_thumb2_ldmdb (wrong_insn))
18309 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
18310 wrong_insn, wrong_insn_addr,
18311 stub_contents);
18312 else if (is_thumb2_vldm (wrong_insn))
18313 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
18314 wrong_insn, wrong_insn_addr,
18315 stub_contents);
18316}
18317
18318/* End of stm32l4xx work-around. */
18319
18320
e489d0ae
PB		 18321/* Do code byteswapping. Return FALSE afterwards so that the section is
18322 written out as normal. */
18323
18324static bfd_boolean
c7b8f16e 18325elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 18326 struct bfd_link_info *link_info,
18327 asection *sec,
e489d0ae
PB		 18328 bfd_byte *contents)
18329{
48229727 18330 unsigned int mapcount, errcount;
8e3de13a 18331 _arm_elf_section_data *arm_data;
c7b8f16e 18332 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 18333 elf32_arm_section_map *map;
c7b8f16e 18334 elf32_vfp11_erratum_list *errnode;
a504d23a 18335 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 18336 bfd_vma ptr;
18337 bfd_vma end;
c7b8f16e 18338 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 18339 bfd_byte tmp;
48229727 18340 unsigned int i;
57e8b36a 18341
4dfe6ac6
NC		 18342 if (globals == NULL)
18343 return FALSE;
18344
8e3de13a
NC		 18345 /* If this section has not been allocated an _arm_elf_section_data
18346 structure then we cannot record anything. */
18347 arm_data = get_arm_elf_section_data (sec);
18348 if (arm_data == NULL)
18349 return FALSE;
18350
18351 mapcount = arm_data->mapcount;
18352 map = arm_data->map;
c7b8f16e
JB		 18353 errcount = arm_data->erratumcount;
18354
18355 if (errcount != 0)
18356 {
18357 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
18358
18359 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 18360 errnode = errnode->next)
18361 {
18362 bfd_vma target = errnode->vma - offset;
18363
18364 switch (errnode->type)
18365 {
18366 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
18367 {
18368 bfd_vma branch_to_veneer;
18369 /* Original condition code of instruction, plus bit mask for
18370 ARM B instruction. */
18371 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
18372 | 0x0a000000;
c7b8f16e
JB		 18373
18374 /* The instruction is before the label. */
91d6fa6a 18375 target -= 4;
c7b8f16e
JB		 18376
18377 /* Above offset included in -4 below. */
18378 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 18379 - errnode->vma - 4;
c7b8f16e
JB		 18380
18381 if ((signed) branch_to_veneer < -(1 << 25)
18382 || (signed) branch_to_veneer >= (1 << 25))
871b3ab2 18383 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 18384 "range"), output_bfd);
c7b8f16e 18385
99059e56
RM		 18386 insn |= (branch_to_veneer >> 2) & 0xffffff;
18387 contents[endianflip ^ target] = insn & 0xff;
18388 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18389 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18390 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18391 }
18392 break;
c7b8f16e
JB		 18393
18394 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 18395 {
18396 bfd_vma branch_from_veneer;
18397 unsigned int insn;
c7b8f16e 18398
99059e56
RM		 18399 /* Take size of veneer into account. */
18400 branch_from_veneer = errnode->u.v.branch->vma
18401 - errnode->vma - 12;
c7b8f16e
JB		 18402
18403 if ((signed) branch_from_veneer < -(1 << 25)
18404 || (signed) branch_from_veneer >= (1 << 25))
871b3ab2 18405 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 18406 "range"), output_bfd);
c7b8f16e 18407
99059e56
RM		 18408 /* Original instruction. */
18409 insn = errnode->u.v.branch->u.b.vfp_insn;
18410 contents[endianflip ^ target] = insn & 0xff;
18411 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18412 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18413 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18414
18415 /* Branch back to insn after original insn. */
18416 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
18417 contents[endianflip ^ (target + 4)] = insn & 0xff;
18418 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
18419 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
18420 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
18421 }
18422 break;
c7b8f16e 18423
99059e56
RM		 18424 default:
18425 abort ();
18426 }
18427 }
c7b8f16e 18428 }
e489d0ae 18429
a504d23a
LA		 18430 if (arm_data->stm32l4xx_erratumcount != 0)
18431 {
18432 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
18433 stm32l4xx_errnode != 0;
18434 stm32l4xx_errnode = stm32l4xx_errnode->next)
18435 {
18436 bfd_vma target = stm32l4xx_errnode->vma - offset;
18437
18438 switch (stm32l4xx_errnode->type)
18439 {
18440 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
18441 {
18442 unsigned int insn;
18443 bfd_vma branch_to_veneer =
18444 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
18445
18446 if ((signed) branch_to_veneer < -(1 << 24)
18447 || (signed) branch_to_veneer >= (1 << 24))
18448 {
18449 bfd_vma out_of_range =
18450 ((signed) branch_to_veneer < -(1 << 24)) ?
18451 - branch_to_veneer - (1 << 24) :
18452 ((signed) branch_to_veneer >= (1 << 24)) ?
18453 branch_to_veneer - (1 << 24) : 0;
18454
4eca0228 18455 _bfd_error_handler
2dcf00ce 18456 (_("%pB(%#" PRIx64 "): error: "
90b6238f
AM		 18457 "cannot create STM32L4XX veneer; "
18458 "jump out of range by %" PRId64 " bytes; "
18459 "cannot encode branch instruction"),
a504d23a 18460 output_bfd,
2dcf00ce
AM		 18461 (uint64_t) (stm32l4xx_errnode->vma - 4),
18462 (int64_t) out_of_range);
a504d23a
LA		 18463 continue;
18464 }
18465
18466 insn = create_instruction_branch_absolute
82188b29 18467 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 18468
18469 /* The instruction is before the label. */
18470 target -= 4;
18471
18472 put_thumb2_insn (globals, output_bfd,
18473 (bfd_vma) insn, contents + target);
18474 }
18475 break;
18476
18477 case STM32L4XX_ERRATUM_VENEER:
18478 {
82188b29
NC		 18479 bfd_byte * veneer;
18480 bfd_byte * veneer_r;
a504d23a
LA		 18481 unsigned int insn;
18482
82188b29
NC		 18483 veneer = contents + target;
18484 veneer_r = veneer
18485 + stm32l4xx_errnode->u.b.veneer->vma
18486 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 18487
18488 if ((signed) (veneer_r - veneer -
18489 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
18490 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
18491 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
18492 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
18493 || (signed) (veneer_r - veneer) >= (1 << 24))
18494 {
90b6238f
AM		 18495 _bfd_error_handler (_("%pB: error: cannot create STM32L4XX "
18496 "veneer"), output_bfd);
a504d23a
LA		 18497 continue;
18498 }
18499
18500 /* Original instruction. */
18501 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
18502
18503 stm32l4xx_create_replacing_stub
18504 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
18505 }
18506 break;
18507
18508 default:
18509 abort ();
18510 }
18511 }
18512 }
18513
2468f9c9
PB		 18514 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
18515 {
18516 arm_unwind_table_edit *edit_node
99059e56 18517 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 18518 /* Now, sec->size is the size of the section we will write. The original
99059e56 18519 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 18520 markers) was sec->rawsize. (This isn't the case if we perform no
18521 edits, then rawsize will be zero and we should use size). */
21d799b5 18522 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 18523 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
18524 unsigned int in_index, out_index;
18525 bfd_vma add_to_offsets = 0;
18526
18527 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 18528 {
2468f9c9
PB		 18529 if (edit_node)
18530 {
18531 unsigned int edit_index = edit_node->index;
b38cadfb 18532
2468f9c9 18533 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 18534 {
2468f9c9
PB		 18535 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18536 contents + in_index * 8, add_to_offsets);
18537 out_index++;
18538 in_index++;
18539 }
18540 else if (in_index == edit_index
18541 || (in_index * 8 >= input_size
18542 && edit_index == UINT_MAX))
99059e56 18543 {
2468f9c9
PB		 18544 switch (edit_node->type)
18545 {
18546 case DELETE_EXIDX_ENTRY:
18547 in_index++;
18548 add_to_offsets += 8;
18549 break;
b38cadfb 18550
2468f9c9
PB		 18551 case INSERT_EXIDX_CANTUNWIND_AT_END:
18552 {
99059e56 18553 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 18554 bfd_vma text_offset = text_sec->output_section->vma
18555 + text_sec->output_offset
18556 + text_sec->size;
18557 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 18558 unsigned long prel31_offset;
2468f9c9
PB		 18559
18560 /* Note: this is meant to be equivalent to an
18561 R_ARM_PREL31 relocation. These synthetic
18562 EXIDX_CANTUNWIND markers are not relocated by the
18563 usual BFD method. */
18564 prel31_offset = (text_offset - exidx_offset)
18565 & 0x7ffffffful;
491d01d3
YU		 18566 if (bfd_link_relocatable (link_info))
18567 {
18568 /* Here relocation for new EXIDX_CANTUNWIND is
18569 created, so there is no need to
18570 adjust offset by hand. */
18571 prel31_offset = text_sec->output_offset
18572 + text_sec->size;
491d01d3 18573 }
2468f9c9
PB		 18574
18575 /* First address we can't unwind. */
18576 bfd_put_32 (output_bfd, prel31_offset,
18577 &edited_contents[out_index * 8]);
18578
18579 /* Code for EXIDX_CANTUNWIND. */
18580 bfd_put_32 (output_bfd, 0x1,
18581 &edited_contents[out_index * 8 + 4]);
18582
18583 out_index++;
18584 add_to_offsets -= 8;
18585 }
18586 break;
18587 }
b38cadfb 18588
2468f9c9
PB		 18589 edit_node = edit_node->next;
18590 }
18591 }
18592 else
18593 {
18594 /* No more edits, copy remaining entries verbatim. */
18595 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18596 contents + in_index * 8, add_to_offsets);
18597 out_index++;
18598 in_index++;
18599 }
18600 }
18601
18602 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
18603 bfd_set_section_contents (output_bfd, sec->output_section,
18604 edited_contents,
18605 (file_ptr) sec->output_offset, sec->size);
18606
18607 return TRUE;
18608 }
18609
48229727
JB		 18610 /* Fix code to point to Cortex-A8 erratum stubs. */
18611 if (globals->fix_cortex_a8)
18612 {
18613 struct a8_branch_to_stub_data data;
18614
18615 data.writing_section = sec;
18616 data.contents = contents;
18617
a504d23a
LA		 18618 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
18619 & data);
48229727
JB		 18620 }
18621
e489d0ae
PB		 18622 if (mapcount == 0)
18623 return FALSE;
18624
c7b8f16e 18625 if (globals->byteswap_code)
e489d0ae 18626 {
c7b8f16e 18627 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 18628
c7b8f16e
JB		 18629 ptr = map[0].vma;
18630 for (i = 0; i < mapcount; i++)
99059e56
RM		 18631 {
18632 if (i == mapcount - 1)
c7b8f16e 18633 end = sec->size;
99059e56
RM		 18634 else
18635 end = map[i + 1].vma;
e489d0ae 18636
99059e56 18637 switch (map[i].type)
e489d0ae 18638 {
c7b8f16e
JB		 18639 case 'a':
18640 /* Byte swap code words. */
18641 while (ptr + 3 < end)
99059e56
RM		 18642 {
18643 tmp = contents[ptr];
18644 contents[ptr] = contents[ptr + 3];
18645 contents[ptr + 3] = tmp;
18646 tmp = contents[ptr + 1];
18647 contents[ptr + 1] = contents[ptr + 2];
18648 contents[ptr + 2] = tmp;
18649 ptr += 4;
18650 }
c7b8f16e 18651 break;
e489d0ae 18652
c7b8f16e
JB		 18653 case 't':
18654 /* Byte swap code halfwords. */
18655 while (ptr + 1 < end)
99059e56
RM		 18656 {
18657 tmp = contents[ptr];
18658 contents[ptr] = contents[ptr + 1];
18659 contents[ptr + 1] = tmp;
18660 ptr += 2;
18661 }
c7b8f16e
JB		 18662 break;
18663
18664 case 'd':
18665 /* Leave data alone. */
18666 break;
18667 }
99059e56
RM		 18668 ptr = end;
18669 }
e489d0ae 18670 }
8e3de13a 18671
93204d3a 18672 free (map);
47b2e99c 18673 arm_data->mapcount = -1;
c7b8f16e 18674 arm_data->mapsize = 0;
8e3de13a 18675 arm_data->map = NULL;
8e3de13a 18676
e489d0ae
PB		 18677 return FALSE;
18678}
18679
0beaef2b
PB		 18680/* Mangle thumb function symbols as we read them in. */
18681
8384fb8f 18682static bfd_boolean
0beaef2b
PB		 18683elf32_arm_swap_symbol_in (bfd * abfd,
18684 const void *psrc,
18685 const void *pshn,
18686 Elf_Internal_Sym *dst)
18687{
4ba2ef8f
TP		 18688 Elf_Internal_Shdr *symtab_hdr;
18689 const char *name = NULL;
18690
8384fb8f
AM		 18691 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
18692 return FALSE;
39d911fc 18693 dst->st_target_internal = 0;
0beaef2b
PB		 18694
18695 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 18696 the address. */
63e1a0fc
PB		 18697 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
18698 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 18699 {
63e1a0fc
PB		 18700 if (dst->st_value & 1)
18701 {
18702 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 18703 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
18704 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 18705 }
18706 else
39d911fc 18707 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 18708 }
18709 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
18710 {
18711 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 18712 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 18713 }
35fc36a8 18714 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 18715 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 18716 else
39d911fc 18717 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 18718
4ba2ef8f
TP		 18719 /* Mark CMSE special symbols. */
18720 symtab_hdr = & elf_symtab_hdr (abfd);
18721 if (symtab_hdr->sh_size)
18722 name = bfd_elf_sym_name (abfd, symtab_hdr, dst, NULL);
18723 if (name && CONST_STRNEQ (name, CMSE_PREFIX))
18724 ARM_SET_SYM_CMSE_SPCL (dst->st_target_internal);
18725
8384fb8f 18726 return TRUE;
0beaef2b
PB		 18727}
18728
18729
18730/* Mangle thumb function symbols as we write them out. */
18731
18732static void
18733elf32_arm_swap_symbol_out (bfd *abfd,
18734 const Elf_Internal_Sym *src,
18735 void *cdst,
18736 void *shndx)
18737{
18738 Elf_Internal_Sym newsym;
18739
18740 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
18741 of the address set, as per the new EABI. We do this unconditionally
18742 because objcopy does not set the elf header flags until after
18743 it writes out the symbol table. */
39d911fc 18744 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 18745 {
18746 newsym = *src;
34e77a92
RS		 18747 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
18748 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 18749 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 18750 {
18751 /* Do this only for defined symbols. At link type, the static
18752 linker will simulate the work of dynamic linker of resolving
18753 symbols and will carry over the thumbness of found symbols to
18754 the output symbol table. It's not clear how it happens, but
18755 the thumbness of undefined symbols can well be different at
18756 runtime, and writing '1' for them will be confusing for users
18757 and possibly for dynamic linker itself.
18758 */
18759 newsym.st_value |= 1;
18760 }
906e58ca 18761
0beaef2b
PB		 18762 src = &newsym;
18763 }
18764 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
18765}
18766
b294bdf8
MM		 18767/* Add the PT_ARM_EXIDX program header. */
18768
18769static bfd_boolean
906e58ca 18770elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 18771 struct bfd_link_info *info ATTRIBUTE_UNUSED)
18772{
18773 struct elf_segment_map *m;
18774 asection *sec;
18775
18776 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18777 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18778 {
18779 /* If there is already a PT_ARM_EXIDX header, then we do not
18780 want to add another one. This situation arises when running
18781 "strip"; the input binary already has the header. */
12bd6957 18782 m = elf_seg_map (abfd);
b294bdf8
MM		 18783 while (m && m->p_type != PT_ARM_EXIDX)
18784 m = m->next;
18785 if (!m)
18786 {
21d799b5 18787 m = (struct elf_segment_map *)
99059e56 18788 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 18789 if (m == NULL)
18790 return FALSE;
18791 m->p_type = PT_ARM_EXIDX;
18792 m->count = 1;
18793 m->sections[0] = sec;
18794
12bd6957
AM		 18795 m->next = elf_seg_map (abfd);
18796 elf_seg_map (abfd) = m;
b294bdf8
MM		 18797 }
18798 }
18799
18800 return TRUE;
18801}
18802
18803/* We may add a PT_ARM_EXIDX program header. */
18804
18805static int
a6b96beb
AM		 18806elf32_arm_additional_program_headers (bfd *abfd,
18807 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 18808{
18809 asection *sec;
18810
18811 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18812 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18813 return 1;
18814 else
18815 return 0;
18816}
18817
34e77a92
RS		 18818/* Hook called by the linker routine which adds symbols from an object
18819 file. */
18820
18821static bfd_boolean
18822elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
18823 Elf_Internal_Sym *sym, const char **namep,
18824 flagword *flagsp, asection **secp, bfd_vma *valp)
18825{
a43942db 18826 if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
f1885d1e
AM		 18827 && (abfd->flags & DYNAMIC) == 0
18828 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
a43942db 18829 elf_tdata (info->output_bfd)->has_gnu_symbols |= elf_gnu_symbol_ifunc;
34e77a92 18830
c792917c
NC		 18831 if (elf32_arm_hash_table (info) == NULL)
18832 return FALSE;
18833
34e77a92
RS		 18834 if (elf32_arm_hash_table (info)->vxworks_p
18835 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
18836 flagsp, secp, valp))
18837 return FALSE;
18838
18839 return TRUE;
18840}
18841
0beaef2b 18842/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 18843const struct elf_size_info elf32_arm_size_info =
18844{
0beaef2b
PB		 18845 sizeof (Elf32_External_Ehdr),
18846 sizeof (Elf32_External_Phdr),
18847 sizeof (Elf32_External_Shdr),
18848 sizeof (Elf32_External_Rel),
18849 sizeof (Elf32_External_Rela),
18850 sizeof (Elf32_External_Sym),
18851 sizeof (Elf32_External_Dyn),
18852 sizeof (Elf_External_Note),
18853 4,
18854 1,
18855 32, 2,
18856 ELFCLASS32, EV_CURRENT,
18857 bfd_elf32_write_out_phdrs,
18858 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 18859 bfd_elf32_checksum_contents,
0beaef2b
PB		 18860 bfd_elf32_write_relocs,
18861 elf32_arm_swap_symbol_in,
18862 elf32_arm_swap_symbol_out,
18863 bfd_elf32_slurp_reloc_table,
18864 bfd_elf32_slurp_symbol_table,
18865 bfd_elf32_swap_dyn_in,
18866 bfd_elf32_swap_dyn_out,
18867 bfd_elf32_swap_reloc_in,
18868 bfd_elf32_swap_reloc_out,
18869 bfd_elf32_swap_reloca_in,
18870 bfd_elf32_swap_reloca_out
18871};
18872
685e70ae
VK		 18873static bfd_vma
18874read_code32 (const bfd *abfd, const bfd_byte *addr)
18875{
18876 /* V7 BE8 code is always little endian. */
18877 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18878 return bfd_getl32 (addr);
18879
18880 return bfd_get_32 (abfd, addr);
18881}
18882
18883static bfd_vma
18884read_code16 (const bfd *abfd, const bfd_byte *addr)
18885{
18886 /* V7 BE8 code is always little endian. */
18887 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18888 return bfd_getl16 (addr);
18889
18890 return bfd_get_16 (abfd, addr);
18891}
18892
6a631e86
YG		 18893/* Return size of plt0 entry starting at ADDR
18894 or (bfd_vma) -1 if size can not be determined. */
18895
18896static bfd_vma
18897elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
18898{
18899 bfd_vma first_word;
18900 bfd_vma plt0_size;
18901
685e70ae 18902 first_word = read_code32 (abfd, addr);
6a631e86
YG		 18903
18904 if (first_word == elf32_arm_plt0_entry[0])
18905 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
18906 else if (first_word == elf32_thumb2_plt0_entry[0])
18907 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
18908 else
18909 /* We don't yet handle this PLT format. */
18910 return (bfd_vma) -1;
18911
18912 return plt0_size;
18913}
18914
18915/* Return size of plt entry starting at offset OFFSET
18916 of plt section located at address START
18917 or (bfd_vma) -1 if size can not be determined. */
18918
18919static bfd_vma
18920elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
18921{
18922 bfd_vma first_insn;
18923 bfd_vma plt_size = 0;
18924 const bfd_byte *addr = start + offset;
18925
18926 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 18927 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 18928 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
18929
18930 /* Respect Thumb stub if necessary. */
685e70ae 18931 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 18932 {
18933 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
18934 }
18935
18936 /* Strip immediate from first add. */
685e70ae 18937 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 18938
18939#ifdef FOUR_WORD_PLT
18940 if (first_insn == elf32_arm_plt_entry[0])
18941 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
18942#else
18943 if (first_insn == elf32_arm_plt_entry_long[0])
18944 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
18945 else if (first_insn == elf32_arm_plt_entry_short[0])
18946 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
18947#endif
18948 else
18949 /* We don't yet handle this PLT format. */
18950 return (bfd_vma) -1;
18951
18952 return plt_size;
18953}
18954
18955/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
18956
18957static long
18958elf32_arm_get_synthetic_symtab (bfd *abfd,
18959 long symcount ATTRIBUTE_UNUSED,
18960 asymbol **syms ATTRIBUTE_UNUSED,
18961 long dynsymcount,
18962 asymbol **dynsyms,
18963 asymbol **ret)
18964{
18965 asection *relplt;
18966 asymbol *s;
18967 arelent *p;
18968 long count, i, n;
18969 size_t size;
18970 Elf_Internal_Shdr *hdr;
18971 char *names;
18972 asection *plt;
18973 bfd_vma offset;
18974 bfd_byte *data;
18975
18976 *ret = NULL;
18977
18978 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
18979 return 0;
18980
18981 if (dynsymcount <= 0)
18982 return 0;
18983
18984 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
18985 if (relplt == NULL)
18986 return 0;
18987
18988 hdr = &elf_section_data (relplt)->this_hdr;
18989 if (hdr->sh_link != elf_dynsymtab (abfd)
18990 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
18991 return 0;
18992
18993 plt = bfd_get_section_by_name (abfd, ".plt");
18994 if (plt == NULL)
18995 return 0;
18996
18997 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
18998 return -1;
18999
19000 data = plt->contents;
19001 if (data == NULL)
19002 {
19003 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
19004 return -1;
19005 bfd_cache_section_contents((asection *) plt, data);
19006 }
19007
19008 count = relplt->size / hdr->sh_entsize;
19009 size = count * sizeof (asymbol);
19010 p = relplt->relocation;
19011 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19012 {
19013 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
19014 if (p->addend != 0)
19015 size += sizeof ("+0x") - 1 + 8;
19016 }
19017
19018 s = *ret = (asymbol *) bfd_malloc (size);
19019 if (s == NULL)
19020 return -1;
19021
19022 offset = elf32_arm_plt0_size (abfd, data);
19023 if (offset == (bfd_vma) -1)
19024 return -1;
19025
19026 names = (char *) (s + count);
19027 p = relplt->relocation;
19028 n = 0;
19029 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19030 {
19031 size_t len;
19032
19033 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
19034 if (plt_size == (bfd_vma) -1)
19035 break;
19036
19037 *s = **p->sym_ptr_ptr;
19038 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
19039 we are defining a symbol, ensure one of them is set. */
19040 if ((s->flags & BSF_LOCAL) == 0)
19041 s->flags |= BSF_GLOBAL;
19042 s->flags |= BSF_SYNTHETIC;
19043 s->section = plt;
19044 s->value = offset;
19045 s->name = names;
19046 s->udata.p = NULL;
19047 len = strlen ((*p->sym_ptr_ptr)->name);
19048 memcpy (names, (*p->sym_ptr_ptr)->name, len);
19049 names += len;
19050 if (p->addend != 0)
19051 {
19052 char buf[30], *a;
19053
19054 memcpy (names, "+0x", sizeof ("+0x") - 1);
19055 names += sizeof ("+0x") - 1;
19056 bfd_sprintf_vma (abfd, buf, p->addend);
19057 for (a = buf; *a == '0'; ++a)
19058 ;
19059 len = strlen (a);
19060 memcpy (names, a, len);
19061 names += len;
19062 }
19063 memcpy (names, "@plt", sizeof ("@plt"));
19064 names += sizeof ("@plt");
19065 ++s, ++n;
19066 offset += plt_size;
19067 }
19068
19069 return n;
19070}
19071
ac4c9b04
MG		 19072static bfd_boolean
19073elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
19074{
f0728ee3
AV		 19075 if (hdr->sh_flags & SHF_ARM_PURECODE)
19076 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 19077 return TRUE;
19078}
19079
19080static flagword
19081elf32_arm_lookup_section_flags (char *flag_name)
19082{
f0728ee3
AV		 19083 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
19084 return SHF_ARM_PURECODE;
ac4c9b04
MG		 19085
19086 return SEC_NO_FLAGS;
19087}
19088
491d01d3
YU		 19089static unsigned int
19090elf32_arm_count_additional_relocs (asection *sec)
19091{
19092 struct _arm_elf_section_data *arm_data;
19093 arm_data = get_arm_elf_section_data (sec);
5025eb7c 19094
6342be70 19095 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 19096}
19097
5522f910 19098/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 19099 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 19100 FALSE otherwise. ISECTION is the best guess matching section from the
19101 input bfd IBFD, but it might be NULL. */
19102
19103static bfd_boolean
19104elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
19105 bfd *obfd ATTRIBUTE_UNUSED,
19106 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
19107 Elf_Internal_Shdr *osection)
19108{
19109 switch (osection->sh_type)
19110 {
19111 case SHT_ARM_EXIDX:
19112 {
19113 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
19114 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
19115 unsigned i = 0;
19116
19117 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
19118 osection->sh_info = 0;
19119
19120 /* The sh_link field must be set to the text section associated with
19121 this index section. Unfortunately the ARM EHABI does not specify
19122 exactly how to determine this association. Our caller does try
19123 to match up OSECTION with its corresponding input section however
19124 so that is a good first guess. */
19125 if (isection != NULL
19126 && osection->bfd_section != NULL
19127 && isection->bfd_section != NULL
19128 && isection->bfd_section->output_section != NULL
19129 && isection->bfd_section->output_section == osection->bfd_section
19130 && iheaders != NULL
19131 && isection->sh_link > 0
19132 && isection->sh_link < elf_numsections (ibfd)
19133 && iheaders[isection->sh_link]->bfd_section != NULL
19134 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
19135 )
19136 {
19137 for (i = elf_numsections (obfd); i-- > 0;)
19138 if (oheaders[i]->bfd_section
19139 == iheaders[isection->sh_link]->bfd_section->output_section)
19140 break;
19141 }
9eaff861 19142
5522f910
NC		 19143 if (i == 0)
19144 {
19145 /* Failing that we have to find a matching section ourselves. If
19146 we had the output section name available we could compare that
19147 with input section names. Unfortunately we don't. So instead
19148 we use a simple heuristic and look for the nearest executable
19149 section before this one. */
19150 for (i = elf_numsections (obfd); i-- > 0;)
19151 if (oheaders[i] == osection)
19152 break;
19153 if (i == 0)
19154 break;
19155
19156 while (i-- > 0)
19157 if (oheaders[i]->sh_type == SHT_PROGBITS
19158 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
19159 == (SHF_ALLOC | SHF_EXECINSTR))
19160 break;
19161 }
19162
19163 if (i)
19164 {
19165 osection->sh_link = i;
19166 /* If the text section was part of a group
19167 then the index section should be too. */
19168 if (oheaders[i]->sh_flags & SHF_GROUP)
19169 osection->sh_flags |= SHF_GROUP;
19170 return TRUE;
19171 }
19172 }
19173 break;
19174
19175 case SHT_ARM_PREEMPTMAP:
19176 osection->sh_flags = SHF_ALLOC;
19177 break;
19178
19179 case SHT_ARM_ATTRIBUTES:
19180 case SHT_ARM_DEBUGOVERLAY:
19181 case SHT_ARM_OVERLAYSECTION:
19182 default:
19183 break;
19184 }
19185
19186 return FALSE;
19187}
19188
d691934d
NC		 19189/* Returns TRUE if NAME is an ARM mapping symbol.
19190 Traditionally the symbols $a, $d and $t have been used.
19191 The ARM ELF standard also defines $x (for A64 code). It also allows a
19192 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
19193 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
19194 not support them here. $t.x indicates the start of ThumbEE instructions. */
19195
19196static bfd_boolean
19197is_arm_mapping_symbol (const char * name)
19198{
19199 return name != NULL /* Paranoia. */
19200 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
19201 the mapping symbols could have acquired a prefix.
19202 We do not support this here, since such symbols no
19203 longer conform to the ARM ELF ABI. */
19204 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
19205 && (name[2] == 0 || name[2] == '.');
19206 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
19207 any characters that follow the period are legal characters for the body
19208 of a symbol's name. For now we just assume that this is the case. */
19209}
19210
fca2a38f
NC		 19211/* Make sure that mapping symbols in object files are not removed via the
19212 "strip --strip-unneeded" tool. These symbols are needed in order to
19213 correctly generate interworking veneers, and for byte swapping code
19214 regions. Once an object file has been linked, it is safe to remove the
19215 symbols as they will no longer be needed. */
19216
19217static void
19218elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
19219{
19220 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 19221 && sym->section != bfd_abs_section_ptr
d691934d 19222 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 19223 sym->flags |= BSF_KEEP;
19224}
19225
5522f910
NC		 19226#undef elf_backend_copy_special_section_fields
19227#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
19228
252b5132 19229#define ELF_ARCH bfd_arch_arm
ae95ffa6 19230#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 19231#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 19232#ifdef __QNXTARGET__
19233#define ELF_MAXPAGESIZE 0x1000
19234#else
7572ca89 19235#define ELF_MAXPAGESIZE 0x10000
d0facd1b 19236#endif
b1342370 19237#define ELF_MINPAGESIZE 0x1000
24718e3b 19238#define ELF_COMMONPAGESIZE 0x1000
252b5132 19239
07d6d2b8 19240#define bfd_elf32_mkobject elf32_arm_mkobject
ba93b8ac 19241
99e4ae17
AJ		 19242#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
19243#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 19244#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
19245#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
07d6d2b8 19246#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 19247#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 19248#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
07d6d2b8
AM		 19249#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
19250#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 19251#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 19252#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 19253#define bfd_elf32_bfd_final_link elf32_arm_final_link
07d6d2b8 19254#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132 19255
07d6d2b8
AM		 19256#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
19257#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 19258#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
07d6d2b8 19259#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 19260#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 19261#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 19262#define elf_backend_write_section elf32_arm_write_section
252b5132 19263#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
07d6d2b8 19264#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 19265#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
19266#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
19267#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 19268#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 19269#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 19270#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 19271#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 19272#define elf_backend_object_p elf32_arm_object_p
07d6d2b8
AM		 19273#define elf_backend_fake_sections elf32_arm_fake_sections
19274#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
19275#define elf_backend_final_write_processing elf32_arm_final_write_processing
19276#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 19277#define elf_backend_size_info elf32_arm_size_info
b294bdf8 19278#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
07d6d2b8
AM		 19279#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
19280#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 19281#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
07d6d2b8 19282#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 19283#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 19284#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 19285#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 19286
19287#define elf_backend_can_refcount 1
19288#define elf_backend_can_gc_sections 1
19289#define elf_backend_plt_readonly 1
19290#define elf_backend_want_got_plt 1
19291#define elf_backend_want_plt_sym 0
5474d94f 19292#define elf_backend_want_dynrelro 1
906e58ca
NC		 19293#define elf_backend_may_use_rel_p 1
19294#define elf_backend_may_use_rela_p 0
4e7fd91e 19295#define elf_backend_default_use_rela_p 0
64f52338 19296#define elf_backend_dtrel_excludes_plt 1
252b5132 19297
04f7c78d 19298#define elf_backend_got_header_size 12
b68a20d6 19299#define elf_backend_extern_protected_data 1
04f7c78d 19300
07d6d2b8 19301#undef elf_backend_obj_attrs_vendor
906e58ca 19302#define elf_backend_obj_attrs_vendor "aeabi"
07d6d2b8 19303#undef elf_backend_obj_attrs_section
906e58ca 19304#define elf_backend_obj_attrs_section ".ARM.attributes"
07d6d2b8 19305#undef elf_backend_obj_attrs_arg_type
906e58ca 19306#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
07d6d2b8 19307#undef elf_backend_obj_attrs_section_type
104d59d1 19308#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb 19309#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
07d6d2b8 19310#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 19311
07d6d2b8 19312#undef elf_backend_section_flags
ac4c9b04 19313#define elf_backend_section_flags elf32_arm_section_flags
07d6d2b8
AM		 19314#undef elf_backend_lookup_section_flags_hook
19315#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
ac4c9b04 19316
a2f63b2e
MR		 19317#define elf_backend_linux_prpsinfo32_ugid16 TRUE
19318
252b5132 19319#include "elf32-target.h"
7f266840 19320
b38cadfb
NC		 19321/* Native Client targets. */
19322
19323#undef TARGET_LITTLE_SYM
6d00b590 19324#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 19325#undef TARGET_LITTLE_NAME
19326#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
19327#undef TARGET_BIG_SYM
6d00b590 19328#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 19329#undef TARGET_BIG_NAME
19330#define TARGET_BIG_NAME "elf32-bigarm-nacl"
19331
19332/* Like elf32_arm_link_hash_table_create -- but overrides
19333 appropriately for NaCl. */
19334
19335static struct bfd_link_hash_table *
19336elf32_arm_nacl_link_hash_table_create (bfd *abfd)
19337{
19338 struct bfd_link_hash_table *ret;
19339
19340 ret = elf32_arm_link_hash_table_create (abfd);
19341 if (ret)
19342 {
19343 struct elf32_arm_link_hash_table *htab
19344 = (struct elf32_arm_link_hash_table *) ret;
19345
19346 htab->nacl_p = 1;
19347
19348 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
19349 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
19350 }
19351 return ret;
19352}
19353
19354/* Since NaCl doesn't use the ARM-specific unwind format, we don't
19355 really need to use elf32_arm_modify_segment_map. But we do it
19356 anyway just to reduce gratuitous differences with the stock ARM backend. */
19357
19358static bfd_boolean
19359elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
19360{
19361 return (elf32_arm_modify_segment_map (abfd, info)
19362 && nacl_modify_segment_map (abfd, info));
19363}
19364
887badb3
RM		 19365static void
19366elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
19367{
19368 elf32_arm_final_write_processing (abfd, linker);
19369 nacl_final_write_processing (abfd, linker);
19370}
19371
6a631e86
YG		 19372static bfd_vma
19373elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
19374 const arelent *rel ATTRIBUTE_UNUSED)
19375{
19376 return plt->vma
19377 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
19378 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
19379}
887badb3 19380
b38cadfb 19381#undef elf32_bed
6a631e86 19382#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 19383#undef bfd_elf32_bfd_link_hash_table_create
19384#define bfd_elf32_bfd_link_hash_table_create \
19385 elf32_arm_nacl_link_hash_table_create
19386#undef elf_backend_plt_alignment
6a631e86 19387#define elf_backend_plt_alignment 4
b38cadfb
NC		 19388#undef elf_backend_modify_segment_map
19389#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
19390#undef elf_backend_modify_program_headers
19391#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 19392#undef elf_backend_final_write_processing
19393#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 19394#undef bfd_elf32_get_synthetic_symtab
19395#undef elf_backend_plt_sym_val
19396#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 19397#undef elf_backend_copy_special_section_fields
b38cadfb 19398
887badb3
RM		 19399#undef ELF_MINPAGESIZE
19400#undef ELF_COMMONPAGESIZE
19401
b38cadfb
NC		 19402
19403#include "elf32-target.h"
19404
19405/* Reset to defaults. */
19406#undef elf_backend_plt_alignment
19407#undef elf_backend_modify_segment_map
19408#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
19409#undef elf_backend_modify_program_headers
887badb3
RM		 19410#undef elf_backend_final_write_processing
19411#define elf_backend_final_write_processing elf32_arm_final_write_processing
19412#undef ELF_MINPAGESIZE
19413#define ELF_MINPAGESIZE 0x1000
19414#undef ELF_COMMONPAGESIZE
19415#define ELF_COMMONPAGESIZE 0x1000
19416
b38cadfb 19417
617a5ada
CL		 19418/* FDPIC Targets. */
19419
19420#undef TARGET_LITTLE_SYM
19421#define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
19422#undef TARGET_LITTLE_NAME
19423#define TARGET_LITTLE_NAME "elf32-littlearm-fdpic"
19424#undef TARGET_BIG_SYM
19425#define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
19426#undef TARGET_BIG_NAME
19427#define TARGET_BIG_NAME "elf32-bigarm-fdpic"
19428#undef elf_match_priority
19429#define elf_match_priority 128
19430
19431/* Like elf32_arm_link_hash_table_create -- but overrides
19432 appropriately for FDPIC. */
19433
19434static struct bfd_link_hash_table *
19435elf32_arm_fdpic_link_hash_table_create (bfd *abfd)
19436{
19437 struct bfd_link_hash_table *ret;
19438
19439 ret = elf32_arm_link_hash_table_create (abfd);
19440 if (ret)
19441 {
19442 struct elf32_arm_link_hash_table *htab = (struct elf32_arm_link_hash_table *) ret;
19443
19444 htab->fdpic_p = 1;
19445 }
19446 return ret;
19447}
19448
19449#undef elf32_bed
19450#define elf32_bed elf32_arm_fdpic_bed
19451
19452#undef bfd_elf32_bfd_link_hash_table_create
19453#define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
19454
19455#include "elf32-target.h"
19456#undef elf_match_priority
19457
906e58ca 19458/* VxWorks Targets. */
4e7fd91e 19459
07d6d2b8
AM		 19460#undef TARGET_LITTLE_SYM
19461#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
19462#undef TARGET_LITTLE_NAME
19463#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
19464#undef TARGET_BIG_SYM
19465#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
19466#undef TARGET_BIG_NAME
19467#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
4e7fd91e
PB		 19468
19469/* Like elf32_arm_link_hash_table_create -- but overrides
19470 appropriately for VxWorks. */
906e58ca 19471
4e7fd91e
PB		 19472static struct bfd_link_hash_table *
19473elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
19474{
19475 struct bfd_link_hash_table *ret;
19476
19477 ret = elf32_arm_link_hash_table_create (abfd);
19478 if (ret)
19479 {
19480 struct elf32_arm_link_hash_table *htab
00a97672 19481 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 19482 htab->use_rel = 0;
00a97672 19483 htab->vxworks_p = 1;
4e7fd91e
PB		 19484 }
19485 return ret;
906e58ca 19486}
4e7fd91e 19487
00a97672
RS		 19488static void
19489elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
19490{
19491 elf32_arm_final_write_processing (abfd, linker);
19492 elf_vxworks_final_write_processing (abfd, linker);
19493}
19494
906e58ca 19495#undef elf32_bed
4e7fd91e
PB		 19496#define elf32_bed elf32_arm_vxworks_bed
19497
906e58ca
NC		 19498#undef bfd_elf32_bfd_link_hash_table_create
19499#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 19500#undef elf_backend_final_write_processing
19501#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
19502#undef elf_backend_emit_relocs
9eaff861 19503#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 19504
906e58ca 19505#undef elf_backend_may_use_rel_p
00a97672 19506#define elf_backend_may_use_rel_p 0
906e58ca 19507#undef elf_backend_may_use_rela_p
00a97672 19508#define elf_backend_may_use_rela_p 1
906e58ca 19509#undef elf_backend_default_use_rela_p
00a97672 19510#define elf_backend_default_use_rela_p 1
906e58ca 19511#undef elf_backend_want_plt_sym
00a97672 19512#define elf_backend_want_plt_sym 1
906e58ca 19513#undef ELF_MAXPAGESIZE
00a97672 19514#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 19515
19516#include "elf32-target.h"
19517
19518
21d799b5
NC		 19519/* Merge backend specific data from an object file to the output
19520 object file when linking. */
19521
19522static bfd_boolean
50e03d47 19523elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 19524{
50e03d47 19525 bfd *obfd = info->output_bfd;
21d799b5
NC		 19526 flagword out_flags;
19527 flagword in_flags;
19528 bfd_boolean flags_compatible = TRUE;
19529 asection *sec;
19530
cc643b88 19531 /* Check if we have the same endianness. */
50e03d47 19532 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 19533 return FALSE;
19534
19535 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
19536 return TRUE;
19537
50e03d47 19538 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 19539 return FALSE;
19540
19541 /* The input BFD must have had its flags initialised. */
19542 /* The following seems bogus to me -- The flags are initialized in
19543 the assembler but I don't think an elf_flags_init field is
19544 written into the object. */
19545 /* BFD_ASSERT (elf_flags_init (ibfd)); */
19546
19547 in_flags = elf_elfheader (ibfd)->e_flags;
19548 out_flags = elf_elfheader (obfd)->e_flags;
19549
19550 /* In theory there is no reason why we couldn't handle this. However
19551 in practice it isn't even close to working and there is no real
19552 reason to want it. */
19553 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
19554 && !(ibfd->flags & DYNAMIC)
19555 && (in_flags & EF_ARM_BE8))
19556 {
871b3ab2 19557 _bfd_error_handler (_("error: %pB is already in final BE8 format"),
21d799b5
NC		 19558 ibfd);
19559 return FALSE;
19560 }
19561
19562 if (!elf_flags_init (obfd))
19563 {
19564 /* If the input is the default architecture and had the default
19565 flags then do not bother setting the flags for the output
19566 architecture, instead allow future merges to do this. If no
19567 future merges ever set these flags then they will retain their
99059e56
RM		 19568 uninitialised values, which surprise surprise, correspond
19569 to the default values. */
21d799b5
NC		 19570 if (bfd_get_arch_info (ibfd)->the_default
19571 && elf_elfheader (ibfd)->e_flags == 0)
19572 return TRUE;
19573
19574 elf_flags_init (obfd) = TRUE;
19575 elf_elfheader (obfd)->e_flags = in_flags;
19576
19577 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
19578 && bfd_get_arch_info (obfd)->the_default)
19579 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
19580
19581 return TRUE;
19582 }
19583
19584 /* Determine what should happen if the input ARM architecture
19585 does not match the output ARM architecture. */
19586 if (! bfd_arm_merge_machines (ibfd, obfd))
19587 return FALSE;
19588
19589 /* Identical flags must be compatible. */
19590 if (in_flags == out_flags)
19591 return TRUE;
19592
19593 /* Check to see if the input BFD actually contains any sections. If
19594 not, its flags may not have been initialised either, but it
19595 cannot actually cause any incompatiblity. Do not short-circuit
19596 dynamic objects; their section list may be emptied by
19597 elf_link_add_object_symbols.
19598
19599 Also check to see if there are no code sections in the input.
19600 In this case there is no need to check for code specific flags.
19601 XXX - do we need to worry about floating-point format compatability
19602 in data sections ? */
19603 if (!(ibfd->flags & DYNAMIC))
19604 {
19605 bfd_boolean null_input_bfd = TRUE;
19606 bfd_boolean only_data_sections = TRUE;
19607
19608 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
19609 {
19610 /* Ignore synthetic glue sections. */
19611 if (strcmp (sec->name, ".glue_7")
19612 && strcmp (sec->name, ".glue_7t"))
19613 {
19614 if ((bfd_get_section_flags (ibfd, sec)
19615 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
19616 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 19617 only_data_sections = FALSE;
21d799b5
NC		 19618
19619 null_input_bfd = FALSE;
19620 break;
19621 }
19622 }
19623
19624 if (null_input_bfd || only_data_sections)
19625 return TRUE;
19626 }
19627
19628 /* Complain about various flag mismatches. */
19629 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
19630 EF_ARM_EABI_VERSION (out_flags)))
19631 {
19632 _bfd_error_handler
90b6238f 19633 (_("error: source object %pB has EABI version %d, but target %pB has EABI version %d"),
c08bb8dd
AM		 19634 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
19635 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 19636 return FALSE;
19637 }
19638
19639 /* Not sure what needs to be checked for EABI versions >= 1. */
19640 /* VxWorks libraries do not use these flags. */
19641 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
19642 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
19643 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
19644 {
19645 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
19646 {
19647 _bfd_error_handler
871b3ab2 19648 (_("error: %pB is compiled for APCS-%d, whereas target %pB uses APCS-%d"),
c08bb8dd
AM		 19649 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
19650 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 19651 flags_compatible = FALSE;
19652 }
19653
19654 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
19655 {
19656 if (in_flags & EF_ARM_APCS_FLOAT)
19657 _bfd_error_handler
871b3ab2 19658 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
21d799b5
NC		 19659 ibfd, obfd);
19660 else
19661 _bfd_error_handler
871b3ab2 19662 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
21d799b5
NC		 19663 ibfd, obfd);
19664
19665 flags_compatible = FALSE;
19666 }
19667
19668 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
19669 {
19670 if (in_flags & EF_ARM_VFP_FLOAT)
19671 _bfd_error_handler
90b6238f
AM		 19672 (_("error: %pB uses %s instructions, whereas %pB does not"),
19673 ibfd, "VFP", obfd);
21d799b5
NC		 19674 else
19675 _bfd_error_handler
90b6238f
AM		 19676 (_("error: %pB uses %s instructions, whereas %pB does not"),
19677 ibfd, "FPA", obfd);
21d799b5
NC		 19678
19679 flags_compatible = FALSE;
19680 }
19681
19682 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
19683 {
19684 if (in_flags & EF_ARM_MAVERICK_FLOAT)
19685 _bfd_error_handler
90b6238f
AM		 19686 (_("error: %pB uses %s instructions, whereas %pB does not"),
19687 ibfd, "Maverick", obfd);
21d799b5
NC		 19688 else
19689 _bfd_error_handler
90b6238f
AM		 19690 (_("error: %pB does not use %s instructions, whereas %pB does"),
19691 ibfd, "Maverick", obfd);
21d799b5
NC		 19692
19693 flags_compatible = FALSE;
19694 }
19695
19696#ifdef EF_ARM_SOFT_FLOAT
19697 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
19698 {
19699 /* We can allow interworking between code that is VFP format
19700 layout, and uses either soft float or integer regs for
19701 passing floating point arguments and results. We already
19702 know that the APCS_FLOAT flags match; similarly for VFP
19703 flags. */
19704 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
19705 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
19706 {
19707 if (in_flags & EF_ARM_SOFT_FLOAT)
19708 _bfd_error_handler
871b3ab2 19709 (_("error: %pB uses software FP, whereas %pB uses hardware FP"),
21d799b5
NC		 19710 ibfd, obfd);
19711 else
19712 _bfd_error_handler
871b3ab2 19713 (_("error: %pB uses hardware FP, whereas %pB uses software FP"),
21d799b5
NC		 19714 ibfd, obfd);
19715
19716 flags_compatible = FALSE;
19717 }
19718 }
19719#endif
19720
19721 /* Interworking mismatch is only a warning. */
19722 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
19723 {
19724 if (in_flags & EF_ARM_INTERWORK)
19725 {
19726 _bfd_error_handler
90b6238f 19727 (_("warning: %pB supports interworking, whereas %pB does not"),
21d799b5
NC		 19728 ibfd, obfd);
19729 }
19730 else
19731 {
19732 _bfd_error_handler
90b6238f 19733 (_("warning: %pB does not support interworking, whereas %pB does"),
21d799b5
NC		 19734 ibfd, obfd);
19735 }
19736 }
19737 }
19738
19739 return flags_compatible;
19740}
19741
19742
906e58ca 19743/* Symbian OS Targets. */
7f266840 19744
07d6d2b8
AM		 19745#undef TARGET_LITTLE_SYM
19746#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
19747#undef TARGET_LITTLE_NAME
19748#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
19749#undef TARGET_BIG_SYM
19750#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
19751#undef TARGET_BIG_NAME
19752#define TARGET_BIG_NAME "elf32-bigarm-symbian"
7f266840
DJ		 19753
19754/* Like elf32_arm_link_hash_table_create -- but overrides
19755 appropriately for Symbian OS. */
906e58ca 19756
7f266840
DJ		 19757static struct bfd_link_hash_table *
19758elf32_arm_symbian_link_hash_table_create (bfd *abfd)
19759{
19760 struct bfd_link_hash_table *ret;
19761
19762 ret = elf32_arm_link_hash_table_create (abfd);
19763 if (ret)
19764 {
19765 struct elf32_arm_link_hash_table *htab
19766 = (struct elf32_arm_link_hash_table *)ret;
19767 /* There is no PLT header for Symbian OS. */
19768 htab->plt_header_size = 0;
95720a86
DJ		 19769 /* The PLT entries are each one instruction and one word. */
19770 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 19771 htab->symbian_p = 1;
33bfe774
JB		 19772 /* Symbian uses armv5t or above, so use_blx is always true. */
19773 htab->use_blx = 1;
67687978 19774 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 19775 }
19776 return ret;
906e58ca 19777}
7f266840 19778
b35d266b 19779static const struct bfd_elf_special_section
551b43fd 19780elf32_arm_symbian_special_sections[] =
7f266840 19781{
5cd3778d
MM		 19782 /* In a BPABI executable, the dynamic linking sections do not go in
19783 the loadable read-only segment. The post-linker may wish to
19784 refer to these sections, but they are not part of the final
19785 program image. */
07d6d2b8
AM		 19786 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
19787 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
19788 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
19789 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
19790 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 19791 /* These sections do not need to be writable as the SymbianOS
19792 postlinker will arrange things so that no dynamic relocation is
19793 required. */
07d6d2b8
AM		 19794 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
19795 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
0112cd26 19796 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
07d6d2b8 19797 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 19798};
19799
c3c76620 19800static void
906e58ca 19801elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 19802 struct bfd_link_info *link_info)
c3c76620
MM		 19803{
19804 /* BPABI objects are never loaded directly by an OS kernel; they are
19805 processed by a postlinker first, into an OS-specific format. If
19806 the D_PAGED bit is set on the file, BFD will align segments on
19807 page boundaries, so that an OS can directly map the file. With
19808 BPABI objects, that just results in wasted space. In addition,
19809 because we clear the D_PAGED bit, map_sections_to_segments will
19810 recognize that the program headers should not be mapped into any
19811 loadable segment. */
19812 abfd->flags &= ~D_PAGED;
906e58ca 19813 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 19814}
7f266840
DJ		 19815
19816static bfd_boolean
906e58ca 19817elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 19818 struct bfd_link_info *info)
7f266840
DJ		 19819{
19820 struct elf_segment_map *m;
19821 asection *dynsec;
19822
7f266840
DJ		 19823 /* BPABI shared libraries and executables should have a PT_DYNAMIC
19824 segment. However, because the .dynamic section is not marked
19825 with SEC_LOAD, the generic ELF code will not create such a
19826 segment. */
19827 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
19828 if (dynsec)
19829 {
12bd6957 19830 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 19831 if (m->p_type == PT_DYNAMIC)
19832 break;
19833
19834 if (m == NULL)
19835 {
19836 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 19837 m->next = elf_seg_map (abfd);
19838 elf_seg_map (abfd) = m;
8ded5a0f 19839 }
7f266840
DJ		 19840 }
19841
b294bdf8
MM		 19842 /* Also call the generic arm routine. */
19843 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 19844}
19845
95720a86
DJ		 19846/* Return address for Ith PLT stub in section PLT, for relocation REL
19847 or (bfd_vma) -1 if it should not be included. */
19848
19849static bfd_vma
19850elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
19851 const arelent *rel ATTRIBUTE_UNUSED)
19852{
19853 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
19854}
19855
8029a119 19856#undef elf32_bed
7f266840
DJ		 19857#define elf32_bed elf32_arm_symbian_bed
19858
19859/* The dynamic sections are not allocated on SymbianOS; the postlinker
19860 will process them and then discard them. */
906e58ca 19861#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 19862#define ELF_DYNAMIC_SEC_FLAGS \
19863 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
19864
9eaff861 19865#undef elf_backend_emit_relocs
c3c76620 19866
906e58ca
NC		 19867#undef bfd_elf32_bfd_link_hash_table_create
19868#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
19869#undef elf_backend_special_sections
07d6d2b8 19870#define elf_backend_special_sections elf32_arm_symbian_special_sections
906e58ca
NC		 19871#undef elf_backend_begin_write_processing
19872#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
19873#undef elf_backend_final_write_processing
19874#define elf_backend_final_write_processing elf32_arm_final_write_processing
19875
19876#undef elf_backend_modify_segment_map
7f266840
DJ		 19877#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
19878
19879/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 19880#undef elf_backend_got_header_size
7f266840
DJ		 19881#define elf_backend_got_header_size 0
19882
19883/* Similarly, there is no .got.plt section. */
906e58ca 19884#undef elf_backend_want_got_plt
7f266840
DJ		 19885#define elf_backend_want_got_plt 0
19886
906e58ca 19887#undef elf_backend_plt_sym_val
95720a86
DJ		 19888#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
19889
906e58ca 19890#undef elf_backend_may_use_rel_p
00a97672 19891#define elf_backend_may_use_rel_p 1
906e58ca 19892#undef elf_backend_may_use_rela_p
00a97672 19893#define elf_backend_may_use_rela_p 0
906e58ca 19894#undef elf_backend_default_use_rela_p
00a97672 19895#define elf_backend_default_use_rela_p 0
906e58ca 19896#undef elf_backend_want_plt_sym
00a97672 19897#define elf_backend_want_plt_sym 0
64f52338
AM		 19898#undef elf_backend_dtrel_excludes_plt
19899#define elf_backend_dtrel_excludes_plt 0
906e58ca 19900#undef ELF_MAXPAGESIZE
00a97672 19901#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 19902
7f266840 19903#include "elf32-target.h"
GDB Binutils - Deliverables
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