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[binutils, ARM, 9/16] New BFL instruction for Armv8.1-M Mainline
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
82704155 2 Copyright (C) 1998-2019 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
00a97672 25#include "libiberty.h"
7f266840
DJ		 26#include "libbfd.h"
27#include "elf-bfd.h"
b38cadfb 28#include "elf-nacl.h"
00a97672 29#include "elf-vxworks.h"
ee065d83 30#include "elf/arm.h"
7f266840 31
00a97672
RS		 32/* Return the relocation section associated with NAME. HTAB is the
33 bfd's elf32_arm_link_hash_entry. */
34#define RELOC_SECTION(HTAB, NAME) \
35 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
36
37/* Return size of a relocation entry. HTAB is the bfd's
38 elf32_arm_link_hash_entry. */
39#define RELOC_SIZE(HTAB) \
40 ((HTAB)->use_rel \
41 ? sizeof (Elf32_External_Rel) \
42 : sizeof (Elf32_External_Rela))
43
44/* Return function to swap relocations in. HTAB is the bfd's
45 elf32_arm_link_hash_entry. */
46#define SWAP_RELOC_IN(HTAB) \
47 ((HTAB)->use_rel \
48 ? bfd_elf32_swap_reloc_in \
49 : bfd_elf32_swap_reloca_in)
50
51/* Return function to swap relocations out. HTAB is the bfd's
52 elf32_arm_link_hash_entry. */
53#define SWAP_RELOC_OUT(HTAB) \
54 ((HTAB)->use_rel \
55 ? bfd_elf32_swap_reloc_out \
56 : bfd_elf32_swap_reloca_out)
57
f3185997 58#define elf_info_to_howto NULL
07d6d2b8 59#define elf_info_to_howto_rel elf32_arm_info_to_howto
7f266840
DJ		 60
61#define ARM_ELF_ABI_VERSION 0
62#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
63
79f08007
YZ		 64/* The Adjusted Place, as defined by AAELF. */
65#define Pa(X) ((X) & 0xfffffffc)
66
3e6b1042
DJ		 67static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
68 struct bfd_link_info *link_info,
69 asection *sec,
70 bfd_byte *contents);
71
7f266840
DJ		 72/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
73 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
74 in that slot. */
75
c19d1205 76static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 77{
8029a119 78 /* No relocation. */
7f266840
DJ		 79 HOWTO (R_ARM_NONE, /* type */
80 0, /* rightshift */
6346d5ca 81 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 82 0, /* bitsize */
83 FALSE, /* pc_relative */
84 0, /* bitpos */
85 complain_overflow_dont,/* complain_on_overflow */
86 bfd_elf_generic_reloc, /* special_function */
87 "R_ARM_NONE", /* name */
88 FALSE, /* partial_inplace */
89 0, /* src_mask */
90 0, /* dst_mask */
91 FALSE), /* pcrel_offset */
92
93 HOWTO (R_ARM_PC24, /* type */
94 2, /* rightshift */
95 2, /* size (0 = byte, 1 = short, 2 = long) */
96 24, /* bitsize */
97 TRUE, /* pc_relative */
98 0, /* bitpos */
99 complain_overflow_signed,/* complain_on_overflow */
100 bfd_elf_generic_reloc, /* special_function */
101 "R_ARM_PC24", /* name */
102 FALSE, /* partial_inplace */
103 0x00ffffff, /* src_mask */
104 0x00ffffff, /* dst_mask */
105 TRUE), /* pcrel_offset */
106
107 /* 32 bit absolute */
108 HOWTO (R_ARM_ABS32, /* type */
109 0, /* rightshift */
110 2, /* size (0 = byte, 1 = short, 2 = long) */
111 32, /* bitsize */
112 FALSE, /* pc_relative */
113 0, /* bitpos */
114 complain_overflow_bitfield,/* complain_on_overflow */
115 bfd_elf_generic_reloc, /* special_function */
116 "R_ARM_ABS32", /* name */
117 FALSE, /* partial_inplace */
118 0xffffffff, /* src_mask */
119 0xffffffff, /* dst_mask */
120 FALSE), /* pcrel_offset */
121
122 /* standard 32bit pc-relative reloc */
123 HOWTO (R_ARM_REL32, /* type */
124 0, /* rightshift */
125 2, /* size (0 = byte, 1 = short, 2 = long) */
126 32, /* bitsize */
127 TRUE, /* pc_relative */
128 0, /* bitpos */
129 complain_overflow_bitfield,/* complain_on_overflow */
130 bfd_elf_generic_reloc, /* special_function */
131 "R_ARM_REL32", /* name */
132 FALSE, /* partial_inplace */
133 0xffffffff, /* src_mask */
134 0xffffffff, /* dst_mask */
135 TRUE), /* pcrel_offset */
136
c19d1205 137 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 138 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 139 0, /* rightshift */
140 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 141 32, /* bitsize */
142 TRUE, /* pc_relative */
7f266840 143 0, /* bitpos */
4962c51a 144 complain_overflow_dont,/* complain_on_overflow */
7f266840 145 bfd_elf_generic_reloc, /* special_function */
4962c51a 146 "R_ARM_LDR_PC_G0", /* name */
7f266840 147 FALSE, /* partial_inplace */
4962c51a
MS		 148 0xffffffff, /* src_mask */
149 0xffffffff, /* dst_mask */
150 TRUE), /* pcrel_offset */
7f266840
DJ		 151
152 /* 16 bit absolute */
153 HOWTO (R_ARM_ABS16, /* type */
154 0, /* rightshift */
155 1, /* size (0 = byte, 1 = short, 2 = long) */
156 16, /* bitsize */
157 FALSE, /* pc_relative */
158 0, /* bitpos */
159 complain_overflow_bitfield,/* complain_on_overflow */
160 bfd_elf_generic_reloc, /* special_function */
161 "R_ARM_ABS16", /* name */
162 FALSE, /* partial_inplace */
163 0x0000ffff, /* src_mask */
164 0x0000ffff, /* dst_mask */
165 FALSE), /* pcrel_offset */
166
167 /* 12 bit absolute */
168 HOWTO (R_ARM_ABS12, /* type */
169 0, /* rightshift */
170 2, /* size (0 = byte, 1 = short, 2 = long) */
171 12, /* bitsize */
172 FALSE, /* pc_relative */
173 0, /* bitpos */
174 complain_overflow_bitfield,/* complain_on_overflow */
175 bfd_elf_generic_reloc, /* special_function */
176 "R_ARM_ABS12", /* name */
177 FALSE, /* partial_inplace */
00a97672
RS		 178 0x00000fff, /* src_mask */
179 0x00000fff, /* dst_mask */
7f266840
DJ		 180 FALSE), /* pcrel_offset */
181
182 HOWTO (R_ARM_THM_ABS5, /* type */
183 6, /* rightshift */
184 1, /* size (0 = byte, 1 = short, 2 = long) */
185 5, /* bitsize */
186 FALSE, /* pc_relative */
187 0, /* bitpos */
188 complain_overflow_bitfield,/* complain_on_overflow */
189 bfd_elf_generic_reloc, /* special_function */
190 "R_ARM_THM_ABS5", /* name */
191 FALSE, /* partial_inplace */
192 0x000007e0, /* src_mask */
193 0x000007e0, /* dst_mask */
194 FALSE), /* pcrel_offset */
195
196 /* 8 bit absolute */
197 HOWTO (R_ARM_ABS8, /* type */
198 0, /* rightshift */
199 0, /* size (0 = byte, 1 = short, 2 = long) */
200 8, /* bitsize */
201 FALSE, /* pc_relative */
202 0, /* bitpos */
203 complain_overflow_bitfield,/* complain_on_overflow */
204 bfd_elf_generic_reloc, /* special_function */
205 "R_ARM_ABS8", /* name */
206 FALSE, /* partial_inplace */
207 0x000000ff, /* src_mask */
208 0x000000ff, /* dst_mask */
209 FALSE), /* pcrel_offset */
210
211 HOWTO (R_ARM_SBREL32, /* type */
212 0, /* rightshift */
213 2, /* size (0 = byte, 1 = short, 2 = long) */
214 32, /* bitsize */
215 FALSE, /* pc_relative */
216 0, /* bitpos */
217 complain_overflow_dont,/* complain_on_overflow */
218 bfd_elf_generic_reloc, /* special_function */
219 "R_ARM_SBREL32", /* name */
220 FALSE, /* partial_inplace */
221 0xffffffff, /* src_mask */
222 0xffffffff, /* dst_mask */
223 FALSE), /* pcrel_offset */
224
c19d1205 225 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 226 1, /* rightshift */
227 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 228 24, /* bitsize */
7f266840
DJ		 229 TRUE, /* pc_relative */
230 0, /* bitpos */
231 complain_overflow_signed,/* complain_on_overflow */
232 bfd_elf_generic_reloc, /* special_function */
c19d1205 233 "R_ARM_THM_CALL", /* name */
7f266840 234 FALSE, /* partial_inplace */
7f6ab9f8
AM		 235 0x07ff2fff, /* src_mask */
236 0x07ff2fff, /* dst_mask */
7f266840
DJ		 237 TRUE), /* pcrel_offset */
238
07d6d2b8 239 HOWTO (R_ARM_THM_PC8, /* type */
7f266840
DJ		 240 1, /* rightshift */
241 1, /* size (0 = byte, 1 = short, 2 = long) */
242 8, /* bitsize */
243 TRUE, /* pc_relative */
244 0, /* bitpos */
245 complain_overflow_signed,/* complain_on_overflow */
246 bfd_elf_generic_reloc, /* special_function */
247 "R_ARM_THM_PC8", /* name */
248 FALSE, /* partial_inplace */
249 0x000000ff, /* src_mask */
250 0x000000ff, /* dst_mask */
251 TRUE), /* pcrel_offset */
252
c19d1205 253 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 254 1, /* rightshift */
255 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 256 32, /* bitsize */
257 FALSE, /* pc_relative */
7f266840
DJ		 258 0, /* bitpos */
259 complain_overflow_signed,/* complain_on_overflow */
260 bfd_elf_generic_reloc, /* special_function */
c19d1205 261 "R_ARM_BREL_ADJ", /* name */
7f266840 262 FALSE, /* partial_inplace */
c19d1205
ZW		 263 0xffffffff, /* src_mask */
264 0xffffffff, /* dst_mask */
265 FALSE), /* pcrel_offset */
7f266840 266
0855e32b 267 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 268 0, /* rightshift */
0855e32b
NS		 269 2, /* size (0 = byte, 1 = short, 2 = long) */
270 32, /* bitsize */
7f266840
DJ		 271 FALSE, /* pc_relative */
272 0, /* bitpos */
0855e32b 273 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 274 bfd_elf_generic_reloc, /* special_function */
0855e32b 275 "R_ARM_TLS_DESC", /* name */
7f266840 276 FALSE, /* partial_inplace */
0855e32b
NS		 277 0xffffffff, /* src_mask */
278 0xffffffff, /* dst_mask */
7f266840
DJ		 279 FALSE), /* pcrel_offset */
280
281 HOWTO (R_ARM_THM_SWI8, /* type */
282 0, /* rightshift */
283 0, /* size (0 = byte, 1 = short, 2 = long) */
284 0, /* bitsize */
285 FALSE, /* pc_relative */
286 0, /* bitpos */
287 complain_overflow_signed,/* complain_on_overflow */
288 bfd_elf_generic_reloc, /* special_function */
289 "R_ARM_SWI8", /* name */
290 FALSE, /* partial_inplace */
291 0x00000000, /* src_mask */
292 0x00000000, /* dst_mask */
293 FALSE), /* pcrel_offset */
294
295 /* BLX instruction for the ARM. */
296 HOWTO (R_ARM_XPC25, /* type */
297 2, /* rightshift */
298 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 299 24, /* bitsize */
7f266840
DJ		 300 TRUE, /* pc_relative */
301 0, /* bitpos */
302 complain_overflow_signed,/* complain_on_overflow */
303 bfd_elf_generic_reloc, /* special_function */
304 "R_ARM_XPC25", /* name */
305 FALSE, /* partial_inplace */
306 0x00ffffff, /* src_mask */
307 0x00ffffff, /* dst_mask */
308 TRUE), /* pcrel_offset */
309
310 /* BLX instruction for the Thumb. */
311 HOWTO (R_ARM_THM_XPC22, /* type */
312 2, /* rightshift */
313 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 314 24, /* bitsize */
7f266840
DJ		 315 TRUE, /* pc_relative */
316 0, /* bitpos */
317 complain_overflow_signed,/* complain_on_overflow */
318 bfd_elf_generic_reloc, /* special_function */
319 "R_ARM_THM_XPC22", /* name */
320 FALSE, /* partial_inplace */
7f6ab9f8
AM		 321 0x07ff2fff, /* src_mask */
322 0x07ff2fff, /* dst_mask */
7f266840
DJ		 323 TRUE), /* pcrel_offset */
324
ba93b8ac 325 /* Dynamic TLS relocations. */
7f266840 326
ba93b8ac 327 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
07d6d2b8
AM		 328 0, /* rightshift */
329 2, /* size (0 = byte, 1 = short, 2 = long) */
330 32, /* bitsize */
331 FALSE, /* pc_relative */
332 0, /* bitpos */
99059e56
RM		 333 complain_overflow_bitfield,/* complain_on_overflow */
334 bfd_elf_generic_reloc, /* special_function */
335 "R_ARM_TLS_DTPMOD32", /* name */
336 TRUE, /* partial_inplace */
337 0xffffffff, /* src_mask */
338 0xffffffff, /* dst_mask */
07d6d2b8 339 FALSE), /* pcrel_offset */
7f266840 340
ba93b8ac 341 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
07d6d2b8
AM		 342 0, /* rightshift */
343 2, /* size (0 = byte, 1 = short, 2 = long) */
344 32, /* bitsize */
345 FALSE, /* pc_relative */
346 0, /* bitpos */
99059e56
RM		 347 complain_overflow_bitfield,/* complain_on_overflow */
348 bfd_elf_generic_reloc, /* special_function */
349 "R_ARM_TLS_DTPOFF32", /* name */
350 TRUE, /* partial_inplace */
351 0xffffffff, /* src_mask */
352 0xffffffff, /* dst_mask */
07d6d2b8 353 FALSE), /* pcrel_offset */
7f266840 354
ba93b8ac 355 HOWTO (R_ARM_TLS_TPOFF32, /* type */
07d6d2b8
AM		 356 0, /* rightshift */
357 2, /* size (0 = byte, 1 = short, 2 = long) */
358 32, /* bitsize */
359 FALSE, /* pc_relative */
360 0, /* bitpos */
99059e56
RM		 361 complain_overflow_bitfield,/* complain_on_overflow */
362 bfd_elf_generic_reloc, /* special_function */
363 "R_ARM_TLS_TPOFF32", /* name */
364 TRUE, /* partial_inplace */
365 0xffffffff, /* src_mask */
366 0xffffffff, /* dst_mask */
07d6d2b8 367 FALSE), /* pcrel_offset */
7f266840
DJ		 368
369 /* Relocs used in ARM Linux */
370
371 HOWTO (R_ARM_COPY, /* type */
07d6d2b8
AM		 372 0, /* rightshift */
373 2, /* size (0 = byte, 1 = short, 2 = long) */
374 32, /* bitsize */
375 FALSE, /* pc_relative */
376 0, /* bitpos */
99059e56
RM		 377 complain_overflow_bitfield,/* complain_on_overflow */
378 bfd_elf_generic_reloc, /* special_function */
379 "R_ARM_COPY", /* name */
380 TRUE, /* partial_inplace */
381 0xffffffff, /* src_mask */
382 0xffffffff, /* dst_mask */
07d6d2b8 383 FALSE), /* pcrel_offset */
7f266840
DJ		 384
385 HOWTO (R_ARM_GLOB_DAT, /* type */
07d6d2b8
AM		 386 0, /* rightshift */
387 2, /* size (0 = byte, 1 = short, 2 = long) */
388 32, /* bitsize */
389 FALSE, /* pc_relative */
390 0, /* bitpos */
99059e56
RM		 391 complain_overflow_bitfield,/* complain_on_overflow */
392 bfd_elf_generic_reloc, /* special_function */
393 "R_ARM_GLOB_DAT", /* name */
394 TRUE, /* partial_inplace */
395 0xffffffff, /* src_mask */
396 0xffffffff, /* dst_mask */
07d6d2b8 397 FALSE), /* pcrel_offset */
7f266840
DJ		 398
399 HOWTO (R_ARM_JUMP_SLOT, /* type */
07d6d2b8
AM		 400 0, /* rightshift */
401 2, /* size (0 = byte, 1 = short, 2 = long) */
402 32, /* bitsize */
403 FALSE, /* pc_relative */
404 0, /* bitpos */
99059e56
RM		 405 complain_overflow_bitfield,/* complain_on_overflow */
406 bfd_elf_generic_reloc, /* special_function */
407 "R_ARM_JUMP_SLOT", /* name */
408 TRUE, /* partial_inplace */
409 0xffffffff, /* src_mask */
410 0xffffffff, /* dst_mask */
07d6d2b8 411 FALSE), /* pcrel_offset */
7f266840
DJ		 412
413 HOWTO (R_ARM_RELATIVE, /* type */
07d6d2b8
AM		 414 0, /* rightshift */
415 2, /* size (0 = byte, 1 = short, 2 = long) */
416 32, /* bitsize */
417 FALSE, /* pc_relative */
418 0, /* bitpos */
99059e56
RM		 419 complain_overflow_bitfield,/* complain_on_overflow */
420 bfd_elf_generic_reloc, /* special_function */
421 "R_ARM_RELATIVE", /* name */
422 TRUE, /* partial_inplace */
423 0xffffffff, /* src_mask */
424 0xffffffff, /* dst_mask */
07d6d2b8 425 FALSE), /* pcrel_offset */
7f266840 426
c19d1205 427 HOWTO (R_ARM_GOTOFF32, /* type */
07d6d2b8
AM		 428 0, /* rightshift */
429 2, /* size (0 = byte, 1 = short, 2 = long) */
430 32, /* bitsize */
431 FALSE, /* pc_relative */
432 0, /* bitpos */
99059e56
RM		 433 complain_overflow_bitfield,/* complain_on_overflow */
434 bfd_elf_generic_reloc, /* special_function */
435 "R_ARM_GOTOFF32", /* name */
436 TRUE, /* partial_inplace */
437 0xffffffff, /* src_mask */
438 0xffffffff, /* dst_mask */
07d6d2b8 439 FALSE), /* pcrel_offset */
7f266840
DJ		 440
441 HOWTO (R_ARM_GOTPC, /* type */
07d6d2b8
AM		 442 0, /* rightshift */
443 2, /* size (0 = byte, 1 = short, 2 = long) */
444 32, /* bitsize */
99059e56 445 TRUE, /* pc_relative */
07d6d2b8 446 0, /* bitpos */
99059e56
RM		 447 complain_overflow_bitfield,/* complain_on_overflow */
448 bfd_elf_generic_reloc, /* special_function */
449 "R_ARM_GOTPC", /* name */
450 TRUE, /* partial_inplace */
451 0xffffffff, /* src_mask */
452 0xffffffff, /* dst_mask */
453 TRUE), /* pcrel_offset */
7f266840
DJ		 454
455 HOWTO (R_ARM_GOT32, /* type */
07d6d2b8
AM		 456 0, /* rightshift */
457 2, /* size (0 = byte, 1 = short, 2 = long) */
458 32, /* bitsize */
99059e56 459 FALSE, /* pc_relative */
07d6d2b8 460 0, /* bitpos */
99059e56
RM		 461 complain_overflow_bitfield,/* complain_on_overflow */
462 bfd_elf_generic_reloc, /* special_function */
463 "R_ARM_GOT32", /* name */
464 TRUE, /* partial_inplace */
465 0xffffffff, /* src_mask */
466 0xffffffff, /* dst_mask */
467 FALSE), /* pcrel_offset */
7f266840
DJ		 468
469 HOWTO (R_ARM_PLT32, /* type */
07d6d2b8
AM		 470 2, /* rightshift */
471 2, /* size (0 = byte, 1 = short, 2 = long) */
472 24, /* bitsize */
99059e56 473 TRUE, /* pc_relative */
07d6d2b8 474 0, /* bitpos */
99059e56
RM		 475 complain_overflow_bitfield,/* complain_on_overflow */
476 bfd_elf_generic_reloc, /* special_function */
477 "R_ARM_PLT32", /* name */
478 FALSE, /* partial_inplace */
479 0x00ffffff, /* src_mask */
480 0x00ffffff, /* dst_mask */
481 TRUE), /* pcrel_offset */
7f266840
DJ		 482
483 HOWTO (R_ARM_CALL, /* type */
484 2, /* rightshift */
485 2, /* size (0 = byte, 1 = short, 2 = long) */
486 24, /* bitsize */
487 TRUE, /* pc_relative */
488 0, /* bitpos */
489 complain_overflow_signed,/* complain_on_overflow */
490 bfd_elf_generic_reloc, /* special_function */
491 "R_ARM_CALL", /* name */
492 FALSE, /* partial_inplace */
493 0x00ffffff, /* src_mask */
494 0x00ffffff, /* dst_mask */
495 TRUE), /* pcrel_offset */
496
497 HOWTO (R_ARM_JUMP24, /* type */
498 2, /* rightshift */
499 2, /* size (0 = byte, 1 = short, 2 = long) */
500 24, /* bitsize */
501 TRUE, /* pc_relative */
502 0, /* bitpos */
503 complain_overflow_signed,/* complain_on_overflow */
504 bfd_elf_generic_reloc, /* special_function */
505 "R_ARM_JUMP24", /* name */
506 FALSE, /* partial_inplace */
507 0x00ffffff, /* src_mask */
508 0x00ffffff, /* dst_mask */
509 TRUE), /* pcrel_offset */
510
c19d1205
ZW		 511 HOWTO (R_ARM_THM_JUMP24, /* type */
512 1, /* rightshift */
513 2, /* size (0 = byte, 1 = short, 2 = long) */
514 24, /* bitsize */
515 TRUE, /* pc_relative */
7f266840 516 0, /* bitpos */
c19d1205 517 complain_overflow_signed,/* complain_on_overflow */
7f266840 518 bfd_elf_generic_reloc, /* special_function */
c19d1205 519 "R_ARM_THM_JUMP24", /* name */
7f266840 520 FALSE, /* partial_inplace */
c19d1205
ZW		 521 0x07ff2fff, /* src_mask */
522 0x07ff2fff, /* dst_mask */
523 TRUE), /* pcrel_offset */
7f266840 524
c19d1205 525 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 526 0, /* rightshift */
c19d1205
ZW		 527 2, /* size (0 = byte, 1 = short, 2 = long) */
528 32, /* bitsize */
7f266840
DJ		 529 FALSE, /* pc_relative */
530 0, /* bitpos */
531 complain_overflow_dont,/* complain_on_overflow */
532 bfd_elf_generic_reloc, /* special_function */
c19d1205 533 "R_ARM_BASE_ABS", /* name */
7f266840 534 FALSE, /* partial_inplace */
c19d1205
ZW		 535 0xffffffff, /* src_mask */
536 0xffffffff, /* dst_mask */
7f266840
DJ		 537 FALSE), /* pcrel_offset */
538
539 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
540 0, /* rightshift */
541 2, /* size (0 = byte, 1 = short, 2 = long) */
542 12, /* bitsize */
543 TRUE, /* pc_relative */
544 0, /* bitpos */
545 complain_overflow_dont,/* complain_on_overflow */
546 bfd_elf_generic_reloc, /* special_function */
547 "R_ARM_ALU_PCREL_7_0", /* name */
548 FALSE, /* partial_inplace */
549 0x00000fff, /* src_mask */
550 0x00000fff, /* dst_mask */
551 TRUE), /* pcrel_offset */
552
553 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
554 0, /* rightshift */
555 2, /* size (0 = byte, 1 = short, 2 = long) */
556 12, /* bitsize */
557 TRUE, /* pc_relative */
558 8, /* bitpos */
559 complain_overflow_dont,/* complain_on_overflow */
560 bfd_elf_generic_reloc, /* special_function */
561 "R_ARM_ALU_PCREL_15_8",/* name */
562 FALSE, /* partial_inplace */
563 0x00000fff, /* src_mask */
564 0x00000fff, /* dst_mask */
565 TRUE), /* pcrel_offset */
566
567 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
568 0, /* rightshift */
569 2, /* size (0 = byte, 1 = short, 2 = long) */
570 12, /* bitsize */
571 TRUE, /* pc_relative */
572 16, /* bitpos */
573 complain_overflow_dont,/* complain_on_overflow */
574 bfd_elf_generic_reloc, /* special_function */
575 "R_ARM_ALU_PCREL_23_15",/* name */
576 FALSE, /* partial_inplace */
577 0x00000fff, /* src_mask */
578 0x00000fff, /* dst_mask */
579 TRUE), /* pcrel_offset */
580
581 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
582 0, /* rightshift */
583 2, /* size (0 = byte, 1 = short, 2 = long) */
584 12, /* bitsize */
585 FALSE, /* pc_relative */
586 0, /* bitpos */
587 complain_overflow_dont,/* complain_on_overflow */
588 bfd_elf_generic_reloc, /* special_function */
589 "R_ARM_LDR_SBREL_11_0",/* name */
590 FALSE, /* partial_inplace */
591 0x00000fff, /* src_mask */
592 0x00000fff, /* dst_mask */
593 FALSE), /* pcrel_offset */
594
595 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
596 0, /* rightshift */
597 2, /* size (0 = byte, 1 = short, 2 = long) */
598 8, /* bitsize */
599 FALSE, /* pc_relative */
600 12, /* bitpos */
601 complain_overflow_dont,/* complain_on_overflow */
602 bfd_elf_generic_reloc, /* special_function */
603 "R_ARM_ALU_SBREL_19_12",/* name */
604 FALSE, /* partial_inplace */
605 0x000ff000, /* src_mask */
606 0x000ff000, /* dst_mask */
607 FALSE), /* pcrel_offset */
608
609 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
610 0, /* rightshift */
611 2, /* size (0 = byte, 1 = short, 2 = long) */
612 8, /* bitsize */
613 FALSE, /* pc_relative */
614 20, /* bitpos */
615 complain_overflow_dont,/* complain_on_overflow */
616 bfd_elf_generic_reloc, /* special_function */
617 "R_ARM_ALU_SBREL_27_20",/* name */
618 FALSE, /* partial_inplace */
619 0x0ff00000, /* src_mask */
620 0x0ff00000, /* dst_mask */
621 FALSE), /* pcrel_offset */
622
623 HOWTO (R_ARM_TARGET1, /* type */
624 0, /* rightshift */
625 2, /* size (0 = byte, 1 = short, 2 = long) */
626 32, /* bitsize */
627 FALSE, /* pc_relative */
628 0, /* bitpos */
629 complain_overflow_dont,/* complain_on_overflow */
630 bfd_elf_generic_reloc, /* special_function */
631 "R_ARM_TARGET1", /* name */
632 FALSE, /* partial_inplace */
633 0xffffffff, /* src_mask */
634 0xffffffff, /* dst_mask */
635 FALSE), /* pcrel_offset */
636
637 HOWTO (R_ARM_ROSEGREL32, /* type */
638 0, /* rightshift */
639 2, /* size (0 = byte, 1 = short, 2 = long) */
640 32, /* bitsize */
641 FALSE, /* pc_relative */
642 0, /* bitpos */
643 complain_overflow_dont,/* complain_on_overflow */
644 bfd_elf_generic_reloc, /* special_function */
645 "R_ARM_ROSEGREL32", /* name */
646 FALSE, /* partial_inplace */
647 0xffffffff, /* src_mask */
648 0xffffffff, /* dst_mask */
649 FALSE), /* pcrel_offset */
650
651 HOWTO (R_ARM_V4BX, /* type */
652 0, /* rightshift */
653 2, /* size (0 = byte, 1 = short, 2 = long) */
654 32, /* bitsize */
655 FALSE, /* pc_relative */
656 0, /* bitpos */
657 complain_overflow_dont,/* complain_on_overflow */
658 bfd_elf_generic_reloc, /* special_function */
659 "R_ARM_V4BX", /* name */
660 FALSE, /* partial_inplace */
661 0xffffffff, /* src_mask */
662 0xffffffff, /* dst_mask */
663 FALSE), /* pcrel_offset */
664
665 HOWTO (R_ARM_TARGET2, /* type */
666 0, /* rightshift */
667 2, /* size (0 = byte, 1 = short, 2 = long) */
668 32, /* bitsize */
669 FALSE, /* pc_relative */
670 0, /* bitpos */
671 complain_overflow_signed,/* complain_on_overflow */
672 bfd_elf_generic_reloc, /* special_function */
673 "R_ARM_TARGET2", /* name */
674 FALSE, /* partial_inplace */
675 0xffffffff, /* src_mask */
676 0xffffffff, /* dst_mask */
677 TRUE), /* pcrel_offset */
678
679 HOWTO (R_ARM_PREL31, /* type */
680 0, /* rightshift */
681 2, /* size (0 = byte, 1 = short, 2 = long) */
682 31, /* bitsize */
683 TRUE, /* pc_relative */
684 0, /* bitpos */
685 complain_overflow_signed,/* complain_on_overflow */
686 bfd_elf_generic_reloc, /* special_function */
687 "R_ARM_PREL31", /* name */
688 FALSE, /* partial_inplace */
689 0x7fffffff, /* src_mask */
690 0x7fffffff, /* dst_mask */
691 TRUE), /* pcrel_offset */
c19d1205
ZW		 692
693 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
694 0, /* rightshift */
695 2, /* size (0 = byte, 1 = short, 2 = long) */
696 16, /* bitsize */
697 FALSE, /* pc_relative */
698 0, /* bitpos */
699 complain_overflow_dont,/* complain_on_overflow */
700 bfd_elf_generic_reloc, /* special_function */
701 "R_ARM_MOVW_ABS_NC", /* name */
702 FALSE, /* partial_inplace */
39623e12
PB		 703 0x000f0fff, /* src_mask */
704 0x000f0fff, /* dst_mask */
c19d1205
ZW		 705 FALSE), /* pcrel_offset */
706
707 HOWTO (R_ARM_MOVT_ABS, /* type */
708 0, /* rightshift */
709 2, /* size (0 = byte, 1 = short, 2 = long) */
710 16, /* bitsize */
711 FALSE, /* pc_relative */
712 0, /* bitpos */
713 complain_overflow_bitfield,/* complain_on_overflow */
714 bfd_elf_generic_reloc, /* special_function */
715 "R_ARM_MOVT_ABS", /* name */
716 FALSE, /* partial_inplace */
39623e12
PB		 717 0x000f0fff, /* src_mask */
718 0x000f0fff, /* dst_mask */
c19d1205
ZW		 719 FALSE), /* pcrel_offset */
720
721 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
722 0, /* rightshift */
723 2, /* size (0 = byte, 1 = short, 2 = long) */
724 16, /* bitsize */
725 TRUE, /* pc_relative */
726 0, /* bitpos */
727 complain_overflow_dont,/* complain_on_overflow */
728 bfd_elf_generic_reloc, /* special_function */
729 "R_ARM_MOVW_PREL_NC", /* name */
730 FALSE, /* partial_inplace */
39623e12
PB		 731 0x000f0fff, /* src_mask */
732 0x000f0fff, /* dst_mask */
c19d1205
ZW		 733 TRUE), /* pcrel_offset */
734
735 HOWTO (R_ARM_MOVT_PREL, /* type */
736 0, /* rightshift */
737 2, /* size (0 = byte, 1 = short, 2 = long) */
738 16, /* bitsize */
739 TRUE, /* pc_relative */
740 0, /* bitpos */
741 complain_overflow_bitfield,/* complain_on_overflow */
742 bfd_elf_generic_reloc, /* special_function */
743 "R_ARM_MOVT_PREL", /* name */
744 FALSE, /* partial_inplace */
39623e12
PB		 745 0x000f0fff, /* src_mask */
746 0x000f0fff, /* dst_mask */
c19d1205
ZW		 747 TRUE), /* pcrel_offset */
748
749 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
750 0, /* rightshift */
751 2, /* size (0 = byte, 1 = short, 2 = long) */
752 16, /* bitsize */
753 FALSE, /* pc_relative */
754 0, /* bitpos */
755 complain_overflow_dont,/* complain_on_overflow */
756 bfd_elf_generic_reloc, /* special_function */
757 "R_ARM_THM_MOVW_ABS_NC",/* name */
758 FALSE, /* partial_inplace */
759 0x040f70ff, /* src_mask */
760 0x040f70ff, /* dst_mask */
761 FALSE), /* pcrel_offset */
762
763 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
764 0, /* rightshift */
765 2, /* size (0 = byte, 1 = short, 2 = long) */
766 16, /* bitsize */
767 FALSE, /* pc_relative */
768 0, /* bitpos */
769 complain_overflow_bitfield,/* complain_on_overflow */
770 bfd_elf_generic_reloc, /* special_function */
771 "R_ARM_THM_MOVT_ABS", /* name */
772 FALSE, /* partial_inplace */
773 0x040f70ff, /* src_mask */
774 0x040f70ff, /* dst_mask */
775 FALSE), /* pcrel_offset */
776
777 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
778 0, /* rightshift */
779 2, /* size (0 = byte, 1 = short, 2 = long) */
780 16, /* bitsize */
781 TRUE, /* pc_relative */
782 0, /* bitpos */
783 complain_overflow_dont,/* complain_on_overflow */
784 bfd_elf_generic_reloc, /* special_function */
785 "R_ARM_THM_MOVW_PREL_NC",/* name */
786 FALSE, /* partial_inplace */
787 0x040f70ff, /* src_mask */
788 0x040f70ff, /* dst_mask */
789 TRUE), /* pcrel_offset */
790
791 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
792 0, /* rightshift */
793 2, /* size (0 = byte, 1 = short, 2 = long) */
794 16, /* bitsize */
795 TRUE, /* pc_relative */
796 0, /* bitpos */
797 complain_overflow_bitfield,/* complain_on_overflow */
798 bfd_elf_generic_reloc, /* special_function */
799 "R_ARM_THM_MOVT_PREL", /* name */
800 FALSE, /* partial_inplace */
801 0x040f70ff, /* src_mask */
802 0x040f70ff, /* dst_mask */
803 TRUE), /* pcrel_offset */
804
805 HOWTO (R_ARM_THM_JUMP19, /* type */
806 1, /* rightshift */
807 2, /* size (0 = byte, 1 = short, 2 = long) */
808 19, /* bitsize */
809 TRUE, /* pc_relative */
810 0, /* bitpos */
811 complain_overflow_signed,/* complain_on_overflow */
812 bfd_elf_generic_reloc, /* special_function */
813 "R_ARM_THM_JUMP19", /* name */
814 FALSE, /* partial_inplace */
815 0x043f2fff, /* src_mask */
816 0x043f2fff, /* dst_mask */
817 TRUE), /* pcrel_offset */
818
819 HOWTO (R_ARM_THM_JUMP6, /* type */
820 1, /* rightshift */
821 1, /* size (0 = byte, 1 = short, 2 = long) */
822 6, /* bitsize */
823 TRUE, /* pc_relative */
824 0, /* bitpos */
825 complain_overflow_unsigned,/* complain_on_overflow */
826 bfd_elf_generic_reloc, /* special_function */
827 "R_ARM_THM_JUMP6", /* name */
828 FALSE, /* partial_inplace */
829 0x02f8, /* src_mask */
830 0x02f8, /* dst_mask */
831 TRUE), /* pcrel_offset */
832
833 /* These are declared as 13-bit signed relocations because we can
834 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
835 versa. */
836 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
837 0, /* rightshift */
838 2, /* size (0 = byte, 1 = short, 2 = long) */
839 13, /* bitsize */
840 TRUE, /* pc_relative */
841 0, /* bitpos */
2cab6cc3 842 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 843 bfd_elf_generic_reloc, /* special_function */
844 "R_ARM_THM_ALU_PREL_11_0",/* name */
845 FALSE, /* partial_inplace */
2cab6cc3
MS		 846 0xffffffff, /* src_mask */
847 0xffffffff, /* dst_mask */
c19d1205
ZW		 848 TRUE), /* pcrel_offset */
849
850 HOWTO (R_ARM_THM_PC12, /* type */
851 0, /* rightshift */
852 2, /* size (0 = byte, 1 = short, 2 = long) */
853 13, /* bitsize */
854 TRUE, /* pc_relative */
855 0, /* bitpos */
2cab6cc3 856 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 857 bfd_elf_generic_reloc, /* special_function */
858 "R_ARM_THM_PC12", /* name */
859 FALSE, /* partial_inplace */
2cab6cc3
MS		 860 0xffffffff, /* src_mask */
861 0xffffffff, /* dst_mask */
c19d1205
ZW		 862 TRUE), /* pcrel_offset */
863
864 HOWTO (R_ARM_ABS32_NOI, /* type */
865 0, /* rightshift */
866 2, /* size (0 = byte, 1 = short, 2 = long) */
867 32, /* bitsize */
868 FALSE, /* pc_relative */
869 0, /* bitpos */
870 complain_overflow_dont,/* complain_on_overflow */
871 bfd_elf_generic_reloc, /* special_function */
872 "R_ARM_ABS32_NOI", /* name */
873 FALSE, /* partial_inplace */
874 0xffffffff, /* src_mask */
875 0xffffffff, /* dst_mask */
876 FALSE), /* pcrel_offset */
877
878 HOWTO (R_ARM_REL32_NOI, /* type */
879 0, /* rightshift */
880 2, /* size (0 = byte, 1 = short, 2 = long) */
881 32, /* bitsize */
882 TRUE, /* pc_relative */
883 0, /* bitpos */
884 complain_overflow_dont,/* complain_on_overflow */
885 bfd_elf_generic_reloc, /* special_function */
886 "R_ARM_REL32_NOI", /* name */
887 FALSE, /* partial_inplace */
888 0xffffffff, /* src_mask */
889 0xffffffff, /* dst_mask */
890 FALSE), /* pcrel_offset */
7f266840 891
4962c51a
MS		 892 /* Group relocations. */
893
894 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
895 0, /* rightshift */
896 2, /* size (0 = byte, 1 = short, 2 = long) */
897 32, /* bitsize */
898 TRUE, /* pc_relative */
899 0, /* bitpos */
900 complain_overflow_dont,/* complain_on_overflow */
901 bfd_elf_generic_reloc, /* special_function */
902 "R_ARM_ALU_PC_G0_NC", /* name */
903 FALSE, /* partial_inplace */
904 0xffffffff, /* src_mask */
905 0xffffffff, /* dst_mask */
906 TRUE), /* pcrel_offset */
907
07d6d2b8 908 HOWTO (R_ARM_ALU_PC_G0, /* type */
4962c51a
MS		 909 0, /* rightshift */
910 2, /* size (0 = byte, 1 = short, 2 = long) */
911 32, /* bitsize */
912 TRUE, /* pc_relative */
913 0, /* bitpos */
914 complain_overflow_dont,/* complain_on_overflow */
915 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 916 "R_ARM_ALU_PC_G0", /* name */
4962c51a
MS		 917 FALSE, /* partial_inplace */
918 0xffffffff, /* src_mask */
919 0xffffffff, /* dst_mask */
920 TRUE), /* pcrel_offset */
921
922 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
923 0, /* rightshift */
924 2, /* size (0 = byte, 1 = short, 2 = long) */
925 32, /* bitsize */
926 TRUE, /* pc_relative */
927 0, /* bitpos */
928 complain_overflow_dont,/* complain_on_overflow */
929 bfd_elf_generic_reloc, /* special_function */
930 "R_ARM_ALU_PC_G1_NC", /* name */
931 FALSE, /* partial_inplace */
932 0xffffffff, /* src_mask */
933 0xffffffff, /* dst_mask */
934 TRUE), /* pcrel_offset */
935
07d6d2b8 936 HOWTO (R_ARM_ALU_PC_G1, /* type */
4962c51a
MS		 937 0, /* rightshift */
938 2, /* size (0 = byte, 1 = short, 2 = long) */
939 32, /* bitsize */
940 TRUE, /* pc_relative */
941 0, /* bitpos */
942 complain_overflow_dont,/* complain_on_overflow */
943 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 944 "R_ARM_ALU_PC_G1", /* name */
4962c51a
MS		 945 FALSE, /* partial_inplace */
946 0xffffffff, /* src_mask */
947 0xffffffff, /* dst_mask */
948 TRUE), /* pcrel_offset */
949
07d6d2b8 950 HOWTO (R_ARM_ALU_PC_G2, /* type */
4962c51a
MS		 951 0, /* rightshift */
952 2, /* size (0 = byte, 1 = short, 2 = long) */
953 32, /* bitsize */
954 TRUE, /* pc_relative */
955 0, /* bitpos */
956 complain_overflow_dont,/* complain_on_overflow */
957 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 958 "R_ARM_ALU_PC_G2", /* name */
4962c51a
MS		 959 FALSE, /* partial_inplace */
960 0xffffffff, /* src_mask */
961 0xffffffff, /* dst_mask */
962 TRUE), /* pcrel_offset */
963
07d6d2b8 964 HOWTO (R_ARM_LDR_PC_G1, /* type */
4962c51a
MS		 965 0, /* rightshift */
966 2, /* size (0 = byte, 1 = short, 2 = long) */
967 32, /* bitsize */
968 TRUE, /* pc_relative */
969 0, /* bitpos */
970 complain_overflow_dont,/* complain_on_overflow */
971 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 972 "R_ARM_LDR_PC_G1", /* name */
4962c51a
MS		 973 FALSE, /* partial_inplace */
974 0xffffffff, /* src_mask */
975 0xffffffff, /* dst_mask */
976 TRUE), /* pcrel_offset */
977
07d6d2b8 978 HOWTO (R_ARM_LDR_PC_G2, /* type */
4962c51a
MS		 979 0, /* rightshift */
980 2, /* size (0 = byte, 1 = short, 2 = long) */
981 32, /* bitsize */
982 TRUE, /* pc_relative */
983 0, /* bitpos */
984 complain_overflow_dont,/* complain_on_overflow */
985 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 986 "R_ARM_LDR_PC_G2", /* name */
4962c51a
MS		 987 FALSE, /* partial_inplace */
988 0xffffffff, /* src_mask */
989 0xffffffff, /* dst_mask */
990 TRUE), /* pcrel_offset */
991
07d6d2b8 992 HOWTO (R_ARM_LDRS_PC_G0, /* type */
4962c51a
MS		 993 0, /* rightshift */
994 2, /* size (0 = byte, 1 = short, 2 = long) */
995 32, /* bitsize */
996 TRUE, /* pc_relative */
997 0, /* bitpos */
998 complain_overflow_dont,/* complain_on_overflow */
999 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1000 "R_ARM_LDRS_PC_G0", /* name */
4962c51a
MS		 1001 FALSE, /* partial_inplace */
1002 0xffffffff, /* src_mask */
1003 0xffffffff, /* dst_mask */
1004 TRUE), /* pcrel_offset */
1005
07d6d2b8 1006 HOWTO (R_ARM_LDRS_PC_G1, /* type */
4962c51a
MS		 1007 0, /* rightshift */
1008 2, /* size (0 = byte, 1 = short, 2 = long) */
1009 32, /* bitsize */
1010 TRUE, /* pc_relative */
1011 0, /* bitpos */
1012 complain_overflow_dont,/* complain_on_overflow */
1013 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1014 "R_ARM_LDRS_PC_G1", /* name */
4962c51a
MS		 1015 FALSE, /* partial_inplace */
1016 0xffffffff, /* src_mask */
1017 0xffffffff, /* dst_mask */
1018 TRUE), /* pcrel_offset */
1019
07d6d2b8 1020 HOWTO (R_ARM_LDRS_PC_G2, /* type */
4962c51a
MS		 1021 0, /* rightshift */
1022 2, /* size (0 = byte, 1 = short, 2 = long) */
1023 32, /* bitsize */
1024 TRUE, /* pc_relative */
1025 0, /* bitpos */
1026 complain_overflow_dont,/* complain_on_overflow */
1027 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1028 "R_ARM_LDRS_PC_G2", /* name */
4962c51a
MS		 1029 FALSE, /* partial_inplace */
1030 0xffffffff, /* src_mask */
1031 0xffffffff, /* dst_mask */
1032 TRUE), /* pcrel_offset */
1033
07d6d2b8 1034 HOWTO (R_ARM_LDC_PC_G0, /* type */
4962c51a
MS		 1035 0, /* rightshift */
1036 2, /* size (0 = byte, 1 = short, 2 = long) */
1037 32, /* bitsize */
1038 TRUE, /* pc_relative */
1039 0, /* bitpos */
1040 complain_overflow_dont,/* complain_on_overflow */
1041 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1042 "R_ARM_LDC_PC_G0", /* name */
4962c51a
MS		 1043 FALSE, /* partial_inplace */
1044 0xffffffff, /* src_mask */
1045 0xffffffff, /* dst_mask */
1046 TRUE), /* pcrel_offset */
1047
07d6d2b8 1048 HOWTO (R_ARM_LDC_PC_G1, /* type */
4962c51a
MS		 1049 0, /* rightshift */
1050 2, /* size (0 = byte, 1 = short, 2 = long) */
1051 32, /* bitsize */
1052 TRUE, /* pc_relative */
1053 0, /* bitpos */
1054 complain_overflow_dont,/* complain_on_overflow */
1055 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1056 "R_ARM_LDC_PC_G1", /* name */
4962c51a
MS		 1057 FALSE, /* partial_inplace */
1058 0xffffffff, /* src_mask */
1059 0xffffffff, /* dst_mask */
1060 TRUE), /* pcrel_offset */
1061
07d6d2b8 1062 HOWTO (R_ARM_LDC_PC_G2, /* type */
4962c51a
MS		 1063 0, /* rightshift */
1064 2, /* size (0 = byte, 1 = short, 2 = long) */
1065 32, /* bitsize */
1066 TRUE, /* pc_relative */
1067 0, /* bitpos */
1068 complain_overflow_dont,/* complain_on_overflow */
1069 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1070 "R_ARM_LDC_PC_G2", /* name */
4962c51a
MS		 1071 FALSE, /* partial_inplace */
1072 0xffffffff, /* src_mask */
1073 0xffffffff, /* dst_mask */
1074 TRUE), /* pcrel_offset */
1075
07d6d2b8 1076 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
4962c51a
MS		 1077 0, /* rightshift */
1078 2, /* size (0 = byte, 1 = short, 2 = long) */
1079 32, /* bitsize */
1080 TRUE, /* pc_relative */
1081 0, /* bitpos */
1082 complain_overflow_dont,/* complain_on_overflow */
1083 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1084 "R_ARM_ALU_SB_G0_NC", /* name */
4962c51a
MS		 1085 FALSE, /* partial_inplace */
1086 0xffffffff, /* src_mask */
1087 0xffffffff, /* dst_mask */
1088 TRUE), /* pcrel_offset */
1089
07d6d2b8 1090 HOWTO (R_ARM_ALU_SB_G0, /* type */
4962c51a
MS		 1091 0, /* rightshift */
1092 2, /* size (0 = byte, 1 = short, 2 = long) */
1093 32, /* bitsize */
1094 TRUE, /* pc_relative */
1095 0, /* bitpos */
1096 complain_overflow_dont,/* complain_on_overflow */
1097 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1098 "R_ARM_ALU_SB_G0", /* name */
4962c51a
MS		 1099 FALSE, /* partial_inplace */
1100 0xffffffff, /* src_mask */
1101 0xffffffff, /* dst_mask */
1102 TRUE), /* pcrel_offset */
1103
07d6d2b8 1104 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
4962c51a
MS		 1105 0, /* rightshift */
1106 2, /* size (0 = byte, 1 = short, 2 = long) */
1107 32, /* bitsize */
1108 TRUE, /* pc_relative */
1109 0, /* bitpos */
1110 complain_overflow_dont,/* complain_on_overflow */
1111 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1112 "R_ARM_ALU_SB_G1_NC", /* name */
4962c51a
MS		 1113 FALSE, /* partial_inplace */
1114 0xffffffff, /* src_mask */
1115 0xffffffff, /* dst_mask */
1116 TRUE), /* pcrel_offset */
1117
07d6d2b8 1118 HOWTO (R_ARM_ALU_SB_G1, /* type */
4962c51a
MS		 1119 0, /* rightshift */
1120 2, /* size (0 = byte, 1 = short, 2 = long) */
1121 32, /* bitsize */
1122 TRUE, /* pc_relative */
1123 0, /* bitpos */
1124 complain_overflow_dont,/* complain_on_overflow */
1125 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1126 "R_ARM_ALU_SB_G1", /* name */
4962c51a
MS		 1127 FALSE, /* partial_inplace */
1128 0xffffffff, /* src_mask */
1129 0xffffffff, /* dst_mask */
1130 TRUE), /* pcrel_offset */
1131
07d6d2b8 1132 HOWTO (R_ARM_ALU_SB_G2, /* type */
4962c51a
MS		 1133 0, /* rightshift */
1134 2, /* size (0 = byte, 1 = short, 2 = long) */
1135 32, /* bitsize */
1136 TRUE, /* pc_relative */
1137 0, /* bitpos */
1138 complain_overflow_dont,/* complain_on_overflow */
1139 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1140 "R_ARM_ALU_SB_G2", /* name */
4962c51a
MS		 1141 FALSE, /* partial_inplace */
1142 0xffffffff, /* src_mask */
1143 0xffffffff, /* dst_mask */
1144 TRUE), /* pcrel_offset */
1145
07d6d2b8 1146 HOWTO (R_ARM_LDR_SB_G0, /* type */
4962c51a
MS		 1147 0, /* rightshift */
1148 2, /* size (0 = byte, 1 = short, 2 = long) */
1149 32, /* bitsize */
1150 TRUE, /* pc_relative */
1151 0, /* bitpos */
1152 complain_overflow_dont,/* complain_on_overflow */
1153 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1154 "R_ARM_LDR_SB_G0", /* name */
4962c51a
MS		 1155 FALSE, /* partial_inplace */
1156 0xffffffff, /* src_mask */
1157 0xffffffff, /* dst_mask */
1158 TRUE), /* pcrel_offset */
1159
07d6d2b8 1160 HOWTO (R_ARM_LDR_SB_G1, /* type */
4962c51a
MS		 1161 0, /* rightshift */
1162 2, /* size (0 = byte, 1 = short, 2 = long) */
1163 32, /* bitsize */
1164 TRUE, /* pc_relative */
1165 0, /* bitpos */
1166 complain_overflow_dont,/* complain_on_overflow */
1167 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1168 "R_ARM_LDR_SB_G1", /* name */
4962c51a
MS		 1169 FALSE, /* partial_inplace */
1170 0xffffffff, /* src_mask */
1171 0xffffffff, /* dst_mask */
1172 TRUE), /* pcrel_offset */
1173
07d6d2b8 1174 HOWTO (R_ARM_LDR_SB_G2, /* type */
4962c51a
MS		 1175 0, /* rightshift */
1176 2, /* size (0 = byte, 1 = short, 2 = long) */
1177 32, /* bitsize */
1178 TRUE, /* pc_relative */
1179 0, /* bitpos */
1180 complain_overflow_dont,/* complain_on_overflow */
1181 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1182 "R_ARM_LDR_SB_G2", /* name */
4962c51a
MS		 1183 FALSE, /* partial_inplace */
1184 0xffffffff, /* src_mask */
1185 0xffffffff, /* dst_mask */
1186 TRUE), /* pcrel_offset */
1187
07d6d2b8 1188 HOWTO (R_ARM_LDRS_SB_G0, /* type */
4962c51a
MS		 1189 0, /* rightshift */
1190 2, /* size (0 = byte, 1 = short, 2 = long) */
1191 32, /* bitsize */
1192 TRUE, /* pc_relative */
1193 0, /* bitpos */
1194 complain_overflow_dont,/* complain_on_overflow */
1195 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1196 "R_ARM_LDRS_SB_G0", /* name */
4962c51a
MS		 1197 FALSE, /* partial_inplace */
1198 0xffffffff, /* src_mask */
1199 0xffffffff, /* dst_mask */
1200 TRUE), /* pcrel_offset */
1201
07d6d2b8 1202 HOWTO (R_ARM_LDRS_SB_G1, /* type */
4962c51a
MS		 1203 0, /* rightshift */
1204 2, /* size (0 = byte, 1 = short, 2 = long) */
1205 32, /* bitsize */
1206 TRUE, /* pc_relative */
1207 0, /* bitpos */
1208 complain_overflow_dont,/* complain_on_overflow */
1209 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1210 "R_ARM_LDRS_SB_G1", /* name */
4962c51a
MS		 1211 FALSE, /* partial_inplace */
1212 0xffffffff, /* src_mask */
1213 0xffffffff, /* dst_mask */
1214 TRUE), /* pcrel_offset */
1215
07d6d2b8 1216 HOWTO (R_ARM_LDRS_SB_G2, /* type */
4962c51a
MS		 1217 0, /* rightshift */
1218 2, /* size (0 = byte, 1 = short, 2 = long) */
1219 32, /* bitsize */
1220 TRUE, /* pc_relative */
1221 0, /* bitpos */
1222 complain_overflow_dont,/* complain_on_overflow */
1223 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1224 "R_ARM_LDRS_SB_G2", /* name */
4962c51a
MS		 1225 FALSE, /* partial_inplace */
1226 0xffffffff, /* src_mask */
1227 0xffffffff, /* dst_mask */
1228 TRUE), /* pcrel_offset */
1229
07d6d2b8 1230 HOWTO (R_ARM_LDC_SB_G0, /* type */
4962c51a
MS		 1231 0, /* rightshift */
1232 2, /* size (0 = byte, 1 = short, 2 = long) */
1233 32, /* bitsize */
1234 TRUE, /* pc_relative */
1235 0, /* bitpos */
1236 complain_overflow_dont,/* complain_on_overflow */
1237 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1238 "R_ARM_LDC_SB_G0", /* name */
4962c51a
MS		 1239 FALSE, /* partial_inplace */
1240 0xffffffff, /* src_mask */
1241 0xffffffff, /* dst_mask */
1242 TRUE), /* pcrel_offset */
1243
07d6d2b8 1244 HOWTO (R_ARM_LDC_SB_G1, /* type */
4962c51a
MS		 1245 0, /* rightshift */
1246 2, /* size (0 = byte, 1 = short, 2 = long) */
1247 32, /* bitsize */
1248 TRUE, /* pc_relative */
1249 0, /* bitpos */
1250 complain_overflow_dont,/* complain_on_overflow */
1251 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1252 "R_ARM_LDC_SB_G1", /* name */
4962c51a
MS		 1253 FALSE, /* partial_inplace */
1254 0xffffffff, /* src_mask */
1255 0xffffffff, /* dst_mask */
1256 TRUE), /* pcrel_offset */
1257
07d6d2b8 1258 HOWTO (R_ARM_LDC_SB_G2, /* type */
4962c51a
MS		 1259 0, /* rightshift */
1260 2, /* size (0 = byte, 1 = short, 2 = long) */
1261 32, /* bitsize */
1262 TRUE, /* pc_relative */
1263 0, /* bitpos */
1264 complain_overflow_dont,/* complain_on_overflow */
1265 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1266 "R_ARM_LDC_SB_G2", /* name */
4962c51a
MS		 1267 FALSE, /* partial_inplace */
1268 0xffffffff, /* src_mask */
1269 0xffffffff, /* dst_mask */
1270 TRUE), /* pcrel_offset */
1271
1272 /* End of group relocations. */
c19d1205 1273
c19d1205
ZW		 1274 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1275 0, /* rightshift */
1276 2, /* size (0 = byte, 1 = short, 2 = long) */
1277 16, /* bitsize */
1278 FALSE, /* pc_relative */
1279 0, /* bitpos */
1280 complain_overflow_dont,/* complain_on_overflow */
1281 bfd_elf_generic_reloc, /* special_function */
1282 "R_ARM_MOVW_BREL_NC", /* name */
1283 FALSE, /* partial_inplace */
1284 0x0000ffff, /* src_mask */
1285 0x0000ffff, /* dst_mask */
1286 FALSE), /* pcrel_offset */
1287
1288 HOWTO (R_ARM_MOVT_BREL, /* type */
1289 0, /* rightshift */
1290 2, /* size (0 = byte, 1 = short, 2 = long) */
1291 16, /* bitsize */
1292 FALSE, /* pc_relative */
1293 0, /* bitpos */
1294 complain_overflow_bitfield,/* complain_on_overflow */
1295 bfd_elf_generic_reloc, /* special_function */
1296 "R_ARM_MOVT_BREL", /* name */
1297 FALSE, /* partial_inplace */
1298 0x0000ffff, /* src_mask */
1299 0x0000ffff, /* dst_mask */
1300 FALSE), /* pcrel_offset */
1301
1302 HOWTO (R_ARM_MOVW_BREL, /* type */
1303 0, /* rightshift */
1304 2, /* size (0 = byte, 1 = short, 2 = long) */
1305 16, /* bitsize */
1306 FALSE, /* pc_relative */
1307 0, /* bitpos */
1308 complain_overflow_dont,/* complain_on_overflow */
1309 bfd_elf_generic_reloc, /* special_function */
1310 "R_ARM_MOVW_BREL", /* name */
1311 FALSE, /* partial_inplace */
1312 0x0000ffff, /* src_mask */
1313 0x0000ffff, /* dst_mask */
1314 FALSE), /* pcrel_offset */
1315
1316 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1317 0, /* rightshift */
1318 2, /* size (0 = byte, 1 = short, 2 = long) */
1319 16, /* bitsize */
1320 FALSE, /* pc_relative */
1321 0, /* bitpos */
1322 complain_overflow_dont,/* complain_on_overflow */
1323 bfd_elf_generic_reloc, /* special_function */
1324 "R_ARM_THM_MOVW_BREL_NC",/* name */
1325 FALSE, /* partial_inplace */
1326 0x040f70ff, /* src_mask */
1327 0x040f70ff, /* dst_mask */
1328 FALSE), /* pcrel_offset */
1329
1330 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1331 0, /* rightshift */
1332 2, /* size (0 = byte, 1 = short, 2 = long) */
1333 16, /* bitsize */
1334 FALSE, /* pc_relative */
1335 0, /* bitpos */
1336 complain_overflow_bitfield,/* complain_on_overflow */
1337 bfd_elf_generic_reloc, /* special_function */
1338 "R_ARM_THM_MOVT_BREL", /* name */
1339 FALSE, /* partial_inplace */
1340 0x040f70ff, /* src_mask */
1341 0x040f70ff, /* dst_mask */
1342 FALSE), /* pcrel_offset */
1343
1344 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1345 0, /* rightshift */
1346 2, /* size (0 = byte, 1 = short, 2 = long) */
1347 16, /* bitsize */
1348 FALSE, /* pc_relative */
1349 0, /* bitpos */
1350 complain_overflow_dont,/* complain_on_overflow */
1351 bfd_elf_generic_reloc, /* special_function */
1352 "R_ARM_THM_MOVW_BREL", /* name */
1353 FALSE, /* partial_inplace */
1354 0x040f70ff, /* src_mask */
1355 0x040f70ff, /* dst_mask */
1356 FALSE), /* pcrel_offset */
1357
0855e32b
NS		 1358 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1359 0, /* rightshift */
1360 2, /* size (0 = byte, 1 = short, 2 = long) */
1361 32, /* bitsize */
1362 FALSE, /* pc_relative */
1363 0, /* bitpos */
1364 complain_overflow_bitfield,/* complain_on_overflow */
1365 NULL, /* special_function */
1366 "R_ARM_TLS_GOTDESC", /* name */
1367 TRUE, /* partial_inplace */
1368 0xffffffff, /* src_mask */
1369 0xffffffff, /* dst_mask */
1370 FALSE), /* pcrel_offset */
1371
1372 HOWTO (R_ARM_TLS_CALL, /* type */
1373 0, /* rightshift */
1374 2, /* size (0 = byte, 1 = short, 2 = long) */
1375 24, /* bitsize */
1376 FALSE, /* pc_relative */
1377 0, /* bitpos */
1378 complain_overflow_dont,/* complain_on_overflow */
1379 bfd_elf_generic_reloc, /* special_function */
1380 "R_ARM_TLS_CALL", /* name */
1381 FALSE, /* partial_inplace */
1382 0x00ffffff, /* src_mask */
1383 0x00ffffff, /* dst_mask */
1384 FALSE), /* pcrel_offset */
1385
1386 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1387 0, /* rightshift */
1388 2, /* size (0 = byte, 1 = short, 2 = long) */
1389 0, /* bitsize */
1390 FALSE, /* pc_relative */
1391 0, /* bitpos */
1392 complain_overflow_bitfield,/* complain_on_overflow */
1393 bfd_elf_generic_reloc, /* special_function */
1394 "R_ARM_TLS_DESCSEQ", /* name */
1395 FALSE, /* partial_inplace */
1396 0x00000000, /* src_mask */
1397 0x00000000, /* dst_mask */
1398 FALSE), /* pcrel_offset */
1399
1400 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1401 0, /* rightshift */
1402 2, /* size (0 = byte, 1 = short, 2 = long) */
1403 24, /* bitsize */
1404 FALSE, /* pc_relative */
1405 0, /* bitpos */
1406 complain_overflow_dont,/* complain_on_overflow */
1407 bfd_elf_generic_reloc, /* special_function */
1408 "R_ARM_THM_TLS_CALL", /* name */
1409 FALSE, /* partial_inplace */
1410 0x07ff07ff, /* src_mask */
1411 0x07ff07ff, /* dst_mask */
1412 FALSE), /* pcrel_offset */
c19d1205
ZW		 1413
1414 HOWTO (R_ARM_PLT32_ABS, /* type */
1415 0, /* rightshift */
1416 2, /* size (0 = byte, 1 = short, 2 = long) */
1417 32, /* bitsize */
1418 FALSE, /* pc_relative */
1419 0, /* bitpos */
1420 complain_overflow_dont,/* complain_on_overflow */
1421 bfd_elf_generic_reloc, /* special_function */
1422 "R_ARM_PLT32_ABS", /* name */
1423 FALSE, /* partial_inplace */
1424 0xffffffff, /* src_mask */
1425 0xffffffff, /* dst_mask */
1426 FALSE), /* pcrel_offset */
1427
1428 HOWTO (R_ARM_GOT_ABS, /* type */
1429 0, /* rightshift */
1430 2, /* size (0 = byte, 1 = short, 2 = long) */
1431 32, /* bitsize */
1432 FALSE, /* pc_relative */
1433 0, /* bitpos */
1434 complain_overflow_dont,/* complain_on_overflow */
1435 bfd_elf_generic_reloc, /* special_function */
1436 "R_ARM_GOT_ABS", /* name */
1437 FALSE, /* partial_inplace */
1438 0xffffffff, /* src_mask */
1439 0xffffffff, /* dst_mask */
1440 FALSE), /* pcrel_offset */
1441
1442 HOWTO (R_ARM_GOT_PREL, /* type */
1443 0, /* rightshift */
1444 2, /* size (0 = byte, 1 = short, 2 = long) */
1445 32, /* bitsize */
1446 TRUE, /* pc_relative */
1447 0, /* bitpos */
1448 complain_overflow_dont, /* complain_on_overflow */
1449 bfd_elf_generic_reloc, /* special_function */
1450 "R_ARM_GOT_PREL", /* name */
1451 FALSE, /* partial_inplace */
1452 0xffffffff, /* src_mask */
1453 0xffffffff, /* dst_mask */
1454 TRUE), /* pcrel_offset */
1455
1456 HOWTO (R_ARM_GOT_BREL12, /* type */
1457 0, /* rightshift */
1458 2, /* size (0 = byte, 1 = short, 2 = long) */
1459 12, /* bitsize */
1460 FALSE, /* pc_relative */
1461 0, /* bitpos */
1462 complain_overflow_bitfield,/* complain_on_overflow */
1463 bfd_elf_generic_reloc, /* special_function */
1464 "R_ARM_GOT_BREL12", /* name */
1465 FALSE, /* partial_inplace */
1466 0x00000fff, /* src_mask */
1467 0x00000fff, /* dst_mask */
1468 FALSE), /* pcrel_offset */
1469
1470 HOWTO (R_ARM_GOTOFF12, /* type */
1471 0, /* rightshift */
1472 2, /* size (0 = byte, 1 = short, 2 = long) */
1473 12, /* bitsize */
1474 FALSE, /* pc_relative */
1475 0, /* bitpos */
1476 complain_overflow_bitfield,/* complain_on_overflow */
1477 bfd_elf_generic_reloc, /* special_function */
1478 "R_ARM_GOTOFF12", /* name */
1479 FALSE, /* partial_inplace */
1480 0x00000fff, /* src_mask */
1481 0x00000fff, /* dst_mask */
1482 FALSE), /* pcrel_offset */
1483
07d6d2b8 1484 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
c19d1205
ZW		 1485
1486 /* GNU extension to record C++ vtable member usage */
07d6d2b8
AM		 1487 HOWTO (R_ARM_GNU_VTENTRY, /* type */
1488 0, /* rightshift */
1489 2, /* size (0 = byte, 1 = short, 2 = long) */
1490 0, /* bitsize */
1491 FALSE, /* pc_relative */
1492 0, /* bitpos */
99059e56 1493 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8
AM		 1494 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1495 "R_ARM_GNU_VTENTRY", /* name */
1496 FALSE, /* partial_inplace */
1497 0, /* src_mask */
1498 0, /* dst_mask */
1499 FALSE), /* pcrel_offset */
c19d1205
ZW		 1500
1501 /* GNU extension to record C++ vtable hierarchy */
1502 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
07d6d2b8
AM		 1503 0, /* rightshift */
1504 2, /* size (0 = byte, 1 = short, 2 = long) */
1505 0, /* bitsize */
1506 FALSE, /* pc_relative */
1507 0, /* bitpos */
99059e56 1508 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8 1509 NULL, /* special_function */
99059e56 1510 "R_ARM_GNU_VTINHERIT", /* name */
07d6d2b8
AM		 1511 FALSE, /* partial_inplace */
1512 0, /* src_mask */
1513 0, /* dst_mask */
1514 FALSE), /* pcrel_offset */
c19d1205
ZW		 1515
1516 HOWTO (R_ARM_THM_JUMP11, /* type */
1517 1, /* rightshift */
1518 1, /* size (0 = byte, 1 = short, 2 = long) */
1519 11, /* bitsize */
1520 TRUE, /* pc_relative */
1521 0, /* bitpos */
1522 complain_overflow_signed, /* complain_on_overflow */
1523 bfd_elf_generic_reloc, /* special_function */
1524 "R_ARM_THM_JUMP11", /* name */
1525 FALSE, /* partial_inplace */
1526 0x000007ff, /* src_mask */
1527 0x000007ff, /* dst_mask */
1528 TRUE), /* pcrel_offset */
1529
1530 HOWTO (R_ARM_THM_JUMP8, /* type */
1531 1, /* rightshift */
1532 1, /* size (0 = byte, 1 = short, 2 = long) */
1533 8, /* bitsize */
1534 TRUE, /* pc_relative */
1535 0, /* bitpos */
1536 complain_overflow_signed, /* complain_on_overflow */
1537 bfd_elf_generic_reloc, /* special_function */
1538 "R_ARM_THM_JUMP8", /* name */
1539 FALSE, /* partial_inplace */
1540 0x000000ff, /* src_mask */
1541 0x000000ff, /* dst_mask */
1542 TRUE), /* pcrel_offset */
ba93b8ac 1543
c19d1205
ZW		 1544 /* TLS relocations */
1545 HOWTO (R_ARM_TLS_GD32, /* type */
07d6d2b8
AM		 1546 0, /* rightshift */
1547 2, /* size (0 = byte, 1 = short, 2 = long) */
1548 32, /* bitsize */
1549 FALSE, /* pc_relative */
1550 0, /* bitpos */
99059e56
RM		 1551 complain_overflow_bitfield,/* complain_on_overflow */
1552 NULL, /* special_function */
1553 "R_ARM_TLS_GD32", /* name */
1554 TRUE, /* partial_inplace */
1555 0xffffffff, /* src_mask */
1556 0xffffffff, /* dst_mask */
07d6d2b8 1557 FALSE), /* pcrel_offset */
ba93b8ac 1558
ba93b8ac 1559 HOWTO (R_ARM_TLS_LDM32, /* type */
07d6d2b8
AM		 1560 0, /* rightshift */
1561 2, /* size (0 = byte, 1 = short, 2 = long) */
1562 32, /* bitsize */
1563 FALSE, /* pc_relative */
1564 0, /* bitpos */
99059e56
RM		 1565 complain_overflow_bitfield,/* complain_on_overflow */
1566 bfd_elf_generic_reloc, /* special_function */
1567 "R_ARM_TLS_LDM32", /* name */
1568 TRUE, /* partial_inplace */
1569 0xffffffff, /* src_mask */
1570 0xffffffff, /* dst_mask */
07d6d2b8 1571 FALSE), /* pcrel_offset */
ba93b8ac 1572
c19d1205 1573 HOWTO (R_ARM_TLS_LDO32, /* type */
07d6d2b8
AM		 1574 0, /* rightshift */
1575 2, /* size (0 = byte, 1 = short, 2 = long) */
1576 32, /* bitsize */
1577 FALSE, /* pc_relative */
1578 0, /* bitpos */
99059e56
RM		 1579 complain_overflow_bitfield,/* complain_on_overflow */
1580 bfd_elf_generic_reloc, /* special_function */
1581 "R_ARM_TLS_LDO32", /* name */
1582 TRUE, /* partial_inplace */
1583 0xffffffff, /* src_mask */
1584 0xffffffff, /* dst_mask */
07d6d2b8 1585 FALSE), /* pcrel_offset */
ba93b8ac 1586
ba93b8ac 1587 HOWTO (R_ARM_TLS_IE32, /* type */
07d6d2b8
AM		 1588 0, /* rightshift */
1589 2, /* size (0 = byte, 1 = short, 2 = long) */
1590 32, /* bitsize */
1591 FALSE, /* pc_relative */
1592 0, /* bitpos */
99059e56
RM		 1593 complain_overflow_bitfield,/* complain_on_overflow */
1594 NULL, /* special_function */
1595 "R_ARM_TLS_IE32", /* name */
1596 TRUE, /* partial_inplace */
1597 0xffffffff, /* src_mask */
1598 0xffffffff, /* dst_mask */
07d6d2b8 1599 FALSE), /* pcrel_offset */
7f266840 1600
c19d1205 1601 HOWTO (R_ARM_TLS_LE32, /* type */
07d6d2b8
AM		 1602 0, /* rightshift */
1603 2, /* size (0 = byte, 1 = short, 2 = long) */
1604 32, /* bitsize */
1605 FALSE, /* pc_relative */
1606 0, /* bitpos */
99059e56 1607 complain_overflow_bitfield,/* complain_on_overflow */
07d6d2b8 1608 NULL, /* special_function */
99059e56
RM		 1609 "R_ARM_TLS_LE32", /* name */
1610 TRUE, /* partial_inplace */
1611 0xffffffff, /* src_mask */
1612 0xffffffff, /* dst_mask */
07d6d2b8 1613 FALSE), /* pcrel_offset */
7f266840 1614
c19d1205
ZW		 1615 HOWTO (R_ARM_TLS_LDO12, /* type */
1616 0, /* rightshift */
1617 2, /* size (0 = byte, 1 = short, 2 = long) */
1618 12, /* bitsize */
1619 FALSE, /* pc_relative */
7f266840 1620 0, /* bitpos */
c19d1205 1621 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1622 bfd_elf_generic_reloc, /* special_function */
c19d1205 1623 "R_ARM_TLS_LDO12", /* name */
7f266840 1624 FALSE, /* partial_inplace */
c19d1205
ZW		 1625 0x00000fff, /* src_mask */
1626 0x00000fff, /* dst_mask */
1627 FALSE), /* pcrel_offset */
7f266840 1628
c19d1205
ZW		 1629 HOWTO (R_ARM_TLS_LE12, /* type */
1630 0, /* rightshift */
1631 2, /* size (0 = byte, 1 = short, 2 = long) */
1632 12, /* bitsize */
1633 FALSE, /* pc_relative */
7f266840 1634 0, /* bitpos */
c19d1205 1635 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1636 bfd_elf_generic_reloc, /* special_function */
c19d1205 1637 "R_ARM_TLS_LE12", /* name */
7f266840 1638 FALSE, /* partial_inplace */
c19d1205
ZW		 1639 0x00000fff, /* src_mask */
1640 0x00000fff, /* dst_mask */
1641 FALSE), /* pcrel_offset */
7f266840 1642
c19d1205 1643 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1644 0, /* rightshift */
1645 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1646 12, /* bitsize */
1647 FALSE, /* pc_relative */
7f266840 1648 0, /* bitpos */
c19d1205 1649 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1650 bfd_elf_generic_reloc, /* special_function */
c19d1205 1651 "R_ARM_TLS_IE12GP", /* name */
7f266840 1652 FALSE, /* partial_inplace */
c19d1205
ZW		 1653 0x00000fff, /* src_mask */
1654 0x00000fff, /* dst_mask */
1655 FALSE), /* pcrel_offset */
0855e32b 1656
34e77a92 1657 /* 112-127 private relocations. */
0855e32b
NS		 1658 EMPTY_HOWTO (112),
1659 EMPTY_HOWTO (113),
1660 EMPTY_HOWTO (114),
1661 EMPTY_HOWTO (115),
1662 EMPTY_HOWTO (116),
1663 EMPTY_HOWTO (117),
1664 EMPTY_HOWTO (118),
1665 EMPTY_HOWTO (119),
1666 EMPTY_HOWTO (120),
1667 EMPTY_HOWTO (121),
1668 EMPTY_HOWTO (122),
1669 EMPTY_HOWTO (123),
1670 EMPTY_HOWTO (124),
1671 EMPTY_HOWTO (125),
1672 EMPTY_HOWTO (126),
1673 EMPTY_HOWTO (127),
34e77a92
RS		 1674
1675 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1676 EMPTY_HOWTO (128),
1677
1678 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1679 0, /* rightshift */
1680 1, /* size (0 = byte, 1 = short, 2 = long) */
1681 0, /* bitsize */
1682 FALSE, /* pc_relative */
1683 0, /* bitpos */
1684 complain_overflow_bitfield,/* complain_on_overflow */
1685 bfd_elf_generic_reloc, /* special_function */
1686 "R_ARM_THM_TLS_DESCSEQ",/* name */
1687 FALSE, /* partial_inplace */
1688 0x00000000, /* src_mask */
1689 0x00000000, /* dst_mask */
1690 FALSE), /* pcrel_offset */
72d98d16
MG		 1691 EMPTY_HOWTO (130),
1692 EMPTY_HOWTO (131),
1693 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1694 0, /* rightshift. */
1695 1, /* size (0 = byte, 1 = short, 2 = long). */
1696 16, /* bitsize. */
1697 FALSE, /* pc_relative. */
1698 0, /* bitpos. */
1699 complain_overflow_bitfield,/* complain_on_overflow. */
1700 bfd_elf_generic_reloc, /* special_function. */
1701 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1702 FALSE, /* partial_inplace. */
1703 0x00000000, /* src_mask. */
1704 0x00000000, /* dst_mask. */
1705 FALSE), /* pcrel_offset. */
1706 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1707 0, /* rightshift. */
1708 1, /* size (0 = byte, 1 = short, 2 = long). */
1709 16, /* bitsize. */
1710 FALSE, /* pc_relative. */
1711 0, /* bitpos. */
1712 complain_overflow_bitfield,/* complain_on_overflow. */
1713 bfd_elf_generic_reloc, /* special_function. */
1714 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1715 FALSE, /* partial_inplace. */
1716 0x00000000, /* src_mask. */
1717 0x00000000, /* dst_mask. */
1718 FALSE), /* pcrel_offset. */
1719 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1720 0, /* rightshift. */
1721 1, /* size (0 = byte, 1 = short, 2 = long). */
1722 16, /* bitsize. */
1723 FALSE, /* pc_relative. */
1724 0, /* bitpos. */
1725 complain_overflow_bitfield,/* complain_on_overflow. */
1726 bfd_elf_generic_reloc, /* special_function. */
1727 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1728 FALSE, /* partial_inplace. */
1729 0x00000000, /* src_mask. */
1730 0x00000000, /* dst_mask. */
1731 FALSE), /* pcrel_offset. */
1732 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1733 0, /* rightshift. */
1734 1, /* size (0 = byte, 1 = short, 2 = long). */
1735 16, /* bitsize. */
1736 FALSE, /* pc_relative. */
1737 0, /* bitpos. */
1738 complain_overflow_bitfield,/* complain_on_overflow. */
1739 bfd_elf_generic_reloc, /* special_function. */
1740 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1741 FALSE, /* partial_inplace. */
1742 0x00000000, /* src_mask. */
1743 0x00000000, /* dst_mask. */
1744 FALSE), /* pcrel_offset. */
e5d6e09e
AV		 1745 /* Relocations for Armv8.1-M Mainline. */
1746 HOWTO (R_ARM_THM_BF16, /* type. */
1747 0, /* rightshift. */
1748 1, /* size (0 = byte, 1 = short, 2 = long). */
1749 16, /* bitsize. */
1750 TRUE, /* pc_relative. */
1751 0, /* bitpos. */
1752 complain_overflow_dont,/* do not complain_on_overflow. */
1753 bfd_elf_generic_reloc, /* special_function. */
1754 "R_ARM_THM_BF16", /* name. */
1755 FALSE, /* partial_inplace. */
1756 0x001f0ffe, /* src_mask. */
1757 0x001f0ffe, /* dst_mask. */
1758 TRUE), /* pcrel_offset. */
1caf72a5
AV		 1759 EMPTY_HOWTO (137),
1760 HOWTO (R_ARM_THM_BF18, /* type. */
1761 0, /* rightshift. */
1762 1, /* size (0 = byte, 1 = short, 2 = long). */
1763 18, /* bitsize. */
1764 TRUE, /* pc_relative. */
1765 0, /* bitpos. */
1766 complain_overflow_dont,/* do not complain_on_overflow. */
1767 bfd_elf_generic_reloc, /* special_function. */
1768 "R_ARM_THM_BF18", /* name. */
1769 FALSE, /* partial_inplace. */
1770 0x007f0ffe, /* src_mask. */
1771 0x007f0ffe, /* dst_mask. */
1772 TRUE), /* pcrel_offset. */
c19d1205
ZW		 1773};
1774
34e77a92 1775/* 160 onwards: */
5c5a4843 1776static reloc_howto_type elf32_arm_howto_table_2[8] =
34e77a92
RS		 1777{
1778 HOWTO (R_ARM_IRELATIVE, /* type */
07d6d2b8
AM		 1779 0, /* rightshift */
1780 2, /* size (0 = byte, 1 = short, 2 = long) */
1781 32, /* bitsize */
1782 FALSE, /* pc_relative */
1783 0, /* bitpos */
99059e56
RM		 1784 complain_overflow_bitfield,/* complain_on_overflow */
1785 bfd_elf_generic_reloc, /* special_function */
1786 "R_ARM_IRELATIVE", /* name */
1787 TRUE, /* partial_inplace */
1788 0xffffffff, /* src_mask */
1789 0xffffffff, /* dst_mask */
188fd7ae
CL		 1790 FALSE), /* pcrel_offset */
1791 HOWTO (R_ARM_GOTFUNCDESC, /* type */
1792 0, /* rightshift */
1793 2, /* size (0 = byte, 1 = short, 2 = long) */
1794 32, /* bitsize */
1795 FALSE, /* pc_relative */
1796 0, /* bitpos */
1797 complain_overflow_bitfield,/* complain_on_overflow */
1798 bfd_elf_generic_reloc, /* special_function */
1799 "R_ARM_GOTFUNCDESC", /* name */
1800 FALSE, /* partial_inplace */
1801 0, /* src_mask */
1802 0xffffffff, /* dst_mask */
1803 FALSE), /* pcrel_offset */
1804 HOWTO (R_ARM_GOTOFFFUNCDESC, /* type */
1805 0, /* rightshift */
1806 2, /* size (0 = byte, 1 = short, 2 = long) */
1807 32, /* bitsize */
1808 FALSE, /* pc_relative */
1809 0, /* bitpos */
1810 complain_overflow_bitfield,/* complain_on_overflow */
1811 bfd_elf_generic_reloc, /* special_function */
1812 "R_ARM_GOTOFFFUNCDESC",/* name */
1813 FALSE, /* partial_inplace */
1814 0, /* src_mask */
1815 0xffffffff, /* dst_mask */
1816 FALSE), /* pcrel_offset */
1817 HOWTO (R_ARM_FUNCDESC, /* type */
1818 0, /* rightshift */
1819 2, /* size (0 = byte, 1 = short, 2 = long) */
1820 32, /* bitsize */
1821 FALSE, /* pc_relative */
1822 0, /* bitpos */
1823 complain_overflow_bitfield,/* complain_on_overflow */
1824 bfd_elf_generic_reloc, /* special_function */
1825 "R_ARM_FUNCDESC", /* name */
1826 FALSE, /* partial_inplace */
1827 0, /* src_mask */
1828 0xffffffff, /* dst_mask */
1829 FALSE), /* pcrel_offset */
1830 HOWTO (R_ARM_FUNCDESC_VALUE, /* type */
1831 0, /* rightshift */
1832 2, /* size (0 = byte, 1 = short, 2 = long) */
1833 64, /* bitsize */
1834 FALSE, /* pc_relative */
1835 0, /* bitpos */
1836 complain_overflow_bitfield,/* complain_on_overflow */
1837 bfd_elf_generic_reloc, /* special_function */
1838 "R_ARM_FUNCDESC_VALUE",/* name */
1839 FALSE, /* partial_inplace */
1840 0, /* src_mask */
1841 0xffffffff, /* dst_mask */
1842 FALSE), /* pcrel_offset */
5c5a4843
CL		 1843 HOWTO (R_ARM_TLS_GD32_FDPIC, /* type */
1844 0, /* rightshift */
1845 2, /* size (0 = byte, 1 = short, 2 = long) */
1846 32, /* bitsize */
1847 FALSE, /* pc_relative */
1848 0, /* bitpos */
1849 complain_overflow_bitfield,/* complain_on_overflow */
1850 bfd_elf_generic_reloc, /* special_function */
1851 "R_ARM_TLS_GD32_FDPIC",/* name */
1852 FALSE, /* partial_inplace */
1853 0, /* src_mask */
1854 0xffffffff, /* dst_mask */
1855 FALSE), /* pcrel_offset */
1856 HOWTO (R_ARM_TLS_LDM32_FDPIC, /* type */
1857 0, /* rightshift */
1858 2, /* size (0 = byte, 1 = short, 2 = long) */
1859 32, /* bitsize */
1860 FALSE, /* pc_relative */
1861 0, /* bitpos */
1862 complain_overflow_bitfield,/* complain_on_overflow */
1863 bfd_elf_generic_reloc, /* special_function */
1864 "R_ARM_TLS_LDM32_FDPIC",/* name */
1865 FALSE, /* partial_inplace */
1866 0, /* src_mask */
1867 0xffffffff, /* dst_mask */
1868 FALSE), /* pcrel_offset */
1869 HOWTO (R_ARM_TLS_IE32_FDPIC, /* type */
1870 0, /* rightshift */
1871 2, /* size (0 = byte, 1 = short, 2 = long) */
1872 32, /* bitsize */
1873 FALSE, /* pc_relative */
1874 0, /* bitpos */
1875 complain_overflow_bitfield,/* complain_on_overflow */
1876 bfd_elf_generic_reloc, /* special_function */
1877 "R_ARM_TLS_IE32_FDPIC",/* name */
1878 FALSE, /* partial_inplace */
1879 0, /* src_mask */
1880 0xffffffff, /* dst_mask */
1881 FALSE), /* pcrel_offset */
34e77a92 1882};
c19d1205 1883
34e77a92
RS		 1884/* 249-255 extended, currently unused, relocations: */
1885static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1886{
1887 HOWTO (R_ARM_RREL32, /* type */
1888 0, /* rightshift */
1889 0, /* size (0 = byte, 1 = short, 2 = long) */
1890 0, /* bitsize */
1891 FALSE, /* pc_relative */
1892 0, /* bitpos */
1893 complain_overflow_dont,/* complain_on_overflow */
1894 bfd_elf_generic_reloc, /* special_function */
1895 "R_ARM_RREL32", /* name */
1896 FALSE, /* partial_inplace */
1897 0, /* src_mask */
1898 0, /* dst_mask */
1899 FALSE), /* pcrel_offset */
1900
1901 HOWTO (R_ARM_RABS32, /* type */
1902 0, /* rightshift */
1903 0, /* size (0 = byte, 1 = short, 2 = long) */
1904 0, /* bitsize */
1905 FALSE, /* pc_relative */
1906 0, /* bitpos */
1907 complain_overflow_dont,/* complain_on_overflow */
1908 bfd_elf_generic_reloc, /* special_function */
1909 "R_ARM_RABS32", /* name */
1910 FALSE, /* partial_inplace */
1911 0, /* src_mask */
1912 0, /* dst_mask */
1913 FALSE), /* pcrel_offset */
1914
1915 HOWTO (R_ARM_RPC24, /* type */
1916 0, /* rightshift */
1917 0, /* size (0 = byte, 1 = short, 2 = long) */
1918 0, /* bitsize */
1919 FALSE, /* pc_relative */
1920 0, /* bitpos */
1921 complain_overflow_dont,/* complain_on_overflow */
1922 bfd_elf_generic_reloc, /* special_function */
1923 "R_ARM_RPC24", /* name */
1924 FALSE, /* partial_inplace */
1925 0, /* src_mask */
1926 0, /* dst_mask */
1927 FALSE), /* pcrel_offset */
1928
1929 HOWTO (R_ARM_RBASE, /* type */
1930 0, /* rightshift */
1931 0, /* size (0 = byte, 1 = short, 2 = long) */
1932 0, /* bitsize */
1933 FALSE, /* pc_relative */
1934 0, /* bitpos */
1935 complain_overflow_dont,/* complain_on_overflow */
1936 bfd_elf_generic_reloc, /* special_function */
1937 "R_ARM_RBASE", /* name */
1938 FALSE, /* partial_inplace */
1939 0, /* src_mask */
1940 0, /* dst_mask */
1941 FALSE) /* pcrel_offset */
1942};
1943
1944static reloc_howto_type *
1945elf32_arm_howto_from_type (unsigned int r_type)
1946{
906e58ca 1947 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1948 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1949
188fd7ae
CL		 1950 if (r_type >= R_ARM_IRELATIVE
1951 && r_type < R_ARM_IRELATIVE + ARRAY_SIZE (elf32_arm_howto_table_2))
34e77a92
RS		 1952 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1953
c19d1205 1954 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1955 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1956 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1957
c19d1205 1958 return NULL;
7f266840
DJ		 1959}
1960
f3185997
NC		 1961static bfd_boolean
1962elf32_arm_info_to_howto (bfd * abfd, arelent * bfd_reloc,
7f266840
DJ		 1963 Elf_Internal_Rela * elf_reloc)
1964{
1965 unsigned int r_type;
1966
1967 r_type = ELF32_R_TYPE (elf_reloc->r_info);
f3185997
NC		 1968 if ((bfd_reloc->howto = elf32_arm_howto_from_type (r_type)) == NULL)
1969 {
1970 /* xgettext:c-format */
1971 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
1972 abfd, r_type);
1973 bfd_set_error (bfd_error_bad_value);
1974 return FALSE;
1975 }
1976 return TRUE;
7f266840
DJ		 1977}
1978
1979struct elf32_arm_reloc_map
1980 {
1981 bfd_reloc_code_real_type bfd_reloc_val;
07d6d2b8 1982 unsigned char elf_reloc_val;
7f266840
DJ		 1983 };
1984
1985/* All entries in this list must also be present in elf32_arm_howto_table. */
1986static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1987 {
07d6d2b8 1988 {BFD_RELOC_NONE, R_ARM_NONE},
7f266840 1989 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1990 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1991 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
07d6d2b8
AM		 1992 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1993 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1994 {BFD_RELOC_32, R_ARM_ABS32},
1995 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1996 {BFD_RELOC_8, R_ARM_ABS8},
1997 {BFD_RELOC_16, R_ARM_ABS16},
1998 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
7f266840 1999 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 2000 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
2001 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
2002 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
2003 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
2004 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
2005 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
07d6d2b8
AM		 2006 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
2007 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
2008 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
2009 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
2010 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
2011 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
2012 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
2013 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
7f266840
DJ		 2014 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
2015 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
2016 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
2017 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac 2018 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
07d6d2b8
AM		 2019 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
2020 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
2021 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
0855e32b 2022 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
07d6d2b8 2023 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
0855e32b 2024 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
07d6d2b8 2025 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 2026 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
2027 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
2028 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
2029 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
2030 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
07d6d2b8
AM		 2031 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
2032 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
2033 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
2034 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
188fd7ae
CL		 2035 {BFD_RELOC_ARM_GOTFUNCDESC, R_ARM_GOTFUNCDESC},
2036 {BFD_RELOC_ARM_GOTOFFFUNCDESC, R_ARM_GOTOFFFUNCDESC},
2037 {BFD_RELOC_ARM_FUNCDESC, R_ARM_FUNCDESC},
2038 {BFD_RELOC_ARM_FUNCDESC_VALUE, R_ARM_FUNCDESC_VALUE},
5c5a4843
CL		 2039 {BFD_RELOC_ARM_TLS_GD32_FDPIC, R_ARM_TLS_GD32_FDPIC},
2040 {BFD_RELOC_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_LDM32_FDPIC},
2041 {BFD_RELOC_ARM_TLS_IE32_FDPIC, R_ARM_TLS_IE32_FDPIC},
c19d1205
ZW		 2042 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
2043 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 2044 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
2045 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
2046 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
2047 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
2048 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
2049 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
2050 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
2051 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 2052 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
2053 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
2054 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
2055 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
2056 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
2057 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
2058 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
2059 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
2060 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
2061 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
2062 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
2063 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
2064 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
2065 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
2066 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
2067 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
2068 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
2069 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
2070 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
2071 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
2072 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
2073 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
2074 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
2075 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
2076 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
2077 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
2078 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 2079 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 2080 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
2081 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
2082 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
2083 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
e5d6e09e 2084 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC},
1caf72a5
AV		 2085 {BFD_RELOC_ARM_THUMB_BF17, R_ARM_THM_BF16},
2086 {BFD_RELOC_ARM_THUMB_BF19, R_ARM_THM_BF18}
7f266840
DJ		 2087 };
2088
2089static reloc_howto_type *
f1c71a59
ZW		 2090elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2091 bfd_reloc_code_real_type code)
7f266840
DJ		 2092{
2093 unsigned int i;
8029a119 2094
906e58ca 2095 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 2096 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
2097 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 2098
c19d1205 2099 return NULL;
7f266840
DJ		 2100}
2101
157090f7
AM		 2102static reloc_howto_type *
2103elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2104 const char *r_name)
2105{
2106 unsigned int i;
2107
906e58ca 2108 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 2109 if (elf32_arm_howto_table_1[i].name != NULL
2110 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
2111 return &elf32_arm_howto_table_1[i];
2112
906e58ca 2113 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 2114 if (elf32_arm_howto_table_2[i].name != NULL
2115 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
2116 return &elf32_arm_howto_table_2[i];
2117
34e77a92
RS		 2118 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
2119 if (elf32_arm_howto_table_3[i].name != NULL
2120 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
2121 return &elf32_arm_howto_table_3[i];
2122
157090f7
AM		 2123 return NULL;
2124}
2125
906e58ca
NC		 2126/* Support for core dump NOTE sections. */
2127
7f266840 2128static bfd_boolean
f1c71a59 2129elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2130{
2131 int offset;
2132 size_t size;
2133
2134 switch (note->descsz)
2135 {
2136 default:
2137 return FALSE;
2138
8029a119 2139 case 148: /* Linux/ARM 32-bit. */
7f266840 2140 /* pr_cursig */
228e534f 2141 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2142
2143 /* pr_pid */
228e534f 2144 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2145
2146 /* pr_reg */
2147 offset = 72;
2148 size = 72;
2149
2150 break;
2151 }
2152
2153 /* Make a ".reg/999" section. */
2154 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2155 size, note->descpos + offset);
2156}
2157
2158static bfd_boolean
f1c71a59 2159elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2160{
2161 switch (note->descsz)
2162 {
2163 default:
2164 return FALSE;
2165
8029a119 2166 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2167 elf_tdata (abfd)->core->pid
4395ee08 2168 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2169 elf_tdata (abfd)->core->program
7f266840 2170 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2171 elf_tdata (abfd)->core->command
7f266840
DJ		 2172 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2173 }
2174
2175 /* Note that for some reason, a spurious space is tacked
2176 onto the end of the args in some (at least one anyway)
2177 implementations, so strip it off if it exists. */
7f266840 2178 {
228e534f 2179 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2180 int n = strlen (command);
2181
2182 if (0 < n && command[n - 1] == ' ')
2183 command[n - 1] = '\0';
2184 }
2185
2186 return TRUE;
2187}
2188
1f20dca5
UW		 2189static char *
2190elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2191 int note_type, ...)
2192{
2193 switch (note_type)
2194 {
2195 default:
2196 return NULL;
2197
2198 case NT_PRPSINFO:
2199 {
602f1657 2200 char data[124] ATTRIBUTE_NONSTRING;
1f20dca5
UW		 2201 va_list ap;
2202
2203 va_start (ap, note_type);
2204 memset (data, 0, sizeof (data));
2205 strncpy (data + 28, va_arg (ap, const char *), 16);
be3e27bb 2206#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2207 DIAGNOSTIC_PUSH;
be3e27bb 2208 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
95da9854
L		 2209 -Wstringop-truncation:
2210 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2211 */
95da9854
L		 2212 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2213#endif
1f20dca5 2214 strncpy (data + 44, va_arg (ap, const char *), 80);
be3e27bb 2215#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2216 DIAGNOSTIC_POP;
fe75810f 2217#endif
1f20dca5
UW		 2218 va_end (ap);
2219
2220 return elfcore_write_note (abfd, buf, bufsiz,
2221 "CORE", note_type, data, sizeof (data));
2222 }
2223
2224 case NT_PRSTATUS:
2225 {
2226 char data[148];
2227 va_list ap;
2228 long pid;
2229 int cursig;
2230 const void *greg;
2231
2232 va_start (ap, note_type);
2233 memset (data, 0, sizeof (data));
2234 pid = va_arg (ap, long);
2235 bfd_put_32 (abfd, pid, data + 24);
2236 cursig = va_arg (ap, int);
2237 bfd_put_16 (abfd, cursig, data + 12);
2238 greg = va_arg (ap, const void *);
2239 memcpy (data + 72, greg, 72);
2240 va_end (ap);
2241
2242 return elfcore_write_note (abfd, buf, bufsiz,
2243 "CORE", note_type, data, sizeof (data));
2244 }
2245 }
2246}
2247
07d6d2b8
AM		 2248#define TARGET_LITTLE_SYM arm_elf32_le_vec
2249#define TARGET_LITTLE_NAME "elf32-littlearm"
2250#define TARGET_BIG_SYM arm_elf32_be_vec
2251#define TARGET_BIG_NAME "elf32-bigarm"
7f266840
DJ		 2252
2253#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2254#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2255#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2256
252b5132
RH		 2257typedef unsigned long int insn32;
2258typedef unsigned short int insn16;
2259
3a4a14e9
PB		 2260/* In lieu of proper flags, assume all EABIv4 or later objects are
2261 interworkable. */
57e8b36a 2262#define INTERWORK_FLAG(abfd) \
3a4a14e9 2263 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2264 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2265 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2266
252b5132
RH		 2267/* The linker script knows the section names for placement.
2268 The entry_names are used to do simple name mangling on the stubs.
2269 Given a function name, and its type, the stub can be found. The
9b485d32 2270 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2271#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2272#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2273
2274#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2275#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2276
c7b8f16e
JB		 2277#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2278#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2279
a504d23a
LA		 2280#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2281#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2282
845b51d6
PB		 2283#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2284#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2285
7413f23f
DJ		 2286#define STUB_ENTRY_NAME "__%s_veneer"
2287
4ba2ef8f
TP		 2288#define CMSE_PREFIX "__acle_se_"
2289
252b5132
RH		 2290/* The name of the dynamic interpreter. This is put in the .interp
2291 section. */
2292#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2293
cb10292c
CL		 2294/* FDPIC default stack size. */
2295#define DEFAULT_STACK_SIZE 0x8000
2296
0855e32b 2297static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2298{
2299 0xe08e0000, /* add r0, lr, r0 */
2300 0xe5901004, /* ldr r1, [r0,#4] */
2301 0xe12fff11, /* bx r1 */
2302};
0855e32b
NS		 2303
2304static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2305{
2306 0xe52d2004, /* push {r2} */
2307 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2308 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2309 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2310 0xe081100f, /* 2: add r1, pc */
2311 0xe12fff12, /* bx r2 */
2312 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2313 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2314 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2315};
0855e32b 2316
7801f98f
CL		 2317/* ARM FDPIC PLT entry. */
2318/* The last 5 words contain PLT lazy fragment code and data. */
2319static const bfd_vma elf32_arm_fdpic_plt_entry [] =
2320 {
2321 0xe59fc008, /* ldr r12, .L1 */
2322 0xe08cc009, /* add r12, r12, r9 */
2323 0xe59c9004, /* ldr r9, [r12, #4] */
2324 0xe59cf000, /* ldr pc, [r12] */
2325 0x00000000, /* L1. .word foo(GOTOFFFUNCDESC) */
2326 0x00000000, /* L1. .word foo(funcdesc_value_reloc_offset) */
2327 0xe51fc00c, /* ldr r12, [pc, #-12] */
2328 0xe92d1000, /* push {r12} */
2329 0xe599c004, /* ldr r12, [r9, #4] */
2330 0xe599f000, /* ldr pc, [r9] */
2331 };
2332
59029f57
CL		 2333/* Thumb FDPIC PLT entry. */
2334/* The last 5 words contain PLT lazy fragment code and data. */
2335static const bfd_vma elf32_arm_fdpic_thumb_plt_entry [] =
2336 {
2337 0xc00cf8df, /* ldr.w r12, .L1 */
2338 0x0c09eb0c, /* add.w r12, r12, r9 */
2339 0x9004f8dc, /* ldr.w r9, [r12, #4] */
2340 0xf000f8dc, /* ldr.w pc, [r12] */
2341 0x00000000, /* .L1 .word foo(GOTOFFFUNCDESC) */
2342 0x00000000, /* .L2 .word foo(funcdesc_value_reloc_offset) */
2343 0xc008f85f, /* ldr.w r12, .L2 */
2344 0xcd04f84d, /* push {r12} */
2345 0xc004f8d9, /* ldr.w r12, [r9, #4] */
2346 0xf000f8d9, /* ldr.w pc, [r9] */
2347 };
2348
5e681ec4
PB		 2349#ifdef FOUR_WORD_PLT
2350
252b5132
RH		 2351/* The first entry in a procedure linkage table looks like
2352 this. It is set up so that any shared library function that is
59f2c4e7 2353 called before the relocation has been set up calls the dynamic
9b485d32 2354 linker first. */
e5a52504 2355static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2356{
2357 0xe52de004, /* str lr, [sp, #-4]! */
2358 0xe59fe010, /* ldr lr, [pc, #16] */
2359 0xe08fe00e, /* add lr, pc, lr */
2360 0xe5bef008, /* ldr pc, [lr, #8]! */
2361};
5e681ec4
PB		 2362
2363/* Subsequent entries in a procedure linkage table look like
2364 this. */
e5a52504 2365static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2366{
2367 0xe28fc600, /* add ip, pc, #NN */
2368 0xe28cca00, /* add ip, ip, #NN */
2369 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2370 0x00000000, /* unused */
2371};
5e681ec4 2372
eed94f8f 2373#else /* not FOUR_WORD_PLT */
5e681ec4 2374
5e681ec4
PB		 2375/* The first entry in a procedure linkage table looks like
2376 this. It is set up so that any shared library function that is
2377 called before the relocation has been set up calls the dynamic
2378 linker first. */
e5a52504 2379static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb 2380{
07d6d2b8
AM		 2381 0xe52de004, /* str lr, [sp, #-4]! */
2382 0xe59fe004, /* ldr lr, [pc, #4] */
2383 0xe08fe00e, /* add lr, pc, lr */
2384 0xe5bef008, /* ldr pc, [lr, #8]! */
2385 0x00000000, /* &GOT[0] - . */
b38cadfb 2386};
252b5132 2387
1db37fe6
YG		 2388/* By default subsequent entries in a procedure linkage table look like
2389 this. Offsets that don't fit into 28 bits will cause link error. */
2390static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2391{
2392 0xe28fc600, /* add ip, pc, #0xNN00000 */
2393 0xe28cca00, /* add ip, ip, #0xNN000 */
2394 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2395};
5e681ec4 2396
1db37fe6
YG		 2397/* When explicitly asked, we'll use this "long" entry format
2398 which can cope with arbitrary displacements. */
2399static const bfd_vma elf32_arm_plt_entry_long [] =
2400{
07d6d2b8
AM		 2401 0xe28fc200, /* add ip, pc, #0xN0000000 */
2402 0xe28cc600, /* add ip, ip, #0xNN00000 */
1db37fe6
YG		 2403 0xe28cca00, /* add ip, ip, #0xNN000 */
2404 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2405};
2406
2407static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2408
eed94f8f
NC		 2409#endif /* not FOUR_WORD_PLT */
2410
2411/* The first entry in a procedure linkage table looks like this.
2412 It is set up so that any shared library function that is called before the
2413 relocation has been set up calls the dynamic linker first. */
2414static const bfd_vma elf32_thumb2_plt0_entry [] =
2415{
2416 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2417 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2418 0xf8dfb500, /* push {lr} */
2419 0x44fee008, /* ldr.w lr, [pc, #8] */
2420 /* add lr, pc */
eed94f8f 2421 0xff08f85e, /* ldr.w pc, [lr, #8]! */
07d6d2b8 2422 0x00000000, /* &GOT[0] - . */
eed94f8f
NC		 2423};
2424
2425/* Subsequent entries in a procedure linkage table for thumb only target
2426 look like this. */
2427static const bfd_vma elf32_thumb2_plt_entry [] =
2428{
2429 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2430 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2431 0x0c00f240, /* movw ip, #0xNNNN */
2432 0x0c00f2c0, /* movt ip, #0xNNNN */
2433 0xf8dc44fc, /* add ip, pc */
2434 0xbf00f000 /* ldr.w pc, [ip] */
2435 /* nop */
eed94f8f 2436};
252b5132 2437
00a97672
RS		 2438/* The format of the first entry in the procedure linkage table
2439 for a VxWorks executable. */
2440static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb 2441{
07d6d2b8
AM		 2442 0xe52dc008, /* str ip,[sp,#-8]! */
2443 0xe59fc000, /* ldr ip,[pc] */
2444 0xe59cf008, /* ldr pc,[ip,#8] */
2445 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
b38cadfb 2446};
00a97672
RS		 2447
2448/* The format of subsequent entries in a VxWorks executable. */
2449static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb 2450{
07d6d2b8
AM		 2451 0xe59fc000, /* ldr ip,[pc] */
2452 0xe59cf000, /* ldr pc,[ip] */
2453 0x00000000, /* .long @got */
2454 0xe59fc000, /* ldr ip,[pc] */
2455 0xea000000, /* b _PLT */
2456 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2457};
00a97672
RS		 2458
2459/* The format of entries in a VxWorks shared library. */
2460static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb 2461{
07d6d2b8
AM		 2462 0xe59fc000, /* ldr ip,[pc] */
2463 0xe79cf009, /* ldr pc,[ip,r9] */
2464 0x00000000, /* .long @got */
2465 0xe59fc000, /* ldr ip,[pc] */
2466 0xe599f008, /* ldr pc,[r9,#8] */
2467 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2468};
00a97672 2469
b7693d02
DJ		 2470/* An initial stub used if the PLT entry is referenced from Thumb code. */
2471#define PLT_THUMB_STUB_SIZE 4
2472static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2473{
2474 0x4778, /* bx pc */
2475 0x46c0 /* nop */
2476};
b7693d02 2477
e5a52504
MM		 2478/* The entries in a PLT when using a DLL-based target with multiple
2479 address spaces. */
906e58ca 2480static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb 2481{
07d6d2b8
AM		 2482 0xe51ff004, /* ldr pc, [pc, #-4] */
2483 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
b38cadfb
NC		 2484};
2485
2486/* The first entry in a procedure linkage table looks like
2487 this. It is set up so that any shared library function that is
2488 called before the relocation has been set up calls the dynamic
2489 linker first. */
2490static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2491{
2492 /* First bundle: */
2493 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2494 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2495 0xe08cc00f, /* add ip, ip, pc */
2496 0xe52dc008, /* str ip, [sp, #-8]! */
2497 /* Second bundle: */
edccdf7c
RM		 2498 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2499 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2500 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2501 0xe12fff1c, /* bx ip */
b38cadfb 2502 /* Third bundle: */
edccdf7c
RM		 2503 0xe320f000, /* nop */
2504 0xe320f000, /* nop */
2505 0xe320f000, /* nop */
b38cadfb
NC		 2506 /* .Lplt_tail: */
2507 0xe50dc004, /* str ip, [sp, #-4] */
2508 /* Fourth bundle: */
edccdf7c
RM		 2509 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2510 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2511 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2512 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2513};
2514#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2515
2516/* Subsequent entries in a procedure linkage table look like this. */
2517static const bfd_vma elf32_arm_nacl_plt_entry [] =
2518{
2519 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2520 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2521 0xe08cc00f, /* add ip, ip, pc */
2522 0xea000000, /* b .Lplt_tail */
2523};
e5a52504 2524
906e58ca
NC		 2525#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2526#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2527#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2528#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2529#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2530#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2531#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2532#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2533
461a49ca 2534enum stub_insn_type
b38cadfb
NC		 2535{
2536 THUMB16_TYPE = 1,
2537 THUMB32_TYPE,
2538 ARM_TYPE,
2539 DATA_TYPE
2540};
461a49ca 2541
48229727
JB		 2542#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2543/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2544 is inserted in arm_build_one_stub(). */
2545#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2546#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2547#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2548#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2549#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2550#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2551#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2552#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2553
2554typedef struct
2555{
07d6d2b8 2556 bfd_vma data;
b38cadfb 2557 enum stub_insn_type type;
07d6d2b8
AM		 2558 unsigned int r_type;
2559 int reloc_addend;
461a49ca
DJ		 2560} insn_sequence;
2561
fea2b4d6
CL		 2562/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2563 to reach the stub if necessary. */
461a49ca 2564static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb 2565{
07d6d2b8 2566 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2567 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2568};
906e58ca 2569
fea2b4d6
CL		 2570/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2571 available. */
461a49ca 2572static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb 2573{
07d6d2b8
AM		 2574 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2575 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2576 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2577};
906e58ca 2578
d3626fb0 2579/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2580static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb 2581{
07d6d2b8
AM		 2582 THUMB16_INSN (0xb401), /* push {r0} */
2583 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2584 THUMB16_INSN (0x4684), /* mov ip, r0 */
2585 THUMB16_INSN (0xbc01), /* pop {r0} */
2586 THUMB16_INSN (0x4760), /* bx ip */
2587 THUMB16_INSN (0xbf00), /* nop */
b38cadfb
NC		 2588 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2589};
906e58ca 2590
80c135e5
TP		 2591/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2592static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2593{
07d6d2b8 2594 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
80c135e5
TP		 2595 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2596};
2597
d5a67c02
AV		 2598/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2599 M-profile architectures. */
2600static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2601{
2602 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2603 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
07d6d2b8 2604 THUMB16_INSN (0x4760), /* bx ip */
d5a67c02
AV		 2605};
2606
d3626fb0
CL		 2607/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2608 allowed. */
2609static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb 2610{
07d6d2b8
AM		 2611 THUMB16_INSN (0x4778), /* bx pc */
2612 THUMB16_INSN (0x46c0), /* nop */
2613 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2614 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2615 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2616};
d3626fb0 2617
fea2b4d6
CL		 2618/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2619 available. */
461a49ca 2620static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb 2621{
07d6d2b8
AM		 2622 THUMB16_INSN (0x4778), /* bx pc */
2623 THUMB16_INSN (0x46c0), /* nop */
2624 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2625 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2626};
906e58ca 2627
fea2b4d6
CL		 2628/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2629 one, when the destination is close enough. */
461a49ca 2630static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb 2631{
07d6d2b8
AM		 2632 THUMB16_INSN (0x4778), /* bx pc */
2633 THUMB16_INSN (0x46c0), /* nop */
b38cadfb
NC		 2634 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2635};
c820be07 2636
cf3eccff 2637/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2638 blx to reach the stub if necessary. */
cf3eccff 2639static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb 2640{
07d6d2b8
AM		 2641 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2642 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
b38cadfb
NC		 2643 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2644};
906e58ca 2645
cf3eccff
DJ		 2646/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2647 blx to reach the stub if necessary. We can not add into pc;
2648 it is not guaranteed to mode switch (different in ARMv6 and
2649 ARMv7). */
2650static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb 2651{
07d6d2b8
AM		 2652 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2653 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2654 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2655 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2656};
cf3eccff 2657
ebe24dd4
CL		 2658/* V4T ARM -> ARM long branch stub, PIC. */
2659static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb 2660{
07d6d2b8
AM		 2661 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2662 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2663 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2664 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2665};
ebe24dd4
CL		 2666
2667/* V4T Thumb -> ARM long branch stub, PIC. */
2668static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb 2669{
07d6d2b8
AM		 2670 THUMB16_INSN (0x4778), /* bx pc */
2671 THUMB16_INSN (0x46c0), /* nop */
2672 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2673 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
b38cadfb
NC		 2674 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2675};
ebe24dd4 2676
d3626fb0
CL		 2677/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2678 architectures. */
ebe24dd4 2679static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb 2680{
07d6d2b8
AM		 2681 THUMB16_INSN (0xb401), /* push {r0} */
2682 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2683 THUMB16_INSN (0x46fc), /* mov ip, pc */
2684 THUMB16_INSN (0x4484), /* add ip, r0 */
2685 THUMB16_INSN (0xbc01), /* pop {r0} */
2686 THUMB16_INSN (0x4760), /* bx ip */
b38cadfb
NC		 2687 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2688};
ebe24dd4 2689
d3626fb0
CL		 2690/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2691 allowed. */
2692static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb 2693{
07d6d2b8
AM		 2694 THUMB16_INSN (0x4778), /* bx pc */
2695 THUMB16_INSN (0x46c0), /* nop */
2696 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2697 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2698 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2699 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2700};
d3626fb0 2701
0855e32b
NS		 2702/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2703 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2704static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2705{
07d6d2b8
AM		 2706 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2707 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
b38cadfb 2708 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2709};
2710
2711/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2712 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2713static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2714{
07d6d2b8
AM		 2715 THUMB16_INSN (0x4778), /* bx pc */
2716 THUMB16_INSN (0x46c0), /* nop */
2717 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2718 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
b38cadfb 2719 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2720};
2721
7a89b94e
NC		 2722/* NaCl ARM -> ARM long branch stub. */
2723static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2724{
2725 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2726 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2727 ARM_INSN (0xe12fff1c), /* bx ip */
2728 ARM_INSN (0xe320f000), /* nop */
2729 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2730 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2731 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2732 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2733};
2734
2735/* NaCl ARM -> ARM long branch stub, PIC. */
2736static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2737{
2738 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
07d6d2b8 2739 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
7a89b94e 2740 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2741 ARM_INSN (0xe12fff1c), /* bx ip */
2742 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2743 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2744 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2745 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2746};
2747
4ba2ef8f
TP		 2748/* Stub used for transition to secure state (aka SG veneer). */
2749static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2750{
2751 THUMB32_INSN (0xe97fe97f), /* sg. */
2752 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2753};
2754
7a89b94e 2755
48229727
JB		 2756/* Cortex-A8 erratum-workaround stubs. */
2757
2758/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2759 can't use a conditional branch to reach this stub). */
2760
2761static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb 2762{
07d6d2b8 2763 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
b38cadfb
NC		 2764 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2765 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2766};
48229727
JB		 2767
2768/* Stub used for b.w and bl.w instructions. */
2769
2770static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2771{
2772 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2773};
48229727
JB		 2774
2775static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2776{
2777 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2778};
48229727
JB		 2779
2780/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2781 instruction (which switches to ARM mode) to point to this stub. Jump to the
2782 real destination using an ARM-mode branch. */
2783
2784static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2785{
2786 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2787};
48229727 2788
9553db3c
NC		 2789/* For each section group there can be a specially created linker section
2790 to hold the stubs for that group. The name of the stub section is based
2791 upon the name of another section within that group with the suffix below
2792 applied.
2793
2794 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2795 create what appeared to be a linker stub section when it actually
2796 contained user code/data. For example, consider this fragment:
b38cadfb 2797
9553db3c
NC		 2798 const char * stubborn_problems[] = { "np" };
2799
2800 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2801 section called:
2802
2803 .data.rel.local.stubborn_problems
2804
2805 This then causes problems in arm32_arm_build_stubs() as it triggers:
2806
2807 // Ignore non-stub sections.
2808 if (!strstr (stub_sec->name, STUB_SUFFIX))
2809 continue;
2810
2811 And so the section would be ignored instead of being processed. Hence
2812 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2813 C identifier. */
2814#define STUB_SUFFIX ".__stub"
906e58ca 2815
738a79f6
CL		 2816/* One entry per long/short branch stub defined above. */
2817#define DEF_STUBS \
2818 DEF_STUB(long_branch_any_any) \
2819 DEF_STUB(long_branch_v4t_arm_thumb) \
2820 DEF_STUB(long_branch_thumb_only) \
2821 DEF_STUB(long_branch_v4t_thumb_thumb) \
2822 DEF_STUB(long_branch_v4t_thumb_arm) \
2823 DEF_STUB(short_branch_v4t_thumb_arm) \
2824 DEF_STUB(long_branch_any_arm_pic) \
2825 DEF_STUB(long_branch_any_thumb_pic) \
2826 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2827 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2828 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2829 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2830 DEF_STUB(long_branch_any_tls_pic) \
2831 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2832 DEF_STUB(long_branch_arm_nacl) \
2833 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2834 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2835 DEF_STUB(a8_veneer_b_cond) \
2836 DEF_STUB(a8_veneer_b) \
2837 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2838 DEF_STUB(a8_veneer_blx) \
2839 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2840 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2841
2842#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2843enum elf32_arm_stub_type
2844{
906e58ca 2845 arm_stub_none,
738a79f6 2846 DEF_STUBS
4f4faa4d 2847 max_stub_type
738a79f6
CL		 2848};
2849#undef DEF_STUB
2850
8d9d9490
TP		 2851/* Note the first a8_veneer type. */
2852const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2853
738a79f6
CL		 2854typedef struct
2855{
d3ce72d0 2856 const insn_sequence* template_sequence;
738a79f6
CL		 2857 int template_size;
2858} stub_def;
2859
2860#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2861static const stub_def stub_definitions[] =
2862{
738a79f6
CL		 2863 {NULL, 0},
2864 DEF_STUBS
906e58ca
NC		 2865};
2866
2867struct elf32_arm_stub_hash_entry
2868{
2869 /* Base hash table entry structure. */
2870 struct bfd_hash_entry root;
2871
2872 /* The stub section. */
2873 asection *stub_sec;
2874
2875 /* Offset within stub_sec of the beginning of this stub. */
2876 bfd_vma stub_offset;
2877
2878 /* Given the symbol's value and its section we can determine its final
2879 value when building the stubs (so the stub knows where to jump). */
2880 bfd_vma target_value;
2881 asection *target_section;
2882
8d9d9490
TP		 2883 /* Same as above but for the source of the branch to the stub. Used for
2884 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2885 such, source section does not need to be recorded since Cortex-A8 erratum
2886 workaround stubs are only generated when both source and target are in the
2887 same section. */
2888 bfd_vma source_value;
48229727
JB		 2889
2890 /* The instruction which caused this stub to be generated (only valid for
2891 Cortex-A8 erratum workaround stubs at present). */
2892 unsigned long orig_insn;
2893
461a49ca 2894 /* The stub type. */
906e58ca 2895 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2896 /* Its encoding size in bytes. */
2897 int stub_size;
2898 /* Its template. */
2899 const insn_sequence *stub_template;
2900 /* The size of the template (number of entries). */
2901 int stub_template_size;
906e58ca
NC		 2902
2903 /* The symbol table entry, if any, that this was derived from. */
2904 struct elf32_arm_link_hash_entry *h;
2905
35fc36a8
RS		 2906 /* Type of branch. */
2907 enum arm_st_branch_type branch_type;
906e58ca
NC		 2908
2909 /* Where this stub is being called from, or, in the case of combined
2910 stub sections, the first input section in the group. */
2911 asection *id_sec;
7413f23f
DJ		 2912
2913 /* The name for the local symbol at the start of this stub. The
2914 stub name in the hash table has to be unique; this does not, so
2915 it can be friendlier. */
2916 char *output_name;
906e58ca
NC		 2917};
2918
e489d0ae
PB		 2919/* Used to build a map of a section. This is required for mixed-endian
2920 code/data. */
2921
2922typedef struct elf32_elf_section_map
2923{
2924 bfd_vma vma;
2925 char type;
2926}
2927elf32_arm_section_map;
2928
c7b8f16e
JB		 2929/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2930
2931typedef enum
2932{
2933 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2934 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2935 VFP11_ERRATUM_ARM_VENEER,
2936 VFP11_ERRATUM_THUMB_VENEER
2937}
2938elf32_vfp11_erratum_type;
2939
2940typedef struct elf32_vfp11_erratum_list
2941{
2942 struct elf32_vfp11_erratum_list *next;
2943 bfd_vma vma;
2944 union
2945 {
2946 struct
2947 {
2948 struct elf32_vfp11_erratum_list *veneer;
2949 unsigned int vfp_insn;
2950 } b;
2951 struct
2952 {
2953 struct elf32_vfp11_erratum_list *branch;
2954 unsigned int id;
2955 } v;
2956 } u;
2957 elf32_vfp11_erratum_type type;
2958}
2959elf32_vfp11_erratum_list;
2960
a504d23a
LA		 2961/* Information about a STM32L4XX erratum veneer, or a branch to such a
2962 veneer. */
2963typedef enum
2964{
2965 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2966 STM32L4XX_ERRATUM_VENEER
2967}
2968elf32_stm32l4xx_erratum_type;
2969
2970typedef struct elf32_stm32l4xx_erratum_list
2971{
2972 struct elf32_stm32l4xx_erratum_list *next;
2973 bfd_vma vma;
2974 union
2975 {
2976 struct
2977 {
2978 struct elf32_stm32l4xx_erratum_list *veneer;
2979 unsigned int insn;
2980 } b;
2981 struct
2982 {
2983 struct elf32_stm32l4xx_erratum_list *branch;
2984 unsigned int id;
2985 } v;
2986 } u;
2987 elf32_stm32l4xx_erratum_type type;
2988}
2989elf32_stm32l4xx_erratum_list;
2990
2468f9c9
PB		 2991typedef enum
2992{
2993 DELETE_EXIDX_ENTRY,
2994 INSERT_EXIDX_CANTUNWIND_AT_END
2995}
2996arm_unwind_edit_type;
2997
2998/* A (sorted) list of edits to apply to an unwind table. */
2999typedef struct arm_unwind_table_edit
3000{
3001 arm_unwind_edit_type type;
3002 /* Note: we sometimes want to insert an unwind entry corresponding to a
3003 section different from the one we're currently writing out, so record the
3004 (text) section this edit relates to here. */
3005 asection *linked_section;
3006 unsigned int index;
3007 struct arm_unwind_table_edit *next;
3008}
3009arm_unwind_table_edit;
3010
8e3de13a 3011typedef struct _arm_elf_section_data
e489d0ae 3012{
2468f9c9 3013 /* Information about mapping symbols. */
e489d0ae 3014 struct bfd_elf_section_data elf;
8e3de13a 3015 unsigned int mapcount;
c7b8f16e 3016 unsigned int mapsize;
e489d0ae 3017 elf32_arm_section_map *map;
2468f9c9 3018 /* Information about CPU errata. */
c7b8f16e
JB		 3019 unsigned int erratumcount;
3020 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 3021 unsigned int stm32l4xx_erratumcount;
3022 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 3023 unsigned int additional_reloc_count;
2468f9c9
PB		 3024 /* Information about unwind tables. */
3025 union
3026 {
3027 /* Unwind info attached to a text section. */
3028 struct
3029 {
3030 asection *arm_exidx_sec;
3031 } text;
3032
3033 /* Unwind info attached to an .ARM.exidx section. */
3034 struct
3035 {
3036 arm_unwind_table_edit *unwind_edit_list;
3037 arm_unwind_table_edit *unwind_edit_tail;
3038 } exidx;
3039 } u;
8e3de13a
NC		 3040}
3041_arm_elf_section_data;
e489d0ae
PB		 3042
3043#define elf32_arm_section_data(sec) \
8e3de13a 3044 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 3045
48229727
JB		 3046/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3047 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3048 so may be created multiple times: we use an array of these entries whilst
3049 relaxing which we can refresh easily, then create stubs for each potentially
3050 erratum-triggering instruction once we've settled on a solution. */
3051
b38cadfb
NC		 3052struct a8_erratum_fix
3053{
48229727
JB		 3054 bfd *input_bfd;
3055 asection *section;
3056 bfd_vma offset;
8d9d9490 3057 bfd_vma target_offset;
48229727
JB		 3058 unsigned long orig_insn;
3059 char *stub_name;
3060 enum elf32_arm_stub_type stub_type;
35fc36a8 3061 enum arm_st_branch_type branch_type;
48229727
JB		 3062};
3063
3064/* A table of relocs applied to branches which might trigger Cortex-A8
3065 erratum. */
3066
b38cadfb
NC		 3067struct a8_erratum_reloc
3068{
48229727
JB		 3069 bfd_vma from;
3070 bfd_vma destination;
92750f34
DJ		 3071 struct elf32_arm_link_hash_entry *hash;
3072 const char *sym_name;
48229727 3073 unsigned int r_type;
35fc36a8 3074 enum arm_st_branch_type branch_type;
48229727
JB		 3075 bfd_boolean non_a8_stub;
3076};
3077
ba93b8ac
DJ		 3078/* The size of the thread control block. */
3079#define TCB_SIZE 8
3080
34e77a92
RS		 3081/* ARM-specific information about a PLT entry, over and above the usual
3082 gotplt_union. */
b38cadfb
NC		 3083struct arm_plt_info
3084{
34e77a92
RS		 3085 /* We reference count Thumb references to a PLT entry separately,
3086 so that we can emit the Thumb trampoline only if needed. */
3087 bfd_signed_vma thumb_refcount;
3088
3089 /* Some references from Thumb code may be eliminated by BL->BLX
3090 conversion, so record them separately. */
3091 bfd_signed_vma maybe_thumb_refcount;
3092
3093 /* How many of the recorded PLT accesses were from non-call relocations.
3094 This information is useful when deciding whether anything takes the
3095 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3096 non-call references to the function should resolve directly to the
3097 real runtime target. */
3098 unsigned int noncall_refcount;
3099
3100 /* Since PLT entries have variable size if the Thumb prologue is
3101 used, we need to record the index into .got.plt instead of
3102 recomputing it from the PLT offset. */
3103 bfd_signed_vma got_offset;
3104};
3105
3106/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 3107struct arm_local_iplt_info
3108{
34e77a92
RS		 3109 /* The information that is usually found in the generic ELF part of
3110 the hash table entry. */
3111 union gotplt_union root;
3112
3113 /* The information that is usually found in the ARM-specific part of
3114 the hash table entry. */
3115 struct arm_plt_info arm;
3116
3117 /* A list of all potential dynamic relocations against this symbol. */
3118 struct elf_dyn_relocs *dyn_relocs;
3119};
3120
e8b09b87
CL		 3121/* Structure to handle FDPIC support for local functions. */
3122struct fdpic_local {
3123 unsigned int funcdesc_cnt;
3124 unsigned int gotofffuncdesc_cnt;
3125 int funcdesc_offset;
3126};
3127
0ffa91dd 3128struct elf_arm_obj_tdata
ba93b8ac
DJ		 3129{
3130 struct elf_obj_tdata root;
3131
3132 /* tls_type for each local got entry. */
3133 char *local_got_tls_type;
ee065d83 3134
0855e32b
NS		 3135 /* GOTPLT entries for TLS descriptors. */
3136 bfd_vma *local_tlsdesc_gotent;
3137
34e77a92
RS		 3138 /* Information for local symbols that need entries in .iplt. */
3139 struct arm_local_iplt_info **local_iplt;
3140
bf21ed78
MS		 3141 /* Zero to warn when linking objects with incompatible enum sizes. */
3142 int no_enum_size_warning;
a9dc9481
JM		 3143
3144 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3145 int no_wchar_size_warning;
e8b09b87
CL		 3146
3147 /* Maintains FDPIC counters and funcdesc info. */
3148 struct fdpic_local *local_fdpic_cnts;
ba93b8ac
DJ		 3149};
3150
0ffa91dd
NC		 3151#define elf_arm_tdata(bfd) \
3152 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 3153
0ffa91dd
NC		 3154#define elf32_arm_local_got_tls_type(bfd) \
3155 (elf_arm_tdata (bfd)->local_got_tls_type)
3156
0855e32b
NS		 3157#define elf32_arm_local_tlsdesc_gotent(bfd) \
3158 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3159
34e77a92
RS		 3160#define elf32_arm_local_iplt(bfd) \
3161 (elf_arm_tdata (bfd)->local_iplt)
3162
e8b09b87
CL		 3163#define elf32_arm_local_fdpic_cnts(bfd) \
3164 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3165
0ffa91dd
NC		 3166#define is_arm_elf(bfd) \
3167 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3168 && elf_tdata (bfd) != NULL \
4dfe6ac6 3169 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 3170
3171static bfd_boolean
3172elf32_arm_mkobject (bfd *abfd)
3173{
0ffa91dd 3174 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 3175 ARM_ELF_DATA);
ba93b8ac
DJ		 3176}
3177
ba93b8ac
DJ		 3178#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3179
e8b09b87
CL		 3180/* Structure to handle FDPIC support for extern functions. */
3181struct fdpic_global {
3182 unsigned int gotofffuncdesc_cnt;
3183 unsigned int gotfuncdesc_cnt;
3184 unsigned int funcdesc_cnt;
3185 int funcdesc_offset;
3186 int gotfuncdesc_offset;
3187};
3188
ba96a88f 3189/* Arm ELF linker hash entry. */
252b5132 3190struct elf32_arm_link_hash_entry
b38cadfb
NC		 3191{
3192 struct elf_link_hash_entry root;
252b5132 3193
b38cadfb
NC		 3194 /* Track dynamic relocs copied for this symbol. */
3195 struct elf_dyn_relocs *dyn_relocs;
b7693d02 3196
b38cadfb
NC		 3197 /* ARM-specific PLT information. */
3198 struct arm_plt_info plt;
ba93b8ac
DJ		 3199
3200#define GOT_UNKNOWN 0
3201#define GOT_NORMAL 1
3202#define GOT_TLS_GD 2
3203#define GOT_TLS_IE 4
0855e32b
NS		 3204#define GOT_TLS_GDESC 8
3205#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3206 unsigned int tls_type : 8;
34e77a92 3207
b38cadfb
NC		 3208 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3209 unsigned int is_iplt : 1;
34e77a92 3210
b38cadfb 3211 unsigned int unused : 23;
a4fd1a8e 3212
b38cadfb
NC		 3213 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3214 starting at the end of the jump table. */
3215 bfd_vma tlsdesc_got;
0855e32b 3216
b38cadfb
NC		 3217 /* The symbol marking the real symbol location for exported thumb
3218 symbols with Arm stubs. */
3219 struct elf_link_hash_entry *export_glue;
906e58ca 3220
b38cadfb 3221 /* A pointer to the most recently used stub hash entry against this
8029a119 3222 symbol. */
b38cadfb 3223 struct elf32_arm_stub_hash_entry *stub_cache;
e8b09b87
CL		 3224
3225 /* Counter for FDPIC relocations against this symbol. */
3226 struct fdpic_global fdpic_cnts;
b38cadfb 3227};
252b5132 3228
252b5132 3229/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3230#define elf32_arm_link_hash_traverse(table, func, info) \
3231 (elf_link_hash_traverse \
3232 (&(table)->root, \
b7693d02 3233 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3234 (info)))
3235
3236/* Get the ARM elf linker hash table from a link_info structure. */
3237#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3238 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3239 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3240
906e58ca
NC		 3241#define arm_stub_hash_lookup(table, string, create, copy) \
3242 ((struct elf32_arm_stub_hash_entry *) \
3243 bfd_hash_lookup ((table), (string), (create), (copy)))
3244
21d799b5
NC		 3245/* Array to keep track of which stub sections have been created, and
3246 information on stub grouping. */
3247struct map_stub
3248{
3249 /* This is the section to which stubs in the group will be
3250 attached. */
3251 asection *link_sec;
3252 /* The stub section. */
3253 asection *stub_sec;
3254};
3255
0855e32b
NS		 3256#define elf32_arm_compute_jump_table_size(htab) \
3257 ((htab)->next_tls_desc_index * 4)
3258
9b485d32 3259/* ARM ELF linker hash table. */
252b5132 3260struct elf32_arm_link_hash_table
906e58ca
NC		 3261{
3262 /* The main hash table. */
3263 struct elf_link_hash_table root;
252b5132 3264
906e58ca
NC		 3265 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3266 bfd_size_type thumb_glue_size;
252b5132 3267
906e58ca
NC		 3268 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3269 bfd_size_type arm_glue_size;
252b5132 3270
906e58ca
NC		 3271 /* The size in bytes of section containing the ARMv4 BX veneers. */
3272 bfd_size_type bx_glue_size;
845b51d6 3273
906e58ca
NC		 3274 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3275 veneer has been populated. */
3276 bfd_vma bx_glue_offset[15];
845b51d6 3277
906e58ca
NC		 3278 /* The size in bytes of the section containing glue for VFP11 erratum
3279 veneers. */
3280 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3281
a504d23a
LA		 3282 /* The size in bytes of the section containing glue for STM32L4XX erratum
3283 veneers. */
3284 bfd_size_type stm32l4xx_erratum_glue_size;
3285
48229727
JB		 3286 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3287 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3288 elf32_arm_write_section(). */
3289 struct a8_erratum_fix *a8_erratum_fixes;
3290 unsigned int num_a8_erratum_fixes;
3291
906e58ca
NC		 3292 /* An arbitrary input BFD chosen to hold the glue sections. */
3293 bfd * bfd_of_glue_owner;
ba96a88f 3294
906e58ca
NC		 3295 /* Nonzero to output a BE8 image. */
3296 int byteswap_code;
e489d0ae 3297
906e58ca
NC		 3298 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3299 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3300 int target1_is_rel;
9c504268 3301
906e58ca
NC		 3302 /* The relocation to use for R_ARM_TARGET2 relocations. */
3303 int target2_reloc;
eb043451 3304
906e58ca
NC		 3305 /* 0 = Ignore R_ARM_V4BX.
3306 1 = Convert BX to MOV PC.
3307 2 = Generate v4 interworing stubs. */
3308 int fix_v4bx;
319850b4 3309
48229727
JB		 3310 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3311 int fix_cortex_a8;
3312
2de70689
MGD		 3313 /* Whether we should fix the ARM1176 BLX immediate issue. */
3314 int fix_arm1176;
3315
906e58ca
NC		 3316 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3317 int use_blx;
33bfe774 3318
906e58ca
NC		 3319 /* What sort of code sequences we should look for which may trigger the
3320 VFP11 denorm erratum. */
3321 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3322
906e58ca
NC		 3323 /* Global counter for the number of fixes we have emitted. */
3324 int num_vfp11_fixes;
c7b8f16e 3325
a504d23a
LA		 3326 /* What sort of code sequences we should look for which may trigger the
3327 STM32L4XX erratum. */
3328 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3329
3330 /* Global counter for the number of fixes we have emitted. */
3331 int num_stm32l4xx_fixes;
3332
906e58ca
NC		 3333 /* Nonzero to force PIC branch veneers. */
3334 int pic_veneer;
27e55c4d 3335
906e58ca
NC		 3336 /* The number of bytes in the initial entry in the PLT. */
3337 bfd_size_type plt_header_size;
e5a52504 3338
906e58ca
NC		 3339 /* The number of bytes in the subsequent PLT etries. */
3340 bfd_size_type plt_entry_size;
e5a52504 3341
906e58ca
NC		 3342 /* True if the target system is VxWorks. */
3343 int vxworks_p;
00a97672 3344
906e58ca
NC		 3345 /* True if the target system is Symbian OS. */
3346 int symbian_p;
e5a52504 3347
b38cadfb
NC		 3348 /* True if the target system is Native Client. */
3349 int nacl_p;
3350
906e58ca 3351 /* True if the target uses REL relocations. */
f3185997 3352 bfd_boolean use_rel;
4e7fd91e 3353
54ddd295
TP		 3354 /* Nonzero if import library must be a secure gateway import library
3355 as per ARMv8-M Security Extensions. */
3356 int cmse_implib;
3357
0955507f
TP		 3358 /* The import library whose symbols' address must remain stable in
3359 the import library generated. */
3360 bfd *in_implib_bfd;
3361
0855e32b
NS		 3362 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3363 bfd_vma next_tls_desc_index;
3364
3365 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3366 bfd_vma num_tls_desc;
3367
906e58ca
NC		 3368 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3369 asection *srelplt2;
00a97672 3370
0855e32b
NS		 3371 /* The offset into splt of the PLT entry for the TLS descriptor
3372 resolver. Special values are 0, if not necessary (or not found
3373 to be necessary yet), and -1 if needed but not determined
3374 yet. */
3375 bfd_vma dt_tlsdesc_plt;
3376
3377 /* The offset into sgot of the GOT entry used by the PLT entry
3378 above. */
b38cadfb 3379 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3380
3381 /* Offset in .plt section of tls_arm_trampoline. */
3382 bfd_vma tls_trampoline;
3383
5c5a4843 3384 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
906e58ca
NC		 3385 union
3386 {
3387 bfd_signed_vma refcount;
3388 bfd_vma offset;
3389 } tls_ldm_got;
b7693d02 3390
87d72d41
AM		 3391 /* Small local sym cache. */
3392 struct sym_cache sym_cache;
906e58ca
NC		 3393
3394 /* For convenience in allocate_dynrelocs. */
3395 bfd * obfd;
3396
0855e32b
NS		 3397 /* The amount of space used by the reserved portion of the sgotplt
3398 section, plus whatever space is used by the jump slots. */
3399 bfd_vma sgotplt_jump_table_size;
3400
906e58ca
NC		 3401 /* The stub hash table. */
3402 struct bfd_hash_table stub_hash_table;
3403
3404 /* Linker stub bfd. */
3405 bfd *stub_bfd;
3406
3407 /* Linker call-backs. */
6bde4c52
TP		 3408 asection * (*add_stub_section) (const char *, asection *, asection *,
3409 unsigned int);
906e58ca
NC		 3410 void (*layout_sections_again) (void);
3411
3412 /* Array to keep track of which stub sections have been created, and
3413 information on stub grouping. */
21d799b5 3414 struct map_stub *stub_group;
906e58ca 3415
4ba2ef8f
TP		 3416 /* Input stub section holding secure gateway veneers. */
3417 asection *cmse_stub_sec;
3418
0955507f
TP		 3419 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3420 start to be allocated. */
3421 bfd_vma new_cmse_stub_offset;
3422
fe33d2fa 3423 /* Number of elements in stub_group. */
7292b3ac 3424 unsigned int top_id;
fe33d2fa 3425
906e58ca
NC		 3426 /* Assorted information used by elf32_arm_size_stubs. */
3427 unsigned int bfd_count;
7292b3ac 3428 unsigned int top_index;
906e58ca 3429 asection **input_list;
617a5ada
CL		 3430
3431 /* True if the target system uses FDPIC. */
3432 int fdpic_p;
e8b09b87
CL		 3433
3434 /* Fixup section. Used for FDPIC. */
3435 asection *srofixup;
906e58ca 3436};
252b5132 3437
e8b09b87
CL		 3438/* Add an FDPIC read-only fixup. */
3439static void
3440arm_elf_add_rofixup (bfd *output_bfd, asection *srofixup, bfd_vma offset)
3441{
3442 bfd_vma fixup_offset;
3443
3444 fixup_offset = srofixup->reloc_count++ * 4;
3445 BFD_ASSERT (fixup_offset < srofixup->size);
3446 bfd_put_32 (output_bfd, offset, srofixup->contents + fixup_offset);
3447}
3448
a504d23a
LA		 3449static inline int
3450ctz (unsigned int mask)
3451{
3452#if GCC_VERSION >= 3004
3453 return __builtin_ctz (mask);
3454#else
3455 unsigned int i;
3456
3457 for (i = 0; i < 8 * sizeof (mask); i++)
3458 {
3459 if (mask & 0x1)
3460 break;
3461 mask = (mask >> 1);
3462 }
3463 return i;
3464#endif
3465}
3466
3467static inline int
b25e998d 3468elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3469{
3470#if GCC_VERSION >= 3004
3471 return __builtin_popcount (mask);
3472#else
b25e998d
CG		 3473 unsigned int i;
3474 int sum = 0;
a504d23a
LA		 3475
3476 for (i = 0; i < 8 * sizeof (mask); i++)
3477 {
3478 if (mask & 0x1)
3479 sum++;
3480 mask = (mask >> 1);
3481 }
3482 return sum;
3483#endif
3484}
3485
e8b09b87
CL		 3486static void elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
3487 asection *sreloc, Elf_Internal_Rela *rel);
3488
3489static void
3490arm_elf_fill_funcdesc(bfd *output_bfd,
3491 struct bfd_link_info *info,
3492 int *funcdesc_offset,
3493 int dynindx,
3494 int offset,
3495 bfd_vma addr,
3496 bfd_vma dynreloc_value,
3497 bfd_vma seg)
3498{
3499 if ((*funcdesc_offset & 1) == 0)
3500 {
3501 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
3502 asection *sgot = globals->root.sgot;
3503
3504 if (bfd_link_pic(info))
3505 {
3506 asection *srelgot = globals->root.srelgot;
3507 Elf_Internal_Rela outrel;
3508
3509 outrel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
3510 outrel.r_offset = sgot->output_section->vma + sgot->output_offset + offset;
3511 outrel.r_addend = 0;
3512
3513 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
3514 bfd_put_32 (output_bfd, addr, sgot->contents + offset);
3515 bfd_put_32 (output_bfd, seg, sgot->contents + offset + 4);
3516 }
3517 else
3518 {
3519 struct elf_link_hash_entry *hgot = globals->root.hgot;
3520 bfd_vma got_value = hgot->root.u.def.value
3521 + hgot->root.u.def.section->output_section->vma
3522 + hgot->root.u.def.section->output_offset;
3523
3524 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3525 sgot->output_section->vma + sgot->output_offset
3526 + offset);
3527 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3528 sgot->output_section->vma + sgot->output_offset
3529 + offset + 4);
3530 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + offset);
3531 bfd_put_32 (output_bfd, got_value, sgot->contents + offset + 4);
3532 }
3533 *funcdesc_offset |= 1;
3534 }
3535}
3536
780a67af
NC		 3537/* Create an entry in an ARM ELF linker hash table. */
3538
3539static struct bfd_hash_entry *
57e8b36a 3540elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3541 struct bfd_hash_table * table,
3542 const char * string)
780a67af
NC		 3543{
3544 struct elf32_arm_link_hash_entry * ret =
3545 (struct elf32_arm_link_hash_entry *) entry;
3546
3547 /* Allocate the structure if it has not already been allocated by a
3548 subclass. */
906e58ca 3549 if (ret == NULL)
21d799b5 3550 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3551 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3552 if (ret == NULL)
780a67af
NC		 3553 return (struct bfd_hash_entry *) ret;
3554
3555 /* Call the allocation method of the superclass. */
3556 ret = ((struct elf32_arm_link_hash_entry *)
3557 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3558 table, string));
57e8b36a 3559 if (ret != NULL)
b7693d02 3560 {
0bdcacaf 3561 ret->dyn_relocs = NULL;
ba93b8ac 3562 ret->tls_type = GOT_UNKNOWN;
0855e32b 3563 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3564 ret->plt.thumb_refcount = 0;
3565 ret->plt.maybe_thumb_refcount = 0;
3566 ret->plt.noncall_refcount = 0;
3567 ret->plt.got_offset = -1;
3568 ret->is_iplt = FALSE;
a4fd1a8e 3569 ret->export_glue = NULL;
906e58ca
NC		 3570
3571 ret->stub_cache = NULL;
e8b09b87
CL		 3572
3573 ret->fdpic_cnts.gotofffuncdesc_cnt = 0;
3574 ret->fdpic_cnts.gotfuncdesc_cnt = 0;
3575 ret->fdpic_cnts.funcdesc_cnt = 0;
3576 ret->fdpic_cnts.funcdesc_offset = -1;
3577 ret->fdpic_cnts.gotfuncdesc_offset = -1;
b7693d02 3578 }
780a67af
NC		 3579
3580 return (struct bfd_hash_entry *) ret;
3581}
3582
34e77a92
RS		 3583/* Ensure that we have allocated bookkeeping structures for ABFD's local
3584 symbols. */
3585
3586static bfd_boolean
3587elf32_arm_allocate_local_sym_info (bfd *abfd)
3588{
3589 if (elf_local_got_refcounts (abfd) == NULL)
3590 {
3591 bfd_size_type num_syms;
3592 bfd_size_type size;
3593 char *data;
3594
3595 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3596 size = num_syms * (sizeof (bfd_signed_vma)
3597 + sizeof (struct arm_local_iplt_info *)
3598 + sizeof (bfd_vma)
e8b09b87
CL		 3599 + sizeof (char)
3600 + sizeof (struct fdpic_local));
34e77a92
RS		 3601 data = bfd_zalloc (abfd, size);
3602 if (data == NULL)
3603 return FALSE;
3604
e8b09b87
CL		 3605 elf32_arm_local_fdpic_cnts (abfd) = (struct fdpic_local *) data;
3606 data += num_syms * sizeof (struct fdpic_local);
3607
34e77a92
RS		 3608 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3609 data += num_syms * sizeof (bfd_signed_vma);
3610
3611 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3612 data += num_syms * sizeof (struct arm_local_iplt_info *);
3613
3614 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3615 data += num_syms * sizeof (bfd_vma);
3616
3617 elf32_arm_local_got_tls_type (abfd) = data;
3618 }
3619 return TRUE;
3620}
3621
3622/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3623 to input bfd ABFD. Create the information if it doesn't already exist.
3624 Return null if an allocation fails. */
3625
3626static struct arm_local_iplt_info *
3627elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3628{
3629 struct arm_local_iplt_info **ptr;
3630
3631 if (!elf32_arm_allocate_local_sym_info (abfd))
3632 return NULL;
3633
3634 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3635 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3636 if (*ptr == NULL)
3637 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3638 return *ptr;
3639}
3640
3641/* Try to obtain PLT information for the symbol with index R_SYMNDX
3642 in ABFD's symbol table. If the symbol is global, H points to its
3643 hash table entry, otherwise H is null.
3644
3645 Return true if the symbol does have PLT information. When returning
3646 true, point *ROOT_PLT at the target-independent reference count/offset
3647 union and *ARM_PLT at the ARM-specific information. */
3648
3649static bfd_boolean
4ba2ef8f
TP		 3650elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3651 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3652 unsigned long r_symndx, union gotplt_union **root_plt,
3653 struct arm_plt_info **arm_plt)
3654{
3655 struct arm_local_iplt_info *local_iplt;
3656
4ba2ef8f
TP		 3657 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3658 return FALSE;
3659
34e77a92
RS		 3660 if (h != NULL)
3661 {
3662 *root_plt = &h->root.plt;
3663 *arm_plt = &h->plt;
3664 return TRUE;
3665 }
3666
3667 if (elf32_arm_local_iplt (abfd) == NULL)
3668 return FALSE;
3669
3670 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3671 if (local_iplt == NULL)
3672 return FALSE;
3673
3674 *root_plt = &local_iplt->root;
3675 *arm_plt = &local_iplt->arm;
3676 return TRUE;
3677}
3678
59029f57
CL		 3679static bfd_boolean using_thumb_only (struct elf32_arm_link_hash_table *globals);
3680
34e77a92
RS		 3681/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3682 before it. */
3683
3684static bfd_boolean
3685elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3686 struct arm_plt_info *arm_plt)
3687{
3688 struct elf32_arm_link_hash_table *htab;
3689
3690 htab = elf32_arm_hash_table (info);
59029f57
CL		 3691
3692 return (!using_thumb_only(htab) && (arm_plt->thumb_refcount != 0
3693 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0)));
34e77a92
RS		 3694}
3695
3696/* Return a pointer to the head of the dynamic reloc list that should
3697 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3698 ABFD's symbol table. Return null if an error occurs. */
3699
3700static struct elf_dyn_relocs **
3701elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3702 Elf_Internal_Sym *isym)
3703{
3704 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3705 {
3706 struct arm_local_iplt_info *local_iplt;
3707
3708 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3709 if (local_iplt == NULL)
3710 return NULL;
3711 return &local_iplt->dyn_relocs;
3712 }
3713 else
3714 {
3715 /* Track dynamic relocs needed for local syms too.
3716 We really need local syms available to do this
3717 easily. Oh well. */
3718 asection *s;
3719 void *vpp;
3720
3721 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3722 if (s == NULL)
3723 abort ();
3724
3725 vpp = &elf_section_data (s)->local_dynrel;
3726 return (struct elf_dyn_relocs **) vpp;
3727 }
3728}
3729
906e58ca
NC		 3730/* Initialize an entry in the stub hash table. */
3731
3732static struct bfd_hash_entry *
3733stub_hash_newfunc (struct bfd_hash_entry *entry,
3734 struct bfd_hash_table *table,
3735 const char *string)
3736{
3737 /* Allocate the structure if it has not already been allocated by a
3738 subclass. */
3739 if (entry == NULL)
3740 {
21d799b5 3741 entry = (struct bfd_hash_entry *)
99059e56 3742 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3743 if (entry == NULL)
3744 return entry;
3745 }
3746
3747 /* Call the allocation method of the superclass. */
3748 entry = bfd_hash_newfunc (entry, table, string);
3749 if (entry != NULL)
3750 {
3751 struct elf32_arm_stub_hash_entry *eh;
3752
3753 /* Initialize the local fields. */
3754 eh = (struct elf32_arm_stub_hash_entry *) entry;
3755 eh->stub_sec = NULL;
0955507f 3756 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3757 eh->source_value = 0;
906e58ca
NC		 3758 eh->target_value = 0;
3759 eh->target_section = NULL;
cedfb179 3760 eh->orig_insn = 0;
906e58ca 3761 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3762 eh->stub_size = 0;
3763 eh->stub_template = NULL;
0955507f 3764 eh->stub_template_size = -1;
906e58ca
NC		 3765 eh->h = NULL;
3766 eh->id_sec = NULL;
d8d2f433 3767 eh->output_name = NULL;
906e58ca
NC		 3768 }
3769
3770 return entry;
3771}
3772
00a97672 3773/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3774 shortcuts to them in our hash table. */
3775
3776static bfd_boolean
57e8b36a 3777create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3778{
3779 struct elf32_arm_link_hash_table *htab;
3780
e5a52504 3781 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3782 if (htab == NULL)
3783 return FALSE;
3784
e5a52504
MM		 3785 /* BPABI objects never have a GOT, or associated sections. */
3786 if (htab->symbian_p)
3787 return TRUE;
3788
5e681ec4
PB		 3789 if (! _bfd_elf_create_got_section (dynobj, info))
3790 return FALSE;
3791
e8b09b87
CL		 3792 /* Also create .rofixup. */
3793 if (htab->fdpic_p)
3794 {
3795 htab->srofixup = bfd_make_section_with_flags (dynobj, ".rofixup",
3796 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS
3797 | SEC_IN_MEMORY | SEC_LINKER_CREATED | SEC_READONLY));
3798 if (htab->srofixup == NULL || ! bfd_set_section_alignment (dynobj, htab->srofixup, 2))
3799 return FALSE;
3800 }
3801
5e681ec4
PB		 3802 return TRUE;
3803}
3804
34e77a92
RS		 3805/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3806
3807static bfd_boolean
3808create_ifunc_sections (struct bfd_link_info *info)
3809{
3810 struct elf32_arm_link_hash_table *htab;
3811 const struct elf_backend_data *bed;
3812 bfd *dynobj;
3813 asection *s;
3814 flagword flags;
b38cadfb 3815
34e77a92
RS		 3816 htab = elf32_arm_hash_table (info);
3817 dynobj = htab->root.dynobj;
3818 bed = get_elf_backend_data (dynobj);
3819 flags = bed->dynamic_sec_flags;
3820
3821 if (htab->root.iplt == NULL)
3822 {
3d4d4302
AM		 3823 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3824 flags | SEC_READONLY | SEC_CODE);
34e77a92 3825 if (s == NULL
a0f49396 3826 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3827 return FALSE;
3828 htab->root.iplt = s;
3829 }
3830
3831 if (htab->root.irelplt == NULL)
3832 {
3d4d4302
AM		 3833 s = bfd_make_section_anyway_with_flags (dynobj,
3834 RELOC_SECTION (htab, ".iplt"),
3835 flags | SEC_READONLY);
34e77a92 3836 if (s == NULL
a0f49396 3837 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3838 return FALSE;
3839 htab->root.irelplt = s;
3840 }
3841
3842 if (htab->root.igotplt == NULL)
3843 {
3d4d4302 3844 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3845 if (s == NULL
3846 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3847 return FALSE;
3848 htab->root.igotplt = s;
3849 }
3850 return TRUE;
3851}
3852
eed94f8f
NC		 3853/* Determine if we're dealing with a Thumb only architecture. */
3854
3855static bfd_boolean
3856using_thumb_only (struct elf32_arm_link_hash_table *globals)
3857{
2fd158eb
TP		 3858 int arch;
3859 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3860 Tag_CPU_arch_profile);
eed94f8f 3861
2fd158eb
TP		 3862 if (profile)
3863 return profile == 'M';
eed94f8f 3864
2fd158eb 3865 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3866
60a019a0 3867 /* Force return logic to be reviewed for each new architecture. */
031254f2 3868 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0 3869
2fd158eb
TP		 3870 if (arch == TAG_CPU_ARCH_V6_M
3871 || arch == TAG_CPU_ARCH_V6S_M
3872 || arch == TAG_CPU_ARCH_V7E_M
3873 || arch == TAG_CPU_ARCH_V8M_BASE
031254f2
AV		 3874 || arch == TAG_CPU_ARCH_V8M_MAIN
3875 || arch == TAG_CPU_ARCH_V8_1M_MAIN)
2fd158eb 3876 return TRUE;
eed94f8f 3877
2fd158eb 3878 return FALSE;
eed94f8f
NC		 3879}
3880
3881/* Determine if we're dealing with a Thumb-2 object. */
3882
3883static bfd_boolean
3884using_thumb2 (struct elf32_arm_link_hash_table *globals)
3885{
60a019a0
TP		 3886 int arch;
3887 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3888 Tag_THUMB_ISA_use);
3889
3890 if (thumb_isa)
3891 return thumb_isa == 2;
3892
3893 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3894
3895 /* Force return logic to be reviewed for each new architecture. */
031254f2 3896 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 3897
3898 return (arch == TAG_CPU_ARCH_V6T2
3899 || arch == TAG_CPU_ARCH_V7
3900 || arch == TAG_CPU_ARCH_V7E_M
3901 || arch == TAG_CPU_ARCH_V8
bff0500d 3902 || arch == TAG_CPU_ARCH_V8R
031254f2
AV		 3903 || arch == TAG_CPU_ARCH_V8M_MAIN
3904 || arch == TAG_CPU_ARCH_V8_1M_MAIN);
eed94f8f
NC		 3905}
3906
5e866f5a
TP		 3907/* Determine whether Thumb-2 BL instruction is available. */
3908
3909static bfd_boolean
3910using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3911{
3912 int arch =
3913 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3914
3915 /* Force return logic to be reviewed for each new architecture. */
031254f2 3916 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
5e866f5a
TP		 3917
3918 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3919 return (arch == TAG_CPU_ARCH_V6T2
3920 || arch >= TAG_CPU_ARCH_V7);
3921}
3922
00a97672
RS		 3923/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3924 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3925 hash table. */
3926
3927static bfd_boolean
57e8b36a 3928elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3929{
3930 struct elf32_arm_link_hash_table *htab;
3931
3932 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3933 if (htab == NULL)
3934 return FALSE;
3935
362d30a1 3936 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3937 return FALSE;
3938
3939 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3940 return FALSE;
3941
00a97672
RS		 3942 if (htab->vxworks_p)
3943 {
3944 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3945 return FALSE;
3946
0e1862bb 3947 if (bfd_link_pic (info))
00a97672
RS		 3948 {
3949 htab->plt_header_size = 0;
3950 htab->plt_entry_size
3951 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3952 }
3953 else
3954 {
3955 htab->plt_header_size
3956 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3957 htab->plt_entry_size
3958 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3959 }
aebf9be7
NC		 3960
3961 if (elf_elfheader (dynobj))
3962 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3963 }
eed94f8f
NC		 3964 else
3965 {
3966 /* PR ld/16017
3967 Test for thumb only architectures. Note - we cannot just call
3968 using_thumb_only() as the attributes in the output bfd have not been
3969 initialised at this point, so instead we use the input bfd. */
3970 bfd * saved_obfd = htab->obfd;
3971
3972 htab->obfd = dynobj;
3973 if (using_thumb_only (htab))
3974 {
3975 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3976 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3977 }
3978 htab->obfd = saved_obfd;
3979 }
5e681ec4 3980
7801f98f
CL		 3981 if (htab->fdpic_p) {
3982 htab->plt_header_size = 0;
3983 if (info->flags & DF_BIND_NOW)
3984 htab->plt_entry_size = 4 * (ARRAY_SIZE(elf32_arm_fdpic_plt_entry) - 5);
3985 else
3986 htab->plt_entry_size = 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry);
3987 }
3988
362d30a1
RS		 3989 if (!htab->root.splt
3990 || !htab->root.srelplt
9d19e4fd
AM		 3991 || !htab->root.sdynbss
3992 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 3993 abort ();
3994
3995 return TRUE;
3996}
3997
906e58ca
NC		 3998/* Copy the extra info we tack onto an elf_link_hash_entry. */
3999
4000static void
4001elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
4002 struct elf_link_hash_entry *dir,
4003 struct elf_link_hash_entry *ind)
4004{
4005 struct elf32_arm_link_hash_entry *edir, *eind;
4006
4007 edir = (struct elf32_arm_link_hash_entry *) dir;
4008 eind = (struct elf32_arm_link_hash_entry *) ind;
4009
0bdcacaf 4010 if (eind->dyn_relocs != NULL)
906e58ca 4011 {
0bdcacaf 4012 if (edir->dyn_relocs != NULL)
906e58ca 4013 {
0bdcacaf
RS		 4014 struct elf_dyn_relocs **pp;
4015 struct elf_dyn_relocs *p;
906e58ca
NC		 4016
4017 /* Add reloc counts against the indirect sym to the direct sym
4018 list. Merge any entries against the same section. */
0bdcacaf 4019 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 4020 {
0bdcacaf 4021 struct elf_dyn_relocs *q;
906e58ca 4022
0bdcacaf
RS		 4023 for (q = edir->dyn_relocs; q != NULL; q = q->next)
4024 if (q->sec == p->sec)
906e58ca
NC		 4025 {
4026 q->pc_count += p->pc_count;
4027 q->count += p->count;
4028 *pp = p->next;
4029 break;
4030 }
4031 if (q == NULL)
4032 pp = &p->next;
4033 }
0bdcacaf 4034 *pp = edir->dyn_relocs;
906e58ca
NC		 4035 }
4036
0bdcacaf
RS		 4037 edir->dyn_relocs = eind->dyn_relocs;
4038 eind->dyn_relocs = NULL;
906e58ca
NC		 4039 }
4040
4041 if (ind->root.type == bfd_link_hash_indirect)
4042 {
4043 /* Copy over PLT info. */
34e77a92
RS		 4044 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
4045 eind->plt.thumb_refcount = 0;
4046 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
4047 eind->plt.maybe_thumb_refcount = 0;
4048 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
4049 eind->plt.noncall_refcount = 0;
4050
e8b09b87
CL		 4051 /* Copy FDPIC counters. */
4052 edir->fdpic_cnts.gotofffuncdesc_cnt += eind->fdpic_cnts.gotofffuncdesc_cnt;
4053 edir->fdpic_cnts.gotfuncdesc_cnt += eind->fdpic_cnts.gotfuncdesc_cnt;
4054 edir->fdpic_cnts.funcdesc_cnt += eind->fdpic_cnts.funcdesc_cnt;
4055
34e77a92
RS		 4056 /* We should only allocate a function to .iplt once the final
4057 symbol information is known. */
4058 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 4059
4060 if (dir->got.refcount <= 0)
4061 {
4062 edir->tls_type = eind->tls_type;
4063 eind->tls_type = GOT_UNKNOWN;
4064 }
4065 }
4066
4067 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
4068}
4069
68faa637
AM		 4070/* Destroy an ARM elf linker hash table. */
4071
4072static void
d495ab0d 4073elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 4074{
4075 struct elf32_arm_link_hash_table *ret
d495ab0d 4076 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 4077
4078 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 4079 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 4080}
4081
906e58ca
NC		 4082/* Create an ARM elf linker hash table. */
4083
4084static struct bfd_link_hash_table *
4085elf32_arm_link_hash_table_create (bfd *abfd)
4086{
4087 struct elf32_arm_link_hash_table *ret;
4088 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
4089
7bf52ea2 4090 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 4091 if (ret == NULL)
4092 return NULL;
4093
4094 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
4095 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 4096 sizeof (struct elf32_arm_link_hash_entry),
4097 ARM_ELF_DATA))
906e58ca
NC		 4098 {
4099 free (ret);
4100 return NULL;
4101 }
4102
906e58ca 4103 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 4104 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 4105#ifdef FOUR_WORD_PLT
4106 ret->plt_header_size = 16;
4107 ret->plt_entry_size = 16;
4108#else
4109 ret->plt_header_size = 20;
1db37fe6 4110 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 4111#endif
f3185997 4112 ret->use_rel = TRUE;
906e58ca 4113 ret->obfd = abfd;
617a5ada 4114 ret->fdpic_p = 0;
906e58ca
NC		 4115
4116 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
4117 sizeof (struct elf32_arm_stub_hash_entry)))
4118 {
d495ab0d 4119 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 4120 return NULL;
4121 }
d495ab0d 4122 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 4123
4124 return &ret->root.root;
4125}
4126
cd1dac3d
DG		 4127/* Determine what kind of NOPs are available. */
4128
4129static bfd_boolean
4130arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
4131{
4132 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
4133 Tag_CPU_arch);
cd1dac3d 4134
60a019a0 4135 /* Force return logic to be reviewed for each new architecture. */
031254f2 4136 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 4137
4138 return (arch == TAG_CPU_ARCH_V6T2
4139 || arch == TAG_CPU_ARCH_V6K
4140 || arch == TAG_CPU_ARCH_V7
bff0500d
TP		 4141 || arch == TAG_CPU_ARCH_V8
4142 || arch == TAG_CPU_ARCH_V8R);
cd1dac3d
DG		 4143}
4144
f4ac8484
DJ		 4145static bfd_boolean
4146arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
4147{
4148 switch (stub_type)
4149 {
fea2b4d6 4150 case arm_stub_long_branch_thumb_only:
80c135e5 4151 case arm_stub_long_branch_thumb2_only:
d5a67c02 4152 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 4153 case arm_stub_long_branch_v4t_thumb_arm:
4154 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 4155 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 4156 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 4157 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 4158 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 4159 return TRUE;
4160 case arm_stub_none:
4161 BFD_FAIL ();
4162 return FALSE;
4163 break;
4164 default:
4165 return FALSE;
4166 }
4167}
4168
906e58ca
NC		 4169/* Determine the type of stub needed, if any, for a call. */
4170
4171static enum elf32_arm_stub_type
4172arm_type_of_stub (struct bfd_link_info *info,
4173 asection *input_sec,
4174 const Elf_Internal_Rela *rel,
34e77a92 4175 unsigned char st_type,
35fc36a8 4176 enum arm_st_branch_type *actual_branch_type,
906e58ca 4177 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 4178 bfd_vma destination,
4179 asection *sym_sec,
4180 bfd *input_bfd,
4181 const char *name)
906e58ca
NC		 4182{
4183 bfd_vma location;
4184 bfd_signed_vma branch_offset;
4185 unsigned int r_type;
4186 struct elf32_arm_link_hash_table * globals;
5e866f5a 4187 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 4188 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 4189 int use_plt = 0;
35fc36a8 4190 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 4191 union gotplt_union *root_plt;
4192 struct arm_plt_info *arm_plt;
d5a67c02
AV		 4193 int arch;
4194 int thumb2_movw;
906e58ca 4195
35fc36a8 4196 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 4197 return stub_type;
4198
906e58ca 4199 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4200 if (globals == NULL)
4201 return stub_type;
906e58ca
NC		 4202
4203 thumb_only = using_thumb_only (globals);
906e58ca 4204 thumb2 = using_thumb2 (globals);
5e866f5a 4205 thumb2_bl = using_thumb2_bl (globals);
906e58ca 4206
d5a67c02
AV		 4207 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
4208
4209 /* True for architectures that implement the thumb2 movw instruction. */
4210 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
4211
906e58ca
NC		 4212 /* Determine where the call point is. */
4213 location = (input_sec->output_offset
4214 + input_sec->output_section->vma
4215 + rel->r_offset);
4216
906e58ca
NC		 4217 r_type = ELF32_R_TYPE (rel->r_info);
4218
39f21624
NC		 4219 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4220 are considering a function call relocation. */
c5423981 4221 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
07d6d2b8 4222 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 4223 && branch_type == ST_BRANCH_TO_ARM)
4224 branch_type = ST_BRANCH_TO_THUMB;
4225
34e77a92
RS		 4226 /* For TLS call relocs, it is the caller's responsibility to provide
4227 the address of the appropriate trampoline. */
4228 if (r_type != R_ARM_TLS_CALL
4229 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 4230 && elf32_arm_get_plt_info (input_bfd, globals, hash,
4231 ELF32_R_SYM (rel->r_info), &root_plt,
4232 &arm_plt)
34e77a92 4233 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 4234 {
34e77a92 4235 asection *splt;
fe33d2fa 4236
34e77a92
RS		 4237 if (hash == NULL || hash->is_iplt)
4238 splt = globals->root.iplt;
4239 else
4240 splt = globals->root.splt;
4241 if (splt != NULL)
b38cadfb 4242 {
34e77a92
RS		 4243 use_plt = 1;
4244
4245 /* Note when dealing with PLT entries: the main PLT stub is in
4246 ARM mode, so if the branch is in Thumb mode, another
4247 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 4248 PLT stub. If a long branch stub is needed, we'll add a
4249 Thumb->Arm one and branch directly to the ARM PLT entry.
4250 Here, we have to check if a pre-PLT Thumb->ARM stub
4251 is needed and if it will be close enough. */
34e77a92
RS		 4252
4253 destination = (splt->output_section->vma
4254 + splt->output_offset
4255 + root_plt->offset);
4256 st_type = STT_FUNC;
2df2751d
CL		 4257
4258 /* Thumb branch/call to PLT: it can become a branch to ARM
4259 or to Thumb. We must perform the same checks and
4260 corrections as in elf32_arm_final_link_relocate. */
4261 if ((r_type == R_ARM_THM_CALL)
4262 || (r_type == R_ARM_THM_JUMP24))
4263 {
4264 if (globals->use_blx
4265 && r_type == R_ARM_THM_CALL
4266 && !thumb_only)
4267 {
4268 /* If the Thumb BLX instruction is available, convert
4269 the BL to a BLX instruction to call the ARM-mode
4270 PLT entry. */
4271 branch_type = ST_BRANCH_TO_ARM;
4272 }
4273 else
4274 {
4275 if (!thumb_only)
4276 /* Target the Thumb stub before the ARM PLT entry. */
4277 destination -= PLT_THUMB_STUB_SIZE;
4278 branch_type = ST_BRANCH_TO_THUMB;
4279 }
4280 }
4281 else
4282 {
4283 branch_type = ST_BRANCH_TO_ARM;
4284 }
34e77a92 4285 }
5fa9e92f 4286 }
34e77a92
RS		 4287 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4288 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 4289
fe33d2fa
CL		 4290 branch_offset = (bfd_signed_vma)(destination - location);
4291
0855e32b 4292 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 4293 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 4294 {
5fa9e92f
CL		 4295 /* Handle cases where:
4296 - this call goes too far (different Thumb/Thumb2 max
99059e56 4297 distance)
155d87d7 4298 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 4299 Thumb->Arm branch (not bl). A stub is needed in this case,
4300 but only if this call is not through a PLT entry. Indeed,
695344c0 4301 PLT stubs handle mode switching already. */
5e866f5a 4302 if ((!thumb2_bl
906e58ca
NC		 4303 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
4304 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 4305 || (thumb2_bl
906e58ca
NC		 4306 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4307 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4308 || (thumb2
4309 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4310 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4311 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4312 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4313 && (((r_type == R_ARM_THM_CALL
4314 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981 4315 || (r_type == R_ARM_THM_JUMP24)
07d6d2b8 4316 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4317 && !use_plt))
906e58ca 4318 {
2df2751d
CL		 4319 /* If we need to insert a Thumb-Thumb long branch stub to a
4320 PLT, use one that branches directly to the ARM PLT
4321 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4322 stub, undo this now. */
695344c0
NC		 4323 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4324 {
4325 branch_type = ST_BRANCH_TO_ARM;
4326 branch_offset += PLT_THUMB_STUB_SIZE;
4327 }
2df2751d 4328
35fc36a8 4329 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4330 {
4331 /* Thumb to thumb. */
4332 if (!thumb_only)
4333 {
d5a67c02 4334 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4335 _bfd_error_handler
871b3ab2 4336 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4337 " section with SHF_ARM_PURECODE section"
4338 " attribute is only supported for M-profile"
90b6238f 4339 " targets that implement the movw instruction"),
10463f39 4340 input_bfd, input_sec);
d5a67c02 4341
0e1862bb 4342 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4343 /* PIC stubs. */
155d87d7 4344 ? ((globals->use_blx
9553db3c 4345 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4346 /* V5T and above. Stub starts with ARM code, so
4347 we must be able to switch mode before
4348 reaching it, which is only possible for 'bl'
4349 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4350 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4351 /* On V4T, use Thumb code only. */
d3626fb0 4352 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4353
4354 /* non-PIC stubs. */
155d87d7 4355 : ((globals->use_blx
9553db3c 4356 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4357 /* V5T and above. */
4358 ? arm_stub_long_branch_any_any
4359 /* V4T. */
d3626fb0 4360 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4361 }
4362 else
4363 {
d5a67c02
AV		 4364 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4365 stub_type = arm_stub_long_branch_thumb2_only_pure;
4366 else
4367 {
4368 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4369 _bfd_error_handler
871b3ab2 4370 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4371 " section with SHF_ARM_PURECODE section"
4372 " attribute is only supported for M-profile"
90b6238f 4373 " targets that implement the movw instruction"),
10463f39 4374 input_bfd, input_sec);
d5a67c02
AV		 4375
4376 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4377 /* PIC stub. */
4378 ? arm_stub_long_branch_thumb_only_pic
4379 /* non-PIC stub. */
4380 : (thumb2 ? arm_stub_long_branch_thumb2_only
4381 : arm_stub_long_branch_thumb_only);
4382 }
906e58ca
NC		 4383 }
4384 }
4385 else
4386 {
d5a67c02 4387 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4388 _bfd_error_handler
871b3ab2 4389 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4390 " section with SHF_ARM_PURECODE section"
4391 " attribute is only supported" " for M-profile"
90b6238f 4392 " targets that implement the movw instruction"),
10463f39 4393 input_bfd, input_sec);
d5a67c02 4394
906e58ca 4395 /* Thumb to arm. */
c820be07
NC		 4396 if (sym_sec != NULL
4397 && sym_sec->owner != NULL
4398 && !INTERWORK_FLAG (sym_sec->owner))
4399 {
4eca0228 4400 _bfd_error_handler
90b6238f
AM		 4401 (_("%pB(%s): warning: interworking not enabled;"
4402 " first occurrence: %pB: %s call to %s"),
4403 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
c820be07
NC		 4404 }
4405
0855e32b 4406 stub_type =
0e1862bb 4407 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4408 /* PIC stubs. */
0855e32b 4409 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4410 /* TLS PIC stubs. */
0855e32b
NS		 4411 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4412 : arm_stub_long_branch_v4t_thumb_tls_pic)
4413 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4414 /* V5T PIC and above. */
4415 ? arm_stub_long_branch_any_arm_pic
4416 /* V4T PIC stub. */
4417 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4418
4419 /* non-PIC stubs. */
0855e32b 4420 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4421 /* V5T and above. */
4422 ? arm_stub_long_branch_any_any
4423 /* V4T. */
4424 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4425
4426 /* Handle v4t short branches. */
fea2b4d6 4427 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4428 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4429 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4430 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4431 }
4432 }
4433 }
fe33d2fa
CL		 4434 else if (r_type == R_ARM_CALL
4435 || r_type == R_ARM_JUMP24
0855e32b
NS		 4436 || r_type == R_ARM_PLT32
4437 || r_type == R_ARM_TLS_CALL)
906e58ca 4438 {
d5a67c02 4439 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4440 _bfd_error_handler
871b3ab2 4441 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4442 " section with SHF_ARM_PURECODE section"
4443 " attribute is only supported for M-profile"
90b6238f 4444 " targets that implement the movw instruction"),
10463f39 4445 input_bfd, input_sec);
35fc36a8 4446 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4447 {
4448 /* Arm to thumb. */
c820be07
NC		 4449
4450 if (sym_sec != NULL
4451 && sym_sec->owner != NULL
4452 && !INTERWORK_FLAG (sym_sec->owner))
4453 {
4eca0228 4454 _bfd_error_handler
90b6238f
AM		 4455 (_("%pB(%s): warning: interworking not enabled;"
4456 " first occurrence: %pB: %s call to %s"),
4457 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
c820be07
NC		 4458 }
4459
4460 /* We have an extra 2-bytes reach because of
4461 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4462 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4463 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4464 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4465 || (r_type == R_ARM_JUMP24)
4466 || (r_type == R_ARM_PLT32))
906e58ca 4467 {
0e1862bb 4468 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4469 /* PIC stubs. */
ebe24dd4
CL		 4470 ? ((globals->use_blx)
4471 /* V5T and above. */
4472 ? arm_stub_long_branch_any_thumb_pic
4473 /* V4T stub. */
4474 : arm_stub_long_branch_v4t_arm_thumb_pic)
4475
c2b4a39d
CL		 4476 /* non-PIC stubs. */
4477 : ((globals->use_blx)
4478 /* V5T and above. */
4479 ? arm_stub_long_branch_any_any
4480 /* V4T. */
4481 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4482 }
4483 }
4484 else
4485 {
4486 /* Arm to arm. */
4487 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4488 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4489 {
0855e32b 4490 stub_type =
0e1862bb 4491 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4492 /* PIC stubs. */
0855e32b 4493 ? (r_type == R_ARM_TLS_CALL
6a631e86 4494 /* TLS PIC Stub. */
0855e32b 4495 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4496 : (globals->nacl_p
4497 ? arm_stub_long_branch_arm_nacl_pic
4498 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4499 /* non-PIC stubs. */
7a89b94e
NC		 4500 : (globals->nacl_p
4501 ? arm_stub_long_branch_arm_nacl
4502 : arm_stub_long_branch_any_any);
906e58ca
NC		 4503 }
4504 }
4505 }
4506
fe33d2fa
CL		 4507 /* If a stub is needed, record the actual destination type. */
4508 if (stub_type != arm_stub_none)
35fc36a8 4509 *actual_branch_type = branch_type;
fe33d2fa 4510
906e58ca
NC		 4511 return stub_type;
4512}
4513
4514/* Build a name for an entry in the stub hash table. */
4515
4516static char *
4517elf32_arm_stub_name (const asection *input_section,
4518 const asection *sym_sec,
4519 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4520 const Elf_Internal_Rela *rel,
4521 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4522{
4523 char *stub_name;
4524 bfd_size_type len;
4525
4526 if (hash)
4527 {
fe33d2fa 4528 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4529 stub_name = (char *) bfd_malloc (len);
906e58ca 4530 if (stub_name != NULL)
fe33d2fa 4531 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4532 input_section->id & 0xffffffff,
4533 hash->root.root.root.string,
fe33d2fa
CL		 4534 (int) rel->r_addend & 0xffffffff,
4535 (int) stub_type);
906e58ca
NC		 4536 }
4537 else
4538 {
fe33d2fa 4539 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4540 stub_name = (char *) bfd_malloc (len);
906e58ca 4541 if (stub_name != NULL)
fe33d2fa 4542 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4543 input_section->id & 0xffffffff,
4544 sym_sec->id & 0xffffffff,
0855e32b
NS		 4545 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4546 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4547 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4548 (int) rel->r_addend & 0xffffffff,
4549 (int) stub_type);
906e58ca
NC		 4550 }
4551
4552 return stub_name;
4553}
4554
4555/* Look up an entry in the stub hash. Stub entries are cached because
4556 creating the stub name takes a bit of time. */
4557
4558static struct elf32_arm_stub_hash_entry *
4559elf32_arm_get_stub_entry (const asection *input_section,
4560 const asection *sym_sec,
4561 struct elf_link_hash_entry *hash,
4562 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4563 struct elf32_arm_link_hash_table *htab,
4564 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4565{
4566 struct elf32_arm_stub_hash_entry *stub_entry;
4567 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4568 const asection *id_sec;
4569
4570 if ((input_section->flags & SEC_CODE) == 0)
4571 return NULL;
4572
4573 /* If this input section is part of a group of sections sharing one
4574 stub section, then use the id of the first section in the group.
4575 Stub names need to include a section id, as there may well be
4576 more than one stub used to reach say, printf, and we need to
4577 distinguish between them. */
c2abbbeb 4578 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4579 id_sec = htab->stub_group[input_section->id].link_sec;
4580
4581 if (h != NULL && h->stub_cache != NULL
4582 && h->stub_cache->h == h
fe33d2fa
CL		 4583 && h->stub_cache->id_sec == id_sec
4584 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4585 {
4586 stub_entry = h->stub_cache;
4587 }
4588 else
4589 {
4590 char *stub_name;
4591
fe33d2fa 4592 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4593 if (stub_name == NULL)
4594 return NULL;
4595
4596 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4597 stub_name, FALSE, FALSE);
4598 if (h != NULL)
4599 h->stub_cache = stub_entry;
4600
4601 free (stub_name);
4602 }
4603
4604 return stub_entry;
4605}
4606
daa4adae
TP		 4607/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4608 section. */
4609
4610static bfd_boolean
4611arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4612{
4613 if (stub_type >= max_stub_type)
4614 abort (); /* Should be unreachable. */
4615
4ba2ef8f
TP		 4616 switch (stub_type)
4617 {
4618 case arm_stub_cmse_branch_thumb_only:
4619 return TRUE;
4620
4621 default:
4622 return FALSE;
4623 }
4624
4625 abort (); /* Should be unreachable. */
daa4adae
TP		 4626}
4627
4628/* Required alignment (as a power of 2) for the dedicated section holding
4629 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4630 with input sections. */
4631
4632static int
4633arm_dedicated_stub_output_section_required_alignment
4634 (enum elf32_arm_stub_type stub_type)
4635{
4636 if (stub_type >= max_stub_type)
4637 abort (); /* Should be unreachable. */
4638
4ba2ef8f
TP		 4639 switch (stub_type)
4640 {
4641 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4642 boundary. */
4643 case arm_stub_cmse_branch_thumb_only:
4644 return 5;
4645
4646 default:
4647 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4648 return 0;
4649 }
4650
4651 abort (); /* Should be unreachable. */
daa4adae
TP		 4652}
4653
4654/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4655 NULL if veneers of this type are interspersed with input sections. */
4656
4657static const char *
4658arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4659{
4660 if (stub_type >= max_stub_type)
4661 abort (); /* Should be unreachable. */
4662
4ba2ef8f
TP		 4663 switch (stub_type)
4664 {
4665 case arm_stub_cmse_branch_thumb_only:
4666 return ".gnu.sgstubs";
4667
4668 default:
4669 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4670 return NULL;
4671 }
4672
4673 abort (); /* Should be unreachable. */
daa4adae
TP		 4674}
4675
4676/* If veneers of type STUB_TYPE should go in a dedicated output section,
4677 returns the address of the hash table field in HTAB holding a pointer to the
4678 corresponding input section. Otherwise, returns NULL. */
4679
4680static asection **
4ba2ef8f
TP		 4681arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4682 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4683{
4684 if (stub_type >= max_stub_type)
4685 abort (); /* Should be unreachable. */
4686
4ba2ef8f
TP		 4687 switch (stub_type)
4688 {
4689 case arm_stub_cmse_branch_thumb_only:
4690 return &htab->cmse_stub_sec;
4691
4692 default:
4693 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4694 return NULL;
4695 }
4696
4697 abort (); /* Should be unreachable. */
daa4adae
TP		 4698}
4699
4700/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4701 is the section that branch into veneer and can be NULL if stub should go in
4702 a dedicated output section. Returns a pointer to the stub section, and the
4703 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4704 LINK_SEC_P may be NULL. */
906e58ca 4705
48229727
JB		 4706static asection *
4707elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4708 struct elf32_arm_link_hash_table *htab,
4709 enum elf32_arm_stub_type stub_type)
906e58ca 4710{
daa4adae
TP		 4711 asection *link_sec, *out_sec, **stub_sec_p;
4712 const char *stub_sec_prefix;
4713 bfd_boolean dedicated_output_section =
4714 arm_dedicated_stub_output_section_required (stub_type);
4715 int align;
906e58ca 4716
daa4adae 4717 if (dedicated_output_section)
906e58ca 4718 {
daa4adae
TP		 4719 bfd *output_bfd = htab->obfd;
4720 const char *out_sec_name =
4721 arm_dedicated_stub_output_section_name (stub_type);
4722 link_sec = NULL;
4723 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4724 stub_sec_prefix = out_sec_name;
4725 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4726 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4727 if (out_sec == NULL)
906e58ca 4728 {
90b6238f 4729 _bfd_error_handler (_("no address assigned to the veneers output "
4eca0228 4730 "section %s"), out_sec_name);
daa4adae 4731 return NULL;
906e58ca 4732 }
daa4adae
TP		 4733 }
4734 else
4735 {
c2abbbeb 4736 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4737 link_sec = htab->stub_group[section->id].link_sec;
4738 BFD_ASSERT (link_sec != NULL);
4739 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4740 if (*stub_sec_p == NULL)
4741 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4742 stub_sec_prefix = link_sec->name;
4743 out_sec = link_sec->output_section;
4744 align = htab->nacl_p ? 4 : 3;
906e58ca 4745 }
b38cadfb 4746
daa4adae
TP		 4747 if (*stub_sec_p == NULL)
4748 {
4749 size_t namelen;
4750 bfd_size_type len;
4751 char *s_name;
4752
4753 namelen = strlen (stub_sec_prefix);
4754 len = namelen + sizeof (STUB_SUFFIX);
4755 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4756 if (s_name == NULL)
4757 return NULL;
4758
4759 memcpy (s_name, stub_sec_prefix, namelen);
4760 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4761 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4762 align);
4763 if (*stub_sec_p == NULL)
4764 return NULL;
4765
4766 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4767 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4768 | SEC_KEEP;
4769 }
4770
4771 if (!dedicated_output_section)
4772 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4773
48229727
JB		 4774 if (link_sec_p)
4775 *link_sec_p = link_sec;
b38cadfb 4776
daa4adae 4777 return *stub_sec_p;
48229727
JB		 4778}
4779
4780/* Add a new stub entry to the stub hash. Not all fields of the new
4781 stub entry are initialised. */
4782
4783static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4784elf32_arm_add_stub (const char *stub_name, asection *section,
4785 struct elf32_arm_link_hash_table *htab,
4786 enum elf32_arm_stub_type stub_type)
48229727
JB		 4787{
4788 asection *link_sec;
4789 asection *stub_sec;
4790 struct elf32_arm_stub_hash_entry *stub_entry;
4791
daa4adae
TP		 4792 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4793 stub_type);
48229727
JB		 4794 if (stub_sec == NULL)
4795 return NULL;
906e58ca
NC		 4796
4797 /* Enter this entry into the linker stub hash table. */
4798 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4799 TRUE, FALSE);
4800 if (stub_entry == NULL)
4801 {
6bde4c52
TP		 4802 if (section == NULL)
4803 section = stub_sec;
871b3ab2 4804 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 4805 section->owner, stub_name);
906e58ca
NC		 4806 return NULL;
4807 }
4808
4809 stub_entry->stub_sec = stub_sec;
0955507f 4810 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4811 stub_entry->id_sec = link_sec;
4812
906e58ca
NC		 4813 return stub_entry;
4814}
4815
4816/* Store an Arm insn into an output section not processed by
4817 elf32_arm_write_section. */
4818
4819static void
8029a119
NC		 4820put_arm_insn (struct elf32_arm_link_hash_table * htab,
4821 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4822{
4823 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4824 bfd_putl32 (val, ptr);
4825 else
4826 bfd_putb32 (val, ptr);
4827}
4828
4829/* Store a 16-bit Thumb insn into an output section not processed by
4830 elf32_arm_write_section. */
4831
4832static void
8029a119
NC		 4833put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4834 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4835{
4836 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4837 bfd_putl16 (val, ptr);
4838 else
4839 bfd_putb16 (val, ptr);
4840}
4841
a504d23a
LA		 4842/* Store a Thumb2 insn into an output section not processed by
4843 elf32_arm_write_section. */
4844
4845static void
4846put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4847 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4848{
4849 /* T2 instructions are 16-bit streamed. */
4850 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4851 {
4852 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4853 bfd_putl16 ((val & 0xffff), ptr + 2);
4854 }
4855 else
4856 {
4857 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4858 bfd_putb16 ((val & 0xffff), ptr + 2);
4859 }
4860}
4861
0855e32b
NS		 4862/* If it's possible to change R_TYPE to a more efficient access
4863 model, return the new reloc type. */
4864
4865static unsigned
b38cadfb 4866elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4867 struct elf_link_hash_entry *h)
4868{
4869 int is_local = (h == NULL);
4870
0e1862bb
L		 4871 if (bfd_link_pic (info)
4872 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4873 return r_type;
4874
b38cadfb 4875 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4876 switch (r_type)
4877 {
4878 case R_ARM_TLS_GOTDESC:
4879 case R_ARM_TLS_CALL:
4880 case R_ARM_THM_TLS_CALL:
4881 case R_ARM_TLS_DESCSEQ:
4882 case R_ARM_THM_TLS_DESCSEQ:
4883 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4884 }
4885
4886 return r_type;
4887}
4888
48229727
JB		 4889static bfd_reloc_status_type elf32_arm_final_link_relocate
4890 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4891 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4892 const char *, unsigned char, enum arm_st_branch_type,
4893 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4894
4563a860
JB		 4895static unsigned int
4896arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4897{
4898 switch (stub_type)
4899 {
4900 case arm_stub_a8_veneer_b_cond:
4901 case arm_stub_a8_veneer_b:
4902 case arm_stub_a8_veneer_bl:
4903 return 2;
4904
4905 case arm_stub_long_branch_any_any:
4906 case arm_stub_long_branch_v4t_arm_thumb:
4907 case arm_stub_long_branch_thumb_only:
80c135e5 4908 case arm_stub_long_branch_thumb2_only:
d5a67c02 4909 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4910 case arm_stub_long_branch_v4t_thumb_thumb:
4911 case arm_stub_long_branch_v4t_thumb_arm:
4912 case arm_stub_short_branch_v4t_thumb_arm:
4913 case arm_stub_long_branch_any_arm_pic:
4914 case arm_stub_long_branch_any_thumb_pic:
4915 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4916 case arm_stub_long_branch_v4t_arm_thumb_pic:
4917 case arm_stub_long_branch_v4t_thumb_arm_pic:
4918 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4919 case arm_stub_long_branch_any_tls_pic:
4920 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4921 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4922 case arm_stub_a8_veneer_blx:
4923 return 4;
b38cadfb 4924
7a89b94e
NC		 4925 case arm_stub_long_branch_arm_nacl:
4926 case arm_stub_long_branch_arm_nacl_pic:
4927 return 16;
4928
4563a860
JB		 4929 default:
4930 abort (); /* Should be unreachable. */
4931 }
4932}
4933
4f4faa4d
TP		 4934/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4935 veneering (TRUE) or have their own symbol (FALSE). */
4936
4937static bfd_boolean
4938arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4939{
4940 if (stub_type >= max_stub_type)
4941 abort (); /* Should be unreachable. */
4942
4ba2ef8f
TP		 4943 switch (stub_type)
4944 {
4945 case arm_stub_cmse_branch_thumb_only:
4946 return TRUE;
4947
4948 default:
4949 return FALSE;
4950 }
4951
4952 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4953}
4954
d7c5bd02
TP		 4955/* Returns the padding needed for the dedicated section used stubs of type
4956 STUB_TYPE. */
4957
4958static int
4959arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4960{
4961 if (stub_type >= max_stub_type)
4962 abort (); /* Should be unreachable. */
4963
4ba2ef8f
TP		 4964 switch (stub_type)
4965 {
4966 case arm_stub_cmse_branch_thumb_only:
4967 return 32;
4968
4969 default:
4970 return 0;
4971 }
4972
4973 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4974}
4975
0955507f
TP		 4976/* If veneers of type STUB_TYPE should go in a dedicated output section,
4977 returns the address of the hash table field in HTAB holding the offset at
4978 which new veneers should be layed out in the stub section. */
4979
4980static bfd_vma*
4981arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
4982 enum elf32_arm_stub_type stub_type)
4983{
4984 switch (stub_type)
4985 {
4986 case arm_stub_cmse_branch_thumb_only:
4987 return &htab->new_cmse_stub_offset;
4988
4989 default:
4990 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4991 return NULL;
4992 }
4993}
4994
906e58ca
NC		 4995static bfd_boolean
4996arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4997 void * in_arg)
4998{
7a89b94e 4999#define MAXRELOCS 3
0955507f 5000 bfd_boolean removed_sg_veneer;
906e58ca 5001 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 5002 struct elf32_arm_link_hash_table *globals;
906e58ca 5003 struct bfd_link_info *info;
906e58ca
NC		 5004 asection *stub_sec;
5005 bfd *stub_bfd;
906e58ca
NC		 5006 bfd_byte *loc;
5007 bfd_vma sym_value;
5008 int template_size;
5009 int size;
d3ce72d0 5010 const insn_sequence *template_sequence;
906e58ca 5011 int i;
48229727
JB		 5012 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
5013 int stub_reloc_offset[MAXRELOCS] = {0, 0};
5014 int nrelocs = 0;
0955507f 5015 int just_allocated = 0;
906e58ca
NC		 5016
5017 /* Massage our args to the form they really have. */
5018 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5019 info = (struct bfd_link_info *) in_arg;
5020
5021 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 5022 if (globals == NULL)
5023 return FALSE;
906e58ca 5024
906e58ca
NC		 5025 stub_sec = stub_entry->stub_sec;
5026
4dfe6ac6 5027 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 5028 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
5029 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 5030 return TRUE;
fe33d2fa 5031
0955507f
TP		 5032 /* Assign a slot at the end of section if none assigned yet. */
5033 if (stub_entry->stub_offset == (bfd_vma) -1)
5034 {
5035 stub_entry->stub_offset = stub_sec->size;
5036 just_allocated = 1;
5037 }
906e58ca
NC		 5038 loc = stub_sec->contents + stub_entry->stub_offset;
5039
5040 stub_bfd = stub_sec->owner;
5041
906e58ca
NC		 5042 /* This is the address of the stub destination. */
5043 sym_value = (stub_entry->target_value
5044 + stub_entry->target_section->output_offset
5045 + stub_entry->target_section->output_section->vma);
5046
d3ce72d0 5047 template_sequence = stub_entry->stub_template;
461a49ca 5048 template_size = stub_entry->stub_template_size;
906e58ca
NC		 5049
5050 size = 0;
461a49ca 5051 for (i = 0; i < template_size; i++)
906e58ca 5052 {
d3ce72d0 5053 switch (template_sequence[i].type)
461a49ca
DJ		 5054 {
5055 case THUMB16_TYPE:
48229727 5056 {
d3ce72d0
NC		 5057 bfd_vma data = (bfd_vma) template_sequence[i].data;
5058 if (template_sequence[i].reloc_addend != 0)
48229727 5059 {
99059e56
RM		 5060 /* We've borrowed the reloc_addend field to mean we should
5061 insert a condition code into this (Thumb-1 branch)
5062 instruction. See THUMB16_BCOND_INSN. */
5063 BFD_ASSERT ((data & 0xff00) == 0xd000);
5064 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 5065 }
fe33d2fa 5066 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 5067 size += 2;
5068 }
461a49ca 5069 break;
906e58ca 5070
48229727 5071 case THUMB32_TYPE:
fe33d2fa
CL		 5072 bfd_put_16 (stub_bfd,
5073 (template_sequence[i].data >> 16) & 0xffff,
5074 loc + size);
5075 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
5076 loc + size + 2);
99059e56
RM		 5077 if (template_sequence[i].r_type != R_ARM_NONE)
5078 {
5079 stub_reloc_idx[nrelocs] = i;
5080 stub_reloc_offset[nrelocs++] = size;
5081 }
5082 size += 4;
5083 break;
48229727 5084
461a49ca 5085 case ARM_TYPE:
fe33d2fa
CL		 5086 bfd_put_32 (stub_bfd, template_sequence[i].data,
5087 loc + size);
461a49ca
DJ		 5088 /* Handle cases where the target is encoded within the
5089 instruction. */
d3ce72d0 5090 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 5091 {
48229727
JB		 5092 stub_reloc_idx[nrelocs] = i;
5093 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5094 }
5095 size += 4;
5096 break;
5097
5098 case DATA_TYPE:
d3ce72d0 5099 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 5100 stub_reloc_idx[nrelocs] = i;
5101 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5102 size += 4;
5103 break;
5104
5105 default:
5106 BFD_FAIL ();
5107 return FALSE;
5108 }
906e58ca 5109 }
461a49ca 5110
0955507f
TP		 5111 if (just_allocated)
5112 stub_sec->size += size;
906e58ca 5113
461a49ca
DJ		 5114 /* Stub size has already been computed in arm_size_one_stub. Check
5115 consistency. */
5116 BFD_ASSERT (size == stub_entry->stub_size);
5117
906e58ca 5118 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 5119 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 5120 sym_value |= 1;
5121
0955507f
TP		 5122 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5123 to relocate in each stub. */
5124 removed_sg_veneer =
5125 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5126 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 5127
48229727 5128 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 5129 {
5130 Elf_Internal_Rela rel;
5131 bfd_boolean unresolved_reloc;
5132 char *error_message;
5133 bfd_vma points_to =
5134 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
5135
5136 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
5137 rel.r_info = ELF32_R_INFO (0,
5138 template_sequence[stub_reloc_idx[i]].r_type);
5139 rel.r_addend = 0;
5140
5141 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
5142 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5143 template should refer back to the instruction after the original
5144 branch. We use target_section as Cortex-A8 erratum workaround stubs
5145 are only generated when both source and target are in the same
5146 section. */
5147 points_to = stub_entry->target_section->output_section->vma
5148 + stub_entry->target_section->output_offset
5149 + stub_entry->source_value;
5150
5151 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
5152 (template_sequence[stub_reloc_idx[i]].r_type),
5153 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
5154 points_to, info, stub_entry->target_section, "", STT_FUNC,
5155 stub_entry->branch_type,
5156 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
5157 &error_message);
5158 }
906e58ca
NC		 5159
5160 return TRUE;
48229727 5161#undef MAXRELOCS
906e58ca
NC		 5162}
5163
48229727
JB		 5164/* Calculate the template, template size and instruction size for a stub.
5165 Return value is the instruction size. */
906e58ca 5166
48229727
JB		 5167static unsigned int
5168find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
5169 const insn_sequence **stub_template,
5170 int *stub_template_size)
906e58ca 5171{
d3ce72d0 5172 const insn_sequence *template_sequence = NULL;
48229727
JB		 5173 int template_size = 0, i;
5174 unsigned int size;
906e58ca 5175
d3ce72d0 5176 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 5177 if (stub_template)
5178 *stub_template = template_sequence;
5179
48229727 5180 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 5181 if (stub_template_size)
5182 *stub_template_size = template_size;
906e58ca
NC		 5183
5184 size = 0;
461a49ca
DJ		 5185 for (i = 0; i < template_size; i++)
5186 {
d3ce72d0 5187 switch (template_sequence[i].type)
461a49ca
DJ		 5188 {
5189 case THUMB16_TYPE:
5190 size += 2;
5191 break;
5192
5193 case ARM_TYPE:
48229727 5194 case THUMB32_TYPE:
461a49ca
DJ		 5195 case DATA_TYPE:
5196 size += 4;
5197 break;
5198
5199 default:
5200 BFD_FAIL ();
2a229407 5201 return 0;
461a49ca
DJ		 5202 }
5203 }
5204
48229727
JB		 5205 return size;
5206}
5207
5208/* As above, but don't actually build the stub. Just bump offset so
5209 we know stub section sizes. */
5210
5211static bfd_boolean
5212arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 5213 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 5214{
5215 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 5216 const insn_sequence *template_sequence;
48229727
JB		 5217 int template_size, size;
5218
5219 /* Massage our args to the form they really have. */
5220 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 5221
5222 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
5223 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
5224
d3ce72d0 5225 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 5226 &template_size);
5227
0955507f
TP		 5228 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5229 if (stub_entry->stub_template_size)
5230 {
5231 stub_entry->stub_size = size;
5232 stub_entry->stub_template = template_sequence;
5233 stub_entry->stub_template_size = template_size;
5234 }
5235
5236 /* Already accounted for. */
5237 if (stub_entry->stub_offset != (bfd_vma) -1)
5238 return TRUE;
461a49ca 5239
906e58ca
NC		 5240 size = (size + 7) & ~7;
5241 stub_entry->stub_sec->size += size;
461a49ca 5242
906e58ca
NC		 5243 return TRUE;
5244}
5245
5246/* External entry points for sizing and building linker stubs. */
5247
5248/* Set up various things so that we can make a list of input sections
5249 for each output section included in the link. Returns -1 on error,
5250 0 when no stubs will be needed, and 1 on success. */
5251
5252int
5253elf32_arm_setup_section_lists (bfd *output_bfd,
5254 struct bfd_link_info *info)
5255{
5256 bfd *input_bfd;
5257 unsigned int bfd_count;
7292b3ac 5258 unsigned int top_id, top_index;
906e58ca
NC		 5259 asection *section;
5260 asection **input_list, **list;
5261 bfd_size_type amt;
5262 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5263
4dfe6ac6
NC		 5264 if (htab == NULL)
5265 return 0;
906e58ca
NC		 5266 if (! is_elf_hash_table (htab))
5267 return 0;
5268
5269 /* Count the number of input BFDs and find the top input section id. */
5270 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
5271 input_bfd != NULL;
c72f2fb2 5272 input_bfd = input_bfd->link.next)
906e58ca
NC		 5273 {
5274 bfd_count += 1;
5275 for (section = input_bfd->sections;
5276 section != NULL;
5277 section = section->next)
5278 {
5279 if (top_id < section->id)
5280 top_id = section->id;
5281 }
5282 }
5283 htab->bfd_count = bfd_count;
5284
5285 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 5286 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 5287 if (htab->stub_group == NULL)
5288 return -1;
fe33d2fa 5289 htab->top_id = top_id;
906e58ca
NC		 5290
5291 /* We can't use output_bfd->section_count here to find the top output
5292 section index as some sections may have been removed, and
5293 _bfd_strip_section_from_output doesn't renumber the indices. */
5294 for (section = output_bfd->sections, top_index = 0;
5295 section != NULL;
5296 section = section->next)
5297 {
5298 if (top_index < section->index)
5299 top_index = section->index;
5300 }
5301
5302 htab->top_index = top_index;
5303 amt = sizeof (asection *) * (top_index + 1);
21d799b5 5304 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 5305 htab->input_list = input_list;
5306 if (input_list == NULL)
5307 return -1;
5308
5309 /* For sections we aren't interested in, mark their entries with a
5310 value we can check later. */
5311 list = input_list + top_index;
5312 do
5313 *list = bfd_abs_section_ptr;
5314 while (list-- != input_list);
5315
5316 for (section = output_bfd->sections;
5317 section != NULL;
5318 section = section->next)
5319 {
5320 if ((section->flags & SEC_CODE) != 0)
5321 input_list[section->index] = NULL;
5322 }
5323
5324 return 1;
5325}
5326
5327/* The linker repeatedly calls this function for each input section,
5328 in the order that input sections are linked into output sections.
5329 Build lists of input sections to determine groupings between which
5330 we may insert linker stubs. */
5331
5332void
5333elf32_arm_next_input_section (struct bfd_link_info *info,
5334 asection *isec)
5335{
5336 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5337
4dfe6ac6
NC		 5338 if (htab == NULL)
5339 return;
5340
906e58ca
NC		 5341 if (isec->output_section->index <= htab->top_index)
5342 {
5343 asection **list = htab->input_list + isec->output_section->index;
5344
a7470592 5345 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5346 {
5347 /* Steal the link_sec pointer for our list. */
5348#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5349 /* This happens to make the list in reverse order,
07d72278 5350 which we reverse later. */
906e58ca
NC		 5351 PREV_SEC (isec) = *list;
5352 *list = isec;
5353 }
5354 }
5355}
5356
5357/* See whether we can group stub sections together. Grouping stub
5358 sections may result in fewer stubs. More importantly, we need to
07d72278 5359 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5360 .fini output sections respectively, because glibc splits the
5361 _init and _fini functions into multiple parts. Putting a stub in
5362 the middle of a function is not a good idea. */
5363
5364static void
5365group_sections (struct elf32_arm_link_hash_table *htab,
5366 bfd_size_type stub_group_size,
07d72278 5367 bfd_boolean stubs_always_after_branch)
906e58ca 5368{
07d72278 5369 asection **list = htab->input_list;
906e58ca
NC		 5370
5371 do
5372 {
5373 asection *tail = *list;
07d72278 5374 asection *head;
906e58ca
NC		 5375
5376 if (tail == bfd_abs_section_ptr)
5377 continue;
5378
07d72278
DJ		 5379 /* Reverse the list: we must avoid placing stubs at the
5380 beginning of the section because the beginning of the text
5381 section may be required for an interrupt vector in bare metal
5382 code. */
5383#define NEXT_SEC PREV_SEC
e780aef2
CL		 5384 head = NULL;
5385 while (tail != NULL)
99059e56
RM		 5386 {
5387 /* Pop from tail. */
5388 asection *item = tail;
5389 tail = PREV_SEC (item);
e780aef2 5390
99059e56
RM		 5391 /* Push on head. */
5392 NEXT_SEC (item) = head;
5393 head = item;
5394 }
07d72278
DJ		 5395
5396 while (head != NULL)
906e58ca
NC		 5397 {
5398 asection *curr;
07d72278 5399 asection *next;
e780aef2
CL		 5400 bfd_vma stub_group_start = head->output_offset;
5401 bfd_vma end_of_next;
906e58ca 5402
07d72278 5403 curr = head;
e780aef2 5404 while (NEXT_SEC (curr) != NULL)
8cd931b7 5405 {
e780aef2
CL		 5406 next = NEXT_SEC (curr);
5407 end_of_next = next->output_offset + next->size;
5408 if (end_of_next - stub_group_start >= stub_group_size)
5409 /* End of NEXT is too far from start, so stop. */
8cd931b7 5410 break;
e780aef2
CL		 5411 /* Add NEXT to the group. */
5412 curr = next;
8cd931b7 5413 }
906e58ca 5414
07d72278 5415 /* OK, the size from the start to the start of CURR is less
906e58ca 5416 than stub_group_size and thus can be handled by one stub
07d72278 5417 section. (Or the head section is itself larger than
906e58ca
NC		 5418 stub_group_size, in which case we may be toast.)
5419 We should really be keeping track of the total size of
5420 stubs added here, as stubs contribute to the final output
7fb9f789 5421 section size. */
906e58ca
NC		 5422 do
5423 {
07d72278 5424 next = NEXT_SEC (head);
906e58ca 5425 /* Set up this stub group. */
07d72278 5426 htab->stub_group[head->id].link_sec = curr;
906e58ca 5427 }
07d72278 5428 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5429
5430 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5431 bytes after the stub section can be handled by it too. */
5432 if (!stubs_always_after_branch)
906e58ca 5433 {
e780aef2
CL		 5434 stub_group_start = curr->output_offset + curr->size;
5435
8cd931b7 5436 while (next != NULL)
906e58ca 5437 {
e780aef2
CL		 5438 end_of_next = next->output_offset + next->size;
5439 if (end_of_next - stub_group_start >= stub_group_size)
5440 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5441 break;
e780aef2 5442 /* Add NEXT to the stub group. */
07d72278
DJ		 5443 head = next;
5444 next = NEXT_SEC (head);
5445 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5446 }
5447 }
07d72278 5448 head = next;
906e58ca
NC		 5449 }
5450 }
07d72278 5451 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5452
5453 free (htab->input_list);
5454#undef PREV_SEC
07d72278 5455#undef NEXT_SEC
906e58ca
NC		 5456}
5457
48229727
JB		 5458/* Comparison function for sorting/searching relocations relating to Cortex-A8
5459 erratum fix. */
5460
5461static int
5462a8_reloc_compare (const void *a, const void *b)
5463{
21d799b5
NC		 5464 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5465 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5466
5467 if (ra->from < rb->from)
5468 return -1;
5469 else if (ra->from > rb->from)
5470 return 1;
5471 else
5472 return 0;
5473}
5474
5475static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5476 const char *, char **);
5477
5478/* Helper function to scan code for sequences which might trigger the Cortex-A8
5479 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5480 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5481 otherwise. */
5482
81694485
NC		 5483static bfd_boolean
5484cortex_a8_erratum_scan (bfd *input_bfd,
5485 struct bfd_link_info *info,
48229727
JB		 5486 struct a8_erratum_fix **a8_fixes_p,
5487 unsigned int *num_a8_fixes_p,
5488 unsigned int *a8_fix_table_size_p,
5489 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5490 unsigned int num_a8_relocs,
5491 unsigned prev_num_a8_fixes,
5492 bfd_boolean *stub_changed_p)
48229727
JB		 5493{
5494 asection *section;
5495 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5496 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5497 unsigned int num_a8_fixes = *num_a8_fixes_p;
5498 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5499
4dfe6ac6
NC		 5500 if (htab == NULL)
5501 return FALSE;
5502
48229727
JB		 5503 for (section = input_bfd->sections;
5504 section != NULL;
5505 section = section->next)
5506 {
5507 bfd_byte *contents = NULL;
5508 struct _arm_elf_section_data *sec_data;
5509 unsigned int span;
5510 bfd_vma base_vma;
5511
5512 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5513 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5514 || (section->flags & SEC_EXCLUDE) != 0
5515 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5516 || (section->output_section == bfd_abs_section_ptr))
5517 continue;
48229727
JB		 5518
5519 base_vma = section->output_section->vma + section->output_offset;
5520
5521 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5522 contents = elf_section_data (section)->this_hdr.contents;
48229727 5523 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5524 return TRUE;
48229727
JB		 5525
5526 sec_data = elf32_arm_section_data (section);
5527
5528 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5529 {
5530 unsigned int span_start = sec_data->map[span].vma;
5531 unsigned int span_end = (span == sec_data->mapcount - 1)
5532 ? section->size : sec_data->map[span + 1].vma;
5533 unsigned int i;
5534 char span_type = sec_data->map[span].type;
5535 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5536
5537 if (span_type != 't')
5538 continue;
5539
5540 /* Span is entirely within a single 4KB region: skip scanning. */
5541 if (((base_vma + span_start) & ~0xfff)
48229727 5542 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5543 continue;
5544
5545 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5546
5547 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5548 * The branch target is in the same 4KB region as the
5549 first half of the branch.
5550 * The instruction before the branch is a 32-bit
5551 length non-branch instruction. */
5552 for (i = span_start; i < span_end;)
5553 {
5554 unsigned int insn = bfd_getl16 (&contents[i]);
5555 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5556 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5557
99059e56
RM		 5558 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5559 insn_32bit = TRUE;
48229727
JB		 5560
5561 if (insn_32bit)
99059e56
RM		 5562 {
5563 /* Load the rest of the insn (in manual-friendly order). */
5564 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5565
5566 /* Encoding T4: B<c>.W. */
5567 is_b = (insn & 0xf800d000) == 0xf0009000;
5568 /* Encoding T1: BL<c>.W. */
5569 is_bl = (insn & 0xf800d000) == 0xf000d000;
5570 /* Encoding T2: BLX<c>.W. */
5571 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5572 /* Encoding T3: B<c>.W (not permitted in IT block). */
5573 is_bcc = (insn & 0xf800d000) == 0xf0008000
5574 && (insn & 0x07f00000) != 0x03800000;
5575 }
5576
5577 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5578
99059e56 5579 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5580 && insn_32bit
5581 && is_32bit_branch
5582 && last_was_32bit
5583 && ! last_was_branch)
99059e56
RM		 5584 {
5585 bfd_signed_vma offset = 0;
5586 bfd_boolean force_target_arm = FALSE;
48229727 5587 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5588 bfd_vma target;
5589 enum elf32_arm_stub_type stub_type = arm_stub_none;
5590 struct a8_erratum_reloc key, *found;
5591 bfd_boolean use_plt = FALSE;
48229727 5592
99059e56
RM		 5593 key.from = base_vma + i;
5594 found = (struct a8_erratum_reloc *)
5595 bsearch (&key, a8_relocs, num_a8_relocs,
5596 sizeof (struct a8_erratum_reloc),
5597 &a8_reloc_compare);
48229727
JB		 5598
5599 if (found)
5600 {
5601 char *error_message = NULL;
5602 struct elf_link_hash_entry *entry;
5603
5604 /* We don't care about the error returned from this
99059e56 5605 function, only if there is glue or not. */
48229727
JB		 5606 entry = find_thumb_glue (info, found->sym_name,
5607 &error_message);
5608
5609 if (entry)
5610 found->non_a8_stub = TRUE;
5611
92750f34 5612 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5613 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5614 && found->hash->root.plt.offset != (bfd_vma) -1)
5615 use_plt = TRUE;
5616
5617 if (found->r_type == R_ARM_THM_CALL)
5618 {
35fc36a8
RS		 5619 if (found->branch_type == ST_BRANCH_TO_ARM
5620 || use_plt)
92750f34
DJ		 5621 force_target_arm = TRUE;
5622 else
5623 force_target_thumb = TRUE;
5624 }
48229727
JB		 5625 }
5626
99059e56 5627 /* Check if we have an offending branch instruction. */
48229727
JB		 5628
5629 if (found && found->non_a8_stub)
5630 /* We've already made a stub for this instruction, e.g.
5631 it's a long branch or a Thumb->ARM stub. Assume that
5632 stub will suffice to work around the A8 erratum (see
5633 setting of always_after_branch above). */
5634 ;
99059e56
RM		 5635 else if (is_bcc)
5636 {
5637 offset = (insn & 0x7ff) << 1;
5638 offset |= (insn & 0x3f0000) >> 4;
5639 offset |= (insn & 0x2000) ? 0x40000 : 0;
5640 offset |= (insn & 0x800) ? 0x80000 : 0;
5641 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5642 if (offset & 0x100000)
5643 offset |= ~ ((bfd_signed_vma) 0xfffff);
5644 stub_type = arm_stub_a8_veneer_b_cond;
5645 }
5646 else if (is_b || is_bl || is_blx)
5647 {
5648 int s = (insn & 0x4000000) != 0;
5649 int j1 = (insn & 0x2000) != 0;
5650 int j2 = (insn & 0x800) != 0;
5651 int i1 = !(j1 ^ s);
5652 int i2 = !(j2 ^ s);
5653
5654 offset = (insn & 0x7ff) << 1;
5655 offset |= (insn & 0x3ff0000) >> 4;
5656 offset |= i2 << 22;
5657 offset |= i1 << 23;
5658 offset |= s << 24;
5659 if (offset & 0x1000000)
5660 offset |= ~ ((bfd_signed_vma) 0xffffff);
5661
5662 if (is_blx)
5663 offset &= ~ ((bfd_signed_vma) 3);
5664
5665 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5666 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5667 }
5668
5669 if (stub_type != arm_stub_none)
5670 {
5671 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5672
5673 /* The original instruction is a BL, but the target is
99059e56 5674 an ARM instruction. If we were not making a stub,
48229727
JB		 5675 the BL would have been converted to a BLX. Use the
5676 BLX stub instead in that case. */
5677 if (htab->use_blx && force_target_arm
5678 && stub_type == arm_stub_a8_veneer_bl)
5679 {
5680 stub_type = arm_stub_a8_veneer_blx;
5681 is_blx = TRUE;
5682 is_bl = FALSE;
5683 }
5684 /* Conversely, if the original instruction was
5685 BLX but the target is Thumb mode, use the BL
5686 stub. */
5687 else if (force_target_thumb
5688 && stub_type == arm_stub_a8_veneer_blx)
5689 {
5690 stub_type = arm_stub_a8_veneer_bl;
5691 is_blx = FALSE;
5692 is_bl = TRUE;
5693 }
5694
99059e56
RM		 5695 if (is_blx)
5696 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5697
99059e56
RM		 5698 /* If we found a relocation, use the proper destination,
5699 not the offset in the (unrelocated) instruction.
48229727
JB		 5700 Note this is always done if we switched the stub type
5701 above. */
99059e56
RM		 5702 if (found)
5703 offset =
81694485 5704 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5705
99059e56
RM		 5706 /* If the stub will use a Thumb-mode branch to a
5707 PLT target, redirect it to the preceding Thumb
5708 entry point. */
5709 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5710 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5711
99059e56 5712 target = pc_for_insn + offset;
48229727 5713
99059e56
RM		 5714 /* The BLX stub is ARM-mode code. Adjust the offset to
5715 take the different PC value (+8 instead of +4) into
48229727 5716 account. */
99059e56
RM		 5717 if (stub_type == arm_stub_a8_veneer_blx)
5718 offset += 4;
5719
5720 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5721 {
5722 char *stub_name = NULL;
5723
5724 if (num_a8_fixes == a8_fix_table_size)
5725 {
5726 a8_fix_table_size *= 2;
5727 a8_fixes = (struct a8_erratum_fix *)
5728 bfd_realloc (a8_fixes,
5729 sizeof (struct a8_erratum_fix)
5730 * a8_fix_table_size);
5731 }
48229727 5732
eb7c4339
NS		 5733 if (num_a8_fixes < prev_num_a8_fixes)
5734 {
5735 /* If we're doing a subsequent scan,
5736 check if we've found the same fix as
5737 before, and try and reuse the stub
5738 name. */
5739 stub_name = a8_fixes[num_a8_fixes].stub_name;
5740 if ((a8_fixes[num_a8_fixes].section != section)
5741 || (a8_fixes[num_a8_fixes].offset != i))
5742 {
5743 free (stub_name);
5744 stub_name = NULL;
5745 *stub_changed_p = TRUE;
5746 }
5747 }
5748
5749 if (!stub_name)
5750 {
21d799b5 5751 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5752 if (stub_name != NULL)
5753 sprintf (stub_name, "%x:%x", section->id, i);
5754 }
48229727 5755
99059e56
RM		 5756 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5757 a8_fixes[num_a8_fixes].section = section;
5758 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5759 a8_fixes[num_a8_fixes].target_offset =
5760 target - base_vma;
99059e56
RM		 5761 a8_fixes[num_a8_fixes].orig_insn = insn;
5762 a8_fixes[num_a8_fixes].stub_name = stub_name;
5763 a8_fixes[num_a8_fixes].stub_type = stub_type;
5764 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5765 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5766
99059e56
RM		 5767 num_a8_fixes++;
5768 }
5769 }
5770 }
48229727 5771
99059e56
RM		 5772 i += insn_32bit ? 4 : 2;
5773 last_was_32bit = insn_32bit;
48229727 5774 last_was_branch = is_32bit_branch;
99059e56
RM		 5775 }
5776 }
48229727
JB		 5777
5778 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5779 free (contents);
48229727 5780 }
fe33d2fa 5781
48229727
JB		 5782 *a8_fixes_p = a8_fixes;
5783 *num_a8_fixes_p = num_a8_fixes;
5784 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5785
81694485 5786 return FALSE;
48229727
JB		 5787}
5788
b715f643
TP		 5789/* Create or update a stub entry depending on whether the stub can already be
5790 found in HTAB. The stub is identified by:
5791 - its type STUB_TYPE
5792 - its source branch (note that several can share the same stub) whose
5793 section and relocation (if any) are given by SECTION and IRELA
5794 respectively
5795 - its target symbol whose input section, hash, name, value and branch type
5796 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5797 respectively
5798
5799 If found, the value of the stub's target symbol is updated from SYM_VALUE
5800 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5801 TRUE and the stub entry is initialized.
5802
0955507f
TP		 5803 Returns the stub that was created or updated, or NULL if an error
5804 occurred. */
b715f643 5805
0955507f 5806static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5807elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5808 enum elf32_arm_stub_type stub_type, asection *section,
5809 Elf_Internal_Rela *irela, asection *sym_sec,
5810 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5811 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5812 bfd_boolean *new_stub)
5813{
5814 const asection *id_sec;
5815 char *stub_name;
5816 struct elf32_arm_stub_hash_entry *stub_entry;
5817 unsigned int r_type;
4f4faa4d 5818 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5819
5820 BFD_ASSERT (stub_type != arm_stub_none);
5821 *new_stub = FALSE;
5822
4f4faa4d
TP		 5823 if (sym_claimed)
5824 stub_name = sym_name;
5825 else
5826 {
5827 BFD_ASSERT (irela);
5828 BFD_ASSERT (section);
c2abbbeb 5829 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5830
4f4faa4d
TP		 5831 /* Support for grouping stub sections. */
5832 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5833
4f4faa4d
TP		 5834 /* Get the name of this stub. */
5835 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5836 stub_type);
5837 if (!stub_name)
0955507f 5838 return NULL;
4f4faa4d 5839 }
b715f643
TP		 5840
5841 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5842 FALSE);
5843 /* The proper stub has already been created, just update its value. */
5844 if (stub_entry != NULL)
5845 {
4f4faa4d
TP		 5846 if (!sym_claimed)
5847 free (stub_name);
b715f643 5848 stub_entry->target_value = sym_value;
0955507f 5849 return stub_entry;
b715f643
TP		 5850 }
5851
daa4adae 5852 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5853 if (stub_entry == NULL)
5854 {
4f4faa4d
TP		 5855 if (!sym_claimed)
5856 free (stub_name);
0955507f 5857 return NULL;
b715f643
TP		 5858 }
5859
5860 stub_entry->target_value = sym_value;
5861 stub_entry->target_section = sym_sec;
5862 stub_entry->stub_type = stub_type;
5863 stub_entry->h = hash;
5864 stub_entry->branch_type = branch_type;
5865
4f4faa4d
TP		 5866 if (sym_claimed)
5867 stub_entry->output_name = sym_name;
5868 else
b715f643 5869 {
4f4faa4d
TP		 5870 if (sym_name == NULL)
5871 sym_name = "unnamed";
5872 stub_entry->output_name = (char *)
5873 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5874 + strlen (sym_name));
5875 if (stub_entry->output_name == NULL)
5876 {
5877 free (stub_name);
0955507f 5878 return NULL;
4f4faa4d 5879 }
b715f643 5880
4f4faa4d
TP		 5881 /* For historical reasons, use the existing names for ARM-to-Thumb and
5882 Thumb-to-ARM stubs. */
5883 r_type = ELF32_R_TYPE (irela->r_info);
5884 if ((r_type == (unsigned int) R_ARM_THM_CALL
5885 || r_type == (unsigned int) R_ARM_THM_JUMP24
5886 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5887 && branch_type == ST_BRANCH_TO_ARM)
5888 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5889 else if ((r_type == (unsigned int) R_ARM_CALL
5890 || r_type == (unsigned int) R_ARM_JUMP24)
5891 && branch_type == ST_BRANCH_TO_THUMB)
5892 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5893 else
5894 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5895 }
b715f643
TP		 5896
5897 *new_stub = TRUE;
0955507f 5898 return stub_entry;
b715f643
TP		 5899}
5900
4ba2ef8f
TP		 5901/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5902 gateway veneer to transition from non secure to secure state and create them
5903 accordingly.
5904
5905 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5906 defines the conditions that govern Secure Gateway veneer creation for a
5907 given symbol <SYM> as follows:
5908 - it has function type
5909 - it has non local binding
5910 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5911 same type, binding and value as <SYM> (called normal symbol).
5912 An entry function can handle secure state transition itself in which case
5913 its special symbol would have a different value from the normal symbol.
5914
5915 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5916 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5917 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5918 created.
4ba2ef8f 5919
0955507f 5920 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5921
5922static bfd_boolean
5923cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5924 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5925 int *cmse_stub_created)
4ba2ef8f
TP		 5926{
5927 const struct elf_backend_data *bed;
5928 Elf_Internal_Shdr *symtab_hdr;
5929 unsigned i, j, sym_count, ext_start;
5930 Elf_Internal_Sym *cmse_sym, *local_syms;
5931 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5932 enum arm_st_branch_type branch_type;
5933 char *sym_name, *lsym_name;
5934 bfd_vma sym_value;
5935 asection *section;
0955507f
TP		 5936 struct elf32_arm_stub_hash_entry *stub_entry;
5937 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5938
5939 bed = get_elf_backend_data (input_bfd);
5940 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5941 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5942 ext_start = symtab_hdr->sh_info;
5943 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5944 && out_attr[Tag_CPU_arch_profile].i == 'M');
5945
5946 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5947 if (local_syms == NULL)
5948 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5949 symtab_hdr->sh_info, 0, NULL, NULL,
5950 NULL);
5951 if (symtab_hdr->sh_info && local_syms == NULL)
5952 return FALSE;
5953
5954 /* Scan symbols. */
5955 for (i = 0; i < sym_count; i++)
5956 {
5957 cmse_invalid = FALSE;
5958
5959 if (i < ext_start)
5960 {
5961 cmse_sym = &local_syms[i];
5962 /* Not a special symbol. */
5963 if (!ARM_GET_SYM_CMSE_SPCL (cmse_sym->st_target_internal))
5964 continue;
5965 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5966 symtab_hdr->sh_link,
5967 cmse_sym->st_name);
5968 /* Special symbol with local binding. */
5969 cmse_invalid = TRUE;
5970 }
5971 else
5972 {
5973 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5974 sym_name = (char *) cmse_hash->root.root.root.string;
5975
5976 /* Not a special symbol. */
5977 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
5978 continue;
5979
5980 /* Special symbol has incorrect binding or type. */
5981 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5982 && cmse_hash->root.root.type != bfd_link_hash_defweak)
5983 || cmse_hash->root.type != STT_FUNC)
5984 cmse_invalid = TRUE;
5985 }
5986
5987 if (!is_v8m)
5988 {
90b6238f
AM		 5989 _bfd_error_handler (_("%pB: special symbol `%s' only allowed for "
5990 "ARMv8-M architecture or later"),
4eca0228 5991 input_bfd, sym_name);
4ba2ef8f
TP		 5992 is_v8m = TRUE; /* Avoid multiple warning. */
5993 ret = FALSE;
5994 }
5995
5996 if (cmse_invalid)
5997 {
90b6238f
AM		 5998 _bfd_error_handler (_("%pB: invalid special symbol `%s'; it must be"
5999 " a global or weak function symbol"),
4eca0228 6000 input_bfd, sym_name);
4ba2ef8f
TP		 6001 ret = FALSE;
6002 if (i < ext_start)
6003 continue;
6004 }
6005
6006 sym_name += strlen (CMSE_PREFIX);
6007 hash = (struct elf32_arm_link_hash_entry *)
6008 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6009
6010 /* No associated normal symbol or it is neither global nor weak. */
6011 if (!hash
6012 || (hash->root.root.type != bfd_link_hash_defined
6013 && hash->root.root.type != bfd_link_hash_defweak)
6014 || hash->root.type != STT_FUNC)
6015 {
6016 /* Initialize here to avoid warning about use of possibly
6017 uninitialized variable. */
6018 j = 0;
6019
6020 if (!hash)
6021 {
6022 /* Searching for a normal symbol with local binding. */
6023 for (; j < ext_start; j++)
6024 {
6025 lsym_name =
6026 bfd_elf_string_from_elf_section (input_bfd,
6027 symtab_hdr->sh_link,
6028 local_syms[j].st_name);
6029 if (!strcmp (sym_name, lsym_name))
6030 break;
6031 }
6032 }
6033
6034 if (hash || j < ext_start)
6035 {
4eca0228 6036 _bfd_error_handler
90b6238f
AM		 6037 (_("%pB: invalid standard symbol `%s'; it must be "
6038 "a global or weak function symbol"),
6039 input_bfd, sym_name);
4ba2ef8f
TP		 6040 }
6041 else
4eca0228 6042 _bfd_error_handler
90b6238f 6043 (_("%pB: absent standard symbol `%s'"), input_bfd, sym_name);
4ba2ef8f
TP		 6044 ret = FALSE;
6045 if (!hash)
6046 continue;
6047 }
6048
6049 sym_value = hash->root.root.u.def.value;
6050 section = hash->root.root.u.def.section;
6051
6052 if (cmse_hash->root.root.u.def.section != section)
6053 {
4eca0228 6054 _bfd_error_handler
90b6238f 6055 (_("%pB: `%s' and its special symbol are in different sections"),
4ba2ef8f
TP		 6056 input_bfd, sym_name);
6057 ret = FALSE;
6058 }
6059 if (cmse_hash->root.root.u.def.value != sym_value)
6060 continue; /* Ignore: could be an entry function starting with SG. */
6061
6062 /* If this section is a link-once section that will be discarded, then
6063 don't create any stubs. */
6064 if (section->output_section == NULL)
6065 {
4eca0228 6066 _bfd_error_handler
90b6238f 6067 (_("%pB: entry function `%s' not output"), input_bfd, sym_name);
4ba2ef8f
TP		 6068 continue;
6069 }
6070
6071 if (hash->root.size == 0)
6072 {
4eca0228 6073 _bfd_error_handler
90b6238f 6074 (_("%pB: entry function `%s' is empty"), input_bfd, sym_name);
4ba2ef8f
TP		 6075 ret = FALSE;
6076 }
6077
6078 if (!ret)
6079 continue;
6080 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 6081 stub_entry
4ba2ef8f
TP		 6082 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6083 NULL, NULL, section, hash, sym_name,
6084 sym_value, branch_type, &new_stub);
6085
0955507f 6086 if (stub_entry == NULL)
4ba2ef8f
TP		 6087 ret = FALSE;
6088 else
6089 {
6090 BFD_ASSERT (new_stub);
0955507f 6091 (*cmse_stub_created)++;
4ba2ef8f
TP		 6092 }
6093 }
6094
6095 if (!symtab_hdr->contents)
6096 free (local_syms);
6097 return ret;
6098}
6099
0955507f
TP		 6100/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6101 code entry function, ie can be called from non secure code without using a
6102 veneer. */
6103
6104static bfd_boolean
6105cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
6106{
42484486 6107 bfd_byte contents[4];
0955507f
TP		 6108 uint32_t first_insn;
6109 asection *section;
6110 file_ptr offset;
6111 bfd *abfd;
6112
6113 /* Defined symbol of function type. */
6114 if (hash->root.root.type != bfd_link_hash_defined
6115 && hash->root.root.type != bfd_link_hash_defweak)
6116 return FALSE;
6117 if (hash->root.type != STT_FUNC)
6118 return FALSE;
6119
6120 /* Read first instruction. */
6121 section = hash->root.root.u.def.section;
6122 abfd = section->owner;
6123 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 6124 if (!bfd_get_section_contents (abfd, section, contents, offset,
6125 sizeof (contents)))
0955507f
TP		 6126 return FALSE;
6127
42484486
TP		 6128 first_insn = bfd_get_32 (abfd, contents);
6129
6130 /* Starts by SG instruction. */
0955507f
TP		 6131 return first_insn == 0xe97fe97f;
6132}
6133
6134/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6135 secure gateway veneers (ie. the veneers was not in the input import library)
6136 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6137
6138static bfd_boolean
6139arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
6140{
6141 struct elf32_arm_stub_hash_entry *stub_entry;
6142 struct bfd_link_info *info;
6143
6144 /* Massage our args to the form they really have. */
6145 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
6146 info = (struct bfd_link_info *) gen_info;
6147
6148 if (info->out_implib_bfd)
6149 return TRUE;
6150
6151 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
6152 return TRUE;
6153
6154 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 6155 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 6156
6157 return TRUE;
6158}
6159
6160/* Set offset of each secure gateway veneers so that its address remain
6161 identical to the one in the input import library referred by
6162 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6163 (present in input import library but absent from the executable being
6164 linked) or if new veneers appeared and there is no output import library
6165 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6166 number of secure gateway veneers found in the input import library.
6167
6168 The function returns whether an error occurred. If no error occurred,
6169 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6170 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6171 veneer observed set for new veneers to be layed out after. */
6172
6173static bfd_boolean
6174set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
6175 struct elf32_arm_link_hash_table *htab,
6176 int *cmse_stub_created)
6177{
6178 long symsize;
6179 char *sym_name;
6180 flagword flags;
6181 long i, symcount;
6182 bfd *in_implib_bfd;
6183 asection *stub_out_sec;
6184 bfd_boolean ret = TRUE;
6185 Elf_Internal_Sym *intsym;
6186 const char *out_sec_name;
6187 bfd_size_type cmse_stub_size;
6188 asymbol **sympp = NULL, *sym;
6189 struct elf32_arm_link_hash_entry *hash;
6190 const insn_sequence *cmse_stub_template;
6191 struct elf32_arm_stub_hash_entry *stub_entry;
6192 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
6193 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
6194 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
6195
6196 /* No input secure gateway import library. */
6197 if (!htab->in_implib_bfd)
6198 return TRUE;
6199
6200 in_implib_bfd = htab->in_implib_bfd;
6201 if (!htab->cmse_implib)
6202 {
871b3ab2 6203 _bfd_error_handler (_("%pB: --in-implib only supported for Secure "
90b6238f 6204 "Gateway import libraries"), in_implib_bfd);
0955507f
TP		 6205 return FALSE;
6206 }
6207
6208 /* Get symbol table size. */
6209 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
6210 if (symsize < 0)
6211 return FALSE;
6212
6213 /* Read in the input secure gateway import library's symbol table. */
6214 sympp = (asymbol **) xmalloc (symsize);
6215 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
6216 if (symcount < 0)
6217 {
6218 ret = FALSE;
6219 goto free_sym_buf;
6220 }
6221
6222 htab->new_cmse_stub_offset = 0;
6223 cmse_stub_size =
6224 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
6225 &cmse_stub_template,
6226 &cmse_stub_template_size);
6227 out_sec_name =
6228 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
6229 stub_out_sec =
6230 bfd_get_section_by_name (htab->obfd, out_sec_name);
6231 if (stub_out_sec != NULL)
6232 cmse_stub_sec_vma = stub_out_sec->vma;
6233
6234 /* Set addresses of veneers mentionned in input secure gateway import
6235 library's symbol table. */
6236 for (i = 0; i < symcount; i++)
6237 {
6238 sym = sympp[i];
6239 flags = sym->flags;
6240 sym_name = (char *) bfd_asymbol_name (sym);
6241 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
6242
6243 if (sym->section != bfd_abs_section_ptr
6244 || !(flags & (BSF_GLOBAL | BSF_WEAK))
6245 || (flags & BSF_FUNCTION) != BSF_FUNCTION
6246 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
6247 != ST_BRANCH_TO_THUMB))
6248 {
90b6238f
AM		 6249 _bfd_error_handler (_("%pB: invalid import library entry: `%s'; "
6250 "symbol should be absolute, global and "
6251 "refer to Thumb functions"),
4eca0228 6252 in_implib_bfd, sym_name);
0955507f
TP		 6253 ret = FALSE;
6254 continue;
6255 }
6256
6257 veneer_value = bfd_asymbol_value (sym);
6258 stub_offset = veneer_value - cmse_stub_sec_vma;
6259 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
6260 FALSE, FALSE);
6261 hash = (struct elf32_arm_link_hash_entry *)
6262 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6263
6264 /* Stub entry should have been created by cmse_scan or the symbol be of
6265 a secure function callable from non secure code. */
6266 if (!stub_entry && !hash)
6267 {
6268 bfd_boolean new_stub;
6269
4eca0228 6270 _bfd_error_handler
90b6238f 6271 (_("entry function `%s' disappeared from secure code"), sym_name);
0955507f
TP		 6272 hash = (struct elf32_arm_link_hash_entry *)
6273 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
6274 stub_entry
6275 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6276 NULL, NULL, bfd_abs_section_ptr, hash,
6277 sym_name, veneer_value,
6278 ST_BRANCH_TO_THUMB, &new_stub);
6279 if (stub_entry == NULL)
6280 ret = FALSE;
6281 else
6282 {
6283 BFD_ASSERT (new_stub);
6284 new_cmse_stubs_created++;
6285 (*cmse_stub_created)++;
6286 }
6287 stub_entry->stub_template_size = stub_entry->stub_size = 0;
6288 stub_entry->stub_offset = stub_offset;
6289 }
6290 /* Symbol found is not callable from non secure code. */
6291 else if (!stub_entry)
6292 {
6293 if (!cmse_entry_fct_p (hash))
6294 {
90b6238f 6295 _bfd_error_handler (_("`%s' refers to a non entry function"),
4eca0228 6296 sym_name);
0955507f
TP		 6297 ret = FALSE;
6298 }
6299 continue;
6300 }
6301 else
6302 {
6303 /* Only stubs for SG veneers should have been created. */
6304 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
6305
6306 /* Check visibility hasn't changed. */
6307 if (!!(flags & BSF_GLOBAL)
6308 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6309 _bfd_error_handler
90b6238f 6310 (_("%pB: visibility of symbol `%s' has changed"), in_implib_bfd,
0955507f
TP		 6311 sym_name);
6312
6313 stub_entry->stub_offset = stub_offset;
6314 }
6315
6316 /* Size should match that of a SG veneer. */
6317 if (intsym->st_size != cmse_stub_size)
6318 {
90b6238f 6319 _bfd_error_handler (_("%pB: incorrect size for symbol `%s'"),
4eca0228 6320 in_implib_bfd, sym_name);
0955507f
TP		 6321 ret = FALSE;
6322 }
6323
6324 /* Previous veneer address is before current SG veneer section. */
6325 if (veneer_value < cmse_stub_sec_vma)
6326 {
6327 /* Avoid offset underflow. */
6328 if (stub_entry)
6329 stub_entry->stub_offset = 0;
6330 stub_offset = 0;
6331 ret = FALSE;
6332 }
6333
6334 /* Complain if stub offset not a multiple of stub size. */
6335 if (stub_offset % cmse_stub_size)
6336 {
4eca0228 6337 _bfd_error_handler
90b6238f
AM		 6338 (_("offset of veneer for entry function `%s' not a multiple of "
6339 "its size"), sym_name);
0955507f
TP		 6340 ret = FALSE;
6341 }
6342
6343 if (!ret)
6344 continue;
6345
6346 new_cmse_stubs_created--;
6347 if (veneer_value < cmse_stub_array_start)
6348 cmse_stub_array_start = veneer_value;
6349 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6350 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6351 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6352 }
6353
6354 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6355 {
6356 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6357 _bfd_error_handler
0955507f
TP		 6358 (_("new entry function(s) introduced but no output import library "
6359 "specified:"));
6360 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6361 }
6362
6363 if (cmse_stub_array_start != cmse_stub_sec_vma)
6364 {
4eca0228 6365 _bfd_error_handler
90b6238f 6366 (_("start address of `%s' is different from previous link"),
0955507f
TP		 6367 out_sec_name);
6368 ret = FALSE;
6369 }
6370
6371free_sym_buf:
6372 free (sympp);
6373 return ret;
6374}
6375
906e58ca
NC		 6376/* Determine and set the size of the stub section for a final link.
6377
6378 The basic idea here is to examine all the relocations looking for
6379 PC-relative calls to a target that is unreachable with a "bl"
6380 instruction. */
6381
6382bfd_boolean
6383elf32_arm_size_stubs (bfd *output_bfd,
6384 bfd *stub_bfd,
6385 struct bfd_link_info *info,
6386 bfd_signed_vma group_size,
7a89b94e 6387 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6388 asection *,
7a89b94e 6389 unsigned int),
906e58ca
NC		 6390 void (*layout_sections_again) (void))
6391{
0955507f 6392 bfd_boolean ret = TRUE;
4ba2ef8f 6393 obj_attribute *out_attr;
0955507f 6394 int cmse_stub_created = 0;
906e58ca 6395 bfd_size_type stub_group_size;
4ba2ef8f 6396 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6397 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6398 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6399 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6400 struct a8_erratum_reloc *a8_relocs = NULL;
6401 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6402
4dfe6ac6
NC		 6403 if (htab == NULL)
6404 return FALSE;
6405
48229727
JB		 6406 if (htab->fix_cortex_a8)
6407 {
21d799b5 6408 a8_fixes = (struct a8_erratum_fix *)
99059e56 6409 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6410 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6411 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6412 }
906e58ca
NC		 6413
6414 /* Propagate mach to stub bfd, because it may not have been
6415 finalized when we created stub_bfd. */
6416 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6417 bfd_get_mach (output_bfd));
6418
6419 /* Stash our params away. */
6420 htab->stub_bfd = stub_bfd;
6421 htab->add_stub_section = add_stub_section;
6422 htab->layout_sections_again = layout_sections_again;
07d72278 6423 stubs_always_after_branch = group_size < 0;
48229727 6424
4ba2ef8f
TP		 6425 out_attr = elf_known_obj_attributes_proc (output_bfd);
6426 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6427
48229727
JB		 6428 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6429 as the first half of a 32-bit branch straddling two 4K pages. This is a
6430 crude way of enforcing that. */
6431 if (htab->fix_cortex_a8)
6432 stubs_always_after_branch = 1;
6433
906e58ca
NC		 6434 if (group_size < 0)
6435 stub_group_size = -group_size;
6436 else
6437 stub_group_size = group_size;
6438
6439 if (stub_group_size == 1)
6440 {
6441 /* Default values. */
6442 /* Thumb branch range is +-4MB has to be used as the default
6443 maximum size (a given section can contain both ARM and Thumb
6444 code, so the worst case has to be taken into account).
6445
6446 This value is 24K less than that, which allows for 2025
6447 12-byte stubs. If we exceed that, then we will fail to link.
6448 The user will have to relink with an explicit group size
6449 option. */
6450 stub_group_size = 4170000;
6451 }
6452
07d72278 6453 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6454
3ae046cc
NS		 6455 /* If we're applying the cortex A8 fix, we need to determine the
6456 program header size now, because we cannot change it later --
6457 that could alter section placements. Notice the A8 erratum fix
6458 ends up requiring the section addresses to remain unchanged
6459 modulo the page size. That's something we cannot represent
6460 inside BFD, and we don't want to force the section alignment to
6461 be the page size. */
6462 if (htab->fix_cortex_a8)
6463 (*htab->layout_sections_again) ();
6464
906e58ca
NC		 6465 while (1)
6466 {
6467 bfd *input_bfd;
6468 unsigned int bfd_indx;
6469 asection *stub_sec;
d7c5bd02 6470 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6471 bfd_boolean stub_changed = FALSE;
6472 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6473
48229727 6474 num_a8_fixes = 0;
906e58ca
NC		 6475 for (input_bfd = info->input_bfds, bfd_indx = 0;
6476 input_bfd != NULL;
c72f2fb2 6477 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6478 {
6479 Elf_Internal_Shdr *symtab_hdr;
6480 asection *section;
6481 Elf_Internal_Sym *local_syms = NULL;
6482
8c246a60
AM		 6483 if (!is_arm_elf (input_bfd)
6484 || (elf_dyn_lib_class (input_bfd) & DYN_AS_NEEDED) != 0)
99059e56 6485 continue;
adbcc655 6486
48229727
JB		 6487 num_a8_relocs = 0;
6488
906e58ca
NC		 6489 /* We'll need the symbol table in a second. */
6490 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6491 if (symtab_hdr->sh_info == 0)
6492 continue;
6493
4ba2ef8f
TP		 6494 /* Limit scan of symbols to object file whose profile is
6495 Microcontroller to not hinder performance in the general case. */
6496 if (m_profile && first_veneer_scan)
6497 {
6498 struct elf_link_hash_entry **sym_hashes;
6499
6500 sym_hashes = elf_sym_hashes (input_bfd);
6501 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6502 &cmse_stub_created))
4ba2ef8f 6503 goto error_ret_free_local;
0955507f
TP		 6504
6505 if (cmse_stub_created != 0)
6506 stub_changed = TRUE;
4ba2ef8f
TP		 6507 }
6508
906e58ca
NC		 6509 /* Walk over each section attached to the input bfd. */
6510 for (section = input_bfd->sections;
6511 section != NULL;
6512 section = section->next)
6513 {
6514 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6515
6516 /* If there aren't any relocs, then there's nothing more
6517 to do. */
6518 if ((section->flags & SEC_RELOC) == 0
6519 || section->reloc_count == 0
6520 || (section->flags & SEC_CODE) == 0)
6521 continue;
6522
6523 /* If this section is a link-once section that will be
6524 discarded, then don't create any stubs. */
6525 if (section->output_section == NULL
6526 || section->output_section->owner != output_bfd)
6527 continue;
6528
6529 /* Get the relocs. */
6530 internal_relocs
6531 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6532 NULL, info->keep_memory);
6533 if (internal_relocs == NULL)
6534 goto error_ret_free_local;
6535
6536 /* Now examine each relocation. */
6537 irela = internal_relocs;
6538 irelaend = irela + section->reloc_count;
6539 for (; irela < irelaend; irela++)
6540 {
6541 unsigned int r_type, r_indx;
906e58ca
NC		 6542 asection *sym_sec;
6543 bfd_vma sym_value;
6544 bfd_vma destination;
6545 struct elf32_arm_link_hash_entry *hash;
7413f23f 6546 const char *sym_name;
34e77a92 6547 unsigned char st_type;
35fc36a8 6548 enum arm_st_branch_type branch_type;
48229727 6549 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6550
6551 r_type = ELF32_R_TYPE (irela->r_info);
6552 r_indx = ELF32_R_SYM (irela->r_info);
6553
6554 if (r_type >= (unsigned int) R_ARM_max)
6555 {
6556 bfd_set_error (bfd_error_bad_value);
6557 error_ret_free_internal:
6558 if (elf_section_data (section)->relocs == NULL)
6559 free (internal_relocs);
15dd01b1
TP		 6560 /* Fall through. */
6561 error_ret_free_local:
6562 if (local_syms != NULL
6563 && (symtab_hdr->contents
6564 != (unsigned char *) local_syms))
6565 free (local_syms);
6566 return FALSE;
906e58ca 6567 }
b38cadfb 6568
0855e32b
NS		 6569 hash = NULL;
6570 if (r_indx >= symtab_hdr->sh_info)
6571 hash = elf32_arm_hash_entry
6572 (elf_sym_hashes (input_bfd)
6573 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6574
0855e32b
NS		 6575 /* Only look for stubs on branch instructions, or
6576 non-relaxed TLSCALL */
906e58ca 6577 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6578 && (r_type != (unsigned int) R_ARM_THM_CALL)
6579 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6580 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6581 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6582 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6583 && (r_type != (unsigned int) R_ARM_PLT32)
6584 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6585 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6586 && r_type == elf32_arm_tls_transition
6587 (info, r_type, &hash->root)
6588 && ((hash ? hash->tls_type
6589 : (elf32_arm_local_got_tls_type
6590 (input_bfd)[r_indx]))
6591 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6592 continue;
6593
6594 /* Now determine the call target, its name, value,
6595 section. */
6596 sym_sec = NULL;
6597 sym_value = 0;
6598 destination = 0;
7413f23f 6599 sym_name = NULL;
b38cadfb 6600
0855e32b
NS		 6601 if (r_type == (unsigned int) R_ARM_TLS_CALL
6602 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6603 {
6604 /* A non-relaxed TLS call. The target is the
6605 plt-resident trampoline and nothing to do
6606 with the symbol. */
6607 BFD_ASSERT (htab->tls_trampoline > 0);
6608 sym_sec = htab->root.splt;
6609 sym_value = htab->tls_trampoline;
6610 hash = 0;
34e77a92 6611 st_type = STT_FUNC;
35fc36a8 6612 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6613 }
6614 else if (!hash)
906e58ca
NC		 6615 {
6616 /* It's a local symbol. */
6617 Elf_Internal_Sym *sym;
906e58ca
NC		 6618
6619 if (local_syms == NULL)
6620 {
6621 local_syms
6622 = (Elf_Internal_Sym *) symtab_hdr->contents;
6623 if (local_syms == NULL)
6624 local_syms
6625 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6626 symtab_hdr->sh_info, 0,
6627 NULL, NULL, NULL);
6628 if (local_syms == NULL)
6629 goto error_ret_free_internal;
6630 }
6631
6632 sym = local_syms + r_indx;
f6d250ce
TS		 6633 if (sym->st_shndx == SHN_UNDEF)
6634 sym_sec = bfd_und_section_ptr;
6635 else if (sym->st_shndx == SHN_ABS)
6636 sym_sec = bfd_abs_section_ptr;
6637 else if (sym->st_shndx == SHN_COMMON)
6638 sym_sec = bfd_com_section_ptr;
6639 else
6640 sym_sec =
6641 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6642
ffcb4889
NS		 6643 if (!sym_sec)
6644 /* This is an undefined symbol. It can never
6a631e86 6645 be resolved. */
ffcb4889 6646 continue;
fe33d2fa 6647
906e58ca
NC		 6648 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6649 sym_value = sym->st_value;
6650 destination = (sym_value + irela->r_addend
6651 + sym_sec->output_offset
6652 + sym_sec->output_section->vma);
34e77a92 6653 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6654 branch_type =
6655 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6656 sym_name
6657 = bfd_elf_string_from_elf_section (input_bfd,
6658 symtab_hdr->sh_link,
6659 sym->st_name);
906e58ca
NC		 6660 }
6661 else
6662 {
6663 /* It's an external symbol. */
906e58ca
NC		 6664 while (hash->root.root.type == bfd_link_hash_indirect
6665 || hash->root.root.type == bfd_link_hash_warning)
6666 hash = ((struct elf32_arm_link_hash_entry *)
6667 hash->root.root.u.i.link);
6668
6669 if (hash->root.root.type == bfd_link_hash_defined
6670 || hash->root.root.type == bfd_link_hash_defweak)
6671 {
6672 sym_sec = hash->root.root.u.def.section;
6673 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6674
6675 struct elf32_arm_link_hash_table *globals =
6676 elf32_arm_hash_table (info);
6677
6678 /* For a destination in a shared library,
6679 use the PLT stub as target address to
6680 decide whether a branch stub is
6681 needed. */
4dfe6ac6 6682 if (globals != NULL
362d30a1 6683 && globals->root.splt != NULL
4dfe6ac6 6684 && hash != NULL
022f8312
CL		 6685 && hash->root.plt.offset != (bfd_vma) -1)
6686 {
362d30a1 6687 sym_sec = globals->root.splt;
022f8312
CL		 6688 sym_value = hash->root.plt.offset;
6689 if (sym_sec->output_section != NULL)
6690 destination = (sym_value
6691 + sym_sec->output_offset
6692 + sym_sec->output_section->vma);
6693 }
6694 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6695 destination = (sym_value + irela->r_addend
6696 + sym_sec->output_offset
6697 + sym_sec->output_section->vma);
6698 }
69c5861e
CL		 6699 else if ((hash->root.root.type == bfd_link_hash_undefined)
6700 || (hash->root.root.type == bfd_link_hash_undefweak))
6701 {
6702 /* For a shared library, use the PLT stub as
6703 target address to decide whether a long
6704 branch stub is needed.
6705 For absolute code, they cannot be handled. */
6706 struct elf32_arm_link_hash_table *globals =
6707 elf32_arm_hash_table (info);
6708
4dfe6ac6 6709 if (globals != NULL
362d30a1 6710 && globals->root.splt != NULL
4dfe6ac6 6711 && hash != NULL
69c5861e
CL		 6712 && hash->root.plt.offset != (bfd_vma) -1)
6713 {
362d30a1 6714 sym_sec = globals->root.splt;
69c5861e
CL		 6715 sym_value = hash->root.plt.offset;
6716 if (sym_sec->output_section != NULL)
6717 destination = (sym_value
6718 + sym_sec->output_offset
6719 + sym_sec->output_section->vma);
6720 }
6721 else
6722 continue;
6723 }
906e58ca
NC		 6724 else
6725 {
6726 bfd_set_error (bfd_error_bad_value);
6727 goto error_ret_free_internal;
6728 }
34e77a92 6729 st_type = hash->root.type;
39d911fc
TP		 6730 branch_type =
6731 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6732 sym_name = hash->root.root.root.string;
906e58ca
NC		 6733 }
6734
48229727 6735 do
7413f23f 6736 {
b715f643 6737 bfd_boolean new_stub;
0955507f 6738 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6739
48229727
JB		 6740 /* Determine what (if any) linker stub is needed. */
6741 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6742 st_type, &branch_type,
6743 hash, destination, sym_sec,
48229727
JB		 6744 input_bfd, sym_name);
6745 if (stub_type == arm_stub_none)
6746 break;
6747
48229727
JB		 6748 /* We've either created a stub for this reloc already,
6749 or we are about to. */
0955507f 6750 stub_entry =
b715f643
TP		 6751 elf32_arm_create_stub (htab, stub_type, section, irela,
6752 sym_sec, hash,
6753 (char *) sym_name, sym_value,
6754 branch_type, &new_stub);
7413f23f 6755
0955507f 6756 created_stub = stub_entry != NULL;
b715f643
TP		 6757 if (!created_stub)
6758 goto error_ret_free_internal;
6759 else if (!new_stub)
6760 break;
99059e56 6761 else
b715f643 6762 stub_changed = TRUE;
99059e56
RM		 6763 }
6764 while (0);
6765
6766 /* Look for relocations which might trigger Cortex-A8
6767 erratum. */
6768 if (htab->fix_cortex_a8
6769 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6770 || r_type == (unsigned int) R_ARM_THM_JUMP19
6771 || r_type == (unsigned int) R_ARM_THM_CALL
6772 || r_type == (unsigned int) R_ARM_THM_XPC22))
6773 {
6774 bfd_vma from = section->output_section->vma
6775 + section->output_offset
6776 + irela->r_offset;
6777
6778 if ((from & 0xfff) == 0xffe)
6779 {
6780 /* Found a candidate. Note we haven't checked the
6781 destination is within 4K here: if we do so (and
6782 don't create an entry in a8_relocs) we can't tell
6783 that a branch should have been relocated when
6784 scanning later. */
6785 if (num_a8_relocs == a8_reloc_table_size)
6786 {
6787 a8_reloc_table_size *= 2;
6788 a8_relocs = (struct a8_erratum_reloc *)
6789 bfd_realloc (a8_relocs,
6790 sizeof (struct a8_erratum_reloc)
6791 * a8_reloc_table_size);
6792 }
6793
6794 a8_relocs[num_a8_relocs].from = from;
6795 a8_relocs[num_a8_relocs].destination = destination;
6796 a8_relocs[num_a8_relocs].r_type = r_type;
6797 a8_relocs[num_a8_relocs].branch_type = branch_type;
6798 a8_relocs[num_a8_relocs].sym_name = sym_name;
6799 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6800 a8_relocs[num_a8_relocs].hash = hash;
6801
6802 num_a8_relocs++;
6803 }
6804 }
906e58ca
NC		 6805 }
6806
99059e56
RM		 6807 /* We're done with the internal relocs, free them. */
6808 if (elf_section_data (section)->relocs == NULL)
6809 free (internal_relocs);
6810 }
48229727 6811
99059e56 6812 if (htab->fix_cortex_a8)
48229727 6813 {
99059e56
RM		 6814 /* Sort relocs which might apply to Cortex-A8 erratum. */
6815 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6816 sizeof (struct a8_erratum_reloc),
99059e56 6817 &a8_reloc_compare);
48229727 6818
99059e56
RM		 6819 /* Scan for branches which might trigger Cortex-A8 erratum. */
6820 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6821 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6822 a8_relocs, num_a8_relocs,
6823 prev_num_a8_fixes, &stub_changed)
6824 != 0)
48229727 6825 goto error_ret_free_local;
5e681ec4 6826 }
7f991970
AM		 6827
6828 if (local_syms != NULL
6829 && symtab_hdr->contents != (unsigned char *) local_syms)
6830 {
6831 if (!info->keep_memory)
6832 free (local_syms);
6833 else
6834 symtab_hdr->contents = (unsigned char *) local_syms;
6835 }
5e681ec4
PB		 6836 }
6837
0955507f
TP		 6838 if (first_veneer_scan
6839 && !set_cmse_veneer_addr_from_implib (info, htab,
6840 &cmse_stub_created))
6841 ret = FALSE;
6842
eb7c4339 6843 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6844 stub_changed = TRUE;
48229727 6845
906e58ca
NC		 6846 if (!stub_changed)
6847 break;
5e681ec4 6848
906e58ca
NC		 6849 /* OK, we've added some stubs. Find out the new size of the
6850 stub sections. */
6851 for (stub_sec = htab->stub_bfd->sections;
6852 stub_sec != NULL;
6853 stub_sec = stub_sec->next)
3e6b1042
DJ		 6854 {
6855 /* Ignore non-stub sections. */
6856 if (!strstr (stub_sec->name, STUB_SUFFIX))
6857 continue;
6858
6859 stub_sec->size = 0;
6860 }
b34b2d70 6861
0955507f
TP		 6862 /* Add new SG veneers after those already in the input import
6863 library. */
6864 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6865 stub_type++)
6866 {
6867 bfd_vma *start_offset_p;
6868 asection **stub_sec_p;
6869
6870 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6871 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6872 if (start_offset_p == NULL)
6873 continue;
6874
6875 BFD_ASSERT (stub_sec_p != NULL);
6876 if (*stub_sec_p != NULL)
6877 (*stub_sec_p)->size = *start_offset_p;
6878 }
6879
d7c5bd02 6880 /* Compute stub section size, considering padding. */
906e58ca 6881 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6882 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6883 stub_type++)
6884 {
6885 int size, padding;
6886 asection **stub_sec_p;
6887
6888 padding = arm_dedicated_stub_section_padding (stub_type);
6889 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6890 /* Skip if no stub input section or no stub section padding
6891 required. */
6892 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6893 continue;
6894 /* Stub section padding required but no dedicated section. */
6895 BFD_ASSERT (stub_sec_p);
6896
6897 size = (*stub_sec_p)->size;
6898 size = (size + padding - 1) & ~(padding - 1);
6899 (*stub_sec_p)->size = size;
6900 }
906e58ca 6901
48229727
JB		 6902 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6903 if (htab->fix_cortex_a8)
99059e56
RM		 6904 for (i = 0; i < num_a8_fixes; i++)
6905 {
48229727 6906 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6907 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6908
6909 if (stub_sec == NULL)
7f991970 6910 return FALSE;
48229727 6911
99059e56
RM		 6912 stub_sec->size
6913 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6914 NULL);
6915 }
48229727
JB		 6916
6917
906e58ca
NC		 6918 /* Ask the linker to do its stuff. */
6919 (*htab->layout_sections_again) ();
4ba2ef8f 6920 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6921 }
6922
48229727
JB		 6923 /* Add stubs for Cortex-A8 erratum fixes now. */
6924 if (htab->fix_cortex_a8)
6925 {
6926 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6927 {
6928 struct elf32_arm_stub_hash_entry *stub_entry;
6929 char *stub_name = a8_fixes[i].stub_name;
6930 asection *section = a8_fixes[i].section;
6931 unsigned int section_id = a8_fixes[i].section->id;
6932 asection *link_sec = htab->stub_group[section_id].link_sec;
6933 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6934 const insn_sequence *template_sequence;
6935 int template_size, size = 0;
6936
6937 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6938 TRUE, FALSE);
6939 if (stub_entry == NULL)
6940 {
871b3ab2 6941 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 6942 section->owner, stub_name);
99059e56
RM		 6943 return FALSE;
6944 }
6945
6946 stub_entry->stub_sec = stub_sec;
0955507f 6947 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6948 stub_entry->id_sec = link_sec;
6949 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6950 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6951 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6952 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6953 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6954 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6955
99059e56
RM		 6956 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6957 &template_sequence,
6958 &template_size);
48229727 6959
99059e56
RM		 6960 stub_entry->stub_size = size;
6961 stub_entry->stub_template = template_sequence;
6962 stub_entry->stub_template_size = template_size;
6963 }
48229727
JB		 6964
6965 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6966 elf32_arm_write_section(). */
48229727
JB		 6967 htab->a8_erratum_fixes = a8_fixes;
6968 htab->num_a8_erratum_fixes = num_a8_fixes;
6969 }
6970 else
6971 {
6972 htab->a8_erratum_fixes = NULL;
6973 htab->num_a8_erratum_fixes = 0;
6974 }
0955507f 6975 return ret;
5e681ec4
PB		 6976}
6977
906e58ca
NC		 6978/* Build all the stubs associated with the current output file. The
6979 stubs are kept in a hash table attached to the main linker hash
6980 table. We also set up the .plt entries for statically linked PIC
6981 functions here. This function is called via arm_elf_finish in the
6982 linker. */
252b5132 6983
906e58ca
NC		 6984bfd_boolean
6985elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 6986{
906e58ca
NC		 6987 asection *stub_sec;
6988 struct bfd_hash_table *table;
0955507f 6989 enum elf32_arm_stub_type stub_type;
906e58ca 6990 struct elf32_arm_link_hash_table *htab;
252b5132 6991
906e58ca 6992 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 6993 if (htab == NULL)
6994 return FALSE;
252b5132 6995
906e58ca
NC		 6996 for (stub_sec = htab->stub_bfd->sections;
6997 stub_sec != NULL;
6998 stub_sec = stub_sec->next)
252b5132 6999 {
906e58ca
NC		 7000 bfd_size_type size;
7001
8029a119 7002 /* Ignore non-stub sections. */
906e58ca
NC		 7003 if (!strstr (stub_sec->name, STUB_SUFFIX))
7004 continue;
7005
d7c5bd02 7006 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 7007 must at least be done for stub section requiring padding and for SG
7008 veneers to ensure that a non secure code branching to a removed SG
7009 veneer causes an error. */
906e58ca 7010 size = stub_sec->size;
21d799b5 7011 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 7012 if (stub_sec->contents == NULL && size != 0)
7013 return FALSE;
0955507f 7014
906e58ca 7015 stub_sec->size = 0;
252b5132
RH		 7016 }
7017
0955507f
TP		 7018 /* Add new SG veneers after those already in the input import library. */
7019 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7020 {
7021 bfd_vma *start_offset_p;
7022 asection **stub_sec_p;
7023
7024 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
7025 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
7026 if (start_offset_p == NULL)
7027 continue;
7028
7029 BFD_ASSERT (stub_sec_p != NULL);
7030 if (*stub_sec_p != NULL)
7031 (*stub_sec_p)->size = *start_offset_p;
7032 }
7033
906e58ca
NC		 7034 /* Build the stubs as directed by the stub hash table. */
7035 table = &htab->stub_hash_table;
7036 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 7037 if (htab->fix_cortex_a8)
7038 {
7039 /* Place the cortex a8 stubs last. */
7040 htab->fix_cortex_a8 = -1;
7041 bfd_hash_traverse (table, arm_build_one_stub, info);
7042 }
252b5132 7043
906e58ca 7044 return TRUE;
252b5132
RH		 7045}
7046
9b485d32
NC		 7047/* Locate the Thumb encoded calling stub for NAME. */
7048
252b5132 7049static struct elf_link_hash_entry *
57e8b36a
NC		 7050find_thumb_glue (struct bfd_link_info *link_info,
7051 const char *name,
f2a9dd69 7052 char **error_message)
252b5132
RH		 7053{
7054 char *tmp_name;
7055 struct elf_link_hash_entry *hash;
7056 struct elf32_arm_link_hash_table *hash_table;
7057
7058 /* We need a pointer to the armelf specific hash table. */
7059 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7060 if (hash_table == NULL)
7061 return NULL;
252b5132 7062
21d799b5 7063 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7064 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7065
7066 BFD_ASSERT (tmp_name);
7067
7068 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
7069
7070 hash = elf_link_hash_lookup
b34976b6 7071 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7072
b1657152 7073 if (hash == NULL
90b6238f
AM		 7074 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7075 "Thumb", tmp_name, name) == -1)
b1657152 7076 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7077
7078 free (tmp_name);
7079
7080 return hash;
7081}
7082
9b485d32
NC		 7083/* Locate the ARM encoded calling stub for NAME. */
7084
252b5132 7085static struct elf_link_hash_entry *
57e8b36a
NC		 7086find_arm_glue (struct bfd_link_info *link_info,
7087 const char *name,
f2a9dd69 7088 char **error_message)
252b5132
RH		 7089{
7090 char *tmp_name;
7091 struct elf_link_hash_entry *myh;
7092 struct elf32_arm_link_hash_table *hash_table;
7093
7094 /* We need a pointer to the elfarm specific hash table. */
7095 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7096 if (hash_table == NULL)
7097 return NULL;
252b5132 7098
21d799b5 7099 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7100 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7101
7102 BFD_ASSERT (tmp_name);
7103
7104 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7105
7106 myh = elf_link_hash_lookup
b34976b6 7107 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7108
b1657152 7109 if (myh == NULL
90b6238f
AM		 7110 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7111 "ARM", tmp_name, name) == -1)
b1657152 7112 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7113
7114 free (tmp_name);
7115
7116 return myh;
7117}
7118
8f6277f5 7119/* ARM->Thumb glue (static images):
252b5132
RH		 7120
7121 .arm
7122 __func_from_arm:
7123 ldr r12, __func_addr
7124 bx r12
7125 __func_addr:
906e58ca 7126 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 7127
26079076
PB		 7128 (v5t static images)
7129 .arm
7130 __func_from_arm:
7131 ldr pc, __func_addr
7132 __func_addr:
906e58ca 7133 .word func @ behave as if you saw a ARM_32 reloc.
26079076 7134
8f6277f5
PB		 7135 (relocatable images)
7136 .arm
7137 __func_from_arm:
7138 ldr r12, __func_offset
7139 add r12, r12, pc
7140 bx r12
7141 __func_offset:
8029a119 7142 .word func - . */
8f6277f5
PB		 7143
7144#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 7145static const insn32 a2t1_ldr_insn = 0xe59fc000;
7146static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
7147static const insn32 a2t3_func_addr_insn = 0x00000001;
7148
26079076
PB		 7149#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7150static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
7151static const insn32 a2t2v5_func_addr_insn = 0x00000001;
7152
8f6277f5
PB		 7153#define ARM2THUMB_PIC_GLUE_SIZE 16
7154static const insn32 a2t1p_ldr_insn = 0xe59fc004;
7155static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
7156static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
7157
07d6d2b8 7158/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 7159
07d6d2b8
AM		 7160 .thumb .thumb
7161 .align 2 .align 2
7162 __func_from_thumb: __func_from_thumb:
7163 bx pc push {r6, lr}
7164 nop ldr r6, __func_addr
7165 .arm mov lr, pc
7166 b func bx r6
99059e56
RM		 7167 .arm
7168 ;; back_to_thumb
7169 ldmia r13! {r6, lr}
7170 bx lr
7171 __func_addr:
07d6d2b8 7172 .word func */
252b5132
RH		 7173
7174#define THUMB2ARM_GLUE_SIZE 8
7175static const insn16 t2a1_bx_pc_insn = 0x4778;
7176static const insn16 t2a2_noop_insn = 0x46c0;
7177static const insn32 t2a3_b_insn = 0xea000000;
7178
c7b8f16e 7179#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 7180#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7181#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 7182
845b51d6
PB		 7183#define ARM_BX_VENEER_SIZE 12
7184static const insn32 armbx1_tst_insn = 0xe3100001;
7185static const insn32 armbx2_moveq_insn = 0x01a0f000;
7186static const insn32 armbx3_bx_insn = 0xe12fff10;
7187
7e392df6 7188#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 7189static void
7190arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 7191{
7192 asection * s;
8029a119 7193 bfd_byte * contents;
252b5132 7194
8029a119 7195 if (size == 0)
3e6b1042
DJ		 7196 {
7197 /* Do not include empty glue sections in the output. */
7198 if (abfd != NULL)
7199 {
3d4d4302 7200 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 7201 if (s != NULL)
7202 s->flags |= SEC_EXCLUDE;
7203 }
7204 return;
7205 }
252b5132 7206
8029a119 7207 BFD_ASSERT (abfd != NULL);
252b5132 7208
3d4d4302 7209 s = bfd_get_linker_section (abfd, name);
8029a119 7210 BFD_ASSERT (s != NULL);
252b5132 7211
21d799b5 7212 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 7213
8029a119
NC		 7214 BFD_ASSERT (s->size == size);
7215 s->contents = contents;
7216}
906e58ca 7217
8029a119
NC		 7218bfd_boolean
7219bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
7220{
7221 struct elf32_arm_link_hash_table * globals;
906e58ca 7222
8029a119
NC		 7223 globals = elf32_arm_hash_table (info);
7224 BFD_ASSERT (globals != NULL);
906e58ca 7225
8029a119
NC		 7226 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7227 globals->arm_glue_size,
7228 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 7229
8029a119
NC		 7230 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7231 globals->thumb_glue_size,
7232 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 7233
8029a119
NC		 7234 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7235 globals->vfp11_erratum_glue_size,
7236 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 7237
a504d23a
LA		 7238 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7239 globals->stm32l4xx_erratum_glue_size,
7240 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7241
8029a119
NC		 7242 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7243 globals->bx_glue_size,
845b51d6
PB		 7244 ARM_BX_GLUE_SECTION_NAME);
7245
b34976b6 7246 return TRUE;
252b5132
RH		 7247}
7248
a4fd1a8e 7249/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 7250 returns the symbol identifying the stub. */
7251
a4fd1a8e 7252static struct elf_link_hash_entry *
57e8b36a
NC		 7253record_arm_to_thumb_glue (struct bfd_link_info * link_info,
7254 struct elf_link_hash_entry * h)
252b5132
RH		 7255{
7256 const char * name = h->root.root.string;
63b0f745 7257 asection * s;
252b5132
RH		 7258 char * tmp_name;
7259 struct elf_link_hash_entry * myh;
14a793b2 7260 struct bfd_link_hash_entry * bh;
252b5132 7261 struct elf32_arm_link_hash_table * globals;
dc810e39 7262 bfd_vma val;
2f475487 7263 bfd_size_type size;
252b5132
RH		 7264
7265 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 7266 BFD_ASSERT (globals != NULL);
7267 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7268
3d4d4302 7269 s = bfd_get_linker_section
252b5132
RH		 7270 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
7271
252b5132
RH		 7272 BFD_ASSERT (s != NULL);
7273
21d799b5 7274 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7275 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7276
7277 BFD_ASSERT (tmp_name);
7278
7279 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7280
7281 myh = elf_link_hash_lookup
b34976b6 7282 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 7283
7284 if (myh != NULL)
7285 {
9b485d32 7286 /* We've already seen this guy. */
252b5132 7287 free (tmp_name);
a4fd1a8e 7288 return myh;
252b5132
RH		 7289 }
7290
57e8b36a
NC		 7291 /* The only trick here is using hash_table->arm_glue_size as the value.
7292 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 7293 putting it. The +1 on the value marks that the stub has not been
7294 output yet - not that it is a Thumb function. */
14a793b2 7295 bh = NULL;
dc810e39
AM		 7296 val = globals->arm_glue_size + 1;
7297 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
7298 tmp_name, BSF_GLOBAL, s, val,
b34976b6 7299 NULL, TRUE, FALSE, &bh);
252b5132 7300
b7693d02
DJ		 7301 myh = (struct elf_link_hash_entry *) bh;
7302 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7303 myh->forced_local = 1;
7304
252b5132
RH		 7305 free (tmp_name);
7306
0e1862bb
L		 7307 if (bfd_link_pic (link_info)
7308 || globals->root.is_relocatable_executable
27e55c4d 7309 || globals->pic_veneer)
2f475487 7310 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7311 else if (globals->use_blx)
7312 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7313 else
2f475487
AM		 7314 size = ARM2THUMB_STATIC_GLUE_SIZE;
7315
7316 s->size += size;
7317 globals->arm_glue_size += size;
252b5132 7318
a4fd1a8e 7319 return myh;
252b5132
RH		 7320}
7321
845b51d6
PB		 7322/* Allocate space for ARMv4 BX veneers. */
7323
7324static void
7325record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7326{
7327 asection * s;
7328 struct elf32_arm_link_hash_table *globals;
7329 char *tmp_name;
7330 struct elf_link_hash_entry *myh;
7331 struct bfd_link_hash_entry *bh;
7332 bfd_vma val;
7333
7334 /* BX PC does not need a veneer. */
7335 if (reg == 15)
7336 return;
7337
7338 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7339 BFD_ASSERT (globals != NULL);
7340 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7341
7342 /* Check if this veneer has already been allocated. */
7343 if (globals->bx_glue_offset[reg])
7344 return;
7345
3d4d4302 7346 s = bfd_get_linker_section
845b51d6
PB		 7347 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7348
7349 BFD_ASSERT (s != NULL);
7350
7351 /* Add symbol for veneer. */
21d799b5
NC		 7352 tmp_name = (char *)
7353 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7354
845b51d6 7355 BFD_ASSERT (tmp_name);
906e58ca 7356
845b51d6 7357 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7358
845b51d6
PB		 7359 myh = elf_link_hash_lookup
7360 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7361
845b51d6 7362 BFD_ASSERT (myh == NULL);
906e58ca 7363
845b51d6
PB		 7364 bh = NULL;
7365 val = globals->bx_glue_size;
7366 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7367 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7368 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7369
7370 myh = (struct elf_link_hash_entry *) bh;
7371 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7372 myh->forced_local = 1;
7373
7374 s->size += ARM_BX_VENEER_SIZE;
7375 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7376 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7377}
7378
7379
c7b8f16e
JB		 7380/* Add an entry to the code/data map for section SEC. */
7381
7382static void
7383elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7384{
7385 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7386 unsigned int newidx;
906e58ca 7387
c7b8f16e
JB		 7388 if (sec_data->map == NULL)
7389 {
21d799b5 7390 sec_data->map = (elf32_arm_section_map *)
99059e56 7391 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7392 sec_data->mapcount = 0;
7393 sec_data->mapsize = 1;
7394 }
906e58ca 7395
c7b8f16e 7396 newidx = sec_data->mapcount++;
906e58ca 7397
c7b8f16e
JB		 7398 if (sec_data->mapcount > sec_data->mapsize)
7399 {
7400 sec_data->mapsize *= 2;
21d799b5 7401 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7402 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7403 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7404 }
7405
7406 if (sec_data->map)
7407 {
7408 sec_data->map[newidx].vma = vma;
7409 sec_data->map[newidx].type = type;
c7b8f16e 7410 }
c7b8f16e
JB		 7411}
7412
7413
7414/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7415 veneers are handled for now. */
7416
7417static bfd_vma
7418record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7419 elf32_vfp11_erratum_list *branch,
7420 bfd *branch_bfd,
7421 asection *branch_sec,
7422 unsigned int offset)
c7b8f16e
JB		 7423{
7424 asection *s;
7425 struct elf32_arm_link_hash_table *hash_table;
7426 char *tmp_name;
7427 struct elf_link_hash_entry *myh;
7428 struct bfd_link_hash_entry *bh;
7429 bfd_vma val;
7430 struct _arm_elf_section_data *sec_data;
c7b8f16e 7431 elf32_vfp11_erratum_list *newerr;
906e58ca 7432
c7b8f16e 7433 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7434 BFD_ASSERT (hash_table != NULL);
7435 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7436
3d4d4302 7437 s = bfd_get_linker_section
c7b8f16e 7438 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7439
c7b8f16e 7440 sec_data = elf32_arm_section_data (s);
906e58ca 7441
c7b8f16e 7442 BFD_ASSERT (s != NULL);
906e58ca 7443
21d799b5 7444 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7445 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7446
c7b8f16e 7447 BFD_ASSERT (tmp_name);
906e58ca 7448
c7b8f16e
JB		 7449 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7450 hash_table->num_vfp11_fixes);
906e58ca 7451
c7b8f16e
JB		 7452 myh = elf_link_hash_lookup
7453 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7454
c7b8f16e 7455 BFD_ASSERT (myh == NULL);
906e58ca 7456
c7b8f16e
JB		 7457 bh = NULL;
7458 val = hash_table->vfp11_erratum_glue_size;
7459 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7460 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7461 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7462
7463 myh = (struct elf_link_hash_entry *) bh;
7464 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7465 myh->forced_local = 1;
7466
7467 /* Link veneer back to calling location. */
c7e2358a 7468 sec_data->erratumcount += 1;
21d799b5
NC		 7469 newerr = (elf32_vfp11_erratum_list *)
7470 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7471
c7b8f16e
JB		 7472 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7473 newerr->vma = -1;
7474 newerr->u.v.branch = branch;
7475 newerr->u.v.id = hash_table->num_vfp11_fixes;
7476 branch->u.b.veneer = newerr;
7477
7478 newerr->next = sec_data->erratumlist;
7479 sec_data->erratumlist = newerr;
7480
7481 /* A symbol for the return from the veneer. */
7482 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7483 hash_table->num_vfp11_fixes);
7484
7485 myh = elf_link_hash_lookup
7486 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7487
c7b8f16e
JB		 7488 if (myh != NULL)
7489 abort ();
7490
7491 bh = NULL;
7492 val = offset + 4;
7493 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7494 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7495
c7b8f16e
JB		 7496 myh = (struct elf_link_hash_entry *) bh;
7497 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7498 myh->forced_local = 1;
7499
7500 free (tmp_name);
906e58ca 7501
c7b8f16e
JB		 7502 /* Generate a mapping symbol for the veneer section, and explicitly add an
7503 entry for that symbol to the code/data map for the section. */
7504 if (hash_table->vfp11_erratum_glue_size == 0)
7505 {
7506 bh = NULL;
7507 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7508 ever requires this erratum fix. */
c7b8f16e
JB		 7509 _bfd_generic_link_add_one_symbol (link_info,
7510 hash_table->bfd_of_glue_owner, "$a",
7511 BSF_LOCAL, s, 0, NULL,
99059e56 7512 TRUE, FALSE, &bh);
c7b8f16e
JB		 7513
7514 myh = (struct elf_link_hash_entry *) bh;
7515 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7516 myh->forced_local = 1;
906e58ca 7517
c7b8f16e 7518 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7519 BFDs. We must make a note of this generated mapping symbol
7520 ourselves so that code byteswapping works properly in
7521 elf32_arm_write_section. */
c7b8f16e
JB		 7522 elf32_arm_section_map_add (s, 'a', 0);
7523 }
906e58ca 7524
c7b8f16e
JB		 7525 s->size += VFP11_ERRATUM_VENEER_SIZE;
7526 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7527 hash_table->num_vfp11_fixes++;
906e58ca 7528
c7b8f16e
JB		 7529 /* The offset of the veneer. */
7530 return val;
7531}
7532
a504d23a
LA		 7533/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7534 veneers need to be handled because used only in Cortex-M. */
7535
7536static bfd_vma
7537record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7538 elf32_stm32l4xx_erratum_list *branch,
7539 bfd *branch_bfd,
7540 asection *branch_sec,
7541 unsigned int offset,
7542 bfd_size_type veneer_size)
7543{
7544 asection *s;
7545 struct elf32_arm_link_hash_table *hash_table;
7546 char *tmp_name;
7547 struct elf_link_hash_entry *myh;
7548 struct bfd_link_hash_entry *bh;
7549 bfd_vma val;
7550 struct _arm_elf_section_data *sec_data;
7551 elf32_stm32l4xx_erratum_list *newerr;
7552
7553 hash_table = elf32_arm_hash_table (link_info);
7554 BFD_ASSERT (hash_table != NULL);
7555 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7556
7557 s = bfd_get_linker_section
7558 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7559
7560 BFD_ASSERT (s != NULL);
7561
7562 sec_data = elf32_arm_section_data (s);
7563
7564 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7565 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7566
7567 BFD_ASSERT (tmp_name);
7568
7569 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7570 hash_table->num_stm32l4xx_fixes);
7571
7572 myh = elf_link_hash_lookup
7573 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7574
7575 BFD_ASSERT (myh == NULL);
7576
7577 bh = NULL;
7578 val = hash_table->stm32l4xx_erratum_glue_size;
7579 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7580 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7581 NULL, TRUE, FALSE, &bh);
7582
7583 myh = (struct elf_link_hash_entry *) bh;
7584 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7585 myh->forced_local = 1;
7586
7587 /* Link veneer back to calling location. */
7588 sec_data->stm32l4xx_erratumcount += 1;
7589 newerr = (elf32_stm32l4xx_erratum_list *)
7590 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7591
7592 newerr->type = STM32L4XX_ERRATUM_VENEER;
7593 newerr->vma = -1;
7594 newerr->u.v.branch = branch;
7595 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7596 branch->u.b.veneer = newerr;
7597
7598 newerr->next = sec_data->stm32l4xx_erratumlist;
7599 sec_data->stm32l4xx_erratumlist = newerr;
7600
7601 /* A symbol for the return from the veneer. */
7602 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7603 hash_table->num_stm32l4xx_fixes);
7604
7605 myh = elf_link_hash_lookup
7606 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7607
7608 if (myh != NULL)
7609 abort ();
7610
7611 bh = NULL;
7612 val = offset + 4;
7613 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7614 branch_sec, val, NULL, TRUE, FALSE, &bh);
7615
7616 myh = (struct elf_link_hash_entry *) bh;
7617 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7618 myh->forced_local = 1;
7619
7620 free (tmp_name);
7621
7622 /* Generate a mapping symbol for the veneer section, and explicitly add an
7623 entry for that symbol to the code/data map for the section. */
7624 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7625 {
7626 bh = NULL;
7627 /* Creates a THUMB symbol since there is no other choice. */
7628 _bfd_generic_link_add_one_symbol (link_info,
7629 hash_table->bfd_of_glue_owner, "$t",
7630 BSF_LOCAL, s, 0, NULL,
7631 TRUE, FALSE, &bh);
7632
7633 myh = (struct elf_link_hash_entry *) bh;
7634 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7635 myh->forced_local = 1;
7636
7637 /* The elf32_arm_init_maps function only cares about symbols from input
7638 BFDs. We must make a note of this generated mapping symbol
7639 ourselves so that code byteswapping works properly in
7640 elf32_arm_write_section. */
7641 elf32_arm_section_map_add (s, 't', 0);
7642 }
7643
7644 s->size += veneer_size;
7645 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7646 hash_table->num_stm32l4xx_fixes++;
7647
7648 /* The offset of the veneer. */
7649 return val;
7650}
7651
8029a119 7652#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7653 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7654 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7655
7656/* Create a fake section for use by the ARM backend of the linker. */
7657
7658static bfd_boolean
7659arm_make_glue_section (bfd * abfd, const char * name)
7660{
7661 asection * sec;
7662
3d4d4302 7663 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7664 if (sec != NULL)
7665 /* Already made. */
7666 return TRUE;
7667
3d4d4302 7668 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7669
7670 if (sec == NULL
7671 || !bfd_set_section_alignment (abfd, sec, 2))
7672 return FALSE;
7673
7674 /* Set the gc mark to prevent the section from being removed by garbage
7675 collection, despite the fact that no relocs refer to this section. */
7676 sec->gc_mark = 1;
7677
7678 return TRUE;
7679}
7680
1db37fe6
YG		 7681/* Set size of .plt entries. This function is called from the
7682 linker scripts in ld/emultempl/{armelf}.em. */
7683
7684void
7685bfd_elf32_arm_use_long_plt (void)
7686{
7687 elf32_arm_use_long_plt_entry = TRUE;
7688}
7689
8afb0e02
NC		 7690/* Add the glue sections to ABFD. This function is called from the
7691 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7692
b34976b6 7693bfd_boolean
57e8b36a
NC		 7694bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7695 struct bfd_link_info *info)
252b5132 7696{
a504d23a
LA		 7697 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7698 bfd_boolean dostm32l4xx = globals
7699 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7700 bfd_boolean addglue;
7701
8afb0e02
NC		 7702 /* If we are only performing a partial
7703 link do not bother adding the glue. */
0e1862bb 7704 if (bfd_link_relocatable (info))
b34976b6 7705 return TRUE;
252b5132 7706
a504d23a 7707 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7708 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7709 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7710 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7711
7712 if (!dostm32l4xx)
7713 return addglue;
7714
7715 return addglue
7716 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7717}
7718
daa4adae
TP		 7719/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7720 ensures they are not marked for deletion by
7721 strip_excluded_output_sections () when veneers are going to be created
7722 later. Not doing so would trigger assert on empty section size in
7723 lang_size_sections_1 (). */
7724
7725void
7726bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7727{
7728 enum elf32_arm_stub_type stub_type;
7729
7730 /* If we are only performing a partial
7731 link do not bother adding the glue. */
7732 if (bfd_link_relocatable (info))
7733 return;
7734
7735 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7736 {
7737 asection *out_sec;
7738 const char *out_sec_name;
7739
7740 if (!arm_dedicated_stub_output_section_required (stub_type))
7741 continue;
7742
7743 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7744 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7745 if (out_sec != NULL)
7746 out_sec->flags |= SEC_KEEP;
7747 }
7748}
7749
8afb0e02
NC		 7750/* Select a BFD to be used to hold the sections used by the glue code.
7751 This function is called from the linker scripts in ld/emultempl/
8029a119 7752 {armelf/pe}.em. */
8afb0e02 7753
b34976b6 7754bfd_boolean
57e8b36a 7755bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7756{
7757 struct elf32_arm_link_hash_table *globals;
7758
7759 /* If we are only performing a partial link
7760 do not bother getting a bfd to hold the glue. */
0e1862bb 7761 if (bfd_link_relocatable (info))
b34976b6 7762 return TRUE;
8afb0e02 7763
b7693d02
DJ		 7764 /* Make sure we don't attach the glue sections to a dynamic object. */
7765 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7766
8afb0e02 7767 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7768 BFD_ASSERT (globals != NULL);
7769
7770 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7771 return TRUE;
8afb0e02 7772
252b5132
RH		 7773 /* Save the bfd for later use. */
7774 globals->bfd_of_glue_owner = abfd;
cedb70c5 7775
b34976b6 7776 return TRUE;
252b5132
RH		 7777}
7778
906e58ca
NC		 7779static void
7780check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7781{
2de70689
MGD		 7782 int cpu_arch;
7783
b38cadfb 7784 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7785 Tag_CPU_arch);
7786
7787 if (globals->fix_arm1176)
7788 {
7789 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7790 globals->use_blx = 1;
7791 }
7792 else
7793 {
7794 if (cpu_arch > TAG_CPU_ARCH_V4T)
7795 globals->use_blx = 1;
7796 }
39b41c9c
PB		 7797}
7798
b34976b6 7799bfd_boolean
57e8b36a 7800bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7801 struct bfd_link_info *link_info)
252b5132
RH		 7802{
7803 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7804 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7805 Elf_Internal_Rela *irel, *irelend;
7806 bfd_byte *contents = NULL;
252b5132
RH		 7807
7808 asection *sec;
7809 struct elf32_arm_link_hash_table *globals;
7810
7811 /* If we are only performing a partial link do not bother
7812 to construct any glue. */
0e1862bb 7813 if (bfd_link_relocatable (link_info))
b34976b6 7814 return TRUE;
252b5132 7815
39ce1a6a
NC		 7816 /* Here we have a bfd that is to be included on the link. We have a
7817 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7818 globals = elf32_arm_hash_table (link_info);
252b5132 7819 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7820
7821 check_use_blx (globals);
252b5132 7822
d504ffc8 7823 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7824 {
90b6238f 7825 _bfd_error_handler (_("%pB: BE8 images only valid in big-endian mode"),
d003868e 7826 abfd);
e489d0ae
PB		 7827 return FALSE;
7828 }
f21f3fe0 7829
39ce1a6a
NC		 7830 /* PR 5398: If we have not decided to include any loadable sections in
7831 the output then we will not have a glue owner bfd. This is OK, it
7832 just means that there is nothing else for us to do here. */
7833 if (globals->bfd_of_glue_owner == NULL)
7834 return TRUE;
7835
252b5132
RH		 7836 /* Rummage around all the relocs and map the glue vectors. */
7837 sec = abfd->sections;
7838
7839 if (sec == NULL)
b34976b6 7840 return TRUE;
252b5132
RH		 7841
7842 for (; sec != NULL; sec = sec->next)
7843 {
7844 if (sec->reloc_count == 0)
7845 continue;
7846
2f475487
AM		 7847 if ((sec->flags & SEC_EXCLUDE) != 0)
7848 continue;
7849
0ffa91dd 7850 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7851
9b485d32 7852 /* Load the relocs. */
6cdc0ccc 7853 internal_relocs
906e58ca 7854 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7855
6cdc0ccc
AM		 7856 if (internal_relocs == NULL)
7857 goto error_return;
252b5132 7858
6cdc0ccc
AM		 7859 irelend = internal_relocs + sec->reloc_count;
7860 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7861 {
7862 long r_type;
7863 unsigned long r_index;
252b5132
RH		 7864
7865 struct elf_link_hash_entry *h;
7866
7867 r_type = ELF32_R_TYPE (irel->r_info);
7868 r_index = ELF32_R_SYM (irel->r_info);
7869
9b485d32 7870 /* These are the only relocation types we care about. */
ba96a88f 7871 if ( r_type != R_ARM_PC24
845b51d6 7872 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7873 continue;
7874
7875 /* Get the section contents if we haven't done so already. */
7876 if (contents == NULL)
7877 {
7878 /* Get cached copy if it exists. */
7879 if (elf_section_data (sec)->this_hdr.contents != NULL)
7880 contents = elf_section_data (sec)->this_hdr.contents;
7881 else
7882 {
7883 /* Go get them off disk. */
57e8b36a 7884 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7885 goto error_return;
7886 }
7887 }
7888
845b51d6
PB		 7889 if (r_type == R_ARM_V4BX)
7890 {
7891 int reg;
7892
7893 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7894 record_arm_bx_glue (link_info, reg);
7895 continue;
7896 }
7897
a7c10850 7898 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7899 h = NULL;
7900
9b485d32 7901 /* We don't care about local symbols. */
252b5132
RH		 7902 if (r_index < symtab_hdr->sh_info)
7903 continue;
7904
9b485d32 7905 /* This is an external symbol. */
252b5132
RH		 7906 r_index -= symtab_hdr->sh_info;
7907 h = (struct elf_link_hash_entry *)
7908 elf_sym_hashes (abfd)[r_index];
7909
7910 /* If the relocation is against a static symbol it must be within
7911 the current section and so cannot be a cross ARM/Thumb relocation. */
7912 if (h == NULL)
7913 continue;
7914
d504ffc8
DJ		 7915 /* If the call will go through a PLT entry then we do not need
7916 glue. */
362d30a1 7917 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7918 continue;
7919
252b5132
RH		 7920 switch (r_type)
7921 {
7922 case R_ARM_PC24:
7923 /* This one is a call from arm code. We need to look up
99059e56
RM		 7924 the target of the call. If it is a thumb target, we
7925 insert glue. */
39d911fc
TP		 7926 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7927 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7928 record_arm_to_thumb_glue (link_info, h);
7929 break;
7930
252b5132 7931 default:
c6596c5e 7932 abort ();
252b5132
RH		 7933 }
7934 }
6cdc0ccc
AM		 7935
7936 if (contents != NULL
7937 && elf_section_data (sec)->this_hdr.contents != contents)
7938 free (contents);
7939 contents = NULL;
7940
7941 if (internal_relocs != NULL
7942 && elf_section_data (sec)->relocs != internal_relocs)
7943 free (internal_relocs);
7944 internal_relocs = NULL;
252b5132
RH		 7945 }
7946
b34976b6 7947 return TRUE;
9a5aca8c 7948
252b5132 7949error_return:
6cdc0ccc
AM		 7950 if (contents != NULL
7951 && elf_section_data (sec)->this_hdr.contents != contents)
7952 free (contents);
7953 if (internal_relocs != NULL
7954 && elf_section_data (sec)->relocs != internal_relocs)
7955 free (internal_relocs);
9a5aca8c 7956
b34976b6 7957 return FALSE;
252b5132 7958}
7e392df6 7959#endif
252b5132 7960
eb043451 7961
c7b8f16e
JB		 7962/* Initialise maps of ARM/Thumb/data for input BFDs. */
7963
7964void
7965bfd_elf32_arm_init_maps (bfd *abfd)
7966{
7967 Elf_Internal_Sym *isymbuf;
7968 Elf_Internal_Shdr *hdr;
7969 unsigned int i, localsyms;
7970
af1f4419
NC		 7971 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7972 if (! is_arm_elf (abfd))
7973 return;
7974
c7b8f16e
JB		 7975 if ((abfd->flags & DYNAMIC) != 0)
7976 return;
7977
0ffa91dd 7978 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7979 localsyms = hdr->sh_info;
7980
7981 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7982 should contain the number of local symbols, which should come before any
7983 global symbols. Mapping symbols are always local. */
7984 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7985 NULL);
7986
7987 /* No internal symbols read? Skip this BFD. */
7988 if (isymbuf == NULL)
7989 return;
7990
7991 for (i = 0; i < localsyms; i++)
7992 {
7993 Elf_Internal_Sym *isym = &isymbuf[i];
7994 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
7995 const char *name;
906e58ca 7996
c7b8f16e 7997 if (sec != NULL
99059e56
RM		 7998 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
7999 {
8000 name = bfd_elf_string_from_elf_section (abfd,
8001 hdr->sh_link, isym->st_name);
906e58ca 8002
99059e56 8003 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 8004 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 8005 elf32_arm_section_map_add (sec, name[1], isym->st_value);
8006 }
c7b8f16e
JB		 8007 }
8008}
8009
8010
48229727
JB		 8011/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
8012 say what they wanted. */
8013
8014void
8015bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
8016{
8017 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8018 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8019
4dfe6ac6
NC		 8020 if (globals == NULL)
8021 return;
8022
48229727
JB		 8023 if (globals->fix_cortex_a8 == -1)
8024 {
8025 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
8026 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
8027 && (out_attr[Tag_CPU_arch_profile].i == 'A'
8028 || out_attr[Tag_CPU_arch_profile].i == 0))
8029 globals->fix_cortex_a8 = 1;
8030 else
8031 globals->fix_cortex_a8 = 0;
8032 }
8033}
8034
8035
c7b8f16e
JB		 8036void
8037bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
8038{
8039 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 8040 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 8041
4dfe6ac6
NC		 8042 if (globals == NULL)
8043 return;
c7b8f16e
JB		 8044 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8045 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
8046 {
8047 switch (globals->vfp11_fix)
99059e56
RM		 8048 {
8049 case BFD_ARM_VFP11_FIX_DEFAULT:
8050 case BFD_ARM_VFP11_FIX_NONE:
8051 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8052 break;
8053
8054 default:
8055 /* Give a warning, but do as the user requests anyway. */
871b3ab2 8056 _bfd_error_handler (_("%pB: warning: selected VFP11 erratum "
99059e56
RM		 8057 "workaround is not necessary for target architecture"), obfd);
8058 }
c7b8f16e
JB		 8059 }
8060 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
8061 /* For earlier architectures, we might need the workaround, but do not
8062 enable it by default. If users is running with broken hardware, they
8063 must enable the erratum fix explicitly. */
8064 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8065}
8066
a504d23a
LA		 8067void
8068bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
8069{
8070 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8071 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8072
8073 if (globals == NULL)
8074 return;
8075
8076 /* We assume only Cortex-M4 may require the fix. */
8077 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
8078 || out_attr[Tag_CPU_arch_profile].i != 'M')
8079 {
8080 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
8081 /* Give a warning, but do as the user requests anyway. */
4eca0228 8082 _bfd_error_handler
871b3ab2 8083 (_("%pB: warning: selected STM32L4XX erratum "
a504d23a
LA		 8084 "workaround is not necessary for target architecture"), obfd);
8085 }
8086}
c7b8f16e 8087
906e58ca
NC		 8088enum bfd_arm_vfp11_pipe
8089{
c7b8f16e
JB		 8090 VFP11_FMAC,
8091 VFP11_LS,
8092 VFP11_DS,
8093 VFP11_BAD
8094};
8095
8096/* Return a VFP register number. This is encoded as RX:X for single-precision
8097 registers, or X:RX for double-precision registers, where RX is the group of
8098 four bits in the instruction encoding and X is the single extension bit.
8099 RX and X fields are specified using their lowest (starting) bit. The return
8100 value is:
8101
8102 0...31: single-precision registers s0...s31
8103 32...63: double-precision registers d0...d31.
906e58ca 8104
c7b8f16e
JB		 8105 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8106 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 8107
c7b8f16e
JB		 8108static unsigned int
8109bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 8110 unsigned int x)
c7b8f16e
JB		 8111{
8112 if (is_double)
8113 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
8114 else
8115 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
8116}
8117
8118/* Set bits in *WMASK according to a register number REG as encoded by
8119 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8120
8121static void
8122bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
8123{
8124 if (reg < 32)
8125 *wmask |= 1 << reg;
8126 else if (reg < 48)
8127 *wmask |= 3 << ((reg - 32) * 2);
8128}
8129
8130/* Return TRUE if WMASK overwrites anything in REGS. */
8131
8132static bfd_boolean
8133bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
8134{
8135 int i;
906e58ca 8136
c7b8f16e
JB		 8137 for (i = 0; i < numregs; i++)
8138 {
8139 unsigned int reg = regs[i];
8140
8141 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 8142 return TRUE;
906e58ca 8143
c7b8f16e
JB		 8144 reg -= 32;
8145
8146 if (reg >= 16)
99059e56 8147 continue;
906e58ca 8148
c7b8f16e 8149 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 8150 return TRUE;
c7b8f16e 8151 }
906e58ca 8152
c7b8f16e
JB		 8153 return FALSE;
8154}
8155
8156/* In this function, we're interested in two things: finding input registers
8157 for VFP data-processing instructions, and finding the set of registers which
8158 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8159 hold the written set, so FLDM etc. are easy to deal with (we're only
8160 interested in 32 SP registers or 16 dp registers, due to the VFP version
8161 implemented by the chip in question). DP registers are marked by setting
8162 both SP registers in the write mask). */
8163
8164static enum bfd_arm_vfp11_pipe
8165bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 8166 int *numregs)
c7b8f16e 8167{
91d6fa6a 8168 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 8169 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
8170
8171 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
8172 {
8173 unsigned int pqrs;
8174 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8175 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
8176
8177 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 8178 | ((insn & 0x00300000) >> 19)
8179 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 8180
8181 switch (pqrs)
99059e56
RM		 8182 {
8183 case 0: /* fmac[sd]. */
8184 case 1: /* fnmac[sd]. */
8185 case 2: /* fmsc[sd]. */
8186 case 3: /* fnmsc[sd]. */
8187 vpipe = VFP11_FMAC;
8188 bfd_arm_vfp11_write_mask (destmask, fd);
8189 regs[0] = fd;
8190 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8191 regs[2] = fm;
8192 *numregs = 3;
8193 break;
8194
8195 case 4: /* fmul[sd]. */
8196 case 5: /* fnmul[sd]. */
8197 case 6: /* fadd[sd]. */
8198 case 7: /* fsub[sd]. */
8199 vpipe = VFP11_FMAC;
8200 goto vfp_binop;
8201
8202 case 8: /* fdiv[sd]. */
8203 vpipe = VFP11_DS;
8204 vfp_binop:
8205 bfd_arm_vfp11_write_mask (destmask, fd);
8206 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8207 regs[1] = fm;
8208 *numregs = 2;
8209 break;
8210
8211 case 15: /* extended opcode. */
8212 {
8213 unsigned int extn = ((insn >> 15) & 0x1e)
8214 | ((insn >> 7) & 1);
8215
8216 switch (extn)
8217 {
8218 case 0: /* fcpy[sd]. */
8219 case 1: /* fabs[sd]. */
8220 case 2: /* fneg[sd]. */
8221 case 8: /* fcmp[sd]. */
8222 case 9: /* fcmpe[sd]. */
8223 case 10: /* fcmpz[sd]. */
8224 case 11: /* fcmpez[sd]. */
8225 case 16: /* fuito[sd]. */
8226 case 17: /* fsito[sd]. */
8227 case 24: /* ftoui[sd]. */
8228 case 25: /* ftouiz[sd]. */
8229 case 26: /* ftosi[sd]. */
8230 case 27: /* ftosiz[sd]. */
8231 /* These instructions will not bounce due to underflow. */
8232 *numregs = 0;
8233 vpipe = VFP11_FMAC;
8234 break;
8235
8236 case 3: /* fsqrt[sd]. */
8237 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8238 registers to cause the erratum in previous instructions. */
8239 bfd_arm_vfp11_write_mask (destmask, fd);
8240 vpipe = VFP11_DS;
8241 break;
8242
8243 case 15: /* fcvt{ds,sd}. */
8244 {
8245 int rnum = 0;
8246
8247 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 8248
8249 /* Only FCVTSD can underflow. */
99059e56
RM		 8250 if ((insn & 0x100) != 0)
8251 regs[rnum++] = fm;
c7b8f16e 8252
99059e56 8253 *numregs = rnum;
c7b8f16e 8254
99059e56
RM		 8255 vpipe = VFP11_FMAC;
8256 }
8257 break;
c7b8f16e 8258
99059e56
RM		 8259 default:
8260 return VFP11_BAD;
8261 }
8262 }
8263 break;
c7b8f16e 8264
99059e56
RM		 8265 default:
8266 return VFP11_BAD;
8267 }
c7b8f16e
JB		 8268 }
8269 /* Two-register transfer. */
8270 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
8271 {
8272 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 8273
c7b8f16e
JB		 8274 if ((insn & 0x100000) == 0)
8275 {
99059e56
RM		 8276 if (is_double)
8277 bfd_arm_vfp11_write_mask (destmask, fm);
8278 else
8279 {
8280 bfd_arm_vfp11_write_mask (destmask, fm);
8281 bfd_arm_vfp11_write_mask (destmask, fm + 1);
8282 }
c7b8f16e
JB		 8283 }
8284
91d6fa6a 8285 vpipe = VFP11_LS;
c7b8f16e
JB		 8286 }
8287 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
8288 {
8289 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8290 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 8291
c7b8f16e 8292 switch (puw)
99059e56
RM		 8293 {
8294 case 0: /* Two-reg transfer. We should catch these above. */
8295 abort ();
906e58ca 8296
99059e56
RM		 8297 case 2: /* fldm[sdx]. */
8298 case 3:
8299 case 5:
8300 {
8301 unsigned int i, offset = insn & 0xff;
c7b8f16e 8302
99059e56
RM		 8303 if (is_double)
8304 offset >>= 1;
c7b8f16e 8305
99059e56
RM		 8306 for (i = fd; i < fd + offset; i++)
8307 bfd_arm_vfp11_write_mask (destmask, i);
8308 }
8309 break;
906e58ca 8310
99059e56
RM		 8311 case 4: /* fld[sd]. */
8312 case 6:
8313 bfd_arm_vfp11_write_mask (destmask, fd);
8314 break;
906e58ca 8315
99059e56
RM		 8316 default:
8317 return VFP11_BAD;
8318 }
c7b8f16e 8319
91d6fa6a 8320 vpipe = VFP11_LS;
c7b8f16e
JB		 8321 }
8322 /* Single-register transfer. Note L==0. */
8323 else if ((insn & 0x0f100e10) == 0x0e000a10)
8324 {
8325 unsigned int opcode = (insn >> 21) & 7;
8326 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8327
8328 switch (opcode)
99059e56
RM		 8329 {
8330 case 0: /* fmsr/fmdlr. */
8331 case 1: /* fmdhr. */
8332 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8333 destination register. I don't know if this is exactly right,
8334 but it is the conservative choice. */
8335 bfd_arm_vfp11_write_mask (destmask, fn);
8336 break;
8337
8338 case 7: /* fmxr. */
8339 break;
8340 }
c7b8f16e 8341
91d6fa6a 8342 vpipe = VFP11_LS;
c7b8f16e
JB		 8343 }
8344
91d6fa6a 8345 return vpipe;
c7b8f16e
JB		 8346}
8347
8348
8349static int elf32_arm_compare_mapping (const void * a, const void * b);
8350
8351
8352/* Look for potentially-troublesome code sequences which might trigger the
8353 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8354 (available from ARM) for details of the erratum. A short version is
8355 described in ld.texinfo. */
8356
8357bfd_boolean
8358bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8359{
8360 asection *sec;
8361 bfd_byte *contents = NULL;
8362 int state = 0;
8363 int regs[3], numregs = 0;
8364 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8365 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8366
4dfe6ac6
NC		 8367 if (globals == NULL)
8368 return FALSE;
8369
c7b8f16e
JB		 8370 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8371 The states transition as follows:
906e58ca 8372
c7b8f16e 8373 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8374 A VFP FMAC-pipeline instruction has been seen. Fill
8375 regs[0]..regs[numregs-1] with its input operands. Remember this
8376 instruction in 'first_fmac'.
c7b8f16e
JB		 8377
8378 1 -> 2
99059e56
RM		 8379 Any instruction, except for a VFP instruction which overwrites
8380 regs[*].
906e58ca 8381
c7b8f16e
JB		 8382 1 -> 3 [ -> 0 ] or
8383 2 -> 3 [ -> 0 ]
99059e56
RM		 8384 A VFP instruction has been seen which overwrites any of regs[*].
8385 We must make a veneer! Reset state to 0 before examining next
8386 instruction.
906e58ca 8387
c7b8f16e 8388 2 -> 0
99059e56
RM		 8389 If we fail to match anything in state 2, reset to state 0 and reset
8390 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8391
8392 If the VFP11 vector mode is in use, there must be at least two unrelated
8393 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8394 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8395
8396 /* If we are only performing a partial link do not bother
8397 to construct any glue. */
0e1862bb 8398 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8399 return TRUE;
8400
0ffa91dd
NC		 8401 /* Skip if this bfd does not correspond to an ELF image. */
8402 if (! is_arm_elf (abfd))
8403 return TRUE;
906e58ca 8404
c7b8f16e
JB		 8405 /* We should have chosen a fix type by the time we get here. */
8406 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8407
8408 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8409 return TRUE;
2e6030b9 8410
33a7ffc2
JM		 8411 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8412 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8413 return TRUE;
8414
c7b8f16e
JB		 8415 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8416 {
8417 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8418 struct _arm_elf_section_data *sec_data;
8419
8420 /* If we don't have executable progbits, we're not interested in this
99059e56 8421 section. Also skip if section is to be excluded. */
c7b8f16e 8422 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8423 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8424 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8425 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8426 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8427 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8428 continue;
c7b8f16e
JB		 8429
8430 sec_data = elf32_arm_section_data (sec);
906e58ca 8431
c7b8f16e 8432 if (sec_data->mapcount == 0)
99059e56 8433 continue;
906e58ca 8434
c7b8f16e
JB		 8435 if (elf_section_data (sec)->this_hdr.contents != NULL)
8436 contents = elf_section_data (sec)->this_hdr.contents;
8437 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8438 goto error_return;
8439
8440 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8441 elf32_arm_compare_mapping);
8442
8443 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8444 {
8445 unsigned int span_start = sec_data->map[span].vma;
8446 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8447 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8448 char span_type = sec_data->map[span].type;
8449
8450 /* FIXME: Only ARM mode is supported at present. We may need to
8451 support Thumb-2 mode also at some point. */
8452 if (span_type != 'a')
8453 continue;
8454
8455 for (i = span_start; i < span_end;)
8456 {
8457 unsigned int next_i = i + 4;
8458 unsigned int insn = bfd_big_endian (abfd)
8459 ? (contents[i] << 24)
8460 | (contents[i + 1] << 16)
8461 | (contents[i + 2] << 8)
8462 | contents[i + 3]
8463 : (contents[i + 3] << 24)
8464 | (contents[i + 2] << 16)
8465 | (contents[i + 1] << 8)
8466 | contents[i];
8467 unsigned int writemask = 0;
8468 enum bfd_arm_vfp11_pipe vpipe;
8469
8470 switch (state)
8471 {
8472 case 0:
8473 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8474 &numregs);
8475 /* I'm assuming the VFP11 erratum can trigger with denorm
8476 operands on either the FMAC or the DS pipeline. This might
8477 lead to slightly overenthusiastic veneer insertion. */
8478 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8479 {
8480 state = use_vector ? 1 : 2;
8481 first_fmac = i;
8482 veneer_of_insn = insn;
8483 }
8484 break;
8485
8486 case 1:
8487 {
8488 int other_regs[3], other_numregs;
8489 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8490 other_regs,
99059e56
RM		 8491 &other_numregs);
8492 if (vpipe != VFP11_BAD
8493 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8494 numregs))
99059e56
RM		 8495 state = 3;
8496 else
8497 state = 2;
8498 }
8499 break;
8500
8501 case 2:
8502 {
8503 int other_regs[3], other_numregs;
8504 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8505 other_regs,
99059e56
RM		 8506 &other_numregs);
8507 if (vpipe != VFP11_BAD
8508 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8509 numregs))
99059e56
RM		 8510 state = 3;
8511 else
8512 {
8513 state = 0;
8514 next_i = first_fmac + 4;
8515 }
8516 }
8517 break;
8518
8519 case 3:
8520 abort (); /* Should be unreachable. */
8521 }
8522
8523 if (state == 3)
8524 {
8525 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8526 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8527
8528 elf32_arm_section_data (sec)->erratumcount += 1;
8529
8530 newerr->u.b.vfp_insn = veneer_of_insn;
8531
8532 switch (span_type)
8533 {
8534 case 'a':
8535 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8536 break;
8537
8538 default:
8539 abort ();
8540 }
8541
8542 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8543 first_fmac);
8544
99059e56 8545 newerr->vma = -1;
c7b8f16e 8546
99059e56
RM		 8547 newerr->next = sec_data->erratumlist;
8548 sec_data->erratumlist = newerr;
c7b8f16e 8549
99059e56
RM		 8550 state = 0;
8551 }
c7b8f16e 8552
99059e56
RM		 8553 i = next_i;
8554 }
8555 }
906e58ca 8556
c7b8f16e 8557 if (contents != NULL
99059e56
RM		 8558 && elf_section_data (sec)->this_hdr.contents != contents)
8559 free (contents);
c7b8f16e
JB		 8560 contents = NULL;
8561 }
8562
8563 return TRUE;
8564
8565error_return:
8566 if (contents != NULL
8567 && elf_section_data (sec)->this_hdr.contents != contents)
8568 free (contents);
906e58ca 8569
c7b8f16e
JB		 8570 return FALSE;
8571}
8572
8573/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8574 after sections have been laid out, using specially-named symbols. */
8575
8576void
8577bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8578 struct bfd_link_info *link_info)
8579{
8580 asection *sec;
8581 struct elf32_arm_link_hash_table *globals;
8582 char *tmp_name;
906e58ca 8583
0e1862bb 8584 if (bfd_link_relocatable (link_info))
c7b8f16e 8585 return;
2e6030b9
MS		 8586
8587 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8588 if (! is_arm_elf (abfd))
2e6030b9
MS		 8589 return;
8590
c7b8f16e 8591 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8592 if (globals == NULL)
8593 return;
906e58ca 8594
21d799b5 8595 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8596 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8597
8598 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8599 {
8600 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8601 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8602
c7b8f16e 8603 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8604 {
8605 struct elf_link_hash_entry *myh;
8606 bfd_vma vma;
8607
8608 switch (errnode->type)
8609 {
8610 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8611 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8612 /* Find veneer symbol. */
8613 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8614 errnode->u.b.veneer->u.v.id);
8615
99059e56
RM		 8616 myh = elf_link_hash_lookup
8617 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8618
a504d23a 8619 if (myh == NULL)
90b6238f
AM		 8620 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8621 abfd, "VFP11", tmp_name);
a504d23a
LA		 8622
8623 vma = myh->root.u.def.section->output_section->vma
8624 + myh->root.u.def.section->output_offset
8625 + myh->root.u.def.value;
8626
8627 errnode->u.b.veneer->vma = vma;
8628 break;
8629
8630 case VFP11_ERRATUM_ARM_VENEER:
8631 case VFP11_ERRATUM_THUMB_VENEER:
8632 /* Find return location. */
8633 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8634 errnode->u.v.id);
8635
8636 myh = elf_link_hash_lookup
8637 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8638
8639 if (myh == NULL)
90b6238f
AM		 8640 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8641 abfd, "VFP11", tmp_name);
a504d23a
LA		 8642
8643 vma = myh->root.u.def.section->output_section->vma
8644 + myh->root.u.def.section->output_offset
8645 + myh->root.u.def.value;
8646
8647 errnode->u.v.branch->vma = vma;
8648 break;
8649
8650 default:
8651 abort ();
8652 }
8653 }
8654 }
8655
8656 free (tmp_name);
8657}
8658
8659/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8660 return locations after sections have been laid out, using
8661 specially-named symbols. */
8662
8663void
8664bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8665 struct bfd_link_info *link_info)
8666{
8667 asection *sec;
8668 struct elf32_arm_link_hash_table *globals;
8669 char *tmp_name;
8670
8671 if (bfd_link_relocatable (link_info))
8672 return;
8673
8674 /* Skip if this bfd does not correspond to an ELF image. */
8675 if (! is_arm_elf (abfd))
8676 return;
8677
8678 globals = elf32_arm_hash_table (link_info);
8679 if (globals == NULL)
8680 return;
8681
8682 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8683 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8684
8685 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8686 {
8687 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8688 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8689
8690 for (; errnode != NULL; errnode = errnode->next)
8691 {
8692 struct elf_link_hash_entry *myh;
8693 bfd_vma vma;
8694
8695 switch (errnode->type)
8696 {
8697 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8698 /* Find veneer symbol. */
8699 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8700 errnode->u.b.veneer->u.v.id);
8701
8702 myh = elf_link_hash_lookup
8703 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8704
8705 if (myh == NULL)
90b6238f
AM		 8706 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8707 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8708
8709 vma = myh->root.u.def.section->output_section->vma
8710 + myh->root.u.def.section->output_offset
8711 + myh->root.u.def.value;
8712
8713 errnode->u.b.veneer->vma = vma;
8714 break;
8715
8716 case STM32L4XX_ERRATUM_VENEER:
8717 /* Find return location. */
8718 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8719 errnode->u.v.id);
8720
8721 myh = elf_link_hash_lookup
8722 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8723
8724 if (myh == NULL)
90b6238f
AM		 8725 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8726 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8727
8728 vma = myh->root.u.def.section->output_section->vma
8729 + myh->root.u.def.section->output_offset
8730 + myh->root.u.def.value;
8731
8732 errnode->u.v.branch->vma = vma;
8733 break;
8734
8735 default:
8736 abort ();
8737 }
8738 }
8739 }
8740
8741 free (tmp_name);
8742}
8743
8744static inline bfd_boolean
8745is_thumb2_ldmia (const insn32 insn)
8746{
8747 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8748 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8749 return (insn & 0xffd02000) == 0xe8900000;
8750}
8751
8752static inline bfd_boolean
8753is_thumb2_ldmdb (const insn32 insn)
8754{
8755 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8756 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8757 return (insn & 0xffd02000) == 0xe9100000;
8758}
8759
8760static inline bfd_boolean
8761is_thumb2_vldm (const insn32 insn)
8762{
8763 /* A6.5 Extension register load or store instruction
8764 A7.7.229
9239bbd3
CM		 8765 We look for SP 32-bit and DP 64-bit registers.
8766 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8767 <list> is consecutive 64-bit registers
8768 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8769 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8770 <list> is consecutive 32-bit registers
8771 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8772 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8773 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8774 return
9239bbd3
CM		 8775 (((insn & 0xfe100f00) == 0xec100b00) ||
8776 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8777 && /* (IA without !). */
8778 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8779 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8780 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8781 /* (DB with !). */
8782 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8783}
8784
8785/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8786 VLDM opcode and:
8787 - computes the number and the mode of memory accesses
8788 - decides if the replacement should be done:
8789 . replaces only if > 8-word accesses
8790 . or (testing purposes only) replaces all accesses. */
8791
8792static bfd_boolean
8793stm32l4xx_need_create_replacing_stub (const insn32 insn,
8794 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8795{
9239bbd3 8796 int nb_words = 0;
a504d23a
LA		 8797
8798 /* The field encoding the register list is the same for both LDMIA
8799 and LDMDB encodings. */
8800 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8801 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8802 else if (is_thumb2_vldm (insn))
9239bbd3 8803 nb_words = (insn & 0xff);
a504d23a
LA		 8804
8805 /* DEFAULT mode accounts for the real bug condition situation,
8806 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8807 return
9239bbd3 8808 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8809 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8810}
8811
8812/* Look for potentially-troublesome code sequences which might trigger
8813 the STM STM32L4XX erratum. */
8814
8815bfd_boolean
8816bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8817 struct bfd_link_info *link_info)
8818{
8819 asection *sec;
8820 bfd_byte *contents = NULL;
8821 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8822
8823 if (globals == NULL)
8824 return FALSE;
8825
8826 /* If we are only performing a partial link do not bother
8827 to construct any glue. */
8828 if (bfd_link_relocatable (link_info))
8829 return TRUE;
8830
8831 /* Skip if this bfd does not correspond to an ELF image. */
8832 if (! is_arm_elf (abfd))
8833 return TRUE;
8834
8835 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8836 return TRUE;
8837
8838 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8839 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8840 return TRUE;
8841
8842 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8843 {
8844 unsigned int i, span;
8845 struct _arm_elf_section_data *sec_data;
8846
8847 /* If we don't have executable progbits, we're not interested in this
8848 section. Also skip if section is to be excluded. */
8849 if (elf_section_type (sec) != SHT_PROGBITS
8850 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8851 || (sec->flags & SEC_EXCLUDE) != 0
8852 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8853 || sec->output_section == bfd_abs_section_ptr
8854 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8855 continue;
8856
8857 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8858
a504d23a
LA		 8859 if (sec_data->mapcount == 0)
8860 continue;
c7b8f16e 8861
a504d23a
LA		 8862 if (elf_section_data (sec)->this_hdr.contents != NULL)
8863 contents = elf_section_data (sec)->this_hdr.contents;
8864 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8865 goto error_return;
c7b8f16e 8866
a504d23a
LA		 8867 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8868 elf32_arm_compare_mapping);
c7b8f16e 8869
a504d23a
LA		 8870 for (span = 0; span < sec_data->mapcount; span++)
8871 {
8872 unsigned int span_start = sec_data->map[span].vma;
8873 unsigned int span_end = (span == sec_data->mapcount - 1)
8874 ? sec->size : sec_data->map[span + 1].vma;
8875 char span_type = sec_data->map[span].type;
8876 int itblock_current_pos = 0;
c7b8f16e 8877
a504d23a
LA		 8878 /* Only Thumb2 mode need be supported with this CM4 specific
8879 code, we should not encounter any arm mode eg span_type
8880 != 'a'. */
8881 if (span_type != 't')
8882 continue;
c7b8f16e 8883
a504d23a
LA		 8884 for (i = span_start; i < span_end;)
8885 {
8886 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8887 bfd_boolean insn_32bit = FALSE;
8888 bfd_boolean is_ldm = FALSE;
8889 bfd_boolean is_vldm = FALSE;
8890 bfd_boolean is_not_last_in_it_block = FALSE;
8891
8892 /* The first 16-bits of all 32-bit thumb2 instructions start
8893 with opcode[15..13]=0b111 and the encoded op1 can be anything
8894 except opcode[12..11]!=0b00.
8895 See 32-bit Thumb instruction encoding. */
8896 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8897 insn_32bit = TRUE;
c7b8f16e 8898
a504d23a
LA		 8899 /* Compute the predicate that tells if the instruction
8900 is concerned by the IT block
8901 - Creates an error if there is a ldm that is not
8902 last in the IT block thus cannot be replaced
8903 - Otherwise we can create a branch at the end of the
8904 IT block, it will be controlled naturally by IT
8905 with the proper pseudo-predicate
8906 - So the only interesting predicate is the one that
8907 tells that we are not on the last item of an IT
8908 block. */
8909 if (itblock_current_pos != 0)
8910 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8911
a504d23a
LA		 8912 if (insn_32bit)
8913 {
8914 /* Load the rest of the insn (in manual-friendly order). */
8915 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8916 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8917 is_vldm = is_thumb2_vldm (insn);
8918
8919 /* Veneers are created for (v)ldm depending on
8920 option flags and memory accesses conditions; but
8921 if the instruction is not the last instruction of
8922 an IT block, we cannot create a jump there, so we
8923 bail out. */
5025eb7c
AO		 8924 if ((is_ldm || is_vldm)
8925 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8926 (insn, globals->stm32l4xx_fix))
8927 {
8928 if (is_not_last_in_it_block)
8929 {
4eca0228 8930 _bfd_error_handler
695344c0 8931 /* xgettext:c-format */
871b3ab2 8932 (_("%pB(%pA+%#x): error: multiple load detected"
90b6238f
AM		 8933 " in non-last IT block instruction:"
8934 " STM32L4XX veneer cannot be generated; "
8935 "use gcc option -mrestrict-it to generate"
8936 " only one instruction per IT block"),
d42c267e 8937 abfd, sec, i);
a504d23a
LA		 8938 }
8939 else
8940 {
8941 elf32_stm32l4xx_erratum_list *newerr =
8942 (elf32_stm32l4xx_erratum_list *)
8943 bfd_zmalloc
8944 (sizeof (elf32_stm32l4xx_erratum_list));
8945
8946 elf32_arm_section_data (sec)
8947 ->stm32l4xx_erratumcount += 1;
8948 newerr->u.b.insn = insn;
8949 /* We create only thumb branches. */
8950 newerr->type =
8951 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8952 record_stm32l4xx_erratum_veneer
8953 (link_info, newerr, abfd, sec,
8954 i,
8955 is_ldm ?
8956 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8957 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8958 newerr->vma = -1;
8959 newerr->next = sec_data->stm32l4xx_erratumlist;
8960 sec_data->stm32l4xx_erratumlist = newerr;
8961 }
8962 }
8963 }
8964 else
8965 {
8966 /* A7.7.37 IT p208
8967 IT blocks are only encoded in T1
8968 Encoding T1: IT{x{y{z}}} <firstcond>
8969 1 0 1 1 - 1 1 1 1 - firstcond - mask
8970 if mask = '0000' then see 'related encodings'
8971 We don't deal with UNPREDICTABLE, just ignore these.
8972 There can be no nested IT blocks so an IT block
8973 is naturally a new one for which it is worth
8974 computing its size. */
5025eb7c
AO		 8975 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
8976 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 8977 /* If we have a new IT block we compute its size. */
8978 if (is_newitblock)
8979 {
8980 /* Compute the number of instructions controlled
8981 by the IT block, it will be used to decide
8982 whether we are inside an IT block or not. */
8983 unsigned int mask = insn & 0x000f;
8984 itblock_current_pos = 4 - ctz (mask);
8985 }
8986 }
8987
8988 i += insn_32bit ? 4 : 2;
99059e56
RM		 8989 }
8990 }
a504d23a
LA		 8991
8992 if (contents != NULL
8993 && elf_section_data (sec)->this_hdr.contents != contents)
8994 free (contents);
8995 contents = NULL;
c7b8f16e 8996 }
906e58ca 8997
a504d23a
LA		 8998 return TRUE;
8999
9000error_return:
9001 if (contents != NULL
9002 && elf_section_data (sec)->this_hdr.contents != contents)
9003 free (contents);
c7b8f16e 9004
a504d23a
LA		 9005 return FALSE;
9006}
c7b8f16e 9007
eb043451
PB		 9008/* Set target relocation values needed during linking. */
9009
9010void
68c39892 9011bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 9012 struct bfd_link_info *link_info,
68c39892 9013 struct elf32_arm_params *params)
eb043451
PB		 9014{
9015 struct elf32_arm_link_hash_table *globals;
9016
9017 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9018 if (globals == NULL)
9019 return;
eb043451 9020
68c39892 9021 globals->target1_is_rel = params->target1_is_rel;
29e9b073
CL		 9022 if (globals->fdpic_p)
9023 globals->target2_reloc = R_ARM_GOT32;
9024 else if (strcmp (params->target2_type, "rel") == 0)
eb043451 9025 globals->target2_reloc = R_ARM_REL32;
68c39892 9026 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 9027 globals->target2_reloc = R_ARM_ABS32;
68c39892 9028 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 9029 globals->target2_reloc = R_ARM_GOT_PREL;
9030 else
9031 {
90b6238f 9032 _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"),
68c39892 9033 params->target2_type);
eb043451 9034 }
68c39892
TP		 9035 globals->fix_v4bx = params->fix_v4bx;
9036 globals->use_blx |= params->use_blx;
9037 globals->vfp11_fix = params->vfp11_denorm_fix;
9038 globals->stm32l4xx_fix = params->stm32l4xx_fix;
e8b09b87
CL		 9039 if (globals->fdpic_p)
9040 globals->pic_veneer = 1;
9041 else
9042 globals->pic_veneer = params->pic_veneer;
68c39892
TP		 9043 globals->fix_cortex_a8 = params->fix_cortex_a8;
9044 globals->fix_arm1176 = params->fix_arm1176;
9045 globals->cmse_implib = params->cmse_implib;
9046 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 9047
0ffa91dd 9048 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 9049 elf_arm_tdata (output_bfd)->no_enum_size_warning
9050 = params->no_enum_size_warning;
9051 elf_arm_tdata (output_bfd)->no_wchar_size_warning
9052 = params->no_wchar_size_warning;
eb043451 9053}
eb043451 9054
12a0a0fd 9055/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 9056
12a0a0fd
PB		 9057static void
9058insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
9059{
9060 bfd_vma upper;
9061 bfd_vma lower;
9062 int reloc_sign;
9063
9064 BFD_ASSERT ((offset & 1) == 0);
9065
9066 upper = bfd_get_16 (abfd, insn);
9067 lower = bfd_get_16 (abfd, insn + 2);
9068 reloc_sign = (offset < 0) ? 1 : 0;
9069 upper = (upper & ~(bfd_vma) 0x7ff)
9070 | ((offset >> 12) & 0x3ff)
9071 | (reloc_sign << 10);
906e58ca 9072 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 9073 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
9074 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
9075 | ((offset >> 1) & 0x7ff);
9076 bfd_put_16 (abfd, upper, insn);
9077 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 9078}
9079
9b485d32
NC		 9080/* Thumb code calling an ARM function. */
9081
252b5132 9082static int
57e8b36a 9083elf32_thumb_to_arm_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9084 const char * name,
9085 bfd * input_bfd,
9086 bfd * output_bfd,
9087 asection * input_section,
9088 bfd_byte * hit_data,
9089 asection * sym_sec,
9090 bfd_vma offset,
9091 bfd_signed_vma addend,
9092 bfd_vma val,
f2a9dd69 9093 char **error_message)
252b5132 9094{
bcbdc74c 9095 asection * s = 0;
dc810e39 9096 bfd_vma my_offset;
252b5132 9097 long int ret_offset;
bcbdc74c
NC		 9098 struct elf_link_hash_entry * myh;
9099 struct elf32_arm_link_hash_table * globals;
252b5132 9100
f2a9dd69 9101 myh = find_thumb_glue (info, name, error_message);
252b5132 9102 if (myh == NULL)
b34976b6 9103 return FALSE;
252b5132
RH		 9104
9105 globals = elf32_arm_hash_table (info);
252b5132
RH		 9106 BFD_ASSERT (globals != NULL);
9107 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9108
9109 my_offset = myh->root.u.def.value;
9110
3d4d4302
AM		 9111 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9112 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 9113
9114 BFD_ASSERT (s != NULL);
9115 BFD_ASSERT (s->contents != NULL);
9116 BFD_ASSERT (s->output_section != NULL);
9117
9118 if ((my_offset & 0x01) == 0x01)
9119 {
9120 if (sym_sec != NULL
9121 && sym_sec->owner != NULL
9122 && !INTERWORK_FLAG (sym_sec->owner))
9123 {
4eca0228 9124 _bfd_error_handler
90b6238f
AM		 9125 (_("%pB(%s): warning: interworking not enabled;"
9126 " first occurrence: %pB: %s call to %s"),
9127 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
252b5132 9128
b34976b6 9129 return FALSE;
252b5132
RH		 9130 }
9131
9132 --my_offset;
9133 myh->root.u.def.value = my_offset;
9134
52ab56c2
PB		 9135 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
9136 s->contents + my_offset);
252b5132 9137
52ab56c2
PB		 9138 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
9139 s->contents + my_offset + 2);
252b5132
RH		 9140
9141 ret_offset =
9b485d32
NC		 9142 /* Address of destination of the stub. */
9143 ((bfd_signed_vma) val)
252b5132 9144 - ((bfd_signed_vma)
57e8b36a
NC		 9145 /* Offset from the start of the current section
9146 to the start of the stubs. */
9b485d32
NC		 9147 (s->output_offset
9148 /* Offset of the start of this stub from the start of the stubs. */
9149 + my_offset
9150 /* Address of the start of the current section. */
9151 + s->output_section->vma)
9152 /* The branch instruction is 4 bytes into the stub. */
9153 + 4
9154 /* ARM branches work from the pc of the instruction + 8. */
9155 + 8);
252b5132 9156
52ab56c2
PB		 9157 put_arm_insn (globals, output_bfd,
9158 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
9159 s->contents + my_offset + 4);
252b5132
RH		 9160 }
9161
9162 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
9163
427bfd90
NC		 9164 /* Now go back and fix up the original BL insn to point to here. */
9165 ret_offset =
9166 /* Address of where the stub is located. */
9167 (s->output_section->vma + s->output_offset + my_offset)
9168 /* Address of where the BL is located. */
57e8b36a
NC		 9169 - (input_section->output_section->vma + input_section->output_offset
9170 + offset)
427bfd90
NC		 9171 /* Addend in the relocation. */
9172 - addend
9173 /* Biassing for PC-relative addressing. */
9174 - 8;
252b5132 9175
12a0a0fd 9176 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 9177
b34976b6 9178 return TRUE;
252b5132
RH		 9179}
9180
a4fd1a8e 9181/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 9182
a4fd1a8e
PB		 9183static struct elf_link_hash_entry *
9184elf32_arm_create_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9185 const char * name,
9186 bfd * input_bfd,
9187 bfd * output_bfd,
9188 asection * sym_sec,
9189 bfd_vma val,
9190 asection * s,
9191 char ** error_message)
252b5132 9192{
dc810e39 9193 bfd_vma my_offset;
252b5132 9194 long int ret_offset;
bcbdc74c
NC		 9195 struct elf_link_hash_entry * myh;
9196 struct elf32_arm_link_hash_table * globals;
252b5132 9197
f2a9dd69 9198 myh = find_arm_glue (info, name, error_message);
252b5132 9199 if (myh == NULL)
a4fd1a8e 9200 return NULL;
252b5132
RH		 9201
9202 globals = elf32_arm_hash_table (info);
252b5132
RH		 9203 BFD_ASSERT (globals != NULL);
9204 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9205
9206 my_offset = myh->root.u.def.value;
252b5132
RH		 9207
9208 if ((my_offset & 0x01) == 0x01)
9209 {
9210 if (sym_sec != NULL
9211 && sym_sec->owner != NULL
9212 && !INTERWORK_FLAG (sym_sec->owner))
9213 {
4eca0228 9214 _bfd_error_handler
90b6238f
AM		 9215 (_("%pB(%s): warning: interworking not enabled;"
9216 " first occurrence: %pB: %s call to %s"),
9217 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
252b5132 9218 }
9b485d32 9219
252b5132
RH		 9220 --my_offset;
9221 myh->root.u.def.value = my_offset;
9222
0e1862bb
L		 9223 if (bfd_link_pic (info)
9224 || globals->root.is_relocatable_executable
27e55c4d 9225 || globals->pic_veneer)
8f6277f5
PB		 9226 {
9227 /* For relocatable objects we can't use absolute addresses,
9228 so construct the address from a relative offset. */
9229 /* TODO: If the offset is small it's probably worth
9230 constructing the address with adds. */
52ab56c2
PB		 9231 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
9232 s->contents + my_offset);
9233 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
9234 s->contents + my_offset + 4);
9235 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
9236 s->contents + my_offset + 8);
8f6277f5
PB		 9237 /* Adjust the offset by 4 for the position of the add,
9238 and 8 for the pipeline offset. */
9239 ret_offset = (val - (s->output_offset
9240 + s->output_section->vma
9241 + my_offset + 12))
9242 | 1;
9243 bfd_put_32 (output_bfd, ret_offset,
9244 s->contents + my_offset + 12);
9245 }
26079076
PB		 9246 else if (globals->use_blx)
9247 {
9248 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
9249 s->contents + my_offset);
9250
9251 /* It's a thumb address. Add the low order bit. */
9252 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
9253 s->contents + my_offset + 4);
9254 }
8f6277f5
PB		 9255 else
9256 {
52ab56c2
PB		 9257 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
9258 s->contents + my_offset);
252b5132 9259
52ab56c2
PB		 9260 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
9261 s->contents + my_offset + 4);
252b5132 9262
8f6277f5
PB		 9263 /* It's a thumb address. Add the low order bit. */
9264 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
9265 s->contents + my_offset + 8);
8029a119
NC		 9266
9267 my_offset += 12;
8f6277f5 9268 }
252b5132
RH		 9269 }
9270
9271 BFD_ASSERT (my_offset <= globals->arm_glue_size);
9272
a4fd1a8e
PB		 9273 return myh;
9274}
9275
9276/* Arm code calling a Thumb function. */
9277
9278static int
9279elf32_arm_to_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9280 const char * name,
9281 bfd * input_bfd,
9282 bfd * output_bfd,
9283 asection * input_section,
9284 bfd_byte * hit_data,
9285 asection * sym_sec,
9286 bfd_vma offset,
9287 bfd_signed_vma addend,
9288 bfd_vma val,
f2a9dd69 9289 char **error_message)
a4fd1a8e
PB		 9290{
9291 unsigned long int tmp;
9292 bfd_vma my_offset;
9293 asection * s;
9294 long int ret_offset;
9295 struct elf_link_hash_entry * myh;
9296 struct elf32_arm_link_hash_table * globals;
9297
9298 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9299 BFD_ASSERT (globals != NULL);
9300 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9301
3d4d4302
AM		 9302 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9303 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9304 BFD_ASSERT (s != NULL);
9305 BFD_ASSERT (s->contents != NULL);
9306 BFD_ASSERT (s->output_section != NULL);
9307
9308 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 9309 sym_sec, val, s, error_message);
a4fd1a8e
PB		 9310 if (!myh)
9311 return FALSE;
9312
9313 my_offset = myh->root.u.def.value;
252b5132
RH		 9314 tmp = bfd_get_32 (input_bfd, hit_data);
9315 tmp = tmp & 0xFF000000;
9316
9b485d32 9317 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9318 ret_offset = (s->output_offset
9319 + my_offset
9320 + s->output_section->vma
9321 - (input_section->output_offset
9322 + input_section->output_section->vma
9323 + offset + addend)
9324 - 8);
9a5aca8c 9325
252b5132
RH		 9326 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9327
dc810e39 9328 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9329
b34976b6 9330 return TRUE;
252b5132
RH		 9331}
9332
a4fd1a8e
PB		 9333/* Populate Arm stub for an exported Thumb function. */
9334
9335static bfd_boolean
9336elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9337{
9338 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9339 asection * s;
9340 struct elf_link_hash_entry * myh;
9341 struct elf32_arm_link_hash_entry *eh;
9342 struct elf32_arm_link_hash_table * globals;
9343 asection *sec;
9344 bfd_vma val;
f2a9dd69 9345 char *error_message;
a4fd1a8e 9346
906e58ca 9347 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9348 /* Allocate stubs for exported Thumb functions on v4t. */
9349 if (eh->export_glue == NULL)
9350 return TRUE;
9351
9352 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9353 BFD_ASSERT (globals != NULL);
9354 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9355
3d4d4302
AM		 9356 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9357 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9358 BFD_ASSERT (s != NULL);
9359 BFD_ASSERT (s->contents != NULL);
9360 BFD_ASSERT (s->output_section != NULL);
9361
9362 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9363
9364 BFD_ASSERT (sec->output_section != NULL);
9365
a4fd1a8e
PB		 9366 val = eh->export_glue->root.u.def.value + sec->output_offset
9367 + sec->output_section->vma;
8029a119 9368
a4fd1a8e
PB		 9369 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9370 h->root.u.def.section->owner,
f2a9dd69
DJ		 9371 globals->obfd, sec, val, s,
9372 &error_message);
a4fd1a8e
PB		 9373 BFD_ASSERT (myh);
9374 return TRUE;
9375}
9376
845b51d6
PB		 9377/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9378
9379static bfd_vma
9380elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9381{
9382 bfd_byte *p;
9383 bfd_vma glue_addr;
9384 asection *s;
9385 struct elf32_arm_link_hash_table *globals;
9386
9387 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9388 BFD_ASSERT (globals != NULL);
9389 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9390
3d4d4302
AM		 9391 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9392 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9393 BFD_ASSERT (s != NULL);
9394 BFD_ASSERT (s->contents != NULL);
9395 BFD_ASSERT (s->output_section != NULL);
9396
9397 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9398
9399 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9400
9401 if ((globals->bx_glue_offset[reg] & 1) == 0)
9402 {
9403 p = s->contents + glue_addr;
9404 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9405 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9406 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9407 globals->bx_glue_offset[reg] |= 1;
9408 }
9409
9410 return glue_addr + s->output_section->vma + s->output_offset;
9411}
9412
a4fd1a8e
PB		 9413/* Generate Arm stubs for exported Thumb symbols. */
9414static void
906e58ca 9415elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9416 struct bfd_link_info *link_info)
9417{
9418 struct elf32_arm_link_hash_table * globals;
9419
8029a119
NC		 9420 if (link_info == NULL)
9421 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9422 return;
9423
9424 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9425 if (globals == NULL)
9426 return;
9427
84c08195
PB		 9428 /* If blx is available then exported Thumb symbols are OK and there is
9429 nothing to do. */
a4fd1a8e
PB		 9430 if (globals->use_blx)
9431 return;
9432
9433 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9434 link_info);
9435}
9436
47beaa6a
RS		 9437/* Reserve space for COUNT dynamic relocations in relocation selection
9438 SRELOC. */
9439
9440static void
9441elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9442 bfd_size_type count)
9443{
9444 struct elf32_arm_link_hash_table *htab;
9445
9446 htab = elf32_arm_hash_table (info);
9447 BFD_ASSERT (htab->root.dynamic_sections_created);
9448 if (sreloc == NULL)
9449 abort ();
9450 sreloc->size += RELOC_SIZE (htab) * count;
9451}
9452
34e77a92
RS		 9453/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9454 dynamic, the relocations should go in SRELOC, otherwise they should
9455 go in the special .rel.iplt section. */
9456
9457static void
9458elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9459 bfd_size_type count)
9460{
9461 struct elf32_arm_link_hash_table *htab;
9462
9463 htab = elf32_arm_hash_table (info);
9464 if (!htab->root.dynamic_sections_created)
9465 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9466 else
9467 {
9468 BFD_ASSERT (sreloc != NULL);
9469 sreloc->size += RELOC_SIZE (htab) * count;
9470 }
9471}
9472
47beaa6a
RS		 9473/* Add relocation REL to the end of relocation section SRELOC. */
9474
9475static void
9476elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9477 asection *sreloc, Elf_Internal_Rela *rel)
9478{
9479 bfd_byte *loc;
9480 struct elf32_arm_link_hash_table *htab;
9481
9482 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9483 if (!htab->root.dynamic_sections_created
9484 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9485 sreloc = htab->root.irelplt;
47beaa6a
RS		 9486 if (sreloc == NULL)
9487 abort ();
9488 loc = sreloc->contents;
9489 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9490 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9491 abort ();
9492 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9493}
9494
34e77a92
RS		 9495/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9496 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9497 to .plt. */
9498
9499static void
9500elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9501 bfd_boolean is_iplt_entry,
9502 union gotplt_union *root_plt,
9503 struct arm_plt_info *arm_plt)
9504{
9505 struct elf32_arm_link_hash_table *htab;
9506 asection *splt;
9507 asection *sgotplt;
9508
9509 htab = elf32_arm_hash_table (info);
9510
9511 if (is_iplt_entry)
9512 {
9513 splt = htab->root.iplt;
9514 sgotplt = htab->root.igotplt;
9515
99059e56
RM		 9516 /* NaCl uses a special first entry in .iplt too. */
9517 if (htab->nacl_p && splt->size == 0)
9518 splt->size += htab->plt_header_size;
9519
34e77a92
RS		 9520 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9521 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9522 }
9523 else
9524 {
9525 splt = htab->root.splt;
9526 sgotplt = htab->root.sgotplt;
9527
7801f98f
CL		 9528 if (htab->fdpic_p)
9529 {
9530 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9531 /* For lazy binding, relocations will be put into .rel.plt, in
9532 .rel.got otherwise. */
9533 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9534 if (info->flags & DF_BIND_NOW)
9535 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
9536 else
9537 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9538 }
9539 else
9540 {
9541 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9542 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9543 }
34e77a92
RS		 9544
9545 /* If this is the first .plt entry, make room for the special
9546 first entry. */
9547 if (splt->size == 0)
9548 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9549
9550 htab->next_tls_desc_index++;
34e77a92
RS		 9551 }
9552
9553 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9554 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9555 splt->size += PLT_THUMB_STUB_SIZE;
9556 root_plt->offset = splt->size;
9557 splt->size += htab->plt_entry_size;
9558
9559 if (!htab->symbian_p)
9560 {
9561 /* We also need to make an entry in the .got.plt section, which
9562 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9563 if (is_iplt_entry)
9564 arm_plt->got_offset = sgotplt->size;
9565 else
9566 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
7801f98f
CL		 9567 if (htab->fdpic_p)
9568 /* Function descriptor takes 64 bits in GOT. */
4b24dd1a 9569 sgotplt->size += 8;
7801f98f
CL		 9570 else
9571 sgotplt->size += 4;
34e77a92
RS		 9572 }
9573}
9574
b38cadfb
NC		 9575static bfd_vma
9576arm_movw_immediate (bfd_vma value)
9577{
9578 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9579}
9580
9581static bfd_vma
9582arm_movt_immediate (bfd_vma value)
9583{
9584 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9585}
9586
34e77a92
RS		 9587/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9588 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9589 Otherwise, DYNINDX is the index of the symbol in the dynamic
9590 symbol table and SYM_VALUE is undefined.
9591
9592 ROOT_PLT points to the offset of the PLT entry from the start of its
9593 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9594 bookkeeping information.
34e77a92 9595
57460bcf
NC		 9596 Returns FALSE if there was a problem. */
9597
9598static bfd_boolean
34e77a92
RS		 9599elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9600 union gotplt_union *root_plt,
9601 struct arm_plt_info *arm_plt,
9602 int dynindx, bfd_vma sym_value)
9603{
9604 struct elf32_arm_link_hash_table *htab;
9605 asection *sgot;
9606 asection *splt;
9607 asection *srel;
9608 bfd_byte *loc;
9609 bfd_vma plt_index;
9610 Elf_Internal_Rela rel;
9611 bfd_vma plt_header_size;
9612 bfd_vma got_header_size;
9613
9614 htab = elf32_arm_hash_table (info);
9615
9616 /* Pick the appropriate sections and sizes. */
9617 if (dynindx == -1)
9618 {
9619 splt = htab->root.iplt;
9620 sgot = htab->root.igotplt;
9621 srel = htab->root.irelplt;
9622
9623 /* There are no reserved entries in .igot.plt, and no special
9624 first entry in .iplt. */
9625 got_header_size = 0;
9626 plt_header_size = 0;
9627 }
9628 else
9629 {
9630 splt = htab->root.splt;
9631 sgot = htab->root.sgotplt;
9632 srel = htab->root.srelplt;
9633
9634 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9635 plt_header_size = htab->plt_header_size;
9636 }
9637 BFD_ASSERT (splt != NULL && srel != NULL);
9638
9639 /* Fill in the entry in the procedure linkage table. */
9640 if (htab->symbian_p)
9641 {
9642 BFD_ASSERT (dynindx >= 0);
9643 put_arm_insn (htab, output_bfd,
9644 elf32_arm_symbian_plt_entry[0],
9645 splt->contents + root_plt->offset);
9646 bfd_put_32 (output_bfd,
9647 elf32_arm_symbian_plt_entry[1],
9648 splt->contents + root_plt->offset + 4);
9649
9650 /* Fill in the entry in the .rel.plt section. */
9651 rel.r_offset = (splt->output_section->vma
9652 + splt->output_offset
9653 + root_plt->offset + 4);
9654 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9655
9656 /* Get the index in the procedure linkage table which
9657 corresponds to this symbol. This is the index of this symbol
9658 in all the symbols for which we are making plt entries. The
9659 first entry in the procedure linkage table is reserved. */
9660 plt_index = ((root_plt->offset - plt_header_size)
9661 / htab->plt_entry_size);
9662 }
9663 else
9664 {
9665 bfd_vma got_offset, got_address, plt_address;
9666 bfd_vma got_displacement, initial_got_entry;
9667 bfd_byte * ptr;
9668
9669 BFD_ASSERT (sgot != NULL);
9670
9671 /* Get the offset into the .(i)got.plt table of the entry that
9672 corresponds to this function. */
9673 got_offset = (arm_plt->got_offset & -2);
9674
9675 /* Get the index in the procedure linkage table which
9676 corresponds to this symbol. This is the index of this symbol
9677 in all the symbols for which we are making plt entries.
9678 After the reserved .got.plt entries, all symbols appear in
9679 the same order as in .plt. */
7801f98f 9680 if (htab->fdpic_p)
4b24dd1a
AM		 9681 /* Function descriptor takes 8 bytes. */
9682 plt_index = (got_offset - got_header_size) / 8;
7801f98f 9683 else
4b24dd1a 9684 plt_index = (got_offset - got_header_size) / 4;
34e77a92
RS		 9685
9686 /* Calculate the address of the GOT entry. */
9687 got_address = (sgot->output_section->vma
9688 + sgot->output_offset
9689 + got_offset);
9690
9691 /* ...and the address of the PLT entry. */
9692 plt_address = (splt->output_section->vma
9693 + splt->output_offset
9694 + root_plt->offset);
9695
9696 ptr = splt->contents + root_plt->offset;
0e1862bb 9697 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9698 {
9699 unsigned int i;
9700 bfd_vma val;
9701
9702 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9703 {
9704 val = elf32_arm_vxworks_shared_plt_entry[i];
9705 if (i == 2)
9706 val |= got_address - sgot->output_section->vma;
9707 if (i == 5)
9708 val |= plt_index * RELOC_SIZE (htab);
9709 if (i == 2 || i == 5)
9710 bfd_put_32 (output_bfd, val, ptr);
9711 else
9712 put_arm_insn (htab, output_bfd, val, ptr);
9713 }
9714 }
9715 else if (htab->vxworks_p)
9716 {
9717 unsigned int i;
9718 bfd_vma val;
9719
9720 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9721 {
9722 val = elf32_arm_vxworks_exec_plt_entry[i];
9723 if (i == 2)
9724 val |= got_address;
9725 if (i == 4)
9726 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9727 if (i == 5)
9728 val |= plt_index * RELOC_SIZE (htab);
9729 if (i == 2 || i == 5)
9730 bfd_put_32 (output_bfd, val, ptr);
9731 else
9732 put_arm_insn (htab, output_bfd, val, ptr);
9733 }
9734
9735 loc = (htab->srelplt2->contents
9736 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9737
9738 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9739 referencing the GOT for this PLT entry. */
9740 rel.r_offset = plt_address + 8;
9741 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9742 rel.r_addend = got_offset;
9743 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9744 loc += RELOC_SIZE (htab);
9745
9746 /* Create the R_ARM_ABS32 relocation referencing the
9747 beginning of the PLT for this GOT entry. */
9748 rel.r_offset = got_address;
9749 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9750 rel.r_addend = 0;
9751 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9752 }
b38cadfb
NC		 9753 else if (htab->nacl_p)
9754 {
9755 /* Calculate the displacement between the PLT slot and the
9756 common tail that's part of the special initial PLT slot. */
6034aab8 9757 int32_t tail_displacement
b38cadfb
NC		 9758 = ((splt->output_section->vma + splt->output_offset
9759 + ARM_NACL_PLT_TAIL_OFFSET)
9760 - (plt_address + htab->plt_entry_size + 4));
9761 BFD_ASSERT ((tail_displacement & 3) == 0);
9762 tail_displacement >>= 2;
9763
9764 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9765 || (-tail_displacement & 0xff000000) == 0);
9766
9767 /* Calculate the displacement between the PLT slot and the entry
9768 in the GOT. The offset accounts for the value produced by
9769 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9770 got_displacement = (got_address
99059e56 9771 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9772
9773 /* NaCl does not support interworking at all. */
9774 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9775
9776 put_arm_insn (htab, output_bfd,
9777 elf32_arm_nacl_plt_entry[0]
9778 | arm_movw_immediate (got_displacement),
9779 ptr + 0);
9780 put_arm_insn (htab, output_bfd,
9781 elf32_arm_nacl_plt_entry[1]
9782 | arm_movt_immediate (got_displacement),
9783 ptr + 4);
9784 put_arm_insn (htab, output_bfd,
9785 elf32_arm_nacl_plt_entry[2],
9786 ptr + 8);
9787 put_arm_insn (htab, output_bfd,
9788 elf32_arm_nacl_plt_entry[3]
9789 | (tail_displacement & 0x00ffffff),
9790 ptr + 12);
9791 }
7801f98f
CL		 9792 else if (htab->fdpic_p)
9793 {
59029f57
CL		 9794 const bfd_vma *plt_entry = using_thumb_only(htab)
9795 ? elf32_arm_fdpic_thumb_plt_entry
9796 : elf32_arm_fdpic_plt_entry;
9797
7801f98f
CL		 9798 /* Fill-up Thumb stub if needed. */
9799 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9800 {
9801 put_thumb_insn (htab, output_bfd,
9802 elf32_arm_plt_thumb_stub[0], ptr - 4);
9803 put_thumb_insn (htab, output_bfd,
9804 elf32_arm_plt_thumb_stub[1], ptr - 2);
9805 }
59029f57
CL		 9806 /* As we are using 32 bit instructions even for the Thumb
9807 version, we have to use 'put_arm_insn' instead of
9808 'put_thumb_insn'. */
9809 put_arm_insn(htab, output_bfd, plt_entry[0], ptr + 0);
9810 put_arm_insn(htab, output_bfd, plt_entry[1], ptr + 4);
9811 put_arm_insn(htab, output_bfd, plt_entry[2], ptr + 8);
9812 put_arm_insn(htab, output_bfd, plt_entry[3], ptr + 12);
7801f98f
CL		 9813 bfd_put_32 (output_bfd, got_offset, ptr + 16);
9814
9815 if (!(info->flags & DF_BIND_NOW))
9816 {
9817 /* funcdesc_value_reloc_offset. */
9818 bfd_put_32 (output_bfd,
9819 htab->root.srelplt->reloc_count * RELOC_SIZE (htab),
9820 ptr + 20);
59029f57
CL		 9821 put_arm_insn(htab, output_bfd, plt_entry[6], ptr + 24);
9822 put_arm_insn(htab, output_bfd, plt_entry[7], ptr + 28);
9823 put_arm_insn(htab, output_bfd, plt_entry[8], ptr + 32);
9824 put_arm_insn(htab, output_bfd, plt_entry[9], ptr + 36);
7801f98f
CL		 9825 }
9826 }
57460bcf
NC		 9827 else if (using_thumb_only (htab))
9828 {
eed94f8f 9829 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9830 if (!using_thumb2 (htab))
eed94f8f
NC		 9831 {
9832 /* FIXME: We ought to be able to generate thumb-1 PLT
9833 instructions... */
90b6238f 9834 _bfd_error_handler (_("%pB: warning: thumb-1 mode PLT generation not currently supported"),
eed94f8f
NC		 9835 output_bfd);
9836 return FALSE;
9837 }
57460bcf 9838
eed94f8f
NC		 9839 /* Calculate the displacement between the PLT slot and the entry in
9840 the GOT. The 12-byte offset accounts for the value produced by
9841 adding to pc in the 3rd instruction of the PLT stub. */
9842 got_displacement = got_address - (plt_address + 12);
9843
9844 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9845 instead of 'put_thumb_insn'. */
9846 put_arm_insn (htab, output_bfd,
9847 elf32_thumb2_plt_entry[0]
9848 | ((got_displacement & 0x000000ff) << 16)
9849 | ((got_displacement & 0x00000700) << 20)
9850 | ((got_displacement & 0x00000800) >> 1)
9851 | ((got_displacement & 0x0000f000) >> 12),
9852 ptr + 0);
9853 put_arm_insn (htab, output_bfd,
9854 elf32_thumb2_plt_entry[1]
9855 | ((got_displacement & 0x00ff0000) )
9856 | ((got_displacement & 0x07000000) << 4)
9857 | ((got_displacement & 0x08000000) >> 17)
9858 | ((got_displacement & 0xf0000000) >> 28),
9859 ptr + 4);
9860 put_arm_insn (htab, output_bfd,
9861 elf32_thumb2_plt_entry[2],
9862 ptr + 8);
9863 put_arm_insn (htab, output_bfd,
9864 elf32_thumb2_plt_entry[3],
9865 ptr + 12);
57460bcf 9866 }
34e77a92
RS		 9867 else
9868 {
9869 /* Calculate the displacement between the PLT slot and the
9870 entry in the GOT. The eight-byte offset accounts for the
9871 value produced by adding to pc in the first instruction
9872 of the PLT stub. */
9873 got_displacement = got_address - (plt_address + 8);
9874
34e77a92
RS		 9875 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9876 {
9877 put_thumb_insn (htab, output_bfd,
9878 elf32_arm_plt_thumb_stub[0], ptr - 4);
9879 put_thumb_insn (htab, output_bfd,
9880 elf32_arm_plt_thumb_stub[1], ptr - 2);
9881 }
9882
1db37fe6
YG		 9883 if (!elf32_arm_use_long_plt_entry)
9884 {
9885 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9886
9887 put_arm_insn (htab, output_bfd,
9888 elf32_arm_plt_entry_short[0]
9889 | ((got_displacement & 0x0ff00000) >> 20),
9890 ptr + 0);
9891 put_arm_insn (htab, output_bfd,
9892 elf32_arm_plt_entry_short[1]
9893 | ((got_displacement & 0x000ff000) >> 12),
9894 ptr+ 4);
9895 put_arm_insn (htab, output_bfd,
9896 elf32_arm_plt_entry_short[2]
9897 | (got_displacement & 0x00000fff),
9898 ptr + 8);
34e77a92 9899#ifdef FOUR_WORD_PLT
1db37fe6 9900 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9901#endif
1db37fe6
YG		 9902 }
9903 else
9904 {
9905 put_arm_insn (htab, output_bfd,
9906 elf32_arm_plt_entry_long[0]
9907 | ((got_displacement & 0xf0000000) >> 28),
9908 ptr + 0);
9909 put_arm_insn (htab, output_bfd,
9910 elf32_arm_plt_entry_long[1]
9911 | ((got_displacement & 0x0ff00000) >> 20),
9912 ptr + 4);
9913 put_arm_insn (htab, output_bfd,
9914 elf32_arm_plt_entry_long[2]
9915 | ((got_displacement & 0x000ff000) >> 12),
9916 ptr+ 8);
9917 put_arm_insn (htab, output_bfd,
9918 elf32_arm_plt_entry_long[3]
9919 | (got_displacement & 0x00000fff),
9920 ptr + 12);
9921 }
34e77a92
RS		 9922 }
9923
9924 /* Fill in the entry in the .rel(a).(i)plt section. */
9925 rel.r_offset = got_address;
9926 rel.r_addend = 0;
9927 if (dynindx == -1)
9928 {
9929 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9930 The dynamic linker or static executable then calls SYM_VALUE
9931 to determine the correct run-time value of the .igot.plt entry. */
9932 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9933 initial_got_entry = sym_value;
9934 }
9935 else
9936 {
7801f98f
CL		 9937 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9938 used by PLT entry. */
9939 if (htab->fdpic_p)
9940 {
9941 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
9942 initial_got_entry = 0;
9943 }
9944 else
9945 {
9946 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9947 initial_got_entry = (splt->output_section->vma
9948 + splt->output_offset);
9949 }
34e77a92
RS		 9950 }
9951
9952 /* Fill in the entry in the global offset table. */
9953 bfd_put_32 (output_bfd, initial_got_entry,
9954 sgot->contents + got_offset);
7801f98f
CL		 9955
9956 if (htab->fdpic_p && !(info->flags & DF_BIND_NOW))
9957 {
9958 /* Setup initial funcdesc value. */
9959 /* FIXME: we don't support lazy binding because there is a
9960 race condition between both words getting written and
9961 some other thread attempting to read them. The ARM
9962 architecture does not have an atomic 64 bit load/store
9963 instruction that could be used to prevent it; it is
9964 recommended that threaded FDPIC applications run with the
9965 LD_BIND_NOW environment variable set. */
9966 bfd_put_32(output_bfd, plt_address + 0x18,
9967 sgot->contents + got_offset);
9968 bfd_put_32(output_bfd, -1 /*TODO*/,
9969 sgot->contents + got_offset + 4);
9970 }
34e77a92
RS		 9971 }
9972
aba8c3de
WN		 9973 if (dynindx == -1)
9974 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9975 else
9976 {
7801f98f
CL		 9977 if (htab->fdpic_p)
9978 {
9979 /* For FDPIC we put PLT relocationss into .rel.got when not
9980 lazy binding otherwise we put them in .rel.plt. For now,
9981 we don't support lazy binding so put it in .rel.got. */
9982 if (info->flags & DF_BIND_NOW)
9983 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelgot, &rel);
9984 else
9985 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelplt, &rel);
9986 }
9987 else
9988 {
9989 loc = srel->contents + plt_index * RELOC_SIZE (htab);
9990 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9991 }
aba8c3de 9992 }
57460bcf
NC		 9993
9994 return TRUE;
34e77a92
RS		 9995}
9996
eb043451
PB		 9997/* Some relocations map to different relocations depending on the
9998 target. Return the real relocation. */
8029a119 9999
eb043451
PB		 10000static int
10001arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
10002 int r_type)
10003{
10004 switch (r_type)
10005 {
10006 case R_ARM_TARGET1:
10007 if (globals->target1_is_rel)
10008 return R_ARM_REL32;
10009 else
10010 return R_ARM_ABS32;
10011
10012 case R_ARM_TARGET2:
10013 return globals->target2_reloc;
10014
10015 default:
10016 return r_type;
10017 }
10018}
eb043451 10019
ba93b8ac
DJ		 10020/* Return the base VMA address which should be subtracted from real addresses
10021 when resolving @dtpoff relocation.
10022 This is PT_TLS segment p_vaddr. */
10023
10024static bfd_vma
10025dtpoff_base (struct bfd_link_info *info)
10026{
10027 /* If tls_sec is NULL, we should have signalled an error already. */
10028 if (elf_hash_table (info)->tls_sec == NULL)
10029 return 0;
10030 return elf_hash_table (info)->tls_sec->vma;
10031}
10032
10033/* Return the relocation value for @tpoff relocation
10034 if STT_TLS virtual address is ADDRESS. */
10035
10036static bfd_vma
10037tpoff (struct bfd_link_info *info, bfd_vma address)
10038{
10039 struct elf_link_hash_table *htab = elf_hash_table (info);
10040 bfd_vma base;
10041
10042 /* If tls_sec is NULL, we should have signalled an error already. */
10043 if (htab->tls_sec == NULL)
10044 return 0;
10045 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
10046 return address - htab->tls_sec->vma + base;
10047}
10048
00a97672
RS		 10049/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10050 VALUE is the relocation value. */
10051
10052static bfd_reloc_status_type
10053elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
10054{
10055 if (value > 0xfff)
10056 return bfd_reloc_overflow;
10057
10058 value |= bfd_get_32 (abfd, data) & 0xfffff000;
10059 bfd_put_32 (abfd, value, data);
10060 return bfd_reloc_ok;
10061}
10062
0855e32b
NS		 10063/* Handle TLS relaxations. Relaxing is possible for symbols that use
10064 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10065 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10066
10067 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10068 is to then call final_link_relocate. Return other values in the
62672b10
NS		 10069 case of error.
10070
10071 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10072 the pre-relaxed code. It would be nice if the relocs were updated
10073 to match the optimization. */
0855e32b 10074
b38cadfb 10075static bfd_reloc_status_type
0855e32b 10076elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 10077 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 10078 Elf_Internal_Rela *rel, unsigned long is_local)
10079{
10080 unsigned long insn;
b38cadfb 10081
0855e32b
NS		 10082 switch (ELF32_R_TYPE (rel->r_info))
10083 {
10084 default:
10085 return bfd_reloc_notsupported;
b38cadfb 10086
0855e32b
NS		 10087 case R_ARM_TLS_GOTDESC:
10088 if (is_local)
10089 insn = 0;
10090 else
10091 {
10092 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10093 if (insn & 1)
10094 insn -= 5; /* THUMB */
10095 else
10096 insn -= 8; /* ARM */
10097 }
10098 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10099 return bfd_reloc_continue;
10100
10101 case R_ARM_THM_TLS_DESCSEQ:
10102 /* Thumb insn. */
10103 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
10104 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
10105 {
10106 if (is_local)
10107 /* nop */
10108 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10109 }
10110 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
10111 {
10112 if (is_local)
10113 /* nop */
10114 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10115 else
10116 /* ldr rx,[ry] */
10117 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
10118 }
10119 else if ((insn & 0xff87) == 0x4780) /* blx rx */
10120 {
10121 if (is_local)
10122 /* nop */
10123 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10124 else
10125 /* mov r0, rx */
10126 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
10127 contents + rel->r_offset);
10128 }
10129 else
10130 {
10131 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10132 /* It's a 32 bit instruction, fetch the rest of it for
10133 error generation. */
10134 insn = (insn << 16)
10135 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 10136 _bfd_error_handler
695344c0 10137 /* xgettext:c-format */
2dcf00ce 10138 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10139 "unexpected %s instruction '%#lx' in TLS trampoline"),
10140 input_bfd, input_sec, (uint64_t) rel->r_offset,
10141 "Thumb", insn);
0855e32b
NS		 10142 return bfd_reloc_notsupported;
10143 }
10144 break;
b38cadfb 10145
0855e32b
NS		 10146 case R_ARM_TLS_DESCSEQ:
10147 /* arm insn. */
10148 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10149 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
10150 {
10151 if (is_local)
10152 /* mov rx, ry */
10153 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
10154 contents + rel->r_offset);
10155 }
10156 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
10157 {
10158 if (is_local)
10159 /* nop */
10160 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10161 else
10162 /* ldr rx,[ry] */
10163 bfd_put_32 (input_bfd, insn & 0xfffff000,
10164 contents + rel->r_offset);
10165 }
10166 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
10167 {
10168 if (is_local)
10169 /* nop */
10170 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10171 else
10172 /* mov r0, rx */
10173 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
10174 contents + rel->r_offset);
10175 }
10176 else
10177 {
4eca0228 10178 _bfd_error_handler
695344c0 10179 /* xgettext:c-format */
2dcf00ce 10180 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10181 "unexpected %s instruction '%#lx' in TLS trampoline"),
10182 input_bfd, input_sec, (uint64_t) rel->r_offset,
10183 "ARM", insn);
0855e32b
NS		 10184 return bfd_reloc_notsupported;
10185 }
10186 break;
10187
10188 case R_ARM_TLS_CALL:
10189 /* GD->IE relaxation, turn the instruction into 'nop' or
10190 'ldr r0, [pc,r0]' */
10191 insn = is_local ? 0xe1a00000 : 0xe79f0000;
10192 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10193 break;
b38cadfb 10194
0855e32b 10195 case R_ARM_THM_TLS_CALL:
6a631e86 10196 /* GD->IE relaxation. */
0855e32b
NS		 10197 if (!is_local)
10198 /* add r0,pc; ldr r0, [r0] */
10199 insn = 0x44786800;
60a019a0 10200 else if (using_thumb2 (globals))
0855e32b
NS		 10201 /* nop.w */
10202 insn = 0xf3af8000;
10203 else
10204 /* nop; nop */
10205 insn = 0xbf00bf00;
b38cadfb 10206
0855e32b
NS		 10207 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
10208 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
10209 break;
10210 }
10211 return bfd_reloc_ok;
10212}
10213
4962c51a
MS		 10214/* For a given value of n, calculate the value of G_n as required to
10215 deal with group relocations. We return it in the form of an
10216 encoded constant-and-rotation, together with the final residual. If n is
10217 specified as less than zero, then final_residual is filled with the
10218 input value and no further action is performed. */
10219
10220static bfd_vma
10221calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
10222{
10223 int current_n;
10224 bfd_vma g_n;
10225 bfd_vma encoded_g_n = 0;
10226 bfd_vma residual = value; /* Also known as Y_n. */
10227
10228 for (current_n = 0; current_n <= n; current_n++)
10229 {
10230 int shift;
10231
10232 /* Calculate which part of the value to mask. */
10233 if (residual == 0)
99059e56 10234 shift = 0;
4962c51a 10235 else
99059e56
RM		 10236 {
10237 int msb;
10238
10239 /* Determine the most significant bit in the residual and
10240 align the resulting value to a 2-bit boundary. */
10241 for (msb = 30; msb >= 0; msb -= 2)
10242 if (residual & (3 << msb))
10243 break;
10244
10245 /* The desired shift is now (msb - 6), or zero, whichever
10246 is the greater. */
10247 shift = msb - 6;
10248 if (shift < 0)
10249 shift = 0;
10250 }
4962c51a
MS		 10251
10252 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10253 g_n = residual & (0xff << shift);
10254 encoded_g_n = (g_n >> shift)
99059e56 10255 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 10256
10257 /* Calculate the residual for the next time around. */
10258 residual &= ~g_n;
10259 }
10260
10261 *final_residual = residual;
10262
10263 return encoded_g_n;
10264}
10265
10266/* Given an ARM instruction, determine whether it is an ADD or a SUB.
10267 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 10268
4962c51a 10269static int
906e58ca 10270identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 10271{
10272 int opcode = insn & 0x1e00000;
10273
10274 if (opcode == 1 << 23) /* ADD */
10275 return 1;
10276
10277 if (opcode == 1 << 22) /* SUB */
10278 return -1;
10279
10280 return 0;
10281}
10282
e5d6e09e
AV		 10283/* Helper function to compute the Addend for Armv8.1-M Mainline relocations. */
10284static bfd_vma
10285get_value_helper (bfd_vma plt_offset,
10286 asection *splt,
10287 asection *input_section,
10288 asection *sym_sec,
10289 struct elf_link_hash_entry * h,
10290 struct bfd_link_info *info,
10291 bfd *input_bfd,
10292 Elf_Internal_Rela *rel,
10293 const char *sym_name,
10294 unsigned char st_type,
10295 struct elf32_arm_link_hash_table *globals,
10296 bfd_boolean *unresolved_reloc_p)
10297{
10298 bfd_vma value = 0;
10299 enum arm_st_branch_type branch_type;
10300 enum elf32_arm_stub_type stub_type = arm_stub_none;
10301 struct elf32_arm_stub_hash_entry *stub_entry;
10302 struct elf32_arm_link_hash_entry *hash
10303 = (struct elf32_arm_link_hash_entry *)h;
10304
10305
10306 if (plt_offset != (bfd_vma) -1)
10307 {
10308 value = (splt->output_section->vma
10309 + splt->output_offset
10310 + plt_offset);
10311 value -= PLT_THUMB_STUB_SIZE;
10312 *unresolved_reloc_p = FALSE;
10313 }
10314
10315 stub_type = arm_type_of_stub (info, input_section, rel,
10316 st_type, &branch_type,
10317 hash, value, sym_sec,
10318 input_bfd, sym_name);
10319
10320 if (stub_type != arm_stub_none)
10321 {
10322 stub_entry = elf32_arm_get_stub_entry (input_section,
10323 sym_sec, h,
10324 rel, globals,
10325 stub_type);
10326 if (stub_entry != NULL)
10327 {
10328 value = (stub_entry->stub_offset
10329 + stub_entry->stub_sec->output_offset
10330 + stub_entry->stub_sec->output_section->vma);
10331 }
10332 }
10333 return value;
10334}
10335
252b5132 10336/* Perform a relocation as part of a final link. */
9b485d32 10337
252b5132 10338static bfd_reloc_status_type
07d6d2b8
AM		 10339elf32_arm_final_link_relocate (reloc_howto_type * howto,
10340 bfd * input_bfd,
10341 bfd * output_bfd,
10342 asection * input_section,
10343 bfd_byte * contents,
10344 Elf_Internal_Rela * rel,
10345 bfd_vma value,
10346 struct bfd_link_info * info,
10347 asection * sym_sec,
10348 const char * sym_name,
10349 unsigned char st_type,
10350 enum arm_st_branch_type branch_type,
0945cdfd 10351 struct elf_link_hash_entry * h,
07d6d2b8
AM		 10352 bfd_boolean * unresolved_reloc_p,
10353 char ** error_message)
10354{
10355 unsigned long r_type = howto->type;
10356 unsigned long r_symndx;
10357 bfd_byte * hit_data = contents + rel->r_offset;
10358 bfd_vma * local_got_offsets;
10359 bfd_vma * local_tlsdesc_gotents;
10360 asection * sgot;
10361 asection * splt;
10362 asection * sreloc = NULL;
10363 asection * srelgot;
10364 bfd_vma addend;
10365 bfd_signed_vma signed_addend;
10366 unsigned char dynreloc_st_type;
10367 bfd_vma dynreloc_value;
ba96a88f 10368 struct elf32_arm_link_hash_table * globals;
34e77a92 10369 struct elf32_arm_link_hash_entry *eh;
07d6d2b8
AM		 10370 union gotplt_union *root_plt;
10371 struct arm_plt_info *arm_plt;
10372 bfd_vma plt_offset;
10373 bfd_vma gotplt_offset;
10374 bfd_boolean has_iplt_entry;
10375 bfd_boolean resolved_to_zero;
f21f3fe0 10376
9c504268 10377 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 10378 if (globals == NULL)
10379 return bfd_reloc_notsupported;
9c504268 10380
0ffa91dd 10381 BFD_ASSERT (is_arm_elf (input_bfd));
47aeb64c 10382 BFD_ASSERT (howto != NULL);
0ffa91dd
NC		 10383
10384 /* Some relocation types map to different relocations depending on the
9c504268 10385 target. We pick the right one here. */
eb043451 10386 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 10387
10388 /* It is possible to have linker relaxations on some TLS access
10389 models. Update our information here. */
10390 r_type = elf32_arm_tls_transition (info, r_type, h);
10391
eb043451
PB		 10392 if (r_type != howto->type)
10393 howto = elf32_arm_howto_from_type (r_type);
9c504268 10394
34e77a92 10395 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 10396 sgot = globals->root.sgot;
252b5132 10397 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 10398 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
10399
34e77a92
RS		 10400 if (globals->root.dynamic_sections_created)
10401 srelgot = globals->root.srelgot;
10402 else
10403 srelgot = NULL;
10404
252b5132
RH		 10405 r_symndx = ELF32_R_SYM (rel->r_info);
10406
4e7fd91e 10407 if (globals->use_rel)
ba96a88f 10408 {
4e7fd91e
PB		 10409 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
10410
10411 if (addend & ((howto->src_mask + 1) >> 1))
10412 {
10413 signed_addend = -1;
10414 signed_addend &= ~ howto->src_mask;
10415 signed_addend |= addend;
10416 }
10417 else
10418 signed_addend = addend;
ba96a88f
NC		 10419 }
10420 else
4e7fd91e 10421 addend = signed_addend = rel->r_addend;
f21f3fe0 10422
39f21624
NC		 10423 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10424 are resolving a function call relocation. */
10425 if (using_thumb_only (globals)
10426 && (r_type == R_ARM_THM_CALL
10427 || r_type == R_ARM_THM_JUMP24)
10428 && branch_type == ST_BRANCH_TO_ARM)
10429 branch_type = ST_BRANCH_TO_THUMB;
10430
34e77a92
RS		 10431 /* Record the symbol information that should be used in dynamic
10432 relocations. */
10433 dynreloc_st_type = st_type;
10434 dynreloc_value = value;
10435 if (branch_type == ST_BRANCH_TO_THUMB)
10436 dynreloc_value |= 1;
10437
10438 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10439 VALUE appropriately for relocations that we resolve at link time. */
10440 has_iplt_entry = FALSE;
4ba2ef8f
TP		 10441 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
10442 &arm_plt)
34e77a92
RS		 10443 && root_plt->offset != (bfd_vma) -1)
10444 {
10445 plt_offset = root_plt->offset;
10446 gotplt_offset = arm_plt->got_offset;
10447
10448 if (h == NULL || eh->is_iplt)
10449 {
10450 has_iplt_entry = TRUE;
10451 splt = globals->root.iplt;
10452
10453 /* Populate .iplt entries here, because not all of them will
10454 be seen by finish_dynamic_symbol. The lower bit is set if
10455 we have already populated the entry. */
10456 if (plt_offset & 1)
10457 plt_offset--;
10458 else
10459 {
57460bcf
NC		 10460 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
10461 -1, dynreloc_value))
10462 root_plt->offset |= 1;
10463 else
10464 return bfd_reloc_notsupported;
34e77a92
RS		 10465 }
10466
10467 /* Static relocations always resolve to the .iplt entry. */
10468 st_type = STT_FUNC;
10469 value = (splt->output_section->vma
10470 + splt->output_offset
10471 + plt_offset);
10472 branch_type = ST_BRANCH_TO_ARM;
10473
10474 /* If there are non-call relocations that resolve to the .iplt
10475 entry, then all dynamic ones must too. */
10476 if (arm_plt->noncall_refcount != 0)
10477 {
10478 dynreloc_st_type = st_type;
10479 dynreloc_value = value;
10480 }
10481 }
10482 else
10483 /* We populate the .plt entry in finish_dynamic_symbol. */
10484 splt = globals->root.splt;
10485 }
10486 else
10487 {
10488 splt = NULL;
10489 plt_offset = (bfd_vma) -1;
10490 gotplt_offset = (bfd_vma) -1;
10491 }
10492
95b03e4a
L		 10493 resolved_to_zero = (h != NULL
10494 && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
10495
252b5132
RH		 10496 switch (r_type)
10497 {
10498 case R_ARM_NONE:
28a094c2
DJ		 10499 /* We don't need to find a value for this symbol. It's just a
10500 marker. */
10501 *unresolved_reloc_p = FALSE;
252b5132
RH		 10502 return bfd_reloc_ok;
10503
00a97672
RS		 10504 case R_ARM_ABS12:
10505 if (!globals->vxworks_p)
10506 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10507 /* Fall through. */
00a97672 10508
252b5132
RH		 10509 case R_ARM_PC24:
10510 case R_ARM_ABS32:
bb224fc3 10511 case R_ARM_ABS32_NOI:
252b5132 10512 case R_ARM_REL32:
bb224fc3 10513 case R_ARM_REL32_NOI:
5b5bb741
PB		 10514 case R_ARM_CALL:
10515 case R_ARM_JUMP24:
dfc5f959 10516 case R_ARM_XPC25:
eb043451 10517 case R_ARM_PREL31:
7359ea65 10518 case R_ARM_PLT32:
7359ea65
DJ		 10519 /* Handle relocations which should use the PLT entry. ABS32/REL32
10520 will use the symbol's value, which may point to a PLT entry, but we
10521 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10522 branches in this object should go to it, except if the PLT is too
10523 far away, in which case a long branch stub should be inserted. */
bb224fc3 10524 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10525 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10526 && r_type != R_ARM_CALL
10527 && r_type != R_ARM_JUMP24
10528 && r_type != R_ARM_PLT32)
34e77a92 10529 && plt_offset != (bfd_vma) -1)
7359ea65 10530 {
34e77a92
RS		 10531 /* If we've created a .plt section, and assigned a PLT entry
10532 to this function, it must either be a STT_GNU_IFUNC reference
10533 or not be known to bind locally. In other cases, we should
10534 have cleared the PLT entry by now. */
10535 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10536
10537 value = (splt->output_section->vma
10538 + splt->output_offset
34e77a92 10539 + plt_offset);
0945cdfd 10540 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10541 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10542 contents, rel->r_offset, value,
00a97672 10543 rel->r_addend);
7359ea65
DJ		 10544 }
10545
67687978
PB		 10546 /* When generating a shared object or relocatable executable, these
10547 relocations are copied into the output file to be resolved at
10548 run time. */
0e1862bb 10549 if ((bfd_link_pic (info)
e8b09b87
CL		 10550 || globals->root.is_relocatable_executable
10551 || globals->fdpic_p)
7359ea65 10552 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10553 && !(globals->vxworks_p
3348747a
NS		 10554 && strcmp (input_section->output_section->name,
10555 ".tls_vars") == 0)
bb224fc3 10556 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10557 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10558 && !(input_bfd == globals->stub_bfd
10559 && strstr (input_section->name, STUB_SUFFIX))
7359ea65 10560 && (h == NULL
95b03e4a
L		 10561 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10562 && !resolved_to_zero)
7359ea65
DJ		 10563 || h->root.type != bfd_link_hash_undefweak)
10564 && r_type != R_ARM_PC24
5b5bb741
PB		 10565 && r_type != R_ARM_CALL
10566 && r_type != R_ARM_JUMP24
ee06dc07 10567 && r_type != R_ARM_PREL31
7359ea65 10568 && r_type != R_ARM_PLT32)
252b5132 10569 {
947216bf 10570 Elf_Internal_Rela outrel;
b34976b6 10571 bfd_boolean skip, relocate;
e8b09b87 10572 int isrofixup = 0;
f21f3fe0 10573
52db4ec2
JW		 10574 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10575 && !h->def_regular)
10576 {
10577 char *v = _("shared object");
10578
0e1862bb 10579 if (bfd_link_executable (info))
52db4ec2
JW		 10580 v = _("PIE executable");
10581
4eca0228 10582 _bfd_error_handler
871b3ab2 10583 (_("%pB: relocation %s against external or undefined symbol `%s'"
52db4ec2
JW		 10584 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10585 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10586 return bfd_reloc_notsupported;
10587 }
10588
0945cdfd
DJ		 10589 *unresolved_reloc_p = FALSE;
10590
34e77a92 10591 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10592 {
83bac4b0
NC		 10593 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10594 ! globals->use_rel);
f21f3fe0 10595
83bac4b0 10596 if (sreloc == NULL)
252b5132 10597 return bfd_reloc_notsupported;
252b5132 10598 }
f21f3fe0 10599
b34976b6
AM		 10600 skip = FALSE;
10601 relocate = FALSE;
f21f3fe0 10602
00a97672 10603 outrel.r_addend = addend;
c629eae0
JJ		 10604 outrel.r_offset =
10605 _bfd_elf_section_offset (output_bfd, info, input_section,
10606 rel->r_offset);
10607 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10608 skip = TRUE;
0bb2d96a 10609 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10610 skip = TRUE, relocate = TRUE;
252b5132
RH		 10611 outrel.r_offset += (input_section->output_section->vma
10612 + input_section->output_offset);
f21f3fe0 10613
252b5132 10614 if (skip)
0bb2d96a 10615 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10616 else if (h != NULL
10617 && h->dynindx != -1
0e1862bb 10618 && (!bfd_link_pic (info)
1dcb9720
JW		 10619 || !(bfd_link_pie (info)
10620 || SYMBOLIC_BIND (info, h))
f5385ebf 10621 || !h->def_regular))
5e681ec4 10622 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10623 else
10624 {
a16385dc
MM		 10625 int symbol;
10626
5e681ec4 10627 /* This symbol is local, or marked to become local. */
e8b09b87
CL		 10628 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI
10629 || (globals->fdpic_p && !bfd_link_pic(info)));
a16385dc 10630 if (globals->symbian_p)
6366ff1e 10631 {
74541ad4
AM		 10632 asection *osec;
10633
6366ff1e
MM		 10634 /* On Symbian OS, the data segment and text segement
10635 can be relocated independently. Therefore, we
10636 must indicate the segment to which this
10637 relocation is relative. The BPABI allows us to
10638 use any symbol in the right segment; we just use
10639 the section symbol as it is convenient. (We
10640 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10641 will not appear in the dynamic symbol table.)
10642
10643 Note that the dynamic linker ignores the section
10644 symbol value, so we don't subtract osec->vma
10645 from the emitted reloc addend. */
10dbd1f3 10646 if (sym_sec)
74541ad4 10647 osec = sym_sec->output_section;
10dbd1f3 10648 else
74541ad4
AM		 10649 osec = input_section->output_section;
10650 symbol = elf_section_data (osec)->dynindx;
10651 if (symbol == 0)
10652 {
10653 struct elf_link_hash_table *htab = elf_hash_table (info);
10654
10655 if ((osec->flags & SEC_READONLY) == 0
10656 && htab->data_index_section != NULL)
10657 osec = htab->data_index_section;
10658 else
10659 osec = htab->text_index_section;
10660 symbol = elf_section_data (osec)->dynindx;
10661 }
6366ff1e
MM		 10662 BFD_ASSERT (symbol != 0);
10663 }
a16385dc
MM		 10664 else
10665 /* On SVR4-ish systems, the dynamic loader cannot
10666 relocate the text and data segments independently,
10667 so the symbol does not matter. */
10668 symbol = 0;
34e77a92
RS		 10669 if (dynreloc_st_type == STT_GNU_IFUNC)
10670 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10671 to the .iplt entry. Instead, every non-call reference
10672 must use an R_ARM_IRELATIVE relocation to obtain the
10673 correct run-time address. */
10674 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
e8b09b87
CL		 10675 else if (globals->fdpic_p && !bfd_link_pic(info))
10676 isrofixup = 1;
34e77a92
RS		 10677 else
10678 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10679 if (globals->use_rel)
10680 relocate = TRUE;
10681 else
34e77a92 10682 outrel.r_addend += dynreloc_value;
252b5132 10683 }
f21f3fe0 10684
e8b09b87
CL		 10685 if (isrofixup)
10686 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
10687 else
10688 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10689
f21f3fe0 10690 /* If this reloc is against an external symbol, we do not want to
252b5132 10691 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10692 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10693 if (! relocate)
10694 return bfd_reloc_ok;
9a5aca8c 10695
f21f3fe0 10696 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10697 contents, rel->r_offset,
10698 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10699 }
10700 else switch (r_type)
10701 {
00a97672
RS		 10702 case R_ARM_ABS12:
10703 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10704
dfc5f959 10705 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10706 case R_ARM_CALL:
10707 case R_ARM_JUMP24:
8029a119 10708 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10709 case R_ARM_PLT32:
906e58ca 10710 {
906e58ca
NC		 10711 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10712
dfc5f959 10713 if (r_type == R_ARM_XPC25)
252b5132 10714 {
dfc5f959
NC		 10715 /* Check for Arm calling Arm function. */
10716 /* FIXME: Should we translate the instruction into a BL
10717 instruction instead ? */
35fc36a8 10718 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10719 _bfd_error_handler
90b6238f
AM		 10720 (_("\%pB: warning: %s BLX instruction targets"
10721 " %s function '%s'"),
10722 input_bfd, "ARM",
10723 "ARM", h ? h->root.root.string : "(local)");
dfc5f959 10724 }
155d87d7 10725 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10726 {
10727 /* Check for Arm calling Thumb function. */
35fc36a8 10728 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10729 {
f2a9dd69
DJ		 10730 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10731 output_bfd, input_section,
10732 hit_data, sym_sec, rel->r_offset,
10733 signed_addend, value,
10734 error_message))
10735 return bfd_reloc_ok;
10736 else
10737 return bfd_reloc_dangerous;
dfc5f959 10738 }
252b5132 10739 }
ba96a88f 10740
906e58ca 10741 /* Check if a stub has to be inserted because the
8029a119 10742 destination is too far or we are changing mode. */
155d87d7
CL		 10743 if ( r_type == R_ARM_CALL
10744 || r_type == R_ARM_JUMP24
10745 || r_type == R_ARM_PLT32)
906e58ca 10746 {
fe33d2fa
CL		 10747 enum elf32_arm_stub_type stub_type = arm_stub_none;
10748 struct elf32_arm_link_hash_entry *hash;
10749
10750 hash = (struct elf32_arm_link_hash_entry *) h;
10751 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10752 st_type, &branch_type,
10753 hash, value, sym_sec,
fe33d2fa 10754 input_bfd, sym_name);
5fa9e92f 10755
fe33d2fa 10756 if (stub_type != arm_stub_none)
906e58ca
NC		 10757 {
10758 /* The target is out of reach, so redirect the
10759 branch to the local stub for this function. */
906e58ca
NC		 10760 stub_entry = elf32_arm_get_stub_entry (input_section,
10761 sym_sec, h,
fe33d2fa
CL		 10762 rel, globals,
10763 stub_type);
9cd3e4e5
NC		 10764 {
10765 if (stub_entry != NULL)
10766 value = (stub_entry->stub_offset
10767 + stub_entry->stub_sec->output_offset
10768 + stub_entry->stub_sec->output_section->vma);
10769
10770 if (plt_offset != (bfd_vma) -1)
10771 *unresolved_reloc_p = FALSE;
10772 }
906e58ca 10773 }
fe33d2fa
CL		 10774 else
10775 {
10776 /* If the call goes through a PLT entry, make sure to
10777 check distance to the right destination address. */
34e77a92 10778 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10779 {
10780 value = (splt->output_section->vma
10781 + splt->output_offset
34e77a92 10782 + plt_offset);
fe33d2fa
CL		 10783 *unresolved_reloc_p = FALSE;
10784 /* The PLT entry is in ARM mode, regardless of the
10785 target function. */
35fc36a8 10786 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10787 }
10788 }
906e58ca
NC		 10789 }
10790
dea514f5
PB		 10791 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10792 where:
10793 S is the address of the symbol in the relocation.
10794 P is address of the instruction being relocated.
10795 A is the addend (extracted from the instruction) in bytes.
10796
10797 S is held in 'value'.
10798 P is the base address of the section containing the
10799 instruction plus the offset of the reloc into that
10800 section, ie:
10801 (input_section->output_section->vma +
10802 input_section->output_offset +
10803 rel->r_offset).
10804 A is the addend, converted into bytes, ie:
10805 (signed_addend * 4)
10806
10807 Note: None of these operations have knowledge of the pipeline
10808 size of the processor, thus it is up to the assembler to
10809 encode this information into the addend. */
10810 value -= (input_section->output_section->vma
10811 + input_section->output_offset);
10812 value -= rel->r_offset;
4e7fd91e
PB		 10813 if (globals->use_rel)
10814 value += (signed_addend << howto->size);
10815 else
10816 /* RELA addends do not have to be adjusted by howto->size. */
10817 value += signed_addend;
23080146 10818
dcb5e6e6
NC		 10819 signed_addend = value;
10820 signed_addend >>= howto->rightshift;
9a5aca8c 10821
5ab79981 10822 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10823 the next instruction unless a PLT entry will be created.
77b4f08f 10824 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10825 The jump to the next instruction is optimized as a NOP depending
10826 on the architecture. */
ffcb4889 10827 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10828 && plt_offset == (bfd_vma) -1)
77b4f08f 10829 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10830 {
cd1dac3d
DG		 10831 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10832
10833 if (arch_has_arm_nop (globals))
10834 value |= 0x0320f000;
10835 else
10836 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10837 }
10838 else
59f2c4e7 10839 {
9b485d32 10840 /* Perform a signed range check. */
dcb5e6e6 10841 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10842 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10843 return bfd_reloc_overflow;
9a5aca8c 10844
5ab79981 10845 addend = (value & 2);
39b41c9c 10846
5ab79981
PB		 10847 value = (signed_addend & howto->dst_mask)
10848 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10849
5ab79981
PB		 10850 if (r_type == R_ARM_CALL)
10851 {
155d87d7 10852 /* Set the H bit in the BLX instruction. */
35fc36a8 10853 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10854 {
10855 if (addend)
10856 value |= (1 << 24);
10857 else
10858 value &= ~(bfd_vma)(1 << 24);
10859 }
10860
5ab79981 10861 /* Select the correct instruction (BL or BLX). */
906e58ca 10862 /* Only if we are not handling a BL to a stub. In this
8029a119 10863 case, mode switching is performed by the stub. */
35fc36a8 10864 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10865 value |= (1 << 28);
63e1a0fc 10866 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10867 {
10868 value &= ~(bfd_vma)(1 << 28);
10869 value |= (1 << 24);
10870 }
39b41c9c
PB		 10871 }
10872 }
906e58ca 10873 }
252b5132 10874 break;
f21f3fe0 10875
252b5132
RH		 10876 case R_ARM_ABS32:
10877 value += addend;
35fc36a8 10878 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10879 value |= 1;
10880 break;
f21f3fe0 10881
bb224fc3
MS		 10882 case R_ARM_ABS32_NOI:
10883 value += addend;
10884 break;
10885
252b5132 10886 case R_ARM_REL32:
a8bc6c78 10887 value += addend;
35fc36a8 10888 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10889 value |= 1;
252b5132 10890 value -= (input_section->output_section->vma
62efb346 10891 + input_section->output_offset + rel->r_offset);
252b5132 10892 break;
eb043451 10893
bb224fc3
MS		 10894 case R_ARM_REL32_NOI:
10895 value += addend;
10896 value -= (input_section->output_section->vma
10897 + input_section->output_offset + rel->r_offset);
10898 break;
10899
eb043451
PB		 10900 case R_ARM_PREL31:
10901 value -= (input_section->output_section->vma
10902 + input_section->output_offset + rel->r_offset);
10903 value += signed_addend;
10904 if (! h || h->root.type != bfd_link_hash_undefweak)
10905 {
8029a119 10906 /* Check for overflow. */
eb043451
PB		 10907 if ((value ^ (value >> 1)) & (1 << 30))
10908 return bfd_reloc_overflow;
10909 }
10910 value &= 0x7fffffff;
10911 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10912 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10913 value |= 1;
10914 break;
252b5132 10915 }
f21f3fe0 10916
252b5132
RH		 10917 bfd_put_32 (input_bfd, value, hit_data);
10918 return bfd_reloc_ok;
10919
10920 case R_ARM_ABS8:
fd0fd00c
MJ		 10921 /* PR 16202: Refectch the addend using the correct size. */
10922 if (globals->use_rel)
10923 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10924 value += addend;
4e67d4ca
DG		 10925
10926 /* There is no way to tell whether the user intended to use a signed or
10927 unsigned addend. When checking for overflow we accept either,
10928 as specified by the AAELF. */
10929 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10930 return bfd_reloc_overflow;
10931
10932 bfd_put_8 (input_bfd, value, hit_data);
10933 return bfd_reloc_ok;
10934
10935 case R_ARM_ABS16:
fd0fd00c
MJ		 10936 /* PR 16202: Refectch the addend using the correct size. */
10937 if (globals->use_rel)
10938 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10939 value += addend;
10940
4e67d4ca
DG		 10941 /* See comment for R_ARM_ABS8. */
10942 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10943 return bfd_reloc_overflow;
10944
10945 bfd_put_16 (input_bfd, value, hit_data);
10946 return bfd_reloc_ok;
10947
252b5132 10948 case R_ARM_THM_ABS5:
9b485d32 10949 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10950 if (globals->use_rel)
10951 {
10952 /* Need to refetch addend. */
10953 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10954 /* ??? Need to determine shift amount from operand size. */
10955 addend >>= howto->rightshift;
10956 }
252b5132
RH		 10957 value += addend;
10958
10959 /* ??? Isn't value unsigned? */
10960 if ((long) value > 0x1f || (long) value < -0x10)
10961 return bfd_reloc_overflow;
10962
10963 /* ??? Value needs to be properly shifted into place first. */
10964 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10965 bfd_put_16 (input_bfd, value, hit_data);
10966 return bfd_reloc_ok;
10967
2cab6cc3
MS		 10968 case R_ARM_THM_ALU_PREL_11_0:
10969 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10970 {
10971 bfd_vma insn;
10972 bfd_signed_vma relocation;
10973
10974 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10975 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10976
99059e56
RM		 10977 if (globals->use_rel)
10978 {
10979 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10980 | ((insn & (1 << 26)) >> 15);
10981 if (insn & 0xf00000)
10982 signed_addend = -signed_addend;
10983 }
2cab6cc3
MS		 10984
10985 relocation = value + signed_addend;
79f08007 10986 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10987 + input_section->output_offset
10988 + rel->r_offset);
2cab6cc3 10989
8c65b54f
CS		 10990 /* PR 21523: Use an absolute value. The user of this reloc will
10991 have already selected an ADD or SUB insn appropriately. */
453f8e1e 10992 value = llabs (relocation);
2cab6cc3 10993
99059e56
RM		 10994 if (value >= 0x1000)
10995 return bfd_reloc_overflow;
2cab6cc3 10996
e645cf40
AG		 10997 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10998 if (branch_type == ST_BRANCH_TO_THUMB)
10999 value |= 1;
11000
2cab6cc3 11001 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 11002 | ((value & 0x700) << 4)
11003 | ((value & 0x800) << 15);
11004 if (relocation < 0)
11005 insn |= 0xa00000;
2cab6cc3
MS		 11006
11007 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11008 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11009
99059e56 11010 return bfd_reloc_ok;
2cab6cc3
MS		 11011 }
11012
e1ec24c6
NC		 11013 case R_ARM_THM_PC8:
11014 /* PR 10073: This reloc is not generated by the GNU toolchain,
11015 but it is supported for compatibility with third party libraries
11016 generated by other compilers, specifically the ARM/IAR. */
11017 {
11018 bfd_vma insn;
11019 bfd_signed_vma relocation;
11020
11021 insn = bfd_get_16 (input_bfd, hit_data);
11022
99059e56 11023 if (globals->use_rel)
79f08007 11024 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 11025
11026 relocation = value + addend;
79f08007 11027 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11028 + input_section->output_offset
11029 + rel->r_offset);
e1ec24c6 11030
b6518b38 11031 value = relocation;
e1ec24c6
NC		 11032
11033 /* We do not check for overflow of this reloc. Although strictly
11034 speaking this is incorrect, it appears to be necessary in order
11035 to work with IAR generated relocs. Since GCC and GAS do not
11036 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
11037 a problem for them. */
11038 value &= 0x3fc;
11039
11040 insn = (insn & 0xff00) | (value >> 2);
11041
11042 bfd_put_16 (input_bfd, insn, hit_data);
11043
99059e56 11044 return bfd_reloc_ok;
e1ec24c6
NC		 11045 }
11046
2cab6cc3
MS		 11047 case R_ARM_THM_PC12:
11048 /* Corresponds to: ldr.w reg, [pc, #offset]. */
11049 {
11050 bfd_vma insn;
11051 bfd_signed_vma relocation;
11052
11053 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 11054 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 11055
99059e56
RM		 11056 if (globals->use_rel)
11057 {
11058 signed_addend = insn & 0xfff;
11059 if (!(insn & (1 << 23)))
11060 signed_addend = -signed_addend;
11061 }
2cab6cc3
MS		 11062
11063 relocation = value + signed_addend;
79f08007 11064 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11065 + input_section->output_offset
11066 + rel->r_offset);
2cab6cc3 11067
b6518b38 11068 value = relocation;
2cab6cc3 11069
99059e56
RM		 11070 if (value >= 0x1000)
11071 return bfd_reloc_overflow;
2cab6cc3
MS		 11072
11073 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 11074 if (relocation >= 0)
11075 insn |= (1 << 23);
2cab6cc3
MS		 11076
11077 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11078 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11079
99059e56 11080 return bfd_reloc_ok;
2cab6cc3
MS		 11081 }
11082
dfc5f959 11083 case R_ARM_THM_XPC22:
c19d1205 11084 case R_ARM_THM_CALL:
bd97cb95 11085 case R_ARM_THM_JUMP24:
dfc5f959 11086 /* Thumb BL (branch long instruction). */
252b5132 11087 {
b34976b6 11088 bfd_vma relocation;
99059e56 11089 bfd_vma reloc_sign;
b34976b6
AM		 11090 bfd_boolean overflow = FALSE;
11091 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11092 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 11093 bfd_signed_vma reloc_signed_max;
11094 bfd_signed_vma reloc_signed_min;
b34976b6 11095 bfd_vma check;
252b5132 11096 bfd_signed_vma signed_check;
e95de063 11097 int bitsize;
cd1dac3d 11098 const int thumb2 = using_thumb2 (globals);
5e866f5a 11099 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 11100
5ab79981 11101 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 11102 the next instruction unless a PLT entry will be created.
11103 The jump to the next instruction is optimized as a NOP.W for
11104 Thumb-2 enabled architectures. */
19540007 11105 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 11106 && plt_offset == (bfd_vma) -1)
5ab79981 11107 {
60a019a0 11108 if (thumb2)
cd1dac3d
DG		 11109 {
11110 bfd_put_16 (input_bfd, 0xf3af, hit_data);
11111 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
11112 }
11113 else
11114 {
11115 bfd_put_16 (input_bfd, 0xe000, hit_data);
11116 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
11117 }
5ab79981
PB		 11118 return bfd_reloc_ok;
11119 }
11120
e95de063 11121 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 11122 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 11123 if (globals->use_rel)
11124 {
99059e56
RM		 11125 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
11126 bfd_vma upper = upper_insn & 0x3ff;
11127 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 11128 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
11129 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 11130 bfd_vma i1 = j1 ^ s ? 0 : 1;
11131 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 11132
99059e56
RM		 11133 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
11134 /* Sign extend. */
11135 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 11136
4e7fd91e
PB		 11137 signed_addend = addend;
11138 }
cb1afa5c 11139
dfc5f959
NC		 11140 if (r_type == R_ARM_THM_XPC22)
11141 {
11142 /* Check for Thumb to Thumb call. */
11143 /* FIXME: Should we translate the instruction into a BL
11144 instruction instead ? */
35fc36a8 11145 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 11146 _bfd_error_handler
90b6238f
AM		 11147 (_("%pB: warning: %s BLX instruction targets"
11148 " %s function '%s'"),
11149 input_bfd, "Thumb",
11150 "Thumb", h ? h->root.root.string : "(local)");
dfc5f959
NC		 11151 }
11152 else
252b5132 11153 {
dfc5f959
NC		 11154 /* If it is not a call to Thumb, assume call to Arm.
11155 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 11156 function call at all, but rather a long jump. Calls through
11157 the PLT do not require stubs. */
34e77a92 11158 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 11159 {
bd97cb95 11160 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11161 {
11162 /* Convert BL to BLX. */
11163 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11164 }
155d87d7
CL		 11165 else if (( r_type != R_ARM_THM_CALL)
11166 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 11167 {
11168 if (elf32_thumb_to_arm_stub
11169 (info, sym_name, input_bfd, output_bfd, input_section,
11170 hit_data, sym_sec, rel->r_offset, signed_addend, value,
11171 error_message))
11172 return bfd_reloc_ok;
11173 else
11174 return bfd_reloc_dangerous;
11175 }
da5938a2 11176 }
35fc36a8
RS		 11177 else if (branch_type == ST_BRANCH_TO_THUMB
11178 && globals->use_blx
bd97cb95 11179 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11180 {
11181 /* Make sure this is a BL. */
11182 lower_insn |= 0x1800;
11183 }
252b5132 11184 }
f21f3fe0 11185
fe33d2fa 11186 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 11187 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 11188 {
11189 /* Check if a stub has to be inserted because the destination
8029a119 11190 is too far. */
fe33d2fa
CL		 11191 struct elf32_arm_stub_hash_entry *stub_entry;
11192 struct elf32_arm_link_hash_entry *hash;
11193
11194 hash = (struct elf32_arm_link_hash_entry *) h;
11195
11196 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 11197 st_type, &branch_type,
11198 hash, value, sym_sec,
fe33d2fa
CL		 11199 input_bfd, sym_name);
11200
11201 if (stub_type != arm_stub_none)
906e58ca
NC		 11202 {
11203 /* The target is out of reach or we are changing modes, so
11204 redirect the branch to the local stub for this
11205 function. */
11206 stub_entry = elf32_arm_get_stub_entry (input_section,
11207 sym_sec, h,
fe33d2fa
CL		 11208 rel, globals,
11209 stub_type);
906e58ca 11210 if (stub_entry != NULL)
9cd3e4e5
NC		 11211 {
11212 value = (stub_entry->stub_offset
11213 + stub_entry->stub_sec->output_offset
11214 + stub_entry->stub_sec->output_section->vma);
11215
11216 if (plt_offset != (bfd_vma) -1)
11217 *unresolved_reloc_p = FALSE;
11218 }
906e58ca 11219
f4ac8484 11220 /* If this call becomes a call to Arm, force BLX. */
155d87d7 11221 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 11222 {
11223 if ((stub_entry
11224 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 11225 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 11226 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11227 }
906e58ca
NC		 11228 }
11229 }
11230
fe33d2fa 11231 /* Handle calls via the PLT. */
34e77a92 11232 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 11233 {
11234 value = (splt->output_section->vma
11235 + splt->output_offset
34e77a92 11236 + plt_offset);
fe33d2fa 11237
eed94f8f
NC		 11238 if (globals->use_blx
11239 && r_type == R_ARM_THM_CALL
11240 && ! using_thumb_only (globals))
fe33d2fa
CL		 11241 {
11242 /* If the Thumb BLX instruction is available, convert
11243 the BL to a BLX instruction to call the ARM-mode
11244 PLT entry. */
11245 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 11246 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 11247 }
11248 else
11249 {
eed94f8f
NC		 11250 if (! using_thumb_only (globals))
11251 /* Target the Thumb stub before the ARM PLT entry. */
11252 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 11253 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 11254 }
11255 *unresolved_reloc_p = FALSE;
11256 }
11257
ba96a88f 11258 relocation = value + signed_addend;
f21f3fe0 11259
252b5132 11260 relocation -= (input_section->output_section->vma
ba96a88f
NC		 11261 + input_section->output_offset
11262 + rel->r_offset);
9a5aca8c 11263
252b5132
RH		 11264 check = relocation >> howto->rightshift;
11265
11266 /* If this is a signed value, the rightshift just dropped
11267 leading 1 bits (assuming twos complement). */
11268 if ((bfd_signed_vma) relocation >= 0)
11269 signed_check = check;
11270 else
11271 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
11272
e95de063
MS		 11273 /* Calculate the permissable maximum and minimum values for
11274 this relocation according to whether we're relocating for
11275 Thumb-2 or not. */
11276 bitsize = howto->bitsize;
5e866f5a 11277 if (!thumb2_bl)
e95de063 11278 bitsize -= 2;
f6ebfac0 11279 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 11280 reloc_signed_min = ~reloc_signed_max;
11281
252b5132 11282 /* Assumes two's complement. */
ba96a88f 11283 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 11284 overflow = TRUE;
252b5132 11285
bd97cb95 11286 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 11287 /* For a BLX instruction, make sure that the relocation is rounded up
11288 to a word boundary. This follows the semantics of the instruction
11289 which specifies that bit 1 of the target address will come from bit
11290 1 of the base address. */
11291 relocation = (relocation + 2) & ~ 3;
cb1afa5c 11292
e95de063
MS		 11293 /* Put RELOCATION back into the insn. Assumes two's complement.
11294 We use the Thumb-2 encoding, which is safe even if dealing with
11295 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 11296 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 11297 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 11298 | ((relocation >> 12) & 0x3ff)
11299 | (reloc_sign << 10);
906e58ca 11300 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 11301 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
11302 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
11303 | ((relocation >> 1) & 0x7ff);
c62e1cc3 11304
252b5132
RH		 11305 /* Put the relocated value back in the object file: */
11306 bfd_put_16 (input_bfd, upper_insn, hit_data);
11307 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11308
11309 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11310 }
11311 break;
11312
c19d1205
ZW		 11313 case R_ARM_THM_JUMP19:
11314 /* Thumb32 conditional branch instruction. */
11315 {
11316 bfd_vma relocation;
11317 bfd_boolean overflow = FALSE;
11318 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11319 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 11320 bfd_signed_vma reloc_signed_max = 0xffffe;
11321 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 11322 bfd_signed_vma signed_check;
07d6d2b8 11323 enum elf32_arm_stub_type stub_type = arm_stub_none;
c5423981
TG		 11324 struct elf32_arm_stub_hash_entry *stub_entry;
11325 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 11326
11327 /* Need to refetch the addend, reconstruct the top three bits,
11328 and squish the two 11 bit pieces together. */
11329 if (globals->use_rel)
11330 {
11331 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 11332 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 11333 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
11334 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
11335 bfd_vma lower = (lower_insn & 0x07ff);
11336
a00a1f35
MS		 11337 upper |= J1 << 6;
11338 upper |= J2 << 7;
11339 upper |= (!S) << 8;
c19d1205
ZW		 11340 upper -= 0x0100; /* Sign extend. */
11341
11342 addend = (upper << 12) | (lower << 1);
11343 signed_addend = addend;
11344 }
11345
bd97cb95 11346 /* Handle calls via the PLT. */
34e77a92 11347 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 11348 {
11349 value = (splt->output_section->vma
11350 + splt->output_offset
34e77a92 11351 + plt_offset);
bd97cb95
DJ		 11352 /* Target the Thumb stub before the ARM PLT entry. */
11353 value -= PLT_THUMB_STUB_SIZE;
11354 *unresolved_reloc_p = FALSE;
11355 }
11356
c5423981
TG		 11357 hash = (struct elf32_arm_link_hash_entry *)h;
11358
11359 stub_type = arm_type_of_stub (info, input_section, rel,
07d6d2b8
AM		 11360 st_type, &branch_type,
11361 hash, value, sym_sec,
11362 input_bfd, sym_name);
c5423981
TG		 11363 if (stub_type != arm_stub_none)
11364 {
11365 stub_entry = elf32_arm_get_stub_entry (input_section,
07d6d2b8
AM		 11366 sym_sec, h,
11367 rel, globals,
11368 stub_type);
c5423981
TG		 11369 if (stub_entry != NULL)
11370 {
07d6d2b8
AM		 11371 value = (stub_entry->stub_offset
11372 + stub_entry->stub_sec->output_offset
11373 + stub_entry->stub_sec->output_section->vma);
c5423981
TG		 11374 }
11375 }
c19d1205 11376
99059e56 11377 relocation = value + signed_addend;
c19d1205
ZW		 11378 relocation -= (input_section->output_section->vma
11379 + input_section->output_offset
11380 + rel->r_offset);
a00a1f35 11381 signed_check = (bfd_signed_vma) relocation;
c19d1205 11382
c19d1205
ZW		 11383 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11384 overflow = TRUE;
11385
11386 /* Put RELOCATION back into the insn. */
11387 {
11388 bfd_vma S = (relocation & 0x00100000) >> 20;
11389 bfd_vma J2 = (relocation & 0x00080000) >> 19;
11390 bfd_vma J1 = (relocation & 0x00040000) >> 18;
11391 bfd_vma hi = (relocation & 0x0003f000) >> 12;
11392 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
11393
a00a1f35 11394 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 11395 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
11396 }
11397
11398 /* Put the relocated value back in the object file: */
11399 bfd_put_16 (input_bfd, upper_insn, hit_data);
11400 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11401
11402 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11403 }
11404
11405 case R_ARM_THM_JUMP11:
11406 case R_ARM_THM_JUMP8:
11407 case R_ARM_THM_JUMP6:
51c5503b
NC		 11408 /* Thumb B (branch) instruction). */
11409 {
6cf9e9fe 11410 bfd_signed_vma relocation;
51c5503b
NC		 11411 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
11412 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 11413 bfd_signed_vma signed_check;
11414
c19d1205
ZW		 11415 /* CZB cannot jump backward. */
11416 if (r_type == R_ARM_THM_JUMP6)
11417 reloc_signed_min = 0;
11418
4e7fd91e 11419 if (globals->use_rel)
6cf9e9fe 11420 {
4e7fd91e
PB		 11421 /* Need to refetch addend. */
11422 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
11423 if (addend & ((howto->src_mask + 1) >> 1))
11424 {
11425 signed_addend = -1;
11426 signed_addend &= ~ howto->src_mask;
11427 signed_addend |= addend;
11428 }
11429 else
11430 signed_addend = addend;
11431 /* The value in the insn has been right shifted. We need to
11432 undo this, so that we can perform the address calculation
11433 in terms of bytes. */
11434 signed_addend <<= howto->rightshift;
6cf9e9fe 11435 }
6cf9e9fe 11436 relocation = value + signed_addend;
51c5503b
NC		 11437
11438 relocation -= (input_section->output_section->vma
11439 + input_section->output_offset
11440 + rel->r_offset);
11441
6cf9e9fe
NC		 11442 relocation >>= howto->rightshift;
11443 signed_check = relocation;
c19d1205
ZW		 11444
11445 if (r_type == R_ARM_THM_JUMP6)
11446 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
11447 else
11448 relocation &= howto->dst_mask;
51c5503b 11449 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 11450
51c5503b
NC		 11451 bfd_put_16 (input_bfd, relocation, hit_data);
11452
11453 /* Assumes two's complement. */
11454 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11455 return bfd_reloc_overflow;
11456
11457 return bfd_reloc_ok;
11458 }
cedb70c5 11459
8375c36b
PB		 11460 case R_ARM_ALU_PCREL7_0:
11461 case R_ARM_ALU_PCREL15_8:
11462 case R_ARM_ALU_PCREL23_15:
11463 {
11464 bfd_vma insn;
11465 bfd_vma relocation;
11466
11467 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 11468 if (globals->use_rel)
11469 {
11470 /* Extract the addend. */
11471 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
11472 signed_addend = addend;
11473 }
8375c36b
PB		 11474 relocation = value + signed_addend;
11475
11476 relocation -= (input_section->output_section->vma
11477 + input_section->output_offset
11478 + rel->r_offset);
11479 insn = (insn & ~0xfff)
11480 | ((howto->bitpos << 7) & 0xf00)
11481 | ((relocation >> howto->bitpos) & 0xff);
11482 bfd_put_32 (input_bfd, value, hit_data);
11483 }
11484 return bfd_reloc_ok;
11485
252b5132
RH		 11486 case R_ARM_GNU_VTINHERIT:
11487 case R_ARM_GNU_VTENTRY:
11488 return bfd_reloc_ok;
11489
c19d1205 11490 case R_ARM_GOTOFF32:
252b5132 11491 /* Relocation is relative to the start of the
99059e56 11492 global offset table. */
252b5132
RH		 11493
11494 BFD_ASSERT (sgot != NULL);
11495 if (sgot == NULL)
99059e56 11496 return bfd_reloc_notsupported;
9a5aca8c 11497
cedb70c5 11498 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11499 address by one, so that attempts to call the function pointer will
11500 correctly interpret it as Thumb code. */
35fc36a8 11501 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11502 value += 1;
11503
252b5132 11504 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11505 calculation. We always want the start of .got. If we
11506 define _GLOBAL_OFFSET_TABLE in a different way, as is
11507 permitted by the ABI, we might have to change this
11508 calculation. */
252b5132 11509 value -= sgot->output_section->vma;
f21f3fe0 11510 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11511 contents, rel->r_offset, value,
00a97672 11512 rel->r_addend);
252b5132
RH		 11513
11514 case R_ARM_GOTPC:
a7c10850 11515 /* Use global offset table as symbol value. */
252b5132 11516 BFD_ASSERT (sgot != NULL);
f21f3fe0 11517
252b5132 11518 if (sgot == NULL)
99059e56 11519 return bfd_reloc_notsupported;
252b5132 11520
0945cdfd 11521 *unresolved_reloc_p = FALSE;
252b5132 11522 value = sgot->output_section->vma;
f21f3fe0 11523 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11524 contents, rel->r_offset, value,
00a97672 11525 rel->r_addend);
f21f3fe0 11526
252b5132 11527 case R_ARM_GOT32:
eb043451 11528 case R_ARM_GOT_PREL:
252b5132 11529 /* Relocation is to the entry for this symbol in the
99059e56 11530 global offset table. */
252b5132
RH		 11531 if (sgot == NULL)
11532 return bfd_reloc_notsupported;
f21f3fe0 11533
34e77a92
RS		 11534 if (dynreloc_st_type == STT_GNU_IFUNC
11535 && plt_offset != (bfd_vma) -1
11536 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11537 {
11538 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11539 symbol, and the relocation resolves directly to the runtime
11540 target rather than to the .iplt entry. This means that any
11541 .got entry would be the same value as the .igot.plt entry,
11542 so there's no point creating both. */
11543 sgot = globals->root.igotplt;
11544 value = sgot->output_offset + gotplt_offset;
11545 }
11546 else if (h != NULL)
252b5132
RH		 11547 {
11548 bfd_vma off;
f21f3fe0 11549
252b5132
RH		 11550 off = h->got.offset;
11551 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11552 if ((off & 1) != 0)
252b5132 11553 {
b436d854
RS		 11554 /* We have already processsed one GOT relocation against
11555 this symbol. */
11556 off &= ~1;
11557 if (globals->root.dynamic_sections_created
11558 && !SYMBOL_REFERENCES_LOCAL (info, h))
11559 *unresolved_reloc_p = FALSE;
11560 }
11561 else
11562 {
11563 Elf_Internal_Rela outrel;
e8b09b87 11564 int isrofixup = 0;
b436d854 11565
e8b09b87
CL		 11566 if (((h->dynindx != -1) || globals->fdpic_p)
11567 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11568 {
11569 /* If the symbol doesn't resolve locally in a static
11570 object, we have an undefined reference. If the
11571 symbol doesn't resolve locally in a dynamic object,
11572 it should be resolved by the dynamic linker. */
11573 if (globals->root.dynamic_sections_created)
11574 {
11575 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11576 *unresolved_reloc_p = FALSE;
11577 }
11578 else
11579 outrel.r_info = 0;
11580 outrel.r_addend = 0;
11581 }
252b5132
RH		 11582 else
11583 {
34e77a92 11584 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11585 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c
AO		 11586 else if (bfd_link_pic (info)
11587 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11588 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 11589 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11590 else
2376f038
EB		 11591 {
11592 outrel.r_info = 0;
11593 if (globals->fdpic_p)
11594 isrofixup = 1;
11595 }
34e77a92 11596 outrel.r_addend = dynreloc_value;
b436d854 11597 }
ee29b9fb 11598
b436d854
RS		 11599 /* The GOT entry is initialized to zero by default.
11600 See if we should install a different value. */
11601 if (outrel.r_addend != 0
2376f038 11602 && (globals->use_rel || outrel.r_info == 0))
b436d854
RS		 11603 {
11604 bfd_put_32 (output_bfd, outrel.r_addend,
11605 sgot->contents + off);
11606 outrel.r_addend = 0;
252b5132 11607 }
f21f3fe0 11608
2376f038
EB		 11609 if (isrofixup)
11610 arm_elf_add_rofixup (output_bfd,
11611 elf32_arm_hash_table(info)->srofixup,
11612 sgot->output_section->vma
11613 + sgot->output_offset + off);
11614
11615 else if (outrel.r_info != 0)
b436d854
RS		 11616 {
11617 outrel.r_offset = (sgot->output_section->vma
11618 + sgot->output_offset
11619 + off);
11620 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11621 }
2376f038 11622
b436d854
RS		 11623 h->got.offset |= 1;
11624 }
252b5132
RH		 11625 value = sgot->output_offset + off;
11626 }
11627 else
11628 {
11629 bfd_vma off;
f21f3fe0 11630
5025eb7c
AO		 11631 BFD_ASSERT (local_got_offsets != NULL
11632 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11633
252b5132 11634 off = local_got_offsets[r_symndx];
f21f3fe0 11635
252b5132
RH		 11636 /* The offset must always be a multiple of 4. We use the
11637 least significant bit to record whether we have already
9b485d32 11638 generated the necessary reloc. */
252b5132
RH		 11639 if ((off & 1) != 0)
11640 off &= ~1;
11641 else
11642 {
2376f038
EB		 11643 Elf_Internal_Rela outrel;
11644 int isrofixup = 0;
f21f3fe0 11645
2376f038
EB		 11646 if (dynreloc_st_type == STT_GNU_IFUNC)
11647 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
11648 else if (bfd_link_pic (info))
11649 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11650 else
252b5132 11651 {
2376f038
EB		 11652 outrel.r_info = 0;
11653 if (globals->fdpic_p)
11654 isrofixup = 1;
11655 }
11656
11657 /* The GOT entry is initialized to zero by default.
11658 See if we should install a different value. */
11659 if (globals->use_rel || outrel.r_info == 0)
11660 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
11661
11662 if (isrofixup)
11663 arm_elf_add_rofixup (output_bfd,
11664 globals->srofixup,
11665 sgot->output_section->vma
11666 + sgot->output_offset + off);
f21f3fe0 11667
2376f038
EB		 11668 else if (outrel.r_info != 0)
11669 {
34e77a92 11670 outrel.r_addend = addend + dynreloc_value;
252b5132 11671 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11672 + sgot->output_offset
252b5132 11673 + off);
47beaa6a 11674 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11675 }
f21f3fe0 11676
252b5132
RH		 11677 local_got_offsets[r_symndx] |= 1;
11678 }
f21f3fe0 11679
252b5132
RH		 11680 value = sgot->output_offset + off;
11681 }
eb043451
PB		 11682 if (r_type != R_ARM_GOT32)
11683 value += sgot->output_section->vma;
9a5aca8c 11684
f21f3fe0 11685 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11686 contents, rel->r_offset, value,
00a97672 11687 rel->r_addend);
f21f3fe0 11688
ba93b8ac
DJ		 11689 case R_ARM_TLS_LDO32:
11690 value = value - dtpoff_base (info);
11691
11692 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11693 contents, rel->r_offset, value,
11694 rel->r_addend);
ba93b8ac
DJ		 11695
11696 case R_ARM_TLS_LDM32:
5c5a4843 11697 case R_ARM_TLS_LDM32_FDPIC:
ba93b8ac
DJ		 11698 {
11699 bfd_vma off;
11700
362d30a1 11701 if (sgot == NULL)
ba93b8ac
DJ		 11702 abort ();
11703
11704 off = globals->tls_ldm_got.offset;
11705
11706 if ((off & 1) != 0)
11707 off &= ~1;
11708 else
11709 {
11710 /* If we don't know the module number, create a relocation
11711 for it. */
0e1862bb 11712 if (bfd_link_pic (info))
ba93b8ac
DJ		 11713 {
11714 Elf_Internal_Rela outrel;
ba93b8ac 11715
362d30a1 11716 if (srelgot == NULL)
ba93b8ac
DJ		 11717 abort ();
11718
00a97672 11719 outrel.r_addend = 0;
362d30a1
RS		 11720 outrel.r_offset = (sgot->output_section->vma
11721 + sgot->output_offset + off);
ba93b8ac
DJ		 11722 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11723
00a97672
RS		 11724 if (globals->use_rel)
11725 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11726 sgot->contents + off);
ba93b8ac 11727
47beaa6a 11728 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11729 }
11730 else
362d30a1 11731 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11732
11733 globals->tls_ldm_got.offset |= 1;
11734 }
11735
5c5a4843 11736 if (r_type == R_ARM_TLS_LDM32_FDPIC)
e8b09b87
CL		 11737 {
11738 bfd_put_32(output_bfd,
11739 globals->root.sgot->output_offset + off,
11740 contents + rel->r_offset);
11741
11742 return bfd_reloc_ok;
11743 }
11744 else
11745 {
11746 value = sgot->output_section->vma + sgot->output_offset + off
11747 - (input_section->output_section->vma
11748 + input_section->output_offset + rel->r_offset);
ba93b8ac 11749
e8b09b87
CL		 11750 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11751 contents, rel->r_offset, value,
11752 rel->r_addend);
11753 }
ba93b8ac
DJ		 11754 }
11755
0855e32b
NS		 11756 case R_ARM_TLS_CALL:
11757 case R_ARM_THM_TLS_CALL:
ba93b8ac 11758 case R_ARM_TLS_GD32:
5c5a4843 11759 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 11760 case R_ARM_TLS_IE32:
5c5a4843 11761 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 11762 case R_ARM_TLS_GOTDESC:
11763 case R_ARM_TLS_DESCSEQ:
11764 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11765 {
0855e32b
NS		 11766 bfd_vma off, offplt;
11767 int indx = 0;
ba93b8ac
DJ		 11768 char tls_type;
11769
0855e32b 11770 BFD_ASSERT (sgot != NULL);
ba93b8ac 11771
ba93b8ac
DJ		 11772 if (h != NULL)
11773 {
11774 bfd_boolean dyn;
11775 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11776 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11777 bfd_link_pic (info),
11778 h)
11779 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11780 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11781 {
11782 *unresolved_reloc_p = FALSE;
11783 indx = h->dynindx;
11784 }
11785 off = h->got.offset;
0855e32b 11786 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11787 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11788 }
11789 else
11790 {
0855e32b 11791 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11792 off = local_got_offsets[r_symndx];
0855e32b 11793 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11794 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11795 }
11796
0855e32b 11797 /* Linker relaxations happens from one of the
b38cadfb 11798 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11799 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11800 tls_type = GOT_TLS_IE;
0855e32b
NS		 11801
11802 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11803
11804 if ((off & 1) != 0)
11805 off &= ~1;
11806 else
11807 {
11808 bfd_boolean need_relocs = FALSE;
11809 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11810 int cur_off = off;
11811
11812 /* The GOT entries have not been initialized yet. Do it
11813 now, and emit any relocations. If both an IE GOT and a
11814 GD GOT are necessary, we emit the GD first. */
11815
0e1862bb 11816 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac 11817 && (h == NULL
95b03e4a
L		 11818 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11819 && !resolved_to_zero)
ba93b8ac
DJ		 11820 || h->root.type != bfd_link_hash_undefweak))
11821 {
11822 need_relocs = TRUE;
0855e32b 11823 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11824 }
11825
0855e32b
NS		 11826 if (tls_type & GOT_TLS_GDESC)
11827 {
47beaa6a
RS		 11828 bfd_byte *loc;
11829
0855e32b
NS		 11830 /* We should have relaxed, unless this is an undefined
11831 weak symbol. */
11832 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 11833 || bfd_link_pic (info));
0855e32b 11834 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11835 <= globals->root.sgotplt->size);
0855e32b
NS		 11836
11837 outrel.r_addend = 0;
11838 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11839 + globals->root.sgotplt->output_offset
11840 + offplt
11841 + globals->sgotplt_jump_table_size);
b38cadfb 11842
0855e32b
NS		 11843 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11844 sreloc = globals->root.srelplt;
11845 loc = sreloc->contents;
11846 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11847 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11848 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11849
11850 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11851
11852 /* For globals, the first word in the relocation gets
11853 the relocation index and the top bit set, or zero,
11854 if we're binding now. For locals, it gets the
11855 symbol's offset in the tls section. */
99059e56 11856 bfd_put_32 (output_bfd,
0855e32b
NS		 11857 !h ? value - elf_hash_table (info)->tls_sec->vma
11858 : info->flags & DF_BIND_NOW ? 0
11859 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11860 globals->root.sgotplt->contents + offplt
11861 + globals->sgotplt_jump_table_size);
11862
0855e32b 11863 /* Second word in the relocation is always zero. */
99059e56 11864 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11865 globals->root.sgotplt->contents + offplt
11866 + globals->sgotplt_jump_table_size + 4);
0855e32b 11867 }
ba93b8ac
DJ		 11868 if (tls_type & GOT_TLS_GD)
11869 {
11870 if (need_relocs)
11871 {
00a97672 11872 outrel.r_addend = 0;
362d30a1
RS		 11873 outrel.r_offset = (sgot->output_section->vma
11874 + sgot->output_offset
00a97672 11875 + cur_off);
ba93b8ac 11876 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11877
00a97672
RS		 11878 if (globals->use_rel)
11879 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11880 sgot->contents + cur_off);
00a97672 11881
47beaa6a 11882 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11883
11884 if (indx == 0)
11885 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11886 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11887 else
11888 {
00a97672 11889 outrel.r_addend = 0;
ba93b8ac
DJ		 11890 outrel.r_info = ELF32_R_INFO (indx,
11891 R_ARM_TLS_DTPOFF32);
11892 outrel.r_offset += 4;
00a97672
RS		 11893
11894 if (globals->use_rel)
11895 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11896 sgot->contents + cur_off + 4);
00a97672 11897
47beaa6a
RS		 11898 elf32_arm_add_dynreloc (output_bfd, info,
11899 srelgot, &outrel);
ba93b8ac
DJ		 11900 }
11901 }
11902 else
11903 {
11904 /* If we are not emitting relocations for a
11905 general dynamic reference, then we must be in a
11906 static link or an executable link with the
11907 symbol binding locally. Mark it as belonging
11908 to module 1, the executable. */
11909 bfd_put_32 (output_bfd, 1,
362d30a1 11910 sgot->contents + cur_off);
ba93b8ac 11911 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11912 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11913 }
11914
11915 cur_off += 8;
11916 }
11917
11918 if (tls_type & GOT_TLS_IE)
11919 {
11920 if (need_relocs)
11921 {
00a97672
RS		 11922 if (indx == 0)
11923 outrel.r_addend = value - dtpoff_base (info);
11924 else
11925 outrel.r_addend = 0;
362d30a1
RS		 11926 outrel.r_offset = (sgot->output_section->vma
11927 + sgot->output_offset
ba93b8ac
DJ		 11928 + cur_off);
11929 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11930
00a97672
RS		 11931 if (globals->use_rel)
11932 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11933 sgot->contents + cur_off);
ba93b8ac 11934
47beaa6a 11935 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11936 }
11937 else
11938 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11939 sgot->contents + cur_off);
ba93b8ac
DJ		 11940 cur_off += 4;
11941 }
11942
11943 if (h != NULL)
11944 h->got.offset |= 1;
11945 else
11946 local_got_offsets[r_symndx] |= 1;
11947 }
11948
5c5a4843 11949 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32 && r_type != R_ARM_TLS_GD32_FDPIC)
ba93b8ac 11950 off += 8;
0855e32b
NS		 11951 else if (tls_type & GOT_TLS_GDESC)
11952 off = offplt;
11953
11954 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11955 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11956 {
11957 bfd_signed_vma offset;
12352d3f
PB		 11958 /* TLS stubs are arm mode. The original symbol is a
11959 data object, so branch_type is bogus. */
11960 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11961 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11962 = arm_type_of_stub (info, input_section, rel,
11963 st_type, &branch_type,
0855e32b
NS		 11964 (struct elf32_arm_link_hash_entry *)h,
11965 globals->tls_trampoline, globals->root.splt,
11966 input_bfd, sym_name);
11967
11968 if (stub_type != arm_stub_none)
11969 {
11970 struct elf32_arm_stub_hash_entry *stub_entry
11971 = elf32_arm_get_stub_entry
11972 (input_section, globals->root.splt, 0, rel,
11973 globals, stub_type);
11974 offset = (stub_entry->stub_offset
11975 + stub_entry->stub_sec->output_offset
11976 + stub_entry->stub_sec->output_section->vma);
11977 }
11978 else
11979 offset = (globals->root.splt->output_section->vma
11980 + globals->root.splt->output_offset
11981 + globals->tls_trampoline);
11982
11983 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11984 {
11985 unsigned long inst;
b38cadfb
NC		 11986
11987 offset -= (input_section->output_section->vma
11988 + input_section->output_offset
11989 + rel->r_offset + 8);
0855e32b
NS		 11990
11991 inst = offset >> 2;
11992 inst &= 0x00ffffff;
11993 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11994 }
11995 else
11996 {
11997 /* Thumb blx encodes the offset in a complicated
11998 fashion. */
11999 unsigned upper_insn, lower_insn;
12000 unsigned neg;
12001
b38cadfb
NC		 12002 offset -= (input_section->output_section->vma
12003 + input_section->output_offset
0855e32b 12004 + rel->r_offset + 4);
b38cadfb 12005
12352d3f
PB		 12006 if (stub_type != arm_stub_none
12007 && arm_stub_is_thumb (stub_type))
12008 {
12009 lower_insn = 0xd000;
12010 }
12011 else
12012 {
12013 lower_insn = 0xc000;
6a631e86 12014 /* Round up the offset to a word boundary. */
12352d3f
PB		 12015 offset = (offset + 2) & ~2;
12016 }
12017
0855e32b
NS		 12018 neg = offset < 0;
12019 upper_insn = (0xf000
12020 | ((offset >> 12) & 0x3ff)
12021 | (neg << 10));
12352d3f 12022 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 12023 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 12024 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 12025 bfd_put_16 (input_bfd, upper_insn, hit_data);
12026 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12027 return bfd_reloc_ok;
12028 }
12029 }
12030 /* These relocations needs special care, as besides the fact
12031 they point somewhere in .gotplt, the addend must be
12032 adjusted accordingly depending on the type of instruction
6a631e86 12033 we refer to. */
0855e32b
NS		 12034 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
12035 {
12036 unsigned long data, insn;
12037 unsigned thumb;
b38cadfb 12038
0855e32b
NS		 12039 data = bfd_get_32 (input_bfd, hit_data);
12040 thumb = data & 1;
12041 data &= ~1u;
b38cadfb 12042
0855e32b
NS		 12043 if (thumb)
12044 {
12045 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
12046 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
12047 insn = (insn << 16)
12048 | bfd_get_16 (input_bfd,
12049 contents + rel->r_offset - data + 2);
12050 if ((insn & 0xf800c000) == 0xf000c000)
12051 /* bl/blx */
12052 value = -6;
12053 else if ((insn & 0xffffff00) == 0x4400)
12054 /* add */
12055 value = -5;
12056 else
12057 {
4eca0228 12058 _bfd_error_handler
695344c0 12059 /* xgettext:c-format */
2dcf00ce 12060 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12061 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12062 "referenced by TLS_GOTDESC"),
12063 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12064 "Thumb", insn);
0855e32b
NS		 12065 return bfd_reloc_notsupported;
12066 }
12067 }
12068 else
12069 {
12070 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
12071
12072 switch (insn >> 24)
12073 {
12074 case 0xeb: /* bl */
12075 case 0xfa: /* blx */
12076 value = -4;
12077 break;
12078
12079 case 0xe0: /* add */
12080 value = -8;
12081 break;
b38cadfb 12082
0855e32b 12083 default:
4eca0228 12084 _bfd_error_handler
695344c0 12085 /* xgettext:c-format */
2dcf00ce 12086 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12087 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12088 "referenced by TLS_GOTDESC"),
12089 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12090 "ARM", insn);
0855e32b
NS		 12091 return bfd_reloc_notsupported;
12092 }
12093 }
b38cadfb 12094
0855e32b
NS		 12095 value += ((globals->root.sgotplt->output_section->vma
12096 + globals->root.sgotplt->output_offset + off)
12097 - (input_section->output_section->vma
12098 + input_section->output_offset
12099 + rel->r_offset)
12100 + globals->sgotplt_jump_table_size);
12101 }
12102 else
12103 value = ((globals->root.sgot->output_section->vma
12104 + globals->root.sgot->output_offset + off)
12105 - (input_section->output_section->vma
12106 + input_section->output_offset + rel->r_offset));
ba93b8ac 12107
5c5a4843
CL		 12108 if (globals->fdpic_p && (r_type == R_ARM_TLS_GD32_FDPIC ||
12109 r_type == R_ARM_TLS_IE32_FDPIC))
e8b09b87
CL		 12110 {
12111 /* For FDPIC relocations, resolve to the offset of the GOT
12112 entry from the start of GOT. */
12113 bfd_put_32(output_bfd,
12114 globals->root.sgot->output_offset + off,
12115 contents + rel->r_offset);
12116
12117 return bfd_reloc_ok;
12118 }
12119 else
12120 {
12121 return _bfd_final_link_relocate (howto, input_bfd, input_section,
12122 contents, rel->r_offset, value,
12123 rel->r_addend);
12124 }
ba93b8ac
DJ		 12125 }
12126
12127 case R_ARM_TLS_LE32:
3cbc1e5e 12128 if (bfd_link_dll (info))
ba93b8ac 12129 {
4eca0228 12130 _bfd_error_handler
695344c0 12131 /* xgettext:c-format */
2dcf00ce
AM		 12132 (_("%pB(%pA+%#" PRIx64 "): %s relocation not permitted "
12133 "in shared object"),
12134 input_bfd, input_section, (uint64_t) rel->r_offset, howto->name);
46691134 12135 return bfd_reloc_notsupported;
ba93b8ac
DJ		 12136 }
12137 else
12138 value = tpoff (info, value);
906e58ca 12139
ba93b8ac 12140 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 12141 contents, rel->r_offset, value,
12142 rel->r_addend);
ba93b8ac 12143
319850b4
JB		 12144 case R_ARM_V4BX:
12145 if (globals->fix_v4bx)
845b51d6
PB		 12146 {
12147 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 12148
845b51d6
PB		 12149 /* Ensure that we have a BX instruction. */
12150 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 12151
845b51d6
PB		 12152 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
12153 {
12154 /* Branch to veneer. */
12155 bfd_vma glue_addr;
12156 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
12157 glue_addr -= input_section->output_section->vma
12158 + input_section->output_offset
12159 + rel->r_offset + 8;
12160 insn = (insn & 0xf0000000) | 0x0a000000
12161 | ((glue_addr >> 2) & 0x00ffffff);
12162 }
12163 else
12164 {
12165 /* Preserve Rm (lowest four bits) and the condition code
12166 (highest four bits). Other bits encode MOV PC,Rm. */
12167 insn = (insn & 0xf000000f) | 0x01a0f000;
12168 }
319850b4 12169
845b51d6
PB		 12170 bfd_put_32 (input_bfd, insn, hit_data);
12171 }
319850b4
JB		 12172 return bfd_reloc_ok;
12173
b6895b4f
PB		 12174 case R_ARM_MOVW_ABS_NC:
12175 case R_ARM_MOVT_ABS:
12176 case R_ARM_MOVW_PREL_NC:
12177 case R_ARM_MOVT_PREL:
92f5d02b
MS		 12178 /* Until we properly support segment-base-relative addressing then
12179 we assume the segment base to be zero, as for the group relocations.
12180 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12181 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12182 case R_ARM_MOVW_BREL_NC:
12183 case R_ARM_MOVW_BREL:
12184 case R_ARM_MOVT_BREL:
b6895b4f
PB		 12185 {
12186 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
12187
12188 if (globals->use_rel)
12189 {
12190 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 12191 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12192 }
92f5d02b 12193
b6895b4f 12194 value += signed_addend;
b6895b4f
PB		 12195
12196 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
12197 value -= (input_section->output_section->vma
12198 + input_section->output_offset + rel->r_offset);
12199
92f5d02b 12200 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 12201 return bfd_reloc_overflow;
92f5d02b 12202
35fc36a8 12203 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12204 value |= 1;
12205
12206 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 12207 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 12208 value >>= 16;
12209
12210 insn &= 0xfff0f000;
12211 insn |= value & 0xfff;
12212 insn |= (value & 0xf000) << 4;
12213 bfd_put_32 (input_bfd, insn, hit_data);
12214 }
12215 return bfd_reloc_ok;
12216
12217 case R_ARM_THM_MOVW_ABS_NC:
12218 case R_ARM_THM_MOVT_ABS:
12219 case R_ARM_THM_MOVW_PREL_NC:
12220 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 12221 /* Until we properly support segment-base-relative addressing then
12222 we assume the segment base to be zero, as for the above relocations.
12223 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12224 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12225 as R_ARM_THM_MOVT_ABS. */
12226 case R_ARM_THM_MOVW_BREL_NC:
12227 case R_ARM_THM_MOVW_BREL:
12228 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 12229 {
12230 bfd_vma insn;
906e58ca 12231
b6895b4f
PB		 12232 insn = bfd_get_16 (input_bfd, hit_data) << 16;
12233 insn |= bfd_get_16 (input_bfd, hit_data + 2);
12234
12235 if (globals->use_rel)
12236 {
12237 addend = ((insn >> 4) & 0xf000)
12238 | ((insn >> 15) & 0x0800)
12239 | ((insn >> 4) & 0x0700)
07d6d2b8 12240 | (insn & 0x00ff);
39623e12 12241 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12242 }
92f5d02b 12243
b6895b4f 12244 value += signed_addend;
b6895b4f
PB		 12245
12246 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
12247 value -= (input_section->output_section->vma
12248 + input_section->output_offset + rel->r_offset);
12249
92f5d02b 12250 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 12251 return bfd_reloc_overflow;
92f5d02b 12252
35fc36a8 12253 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12254 value |= 1;
12255
12256 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 12257 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 12258 value >>= 16;
12259
12260 insn &= 0xfbf08f00;
12261 insn |= (value & 0xf000) << 4;
12262 insn |= (value & 0x0800) << 15;
12263 insn |= (value & 0x0700) << 4;
12264 insn |= (value & 0x00ff);
12265
12266 bfd_put_16 (input_bfd, insn >> 16, hit_data);
12267 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
12268 }
12269 return bfd_reloc_ok;
12270
4962c51a
MS		 12271 case R_ARM_ALU_PC_G0_NC:
12272 case R_ARM_ALU_PC_G1_NC:
12273 case R_ARM_ALU_PC_G0:
12274 case R_ARM_ALU_PC_G1:
12275 case R_ARM_ALU_PC_G2:
12276 case R_ARM_ALU_SB_G0_NC:
12277 case R_ARM_ALU_SB_G1_NC:
12278 case R_ARM_ALU_SB_G0:
12279 case R_ARM_ALU_SB_G1:
12280 case R_ARM_ALU_SB_G2:
12281 {
12282 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12283 bfd_vma pc = input_section->output_section->vma
4962c51a 12284 + input_section->output_offset + rel->r_offset;
31a91d61 12285 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12286 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 12287 bfd_vma residual;
12288 bfd_vma g_n;
4962c51a 12289 bfd_signed_vma signed_value;
99059e56
RM		 12290 int group = 0;
12291
12292 /* Determine which group of bits to select. */
12293 switch (r_type)
12294 {
12295 case R_ARM_ALU_PC_G0_NC:
12296 case R_ARM_ALU_PC_G0:
12297 case R_ARM_ALU_SB_G0_NC:
12298 case R_ARM_ALU_SB_G0:
12299 group = 0;
12300 break;
12301
12302 case R_ARM_ALU_PC_G1_NC:
12303 case R_ARM_ALU_PC_G1:
12304 case R_ARM_ALU_SB_G1_NC:
12305 case R_ARM_ALU_SB_G1:
12306 group = 1;
12307 break;
12308
12309 case R_ARM_ALU_PC_G2:
12310 case R_ARM_ALU_SB_G2:
12311 group = 2;
12312 break;
12313
12314 default:
12315 abort ();
12316 }
12317
12318 /* If REL, extract the addend from the insn. If RELA, it will
12319 have already been fetched for us. */
4962c51a 12320 if (globals->use_rel)
99059e56
RM		 12321 {
12322 int negative;
12323 bfd_vma constant = insn & 0xff;
12324 bfd_vma rotation = (insn & 0xf00) >> 8;
12325
12326 if (rotation == 0)
12327 signed_addend = constant;
12328 else
12329 {
12330 /* Compensate for the fact that in the instruction, the
12331 rotation is stored in multiples of 2 bits. */
12332 rotation *= 2;
12333
12334 /* Rotate "constant" right by "rotation" bits. */
12335 signed_addend = (constant >> rotation) |
12336 (constant << (8 * sizeof (bfd_vma) - rotation));
12337 }
12338
12339 /* Determine if the instruction is an ADD or a SUB.
12340 (For REL, this determines the sign of the addend.) */
12341 negative = identify_add_or_sub (insn);
12342 if (negative == 0)
12343 {
4eca0228 12344 _bfd_error_handler
695344c0 12345 /* xgettext:c-format */
90b6238f 12346 (_("%pB(%pA+%#" PRIx64 "): only ADD or SUB instructions "
2dcf00ce
AM		 12347 "are allowed for ALU group relocations"),
12348 input_bfd, input_section, (uint64_t) rel->r_offset);
99059e56
RM		 12349 return bfd_reloc_overflow;
12350 }
12351
12352 signed_addend *= negative;
12353 }
4962c51a
MS		 12354
12355 /* Compute the value (X) to go in the place. */
99059e56
RM		 12356 if (r_type == R_ARM_ALU_PC_G0_NC
12357 || r_type == R_ARM_ALU_PC_G1_NC
12358 || r_type == R_ARM_ALU_PC_G0
12359 || r_type == R_ARM_ALU_PC_G1
12360 || r_type == R_ARM_ALU_PC_G2)
12361 /* PC relative. */
12362 signed_value = value - pc + signed_addend;
12363 else
12364 /* Section base relative. */
12365 signed_value = value - sb + signed_addend;
12366
12367 /* If the target symbol is a Thumb function, then set the
12368 Thumb bit in the address. */
35fc36a8 12369 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 12370 signed_value |= 1;
12371
99059e56
RM		 12372 /* Calculate the value of the relevant G_n, in encoded
12373 constant-with-rotation format. */
b6518b38
NC		 12374 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12375 group, &residual);
99059e56
RM		 12376
12377 /* Check for overflow if required. */
12378 if ((r_type == R_ARM_ALU_PC_G0
12379 || r_type == R_ARM_ALU_PC_G1
12380 || r_type == R_ARM_ALU_PC_G2
12381 || r_type == R_ARM_ALU_SB_G0
12382 || r_type == R_ARM_ALU_SB_G1
12383 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
12384 {
4eca0228 12385 _bfd_error_handler
695344c0 12386 /* xgettext:c-format */
90b6238f 12387 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12388 "splitting %#" PRIx64 " for group relocation %s"),
12389 input_bfd, input_section, (uint64_t) rel->r_offset,
12390 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12391 howto->name);
99059e56
RM		 12392 return bfd_reloc_overflow;
12393 }
12394
12395 /* Mask out the value and the ADD/SUB part of the opcode; take care
12396 not to destroy the S bit. */
12397 insn &= 0xff1ff000;
12398
12399 /* Set the opcode according to whether the value to go in the
12400 place is negative. */
12401 if (signed_value < 0)
12402 insn |= 1 << 22;
12403 else
12404 insn |= 1 << 23;
12405
12406 /* Encode the offset. */
12407 insn |= g_n;
4962c51a
MS		 12408
12409 bfd_put_32 (input_bfd, insn, hit_data);
12410 }
12411 return bfd_reloc_ok;
12412
12413 case R_ARM_LDR_PC_G0:
12414 case R_ARM_LDR_PC_G1:
12415 case R_ARM_LDR_PC_G2:
12416 case R_ARM_LDR_SB_G0:
12417 case R_ARM_LDR_SB_G1:
12418 case R_ARM_LDR_SB_G2:
12419 {
12420 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12421 bfd_vma pc = input_section->output_section->vma
4962c51a 12422 + input_section->output_offset + rel->r_offset;
31a91d61 12423 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12424 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12425 bfd_vma residual;
4962c51a 12426 bfd_signed_vma signed_value;
99059e56
RM		 12427 int group = 0;
12428
12429 /* Determine which groups of bits to calculate. */
12430 switch (r_type)
12431 {
12432 case R_ARM_LDR_PC_G0:
12433 case R_ARM_LDR_SB_G0:
12434 group = 0;
12435 break;
12436
12437 case R_ARM_LDR_PC_G1:
12438 case R_ARM_LDR_SB_G1:
12439 group = 1;
12440 break;
12441
12442 case R_ARM_LDR_PC_G2:
12443 case R_ARM_LDR_SB_G2:
12444 group = 2;
12445 break;
12446
12447 default:
12448 abort ();
12449 }
12450
12451 /* If REL, extract the addend from the insn. If RELA, it will
12452 have already been fetched for us. */
4962c51a 12453 if (globals->use_rel)
99059e56
RM		 12454 {
12455 int negative = (insn & (1 << 23)) ? 1 : -1;
12456 signed_addend = negative * (insn & 0xfff);
12457 }
4962c51a
MS		 12458
12459 /* Compute the value (X) to go in the place. */
99059e56
RM		 12460 if (r_type == R_ARM_LDR_PC_G0
12461 || r_type == R_ARM_LDR_PC_G1
12462 || r_type == R_ARM_LDR_PC_G2)
12463 /* PC relative. */
12464 signed_value = value - pc + signed_addend;
12465 else
12466 /* Section base relative. */
12467 signed_value = value - sb + signed_addend;
12468
12469 /* Calculate the value of the relevant G_{n-1} to obtain
12470 the residual at that stage. */
b6518b38
NC		 12471 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12472 group - 1, &residual);
99059e56
RM		 12473
12474 /* Check for overflow. */
12475 if (residual >= 0x1000)
12476 {
4eca0228 12477 _bfd_error_handler
695344c0 12478 /* xgettext:c-format */
90b6238f 12479 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12480 "splitting %#" PRIx64 " for group relocation %s"),
12481 input_bfd, input_section, (uint64_t) rel->r_offset,
12482 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12483 howto->name);
99059e56
RM		 12484 return bfd_reloc_overflow;
12485 }
12486
12487 /* Mask out the value and U bit. */
12488 insn &= 0xff7ff000;
12489
12490 /* Set the U bit if the value to go in the place is non-negative. */
12491 if (signed_value >= 0)
12492 insn |= 1 << 23;
12493
12494 /* Encode the offset. */
12495 insn |= residual;
4962c51a
MS		 12496
12497 bfd_put_32 (input_bfd, insn, hit_data);
12498 }
12499 return bfd_reloc_ok;
12500
12501 case R_ARM_LDRS_PC_G0:
12502 case R_ARM_LDRS_PC_G1:
12503 case R_ARM_LDRS_PC_G2:
12504 case R_ARM_LDRS_SB_G0:
12505 case R_ARM_LDRS_SB_G1:
12506 case R_ARM_LDRS_SB_G2:
12507 {
12508 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12509 bfd_vma pc = input_section->output_section->vma
4962c51a 12510 + input_section->output_offset + rel->r_offset;
31a91d61 12511 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12512 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12513 bfd_vma residual;
4962c51a 12514 bfd_signed_vma signed_value;
99059e56
RM		 12515 int group = 0;
12516
12517 /* Determine which groups of bits to calculate. */
12518 switch (r_type)
12519 {
12520 case R_ARM_LDRS_PC_G0:
12521 case R_ARM_LDRS_SB_G0:
12522 group = 0;
12523 break;
12524
12525 case R_ARM_LDRS_PC_G1:
12526 case R_ARM_LDRS_SB_G1:
12527 group = 1;
12528 break;
12529
12530 case R_ARM_LDRS_PC_G2:
12531 case R_ARM_LDRS_SB_G2:
12532 group = 2;
12533 break;
12534
12535 default:
12536 abort ();
12537 }
12538
12539 /* If REL, extract the addend from the insn. If RELA, it will
12540 have already been fetched for us. */
4962c51a 12541 if (globals->use_rel)
99059e56
RM		 12542 {
12543 int negative = (insn & (1 << 23)) ? 1 : -1;
12544 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
12545 }
4962c51a
MS		 12546
12547 /* Compute the value (X) to go in the place. */
99059e56
RM		 12548 if (r_type == R_ARM_LDRS_PC_G0
12549 || r_type == R_ARM_LDRS_PC_G1
12550 || r_type == R_ARM_LDRS_PC_G2)
12551 /* PC relative. */
12552 signed_value = value - pc + signed_addend;
12553 else
12554 /* Section base relative. */
12555 signed_value = value - sb + signed_addend;
12556
12557 /* Calculate the value of the relevant G_{n-1} to obtain
12558 the residual at that stage. */
b6518b38
NC		 12559 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12560 group - 1, &residual);
99059e56
RM		 12561
12562 /* Check for overflow. */
12563 if (residual >= 0x100)
12564 {
4eca0228 12565 _bfd_error_handler
695344c0 12566 /* xgettext:c-format */
90b6238f 12567 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12568 "splitting %#" PRIx64 " for group relocation %s"),
12569 input_bfd, input_section, (uint64_t) rel->r_offset,
12570 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12571 howto->name);
99059e56
RM		 12572 return bfd_reloc_overflow;
12573 }
12574
12575 /* Mask out the value and U bit. */
12576 insn &= 0xff7ff0f0;
12577
12578 /* Set the U bit if the value to go in the place is non-negative. */
12579 if (signed_value >= 0)
12580 insn |= 1 << 23;
12581
12582 /* Encode the offset. */
12583 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12584
12585 bfd_put_32 (input_bfd, insn, hit_data);
12586 }
12587 return bfd_reloc_ok;
12588
12589 case R_ARM_LDC_PC_G0:
12590 case R_ARM_LDC_PC_G1:
12591 case R_ARM_LDC_PC_G2:
12592 case R_ARM_LDC_SB_G0:
12593 case R_ARM_LDC_SB_G1:
12594 case R_ARM_LDC_SB_G2:
12595 {
12596 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12597 bfd_vma pc = input_section->output_section->vma
4962c51a 12598 + input_section->output_offset + rel->r_offset;
31a91d61 12599 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12600 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12601 bfd_vma residual;
4962c51a 12602 bfd_signed_vma signed_value;
99059e56
RM		 12603 int group = 0;
12604
12605 /* Determine which groups of bits to calculate. */
12606 switch (r_type)
12607 {
12608 case R_ARM_LDC_PC_G0:
12609 case R_ARM_LDC_SB_G0:
12610 group = 0;
12611 break;
12612
12613 case R_ARM_LDC_PC_G1:
12614 case R_ARM_LDC_SB_G1:
12615 group = 1;
12616 break;
12617
12618 case R_ARM_LDC_PC_G2:
12619 case R_ARM_LDC_SB_G2:
12620 group = 2;
12621 break;
12622
12623 default:
12624 abort ();
12625 }
12626
12627 /* If REL, extract the addend from the insn. If RELA, it will
12628 have already been fetched for us. */
4962c51a 12629 if (globals->use_rel)
99059e56
RM		 12630 {
12631 int negative = (insn & (1 << 23)) ? 1 : -1;
12632 signed_addend = negative * ((insn & 0xff) << 2);
12633 }
4962c51a
MS		 12634
12635 /* Compute the value (X) to go in the place. */
99059e56
RM		 12636 if (r_type == R_ARM_LDC_PC_G0
12637 || r_type == R_ARM_LDC_PC_G1
12638 || r_type == R_ARM_LDC_PC_G2)
12639 /* PC relative. */
12640 signed_value = value - pc + signed_addend;
12641 else
12642 /* Section base relative. */
12643 signed_value = value - sb + signed_addend;
12644
12645 /* Calculate the value of the relevant G_{n-1} to obtain
12646 the residual at that stage. */
b6518b38
NC		 12647 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12648 group - 1, &residual);
99059e56
RM		 12649
12650 /* Check for overflow. (The absolute value to go in the place must be
12651 divisible by four and, after having been divided by four, must
12652 fit in eight bits.) */
12653 if ((residual & 0x3) != 0 || residual >= 0x400)
12654 {
4eca0228 12655 _bfd_error_handler
695344c0 12656 /* xgettext:c-format */
90b6238f 12657 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12658 "splitting %#" PRIx64 " for group relocation %s"),
12659 input_bfd, input_section, (uint64_t) rel->r_offset,
12660 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12661 howto->name);
99059e56
RM		 12662 return bfd_reloc_overflow;
12663 }
12664
12665 /* Mask out the value and U bit. */
12666 insn &= 0xff7fff00;
12667
12668 /* Set the U bit if the value to go in the place is non-negative. */
12669 if (signed_value >= 0)
12670 insn |= 1 << 23;
12671
12672 /* Encode the offset. */
12673 insn |= residual >> 2;
4962c51a
MS		 12674
12675 bfd_put_32 (input_bfd, insn, hit_data);
12676 }
12677 return bfd_reloc_ok;
12678
72d98d16
MG		 12679 case R_ARM_THM_ALU_ABS_G0_NC:
12680 case R_ARM_THM_ALU_ABS_G1_NC:
12681 case R_ARM_THM_ALU_ABS_G2_NC:
12682 case R_ARM_THM_ALU_ABS_G3_NC:
12683 {
12684 const int shift_array[4] = {0, 8, 16, 24};
12685 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12686 bfd_vma addr = value;
12687 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12688
12689 /* Compute address. */
12690 if (globals->use_rel)
12691 signed_addend = insn & 0xff;
12692 addr += signed_addend;
12693 if (branch_type == ST_BRANCH_TO_THUMB)
12694 addr |= 1;
12695 /* Clean imm8 insn. */
12696 insn &= 0xff00;
12697 /* And update with correct part of address. */
12698 insn |= (addr >> shift) & 0xff;
12699 /* Update insn. */
12700 bfd_put_16 (input_bfd, insn, hit_data);
12701 }
12702
12703 *unresolved_reloc_p = FALSE;
12704 return bfd_reloc_ok;
12705
e8b09b87
CL		 12706 case R_ARM_GOTOFFFUNCDESC:
12707 {
4b24dd1a 12708 if (h == NULL)
e8b09b87
CL		 12709 {
12710 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12711 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12712 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12713 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12714 bfd_vma seg = -1;
12715
12716 if (bfd_link_pic(info) && dynindx == 0)
12717 abort();
12718
12719 /* Resolve relocation. */
12720 bfd_put_32(output_bfd, (offset + sgot->output_offset)
12721 , contents + rel->r_offset);
12722 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12723 not done yet. */
12724 arm_elf_fill_funcdesc(output_bfd, info,
12725 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12726 dynindx, offset, addr, dynreloc_value, seg);
12727 }
12728 else
12729 {
12730 int dynindx;
12731 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12732 bfd_vma addr;
12733 bfd_vma seg = -1;
12734
12735 /* For static binaries, sym_sec can be null. */
12736 if (sym_sec)
12737 {
12738 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12739 addr = dynreloc_value - sym_sec->output_section->vma;
12740 }
12741 else
12742 {
12743 dynindx = 0;
12744 addr = 0;
12745 }
12746
12747 if (bfd_link_pic(info) && dynindx == 0)
12748 abort();
12749
12750 /* This case cannot occur since funcdesc is allocated by
12751 the dynamic loader so we cannot resolve the relocation. */
12752 if (h->dynindx != -1)
12753 abort();
12754
12755 /* Resolve relocation. */
12756 bfd_put_32(output_bfd, (offset + sgot->output_offset),
12757 contents + rel->r_offset);
12758 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12759 arm_elf_fill_funcdesc(output_bfd, info,
12760 &eh->fdpic_cnts.funcdesc_offset,
12761 dynindx, offset, addr, dynreloc_value, seg);
12762 }
12763 }
12764 *unresolved_reloc_p = FALSE;
12765 return bfd_reloc_ok;
12766
12767 case R_ARM_GOTFUNCDESC:
12768 {
4b24dd1a 12769 if (h != NULL)
e8b09b87
CL		 12770 {
12771 Elf_Internal_Rela outrel;
12772
12773 /* Resolve relocation. */
12774 bfd_put_32(output_bfd, ((eh->fdpic_cnts.gotfuncdesc_offset & ~1)
12775 + sgot->output_offset),
12776 contents + rel->r_offset);
12777 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12778 if(h->dynindx == -1)
12779 {
12780 int dynindx;
12781 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12782 bfd_vma addr;
12783 bfd_vma seg = -1;
12784
12785 /* For static binaries sym_sec can be null. */
12786 if (sym_sec)
12787 {
12788 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12789 addr = dynreloc_value - sym_sec->output_section->vma;
12790 }
12791 else
12792 {
12793 dynindx = 0;
12794 addr = 0;
12795 }
12796
12797 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12798 arm_elf_fill_funcdesc(output_bfd, info,
12799 &eh->fdpic_cnts.funcdesc_offset,
12800 dynindx, offset, addr, dynreloc_value, seg);
12801 }
12802
12803 /* Add a dynamic relocation on GOT entry if not already done. */
12804 if ((eh->fdpic_cnts.gotfuncdesc_offset & 1) == 0)
12805 {
12806 if (h->dynindx == -1)
12807 {
12808 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12809 if (h->root.type == bfd_link_hash_undefweak)
12810 bfd_put_32(output_bfd, 0, sgot->contents
12811 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12812 else
12813 bfd_put_32(output_bfd, sgot->output_section->vma
12814 + sgot->output_offset
12815 + (eh->fdpic_cnts.funcdesc_offset & ~1),
12816 sgot->contents
12817 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12818 }
12819 else
12820 {
12821 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12822 }
12823 outrel.r_offset = sgot->output_section->vma
12824 + sgot->output_offset
12825 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1);
12826 outrel.r_addend = 0;
12827 if (h->dynindx == -1 && !bfd_link_pic(info))
12828 if (h->root.type == bfd_link_hash_undefweak)
4b24dd1a 12829 arm_elf_add_rofixup(output_bfd, globals->srofixup, -1);
e8b09b87 12830 else
4b24dd1a
AM		 12831 arm_elf_add_rofixup(output_bfd, globals->srofixup,
12832 outrel.r_offset);
e8b09b87
CL		 12833 else
12834 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12835 eh->fdpic_cnts.gotfuncdesc_offset |= 1;
12836 }
12837 }
12838 else
12839 {
12840 /* Such relocation on static function should not have been
12841 emitted by the compiler. */
12842 abort();
12843 }
12844 }
12845 *unresolved_reloc_p = FALSE;
12846 return bfd_reloc_ok;
12847
12848 case R_ARM_FUNCDESC:
12849 {
4b24dd1a 12850 if (h == NULL)
e8b09b87
CL		 12851 {
12852 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12853 Elf_Internal_Rela outrel;
12854 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12855 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12856 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12857 bfd_vma seg = -1;
12858
12859 if (bfd_link_pic(info) && dynindx == 0)
12860 abort();
12861
12862 /* Replace static FUNCDESC relocation with a
12863 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12864 executable. */
12865 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12866 outrel.r_offset = input_section->output_section->vma
12867 + input_section->output_offset + rel->r_offset;
12868 outrel.r_addend = 0;
12869 if (bfd_link_pic(info))
12870 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12871 else
12872 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12873
12874 bfd_put_32 (input_bfd, sgot->output_section->vma
12875 + sgot->output_offset + offset, hit_data);
12876
12877 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12878 arm_elf_fill_funcdesc(output_bfd, info,
12879 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12880 dynindx, offset, addr, dynreloc_value, seg);
12881 }
12882 else
12883 {
12884 if (h->dynindx == -1)
12885 {
12886 int dynindx;
12887 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12888 bfd_vma addr;
12889 bfd_vma seg = -1;
12890 Elf_Internal_Rela outrel;
12891
12892 /* For static binaries sym_sec can be null. */
12893 if (sym_sec)
12894 {
12895 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12896 addr = dynreloc_value - sym_sec->output_section->vma;
12897 }
12898 else
12899 {
12900 dynindx = 0;
12901 addr = 0;
12902 }
12903
12904 if (bfd_link_pic(info) && dynindx == 0)
12905 abort();
12906
12907 /* Replace static FUNCDESC relocation with a
12908 R_ARM_RELATIVE dynamic relocation. */
12909 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12910 outrel.r_offset = input_section->output_section->vma
12911 + input_section->output_offset + rel->r_offset;
12912 outrel.r_addend = 0;
12913 if (bfd_link_pic(info))
12914 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12915 else
12916 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12917
12918 bfd_put_32 (input_bfd, sgot->output_section->vma
12919 + sgot->output_offset + offset, hit_data);
12920
12921 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12922 arm_elf_fill_funcdesc(output_bfd, info,
12923 &eh->fdpic_cnts.funcdesc_offset,
12924 dynindx, offset, addr, dynreloc_value, seg);
12925 }
12926 else
12927 {
12928 Elf_Internal_Rela outrel;
12929
12930 /* Add a dynamic relocation. */
12931 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12932 outrel.r_offset = input_section->output_section->vma
12933 + input_section->output_offset + rel->r_offset;
12934 outrel.r_addend = 0;
12935 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12936 }
12937 }
12938 }
12939 *unresolved_reloc_p = FALSE;
12940 return bfd_reloc_ok;
12941
e5d6e09e
AV		 12942 case R_ARM_THM_BF16:
12943 {
12944 bfd_vma relocation;
12945 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12946 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12947
12948 if (globals->use_rel)
12949 {
12950 bfd_vma immA = (upper_insn & 0x001f);
12951 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12952 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12953 addend = (immA << 12);
12954 addend |= (immB << 2);
12955 addend |= (immC << 1);
12956 addend |= 1;
12957 /* Sign extend. */
12958 addend = (addend & 0x10000) ? addend - (1 << 17) : addend;
12959 }
12960
12961 value = get_value_helper (plt_offset, splt, input_section, sym_sec, h,
12962 info, input_bfd, rel, sym_name, st_type,
12963 globals, unresolved_reloc_p);
12964
12965 relocation = value + addend;
12966 relocation -= (input_section->output_section->vma
12967 + input_section->output_offset
12968 + rel->r_offset);
12969
12970 /* Put RELOCATION back into the insn. */
12971 {
12972 bfd_vma immA = (relocation & 0x0001f000) >> 12;
12973 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12974 bfd_vma immC = (relocation & 0x00000002) >> 1;
12975
12976 upper_insn = (upper_insn & 0xffe0) | immA;
12977 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
12978 }
12979
12980 /* Put the relocated value back in the object file: */
12981 bfd_put_16 (input_bfd, upper_insn, hit_data);
12982 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12983
12984 return bfd_reloc_ok;
12985 }
12986
1caf72a5
AV		 12987 case R_ARM_THM_BF18:
12988 {
12989 bfd_vma relocation;
12990 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12991 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12992
12993 if (globals->use_rel)
12994 {
12995 bfd_vma immA = (upper_insn & 0x007f);
12996 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12997 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12998 addend = (immA << 12);
12999 addend |= (immB << 2);
13000 addend |= (immC << 1);
13001 addend |= 1;
13002 /* Sign extend. */
13003 addend = (addend & 0x40000) ? addend - (1 << 19) : addend;
13004 }
13005
13006 value = get_value_helper (plt_offset, splt, input_section, sym_sec, h,
13007 info, input_bfd, rel, sym_name, st_type,
13008 globals, unresolved_reloc_p);
13009
13010 relocation = value + addend;
13011 relocation -= (input_section->output_section->vma
13012 + input_section->output_offset
13013 + rel->r_offset);
13014
13015 /* Put RELOCATION back into the insn. */
13016 {
13017 bfd_vma immA = (relocation & 0x0007f000) >> 12;
13018 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
13019 bfd_vma immC = (relocation & 0x00000002) >> 1;
13020
13021 upper_insn = (upper_insn & 0xff80) | immA;
13022 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
13023 }
13024
13025 /* Put the relocated value back in the object file: */
13026 bfd_put_16 (input_bfd, upper_insn, hit_data);
13027 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
13028
13029 return bfd_reloc_ok;
13030 }
13031
252b5132
RH		 13032 default:
13033 return bfd_reloc_notsupported;
13034 }
13035}
13036
98c1d4aa
NC		 13037/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
13038static void
07d6d2b8
AM		 13039arm_add_to_rel (bfd * abfd,
13040 bfd_byte * address,
57e8b36a 13041 reloc_howto_type * howto,
07d6d2b8 13042 bfd_signed_vma increment)
98c1d4aa 13043{
98c1d4aa
NC		 13044 bfd_signed_vma addend;
13045
bd97cb95
DJ		 13046 if (howto->type == R_ARM_THM_CALL
13047 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 13048 {
9a5aca8c
AM		 13049 int upper_insn, lower_insn;
13050 int upper, lower;
98c1d4aa 13051
9a5aca8c
AM		 13052 upper_insn = bfd_get_16 (abfd, address);
13053 lower_insn = bfd_get_16 (abfd, address + 2);
13054 upper = upper_insn & 0x7ff;
13055 lower = lower_insn & 0x7ff;
13056
13057 addend = (upper << 12) | (lower << 1);
ddda4409 13058 addend += increment;
9a5aca8c 13059 addend >>= 1;
98c1d4aa 13060
9a5aca8c
AM		 13061 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
13062 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
13063
dc810e39
AM		 13064 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
13065 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 13066 }
13067 else
13068 {
07d6d2b8 13069 bfd_vma contents;
9a5aca8c
AM		 13070
13071 contents = bfd_get_32 (abfd, address);
13072
13073 /* Get the (signed) value from the instruction. */
13074 addend = contents & howto->src_mask;
13075 if (addend & ((howto->src_mask + 1) >> 1))
13076 {
13077 bfd_signed_vma mask;
13078
13079 mask = -1;
13080 mask &= ~ howto->src_mask;
13081 addend |= mask;
13082 }
13083
13084 /* Add in the increment, (which is a byte value). */
13085 switch (howto->type)
13086 {
13087 default:
13088 addend += increment;
13089 break;
13090
13091 case R_ARM_PC24:
c6596c5e 13092 case R_ARM_PLT32:
5b5bb741
PB		 13093 case R_ARM_CALL:
13094 case R_ARM_JUMP24:
9a5aca8c 13095 addend <<= howto->size;
dc810e39 13096 addend += increment;
9a5aca8c
AM		 13097
13098 /* Should we check for overflow here ? */
13099
13100 /* Drop any undesired bits. */
13101 addend >>= howto->rightshift;
13102 break;
13103 }
13104
13105 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
13106
13107 bfd_put_32 (abfd, contents, address);
ddda4409 13108 }
98c1d4aa 13109}
252b5132 13110
ba93b8ac
DJ		 13111#define IS_ARM_TLS_RELOC(R_TYPE) \
13112 ((R_TYPE) == R_ARM_TLS_GD32 \
5c5a4843 13113 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
ba93b8ac
DJ		 13114 || (R_TYPE) == R_ARM_TLS_LDO32 \
13115 || (R_TYPE) == R_ARM_TLS_LDM32 \
5c5a4843 13116 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
ba93b8ac
DJ		 13117 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
13118 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
13119 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
13120 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b 13121 || (R_TYPE) == R_ARM_TLS_IE32 \
5c5a4843 13122 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
0855e32b
NS		 13123 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
13124
13125/* Specific set of relocations for the gnu tls dialect. */
13126#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
13127 ((R_TYPE) == R_ARM_TLS_GOTDESC \
13128 || (R_TYPE) == R_ARM_TLS_CALL \
13129 || (R_TYPE) == R_ARM_THM_TLS_CALL \
13130 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
13131 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 13132
252b5132 13133/* Relocate an ARM ELF section. */
906e58ca 13134
b34976b6 13135static bfd_boolean
07d6d2b8 13136elf32_arm_relocate_section (bfd * output_bfd,
57e8b36a 13137 struct bfd_link_info * info,
07d6d2b8
AM		 13138 bfd * input_bfd,
13139 asection * input_section,
13140 bfd_byte * contents,
13141 Elf_Internal_Rela * relocs,
13142 Elf_Internal_Sym * local_syms,
13143 asection ** local_sections)
252b5132 13144{
b34976b6
AM		 13145 Elf_Internal_Shdr *symtab_hdr;
13146 struct elf_link_hash_entry **sym_hashes;
13147 Elf_Internal_Rela *rel;
13148 Elf_Internal_Rela *relend;
13149 const char *name;
b32d3aa2 13150 struct elf32_arm_link_hash_table * globals;
252b5132 13151
4e7fd91e 13152 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13153 if (globals == NULL)
13154 return FALSE;
b491616a 13155
0ffa91dd 13156 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 13157 sym_hashes = elf_sym_hashes (input_bfd);
13158
13159 rel = relocs;
13160 relend = relocs + input_section->reloc_count;
13161 for (; rel < relend; rel++)
13162 {
07d6d2b8
AM		 13163 int r_type;
13164 reloc_howto_type * howto;
13165 unsigned long r_symndx;
13166 Elf_Internal_Sym * sym;
13167 asection * sec;
252b5132 13168 struct elf_link_hash_entry * h;
07d6d2b8
AM		 13169 bfd_vma relocation;
13170 bfd_reloc_status_type r;
13171 arelent bfd_reloc;
13172 char sym_type;
13173 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 13174 char *error_message = NULL;
f21f3fe0 13175
252b5132 13176 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 13177 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 13178 r_type = arm_real_reloc_type (globals, r_type);
252b5132 13179
ba96a88f 13180 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 13181 || r_type == R_ARM_GNU_VTINHERIT)
13182 continue;
252b5132 13183
47aeb64c
NC		 13184 howto = bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
13185
13186 if (howto == NULL)
13187 return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
252b5132 13188
252b5132
RH		 13189 h = NULL;
13190 sym = NULL;
13191 sec = NULL;
9b485d32 13192
252b5132
RH		 13193 if (r_symndx < symtab_hdr->sh_info)
13194 {
13195 sym = local_syms + r_symndx;
ba93b8ac 13196 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 13197 sec = local_sections[r_symndx];
ffcb4889
NS		 13198
13199 /* An object file might have a reference to a local
13200 undefined symbol. This is a daft object file, but we
13201 should at least do something about it. V4BX & NONE
13202 relocations do not use the symbol and are explicitly
77b4f08f
TS		 13203 allowed to use the undefined symbol, so allow those.
13204 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 13205 if (r_type != R_ARM_V4BX
13206 && r_type != R_ARM_NONE
77b4f08f 13207 && r_symndx != STN_UNDEF
ffcb4889
NS		 13208 && bfd_is_und_section (sec)
13209 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 13210 (*info->callbacks->undefined_symbol)
13211 (info, bfd_elf_string_from_elf_section
13212 (input_bfd, symtab_hdr->sh_link, sym->st_name),
13213 input_bfd, input_section,
13214 rel->r_offset, TRUE);
b38cadfb 13215
4e7fd91e 13216 if (globals->use_rel)
f8df10f4 13217 {
4e7fd91e
PB		 13218 relocation = (sec->output_section->vma
13219 + sec->output_offset
13220 + sym->st_value);
0e1862bb 13221 if (!bfd_link_relocatable (info)
ab96bf03
AM		 13222 && (sec->flags & SEC_MERGE)
13223 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 13224 {
4e7fd91e
PB		 13225 asection *msec;
13226 bfd_vma addend, value;
13227
39623e12 13228 switch (r_type)
4e7fd91e 13229 {
39623e12
PB		 13230 case R_ARM_MOVW_ABS_NC:
13231 case R_ARM_MOVT_ABS:
13232 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13233 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
13234 addend = (addend ^ 0x8000) - 0x8000;
13235 break;
f8df10f4 13236
39623e12
PB		 13237 case R_ARM_THM_MOVW_ABS_NC:
13238 case R_ARM_THM_MOVT_ABS:
13239 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
13240 << 16;
13241 value |= bfd_get_16 (input_bfd,
13242 contents + rel->r_offset + 2);
13243 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
13244 | ((value & 0x04000000) >> 15);
13245 addend = (addend ^ 0x8000) - 0x8000;
13246 break;
f8df10f4 13247
39623e12
PB		 13248 default:
13249 if (howto->rightshift
13250 || (howto->src_mask & (howto->src_mask + 1)))
13251 {
4eca0228 13252 _bfd_error_handler
695344c0 13253 /* xgettext:c-format */
2dcf00ce
AM		 13254 (_("%pB(%pA+%#" PRIx64 "): "
13255 "%s relocation against SEC_MERGE section"),
39623e12 13256 input_bfd, input_section,
2dcf00ce 13257 (uint64_t) rel->r_offset, howto->name);
39623e12
PB		 13258 return FALSE;
13259 }
13260
13261 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13262
13263 /* Get the (signed) value from the instruction. */
13264 addend = value & howto->src_mask;
13265 if (addend & ((howto->src_mask + 1) >> 1))
13266 {
13267 bfd_signed_vma mask;
13268
13269 mask = -1;
13270 mask &= ~ howto->src_mask;
13271 addend |= mask;
13272 }
13273 break;
4e7fd91e 13274 }
39623e12 13275
4e7fd91e
PB		 13276 msec = sec;
13277 addend =
13278 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
13279 - relocation;
13280 addend += msec->output_section->vma + msec->output_offset;
39623e12 13281
cc643b88 13282 /* Cases here must match those in the preceding
39623e12
PB		 13283 switch statement. */
13284 switch (r_type)
13285 {
13286 case R_ARM_MOVW_ABS_NC:
13287 case R_ARM_MOVT_ABS:
13288 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
13289 | (addend & 0xfff);
13290 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13291 break;
13292
13293 case R_ARM_THM_MOVW_ABS_NC:
13294 case R_ARM_THM_MOVT_ABS:
13295 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
13296 | (addend & 0xff) | ((addend & 0x0800) << 15);
13297 bfd_put_16 (input_bfd, value >> 16,
13298 contents + rel->r_offset);
13299 bfd_put_16 (input_bfd, value,
13300 contents + rel->r_offset + 2);
13301 break;
13302
13303 default:
13304 value = (value & ~ howto->dst_mask)
13305 | (addend & howto->dst_mask);
13306 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13307 break;
13308 }
f8df10f4 13309 }
f8df10f4 13310 }
4e7fd91e
PB		 13311 else
13312 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 13313 }
13314 else
13315 {
62d887d4 13316 bfd_boolean warned, ignored;
560e09e9 13317
b2a8e766
AM		 13318 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
13319 r_symndx, symtab_hdr, sym_hashes,
13320 h, sec, relocation,
62d887d4 13321 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 13322
13323 sym_type = h->type;
252b5132
RH		 13324 }
13325
dbaa2011 13326 if (sec != NULL && discarded_section (sec))
e4067dbb 13327 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 13328 rel, 1, relend, howto, 0, contents);
ab96bf03 13329
0e1862bb 13330 if (bfd_link_relocatable (info))
ab96bf03
AM		 13331 {
13332 /* This is a relocatable link. We don't have to change
13333 anything, unless the reloc is against a section symbol,
13334 in which case we have to adjust according to where the
13335 section symbol winds up in the output section. */
13336 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
13337 {
13338 if (globals->use_rel)
13339 arm_add_to_rel (input_bfd, contents + rel->r_offset,
13340 howto, (bfd_signed_vma) sec->output_offset);
13341 else
13342 rel->r_addend += sec->output_offset;
13343 }
13344 continue;
13345 }
13346
252b5132
RH		 13347 if (h != NULL)
13348 name = h->root.root.string;
13349 else
13350 {
13351 name = (bfd_elf_string_from_elf_section
13352 (input_bfd, symtab_hdr->sh_link, sym->st_name));
13353 if (name == NULL || *name == '\0')
13354 name = bfd_section_name (input_bfd, sec);
13355 }
f21f3fe0 13356
cf35638d 13357 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 13358 && r_type != R_ARM_NONE
13359 && (h == NULL
13360 || h->root.type == bfd_link_hash_defined
13361 || h->root.type == bfd_link_hash_defweak)
13362 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
13363 {
4eca0228 13364 _bfd_error_handler
ba93b8ac 13365 ((sym_type == STT_TLS
695344c0 13366 /* xgettext:c-format */
2dcf00ce 13367 ? _("%pB(%pA+%#" PRIx64 "): %s used with TLS symbol %s")
695344c0 13368 /* xgettext:c-format */
2dcf00ce 13369 : _("%pB(%pA+%#" PRIx64 "): %s used with non-TLS symbol %s")),
ba93b8ac
DJ		 13370 input_bfd,
13371 input_section,
2dcf00ce 13372 (uint64_t) rel->r_offset,
ba93b8ac
DJ		 13373 howto->name,
13374 name);
13375 }
13376
0855e32b 13377 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 13378 done, i.e., the relaxation produced the final output we want,
13379 and we won't let anybody mess with it. Also, we have to do
13380 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 13381 both in relaxed and non-relaxed cases. */
39d911fc
TP		 13382 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
13383 || (IS_ARM_TLS_GNU_RELOC (r_type)
13384 && !((h ? elf32_arm_hash_entry (h)->tls_type :
13385 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
13386 & GOT_TLS_GDESC)))
13387 {
13388 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
13389 contents, rel, h == NULL);
13390 /* This may have been marked unresolved because it came from
13391 a shared library. But we've just dealt with that. */
13392 unresolved_reloc = 0;
13393 }
13394 else
13395 r = bfd_reloc_continue;
b38cadfb 13396
39d911fc
TP		 13397 if (r == bfd_reloc_continue)
13398 {
13399 unsigned char branch_type =
13400 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
13401 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
13402
13403 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
13404 input_section, contents, rel,
13405 relocation, info, sec, name,
13406 sym_type, branch_type, h,
13407 &unresolved_reloc,
13408 &error_message);
13409 }
0945cdfd
DJ		 13410
13411 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13412 because such sections are not SEC_ALLOC and thus ld.so will
13413 not process them. */
13414 if (unresolved_reloc
99059e56
RM		 13415 && !((input_section->flags & SEC_DEBUGGING) != 0
13416 && h->def_dynamic)
1d5316ab
AM		 13417 && _bfd_elf_section_offset (output_bfd, info, input_section,
13418 rel->r_offset) != (bfd_vma) -1)
0945cdfd 13419 {
4eca0228 13420 _bfd_error_handler
695344c0 13421 /* xgettext:c-format */
2dcf00ce
AM		 13422 (_("%pB(%pA+%#" PRIx64 "): "
13423 "unresolvable %s relocation against symbol `%s'"),
843fe662
L		 13424 input_bfd,
13425 input_section,
2dcf00ce 13426 (uint64_t) rel->r_offset,
843fe662
L		 13427 howto->name,
13428 h->root.root.string);
0945cdfd
DJ		 13429 return FALSE;
13430 }
252b5132
RH		 13431
13432 if (r != bfd_reloc_ok)
13433 {
252b5132
RH		 13434 switch (r)
13435 {
13436 case bfd_reloc_overflow:
cf919dfd
PB		 13437 /* If the overflowing reloc was to an undefined symbol,
13438 we have already printed one error message and there
13439 is no point complaining again. */
1a72702b
AM		 13440 if (!h || h->root.type != bfd_link_hash_undefined)
13441 (*info->callbacks->reloc_overflow)
13442 (info, (h ? &h->root : NULL), name, howto->name,
13443 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13444 break;
13445
13446 case bfd_reloc_undefined:
1a72702b
AM		 13447 (*info->callbacks->undefined_symbol)
13448 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 13449 break;
13450
13451 case bfd_reloc_outofrange:
f2a9dd69 13452 error_message = _("out of range");
252b5132
RH		 13453 goto common_error;
13454
13455 case bfd_reloc_notsupported:
f2a9dd69 13456 error_message = _("unsupported relocation");
252b5132
RH		 13457 goto common_error;
13458
13459 case bfd_reloc_dangerous:
f2a9dd69 13460 /* error_message should already be set. */
252b5132
RH		 13461 goto common_error;
13462
13463 default:
f2a9dd69 13464 error_message = _("unknown error");
8029a119 13465 /* Fall through. */
252b5132
RH		 13466
13467 common_error:
f2a9dd69 13468 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 13469 (*info->callbacks->reloc_dangerous)
13470 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13471 break;
13472 }
13473 }
13474 }
13475
b34976b6 13476 return TRUE;
252b5132
RH		 13477}
13478
91d6fa6a 13479/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 13480 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 13481 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 13482 maintaining that condition). */
13483
13484static void
13485add_unwind_table_edit (arm_unwind_table_edit **head,
13486 arm_unwind_table_edit **tail,
13487 arm_unwind_edit_type type,
13488 asection *linked_section,
91d6fa6a 13489 unsigned int tindex)
2468f9c9 13490{
21d799b5
NC		 13491 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
13492 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 13493
2468f9c9
PB		 13494 new_edit->type = type;
13495 new_edit->linked_section = linked_section;
91d6fa6a 13496 new_edit->index = tindex;
b38cadfb 13497
91d6fa6a 13498 if (tindex > 0)
2468f9c9
PB		 13499 {
13500 new_edit->next = NULL;
13501
13502 if (*tail)
13503 (*tail)->next = new_edit;
13504
13505 (*tail) = new_edit;
13506
13507 if (!*head)
13508 (*head) = new_edit;
13509 }
13510 else
13511 {
13512 new_edit->next = *head;
13513
13514 if (!*tail)
13515 *tail = new_edit;
13516
13517 *head = new_edit;
13518 }
13519}
13520
13521static _arm_elf_section_data *get_arm_elf_section_data (asection *);
13522
13523/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13524static void
13525adjust_exidx_size(asection *exidx_sec, int adjust)
13526{
13527 asection *out_sec;
13528
13529 if (!exidx_sec->rawsize)
13530 exidx_sec->rawsize = exidx_sec->size;
13531
13532 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
13533 out_sec = exidx_sec->output_section;
13534 /* Adjust size of output section. */
13535 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
13536}
13537
13538/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13539static void
13540insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
13541{
13542 struct _arm_elf_section_data *exidx_arm_data;
13543
13544 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13545 add_unwind_table_edit (
13546 &exidx_arm_data->u.exidx.unwind_edit_list,
13547 &exidx_arm_data->u.exidx.unwind_edit_tail,
13548 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
13549
491d01d3
YU		 13550 exidx_arm_data->additional_reloc_count++;
13551
2468f9c9
PB		 13552 adjust_exidx_size(exidx_sec, 8);
13553}
13554
13555/* Scan .ARM.exidx tables, and create a list describing edits which should be
13556 made to those tables, such that:
b38cadfb 13557
2468f9c9
PB		 13558 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13559 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 13560 codes which have been inlined into the index).
2468f9c9 13561
85fdf906
AH		 13562 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13563
2468f9c9 13564 The edits are applied when the tables are written
b38cadfb 13565 (in elf32_arm_write_section). */
2468f9c9
PB		 13566
13567bfd_boolean
13568elf32_arm_fix_exidx_coverage (asection **text_section_order,
13569 unsigned int num_text_sections,
85fdf906
AH		 13570 struct bfd_link_info *info,
13571 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 13572{
13573 bfd *inp;
13574 unsigned int last_second_word = 0, i;
13575 asection *last_exidx_sec = NULL;
13576 asection *last_text_sec = NULL;
13577 int last_unwind_type = -1;
13578
13579 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13580 text sections. */
c72f2fb2 13581 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 13582 {
13583 asection *sec;
b38cadfb 13584
2468f9c9 13585 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 13586 {
2468f9c9
PB		 13587 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
13588 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 13589
dec9d5df 13590 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 13591 continue;
b38cadfb 13592
2468f9c9
PB		 13593 if (elf_sec->linked_to)
13594 {
13595 Elf_Internal_Shdr *linked_hdr
99059e56 13596 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 13597 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 13598 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 13599
13600 if (linked_sec_arm_data == NULL)
99059e56 13601 continue;
2468f9c9
PB		 13602
13603 /* Link this .ARM.exidx section back from the text section it
99059e56 13604 describes. */
2468f9c9
PB		 13605 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
13606 }
13607 }
13608 }
13609
13610 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13611 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 13612 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 13613
13614 for (i = 0; i < num_text_sections; i++)
13615 {
13616 asection *sec = text_section_order[i];
13617 asection *exidx_sec;
13618 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
13619 struct _arm_elf_section_data *exidx_arm_data;
13620 bfd_byte *contents = NULL;
13621 int deleted_exidx_bytes = 0;
13622 bfd_vma j;
13623 arm_unwind_table_edit *unwind_edit_head = NULL;
13624 arm_unwind_table_edit *unwind_edit_tail = NULL;
13625 Elf_Internal_Shdr *hdr;
13626 bfd *ibfd;
13627
13628 if (arm_data == NULL)
99059e56 13629 continue;
2468f9c9
PB		 13630
13631 exidx_sec = arm_data->u.text.arm_exidx_sec;
13632 if (exidx_sec == NULL)
13633 {
13634 /* Section has no unwind data. */
13635 if (last_unwind_type == 0 || !last_exidx_sec)
13636 continue;
13637
13638 /* Ignore zero sized sections. */
13639 if (sec->size == 0)
13640 continue;
13641
13642 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13643 last_unwind_type = 0;
13644 continue;
13645 }
13646
22a8f80e
PB		 13647 /* Skip /DISCARD/ sections. */
13648 if (bfd_is_abs_section (exidx_sec->output_section))
13649 continue;
13650
2468f9c9
PB		 13651 hdr = &elf_section_data (exidx_sec)->this_hdr;
13652 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 13653 continue;
b38cadfb 13654
2468f9c9
PB		 13655 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13656 if (exidx_arm_data == NULL)
99059e56 13657 continue;
b38cadfb 13658
2468f9c9 13659 ibfd = exidx_sec->owner;
b38cadfb 13660
2468f9c9
PB		 13661 if (hdr->contents != NULL)
13662 contents = hdr->contents;
13663 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
13664 /* An error? */
13665 continue;
13666
ac06903d
YU		 13667 if (last_unwind_type > 0)
13668 {
13669 unsigned int first_word = bfd_get_32 (ibfd, contents);
13670 /* Add cantunwind if first unwind item does not match section
13671 start. */
13672 if (first_word != sec->vma)
13673 {
13674 insert_cantunwind_after (last_text_sec, last_exidx_sec);
13675 last_unwind_type = 0;
13676 }
13677 }
13678
2468f9c9
PB		 13679 for (j = 0; j < hdr->sh_size; j += 8)
13680 {
13681 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
13682 int unwind_type;
13683 int elide = 0;
13684
13685 /* An EXIDX_CANTUNWIND entry. */
13686 if (second_word == 1)
13687 {
13688 if (last_unwind_type == 0)
13689 elide = 1;
13690 unwind_type = 0;
13691 }
13692 /* Inlined unwinding data. Merge if equal to previous. */
13693 else if ((second_word & 0x80000000) != 0)
13694 {
85fdf906
AH		 13695 if (merge_exidx_entries
13696 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 13697 elide = 1;
13698 unwind_type = 1;
13699 last_second_word = second_word;
13700 }
13701 /* Normal table entry. In theory we could merge these too,
13702 but duplicate entries are likely to be much less common. */
13703 else
13704 unwind_type = 2;
13705
491d01d3 13706 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 13707 {
13708 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
13709 DELETE_EXIDX_ENTRY, NULL, j / 8);
13710
13711 deleted_exidx_bytes += 8;
13712 }
13713
13714 last_unwind_type = unwind_type;
13715 }
13716
13717 /* Free contents if we allocated it ourselves. */
13718 if (contents != hdr->contents)
99059e56 13719 free (contents);
2468f9c9
PB		 13720
13721 /* Record edits to be applied later (in elf32_arm_write_section). */
13722 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
13723 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 13724
2468f9c9
PB		 13725 if (deleted_exidx_bytes > 0)
13726 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
13727
13728 last_exidx_sec = exidx_sec;
13729 last_text_sec = sec;
13730 }
13731
13732 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 13733 if (!bfd_link_relocatable (info) && last_exidx_sec
13734 && last_unwind_type != 0)
2468f9c9
PB		 13735 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13736
13737 return TRUE;
13738}
13739
3e6b1042
DJ		 13740static bfd_boolean
13741elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
13742 bfd *ibfd, const char *name)
13743{
13744 asection *sec, *osec;
13745
3d4d4302 13746 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 13747 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
13748 return TRUE;
13749
13750 osec = sec->output_section;
13751 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
13752 return TRUE;
13753
13754 if (! bfd_set_section_contents (obfd, osec, sec->contents,
13755 sec->output_offset, sec->size))
13756 return FALSE;
13757
13758 return TRUE;
13759}
13760
13761static bfd_boolean
13762elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
13763{
13764 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 13765 asection *sec, *osec;
3e6b1042 13766
4dfe6ac6
NC		 13767 if (globals == NULL)
13768 return FALSE;
13769
3e6b1042
DJ		 13770 /* Invoke the regular ELF backend linker to do all the work. */
13771 if (!bfd_elf_final_link (abfd, info))
13772 return FALSE;
13773
fe33d2fa
CL		 13774 /* Process stub sections (eg BE8 encoding, ...). */
13775 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 13776 unsigned int i;
cdb21a0a
NS		 13777 for (i=0; i<htab->top_id; i++)
13778 {
13779 sec = htab->stub_group[i].stub_sec;
13780 /* Only process it once, in its link_sec slot. */
13781 if (sec && i == htab->stub_group[i].link_sec->id)
13782 {
13783 osec = sec->output_section;
13784 elf32_arm_write_section (abfd, info, sec, sec->contents);
13785 if (! bfd_set_section_contents (abfd, osec, sec->contents,
13786 sec->output_offset, sec->size))
13787 return FALSE;
13788 }
fe33d2fa 13789 }
fe33d2fa 13790
3e6b1042
DJ		 13791 /* Write out any glue sections now that we have created all the
13792 stubs. */
13793 if (globals->bfd_of_glue_owner != NULL)
13794 {
13795 if (! elf32_arm_output_glue_section (info, abfd,
13796 globals->bfd_of_glue_owner,
13797 ARM2THUMB_GLUE_SECTION_NAME))
13798 return FALSE;
13799
13800 if (! elf32_arm_output_glue_section (info, abfd,
13801 globals->bfd_of_glue_owner,
13802 THUMB2ARM_GLUE_SECTION_NAME))
13803 return FALSE;
13804
13805 if (! elf32_arm_output_glue_section (info, abfd,
13806 globals->bfd_of_glue_owner,
13807 VFP11_ERRATUM_VENEER_SECTION_NAME))
13808 return FALSE;
13809
a504d23a
LA		 13810 if (! elf32_arm_output_glue_section (info, abfd,
13811 globals->bfd_of_glue_owner,
13812 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13813 return FALSE;
13814
3e6b1042
DJ		 13815 if (! elf32_arm_output_glue_section (info, abfd,
13816 globals->bfd_of_glue_owner,
13817 ARM_BX_GLUE_SECTION_NAME))
13818 return FALSE;
13819 }
13820
13821 return TRUE;
13822}
13823
5968a7b8
NC		 13824/* Return a best guess for the machine number based on the attributes. */
13825
13826static unsigned int
13827bfd_arm_get_mach_from_attributes (bfd * abfd)
13828{
13829 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
13830
13831 switch (arch)
13832 {
c0c468d5 13833 case TAG_CPU_ARCH_PRE_V4: return bfd_mach_arm_3M;
5968a7b8
NC		 13834 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
13835 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
13836 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
13837
13838 case TAG_CPU_ARCH_V5TE:
13839 {
13840 char * name;
13841
13842 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
13843 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
13844
13845 if (name)
13846 {
13847 if (strcmp (name, "IWMMXT2") == 0)
13848 return bfd_mach_arm_iWMMXt2;
13849
13850 if (strcmp (name, "IWMMXT") == 0)
6034aab8 13851 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 13852
13853 if (strcmp (name, "XSCALE") == 0)
13854 {
13855 int wmmx;
13856
13857 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
13858 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
13859 switch (wmmx)
13860 {
13861 case 1: return bfd_mach_arm_iWMMXt;
13862 case 2: return bfd_mach_arm_iWMMXt2;
13863 default: return bfd_mach_arm_XScale;
13864 }
13865 }
5968a7b8
NC		 13866 }
13867
13868 return bfd_mach_arm_5TE;
13869 }
13870
c0c468d5
TP		 13871 case TAG_CPU_ARCH_V5TEJ:
13872 return bfd_mach_arm_5TEJ;
13873 case TAG_CPU_ARCH_V6:
13874 return bfd_mach_arm_6;
13875 case TAG_CPU_ARCH_V6KZ:
13876 return bfd_mach_arm_6KZ;
13877 case TAG_CPU_ARCH_V6T2:
13878 return bfd_mach_arm_6T2;
13879 case TAG_CPU_ARCH_V6K:
13880 return bfd_mach_arm_6K;
13881 case TAG_CPU_ARCH_V7:
13882 return bfd_mach_arm_7;
13883 case TAG_CPU_ARCH_V6_M:
13884 return bfd_mach_arm_6M;
13885 case TAG_CPU_ARCH_V6S_M:
13886 return bfd_mach_arm_6SM;
13887 case TAG_CPU_ARCH_V7E_M:
13888 return bfd_mach_arm_7EM;
13889 case TAG_CPU_ARCH_V8:
13890 return bfd_mach_arm_8;
13891 case TAG_CPU_ARCH_V8R:
13892 return bfd_mach_arm_8R;
13893 case TAG_CPU_ARCH_V8M_BASE:
13894 return bfd_mach_arm_8M_BASE;
13895 case TAG_CPU_ARCH_V8M_MAIN:
13896 return bfd_mach_arm_8M_MAIN;
031254f2
AV		 13897 case TAG_CPU_ARCH_V8_1M_MAIN:
13898 return bfd_mach_arm_8_1M_MAIN;
c0c468d5 13899
5968a7b8 13900 default:
c0c468d5
TP		 13901 /* Force entry to be added for any new known Tag_CPU_arch value. */
13902 BFD_ASSERT (arch > MAX_TAG_CPU_ARCH);
13903
13904 /* Unknown Tag_CPU_arch value. */
5968a7b8
NC		 13905 return bfd_mach_arm_unknown;
13906 }
13907}
13908
c178919b
NC		 13909/* Set the right machine number. */
13910
13911static bfd_boolean
57e8b36a 13912elf32_arm_object_p (bfd *abfd)
c178919b 13913{
5a6c6817 13914 unsigned int mach;
57e8b36a 13915
5a6c6817 13916 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 13917
5968a7b8
NC		 13918 if (mach == bfd_mach_arm_unknown)
13919 {
13920 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13921 mach = bfd_mach_arm_ep9312;
13922 else
13923 mach = bfd_arm_get_mach_from_attributes (abfd);
13924 }
c178919b 13925
5968a7b8 13926 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13927 return TRUE;
13928}
13929
fc830a83 13930/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13931
b34976b6 13932static bfd_boolean
57e8b36a 13933elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13934{
13935 if (elf_flags_init (abfd)
13936 && elf_elfheader (abfd)->e_flags != flags)
13937 {
fc830a83
NC		 13938 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13939 {
fd2ec330 13940 if (flags & EF_ARM_INTERWORK)
4eca0228 13941 _bfd_error_handler
90b6238f 13942 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
d003868e 13943 abfd);
fc830a83 13944 else
d003868e 13945 _bfd_error_handler
90b6238f 13946 (_("warning: clearing the interworking flag of %pB due to outside request"),
d003868e 13947 abfd);
fc830a83 13948 }
252b5132
RH		 13949 }
13950 else
13951 {
13952 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13953 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13954 }
13955
b34976b6 13956 return TRUE;
252b5132
RH		 13957}
13958
fc830a83 13959/* Copy backend specific data from one object module to another. */
9b485d32 13960
b34976b6 13961static bfd_boolean
57e8b36a 13962elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13963{
13964 flagword in_flags;
13965 flagword out_flags;
13966
0ffa91dd 13967 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13968 return TRUE;
252b5132 13969
fc830a83 13970 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13971 out_flags = elf_elfheader (obfd)->e_flags;
13972
fc830a83
NC		 13973 if (elf_flags_init (obfd)
13974 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13975 && in_flags != out_flags)
252b5132 13976 {
252b5132 13977 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 13978 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 13979 return FALSE;
252b5132
RH		 13980
13981 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 13982 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 13983 return FALSE;
252b5132
RH		 13984
13985 /* If the src and dest have different interworking flags
99059e56 13986 then turn off the interworking bit. */
fd2ec330 13987 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 13988 {
fd2ec330 13989 if (out_flags & EF_ARM_INTERWORK)
d003868e 13990 _bfd_error_handler
90b6238f 13991 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
d003868e 13992 obfd, ibfd);
252b5132 13993
fd2ec330 13994 in_flags &= ~EF_ARM_INTERWORK;
252b5132 13995 }
1006ba19
PB		 13996
13997 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 13998 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
13999 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 14000 }
14001
14002 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 14003 elf_flags_init (obfd) = TRUE;
252b5132 14004
e2349352 14005 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 14006}
14007
14008/* Values for Tag_ABI_PCS_R9_use. */
14009enum
14010{
14011 AEABI_R9_V6,
14012 AEABI_R9_SB,
14013 AEABI_R9_TLS,
14014 AEABI_R9_unused
14015};
14016
14017/* Values for Tag_ABI_PCS_RW_data. */
14018enum
14019{
14020 AEABI_PCS_RW_data_absolute,
14021 AEABI_PCS_RW_data_PCrel,
14022 AEABI_PCS_RW_data_SBrel,
14023 AEABI_PCS_RW_data_unused
14024};
14025
14026/* Values for Tag_ABI_enum_size. */
14027enum
14028{
14029 AEABI_enum_unused,
14030 AEABI_enum_short,
14031 AEABI_enum_wide,
14032 AEABI_enum_forced_wide
14033};
14034
104d59d1
JM		 14035/* Determine whether an object attribute tag takes an integer, a
14036 string or both. */
906e58ca 14037
104d59d1
JM		 14038static int
14039elf32_arm_obj_attrs_arg_type (int tag)
14040{
14041 if (tag == Tag_compatibility)
3483fe2e 14042 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 14043 else if (tag == Tag_nodefaults)
3483fe2e
AS		 14044 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
14045 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
14046 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 14047 else if (tag < 32)
3483fe2e 14048 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 14049 else
3483fe2e 14050 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 14051}
14052
5aa6ff7c
AS		 14053/* The ABI defines that Tag_conformance should be emitted first, and that
14054 Tag_nodefaults should be second (if either is defined). This sets those
14055 two positions, and bumps up the position of all the remaining tags to
14056 compensate. */
14057static int
14058elf32_arm_obj_attrs_order (int num)
14059{
3de4a297 14060 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 14061 return Tag_conformance;
3de4a297 14062 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 14063 return Tag_nodefaults;
14064 if ((num - 2) < Tag_nodefaults)
14065 return num - 2;
14066 if ((num - 1) < Tag_conformance)
14067 return num - 1;
14068 return num;
14069}
14070
e8b36cd1
JM		 14071/* Attribute numbers >=64 (mod 128) can be safely ignored. */
14072static bfd_boolean
14073elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
14074{
14075 if ((tag & 127) < 64)
14076 {
14077 _bfd_error_handler
90b6238f 14078 (_("%pB: unknown mandatory EABI object attribute %d"),
e8b36cd1
JM		 14079 abfd, tag);
14080 bfd_set_error (bfd_error_bad_value);
14081 return FALSE;
14082 }
14083 else
14084 {
14085 _bfd_error_handler
90b6238f 14086 (_("warning: %pB: unknown EABI object attribute %d"),
e8b36cd1
JM		 14087 abfd, tag);
14088 return TRUE;
14089 }
14090}
14091
91e22acd
AS		 14092/* Read the architecture from the Tag_also_compatible_with attribute, if any.
14093 Returns -1 if no architecture could be read. */
14094
14095static int
14096get_secondary_compatible_arch (bfd *abfd)
14097{
14098 obj_attribute *attr =
14099 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
14100
14101 /* Note: the tag and its argument below are uleb128 values, though
14102 currently-defined values fit in one byte for each. */
14103 if (attr->s
14104 && attr->s[0] == Tag_CPU_arch
14105 && (attr->s[1] & 128) != 128
14106 && attr->s[2] == 0)
14107 return attr->s[1];
14108
14109 /* This tag is "safely ignorable", so don't complain if it looks funny. */
14110 return -1;
14111}
14112
14113/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
14114 The tag is removed if ARCH is -1. */
14115
8e79c3df 14116static void
91e22acd 14117set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 14118{
91e22acd
AS		 14119 obj_attribute *attr =
14120 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 14121
91e22acd
AS		 14122 if (arch == -1)
14123 {
14124 attr->s = NULL;
14125 return;
8e79c3df 14126 }
91e22acd
AS		 14127
14128 /* Note: the tag and its argument below are uleb128 values, though
14129 currently-defined values fit in one byte for each. */
14130 if (!attr->s)
21d799b5 14131 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 14132 attr->s[0] = Tag_CPU_arch;
14133 attr->s[1] = arch;
14134 attr->s[2] = '\0';
8e79c3df
CM		 14135}
14136
91e22acd
AS		 14137/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
14138 into account. */
14139
14140static int
14141tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
14142 int newtag, int secondary_compat)
8e79c3df 14143{
91e22acd
AS		 14144#define T(X) TAG_CPU_ARCH_##X
14145 int tagl, tagh, result;
14146 const int v6t2[] =
14147 {
14148 T(V6T2), /* PRE_V4. */
14149 T(V6T2), /* V4. */
14150 T(V6T2), /* V4T. */
14151 T(V6T2), /* V5T. */
14152 T(V6T2), /* V5TE. */
14153 T(V6T2), /* V5TEJ. */
14154 T(V6T2), /* V6. */
14155 T(V7), /* V6KZ. */
14156 T(V6T2) /* V6T2. */
14157 };
14158 const int v6k[] =
14159 {
14160 T(V6K), /* PRE_V4. */
14161 T(V6K), /* V4. */
14162 T(V6K), /* V4T. */
14163 T(V6K), /* V5T. */
14164 T(V6K), /* V5TE. */
14165 T(V6K), /* V5TEJ. */
14166 T(V6K), /* V6. */
14167 T(V6KZ), /* V6KZ. */
14168 T(V7), /* V6T2. */
14169 T(V6K) /* V6K. */
14170 };
14171 const int v7[] =
14172 {
14173 T(V7), /* PRE_V4. */
14174 T(V7), /* V4. */
14175 T(V7), /* V4T. */
14176 T(V7), /* V5T. */
14177 T(V7), /* V5TE. */
14178 T(V7), /* V5TEJ. */
14179 T(V7), /* V6. */
14180 T(V7), /* V6KZ. */
14181 T(V7), /* V6T2. */
14182 T(V7), /* V6K. */
14183 T(V7) /* V7. */
14184 };
14185 const int v6_m[] =
14186 {
07d6d2b8
AM		 14187 -1, /* PRE_V4. */
14188 -1, /* V4. */
91e22acd
AS		 14189 T(V6K), /* V4T. */
14190 T(V6K), /* V5T. */
14191 T(V6K), /* V5TE. */
14192 T(V6K), /* V5TEJ. */
14193 T(V6K), /* V6. */
14194 T(V6KZ), /* V6KZ. */
14195 T(V7), /* V6T2. */
14196 T(V6K), /* V6K. */
14197 T(V7), /* V7. */
14198 T(V6_M) /* V6_M. */
14199 };
14200 const int v6s_m[] =
14201 {
07d6d2b8
AM		 14202 -1, /* PRE_V4. */
14203 -1, /* V4. */
91e22acd
AS		 14204 T(V6K), /* V4T. */
14205 T(V6K), /* V5T. */
14206 T(V6K), /* V5TE. */
14207 T(V6K), /* V5TEJ. */
14208 T(V6K), /* V6. */
14209 T(V6KZ), /* V6KZ. */
14210 T(V7), /* V6T2. */
14211 T(V6K), /* V6K. */
14212 T(V7), /* V7. */
14213 T(V6S_M), /* V6_M. */
14214 T(V6S_M) /* V6S_M. */
14215 };
9e3c6df6
PB		 14216 const int v7e_m[] =
14217 {
07d6d2b8
AM		 14218 -1, /* PRE_V4. */
14219 -1, /* V4. */
9e3c6df6
PB		 14220 T(V7E_M), /* V4T. */
14221 T(V7E_M), /* V5T. */
14222 T(V7E_M), /* V5TE. */
14223 T(V7E_M), /* V5TEJ. */
14224 T(V7E_M), /* V6. */
14225 T(V7E_M), /* V6KZ. */
14226 T(V7E_M), /* V6T2. */
14227 T(V7E_M), /* V6K. */
14228 T(V7E_M), /* V7. */
14229 T(V7E_M), /* V6_M. */
14230 T(V7E_M), /* V6S_M. */
14231 T(V7E_M) /* V7E_M. */
14232 };
bca38921
MGD		 14233 const int v8[] =
14234 {
14235 T(V8), /* PRE_V4. */
14236 T(V8), /* V4. */
14237 T(V8), /* V4T. */
14238 T(V8), /* V5T. */
14239 T(V8), /* V5TE. */
14240 T(V8), /* V5TEJ. */
14241 T(V8), /* V6. */
14242 T(V8), /* V6KZ. */
14243 T(V8), /* V6T2. */
14244 T(V8), /* V6K. */
14245 T(V8), /* V7. */
14246 T(V8), /* V6_M. */
14247 T(V8), /* V6S_M. */
14248 T(V8), /* V7E_M. */
14249 T(V8) /* V8. */
14250 };
bff0500d
TP		 14251 const int v8r[] =
14252 {
14253 T(V8R), /* PRE_V4. */
14254 T(V8R), /* V4. */
14255 T(V8R), /* V4T. */
14256 T(V8R), /* V5T. */
14257 T(V8R), /* V5TE. */
14258 T(V8R), /* V5TEJ. */
14259 T(V8R), /* V6. */
14260 T(V8R), /* V6KZ. */
14261 T(V8R), /* V6T2. */
14262 T(V8R), /* V6K. */
14263 T(V8R), /* V7. */
14264 T(V8R), /* V6_M. */
14265 T(V8R), /* V6S_M. */
14266 T(V8R), /* V7E_M. */
14267 T(V8), /* V8. */
14268 T(V8R), /* V8R. */
14269 };
2fd158eb
TP		 14270 const int v8m_baseline[] =
14271 {
14272 -1, /* PRE_V4. */
14273 -1, /* V4. */
14274 -1, /* V4T. */
14275 -1, /* V5T. */
14276 -1, /* V5TE. */
14277 -1, /* V5TEJ. */
14278 -1, /* V6. */
14279 -1, /* V6KZ. */
14280 -1, /* V6T2. */
14281 -1, /* V6K. */
14282 -1, /* V7. */
14283 T(V8M_BASE), /* V6_M. */
14284 T(V8M_BASE), /* V6S_M. */
14285 -1, /* V7E_M. */
14286 -1, /* V8. */
bff0500d 14287 -1, /* V8R. */
2fd158eb
TP		 14288 T(V8M_BASE) /* V8-M BASELINE. */
14289 };
14290 const int v8m_mainline[] =
14291 {
14292 -1, /* PRE_V4. */
14293 -1, /* V4. */
14294 -1, /* V4T. */
14295 -1, /* V5T. */
14296 -1, /* V5TE. */
14297 -1, /* V5TEJ. */
14298 -1, /* V6. */
14299 -1, /* V6KZ. */
14300 -1, /* V6T2. */
14301 -1, /* V6K. */
14302 T(V8M_MAIN), /* V7. */
14303 T(V8M_MAIN), /* V6_M. */
14304 T(V8M_MAIN), /* V6S_M. */
14305 T(V8M_MAIN), /* V7E_M. */
14306 -1, /* V8. */
bff0500d 14307 -1, /* V8R. */
2fd158eb
TP		 14308 T(V8M_MAIN), /* V8-M BASELINE. */
14309 T(V8M_MAIN) /* V8-M MAINLINE. */
14310 };
031254f2
AV		 14311 const int v8_1m_mainline[] =
14312 {
14313 -1, /* PRE_V4. */
14314 -1, /* V4. */
14315 -1, /* V4T. */
14316 -1, /* V5T. */
14317 -1, /* V5TE. */
14318 -1, /* V5TEJ. */
14319 -1, /* V6. */
14320 -1, /* V6KZ. */
14321 -1, /* V6T2. */
14322 -1, /* V6K. */
14323 T(V8_1M_MAIN), /* V7. */
14324 T(V8_1M_MAIN), /* V6_M. */
14325 T(V8_1M_MAIN), /* V6S_M. */
14326 T(V8_1M_MAIN), /* V7E_M. */
14327 -1, /* V8. */
14328 -1, /* V8R. */
14329 T(V8_1M_MAIN), /* V8-M BASELINE. */
14330 T(V8_1M_MAIN), /* V8-M MAINLINE. */
14331 -1, /* Unused (18). */
14332 -1, /* Unused (19). */
14333 -1, /* Unused (20). */
14334 T(V8_1M_MAIN) /* V8.1-M MAINLINE. */
14335 };
91e22acd
AS		 14336 const int v4t_plus_v6_m[] =
14337 {
14338 -1, /* PRE_V4. */
14339 -1, /* V4. */
14340 T(V4T), /* V4T. */
14341 T(V5T), /* V5T. */
14342 T(V5TE), /* V5TE. */
14343 T(V5TEJ), /* V5TEJ. */
14344 T(V6), /* V6. */
14345 T(V6KZ), /* V6KZ. */
14346 T(V6T2), /* V6T2. */
14347 T(V6K), /* V6K. */
14348 T(V7), /* V7. */
14349 T(V6_M), /* V6_M. */
14350 T(V6S_M), /* V6S_M. */
9e3c6df6 14351 T(V7E_M), /* V7E_M. */
bca38921 14352 T(V8), /* V8. */
bff0500d 14353 -1, /* V8R. */
2fd158eb
TP		 14354 T(V8M_BASE), /* V8-M BASELINE. */
14355 T(V8M_MAIN), /* V8-M MAINLINE. */
031254f2
AV		 14356 -1, /* Unused (18). */
14357 -1, /* Unused (19). */
14358 -1, /* Unused (20). */
14359 T(V8_1M_MAIN), /* V8.1-M MAINLINE. */
91e22acd
AS		 14360 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
14361 };
14362 const int *comb[] =
14363 {
14364 v6t2,
14365 v6k,
14366 v7,
14367 v6_m,
14368 v6s_m,
9e3c6df6 14369 v7e_m,
bca38921 14370 v8,
bff0500d 14371 v8r,
2fd158eb
TP		 14372 v8m_baseline,
14373 v8m_mainline,
031254f2
AV		 14374 NULL,
14375 NULL,
14376 NULL,
14377 v8_1m_mainline,
91e22acd
AS		 14378 /* Pseudo-architecture. */
14379 v4t_plus_v6_m
14380 };
14381
14382 /* Check we've not got a higher architecture than we know about. */
14383
9e3c6df6 14384 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 14385 {
90b6238f 14386 _bfd_error_handler (_("error: %pB: unknown CPU architecture"), ibfd);
91e22acd
AS		 14387 return -1;
14388 }
14389
14390 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14391
14392 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
14393 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
14394 oldtag = T(V4T_PLUS_V6_M);
14395
14396 /* And override the new tag if we have a Tag_also_compatible_with on the
14397 input. */
14398
14399 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
14400 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
14401 newtag = T(V4T_PLUS_V6_M);
14402
14403 tagl = (oldtag < newtag) ? oldtag : newtag;
14404 result = tagh = (oldtag > newtag) ? oldtag : newtag;
14405
14406 /* Architectures before V6KZ add features monotonically. */
14407 if (tagh <= TAG_CPU_ARCH_V6KZ)
14408 return result;
14409
4ed7ed8d 14410 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 14411
14412 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14413 as the canonical version. */
14414 if (result == T(V4T_PLUS_V6_M))
14415 {
14416 result = T(V4T);
14417 *secondary_compat_out = T(V6_M);
14418 }
14419 else
14420 *secondary_compat_out = -1;
14421
14422 if (result == -1)
14423 {
90b6238f 14424 _bfd_error_handler (_("error: %pB: conflicting CPU architectures %d/%d"),
91e22acd
AS		 14425 ibfd, oldtag, newtag);
14426 return -1;
14427 }
14428
14429 return result;
14430#undef T
8e79c3df
CM		 14431}
14432
ac56ee8f
MGD		 14433/* Query attributes object to see if integer divide instructions may be
14434 present in an object. */
14435static bfd_boolean
14436elf32_arm_attributes_accept_div (const obj_attribute *attr)
14437{
14438 int arch = attr[Tag_CPU_arch].i;
14439 int profile = attr[Tag_CPU_arch_profile].i;
14440
14441 switch (attr[Tag_DIV_use].i)
14442 {
14443 case 0:
14444 /* Integer divide allowed if instruction contained in archetecture. */
14445 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
14446 return TRUE;
14447 else if (arch >= TAG_CPU_ARCH_V7E_M)
14448 return TRUE;
14449 else
14450 return FALSE;
14451
14452 case 1:
14453 /* Integer divide explicitly prohibited. */
14454 return FALSE;
14455
14456 default:
14457 /* Unrecognised case - treat as allowing divide everywhere. */
14458 case 2:
14459 /* Integer divide allowed in ARM state. */
14460 return TRUE;
14461 }
14462}
14463
14464/* Query attributes object to see if integer divide instructions are
14465 forbidden to be in the object. This is not the inverse of
14466 elf32_arm_attributes_accept_div. */
14467static bfd_boolean
14468elf32_arm_attributes_forbid_div (const obj_attribute *attr)
14469{
14470 return attr[Tag_DIV_use].i == 1;
14471}
14472
ee065d83
PB		 14473/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14474 are conflicting attributes. */
906e58ca 14475
ee065d83 14476static bfd_boolean
50e03d47 14477elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 14478{
50e03d47 14479 bfd *obfd = info->output_bfd;
104d59d1
JM		 14480 obj_attribute *in_attr;
14481 obj_attribute *out_attr;
ee065d83
PB		 14482 /* Some tags have 0 = don't care, 1 = strong requirement,
14483 2 = weak requirement. */
91e22acd 14484 static const int order_021[3] = {0, 2, 1};
ee065d83 14485 int i;
91e22acd 14486 bfd_boolean result = TRUE;
9274e9de 14487 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 14488
3e6b1042
DJ		 14489 /* Skip the linker stubs file. This preserves previous behavior
14490 of accepting unknown attributes in the first input file - but
14491 is that a bug? */
14492 if (ibfd->flags & BFD_LINKER_CREATED)
14493 return TRUE;
14494
9274e9de
TG		 14495 /* Skip any input that hasn't attribute section.
14496 This enables to link object files without attribute section with
14497 any others. */
14498 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
14499 return TRUE;
14500
104d59d1 14501 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 14502 {
14503 /* This is the first object. Copy the attributes. */
104d59d1 14504 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 14505
cd21e546
MGD		 14506 out_attr = elf_known_obj_attributes_proc (obfd);
14507
004ae526
PB		 14508 /* Use the Tag_null value to indicate the attributes have been
14509 initialized. */
cd21e546 14510 out_attr[0].i = 1;
004ae526 14511
cd21e546
MGD		 14512 /* We do not output objects with Tag_MPextension_use_legacy - we move
14513 the attribute's value to Tag_MPextension_use. */
14514 if (out_attr[Tag_MPextension_use_legacy].i != 0)
14515 {
14516 if (out_attr[Tag_MPextension_use].i != 0
14517 && out_attr[Tag_MPextension_use_legacy].i
99059e56 14518 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 14519 {
14520 _bfd_error_handler
871b3ab2 14521 (_("Error: %pB has both the current and legacy "
cd21e546
MGD		 14522 "Tag_MPextension_use attributes"), ibfd);
14523 result = FALSE;
14524 }
14525
14526 out_attr[Tag_MPextension_use] =
14527 out_attr[Tag_MPextension_use_legacy];
14528 out_attr[Tag_MPextension_use_legacy].type = 0;
14529 out_attr[Tag_MPextension_use_legacy].i = 0;
14530 }
14531
14532 return result;
ee065d83
PB		 14533 }
14534
104d59d1
JM		 14535 in_attr = elf_known_obj_attributes_proc (ibfd);
14536 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 14537 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14538 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
14539 {
5c294fee
TG		 14540 /* Ignore mismatches if the object doesn't use floating point or is
14541 floating point ABI independent. */
14542 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
14543 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14544 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 14545 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 14546 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14547 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 14548 {
14549 _bfd_error_handler
871b3ab2 14550 (_("error: %pB uses VFP register arguments, %pB does not"),
deddc40b
NS		 14551 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
14552 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 14553 result = FALSE;
ee065d83
PB		 14554 }
14555 }
14556
3de4a297 14557 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 14558 {
14559 /* Merge this attribute with existing attributes. */
14560 switch (i)
14561 {
14562 case Tag_CPU_raw_name:
14563 case Tag_CPU_name:
6a631e86 14564 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 14565 break;
14566
14567 case Tag_ABI_optimization_goals:
14568 case Tag_ABI_FP_optimization_goals:
14569 /* Use the first value seen. */
14570 break;
14571
14572 case Tag_CPU_arch:
91e22acd
AS		 14573 {
14574 int secondary_compat = -1, secondary_compat_out = -1;
14575 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 14576 int arch_attr;
14577 static const char *name_table[] =
14578 {
91e22acd
AS		 14579 /* These aren't real CPU names, but we can't guess
14580 that from the architecture version alone. */
14581 "Pre v4",
14582 "ARM v4",
14583 "ARM v4T",
14584 "ARM v5T",
14585 "ARM v5TE",
14586 "ARM v5TEJ",
14587 "ARM v6",
14588 "ARM v6KZ",
14589 "ARM v6T2",
14590 "ARM v6K",
14591 "ARM v7",
14592 "ARM v6-M",
bca38921 14593 "ARM v6S-M",
2fd158eb
TP		 14594 "ARM v8",
14595 "",
14596 "ARM v8-M.baseline",
14597 "ARM v8-M.mainline",
91e22acd
AS		 14598 };
14599
14600 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14601 secondary_compat = get_secondary_compatible_arch (ibfd);
14602 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 14603 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
14604 &secondary_compat_out,
14605 in_attr[i].i,
14606 secondary_compat);
14607
14608 /* Return with error if failed to merge. */
14609 if (arch_attr == -1)
14610 return FALSE;
14611
14612 out_attr[i].i = arch_attr;
14613
91e22acd
AS		 14614 set_secondary_compatible_arch (obfd, secondary_compat_out);
14615
14616 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14617 if (out_attr[i].i == saved_out_attr)
14618 ; /* Leave the names alone. */
14619 else if (out_attr[i].i == in_attr[i].i)
14620 {
14621 /* The output architecture has been changed to match the
14622 input architecture. Use the input names. */
14623 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
14624 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
14625 : NULL;
14626 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
14627 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
14628 : NULL;
14629 }
14630 else
14631 {
14632 out_attr[Tag_CPU_name].s = NULL;
14633 out_attr[Tag_CPU_raw_name].s = NULL;
14634 }
14635
14636 /* If we still don't have a value for Tag_CPU_name,
14637 make one up now. Tag_CPU_raw_name remains blank. */
14638 if (out_attr[Tag_CPU_name].s == NULL
14639 && out_attr[i].i < ARRAY_SIZE (name_table))
14640 out_attr[Tag_CPU_name].s =
14641 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
14642 }
14643 break;
14644
ee065d83
PB		 14645 case Tag_ARM_ISA_use:
14646 case Tag_THUMB_ISA_use:
ee065d83 14647 case Tag_WMMX_arch:
91e22acd
AS		 14648 case Tag_Advanced_SIMD_arch:
14649 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 14650 case Tag_ABI_FP_rounding:
ee065d83
PB		 14651 case Tag_ABI_FP_exceptions:
14652 case Tag_ABI_FP_user_exceptions:
14653 case Tag_ABI_FP_number_model:
75375b3e 14654 case Tag_FP_HP_extension:
91e22acd
AS		 14655 case Tag_CPU_unaligned_access:
14656 case Tag_T2EE_use:
91e22acd 14657 case Tag_MPextension_use:
ee065d83
PB		 14658 /* Use the largest value specified. */
14659 if (in_attr[i].i > out_attr[i].i)
14660 out_attr[i].i = in_attr[i].i;
14661 break;
14662
75375b3e 14663 case Tag_ABI_align_preserved:
91e22acd
AS		 14664 case Tag_ABI_PCS_RO_data:
14665 /* Use the smallest value specified. */
14666 if (in_attr[i].i < out_attr[i].i)
14667 out_attr[i].i = in_attr[i].i;
14668 break;
14669
75375b3e 14670 case Tag_ABI_align_needed:
91e22acd 14671 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 14672 && (in_attr[Tag_ABI_align_preserved].i == 0
14673 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 14674 {
91e22acd
AS		 14675 /* This error message should be enabled once all non-conformant
14676 binaries in the toolchain have had the attributes set
14677 properly.
ee065d83 14678 _bfd_error_handler
871b3ab2 14679 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
91e22acd
AS		 14680 obfd, ibfd);
14681 result = FALSE; */
ee065d83 14682 }
91e22acd
AS		 14683 /* Fall through. */
14684 case Tag_ABI_FP_denormal:
14685 case Tag_ABI_PCS_GOT_use:
14686 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14687 value if greater than 2 (for future-proofing). */
14688 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
14689 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
14690 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 14691 out_attr[i].i = in_attr[i].i;
14692 break;
91e22acd 14693
75375b3e
MGD		 14694 case Tag_Virtualization_use:
14695 /* The virtualization tag effectively stores two bits of
14696 information: the intended use of TrustZone (in bit 0), and the
14697 intended use of Virtualization (in bit 1). */
14698 if (out_attr[i].i == 0)
14699 out_attr[i].i = in_attr[i].i;
14700 else if (in_attr[i].i != 0
14701 && in_attr[i].i != out_attr[i].i)
14702 {
14703 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
14704 out_attr[i].i = 3;
14705 else
14706 {
14707 _bfd_error_handler
871b3ab2
AM		 14708 (_("error: %pB: unable to merge virtualization attributes "
14709 "with %pB"),
75375b3e
MGD		 14710 obfd, ibfd);
14711 result = FALSE;
14712 }
14713 }
14714 break;
91e22acd
AS		 14715
14716 case Tag_CPU_arch_profile:
14717 if (out_attr[i].i != in_attr[i].i)
14718 {
14719 /* 0 will merge with anything.
14720 'A' and 'S' merge to 'A'.
14721 'R' and 'S' merge to 'R'.
99059e56 14722 'M' and 'A|R|S' is an error. */
91e22acd
AS		 14723 if (out_attr[i].i == 0
14724 || (out_attr[i].i == 'S'
14725 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
14726 out_attr[i].i = in_attr[i].i;
14727 else if (in_attr[i].i == 0
14728 || (in_attr[i].i == 'S'
14729 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 14730 ; /* Do nothing. */
91e22acd
AS		 14731 else
14732 {
14733 _bfd_error_handler
90b6238f 14734 (_("error: %pB: conflicting architecture profiles %c/%c"),
91e22acd
AS		 14735 ibfd,
14736 in_attr[i].i ? in_attr[i].i : '0',
14737 out_attr[i].i ? out_attr[i].i : '0');
14738 result = FALSE;
14739 }
14740 }
14741 break;
15afaa63
TP		 14742
14743 case Tag_DSP_extension:
14744 /* No need to change output value if any of:
14745 - pre (<=) ARMv5T input architecture (do not have DSP)
14746 - M input profile not ARMv7E-M and do not have DSP. */
14747 if (in_attr[Tag_CPU_arch].i <= 3
14748 || (in_attr[Tag_CPU_arch_profile].i == 'M'
14749 && in_attr[Tag_CPU_arch].i != 13
14750 && in_attr[i].i == 0))
14751 ; /* Do nothing. */
14752 /* Output value should be 0 if DSP part of architecture, ie.
14753 - post (>=) ARMv5te architecture output
14754 - A, R or S profile output or ARMv7E-M output architecture. */
14755 else if (out_attr[Tag_CPU_arch].i >= 4
14756 && (out_attr[Tag_CPU_arch_profile].i == 'A'
14757 || out_attr[Tag_CPU_arch_profile].i == 'R'
14758 || out_attr[Tag_CPU_arch_profile].i == 'S'
14759 || out_attr[Tag_CPU_arch].i == 13))
14760 out_attr[i].i = 0;
14761 /* Otherwise, DSP instructions are added and not part of output
14762 architecture. */
14763 else
14764 out_attr[i].i = 1;
14765 break;
14766
75375b3e 14767 case Tag_FP_arch:
62f3b8c8 14768 {
4547cb56
NC		 14769 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14770 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14771 when it's 0. It might mean absence of FP hardware if
99654aaf 14772 Tag_FP_arch is zero. */
4547cb56 14773
a715796b 14774#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 14775 static const struct
14776 {
14777 int ver;
14778 int regs;
bca38921 14779 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 14780 {
14781 {0, 0},
14782 {1, 16},
14783 {2, 16},
14784 {3, 32},
14785 {3, 16},
14786 {4, 32},
bca38921 14787 {4, 16},
a715796b
TG		 14788 {8, 32},
14789 {8, 16}
62f3b8c8
PB		 14790 };
14791 int ver;
14792 int regs;
14793 int newval;
14794
4547cb56
NC		 14795 /* If the output has no requirement about FP hardware,
14796 follow the requirement of the input. */
14797 if (out_attr[i].i == 0)
14798 {
4ec192e6
RE		 14799 /* This assert is still reasonable, we shouldn't
14800 produce the suspicious build attribute
14801 combination (See below for in_attr). */
4547cb56
NC		 14802 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
14803 out_attr[i].i = in_attr[i].i;
14804 out_attr[Tag_ABI_HardFP_use].i
14805 = in_attr[Tag_ABI_HardFP_use].i;
14806 break;
14807 }
14808 /* If the input has no requirement about FP hardware, do
14809 nothing. */
14810 else if (in_attr[i].i == 0)
14811 {
4ec192e6
RE		 14812 /* We used to assert that Tag_ABI_HardFP_use was
14813 zero here, but we should never assert when
14814 consuming an object file that has suspicious
14815 build attributes. The single precision variant
14816 of 'no FP architecture' is still 'no FP
14817 architecture', so we just ignore the tag in this
14818 case. */
4547cb56
NC		 14819 break;
14820 }
14821
14822 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 14823 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 14824
14825 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14826 do nothing. */
14827 if (in_attr[Tag_ABI_HardFP_use].i == 0
14828 && out_attr[Tag_ABI_HardFP_use].i == 0)
14829 ;
14830 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 14831 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 14832 else if (in_attr[Tag_ABI_HardFP_use].i
14833 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 14834 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 14835
14836 /* Now we can handle Tag_FP_arch. */
14837
bca38921
MGD		 14838 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14839 pick the biggest. */
14840 if (in_attr[i].i >= VFP_VERSION_COUNT
14841 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 14842 {
14843 out_attr[i] = in_attr[i];
14844 break;
14845 }
14846 /* The output uses the superset of input features
14847 (ISA version) and registers. */
14848 ver = vfp_versions[in_attr[i].i].ver;
14849 if (ver < vfp_versions[out_attr[i].i].ver)
14850 ver = vfp_versions[out_attr[i].i].ver;
14851 regs = vfp_versions[in_attr[i].i].regs;
14852 if (regs < vfp_versions[out_attr[i].i].regs)
14853 regs = vfp_versions[out_attr[i].i].regs;
14854 /* This assumes all possible supersets are also a valid
99059e56 14855 options. */
bca38921 14856 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 14857 {
14858 if (regs == vfp_versions[newval].regs
14859 && ver == vfp_versions[newval].ver)
14860 break;
14861 }
14862 out_attr[i].i = newval;
14863 }
b1cc4aeb 14864 break;
ee065d83
PB		 14865 case Tag_PCS_config:
14866 if (out_attr[i].i == 0)
14867 out_attr[i].i = in_attr[i].i;
b6009aca 14868 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 14869 {
14870 /* It's sometimes ok to mix different configs, so this is only
99059e56 14871 a warning. */
ee065d83 14872 _bfd_error_handler
90b6238f 14873 (_("warning: %pB: conflicting platform configuration"), ibfd);
ee065d83
PB		 14874 }
14875 break;
14876 case Tag_ABI_PCS_R9_use:
004ae526
PB		 14877 if (in_attr[i].i != out_attr[i].i
14878 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 14879 && in_attr[i].i != AEABI_R9_unused)
14880 {
14881 _bfd_error_handler
90b6238f 14882 (_("error: %pB: conflicting use of R9"), ibfd);
91e22acd 14883 result = FALSE;
ee065d83
PB		 14884 }
14885 if (out_attr[i].i == AEABI_R9_unused)
14886 out_attr[i].i = in_attr[i].i;
14887 break;
14888 case Tag_ABI_PCS_RW_data:
14889 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
14890 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
14891 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
14892 {
14893 _bfd_error_handler
871b3ab2 14894 (_("error: %pB: SB relative addressing conflicts with use of R9"),
ee065d83 14895 ibfd);
91e22acd 14896 result = FALSE;
ee065d83
PB		 14897 }
14898 /* Use the smallest value specified. */
14899 if (in_attr[i].i < out_attr[i].i)
14900 out_attr[i].i = in_attr[i].i;
14901 break;
ee065d83 14902 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 14903 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
14904 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 14905 {
14906 _bfd_error_handler
871b3ab2 14907 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
a9dc9481 14908 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 14909 }
a9dc9481 14910 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 14911 out_attr[i].i = in_attr[i].i;
14912 break;
ee065d83
PB		 14913 case Tag_ABI_enum_size:
14914 if (in_attr[i].i != AEABI_enum_unused)
14915 {
14916 if (out_attr[i].i == AEABI_enum_unused
14917 || out_attr[i].i == AEABI_enum_forced_wide)
14918 {
14919 /* The existing object is compatible with anything.
14920 Use whatever requirements the new object has. */
14921 out_attr[i].i = in_attr[i].i;
14922 }
14923 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 14924 && out_attr[i].i != in_attr[i].i
0ffa91dd 14925 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 14926 {
91e22acd 14927 static const char *aeabi_enum_names[] =
bf21ed78 14928 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 14929 const char *in_name =
14930 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14931 ? aeabi_enum_names[in_attr[i].i]
14932 : "<unknown>";
14933 const char *out_name =
14934 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14935 ? aeabi_enum_names[out_attr[i].i]
14936 : "<unknown>";
ee065d83 14937 _bfd_error_handler
871b3ab2 14938 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 14939 ibfd, in_name, out_name);
ee065d83
PB		 14940 }
14941 }
14942 break;
14943 case Tag_ABI_VFP_args:
14944 /* Aready done. */
14945 break;
14946 case Tag_ABI_WMMX_args:
14947 if (in_attr[i].i != out_attr[i].i)
14948 {
14949 _bfd_error_handler
871b3ab2 14950 (_("error: %pB uses iWMMXt register arguments, %pB does not"),
ee065d83 14951 ibfd, obfd);
91e22acd 14952 result = FALSE;
ee065d83
PB		 14953 }
14954 break;
7b86a9fa
AS		 14955 case Tag_compatibility:
14956 /* Merged in target-independent code. */
14957 break;
91e22acd 14958 case Tag_ABI_HardFP_use:
4547cb56 14959 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 14960 break;
14961 case Tag_ABI_FP_16bit_format:
14962 if (in_attr[i].i != 0 && out_attr[i].i != 0)
14963 {
14964 if (in_attr[i].i != out_attr[i].i)
14965 {
14966 _bfd_error_handler
871b3ab2 14967 (_("error: fp16 format mismatch between %pB and %pB"),
91e22acd
AS		 14968 ibfd, obfd);
14969 result = FALSE;
14970 }
14971 }
14972 if (in_attr[i].i != 0)
14973 out_attr[i].i = in_attr[i].i;
14974 break;
7b86a9fa 14975
cd21e546 14976 case Tag_DIV_use:
ac56ee8f
MGD		 14977 /* A value of zero on input means that the divide instruction may
14978 be used if available in the base architecture as specified via
14979 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
14980 the user did not want divide instructions. A value of 2
14981 explicitly means that divide instructions were allowed in ARM
14982 and Thumb state. */
14983 if (in_attr[i].i == out_attr[i].i)
14984 /* Do nothing. */ ;
14985 else if (elf32_arm_attributes_forbid_div (in_attr)
14986 && !elf32_arm_attributes_accept_div (out_attr))
14987 out_attr[i].i = 1;
14988 else if (elf32_arm_attributes_forbid_div (out_attr)
14989 && elf32_arm_attributes_accept_div (in_attr))
14990 out_attr[i].i = in_attr[i].i;
14991 else if (in_attr[i].i == 2)
14992 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 14993 break;
14994
14995 case Tag_MPextension_use_legacy:
14996 /* We don't output objects with Tag_MPextension_use_legacy - we
14997 move the value to Tag_MPextension_use. */
14998 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
14999 {
15000 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
15001 {
15002 _bfd_error_handler
871b3ab2 15003 (_("%pB has both the current and legacy "
b38cadfb 15004 "Tag_MPextension_use attributes"),
cd21e546
MGD		 15005 ibfd);
15006 result = FALSE;
15007 }
15008 }
15009
15010 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
15011 out_attr[Tag_MPextension_use] = in_attr[i];
15012
15013 break;
15014
91e22acd 15015 case Tag_nodefaults:
2d0bb761
AS		 15016 /* This tag is set if it exists, but the value is unused (and is
15017 typically zero). We don't actually need to do anything here -
15018 the merge happens automatically when the type flags are merged
15019 below. */
91e22acd
AS		 15020 break;
15021 case Tag_also_compatible_with:
15022 /* Already done in Tag_CPU_arch. */
15023 break;
15024 case Tag_conformance:
15025 /* Keep the attribute if it matches. Throw it away otherwise.
15026 No attribute means no claim to conform. */
15027 if (!in_attr[i].s || !out_attr[i].s
15028 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
15029 out_attr[i].s = NULL;
15030 break;
3cfad14c 15031
91e22acd 15032 default:
e8b36cd1
JM		 15033 result
15034 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 15035 }
15036
15037 /* If out_attr was copied from in_attr then it won't have a type yet. */
15038 if (in_attr[i].type && !out_attr[i].type)
15039 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 15040 }
15041
104d59d1 15042 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 15043 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 15044 return FALSE;
ee065d83 15045
104d59d1 15046 /* Check for any attributes not known on ARM. */
e8b36cd1 15047 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 15048
91e22acd 15049 return result;
252b5132
RH		 15050}
15051
3a4a14e9
PB		 15052
15053/* Return TRUE if the two EABI versions are incompatible. */
15054
15055static bfd_boolean
15056elf32_arm_versions_compatible (unsigned iver, unsigned over)
15057{
15058 /* v4 and v5 are the same spec before and after it was released,
15059 so allow mixing them. */
15060 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
15061 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
15062 return TRUE;
15063
15064 return (iver == over);
15065}
15066
252b5132
RH		 15067/* Merge backend specific data from an object file to the output
15068 object file when linking. */
9b485d32 15069
b34976b6 15070static bfd_boolean
50e03d47 15071elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 15072
9b485d32
NC		 15073/* Display the flags field. */
15074
b34976b6 15075static bfd_boolean
57e8b36a 15076elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 15077{
fc830a83
NC		 15078 FILE * file = (FILE *) ptr;
15079 unsigned long flags;
252b5132
RH		 15080
15081 BFD_ASSERT (abfd != NULL && ptr != NULL);
15082
15083 /* Print normal ELF private data. */
15084 _bfd_elf_print_private_bfd_data (abfd, ptr);
15085
fc830a83 15086 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 15087 /* Ignore init flag - it may not be set, despite the flags field
15088 containing valid data. */
252b5132 15089
9b485d32 15090 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 15091
fc830a83
NC		 15092 switch (EF_ARM_EABI_VERSION (flags))
15093 {
15094 case EF_ARM_EABI_UNKNOWN:
4cc11e76 15095 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 15096 official ARM ELF extended ABI. Hence they are only decoded if
15097 the EABI version is not set. */
fd2ec330 15098 if (flags & EF_ARM_INTERWORK)
9b485d32 15099 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 15100
fd2ec330 15101 if (flags & EF_ARM_APCS_26)
6c571f00 15102 fprintf (file, " [APCS-26]");
fc830a83 15103 else
6c571f00 15104 fprintf (file, " [APCS-32]");
9a5aca8c 15105
96a846ea
RE		 15106 if (flags & EF_ARM_VFP_FLOAT)
15107 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 15108 else if (flags & EF_ARM_MAVERICK_FLOAT)
15109 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 15110 else
15111 fprintf (file, _(" [FPA float format]"));
15112
fd2ec330 15113 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 15114 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 15115
fd2ec330 15116 if (flags & EF_ARM_PIC)
9b485d32 15117 fprintf (file, _(" [position independent]"));
fc830a83 15118
fd2ec330 15119 if (flags & EF_ARM_NEW_ABI)
9b485d32 15120 fprintf (file, _(" [new ABI]"));
9a5aca8c 15121
fd2ec330 15122 if (flags & EF_ARM_OLD_ABI)
9b485d32 15123 fprintf (file, _(" [old ABI]"));
9a5aca8c 15124
fd2ec330 15125 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 15126 fprintf (file, _(" [software FP]"));
9a5aca8c 15127
96a846ea
RE		 15128 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
15129 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 15130 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
15131 | EF_ARM_MAVERICK_FLOAT);
fc830a83 15132 break;
9a5aca8c 15133
fc830a83 15134 case EF_ARM_EABI_VER1:
9b485d32 15135 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 15136
fc830a83 15137 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 15138 fprintf (file, _(" [sorted symbol table]"));
fc830a83 15139 else
9b485d32 15140 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 15141
fc830a83
NC		 15142 flags &= ~ EF_ARM_SYMSARESORTED;
15143 break;
9a5aca8c 15144
fd2ec330
PB		 15145 case EF_ARM_EABI_VER2:
15146 fprintf (file, _(" [Version2 EABI]"));
15147
15148 if (flags & EF_ARM_SYMSARESORTED)
15149 fprintf (file, _(" [sorted symbol table]"));
15150 else
15151 fprintf (file, _(" [unsorted symbol table]"));
15152
15153 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
15154 fprintf (file, _(" [dynamic symbols use segment index]"));
15155
15156 if (flags & EF_ARM_MAPSYMSFIRST)
15157 fprintf (file, _(" [mapping symbols precede others]"));
15158
99e4ae17 15159 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 15160 | EF_ARM_MAPSYMSFIRST);
15161 break;
15162
d507cf36
PB		 15163 case EF_ARM_EABI_VER3:
15164 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 15165 break;
15166
15167 case EF_ARM_EABI_VER4:
15168 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 15169 goto eabi;
d507cf36 15170
3a4a14e9
PB		 15171 case EF_ARM_EABI_VER5:
15172 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 15173
15174 if (flags & EF_ARM_ABI_FLOAT_SOFT)
15175 fprintf (file, _(" [soft-float ABI]"));
15176
15177 if (flags & EF_ARM_ABI_FLOAT_HARD)
15178 fprintf (file, _(" [hard-float ABI]"));
15179
15180 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
15181
3a4a14e9 15182 eabi:
d507cf36
PB		 15183 if (flags & EF_ARM_BE8)
15184 fprintf (file, _(" [BE8]"));
15185
15186 if (flags & EF_ARM_LE8)
15187 fprintf (file, _(" [LE8]"));
15188
15189 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
15190 break;
15191
fc830a83 15192 default:
9b485d32 15193 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 15194 break;
15195 }
252b5132 15196
fc830a83 15197 flags &= ~ EF_ARM_EABIMASK;
252b5132 15198
fc830a83 15199 if (flags & EF_ARM_RELEXEC)
9b485d32 15200 fprintf (file, _(" [relocatable executable]"));
252b5132 15201
18a20338
CL		 15202 if (flags & EF_ARM_PIC)
15203 fprintf (file, _(" [position independent]"));
15204
15205 if (elf_elfheader (abfd)->e_ident[EI_OSABI] == ELFOSABI_ARM_FDPIC)
15206 fprintf (file, _(" [FDPIC ABI supplement]"));
15207
15208 flags &= ~ (EF_ARM_RELEXEC | EF_ARM_PIC);
fc830a83
NC		 15209
15210 if (flags)
9b485d32 15211 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 15212
252b5132
RH		 15213 fputc ('\n', file);
15214
b34976b6 15215 return TRUE;
252b5132
RH		 15216}
15217
15218static int
57e8b36a 15219elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 15220{
2f0ca46a
NC		 15221 switch (ELF_ST_TYPE (elf_sym->st_info))
15222 {
15223 case STT_ARM_TFUNC:
15224 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 15225
2f0ca46a
NC		 15226 case STT_ARM_16BIT:
15227 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15228 This allows us to distinguish between data used by Thumb instructions
15229 and non-data (which is probably code) inside Thumb regions of an
15230 executable. */
1a0eb693 15231 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 15232 return ELF_ST_TYPE (elf_sym->st_info);
15233 break;
9a5aca8c 15234
ce855c42
NC		 15235 default:
15236 break;
2f0ca46a
NC		 15237 }
15238
15239 return type;
252b5132 15240}
f21f3fe0 15241
252b5132 15242static asection *
07adf181
AM		 15243elf32_arm_gc_mark_hook (asection *sec,
15244 struct bfd_link_info *info,
15245 Elf_Internal_Rela *rel,
15246 struct elf_link_hash_entry *h,
15247 Elf_Internal_Sym *sym)
252b5132
RH		 15248{
15249 if (h != NULL)
07adf181 15250 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 15251 {
15252 case R_ARM_GNU_VTINHERIT:
15253 case R_ARM_GNU_VTENTRY:
07adf181
AM		 15254 return NULL;
15255 }
9ad5cbcf 15256
07adf181 15257 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 15258}
15259
780a67af
NC		 15260/* Look through the relocs for a section during the first phase. */
15261
b34976b6 15262static bfd_boolean
57e8b36a
NC		 15263elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
15264 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 15265{
b34976b6
AM		 15266 Elf_Internal_Shdr *symtab_hdr;
15267 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 15268 const Elf_Internal_Rela *rel;
15269 const Elf_Internal_Rela *rel_end;
15270 bfd *dynobj;
5e681ec4 15271 asection *sreloc;
5e681ec4 15272 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 15273 bfd_boolean call_reloc_p;
15274 bfd_boolean may_become_dynamic_p;
15275 bfd_boolean may_need_local_target_p;
ce98a316 15276 unsigned long nsyms;
9a5aca8c 15277
0e1862bb 15278 if (bfd_link_relocatable (info))
b34976b6 15279 return TRUE;
9a5aca8c 15280
0ffa91dd
NC		 15281 BFD_ASSERT (is_arm_elf (abfd));
15282
5e681ec4 15283 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15284 if (htab == NULL)
15285 return FALSE;
15286
5e681ec4 15287 sreloc = NULL;
9a5aca8c 15288
67687978
PB		 15289 /* Create dynamic sections for relocatable executables so that we can
15290 copy relocations. */
15291 if (htab->root.is_relocatable_executable
15292 && ! htab->root.dynamic_sections_created)
15293 {
15294 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
15295 return FALSE;
15296 }
15297
cbc704f3
RS		 15298 if (htab->root.dynobj == NULL)
15299 htab->root.dynobj = abfd;
34e77a92
RS		 15300 if (!create_ifunc_sections (info))
15301 return FALSE;
cbc704f3
RS		 15302
15303 dynobj = htab->root.dynobj;
15304
0ffa91dd 15305 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 15306 sym_hashes = elf_sym_hashes (abfd);
ce98a316 15307 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 15308
252b5132
RH		 15309 rel_end = relocs + sec->reloc_count;
15310 for (rel = relocs; rel < rel_end; rel++)
15311 {
34e77a92 15312 Elf_Internal_Sym *isym;
252b5132 15313 struct elf_link_hash_entry *h;
b7693d02 15314 struct elf32_arm_link_hash_entry *eh;
d42c267e 15315 unsigned int r_symndx;
eb043451 15316 int r_type;
9a5aca8c 15317
252b5132 15318 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 15319 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 15320 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 15321
ce98a316
NC		 15322 if (r_symndx >= nsyms
15323 /* PR 9934: It is possible to have relocations that do not
15324 refer to symbols, thus it is also possible to have an
15325 object file containing relocations but no symbol table. */
cf35638d 15326 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 15327 {
871b3ab2 15328 _bfd_error_handler (_("%pB: bad symbol index: %d"), abfd,
4eca0228 15329 r_symndx);
ba93b8ac
DJ		 15330 return FALSE;
15331 }
15332
34e77a92
RS		 15333 h = NULL;
15334 isym = NULL;
15335 if (nsyms > 0)
973a3492 15336 {
34e77a92
RS		 15337 if (r_symndx < symtab_hdr->sh_info)
15338 {
15339 /* A local symbol. */
15340 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
15341 abfd, r_symndx);
15342 if (isym == NULL)
15343 return FALSE;
15344 }
15345 else
15346 {
15347 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
15348 while (h->root.type == bfd_link_hash_indirect
15349 || h->root.type == bfd_link_hash_warning)
15350 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15351 }
973a3492 15352 }
9a5aca8c 15353
b7693d02
DJ		 15354 eh = (struct elf32_arm_link_hash_entry *) h;
15355
f6e32f6d
RS		 15356 call_reloc_p = FALSE;
15357 may_become_dynamic_p = FALSE;
15358 may_need_local_target_p = FALSE;
15359
0855e32b
NS		 15360 /* Could be done earlier, if h were already available. */
15361 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 15362 switch (r_type)
99059e56 15363 {
e8b09b87
CL		 15364 case R_ARM_GOTOFFFUNCDESC:
15365 {
15366 if (h == NULL)
15367 {
15368 if (!elf32_arm_allocate_local_sym_info (abfd))
15369 return FALSE;
15370 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].gotofffuncdesc_cnt += 1;
15371 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15372 }
15373 else
15374 {
15375 eh->fdpic_cnts.gotofffuncdesc_cnt++;
15376 }
15377 }
15378 break;
15379
15380 case R_ARM_GOTFUNCDESC:
15381 {
15382 if (h == NULL)
15383 {
15384 /* Such a relocation is not supposed to be generated
15385 by gcc on a static function. */
15386 /* Anyway if needed it could be handled. */
15387 abort();
15388 }
15389 else
15390 {
15391 eh->fdpic_cnts.gotfuncdesc_cnt++;
15392 }
15393 }
15394 break;
15395
15396 case R_ARM_FUNCDESC:
15397 {
15398 if (h == NULL)
15399 {
15400 if (!elf32_arm_allocate_local_sym_info (abfd))
15401 return FALSE;
15402 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_cnt += 1;
15403 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15404 }
15405 else
15406 {
15407 eh->fdpic_cnts.funcdesc_cnt++;
15408 }
15409 }
15410 break;
15411
5e681ec4 15412 case R_ARM_GOT32:
eb043451 15413 case R_ARM_GOT_PREL:
ba93b8ac 15414 case R_ARM_TLS_GD32:
5c5a4843 15415 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 15416 case R_ARM_TLS_IE32:
5c5a4843 15417 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 15418 case R_ARM_TLS_GOTDESC:
15419 case R_ARM_TLS_DESCSEQ:
15420 case R_ARM_THM_TLS_DESCSEQ:
15421 case R_ARM_TLS_CALL:
15422 case R_ARM_THM_TLS_CALL:
5e681ec4 15423 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 15424 {
15425 int tls_type, old_tls_type;
5e681ec4 15426
ba93b8ac
DJ		 15427 switch (r_type)
15428 {
15429 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
5c5a4843 15430 case R_ARM_TLS_GD32_FDPIC: tls_type = GOT_TLS_GD; break;
b38cadfb 15431
ba93b8ac 15432 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
5c5a4843 15433 case R_ARM_TLS_IE32_FDPIC: tls_type = GOT_TLS_IE; break;
b38cadfb 15434
0855e32b
NS		 15435 case R_ARM_TLS_GOTDESC:
15436 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
15437 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
15438 tls_type = GOT_TLS_GDESC; break;
b38cadfb 15439
ba93b8ac
DJ		 15440 default: tls_type = GOT_NORMAL; break;
15441 }
252b5132 15442
0e1862bb 15443 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 15444 info->flags |= DF_STATIC_TLS;
15445
ba93b8ac
DJ		 15446 if (h != NULL)
15447 {
15448 h->got.refcount++;
15449 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
15450 }
15451 else
15452 {
ba93b8ac 15453 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 15454 if (!elf32_arm_allocate_local_sym_info (abfd))
15455 return FALSE;
15456 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 15457 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
15458 }
15459
0855e32b 15460 /* If a variable is accessed with both tls methods, two
99059e56 15461 slots may be created. */
0855e32b
NS		 15462 if (GOT_TLS_GD_ANY_P (old_tls_type)
15463 && GOT_TLS_GD_ANY_P (tls_type))
15464 tls_type |= old_tls_type;
15465
15466 /* We will already have issued an error message if there
15467 is a TLS/non-TLS mismatch, based on the symbol
15468 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 15469 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
15470 && tls_type != GOT_NORMAL)
15471 tls_type |= old_tls_type;
15472
0855e32b 15473 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 15474 method, we're able to relax. Turn off the GDESC flag,
15475 without messing up with any other kind of tls types
6a631e86 15476 that may be involved. */
0855e32b
NS		 15477 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
15478 tls_type &= ~GOT_TLS_GDESC;
15479
ba93b8ac
DJ		 15480 if (old_tls_type != tls_type)
15481 {
15482 if (h != NULL)
15483 elf32_arm_hash_entry (h)->tls_type = tls_type;
15484 else
15485 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
15486 }
15487 }
8029a119 15488 /* Fall through. */
ba93b8ac
DJ		 15489
15490 case R_ARM_TLS_LDM32:
5c5a4843
CL		 15491 case R_ARM_TLS_LDM32_FDPIC:
15492 if (r_type == R_ARM_TLS_LDM32 || r_type == R_ARM_TLS_LDM32_FDPIC)
ba93b8ac 15493 htab->tls_ldm_got.refcount++;
8029a119 15494 /* Fall through. */
252b5132 15495
c19d1205 15496 case R_ARM_GOTOFF32:
5e681ec4 15497 case R_ARM_GOTPC:
cbc704f3
RS		 15498 if (htab->root.sgot == NULL
15499 && !create_got_section (htab->root.dynobj, info))
15500 return FALSE;
252b5132
RH		 15501 break;
15502
252b5132 15503 case R_ARM_PC24:
7359ea65 15504 case R_ARM_PLT32:
5b5bb741
PB		 15505 case R_ARM_CALL:
15506 case R_ARM_JUMP24:
eb043451 15507 case R_ARM_PREL31:
c19d1205 15508 case R_ARM_THM_CALL:
bd97cb95
DJ		 15509 case R_ARM_THM_JUMP24:
15510 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 15511 call_reloc_p = TRUE;
15512 may_need_local_target_p = TRUE;
15513 break;
15514
15515 case R_ARM_ABS12:
15516 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15517 ldr __GOTT_INDEX__ offsets. */
15518 if (!htab->vxworks_p)
15519 {
15520 may_need_local_target_p = TRUE;
15521 break;
15522 }
aebf9be7 15523 else goto jump_over;
9eaff861 15524
f6e32f6d 15525 /* Fall through. */
39623e12 15526
96c23d59
JM		 15527 case R_ARM_MOVW_ABS_NC:
15528 case R_ARM_MOVT_ABS:
15529 case R_ARM_THM_MOVW_ABS_NC:
15530 case R_ARM_THM_MOVT_ABS:
0e1862bb 15531 if (bfd_link_pic (info))
96c23d59 15532 {
4eca0228 15533 _bfd_error_handler
871b3ab2 15534 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
96c23d59
JM		 15535 abfd, elf32_arm_howto_table_1[r_type].name,
15536 (h) ? h->root.root.string : "a local symbol");
15537 bfd_set_error (bfd_error_bad_value);
15538 return FALSE;
15539 }
15540
15541 /* Fall through. */
39623e12
PB		 15542 case R_ARM_ABS32:
15543 case R_ARM_ABS32_NOI:
aebf9be7 15544 jump_over:
0e1862bb 15545 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 15546 {
15547 h->pointer_equality_needed = 1;
15548 }
15549 /* Fall through. */
39623e12
PB		 15550 case R_ARM_REL32:
15551 case R_ARM_REL32_NOI:
b6895b4f
PB		 15552 case R_ARM_MOVW_PREL_NC:
15553 case R_ARM_MOVT_PREL:
b6895b4f
PB		 15554 case R_ARM_THM_MOVW_PREL_NC:
15555 case R_ARM_THM_MOVT_PREL:
39623e12 15556
b7693d02 15557 /* Should the interworking branches be listed here? */
e8b09b87
CL		 15558 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable
15559 || htab->fdpic_p)
34e77a92
RS		 15560 && (sec->flags & SEC_ALLOC) != 0)
15561 {
15562 if (h == NULL
469a3493 15563 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 15564 {
15565 /* In shared libraries and relocatable executables,
15566 we treat local relative references as calls;
15567 see the related SYMBOL_CALLS_LOCAL code in
15568 allocate_dynrelocs. */
15569 call_reloc_p = TRUE;
15570 may_need_local_target_p = TRUE;
15571 }
15572 else
15573 /* We are creating a shared library or relocatable
15574 executable, and this is a reloc against a global symbol,
15575 or a non-PC-relative reloc against a local symbol.
15576 We may need to copy the reloc into the output. */
15577 may_become_dynamic_p = TRUE;
15578 }
f6e32f6d
RS		 15579 else
15580 may_need_local_target_p = TRUE;
252b5132
RH		 15581 break;
15582
99059e56
RM		 15583 /* This relocation describes the C++ object vtable hierarchy.
15584 Reconstruct it for later use during GC. */
15585 case R_ARM_GNU_VTINHERIT:
15586 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
15587 return FALSE;
15588 break;
15589
15590 /* This relocation describes which C++ vtable entries are actually
15591 used. Record for later use during GC. */
15592 case R_ARM_GNU_VTENTRY:
a0ea3a14 15593 if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
99059e56
RM		 15594 return FALSE;
15595 break;
15596 }
f6e32f6d
RS		 15597
15598 if (h != NULL)
15599 {
15600 if (call_reloc_p)
15601 /* We may need a .plt entry if the function this reloc
15602 refers to is in a different object, regardless of the
15603 symbol's type. We can't tell for sure yet, because
15604 something later might force the symbol local. */
15605 h->needs_plt = 1;
15606 else if (may_need_local_target_p)
15607 /* If this reloc is in a read-only section, we might
15608 need a copy reloc. We can't check reliably at this
15609 stage whether the section is read-only, as input
15610 sections have not yet been mapped to output sections.
15611 Tentatively set the flag for now, and correct in
15612 adjust_dynamic_symbol. */
15613 h->non_got_ref = 1;
15614 }
15615
34e77a92
RS		 15616 if (may_need_local_target_p
15617 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 15618 {
34e77a92
RS		 15619 union gotplt_union *root_plt;
15620 struct arm_plt_info *arm_plt;
15621 struct arm_local_iplt_info *local_iplt;
15622
15623 if (h != NULL)
15624 {
15625 root_plt = &h->plt;
15626 arm_plt = &eh->plt;
15627 }
15628 else
15629 {
15630 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
15631 if (local_iplt == NULL)
15632 return FALSE;
15633 root_plt = &local_iplt->root;
15634 arm_plt = &local_iplt->arm;
15635 }
15636
f6e32f6d
RS		 15637 /* If the symbol is a function that doesn't bind locally,
15638 this relocation will need a PLT entry. */
a8c887dd
NC		 15639 if (root_plt->refcount != -1)
15640 root_plt->refcount += 1;
34e77a92
RS		 15641
15642 if (!call_reloc_p)
15643 arm_plt->noncall_refcount++;
f6e32f6d
RS		 15644
15645 /* It's too early to use htab->use_blx here, so we have to
15646 record possible blx references separately from
15647 relocs that definitely need a thumb stub. */
15648
15649 if (r_type == R_ARM_THM_CALL)
34e77a92 15650 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 15651
15652 if (r_type == R_ARM_THM_JUMP24
15653 || r_type == R_ARM_THM_JUMP19)
34e77a92 15654 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 15655 }
15656
15657 if (may_become_dynamic_p)
15658 {
15659 struct elf_dyn_relocs *p, **head;
15660
15661 /* Create a reloc section in dynobj. */
15662 if (sreloc == NULL)
15663 {
15664 sreloc = _bfd_elf_make_dynamic_reloc_section
15665 (sec, dynobj, 2, abfd, ! htab->use_rel);
15666
15667 if (sreloc == NULL)
15668 return FALSE;
15669
15670 /* BPABI objects never have dynamic relocations mapped. */
15671 if (htab->symbian_p)
15672 {
15673 flagword flags;
15674
15675 flags = bfd_get_section_flags (dynobj, sreloc);
15676 flags &= ~(SEC_LOAD | SEC_ALLOC);
15677 bfd_set_section_flags (dynobj, sreloc, flags);
15678 }
15679 }
15680
15681 /* If this is a global symbol, count the number of
15682 relocations we need for this symbol. */
15683 if (h != NULL)
15684 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
15685 else
15686 {
34e77a92
RS		 15687 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
15688 if (head == NULL)
f6e32f6d 15689 return FALSE;
f6e32f6d
RS		 15690 }
15691
15692 p = *head;
15693 if (p == NULL || p->sec != sec)
15694 {
15695 bfd_size_type amt = sizeof *p;
15696
15697 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
15698 if (p == NULL)
15699 return FALSE;
15700 p->next = *head;
15701 *head = p;
15702 p->sec = sec;
15703 p->count = 0;
15704 p->pc_count = 0;
15705 }
15706
469a3493 15707 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 15708 p->pc_count += 1;
15709 p->count += 1;
e8b09b87
CL		 15710 if (h == NULL && htab->fdpic_p && !bfd_link_pic(info)
15711 && r_type != R_ARM_ABS32 && r_type != R_ARM_ABS32_NOI) {
15712 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15713 that will become rofixup. */
15714 /* This is due to the fact that we suppose all will become rofixup. */
15715 fprintf(stderr, "FDPIC does not yet support %d relocation to become dynamic for executable\n", r_type);
15716 _bfd_error_handler
15717 (_("FDPIC does not yet support %s relocation"
15718 " to become dynamic for executable"),
15719 elf32_arm_howto_table_1[r_type].name);
15720 abort();
15721 }
f6e32f6d 15722 }
252b5132 15723 }
f21f3fe0 15724
b34976b6 15725 return TRUE;
252b5132
RH		 15726}
15727
9eaff861
AO		 15728static void
15729elf32_arm_update_relocs (asection *o,
15730 struct bfd_elf_section_reloc_data *reldata)
15731{
15732 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
15733 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
15734 const struct elf_backend_data *bed;
15735 _arm_elf_section_data *eado;
15736 struct bfd_link_order *p;
15737 bfd_byte *erela_head, *erela;
15738 Elf_Internal_Rela *irela_head, *irela;
15739 Elf_Internal_Shdr *rel_hdr;
15740 bfd *abfd;
15741 unsigned int count;
15742
15743 eado = get_arm_elf_section_data (o);
15744
15745 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
15746 return;
15747
15748 abfd = o->owner;
15749 bed = get_elf_backend_data (abfd);
15750 rel_hdr = reldata->hdr;
15751
15752 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
15753 {
15754 swap_in = bed->s->swap_reloc_in;
15755 swap_out = bed->s->swap_reloc_out;
15756 }
15757 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
15758 {
15759 swap_in = bed->s->swap_reloca_in;
15760 swap_out = bed->s->swap_reloca_out;
15761 }
15762 else
15763 abort ();
15764
15765 erela_head = rel_hdr->contents;
15766 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
15767 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
15768
15769 erela = erela_head;
15770 irela = irela_head;
15771 count = 0;
15772
15773 for (p = o->map_head.link_order; p; p = p->next)
15774 {
15775 if (p->type == bfd_section_reloc_link_order
15776 || p->type == bfd_symbol_reloc_link_order)
15777 {
15778 (*swap_in) (abfd, erela, irela);
15779 erela += rel_hdr->sh_entsize;
15780 irela++;
15781 count++;
15782 }
15783 else if (p->type == bfd_indirect_link_order)
15784 {
15785 struct bfd_elf_section_reloc_data *input_reldata;
15786 arm_unwind_table_edit *edit_list, *edit_tail;
15787 _arm_elf_section_data *eadi;
15788 bfd_size_type j;
15789 bfd_vma offset;
15790 asection *i;
15791
15792 i = p->u.indirect.section;
15793
15794 eadi = get_arm_elf_section_data (i);
15795 edit_list = eadi->u.exidx.unwind_edit_list;
15796 edit_tail = eadi->u.exidx.unwind_edit_tail;
15797 offset = o->vma + i->output_offset;
15798
15799 if (eadi->elf.rel.hdr &&
15800 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
15801 input_reldata = &eadi->elf.rel;
15802 else if (eadi->elf.rela.hdr &&
15803 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
15804 input_reldata = &eadi->elf.rela;
15805 else
15806 abort ();
15807
15808 if (edit_list)
15809 {
15810 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15811 {
15812 arm_unwind_table_edit *edit_node, *edit_next;
15813 bfd_vma bias;
c48182bf 15814 bfd_vma reloc_index;
9eaff861
AO		 15815
15816 (*swap_in) (abfd, erela, irela);
c48182bf 15817 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 15818
15819 bias = 0;
15820 edit_node = edit_list;
15821 for (edit_next = edit_list;
c48182bf 15822 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 15823 edit_next = edit_node->next)
15824 {
15825 bias++;
15826 edit_node = edit_next;
15827 }
15828
15829 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 15830 || edit_node->index != reloc_index)
9eaff861
AO		 15831 {
15832 irela->r_offset -= bias * 8;
15833 irela++;
15834 count++;
15835 }
15836
15837 erela += rel_hdr->sh_entsize;
15838 }
15839
15840 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
15841 {
15842 /* New relocation entity. */
15843 asection *text_sec = edit_tail->linked_section;
15844 asection *text_out = text_sec->output_section;
15845 bfd_vma exidx_offset = offset + i->size - 8;
15846
15847 irela->r_addend = 0;
15848 irela->r_offset = exidx_offset;
15849 irela->r_info = ELF32_R_INFO
15850 (text_out->target_index, R_ARM_PREL31);
15851 irela++;
15852 count++;
15853 }
15854 }
15855 else
15856 {
15857 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15858 {
15859 (*swap_in) (abfd, erela, irela);
15860 erela += rel_hdr->sh_entsize;
15861 irela++;
15862 }
15863
15864 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15865 }
15866 }
15867 }
15868
15869 reldata->count = count;
15870 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15871
15872 erela = erela_head;
15873 irela = irela_head;
15874 while (count > 0)
15875 {
15876 (*swap_out) (abfd, irela, erela);
15877 erela += rel_hdr->sh_entsize;
15878 irela++;
15879 count--;
15880 }
15881
15882 free (irela_head);
15883
15884 /* Hashes are no longer valid. */
15885 free (reldata->hashes);
15886 reldata->hashes = NULL;
15887}
15888
6a5bb875 15889/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15890 required if the corresponding code section is marked. Similarly, ARMv8-M
15891 secure entry functions can only be referenced by SG veneers which are
15892 created after the GC process. They need to be marked in case they reside in
15893 their own section (as would be the case if code was compiled with
15894 -ffunction-sections). */
6a5bb875
PB		 15895
15896static bfd_boolean
906e58ca
NC		 15897elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15898 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15899{
15900 bfd *sub;
15901 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15902 asection *cmse_sec;
15903 obj_attribute *out_attr;
15904 Elf_Internal_Shdr *symtab_hdr;
15905 unsigned i, sym_count, ext_start;
15906 const struct elf_backend_data *bed;
15907 struct elf_link_hash_entry **sym_hashes;
15908 struct elf32_arm_link_hash_entry *cmse_hash;
15909 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
6a5bb875 15910
7f6ab9f8
AM		 15911 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15912
4ba2ef8f
TP		 15913 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15914 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15915 && out_attr[Tag_CPU_arch_profile].i == 'M';
15916
6a5bb875
PB		 15917 /* Marking EH data may cause additional code sections to be marked,
15918 requiring multiple passes. */
15919 again = TRUE;
15920 while (again)
15921 {
15922 again = FALSE;
c72f2fb2 15923 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15924 {
15925 asection *o;
15926
0ffa91dd 15927 if (! is_arm_elf (sub))
6a5bb875
PB		 15928 continue;
15929
15930 elf_shdrp = elf_elfsections (sub);
15931 for (o = sub->sections; o != NULL; o = o->next)
15932 {
15933 Elf_Internal_Shdr *hdr;
0ffa91dd 15934
6a5bb875 15935 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15936 if (hdr->sh_type == SHT_ARM_EXIDX
15937 && hdr->sh_link
15938 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15939 && !o->gc_mark
15940 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15941 {
15942 again = TRUE;
15943 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15944 return FALSE;
15945 }
15946 }
4ba2ef8f
TP		 15947
15948 /* Mark section holding ARMv8-M secure entry functions. We mark all
15949 of them so no need for a second browsing. */
15950 if (is_v8m && first_bfd_browse)
15951 {
15952 sym_hashes = elf_sym_hashes (sub);
15953 bed = get_elf_backend_data (sub);
15954 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15955 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15956 ext_start = symtab_hdr->sh_info;
15957
15958 /* Scan symbols. */
15959 for (i = ext_start; i < sym_count; i++)
15960 {
15961 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15962
15963 /* Assume it is a special symbol. If not, cmse_scan will
15964 warn about it and user can do something about it. */
15965 if (ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
15966 {
15967 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 15968 if (!cmse_sec->gc_mark
15969 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f
TP		 15970 return FALSE;
15971 }
15972 }
15973 }
6a5bb875 15974 }
4ba2ef8f 15975 first_bfd_browse = FALSE;
6a5bb875
PB		 15976 }
15977
15978 return TRUE;
15979}
15980
3c9458e9
NC		 15981/* Treat mapping symbols as special target symbols. */
15982
15983static bfd_boolean
15984elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
15985{
b0796911
PB		 15986 return bfd_is_arm_special_symbol_name (sym->name,
15987 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 15988}
15989
0367ecfb
NC		 15990/* This is a copy of elf_find_function() from elf.c except that
15991 ARM mapping symbols are ignored when looking for function names
15992 and STT_ARM_TFUNC is considered to a function type. */
252b5132 15993
0367ecfb 15994static bfd_boolean
07d6d2b8 15995arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 15996 asymbol ** symbols,
fb167eb2 15997 asection * section,
07d6d2b8 15998 bfd_vma offset,
0367ecfb
NC		 15999 const char ** filename_ptr,
16000 const char ** functionname_ptr)
16001{
16002 const char * filename = NULL;
16003 asymbol * func = NULL;
16004 bfd_vma low_func = 0;
16005 asymbol ** p;
252b5132
RH		 16006
16007 for (p = symbols; *p != NULL; p++)
16008 {
16009 elf_symbol_type *q;
16010
16011 q = (elf_symbol_type *) *p;
16012
252b5132
RH		 16013 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
16014 {
16015 default:
16016 break;
16017 case STT_FILE:
16018 filename = bfd_asymbol_name (&q->symbol);
16019 break;
252b5132
RH		 16020 case STT_FUNC:
16021 case STT_ARM_TFUNC:
9d2da7ca 16022 case STT_NOTYPE:
b0796911 16023 /* Skip mapping symbols. */
0367ecfb 16024 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 16025 && bfd_is_arm_special_symbol_name (q->symbol.name,
16026 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 16027 continue;
16028 /* Fall through. */
6b40fcba 16029 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 16030 && q->symbol.value >= low_func
16031 && q->symbol.value <= offset)
16032 {
16033 func = (asymbol *) q;
16034 low_func = q->symbol.value;
16035 }
16036 break;
16037 }
16038 }
16039
16040 if (func == NULL)
b34976b6 16041 return FALSE;
252b5132 16042
0367ecfb
NC		 16043 if (filename_ptr)
16044 *filename_ptr = filename;
16045 if (functionname_ptr)
16046 *functionname_ptr = bfd_asymbol_name (func);
16047
16048 return TRUE;
906e58ca 16049}
0367ecfb
NC		 16050
16051
16052/* Find the nearest line to a particular section and offset, for error
16053 reporting. This code is a duplicate of the code in elf.c, except
16054 that it uses arm_elf_find_function. */
16055
16056static bfd_boolean
07d6d2b8
AM		 16057elf32_arm_find_nearest_line (bfd * abfd,
16058 asymbol ** symbols,
16059 asection * section,
16060 bfd_vma offset,
0367ecfb
NC		 16061 const char ** filename_ptr,
16062 const char ** functionname_ptr,
fb167eb2
AM		 16063 unsigned int * line_ptr,
16064 unsigned int * discriminator_ptr)
0367ecfb
NC		 16065{
16066 bfd_boolean found = FALSE;
16067
fb167eb2 16068 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 16069 filename_ptr, functionname_ptr,
fb167eb2
AM		 16070 line_ptr, discriminator_ptr,
16071 dwarf_debug_sections, 0,
0367ecfb
NC		 16072 & elf_tdata (abfd)->dwarf2_find_line_info))
16073 {
16074 if (!*functionname_ptr)
fb167eb2 16075 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 16076 *filename_ptr ? NULL : filename_ptr,
16077 functionname_ptr);
f21f3fe0 16078
0367ecfb
NC		 16079 return TRUE;
16080 }
16081
fb167eb2
AM		 16082 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
16083 uses DWARF1. */
16084
0367ecfb
NC		 16085 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
16086 & found, filename_ptr,
16087 functionname_ptr, line_ptr,
16088 & elf_tdata (abfd)->line_info))
16089 return FALSE;
16090
16091 if (found && (*functionname_ptr || *line_ptr))
16092 return TRUE;
16093
16094 if (symbols == NULL)
16095 return FALSE;
16096
fb167eb2 16097 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 16098 filename_ptr, functionname_ptr))
16099 return FALSE;
16100
16101 *line_ptr = 0;
b34976b6 16102 return TRUE;
252b5132
RH		 16103}
16104
4ab527b0 16105static bfd_boolean
07d6d2b8 16106elf32_arm_find_inliner_info (bfd * abfd,
4ab527b0
FF		 16107 const char ** filename_ptr,
16108 const char ** functionname_ptr,
16109 unsigned int * line_ptr)
16110{
16111 bfd_boolean found;
16112 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
16113 functionname_ptr, line_ptr,
16114 & elf_tdata (abfd)->dwarf2_find_line_info);
16115 return found;
16116}
16117
63c1f59d
AM		 16118/* Find dynamic relocs for H that apply to read-only sections. */
16119
16120static asection *
16121readonly_dynrelocs (struct elf_link_hash_entry *h)
16122{
16123 struct elf_dyn_relocs *p;
16124
16125 for (p = elf32_arm_hash_entry (h)->dyn_relocs; p != NULL; p = p->next)
16126 {
16127 asection *s = p->sec->output_section;
16128
16129 if (s != NULL && (s->flags & SEC_READONLY) != 0)
16130 return p->sec;
16131 }
16132 return NULL;
16133}
16134
252b5132
RH		 16135/* Adjust a symbol defined by a dynamic object and referenced by a
16136 regular object. The current definition is in some section of the
16137 dynamic object, but we're not including those sections. We have to
16138 change the definition to something the rest of the link can
16139 understand. */
16140
b34976b6 16141static bfd_boolean
57e8b36a
NC		 16142elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
16143 struct elf_link_hash_entry * h)
252b5132
RH		 16144{
16145 bfd * dynobj;
5474d94f 16146 asection *s, *srel;
b7693d02 16147 struct elf32_arm_link_hash_entry * eh;
67687978 16148 struct elf32_arm_link_hash_table *globals;
252b5132 16149
67687978 16150 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16151 if (globals == NULL)
16152 return FALSE;
16153
252b5132
RH		 16154 dynobj = elf_hash_table (info)->dynobj;
16155
16156 /* Make sure we know what is going on here. */
16157 BFD_ASSERT (dynobj != NULL
f5385ebf 16158 && (h->needs_plt
34e77a92 16159 || h->type == STT_GNU_IFUNC
60d67dc8 16160 || h->is_weakalias
f5385ebf
AM		 16161 || (h->def_dynamic
16162 && h->ref_regular
16163 && !h->def_regular)));
252b5132 16164
b7693d02
DJ		 16165 eh = (struct elf32_arm_link_hash_entry *) h;
16166
252b5132
RH		 16167 /* If this is a function, put it in the procedure linkage table. We
16168 will fill in the contents of the procedure linkage table later,
16169 when we know the address of the .got section. */
34e77a92 16170 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 16171 {
34e77a92
RS		 16172 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
16173 symbol binds locally. */
5e681ec4 16174 if (h->plt.refcount <= 0
34e77a92
RS		 16175 || (h->type != STT_GNU_IFUNC
16176 && (SYMBOL_CALLS_LOCAL (info, h)
16177 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16178 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 16179 {
16180 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 16181 file, but the symbol was never referred to by a dynamic
16182 object, or if all references were garbage collected. In
16183 such a case, we don't actually need to build a procedure
16184 linkage table, and we can just do a PC24 reloc instead. */
16185 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16186 eh->plt.thumb_refcount = 0;
16187 eh->plt.maybe_thumb_refcount = 0;
16188 eh->plt.noncall_refcount = 0;
f5385ebf 16189 h->needs_plt = 0;
252b5132
RH		 16190 }
16191
b34976b6 16192 return TRUE;
252b5132 16193 }
5e681ec4 16194 else
b7693d02
DJ		 16195 {
16196 /* It's possible that we incorrectly decided a .plt reloc was
16197 needed for an R_ARM_PC24 or similar reloc to a non-function sym
16198 in check_relocs. We can't decide accurately between function
16199 and non-function syms in check-relocs; Objects loaded later in
16200 the link may change h->type. So fix it now. */
16201 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16202 eh->plt.thumb_refcount = 0;
16203 eh->plt.maybe_thumb_refcount = 0;
16204 eh->plt.noncall_refcount = 0;
b7693d02 16205 }
252b5132
RH		 16206
16207 /* If this is a weak symbol, and there is a real definition, the
16208 processor independent code will have arranged for us to see the
16209 real definition first, and we can just use the same value. */
60d67dc8 16210 if (h->is_weakalias)
252b5132 16211 {
60d67dc8
AM		 16212 struct elf_link_hash_entry *def = weakdef (h);
16213 BFD_ASSERT (def->root.type == bfd_link_hash_defined);
16214 h->root.u.def.section = def->root.u.def.section;
16215 h->root.u.def.value = def->root.u.def.value;
b34976b6 16216 return TRUE;
252b5132
RH		 16217 }
16218
ba93b8ac
DJ		 16219 /* If there are no non-GOT references, we do not need a copy
16220 relocation. */
16221 if (!h->non_got_ref)
16222 return TRUE;
16223
252b5132
RH		 16224 /* This is a reference to a symbol defined by a dynamic object which
16225 is not a function. */
16226
16227 /* If we are creating a shared library, we must presume that the
16228 only references to the symbol are via the global offset table.
16229 For such cases we need not do anything here; the relocations will
67687978
PB		 16230 be handled correctly by relocate_section. Relocatable executables
16231 can reference data in shared objects directly, so we don't need to
16232 do anything here. */
0e1862bb 16233 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 16234 return TRUE;
252b5132
RH		 16235
16236 /* We must allocate the symbol in our .dynbss section, which will
16237 become part of the .bss section of the executable. There will be
16238 an entry for this symbol in the .dynsym section. The dynamic
16239 object will contain position independent code, so all references
16240 from the dynamic object to this symbol will go through the global
16241 offset table. The dynamic linker will use the .dynsym entry to
16242 determine the address it must put in the global offset table, so
16243 both the dynamic object and the regular object will refer to the
16244 same memory location for the variable. */
5522f910
NC		 16245 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16246 linker to copy the initial value out of the dynamic object and into
16247 the runtime process image. We need to remember the offset into the
00a97672 16248 .rel(a).bss section we are going to use. */
5474d94f
AM		 16249 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
16250 {
16251 s = globals->root.sdynrelro;
16252 srel = globals->root.sreldynrelro;
16253 }
16254 else
16255 {
16256 s = globals->root.sdynbss;
16257 srel = globals->root.srelbss;
16258 }
5522f910
NC		 16259 if (info->nocopyreloc == 0
16260 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 16261 && h->size != 0)
252b5132 16262 {
47beaa6a 16263 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 16264 h->needs_copy = 1;
252b5132
RH		 16265 }
16266
6cabe1ea 16267 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 16268}
16269
5e681ec4
PB		 16270/* Allocate space in .plt, .got and associated reloc sections for
16271 dynamic relocs. */
16272
16273static bfd_boolean
47beaa6a 16274allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 16275{
16276 struct bfd_link_info *info;
16277 struct elf32_arm_link_hash_table *htab;
16278 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 16279 struct elf_dyn_relocs *p;
5e681ec4
PB		 16280
16281 if (h->root.type == bfd_link_hash_indirect)
16282 return TRUE;
16283
e6a6bb22
AM		 16284 eh = (struct elf32_arm_link_hash_entry *) h;
16285
5e681ec4
PB		 16286 info = (struct bfd_link_info *) inf;
16287 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16288 if (htab == NULL)
16289 return FALSE;
5e681ec4 16290
34e77a92 16291 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 16292 && h->plt.refcount > 0)
16293 {
16294 /* Make sure this symbol is output as a dynamic symbol.
16295 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16296 if (h->dynindx == -1 && !h->forced_local
16297 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16298 {
c152c796 16299 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16300 return FALSE;
16301 }
16302
34e77a92
RS		 16303 /* If the call in the PLT entry binds locally, the associated
16304 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16305 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16306 than the .plt section. */
16307 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
16308 {
16309 eh->is_iplt = 1;
16310 if (eh->plt.noncall_refcount == 0
16311 && SYMBOL_REFERENCES_LOCAL (info, h))
16312 /* All non-call references can be resolved directly.
16313 This means that they can (and in some cases, must)
16314 resolve directly to the run-time target, rather than
16315 to the PLT. That in turns means that any .got entry
16316 would be equal to the .igot.plt entry, so there's
16317 no point having both. */
16318 h->got.refcount = 0;
16319 }
16320
0e1862bb 16321 if (bfd_link_pic (info)
34e77a92 16322 || eh->is_iplt
7359ea65 16323 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 16324 {
34e77a92 16325 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 16326
5e681ec4
PB		 16327 /* If this symbol is not defined in a regular file, and we are
16328 not generating a shared library, then set the symbol to this
16329 location in the .plt. This is required to make function
16330 pointers compare as equal between the normal executable and
16331 the shared library. */
0e1862bb 16332 if (! bfd_link_pic (info)
f5385ebf 16333 && !h->def_regular)
5e681ec4 16334 {
34e77a92 16335 h->root.u.def.section = htab->root.splt;
5e681ec4 16336 h->root.u.def.value = h->plt.offset;
5e681ec4 16337
67d74e43
DJ		 16338 /* Make sure the function is not marked as Thumb, in case
16339 it is the target of an ABS32 relocation, which will
16340 point to the PLT entry. */
39d911fc 16341 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 16342 }
022f8312 16343
00a97672
RS		 16344 /* VxWorks executables have a second set of relocations for
16345 each PLT entry. They go in a separate relocation section,
16346 which is processed by the kernel loader. */
0e1862bb 16347 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 16348 {
16349 /* There is a relocation for the initial PLT entry:
16350 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16351 if (h->plt.offset == htab->plt_header_size)
47beaa6a 16352 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 16353
16354 /* There are two extra relocations for each subsequent
16355 PLT entry: an R_ARM_32 relocation for the GOT entry,
16356 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 16357 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 16358 }
5e681ec4
PB		 16359 }
16360 else
16361 {
16362 h->plt.offset = (bfd_vma) -1;
f5385ebf 16363 h->needs_plt = 0;
5e681ec4
PB		 16364 }
16365 }
16366 else
16367 {
16368 h->plt.offset = (bfd_vma) -1;
f5385ebf 16369 h->needs_plt = 0;
5e681ec4
PB		 16370 }
16371
0855e32b
NS		 16372 eh = (struct elf32_arm_link_hash_entry *) h;
16373 eh->tlsdesc_got = (bfd_vma) -1;
16374
5e681ec4
PB		 16375 if (h->got.refcount > 0)
16376 {
16377 asection *s;
16378 bfd_boolean dyn;
ba93b8ac
DJ		 16379 int tls_type = elf32_arm_hash_entry (h)->tls_type;
16380 int indx;
5e681ec4
PB		 16381
16382 /* Make sure this symbol is output as a dynamic symbol.
16383 Undefined weak syms won't yet be marked as dynamic. */
e8b09b87 16384 if (htab->root.dynamic_sections_created && h->dynindx == -1 && !h->forced_local
6c699715 16385 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16386 {
c152c796 16387 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16388 return FALSE;
16389 }
16390
e5a52504
MM		 16391 if (!htab->symbian_p)
16392 {
362d30a1 16393 s = htab->root.sgot;
e5a52504 16394 h->got.offset = s->size;
ba93b8ac
DJ		 16395
16396 if (tls_type == GOT_UNKNOWN)
16397 abort ();
16398
16399 if (tls_type == GOT_NORMAL)
16400 /* Non-TLS symbols need one GOT slot. */
16401 s->size += 4;
16402 else
16403 {
99059e56
RM		 16404 if (tls_type & GOT_TLS_GDESC)
16405 {
0855e32b 16406 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 16407 eh->tlsdesc_got
0855e32b
NS		 16408 = (htab->root.sgotplt->size
16409 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 16410 htab->root.sgotplt->size += 8;
16411 h->got.offset = (bfd_vma) -2;
34e77a92 16412 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16413 reloc in the middle of .got.plt. */
99059e56
RM		 16414 htab->num_tls_desc++;
16415 }
0855e32b 16416
ba93b8ac 16417 if (tls_type & GOT_TLS_GD)
0855e32b 16418 {
5c5a4843
CL		 16419 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16420 consecutive GOT slots. If the symbol is both GD
16421 and GDESC, got.offset may have been
16422 overwritten. */
0855e32b
NS		 16423 h->got.offset = s->size;
16424 s->size += 8;
16425 }
16426
ba93b8ac 16427 if (tls_type & GOT_TLS_IE)
5c5a4843
CL		 16428 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16429 slot. */
ba93b8ac
DJ		 16430 s->size += 4;
16431 }
16432
e5a52504 16433 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 16434
16435 indx = 0;
0e1862bb
L		 16436 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
16437 bfd_link_pic (info),
16438 h)
16439 && (!bfd_link_pic (info)
ba93b8ac
DJ		 16440 || !SYMBOL_REFERENCES_LOCAL (info, h)))
16441 indx = h->dynindx;
16442
16443 if (tls_type != GOT_NORMAL
0e1862bb 16444 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 16445 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16446 || h->root.type != bfd_link_hash_undefweak))
16447 {
16448 if (tls_type & GOT_TLS_IE)
47beaa6a 16449 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16450
16451 if (tls_type & GOT_TLS_GD)
47beaa6a 16452 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16453
b38cadfb 16454 if (tls_type & GOT_TLS_GDESC)
0855e32b 16455 {
47beaa6a 16456 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 16457 /* GDESC needs a trampoline to jump to. */
16458 htab->tls_trampoline = -1;
16459 }
16460
16461 /* Only GD needs it. GDESC just emits one relocation per
16462 2 entries. */
b38cadfb 16463 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 16464 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16465 }
e8b09b87
CL		 16466 else if (((indx != -1) || htab->fdpic_p)
16467 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 16468 {
16469 if (htab->root.dynamic_sections_created)
16470 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16471 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16472 }
34e77a92
RS		 16473 else if (h->type == STT_GNU_IFUNC
16474 && eh->plt.noncall_refcount == 0)
16475 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16476 they all resolve dynamically instead. Reserve room for the
16477 GOT entry's R_ARM_IRELATIVE relocation. */
16478 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 16479 else if (bfd_link_pic (info)
16480 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16481 || h->root.type != bfd_link_hash_undefweak))
b436d854 16482 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 16483 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16484 else if (htab->fdpic_p && tls_type == GOT_NORMAL)
16485 /* Reserve room for rofixup for FDPIC executable. */
16486 /* TLS relocs do not need space since they are completely
16487 resolved. */
16488 htab->srofixup->size += 4;
e5a52504 16489 }
5e681ec4
PB		 16490 }
16491 else
16492 h->got.offset = (bfd_vma) -1;
16493
e8b09b87
CL		 16494 /* FDPIC support. */
16495 if (eh->fdpic_cnts.gotofffuncdesc_cnt > 0)
16496 {
16497 /* Symbol musn't be exported. */
16498 if (h->dynindx != -1)
16499 abort();
16500
16501 /* We only allocate one function descriptor with its associated relocation. */
16502 if (eh->fdpic_cnts.funcdesc_offset == -1)
16503 {
16504 asection *s = htab->root.sgot;
16505
16506 eh->fdpic_cnts.funcdesc_offset = s->size;
16507 s->size += 8;
16508 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16509 if (bfd_link_pic(info))
16510 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16511 else
16512 htab->srofixup->size += 8;
16513 }
16514 }
16515
16516 if (eh->fdpic_cnts.gotfuncdesc_cnt > 0)
16517 {
16518 asection *s = htab->root.sgot;
16519
16520 if (htab->root.dynamic_sections_created && h->dynindx == -1
16521 && !h->forced_local)
16522 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16523 return FALSE;
16524
16525 if (h->dynindx == -1)
16526 {
16527 /* We only allocate one function descriptor with its associated relocation. q */
16528 if (eh->fdpic_cnts.funcdesc_offset == -1)
16529 {
16530
16531 eh->fdpic_cnts.funcdesc_offset = s->size;
16532 s->size += 8;
16533 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16534 if (bfd_link_pic(info))
16535 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16536 else
16537 htab->srofixup->size += 8;
16538 }
16539 }
16540
16541 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16542 R_ARM_RELATIVE/rofixup relocation on it. */
16543 eh->fdpic_cnts.gotfuncdesc_offset = s->size;
16544 s->size += 4;
16545 if (h->dynindx == -1 && !bfd_link_pic(info))
4b24dd1a 16546 htab->srofixup->size += 4;
e8b09b87 16547 else
4b24dd1a 16548 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16549 }
16550
16551 if (eh->fdpic_cnts.funcdesc_cnt > 0)
16552 {
16553 if (htab->root.dynamic_sections_created && h->dynindx == -1
16554 && !h->forced_local)
16555 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16556 return FALSE;
16557
16558 if (h->dynindx == -1)
16559 {
16560 /* We only allocate one function descriptor with its associated relocation. */
16561 if (eh->fdpic_cnts.funcdesc_offset == -1)
16562 {
16563 asection *s = htab->root.sgot;
16564
16565 eh->fdpic_cnts.funcdesc_offset = s->size;
16566 s->size += 8;
16567 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16568 if (bfd_link_pic(info))
16569 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16570 else
16571 htab->srofixup->size += 8;
16572 }
16573 }
16574 if (h->dynindx == -1 && !bfd_link_pic(info))
16575 {
16576 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16577 htab->srofixup->size += 4 * eh->fdpic_cnts.funcdesc_cnt;
16578 }
16579 else
16580 {
16581 /* Will need one dynamic reloc per reference. will be either
16582 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16583 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot,
16584 eh->fdpic_cnts.funcdesc_cnt);
16585 }
16586 }
16587
a4fd1a8e
PB		 16588 /* Allocate stubs for exported Thumb functions on v4t. */
16589 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 16590 && h->def_regular
39d911fc 16591 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 16592 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
16593 {
16594 struct elf_link_hash_entry * th;
16595 struct bfd_link_hash_entry * bh;
16596 struct elf_link_hash_entry * myh;
16597 char name[1024];
16598 asection *s;
16599 bh = NULL;
16600 /* Create a new symbol to regist the real location of the function. */
16601 s = h->root.u.def.section;
906e58ca 16602 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 16603 _bfd_generic_link_add_one_symbol (info, s->owner,
16604 name, BSF_GLOBAL, s,
16605 h->root.u.def.value,
16606 NULL, TRUE, FALSE, &bh);
16607
16608 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 16609 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 16610 myh->forced_local = 1;
39d911fc 16611 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 16612 eh->export_glue = myh;
16613 th = record_arm_to_thumb_glue (info, h);
16614 /* Point the symbol at the stub. */
16615 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 16616 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 16617 h->root.u.def.section = th->root.u.def.section;
16618 h->root.u.def.value = th->root.u.def.value & ~1;
16619 }
16620
0bdcacaf 16621 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 16622 return TRUE;
16623
16624 /* In the shared -Bsymbolic case, discard space allocated for
16625 dynamic pc-relative relocs against symbols which turn out to be
16626 defined in regular objects. For the normal shared case, discard
16627 space for pc-relative relocs that have become local due to symbol
16628 visibility changes. */
16629
e8b09b87 16630 if (bfd_link_pic (info) || htab->root.is_relocatable_executable || htab->fdpic_p)
5e681ec4 16631 {
469a3493
RM		 16632 /* Relocs that use pc_count are PC-relative forms, which will appear
16633 on something like ".long foo - ." or "movw REG, foo - .". We want
16634 calls to protected symbols to resolve directly to the function
16635 rather than going via the plt. If people want function pointer
16636 comparisons to work as expected then they should avoid writing
16637 assembly like ".long foo - .". */
ba93b8ac
DJ		 16638 if (SYMBOL_CALLS_LOCAL (info, h))
16639 {
0bdcacaf 16640 struct elf_dyn_relocs **pp;
ba93b8ac 16641
0bdcacaf 16642 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 16643 {
16644 p->count -= p->pc_count;
16645 p->pc_count = 0;
16646 if (p->count == 0)
16647 *pp = p->next;
16648 else
16649 pp = &p->next;
16650 }
16651 }
16652
4dfe6ac6 16653 if (htab->vxworks_p)
3348747a 16654 {
0bdcacaf 16655 struct elf_dyn_relocs **pp;
3348747a 16656
0bdcacaf 16657 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 16658 {
0bdcacaf 16659 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 16660 *pp = p->next;
16661 else
16662 pp = &p->next;
16663 }
16664 }
16665
ba93b8ac 16666 /* Also discard relocs on undefined weak syms with non-default
99059e56 16667 visibility. */
0bdcacaf 16668 if (eh->dyn_relocs != NULL
5e681ec4 16669 && h->root.type == bfd_link_hash_undefweak)
22d606e9 16670 {
95b03e4a
L		 16671 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16672 || UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
0bdcacaf 16673 eh->dyn_relocs = NULL;
22d606e9
AM		 16674
16675 /* Make sure undefined weak symbols are output as a dynamic
16676 symbol in PIEs. */
e8b09b87 16677 else if (htab->root.dynamic_sections_created && h->dynindx == -1
22d606e9
AM		 16678 && !h->forced_local)
16679 {
16680 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16681 return FALSE;
16682 }
16683 }
16684
67687978
PB		 16685 else if (htab->root.is_relocatable_executable && h->dynindx == -1
16686 && h->root.type == bfd_link_hash_new)
16687 {
16688 /* Output absolute symbols so that we can create relocations
16689 against them. For normal symbols we output a relocation
16690 against the section that contains them. */
16691 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16692 return FALSE;
16693 }
16694
5e681ec4
PB		 16695 }
16696 else
16697 {
16698 /* For the non-shared case, discard space for relocs against
16699 symbols which turn out to need copy relocs or are not
16700 dynamic. */
16701
f5385ebf
AM		 16702 if (!h->non_got_ref
16703 && ((h->def_dynamic
16704 && !h->def_regular)
5e681ec4
PB		 16705 || (htab->root.dynamic_sections_created
16706 && (h->root.type == bfd_link_hash_undefweak
16707 || h->root.type == bfd_link_hash_undefined))))
16708 {
16709 /* Make sure this symbol is output as a dynamic symbol.
16710 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16711 if (h->dynindx == -1 && !h->forced_local
16712 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16713 {
c152c796 16714 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16715 return FALSE;
16716 }
16717
16718 /* If that succeeded, we know we'll be keeping all the
16719 relocs. */
16720 if (h->dynindx != -1)
16721 goto keep;
16722 }
16723
0bdcacaf 16724 eh->dyn_relocs = NULL;
5e681ec4
PB		 16725
16726 keep: ;
16727 }
16728
16729 /* Finally, allocate space. */
0bdcacaf 16730 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 16731 {
0bdcacaf 16732 asection *sreloc = elf_section_data (p->sec)->sreloc;
e8b09b87 16733
34e77a92
RS		 16734 if (h->type == STT_GNU_IFUNC
16735 && eh->plt.noncall_refcount == 0
16736 && SYMBOL_REFERENCES_LOCAL (info, h))
16737 elf32_arm_allocate_irelocs (info, sreloc, p->count);
e8b09b87
CL		 16738 else if (h->dynindx != -1 && (!bfd_link_pic(info) || !info->symbolic || !h->def_regular))
16739 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
16740 else if (htab->fdpic_p && !bfd_link_pic(info))
16741 htab->srofixup->size += 4 * p->count;
34e77a92
RS		 16742 else
16743 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 16744 }
16745
16746 return TRUE;
16747}
16748
63c1f59d
AM		 16749/* Set DF_TEXTREL if we find any dynamic relocs that apply to
16750 read-only sections. */
08d1f311
DJ		 16751
16752static bfd_boolean
63c1f59d 16753maybe_set_textrel (struct elf_link_hash_entry *h, void *info_p)
08d1f311 16754{
63c1f59d 16755 asection *sec;
08d1f311 16756
63c1f59d
AM		 16757 if (h->root.type == bfd_link_hash_indirect)
16758 return TRUE;
08d1f311 16759
63c1f59d
AM		 16760 sec = readonly_dynrelocs (h);
16761 if (sec != NULL)
16762 {
16763 struct bfd_link_info *info = (struct bfd_link_info *) info_p;
08d1f311 16764
63c1f59d
AM		 16765 info->flags |= DF_TEXTREL;
16766 info->callbacks->minfo
c1c8c1ef 16767 (_("%pB: dynamic relocation against `%pT' in read-only section `%pA'\n"),
63c1f59d 16768 sec->owner, h->root.root.string, sec);
08d1f311 16769
63c1f59d
AM		 16770 /* Not an error, just cut short the traversal. */
16771 return FALSE;
08d1f311 16772 }
cb10292c 16773
08d1f311
DJ		 16774 return TRUE;
16775}
16776
d504ffc8
DJ		 16777void
16778bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
16779 int byteswap_code)
16780{
16781 struct elf32_arm_link_hash_table *globals;
16782
16783 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16784 if (globals == NULL)
16785 return;
16786
d504ffc8
DJ		 16787 globals->byteswap_code = byteswap_code;
16788}
16789
252b5132
RH		 16790/* Set the sizes of the dynamic sections. */
16791
b34976b6 16792static bfd_boolean
57e8b36a
NC		 16793elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
16794 struct bfd_link_info * info)
252b5132
RH		 16795{
16796 bfd * dynobj;
16797 asection * s;
b34976b6
AM		 16798 bfd_boolean plt;
16799 bfd_boolean relocs;
5e681ec4
PB		 16800 bfd *ibfd;
16801 struct elf32_arm_link_hash_table *htab;
252b5132 16802
5e681ec4 16803 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16804 if (htab == NULL)
16805 return FALSE;
16806
252b5132
RH		 16807 dynobj = elf_hash_table (info)->dynobj;
16808 BFD_ASSERT (dynobj != NULL);
39b41c9c 16809 check_use_blx (htab);
252b5132
RH		 16810
16811 if (elf_hash_table (info)->dynamic_sections_created)
16812 {
16813 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 16814 if (bfd_link_executable (info) && !info->nointerp)
252b5132 16815 {
3d4d4302 16816 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 16817 BFD_ASSERT (s != NULL);
eea6121a 16818 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 16819 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
16820 }
16821 }
5e681ec4
PB		 16822
16823 /* Set up .got offsets for local syms, and space for local dynamic
16824 relocs. */
c72f2fb2 16825 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 16826 {
5e681ec4
PB		 16827 bfd_signed_vma *local_got;
16828 bfd_signed_vma *end_local_got;
34e77a92 16829 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 16830 char *local_tls_type;
0855e32b 16831 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 16832 bfd_size_type locsymcount;
16833 Elf_Internal_Shdr *symtab_hdr;
16834 asection *srel;
4dfe6ac6 16835 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 16836 unsigned int symndx;
e8b09b87 16837 struct fdpic_local *local_fdpic_cnts;
5e681ec4 16838
0ffa91dd 16839 if (! is_arm_elf (ibfd))
5e681ec4
PB		 16840 continue;
16841
16842 for (s = ibfd->sections; s != NULL; s = s->next)
16843 {
0bdcacaf 16844 struct elf_dyn_relocs *p;
5e681ec4 16845
0bdcacaf 16846 for (p = (struct elf_dyn_relocs *)
99059e56 16847 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 16848 {
0bdcacaf
RS		 16849 if (!bfd_is_abs_section (p->sec)
16850 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 16851 {
16852 /* Input section has been discarded, either because
16853 it is a copy of a linkonce section or due to
16854 linker script /DISCARD/, so we'll be discarding
16855 the relocs too. */
16856 }
3348747a 16857 else if (is_vxworks
0bdcacaf 16858 && strcmp (p->sec->output_section->name,
3348747a
NS		 16859 ".tls_vars") == 0)
16860 {
16861 /* Relocations in vxworks .tls_vars sections are
16862 handled specially by the loader. */
16863 }
5e681ec4
PB		 16864 else if (p->count != 0)
16865 {
0bdcacaf 16866 srel = elf_section_data (p->sec)->sreloc;
e8b09b87
CL		 16867 if (htab->fdpic_p && !bfd_link_pic(info))
16868 htab->srofixup->size += 4 * p->count;
16869 else
16870 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 16871 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 16872 info->flags |= DF_TEXTREL;
16873 }
16874 }
16875 }
16876
16877 local_got = elf_local_got_refcounts (ibfd);
16878 if (!local_got)
16879 continue;
16880
0ffa91dd 16881 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 16882 locsymcount = symtab_hdr->sh_info;
16883 end_local_got = local_got + locsymcount;
34e77a92 16884 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 16885 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 16886 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
e8b09b87 16887 local_fdpic_cnts = elf32_arm_local_fdpic_cnts (ibfd);
34e77a92 16888 symndx = 0;
362d30a1
RS		 16889 s = htab->root.sgot;
16890 srel = htab->root.srelgot;
0855e32b 16891 for (; local_got < end_local_got;
34e77a92 16892 ++local_got, ++local_iplt_ptr, ++local_tls_type,
e8b09b87 16893 ++local_tlsdesc_gotent, ++symndx, ++local_fdpic_cnts)
5e681ec4 16894 {
0855e32b 16895 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92 16896 local_iplt = *local_iplt_ptr;
e8b09b87
CL		 16897
16898 /* FDPIC support. */
16899 if (local_fdpic_cnts->gotofffuncdesc_cnt > 0)
16900 {
16901 if (local_fdpic_cnts->funcdesc_offset == -1)
16902 {
16903 local_fdpic_cnts->funcdesc_offset = s->size;
16904 s->size += 8;
16905
16906 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16907 if (bfd_link_pic(info))
16908 elf32_arm_allocate_dynrelocs (info, srel, 1);
16909 else
16910 htab->srofixup->size += 8;
16911 }
16912 }
16913
16914 if (local_fdpic_cnts->funcdesc_cnt > 0)
16915 {
16916 if (local_fdpic_cnts->funcdesc_offset == -1)
16917 {
16918 local_fdpic_cnts->funcdesc_offset = s->size;
16919 s->size += 8;
16920
16921 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16922 if (bfd_link_pic(info))
16923 elf32_arm_allocate_dynrelocs (info, srel, 1);
16924 else
16925 htab->srofixup->size += 8;
16926 }
16927
16928 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16929 if (bfd_link_pic(info))
16930 elf32_arm_allocate_dynrelocs (info, srel, local_fdpic_cnts->funcdesc_cnt);
16931 else
16932 htab->srofixup->size += 4 * local_fdpic_cnts->funcdesc_cnt;
16933 }
16934
34e77a92
RS		 16935 if (local_iplt != NULL)
16936 {
16937 struct elf_dyn_relocs *p;
16938
16939 if (local_iplt->root.refcount > 0)
16940 {
16941 elf32_arm_allocate_plt_entry (info, TRUE,
16942 &local_iplt->root,
16943 &local_iplt->arm);
16944 if (local_iplt->arm.noncall_refcount == 0)
16945 /* All references to the PLT are calls, so all
16946 non-call references can resolve directly to the
16947 run-time target. This means that the .got entry
16948 would be the same as the .igot.plt entry, so there's
16949 no point creating both. */
16950 *local_got = 0;
16951 }
16952 else
16953 {
16954 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
16955 local_iplt->root.offset = (bfd_vma) -1;
16956 }
16957
16958 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
16959 {
16960 asection *psrel;
16961
16962 psrel = elf_section_data (p->sec)->sreloc;
16963 if (local_iplt->arm.noncall_refcount == 0)
16964 elf32_arm_allocate_irelocs (info, psrel, p->count);
16965 else
16966 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
16967 }
16968 }
5e681ec4
PB		 16969 if (*local_got > 0)
16970 {
34e77a92
RS		 16971 Elf_Internal_Sym *isym;
16972
eea6121a 16973 *local_got = s->size;
ba93b8ac
DJ		 16974 if (*local_tls_type & GOT_TLS_GD)
16975 /* TLS_GD relocs need an 8-byte structure in the GOT. */
16976 s->size += 8;
0855e32b
NS		 16977 if (*local_tls_type & GOT_TLS_GDESC)
16978 {
16979 *local_tlsdesc_gotent = htab->root.sgotplt->size
16980 - elf32_arm_compute_jump_table_size (htab);
16981 htab->root.sgotplt->size += 8;
16982 *local_got = (bfd_vma) -2;
34e77a92 16983 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16984 reloc in the middle of .got.plt. */
99059e56 16985 htab->num_tls_desc++;
0855e32b 16986 }
ba93b8ac
DJ		 16987 if (*local_tls_type & GOT_TLS_IE)
16988 s->size += 4;
ba93b8ac 16989
0855e32b
NS		 16990 if (*local_tls_type & GOT_NORMAL)
16991 {
16992 /* If the symbol is both GD and GDESC, *local_got
16993 may have been overwritten. */
16994 *local_got = s->size;
16995 s->size += 4;
16996 }
16997
34e77a92
RS		 16998 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
16999 if (isym == NULL)
17000 return FALSE;
17001
17002 /* If all references to an STT_GNU_IFUNC PLT are calls,
17003 then all non-call references, including this GOT entry,
17004 resolve directly to the run-time target. */
17005 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
17006 && (local_iplt == NULL
17007 || local_iplt->arm.noncall_refcount == 0))
17008 elf32_arm_allocate_irelocs (info, srel, 1);
e8b09b87 17009 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC || htab->fdpic_p)
0855e32b 17010 {
e8b09b87 17011 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC)))
3064e1ff 17012 elf32_arm_allocate_dynrelocs (info, srel, 1);
e8b09b87
CL		 17013 else if (htab->fdpic_p && *local_tls_type & GOT_NORMAL)
17014 htab->srofixup->size += 4;
99059e56 17015
e8b09b87
CL		 17016 if ((bfd_link_pic (info) || htab->fdpic_p)
17017 && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 17018 {
17019 elf32_arm_allocate_dynrelocs (info,
17020 htab->root.srelplt, 1);
17021 htab->tls_trampoline = -1;
17022 }
0855e32b 17023 }
5e681ec4
PB		 17024 }
17025 else
17026 *local_got = (bfd_vma) -1;
17027 }
252b5132
RH		 17028 }
17029
ba93b8ac
DJ		 17030 if (htab->tls_ldm_got.refcount > 0)
17031 {
17032 /* Allocate two GOT entries and one dynamic relocation (if necessary)
5c5a4843 17033 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
362d30a1
RS		 17034 htab->tls_ldm_got.offset = htab->root.sgot->size;
17035 htab->root.sgot->size += 8;
0e1862bb 17036 if (bfd_link_pic (info))
47beaa6a 17037 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 17038 }
17039 else
17040 htab->tls_ldm_got.offset = -1;
17041
e8b09b87
CL		 17042 /* At the very end of the .rofixup section is a pointer to the GOT,
17043 reserve space for it. */
17044 if (htab->fdpic_p && htab->srofixup != NULL)
17045 htab->srofixup->size += 4;
17046
5e681ec4
PB		 17047 /* Allocate global sym .plt and .got entries, and space for global
17048 sym dynamic relocs. */
47beaa6a 17049 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 17050
d504ffc8 17051 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 17052 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 17053 {
0ffa91dd 17054 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 17055 continue;
17056
c7b8f16e
JB		 17057 /* Initialise mapping tables for code/data. */
17058 bfd_elf32_arm_init_maps (ibfd);
906e58ca 17059
c7b8f16e 17060 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 17061 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
17062 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
90b6238f 17063 _bfd_error_handler (_("errors encountered processing file %pB"), ibfd);
c7b8f16e 17064 }
d504ffc8 17065
3e6b1042
DJ		 17066 /* Allocate space for the glue sections now that we've sized them. */
17067 bfd_elf32_arm_allocate_interworking_sections (info);
17068
0855e32b
NS		 17069 /* For every jump slot reserved in the sgotplt, reloc_count is
17070 incremented. However, when we reserve space for TLS descriptors,
17071 it's not incremented, so in order to compute the space reserved
17072 for them, it suffices to multiply the reloc count by the jump
17073 slot size. */
17074 if (htab->root.srelplt)
17075 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
17076
17077 if (htab->tls_trampoline)
17078 {
17079 if (htab->root.splt->size == 0)
17080 htab->root.splt->size += htab->plt_header_size;
b38cadfb 17081
0855e32b
NS		 17082 htab->tls_trampoline = htab->root.splt->size;
17083 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 17084
0855e32b 17085 /* If we're not using lazy TLS relocations, don't generate the
99059e56 17086 PLT and GOT entries they require. */
0855e32b
NS		 17087 if (!(info->flags & DF_BIND_NOW))
17088 {
17089 htab->dt_tlsdesc_got = htab->root.sgot->size;
17090 htab->root.sgot->size += 4;
17091
17092 htab->dt_tlsdesc_plt = htab->root.splt->size;
17093 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
17094 }
17095 }
17096
252b5132
RH		 17097 /* The check_relocs and adjust_dynamic_symbol entry points have
17098 determined the sizes of the various dynamic sections. Allocate
17099 memory for them. */
b34976b6
AM		 17100 plt = FALSE;
17101 relocs = FALSE;
252b5132
RH		 17102 for (s = dynobj->sections; s != NULL; s = s->next)
17103 {
17104 const char * name;
252b5132
RH		 17105
17106 if ((s->flags & SEC_LINKER_CREATED) == 0)
17107 continue;
17108
17109 /* It's OK to base decisions on the section name, because none
17110 of the dynobj section names depend upon the input files. */
17111 name = bfd_get_section_name (dynobj, s);
17112
34e77a92 17113 if (s == htab->root.splt)
252b5132 17114 {
c456f082
AM		 17115 /* Remember whether there is a PLT. */
17116 plt = s->size != 0;
252b5132 17117 }
0112cd26 17118 else if (CONST_STRNEQ (name, ".rel"))
252b5132 17119 {
c456f082 17120 if (s->size != 0)
252b5132 17121 {
252b5132 17122 /* Remember whether there are any reloc sections other
00a97672 17123 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 17124 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 17125 relocs = TRUE;
252b5132
RH		 17126
17127 /* We use the reloc_count field as a counter if we need
17128 to copy relocs into the output file. */
17129 s->reloc_count = 0;
17130 }
17131 }
34e77a92
RS		 17132 else if (s != htab->root.sgot
17133 && s != htab->root.sgotplt
17134 && s != htab->root.iplt
17135 && s != htab->root.igotplt
5474d94f 17136 && s != htab->root.sdynbss
e8b09b87
CL		 17137 && s != htab->root.sdynrelro
17138 && s != htab->srofixup)
252b5132
RH		 17139 {
17140 /* It's not one of our sections, so don't allocate space. */
17141 continue;
17142 }
17143
c456f082 17144 if (s->size == 0)
252b5132 17145 {
c456f082 17146 /* If we don't need this section, strip it from the
00a97672
RS		 17147 output file. This is mostly to handle .rel(a).bss and
17148 .rel(a).plt. We must create both sections in
c456f082
AM		 17149 create_dynamic_sections, because they must be created
17150 before the linker maps input sections to output
17151 sections. The linker does that before
17152 adjust_dynamic_symbol is called, and it is that
17153 function which decides whether anything needs to go
17154 into these sections. */
8423293d 17155 s->flags |= SEC_EXCLUDE;
252b5132
RH		 17156 continue;
17157 }
17158
c456f082
AM		 17159 if ((s->flags & SEC_HAS_CONTENTS) == 0)
17160 continue;
17161
252b5132 17162 /* Allocate memory for the section contents. */
21d799b5 17163 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 17164 if (s->contents == NULL)
b34976b6 17165 return FALSE;
252b5132
RH		 17166 }
17167
17168 if (elf_hash_table (info)->dynamic_sections_created)
17169 {
17170 /* Add some entries to the .dynamic section. We fill in the
17171 values later, in elf32_arm_finish_dynamic_sections, but we
17172 must add the entries now so that we get the correct size for
17173 the .dynamic section. The DT_DEBUG entry is filled in by the
17174 dynamic linker and used by the debugger. */
dc810e39 17175#define add_dynamic_entry(TAG, VAL) \
5a580b3a 17176 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 17177
0e1862bb 17178 if (bfd_link_executable (info))
252b5132 17179 {
dc810e39 17180 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 17181 return FALSE;
252b5132
RH		 17182 }
17183
17184 if (plt)
17185 {
dc810e39
AM		 17186 if ( !add_dynamic_entry (DT_PLTGOT, 0)
17187 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 17188 || !add_dynamic_entry (DT_PLTREL,
17189 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 17190 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 17191 return FALSE;
0855e32b 17192
5025eb7c
AO		 17193 if (htab->dt_tlsdesc_plt
17194 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
17195 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 17196 return FALSE;
252b5132
RH		 17197 }
17198
17199 if (relocs)
17200 {
00a97672
RS		 17201 if (htab->use_rel)
17202 {
17203 if (!add_dynamic_entry (DT_REL, 0)
17204 || !add_dynamic_entry (DT_RELSZ, 0)
17205 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
17206 return FALSE;
17207 }
17208 else
17209 {
17210 if (!add_dynamic_entry (DT_RELA, 0)
17211 || !add_dynamic_entry (DT_RELASZ, 0)
17212 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
17213 return FALSE;
17214 }
252b5132
RH		 17215 }
17216
08d1f311
DJ		 17217 /* If any dynamic relocs apply to a read-only section,
17218 then we need a DT_TEXTREL entry. */
17219 if ((info->flags & DF_TEXTREL) == 0)
63c1f59d 17220 elf_link_hash_traverse (&htab->root, maybe_set_textrel, info);
08d1f311 17221
99e4ae17 17222 if ((info->flags & DF_TEXTREL) != 0)
252b5132 17223 {
dc810e39 17224 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 17225 return FALSE;
252b5132 17226 }
7a2b07ff
NS		 17227 if (htab->vxworks_p
17228 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
17229 return FALSE;
252b5132 17230 }
8532796c 17231#undef add_dynamic_entry
252b5132 17232
b34976b6 17233 return TRUE;
252b5132
RH		 17234}
17235
0855e32b
NS		 17236/* Size sections even though they're not dynamic. We use it to setup
17237 _TLS_MODULE_BASE_, if needed. */
17238
17239static bfd_boolean
17240elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 17241 struct bfd_link_info *info)
0855e32b
NS		 17242{
17243 asection *tls_sec;
cb10292c
CL		 17244 struct elf32_arm_link_hash_table *htab;
17245
17246 htab = elf32_arm_hash_table (info);
0855e32b 17247
0e1862bb 17248 if (bfd_link_relocatable (info))
0855e32b
NS		 17249 return TRUE;
17250
17251 tls_sec = elf_hash_table (info)->tls_sec;
17252
17253 if (tls_sec)
17254 {
17255 struct elf_link_hash_entry *tlsbase;
17256
17257 tlsbase = elf_link_hash_lookup
17258 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
17259
17260 if (tlsbase)
99059e56
RM		 17261 {
17262 struct bfd_link_hash_entry *bh = NULL;
0855e32b 17263 const struct elf_backend_data *bed
99059e56 17264 = get_elf_backend_data (output_bfd);
0855e32b 17265
99059e56 17266 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 17267 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
17268 tls_sec, 0, NULL, FALSE,
17269 bed->collect, &bh)))
17270 return FALSE;
b38cadfb 17271
99059e56
RM		 17272 tlsbase->type = STT_TLS;
17273 tlsbase = (struct elf_link_hash_entry *)bh;
17274 tlsbase->def_regular = 1;
17275 tlsbase->other = STV_HIDDEN;
17276 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 17277 }
17278 }
cb10292c
CL		 17279
17280 if (htab->fdpic_p && !bfd_link_relocatable (info)
17281 && !bfd_elf_stack_segment_size (output_bfd, info,
17282 "__stacksize", DEFAULT_STACK_SIZE))
17283 return FALSE;
17284
0855e32b
NS		 17285 return TRUE;
17286}
17287
252b5132
RH		 17288/* Finish up dynamic symbol handling. We set the contents of various
17289 dynamic sections here. */
17290
b34976b6 17291static bfd_boolean
906e58ca
NC		 17292elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
17293 struct bfd_link_info * info,
17294 struct elf_link_hash_entry * h,
17295 Elf_Internal_Sym * sym)
252b5132 17296{
e5a52504 17297 struct elf32_arm_link_hash_table *htab;
b7693d02 17298 struct elf32_arm_link_hash_entry *eh;
252b5132 17299
e5a52504 17300 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17301 if (htab == NULL)
17302 return FALSE;
17303
b7693d02 17304 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 17305
17306 if (h->plt.offset != (bfd_vma) -1)
17307 {
34e77a92 17308 if (!eh->is_iplt)
e5a52504 17309 {
34e77a92 17310 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 17311 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
17312 h->dynindx, 0))
17313 return FALSE;
e5a52504 17314 }
57e8b36a 17315
f5385ebf 17316 if (!h->def_regular)
252b5132
RH		 17317 {
17318 /* Mark the symbol as undefined, rather than as defined in
3a635617 17319 the .plt section. */
252b5132 17320 sym->st_shndx = SHN_UNDEF;
3a635617 17321 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 17322 Otherwise, the PLT entry would provide a definition for
17323 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 17324 and so the symbol would never be NULL. Leave the value if
17325 there were any relocations where pointer equality matters
17326 (this is a clue for the dynamic linker, to make function
17327 pointer comparisons work between an application and shared
17328 library). */
97323ad1 17329 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 17330 sym->st_value = 0;
252b5132 17331 }
34e77a92
RS		 17332 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
17333 {
17334 /* At least one non-call relocation references this .iplt entry,
17335 so the .iplt entry is the function's canonical address. */
17336 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 17337 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 17338 sym->st_shndx = (_bfd_elf_section_from_bfd_section
17339 (output_bfd, htab->root.iplt->output_section));
17340 sym->st_value = (h->plt.offset
17341 + htab->root.iplt->output_section->vma
17342 + htab->root.iplt->output_offset);
17343 }
252b5132
RH		 17344 }
17345
f5385ebf 17346 if (h->needs_copy)
252b5132
RH		 17347 {
17348 asection * s;
947216bf 17349 Elf_Internal_Rela rel;
252b5132
RH		 17350
17351 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 17352 BFD_ASSERT (h->dynindx != -1
17353 && (h->root.type == bfd_link_hash_defined
17354 || h->root.type == bfd_link_hash_defweak));
17355
00a97672 17356 rel.r_addend = 0;
252b5132
RH		 17357 rel.r_offset = (h->root.u.def.value
17358 + h->root.u.def.section->output_section->vma
17359 + h->root.u.def.section->output_offset);
17360 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 17361 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 17362 s = htab->root.sreldynrelro;
17363 else
17364 s = htab->root.srelbss;
47beaa6a 17365 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 17366 }
17367
00a97672 17368 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
fac7bd64
CL		 17369 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17370 it is relative to the ".got" section. */
9637f6ef 17371 if (h == htab->root.hdynamic
fac7bd64 17372 || (!htab->fdpic_p && !htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 17373 sym->st_shndx = SHN_ABS;
17374
b34976b6 17375 return TRUE;
252b5132
RH		 17376}
17377
0855e32b
NS		 17378static void
17379arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17380 void *contents,
17381 const unsigned long *template, unsigned count)
17382{
17383 unsigned ix;
b38cadfb 17384
0855e32b
NS		 17385 for (ix = 0; ix != count; ix++)
17386 {
17387 unsigned long insn = template[ix];
17388
17389 /* Emit mov pc,rx if bx is not permitted. */
17390 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
17391 insn = (insn & 0xf000000f) | 0x01a0f000;
17392 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
17393 }
17394}
17395
99059e56
RM		 17396/* Install the special first PLT entry for elf32-arm-nacl. Unlike
17397 other variants, NaCl needs this entry in a static executable's
17398 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17399 zero. For .iplt really only the last bundle is useful, and .iplt
17400 could have a shorter first entry, with each individual PLT entry's
17401 relative branch calculated differently so it targets the last
17402 bundle instead of the instruction before it (labelled .Lplt_tail
17403 above). But it's simpler to keep the size and layout of PLT0
17404 consistent with the dynamic case, at the cost of some dead code at
17405 the start of .iplt and the one dead store to the stack at the start
17406 of .Lplt_tail. */
17407static void
17408arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17409 asection *plt, bfd_vma got_displacement)
17410{
17411 unsigned int i;
17412
17413 put_arm_insn (htab, output_bfd,
17414 elf32_arm_nacl_plt0_entry[0]
17415 | arm_movw_immediate (got_displacement),
17416 plt->contents + 0);
17417 put_arm_insn (htab, output_bfd,
17418 elf32_arm_nacl_plt0_entry[1]
17419 | arm_movt_immediate (got_displacement),
17420 plt->contents + 4);
17421
17422 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
17423 put_arm_insn (htab, output_bfd,
17424 elf32_arm_nacl_plt0_entry[i],
17425 plt->contents + (i * 4));
17426}
17427
252b5132
RH		 17428/* Finish up the dynamic sections. */
17429
b34976b6 17430static bfd_boolean
57e8b36a 17431elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 17432{
17433 bfd * dynobj;
17434 asection * sgot;
17435 asection * sdyn;
4dfe6ac6
NC		 17436 struct elf32_arm_link_hash_table *htab;
17437
17438 htab = elf32_arm_hash_table (info);
17439 if (htab == NULL)
17440 return FALSE;
252b5132
RH		 17441
17442 dynobj = elf_hash_table (info)->dynobj;
17443
362d30a1 17444 sgot = htab->root.sgotplt;
894891db
NC		 17445 /* A broken linker script might have discarded the dynamic sections.
17446 Catch this here so that we do not seg-fault later on. */
17447 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
17448 return FALSE;
3d4d4302 17449 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 17450
17451 if (elf_hash_table (info)->dynamic_sections_created)
17452 {
17453 asection *splt;
17454 Elf32_External_Dyn *dyncon, *dynconend;
17455
362d30a1 17456 splt = htab->root.splt;
24a1ba0f 17457 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 17458 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 17459
17460 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 17461 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 17462
252b5132
RH		 17463 for (; dyncon < dynconend; dyncon++)
17464 {
17465 Elf_Internal_Dyn dyn;
17466 const char * name;
17467 asection * s;
17468
17469 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
17470
17471 switch (dyn.d_tag)
17472 {
229fcec5
MM		 17473 unsigned int type;
17474
252b5132 17475 default:
7a2b07ff
NS		 17476 if (htab->vxworks_p
17477 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
17478 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 17479 break;
17480
229fcec5
MM		 17481 case DT_HASH:
17482 name = ".hash";
17483 goto get_vma_if_bpabi;
17484 case DT_STRTAB:
17485 name = ".dynstr";
17486 goto get_vma_if_bpabi;
17487 case DT_SYMTAB:
17488 name = ".dynsym";
17489 goto get_vma_if_bpabi;
c0042f5d
MM		 17490 case DT_VERSYM:
17491 name = ".gnu.version";
17492 goto get_vma_if_bpabi;
17493 case DT_VERDEF:
17494 name = ".gnu.version_d";
17495 goto get_vma_if_bpabi;
17496 case DT_VERNEED:
17497 name = ".gnu.version_r";
17498 goto get_vma_if_bpabi;
17499
252b5132 17500 case DT_PLTGOT:
4ade44b7 17501 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 17502 goto get_vma;
17503 case DT_JMPREL:
00a97672 17504 name = RELOC_SECTION (htab, ".plt");
252b5132 17505 get_vma:
4ade44b7 17506 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 17507 if (s == NULL)
17508 {
4eca0228 17509 _bfd_error_handler
4ade44b7 17510 (_("could not find section %s"), name);
05456594
NC		 17511 bfd_set_error (bfd_error_invalid_operation);
17512 return FALSE;
17513 }
229fcec5 17514 if (!htab->symbian_p)
4ade44b7 17515 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 17516 else
17517 /* In the BPABI, tags in the PT_DYNAMIC section point
17518 at the file offset, not the memory address, for the
17519 convenience of the post linker. */
4ade44b7 17520 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 17521 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17522 break;
17523
229fcec5
MM		 17524 get_vma_if_bpabi:
17525 if (htab->symbian_p)
17526 goto get_vma;
17527 break;
17528
252b5132 17529 case DT_PLTRELSZ:
362d30a1 17530 s = htab->root.srelplt;
252b5132 17531 BFD_ASSERT (s != NULL);
eea6121a 17532 dyn.d_un.d_val = s->size;
252b5132
RH		 17533 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17534 break;
906e58ca 17535
252b5132 17536 case DT_RELSZ:
00a97672 17537 case DT_RELASZ:
229fcec5
MM		 17538 case DT_REL:
17539 case DT_RELA:
229fcec5
MM		 17540 /* In the BPABI, the DT_REL tag must point at the file
17541 offset, not the VMA, of the first relocation
17542 section. So, we use code similar to that in
17543 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 17544 relocation section, since relocation sections are
17545 never allocated under the BPABI. PLT relocs are also
17546 included. */
229fcec5
MM		 17547 if (htab->symbian_p)
17548 {
17549 unsigned int i;
17550 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
17551 ? SHT_REL : SHT_RELA);
17552 dyn.d_un.d_val = 0;
17553 for (i = 1; i < elf_numsections (output_bfd); i++)
17554 {
906e58ca 17555 Elf_Internal_Shdr *hdr
229fcec5
MM		 17556 = elf_elfsections (output_bfd)[i];
17557 if (hdr->sh_type == type)
17558 {
906e58ca 17559 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 17560 || dyn.d_tag == DT_RELASZ)
17561 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 17562 else if ((ufile_ptr) hdr->sh_offset
17563 <= dyn.d_un.d_val - 1)
229fcec5
MM		 17564 dyn.d_un.d_val = hdr->sh_offset;
17565 }
17566 }
17567 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17568 }
252b5132 17569 break;
88f7bcd5 17570
0855e32b 17571 case DT_TLSDESC_PLT:
99059e56 17572 s = htab->root.splt;
0855e32b
NS		 17573 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
17574 + htab->dt_tlsdesc_plt);
17575 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17576 break;
17577
17578 case DT_TLSDESC_GOT:
99059e56 17579 s = htab->root.sgot;
0855e32b 17580 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 17581 + htab->dt_tlsdesc_got);
0855e32b
NS		 17582 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17583 break;
17584
88f7bcd5
NC		 17585 /* Set the bottom bit of DT_INIT/FINI if the
17586 corresponding function is Thumb. */
17587 case DT_INIT:
17588 name = info->init_function;
17589 goto get_sym;
17590 case DT_FINI:
17591 name = info->fini_function;
17592 get_sym:
17593 /* If it wasn't set by elf_bfd_final_link
4cc11e76 17594 then there is nothing to adjust. */
88f7bcd5
NC		 17595 if (dyn.d_un.d_val != 0)
17596 {
17597 struct elf_link_hash_entry * eh;
17598
17599 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 17600 FALSE, FALSE, TRUE);
39d911fc
TP		 17601 if (eh != NULL
17602 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
17603 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 17604 {
17605 dyn.d_un.d_val |= 1;
b34976b6 17606 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 17607 }
17608 }
17609 break;
252b5132
RH		 17610 }
17611 }
17612
24a1ba0f 17613 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 17614 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 17615 {
00a97672
RS		 17616 const bfd_vma *plt0_entry;
17617 bfd_vma got_address, plt_address, got_displacement;
17618
17619 /* Calculate the addresses of the GOT and PLT. */
17620 got_address = sgot->output_section->vma + sgot->output_offset;
17621 plt_address = splt->output_section->vma + splt->output_offset;
17622
17623 if (htab->vxworks_p)
17624 {
17625 /* The VxWorks GOT is relocated by the dynamic linker.
17626 Therefore, we must emit relocations rather than simply
17627 computing the values now. */
17628 Elf_Internal_Rela rel;
17629
17630 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 17631 put_arm_insn (htab, output_bfd, plt0_entry[0],
17632 splt->contents + 0);
17633 put_arm_insn (htab, output_bfd, plt0_entry[1],
17634 splt->contents + 4);
17635 put_arm_insn (htab, output_bfd, plt0_entry[2],
17636 splt->contents + 8);
00a97672
RS		 17637 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
17638
8029a119 17639 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 17640 rel.r_offset = plt_address + 12;
17641 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17642 rel.r_addend = 0;
17643 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
17644 htab->srelplt2->contents);
17645 }
b38cadfb 17646 else if (htab->nacl_p)
99059e56
RM		 17647 arm_nacl_put_plt0 (htab, output_bfd, splt,
17648 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 17649 else if (using_thumb_only (htab))
17650 {
17651 got_displacement = got_address - (plt_address + 12);
17652
17653 plt0_entry = elf32_thumb2_plt0_entry;
17654 put_arm_insn (htab, output_bfd, plt0_entry[0],
17655 splt->contents + 0);
17656 put_arm_insn (htab, output_bfd, plt0_entry[1],
17657 splt->contents + 4);
17658 put_arm_insn (htab, output_bfd, plt0_entry[2],
17659 splt->contents + 8);
17660
17661 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
17662 }
00a97672
RS		 17663 else
17664 {
17665 got_displacement = got_address - (plt_address + 16);
17666
17667 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 17668 put_arm_insn (htab, output_bfd, plt0_entry[0],
17669 splt->contents + 0);
17670 put_arm_insn (htab, output_bfd, plt0_entry[1],
17671 splt->contents + 4);
17672 put_arm_insn (htab, output_bfd, plt0_entry[2],
17673 splt->contents + 8);
17674 put_arm_insn (htab, output_bfd, plt0_entry[3],
17675 splt->contents + 12);
5e681ec4 17676
5e681ec4 17677#ifdef FOUR_WORD_PLT
00a97672
RS		 17678 /* The displacement value goes in the otherwise-unused
17679 last word of the second entry. */
17680 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 17681#else
00a97672 17682 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 17683#endif
00a97672 17684 }
f7a74f8c 17685 }
252b5132
RH		 17686
17687 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17688 really seem like the right value. */
74541ad4
AM		 17689 if (splt->output_section->owner == output_bfd)
17690 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 17691
0855e32b
NS		 17692 if (htab->dt_tlsdesc_plt)
17693 {
17694 bfd_vma got_address
17695 = sgot->output_section->vma + sgot->output_offset;
17696 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
17697 + htab->root.sgot->output_offset);
17698 bfd_vma plt_address
17699 = splt->output_section->vma + splt->output_offset;
17700
b38cadfb 17701 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17702 splt->contents + htab->dt_tlsdesc_plt,
17703 dl_tlsdesc_lazy_trampoline, 6);
17704
17705 bfd_put_32 (output_bfd,
17706 gotplt_address + htab->dt_tlsdesc_got
17707 - (plt_address + htab->dt_tlsdesc_plt)
17708 - dl_tlsdesc_lazy_trampoline[6],
17709 splt->contents + htab->dt_tlsdesc_plt + 24);
17710 bfd_put_32 (output_bfd,
17711 got_address - (plt_address + htab->dt_tlsdesc_plt)
17712 - dl_tlsdesc_lazy_trampoline[7],
17713 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
17714 }
17715
17716 if (htab->tls_trampoline)
17717 {
b38cadfb 17718 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17719 splt->contents + htab->tls_trampoline,
17720 tls_trampoline, 3);
17721#ifdef FOUR_WORD_PLT
17722 bfd_put_32 (output_bfd, 0x00000000,
17723 splt->contents + htab->tls_trampoline + 12);
b38cadfb 17724#endif
0855e32b
NS		 17725 }
17726
0e1862bb
L		 17727 if (htab->vxworks_p
17728 && !bfd_link_pic (info)
17729 && htab->root.splt->size > 0)
00a97672
RS		 17730 {
17731 /* Correct the .rel(a).plt.unloaded relocations. They will have
17732 incorrect symbol indexes. */
17733 int num_plts;
eed62c48 17734 unsigned char *p;
00a97672 17735
362d30a1 17736 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 17737 / htab->plt_entry_size);
17738 p = htab->srelplt2->contents + RELOC_SIZE (htab);
17739
17740 for (; num_plts; num_plts--)
17741 {
17742 Elf_Internal_Rela rel;
17743
17744 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17745 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17746 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17747 p += RELOC_SIZE (htab);
17748
17749 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17750 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
17751 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17752 p += RELOC_SIZE (htab);
17753 }
17754 }
252b5132
RH		 17755 }
17756
99059e56
RM		 17757 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
17758 /* NaCl uses a special first entry in .iplt too. */
17759 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
17760
252b5132 17761 /* Fill in the first three entries in the global offset table. */
229fcec5 17762 if (sgot)
252b5132 17763 {
229fcec5
MM		 17764 if (sgot->size > 0)
17765 {
17766 if (sdyn == NULL)
17767 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
17768 else
17769 bfd_put_32 (output_bfd,
17770 sdyn->output_section->vma + sdyn->output_offset,
17771 sgot->contents);
17772 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
17773 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
17774 }
252b5132 17775
229fcec5
MM		 17776 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
17777 }
252b5132 17778
e8b09b87
CL		 17779 /* At the very end of the .rofixup section is a pointer to the GOT. */
17780 if (htab->fdpic_p && htab->srofixup != NULL)
17781 {
17782 struct elf_link_hash_entry *hgot = htab->root.hgot;
17783
17784 bfd_vma got_value = hgot->root.u.def.value
17785 + hgot->root.u.def.section->output_section->vma
17786 + hgot->root.u.def.section->output_offset;
17787
17788 arm_elf_add_rofixup(output_bfd, htab->srofixup, got_value);
17789
17790 /* Make sure we allocated and generated the same number of fixups. */
17791 BFD_ASSERT (htab->srofixup->reloc_count * 4 == htab->srofixup->size);
17792 }
17793
b34976b6 17794 return TRUE;
252b5132
RH		 17795}
17796
ba96a88f 17797static void
57e8b36a 17798elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 17799{
9b485d32 17800 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 17801 struct elf32_arm_link_hash_table *globals;
ac4c9b04 17802 struct elf_segment_map *m;
ba96a88f
NC		 17803
17804 i_ehdrp = elf_elfheader (abfd);
17805
94a3258f
PB		 17806 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
17807 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
17808 else
7394f108 17809 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 17810 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 17811
93204d3a
PB		 17812 if (link_info)
17813 {
17814 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 17815 if (globals != NULL && globals->byteswap_code)
93204d3a 17816 i_ehdrp->e_flags |= EF_ARM_BE8;
18a20338
CL		 17817
17818 if (globals->fdpic_p)
17819 i_ehdrp->e_ident[EI_OSABI] |= ELFOSABI_ARM_FDPIC;
93204d3a 17820 }
3bfcb652
NC		 17821
17822 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
17823 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
17824 {
17825 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 17826 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 17827 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
17828 else
17829 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
17830 }
ac4c9b04
MG		 17831
17832 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 17833 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 17834 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
17835 {
17836 unsigned int j;
17837
17838 if (m->count == 0)
17839 continue;
17840 for (j = 0; j < m->count; j++)
17841 {
f0728ee3 17842 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 17843 break;
17844 }
17845 if (j == m->count)
17846 {
17847 m->p_flags = PF_X;
17848 m->p_flags_valid = 1;
17849 }
17850 }
ba96a88f
NC		 17851}
17852
99e4ae17 17853static enum elf_reloc_type_class
7e612e98
AM		 17854elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
17855 const asection *rel_sec ATTRIBUTE_UNUSED,
17856 const Elf_Internal_Rela *rela)
99e4ae17 17857{
f51e552e 17858 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 17859 {
17860 case R_ARM_RELATIVE:
17861 return reloc_class_relative;
17862 case R_ARM_JUMP_SLOT:
17863 return reloc_class_plt;
17864 case R_ARM_COPY:
17865 return reloc_class_copy;
109575d7
JW		 17866 case R_ARM_IRELATIVE:
17867 return reloc_class_ifunc;
99e4ae17
AJ		 17868 default:
17869 return reloc_class_normal;
17870 }
17871}
17872
e489d0ae 17873static void
57e8b36a 17874elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 17875{
5a6c6817 17876 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 17877}
17878
40a18ebd
NC		 17879/* Return TRUE if this is an unwinding table entry. */
17880
17881static bfd_boolean
17882is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
17883{
0112cd26
NC		 17884 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
17885 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 17886}
17887
17888
17889/* Set the type and flags for an ARM section. We do this by
17890 the section name, which is a hack, but ought to work. */
17891
17892static bfd_boolean
17893elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
17894{
17895 const char * name;
17896
17897 name = bfd_get_section_name (abfd, sec);
17898
17899 if (is_arm_elf_unwind_section_name (abfd, name))
17900 {
17901 hdr->sh_type = SHT_ARM_EXIDX;
17902 hdr->sh_flags |= SHF_LINK_ORDER;
17903 }
ac4c9b04 17904
f0728ee3
AV		 17905 if (sec->flags & SEC_ELF_PURECODE)
17906 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 17907
40a18ebd
NC		 17908 return TRUE;
17909}
17910
6dc132d9
L		 17911/* Handle an ARM specific section when reading an object file. This is
17912 called when bfd_section_from_shdr finds a section with an unknown
17913 type. */
40a18ebd
NC		 17914
17915static bfd_boolean
17916elf32_arm_section_from_shdr (bfd *abfd,
17917 Elf_Internal_Shdr * hdr,
6dc132d9
L		 17918 const char *name,
17919 int shindex)
40a18ebd
NC		 17920{
17921 /* There ought to be a place to keep ELF backend specific flags, but
17922 at the moment there isn't one. We just keep track of the
17923 sections by their name, instead. Fortunately, the ABI gives
17924 names for all the ARM specific sections, so we will probably get
17925 away with this. */
17926 switch (hdr->sh_type)
17927 {
17928 case SHT_ARM_EXIDX:
0951f019
RE		 17929 case SHT_ARM_PREEMPTMAP:
17930 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 17931 break;
17932
17933 default:
17934 return FALSE;
17935 }
17936
6dc132d9 17937 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 17938 return FALSE;
17939
17940 return TRUE;
17941}
e489d0ae 17942
44444f50
NC		 17943static _arm_elf_section_data *
17944get_arm_elf_section_data (asection * sec)
17945{
47b2e99c
JZ		 17946 if (sec && sec->owner && is_arm_elf (sec->owner))
17947 return elf32_arm_section_data (sec);
44444f50
NC		 17948 else
17949 return NULL;
8e3de13a
NC		 17950}
17951
4e617b1e
PB		 17952typedef struct
17953{
57402f1e 17954 void *flaginfo;
4e617b1e 17955 struct bfd_link_info *info;
91a5743d
PB		 17956 asection *sec;
17957 int sec_shndx;
6e0b88f1
AM		 17958 int (*func) (void *, const char *, Elf_Internal_Sym *,
17959 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 17960} output_arch_syminfo;
17961
17962enum map_symbol_type
17963{
17964 ARM_MAP_ARM,
17965 ARM_MAP_THUMB,
17966 ARM_MAP_DATA
17967};
17968
17969
7413f23f 17970/* Output a single mapping symbol. */
4e617b1e
PB		 17971
17972static bfd_boolean
7413f23f
DJ		 17973elf32_arm_output_map_sym (output_arch_syminfo *osi,
17974 enum map_symbol_type type,
17975 bfd_vma offset)
4e617b1e
PB		 17976{
17977 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 17978 Elf_Internal_Sym sym;
17979
91a5743d
PB		 17980 sym.st_value = osi->sec->output_section->vma
17981 + osi->sec->output_offset
17982 + offset;
4e617b1e
PB		 17983 sym.st_size = 0;
17984 sym.st_other = 0;
17985 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 17986 sym.st_shndx = osi->sec_shndx;
35fc36a8 17987 sym.st_target_internal = 0;
fe33d2fa 17988 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 17989 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 17990}
17991
34e77a92
RS		 17992/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
17993 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 17994
17995static bfd_boolean
34e77a92
RS		 17996elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
17997 bfd_boolean is_iplt_entry_p,
17998 union gotplt_union *root_plt,
17999 struct arm_plt_info *arm_plt)
4e617b1e 18000{
4e617b1e 18001 struct elf32_arm_link_hash_table *htab;
34e77a92 18002 bfd_vma addr, plt_header_size;
4e617b1e 18003
34e77a92 18004 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 18005 return TRUE;
18006
4dfe6ac6
NC		 18007 htab = elf32_arm_hash_table (osi->info);
18008 if (htab == NULL)
18009 return FALSE;
18010
34e77a92
RS		 18011 if (is_iplt_entry_p)
18012 {
18013 osi->sec = htab->root.iplt;
18014 plt_header_size = 0;
18015 }
18016 else
18017 {
18018 osi->sec = htab->root.splt;
18019 plt_header_size = htab->plt_header_size;
18020 }
18021 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
18022 (osi->info->output_bfd, osi->sec->output_section));
18023
18024 addr = root_plt->offset & -2;
4e617b1e
PB		 18025 if (htab->symbian_p)
18026 {
7413f23f 18027 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18028 return FALSE;
7413f23f 18029 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 18030 return FALSE;
18031 }
18032 else if (htab->vxworks_p)
18033 {
7413f23f 18034 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18035 return FALSE;
7413f23f 18036 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 18037 return FALSE;
7413f23f 18038 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 18039 return FALSE;
7413f23f 18040 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 18041 return FALSE;
18042 }
b38cadfb
NC		 18043 else if (htab->nacl_p)
18044 {
18045 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
18046 return FALSE;
18047 }
7801f98f
CL		 18048 else if (htab->fdpic_p)
18049 {
59029f57
CL		 18050 enum map_symbol_type type = using_thumb_only(htab)
18051 ? ARM_MAP_THUMB
18052 : ARM_MAP_ARM;
18053
7801f98f 18054 if (elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt))
4b24dd1a
AM		 18055 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
18056 return FALSE;
59029f57 18057 if (!elf32_arm_output_map_sym (osi, type, addr))
4b24dd1a 18058 return FALSE;
7801f98f 18059 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 16))
4b24dd1a 18060 return FALSE;
7801f98f 18061 if (htab->plt_entry_size == 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry))
4b24dd1a
AM		 18062 if (!elf32_arm_output_map_sym (osi, type, addr + 24))
18063 return FALSE;
7801f98f 18064 }
eed94f8f
NC		 18065 else if (using_thumb_only (htab))
18066 {
18067 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
18068 return FALSE;
6a631e86 18069 }
4e617b1e
PB		 18070 else
18071 {
34e77a92 18072 bfd_boolean thumb_stub_p;
bd97cb95 18073
34e77a92
RS		 18074 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
18075 if (thumb_stub_p)
4e617b1e 18076 {
7413f23f 18077 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 18078 return FALSE;
18079 }
18080#ifdef FOUR_WORD_PLT
7413f23f 18081 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18082 return FALSE;
7413f23f 18083 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 18084 return FALSE;
18085#else
906e58ca 18086 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 18087 so only need to output a mapping symbol for the first PLT entry and
18088 entries with thumb thunks. */
34e77a92 18089 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 18090 {
7413f23f 18091 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 18092 return FALSE;
18093 }
18094#endif
18095 }
18096
18097 return TRUE;
18098}
18099
34e77a92
RS		 18100/* Output mapping symbols for PLT entries associated with H. */
18101
18102static bfd_boolean
18103elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
18104{
18105 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
18106 struct elf32_arm_link_hash_entry *eh;
18107
18108 if (h->root.type == bfd_link_hash_indirect)
18109 return TRUE;
18110
18111 if (h->root.type == bfd_link_hash_warning)
18112 /* When warning symbols are created, they **replace** the "real"
18113 entry in the hash table, thus we never get to see the real
18114 symbol in a hash traversal. So look at it now. */
18115 h = (struct elf_link_hash_entry *) h->root.u.i.link;
18116
18117 eh = (struct elf32_arm_link_hash_entry *) h;
18118 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
18119 &h->plt, &eh->plt);
18120}
18121
4f4faa4d
TP		 18122/* Bind a veneered symbol to its veneer identified by its hash entry
18123 STUB_ENTRY. The veneered location thus loose its symbol. */
18124
18125static void
18126arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
18127{
18128 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
18129
18130 BFD_ASSERT (hash);
18131 hash->root.root.u.def.section = stub_entry->stub_sec;
18132 hash->root.root.u.def.value = stub_entry->stub_offset;
18133 hash->root.size = stub_entry->stub_size;
18134}
18135
7413f23f
DJ		 18136/* Output a single local symbol for a generated stub. */
18137
18138static bfd_boolean
18139elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
18140 bfd_vma offset, bfd_vma size)
18141{
7413f23f
DJ		 18142 Elf_Internal_Sym sym;
18143
7413f23f
DJ		 18144 sym.st_value = osi->sec->output_section->vma
18145 + osi->sec->output_offset
18146 + offset;
18147 sym.st_size = size;
18148 sym.st_other = 0;
18149 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
18150 sym.st_shndx = osi->sec_shndx;
35fc36a8 18151 sym.st_target_internal = 0;
57402f1e 18152 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 18153}
4e617b1e 18154
da5938a2 18155static bfd_boolean
8029a119
NC		 18156arm_map_one_stub (struct bfd_hash_entry * gen_entry,
18157 void * in_arg)
da5938a2
NC		 18158{
18159 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 18160 asection *stub_sec;
18161 bfd_vma addr;
7413f23f 18162 char *stub_name;
9a008db3 18163 output_arch_syminfo *osi;
d3ce72d0 18164 const insn_sequence *template_sequence;
461a49ca
DJ		 18165 enum stub_insn_type prev_type;
18166 int size;
18167 int i;
18168 enum map_symbol_type sym_type;
da5938a2
NC		 18169
18170 /* Massage our args to the form they really have. */
18171 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 18172 osi = (output_arch_syminfo *) in_arg;
da5938a2 18173
da5938a2
NC		 18174 stub_sec = stub_entry->stub_sec;
18175
18176 /* Ensure this stub is attached to the current section being
7413f23f 18177 processed. */
da5938a2
NC		 18178 if (stub_sec != osi->sec)
18179 return TRUE;
18180
7413f23f 18181 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 18182 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 18183
18184 if (arm_stub_sym_claimed (stub_entry->stub_type))
18185 arm_stub_claim_sym (stub_entry);
18186 else
7413f23f 18187 {
4f4faa4d
TP		 18188 stub_name = stub_entry->output_name;
18189 switch (template_sequence[0].type)
18190 {
18191 case ARM_TYPE:
18192 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
18193 stub_entry->stub_size))
18194 return FALSE;
18195 break;
18196 case THUMB16_TYPE:
18197 case THUMB32_TYPE:
18198 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
18199 stub_entry->stub_size))
18200 return FALSE;
18201 break;
18202 default:
18203 BFD_FAIL ();
18204 return 0;
18205 }
7413f23f 18206 }
da5938a2 18207
461a49ca
DJ		 18208 prev_type = DATA_TYPE;
18209 size = 0;
18210 for (i = 0; i < stub_entry->stub_template_size; i++)
18211 {
d3ce72d0 18212 switch (template_sequence[i].type)
461a49ca
DJ		 18213 {
18214 case ARM_TYPE:
18215 sym_type = ARM_MAP_ARM;
18216 break;
18217
18218 case THUMB16_TYPE:
48229727 18219 case THUMB32_TYPE:
461a49ca
DJ		 18220 sym_type = ARM_MAP_THUMB;
18221 break;
18222
18223 case DATA_TYPE:
18224 sym_type = ARM_MAP_DATA;
18225 break;
18226
18227 default:
18228 BFD_FAIL ();
4e31c731 18229 return FALSE;
461a49ca
DJ		 18230 }
18231
d3ce72d0 18232 if (template_sequence[i].type != prev_type)
461a49ca 18233 {
d3ce72d0 18234 prev_type = template_sequence[i].type;
461a49ca
DJ		 18235 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
18236 return FALSE;
18237 }
18238
d3ce72d0 18239 switch (template_sequence[i].type)
461a49ca
DJ		 18240 {
18241 case ARM_TYPE:
48229727 18242 case THUMB32_TYPE:
461a49ca
DJ		 18243 size += 4;
18244 break;
18245
18246 case THUMB16_TYPE:
18247 size += 2;
18248 break;
18249
18250 case DATA_TYPE:
18251 size += 4;
18252 break;
18253
18254 default:
18255 BFD_FAIL ();
4e31c731 18256 return FALSE;
461a49ca
DJ		 18257 }
18258 }
18259
da5938a2
NC		 18260 return TRUE;
18261}
18262
33811162
DG		 18263/* Output mapping symbols for linker generated sections,
18264 and for those data-only sections that do not have a
18265 $d. */
4e617b1e
PB		 18266
18267static bfd_boolean
18268elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 18269 struct bfd_link_info *info,
57402f1e 18270 void *flaginfo,
6e0b88f1
AM		 18271 int (*func) (void *, const char *,
18272 Elf_Internal_Sym *,
18273 asection *,
18274 struct elf_link_hash_entry *))
4e617b1e
PB		 18275{
18276 output_arch_syminfo osi;
18277 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 18278 bfd_vma offset;
18279 bfd_size_type size;
33811162 18280 bfd *input_bfd;
4e617b1e
PB		 18281
18282 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 18283 if (htab == NULL)
18284 return FALSE;
18285
906e58ca 18286 check_use_blx (htab);
91a5743d 18287
57402f1e 18288 osi.flaginfo = flaginfo;
4e617b1e
PB		 18289 osi.info = info;
18290 osi.func = func;
906e58ca 18291
33811162
DG		 18292 /* Add a $d mapping symbol to data-only sections that
18293 don't have any mapping symbol. This may result in (harmless) redundant
18294 mapping symbols. */
18295 for (input_bfd = info->input_bfds;
18296 input_bfd != NULL;
c72f2fb2 18297 input_bfd = input_bfd->link.next)
33811162
DG		 18298 {
18299 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
18300 for (osi.sec = input_bfd->sections;
18301 osi.sec != NULL;
18302 osi.sec = osi.sec->next)
18303 {
18304 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 18305 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
18306 != 0)
33811162
DG		 18307 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
18308 == SEC_HAS_CONTENTS
18309 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 18310 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 18311 && osi.sec->size > 0
18312 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 18313 {
18314 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18315 (output_bfd, osi.sec->output_section);
18316 if (osi.sec_shndx != (int)SHN_BAD)
18317 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
18318 }
18319 }
18320 }
18321
91a5743d
PB		 18322 /* ARM->Thumb glue. */
18323 if (htab->arm_glue_size > 0)
18324 {
3d4d4302
AM		 18325 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18326 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 18327
18328 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18329 (output_bfd, osi.sec->output_section);
0e1862bb 18330 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 18331 || htab->pic_veneer)
18332 size = ARM2THUMB_PIC_GLUE_SIZE;
18333 else if (htab->use_blx)
18334 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
18335 else
18336 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 18337
91a5743d
PB		 18338 for (offset = 0; offset < htab->arm_glue_size; offset += size)
18339 {
7413f23f
DJ		 18340 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
18341 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 18342 }
18343 }
18344
18345 /* Thumb->ARM glue. */
18346 if (htab->thumb_glue_size > 0)
18347 {
3d4d4302
AM		 18348 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18349 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 18350
18351 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18352 (output_bfd, osi.sec->output_section);
18353 size = THUMB2ARM_GLUE_SIZE;
18354
18355 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
18356 {
7413f23f
DJ		 18357 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
18358 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 18359 }
18360 }
18361
845b51d6
PB		 18362 /* ARMv4 BX veneers. */
18363 if (htab->bx_glue_size > 0)
18364 {
3d4d4302
AM		 18365 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18366 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 18367
18368 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18369 (output_bfd, osi.sec->output_section);
18370
7413f23f 18371 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 18372 }
18373
8029a119
NC		 18374 /* Long calls stubs. */
18375 if (htab->stub_bfd && htab->stub_bfd->sections)
18376 {
da5938a2 18377 asection* stub_sec;
8029a119 18378
da5938a2
NC		 18379 for (stub_sec = htab->stub_bfd->sections;
18380 stub_sec != NULL;
8029a119
NC		 18381 stub_sec = stub_sec->next)
18382 {
18383 /* Ignore non-stub sections. */
18384 if (!strstr (stub_sec->name, STUB_SUFFIX))
18385 continue;
da5938a2 18386
8029a119 18387 osi.sec = stub_sec;
da5938a2 18388
8029a119
NC		 18389 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18390 (output_bfd, osi.sec->output_section);
da5938a2 18391
8029a119
NC		 18392 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
18393 }
18394 }
da5938a2 18395
91a5743d 18396 /* Finally, output mapping symbols for the PLT. */
34e77a92 18397 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 18398 {
34e77a92
RS		 18399 osi.sec = htab->root.splt;
18400 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18401 (output_bfd, osi.sec->output_section));
18402
18403 /* Output mapping symbols for the plt header. SymbianOS does not have a
18404 plt header. */
18405 if (htab->vxworks_p)
18406 {
18407 /* VxWorks shared libraries have no PLT header. */
0e1862bb 18408 if (!bfd_link_pic (info))
34e77a92
RS		 18409 {
18410 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18411 return FALSE;
18412 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18413 return FALSE;
18414 }
18415 }
b38cadfb
NC		 18416 else if (htab->nacl_p)
18417 {
18418 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18419 return FALSE;
18420 }
59029f57 18421 else if (using_thumb_only (htab) && !htab->fdpic_p)
eed94f8f
NC		 18422 {
18423 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
18424 return FALSE;
18425 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18426 return FALSE;
18427 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
18428 return FALSE;
18429 }
e8b09b87 18430 else if (!htab->symbian_p && !htab->fdpic_p)
4e617b1e 18431 {
7413f23f 18432 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 18433 return FALSE;
34e77a92
RS		 18434#ifndef FOUR_WORD_PLT
18435 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 18436 return FALSE;
34e77a92 18437#endif
4e617b1e
PB		 18438 }
18439 }
99059e56
RM		 18440 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
18441 {
18442 /* NaCl uses a special first entry in .iplt too. */
18443 osi.sec = htab->root.iplt;
18444 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18445 (output_bfd, osi.sec->output_section));
18446 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18447 return FALSE;
18448 }
34e77a92
RS		 18449 if ((htab->root.splt && htab->root.splt->size > 0)
18450 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 18451 {
34e77a92
RS		 18452 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
18453 for (input_bfd = info->input_bfds;
18454 input_bfd != NULL;
c72f2fb2 18455 input_bfd = input_bfd->link.next)
34e77a92
RS		 18456 {
18457 struct arm_local_iplt_info **local_iplt;
18458 unsigned int i, num_syms;
4e617b1e 18459
34e77a92
RS		 18460 local_iplt = elf32_arm_local_iplt (input_bfd);
18461 if (local_iplt != NULL)
18462 {
18463 num_syms = elf_symtab_hdr (input_bfd).sh_info;
18464 for (i = 0; i < num_syms; i++)
18465 if (local_iplt[i] != NULL
18466 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
18467 &local_iplt[i]->root,
18468 &local_iplt[i]->arm))
18469 return FALSE;
18470 }
18471 }
18472 }
0855e32b
NS		 18473 if (htab->dt_tlsdesc_plt != 0)
18474 {
18475 /* Mapping symbols for the lazy tls trampoline. */
18476 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
18477 return FALSE;
b38cadfb 18478
0855e32b
NS		 18479 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18480 htab->dt_tlsdesc_plt + 24))
18481 return FALSE;
18482 }
18483 if (htab->tls_trampoline != 0)
18484 {
18485 /* Mapping symbols for the tls trampoline. */
18486 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
18487 return FALSE;
18488#ifdef FOUR_WORD_PLT
18489 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18490 htab->tls_trampoline + 12))
18491 return FALSE;
b38cadfb 18492#endif
0855e32b 18493 }
b38cadfb 18494
4e617b1e
PB		 18495 return TRUE;
18496}
18497
54ddd295
TP		 18498/* Filter normal symbols of CMSE entry functions of ABFD to include in
18499 the import library. All SYMCOUNT symbols of ABFD can be examined
18500 from their pointers in SYMS. Pointers of symbols to keep should be
18501 stored continuously at the beginning of that array.
18502
18503 Returns the number of symbols to keep. */
18504
18505static unsigned int
18506elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18507 struct bfd_link_info *info,
18508 asymbol **syms, long symcount)
18509{
18510 size_t maxnamelen;
18511 char *cmse_name;
18512 long src_count, dst_count = 0;
18513 struct elf32_arm_link_hash_table *htab;
18514
18515 htab = elf32_arm_hash_table (info);
18516 if (!htab->stub_bfd || !htab->stub_bfd->sections)
18517 symcount = 0;
18518
18519 maxnamelen = 128;
18520 cmse_name = (char *) bfd_malloc (maxnamelen);
18521 for (src_count = 0; src_count < symcount; src_count++)
18522 {
18523 struct elf32_arm_link_hash_entry *cmse_hash;
18524 asymbol *sym;
18525 flagword flags;
18526 char *name;
18527 size_t namelen;
18528
18529 sym = syms[src_count];
18530 flags = sym->flags;
18531 name = (char *) bfd_asymbol_name (sym);
18532
18533 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
18534 continue;
18535 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
18536 continue;
18537
18538 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
18539 if (namelen > maxnamelen)
18540 {
18541 cmse_name = (char *)
18542 bfd_realloc (cmse_name, namelen);
18543 maxnamelen = namelen;
18544 }
18545 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
18546 cmse_hash = (struct elf32_arm_link_hash_entry *)
18547 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
18548
18549 if (!cmse_hash
18550 || (cmse_hash->root.root.type != bfd_link_hash_defined
18551 && cmse_hash->root.root.type != bfd_link_hash_defweak)
18552 || cmse_hash->root.type != STT_FUNC)
18553 continue;
18554
18555 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
18556 continue;
18557
18558 syms[dst_count++] = sym;
18559 }
18560 free (cmse_name);
18561
18562 syms[dst_count] = NULL;
18563
18564 return dst_count;
18565}
18566
18567/* Filter symbols of ABFD to include in the import library. All
18568 SYMCOUNT symbols of ABFD can be examined from their pointers in
18569 SYMS. Pointers of symbols to keep should be stored continuously at
18570 the beginning of that array.
18571
18572 Returns the number of symbols to keep. */
18573
18574static unsigned int
18575elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18576 struct bfd_link_info *info,
18577 asymbol **syms, long symcount)
18578{
18579 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
18580
046734ff
TP		 18581 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18582 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18583 library to be a relocatable object file. */
18584 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
54ddd295
TP		 18585 if (globals->cmse_implib)
18586 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
18587 else
18588 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
18589}
18590
e489d0ae
PB		 18591/* Allocate target specific section data. */
18592
18593static bfd_boolean
18594elf32_arm_new_section_hook (bfd *abfd, asection *sec)
18595{
f592407e
AM		 18596 if (!sec->used_by_bfd)
18597 {
18598 _arm_elf_section_data *sdata;
18599 bfd_size_type amt = sizeof (*sdata);
e489d0ae 18600
21d799b5 18601 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 18602 if (sdata == NULL)
18603 return FALSE;
18604 sec->used_by_bfd = sdata;
18605 }
e489d0ae
PB		 18606
18607 return _bfd_elf_new_section_hook (abfd, sec);
18608}
18609
18610
18611/* Used to order a list of mapping symbols by address. */
18612
18613static int
18614elf32_arm_compare_mapping (const void * a, const void * b)
18615{
7f6a71ff
JM		 18616 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
18617 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
18618
18619 if (amap->vma > bmap->vma)
18620 return 1;
18621 else if (amap->vma < bmap->vma)
18622 return -1;
18623 else if (amap->type > bmap->type)
18624 /* Ensure results do not depend on the host qsort for objects with
18625 multiple mapping symbols at the same address by sorting on type
18626 after vma. */
18627 return 1;
18628 else if (amap->type < bmap->type)
18629 return -1;
18630 else
18631 return 0;
e489d0ae
PB		 18632}
18633
2468f9c9
PB		 18634/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18635
18636static unsigned long
18637offset_prel31 (unsigned long addr, bfd_vma offset)
18638{
18639 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
18640}
18641
18642/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18643 relocations. */
18644
18645static void
18646copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
18647{
18648 unsigned long first_word = bfd_get_32 (output_bfd, from);
18649 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 18650
2468f9c9
PB		 18651 /* High bit of first word is supposed to be zero. */
18652 if ((first_word & 0x80000000ul) == 0)
18653 first_word = offset_prel31 (first_word, offset);
b38cadfb 18654
2468f9c9
PB		 18655 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18656 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18657 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
18658 second_word = offset_prel31 (second_word, offset);
b38cadfb 18659
2468f9c9
PB		 18660 bfd_put_32 (output_bfd, first_word, to);
18661 bfd_put_32 (output_bfd, second_word, to + 4);
18662}
e489d0ae 18663
48229727
JB		 18664/* Data for make_branch_to_a8_stub(). */
18665
b38cadfb
NC		 18666struct a8_branch_to_stub_data
18667{
48229727
JB		 18668 asection *writing_section;
18669 bfd_byte *contents;
18670};
18671
18672
18673/* Helper to insert branches to Cortex-A8 erratum stubs in the right
18674 places for a particular section. */
18675
18676static bfd_boolean
18677make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 18678 void *in_arg)
48229727
JB		 18679{
18680 struct elf32_arm_stub_hash_entry *stub_entry;
18681 struct a8_branch_to_stub_data *data;
18682 bfd_byte *contents;
18683 unsigned long branch_insn;
18684 bfd_vma veneered_insn_loc, veneer_entry_loc;
18685 bfd_signed_vma branch_offset;
18686 bfd *abfd;
8d9d9490 18687 unsigned int loc;
48229727
JB		 18688
18689 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
18690 data = (struct a8_branch_to_stub_data *) in_arg;
18691
18692 if (stub_entry->target_section != data->writing_section
4563a860 18693 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 18694 return TRUE;
18695
18696 contents = data->contents;
18697
8d9d9490
TP		 18698 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18699 generated when both source and target are in the same section. */
48229727
JB		 18700 veneered_insn_loc = stub_entry->target_section->output_section->vma
18701 + stub_entry->target_section->output_offset
8d9d9490 18702 + stub_entry->source_value;
48229727
JB		 18703
18704 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
18705 + stub_entry->stub_sec->output_offset
18706 + stub_entry->stub_offset;
18707
18708 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
18709 veneered_insn_loc &= ~3u;
18710
18711 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
18712
18713 abfd = stub_entry->target_section->owner;
8d9d9490 18714 loc = stub_entry->source_value;
48229727
JB		 18715
18716 /* We attempt to avoid this condition by setting stubs_always_after_branch
18717 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18718 This check is just to be on the safe side... */
18719 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
18720 {
871b3ab2 18721 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub is "
4eca0228 18722 "allocated in unsafe location"), abfd);
48229727
JB		 18723 return FALSE;
18724 }
18725
18726 switch (stub_entry->stub_type)
18727 {
18728 case arm_stub_a8_veneer_b:
18729 case arm_stub_a8_veneer_b_cond:
18730 branch_insn = 0xf0009000;
18731 goto jump24;
18732
18733 case arm_stub_a8_veneer_blx:
18734 branch_insn = 0xf000e800;
18735 goto jump24;
18736
18737 case arm_stub_a8_veneer_bl:
18738 {
18739 unsigned int i1, j1, i2, j2, s;
18740
18741 branch_insn = 0xf000d000;
18742
18743 jump24:
18744 if (branch_offset < -16777216 || branch_offset > 16777214)
18745 {
18746 /* There's not much we can do apart from complain if this
18747 happens. */
871b3ab2 18748 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub out "
4eca0228 18749 "of range (input file too large)"), abfd);
48229727
JB		 18750 return FALSE;
18751 }
18752
18753 /* i1 = not(j1 eor s), so:
18754 not i1 = j1 eor s
18755 j1 = (not i1) eor s. */
18756
18757 branch_insn |= (branch_offset >> 1) & 0x7ff;
18758 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
18759 i2 = (branch_offset >> 22) & 1;
18760 i1 = (branch_offset >> 23) & 1;
18761 s = (branch_offset >> 24) & 1;
18762 j1 = (!i1) ^ s;
18763 j2 = (!i2) ^ s;
18764 branch_insn |= j2 << 11;
18765 branch_insn |= j1 << 13;
18766 branch_insn |= s << 26;
18767 }
18768 break;
18769
18770 default:
18771 BFD_FAIL ();
18772 return FALSE;
18773 }
18774
8d9d9490
TP		 18775 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
18776 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 18777
18778 return TRUE;
18779}
18780
a504d23a
LA		 18781/* Beginning of stm32l4xx work-around. */
18782
18783/* Functions encoding instructions necessary for the emission of the
18784 fix-stm32l4xx-629360.
18785 Encoding is extracted from the
18786 ARM (C) Architecture Reference Manual
18787 ARMv7-A and ARMv7-R edition
18788 ARM DDI 0406C.b (ID072512). */
18789
18790static inline bfd_vma
82188b29 18791create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 18792{
18793 /* A8.8.18 B (A8-334)
18794 B target_address (Encoding T4). */
18795 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18796 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18797 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18798
a504d23a
LA		 18799 int s = ((branch_offset & 0x1000000) >> 24);
18800 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
18801 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
18802
18803 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
18804 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
18805
18806 bfd_vma patched_inst = 0xf0009000
18807 | s << 26 /* S. */
18808 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
18809 | j1 << 13 /* J1. */
18810 | j2 << 11 /* J2. */
18811 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
18812
18813 return patched_inst;
18814}
18815
18816static inline bfd_vma
18817create_instruction_ldmia (int base_reg, int wback, int reg_mask)
18818{
18819 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18820 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18821 bfd_vma patched_inst = 0xe8900000
18822 | (/*W=*/wback << 21)
18823 | (base_reg << 16)
18824 | (reg_mask & 0x0000ffff);
18825
18826 return patched_inst;
18827}
18828
18829static inline bfd_vma
18830create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
18831{
18832 /* A8.8.60 LDMDB/LDMEA (A8-402)
18833 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18834 bfd_vma patched_inst = 0xe9100000
18835 | (/*W=*/wback << 21)
18836 | (base_reg << 16)
18837 | (reg_mask & 0x0000ffff);
18838
18839 return patched_inst;
18840}
18841
18842static inline bfd_vma
18843create_instruction_mov (int target_reg, int source_reg)
18844{
18845 /* A8.8.103 MOV (register) (A8-486)
18846 MOV Rd, Rm (Encoding T1). */
18847 bfd_vma patched_inst = 0x4600
18848 | (target_reg & 0x7)
18849 | ((target_reg & 0x8) >> 3) << 7
18850 | (source_reg << 3);
18851
18852 return patched_inst;
18853}
18854
18855static inline bfd_vma
18856create_instruction_sub (int target_reg, int source_reg, int value)
18857{
18858 /* A8.8.221 SUB (immediate) (A8-708)
18859 SUB Rd, Rn, #value (Encoding T3). */
18860 bfd_vma patched_inst = 0xf1a00000
18861 | (target_reg << 8)
18862 | (source_reg << 16)
18863 | (/*S=*/0 << 20)
18864 | ((value & 0x800) >> 11) << 26
18865 | ((value & 0x700) >> 8) << 12
18866 | (value & 0x0ff);
18867
18868 return patched_inst;
18869}
18870
18871static inline bfd_vma
9239bbd3 18872create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 18873 int first_reg)
18874{
18875 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18876 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18877 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 18878 | (/*W=*/wback << 21)
18879 | (base_reg << 16)
9239bbd3
CM		 18880 | (num_words & 0x000000ff)
18881 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 18882 | (first_reg & 0x00000001) << 22;
18883
18884 return patched_inst;
18885}
18886
18887static inline bfd_vma
9239bbd3
CM		 18888create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
18889 int first_reg)
a504d23a
LA		 18890{
18891 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18892 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18893 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 18894 | (base_reg << 16)
9239bbd3
CM		 18895 | (num_words & 0x000000ff)
18896 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 18897 | (first_reg & 0x00000001) << 22;
18898
18899 return patched_inst;
18900}
18901
18902static inline bfd_vma
18903create_instruction_udf_w (int value)
18904{
18905 /* A8.8.247 UDF (A8-758)
18906 Undefined (Encoding T2). */
18907 bfd_vma patched_inst = 0xf7f0a000
18908 | (value & 0x00000fff)
18909 | (value & 0x000f0000) << 16;
18910
18911 return patched_inst;
18912}
18913
18914static inline bfd_vma
18915create_instruction_udf (int value)
18916{
18917 /* A8.8.247 UDF (A8-758)
18918 Undefined (Encoding T1). */
18919 bfd_vma patched_inst = 0xde00
18920 | (value & 0xff);
18921
18922 return patched_inst;
18923}
18924
18925/* Functions writing an instruction in memory, returning the next
18926 memory position to write to. */
18927
18928static inline bfd_byte *
18929push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
18930 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18931{
18932 put_thumb2_insn (htab, output_bfd, insn, pt);
18933 return pt + 4;
18934}
18935
18936static inline bfd_byte *
18937push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
18938 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18939{
18940 put_thumb_insn (htab, output_bfd, insn, pt);
18941 return pt + 2;
18942}
18943
18944/* Function filling up a region in memory with T1 and T2 UDFs taking
18945 care of alignment. */
18946
18947static bfd_byte *
18948stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
07d6d2b8
AM		 18949 bfd * output_bfd,
18950 const bfd_byte * const base_stub_contents,
18951 bfd_byte * const from_stub_contents,
18952 const bfd_byte * const end_stub_contents)
a504d23a
LA		 18953{
18954 bfd_byte *current_stub_contents = from_stub_contents;
18955
18956 /* Fill the remaining of the stub with deterministic contents : UDF
18957 instructions.
18958 Check if realignment is needed on modulo 4 frontier using T1, to
18959 further use T2. */
18960 if ((current_stub_contents < end_stub_contents)
18961 && !((current_stub_contents - base_stub_contents) % 2)
18962 && ((current_stub_contents - base_stub_contents) % 4))
18963 current_stub_contents =
18964 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18965 create_instruction_udf (0));
18966
18967 for (; current_stub_contents < end_stub_contents;)
18968 current_stub_contents =
18969 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18970 create_instruction_udf_w (0));
18971
18972 return current_stub_contents;
18973}
18974
18975/* Functions writing the stream of instructions equivalent to the
18976 derived sequence for ldmia, ldmdb, vldm respectively. */
18977
18978static void
18979stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
18980 bfd * output_bfd,
18981 const insn32 initial_insn,
18982 const bfd_byte *const initial_insn_addr,
18983 bfd_byte *const base_stub_contents)
18984{
18985 int wback = (initial_insn & 0x00200000) >> 21;
18986 int ri, rn = (initial_insn & 0x000F0000) >> 16;
18987 int insn_all_registers = initial_insn & 0x0000ffff;
18988 int insn_low_registers, insn_high_registers;
18989 int usable_register_mask;
b25e998d 18990 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18991 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18992 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
18993 bfd_byte *current_stub_contents = base_stub_contents;
18994
18995 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
18996
18997 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18998 smaller than 8 registers load sequences that do not cause the
18999 hardware issue. */
19000 if (nb_registers <= 8)
19001 {
19002 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
19003 current_stub_contents =
19004 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19005 initial_insn);
19006
19007 /* B initial_insn_addr+4. */
19008 if (!restore_pc)
19009 current_stub_contents =
19010 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19011 create_instruction_branch_absolute
82188b29 19012 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19013
19014 /* Fill the remaining of the stub with deterministic contents. */
19015 current_stub_contents =
19016 stm32l4xx_fill_stub_udf (htab, output_bfd,
19017 base_stub_contents, current_stub_contents,
19018 base_stub_contents +
19019 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19020
19021 return;
19022 }
19023
19024 /* - reg_list[13] == 0. */
19025 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
19026
19027 /* - reg_list[14] & reg_list[15] != 1. */
19028 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
19029
19030 /* - if (wback==1) reg_list[rn] == 0. */
19031 BFD_ASSERT (!wback || !restore_rn);
19032
19033 /* - nb_registers > 8. */
b25e998d 19034 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19035
19036 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19037
19038 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
19039 - One with the 7 lowest registers (register mask 0x007F)
19040 This LDM will finally contain between 2 and 7 registers
19041 - One with the 7 highest registers (register mask 0xDF80)
19042 This ldm will finally contain between 2 and 7 registers. */
19043 insn_low_registers = insn_all_registers & 0x007F;
19044 insn_high_registers = insn_all_registers & 0xDF80;
19045
19046 /* A spare register may be needed during this veneer to temporarily
19047 handle the base register. This register will be restored with the
19048 last LDM operation.
19049 The usable register may be any general purpose register (that
19050 excludes PC, SP, LR : register mask is 0x1FFF). */
19051 usable_register_mask = 0x1FFF;
19052
19053 /* Generate the stub function. */
19054 if (wback)
19055 {
19056 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
19057 current_stub_contents =
19058 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19059 create_instruction_ldmia
19060 (rn, /*wback=*/1, insn_low_registers));
19061
19062 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
19063 current_stub_contents =
19064 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19065 create_instruction_ldmia
19066 (rn, /*wback=*/1, insn_high_registers));
19067 if (!restore_pc)
19068 {
19069 /* B initial_insn_addr+4. */
19070 current_stub_contents =
19071 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19072 create_instruction_branch_absolute
82188b29 19073 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19074 }
19075 }
19076 else /* if (!wback). */
19077 {
19078 ri = rn;
19079
19080 /* If Rn is not part of the high-register-list, move it there. */
19081 if (!(insn_high_registers & (1 << rn)))
19082 {
19083 /* Choose a Ri in the high-register-list that will be restored. */
19084 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19085
19086 /* MOV Ri, Rn. */
19087 current_stub_contents =
19088 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19089 create_instruction_mov (ri, rn));
19090 }
19091
19092 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
19093 current_stub_contents =
19094 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19095 create_instruction_ldmia
19096 (ri, /*wback=*/1, insn_low_registers));
19097
19098 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
19099 current_stub_contents =
19100 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19101 create_instruction_ldmia
19102 (ri, /*wback=*/0, insn_high_registers));
19103
19104 if (!restore_pc)
19105 {
19106 /* B initial_insn_addr+4. */
19107 current_stub_contents =
19108 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19109 create_instruction_branch_absolute
82188b29 19110 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19111 }
19112 }
19113
19114 /* Fill the remaining of the stub with deterministic contents. */
19115 current_stub_contents =
19116 stm32l4xx_fill_stub_udf (htab, output_bfd,
19117 base_stub_contents, current_stub_contents,
19118 base_stub_contents +
19119 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19120}
19121
19122static void
19123stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
19124 bfd * output_bfd,
19125 const insn32 initial_insn,
19126 const bfd_byte *const initial_insn_addr,
19127 bfd_byte *const base_stub_contents)
19128{
19129 int wback = (initial_insn & 0x00200000) >> 21;
19130 int ri, rn = (initial_insn & 0x000f0000) >> 16;
19131 int insn_all_registers = initial_insn & 0x0000ffff;
19132 int insn_low_registers, insn_high_registers;
19133 int usable_register_mask;
19134 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
19135 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 19136 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 19137 bfd_byte *current_stub_contents = base_stub_contents;
19138
19139 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
19140
19141 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19142 smaller than 8 registers load sequences that do not cause the
19143 hardware issue. */
19144 if (nb_registers <= 8)
19145 {
19146 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
19147 current_stub_contents =
19148 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19149 initial_insn);
19150
19151 /* B initial_insn_addr+4. */
19152 current_stub_contents =
19153 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19154 create_instruction_branch_absolute
82188b29 19155 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19156
19157 /* Fill the remaining of the stub with deterministic contents. */
19158 current_stub_contents =
19159 stm32l4xx_fill_stub_udf (htab, output_bfd,
19160 base_stub_contents, current_stub_contents,
19161 base_stub_contents +
19162 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19163
19164 return;
19165 }
19166
19167 /* - reg_list[13] == 0. */
19168 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
19169
19170 /* - reg_list[14] & reg_list[15] != 1. */
19171 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
19172
19173 /* - if (wback==1) reg_list[rn] == 0. */
19174 BFD_ASSERT (!wback || !restore_rn);
19175
19176 /* - nb_registers > 8. */
b25e998d 19177 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19178
19179 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19180
19181 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
19182 - One with the 7 lowest registers (register mask 0x007F)
19183 This LDM will finally contain between 2 and 7 registers
19184 - One with the 7 highest registers (register mask 0xDF80)
19185 This ldm will finally contain between 2 and 7 registers. */
19186 insn_low_registers = insn_all_registers & 0x007F;
19187 insn_high_registers = insn_all_registers & 0xDF80;
19188
19189 /* A spare register may be needed during this veneer to temporarily
19190 handle the base register. This register will be restored with
19191 the last LDM operation.
19192 The usable register may be any general purpose register (that excludes
19193 PC, SP, LR : register mask is 0x1FFF). */
19194 usable_register_mask = 0x1FFF;
19195
19196 /* Generate the stub function. */
19197 if (!wback && !restore_pc && !restore_rn)
19198 {
19199 /* Choose a Ri in the low-register-list that will be restored. */
19200 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19201
19202 /* MOV Ri, Rn. */
19203 current_stub_contents =
19204 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19205 create_instruction_mov (ri, rn));
19206
19207 /* LDMDB Ri!, {R-high-register-list}. */
19208 current_stub_contents =
19209 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19210 create_instruction_ldmdb
19211 (ri, /*wback=*/1, insn_high_registers));
19212
19213 /* LDMDB Ri, {R-low-register-list}. */
19214 current_stub_contents =
19215 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19216 create_instruction_ldmdb
19217 (ri, /*wback=*/0, insn_low_registers));
19218
19219 /* B initial_insn_addr+4. */
19220 current_stub_contents =
19221 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19222 create_instruction_branch_absolute
82188b29 19223 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19224 }
19225 else if (wback && !restore_pc && !restore_rn)
19226 {
19227 /* LDMDB Rn!, {R-high-register-list}. */
19228 current_stub_contents =
19229 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19230 create_instruction_ldmdb
19231 (rn, /*wback=*/1, insn_high_registers));
19232
19233 /* LDMDB Rn!, {R-low-register-list}. */
19234 current_stub_contents =
19235 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19236 create_instruction_ldmdb
19237 (rn, /*wback=*/1, insn_low_registers));
19238
19239 /* B initial_insn_addr+4. */
19240 current_stub_contents =
19241 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19242 create_instruction_branch_absolute
82188b29 19243 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19244 }
19245 else if (!wback && restore_pc && !restore_rn)
19246 {
19247 /* Choose a Ri in the high-register-list that will be restored. */
19248 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19249
19250 /* SUB Ri, Rn, #(4*nb_registers). */
19251 current_stub_contents =
19252 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19253 create_instruction_sub (ri, rn, (4 * nb_registers)));
19254
19255 /* LDMIA Ri!, {R-low-register-list}. */
19256 current_stub_contents =
19257 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19258 create_instruction_ldmia
19259 (ri, /*wback=*/1, insn_low_registers));
19260
19261 /* LDMIA Ri, {R-high-register-list}. */
19262 current_stub_contents =
19263 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19264 create_instruction_ldmia
19265 (ri, /*wback=*/0, insn_high_registers));
19266 }
19267 else if (wback && restore_pc && !restore_rn)
19268 {
19269 /* Choose a Ri in the high-register-list that will be restored. */
19270 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19271
19272 /* SUB Rn, Rn, #(4*nb_registers) */
19273 current_stub_contents =
19274 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19275 create_instruction_sub (rn, rn, (4 * nb_registers)));
19276
19277 /* MOV Ri, Rn. */
19278 current_stub_contents =
19279 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19280 create_instruction_mov (ri, rn));
19281
19282 /* LDMIA Ri!, {R-low-register-list}. */
19283 current_stub_contents =
19284 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19285 create_instruction_ldmia
19286 (ri, /*wback=*/1, insn_low_registers));
19287
19288 /* LDMIA Ri, {R-high-register-list}. */
19289 current_stub_contents =
19290 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19291 create_instruction_ldmia
19292 (ri, /*wback=*/0, insn_high_registers));
19293 }
19294 else if (!wback && !restore_pc && restore_rn)
19295 {
19296 ri = rn;
19297 if (!(insn_low_registers & (1 << rn)))
19298 {
19299 /* Choose a Ri in the low-register-list that will be restored. */
19300 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19301
19302 /* MOV Ri, Rn. */
19303 current_stub_contents =
19304 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19305 create_instruction_mov (ri, rn));
19306 }
19307
19308 /* LDMDB Ri!, {R-high-register-list}. */
19309 current_stub_contents =
19310 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19311 create_instruction_ldmdb
19312 (ri, /*wback=*/1, insn_high_registers));
19313
19314 /* LDMDB Ri, {R-low-register-list}. */
19315 current_stub_contents =
19316 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19317 create_instruction_ldmdb
19318 (ri, /*wback=*/0, insn_low_registers));
19319
19320 /* B initial_insn_addr+4. */
19321 current_stub_contents =
19322 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19323 create_instruction_branch_absolute
82188b29 19324 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19325 }
19326 else if (!wback && restore_pc && restore_rn)
19327 {
19328 ri = rn;
19329 if (!(insn_high_registers & (1 << rn)))
19330 {
19331 /* Choose a Ri in the high-register-list that will be restored. */
19332 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19333 }
19334
19335 /* SUB Ri, Rn, #(4*nb_registers). */
19336 current_stub_contents =
19337 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19338 create_instruction_sub (ri, rn, (4 * nb_registers)));
19339
19340 /* LDMIA Ri!, {R-low-register-list}. */
19341 current_stub_contents =
19342 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19343 create_instruction_ldmia
19344 (ri, /*wback=*/1, insn_low_registers));
19345
19346 /* LDMIA Ri, {R-high-register-list}. */
19347 current_stub_contents =
19348 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19349 create_instruction_ldmia
19350 (ri, /*wback=*/0, insn_high_registers));
19351 }
19352 else if (wback && restore_rn)
19353 {
19354 /* The assembler should not have accepted to encode this. */
19355 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
19356 "undefined behavior.\n");
19357 }
19358
19359 /* Fill the remaining of the stub with deterministic contents. */
19360 current_stub_contents =
19361 stm32l4xx_fill_stub_udf (htab, output_bfd,
19362 base_stub_contents, current_stub_contents,
19363 base_stub_contents +
19364 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19365
19366}
19367
19368static void
19369stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
19370 bfd * output_bfd,
19371 const insn32 initial_insn,
19372 const bfd_byte *const initial_insn_addr,
19373 bfd_byte *const base_stub_contents)
19374{
9239bbd3 19375 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 19376 bfd_byte *current_stub_contents = base_stub_contents;
19377
19378 BFD_ASSERT (is_thumb2_vldm (initial_insn));
19379
19380 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 19381 smaller than 8 words load sequences that do not cause the
a504d23a 19382 hardware issue. */
9239bbd3 19383 if (num_words <= 8)
a504d23a
LA		 19384 {
19385 /* Untouched instruction. */
19386 current_stub_contents =
19387 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19388 initial_insn);
19389
19390 /* B initial_insn_addr+4. */
19391 current_stub_contents =
19392 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19393 create_instruction_branch_absolute
82188b29 19394 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19395 }
19396 else
19397 {
9eaff861 19398 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 19399 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 19400 bfd_boolean is_ia_nobang = /* (IA without !). */
19401 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
19402 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
19403 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
19404 bfd_boolean is_db_bang = /* (DB with !). */
19405 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 19406 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 19407 /* d = UInt (Vd:D);. */
9239bbd3 19408 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 19409 | (((unsigned int)initial_insn << 9) >> 31);
19410
9239bbd3
CM		 19411 /* Compute the number of 8-words chunks needed to split. */
19412 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 19413 int chunk;
19414
19415 /* The test coverage has been done assuming the following
19416 hypothesis that exactly one of the previous is_ predicates is
19417 true. */
9239bbd3
CM		 19418 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
19419 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 19420
9239bbd3 19421 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 19422 cases, then we emit the adjustments:
19423
19424 vldm rx, {...}
19425 -> vldm rx!, {8_words_or_less} for each needed 8_word
19426 -> sub rx, rx, #size (list)
19427
19428 vldm rx!, {...}
19429 -> vldm rx!, {8_words_or_less} for each needed 8_word
19430 This also handles vpop instruction (when rx is sp)
19431
19432 vldmd rx!, {...}
19433 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 19434 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 19435 {
9239bbd3
CM		 19436 bfd_vma new_insn = 0;
19437
a504d23a
LA		 19438 if (is_ia_nobang || is_ia_bang)
19439 {
9239bbd3
CM		 19440 new_insn = create_instruction_vldmia
19441 (base_reg,
19442 is_dp,
19443 /*wback= . */1,
19444 chunks - (chunk + 1) ?
19445 8 : num_words - chunk * 8,
19446 first_reg + chunk * 8);
a504d23a
LA		 19447 }
19448 else if (is_db_bang)
19449 {
9239bbd3
CM		 19450 new_insn = create_instruction_vldmdb
19451 (base_reg,
19452 is_dp,
19453 chunks - (chunk + 1) ?
19454 8 : num_words - chunk * 8,
19455 first_reg + chunk * 8);
a504d23a 19456 }
9239bbd3
CM		 19457
19458 if (new_insn)
19459 current_stub_contents =
19460 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19461 new_insn);
a504d23a
LA		 19462 }
19463
19464 /* Only this case requires the base register compensation
19465 subtract. */
19466 if (is_ia_nobang)
19467 {
19468 current_stub_contents =
19469 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19470 create_instruction_sub
9239bbd3 19471 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 19472 }
19473
19474 /* B initial_insn_addr+4. */
19475 current_stub_contents =
19476 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19477 create_instruction_branch_absolute
82188b29 19478 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19479 }
19480
19481 /* Fill the remaining of the stub with deterministic contents. */
19482 current_stub_contents =
19483 stm32l4xx_fill_stub_udf (htab, output_bfd,
19484 base_stub_contents, current_stub_contents,
19485 base_stub_contents +
19486 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19487}
19488
19489static void
19490stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
19491 bfd * output_bfd,
19492 const insn32 wrong_insn,
19493 const bfd_byte *const wrong_insn_addr,
19494 bfd_byte *const stub_contents)
19495{
19496 if (is_thumb2_ldmia (wrong_insn))
19497 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
19498 wrong_insn, wrong_insn_addr,
19499 stub_contents);
19500 else if (is_thumb2_ldmdb (wrong_insn))
19501 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
19502 wrong_insn, wrong_insn_addr,
19503 stub_contents);
19504 else if (is_thumb2_vldm (wrong_insn))
19505 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
19506 wrong_insn, wrong_insn_addr,
19507 stub_contents);
19508}
19509
19510/* End of stm32l4xx work-around. */
19511
19512
e489d0ae
PB		 19513/* Do code byteswapping. Return FALSE afterwards so that the section is
19514 written out as normal. */
19515
19516static bfd_boolean
c7b8f16e 19517elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 19518 struct bfd_link_info *link_info,
19519 asection *sec,
e489d0ae
PB		 19520 bfd_byte *contents)
19521{
48229727 19522 unsigned int mapcount, errcount;
8e3de13a 19523 _arm_elf_section_data *arm_data;
c7b8f16e 19524 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 19525 elf32_arm_section_map *map;
c7b8f16e 19526 elf32_vfp11_erratum_list *errnode;
a504d23a 19527 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 19528 bfd_vma ptr;
19529 bfd_vma end;
c7b8f16e 19530 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 19531 bfd_byte tmp;
48229727 19532 unsigned int i;
57e8b36a 19533
4dfe6ac6
NC		 19534 if (globals == NULL)
19535 return FALSE;
19536
8e3de13a
NC		 19537 /* If this section has not been allocated an _arm_elf_section_data
19538 structure then we cannot record anything. */
19539 arm_data = get_arm_elf_section_data (sec);
19540 if (arm_data == NULL)
19541 return FALSE;
19542
19543 mapcount = arm_data->mapcount;
19544 map = arm_data->map;
c7b8f16e
JB		 19545 errcount = arm_data->erratumcount;
19546
19547 if (errcount != 0)
19548 {
19549 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
19550
19551 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 19552 errnode = errnode->next)
19553 {
19554 bfd_vma target = errnode->vma - offset;
19555
19556 switch (errnode->type)
19557 {
19558 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
19559 {
19560 bfd_vma branch_to_veneer;
19561 /* Original condition code of instruction, plus bit mask for
19562 ARM B instruction. */
19563 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
19564 | 0x0a000000;
c7b8f16e
JB		 19565
19566 /* The instruction is before the label. */
91d6fa6a 19567 target -= 4;
c7b8f16e
JB		 19568
19569 /* Above offset included in -4 below. */
19570 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 19571 - errnode->vma - 4;
c7b8f16e
JB		 19572
19573 if ((signed) branch_to_veneer < -(1 << 25)
19574 || (signed) branch_to_veneer >= (1 << 25))
871b3ab2 19575 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19576 "range"), output_bfd);
c7b8f16e 19577
99059e56
RM		 19578 insn |= (branch_to_veneer >> 2) & 0xffffff;
19579 contents[endianflip ^ target] = insn & 0xff;
19580 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19581 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19582 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19583 }
19584 break;
c7b8f16e
JB		 19585
19586 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 19587 {
19588 bfd_vma branch_from_veneer;
19589 unsigned int insn;
c7b8f16e 19590
99059e56
RM		 19591 /* Take size of veneer into account. */
19592 branch_from_veneer = errnode->u.v.branch->vma
19593 - errnode->vma - 12;
c7b8f16e
JB		 19594
19595 if ((signed) branch_from_veneer < -(1 << 25)
19596 || (signed) branch_from_veneer >= (1 << 25))
871b3ab2 19597 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19598 "range"), output_bfd);
c7b8f16e 19599
99059e56
RM		 19600 /* Original instruction. */
19601 insn = errnode->u.v.branch->u.b.vfp_insn;
19602 contents[endianflip ^ target] = insn & 0xff;
19603 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19604 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19605 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19606
19607 /* Branch back to insn after original insn. */
19608 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
19609 contents[endianflip ^ (target + 4)] = insn & 0xff;
19610 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
19611 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
19612 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
19613 }
19614 break;
c7b8f16e 19615
99059e56
RM		 19616 default:
19617 abort ();
19618 }
19619 }
c7b8f16e 19620 }
e489d0ae 19621
a504d23a
LA		 19622 if (arm_data->stm32l4xx_erratumcount != 0)
19623 {
19624 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
19625 stm32l4xx_errnode != 0;
19626 stm32l4xx_errnode = stm32l4xx_errnode->next)
19627 {
19628 bfd_vma target = stm32l4xx_errnode->vma - offset;
19629
19630 switch (stm32l4xx_errnode->type)
19631 {
19632 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
19633 {
19634 unsigned int insn;
19635 bfd_vma branch_to_veneer =
19636 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
19637
19638 if ((signed) branch_to_veneer < -(1 << 24)
19639 || (signed) branch_to_veneer >= (1 << 24))
19640 {
19641 bfd_vma out_of_range =
19642 ((signed) branch_to_veneer < -(1 << 24)) ?
19643 - branch_to_veneer - (1 << 24) :
19644 ((signed) branch_to_veneer >= (1 << 24)) ?
19645 branch_to_veneer - (1 << 24) : 0;
19646
4eca0228 19647 _bfd_error_handler
2dcf00ce 19648 (_("%pB(%#" PRIx64 "): error: "
90b6238f
AM		 19649 "cannot create STM32L4XX veneer; "
19650 "jump out of range by %" PRId64 " bytes; "
19651 "cannot encode branch instruction"),
a504d23a 19652 output_bfd,
2dcf00ce
AM		 19653 (uint64_t) (stm32l4xx_errnode->vma - 4),
19654 (int64_t) out_of_range);
a504d23a
LA		 19655 continue;
19656 }
19657
19658 insn = create_instruction_branch_absolute
82188b29 19659 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 19660
19661 /* The instruction is before the label. */
19662 target -= 4;
19663
19664 put_thumb2_insn (globals, output_bfd,
19665 (bfd_vma) insn, contents + target);
19666 }
19667 break;
19668
19669 case STM32L4XX_ERRATUM_VENEER:
19670 {
82188b29
NC		 19671 bfd_byte * veneer;
19672 bfd_byte * veneer_r;
a504d23a
LA		 19673 unsigned int insn;
19674
82188b29
NC		 19675 veneer = contents + target;
19676 veneer_r = veneer
19677 + stm32l4xx_errnode->u.b.veneer->vma
19678 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 19679
19680 if ((signed) (veneer_r - veneer -
19681 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19682 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19683 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19684 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
19685 || (signed) (veneer_r - veneer) >= (1 << 24))
19686 {
90b6238f
AM		 19687 _bfd_error_handler (_("%pB: error: cannot create STM32L4XX "
19688 "veneer"), output_bfd);
a504d23a
LA		 19689 continue;
19690 }
19691
19692 /* Original instruction. */
19693 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
19694
19695 stm32l4xx_create_replacing_stub
19696 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
19697 }
19698 break;
19699
19700 default:
19701 abort ();
19702 }
19703 }
19704 }
19705
2468f9c9
PB		 19706 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
19707 {
19708 arm_unwind_table_edit *edit_node
99059e56 19709 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 19710 /* Now, sec->size is the size of the section we will write. The original
99059e56 19711 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 19712 markers) was sec->rawsize. (This isn't the case if we perform no
19713 edits, then rawsize will be zero and we should use size). */
21d799b5 19714 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 19715 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
19716 unsigned int in_index, out_index;
19717 bfd_vma add_to_offsets = 0;
19718
19719 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 19720 {
2468f9c9
PB		 19721 if (edit_node)
19722 {
19723 unsigned int edit_index = edit_node->index;
b38cadfb 19724
2468f9c9 19725 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 19726 {
2468f9c9
PB		 19727 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19728 contents + in_index * 8, add_to_offsets);
19729 out_index++;
19730 in_index++;
19731 }
19732 else if (in_index == edit_index
19733 || (in_index * 8 >= input_size
19734 && edit_index == UINT_MAX))
99059e56 19735 {
2468f9c9
PB		 19736 switch (edit_node->type)
19737 {
19738 case DELETE_EXIDX_ENTRY:
19739 in_index++;
19740 add_to_offsets += 8;
19741 break;
b38cadfb 19742
2468f9c9
PB		 19743 case INSERT_EXIDX_CANTUNWIND_AT_END:
19744 {
99059e56 19745 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 19746 bfd_vma text_offset = text_sec->output_section->vma
19747 + text_sec->output_offset
19748 + text_sec->size;
19749 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 19750 unsigned long prel31_offset;
2468f9c9
PB		 19751
19752 /* Note: this is meant to be equivalent to an
19753 R_ARM_PREL31 relocation. These synthetic
19754 EXIDX_CANTUNWIND markers are not relocated by the
19755 usual BFD method. */
19756 prel31_offset = (text_offset - exidx_offset)
19757 & 0x7ffffffful;
491d01d3
YU		 19758 if (bfd_link_relocatable (link_info))
19759 {
19760 /* Here relocation for new EXIDX_CANTUNWIND is
19761 created, so there is no need to
19762 adjust offset by hand. */
19763 prel31_offset = text_sec->output_offset
19764 + text_sec->size;
491d01d3 19765 }
2468f9c9
PB		 19766
19767 /* First address we can't unwind. */
19768 bfd_put_32 (output_bfd, prel31_offset,
19769 &edited_contents[out_index * 8]);
19770
19771 /* Code for EXIDX_CANTUNWIND. */
19772 bfd_put_32 (output_bfd, 0x1,
19773 &edited_contents[out_index * 8 + 4]);
19774
19775 out_index++;
19776 add_to_offsets -= 8;
19777 }
19778 break;
19779 }
b38cadfb 19780
2468f9c9
PB		 19781 edit_node = edit_node->next;
19782 }
19783 }
19784 else
19785 {
19786 /* No more edits, copy remaining entries verbatim. */
19787 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19788 contents + in_index * 8, add_to_offsets);
19789 out_index++;
19790 in_index++;
19791 }
19792 }
19793
19794 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
19795 bfd_set_section_contents (output_bfd, sec->output_section,
19796 edited_contents,
19797 (file_ptr) sec->output_offset, sec->size);
19798
19799 return TRUE;
19800 }
19801
48229727
JB		 19802 /* Fix code to point to Cortex-A8 erratum stubs. */
19803 if (globals->fix_cortex_a8)
19804 {
19805 struct a8_branch_to_stub_data data;
19806
19807 data.writing_section = sec;
19808 data.contents = contents;
19809
a504d23a
LA		 19810 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
19811 & data);
48229727
JB		 19812 }
19813
e489d0ae
PB		 19814 if (mapcount == 0)
19815 return FALSE;
19816
c7b8f16e 19817 if (globals->byteswap_code)
e489d0ae 19818 {
c7b8f16e 19819 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 19820
c7b8f16e
JB		 19821 ptr = map[0].vma;
19822 for (i = 0; i < mapcount; i++)
99059e56
RM		 19823 {
19824 if (i == mapcount - 1)
c7b8f16e 19825 end = sec->size;
99059e56
RM		 19826 else
19827 end = map[i + 1].vma;
e489d0ae 19828
99059e56 19829 switch (map[i].type)
e489d0ae 19830 {
c7b8f16e
JB		 19831 case 'a':
19832 /* Byte swap code words. */
19833 while (ptr + 3 < end)
99059e56
RM		 19834 {
19835 tmp = contents[ptr];
19836 contents[ptr] = contents[ptr + 3];
19837 contents[ptr + 3] = tmp;
19838 tmp = contents[ptr + 1];
19839 contents[ptr + 1] = contents[ptr + 2];
19840 contents[ptr + 2] = tmp;
19841 ptr += 4;
19842 }
c7b8f16e 19843 break;
e489d0ae 19844
c7b8f16e
JB		 19845 case 't':
19846 /* Byte swap code halfwords. */
19847 while (ptr + 1 < end)
99059e56
RM		 19848 {
19849 tmp = contents[ptr];
19850 contents[ptr] = contents[ptr + 1];
19851 contents[ptr + 1] = tmp;
19852 ptr += 2;
19853 }
c7b8f16e
JB		 19854 break;
19855
19856 case 'd':
19857 /* Leave data alone. */
19858 break;
19859 }
99059e56
RM		 19860 ptr = end;
19861 }
e489d0ae 19862 }
8e3de13a 19863
93204d3a 19864 free (map);
47b2e99c 19865 arm_data->mapcount = -1;
c7b8f16e 19866 arm_data->mapsize = 0;
8e3de13a 19867 arm_data->map = NULL;
8e3de13a 19868
e489d0ae
PB		 19869 return FALSE;
19870}
19871
0beaef2b
PB		 19872/* Mangle thumb function symbols as we read them in. */
19873
8384fb8f 19874static bfd_boolean
0beaef2b
PB		 19875elf32_arm_swap_symbol_in (bfd * abfd,
19876 const void *psrc,
19877 const void *pshn,
19878 Elf_Internal_Sym *dst)
19879{
4ba2ef8f
TP		 19880 Elf_Internal_Shdr *symtab_hdr;
19881 const char *name = NULL;
19882
8384fb8f
AM		 19883 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
19884 return FALSE;
39d911fc 19885 dst->st_target_internal = 0;
0beaef2b
PB		 19886
19887 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 19888 the address. */
63e1a0fc
PB		 19889 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
19890 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 19891 {
63e1a0fc
PB		 19892 if (dst->st_value & 1)
19893 {
19894 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 19895 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
19896 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 19897 }
19898 else
39d911fc 19899 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 19900 }
19901 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
19902 {
19903 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 19904 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 19905 }
35fc36a8 19906 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 19907 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 19908 else
39d911fc 19909 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 19910
4ba2ef8f
TP		 19911 /* Mark CMSE special symbols. */
19912 symtab_hdr = & elf_symtab_hdr (abfd);
19913 if (symtab_hdr->sh_size)
19914 name = bfd_elf_sym_name (abfd, symtab_hdr, dst, NULL);
19915 if (name && CONST_STRNEQ (name, CMSE_PREFIX))
19916 ARM_SET_SYM_CMSE_SPCL (dst->st_target_internal);
19917
8384fb8f 19918 return TRUE;
0beaef2b
PB		 19919}
19920
19921
19922/* Mangle thumb function symbols as we write them out. */
19923
19924static void
19925elf32_arm_swap_symbol_out (bfd *abfd,
19926 const Elf_Internal_Sym *src,
19927 void *cdst,
19928 void *shndx)
19929{
19930 Elf_Internal_Sym newsym;
19931
19932 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19933 of the address set, as per the new EABI. We do this unconditionally
19934 because objcopy does not set the elf header flags until after
19935 it writes out the symbol table. */
39d911fc 19936 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 19937 {
19938 newsym = *src;
34e77a92
RS		 19939 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
19940 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 19941 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 19942 {
19943 /* Do this only for defined symbols. At link type, the static
19944 linker will simulate the work of dynamic linker of resolving
19945 symbols and will carry over the thumbness of found symbols to
19946 the output symbol table. It's not clear how it happens, but
19947 the thumbness of undefined symbols can well be different at
19948 runtime, and writing '1' for them will be confusing for users
19949 and possibly for dynamic linker itself.
19950 */
19951 newsym.st_value |= 1;
19952 }
906e58ca 19953
0beaef2b
PB		 19954 src = &newsym;
19955 }
19956 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
19957}
19958
b294bdf8
MM		 19959/* Add the PT_ARM_EXIDX program header. */
19960
19961static bfd_boolean
906e58ca 19962elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 19963 struct bfd_link_info *info ATTRIBUTE_UNUSED)
19964{
19965 struct elf_segment_map *m;
19966 asection *sec;
19967
19968 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19969 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19970 {
19971 /* If there is already a PT_ARM_EXIDX header, then we do not
19972 want to add another one. This situation arises when running
19973 "strip"; the input binary already has the header. */
12bd6957 19974 m = elf_seg_map (abfd);
b294bdf8
MM		 19975 while (m && m->p_type != PT_ARM_EXIDX)
19976 m = m->next;
19977 if (!m)
19978 {
21d799b5 19979 m = (struct elf_segment_map *)
99059e56 19980 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 19981 if (m == NULL)
19982 return FALSE;
19983 m->p_type = PT_ARM_EXIDX;
19984 m->count = 1;
19985 m->sections[0] = sec;
19986
12bd6957
AM		 19987 m->next = elf_seg_map (abfd);
19988 elf_seg_map (abfd) = m;
b294bdf8
MM		 19989 }
19990 }
19991
19992 return TRUE;
19993}
19994
19995/* We may add a PT_ARM_EXIDX program header. */
19996
19997static int
a6b96beb
AM		 19998elf32_arm_additional_program_headers (bfd *abfd,
19999 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 20000{
20001 asection *sec;
20002
20003 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
20004 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
20005 return 1;
20006 else
20007 return 0;
20008}
20009
34e77a92
RS		 20010/* Hook called by the linker routine which adds symbols from an object
20011 file. */
20012
20013static bfd_boolean
20014elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
20015 Elf_Internal_Sym *sym, const char **namep,
20016 flagword *flagsp, asection **secp, bfd_vma *valp)
20017{
c792917c
NC		 20018 if (elf32_arm_hash_table (info) == NULL)
20019 return FALSE;
20020
34e77a92
RS		 20021 if (elf32_arm_hash_table (info)->vxworks_p
20022 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
20023 flagsp, secp, valp))
20024 return FALSE;
20025
20026 return TRUE;
20027}
20028
0beaef2b 20029/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 20030const struct elf_size_info elf32_arm_size_info =
20031{
0beaef2b
PB		 20032 sizeof (Elf32_External_Ehdr),
20033 sizeof (Elf32_External_Phdr),
20034 sizeof (Elf32_External_Shdr),
20035 sizeof (Elf32_External_Rel),
20036 sizeof (Elf32_External_Rela),
20037 sizeof (Elf32_External_Sym),
20038 sizeof (Elf32_External_Dyn),
20039 sizeof (Elf_External_Note),
20040 4,
20041 1,
20042 32, 2,
20043 ELFCLASS32, EV_CURRENT,
20044 bfd_elf32_write_out_phdrs,
20045 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 20046 bfd_elf32_checksum_contents,
0beaef2b
PB		 20047 bfd_elf32_write_relocs,
20048 elf32_arm_swap_symbol_in,
20049 elf32_arm_swap_symbol_out,
20050 bfd_elf32_slurp_reloc_table,
20051 bfd_elf32_slurp_symbol_table,
20052 bfd_elf32_swap_dyn_in,
20053 bfd_elf32_swap_dyn_out,
20054 bfd_elf32_swap_reloc_in,
20055 bfd_elf32_swap_reloc_out,
20056 bfd_elf32_swap_reloca_in,
20057 bfd_elf32_swap_reloca_out
20058};
20059
685e70ae
VK		 20060static bfd_vma
20061read_code32 (const bfd *abfd, const bfd_byte *addr)
20062{
20063 /* V7 BE8 code is always little endian. */
20064 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
20065 return bfd_getl32 (addr);
20066
20067 return bfd_get_32 (abfd, addr);
20068}
20069
20070static bfd_vma
20071read_code16 (const bfd *abfd, const bfd_byte *addr)
20072{
20073 /* V7 BE8 code is always little endian. */
20074 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
20075 return bfd_getl16 (addr);
20076
20077 return bfd_get_16 (abfd, addr);
20078}
20079
6a631e86
YG		 20080/* Return size of plt0 entry starting at ADDR
20081 or (bfd_vma) -1 if size can not be determined. */
20082
20083static bfd_vma
20084elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
20085{
20086 bfd_vma first_word;
20087 bfd_vma plt0_size;
20088
685e70ae 20089 first_word = read_code32 (abfd, addr);
6a631e86
YG		 20090
20091 if (first_word == elf32_arm_plt0_entry[0])
20092 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
20093 else if (first_word == elf32_thumb2_plt0_entry[0])
20094 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
20095 else
20096 /* We don't yet handle this PLT format. */
20097 return (bfd_vma) -1;
20098
20099 return plt0_size;
20100}
20101
20102/* Return size of plt entry starting at offset OFFSET
20103 of plt section located at address START
20104 or (bfd_vma) -1 if size can not be determined. */
20105
20106static bfd_vma
20107elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
20108{
20109 bfd_vma first_insn;
20110 bfd_vma plt_size = 0;
20111 const bfd_byte *addr = start + offset;
20112
20113 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 20114 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 20115 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
20116
20117 /* Respect Thumb stub if necessary. */
685e70ae 20118 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 20119 {
20120 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
20121 }
20122
20123 /* Strip immediate from first add. */
685e70ae 20124 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 20125
20126#ifdef FOUR_WORD_PLT
20127 if (first_insn == elf32_arm_plt_entry[0])
20128 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
20129#else
20130 if (first_insn == elf32_arm_plt_entry_long[0])
20131 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
20132 else if (first_insn == elf32_arm_plt_entry_short[0])
20133 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
20134#endif
20135 else
20136 /* We don't yet handle this PLT format. */
20137 return (bfd_vma) -1;
20138
20139 return plt_size;
20140}
20141
20142/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
20143
20144static long
20145elf32_arm_get_synthetic_symtab (bfd *abfd,
20146 long symcount ATTRIBUTE_UNUSED,
20147 asymbol **syms ATTRIBUTE_UNUSED,
20148 long dynsymcount,
20149 asymbol **dynsyms,
20150 asymbol **ret)
20151{
20152 asection *relplt;
20153 asymbol *s;
20154 arelent *p;
20155 long count, i, n;
20156 size_t size;
20157 Elf_Internal_Shdr *hdr;
20158 char *names;
20159 asection *plt;
20160 bfd_vma offset;
20161 bfd_byte *data;
20162
20163 *ret = NULL;
20164
20165 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
20166 return 0;
20167
20168 if (dynsymcount <= 0)
20169 return 0;
20170
20171 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
20172 if (relplt == NULL)
20173 return 0;
20174
20175 hdr = &elf_section_data (relplt)->this_hdr;
20176 if (hdr->sh_link != elf_dynsymtab (abfd)
20177 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
20178 return 0;
20179
20180 plt = bfd_get_section_by_name (abfd, ".plt");
20181 if (plt == NULL)
20182 return 0;
20183
20184 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
20185 return -1;
20186
20187 data = plt->contents;
20188 if (data == NULL)
20189 {
20190 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
20191 return -1;
20192 bfd_cache_section_contents((asection *) plt, data);
20193 }
20194
20195 count = relplt->size / hdr->sh_entsize;
20196 size = count * sizeof (asymbol);
20197 p = relplt->relocation;
20198 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20199 {
20200 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
20201 if (p->addend != 0)
20202 size += sizeof ("+0x") - 1 + 8;
20203 }
20204
20205 s = *ret = (asymbol *) bfd_malloc (size);
20206 if (s == NULL)
20207 return -1;
20208
20209 offset = elf32_arm_plt0_size (abfd, data);
20210 if (offset == (bfd_vma) -1)
20211 return -1;
20212
20213 names = (char *) (s + count);
20214 p = relplt->relocation;
20215 n = 0;
20216 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20217 {
20218 size_t len;
20219
20220 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
20221 if (plt_size == (bfd_vma) -1)
20222 break;
20223
20224 *s = **p->sym_ptr_ptr;
20225 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20226 we are defining a symbol, ensure one of them is set. */
20227 if ((s->flags & BSF_LOCAL) == 0)
20228 s->flags |= BSF_GLOBAL;
20229 s->flags |= BSF_SYNTHETIC;
20230 s->section = plt;
20231 s->value = offset;
20232 s->name = names;
20233 s->udata.p = NULL;
20234 len = strlen ((*p->sym_ptr_ptr)->name);
20235 memcpy (names, (*p->sym_ptr_ptr)->name, len);
20236 names += len;
20237 if (p->addend != 0)
20238 {
20239 char buf[30], *a;
20240
20241 memcpy (names, "+0x", sizeof ("+0x") - 1);
20242 names += sizeof ("+0x") - 1;
20243 bfd_sprintf_vma (abfd, buf, p->addend);
20244 for (a = buf; *a == '0'; ++a)
20245 ;
20246 len = strlen (a);
20247 memcpy (names, a, len);
20248 names += len;
20249 }
20250 memcpy (names, "@plt", sizeof ("@plt"));
20251 names += sizeof ("@plt");
20252 ++s, ++n;
20253 offset += plt_size;
20254 }
20255
20256 return n;
20257}
20258
ac4c9b04
MG		 20259static bfd_boolean
20260elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
20261{
f0728ee3
AV		 20262 if (hdr->sh_flags & SHF_ARM_PURECODE)
20263 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 20264 return TRUE;
20265}
20266
20267static flagword
20268elf32_arm_lookup_section_flags (char *flag_name)
20269{
f0728ee3
AV		 20270 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
20271 return SHF_ARM_PURECODE;
ac4c9b04
MG		 20272
20273 return SEC_NO_FLAGS;
20274}
20275
491d01d3
YU		 20276static unsigned int
20277elf32_arm_count_additional_relocs (asection *sec)
20278{
20279 struct _arm_elf_section_data *arm_data;
20280 arm_data = get_arm_elf_section_data (sec);
5025eb7c 20281
6342be70 20282 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 20283}
20284
5522f910 20285/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 20286 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 20287 FALSE otherwise. ISECTION is the best guess matching section from the
20288 input bfd IBFD, but it might be NULL. */
20289
20290static bfd_boolean
20291elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
20292 bfd *obfd ATTRIBUTE_UNUSED,
20293 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
20294 Elf_Internal_Shdr *osection)
20295{
20296 switch (osection->sh_type)
20297 {
20298 case SHT_ARM_EXIDX:
20299 {
20300 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
20301 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
20302 unsigned i = 0;
20303
20304 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
20305 osection->sh_info = 0;
20306
20307 /* The sh_link field must be set to the text section associated with
20308 this index section. Unfortunately the ARM EHABI does not specify
20309 exactly how to determine this association. Our caller does try
20310 to match up OSECTION with its corresponding input section however
20311 so that is a good first guess. */
20312 if (isection != NULL
20313 && osection->bfd_section != NULL
20314 && isection->bfd_section != NULL
20315 && isection->bfd_section->output_section != NULL
20316 && isection->bfd_section->output_section == osection->bfd_section
20317 && iheaders != NULL
20318 && isection->sh_link > 0
20319 && isection->sh_link < elf_numsections (ibfd)
20320 && iheaders[isection->sh_link]->bfd_section != NULL
20321 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
20322 )
20323 {
20324 for (i = elf_numsections (obfd); i-- > 0;)
20325 if (oheaders[i]->bfd_section
20326 == iheaders[isection->sh_link]->bfd_section->output_section)
20327 break;
20328 }
9eaff861 20329
5522f910
NC		 20330 if (i == 0)
20331 {
20332 /* Failing that we have to find a matching section ourselves. If
20333 we had the output section name available we could compare that
20334 with input section names. Unfortunately we don't. So instead
20335 we use a simple heuristic and look for the nearest executable
20336 section before this one. */
20337 for (i = elf_numsections (obfd); i-- > 0;)
20338 if (oheaders[i] == osection)
20339 break;
20340 if (i == 0)
20341 break;
20342
20343 while (i-- > 0)
20344 if (oheaders[i]->sh_type == SHT_PROGBITS
20345 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
20346 == (SHF_ALLOC | SHF_EXECINSTR))
20347 break;
20348 }
20349
20350 if (i)
20351 {
20352 osection->sh_link = i;
20353 /* If the text section was part of a group
20354 then the index section should be too. */
20355 if (oheaders[i]->sh_flags & SHF_GROUP)
20356 osection->sh_flags |= SHF_GROUP;
20357 return TRUE;
20358 }
20359 }
20360 break;
20361
20362 case SHT_ARM_PREEMPTMAP:
20363 osection->sh_flags = SHF_ALLOC;
20364 break;
20365
20366 case SHT_ARM_ATTRIBUTES:
20367 case SHT_ARM_DEBUGOVERLAY:
20368 case SHT_ARM_OVERLAYSECTION:
20369 default:
20370 break;
20371 }
20372
20373 return FALSE;
20374}
20375
d691934d
NC		 20376/* Returns TRUE if NAME is an ARM mapping symbol.
20377 Traditionally the symbols $a, $d and $t have been used.
20378 The ARM ELF standard also defines $x (for A64 code). It also allows a
20379 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20380 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20381 not support them here. $t.x indicates the start of ThumbEE instructions. */
20382
20383static bfd_boolean
20384is_arm_mapping_symbol (const char * name)
20385{
20386 return name != NULL /* Paranoia. */
20387 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
20388 the mapping symbols could have acquired a prefix.
20389 We do not support this here, since such symbols no
20390 longer conform to the ARM ELF ABI. */
20391 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
20392 && (name[2] == 0 || name[2] == '.');
20393 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20394 any characters that follow the period are legal characters for the body
20395 of a symbol's name. For now we just assume that this is the case. */
20396}
20397
fca2a38f
NC		 20398/* Make sure that mapping symbols in object files are not removed via the
20399 "strip --strip-unneeded" tool. These symbols are needed in order to
20400 correctly generate interworking veneers, and for byte swapping code
20401 regions. Once an object file has been linked, it is safe to remove the
20402 symbols as they will no longer be needed. */
20403
20404static void
20405elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
20406{
20407 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 20408 && sym->section != bfd_abs_section_ptr
d691934d 20409 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 20410 sym->flags |= BSF_KEEP;
20411}
20412
5522f910
NC		 20413#undef elf_backend_copy_special_section_fields
20414#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20415
252b5132 20416#define ELF_ARCH bfd_arch_arm
ae95ffa6 20417#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 20418#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 20419#ifdef __QNXTARGET__
20420#define ELF_MAXPAGESIZE 0x1000
20421#else
7572ca89 20422#define ELF_MAXPAGESIZE 0x10000
d0facd1b 20423#endif
b1342370 20424#define ELF_MINPAGESIZE 0x1000
24718e3b 20425#define ELF_COMMONPAGESIZE 0x1000
252b5132 20426
07d6d2b8 20427#define bfd_elf32_mkobject elf32_arm_mkobject
ba93b8ac 20428
99e4ae17
AJ		 20429#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20430#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 20431#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20432#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
07d6d2b8 20433#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 20434#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 20435#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
07d6d2b8
AM		 20436#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
20437#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 20438#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 20439#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 20440#define bfd_elf32_bfd_final_link elf32_arm_final_link
07d6d2b8 20441#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132 20442
07d6d2b8
AM		 20443#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
20444#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 20445#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
07d6d2b8 20446#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 20447#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 20448#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 20449#define elf_backend_write_section elf32_arm_write_section
252b5132 20450#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
07d6d2b8 20451#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 20452#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20453#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20454#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 20455#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 20456#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 20457#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 20458#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 20459#define elf_backend_object_p elf32_arm_object_p
07d6d2b8
AM		 20460#define elf_backend_fake_sections elf32_arm_fake_sections
20461#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20462#define elf_backend_final_write_processing elf32_arm_final_write_processing
20463#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 20464#define elf_backend_size_info elf32_arm_size_info
b294bdf8 20465#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
07d6d2b8
AM		 20466#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20467#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 20468#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
07d6d2b8 20469#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 20470#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 20471#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 20472#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 20473
20474#define elf_backend_can_refcount 1
20475#define elf_backend_can_gc_sections 1
20476#define elf_backend_plt_readonly 1
20477#define elf_backend_want_got_plt 1
20478#define elf_backend_want_plt_sym 0
5474d94f 20479#define elf_backend_want_dynrelro 1
906e58ca
NC		 20480#define elf_backend_may_use_rel_p 1
20481#define elf_backend_may_use_rela_p 0
4e7fd91e 20482#define elf_backend_default_use_rela_p 0
64f52338 20483#define elf_backend_dtrel_excludes_plt 1
252b5132 20484
04f7c78d 20485#define elf_backend_got_header_size 12
b68a20d6 20486#define elf_backend_extern_protected_data 1
04f7c78d 20487
07d6d2b8 20488#undef elf_backend_obj_attrs_vendor
906e58ca 20489#define elf_backend_obj_attrs_vendor "aeabi"
07d6d2b8 20490#undef elf_backend_obj_attrs_section
906e58ca 20491#define elf_backend_obj_attrs_section ".ARM.attributes"
07d6d2b8 20492#undef elf_backend_obj_attrs_arg_type
906e58ca 20493#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
07d6d2b8 20494#undef elf_backend_obj_attrs_section_type
104d59d1 20495#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb 20496#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
07d6d2b8 20497#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 20498
07d6d2b8 20499#undef elf_backend_section_flags
ac4c9b04 20500#define elf_backend_section_flags elf32_arm_section_flags
07d6d2b8
AM		 20501#undef elf_backend_lookup_section_flags_hook
20502#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
ac4c9b04 20503
a2f63b2e
MR		 20504#define elf_backend_linux_prpsinfo32_ugid16 TRUE
20505
252b5132 20506#include "elf32-target.h"
7f266840 20507
b38cadfb
NC		 20508/* Native Client targets. */
20509
20510#undef TARGET_LITTLE_SYM
6d00b590 20511#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 20512#undef TARGET_LITTLE_NAME
20513#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
20514#undef TARGET_BIG_SYM
6d00b590 20515#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 20516#undef TARGET_BIG_NAME
20517#define TARGET_BIG_NAME "elf32-bigarm-nacl"
20518
20519/* Like elf32_arm_link_hash_table_create -- but overrides
20520 appropriately for NaCl. */
20521
20522static struct bfd_link_hash_table *
20523elf32_arm_nacl_link_hash_table_create (bfd *abfd)
20524{
20525 struct bfd_link_hash_table *ret;
20526
20527 ret = elf32_arm_link_hash_table_create (abfd);
20528 if (ret)
20529 {
20530 struct elf32_arm_link_hash_table *htab
20531 = (struct elf32_arm_link_hash_table *) ret;
20532
20533 htab->nacl_p = 1;
20534
20535 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
20536 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
20537 }
20538 return ret;
20539}
20540
20541/* Since NaCl doesn't use the ARM-specific unwind format, we don't
20542 really need to use elf32_arm_modify_segment_map. But we do it
20543 anyway just to reduce gratuitous differences with the stock ARM backend. */
20544
20545static bfd_boolean
20546elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
20547{
20548 return (elf32_arm_modify_segment_map (abfd, info)
20549 && nacl_modify_segment_map (abfd, info));
20550}
20551
887badb3
RM		 20552static void
20553elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
20554{
20555 elf32_arm_final_write_processing (abfd, linker);
20556 nacl_final_write_processing (abfd, linker);
20557}
20558
6a631e86
YG		 20559static bfd_vma
20560elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
20561 const arelent *rel ATTRIBUTE_UNUSED)
20562{
20563 return plt->vma
20564 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
20565 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
20566}
887badb3 20567
b38cadfb 20568#undef elf32_bed
6a631e86 20569#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 20570#undef bfd_elf32_bfd_link_hash_table_create
20571#define bfd_elf32_bfd_link_hash_table_create \
20572 elf32_arm_nacl_link_hash_table_create
20573#undef elf_backend_plt_alignment
6a631e86 20574#define elf_backend_plt_alignment 4
b38cadfb
NC		 20575#undef elf_backend_modify_segment_map
20576#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
20577#undef elf_backend_modify_program_headers
20578#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 20579#undef elf_backend_final_write_processing
20580#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 20581#undef bfd_elf32_get_synthetic_symtab
20582#undef elf_backend_plt_sym_val
20583#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 20584#undef elf_backend_copy_special_section_fields
b38cadfb 20585
887badb3
RM		 20586#undef ELF_MINPAGESIZE
20587#undef ELF_COMMONPAGESIZE
20588
b38cadfb
NC		 20589
20590#include "elf32-target.h"
20591
20592/* Reset to defaults. */
20593#undef elf_backend_plt_alignment
20594#undef elf_backend_modify_segment_map
20595#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20596#undef elf_backend_modify_program_headers
887badb3
RM		 20597#undef elf_backend_final_write_processing
20598#define elf_backend_final_write_processing elf32_arm_final_write_processing
20599#undef ELF_MINPAGESIZE
20600#define ELF_MINPAGESIZE 0x1000
20601#undef ELF_COMMONPAGESIZE
20602#define ELF_COMMONPAGESIZE 0x1000
20603
b38cadfb 20604
617a5ada
CL		 20605/* FDPIC Targets. */
20606
20607#undef TARGET_LITTLE_SYM
20608#define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20609#undef TARGET_LITTLE_NAME
20610#define TARGET_LITTLE_NAME "elf32-littlearm-fdpic"
20611#undef TARGET_BIG_SYM
20612#define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20613#undef TARGET_BIG_NAME
20614#define TARGET_BIG_NAME "elf32-bigarm-fdpic"
20615#undef elf_match_priority
20616#define elf_match_priority 128
18a20338
CL		 20617#undef ELF_OSABI
20618#define ELF_OSABI ELFOSABI_ARM_FDPIC
617a5ada
CL		 20619
20620/* Like elf32_arm_link_hash_table_create -- but overrides
20621 appropriately for FDPIC. */
20622
20623static struct bfd_link_hash_table *
20624elf32_arm_fdpic_link_hash_table_create (bfd *abfd)
20625{
20626 struct bfd_link_hash_table *ret;
20627
20628 ret = elf32_arm_link_hash_table_create (abfd);
20629 if (ret)
20630 {
20631 struct elf32_arm_link_hash_table *htab = (struct elf32_arm_link_hash_table *) ret;
20632
20633 htab->fdpic_p = 1;
20634 }
20635 return ret;
20636}
20637
e8b09b87
CL		 20638/* We need dynamic symbols for every section, since segments can
20639 relocate independently. */
20640static bfd_boolean
20641elf32_arm_fdpic_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
20642 struct bfd_link_info *info
20643 ATTRIBUTE_UNUSED,
20644 asection *p ATTRIBUTE_UNUSED)
20645{
20646 switch (elf_section_data (p)->this_hdr.sh_type)
20647 {
20648 case SHT_PROGBITS:
20649 case SHT_NOBITS:
20650 /* If sh_type is yet undecided, assume it could be
20651 SHT_PROGBITS/SHT_NOBITS. */
20652 case SHT_NULL:
20653 return FALSE;
20654
20655 /* There shouldn't be section relative relocations
20656 against any other section. */
20657 default:
20658 return TRUE;
20659 }
20660}
20661
617a5ada
CL		 20662#undef elf32_bed
20663#define elf32_bed elf32_arm_fdpic_bed
20664
20665#undef bfd_elf32_bfd_link_hash_table_create
4b24dd1a 20666#define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
617a5ada 20667
e8b09b87
CL		 20668#undef elf_backend_omit_section_dynsym
20669#define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20670
617a5ada 20671#include "elf32-target.h"
e8b09b87 20672
617a5ada 20673#undef elf_match_priority
18a20338 20674#undef ELF_OSABI
e8b09b87 20675#undef elf_backend_omit_section_dynsym
617a5ada 20676
906e58ca 20677/* VxWorks Targets. */
4e7fd91e 20678
07d6d2b8
AM		 20679#undef TARGET_LITTLE_SYM
20680#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20681#undef TARGET_LITTLE_NAME
20682#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
20683#undef TARGET_BIG_SYM
20684#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20685#undef TARGET_BIG_NAME
20686#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
4e7fd91e
PB		 20687
20688/* Like elf32_arm_link_hash_table_create -- but overrides
20689 appropriately for VxWorks. */
906e58ca 20690
4e7fd91e
PB		 20691static struct bfd_link_hash_table *
20692elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
20693{
20694 struct bfd_link_hash_table *ret;
20695
20696 ret = elf32_arm_link_hash_table_create (abfd);
20697 if (ret)
20698 {
20699 struct elf32_arm_link_hash_table *htab
00a97672 20700 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 20701 htab->use_rel = 0;
00a97672 20702 htab->vxworks_p = 1;
4e7fd91e
PB		 20703 }
20704 return ret;
906e58ca 20705}
4e7fd91e 20706
00a97672
RS		 20707static void
20708elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
20709{
20710 elf32_arm_final_write_processing (abfd, linker);
20711 elf_vxworks_final_write_processing (abfd, linker);
20712}
20713
906e58ca 20714#undef elf32_bed
4e7fd91e
PB		 20715#define elf32_bed elf32_arm_vxworks_bed
20716
906e58ca
NC		 20717#undef bfd_elf32_bfd_link_hash_table_create
20718#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 20719#undef elf_backend_final_write_processing
20720#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20721#undef elf_backend_emit_relocs
9eaff861 20722#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 20723
906e58ca 20724#undef elf_backend_may_use_rel_p
00a97672 20725#define elf_backend_may_use_rel_p 0
906e58ca 20726#undef elf_backend_may_use_rela_p
00a97672 20727#define elf_backend_may_use_rela_p 1
906e58ca 20728#undef elf_backend_default_use_rela_p
00a97672 20729#define elf_backend_default_use_rela_p 1
906e58ca 20730#undef elf_backend_want_plt_sym
00a97672 20731#define elf_backend_want_plt_sym 1
906e58ca 20732#undef ELF_MAXPAGESIZE
00a97672 20733#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 20734
20735#include "elf32-target.h"
20736
20737
21d799b5
NC		 20738/* Merge backend specific data from an object file to the output
20739 object file when linking. */
20740
20741static bfd_boolean
50e03d47 20742elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 20743{
50e03d47 20744 bfd *obfd = info->output_bfd;
21d799b5
NC		 20745 flagword out_flags;
20746 flagword in_flags;
20747 bfd_boolean flags_compatible = TRUE;
20748 asection *sec;
20749
cc643b88 20750 /* Check if we have the same endianness. */
50e03d47 20751 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 20752 return FALSE;
20753
20754 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
20755 return TRUE;
20756
50e03d47 20757 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 20758 return FALSE;
20759
20760 /* The input BFD must have had its flags initialised. */
20761 /* The following seems bogus to me -- The flags are initialized in
20762 the assembler but I don't think an elf_flags_init field is
20763 written into the object. */
20764 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20765
20766 in_flags = elf_elfheader (ibfd)->e_flags;
20767 out_flags = elf_elfheader (obfd)->e_flags;
20768
20769 /* In theory there is no reason why we couldn't handle this. However
20770 in practice it isn't even close to working and there is no real
20771 reason to want it. */
20772 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
20773 && !(ibfd->flags & DYNAMIC)
20774 && (in_flags & EF_ARM_BE8))
20775 {
871b3ab2 20776 _bfd_error_handler (_("error: %pB is already in final BE8 format"),
21d799b5
NC		 20777 ibfd);
20778 return FALSE;
20779 }
20780
20781 if (!elf_flags_init (obfd))
20782 {
20783 /* If the input is the default architecture and had the default
20784 flags then do not bother setting the flags for the output
20785 architecture, instead allow future merges to do this. If no
20786 future merges ever set these flags then they will retain their
99059e56
RM		 20787 uninitialised values, which surprise surprise, correspond
20788 to the default values. */
21d799b5
NC		 20789 if (bfd_get_arch_info (ibfd)->the_default
20790 && elf_elfheader (ibfd)->e_flags == 0)
20791 return TRUE;
20792
20793 elf_flags_init (obfd) = TRUE;
20794 elf_elfheader (obfd)->e_flags = in_flags;
20795
20796 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
20797 && bfd_get_arch_info (obfd)->the_default)
20798 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
20799
20800 return TRUE;
20801 }
20802
20803 /* Determine what should happen if the input ARM architecture
20804 does not match the output ARM architecture. */
20805 if (! bfd_arm_merge_machines (ibfd, obfd))
20806 return FALSE;
20807
20808 /* Identical flags must be compatible. */
20809 if (in_flags == out_flags)
20810 return TRUE;
20811
20812 /* Check to see if the input BFD actually contains any sections. If
20813 not, its flags may not have been initialised either, but it
20814 cannot actually cause any incompatiblity. Do not short-circuit
20815 dynamic objects; their section list may be emptied by
20816 elf_link_add_object_symbols.
20817
20818 Also check to see if there are no code sections in the input.
20819 In this case there is no need to check for code specific flags.
20820 XXX - do we need to worry about floating-point format compatability
20821 in data sections ? */
20822 if (!(ibfd->flags & DYNAMIC))
20823 {
20824 bfd_boolean null_input_bfd = TRUE;
20825 bfd_boolean only_data_sections = TRUE;
20826
20827 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
20828 {
20829 /* Ignore synthetic glue sections. */
20830 if (strcmp (sec->name, ".glue_7")
20831 && strcmp (sec->name, ".glue_7t"))
20832 {
20833 if ((bfd_get_section_flags (ibfd, sec)
20834 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
20835 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 20836 only_data_sections = FALSE;
21d799b5
NC		 20837
20838 null_input_bfd = FALSE;
20839 break;
20840 }
20841 }
20842
20843 if (null_input_bfd || only_data_sections)
20844 return TRUE;
20845 }
20846
20847 /* Complain about various flag mismatches. */
20848 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
20849 EF_ARM_EABI_VERSION (out_flags)))
20850 {
20851 _bfd_error_handler
90b6238f 20852 (_("error: source object %pB has EABI version %d, but target %pB has EABI version %d"),
c08bb8dd
AM		 20853 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
20854 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 20855 return FALSE;
20856 }
20857
20858 /* Not sure what needs to be checked for EABI versions >= 1. */
20859 /* VxWorks libraries do not use these flags. */
20860 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
20861 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
20862 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
20863 {
20864 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
20865 {
20866 _bfd_error_handler
871b3ab2 20867 (_("error: %pB is compiled for APCS-%d, whereas target %pB uses APCS-%d"),
c08bb8dd
AM		 20868 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
20869 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 20870 flags_compatible = FALSE;
20871 }
20872
20873 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
20874 {
20875 if (in_flags & EF_ARM_APCS_FLOAT)
20876 _bfd_error_handler
871b3ab2 20877 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
21d799b5
NC		 20878 ibfd, obfd);
20879 else
20880 _bfd_error_handler
871b3ab2 20881 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
21d799b5
NC		 20882 ibfd, obfd);
20883
20884 flags_compatible = FALSE;
20885 }
20886
20887 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
20888 {
20889 if (in_flags & EF_ARM_VFP_FLOAT)
20890 _bfd_error_handler
90b6238f
AM		 20891 (_("error: %pB uses %s instructions, whereas %pB does not"),
20892 ibfd, "VFP", obfd);
21d799b5
NC		 20893 else
20894 _bfd_error_handler
90b6238f
AM		 20895 (_("error: %pB uses %s instructions, whereas %pB does not"),
20896 ibfd, "FPA", obfd);
21d799b5
NC		 20897
20898 flags_compatible = FALSE;
20899 }
20900
20901 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
20902 {
20903 if (in_flags & EF_ARM_MAVERICK_FLOAT)
20904 _bfd_error_handler
90b6238f
AM		 20905 (_("error: %pB uses %s instructions, whereas %pB does not"),
20906 ibfd, "Maverick", obfd);
21d799b5
NC		 20907 else
20908 _bfd_error_handler
90b6238f
AM		 20909 (_("error: %pB does not use %s instructions, whereas %pB does"),
20910 ibfd, "Maverick", obfd);
21d799b5
NC		 20911
20912 flags_compatible = FALSE;
20913 }
20914
20915#ifdef EF_ARM_SOFT_FLOAT
20916 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
20917 {
20918 /* We can allow interworking between code that is VFP format
20919 layout, and uses either soft float or integer regs for
20920 passing floating point arguments and results. We already
20921 know that the APCS_FLOAT flags match; similarly for VFP
20922 flags. */
20923 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
20924 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
20925 {
20926 if (in_flags & EF_ARM_SOFT_FLOAT)
20927 _bfd_error_handler
871b3ab2 20928 (_("error: %pB uses software FP, whereas %pB uses hardware FP"),
21d799b5
NC		 20929 ibfd, obfd);
20930 else
20931 _bfd_error_handler
871b3ab2 20932 (_("error: %pB uses hardware FP, whereas %pB uses software FP"),
21d799b5
NC		 20933 ibfd, obfd);
20934
20935 flags_compatible = FALSE;
20936 }
20937 }
20938#endif
20939
20940 /* Interworking mismatch is only a warning. */
20941 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
20942 {
20943 if (in_flags & EF_ARM_INTERWORK)
20944 {
20945 _bfd_error_handler
90b6238f 20946 (_("warning: %pB supports interworking, whereas %pB does not"),
21d799b5
NC		 20947 ibfd, obfd);
20948 }
20949 else
20950 {
20951 _bfd_error_handler
90b6238f 20952 (_("warning: %pB does not support interworking, whereas %pB does"),
21d799b5
NC		 20953 ibfd, obfd);
20954 }
20955 }
20956 }
20957
20958 return flags_compatible;
20959}
20960
20961
906e58ca 20962/* Symbian OS Targets. */
7f266840 20963
07d6d2b8
AM		 20964#undef TARGET_LITTLE_SYM
20965#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
20966#undef TARGET_LITTLE_NAME
20967#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
20968#undef TARGET_BIG_SYM
20969#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
20970#undef TARGET_BIG_NAME
20971#define TARGET_BIG_NAME "elf32-bigarm-symbian"
7f266840
DJ		 20972
20973/* Like elf32_arm_link_hash_table_create -- but overrides
20974 appropriately for Symbian OS. */
906e58ca 20975
7f266840
DJ		 20976static struct bfd_link_hash_table *
20977elf32_arm_symbian_link_hash_table_create (bfd *abfd)
20978{
20979 struct bfd_link_hash_table *ret;
20980
20981 ret = elf32_arm_link_hash_table_create (abfd);
20982 if (ret)
20983 {
20984 struct elf32_arm_link_hash_table *htab
20985 = (struct elf32_arm_link_hash_table *)ret;
20986 /* There is no PLT header for Symbian OS. */
20987 htab->plt_header_size = 0;
95720a86
DJ		 20988 /* The PLT entries are each one instruction and one word. */
20989 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 20990 htab->symbian_p = 1;
33bfe774
JB		 20991 /* Symbian uses armv5t or above, so use_blx is always true. */
20992 htab->use_blx = 1;
67687978 20993 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 20994 }
20995 return ret;
906e58ca 20996}
7f266840 20997
b35d266b 20998static const struct bfd_elf_special_section
551b43fd 20999elf32_arm_symbian_special_sections[] =
7f266840 21000{
5cd3778d
MM		 21001 /* In a BPABI executable, the dynamic linking sections do not go in
21002 the loadable read-only segment. The post-linker may wish to
21003 refer to these sections, but they are not part of the final
21004 program image. */
07d6d2b8
AM		 21005 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
21006 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
21007 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
21008 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
21009 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 21010 /* These sections do not need to be writable as the SymbianOS
21011 postlinker will arrange things so that no dynamic relocation is
21012 required. */
07d6d2b8
AM		 21013 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
21014 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
0112cd26 21015 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
07d6d2b8 21016 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 21017};
21018
c3c76620 21019static void
906e58ca 21020elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 21021 struct bfd_link_info *link_info)
c3c76620
MM		 21022{
21023 /* BPABI objects are never loaded directly by an OS kernel; they are
21024 processed by a postlinker first, into an OS-specific format. If
21025 the D_PAGED bit is set on the file, BFD will align segments on
21026 page boundaries, so that an OS can directly map the file. With
21027 BPABI objects, that just results in wasted space. In addition,
21028 because we clear the D_PAGED bit, map_sections_to_segments will
21029 recognize that the program headers should not be mapped into any
21030 loadable segment. */
21031 abfd->flags &= ~D_PAGED;
906e58ca 21032 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 21033}
7f266840
DJ		 21034
21035static bfd_boolean
906e58ca 21036elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 21037 struct bfd_link_info *info)
7f266840
DJ		 21038{
21039 struct elf_segment_map *m;
21040 asection *dynsec;
21041
7f266840
DJ		 21042 /* BPABI shared libraries and executables should have a PT_DYNAMIC
21043 segment. However, because the .dynamic section is not marked
21044 with SEC_LOAD, the generic ELF code will not create such a
21045 segment. */
21046 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
21047 if (dynsec)
21048 {
12bd6957 21049 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 21050 if (m->p_type == PT_DYNAMIC)
21051 break;
21052
21053 if (m == NULL)
21054 {
21055 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 21056 m->next = elf_seg_map (abfd);
21057 elf_seg_map (abfd) = m;
8ded5a0f 21058 }
7f266840
DJ		 21059 }
21060
b294bdf8
MM		 21061 /* Also call the generic arm routine. */
21062 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 21063}
21064
95720a86
DJ		 21065/* Return address for Ith PLT stub in section PLT, for relocation REL
21066 or (bfd_vma) -1 if it should not be included. */
21067
21068static bfd_vma
21069elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
21070 const arelent *rel ATTRIBUTE_UNUSED)
21071{
21072 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
21073}
21074
8029a119 21075#undef elf32_bed
7f266840
DJ		 21076#define elf32_bed elf32_arm_symbian_bed
21077
21078/* The dynamic sections are not allocated on SymbianOS; the postlinker
21079 will process them and then discard them. */
906e58ca 21080#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 21081#define ELF_DYNAMIC_SEC_FLAGS \
21082 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
21083
9eaff861 21084#undef elf_backend_emit_relocs
c3c76620 21085
906e58ca
NC		 21086#undef bfd_elf32_bfd_link_hash_table_create
21087#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
21088#undef elf_backend_special_sections
07d6d2b8 21089#define elf_backend_special_sections elf32_arm_symbian_special_sections
906e58ca
NC		 21090#undef elf_backend_begin_write_processing
21091#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
21092#undef elf_backend_final_write_processing
21093#define elf_backend_final_write_processing elf32_arm_final_write_processing
21094
21095#undef elf_backend_modify_segment_map
7f266840
DJ		 21096#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
21097
21098/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 21099#undef elf_backend_got_header_size
7f266840
DJ		 21100#define elf_backend_got_header_size 0
21101
21102/* Similarly, there is no .got.plt section. */
906e58ca 21103#undef elf_backend_want_got_plt
7f266840
DJ		 21104#define elf_backend_want_got_plt 0
21105
906e58ca 21106#undef elf_backend_plt_sym_val
95720a86
DJ		 21107#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
21108
906e58ca 21109#undef elf_backend_may_use_rel_p
00a97672 21110#define elf_backend_may_use_rel_p 1
906e58ca 21111#undef elf_backend_may_use_rela_p
00a97672 21112#define elf_backend_may_use_rela_p 0
906e58ca 21113#undef elf_backend_default_use_rela_p
00a97672 21114#define elf_backend_default_use_rela_p 0
906e58ca 21115#undef elf_backend_want_plt_sym
00a97672 21116#define elf_backend_want_plt_sym 0
64f52338
AM		 21117#undef elf_backend_dtrel_excludes_plt
21118#define elf_backend_dtrel_excludes_plt 0
906e58ca 21119#undef ELF_MAXPAGESIZE
00a97672 21120#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 21121
7f266840 21122#include "elf32-target.h"
GDB Binutils - Deliverables
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