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[gdb] Only force INTERP_CONSOLE ui_out for breakpoint commands in MI mode
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
82704155 2 Copyright (C) 1998-2019 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
00a97672 25#include "libiberty.h"
7f266840
DJ		 26#include "libbfd.h"
27#include "elf-bfd.h"
b38cadfb 28#include "elf-nacl.h"
00a97672 29#include "elf-vxworks.h"
ee065d83 30#include "elf/arm.h"
f37164d7
AM		 31#include "elf32-arm.h"
32#include "cpu-arm.h"
7f266840 33
00a97672
RS		 34/* Return the relocation section associated with NAME. HTAB is the
35 bfd's elf32_arm_link_hash_entry. */
36#define RELOC_SECTION(HTAB, NAME) \
37 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
38
39/* Return size of a relocation entry. HTAB is the bfd's
40 elf32_arm_link_hash_entry. */
41#define RELOC_SIZE(HTAB) \
42 ((HTAB)->use_rel \
43 ? sizeof (Elf32_External_Rel) \
44 : sizeof (Elf32_External_Rela))
45
46/* Return function to swap relocations in. HTAB is the bfd's
47 elf32_arm_link_hash_entry. */
48#define SWAP_RELOC_IN(HTAB) \
49 ((HTAB)->use_rel \
50 ? bfd_elf32_swap_reloc_in \
51 : bfd_elf32_swap_reloca_in)
52
53/* Return function to swap relocations out. HTAB is the bfd's
54 elf32_arm_link_hash_entry. */
55#define SWAP_RELOC_OUT(HTAB) \
56 ((HTAB)->use_rel \
57 ? bfd_elf32_swap_reloc_out \
58 : bfd_elf32_swap_reloca_out)
59
f3185997 60#define elf_info_to_howto NULL
07d6d2b8 61#define elf_info_to_howto_rel elf32_arm_info_to_howto
7f266840
DJ		 62
63#define ARM_ELF_ABI_VERSION 0
64#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
65
79f08007
YZ		 66/* The Adjusted Place, as defined by AAELF. */
67#define Pa(X) ((X) & 0xfffffffc)
68
3e6b1042
DJ		 69static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
70 struct bfd_link_info *link_info,
71 asection *sec,
72 bfd_byte *contents);
73
7f266840
DJ		 74/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
75 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
76 in that slot. */
77
c19d1205 78static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 79{
8029a119 80 /* No relocation. */
7f266840
DJ		 81 HOWTO (R_ARM_NONE, /* type */
82 0, /* rightshift */
6346d5ca 83 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 84 0, /* bitsize */
85 FALSE, /* pc_relative */
86 0, /* bitpos */
87 complain_overflow_dont,/* complain_on_overflow */
88 bfd_elf_generic_reloc, /* special_function */
89 "R_ARM_NONE", /* name */
90 FALSE, /* partial_inplace */
91 0, /* src_mask */
92 0, /* dst_mask */
93 FALSE), /* pcrel_offset */
94
95 HOWTO (R_ARM_PC24, /* type */
96 2, /* rightshift */
97 2, /* size (0 = byte, 1 = short, 2 = long) */
98 24, /* bitsize */
99 TRUE, /* pc_relative */
100 0, /* bitpos */
101 complain_overflow_signed,/* complain_on_overflow */
102 bfd_elf_generic_reloc, /* special_function */
103 "R_ARM_PC24", /* name */
104 FALSE, /* partial_inplace */
105 0x00ffffff, /* src_mask */
106 0x00ffffff, /* dst_mask */
107 TRUE), /* pcrel_offset */
108
109 /* 32 bit absolute */
110 HOWTO (R_ARM_ABS32, /* type */
111 0, /* rightshift */
112 2, /* size (0 = byte, 1 = short, 2 = long) */
113 32, /* bitsize */
114 FALSE, /* pc_relative */
115 0, /* bitpos */
116 complain_overflow_bitfield,/* complain_on_overflow */
117 bfd_elf_generic_reloc, /* special_function */
118 "R_ARM_ABS32", /* name */
119 FALSE, /* partial_inplace */
120 0xffffffff, /* src_mask */
121 0xffffffff, /* dst_mask */
122 FALSE), /* pcrel_offset */
123
124 /* standard 32bit pc-relative reloc */
125 HOWTO (R_ARM_REL32, /* type */
126 0, /* rightshift */
127 2, /* size (0 = byte, 1 = short, 2 = long) */
128 32, /* bitsize */
129 TRUE, /* pc_relative */
130 0, /* bitpos */
131 complain_overflow_bitfield,/* complain_on_overflow */
132 bfd_elf_generic_reloc, /* special_function */
133 "R_ARM_REL32", /* name */
134 FALSE, /* partial_inplace */
135 0xffffffff, /* src_mask */
136 0xffffffff, /* dst_mask */
137 TRUE), /* pcrel_offset */
138
c19d1205 139 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 140 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 141 0, /* rightshift */
142 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 143 32, /* bitsize */
144 TRUE, /* pc_relative */
7f266840 145 0, /* bitpos */
4962c51a 146 complain_overflow_dont,/* complain_on_overflow */
7f266840 147 bfd_elf_generic_reloc, /* special_function */
4962c51a 148 "R_ARM_LDR_PC_G0", /* name */
7f266840 149 FALSE, /* partial_inplace */
4962c51a
MS		 150 0xffffffff, /* src_mask */
151 0xffffffff, /* dst_mask */
152 TRUE), /* pcrel_offset */
7f266840
DJ		 153
154 /* 16 bit absolute */
155 HOWTO (R_ARM_ABS16, /* type */
156 0, /* rightshift */
157 1, /* size (0 = byte, 1 = short, 2 = long) */
158 16, /* bitsize */
159 FALSE, /* pc_relative */
160 0, /* bitpos */
161 complain_overflow_bitfield,/* complain_on_overflow */
162 bfd_elf_generic_reloc, /* special_function */
163 "R_ARM_ABS16", /* name */
164 FALSE, /* partial_inplace */
165 0x0000ffff, /* src_mask */
166 0x0000ffff, /* dst_mask */
167 FALSE), /* pcrel_offset */
168
169 /* 12 bit absolute */
170 HOWTO (R_ARM_ABS12, /* type */
171 0, /* rightshift */
172 2, /* size (0 = byte, 1 = short, 2 = long) */
173 12, /* bitsize */
174 FALSE, /* pc_relative */
175 0, /* bitpos */
176 complain_overflow_bitfield,/* complain_on_overflow */
177 bfd_elf_generic_reloc, /* special_function */
178 "R_ARM_ABS12", /* name */
179 FALSE, /* partial_inplace */
00a97672
RS		 180 0x00000fff, /* src_mask */
181 0x00000fff, /* dst_mask */
7f266840
DJ		 182 FALSE), /* pcrel_offset */
183
184 HOWTO (R_ARM_THM_ABS5, /* type */
185 6, /* rightshift */
186 1, /* size (0 = byte, 1 = short, 2 = long) */
187 5, /* bitsize */
188 FALSE, /* pc_relative */
189 0, /* bitpos */
190 complain_overflow_bitfield,/* complain_on_overflow */
191 bfd_elf_generic_reloc, /* special_function */
192 "R_ARM_THM_ABS5", /* name */
193 FALSE, /* partial_inplace */
194 0x000007e0, /* src_mask */
195 0x000007e0, /* dst_mask */
196 FALSE), /* pcrel_offset */
197
198 /* 8 bit absolute */
199 HOWTO (R_ARM_ABS8, /* type */
200 0, /* rightshift */
201 0, /* size (0 = byte, 1 = short, 2 = long) */
202 8, /* bitsize */
203 FALSE, /* pc_relative */
204 0, /* bitpos */
205 complain_overflow_bitfield,/* complain_on_overflow */
206 bfd_elf_generic_reloc, /* special_function */
207 "R_ARM_ABS8", /* name */
208 FALSE, /* partial_inplace */
209 0x000000ff, /* src_mask */
210 0x000000ff, /* dst_mask */
211 FALSE), /* pcrel_offset */
212
213 HOWTO (R_ARM_SBREL32, /* type */
214 0, /* rightshift */
215 2, /* size (0 = byte, 1 = short, 2 = long) */
216 32, /* bitsize */
217 FALSE, /* pc_relative */
218 0, /* bitpos */
219 complain_overflow_dont,/* complain_on_overflow */
220 bfd_elf_generic_reloc, /* special_function */
221 "R_ARM_SBREL32", /* name */
222 FALSE, /* partial_inplace */
223 0xffffffff, /* src_mask */
224 0xffffffff, /* dst_mask */
225 FALSE), /* pcrel_offset */
226
c19d1205 227 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 228 1, /* rightshift */
229 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 230 24, /* bitsize */
7f266840
DJ		 231 TRUE, /* pc_relative */
232 0, /* bitpos */
233 complain_overflow_signed,/* complain_on_overflow */
234 bfd_elf_generic_reloc, /* special_function */
c19d1205 235 "R_ARM_THM_CALL", /* name */
7f266840 236 FALSE, /* partial_inplace */
7f6ab9f8
AM		 237 0x07ff2fff, /* src_mask */
238 0x07ff2fff, /* dst_mask */
7f266840
DJ		 239 TRUE), /* pcrel_offset */
240
07d6d2b8 241 HOWTO (R_ARM_THM_PC8, /* type */
7f266840
DJ		 242 1, /* rightshift */
243 1, /* size (0 = byte, 1 = short, 2 = long) */
244 8, /* bitsize */
245 TRUE, /* pc_relative */
246 0, /* bitpos */
247 complain_overflow_signed,/* complain_on_overflow */
248 bfd_elf_generic_reloc, /* special_function */
249 "R_ARM_THM_PC8", /* name */
250 FALSE, /* partial_inplace */
251 0x000000ff, /* src_mask */
252 0x000000ff, /* dst_mask */
253 TRUE), /* pcrel_offset */
254
c19d1205 255 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 256 1, /* rightshift */
257 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 258 32, /* bitsize */
259 FALSE, /* pc_relative */
7f266840
DJ		 260 0, /* bitpos */
261 complain_overflow_signed,/* complain_on_overflow */
262 bfd_elf_generic_reloc, /* special_function */
c19d1205 263 "R_ARM_BREL_ADJ", /* name */
7f266840 264 FALSE, /* partial_inplace */
c19d1205
ZW		 265 0xffffffff, /* src_mask */
266 0xffffffff, /* dst_mask */
267 FALSE), /* pcrel_offset */
7f266840 268
0855e32b 269 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 270 0, /* rightshift */
0855e32b
NS		 271 2, /* size (0 = byte, 1 = short, 2 = long) */
272 32, /* bitsize */
7f266840
DJ		 273 FALSE, /* pc_relative */
274 0, /* bitpos */
0855e32b 275 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 276 bfd_elf_generic_reloc, /* special_function */
0855e32b 277 "R_ARM_TLS_DESC", /* name */
7f266840 278 FALSE, /* partial_inplace */
0855e32b
NS		 279 0xffffffff, /* src_mask */
280 0xffffffff, /* dst_mask */
7f266840
DJ		 281 FALSE), /* pcrel_offset */
282
283 HOWTO (R_ARM_THM_SWI8, /* type */
284 0, /* rightshift */
285 0, /* size (0 = byte, 1 = short, 2 = long) */
286 0, /* bitsize */
287 FALSE, /* pc_relative */
288 0, /* bitpos */
289 complain_overflow_signed,/* complain_on_overflow */
290 bfd_elf_generic_reloc, /* special_function */
291 "R_ARM_SWI8", /* name */
292 FALSE, /* partial_inplace */
293 0x00000000, /* src_mask */
294 0x00000000, /* dst_mask */
295 FALSE), /* pcrel_offset */
296
297 /* BLX instruction for the ARM. */
298 HOWTO (R_ARM_XPC25, /* type */
299 2, /* rightshift */
300 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 301 24, /* bitsize */
7f266840
DJ		 302 TRUE, /* pc_relative */
303 0, /* bitpos */
304 complain_overflow_signed,/* complain_on_overflow */
305 bfd_elf_generic_reloc, /* special_function */
306 "R_ARM_XPC25", /* name */
307 FALSE, /* partial_inplace */
308 0x00ffffff, /* src_mask */
309 0x00ffffff, /* dst_mask */
310 TRUE), /* pcrel_offset */
311
312 /* BLX instruction for the Thumb. */
313 HOWTO (R_ARM_THM_XPC22, /* type */
314 2, /* rightshift */
315 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 316 24, /* bitsize */
7f266840
DJ		 317 TRUE, /* pc_relative */
318 0, /* bitpos */
319 complain_overflow_signed,/* complain_on_overflow */
320 bfd_elf_generic_reloc, /* special_function */
321 "R_ARM_THM_XPC22", /* name */
322 FALSE, /* partial_inplace */
7f6ab9f8
AM		 323 0x07ff2fff, /* src_mask */
324 0x07ff2fff, /* dst_mask */
7f266840
DJ		 325 TRUE), /* pcrel_offset */
326
ba93b8ac 327 /* Dynamic TLS relocations. */
7f266840 328
ba93b8ac 329 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
07d6d2b8
AM		 330 0, /* rightshift */
331 2, /* size (0 = byte, 1 = short, 2 = long) */
332 32, /* bitsize */
333 FALSE, /* pc_relative */
334 0, /* bitpos */
99059e56
RM		 335 complain_overflow_bitfield,/* complain_on_overflow */
336 bfd_elf_generic_reloc, /* special_function */
337 "R_ARM_TLS_DTPMOD32", /* name */
338 TRUE, /* partial_inplace */
339 0xffffffff, /* src_mask */
340 0xffffffff, /* dst_mask */
07d6d2b8 341 FALSE), /* pcrel_offset */
7f266840 342
ba93b8ac 343 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
07d6d2b8
AM		 344 0, /* rightshift */
345 2, /* size (0 = byte, 1 = short, 2 = long) */
346 32, /* bitsize */
347 FALSE, /* pc_relative */
348 0, /* bitpos */
99059e56
RM		 349 complain_overflow_bitfield,/* complain_on_overflow */
350 bfd_elf_generic_reloc, /* special_function */
351 "R_ARM_TLS_DTPOFF32", /* name */
352 TRUE, /* partial_inplace */
353 0xffffffff, /* src_mask */
354 0xffffffff, /* dst_mask */
07d6d2b8 355 FALSE), /* pcrel_offset */
7f266840 356
ba93b8ac 357 HOWTO (R_ARM_TLS_TPOFF32, /* type */
07d6d2b8
AM		 358 0, /* rightshift */
359 2, /* size (0 = byte, 1 = short, 2 = long) */
360 32, /* bitsize */
361 FALSE, /* pc_relative */
362 0, /* bitpos */
99059e56
RM		 363 complain_overflow_bitfield,/* complain_on_overflow */
364 bfd_elf_generic_reloc, /* special_function */
365 "R_ARM_TLS_TPOFF32", /* name */
366 TRUE, /* partial_inplace */
367 0xffffffff, /* src_mask */
368 0xffffffff, /* dst_mask */
07d6d2b8 369 FALSE), /* pcrel_offset */
7f266840
DJ		 370
371 /* Relocs used in ARM Linux */
372
373 HOWTO (R_ARM_COPY, /* type */
07d6d2b8
AM		 374 0, /* rightshift */
375 2, /* size (0 = byte, 1 = short, 2 = long) */
376 32, /* bitsize */
377 FALSE, /* pc_relative */
378 0, /* bitpos */
99059e56
RM		 379 complain_overflow_bitfield,/* complain_on_overflow */
380 bfd_elf_generic_reloc, /* special_function */
381 "R_ARM_COPY", /* name */
382 TRUE, /* partial_inplace */
383 0xffffffff, /* src_mask */
384 0xffffffff, /* dst_mask */
07d6d2b8 385 FALSE), /* pcrel_offset */
7f266840
DJ		 386
387 HOWTO (R_ARM_GLOB_DAT, /* type */
07d6d2b8
AM		 388 0, /* rightshift */
389 2, /* size (0 = byte, 1 = short, 2 = long) */
390 32, /* bitsize */
391 FALSE, /* pc_relative */
392 0, /* bitpos */
99059e56
RM		 393 complain_overflow_bitfield,/* complain_on_overflow */
394 bfd_elf_generic_reloc, /* special_function */
395 "R_ARM_GLOB_DAT", /* name */
396 TRUE, /* partial_inplace */
397 0xffffffff, /* src_mask */
398 0xffffffff, /* dst_mask */
07d6d2b8 399 FALSE), /* pcrel_offset */
7f266840
DJ		 400
401 HOWTO (R_ARM_JUMP_SLOT, /* type */
07d6d2b8
AM		 402 0, /* rightshift */
403 2, /* size (0 = byte, 1 = short, 2 = long) */
404 32, /* bitsize */
405 FALSE, /* pc_relative */
406 0, /* bitpos */
99059e56
RM		 407 complain_overflow_bitfield,/* complain_on_overflow */
408 bfd_elf_generic_reloc, /* special_function */
409 "R_ARM_JUMP_SLOT", /* name */
410 TRUE, /* partial_inplace */
411 0xffffffff, /* src_mask */
412 0xffffffff, /* dst_mask */
07d6d2b8 413 FALSE), /* pcrel_offset */
7f266840
DJ		 414
415 HOWTO (R_ARM_RELATIVE, /* type */
07d6d2b8
AM		 416 0, /* rightshift */
417 2, /* size (0 = byte, 1 = short, 2 = long) */
418 32, /* bitsize */
419 FALSE, /* pc_relative */
420 0, /* bitpos */
99059e56
RM		 421 complain_overflow_bitfield,/* complain_on_overflow */
422 bfd_elf_generic_reloc, /* special_function */
423 "R_ARM_RELATIVE", /* name */
424 TRUE, /* partial_inplace */
425 0xffffffff, /* src_mask */
426 0xffffffff, /* dst_mask */
07d6d2b8 427 FALSE), /* pcrel_offset */
7f266840 428
c19d1205 429 HOWTO (R_ARM_GOTOFF32, /* type */
07d6d2b8
AM		 430 0, /* rightshift */
431 2, /* size (0 = byte, 1 = short, 2 = long) */
432 32, /* bitsize */
433 FALSE, /* pc_relative */
434 0, /* bitpos */
99059e56
RM		 435 complain_overflow_bitfield,/* complain_on_overflow */
436 bfd_elf_generic_reloc, /* special_function */
437 "R_ARM_GOTOFF32", /* name */
438 TRUE, /* partial_inplace */
439 0xffffffff, /* src_mask */
440 0xffffffff, /* dst_mask */
07d6d2b8 441 FALSE), /* pcrel_offset */
7f266840
DJ		 442
443 HOWTO (R_ARM_GOTPC, /* type */
07d6d2b8
AM		 444 0, /* rightshift */
445 2, /* size (0 = byte, 1 = short, 2 = long) */
446 32, /* bitsize */
99059e56 447 TRUE, /* pc_relative */
07d6d2b8 448 0, /* bitpos */
99059e56
RM		 449 complain_overflow_bitfield,/* complain_on_overflow */
450 bfd_elf_generic_reloc, /* special_function */
451 "R_ARM_GOTPC", /* name */
452 TRUE, /* partial_inplace */
453 0xffffffff, /* src_mask */
454 0xffffffff, /* dst_mask */
455 TRUE), /* pcrel_offset */
7f266840
DJ		 456
457 HOWTO (R_ARM_GOT32, /* type */
07d6d2b8
AM		 458 0, /* rightshift */
459 2, /* size (0 = byte, 1 = short, 2 = long) */
460 32, /* bitsize */
99059e56 461 FALSE, /* pc_relative */
07d6d2b8 462 0, /* bitpos */
99059e56
RM		 463 complain_overflow_bitfield,/* complain_on_overflow */
464 bfd_elf_generic_reloc, /* special_function */
465 "R_ARM_GOT32", /* name */
466 TRUE, /* partial_inplace */
467 0xffffffff, /* src_mask */
468 0xffffffff, /* dst_mask */
469 FALSE), /* pcrel_offset */
7f266840
DJ		 470
471 HOWTO (R_ARM_PLT32, /* type */
07d6d2b8
AM		 472 2, /* rightshift */
473 2, /* size (0 = byte, 1 = short, 2 = long) */
474 24, /* bitsize */
99059e56 475 TRUE, /* pc_relative */
07d6d2b8 476 0, /* bitpos */
99059e56
RM		 477 complain_overflow_bitfield,/* complain_on_overflow */
478 bfd_elf_generic_reloc, /* special_function */
479 "R_ARM_PLT32", /* name */
480 FALSE, /* partial_inplace */
481 0x00ffffff, /* src_mask */
482 0x00ffffff, /* dst_mask */
483 TRUE), /* pcrel_offset */
7f266840
DJ		 484
485 HOWTO (R_ARM_CALL, /* type */
486 2, /* rightshift */
487 2, /* size (0 = byte, 1 = short, 2 = long) */
488 24, /* bitsize */
489 TRUE, /* pc_relative */
490 0, /* bitpos */
491 complain_overflow_signed,/* complain_on_overflow */
492 bfd_elf_generic_reloc, /* special_function */
493 "R_ARM_CALL", /* name */
494 FALSE, /* partial_inplace */
495 0x00ffffff, /* src_mask */
496 0x00ffffff, /* dst_mask */
497 TRUE), /* pcrel_offset */
498
499 HOWTO (R_ARM_JUMP24, /* type */
500 2, /* rightshift */
501 2, /* size (0 = byte, 1 = short, 2 = long) */
502 24, /* bitsize */
503 TRUE, /* pc_relative */
504 0, /* bitpos */
505 complain_overflow_signed,/* complain_on_overflow */
506 bfd_elf_generic_reloc, /* special_function */
507 "R_ARM_JUMP24", /* name */
508 FALSE, /* partial_inplace */
509 0x00ffffff, /* src_mask */
510 0x00ffffff, /* dst_mask */
511 TRUE), /* pcrel_offset */
512
c19d1205
ZW		 513 HOWTO (R_ARM_THM_JUMP24, /* type */
514 1, /* rightshift */
515 2, /* size (0 = byte, 1 = short, 2 = long) */
516 24, /* bitsize */
517 TRUE, /* pc_relative */
7f266840 518 0, /* bitpos */
c19d1205 519 complain_overflow_signed,/* complain_on_overflow */
7f266840 520 bfd_elf_generic_reloc, /* special_function */
c19d1205 521 "R_ARM_THM_JUMP24", /* name */
7f266840 522 FALSE, /* partial_inplace */
c19d1205
ZW		 523 0x07ff2fff, /* src_mask */
524 0x07ff2fff, /* dst_mask */
525 TRUE), /* pcrel_offset */
7f266840 526
c19d1205 527 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 528 0, /* rightshift */
c19d1205
ZW		 529 2, /* size (0 = byte, 1 = short, 2 = long) */
530 32, /* bitsize */
7f266840
DJ		 531 FALSE, /* pc_relative */
532 0, /* bitpos */
533 complain_overflow_dont,/* complain_on_overflow */
534 bfd_elf_generic_reloc, /* special_function */
c19d1205 535 "R_ARM_BASE_ABS", /* name */
7f266840 536 FALSE, /* partial_inplace */
c19d1205
ZW		 537 0xffffffff, /* src_mask */
538 0xffffffff, /* dst_mask */
7f266840
DJ		 539 FALSE), /* pcrel_offset */
540
541 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
542 0, /* rightshift */
543 2, /* size (0 = byte, 1 = short, 2 = long) */
544 12, /* bitsize */
545 TRUE, /* pc_relative */
546 0, /* bitpos */
547 complain_overflow_dont,/* complain_on_overflow */
548 bfd_elf_generic_reloc, /* special_function */
549 "R_ARM_ALU_PCREL_7_0", /* name */
550 FALSE, /* partial_inplace */
551 0x00000fff, /* src_mask */
552 0x00000fff, /* dst_mask */
553 TRUE), /* pcrel_offset */
554
555 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
556 0, /* rightshift */
557 2, /* size (0 = byte, 1 = short, 2 = long) */
558 12, /* bitsize */
559 TRUE, /* pc_relative */
560 8, /* bitpos */
561 complain_overflow_dont,/* complain_on_overflow */
562 bfd_elf_generic_reloc, /* special_function */
563 "R_ARM_ALU_PCREL_15_8",/* name */
564 FALSE, /* partial_inplace */
565 0x00000fff, /* src_mask */
566 0x00000fff, /* dst_mask */
567 TRUE), /* pcrel_offset */
568
569 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
570 0, /* rightshift */
571 2, /* size (0 = byte, 1 = short, 2 = long) */
572 12, /* bitsize */
573 TRUE, /* pc_relative */
574 16, /* bitpos */
575 complain_overflow_dont,/* complain_on_overflow */
576 bfd_elf_generic_reloc, /* special_function */
577 "R_ARM_ALU_PCREL_23_15",/* name */
578 FALSE, /* partial_inplace */
579 0x00000fff, /* src_mask */
580 0x00000fff, /* dst_mask */
581 TRUE), /* pcrel_offset */
582
583 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
584 0, /* rightshift */
585 2, /* size (0 = byte, 1 = short, 2 = long) */
586 12, /* bitsize */
587 FALSE, /* pc_relative */
588 0, /* bitpos */
589 complain_overflow_dont,/* complain_on_overflow */
590 bfd_elf_generic_reloc, /* special_function */
591 "R_ARM_LDR_SBREL_11_0",/* name */
592 FALSE, /* partial_inplace */
593 0x00000fff, /* src_mask */
594 0x00000fff, /* dst_mask */
595 FALSE), /* pcrel_offset */
596
597 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
598 0, /* rightshift */
599 2, /* size (0 = byte, 1 = short, 2 = long) */
600 8, /* bitsize */
601 FALSE, /* pc_relative */
602 12, /* bitpos */
603 complain_overflow_dont,/* complain_on_overflow */
604 bfd_elf_generic_reloc, /* special_function */
605 "R_ARM_ALU_SBREL_19_12",/* name */
606 FALSE, /* partial_inplace */
607 0x000ff000, /* src_mask */
608 0x000ff000, /* dst_mask */
609 FALSE), /* pcrel_offset */
610
611 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
612 0, /* rightshift */
613 2, /* size (0 = byte, 1 = short, 2 = long) */
614 8, /* bitsize */
615 FALSE, /* pc_relative */
616 20, /* bitpos */
617 complain_overflow_dont,/* complain_on_overflow */
618 bfd_elf_generic_reloc, /* special_function */
619 "R_ARM_ALU_SBREL_27_20",/* name */
620 FALSE, /* partial_inplace */
621 0x0ff00000, /* src_mask */
622 0x0ff00000, /* dst_mask */
623 FALSE), /* pcrel_offset */
624
625 HOWTO (R_ARM_TARGET1, /* type */
626 0, /* rightshift */
627 2, /* size (0 = byte, 1 = short, 2 = long) */
628 32, /* bitsize */
629 FALSE, /* pc_relative */
630 0, /* bitpos */
631 complain_overflow_dont,/* complain_on_overflow */
632 bfd_elf_generic_reloc, /* special_function */
633 "R_ARM_TARGET1", /* name */
634 FALSE, /* partial_inplace */
635 0xffffffff, /* src_mask */
636 0xffffffff, /* dst_mask */
637 FALSE), /* pcrel_offset */
638
639 HOWTO (R_ARM_ROSEGREL32, /* type */
640 0, /* rightshift */
641 2, /* size (0 = byte, 1 = short, 2 = long) */
642 32, /* bitsize */
643 FALSE, /* pc_relative */
644 0, /* bitpos */
645 complain_overflow_dont,/* complain_on_overflow */
646 bfd_elf_generic_reloc, /* special_function */
647 "R_ARM_ROSEGREL32", /* name */
648 FALSE, /* partial_inplace */
649 0xffffffff, /* src_mask */
650 0xffffffff, /* dst_mask */
651 FALSE), /* pcrel_offset */
652
653 HOWTO (R_ARM_V4BX, /* type */
654 0, /* rightshift */
655 2, /* size (0 = byte, 1 = short, 2 = long) */
656 32, /* bitsize */
657 FALSE, /* pc_relative */
658 0, /* bitpos */
659 complain_overflow_dont,/* complain_on_overflow */
660 bfd_elf_generic_reloc, /* special_function */
661 "R_ARM_V4BX", /* name */
662 FALSE, /* partial_inplace */
663 0xffffffff, /* src_mask */
664 0xffffffff, /* dst_mask */
665 FALSE), /* pcrel_offset */
666
667 HOWTO (R_ARM_TARGET2, /* type */
668 0, /* rightshift */
669 2, /* size (0 = byte, 1 = short, 2 = long) */
670 32, /* bitsize */
671 FALSE, /* pc_relative */
672 0, /* bitpos */
673 complain_overflow_signed,/* complain_on_overflow */
674 bfd_elf_generic_reloc, /* special_function */
675 "R_ARM_TARGET2", /* name */
676 FALSE, /* partial_inplace */
677 0xffffffff, /* src_mask */
678 0xffffffff, /* dst_mask */
679 TRUE), /* pcrel_offset */
680
681 HOWTO (R_ARM_PREL31, /* type */
682 0, /* rightshift */
683 2, /* size (0 = byte, 1 = short, 2 = long) */
684 31, /* bitsize */
685 TRUE, /* pc_relative */
686 0, /* bitpos */
687 complain_overflow_signed,/* complain_on_overflow */
688 bfd_elf_generic_reloc, /* special_function */
689 "R_ARM_PREL31", /* name */
690 FALSE, /* partial_inplace */
691 0x7fffffff, /* src_mask */
692 0x7fffffff, /* dst_mask */
693 TRUE), /* pcrel_offset */
c19d1205
ZW		 694
695 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
696 0, /* rightshift */
697 2, /* size (0 = byte, 1 = short, 2 = long) */
698 16, /* bitsize */
699 FALSE, /* pc_relative */
700 0, /* bitpos */
701 complain_overflow_dont,/* complain_on_overflow */
702 bfd_elf_generic_reloc, /* special_function */
703 "R_ARM_MOVW_ABS_NC", /* name */
704 FALSE, /* partial_inplace */
39623e12
PB		 705 0x000f0fff, /* src_mask */
706 0x000f0fff, /* dst_mask */
c19d1205
ZW		 707 FALSE), /* pcrel_offset */
708
709 HOWTO (R_ARM_MOVT_ABS, /* type */
710 0, /* rightshift */
711 2, /* size (0 = byte, 1 = short, 2 = long) */
712 16, /* bitsize */
713 FALSE, /* pc_relative */
714 0, /* bitpos */
715 complain_overflow_bitfield,/* complain_on_overflow */
716 bfd_elf_generic_reloc, /* special_function */
717 "R_ARM_MOVT_ABS", /* name */
718 FALSE, /* partial_inplace */
39623e12
PB		 719 0x000f0fff, /* src_mask */
720 0x000f0fff, /* dst_mask */
c19d1205
ZW		 721 FALSE), /* pcrel_offset */
722
723 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
724 0, /* rightshift */
725 2, /* size (0 = byte, 1 = short, 2 = long) */
726 16, /* bitsize */
727 TRUE, /* pc_relative */
728 0, /* bitpos */
729 complain_overflow_dont,/* complain_on_overflow */
730 bfd_elf_generic_reloc, /* special_function */
731 "R_ARM_MOVW_PREL_NC", /* name */
732 FALSE, /* partial_inplace */
39623e12
PB		 733 0x000f0fff, /* src_mask */
734 0x000f0fff, /* dst_mask */
c19d1205
ZW		 735 TRUE), /* pcrel_offset */
736
737 HOWTO (R_ARM_MOVT_PREL, /* type */
738 0, /* rightshift */
739 2, /* size (0 = byte, 1 = short, 2 = long) */
740 16, /* bitsize */
741 TRUE, /* pc_relative */
742 0, /* bitpos */
743 complain_overflow_bitfield,/* complain_on_overflow */
744 bfd_elf_generic_reloc, /* special_function */
745 "R_ARM_MOVT_PREL", /* name */
746 FALSE, /* partial_inplace */
39623e12
PB		 747 0x000f0fff, /* src_mask */
748 0x000f0fff, /* dst_mask */
c19d1205
ZW		 749 TRUE), /* pcrel_offset */
750
751 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
752 0, /* rightshift */
753 2, /* size (0 = byte, 1 = short, 2 = long) */
754 16, /* bitsize */
755 FALSE, /* pc_relative */
756 0, /* bitpos */
757 complain_overflow_dont,/* complain_on_overflow */
758 bfd_elf_generic_reloc, /* special_function */
759 "R_ARM_THM_MOVW_ABS_NC",/* name */
760 FALSE, /* partial_inplace */
761 0x040f70ff, /* src_mask */
762 0x040f70ff, /* dst_mask */
763 FALSE), /* pcrel_offset */
764
765 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
766 0, /* rightshift */
767 2, /* size (0 = byte, 1 = short, 2 = long) */
768 16, /* bitsize */
769 FALSE, /* pc_relative */
770 0, /* bitpos */
771 complain_overflow_bitfield,/* complain_on_overflow */
772 bfd_elf_generic_reloc, /* special_function */
773 "R_ARM_THM_MOVT_ABS", /* name */
774 FALSE, /* partial_inplace */
775 0x040f70ff, /* src_mask */
776 0x040f70ff, /* dst_mask */
777 FALSE), /* pcrel_offset */
778
779 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
780 0, /* rightshift */
781 2, /* size (0 = byte, 1 = short, 2 = long) */
782 16, /* bitsize */
783 TRUE, /* pc_relative */
784 0, /* bitpos */
785 complain_overflow_dont,/* complain_on_overflow */
786 bfd_elf_generic_reloc, /* special_function */
787 "R_ARM_THM_MOVW_PREL_NC",/* name */
788 FALSE, /* partial_inplace */
789 0x040f70ff, /* src_mask */
790 0x040f70ff, /* dst_mask */
791 TRUE), /* pcrel_offset */
792
793 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
794 0, /* rightshift */
795 2, /* size (0 = byte, 1 = short, 2 = long) */
796 16, /* bitsize */
797 TRUE, /* pc_relative */
798 0, /* bitpos */
799 complain_overflow_bitfield,/* complain_on_overflow */
800 bfd_elf_generic_reloc, /* special_function */
801 "R_ARM_THM_MOVT_PREL", /* name */
802 FALSE, /* partial_inplace */
803 0x040f70ff, /* src_mask */
804 0x040f70ff, /* dst_mask */
805 TRUE), /* pcrel_offset */
806
807 HOWTO (R_ARM_THM_JUMP19, /* type */
808 1, /* rightshift */
809 2, /* size (0 = byte, 1 = short, 2 = long) */
810 19, /* bitsize */
811 TRUE, /* pc_relative */
812 0, /* bitpos */
813 complain_overflow_signed,/* complain_on_overflow */
814 bfd_elf_generic_reloc, /* special_function */
815 "R_ARM_THM_JUMP19", /* name */
816 FALSE, /* partial_inplace */
817 0x043f2fff, /* src_mask */
818 0x043f2fff, /* dst_mask */
819 TRUE), /* pcrel_offset */
820
821 HOWTO (R_ARM_THM_JUMP6, /* type */
822 1, /* rightshift */
823 1, /* size (0 = byte, 1 = short, 2 = long) */
824 6, /* bitsize */
825 TRUE, /* pc_relative */
826 0, /* bitpos */
827 complain_overflow_unsigned,/* complain_on_overflow */
828 bfd_elf_generic_reloc, /* special_function */
829 "R_ARM_THM_JUMP6", /* name */
830 FALSE, /* partial_inplace */
831 0x02f8, /* src_mask */
832 0x02f8, /* dst_mask */
833 TRUE), /* pcrel_offset */
834
835 /* These are declared as 13-bit signed relocations because we can
836 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
837 versa. */
838 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
839 0, /* rightshift */
840 2, /* size (0 = byte, 1 = short, 2 = long) */
841 13, /* bitsize */
842 TRUE, /* pc_relative */
843 0, /* bitpos */
2cab6cc3 844 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 845 bfd_elf_generic_reloc, /* special_function */
846 "R_ARM_THM_ALU_PREL_11_0",/* name */
847 FALSE, /* partial_inplace */
2cab6cc3
MS		 848 0xffffffff, /* src_mask */
849 0xffffffff, /* dst_mask */
c19d1205
ZW		 850 TRUE), /* pcrel_offset */
851
852 HOWTO (R_ARM_THM_PC12, /* type */
853 0, /* rightshift */
854 2, /* size (0 = byte, 1 = short, 2 = long) */
855 13, /* bitsize */
856 TRUE, /* pc_relative */
857 0, /* bitpos */
2cab6cc3 858 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 859 bfd_elf_generic_reloc, /* special_function */
860 "R_ARM_THM_PC12", /* name */
861 FALSE, /* partial_inplace */
2cab6cc3
MS		 862 0xffffffff, /* src_mask */
863 0xffffffff, /* dst_mask */
c19d1205
ZW		 864 TRUE), /* pcrel_offset */
865
866 HOWTO (R_ARM_ABS32_NOI, /* type */
867 0, /* rightshift */
868 2, /* size (0 = byte, 1 = short, 2 = long) */
869 32, /* bitsize */
870 FALSE, /* pc_relative */
871 0, /* bitpos */
872 complain_overflow_dont,/* complain_on_overflow */
873 bfd_elf_generic_reloc, /* special_function */
874 "R_ARM_ABS32_NOI", /* name */
875 FALSE, /* partial_inplace */
876 0xffffffff, /* src_mask */
877 0xffffffff, /* dst_mask */
878 FALSE), /* pcrel_offset */
879
880 HOWTO (R_ARM_REL32_NOI, /* type */
881 0, /* rightshift */
882 2, /* size (0 = byte, 1 = short, 2 = long) */
883 32, /* bitsize */
884 TRUE, /* pc_relative */
885 0, /* bitpos */
886 complain_overflow_dont,/* complain_on_overflow */
887 bfd_elf_generic_reloc, /* special_function */
888 "R_ARM_REL32_NOI", /* name */
889 FALSE, /* partial_inplace */
890 0xffffffff, /* src_mask */
891 0xffffffff, /* dst_mask */
892 FALSE), /* pcrel_offset */
7f266840 893
4962c51a
MS		 894 /* Group relocations. */
895
896 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
897 0, /* rightshift */
898 2, /* size (0 = byte, 1 = short, 2 = long) */
899 32, /* bitsize */
900 TRUE, /* pc_relative */
901 0, /* bitpos */
902 complain_overflow_dont,/* complain_on_overflow */
903 bfd_elf_generic_reloc, /* special_function */
904 "R_ARM_ALU_PC_G0_NC", /* name */
905 FALSE, /* partial_inplace */
906 0xffffffff, /* src_mask */
907 0xffffffff, /* dst_mask */
908 TRUE), /* pcrel_offset */
909
07d6d2b8 910 HOWTO (R_ARM_ALU_PC_G0, /* type */
4962c51a
MS		 911 0, /* rightshift */
912 2, /* size (0 = byte, 1 = short, 2 = long) */
913 32, /* bitsize */
914 TRUE, /* pc_relative */
915 0, /* bitpos */
916 complain_overflow_dont,/* complain_on_overflow */
917 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 918 "R_ARM_ALU_PC_G0", /* name */
4962c51a
MS		 919 FALSE, /* partial_inplace */
920 0xffffffff, /* src_mask */
921 0xffffffff, /* dst_mask */
922 TRUE), /* pcrel_offset */
923
924 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
925 0, /* rightshift */
926 2, /* size (0 = byte, 1 = short, 2 = long) */
927 32, /* bitsize */
928 TRUE, /* pc_relative */
929 0, /* bitpos */
930 complain_overflow_dont,/* complain_on_overflow */
931 bfd_elf_generic_reloc, /* special_function */
932 "R_ARM_ALU_PC_G1_NC", /* name */
933 FALSE, /* partial_inplace */
934 0xffffffff, /* src_mask */
935 0xffffffff, /* dst_mask */
936 TRUE), /* pcrel_offset */
937
07d6d2b8 938 HOWTO (R_ARM_ALU_PC_G1, /* type */
4962c51a
MS		 939 0, /* rightshift */
940 2, /* size (0 = byte, 1 = short, 2 = long) */
941 32, /* bitsize */
942 TRUE, /* pc_relative */
943 0, /* bitpos */
944 complain_overflow_dont,/* complain_on_overflow */
945 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 946 "R_ARM_ALU_PC_G1", /* name */
4962c51a
MS		 947 FALSE, /* partial_inplace */
948 0xffffffff, /* src_mask */
949 0xffffffff, /* dst_mask */
950 TRUE), /* pcrel_offset */
951
07d6d2b8 952 HOWTO (R_ARM_ALU_PC_G2, /* type */
4962c51a
MS		 953 0, /* rightshift */
954 2, /* size (0 = byte, 1 = short, 2 = long) */
955 32, /* bitsize */
956 TRUE, /* pc_relative */
957 0, /* bitpos */
958 complain_overflow_dont,/* complain_on_overflow */
959 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 960 "R_ARM_ALU_PC_G2", /* name */
4962c51a
MS		 961 FALSE, /* partial_inplace */
962 0xffffffff, /* src_mask */
963 0xffffffff, /* dst_mask */
964 TRUE), /* pcrel_offset */
965
07d6d2b8 966 HOWTO (R_ARM_LDR_PC_G1, /* type */
4962c51a
MS		 967 0, /* rightshift */
968 2, /* size (0 = byte, 1 = short, 2 = long) */
969 32, /* bitsize */
970 TRUE, /* pc_relative */
971 0, /* bitpos */
972 complain_overflow_dont,/* complain_on_overflow */
973 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 974 "R_ARM_LDR_PC_G1", /* name */
4962c51a
MS		 975 FALSE, /* partial_inplace */
976 0xffffffff, /* src_mask */
977 0xffffffff, /* dst_mask */
978 TRUE), /* pcrel_offset */
979
07d6d2b8 980 HOWTO (R_ARM_LDR_PC_G2, /* type */
4962c51a
MS		 981 0, /* rightshift */
982 2, /* size (0 = byte, 1 = short, 2 = long) */
983 32, /* bitsize */
984 TRUE, /* pc_relative */
985 0, /* bitpos */
986 complain_overflow_dont,/* complain_on_overflow */
987 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 988 "R_ARM_LDR_PC_G2", /* name */
4962c51a
MS		 989 FALSE, /* partial_inplace */
990 0xffffffff, /* src_mask */
991 0xffffffff, /* dst_mask */
992 TRUE), /* pcrel_offset */
993
07d6d2b8 994 HOWTO (R_ARM_LDRS_PC_G0, /* type */
4962c51a
MS		 995 0, /* rightshift */
996 2, /* size (0 = byte, 1 = short, 2 = long) */
997 32, /* bitsize */
998 TRUE, /* pc_relative */
999 0, /* bitpos */
1000 complain_overflow_dont,/* complain_on_overflow */
1001 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1002 "R_ARM_LDRS_PC_G0", /* name */
4962c51a
MS		 1003 FALSE, /* partial_inplace */
1004 0xffffffff, /* src_mask */
1005 0xffffffff, /* dst_mask */
1006 TRUE), /* pcrel_offset */
1007
07d6d2b8 1008 HOWTO (R_ARM_LDRS_PC_G1, /* type */
4962c51a
MS		 1009 0, /* rightshift */
1010 2, /* size (0 = byte, 1 = short, 2 = long) */
1011 32, /* bitsize */
1012 TRUE, /* pc_relative */
1013 0, /* bitpos */
1014 complain_overflow_dont,/* complain_on_overflow */
1015 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1016 "R_ARM_LDRS_PC_G1", /* name */
4962c51a
MS		 1017 FALSE, /* partial_inplace */
1018 0xffffffff, /* src_mask */
1019 0xffffffff, /* dst_mask */
1020 TRUE), /* pcrel_offset */
1021
07d6d2b8 1022 HOWTO (R_ARM_LDRS_PC_G2, /* type */
4962c51a
MS		 1023 0, /* rightshift */
1024 2, /* size (0 = byte, 1 = short, 2 = long) */
1025 32, /* bitsize */
1026 TRUE, /* pc_relative */
1027 0, /* bitpos */
1028 complain_overflow_dont,/* complain_on_overflow */
1029 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1030 "R_ARM_LDRS_PC_G2", /* name */
4962c51a
MS		 1031 FALSE, /* partial_inplace */
1032 0xffffffff, /* src_mask */
1033 0xffffffff, /* dst_mask */
1034 TRUE), /* pcrel_offset */
1035
07d6d2b8 1036 HOWTO (R_ARM_LDC_PC_G0, /* type */
4962c51a
MS		 1037 0, /* rightshift */
1038 2, /* size (0 = byte, 1 = short, 2 = long) */
1039 32, /* bitsize */
1040 TRUE, /* pc_relative */
1041 0, /* bitpos */
1042 complain_overflow_dont,/* complain_on_overflow */
1043 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1044 "R_ARM_LDC_PC_G0", /* name */
4962c51a
MS		 1045 FALSE, /* partial_inplace */
1046 0xffffffff, /* src_mask */
1047 0xffffffff, /* dst_mask */
1048 TRUE), /* pcrel_offset */
1049
07d6d2b8 1050 HOWTO (R_ARM_LDC_PC_G1, /* type */
4962c51a
MS		 1051 0, /* rightshift */
1052 2, /* size (0 = byte, 1 = short, 2 = long) */
1053 32, /* bitsize */
1054 TRUE, /* pc_relative */
1055 0, /* bitpos */
1056 complain_overflow_dont,/* complain_on_overflow */
1057 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1058 "R_ARM_LDC_PC_G1", /* name */
4962c51a
MS		 1059 FALSE, /* partial_inplace */
1060 0xffffffff, /* src_mask */
1061 0xffffffff, /* dst_mask */
1062 TRUE), /* pcrel_offset */
1063
07d6d2b8 1064 HOWTO (R_ARM_LDC_PC_G2, /* type */
4962c51a
MS		 1065 0, /* rightshift */
1066 2, /* size (0 = byte, 1 = short, 2 = long) */
1067 32, /* bitsize */
1068 TRUE, /* pc_relative */
1069 0, /* bitpos */
1070 complain_overflow_dont,/* complain_on_overflow */
1071 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1072 "R_ARM_LDC_PC_G2", /* name */
4962c51a
MS		 1073 FALSE, /* partial_inplace */
1074 0xffffffff, /* src_mask */
1075 0xffffffff, /* dst_mask */
1076 TRUE), /* pcrel_offset */
1077
07d6d2b8 1078 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
4962c51a
MS		 1079 0, /* rightshift */
1080 2, /* size (0 = byte, 1 = short, 2 = long) */
1081 32, /* bitsize */
1082 TRUE, /* pc_relative */
1083 0, /* bitpos */
1084 complain_overflow_dont,/* complain_on_overflow */
1085 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1086 "R_ARM_ALU_SB_G0_NC", /* name */
4962c51a
MS		 1087 FALSE, /* partial_inplace */
1088 0xffffffff, /* src_mask */
1089 0xffffffff, /* dst_mask */
1090 TRUE), /* pcrel_offset */
1091
07d6d2b8 1092 HOWTO (R_ARM_ALU_SB_G0, /* type */
4962c51a
MS		 1093 0, /* rightshift */
1094 2, /* size (0 = byte, 1 = short, 2 = long) */
1095 32, /* bitsize */
1096 TRUE, /* pc_relative */
1097 0, /* bitpos */
1098 complain_overflow_dont,/* complain_on_overflow */
1099 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1100 "R_ARM_ALU_SB_G0", /* name */
4962c51a
MS		 1101 FALSE, /* partial_inplace */
1102 0xffffffff, /* src_mask */
1103 0xffffffff, /* dst_mask */
1104 TRUE), /* pcrel_offset */
1105
07d6d2b8 1106 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
4962c51a
MS		 1107 0, /* rightshift */
1108 2, /* size (0 = byte, 1 = short, 2 = long) */
1109 32, /* bitsize */
1110 TRUE, /* pc_relative */
1111 0, /* bitpos */
1112 complain_overflow_dont,/* complain_on_overflow */
1113 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1114 "R_ARM_ALU_SB_G1_NC", /* name */
4962c51a
MS		 1115 FALSE, /* partial_inplace */
1116 0xffffffff, /* src_mask */
1117 0xffffffff, /* dst_mask */
1118 TRUE), /* pcrel_offset */
1119
07d6d2b8 1120 HOWTO (R_ARM_ALU_SB_G1, /* type */
4962c51a
MS		 1121 0, /* rightshift */
1122 2, /* size (0 = byte, 1 = short, 2 = long) */
1123 32, /* bitsize */
1124 TRUE, /* pc_relative */
1125 0, /* bitpos */
1126 complain_overflow_dont,/* complain_on_overflow */
1127 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1128 "R_ARM_ALU_SB_G1", /* name */
4962c51a
MS		 1129 FALSE, /* partial_inplace */
1130 0xffffffff, /* src_mask */
1131 0xffffffff, /* dst_mask */
1132 TRUE), /* pcrel_offset */
1133
07d6d2b8 1134 HOWTO (R_ARM_ALU_SB_G2, /* type */
4962c51a
MS		 1135 0, /* rightshift */
1136 2, /* size (0 = byte, 1 = short, 2 = long) */
1137 32, /* bitsize */
1138 TRUE, /* pc_relative */
1139 0, /* bitpos */
1140 complain_overflow_dont,/* complain_on_overflow */
1141 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1142 "R_ARM_ALU_SB_G2", /* name */
4962c51a
MS		 1143 FALSE, /* partial_inplace */
1144 0xffffffff, /* src_mask */
1145 0xffffffff, /* dst_mask */
1146 TRUE), /* pcrel_offset */
1147
07d6d2b8 1148 HOWTO (R_ARM_LDR_SB_G0, /* type */
4962c51a
MS		 1149 0, /* rightshift */
1150 2, /* size (0 = byte, 1 = short, 2 = long) */
1151 32, /* bitsize */
1152 TRUE, /* pc_relative */
1153 0, /* bitpos */
1154 complain_overflow_dont,/* complain_on_overflow */
1155 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1156 "R_ARM_LDR_SB_G0", /* name */
4962c51a
MS		 1157 FALSE, /* partial_inplace */
1158 0xffffffff, /* src_mask */
1159 0xffffffff, /* dst_mask */
1160 TRUE), /* pcrel_offset */
1161
07d6d2b8 1162 HOWTO (R_ARM_LDR_SB_G1, /* type */
4962c51a
MS		 1163 0, /* rightshift */
1164 2, /* size (0 = byte, 1 = short, 2 = long) */
1165 32, /* bitsize */
1166 TRUE, /* pc_relative */
1167 0, /* bitpos */
1168 complain_overflow_dont,/* complain_on_overflow */
1169 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1170 "R_ARM_LDR_SB_G1", /* name */
4962c51a
MS		 1171 FALSE, /* partial_inplace */
1172 0xffffffff, /* src_mask */
1173 0xffffffff, /* dst_mask */
1174 TRUE), /* pcrel_offset */
1175
07d6d2b8 1176 HOWTO (R_ARM_LDR_SB_G2, /* type */
4962c51a
MS		 1177 0, /* rightshift */
1178 2, /* size (0 = byte, 1 = short, 2 = long) */
1179 32, /* bitsize */
1180 TRUE, /* pc_relative */
1181 0, /* bitpos */
1182 complain_overflow_dont,/* complain_on_overflow */
1183 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1184 "R_ARM_LDR_SB_G2", /* name */
4962c51a
MS		 1185 FALSE, /* partial_inplace */
1186 0xffffffff, /* src_mask */
1187 0xffffffff, /* dst_mask */
1188 TRUE), /* pcrel_offset */
1189
07d6d2b8 1190 HOWTO (R_ARM_LDRS_SB_G0, /* type */
4962c51a
MS		 1191 0, /* rightshift */
1192 2, /* size (0 = byte, 1 = short, 2 = long) */
1193 32, /* bitsize */
1194 TRUE, /* pc_relative */
1195 0, /* bitpos */
1196 complain_overflow_dont,/* complain_on_overflow */
1197 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1198 "R_ARM_LDRS_SB_G0", /* name */
4962c51a
MS		 1199 FALSE, /* partial_inplace */
1200 0xffffffff, /* src_mask */
1201 0xffffffff, /* dst_mask */
1202 TRUE), /* pcrel_offset */
1203
07d6d2b8 1204 HOWTO (R_ARM_LDRS_SB_G1, /* type */
4962c51a
MS		 1205 0, /* rightshift */
1206 2, /* size (0 = byte, 1 = short, 2 = long) */
1207 32, /* bitsize */
1208 TRUE, /* pc_relative */
1209 0, /* bitpos */
1210 complain_overflow_dont,/* complain_on_overflow */
1211 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1212 "R_ARM_LDRS_SB_G1", /* name */
4962c51a
MS		 1213 FALSE, /* partial_inplace */
1214 0xffffffff, /* src_mask */
1215 0xffffffff, /* dst_mask */
1216 TRUE), /* pcrel_offset */
1217
07d6d2b8 1218 HOWTO (R_ARM_LDRS_SB_G2, /* type */
4962c51a
MS		 1219 0, /* rightshift */
1220 2, /* size (0 = byte, 1 = short, 2 = long) */
1221 32, /* bitsize */
1222 TRUE, /* pc_relative */
1223 0, /* bitpos */
1224 complain_overflow_dont,/* complain_on_overflow */
1225 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1226 "R_ARM_LDRS_SB_G2", /* name */
4962c51a
MS		 1227 FALSE, /* partial_inplace */
1228 0xffffffff, /* src_mask */
1229 0xffffffff, /* dst_mask */
1230 TRUE), /* pcrel_offset */
1231
07d6d2b8 1232 HOWTO (R_ARM_LDC_SB_G0, /* type */
4962c51a
MS		 1233 0, /* rightshift */
1234 2, /* size (0 = byte, 1 = short, 2 = long) */
1235 32, /* bitsize */
1236 TRUE, /* pc_relative */
1237 0, /* bitpos */
1238 complain_overflow_dont,/* complain_on_overflow */
1239 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1240 "R_ARM_LDC_SB_G0", /* name */
4962c51a
MS		 1241 FALSE, /* partial_inplace */
1242 0xffffffff, /* src_mask */
1243 0xffffffff, /* dst_mask */
1244 TRUE), /* pcrel_offset */
1245
07d6d2b8 1246 HOWTO (R_ARM_LDC_SB_G1, /* type */
4962c51a
MS		 1247 0, /* rightshift */
1248 2, /* size (0 = byte, 1 = short, 2 = long) */
1249 32, /* bitsize */
1250 TRUE, /* pc_relative */
1251 0, /* bitpos */
1252 complain_overflow_dont,/* complain_on_overflow */
1253 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1254 "R_ARM_LDC_SB_G1", /* name */
4962c51a
MS		 1255 FALSE, /* partial_inplace */
1256 0xffffffff, /* src_mask */
1257 0xffffffff, /* dst_mask */
1258 TRUE), /* pcrel_offset */
1259
07d6d2b8 1260 HOWTO (R_ARM_LDC_SB_G2, /* type */
4962c51a
MS		 1261 0, /* rightshift */
1262 2, /* size (0 = byte, 1 = short, 2 = long) */
1263 32, /* bitsize */
1264 TRUE, /* pc_relative */
1265 0, /* bitpos */
1266 complain_overflow_dont,/* complain_on_overflow */
1267 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1268 "R_ARM_LDC_SB_G2", /* name */
4962c51a
MS		 1269 FALSE, /* partial_inplace */
1270 0xffffffff, /* src_mask */
1271 0xffffffff, /* dst_mask */
1272 TRUE), /* pcrel_offset */
1273
1274 /* End of group relocations. */
c19d1205 1275
c19d1205
ZW		 1276 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1277 0, /* rightshift */
1278 2, /* size (0 = byte, 1 = short, 2 = long) */
1279 16, /* bitsize */
1280 FALSE, /* pc_relative */
1281 0, /* bitpos */
1282 complain_overflow_dont,/* complain_on_overflow */
1283 bfd_elf_generic_reloc, /* special_function */
1284 "R_ARM_MOVW_BREL_NC", /* name */
1285 FALSE, /* partial_inplace */
1286 0x0000ffff, /* src_mask */
1287 0x0000ffff, /* dst_mask */
1288 FALSE), /* pcrel_offset */
1289
1290 HOWTO (R_ARM_MOVT_BREL, /* type */
1291 0, /* rightshift */
1292 2, /* size (0 = byte, 1 = short, 2 = long) */
1293 16, /* bitsize */
1294 FALSE, /* pc_relative */
1295 0, /* bitpos */
1296 complain_overflow_bitfield,/* complain_on_overflow */
1297 bfd_elf_generic_reloc, /* special_function */
1298 "R_ARM_MOVT_BREL", /* name */
1299 FALSE, /* partial_inplace */
1300 0x0000ffff, /* src_mask */
1301 0x0000ffff, /* dst_mask */
1302 FALSE), /* pcrel_offset */
1303
1304 HOWTO (R_ARM_MOVW_BREL, /* type */
1305 0, /* rightshift */
1306 2, /* size (0 = byte, 1 = short, 2 = long) */
1307 16, /* bitsize */
1308 FALSE, /* pc_relative */
1309 0, /* bitpos */
1310 complain_overflow_dont,/* complain_on_overflow */
1311 bfd_elf_generic_reloc, /* special_function */
1312 "R_ARM_MOVW_BREL", /* name */
1313 FALSE, /* partial_inplace */
1314 0x0000ffff, /* src_mask */
1315 0x0000ffff, /* dst_mask */
1316 FALSE), /* pcrel_offset */
1317
1318 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1319 0, /* rightshift */
1320 2, /* size (0 = byte, 1 = short, 2 = long) */
1321 16, /* bitsize */
1322 FALSE, /* pc_relative */
1323 0, /* bitpos */
1324 complain_overflow_dont,/* complain_on_overflow */
1325 bfd_elf_generic_reloc, /* special_function */
1326 "R_ARM_THM_MOVW_BREL_NC",/* name */
1327 FALSE, /* partial_inplace */
1328 0x040f70ff, /* src_mask */
1329 0x040f70ff, /* dst_mask */
1330 FALSE), /* pcrel_offset */
1331
1332 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1333 0, /* rightshift */
1334 2, /* size (0 = byte, 1 = short, 2 = long) */
1335 16, /* bitsize */
1336 FALSE, /* pc_relative */
1337 0, /* bitpos */
1338 complain_overflow_bitfield,/* complain_on_overflow */
1339 bfd_elf_generic_reloc, /* special_function */
1340 "R_ARM_THM_MOVT_BREL", /* name */
1341 FALSE, /* partial_inplace */
1342 0x040f70ff, /* src_mask */
1343 0x040f70ff, /* dst_mask */
1344 FALSE), /* pcrel_offset */
1345
1346 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1347 0, /* rightshift */
1348 2, /* size (0 = byte, 1 = short, 2 = long) */
1349 16, /* bitsize */
1350 FALSE, /* pc_relative */
1351 0, /* bitpos */
1352 complain_overflow_dont,/* complain_on_overflow */
1353 bfd_elf_generic_reloc, /* special_function */
1354 "R_ARM_THM_MOVW_BREL", /* name */
1355 FALSE, /* partial_inplace */
1356 0x040f70ff, /* src_mask */
1357 0x040f70ff, /* dst_mask */
1358 FALSE), /* pcrel_offset */
1359
0855e32b
NS		 1360 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1361 0, /* rightshift */
1362 2, /* size (0 = byte, 1 = short, 2 = long) */
1363 32, /* bitsize */
1364 FALSE, /* pc_relative */
1365 0, /* bitpos */
1366 complain_overflow_bitfield,/* complain_on_overflow */
1367 NULL, /* special_function */
1368 "R_ARM_TLS_GOTDESC", /* name */
1369 TRUE, /* partial_inplace */
1370 0xffffffff, /* src_mask */
1371 0xffffffff, /* dst_mask */
1372 FALSE), /* pcrel_offset */
1373
1374 HOWTO (R_ARM_TLS_CALL, /* type */
1375 0, /* rightshift */
1376 2, /* size (0 = byte, 1 = short, 2 = long) */
1377 24, /* bitsize */
1378 FALSE, /* pc_relative */
1379 0, /* bitpos */
1380 complain_overflow_dont,/* complain_on_overflow */
1381 bfd_elf_generic_reloc, /* special_function */
1382 "R_ARM_TLS_CALL", /* name */
1383 FALSE, /* partial_inplace */
1384 0x00ffffff, /* src_mask */
1385 0x00ffffff, /* dst_mask */
1386 FALSE), /* pcrel_offset */
1387
1388 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1389 0, /* rightshift */
1390 2, /* size (0 = byte, 1 = short, 2 = long) */
1391 0, /* bitsize */
1392 FALSE, /* pc_relative */
1393 0, /* bitpos */
1394 complain_overflow_bitfield,/* complain_on_overflow */
1395 bfd_elf_generic_reloc, /* special_function */
1396 "R_ARM_TLS_DESCSEQ", /* name */
1397 FALSE, /* partial_inplace */
1398 0x00000000, /* src_mask */
1399 0x00000000, /* dst_mask */
1400 FALSE), /* pcrel_offset */
1401
1402 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1403 0, /* rightshift */
1404 2, /* size (0 = byte, 1 = short, 2 = long) */
1405 24, /* bitsize */
1406 FALSE, /* pc_relative */
1407 0, /* bitpos */
1408 complain_overflow_dont,/* complain_on_overflow */
1409 bfd_elf_generic_reloc, /* special_function */
1410 "R_ARM_THM_TLS_CALL", /* name */
1411 FALSE, /* partial_inplace */
1412 0x07ff07ff, /* src_mask */
1413 0x07ff07ff, /* dst_mask */
1414 FALSE), /* pcrel_offset */
c19d1205
ZW		 1415
1416 HOWTO (R_ARM_PLT32_ABS, /* type */
1417 0, /* rightshift */
1418 2, /* size (0 = byte, 1 = short, 2 = long) */
1419 32, /* bitsize */
1420 FALSE, /* pc_relative */
1421 0, /* bitpos */
1422 complain_overflow_dont,/* complain_on_overflow */
1423 bfd_elf_generic_reloc, /* special_function */
1424 "R_ARM_PLT32_ABS", /* name */
1425 FALSE, /* partial_inplace */
1426 0xffffffff, /* src_mask */
1427 0xffffffff, /* dst_mask */
1428 FALSE), /* pcrel_offset */
1429
1430 HOWTO (R_ARM_GOT_ABS, /* type */
1431 0, /* rightshift */
1432 2, /* size (0 = byte, 1 = short, 2 = long) */
1433 32, /* bitsize */
1434 FALSE, /* pc_relative */
1435 0, /* bitpos */
1436 complain_overflow_dont,/* complain_on_overflow */
1437 bfd_elf_generic_reloc, /* special_function */
1438 "R_ARM_GOT_ABS", /* name */
1439 FALSE, /* partial_inplace */
1440 0xffffffff, /* src_mask */
1441 0xffffffff, /* dst_mask */
1442 FALSE), /* pcrel_offset */
1443
1444 HOWTO (R_ARM_GOT_PREL, /* type */
1445 0, /* rightshift */
1446 2, /* size (0 = byte, 1 = short, 2 = long) */
1447 32, /* bitsize */
1448 TRUE, /* pc_relative */
1449 0, /* bitpos */
1450 complain_overflow_dont, /* complain_on_overflow */
1451 bfd_elf_generic_reloc, /* special_function */
1452 "R_ARM_GOT_PREL", /* name */
1453 FALSE, /* partial_inplace */
1454 0xffffffff, /* src_mask */
1455 0xffffffff, /* dst_mask */
1456 TRUE), /* pcrel_offset */
1457
1458 HOWTO (R_ARM_GOT_BREL12, /* type */
1459 0, /* rightshift */
1460 2, /* size (0 = byte, 1 = short, 2 = long) */
1461 12, /* bitsize */
1462 FALSE, /* pc_relative */
1463 0, /* bitpos */
1464 complain_overflow_bitfield,/* complain_on_overflow */
1465 bfd_elf_generic_reloc, /* special_function */
1466 "R_ARM_GOT_BREL12", /* name */
1467 FALSE, /* partial_inplace */
1468 0x00000fff, /* src_mask */
1469 0x00000fff, /* dst_mask */
1470 FALSE), /* pcrel_offset */
1471
1472 HOWTO (R_ARM_GOTOFF12, /* type */
1473 0, /* rightshift */
1474 2, /* size (0 = byte, 1 = short, 2 = long) */
1475 12, /* bitsize */
1476 FALSE, /* pc_relative */
1477 0, /* bitpos */
1478 complain_overflow_bitfield,/* complain_on_overflow */
1479 bfd_elf_generic_reloc, /* special_function */
1480 "R_ARM_GOTOFF12", /* name */
1481 FALSE, /* partial_inplace */
1482 0x00000fff, /* src_mask */
1483 0x00000fff, /* dst_mask */
1484 FALSE), /* pcrel_offset */
1485
07d6d2b8 1486 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
c19d1205
ZW		 1487
1488 /* GNU extension to record C++ vtable member usage */
07d6d2b8
AM		 1489 HOWTO (R_ARM_GNU_VTENTRY, /* type */
1490 0, /* rightshift */
1491 2, /* size (0 = byte, 1 = short, 2 = long) */
1492 0, /* bitsize */
1493 FALSE, /* pc_relative */
1494 0, /* bitpos */
99059e56 1495 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8
AM		 1496 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1497 "R_ARM_GNU_VTENTRY", /* name */
1498 FALSE, /* partial_inplace */
1499 0, /* src_mask */
1500 0, /* dst_mask */
1501 FALSE), /* pcrel_offset */
c19d1205
ZW		 1502
1503 /* GNU extension to record C++ vtable hierarchy */
1504 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
07d6d2b8
AM		 1505 0, /* rightshift */
1506 2, /* size (0 = byte, 1 = short, 2 = long) */
1507 0, /* bitsize */
1508 FALSE, /* pc_relative */
1509 0, /* bitpos */
99059e56 1510 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8 1511 NULL, /* special_function */
99059e56 1512 "R_ARM_GNU_VTINHERIT", /* name */
07d6d2b8
AM		 1513 FALSE, /* partial_inplace */
1514 0, /* src_mask */
1515 0, /* dst_mask */
1516 FALSE), /* pcrel_offset */
c19d1205
ZW		 1517
1518 HOWTO (R_ARM_THM_JUMP11, /* type */
1519 1, /* rightshift */
1520 1, /* size (0 = byte, 1 = short, 2 = long) */
1521 11, /* bitsize */
1522 TRUE, /* pc_relative */
1523 0, /* bitpos */
1524 complain_overflow_signed, /* complain_on_overflow */
1525 bfd_elf_generic_reloc, /* special_function */
1526 "R_ARM_THM_JUMP11", /* name */
1527 FALSE, /* partial_inplace */
1528 0x000007ff, /* src_mask */
1529 0x000007ff, /* dst_mask */
1530 TRUE), /* pcrel_offset */
1531
1532 HOWTO (R_ARM_THM_JUMP8, /* type */
1533 1, /* rightshift */
1534 1, /* size (0 = byte, 1 = short, 2 = long) */
1535 8, /* bitsize */
1536 TRUE, /* pc_relative */
1537 0, /* bitpos */
1538 complain_overflow_signed, /* complain_on_overflow */
1539 bfd_elf_generic_reloc, /* special_function */
1540 "R_ARM_THM_JUMP8", /* name */
1541 FALSE, /* partial_inplace */
1542 0x000000ff, /* src_mask */
1543 0x000000ff, /* dst_mask */
1544 TRUE), /* pcrel_offset */
ba93b8ac 1545
c19d1205
ZW		 1546 /* TLS relocations */
1547 HOWTO (R_ARM_TLS_GD32, /* type */
07d6d2b8
AM		 1548 0, /* rightshift */
1549 2, /* size (0 = byte, 1 = short, 2 = long) */
1550 32, /* bitsize */
1551 FALSE, /* pc_relative */
1552 0, /* bitpos */
99059e56
RM		 1553 complain_overflow_bitfield,/* complain_on_overflow */
1554 NULL, /* special_function */
1555 "R_ARM_TLS_GD32", /* name */
1556 TRUE, /* partial_inplace */
1557 0xffffffff, /* src_mask */
1558 0xffffffff, /* dst_mask */
07d6d2b8 1559 FALSE), /* pcrel_offset */
ba93b8ac 1560
ba93b8ac 1561 HOWTO (R_ARM_TLS_LDM32, /* type */
07d6d2b8
AM		 1562 0, /* rightshift */
1563 2, /* size (0 = byte, 1 = short, 2 = long) */
1564 32, /* bitsize */
1565 FALSE, /* pc_relative */
1566 0, /* bitpos */
99059e56
RM		 1567 complain_overflow_bitfield,/* complain_on_overflow */
1568 bfd_elf_generic_reloc, /* special_function */
1569 "R_ARM_TLS_LDM32", /* name */
1570 TRUE, /* partial_inplace */
1571 0xffffffff, /* src_mask */
1572 0xffffffff, /* dst_mask */
07d6d2b8 1573 FALSE), /* pcrel_offset */
ba93b8ac 1574
c19d1205 1575 HOWTO (R_ARM_TLS_LDO32, /* type */
07d6d2b8
AM		 1576 0, /* rightshift */
1577 2, /* size (0 = byte, 1 = short, 2 = long) */
1578 32, /* bitsize */
1579 FALSE, /* pc_relative */
1580 0, /* bitpos */
99059e56
RM		 1581 complain_overflow_bitfield,/* complain_on_overflow */
1582 bfd_elf_generic_reloc, /* special_function */
1583 "R_ARM_TLS_LDO32", /* name */
1584 TRUE, /* partial_inplace */
1585 0xffffffff, /* src_mask */
1586 0xffffffff, /* dst_mask */
07d6d2b8 1587 FALSE), /* pcrel_offset */
ba93b8ac 1588
ba93b8ac 1589 HOWTO (R_ARM_TLS_IE32, /* type */
07d6d2b8
AM		 1590 0, /* rightshift */
1591 2, /* size (0 = byte, 1 = short, 2 = long) */
1592 32, /* bitsize */
1593 FALSE, /* pc_relative */
1594 0, /* bitpos */
99059e56
RM		 1595 complain_overflow_bitfield,/* complain_on_overflow */
1596 NULL, /* special_function */
1597 "R_ARM_TLS_IE32", /* name */
1598 TRUE, /* partial_inplace */
1599 0xffffffff, /* src_mask */
1600 0xffffffff, /* dst_mask */
07d6d2b8 1601 FALSE), /* pcrel_offset */
7f266840 1602
c19d1205 1603 HOWTO (R_ARM_TLS_LE32, /* type */
07d6d2b8
AM		 1604 0, /* rightshift */
1605 2, /* size (0 = byte, 1 = short, 2 = long) */
1606 32, /* bitsize */
1607 FALSE, /* pc_relative */
1608 0, /* bitpos */
99059e56 1609 complain_overflow_bitfield,/* complain_on_overflow */
07d6d2b8 1610 NULL, /* special_function */
99059e56
RM		 1611 "R_ARM_TLS_LE32", /* name */
1612 TRUE, /* partial_inplace */
1613 0xffffffff, /* src_mask */
1614 0xffffffff, /* dst_mask */
07d6d2b8 1615 FALSE), /* pcrel_offset */
7f266840 1616
c19d1205
ZW		 1617 HOWTO (R_ARM_TLS_LDO12, /* type */
1618 0, /* rightshift */
1619 2, /* size (0 = byte, 1 = short, 2 = long) */
1620 12, /* bitsize */
1621 FALSE, /* pc_relative */
7f266840 1622 0, /* bitpos */
c19d1205 1623 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1624 bfd_elf_generic_reloc, /* special_function */
c19d1205 1625 "R_ARM_TLS_LDO12", /* name */
7f266840 1626 FALSE, /* partial_inplace */
c19d1205
ZW		 1627 0x00000fff, /* src_mask */
1628 0x00000fff, /* dst_mask */
1629 FALSE), /* pcrel_offset */
7f266840 1630
c19d1205
ZW		 1631 HOWTO (R_ARM_TLS_LE12, /* type */
1632 0, /* rightshift */
1633 2, /* size (0 = byte, 1 = short, 2 = long) */
1634 12, /* bitsize */
1635 FALSE, /* pc_relative */
7f266840 1636 0, /* bitpos */
c19d1205 1637 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1638 bfd_elf_generic_reloc, /* special_function */
c19d1205 1639 "R_ARM_TLS_LE12", /* name */
7f266840 1640 FALSE, /* partial_inplace */
c19d1205
ZW		 1641 0x00000fff, /* src_mask */
1642 0x00000fff, /* dst_mask */
1643 FALSE), /* pcrel_offset */
7f266840 1644
c19d1205 1645 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1646 0, /* rightshift */
1647 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1648 12, /* bitsize */
1649 FALSE, /* pc_relative */
7f266840 1650 0, /* bitpos */
c19d1205 1651 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1652 bfd_elf_generic_reloc, /* special_function */
c19d1205 1653 "R_ARM_TLS_IE12GP", /* name */
7f266840 1654 FALSE, /* partial_inplace */
c19d1205
ZW		 1655 0x00000fff, /* src_mask */
1656 0x00000fff, /* dst_mask */
1657 FALSE), /* pcrel_offset */
0855e32b 1658
34e77a92 1659 /* 112-127 private relocations. */
0855e32b
NS		 1660 EMPTY_HOWTO (112),
1661 EMPTY_HOWTO (113),
1662 EMPTY_HOWTO (114),
1663 EMPTY_HOWTO (115),
1664 EMPTY_HOWTO (116),
1665 EMPTY_HOWTO (117),
1666 EMPTY_HOWTO (118),
1667 EMPTY_HOWTO (119),
1668 EMPTY_HOWTO (120),
1669 EMPTY_HOWTO (121),
1670 EMPTY_HOWTO (122),
1671 EMPTY_HOWTO (123),
1672 EMPTY_HOWTO (124),
1673 EMPTY_HOWTO (125),
1674 EMPTY_HOWTO (126),
1675 EMPTY_HOWTO (127),
34e77a92
RS		 1676
1677 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1678 EMPTY_HOWTO (128),
1679
1680 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1681 0, /* rightshift */
1682 1, /* size (0 = byte, 1 = short, 2 = long) */
1683 0, /* bitsize */
1684 FALSE, /* pc_relative */
1685 0, /* bitpos */
1686 complain_overflow_bitfield,/* complain_on_overflow */
1687 bfd_elf_generic_reloc, /* special_function */
1688 "R_ARM_THM_TLS_DESCSEQ",/* name */
1689 FALSE, /* partial_inplace */
1690 0x00000000, /* src_mask */
1691 0x00000000, /* dst_mask */
1692 FALSE), /* pcrel_offset */
72d98d16
MG		 1693 EMPTY_HOWTO (130),
1694 EMPTY_HOWTO (131),
1695 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1696 0, /* rightshift. */
1697 1, /* size (0 = byte, 1 = short, 2 = long). */
1698 16, /* bitsize. */
1699 FALSE, /* pc_relative. */
1700 0, /* bitpos. */
1701 complain_overflow_bitfield,/* complain_on_overflow. */
1702 bfd_elf_generic_reloc, /* special_function. */
1703 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1704 FALSE, /* partial_inplace. */
1705 0x00000000, /* src_mask. */
1706 0x00000000, /* dst_mask. */
1707 FALSE), /* pcrel_offset. */
1708 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1709 0, /* rightshift. */
1710 1, /* size (0 = byte, 1 = short, 2 = long). */
1711 16, /* bitsize. */
1712 FALSE, /* pc_relative. */
1713 0, /* bitpos. */
1714 complain_overflow_bitfield,/* complain_on_overflow. */
1715 bfd_elf_generic_reloc, /* special_function. */
1716 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1717 FALSE, /* partial_inplace. */
1718 0x00000000, /* src_mask. */
1719 0x00000000, /* dst_mask. */
1720 FALSE), /* pcrel_offset. */
1721 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1722 0, /* rightshift. */
1723 1, /* size (0 = byte, 1 = short, 2 = long). */
1724 16, /* bitsize. */
1725 FALSE, /* pc_relative. */
1726 0, /* bitpos. */
1727 complain_overflow_bitfield,/* complain_on_overflow. */
1728 bfd_elf_generic_reloc, /* special_function. */
1729 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1730 FALSE, /* partial_inplace. */
1731 0x00000000, /* src_mask. */
1732 0x00000000, /* dst_mask. */
1733 FALSE), /* pcrel_offset. */
1734 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1735 0, /* rightshift. */
1736 1, /* size (0 = byte, 1 = short, 2 = long). */
1737 16, /* bitsize. */
1738 FALSE, /* pc_relative. */
1739 0, /* bitpos. */
1740 complain_overflow_bitfield,/* complain_on_overflow. */
1741 bfd_elf_generic_reloc, /* special_function. */
1742 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1743 FALSE, /* partial_inplace. */
1744 0x00000000, /* src_mask. */
1745 0x00000000, /* dst_mask. */
1746 FALSE), /* pcrel_offset. */
e5d6e09e
AV		 1747 /* Relocations for Armv8.1-M Mainline. */
1748 HOWTO (R_ARM_THM_BF16, /* type. */
1749 0, /* rightshift. */
1750 1, /* size (0 = byte, 1 = short, 2 = long). */
1751 16, /* bitsize. */
1752 TRUE, /* pc_relative. */
1753 0, /* bitpos. */
1754 complain_overflow_dont,/* do not complain_on_overflow. */
1755 bfd_elf_generic_reloc, /* special_function. */
1756 "R_ARM_THM_BF16", /* name. */
1757 FALSE, /* partial_inplace. */
1758 0x001f0ffe, /* src_mask. */
1759 0x001f0ffe, /* dst_mask. */
1760 TRUE), /* pcrel_offset. */
1889da70
AV		 1761 HOWTO (R_ARM_THM_BF12, /* type. */
1762 0, /* rightshift. */
1763 1, /* size (0 = byte, 1 = short, 2 = long). */
1764 12, /* bitsize. */
1765 TRUE, /* pc_relative. */
1766 0, /* bitpos. */
1767 complain_overflow_dont,/* do not complain_on_overflow. */
1768 bfd_elf_generic_reloc, /* special_function. */
1769 "R_ARM_THM_BF12", /* name. */
1770 FALSE, /* partial_inplace. */
1771 0x00010ffe, /* src_mask. */
1772 0x00010ffe, /* dst_mask. */
1773 TRUE), /* pcrel_offset. */
1caf72a5
AV		 1774 HOWTO (R_ARM_THM_BF18, /* type. */
1775 0, /* rightshift. */
1776 1, /* size (0 = byte, 1 = short, 2 = long). */
1777 18, /* bitsize. */
1778 TRUE, /* pc_relative. */
1779 0, /* bitpos. */
1780 complain_overflow_dont,/* do not complain_on_overflow. */
1781 bfd_elf_generic_reloc, /* special_function. */
1782 "R_ARM_THM_BF18", /* name. */
1783 FALSE, /* partial_inplace. */
1784 0x007f0ffe, /* src_mask. */
1785 0x007f0ffe, /* dst_mask. */
1786 TRUE), /* pcrel_offset. */
c19d1205
ZW		 1787};
1788
34e77a92 1789/* 160 onwards: */
5c5a4843 1790static reloc_howto_type elf32_arm_howto_table_2[8] =
34e77a92
RS		 1791{
1792 HOWTO (R_ARM_IRELATIVE, /* type */
07d6d2b8
AM		 1793 0, /* rightshift */
1794 2, /* size (0 = byte, 1 = short, 2 = long) */
1795 32, /* bitsize */
1796 FALSE, /* pc_relative */
1797 0, /* bitpos */
99059e56
RM		 1798 complain_overflow_bitfield,/* complain_on_overflow */
1799 bfd_elf_generic_reloc, /* special_function */
1800 "R_ARM_IRELATIVE", /* name */
1801 TRUE, /* partial_inplace */
1802 0xffffffff, /* src_mask */
1803 0xffffffff, /* dst_mask */
188fd7ae
CL		 1804 FALSE), /* pcrel_offset */
1805 HOWTO (R_ARM_GOTFUNCDESC, /* type */
1806 0, /* rightshift */
1807 2, /* size (0 = byte, 1 = short, 2 = long) */
1808 32, /* bitsize */
1809 FALSE, /* pc_relative */
1810 0, /* bitpos */
1811 complain_overflow_bitfield,/* complain_on_overflow */
1812 bfd_elf_generic_reloc, /* special_function */
1813 "R_ARM_GOTFUNCDESC", /* name */
1814 FALSE, /* partial_inplace */
1815 0, /* src_mask */
1816 0xffffffff, /* dst_mask */
1817 FALSE), /* pcrel_offset */
1818 HOWTO (R_ARM_GOTOFFFUNCDESC, /* type */
1819 0, /* rightshift */
1820 2, /* size (0 = byte, 1 = short, 2 = long) */
1821 32, /* bitsize */
1822 FALSE, /* pc_relative */
1823 0, /* bitpos */
1824 complain_overflow_bitfield,/* complain_on_overflow */
1825 bfd_elf_generic_reloc, /* special_function */
1826 "R_ARM_GOTOFFFUNCDESC",/* name */
1827 FALSE, /* partial_inplace */
1828 0, /* src_mask */
1829 0xffffffff, /* dst_mask */
1830 FALSE), /* pcrel_offset */
1831 HOWTO (R_ARM_FUNCDESC, /* type */
1832 0, /* rightshift */
1833 2, /* size (0 = byte, 1 = short, 2 = long) */
1834 32, /* bitsize */
1835 FALSE, /* pc_relative */
1836 0, /* bitpos */
1837 complain_overflow_bitfield,/* complain_on_overflow */
1838 bfd_elf_generic_reloc, /* special_function */
1839 "R_ARM_FUNCDESC", /* name */
1840 FALSE, /* partial_inplace */
1841 0, /* src_mask */
1842 0xffffffff, /* dst_mask */
1843 FALSE), /* pcrel_offset */
1844 HOWTO (R_ARM_FUNCDESC_VALUE, /* type */
1845 0, /* rightshift */
1846 2, /* size (0 = byte, 1 = short, 2 = long) */
1847 64, /* bitsize */
1848 FALSE, /* pc_relative */
1849 0, /* bitpos */
1850 complain_overflow_bitfield,/* complain_on_overflow */
1851 bfd_elf_generic_reloc, /* special_function */
1852 "R_ARM_FUNCDESC_VALUE",/* name */
1853 FALSE, /* partial_inplace */
1854 0, /* src_mask */
1855 0xffffffff, /* dst_mask */
1856 FALSE), /* pcrel_offset */
5c5a4843
CL		 1857 HOWTO (R_ARM_TLS_GD32_FDPIC, /* type */
1858 0, /* rightshift */
1859 2, /* size (0 = byte, 1 = short, 2 = long) */
1860 32, /* bitsize */
1861 FALSE, /* pc_relative */
1862 0, /* bitpos */
1863 complain_overflow_bitfield,/* complain_on_overflow */
1864 bfd_elf_generic_reloc, /* special_function */
1865 "R_ARM_TLS_GD32_FDPIC",/* name */
1866 FALSE, /* partial_inplace */
1867 0, /* src_mask */
1868 0xffffffff, /* dst_mask */
1869 FALSE), /* pcrel_offset */
1870 HOWTO (R_ARM_TLS_LDM32_FDPIC, /* type */
1871 0, /* rightshift */
1872 2, /* size (0 = byte, 1 = short, 2 = long) */
1873 32, /* bitsize */
1874 FALSE, /* pc_relative */
1875 0, /* bitpos */
1876 complain_overflow_bitfield,/* complain_on_overflow */
1877 bfd_elf_generic_reloc, /* special_function */
1878 "R_ARM_TLS_LDM32_FDPIC",/* name */
1879 FALSE, /* partial_inplace */
1880 0, /* src_mask */
1881 0xffffffff, /* dst_mask */
1882 FALSE), /* pcrel_offset */
1883 HOWTO (R_ARM_TLS_IE32_FDPIC, /* type */
1884 0, /* rightshift */
1885 2, /* size (0 = byte, 1 = short, 2 = long) */
1886 32, /* bitsize */
1887 FALSE, /* pc_relative */
1888 0, /* bitpos */
1889 complain_overflow_bitfield,/* complain_on_overflow */
1890 bfd_elf_generic_reloc, /* special_function */
1891 "R_ARM_TLS_IE32_FDPIC",/* name */
1892 FALSE, /* partial_inplace */
1893 0, /* src_mask */
1894 0xffffffff, /* dst_mask */
1895 FALSE), /* pcrel_offset */
34e77a92 1896};
c19d1205 1897
34e77a92
RS		 1898/* 249-255 extended, currently unused, relocations: */
1899static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1900{
1901 HOWTO (R_ARM_RREL32, /* type */
1902 0, /* rightshift */
1903 0, /* size (0 = byte, 1 = short, 2 = long) */
1904 0, /* bitsize */
1905 FALSE, /* pc_relative */
1906 0, /* bitpos */
1907 complain_overflow_dont,/* complain_on_overflow */
1908 bfd_elf_generic_reloc, /* special_function */
1909 "R_ARM_RREL32", /* name */
1910 FALSE, /* partial_inplace */
1911 0, /* src_mask */
1912 0, /* dst_mask */
1913 FALSE), /* pcrel_offset */
1914
1915 HOWTO (R_ARM_RABS32, /* type */
1916 0, /* rightshift */
1917 0, /* size (0 = byte, 1 = short, 2 = long) */
1918 0, /* bitsize */
1919 FALSE, /* pc_relative */
1920 0, /* bitpos */
1921 complain_overflow_dont,/* complain_on_overflow */
1922 bfd_elf_generic_reloc, /* special_function */
1923 "R_ARM_RABS32", /* name */
1924 FALSE, /* partial_inplace */
1925 0, /* src_mask */
1926 0, /* dst_mask */
1927 FALSE), /* pcrel_offset */
1928
1929 HOWTO (R_ARM_RPC24, /* type */
1930 0, /* rightshift */
1931 0, /* size (0 = byte, 1 = short, 2 = long) */
1932 0, /* bitsize */
1933 FALSE, /* pc_relative */
1934 0, /* bitpos */
1935 complain_overflow_dont,/* complain_on_overflow */
1936 bfd_elf_generic_reloc, /* special_function */
1937 "R_ARM_RPC24", /* name */
1938 FALSE, /* partial_inplace */
1939 0, /* src_mask */
1940 0, /* dst_mask */
1941 FALSE), /* pcrel_offset */
1942
1943 HOWTO (R_ARM_RBASE, /* type */
1944 0, /* rightshift */
1945 0, /* size (0 = byte, 1 = short, 2 = long) */
1946 0, /* bitsize */
1947 FALSE, /* pc_relative */
1948 0, /* bitpos */
1949 complain_overflow_dont,/* complain_on_overflow */
1950 bfd_elf_generic_reloc, /* special_function */
1951 "R_ARM_RBASE", /* name */
1952 FALSE, /* partial_inplace */
1953 0, /* src_mask */
1954 0, /* dst_mask */
1955 FALSE) /* pcrel_offset */
1956};
1957
1958static reloc_howto_type *
1959elf32_arm_howto_from_type (unsigned int r_type)
1960{
906e58ca 1961 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1962 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1963
188fd7ae
CL		 1964 if (r_type >= R_ARM_IRELATIVE
1965 && r_type < R_ARM_IRELATIVE + ARRAY_SIZE (elf32_arm_howto_table_2))
34e77a92
RS		 1966 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1967
c19d1205 1968 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1969 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1970 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1971
c19d1205 1972 return NULL;
7f266840
DJ		 1973}
1974
f3185997
NC		 1975static bfd_boolean
1976elf32_arm_info_to_howto (bfd * abfd, arelent * bfd_reloc,
7f266840
DJ		 1977 Elf_Internal_Rela * elf_reloc)
1978{
1979 unsigned int r_type;
1980
1981 r_type = ELF32_R_TYPE (elf_reloc->r_info);
f3185997
NC		 1982 if ((bfd_reloc->howto = elf32_arm_howto_from_type (r_type)) == NULL)
1983 {
1984 /* xgettext:c-format */
1985 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
1986 abfd, r_type);
1987 bfd_set_error (bfd_error_bad_value);
1988 return FALSE;
1989 }
1990 return TRUE;
7f266840
DJ		 1991}
1992
1993struct elf32_arm_reloc_map
1994 {
1995 bfd_reloc_code_real_type bfd_reloc_val;
07d6d2b8 1996 unsigned char elf_reloc_val;
7f266840
DJ		 1997 };
1998
1999/* All entries in this list must also be present in elf32_arm_howto_table. */
2000static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
2001 {
07d6d2b8 2002 {BFD_RELOC_NONE, R_ARM_NONE},
7f266840 2003 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 2004 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
2005 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
07d6d2b8
AM		 2006 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
2007 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
2008 {BFD_RELOC_32, R_ARM_ABS32},
2009 {BFD_RELOC_32_PCREL, R_ARM_REL32},
2010 {BFD_RELOC_8, R_ARM_ABS8},
2011 {BFD_RELOC_16, R_ARM_ABS16},
2012 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
7f266840 2013 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 2014 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
2015 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
2016 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
2017 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
2018 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
2019 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
07d6d2b8
AM		 2020 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
2021 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
2022 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
2023 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
2024 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
2025 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
2026 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
2027 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
7f266840
DJ		 2028 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
2029 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
2030 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
2031 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac 2032 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
07d6d2b8
AM		 2033 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
2034 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
2035 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
0855e32b 2036 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
07d6d2b8 2037 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
0855e32b 2038 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
07d6d2b8 2039 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 2040 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
2041 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
2042 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
2043 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
2044 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
07d6d2b8
AM		 2045 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
2046 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
2047 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
2048 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
188fd7ae
CL		 2049 {BFD_RELOC_ARM_GOTFUNCDESC, R_ARM_GOTFUNCDESC},
2050 {BFD_RELOC_ARM_GOTOFFFUNCDESC, R_ARM_GOTOFFFUNCDESC},
2051 {BFD_RELOC_ARM_FUNCDESC, R_ARM_FUNCDESC},
2052 {BFD_RELOC_ARM_FUNCDESC_VALUE, R_ARM_FUNCDESC_VALUE},
5c5a4843
CL		 2053 {BFD_RELOC_ARM_TLS_GD32_FDPIC, R_ARM_TLS_GD32_FDPIC},
2054 {BFD_RELOC_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_LDM32_FDPIC},
2055 {BFD_RELOC_ARM_TLS_IE32_FDPIC, R_ARM_TLS_IE32_FDPIC},
c19d1205
ZW		 2056 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
2057 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 2058 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
2059 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
2060 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
2061 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
2062 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
2063 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
2064 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
2065 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 2066 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
2067 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
2068 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
2069 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
2070 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
2071 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
2072 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
2073 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
2074 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
2075 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
2076 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
2077 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
2078 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
2079 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
2080 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
2081 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
2082 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
2083 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
2084 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
2085 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
2086 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
2087 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
2088 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
2089 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
2090 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
2091 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
2092 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 2093 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 2094 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
2095 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
2096 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
2097 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
e5d6e09e 2098 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC},
1caf72a5 2099 {BFD_RELOC_ARM_THUMB_BF17, R_ARM_THM_BF16},
1889da70 2100 {BFD_RELOC_ARM_THUMB_BF13, R_ARM_THM_BF12},
1caf72a5 2101 {BFD_RELOC_ARM_THUMB_BF19, R_ARM_THM_BF18}
7f266840
DJ		 2102 };
2103
2104static reloc_howto_type *
f1c71a59
ZW		 2105elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2106 bfd_reloc_code_real_type code)
7f266840
DJ		 2107{
2108 unsigned int i;
8029a119 2109
906e58ca 2110 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 2111 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
2112 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 2113
c19d1205 2114 return NULL;
7f266840
DJ		 2115}
2116
157090f7
AM		 2117static reloc_howto_type *
2118elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2119 const char *r_name)
2120{
2121 unsigned int i;
2122
906e58ca 2123 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 2124 if (elf32_arm_howto_table_1[i].name != NULL
2125 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
2126 return &elf32_arm_howto_table_1[i];
2127
906e58ca 2128 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 2129 if (elf32_arm_howto_table_2[i].name != NULL
2130 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
2131 return &elf32_arm_howto_table_2[i];
2132
34e77a92
RS		 2133 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
2134 if (elf32_arm_howto_table_3[i].name != NULL
2135 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
2136 return &elf32_arm_howto_table_3[i];
2137
157090f7
AM		 2138 return NULL;
2139}
2140
906e58ca
NC		 2141/* Support for core dump NOTE sections. */
2142
7f266840 2143static bfd_boolean
f1c71a59 2144elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2145{
2146 int offset;
2147 size_t size;
2148
2149 switch (note->descsz)
2150 {
2151 default:
2152 return FALSE;
2153
8029a119 2154 case 148: /* Linux/ARM 32-bit. */
7f266840 2155 /* pr_cursig */
228e534f 2156 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2157
2158 /* pr_pid */
228e534f 2159 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2160
2161 /* pr_reg */
2162 offset = 72;
2163 size = 72;
2164
2165 break;
2166 }
2167
2168 /* Make a ".reg/999" section. */
2169 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2170 size, note->descpos + offset);
2171}
2172
2173static bfd_boolean
f1c71a59 2174elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2175{
2176 switch (note->descsz)
2177 {
2178 default:
2179 return FALSE;
2180
8029a119 2181 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2182 elf_tdata (abfd)->core->pid
4395ee08 2183 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2184 elf_tdata (abfd)->core->program
7f266840 2185 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2186 elf_tdata (abfd)->core->command
7f266840
DJ		 2187 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2188 }
2189
2190 /* Note that for some reason, a spurious space is tacked
2191 onto the end of the args in some (at least one anyway)
2192 implementations, so strip it off if it exists. */
7f266840 2193 {
228e534f 2194 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2195 int n = strlen (command);
2196
2197 if (0 < n && command[n - 1] == ' ')
2198 command[n - 1] = '\0';
2199 }
2200
2201 return TRUE;
2202}
2203
1f20dca5
UW		 2204static char *
2205elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2206 int note_type, ...)
2207{
2208 switch (note_type)
2209 {
2210 default:
2211 return NULL;
2212
2213 case NT_PRPSINFO:
2214 {
602f1657 2215 char data[124] ATTRIBUTE_NONSTRING;
1f20dca5
UW		 2216 va_list ap;
2217
2218 va_start (ap, note_type);
2219 memset (data, 0, sizeof (data));
2220 strncpy (data + 28, va_arg (ap, const char *), 16);
be3e27bb 2221#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2222 DIAGNOSTIC_PUSH;
be3e27bb 2223 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
95da9854
L		 2224 -Wstringop-truncation:
2225 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2226 */
95da9854
L		 2227 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2228#endif
1f20dca5 2229 strncpy (data + 44, va_arg (ap, const char *), 80);
be3e27bb 2230#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2231 DIAGNOSTIC_POP;
fe75810f 2232#endif
1f20dca5
UW		 2233 va_end (ap);
2234
2235 return elfcore_write_note (abfd, buf, bufsiz,
2236 "CORE", note_type, data, sizeof (data));
2237 }
2238
2239 case NT_PRSTATUS:
2240 {
2241 char data[148];
2242 va_list ap;
2243 long pid;
2244 int cursig;
2245 const void *greg;
2246
2247 va_start (ap, note_type);
2248 memset (data, 0, sizeof (data));
2249 pid = va_arg (ap, long);
2250 bfd_put_32 (abfd, pid, data + 24);
2251 cursig = va_arg (ap, int);
2252 bfd_put_16 (abfd, cursig, data + 12);
2253 greg = va_arg (ap, const void *);
2254 memcpy (data + 72, greg, 72);
2255 va_end (ap);
2256
2257 return elfcore_write_note (abfd, buf, bufsiz,
2258 "CORE", note_type, data, sizeof (data));
2259 }
2260 }
2261}
2262
07d6d2b8
AM		 2263#define TARGET_LITTLE_SYM arm_elf32_le_vec
2264#define TARGET_LITTLE_NAME "elf32-littlearm"
2265#define TARGET_BIG_SYM arm_elf32_be_vec
2266#define TARGET_BIG_NAME "elf32-bigarm"
7f266840
DJ		 2267
2268#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2269#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2270#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2271
252b5132
RH		 2272typedef unsigned long int insn32;
2273typedef unsigned short int insn16;
2274
3a4a14e9
PB		 2275/* In lieu of proper flags, assume all EABIv4 or later objects are
2276 interworkable. */
57e8b36a 2277#define INTERWORK_FLAG(abfd) \
3a4a14e9 2278 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2279 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2280 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2281
252b5132
RH		 2282/* The linker script knows the section names for placement.
2283 The entry_names are used to do simple name mangling on the stubs.
2284 Given a function name, and its type, the stub can be found. The
9b485d32 2285 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2286#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2287#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2288
2289#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2290#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2291
c7b8f16e
JB		 2292#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2293#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2294
a504d23a
LA		 2295#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2296#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2297
845b51d6
PB		 2298#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2299#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2300
7413f23f
DJ		 2301#define STUB_ENTRY_NAME "__%s_veneer"
2302
4ba2ef8f
TP		 2303#define CMSE_PREFIX "__acle_se_"
2304
4d83e8d9
CL		 2305#define CMSE_STUB_NAME ".gnu.sgstubs"
2306
252b5132
RH		 2307/* The name of the dynamic interpreter. This is put in the .interp
2308 section. */
2309#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2310
cb10292c
CL		 2311/* FDPIC default stack size. */
2312#define DEFAULT_STACK_SIZE 0x8000
2313
0855e32b 2314static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2315{
2316 0xe08e0000, /* add r0, lr, r0 */
2317 0xe5901004, /* ldr r1, [r0,#4] */
2318 0xe12fff11, /* bx r1 */
2319};
0855e32b
NS		 2320
2321static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2322{
2323 0xe52d2004, /* push {r2} */
2324 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2325 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2326 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2327 0xe081100f, /* 2: add r1, pc */
2328 0xe12fff12, /* bx r2 */
2329 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2330 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2331 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2332};
0855e32b 2333
b4e87f2c
TC		 2334/* NOTE: [Thumb nop sequence]
2335 When adding code that transitions from Thumb to Arm the instruction that
2336 should be used for the alignment padding should be 0xe7fd (b .-2) instead of
2337 a nop for performance reasons. */
2338
7801f98f
CL		 2339/* ARM FDPIC PLT entry. */
2340/* The last 5 words contain PLT lazy fragment code and data. */
2341static const bfd_vma elf32_arm_fdpic_plt_entry [] =
2342 {
2343 0xe59fc008, /* ldr r12, .L1 */
2344 0xe08cc009, /* add r12, r12, r9 */
2345 0xe59c9004, /* ldr r9, [r12, #4] */
2346 0xe59cf000, /* ldr pc, [r12] */
2347 0x00000000, /* L1. .word foo(GOTOFFFUNCDESC) */
2348 0x00000000, /* L1. .word foo(funcdesc_value_reloc_offset) */
2349 0xe51fc00c, /* ldr r12, [pc, #-12] */
2350 0xe92d1000, /* push {r12} */
2351 0xe599c004, /* ldr r12, [r9, #4] */
2352 0xe599f000, /* ldr pc, [r9] */
2353 };
2354
59029f57
CL		 2355/* Thumb FDPIC PLT entry. */
2356/* The last 5 words contain PLT lazy fragment code and data. */
2357static const bfd_vma elf32_arm_fdpic_thumb_plt_entry [] =
2358 {
2359 0xc00cf8df, /* ldr.w r12, .L1 */
2360 0x0c09eb0c, /* add.w r12, r12, r9 */
2361 0x9004f8dc, /* ldr.w r9, [r12, #4] */
2362 0xf000f8dc, /* ldr.w pc, [r12] */
2363 0x00000000, /* .L1 .word foo(GOTOFFFUNCDESC) */
2364 0x00000000, /* .L2 .word foo(funcdesc_value_reloc_offset) */
2365 0xc008f85f, /* ldr.w r12, .L2 */
2366 0xcd04f84d, /* push {r12} */
2367 0xc004f8d9, /* ldr.w r12, [r9, #4] */
2368 0xf000f8d9, /* ldr.w pc, [r9] */
2369 };
2370
5e681ec4
PB		 2371#ifdef FOUR_WORD_PLT
2372
252b5132
RH		 2373/* The first entry in a procedure linkage table looks like
2374 this. It is set up so that any shared library function that is
59f2c4e7 2375 called before the relocation has been set up calls the dynamic
9b485d32 2376 linker first. */
e5a52504 2377static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2378{
2379 0xe52de004, /* str lr, [sp, #-4]! */
2380 0xe59fe010, /* ldr lr, [pc, #16] */
2381 0xe08fe00e, /* add lr, pc, lr */
2382 0xe5bef008, /* ldr pc, [lr, #8]! */
2383};
5e681ec4
PB		 2384
2385/* Subsequent entries in a procedure linkage table look like
2386 this. */
e5a52504 2387static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2388{
2389 0xe28fc600, /* add ip, pc, #NN */
2390 0xe28cca00, /* add ip, ip, #NN */
2391 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2392 0x00000000, /* unused */
2393};
5e681ec4 2394
eed94f8f 2395#else /* not FOUR_WORD_PLT */
5e681ec4 2396
5e681ec4
PB		 2397/* The first entry in a procedure linkage table looks like
2398 this. It is set up so that any shared library function that is
2399 called before the relocation has been set up calls the dynamic
2400 linker first. */
e5a52504 2401static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb 2402{
07d6d2b8
AM		 2403 0xe52de004, /* str lr, [sp, #-4]! */
2404 0xe59fe004, /* ldr lr, [pc, #4] */
2405 0xe08fe00e, /* add lr, pc, lr */
2406 0xe5bef008, /* ldr pc, [lr, #8]! */
2407 0x00000000, /* &GOT[0] - . */
b38cadfb 2408};
252b5132 2409
1db37fe6
YG		 2410/* By default subsequent entries in a procedure linkage table look like
2411 this. Offsets that don't fit into 28 bits will cause link error. */
2412static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2413{
2414 0xe28fc600, /* add ip, pc, #0xNN00000 */
2415 0xe28cca00, /* add ip, ip, #0xNN000 */
2416 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2417};
5e681ec4 2418
1db37fe6
YG		 2419/* When explicitly asked, we'll use this "long" entry format
2420 which can cope with arbitrary displacements. */
2421static const bfd_vma elf32_arm_plt_entry_long [] =
2422{
07d6d2b8
AM		 2423 0xe28fc200, /* add ip, pc, #0xN0000000 */
2424 0xe28cc600, /* add ip, ip, #0xNN00000 */
1db37fe6
YG		 2425 0xe28cca00, /* add ip, ip, #0xNN000 */
2426 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2427};
2428
2429static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2430
eed94f8f
NC		 2431#endif /* not FOUR_WORD_PLT */
2432
2433/* The first entry in a procedure linkage table looks like this.
2434 It is set up so that any shared library function that is called before the
2435 relocation has been set up calls the dynamic linker first. */
2436static const bfd_vma elf32_thumb2_plt0_entry [] =
2437{
2438 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2439 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2440 0xf8dfb500, /* push {lr} */
2441 0x44fee008, /* ldr.w lr, [pc, #8] */
2442 /* add lr, pc */
eed94f8f 2443 0xff08f85e, /* ldr.w pc, [lr, #8]! */
07d6d2b8 2444 0x00000000, /* &GOT[0] - . */
eed94f8f
NC		 2445};
2446
2447/* Subsequent entries in a procedure linkage table for thumb only target
2448 look like this. */
2449static const bfd_vma elf32_thumb2_plt_entry [] =
2450{
2451 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2452 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2453 0x0c00f240, /* movw ip, #0xNNNN */
2454 0x0c00f2c0, /* movt ip, #0xNNNN */
2455 0xf8dc44fc, /* add ip, pc */
b4e87f2c
TC		 2456 0xe7fdf000 /* ldr.w pc, [ip] */
2457 /* b .-2 */
eed94f8f 2458};
252b5132 2459
00a97672
RS		 2460/* The format of the first entry in the procedure linkage table
2461 for a VxWorks executable. */
2462static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb 2463{
07d6d2b8
AM		 2464 0xe52dc008, /* str ip,[sp,#-8]! */
2465 0xe59fc000, /* ldr ip,[pc] */
2466 0xe59cf008, /* ldr pc,[ip,#8] */
2467 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
b38cadfb 2468};
00a97672
RS		 2469
2470/* The format of subsequent entries in a VxWorks executable. */
2471static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb 2472{
07d6d2b8
AM		 2473 0xe59fc000, /* ldr ip,[pc] */
2474 0xe59cf000, /* ldr pc,[ip] */
2475 0x00000000, /* .long @got */
2476 0xe59fc000, /* ldr ip,[pc] */
2477 0xea000000, /* b _PLT */
2478 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2479};
00a97672
RS		 2480
2481/* The format of entries in a VxWorks shared library. */
2482static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb 2483{
07d6d2b8
AM		 2484 0xe59fc000, /* ldr ip,[pc] */
2485 0xe79cf009, /* ldr pc,[ip,r9] */
2486 0x00000000, /* .long @got */
2487 0xe59fc000, /* ldr ip,[pc] */
2488 0xe599f008, /* ldr pc,[r9,#8] */
2489 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2490};
00a97672 2491
b7693d02
DJ		 2492/* An initial stub used if the PLT entry is referenced from Thumb code. */
2493#define PLT_THUMB_STUB_SIZE 4
2494static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2495{
2496 0x4778, /* bx pc */
b4e87f2c 2497 0xe7fd /* b .-2 */
b38cadfb 2498};
b7693d02 2499
e5a52504
MM		 2500/* The entries in a PLT when using a DLL-based target with multiple
2501 address spaces. */
906e58ca 2502static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb 2503{
07d6d2b8
AM		 2504 0xe51ff004, /* ldr pc, [pc, #-4] */
2505 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
b38cadfb
NC		 2506};
2507
2508/* The first entry in a procedure linkage table looks like
2509 this. It is set up so that any shared library function that is
2510 called before the relocation has been set up calls the dynamic
2511 linker first. */
2512static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2513{
2514 /* First bundle: */
2515 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2516 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2517 0xe08cc00f, /* add ip, ip, pc */
2518 0xe52dc008, /* str ip, [sp, #-8]! */
2519 /* Second bundle: */
edccdf7c
RM		 2520 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2521 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2522 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2523 0xe12fff1c, /* bx ip */
b38cadfb 2524 /* Third bundle: */
edccdf7c
RM		 2525 0xe320f000, /* nop */
2526 0xe320f000, /* nop */
2527 0xe320f000, /* nop */
b38cadfb
NC		 2528 /* .Lplt_tail: */
2529 0xe50dc004, /* str ip, [sp, #-4] */
2530 /* Fourth bundle: */
edccdf7c
RM		 2531 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2532 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2533 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2534 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2535};
2536#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2537
2538/* Subsequent entries in a procedure linkage table look like this. */
2539static const bfd_vma elf32_arm_nacl_plt_entry [] =
2540{
2541 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2542 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2543 0xe08cc00f, /* add ip, ip, pc */
2544 0xea000000, /* b .Lplt_tail */
2545};
e5a52504 2546
906e58ca
NC		 2547#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2548#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2549#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2550#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2551#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2552#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2553#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2554#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2555
461a49ca 2556enum stub_insn_type
b38cadfb
NC		 2557{
2558 THUMB16_TYPE = 1,
2559 THUMB32_TYPE,
2560 ARM_TYPE,
2561 DATA_TYPE
2562};
461a49ca 2563
48229727
JB		 2564#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2565/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2566 is inserted in arm_build_one_stub(). */
2567#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2568#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2569#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2570#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2571#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2572#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2573#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2574#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2575
2576typedef struct
2577{
07d6d2b8 2578 bfd_vma data;
b38cadfb 2579 enum stub_insn_type type;
07d6d2b8
AM		 2580 unsigned int r_type;
2581 int reloc_addend;
461a49ca
DJ		 2582} insn_sequence;
2583
b4e87f2c
TC		 2584/* See note [Thumb nop sequence] when adding a veneer. */
2585
fea2b4d6
CL		 2586/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2587 to reach the stub if necessary. */
461a49ca 2588static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb 2589{
07d6d2b8 2590 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2591 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2592};
906e58ca 2593
fea2b4d6
CL		 2594/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2595 available. */
461a49ca 2596static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb 2597{
07d6d2b8
AM		 2598 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2599 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2600 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2601};
906e58ca 2602
d3626fb0 2603/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2604static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb 2605{
07d6d2b8
AM		 2606 THUMB16_INSN (0xb401), /* push {r0} */
2607 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2608 THUMB16_INSN (0x4684), /* mov ip, r0 */
2609 THUMB16_INSN (0xbc01), /* pop {r0} */
2610 THUMB16_INSN (0x4760), /* bx ip */
2611 THUMB16_INSN (0xbf00), /* nop */
b38cadfb
NC		 2612 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2613};
906e58ca 2614
80c135e5
TP		 2615/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2616static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2617{
07d6d2b8 2618 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
80c135e5
TP		 2619 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2620};
2621
d5a67c02
AV		 2622/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2623 M-profile architectures. */
2624static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2625{
2626 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2627 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
07d6d2b8 2628 THUMB16_INSN (0x4760), /* bx ip */
d5a67c02
AV		 2629};
2630
d3626fb0
CL		 2631/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2632 allowed. */
2633static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb 2634{
07d6d2b8 2635 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2636 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2637 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2638 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2639 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2640};
d3626fb0 2641
fea2b4d6
CL		 2642/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2643 available. */
461a49ca 2644static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb 2645{
07d6d2b8 2646 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2647 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8 2648 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2649 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2650};
906e58ca 2651
fea2b4d6
CL		 2652/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2653 one, when the destination is close enough. */
461a49ca 2654static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb 2655{
07d6d2b8 2656 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2657 THUMB16_INSN (0xe7fd), /* b .-2 */
b38cadfb
NC		 2658 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2659};
c820be07 2660
cf3eccff 2661/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2662 blx to reach the stub if necessary. */
cf3eccff 2663static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb 2664{
07d6d2b8
AM		 2665 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2666 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
b38cadfb
NC		 2667 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2668};
906e58ca 2669
cf3eccff
DJ		 2670/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2671 blx to reach the stub if necessary. We can not add into pc;
2672 it is not guaranteed to mode switch (different in ARMv6 and
2673 ARMv7). */
2674static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb 2675{
07d6d2b8
AM		 2676 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2677 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2678 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2679 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2680};
cf3eccff 2681
ebe24dd4
CL		 2682/* V4T ARM -> ARM long branch stub, PIC. */
2683static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb 2684{
07d6d2b8
AM		 2685 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2686 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2687 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2688 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2689};
ebe24dd4
CL		 2690
2691/* V4T Thumb -> ARM long branch stub, PIC. */
2692static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb 2693{
07d6d2b8 2694 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2695 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2696 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2697 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
b38cadfb
NC		 2698 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2699};
ebe24dd4 2700
d3626fb0
CL		 2701/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2702 architectures. */
ebe24dd4 2703static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb 2704{
07d6d2b8
AM		 2705 THUMB16_INSN (0xb401), /* push {r0} */
2706 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2707 THUMB16_INSN (0x46fc), /* mov ip, pc */
2708 THUMB16_INSN (0x4484), /* add ip, r0 */
2709 THUMB16_INSN (0xbc01), /* pop {r0} */
2710 THUMB16_INSN (0x4760), /* bx ip */
b38cadfb
NC		 2711 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2712};
ebe24dd4 2713
d3626fb0
CL		 2714/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2715 allowed. */
2716static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb 2717{
07d6d2b8 2718 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2719 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2720 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2721 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2722 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2723 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2724};
d3626fb0 2725
0855e32b
NS		 2726/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2727 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2728static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2729{
07d6d2b8
AM		 2730 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2731 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
b38cadfb 2732 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2733};
2734
2735/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2736 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2737static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2738{
07d6d2b8 2739 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2740 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2741 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2742 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
b38cadfb 2743 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2744};
2745
7a89b94e
NC		 2746/* NaCl ARM -> ARM long branch stub. */
2747static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2748{
2749 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2750 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2751 ARM_INSN (0xe12fff1c), /* bx ip */
2752 ARM_INSN (0xe320f000), /* nop */
2753 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2754 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2755 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2756 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2757};
2758
2759/* NaCl ARM -> ARM long branch stub, PIC. */
2760static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2761{
2762 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
07d6d2b8 2763 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
7a89b94e 2764 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2765 ARM_INSN (0xe12fff1c), /* bx ip */
2766 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2767 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2768 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2769 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2770};
2771
4ba2ef8f
TP		 2772/* Stub used for transition to secure state (aka SG veneer). */
2773static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2774{
2775 THUMB32_INSN (0xe97fe97f), /* sg. */
2776 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2777};
2778
7a89b94e 2779
48229727
JB		 2780/* Cortex-A8 erratum-workaround stubs. */
2781
2782/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2783 can't use a conditional branch to reach this stub). */
2784
2785static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb 2786{
07d6d2b8 2787 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
b38cadfb
NC		 2788 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2789 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2790};
48229727
JB		 2791
2792/* Stub used for b.w and bl.w instructions. */
2793
2794static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2795{
2796 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2797};
48229727
JB		 2798
2799static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2800{
2801 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2802};
48229727
JB		 2803
2804/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2805 instruction (which switches to ARM mode) to point to this stub. Jump to the
2806 real destination using an ARM-mode branch. */
2807
2808static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2809{
2810 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2811};
48229727 2812
9553db3c
NC		 2813/* For each section group there can be a specially created linker section
2814 to hold the stubs for that group. The name of the stub section is based
2815 upon the name of another section within that group with the suffix below
2816 applied.
2817
2818 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2819 create what appeared to be a linker stub section when it actually
2820 contained user code/data. For example, consider this fragment:
b38cadfb 2821
9553db3c
NC		 2822 const char * stubborn_problems[] = { "np" };
2823
2824 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2825 section called:
2826
2827 .data.rel.local.stubborn_problems
2828
2829 This then causes problems in arm32_arm_build_stubs() as it triggers:
2830
2831 // Ignore non-stub sections.
2832 if (!strstr (stub_sec->name, STUB_SUFFIX))
2833 continue;
2834
2835 And so the section would be ignored instead of being processed. Hence
2836 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2837 C identifier. */
2838#define STUB_SUFFIX ".__stub"
906e58ca 2839
738a79f6
CL		 2840/* One entry per long/short branch stub defined above. */
2841#define DEF_STUBS \
2842 DEF_STUB(long_branch_any_any) \
2843 DEF_STUB(long_branch_v4t_arm_thumb) \
2844 DEF_STUB(long_branch_thumb_only) \
2845 DEF_STUB(long_branch_v4t_thumb_thumb) \
2846 DEF_STUB(long_branch_v4t_thumb_arm) \
2847 DEF_STUB(short_branch_v4t_thumb_arm) \
2848 DEF_STUB(long_branch_any_arm_pic) \
2849 DEF_STUB(long_branch_any_thumb_pic) \
2850 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2851 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2852 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2853 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2854 DEF_STUB(long_branch_any_tls_pic) \
2855 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2856 DEF_STUB(long_branch_arm_nacl) \
2857 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2858 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2859 DEF_STUB(a8_veneer_b_cond) \
2860 DEF_STUB(a8_veneer_b) \
2861 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2862 DEF_STUB(a8_veneer_blx) \
2863 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2864 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2865
2866#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2867enum elf32_arm_stub_type
2868{
906e58ca 2869 arm_stub_none,
738a79f6 2870 DEF_STUBS
4f4faa4d 2871 max_stub_type
738a79f6
CL		 2872};
2873#undef DEF_STUB
2874
8d9d9490
TP		 2875/* Note the first a8_veneer type. */
2876const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2877
738a79f6
CL		 2878typedef struct
2879{
d3ce72d0 2880 const insn_sequence* template_sequence;
738a79f6
CL		 2881 int template_size;
2882} stub_def;
2883
2884#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2885static const stub_def stub_definitions[] =
2886{
738a79f6
CL		 2887 {NULL, 0},
2888 DEF_STUBS
906e58ca
NC		 2889};
2890
2891struct elf32_arm_stub_hash_entry
2892{
2893 /* Base hash table entry structure. */
2894 struct bfd_hash_entry root;
2895
2896 /* The stub section. */
2897 asection *stub_sec;
2898
2899 /* Offset within stub_sec of the beginning of this stub. */
2900 bfd_vma stub_offset;
2901
2902 /* Given the symbol's value and its section we can determine its final
2903 value when building the stubs (so the stub knows where to jump). */
2904 bfd_vma target_value;
2905 asection *target_section;
2906
8d9d9490
TP		 2907 /* Same as above but for the source of the branch to the stub. Used for
2908 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2909 such, source section does not need to be recorded since Cortex-A8 erratum
2910 workaround stubs are only generated when both source and target are in the
2911 same section. */
2912 bfd_vma source_value;
48229727
JB		 2913
2914 /* The instruction which caused this stub to be generated (only valid for
2915 Cortex-A8 erratum workaround stubs at present). */
2916 unsigned long orig_insn;
2917
461a49ca 2918 /* The stub type. */
906e58ca 2919 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2920 /* Its encoding size in bytes. */
2921 int stub_size;
2922 /* Its template. */
2923 const insn_sequence *stub_template;
2924 /* The size of the template (number of entries). */
2925 int stub_template_size;
906e58ca
NC		 2926
2927 /* The symbol table entry, if any, that this was derived from. */
2928 struct elf32_arm_link_hash_entry *h;
2929
35fc36a8
RS		 2930 /* Type of branch. */
2931 enum arm_st_branch_type branch_type;
906e58ca
NC		 2932
2933 /* Where this stub is being called from, or, in the case of combined
2934 stub sections, the first input section in the group. */
2935 asection *id_sec;
7413f23f
DJ		 2936
2937 /* The name for the local symbol at the start of this stub. The
2938 stub name in the hash table has to be unique; this does not, so
2939 it can be friendlier. */
2940 char *output_name;
906e58ca
NC		 2941};
2942
e489d0ae
PB		 2943/* Used to build a map of a section. This is required for mixed-endian
2944 code/data. */
2945
2946typedef struct elf32_elf_section_map
2947{
2948 bfd_vma vma;
2949 char type;
2950}
2951elf32_arm_section_map;
2952
c7b8f16e
JB		 2953/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2954
2955typedef enum
2956{
2957 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2958 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2959 VFP11_ERRATUM_ARM_VENEER,
2960 VFP11_ERRATUM_THUMB_VENEER
2961}
2962elf32_vfp11_erratum_type;
2963
2964typedef struct elf32_vfp11_erratum_list
2965{
2966 struct elf32_vfp11_erratum_list *next;
2967 bfd_vma vma;
2968 union
2969 {
2970 struct
2971 {
2972 struct elf32_vfp11_erratum_list *veneer;
2973 unsigned int vfp_insn;
2974 } b;
2975 struct
2976 {
2977 struct elf32_vfp11_erratum_list *branch;
2978 unsigned int id;
2979 } v;
2980 } u;
2981 elf32_vfp11_erratum_type type;
2982}
2983elf32_vfp11_erratum_list;
2984
a504d23a
LA		 2985/* Information about a STM32L4XX erratum veneer, or a branch to such a
2986 veneer. */
2987typedef enum
2988{
2989 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2990 STM32L4XX_ERRATUM_VENEER
2991}
2992elf32_stm32l4xx_erratum_type;
2993
2994typedef struct elf32_stm32l4xx_erratum_list
2995{
2996 struct elf32_stm32l4xx_erratum_list *next;
2997 bfd_vma vma;
2998 union
2999 {
3000 struct
3001 {
3002 struct elf32_stm32l4xx_erratum_list *veneer;
3003 unsigned int insn;
3004 } b;
3005 struct
3006 {
3007 struct elf32_stm32l4xx_erratum_list *branch;
3008 unsigned int id;
3009 } v;
3010 } u;
3011 elf32_stm32l4xx_erratum_type type;
3012}
3013elf32_stm32l4xx_erratum_list;
3014
2468f9c9
PB		 3015typedef enum
3016{
3017 DELETE_EXIDX_ENTRY,
3018 INSERT_EXIDX_CANTUNWIND_AT_END
3019}
3020arm_unwind_edit_type;
3021
3022/* A (sorted) list of edits to apply to an unwind table. */
3023typedef struct arm_unwind_table_edit
3024{
3025 arm_unwind_edit_type type;
3026 /* Note: we sometimes want to insert an unwind entry corresponding to a
3027 section different from the one we're currently writing out, so record the
3028 (text) section this edit relates to here. */
3029 asection *linked_section;
3030 unsigned int index;
3031 struct arm_unwind_table_edit *next;
3032}
3033arm_unwind_table_edit;
3034
8e3de13a 3035typedef struct _arm_elf_section_data
e489d0ae 3036{
2468f9c9 3037 /* Information about mapping symbols. */
e489d0ae 3038 struct bfd_elf_section_data elf;
8e3de13a 3039 unsigned int mapcount;
c7b8f16e 3040 unsigned int mapsize;
e489d0ae 3041 elf32_arm_section_map *map;
2468f9c9 3042 /* Information about CPU errata. */
c7b8f16e
JB		 3043 unsigned int erratumcount;
3044 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 3045 unsigned int stm32l4xx_erratumcount;
3046 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 3047 unsigned int additional_reloc_count;
2468f9c9
PB		 3048 /* Information about unwind tables. */
3049 union
3050 {
3051 /* Unwind info attached to a text section. */
3052 struct
3053 {
3054 asection *arm_exidx_sec;
3055 } text;
3056
3057 /* Unwind info attached to an .ARM.exidx section. */
3058 struct
3059 {
3060 arm_unwind_table_edit *unwind_edit_list;
3061 arm_unwind_table_edit *unwind_edit_tail;
3062 } exidx;
3063 } u;
8e3de13a
NC		 3064}
3065_arm_elf_section_data;
e489d0ae
PB		 3066
3067#define elf32_arm_section_data(sec) \
8e3de13a 3068 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 3069
48229727
JB		 3070/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3071 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3072 so may be created multiple times: we use an array of these entries whilst
3073 relaxing which we can refresh easily, then create stubs for each potentially
3074 erratum-triggering instruction once we've settled on a solution. */
3075
b38cadfb
NC		 3076struct a8_erratum_fix
3077{
48229727
JB		 3078 bfd *input_bfd;
3079 asection *section;
3080 bfd_vma offset;
8d9d9490 3081 bfd_vma target_offset;
48229727
JB		 3082 unsigned long orig_insn;
3083 char *stub_name;
3084 enum elf32_arm_stub_type stub_type;
35fc36a8 3085 enum arm_st_branch_type branch_type;
48229727
JB		 3086};
3087
3088/* A table of relocs applied to branches which might trigger Cortex-A8
3089 erratum. */
3090
b38cadfb
NC		 3091struct a8_erratum_reloc
3092{
48229727
JB		 3093 bfd_vma from;
3094 bfd_vma destination;
92750f34
DJ		 3095 struct elf32_arm_link_hash_entry *hash;
3096 const char *sym_name;
48229727 3097 unsigned int r_type;
35fc36a8 3098 enum arm_st_branch_type branch_type;
48229727
JB		 3099 bfd_boolean non_a8_stub;
3100};
3101
ba93b8ac
DJ		 3102/* The size of the thread control block. */
3103#define TCB_SIZE 8
3104
34e77a92
RS		 3105/* ARM-specific information about a PLT entry, over and above the usual
3106 gotplt_union. */
b38cadfb
NC		 3107struct arm_plt_info
3108{
34e77a92
RS		 3109 /* We reference count Thumb references to a PLT entry separately,
3110 so that we can emit the Thumb trampoline only if needed. */
3111 bfd_signed_vma thumb_refcount;
3112
3113 /* Some references from Thumb code may be eliminated by BL->BLX
3114 conversion, so record them separately. */
3115 bfd_signed_vma maybe_thumb_refcount;
3116
3117 /* How many of the recorded PLT accesses were from non-call relocations.
3118 This information is useful when deciding whether anything takes the
3119 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3120 non-call references to the function should resolve directly to the
3121 real runtime target. */
3122 unsigned int noncall_refcount;
3123
3124 /* Since PLT entries have variable size if the Thumb prologue is
3125 used, we need to record the index into .got.plt instead of
3126 recomputing it from the PLT offset. */
3127 bfd_signed_vma got_offset;
3128};
3129
3130/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 3131struct arm_local_iplt_info
3132{
34e77a92
RS		 3133 /* The information that is usually found in the generic ELF part of
3134 the hash table entry. */
3135 union gotplt_union root;
3136
3137 /* The information that is usually found in the ARM-specific part of
3138 the hash table entry. */
3139 struct arm_plt_info arm;
3140
3141 /* A list of all potential dynamic relocations against this symbol. */
3142 struct elf_dyn_relocs *dyn_relocs;
3143};
3144
e8b09b87
CL		 3145/* Structure to handle FDPIC support for local functions. */
3146struct fdpic_local {
3147 unsigned int funcdesc_cnt;
3148 unsigned int gotofffuncdesc_cnt;
3149 int funcdesc_offset;
3150};
3151
0ffa91dd 3152struct elf_arm_obj_tdata
ba93b8ac
DJ		 3153{
3154 struct elf_obj_tdata root;
3155
3156 /* tls_type for each local got entry. */
3157 char *local_got_tls_type;
ee065d83 3158
0855e32b
NS		 3159 /* GOTPLT entries for TLS descriptors. */
3160 bfd_vma *local_tlsdesc_gotent;
3161
34e77a92
RS		 3162 /* Information for local symbols that need entries in .iplt. */
3163 struct arm_local_iplt_info **local_iplt;
3164
bf21ed78
MS		 3165 /* Zero to warn when linking objects with incompatible enum sizes. */
3166 int no_enum_size_warning;
a9dc9481
JM		 3167
3168 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3169 int no_wchar_size_warning;
e8b09b87
CL		 3170
3171 /* Maintains FDPIC counters and funcdesc info. */
3172 struct fdpic_local *local_fdpic_cnts;
ba93b8ac
DJ		 3173};
3174
0ffa91dd
NC		 3175#define elf_arm_tdata(bfd) \
3176 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 3177
0ffa91dd
NC		 3178#define elf32_arm_local_got_tls_type(bfd) \
3179 (elf_arm_tdata (bfd)->local_got_tls_type)
3180
0855e32b
NS		 3181#define elf32_arm_local_tlsdesc_gotent(bfd) \
3182 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3183
34e77a92
RS		 3184#define elf32_arm_local_iplt(bfd) \
3185 (elf_arm_tdata (bfd)->local_iplt)
3186
e8b09b87
CL		 3187#define elf32_arm_local_fdpic_cnts(bfd) \
3188 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3189
0ffa91dd
NC		 3190#define is_arm_elf(bfd) \
3191 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3192 && elf_tdata (bfd) != NULL \
4dfe6ac6 3193 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 3194
3195static bfd_boolean
3196elf32_arm_mkobject (bfd *abfd)
3197{
0ffa91dd 3198 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 3199 ARM_ELF_DATA);
ba93b8ac
DJ		 3200}
3201
ba93b8ac
DJ		 3202#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3203
e8b09b87
CL		 3204/* Structure to handle FDPIC support for extern functions. */
3205struct fdpic_global {
3206 unsigned int gotofffuncdesc_cnt;
3207 unsigned int gotfuncdesc_cnt;
3208 unsigned int funcdesc_cnt;
3209 int funcdesc_offset;
3210 int gotfuncdesc_offset;
3211};
3212
ba96a88f 3213/* Arm ELF linker hash entry. */
252b5132 3214struct elf32_arm_link_hash_entry
b38cadfb
NC		 3215{
3216 struct elf_link_hash_entry root;
252b5132 3217
b38cadfb
NC		 3218 /* Track dynamic relocs copied for this symbol. */
3219 struct elf_dyn_relocs *dyn_relocs;
b7693d02 3220
b38cadfb
NC		 3221 /* ARM-specific PLT information. */
3222 struct arm_plt_info plt;
ba93b8ac
DJ		 3223
3224#define GOT_UNKNOWN 0
3225#define GOT_NORMAL 1
3226#define GOT_TLS_GD 2
3227#define GOT_TLS_IE 4
0855e32b
NS		 3228#define GOT_TLS_GDESC 8
3229#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3230 unsigned int tls_type : 8;
34e77a92 3231
b38cadfb
NC		 3232 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3233 unsigned int is_iplt : 1;
34e77a92 3234
b38cadfb 3235 unsigned int unused : 23;
a4fd1a8e 3236
b38cadfb
NC		 3237 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3238 starting at the end of the jump table. */
3239 bfd_vma tlsdesc_got;
0855e32b 3240
b38cadfb
NC		 3241 /* The symbol marking the real symbol location for exported thumb
3242 symbols with Arm stubs. */
3243 struct elf_link_hash_entry *export_glue;
906e58ca 3244
b38cadfb 3245 /* A pointer to the most recently used stub hash entry against this
8029a119 3246 symbol. */
b38cadfb 3247 struct elf32_arm_stub_hash_entry *stub_cache;
e8b09b87
CL		 3248
3249 /* Counter for FDPIC relocations against this symbol. */
3250 struct fdpic_global fdpic_cnts;
b38cadfb 3251};
252b5132 3252
252b5132 3253/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3254#define elf32_arm_link_hash_traverse(table, func, info) \
3255 (elf_link_hash_traverse \
3256 (&(table)->root, \
b7693d02 3257 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3258 (info)))
3259
3260/* Get the ARM elf linker hash table from a link_info structure. */
3261#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3262 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3263 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3264
906e58ca
NC		 3265#define arm_stub_hash_lookup(table, string, create, copy) \
3266 ((struct elf32_arm_stub_hash_entry *) \
3267 bfd_hash_lookup ((table), (string), (create), (copy)))
3268
21d799b5
NC		 3269/* Array to keep track of which stub sections have been created, and
3270 information on stub grouping. */
3271struct map_stub
3272{
3273 /* This is the section to which stubs in the group will be
3274 attached. */
3275 asection *link_sec;
3276 /* The stub section. */
3277 asection *stub_sec;
3278};
3279
0855e32b
NS		 3280#define elf32_arm_compute_jump_table_size(htab) \
3281 ((htab)->next_tls_desc_index * 4)
3282
9b485d32 3283/* ARM ELF linker hash table. */
252b5132 3284struct elf32_arm_link_hash_table
906e58ca
NC		 3285{
3286 /* The main hash table. */
3287 struct elf_link_hash_table root;
252b5132 3288
906e58ca
NC		 3289 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3290 bfd_size_type thumb_glue_size;
252b5132 3291
906e58ca
NC		 3292 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3293 bfd_size_type arm_glue_size;
252b5132 3294
906e58ca
NC		 3295 /* The size in bytes of section containing the ARMv4 BX veneers. */
3296 bfd_size_type bx_glue_size;
845b51d6 3297
906e58ca
NC		 3298 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3299 veneer has been populated. */
3300 bfd_vma bx_glue_offset[15];
845b51d6 3301
906e58ca
NC		 3302 /* The size in bytes of the section containing glue for VFP11 erratum
3303 veneers. */
3304 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3305
a504d23a
LA		 3306 /* The size in bytes of the section containing glue for STM32L4XX erratum
3307 veneers. */
3308 bfd_size_type stm32l4xx_erratum_glue_size;
3309
48229727
JB		 3310 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3311 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3312 elf32_arm_write_section(). */
3313 struct a8_erratum_fix *a8_erratum_fixes;
3314 unsigned int num_a8_erratum_fixes;
3315
906e58ca
NC		 3316 /* An arbitrary input BFD chosen to hold the glue sections. */
3317 bfd * bfd_of_glue_owner;
ba96a88f 3318
906e58ca
NC		 3319 /* Nonzero to output a BE8 image. */
3320 int byteswap_code;
e489d0ae 3321
906e58ca
NC		 3322 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3323 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3324 int target1_is_rel;
9c504268 3325
906e58ca
NC		 3326 /* The relocation to use for R_ARM_TARGET2 relocations. */
3327 int target2_reloc;
eb043451 3328
906e58ca
NC		 3329 /* 0 = Ignore R_ARM_V4BX.
3330 1 = Convert BX to MOV PC.
3331 2 = Generate v4 interworing stubs. */
3332 int fix_v4bx;
319850b4 3333
48229727
JB		 3334 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3335 int fix_cortex_a8;
3336
2de70689
MGD		 3337 /* Whether we should fix the ARM1176 BLX immediate issue. */
3338 int fix_arm1176;
3339
906e58ca
NC		 3340 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3341 int use_blx;
33bfe774 3342
906e58ca
NC		 3343 /* What sort of code sequences we should look for which may trigger the
3344 VFP11 denorm erratum. */
3345 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3346
906e58ca
NC		 3347 /* Global counter for the number of fixes we have emitted. */
3348 int num_vfp11_fixes;
c7b8f16e 3349
a504d23a
LA		 3350 /* What sort of code sequences we should look for which may trigger the
3351 STM32L4XX erratum. */
3352 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3353
3354 /* Global counter for the number of fixes we have emitted. */
3355 int num_stm32l4xx_fixes;
3356
906e58ca
NC		 3357 /* Nonzero to force PIC branch veneers. */
3358 int pic_veneer;
27e55c4d 3359
906e58ca
NC		 3360 /* The number of bytes in the initial entry in the PLT. */
3361 bfd_size_type plt_header_size;
e5a52504 3362
906e58ca
NC		 3363 /* The number of bytes in the subsequent PLT etries. */
3364 bfd_size_type plt_entry_size;
e5a52504 3365
906e58ca
NC		 3366 /* True if the target system is VxWorks. */
3367 int vxworks_p;
00a97672 3368
906e58ca
NC		 3369 /* True if the target system is Symbian OS. */
3370 int symbian_p;
e5a52504 3371
b38cadfb
NC		 3372 /* True if the target system is Native Client. */
3373 int nacl_p;
3374
906e58ca 3375 /* True if the target uses REL relocations. */
f3185997 3376 bfd_boolean use_rel;
4e7fd91e 3377
54ddd295
TP		 3378 /* Nonzero if import library must be a secure gateway import library
3379 as per ARMv8-M Security Extensions. */
3380 int cmse_implib;
3381
0955507f
TP		 3382 /* The import library whose symbols' address must remain stable in
3383 the import library generated. */
3384 bfd *in_implib_bfd;
3385
0855e32b
NS		 3386 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3387 bfd_vma next_tls_desc_index;
3388
3389 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3390 bfd_vma num_tls_desc;
3391
906e58ca
NC		 3392 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3393 asection *srelplt2;
00a97672 3394
0855e32b
NS		 3395 /* The offset into splt of the PLT entry for the TLS descriptor
3396 resolver. Special values are 0, if not necessary (or not found
3397 to be necessary yet), and -1 if needed but not determined
3398 yet. */
3399 bfd_vma dt_tlsdesc_plt;
3400
3401 /* The offset into sgot of the GOT entry used by the PLT entry
3402 above. */
b38cadfb 3403 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3404
3405 /* Offset in .plt section of tls_arm_trampoline. */
3406 bfd_vma tls_trampoline;
3407
5c5a4843 3408 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
906e58ca
NC		 3409 union
3410 {
3411 bfd_signed_vma refcount;
3412 bfd_vma offset;
3413 } tls_ldm_got;
b7693d02 3414
87d72d41
AM		 3415 /* Small local sym cache. */
3416 struct sym_cache sym_cache;
906e58ca
NC		 3417
3418 /* For convenience in allocate_dynrelocs. */
3419 bfd * obfd;
3420
0855e32b
NS		 3421 /* The amount of space used by the reserved portion of the sgotplt
3422 section, plus whatever space is used by the jump slots. */
3423 bfd_vma sgotplt_jump_table_size;
3424
906e58ca
NC		 3425 /* The stub hash table. */
3426 struct bfd_hash_table stub_hash_table;
3427
3428 /* Linker stub bfd. */
3429 bfd *stub_bfd;
3430
3431 /* Linker call-backs. */
6bde4c52
TP		 3432 asection * (*add_stub_section) (const char *, asection *, asection *,
3433 unsigned int);
906e58ca
NC		 3434 void (*layout_sections_again) (void);
3435
3436 /* Array to keep track of which stub sections have been created, and
3437 information on stub grouping. */
21d799b5 3438 struct map_stub *stub_group;
906e58ca 3439
4ba2ef8f
TP		 3440 /* Input stub section holding secure gateway veneers. */
3441 asection *cmse_stub_sec;
3442
0955507f
TP		 3443 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3444 start to be allocated. */
3445 bfd_vma new_cmse_stub_offset;
3446
fe33d2fa 3447 /* Number of elements in stub_group. */
7292b3ac 3448 unsigned int top_id;
fe33d2fa 3449
906e58ca
NC		 3450 /* Assorted information used by elf32_arm_size_stubs. */
3451 unsigned int bfd_count;
7292b3ac 3452 unsigned int top_index;
906e58ca 3453 asection **input_list;
617a5ada
CL		 3454
3455 /* True if the target system uses FDPIC. */
3456 int fdpic_p;
e8b09b87
CL		 3457
3458 /* Fixup section. Used for FDPIC. */
3459 asection *srofixup;
906e58ca 3460};
252b5132 3461
e8b09b87
CL		 3462/* Add an FDPIC read-only fixup. */
3463static void
3464arm_elf_add_rofixup (bfd *output_bfd, asection *srofixup, bfd_vma offset)
3465{
3466 bfd_vma fixup_offset;
3467
3468 fixup_offset = srofixup->reloc_count++ * 4;
3469 BFD_ASSERT (fixup_offset < srofixup->size);
3470 bfd_put_32 (output_bfd, offset, srofixup->contents + fixup_offset);
3471}
3472
a504d23a
LA		 3473static inline int
3474ctz (unsigned int mask)
3475{
3476#if GCC_VERSION >= 3004
3477 return __builtin_ctz (mask);
3478#else
3479 unsigned int i;
3480
3481 for (i = 0; i < 8 * sizeof (mask); i++)
3482 {
3483 if (mask & 0x1)
3484 break;
3485 mask = (mask >> 1);
3486 }
3487 return i;
3488#endif
3489}
3490
3491static inline int
b25e998d 3492elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3493{
3494#if GCC_VERSION >= 3004
3495 return __builtin_popcount (mask);
3496#else
b25e998d
CG		 3497 unsigned int i;
3498 int sum = 0;
a504d23a
LA		 3499
3500 for (i = 0; i < 8 * sizeof (mask); i++)
3501 {
3502 if (mask & 0x1)
3503 sum++;
3504 mask = (mask >> 1);
3505 }
3506 return sum;
3507#endif
3508}
3509
e8b09b87
CL		 3510static void elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
3511 asection *sreloc, Elf_Internal_Rela *rel);
3512
3513static void
3514arm_elf_fill_funcdesc(bfd *output_bfd,
3515 struct bfd_link_info *info,
3516 int *funcdesc_offset,
3517 int dynindx,
3518 int offset,
3519 bfd_vma addr,
3520 bfd_vma dynreloc_value,
3521 bfd_vma seg)
3522{
3523 if ((*funcdesc_offset & 1) == 0)
3524 {
3525 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
3526 asection *sgot = globals->root.sgot;
3527
3528 if (bfd_link_pic(info))
3529 {
3530 asection *srelgot = globals->root.srelgot;
3531 Elf_Internal_Rela outrel;
3532
3533 outrel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
3534 outrel.r_offset = sgot->output_section->vma + sgot->output_offset + offset;
3535 outrel.r_addend = 0;
3536
3537 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
3538 bfd_put_32 (output_bfd, addr, sgot->contents + offset);
3539 bfd_put_32 (output_bfd, seg, sgot->contents + offset + 4);
3540 }
3541 else
3542 {
3543 struct elf_link_hash_entry *hgot = globals->root.hgot;
3544 bfd_vma got_value = hgot->root.u.def.value
3545 + hgot->root.u.def.section->output_section->vma
3546 + hgot->root.u.def.section->output_offset;
3547
3548 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3549 sgot->output_section->vma + sgot->output_offset
3550 + offset);
3551 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3552 sgot->output_section->vma + sgot->output_offset
3553 + offset + 4);
3554 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + offset);
3555 bfd_put_32 (output_bfd, got_value, sgot->contents + offset + 4);
3556 }
3557 *funcdesc_offset |= 1;
3558 }
3559}
3560
780a67af
NC		 3561/* Create an entry in an ARM ELF linker hash table. */
3562
3563static struct bfd_hash_entry *
57e8b36a 3564elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3565 struct bfd_hash_table * table,
3566 const char * string)
780a67af
NC		 3567{
3568 struct elf32_arm_link_hash_entry * ret =
3569 (struct elf32_arm_link_hash_entry *) entry;
3570
3571 /* Allocate the structure if it has not already been allocated by a
3572 subclass. */
906e58ca 3573 if (ret == NULL)
21d799b5 3574 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3575 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3576 if (ret == NULL)
780a67af
NC		 3577 return (struct bfd_hash_entry *) ret;
3578
3579 /* Call the allocation method of the superclass. */
3580 ret = ((struct elf32_arm_link_hash_entry *)
3581 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3582 table, string));
57e8b36a 3583 if (ret != NULL)
b7693d02 3584 {
0bdcacaf 3585 ret->dyn_relocs = NULL;
ba93b8ac 3586 ret->tls_type = GOT_UNKNOWN;
0855e32b 3587 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3588 ret->plt.thumb_refcount = 0;
3589 ret->plt.maybe_thumb_refcount = 0;
3590 ret->plt.noncall_refcount = 0;
3591 ret->plt.got_offset = -1;
3592 ret->is_iplt = FALSE;
a4fd1a8e 3593 ret->export_glue = NULL;
906e58ca
NC		 3594
3595 ret->stub_cache = NULL;
e8b09b87
CL		 3596
3597 ret->fdpic_cnts.gotofffuncdesc_cnt = 0;
3598 ret->fdpic_cnts.gotfuncdesc_cnt = 0;
3599 ret->fdpic_cnts.funcdesc_cnt = 0;
3600 ret->fdpic_cnts.funcdesc_offset = -1;
3601 ret->fdpic_cnts.gotfuncdesc_offset = -1;
b7693d02 3602 }
780a67af
NC		 3603
3604 return (struct bfd_hash_entry *) ret;
3605}
3606
34e77a92
RS		 3607/* Ensure that we have allocated bookkeeping structures for ABFD's local
3608 symbols. */
3609
3610static bfd_boolean
3611elf32_arm_allocate_local_sym_info (bfd *abfd)
3612{
3613 if (elf_local_got_refcounts (abfd) == NULL)
3614 {
3615 bfd_size_type num_syms;
3616 bfd_size_type size;
3617 char *data;
3618
3619 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3620 size = num_syms * (sizeof (bfd_signed_vma)
3621 + sizeof (struct arm_local_iplt_info *)
3622 + sizeof (bfd_vma)
e8b09b87
CL		 3623 + sizeof (char)
3624 + sizeof (struct fdpic_local));
34e77a92
RS		 3625 data = bfd_zalloc (abfd, size);
3626 if (data == NULL)
3627 return FALSE;
3628
e8b09b87
CL		 3629 elf32_arm_local_fdpic_cnts (abfd) = (struct fdpic_local *) data;
3630 data += num_syms * sizeof (struct fdpic_local);
3631
34e77a92
RS		 3632 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3633 data += num_syms * sizeof (bfd_signed_vma);
3634
3635 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3636 data += num_syms * sizeof (struct arm_local_iplt_info *);
3637
3638 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3639 data += num_syms * sizeof (bfd_vma);
3640
3641 elf32_arm_local_got_tls_type (abfd) = data;
3642 }
3643 return TRUE;
3644}
3645
3646/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3647 to input bfd ABFD. Create the information if it doesn't already exist.
3648 Return null if an allocation fails. */
3649
3650static struct arm_local_iplt_info *
3651elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3652{
3653 struct arm_local_iplt_info **ptr;
3654
3655 if (!elf32_arm_allocate_local_sym_info (abfd))
3656 return NULL;
3657
3658 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3659 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3660 if (*ptr == NULL)
3661 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3662 return *ptr;
3663}
3664
3665/* Try to obtain PLT information for the symbol with index R_SYMNDX
3666 in ABFD's symbol table. If the symbol is global, H points to its
3667 hash table entry, otherwise H is null.
3668
3669 Return true if the symbol does have PLT information. When returning
3670 true, point *ROOT_PLT at the target-independent reference count/offset
3671 union and *ARM_PLT at the ARM-specific information. */
3672
3673static bfd_boolean
4ba2ef8f
TP		 3674elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3675 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3676 unsigned long r_symndx, union gotplt_union **root_plt,
3677 struct arm_plt_info **arm_plt)
3678{
3679 struct arm_local_iplt_info *local_iplt;
3680
4ba2ef8f
TP		 3681 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3682 return FALSE;
3683
34e77a92
RS		 3684 if (h != NULL)
3685 {
3686 *root_plt = &h->root.plt;
3687 *arm_plt = &h->plt;
3688 return TRUE;
3689 }
3690
3691 if (elf32_arm_local_iplt (abfd) == NULL)
3692 return FALSE;
3693
3694 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3695 if (local_iplt == NULL)
3696 return FALSE;
3697
3698 *root_plt = &local_iplt->root;
3699 *arm_plt = &local_iplt->arm;
3700 return TRUE;
3701}
3702
59029f57
CL		 3703static bfd_boolean using_thumb_only (struct elf32_arm_link_hash_table *globals);
3704
34e77a92
RS		 3705/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3706 before it. */
3707
3708static bfd_boolean
3709elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3710 struct arm_plt_info *arm_plt)
3711{
3712 struct elf32_arm_link_hash_table *htab;
3713
3714 htab = elf32_arm_hash_table (info);
59029f57
CL		 3715
3716 return (!using_thumb_only(htab) && (arm_plt->thumb_refcount != 0
3717 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0)));
34e77a92
RS		 3718}
3719
3720/* Return a pointer to the head of the dynamic reloc list that should
3721 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3722 ABFD's symbol table. Return null if an error occurs. */
3723
3724static struct elf_dyn_relocs **
3725elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3726 Elf_Internal_Sym *isym)
3727{
3728 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3729 {
3730 struct arm_local_iplt_info *local_iplt;
3731
3732 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3733 if (local_iplt == NULL)
3734 return NULL;
3735 return &local_iplt->dyn_relocs;
3736 }
3737 else
3738 {
3739 /* Track dynamic relocs needed for local syms too.
3740 We really need local syms available to do this
3741 easily. Oh well. */
3742 asection *s;
3743 void *vpp;
3744
3745 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3746 if (s == NULL)
3747 abort ();
3748
3749 vpp = &elf_section_data (s)->local_dynrel;
3750 return (struct elf_dyn_relocs **) vpp;
3751 }
3752}
3753
906e58ca
NC		 3754/* Initialize an entry in the stub hash table. */
3755
3756static struct bfd_hash_entry *
3757stub_hash_newfunc (struct bfd_hash_entry *entry,
3758 struct bfd_hash_table *table,
3759 const char *string)
3760{
3761 /* Allocate the structure if it has not already been allocated by a
3762 subclass. */
3763 if (entry == NULL)
3764 {
21d799b5 3765 entry = (struct bfd_hash_entry *)
99059e56 3766 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3767 if (entry == NULL)
3768 return entry;
3769 }
3770
3771 /* Call the allocation method of the superclass. */
3772 entry = bfd_hash_newfunc (entry, table, string);
3773 if (entry != NULL)
3774 {
3775 struct elf32_arm_stub_hash_entry *eh;
3776
3777 /* Initialize the local fields. */
3778 eh = (struct elf32_arm_stub_hash_entry *) entry;
3779 eh->stub_sec = NULL;
0955507f 3780 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3781 eh->source_value = 0;
906e58ca
NC		 3782 eh->target_value = 0;
3783 eh->target_section = NULL;
cedfb179 3784 eh->orig_insn = 0;
906e58ca 3785 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3786 eh->stub_size = 0;
3787 eh->stub_template = NULL;
0955507f 3788 eh->stub_template_size = -1;
906e58ca
NC		 3789 eh->h = NULL;
3790 eh->id_sec = NULL;
d8d2f433 3791 eh->output_name = NULL;
906e58ca
NC		 3792 }
3793
3794 return entry;
3795}
3796
00a97672 3797/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3798 shortcuts to them in our hash table. */
3799
3800static bfd_boolean
57e8b36a 3801create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3802{
3803 struct elf32_arm_link_hash_table *htab;
3804
e5a52504 3805 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3806 if (htab == NULL)
3807 return FALSE;
3808
e5a52504
MM		 3809 /* BPABI objects never have a GOT, or associated sections. */
3810 if (htab->symbian_p)
3811 return TRUE;
3812
5e681ec4
PB		 3813 if (! _bfd_elf_create_got_section (dynobj, info))
3814 return FALSE;
3815
e8b09b87
CL		 3816 /* Also create .rofixup. */
3817 if (htab->fdpic_p)
3818 {
3819 htab->srofixup = bfd_make_section_with_flags (dynobj, ".rofixup",
3820 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS
3821 | SEC_IN_MEMORY | SEC_LINKER_CREATED | SEC_READONLY));
fd361982
AM		 3822 if (htab->srofixup == NULL
3823 || !bfd_set_section_alignment (htab->srofixup, 2))
e8b09b87
CL		 3824 return FALSE;
3825 }
3826
5e681ec4
PB		 3827 return TRUE;
3828}
3829
34e77a92
RS		 3830/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3831
3832static bfd_boolean
3833create_ifunc_sections (struct bfd_link_info *info)
3834{
3835 struct elf32_arm_link_hash_table *htab;
3836 const struct elf_backend_data *bed;
3837 bfd *dynobj;
3838 asection *s;
3839 flagword flags;
b38cadfb 3840
34e77a92
RS		 3841 htab = elf32_arm_hash_table (info);
3842 dynobj = htab->root.dynobj;
3843 bed = get_elf_backend_data (dynobj);
3844 flags = bed->dynamic_sec_flags;
3845
3846 if (htab->root.iplt == NULL)
3847 {
3d4d4302
AM		 3848 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3849 flags | SEC_READONLY | SEC_CODE);
34e77a92 3850 if (s == NULL
fd361982 3851 || !bfd_set_section_alignment (s, bed->plt_alignment))
34e77a92
RS		 3852 return FALSE;
3853 htab->root.iplt = s;
3854 }
3855
3856 if (htab->root.irelplt == NULL)
3857 {
3d4d4302
AM		 3858 s = bfd_make_section_anyway_with_flags (dynobj,
3859 RELOC_SECTION (htab, ".iplt"),
3860 flags | SEC_READONLY);
34e77a92 3861 if (s == NULL
fd361982 3862 || !bfd_set_section_alignment (s, bed->s->log_file_align))
34e77a92
RS		 3863 return FALSE;
3864 htab->root.irelplt = s;
3865 }
3866
3867 if (htab->root.igotplt == NULL)
3868 {
3d4d4302 3869 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92 3870 if (s == NULL
fd361982 3871 || !bfd_set_section_alignment (s, bed->s->log_file_align))
34e77a92
RS		 3872 return FALSE;
3873 htab->root.igotplt = s;
3874 }
3875 return TRUE;
3876}
3877
eed94f8f
NC		 3878/* Determine if we're dealing with a Thumb only architecture. */
3879
3880static bfd_boolean
3881using_thumb_only (struct elf32_arm_link_hash_table *globals)
3882{
2fd158eb
TP		 3883 int arch;
3884 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3885 Tag_CPU_arch_profile);
eed94f8f 3886
2fd158eb
TP		 3887 if (profile)
3888 return profile == 'M';
eed94f8f 3889
2fd158eb 3890 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3891
60a019a0 3892 /* Force return logic to be reviewed for each new architecture. */
031254f2 3893 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0 3894
2fd158eb
TP		 3895 if (arch == TAG_CPU_ARCH_V6_M
3896 || arch == TAG_CPU_ARCH_V6S_M
3897 || arch == TAG_CPU_ARCH_V7E_M
3898 || arch == TAG_CPU_ARCH_V8M_BASE
031254f2
AV		 3899 || arch == TAG_CPU_ARCH_V8M_MAIN
3900 || arch == TAG_CPU_ARCH_V8_1M_MAIN)
2fd158eb 3901 return TRUE;
eed94f8f 3902
2fd158eb 3903 return FALSE;
eed94f8f
NC		 3904}
3905
3906/* Determine if we're dealing with a Thumb-2 object. */
3907
3908static bfd_boolean
3909using_thumb2 (struct elf32_arm_link_hash_table *globals)
3910{
60a019a0
TP		 3911 int arch;
3912 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3913 Tag_THUMB_ISA_use);
3914
3915 if (thumb_isa)
3916 return thumb_isa == 2;
3917
3918 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3919
3920 /* Force return logic to be reviewed for each new architecture. */
031254f2 3921 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 3922
3923 return (arch == TAG_CPU_ARCH_V6T2
3924 || arch == TAG_CPU_ARCH_V7
3925 || arch == TAG_CPU_ARCH_V7E_M
3926 || arch == TAG_CPU_ARCH_V8
bff0500d 3927 || arch == TAG_CPU_ARCH_V8R
031254f2
AV		 3928 || arch == TAG_CPU_ARCH_V8M_MAIN
3929 || arch == TAG_CPU_ARCH_V8_1M_MAIN);
eed94f8f
NC		 3930}
3931
5e866f5a
TP		 3932/* Determine whether Thumb-2 BL instruction is available. */
3933
3934static bfd_boolean
3935using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3936{
3937 int arch =
3938 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3939
3940 /* Force return logic to be reviewed for each new architecture. */
031254f2 3941 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
5e866f5a
TP		 3942
3943 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3944 return (arch == TAG_CPU_ARCH_V6T2
3945 || arch >= TAG_CPU_ARCH_V7);
3946}
3947
00a97672
RS		 3948/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3949 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3950 hash table. */
3951
3952static bfd_boolean
57e8b36a 3953elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3954{
3955 struct elf32_arm_link_hash_table *htab;
3956
3957 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3958 if (htab == NULL)
3959 return FALSE;
3960
362d30a1 3961 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3962 return FALSE;
3963
3964 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3965 return FALSE;
3966
00a97672
RS		 3967 if (htab->vxworks_p)
3968 {
3969 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3970 return FALSE;
3971
0e1862bb 3972 if (bfd_link_pic (info))
00a97672
RS		 3973 {
3974 htab->plt_header_size = 0;
3975 htab->plt_entry_size
3976 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3977 }
3978 else
3979 {
3980 htab->plt_header_size
3981 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3982 htab->plt_entry_size
3983 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3984 }
aebf9be7
NC		 3985
3986 if (elf_elfheader (dynobj))
3987 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3988 }
eed94f8f
NC		 3989 else
3990 {
3991 /* PR ld/16017
3992 Test for thumb only architectures. Note - we cannot just call
3993 using_thumb_only() as the attributes in the output bfd have not been
3994 initialised at this point, so instead we use the input bfd. */
3995 bfd * saved_obfd = htab->obfd;
3996
3997 htab->obfd = dynobj;
3998 if (using_thumb_only (htab))
3999 {
4000 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
4001 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
4002 }
4003 htab->obfd = saved_obfd;
4004 }
5e681ec4 4005
7801f98f
CL		 4006 if (htab->fdpic_p) {
4007 htab->plt_header_size = 0;
4008 if (info->flags & DF_BIND_NOW)
4009 htab->plt_entry_size = 4 * (ARRAY_SIZE(elf32_arm_fdpic_plt_entry) - 5);
4010 else
4011 htab->plt_entry_size = 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry);
4012 }
4013
362d30a1
RS		 4014 if (!htab->root.splt
4015 || !htab->root.srelplt
9d19e4fd
AM		 4016 || !htab->root.sdynbss
4017 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 4018 abort ();
4019
4020 return TRUE;
4021}
4022
906e58ca
NC		 4023/* Copy the extra info we tack onto an elf_link_hash_entry. */
4024
4025static void
4026elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
4027 struct elf_link_hash_entry *dir,
4028 struct elf_link_hash_entry *ind)
4029{
4030 struct elf32_arm_link_hash_entry *edir, *eind;
4031
4032 edir = (struct elf32_arm_link_hash_entry *) dir;
4033 eind = (struct elf32_arm_link_hash_entry *) ind;
4034
0bdcacaf 4035 if (eind->dyn_relocs != NULL)
906e58ca 4036 {
0bdcacaf 4037 if (edir->dyn_relocs != NULL)
906e58ca 4038 {
0bdcacaf
RS		 4039 struct elf_dyn_relocs **pp;
4040 struct elf_dyn_relocs *p;
906e58ca
NC		 4041
4042 /* Add reloc counts against the indirect sym to the direct sym
4043 list. Merge any entries against the same section. */
0bdcacaf 4044 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 4045 {
0bdcacaf 4046 struct elf_dyn_relocs *q;
906e58ca 4047
0bdcacaf
RS		 4048 for (q = edir->dyn_relocs; q != NULL; q = q->next)
4049 if (q->sec == p->sec)
906e58ca
NC		 4050 {
4051 q->pc_count += p->pc_count;
4052 q->count += p->count;
4053 *pp = p->next;
4054 break;
4055 }
4056 if (q == NULL)
4057 pp = &p->next;
4058 }
0bdcacaf 4059 *pp = edir->dyn_relocs;
906e58ca
NC		 4060 }
4061
0bdcacaf
RS		 4062 edir->dyn_relocs = eind->dyn_relocs;
4063 eind->dyn_relocs = NULL;
906e58ca
NC		 4064 }
4065
4066 if (ind->root.type == bfd_link_hash_indirect)
4067 {
4068 /* Copy over PLT info. */
34e77a92
RS		 4069 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
4070 eind->plt.thumb_refcount = 0;
4071 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
4072 eind->plt.maybe_thumb_refcount = 0;
4073 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
4074 eind->plt.noncall_refcount = 0;
4075
e8b09b87
CL		 4076 /* Copy FDPIC counters. */
4077 edir->fdpic_cnts.gotofffuncdesc_cnt += eind->fdpic_cnts.gotofffuncdesc_cnt;
4078 edir->fdpic_cnts.gotfuncdesc_cnt += eind->fdpic_cnts.gotfuncdesc_cnt;
4079 edir->fdpic_cnts.funcdesc_cnt += eind->fdpic_cnts.funcdesc_cnt;
4080
34e77a92
RS		 4081 /* We should only allocate a function to .iplt once the final
4082 symbol information is known. */
4083 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 4084
4085 if (dir->got.refcount <= 0)
4086 {
4087 edir->tls_type = eind->tls_type;
4088 eind->tls_type = GOT_UNKNOWN;
4089 }
4090 }
4091
4092 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
4093}
4094
68faa637
AM		 4095/* Destroy an ARM elf linker hash table. */
4096
4097static void
d495ab0d 4098elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 4099{
4100 struct elf32_arm_link_hash_table *ret
d495ab0d 4101 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 4102
4103 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 4104 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 4105}
4106
906e58ca
NC		 4107/* Create an ARM elf linker hash table. */
4108
4109static struct bfd_link_hash_table *
4110elf32_arm_link_hash_table_create (bfd *abfd)
4111{
4112 struct elf32_arm_link_hash_table *ret;
4113 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
4114
7bf52ea2 4115 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 4116 if (ret == NULL)
4117 return NULL;
4118
4119 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
4120 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 4121 sizeof (struct elf32_arm_link_hash_entry),
4122 ARM_ELF_DATA))
906e58ca
NC		 4123 {
4124 free (ret);
4125 return NULL;
4126 }
4127
906e58ca 4128 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 4129 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 4130#ifdef FOUR_WORD_PLT
4131 ret->plt_header_size = 16;
4132 ret->plt_entry_size = 16;
4133#else
4134 ret->plt_header_size = 20;
1db37fe6 4135 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 4136#endif
f3185997 4137 ret->use_rel = TRUE;
906e58ca 4138 ret->obfd = abfd;
617a5ada 4139 ret->fdpic_p = 0;
906e58ca
NC		 4140
4141 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
4142 sizeof (struct elf32_arm_stub_hash_entry)))
4143 {
d495ab0d 4144 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 4145 return NULL;
4146 }
d495ab0d 4147 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 4148
4149 return &ret->root.root;
4150}
4151
cd1dac3d
DG		 4152/* Determine what kind of NOPs are available. */
4153
4154static bfd_boolean
4155arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
4156{
4157 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
4158 Tag_CPU_arch);
cd1dac3d 4159
60a019a0 4160 /* Force return logic to be reviewed for each new architecture. */
031254f2 4161 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 4162
4163 return (arch == TAG_CPU_ARCH_V6T2
4164 || arch == TAG_CPU_ARCH_V6K
4165 || arch == TAG_CPU_ARCH_V7
bff0500d
TP		 4166 || arch == TAG_CPU_ARCH_V8
4167 || arch == TAG_CPU_ARCH_V8R);
cd1dac3d
DG		 4168}
4169
f4ac8484
DJ		 4170static bfd_boolean
4171arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
4172{
4173 switch (stub_type)
4174 {
fea2b4d6 4175 case arm_stub_long_branch_thumb_only:
80c135e5 4176 case arm_stub_long_branch_thumb2_only:
d5a67c02 4177 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 4178 case arm_stub_long_branch_v4t_thumb_arm:
4179 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 4180 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 4181 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 4182 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 4183 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 4184 return TRUE;
4185 case arm_stub_none:
4186 BFD_FAIL ();
4187 return FALSE;
4188 break;
4189 default:
4190 return FALSE;
4191 }
4192}
4193
906e58ca
NC		 4194/* Determine the type of stub needed, if any, for a call. */
4195
4196static enum elf32_arm_stub_type
4197arm_type_of_stub (struct bfd_link_info *info,
4198 asection *input_sec,
4199 const Elf_Internal_Rela *rel,
34e77a92 4200 unsigned char st_type,
35fc36a8 4201 enum arm_st_branch_type *actual_branch_type,
906e58ca 4202 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 4203 bfd_vma destination,
4204 asection *sym_sec,
4205 bfd *input_bfd,
4206 const char *name)
906e58ca
NC		 4207{
4208 bfd_vma location;
4209 bfd_signed_vma branch_offset;
4210 unsigned int r_type;
4211 struct elf32_arm_link_hash_table * globals;
5e866f5a 4212 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 4213 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 4214 int use_plt = 0;
35fc36a8 4215 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 4216 union gotplt_union *root_plt;
4217 struct arm_plt_info *arm_plt;
d5a67c02
AV		 4218 int arch;
4219 int thumb2_movw;
906e58ca 4220
35fc36a8 4221 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 4222 return stub_type;
4223
906e58ca 4224 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4225 if (globals == NULL)
4226 return stub_type;
906e58ca
NC		 4227
4228 thumb_only = using_thumb_only (globals);
906e58ca 4229 thumb2 = using_thumb2 (globals);
5e866f5a 4230 thumb2_bl = using_thumb2_bl (globals);
906e58ca 4231
d5a67c02
AV		 4232 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
4233
4234 /* True for architectures that implement the thumb2 movw instruction. */
4235 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
4236
906e58ca
NC		 4237 /* Determine where the call point is. */
4238 location = (input_sec->output_offset
4239 + input_sec->output_section->vma
4240 + rel->r_offset);
4241
906e58ca
NC		 4242 r_type = ELF32_R_TYPE (rel->r_info);
4243
39f21624
NC		 4244 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4245 are considering a function call relocation. */
c5423981 4246 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
07d6d2b8 4247 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 4248 && branch_type == ST_BRANCH_TO_ARM)
4249 branch_type = ST_BRANCH_TO_THUMB;
4250
34e77a92
RS		 4251 /* For TLS call relocs, it is the caller's responsibility to provide
4252 the address of the appropriate trampoline. */
4253 if (r_type != R_ARM_TLS_CALL
4254 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 4255 && elf32_arm_get_plt_info (input_bfd, globals, hash,
4256 ELF32_R_SYM (rel->r_info), &root_plt,
4257 &arm_plt)
34e77a92 4258 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 4259 {
34e77a92 4260 asection *splt;
fe33d2fa 4261
34e77a92
RS		 4262 if (hash == NULL || hash->is_iplt)
4263 splt = globals->root.iplt;
4264 else
4265 splt = globals->root.splt;
4266 if (splt != NULL)
b38cadfb 4267 {
34e77a92
RS		 4268 use_plt = 1;
4269
4270 /* Note when dealing with PLT entries: the main PLT stub is in
4271 ARM mode, so if the branch is in Thumb mode, another
4272 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 4273 PLT stub. If a long branch stub is needed, we'll add a
4274 Thumb->Arm one and branch directly to the ARM PLT entry.
4275 Here, we have to check if a pre-PLT Thumb->ARM stub
4276 is needed and if it will be close enough. */
34e77a92
RS		 4277
4278 destination = (splt->output_section->vma
4279 + splt->output_offset
4280 + root_plt->offset);
4281 st_type = STT_FUNC;
2df2751d
CL		 4282
4283 /* Thumb branch/call to PLT: it can become a branch to ARM
4284 or to Thumb. We must perform the same checks and
4285 corrections as in elf32_arm_final_link_relocate. */
4286 if ((r_type == R_ARM_THM_CALL)
4287 || (r_type == R_ARM_THM_JUMP24))
4288 {
4289 if (globals->use_blx
4290 && r_type == R_ARM_THM_CALL
4291 && !thumb_only)
4292 {
4293 /* If the Thumb BLX instruction is available, convert
4294 the BL to a BLX instruction to call the ARM-mode
4295 PLT entry. */
4296 branch_type = ST_BRANCH_TO_ARM;
4297 }
4298 else
4299 {
4300 if (!thumb_only)
4301 /* Target the Thumb stub before the ARM PLT entry. */
4302 destination -= PLT_THUMB_STUB_SIZE;
4303 branch_type = ST_BRANCH_TO_THUMB;
4304 }
4305 }
4306 else
4307 {
4308 branch_type = ST_BRANCH_TO_ARM;
4309 }
34e77a92 4310 }
5fa9e92f 4311 }
34e77a92
RS		 4312 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4313 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 4314
fe33d2fa
CL		 4315 branch_offset = (bfd_signed_vma)(destination - location);
4316
0855e32b 4317 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 4318 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 4319 {
5fa9e92f
CL		 4320 /* Handle cases where:
4321 - this call goes too far (different Thumb/Thumb2 max
99059e56 4322 distance)
155d87d7 4323 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 4324 Thumb->Arm branch (not bl). A stub is needed in this case,
4325 but only if this call is not through a PLT entry. Indeed,
695344c0 4326 PLT stubs handle mode switching already. */
5e866f5a 4327 if ((!thumb2_bl
906e58ca
NC		 4328 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
4329 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 4330 || (thumb2_bl
906e58ca
NC		 4331 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4332 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4333 || (thumb2
4334 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4335 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4336 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4337 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4338 && (((r_type == R_ARM_THM_CALL
4339 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981 4340 || (r_type == R_ARM_THM_JUMP24)
07d6d2b8 4341 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4342 && !use_plt))
906e58ca 4343 {
2df2751d
CL		 4344 /* If we need to insert a Thumb-Thumb long branch stub to a
4345 PLT, use one that branches directly to the ARM PLT
4346 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4347 stub, undo this now. */
695344c0
NC		 4348 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4349 {
4350 branch_type = ST_BRANCH_TO_ARM;
4351 branch_offset += PLT_THUMB_STUB_SIZE;
4352 }
2df2751d 4353
35fc36a8 4354 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4355 {
4356 /* Thumb to thumb. */
4357 if (!thumb_only)
4358 {
d5a67c02 4359 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4360 _bfd_error_handler
871b3ab2 4361 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4362 " section with SHF_ARM_PURECODE section"
4363 " attribute is only supported for M-profile"
90b6238f 4364 " targets that implement the movw instruction"),
10463f39 4365 input_bfd, input_sec);
d5a67c02 4366
0e1862bb 4367 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4368 /* PIC stubs. */
155d87d7 4369 ? ((globals->use_blx
9553db3c 4370 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4371 /* V5T and above. Stub starts with ARM code, so
4372 we must be able to switch mode before
4373 reaching it, which is only possible for 'bl'
4374 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4375 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4376 /* On V4T, use Thumb code only. */
d3626fb0 4377 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4378
4379 /* non-PIC stubs. */
155d87d7 4380 : ((globals->use_blx
9553db3c 4381 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4382 /* V5T and above. */
4383 ? arm_stub_long_branch_any_any
4384 /* V4T. */
d3626fb0 4385 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4386 }
4387 else
4388 {
d5a67c02
AV		 4389 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4390 stub_type = arm_stub_long_branch_thumb2_only_pure;
4391 else
4392 {
4393 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4394 _bfd_error_handler
871b3ab2 4395 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4396 " section with SHF_ARM_PURECODE section"
4397 " attribute is only supported for M-profile"
90b6238f 4398 " targets that implement the movw instruction"),
10463f39 4399 input_bfd, input_sec);
d5a67c02
AV		 4400
4401 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4402 /* PIC stub. */
4403 ? arm_stub_long_branch_thumb_only_pic
4404 /* non-PIC stub. */
4405 : (thumb2 ? arm_stub_long_branch_thumb2_only
4406 : arm_stub_long_branch_thumb_only);
4407 }
906e58ca
NC		 4408 }
4409 }
4410 else
4411 {
d5a67c02 4412 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4413 _bfd_error_handler
871b3ab2 4414 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4415 " section with SHF_ARM_PURECODE section"
4416 " attribute is only supported" " for M-profile"
90b6238f 4417 " targets that implement the movw instruction"),
10463f39 4418 input_bfd, input_sec);
d5a67c02 4419
906e58ca 4420 /* Thumb to arm. */
c820be07
NC		 4421 if (sym_sec != NULL
4422 && sym_sec->owner != NULL
4423 && !INTERWORK_FLAG (sym_sec->owner))
4424 {
4eca0228 4425 _bfd_error_handler
90b6238f
AM		 4426 (_("%pB(%s): warning: interworking not enabled;"
4427 " first occurrence: %pB: %s call to %s"),
4428 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
c820be07
NC		 4429 }
4430
0855e32b 4431 stub_type =
0e1862bb 4432 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4433 /* PIC stubs. */
0855e32b 4434 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4435 /* TLS PIC stubs. */
0855e32b
NS		 4436 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4437 : arm_stub_long_branch_v4t_thumb_tls_pic)
4438 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4439 /* V5T PIC and above. */
4440 ? arm_stub_long_branch_any_arm_pic
4441 /* V4T PIC stub. */
4442 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4443
4444 /* non-PIC stubs. */
0855e32b 4445 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4446 /* V5T and above. */
4447 ? arm_stub_long_branch_any_any
4448 /* V4T. */
4449 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4450
4451 /* Handle v4t short branches. */
fea2b4d6 4452 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4453 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4454 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4455 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4456 }
4457 }
4458 }
fe33d2fa
CL		 4459 else if (r_type == R_ARM_CALL
4460 || r_type == R_ARM_JUMP24
0855e32b
NS		 4461 || r_type == R_ARM_PLT32
4462 || r_type == R_ARM_TLS_CALL)
906e58ca 4463 {
d5a67c02 4464 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4465 _bfd_error_handler
871b3ab2 4466 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4467 " section with SHF_ARM_PURECODE section"
4468 " attribute is only supported for M-profile"
90b6238f 4469 " targets that implement the movw instruction"),
10463f39 4470 input_bfd, input_sec);
35fc36a8 4471 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4472 {
4473 /* Arm to thumb. */
c820be07
NC		 4474
4475 if (sym_sec != NULL
4476 && sym_sec->owner != NULL
4477 && !INTERWORK_FLAG (sym_sec->owner))
4478 {
4eca0228 4479 _bfd_error_handler
90b6238f
AM		 4480 (_("%pB(%s): warning: interworking not enabled;"
4481 " first occurrence: %pB: %s call to %s"),
4482 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
c820be07
NC		 4483 }
4484
4485 /* We have an extra 2-bytes reach because of
4486 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4487 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4488 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4489 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4490 || (r_type == R_ARM_JUMP24)
4491 || (r_type == R_ARM_PLT32))
906e58ca 4492 {
0e1862bb 4493 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4494 /* PIC stubs. */
ebe24dd4
CL		 4495 ? ((globals->use_blx)
4496 /* V5T and above. */
4497 ? arm_stub_long_branch_any_thumb_pic
4498 /* V4T stub. */
4499 : arm_stub_long_branch_v4t_arm_thumb_pic)
4500
c2b4a39d
CL		 4501 /* non-PIC stubs. */
4502 : ((globals->use_blx)
4503 /* V5T and above. */
4504 ? arm_stub_long_branch_any_any
4505 /* V4T. */
4506 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4507 }
4508 }
4509 else
4510 {
4511 /* Arm to arm. */
4512 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4513 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4514 {
0855e32b 4515 stub_type =
0e1862bb 4516 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4517 /* PIC stubs. */
0855e32b 4518 ? (r_type == R_ARM_TLS_CALL
6a631e86 4519 /* TLS PIC Stub. */
0855e32b 4520 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4521 : (globals->nacl_p
4522 ? arm_stub_long_branch_arm_nacl_pic
4523 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4524 /* non-PIC stubs. */
7a89b94e
NC		 4525 : (globals->nacl_p
4526 ? arm_stub_long_branch_arm_nacl
4527 : arm_stub_long_branch_any_any);
906e58ca
NC		 4528 }
4529 }
4530 }
4531
fe33d2fa
CL		 4532 /* If a stub is needed, record the actual destination type. */
4533 if (stub_type != arm_stub_none)
35fc36a8 4534 *actual_branch_type = branch_type;
fe33d2fa 4535
906e58ca
NC		 4536 return stub_type;
4537}
4538
4539/* Build a name for an entry in the stub hash table. */
4540
4541static char *
4542elf32_arm_stub_name (const asection *input_section,
4543 const asection *sym_sec,
4544 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4545 const Elf_Internal_Rela *rel,
4546 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4547{
4548 char *stub_name;
4549 bfd_size_type len;
4550
4551 if (hash)
4552 {
fe33d2fa 4553 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4554 stub_name = (char *) bfd_malloc (len);
906e58ca 4555 if (stub_name != NULL)
fe33d2fa 4556 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4557 input_section->id & 0xffffffff,
4558 hash->root.root.root.string,
fe33d2fa
CL		 4559 (int) rel->r_addend & 0xffffffff,
4560 (int) stub_type);
906e58ca
NC		 4561 }
4562 else
4563 {
fe33d2fa 4564 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4565 stub_name = (char *) bfd_malloc (len);
906e58ca 4566 if (stub_name != NULL)
fe33d2fa 4567 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4568 input_section->id & 0xffffffff,
4569 sym_sec->id & 0xffffffff,
0855e32b
NS		 4570 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4571 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4572 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4573 (int) rel->r_addend & 0xffffffff,
4574 (int) stub_type);
906e58ca
NC		 4575 }
4576
4577 return stub_name;
4578}
4579
4580/* Look up an entry in the stub hash. Stub entries are cached because
4581 creating the stub name takes a bit of time. */
4582
4583static struct elf32_arm_stub_hash_entry *
4584elf32_arm_get_stub_entry (const asection *input_section,
4585 const asection *sym_sec,
4586 struct elf_link_hash_entry *hash,
4587 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4588 struct elf32_arm_link_hash_table *htab,
4589 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4590{
4591 struct elf32_arm_stub_hash_entry *stub_entry;
4592 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4593 const asection *id_sec;
4594
4595 if ((input_section->flags & SEC_CODE) == 0)
4596 return NULL;
4597
4d83e8d9
CL		 4598 /* If the input section is the CMSE stubs one and it needs a long
4599 branch stub to reach it's final destination, give up with an
4600 error message: this is not supported. See PR ld/24709. */
4601 if (!strncmp (input_section->name, CMSE_STUB_NAME, strlen(CMSE_STUB_NAME)))
4602 {
4603 bfd *output_bfd = htab->obfd;
4604 asection *out_sec = bfd_get_section_by_name (output_bfd, CMSE_STUB_NAME);
4605
4606 _bfd_error_handler (_("ERROR: CMSE stub (%s section) too far "
4607 "(%#" PRIx64 ") from destination (%#" PRIx64 ")"),
4608 CMSE_STUB_NAME,
4609 (uint64_t)out_sec->output_section->vma
4610 + out_sec->output_offset,
4611 (uint64_t)sym_sec->output_section->vma
4612 + sym_sec->output_offset
4613 + h->root.root.u.def.value);
4614 /* Exit, rather than leave incompletely processed
4615 relocations. */
4616 xexit(1);
4617 }
4618
906e58ca
NC		 4619 /* If this input section is part of a group of sections sharing one
4620 stub section, then use the id of the first section in the group.
4621 Stub names need to include a section id, as there may well be
4622 more than one stub used to reach say, printf, and we need to
4623 distinguish between them. */
c2abbbeb 4624 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4625 id_sec = htab->stub_group[input_section->id].link_sec;
4626
4627 if (h != NULL && h->stub_cache != NULL
4628 && h->stub_cache->h == h
fe33d2fa
CL		 4629 && h->stub_cache->id_sec == id_sec
4630 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4631 {
4632 stub_entry = h->stub_cache;
4633 }
4634 else
4635 {
4636 char *stub_name;
4637
fe33d2fa 4638 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4639 if (stub_name == NULL)
4640 return NULL;
4641
4642 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4643 stub_name, FALSE, FALSE);
4644 if (h != NULL)
4645 h->stub_cache = stub_entry;
4646
4647 free (stub_name);
4648 }
4649
4650 return stub_entry;
4651}
4652
daa4adae
TP		 4653/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4654 section. */
4655
4656static bfd_boolean
4657arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4658{
4659 if (stub_type >= max_stub_type)
4660 abort (); /* Should be unreachable. */
4661
4ba2ef8f
TP		 4662 switch (stub_type)
4663 {
4664 case arm_stub_cmse_branch_thumb_only:
4665 return TRUE;
4666
4667 default:
4668 return FALSE;
4669 }
4670
4671 abort (); /* Should be unreachable. */
daa4adae
TP		 4672}
4673
4674/* Required alignment (as a power of 2) for the dedicated section holding
4675 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4676 with input sections. */
4677
4678static int
4679arm_dedicated_stub_output_section_required_alignment
4680 (enum elf32_arm_stub_type stub_type)
4681{
4682 if (stub_type >= max_stub_type)
4683 abort (); /* Should be unreachable. */
4684
4ba2ef8f
TP		 4685 switch (stub_type)
4686 {
4687 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4688 boundary. */
4689 case arm_stub_cmse_branch_thumb_only:
4690 return 5;
4691
4692 default:
4693 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4694 return 0;
4695 }
4696
4697 abort (); /* Should be unreachable. */
daa4adae
TP		 4698}
4699
4700/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4701 NULL if veneers of this type are interspersed with input sections. */
4702
4703static const char *
4704arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4705{
4706 if (stub_type >= max_stub_type)
4707 abort (); /* Should be unreachable. */
4708
4ba2ef8f
TP		 4709 switch (stub_type)
4710 {
4711 case arm_stub_cmse_branch_thumb_only:
4d83e8d9 4712 return CMSE_STUB_NAME;
4ba2ef8f
TP		 4713
4714 default:
4715 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4716 return NULL;
4717 }
4718
4719 abort (); /* Should be unreachable. */
daa4adae
TP		 4720}
4721
4722/* If veneers of type STUB_TYPE should go in a dedicated output section,
4723 returns the address of the hash table field in HTAB holding a pointer to the
4724 corresponding input section. Otherwise, returns NULL. */
4725
4726static asection **
4ba2ef8f
TP		 4727arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4728 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4729{
4730 if (stub_type >= max_stub_type)
4731 abort (); /* Should be unreachable. */
4732
4ba2ef8f
TP		 4733 switch (stub_type)
4734 {
4735 case arm_stub_cmse_branch_thumb_only:
4736 return &htab->cmse_stub_sec;
4737
4738 default:
4739 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4740 return NULL;
4741 }
4742
4743 abort (); /* Should be unreachable. */
daa4adae
TP		 4744}
4745
4746/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4747 is the section that branch into veneer and can be NULL if stub should go in
4748 a dedicated output section. Returns a pointer to the stub section, and the
4749 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4750 LINK_SEC_P may be NULL. */
906e58ca 4751
48229727
JB		 4752static asection *
4753elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4754 struct elf32_arm_link_hash_table *htab,
4755 enum elf32_arm_stub_type stub_type)
906e58ca 4756{
daa4adae
TP		 4757 asection *link_sec, *out_sec, **stub_sec_p;
4758 const char *stub_sec_prefix;
4759 bfd_boolean dedicated_output_section =
4760 arm_dedicated_stub_output_section_required (stub_type);
4761 int align;
906e58ca 4762
daa4adae 4763 if (dedicated_output_section)
906e58ca 4764 {
daa4adae
TP		 4765 bfd *output_bfd = htab->obfd;
4766 const char *out_sec_name =
4767 arm_dedicated_stub_output_section_name (stub_type);
4768 link_sec = NULL;
4769 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4770 stub_sec_prefix = out_sec_name;
4771 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4772 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4773 if (out_sec == NULL)
906e58ca 4774 {
90b6238f 4775 _bfd_error_handler (_("no address assigned to the veneers output "
4eca0228 4776 "section %s"), out_sec_name);
daa4adae 4777 return NULL;
906e58ca 4778 }
daa4adae
TP		 4779 }
4780 else
4781 {
c2abbbeb 4782 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4783 link_sec = htab->stub_group[section->id].link_sec;
4784 BFD_ASSERT (link_sec != NULL);
4785 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4786 if (*stub_sec_p == NULL)
4787 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4788 stub_sec_prefix = link_sec->name;
4789 out_sec = link_sec->output_section;
4790 align = htab->nacl_p ? 4 : 3;
906e58ca 4791 }
b38cadfb 4792
daa4adae
TP		 4793 if (*stub_sec_p == NULL)
4794 {
4795 size_t namelen;
4796 bfd_size_type len;
4797 char *s_name;
4798
4799 namelen = strlen (stub_sec_prefix);
4800 len = namelen + sizeof (STUB_SUFFIX);
4801 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4802 if (s_name == NULL)
4803 return NULL;
4804
4805 memcpy (s_name, stub_sec_prefix, namelen);
4806 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4807 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4808 align);
4809 if (*stub_sec_p == NULL)
4810 return NULL;
4811
4812 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4813 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4814 | SEC_KEEP;
4815 }
4816
4817 if (!dedicated_output_section)
4818 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4819
48229727
JB		 4820 if (link_sec_p)
4821 *link_sec_p = link_sec;
b38cadfb 4822
daa4adae 4823 return *stub_sec_p;
48229727
JB		 4824}
4825
4826/* Add a new stub entry to the stub hash. Not all fields of the new
4827 stub entry are initialised. */
4828
4829static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4830elf32_arm_add_stub (const char *stub_name, asection *section,
4831 struct elf32_arm_link_hash_table *htab,
4832 enum elf32_arm_stub_type stub_type)
48229727
JB		 4833{
4834 asection *link_sec;
4835 asection *stub_sec;
4836 struct elf32_arm_stub_hash_entry *stub_entry;
4837
daa4adae
TP		 4838 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4839 stub_type);
48229727
JB		 4840 if (stub_sec == NULL)
4841 return NULL;
906e58ca
NC		 4842
4843 /* Enter this entry into the linker stub hash table. */
4844 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4845 TRUE, FALSE);
4846 if (stub_entry == NULL)
4847 {
6bde4c52
TP		 4848 if (section == NULL)
4849 section = stub_sec;
871b3ab2 4850 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 4851 section->owner, stub_name);
906e58ca
NC		 4852 return NULL;
4853 }
4854
4855 stub_entry->stub_sec = stub_sec;
0955507f 4856 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4857 stub_entry->id_sec = link_sec;
4858
906e58ca
NC		 4859 return stub_entry;
4860}
4861
4862/* Store an Arm insn into an output section not processed by
4863 elf32_arm_write_section. */
4864
4865static void
8029a119
NC		 4866put_arm_insn (struct elf32_arm_link_hash_table * htab,
4867 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4868{
4869 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4870 bfd_putl32 (val, ptr);
4871 else
4872 bfd_putb32 (val, ptr);
4873}
4874
4875/* Store a 16-bit Thumb insn into an output section not processed by
4876 elf32_arm_write_section. */
4877
4878static void
8029a119
NC		 4879put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4880 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4881{
4882 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4883 bfd_putl16 (val, ptr);
4884 else
4885 bfd_putb16 (val, ptr);
4886}
4887
a504d23a
LA		 4888/* Store a Thumb2 insn into an output section not processed by
4889 elf32_arm_write_section. */
4890
4891static void
4892put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4893 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4894{
4895 /* T2 instructions are 16-bit streamed. */
4896 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4897 {
4898 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4899 bfd_putl16 ((val & 0xffff), ptr + 2);
4900 }
4901 else
4902 {
4903 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4904 bfd_putb16 ((val & 0xffff), ptr + 2);
4905 }
4906}
4907
0855e32b
NS		 4908/* If it's possible to change R_TYPE to a more efficient access
4909 model, return the new reloc type. */
4910
4911static unsigned
b38cadfb 4912elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4913 struct elf_link_hash_entry *h)
4914{
4915 int is_local = (h == NULL);
4916
9cb09e33 4917 if (bfd_link_dll (info)
0e1862bb 4918 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4919 return r_type;
4920
b38cadfb 4921 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4922 switch (r_type)
4923 {
4924 case R_ARM_TLS_GOTDESC:
4925 case R_ARM_TLS_CALL:
4926 case R_ARM_THM_TLS_CALL:
4927 case R_ARM_TLS_DESCSEQ:
4928 case R_ARM_THM_TLS_DESCSEQ:
4929 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4930 }
4931
4932 return r_type;
4933}
4934
48229727
JB		 4935static bfd_reloc_status_type elf32_arm_final_link_relocate
4936 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4937 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4938 const char *, unsigned char, enum arm_st_branch_type,
4939 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4940
4563a860
JB		 4941static unsigned int
4942arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4943{
4944 switch (stub_type)
4945 {
4946 case arm_stub_a8_veneer_b_cond:
4947 case arm_stub_a8_veneer_b:
4948 case arm_stub_a8_veneer_bl:
4949 return 2;
4950
4951 case arm_stub_long_branch_any_any:
4952 case arm_stub_long_branch_v4t_arm_thumb:
4953 case arm_stub_long_branch_thumb_only:
80c135e5 4954 case arm_stub_long_branch_thumb2_only:
d5a67c02 4955 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4956 case arm_stub_long_branch_v4t_thumb_thumb:
4957 case arm_stub_long_branch_v4t_thumb_arm:
4958 case arm_stub_short_branch_v4t_thumb_arm:
4959 case arm_stub_long_branch_any_arm_pic:
4960 case arm_stub_long_branch_any_thumb_pic:
4961 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4962 case arm_stub_long_branch_v4t_arm_thumb_pic:
4963 case arm_stub_long_branch_v4t_thumb_arm_pic:
4964 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4965 case arm_stub_long_branch_any_tls_pic:
4966 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4967 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4968 case arm_stub_a8_veneer_blx:
4969 return 4;
b38cadfb 4970
7a89b94e
NC		 4971 case arm_stub_long_branch_arm_nacl:
4972 case arm_stub_long_branch_arm_nacl_pic:
4973 return 16;
4974
4563a860
JB		 4975 default:
4976 abort (); /* Should be unreachable. */
4977 }
4978}
4979
4f4faa4d
TP		 4980/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4981 veneering (TRUE) or have their own symbol (FALSE). */
4982
4983static bfd_boolean
4984arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4985{
4986 if (stub_type >= max_stub_type)
4987 abort (); /* Should be unreachable. */
4988
4ba2ef8f
TP		 4989 switch (stub_type)
4990 {
4991 case arm_stub_cmse_branch_thumb_only:
4992 return TRUE;
4993
4994 default:
4995 return FALSE;
4996 }
4997
4998 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4999}
5000
d7c5bd02
TP		 5001/* Returns the padding needed for the dedicated section used stubs of type
5002 STUB_TYPE. */
5003
5004static int
5005arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
5006{
5007 if (stub_type >= max_stub_type)
5008 abort (); /* Should be unreachable. */
5009
4ba2ef8f
TP		 5010 switch (stub_type)
5011 {
5012 case arm_stub_cmse_branch_thumb_only:
5013 return 32;
5014
5015 default:
5016 return 0;
5017 }
5018
5019 abort (); /* Should be unreachable. */
d7c5bd02
TP		 5020}
5021
0955507f
TP		 5022/* If veneers of type STUB_TYPE should go in a dedicated output section,
5023 returns the address of the hash table field in HTAB holding the offset at
5024 which new veneers should be layed out in the stub section. */
5025
5026static bfd_vma*
5027arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
5028 enum elf32_arm_stub_type stub_type)
5029{
5030 switch (stub_type)
5031 {
5032 case arm_stub_cmse_branch_thumb_only:
5033 return &htab->new_cmse_stub_offset;
5034
5035 default:
5036 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
5037 return NULL;
5038 }
5039}
5040
906e58ca
NC		 5041static bfd_boolean
5042arm_build_one_stub (struct bfd_hash_entry *gen_entry,
5043 void * in_arg)
5044{
7a89b94e 5045#define MAXRELOCS 3
0955507f 5046 bfd_boolean removed_sg_veneer;
906e58ca 5047 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 5048 struct elf32_arm_link_hash_table *globals;
906e58ca 5049 struct bfd_link_info *info;
906e58ca
NC		 5050 asection *stub_sec;
5051 bfd *stub_bfd;
906e58ca
NC		 5052 bfd_byte *loc;
5053 bfd_vma sym_value;
5054 int template_size;
5055 int size;
d3ce72d0 5056 const insn_sequence *template_sequence;
906e58ca 5057 int i;
48229727
JB		 5058 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
5059 int stub_reloc_offset[MAXRELOCS] = {0, 0};
5060 int nrelocs = 0;
0955507f 5061 int just_allocated = 0;
906e58ca
NC		 5062
5063 /* Massage our args to the form they really have. */
5064 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5065 info = (struct bfd_link_info *) in_arg;
5066
5067 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 5068 if (globals == NULL)
5069 return FALSE;
906e58ca 5070
906e58ca
NC		 5071 stub_sec = stub_entry->stub_sec;
5072
4dfe6ac6 5073 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 5074 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
5075 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 5076 return TRUE;
fe33d2fa 5077
0955507f
TP		 5078 /* Assign a slot at the end of section if none assigned yet. */
5079 if (stub_entry->stub_offset == (bfd_vma) -1)
5080 {
5081 stub_entry->stub_offset = stub_sec->size;
5082 just_allocated = 1;
5083 }
906e58ca
NC		 5084 loc = stub_sec->contents + stub_entry->stub_offset;
5085
5086 stub_bfd = stub_sec->owner;
5087
906e58ca
NC		 5088 /* This is the address of the stub destination. */
5089 sym_value = (stub_entry->target_value
5090 + stub_entry->target_section->output_offset
5091 + stub_entry->target_section->output_section->vma);
5092
d3ce72d0 5093 template_sequence = stub_entry->stub_template;
461a49ca 5094 template_size = stub_entry->stub_template_size;
906e58ca
NC		 5095
5096 size = 0;
461a49ca 5097 for (i = 0; i < template_size; i++)
906e58ca 5098 {
d3ce72d0 5099 switch (template_sequence[i].type)
461a49ca
DJ		 5100 {
5101 case THUMB16_TYPE:
48229727 5102 {
d3ce72d0
NC		 5103 bfd_vma data = (bfd_vma) template_sequence[i].data;
5104 if (template_sequence[i].reloc_addend != 0)
48229727 5105 {
99059e56
RM		 5106 /* We've borrowed the reloc_addend field to mean we should
5107 insert a condition code into this (Thumb-1 branch)
5108 instruction. See THUMB16_BCOND_INSN. */
5109 BFD_ASSERT ((data & 0xff00) == 0xd000);
5110 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 5111 }
fe33d2fa 5112 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 5113 size += 2;
5114 }
461a49ca 5115 break;
906e58ca 5116
48229727 5117 case THUMB32_TYPE:
fe33d2fa
CL		 5118 bfd_put_16 (stub_bfd,
5119 (template_sequence[i].data >> 16) & 0xffff,
5120 loc + size);
5121 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
5122 loc + size + 2);
99059e56
RM		 5123 if (template_sequence[i].r_type != R_ARM_NONE)
5124 {
5125 stub_reloc_idx[nrelocs] = i;
5126 stub_reloc_offset[nrelocs++] = size;
5127 }
5128 size += 4;
5129 break;
48229727 5130
461a49ca 5131 case ARM_TYPE:
fe33d2fa
CL		 5132 bfd_put_32 (stub_bfd, template_sequence[i].data,
5133 loc + size);
461a49ca
DJ		 5134 /* Handle cases where the target is encoded within the
5135 instruction. */
d3ce72d0 5136 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 5137 {
48229727
JB		 5138 stub_reloc_idx[nrelocs] = i;
5139 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5140 }
5141 size += 4;
5142 break;
5143
5144 case DATA_TYPE:
d3ce72d0 5145 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 5146 stub_reloc_idx[nrelocs] = i;
5147 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5148 size += 4;
5149 break;
5150
5151 default:
5152 BFD_FAIL ();
5153 return FALSE;
5154 }
906e58ca 5155 }
461a49ca 5156
0955507f
TP		 5157 if (just_allocated)
5158 stub_sec->size += size;
906e58ca 5159
461a49ca
DJ		 5160 /* Stub size has already been computed in arm_size_one_stub. Check
5161 consistency. */
5162 BFD_ASSERT (size == stub_entry->stub_size);
5163
906e58ca 5164 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 5165 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 5166 sym_value |= 1;
5167
0955507f
TP		 5168 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5169 to relocate in each stub. */
5170 removed_sg_veneer =
5171 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5172 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 5173
48229727 5174 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 5175 {
5176 Elf_Internal_Rela rel;
5177 bfd_boolean unresolved_reloc;
5178 char *error_message;
5179 bfd_vma points_to =
5180 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
5181
5182 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
5183 rel.r_info = ELF32_R_INFO (0,
5184 template_sequence[stub_reloc_idx[i]].r_type);
5185 rel.r_addend = 0;
5186
5187 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
5188 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5189 template should refer back to the instruction after the original
5190 branch. We use target_section as Cortex-A8 erratum workaround stubs
5191 are only generated when both source and target are in the same
5192 section. */
5193 points_to = stub_entry->target_section->output_section->vma
5194 + stub_entry->target_section->output_offset
5195 + stub_entry->source_value;
5196
5197 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
5198 (template_sequence[stub_reloc_idx[i]].r_type),
5199 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
5200 points_to, info, stub_entry->target_section, "", STT_FUNC,
5201 stub_entry->branch_type,
5202 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
5203 &error_message);
5204 }
906e58ca
NC		 5205
5206 return TRUE;
48229727 5207#undef MAXRELOCS
906e58ca
NC		 5208}
5209
48229727
JB		 5210/* Calculate the template, template size and instruction size for a stub.
5211 Return value is the instruction size. */
906e58ca 5212
48229727
JB		 5213static unsigned int
5214find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
5215 const insn_sequence **stub_template,
5216 int *stub_template_size)
906e58ca 5217{
d3ce72d0 5218 const insn_sequence *template_sequence = NULL;
48229727
JB		 5219 int template_size = 0, i;
5220 unsigned int size;
906e58ca 5221
d3ce72d0 5222 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 5223 if (stub_template)
5224 *stub_template = template_sequence;
5225
48229727 5226 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 5227 if (stub_template_size)
5228 *stub_template_size = template_size;
906e58ca
NC		 5229
5230 size = 0;
461a49ca
DJ		 5231 for (i = 0; i < template_size; i++)
5232 {
d3ce72d0 5233 switch (template_sequence[i].type)
461a49ca
DJ		 5234 {
5235 case THUMB16_TYPE:
5236 size += 2;
5237 break;
5238
5239 case ARM_TYPE:
48229727 5240 case THUMB32_TYPE:
461a49ca
DJ		 5241 case DATA_TYPE:
5242 size += 4;
5243 break;
5244
5245 default:
5246 BFD_FAIL ();
2a229407 5247 return 0;
461a49ca
DJ		 5248 }
5249 }
5250
48229727
JB		 5251 return size;
5252}
5253
5254/* As above, but don't actually build the stub. Just bump offset so
5255 we know stub section sizes. */
5256
5257static bfd_boolean
5258arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 5259 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 5260{
5261 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 5262 const insn_sequence *template_sequence;
48229727
JB		 5263 int template_size, size;
5264
5265 /* Massage our args to the form they really have. */
5266 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 5267
5268 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
5269 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
5270
d3ce72d0 5271 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 5272 &template_size);
5273
0955507f
TP		 5274 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5275 if (stub_entry->stub_template_size)
5276 {
5277 stub_entry->stub_size = size;
5278 stub_entry->stub_template = template_sequence;
5279 stub_entry->stub_template_size = template_size;
5280 }
5281
5282 /* Already accounted for. */
5283 if (stub_entry->stub_offset != (bfd_vma) -1)
5284 return TRUE;
461a49ca 5285
906e58ca
NC		 5286 size = (size + 7) & ~7;
5287 stub_entry->stub_sec->size += size;
461a49ca 5288
906e58ca
NC		 5289 return TRUE;
5290}
5291
5292/* External entry points for sizing and building linker stubs. */
5293
5294/* Set up various things so that we can make a list of input sections
5295 for each output section included in the link. Returns -1 on error,
5296 0 when no stubs will be needed, and 1 on success. */
5297
5298int
5299elf32_arm_setup_section_lists (bfd *output_bfd,
5300 struct bfd_link_info *info)
5301{
5302 bfd *input_bfd;
5303 unsigned int bfd_count;
7292b3ac 5304 unsigned int top_id, top_index;
906e58ca
NC		 5305 asection *section;
5306 asection **input_list, **list;
5307 bfd_size_type amt;
5308 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5309
4dfe6ac6
NC		 5310 if (htab == NULL)
5311 return 0;
906e58ca
NC		 5312 if (! is_elf_hash_table (htab))
5313 return 0;
5314
5315 /* Count the number of input BFDs and find the top input section id. */
5316 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
5317 input_bfd != NULL;
c72f2fb2 5318 input_bfd = input_bfd->link.next)
906e58ca
NC		 5319 {
5320 bfd_count += 1;
5321 for (section = input_bfd->sections;
5322 section != NULL;
5323 section = section->next)
5324 {
5325 if (top_id < section->id)
5326 top_id = section->id;
5327 }
5328 }
5329 htab->bfd_count = bfd_count;
5330
5331 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 5332 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 5333 if (htab->stub_group == NULL)
5334 return -1;
fe33d2fa 5335 htab->top_id = top_id;
906e58ca
NC		 5336
5337 /* We can't use output_bfd->section_count here to find the top output
5338 section index as some sections may have been removed, and
5339 _bfd_strip_section_from_output doesn't renumber the indices. */
5340 for (section = output_bfd->sections, top_index = 0;
5341 section != NULL;
5342 section = section->next)
5343 {
5344 if (top_index < section->index)
5345 top_index = section->index;
5346 }
5347
5348 htab->top_index = top_index;
5349 amt = sizeof (asection *) * (top_index + 1);
21d799b5 5350 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 5351 htab->input_list = input_list;
5352 if (input_list == NULL)
5353 return -1;
5354
5355 /* For sections we aren't interested in, mark their entries with a
5356 value we can check later. */
5357 list = input_list + top_index;
5358 do
5359 *list = bfd_abs_section_ptr;
5360 while (list-- != input_list);
5361
5362 for (section = output_bfd->sections;
5363 section != NULL;
5364 section = section->next)
5365 {
5366 if ((section->flags & SEC_CODE) != 0)
5367 input_list[section->index] = NULL;
5368 }
5369
5370 return 1;
5371}
5372
5373/* The linker repeatedly calls this function for each input section,
5374 in the order that input sections are linked into output sections.
5375 Build lists of input sections to determine groupings between which
5376 we may insert linker stubs. */
5377
5378void
5379elf32_arm_next_input_section (struct bfd_link_info *info,
5380 asection *isec)
5381{
5382 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5383
4dfe6ac6
NC		 5384 if (htab == NULL)
5385 return;
5386
906e58ca
NC		 5387 if (isec->output_section->index <= htab->top_index)
5388 {
5389 asection **list = htab->input_list + isec->output_section->index;
5390
a7470592 5391 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5392 {
5393 /* Steal the link_sec pointer for our list. */
5394#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5395 /* This happens to make the list in reverse order,
07d72278 5396 which we reverse later. */
906e58ca
NC		 5397 PREV_SEC (isec) = *list;
5398 *list = isec;
5399 }
5400 }
5401}
5402
5403/* See whether we can group stub sections together. Grouping stub
5404 sections may result in fewer stubs. More importantly, we need to
07d72278 5405 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5406 .fini output sections respectively, because glibc splits the
5407 _init and _fini functions into multiple parts. Putting a stub in
5408 the middle of a function is not a good idea. */
5409
5410static void
5411group_sections (struct elf32_arm_link_hash_table *htab,
5412 bfd_size_type stub_group_size,
07d72278 5413 bfd_boolean stubs_always_after_branch)
906e58ca 5414{
07d72278 5415 asection **list = htab->input_list;
906e58ca
NC		 5416
5417 do
5418 {
5419 asection *tail = *list;
07d72278 5420 asection *head;
906e58ca
NC		 5421
5422 if (tail == bfd_abs_section_ptr)
5423 continue;
5424
07d72278
DJ		 5425 /* Reverse the list: we must avoid placing stubs at the
5426 beginning of the section because the beginning of the text
5427 section may be required for an interrupt vector in bare metal
5428 code. */
5429#define NEXT_SEC PREV_SEC
e780aef2
CL		 5430 head = NULL;
5431 while (tail != NULL)
99059e56
RM		 5432 {
5433 /* Pop from tail. */
5434 asection *item = tail;
5435 tail = PREV_SEC (item);
e780aef2 5436
99059e56
RM		 5437 /* Push on head. */
5438 NEXT_SEC (item) = head;
5439 head = item;
5440 }
07d72278
DJ		 5441
5442 while (head != NULL)
906e58ca
NC		 5443 {
5444 asection *curr;
07d72278 5445 asection *next;
e780aef2
CL		 5446 bfd_vma stub_group_start = head->output_offset;
5447 bfd_vma end_of_next;
906e58ca 5448
07d72278 5449 curr = head;
e780aef2 5450 while (NEXT_SEC (curr) != NULL)
8cd931b7 5451 {
e780aef2
CL		 5452 next = NEXT_SEC (curr);
5453 end_of_next = next->output_offset + next->size;
5454 if (end_of_next - stub_group_start >= stub_group_size)
5455 /* End of NEXT is too far from start, so stop. */
8cd931b7 5456 break;
e780aef2
CL		 5457 /* Add NEXT to the group. */
5458 curr = next;
8cd931b7 5459 }
906e58ca 5460
07d72278 5461 /* OK, the size from the start to the start of CURR is less
906e58ca 5462 than stub_group_size and thus can be handled by one stub
07d72278 5463 section. (Or the head section is itself larger than
906e58ca
NC		 5464 stub_group_size, in which case we may be toast.)
5465 We should really be keeping track of the total size of
5466 stubs added here, as stubs contribute to the final output
7fb9f789 5467 section size. */
906e58ca
NC		 5468 do
5469 {
07d72278 5470 next = NEXT_SEC (head);
906e58ca 5471 /* Set up this stub group. */
07d72278 5472 htab->stub_group[head->id].link_sec = curr;
906e58ca 5473 }
07d72278 5474 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5475
5476 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5477 bytes after the stub section can be handled by it too. */
5478 if (!stubs_always_after_branch)
906e58ca 5479 {
e780aef2
CL		 5480 stub_group_start = curr->output_offset + curr->size;
5481
8cd931b7 5482 while (next != NULL)
906e58ca 5483 {
e780aef2
CL		 5484 end_of_next = next->output_offset + next->size;
5485 if (end_of_next - stub_group_start >= stub_group_size)
5486 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5487 break;
e780aef2 5488 /* Add NEXT to the stub group. */
07d72278
DJ		 5489 head = next;
5490 next = NEXT_SEC (head);
5491 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5492 }
5493 }
07d72278 5494 head = next;
906e58ca
NC		 5495 }
5496 }
07d72278 5497 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5498
5499 free (htab->input_list);
5500#undef PREV_SEC
07d72278 5501#undef NEXT_SEC
906e58ca
NC		 5502}
5503
48229727
JB		 5504/* Comparison function for sorting/searching relocations relating to Cortex-A8
5505 erratum fix. */
5506
5507static int
5508a8_reloc_compare (const void *a, const void *b)
5509{
21d799b5
NC		 5510 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5511 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5512
5513 if (ra->from < rb->from)
5514 return -1;
5515 else if (ra->from > rb->from)
5516 return 1;
5517 else
5518 return 0;
5519}
5520
5521static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5522 const char *, char **);
5523
5524/* Helper function to scan code for sequences which might trigger the Cortex-A8
5525 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5526 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5527 otherwise. */
5528
81694485
NC		 5529static bfd_boolean
5530cortex_a8_erratum_scan (bfd *input_bfd,
5531 struct bfd_link_info *info,
48229727
JB		 5532 struct a8_erratum_fix **a8_fixes_p,
5533 unsigned int *num_a8_fixes_p,
5534 unsigned int *a8_fix_table_size_p,
5535 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5536 unsigned int num_a8_relocs,
5537 unsigned prev_num_a8_fixes,
5538 bfd_boolean *stub_changed_p)
48229727
JB		 5539{
5540 asection *section;
5541 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5542 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5543 unsigned int num_a8_fixes = *num_a8_fixes_p;
5544 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5545
4dfe6ac6
NC		 5546 if (htab == NULL)
5547 return FALSE;
5548
48229727
JB		 5549 for (section = input_bfd->sections;
5550 section != NULL;
5551 section = section->next)
5552 {
5553 bfd_byte *contents = NULL;
5554 struct _arm_elf_section_data *sec_data;
5555 unsigned int span;
5556 bfd_vma base_vma;
5557
5558 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5559 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5560 || (section->flags & SEC_EXCLUDE) != 0
5561 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5562 || (section->output_section == bfd_abs_section_ptr))
5563 continue;
48229727
JB		 5564
5565 base_vma = section->output_section->vma + section->output_offset;
5566
5567 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5568 contents = elf_section_data (section)->this_hdr.contents;
48229727 5569 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5570 return TRUE;
48229727
JB		 5571
5572 sec_data = elf32_arm_section_data (section);
5573
5574 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5575 {
5576 unsigned int span_start = sec_data->map[span].vma;
5577 unsigned int span_end = (span == sec_data->mapcount - 1)
5578 ? section->size : sec_data->map[span + 1].vma;
5579 unsigned int i;
5580 char span_type = sec_data->map[span].type;
5581 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5582
5583 if (span_type != 't')
5584 continue;
5585
5586 /* Span is entirely within a single 4KB region: skip scanning. */
5587 if (((base_vma + span_start) & ~0xfff)
48229727 5588 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5589 continue;
5590
5591 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5592
5593 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5594 * The branch target is in the same 4KB region as the
5595 first half of the branch.
5596 * The instruction before the branch is a 32-bit
5597 length non-branch instruction. */
5598 for (i = span_start; i < span_end;)
5599 {
5600 unsigned int insn = bfd_getl16 (&contents[i]);
5601 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5602 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5603
99059e56
RM		 5604 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5605 insn_32bit = TRUE;
48229727
JB		 5606
5607 if (insn_32bit)
99059e56
RM		 5608 {
5609 /* Load the rest of the insn (in manual-friendly order). */
5610 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5611
5612 /* Encoding T4: B<c>.W. */
5613 is_b = (insn & 0xf800d000) == 0xf0009000;
5614 /* Encoding T1: BL<c>.W. */
5615 is_bl = (insn & 0xf800d000) == 0xf000d000;
5616 /* Encoding T2: BLX<c>.W. */
5617 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5618 /* Encoding T3: B<c>.W (not permitted in IT block). */
5619 is_bcc = (insn & 0xf800d000) == 0xf0008000
5620 && (insn & 0x07f00000) != 0x03800000;
5621 }
5622
5623 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5624
99059e56 5625 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5626 && insn_32bit
5627 && is_32bit_branch
5628 && last_was_32bit
5629 && ! last_was_branch)
99059e56
RM		 5630 {
5631 bfd_signed_vma offset = 0;
5632 bfd_boolean force_target_arm = FALSE;
48229727 5633 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5634 bfd_vma target;
5635 enum elf32_arm_stub_type stub_type = arm_stub_none;
5636 struct a8_erratum_reloc key, *found;
5637 bfd_boolean use_plt = FALSE;
48229727 5638
99059e56
RM		 5639 key.from = base_vma + i;
5640 found = (struct a8_erratum_reloc *)
5641 bsearch (&key, a8_relocs, num_a8_relocs,
5642 sizeof (struct a8_erratum_reloc),
5643 &a8_reloc_compare);
48229727
JB		 5644
5645 if (found)
5646 {
5647 char *error_message = NULL;
5648 struct elf_link_hash_entry *entry;
5649
5650 /* We don't care about the error returned from this
99059e56 5651 function, only if there is glue or not. */
48229727
JB		 5652 entry = find_thumb_glue (info, found->sym_name,
5653 &error_message);
5654
5655 if (entry)
5656 found->non_a8_stub = TRUE;
5657
92750f34 5658 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5659 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5660 && found->hash->root.plt.offset != (bfd_vma) -1)
5661 use_plt = TRUE;
5662
5663 if (found->r_type == R_ARM_THM_CALL)
5664 {
35fc36a8
RS		 5665 if (found->branch_type == ST_BRANCH_TO_ARM
5666 || use_plt)
92750f34
DJ		 5667 force_target_arm = TRUE;
5668 else
5669 force_target_thumb = TRUE;
5670 }
48229727
JB		 5671 }
5672
99059e56 5673 /* Check if we have an offending branch instruction. */
48229727
JB		 5674
5675 if (found && found->non_a8_stub)
5676 /* We've already made a stub for this instruction, e.g.
5677 it's a long branch or a Thumb->ARM stub. Assume that
5678 stub will suffice to work around the A8 erratum (see
5679 setting of always_after_branch above). */
5680 ;
99059e56
RM		 5681 else if (is_bcc)
5682 {
5683 offset = (insn & 0x7ff) << 1;
5684 offset |= (insn & 0x3f0000) >> 4;
5685 offset |= (insn & 0x2000) ? 0x40000 : 0;
5686 offset |= (insn & 0x800) ? 0x80000 : 0;
5687 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5688 if (offset & 0x100000)
5689 offset |= ~ ((bfd_signed_vma) 0xfffff);
5690 stub_type = arm_stub_a8_veneer_b_cond;
5691 }
5692 else if (is_b || is_bl || is_blx)
5693 {
5694 int s = (insn & 0x4000000) != 0;
5695 int j1 = (insn & 0x2000) != 0;
5696 int j2 = (insn & 0x800) != 0;
5697 int i1 = !(j1 ^ s);
5698 int i2 = !(j2 ^ s);
5699
5700 offset = (insn & 0x7ff) << 1;
5701 offset |= (insn & 0x3ff0000) >> 4;
5702 offset |= i2 << 22;
5703 offset |= i1 << 23;
5704 offset |= s << 24;
5705 if (offset & 0x1000000)
5706 offset |= ~ ((bfd_signed_vma) 0xffffff);
5707
5708 if (is_blx)
5709 offset &= ~ ((bfd_signed_vma) 3);
5710
5711 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5712 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5713 }
5714
5715 if (stub_type != arm_stub_none)
5716 {
5717 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5718
5719 /* The original instruction is a BL, but the target is
99059e56 5720 an ARM instruction. If we were not making a stub,
48229727
JB		 5721 the BL would have been converted to a BLX. Use the
5722 BLX stub instead in that case. */
5723 if (htab->use_blx && force_target_arm
5724 && stub_type == arm_stub_a8_veneer_bl)
5725 {
5726 stub_type = arm_stub_a8_veneer_blx;
5727 is_blx = TRUE;
5728 is_bl = FALSE;
5729 }
5730 /* Conversely, if the original instruction was
5731 BLX but the target is Thumb mode, use the BL
5732 stub. */
5733 else if (force_target_thumb
5734 && stub_type == arm_stub_a8_veneer_blx)
5735 {
5736 stub_type = arm_stub_a8_veneer_bl;
5737 is_blx = FALSE;
5738 is_bl = TRUE;
5739 }
5740
99059e56
RM		 5741 if (is_blx)
5742 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5743
99059e56
RM		 5744 /* If we found a relocation, use the proper destination,
5745 not the offset in the (unrelocated) instruction.
48229727
JB		 5746 Note this is always done if we switched the stub type
5747 above. */
99059e56
RM		 5748 if (found)
5749 offset =
81694485 5750 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5751
99059e56
RM		 5752 /* If the stub will use a Thumb-mode branch to a
5753 PLT target, redirect it to the preceding Thumb
5754 entry point. */
5755 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5756 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5757
99059e56 5758 target = pc_for_insn + offset;
48229727 5759
99059e56
RM		 5760 /* The BLX stub is ARM-mode code. Adjust the offset to
5761 take the different PC value (+8 instead of +4) into
48229727 5762 account. */
99059e56
RM		 5763 if (stub_type == arm_stub_a8_veneer_blx)
5764 offset += 4;
5765
5766 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5767 {
5768 char *stub_name = NULL;
5769
5770 if (num_a8_fixes == a8_fix_table_size)
5771 {
5772 a8_fix_table_size *= 2;
5773 a8_fixes = (struct a8_erratum_fix *)
5774 bfd_realloc (a8_fixes,
5775 sizeof (struct a8_erratum_fix)
5776 * a8_fix_table_size);
5777 }
48229727 5778
eb7c4339
NS		 5779 if (num_a8_fixes < prev_num_a8_fixes)
5780 {
5781 /* If we're doing a subsequent scan,
5782 check if we've found the same fix as
5783 before, and try and reuse the stub
5784 name. */
5785 stub_name = a8_fixes[num_a8_fixes].stub_name;
5786 if ((a8_fixes[num_a8_fixes].section != section)
5787 || (a8_fixes[num_a8_fixes].offset != i))
5788 {
5789 free (stub_name);
5790 stub_name = NULL;
5791 *stub_changed_p = TRUE;
5792 }
5793 }
5794
5795 if (!stub_name)
5796 {
21d799b5 5797 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5798 if (stub_name != NULL)
5799 sprintf (stub_name, "%x:%x", section->id, i);
5800 }
48229727 5801
99059e56
RM		 5802 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5803 a8_fixes[num_a8_fixes].section = section;
5804 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5805 a8_fixes[num_a8_fixes].target_offset =
5806 target - base_vma;
99059e56
RM		 5807 a8_fixes[num_a8_fixes].orig_insn = insn;
5808 a8_fixes[num_a8_fixes].stub_name = stub_name;
5809 a8_fixes[num_a8_fixes].stub_type = stub_type;
5810 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5811 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5812
99059e56
RM		 5813 num_a8_fixes++;
5814 }
5815 }
5816 }
48229727 5817
99059e56
RM		 5818 i += insn_32bit ? 4 : 2;
5819 last_was_32bit = insn_32bit;
48229727 5820 last_was_branch = is_32bit_branch;
99059e56
RM		 5821 }
5822 }
48229727
JB		 5823
5824 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5825 free (contents);
48229727 5826 }
fe33d2fa 5827
48229727
JB		 5828 *a8_fixes_p = a8_fixes;
5829 *num_a8_fixes_p = num_a8_fixes;
5830 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5831
81694485 5832 return FALSE;
48229727
JB		 5833}
5834
b715f643
TP		 5835/* Create or update a stub entry depending on whether the stub can already be
5836 found in HTAB. The stub is identified by:
5837 - its type STUB_TYPE
5838 - its source branch (note that several can share the same stub) whose
5839 section and relocation (if any) are given by SECTION and IRELA
5840 respectively
5841 - its target symbol whose input section, hash, name, value and branch type
5842 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5843 respectively
5844
5845 If found, the value of the stub's target symbol is updated from SYM_VALUE
5846 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5847 TRUE and the stub entry is initialized.
5848
0955507f
TP		 5849 Returns the stub that was created or updated, or NULL if an error
5850 occurred. */
b715f643 5851
0955507f 5852static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5853elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5854 enum elf32_arm_stub_type stub_type, asection *section,
5855 Elf_Internal_Rela *irela, asection *sym_sec,
5856 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5857 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5858 bfd_boolean *new_stub)
5859{
5860 const asection *id_sec;
5861 char *stub_name;
5862 struct elf32_arm_stub_hash_entry *stub_entry;
5863 unsigned int r_type;
4f4faa4d 5864 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5865
5866 BFD_ASSERT (stub_type != arm_stub_none);
5867 *new_stub = FALSE;
5868
4f4faa4d
TP		 5869 if (sym_claimed)
5870 stub_name = sym_name;
5871 else
5872 {
5873 BFD_ASSERT (irela);
5874 BFD_ASSERT (section);
c2abbbeb 5875 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5876
4f4faa4d
TP		 5877 /* Support for grouping stub sections. */
5878 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5879
4f4faa4d
TP		 5880 /* Get the name of this stub. */
5881 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5882 stub_type);
5883 if (!stub_name)
0955507f 5884 return NULL;
4f4faa4d 5885 }
b715f643
TP		 5886
5887 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5888 FALSE);
5889 /* The proper stub has already been created, just update its value. */
5890 if (stub_entry != NULL)
5891 {
4f4faa4d
TP		 5892 if (!sym_claimed)
5893 free (stub_name);
b715f643 5894 stub_entry->target_value = sym_value;
0955507f 5895 return stub_entry;
b715f643
TP		 5896 }
5897
daa4adae 5898 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5899 if (stub_entry == NULL)
5900 {
4f4faa4d
TP		 5901 if (!sym_claimed)
5902 free (stub_name);
0955507f 5903 return NULL;
b715f643
TP		 5904 }
5905
5906 stub_entry->target_value = sym_value;
5907 stub_entry->target_section = sym_sec;
5908 stub_entry->stub_type = stub_type;
5909 stub_entry->h = hash;
5910 stub_entry->branch_type = branch_type;
5911
4f4faa4d
TP		 5912 if (sym_claimed)
5913 stub_entry->output_name = sym_name;
5914 else
b715f643 5915 {
4f4faa4d
TP		 5916 if (sym_name == NULL)
5917 sym_name = "unnamed";
5918 stub_entry->output_name = (char *)
5919 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5920 + strlen (sym_name));
5921 if (stub_entry->output_name == NULL)
5922 {
5923 free (stub_name);
0955507f 5924 return NULL;
4f4faa4d 5925 }
b715f643 5926
4f4faa4d
TP		 5927 /* For historical reasons, use the existing names for ARM-to-Thumb and
5928 Thumb-to-ARM stubs. */
5929 r_type = ELF32_R_TYPE (irela->r_info);
5930 if ((r_type == (unsigned int) R_ARM_THM_CALL
5931 || r_type == (unsigned int) R_ARM_THM_JUMP24
5932 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5933 && branch_type == ST_BRANCH_TO_ARM)
5934 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5935 else if ((r_type == (unsigned int) R_ARM_CALL
5936 || r_type == (unsigned int) R_ARM_JUMP24)
5937 && branch_type == ST_BRANCH_TO_THUMB)
5938 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5939 else
5940 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5941 }
b715f643
TP		 5942
5943 *new_stub = TRUE;
0955507f 5944 return stub_entry;
b715f643
TP		 5945}
5946
4ba2ef8f
TP		 5947/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5948 gateway veneer to transition from non secure to secure state and create them
5949 accordingly.
5950
5951 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5952 defines the conditions that govern Secure Gateway veneer creation for a
5953 given symbol <SYM> as follows:
5954 - it has function type
5955 - it has non local binding
5956 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5957 same type, binding and value as <SYM> (called normal symbol).
5958 An entry function can handle secure state transition itself in which case
5959 its special symbol would have a different value from the normal symbol.
5960
5961 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5962 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5963 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5964 created.
4ba2ef8f 5965
0955507f 5966 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5967
5968static bfd_boolean
5969cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5970 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5971 int *cmse_stub_created)
4ba2ef8f
TP		 5972{
5973 const struct elf_backend_data *bed;
5974 Elf_Internal_Shdr *symtab_hdr;
5975 unsigned i, j, sym_count, ext_start;
5976 Elf_Internal_Sym *cmse_sym, *local_syms;
5977 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5978 enum arm_st_branch_type branch_type;
5979 char *sym_name, *lsym_name;
5980 bfd_vma sym_value;
5981 asection *section;
0955507f
TP		 5982 struct elf32_arm_stub_hash_entry *stub_entry;
5983 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5984
5985 bed = get_elf_backend_data (input_bfd);
5986 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5987 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5988 ext_start = symtab_hdr->sh_info;
5989 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5990 && out_attr[Tag_CPU_arch_profile].i == 'M');
5991
5992 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5993 if (local_syms == NULL)
5994 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5995 symtab_hdr->sh_info, 0, NULL, NULL,
5996 NULL);
5997 if (symtab_hdr->sh_info && local_syms == NULL)
5998 return FALSE;
5999
6000 /* Scan symbols. */
6001 for (i = 0; i < sym_count; i++)
6002 {
6003 cmse_invalid = FALSE;
6004
6005 if (i < ext_start)
6006 {
6007 cmse_sym = &local_syms[i];
4ba2ef8f
TP		 6008 sym_name = bfd_elf_string_from_elf_section (input_bfd,
6009 symtab_hdr->sh_link,
6010 cmse_sym->st_name);
baf46cd7
AM		 6011 if (!sym_name || !CONST_STRNEQ (sym_name, CMSE_PREFIX))
6012 continue;
6013
4ba2ef8f
TP		 6014 /* Special symbol with local binding. */
6015 cmse_invalid = TRUE;
6016 }
6017 else
6018 {
6019 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
6020 sym_name = (char *) cmse_hash->root.root.root.string;
baf46cd7 6021 if (!CONST_STRNEQ (sym_name, CMSE_PREFIX))
4ba2ef8f
TP		 6022 continue;
6023
6024 /* Special symbol has incorrect binding or type. */
6025 if ((cmse_hash->root.root.type != bfd_link_hash_defined
6026 && cmse_hash->root.root.type != bfd_link_hash_defweak)
6027 || cmse_hash->root.type != STT_FUNC)
6028 cmse_invalid = TRUE;
6029 }
6030
6031 if (!is_v8m)
6032 {
90b6238f
AM		 6033 _bfd_error_handler (_("%pB: special symbol `%s' only allowed for "
6034 "ARMv8-M architecture or later"),
4eca0228 6035 input_bfd, sym_name);
4ba2ef8f
TP		 6036 is_v8m = TRUE; /* Avoid multiple warning. */
6037 ret = FALSE;
6038 }
6039
6040 if (cmse_invalid)
6041 {
90b6238f
AM		 6042 _bfd_error_handler (_("%pB: invalid special symbol `%s'; it must be"
6043 " a global or weak function symbol"),
4eca0228 6044 input_bfd, sym_name);
4ba2ef8f
TP		 6045 ret = FALSE;
6046 if (i < ext_start)
6047 continue;
6048 }
6049
6050 sym_name += strlen (CMSE_PREFIX);
6051 hash = (struct elf32_arm_link_hash_entry *)
6052 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6053
6054 /* No associated normal symbol or it is neither global nor weak. */
6055 if (!hash
6056 || (hash->root.root.type != bfd_link_hash_defined
6057 && hash->root.root.type != bfd_link_hash_defweak)
6058 || hash->root.type != STT_FUNC)
6059 {
6060 /* Initialize here to avoid warning about use of possibly
6061 uninitialized variable. */
6062 j = 0;
6063
6064 if (!hash)
6065 {
6066 /* Searching for a normal symbol with local binding. */
6067 for (; j < ext_start; j++)
6068 {
6069 lsym_name =
6070 bfd_elf_string_from_elf_section (input_bfd,
6071 symtab_hdr->sh_link,
6072 local_syms[j].st_name);
6073 if (!strcmp (sym_name, lsym_name))
6074 break;
6075 }
6076 }
6077
6078 if (hash || j < ext_start)
6079 {
4eca0228 6080 _bfd_error_handler
90b6238f
AM		 6081 (_("%pB: invalid standard symbol `%s'; it must be "
6082 "a global or weak function symbol"),
6083 input_bfd, sym_name);
4ba2ef8f
TP		 6084 }
6085 else
4eca0228 6086 _bfd_error_handler
90b6238f 6087 (_("%pB: absent standard symbol `%s'"), input_bfd, sym_name);
4ba2ef8f
TP		 6088 ret = FALSE;
6089 if (!hash)
6090 continue;
6091 }
6092
6093 sym_value = hash->root.root.u.def.value;
6094 section = hash->root.root.u.def.section;
6095
6096 if (cmse_hash->root.root.u.def.section != section)
6097 {
4eca0228 6098 _bfd_error_handler
90b6238f 6099 (_("%pB: `%s' and its special symbol are in different sections"),
4ba2ef8f
TP		 6100 input_bfd, sym_name);
6101 ret = FALSE;
6102 }
6103 if (cmse_hash->root.root.u.def.value != sym_value)
6104 continue; /* Ignore: could be an entry function starting with SG. */
6105
6106 /* If this section is a link-once section that will be discarded, then
6107 don't create any stubs. */
6108 if (section->output_section == NULL)
6109 {
4eca0228 6110 _bfd_error_handler
90b6238f 6111 (_("%pB: entry function `%s' not output"), input_bfd, sym_name);
4ba2ef8f
TP		 6112 continue;
6113 }
6114
6115 if (hash->root.size == 0)
6116 {
4eca0228 6117 _bfd_error_handler
90b6238f 6118 (_("%pB: entry function `%s' is empty"), input_bfd, sym_name);
4ba2ef8f
TP		 6119 ret = FALSE;
6120 }
6121
6122 if (!ret)
6123 continue;
6124 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 6125 stub_entry
4ba2ef8f
TP		 6126 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6127 NULL, NULL, section, hash, sym_name,
6128 sym_value, branch_type, &new_stub);
6129
0955507f 6130 if (stub_entry == NULL)
4ba2ef8f
TP		 6131 ret = FALSE;
6132 else
6133 {
6134 BFD_ASSERT (new_stub);
0955507f 6135 (*cmse_stub_created)++;
4ba2ef8f
TP		 6136 }
6137 }
6138
6139 if (!symtab_hdr->contents)
6140 free (local_syms);
6141 return ret;
6142}
6143
0955507f
TP		 6144/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6145 code entry function, ie can be called from non secure code without using a
6146 veneer. */
6147
6148static bfd_boolean
6149cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
6150{
42484486 6151 bfd_byte contents[4];
0955507f
TP		 6152 uint32_t first_insn;
6153 asection *section;
6154 file_ptr offset;
6155 bfd *abfd;
6156
6157 /* Defined symbol of function type. */
6158 if (hash->root.root.type != bfd_link_hash_defined
6159 && hash->root.root.type != bfd_link_hash_defweak)
6160 return FALSE;
6161 if (hash->root.type != STT_FUNC)
6162 return FALSE;
6163
6164 /* Read first instruction. */
6165 section = hash->root.root.u.def.section;
6166 abfd = section->owner;
6167 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 6168 if (!bfd_get_section_contents (abfd, section, contents, offset,
6169 sizeof (contents)))
0955507f
TP		 6170 return FALSE;
6171
42484486
TP		 6172 first_insn = bfd_get_32 (abfd, contents);
6173
6174 /* Starts by SG instruction. */
0955507f
TP		 6175 return first_insn == 0xe97fe97f;
6176}
6177
6178/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6179 secure gateway veneers (ie. the veneers was not in the input import library)
6180 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6181
6182static bfd_boolean
6183arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
6184{
6185 struct elf32_arm_stub_hash_entry *stub_entry;
6186 struct bfd_link_info *info;
6187
6188 /* Massage our args to the form they really have. */
6189 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
6190 info = (struct bfd_link_info *) gen_info;
6191
6192 if (info->out_implib_bfd)
6193 return TRUE;
6194
6195 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
6196 return TRUE;
6197
6198 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 6199 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 6200
6201 return TRUE;
6202}
6203
6204/* Set offset of each secure gateway veneers so that its address remain
6205 identical to the one in the input import library referred by
6206 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6207 (present in input import library but absent from the executable being
6208 linked) or if new veneers appeared and there is no output import library
6209 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6210 number of secure gateway veneers found in the input import library.
6211
6212 The function returns whether an error occurred. If no error occurred,
6213 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6214 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6215 veneer observed set for new veneers to be layed out after. */
6216
6217static bfd_boolean
6218set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
6219 struct elf32_arm_link_hash_table *htab,
6220 int *cmse_stub_created)
6221{
6222 long symsize;
6223 char *sym_name;
6224 flagword flags;
6225 long i, symcount;
6226 bfd *in_implib_bfd;
6227 asection *stub_out_sec;
6228 bfd_boolean ret = TRUE;
6229 Elf_Internal_Sym *intsym;
6230 const char *out_sec_name;
6231 bfd_size_type cmse_stub_size;
6232 asymbol **sympp = NULL, *sym;
6233 struct elf32_arm_link_hash_entry *hash;
6234 const insn_sequence *cmse_stub_template;
6235 struct elf32_arm_stub_hash_entry *stub_entry;
6236 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
6237 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
6238 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
6239
6240 /* No input secure gateway import library. */
6241 if (!htab->in_implib_bfd)
6242 return TRUE;
6243
6244 in_implib_bfd = htab->in_implib_bfd;
6245 if (!htab->cmse_implib)
6246 {
871b3ab2 6247 _bfd_error_handler (_("%pB: --in-implib only supported for Secure "
90b6238f 6248 "Gateway import libraries"), in_implib_bfd);
0955507f
TP		 6249 return FALSE;
6250 }
6251
6252 /* Get symbol table size. */
6253 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
6254 if (symsize < 0)
6255 return FALSE;
6256
6257 /* Read in the input secure gateway import library's symbol table. */
9a733151
AM		 6258 sympp = (asymbol **) bfd_malloc (symsize);
6259 if (sympp == NULL)
6260 return FALSE;
6261
0955507f
TP		 6262 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
6263 if (symcount < 0)
6264 {
6265 ret = FALSE;
6266 goto free_sym_buf;
6267 }
6268
6269 htab->new_cmse_stub_offset = 0;
6270 cmse_stub_size =
6271 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
6272 &cmse_stub_template,
6273 &cmse_stub_template_size);
6274 out_sec_name =
6275 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
6276 stub_out_sec =
6277 bfd_get_section_by_name (htab->obfd, out_sec_name);
6278 if (stub_out_sec != NULL)
6279 cmse_stub_sec_vma = stub_out_sec->vma;
6280
6281 /* Set addresses of veneers mentionned in input secure gateway import
6282 library's symbol table. */
6283 for (i = 0; i < symcount; i++)
6284 {
6285 sym = sympp[i];
6286 flags = sym->flags;
6287 sym_name = (char *) bfd_asymbol_name (sym);
6288 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
6289
6290 if (sym->section != bfd_abs_section_ptr
6291 || !(flags & (BSF_GLOBAL | BSF_WEAK))
6292 || (flags & BSF_FUNCTION) != BSF_FUNCTION
6293 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
6294 != ST_BRANCH_TO_THUMB))
6295 {
90b6238f
AM		 6296 _bfd_error_handler (_("%pB: invalid import library entry: `%s'; "
6297 "symbol should be absolute, global and "
6298 "refer to Thumb functions"),
4eca0228 6299 in_implib_bfd, sym_name);
0955507f
TP		 6300 ret = FALSE;
6301 continue;
6302 }
6303
6304 veneer_value = bfd_asymbol_value (sym);
6305 stub_offset = veneer_value - cmse_stub_sec_vma;
6306 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
6307 FALSE, FALSE);
6308 hash = (struct elf32_arm_link_hash_entry *)
6309 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6310
6311 /* Stub entry should have been created by cmse_scan or the symbol be of
6312 a secure function callable from non secure code. */
6313 if (!stub_entry && !hash)
6314 {
6315 bfd_boolean new_stub;
6316
4eca0228 6317 _bfd_error_handler
90b6238f 6318 (_("entry function `%s' disappeared from secure code"), sym_name);
0955507f
TP		 6319 hash = (struct elf32_arm_link_hash_entry *)
6320 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
6321 stub_entry
6322 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6323 NULL, NULL, bfd_abs_section_ptr, hash,
6324 sym_name, veneer_value,
6325 ST_BRANCH_TO_THUMB, &new_stub);
6326 if (stub_entry == NULL)
6327 ret = FALSE;
6328 else
6329 {
6330 BFD_ASSERT (new_stub);
6331 new_cmse_stubs_created++;
6332 (*cmse_stub_created)++;
6333 }
6334 stub_entry->stub_template_size = stub_entry->stub_size = 0;
6335 stub_entry->stub_offset = stub_offset;
6336 }
6337 /* Symbol found is not callable from non secure code. */
6338 else if (!stub_entry)
6339 {
6340 if (!cmse_entry_fct_p (hash))
6341 {
90b6238f 6342 _bfd_error_handler (_("`%s' refers to a non entry function"),
4eca0228 6343 sym_name);
0955507f
TP		 6344 ret = FALSE;
6345 }
6346 continue;
6347 }
6348 else
6349 {
6350 /* Only stubs for SG veneers should have been created. */
6351 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
6352
6353 /* Check visibility hasn't changed. */
6354 if (!!(flags & BSF_GLOBAL)
6355 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6356 _bfd_error_handler
90b6238f 6357 (_("%pB: visibility of symbol `%s' has changed"), in_implib_bfd,
0955507f
TP		 6358 sym_name);
6359
6360 stub_entry->stub_offset = stub_offset;
6361 }
6362
6363 /* Size should match that of a SG veneer. */
6364 if (intsym->st_size != cmse_stub_size)
6365 {
90b6238f 6366 _bfd_error_handler (_("%pB: incorrect size for symbol `%s'"),
4eca0228 6367 in_implib_bfd, sym_name);
0955507f
TP		 6368 ret = FALSE;
6369 }
6370
6371 /* Previous veneer address is before current SG veneer section. */
6372 if (veneer_value < cmse_stub_sec_vma)
6373 {
6374 /* Avoid offset underflow. */
6375 if (stub_entry)
6376 stub_entry->stub_offset = 0;
6377 stub_offset = 0;
6378 ret = FALSE;
6379 }
6380
6381 /* Complain if stub offset not a multiple of stub size. */
6382 if (stub_offset % cmse_stub_size)
6383 {
4eca0228 6384 _bfd_error_handler
90b6238f
AM		 6385 (_("offset of veneer for entry function `%s' not a multiple of "
6386 "its size"), sym_name);
0955507f
TP		 6387 ret = FALSE;
6388 }
6389
6390 if (!ret)
6391 continue;
6392
6393 new_cmse_stubs_created--;
6394 if (veneer_value < cmse_stub_array_start)
6395 cmse_stub_array_start = veneer_value;
6396 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6397 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6398 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6399 }
6400
6401 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6402 {
6403 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6404 _bfd_error_handler
0955507f
TP		 6405 (_("new entry function(s) introduced but no output import library "
6406 "specified:"));
6407 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6408 }
6409
6410 if (cmse_stub_array_start != cmse_stub_sec_vma)
6411 {
4eca0228 6412 _bfd_error_handler
90b6238f 6413 (_("start address of `%s' is different from previous link"),
0955507f
TP		 6414 out_sec_name);
6415 ret = FALSE;
6416 }
6417
6418free_sym_buf:
6419 free (sympp);
6420 return ret;
6421}
6422
906e58ca
NC		 6423/* Determine and set the size of the stub section for a final link.
6424
6425 The basic idea here is to examine all the relocations looking for
6426 PC-relative calls to a target that is unreachable with a "bl"
6427 instruction. */
6428
6429bfd_boolean
6430elf32_arm_size_stubs (bfd *output_bfd,
6431 bfd *stub_bfd,
6432 struct bfd_link_info *info,
6433 bfd_signed_vma group_size,
7a89b94e 6434 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6435 asection *,
7a89b94e 6436 unsigned int),
906e58ca
NC		 6437 void (*layout_sections_again) (void))
6438{
0955507f 6439 bfd_boolean ret = TRUE;
4ba2ef8f 6440 obj_attribute *out_attr;
0955507f 6441 int cmse_stub_created = 0;
906e58ca 6442 bfd_size_type stub_group_size;
4ba2ef8f 6443 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6444 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6445 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6446 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6447 struct a8_erratum_reloc *a8_relocs = NULL;
6448 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6449
4dfe6ac6
NC		 6450 if (htab == NULL)
6451 return FALSE;
6452
48229727
JB		 6453 if (htab->fix_cortex_a8)
6454 {
21d799b5 6455 a8_fixes = (struct a8_erratum_fix *)
99059e56 6456 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6457 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6458 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6459 }
906e58ca
NC		 6460
6461 /* Propagate mach to stub bfd, because it may not have been
6462 finalized when we created stub_bfd. */
6463 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6464 bfd_get_mach (output_bfd));
6465
6466 /* Stash our params away. */
6467 htab->stub_bfd = stub_bfd;
6468 htab->add_stub_section = add_stub_section;
6469 htab->layout_sections_again = layout_sections_again;
07d72278 6470 stubs_always_after_branch = group_size < 0;
48229727 6471
4ba2ef8f
TP		 6472 out_attr = elf_known_obj_attributes_proc (output_bfd);
6473 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6474
48229727
JB		 6475 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6476 as the first half of a 32-bit branch straddling two 4K pages. This is a
6477 crude way of enforcing that. */
6478 if (htab->fix_cortex_a8)
6479 stubs_always_after_branch = 1;
6480
906e58ca
NC		 6481 if (group_size < 0)
6482 stub_group_size = -group_size;
6483 else
6484 stub_group_size = group_size;
6485
6486 if (stub_group_size == 1)
6487 {
6488 /* Default values. */
6489 /* Thumb branch range is +-4MB has to be used as the default
6490 maximum size (a given section can contain both ARM and Thumb
6491 code, so the worst case has to be taken into account).
6492
6493 This value is 24K less than that, which allows for 2025
6494 12-byte stubs. If we exceed that, then we will fail to link.
6495 The user will have to relink with an explicit group size
6496 option. */
6497 stub_group_size = 4170000;
6498 }
6499
07d72278 6500 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6501
3ae046cc
NS		 6502 /* If we're applying the cortex A8 fix, we need to determine the
6503 program header size now, because we cannot change it later --
6504 that could alter section placements. Notice the A8 erratum fix
6505 ends up requiring the section addresses to remain unchanged
6506 modulo the page size. That's something we cannot represent
6507 inside BFD, and we don't want to force the section alignment to
6508 be the page size. */
6509 if (htab->fix_cortex_a8)
6510 (*htab->layout_sections_again) ();
6511
906e58ca
NC		 6512 while (1)
6513 {
6514 bfd *input_bfd;
6515 unsigned int bfd_indx;
6516 asection *stub_sec;
d7c5bd02 6517 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6518 bfd_boolean stub_changed = FALSE;
6519 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6520
48229727 6521 num_a8_fixes = 0;
906e58ca
NC		 6522 for (input_bfd = info->input_bfds, bfd_indx = 0;
6523 input_bfd != NULL;
c72f2fb2 6524 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6525 {
6526 Elf_Internal_Shdr *symtab_hdr;
6527 asection *section;
6528 Elf_Internal_Sym *local_syms = NULL;
6529
8c246a60
AM		 6530 if (!is_arm_elf (input_bfd)
6531 || (elf_dyn_lib_class (input_bfd) & DYN_AS_NEEDED) != 0)
99059e56 6532 continue;
adbcc655 6533
48229727
JB		 6534 num_a8_relocs = 0;
6535
906e58ca
NC		 6536 /* We'll need the symbol table in a second. */
6537 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6538 if (symtab_hdr->sh_info == 0)
6539 continue;
6540
4ba2ef8f
TP		 6541 /* Limit scan of symbols to object file whose profile is
6542 Microcontroller to not hinder performance in the general case. */
6543 if (m_profile && first_veneer_scan)
6544 {
6545 struct elf_link_hash_entry **sym_hashes;
6546
6547 sym_hashes = elf_sym_hashes (input_bfd);
6548 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6549 &cmse_stub_created))
4ba2ef8f 6550 goto error_ret_free_local;
0955507f
TP		 6551
6552 if (cmse_stub_created != 0)
6553 stub_changed = TRUE;
4ba2ef8f
TP		 6554 }
6555
906e58ca
NC		 6556 /* Walk over each section attached to the input bfd. */
6557 for (section = input_bfd->sections;
6558 section != NULL;
6559 section = section->next)
6560 {
6561 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6562
6563 /* If there aren't any relocs, then there's nothing more
6564 to do. */
6565 if ((section->flags & SEC_RELOC) == 0
6566 || section->reloc_count == 0
6567 || (section->flags & SEC_CODE) == 0)
6568 continue;
6569
6570 /* If this section is a link-once section that will be
6571 discarded, then don't create any stubs. */
6572 if (section->output_section == NULL
6573 || section->output_section->owner != output_bfd)
6574 continue;
6575
6576 /* Get the relocs. */
6577 internal_relocs
6578 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6579 NULL, info->keep_memory);
6580 if (internal_relocs == NULL)
6581 goto error_ret_free_local;
6582
6583 /* Now examine each relocation. */
6584 irela = internal_relocs;
6585 irelaend = irela + section->reloc_count;
6586 for (; irela < irelaend; irela++)
6587 {
6588 unsigned int r_type, r_indx;
906e58ca
NC		 6589 asection *sym_sec;
6590 bfd_vma sym_value;
6591 bfd_vma destination;
6592 struct elf32_arm_link_hash_entry *hash;
7413f23f 6593 const char *sym_name;
34e77a92 6594 unsigned char st_type;
35fc36a8 6595 enum arm_st_branch_type branch_type;
48229727 6596 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6597
6598 r_type = ELF32_R_TYPE (irela->r_info);
6599 r_indx = ELF32_R_SYM (irela->r_info);
6600
6601 if (r_type >= (unsigned int) R_ARM_max)
6602 {
6603 bfd_set_error (bfd_error_bad_value);
6604 error_ret_free_internal:
6605 if (elf_section_data (section)->relocs == NULL)
6606 free (internal_relocs);
15dd01b1
TP		 6607 /* Fall through. */
6608 error_ret_free_local:
6609 if (local_syms != NULL
6610 && (symtab_hdr->contents
6611 != (unsigned char *) local_syms))
6612 free (local_syms);
6613 return FALSE;
906e58ca 6614 }
b38cadfb 6615
0855e32b
NS		 6616 hash = NULL;
6617 if (r_indx >= symtab_hdr->sh_info)
6618 hash = elf32_arm_hash_entry
6619 (elf_sym_hashes (input_bfd)
6620 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6621
0855e32b
NS		 6622 /* Only look for stubs on branch instructions, or
6623 non-relaxed TLSCALL */
906e58ca 6624 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6625 && (r_type != (unsigned int) R_ARM_THM_CALL)
6626 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6627 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6628 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6629 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6630 && (r_type != (unsigned int) R_ARM_PLT32)
6631 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6632 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6633 && r_type == elf32_arm_tls_transition
6634 (info, r_type, &hash->root)
6635 && ((hash ? hash->tls_type
6636 : (elf32_arm_local_got_tls_type
6637 (input_bfd)[r_indx]))
6638 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6639 continue;
6640
6641 /* Now determine the call target, its name, value,
6642 section. */
6643 sym_sec = NULL;
6644 sym_value = 0;
6645 destination = 0;
7413f23f 6646 sym_name = NULL;
b38cadfb 6647
0855e32b
NS		 6648 if (r_type == (unsigned int) R_ARM_TLS_CALL
6649 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6650 {
6651 /* A non-relaxed TLS call. The target is the
6652 plt-resident trampoline and nothing to do
6653 with the symbol. */
6654 BFD_ASSERT (htab->tls_trampoline > 0);
6655 sym_sec = htab->root.splt;
6656 sym_value = htab->tls_trampoline;
6657 hash = 0;
34e77a92 6658 st_type = STT_FUNC;
35fc36a8 6659 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6660 }
6661 else if (!hash)
906e58ca
NC		 6662 {
6663 /* It's a local symbol. */
6664 Elf_Internal_Sym *sym;
906e58ca
NC		 6665
6666 if (local_syms == NULL)
6667 {
6668 local_syms
6669 = (Elf_Internal_Sym *) symtab_hdr->contents;
6670 if (local_syms == NULL)
6671 local_syms
6672 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6673 symtab_hdr->sh_info, 0,
6674 NULL, NULL, NULL);
6675 if (local_syms == NULL)
6676 goto error_ret_free_internal;
6677 }
6678
6679 sym = local_syms + r_indx;
f6d250ce
TS		 6680 if (sym->st_shndx == SHN_UNDEF)
6681 sym_sec = bfd_und_section_ptr;
6682 else if (sym->st_shndx == SHN_ABS)
6683 sym_sec = bfd_abs_section_ptr;
6684 else if (sym->st_shndx == SHN_COMMON)
6685 sym_sec = bfd_com_section_ptr;
6686 else
6687 sym_sec =
6688 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6689
ffcb4889
NS		 6690 if (!sym_sec)
6691 /* This is an undefined symbol. It can never
6a631e86 6692 be resolved. */
ffcb4889 6693 continue;
fe33d2fa 6694
906e58ca
NC		 6695 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6696 sym_value = sym->st_value;
6697 destination = (sym_value + irela->r_addend
6698 + sym_sec->output_offset
6699 + sym_sec->output_section->vma);
34e77a92 6700 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6701 branch_type =
6702 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6703 sym_name
6704 = bfd_elf_string_from_elf_section (input_bfd,
6705 symtab_hdr->sh_link,
6706 sym->st_name);
906e58ca
NC		 6707 }
6708 else
6709 {
6710 /* It's an external symbol. */
906e58ca
NC		 6711 while (hash->root.root.type == bfd_link_hash_indirect
6712 || hash->root.root.type == bfd_link_hash_warning)
6713 hash = ((struct elf32_arm_link_hash_entry *)
6714 hash->root.root.u.i.link);
6715
6716 if (hash->root.root.type == bfd_link_hash_defined
6717 || hash->root.root.type == bfd_link_hash_defweak)
6718 {
6719 sym_sec = hash->root.root.u.def.section;
6720 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6721
6722 struct elf32_arm_link_hash_table *globals =
6723 elf32_arm_hash_table (info);
6724
6725 /* For a destination in a shared library,
6726 use the PLT stub as target address to
6727 decide whether a branch stub is
6728 needed. */
4dfe6ac6 6729 if (globals != NULL
362d30a1 6730 && globals->root.splt != NULL
4dfe6ac6 6731 && hash != NULL
022f8312
CL		 6732 && hash->root.plt.offset != (bfd_vma) -1)
6733 {
362d30a1 6734 sym_sec = globals->root.splt;
022f8312
CL		 6735 sym_value = hash->root.plt.offset;
6736 if (sym_sec->output_section != NULL)
6737 destination = (sym_value
6738 + sym_sec->output_offset
6739 + sym_sec->output_section->vma);
6740 }
6741 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6742 destination = (sym_value + irela->r_addend
6743 + sym_sec->output_offset
6744 + sym_sec->output_section->vma);
6745 }
69c5861e
CL		 6746 else if ((hash->root.root.type == bfd_link_hash_undefined)
6747 || (hash->root.root.type == bfd_link_hash_undefweak))
6748 {
6749 /* For a shared library, use the PLT stub as
6750 target address to decide whether a long
6751 branch stub is needed.
6752 For absolute code, they cannot be handled. */
6753 struct elf32_arm_link_hash_table *globals =
6754 elf32_arm_hash_table (info);
6755
4dfe6ac6 6756 if (globals != NULL
362d30a1 6757 && globals->root.splt != NULL
4dfe6ac6 6758 && hash != NULL
69c5861e
CL		 6759 && hash->root.plt.offset != (bfd_vma) -1)
6760 {
362d30a1 6761 sym_sec = globals->root.splt;
69c5861e
CL		 6762 sym_value = hash->root.plt.offset;
6763 if (sym_sec->output_section != NULL)
6764 destination = (sym_value
6765 + sym_sec->output_offset
6766 + sym_sec->output_section->vma);
6767 }
6768 else
6769 continue;
6770 }
906e58ca
NC		 6771 else
6772 {
6773 bfd_set_error (bfd_error_bad_value);
6774 goto error_ret_free_internal;
6775 }
34e77a92 6776 st_type = hash->root.type;
39d911fc
TP		 6777 branch_type =
6778 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6779 sym_name = hash->root.root.root.string;
906e58ca
NC		 6780 }
6781
48229727 6782 do
7413f23f 6783 {
b715f643 6784 bfd_boolean new_stub;
0955507f 6785 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6786
48229727
JB		 6787 /* Determine what (if any) linker stub is needed. */
6788 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6789 st_type, &branch_type,
6790 hash, destination, sym_sec,
48229727
JB		 6791 input_bfd, sym_name);
6792 if (stub_type == arm_stub_none)
6793 break;
6794
48229727
JB		 6795 /* We've either created a stub for this reloc already,
6796 or we are about to. */
0955507f 6797 stub_entry =
b715f643
TP		 6798 elf32_arm_create_stub (htab, stub_type, section, irela,
6799 sym_sec, hash,
6800 (char *) sym_name, sym_value,
6801 branch_type, &new_stub);
7413f23f 6802
0955507f 6803 created_stub = stub_entry != NULL;
b715f643
TP		 6804 if (!created_stub)
6805 goto error_ret_free_internal;
6806 else if (!new_stub)
6807 break;
99059e56 6808 else
b715f643 6809 stub_changed = TRUE;
99059e56
RM		 6810 }
6811 while (0);
6812
6813 /* Look for relocations which might trigger Cortex-A8
6814 erratum. */
6815 if (htab->fix_cortex_a8
6816 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6817 || r_type == (unsigned int) R_ARM_THM_JUMP19
6818 || r_type == (unsigned int) R_ARM_THM_CALL
6819 || r_type == (unsigned int) R_ARM_THM_XPC22))
6820 {
6821 bfd_vma from = section->output_section->vma
6822 + section->output_offset
6823 + irela->r_offset;
6824
6825 if ((from & 0xfff) == 0xffe)
6826 {
6827 /* Found a candidate. Note we haven't checked the
6828 destination is within 4K here: if we do so (and
6829 don't create an entry in a8_relocs) we can't tell
6830 that a branch should have been relocated when
6831 scanning later. */
6832 if (num_a8_relocs == a8_reloc_table_size)
6833 {
6834 a8_reloc_table_size *= 2;
6835 a8_relocs = (struct a8_erratum_reloc *)
6836 bfd_realloc (a8_relocs,
6837 sizeof (struct a8_erratum_reloc)
6838 * a8_reloc_table_size);
6839 }
6840
6841 a8_relocs[num_a8_relocs].from = from;
6842 a8_relocs[num_a8_relocs].destination = destination;
6843 a8_relocs[num_a8_relocs].r_type = r_type;
6844 a8_relocs[num_a8_relocs].branch_type = branch_type;
6845 a8_relocs[num_a8_relocs].sym_name = sym_name;
6846 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6847 a8_relocs[num_a8_relocs].hash = hash;
6848
6849 num_a8_relocs++;
6850 }
6851 }
906e58ca
NC		 6852 }
6853
99059e56
RM		 6854 /* We're done with the internal relocs, free them. */
6855 if (elf_section_data (section)->relocs == NULL)
6856 free (internal_relocs);
6857 }
48229727 6858
99059e56 6859 if (htab->fix_cortex_a8)
48229727 6860 {
99059e56
RM		 6861 /* Sort relocs which might apply to Cortex-A8 erratum. */
6862 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6863 sizeof (struct a8_erratum_reloc),
99059e56 6864 &a8_reloc_compare);
48229727 6865
99059e56
RM		 6866 /* Scan for branches which might trigger Cortex-A8 erratum. */
6867 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6868 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6869 a8_relocs, num_a8_relocs,
6870 prev_num_a8_fixes, &stub_changed)
6871 != 0)
48229727 6872 goto error_ret_free_local;
5e681ec4 6873 }
7f991970
AM		 6874
6875 if (local_syms != NULL
6876 && symtab_hdr->contents != (unsigned char *) local_syms)
6877 {
6878 if (!info->keep_memory)
6879 free (local_syms);
6880 else
6881 symtab_hdr->contents = (unsigned char *) local_syms;
6882 }
5e681ec4
PB		 6883 }
6884
0955507f
TP		 6885 if (first_veneer_scan
6886 && !set_cmse_veneer_addr_from_implib (info, htab,
6887 &cmse_stub_created))
6888 ret = FALSE;
6889
eb7c4339 6890 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6891 stub_changed = TRUE;
48229727 6892
906e58ca
NC		 6893 if (!stub_changed)
6894 break;
5e681ec4 6895
906e58ca
NC		 6896 /* OK, we've added some stubs. Find out the new size of the
6897 stub sections. */
6898 for (stub_sec = htab->stub_bfd->sections;
6899 stub_sec != NULL;
6900 stub_sec = stub_sec->next)
3e6b1042
DJ		 6901 {
6902 /* Ignore non-stub sections. */
6903 if (!strstr (stub_sec->name, STUB_SUFFIX))
6904 continue;
6905
6906 stub_sec->size = 0;
6907 }
b34b2d70 6908
0955507f
TP		 6909 /* Add new SG veneers after those already in the input import
6910 library. */
6911 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6912 stub_type++)
6913 {
6914 bfd_vma *start_offset_p;
6915 asection **stub_sec_p;
6916
6917 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6918 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6919 if (start_offset_p == NULL)
6920 continue;
6921
6922 BFD_ASSERT (stub_sec_p != NULL);
6923 if (*stub_sec_p != NULL)
6924 (*stub_sec_p)->size = *start_offset_p;
6925 }
6926
d7c5bd02 6927 /* Compute stub section size, considering padding. */
906e58ca 6928 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6929 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6930 stub_type++)
6931 {
6932 int size, padding;
6933 asection **stub_sec_p;
6934
6935 padding = arm_dedicated_stub_section_padding (stub_type);
6936 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6937 /* Skip if no stub input section or no stub section padding
6938 required. */
6939 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6940 continue;
6941 /* Stub section padding required but no dedicated section. */
6942 BFD_ASSERT (stub_sec_p);
6943
6944 size = (*stub_sec_p)->size;
6945 size = (size + padding - 1) & ~(padding - 1);
6946 (*stub_sec_p)->size = size;
6947 }
906e58ca 6948
48229727
JB		 6949 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6950 if (htab->fix_cortex_a8)
99059e56
RM		 6951 for (i = 0; i < num_a8_fixes; i++)
6952 {
48229727 6953 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6954 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6955
6956 if (stub_sec == NULL)
7f991970 6957 return FALSE;
48229727 6958
99059e56
RM		 6959 stub_sec->size
6960 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6961 NULL);
6962 }
48229727
JB		 6963
6964
906e58ca
NC		 6965 /* Ask the linker to do its stuff. */
6966 (*htab->layout_sections_again) ();
4ba2ef8f 6967 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6968 }
6969
48229727
JB		 6970 /* Add stubs for Cortex-A8 erratum fixes now. */
6971 if (htab->fix_cortex_a8)
6972 {
6973 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6974 {
6975 struct elf32_arm_stub_hash_entry *stub_entry;
6976 char *stub_name = a8_fixes[i].stub_name;
6977 asection *section = a8_fixes[i].section;
6978 unsigned int section_id = a8_fixes[i].section->id;
6979 asection *link_sec = htab->stub_group[section_id].link_sec;
6980 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6981 const insn_sequence *template_sequence;
6982 int template_size, size = 0;
6983
6984 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6985 TRUE, FALSE);
6986 if (stub_entry == NULL)
6987 {
871b3ab2 6988 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 6989 section->owner, stub_name);
99059e56
RM		 6990 return FALSE;
6991 }
6992
6993 stub_entry->stub_sec = stub_sec;
0955507f 6994 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6995 stub_entry->id_sec = link_sec;
6996 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6997 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6998 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6999 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 7000 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 7001 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 7002
99059e56
RM		 7003 size = find_stub_size_and_template (a8_fixes[i].stub_type,
7004 &template_sequence,
7005 &template_size);
48229727 7006
99059e56
RM		 7007 stub_entry->stub_size = size;
7008 stub_entry->stub_template = template_sequence;
7009 stub_entry->stub_template_size = template_size;
7010 }
48229727
JB		 7011
7012 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 7013 elf32_arm_write_section(). */
48229727
JB		 7014 htab->a8_erratum_fixes = a8_fixes;
7015 htab->num_a8_erratum_fixes = num_a8_fixes;
7016 }
7017 else
7018 {
7019 htab->a8_erratum_fixes = NULL;
7020 htab->num_a8_erratum_fixes = 0;
7021 }
0955507f 7022 return ret;
5e681ec4
PB		 7023}
7024
906e58ca
NC		 7025/* Build all the stubs associated with the current output file. The
7026 stubs are kept in a hash table attached to the main linker hash
7027 table. We also set up the .plt entries for statically linked PIC
7028 functions here. This function is called via arm_elf_finish in the
7029 linker. */
252b5132 7030
906e58ca
NC		 7031bfd_boolean
7032elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 7033{
906e58ca
NC		 7034 asection *stub_sec;
7035 struct bfd_hash_table *table;
0955507f 7036 enum elf32_arm_stub_type stub_type;
906e58ca 7037 struct elf32_arm_link_hash_table *htab;
252b5132 7038
906e58ca 7039 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 7040 if (htab == NULL)
7041 return FALSE;
252b5132 7042
906e58ca
NC		 7043 for (stub_sec = htab->stub_bfd->sections;
7044 stub_sec != NULL;
7045 stub_sec = stub_sec->next)
252b5132 7046 {
906e58ca
NC		 7047 bfd_size_type size;
7048
8029a119 7049 /* Ignore non-stub sections. */
906e58ca
NC		 7050 if (!strstr (stub_sec->name, STUB_SUFFIX))
7051 continue;
7052
d7c5bd02 7053 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 7054 must at least be done for stub section requiring padding and for SG
7055 veneers to ensure that a non secure code branching to a removed SG
7056 veneer causes an error. */
906e58ca 7057 size = stub_sec->size;
21d799b5 7058 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 7059 if (stub_sec->contents == NULL && size != 0)
7060 return FALSE;
0955507f 7061
906e58ca 7062 stub_sec->size = 0;
252b5132
RH		 7063 }
7064
0955507f
TP		 7065 /* Add new SG veneers after those already in the input import library. */
7066 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7067 {
7068 bfd_vma *start_offset_p;
7069 asection **stub_sec_p;
7070
7071 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
7072 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
7073 if (start_offset_p == NULL)
7074 continue;
7075
7076 BFD_ASSERT (stub_sec_p != NULL);
7077 if (*stub_sec_p != NULL)
7078 (*stub_sec_p)->size = *start_offset_p;
7079 }
7080
906e58ca
NC		 7081 /* Build the stubs as directed by the stub hash table. */
7082 table = &htab->stub_hash_table;
7083 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 7084 if (htab->fix_cortex_a8)
7085 {
7086 /* Place the cortex a8 stubs last. */
7087 htab->fix_cortex_a8 = -1;
7088 bfd_hash_traverse (table, arm_build_one_stub, info);
7089 }
252b5132 7090
906e58ca 7091 return TRUE;
252b5132
RH		 7092}
7093
9b485d32
NC		 7094/* Locate the Thumb encoded calling stub for NAME. */
7095
252b5132 7096static struct elf_link_hash_entry *
57e8b36a
NC		 7097find_thumb_glue (struct bfd_link_info *link_info,
7098 const char *name,
f2a9dd69 7099 char **error_message)
252b5132
RH		 7100{
7101 char *tmp_name;
7102 struct elf_link_hash_entry *hash;
7103 struct elf32_arm_link_hash_table *hash_table;
7104
7105 /* We need a pointer to the armelf specific hash table. */
7106 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7107 if (hash_table == NULL)
7108 return NULL;
252b5132 7109
21d799b5 7110 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7111 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7112
7113 BFD_ASSERT (tmp_name);
7114
7115 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
7116
7117 hash = elf_link_hash_lookup
b34976b6 7118 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7119
b1657152 7120 if (hash == NULL
90b6238f
AM		 7121 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7122 "Thumb", tmp_name, name) == -1)
b1657152 7123 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7124
7125 free (tmp_name);
7126
7127 return hash;
7128}
7129
9b485d32
NC		 7130/* Locate the ARM encoded calling stub for NAME. */
7131
252b5132 7132static struct elf_link_hash_entry *
57e8b36a
NC		 7133find_arm_glue (struct bfd_link_info *link_info,
7134 const char *name,
f2a9dd69 7135 char **error_message)
252b5132
RH		 7136{
7137 char *tmp_name;
7138 struct elf_link_hash_entry *myh;
7139 struct elf32_arm_link_hash_table *hash_table;
7140
7141 /* We need a pointer to the elfarm specific hash table. */
7142 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7143 if (hash_table == NULL)
7144 return NULL;
252b5132 7145
21d799b5 7146 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7147 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7148
7149 BFD_ASSERT (tmp_name);
7150
7151 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7152
7153 myh = elf_link_hash_lookup
b34976b6 7154 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7155
b1657152 7156 if (myh == NULL
90b6238f
AM		 7157 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7158 "ARM", tmp_name, name) == -1)
b1657152 7159 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7160
7161 free (tmp_name);
7162
7163 return myh;
7164}
7165
8f6277f5 7166/* ARM->Thumb glue (static images):
252b5132
RH		 7167
7168 .arm
7169 __func_from_arm:
7170 ldr r12, __func_addr
7171 bx r12
7172 __func_addr:
906e58ca 7173 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 7174
26079076
PB		 7175 (v5t static images)
7176 .arm
7177 __func_from_arm:
7178 ldr pc, __func_addr
7179 __func_addr:
906e58ca 7180 .word func @ behave as if you saw a ARM_32 reloc.
26079076 7181
8f6277f5
PB		 7182 (relocatable images)
7183 .arm
7184 __func_from_arm:
7185 ldr r12, __func_offset
7186 add r12, r12, pc
7187 bx r12
7188 __func_offset:
8029a119 7189 .word func - . */
8f6277f5
PB		 7190
7191#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 7192static const insn32 a2t1_ldr_insn = 0xe59fc000;
7193static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
7194static const insn32 a2t3_func_addr_insn = 0x00000001;
7195
26079076
PB		 7196#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7197static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
7198static const insn32 a2t2v5_func_addr_insn = 0x00000001;
7199
8f6277f5
PB		 7200#define ARM2THUMB_PIC_GLUE_SIZE 16
7201static const insn32 a2t1p_ldr_insn = 0xe59fc004;
7202static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
7203static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
7204
07d6d2b8 7205/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 7206
07d6d2b8
AM		 7207 .thumb .thumb
7208 .align 2 .align 2
7209 __func_from_thumb: __func_from_thumb:
7210 bx pc push {r6, lr}
7211 nop ldr r6, __func_addr
7212 .arm mov lr, pc
7213 b func bx r6
99059e56
RM		 7214 .arm
7215 ;; back_to_thumb
7216 ldmia r13! {r6, lr}
7217 bx lr
7218 __func_addr:
07d6d2b8 7219 .word func */
252b5132
RH		 7220
7221#define THUMB2ARM_GLUE_SIZE 8
7222static const insn16 t2a1_bx_pc_insn = 0x4778;
7223static const insn16 t2a2_noop_insn = 0x46c0;
7224static const insn32 t2a3_b_insn = 0xea000000;
7225
c7b8f16e 7226#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 7227#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7228#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 7229
845b51d6
PB		 7230#define ARM_BX_VENEER_SIZE 12
7231static const insn32 armbx1_tst_insn = 0xe3100001;
7232static const insn32 armbx2_moveq_insn = 0x01a0f000;
7233static const insn32 armbx3_bx_insn = 0xe12fff10;
7234
7e392df6 7235#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 7236static void
7237arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 7238{
7239 asection * s;
8029a119 7240 bfd_byte * contents;
252b5132 7241
8029a119 7242 if (size == 0)
3e6b1042
DJ		 7243 {
7244 /* Do not include empty glue sections in the output. */
7245 if (abfd != NULL)
7246 {
3d4d4302 7247 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 7248 if (s != NULL)
7249 s->flags |= SEC_EXCLUDE;
7250 }
7251 return;
7252 }
252b5132 7253
8029a119 7254 BFD_ASSERT (abfd != NULL);
252b5132 7255
3d4d4302 7256 s = bfd_get_linker_section (abfd, name);
8029a119 7257 BFD_ASSERT (s != NULL);
252b5132 7258
b0f4fbf8 7259 contents = (bfd_byte *) bfd_zalloc (abfd, size);
252b5132 7260
8029a119
NC		 7261 BFD_ASSERT (s->size == size);
7262 s->contents = contents;
7263}
906e58ca 7264
8029a119
NC		 7265bfd_boolean
7266bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
7267{
7268 struct elf32_arm_link_hash_table * globals;
906e58ca 7269
8029a119
NC		 7270 globals = elf32_arm_hash_table (info);
7271 BFD_ASSERT (globals != NULL);
906e58ca 7272
8029a119
NC		 7273 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7274 globals->arm_glue_size,
7275 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 7276
8029a119
NC		 7277 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7278 globals->thumb_glue_size,
7279 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 7280
8029a119
NC		 7281 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7282 globals->vfp11_erratum_glue_size,
7283 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 7284
a504d23a
LA		 7285 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7286 globals->stm32l4xx_erratum_glue_size,
7287 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7288
8029a119
NC		 7289 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7290 globals->bx_glue_size,
845b51d6
PB		 7291 ARM_BX_GLUE_SECTION_NAME);
7292
b34976b6 7293 return TRUE;
252b5132
RH		 7294}
7295
a4fd1a8e 7296/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 7297 returns the symbol identifying the stub. */
7298
a4fd1a8e 7299static struct elf_link_hash_entry *
57e8b36a
NC		 7300record_arm_to_thumb_glue (struct bfd_link_info * link_info,
7301 struct elf_link_hash_entry * h)
252b5132
RH		 7302{
7303 const char * name = h->root.root.string;
63b0f745 7304 asection * s;
252b5132
RH		 7305 char * tmp_name;
7306 struct elf_link_hash_entry * myh;
14a793b2 7307 struct bfd_link_hash_entry * bh;
252b5132 7308 struct elf32_arm_link_hash_table * globals;
dc810e39 7309 bfd_vma val;
2f475487 7310 bfd_size_type size;
252b5132
RH		 7311
7312 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 7313 BFD_ASSERT (globals != NULL);
7314 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7315
3d4d4302 7316 s = bfd_get_linker_section
252b5132
RH		 7317 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
7318
252b5132
RH		 7319 BFD_ASSERT (s != NULL);
7320
21d799b5 7321 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7322 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7323
7324 BFD_ASSERT (tmp_name);
7325
7326 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7327
7328 myh = elf_link_hash_lookup
b34976b6 7329 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 7330
7331 if (myh != NULL)
7332 {
9b485d32 7333 /* We've already seen this guy. */
252b5132 7334 free (tmp_name);
a4fd1a8e 7335 return myh;
252b5132
RH		 7336 }
7337
57e8b36a
NC		 7338 /* The only trick here is using hash_table->arm_glue_size as the value.
7339 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 7340 putting it. The +1 on the value marks that the stub has not been
7341 output yet - not that it is a Thumb function. */
14a793b2 7342 bh = NULL;
dc810e39
AM		 7343 val = globals->arm_glue_size + 1;
7344 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
7345 tmp_name, BSF_GLOBAL, s, val,
b34976b6 7346 NULL, TRUE, FALSE, &bh);
252b5132 7347
b7693d02
DJ		 7348 myh = (struct elf_link_hash_entry *) bh;
7349 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7350 myh->forced_local = 1;
7351
252b5132
RH		 7352 free (tmp_name);
7353
0e1862bb
L		 7354 if (bfd_link_pic (link_info)
7355 || globals->root.is_relocatable_executable
27e55c4d 7356 || globals->pic_veneer)
2f475487 7357 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7358 else if (globals->use_blx)
7359 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7360 else
2f475487
AM		 7361 size = ARM2THUMB_STATIC_GLUE_SIZE;
7362
7363 s->size += size;
7364 globals->arm_glue_size += size;
252b5132 7365
a4fd1a8e 7366 return myh;
252b5132
RH		 7367}
7368
845b51d6
PB		 7369/* Allocate space for ARMv4 BX veneers. */
7370
7371static void
7372record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7373{
7374 asection * s;
7375 struct elf32_arm_link_hash_table *globals;
7376 char *tmp_name;
7377 struct elf_link_hash_entry *myh;
7378 struct bfd_link_hash_entry *bh;
7379 bfd_vma val;
7380
7381 /* BX PC does not need a veneer. */
7382 if (reg == 15)
7383 return;
7384
7385 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7386 BFD_ASSERT (globals != NULL);
7387 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7388
7389 /* Check if this veneer has already been allocated. */
7390 if (globals->bx_glue_offset[reg])
7391 return;
7392
3d4d4302 7393 s = bfd_get_linker_section
845b51d6
PB		 7394 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7395
7396 BFD_ASSERT (s != NULL);
7397
7398 /* Add symbol for veneer. */
21d799b5
NC		 7399 tmp_name = (char *)
7400 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7401
845b51d6 7402 BFD_ASSERT (tmp_name);
906e58ca 7403
845b51d6 7404 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7405
845b51d6
PB		 7406 myh = elf_link_hash_lookup
7407 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7408
845b51d6 7409 BFD_ASSERT (myh == NULL);
906e58ca 7410
845b51d6
PB		 7411 bh = NULL;
7412 val = globals->bx_glue_size;
7413 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7414 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7415 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7416
7417 myh = (struct elf_link_hash_entry *) bh;
7418 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7419 myh->forced_local = 1;
7420
7421 s->size += ARM_BX_VENEER_SIZE;
7422 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7423 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7424}
7425
7426
c7b8f16e
JB		 7427/* Add an entry to the code/data map for section SEC. */
7428
7429static void
7430elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7431{
7432 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7433 unsigned int newidx;
906e58ca 7434
c7b8f16e
JB		 7435 if (sec_data->map == NULL)
7436 {
21d799b5 7437 sec_data->map = (elf32_arm_section_map *)
99059e56 7438 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7439 sec_data->mapcount = 0;
7440 sec_data->mapsize = 1;
7441 }
906e58ca 7442
c7b8f16e 7443 newidx = sec_data->mapcount++;
906e58ca 7444
c7b8f16e
JB		 7445 if (sec_data->mapcount > sec_data->mapsize)
7446 {
7447 sec_data->mapsize *= 2;
21d799b5 7448 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7449 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7450 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7451 }
7452
7453 if (sec_data->map)
7454 {
7455 sec_data->map[newidx].vma = vma;
7456 sec_data->map[newidx].type = type;
c7b8f16e 7457 }
c7b8f16e
JB		 7458}
7459
7460
7461/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7462 veneers are handled for now. */
7463
7464static bfd_vma
7465record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7466 elf32_vfp11_erratum_list *branch,
7467 bfd *branch_bfd,
7468 asection *branch_sec,
7469 unsigned int offset)
c7b8f16e
JB		 7470{
7471 asection *s;
7472 struct elf32_arm_link_hash_table *hash_table;
7473 char *tmp_name;
7474 struct elf_link_hash_entry *myh;
7475 struct bfd_link_hash_entry *bh;
7476 bfd_vma val;
7477 struct _arm_elf_section_data *sec_data;
c7b8f16e 7478 elf32_vfp11_erratum_list *newerr;
906e58ca 7479
c7b8f16e 7480 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7481 BFD_ASSERT (hash_table != NULL);
7482 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7483
3d4d4302 7484 s = bfd_get_linker_section
c7b8f16e 7485 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7486
c7b8f16e 7487 sec_data = elf32_arm_section_data (s);
906e58ca 7488
c7b8f16e 7489 BFD_ASSERT (s != NULL);
906e58ca 7490
21d799b5 7491 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7492 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7493
c7b8f16e 7494 BFD_ASSERT (tmp_name);
906e58ca 7495
c7b8f16e
JB		 7496 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7497 hash_table->num_vfp11_fixes);
906e58ca 7498
c7b8f16e
JB		 7499 myh = elf_link_hash_lookup
7500 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7501
c7b8f16e 7502 BFD_ASSERT (myh == NULL);
906e58ca 7503
c7b8f16e
JB		 7504 bh = NULL;
7505 val = hash_table->vfp11_erratum_glue_size;
7506 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7507 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7508 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7509
7510 myh = (struct elf_link_hash_entry *) bh;
7511 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7512 myh->forced_local = 1;
7513
7514 /* Link veneer back to calling location. */
c7e2358a 7515 sec_data->erratumcount += 1;
21d799b5
NC		 7516 newerr = (elf32_vfp11_erratum_list *)
7517 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7518
c7b8f16e
JB		 7519 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7520 newerr->vma = -1;
7521 newerr->u.v.branch = branch;
7522 newerr->u.v.id = hash_table->num_vfp11_fixes;
7523 branch->u.b.veneer = newerr;
7524
7525 newerr->next = sec_data->erratumlist;
7526 sec_data->erratumlist = newerr;
7527
7528 /* A symbol for the return from the veneer. */
7529 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7530 hash_table->num_vfp11_fixes);
7531
7532 myh = elf_link_hash_lookup
7533 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7534
c7b8f16e
JB		 7535 if (myh != NULL)
7536 abort ();
7537
7538 bh = NULL;
7539 val = offset + 4;
7540 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7541 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7542
c7b8f16e
JB		 7543 myh = (struct elf_link_hash_entry *) bh;
7544 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7545 myh->forced_local = 1;
7546
7547 free (tmp_name);
906e58ca 7548
c7b8f16e
JB		 7549 /* Generate a mapping symbol for the veneer section, and explicitly add an
7550 entry for that symbol to the code/data map for the section. */
7551 if (hash_table->vfp11_erratum_glue_size == 0)
7552 {
7553 bh = NULL;
7554 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7555 ever requires this erratum fix. */
c7b8f16e
JB		 7556 _bfd_generic_link_add_one_symbol (link_info,
7557 hash_table->bfd_of_glue_owner, "$a",
7558 BSF_LOCAL, s, 0, NULL,
99059e56 7559 TRUE, FALSE, &bh);
c7b8f16e
JB		 7560
7561 myh = (struct elf_link_hash_entry *) bh;
7562 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7563 myh->forced_local = 1;
906e58ca 7564
c7b8f16e 7565 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7566 BFDs. We must make a note of this generated mapping symbol
7567 ourselves so that code byteswapping works properly in
7568 elf32_arm_write_section. */
c7b8f16e
JB		 7569 elf32_arm_section_map_add (s, 'a', 0);
7570 }
906e58ca 7571
c7b8f16e
JB		 7572 s->size += VFP11_ERRATUM_VENEER_SIZE;
7573 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7574 hash_table->num_vfp11_fixes++;
906e58ca 7575
c7b8f16e
JB		 7576 /* The offset of the veneer. */
7577 return val;
7578}
7579
a504d23a
LA		 7580/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7581 veneers need to be handled because used only in Cortex-M. */
7582
7583static bfd_vma
7584record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7585 elf32_stm32l4xx_erratum_list *branch,
7586 bfd *branch_bfd,
7587 asection *branch_sec,
7588 unsigned int offset,
7589 bfd_size_type veneer_size)
7590{
7591 asection *s;
7592 struct elf32_arm_link_hash_table *hash_table;
7593 char *tmp_name;
7594 struct elf_link_hash_entry *myh;
7595 struct bfd_link_hash_entry *bh;
7596 bfd_vma val;
7597 struct _arm_elf_section_data *sec_data;
7598 elf32_stm32l4xx_erratum_list *newerr;
7599
7600 hash_table = elf32_arm_hash_table (link_info);
7601 BFD_ASSERT (hash_table != NULL);
7602 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7603
7604 s = bfd_get_linker_section
7605 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7606
7607 BFD_ASSERT (s != NULL);
7608
7609 sec_data = elf32_arm_section_data (s);
7610
7611 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7612 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7613
7614 BFD_ASSERT (tmp_name);
7615
7616 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7617 hash_table->num_stm32l4xx_fixes);
7618
7619 myh = elf_link_hash_lookup
7620 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7621
7622 BFD_ASSERT (myh == NULL);
7623
7624 bh = NULL;
7625 val = hash_table->stm32l4xx_erratum_glue_size;
7626 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7627 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7628 NULL, TRUE, FALSE, &bh);
7629
7630 myh = (struct elf_link_hash_entry *) bh;
7631 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7632 myh->forced_local = 1;
7633
7634 /* Link veneer back to calling location. */
7635 sec_data->stm32l4xx_erratumcount += 1;
7636 newerr = (elf32_stm32l4xx_erratum_list *)
7637 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7638
7639 newerr->type = STM32L4XX_ERRATUM_VENEER;
7640 newerr->vma = -1;
7641 newerr->u.v.branch = branch;
7642 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7643 branch->u.b.veneer = newerr;
7644
7645 newerr->next = sec_data->stm32l4xx_erratumlist;
7646 sec_data->stm32l4xx_erratumlist = newerr;
7647
7648 /* A symbol for the return from the veneer. */
7649 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7650 hash_table->num_stm32l4xx_fixes);
7651
7652 myh = elf_link_hash_lookup
7653 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7654
7655 if (myh != NULL)
7656 abort ();
7657
7658 bh = NULL;
7659 val = offset + 4;
7660 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7661 branch_sec, val, NULL, TRUE, FALSE, &bh);
7662
7663 myh = (struct elf_link_hash_entry *) bh;
7664 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7665 myh->forced_local = 1;
7666
7667 free (tmp_name);
7668
7669 /* Generate a mapping symbol for the veneer section, and explicitly add an
7670 entry for that symbol to the code/data map for the section. */
7671 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7672 {
7673 bh = NULL;
7674 /* Creates a THUMB symbol since there is no other choice. */
7675 _bfd_generic_link_add_one_symbol (link_info,
7676 hash_table->bfd_of_glue_owner, "$t",
7677 BSF_LOCAL, s, 0, NULL,
7678 TRUE, FALSE, &bh);
7679
7680 myh = (struct elf_link_hash_entry *) bh;
7681 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7682 myh->forced_local = 1;
7683
7684 /* The elf32_arm_init_maps function only cares about symbols from input
7685 BFDs. We must make a note of this generated mapping symbol
7686 ourselves so that code byteswapping works properly in
7687 elf32_arm_write_section. */
7688 elf32_arm_section_map_add (s, 't', 0);
7689 }
7690
7691 s->size += veneer_size;
7692 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7693 hash_table->num_stm32l4xx_fixes++;
7694
7695 /* The offset of the veneer. */
7696 return val;
7697}
7698
8029a119 7699#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7700 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7701 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7702
7703/* Create a fake section for use by the ARM backend of the linker. */
7704
7705static bfd_boolean
7706arm_make_glue_section (bfd * abfd, const char * name)
7707{
7708 asection * sec;
7709
3d4d4302 7710 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7711 if (sec != NULL)
7712 /* Already made. */
7713 return TRUE;
7714
3d4d4302 7715 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7716
7717 if (sec == NULL
fd361982 7718 || !bfd_set_section_alignment (sec, 2))
8029a119
NC		 7719 return FALSE;
7720
7721 /* Set the gc mark to prevent the section from being removed by garbage
7722 collection, despite the fact that no relocs refer to this section. */
7723 sec->gc_mark = 1;
7724
7725 return TRUE;
7726}
7727
1db37fe6
YG		 7728/* Set size of .plt entries. This function is called from the
7729 linker scripts in ld/emultempl/{armelf}.em. */
7730
7731void
7732bfd_elf32_arm_use_long_plt (void)
7733{
7734 elf32_arm_use_long_plt_entry = TRUE;
7735}
7736
8afb0e02
NC		 7737/* Add the glue sections to ABFD. This function is called from the
7738 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7739
b34976b6 7740bfd_boolean
57e8b36a
NC		 7741bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7742 struct bfd_link_info *info)
252b5132 7743{
a504d23a
LA		 7744 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7745 bfd_boolean dostm32l4xx = globals
7746 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7747 bfd_boolean addglue;
7748
8afb0e02
NC		 7749 /* If we are only performing a partial
7750 link do not bother adding the glue. */
0e1862bb 7751 if (bfd_link_relocatable (info))
b34976b6 7752 return TRUE;
252b5132 7753
a504d23a 7754 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7755 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7756 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7757 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7758
7759 if (!dostm32l4xx)
7760 return addglue;
7761
7762 return addglue
7763 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7764}
7765
daa4adae
TP		 7766/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7767 ensures they are not marked for deletion by
7768 strip_excluded_output_sections () when veneers are going to be created
7769 later. Not doing so would trigger assert on empty section size in
7770 lang_size_sections_1 (). */
7771
7772void
7773bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7774{
7775 enum elf32_arm_stub_type stub_type;
7776
7777 /* If we are only performing a partial
7778 link do not bother adding the glue. */
7779 if (bfd_link_relocatable (info))
7780 return;
7781
7782 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7783 {
7784 asection *out_sec;
7785 const char *out_sec_name;
7786
7787 if (!arm_dedicated_stub_output_section_required (stub_type))
7788 continue;
7789
7790 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7791 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7792 if (out_sec != NULL)
7793 out_sec->flags |= SEC_KEEP;
7794 }
7795}
7796
8afb0e02
NC		 7797/* Select a BFD to be used to hold the sections used by the glue code.
7798 This function is called from the linker scripts in ld/emultempl/
8029a119 7799 {armelf/pe}.em. */
8afb0e02 7800
b34976b6 7801bfd_boolean
57e8b36a 7802bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7803{
7804 struct elf32_arm_link_hash_table *globals;
7805
7806 /* If we are only performing a partial link
7807 do not bother getting a bfd to hold the glue. */
0e1862bb 7808 if (bfd_link_relocatable (info))
b34976b6 7809 return TRUE;
8afb0e02 7810
b7693d02
DJ		 7811 /* Make sure we don't attach the glue sections to a dynamic object. */
7812 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7813
8afb0e02 7814 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7815 BFD_ASSERT (globals != NULL);
7816
7817 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7818 return TRUE;
8afb0e02 7819
252b5132
RH		 7820 /* Save the bfd for later use. */
7821 globals->bfd_of_glue_owner = abfd;
cedb70c5 7822
b34976b6 7823 return TRUE;
252b5132
RH		 7824}
7825
906e58ca
NC		 7826static void
7827check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7828{
2de70689
MGD		 7829 int cpu_arch;
7830
b38cadfb 7831 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7832 Tag_CPU_arch);
7833
7834 if (globals->fix_arm1176)
7835 {
7836 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7837 globals->use_blx = 1;
7838 }
7839 else
7840 {
7841 if (cpu_arch > TAG_CPU_ARCH_V4T)
7842 globals->use_blx = 1;
7843 }
39b41c9c
PB		 7844}
7845
b34976b6 7846bfd_boolean
57e8b36a 7847bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7848 struct bfd_link_info *link_info)
252b5132
RH		 7849{
7850 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7851 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7852 Elf_Internal_Rela *irel, *irelend;
7853 bfd_byte *contents = NULL;
252b5132
RH		 7854
7855 asection *sec;
7856 struct elf32_arm_link_hash_table *globals;
7857
7858 /* If we are only performing a partial link do not bother
7859 to construct any glue. */
0e1862bb 7860 if (bfd_link_relocatable (link_info))
b34976b6 7861 return TRUE;
252b5132 7862
39ce1a6a
NC		 7863 /* Here we have a bfd that is to be included on the link. We have a
7864 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7865 globals = elf32_arm_hash_table (link_info);
252b5132 7866 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7867
7868 check_use_blx (globals);
252b5132 7869
d504ffc8 7870 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7871 {
90b6238f 7872 _bfd_error_handler (_("%pB: BE8 images only valid in big-endian mode"),
d003868e 7873 abfd);
e489d0ae
PB		 7874 return FALSE;
7875 }
f21f3fe0 7876
39ce1a6a
NC		 7877 /* PR 5398: If we have not decided to include any loadable sections in
7878 the output then we will not have a glue owner bfd. This is OK, it
7879 just means that there is nothing else for us to do here. */
7880 if (globals->bfd_of_glue_owner == NULL)
7881 return TRUE;
7882
252b5132
RH		 7883 /* Rummage around all the relocs and map the glue vectors. */
7884 sec = abfd->sections;
7885
7886 if (sec == NULL)
b34976b6 7887 return TRUE;
252b5132
RH		 7888
7889 for (; sec != NULL; sec = sec->next)
7890 {
7891 if (sec->reloc_count == 0)
7892 continue;
7893
2f475487
AM		 7894 if ((sec->flags & SEC_EXCLUDE) != 0)
7895 continue;
7896
0ffa91dd 7897 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7898
9b485d32 7899 /* Load the relocs. */
6cdc0ccc 7900 internal_relocs
906e58ca 7901 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7902
6cdc0ccc
AM		 7903 if (internal_relocs == NULL)
7904 goto error_return;
252b5132 7905
6cdc0ccc
AM		 7906 irelend = internal_relocs + sec->reloc_count;
7907 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7908 {
7909 long r_type;
7910 unsigned long r_index;
252b5132
RH		 7911
7912 struct elf_link_hash_entry *h;
7913
7914 r_type = ELF32_R_TYPE (irel->r_info);
7915 r_index = ELF32_R_SYM (irel->r_info);
7916
9b485d32 7917 /* These are the only relocation types we care about. */
ba96a88f 7918 if ( r_type != R_ARM_PC24
845b51d6 7919 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7920 continue;
7921
7922 /* Get the section contents if we haven't done so already. */
7923 if (contents == NULL)
7924 {
7925 /* Get cached copy if it exists. */
7926 if (elf_section_data (sec)->this_hdr.contents != NULL)
7927 contents = elf_section_data (sec)->this_hdr.contents;
7928 else
7929 {
7930 /* Go get them off disk. */
57e8b36a 7931 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7932 goto error_return;
7933 }
7934 }
7935
845b51d6
PB		 7936 if (r_type == R_ARM_V4BX)
7937 {
7938 int reg;
7939
7940 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7941 record_arm_bx_glue (link_info, reg);
7942 continue;
7943 }
7944
a7c10850 7945 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7946 h = NULL;
7947
9b485d32 7948 /* We don't care about local symbols. */
252b5132
RH		 7949 if (r_index < symtab_hdr->sh_info)
7950 continue;
7951
9b485d32 7952 /* This is an external symbol. */
252b5132
RH		 7953 r_index -= symtab_hdr->sh_info;
7954 h = (struct elf_link_hash_entry *)
7955 elf_sym_hashes (abfd)[r_index];
7956
7957 /* If the relocation is against a static symbol it must be within
7958 the current section and so cannot be a cross ARM/Thumb relocation. */
7959 if (h == NULL)
7960 continue;
7961
d504ffc8
DJ		 7962 /* If the call will go through a PLT entry then we do not need
7963 glue. */
362d30a1 7964 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7965 continue;
7966
252b5132
RH		 7967 switch (r_type)
7968 {
7969 case R_ARM_PC24:
7970 /* This one is a call from arm code. We need to look up
99059e56
RM		 7971 the target of the call. If it is a thumb target, we
7972 insert glue. */
39d911fc
TP		 7973 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7974 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7975 record_arm_to_thumb_glue (link_info, h);
7976 break;
7977
252b5132 7978 default:
c6596c5e 7979 abort ();
252b5132
RH		 7980 }
7981 }
6cdc0ccc
AM		 7982
7983 if (contents != NULL
7984 && elf_section_data (sec)->this_hdr.contents != contents)
7985 free (contents);
7986 contents = NULL;
7987
7988 if (internal_relocs != NULL
7989 && elf_section_data (sec)->relocs != internal_relocs)
7990 free (internal_relocs);
7991 internal_relocs = NULL;
252b5132
RH		 7992 }
7993
b34976b6 7994 return TRUE;
9a5aca8c 7995
252b5132 7996error_return:
6cdc0ccc
AM		 7997 if (contents != NULL
7998 && elf_section_data (sec)->this_hdr.contents != contents)
7999 free (contents);
8000 if (internal_relocs != NULL
8001 && elf_section_data (sec)->relocs != internal_relocs)
8002 free (internal_relocs);
9a5aca8c 8003
b34976b6 8004 return FALSE;
252b5132 8005}
7e392df6 8006#endif
252b5132 8007
eb043451 8008
c7b8f16e
JB		 8009/* Initialise maps of ARM/Thumb/data for input BFDs. */
8010
8011void
8012bfd_elf32_arm_init_maps (bfd *abfd)
8013{
8014 Elf_Internal_Sym *isymbuf;
8015 Elf_Internal_Shdr *hdr;
8016 unsigned int i, localsyms;
8017
af1f4419
NC		 8018 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
8019 if (! is_arm_elf (abfd))
8020 return;
8021
c7b8f16e
JB		 8022 if ((abfd->flags & DYNAMIC) != 0)
8023 return;
8024
0ffa91dd 8025 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 8026 localsyms = hdr->sh_info;
8027
8028 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
8029 should contain the number of local symbols, which should come before any
8030 global symbols. Mapping symbols are always local. */
8031 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
8032 NULL);
8033
8034 /* No internal symbols read? Skip this BFD. */
8035 if (isymbuf == NULL)
8036 return;
8037
8038 for (i = 0; i < localsyms; i++)
8039 {
8040 Elf_Internal_Sym *isym = &isymbuf[i];
8041 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
8042 const char *name;
906e58ca 8043
c7b8f16e 8044 if (sec != NULL
99059e56
RM		 8045 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
8046 {
8047 name = bfd_elf_string_from_elf_section (abfd,
8048 hdr->sh_link, isym->st_name);
906e58ca 8049
99059e56 8050 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 8051 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 8052 elf32_arm_section_map_add (sec, name[1], isym->st_value);
8053 }
c7b8f16e
JB		 8054 }
8055}
8056
8057
48229727
JB		 8058/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
8059 say what they wanted. */
8060
8061void
8062bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
8063{
8064 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8065 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8066
4dfe6ac6
NC		 8067 if (globals == NULL)
8068 return;
8069
48229727
JB		 8070 if (globals->fix_cortex_a8 == -1)
8071 {
8072 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
8073 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
8074 && (out_attr[Tag_CPU_arch_profile].i == 'A'
8075 || out_attr[Tag_CPU_arch_profile].i == 0))
8076 globals->fix_cortex_a8 = 1;
8077 else
8078 globals->fix_cortex_a8 = 0;
8079 }
8080}
8081
8082
c7b8f16e
JB		 8083void
8084bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
8085{
8086 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 8087 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 8088
4dfe6ac6
NC		 8089 if (globals == NULL)
8090 return;
c7b8f16e
JB		 8091 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8092 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
8093 {
8094 switch (globals->vfp11_fix)
99059e56
RM		 8095 {
8096 case BFD_ARM_VFP11_FIX_DEFAULT:
8097 case BFD_ARM_VFP11_FIX_NONE:
8098 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8099 break;
8100
8101 default:
8102 /* Give a warning, but do as the user requests anyway. */
871b3ab2 8103 _bfd_error_handler (_("%pB: warning: selected VFP11 erratum "
99059e56
RM		 8104 "workaround is not necessary for target architecture"), obfd);
8105 }
c7b8f16e
JB		 8106 }
8107 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
8108 /* For earlier architectures, we might need the workaround, but do not
8109 enable it by default. If users is running with broken hardware, they
8110 must enable the erratum fix explicitly. */
8111 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8112}
8113
a504d23a
LA		 8114void
8115bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
8116{
8117 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8118 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8119
8120 if (globals == NULL)
8121 return;
8122
8123 /* We assume only Cortex-M4 may require the fix. */
8124 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
8125 || out_attr[Tag_CPU_arch_profile].i != 'M')
8126 {
8127 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
8128 /* Give a warning, but do as the user requests anyway. */
4eca0228 8129 _bfd_error_handler
871b3ab2 8130 (_("%pB: warning: selected STM32L4XX erratum "
a504d23a
LA		 8131 "workaround is not necessary for target architecture"), obfd);
8132 }
8133}
c7b8f16e 8134
906e58ca
NC		 8135enum bfd_arm_vfp11_pipe
8136{
c7b8f16e
JB		 8137 VFP11_FMAC,
8138 VFP11_LS,
8139 VFP11_DS,
8140 VFP11_BAD
8141};
8142
8143/* Return a VFP register number. This is encoded as RX:X for single-precision
8144 registers, or X:RX for double-precision registers, where RX is the group of
8145 four bits in the instruction encoding and X is the single extension bit.
8146 RX and X fields are specified using their lowest (starting) bit. The return
8147 value is:
8148
8149 0...31: single-precision registers s0...s31
8150 32...63: double-precision registers d0...d31.
906e58ca 8151
c7b8f16e
JB		 8152 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8153 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 8154
c7b8f16e
JB		 8155static unsigned int
8156bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 8157 unsigned int x)
c7b8f16e
JB		 8158{
8159 if (is_double)
8160 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
8161 else
8162 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
8163}
8164
8165/* Set bits in *WMASK according to a register number REG as encoded by
8166 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8167
8168static void
8169bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
8170{
8171 if (reg < 32)
8172 *wmask |= 1 << reg;
8173 else if (reg < 48)
8174 *wmask |= 3 << ((reg - 32) * 2);
8175}
8176
8177/* Return TRUE if WMASK overwrites anything in REGS. */
8178
8179static bfd_boolean
8180bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
8181{
8182 int i;
906e58ca 8183
c7b8f16e
JB		 8184 for (i = 0; i < numregs; i++)
8185 {
8186 unsigned int reg = regs[i];
8187
8188 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 8189 return TRUE;
906e58ca 8190
c7b8f16e
JB		 8191 reg -= 32;
8192
8193 if (reg >= 16)
99059e56 8194 continue;
906e58ca 8195
c7b8f16e 8196 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 8197 return TRUE;
c7b8f16e 8198 }
906e58ca 8199
c7b8f16e
JB		 8200 return FALSE;
8201}
8202
8203/* In this function, we're interested in two things: finding input registers
8204 for VFP data-processing instructions, and finding the set of registers which
8205 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8206 hold the written set, so FLDM etc. are easy to deal with (we're only
8207 interested in 32 SP registers or 16 dp registers, due to the VFP version
8208 implemented by the chip in question). DP registers are marked by setting
8209 both SP registers in the write mask). */
8210
8211static enum bfd_arm_vfp11_pipe
8212bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 8213 int *numregs)
c7b8f16e 8214{
91d6fa6a 8215 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 8216 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
8217
8218 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
8219 {
8220 unsigned int pqrs;
8221 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8222 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
8223
8224 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 8225 | ((insn & 0x00300000) >> 19)
8226 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 8227
8228 switch (pqrs)
99059e56
RM		 8229 {
8230 case 0: /* fmac[sd]. */
8231 case 1: /* fnmac[sd]. */
8232 case 2: /* fmsc[sd]. */
8233 case 3: /* fnmsc[sd]. */
8234 vpipe = VFP11_FMAC;
8235 bfd_arm_vfp11_write_mask (destmask, fd);
8236 regs[0] = fd;
8237 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8238 regs[2] = fm;
8239 *numregs = 3;
8240 break;
8241
8242 case 4: /* fmul[sd]. */
8243 case 5: /* fnmul[sd]. */
8244 case 6: /* fadd[sd]. */
8245 case 7: /* fsub[sd]. */
8246 vpipe = VFP11_FMAC;
8247 goto vfp_binop;
8248
8249 case 8: /* fdiv[sd]. */
8250 vpipe = VFP11_DS;
8251 vfp_binop:
8252 bfd_arm_vfp11_write_mask (destmask, fd);
8253 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8254 regs[1] = fm;
8255 *numregs = 2;
8256 break;
8257
8258 case 15: /* extended opcode. */
8259 {
8260 unsigned int extn = ((insn >> 15) & 0x1e)
8261 | ((insn >> 7) & 1);
8262
8263 switch (extn)
8264 {
8265 case 0: /* fcpy[sd]. */
8266 case 1: /* fabs[sd]. */
8267 case 2: /* fneg[sd]. */
8268 case 8: /* fcmp[sd]. */
8269 case 9: /* fcmpe[sd]. */
8270 case 10: /* fcmpz[sd]. */
8271 case 11: /* fcmpez[sd]. */
8272 case 16: /* fuito[sd]. */
8273 case 17: /* fsito[sd]. */
8274 case 24: /* ftoui[sd]. */
8275 case 25: /* ftouiz[sd]. */
8276 case 26: /* ftosi[sd]. */
8277 case 27: /* ftosiz[sd]. */
8278 /* These instructions will not bounce due to underflow. */
8279 *numregs = 0;
8280 vpipe = VFP11_FMAC;
8281 break;
8282
8283 case 3: /* fsqrt[sd]. */
8284 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8285 registers to cause the erratum in previous instructions. */
8286 bfd_arm_vfp11_write_mask (destmask, fd);
8287 vpipe = VFP11_DS;
8288 break;
8289
8290 case 15: /* fcvt{ds,sd}. */
8291 {
8292 int rnum = 0;
8293
8294 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 8295
8296 /* Only FCVTSD can underflow. */
99059e56
RM		 8297 if ((insn & 0x100) != 0)
8298 regs[rnum++] = fm;
c7b8f16e 8299
99059e56 8300 *numregs = rnum;
c7b8f16e 8301
99059e56
RM		 8302 vpipe = VFP11_FMAC;
8303 }
8304 break;
c7b8f16e 8305
99059e56
RM		 8306 default:
8307 return VFP11_BAD;
8308 }
8309 }
8310 break;
c7b8f16e 8311
99059e56
RM		 8312 default:
8313 return VFP11_BAD;
8314 }
c7b8f16e
JB		 8315 }
8316 /* Two-register transfer. */
8317 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
8318 {
8319 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 8320
c7b8f16e
JB		 8321 if ((insn & 0x100000) == 0)
8322 {
99059e56
RM		 8323 if (is_double)
8324 bfd_arm_vfp11_write_mask (destmask, fm);
8325 else
8326 {
8327 bfd_arm_vfp11_write_mask (destmask, fm);
8328 bfd_arm_vfp11_write_mask (destmask, fm + 1);
8329 }
c7b8f16e
JB		 8330 }
8331
91d6fa6a 8332 vpipe = VFP11_LS;
c7b8f16e
JB		 8333 }
8334 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
8335 {
8336 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8337 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 8338
c7b8f16e 8339 switch (puw)
99059e56
RM		 8340 {
8341 case 0: /* Two-reg transfer. We should catch these above. */
8342 abort ();
906e58ca 8343
99059e56
RM		 8344 case 2: /* fldm[sdx]. */
8345 case 3:
8346 case 5:
8347 {
8348 unsigned int i, offset = insn & 0xff;
c7b8f16e 8349
99059e56
RM		 8350 if (is_double)
8351 offset >>= 1;
c7b8f16e 8352
99059e56
RM		 8353 for (i = fd; i < fd + offset; i++)
8354 bfd_arm_vfp11_write_mask (destmask, i);
8355 }
8356 break;
906e58ca 8357
99059e56
RM		 8358 case 4: /* fld[sd]. */
8359 case 6:
8360 bfd_arm_vfp11_write_mask (destmask, fd);
8361 break;
906e58ca 8362
99059e56
RM		 8363 default:
8364 return VFP11_BAD;
8365 }
c7b8f16e 8366
91d6fa6a 8367 vpipe = VFP11_LS;
c7b8f16e
JB		 8368 }
8369 /* Single-register transfer. Note L==0. */
8370 else if ((insn & 0x0f100e10) == 0x0e000a10)
8371 {
8372 unsigned int opcode = (insn >> 21) & 7;
8373 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8374
8375 switch (opcode)
99059e56
RM		 8376 {
8377 case 0: /* fmsr/fmdlr. */
8378 case 1: /* fmdhr. */
8379 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8380 destination register. I don't know if this is exactly right,
8381 but it is the conservative choice. */
8382 bfd_arm_vfp11_write_mask (destmask, fn);
8383 break;
8384
8385 case 7: /* fmxr. */
8386 break;
8387 }
c7b8f16e 8388
91d6fa6a 8389 vpipe = VFP11_LS;
c7b8f16e
JB		 8390 }
8391
91d6fa6a 8392 return vpipe;
c7b8f16e
JB		 8393}
8394
8395
8396static int elf32_arm_compare_mapping (const void * a, const void * b);
8397
8398
8399/* Look for potentially-troublesome code sequences which might trigger the
8400 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8401 (available from ARM) for details of the erratum. A short version is
8402 described in ld.texinfo. */
8403
8404bfd_boolean
8405bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8406{
8407 asection *sec;
8408 bfd_byte *contents = NULL;
8409 int state = 0;
8410 int regs[3], numregs = 0;
8411 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8412 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8413
4dfe6ac6
NC		 8414 if (globals == NULL)
8415 return FALSE;
8416
c7b8f16e
JB		 8417 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8418 The states transition as follows:
906e58ca 8419
c7b8f16e 8420 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8421 A VFP FMAC-pipeline instruction has been seen. Fill
8422 regs[0]..regs[numregs-1] with its input operands. Remember this
8423 instruction in 'first_fmac'.
c7b8f16e
JB		 8424
8425 1 -> 2
99059e56
RM		 8426 Any instruction, except for a VFP instruction which overwrites
8427 regs[*].
906e58ca 8428
c7b8f16e
JB		 8429 1 -> 3 [ -> 0 ] or
8430 2 -> 3 [ -> 0 ]
99059e56
RM		 8431 A VFP instruction has been seen which overwrites any of regs[*].
8432 We must make a veneer! Reset state to 0 before examining next
8433 instruction.
906e58ca 8434
c7b8f16e 8435 2 -> 0
99059e56
RM		 8436 If we fail to match anything in state 2, reset to state 0 and reset
8437 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8438
8439 If the VFP11 vector mode is in use, there must be at least two unrelated
8440 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8441 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8442
8443 /* If we are only performing a partial link do not bother
8444 to construct any glue. */
0e1862bb 8445 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8446 return TRUE;
8447
0ffa91dd
NC		 8448 /* Skip if this bfd does not correspond to an ELF image. */
8449 if (! is_arm_elf (abfd))
8450 return TRUE;
906e58ca 8451
c7b8f16e
JB		 8452 /* We should have chosen a fix type by the time we get here. */
8453 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8454
8455 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8456 return TRUE;
2e6030b9 8457
33a7ffc2
JM		 8458 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8459 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8460 return TRUE;
8461
c7b8f16e
JB		 8462 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8463 {
8464 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8465 struct _arm_elf_section_data *sec_data;
8466
8467 /* If we don't have executable progbits, we're not interested in this
99059e56 8468 section. Also skip if section is to be excluded. */
c7b8f16e 8469 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8470 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8471 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8472 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8473 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8474 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8475 continue;
c7b8f16e
JB		 8476
8477 sec_data = elf32_arm_section_data (sec);
906e58ca 8478
c7b8f16e 8479 if (sec_data->mapcount == 0)
99059e56 8480 continue;
906e58ca 8481
c7b8f16e
JB		 8482 if (elf_section_data (sec)->this_hdr.contents != NULL)
8483 contents = elf_section_data (sec)->this_hdr.contents;
8484 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8485 goto error_return;
8486
8487 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8488 elf32_arm_compare_mapping);
8489
8490 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8491 {
8492 unsigned int span_start = sec_data->map[span].vma;
8493 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8494 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8495 char span_type = sec_data->map[span].type;
8496
8497 /* FIXME: Only ARM mode is supported at present. We may need to
8498 support Thumb-2 mode also at some point. */
8499 if (span_type != 'a')
8500 continue;
8501
8502 for (i = span_start; i < span_end;)
8503 {
8504 unsigned int next_i = i + 4;
8505 unsigned int insn = bfd_big_endian (abfd)
8506 ? (contents[i] << 24)
8507 | (contents[i + 1] << 16)
8508 | (contents[i + 2] << 8)
8509 | contents[i + 3]
8510 : (contents[i + 3] << 24)
8511 | (contents[i + 2] << 16)
8512 | (contents[i + 1] << 8)
8513 | contents[i];
8514 unsigned int writemask = 0;
8515 enum bfd_arm_vfp11_pipe vpipe;
8516
8517 switch (state)
8518 {
8519 case 0:
8520 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8521 &numregs);
8522 /* I'm assuming the VFP11 erratum can trigger with denorm
8523 operands on either the FMAC or the DS pipeline. This might
8524 lead to slightly overenthusiastic veneer insertion. */
8525 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8526 {
8527 state = use_vector ? 1 : 2;
8528 first_fmac = i;
8529 veneer_of_insn = insn;
8530 }
8531 break;
8532
8533 case 1:
8534 {
8535 int other_regs[3], other_numregs;
8536 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8537 other_regs,
99059e56
RM		 8538 &other_numregs);
8539 if (vpipe != VFP11_BAD
8540 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8541 numregs))
99059e56
RM		 8542 state = 3;
8543 else
8544 state = 2;
8545 }
8546 break;
8547
8548 case 2:
8549 {
8550 int other_regs[3], other_numregs;
8551 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8552 other_regs,
99059e56
RM		 8553 &other_numregs);
8554 if (vpipe != VFP11_BAD
8555 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8556 numregs))
99059e56
RM		 8557 state = 3;
8558 else
8559 {
8560 state = 0;
8561 next_i = first_fmac + 4;
8562 }
8563 }
8564 break;
8565
8566 case 3:
8567 abort (); /* Should be unreachable. */
8568 }
8569
8570 if (state == 3)
8571 {
8572 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8573 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8574
8575 elf32_arm_section_data (sec)->erratumcount += 1;
8576
8577 newerr->u.b.vfp_insn = veneer_of_insn;
8578
8579 switch (span_type)
8580 {
8581 case 'a':
8582 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8583 break;
8584
8585 default:
8586 abort ();
8587 }
8588
8589 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8590 first_fmac);
8591
99059e56 8592 newerr->vma = -1;
c7b8f16e 8593
99059e56
RM		 8594 newerr->next = sec_data->erratumlist;
8595 sec_data->erratumlist = newerr;
c7b8f16e 8596
99059e56
RM		 8597 state = 0;
8598 }
c7b8f16e 8599
99059e56
RM		 8600 i = next_i;
8601 }
8602 }
906e58ca 8603
c7b8f16e 8604 if (contents != NULL
99059e56
RM		 8605 && elf_section_data (sec)->this_hdr.contents != contents)
8606 free (contents);
c7b8f16e
JB		 8607 contents = NULL;
8608 }
8609
8610 return TRUE;
8611
8612error_return:
8613 if (contents != NULL
8614 && elf_section_data (sec)->this_hdr.contents != contents)
8615 free (contents);
906e58ca 8616
c7b8f16e
JB		 8617 return FALSE;
8618}
8619
8620/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8621 after sections have been laid out, using specially-named symbols. */
8622
8623void
8624bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8625 struct bfd_link_info *link_info)
8626{
8627 asection *sec;
8628 struct elf32_arm_link_hash_table *globals;
8629 char *tmp_name;
906e58ca 8630
0e1862bb 8631 if (bfd_link_relocatable (link_info))
c7b8f16e 8632 return;
2e6030b9
MS		 8633
8634 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8635 if (! is_arm_elf (abfd))
2e6030b9
MS		 8636 return;
8637
c7b8f16e 8638 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8639 if (globals == NULL)
8640 return;
906e58ca 8641
21d799b5 8642 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8643 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8644
8645 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8646 {
8647 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8648 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8649
c7b8f16e 8650 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8651 {
8652 struct elf_link_hash_entry *myh;
8653 bfd_vma vma;
8654
8655 switch (errnode->type)
8656 {
8657 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8658 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8659 /* Find veneer symbol. */
8660 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8661 errnode->u.b.veneer->u.v.id);
8662
99059e56
RM		 8663 myh = elf_link_hash_lookup
8664 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8665
a504d23a 8666 if (myh == NULL)
90b6238f
AM		 8667 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8668 abfd, "VFP11", tmp_name);
a504d23a
LA		 8669
8670 vma = myh->root.u.def.section->output_section->vma
8671 + myh->root.u.def.section->output_offset
8672 + myh->root.u.def.value;
8673
8674 errnode->u.b.veneer->vma = vma;
8675 break;
8676
8677 case VFP11_ERRATUM_ARM_VENEER:
8678 case VFP11_ERRATUM_THUMB_VENEER:
8679 /* Find return location. */
8680 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8681 errnode->u.v.id);
8682
8683 myh = elf_link_hash_lookup
8684 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8685
8686 if (myh == NULL)
90b6238f
AM		 8687 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8688 abfd, "VFP11", tmp_name);
a504d23a
LA		 8689
8690 vma = myh->root.u.def.section->output_section->vma
8691 + myh->root.u.def.section->output_offset
8692 + myh->root.u.def.value;
8693
8694 errnode->u.v.branch->vma = vma;
8695 break;
8696
8697 default:
8698 abort ();
8699 }
8700 }
8701 }
8702
8703 free (tmp_name);
8704}
8705
8706/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8707 return locations after sections have been laid out, using
8708 specially-named symbols. */
8709
8710void
8711bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8712 struct bfd_link_info *link_info)
8713{
8714 asection *sec;
8715 struct elf32_arm_link_hash_table *globals;
8716 char *tmp_name;
8717
8718 if (bfd_link_relocatable (link_info))
8719 return;
8720
8721 /* Skip if this bfd does not correspond to an ELF image. */
8722 if (! is_arm_elf (abfd))
8723 return;
8724
8725 globals = elf32_arm_hash_table (link_info);
8726 if (globals == NULL)
8727 return;
8728
8729 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8730 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8731
8732 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8733 {
8734 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8735 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8736
8737 for (; errnode != NULL; errnode = errnode->next)
8738 {
8739 struct elf_link_hash_entry *myh;
8740 bfd_vma vma;
8741
8742 switch (errnode->type)
8743 {
8744 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8745 /* Find veneer symbol. */
8746 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8747 errnode->u.b.veneer->u.v.id);
8748
8749 myh = elf_link_hash_lookup
8750 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8751
8752 if (myh == NULL)
90b6238f
AM		 8753 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8754 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8755
8756 vma = myh->root.u.def.section->output_section->vma
8757 + myh->root.u.def.section->output_offset
8758 + myh->root.u.def.value;
8759
8760 errnode->u.b.veneer->vma = vma;
8761 break;
8762
8763 case STM32L4XX_ERRATUM_VENEER:
8764 /* Find return location. */
8765 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8766 errnode->u.v.id);
8767
8768 myh = elf_link_hash_lookup
8769 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8770
8771 if (myh == NULL)
90b6238f
AM		 8772 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8773 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8774
8775 vma = myh->root.u.def.section->output_section->vma
8776 + myh->root.u.def.section->output_offset
8777 + myh->root.u.def.value;
8778
8779 errnode->u.v.branch->vma = vma;
8780 break;
8781
8782 default:
8783 abort ();
8784 }
8785 }
8786 }
8787
8788 free (tmp_name);
8789}
8790
8791static inline bfd_boolean
8792is_thumb2_ldmia (const insn32 insn)
8793{
8794 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8795 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8796 return (insn & 0xffd02000) == 0xe8900000;
8797}
8798
8799static inline bfd_boolean
8800is_thumb2_ldmdb (const insn32 insn)
8801{
8802 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8803 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8804 return (insn & 0xffd02000) == 0xe9100000;
8805}
8806
8807static inline bfd_boolean
8808is_thumb2_vldm (const insn32 insn)
8809{
8810 /* A6.5 Extension register load or store instruction
8811 A7.7.229
9239bbd3
CM		 8812 We look for SP 32-bit and DP 64-bit registers.
8813 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8814 <list> is consecutive 64-bit registers
8815 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8816 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8817 <list> is consecutive 32-bit registers
8818 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8819 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8820 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8821 return
9239bbd3
CM		 8822 (((insn & 0xfe100f00) == 0xec100b00) ||
8823 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8824 && /* (IA without !). */
8825 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8826 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8827 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8828 /* (DB with !). */
8829 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8830}
8831
8832/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8833 VLDM opcode and:
8834 - computes the number and the mode of memory accesses
8835 - decides if the replacement should be done:
8836 . replaces only if > 8-word accesses
8837 . or (testing purposes only) replaces all accesses. */
8838
8839static bfd_boolean
8840stm32l4xx_need_create_replacing_stub (const insn32 insn,
8841 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8842{
9239bbd3 8843 int nb_words = 0;
a504d23a
LA		 8844
8845 /* The field encoding the register list is the same for both LDMIA
8846 and LDMDB encodings. */
8847 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8848 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8849 else if (is_thumb2_vldm (insn))
9239bbd3 8850 nb_words = (insn & 0xff);
a504d23a
LA		 8851
8852 /* DEFAULT mode accounts for the real bug condition situation,
8853 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8854 return
9239bbd3 8855 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8856 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8857}
8858
8859/* Look for potentially-troublesome code sequences which might trigger
8860 the STM STM32L4XX erratum. */
8861
8862bfd_boolean
8863bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8864 struct bfd_link_info *link_info)
8865{
8866 asection *sec;
8867 bfd_byte *contents = NULL;
8868 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8869
8870 if (globals == NULL)
8871 return FALSE;
8872
8873 /* If we are only performing a partial link do not bother
8874 to construct any glue. */
8875 if (bfd_link_relocatable (link_info))
8876 return TRUE;
8877
8878 /* Skip if this bfd does not correspond to an ELF image. */
8879 if (! is_arm_elf (abfd))
8880 return TRUE;
8881
8882 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8883 return TRUE;
8884
8885 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8886 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8887 return TRUE;
8888
8889 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8890 {
8891 unsigned int i, span;
8892 struct _arm_elf_section_data *sec_data;
8893
8894 /* If we don't have executable progbits, we're not interested in this
8895 section. Also skip if section is to be excluded. */
8896 if (elf_section_type (sec) != SHT_PROGBITS
8897 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8898 || (sec->flags & SEC_EXCLUDE) != 0
8899 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8900 || sec->output_section == bfd_abs_section_ptr
8901 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8902 continue;
8903
8904 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8905
a504d23a
LA		 8906 if (sec_data->mapcount == 0)
8907 continue;
c7b8f16e 8908
a504d23a
LA		 8909 if (elf_section_data (sec)->this_hdr.contents != NULL)
8910 contents = elf_section_data (sec)->this_hdr.contents;
8911 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8912 goto error_return;
c7b8f16e 8913
a504d23a
LA		 8914 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8915 elf32_arm_compare_mapping);
c7b8f16e 8916
a504d23a
LA		 8917 for (span = 0; span < sec_data->mapcount; span++)
8918 {
8919 unsigned int span_start = sec_data->map[span].vma;
8920 unsigned int span_end = (span == sec_data->mapcount - 1)
8921 ? sec->size : sec_data->map[span + 1].vma;
8922 char span_type = sec_data->map[span].type;
8923 int itblock_current_pos = 0;
c7b8f16e 8924
a504d23a
LA		 8925 /* Only Thumb2 mode need be supported with this CM4 specific
8926 code, we should not encounter any arm mode eg span_type
8927 != 'a'. */
8928 if (span_type != 't')
8929 continue;
c7b8f16e 8930
a504d23a
LA		 8931 for (i = span_start; i < span_end;)
8932 {
8933 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8934 bfd_boolean insn_32bit = FALSE;
8935 bfd_boolean is_ldm = FALSE;
8936 bfd_boolean is_vldm = FALSE;
8937 bfd_boolean is_not_last_in_it_block = FALSE;
8938
8939 /* The first 16-bits of all 32-bit thumb2 instructions start
8940 with opcode[15..13]=0b111 and the encoded op1 can be anything
8941 except opcode[12..11]!=0b00.
8942 See 32-bit Thumb instruction encoding. */
8943 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8944 insn_32bit = TRUE;
c7b8f16e 8945
a504d23a
LA		 8946 /* Compute the predicate that tells if the instruction
8947 is concerned by the IT block
8948 - Creates an error if there is a ldm that is not
8949 last in the IT block thus cannot be replaced
8950 - Otherwise we can create a branch at the end of the
8951 IT block, it will be controlled naturally by IT
8952 with the proper pseudo-predicate
8953 - So the only interesting predicate is the one that
8954 tells that we are not on the last item of an IT
8955 block. */
8956 if (itblock_current_pos != 0)
8957 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8958
a504d23a
LA		 8959 if (insn_32bit)
8960 {
8961 /* Load the rest of the insn (in manual-friendly order). */
8962 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8963 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8964 is_vldm = is_thumb2_vldm (insn);
8965
8966 /* Veneers are created for (v)ldm depending on
8967 option flags and memory accesses conditions; but
8968 if the instruction is not the last instruction of
8969 an IT block, we cannot create a jump there, so we
8970 bail out. */
5025eb7c
AO		 8971 if ((is_ldm || is_vldm)
8972 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8973 (insn, globals->stm32l4xx_fix))
8974 {
8975 if (is_not_last_in_it_block)
8976 {
4eca0228 8977 _bfd_error_handler
695344c0 8978 /* xgettext:c-format */
871b3ab2 8979 (_("%pB(%pA+%#x): error: multiple load detected"
90b6238f
AM		 8980 " in non-last IT block instruction:"
8981 " STM32L4XX veneer cannot be generated; "
8982 "use gcc option -mrestrict-it to generate"
8983 " only one instruction per IT block"),
d42c267e 8984 abfd, sec, i);
a504d23a
LA		 8985 }
8986 else
8987 {
8988 elf32_stm32l4xx_erratum_list *newerr =
8989 (elf32_stm32l4xx_erratum_list *)
8990 bfd_zmalloc
8991 (sizeof (elf32_stm32l4xx_erratum_list));
8992
8993 elf32_arm_section_data (sec)
8994 ->stm32l4xx_erratumcount += 1;
8995 newerr->u.b.insn = insn;
8996 /* We create only thumb branches. */
8997 newerr->type =
8998 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8999 record_stm32l4xx_erratum_veneer
9000 (link_info, newerr, abfd, sec,
9001 i,
9002 is_ldm ?
9003 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
9004 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
9005 newerr->vma = -1;
9006 newerr->next = sec_data->stm32l4xx_erratumlist;
9007 sec_data->stm32l4xx_erratumlist = newerr;
9008 }
9009 }
9010 }
9011 else
9012 {
9013 /* A7.7.37 IT p208
9014 IT blocks are only encoded in T1
9015 Encoding T1: IT{x{y{z}}} <firstcond>
9016 1 0 1 1 - 1 1 1 1 - firstcond - mask
9017 if mask = '0000' then see 'related encodings'
9018 We don't deal with UNPREDICTABLE, just ignore these.
9019 There can be no nested IT blocks so an IT block
9020 is naturally a new one for which it is worth
9021 computing its size. */
5025eb7c
AO		 9022 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
9023 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 9024 /* If we have a new IT block we compute its size. */
9025 if (is_newitblock)
9026 {
9027 /* Compute the number of instructions controlled
9028 by the IT block, it will be used to decide
9029 whether we are inside an IT block or not. */
9030 unsigned int mask = insn & 0x000f;
9031 itblock_current_pos = 4 - ctz (mask);
9032 }
9033 }
9034
9035 i += insn_32bit ? 4 : 2;
99059e56
RM		 9036 }
9037 }
a504d23a
LA		 9038
9039 if (contents != NULL
9040 && elf_section_data (sec)->this_hdr.contents != contents)
9041 free (contents);
9042 contents = NULL;
c7b8f16e 9043 }
906e58ca 9044
a504d23a
LA		 9045 return TRUE;
9046
9047error_return:
9048 if (contents != NULL
9049 && elf_section_data (sec)->this_hdr.contents != contents)
9050 free (contents);
c7b8f16e 9051
a504d23a
LA		 9052 return FALSE;
9053}
c7b8f16e 9054
eb043451
PB		 9055/* Set target relocation values needed during linking. */
9056
9057void
68c39892 9058bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 9059 struct bfd_link_info *link_info,
68c39892 9060 struct elf32_arm_params *params)
eb043451
PB		 9061{
9062 struct elf32_arm_link_hash_table *globals;
9063
9064 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9065 if (globals == NULL)
9066 return;
eb043451 9067
68c39892 9068 globals->target1_is_rel = params->target1_is_rel;
29e9b073
CL		 9069 if (globals->fdpic_p)
9070 globals->target2_reloc = R_ARM_GOT32;
9071 else if (strcmp (params->target2_type, "rel") == 0)
eb043451 9072 globals->target2_reloc = R_ARM_REL32;
68c39892 9073 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 9074 globals->target2_reloc = R_ARM_ABS32;
68c39892 9075 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 9076 globals->target2_reloc = R_ARM_GOT_PREL;
9077 else
9078 {
90b6238f 9079 _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"),
68c39892 9080 params->target2_type);
eb043451 9081 }
68c39892
TP		 9082 globals->fix_v4bx = params->fix_v4bx;
9083 globals->use_blx |= params->use_blx;
9084 globals->vfp11_fix = params->vfp11_denorm_fix;
9085 globals->stm32l4xx_fix = params->stm32l4xx_fix;
e8b09b87
CL		 9086 if (globals->fdpic_p)
9087 globals->pic_veneer = 1;
9088 else
9089 globals->pic_veneer = params->pic_veneer;
68c39892
TP		 9090 globals->fix_cortex_a8 = params->fix_cortex_a8;
9091 globals->fix_arm1176 = params->fix_arm1176;
9092 globals->cmse_implib = params->cmse_implib;
9093 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 9094
0ffa91dd 9095 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 9096 elf_arm_tdata (output_bfd)->no_enum_size_warning
9097 = params->no_enum_size_warning;
9098 elf_arm_tdata (output_bfd)->no_wchar_size_warning
9099 = params->no_wchar_size_warning;
eb043451 9100}
eb043451 9101
12a0a0fd 9102/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 9103
12a0a0fd
PB		 9104static void
9105insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
9106{
9107 bfd_vma upper;
9108 bfd_vma lower;
9109 int reloc_sign;
9110
9111 BFD_ASSERT ((offset & 1) == 0);
9112
9113 upper = bfd_get_16 (abfd, insn);
9114 lower = bfd_get_16 (abfd, insn + 2);
9115 reloc_sign = (offset < 0) ? 1 : 0;
9116 upper = (upper & ~(bfd_vma) 0x7ff)
9117 | ((offset >> 12) & 0x3ff)
9118 | (reloc_sign << 10);
906e58ca 9119 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 9120 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
9121 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
9122 | ((offset >> 1) & 0x7ff);
9123 bfd_put_16 (abfd, upper, insn);
9124 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 9125}
9126
9b485d32
NC		 9127/* Thumb code calling an ARM function. */
9128
252b5132 9129static int
57e8b36a 9130elf32_thumb_to_arm_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9131 const char * name,
9132 bfd * input_bfd,
9133 bfd * output_bfd,
9134 asection * input_section,
9135 bfd_byte * hit_data,
9136 asection * sym_sec,
9137 bfd_vma offset,
9138 bfd_signed_vma addend,
9139 bfd_vma val,
f2a9dd69 9140 char **error_message)
252b5132 9141{
bcbdc74c 9142 asection * s = 0;
dc810e39 9143 bfd_vma my_offset;
252b5132 9144 long int ret_offset;
bcbdc74c
NC		 9145 struct elf_link_hash_entry * myh;
9146 struct elf32_arm_link_hash_table * globals;
252b5132 9147
f2a9dd69 9148 myh = find_thumb_glue (info, name, error_message);
252b5132 9149 if (myh == NULL)
b34976b6 9150 return FALSE;
252b5132
RH		 9151
9152 globals = elf32_arm_hash_table (info);
252b5132
RH		 9153 BFD_ASSERT (globals != NULL);
9154 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9155
9156 my_offset = myh->root.u.def.value;
9157
3d4d4302
AM		 9158 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9159 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 9160
9161 BFD_ASSERT (s != NULL);
9162 BFD_ASSERT (s->contents != NULL);
9163 BFD_ASSERT (s->output_section != NULL);
9164
9165 if ((my_offset & 0x01) == 0x01)
9166 {
9167 if (sym_sec != NULL
9168 && sym_sec->owner != NULL
9169 && !INTERWORK_FLAG (sym_sec->owner))
9170 {
4eca0228 9171 _bfd_error_handler
90b6238f
AM		 9172 (_("%pB(%s): warning: interworking not enabled;"
9173 " first occurrence: %pB: %s call to %s"),
9174 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
252b5132 9175
b34976b6 9176 return FALSE;
252b5132
RH		 9177 }
9178
9179 --my_offset;
9180 myh->root.u.def.value = my_offset;
9181
52ab56c2
PB		 9182 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
9183 s->contents + my_offset);
252b5132 9184
52ab56c2
PB		 9185 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
9186 s->contents + my_offset + 2);
252b5132
RH		 9187
9188 ret_offset =
9b485d32
NC		 9189 /* Address of destination of the stub. */
9190 ((bfd_signed_vma) val)
252b5132 9191 - ((bfd_signed_vma)
57e8b36a
NC		 9192 /* Offset from the start of the current section
9193 to the start of the stubs. */
9b485d32
NC		 9194 (s->output_offset
9195 /* Offset of the start of this stub from the start of the stubs. */
9196 + my_offset
9197 /* Address of the start of the current section. */
9198 + s->output_section->vma)
9199 /* The branch instruction is 4 bytes into the stub. */
9200 + 4
9201 /* ARM branches work from the pc of the instruction + 8. */
9202 + 8);
252b5132 9203
52ab56c2
PB		 9204 put_arm_insn (globals, output_bfd,
9205 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
9206 s->contents + my_offset + 4);
252b5132
RH		 9207 }
9208
9209 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
9210
427bfd90
NC		 9211 /* Now go back and fix up the original BL insn to point to here. */
9212 ret_offset =
9213 /* Address of where the stub is located. */
9214 (s->output_section->vma + s->output_offset + my_offset)
9215 /* Address of where the BL is located. */
57e8b36a
NC		 9216 - (input_section->output_section->vma + input_section->output_offset
9217 + offset)
427bfd90
NC		 9218 /* Addend in the relocation. */
9219 - addend
9220 /* Biassing for PC-relative addressing. */
9221 - 8;
252b5132 9222
12a0a0fd 9223 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 9224
b34976b6 9225 return TRUE;
252b5132
RH		 9226}
9227
a4fd1a8e 9228/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 9229
a4fd1a8e
PB		 9230static struct elf_link_hash_entry *
9231elf32_arm_create_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9232 const char * name,
9233 bfd * input_bfd,
9234 bfd * output_bfd,
9235 asection * sym_sec,
9236 bfd_vma val,
9237 asection * s,
9238 char ** error_message)
252b5132 9239{
dc810e39 9240 bfd_vma my_offset;
252b5132 9241 long int ret_offset;
bcbdc74c
NC		 9242 struct elf_link_hash_entry * myh;
9243 struct elf32_arm_link_hash_table * globals;
252b5132 9244
f2a9dd69 9245 myh = find_arm_glue (info, name, error_message);
252b5132 9246 if (myh == NULL)
a4fd1a8e 9247 return NULL;
252b5132
RH		 9248
9249 globals = elf32_arm_hash_table (info);
252b5132
RH		 9250 BFD_ASSERT (globals != NULL);
9251 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9252
9253 my_offset = myh->root.u.def.value;
252b5132
RH		 9254
9255 if ((my_offset & 0x01) == 0x01)
9256 {
9257 if (sym_sec != NULL
9258 && sym_sec->owner != NULL
9259 && !INTERWORK_FLAG (sym_sec->owner))
9260 {
4eca0228 9261 _bfd_error_handler
90b6238f
AM		 9262 (_("%pB(%s): warning: interworking not enabled;"
9263 " first occurrence: %pB: %s call to %s"),
9264 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
252b5132 9265 }
9b485d32 9266
252b5132
RH		 9267 --my_offset;
9268 myh->root.u.def.value = my_offset;
9269
0e1862bb
L		 9270 if (bfd_link_pic (info)
9271 || globals->root.is_relocatable_executable
27e55c4d 9272 || globals->pic_veneer)
8f6277f5
PB		 9273 {
9274 /* For relocatable objects we can't use absolute addresses,
9275 so construct the address from a relative offset. */
9276 /* TODO: If the offset is small it's probably worth
9277 constructing the address with adds. */
52ab56c2
PB		 9278 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
9279 s->contents + my_offset);
9280 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
9281 s->contents + my_offset + 4);
9282 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
9283 s->contents + my_offset + 8);
8f6277f5
PB		 9284 /* Adjust the offset by 4 for the position of the add,
9285 and 8 for the pipeline offset. */
9286 ret_offset = (val - (s->output_offset
9287 + s->output_section->vma
9288 + my_offset + 12))
9289 | 1;
9290 bfd_put_32 (output_bfd, ret_offset,
9291 s->contents + my_offset + 12);
9292 }
26079076
PB		 9293 else if (globals->use_blx)
9294 {
9295 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
9296 s->contents + my_offset);
9297
9298 /* It's a thumb address. Add the low order bit. */
9299 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
9300 s->contents + my_offset + 4);
9301 }
8f6277f5
PB		 9302 else
9303 {
52ab56c2
PB		 9304 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
9305 s->contents + my_offset);
252b5132 9306
52ab56c2
PB		 9307 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
9308 s->contents + my_offset + 4);
252b5132 9309
8f6277f5
PB		 9310 /* It's a thumb address. Add the low order bit. */
9311 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
9312 s->contents + my_offset + 8);
8029a119
NC		 9313
9314 my_offset += 12;
8f6277f5 9315 }
252b5132
RH		 9316 }
9317
9318 BFD_ASSERT (my_offset <= globals->arm_glue_size);
9319
a4fd1a8e
PB		 9320 return myh;
9321}
9322
9323/* Arm code calling a Thumb function. */
9324
9325static int
9326elf32_arm_to_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9327 const char * name,
9328 bfd * input_bfd,
9329 bfd * output_bfd,
9330 asection * input_section,
9331 bfd_byte * hit_data,
9332 asection * sym_sec,
9333 bfd_vma offset,
9334 bfd_signed_vma addend,
9335 bfd_vma val,
f2a9dd69 9336 char **error_message)
a4fd1a8e
PB		 9337{
9338 unsigned long int tmp;
9339 bfd_vma my_offset;
9340 asection * s;
9341 long int ret_offset;
9342 struct elf_link_hash_entry * myh;
9343 struct elf32_arm_link_hash_table * globals;
9344
9345 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9346 BFD_ASSERT (globals != NULL);
9347 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9348
3d4d4302
AM		 9349 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9350 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9351 BFD_ASSERT (s != NULL);
9352 BFD_ASSERT (s->contents != NULL);
9353 BFD_ASSERT (s->output_section != NULL);
9354
9355 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 9356 sym_sec, val, s, error_message);
a4fd1a8e
PB		 9357 if (!myh)
9358 return FALSE;
9359
9360 my_offset = myh->root.u.def.value;
252b5132
RH		 9361 tmp = bfd_get_32 (input_bfd, hit_data);
9362 tmp = tmp & 0xFF000000;
9363
9b485d32 9364 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9365 ret_offset = (s->output_offset
9366 + my_offset
9367 + s->output_section->vma
9368 - (input_section->output_offset
9369 + input_section->output_section->vma
9370 + offset + addend)
9371 - 8);
9a5aca8c 9372
252b5132
RH		 9373 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9374
dc810e39 9375 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9376
b34976b6 9377 return TRUE;
252b5132
RH		 9378}
9379
a4fd1a8e
PB		 9380/* Populate Arm stub for an exported Thumb function. */
9381
9382static bfd_boolean
9383elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9384{
9385 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9386 asection * s;
9387 struct elf_link_hash_entry * myh;
9388 struct elf32_arm_link_hash_entry *eh;
9389 struct elf32_arm_link_hash_table * globals;
9390 asection *sec;
9391 bfd_vma val;
f2a9dd69 9392 char *error_message;
a4fd1a8e 9393
906e58ca 9394 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9395 /* Allocate stubs for exported Thumb functions on v4t. */
9396 if (eh->export_glue == NULL)
9397 return TRUE;
9398
9399 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9400 BFD_ASSERT (globals != NULL);
9401 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9402
3d4d4302
AM		 9403 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9404 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9405 BFD_ASSERT (s != NULL);
9406 BFD_ASSERT (s->contents != NULL);
9407 BFD_ASSERT (s->output_section != NULL);
9408
9409 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9410
9411 BFD_ASSERT (sec->output_section != NULL);
9412
a4fd1a8e
PB		 9413 val = eh->export_glue->root.u.def.value + sec->output_offset
9414 + sec->output_section->vma;
8029a119 9415
a4fd1a8e
PB		 9416 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9417 h->root.u.def.section->owner,
f2a9dd69
DJ		 9418 globals->obfd, sec, val, s,
9419 &error_message);
a4fd1a8e
PB		 9420 BFD_ASSERT (myh);
9421 return TRUE;
9422}
9423
845b51d6
PB		 9424/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9425
9426static bfd_vma
9427elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9428{
9429 bfd_byte *p;
9430 bfd_vma glue_addr;
9431 asection *s;
9432 struct elf32_arm_link_hash_table *globals;
9433
9434 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9435 BFD_ASSERT (globals != NULL);
9436 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9437
3d4d4302
AM		 9438 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9439 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9440 BFD_ASSERT (s != NULL);
9441 BFD_ASSERT (s->contents != NULL);
9442 BFD_ASSERT (s->output_section != NULL);
9443
9444 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9445
9446 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9447
9448 if ((globals->bx_glue_offset[reg] & 1) == 0)
9449 {
9450 p = s->contents + glue_addr;
9451 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9452 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9453 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9454 globals->bx_glue_offset[reg] |= 1;
9455 }
9456
9457 return glue_addr + s->output_section->vma + s->output_offset;
9458}
9459
a4fd1a8e
PB		 9460/* Generate Arm stubs for exported Thumb symbols. */
9461static void
906e58ca 9462elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9463 struct bfd_link_info *link_info)
9464{
9465 struct elf32_arm_link_hash_table * globals;
9466
8029a119
NC		 9467 if (link_info == NULL)
9468 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9469 return;
9470
9471 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9472 if (globals == NULL)
9473 return;
9474
84c08195
PB		 9475 /* If blx is available then exported Thumb symbols are OK and there is
9476 nothing to do. */
a4fd1a8e
PB		 9477 if (globals->use_blx)
9478 return;
9479
9480 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9481 link_info);
9482}
9483
47beaa6a
RS		 9484/* Reserve space for COUNT dynamic relocations in relocation selection
9485 SRELOC. */
9486
9487static void
9488elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9489 bfd_size_type count)
9490{
9491 struct elf32_arm_link_hash_table *htab;
9492
9493 htab = elf32_arm_hash_table (info);
9494 BFD_ASSERT (htab->root.dynamic_sections_created);
9495 if (sreloc == NULL)
9496 abort ();
9497 sreloc->size += RELOC_SIZE (htab) * count;
9498}
9499
34e77a92
RS		 9500/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9501 dynamic, the relocations should go in SRELOC, otherwise they should
9502 go in the special .rel.iplt section. */
9503
9504static void
9505elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9506 bfd_size_type count)
9507{
9508 struct elf32_arm_link_hash_table *htab;
9509
9510 htab = elf32_arm_hash_table (info);
9511 if (!htab->root.dynamic_sections_created)
9512 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9513 else
9514 {
9515 BFD_ASSERT (sreloc != NULL);
9516 sreloc->size += RELOC_SIZE (htab) * count;
9517 }
9518}
9519
47beaa6a
RS		 9520/* Add relocation REL to the end of relocation section SRELOC. */
9521
9522static void
9523elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9524 asection *sreloc, Elf_Internal_Rela *rel)
9525{
9526 bfd_byte *loc;
9527 struct elf32_arm_link_hash_table *htab;
9528
9529 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9530 if (!htab->root.dynamic_sections_created
9531 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9532 sreloc = htab->root.irelplt;
47beaa6a
RS		 9533 if (sreloc == NULL)
9534 abort ();
9535 loc = sreloc->contents;
9536 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9537 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9538 abort ();
9539 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9540}
9541
34e77a92
RS		 9542/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9543 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9544 to .plt. */
9545
9546static void
9547elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9548 bfd_boolean is_iplt_entry,
9549 union gotplt_union *root_plt,
9550 struct arm_plt_info *arm_plt)
9551{
9552 struct elf32_arm_link_hash_table *htab;
9553 asection *splt;
9554 asection *sgotplt;
9555
9556 htab = elf32_arm_hash_table (info);
9557
9558 if (is_iplt_entry)
9559 {
9560 splt = htab->root.iplt;
9561 sgotplt = htab->root.igotplt;
9562
99059e56
RM		 9563 /* NaCl uses a special first entry in .iplt too. */
9564 if (htab->nacl_p && splt->size == 0)
9565 splt->size += htab->plt_header_size;
9566
34e77a92
RS		 9567 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9568 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9569 }
9570 else
9571 {
9572 splt = htab->root.splt;
9573 sgotplt = htab->root.sgotplt;
9574
7801f98f
CL		 9575 if (htab->fdpic_p)
9576 {
9577 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9578 /* For lazy binding, relocations will be put into .rel.plt, in
9579 .rel.got otherwise. */
9580 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9581 if (info->flags & DF_BIND_NOW)
9582 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
9583 else
9584 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9585 }
9586 else
9587 {
9588 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9589 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9590 }
34e77a92
RS		 9591
9592 /* If this is the first .plt entry, make room for the special
9593 first entry. */
9594 if (splt->size == 0)
9595 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9596
9597 htab->next_tls_desc_index++;
34e77a92
RS		 9598 }
9599
9600 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9601 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9602 splt->size += PLT_THUMB_STUB_SIZE;
9603 root_plt->offset = splt->size;
9604 splt->size += htab->plt_entry_size;
9605
9606 if (!htab->symbian_p)
9607 {
9608 /* We also need to make an entry in the .got.plt section, which
9609 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9610 if (is_iplt_entry)
9611 arm_plt->got_offset = sgotplt->size;
9612 else
9613 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
7801f98f
CL		 9614 if (htab->fdpic_p)
9615 /* Function descriptor takes 64 bits in GOT. */
4b24dd1a 9616 sgotplt->size += 8;
7801f98f
CL		 9617 else
9618 sgotplt->size += 4;
34e77a92
RS		 9619 }
9620}
9621
b38cadfb
NC		 9622static bfd_vma
9623arm_movw_immediate (bfd_vma value)
9624{
9625 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9626}
9627
9628static bfd_vma
9629arm_movt_immediate (bfd_vma value)
9630{
9631 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9632}
9633
34e77a92
RS		 9634/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9635 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9636 Otherwise, DYNINDX is the index of the symbol in the dynamic
9637 symbol table and SYM_VALUE is undefined.
9638
9639 ROOT_PLT points to the offset of the PLT entry from the start of its
9640 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9641 bookkeeping information.
34e77a92 9642
57460bcf
NC		 9643 Returns FALSE if there was a problem. */
9644
9645static bfd_boolean
34e77a92
RS		 9646elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9647 union gotplt_union *root_plt,
9648 struct arm_plt_info *arm_plt,
9649 int dynindx, bfd_vma sym_value)
9650{
9651 struct elf32_arm_link_hash_table *htab;
9652 asection *sgot;
9653 asection *splt;
9654 asection *srel;
9655 bfd_byte *loc;
9656 bfd_vma plt_index;
9657 Elf_Internal_Rela rel;
9658 bfd_vma plt_header_size;
9659 bfd_vma got_header_size;
9660
9661 htab = elf32_arm_hash_table (info);
9662
9663 /* Pick the appropriate sections and sizes. */
9664 if (dynindx == -1)
9665 {
9666 splt = htab->root.iplt;
9667 sgot = htab->root.igotplt;
9668 srel = htab->root.irelplt;
9669
9670 /* There are no reserved entries in .igot.plt, and no special
9671 first entry in .iplt. */
9672 got_header_size = 0;
9673 plt_header_size = 0;
9674 }
9675 else
9676 {
9677 splt = htab->root.splt;
9678 sgot = htab->root.sgotplt;
9679 srel = htab->root.srelplt;
9680
9681 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9682 plt_header_size = htab->plt_header_size;
9683 }
9684 BFD_ASSERT (splt != NULL && srel != NULL);
9685
9686 /* Fill in the entry in the procedure linkage table. */
9687 if (htab->symbian_p)
9688 {
9689 BFD_ASSERT (dynindx >= 0);
9690 put_arm_insn (htab, output_bfd,
9691 elf32_arm_symbian_plt_entry[0],
9692 splt->contents + root_plt->offset);
9693 bfd_put_32 (output_bfd,
9694 elf32_arm_symbian_plt_entry[1],
9695 splt->contents + root_plt->offset + 4);
9696
9697 /* Fill in the entry in the .rel.plt section. */
9698 rel.r_offset = (splt->output_section->vma
9699 + splt->output_offset
9700 + root_plt->offset + 4);
9701 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9702
9703 /* Get the index in the procedure linkage table which
9704 corresponds to this symbol. This is the index of this symbol
9705 in all the symbols for which we are making plt entries. The
9706 first entry in the procedure linkage table is reserved. */
9707 plt_index = ((root_plt->offset - plt_header_size)
9708 / htab->plt_entry_size);
9709 }
9710 else
9711 {
9712 bfd_vma got_offset, got_address, plt_address;
9713 bfd_vma got_displacement, initial_got_entry;
9714 bfd_byte * ptr;
9715
9716 BFD_ASSERT (sgot != NULL);
9717
9718 /* Get the offset into the .(i)got.plt table of the entry that
9719 corresponds to this function. */
9720 got_offset = (arm_plt->got_offset & -2);
9721
9722 /* Get the index in the procedure linkage table which
9723 corresponds to this symbol. This is the index of this symbol
9724 in all the symbols for which we are making plt entries.
9725 After the reserved .got.plt entries, all symbols appear in
9726 the same order as in .plt. */
7801f98f 9727 if (htab->fdpic_p)
4b24dd1a
AM		 9728 /* Function descriptor takes 8 bytes. */
9729 plt_index = (got_offset - got_header_size) / 8;
7801f98f 9730 else
4b24dd1a 9731 plt_index = (got_offset - got_header_size) / 4;
34e77a92
RS		 9732
9733 /* Calculate the address of the GOT entry. */
9734 got_address = (sgot->output_section->vma
9735 + sgot->output_offset
9736 + got_offset);
9737
9738 /* ...and the address of the PLT entry. */
9739 plt_address = (splt->output_section->vma
9740 + splt->output_offset
9741 + root_plt->offset);
9742
9743 ptr = splt->contents + root_plt->offset;
0e1862bb 9744 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9745 {
9746 unsigned int i;
9747 bfd_vma val;
9748
9749 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9750 {
9751 val = elf32_arm_vxworks_shared_plt_entry[i];
9752 if (i == 2)
9753 val |= got_address - sgot->output_section->vma;
9754 if (i == 5)
9755 val |= plt_index * RELOC_SIZE (htab);
9756 if (i == 2 || i == 5)
9757 bfd_put_32 (output_bfd, val, ptr);
9758 else
9759 put_arm_insn (htab, output_bfd, val, ptr);
9760 }
9761 }
9762 else if (htab->vxworks_p)
9763 {
9764 unsigned int i;
9765 bfd_vma val;
9766
9767 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9768 {
9769 val = elf32_arm_vxworks_exec_plt_entry[i];
9770 if (i == 2)
9771 val |= got_address;
9772 if (i == 4)
9773 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9774 if (i == 5)
9775 val |= plt_index * RELOC_SIZE (htab);
9776 if (i == 2 || i == 5)
9777 bfd_put_32 (output_bfd, val, ptr);
9778 else
9779 put_arm_insn (htab, output_bfd, val, ptr);
9780 }
9781
9782 loc = (htab->srelplt2->contents
9783 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9784
9785 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9786 referencing the GOT for this PLT entry. */
9787 rel.r_offset = plt_address + 8;
9788 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9789 rel.r_addend = got_offset;
9790 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9791 loc += RELOC_SIZE (htab);
9792
9793 /* Create the R_ARM_ABS32 relocation referencing the
9794 beginning of the PLT for this GOT entry. */
9795 rel.r_offset = got_address;
9796 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9797 rel.r_addend = 0;
9798 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9799 }
b38cadfb
NC		 9800 else if (htab->nacl_p)
9801 {
9802 /* Calculate the displacement between the PLT slot and the
9803 common tail that's part of the special initial PLT slot. */
6034aab8 9804 int32_t tail_displacement
b38cadfb
NC		 9805 = ((splt->output_section->vma + splt->output_offset
9806 + ARM_NACL_PLT_TAIL_OFFSET)
9807 - (plt_address + htab->plt_entry_size + 4));
9808 BFD_ASSERT ((tail_displacement & 3) == 0);
9809 tail_displacement >>= 2;
9810
9811 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9812 || (-tail_displacement & 0xff000000) == 0);
9813
9814 /* Calculate the displacement between the PLT slot and the entry
9815 in the GOT. The offset accounts for the value produced by
9816 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9817 got_displacement = (got_address
99059e56 9818 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9819
9820 /* NaCl does not support interworking at all. */
9821 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9822
9823 put_arm_insn (htab, output_bfd,
9824 elf32_arm_nacl_plt_entry[0]
9825 | arm_movw_immediate (got_displacement),
9826 ptr + 0);
9827 put_arm_insn (htab, output_bfd,
9828 elf32_arm_nacl_plt_entry[1]
9829 | arm_movt_immediate (got_displacement),
9830 ptr + 4);
9831 put_arm_insn (htab, output_bfd,
9832 elf32_arm_nacl_plt_entry[2],
9833 ptr + 8);
9834 put_arm_insn (htab, output_bfd,
9835 elf32_arm_nacl_plt_entry[3]
9836 | (tail_displacement & 0x00ffffff),
9837 ptr + 12);
9838 }
7801f98f
CL		 9839 else if (htab->fdpic_p)
9840 {
59029f57
CL		 9841 const bfd_vma *plt_entry = using_thumb_only(htab)
9842 ? elf32_arm_fdpic_thumb_plt_entry
9843 : elf32_arm_fdpic_plt_entry;
9844
7801f98f
CL		 9845 /* Fill-up Thumb stub if needed. */
9846 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9847 {
9848 put_thumb_insn (htab, output_bfd,
9849 elf32_arm_plt_thumb_stub[0], ptr - 4);
9850 put_thumb_insn (htab, output_bfd,
9851 elf32_arm_plt_thumb_stub[1], ptr - 2);
9852 }
59029f57
CL		 9853 /* As we are using 32 bit instructions even for the Thumb
9854 version, we have to use 'put_arm_insn' instead of
9855 'put_thumb_insn'. */
9856 put_arm_insn(htab, output_bfd, plt_entry[0], ptr + 0);
9857 put_arm_insn(htab, output_bfd, plt_entry[1], ptr + 4);
9858 put_arm_insn(htab, output_bfd, plt_entry[2], ptr + 8);
9859 put_arm_insn(htab, output_bfd, plt_entry[3], ptr + 12);
7801f98f
CL		 9860 bfd_put_32 (output_bfd, got_offset, ptr + 16);
9861
9862 if (!(info->flags & DF_BIND_NOW))
9863 {
9864 /* funcdesc_value_reloc_offset. */
9865 bfd_put_32 (output_bfd,
9866 htab->root.srelplt->reloc_count * RELOC_SIZE (htab),
9867 ptr + 20);
59029f57
CL		 9868 put_arm_insn(htab, output_bfd, plt_entry[6], ptr + 24);
9869 put_arm_insn(htab, output_bfd, plt_entry[7], ptr + 28);
9870 put_arm_insn(htab, output_bfd, plt_entry[8], ptr + 32);
9871 put_arm_insn(htab, output_bfd, plt_entry[9], ptr + 36);
7801f98f
CL		 9872 }
9873 }
57460bcf
NC		 9874 else if (using_thumb_only (htab))
9875 {
eed94f8f 9876 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9877 if (!using_thumb2 (htab))
eed94f8f
NC		 9878 {
9879 /* FIXME: We ought to be able to generate thumb-1 PLT
9880 instructions... */
90b6238f 9881 _bfd_error_handler (_("%pB: warning: thumb-1 mode PLT generation not currently supported"),
eed94f8f
NC		 9882 output_bfd);
9883 return FALSE;
9884 }
57460bcf 9885
eed94f8f
NC		 9886 /* Calculate the displacement between the PLT slot and the entry in
9887 the GOT. The 12-byte offset accounts for the value produced by
9888 adding to pc in the 3rd instruction of the PLT stub. */
9889 got_displacement = got_address - (plt_address + 12);
9890
9891 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9892 instead of 'put_thumb_insn'. */
9893 put_arm_insn (htab, output_bfd,
9894 elf32_thumb2_plt_entry[0]
9895 | ((got_displacement & 0x000000ff) << 16)
9896 | ((got_displacement & 0x00000700) << 20)
9897 | ((got_displacement & 0x00000800) >> 1)
9898 | ((got_displacement & 0x0000f000) >> 12),
9899 ptr + 0);
9900 put_arm_insn (htab, output_bfd,
9901 elf32_thumb2_plt_entry[1]
9902 | ((got_displacement & 0x00ff0000) )
9903 | ((got_displacement & 0x07000000) << 4)
9904 | ((got_displacement & 0x08000000) >> 17)
9905 | ((got_displacement & 0xf0000000) >> 28),
9906 ptr + 4);
9907 put_arm_insn (htab, output_bfd,
9908 elf32_thumb2_plt_entry[2],
9909 ptr + 8);
9910 put_arm_insn (htab, output_bfd,
9911 elf32_thumb2_plt_entry[3],
9912 ptr + 12);
57460bcf 9913 }
34e77a92
RS		 9914 else
9915 {
9916 /* Calculate the displacement between the PLT slot and the
9917 entry in the GOT. The eight-byte offset accounts for the
9918 value produced by adding to pc in the first instruction
9919 of the PLT stub. */
9920 got_displacement = got_address - (plt_address + 8);
9921
34e77a92
RS		 9922 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9923 {
9924 put_thumb_insn (htab, output_bfd,
9925 elf32_arm_plt_thumb_stub[0], ptr - 4);
9926 put_thumb_insn (htab, output_bfd,
9927 elf32_arm_plt_thumb_stub[1], ptr - 2);
9928 }
9929
1db37fe6
YG		 9930 if (!elf32_arm_use_long_plt_entry)
9931 {
9932 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9933
9934 put_arm_insn (htab, output_bfd,
9935 elf32_arm_plt_entry_short[0]
9936 | ((got_displacement & 0x0ff00000) >> 20),
9937 ptr + 0);
9938 put_arm_insn (htab, output_bfd,
9939 elf32_arm_plt_entry_short[1]
9940 | ((got_displacement & 0x000ff000) >> 12),
9941 ptr+ 4);
9942 put_arm_insn (htab, output_bfd,
9943 elf32_arm_plt_entry_short[2]
9944 | (got_displacement & 0x00000fff),
9945 ptr + 8);
34e77a92 9946#ifdef FOUR_WORD_PLT
1db37fe6 9947 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9948#endif
1db37fe6
YG		 9949 }
9950 else
9951 {
9952 put_arm_insn (htab, output_bfd,
9953 elf32_arm_plt_entry_long[0]
9954 | ((got_displacement & 0xf0000000) >> 28),
9955 ptr + 0);
9956 put_arm_insn (htab, output_bfd,
9957 elf32_arm_plt_entry_long[1]
9958 | ((got_displacement & 0x0ff00000) >> 20),
9959 ptr + 4);
9960 put_arm_insn (htab, output_bfd,
9961 elf32_arm_plt_entry_long[2]
9962 | ((got_displacement & 0x000ff000) >> 12),
9963 ptr+ 8);
9964 put_arm_insn (htab, output_bfd,
9965 elf32_arm_plt_entry_long[3]
9966 | (got_displacement & 0x00000fff),
9967 ptr + 12);
9968 }
34e77a92
RS		 9969 }
9970
9971 /* Fill in the entry in the .rel(a).(i)plt section. */
9972 rel.r_offset = got_address;
9973 rel.r_addend = 0;
9974 if (dynindx == -1)
9975 {
9976 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9977 The dynamic linker or static executable then calls SYM_VALUE
9978 to determine the correct run-time value of the .igot.plt entry. */
9979 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9980 initial_got_entry = sym_value;
9981 }
9982 else
9983 {
7801f98f
CL		 9984 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9985 used by PLT entry. */
9986 if (htab->fdpic_p)
9987 {
9988 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
9989 initial_got_entry = 0;
9990 }
9991 else
9992 {
9993 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9994 initial_got_entry = (splt->output_section->vma
9995 + splt->output_offset);
9996 }
34e77a92
RS		 9997 }
9998
9999 /* Fill in the entry in the global offset table. */
10000 bfd_put_32 (output_bfd, initial_got_entry,
10001 sgot->contents + got_offset);
7801f98f
CL		 10002
10003 if (htab->fdpic_p && !(info->flags & DF_BIND_NOW))
10004 {
10005 /* Setup initial funcdesc value. */
10006 /* FIXME: we don't support lazy binding because there is a
10007 race condition between both words getting written and
10008 some other thread attempting to read them. The ARM
10009 architecture does not have an atomic 64 bit load/store
10010 instruction that could be used to prevent it; it is
10011 recommended that threaded FDPIC applications run with the
10012 LD_BIND_NOW environment variable set. */
10013 bfd_put_32(output_bfd, plt_address + 0x18,
10014 sgot->contents + got_offset);
10015 bfd_put_32(output_bfd, -1 /*TODO*/,
10016 sgot->contents + got_offset + 4);
10017 }
34e77a92
RS		 10018 }
10019
aba8c3de
WN		 10020 if (dynindx == -1)
10021 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
10022 else
10023 {
7801f98f
CL		 10024 if (htab->fdpic_p)
10025 {
10026 /* For FDPIC we put PLT relocationss into .rel.got when not
10027 lazy binding otherwise we put them in .rel.plt. For now,
10028 we don't support lazy binding so put it in .rel.got. */
10029 if (info->flags & DF_BIND_NOW)
10030 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelgot, &rel);
10031 else
10032 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelplt, &rel);
10033 }
10034 else
10035 {
10036 loc = srel->contents + plt_index * RELOC_SIZE (htab);
10037 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
10038 }
aba8c3de 10039 }
57460bcf
NC		 10040
10041 return TRUE;
34e77a92
RS		 10042}
10043
eb043451
PB		 10044/* Some relocations map to different relocations depending on the
10045 target. Return the real relocation. */
8029a119 10046
eb043451
PB		 10047static int
10048arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
10049 int r_type)
10050{
10051 switch (r_type)
10052 {
10053 case R_ARM_TARGET1:
10054 if (globals->target1_is_rel)
10055 return R_ARM_REL32;
10056 else
10057 return R_ARM_ABS32;
10058
10059 case R_ARM_TARGET2:
10060 return globals->target2_reloc;
10061
10062 default:
10063 return r_type;
10064 }
10065}
eb043451 10066
ba93b8ac
DJ		 10067/* Return the base VMA address which should be subtracted from real addresses
10068 when resolving @dtpoff relocation.
10069 This is PT_TLS segment p_vaddr. */
10070
10071static bfd_vma
10072dtpoff_base (struct bfd_link_info *info)
10073{
10074 /* If tls_sec is NULL, we should have signalled an error already. */
10075 if (elf_hash_table (info)->tls_sec == NULL)
10076 return 0;
10077 return elf_hash_table (info)->tls_sec->vma;
10078}
10079
10080/* Return the relocation value for @tpoff relocation
10081 if STT_TLS virtual address is ADDRESS. */
10082
10083static bfd_vma
10084tpoff (struct bfd_link_info *info, bfd_vma address)
10085{
10086 struct elf_link_hash_table *htab = elf_hash_table (info);
10087 bfd_vma base;
10088
10089 /* If tls_sec is NULL, we should have signalled an error already. */
10090 if (htab->tls_sec == NULL)
10091 return 0;
10092 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
10093 return address - htab->tls_sec->vma + base;
10094}
10095
00a97672
RS		 10096/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10097 VALUE is the relocation value. */
10098
10099static bfd_reloc_status_type
10100elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
10101{
10102 if (value > 0xfff)
10103 return bfd_reloc_overflow;
10104
10105 value |= bfd_get_32 (abfd, data) & 0xfffff000;
10106 bfd_put_32 (abfd, value, data);
10107 return bfd_reloc_ok;
10108}
10109
0855e32b
NS		 10110/* Handle TLS relaxations. Relaxing is possible for symbols that use
10111 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10112 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10113
10114 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10115 is to then call final_link_relocate. Return other values in the
62672b10
NS		 10116 case of error.
10117
10118 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10119 the pre-relaxed code. It would be nice if the relocs were updated
10120 to match the optimization. */
0855e32b 10121
b38cadfb 10122static bfd_reloc_status_type
0855e32b 10123elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 10124 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 10125 Elf_Internal_Rela *rel, unsigned long is_local)
10126{
10127 unsigned long insn;
b38cadfb 10128
0855e32b
NS		 10129 switch (ELF32_R_TYPE (rel->r_info))
10130 {
10131 default:
10132 return bfd_reloc_notsupported;
b38cadfb 10133
0855e32b
NS		 10134 case R_ARM_TLS_GOTDESC:
10135 if (is_local)
10136 insn = 0;
10137 else
10138 {
10139 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10140 if (insn & 1)
10141 insn -= 5; /* THUMB */
10142 else
10143 insn -= 8; /* ARM */
10144 }
10145 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10146 return bfd_reloc_continue;
10147
10148 case R_ARM_THM_TLS_DESCSEQ:
10149 /* Thumb insn. */
10150 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
10151 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
10152 {
10153 if (is_local)
10154 /* nop */
10155 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10156 }
10157 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
10158 {
10159 if (is_local)
10160 /* nop */
10161 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10162 else
10163 /* ldr rx,[ry] */
10164 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
10165 }
10166 else if ((insn & 0xff87) == 0x4780) /* blx rx */
10167 {
10168 if (is_local)
10169 /* nop */
10170 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10171 else
10172 /* mov r0, rx */
10173 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
10174 contents + rel->r_offset);
10175 }
10176 else
10177 {
10178 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10179 /* It's a 32 bit instruction, fetch the rest of it for
10180 error generation. */
10181 insn = (insn << 16)
10182 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 10183 _bfd_error_handler
695344c0 10184 /* xgettext:c-format */
2dcf00ce 10185 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10186 "unexpected %s instruction '%#lx' in TLS trampoline"),
10187 input_bfd, input_sec, (uint64_t) rel->r_offset,
10188 "Thumb", insn);
0855e32b
NS		 10189 return bfd_reloc_notsupported;
10190 }
10191 break;
b38cadfb 10192
0855e32b
NS		 10193 case R_ARM_TLS_DESCSEQ:
10194 /* arm insn. */
10195 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10196 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
10197 {
10198 if (is_local)
10199 /* mov rx, ry */
10200 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
10201 contents + rel->r_offset);
10202 }
10203 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
10204 {
10205 if (is_local)
10206 /* nop */
10207 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10208 else
10209 /* ldr rx,[ry] */
10210 bfd_put_32 (input_bfd, insn & 0xfffff000,
10211 contents + rel->r_offset);
10212 }
10213 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
10214 {
10215 if (is_local)
10216 /* nop */
10217 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10218 else
10219 /* mov r0, rx */
10220 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
10221 contents + rel->r_offset);
10222 }
10223 else
10224 {
4eca0228 10225 _bfd_error_handler
695344c0 10226 /* xgettext:c-format */
2dcf00ce 10227 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10228 "unexpected %s instruction '%#lx' in TLS trampoline"),
10229 input_bfd, input_sec, (uint64_t) rel->r_offset,
10230 "ARM", insn);
0855e32b
NS		 10231 return bfd_reloc_notsupported;
10232 }
10233 break;
10234
10235 case R_ARM_TLS_CALL:
10236 /* GD->IE relaxation, turn the instruction into 'nop' or
10237 'ldr r0, [pc,r0]' */
10238 insn = is_local ? 0xe1a00000 : 0xe79f0000;
10239 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10240 break;
b38cadfb 10241
0855e32b 10242 case R_ARM_THM_TLS_CALL:
6a631e86 10243 /* GD->IE relaxation. */
0855e32b
NS		 10244 if (!is_local)
10245 /* add r0,pc; ldr r0, [r0] */
10246 insn = 0x44786800;
60a019a0 10247 else if (using_thumb2 (globals))
0855e32b
NS		 10248 /* nop.w */
10249 insn = 0xf3af8000;
10250 else
10251 /* nop; nop */
10252 insn = 0xbf00bf00;
b38cadfb 10253
0855e32b
NS		 10254 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
10255 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
10256 break;
10257 }
10258 return bfd_reloc_ok;
10259}
10260
4962c51a
MS		 10261/* For a given value of n, calculate the value of G_n as required to
10262 deal with group relocations. We return it in the form of an
10263 encoded constant-and-rotation, together with the final residual. If n is
10264 specified as less than zero, then final_residual is filled with the
10265 input value and no further action is performed. */
10266
10267static bfd_vma
10268calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
10269{
10270 int current_n;
10271 bfd_vma g_n;
10272 bfd_vma encoded_g_n = 0;
10273 bfd_vma residual = value; /* Also known as Y_n. */
10274
10275 for (current_n = 0; current_n <= n; current_n++)
10276 {
10277 int shift;
10278
10279 /* Calculate which part of the value to mask. */
10280 if (residual == 0)
99059e56 10281 shift = 0;
4962c51a 10282 else
99059e56
RM		 10283 {
10284 int msb;
10285
10286 /* Determine the most significant bit in the residual and
10287 align the resulting value to a 2-bit boundary. */
10288 for (msb = 30; msb >= 0; msb -= 2)
10289 if (residual & (3 << msb))
10290 break;
10291
10292 /* The desired shift is now (msb - 6), or zero, whichever
10293 is the greater. */
10294 shift = msb - 6;
10295 if (shift < 0)
10296 shift = 0;
10297 }
4962c51a
MS		 10298
10299 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10300 g_n = residual & (0xff << shift);
10301 encoded_g_n = (g_n >> shift)
99059e56 10302 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 10303
10304 /* Calculate the residual for the next time around. */
10305 residual &= ~g_n;
10306 }
10307
10308 *final_residual = residual;
10309
10310 return encoded_g_n;
10311}
10312
10313/* Given an ARM instruction, determine whether it is an ADD or a SUB.
10314 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 10315
4962c51a 10316static int
906e58ca 10317identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 10318{
10319 int opcode = insn & 0x1e00000;
10320
10321 if (opcode == 1 << 23) /* ADD */
10322 return 1;
10323
10324 if (opcode == 1 << 22) /* SUB */
10325 return -1;
10326
10327 return 0;
10328}
10329
252b5132 10330/* Perform a relocation as part of a final link. */
9b485d32 10331
252b5132 10332static bfd_reloc_status_type
07d6d2b8
AM		 10333elf32_arm_final_link_relocate (reloc_howto_type * howto,
10334 bfd * input_bfd,
10335 bfd * output_bfd,
10336 asection * input_section,
10337 bfd_byte * contents,
10338 Elf_Internal_Rela * rel,
10339 bfd_vma value,
10340 struct bfd_link_info * info,
10341 asection * sym_sec,
10342 const char * sym_name,
10343 unsigned char st_type,
10344 enum arm_st_branch_type branch_type,
0945cdfd 10345 struct elf_link_hash_entry * h,
07d6d2b8
AM		 10346 bfd_boolean * unresolved_reloc_p,
10347 char ** error_message)
10348{
10349 unsigned long r_type = howto->type;
10350 unsigned long r_symndx;
10351 bfd_byte * hit_data = contents + rel->r_offset;
10352 bfd_vma * local_got_offsets;
10353 bfd_vma * local_tlsdesc_gotents;
10354 asection * sgot;
10355 asection * splt;
10356 asection * sreloc = NULL;
10357 asection * srelgot;
10358 bfd_vma addend;
10359 bfd_signed_vma signed_addend;
10360 unsigned char dynreloc_st_type;
10361 bfd_vma dynreloc_value;
ba96a88f 10362 struct elf32_arm_link_hash_table * globals;
34e77a92 10363 struct elf32_arm_link_hash_entry *eh;
07d6d2b8
AM		 10364 union gotplt_union *root_plt;
10365 struct arm_plt_info *arm_plt;
10366 bfd_vma plt_offset;
10367 bfd_vma gotplt_offset;
10368 bfd_boolean has_iplt_entry;
10369 bfd_boolean resolved_to_zero;
f21f3fe0 10370
9c504268 10371 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 10372 if (globals == NULL)
10373 return bfd_reloc_notsupported;
9c504268 10374
0ffa91dd 10375 BFD_ASSERT (is_arm_elf (input_bfd));
47aeb64c 10376 BFD_ASSERT (howto != NULL);
0ffa91dd
NC		 10377
10378 /* Some relocation types map to different relocations depending on the
9c504268 10379 target. We pick the right one here. */
eb043451 10380 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 10381
10382 /* It is possible to have linker relaxations on some TLS access
10383 models. Update our information here. */
10384 r_type = elf32_arm_tls_transition (info, r_type, h);
10385
eb043451
PB		 10386 if (r_type != howto->type)
10387 howto = elf32_arm_howto_from_type (r_type);
9c504268 10388
34e77a92 10389 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 10390 sgot = globals->root.sgot;
252b5132 10391 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 10392 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
10393
34e77a92
RS		 10394 if (globals->root.dynamic_sections_created)
10395 srelgot = globals->root.srelgot;
10396 else
10397 srelgot = NULL;
10398
252b5132
RH		 10399 r_symndx = ELF32_R_SYM (rel->r_info);
10400
4e7fd91e 10401 if (globals->use_rel)
ba96a88f 10402 {
4e7fd91e
PB		 10403 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
10404
10405 if (addend & ((howto->src_mask + 1) >> 1))
10406 {
10407 signed_addend = -1;
10408 signed_addend &= ~ howto->src_mask;
10409 signed_addend |= addend;
10410 }
10411 else
10412 signed_addend = addend;
ba96a88f
NC		 10413 }
10414 else
4e7fd91e 10415 addend = signed_addend = rel->r_addend;
f21f3fe0 10416
39f21624
NC		 10417 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10418 are resolving a function call relocation. */
10419 if (using_thumb_only (globals)
10420 && (r_type == R_ARM_THM_CALL
10421 || r_type == R_ARM_THM_JUMP24)
10422 && branch_type == ST_BRANCH_TO_ARM)
10423 branch_type = ST_BRANCH_TO_THUMB;
10424
34e77a92
RS		 10425 /* Record the symbol information that should be used in dynamic
10426 relocations. */
10427 dynreloc_st_type = st_type;
10428 dynreloc_value = value;
10429 if (branch_type == ST_BRANCH_TO_THUMB)
10430 dynreloc_value |= 1;
10431
10432 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10433 VALUE appropriately for relocations that we resolve at link time. */
10434 has_iplt_entry = FALSE;
4ba2ef8f
TP		 10435 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
10436 &arm_plt)
34e77a92
RS		 10437 && root_plt->offset != (bfd_vma) -1)
10438 {
10439 plt_offset = root_plt->offset;
10440 gotplt_offset = arm_plt->got_offset;
10441
10442 if (h == NULL || eh->is_iplt)
10443 {
10444 has_iplt_entry = TRUE;
10445 splt = globals->root.iplt;
10446
10447 /* Populate .iplt entries here, because not all of them will
10448 be seen by finish_dynamic_symbol. The lower bit is set if
10449 we have already populated the entry. */
10450 if (plt_offset & 1)
10451 plt_offset--;
10452 else
10453 {
57460bcf
NC		 10454 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
10455 -1, dynreloc_value))
10456 root_plt->offset |= 1;
10457 else
10458 return bfd_reloc_notsupported;
34e77a92
RS		 10459 }
10460
10461 /* Static relocations always resolve to the .iplt entry. */
10462 st_type = STT_FUNC;
10463 value = (splt->output_section->vma
10464 + splt->output_offset
10465 + plt_offset);
10466 branch_type = ST_BRANCH_TO_ARM;
10467
10468 /* If there are non-call relocations that resolve to the .iplt
10469 entry, then all dynamic ones must too. */
10470 if (arm_plt->noncall_refcount != 0)
10471 {
10472 dynreloc_st_type = st_type;
10473 dynreloc_value = value;
10474 }
10475 }
10476 else
10477 /* We populate the .plt entry in finish_dynamic_symbol. */
10478 splt = globals->root.splt;
10479 }
10480 else
10481 {
10482 splt = NULL;
10483 plt_offset = (bfd_vma) -1;
10484 gotplt_offset = (bfd_vma) -1;
10485 }
10486
95b03e4a
L		 10487 resolved_to_zero = (h != NULL
10488 && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
10489
252b5132
RH		 10490 switch (r_type)
10491 {
10492 case R_ARM_NONE:
28a094c2
DJ		 10493 /* We don't need to find a value for this symbol. It's just a
10494 marker. */
10495 *unresolved_reloc_p = FALSE;
252b5132
RH		 10496 return bfd_reloc_ok;
10497
00a97672
RS		 10498 case R_ARM_ABS12:
10499 if (!globals->vxworks_p)
10500 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10501 /* Fall through. */
00a97672 10502
252b5132
RH		 10503 case R_ARM_PC24:
10504 case R_ARM_ABS32:
bb224fc3 10505 case R_ARM_ABS32_NOI:
252b5132 10506 case R_ARM_REL32:
bb224fc3 10507 case R_ARM_REL32_NOI:
5b5bb741
PB		 10508 case R_ARM_CALL:
10509 case R_ARM_JUMP24:
dfc5f959 10510 case R_ARM_XPC25:
eb043451 10511 case R_ARM_PREL31:
7359ea65 10512 case R_ARM_PLT32:
7359ea65
DJ		 10513 /* Handle relocations which should use the PLT entry. ABS32/REL32
10514 will use the symbol's value, which may point to a PLT entry, but we
10515 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10516 branches in this object should go to it, except if the PLT is too
10517 far away, in which case a long branch stub should be inserted. */
bb224fc3 10518 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10519 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10520 && r_type != R_ARM_CALL
10521 && r_type != R_ARM_JUMP24
10522 && r_type != R_ARM_PLT32)
34e77a92 10523 && plt_offset != (bfd_vma) -1)
7359ea65 10524 {
34e77a92
RS		 10525 /* If we've created a .plt section, and assigned a PLT entry
10526 to this function, it must either be a STT_GNU_IFUNC reference
10527 or not be known to bind locally. In other cases, we should
10528 have cleared the PLT entry by now. */
10529 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10530
10531 value = (splt->output_section->vma
10532 + splt->output_offset
34e77a92 10533 + plt_offset);
0945cdfd 10534 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10535 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10536 contents, rel->r_offset, value,
00a97672 10537 rel->r_addend);
7359ea65
DJ		 10538 }
10539
67687978
PB		 10540 /* When generating a shared object or relocatable executable, these
10541 relocations are copied into the output file to be resolved at
10542 run time. */
0e1862bb 10543 if ((bfd_link_pic (info)
e8b09b87
CL		 10544 || globals->root.is_relocatable_executable
10545 || globals->fdpic_p)
7359ea65 10546 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10547 && !(globals->vxworks_p
3348747a
NS		 10548 && strcmp (input_section->output_section->name,
10549 ".tls_vars") == 0)
bb224fc3 10550 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10551 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10552 && !(input_bfd == globals->stub_bfd
10553 && strstr (input_section->name, STUB_SUFFIX))
7359ea65 10554 && (h == NULL
95b03e4a
L		 10555 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10556 && !resolved_to_zero)
7359ea65
DJ		 10557 || h->root.type != bfd_link_hash_undefweak)
10558 && r_type != R_ARM_PC24
5b5bb741
PB		 10559 && r_type != R_ARM_CALL
10560 && r_type != R_ARM_JUMP24
ee06dc07 10561 && r_type != R_ARM_PREL31
7359ea65 10562 && r_type != R_ARM_PLT32)
252b5132 10563 {
947216bf 10564 Elf_Internal_Rela outrel;
b34976b6 10565 bfd_boolean skip, relocate;
e8b09b87 10566 int isrofixup = 0;
f21f3fe0 10567
52db4ec2
JW		 10568 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10569 && !h->def_regular)
10570 {
10571 char *v = _("shared object");
10572
0e1862bb 10573 if (bfd_link_executable (info))
52db4ec2
JW		 10574 v = _("PIE executable");
10575
4eca0228 10576 _bfd_error_handler
871b3ab2 10577 (_("%pB: relocation %s against external or undefined symbol `%s'"
52db4ec2
JW		 10578 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10579 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10580 return bfd_reloc_notsupported;
10581 }
10582
0945cdfd
DJ		 10583 *unresolved_reloc_p = FALSE;
10584
34e77a92 10585 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10586 {
83bac4b0
NC		 10587 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10588 ! globals->use_rel);
f21f3fe0 10589
83bac4b0 10590 if (sreloc == NULL)
252b5132 10591 return bfd_reloc_notsupported;
252b5132 10592 }
f21f3fe0 10593
b34976b6
AM		 10594 skip = FALSE;
10595 relocate = FALSE;
f21f3fe0 10596
00a97672 10597 outrel.r_addend = addend;
c629eae0
JJ		 10598 outrel.r_offset =
10599 _bfd_elf_section_offset (output_bfd, info, input_section,
10600 rel->r_offset);
10601 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10602 skip = TRUE;
0bb2d96a 10603 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10604 skip = TRUE, relocate = TRUE;
252b5132
RH		 10605 outrel.r_offset += (input_section->output_section->vma
10606 + input_section->output_offset);
f21f3fe0 10607
252b5132 10608 if (skip)
0bb2d96a 10609 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10610 else if (h != NULL
10611 && h->dynindx != -1
0e1862bb 10612 && (!bfd_link_pic (info)
1dcb9720
JW		 10613 || !(bfd_link_pie (info)
10614 || SYMBOLIC_BIND (info, h))
f5385ebf 10615 || !h->def_regular))
5e681ec4 10616 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10617 else
10618 {
a16385dc
MM		 10619 int symbol;
10620
5e681ec4 10621 /* This symbol is local, or marked to become local. */
e8b09b87
CL		 10622 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI
10623 || (globals->fdpic_p && !bfd_link_pic(info)));
a16385dc 10624 if (globals->symbian_p)
6366ff1e 10625 {
74541ad4
AM		 10626 asection *osec;
10627
6366ff1e
MM		 10628 /* On Symbian OS, the data segment and text segement
10629 can be relocated independently. Therefore, we
10630 must indicate the segment to which this
10631 relocation is relative. The BPABI allows us to
10632 use any symbol in the right segment; we just use
10633 the section symbol as it is convenient. (We
10634 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10635 will not appear in the dynamic symbol table.)
10636
10637 Note that the dynamic linker ignores the section
10638 symbol value, so we don't subtract osec->vma
10639 from the emitted reloc addend. */
10dbd1f3 10640 if (sym_sec)
74541ad4 10641 osec = sym_sec->output_section;
10dbd1f3 10642 else
74541ad4
AM		 10643 osec = input_section->output_section;
10644 symbol = elf_section_data (osec)->dynindx;
10645 if (symbol == 0)
10646 {
10647 struct elf_link_hash_table *htab = elf_hash_table (info);
10648
10649 if ((osec->flags & SEC_READONLY) == 0
10650 && htab->data_index_section != NULL)
10651 osec = htab->data_index_section;
10652 else
10653 osec = htab->text_index_section;
10654 symbol = elf_section_data (osec)->dynindx;
10655 }
6366ff1e
MM		 10656 BFD_ASSERT (symbol != 0);
10657 }
a16385dc
MM		 10658 else
10659 /* On SVR4-ish systems, the dynamic loader cannot
10660 relocate the text and data segments independently,
10661 so the symbol does not matter. */
10662 symbol = 0;
34e77a92
RS		 10663 if (dynreloc_st_type == STT_GNU_IFUNC)
10664 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10665 to the .iplt entry. Instead, every non-call reference
10666 must use an R_ARM_IRELATIVE relocation to obtain the
10667 correct run-time address. */
10668 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
e8b09b87
CL		 10669 else if (globals->fdpic_p && !bfd_link_pic(info))
10670 isrofixup = 1;
34e77a92
RS		 10671 else
10672 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10673 if (globals->use_rel)
10674 relocate = TRUE;
10675 else
34e77a92 10676 outrel.r_addend += dynreloc_value;
252b5132 10677 }
f21f3fe0 10678
e8b09b87
CL		 10679 if (isrofixup)
10680 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
10681 else
10682 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10683
f21f3fe0 10684 /* If this reloc is against an external symbol, we do not want to
252b5132 10685 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10686 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10687 if (! relocate)
10688 return bfd_reloc_ok;
9a5aca8c 10689
f21f3fe0 10690 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10691 contents, rel->r_offset,
10692 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10693 }
10694 else switch (r_type)
10695 {
00a97672
RS		 10696 case R_ARM_ABS12:
10697 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10698
dfc5f959 10699 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10700 case R_ARM_CALL:
10701 case R_ARM_JUMP24:
8029a119 10702 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10703 case R_ARM_PLT32:
906e58ca 10704 {
906e58ca
NC		 10705 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10706
dfc5f959 10707 if (r_type == R_ARM_XPC25)
252b5132 10708 {
dfc5f959
NC		 10709 /* Check for Arm calling Arm function. */
10710 /* FIXME: Should we translate the instruction into a BL
10711 instruction instead ? */
35fc36a8 10712 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10713 _bfd_error_handler
90b6238f
AM		 10714 (_("\%pB: warning: %s BLX instruction targets"
10715 " %s function '%s'"),
10716 input_bfd, "ARM",
10717 "ARM", h ? h->root.root.string : "(local)");
dfc5f959 10718 }
155d87d7 10719 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10720 {
10721 /* Check for Arm calling Thumb function. */
35fc36a8 10722 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10723 {
f2a9dd69
DJ		 10724 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10725 output_bfd, input_section,
10726 hit_data, sym_sec, rel->r_offset,
10727 signed_addend, value,
10728 error_message))
10729 return bfd_reloc_ok;
10730 else
10731 return bfd_reloc_dangerous;
dfc5f959 10732 }
252b5132 10733 }
ba96a88f 10734
906e58ca 10735 /* Check if a stub has to be inserted because the
8029a119 10736 destination is too far or we are changing mode. */
155d87d7
CL		 10737 if ( r_type == R_ARM_CALL
10738 || r_type == R_ARM_JUMP24
10739 || r_type == R_ARM_PLT32)
906e58ca 10740 {
fe33d2fa
CL		 10741 enum elf32_arm_stub_type stub_type = arm_stub_none;
10742 struct elf32_arm_link_hash_entry *hash;
10743
10744 hash = (struct elf32_arm_link_hash_entry *) h;
10745 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10746 st_type, &branch_type,
10747 hash, value, sym_sec,
fe33d2fa 10748 input_bfd, sym_name);
5fa9e92f 10749
fe33d2fa 10750 if (stub_type != arm_stub_none)
906e58ca
NC		 10751 {
10752 /* The target is out of reach, so redirect the
10753 branch to the local stub for this function. */
906e58ca
NC		 10754 stub_entry = elf32_arm_get_stub_entry (input_section,
10755 sym_sec, h,
fe33d2fa
CL		 10756 rel, globals,
10757 stub_type);
9cd3e4e5
NC		 10758 {
10759 if (stub_entry != NULL)
10760 value = (stub_entry->stub_offset
10761 + stub_entry->stub_sec->output_offset
10762 + stub_entry->stub_sec->output_section->vma);
10763
10764 if (plt_offset != (bfd_vma) -1)
10765 *unresolved_reloc_p = FALSE;
10766 }
906e58ca 10767 }
fe33d2fa
CL		 10768 else
10769 {
10770 /* If the call goes through a PLT entry, make sure to
10771 check distance to the right destination address. */
34e77a92 10772 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10773 {
10774 value = (splt->output_section->vma
10775 + splt->output_offset
34e77a92 10776 + plt_offset);
fe33d2fa
CL		 10777 *unresolved_reloc_p = FALSE;
10778 /* The PLT entry is in ARM mode, regardless of the
10779 target function. */
35fc36a8 10780 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10781 }
10782 }
906e58ca
NC		 10783 }
10784
dea514f5
PB		 10785 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10786 where:
10787 S is the address of the symbol in the relocation.
10788 P is address of the instruction being relocated.
10789 A is the addend (extracted from the instruction) in bytes.
10790
10791 S is held in 'value'.
10792 P is the base address of the section containing the
10793 instruction plus the offset of the reloc into that
10794 section, ie:
10795 (input_section->output_section->vma +
10796 input_section->output_offset +
10797 rel->r_offset).
10798 A is the addend, converted into bytes, ie:
10799 (signed_addend * 4)
10800
10801 Note: None of these operations have knowledge of the pipeline
10802 size of the processor, thus it is up to the assembler to
10803 encode this information into the addend. */
10804 value -= (input_section->output_section->vma
10805 + input_section->output_offset);
10806 value -= rel->r_offset;
4e7fd91e
PB		 10807 if (globals->use_rel)
10808 value += (signed_addend << howto->size);
10809 else
10810 /* RELA addends do not have to be adjusted by howto->size. */
10811 value += signed_addend;
23080146 10812
dcb5e6e6
NC		 10813 signed_addend = value;
10814 signed_addend >>= howto->rightshift;
9a5aca8c 10815
5ab79981 10816 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10817 the next instruction unless a PLT entry will be created.
77b4f08f 10818 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10819 The jump to the next instruction is optimized as a NOP depending
10820 on the architecture. */
ffcb4889 10821 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10822 && plt_offset == (bfd_vma) -1)
77b4f08f 10823 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10824 {
cd1dac3d
DG		 10825 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10826
10827 if (arch_has_arm_nop (globals))
10828 value |= 0x0320f000;
10829 else
10830 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10831 }
10832 else
59f2c4e7 10833 {
9b485d32 10834 /* Perform a signed range check. */
dcb5e6e6 10835 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10836 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10837 return bfd_reloc_overflow;
9a5aca8c 10838
5ab79981 10839 addend = (value & 2);
39b41c9c 10840
5ab79981
PB		 10841 value = (signed_addend & howto->dst_mask)
10842 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10843
5ab79981
PB		 10844 if (r_type == R_ARM_CALL)
10845 {
155d87d7 10846 /* Set the H bit in the BLX instruction. */
35fc36a8 10847 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10848 {
10849 if (addend)
10850 value |= (1 << 24);
10851 else
10852 value &= ~(bfd_vma)(1 << 24);
10853 }
10854
5ab79981 10855 /* Select the correct instruction (BL or BLX). */
906e58ca 10856 /* Only if we are not handling a BL to a stub. In this
8029a119 10857 case, mode switching is performed by the stub. */
35fc36a8 10858 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10859 value |= (1 << 28);
63e1a0fc 10860 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10861 {
10862 value &= ~(bfd_vma)(1 << 28);
10863 value |= (1 << 24);
10864 }
39b41c9c
PB		 10865 }
10866 }
906e58ca 10867 }
252b5132 10868 break;
f21f3fe0 10869
252b5132
RH		 10870 case R_ARM_ABS32:
10871 value += addend;
35fc36a8 10872 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10873 value |= 1;
10874 break;
f21f3fe0 10875
bb224fc3
MS		 10876 case R_ARM_ABS32_NOI:
10877 value += addend;
10878 break;
10879
252b5132 10880 case R_ARM_REL32:
a8bc6c78 10881 value += addend;
35fc36a8 10882 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10883 value |= 1;
252b5132 10884 value -= (input_section->output_section->vma
62efb346 10885 + input_section->output_offset + rel->r_offset);
252b5132 10886 break;
eb043451 10887
bb224fc3
MS		 10888 case R_ARM_REL32_NOI:
10889 value += addend;
10890 value -= (input_section->output_section->vma
10891 + input_section->output_offset + rel->r_offset);
10892 break;
10893
eb043451
PB		 10894 case R_ARM_PREL31:
10895 value -= (input_section->output_section->vma
10896 + input_section->output_offset + rel->r_offset);
10897 value += signed_addend;
10898 if (! h || h->root.type != bfd_link_hash_undefweak)
10899 {
8029a119 10900 /* Check for overflow. */
eb043451
PB		 10901 if ((value ^ (value >> 1)) & (1 << 30))
10902 return bfd_reloc_overflow;
10903 }
10904 value &= 0x7fffffff;
10905 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10906 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10907 value |= 1;
10908 break;
252b5132 10909 }
f21f3fe0 10910
252b5132
RH		 10911 bfd_put_32 (input_bfd, value, hit_data);
10912 return bfd_reloc_ok;
10913
10914 case R_ARM_ABS8:
fd0fd00c
MJ		 10915 /* PR 16202: Refectch the addend using the correct size. */
10916 if (globals->use_rel)
10917 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10918 value += addend;
4e67d4ca
DG		 10919
10920 /* There is no way to tell whether the user intended to use a signed or
10921 unsigned addend. When checking for overflow we accept either,
10922 as specified by the AAELF. */
10923 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10924 return bfd_reloc_overflow;
10925
10926 bfd_put_8 (input_bfd, value, hit_data);
10927 return bfd_reloc_ok;
10928
10929 case R_ARM_ABS16:
fd0fd00c
MJ		 10930 /* PR 16202: Refectch the addend using the correct size. */
10931 if (globals->use_rel)
10932 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10933 value += addend;
10934
4e67d4ca
DG		 10935 /* See comment for R_ARM_ABS8. */
10936 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10937 return bfd_reloc_overflow;
10938
10939 bfd_put_16 (input_bfd, value, hit_data);
10940 return bfd_reloc_ok;
10941
252b5132 10942 case R_ARM_THM_ABS5:
9b485d32 10943 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10944 if (globals->use_rel)
10945 {
10946 /* Need to refetch addend. */
10947 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10948 /* ??? Need to determine shift amount from operand size. */
10949 addend >>= howto->rightshift;
10950 }
252b5132
RH		 10951 value += addend;
10952
10953 /* ??? Isn't value unsigned? */
10954 if ((long) value > 0x1f || (long) value < -0x10)
10955 return bfd_reloc_overflow;
10956
10957 /* ??? Value needs to be properly shifted into place first. */
10958 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10959 bfd_put_16 (input_bfd, value, hit_data);
10960 return bfd_reloc_ok;
10961
2cab6cc3
MS		 10962 case R_ARM_THM_ALU_PREL_11_0:
10963 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10964 {
10965 bfd_vma insn;
10966 bfd_signed_vma relocation;
10967
10968 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10969 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10970
99059e56
RM		 10971 if (globals->use_rel)
10972 {
10973 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10974 | ((insn & (1 << 26)) >> 15);
10975 if (insn & 0xf00000)
10976 signed_addend = -signed_addend;
10977 }
2cab6cc3
MS		 10978
10979 relocation = value + signed_addend;
79f08007 10980 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10981 + input_section->output_offset
10982 + rel->r_offset);
2cab6cc3 10983
8c65b54f
CS		 10984 /* PR 21523: Use an absolute value. The user of this reloc will
10985 have already selected an ADD or SUB insn appropriately. */
453f8e1e 10986 value = llabs (relocation);
2cab6cc3 10987
99059e56
RM		 10988 if (value >= 0x1000)
10989 return bfd_reloc_overflow;
2cab6cc3 10990
e645cf40
AG		 10991 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10992 if (branch_type == ST_BRANCH_TO_THUMB)
10993 value |= 1;
10994
2cab6cc3 10995 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10996 | ((value & 0x700) << 4)
10997 | ((value & 0x800) << 15);
10998 if (relocation < 0)
10999 insn |= 0xa00000;
2cab6cc3
MS		 11000
11001 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11002 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11003
99059e56 11004 return bfd_reloc_ok;
2cab6cc3
MS		 11005 }
11006
e1ec24c6
NC		 11007 case R_ARM_THM_PC8:
11008 /* PR 10073: This reloc is not generated by the GNU toolchain,
11009 but it is supported for compatibility with third party libraries
11010 generated by other compilers, specifically the ARM/IAR. */
11011 {
11012 bfd_vma insn;
11013 bfd_signed_vma relocation;
11014
11015 insn = bfd_get_16 (input_bfd, hit_data);
11016
99059e56 11017 if (globals->use_rel)
79f08007 11018 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 11019
11020 relocation = value + addend;
79f08007 11021 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11022 + input_section->output_offset
11023 + rel->r_offset);
e1ec24c6 11024
b6518b38 11025 value = relocation;
e1ec24c6
NC		 11026
11027 /* We do not check for overflow of this reloc. Although strictly
11028 speaking this is incorrect, it appears to be necessary in order
11029 to work with IAR generated relocs. Since GCC and GAS do not
11030 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
11031 a problem for them. */
11032 value &= 0x3fc;
11033
11034 insn = (insn & 0xff00) | (value >> 2);
11035
11036 bfd_put_16 (input_bfd, insn, hit_data);
11037
99059e56 11038 return bfd_reloc_ok;
e1ec24c6
NC		 11039 }
11040
2cab6cc3
MS		 11041 case R_ARM_THM_PC12:
11042 /* Corresponds to: ldr.w reg, [pc, #offset]. */
11043 {
11044 bfd_vma insn;
11045 bfd_signed_vma relocation;
11046
11047 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 11048 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 11049
99059e56
RM		 11050 if (globals->use_rel)
11051 {
11052 signed_addend = insn & 0xfff;
11053 if (!(insn & (1 << 23)))
11054 signed_addend = -signed_addend;
11055 }
2cab6cc3
MS		 11056
11057 relocation = value + signed_addend;
79f08007 11058 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11059 + input_section->output_offset
11060 + rel->r_offset);
2cab6cc3 11061
b6518b38 11062 value = relocation;
2cab6cc3 11063
99059e56
RM		 11064 if (value >= 0x1000)
11065 return bfd_reloc_overflow;
2cab6cc3
MS		 11066
11067 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 11068 if (relocation >= 0)
11069 insn |= (1 << 23);
2cab6cc3
MS		 11070
11071 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11072 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11073
99059e56 11074 return bfd_reloc_ok;
2cab6cc3
MS		 11075 }
11076
dfc5f959 11077 case R_ARM_THM_XPC22:
c19d1205 11078 case R_ARM_THM_CALL:
bd97cb95 11079 case R_ARM_THM_JUMP24:
dfc5f959 11080 /* Thumb BL (branch long instruction). */
252b5132 11081 {
b34976b6 11082 bfd_vma relocation;
99059e56 11083 bfd_vma reloc_sign;
b34976b6
AM		 11084 bfd_boolean overflow = FALSE;
11085 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11086 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 11087 bfd_signed_vma reloc_signed_max;
11088 bfd_signed_vma reloc_signed_min;
b34976b6 11089 bfd_vma check;
252b5132 11090 bfd_signed_vma signed_check;
e95de063 11091 int bitsize;
cd1dac3d 11092 const int thumb2 = using_thumb2 (globals);
5e866f5a 11093 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 11094
5ab79981 11095 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 11096 the next instruction unless a PLT entry will be created.
11097 The jump to the next instruction is optimized as a NOP.W for
11098 Thumb-2 enabled architectures. */
19540007 11099 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 11100 && plt_offset == (bfd_vma) -1)
5ab79981 11101 {
60a019a0 11102 if (thumb2)
cd1dac3d
DG		 11103 {
11104 bfd_put_16 (input_bfd, 0xf3af, hit_data);
11105 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
11106 }
11107 else
11108 {
11109 bfd_put_16 (input_bfd, 0xe000, hit_data);
11110 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
11111 }
5ab79981
PB		 11112 return bfd_reloc_ok;
11113 }
11114
e95de063 11115 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 11116 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 11117 if (globals->use_rel)
11118 {
99059e56
RM		 11119 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
11120 bfd_vma upper = upper_insn & 0x3ff;
11121 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 11122 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
11123 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 11124 bfd_vma i1 = j1 ^ s ? 0 : 1;
11125 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 11126
99059e56
RM		 11127 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
11128 /* Sign extend. */
11129 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 11130
4e7fd91e
PB		 11131 signed_addend = addend;
11132 }
cb1afa5c 11133
dfc5f959
NC		 11134 if (r_type == R_ARM_THM_XPC22)
11135 {
11136 /* Check for Thumb to Thumb call. */
11137 /* FIXME: Should we translate the instruction into a BL
11138 instruction instead ? */
35fc36a8 11139 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 11140 _bfd_error_handler
90b6238f
AM		 11141 (_("%pB: warning: %s BLX instruction targets"
11142 " %s function '%s'"),
11143 input_bfd, "Thumb",
11144 "Thumb", h ? h->root.root.string : "(local)");
dfc5f959
NC		 11145 }
11146 else
252b5132 11147 {
dfc5f959
NC		 11148 /* If it is not a call to Thumb, assume call to Arm.
11149 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 11150 function call at all, but rather a long jump. Calls through
11151 the PLT do not require stubs. */
34e77a92 11152 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 11153 {
bd97cb95 11154 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11155 {
11156 /* Convert BL to BLX. */
11157 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11158 }
155d87d7
CL		 11159 else if (( r_type != R_ARM_THM_CALL)
11160 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 11161 {
11162 if (elf32_thumb_to_arm_stub
11163 (info, sym_name, input_bfd, output_bfd, input_section,
11164 hit_data, sym_sec, rel->r_offset, signed_addend, value,
11165 error_message))
11166 return bfd_reloc_ok;
11167 else
11168 return bfd_reloc_dangerous;
11169 }
da5938a2 11170 }
35fc36a8
RS		 11171 else if (branch_type == ST_BRANCH_TO_THUMB
11172 && globals->use_blx
bd97cb95 11173 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11174 {
11175 /* Make sure this is a BL. */
11176 lower_insn |= 0x1800;
11177 }
252b5132 11178 }
f21f3fe0 11179
fe33d2fa 11180 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 11181 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 11182 {
11183 /* Check if a stub has to be inserted because the destination
8029a119 11184 is too far. */
fe33d2fa
CL		 11185 struct elf32_arm_stub_hash_entry *stub_entry;
11186 struct elf32_arm_link_hash_entry *hash;
11187
11188 hash = (struct elf32_arm_link_hash_entry *) h;
11189
11190 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 11191 st_type, &branch_type,
11192 hash, value, sym_sec,
fe33d2fa
CL		 11193 input_bfd, sym_name);
11194
11195 if (stub_type != arm_stub_none)
906e58ca
NC		 11196 {
11197 /* The target is out of reach or we are changing modes, so
11198 redirect the branch to the local stub for this
11199 function. */
11200 stub_entry = elf32_arm_get_stub_entry (input_section,
11201 sym_sec, h,
fe33d2fa
CL		 11202 rel, globals,
11203 stub_type);
906e58ca 11204 if (stub_entry != NULL)
9cd3e4e5
NC		 11205 {
11206 value = (stub_entry->stub_offset
11207 + stub_entry->stub_sec->output_offset
11208 + stub_entry->stub_sec->output_section->vma);
11209
11210 if (plt_offset != (bfd_vma) -1)
11211 *unresolved_reloc_p = FALSE;
11212 }
906e58ca 11213
f4ac8484 11214 /* If this call becomes a call to Arm, force BLX. */
155d87d7 11215 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 11216 {
11217 if ((stub_entry
11218 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 11219 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 11220 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11221 }
906e58ca
NC		 11222 }
11223 }
11224
fe33d2fa 11225 /* Handle calls via the PLT. */
34e77a92 11226 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 11227 {
11228 value = (splt->output_section->vma
11229 + splt->output_offset
34e77a92 11230 + plt_offset);
fe33d2fa 11231
eed94f8f
NC		 11232 if (globals->use_blx
11233 && r_type == R_ARM_THM_CALL
11234 && ! using_thumb_only (globals))
fe33d2fa
CL		 11235 {
11236 /* If the Thumb BLX instruction is available, convert
11237 the BL to a BLX instruction to call the ARM-mode
11238 PLT entry. */
11239 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 11240 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 11241 }
11242 else
11243 {
eed94f8f
NC		 11244 if (! using_thumb_only (globals))
11245 /* Target the Thumb stub before the ARM PLT entry. */
11246 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 11247 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 11248 }
11249 *unresolved_reloc_p = FALSE;
11250 }
11251
ba96a88f 11252 relocation = value + signed_addend;
f21f3fe0 11253
252b5132 11254 relocation -= (input_section->output_section->vma
ba96a88f
NC		 11255 + input_section->output_offset
11256 + rel->r_offset);
9a5aca8c 11257
252b5132
RH		 11258 check = relocation >> howto->rightshift;
11259
11260 /* If this is a signed value, the rightshift just dropped
11261 leading 1 bits (assuming twos complement). */
11262 if ((bfd_signed_vma) relocation >= 0)
11263 signed_check = check;
11264 else
11265 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
11266
e95de063
MS		 11267 /* Calculate the permissable maximum and minimum values for
11268 this relocation according to whether we're relocating for
11269 Thumb-2 or not. */
11270 bitsize = howto->bitsize;
5e866f5a 11271 if (!thumb2_bl)
e95de063 11272 bitsize -= 2;
f6ebfac0 11273 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 11274 reloc_signed_min = ~reloc_signed_max;
11275
252b5132 11276 /* Assumes two's complement. */
ba96a88f 11277 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 11278 overflow = TRUE;
252b5132 11279
bd97cb95 11280 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 11281 /* For a BLX instruction, make sure that the relocation is rounded up
11282 to a word boundary. This follows the semantics of the instruction
11283 which specifies that bit 1 of the target address will come from bit
11284 1 of the base address. */
11285 relocation = (relocation + 2) & ~ 3;
cb1afa5c 11286
e95de063
MS		 11287 /* Put RELOCATION back into the insn. Assumes two's complement.
11288 We use the Thumb-2 encoding, which is safe even if dealing with
11289 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 11290 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 11291 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 11292 | ((relocation >> 12) & 0x3ff)
11293 | (reloc_sign << 10);
906e58ca 11294 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 11295 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
11296 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
11297 | ((relocation >> 1) & 0x7ff);
c62e1cc3 11298
252b5132
RH		 11299 /* Put the relocated value back in the object file: */
11300 bfd_put_16 (input_bfd, upper_insn, hit_data);
11301 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11302
11303 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11304 }
11305 break;
11306
c19d1205
ZW		 11307 case R_ARM_THM_JUMP19:
11308 /* Thumb32 conditional branch instruction. */
11309 {
11310 bfd_vma relocation;
11311 bfd_boolean overflow = FALSE;
11312 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11313 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 11314 bfd_signed_vma reloc_signed_max = 0xffffe;
11315 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 11316 bfd_signed_vma signed_check;
07d6d2b8 11317 enum elf32_arm_stub_type stub_type = arm_stub_none;
c5423981
TG		 11318 struct elf32_arm_stub_hash_entry *stub_entry;
11319 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 11320
11321 /* Need to refetch the addend, reconstruct the top three bits,
11322 and squish the two 11 bit pieces together. */
11323 if (globals->use_rel)
11324 {
11325 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 11326 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 11327 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
11328 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
11329 bfd_vma lower = (lower_insn & 0x07ff);
11330
a00a1f35
MS		 11331 upper |= J1 << 6;
11332 upper |= J2 << 7;
11333 upper |= (!S) << 8;
c19d1205
ZW		 11334 upper -= 0x0100; /* Sign extend. */
11335
11336 addend = (upper << 12) | (lower << 1);
11337 signed_addend = addend;
11338 }
11339
bd97cb95 11340 /* Handle calls via the PLT. */
34e77a92 11341 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 11342 {
11343 value = (splt->output_section->vma
11344 + splt->output_offset
34e77a92 11345 + plt_offset);
bd97cb95
DJ		 11346 /* Target the Thumb stub before the ARM PLT entry. */
11347 value -= PLT_THUMB_STUB_SIZE;
11348 *unresolved_reloc_p = FALSE;
11349 }
11350
c5423981
TG		 11351 hash = (struct elf32_arm_link_hash_entry *)h;
11352
11353 stub_type = arm_type_of_stub (info, input_section, rel,
07d6d2b8
AM		 11354 st_type, &branch_type,
11355 hash, value, sym_sec,
11356 input_bfd, sym_name);
c5423981
TG		 11357 if (stub_type != arm_stub_none)
11358 {
11359 stub_entry = elf32_arm_get_stub_entry (input_section,
07d6d2b8
AM		 11360 sym_sec, h,
11361 rel, globals,
11362 stub_type);
c5423981
TG		 11363 if (stub_entry != NULL)
11364 {
07d6d2b8
AM		 11365 value = (stub_entry->stub_offset
11366 + stub_entry->stub_sec->output_offset
11367 + stub_entry->stub_sec->output_section->vma);
c5423981
TG		 11368 }
11369 }
c19d1205 11370
99059e56 11371 relocation = value + signed_addend;
c19d1205
ZW		 11372 relocation -= (input_section->output_section->vma
11373 + input_section->output_offset
11374 + rel->r_offset);
a00a1f35 11375 signed_check = (bfd_signed_vma) relocation;
c19d1205 11376
c19d1205
ZW		 11377 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11378 overflow = TRUE;
11379
11380 /* Put RELOCATION back into the insn. */
11381 {
11382 bfd_vma S = (relocation & 0x00100000) >> 20;
11383 bfd_vma J2 = (relocation & 0x00080000) >> 19;
11384 bfd_vma J1 = (relocation & 0x00040000) >> 18;
11385 bfd_vma hi = (relocation & 0x0003f000) >> 12;
11386 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
11387
a00a1f35 11388 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 11389 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
11390 }
11391
11392 /* Put the relocated value back in the object file: */
11393 bfd_put_16 (input_bfd, upper_insn, hit_data);
11394 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11395
11396 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11397 }
11398
11399 case R_ARM_THM_JUMP11:
11400 case R_ARM_THM_JUMP8:
11401 case R_ARM_THM_JUMP6:
51c5503b
NC		 11402 /* Thumb B (branch) instruction). */
11403 {
6cf9e9fe 11404 bfd_signed_vma relocation;
51c5503b
NC		 11405 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
11406 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 11407 bfd_signed_vma signed_check;
11408
c19d1205
ZW		 11409 /* CZB cannot jump backward. */
11410 if (r_type == R_ARM_THM_JUMP6)
11411 reloc_signed_min = 0;
11412
4e7fd91e 11413 if (globals->use_rel)
6cf9e9fe 11414 {
4e7fd91e
PB		 11415 /* Need to refetch addend. */
11416 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
11417 if (addend & ((howto->src_mask + 1) >> 1))
11418 {
11419 signed_addend = -1;
11420 signed_addend &= ~ howto->src_mask;
11421 signed_addend |= addend;
11422 }
11423 else
11424 signed_addend = addend;
11425 /* The value in the insn has been right shifted. We need to
11426 undo this, so that we can perform the address calculation
11427 in terms of bytes. */
11428 signed_addend <<= howto->rightshift;
6cf9e9fe 11429 }
6cf9e9fe 11430 relocation = value + signed_addend;
51c5503b
NC		 11431
11432 relocation -= (input_section->output_section->vma
11433 + input_section->output_offset
11434 + rel->r_offset);
11435
6cf9e9fe
NC		 11436 relocation >>= howto->rightshift;
11437 signed_check = relocation;
c19d1205
ZW		 11438
11439 if (r_type == R_ARM_THM_JUMP6)
11440 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
11441 else
11442 relocation &= howto->dst_mask;
51c5503b 11443 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 11444
51c5503b
NC		 11445 bfd_put_16 (input_bfd, relocation, hit_data);
11446
11447 /* Assumes two's complement. */
11448 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11449 return bfd_reloc_overflow;
11450
11451 return bfd_reloc_ok;
11452 }
cedb70c5 11453
8375c36b
PB		 11454 case R_ARM_ALU_PCREL7_0:
11455 case R_ARM_ALU_PCREL15_8:
11456 case R_ARM_ALU_PCREL23_15:
11457 {
11458 bfd_vma insn;
11459 bfd_vma relocation;
11460
11461 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 11462 if (globals->use_rel)
11463 {
11464 /* Extract the addend. */
11465 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
11466 signed_addend = addend;
11467 }
8375c36b
PB		 11468 relocation = value + signed_addend;
11469
11470 relocation -= (input_section->output_section->vma
11471 + input_section->output_offset
11472 + rel->r_offset);
11473 insn = (insn & ~0xfff)
11474 | ((howto->bitpos << 7) & 0xf00)
11475 | ((relocation >> howto->bitpos) & 0xff);
11476 bfd_put_32 (input_bfd, value, hit_data);
11477 }
11478 return bfd_reloc_ok;
11479
252b5132
RH		 11480 case R_ARM_GNU_VTINHERIT:
11481 case R_ARM_GNU_VTENTRY:
11482 return bfd_reloc_ok;
11483
c19d1205 11484 case R_ARM_GOTOFF32:
252b5132 11485 /* Relocation is relative to the start of the
99059e56 11486 global offset table. */
252b5132
RH		 11487
11488 BFD_ASSERT (sgot != NULL);
11489 if (sgot == NULL)
99059e56 11490 return bfd_reloc_notsupported;
9a5aca8c 11491
cedb70c5 11492 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11493 address by one, so that attempts to call the function pointer will
11494 correctly interpret it as Thumb code. */
35fc36a8 11495 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11496 value += 1;
11497
252b5132 11498 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11499 calculation. We always want the start of .got. If we
11500 define _GLOBAL_OFFSET_TABLE in a different way, as is
11501 permitted by the ABI, we might have to change this
11502 calculation. */
252b5132 11503 value -= sgot->output_section->vma;
f21f3fe0 11504 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11505 contents, rel->r_offset, value,
00a97672 11506 rel->r_addend);
252b5132
RH		 11507
11508 case R_ARM_GOTPC:
a7c10850 11509 /* Use global offset table as symbol value. */
252b5132 11510 BFD_ASSERT (sgot != NULL);
f21f3fe0 11511
252b5132 11512 if (sgot == NULL)
99059e56 11513 return bfd_reloc_notsupported;
252b5132 11514
0945cdfd 11515 *unresolved_reloc_p = FALSE;
252b5132 11516 value = sgot->output_section->vma;
f21f3fe0 11517 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11518 contents, rel->r_offset, value,
00a97672 11519 rel->r_addend);
f21f3fe0 11520
252b5132 11521 case R_ARM_GOT32:
eb043451 11522 case R_ARM_GOT_PREL:
252b5132 11523 /* Relocation is to the entry for this symbol in the
99059e56 11524 global offset table. */
252b5132
RH		 11525 if (sgot == NULL)
11526 return bfd_reloc_notsupported;
f21f3fe0 11527
34e77a92
RS		 11528 if (dynreloc_st_type == STT_GNU_IFUNC
11529 && plt_offset != (bfd_vma) -1
11530 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11531 {
11532 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11533 symbol, and the relocation resolves directly to the runtime
11534 target rather than to the .iplt entry. This means that any
11535 .got entry would be the same value as the .igot.plt entry,
11536 so there's no point creating both. */
11537 sgot = globals->root.igotplt;
11538 value = sgot->output_offset + gotplt_offset;
11539 }
11540 else if (h != NULL)
252b5132
RH		 11541 {
11542 bfd_vma off;
f21f3fe0 11543
252b5132
RH		 11544 off = h->got.offset;
11545 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11546 if ((off & 1) != 0)
252b5132 11547 {
b436d854
RS		 11548 /* We have already processsed one GOT relocation against
11549 this symbol. */
11550 off &= ~1;
11551 if (globals->root.dynamic_sections_created
11552 && !SYMBOL_REFERENCES_LOCAL (info, h))
11553 *unresolved_reloc_p = FALSE;
11554 }
11555 else
11556 {
11557 Elf_Internal_Rela outrel;
e8b09b87 11558 int isrofixup = 0;
b436d854 11559
e8b09b87
CL		 11560 if (((h->dynindx != -1) || globals->fdpic_p)
11561 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11562 {
11563 /* If the symbol doesn't resolve locally in a static
11564 object, we have an undefined reference. If the
11565 symbol doesn't resolve locally in a dynamic object,
11566 it should be resolved by the dynamic linker. */
11567 if (globals->root.dynamic_sections_created)
11568 {
11569 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11570 *unresolved_reloc_p = FALSE;
11571 }
11572 else
11573 outrel.r_info = 0;
11574 outrel.r_addend = 0;
11575 }
252b5132
RH		 11576 else
11577 {
34e77a92 11578 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11579 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c
AO		 11580 else if (bfd_link_pic (info)
11581 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11582 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 11583 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11584 else
2376f038
EB		 11585 {
11586 outrel.r_info = 0;
11587 if (globals->fdpic_p)
11588 isrofixup = 1;
11589 }
34e77a92 11590 outrel.r_addend = dynreloc_value;
b436d854 11591 }
ee29b9fb 11592
b436d854
RS		 11593 /* The GOT entry is initialized to zero by default.
11594 See if we should install a different value. */
11595 if (outrel.r_addend != 0
2376f038 11596 && (globals->use_rel || outrel.r_info == 0))
b436d854
RS		 11597 {
11598 bfd_put_32 (output_bfd, outrel.r_addend,
11599 sgot->contents + off);
11600 outrel.r_addend = 0;
252b5132 11601 }
f21f3fe0 11602
2376f038
EB		 11603 if (isrofixup)
11604 arm_elf_add_rofixup (output_bfd,
11605 elf32_arm_hash_table(info)->srofixup,
11606 sgot->output_section->vma
11607 + sgot->output_offset + off);
11608
11609 else if (outrel.r_info != 0)
b436d854
RS		 11610 {
11611 outrel.r_offset = (sgot->output_section->vma
11612 + sgot->output_offset
11613 + off);
11614 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11615 }
2376f038 11616
b436d854
RS		 11617 h->got.offset |= 1;
11618 }
252b5132
RH		 11619 value = sgot->output_offset + off;
11620 }
11621 else
11622 {
11623 bfd_vma off;
f21f3fe0 11624
5025eb7c
AO		 11625 BFD_ASSERT (local_got_offsets != NULL
11626 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11627
252b5132 11628 off = local_got_offsets[r_symndx];
f21f3fe0 11629
252b5132
RH		 11630 /* The offset must always be a multiple of 4. We use the
11631 least significant bit to record whether we have already
9b485d32 11632 generated the necessary reloc. */
252b5132
RH		 11633 if ((off & 1) != 0)
11634 off &= ~1;
11635 else
11636 {
2376f038
EB		 11637 Elf_Internal_Rela outrel;
11638 int isrofixup = 0;
f21f3fe0 11639
2376f038
EB		 11640 if (dynreloc_st_type == STT_GNU_IFUNC)
11641 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
11642 else if (bfd_link_pic (info))
11643 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11644 else
252b5132 11645 {
2376f038
EB		 11646 outrel.r_info = 0;
11647 if (globals->fdpic_p)
11648 isrofixup = 1;
11649 }
11650
11651 /* The GOT entry is initialized to zero by default.
11652 See if we should install a different value. */
11653 if (globals->use_rel || outrel.r_info == 0)
11654 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
11655
11656 if (isrofixup)
11657 arm_elf_add_rofixup (output_bfd,
11658 globals->srofixup,
11659 sgot->output_section->vma
11660 + sgot->output_offset + off);
f21f3fe0 11661
2376f038
EB		 11662 else if (outrel.r_info != 0)
11663 {
34e77a92 11664 outrel.r_addend = addend + dynreloc_value;
252b5132 11665 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11666 + sgot->output_offset
252b5132 11667 + off);
47beaa6a 11668 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11669 }
f21f3fe0 11670
252b5132
RH		 11671 local_got_offsets[r_symndx] |= 1;
11672 }
f21f3fe0 11673
252b5132
RH		 11674 value = sgot->output_offset + off;
11675 }
eb043451
PB		 11676 if (r_type != R_ARM_GOT32)
11677 value += sgot->output_section->vma;
9a5aca8c 11678
f21f3fe0 11679 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11680 contents, rel->r_offset, value,
00a97672 11681 rel->r_addend);
f21f3fe0 11682
ba93b8ac
DJ		 11683 case R_ARM_TLS_LDO32:
11684 value = value - dtpoff_base (info);
11685
11686 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11687 contents, rel->r_offset, value,
11688 rel->r_addend);
ba93b8ac
DJ		 11689
11690 case R_ARM_TLS_LDM32:
5c5a4843 11691 case R_ARM_TLS_LDM32_FDPIC:
ba93b8ac
DJ		 11692 {
11693 bfd_vma off;
11694
362d30a1 11695 if (sgot == NULL)
ba93b8ac
DJ		 11696 abort ();
11697
11698 off = globals->tls_ldm_got.offset;
11699
11700 if ((off & 1) != 0)
11701 off &= ~1;
11702 else
11703 {
11704 /* If we don't know the module number, create a relocation
11705 for it. */
9cb09e33 11706 if (bfd_link_dll (info))
ba93b8ac
DJ		 11707 {
11708 Elf_Internal_Rela outrel;
ba93b8ac 11709
362d30a1 11710 if (srelgot == NULL)
ba93b8ac
DJ		 11711 abort ();
11712
00a97672 11713 outrel.r_addend = 0;
362d30a1
RS		 11714 outrel.r_offset = (sgot->output_section->vma
11715 + sgot->output_offset + off);
ba93b8ac
DJ		 11716 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11717
00a97672
RS		 11718 if (globals->use_rel)
11719 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11720 sgot->contents + off);
ba93b8ac 11721
47beaa6a 11722 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11723 }
11724 else
362d30a1 11725 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11726
11727 globals->tls_ldm_got.offset |= 1;
11728 }
11729
5c5a4843 11730 if (r_type == R_ARM_TLS_LDM32_FDPIC)
e8b09b87
CL		 11731 {
11732 bfd_put_32(output_bfd,
11733 globals->root.sgot->output_offset + off,
11734 contents + rel->r_offset);
11735
11736 return bfd_reloc_ok;
11737 }
11738 else
11739 {
11740 value = sgot->output_section->vma + sgot->output_offset + off
11741 - (input_section->output_section->vma
11742 + input_section->output_offset + rel->r_offset);
ba93b8ac 11743
e8b09b87
CL		 11744 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11745 contents, rel->r_offset, value,
11746 rel->r_addend);
11747 }
ba93b8ac
DJ		 11748 }
11749
0855e32b
NS		 11750 case R_ARM_TLS_CALL:
11751 case R_ARM_THM_TLS_CALL:
ba93b8ac 11752 case R_ARM_TLS_GD32:
5c5a4843 11753 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 11754 case R_ARM_TLS_IE32:
5c5a4843 11755 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 11756 case R_ARM_TLS_GOTDESC:
11757 case R_ARM_TLS_DESCSEQ:
11758 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11759 {
0855e32b
NS		 11760 bfd_vma off, offplt;
11761 int indx = 0;
ba93b8ac
DJ		 11762 char tls_type;
11763
0855e32b 11764 BFD_ASSERT (sgot != NULL);
ba93b8ac 11765
ba93b8ac
DJ		 11766 if (h != NULL)
11767 {
11768 bfd_boolean dyn;
11769 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11770 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11771 bfd_link_pic (info),
11772 h)
11773 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11774 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11775 {
11776 *unresolved_reloc_p = FALSE;
11777 indx = h->dynindx;
11778 }
11779 off = h->got.offset;
0855e32b 11780 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11781 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11782 }
11783 else
11784 {
0855e32b 11785 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11786 off = local_got_offsets[r_symndx];
0855e32b 11787 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11788 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11789 }
11790
0855e32b 11791 /* Linker relaxations happens from one of the
b38cadfb 11792 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11793 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11794 tls_type = GOT_TLS_IE;
0855e32b
NS		 11795
11796 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11797
11798 if ((off & 1) != 0)
11799 off &= ~1;
11800 else
11801 {
11802 bfd_boolean need_relocs = FALSE;
11803 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11804 int cur_off = off;
11805
11806 /* The GOT entries have not been initialized yet. Do it
11807 now, and emit any relocations. If both an IE GOT and a
11808 GD GOT are necessary, we emit the GD first. */
11809
9cb09e33 11810 if ((bfd_link_dll (info) || indx != 0)
ba93b8ac 11811 && (h == NULL
95b03e4a
L		 11812 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11813 && !resolved_to_zero)
ba93b8ac
DJ		 11814 || h->root.type != bfd_link_hash_undefweak))
11815 {
11816 need_relocs = TRUE;
0855e32b 11817 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11818 }
11819
0855e32b
NS		 11820 if (tls_type & GOT_TLS_GDESC)
11821 {
47beaa6a
RS		 11822 bfd_byte *loc;
11823
0855e32b
NS		 11824 /* We should have relaxed, unless this is an undefined
11825 weak symbol. */
11826 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
9cb09e33 11827 || bfd_link_dll (info));
0855e32b 11828 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11829 <= globals->root.sgotplt->size);
0855e32b
NS		 11830
11831 outrel.r_addend = 0;
11832 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11833 + globals->root.sgotplt->output_offset
11834 + offplt
11835 + globals->sgotplt_jump_table_size);
b38cadfb 11836
0855e32b
NS		 11837 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11838 sreloc = globals->root.srelplt;
11839 loc = sreloc->contents;
11840 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11841 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11842 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11843
11844 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11845
11846 /* For globals, the first word in the relocation gets
11847 the relocation index and the top bit set, or zero,
11848 if we're binding now. For locals, it gets the
11849 symbol's offset in the tls section. */
99059e56 11850 bfd_put_32 (output_bfd,
0855e32b
NS		 11851 !h ? value - elf_hash_table (info)->tls_sec->vma
11852 : info->flags & DF_BIND_NOW ? 0
11853 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11854 globals->root.sgotplt->contents + offplt
11855 + globals->sgotplt_jump_table_size);
11856
0855e32b 11857 /* Second word in the relocation is always zero. */
99059e56 11858 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11859 globals->root.sgotplt->contents + offplt
11860 + globals->sgotplt_jump_table_size + 4);
0855e32b 11861 }
ba93b8ac
DJ		 11862 if (tls_type & GOT_TLS_GD)
11863 {
11864 if (need_relocs)
11865 {
00a97672 11866 outrel.r_addend = 0;
362d30a1
RS		 11867 outrel.r_offset = (sgot->output_section->vma
11868 + sgot->output_offset
00a97672 11869 + cur_off);
ba93b8ac 11870 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11871
00a97672
RS		 11872 if (globals->use_rel)
11873 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11874 sgot->contents + cur_off);
00a97672 11875
47beaa6a 11876 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11877
11878 if (indx == 0)
11879 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11880 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11881 else
11882 {
00a97672 11883 outrel.r_addend = 0;
ba93b8ac
DJ		 11884 outrel.r_info = ELF32_R_INFO (indx,
11885 R_ARM_TLS_DTPOFF32);
11886 outrel.r_offset += 4;
00a97672
RS		 11887
11888 if (globals->use_rel)
11889 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11890 sgot->contents + cur_off + 4);
00a97672 11891
47beaa6a
RS		 11892 elf32_arm_add_dynreloc (output_bfd, info,
11893 srelgot, &outrel);
ba93b8ac
DJ		 11894 }
11895 }
11896 else
11897 {
11898 /* If we are not emitting relocations for a
11899 general dynamic reference, then we must be in a
11900 static link or an executable link with the
11901 symbol binding locally. Mark it as belonging
11902 to module 1, the executable. */
11903 bfd_put_32 (output_bfd, 1,
362d30a1 11904 sgot->contents + cur_off);
ba93b8ac 11905 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11906 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11907 }
11908
11909 cur_off += 8;
11910 }
11911
11912 if (tls_type & GOT_TLS_IE)
11913 {
11914 if (need_relocs)
11915 {
00a97672
RS		 11916 if (indx == 0)
11917 outrel.r_addend = value - dtpoff_base (info);
11918 else
11919 outrel.r_addend = 0;
362d30a1
RS		 11920 outrel.r_offset = (sgot->output_section->vma
11921 + sgot->output_offset
ba93b8ac
DJ		 11922 + cur_off);
11923 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11924
00a97672
RS		 11925 if (globals->use_rel)
11926 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11927 sgot->contents + cur_off);
ba93b8ac 11928
47beaa6a 11929 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11930 }
11931 else
11932 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11933 sgot->contents + cur_off);
ba93b8ac
DJ		 11934 cur_off += 4;
11935 }
11936
11937 if (h != NULL)
11938 h->got.offset |= 1;
11939 else
11940 local_got_offsets[r_symndx] |= 1;
11941 }
11942
5c5a4843 11943 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32 && r_type != R_ARM_TLS_GD32_FDPIC)
ba93b8ac 11944 off += 8;
0855e32b
NS		 11945 else if (tls_type & GOT_TLS_GDESC)
11946 off = offplt;
11947
11948 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11949 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11950 {
11951 bfd_signed_vma offset;
12352d3f
PB		 11952 /* TLS stubs are arm mode. The original symbol is a
11953 data object, so branch_type is bogus. */
11954 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11955 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11956 = arm_type_of_stub (info, input_section, rel,
11957 st_type, &branch_type,
0855e32b
NS		 11958 (struct elf32_arm_link_hash_entry *)h,
11959 globals->tls_trampoline, globals->root.splt,
11960 input_bfd, sym_name);
11961
11962 if (stub_type != arm_stub_none)
11963 {
11964 struct elf32_arm_stub_hash_entry *stub_entry
11965 = elf32_arm_get_stub_entry
11966 (input_section, globals->root.splt, 0, rel,
11967 globals, stub_type);
11968 offset = (stub_entry->stub_offset
11969 + stub_entry->stub_sec->output_offset
11970 + stub_entry->stub_sec->output_section->vma);
11971 }
11972 else
11973 offset = (globals->root.splt->output_section->vma
11974 + globals->root.splt->output_offset
11975 + globals->tls_trampoline);
11976
11977 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11978 {
11979 unsigned long inst;
b38cadfb
NC		 11980
11981 offset -= (input_section->output_section->vma
11982 + input_section->output_offset
11983 + rel->r_offset + 8);
0855e32b
NS		 11984
11985 inst = offset >> 2;
11986 inst &= 0x00ffffff;
11987 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11988 }
11989 else
11990 {
11991 /* Thumb blx encodes the offset in a complicated
11992 fashion. */
11993 unsigned upper_insn, lower_insn;
11994 unsigned neg;
11995
b38cadfb
NC		 11996 offset -= (input_section->output_section->vma
11997 + input_section->output_offset
0855e32b 11998 + rel->r_offset + 4);
b38cadfb 11999
12352d3f
PB		 12000 if (stub_type != arm_stub_none
12001 && arm_stub_is_thumb (stub_type))
12002 {
12003 lower_insn = 0xd000;
12004 }
12005 else
12006 {
12007 lower_insn = 0xc000;
6a631e86 12008 /* Round up the offset to a word boundary. */
12352d3f
PB		 12009 offset = (offset + 2) & ~2;
12010 }
12011
0855e32b
NS		 12012 neg = offset < 0;
12013 upper_insn = (0xf000
12014 | ((offset >> 12) & 0x3ff)
12015 | (neg << 10));
12352d3f 12016 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 12017 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 12018 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 12019 bfd_put_16 (input_bfd, upper_insn, hit_data);
12020 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12021 return bfd_reloc_ok;
12022 }
12023 }
12024 /* These relocations needs special care, as besides the fact
12025 they point somewhere in .gotplt, the addend must be
12026 adjusted accordingly depending on the type of instruction
6a631e86 12027 we refer to. */
0855e32b
NS		 12028 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
12029 {
12030 unsigned long data, insn;
12031 unsigned thumb;
b38cadfb 12032
b627f562 12033 data = bfd_get_signed_32 (input_bfd, hit_data);
0855e32b 12034 thumb = data & 1;
b627f562 12035 data &= ~1ul;
b38cadfb 12036
0855e32b
NS		 12037 if (thumb)
12038 {
12039 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
12040 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
12041 insn = (insn << 16)
12042 | bfd_get_16 (input_bfd,
12043 contents + rel->r_offset - data + 2);
12044 if ((insn & 0xf800c000) == 0xf000c000)
12045 /* bl/blx */
12046 value = -6;
12047 else if ((insn & 0xffffff00) == 0x4400)
12048 /* add */
12049 value = -5;
12050 else
12051 {
4eca0228 12052 _bfd_error_handler
695344c0 12053 /* xgettext:c-format */
2dcf00ce 12054 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12055 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12056 "referenced by TLS_GOTDESC"),
12057 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12058 "Thumb", insn);
0855e32b
NS		 12059 return bfd_reloc_notsupported;
12060 }
12061 }
12062 else
12063 {
12064 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
12065
12066 switch (insn >> 24)
12067 {
12068 case 0xeb: /* bl */
12069 case 0xfa: /* blx */
12070 value = -4;
12071 break;
12072
12073 case 0xe0: /* add */
12074 value = -8;
12075 break;
b38cadfb 12076
0855e32b 12077 default:
4eca0228 12078 _bfd_error_handler
695344c0 12079 /* xgettext:c-format */
2dcf00ce 12080 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12081 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12082 "referenced by TLS_GOTDESC"),
12083 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12084 "ARM", insn);
0855e32b
NS		 12085 return bfd_reloc_notsupported;
12086 }
12087 }
b38cadfb 12088
0855e32b
NS		 12089 value += ((globals->root.sgotplt->output_section->vma
12090 + globals->root.sgotplt->output_offset + off)
12091 - (input_section->output_section->vma
12092 + input_section->output_offset
12093 + rel->r_offset)
12094 + globals->sgotplt_jump_table_size);
12095 }
12096 else
12097 value = ((globals->root.sgot->output_section->vma
12098 + globals->root.sgot->output_offset + off)
12099 - (input_section->output_section->vma
12100 + input_section->output_offset + rel->r_offset));
ba93b8ac 12101
5c5a4843
CL		 12102 if (globals->fdpic_p && (r_type == R_ARM_TLS_GD32_FDPIC ||
12103 r_type == R_ARM_TLS_IE32_FDPIC))
e8b09b87
CL		 12104 {
12105 /* For FDPIC relocations, resolve to the offset of the GOT
12106 entry from the start of GOT. */
12107 bfd_put_32(output_bfd,
12108 globals->root.sgot->output_offset + off,
12109 contents + rel->r_offset);
12110
12111 return bfd_reloc_ok;
12112 }
12113 else
12114 {
12115 return _bfd_final_link_relocate (howto, input_bfd, input_section,
12116 contents, rel->r_offset, value,
12117 rel->r_addend);
12118 }
ba93b8ac
DJ		 12119 }
12120
12121 case R_ARM_TLS_LE32:
3cbc1e5e 12122 if (bfd_link_dll (info))
ba93b8ac 12123 {
4eca0228 12124 _bfd_error_handler
695344c0 12125 /* xgettext:c-format */
2dcf00ce
AM		 12126 (_("%pB(%pA+%#" PRIx64 "): %s relocation not permitted "
12127 "in shared object"),
12128 input_bfd, input_section, (uint64_t) rel->r_offset, howto->name);
46691134 12129 return bfd_reloc_notsupported;
ba93b8ac
DJ		 12130 }
12131 else
12132 value = tpoff (info, value);
906e58ca 12133
ba93b8ac 12134 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 12135 contents, rel->r_offset, value,
12136 rel->r_addend);
ba93b8ac 12137
319850b4
JB		 12138 case R_ARM_V4BX:
12139 if (globals->fix_v4bx)
845b51d6
PB		 12140 {
12141 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 12142
845b51d6
PB		 12143 /* Ensure that we have a BX instruction. */
12144 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 12145
845b51d6
PB		 12146 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
12147 {
12148 /* Branch to veneer. */
12149 bfd_vma glue_addr;
12150 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
12151 glue_addr -= input_section->output_section->vma
12152 + input_section->output_offset
12153 + rel->r_offset + 8;
12154 insn = (insn & 0xf0000000) | 0x0a000000
12155 | ((glue_addr >> 2) & 0x00ffffff);
12156 }
12157 else
12158 {
12159 /* Preserve Rm (lowest four bits) and the condition code
12160 (highest four bits). Other bits encode MOV PC,Rm. */
12161 insn = (insn & 0xf000000f) | 0x01a0f000;
12162 }
319850b4 12163
845b51d6
PB		 12164 bfd_put_32 (input_bfd, insn, hit_data);
12165 }
319850b4
JB		 12166 return bfd_reloc_ok;
12167
b6895b4f
PB		 12168 case R_ARM_MOVW_ABS_NC:
12169 case R_ARM_MOVT_ABS:
12170 case R_ARM_MOVW_PREL_NC:
12171 case R_ARM_MOVT_PREL:
92f5d02b
MS		 12172 /* Until we properly support segment-base-relative addressing then
12173 we assume the segment base to be zero, as for the group relocations.
12174 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12175 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12176 case R_ARM_MOVW_BREL_NC:
12177 case R_ARM_MOVW_BREL:
12178 case R_ARM_MOVT_BREL:
b6895b4f
PB		 12179 {
12180 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
12181
12182 if (globals->use_rel)
12183 {
12184 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 12185 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12186 }
92f5d02b 12187
b6895b4f 12188 value += signed_addend;
b6895b4f
PB		 12189
12190 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
12191 value -= (input_section->output_section->vma
12192 + input_section->output_offset + rel->r_offset);
12193
92f5d02b 12194 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 12195 return bfd_reloc_overflow;
92f5d02b 12196
35fc36a8 12197 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12198 value |= 1;
12199
12200 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 12201 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 12202 value >>= 16;
12203
12204 insn &= 0xfff0f000;
12205 insn |= value & 0xfff;
12206 insn |= (value & 0xf000) << 4;
12207 bfd_put_32 (input_bfd, insn, hit_data);
12208 }
12209 return bfd_reloc_ok;
12210
12211 case R_ARM_THM_MOVW_ABS_NC:
12212 case R_ARM_THM_MOVT_ABS:
12213 case R_ARM_THM_MOVW_PREL_NC:
12214 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 12215 /* Until we properly support segment-base-relative addressing then
12216 we assume the segment base to be zero, as for the above relocations.
12217 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12218 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12219 as R_ARM_THM_MOVT_ABS. */
12220 case R_ARM_THM_MOVW_BREL_NC:
12221 case R_ARM_THM_MOVW_BREL:
12222 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 12223 {
12224 bfd_vma insn;
906e58ca 12225
b6895b4f
PB		 12226 insn = bfd_get_16 (input_bfd, hit_data) << 16;
12227 insn |= bfd_get_16 (input_bfd, hit_data + 2);
12228
12229 if (globals->use_rel)
12230 {
12231 addend = ((insn >> 4) & 0xf000)
12232 | ((insn >> 15) & 0x0800)
12233 | ((insn >> 4) & 0x0700)
07d6d2b8 12234 | (insn & 0x00ff);
39623e12 12235 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12236 }
92f5d02b 12237
b6895b4f 12238 value += signed_addend;
b6895b4f
PB		 12239
12240 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
12241 value -= (input_section->output_section->vma
12242 + input_section->output_offset + rel->r_offset);
12243
92f5d02b 12244 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 12245 return bfd_reloc_overflow;
92f5d02b 12246
35fc36a8 12247 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12248 value |= 1;
12249
12250 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 12251 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 12252 value >>= 16;
12253
12254 insn &= 0xfbf08f00;
12255 insn |= (value & 0xf000) << 4;
12256 insn |= (value & 0x0800) << 15;
12257 insn |= (value & 0x0700) << 4;
12258 insn |= (value & 0x00ff);
12259
12260 bfd_put_16 (input_bfd, insn >> 16, hit_data);
12261 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
12262 }
12263 return bfd_reloc_ok;
12264
4962c51a
MS		 12265 case R_ARM_ALU_PC_G0_NC:
12266 case R_ARM_ALU_PC_G1_NC:
12267 case R_ARM_ALU_PC_G0:
12268 case R_ARM_ALU_PC_G1:
12269 case R_ARM_ALU_PC_G2:
12270 case R_ARM_ALU_SB_G0_NC:
12271 case R_ARM_ALU_SB_G1_NC:
12272 case R_ARM_ALU_SB_G0:
12273 case R_ARM_ALU_SB_G1:
12274 case R_ARM_ALU_SB_G2:
12275 {
12276 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12277 bfd_vma pc = input_section->output_section->vma
4962c51a 12278 + input_section->output_offset + rel->r_offset;
31a91d61 12279 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12280 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 12281 bfd_vma residual;
12282 bfd_vma g_n;
4962c51a 12283 bfd_signed_vma signed_value;
99059e56
RM		 12284 int group = 0;
12285
12286 /* Determine which group of bits to select. */
12287 switch (r_type)
12288 {
12289 case R_ARM_ALU_PC_G0_NC:
12290 case R_ARM_ALU_PC_G0:
12291 case R_ARM_ALU_SB_G0_NC:
12292 case R_ARM_ALU_SB_G0:
12293 group = 0;
12294 break;
12295
12296 case R_ARM_ALU_PC_G1_NC:
12297 case R_ARM_ALU_PC_G1:
12298 case R_ARM_ALU_SB_G1_NC:
12299 case R_ARM_ALU_SB_G1:
12300 group = 1;
12301 break;
12302
12303 case R_ARM_ALU_PC_G2:
12304 case R_ARM_ALU_SB_G2:
12305 group = 2;
12306 break;
12307
12308 default:
12309 abort ();
12310 }
12311
12312 /* If REL, extract the addend from the insn. If RELA, it will
12313 have already been fetched for us. */
4962c51a 12314 if (globals->use_rel)
99059e56
RM		 12315 {
12316 int negative;
12317 bfd_vma constant = insn & 0xff;
12318 bfd_vma rotation = (insn & 0xf00) >> 8;
12319
12320 if (rotation == 0)
12321 signed_addend = constant;
12322 else
12323 {
12324 /* Compensate for the fact that in the instruction, the
12325 rotation is stored in multiples of 2 bits. */
12326 rotation *= 2;
12327
12328 /* Rotate "constant" right by "rotation" bits. */
12329 signed_addend = (constant >> rotation) |
12330 (constant << (8 * sizeof (bfd_vma) - rotation));
12331 }
12332
12333 /* Determine if the instruction is an ADD or a SUB.
12334 (For REL, this determines the sign of the addend.) */
12335 negative = identify_add_or_sub (insn);
12336 if (negative == 0)
12337 {
4eca0228 12338 _bfd_error_handler
695344c0 12339 /* xgettext:c-format */
90b6238f 12340 (_("%pB(%pA+%#" PRIx64 "): only ADD or SUB instructions "
2dcf00ce
AM		 12341 "are allowed for ALU group relocations"),
12342 input_bfd, input_section, (uint64_t) rel->r_offset);
99059e56
RM		 12343 return bfd_reloc_overflow;
12344 }
12345
12346 signed_addend *= negative;
12347 }
4962c51a
MS		 12348
12349 /* Compute the value (X) to go in the place. */
99059e56
RM		 12350 if (r_type == R_ARM_ALU_PC_G0_NC
12351 || r_type == R_ARM_ALU_PC_G1_NC
12352 || r_type == R_ARM_ALU_PC_G0
12353 || r_type == R_ARM_ALU_PC_G1
12354 || r_type == R_ARM_ALU_PC_G2)
12355 /* PC relative. */
12356 signed_value = value - pc + signed_addend;
12357 else
12358 /* Section base relative. */
12359 signed_value = value - sb + signed_addend;
12360
12361 /* If the target symbol is a Thumb function, then set the
12362 Thumb bit in the address. */
35fc36a8 12363 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 12364 signed_value |= 1;
12365
99059e56
RM		 12366 /* Calculate the value of the relevant G_n, in encoded
12367 constant-with-rotation format. */
b6518b38
NC		 12368 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12369 group, &residual);
99059e56
RM		 12370
12371 /* Check for overflow if required. */
12372 if ((r_type == R_ARM_ALU_PC_G0
12373 || r_type == R_ARM_ALU_PC_G1
12374 || r_type == R_ARM_ALU_PC_G2
12375 || r_type == R_ARM_ALU_SB_G0
12376 || r_type == R_ARM_ALU_SB_G1
12377 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
12378 {
4eca0228 12379 _bfd_error_handler
695344c0 12380 /* xgettext:c-format */
90b6238f 12381 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12382 "splitting %#" PRIx64 " for group relocation %s"),
12383 input_bfd, input_section, (uint64_t) rel->r_offset,
12384 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12385 howto->name);
99059e56
RM		 12386 return bfd_reloc_overflow;
12387 }
12388
12389 /* Mask out the value and the ADD/SUB part of the opcode; take care
12390 not to destroy the S bit. */
12391 insn &= 0xff1ff000;
12392
12393 /* Set the opcode according to whether the value to go in the
12394 place is negative. */
12395 if (signed_value < 0)
12396 insn |= 1 << 22;
12397 else
12398 insn |= 1 << 23;
12399
12400 /* Encode the offset. */
12401 insn |= g_n;
4962c51a
MS		 12402
12403 bfd_put_32 (input_bfd, insn, hit_data);
12404 }
12405 return bfd_reloc_ok;
12406
12407 case R_ARM_LDR_PC_G0:
12408 case R_ARM_LDR_PC_G1:
12409 case R_ARM_LDR_PC_G2:
12410 case R_ARM_LDR_SB_G0:
12411 case R_ARM_LDR_SB_G1:
12412 case R_ARM_LDR_SB_G2:
12413 {
12414 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12415 bfd_vma pc = input_section->output_section->vma
4962c51a 12416 + input_section->output_offset + rel->r_offset;
31a91d61 12417 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12418 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12419 bfd_vma residual;
4962c51a 12420 bfd_signed_vma signed_value;
99059e56
RM		 12421 int group = 0;
12422
12423 /* Determine which groups of bits to calculate. */
12424 switch (r_type)
12425 {
12426 case R_ARM_LDR_PC_G0:
12427 case R_ARM_LDR_SB_G0:
12428 group = 0;
12429 break;
12430
12431 case R_ARM_LDR_PC_G1:
12432 case R_ARM_LDR_SB_G1:
12433 group = 1;
12434 break;
12435
12436 case R_ARM_LDR_PC_G2:
12437 case R_ARM_LDR_SB_G2:
12438 group = 2;
12439 break;
12440
12441 default:
12442 abort ();
12443 }
12444
12445 /* If REL, extract the addend from the insn. If RELA, it will
12446 have already been fetched for us. */
4962c51a 12447 if (globals->use_rel)
99059e56
RM		 12448 {
12449 int negative = (insn & (1 << 23)) ? 1 : -1;
12450 signed_addend = negative * (insn & 0xfff);
12451 }
4962c51a
MS		 12452
12453 /* Compute the value (X) to go in the place. */
99059e56
RM		 12454 if (r_type == R_ARM_LDR_PC_G0
12455 || r_type == R_ARM_LDR_PC_G1
12456 || r_type == R_ARM_LDR_PC_G2)
12457 /* PC relative. */
12458 signed_value = value - pc + signed_addend;
12459 else
12460 /* Section base relative. */
12461 signed_value = value - sb + signed_addend;
12462
12463 /* Calculate the value of the relevant G_{n-1} to obtain
12464 the residual at that stage. */
b6518b38
NC		 12465 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12466 group - 1, &residual);
99059e56
RM		 12467
12468 /* Check for overflow. */
12469 if (residual >= 0x1000)
12470 {
4eca0228 12471 _bfd_error_handler
695344c0 12472 /* xgettext:c-format */
90b6238f 12473 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12474 "splitting %#" PRIx64 " for group relocation %s"),
12475 input_bfd, input_section, (uint64_t) rel->r_offset,
12476 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12477 howto->name);
99059e56
RM		 12478 return bfd_reloc_overflow;
12479 }
12480
12481 /* Mask out the value and U bit. */
12482 insn &= 0xff7ff000;
12483
12484 /* Set the U bit if the value to go in the place is non-negative. */
12485 if (signed_value >= 0)
12486 insn |= 1 << 23;
12487
12488 /* Encode the offset. */
12489 insn |= residual;
4962c51a
MS		 12490
12491 bfd_put_32 (input_bfd, insn, hit_data);
12492 }
12493 return bfd_reloc_ok;
12494
12495 case R_ARM_LDRS_PC_G0:
12496 case R_ARM_LDRS_PC_G1:
12497 case R_ARM_LDRS_PC_G2:
12498 case R_ARM_LDRS_SB_G0:
12499 case R_ARM_LDRS_SB_G1:
12500 case R_ARM_LDRS_SB_G2:
12501 {
12502 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12503 bfd_vma pc = input_section->output_section->vma
4962c51a 12504 + input_section->output_offset + rel->r_offset;
31a91d61 12505 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12506 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12507 bfd_vma residual;
4962c51a 12508 bfd_signed_vma signed_value;
99059e56
RM		 12509 int group = 0;
12510
12511 /* Determine which groups of bits to calculate. */
12512 switch (r_type)
12513 {
12514 case R_ARM_LDRS_PC_G0:
12515 case R_ARM_LDRS_SB_G0:
12516 group = 0;
12517 break;
12518
12519 case R_ARM_LDRS_PC_G1:
12520 case R_ARM_LDRS_SB_G1:
12521 group = 1;
12522 break;
12523
12524 case R_ARM_LDRS_PC_G2:
12525 case R_ARM_LDRS_SB_G2:
12526 group = 2;
12527 break;
12528
12529 default:
12530 abort ();
12531 }
12532
12533 /* If REL, extract the addend from the insn. If RELA, it will
12534 have already been fetched for us. */
4962c51a 12535 if (globals->use_rel)
99059e56
RM		 12536 {
12537 int negative = (insn & (1 << 23)) ? 1 : -1;
12538 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
12539 }
4962c51a
MS		 12540
12541 /* Compute the value (X) to go in the place. */
99059e56
RM		 12542 if (r_type == R_ARM_LDRS_PC_G0
12543 || r_type == R_ARM_LDRS_PC_G1
12544 || r_type == R_ARM_LDRS_PC_G2)
12545 /* PC relative. */
12546 signed_value = value - pc + signed_addend;
12547 else
12548 /* Section base relative. */
12549 signed_value = value - sb + signed_addend;
12550
12551 /* Calculate the value of the relevant G_{n-1} to obtain
12552 the residual at that stage. */
b6518b38
NC		 12553 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12554 group - 1, &residual);
99059e56
RM		 12555
12556 /* Check for overflow. */
12557 if (residual >= 0x100)
12558 {
4eca0228 12559 _bfd_error_handler
695344c0 12560 /* xgettext:c-format */
90b6238f 12561 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12562 "splitting %#" PRIx64 " for group relocation %s"),
12563 input_bfd, input_section, (uint64_t) rel->r_offset,
12564 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12565 howto->name);
99059e56
RM		 12566 return bfd_reloc_overflow;
12567 }
12568
12569 /* Mask out the value and U bit. */
12570 insn &= 0xff7ff0f0;
12571
12572 /* Set the U bit if the value to go in the place is non-negative. */
12573 if (signed_value >= 0)
12574 insn |= 1 << 23;
12575
12576 /* Encode the offset. */
12577 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12578
12579 bfd_put_32 (input_bfd, insn, hit_data);
12580 }
12581 return bfd_reloc_ok;
12582
12583 case R_ARM_LDC_PC_G0:
12584 case R_ARM_LDC_PC_G1:
12585 case R_ARM_LDC_PC_G2:
12586 case R_ARM_LDC_SB_G0:
12587 case R_ARM_LDC_SB_G1:
12588 case R_ARM_LDC_SB_G2:
12589 {
12590 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12591 bfd_vma pc = input_section->output_section->vma
4962c51a 12592 + input_section->output_offset + rel->r_offset;
31a91d61 12593 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12594 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12595 bfd_vma residual;
4962c51a 12596 bfd_signed_vma signed_value;
99059e56
RM		 12597 int group = 0;
12598
12599 /* Determine which groups of bits to calculate. */
12600 switch (r_type)
12601 {
12602 case R_ARM_LDC_PC_G0:
12603 case R_ARM_LDC_SB_G0:
12604 group = 0;
12605 break;
12606
12607 case R_ARM_LDC_PC_G1:
12608 case R_ARM_LDC_SB_G1:
12609 group = 1;
12610 break;
12611
12612 case R_ARM_LDC_PC_G2:
12613 case R_ARM_LDC_SB_G2:
12614 group = 2;
12615 break;
12616
12617 default:
12618 abort ();
12619 }
12620
12621 /* If REL, extract the addend from the insn. If RELA, it will
12622 have already been fetched for us. */
4962c51a 12623 if (globals->use_rel)
99059e56
RM		 12624 {
12625 int negative = (insn & (1 << 23)) ? 1 : -1;
12626 signed_addend = negative * ((insn & 0xff) << 2);
12627 }
4962c51a
MS		 12628
12629 /* Compute the value (X) to go in the place. */
99059e56
RM		 12630 if (r_type == R_ARM_LDC_PC_G0
12631 || r_type == R_ARM_LDC_PC_G1
12632 || r_type == R_ARM_LDC_PC_G2)
12633 /* PC relative. */
12634 signed_value = value - pc + signed_addend;
12635 else
12636 /* Section base relative. */
12637 signed_value = value - sb + signed_addend;
12638
12639 /* Calculate the value of the relevant G_{n-1} to obtain
12640 the residual at that stage. */
b6518b38
NC		 12641 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12642 group - 1, &residual);
99059e56
RM		 12643
12644 /* Check for overflow. (The absolute value to go in the place must be
12645 divisible by four and, after having been divided by four, must
12646 fit in eight bits.) */
12647 if ((residual & 0x3) != 0 || residual >= 0x400)
12648 {
4eca0228 12649 _bfd_error_handler
695344c0 12650 /* xgettext:c-format */
90b6238f 12651 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12652 "splitting %#" PRIx64 " for group relocation %s"),
12653 input_bfd, input_section, (uint64_t) rel->r_offset,
12654 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12655 howto->name);
99059e56
RM		 12656 return bfd_reloc_overflow;
12657 }
12658
12659 /* Mask out the value and U bit. */
12660 insn &= 0xff7fff00;
12661
12662 /* Set the U bit if the value to go in the place is non-negative. */
12663 if (signed_value >= 0)
12664 insn |= 1 << 23;
12665
12666 /* Encode the offset. */
12667 insn |= residual >> 2;
4962c51a
MS		 12668
12669 bfd_put_32 (input_bfd, insn, hit_data);
12670 }
12671 return bfd_reloc_ok;
12672
72d98d16
MG		 12673 case R_ARM_THM_ALU_ABS_G0_NC:
12674 case R_ARM_THM_ALU_ABS_G1_NC:
12675 case R_ARM_THM_ALU_ABS_G2_NC:
12676 case R_ARM_THM_ALU_ABS_G3_NC:
12677 {
12678 const int shift_array[4] = {0, 8, 16, 24};
12679 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12680 bfd_vma addr = value;
12681 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12682
12683 /* Compute address. */
12684 if (globals->use_rel)
12685 signed_addend = insn & 0xff;
12686 addr += signed_addend;
12687 if (branch_type == ST_BRANCH_TO_THUMB)
12688 addr |= 1;
12689 /* Clean imm8 insn. */
12690 insn &= 0xff00;
12691 /* And update with correct part of address. */
12692 insn |= (addr >> shift) & 0xff;
12693 /* Update insn. */
12694 bfd_put_16 (input_bfd, insn, hit_data);
12695 }
12696
12697 *unresolved_reloc_p = FALSE;
12698 return bfd_reloc_ok;
12699
e8b09b87
CL		 12700 case R_ARM_GOTOFFFUNCDESC:
12701 {
4b24dd1a 12702 if (h == NULL)
e8b09b87
CL		 12703 {
12704 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12705 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12706 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12707 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12708 bfd_vma seg = -1;
12709
12710 if (bfd_link_pic(info) && dynindx == 0)
12711 abort();
12712
12713 /* Resolve relocation. */
12714 bfd_put_32(output_bfd, (offset + sgot->output_offset)
12715 , contents + rel->r_offset);
12716 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12717 not done yet. */
12718 arm_elf_fill_funcdesc(output_bfd, info,
12719 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12720 dynindx, offset, addr, dynreloc_value, seg);
12721 }
12722 else
12723 {
12724 int dynindx;
12725 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12726 bfd_vma addr;
12727 bfd_vma seg = -1;
12728
12729 /* For static binaries, sym_sec can be null. */
12730 if (sym_sec)
12731 {
12732 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12733 addr = dynreloc_value - sym_sec->output_section->vma;
12734 }
12735 else
12736 {
12737 dynindx = 0;
12738 addr = 0;
12739 }
12740
12741 if (bfd_link_pic(info) && dynindx == 0)
12742 abort();
12743
12744 /* This case cannot occur since funcdesc is allocated by
12745 the dynamic loader so we cannot resolve the relocation. */
12746 if (h->dynindx != -1)
12747 abort();
12748
12749 /* Resolve relocation. */
12750 bfd_put_32(output_bfd, (offset + sgot->output_offset),
12751 contents + rel->r_offset);
12752 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12753 arm_elf_fill_funcdesc(output_bfd, info,
12754 &eh->fdpic_cnts.funcdesc_offset,
12755 dynindx, offset, addr, dynreloc_value, seg);
12756 }
12757 }
12758 *unresolved_reloc_p = FALSE;
12759 return bfd_reloc_ok;
12760
12761 case R_ARM_GOTFUNCDESC:
12762 {
4b24dd1a 12763 if (h != NULL)
e8b09b87
CL		 12764 {
12765 Elf_Internal_Rela outrel;
12766
12767 /* Resolve relocation. */
12768 bfd_put_32(output_bfd, ((eh->fdpic_cnts.gotfuncdesc_offset & ~1)
12769 + sgot->output_offset),
12770 contents + rel->r_offset);
12771 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12772 if(h->dynindx == -1)
12773 {
12774 int dynindx;
12775 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12776 bfd_vma addr;
12777 bfd_vma seg = -1;
12778
12779 /* For static binaries sym_sec can be null. */
12780 if (sym_sec)
12781 {
12782 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12783 addr = dynreloc_value - sym_sec->output_section->vma;
12784 }
12785 else
12786 {
12787 dynindx = 0;
12788 addr = 0;
12789 }
12790
12791 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12792 arm_elf_fill_funcdesc(output_bfd, info,
12793 &eh->fdpic_cnts.funcdesc_offset,
12794 dynindx, offset, addr, dynreloc_value, seg);
12795 }
12796
12797 /* Add a dynamic relocation on GOT entry if not already done. */
12798 if ((eh->fdpic_cnts.gotfuncdesc_offset & 1) == 0)
12799 {
12800 if (h->dynindx == -1)
12801 {
12802 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12803 if (h->root.type == bfd_link_hash_undefweak)
12804 bfd_put_32(output_bfd, 0, sgot->contents
12805 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12806 else
12807 bfd_put_32(output_bfd, sgot->output_section->vma
12808 + sgot->output_offset
12809 + (eh->fdpic_cnts.funcdesc_offset & ~1),
12810 sgot->contents
12811 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12812 }
12813 else
12814 {
12815 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12816 }
12817 outrel.r_offset = sgot->output_section->vma
12818 + sgot->output_offset
12819 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1);
12820 outrel.r_addend = 0;
12821 if (h->dynindx == -1 && !bfd_link_pic(info))
12822 if (h->root.type == bfd_link_hash_undefweak)
4b24dd1a 12823 arm_elf_add_rofixup(output_bfd, globals->srofixup, -1);
e8b09b87 12824 else
4b24dd1a
AM		 12825 arm_elf_add_rofixup(output_bfd, globals->srofixup,
12826 outrel.r_offset);
e8b09b87
CL		 12827 else
12828 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12829 eh->fdpic_cnts.gotfuncdesc_offset |= 1;
12830 }
12831 }
12832 else
12833 {
12834 /* Such relocation on static function should not have been
12835 emitted by the compiler. */
12836 abort();
12837 }
12838 }
12839 *unresolved_reloc_p = FALSE;
12840 return bfd_reloc_ok;
12841
12842 case R_ARM_FUNCDESC:
12843 {
4b24dd1a 12844 if (h == NULL)
e8b09b87
CL		 12845 {
12846 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12847 Elf_Internal_Rela outrel;
12848 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12849 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12850 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12851 bfd_vma seg = -1;
12852
12853 if (bfd_link_pic(info) && dynindx == 0)
12854 abort();
12855
12856 /* Replace static FUNCDESC relocation with a
12857 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12858 executable. */
12859 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12860 outrel.r_offset = input_section->output_section->vma
12861 + input_section->output_offset + rel->r_offset;
12862 outrel.r_addend = 0;
12863 if (bfd_link_pic(info))
12864 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12865 else
12866 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12867
12868 bfd_put_32 (input_bfd, sgot->output_section->vma
12869 + sgot->output_offset + offset, hit_data);
12870
12871 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12872 arm_elf_fill_funcdesc(output_bfd, info,
12873 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12874 dynindx, offset, addr, dynreloc_value, seg);
12875 }
12876 else
12877 {
12878 if (h->dynindx == -1)
12879 {
12880 int dynindx;
12881 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12882 bfd_vma addr;
12883 bfd_vma seg = -1;
12884 Elf_Internal_Rela outrel;
12885
12886 /* For static binaries sym_sec can be null. */
12887 if (sym_sec)
12888 {
12889 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12890 addr = dynreloc_value - sym_sec->output_section->vma;
12891 }
12892 else
12893 {
12894 dynindx = 0;
12895 addr = 0;
12896 }
12897
12898 if (bfd_link_pic(info) && dynindx == 0)
12899 abort();
12900
12901 /* Replace static FUNCDESC relocation with a
12902 R_ARM_RELATIVE dynamic relocation. */
12903 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12904 outrel.r_offset = input_section->output_section->vma
12905 + input_section->output_offset + rel->r_offset;
12906 outrel.r_addend = 0;
12907 if (bfd_link_pic(info))
12908 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12909 else
12910 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12911
12912 bfd_put_32 (input_bfd, sgot->output_section->vma
12913 + sgot->output_offset + offset, hit_data);
12914
12915 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12916 arm_elf_fill_funcdesc(output_bfd, info,
12917 &eh->fdpic_cnts.funcdesc_offset,
12918 dynindx, offset, addr, dynreloc_value, seg);
12919 }
12920 else
12921 {
12922 Elf_Internal_Rela outrel;
12923
12924 /* Add a dynamic relocation. */
12925 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12926 outrel.r_offset = input_section->output_section->vma
12927 + input_section->output_offset + rel->r_offset;
12928 outrel.r_addend = 0;
12929 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12930 }
12931 }
12932 }
12933 *unresolved_reloc_p = FALSE;
12934 return bfd_reloc_ok;
12935
e5d6e09e
AV		 12936 case R_ARM_THM_BF16:
12937 {
12938 bfd_vma relocation;
12939 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12940 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12941
12942 if (globals->use_rel)
12943 {
12944 bfd_vma immA = (upper_insn & 0x001f);
12945 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12946 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12947 addend = (immA << 12);
12948 addend |= (immB << 2);
12949 addend |= (immC << 1);
12950 addend |= 1;
12951 /* Sign extend. */
e6f65e75 12952 signed_addend = (addend & 0x10000) ? addend - (1 << 17) : addend;
e5d6e09e
AV		 12953 }
12954
e6f65e75 12955 relocation = value + signed_addend;
e5d6e09e
AV		 12956 relocation -= (input_section->output_section->vma
12957 + input_section->output_offset
12958 + rel->r_offset);
12959
12960 /* Put RELOCATION back into the insn. */
12961 {
12962 bfd_vma immA = (relocation & 0x0001f000) >> 12;
12963 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12964 bfd_vma immC = (relocation & 0x00000002) >> 1;
12965
12966 upper_insn = (upper_insn & 0xffe0) | immA;
12967 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
12968 }
12969
12970 /* Put the relocated value back in the object file: */
12971 bfd_put_16 (input_bfd, upper_insn, hit_data);
12972 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12973
12974 return bfd_reloc_ok;
12975 }
12976
1889da70
AV		 12977 case R_ARM_THM_BF12:
12978 {
12979 bfd_vma relocation;
12980 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12981 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12982
12983 if (globals->use_rel)
12984 {
12985 bfd_vma immA = (upper_insn & 0x0001);
12986 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12987 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12988 addend = (immA << 12);
12989 addend |= (immB << 2);
12990 addend |= (immC << 1);
12991 addend |= 1;
12992 /* Sign extend. */
12993 addend = (addend & 0x1000) ? addend - (1 << 13) : addend;
e6f65e75 12994 signed_addend = addend;
1889da70
AV		 12995 }
12996
e6f65e75 12997 relocation = value + signed_addend;
1889da70
AV		 12998 relocation -= (input_section->output_section->vma
12999 + input_section->output_offset
13000 + rel->r_offset);
13001
13002 /* Put RELOCATION back into the insn. */
13003 {
13004 bfd_vma immA = (relocation & 0x00001000) >> 12;
13005 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
13006 bfd_vma immC = (relocation & 0x00000002) >> 1;
13007
13008 upper_insn = (upper_insn & 0xfffe) | immA;
13009 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
13010 }
13011
13012 /* Put the relocated value back in the object file: */
13013 bfd_put_16 (input_bfd, upper_insn, hit_data);
13014 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
13015
13016 return bfd_reloc_ok;
13017 }
13018
1caf72a5
AV		 13019 case R_ARM_THM_BF18:
13020 {
13021 bfd_vma relocation;
13022 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
13023 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
13024
13025 if (globals->use_rel)
13026 {
13027 bfd_vma immA = (upper_insn & 0x007f);
13028 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
13029 bfd_vma immC = (lower_insn & 0x0800) >> 11;
13030 addend = (immA << 12);
13031 addend |= (immB << 2);
13032 addend |= (immC << 1);
13033 addend |= 1;
13034 /* Sign extend. */
13035 addend = (addend & 0x40000) ? addend - (1 << 19) : addend;
e6f65e75 13036 signed_addend = addend;
1caf72a5
AV		 13037 }
13038
e6f65e75 13039 relocation = value + signed_addend;
1caf72a5
AV		 13040 relocation -= (input_section->output_section->vma
13041 + input_section->output_offset
13042 + rel->r_offset);
13043
13044 /* Put RELOCATION back into the insn. */
13045 {
13046 bfd_vma immA = (relocation & 0x0007f000) >> 12;
13047 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
13048 bfd_vma immC = (relocation & 0x00000002) >> 1;
13049
13050 upper_insn = (upper_insn & 0xff80) | immA;
13051 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
13052 }
13053
13054 /* Put the relocated value back in the object file: */
13055 bfd_put_16 (input_bfd, upper_insn, hit_data);
13056 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
13057
13058 return bfd_reloc_ok;
13059 }
13060
252b5132
RH		 13061 default:
13062 return bfd_reloc_notsupported;
13063 }
13064}
13065
98c1d4aa
NC		 13066/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
13067static void
07d6d2b8
AM		 13068arm_add_to_rel (bfd * abfd,
13069 bfd_byte * address,
57e8b36a 13070 reloc_howto_type * howto,
07d6d2b8 13071 bfd_signed_vma increment)
98c1d4aa 13072{
98c1d4aa
NC		 13073 bfd_signed_vma addend;
13074
bd97cb95
DJ		 13075 if (howto->type == R_ARM_THM_CALL
13076 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 13077 {
9a5aca8c
AM		 13078 int upper_insn, lower_insn;
13079 int upper, lower;
98c1d4aa 13080
9a5aca8c
AM		 13081 upper_insn = bfd_get_16 (abfd, address);
13082 lower_insn = bfd_get_16 (abfd, address + 2);
13083 upper = upper_insn & 0x7ff;
13084 lower = lower_insn & 0x7ff;
13085
13086 addend = (upper << 12) | (lower << 1);
ddda4409 13087 addend += increment;
9a5aca8c 13088 addend >>= 1;
98c1d4aa 13089
9a5aca8c
AM		 13090 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
13091 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
13092
dc810e39
AM		 13093 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
13094 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 13095 }
13096 else
13097 {
07d6d2b8 13098 bfd_vma contents;
9a5aca8c
AM		 13099
13100 contents = bfd_get_32 (abfd, address);
13101
13102 /* Get the (signed) value from the instruction. */
13103 addend = contents & howto->src_mask;
13104 if (addend & ((howto->src_mask + 1) >> 1))
13105 {
13106 bfd_signed_vma mask;
13107
13108 mask = -1;
13109 mask &= ~ howto->src_mask;
13110 addend |= mask;
13111 }
13112
13113 /* Add in the increment, (which is a byte value). */
13114 switch (howto->type)
13115 {
13116 default:
13117 addend += increment;
13118 break;
13119
13120 case R_ARM_PC24:
c6596c5e 13121 case R_ARM_PLT32:
5b5bb741
PB		 13122 case R_ARM_CALL:
13123 case R_ARM_JUMP24:
9a5aca8c 13124 addend <<= howto->size;
dc810e39 13125 addend += increment;
9a5aca8c
AM		 13126
13127 /* Should we check for overflow here ? */
13128
13129 /* Drop any undesired bits. */
13130 addend >>= howto->rightshift;
13131 break;
13132 }
13133
13134 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
13135
13136 bfd_put_32 (abfd, contents, address);
ddda4409 13137 }
98c1d4aa 13138}
252b5132 13139
ba93b8ac
DJ		 13140#define IS_ARM_TLS_RELOC(R_TYPE) \
13141 ((R_TYPE) == R_ARM_TLS_GD32 \
5c5a4843 13142 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
ba93b8ac
DJ		 13143 || (R_TYPE) == R_ARM_TLS_LDO32 \
13144 || (R_TYPE) == R_ARM_TLS_LDM32 \
5c5a4843 13145 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
ba93b8ac
DJ		 13146 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
13147 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
13148 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
13149 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b 13150 || (R_TYPE) == R_ARM_TLS_IE32 \
5c5a4843 13151 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
0855e32b
NS		 13152 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
13153
13154/* Specific set of relocations for the gnu tls dialect. */
13155#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
13156 ((R_TYPE) == R_ARM_TLS_GOTDESC \
13157 || (R_TYPE) == R_ARM_TLS_CALL \
13158 || (R_TYPE) == R_ARM_THM_TLS_CALL \
13159 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
13160 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 13161
252b5132 13162/* Relocate an ARM ELF section. */
906e58ca 13163
b34976b6 13164static bfd_boolean
07d6d2b8 13165elf32_arm_relocate_section (bfd * output_bfd,
57e8b36a 13166 struct bfd_link_info * info,
07d6d2b8
AM		 13167 bfd * input_bfd,
13168 asection * input_section,
13169 bfd_byte * contents,
13170 Elf_Internal_Rela * relocs,
13171 Elf_Internal_Sym * local_syms,
13172 asection ** local_sections)
252b5132 13173{
b34976b6
AM		 13174 Elf_Internal_Shdr *symtab_hdr;
13175 struct elf_link_hash_entry **sym_hashes;
13176 Elf_Internal_Rela *rel;
13177 Elf_Internal_Rela *relend;
13178 const char *name;
b32d3aa2 13179 struct elf32_arm_link_hash_table * globals;
252b5132 13180
4e7fd91e 13181 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13182 if (globals == NULL)
13183 return FALSE;
b491616a 13184
0ffa91dd 13185 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 13186 sym_hashes = elf_sym_hashes (input_bfd);
13187
13188 rel = relocs;
13189 relend = relocs + input_section->reloc_count;
13190 for (; rel < relend; rel++)
13191 {
07d6d2b8
AM		 13192 int r_type;
13193 reloc_howto_type * howto;
13194 unsigned long r_symndx;
13195 Elf_Internal_Sym * sym;
13196 asection * sec;
252b5132 13197 struct elf_link_hash_entry * h;
07d6d2b8
AM		 13198 bfd_vma relocation;
13199 bfd_reloc_status_type r;
13200 arelent bfd_reloc;
13201 char sym_type;
13202 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 13203 char *error_message = NULL;
f21f3fe0 13204
252b5132 13205 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 13206 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 13207 r_type = arm_real_reloc_type (globals, r_type);
252b5132 13208
ba96a88f 13209 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 13210 || r_type == R_ARM_GNU_VTINHERIT)
13211 continue;
252b5132 13212
47aeb64c
NC		 13213 howto = bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
13214
13215 if (howto == NULL)
13216 return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
252b5132 13217
252b5132
RH		 13218 h = NULL;
13219 sym = NULL;
13220 sec = NULL;
9b485d32 13221
252b5132
RH		 13222 if (r_symndx < symtab_hdr->sh_info)
13223 {
13224 sym = local_syms + r_symndx;
ba93b8ac 13225 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 13226 sec = local_sections[r_symndx];
ffcb4889
NS		 13227
13228 /* An object file might have a reference to a local
13229 undefined symbol. This is a daft object file, but we
13230 should at least do something about it. V4BX & NONE
13231 relocations do not use the symbol and are explicitly
77b4f08f
TS		 13232 allowed to use the undefined symbol, so allow those.
13233 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 13234 if (r_type != R_ARM_V4BX
13235 && r_type != R_ARM_NONE
77b4f08f 13236 && r_symndx != STN_UNDEF
ffcb4889
NS		 13237 && bfd_is_und_section (sec)
13238 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 13239 (*info->callbacks->undefined_symbol)
13240 (info, bfd_elf_string_from_elf_section
13241 (input_bfd, symtab_hdr->sh_link, sym->st_name),
13242 input_bfd, input_section,
13243 rel->r_offset, TRUE);
b38cadfb 13244
4e7fd91e 13245 if (globals->use_rel)
f8df10f4 13246 {
4e7fd91e
PB		 13247 relocation = (sec->output_section->vma
13248 + sec->output_offset
13249 + sym->st_value);
0e1862bb 13250 if (!bfd_link_relocatable (info)
ab96bf03
AM		 13251 && (sec->flags & SEC_MERGE)
13252 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 13253 {
4e7fd91e
PB		 13254 asection *msec;
13255 bfd_vma addend, value;
13256
39623e12 13257 switch (r_type)
4e7fd91e 13258 {
39623e12
PB		 13259 case R_ARM_MOVW_ABS_NC:
13260 case R_ARM_MOVT_ABS:
13261 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13262 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
13263 addend = (addend ^ 0x8000) - 0x8000;
13264 break;
f8df10f4 13265
39623e12
PB		 13266 case R_ARM_THM_MOVW_ABS_NC:
13267 case R_ARM_THM_MOVT_ABS:
13268 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
13269 << 16;
13270 value |= bfd_get_16 (input_bfd,
13271 contents + rel->r_offset + 2);
13272 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
13273 | ((value & 0x04000000) >> 15);
13274 addend = (addend ^ 0x8000) - 0x8000;
13275 break;
f8df10f4 13276
39623e12
PB		 13277 default:
13278 if (howto->rightshift
13279 || (howto->src_mask & (howto->src_mask + 1)))
13280 {
4eca0228 13281 _bfd_error_handler
695344c0 13282 /* xgettext:c-format */
2dcf00ce
AM		 13283 (_("%pB(%pA+%#" PRIx64 "): "
13284 "%s relocation against SEC_MERGE section"),
39623e12 13285 input_bfd, input_section,
2dcf00ce 13286 (uint64_t) rel->r_offset, howto->name);
39623e12
PB		 13287 return FALSE;
13288 }
13289
13290 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13291
13292 /* Get the (signed) value from the instruction. */
13293 addend = value & howto->src_mask;
13294 if (addend & ((howto->src_mask + 1) >> 1))
13295 {
13296 bfd_signed_vma mask;
13297
13298 mask = -1;
13299 mask &= ~ howto->src_mask;
13300 addend |= mask;
13301 }
13302 break;
4e7fd91e 13303 }
39623e12 13304
4e7fd91e
PB		 13305 msec = sec;
13306 addend =
13307 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
13308 - relocation;
13309 addend += msec->output_section->vma + msec->output_offset;
39623e12 13310
cc643b88 13311 /* Cases here must match those in the preceding
39623e12
PB		 13312 switch statement. */
13313 switch (r_type)
13314 {
13315 case R_ARM_MOVW_ABS_NC:
13316 case R_ARM_MOVT_ABS:
13317 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
13318 | (addend & 0xfff);
13319 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13320 break;
13321
13322 case R_ARM_THM_MOVW_ABS_NC:
13323 case R_ARM_THM_MOVT_ABS:
13324 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
13325 | (addend & 0xff) | ((addend & 0x0800) << 15);
13326 bfd_put_16 (input_bfd, value >> 16,
13327 contents + rel->r_offset);
13328 bfd_put_16 (input_bfd, value,
13329 contents + rel->r_offset + 2);
13330 break;
13331
13332 default:
13333 value = (value & ~ howto->dst_mask)
13334 | (addend & howto->dst_mask);
13335 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13336 break;
13337 }
f8df10f4 13338 }
f8df10f4 13339 }
4e7fd91e
PB		 13340 else
13341 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 13342 }
13343 else
13344 {
62d887d4 13345 bfd_boolean warned, ignored;
560e09e9 13346
b2a8e766
AM		 13347 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
13348 r_symndx, symtab_hdr, sym_hashes,
13349 h, sec, relocation,
62d887d4 13350 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 13351
13352 sym_type = h->type;
252b5132
RH		 13353 }
13354
dbaa2011 13355 if (sec != NULL && discarded_section (sec))
e4067dbb 13356 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 13357 rel, 1, relend, howto, 0, contents);
ab96bf03 13358
0e1862bb 13359 if (bfd_link_relocatable (info))
ab96bf03
AM		 13360 {
13361 /* This is a relocatable link. We don't have to change
13362 anything, unless the reloc is against a section symbol,
13363 in which case we have to adjust according to where the
13364 section symbol winds up in the output section. */
13365 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
13366 {
13367 if (globals->use_rel)
13368 arm_add_to_rel (input_bfd, contents + rel->r_offset,
13369 howto, (bfd_signed_vma) sec->output_offset);
13370 else
13371 rel->r_addend += sec->output_offset;
13372 }
13373 continue;
13374 }
13375
252b5132
RH		 13376 if (h != NULL)
13377 name = h->root.root.string;
13378 else
13379 {
13380 name = (bfd_elf_string_from_elf_section
13381 (input_bfd, symtab_hdr->sh_link, sym->st_name));
13382 if (name == NULL || *name == '\0')
fd361982 13383 name = bfd_section_name (sec);
252b5132 13384 }
f21f3fe0 13385
cf35638d 13386 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 13387 && r_type != R_ARM_NONE
13388 && (h == NULL
13389 || h->root.type == bfd_link_hash_defined
13390 || h->root.type == bfd_link_hash_defweak)
13391 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
13392 {
4eca0228 13393 _bfd_error_handler
ba93b8ac 13394 ((sym_type == STT_TLS
695344c0 13395 /* xgettext:c-format */
2dcf00ce 13396 ? _("%pB(%pA+%#" PRIx64 "): %s used with TLS symbol %s")
695344c0 13397 /* xgettext:c-format */
2dcf00ce 13398 : _("%pB(%pA+%#" PRIx64 "): %s used with non-TLS symbol %s")),
ba93b8ac
DJ		 13399 input_bfd,
13400 input_section,
2dcf00ce 13401 (uint64_t) rel->r_offset,
ba93b8ac
DJ		 13402 howto->name,
13403 name);
13404 }
13405
0855e32b 13406 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 13407 done, i.e., the relaxation produced the final output we want,
13408 and we won't let anybody mess with it. Also, we have to do
13409 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 13410 both in relaxed and non-relaxed cases. */
39d911fc
TP		 13411 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
13412 || (IS_ARM_TLS_GNU_RELOC (r_type)
13413 && !((h ? elf32_arm_hash_entry (h)->tls_type :
13414 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
13415 & GOT_TLS_GDESC)))
13416 {
13417 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
13418 contents, rel, h == NULL);
13419 /* This may have been marked unresolved because it came from
13420 a shared library. But we've just dealt with that. */
13421 unresolved_reloc = 0;
13422 }
13423 else
13424 r = bfd_reloc_continue;
b38cadfb 13425
39d911fc
TP		 13426 if (r == bfd_reloc_continue)
13427 {
13428 unsigned char branch_type =
13429 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
13430 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
13431
13432 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
13433 input_section, contents, rel,
13434 relocation, info, sec, name,
13435 sym_type, branch_type, h,
13436 &unresolved_reloc,
13437 &error_message);
13438 }
0945cdfd
DJ		 13439
13440 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13441 because such sections are not SEC_ALLOC and thus ld.so will
13442 not process them. */
13443 if (unresolved_reloc
99059e56
RM		 13444 && !((input_section->flags & SEC_DEBUGGING) != 0
13445 && h->def_dynamic)
1d5316ab
AM		 13446 && _bfd_elf_section_offset (output_bfd, info, input_section,
13447 rel->r_offset) != (bfd_vma) -1)
0945cdfd 13448 {
4eca0228 13449 _bfd_error_handler
695344c0 13450 /* xgettext:c-format */
2dcf00ce
AM		 13451 (_("%pB(%pA+%#" PRIx64 "): "
13452 "unresolvable %s relocation against symbol `%s'"),
843fe662
L		 13453 input_bfd,
13454 input_section,
2dcf00ce 13455 (uint64_t) rel->r_offset,
843fe662
L		 13456 howto->name,
13457 h->root.root.string);
0945cdfd
DJ		 13458 return FALSE;
13459 }
252b5132
RH		 13460
13461 if (r != bfd_reloc_ok)
13462 {
252b5132
RH		 13463 switch (r)
13464 {
13465 case bfd_reloc_overflow:
cf919dfd
PB		 13466 /* If the overflowing reloc was to an undefined symbol,
13467 we have already printed one error message and there
13468 is no point complaining again. */
1a72702b
AM		 13469 if (!h || h->root.type != bfd_link_hash_undefined)
13470 (*info->callbacks->reloc_overflow)
13471 (info, (h ? &h->root : NULL), name, howto->name,
13472 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13473 break;
13474
13475 case bfd_reloc_undefined:
1a72702b
AM		 13476 (*info->callbacks->undefined_symbol)
13477 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 13478 break;
13479
13480 case bfd_reloc_outofrange:
f2a9dd69 13481 error_message = _("out of range");
252b5132
RH		 13482 goto common_error;
13483
13484 case bfd_reloc_notsupported:
f2a9dd69 13485 error_message = _("unsupported relocation");
252b5132
RH		 13486 goto common_error;
13487
13488 case bfd_reloc_dangerous:
f2a9dd69 13489 /* error_message should already be set. */
252b5132
RH		 13490 goto common_error;
13491
13492 default:
f2a9dd69 13493 error_message = _("unknown error");
8029a119 13494 /* Fall through. */
252b5132
RH		 13495
13496 common_error:
f2a9dd69 13497 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 13498 (*info->callbacks->reloc_dangerous)
13499 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13500 break;
13501 }
13502 }
13503 }
13504
b34976b6 13505 return TRUE;
252b5132
RH		 13506}
13507
91d6fa6a 13508/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 13509 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 13510 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 13511 maintaining that condition). */
13512
13513static void
13514add_unwind_table_edit (arm_unwind_table_edit **head,
13515 arm_unwind_table_edit **tail,
13516 arm_unwind_edit_type type,
13517 asection *linked_section,
91d6fa6a 13518 unsigned int tindex)
2468f9c9 13519{
21d799b5
NC		 13520 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
13521 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 13522
2468f9c9
PB		 13523 new_edit->type = type;
13524 new_edit->linked_section = linked_section;
91d6fa6a 13525 new_edit->index = tindex;
b38cadfb 13526
91d6fa6a 13527 if (tindex > 0)
2468f9c9
PB		 13528 {
13529 new_edit->next = NULL;
13530
13531 if (*tail)
13532 (*tail)->next = new_edit;
13533
13534 (*tail) = new_edit;
13535
13536 if (!*head)
13537 (*head) = new_edit;
13538 }
13539 else
13540 {
13541 new_edit->next = *head;
13542
13543 if (!*tail)
13544 *tail = new_edit;
13545
13546 *head = new_edit;
13547 }
13548}
13549
13550static _arm_elf_section_data *get_arm_elf_section_data (asection *);
13551
13552/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13553static void
13554adjust_exidx_size(asection *exidx_sec, int adjust)
13555{
13556 asection *out_sec;
13557
13558 if (!exidx_sec->rawsize)
13559 exidx_sec->rawsize = exidx_sec->size;
13560
fd361982 13561 bfd_set_section_size (exidx_sec, exidx_sec->size + adjust);
2468f9c9
PB		 13562 out_sec = exidx_sec->output_section;
13563 /* Adjust size of output section. */
fd361982 13564 bfd_set_section_size (out_sec, out_sec->size +adjust);
2468f9c9
PB		 13565}
13566
13567/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13568static void
13569insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
13570{
13571 struct _arm_elf_section_data *exidx_arm_data;
13572
13573 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13574 add_unwind_table_edit (
13575 &exidx_arm_data->u.exidx.unwind_edit_list,
13576 &exidx_arm_data->u.exidx.unwind_edit_tail,
13577 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
13578
491d01d3
YU		 13579 exidx_arm_data->additional_reloc_count++;
13580
2468f9c9
PB		 13581 adjust_exidx_size(exidx_sec, 8);
13582}
13583
13584/* Scan .ARM.exidx tables, and create a list describing edits which should be
13585 made to those tables, such that:
b38cadfb 13586
2468f9c9
PB		 13587 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13588 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 13589 codes which have been inlined into the index).
2468f9c9 13590
85fdf906
AH		 13591 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13592
2468f9c9 13593 The edits are applied when the tables are written
b38cadfb 13594 (in elf32_arm_write_section). */
2468f9c9
PB		 13595
13596bfd_boolean
13597elf32_arm_fix_exidx_coverage (asection **text_section_order,
13598 unsigned int num_text_sections,
85fdf906
AH		 13599 struct bfd_link_info *info,
13600 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 13601{
13602 bfd *inp;
13603 unsigned int last_second_word = 0, i;
13604 asection *last_exidx_sec = NULL;
13605 asection *last_text_sec = NULL;
13606 int last_unwind_type = -1;
13607
13608 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13609 text sections. */
c72f2fb2 13610 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 13611 {
13612 asection *sec;
b38cadfb 13613
2468f9c9 13614 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 13615 {
2468f9c9
PB		 13616 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
13617 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 13618
dec9d5df 13619 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 13620 continue;
b38cadfb 13621
2468f9c9
PB		 13622 if (elf_sec->linked_to)
13623 {
13624 Elf_Internal_Shdr *linked_hdr
99059e56 13625 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 13626 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 13627 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 13628
13629 if (linked_sec_arm_data == NULL)
99059e56 13630 continue;
2468f9c9
PB		 13631
13632 /* Link this .ARM.exidx section back from the text section it
99059e56 13633 describes. */
2468f9c9
PB		 13634 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
13635 }
13636 }
13637 }
13638
13639 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13640 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 13641 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 13642
13643 for (i = 0; i < num_text_sections; i++)
13644 {
13645 asection *sec = text_section_order[i];
13646 asection *exidx_sec;
13647 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
13648 struct _arm_elf_section_data *exidx_arm_data;
13649 bfd_byte *contents = NULL;
13650 int deleted_exidx_bytes = 0;
13651 bfd_vma j;
13652 arm_unwind_table_edit *unwind_edit_head = NULL;
13653 arm_unwind_table_edit *unwind_edit_tail = NULL;
13654 Elf_Internal_Shdr *hdr;
13655 bfd *ibfd;
13656
13657 if (arm_data == NULL)
99059e56 13658 continue;
2468f9c9
PB		 13659
13660 exidx_sec = arm_data->u.text.arm_exidx_sec;
13661 if (exidx_sec == NULL)
13662 {
13663 /* Section has no unwind data. */
13664 if (last_unwind_type == 0 || !last_exidx_sec)
13665 continue;
13666
13667 /* Ignore zero sized sections. */
13668 if (sec->size == 0)
13669 continue;
13670
13671 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13672 last_unwind_type = 0;
13673 continue;
13674 }
13675
22a8f80e
PB		 13676 /* Skip /DISCARD/ sections. */
13677 if (bfd_is_abs_section (exidx_sec->output_section))
13678 continue;
13679
2468f9c9
PB		 13680 hdr = &elf_section_data (exidx_sec)->this_hdr;
13681 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 13682 continue;
b38cadfb 13683
2468f9c9
PB		 13684 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13685 if (exidx_arm_data == NULL)
99059e56 13686 continue;
b38cadfb 13687
2468f9c9 13688 ibfd = exidx_sec->owner;
b38cadfb 13689
2468f9c9
PB		 13690 if (hdr->contents != NULL)
13691 contents = hdr->contents;
13692 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
13693 /* An error? */
13694 continue;
13695
ac06903d
YU		 13696 if (last_unwind_type > 0)
13697 {
13698 unsigned int first_word = bfd_get_32 (ibfd, contents);
13699 /* Add cantunwind if first unwind item does not match section
13700 start. */
13701 if (first_word != sec->vma)
13702 {
13703 insert_cantunwind_after (last_text_sec, last_exidx_sec);
13704 last_unwind_type = 0;
13705 }
13706 }
13707
2468f9c9
PB		 13708 for (j = 0; j < hdr->sh_size; j += 8)
13709 {
13710 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
13711 int unwind_type;
13712 int elide = 0;
13713
13714 /* An EXIDX_CANTUNWIND entry. */
13715 if (second_word == 1)
13716 {
13717 if (last_unwind_type == 0)
13718 elide = 1;
13719 unwind_type = 0;
13720 }
13721 /* Inlined unwinding data. Merge if equal to previous. */
13722 else if ((second_word & 0x80000000) != 0)
13723 {
85fdf906
AH		 13724 if (merge_exidx_entries
13725 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 13726 elide = 1;
13727 unwind_type = 1;
13728 last_second_word = second_word;
13729 }
13730 /* Normal table entry. In theory we could merge these too,
13731 but duplicate entries are likely to be much less common. */
13732 else
13733 unwind_type = 2;
13734
491d01d3 13735 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 13736 {
13737 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
13738 DELETE_EXIDX_ENTRY, NULL, j / 8);
13739
13740 deleted_exidx_bytes += 8;
13741 }
13742
13743 last_unwind_type = unwind_type;
13744 }
13745
13746 /* Free contents if we allocated it ourselves. */
13747 if (contents != hdr->contents)
99059e56 13748 free (contents);
2468f9c9
PB		 13749
13750 /* Record edits to be applied later (in elf32_arm_write_section). */
13751 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
13752 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 13753
2468f9c9
PB		 13754 if (deleted_exidx_bytes > 0)
13755 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
13756
13757 last_exidx_sec = exidx_sec;
13758 last_text_sec = sec;
13759 }
13760
13761 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 13762 if (!bfd_link_relocatable (info) && last_exidx_sec
13763 && last_unwind_type != 0)
2468f9c9
PB		 13764 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13765
13766 return TRUE;
13767}
13768
3e6b1042
DJ		 13769static bfd_boolean
13770elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
13771 bfd *ibfd, const char *name)
13772{
13773 asection *sec, *osec;
13774
3d4d4302 13775 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 13776 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
13777 return TRUE;
13778
13779 osec = sec->output_section;
13780 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
13781 return TRUE;
13782
13783 if (! bfd_set_section_contents (obfd, osec, sec->contents,
13784 sec->output_offset, sec->size))
13785 return FALSE;
13786
13787 return TRUE;
13788}
13789
13790static bfd_boolean
13791elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
13792{
13793 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 13794 asection *sec, *osec;
3e6b1042 13795
4dfe6ac6
NC		 13796 if (globals == NULL)
13797 return FALSE;
13798
3e6b1042
DJ		 13799 /* Invoke the regular ELF backend linker to do all the work. */
13800 if (!bfd_elf_final_link (abfd, info))
13801 return FALSE;
13802
fe33d2fa
CL		 13803 /* Process stub sections (eg BE8 encoding, ...). */
13804 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 13805 unsigned int i;
cdb21a0a
NS		 13806 for (i=0; i<htab->top_id; i++)
13807 {
13808 sec = htab->stub_group[i].stub_sec;
13809 /* Only process it once, in its link_sec slot. */
13810 if (sec && i == htab->stub_group[i].link_sec->id)
13811 {
13812 osec = sec->output_section;
13813 elf32_arm_write_section (abfd, info, sec, sec->contents);
13814 if (! bfd_set_section_contents (abfd, osec, sec->contents,
13815 sec->output_offset, sec->size))
13816 return FALSE;
13817 }
fe33d2fa 13818 }
fe33d2fa 13819
3e6b1042
DJ		 13820 /* Write out any glue sections now that we have created all the
13821 stubs. */
13822 if (globals->bfd_of_glue_owner != NULL)
13823 {
13824 if (! elf32_arm_output_glue_section (info, abfd,
13825 globals->bfd_of_glue_owner,
13826 ARM2THUMB_GLUE_SECTION_NAME))
13827 return FALSE;
13828
13829 if (! elf32_arm_output_glue_section (info, abfd,
13830 globals->bfd_of_glue_owner,
13831 THUMB2ARM_GLUE_SECTION_NAME))
13832 return FALSE;
13833
13834 if (! elf32_arm_output_glue_section (info, abfd,
13835 globals->bfd_of_glue_owner,
13836 VFP11_ERRATUM_VENEER_SECTION_NAME))
13837 return FALSE;
13838
a504d23a
LA		 13839 if (! elf32_arm_output_glue_section (info, abfd,
13840 globals->bfd_of_glue_owner,
13841 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13842 return FALSE;
13843
3e6b1042
DJ		 13844 if (! elf32_arm_output_glue_section (info, abfd,
13845 globals->bfd_of_glue_owner,
13846 ARM_BX_GLUE_SECTION_NAME))
13847 return FALSE;
13848 }
13849
13850 return TRUE;
13851}
13852
5968a7b8
NC		 13853/* Return a best guess for the machine number based on the attributes. */
13854
13855static unsigned int
13856bfd_arm_get_mach_from_attributes (bfd * abfd)
13857{
13858 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
13859
13860 switch (arch)
13861 {
c0c468d5 13862 case TAG_CPU_ARCH_PRE_V4: return bfd_mach_arm_3M;
5968a7b8
NC		 13863 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
13864 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
13865 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
13866
13867 case TAG_CPU_ARCH_V5TE:
13868 {
13869 char * name;
13870
13871 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
13872 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
13873
13874 if (name)
13875 {
13876 if (strcmp (name, "IWMMXT2") == 0)
13877 return bfd_mach_arm_iWMMXt2;
13878
13879 if (strcmp (name, "IWMMXT") == 0)
6034aab8 13880 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 13881
13882 if (strcmp (name, "XSCALE") == 0)
13883 {
13884 int wmmx;
13885
13886 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
13887 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
13888 switch (wmmx)
13889 {
13890 case 1: return bfd_mach_arm_iWMMXt;
13891 case 2: return bfd_mach_arm_iWMMXt2;
13892 default: return bfd_mach_arm_XScale;
13893 }
13894 }
5968a7b8
NC		 13895 }
13896
13897 return bfd_mach_arm_5TE;
13898 }
13899
c0c468d5
TP		 13900 case TAG_CPU_ARCH_V5TEJ:
13901 return bfd_mach_arm_5TEJ;
13902 case TAG_CPU_ARCH_V6:
13903 return bfd_mach_arm_6;
13904 case TAG_CPU_ARCH_V6KZ:
13905 return bfd_mach_arm_6KZ;
13906 case TAG_CPU_ARCH_V6T2:
13907 return bfd_mach_arm_6T2;
13908 case TAG_CPU_ARCH_V6K:
13909 return bfd_mach_arm_6K;
13910 case TAG_CPU_ARCH_V7:
13911 return bfd_mach_arm_7;
13912 case TAG_CPU_ARCH_V6_M:
13913 return bfd_mach_arm_6M;
13914 case TAG_CPU_ARCH_V6S_M:
13915 return bfd_mach_arm_6SM;
13916 case TAG_CPU_ARCH_V7E_M:
13917 return bfd_mach_arm_7EM;
13918 case TAG_CPU_ARCH_V8:
13919 return bfd_mach_arm_8;
13920 case TAG_CPU_ARCH_V8R:
13921 return bfd_mach_arm_8R;
13922 case TAG_CPU_ARCH_V8M_BASE:
13923 return bfd_mach_arm_8M_BASE;
13924 case TAG_CPU_ARCH_V8M_MAIN:
13925 return bfd_mach_arm_8M_MAIN;
031254f2
AV		 13926 case TAG_CPU_ARCH_V8_1M_MAIN:
13927 return bfd_mach_arm_8_1M_MAIN;
c0c468d5 13928
5968a7b8 13929 default:
c0c468d5
TP		 13930 /* Force entry to be added for any new known Tag_CPU_arch value. */
13931 BFD_ASSERT (arch > MAX_TAG_CPU_ARCH);
13932
13933 /* Unknown Tag_CPU_arch value. */
5968a7b8
NC		 13934 return bfd_mach_arm_unknown;
13935 }
13936}
13937
c178919b
NC		 13938/* Set the right machine number. */
13939
13940static bfd_boolean
57e8b36a 13941elf32_arm_object_p (bfd *abfd)
c178919b 13942{
5a6c6817 13943 unsigned int mach;
57e8b36a 13944
5a6c6817 13945 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 13946
5968a7b8
NC		 13947 if (mach == bfd_mach_arm_unknown)
13948 {
13949 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13950 mach = bfd_mach_arm_ep9312;
13951 else
13952 mach = bfd_arm_get_mach_from_attributes (abfd);
13953 }
c178919b 13954
5968a7b8 13955 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13956 return TRUE;
13957}
13958
fc830a83 13959/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13960
b34976b6 13961static bfd_boolean
57e8b36a 13962elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13963{
13964 if (elf_flags_init (abfd)
13965 && elf_elfheader (abfd)->e_flags != flags)
13966 {
fc830a83
NC		 13967 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13968 {
fd2ec330 13969 if (flags & EF_ARM_INTERWORK)
4eca0228 13970 _bfd_error_handler
90b6238f 13971 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
d003868e 13972 abfd);
fc830a83 13973 else
d003868e 13974 _bfd_error_handler
90b6238f 13975 (_("warning: clearing the interworking flag of %pB due to outside request"),
d003868e 13976 abfd);
fc830a83 13977 }
252b5132
RH		 13978 }
13979 else
13980 {
13981 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13982 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13983 }
13984
b34976b6 13985 return TRUE;
252b5132
RH		 13986}
13987
fc830a83 13988/* Copy backend specific data from one object module to another. */
9b485d32 13989
b34976b6 13990static bfd_boolean
57e8b36a 13991elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13992{
13993 flagword in_flags;
13994 flagword out_flags;
13995
0ffa91dd 13996 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13997 return TRUE;
252b5132 13998
fc830a83 13999 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 14000 out_flags = elf_elfheader (obfd)->e_flags;
14001
fc830a83
NC		 14002 if (elf_flags_init (obfd)
14003 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
14004 && in_flags != out_flags)
252b5132 14005 {
252b5132 14006 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 14007 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 14008 return FALSE;
252b5132
RH		 14009
14010 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 14011 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 14012 return FALSE;
252b5132
RH		 14013
14014 /* If the src and dest have different interworking flags
99059e56 14015 then turn off the interworking bit. */
fd2ec330 14016 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 14017 {
fd2ec330 14018 if (out_flags & EF_ARM_INTERWORK)
d003868e 14019 _bfd_error_handler
90b6238f 14020 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
d003868e 14021 obfd, ibfd);
252b5132 14022
fd2ec330 14023 in_flags &= ~EF_ARM_INTERWORK;
252b5132 14024 }
1006ba19
PB		 14025
14026 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 14027 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
14028 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 14029 }
14030
14031 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 14032 elf_flags_init (obfd) = TRUE;
252b5132 14033
e2349352 14034 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 14035}
14036
14037/* Values for Tag_ABI_PCS_R9_use. */
14038enum
14039{
14040 AEABI_R9_V6,
14041 AEABI_R9_SB,
14042 AEABI_R9_TLS,
14043 AEABI_R9_unused
14044};
14045
14046/* Values for Tag_ABI_PCS_RW_data. */
14047enum
14048{
14049 AEABI_PCS_RW_data_absolute,
14050 AEABI_PCS_RW_data_PCrel,
14051 AEABI_PCS_RW_data_SBrel,
14052 AEABI_PCS_RW_data_unused
14053};
14054
14055/* Values for Tag_ABI_enum_size. */
14056enum
14057{
14058 AEABI_enum_unused,
14059 AEABI_enum_short,
14060 AEABI_enum_wide,
14061 AEABI_enum_forced_wide
14062};
14063
104d59d1
JM		 14064/* Determine whether an object attribute tag takes an integer, a
14065 string or both. */
906e58ca 14066
104d59d1
JM		 14067static int
14068elf32_arm_obj_attrs_arg_type (int tag)
14069{
14070 if (tag == Tag_compatibility)
3483fe2e 14071 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 14072 else if (tag == Tag_nodefaults)
3483fe2e
AS		 14073 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
14074 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
14075 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 14076 else if (tag < 32)
3483fe2e 14077 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 14078 else
3483fe2e 14079 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 14080}
14081
5aa6ff7c
AS		 14082/* The ABI defines that Tag_conformance should be emitted first, and that
14083 Tag_nodefaults should be second (if either is defined). This sets those
14084 two positions, and bumps up the position of all the remaining tags to
14085 compensate. */
14086static int
14087elf32_arm_obj_attrs_order (int num)
14088{
3de4a297 14089 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 14090 return Tag_conformance;
3de4a297 14091 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 14092 return Tag_nodefaults;
14093 if ((num - 2) < Tag_nodefaults)
14094 return num - 2;
14095 if ((num - 1) < Tag_conformance)
14096 return num - 1;
14097 return num;
14098}
14099
e8b36cd1
JM		 14100/* Attribute numbers >=64 (mod 128) can be safely ignored. */
14101static bfd_boolean
14102elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
14103{
14104 if ((tag & 127) < 64)
14105 {
14106 _bfd_error_handler
90b6238f 14107 (_("%pB: unknown mandatory EABI object attribute %d"),
e8b36cd1
JM		 14108 abfd, tag);
14109 bfd_set_error (bfd_error_bad_value);
14110 return FALSE;
14111 }
14112 else
14113 {
14114 _bfd_error_handler
90b6238f 14115 (_("warning: %pB: unknown EABI object attribute %d"),
e8b36cd1
JM		 14116 abfd, tag);
14117 return TRUE;
14118 }
14119}
14120
91e22acd
AS		 14121/* Read the architecture from the Tag_also_compatible_with attribute, if any.
14122 Returns -1 if no architecture could be read. */
14123
14124static int
14125get_secondary_compatible_arch (bfd *abfd)
14126{
14127 obj_attribute *attr =
14128 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
14129
14130 /* Note: the tag and its argument below are uleb128 values, though
14131 currently-defined values fit in one byte for each. */
14132 if (attr->s
14133 && attr->s[0] == Tag_CPU_arch
14134 && (attr->s[1] & 128) != 128
14135 && attr->s[2] == 0)
14136 return attr->s[1];
14137
14138 /* This tag is "safely ignorable", so don't complain if it looks funny. */
14139 return -1;
14140}
14141
14142/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
14143 The tag is removed if ARCH is -1. */
14144
8e79c3df 14145static void
91e22acd 14146set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 14147{
91e22acd
AS		 14148 obj_attribute *attr =
14149 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 14150
91e22acd
AS		 14151 if (arch == -1)
14152 {
14153 attr->s = NULL;
14154 return;
8e79c3df 14155 }
91e22acd
AS		 14156
14157 /* Note: the tag and its argument below are uleb128 values, though
14158 currently-defined values fit in one byte for each. */
14159 if (!attr->s)
21d799b5 14160 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 14161 attr->s[0] = Tag_CPU_arch;
14162 attr->s[1] = arch;
14163 attr->s[2] = '\0';
8e79c3df
CM		 14164}
14165
91e22acd
AS		 14166/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
14167 into account. */
14168
14169static int
14170tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
14171 int newtag, int secondary_compat)
8e79c3df 14172{
91e22acd
AS		 14173#define T(X) TAG_CPU_ARCH_##X
14174 int tagl, tagh, result;
14175 const int v6t2[] =
14176 {
14177 T(V6T2), /* PRE_V4. */
14178 T(V6T2), /* V4. */
14179 T(V6T2), /* V4T. */
14180 T(V6T2), /* V5T. */
14181 T(V6T2), /* V5TE. */
14182 T(V6T2), /* V5TEJ. */
14183 T(V6T2), /* V6. */
14184 T(V7), /* V6KZ. */
14185 T(V6T2) /* V6T2. */
14186 };
14187 const int v6k[] =
14188 {
14189 T(V6K), /* PRE_V4. */
14190 T(V6K), /* V4. */
14191 T(V6K), /* V4T. */
14192 T(V6K), /* V5T. */
14193 T(V6K), /* V5TE. */
14194 T(V6K), /* V5TEJ. */
14195 T(V6K), /* V6. */
14196 T(V6KZ), /* V6KZ. */
14197 T(V7), /* V6T2. */
14198 T(V6K) /* V6K. */
14199 };
14200 const int v7[] =
14201 {
14202 T(V7), /* PRE_V4. */
14203 T(V7), /* V4. */
14204 T(V7), /* V4T. */
14205 T(V7), /* V5T. */
14206 T(V7), /* V5TE. */
14207 T(V7), /* V5TEJ. */
14208 T(V7), /* V6. */
14209 T(V7), /* V6KZ. */
14210 T(V7), /* V6T2. */
14211 T(V7), /* V6K. */
14212 T(V7) /* V7. */
14213 };
14214 const int v6_m[] =
14215 {
07d6d2b8
AM		 14216 -1, /* PRE_V4. */
14217 -1, /* V4. */
91e22acd
AS		 14218 T(V6K), /* V4T. */
14219 T(V6K), /* V5T. */
14220 T(V6K), /* V5TE. */
14221 T(V6K), /* V5TEJ. */
14222 T(V6K), /* V6. */
14223 T(V6KZ), /* V6KZ. */
14224 T(V7), /* V6T2. */
14225 T(V6K), /* V6K. */
14226 T(V7), /* V7. */
14227 T(V6_M) /* V6_M. */
14228 };
14229 const int v6s_m[] =
14230 {
07d6d2b8
AM		 14231 -1, /* PRE_V4. */
14232 -1, /* V4. */
91e22acd
AS		 14233 T(V6K), /* V4T. */
14234 T(V6K), /* V5T. */
14235 T(V6K), /* V5TE. */
14236 T(V6K), /* V5TEJ. */
14237 T(V6K), /* V6. */
14238 T(V6KZ), /* V6KZ. */
14239 T(V7), /* V6T2. */
14240 T(V6K), /* V6K. */
14241 T(V7), /* V7. */
14242 T(V6S_M), /* V6_M. */
14243 T(V6S_M) /* V6S_M. */
14244 };
9e3c6df6
PB		 14245 const int v7e_m[] =
14246 {
07d6d2b8
AM		 14247 -1, /* PRE_V4. */
14248 -1, /* V4. */
9e3c6df6
PB		 14249 T(V7E_M), /* V4T. */
14250 T(V7E_M), /* V5T. */
14251 T(V7E_M), /* V5TE. */
14252 T(V7E_M), /* V5TEJ. */
14253 T(V7E_M), /* V6. */
14254 T(V7E_M), /* V6KZ. */
14255 T(V7E_M), /* V6T2. */
14256 T(V7E_M), /* V6K. */
14257 T(V7E_M), /* V7. */
14258 T(V7E_M), /* V6_M. */
14259 T(V7E_M), /* V6S_M. */
14260 T(V7E_M) /* V7E_M. */
14261 };
bca38921
MGD		 14262 const int v8[] =
14263 {
14264 T(V8), /* PRE_V4. */
14265 T(V8), /* V4. */
14266 T(V8), /* V4T. */
14267 T(V8), /* V5T. */
14268 T(V8), /* V5TE. */
14269 T(V8), /* V5TEJ. */
14270 T(V8), /* V6. */
14271 T(V8), /* V6KZ. */
14272 T(V8), /* V6T2. */
14273 T(V8), /* V6K. */
14274 T(V8), /* V7. */
14275 T(V8), /* V6_M. */
14276 T(V8), /* V6S_M. */
14277 T(V8), /* V7E_M. */
14278 T(V8) /* V8. */
14279 };
bff0500d
TP		 14280 const int v8r[] =
14281 {
14282 T(V8R), /* PRE_V4. */
14283 T(V8R), /* V4. */
14284 T(V8R), /* V4T. */
14285 T(V8R), /* V5T. */
14286 T(V8R), /* V5TE. */
14287 T(V8R), /* V5TEJ. */
14288 T(V8R), /* V6. */
14289 T(V8R), /* V6KZ. */
14290 T(V8R), /* V6T2. */
14291 T(V8R), /* V6K. */
14292 T(V8R), /* V7. */
14293 T(V8R), /* V6_M. */
14294 T(V8R), /* V6S_M. */
14295 T(V8R), /* V7E_M. */
14296 T(V8), /* V8. */
14297 T(V8R), /* V8R. */
14298 };
2fd158eb
TP		 14299 const int v8m_baseline[] =
14300 {
14301 -1, /* PRE_V4. */
14302 -1, /* V4. */
14303 -1, /* V4T. */
14304 -1, /* V5T. */
14305 -1, /* V5TE. */
14306 -1, /* V5TEJ. */
14307 -1, /* V6. */
14308 -1, /* V6KZ. */
14309 -1, /* V6T2. */
14310 -1, /* V6K. */
14311 -1, /* V7. */
14312 T(V8M_BASE), /* V6_M. */
14313 T(V8M_BASE), /* V6S_M. */
14314 -1, /* V7E_M. */
14315 -1, /* V8. */
bff0500d 14316 -1, /* V8R. */
2fd158eb
TP		 14317 T(V8M_BASE) /* V8-M BASELINE. */
14318 };
14319 const int v8m_mainline[] =
14320 {
14321 -1, /* PRE_V4. */
14322 -1, /* V4. */
14323 -1, /* V4T. */
14324 -1, /* V5T. */
14325 -1, /* V5TE. */
14326 -1, /* V5TEJ. */
14327 -1, /* V6. */
14328 -1, /* V6KZ. */
14329 -1, /* V6T2. */
14330 -1, /* V6K. */
14331 T(V8M_MAIN), /* V7. */
14332 T(V8M_MAIN), /* V6_M. */
14333 T(V8M_MAIN), /* V6S_M. */
14334 T(V8M_MAIN), /* V7E_M. */
14335 -1, /* V8. */
bff0500d 14336 -1, /* V8R. */
2fd158eb
TP		 14337 T(V8M_MAIN), /* V8-M BASELINE. */
14338 T(V8M_MAIN) /* V8-M MAINLINE. */
14339 };
031254f2
AV		 14340 const int v8_1m_mainline[] =
14341 {
14342 -1, /* PRE_V4. */
14343 -1, /* V4. */
14344 -1, /* V4T. */
14345 -1, /* V5T. */
14346 -1, /* V5TE. */
14347 -1, /* V5TEJ. */
14348 -1, /* V6. */
14349 -1, /* V6KZ. */
14350 -1, /* V6T2. */
14351 -1, /* V6K. */
14352 T(V8_1M_MAIN), /* V7. */
14353 T(V8_1M_MAIN), /* V6_M. */
14354 T(V8_1M_MAIN), /* V6S_M. */
14355 T(V8_1M_MAIN), /* V7E_M. */
14356 -1, /* V8. */
14357 -1, /* V8R. */
14358 T(V8_1M_MAIN), /* V8-M BASELINE. */
14359 T(V8_1M_MAIN), /* V8-M MAINLINE. */
14360 -1, /* Unused (18). */
14361 -1, /* Unused (19). */
14362 -1, /* Unused (20). */
14363 T(V8_1M_MAIN) /* V8.1-M MAINLINE. */
14364 };
91e22acd
AS		 14365 const int v4t_plus_v6_m[] =
14366 {
14367 -1, /* PRE_V4. */
14368 -1, /* V4. */
14369 T(V4T), /* V4T. */
14370 T(V5T), /* V5T. */
14371 T(V5TE), /* V5TE. */
14372 T(V5TEJ), /* V5TEJ. */
14373 T(V6), /* V6. */
14374 T(V6KZ), /* V6KZ. */
14375 T(V6T2), /* V6T2. */
14376 T(V6K), /* V6K. */
14377 T(V7), /* V7. */
14378 T(V6_M), /* V6_M. */
14379 T(V6S_M), /* V6S_M. */
9e3c6df6 14380 T(V7E_M), /* V7E_M. */
bca38921 14381 T(V8), /* V8. */
bff0500d 14382 -1, /* V8R. */
2fd158eb
TP		 14383 T(V8M_BASE), /* V8-M BASELINE. */
14384 T(V8M_MAIN), /* V8-M MAINLINE. */
031254f2
AV		 14385 -1, /* Unused (18). */
14386 -1, /* Unused (19). */
14387 -1, /* Unused (20). */
14388 T(V8_1M_MAIN), /* V8.1-M MAINLINE. */
91e22acd
AS		 14389 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
14390 };
14391 const int *comb[] =
14392 {
14393 v6t2,
14394 v6k,
14395 v7,
14396 v6_m,
14397 v6s_m,
9e3c6df6 14398 v7e_m,
bca38921 14399 v8,
bff0500d 14400 v8r,
2fd158eb
TP		 14401 v8m_baseline,
14402 v8m_mainline,
031254f2
AV		 14403 NULL,
14404 NULL,
14405 NULL,
14406 v8_1m_mainline,
91e22acd
AS		 14407 /* Pseudo-architecture. */
14408 v4t_plus_v6_m
14409 };
14410
14411 /* Check we've not got a higher architecture than we know about. */
14412
9e3c6df6 14413 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 14414 {
90b6238f 14415 _bfd_error_handler (_("error: %pB: unknown CPU architecture"), ibfd);
91e22acd
AS		 14416 return -1;
14417 }
14418
14419 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14420
14421 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
14422 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
14423 oldtag = T(V4T_PLUS_V6_M);
14424
14425 /* And override the new tag if we have a Tag_also_compatible_with on the
14426 input. */
14427
14428 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
14429 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
14430 newtag = T(V4T_PLUS_V6_M);
14431
14432 tagl = (oldtag < newtag) ? oldtag : newtag;
14433 result = tagh = (oldtag > newtag) ? oldtag : newtag;
14434
14435 /* Architectures before V6KZ add features monotonically. */
14436 if (tagh <= TAG_CPU_ARCH_V6KZ)
14437 return result;
14438
4ed7ed8d 14439 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 14440
14441 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14442 as the canonical version. */
14443 if (result == T(V4T_PLUS_V6_M))
14444 {
14445 result = T(V4T);
14446 *secondary_compat_out = T(V6_M);
14447 }
14448 else
14449 *secondary_compat_out = -1;
14450
14451 if (result == -1)
14452 {
90b6238f 14453 _bfd_error_handler (_("error: %pB: conflicting CPU architectures %d/%d"),
91e22acd
AS		 14454 ibfd, oldtag, newtag);
14455 return -1;
14456 }
14457
14458 return result;
14459#undef T
8e79c3df
CM		 14460}
14461
ac56ee8f
MGD		 14462/* Query attributes object to see if integer divide instructions may be
14463 present in an object. */
14464static bfd_boolean
14465elf32_arm_attributes_accept_div (const obj_attribute *attr)
14466{
14467 int arch = attr[Tag_CPU_arch].i;
14468 int profile = attr[Tag_CPU_arch_profile].i;
14469
14470 switch (attr[Tag_DIV_use].i)
14471 {
14472 case 0:
14473 /* Integer divide allowed if instruction contained in archetecture. */
14474 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
14475 return TRUE;
14476 else if (arch >= TAG_CPU_ARCH_V7E_M)
14477 return TRUE;
14478 else
14479 return FALSE;
14480
14481 case 1:
14482 /* Integer divide explicitly prohibited. */
14483 return FALSE;
14484
14485 default:
14486 /* Unrecognised case - treat as allowing divide everywhere. */
14487 case 2:
14488 /* Integer divide allowed in ARM state. */
14489 return TRUE;
14490 }
14491}
14492
14493/* Query attributes object to see if integer divide instructions are
14494 forbidden to be in the object. This is not the inverse of
14495 elf32_arm_attributes_accept_div. */
14496static bfd_boolean
14497elf32_arm_attributes_forbid_div (const obj_attribute *attr)
14498{
14499 return attr[Tag_DIV_use].i == 1;
14500}
14501
ee065d83
PB		 14502/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14503 are conflicting attributes. */
906e58ca 14504
ee065d83 14505static bfd_boolean
50e03d47 14506elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 14507{
50e03d47 14508 bfd *obfd = info->output_bfd;
104d59d1
JM		 14509 obj_attribute *in_attr;
14510 obj_attribute *out_attr;
ee065d83
PB		 14511 /* Some tags have 0 = don't care, 1 = strong requirement,
14512 2 = weak requirement. */
91e22acd 14513 static const int order_021[3] = {0, 2, 1};
ee065d83 14514 int i;
91e22acd 14515 bfd_boolean result = TRUE;
9274e9de 14516 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 14517
3e6b1042
DJ		 14518 /* Skip the linker stubs file. This preserves previous behavior
14519 of accepting unknown attributes in the first input file - but
14520 is that a bug? */
14521 if (ibfd->flags & BFD_LINKER_CREATED)
14522 return TRUE;
14523
9274e9de
TG		 14524 /* Skip any input that hasn't attribute section.
14525 This enables to link object files without attribute section with
14526 any others. */
14527 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
14528 return TRUE;
14529
104d59d1 14530 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 14531 {
14532 /* This is the first object. Copy the attributes. */
104d59d1 14533 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 14534
cd21e546
MGD		 14535 out_attr = elf_known_obj_attributes_proc (obfd);
14536
004ae526
PB		 14537 /* Use the Tag_null value to indicate the attributes have been
14538 initialized. */
cd21e546 14539 out_attr[0].i = 1;
004ae526 14540
cd21e546
MGD		 14541 /* We do not output objects with Tag_MPextension_use_legacy - we move
14542 the attribute's value to Tag_MPextension_use. */
14543 if (out_attr[Tag_MPextension_use_legacy].i != 0)
14544 {
14545 if (out_attr[Tag_MPextension_use].i != 0
14546 && out_attr[Tag_MPextension_use_legacy].i
99059e56 14547 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 14548 {
14549 _bfd_error_handler
871b3ab2 14550 (_("Error: %pB has both the current and legacy "
cd21e546
MGD		 14551 "Tag_MPextension_use attributes"), ibfd);
14552 result = FALSE;
14553 }
14554
14555 out_attr[Tag_MPextension_use] =
14556 out_attr[Tag_MPextension_use_legacy];
14557 out_attr[Tag_MPextension_use_legacy].type = 0;
14558 out_attr[Tag_MPextension_use_legacy].i = 0;
14559 }
14560
14561 return result;
ee065d83
PB		 14562 }
14563
104d59d1
JM		 14564 in_attr = elf_known_obj_attributes_proc (ibfd);
14565 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 14566 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14567 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
14568 {
5c294fee
TG		 14569 /* Ignore mismatches if the object doesn't use floating point or is
14570 floating point ABI independent. */
14571 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
14572 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14573 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 14574 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 14575 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14576 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 14577 {
14578 _bfd_error_handler
871b3ab2 14579 (_("error: %pB uses VFP register arguments, %pB does not"),
deddc40b
NS		 14580 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
14581 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 14582 result = FALSE;
ee065d83
PB		 14583 }
14584 }
14585
3de4a297 14586 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 14587 {
14588 /* Merge this attribute with existing attributes. */
14589 switch (i)
14590 {
14591 case Tag_CPU_raw_name:
14592 case Tag_CPU_name:
6a631e86 14593 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 14594 break;
14595
14596 case Tag_ABI_optimization_goals:
14597 case Tag_ABI_FP_optimization_goals:
14598 /* Use the first value seen. */
14599 break;
14600
14601 case Tag_CPU_arch:
91e22acd
AS		 14602 {
14603 int secondary_compat = -1, secondary_compat_out = -1;
14604 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 14605 int arch_attr;
14606 static const char *name_table[] =
14607 {
91e22acd
AS		 14608 /* These aren't real CPU names, but we can't guess
14609 that from the architecture version alone. */
14610 "Pre v4",
14611 "ARM v4",
14612 "ARM v4T",
14613 "ARM v5T",
14614 "ARM v5TE",
14615 "ARM v5TEJ",
14616 "ARM v6",
14617 "ARM v6KZ",
14618 "ARM v6T2",
14619 "ARM v6K",
14620 "ARM v7",
14621 "ARM v6-M",
bca38921 14622 "ARM v6S-M",
2fd158eb
TP		 14623 "ARM v8",
14624 "",
14625 "ARM v8-M.baseline",
14626 "ARM v8-M.mainline",
91e22acd
AS		 14627 };
14628
14629 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14630 secondary_compat = get_secondary_compatible_arch (ibfd);
14631 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 14632 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
14633 &secondary_compat_out,
14634 in_attr[i].i,
14635 secondary_compat);
14636
14637 /* Return with error if failed to merge. */
14638 if (arch_attr == -1)
14639 return FALSE;
14640
14641 out_attr[i].i = arch_attr;
14642
91e22acd
AS		 14643 set_secondary_compatible_arch (obfd, secondary_compat_out);
14644
14645 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14646 if (out_attr[i].i == saved_out_attr)
14647 ; /* Leave the names alone. */
14648 else if (out_attr[i].i == in_attr[i].i)
14649 {
14650 /* The output architecture has been changed to match the
14651 input architecture. Use the input names. */
14652 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
14653 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
14654 : NULL;
14655 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
14656 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
14657 : NULL;
14658 }
14659 else
14660 {
14661 out_attr[Tag_CPU_name].s = NULL;
14662 out_attr[Tag_CPU_raw_name].s = NULL;
14663 }
14664
14665 /* If we still don't have a value for Tag_CPU_name,
14666 make one up now. Tag_CPU_raw_name remains blank. */
14667 if (out_attr[Tag_CPU_name].s == NULL
14668 && out_attr[i].i < ARRAY_SIZE (name_table))
14669 out_attr[Tag_CPU_name].s =
14670 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
14671 }
14672 break;
14673
ee065d83
PB		 14674 case Tag_ARM_ISA_use:
14675 case Tag_THUMB_ISA_use:
ee065d83 14676 case Tag_WMMX_arch:
91e22acd
AS		 14677 case Tag_Advanced_SIMD_arch:
14678 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 14679 case Tag_ABI_FP_rounding:
ee065d83
PB		 14680 case Tag_ABI_FP_exceptions:
14681 case Tag_ABI_FP_user_exceptions:
14682 case Tag_ABI_FP_number_model:
75375b3e 14683 case Tag_FP_HP_extension:
91e22acd
AS		 14684 case Tag_CPU_unaligned_access:
14685 case Tag_T2EE_use:
91e22acd 14686 case Tag_MPextension_use:
a7ad558c 14687 case Tag_MVE_arch:
ee065d83
PB		 14688 /* Use the largest value specified. */
14689 if (in_attr[i].i > out_attr[i].i)
14690 out_attr[i].i = in_attr[i].i;
14691 break;
14692
75375b3e 14693 case Tag_ABI_align_preserved:
91e22acd
AS		 14694 case Tag_ABI_PCS_RO_data:
14695 /* Use the smallest value specified. */
14696 if (in_attr[i].i < out_attr[i].i)
14697 out_attr[i].i = in_attr[i].i;
14698 break;
14699
75375b3e 14700 case Tag_ABI_align_needed:
91e22acd 14701 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 14702 && (in_attr[Tag_ABI_align_preserved].i == 0
14703 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 14704 {
91e22acd
AS		 14705 /* This error message should be enabled once all non-conformant
14706 binaries in the toolchain have had the attributes set
14707 properly.
ee065d83 14708 _bfd_error_handler
871b3ab2 14709 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
91e22acd
AS		 14710 obfd, ibfd);
14711 result = FALSE; */
ee065d83 14712 }
91e22acd
AS		 14713 /* Fall through. */
14714 case Tag_ABI_FP_denormal:
14715 case Tag_ABI_PCS_GOT_use:
14716 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14717 value if greater than 2 (for future-proofing). */
14718 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
14719 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
14720 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 14721 out_attr[i].i = in_attr[i].i;
14722 break;
91e22acd 14723
75375b3e
MGD		 14724 case Tag_Virtualization_use:
14725 /* The virtualization tag effectively stores two bits of
14726 information: the intended use of TrustZone (in bit 0), and the
14727 intended use of Virtualization (in bit 1). */
14728 if (out_attr[i].i == 0)
14729 out_attr[i].i = in_attr[i].i;
14730 else if (in_attr[i].i != 0
14731 && in_attr[i].i != out_attr[i].i)
14732 {
14733 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
14734 out_attr[i].i = 3;
14735 else
14736 {
14737 _bfd_error_handler
871b3ab2
AM		 14738 (_("error: %pB: unable to merge virtualization attributes "
14739 "with %pB"),
75375b3e
MGD		 14740 obfd, ibfd);
14741 result = FALSE;
14742 }
14743 }
14744 break;
91e22acd
AS		 14745
14746 case Tag_CPU_arch_profile:
14747 if (out_attr[i].i != in_attr[i].i)
14748 {
14749 /* 0 will merge with anything.
14750 'A' and 'S' merge to 'A'.
14751 'R' and 'S' merge to 'R'.
99059e56 14752 'M' and 'A|R|S' is an error. */
91e22acd
AS		 14753 if (out_attr[i].i == 0
14754 || (out_attr[i].i == 'S'
14755 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
14756 out_attr[i].i = in_attr[i].i;
14757 else if (in_attr[i].i == 0
14758 || (in_attr[i].i == 'S'
14759 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 14760 ; /* Do nothing. */
91e22acd
AS		 14761 else
14762 {
14763 _bfd_error_handler
90b6238f 14764 (_("error: %pB: conflicting architecture profiles %c/%c"),
91e22acd
AS		 14765 ibfd,
14766 in_attr[i].i ? in_attr[i].i : '0',
14767 out_attr[i].i ? out_attr[i].i : '0');
14768 result = FALSE;
14769 }
14770 }
14771 break;
15afaa63
TP		 14772
14773 case Tag_DSP_extension:
14774 /* No need to change output value if any of:
14775 - pre (<=) ARMv5T input architecture (do not have DSP)
14776 - M input profile not ARMv7E-M and do not have DSP. */
14777 if (in_attr[Tag_CPU_arch].i <= 3
14778 || (in_attr[Tag_CPU_arch_profile].i == 'M'
14779 && in_attr[Tag_CPU_arch].i != 13
14780 && in_attr[i].i == 0))
14781 ; /* Do nothing. */
14782 /* Output value should be 0 if DSP part of architecture, ie.
14783 - post (>=) ARMv5te architecture output
14784 - A, R or S profile output or ARMv7E-M output architecture. */
14785 else if (out_attr[Tag_CPU_arch].i >= 4
14786 && (out_attr[Tag_CPU_arch_profile].i == 'A'
14787 || out_attr[Tag_CPU_arch_profile].i == 'R'
14788 || out_attr[Tag_CPU_arch_profile].i == 'S'
14789 || out_attr[Tag_CPU_arch].i == 13))
14790 out_attr[i].i = 0;
14791 /* Otherwise, DSP instructions are added and not part of output
14792 architecture. */
14793 else
14794 out_attr[i].i = 1;
14795 break;
14796
75375b3e 14797 case Tag_FP_arch:
62f3b8c8 14798 {
4547cb56
NC		 14799 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14800 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14801 when it's 0. It might mean absence of FP hardware if
99654aaf 14802 Tag_FP_arch is zero. */
4547cb56 14803
a715796b 14804#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 14805 static const struct
14806 {
14807 int ver;
14808 int regs;
bca38921 14809 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 14810 {
14811 {0, 0},
14812 {1, 16},
14813 {2, 16},
14814 {3, 32},
14815 {3, 16},
14816 {4, 32},
bca38921 14817 {4, 16},
a715796b
TG		 14818 {8, 32},
14819 {8, 16}
62f3b8c8
PB		 14820 };
14821 int ver;
14822 int regs;
14823 int newval;
14824
4547cb56
NC		 14825 /* If the output has no requirement about FP hardware,
14826 follow the requirement of the input. */
14827 if (out_attr[i].i == 0)
14828 {
4ec192e6
RE		 14829 /* This assert is still reasonable, we shouldn't
14830 produce the suspicious build attribute
14831 combination (See below for in_attr). */
4547cb56
NC		 14832 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
14833 out_attr[i].i = in_attr[i].i;
14834 out_attr[Tag_ABI_HardFP_use].i
14835 = in_attr[Tag_ABI_HardFP_use].i;
14836 break;
14837 }
14838 /* If the input has no requirement about FP hardware, do
14839 nothing. */
14840 else if (in_attr[i].i == 0)
14841 {
4ec192e6
RE		 14842 /* We used to assert that Tag_ABI_HardFP_use was
14843 zero here, but we should never assert when
14844 consuming an object file that has suspicious
14845 build attributes. The single precision variant
14846 of 'no FP architecture' is still 'no FP
14847 architecture', so we just ignore the tag in this
14848 case. */
4547cb56
NC		 14849 break;
14850 }
14851
14852 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 14853 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 14854
14855 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14856 do nothing. */
14857 if (in_attr[Tag_ABI_HardFP_use].i == 0
14858 && out_attr[Tag_ABI_HardFP_use].i == 0)
14859 ;
14860 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 14861 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 14862 else if (in_attr[Tag_ABI_HardFP_use].i
14863 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 14864 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 14865
14866 /* Now we can handle Tag_FP_arch. */
14867
bca38921
MGD		 14868 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14869 pick the biggest. */
14870 if (in_attr[i].i >= VFP_VERSION_COUNT
14871 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 14872 {
14873 out_attr[i] = in_attr[i];
14874 break;
14875 }
14876 /* The output uses the superset of input features
14877 (ISA version) and registers. */
14878 ver = vfp_versions[in_attr[i].i].ver;
14879 if (ver < vfp_versions[out_attr[i].i].ver)
14880 ver = vfp_versions[out_attr[i].i].ver;
14881 regs = vfp_versions[in_attr[i].i].regs;
14882 if (regs < vfp_versions[out_attr[i].i].regs)
14883 regs = vfp_versions[out_attr[i].i].regs;
14884 /* This assumes all possible supersets are also a valid
99059e56 14885 options. */
bca38921 14886 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 14887 {
14888 if (regs == vfp_versions[newval].regs
14889 && ver == vfp_versions[newval].ver)
14890 break;
14891 }
14892 out_attr[i].i = newval;
14893 }
b1cc4aeb 14894 break;
ee065d83
PB		 14895 case Tag_PCS_config:
14896 if (out_attr[i].i == 0)
14897 out_attr[i].i = in_attr[i].i;
b6009aca 14898 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 14899 {
14900 /* It's sometimes ok to mix different configs, so this is only
99059e56 14901 a warning. */
ee065d83 14902 _bfd_error_handler
90b6238f 14903 (_("warning: %pB: conflicting platform configuration"), ibfd);
ee065d83
PB		 14904 }
14905 break;
14906 case Tag_ABI_PCS_R9_use:
004ae526
PB		 14907 if (in_attr[i].i != out_attr[i].i
14908 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 14909 && in_attr[i].i != AEABI_R9_unused)
14910 {
14911 _bfd_error_handler
90b6238f 14912 (_("error: %pB: conflicting use of R9"), ibfd);
91e22acd 14913 result = FALSE;
ee065d83
PB		 14914 }
14915 if (out_attr[i].i == AEABI_R9_unused)
14916 out_attr[i].i = in_attr[i].i;
14917 break;
14918 case Tag_ABI_PCS_RW_data:
14919 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
14920 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
14921 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
14922 {
14923 _bfd_error_handler
871b3ab2 14924 (_("error: %pB: SB relative addressing conflicts with use of R9"),
ee065d83 14925 ibfd);
91e22acd 14926 result = FALSE;
ee065d83
PB		 14927 }
14928 /* Use the smallest value specified. */
14929 if (in_attr[i].i < out_attr[i].i)
14930 out_attr[i].i = in_attr[i].i;
14931 break;
ee065d83 14932 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 14933 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
14934 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 14935 {
14936 _bfd_error_handler
871b3ab2 14937 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
a9dc9481 14938 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 14939 }
a9dc9481 14940 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 14941 out_attr[i].i = in_attr[i].i;
14942 break;
ee065d83
PB		 14943 case Tag_ABI_enum_size:
14944 if (in_attr[i].i != AEABI_enum_unused)
14945 {
14946 if (out_attr[i].i == AEABI_enum_unused
14947 || out_attr[i].i == AEABI_enum_forced_wide)
14948 {
14949 /* The existing object is compatible with anything.
14950 Use whatever requirements the new object has. */
14951 out_attr[i].i = in_attr[i].i;
14952 }
14953 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 14954 && out_attr[i].i != in_attr[i].i
0ffa91dd 14955 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 14956 {
91e22acd 14957 static const char *aeabi_enum_names[] =
bf21ed78 14958 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 14959 const char *in_name =
14960 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14961 ? aeabi_enum_names[in_attr[i].i]
14962 : "<unknown>";
14963 const char *out_name =
14964 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14965 ? aeabi_enum_names[out_attr[i].i]
14966 : "<unknown>";
ee065d83 14967 _bfd_error_handler
871b3ab2 14968 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 14969 ibfd, in_name, out_name);
ee065d83
PB		 14970 }
14971 }
14972 break;
14973 case Tag_ABI_VFP_args:
14974 /* Aready done. */
14975 break;
14976 case Tag_ABI_WMMX_args:
14977 if (in_attr[i].i != out_attr[i].i)
14978 {
14979 _bfd_error_handler
871b3ab2 14980 (_("error: %pB uses iWMMXt register arguments, %pB does not"),
ee065d83 14981 ibfd, obfd);
91e22acd 14982 result = FALSE;
ee065d83
PB		 14983 }
14984 break;
7b86a9fa
AS		 14985 case Tag_compatibility:
14986 /* Merged in target-independent code. */
14987 break;
91e22acd 14988 case Tag_ABI_HardFP_use:
4547cb56 14989 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 14990 break;
14991 case Tag_ABI_FP_16bit_format:
14992 if (in_attr[i].i != 0 && out_attr[i].i != 0)
14993 {
14994 if (in_attr[i].i != out_attr[i].i)
14995 {
14996 _bfd_error_handler
871b3ab2 14997 (_("error: fp16 format mismatch between %pB and %pB"),
91e22acd
AS		 14998 ibfd, obfd);
14999 result = FALSE;
15000 }
15001 }
15002 if (in_attr[i].i != 0)
15003 out_attr[i].i = in_attr[i].i;
15004 break;
7b86a9fa 15005
cd21e546 15006 case Tag_DIV_use:
ac56ee8f
MGD		 15007 /* A value of zero on input means that the divide instruction may
15008 be used if available in the base architecture as specified via
15009 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
15010 the user did not want divide instructions. A value of 2
15011 explicitly means that divide instructions were allowed in ARM
15012 and Thumb state. */
15013 if (in_attr[i].i == out_attr[i].i)
15014 /* Do nothing. */ ;
15015 else if (elf32_arm_attributes_forbid_div (in_attr)
15016 && !elf32_arm_attributes_accept_div (out_attr))
15017 out_attr[i].i = 1;
15018 else if (elf32_arm_attributes_forbid_div (out_attr)
15019 && elf32_arm_attributes_accept_div (in_attr))
15020 out_attr[i].i = in_attr[i].i;
15021 else if (in_attr[i].i == 2)
15022 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 15023 break;
15024
15025 case Tag_MPextension_use_legacy:
15026 /* We don't output objects with Tag_MPextension_use_legacy - we
15027 move the value to Tag_MPextension_use. */
15028 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
15029 {
15030 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
15031 {
15032 _bfd_error_handler
871b3ab2 15033 (_("%pB has both the current and legacy "
b38cadfb 15034 "Tag_MPextension_use attributes"),
cd21e546
MGD		 15035 ibfd);
15036 result = FALSE;
15037 }
15038 }
15039
15040 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
15041 out_attr[Tag_MPextension_use] = in_attr[i];
15042
15043 break;
15044
91e22acd 15045 case Tag_nodefaults:
2d0bb761
AS		 15046 /* This tag is set if it exists, but the value is unused (and is
15047 typically zero). We don't actually need to do anything here -
15048 the merge happens automatically when the type flags are merged
15049 below. */
91e22acd
AS		 15050 break;
15051 case Tag_also_compatible_with:
15052 /* Already done in Tag_CPU_arch. */
15053 break;
15054 case Tag_conformance:
15055 /* Keep the attribute if it matches. Throw it away otherwise.
15056 No attribute means no claim to conform. */
15057 if (!in_attr[i].s || !out_attr[i].s
15058 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
15059 out_attr[i].s = NULL;
15060 break;
3cfad14c 15061
91e22acd 15062 default:
e8b36cd1
JM		 15063 result
15064 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 15065 }
15066
15067 /* If out_attr was copied from in_attr then it won't have a type yet. */
15068 if (in_attr[i].type && !out_attr[i].type)
15069 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 15070 }
15071
104d59d1 15072 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 15073 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 15074 return FALSE;
ee065d83 15075
104d59d1 15076 /* Check for any attributes not known on ARM. */
e8b36cd1 15077 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 15078
91e22acd 15079 return result;
252b5132
RH		 15080}
15081
3a4a14e9
PB		 15082
15083/* Return TRUE if the two EABI versions are incompatible. */
15084
15085static bfd_boolean
15086elf32_arm_versions_compatible (unsigned iver, unsigned over)
15087{
15088 /* v4 and v5 are the same spec before and after it was released,
15089 so allow mixing them. */
15090 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
15091 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
15092 return TRUE;
15093
15094 return (iver == over);
15095}
15096
252b5132
RH		 15097/* Merge backend specific data from an object file to the output
15098 object file when linking. */
9b485d32 15099
b34976b6 15100static bfd_boolean
50e03d47 15101elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 15102
9b485d32
NC		 15103/* Display the flags field. */
15104
b34976b6 15105static bfd_boolean
57e8b36a 15106elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 15107{
fc830a83
NC		 15108 FILE * file = (FILE *) ptr;
15109 unsigned long flags;
252b5132
RH		 15110
15111 BFD_ASSERT (abfd != NULL && ptr != NULL);
15112
15113 /* Print normal ELF private data. */
15114 _bfd_elf_print_private_bfd_data (abfd, ptr);
15115
fc830a83 15116 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 15117 /* Ignore init flag - it may not be set, despite the flags field
15118 containing valid data. */
252b5132 15119
9b485d32 15120 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 15121
fc830a83
NC		 15122 switch (EF_ARM_EABI_VERSION (flags))
15123 {
15124 case EF_ARM_EABI_UNKNOWN:
4cc11e76 15125 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 15126 official ARM ELF extended ABI. Hence they are only decoded if
15127 the EABI version is not set. */
fd2ec330 15128 if (flags & EF_ARM_INTERWORK)
9b485d32 15129 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 15130
fd2ec330 15131 if (flags & EF_ARM_APCS_26)
6c571f00 15132 fprintf (file, " [APCS-26]");
fc830a83 15133 else
6c571f00 15134 fprintf (file, " [APCS-32]");
9a5aca8c 15135
96a846ea
RE		 15136 if (flags & EF_ARM_VFP_FLOAT)
15137 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 15138 else if (flags & EF_ARM_MAVERICK_FLOAT)
15139 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 15140 else
15141 fprintf (file, _(" [FPA float format]"));
15142
fd2ec330 15143 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 15144 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 15145
fd2ec330 15146 if (flags & EF_ARM_PIC)
9b485d32 15147 fprintf (file, _(" [position independent]"));
fc830a83 15148
fd2ec330 15149 if (flags & EF_ARM_NEW_ABI)
9b485d32 15150 fprintf (file, _(" [new ABI]"));
9a5aca8c 15151
fd2ec330 15152 if (flags & EF_ARM_OLD_ABI)
9b485d32 15153 fprintf (file, _(" [old ABI]"));
9a5aca8c 15154
fd2ec330 15155 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 15156 fprintf (file, _(" [software FP]"));
9a5aca8c 15157
96a846ea
RE		 15158 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
15159 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 15160 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
15161 | EF_ARM_MAVERICK_FLOAT);
fc830a83 15162 break;
9a5aca8c 15163
fc830a83 15164 case EF_ARM_EABI_VER1:
9b485d32 15165 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 15166
fc830a83 15167 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 15168 fprintf (file, _(" [sorted symbol table]"));
fc830a83 15169 else
9b485d32 15170 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 15171
fc830a83
NC		 15172 flags &= ~ EF_ARM_SYMSARESORTED;
15173 break;
9a5aca8c 15174
fd2ec330
PB		 15175 case EF_ARM_EABI_VER2:
15176 fprintf (file, _(" [Version2 EABI]"));
15177
15178 if (flags & EF_ARM_SYMSARESORTED)
15179 fprintf (file, _(" [sorted symbol table]"));
15180 else
15181 fprintf (file, _(" [unsorted symbol table]"));
15182
15183 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
15184 fprintf (file, _(" [dynamic symbols use segment index]"));
15185
15186 if (flags & EF_ARM_MAPSYMSFIRST)
15187 fprintf (file, _(" [mapping symbols precede others]"));
15188
99e4ae17 15189 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 15190 | EF_ARM_MAPSYMSFIRST);
15191 break;
15192
d507cf36
PB		 15193 case EF_ARM_EABI_VER3:
15194 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 15195 break;
15196
15197 case EF_ARM_EABI_VER4:
15198 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 15199 goto eabi;
d507cf36 15200
3a4a14e9
PB		 15201 case EF_ARM_EABI_VER5:
15202 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 15203
15204 if (flags & EF_ARM_ABI_FLOAT_SOFT)
15205 fprintf (file, _(" [soft-float ABI]"));
15206
15207 if (flags & EF_ARM_ABI_FLOAT_HARD)
15208 fprintf (file, _(" [hard-float ABI]"));
15209
15210 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
15211
3a4a14e9 15212 eabi:
d507cf36
PB		 15213 if (flags & EF_ARM_BE8)
15214 fprintf (file, _(" [BE8]"));
15215
15216 if (flags & EF_ARM_LE8)
15217 fprintf (file, _(" [LE8]"));
15218
15219 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
15220 break;
15221
fc830a83 15222 default:
9b485d32 15223 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 15224 break;
15225 }
252b5132 15226
fc830a83 15227 flags &= ~ EF_ARM_EABIMASK;
252b5132 15228
fc830a83 15229 if (flags & EF_ARM_RELEXEC)
9b485d32 15230 fprintf (file, _(" [relocatable executable]"));
252b5132 15231
18a20338
CL		 15232 if (flags & EF_ARM_PIC)
15233 fprintf (file, _(" [position independent]"));
15234
15235 if (elf_elfheader (abfd)->e_ident[EI_OSABI] == ELFOSABI_ARM_FDPIC)
15236 fprintf (file, _(" [FDPIC ABI supplement]"));
15237
15238 flags &= ~ (EF_ARM_RELEXEC | EF_ARM_PIC);
fc830a83
NC		 15239
15240 if (flags)
9b485d32 15241 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 15242
252b5132
RH		 15243 fputc ('\n', file);
15244
b34976b6 15245 return TRUE;
252b5132
RH		 15246}
15247
15248static int
57e8b36a 15249elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 15250{
2f0ca46a
NC		 15251 switch (ELF_ST_TYPE (elf_sym->st_info))
15252 {
15253 case STT_ARM_TFUNC:
15254 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 15255
2f0ca46a
NC		 15256 case STT_ARM_16BIT:
15257 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15258 This allows us to distinguish between data used by Thumb instructions
15259 and non-data (which is probably code) inside Thumb regions of an
15260 executable. */
1a0eb693 15261 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 15262 return ELF_ST_TYPE (elf_sym->st_info);
15263 break;
9a5aca8c 15264
ce855c42
NC		 15265 default:
15266 break;
2f0ca46a
NC		 15267 }
15268
15269 return type;
252b5132 15270}
f21f3fe0 15271
252b5132 15272static asection *
07adf181
AM		 15273elf32_arm_gc_mark_hook (asection *sec,
15274 struct bfd_link_info *info,
15275 Elf_Internal_Rela *rel,
15276 struct elf_link_hash_entry *h,
15277 Elf_Internal_Sym *sym)
252b5132
RH		 15278{
15279 if (h != NULL)
07adf181 15280 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 15281 {
15282 case R_ARM_GNU_VTINHERIT:
15283 case R_ARM_GNU_VTENTRY:
07adf181
AM		 15284 return NULL;
15285 }
9ad5cbcf 15286
07adf181 15287 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 15288}
15289
780a67af
NC		 15290/* Look through the relocs for a section during the first phase. */
15291
b34976b6 15292static bfd_boolean
57e8b36a
NC		 15293elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
15294 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 15295{
b34976b6
AM		 15296 Elf_Internal_Shdr *symtab_hdr;
15297 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 15298 const Elf_Internal_Rela *rel;
15299 const Elf_Internal_Rela *rel_end;
15300 bfd *dynobj;
5e681ec4 15301 asection *sreloc;
5e681ec4 15302 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 15303 bfd_boolean call_reloc_p;
15304 bfd_boolean may_become_dynamic_p;
15305 bfd_boolean may_need_local_target_p;
ce98a316 15306 unsigned long nsyms;
9a5aca8c 15307
0e1862bb 15308 if (bfd_link_relocatable (info))
b34976b6 15309 return TRUE;
9a5aca8c 15310
0ffa91dd
NC		 15311 BFD_ASSERT (is_arm_elf (abfd));
15312
5e681ec4 15313 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15314 if (htab == NULL)
15315 return FALSE;
15316
5e681ec4 15317 sreloc = NULL;
9a5aca8c 15318
67687978
PB		 15319 /* Create dynamic sections for relocatable executables so that we can
15320 copy relocations. */
15321 if (htab->root.is_relocatable_executable
15322 && ! htab->root.dynamic_sections_created)
15323 {
15324 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
15325 return FALSE;
15326 }
15327
cbc704f3
RS		 15328 if (htab->root.dynobj == NULL)
15329 htab->root.dynobj = abfd;
34e77a92
RS		 15330 if (!create_ifunc_sections (info))
15331 return FALSE;
cbc704f3
RS		 15332
15333 dynobj = htab->root.dynobj;
15334
0ffa91dd 15335 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 15336 sym_hashes = elf_sym_hashes (abfd);
ce98a316 15337 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 15338
252b5132
RH		 15339 rel_end = relocs + sec->reloc_count;
15340 for (rel = relocs; rel < rel_end; rel++)
15341 {
34e77a92 15342 Elf_Internal_Sym *isym;
252b5132 15343 struct elf_link_hash_entry *h;
b7693d02 15344 struct elf32_arm_link_hash_entry *eh;
d42c267e 15345 unsigned int r_symndx;
eb043451 15346 int r_type;
9a5aca8c 15347
252b5132 15348 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 15349 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 15350 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 15351
ce98a316
NC		 15352 if (r_symndx >= nsyms
15353 /* PR 9934: It is possible to have relocations that do not
15354 refer to symbols, thus it is also possible to have an
15355 object file containing relocations but no symbol table. */
cf35638d 15356 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 15357 {
871b3ab2 15358 _bfd_error_handler (_("%pB: bad symbol index: %d"), abfd,
4eca0228 15359 r_symndx);
ba93b8ac
DJ		 15360 return FALSE;
15361 }
15362
34e77a92
RS		 15363 h = NULL;
15364 isym = NULL;
15365 if (nsyms > 0)
973a3492 15366 {
34e77a92
RS		 15367 if (r_symndx < symtab_hdr->sh_info)
15368 {
15369 /* A local symbol. */
15370 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
15371 abfd, r_symndx);
15372 if (isym == NULL)
15373 return FALSE;
15374 }
15375 else
15376 {
15377 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
15378 while (h->root.type == bfd_link_hash_indirect
15379 || h->root.type == bfd_link_hash_warning)
15380 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15381 }
973a3492 15382 }
9a5aca8c 15383
b7693d02
DJ		 15384 eh = (struct elf32_arm_link_hash_entry *) h;
15385
f6e32f6d
RS		 15386 call_reloc_p = FALSE;
15387 may_become_dynamic_p = FALSE;
15388 may_need_local_target_p = FALSE;
15389
0855e32b
NS		 15390 /* Could be done earlier, if h were already available. */
15391 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 15392 switch (r_type)
99059e56 15393 {
e8b09b87
CL		 15394 case R_ARM_GOTOFFFUNCDESC:
15395 {
15396 if (h == NULL)
15397 {
15398 if (!elf32_arm_allocate_local_sym_info (abfd))
15399 return FALSE;
15400 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].gotofffuncdesc_cnt += 1;
15401 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15402 }
15403 else
15404 {
15405 eh->fdpic_cnts.gotofffuncdesc_cnt++;
15406 }
15407 }
15408 break;
15409
15410 case R_ARM_GOTFUNCDESC:
15411 {
15412 if (h == NULL)
15413 {
15414 /* Such a relocation is not supposed to be generated
15415 by gcc on a static function. */
15416 /* Anyway if needed it could be handled. */
15417 abort();
15418 }
15419 else
15420 {
15421 eh->fdpic_cnts.gotfuncdesc_cnt++;
15422 }
15423 }
15424 break;
15425
15426 case R_ARM_FUNCDESC:
15427 {
15428 if (h == NULL)
15429 {
15430 if (!elf32_arm_allocate_local_sym_info (abfd))
15431 return FALSE;
15432 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_cnt += 1;
15433 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15434 }
15435 else
15436 {
15437 eh->fdpic_cnts.funcdesc_cnt++;
15438 }
15439 }
15440 break;
15441
5e681ec4 15442 case R_ARM_GOT32:
eb043451 15443 case R_ARM_GOT_PREL:
ba93b8ac 15444 case R_ARM_TLS_GD32:
5c5a4843 15445 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 15446 case R_ARM_TLS_IE32:
5c5a4843 15447 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 15448 case R_ARM_TLS_GOTDESC:
15449 case R_ARM_TLS_DESCSEQ:
15450 case R_ARM_THM_TLS_DESCSEQ:
15451 case R_ARM_TLS_CALL:
15452 case R_ARM_THM_TLS_CALL:
5e681ec4 15453 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 15454 {
15455 int tls_type, old_tls_type;
5e681ec4 15456
ba93b8ac
DJ		 15457 switch (r_type)
15458 {
15459 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
5c5a4843 15460 case R_ARM_TLS_GD32_FDPIC: tls_type = GOT_TLS_GD; break;
b38cadfb 15461
ba93b8ac 15462 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
5c5a4843 15463 case R_ARM_TLS_IE32_FDPIC: tls_type = GOT_TLS_IE; break;
b38cadfb 15464
0855e32b
NS		 15465 case R_ARM_TLS_GOTDESC:
15466 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
15467 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
15468 tls_type = GOT_TLS_GDESC; break;
b38cadfb 15469
ba93b8ac
DJ		 15470 default: tls_type = GOT_NORMAL; break;
15471 }
252b5132 15472
0e1862bb 15473 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 15474 info->flags |= DF_STATIC_TLS;
15475
ba93b8ac
DJ		 15476 if (h != NULL)
15477 {
15478 h->got.refcount++;
15479 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
15480 }
15481 else
15482 {
ba93b8ac 15483 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 15484 if (!elf32_arm_allocate_local_sym_info (abfd))
15485 return FALSE;
15486 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 15487 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
15488 }
15489
0855e32b 15490 /* If a variable is accessed with both tls methods, two
99059e56 15491 slots may be created. */
0855e32b
NS		 15492 if (GOT_TLS_GD_ANY_P (old_tls_type)
15493 && GOT_TLS_GD_ANY_P (tls_type))
15494 tls_type |= old_tls_type;
15495
15496 /* We will already have issued an error message if there
15497 is a TLS/non-TLS mismatch, based on the symbol
15498 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 15499 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
15500 && tls_type != GOT_NORMAL)
15501 tls_type |= old_tls_type;
15502
0855e32b 15503 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 15504 method, we're able to relax. Turn off the GDESC flag,
15505 without messing up with any other kind of tls types
6a631e86 15506 that may be involved. */
0855e32b
NS		 15507 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
15508 tls_type &= ~GOT_TLS_GDESC;
15509
ba93b8ac
DJ		 15510 if (old_tls_type != tls_type)
15511 {
15512 if (h != NULL)
15513 elf32_arm_hash_entry (h)->tls_type = tls_type;
15514 else
15515 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
15516 }
15517 }
8029a119 15518 /* Fall through. */
ba93b8ac
DJ		 15519
15520 case R_ARM_TLS_LDM32:
5c5a4843
CL		 15521 case R_ARM_TLS_LDM32_FDPIC:
15522 if (r_type == R_ARM_TLS_LDM32 || r_type == R_ARM_TLS_LDM32_FDPIC)
ba93b8ac 15523 htab->tls_ldm_got.refcount++;
8029a119 15524 /* Fall through. */
252b5132 15525
c19d1205 15526 case R_ARM_GOTOFF32:
5e681ec4 15527 case R_ARM_GOTPC:
cbc704f3
RS		 15528 if (htab->root.sgot == NULL
15529 && !create_got_section (htab->root.dynobj, info))
15530 return FALSE;
252b5132
RH		 15531 break;
15532
252b5132 15533 case R_ARM_PC24:
7359ea65 15534 case R_ARM_PLT32:
5b5bb741
PB		 15535 case R_ARM_CALL:
15536 case R_ARM_JUMP24:
eb043451 15537 case R_ARM_PREL31:
c19d1205 15538 case R_ARM_THM_CALL:
bd97cb95
DJ		 15539 case R_ARM_THM_JUMP24:
15540 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 15541 call_reloc_p = TRUE;
15542 may_need_local_target_p = TRUE;
15543 break;
15544
15545 case R_ARM_ABS12:
15546 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15547 ldr __GOTT_INDEX__ offsets. */
15548 if (!htab->vxworks_p)
15549 {
15550 may_need_local_target_p = TRUE;
15551 break;
15552 }
aebf9be7 15553 else goto jump_over;
9eaff861 15554
f6e32f6d 15555 /* Fall through. */
39623e12 15556
96c23d59
JM		 15557 case R_ARM_MOVW_ABS_NC:
15558 case R_ARM_MOVT_ABS:
15559 case R_ARM_THM_MOVW_ABS_NC:
15560 case R_ARM_THM_MOVT_ABS:
0e1862bb 15561 if (bfd_link_pic (info))
96c23d59 15562 {
4eca0228 15563 _bfd_error_handler
871b3ab2 15564 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
96c23d59
JM		 15565 abfd, elf32_arm_howto_table_1[r_type].name,
15566 (h) ? h->root.root.string : "a local symbol");
15567 bfd_set_error (bfd_error_bad_value);
15568 return FALSE;
15569 }
15570
15571 /* Fall through. */
39623e12
PB		 15572 case R_ARM_ABS32:
15573 case R_ARM_ABS32_NOI:
aebf9be7 15574 jump_over:
0e1862bb 15575 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 15576 {
15577 h->pointer_equality_needed = 1;
15578 }
15579 /* Fall through. */
39623e12
PB		 15580 case R_ARM_REL32:
15581 case R_ARM_REL32_NOI:
b6895b4f
PB		 15582 case R_ARM_MOVW_PREL_NC:
15583 case R_ARM_MOVT_PREL:
b6895b4f
PB		 15584 case R_ARM_THM_MOVW_PREL_NC:
15585 case R_ARM_THM_MOVT_PREL:
39623e12 15586
b7693d02 15587 /* Should the interworking branches be listed here? */
e8b09b87
CL		 15588 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable
15589 || htab->fdpic_p)
34e77a92
RS		 15590 && (sec->flags & SEC_ALLOC) != 0)
15591 {
15592 if (h == NULL
469a3493 15593 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 15594 {
15595 /* In shared libraries and relocatable executables,
15596 we treat local relative references as calls;
15597 see the related SYMBOL_CALLS_LOCAL code in
15598 allocate_dynrelocs. */
15599 call_reloc_p = TRUE;
15600 may_need_local_target_p = TRUE;
15601 }
15602 else
15603 /* We are creating a shared library or relocatable
15604 executable, and this is a reloc against a global symbol,
15605 or a non-PC-relative reloc against a local symbol.
15606 We may need to copy the reloc into the output. */
15607 may_become_dynamic_p = TRUE;
15608 }
f6e32f6d
RS		 15609 else
15610 may_need_local_target_p = TRUE;
252b5132
RH		 15611 break;
15612
99059e56
RM		 15613 /* This relocation describes the C++ object vtable hierarchy.
15614 Reconstruct it for later use during GC. */
15615 case R_ARM_GNU_VTINHERIT:
15616 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
15617 return FALSE;
15618 break;
15619
15620 /* This relocation describes which C++ vtable entries are actually
15621 used. Record for later use during GC. */
15622 case R_ARM_GNU_VTENTRY:
a0ea3a14 15623 if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
99059e56
RM		 15624 return FALSE;
15625 break;
15626 }
f6e32f6d
RS		 15627
15628 if (h != NULL)
15629 {
15630 if (call_reloc_p)
15631 /* We may need a .plt entry if the function this reloc
15632 refers to is in a different object, regardless of the
15633 symbol's type. We can't tell for sure yet, because
15634 something later might force the symbol local. */
15635 h->needs_plt = 1;
15636 else if (may_need_local_target_p)
15637 /* If this reloc is in a read-only section, we might
15638 need a copy reloc. We can't check reliably at this
15639 stage whether the section is read-only, as input
15640 sections have not yet been mapped to output sections.
15641 Tentatively set the flag for now, and correct in
15642 adjust_dynamic_symbol. */
15643 h->non_got_ref = 1;
15644 }
15645
34e77a92
RS		 15646 if (may_need_local_target_p
15647 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 15648 {
34e77a92
RS		 15649 union gotplt_union *root_plt;
15650 struct arm_plt_info *arm_plt;
15651 struct arm_local_iplt_info *local_iplt;
15652
15653 if (h != NULL)
15654 {
15655 root_plt = &h->plt;
15656 arm_plt = &eh->plt;
15657 }
15658 else
15659 {
15660 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
15661 if (local_iplt == NULL)
15662 return FALSE;
15663 root_plt = &local_iplt->root;
15664 arm_plt = &local_iplt->arm;
15665 }
15666
f6e32f6d
RS		 15667 /* If the symbol is a function that doesn't bind locally,
15668 this relocation will need a PLT entry. */
a8c887dd
NC		 15669 if (root_plt->refcount != -1)
15670 root_plt->refcount += 1;
34e77a92
RS		 15671
15672 if (!call_reloc_p)
15673 arm_plt->noncall_refcount++;
f6e32f6d
RS		 15674
15675 /* It's too early to use htab->use_blx here, so we have to
15676 record possible blx references separately from
15677 relocs that definitely need a thumb stub. */
15678
15679 if (r_type == R_ARM_THM_CALL)
34e77a92 15680 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 15681
15682 if (r_type == R_ARM_THM_JUMP24
15683 || r_type == R_ARM_THM_JUMP19)
34e77a92 15684 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 15685 }
15686
15687 if (may_become_dynamic_p)
15688 {
15689 struct elf_dyn_relocs *p, **head;
15690
15691 /* Create a reloc section in dynobj. */
15692 if (sreloc == NULL)
15693 {
15694 sreloc = _bfd_elf_make_dynamic_reloc_section
15695 (sec, dynobj, 2, abfd, ! htab->use_rel);
15696
15697 if (sreloc == NULL)
15698 return FALSE;
15699
15700 /* BPABI objects never have dynamic relocations mapped. */
15701 if (htab->symbian_p)
15702 {
15703 flagword flags;
15704
fd361982 15705 flags = bfd_section_flags (sreloc);
f6e32f6d 15706 flags &= ~(SEC_LOAD | SEC_ALLOC);
fd361982 15707 bfd_set_section_flags (sreloc, flags);
f6e32f6d
RS		 15708 }
15709 }
15710
15711 /* If this is a global symbol, count the number of
15712 relocations we need for this symbol. */
15713 if (h != NULL)
15714 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
15715 else
15716 {
34e77a92
RS		 15717 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
15718 if (head == NULL)
f6e32f6d 15719 return FALSE;
f6e32f6d
RS		 15720 }
15721
15722 p = *head;
15723 if (p == NULL || p->sec != sec)
15724 {
15725 bfd_size_type amt = sizeof *p;
15726
15727 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
15728 if (p == NULL)
15729 return FALSE;
15730 p->next = *head;
15731 *head = p;
15732 p->sec = sec;
15733 p->count = 0;
15734 p->pc_count = 0;
15735 }
15736
469a3493 15737 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 15738 p->pc_count += 1;
15739 p->count += 1;
e8b09b87
CL		 15740 if (h == NULL && htab->fdpic_p && !bfd_link_pic(info)
15741 && r_type != R_ARM_ABS32 && r_type != R_ARM_ABS32_NOI) {
15742 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15743 that will become rofixup. */
15744 /* This is due to the fact that we suppose all will become rofixup. */
15745 fprintf(stderr, "FDPIC does not yet support %d relocation to become dynamic for executable\n", r_type);
15746 _bfd_error_handler
15747 (_("FDPIC does not yet support %s relocation"
15748 " to become dynamic for executable"),
15749 elf32_arm_howto_table_1[r_type].name);
15750 abort();
15751 }
f6e32f6d 15752 }
252b5132 15753 }
f21f3fe0 15754
b34976b6 15755 return TRUE;
252b5132
RH		 15756}
15757
9eaff861
AO		 15758static void
15759elf32_arm_update_relocs (asection *o,
15760 struct bfd_elf_section_reloc_data *reldata)
15761{
15762 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
15763 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
15764 const struct elf_backend_data *bed;
15765 _arm_elf_section_data *eado;
15766 struct bfd_link_order *p;
15767 bfd_byte *erela_head, *erela;
15768 Elf_Internal_Rela *irela_head, *irela;
15769 Elf_Internal_Shdr *rel_hdr;
15770 bfd *abfd;
15771 unsigned int count;
15772
15773 eado = get_arm_elf_section_data (o);
15774
15775 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
15776 return;
15777
15778 abfd = o->owner;
15779 bed = get_elf_backend_data (abfd);
15780 rel_hdr = reldata->hdr;
15781
15782 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
15783 {
15784 swap_in = bed->s->swap_reloc_in;
15785 swap_out = bed->s->swap_reloc_out;
15786 }
15787 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
15788 {
15789 swap_in = bed->s->swap_reloca_in;
15790 swap_out = bed->s->swap_reloca_out;
15791 }
15792 else
15793 abort ();
15794
15795 erela_head = rel_hdr->contents;
15796 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
15797 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
15798
15799 erela = erela_head;
15800 irela = irela_head;
15801 count = 0;
15802
15803 for (p = o->map_head.link_order; p; p = p->next)
15804 {
15805 if (p->type == bfd_section_reloc_link_order
15806 || p->type == bfd_symbol_reloc_link_order)
15807 {
15808 (*swap_in) (abfd, erela, irela);
15809 erela += rel_hdr->sh_entsize;
15810 irela++;
15811 count++;
15812 }
15813 else if (p->type == bfd_indirect_link_order)
15814 {
15815 struct bfd_elf_section_reloc_data *input_reldata;
15816 arm_unwind_table_edit *edit_list, *edit_tail;
15817 _arm_elf_section_data *eadi;
15818 bfd_size_type j;
15819 bfd_vma offset;
15820 asection *i;
15821
15822 i = p->u.indirect.section;
15823
15824 eadi = get_arm_elf_section_data (i);
15825 edit_list = eadi->u.exidx.unwind_edit_list;
15826 edit_tail = eadi->u.exidx.unwind_edit_tail;
539300fb 15827 offset = i->output_offset;
9eaff861
AO		 15828
15829 if (eadi->elf.rel.hdr &&
15830 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
15831 input_reldata = &eadi->elf.rel;
15832 else if (eadi->elf.rela.hdr &&
15833 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
15834 input_reldata = &eadi->elf.rela;
15835 else
15836 abort ();
15837
15838 if (edit_list)
15839 {
15840 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15841 {
15842 arm_unwind_table_edit *edit_node, *edit_next;
15843 bfd_vma bias;
c48182bf 15844 bfd_vma reloc_index;
9eaff861
AO		 15845
15846 (*swap_in) (abfd, erela, irela);
c48182bf 15847 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 15848
15849 bias = 0;
15850 edit_node = edit_list;
15851 for (edit_next = edit_list;
c48182bf 15852 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 15853 edit_next = edit_node->next)
15854 {
15855 bias++;
15856 edit_node = edit_next;
15857 }
15858
15859 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 15860 || edit_node->index != reloc_index)
9eaff861
AO		 15861 {
15862 irela->r_offset -= bias * 8;
15863 irela++;
15864 count++;
15865 }
15866
15867 erela += rel_hdr->sh_entsize;
15868 }
15869
15870 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
15871 {
15872 /* New relocation entity. */
15873 asection *text_sec = edit_tail->linked_section;
15874 asection *text_out = text_sec->output_section;
15875 bfd_vma exidx_offset = offset + i->size - 8;
15876
15877 irela->r_addend = 0;
15878 irela->r_offset = exidx_offset;
15879 irela->r_info = ELF32_R_INFO
15880 (text_out->target_index, R_ARM_PREL31);
15881 irela++;
15882 count++;
15883 }
15884 }
15885 else
15886 {
15887 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15888 {
15889 (*swap_in) (abfd, erela, irela);
15890 erela += rel_hdr->sh_entsize;
15891 irela++;
15892 }
15893
15894 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15895 }
15896 }
15897 }
15898
15899 reldata->count = count;
15900 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15901
15902 erela = erela_head;
15903 irela = irela_head;
15904 while (count > 0)
15905 {
15906 (*swap_out) (abfd, irela, erela);
15907 erela += rel_hdr->sh_entsize;
15908 irela++;
15909 count--;
15910 }
15911
15912 free (irela_head);
15913
15914 /* Hashes are no longer valid. */
15915 free (reldata->hashes);
15916 reldata->hashes = NULL;
15917}
15918
6a5bb875 15919/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15920 required if the corresponding code section is marked. Similarly, ARMv8-M
15921 secure entry functions can only be referenced by SG veneers which are
15922 created after the GC process. They need to be marked in case they reside in
15923 their own section (as would be the case if code was compiled with
15924 -ffunction-sections). */
6a5bb875
PB		 15925
15926static bfd_boolean
906e58ca
NC		 15927elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15928 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15929{
15930 bfd *sub;
15931 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15932 asection *cmse_sec;
15933 obj_attribute *out_attr;
15934 Elf_Internal_Shdr *symtab_hdr;
15935 unsigned i, sym_count, ext_start;
15936 const struct elf_backend_data *bed;
15937 struct elf_link_hash_entry **sym_hashes;
15938 struct elf32_arm_link_hash_entry *cmse_hash;
15939 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
bb32413f
SP		 15940 bfd_boolean debug_sec_need_to_be_marked = FALSE;
15941 asection *isec;
6a5bb875 15942
7f6ab9f8
AM		 15943 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15944
4ba2ef8f
TP		 15945 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15946 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15947 && out_attr[Tag_CPU_arch_profile].i == 'M';
15948
6a5bb875
PB		 15949 /* Marking EH data may cause additional code sections to be marked,
15950 requiring multiple passes. */
15951 again = TRUE;
15952 while (again)
15953 {
15954 again = FALSE;
c72f2fb2 15955 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15956 {
15957 asection *o;
15958
0ffa91dd 15959 if (! is_arm_elf (sub))
6a5bb875
PB		 15960 continue;
15961
15962 elf_shdrp = elf_elfsections (sub);
15963 for (o = sub->sections; o != NULL; o = o->next)
15964 {
15965 Elf_Internal_Shdr *hdr;
0ffa91dd 15966
6a5bb875 15967 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15968 if (hdr->sh_type == SHT_ARM_EXIDX
15969 && hdr->sh_link
15970 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15971 && !o->gc_mark
15972 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15973 {
15974 again = TRUE;
15975 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15976 return FALSE;
15977 }
15978 }
4ba2ef8f
TP		 15979
15980 /* Mark section holding ARMv8-M secure entry functions. We mark all
15981 of them so no need for a second browsing. */
15982 if (is_v8m && first_bfd_browse)
15983 {
15984 sym_hashes = elf_sym_hashes (sub);
15985 bed = get_elf_backend_data (sub);
15986 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15987 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15988 ext_start = symtab_hdr->sh_info;
15989
15990 /* Scan symbols. */
15991 for (i = ext_start; i < sym_count; i++)
15992 {
15993 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15994
15995 /* Assume it is a special symbol. If not, cmse_scan will
15996 warn about it and user can do something about it. */
baf46cd7
AM		 15997 if (CONST_STRNEQ (cmse_hash->root.root.root.string,
15998 CMSE_PREFIX))
4ba2ef8f
TP		 15999 {
16000 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 16001 if (!cmse_sec->gc_mark
16002 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f 16003 return FALSE;
bb32413f
SP		 16004 /* The debug sections related to these secure entry
16005 functions are marked on enabling below flag. */
16006 debug_sec_need_to_be_marked = TRUE;
4ba2ef8f
TP		 16007 }
16008 }
bb32413f
SP		 16009
16010 if (debug_sec_need_to_be_marked)
16011 {
16012 /* Looping over all the sections of the object file containing
16013 Armv8-M secure entry functions and marking all the debug
16014 sections. */
16015 for (isec = sub->sections; isec != NULL; isec = isec->next)
16016 {
16017 /* If not a debug sections, skip it. */
16018 if (!isec->gc_mark && (isec->flags & SEC_DEBUGGING))
16019 isec->gc_mark = 1 ;
16020 }
16021 debug_sec_need_to_be_marked = FALSE;
16022 }
4ba2ef8f 16023 }
6a5bb875 16024 }
4ba2ef8f 16025 first_bfd_browse = FALSE;
6a5bb875
PB		 16026 }
16027
16028 return TRUE;
16029}
16030
3c9458e9
NC		 16031/* Treat mapping symbols as special target symbols. */
16032
16033static bfd_boolean
16034elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
16035{
b0796911
PB		 16036 return bfd_is_arm_special_symbol_name (sym->name,
16037 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 16038}
16039
62e0492f 16040/* This is a version of _bfd_elf_find_function() from dwarf2.c except that
0367ecfb
NC		 16041 ARM mapping symbols are ignored when looking for function names
16042 and STT_ARM_TFUNC is considered to a function type. */
252b5132 16043
0367ecfb 16044static bfd_boolean
62e0492f 16045arm_elf_find_function (bfd * abfd,
0367ecfb 16046 asymbol ** symbols,
fb167eb2 16047 asection * section,
07d6d2b8 16048 bfd_vma offset,
0367ecfb
NC		 16049 const char ** filename_ptr,
16050 const char ** functionname_ptr)
16051{
16052 const char * filename = NULL;
16053 asymbol * func = NULL;
16054 bfd_vma low_func = 0;
16055 asymbol ** p;
252b5132 16056
62e0492f
AL		 16057 if (symbols == NULL)
16058 return FALSE;
16059
16060 if (bfd_get_flavour (abfd) != bfd_target_elf_flavour)
16061 return FALSE;
16062
252b5132
RH		 16063 for (p = symbols; *p != NULL; p++)
16064 {
16065 elf_symbol_type *q;
16066
16067 q = (elf_symbol_type *) *p;
16068
252b5132
RH		 16069 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
16070 {
16071 default:
16072 break;
16073 case STT_FILE:
16074 filename = bfd_asymbol_name (&q->symbol);
16075 break;
252b5132
RH		 16076 case STT_FUNC:
16077 case STT_ARM_TFUNC:
9d2da7ca 16078 case STT_NOTYPE:
b0796911 16079 /* Skip mapping symbols. */
0367ecfb 16080 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 16081 && bfd_is_arm_special_symbol_name (q->symbol.name,
16082 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 16083 continue;
16084 /* Fall through. */
e6f7f6d1 16085 if (bfd_asymbol_section (&q->symbol) == section
252b5132
RH		 16086 && q->symbol.value >= low_func
16087 && q->symbol.value <= offset)
16088 {
16089 func = (asymbol *) q;
16090 low_func = q->symbol.value;
16091 }
16092 break;
16093 }
16094 }
16095
16096 if (func == NULL)
b34976b6 16097 return FALSE;
252b5132 16098
0367ecfb
NC		 16099 if (filename_ptr)
16100 *filename_ptr = filename;
16101 if (functionname_ptr)
16102 *functionname_ptr = bfd_asymbol_name (func);
16103
16104 return TRUE;
906e58ca 16105}
0367ecfb
NC		 16106
16107
16108/* Find the nearest line to a particular section and offset, for error
16109 reporting. This code is a duplicate of the code in elf.c, except
16110 that it uses arm_elf_find_function. */
16111
16112static bfd_boolean
07d6d2b8
AM		 16113elf32_arm_find_nearest_line (bfd * abfd,
16114 asymbol ** symbols,
16115 asection * section,
16116 bfd_vma offset,
0367ecfb
NC		 16117 const char ** filename_ptr,
16118 const char ** functionname_ptr,
fb167eb2
AM		 16119 unsigned int * line_ptr,
16120 unsigned int * discriminator_ptr)
0367ecfb
NC		 16121{
16122 bfd_boolean found = FALSE;
16123
fb167eb2 16124 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 16125 filename_ptr, functionname_ptr,
fb167eb2 16126 line_ptr, discriminator_ptr,
9defd221 16127 dwarf_debug_sections,
0367ecfb
NC		 16128 & elf_tdata (abfd)->dwarf2_find_line_info))
16129 {
16130 if (!*functionname_ptr)
fb167eb2 16131 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 16132 *filename_ptr ? NULL : filename_ptr,
16133 functionname_ptr);
f21f3fe0 16134
0367ecfb
NC		 16135 return TRUE;
16136 }
16137
fb167eb2
AM		 16138 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
16139 uses DWARF1. */
16140
0367ecfb
NC		 16141 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
16142 & found, filename_ptr,
16143 functionname_ptr, line_ptr,
16144 & elf_tdata (abfd)->line_info))
16145 return FALSE;
16146
16147 if (found && (*functionname_ptr || *line_ptr))
16148 return TRUE;
16149
16150 if (symbols == NULL)
16151 return FALSE;
16152
fb167eb2 16153 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 16154 filename_ptr, functionname_ptr))
16155 return FALSE;
16156
16157 *line_ptr = 0;
b34976b6 16158 return TRUE;
252b5132
RH		 16159}
16160
4ab527b0 16161static bfd_boolean
07d6d2b8 16162elf32_arm_find_inliner_info (bfd * abfd,
4ab527b0
FF		 16163 const char ** filename_ptr,
16164 const char ** functionname_ptr,
16165 unsigned int * line_ptr)
16166{
16167 bfd_boolean found;
16168 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
16169 functionname_ptr, line_ptr,
16170 & elf_tdata (abfd)->dwarf2_find_line_info);
16171 return found;
16172}
16173
63c1f59d
AM		 16174/* Find dynamic relocs for H that apply to read-only sections. */
16175
16176static asection *
16177readonly_dynrelocs (struct elf_link_hash_entry *h)
16178{
16179 struct elf_dyn_relocs *p;
16180
16181 for (p = elf32_arm_hash_entry (h)->dyn_relocs; p != NULL; p = p->next)
16182 {
16183 asection *s = p->sec->output_section;
16184
16185 if (s != NULL && (s->flags & SEC_READONLY) != 0)
16186 return p->sec;
16187 }
16188 return NULL;
16189}
16190
252b5132
RH		 16191/* Adjust a symbol defined by a dynamic object and referenced by a
16192 regular object. The current definition is in some section of the
16193 dynamic object, but we're not including those sections. We have to
16194 change the definition to something the rest of the link can
16195 understand. */
16196
b34976b6 16197static bfd_boolean
57e8b36a
NC		 16198elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
16199 struct elf_link_hash_entry * h)
252b5132
RH		 16200{
16201 bfd * dynobj;
5474d94f 16202 asection *s, *srel;
b7693d02 16203 struct elf32_arm_link_hash_entry * eh;
67687978 16204 struct elf32_arm_link_hash_table *globals;
252b5132 16205
67687978 16206 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16207 if (globals == NULL)
16208 return FALSE;
16209
252b5132
RH		 16210 dynobj = elf_hash_table (info)->dynobj;
16211
16212 /* Make sure we know what is going on here. */
16213 BFD_ASSERT (dynobj != NULL
f5385ebf 16214 && (h->needs_plt
34e77a92 16215 || h->type == STT_GNU_IFUNC
60d67dc8 16216 || h->is_weakalias
f5385ebf
AM		 16217 || (h->def_dynamic
16218 && h->ref_regular
16219 && !h->def_regular)));
252b5132 16220
b7693d02
DJ		 16221 eh = (struct elf32_arm_link_hash_entry *) h;
16222
252b5132
RH		 16223 /* If this is a function, put it in the procedure linkage table. We
16224 will fill in the contents of the procedure linkage table later,
16225 when we know the address of the .got section. */
34e77a92 16226 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 16227 {
34e77a92
RS		 16228 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
16229 symbol binds locally. */
5e681ec4 16230 if (h->plt.refcount <= 0
34e77a92
RS		 16231 || (h->type != STT_GNU_IFUNC
16232 && (SYMBOL_CALLS_LOCAL (info, h)
16233 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16234 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 16235 {
16236 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 16237 file, but the symbol was never referred to by a dynamic
16238 object, or if all references were garbage collected. In
16239 such a case, we don't actually need to build a procedure
16240 linkage table, and we can just do a PC24 reloc instead. */
16241 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16242 eh->plt.thumb_refcount = 0;
16243 eh->plt.maybe_thumb_refcount = 0;
16244 eh->plt.noncall_refcount = 0;
f5385ebf 16245 h->needs_plt = 0;
252b5132
RH		 16246 }
16247
b34976b6 16248 return TRUE;
252b5132 16249 }
5e681ec4 16250 else
b7693d02
DJ		 16251 {
16252 /* It's possible that we incorrectly decided a .plt reloc was
16253 needed for an R_ARM_PC24 or similar reloc to a non-function sym
16254 in check_relocs. We can't decide accurately between function
16255 and non-function syms in check-relocs; Objects loaded later in
16256 the link may change h->type. So fix it now. */
16257 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16258 eh->plt.thumb_refcount = 0;
16259 eh->plt.maybe_thumb_refcount = 0;
16260 eh->plt.noncall_refcount = 0;
b7693d02 16261 }
252b5132
RH		 16262
16263 /* If this is a weak symbol, and there is a real definition, the
16264 processor independent code will have arranged for us to see the
16265 real definition first, and we can just use the same value. */
60d67dc8 16266 if (h->is_weakalias)
252b5132 16267 {
60d67dc8
AM		 16268 struct elf_link_hash_entry *def = weakdef (h);
16269 BFD_ASSERT (def->root.type == bfd_link_hash_defined);
16270 h->root.u.def.section = def->root.u.def.section;
16271 h->root.u.def.value = def->root.u.def.value;
b34976b6 16272 return TRUE;
252b5132
RH		 16273 }
16274
ba93b8ac
DJ		 16275 /* If there are no non-GOT references, we do not need a copy
16276 relocation. */
16277 if (!h->non_got_ref)
16278 return TRUE;
16279
252b5132
RH		 16280 /* This is a reference to a symbol defined by a dynamic object which
16281 is not a function. */
16282
16283 /* If we are creating a shared library, we must presume that the
16284 only references to the symbol are via the global offset table.
16285 For such cases we need not do anything here; the relocations will
67687978
PB		 16286 be handled correctly by relocate_section. Relocatable executables
16287 can reference data in shared objects directly, so we don't need to
16288 do anything here. */
0e1862bb 16289 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 16290 return TRUE;
252b5132
RH		 16291
16292 /* We must allocate the symbol in our .dynbss section, which will
16293 become part of the .bss section of the executable. There will be
16294 an entry for this symbol in the .dynsym section. The dynamic
16295 object will contain position independent code, so all references
16296 from the dynamic object to this symbol will go through the global
16297 offset table. The dynamic linker will use the .dynsym entry to
16298 determine the address it must put in the global offset table, so
16299 both the dynamic object and the regular object will refer to the
16300 same memory location for the variable. */
5522f910
NC		 16301 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16302 linker to copy the initial value out of the dynamic object and into
16303 the runtime process image. We need to remember the offset into the
00a97672 16304 .rel(a).bss section we are going to use. */
5474d94f
AM		 16305 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
16306 {
16307 s = globals->root.sdynrelro;
16308 srel = globals->root.sreldynrelro;
16309 }
16310 else
16311 {
16312 s = globals->root.sdynbss;
16313 srel = globals->root.srelbss;
16314 }
5522f910
NC		 16315 if (info->nocopyreloc == 0
16316 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 16317 && h->size != 0)
252b5132 16318 {
47beaa6a 16319 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 16320 h->needs_copy = 1;
252b5132
RH		 16321 }
16322
6cabe1ea 16323 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 16324}
16325
5e681ec4
PB		 16326/* Allocate space in .plt, .got and associated reloc sections for
16327 dynamic relocs. */
16328
16329static bfd_boolean
47beaa6a 16330allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 16331{
16332 struct bfd_link_info *info;
16333 struct elf32_arm_link_hash_table *htab;
16334 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 16335 struct elf_dyn_relocs *p;
5e681ec4
PB		 16336
16337 if (h->root.type == bfd_link_hash_indirect)
16338 return TRUE;
16339
e6a6bb22
AM		 16340 eh = (struct elf32_arm_link_hash_entry *) h;
16341
5e681ec4
PB		 16342 info = (struct bfd_link_info *) inf;
16343 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16344 if (htab == NULL)
16345 return FALSE;
5e681ec4 16346
34e77a92 16347 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 16348 && h->plt.refcount > 0)
16349 {
16350 /* Make sure this symbol is output as a dynamic symbol.
16351 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16352 if (h->dynindx == -1 && !h->forced_local
16353 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16354 {
c152c796 16355 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16356 return FALSE;
16357 }
16358
34e77a92
RS		 16359 /* If the call in the PLT entry binds locally, the associated
16360 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16361 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16362 than the .plt section. */
16363 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
16364 {
16365 eh->is_iplt = 1;
16366 if (eh->plt.noncall_refcount == 0
16367 && SYMBOL_REFERENCES_LOCAL (info, h))
16368 /* All non-call references can be resolved directly.
16369 This means that they can (and in some cases, must)
16370 resolve directly to the run-time target, rather than
16371 to the PLT. That in turns means that any .got entry
16372 would be equal to the .igot.plt entry, so there's
16373 no point having both. */
16374 h->got.refcount = 0;
16375 }
16376
0e1862bb 16377 if (bfd_link_pic (info)
34e77a92 16378 || eh->is_iplt
7359ea65 16379 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 16380 {
34e77a92 16381 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 16382
5e681ec4
PB		 16383 /* If this symbol is not defined in a regular file, and we are
16384 not generating a shared library, then set the symbol to this
16385 location in the .plt. This is required to make function
16386 pointers compare as equal between the normal executable and
16387 the shared library. */
0e1862bb 16388 if (! bfd_link_pic (info)
f5385ebf 16389 && !h->def_regular)
5e681ec4 16390 {
34e77a92 16391 h->root.u.def.section = htab->root.splt;
5e681ec4 16392 h->root.u.def.value = h->plt.offset;
5e681ec4 16393
67d74e43
DJ		 16394 /* Make sure the function is not marked as Thumb, in case
16395 it is the target of an ABS32 relocation, which will
16396 point to the PLT entry. */
39d911fc 16397 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 16398 }
022f8312 16399
00a97672
RS		 16400 /* VxWorks executables have a second set of relocations for
16401 each PLT entry. They go in a separate relocation section,
16402 which is processed by the kernel loader. */
0e1862bb 16403 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 16404 {
16405 /* There is a relocation for the initial PLT entry:
16406 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16407 if (h->plt.offset == htab->plt_header_size)
47beaa6a 16408 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 16409
16410 /* There are two extra relocations for each subsequent
16411 PLT entry: an R_ARM_32 relocation for the GOT entry,
16412 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 16413 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 16414 }
5e681ec4
PB		 16415 }
16416 else
16417 {
16418 h->plt.offset = (bfd_vma) -1;
f5385ebf 16419 h->needs_plt = 0;
5e681ec4
PB		 16420 }
16421 }
16422 else
16423 {
16424 h->plt.offset = (bfd_vma) -1;
f5385ebf 16425 h->needs_plt = 0;
5e681ec4
PB		 16426 }
16427
0855e32b
NS		 16428 eh = (struct elf32_arm_link_hash_entry *) h;
16429 eh->tlsdesc_got = (bfd_vma) -1;
16430
5e681ec4
PB		 16431 if (h->got.refcount > 0)
16432 {
16433 asection *s;
16434 bfd_boolean dyn;
ba93b8ac
DJ		 16435 int tls_type = elf32_arm_hash_entry (h)->tls_type;
16436 int indx;
5e681ec4
PB		 16437
16438 /* Make sure this symbol is output as a dynamic symbol.
16439 Undefined weak syms won't yet be marked as dynamic. */
e8b09b87 16440 if (htab->root.dynamic_sections_created && h->dynindx == -1 && !h->forced_local
6c699715 16441 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16442 {
c152c796 16443 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16444 return FALSE;
16445 }
16446
e5a52504
MM		 16447 if (!htab->symbian_p)
16448 {
362d30a1 16449 s = htab->root.sgot;
e5a52504 16450 h->got.offset = s->size;
ba93b8ac
DJ		 16451
16452 if (tls_type == GOT_UNKNOWN)
16453 abort ();
16454
16455 if (tls_type == GOT_NORMAL)
16456 /* Non-TLS symbols need one GOT slot. */
16457 s->size += 4;
16458 else
16459 {
99059e56
RM		 16460 if (tls_type & GOT_TLS_GDESC)
16461 {
0855e32b 16462 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 16463 eh->tlsdesc_got
0855e32b
NS		 16464 = (htab->root.sgotplt->size
16465 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 16466 htab->root.sgotplt->size += 8;
16467 h->got.offset = (bfd_vma) -2;
34e77a92 16468 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16469 reloc in the middle of .got.plt. */
99059e56
RM		 16470 htab->num_tls_desc++;
16471 }
0855e32b 16472
ba93b8ac 16473 if (tls_type & GOT_TLS_GD)
0855e32b 16474 {
5c5a4843
CL		 16475 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16476 consecutive GOT slots. If the symbol is both GD
16477 and GDESC, got.offset may have been
16478 overwritten. */
0855e32b
NS		 16479 h->got.offset = s->size;
16480 s->size += 8;
16481 }
16482
ba93b8ac 16483 if (tls_type & GOT_TLS_IE)
5c5a4843
CL		 16484 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16485 slot. */
ba93b8ac
DJ		 16486 s->size += 4;
16487 }
16488
e5a52504 16489 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 16490
16491 indx = 0;
0e1862bb
L		 16492 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
16493 bfd_link_pic (info),
16494 h)
16495 && (!bfd_link_pic (info)
ba93b8ac
DJ		 16496 || !SYMBOL_REFERENCES_LOCAL (info, h)))
16497 indx = h->dynindx;
16498
16499 if (tls_type != GOT_NORMAL
9cb09e33 16500 && (bfd_link_dll (info) || indx != 0)
ba93b8ac
DJ		 16501 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16502 || h->root.type != bfd_link_hash_undefweak))
16503 {
16504 if (tls_type & GOT_TLS_IE)
47beaa6a 16505 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16506
16507 if (tls_type & GOT_TLS_GD)
47beaa6a 16508 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16509
b38cadfb 16510 if (tls_type & GOT_TLS_GDESC)
0855e32b 16511 {
47beaa6a 16512 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 16513 /* GDESC needs a trampoline to jump to. */
16514 htab->tls_trampoline = -1;
16515 }
16516
16517 /* Only GD needs it. GDESC just emits one relocation per
16518 2 entries. */
b38cadfb 16519 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 16520 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16521 }
e8b09b87
CL		 16522 else if (((indx != -1) || htab->fdpic_p)
16523 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 16524 {
16525 if (htab->root.dynamic_sections_created)
16526 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16527 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16528 }
34e77a92
RS		 16529 else if (h->type == STT_GNU_IFUNC
16530 && eh->plt.noncall_refcount == 0)
16531 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16532 they all resolve dynamically instead. Reserve room for the
16533 GOT entry's R_ARM_IRELATIVE relocation. */
16534 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 16535 else if (bfd_link_pic (info)
16536 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16537 || h->root.type != bfd_link_hash_undefweak))
b436d854 16538 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 16539 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16540 else if (htab->fdpic_p && tls_type == GOT_NORMAL)
16541 /* Reserve room for rofixup for FDPIC executable. */
16542 /* TLS relocs do not need space since they are completely
16543 resolved. */
16544 htab->srofixup->size += 4;
e5a52504 16545 }
5e681ec4
PB		 16546 }
16547 else
16548 h->got.offset = (bfd_vma) -1;
16549
e8b09b87
CL		 16550 /* FDPIC support. */
16551 if (eh->fdpic_cnts.gotofffuncdesc_cnt > 0)
16552 {
16553 /* Symbol musn't be exported. */
16554 if (h->dynindx != -1)
16555 abort();
16556
16557 /* We only allocate one function descriptor with its associated relocation. */
16558 if (eh->fdpic_cnts.funcdesc_offset == -1)
16559 {
16560 asection *s = htab->root.sgot;
16561
16562 eh->fdpic_cnts.funcdesc_offset = s->size;
16563 s->size += 8;
16564 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16565 if (bfd_link_pic(info))
16566 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16567 else
16568 htab->srofixup->size += 8;
16569 }
16570 }
16571
16572 if (eh->fdpic_cnts.gotfuncdesc_cnt > 0)
16573 {
16574 asection *s = htab->root.sgot;
16575
16576 if (htab->root.dynamic_sections_created && h->dynindx == -1
16577 && !h->forced_local)
16578 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16579 return FALSE;
16580
16581 if (h->dynindx == -1)
16582 {
16583 /* We only allocate one function descriptor with its associated relocation. q */
16584 if (eh->fdpic_cnts.funcdesc_offset == -1)
16585 {
16586
16587 eh->fdpic_cnts.funcdesc_offset = s->size;
16588 s->size += 8;
16589 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16590 if (bfd_link_pic(info))
16591 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16592 else
16593 htab->srofixup->size += 8;
16594 }
16595 }
16596
16597 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16598 R_ARM_RELATIVE/rofixup relocation on it. */
16599 eh->fdpic_cnts.gotfuncdesc_offset = s->size;
16600 s->size += 4;
16601 if (h->dynindx == -1 && !bfd_link_pic(info))
4b24dd1a 16602 htab->srofixup->size += 4;
e8b09b87 16603 else
4b24dd1a 16604 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16605 }
16606
16607 if (eh->fdpic_cnts.funcdesc_cnt > 0)
16608 {
16609 if (htab->root.dynamic_sections_created && h->dynindx == -1
16610 && !h->forced_local)
16611 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16612 return FALSE;
16613
16614 if (h->dynindx == -1)
16615 {
16616 /* We only allocate one function descriptor with its associated relocation. */
16617 if (eh->fdpic_cnts.funcdesc_offset == -1)
16618 {
16619 asection *s = htab->root.sgot;
16620
16621 eh->fdpic_cnts.funcdesc_offset = s->size;
16622 s->size += 8;
16623 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16624 if (bfd_link_pic(info))
16625 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16626 else
16627 htab->srofixup->size += 8;
16628 }
16629 }
16630 if (h->dynindx == -1 && !bfd_link_pic(info))
16631 {
16632 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16633 htab->srofixup->size += 4 * eh->fdpic_cnts.funcdesc_cnt;
16634 }
16635 else
16636 {
16637 /* Will need one dynamic reloc per reference. will be either
16638 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16639 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot,
16640 eh->fdpic_cnts.funcdesc_cnt);
16641 }
16642 }
16643
a4fd1a8e
PB		 16644 /* Allocate stubs for exported Thumb functions on v4t. */
16645 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 16646 && h->def_regular
39d911fc 16647 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 16648 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
16649 {
16650 struct elf_link_hash_entry * th;
16651 struct bfd_link_hash_entry * bh;
16652 struct elf_link_hash_entry * myh;
16653 char name[1024];
16654 asection *s;
16655 bh = NULL;
16656 /* Create a new symbol to regist the real location of the function. */
16657 s = h->root.u.def.section;
906e58ca 16658 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 16659 _bfd_generic_link_add_one_symbol (info, s->owner,
16660 name, BSF_GLOBAL, s,
16661 h->root.u.def.value,
16662 NULL, TRUE, FALSE, &bh);
16663
16664 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 16665 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 16666 myh->forced_local = 1;
39d911fc 16667 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 16668 eh->export_glue = myh;
16669 th = record_arm_to_thumb_glue (info, h);
16670 /* Point the symbol at the stub. */
16671 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 16672 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 16673 h->root.u.def.section = th->root.u.def.section;
16674 h->root.u.def.value = th->root.u.def.value & ~1;
16675 }
16676
0bdcacaf 16677 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 16678 return TRUE;
16679
16680 /* In the shared -Bsymbolic case, discard space allocated for
16681 dynamic pc-relative relocs against symbols which turn out to be
16682 defined in regular objects. For the normal shared case, discard
16683 space for pc-relative relocs that have become local due to symbol
16684 visibility changes. */
16685
e8b09b87 16686 if (bfd_link_pic (info) || htab->root.is_relocatable_executable || htab->fdpic_p)
5e681ec4 16687 {
469a3493
RM		 16688 /* Relocs that use pc_count are PC-relative forms, which will appear
16689 on something like ".long foo - ." or "movw REG, foo - .". We want
16690 calls to protected symbols to resolve directly to the function
16691 rather than going via the plt. If people want function pointer
16692 comparisons to work as expected then they should avoid writing
16693 assembly like ".long foo - .". */
ba93b8ac
DJ		 16694 if (SYMBOL_CALLS_LOCAL (info, h))
16695 {
0bdcacaf 16696 struct elf_dyn_relocs **pp;
ba93b8ac 16697
0bdcacaf 16698 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 16699 {
16700 p->count -= p->pc_count;
16701 p->pc_count = 0;
16702 if (p->count == 0)
16703 *pp = p->next;
16704 else
16705 pp = &p->next;
16706 }
16707 }
16708
4dfe6ac6 16709 if (htab->vxworks_p)
3348747a 16710 {
0bdcacaf 16711 struct elf_dyn_relocs **pp;
3348747a 16712
0bdcacaf 16713 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 16714 {
0bdcacaf 16715 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 16716 *pp = p->next;
16717 else
16718 pp = &p->next;
16719 }
16720 }
16721
ba93b8ac 16722 /* Also discard relocs on undefined weak syms with non-default
99059e56 16723 visibility. */
0bdcacaf 16724 if (eh->dyn_relocs != NULL
5e681ec4 16725 && h->root.type == bfd_link_hash_undefweak)
22d606e9 16726 {
95b03e4a
L		 16727 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16728 || UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
0bdcacaf 16729 eh->dyn_relocs = NULL;
22d606e9
AM		 16730
16731 /* Make sure undefined weak symbols are output as a dynamic
16732 symbol in PIEs. */
e8b09b87 16733 else if (htab->root.dynamic_sections_created && h->dynindx == -1
22d606e9
AM		 16734 && !h->forced_local)
16735 {
16736 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16737 return FALSE;
16738 }
16739 }
16740
67687978
PB		 16741 else if (htab->root.is_relocatable_executable && h->dynindx == -1
16742 && h->root.type == bfd_link_hash_new)
16743 {
16744 /* Output absolute symbols so that we can create relocations
16745 against them. For normal symbols we output a relocation
16746 against the section that contains them. */
16747 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16748 return FALSE;
16749 }
16750
5e681ec4
PB		 16751 }
16752 else
16753 {
16754 /* For the non-shared case, discard space for relocs against
16755 symbols which turn out to need copy relocs or are not
16756 dynamic. */
16757
f5385ebf
AM		 16758 if (!h->non_got_ref
16759 && ((h->def_dynamic
16760 && !h->def_regular)
5e681ec4
PB		 16761 || (htab->root.dynamic_sections_created
16762 && (h->root.type == bfd_link_hash_undefweak
16763 || h->root.type == bfd_link_hash_undefined))))
16764 {
16765 /* Make sure this symbol is output as a dynamic symbol.
16766 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16767 if (h->dynindx == -1 && !h->forced_local
16768 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16769 {
c152c796 16770 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16771 return FALSE;
16772 }
16773
16774 /* If that succeeded, we know we'll be keeping all the
16775 relocs. */
16776 if (h->dynindx != -1)
16777 goto keep;
16778 }
16779
0bdcacaf 16780 eh->dyn_relocs = NULL;
5e681ec4
PB		 16781
16782 keep: ;
16783 }
16784
16785 /* Finally, allocate space. */
0bdcacaf 16786 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 16787 {
0bdcacaf 16788 asection *sreloc = elf_section_data (p->sec)->sreloc;
e8b09b87 16789
34e77a92
RS		 16790 if (h->type == STT_GNU_IFUNC
16791 && eh->plt.noncall_refcount == 0
16792 && SYMBOL_REFERENCES_LOCAL (info, h))
16793 elf32_arm_allocate_irelocs (info, sreloc, p->count);
e8b09b87
CL		 16794 else if (h->dynindx != -1 && (!bfd_link_pic(info) || !info->symbolic || !h->def_regular))
16795 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
16796 else if (htab->fdpic_p && !bfd_link_pic(info))
16797 htab->srofixup->size += 4 * p->count;
34e77a92
RS		 16798 else
16799 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 16800 }
16801
16802 return TRUE;
16803}
16804
63c1f59d
AM		 16805/* Set DF_TEXTREL if we find any dynamic relocs that apply to
16806 read-only sections. */
08d1f311
DJ		 16807
16808static bfd_boolean
63c1f59d 16809maybe_set_textrel (struct elf_link_hash_entry *h, void *info_p)
08d1f311 16810{
63c1f59d 16811 asection *sec;
08d1f311 16812
63c1f59d
AM		 16813 if (h->root.type == bfd_link_hash_indirect)
16814 return TRUE;
08d1f311 16815
63c1f59d
AM		 16816 sec = readonly_dynrelocs (h);
16817 if (sec != NULL)
16818 {
16819 struct bfd_link_info *info = (struct bfd_link_info *) info_p;
08d1f311 16820
63c1f59d
AM		 16821 info->flags |= DF_TEXTREL;
16822 info->callbacks->minfo
c1c8c1ef 16823 (_("%pB: dynamic relocation against `%pT' in read-only section `%pA'\n"),
63c1f59d 16824 sec->owner, h->root.root.string, sec);
08d1f311 16825
63c1f59d
AM		 16826 /* Not an error, just cut short the traversal. */
16827 return FALSE;
08d1f311 16828 }
cb10292c 16829
08d1f311
DJ		 16830 return TRUE;
16831}
16832
d504ffc8
DJ		 16833void
16834bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
16835 int byteswap_code)
16836{
16837 struct elf32_arm_link_hash_table *globals;
16838
16839 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16840 if (globals == NULL)
16841 return;
16842
d504ffc8
DJ		 16843 globals->byteswap_code = byteswap_code;
16844}
16845
252b5132
RH		 16846/* Set the sizes of the dynamic sections. */
16847
b34976b6 16848static bfd_boolean
57e8b36a
NC		 16849elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
16850 struct bfd_link_info * info)
252b5132
RH		 16851{
16852 bfd * dynobj;
16853 asection * s;
b34976b6
AM		 16854 bfd_boolean plt;
16855 bfd_boolean relocs;
5e681ec4
PB		 16856 bfd *ibfd;
16857 struct elf32_arm_link_hash_table *htab;
252b5132 16858
5e681ec4 16859 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16860 if (htab == NULL)
16861 return FALSE;
16862
252b5132
RH		 16863 dynobj = elf_hash_table (info)->dynobj;
16864 BFD_ASSERT (dynobj != NULL);
39b41c9c 16865 check_use_blx (htab);
252b5132
RH		 16866
16867 if (elf_hash_table (info)->dynamic_sections_created)
16868 {
16869 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 16870 if (bfd_link_executable (info) && !info->nointerp)
252b5132 16871 {
3d4d4302 16872 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 16873 BFD_ASSERT (s != NULL);
eea6121a 16874 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 16875 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
16876 }
16877 }
5e681ec4
PB		 16878
16879 /* Set up .got offsets for local syms, and space for local dynamic
16880 relocs. */
c72f2fb2 16881 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 16882 {
5e681ec4
PB		 16883 bfd_signed_vma *local_got;
16884 bfd_signed_vma *end_local_got;
34e77a92 16885 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 16886 char *local_tls_type;
0855e32b 16887 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 16888 bfd_size_type locsymcount;
16889 Elf_Internal_Shdr *symtab_hdr;
16890 asection *srel;
4dfe6ac6 16891 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 16892 unsigned int symndx;
e8b09b87 16893 struct fdpic_local *local_fdpic_cnts;
5e681ec4 16894
0ffa91dd 16895 if (! is_arm_elf (ibfd))
5e681ec4
PB		 16896 continue;
16897
16898 for (s = ibfd->sections; s != NULL; s = s->next)
16899 {
0bdcacaf 16900 struct elf_dyn_relocs *p;
5e681ec4 16901
0bdcacaf 16902 for (p = (struct elf_dyn_relocs *)
99059e56 16903 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 16904 {
0bdcacaf
RS		 16905 if (!bfd_is_abs_section (p->sec)
16906 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 16907 {
16908 /* Input section has been discarded, either because
16909 it is a copy of a linkonce section or due to
16910 linker script /DISCARD/, so we'll be discarding
16911 the relocs too. */
16912 }
3348747a 16913 else if (is_vxworks
0bdcacaf 16914 && strcmp (p->sec->output_section->name,
3348747a
NS		 16915 ".tls_vars") == 0)
16916 {
16917 /* Relocations in vxworks .tls_vars sections are
16918 handled specially by the loader. */
16919 }
5e681ec4
PB		 16920 else if (p->count != 0)
16921 {
0bdcacaf 16922 srel = elf_section_data (p->sec)->sreloc;
e8b09b87
CL		 16923 if (htab->fdpic_p && !bfd_link_pic(info))
16924 htab->srofixup->size += 4 * p->count;
16925 else
16926 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 16927 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 16928 info->flags |= DF_TEXTREL;
16929 }
16930 }
16931 }
16932
16933 local_got = elf_local_got_refcounts (ibfd);
16934 if (!local_got)
16935 continue;
16936
0ffa91dd 16937 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 16938 locsymcount = symtab_hdr->sh_info;
16939 end_local_got = local_got + locsymcount;
34e77a92 16940 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 16941 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 16942 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
e8b09b87 16943 local_fdpic_cnts = elf32_arm_local_fdpic_cnts (ibfd);
34e77a92 16944 symndx = 0;
362d30a1
RS		 16945 s = htab->root.sgot;
16946 srel = htab->root.srelgot;
0855e32b 16947 for (; local_got < end_local_got;
34e77a92 16948 ++local_got, ++local_iplt_ptr, ++local_tls_type,
e8b09b87 16949 ++local_tlsdesc_gotent, ++symndx, ++local_fdpic_cnts)
5e681ec4 16950 {
0855e32b 16951 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92 16952 local_iplt = *local_iplt_ptr;
e8b09b87
CL		 16953
16954 /* FDPIC support. */
16955 if (local_fdpic_cnts->gotofffuncdesc_cnt > 0)
16956 {
16957 if (local_fdpic_cnts->funcdesc_offset == -1)
16958 {
16959 local_fdpic_cnts->funcdesc_offset = s->size;
16960 s->size += 8;
16961
16962 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16963 if (bfd_link_pic(info))
16964 elf32_arm_allocate_dynrelocs (info, srel, 1);
16965 else
16966 htab->srofixup->size += 8;
16967 }
16968 }
16969
16970 if (local_fdpic_cnts->funcdesc_cnt > 0)
16971 {
16972 if (local_fdpic_cnts->funcdesc_offset == -1)
16973 {
16974 local_fdpic_cnts->funcdesc_offset = s->size;
16975 s->size += 8;
16976
16977 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16978 if (bfd_link_pic(info))
16979 elf32_arm_allocate_dynrelocs (info, srel, 1);
16980 else
16981 htab->srofixup->size += 8;
16982 }
16983
16984 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16985 if (bfd_link_pic(info))
16986 elf32_arm_allocate_dynrelocs (info, srel, local_fdpic_cnts->funcdesc_cnt);
16987 else
16988 htab->srofixup->size += 4 * local_fdpic_cnts->funcdesc_cnt;
16989 }
16990
34e77a92
RS		 16991 if (local_iplt != NULL)
16992 {
16993 struct elf_dyn_relocs *p;
16994
16995 if (local_iplt->root.refcount > 0)
16996 {
16997 elf32_arm_allocate_plt_entry (info, TRUE,
16998 &local_iplt->root,
16999 &local_iplt->arm);
17000 if (local_iplt->arm.noncall_refcount == 0)
17001 /* All references to the PLT are calls, so all
17002 non-call references can resolve directly to the
17003 run-time target. This means that the .got entry
17004 would be the same as the .igot.plt entry, so there's
17005 no point creating both. */
17006 *local_got = 0;
17007 }
17008 else
17009 {
17010 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
17011 local_iplt->root.offset = (bfd_vma) -1;
17012 }
17013
17014 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
17015 {
17016 asection *psrel;
17017
17018 psrel = elf_section_data (p->sec)->sreloc;
17019 if (local_iplt->arm.noncall_refcount == 0)
17020 elf32_arm_allocate_irelocs (info, psrel, p->count);
17021 else
17022 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
17023 }
17024 }
5e681ec4
PB		 17025 if (*local_got > 0)
17026 {
34e77a92
RS		 17027 Elf_Internal_Sym *isym;
17028
eea6121a 17029 *local_got = s->size;
ba93b8ac
DJ		 17030 if (*local_tls_type & GOT_TLS_GD)
17031 /* TLS_GD relocs need an 8-byte structure in the GOT. */
17032 s->size += 8;
0855e32b
NS		 17033 if (*local_tls_type & GOT_TLS_GDESC)
17034 {
17035 *local_tlsdesc_gotent = htab->root.sgotplt->size
17036 - elf32_arm_compute_jump_table_size (htab);
17037 htab->root.sgotplt->size += 8;
17038 *local_got = (bfd_vma) -2;
34e77a92 17039 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 17040 reloc in the middle of .got.plt. */
99059e56 17041 htab->num_tls_desc++;
0855e32b 17042 }
ba93b8ac
DJ		 17043 if (*local_tls_type & GOT_TLS_IE)
17044 s->size += 4;
ba93b8ac 17045
0855e32b
NS		 17046 if (*local_tls_type & GOT_NORMAL)
17047 {
17048 /* If the symbol is both GD and GDESC, *local_got
17049 may have been overwritten. */
17050 *local_got = s->size;
17051 s->size += 4;
17052 }
17053
34e77a92
RS		 17054 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
17055 if (isym == NULL)
17056 return FALSE;
17057
17058 /* If all references to an STT_GNU_IFUNC PLT are calls,
17059 then all non-call references, including this GOT entry,
17060 resolve directly to the run-time target. */
17061 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
17062 && (local_iplt == NULL
17063 || local_iplt->arm.noncall_refcount == 0))
17064 elf32_arm_allocate_irelocs (info, srel, 1);
e8b09b87 17065 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC || htab->fdpic_p)
0855e32b 17066 {
e8b09b87 17067 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC)))
3064e1ff 17068 elf32_arm_allocate_dynrelocs (info, srel, 1);
e8b09b87
CL		 17069 else if (htab->fdpic_p && *local_tls_type & GOT_NORMAL)
17070 htab->srofixup->size += 4;
99059e56 17071
e8b09b87
CL		 17072 if ((bfd_link_pic (info) || htab->fdpic_p)
17073 && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 17074 {
17075 elf32_arm_allocate_dynrelocs (info,
17076 htab->root.srelplt, 1);
17077 htab->tls_trampoline = -1;
17078 }
0855e32b 17079 }
5e681ec4
PB		 17080 }
17081 else
17082 *local_got = (bfd_vma) -1;
17083 }
252b5132
RH		 17084 }
17085
ba93b8ac
DJ		 17086 if (htab->tls_ldm_got.refcount > 0)
17087 {
17088 /* Allocate two GOT entries and one dynamic relocation (if necessary)
5c5a4843 17089 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
362d30a1
RS		 17090 htab->tls_ldm_got.offset = htab->root.sgot->size;
17091 htab->root.sgot->size += 8;
0e1862bb 17092 if (bfd_link_pic (info))
47beaa6a 17093 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 17094 }
17095 else
17096 htab->tls_ldm_got.offset = -1;
17097
e8b09b87
CL		 17098 /* At the very end of the .rofixup section is a pointer to the GOT,
17099 reserve space for it. */
17100 if (htab->fdpic_p && htab->srofixup != NULL)
17101 htab->srofixup->size += 4;
17102
5e681ec4
PB		 17103 /* Allocate global sym .plt and .got entries, and space for global
17104 sym dynamic relocs. */
47beaa6a 17105 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 17106
d504ffc8 17107 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 17108 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 17109 {
0ffa91dd 17110 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 17111 continue;
17112
c7b8f16e
JB		 17113 /* Initialise mapping tables for code/data. */
17114 bfd_elf32_arm_init_maps (ibfd);
906e58ca 17115
c7b8f16e 17116 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 17117 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
17118 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
90b6238f 17119 _bfd_error_handler (_("errors encountered processing file %pB"), ibfd);
c7b8f16e 17120 }
d504ffc8 17121
3e6b1042
DJ		 17122 /* Allocate space for the glue sections now that we've sized them. */
17123 bfd_elf32_arm_allocate_interworking_sections (info);
17124
0855e32b
NS		 17125 /* For every jump slot reserved in the sgotplt, reloc_count is
17126 incremented. However, when we reserve space for TLS descriptors,
17127 it's not incremented, so in order to compute the space reserved
17128 for them, it suffices to multiply the reloc count by the jump
17129 slot size. */
17130 if (htab->root.srelplt)
17131 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
17132
17133 if (htab->tls_trampoline)
17134 {
17135 if (htab->root.splt->size == 0)
17136 htab->root.splt->size += htab->plt_header_size;
b38cadfb 17137
0855e32b
NS		 17138 htab->tls_trampoline = htab->root.splt->size;
17139 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 17140
0855e32b 17141 /* If we're not using lazy TLS relocations, don't generate the
99059e56 17142 PLT and GOT entries they require. */
0855e32b
NS		 17143 if (!(info->flags & DF_BIND_NOW))
17144 {
17145 htab->dt_tlsdesc_got = htab->root.sgot->size;
17146 htab->root.sgot->size += 4;
17147
17148 htab->dt_tlsdesc_plt = htab->root.splt->size;
17149 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
17150 }
17151 }
17152
252b5132
RH		 17153 /* The check_relocs and adjust_dynamic_symbol entry points have
17154 determined the sizes of the various dynamic sections. Allocate
17155 memory for them. */
b34976b6
AM		 17156 plt = FALSE;
17157 relocs = FALSE;
252b5132
RH		 17158 for (s = dynobj->sections; s != NULL; s = s->next)
17159 {
17160 const char * name;
252b5132
RH		 17161
17162 if ((s->flags & SEC_LINKER_CREATED) == 0)
17163 continue;
17164
17165 /* It's OK to base decisions on the section name, because none
17166 of the dynobj section names depend upon the input files. */
fd361982 17167 name = bfd_section_name (s);
252b5132 17168
34e77a92 17169 if (s == htab->root.splt)
252b5132 17170 {
c456f082
AM		 17171 /* Remember whether there is a PLT. */
17172 plt = s->size != 0;
252b5132 17173 }
0112cd26 17174 else if (CONST_STRNEQ (name, ".rel"))
252b5132 17175 {
c456f082 17176 if (s->size != 0)
252b5132 17177 {
252b5132 17178 /* Remember whether there are any reloc sections other
00a97672 17179 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 17180 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 17181 relocs = TRUE;
252b5132
RH		 17182
17183 /* We use the reloc_count field as a counter if we need
17184 to copy relocs into the output file. */
17185 s->reloc_count = 0;
17186 }
17187 }
34e77a92
RS		 17188 else if (s != htab->root.sgot
17189 && s != htab->root.sgotplt
17190 && s != htab->root.iplt
17191 && s != htab->root.igotplt
5474d94f 17192 && s != htab->root.sdynbss
e8b09b87
CL		 17193 && s != htab->root.sdynrelro
17194 && s != htab->srofixup)
252b5132
RH		 17195 {
17196 /* It's not one of our sections, so don't allocate space. */
17197 continue;
17198 }
17199
c456f082 17200 if (s->size == 0)
252b5132 17201 {
c456f082 17202 /* If we don't need this section, strip it from the
00a97672
RS		 17203 output file. This is mostly to handle .rel(a).bss and
17204 .rel(a).plt. We must create both sections in
c456f082
AM		 17205 create_dynamic_sections, because they must be created
17206 before the linker maps input sections to output
17207 sections. The linker does that before
17208 adjust_dynamic_symbol is called, and it is that
17209 function which decides whether anything needs to go
17210 into these sections. */
8423293d 17211 s->flags |= SEC_EXCLUDE;
252b5132
RH		 17212 continue;
17213 }
17214
c456f082
AM		 17215 if ((s->flags & SEC_HAS_CONTENTS) == 0)
17216 continue;
17217
252b5132 17218 /* Allocate memory for the section contents. */
21d799b5 17219 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 17220 if (s->contents == NULL)
b34976b6 17221 return FALSE;
252b5132
RH		 17222 }
17223
17224 if (elf_hash_table (info)->dynamic_sections_created)
17225 {
17226 /* Add some entries to the .dynamic section. We fill in the
17227 values later, in elf32_arm_finish_dynamic_sections, but we
17228 must add the entries now so that we get the correct size for
17229 the .dynamic section. The DT_DEBUG entry is filled in by the
17230 dynamic linker and used by the debugger. */
dc810e39 17231#define add_dynamic_entry(TAG, VAL) \
5a580b3a 17232 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 17233
0e1862bb 17234 if (bfd_link_executable (info))
252b5132 17235 {
dc810e39 17236 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 17237 return FALSE;
252b5132
RH		 17238 }
17239
17240 if (plt)
17241 {
dc810e39
AM		 17242 if ( !add_dynamic_entry (DT_PLTGOT, 0)
17243 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 17244 || !add_dynamic_entry (DT_PLTREL,
17245 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 17246 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 17247 return FALSE;
0855e32b 17248
5025eb7c
AO		 17249 if (htab->dt_tlsdesc_plt
17250 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
17251 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 17252 return FALSE;
252b5132
RH		 17253 }
17254
17255 if (relocs)
17256 {
00a97672
RS		 17257 if (htab->use_rel)
17258 {
17259 if (!add_dynamic_entry (DT_REL, 0)
17260 || !add_dynamic_entry (DT_RELSZ, 0)
17261 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
17262 return FALSE;
17263 }
17264 else
17265 {
17266 if (!add_dynamic_entry (DT_RELA, 0)
17267 || !add_dynamic_entry (DT_RELASZ, 0)
17268 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
17269 return FALSE;
17270 }
252b5132
RH		 17271 }
17272
08d1f311
DJ		 17273 /* If any dynamic relocs apply to a read-only section,
17274 then we need a DT_TEXTREL entry. */
17275 if ((info->flags & DF_TEXTREL) == 0)
63c1f59d 17276 elf_link_hash_traverse (&htab->root, maybe_set_textrel, info);
08d1f311 17277
99e4ae17 17278 if ((info->flags & DF_TEXTREL) != 0)
252b5132 17279 {
dc810e39 17280 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 17281 return FALSE;
252b5132 17282 }
7a2b07ff
NS		 17283 if (htab->vxworks_p
17284 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
17285 return FALSE;
252b5132 17286 }
8532796c 17287#undef add_dynamic_entry
252b5132 17288
b34976b6 17289 return TRUE;
252b5132
RH		 17290}
17291
0855e32b
NS		 17292/* Size sections even though they're not dynamic. We use it to setup
17293 _TLS_MODULE_BASE_, if needed. */
17294
17295static bfd_boolean
17296elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 17297 struct bfd_link_info *info)
0855e32b
NS		 17298{
17299 asection *tls_sec;
cb10292c
CL		 17300 struct elf32_arm_link_hash_table *htab;
17301
17302 htab = elf32_arm_hash_table (info);
0855e32b 17303
0e1862bb 17304 if (bfd_link_relocatable (info))
0855e32b
NS		 17305 return TRUE;
17306
17307 tls_sec = elf_hash_table (info)->tls_sec;
17308
17309 if (tls_sec)
17310 {
17311 struct elf_link_hash_entry *tlsbase;
17312
17313 tlsbase = elf_link_hash_lookup
17314 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
17315
17316 if (tlsbase)
99059e56
RM		 17317 {
17318 struct bfd_link_hash_entry *bh = NULL;
0855e32b 17319 const struct elf_backend_data *bed
99059e56 17320 = get_elf_backend_data (output_bfd);
0855e32b 17321
99059e56 17322 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 17323 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
17324 tls_sec, 0, NULL, FALSE,
17325 bed->collect, &bh)))
17326 return FALSE;
b38cadfb 17327
99059e56
RM		 17328 tlsbase->type = STT_TLS;
17329 tlsbase = (struct elf_link_hash_entry *)bh;
17330 tlsbase->def_regular = 1;
17331 tlsbase->other = STV_HIDDEN;
17332 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 17333 }
17334 }
cb10292c
CL		 17335
17336 if (htab->fdpic_p && !bfd_link_relocatable (info)
17337 && !bfd_elf_stack_segment_size (output_bfd, info,
17338 "__stacksize", DEFAULT_STACK_SIZE))
17339 return FALSE;
17340
0855e32b
NS		 17341 return TRUE;
17342}
17343
252b5132
RH		 17344/* Finish up dynamic symbol handling. We set the contents of various
17345 dynamic sections here. */
17346
b34976b6 17347static bfd_boolean
906e58ca
NC		 17348elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
17349 struct bfd_link_info * info,
17350 struct elf_link_hash_entry * h,
17351 Elf_Internal_Sym * sym)
252b5132 17352{
e5a52504 17353 struct elf32_arm_link_hash_table *htab;
b7693d02 17354 struct elf32_arm_link_hash_entry *eh;
252b5132 17355
e5a52504 17356 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17357 if (htab == NULL)
17358 return FALSE;
17359
b7693d02 17360 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 17361
17362 if (h->plt.offset != (bfd_vma) -1)
17363 {
34e77a92 17364 if (!eh->is_iplt)
e5a52504 17365 {
34e77a92 17366 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 17367 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
17368 h->dynindx, 0))
17369 return FALSE;
e5a52504 17370 }
57e8b36a 17371
f5385ebf 17372 if (!h->def_regular)
252b5132
RH		 17373 {
17374 /* Mark the symbol as undefined, rather than as defined in
3a635617 17375 the .plt section. */
252b5132 17376 sym->st_shndx = SHN_UNDEF;
3a635617 17377 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 17378 Otherwise, the PLT entry would provide a definition for
17379 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 17380 and so the symbol would never be NULL. Leave the value if
17381 there were any relocations where pointer equality matters
17382 (this is a clue for the dynamic linker, to make function
17383 pointer comparisons work between an application and shared
17384 library). */
97323ad1 17385 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 17386 sym->st_value = 0;
252b5132 17387 }
34e77a92
RS		 17388 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
17389 {
17390 /* At least one non-call relocation references this .iplt entry,
17391 so the .iplt entry is the function's canonical address. */
17392 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 17393 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 17394 sym->st_shndx = (_bfd_elf_section_from_bfd_section
17395 (output_bfd, htab->root.iplt->output_section));
17396 sym->st_value = (h->plt.offset
17397 + htab->root.iplt->output_section->vma
17398 + htab->root.iplt->output_offset);
17399 }
252b5132
RH		 17400 }
17401
f5385ebf 17402 if (h->needs_copy)
252b5132
RH		 17403 {
17404 asection * s;
947216bf 17405 Elf_Internal_Rela rel;
252b5132
RH		 17406
17407 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 17408 BFD_ASSERT (h->dynindx != -1
17409 && (h->root.type == bfd_link_hash_defined
17410 || h->root.type == bfd_link_hash_defweak));
17411
00a97672 17412 rel.r_addend = 0;
252b5132
RH		 17413 rel.r_offset = (h->root.u.def.value
17414 + h->root.u.def.section->output_section->vma
17415 + h->root.u.def.section->output_offset);
17416 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 17417 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 17418 s = htab->root.sreldynrelro;
17419 else
17420 s = htab->root.srelbss;
47beaa6a 17421 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 17422 }
17423
00a97672 17424 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
fac7bd64
CL		 17425 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17426 it is relative to the ".got" section. */
9637f6ef 17427 if (h == htab->root.hdynamic
fac7bd64 17428 || (!htab->fdpic_p && !htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 17429 sym->st_shndx = SHN_ABS;
17430
b34976b6 17431 return TRUE;
252b5132
RH		 17432}
17433
0855e32b
NS		 17434static void
17435arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17436 void *contents,
17437 const unsigned long *template, unsigned count)
17438{
17439 unsigned ix;
b38cadfb 17440
0855e32b
NS		 17441 for (ix = 0; ix != count; ix++)
17442 {
17443 unsigned long insn = template[ix];
17444
17445 /* Emit mov pc,rx if bx is not permitted. */
17446 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
17447 insn = (insn & 0xf000000f) | 0x01a0f000;
17448 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
17449 }
17450}
17451
99059e56
RM		 17452/* Install the special first PLT entry for elf32-arm-nacl. Unlike
17453 other variants, NaCl needs this entry in a static executable's
17454 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17455 zero. For .iplt really only the last bundle is useful, and .iplt
17456 could have a shorter first entry, with each individual PLT entry's
17457 relative branch calculated differently so it targets the last
17458 bundle instead of the instruction before it (labelled .Lplt_tail
17459 above). But it's simpler to keep the size and layout of PLT0
17460 consistent with the dynamic case, at the cost of some dead code at
17461 the start of .iplt and the one dead store to the stack at the start
17462 of .Lplt_tail. */
17463static void
17464arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17465 asection *plt, bfd_vma got_displacement)
17466{
17467 unsigned int i;
17468
17469 put_arm_insn (htab, output_bfd,
17470 elf32_arm_nacl_plt0_entry[0]
17471 | arm_movw_immediate (got_displacement),
17472 plt->contents + 0);
17473 put_arm_insn (htab, output_bfd,
17474 elf32_arm_nacl_plt0_entry[1]
17475 | arm_movt_immediate (got_displacement),
17476 plt->contents + 4);
17477
17478 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
17479 put_arm_insn (htab, output_bfd,
17480 elf32_arm_nacl_plt0_entry[i],
17481 plt->contents + (i * 4));
17482}
17483
252b5132
RH		 17484/* Finish up the dynamic sections. */
17485
b34976b6 17486static bfd_boolean
57e8b36a 17487elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 17488{
17489 bfd * dynobj;
17490 asection * sgot;
17491 asection * sdyn;
4dfe6ac6
NC		 17492 struct elf32_arm_link_hash_table *htab;
17493
17494 htab = elf32_arm_hash_table (info);
17495 if (htab == NULL)
17496 return FALSE;
252b5132
RH		 17497
17498 dynobj = elf_hash_table (info)->dynobj;
17499
362d30a1 17500 sgot = htab->root.sgotplt;
894891db
NC		 17501 /* A broken linker script might have discarded the dynamic sections.
17502 Catch this here so that we do not seg-fault later on. */
17503 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
17504 return FALSE;
3d4d4302 17505 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 17506
17507 if (elf_hash_table (info)->dynamic_sections_created)
17508 {
17509 asection *splt;
17510 Elf32_External_Dyn *dyncon, *dynconend;
17511
362d30a1 17512 splt = htab->root.splt;
24a1ba0f 17513 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 17514 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 17515
17516 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 17517 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 17518
252b5132
RH		 17519 for (; dyncon < dynconend; dyncon++)
17520 {
17521 Elf_Internal_Dyn dyn;
17522 const char * name;
17523 asection * s;
17524
17525 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
17526
17527 switch (dyn.d_tag)
17528 {
229fcec5
MM		 17529 unsigned int type;
17530
252b5132 17531 default:
7a2b07ff
NS		 17532 if (htab->vxworks_p
17533 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
17534 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 17535 break;
17536
229fcec5
MM		 17537 case DT_HASH:
17538 name = ".hash";
17539 goto get_vma_if_bpabi;
17540 case DT_STRTAB:
17541 name = ".dynstr";
17542 goto get_vma_if_bpabi;
17543 case DT_SYMTAB:
17544 name = ".dynsym";
17545 goto get_vma_if_bpabi;
c0042f5d
MM		 17546 case DT_VERSYM:
17547 name = ".gnu.version";
17548 goto get_vma_if_bpabi;
17549 case DT_VERDEF:
17550 name = ".gnu.version_d";
17551 goto get_vma_if_bpabi;
17552 case DT_VERNEED:
17553 name = ".gnu.version_r";
17554 goto get_vma_if_bpabi;
17555
252b5132 17556 case DT_PLTGOT:
4ade44b7 17557 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 17558 goto get_vma;
17559 case DT_JMPREL:
00a97672 17560 name = RELOC_SECTION (htab, ".plt");
252b5132 17561 get_vma:
4ade44b7 17562 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 17563 if (s == NULL)
17564 {
4eca0228 17565 _bfd_error_handler
4ade44b7 17566 (_("could not find section %s"), name);
05456594
NC		 17567 bfd_set_error (bfd_error_invalid_operation);
17568 return FALSE;
17569 }
229fcec5 17570 if (!htab->symbian_p)
4ade44b7 17571 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 17572 else
17573 /* In the BPABI, tags in the PT_DYNAMIC section point
17574 at the file offset, not the memory address, for the
17575 convenience of the post linker. */
4ade44b7 17576 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 17577 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17578 break;
17579
229fcec5
MM		 17580 get_vma_if_bpabi:
17581 if (htab->symbian_p)
17582 goto get_vma;
17583 break;
17584
252b5132 17585 case DT_PLTRELSZ:
362d30a1 17586 s = htab->root.srelplt;
252b5132 17587 BFD_ASSERT (s != NULL);
eea6121a 17588 dyn.d_un.d_val = s->size;
252b5132
RH		 17589 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17590 break;
906e58ca 17591
252b5132 17592 case DT_RELSZ:
00a97672 17593 case DT_RELASZ:
229fcec5
MM		 17594 case DT_REL:
17595 case DT_RELA:
229fcec5
MM		 17596 /* In the BPABI, the DT_REL tag must point at the file
17597 offset, not the VMA, of the first relocation
17598 section. So, we use code similar to that in
17599 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 17600 relocation section, since relocation sections are
17601 never allocated under the BPABI. PLT relocs are also
17602 included. */
229fcec5
MM		 17603 if (htab->symbian_p)
17604 {
17605 unsigned int i;
17606 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
17607 ? SHT_REL : SHT_RELA);
17608 dyn.d_un.d_val = 0;
17609 for (i = 1; i < elf_numsections (output_bfd); i++)
17610 {
906e58ca 17611 Elf_Internal_Shdr *hdr
229fcec5
MM		 17612 = elf_elfsections (output_bfd)[i];
17613 if (hdr->sh_type == type)
17614 {
906e58ca 17615 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 17616 || dyn.d_tag == DT_RELASZ)
17617 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 17618 else if ((ufile_ptr) hdr->sh_offset
17619 <= dyn.d_un.d_val - 1)
229fcec5
MM		 17620 dyn.d_un.d_val = hdr->sh_offset;
17621 }
17622 }
17623 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17624 }
252b5132 17625 break;
88f7bcd5 17626
0855e32b 17627 case DT_TLSDESC_PLT:
99059e56 17628 s = htab->root.splt;
0855e32b
NS		 17629 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
17630 + htab->dt_tlsdesc_plt);
17631 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17632 break;
17633
17634 case DT_TLSDESC_GOT:
99059e56 17635 s = htab->root.sgot;
0855e32b 17636 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 17637 + htab->dt_tlsdesc_got);
0855e32b
NS		 17638 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17639 break;
17640
88f7bcd5
NC		 17641 /* Set the bottom bit of DT_INIT/FINI if the
17642 corresponding function is Thumb. */
17643 case DT_INIT:
17644 name = info->init_function;
17645 goto get_sym;
17646 case DT_FINI:
17647 name = info->fini_function;
17648 get_sym:
17649 /* If it wasn't set by elf_bfd_final_link
4cc11e76 17650 then there is nothing to adjust. */
88f7bcd5
NC		 17651 if (dyn.d_un.d_val != 0)
17652 {
17653 struct elf_link_hash_entry * eh;
17654
17655 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 17656 FALSE, FALSE, TRUE);
39d911fc
TP		 17657 if (eh != NULL
17658 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
17659 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 17660 {
17661 dyn.d_un.d_val |= 1;
b34976b6 17662 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 17663 }
17664 }
17665 break;
252b5132
RH		 17666 }
17667 }
17668
24a1ba0f 17669 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 17670 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 17671 {
00a97672
RS		 17672 const bfd_vma *plt0_entry;
17673 bfd_vma got_address, plt_address, got_displacement;
17674
17675 /* Calculate the addresses of the GOT and PLT. */
17676 got_address = sgot->output_section->vma + sgot->output_offset;
17677 plt_address = splt->output_section->vma + splt->output_offset;
17678
17679 if (htab->vxworks_p)
17680 {
17681 /* The VxWorks GOT is relocated by the dynamic linker.
17682 Therefore, we must emit relocations rather than simply
17683 computing the values now. */
17684 Elf_Internal_Rela rel;
17685
17686 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 17687 put_arm_insn (htab, output_bfd, plt0_entry[0],
17688 splt->contents + 0);
17689 put_arm_insn (htab, output_bfd, plt0_entry[1],
17690 splt->contents + 4);
17691 put_arm_insn (htab, output_bfd, plt0_entry[2],
17692 splt->contents + 8);
00a97672
RS		 17693 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
17694
8029a119 17695 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 17696 rel.r_offset = plt_address + 12;
17697 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17698 rel.r_addend = 0;
17699 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
17700 htab->srelplt2->contents);
17701 }
b38cadfb 17702 else if (htab->nacl_p)
99059e56
RM		 17703 arm_nacl_put_plt0 (htab, output_bfd, splt,
17704 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 17705 else if (using_thumb_only (htab))
17706 {
17707 got_displacement = got_address - (plt_address + 12);
17708
17709 plt0_entry = elf32_thumb2_plt0_entry;
17710 put_arm_insn (htab, output_bfd, plt0_entry[0],
17711 splt->contents + 0);
17712 put_arm_insn (htab, output_bfd, plt0_entry[1],
17713 splt->contents + 4);
17714 put_arm_insn (htab, output_bfd, plt0_entry[2],
17715 splt->contents + 8);
17716
17717 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
17718 }
00a97672
RS		 17719 else
17720 {
17721 got_displacement = got_address - (plt_address + 16);
17722
17723 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 17724 put_arm_insn (htab, output_bfd, plt0_entry[0],
17725 splt->contents + 0);
17726 put_arm_insn (htab, output_bfd, plt0_entry[1],
17727 splt->contents + 4);
17728 put_arm_insn (htab, output_bfd, plt0_entry[2],
17729 splt->contents + 8);
17730 put_arm_insn (htab, output_bfd, plt0_entry[3],
17731 splt->contents + 12);
5e681ec4 17732
5e681ec4 17733#ifdef FOUR_WORD_PLT
00a97672
RS		 17734 /* The displacement value goes in the otherwise-unused
17735 last word of the second entry. */
17736 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 17737#else
00a97672 17738 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 17739#endif
00a97672 17740 }
f7a74f8c 17741 }
252b5132
RH		 17742
17743 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17744 really seem like the right value. */
74541ad4
AM		 17745 if (splt->output_section->owner == output_bfd)
17746 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 17747
0855e32b
NS		 17748 if (htab->dt_tlsdesc_plt)
17749 {
17750 bfd_vma got_address
17751 = sgot->output_section->vma + sgot->output_offset;
17752 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
17753 + htab->root.sgot->output_offset);
17754 bfd_vma plt_address
17755 = splt->output_section->vma + splt->output_offset;
17756
b38cadfb 17757 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17758 splt->contents + htab->dt_tlsdesc_plt,
17759 dl_tlsdesc_lazy_trampoline, 6);
17760
17761 bfd_put_32 (output_bfd,
17762 gotplt_address + htab->dt_tlsdesc_got
17763 - (plt_address + htab->dt_tlsdesc_plt)
17764 - dl_tlsdesc_lazy_trampoline[6],
17765 splt->contents + htab->dt_tlsdesc_plt + 24);
17766 bfd_put_32 (output_bfd,
17767 got_address - (plt_address + htab->dt_tlsdesc_plt)
17768 - dl_tlsdesc_lazy_trampoline[7],
17769 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
17770 }
17771
17772 if (htab->tls_trampoline)
17773 {
b38cadfb 17774 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17775 splt->contents + htab->tls_trampoline,
17776 tls_trampoline, 3);
17777#ifdef FOUR_WORD_PLT
17778 bfd_put_32 (output_bfd, 0x00000000,
17779 splt->contents + htab->tls_trampoline + 12);
b38cadfb 17780#endif
0855e32b
NS		 17781 }
17782
0e1862bb
L		 17783 if (htab->vxworks_p
17784 && !bfd_link_pic (info)
17785 && htab->root.splt->size > 0)
00a97672
RS		 17786 {
17787 /* Correct the .rel(a).plt.unloaded relocations. They will have
17788 incorrect symbol indexes. */
17789 int num_plts;
eed62c48 17790 unsigned char *p;
00a97672 17791
362d30a1 17792 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 17793 / htab->plt_entry_size);
17794 p = htab->srelplt2->contents + RELOC_SIZE (htab);
17795
17796 for (; num_plts; num_plts--)
17797 {
17798 Elf_Internal_Rela rel;
17799
17800 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17801 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17802 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17803 p += RELOC_SIZE (htab);
17804
17805 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17806 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
17807 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17808 p += RELOC_SIZE (htab);
17809 }
17810 }
252b5132
RH		 17811 }
17812
99059e56
RM		 17813 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
17814 /* NaCl uses a special first entry in .iplt too. */
17815 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
17816
252b5132 17817 /* Fill in the first three entries in the global offset table. */
229fcec5 17818 if (sgot)
252b5132 17819 {
229fcec5
MM		 17820 if (sgot->size > 0)
17821 {
17822 if (sdyn == NULL)
17823 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
17824 else
17825 bfd_put_32 (output_bfd,
17826 sdyn->output_section->vma + sdyn->output_offset,
17827 sgot->contents);
17828 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
17829 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
17830 }
252b5132 17831
229fcec5
MM		 17832 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
17833 }
252b5132 17834
e8b09b87
CL		 17835 /* At the very end of the .rofixup section is a pointer to the GOT. */
17836 if (htab->fdpic_p && htab->srofixup != NULL)
17837 {
17838 struct elf_link_hash_entry *hgot = htab->root.hgot;
17839
17840 bfd_vma got_value = hgot->root.u.def.value
17841 + hgot->root.u.def.section->output_section->vma
17842 + hgot->root.u.def.section->output_offset;
17843
17844 arm_elf_add_rofixup(output_bfd, htab->srofixup, got_value);
17845
17846 /* Make sure we allocated and generated the same number of fixups. */
17847 BFD_ASSERT (htab->srofixup->reloc_count * 4 == htab->srofixup->size);
17848 }
17849
b34976b6 17850 return TRUE;
252b5132
RH		 17851}
17852
ed7e9d0b
AM		 17853static bfd_boolean
17854elf32_arm_init_file_header (bfd *abfd, struct bfd_link_info *link_info)
ba96a88f 17855{
9b485d32 17856 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 17857 struct elf32_arm_link_hash_table *globals;
ac4c9b04 17858 struct elf_segment_map *m;
ba96a88f 17859
ed7e9d0b
AM		 17860 if (!_bfd_elf_init_file_header (abfd, link_info))
17861 return FALSE;
17862
ba96a88f
NC		 17863 i_ehdrp = elf_elfheader (abfd);
17864
94a3258f
PB		 17865 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
17866 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
ba96a88f 17867 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 17868
93204d3a
PB		 17869 if (link_info)
17870 {
17871 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 17872 if (globals != NULL && globals->byteswap_code)
93204d3a 17873 i_ehdrp->e_flags |= EF_ARM_BE8;
18a20338
CL		 17874
17875 if (globals->fdpic_p)
17876 i_ehdrp->e_ident[EI_OSABI] |= ELFOSABI_ARM_FDPIC;
93204d3a 17877 }
3bfcb652
NC		 17878
17879 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
17880 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
17881 {
17882 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 17883 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 17884 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
17885 else
17886 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
17887 }
ac4c9b04
MG		 17888
17889 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 17890 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 17891 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
17892 {
17893 unsigned int j;
17894
17895 if (m->count == 0)
17896 continue;
17897 for (j = 0; j < m->count; j++)
17898 {
f0728ee3 17899 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 17900 break;
17901 }
17902 if (j == m->count)
17903 {
17904 m->p_flags = PF_X;
17905 m->p_flags_valid = 1;
17906 }
17907 }
ed7e9d0b 17908 return TRUE;
ba96a88f
NC		 17909}
17910
99e4ae17 17911static enum elf_reloc_type_class
7e612e98
AM		 17912elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
17913 const asection *rel_sec ATTRIBUTE_UNUSED,
17914 const Elf_Internal_Rela *rela)
99e4ae17 17915{
f51e552e 17916 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 17917 {
17918 case R_ARM_RELATIVE:
17919 return reloc_class_relative;
17920 case R_ARM_JUMP_SLOT:
17921 return reloc_class_plt;
17922 case R_ARM_COPY:
17923 return reloc_class_copy;
109575d7
JW		 17924 case R_ARM_IRELATIVE:
17925 return reloc_class_ifunc;
99e4ae17
AJ		 17926 default:
17927 return reloc_class_normal;
17928 }
17929}
17930
e489d0ae 17931static void
cc364be6 17932arm_final_write_processing (bfd *abfd)
e16bb312 17933{
5a6c6817 17934 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 17935}
17936
cc364be6
AM		 17937static bfd_boolean
17938elf32_arm_final_write_processing (bfd *abfd)
06f44071 17939{
cc364be6
AM		 17940 arm_final_write_processing (abfd);
17941 return _bfd_elf_final_write_processing (abfd);
06f44071
AM		 17942}
17943
40a18ebd
NC		 17944/* Return TRUE if this is an unwinding table entry. */
17945
17946static bfd_boolean
17947is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
17948{
0112cd26
NC		 17949 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
17950 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 17951}
17952
17953
17954/* Set the type and flags for an ARM section. We do this by
17955 the section name, which is a hack, but ought to work. */
17956
17957static bfd_boolean
17958elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
17959{
17960 const char * name;
17961
fd361982 17962 name = bfd_section_name (sec);
40a18ebd
NC		 17963
17964 if (is_arm_elf_unwind_section_name (abfd, name))
17965 {
17966 hdr->sh_type = SHT_ARM_EXIDX;
17967 hdr->sh_flags |= SHF_LINK_ORDER;
17968 }
ac4c9b04 17969
f0728ee3
AV		 17970 if (sec->flags & SEC_ELF_PURECODE)
17971 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 17972
40a18ebd
NC		 17973 return TRUE;
17974}
17975
6dc132d9
L		 17976/* Handle an ARM specific section when reading an object file. This is
17977 called when bfd_section_from_shdr finds a section with an unknown
17978 type. */
40a18ebd
NC		 17979
17980static bfd_boolean
17981elf32_arm_section_from_shdr (bfd *abfd,
17982 Elf_Internal_Shdr * hdr,
6dc132d9
L		 17983 const char *name,
17984 int shindex)
40a18ebd
NC		 17985{
17986 /* There ought to be a place to keep ELF backend specific flags, but
17987 at the moment there isn't one. We just keep track of the
17988 sections by their name, instead. Fortunately, the ABI gives
17989 names for all the ARM specific sections, so we will probably get
17990 away with this. */
17991 switch (hdr->sh_type)
17992 {
17993 case SHT_ARM_EXIDX:
0951f019
RE		 17994 case SHT_ARM_PREEMPTMAP:
17995 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 17996 break;
17997
17998 default:
17999 return FALSE;
18000 }
18001
6dc132d9 18002 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 18003 return FALSE;
18004
18005 return TRUE;
18006}
e489d0ae 18007
44444f50
NC		 18008static _arm_elf_section_data *
18009get_arm_elf_section_data (asection * sec)
18010{
47b2e99c
JZ		 18011 if (sec && sec->owner && is_arm_elf (sec->owner))
18012 return elf32_arm_section_data (sec);
44444f50
NC		 18013 else
18014 return NULL;
8e3de13a
NC		 18015}
18016
4e617b1e
PB		 18017typedef struct
18018{
57402f1e 18019 void *flaginfo;
4e617b1e 18020 struct bfd_link_info *info;
91a5743d
PB		 18021 asection *sec;
18022 int sec_shndx;
6e0b88f1
AM		 18023 int (*func) (void *, const char *, Elf_Internal_Sym *,
18024 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 18025} output_arch_syminfo;
18026
18027enum map_symbol_type
18028{
18029 ARM_MAP_ARM,
18030 ARM_MAP_THUMB,
18031 ARM_MAP_DATA
18032};
18033
18034
7413f23f 18035/* Output a single mapping symbol. */
4e617b1e
PB		 18036
18037static bfd_boolean
7413f23f
DJ		 18038elf32_arm_output_map_sym (output_arch_syminfo *osi,
18039 enum map_symbol_type type,
18040 bfd_vma offset)
4e617b1e
PB		 18041{
18042 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 18043 Elf_Internal_Sym sym;
18044
91a5743d
PB		 18045 sym.st_value = osi->sec->output_section->vma
18046 + osi->sec->output_offset
18047 + offset;
4e617b1e
PB		 18048 sym.st_size = 0;
18049 sym.st_other = 0;
18050 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 18051 sym.st_shndx = osi->sec_shndx;
35fc36a8 18052 sym.st_target_internal = 0;
fe33d2fa 18053 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 18054 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 18055}
18056
34e77a92
RS		 18057/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
18058 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 18059
18060static bfd_boolean
34e77a92
RS		 18061elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
18062 bfd_boolean is_iplt_entry_p,
18063 union gotplt_union *root_plt,
18064 struct arm_plt_info *arm_plt)
4e617b1e 18065{
4e617b1e 18066 struct elf32_arm_link_hash_table *htab;
34e77a92 18067 bfd_vma addr, plt_header_size;
4e617b1e 18068
34e77a92 18069 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 18070 return TRUE;
18071
4dfe6ac6
NC		 18072 htab = elf32_arm_hash_table (osi->info);
18073 if (htab == NULL)
18074 return FALSE;
18075
34e77a92
RS		 18076 if (is_iplt_entry_p)
18077 {
18078 osi->sec = htab->root.iplt;
18079 plt_header_size = 0;
18080 }
18081 else
18082 {
18083 osi->sec = htab->root.splt;
18084 plt_header_size = htab->plt_header_size;
18085 }
18086 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
18087 (osi->info->output_bfd, osi->sec->output_section));
18088
18089 addr = root_plt->offset & -2;
4e617b1e
PB		 18090 if (htab->symbian_p)
18091 {
7413f23f 18092 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18093 return FALSE;
7413f23f 18094 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 18095 return FALSE;
18096 }
18097 else if (htab->vxworks_p)
18098 {
7413f23f 18099 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18100 return FALSE;
7413f23f 18101 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 18102 return FALSE;
7413f23f 18103 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 18104 return FALSE;
7413f23f 18105 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 18106 return FALSE;
18107 }
b38cadfb
NC		 18108 else if (htab->nacl_p)
18109 {
18110 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
18111 return FALSE;
18112 }
7801f98f
CL		 18113 else if (htab->fdpic_p)
18114 {
59029f57
CL		 18115 enum map_symbol_type type = using_thumb_only(htab)
18116 ? ARM_MAP_THUMB
18117 : ARM_MAP_ARM;
18118
7801f98f 18119 if (elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt))
4b24dd1a
AM		 18120 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
18121 return FALSE;
59029f57 18122 if (!elf32_arm_output_map_sym (osi, type, addr))
4b24dd1a 18123 return FALSE;
7801f98f 18124 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 16))
4b24dd1a 18125 return FALSE;
7801f98f 18126 if (htab->plt_entry_size == 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry))
4b24dd1a
AM		 18127 if (!elf32_arm_output_map_sym (osi, type, addr + 24))
18128 return FALSE;
7801f98f 18129 }
eed94f8f
NC		 18130 else if (using_thumb_only (htab))
18131 {
18132 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
18133 return FALSE;
6a631e86 18134 }
4e617b1e
PB		 18135 else
18136 {
34e77a92 18137 bfd_boolean thumb_stub_p;
bd97cb95 18138
34e77a92
RS		 18139 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
18140 if (thumb_stub_p)
4e617b1e 18141 {
7413f23f 18142 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 18143 return FALSE;
18144 }
18145#ifdef FOUR_WORD_PLT
7413f23f 18146 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18147 return FALSE;
7413f23f 18148 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 18149 return FALSE;
18150#else
906e58ca 18151 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 18152 so only need to output a mapping symbol for the first PLT entry and
18153 entries with thumb thunks. */
34e77a92 18154 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 18155 {
7413f23f 18156 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 18157 return FALSE;
18158 }
18159#endif
18160 }
18161
18162 return TRUE;
18163}
18164
34e77a92
RS		 18165/* Output mapping symbols for PLT entries associated with H. */
18166
18167static bfd_boolean
18168elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
18169{
18170 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
18171 struct elf32_arm_link_hash_entry *eh;
18172
18173 if (h->root.type == bfd_link_hash_indirect)
18174 return TRUE;
18175
18176 if (h->root.type == bfd_link_hash_warning)
18177 /* When warning symbols are created, they **replace** the "real"
18178 entry in the hash table, thus we never get to see the real
18179 symbol in a hash traversal. So look at it now. */
18180 h = (struct elf_link_hash_entry *) h->root.u.i.link;
18181
18182 eh = (struct elf32_arm_link_hash_entry *) h;
18183 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
18184 &h->plt, &eh->plt);
18185}
18186
4f4faa4d
TP		 18187/* Bind a veneered symbol to its veneer identified by its hash entry
18188 STUB_ENTRY. The veneered location thus loose its symbol. */
18189
18190static void
18191arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
18192{
18193 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
18194
18195 BFD_ASSERT (hash);
18196 hash->root.root.u.def.section = stub_entry->stub_sec;
18197 hash->root.root.u.def.value = stub_entry->stub_offset;
18198 hash->root.size = stub_entry->stub_size;
18199}
18200
7413f23f
DJ		 18201/* Output a single local symbol for a generated stub. */
18202
18203static bfd_boolean
18204elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
18205 bfd_vma offset, bfd_vma size)
18206{
7413f23f
DJ		 18207 Elf_Internal_Sym sym;
18208
7413f23f
DJ		 18209 sym.st_value = osi->sec->output_section->vma
18210 + osi->sec->output_offset
18211 + offset;
18212 sym.st_size = size;
18213 sym.st_other = 0;
18214 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
18215 sym.st_shndx = osi->sec_shndx;
35fc36a8 18216 sym.st_target_internal = 0;
57402f1e 18217 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 18218}
4e617b1e 18219
da5938a2 18220static bfd_boolean
8029a119
NC		 18221arm_map_one_stub (struct bfd_hash_entry * gen_entry,
18222 void * in_arg)
da5938a2
NC		 18223{
18224 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 18225 asection *stub_sec;
18226 bfd_vma addr;
7413f23f 18227 char *stub_name;
9a008db3 18228 output_arch_syminfo *osi;
d3ce72d0 18229 const insn_sequence *template_sequence;
461a49ca
DJ		 18230 enum stub_insn_type prev_type;
18231 int size;
18232 int i;
18233 enum map_symbol_type sym_type;
da5938a2
NC		 18234
18235 /* Massage our args to the form they really have. */
18236 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 18237 osi = (output_arch_syminfo *) in_arg;
da5938a2 18238
da5938a2
NC		 18239 stub_sec = stub_entry->stub_sec;
18240
18241 /* Ensure this stub is attached to the current section being
7413f23f 18242 processed. */
da5938a2
NC		 18243 if (stub_sec != osi->sec)
18244 return TRUE;
18245
7413f23f 18246 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 18247 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 18248
18249 if (arm_stub_sym_claimed (stub_entry->stub_type))
18250 arm_stub_claim_sym (stub_entry);
18251 else
7413f23f 18252 {
4f4faa4d
TP		 18253 stub_name = stub_entry->output_name;
18254 switch (template_sequence[0].type)
18255 {
18256 case ARM_TYPE:
18257 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
18258 stub_entry->stub_size))
18259 return FALSE;
18260 break;
18261 case THUMB16_TYPE:
18262 case THUMB32_TYPE:
18263 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
18264 stub_entry->stub_size))
18265 return FALSE;
18266 break;
18267 default:
18268 BFD_FAIL ();
18269 return 0;
18270 }
7413f23f 18271 }
da5938a2 18272
461a49ca
DJ		 18273 prev_type = DATA_TYPE;
18274 size = 0;
18275 for (i = 0; i < stub_entry->stub_template_size; i++)
18276 {
d3ce72d0 18277 switch (template_sequence[i].type)
461a49ca
DJ		 18278 {
18279 case ARM_TYPE:
18280 sym_type = ARM_MAP_ARM;
18281 break;
18282
18283 case THUMB16_TYPE:
48229727 18284 case THUMB32_TYPE:
461a49ca
DJ		 18285 sym_type = ARM_MAP_THUMB;
18286 break;
18287
18288 case DATA_TYPE:
18289 sym_type = ARM_MAP_DATA;
18290 break;
18291
18292 default:
18293 BFD_FAIL ();
4e31c731 18294 return FALSE;
461a49ca
DJ		 18295 }
18296
d3ce72d0 18297 if (template_sequence[i].type != prev_type)
461a49ca 18298 {
d3ce72d0 18299 prev_type = template_sequence[i].type;
461a49ca
DJ		 18300 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
18301 return FALSE;
18302 }
18303
d3ce72d0 18304 switch (template_sequence[i].type)
461a49ca
DJ		 18305 {
18306 case ARM_TYPE:
48229727 18307 case THUMB32_TYPE:
461a49ca
DJ		 18308 size += 4;
18309 break;
18310
18311 case THUMB16_TYPE:
18312 size += 2;
18313 break;
18314
18315 case DATA_TYPE:
18316 size += 4;
18317 break;
18318
18319 default:
18320 BFD_FAIL ();
4e31c731 18321 return FALSE;
461a49ca
DJ		 18322 }
18323 }
18324
da5938a2
NC		 18325 return TRUE;
18326}
18327
33811162
DG		 18328/* Output mapping symbols for linker generated sections,
18329 and for those data-only sections that do not have a
18330 $d. */
4e617b1e
PB		 18331
18332static bfd_boolean
18333elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 18334 struct bfd_link_info *info,
57402f1e 18335 void *flaginfo,
6e0b88f1
AM		 18336 int (*func) (void *, const char *,
18337 Elf_Internal_Sym *,
18338 asection *,
18339 struct elf_link_hash_entry *))
4e617b1e
PB		 18340{
18341 output_arch_syminfo osi;
18342 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 18343 bfd_vma offset;
18344 bfd_size_type size;
33811162 18345 bfd *input_bfd;
4e617b1e
PB		 18346
18347 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 18348 if (htab == NULL)
18349 return FALSE;
18350
906e58ca 18351 check_use_blx (htab);
91a5743d 18352
57402f1e 18353 osi.flaginfo = flaginfo;
4e617b1e
PB		 18354 osi.info = info;
18355 osi.func = func;
906e58ca 18356
33811162
DG		 18357 /* Add a $d mapping symbol to data-only sections that
18358 don't have any mapping symbol. This may result in (harmless) redundant
18359 mapping symbols. */
18360 for (input_bfd = info->input_bfds;
18361 input_bfd != NULL;
c72f2fb2 18362 input_bfd = input_bfd->link.next)
33811162
DG		 18363 {
18364 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
18365 for (osi.sec = input_bfd->sections;
18366 osi.sec != NULL;
18367 osi.sec = osi.sec->next)
18368 {
18369 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 18370 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
18371 != 0)
33811162
DG		 18372 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
18373 == SEC_HAS_CONTENTS
18374 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 18375 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 18376 && osi.sec->size > 0
18377 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 18378 {
18379 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18380 (output_bfd, osi.sec->output_section);
18381 if (osi.sec_shndx != (int)SHN_BAD)
18382 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
18383 }
18384 }
18385 }
18386
91a5743d
PB		 18387 /* ARM->Thumb glue. */
18388 if (htab->arm_glue_size > 0)
18389 {
3d4d4302
AM		 18390 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18391 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 18392
18393 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18394 (output_bfd, osi.sec->output_section);
0e1862bb 18395 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 18396 || htab->pic_veneer)
18397 size = ARM2THUMB_PIC_GLUE_SIZE;
18398 else if (htab->use_blx)
18399 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
18400 else
18401 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 18402
91a5743d
PB		 18403 for (offset = 0; offset < htab->arm_glue_size; offset += size)
18404 {
7413f23f
DJ		 18405 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
18406 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 18407 }
18408 }
18409
18410 /* Thumb->ARM glue. */
18411 if (htab->thumb_glue_size > 0)
18412 {
3d4d4302
AM		 18413 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18414 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 18415
18416 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18417 (output_bfd, osi.sec->output_section);
18418 size = THUMB2ARM_GLUE_SIZE;
18419
18420 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
18421 {
7413f23f
DJ		 18422 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
18423 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 18424 }
18425 }
18426
845b51d6
PB		 18427 /* ARMv4 BX veneers. */
18428 if (htab->bx_glue_size > 0)
18429 {
3d4d4302
AM		 18430 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18431 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 18432
18433 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18434 (output_bfd, osi.sec->output_section);
18435
7413f23f 18436 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 18437 }
18438
8029a119
NC		 18439 /* Long calls stubs. */
18440 if (htab->stub_bfd && htab->stub_bfd->sections)
18441 {
da5938a2 18442 asection* stub_sec;
8029a119 18443
da5938a2
NC		 18444 for (stub_sec = htab->stub_bfd->sections;
18445 stub_sec != NULL;
8029a119
NC		 18446 stub_sec = stub_sec->next)
18447 {
18448 /* Ignore non-stub sections. */
18449 if (!strstr (stub_sec->name, STUB_SUFFIX))
18450 continue;
da5938a2 18451
8029a119 18452 osi.sec = stub_sec;
da5938a2 18453
8029a119
NC		 18454 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18455 (output_bfd, osi.sec->output_section);
da5938a2 18456
8029a119
NC		 18457 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
18458 }
18459 }
da5938a2 18460
91a5743d 18461 /* Finally, output mapping symbols for the PLT. */
34e77a92 18462 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 18463 {
34e77a92
RS		 18464 osi.sec = htab->root.splt;
18465 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18466 (output_bfd, osi.sec->output_section));
18467
18468 /* Output mapping symbols for the plt header. SymbianOS does not have a
18469 plt header. */
18470 if (htab->vxworks_p)
18471 {
18472 /* VxWorks shared libraries have no PLT header. */
0e1862bb 18473 if (!bfd_link_pic (info))
34e77a92
RS		 18474 {
18475 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18476 return FALSE;
18477 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18478 return FALSE;
18479 }
18480 }
b38cadfb
NC		 18481 else if (htab->nacl_p)
18482 {
18483 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18484 return FALSE;
18485 }
59029f57 18486 else if (using_thumb_only (htab) && !htab->fdpic_p)
eed94f8f
NC		 18487 {
18488 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
18489 return FALSE;
18490 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18491 return FALSE;
18492 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
18493 return FALSE;
18494 }
e8b09b87 18495 else if (!htab->symbian_p && !htab->fdpic_p)
4e617b1e 18496 {
7413f23f 18497 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 18498 return FALSE;
34e77a92
RS		 18499#ifndef FOUR_WORD_PLT
18500 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 18501 return FALSE;
34e77a92 18502#endif
4e617b1e
PB		 18503 }
18504 }
99059e56
RM		 18505 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
18506 {
18507 /* NaCl uses a special first entry in .iplt too. */
18508 osi.sec = htab->root.iplt;
18509 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18510 (output_bfd, osi.sec->output_section));
18511 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18512 return FALSE;
18513 }
34e77a92
RS		 18514 if ((htab->root.splt && htab->root.splt->size > 0)
18515 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 18516 {
34e77a92
RS		 18517 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
18518 for (input_bfd = info->input_bfds;
18519 input_bfd != NULL;
c72f2fb2 18520 input_bfd = input_bfd->link.next)
34e77a92
RS		 18521 {
18522 struct arm_local_iplt_info **local_iplt;
18523 unsigned int i, num_syms;
4e617b1e 18524
34e77a92
RS		 18525 local_iplt = elf32_arm_local_iplt (input_bfd);
18526 if (local_iplt != NULL)
18527 {
18528 num_syms = elf_symtab_hdr (input_bfd).sh_info;
18529 for (i = 0; i < num_syms; i++)
18530 if (local_iplt[i] != NULL
18531 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
18532 &local_iplt[i]->root,
18533 &local_iplt[i]->arm))
18534 return FALSE;
18535 }
18536 }
18537 }
0855e32b
NS		 18538 if (htab->dt_tlsdesc_plt != 0)
18539 {
18540 /* Mapping symbols for the lazy tls trampoline. */
18541 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
18542 return FALSE;
b38cadfb 18543
0855e32b
NS		 18544 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18545 htab->dt_tlsdesc_plt + 24))
18546 return FALSE;
18547 }
18548 if (htab->tls_trampoline != 0)
18549 {
18550 /* Mapping symbols for the tls trampoline. */
18551 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
18552 return FALSE;
18553#ifdef FOUR_WORD_PLT
18554 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18555 htab->tls_trampoline + 12))
18556 return FALSE;
b38cadfb 18557#endif
0855e32b 18558 }
b38cadfb 18559
4e617b1e
PB		 18560 return TRUE;
18561}
18562
54ddd295
TP		 18563/* Filter normal symbols of CMSE entry functions of ABFD to include in
18564 the import library. All SYMCOUNT symbols of ABFD can be examined
18565 from their pointers in SYMS. Pointers of symbols to keep should be
18566 stored continuously at the beginning of that array.
18567
18568 Returns the number of symbols to keep. */
18569
18570static unsigned int
18571elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18572 struct bfd_link_info *info,
18573 asymbol **syms, long symcount)
18574{
18575 size_t maxnamelen;
18576 char *cmse_name;
18577 long src_count, dst_count = 0;
18578 struct elf32_arm_link_hash_table *htab;
18579
18580 htab = elf32_arm_hash_table (info);
18581 if (!htab->stub_bfd || !htab->stub_bfd->sections)
18582 symcount = 0;
18583
18584 maxnamelen = 128;
18585 cmse_name = (char *) bfd_malloc (maxnamelen);
18586 for (src_count = 0; src_count < symcount; src_count++)
18587 {
18588 struct elf32_arm_link_hash_entry *cmse_hash;
18589 asymbol *sym;
18590 flagword flags;
18591 char *name;
18592 size_t namelen;
18593
18594 sym = syms[src_count];
18595 flags = sym->flags;
18596 name = (char *) bfd_asymbol_name (sym);
18597
18598 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
18599 continue;
18600 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
18601 continue;
18602
18603 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
18604 if (namelen > maxnamelen)
18605 {
18606 cmse_name = (char *)
18607 bfd_realloc (cmse_name, namelen);
18608 maxnamelen = namelen;
18609 }
18610 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
18611 cmse_hash = (struct elf32_arm_link_hash_entry *)
18612 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
18613
18614 if (!cmse_hash
18615 || (cmse_hash->root.root.type != bfd_link_hash_defined
18616 && cmse_hash->root.root.type != bfd_link_hash_defweak)
18617 || cmse_hash->root.type != STT_FUNC)
18618 continue;
18619
54ddd295
TP		 18620 syms[dst_count++] = sym;
18621 }
18622 free (cmse_name);
18623
18624 syms[dst_count] = NULL;
18625
18626 return dst_count;
18627}
18628
18629/* Filter symbols of ABFD to include in the import library. All
18630 SYMCOUNT symbols of ABFD can be examined from their pointers in
18631 SYMS. Pointers of symbols to keep should be stored continuously at
18632 the beginning of that array.
18633
18634 Returns the number of symbols to keep. */
18635
18636static unsigned int
18637elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18638 struct bfd_link_info *info,
18639 asymbol **syms, long symcount)
18640{
18641 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
18642
046734ff
TP		 18643 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18644 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18645 library to be a relocatable object file. */
18646 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
54ddd295
TP		 18647 if (globals->cmse_implib)
18648 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
18649 else
18650 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
18651}
18652
e489d0ae
PB		 18653/* Allocate target specific section data. */
18654
18655static bfd_boolean
18656elf32_arm_new_section_hook (bfd *abfd, asection *sec)
18657{
f592407e
AM		 18658 if (!sec->used_by_bfd)
18659 {
18660 _arm_elf_section_data *sdata;
18661 bfd_size_type amt = sizeof (*sdata);
e489d0ae 18662
21d799b5 18663 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 18664 if (sdata == NULL)
18665 return FALSE;
18666 sec->used_by_bfd = sdata;
18667 }
e489d0ae
PB		 18668
18669 return _bfd_elf_new_section_hook (abfd, sec);
18670}
18671
18672
18673/* Used to order a list of mapping symbols by address. */
18674
18675static int
18676elf32_arm_compare_mapping (const void * a, const void * b)
18677{
7f6a71ff
JM		 18678 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
18679 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
18680
18681 if (amap->vma > bmap->vma)
18682 return 1;
18683 else if (amap->vma < bmap->vma)
18684 return -1;
18685 else if (amap->type > bmap->type)
18686 /* Ensure results do not depend on the host qsort for objects with
18687 multiple mapping symbols at the same address by sorting on type
18688 after vma. */
18689 return 1;
18690 else if (amap->type < bmap->type)
18691 return -1;
18692 else
18693 return 0;
e489d0ae
PB		 18694}
18695
2468f9c9
PB		 18696/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18697
18698static unsigned long
18699offset_prel31 (unsigned long addr, bfd_vma offset)
18700{
18701 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
18702}
18703
18704/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18705 relocations. */
18706
18707static void
18708copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
18709{
18710 unsigned long first_word = bfd_get_32 (output_bfd, from);
18711 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 18712
2468f9c9
PB		 18713 /* High bit of first word is supposed to be zero. */
18714 if ((first_word & 0x80000000ul) == 0)
18715 first_word = offset_prel31 (first_word, offset);
b38cadfb 18716
2468f9c9
PB		 18717 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18718 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18719 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
18720 second_word = offset_prel31 (second_word, offset);
b38cadfb 18721
2468f9c9
PB		 18722 bfd_put_32 (output_bfd, first_word, to);
18723 bfd_put_32 (output_bfd, second_word, to + 4);
18724}
e489d0ae 18725
48229727
JB		 18726/* Data for make_branch_to_a8_stub(). */
18727
b38cadfb
NC		 18728struct a8_branch_to_stub_data
18729{
48229727
JB		 18730 asection *writing_section;
18731 bfd_byte *contents;
18732};
18733
18734
18735/* Helper to insert branches to Cortex-A8 erratum stubs in the right
18736 places for a particular section. */
18737
18738static bfd_boolean
18739make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 18740 void *in_arg)
48229727
JB		 18741{
18742 struct elf32_arm_stub_hash_entry *stub_entry;
18743 struct a8_branch_to_stub_data *data;
18744 bfd_byte *contents;
18745 unsigned long branch_insn;
18746 bfd_vma veneered_insn_loc, veneer_entry_loc;
18747 bfd_signed_vma branch_offset;
18748 bfd *abfd;
8d9d9490 18749 unsigned int loc;
48229727
JB		 18750
18751 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
18752 data = (struct a8_branch_to_stub_data *) in_arg;
18753
18754 if (stub_entry->target_section != data->writing_section
4563a860 18755 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 18756 return TRUE;
18757
18758 contents = data->contents;
18759
8d9d9490
TP		 18760 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18761 generated when both source and target are in the same section. */
48229727
JB		 18762 veneered_insn_loc = stub_entry->target_section->output_section->vma
18763 + stub_entry->target_section->output_offset
8d9d9490 18764 + stub_entry->source_value;
48229727
JB		 18765
18766 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
18767 + stub_entry->stub_sec->output_offset
18768 + stub_entry->stub_offset;
18769
18770 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
18771 veneered_insn_loc &= ~3u;
18772
18773 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
18774
18775 abfd = stub_entry->target_section->owner;
8d9d9490 18776 loc = stub_entry->source_value;
48229727
JB		 18777
18778 /* We attempt to avoid this condition by setting stubs_always_after_branch
18779 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18780 This check is just to be on the safe side... */
18781 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
18782 {
871b3ab2 18783 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub is "
4eca0228 18784 "allocated in unsafe location"), abfd);
48229727
JB		 18785 return FALSE;
18786 }
18787
18788 switch (stub_entry->stub_type)
18789 {
18790 case arm_stub_a8_veneer_b:
18791 case arm_stub_a8_veneer_b_cond:
18792 branch_insn = 0xf0009000;
18793 goto jump24;
18794
18795 case arm_stub_a8_veneer_blx:
18796 branch_insn = 0xf000e800;
18797 goto jump24;
18798
18799 case arm_stub_a8_veneer_bl:
18800 {
18801 unsigned int i1, j1, i2, j2, s;
18802
18803 branch_insn = 0xf000d000;
18804
18805 jump24:
18806 if (branch_offset < -16777216 || branch_offset > 16777214)
18807 {
18808 /* There's not much we can do apart from complain if this
18809 happens. */
871b3ab2 18810 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub out "
4eca0228 18811 "of range (input file too large)"), abfd);
48229727
JB		 18812 return FALSE;
18813 }
18814
18815 /* i1 = not(j1 eor s), so:
18816 not i1 = j1 eor s
18817 j1 = (not i1) eor s. */
18818
18819 branch_insn |= (branch_offset >> 1) & 0x7ff;
18820 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
18821 i2 = (branch_offset >> 22) & 1;
18822 i1 = (branch_offset >> 23) & 1;
18823 s = (branch_offset >> 24) & 1;
18824 j1 = (!i1) ^ s;
18825 j2 = (!i2) ^ s;
18826 branch_insn |= j2 << 11;
18827 branch_insn |= j1 << 13;
18828 branch_insn |= s << 26;
18829 }
18830 break;
18831
18832 default:
18833 BFD_FAIL ();
18834 return FALSE;
18835 }
18836
8d9d9490
TP		 18837 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
18838 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 18839
18840 return TRUE;
18841}
18842
a504d23a
LA		 18843/* Beginning of stm32l4xx work-around. */
18844
18845/* Functions encoding instructions necessary for the emission of the
18846 fix-stm32l4xx-629360.
18847 Encoding is extracted from the
18848 ARM (C) Architecture Reference Manual
18849 ARMv7-A and ARMv7-R edition
18850 ARM DDI 0406C.b (ID072512). */
18851
18852static inline bfd_vma
82188b29 18853create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 18854{
18855 /* A8.8.18 B (A8-334)
18856 B target_address (Encoding T4). */
18857 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18858 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18859 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18860
a504d23a
LA		 18861 int s = ((branch_offset & 0x1000000) >> 24);
18862 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
18863 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
18864
18865 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
18866 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
18867
18868 bfd_vma patched_inst = 0xf0009000
18869 | s << 26 /* S. */
18870 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
18871 | j1 << 13 /* J1. */
18872 | j2 << 11 /* J2. */
18873 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
18874
18875 return patched_inst;
18876}
18877
18878static inline bfd_vma
18879create_instruction_ldmia (int base_reg, int wback, int reg_mask)
18880{
18881 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18882 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18883 bfd_vma patched_inst = 0xe8900000
18884 | (/*W=*/wback << 21)
18885 | (base_reg << 16)
18886 | (reg_mask & 0x0000ffff);
18887
18888 return patched_inst;
18889}
18890
18891static inline bfd_vma
18892create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
18893{
18894 /* A8.8.60 LDMDB/LDMEA (A8-402)
18895 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18896 bfd_vma patched_inst = 0xe9100000
18897 | (/*W=*/wback << 21)
18898 | (base_reg << 16)
18899 | (reg_mask & 0x0000ffff);
18900
18901 return patched_inst;
18902}
18903
18904static inline bfd_vma
18905create_instruction_mov (int target_reg, int source_reg)
18906{
18907 /* A8.8.103 MOV (register) (A8-486)
18908 MOV Rd, Rm (Encoding T1). */
18909 bfd_vma patched_inst = 0x4600
18910 | (target_reg & 0x7)
18911 | ((target_reg & 0x8) >> 3) << 7
18912 | (source_reg << 3);
18913
18914 return patched_inst;
18915}
18916
18917static inline bfd_vma
18918create_instruction_sub (int target_reg, int source_reg, int value)
18919{
18920 /* A8.8.221 SUB (immediate) (A8-708)
18921 SUB Rd, Rn, #value (Encoding T3). */
18922 bfd_vma patched_inst = 0xf1a00000
18923 | (target_reg << 8)
18924 | (source_reg << 16)
18925 | (/*S=*/0 << 20)
18926 | ((value & 0x800) >> 11) << 26
18927 | ((value & 0x700) >> 8) << 12
18928 | (value & 0x0ff);
18929
18930 return patched_inst;
18931}
18932
18933static inline bfd_vma
9239bbd3 18934create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 18935 int first_reg)
18936{
18937 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18938 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18939 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 18940 | (/*W=*/wback << 21)
18941 | (base_reg << 16)
9239bbd3
CM		 18942 | (num_words & 0x000000ff)
18943 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 18944 | (first_reg & 0x00000001) << 22;
18945
18946 return patched_inst;
18947}
18948
18949static inline bfd_vma
9239bbd3
CM		 18950create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
18951 int first_reg)
a504d23a
LA		 18952{
18953 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18954 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18955 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 18956 | (base_reg << 16)
9239bbd3
CM		 18957 | (num_words & 0x000000ff)
18958 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 18959 | (first_reg & 0x00000001) << 22;
18960
18961 return patched_inst;
18962}
18963
18964static inline bfd_vma
18965create_instruction_udf_w (int value)
18966{
18967 /* A8.8.247 UDF (A8-758)
18968 Undefined (Encoding T2). */
18969 bfd_vma patched_inst = 0xf7f0a000
18970 | (value & 0x00000fff)
18971 | (value & 0x000f0000) << 16;
18972
18973 return patched_inst;
18974}
18975
18976static inline bfd_vma
18977create_instruction_udf (int value)
18978{
18979 /* A8.8.247 UDF (A8-758)
18980 Undefined (Encoding T1). */
18981 bfd_vma patched_inst = 0xde00
18982 | (value & 0xff);
18983
18984 return patched_inst;
18985}
18986
18987/* Functions writing an instruction in memory, returning the next
18988 memory position to write to. */
18989
18990static inline bfd_byte *
18991push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
18992 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18993{
18994 put_thumb2_insn (htab, output_bfd, insn, pt);
18995 return pt + 4;
18996}
18997
18998static inline bfd_byte *
18999push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
19000 bfd * output_bfd, bfd_byte *pt, insn32 insn)
19001{
19002 put_thumb_insn (htab, output_bfd, insn, pt);
19003 return pt + 2;
19004}
19005
19006/* Function filling up a region in memory with T1 and T2 UDFs taking
19007 care of alignment. */
19008
19009static bfd_byte *
19010stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
07d6d2b8
AM		 19011 bfd * output_bfd,
19012 const bfd_byte * const base_stub_contents,
19013 bfd_byte * const from_stub_contents,
19014 const bfd_byte * const end_stub_contents)
a504d23a
LA		 19015{
19016 bfd_byte *current_stub_contents = from_stub_contents;
19017
19018 /* Fill the remaining of the stub with deterministic contents : UDF
19019 instructions.
19020 Check if realignment is needed on modulo 4 frontier using T1, to
19021 further use T2. */
19022 if ((current_stub_contents < end_stub_contents)
19023 && !((current_stub_contents - base_stub_contents) % 2)
19024 && ((current_stub_contents - base_stub_contents) % 4))
19025 current_stub_contents =
19026 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19027 create_instruction_udf (0));
19028
19029 for (; current_stub_contents < end_stub_contents;)
19030 current_stub_contents =
19031 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19032 create_instruction_udf_w (0));
19033
19034 return current_stub_contents;
19035}
19036
19037/* Functions writing the stream of instructions equivalent to the
19038 derived sequence for ldmia, ldmdb, vldm respectively. */
19039
19040static void
19041stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
19042 bfd * output_bfd,
19043 const insn32 initial_insn,
19044 const bfd_byte *const initial_insn_addr,
19045 bfd_byte *const base_stub_contents)
19046{
19047 int wback = (initial_insn & 0x00200000) >> 21;
19048 int ri, rn = (initial_insn & 0x000F0000) >> 16;
19049 int insn_all_registers = initial_insn & 0x0000ffff;
19050 int insn_low_registers, insn_high_registers;
19051 int usable_register_mask;
b25e998d 19052 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 19053 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
19054 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
19055 bfd_byte *current_stub_contents = base_stub_contents;
19056
19057 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
19058
19059 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19060 smaller than 8 registers load sequences that do not cause the
19061 hardware issue. */
19062 if (nb_registers <= 8)
19063 {
19064 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
19065 current_stub_contents =
19066 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19067 initial_insn);
19068
19069 /* B initial_insn_addr+4. */
19070 if (!restore_pc)
19071 current_stub_contents =
19072 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19073 create_instruction_branch_absolute
82188b29 19074 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19075
19076 /* Fill the remaining of the stub with deterministic contents. */
19077 current_stub_contents =
19078 stm32l4xx_fill_stub_udf (htab, output_bfd,
19079 base_stub_contents, current_stub_contents,
19080 base_stub_contents +
19081 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19082
19083 return;
19084 }
19085
19086 /* - reg_list[13] == 0. */
19087 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
19088
19089 /* - reg_list[14] & reg_list[15] != 1. */
19090 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
19091
19092 /* - if (wback==1) reg_list[rn] == 0. */
19093 BFD_ASSERT (!wback || !restore_rn);
19094
19095 /* - nb_registers > 8. */
b25e998d 19096 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19097
19098 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19099
19100 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
19101 - One with the 7 lowest registers (register mask 0x007F)
19102 This LDM will finally contain between 2 and 7 registers
19103 - One with the 7 highest registers (register mask 0xDF80)
19104 This ldm will finally contain between 2 and 7 registers. */
19105 insn_low_registers = insn_all_registers & 0x007F;
19106 insn_high_registers = insn_all_registers & 0xDF80;
19107
19108 /* A spare register may be needed during this veneer to temporarily
19109 handle the base register. This register will be restored with the
19110 last LDM operation.
19111 The usable register may be any general purpose register (that
19112 excludes PC, SP, LR : register mask is 0x1FFF). */
19113 usable_register_mask = 0x1FFF;
19114
19115 /* Generate the stub function. */
19116 if (wback)
19117 {
19118 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
19119 current_stub_contents =
19120 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19121 create_instruction_ldmia
19122 (rn, /*wback=*/1, insn_low_registers));
19123
19124 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
19125 current_stub_contents =
19126 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19127 create_instruction_ldmia
19128 (rn, /*wback=*/1, insn_high_registers));
19129 if (!restore_pc)
19130 {
19131 /* B initial_insn_addr+4. */
19132 current_stub_contents =
19133 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19134 create_instruction_branch_absolute
82188b29 19135 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19136 }
19137 }
19138 else /* if (!wback). */
19139 {
19140 ri = rn;
19141
19142 /* If Rn is not part of the high-register-list, move it there. */
19143 if (!(insn_high_registers & (1 << rn)))
19144 {
19145 /* Choose a Ri in the high-register-list that will be restored. */
19146 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19147
19148 /* MOV Ri, Rn. */
19149 current_stub_contents =
19150 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19151 create_instruction_mov (ri, rn));
19152 }
19153
19154 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
19155 current_stub_contents =
19156 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19157 create_instruction_ldmia
19158 (ri, /*wback=*/1, insn_low_registers));
19159
19160 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
19161 current_stub_contents =
19162 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19163 create_instruction_ldmia
19164 (ri, /*wback=*/0, insn_high_registers));
19165
19166 if (!restore_pc)
19167 {
19168 /* B initial_insn_addr+4. */
19169 current_stub_contents =
19170 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19171 create_instruction_branch_absolute
82188b29 19172 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19173 }
19174 }
19175
19176 /* Fill the remaining of the stub with deterministic contents. */
19177 current_stub_contents =
19178 stm32l4xx_fill_stub_udf (htab, output_bfd,
19179 base_stub_contents, current_stub_contents,
19180 base_stub_contents +
19181 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19182}
19183
19184static void
19185stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
19186 bfd * output_bfd,
19187 const insn32 initial_insn,
19188 const bfd_byte *const initial_insn_addr,
19189 bfd_byte *const base_stub_contents)
19190{
19191 int wback = (initial_insn & 0x00200000) >> 21;
19192 int ri, rn = (initial_insn & 0x000f0000) >> 16;
19193 int insn_all_registers = initial_insn & 0x0000ffff;
19194 int insn_low_registers, insn_high_registers;
19195 int usable_register_mask;
19196 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
19197 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 19198 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 19199 bfd_byte *current_stub_contents = base_stub_contents;
19200
19201 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
19202
19203 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19204 smaller than 8 registers load sequences that do not cause the
19205 hardware issue. */
19206 if (nb_registers <= 8)
19207 {
19208 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
19209 current_stub_contents =
19210 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19211 initial_insn);
19212
19213 /* B initial_insn_addr+4. */
19214 current_stub_contents =
19215 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19216 create_instruction_branch_absolute
82188b29 19217 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19218
19219 /* Fill the remaining of the stub with deterministic contents. */
19220 current_stub_contents =
19221 stm32l4xx_fill_stub_udf (htab, output_bfd,
19222 base_stub_contents, current_stub_contents,
19223 base_stub_contents +
19224 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19225
19226 return;
19227 }
19228
19229 /* - reg_list[13] == 0. */
19230 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
19231
19232 /* - reg_list[14] & reg_list[15] != 1. */
19233 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
19234
19235 /* - if (wback==1) reg_list[rn] == 0. */
19236 BFD_ASSERT (!wback || !restore_rn);
19237
19238 /* - nb_registers > 8. */
b25e998d 19239 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19240
19241 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19242
19243 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
19244 - One with the 7 lowest registers (register mask 0x007F)
19245 This LDM will finally contain between 2 and 7 registers
19246 - One with the 7 highest registers (register mask 0xDF80)
19247 This ldm will finally contain between 2 and 7 registers. */
19248 insn_low_registers = insn_all_registers & 0x007F;
19249 insn_high_registers = insn_all_registers & 0xDF80;
19250
19251 /* A spare register may be needed during this veneer to temporarily
19252 handle the base register. This register will be restored with
19253 the last LDM operation.
19254 The usable register may be any general purpose register (that excludes
19255 PC, SP, LR : register mask is 0x1FFF). */
19256 usable_register_mask = 0x1FFF;
19257
19258 /* Generate the stub function. */
19259 if (!wback && !restore_pc && !restore_rn)
19260 {
19261 /* Choose a Ri in the low-register-list that will be restored. */
19262 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19263
19264 /* MOV Ri, Rn. */
19265 current_stub_contents =
19266 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19267 create_instruction_mov (ri, rn));
19268
19269 /* LDMDB Ri!, {R-high-register-list}. */
19270 current_stub_contents =
19271 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19272 create_instruction_ldmdb
19273 (ri, /*wback=*/1, insn_high_registers));
19274
19275 /* LDMDB Ri, {R-low-register-list}. */
19276 current_stub_contents =
19277 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19278 create_instruction_ldmdb
19279 (ri, /*wback=*/0, insn_low_registers));
19280
19281 /* B initial_insn_addr+4. */
19282 current_stub_contents =
19283 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19284 create_instruction_branch_absolute
82188b29 19285 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19286 }
19287 else if (wback && !restore_pc && !restore_rn)
19288 {
19289 /* LDMDB Rn!, {R-high-register-list}. */
19290 current_stub_contents =
19291 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19292 create_instruction_ldmdb
19293 (rn, /*wback=*/1, insn_high_registers));
19294
19295 /* LDMDB Rn!, {R-low-register-list}. */
19296 current_stub_contents =
19297 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19298 create_instruction_ldmdb
19299 (rn, /*wback=*/1, insn_low_registers));
19300
19301 /* B initial_insn_addr+4. */
19302 current_stub_contents =
19303 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19304 create_instruction_branch_absolute
82188b29 19305 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19306 }
19307 else if (!wback && restore_pc && !restore_rn)
19308 {
19309 /* Choose a Ri in the high-register-list that will be restored. */
19310 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19311
19312 /* SUB Ri, Rn, #(4*nb_registers). */
19313 current_stub_contents =
19314 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19315 create_instruction_sub (ri, rn, (4 * nb_registers)));
19316
19317 /* LDMIA Ri!, {R-low-register-list}. */
19318 current_stub_contents =
19319 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19320 create_instruction_ldmia
19321 (ri, /*wback=*/1, insn_low_registers));
19322
19323 /* LDMIA Ri, {R-high-register-list}. */
19324 current_stub_contents =
19325 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19326 create_instruction_ldmia
19327 (ri, /*wback=*/0, insn_high_registers));
19328 }
19329 else if (wback && restore_pc && !restore_rn)
19330 {
19331 /* Choose a Ri in the high-register-list that will be restored. */
19332 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19333
19334 /* SUB Rn, Rn, #(4*nb_registers) */
19335 current_stub_contents =
19336 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19337 create_instruction_sub (rn, rn, (4 * nb_registers)));
19338
19339 /* MOV Ri, Rn. */
19340 current_stub_contents =
19341 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19342 create_instruction_mov (ri, rn));
19343
19344 /* LDMIA Ri!, {R-low-register-list}. */
19345 current_stub_contents =
19346 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19347 create_instruction_ldmia
19348 (ri, /*wback=*/1, insn_low_registers));
19349
19350 /* LDMIA Ri, {R-high-register-list}. */
19351 current_stub_contents =
19352 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19353 create_instruction_ldmia
19354 (ri, /*wback=*/0, insn_high_registers));
19355 }
19356 else if (!wback && !restore_pc && restore_rn)
19357 {
19358 ri = rn;
19359 if (!(insn_low_registers & (1 << rn)))
19360 {
19361 /* Choose a Ri in the low-register-list that will be restored. */
19362 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19363
19364 /* MOV Ri, Rn. */
19365 current_stub_contents =
19366 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19367 create_instruction_mov (ri, rn));
19368 }
19369
19370 /* LDMDB Ri!, {R-high-register-list}. */
19371 current_stub_contents =
19372 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19373 create_instruction_ldmdb
19374 (ri, /*wback=*/1, insn_high_registers));
19375
19376 /* LDMDB Ri, {R-low-register-list}. */
19377 current_stub_contents =
19378 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19379 create_instruction_ldmdb
19380 (ri, /*wback=*/0, insn_low_registers));
19381
19382 /* B initial_insn_addr+4. */
19383 current_stub_contents =
19384 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19385 create_instruction_branch_absolute
82188b29 19386 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19387 }
19388 else if (!wback && restore_pc && restore_rn)
19389 {
19390 ri = rn;
19391 if (!(insn_high_registers & (1 << rn)))
19392 {
19393 /* Choose a Ri in the high-register-list that will be restored. */
19394 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19395 }
19396
19397 /* SUB Ri, Rn, #(4*nb_registers). */
19398 current_stub_contents =
19399 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19400 create_instruction_sub (ri, rn, (4 * nb_registers)));
19401
19402 /* LDMIA Ri!, {R-low-register-list}. */
19403 current_stub_contents =
19404 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19405 create_instruction_ldmia
19406 (ri, /*wback=*/1, insn_low_registers));
19407
19408 /* LDMIA Ri, {R-high-register-list}. */
19409 current_stub_contents =
19410 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19411 create_instruction_ldmia
19412 (ri, /*wback=*/0, insn_high_registers));
19413 }
19414 else if (wback && restore_rn)
19415 {
19416 /* The assembler should not have accepted to encode this. */
19417 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
19418 "undefined behavior.\n");
19419 }
19420
19421 /* Fill the remaining of the stub with deterministic contents. */
19422 current_stub_contents =
19423 stm32l4xx_fill_stub_udf (htab, output_bfd,
19424 base_stub_contents, current_stub_contents,
19425 base_stub_contents +
19426 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19427
19428}
19429
19430static void
19431stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
19432 bfd * output_bfd,
19433 const insn32 initial_insn,
19434 const bfd_byte *const initial_insn_addr,
19435 bfd_byte *const base_stub_contents)
19436{
9239bbd3 19437 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 19438 bfd_byte *current_stub_contents = base_stub_contents;
19439
19440 BFD_ASSERT (is_thumb2_vldm (initial_insn));
19441
19442 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 19443 smaller than 8 words load sequences that do not cause the
a504d23a 19444 hardware issue. */
9239bbd3 19445 if (num_words <= 8)
a504d23a
LA		 19446 {
19447 /* Untouched instruction. */
19448 current_stub_contents =
19449 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19450 initial_insn);
19451
19452 /* B initial_insn_addr+4. */
19453 current_stub_contents =
19454 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19455 create_instruction_branch_absolute
82188b29 19456 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19457 }
19458 else
19459 {
9eaff861 19460 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 19461 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 19462 bfd_boolean is_ia_nobang = /* (IA without !). */
19463 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
19464 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
19465 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
19466 bfd_boolean is_db_bang = /* (DB with !). */
19467 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 19468 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 19469 /* d = UInt (Vd:D);. */
9239bbd3 19470 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 19471 | (((unsigned int)initial_insn << 9) >> 31);
19472
9239bbd3
CM		 19473 /* Compute the number of 8-words chunks needed to split. */
19474 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 19475 int chunk;
19476
19477 /* The test coverage has been done assuming the following
19478 hypothesis that exactly one of the previous is_ predicates is
19479 true. */
9239bbd3
CM		 19480 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
19481 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 19482
9239bbd3 19483 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 19484 cases, then we emit the adjustments:
19485
19486 vldm rx, {...}
19487 -> vldm rx!, {8_words_or_less} for each needed 8_word
19488 -> sub rx, rx, #size (list)
19489
19490 vldm rx!, {...}
19491 -> vldm rx!, {8_words_or_less} for each needed 8_word
19492 This also handles vpop instruction (when rx is sp)
19493
19494 vldmd rx!, {...}
19495 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 19496 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 19497 {
9239bbd3
CM		 19498 bfd_vma new_insn = 0;
19499
a504d23a
LA		 19500 if (is_ia_nobang || is_ia_bang)
19501 {
9239bbd3
CM		 19502 new_insn = create_instruction_vldmia
19503 (base_reg,
19504 is_dp,
19505 /*wback= . */1,
19506 chunks - (chunk + 1) ?
19507 8 : num_words - chunk * 8,
19508 first_reg + chunk * 8);
a504d23a
LA		 19509 }
19510 else if (is_db_bang)
19511 {
9239bbd3
CM		 19512 new_insn = create_instruction_vldmdb
19513 (base_reg,
19514 is_dp,
19515 chunks - (chunk + 1) ?
19516 8 : num_words - chunk * 8,
19517 first_reg + chunk * 8);
a504d23a 19518 }
9239bbd3
CM		 19519
19520 if (new_insn)
19521 current_stub_contents =
19522 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19523 new_insn);
a504d23a
LA		 19524 }
19525
19526 /* Only this case requires the base register compensation
19527 subtract. */
19528 if (is_ia_nobang)
19529 {
19530 current_stub_contents =
19531 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19532 create_instruction_sub
9239bbd3 19533 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 19534 }
19535
19536 /* B initial_insn_addr+4. */
19537 current_stub_contents =
19538 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19539 create_instruction_branch_absolute
82188b29 19540 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19541 }
19542
19543 /* Fill the remaining of the stub with deterministic contents. */
19544 current_stub_contents =
19545 stm32l4xx_fill_stub_udf (htab, output_bfd,
19546 base_stub_contents, current_stub_contents,
19547 base_stub_contents +
19548 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19549}
19550
19551static void
19552stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
19553 bfd * output_bfd,
19554 const insn32 wrong_insn,
19555 const bfd_byte *const wrong_insn_addr,
19556 bfd_byte *const stub_contents)
19557{
19558 if (is_thumb2_ldmia (wrong_insn))
19559 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
19560 wrong_insn, wrong_insn_addr,
19561 stub_contents);
19562 else if (is_thumb2_ldmdb (wrong_insn))
19563 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
19564 wrong_insn, wrong_insn_addr,
19565 stub_contents);
19566 else if (is_thumb2_vldm (wrong_insn))
19567 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
19568 wrong_insn, wrong_insn_addr,
19569 stub_contents);
19570}
19571
19572/* End of stm32l4xx work-around. */
19573
19574
e489d0ae
PB		 19575/* Do code byteswapping. Return FALSE afterwards so that the section is
19576 written out as normal. */
19577
19578static bfd_boolean
c7b8f16e 19579elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 19580 struct bfd_link_info *link_info,
19581 asection *sec,
e489d0ae
PB		 19582 bfd_byte *contents)
19583{
48229727 19584 unsigned int mapcount, errcount;
8e3de13a 19585 _arm_elf_section_data *arm_data;
c7b8f16e 19586 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 19587 elf32_arm_section_map *map;
c7b8f16e 19588 elf32_vfp11_erratum_list *errnode;
a504d23a 19589 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 19590 bfd_vma ptr;
19591 bfd_vma end;
c7b8f16e 19592 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 19593 bfd_byte tmp;
48229727 19594 unsigned int i;
57e8b36a 19595
4dfe6ac6
NC		 19596 if (globals == NULL)
19597 return FALSE;
19598
8e3de13a
NC		 19599 /* If this section has not been allocated an _arm_elf_section_data
19600 structure then we cannot record anything. */
19601 arm_data = get_arm_elf_section_data (sec);
19602 if (arm_data == NULL)
19603 return FALSE;
19604
19605 mapcount = arm_data->mapcount;
19606 map = arm_data->map;
c7b8f16e
JB		 19607 errcount = arm_data->erratumcount;
19608
19609 if (errcount != 0)
19610 {
19611 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
19612
19613 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 19614 errnode = errnode->next)
19615 {
19616 bfd_vma target = errnode->vma - offset;
19617
19618 switch (errnode->type)
19619 {
19620 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
19621 {
19622 bfd_vma branch_to_veneer;
19623 /* Original condition code of instruction, plus bit mask for
19624 ARM B instruction. */
19625 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
19626 | 0x0a000000;
c7b8f16e
JB		 19627
19628 /* The instruction is before the label. */
91d6fa6a 19629 target -= 4;
c7b8f16e
JB		 19630
19631 /* Above offset included in -4 below. */
19632 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 19633 - errnode->vma - 4;
c7b8f16e
JB		 19634
19635 if ((signed) branch_to_veneer < -(1 << 25)
19636 || (signed) branch_to_veneer >= (1 << 25))
871b3ab2 19637 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19638 "range"), output_bfd);
c7b8f16e 19639
99059e56
RM		 19640 insn |= (branch_to_veneer >> 2) & 0xffffff;
19641 contents[endianflip ^ target] = insn & 0xff;
19642 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19643 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19644 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19645 }
19646 break;
c7b8f16e
JB		 19647
19648 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 19649 {
19650 bfd_vma branch_from_veneer;
19651 unsigned int insn;
c7b8f16e 19652
99059e56
RM		 19653 /* Take size of veneer into account. */
19654 branch_from_veneer = errnode->u.v.branch->vma
19655 - errnode->vma - 12;
c7b8f16e
JB		 19656
19657 if ((signed) branch_from_veneer < -(1 << 25)
19658 || (signed) branch_from_veneer >= (1 << 25))
871b3ab2 19659 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19660 "range"), output_bfd);
c7b8f16e 19661
99059e56
RM		 19662 /* Original instruction. */
19663 insn = errnode->u.v.branch->u.b.vfp_insn;
19664 contents[endianflip ^ target] = insn & 0xff;
19665 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19666 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19667 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19668
19669 /* Branch back to insn after original insn. */
19670 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
19671 contents[endianflip ^ (target + 4)] = insn & 0xff;
19672 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
19673 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
19674 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
19675 }
19676 break;
c7b8f16e 19677
99059e56
RM		 19678 default:
19679 abort ();
19680 }
19681 }
c7b8f16e 19682 }
e489d0ae 19683
a504d23a
LA		 19684 if (arm_data->stm32l4xx_erratumcount != 0)
19685 {
19686 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
19687 stm32l4xx_errnode != 0;
19688 stm32l4xx_errnode = stm32l4xx_errnode->next)
19689 {
19690 bfd_vma target = stm32l4xx_errnode->vma - offset;
19691
19692 switch (stm32l4xx_errnode->type)
19693 {
19694 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
19695 {
19696 unsigned int insn;
19697 bfd_vma branch_to_veneer =
19698 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
19699
19700 if ((signed) branch_to_veneer < -(1 << 24)
19701 || (signed) branch_to_veneer >= (1 << 24))
19702 {
19703 bfd_vma out_of_range =
19704 ((signed) branch_to_veneer < -(1 << 24)) ?
19705 - branch_to_veneer - (1 << 24) :
19706 ((signed) branch_to_veneer >= (1 << 24)) ?
19707 branch_to_veneer - (1 << 24) : 0;
19708
4eca0228 19709 _bfd_error_handler
2dcf00ce 19710 (_("%pB(%#" PRIx64 "): error: "
90b6238f
AM		 19711 "cannot create STM32L4XX veneer; "
19712 "jump out of range by %" PRId64 " bytes; "
19713 "cannot encode branch instruction"),
a504d23a 19714 output_bfd,
2dcf00ce
AM		 19715 (uint64_t) (stm32l4xx_errnode->vma - 4),
19716 (int64_t) out_of_range);
a504d23a
LA		 19717 continue;
19718 }
19719
19720 insn = create_instruction_branch_absolute
82188b29 19721 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a 19722
a2699ef2
AM		 19723 /* The instruction is before the label. */
19724 target -= 4;
19725
a504d23a
LA		 19726 put_thumb2_insn (globals, output_bfd,
19727 (bfd_vma) insn, contents + target);
19728 }
19729 break;
19730
19731 case STM32L4XX_ERRATUM_VENEER:
19732 {
82188b29
NC		 19733 bfd_byte * veneer;
19734 bfd_byte * veneer_r;
a504d23a
LA		 19735 unsigned int insn;
19736
82188b29
NC		 19737 veneer = contents + target;
19738 veneer_r = veneer
19739 + stm32l4xx_errnode->u.b.veneer->vma
19740 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 19741
19742 if ((signed) (veneer_r - veneer -
19743 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19744 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19745 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19746 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
19747 || (signed) (veneer_r - veneer) >= (1 << 24))
19748 {
90b6238f
AM		 19749 _bfd_error_handler (_("%pB: error: cannot create STM32L4XX "
19750 "veneer"), output_bfd);
a504d23a
LA		 19751 continue;
19752 }
19753
19754 /* Original instruction. */
19755 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
19756
19757 stm32l4xx_create_replacing_stub
19758 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
19759 }
19760 break;
19761
19762 default:
19763 abort ();
19764 }
19765 }
19766 }
19767
2468f9c9
PB		 19768 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
19769 {
19770 arm_unwind_table_edit *edit_node
99059e56 19771 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 19772 /* Now, sec->size is the size of the section we will write. The original
99059e56 19773 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 19774 markers) was sec->rawsize. (This isn't the case if we perform no
19775 edits, then rawsize will be zero and we should use size). */
21d799b5 19776 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 19777 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
19778 unsigned int in_index, out_index;
19779 bfd_vma add_to_offsets = 0;
19780
19781 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 19782 {
2468f9c9
PB		 19783 if (edit_node)
19784 {
19785 unsigned int edit_index = edit_node->index;
b38cadfb 19786
2468f9c9 19787 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 19788 {
2468f9c9
PB		 19789 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19790 contents + in_index * 8, add_to_offsets);
19791 out_index++;
19792 in_index++;
19793 }
19794 else if (in_index == edit_index
19795 || (in_index * 8 >= input_size
19796 && edit_index == UINT_MAX))
99059e56 19797 {
2468f9c9
PB		 19798 switch (edit_node->type)
19799 {
19800 case DELETE_EXIDX_ENTRY:
19801 in_index++;
19802 add_to_offsets += 8;
19803 break;
b38cadfb 19804
2468f9c9
PB		 19805 case INSERT_EXIDX_CANTUNWIND_AT_END:
19806 {
99059e56 19807 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 19808 bfd_vma text_offset = text_sec->output_section->vma
19809 + text_sec->output_offset
19810 + text_sec->size;
19811 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 19812 unsigned long prel31_offset;
2468f9c9
PB		 19813
19814 /* Note: this is meant to be equivalent to an
19815 R_ARM_PREL31 relocation. These synthetic
19816 EXIDX_CANTUNWIND markers are not relocated by the
19817 usual BFD method. */
19818 prel31_offset = (text_offset - exidx_offset)
19819 & 0x7ffffffful;
491d01d3
YU		 19820 if (bfd_link_relocatable (link_info))
19821 {
19822 /* Here relocation for new EXIDX_CANTUNWIND is
19823 created, so there is no need to
19824 adjust offset by hand. */
19825 prel31_offset = text_sec->output_offset
19826 + text_sec->size;
491d01d3 19827 }
2468f9c9
PB		 19828
19829 /* First address we can't unwind. */
19830 bfd_put_32 (output_bfd, prel31_offset,
19831 &edited_contents[out_index * 8]);
19832
19833 /* Code for EXIDX_CANTUNWIND. */
19834 bfd_put_32 (output_bfd, 0x1,
19835 &edited_contents[out_index * 8 + 4]);
19836
19837 out_index++;
19838 add_to_offsets -= 8;
19839 }
19840 break;
19841 }
b38cadfb 19842
2468f9c9
PB		 19843 edit_node = edit_node->next;
19844 }
19845 }
19846 else
19847 {
19848 /* No more edits, copy remaining entries verbatim. */
19849 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19850 contents + in_index * 8, add_to_offsets);
19851 out_index++;
19852 in_index++;
19853 }
19854 }
19855
19856 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
19857 bfd_set_section_contents (output_bfd, sec->output_section,
19858 edited_contents,
19859 (file_ptr) sec->output_offset, sec->size);
19860
19861 return TRUE;
19862 }
19863
48229727
JB		 19864 /* Fix code to point to Cortex-A8 erratum stubs. */
19865 if (globals->fix_cortex_a8)
19866 {
19867 struct a8_branch_to_stub_data data;
19868
19869 data.writing_section = sec;
19870 data.contents = contents;
19871
a504d23a
LA		 19872 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
19873 & data);
48229727
JB		 19874 }
19875
e489d0ae
PB		 19876 if (mapcount == 0)
19877 return FALSE;
19878
c7b8f16e 19879 if (globals->byteswap_code)
e489d0ae 19880 {
c7b8f16e 19881 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 19882
c7b8f16e
JB		 19883 ptr = map[0].vma;
19884 for (i = 0; i < mapcount; i++)
99059e56
RM		 19885 {
19886 if (i == mapcount - 1)
c7b8f16e 19887 end = sec->size;
99059e56
RM		 19888 else
19889 end = map[i + 1].vma;
e489d0ae 19890
99059e56 19891 switch (map[i].type)
e489d0ae 19892 {
c7b8f16e
JB		 19893 case 'a':
19894 /* Byte swap code words. */
19895 while (ptr + 3 < end)
99059e56
RM		 19896 {
19897 tmp = contents[ptr];
19898 contents[ptr] = contents[ptr + 3];
19899 contents[ptr + 3] = tmp;
19900 tmp = contents[ptr + 1];
19901 contents[ptr + 1] = contents[ptr + 2];
19902 contents[ptr + 2] = tmp;
19903 ptr += 4;
19904 }
c7b8f16e 19905 break;
e489d0ae 19906
c7b8f16e
JB		 19907 case 't':
19908 /* Byte swap code halfwords. */
19909 while (ptr + 1 < end)
99059e56
RM		 19910 {
19911 tmp = contents[ptr];
19912 contents[ptr] = contents[ptr + 1];
19913 contents[ptr + 1] = tmp;
19914 ptr += 2;
19915 }
c7b8f16e
JB		 19916 break;
19917
19918 case 'd':
19919 /* Leave data alone. */
19920 break;
19921 }
99059e56
RM		 19922 ptr = end;
19923 }
e489d0ae 19924 }
8e3de13a 19925
93204d3a 19926 free (map);
47b2e99c 19927 arm_data->mapcount = -1;
c7b8f16e 19928 arm_data->mapsize = 0;
8e3de13a 19929 arm_data->map = NULL;
8e3de13a 19930
e489d0ae
PB		 19931 return FALSE;
19932}
19933
0beaef2b
PB		 19934/* Mangle thumb function symbols as we read them in. */
19935
8384fb8f 19936static bfd_boolean
0beaef2b
PB		 19937elf32_arm_swap_symbol_in (bfd * abfd,
19938 const void *psrc,
19939 const void *pshn,
19940 Elf_Internal_Sym *dst)
19941{
8384fb8f
AM		 19942 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
19943 return FALSE;
39d911fc 19944 dst->st_target_internal = 0;
0beaef2b
PB		 19945
19946 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 19947 the address. */
63e1a0fc
PB		 19948 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
19949 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 19950 {
63e1a0fc
PB		 19951 if (dst->st_value & 1)
19952 {
19953 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 19954 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
19955 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 19956 }
19957 else
39d911fc 19958 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 19959 }
19960 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
19961 {
19962 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 19963 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 19964 }
35fc36a8 19965 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 19966 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 19967 else
39d911fc 19968 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 19969
8384fb8f 19970 return TRUE;
0beaef2b
PB		 19971}
19972
19973
19974/* Mangle thumb function symbols as we write them out. */
19975
19976static void
19977elf32_arm_swap_symbol_out (bfd *abfd,
19978 const Elf_Internal_Sym *src,
19979 void *cdst,
19980 void *shndx)
19981{
19982 Elf_Internal_Sym newsym;
19983
19984 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19985 of the address set, as per the new EABI. We do this unconditionally
19986 because objcopy does not set the elf header flags until after
19987 it writes out the symbol table. */
39d911fc 19988 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 19989 {
19990 newsym = *src;
34e77a92
RS		 19991 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
19992 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 19993 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 19994 {
19995 /* Do this only for defined symbols. At link type, the static
19996 linker will simulate the work of dynamic linker of resolving
19997 symbols and will carry over the thumbness of found symbols to
19998 the output symbol table. It's not clear how it happens, but
19999 the thumbness of undefined symbols can well be different at
20000 runtime, and writing '1' for them will be confusing for users
20001 and possibly for dynamic linker itself.
20002 */
20003 newsym.st_value |= 1;
20004 }
906e58ca 20005
0beaef2b
PB		 20006 src = &newsym;
20007 }
20008 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
20009}
20010
b294bdf8
MM		 20011/* Add the PT_ARM_EXIDX program header. */
20012
20013static bfd_boolean
906e58ca 20014elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 20015 struct bfd_link_info *info ATTRIBUTE_UNUSED)
20016{
20017 struct elf_segment_map *m;
20018 asection *sec;
20019
20020 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
20021 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
20022 {
20023 /* If there is already a PT_ARM_EXIDX header, then we do not
20024 want to add another one. This situation arises when running
20025 "strip"; the input binary already has the header. */
12bd6957 20026 m = elf_seg_map (abfd);
b294bdf8
MM		 20027 while (m && m->p_type != PT_ARM_EXIDX)
20028 m = m->next;
20029 if (!m)
20030 {
21d799b5 20031 m = (struct elf_segment_map *)
99059e56 20032 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 20033 if (m == NULL)
20034 return FALSE;
20035 m->p_type = PT_ARM_EXIDX;
20036 m->count = 1;
20037 m->sections[0] = sec;
20038
12bd6957
AM		 20039 m->next = elf_seg_map (abfd);
20040 elf_seg_map (abfd) = m;
b294bdf8
MM		 20041 }
20042 }
20043
20044 return TRUE;
20045}
20046
20047/* We may add a PT_ARM_EXIDX program header. */
20048
20049static int
a6b96beb
AM		 20050elf32_arm_additional_program_headers (bfd *abfd,
20051 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 20052{
20053 asection *sec;
20054
20055 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
20056 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
20057 return 1;
20058 else
20059 return 0;
20060}
20061
34e77a92
RS		 20062/* Hook called by the linker routine which adds symbols from an object
20063 file. */
20064
20065static bfd_boolean
20066elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
20067 Elf_Internal_Sym *sym, const char **namep,
20068 flagword *flagsp, asection **secp, bfd_vma *valp)
20069{
c792917c
NC		 20070 if (elf32_arm_hash_table (info) == NULL)
20071 return FALSE;
20072
34e77a92
RS		 20073 if (elf32_arm_hash_table (info)->vxworks_p
20074 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
20075 flagsp, secp, valp))
20076 return FALSE;
20077
20078 return TRUE;
20079}
20080
0beaef2b 20081/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 20082const struct elf_size_info elf32_arm_size_info =
20083{
0beaef2b
PB		 20084 sizeof (Elf32_External_Ehdr),
20085 sizeof (Elf32_External_Phdr),
20086 sizeof (Elf32_External_Shdr),
20087 sizeof (Elf32_External_Rel),
20088 sizeof (Elf32_External_Rela),
20089 sizeof (Elf32_External_Sym),
20090 sizeof (Elf32_External_Dyn),
20091 sizeof (Elf_External_Note),
20092 4,
20093 1,
20094 32, 2,
20095 ELFCLASS32, EV_CURRENT,
20096 bfd_elf32_write_out_phdrs,
20097 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 20098 bfd_elf32_checksum_contents,
0beaef2b
PB		 20099 bfd_elf32_write_relocs,
20100 elf32_arm_swap_symbol_in,
20101 elf32_arm_swap_symbol_out,
20102 bfd_elf32_slurp_reloc_table,
20103 bfd_elf32_slurp_symbol_table,
20104 bfd_elf32_swap_dyn_in,
20105 bfd_elf32_swap_dyn_out,
20106 bfd_elf32_swap_reloc_in,
20107 bfd_elf32_swap_reloc_out,
20108 bfd_elf32_swap_reloca_in,
20109 bfd_elf32_swap_reloca_out
20110};
20111
685e70ae
VK		 20112static bfd_vma
20113read_code32 (const bfd *abfd, const bfd_byte *addr)
20114{
20115 /* V7 BE8 code is always little endian. */
20116 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
20117 return bfd_getl32 (addr);
20118
20119 return bfd_get_32 (abfd, addr);
20120}
20121
20122static bfd_vma
20123read_code16 (const bfd *abfd, const bfd_byte *addr)
20124{
20125 /* V7 BE8 code is always little endian. */
20126 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
20127 return bfd_getl16 (addr);
20128
20129 return bfd_get_16 (abfd, addr);
20130}
20131
6a631e86
YG		 20132/* Return size of plt0 entry starting at ADDR
20133 or (bfd_vma) -1 if size can not be determined. */
20134
20135static bfd_vma
20136elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
20137{
20138 bfd_vma first_word;
20139 bfd_vma plt0_size;
20140
685e70ae 20141 first_word = read_code32 (abfd, addr);
6a631e86
YG		 20142
20143 if (first_word == elf32_arm_plt0_entry[0])
20144 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
20145 else if (first_word == elf32_thumb2_plt0_entry[0])
20146 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
20147 else
20148 /* We don't yet handle this PLT format. */
20149 return (bfd_vma) -1;
20150
20151 return plt0_size;
20152}
20153
20154/* Return size of plt entry starting at offset OFFSET
20155 of plt section located at address START
20156 or (bfd_vma) -1 if size can not be determined. */
20157
20158static bfd_vma
20159elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
20160{
20161 bfd_vma first_insn;
20162 bfd_vma plt_size = 0;
20163 const bfd_byte *addr = start + offset;
20164
20165 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 20166 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 20167 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
20168
20169 /* Respect Thumb stub if necessary. */
685e70ae 20170 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 20171 {
20172 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
20173 }
20174
20175 /* Strip immediate from first add. */
685e70ae 20176 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 20177
20178#ifdef FOUR_WORD_PLT
20179 if (first_insn == elf32_arm_plt_entry[0])
20180 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
20181#else
20182 if (first_insn == elf32_arm_plt_entry_long[0])
20183 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
20184 else if (first_insn == elf32_arm_plt_entry_short[0])
20185 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
20186#endif
20187 else
20188 /* We don't yet handle this PLT format. */
20189 return (bfd_vma) -1;
20190
20191 return plt_size;
20192}
20193
20194/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
20195
20196static long
20197elf32_arm_get_synthetic_symtab (bfd *abfd,
20198 long symcount ATTRIBUTE_UNUSED,
20199 asymbol **syms ATTRIBUTE_UNUSED,
20200 long dynsymcount,
20201 asymbol **dynsyms,
20202 asymbol **ret)
20203{
20204 asection *relplt;
20205 asymbol *s;
20206 arelent *p;
20207 long count, i, n;
20208 size_t size;
20209 Elf_Internal_Shdr *hdr;
20210 char *names;
20211 asection *plt;
20212 bfd_vma offset;
20213 bfd_byte *data;
20214
20215 *ret = NULL;
20216
20217 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
20218 return 0;
20219
20220 if (dynsymcount <= 0)
20221 return 0;
20222
20223 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
20224 if (relplt == NULL)
20225 return 0;
20226
20227 hdr = &elf_section_data (relplt)->this_hdr;
20228 if (hdr->sh_link != elf_dynsymtab (abfd)
20229 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
20230 return 0;
20231
20232 plt = bfd_get_section_by_name (abfd, ".plt");
20233 if (plt == NULL)
20234 return 0;
20235
20236 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
20237 return -1;
20238
20239 data = plt->contents;
20240 if (data == NULL)
20241 {
20242 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
20243 return -1;
20244 bfd_cache_section_contents((asection *) plt, data);
20245 }
20246
20247 count = relplt->size / hdr->sh_entsize;
20248 size = count * sizeof (asymbol);
20249 p = relplt->relocation;
20250 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20251 {
20252 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
20253 if (p->addend != 0)
20254 size += sizeof ("+0x") - 1 + 8;
20255 }
20256
20257 s = *ret = (asymbol *) bfd_malloc (size);
20258 if (s == NULL)
20259 return -1;
20260
20261 offset = elf32_arm_plt0_size (abfd, data);
20262 if (offset == (bfd_vma) -1)
20263 return -1;
20264
20265 names = (char *) (s + count);
20266 p = relplt->relocation;
20267 n = 0;
20268 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20269 {
20270 size_t len;
20271
20272 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
20273 if (plt_size == (bfd_vma) -1)
20274 break;
20275
20276 *s = **p->sym_ptr_ptr;
20277 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20278 we are defining a symbol, ensure one of them is set. */
20279 if ((s->flags & BSF_LOCAL) == 0)
20280 s->flags |= BSF_GLOBAL;
20281 s->flags |= BSF_SYNTHETIC;
20282 s->section = plt;
20283 s->value = offset;
20284 s->name = names;
20285 s->udata.p = NULL;
20286 len = strlen ((*p->sym_ptr_ptr)->name);
20287 memcpy (names, (*p->sym_ptr_ptr)->name, len);
20288 names += len;
20289 if (p->addend != 0)
20290 {
20291 char buf[30], *a;
20292
20293 memcpy (names, "+0x", sizeof ("+0x") - 1);
20294 names += sizeof ("+0x") - 1;
20295 bfd_sprintf_vma (abfd, buf, p->addend);
20296 for (a = buf; *a == '0'; ++a)
20297 ;
20298 len = strlen (a);
20299 memcpy (names, a, len);
20300 names += len;
20301 }
20302 memcpy (names, "@plt", sizeof ("@plt"));
20303 names += sizeof ("@plt");
20304 ++s, ++n;
20305 offset += plt_size;
20306 }
20307
20308 return n;
20309}
20310
ac4c9b04
MG		 20311static bfd_boolean
20312elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
20313{
f0728ee3
AV		 20314 if (hdr->sh_flags & SHF_ARM_PURECODE)
20315 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 20316 return TRUE;
20317}
20318
20319static flagword
20320elf32_arm_lookup_section_flags (char *flag_name)
20321{
f0728ee3
AV		 20322 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
20323 return SHF_ARM_PURECODE;
ac4c9b04
MG		 20324
20325 return SEC_NO_FLAGS;
20326}
20327
491d01d3
YU		 20328static unsigned int
20329elf32_arm_count_additional_relocs (asection *sec)
20330{
20331 struct _arm_elf_section_data *arm_data;
20332 arm_data = get_arm_elf_section_data (sec);
5025eb7c 20333
6342be70 20334 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 20335}
20336
5522f910 20337/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 20338 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 20339 FALSE otherwise. ISECTION is the best guess matching section from the
20340 input bfd IBFD, but it might be NULL. */
20341
20342static bfd_boolean
20343elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
20344 bfd *obfd ATTRIBUTE_UNUSED,
20345 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
20346 Elf_Internal_Shdr *osection)
20347{
20348 switch (osection->sh_type)
20349 {
20350 case SHT_ARM_EXIDX:
20351 {
20352 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
20353 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
20354 unsigned i = 0;
20355
20356 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
20357 osection->sh_info = 0;
20358
20359 /* The sh_link field must be set to the text section associated with
20360 this index section. Unfortunately the ARM EHABI does not specify
20361 exactly how to determine this association. Our caller does try
20362 to match up OSECTION with its corresponding input section however
20363 so that is a good first guess. */
20364 if (isection != NULL
20365 && osection->bfd_section != NULL
20366 && isection->bfd_section != NULL
20367 && isection->bfd_section->output_section != NULL
20368 && isection->bfd_section->output_section == osection->bfd_section
20369 && iheaders != NULL
20370 && isection->sh_link > 0
20371 && isection->sh_link < elf_numsections (ibfd)
20372 && iheaders[isection->sh_link]->bfd_section != NULL
20373 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
20374 )
20375 {
20376 for (i = elf_numsections (obfd); i-- > 0;)
20377 if (oheaders[i]->bfd_section
20378 == iheaders[isection->sh_link]->bfd_section->output_section)
20379 break;
20380 }
9eaff861 20381
5522f910
NC		 20382 if (i == 0)
20383 {
20384 /* Failing that we have to find a matching section ourselves. If
20385 we had the output section name available we could compare that
20386 with input section names. Unfortunately we don't. So instead
20387 we use a simple heuristic and look for the nearest executable
20388 section before this one. */
20389 for (i = elf_numsections (obfd); i-- > 0;)
20390 if (oheaders[i] == osection)
20391 break;
20392 if (i == 0)
20393 break;
20394
20395 while (i-- > 0)
20396 if (oheaders[i]->sh_type == SHT_PROGBITS
20397 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
20398 == (SHF_ALLOC | SHF_EXECINSTR))
20399 break;
20400 }
20401
20402 if (i)
20403 {
20404 osection->sh_link = i;
20405 /* If the text section was part of a group
20406 then the index section should be too. */
20407 if (oheaders[i]->sh_flags & SHF_GROUP)
20408 osection->sh_flags |= SHF_GROUP;
20409 return TRUE;
20410 }
20411 }
20412 break;
20413
20414 case SHT_ARM_PREEMPTMAP:
20415 osection->sh_flags = SHF_ALLOC;
20416 break;
20417
20418 case SHT_ARM_ATTRIBUTES:
20419 case SHT_ARM_DEBUGOVERLAY:
20420 case SHT_ARM_OVERLAYSECTION:
20421 default:
20422 break;
20423 }
20424
20425 return FALSE;
20426}
20427
d691934d
NC		 20428/* Returns TRUE if NAME is an ARM mapping symbol.
20429 Traditionally the symbols $a, $d and $t have been used.
20430 The ARM ELF standard also defines $x (for A64 code). It also allows a
20431 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20432 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20433 not support them here. $t.x indicates the start of ThumbEE instructions. */
20434
20435static bfd_boolean
20436is_arm_mapping_symbol (const char * name)
20437{
20438 return name != NULL /* Paranoia. */
20439 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
20440 the mapping symbols could have acquired a prefix.
20441 We do not support this here, since such symbols no
20442 longer conform to the ARM ELF ABI. */
20443 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
20444 && (name[2] == 0 || name[2] == '.');
20445 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20446 any characters that follow the period are legal characters for the body
20447 of a symbol's name. For now we just assume that this is the case. */
20448}
20449
fca2a38f
NC		 20450/* Make sure that mapping symbols in object files are not removed via the
20451 "strip --strip-unneeded" tool. These symbols are needed in order to
20452 correctly generate interworking veneers, and for byte swapping code
20453 regions. Once an object file has been linked, it is safe to remove the
20454 symbols as they will no longer be needed. */
20455
20456static void
20457elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
20458{
20459 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 20460 && sym->section != bfd_abs_section_ptr
d691934d 20461 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 20462 sym->flags |= BSF_KEEP;
20463}
20464
5522f910
NC		 20465#undef elf_backend_copy_special_section_fields
20466#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20467
252b5132 20468#define ELF_ARCH bfd_arch_arm
ae95ffa6 20469#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 20470#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 20471#ifdef __QNXTARGET__
20472#define ELF_MAXPAGESIZE 0x1000
20473#else
7572ca89 20474#define ELF_MAXPAGESIZE 0x10000
d0facd1b 20475#endif
b1342370 20476#define ELF_MINPAGESIZE 0x1000
24718e3b 20477#define ELF_COMMONPAGESIZE 0x1000
252b5132 20478
07d6d2b8 20479#define bfd_elf32_mkobject elf32_arm_mkobject
ba93b8ac 20480
99e4ae17
AJ		 20481#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20482#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 20483#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20484#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
07d6d2b8 20485#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 20486#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 20487#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
07d6d2b8
AM		 20488#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
20489#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 20490#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 20491#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 20492#define bfd_elf32_bfd_final_link elf32_arm_final_link
07d6d2b8 20493#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132 20494
07d6d2b8
AM		 20495#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
20496#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 20497#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
07d6d2b8 20498#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 20499#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 20500#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 20501#define elf_backend_write_section elf32_arm_write_section
252b5132 20502#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
07d6d2b8 20503#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 20504#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20505#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20506#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 20507#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 20508#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ed7e9d0b 20509#define elf_backend_init_file_header elf32_arm_init_file_header
99e4ae17 20510#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 20511#define elf_backend_object_p elf32_arm_object_p
07d6d2b8
AM		 20512#define elf_backend_fake_sections elf32_arm_fake_sections
20513#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20514#define elf_backend_final_write_processing elf32_arm_final_write_processing
20515#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 20516#define elf_backend_size_info elf32_arm_size_info
b294bdf8 20517#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
07d6d2b8
AM		 20518#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20519#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 20520#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
07d6d2b8 20521#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 20522#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 20523#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 20524#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 20525
20526#define elf_backend_can_refcount 1
20527#define elf_backend_can_gc_sections 1
20528#define elf_backend_plt_readonly 1
20529#define elf_backend_want_got_plt 1
20530#define elf_backend_want_plt_sym 0
5474d94f 20531#define elf_backend_want_dynrelro 1
906e58ca
NC		 20532#define elf_backend_may_use_rel_p 1
20533#define elf_backend_may_use_rela_p 0
4e7fd91e 20534#define elf_backend_default_use_rela_p 0
64f52338 20535#define elf_backend_dtrel_excludes_plt 1
252b5132 20536
04f7c78d 20537#define elf_backend_got_header_size 12
b68a20d6 20538#define elf_backend_extern_protected_data 1
04f7c78d 20539
07d6d2b8 20540#undef elf_backend_obj_attrs_vendor
906e58ca 20541#define elf_backend_obj_attrs_vendor "aeabi"
07d6d2b8 20542#undef elf_backend_obj_attrs_section
906e58ca 20543#define elf_backend_obj_attrs_section ".ARM.attributes"
07d6d2b8 20544#undef elf_backend_obj_attrs_arg_type
906e58ca 20545#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
07d6d2b8 20546#undef elf_backend_obj_attrs_section_type
104d59d1 20547#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb 20548#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
07d6d2b8 20549#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 20550
07d6d2b8 20551#undef elf_backend_section_flags
ac4c9b04 20552#define elf_backend_section_flags elf32_arm_section_flags
07d6d2b8
AM		 20553#undef elf_backend_lookup_section_flags_hook
20554#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
ac4c9b04 20555
a2f63b2e
MR		 20556#define elf_backend_linux_prpsinfo32_ugid16 TRUE
20557
252b5132 20558#include "elf32-target.h"
7f266840 20559
b38cadfb
NC		 20560/* Native Client targets. */
20561
20562#undef TARGET_LITTLE_SYM
6d00b590 20563#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 20564#undef TARGET_LITTLE_NAME
20565#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
20566#undef TARGET_BIG_SYM
6d00b590 20567#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 20568#undef TARGET_BIG_NAME
20569#define TARGET_BIG_NAME "elf32-bigarm-nacl"
20570
20571/* Like elf32_arm_link_hash_table_create -- but overrides
20572 appropriately for NaCl. */
20573
20574static struct bfd_link_hash_table *
20575elf32_arm_nacl_link_hash_table_create (bfd *abfd)
20576{
20577 struct bfd_link_hash_table *ret;
20578
20579 ret = elf32_arm_link_hash_table_create (abfd);
20580 if (ret)
20581 {
20582 struct elf32_arm_link_hash_table *htab
20583 = (struct elf32_arm_link_hash_table *) ret;
20584
20585 htab->nacl_p = 1;
20586
20587 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
20588 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
20589 }
20590 return ret;
20591}
20592
20593/* Since NaCl doesn't use the ARM-specific unwind format, we don't
20594 really need to use elf32_arm_modify_segment_map. But we do it
20595 anyway just to reduce gratuitous differences with the stock ARM backend. */
20596
20597static bfd_boolean
20598elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
20599{
20600 return (elf32_arm_modify_segment_map (abfd, info)
20601 && nacl_modify_segment_map (abfd, info));
20602}
20603
cc364be6
AM		 20604static bfd_boolean
20605elf32_arm_nacl_final_write_processing (bfd *abfd)
887badb3 20606{
cc364be6
AM		 20607 arm_final_write_processing (abfd);
20608 return nacl_final_write_processing (abfd);
887badb3
RM		 20609}
20610
6a631e86
YG		 20611static bfd_vma
20612elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
20613 const arelent *rel ATTRIBUTE_UNUSED)
20614{
20615 return plt->vma
20616 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
20617 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
20618}
887badb3 20619
b38cadfb 20620#undef elf32_bed
6a631e86 20621#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 20622#undef bfd_elf32_bfd_link_hash_table_create
20623#define bfd_elf32_bfd_link_hash_table_create \
20624 elf32_arm_nacl_link_hash_table_create
20625#undef elf_backend_plt_alignment
6a631e86 20626#define elf_backend_plt_alignment 4
b38cadfb
NC		 20627#undef elf_backend_modify_segment_map
20628#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
6d6c25c8
AM		 20629#undef elf_backend_modify_headers
20630#define elf_backend_modify_headers nacl_modify_headers
887badb3
RM		 20631#undef elf_backend_final_write_processing
20632#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 20633#undef bfd_elf32_get_synthetic_symtab
20634#undef elf_backend_plt_sym_val
20635#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 20636#undef elf_backend_copy_special_section_fields
b38cadfb 20637
887badb3
RM		 20638#undef ELF_MINPAGESIZE
20639#undef ELF_COMMONPAGESIZE
20640
b38cadfb
NC		 20641
20642#include "elf32-target.h"
20643
20644/* Reset to defaults. */
20645#undef elf_backend_plt_alignment
20646#undef elf_backend_modify_segment_map
20647#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
6d6c25c8 20648#undef elf_backend_modify_headers
887badb3
RM		 20649#undef elf_backend_final_write_processing
20650#define elf_backend_final_write_processing elf32_arm_final_write_processing
20651#undef ELF_MINPAGESIZE
20652#define ELF_MINPAGESIZE 0x1000
20653#undef ELF_COMMONPAGESIZE
20654#define ELF_COMMONPAGESIZE 0x1000
20655
b38cadfb 20656
617a5ada
CL		 20657/* FDPIC Targets. */
20658
20659#undef TARGET_LITTLE_SYM
20660#define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20661#undef TARGET_LITTLE_NAME
20662#define TARGET_LITTLE_NAME "elf32-littlearm-fdpic"
20663#undef TARGET_BIG_SYM
20664#define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20665#undef TARGET_BIG_NAME
20666#define TARGET_BIG_NAME "elf32-bigarm-fdpic"
20667#undef elf_match_priority
20668#define elf_match_priority 128
18a20338
CL		 20669#undef ELF_OSABI
20670#define ELF_OSABI ELFOSABI_ARM_FDPIC
617a5ada
CL		 20671
20672/* Like elf32_arm_link_hash_table_create -- but overrides
20673 appropriately for FDPIC. */
20674
20675static struct bfd_link_hash_table *
20676elf32_arm_fdpic_link_hash_table_create (bfd *abfd)
20677{
20678 struct bfd_link_hash_table *ret;
20679
20680 ret = elf32_arm_link_hash_table_create (abfd);
20681 if (ret)
20682 {
20683 struct elf32_arm_link_hash_table *htab = (struct elf32_arm_link_hash_table *) ret;
20684
20685 htab->fdpic_p = 1;
20686 }
20687 return ret;
20688}
20689
e8b09b87
CL		 20690/* We need dynamic symbols for every section, since segments can
20691 relocate independently. */
20692static bfd_boolean
20693elf32_arm_fdpic_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
20694 struct bfd_link_info *info
20695 ATTRIBUTE_UNUSED,
20696 asection *p ATTRIBUTE_UNUSED)
20697{
20698 switch (elf_section_data (p)->this_hdr.sh_type)
20699 {
20700 case SHT_PROGBITS:
20701 case SHT_NOBITS:
20702 /* If sh_type is yet undecided, assume it could be
20703 SHT_PROGBITS/SHT_NOBITS. */
20704 case SHT_NULL:
20705 return FALSE;
20706
20707 /* There shouldn't be section relative relocations
20708 against any other section. */
20709 default:
20710 return TRUE;
20711 }
20712}
20713
617a5ada
CL		 20714#undef elf32_bed
20715#define elf32_bed elf32_arm_fdpic_bed
20716
20717#undef bfd_elf32_bfd_link_hash_table_create
4b24dd1a 20718#define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
617a5ada 20719
e8b09b87
CL		 20720#undef elf_backend_omit_section_dynsym
20721#define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20722
617a5ada 20723#include "elf32-target.h"
e8b09b87 20724
617a5ada 20725#undef elf_match_priority
18a20338 20726#undef ELF_OSABI
e8b09b87 20727#undef elf_backend_omit_section_dynsym
617a5ada 20728
906e58ca 20729/* VxWorks Targets. */
4e7fd91e 20730
07d6d2b8
AM		 20731#undef TARGET_LITTLE_SYM
20732#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20733#undef TARGET_LITTLE_NAME
20734#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
20735#undef TARGET_BIG_SYM
20736#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20737#undef TARGET_BIG_NAME
20738#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
4e7fd91e
PB		 20739
20740/* Like elf32_arm_link_hash_table_create -- but overrides
20741 appropriately for VxWorks. */
906e58ca 20742
4e7fd91e
PB		 20743static struct bfd_link_hash_table *
20744elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
20745{
20746 struct bfd_link_hash_table *ret;
20747
20748 ret = elf32_arm_link_hash_table_create (abfd);
20749 if (ret)
20750 {
20751 struct elf32_arm_link_hash_table *htab
00a97672 20752 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 20753 htab->use_rel = 0;
00a97672 20754 htab->vxworks_p = 1;
4e7fd91e
PB		 20755 }
20756 return ret;
906e58ca 20757}
4e7fd91e 20758
cc364be6
AM		 20759static bfd_boolean
20760elf32_arm_vxworks_final_write_processing (bfd *abfd)
00a97672 20761{
cc364be6
AM		 20762 arm_final_write_processing (abfd);
20763 return elf_vxworks_final_write_processing (abfd);
00a97672
RS		 20764}
20765
906e58ca 20766#undef elf32_bed
4e7fd91e
PB		 20767#define elf32_bed elf32_arm_vxworks_bed
20768
906e58ca
NC		 20769#undef bfd_elf32_bfd_link_hash_table_create
20770#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 20771#undef elf_backend_final_write_processing
20772#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20773#undef elf_backend_emit_relocs
9eaff861 20774#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 20775
906e58ca 20776#undef elf_backend_may_use_rel_p
00a97672 20777#define elf_backend_may_use_rel_p 0
906e58ca 20778#undef elf_backend_may_use_rela_p
00a97672 20779#define elf_backend_may_use_rela_p 1
906e58ca 20780#undef elf_backend_default_use_rela_p
00a97672 20781#define elf_backend_default_use_rela_p 1
906e58ca 20782#undef elf_backend_want_plt_sym
00a97672 20783#define elf_backend_want_plt_sym 1
906e58ca 20784#undef ELF_MAXPAGESIZE
00a97672 20785#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 20786
20787#include "elf32-target.h"
20788
20789
21d799b5
NC		 20790/* Merge backend specific data from an object file to the output
20791 object file when linking. */
20792
20793static bfd_boolean
50e03d47 20794elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 20795{
50e03d47 20796 bfd *obfd = info->output_bfd;
21d799b5
NC		 20797 flagword out_flags;
20798 flagword in_flags;
20799 bfd_boolean flags_compatible = TRUE;
20800 asection *sec;
20801
cc643b88 20802 /* Check if we have the same endianness. */
50e03d47 20803 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 20804 return FALSE;
20805
20806 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
20807 return TRUE;
20808
50e03d47 20809 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 20810 return FALSE;
20811
20812 /* The input BFD must have had its flags initialised. */
20813 /* The following seems bogus to me -- The flags are initialized in
20814 the assembler but I don't think an elf_flags_init field is
20815 written into the object. */
20816 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20817
20818 in_flags = elf_elfheader (ibfd)->e_flags;
20819 out_flags = elf_elfheader (obfd)->e_flags;
20820
20821 /* In theory there is no reason why we couldn't handle this. However
20822 in practice it isn't even close to working and there is no real
20823 reason to want it. */
20824 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
20825 && !(ibfd->flags & DYNAMIC)
20826 && (in_flags & EF_ARM_BE8))
20827 {
871b3ab2 20828 _bfd_error_handler (_("error: %pB is already in final BE8 format"),
21d799b5
NC		 20829 ibfd);
20830 return FALSE;
20831 }
20832
20833 if (!elf_flags_init (obfd))
20834 {
20835 /* If the input is the default architecture and had the default
20836 flags then do not bother setting the flags for the output
20837 architecture, instead allow future merges to do this. If no
20838 future merges ever set these flags then they will retain their
99059e56
RM		 20839 uninitialised values, which surprise surprise, correspond
20840 to the default values. */
21d799b5
NC		 20841 if (bfd_get_arch_info (ibfd)->the_default
20842 && elf_elfheader (ibfd)->e_flags == 0)
20843 return TRUE;
20844
20845 elf_flags_init (obfd) = TRUE;
20846 elf_elfheader (obfd)->e_flags = in_flags;
20847
20848 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
20849 && bfd_get_arch_info (obfd)->the_default)
20850 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
20851
20852 return TRUE;
20853 }
20854
20855 /* Determine what should happen if the input ARM architecture
20856 does not match the output ARM architecture. */
20857 if (! bfd_arm_merge_machines (ibfd, obfd))
20858 return FALSE;
20859
20860 /* Identical flags must be compatible. */
20861 if (in_flags == out_flags)
20862 return TRUE;
20863
20864 /* Check to see if the input BFD actually contains any sections. If
20865 not, its flags may not have been initialised either, but it
20866 cannot actually cause any incompatiblity. Do not short-circuit
20867 dynamic objects; their section list may be emptied by
20868 elf_link_add_object_symbols.
20869
20870 Also check to see if there are no code sections in the input.
20871 In this case there is no need to check for code specific flags.
20872 XXX - do we need to worry about floating-point format compatability
20873 in data sections ? */
20874 if (!(ibfd->flags & DYNAMIC))
20875 {
20876 bfd_boolean null_input_bfd = TRUE;
20877 bfd_boolean only_data_sections = TRUE;
20878
20879 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
20880 {
20881 /* Ignore synthetic glue sections. */
20882 if (strcmp (sec->name, ".glue_7")
20883 && strcmp (sec->name, ".glue_7t"))
20884 {
fd361982 20885 if ((bfd_section_flags (sec)
21d799b5
NC		 20886 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
20887 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 20888 only_data_sections = FALSE;
21d799b5
NC		 20889
20890 null_input_bfd = FALSE;
20891 break;
20892 }
20893 }
20894
20895 if (null_input_bfd || only_data_sections)
20896 return TRUE;
20897 }
20898
20899 /* Complain about various flag mismatches. */
20900 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
20901 EF_ARM_EABI_VERSION (out_flags)))
20902 {
20903 _bfd_error_handler
90b6238f 20904 (_("error: source object %pB has EABI version %d, but target %pB has EABI version %d"),
c08bb8dd
AM		 20905 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
20906 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 20907 return FALSE;
20908 }
20909
20910 /* Not sure what needs to be checked for EABI versions >= 1. */
20911 /* VxWorks libraries do not use these flags. */
20912 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
20913 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
20914 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
20915 {
20916 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
20917 {
20918 _bfd_error_handler
871b3ab2 20919 (_("error: %pB is compiled for APCS-%d, whereas target %pB uses APCS-%d"),
c08bb8dd
AM		 20920 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
20921 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 20922 flags_compatible = FALSE;
20923 }
20924
20925 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
20926 {
20927 if (in_flags & EF_ARM_APCS_FLOAT)
20928 _bfd_error_handler
871b3ab2 20929 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
21d799b5
NC		 20930 ibfd, obfd);
20931 else
20932 _bfd_error_handler
871b3ab2 20933 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
21d799b5
NC		 20934 ibfd, obfd);
20935
20936 flags_compatible = FALSE;
20937 }
20938
20939 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
20940 {
20941 if (in_flags & EF_ARM_VFP_FLOAT)
20942 _bfd_error_handler
90b6238f
AM		 20943 (_("error: %pB uses %s instructions, whereas %pB does not"),
20944 ibfd, "VFP", obfd);
21d799b5
NC		 20945 else
20946 _bfd_error_handler
90b6238f
AM		 20947 (_("error: %pB uses %s instructions, whereas %pB does not"),
20948 ibfd, "FPA", obfd);
21d799b5
NC		 20949
20950 flags_compatible = FALSE;
20951 }
20952
20953 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
20954 {
20955 if (in_flags & EF_ARM_MAVERICK_FLOAT)
20956 _bfd_error_handler
90b6238f
AM		 20957 (_("error: %pB uses %s instructions, whereas %pB does not"),
20958 ibfd, "Maverick", obfd);
21d799b5
NC		 20959 else
20960 _bfd_error_handler
90b6238f
AM		 20961 (_("error: %pB does not use %s instructions, whereas %pB does"),
20962 ibfd, "Maverick", obfd);
21d799b5
NC		 20963
20964 flags_compatible = FALSE;
20965 }
20966
20967#ifdef EF_ARM_SOFT_FLOAT
20968 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
20969 {
20970 /* We can allow interworking between code that is VFP format
20971 layout, and uses either soft float or integer regs for
20972 passing floating point arguments and results. We already
20973 know that the APCS_FLOAT flags match; similarly for VFP
20974 flags. */
20975 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
20976 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
20977 {
20978 if (in_flags & EF_ARM_SOFT_FLOAT)
20979 _bfd_error_handler
871b3ab2 20980 (_("error: %pB uses software FP, whereas %pB uses hardware FP"),
21d799b5
NC		 20981 ibfd, obfd);
20982 else
20983 _bfd_error_handler
871b3ab2 20984 (_("error: %pB uses hardware FP, whereas %pB uses software FP"),
21d799b5
NC		 20985 ibfd, obfd);
20986
20987 flags_compatible = FALSE;
20988 }
20989 }
20990#endif
20991
20992 /* Interworking mismatch is only a warning. */
20993 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
20994 {
20995 if (in_flags & EF_ARM_INTERWORK)
20996 {
20997 _bfd_error_handler
90b6238f 20998 (_("warning: %pB supports interworking, whereas %pB does not"),
21d799b5
NC		 20999 ibfd, obfd);
21000 }
21001 else
21002 {
21003 _bfd_error_handler
90b6238f 21004 (_("warning: %pB does not support interworking, whereas %pB does"),
21d799b5
NC		 21005 ibfd, obfd);
21006 }
21007 }
21008 }
21009
21010 return flags_compatible;
21011}
21012
21013
906e58ca 21014/* Symbian OS Targets. */
7f266840 21015
07d6d2b8
AM		 21016#undef TARGET_LITTLE_SYM
21017#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
21018#undef TARGET_LITTLE_NAME
21019#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
21020#undef TARGET_BIG_SYM
21021#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
21022#undef TARGET_BIG_NAME
21023#define TARGET_BIG_NAME "elf32-bigarm-symbian"
7f266840
DJ		 21024
21025/* Like elf32_arm_link_hash_table_create -- but overrides
21026 appropriately for Symbian OS. */
906e58ca 21027
7f266840
DJ		 21028static struct bfd_link_hash_table *
21029elf32_arm_symbian_link_hash_table_create (bfd *abfd)
21030{
21031 struct bfd_link_hash_table *ret;
21032
21033 ret = elf32_arm_link_hash_table_create (abfd);
21034 if (ret)
21035 {
21036 struct elf32_arm_link_hash_table *htab
21037 = (struct elf32_arm_link_hash_table *)ret;
21038 /* There is no PLT header for Symbian OS. */
21039 htab->plt_header_size = 0;
95720a86
DJ		 21040 /* The PLT entries are each one instruction and one word. */
21041 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 21042 htab->symbian_p = 1;
33bfe774
JB		 21043 /* Symbian uses armv5t or above, so use_blx is always true. */
21044 htab->use_blx = 1;
67687978 21045 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 21046 }
21047 return ret;
906e58ca 21048}
7f266840 21049
b35d266b 21050static const struct bfd_elf_special_section
551b43fd 21051elf32_arm_symbian_special_sections[] =
7f266840 21052{
5cd3778d
MM		 21053 /* In a BPABI executable, the dynamic linking sections do not go in
21054 the loadable read-only segment. The post-linker may wish to
21055 refer to these sections, but they are not part of the final
21056 program image. */
07d6d2b8
AM		 21057 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
21058 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
21059 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
21060 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
21061 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 21062 /* These sections do not need to be writable as the SymbianOS
21063 postlinker will arrange things so that no dynamic relocation is
21064 required. */
07d6d2b8
AM		 21065 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
21066 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
0112cd26 21067 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
07d6d2b8 21068 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 21069};
21070
c3c76620 21071static void
906e58ca 21072elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 21073 struct bfd_link_info *link_info)
c3c76620
MM		 21074{
21075 /* BPABI objects are never loaded directly by an OS kernel; they are
21076 processed by a postlinker first, into an OS-specific format. If
21077 the D_PAGED bit is set on the file, BFD will align segments on
21078 page boundaries, so that an OS can directly map the file. With
21079 BPABI objects, that just results in wasted space. In addition,
21080 because we clear the D_PAGED bit, map_sections_to_segments will
21081 recognize that the program headers should not be mapped into any
21082 loadable segment. */
21083 abfd->flags &= ~D_PAGED;
906e58ca 21084 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 21085}
7f266840
DJ		 21086
21087static bfd_boolean
906e58ca 21088elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 21089 struct bfd_link_info *info)
7f266840
DJ		 21090{
21091 struct elf_segment_map *m;
21092 asection *dynsec;
21093
7f266840
DJ		 21094 /* BPABI shared libraries and executables should have a PT_DYNAMIC
21095 segment. However, because the .dynamic section is not marked
21096 with SEC_LOAD, the generic ELF code will not create such a
21097 segment. */
21098 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
21099 if (dynsec)
21100 {
12bd6957 21101 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 21102 if (m->p_type == PT_DYNAMIC)
21103 break;
21104
21105 if (m == NULL)
21106 {
21107 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 21108 m->next = elf_seg_map (abfd);
21109 elf_seg_map (abfd) = m;
8ded5a0f 21110 }
7f266840
DJ		 21111 }
21112
b294bdf8
MM		 21113 /* Also call the generic arm routine. */
21114 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 21115}
21116
95720a86
DJ		 21117/* Return address for Ith PLT stub in section PLT, for relocation REL
21118 or (bfd_vma) -1 if it should not be included. */
21119
21120static bfd_vma
21121elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
21122 const arelent *rel ATTRIBUTE_UNUSED)
21123{
21124 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
21125}
21126
8029a119 21127#undef elf32_bed
7f266840
DJ		 21128#define elf32_bed elf32_arm_symbian_bed
21129
21130/* The dynamic sections are not allocated on SymbianOS; the postlinker
21131 will process them and then discard them. */
906e58ca 21132#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 21133#define ELF_DYNAMIC_SEC_FLAGS \
21134 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
21135
9eaff861 21136#undef elf_backend_emit_relocs
c3c76620 21137
906e58ca
NC		 21138#undef bfd_elf32_bfd_link_hash_table_create
21139#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
21140#undef elf_backend_special_sections
07d6d2b8 21141#define elf_backend_special_sections elf32_arm_symbian_special_sections
906e58ca
NC		 21142#undef elf_backend_begin_write_processing
21143#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
21144#undef elf_backend_final_write_processing
21145#define elf_backend_final_write_processing elf32_arm_final_write_processing
21146
21147#undef elf_backend_modify_segment_map
7f266840
DJ		 21148#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
21149
21150/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 21151#undef elf_backend_got_header_size
7f266840
DJ		 21152#define elf_backend_got_header_size 0
21153
21154/* Similarly, there is no .got.plt section. */
906e58ca 21155#undef elf_backend_want_got_plt
7f266840
DJ		 21156#define elf_backend_want_got_plt 0
21157
906e58ca 21158#undef elf_backend_plt_sym_val
95720a86
DJ		 21159#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
21160
906e58ca 21161#undef elf_backend_may_use_rel_p
00a97672 21162#define elf_backend_may_use_rel_p 1
906e58ca 21163#undef elf_backend_may_use_rela_p
00a97672 21164#define elf_backend_may_use_rela_p 0
906e58ca 21165#undef elf_backend_default_use_rela_p
00a97672 21166#define elf_backend_default_use_rela_p 0
906e58ca 21167#undef elf_backend_want_plt_sym
00a97672 21168#define elf_backend_want_plt_sym 0
64f52338
AM		 21169#undef elf_backend_dtrel_excludes_plt
21170#define elf_backend_dtrel_excludes_plt 0
906e58ca 21171#undef ELF_MAXPAGESIZE
00a97672 21172#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 21173
7f266840 21174#include "elf32-target.h"
GDB Binutils - Deliverables
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