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Allow stubs without associated input section in ARM backend
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
6f2750fe 2 Copyright (C) 1998-2016 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
7f266840
DJ		 59#define elf_info_to_howto 0
60#define elf_info_to_howto_rel elf32_arm_info_to_howto
61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
240 HOWTO (R_ARM_THM_PC8, /* type */
241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
99059e56
RM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
99059e56
RM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
99059e56
RM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
99059e56
RM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
99059e56
RM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
99059e56
RM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
99059e56
RM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
99059e56
RM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
99059e56
RM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
446 TRUE, /* pc_relative */
447 0, /* bitpos */
448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
99059e56
RM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
460 FALSE, /* pc_relative */
461 0, /* bitpos */
462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
99059e56
RM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
474 TRUE, /* pc_relative */
475 0, /* bitpos */
476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
909 HOWTO (R_ARM_ALU_PC_G0, /* type */
910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
917 "R_ARM_ALU_PC_G0", /* name */
918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
937 HOWTO (R_ARM_ALU_PC_G1, /* type */
938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
945 "R_ARM_ALU_PC_G1", /* name */
946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
951 HOWTO (R_ARM_ALU_PC_G2, /* type */
952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
959 "R_ARM_ALU_PC_G2", /* name */
960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
965 HOWTO (R_ARM_LDR_PC_G1, /* type */
966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
973 "R_ARM_LDR_PC_G1", /* name */
974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
979 HOWTO (R_ARM_LDR_PC_G2, /* type */
980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
987 "R_ARM_LDR_PC_G2", /* name */
988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
1001 "R_ARM_LDRS_PC_G0", /* name */
1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
1015 "R_ARM_LDRS_PC_G1", /* name */
1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
1029 "R_ARM_LDRS_PC_G2", /* name */
1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
1043 "R_ARM_LDC_PC_G0", /* name */
1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
1057 "R_ARM_LDC_PC_G1", /* name */
1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
1071 "R_ARM_LDC_PC_G2", /* name */
1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
1085 "R_ARM_ALU_SB_G0_NC", /* name */
1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
1099 "R_ARM_ALU_SB_G0", /* name */
1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
1113 "R_ARM_ALU_SB_G1_NC", /* name */
1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
1127 "R_ARM_ALU_SB_G1", /* name */
1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
1141 "R_ARM_ALU_SB_G2", /* name */
1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
1155 "R_ARM_LDR_SB_G0", /* name */
1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
1169 "R_ARM_LDR_SB_G1", /* name */
1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
1183 "R_ARM_LDR_SB_G2", /* name */
1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
1197 "R_ARM_LDRS_SB_G0", /* name */
1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
1211 "R_ARM_LDRS_SB_G1", /* name */
1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
1225 "R_ARM_LDRS_SB_G2", /* name */
1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
1239 "R_ARM_LDC_SB_G0", /* name */
1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
1253 "R_ARM_LDC_SB_G1", /* name */
1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
1267 "R_ARM_LDC_SB_G2", /* name */
1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
1486
1487 /* GNU extension to record C++ vtable member usage */
1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
99059e56
RM		 1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
1494 complain_overflow_dont, /* complain_on_overflow */
1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
99059e56
RM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
1509 complain_overflow_dont, /* complain_on_overflow */
1510 NULL, /* special_function */
1511 "R_ARM_GNU_VTINHERIT", /* name */
1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
99059e56
RM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
99059e56
RM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
99059e56
RM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
99059e56
RM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
99059e56
RM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
1608 complain_overflow_bitfield,/* complain_on_overflow */
75c11999 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92
RS		 1748/* 160 onwards: */
1749static reloc_howto_type elf32_arm_howto_table_2[1] =
1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
99059e56
RM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
1763 FALSE) /* pcrel_offset */
34e77a92 1764};
c19d1205 1765
34e77a92
RS		 1766/* 249-255 extended, currently unused, relocations: */
1767static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1768{
1769 HOWTO (R_ARM_RREL32, /* type */
1770 0, /* rightshift */
1771 0, /* size (0 = byte, 1 = short, 2 = long) */
1772 0, /* bitsize */
1773 FALSE, /* pc_relative */
1774 0, /* bitpos */
1775 complain_overflow_dont,/* complain_on_overflow */
1776 bfd_elf_generic_reloc, /* special_function */
1777 "R_ARM_RREL32", /* name */
1778 FALSE, /* partial_inplace */
1779 0, /* src_mask */
1780 0, /* dst_mask */
1781 FALSE), /* pcrel_offset */
1782
1783 HOWTO (R_ARM_RABS32, /* type */
1784 0, /* rightshift */
1785 0, /* size (0 = byte, 1 = short, 2 = long) */
1786 0, /* bitsize */
1787 FALSE, /* pc_relative */
1788 0, /* bitpos */
1789 complain_overflow_dont,/* complain_on_overflow */
1790 bfd_elf_generic_reloc, /* special_function */
1791 "R_ARM_RABS32", /* name */
1792 FALSE, /* partial_inplace */
1793 0, /* src_mask */
1794 0, /* dst_mask */
1795 FALSE), /* pcrel_offset */
1796
1797 HOWTO (R_ARM_RPC24, /* type */
1798 0, /* rightshift */
1799 0, /* size (0 = byte, 1 = short, 2 = long) */
1800 0, /* bitsize */
1801 FALSE, /* pc_relative */
1802 0, /* bitpos */
1803 complain_overflow_dont,/* complain_on_overflow */
1804 bfd_elf_generic_reloc, /* special_function */
1805 "R_ARM_RPC24", /* name */
1806 FALSE, /* partial_inplace */
1807 0, /* src_mask */
1808 0, /* dst_mask */
1809 FALSE), /* pcrel_offset */
1810
1811 HOWTO (R_ARM_RBASE, /* type */
1812 0, /* rightshift */
1813 0, /* size (0 = byte, 1 = short, 2 = long) */
1814 0, /* bitsize */
1815 FALSE, /* pc_relative */
1816 0, /* bitpos */
1817 complain_overflow_dont,/* complain_on_overflow */
1818 bfd_elf_generic_reloc, /* special_function */
1819 "R_ARM_RBASE", /* name */
1820 FALSE, /* partial_inplace */
1821 0, /* src_mask */
1822 0, /* dst_mask */
1823 FALSE) /* pcrel_offset */
1824};
1825
1826static reloc_howto_type *
1827elf32_arm_howto_from_type (unsigned int r_type)
1828{
906e58ca 1829 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1830 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1831
34e77a92
RS		 1832 if (r_type == R_ARM_IRELATIVE)
1833 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1834
c19d1205 1835 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1836 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1837 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1838
c19d1205 1839 return NULL;
7f266840
DJ		 1840}
1841
1842static void
1843elf32_arm_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, arelent * bfd_reloc,
1844 Elf_Internal_Rela * elf_reloc)
1845{
1846 unsigned int r_type;
1847
1848 r_type = ELF32_R_TYPE (elf_reloc->r_info);
1849 bfd_reloc->howto = elf32_arm_howto_from_type (r_type);
1850}
1851
1852struct elf32_arm_reloc_map
1853 {
1854 bfd_reloc_code_real_type bfd_reloc_val;
1855 unsigned char elf_reloc_val;
1856 };
1857
1858/* All entries in this list must also be present in elf32_arm_howto_table. */
1859static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1860 {
1861 {BFD_RELOC_NONE, R_ARM_NONE},
1862 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1863 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1864 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
7f266840
DJ		 1865 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1866 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1867 {BFD_RELOC_32, R_ARM_ABS32},
1868 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1869 {BFD_RELOC_8, R_ARM_ABS8},
1870 {BFD_RELOC_16, R_ARM_ABS16},
1871 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
1872 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1873 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1874 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1875 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1876 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1877 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1878 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
7f266840
DJ		 1879 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1880 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1881 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
c19d1205 1882 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
7f266840 1883 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
b43420e6 1884 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
7f266840
DJ		 1885 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1886 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1887 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1888 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1889 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1890 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac
DJ		 1891 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
1892 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
0855e32b
NS		 1893 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1894 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
1895 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
1896 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
1897 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
1898 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1899 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1900 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1901 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1902 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1903 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
1904 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1905 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1906 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
34e77a92 1907 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
c19d1205
ZW		 1908 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1909 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1910 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1911 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1912 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1913 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1914 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1915 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1916 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1917 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1918 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1919 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1920 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1921 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1922 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1923 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1924 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1925 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1926 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1927 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1928 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1929 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1930 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1931 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1932 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1933 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1934 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
1935 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
1936 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
1937 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
1938 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
1939 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
1940 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
1941 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
1942 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
1943 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
1944 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 1945 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 1946 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
1947 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
1948 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
1949 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
1950 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 1951 };
1952
1953static reloc_howto_type *
f1c71a59
ZW		 1954elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1955 bfd_reloc_code_real_type code)
7f266840
DJ		 1956{
1957 unsigned int i;
8029a119 1958
906e58ca 1959 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 1960 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
1961 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 1962
c19d1205 1963 return NULL;
7f266840
DJ		 1964}
1965
157090f7
AM		 1966static reloc_howto_type *
1967elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1968 const char *r_name)
1969{
1970 unsigned int i;
1971
906e58ca 1972 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 1973 if (elf32_arm_howto_table_1[i].name != NULL
1974 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
1975 return &elf32_arm_howto_table_1[i];
1976
906e58ca 1977 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 1978 if (elf32_arm_howto_table_2[i].name != NULL
1979 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
1980 return &elf32_arm_howto_table_2[i];
1981
34e77a92
RS		 1982 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
1983 if (elf32_arm_howto_table_3[i].name != NULL
1984 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
1985 return &elf32_arm_howto_table_3[i];
1986
157090f7
AM		 1987 return NULL;
1988}
1989
906e58ca
NC		 1990/* Support for core dump NOTE sections. */
1991
7f266840 1992static bfd_boolean
f1c71a59 1993elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 1994{
1995 int offset;
1996 size_t size;
1997
1998 switch (note->descsz)
1999 {
2000 default:
2001 return FALSE;
2002
8029a119 2003 case 148: /* Linux/ARM 32-bit. */
7f266840 2004 /* pr_cursig */
228e534f 2005 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2006
2007 /* pr_pid */
228e534f 2008 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2009
2010 /* pr_reg */
2011 offset = 72;
2012 size = 72;
2013
2014 break;
2015 }
2016
2017 /* Make a ".reg/999" section. */
2018 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2019 size, note->descpos + offset);
2020}
2021
2022static bfd_boolean
f1c71a59 2023elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2024{
2025 switch (note->descsz)
2026 {
2027 default:
2028 return FALSE;
2029
8029a119 2030 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2031 elf_tdata (abfd)->core->pid
4395ee08 2032 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2033 elf_tdata (abfd)->core->program
7f266840 2034 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2035 elf_tdata (abfd)->core->command
7f266840
DJ		 2036 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2037 }
2038
2039 /* Note that for some reason, a spurious space is tacked
2040 onto the end of the args in some (at least one anyway)
2041 implementations, so strip it off if it exists. */
7f266840 2042 {
228e534f 2043 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2044 int n = strlen (command);
2045
2046 if (0 < n && command[n - 1] == ' ')
2047 command[n - 1] = '\0';
2048 }
2049
2050 return TRUE;
2051}
2052
1f20dca5
UW		 2053static char *
2054elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2055 int note_type, ...)
2056{
2057 switch (note_type)
2058 {
2059 default:
2060 return NULL;
2061
2062 case NT_PRPSINFO:
2063 {
2064 char data[124];
2065 va_list ap;
2066
2067 va_start (ap, note_type);
2068 memset (data, 0, sizeof (data));
2069 strncpy (data + 28, va_arg (ap, const char *), 16);
2070 strncpy (data + 44, va_arg (ap, const char *), 80);
2071 va_end (ap);
2072
2073 return elfcore_write_note (abfd, buf, bufsiz,
2074 "CORE", note_type, data, sizeof (data));
2075 }
2076
2077 case NT_PRSTATUS:
2078 {
2079 char data[148];
2080 va_list ap;
2081 long pid;
2082 int cursig;
2083 const void *greg;
2084
2085 va_start (ap, note_type);
2086 memset (data, 0, sizeof (data));
2087 pid = va_arg (ap, long);
2088 bfd_put_32 (abfd, pid, data + 24);
2089 cursig = va_arg (ap, int);
2090 bfd_put_16 (abfd, cursig, data + 12);
2091 greg = va_arg (ap, const void *);
2092 memcpy (data + 72, greg, 72);
2093 va_end (ap);
2094
2095 return elfcore_write_note (abfd, buf, bufsiz,
2096 "CORE", note_type, data, sizeof (data));
2097 }
2098 }
2099}
2100
6d00b590 2101#define TARGET_LITTLE_SYM arm_elf32_le_vec
7f266840 2102#define TARGET_LITTLE_NAME "elf32-littlearm"
6d00b590 2103#define TARGET_BIG_SYM arm_elf32_be_vec
7f266840
DJ		 2104#define TARGET_BIG_NAME "elf32-bigarm"
2105
2106#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2107#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2108#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2109
252b5132
RH		 2110typedef unsigned long int insn32;
2111typedef unsigned short int insn16;
2112
3a4a14e9
PB		 2113/* In lieu of proper flags, assume all EABIv4 or later objects are
2114 interworkable. */
57e8b36a 2115#define INTERWORK_FLAG(abfd) \
3a4a14e9 2116 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2117 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2118 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2119
252b5132
RH		 2120/* The linker script knows the section names for placement.
2121 The entry_names are used to do simple name mangling on the stubs.
2122 Given a function name, and its type, the stub can be found. The
9b485d32 2123 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2124#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2125#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2126
2127#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2128#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2129
c7b8f16e
JB		 2130#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2131#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2132
a504d23a
LA		 2133#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2134#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2135
845b51d6
PB		 2136#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2137#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2138
7413f23f
DJ		 2139#define STUB_ENTRY_NAME "__%s_veneer"
2140
252b5132
RH		 2141/* The name of the dynamic interpreter. This is put in the .interp
2142 section. */
2143#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2144
0855e32b 2145static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2146{
2147 0xe08e0000, /* add r0, lr, r0 */
2148 0xe5901004, /* ldr r1, [r0,#4] */
2149 0xe12fff11, /* bx r1 */
2150};
0855e32b
NS		 2151
2152static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2153{
2154 0xe52d2004, /* push {r2} */
2155 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2156 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2157 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2158 0xe081100f, /* 2: add r1, pc */
2159 0xe12fff12, /* bx r2 */
2160 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2161 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2162 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2163};
0855e32b 2164
5e681ec4
PB		 2165#ifdef FOUR_WORD_PLT
2166
252b5132
RH		 2167/* The first entry in a procedure linkage table looks like
2168 this. It is set up so that any shared library function that is
59f2c4e7 2169 called before the relocation has been set up calls the dynamic
9b485d32 2170 linker first. */
e5a52504 2171static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2172{
2173 0xe52de004, /* str lr, [sp, #-4]! */
2174 0xe59fe010, /* ldr lr, [pc, #16] */
2175 0xe08fe00e, /* add lr, pc, lr */
2176 0xe5bef008, /* ldr pc, [lr, #8]! */
2177};
5e681ec4
PB		 2178
2179/* Subsequent entries in a procedure linkage table look like
2180 this. */
e5a52504 2181static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2182{
2183 0xe28fc600, /* add ip, pc, #NN */
2184 0xe28cca00, /* add ip, ip, #NN */
2185 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2186 0x00000000, /* unused */
2187};
5e681ec4 2188
eed94f8f 2189#else /* not FOUR_WORD_PLT */
5e681ec4 2190
5e681ec4
PB		 2191/* The first entry in a procedure linkage table looks like
2192 this. It is set up so that any shared library function that is
2193 called before the relocation has been set up calls the dynamic
2194 linker first. */
e5a52504 2195static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2196{
2197 0xe52de004, /* str lr, [sp, #-4]! */
2198 0xe59fe004, /* ldr lr, [pc, #4] */
2199 0xe08fe00e, /* add lr, pc, lr */
2200 0xe5bef008, /* ldr pc, [lr, #8]! */
2201 0x00000000, /* &GOT[0] - . */
2202};
252b5132 2203
1db37fe6
YG		 2204/* By default subsequent entries in a procedure linkage table look like
2205 this. Offsets that don't fit into 28 bits will cause link error. */
2206static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2207{
2208 0xe28fc600, /* add ip, pc, #0xNN00000 */
2209 0xe28cca00, /* add ip, ip, #0xNN000 */
2210 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2211};
5e681ec4 2212
1db37fe6
YG		 2213/* When explicitly asked, we'll use this "long" entry format
2214 which can cope with arbitrary displacements. */
2215static const bfd_vma elf32_arm_plt_entry_long [] =
2216{
2217 0xe28fc200, /* add ip, pc, #0xN0000000 */
2218 0xe28cc600, /* add ip, ip, #0xNN00000 */
2219 0xe28cca00, /* add ip, ip, #0xNN000 */
2220 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2221};
2222
2223static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2224
eed94f8f
NC		 2225#endif /* not FOUR_WORD_PLT */
2226
2227/* The first entry in a procedure linkage table looks like this.
2228 It is set up so that any shared library function that is called before the
2229 relocation has been set up calls the dynamic linker first. */
2230static const bfd_vma elf32_thumb2_plt0_entry [] =
2231{
2232 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2233 an instruction maybe encoded to one or two array elements. */
2234 0xf8dfb500, /* push {lr} */
2235 0x44fee008, /* ldr.w lr, [pc, #8] */
469a3493 2236 /* add lr, pc */
eed94f8f
NC		 2237 0xff08f85e, /* ldr.w pc, [lr, #8]! */
2238 0x00000000, /* &GOT[0] - . */
2239};
2240
2241/* Subsequent entries in a procedure linkage table for thumb only target
2242 look like this. */
2243static const bfd_vma elf32_thumb2_plt_entry [] =
2244{
2245 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2246 an instruction maybe encoded to one or two array elements. */
2247 0x0c00f240, /* movw ip, #0xNNNN */
2248 0x0c00f2c0, /* movt ip, #0xNNNN */
2249 0xf8dc44fc, /* add ip, pc */
2250 0xbf00f000 /* ldr.w pc, [ip] */
469a3493 2251 /* nop */
eed94f8f 2252};
252b5132 2253
00a97672
RS		 2254/* The format of the first entry in the procedure linkage table
2255 for a VxWorks executable. */
2256static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb
NC		 2257{
2258 0xe52dc008, /* str ip,[sp,#-8]! */
2259 0xe59fc000, /* ldr ip,[pc] */
2260 0xe59cf008, /* ldr pc,[ip,#8] */
2261 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
2262};
00a97672
RS		 2263
2264/* The format of subsequent entries in a VxWorks executable. */
2265static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb
NC		 2266{
2267 0xe59fc000, /* ldr ip,[pc] */
2268 0xe59cf000, /* ldr pc,[ip] */
2269 0x00000000, /* .long @got */
2270 0xe59fc000, /* ldr ip,[pc] */
2271 0xea000000, /* b _PLT */
2272 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2273};
00a97672
RS		 2274
2275/* The format of entries in a VxWorks shared library. */
2276static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb
NC		 2277{
2278 0xe59fc000, /* ldr ip,[pc] */
2279 0xe79cf009, /* ldr pc,[ip,r9] */
2280 0x00000000, /* .long @got */
2281 0xe59fc000, /* ldr ip,[pc] */
2282 0xe599f008, /* ldr pc,[r9,#8] */
2283 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2284};
00a97672 2285
b7693d02
DJ		 2286/* An initial stub used if the PLT entry is referenced from Thumb code. */
2287#define PLT_THUMB_STUB_SIZE 4
2288static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2289{
2290 0x4778, /* bx pc */
2291 0x46c0 /* nop */
2292};
b7693d02 2293
e5a52504
MM		 2294/* The entries in a PLT when using a DLL-based target with multiple
2295 address spaces. */
906e58ca 2296static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb
NC		 2297{
2298 0xe51ff004, /* ldr pc, [pc, #-4] */
2299 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
2300};
2301
2302/* The first entry in a procedure linkage table looks like
2303 this. It is set up so that any shared library function that is
2304 called before the relocation has been set up calls the dynamic
2305 linker first. */
2306static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2307{
2308 /* First bundle: */
2309 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2310 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2311 0xe08cc00f, /* add ip, ip, pc */
2312 0xe52dc008, /* str ip, [sp, #-8]! */
2313 /* Second bundle: */
edccdf7c
RM		 2314 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2315 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2316 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2317 0xe12fff1c, /* bx ip */
b38cadfb 2318 /* Third bundle: */
edccdf7c
RM		 2319 0xe320f000, /* nop */
2320 0xe320f000, /* nop */
2321 0xe320f000, /* nop */
b38cadfb
NC		 2322 /* .Lplt_tail: */
2323 0xe50dc004, /* str ip, [sp, #-4] */
2324 /* Fourth bundle: */
edccdf7c
RM		 2325 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2326 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2327 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2328 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2329};
2330#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2331
2332/* Subsequent entries in a procedure linkage table look like this. */
2333static const bfd_vma elf32_arm_nacl_plt_entry [] =
2334{
2335 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2336 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2337 0xe08cc00f, /* add ip, ip, pc */
2338 0xea000000, /* b .Lplt_tail */
2339};
e5a52504 2340
906e58ca
NC		 2341#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2342#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2343#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2344#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2345#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2346#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2347#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2348#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2349
461a49ca 2350enum stub_insn_type
b38cadfb
NC		 2351{
2352 THUMB16_TYPE = 1,
2353 THUMB32_TYPE,
2354 ARM_TYPE,
2355 DATA_TYPE
2356};
461a49ca 2357
48229727
JB		 2358#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2359/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2360 is inserted in arm_build_one_stub(). */
2361#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2362#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2363#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2364#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2365#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2366#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2367
2368typedef struct
2369{
b38cadfb
NC		 2370 bfd_vma data;
2371 enum stub_insn_type type;
2372 unsigned int r_type;
2373 int reloc_addend;
461a49ca
DJ		 2374} insn_sequence;
2375
fea2b4d6
CL		 2376/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2377 to reach the stub if necessary. */
461a49ca 2378static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb
NC		 2379{
2380 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2381 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2382};
906e58ca 2383
fea2b4d6
CL		 2384/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2385 available. */
461a49ca 2386static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb
NC		 2387{
2388 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2389 ARM_INSN (0xe12fff1c), /* bx ip */
2390 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2391};
906e58ca 2392
d3626fb0 2393/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2394static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb
NC		 2395{
2396 THUMB16_INSN (0xb401), /* push {r0} */
2397 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2398 THUMB16_INSN (0x4684), /* mov ip, r0 */
2399 THUMB16_INSN (0xbc01), /* pop {r0} */
2400 THUMB16_INSN (0x4760), /* bx ip */
2401 THUMB16_INSN (0xbf00), /* nop */
2402 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2403};
906e58ca 2404
d3626fb0
CL		 2405/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2406 allowed. */
2407static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb
NC		 2408{
2409 THUMB16_INSN (0x4778), /* bx pc */
2410 THUMB16_INSN (0x46c0), /* nop */
2411 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2412 ARM_INSN (0xe12fff1c), /* bx ip */
2413 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2414};
d3626fb0 2415
fea2b4d6
CL		 2416/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2417 available. */
461a49ca 2418static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2419{
2420 THUMB16_INSN (0x4778), /* bx pc */
2421 THUMB16_INSN (0x46c0), /* nop */
2422 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2423 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2424};
906e58ca 2425
fea2b4d6
CL		 2426/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2427 one, when the destination is close enough. */
461a49ca 2428static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2429{
2430 THUMB16_INSN (0x4778), /* bx pc */
2431 THUMB16_INSN (0x46c0), /* nop */
2432 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2433};
c820be07 2434
cf3eccff 2435/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2436 blx to reach the stub if necessary. */
cf3eccff 2437static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb
NC		 2438{
2439 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2440 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
2441 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2442};
906e58ca 2443
cf3eccff
DJ		 2444/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2445 blx to reach the stub if necessary. We can not add into pc;
2446 it is not guaranteed to mode switch (different in ARMv6 and
2447 ARMv7). */
2448static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb
NC		 2449{
2450 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2451 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2452 ARM_INSN (0xe12fff1c), /* bx ip */
2453 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2454};
cf3eccff 2455
ebe24dd4
CL		 2456/* V4T ARM -> ARM long branch stub, PIC. */
2457static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb
NC		 2458{
2459 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2460 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2461 ARM_INSN (0xe12fff1c), /* bx ip */
2462 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2463};
ebe24dd4
CL		 2464
2465/* V4T Thumb -> ARM long branch stub, PIC. */
2466static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb
NC		 2467{
2468 THUMB16_INSN (0x4778), /* bx pc */
2469 THUMB16_INSN (0x46c0), /* nop */
2470 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2471 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
2472 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2473};
ebe24dd4 2474
d3626fb0
CL		 2475/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2476 architectures. */
ebe24dd4 2477static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb
NC		 2478{
2479 THUMB16_INSN (0xb401), /* push {r0} */
2480 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2481 THUMB16_INSN (0x46fc), /* mov ip, pc */
2482 THUMB16_INSN (0x4484), /* add ip, r0 */
2483 THUMB16_INSN (0xbc01), /* pop {r0} */
2484 THUMB16_INSN (0x4760), /* bx ip */
2485 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2486};
ebe24dd4 2487
d3626fb0
CL		 2488/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2489 allowed. */
2490static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb
NC		 2491{
2492 THUMB16_INSN (0x4778), /* bx pc */
2493 THUMB16_INSN (0x46c0), /* nop */
2494 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2495 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2496 ARM_INSN (0xe12fff1c), /* bx ip */
2497 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2498};
d3626fb0 2499
0855e32b
NS		 2500/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2501 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2502static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2503{
b38cadfb
NC		 2504 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2505 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
2506 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2507};
2508
2509/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2510 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2511static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2512{
b38cadfb
NC		 2513 THUMB16_INSN (0x4778), /* bx pc */
2514 THUMB16_INSN (0x46c0), /* nop */
2515 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2516 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
2517 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2518};
2519
7a89b94e
NC		 2520/* NaCl ARM -> ARM long branch stub. */
2521static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2522{
2523 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2524 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2525 ARM_INSN (0xe12fff1c), /* bx ip */
2526 ARM_INSN (0xe320f000), /* nop */
2527 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2528 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2529 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2530 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2531};
2532
2533/* NaCl ARM -> ARM long branch stub, PIC. */
2534static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2535{
2536 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2537 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
2538 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2539 ARM_INSN (0xe12fff1c), /* bx ip */
2540 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2541 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2542 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2543 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2544};
2545
2546
48229727
JB		 2547/* Cortex-A8 erratum-workaround stubs. */
2548
2549/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2550 can't use a conditional branch to reach this stub). */
2551
2552static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb
NC		 2553{
2554 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
2555 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2556 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2557};
48229727
JB		 2558
2559/* Stub used for b.w and bl.w instructions. */
2560
2561static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2562{
2563 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2564};
48229727
JB		 2565
2566static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2567{
2568 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2569};
48229727
JB		 2570
2571/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2572 instruction (which switches to ARM mode) to point to this stub. Jump to the
2573 real destination using an ARM-mode branch. */
2574
2575static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2576{
2577 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2578};
48229727 2579
9553db3c
NC		 2580/* For each section group there can be a specially created linker section
2581 to hold the stubs for that group. The name of the stub section is based
2582 upon the name of another section within that group with the suffix below
2583 applied.
2584
2585 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2586 create what appeared to be a linker stub section when it actually
2587 contained user code/data. For example, consider this fragment:
b38cadfb 2588
9553db3c
NC		 2589 const char * stubborn_problems[] = { "np" };
2590
2591 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2592 section called:
2593
2594 .data.rel.local.stubborn_problems
2595
2596 This then causes problems in arm32_arm_build_stubs() as it triggers:
2597
2598 // Ignore non-stub sections.
2599 if (!strstr (stub_sec->name, STUB_SUFFIX))
2600 continue;
2601
2602 And so the section would be ignored instead of being processed. Hence
2603 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2604 C identifier. */
2605#define STUB_SUFFIX ".__stub"
906e58ca 2606
738a79f6
CL		 2607/* One entry per long/short branch stub defined above. */
2608#define DEF_STUBS \
2609 DEF_STUB(long_branch_any_any) \
2610 DEF_STUB(long_branch_v4t_arm_thumb) \
2611 DEF_STUB(long_branch_thumb_only) \
2612 DEF_STUB(long_branch_v4t_thumb_thumb) \
2613 DEF_STUB(long_branch_v4t_thumb_arm) \
2614 DEF_STUB(short_branch_v4t_thumb_arm) \
2615 DEF_STUB(long_branch_any_arm_pic) \
2616 DEF_STUB(long_branch_any_thumb_pic) \
2617 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2618 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2619 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2620 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2621 DEF_STUB(long_branch_any_tls_pic) \
2622 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2623 DEF_STUB(long_branch_arm_nacl) \
2624 DEF_STUB(long_branch_arm_nacl_pic) \
48229727
JB		 2625 DEF_STUB(a8_veneer_b_cond) \
2626 DEF_STUB(a8_veneer_b) \
2627 DEF_STUB(a8_veneer_bl) \
2628 DEF_STUB(a8_veneer_blx)
738a79f6
CL		 2629
2630#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2631enum elf32_arm_stub_type
2632{
906e58ca 2633 arm_stub_none,
738a79f6
CL		 2634 DEF_STUBS
2635};
2636#undef DEF_STUB
2637
8d9d9490
TP		 2638/* Note the first a8_veneer type. */
2639const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2640
738a79f6
CL		 2641typedef struct
2642{
d3ce72d0 2643 const insn_sequence* template_sequence;
738a79f6
CL		 2644 int template_size;
2645} stub_def;
2646
2647#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2648static const stub_def stub_definitions[] =
2649{
738a79f6
CL		 2650 {NULL, 0},
2651 DEF_STUBS
906e58ca
NC		 2652};
2653
2654struct elf32_arm_stub_hash_entry
2655{
2656 /* Base hash table entry structure. */
2657 struct bfd_hash_entry root;
2658
2659 /* The stub section. */
2660 asection *stub_sec;
2661
2662 /* Offset within stub_sec of the beginning of this stub. */
2663 bfd_vma stub_offset;
2664
2665 /* Given the symbol's value and its section we can determine its final
2666 value when building the stubs (so the stub knows where to jump). */
2667 bfd_vma target_value;
2668 asection *target_section;
2669
8d9d9490
TP		 2670 /* Same as above but for the source of the branch to the stub. Used for
2671 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2672 such, source section does not need to be recorded since Cortex-A8 erratum
2673 workaround stubs are only generated when both source and target are in the
2674 same section. */
2675 bfd_vma source_value;
48229727
JB		 2676
2677 /* The instruction which caused this stub to be generated (only valid for
2678 Cortex-A8 erratum workaround stubs at present). */
2679 unsigned long orig_insn;
2680
461a49ca 2681 /* The stub type. */
906e58ca 2682 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2683 /* Its encoding size in bytes. */
2684 int stub_size;
2685 /* Its template. */
2686 const insn_sequence *stub_template;
2687 /* The size of the template (number of entries). */
2688 int stub_template_size;
906e58ca
NC		 2689
2690 /* The symbol table entry, if any, that this was derived from. */
2691 struct elf32_arm_link_hash_entry *h;
2692
35fc36a8
RS		 2693 /* Type of branch. */
2694 enum arm_st_branch_type branch_type;
906e58ca
NC		 2695
2696 /* Where this stub is being called from, or, in the case of combined
2697 stub sections, the first input section in the group. */
2698 asection *id_sec;
7413f23f
DJ		 2699
2700 /* The name for the local symbol at the start of this stub. The
2701 stub name in the hash table has to be unique; this does not, so
2702 it can be friendlier. */
2703 char *output_name;
906e58ca
NC		 2704};
2705
e489d0ae
PB		 2706/* Used to build a map of a section. This is required for mixed-endian
2707 code/data. */
2708
2709typedef struct elf32_elf_section_map
2710{
2711 bfd_vma vma;
2712 char type;
2713}
2714elf32_arm_section_map;
2715
c7b8f16e
JB		 2716/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2717
2718typedef enum
2719{
2720 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2721 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2722 VFP11_ERRATUM_ARM_VENEER,
2723 VFP11_ERRATUM_THUMB_VENEER
2724}
2725elf32_vfp11_erratum_type;
2726
2727typedef struct elf32_vfp11_erratum_list
2728{
2729 struct elf32_vfp11_erratum_list *next;
2730 bfd_vma vma;
2731 union
2732 {
2733 struct
2734 {
2735 struct elf32_vfp11_erratum_list *veneer;
2736 unsigned int vfp_insn;
2737 } b;
2738 struct
2739 {
2740 struct elf32_vfp11_erratum_list *branch;
2741 unsigned int id;
2742 } v;
2743 } u;
2744 elf32_vfp11_erratum_type type;
2745}
2746elf32_vfp11_erratum_list;
2747
a504d23a
LA		 2748/* Information about a STM32L4XX erratum veneer, or a branch to such a
2749 veneer. */
2750typedef enum
2751{
2752 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2753 STM32L4XX_ERRATUM_VENEER
2754}
2755elf32_stm32l4xx_erratum_type;
2756
2757typedef struct elf32_stm32l4xx_erratum_list
2758{
2759 struct elf32_stm32l4xx_erratum_list *next;
2760 bfd_vma vma;
2761 union
2762 {
2763 struct
2764 {
2765 struct elf32_stm32l4xx_erratum_list *veneer;
2766 unsigned int insn;
2767 } b;
2768 struct
2769 {
2770 struct elf32_stm32l4xx_erratum_list *branch;
2771 unsigned int id;
2772 } v;
2773 } u;
2774 elf32_stm32l4xx_erratum_type type;
2775}
2776elf32_stm32l4xx_erratum_list;
2777
2468f9c9
PB		 2778typedef enum
2779{
2780 DELETE_EXIDX_ENTRY,
2781 INSERT_EXIDX_CANTUNWIND_AT_END
2782}
2783arm_unwind_edit_type;
2784
2785/* A (sorted) list of edits to apply to an unwind table. */
2786typedef struct arm_unwind_table_edit
2787{
2788 arm_unwind_edit_type type;
2789 /* Note: we sometimes want to insert an unwind entry corresponding to a
2790 section different from the one we're currently writing out, so record the
2791 (text) section this edit relates to here. */
2792 asection *linked_section;
2793 unsigned int index;
2794 struct arm_unwind_table_edit *next;
2795}
2796arm_unwind_table_edit;
2797
8e3de13a 2798typedef struct _arm_elf_section_data
e489d0ae 2799{
2468f9c9 2800 /* Information about mapping symbols. */
e489d0ae 2801 struct bfd_elf_section_data elf;
8e3de13a 2802 unsigned int mapcount;
c7b8f16e 2803 unsigned int mapsize;
e489d0ae 2804 elf32_arm_section_map *map;
2468f9c9 2805 /* Information about CPU errata. */
c7b8f16e
JB		 2806 unsigned int erratumcount;
2807 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2808 unsigned int stm32l4xx_erratumcount;
2809 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2810 unsigned int additional_reloc_count;
2468f9c9
PB		 2811 /* Information about unwind tables. */
2812 union
2813 {
2814 /* Unwind info attached to a text section. */
2815 struct
2816 {
2817 asection *arm_exidx_sec;
2818 } text;
2819
2820 /* Unwind info attached to an .ARM.exidx section. */
2821 struct
2822 {
2823 arm_unwind_table_edit *unwind_edit_list;
2824 arm_unwind_table_edit *unwind_edit_tail;
2825 } exidx;
2826 } u;
8e3de13a
NC		 2827}
2828_arm_elf_section_data;
e489d0ae
PB		 2829
2830#define elf32_arm_section_data(sec) \
8e3de13a 2831 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2832
48229727
JB		 2833/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2834 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2835 so may be created multiple times: we use an array of these entries whilst
2836 relaxing which we can refresh easily, then create stubs for each potentially
2837 erratum-triggering instruction once we've settled on a solution. */
2838
b38cadfb
NC		 2839struct a8_erratum_fix
2840{
48229727
JB		 2841 bfd *input_bfd;
2842 asection *section;
2843 bfd_vma offset;
8d9d9490 2844 bfd_vma target_offset;
48229727
JB		 2845 unsigned long orig_insn;
2846 char *stub_name;
2847 enum elf32_arm_stub_type stub_type;
35fc36a8 2848 enum arm_st_branch_type branch_type;
48229727
JB		 2849};
2850
2851/* A table of relocs applied to branches which might trigger Cortex-A8
2852 erratum. */
2853
b38cadfb
NC		 2854struct a8_erratum_reloc
2855{
48229727
JB		 2856 bfd_vma from;
2857 bfd_vma destination;
92750f34
DJ		 2858 struct elf32_arm_link_hash_entry *hash;
2859 const char *sym_name;
48229727 2860 unsigned int r_type;
35fc36a8 2861 enum arm_st_branch_type branch_type;
48229727
JB		 2862 bfd_boolean non_a8_stub;
2863};
2864
ba93b8ac
DJ		 2865/* The size of the thread control block. */
2866#define TCB_SIZE 8
2867
34e77a92
RS		 2868/* ARM-specific information about a PLT entry, over and above the usual
2869 gotplt_union. */
b38cadfb
NC		 2870struct arm_plt_info
2871{
34e77a92
RS		 2872 /* We reference count Thumb references to a PLT entry separately,
2873 so that we can emit the Thumb trampoline only if needed. */
2874 bfd_signed_vma thumb_refcount;
2875
2876 /* Some references from Thumb code may be eliminated by BL->BLX
2877 conversion, so record them separately. */
2878 bfd_signed_vma maybe_thumb_refcount;
2879
2880 /* How many of the recorded PLT accesses were from non-call relocations.
2881 This information is useful when deciding whether anything takes the
2882 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2883 non-call references to the function should resolve directly to the
2884 real runtime target. */
2885 unsigned int noncall_refcount;
2886
2887 /* Since PLT entries have variable size if the Thumb prologue is
2888 used, we need to record the index into .got.plt instead of
2889 recomputing it from the PLT offset. */
2890 bfd_signed_vma got_offset;
2891};
2892
2893/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2894struct arm_local_iplt_info
2895{
34e77a92
RS		 2896 /* The information that is usually found in the generic ELF part of
2897 the hash table entry. */
2898 union gotplt_union root;
2899
2900 /* The information that is usually found in the ARM-specific part of
2901 the hash table entry. */
2902 struct arm_plt_info arm;
2903
2904 /* A list of all potential dynamic relocations against this symbol. */
2905 struct elf_dyn_relocs *dyn_relocs;
2906};
2907
0ffa91dd 2908struct elf_arm_obj_tdata
ba93b8ac
DJ		 2909{
2910 struct elf_obj_tdata root;
2911
2912 /* tls_type for each local got entry. */
2913 char *local_got_tls_type;
ee065d83 2914
0855e32b
NS		 2915 /* GOTPLT entries for TLS descriptors. */
2916 bfd_vma *local_tlsdesc_gotent;
2917
34e77a92
RS		 2918 /* Information for local symbols that need entries in .iplt. */
2919 struct arm_local_iplt_info **local_iplt;
2920
bf21ed78
MS		 2921 /* Zero to warn when linking objects with incompatible enum sizes. */
2922 int no_enum_size_warning;
a9dc9481
JM		 2923
2924 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2925 int no_wchar_size_warning;
ba93b8ac
DJ		 2926};
2927
0ffa91dd
NC		 2928#define elf_arm_tdata(bfd) \
2929 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 2930
0ffa91dd
NC		 2931#define elf32_arm_local_got_tls_type(bfd) \
2932 (elf_arm_tdata (bfd)->local_got_tls_type)
2933
0855e32b
NS		 2934#define elf32_arm_local_tlsdesc_gotent(bfd) \
2935 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2936
34e77a92
RS		 2937#define elf32_arm_local_iplt(bfd) \
2938 (elf_arm_tdata (bfd)->local_iplt)
2939
0ffa91dd
NC		 2940#define is_arm_elf(bfd) \
2941 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2942 && elf_tdata (bfd) != NULL \
4dfe6ac6 2943 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 2944
2945static bfd_boolean
2946elf32_arm_mkobject (bfd *abfd)
2947{
0ffa91dd 2948 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 2949 ARM_ELF_DATA);
ba93b8ac
DJ		 2950}
2951
ba93b8ac
DJ		 2952#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2953
ba96a88f 2954/* Arm ELF linker hash entry. */
252b5132 2955struct elf32_arm_link_hash_entry
b38cadfb
NC		 2956{
2957 struct elf_link_hash_entry root;
252b5132 2958
b38cadfb
NC		 2959 /* Track dynamic relocs copied for this symbol. */
2960 struct elf_dyn_relocs *dyn_relocs;
b7693d02 2961
b38cadfb
NC		 2962 /* ARM-specific PLT information. */
2963 struct arm_plt_info plt;
ba93b8ac
DJ		 2964
2965#define GOT_UNKNOWN 0
2966#define GOT_NORMAL 1
2967#define GOT_TLS_GD 2
2968#define GOT_TLS_IE 4
0855e32b
NS		 2969#define GOT_TLS_GDESC 8
2970#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 2971 unsigned int tls_type : 8;
34e77a92 2972
b38cadfb
NC		 2973 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
2974 unsigned int is_iplt : 1;
34e77a92 2975
b38cadfb 2976 unsigned int unused : 23;
a4fd1a8e 2977
b38cadfb
NC		 2978 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
2979 starting at the end of the jump table. */
2980 bfd_vma tlsdesc_got;
0855e32b 2981
b38cadfb
NC		 2982 /* The symbol marking the real symbol location for exported thumb
2983 symbols with Arm stubs. */
2984 struct elf_link_hash_entry *export_glue;
906e58ca 2985
b38cadfb 2986 /* A pointer to the most recently used stub hash entry against this
8029a119 2987 symbol. */
b38cadfb
NC		 2988 struct elf32_arm_stub_hash_entry *stub_cache;
2989};
252b5132 2990
252b5132 2991/* Traverse an arm ELF linker hash table. */
252b5132
RH		 2992#define elf32_arm_link_hash_traverse(table, func, info) \
2993 (elf_link_hash_traverse \
2994 (&(table)->root, \
b7693d02 2995 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 2996 (info)))
2997
2998/* Get the ARM elf linker hash table from a link_info structure. */
2999#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3000 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3001 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3002
906e58ca
NC		 3003#define arm_stub_hash_lookup(table, string, create, copy) \
3004 ((struct elf32_arm_stub_hash_entry *) \
3005 bfd_hash_lookup ((table), (string), (create), (copy)))
3006
21d799b5
NC		 3007/* Array to keep track of which stub sections have been created, and
3008 information on stub grouping. */
3009struct map_stub
3010{
3011 /* This is the section to which stubs in the group will be
3012 attached. */
3013 asection *link_sec;
3014 /* The stub section. */
3015 asection *stub_sec;
3016};
3017
0855e32b
NS		 3018#define elf32_arm_compute_jump_table_size(htab) \
3019 ((htab)->next_tls_desc_index * 4)
3020
9b485d32 3021/* ARM ELF linker hash table. */
252b5132 3022struct elf32_arm_link_hash_table
906e58ca
NC		 3023{
3024 /* The main hash table. */
3025 struct elf_link_hash_table root;
252b5132 3026
906e58ca
NC		 3027 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3028 bfd_size_type thumb_glue_size;
252b5132 3029
906e58ca
NC		 3030 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3031 bfd_size_type arm_glue_size;
252b5132 3032
906e58ca
NC		 3033 /* The size in bytes of section containing the ARMv4 BX veneers. */
3034 bfd_size_type bx_glue_size;
845b51d6 3035
906e58ca
NC		 3036 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3037 veneer has been populated. */
3038 bfd_vma bx_glue_offset[15];
845b51d6 3039
906e58ca
NC		 3040 /* The size in bytes of the section containing glue for VFP11 erratum
3041 veneers. */
3042 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3043
a504d23a
LA		 3044 /* The size in bytes of the section containing glue for STM32L4XX erratum
3045 veneers. */
3046 bfd_size_type stm32l4xx_erratum_glue_size;
3047
48229727
JB		 3048 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3049 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3050 elf32_arm_write_section(). */
3051 struct a8_erratum_fix *a8_erratum_fixes;
3052 unsigned int num_a8_erratum_fixes;
3053
906e58ca
NC		 3054 /* An arbitrary input BFD chosen to hold the glue sections. */
3055 bfd * bfd_of_glue_owner;
ba96a88f 3056
906e58ca
NC		 3057 /* Nonzero to output a BE8 image. */
3058 int byteswap_code;
e489d0ae 3059
906e58ca
NC		 3060 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3061 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3062 int target1_is_rel;
9c504268 3063
906e58ca
NC		 3064 /* The relocation to use for R_ARM_TARGET2 relocations. */
3065 int target2_reloc;
eb043451 3066
906e58ca
NC		 3067 /* 0 = Ignore R_ARM_V4BX.
3068 1 = Convert BX to MOV PC.
3069 2 = Generate v4 interworing stubs. */
3070 int fix_v4bx;
319850b4 3071
48229727
JB		 3072 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3073 int fix_cortex_a8;
3074
2de70689
MGD		 3075 /* Whether we should fix the ARM1176 BLX immediate issue. */
3076 int fix_arm1176;
3077
906e58ca
NC		 3078 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3079 int use_blx;
33bfe774 3080
906e58ca
NC		 3081 /* What sort of code sequences we should look for which may trigger the
3082 VFP11 denorm erratum. */
3083 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3084
906e58ca
NC		 3085 /* Global counter for the number of fixes we have emitted. */
3086 int num_vfp11_fixes;
c7b8f16e 3087
a504d23a
LA		 3088 /* What sort of code sequences we should look for which may trigger the
3089 STM32L4XX erratum. */
3090 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3091
3092 /* Global counter for the number of fixes we have emitted. */
3093 int num_stm32l4xx_fixes;
3094
906e58ca
NC		 3095 /* Nonzero to force PIC branch veneers. */
3096 int pic_veneer;
27e55c4d 3097
906e58ca
NC		 3098 /* The number of bytes in the initial entry in the PLT. */
3099 bfd_size_type plt_header_size;
e5a52504 3100
906e58ca
NC		 3101 /* The number of bytes in the subsequent PLT etries. */
3102 bfd_size_type plt_entry_size;
e5a52504 3103
906e58ca
NC		 3104 /* True if the target system is VxWorks. */
3105 int vxworks_p;
00a97672 3106
906e58ca
NC		 3107 /* True if the target system is Symbian OS. */
3108 int symbian_p;
e5a52504 3109
b38cadfb
NC		 3110 /* True if the target system is Native Client. */
3111 int nacl_p;
3112
906e58ca
NC		 3113 /* True if the target uses REL relocations. */
3114 int use_rel;
4e7fd91e 3115
0855e32b
NS		 3116 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3117 bfd_vma next_tls_desc_index;
3118
3119 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3120 bfd_vma num_tls_desc;
3121
906e58ca 3122 /* Short-cuts to get to dynamic linker sections. */
906e58ca
NC		 3123 asection *sdynbss;
3124 asection *srelbss;
5e681ec4 3125
906e58ca
NC		 3126 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3127 asection *srelplt2;
00a97672 3128
0855e32b
NS		 3129 /* The offset into splt of the PLT entry for the TLS descriptor
3130 resolver. Special values are 0, if not necessary (or not found
3131 to be necessary yet), and -1 if needed but not determined
3132 yet. */
3133 bfd_vma dt_tlsdesc_plt;
3134
3135 /* The offset into sgot of the GOT entry used by the PLT entry
3136 above. */
b38cadfb 3137 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3138
3139 /* Offset in .plt section of tls_arm_trampoline. */
3140 bfd_vma tls_trampoline;
3141
906e58ca
NC		 3142 /* Data for R_ARM_TLS_LDM32 relocations. */
3143 union
3144 {
3145 bfd_signed_vma refcount;
3146 bfd_vma offset;
3147 } tls_ldm_got;
b7693d02 3148
87d72d41
AM		 3149 /* Small local sym cache. */
3150 struct sym_cache sym_cache;
906e58ca
NC		 3151
3152 /* For convenience in allocate_dynrelocs. */
3153 bfd * obfd;
3154
0855e32b
NS		 3155 /* The amount of space used by the reserved portion of the sgotplt
3156 section, plus whatever space is used by the jump slots. */
3157 bfd_vma sgotplt_jump_table_size;
3158
906e58ca
NC		 3159 /* The stub hash table. */
3160 struct bfd_hash_table stub_hash_table;
3161
3162 /* Linker stub bfd. */
3163 bfd *stub_bfd;
3164
3165 /* Linker call-backs. */
6bde4c52
TP		 3166 asection * (*add_stub_section) (const char *, asection *, asection *,
3167 unsigned int);
906e58ca
NC		 3168 void (*layout_sections_again) (void);
3169
3170 /* Array to keep track of which stub sections have been created, and
3171 information on stub grouping. */
21d799b5 3172 struct map_stub *stub_group;
906e58ca 3173
fe33d2fa 3174 /* Number of elements in stub_group. */
7292b3ac 3175 unsigned int top_id;
fe33d2fa 3176
906e58ca
NC		 3177 /* Assorted information used by elf32_arm_size_stubs. */
3178 unsigned int bfd_count;
7292b3ac 3179 unsigned int top_index;
906e58ca
NC		 3180 asection **input_list;
3181};
252b5132 3182
a504d23a
LA		 3183static inline int
3184ctz (unsigned int mask)
3185{
3186#if GCC_VERSION >= 3004
3187 return __builtin_ctz (mask);
3188#else
3189 unsigned int i;
3190
3191 for (i = 0; i < 8 * sizeof (mask); i++)
3192 {
3193 if (mask & 0x1)
3194 break;
3195 mask = (mask >> 1);
3196 }
3197 return i;
3198#endif
3199}
3200
3201static inline int
3202popcount (unsigned int mask)
3203{
3204#if GCC_VERSION >= 3004
3205 return __builtin_popcount (mask);
3206#else
3207 unsigned int i, sum = 0;
3208
3209 for (i = 0; i < 8 * sizeof (mask); i++)
3210 {
3211 if (mask & 0x1)
3212 sum++;
3213 mask = (mask >> 1);
3214 }
3215 return sum;
3216#endif
3217}
3218
780a67af
NC		 3219/* Create an entry in an ARM ELF linker hash table. */
3220
3221static struct bfd_hash_entry *
57e8b36a 3222elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3223 struct bfd_hash_table * table,
3224 const char * string)
780a67af
NC		 3225{
3226 struct elf32_arm_link_hash_entry * ret =
3227 (struct elf32_arm_link_hash_entry *) entry;
3228
3229 /* Allocate the structure if it has not already been allocated by a
3230 subclass. */
906e58ca 3231 if (ret == NULL)
21d799b5 3232 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3233 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3234 if (ret == NULL)
780a67af
NC		 3235 return (struct bfd_hash_entry *) ret;
3236
3237 /* Call the allocation method of the superclass. */
3238 ret = ((struct elf32_arm_link_hash_entry *)
3239 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3240 table, string));
57e8b36a 3241 if (ret != NULL)
b7693d02 3242 {
0bdcacaf 3243 ret->dyn_relocs = NULL;
ba93b8ac 3244 ret->tls_type = GOT_UNKNOWN;
0855e32b 3245 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3246 ret->plt.thumb_refcount = 0;
3247 ret->plt.maybe_thumb_refcount = 0;
3248 ret->plt.noncall_refcount = 0;
3249 ret->plt.got_offset = -1;
3250 ret->is_iplt = FALSE;
a4fd1a8e 3251 ret->export_glue = NULL;
906e58ca
NC		 3252
3253 ret->stub_cache = NULL;
b7693d02 3254 }
780a67af
NC		 3255
3256 return (struct bfd_hash_entry *) ret;
3257}
3258
34e77a92
RS		 3259/* Ensure that we have allocated bookkeeping structures for ABFD's local
3260 symbols. */
3261
3262static bfd_boolean
3263elf32_arm_allocate_local_sym_info (bfd *abfd)
3264{
3265 if (elf_local_got_refcounts (abfd) == NULL)
3266 {
3267 bfd_size_type num_syms;
3268 bfd_size_type size;
3269 char *data;
3270
3271 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3272 size = num_syms * (sizeof (bfd_signed_vma)
3273 + sizeof (struct arm_local_iplt_info *)
3274 + sizeof (bfd_vma)
3275 + sizeof (char));
3276 data = bfd_zalloc (abfd, size);
3277 if (data == NULL)
3278 return FALSE;
3279
3280 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3281 data += num_syms * sizeof (bfd_signed_vma);
3282
3283 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3284 data += num_syms * sizeof (struct arm_local_iplt_info *);
3285
3286 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3287 data += num_syms * sizeof (bfd_vma);
3288
3289 elf32_arm_local_got_tls_type (abfd) = data;
3290 }
3291 return TRUE;
3292}
3293
3294/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3295 to input bfd ABFD. Create the information if it doesn't already exist.
3296 Return null if an allocation fails. */
3297
3298static struct arm_local_iplt_info *
3299elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3300{
3301 struct arm_local_iplt_info **ptr;
3302
3303 if (!elf32_arm_allocate_local_sym_info (abfd))
3304 return NULL;
3305
3306 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3307 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3308 if (*ptr == NULL)
3309 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3310 return *ptr;
3311}
3312
3313/* Try to obtain PLT information for the symbol with index R_SYMNDX
3314 in ABFD's symbol table. If the symbol is global, H points to its
3315 hash table entry, otherwise H is null.
3316
3317 Return true if the symbol does have PLT information. When returning
3318 true, point *ROOT_PLT at the target-independent reference count/offset
3319 union and *ARM_PLT at the ARM-specific information. */
3320
3321static bfd_boolean
3322elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_entry *h,
3323 unsigned long r_symndx, union gotplt_union **root_plt,
3324 struct arm_plt_info **arm_plt)
3325{
3326 struct arm_local_iplt_info *local_iplt;
3327
3328 if (h != NULL)
3329 {
3330 *root_plt = &h->root.plt;
3331 *arm_plt = &h->plt;
3332 return TRUE;
3333 }
3334
3335 if (elf32_arm_local_iplt (abfd) == NULL)
3336 return FALSE;
3337
3338 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3339 if (local_iplt == NULL)
3340 return FALSE;
3341
3342 *root_plt = &local_iplt->root;
3343 *arm_plt = &local_iplt->arm;
3344 return TRUE;
3345}
3346
3347/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3348 before it. */
3349
3350static bfd_boolean
3351elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3352 struct arm_plt_info *arm_plt)
3353{
3354 struct elf32_arm_link_hash_table *htab;
3355
3356 htab = elf32_arm_hash_table (info);
3357 return (arm_plt->thumb_refcount != 0
3358 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3359}
3360
3361/* Return a pointer to the head of the dynamic reloc list that should
3362 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3363 ABFD's symbol table. Return null if an error occurs. */
3364
3365static struct elf_dyn_relocs **
3366elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3367 Elf_Internal_Sym *isym)
3368{
3369 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3370 {
3371 struct arm_local_iplt_info *local_iplt;
3372
3373 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3374 if (local_iplt == NULL)
3375 return NULL;
3376 return &local_iplt->dyn_relocs;
3377 }
3378 else
3379 {
3380 /* Track dynamic relocs needed for local syms too.
3381 We really need local syms available to do this
3382 easily. Oh well. */
3383 asection *s;
3384 void *vpp;
3385
3386 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3387 if (s == NULL)
3388 abort ();
3389
3390 vpp = &elf_section_data (s)->local_dynrel;
3391 return (struct elf_dyn_relocs **) vpp;
3392 }
3393}
3394
906e58ca
NC		 3395/* Initialize an entry in the stub hash table. */
3396
3397static struct bfd_hash_entry *
3398stub_hash_newfunc (struct bfd_hash_entry *entry,
3399 struct bfd_hash_table *table,
3400 const char *string)
3401{
3402 /* Allocate the structure if it has not already been allocated by a
3403 subclass. */
3404 if (entry == NULL)
3405 {
21d799b5 3406 entry = (struct bfd_hash_entry *)
99059e56 3407 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3408 if (entry == NULL)
3409 return entry;
3410 }
3411
3412 /* Call the allocation method of the superclass. */
3413 entry = bfd_hash_newfunc (entry, table, string);
3414 if (entry != NULL)
3415 {
3416 struct elf32_arm_stub_hash_entry *eh;
3417
3418 /* Initialize the local fields. */
3419 eh = (struct elf32_arm_stub_hash_entry *) entry;
3420 eh->stub_sec = NULL;
3421 eh->stub_offset = 0;
8d9d9490 3422 eh->source_value = 0;
906e58ca
NC		 3423 eh->target_value = 0;
3424 eh->target_section = NULL;
cedfb179 3425 eh->orig_insn = 0;
906e58ca 3426 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3427 eh->stub_size = 0;
3428 eh->stub_template = NULL;
3429 eh->stub_template_size = 0;
906e58ca
NC		 3430 eh->h = NULL;
3431 eh->id_sec = NULL;
d8d2f433 3432 eh->output_name = NULL;
906e58ca
NC		 3433 }
3434
3435 return entry;
3436}
3437
00a97672 3438/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3439 shortcuts to them in our hash table. */
3440
3441static bfd_boolean
57e8b36a 3442create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3443{
3444 struct elf32_arm_link_hash_table *htab;
3445
e5a52504 3446 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3447 if (htab == NULL)
3448 return FALSE;
3449
e5a52504
MM		 3450 /* BPABI objects never have a GOT, or associated sections. */
3451 if (htab->symbian_p)
3452 return TRUE;
3453
5e681ec4
PB		 3454 if (! _bfd_elf_create_got_section (dynobj, info))
3455 return FALSE;
3456
5e681ec4
PB		 3457 return TRUE;
3458}
3459
34e77a92
RS		 3460/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3461
3462static bfd_boolean
3463create_ifunc_sections (struct bfd_link_info *info)
3464{
3465 struct elf32_arm_link_hash_table *htab;
3466 const struct elf_backend_data *bed;
3467 bfd *dynobj;
3468 asection *s;
3469 flagword flags;
b38cadfb 3470
34e77a92
RS		 3471 htab = elf32_arm_hash_table (info);
3472 dynobj = htab->root.dynobj;
3473 bed = get_elf_backend_data (dynobj);
3474 flags = bed->dynamic_sec_flags;
3475
3476 if (htab->root.iplt == NULL)
3477 {
3d4d4302
AM		 3478 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3479 flags | SEC_READONLY | SEC_CODE);
34e77a92 3480 if (s == NULL
a0f49396 3481 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3482 return FALSE;
3483 htab->root.iplt = s;
3484 }
3485
3486 if (htab->root.irelplt == NULL)
3487 {
3d4d4302
AM		 3488 s = bfd_make_section_anyway_with_flags (dynobj,
3489 RELOC_SECTION (htab, ".iplt"),
3490 flags | SEC_READONLY);
34e77a92 3491 if (s == NULL
a0f49396 3492 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3493 return FALSE;
3494 htab->root.irelplt = s;
3495 }
3496
3497 if (htab->root.igotplt == NULL)
3498 {
3d4d4302 3499 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3500 if (s == NULL
3501 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3502 return FALSE;
3503 htab->root.igotplt = s;
3504 }
3505 return TRUE;
3506}
3507
eed94f8f
NC		 3508/* Determine if we're dealing with a Thumb only architecture. */
3509
3510static bfd_boolean
3511using_thumb_only (struct elf32_arm_link_hash_table *globals)
3512{
2fd158eb
TP		 3513 int arch;
3514 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3515 Tag_CPU_arch_profile);
eed94f8f 3516
2fd158eb
TP		 3517 if (profile)
3518 return profile == 'M';
eed94f8f 3519
2fd158eb 3520 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3521
2fd158eb
TP		 3522 if (arch == TAG_CPU_ARCH_V6_M
3523 || arch == TAG_CPU_ARCH_V6S_M
3524 || arch == TAG_CPU_ARCH_V7E_M
3525 || arch == TAG_CPU_ARCH_V8M_BASE
3526 || arch == TAG_CPU_ARCH_V8M_MAIN)
3527 return TRUE;
eed94f8f 3528
2fd158eb 3529 return FALSE;
eed94f8f
NC		 3530}
3531
3532/* Determine if we're dealing with a Thumb-2 object. */
3533
3534static bfd_boolean
3535using_thumb2 (struct elf32_arm_link_hash_table *globals)
3536{
3537 int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3538 Tag_CPU_arch);
3539 return arch == TAG_CPU_ARCH_V6T2 || arch >= TAG_CPU_ARCH_V7;
3540}
3541
00a97672
RS		 3542/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3543 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3544 hash table. */
3545
3546static bfd_boolean
57e8b36a 3547elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3548{
3549 struct elf32_arm_link_hash_table *htab;
3550
3551 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3552 if (htab == NULL)
3553 return FALSE;
3554
362d30a1 3555 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3556 return FALSE;
3557
3558 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3559 return FALSE;
3560
3d4d4302 3561 htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss");
0e1862bb 3562 if (!bfd_link_pic (info))
3d4d4302
AM		 3563 htab->srelbss = bfd_get_linker_section (dynobj,
3564 RELOC_SECTION (htab, ".bss"));
00a97672
RS		 3565
3566 if (htab->vxworks_p)
3567 {
3568 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3569 return FALSE;
3570
0e1862bb 3571 if (bfd_link_pic (info))
00a97672
RS		 3572 {
3573 htab->plt_header_size = 0;
3574 htab->plt_entry_size
3575 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3576 }
3577 else
3578 {
3579 htab->plt_header_size
3580 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3581 htab->plt_entry_size
3582 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3583 }
aebf9be7
NC		 3584
3585 if (elf_elfheader (dynobj))
3586 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3587 }
eed94f8f
NC		 3588 else
3589 {
3590 /* PR ld/16017
3591 Test for thumb only architectures. Note - we cannot just call
3592 using_thumb_only() as the attributes in the output bfd have not been
3593 initialised at this point, so instead we use the input bfd. */
3594 bfd * saved_obfd = htab->obfd;
3595
3596 htab->obfd = dynobj;
3597 if (using_thumb_only (htab))
3598 {
3599 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3600 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3601 }
3602 htab->obfd = saved_obfd;
3603 }
5e681ec4 3604
362d30a1
RS		 3605 if (!htab->root.splt
3606 || !htab->root.srelplt
e5a52504 3607 || !htab->sdynbss
0e1862bb 3608 || (!bfd_link_pic (info) && !htab->srelbss))
5e681ec4
PB		 3609 abort ();
3610
3611 return TRUE;
3612}
3613
906e58ca
NC		 3614/* Copy the extra info we tack onto an elf_link_hash_entry. */
3615
3616static void
3617elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3618 struct elf_link_hash_entry *dir,
3619 struct elf_link_hash_entry *ind)
3620{
3621 struct elf32_arm_link_hash_entry *edir, *eind;
3622
3623 edir = (struct elf32_arm_link_hash_entry *) dir;
3624 eind = (struct elf32_arm_link_hash_entry *) ind;
3625
0bdcacaf 3626 if (eind->dyn_relocs != NULL)
906e58ca 3627 {
0bdcacaf 3628 if (edir->dyn_relocs != NULL)
906e58ca 3629 {
0bdcacaf
RS		 3630 struct elf_dyn_relocs **pp;
3631 struct elf_dyn_relocs *p;
906e58ca
NC		 3632
3633 /* Add reloc counts against the indirect sym to the direct sym
3634 list. Merge any entries against the same section. */
0bdcacaf 3635 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3636 {
0bdcacaf 3637 struct elf_dyn_relocs *q;
906e58ca 3638
0bdcacaf
RS		 3639 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3640 if (q->sec == p->sec)
906e58ca
NC		 3641 {
3642 q->pc_count += p->pc_count;
3643 q->count += p->count;
3644 *pp = p->next;
3645 break;
3646 }
3647 if (q == NULL)
3648 pp = &p->next;
3649 }
0bdcacaf 3650 *pp = edir->dyn_relocs;
906e58ca
NC		 3651 }
3652
0bdcacaf
RS		 3653 edir->dyn_relocs = eind->dyn_relocs;
3654 eind->dyn_relocs = NULL;
906e58ca
NC		 3655 }
3656
3657 if (ind->root.type == bfd_link_hash_indirect)
3658 {
3659 /* Copy over PLT info. */
34e77a92
RS		 3660 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3661 eind->plt.thumb_refcount = 0;
3662 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3663 eind->plt.maybe_thumb_refcount = 0;
3664 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3665 eind->plt.noncall_refcount = 0;
3666
3667 /* We should only allocate a function to .iplt once the final
3668 symbol information is known. */
3669 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3670
3671 if (dir->got.refcount <= 0)
3672 {
3673 edir->tls_type = eind->tls_type;
3674 eind->tls_type = GOT_UNKNOWN;
3675 }
3676 }
3677
3678 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3679}
3680
68faa637
AM		 3681/* Destroy an ARM elf linker hash table. */
3682
3683static void
d495ab0d 3684elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3685{
3686 struct elf32_arm_link_hash_table *ret
d495ab0d 3687 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3688
3689 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3690 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3691}
3692
906e58ca
NC		 3693/* Create an ARM elf linker hash table. */
3694
3695static struct bfd_link_hash_table *
3696elf32_arm_link_hash_table_create (bfd *abfd)
3697{
3698 struct elf32_arm_link_hash_table *ret;
3699 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3700
7bf52ea2 3701 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3702 if (ret == NULL)
3703 return NULL;
3704
3705 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3706 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3707 sizeof (struct elf32_arm_link_hash_entry),
3708 ARM_ELF_DATA))
906e58ca
NC		 3709 {
3710 free (ret);
3711 return NULL;
3712 }
3713
906e58ca 3714 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3715 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3716#ifdef FOUR_WORD_PLT
3717 ret->plt_header_size = 16;
3718 ret->plt_entry_size = 16;
3719#else
3720 ret->plt_header_size = 20;
1db37fe6 3721 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3722#endif
906e58ca 3723 ret->use_rel = 1;
906e58ca 3724 ret->obfd = abfd;
906e58ca
NC		 3725
3726 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3727 sizeof (struct elf32_arm_stub_hash_entry)))
3728 {
d495ab0d 3729 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3730 return NULL;
3731 }
d495ab0d 3732 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3733
3734 return &ret->root.root;
3735}
3736
cd1dac3d
DG		 3737/* Determine what kind of NOPs are available. */
3738
3739static bfd_boolean
3740arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3741{
3742 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3743 Tag_CPU_arch);
3744 return arch == TAG_CPU_ARCH_V6T2
3745 || arch == TAG_CPU_ARCH_V6K
9e3c6df6
PB		 3746 || arch == TAG_CPU_ARCH_V7
3747 || arch == TAG_CPU_ARCH_V7E_M;
cd1dac3d
DG		 3748}
3749
3750static bfd_boolean
3751arch_has_thumb2_nop (struct elf32_arm_link_hash_table *globals)
3752{
3753 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3754 Tag_CPU_arch);
9e3c6df6
PB		 3755 return (arch == TAG_CPU_ARCH_V6T2 || arch == TAG_CPU_ARCH_V7
3756 || arch == TAG_CPU_ARCH_V7E_M);
cd1dac3d
DG		 3757}
3758
f4ac8484
DJ		 3759static bfd_boolean
3760arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3761{
3762 switch (stub_type)
3763 {
fea2b4d6
CL		 3764 case arm_stub_long_branch_thumb_only:
3765 case arm_stub_long_branch_v4t_thumb_arm:
3766 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3767 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3768 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3769 case arm_stub_long_branch_thumb_only_pic:
f4ac8484
DJ		 3770 return TRUE;
3771 case arm_stub_none:
3772 BFD_FAIL ();
3773 return FALSE;
3774 break;
3775 default:
3776 return FALSE;
3777 }
3778}
3779
906e58ca
NC		 3780/* Determine the type of stub needed, if any, for a call. */
3781
3782static enum elf32_arm_stub_type
3783arm_type_of_stub (struct bfd_link_info *info,
3784 asection *input_sec,
3785 const Elf_Internal_Rela *rel,
34e77a92 3786 unsigned char st_type,
35fc36a8 3787 enum arm_st_branch_type *actual_branch_type,
906e58ca 3788 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3789 bfd_vma destination,
3790 asection *sym_sec,
3791 bfd *input_bfd,
3792 const char *name)
906e58ca
NC		 3793{
3794 bfd_vma location;
3795 bfd_signed_vma branch_offset;
3796 unsigned int r_type;
3797 struct elf32_arm_link_hash_table * globals;
3798 int thumb2;
3799 int thumb_only;
3800 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3801 int use_plt = 0;
35fc36a8 3802 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3803 union gotplt_union *root_plt;
3804 struct arm_plt_info *arm_plt;
906e58ca 3805
35fc36a8 3806 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3807 return stub_type;
3808
906e58ca 3809 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3810 if (globals == NULL)
3811 return stub_type;
906e58ca
NC		 3812
3813 thumb_only = using_thumb_only (globals);
3814
3815 thumb2 = using_thumb2 (globals);
3816
3817 /* Determine where the call point is. */
3818 location = (input_sec->output_offset
3819 + input_sec->output_section->vma
3820 + rel->r_offset);
3821
906e58ca
NC		 3822 r_type = ELF32_R_TYPE (rel->r_info);
3823
39f21624
NC		 3824 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3825 are considering a function call relocation. */
c5423981
TG		 3826 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
3827 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3828 && branch_type == ST_BRANCH_TO_ARM)
3829 branch_type = ST_BRANCH_TO_THUMB;
3830
34e77a92
RS		 3831 /* For TLS call relocs, it is the caller's responsibility to provide
3832 the address of the appropriate trampoline. */
3833 if (r_type != R_ARM_TLS_CALL
3834 && r_type != R_ARM_THM_TLS_CALL
3835 && elf32_arm_get_plt_info (input_bfd, hash, ELF32_R_SYM (rel->r_info),
3836 &root_plt, &arm_plt)
3837 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3838 {
34e77a92 3839 asection *splt;
fe33d2fa 3840
34e77a92
RS		 3841 if (hash == NULL || hash->is_iplt)
3842 splt = globals->root.iplt;
3843 else
3844 splt = globals->root.splt;
3845 if (splt != NULL)
b38cadfb 3846 {
34e77a92
RS		 3847 use_plt = 1;
3848
3849 /* Note when dealing with PLT entries: the main PLT stub is in
3850 ARM mode, so if the branch is in Thumb mode, another
3851 Thumb->ARM stub will be inserted later just before the ARM
3852 PLT stub. We don't take this extra distance into account
3853 here, because if a long branch stub is needed, we'll add a
3854 Thumb->Arm one and branch directly to the ARM PLT entry
3855 because it avoids spreading offset corrections in several
3856 places. */
3857
3858 destination = (splt->output_section->vma
3859 + splt->output_offset
3860 + root_plt->offset);
3861 st_type = STT_FUNC;
3862 branch_type = ST_BRANCH_TO_ARM;
3863 }
5fa9e92f 3864 }
34e77a92
RS		 3865 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3866 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 3867
fe33d2fa
CL		 3868 branch_offset = (bfd_signed_vma)(destination - location);
3869
0855e32b 3870 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 3871 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 3872 {
5fa9e92f
CL		 3873 /* Handle cases where:
3874 - this call goes too far (different Thumb/Thumb2 max
99059e56 3875 distance)
155d87d7 3876 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 3877 Thumb->Arm branch (not bl). A stub is needed in this case,
3878 but only if this call is not through a PLT entry. Indeed,
3879 PLT stubs handle mode switching already.
5fa9e92f 3880 */
906e58ca
NC		 3881 if ((!thumb2
3882 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
3883 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
3884 || (thumb2
3885 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
3886 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 3887 || (thumb2
3888 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
3889 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
3890 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 3891 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 3892 && (((r_type == R_ARM_THM_CALL
3893 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981
TG		 3894 || (r_type == R_ARM_THM_JUMP24)
3895 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 3896 && !use_plt))
906e58ca 3897 {
35fc36a8 3898 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 3899 {
3900 /* Thumb to thumb. */
3901 if (!thumb_only)
3902 {
0e1862bb 3903 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3904 /* PIC stubs. */
155d87d7 3905 ? ((globals->use_blx
9553db3c 3906 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 3907 /* V5T and above. Stub starts with ARM code, so
3908 we must be able to switch mode before
3909 reaching it, which is only possible for 'bl'
3910 (ie R_ARM_THM_CALL relocation). */
cf3eccff 3911 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 3912 /* On V4T, use Thumb code only. */
d3626fb0 3913 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 3914
3915 /* non-PIC stubs. */
155d87d7 3916 : ((globals->use_blx
9553db3c 3917 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 3918 /* V5T and above. */
3919 ? arm_stub_long_branch_any_any
3920 /* V4T. */
d3626fb0 3921 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 3922 }
3923 else
3924 {
0e1862bb 3925 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
ebe24dd4
CL		 3926 /* PIC stub. */
3927 ? arm_stub_long_branch_thumb_only_pic
c2b4a39d
CL		 3928 /* non-PIC stub. */
3929 : arm_stub_long_branch_thumb_only;
906e58ca
NC		 3930 }
3931 }
3932 else
3933 {
3934 /* Thumb to arm. */
c820be07
NC		 3935 if (sym_sec != NULL
3936 && sym_sec->owner != NULL
3937 && !INTERWORK_FLAG (sym_sec->owner))
3938 {
3939 (*_bfd_error_handler)
3940 (_("%B(%s): warning: interworking not enabled.\n"
3941 " first occurrence: %B: Thumb call to ARM"),
3942 sym_sec->owner, input_bfd, name);
3943 }
3944
0855e32b 3945 stub_type =
0e1862bb 3946 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3947 /* PIC stubs. */
0855e32b 3948 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 3949 /* TLS PIC stubs. */
0855e32b
NS		 3950 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
3951 : arm_stub_long_branch_v4t_thumb_tls_pic)
3952 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
3953 /* V5T PIC and above. */
3954 ? arm_stub_long_branch_any_arm_pic
3955 /* V4T PIC stub. */
3956 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 3957
3958 /* non-PIC stubs. */
0855e32b 3959 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 3960 /* V5T and above. */
3961 ? arm_stub_long_branch_any_any
3962 /* V4T. */
3963 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 3964
3965 /* Handle v4t short branches. */
fea2b4d6 3966 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 3967 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
3968 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 3969 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 3970 }
3971 }
3972 }
fe33d2fa
CL		 3973 else if (r_type == R_ARM_CALL
3974 || r_type == R_ARM_JUMP24
0855e32b
NS		 3975 || r_type == R_ARM_PLT32
3976 || r_type == R_ARM_TLS_CALL)
906e58ca 3977 {
35fc36a8 3978 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 3979 {
3980 /* Arm to thumb. */
c820be07
NC		 3981
3982 if (sym_sec != NULL
3983 && sym_sec->owner != NULL
3984 && !INTERWORK_FLAG (sym_sec->owner))
3985 {
3986 (*_bfd_error_handler)
3987 (_("%B(%s): warning: interworking not enabled.\n"
c2b4a39d 3988 " first occurrence: %B: ARM call to Thumb"),
c820be07
NC		 3989 sym_sec->owner, input_bfd, name);
3990 }
3991
3992 /* We have an extra 2-bytes reach because of
3993 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 3994 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
3995 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 3996 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 3997 || (r_type == R_ARM_JUMP24)
3998 || (r_type == R_ARM_PLT32))
906e58ca 3999 {
0e1862bb 4000 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4001 /* PIC stubs. */
ebe24dd4
CL		 4002 ? ((globals->use_blx)
4003 /* V5T and above. */
4004 ? arm_stub_long_branch_any_thumb_pic
4005 /* V4T stub. */
4006 : arm_stub_long_branch_v4t_arm_thumb_pic)
4007
c2b4a39d
CL		 4008 /* non-PIC stubs. */
4009 : ((globals->use_blx)
4010 /* V5T and above. */
4011 ? arm_stub_long_branch_any_any
4012 /* V4T. */
4013 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4014 }
4015 }
4016 else
4017 {
4018 /* Arm to arm. */
4019 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4020 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4021 {
0855e32b 4022 stub_type =
0e1862bb 4023 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4024 /* PIC stubs. */
0855e32b 4025 ? (r_type == R_ARM_TLS_CALL
6a631e86 4026 /* TLS PIC Stub. */
0855e32b 4027 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4028 : (globals->nacl_p
4029 ? arm_stub_long_branch_arm_nacl_pic
4030 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4031 /* non-PIC stubs. */
7a89b94e
NC		 4032 : (globals->nacl_p
4033 ? arm_stub_long_branch_arm_nacl
4034 : arm_stub_long_branch_any_any);
906e58ca
NC		 4035 }
4036 }
4037 }
4038
fe33d2fa
CL		 4039 /* If a stub is needed, record the actual destination type. */
4040 if (stub_type != arm_stub_none)
35fc36a8 4041 *actual_branch_type = branch_type;
fe33d2fa 4042
906e58ca
NC		 4043 return stub_type;
4044}
4045
4046/* Build a name for an entry in the stub hash table. */
4047
4048static char *
4049elf32_arm_stub_name (const asection *input_section,
4050 const asection *sym_sec,
4051 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4052 const Elf_Internal_Rela *rel,
4053 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4054{
4055 char *stub_name;
4056 bfd_size_type len;
4057
4058 if (hash)
4059 {
fe33d2fa 4060 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4061 stub_name = (char *) bfd_malloc (len);
906e58ca 4062 if (stub_name != NULL)
fe33d2fa 4063 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4064 input_section->id & 0xffffffff,
4065 hash->root.root.root.string,
fe33d2fa
CL		 4066 (int) rel->r_addend & 0xffffffff,
4067 (int) stub_type);
906e58ca
NC		 4068 }
4069 else
4070 {
fe33d2fa 4071 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4072 stub_name = (char *) bfd_malloc (len);
906e58ca 4073 if (stub_name != NULL)
fe33d2fa 4074 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4075 input_section->id & 0xffffffff,
4076 sym_sec->id & 0xffffffff,
0855e32b
NS		 4077 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4078 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4079 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4080 (int) rel->r_addend & 0xffffffff,
4081 (int) stub_type);
906e58ca
NC		 4082 }
4083
4084 return stub_name;
4085}
4086
4087/* Look up an entry in the stub hash. Stub entries are cached because
4088 creating the stub name takes a bit of time. */
4089
4090static struct elf32_arm_stub_hash_entry *
4091elf32_arm_get_stub_entry (const asection *input_section,
4092 const asection *sym_sec,
4093 struct elf_link_hash_entry *hash,
4094 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4095 struct elf32_arm_link_hash_table *htab,
4096 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4097{
4098 struct elf32_arm_stub_hash_entry *stub_entry;
4099 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4100 const asection *id_sec;
4101
4102 if ((input_section->flags & SEC_CODE) == 0)
4103 return NULL;
4104
4105 /* If this input section is part of a group of sections sharing one
4106 stub section, then use the id of the first section in the group.
4107 Stub names need to include a section id, as there may well be
4108 more than one stub used to reach say, printf, and we need to
4109 distinguish between them. */
4110 id_sec = htab->stub_group[input_section->id].link_sec;
4111
4112 if (h != NULL && h->stub_cache != NULL
4113 && h->stub_cache->h == h
fe33d2fa
CL		 4114 && h->stub_cache->id_sec == id_sec
4115 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4116 {
4117 stub_entry = h->stub_cache;
4118 }
4119 else
4120 {
4121 char *stub_name;
4122
fe33d2fa 4123 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4124 if (stub_name == NULL)
4125 return NULL;
4126
4127 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4128 stub_name, FALSE, FALSE);
4129 if (h != NULL)
4130 h->stub_cache = stub_entry;
4131
4132 free (stub_name);
4133 }
4134
4135 return stub_entry;
4136}
4137
48229727 4138/* Find or create a stub section. Returns a pointer to the stub section, and
b38cadfb 4139 the section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4140 LINK_SEC_P may be NULL. */
906e58ca 4141
48229727
JB		 4142static asection *
4143elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
4144 struct elf32_arm_link_hash_table *htab)
906e58ca
NC		 4145{
4146 asection *link_sec;
4147 asection *stub_sec;
6bde4c52 4148 asection *out_sec;
906e58ca
NC		 4149
4150 link_sec = htab->stub_group[section->id].link_sec;
9553db3c 4151 BFD_ASSERT (link_sec != NULL);
906e58ca 4152 stub_sec = htab->stub_group[section->id].stub_sec;
9553db3c 4153
906e58ca
NC		 4154 if (stub_sec == NULL)
4155 {
4156 stub_sec = htab->stub_group[link_sec->id].stub_sec;
4157 if (stub_sec == NULL)
4158 {
4159 size_t namelen;
4160 bfd_size_type len;
4161 char *s_name;
4162
4163 namelen = strlen (link_sec->name);
4164 len = namelen + sizeof (STUB_SUFFIX);
21d799b5 4165 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
906e58ca
NC		 4166 if (s_name == NULL)
4167 return NULL;
4168
4169 memcpy (s_name, link_sec->name, namelen);
4170 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
6bde4c52
TP		 4171 out_sec = link_sec->output_section;
4172 stub_sec = (*htab->add_stub_section) (s_name, out_sec, link_sec,
7a89b94e 4173 htab->nacl_p ? 4 : 3);
906e58ca
NC		 4174 if (stub_sec == NULL)
4175 return NULL;
4176 htab->stub_group[link_sec->id].stub_sec = stub_sec;
4177 }
4178 htab->stub_group[section->id].stub_sec = stub_sec;
4179 }
b38cadfb 4180
48229727
JB		 4181 if (link_sec_p)
4182 *link_sec_p = link_sec;
b38cadfb 4183
48229727
JB		 4184 return stub_sec;
4185}
4186
4187/* Add a new stub entry to the stub hash. Not all fields of the new
4188 stub entry are initialised. */
4189
4190static struct elf32_arm_stub_hash_entry *
4191elf32_arm_add_stub (const char *stub_name,
4192 asection *section,
4193 struct elf32_arm_link_hash_table *htab)
4194{
4195 asection *link_sec;
4196 asection *stub_sec;
4197 struct elf32_arm_stub_hash_entry *stub_entry;
4198
4199 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab);
4200 if (stub_sec == NULL)
4201 return NULL;
906e58ca
NC		 4202
4203 /* Enter this entry into the linker stub hash table. */
4204 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4205 TRUE, FALSE);
4206 if (stub_entry == NULL)
4207 {
6bde4c52
TP		 4208 if (section == NULL)
4209 section = stub_sec;
906e58ca
NC		 4210 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
4211 section->owner,
4212 stub_name);
4213 return NULL;
4214 }
4215
4216 stub_entry->stub_sec = stub_sec;
4217 stub_entry->stub_offset = 0;
4218 stub_entry->id_sec = link_sec;
4219
906e58ca
NC		 4220 return stub_entry;
4221}
4222
4223/* Store an Arm insn into an output section not processed by
4224 elf32_arm_write_section. */
4225
4226static void
8029a119
NC		 4227put_arm_insn (struct elf32_arm_link_hash_table * htab,
4228 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4229{
4230 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4231 bfd_putl32 (val, ptr);
4232 else
4233 bfd_putb32 (val, ptr);
4234}
4235
4236/* Store a 16-bit Thumb insn into an output section not processed by
4237 elf32_arm_write_section. */
4238
4239static void
8029a119
NC		 4240put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4241 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4242{
4243 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4244 bfd_putl16 (val, ptr);
4245 else
4246 bfd_putb16 (val, ptr);
4247}
4248
a504d23a
LA		 4249/* Store a Thumb2 insn into an output section not processed by
4250 elf32_arm_write_section. */
4251
4252static void
4253put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4254 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4255{
4256 /* T2 instructions are 16-bit streamed. */
4257 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4258 {
4259 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4260 bfd_putl16 ((val & 0xffff), ptr + 2);
4261 }
4262 else
4263 {
4264 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4265 bfd_putb16 ((val & 0xffff), ptr + 2);
4266 }
4267}
4268
0855e32b
NS		 4269/* If it's possible to change R_TYPE to a more efficient access
4270 model, return the new reloc type. */
4271
4272static unsigned
b38cadfb 4273elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4274 struct elf_link_hash_entry *h)
4275{
4276 int is_local = (h == NULL);
4277
0e1862bb
L		 4278 if (bfd_link_pic (info)
4279 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4280 return r_type;
4281
b38cadfb 4282 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4283 switch (r_type)
4284 {
4285 case R_ARM_TLS_GOTDESC:
4286 case R_ARM_TLS_CALL:
4287 case R_ARM_THM_TLS_CALL:
4288 case R_ARM_TLS_DESCSEQ:
4289 case R_ARM_THM_TLS_DESCSEQ:
4290 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4291 }
4292
4293 return r_type;
4294}
4295
48229727
JB		 4296static bfd_reloc_status_type elf32_arm_final_link_relocate
4297 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4298 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4299 const char *, unsigned char, enum arm_st_branch_type,
4300 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4301
4563a860
JB		 4302static unsigned int
4303arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4304{
4305 switch (stub_type)
4306 {
4307 case arm_stub_a8_veneer_b_cond:
4308 case arm_stub_a8_veneer_b:
4309 case arm_stub_a8_veneer_bl:
4310 return 2;
4311
4312 case arm_stub_long_branch_any_any:
4313 case arm_stub_long_branch_v4t_arm_thumb:
4314 case arm_stub_long_branch_thumb_only:
4315 case arm_stub_long_branch_v4t_thumb_thumb:
4316 case arm_stub_long_branch_v4t_thumb_arm:
4317 case arm_stub_short_branch_v4t_thumb_arm:
4318 case arm_stub_long_branch_any_arm_pic:
4319 case arm_stub_long_branch_any_thumb_pic:
4320 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4321 case arm_stub_long_branch_v4t_arm_thumb_pic:
4322 case arm_stub_long_branch_v4t_thumb_arm_pic:
4323 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4324 case arm_stub_long_branch_any_tls_pic:
4325 case arm_stub_long_branch_v4t_thumb_tls_pic:
4563a860
JB		 4326 case arm_stub_a8_veneer_blx:
4327 return 4;
b38cadfb 4328
7a89b94e
NC		 4329 case arm_stub_long_branch_arm_nacl:
4330 case arm_stub_long_branch_arm_nacl_pic:
4331 return 16;
4332
4563a860
JB		 4333 default:
4334 abort (); /* Should be unreachable. */
4335 }
4336}
4337
906e58ca
NC		 4338static bfd_boolean
4339arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4340 void * in_arg)
4341{
7a89b94e 4342#define MAXRELOCS 3
906e58ca 4343 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4344 struct elf32_arm_link_hash_table *globals;
906e58ca 4345 struct bfd_link_info *info;
906e58ca
NC		 4346 asection *stub_sec;
4347 bfd *stub_bfd;
906e58ca
NC		 4348 bfd_byte *loc;
4349 bfd_vma sym_value;
4350 int template_size;
4351 int size;
d3ce72d0 4352 const insn_sequence *template_sequence;
906e58ca 4353 int i;
48229727
JB		 4354 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4355 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4356 int nrelocs = 0;
906e58ca
NC		 4357
4358 /* Massage our args to the form they really have. */
4359 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4360 info = (struct bfd_link_info *) in_arg;
4361
4362 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4363 if (globals == NULL)
4364 return FALSE;
906e58ca 4365
906e58ca
NC		 4366 stub_sec = stub_entry->stub_sec;
4367
4dfe6ac6 4368 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4369 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4370 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4371 return TRUE;
fe33d2fa 4372
906e58ca
NC		 4373 /* Make a note of the offset within the stubs for this entry. */
4374 stub_entry->stub_offset = stub_sec->size;
4375 loc = stub_sec->contents + stub_entry->stub_offset;
4376
4377 stub_bfd = stub_sec->owner;
4378
906e58ca
NC		 4379 /* This is the address of the stub destination. */
4380 sym_value = (stub_entry->target_value
4381 + stub_entry->target_section->output_offset
4382 + stub_entry->target_section->output_section->vma);
4383
d3ce72d0 4384 template_sequence = stub_entry->stub_template;
461a49ca 4385 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4386
4387 size = 0;
461a49ca 4388 for (i = 0; i < template_size; i++)
906e58ca 4389 {
d3ce72d0 4390 switch (template_sequence[i].type)
461a49ca
DJ		 4391 {
4392 case THUMB16_TYPE:
48229727 4393 {
d3ce72d0
NC		 4394 bfd_vma data = (bfd_vma) template_sequence[i].data;
4395 if (template_sequence[i].reloc_addend != 0)
48229727 4396 {
99059e56
RM		 4397 /* We've borrowed the reloc_addend field to mean we should
4398 insert a condition code into this (Thumb-1 branch)
4399 instruction. See THUMB16_BCOND_INSN. */
4400 BFD_ASSERT ((data & 0xff00) == 0xd000);
4401 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4402 }
fe33d2fa 4403 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4404 size += 2;
4405 }
461a49ca 4406 break;
906e58ca 4407
48229727 4408 case THUMB32_TYPE:
fe33d2fa
CL		 4409 bfd_put_16 (stub_bfd,
4410 (template_sequence[i].data >> 16) & 0xffff,
4411 loc + size);
4412 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4413 loc + size + 2);
99059e56
RM		 4414 if (template_sequence[i].r_type != R_ARM_NONE)
4415 {
4416 stub_reloc_idx[nrelocs] = i;
4417 stub_reloc_offset[nrelocs++] = size;
4418 }
4419 size += 4;
4420 break;
48229727 4421
461a49ca 4422 case ARM_TYPE:
fe33d2fa
CL		 4423 bfd_put_32 (stub_bfd, template_sequence[i].data,
4424 loc + size);
461a49ca
DJ		 4425 /* Handle cases where the target is encoded within the
4426 instruction. */
d3ce72d0 4427 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4428 {
48229727
JB		 4429 stub_reloc_idx[nrelocs] = i;
4430 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4431 }
4432 size += 4;
4433 break;
4434
4435 case DATA_TYPE:
d3ce72d0 4436 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4437 stub_reloc_idx[nrelocs] = i;
4438 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4439 size += 4;
4440 break;
4441
4442 default:
4443 BFD_FAIL ();
4444 return FALSE;
4445 }
906e58ca 4446 }
461a49ca 4447
906e58ca
NC		 4448 stub_sec->size += size;
4449
461a49ca
DJ		 4450 /* Stub size has already been computed in arm_size_one_stub. Check
4451 consistency. */
4452 BFD_ASSERT (size == stub_entry->stub_size);
4453
906e58ca 4454 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4455 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4456 sym_value |= 1;
4457
48229727
JB		 4458 /* Assume there is at least one and at most MAXRELOCS entries to relocate
4459 in each stub. */
4460 BFD_ASSERT (nrelocs != 0 && nrelocs <= MAXRELOCS);
c820be07 4461
48229727 4462 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 4463 {
4464 Elf_Internal_Rela rel;
4465 bfd_boolean unresolved_reloc;
4466 char *error_message;
4467 bfd_vma points_to =
4468 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
4469
4470 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4471 rel.r_info = ELF32_R_INFO (0,
4472 template_sequence[stub_reloc_idx[i]].r_type);
4473 rel.r_addend = 0;
4474
4475 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4476 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4477 template should refer back to the instruction after the original
4478 branch. We use target_section as Cortex-A8 erratum workaround stubs
4479 are only generated when both source and target are in the same
4480 section. */
4481 points_to = stub_entry->target_section->output_section->vma
4482 + stub_entry->target_section->output_offset
4483 + stub_entry->source_value;
4484
4485 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4486 (template_sequence[stub_reloc_idx[i]].r_type),
4487 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
4488 points_to, info, stub_entry->target_section, "", STT_FUNC,
4489 stub_entry->branch_type,
4490 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4491 &error_message);
4492 }
906e58ca
NC		 4493
4494 return TRUE;
48229727 4495#undef MAXRELOCS
906e58ca
NC		 4496}
4497
48229727
JB		 4498/* Calculate the template, template size and instruction size for a stub.
4499 Return value is the instruction size. */
906e58ca 4500
48229727
JB		 4501static unsigned int
4502find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4503 const insn_sequence **stub_template,
4504 int *stub_template_size)
906e58ca 4505{
d3ce72d0 4506 const insn_sequence *template_sequence = NULL;
48229727
JB		 4507 int template_size = 0, i;
4508 unsigned int size;
906e58ca 4509
d3ce72d0 4510 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4511 if (stub_template)
4512 *stub_template = template_sequence;
4513
48229727 4514 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4515 if (stub_template_size)
4516 *stub_template_size = template_size;
906e58ca
NC		 4517
4518 size = 0;
461a49ca
DJ		 4519 for (i = 0; i < template_size; i++)
4520 {
d3ce72d0 4521 switch (template_sequence[i].type)
461a49ca
DJ		 4522 {
4523 case THUMB16_TYPE:
4524 size += 2;
4525 break;
4526
4527 case ARM_TYPE:
48229727 4528 case THUMB32_TYPE:
461a49ca
DJ		 4529 case DATA_TYPE:
4530 size += 4;
4531 break;
4532
4533 default:
4534 BFD_FAIL ();
2a229407 4535 return 0;
461a49ca
DJ		 4536 }
4537 }
4538
48229727
JB		 4539 return size;
4540}
4541
4542/* As above, but don't actually build the stub. Just bump offset so
4543 we know stub section sizes. */
4544
4545static bfd_boolean
4546arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4547 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4548{
4549 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4550 const insn_sequence *template_sequence;
48229727
JB		 4551 int template_size, size;
4552
4553 /* Massage our args to the form they really have. */
4554 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4555
4556 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4557 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4558
d3ce72d0 4559 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4560 &template_size);
4561
461a49ca 4562 stub_entry->stub_size = size;
d3ce72d0 4563 stub_entry->stub_template = template_sequence;
461a49ca
DJ		 4564 stub_entry->stub_template_size = template_size;
4565
906e58ca
NC		 4566 size = (size + 7) & ~7;
4567 stub_entry->stub_sec->size += size;
461a49ca 4568
906e58ca
NC		 4569 return TRUE;
4570}
4571
4572/* External entry points for sizing and building linker stubs. */
4573
4574/* Set up various things so that we can make a list of input sections
4575 for each output section included in the link. Returns -1 on error,
4576 0 when no stubs will be needed, and 1 on success. */
4577
4578int
4579elf32_arm_setup_section_lists (bfd *output_bfd,
4580 struct bfd_link_info *info)
4581{
4582 bfd *input_bfd;
4583 unsigned int bfd_count;
7292b3ac 4584 unsigned int top_id, top_index;
906e58ca
NC		 4585 asection *section;
4586 asection **input_list, **list;
4587 bfd_size_type amt;
4588 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4589
4dfe6ac6
NC		 4590 if (htab == NULL)
4591 return 0;
906e58ca
NC		 4592 if (! is_elf_hash_table (htab))
4593 return 0;
4594
4595 /* Count the number of input BFDs and find the top input section id. */
4596 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
4597 input_bfd != NULL;
c72f2fb2 4598 input_bfd = input_bfd->link.next)
906e58ca
NC		 4599 {
4600 bfd_count += 1;
4601 for (section = input_bfd->sections;
4602 section != NULL;
4603 section = section->next)
4604 {
4605 if (top_id < section->id)
4606 top_id = section->id;
4607 }
4608 }
4609 htab->bfd_count = bfd_count;
4610
4611 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 4612 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 4613 if (htab->stub_group == NULL)
4614 return -1;
fe33d2fa 4615 htab->top_id = top_id;
906e58ca
NC		 4616
4617 /* We can't use output_bfd->section_count here to find the top output
4618 section index as some sections may have been removed, and
4619 _bfd_strip_section_from_output doesn't renumber the indices. */
4620 for (section = output_bfd->sections, top_index = 0;
4621 section != NULL;
4622 section = section->next)
4623 {
4624 if (top_index < section->index)
4625 top_index = section->index;
4626 }
4627
4628 htab->top_index = top_index;
4629 amt = sizeof (asection *) * (top_index + 1);
21d799b5 4630 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 4631 htab->input_list = input_list;
4632 if (input_list == NULL)
4633 return -1;
4634
4635 /* For sections we aren't interested in, mark their entries with a
4636 value we can check later. */
4637 list = input_list + top_index;
4638 do
4639 *list = bfd_abs_section_ptr;
4640 while (list-- != input_list);
4641
4642 for (section = output_bfd->sections;
4643 section != NULL;
4644 section = section->next)
4645 {
4646 if ((section->flags & SEC_CODE) != 0)
4647 input_list[section->index] = NULL;
4648 }
4649
4650 return 1;
4651}
4652
4653/* The linker repeatedly calls this function for each input section,
4654 in the order that input sections are linked into output sections.
4655 Build lists of input sections to determine groupings between which
4656 we may insert linker stubs. */
4657
4658void
4659elf32_arm_next_input_section (struct bfd_link_info *info,
4660 asection *isec)
4661{
4662 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4663
4dfe6ac6
NC		 4664 if (htab == NULL)
4665 return;
4666
906e58ca
NC		 4667 if (isec->output_section->index <= htab->top_index)
4668 {
4669 asection **list = htab->input_list + isec->output_section->index;
4670
a7470592 4671 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 4672 {
4673 /* Steal the link_sec pointer for our list. */
4674#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
4675 /* This happens to make the list in reverse order,
07d72278 4676 which we reverse later. */
906e58ca
NC		 4677 PREV_SEC (isec) = *list;
4678 *list = isec;
4679 }
4680 }
4681}
4682
4683/* See whether we can group stub sections together. Grouping stub
4684 sections may result in fewer stubs. More importantly, we need to
07d72278 4685 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 4686 .fini output sections respectively, because glibc splits the
4687 _init and _fini functions into multiple parts. Putting a stub in
4688 the middle of a function is not a good idea. */
4689
4690static void
4691group_sections (struct elf32_arm_link_hash_table *htab,
4692 bfd_size_type stub_group_size,
07d72278 4693 bfd_boolean stubs_always_after_branch)
906e58ca 4694{
07d72278 4695 asection **list = htab->input_list;
906e58ca
NC		 4696
4697 do
4698 {
4699 asection *tail = *list;
07d72278 4700 asection *head;
906e58ca
NC		 4701
4702 if (tail == bfd_abs_section_ptr)
4703 continue;
4704
07d72278
DJ		 4705 /* Reverse the list: we must avoid placing stubs at the
4706 beginning of the section because the beginning of the text
4707 section may be required for an interrupt vector in bare metal
4708 code. */
4709#define NEXT_SEC PREV_SEC
e780aef2
CL		 4710 head = NULL;
4711 while (tail != NULL)
99059e56
RM		 4712 {
4713 /* Pop from tail. */
4714 asection *item = tail;
4715 tail = PREV_SEC (item);
e780aef2 4716
99059e56
RM		 4717 /* Push on head. */
4718 NEXT_SEC (item) = head;
4719 head = item;
4720 }
07d72278
DJ		 4721
4722 while (head != NULL)
906e58ca
NC		 4723 {
4724 asection *curr;
07d72278 4725 asection *next;
e780aef2
CL		 4726 bfd_vma stub_group_start = head->output_offset;
4727 bfd_vma end_of_next;
906e58ca 4728
07d72278 4729 curr = head;
e780aef2 4730 while (NEXT_SEC (curr) != NULL)
8cd931b7 4731 {
e780aef2
CL		 4732 next = NEXT_SEC (curr);
4733 end_of_next = next->output_offset + next->size;
4734 if (end_of_next - stub_group_start >= stub_group_size)
4735 /* End of NEXT is too far from start, so stop. */
8cd931b7 4736 break;
e780aef2
CL		 4737 /* Add NEXT to the group. */
4738 curr = next;
8cd931b7 4739 }
906e58ca 4740
07d72278 4741 /* OK, the size from the start to the start of CURR is less
906e58ca 4742 than stub_group_size and thus can be handled by one stub
07d72278 4743 section. (Or the head section is itself larger than
906e58ca
NC		 4744 stub_group_size, in which case we may be toast.)
4745 We should really be keeping track of the total size of
4746 stubs added here, as stubs contribute to the final output
7fb9f789 4747 section size. */
906e58ca
NC		 4748 do
4749 {
07d72278 4750 next = NEXT_SEC (head);
906e58ca 4751 /* Set up this stub group. */
07d72278 4752 htab->stub_group[head->id].link_sec = curr;
906e58ca 4753 }
07d72278 4754 while (head != curr && (head = next) != NULL);
906e58ca
NC		 4755
4756 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 4757 bytes after the stub section can be handled by it too. */
4758 if (!stubs_always_after_branch)
906e58ca 4759 {
e780aef2
CL		 4760 stub_group_start = curr->output_offset + curr->size;
4761
8cd931b7 4762 while (next != NULL)
906e58ca 4763 {
e780aef2
CL		 4764 end_of_next = next->output_offset + next->size;
4765 if (end_of_next - stub_group_start >= stub_group_size)
4766 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 4767 break;
e780aef2 4768 /* Add NEXT to the stub group. */
07d72278
DJ		 4769 head = next;
4770 next = NEXT_SEC (head);
4771 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 4772 }
4773 }
07d72278 4774 head = next;
906e58ca
NC		 4775 }
4776 }
07d72278 4777 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 4778
4779 free (htab->input_list);
4780#undef PREV_SEC
07d72278 4781#undef NEXT_SEC
906e58ca
NC		 4782}
4783
48229727
JB		 4784/* Comparison function for sorting/searching relocations relating to Cortex-A8
4785 erratum fix. */
4786
4787static int
4788a8_reloc_compare (const void *a, const void *b)
4789{
21d799b5
NC		 4790 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
4791 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 4792
4793 if (ra->from < rb->from)
4794 return -1;
4795 else if (ra->from > rb->from)
4796 return 1;
4797 else
4798 return 0;
4799}
4800
4801static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
4802 const char *, char **);
4803
4804/* Helper function to scan code for sequences which might trigger the Cortex-A8
4805 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 4806 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 4807 otherwise. */
4808
81694485
NC		 4809static bfd_boolean
4810cortex_a8_erratum_scan (bfd *input_bfd,
4811 struct bfd_link_info *info,
48229727
JB		 4812 struct a8_erratum_fix **a8_fixes_p,
4813 unsigned int *num_a8_fixes_p,
4814 unsigned int *a8_fix_table_size_p,
4815 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 4816 unsigned int num_a8_relocs,
4817 unsigned prev_num_a8_fixes,
4818 bfd_boolean *stub_changed_p)
48229727
JB		 4819{
4820 asection *section;
4821 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4822 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
4823 unsigned int num_a8_fixes = *num_a8_fixes_p;
4824 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
4825
4dfe6ac6
NC		 4826 if (htab == NULL)
4827 return FALSE;
4828
48229727
JB		 4829 for (section = input_bfd->sections;
4830 section != NULL;
4831 section = section->next)
4832 {
4833 bfd_byte *contents = NULL;
4834 struct _arm_elf_section_data *sec_data;
4835 unsigned int span;
4836 bfd_vma base_vma;
4837
4838 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 4839 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
4840 || (section->flags & SEC_EXCLUDE) != 0
4841 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
4842 || (section->output_section == bfd_abs_section_ptr))
4843 continue;
48229727
JB		 4844
4845 base_vma = section->output_section->vma + section->output_offset;
4846
4847 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 4848 contents = elf_section_data (section)->this_hdr.contents;
48229727 4849 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 4850 return TRUE;
48229727
JB		 4851
4852 sec_data = elf32_arm_section_data (section);
4853
4854 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 4855 {
4856 unsigned int span_start = sec_data->map[span].vma;
4857 unsigned int span_end = (span == sec_data->mapcount - 1)
4858 ? section->size : sec_data->map[span + 1].vma;
4859 unsigned int i;
4860 char span_type = sec_data->map[span].type;
4861 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
4862
4863 if (span_type != 't')
4864 continue;
4865
4866 /* Span is entirely within a single 4KB region: skip scanning. */
4867 if (((base_vma + span_start) & ~0xfff)
48229727 4868 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 4869 continue;
4870
4871 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
4872
4873 * The opcode is BLX.W, BL.W, B.W, Bcc.W
4874 * The branch target is in the same 4KB region as the
4875 first half of the branch.
4876 * The instruction before the branch is a 32-bit
4877 length non-branch instruction. */
4878 for (i = span_start; i < span_end;)
4879 {
4880 unsigned int insn = bfd_getl16 (&contents[i]);
4881 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 4882 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
4883
99059e56
RM		 4884 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
4885 insn_32bit = TRUE;
48229727
JB		 4886
4887 if (insn_32bit)
99059e56
RM		 4888 {
4889 /* Load the rest of the insn (in manual-friendly order). */
4890 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
4891
4892 /* Encoding T4: B<c>.W. */
4893 is_b = (insn & 0xf800d000) == 0xf0009000;
4894 /* Encoding T1: BL<c>.W. */
4895 is_bl = (insn & 0xf800d000) == 0xf000d000;
4896 /* Encoding T2: BLX<c>.W. */
4897 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 4898 /* Encoding T3: B<c>.W (not permitted in IT block). */
4899 is_bcc = (insn & 0xf800d000) == 0xf0008000
4900 && (insn & 0x07f00000) != 0x03800000;
4901 }
4902
4903 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 4904
99059e56 4905 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 4906 && insn_32bit
4907 && is_32bit_branch
4908 && last_was_32bit
4909 && ! last_was_branch)
99059e56
RM		 4910 {
4911 bfd_signed_vma offset = 0;
4912 bfd_boolean force_target_arm = FALSE;
48229727 4913 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 4914 bfd_vma target;
4915 enum elf32_arm_stub_type stub_type = arm_stub_none;
4916 struct a8_erratum_reloc key, *found;
4917 bfd_boolean use_plt = FALSE;
48229727 4918
99059e56
RM		 4919 key.from = base_vma + i;
4920 found = (struct a8_erratum_reloc *)
4921 bsearch (&key, a8_relocs, num_a8_relocs,
4922 sizeof (struct a8_erratum_reloc),
4923 &a8_reloc_compare);
48229727
JB		 4924
4925 if (found)
4926 {
4927 char *error_message = NULL;
4928 struct elf_link_hash_entry *entry;
4929
4930 /* We don't care about the error returned from this
99059e56 4931 function, only if there is glue or not. */
48229727
JB		 4932 entry = find_thumb_glue (info, found->sym_name,
4933 &error_message);
4934
4935 if (entry)
4936 found->non_a8_stub = TRUE;
4937
92750f34 4938 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 4939 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 4940 && found->hash->root.plt.offset != (bfd_vma) -1)
4941 use_plt = TRUE;
4942
4943 if (found->r_type == R_ARM_THM_CALL)
4944 {
35fc36a8
RS		 4945 if (found->branch_type == ST_BRANCH_TO_ARM
4946 || use_plt)
92750f34
DJ		 4947 force_target_arm = TRUE;
4948 else
4949 force_target_thumb = TRUE;
4950 }
48229727
JB		 4951 }
4952
99059e56 4953 /* Check if we have an offending branch instruction. */
48229727
JB		 4954
4955 if (found && found->non_a8_stub)
4956 /* We've already made a stub for this instruction, e.g.
4957 it's a long branch or a Thumb->ARM stub. Assume that
4958 stub will suffice to work around the A8 erratum (see
4959 setting of always_after_branch above). */
4960 ;
99059e56
RM		 4961 else if (is_bcc)
4962 {
4963 offset = (insn & 0x7ff) << 1;
4964 offset |= (insn & 0x3f0000) >> 4;
4965 offset |= (insn & 0x2000) ? 0x40000 : 0;
4966 offset |= (insn & 0x800) ? 0x80000 : 0;
4967 offset |= (insn & 0x4000000) ? 0x100000 : 0;
4968 if (offset & 0x100000)
4969 offset |= ~ ((bfd_signed_vma) 0xfffff);
4970 stub_type = arm_stub_a8_veneer_b_cond;
4971 }
4972 else if (is_b || is_bl || is_blx)
4973 {
4974 int s = (insn & 0x4000000) != 0;
4975 int j1 = (insn & 0x2000) != 0;
4976 int j2 = (insn & 0x800) != 0;
4977 int i1 = !(j1 ^ s);
4978 int i2 = !(j2 ^ s);
4979
4980 offset = (insn & 0x7ff) << 1;
4981 offset |= (insn & 0x3ff0000) >> 4;
4982 offset |= i2 << 22;
4983 offset |= i1 << 23;
4984 offset |= s << 24;
4985 if (offset & 0x1000000)
4986 offset |= ~ ((bfd_signed_vma) 0xffffff);
4987
4988 if (is_blx)
4989 offset &= ~ ((bfd_signed_vma) 3);
4990
4991 stub_type = is_blx ? arm_stub_a8_veneer_blx :
4992 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
4993 }
4994
4995 if (stub_type != arm_stub_none)
4996 {
4997 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 4998
4999 /* The original instruction is a BL, but the target is
99059e56 5000 an ARM instruction. If we were not making a stub,
48229727
JB		 5001 the BL would have been converted to a BLX. Use the
5002 BLX stub instead in that case. */
5003 if (htab->use_blx && force_target_arm
5004 && stub_type == arm_stub_a8_veneer_bl)
5005 {
5006 stub_type = arm_stub_a8_veneer_blx;
5007 is_blx = TRUE;
5008 is_bl = FALSE;
5009 }
5010 /* Conversely, if the original instruction was
5011 BLX but the target is Thumb mode, use the BL
5012 stub. */
5013 else if (force_target_thumb
5014 && stub_type == arm_stub_a8_veneer_blx)
5015 {
5016 stub_type = arm_stub_a8_veneer_bl;
5017 is_blx = FALSE;
5018 is_bl = TRUE;
5019 }
5020
99059e56
RM		 5021 if (is_blx)
5022 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5023
99059e56
RM		 5024 /* If we found a relocation, use the proper destination,
5025 not the offset in the (unrelocated) instruction.
48229727
JB		 5026 Note this is always done if we switched the stub type
5027 above. */
99059e56
RM		 5028 if (found)
5029 offset =
81694485 5030 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5031
99059e56
RM		 5032 /* If the stub will use a Thumb-mode branch to a
5033 PLT target, redirect it to the preceding Thumb
5034 entry point. */
5035 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5036 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5037
99059e56 5038 target = pc_for_insn + offset;
48229727 5039
99059e56
RM		 5040 /* The BLX stub is ARM-mode code. Adjust the offset to
5041 take the different PC value (+8 instead of +4) into
48229727 5042 account. */
99059e56
RM		 5043 if (stub_type == arm_stub_a8_veneer_blx)
5044 offset += 4;
5045
5046 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5047 {
5048 char *stub_name = NULL;
5049
5050 if (num_a8_fixes == a8_fix_table_size)
5051 {
5052 a8_fix_table_size *= 2;
5053 a8_fixes = (struct a8_erratum_fix *)
5054 bfd_realloc (a8_fixes,
5055 sizeof (struct a8_erratum_fix)
5056 * a8_fix_table_size);
5057 }
48229727 5058
eb7c4339
NS		 5059 if (num_a8_fixes < prev_num_a8_fixes)
5060 {
5061 /* If we're doing a subsequent scan,
5062 check if we've found the same fix as
5063 before, and try and reuse the stub
5064 name. */
5065 stub_name = a8_fixes[num_a8_fixes].stub_name;
5066 if ((a8_fixes[num_a8_fixes].section != section)
5067 || (a8_fixes[num_a8_fixes].offset != i))
5068 {
5069 free (stub_name);
5070 stub_name = NULL;
5071 *stub_changed_p = TRUE;
5072 }
5073 }
5074
5075 if (!stub_name)
5076 {
21d799b5 5077 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5078 if (stub_name != NULL)
5079 sprintf (stub_name, "%x:%x", section->id, i);
5080 }
48229727 5081
99059e56
RM		 5082 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5083 a8_fixes[num_a8_fixes].section = section;
5084 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5085 a8_fixes[num_a8_fixes].target_offset =
5086 target - base_vma;
99059e56
RM		 5087 a8_fixes[num_a8_fixes].orig_insn = insn;
5088 a8_fixes[num_a8_fixes].stub_name = stub_name;
5089 a8_fixes[num_a8_fixes].stub_type = stub_type;
5090 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5091 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5092
99059e56
RM		 5093 num_a8_fixes++;
5094 }
5095 }
5096 }
48229727 5097
99059e56
RM		 5098 i += insn_32bit ? 4 : 2;
5099 last_was_32bit = insn_32bit;
48229727 5100 last_was_branch = is_32bit_branch;
99059e56
RM		 5101 }
5102 }
48229727
JB		 5103
5104 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5105 free (contents);
48229727 5106 }
fe33d2fa 5107
48229727
JB		 5108 *a8_fixes_p = a8_fixes;
5109 *num_a8_fixes_p = num_a8_fixes;
5110 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5111
81694485 5112 return FALSE;
48229727
JB		 5113}
5114
b715f643
TP		 5115/* Create or update a stub entry depending on whether the stub can already be
5116 found in HTAB. The stub is identified by:
5117 - its type STUB_TYPE
5118 - its source branch (note that several can share the same stub) whose
5119 section and relocation (if any) are given by SECTION and IRELA
5120 respectively
5121 - its target symbol whose input section, hash, name, value and branch type
5122 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5123 respectively
5124
5125 If found, the value of the stub's target symbol is updated from SYM_VALUE
5126 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5127 TRUE and the stub entry is initialized.
5128
5129 Returns whether the stub could be successfully created or updated, or FALSE
5130 if an error occured. */
5131
5132static bfd_boolean
5133elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5134 enum elf32_arm_stub_type stub_type, asection *section,
5135 Elf_Internal_Rela *irela, asection *sym_sec,
5136 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5137 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5138 bfd_boolean *new_stub)
5139{
5140 const asection *id_sec;
5141 char *stub_name;
5142 struct elf32_arm_stub_hash_entry *stub_entry;
5143 unsigned int r_type;
5144
5145 BFD_ASSERT (stub_type != arm_stub_none);
5146 *new_stub = FALSE;
5147
5148 BFD_ASSERT (irela);
5149 BFD_ASSERT (section);
5150
5151 /* Support for grouping stub sections. */
5152 id_sec = htab->stub_group[section->id].link_sec;
5153
5154 /* Get the name of this stub. */
5155 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela, stub_type);
5156 if (!stub_name)
5157 return FALSE;
5158
5159 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5160 FALSE);
5161 /* The proper stub has already been created, just update its value. */
5162 if (stub_entry != NULL)
5163 {
5164 free (stub_name);
5165 stub_entry->target_value = sym_value;
5166 return TRUE;
5167 }
5168
5169 stub_entry = elf32_arm_add_stub (stub_name, section, htab);
5170 if (stub_entry == NULL)
5171 {
5172 free (stub_name);
5173 return FALSE;
5174 }
5175
5176 stub_entry->target_value = sym_value;
5177 stub_entry->target_section = sym_sec;
5178 stub_entry->stub_type = stub_type;
5179 stub_entry->h = hash;
5180 stub_entry->branch_type = branch_type;
5181
5182 if (sym_name == NULL)
5183 sym_name = "unnamed";
5184 stub_entry->output_name = (char *)
5185 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5186 + strlen (sym_name));
5187 if (stub_entry->output_name == NULL)
5188 {
5189 free (stub_name);
5190 return FALSE;
5191 }
5192
5193 /* For historical reasons, use the existing names for ARM-to-Thumb and
5194 Thumb-to-ARM stubs. */
5195 r_type = ELF32_R_TYPE (irela->r_info);
5196 if ((r_type == (unsigned int) R_ARM_THM_CALL
5197 || r_type == (unsigned int) R_ARM_THM_JUMP24
5198 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5199 && branch_type == ST_BRANCH_TO_ARM)
5200 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5201 else if ((r_type == (unsigned int) R_ARM_CALL
5202 || r_type == (unsigned int) R_ARM_JUMP24)
5203 && branch_type == ST_BRANCH_TO_THUMB)
5204 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5205 else
5206 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5207
5208 *new_stub = TRUE;
5209 return TRUE;
5210}
5211
906e58ca
NC		 5212/* Determine and set the size of the stub section for a final link.
5213
5214 The basic idea here is to examine all the relocations looking for
5215 PC-relative calls to a target that is unreachable with a "bl"
5216 instruction. */
5217
5218bfd_boolean
5219elf32_arm_size_stubs (bfd *output_bfd,
5220 bfd *stub_bfd,
5221 struct bfd_link_info *info,
5222 bfd_signed_vma group_size,
7a89b94e 5223 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 5224 asection *,
7a89b94e 5225 unsigned int),
906e58ca
NC		 5226 void (*layout_sections_again) (void))
5227{
5228 bfd_size_type stub_group_size;
07d72278 5229 bfd_boolean stubs_always_after_branch;
906e58ca 5230 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 5231 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 5232 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 5233 struct a8_erratum_reloc *a8_relocs = NULL;
5234 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
5235
4dfe6ac6
NC		 5236 if (htab == NULL)
5237 return FALSE;
5238
48229727
JB		 5239 if (htab->fix_cortex_a8)
5240 {
21d799b5 5241 a8_fixes = (struct a8_erratum_fix *)
99059e56 5242 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 5243 a8_relocs = (struct a8_erratum_reloc *)
99059e56 5244 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 5245 }
906e58ca
NC		 5246
5247 /* Propagate mach to stub bfd, because it may not have been
5248 finalized when we created stub_bfd. */
5249 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
5250 bfd_get_mach (output_bfd));
5251
5252 /* Stash our params away. */
5253 htab->stub_bfd = stub_bfd;
5254 htab->add_stub_section = add_stub_section;
5255 htab->layout_sections_again = layout_sections_again;
07d72278 5256 stubs_always_after_branch = group_size < 0;
48229727
JB		 5257
5258 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
5259 as the first half of a 32-bit branch straddling two 4K pages. This is a
5260 crude way of enforcing that. */
5261 if (htab->fix_cortex_a8)
5262 stubs_always_after_branch = 1;
5263
906e58ca
NC		 5264 if (group_size < 0)
5265 stub_group_size = -group_size;
5266 else
5267 stub_group_size = group_size;
5268
5269 if (stub_group_size == 1)
5270 {
5271 /* Default values. */
5272 /* Thumb branch range is +-4MB has to be used as the default
5273 maximum size (a given section can contain both ARM and Thumb
5274 code, so the worst case has to be taken into account).
5275
5276 This value is 24K less than that, which allows for 2025
5277 12-byte stubs. If we exceed that, then we will fail to link.
5278 The user will have to relink with an explicit group size
5279 option. */
5280 stub_group_size = 4170000;
5281 }
5282
07d72278 5283 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 5284
3ae046cc
NS		 5285 /* If we're applying the cortex A8 fix, we need to determine the
5286 program header size now, because we cannot change it later --
5287 that could alter section placements. Notice the A8 erratum fix
5288 ends up requiring the section addresses to remain unchanged
5289 modulo the page size. That's something we cannot represent
5290 inside BFD, and we don't want to force the section alignment to
5291 be the page size. */
5292 if (htab->fix_cortex_a8)
5293 (*htab->layout_sections_again) ();
5294
906e58ca
NC		 5295 while (1)
5296 {
5297 bfd *input_bfd;
5298 unsigned int bfd_indx;
5299 asection *stub_sec;
eb7c4339
NS		 5300 bfd_boolean stub_changed = FALSE;
5301 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 5302
48229727 5303 num_a8_fixes = 0;
906e58ca
NC		 5304 for (input_bfd = info->input_bfds, bfd_indx = 0;
5305 input_bfd != NULL;
c72f2fb2 5306 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 5307 {
5308 Elf_Internal_Shdr *symtab_hdr;
5309 asection *section;
5310 Elf_Internal_Sym *local_syms = NULL;
5311
99059e56
RM		 5312 if (!is_arm_elf (input_bfd))
5313 continue;
adbcc655 5314
48229727
JB		 5315 num_a8_relocs = 0;
5316
906e58ca
NC		 5317 /* We'll need the symbol table in a second. */
5318 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5319 if (symtab_hdr->sh_info == 0)
5320 continue;
5321
5322 /* Walk over each section attached to the input bfd. */
5323 for (section = input_bfd->sections;
5324 section != NULL;
5325 section = section->next)
5326 {
5327 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
5328
5329 /* If there aren't any relocs, then there's nothing more
5330 to do. */
5331 if ((section->flags & SEC_RELOC) == 0
5332 || section->reloc_count == 0
5333 || (section->flags & SEC_CODE) == 0)
5334 continue;
5335
5336 /* If this section is a link-once section that will be
5337 discarded, then don't create any stubs. */
5338 if (section->output_section == NULL
5339 || section->output_section->owner != output_bfd)
5340 continue;
5341
5342 /* Get the relocs. */
5343 internal_relocs
5344 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
5345 NULL, info->keep_memory);
5346 if (internal_relocs == NULL)
5347 goto error_ret_free_local;
5348
5349 /* Now examine each relocation. */
5350 irela = internal_relocs;
5351 irelaend = irela + section->reloc_count;
5352 for (; irela < irelaend; irela++)
5353 {
5354 unsigned int r_type, r_indx;
5355 enum elf32_arm_stub_type stub_type;
906e58ca
NC		 5356 asection *sym_sec;
5357 bfd_vma sym_value;
5358 bfd_vma destination;
5359 struct elf32_arm_link_hash_entry *hash;
7413f23f 5360 const char *sym_name;
34e77a92 5361 unsigned char st_type;
35fc36a8 5362 enum arm_st_branch_type branch_type;
48229727 5363 bfd_boolean created_stub = FALSE;
906e58ca
NC		 5364
5365 r_type = ELF32_R_TYPE (irela->r_info);
5366 r_indx = ELF32_R_SYM (irela->r_info);
5367
5368 if (r_type >= (unsigned int) R_ARM_max)
5369 {
5370 bfd_set_error (bfd_error_bad_value);
5371 error_ret_free_internal:
5372 if (elf_section_data (section)->relocs == NULL)
5373 free (internal_relocs);
15dd01b1
TP		 5374 /* Fall through. */
5375 error_ret_free_local:
5376 if (local_syms != NULL
5377 && (symtab_hdr->contents
5378 != (unsigned char *) local_syms))
5379 free (local_syms);
5380 return FALSE;
906e58ca 5381 }
b38cadfb 5382
0855e32b
NS		 5383 hash = NULL;
5384 if (r_indx >= symtab_hdr->sh_info)
5385 hash = elf32_arm_hash_entry
5386 (elf_sym_hashes (input_bfd)
5387 [r_indx - symtab_hdr->sh_info]);
b38cadfb 5388
0855e32b
NS		 5389 /* Only look for stubs on branch instructions, or
5390 non-relaxed TLSCALL */
906e58ca 5391 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 5392 && (r_type != (unsigned int) R_ARM_THM_CALL)
5393 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 5394 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
5395 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 5396 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 5397 && (r_type != (unsigned int) R_ARM_PLT32)
5398 && !((r_type == (unsigned int) R_ARM_TLS_CALL
5399 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
5400 && r_type == elf32_arm_tls_transition
5401 (info, r_type, &hash->root)
5402 && ((hash ? hash->tls_type
5403 : (elf32_arm_local_got_tls_type
5404 (input_bfd)[r_indx]))
5405 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 5406 continue;
5407
5408 /* Now determine the call target, its name, value,
5409 section. */
5410 sym_sec = NULL;
5411 sym_value = 0;
5412 destination = 0;
7413f23f 5413 sym_name = NULL;
b38cadfb 5414
0855e32b
NS		 5415 if (r_type == (unsigned int) R_ARM_TLS_CALL
5416 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
5417 {
5418 /* A non-relaxed TLS call. The target is the
5419 plt-resident trampoline and nothing to do
5420 with the symbol. */
5421 BFD_ASSERT (htab->tls_trampoline > 0);
5422 sym_sec = htab->root.splt;
5423 sym_value = htab->tls_trampoline;
5424 hash = 0;
34e77a92 5425 st_type = STT_FUNC;
35fc36a8 5426 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 5427 }
5428 else if (!hash)
906e58ca
NC		 5429 {
5430 /* It's a local symbol. */
5431 Elf_Internal_Sym *sym;
906e58ca
NC		 5432
5433 if (local_syms == NULL)
5434 {
5435 local_syms
5436 = (Elf_Internal_Sym *) symtab_hdr->contents;
5437 if (local_syms == NULL)
5438 local_syms
5439 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5440 symtab_hdr->sh_info, 0,
5441 NULL, NULL, NULL);
5442 if (local_syms == NULL)
5443 goto error_ret_free_internal;
5444 }
5445
5446 sym = local_syms + r_indx;
f6d250ce
TS		 5447 if (sym->st_shndx == SHN_UNDEF)
5448 sym_sec = bfd_und_section_ptr;
5449 else if (sym->st_shndx == SHN_ABS)
5450 sym_sec = bfd_abs_section_ptr;
5451 else if (sym->st_shndx == SHN_COMMON)
5452 sym_sec = bfd_com_section_ptr;
5453 else
5454 sym_sec =
5455 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
5456
ffcb4889
NS		 5457 if (!sym_sec)
5458 /* This is an undefined symbol. It can never
6a631e86 5459 be resolved. */
ffcb4889 5460 continue;
fe33d2fa 5461
906e58ca
NC		 5462 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
5463 sym_value = sym->st_value;
5464 destination = (sym_value + irela->r_addend
5465 + sym_sec->output_offset
5466 + sym_sec->output_section->vma);
34e77a92 5467 st_type = ELF_ST_TYPE (sym->st_info);
35fc36a8 5468 branch_type = ARM_SYM_BRANCH_TYPE (sym);
7413f23f
DJ		 5469 sym_name
5470 = bfd_elf_string_from_elf_section (input_bfd,
5471 symtab_hdr->sh_link,
5472 sym->st_name);
906e58ca
NC		 5473 }
5474 else
5475 {
5476 /* It's an external symbol. */
906e58ca
NC		 5477 while (hash->root.root.type == bfd_link_hash_indirect
5478 || hash->root.root.type == bfd_link_hash_warning)
5479 hash = ((struct elf32_arm_link_hash_entry *)
5480 hash->root.root.u.i.link);
5481
5482 if (hash->root.root.type == bfd_link_hash_defined
5483 || hash->root.root.type == bfd_link_hash_defweak)
5484 {
5485 sym_sec = hash->root.root.u.def.section;
5486 sym_value = hash->root.root.u.def.value;
022f8312
CL		 5487
5488 struct elf32_arm_link_hash_table *globals =
5489 elf32_arm_hash_table (info);
5490
5491 /* For a destination in a shared library,
5492 use the PLT stub as target address to
5493 decide whether a branch stub is
5494 needed. */
4dfe6ac6 5495 if (globals != NULL
362d30a1 5496 && globals->root.splt != NULL
4dfe6ac6 5497 && hash != NULL
022f8312
CL		 5498 && hash->root.plt.offset != (bfd_vma) -1)
5499 {
362d30a1 5500 sym_sec = globals->root.splt;
022f8312
CL		 5501 sym_value = hash->root.plt.offset;
5502 if (sym_sec->output_section != NULL)
5503 destination = (sym_value
5504 + sym_sec->output_offset
5505 + sym_sec->output_section->vma);
5506 }
5507 else if (sym_sec->output_section != NULL)
906e58ca
NC		 5508 destination = (sym_value + irela->r_addend
5509 + sym_sec->output_offset
5510 + sym_sec->output_section->vma);
5511 }
69c5861e
CL		 5512 else if ((hash->root.root.type == bfd_link_hash_undefined)
5513 || (hash->root.root.type == bfd_link_hash_undefweak))
5514 {
5515 /* For a shared library, use the PLT stub as
5516 target address to decide whether a long
5517 branch stub is needed.
5518 For absolute code, they cannot be handled. */
5519 struct elf32_arm_link_hash_table *globals =
5520 elf32_arm_hash_table (info);
5521
4dfe6ac6 5522 if (globals != NULL
362d30a1 5523 && globals->root.splt != NULL
4dfe6ac6 5524 && hash != NULL
69c5861e
CL		 5525 && hash->root.plt.offset != (bfd_vma) -1)
5526 {
362d30a1 5527 sym_sec = globals->root.splt;
69c5861e
CL		 5528 sym_value = hash->root.plt.offset;
5529 if (sym_sec->output_section != NULL)
5530 destination = (sym_value
5531 + sym_sec->output_offset
5532 + sym_sec->output_section->vma);
5533 }
5534 else
5535 continue;
5536 }
906e58ca
NC		 5537 else
5538 {
5539 bfd_set_error (bfd_error_bad_value);
5540 goto error_ret_free_internal;
5541 }
34e77a92 5542 st_type = hash->root.type;
35fc36a8 5543 branch_type = hash->root.target_internal;
7413f23f 5544 sym_name = hash->root.root.root.string;
906e58ca
NC		 5545 }
5546
48229727 5547 do
7413f23f 5548 {
b715f643
TP		 5549 bfd_boolean new_stub;
5550
48229727
JB		 5551 /* Determine what (if any) linker stub is needed. */
5552 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 5553 st_type, &branch_type,
5554 hash, destination, sym_sec,
48229727
JB		 5555 input_bfd, sym_name);
5556 if (stub_type == arm_stub_none)
5557 break;
5558
48229727
JB		 5559 /* We've either created a stub for this reloc already,
5560 or we are about to. */
b715f643
TP		 5561 created_stub =
5562 elf32_arm_create_stub (htab, stub_type, section, irela,
5563 sym_sec, hash,
5564 (char *) sym_name, sym_value,
5565 branch_type, &new_stub);
7413f23f 5566
b715f643
TP		 5567 if (!created_stub)
5568 goto error_ret_free_internal;
5569 else if (!new_stub)
5570 break;
99059e56 5571 else
b715f643 5572 stub_changed = TRUE;
99059e56
RM		 5573 }
5574 while (0);
5575
5576 /* Look for relocations which might trigger Cortex-A8
5577 erratum. */
5578 if (htab->fix_cortex_a8
5579 && (r_type == (unsigned int) R_ARM_THM_JUMP24
5580 || r_type == (unsigned int) R_ARM_THM_JUMP19
5581 || r_type == (unsigned int) R_ARM_THM_CALL
5582 || r_type == (unsigned int) R_ARM_THM_XPC22))
5583 {
5584 bfd_vma from = section->output_section->vma
5585 + section->output_offset
5586 + irela->r_offset;
5587
5588 if ((from & 0xfff) == 0xffe)
5589 {
5590 /* Found a candidate. Note we haven't checked the
5591 destination is within 4K here: if we do so (and
5592 don't create an entry in a8_relocs) we can't tell
5593 that a branch should have been relocated when
5594 scanning later. */
5595 if (num_a8_relocs == a8_reloc_table_size)
5596 {
5597 a8_reloc_table_size *= 2;
5598 a8_relocs = (struct a8_erratum_reloc *)
5599 bfd_realloc (a8_relocs,
5600 sizeof (struct a8_erratum_reloc)
5601 * a8_reloc_table_size);
5602 }
5603
5604 a8_relocs[num_a8_relocs].from = from;
5605 a8_relocs[num_a8_relocs].destination = destination;
5606 a8_relocs[num_a8_relocs].r_type = r_type;
5607 a8_relocs[num_a8_relocs].branch_type = branch_type;
5608 a8_relocs[num_a8_relocs].sym_name = sym_name;
5609 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
5610 a8_relocs[num_a8_relocs].hash = hash;
5611
5612 num_a8_relocs++;
5613 }
5614 }
906e58ca
NC		 5615 }
5616
99059e56
RM		 5617 /* We're done with the internal relocs, free them. */
5618 if (elf_section_data (section)->relocs == NULL)
5619 free (internal_relocs);
5620 }
48229727 5621
99059e56 5622 if (htab->fix_cortex_a8)
48229727 5623 {
99059e56
RM		 5624 /* Sort relocs which might apply to Cortex-A8 erratum. */
5625 qsort (a8_relocs, num_a8_relocs,
eb7c4339 5626 sizeof (struct a8_erratum_reloc),
99059e56 5627 &a8_reloc_compare);
48229727 5628
99059e56
RM		 5629 /* Scan for branches which might trigger Cortex-A8 erratum. */
5630 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 5631 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 5632 a8_relocs, num_a8_relocs,
5633 prev_num_a8_fixes, &stub_changed)
5634 != 0)
48229727 5635 goto error_ret_free_local;
5e681ec4 5636 }
5e681ec4
PB		 5637 }
5638
eb7c4339 5639 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 5640 stub_changed = TRUE;
48229727 5641
906e58ca
NC		 5642 if (!stub_changed)
5643 break;
5e681ec4 5644
906e58ca
NC		 5645 /* OK, we've added some stubs. Find out the new size of the
5646 stub sections. */
5647 for (stub_sec = htab->stub_bfd->sections;
5648 stub_sec != NULL;
5649 stub_sec = stub_sec->next)
3e6b1042
DJ		 5650 {
5651 /* Ignore non-stub sections. */
5652 if (!strstr (stub_sec->name, STUB_SUFFIX))
5653 continue;
5654
5655 stub_sec->size = 0;
5656 }
b34b2d70 5657
906e58ca
NC		 5658 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
5659
48229727
JB		 5660 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
5661 if (htab->fix_cortex_a8)
99059e56
RM		 5662 for (i = 0; i < num_a8_fixes; i++)
5663 {
48229727
JB		 5664 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
5665 a8_fixes[i].section, htab);
5666
5667 if (stub_sec == NULL)
5668 goto error_ret_free_local;
5669
99059e56
RM		 5670 stub_sec->size
5671 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
5672 NULL);
5673 }
48229727
JB		 5674
5675
906e58ca
NC		 5676 /* Ask the linker to do its stuff. */
5677 (*htab->layout_sections_again) ();
ba93b8ac
DJ		 5678 }
5679
48229727
JB		 5680 /* Add stubs for Cortex-A8 erratum fixes now. */
5681 if (htab->fix_cortex_a8)
5682 {
5683 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 5684 {
5685 struct elf32_arm_stub_hash_entry *stub_entry;
5686 char *stub_name = a8_fixes[i].stub_name;
5687 asection *section = a8_fixes[i].section;
5688 unsigned int section_id = a8_fixes[i].section->id;
5689 asection *link_sec = htab->stub_group[section_id].link_sec;
5690 asection *stub_sec = htab->stub_group[section_id].stub_sec;
5691 const insn_sequence *template_sequence;
5692 int template_size, size = 0;
5693
5694 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
5695 TRUE, FALSE);
5696 if (stub_entry == NULL)
5697 {
5698 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
5699 section->owner,
5700 stub_name);
5701 return FALSE;
5702 }
5703
5704 stub_entry->stub_sec = stub_sec;
5705 stub_entry->stub_offset = 0;
5706 stub_entry->id_sec = link_sec;
5707 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 5708 stub_entry->source_value = a8_fixes[i].offset;
99059e56 5709 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 5710 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 5711 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 5712 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 5713
99059e56
RM		 5714 size = find_stub_size_and_template (a8_fixes[i].stub_type,
5715 &template_sequence,
5716 &template_size);
48229727 5717
99059e56
RM		 5718 stub_entry->stub_size = size;
5719 stub_entry->stub_template = template_sequence;
5720 stub_entry->stub_template_size = template_size;
5721 }
48229727
JB		 5722
5723 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 5724 elf32_arm_write_section(). */
48229727
JB		 5725 htab->a8_erratum_fixes = a8_fixes;
5726 htab->num_a8_erratum_fixes = num_a8_fixes;
5727 }
5728 else
5729 {
5730 htab->a8_erratum_fixes = NULL;
5731 htab->num_a8_erratum_fixes = 0;
5732 }
906e58ca 5733 return TRUE;
5e681ec4
PB		 5734}
5735
906e58ca
NC		 5736/* Build all the stubs associated with the current output file. The
5737 stubs are kept in a hash table attached to the main linker hash
5738 table. We also set up the .plt entries for statically linked PIC
5739 functions here. This function is called via arm_elf_finish in the
5740 linker. */
252b5132 5741
906e58ca
NC		 5742bfd_boolean
5743elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 5744{
906e58ca
NC		 5745 asection *stub_sec;
5746 struct bfd_hash_table *table;
5747 struct elf32_arm_link_hash_table *htab;
252b5132 5748
906e58ca 5749 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 5750 if (htab == NULL)
5751 return FALSE;
252b5132 5752
906e58ca
NC		 5753 for (stub_sec = htab->stub_bfd->sections;
5754 stub_sec != NULL;
5755 stub_sec = stub_sec->next)
252b5132 5756 {
906e58ca
NC		 5757 bfd_size_type size;
5758
8029a119 5759 /* Ignore non-stub sections. */
906e58ca
NC		 5760 if (!strstr (stub_sec->name, STUB_SUFFIX))
5761 continue;
5762
5763 /* Allocate memory to hold the linker stubs. */
5764 size = stub_sec->size;
21d799b5 5765 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 5766 if (stub_sec->contents == NULL && size != 0)
5767 return FALSE;
5768 stub_sec->size = 0;
252b5132
RH		 5769 }
5770
906e58ca
NC		 5771 /* Build the stubs as directed by the stub hash table. */
5772 table = &htab->stub_hash_table;
5773 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 5774 if (htab->fix_cortex_a8)
5775 {
5776 /* Place the cortex a8 stubs last. */
5777 htab->fix_cortex_a8 = -1;
5778 bfd_hash_traverse (table, arm_build_one_stub, info);
5779 }
252b5132 5780
906e58ca 5781 return TRUE;
252b5132
RH		 5782}
5783
9b485d32
NC		 5784/* Locate the Thumb encoded calling stub for NAME. */
5785
252b5132 5786static struct elf_link_hash_entry *
57e8b36a
NC		 5787find_thumb_glue (struct bfd_link_info *link_info,
5788 const char *name,
f2a9dd69 5789 char **error_message)
252b5132
RH		 5790{
5791 char *tmp_name;
5792 struct elf_link_hash_entry *hash;
5793 struct elf32_arm_link_hash_table *hash_table;
5794
5795 /* We need a pointer to the armelf specific hash table. */
5796 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 5797 if (hash_table == NULL)
5798 return NULL;
252b5132 5799
21d799b5 5800 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 5801 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 5802
5803 BFD_ASSERT (tmp_name);
5804
5805 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
5806
5807 hash = elf_link_hash_lookup
b34976b6 5808 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 5809
b1657152
AM		 5810 if (hash == NULL
5811 && asprintf (error_message, _("unable to find THUMB glue '%s' for '%s'"),
5812 tmp_name, name) == -1)
5813 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 5814
5815 free (tmp_name);
5816
5817 return hash;
5818}
5819
9b485d32
NC		 5820/* Locate the ARM encoded calling stub for NAME. */
5821
252b5132 5822static struct elf_link_hash_entry *
57e8b36a
NC		 5823find_arm_glue (struct bfd_link_info *link_info,
5824 const char *name,
f2a9dd69 5825 char **error_message)
252b5132
RH		 5826{
5827 char *tmp_name;
5828 struct elf_link_hash_entry *myh;
5829 struct elf32_arm_link_hash_table *hash_table;
5830
5831 /* We need a pointer to the elfarm specific hash table. */
5832 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 5833 if (hash_table == NULL)
5834 return NULL;
252b5132 5835
21d799b5 5836 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 5837 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 5838
5839 BFD_ASSERT (tmp_name);
5840
5841 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
5842
5843 myh = elf_link_hash_lookup
b34976b6 5844 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 5845
b1657152
AM		 5846 if (myh == NULL
5847 && asprintf (error_message, _("unable to find ARM glue '%s' for '%s'"),
5848 tmp_name, name) == -1)
5849 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 5850
5851 free (tmp_name);
5852
5853 return myh;
5854}
5855
8f6277f5 5856/* ARM->Thumb glue (static images):
252b5132
RH		 5857
5858 .arm
5859 __func_from_arm:
5860 ldr r12, __func_addr
5861 bx r12
5862 __func_addr:
906e58ca 5863 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 5864
26079076
PB		 5865 (v5t static images)
5866 .arm
5867 __func_from_arm:
5868 ldr pc, __func_addr
5869 __func_addr:
906e58ca 5870 .word func @ behave as if you saw a ARM_32 reloc.
26079076 5871
8f6277f5
PB		 5872 (relocatable images)
5873 .arm
5874 __func_from_arm:
5875 ldr r12, __func_offset
5876 add r12, r12, pc
5877 bx r12
5878 __func_offset:
8029a119 5879 .word func - . */
8f6277f5
PB		 5880
5881#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 5882static const insn32 a2t1_ldr_insn = 0xe59fc000;
5883static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
5884static const insn32 a2t3_func_addr_insn = 0x00000001;
5885
26079076
PB		 5886#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
5887static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
5888static const insn32 a2t2v5_func_addr_insn = 0x00000001;
5889
8f6277f5
PB		 5890#define ARM2THUMB_PIC_GLUE_SIZE 16
5891static const insn32 a2t1p_ldr_insn = 0xe59fc004;
5892static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
5893static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
5894
9b485d32 5895/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 5896
8029a119
NC		 5897 .thumb .thumb
5898 .align 2 .align 2
5899 __func_from_thumb: __func_from_thumb:
5900 bx pc push {r6, lr}
5901 nop ldr r6, __func_addr
5902 .arm mov lr, pc
5903 b func bx r6
99059e56
RM		 5904 .arm
5905 ;; back_to_thumb
5906 ldmia r13! {r6, lr}
5907 bx lr
5908 __func_addr:
5909 .word func */
252b5132
RH		 5910
5911#define THUMB2ARM_GLUE_SIZE 8
5912static const insn16 t2a1_bx_pc_insn = 0x4778;
5913static const insn16 t2a2_noop_insn = 0x46c0;
5914static const insn32 t2a3_b_insn = 0xea000000;
5915
c7b8f16e 5916#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 5917#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
5918#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 5919
845b51d6
PB		 5920#define ARM_BX_VENEER_SIZE 12
5921static const insn32 armbx1_tst_insn = 0xe3100001;
5922static const insn32 armbx2_moveq_insn = 0x01a0f000;
5923static const insn32 armbx3_bx_insn = 0xe12fff10;
5924
7e392df6 5925#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 5926static void
5927arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 5928{
5929 asection * s;
8029a119 5930 bfd_byte * contents;
252b5132 5931
8029a119 5932 if (size == 0)
3e6b1042
DJ		 5933 {
5934 /* Do not include empty glue sections in the output. */
5935 if (abfd != NULL)
5936 {
3d4d4302 5937 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 5938 if (s != NULL)
5939 s->flags |= SEC_EXCLUDE;
5940 }
5941 return;
5942 }
252b5132 5943
8029a119 5944 BFD_ASSERT (abfd != NULL);
252b5132 5945
3d4d4302 5946 s = bfd_get_linker_section (abfd, name);
8029a119 5947 BFD_ASSERT (s != NULL);
252b5132 5948
21d799b5 5949 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 5950
8029a119
NC		 5951 BFD_ASSERT (s->size == size);
5952 s->contents = contents;
5953}
906e58ca 5954
8029a119
NC		 5955bfd_boolean
5956bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
5957{
5958 struct elf32_arm_link_hash_table * globals;
906e58ca 5959
8029a119
NC		 5960 globals = elf32_arm_hash_table (info);
5961 BFD_ASSERT (globals != NULL);
906e58ca 5962
8029a119
NC		 5963 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5964 globals->arm_glue_size,
5965 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 5966
8029a119
NC		 5967 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5968 globals->thumb_glue_size,
5969 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 5970
8029a119
NC		 5971 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5972 globals->vfp11_erratum_glue_size,
5973 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 5974
a504d23a
LA		 5975 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5976 globals->stm32l4xx_erratum_glue_size,
5977 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
5978
8029a119
NC		 5979 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5980 globals->bx_glue_size,
845b51d6
PB		 5981 ARM_BX_GLUE_SECTION_NAME);
5982
b34976b6 5983 return TRUE;
252b5132
RH		 5984}
5985
a4fd1a8e 5986/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 5987 returns the symbol identifying the stub. */
5988
a4fd1a8e 5989static struct elf_link_hash_entry *
57e8b36a
NC		 5990record_arm_to_thumb_glue (struct bfd_link_info * link_info,
5991 struct elf_link_hash_entry * h)
252b5132
RH		 5992{
5993 const char * name = h->root.root.string;
63b0f745 5994 asection * s;
252b5132
RH		 5995 char * tmp_name;
5996 struct elf_link_hash_entry * myh;
14a793b2 5997 struct bfd_link_hash_entry * bh;
252b5132 5998 struct elf32_arm_link_hash_table * globals;
dc810e39 5999 bfd_vma val;
2f475487 6000 bfd_size_type size;
252b5132
RH		 6001
6002 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 6003 BFD_ASSERT (globals != NULL);
6004 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6005
3d4d4302 6006 s = bfd_get_linker_section
252b5132
RH		 6007 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
6008
252b5132
RH		 6009 BFD_ASSERT (s != NULL);
6010
21d799b5 6011 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6012 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6013
6014 BFD_ASSERT (tmp_name);
6015
6016 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6017
6018 myh = elf_link_hash_lookup
b34976b6 6019 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 6020
6021 if (myh != NULL)
6022 {
9b485d32 6023 /* We've already seen this guy. */
252b5132 6024 free (tmp_name);
a4fd1a8e 6025 return myh;
252b5132
RH		 6026 }
6027
57e8b36a
NC		 6028 /* The only trick here is using hash_table->arm_glue_size as the value.
6029 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 6030 putting it. The +1 on the value marks that the stub has not been
6031 output yet - not that it is a Thumb function. */
14a793b2 6032 bh = NULL;
dc810e39
AM		 6033 val = globals->arm_glue_size + 1;
6034 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
6035 tmp_name, BSF_GLOBAL, s, val,
b34976b6 6036 NULL, TRUE, FALSE, &bh);
252b5132 6037
b7693d02
DJ		 6038 myh = (struct elf_link_hash_entry *) bh;
6039 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6040 myh->forced_local = 1;
6041
252b5132
RH		 6042 free (tmp_name);
6043
0e1862bb
L		 6044 if (bfd_link_pic (link_info)
6045 || globals->root.is_relocatable_executable
27e55c4d 6046 || globals->pic_veneer)
2f475487 6047 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 6048 else if (globals->use_blx)
6049 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 6050 else
2f475487
AM		 6051 size = ARM2THUMB_STATIC_GLUE_SIZE;
6052
6053 s->size += size;
6054 globals->arm_glue_size += size;
252b5132 6055
a4fd1a8e 6056 return myh;
252b5132
RH		 6057}
6058
845b51d6
PB		 6059/* Allocate space for ARMv4 BX veneers. */
6060
6061static void
6062record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
6063{
6064 asection * s;
6065 struct elf32_arm_link_hash_table *globals;
6066 char *tmp_name;
6067 struct elf_link_hash_entry *myh;
6068 struct bfd_link_hash_entry *bh;
6069 bfd_vma val;
6070
6071 /* BX PC does not need a veneer. */
6072 if (reg == 15)
6073 return;
6074
6075 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 6076 BFD_ASSERT (globals != NULL);
6077 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6078
6079 /* Check if this veneer has already been allocated. */
6080 if (globals->bx_glue_offset[reg])
6081 return;
6082
3d4d4302 6083 s = bfd_get_linker_section
845b51d6
PB		 6084 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
6085
6086 BFD_ASSERT (s != NULL);
6087
6088 /* Add symbol for veneer. */
21d799b5
NC		 6089 tmp_name = (char *)
6090 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 6091
845b51d6 6092 BFD_ASSERT (tmp_name);
906e58ca 6093
845b51d6 6094 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 6095
845b51d6
PB		 6096 myh = elf_link_hash_lookup
6097 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6098
845b51d6 6099 BFD_ASSERT (myh == NULL);
906e58ca 6100
845b51d6
PB		 6101 bh = NULL;
6102 val = globals->bx_glue_size;
6103 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 6104 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6105 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 6106
6107 myh = (struct elf_link_hash_entry *) bh;
6108 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6109 myh->forced_local = 1;
6110
6111 s->size += ARM_BX_VENEER_SIZE;
6112 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
6113 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
6114}
6115
6116
c7b8f16e
JB		 6117/* Add an entry to the code/data map for section SEC. */
6118
6119static void
6120elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
6121{
6122 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
6123 unsigned int newidx;
906e58ca 6124
c7b8f16e
JB		 6125 if (sec_data->map == NULL)
6126 {
21d799b5 6127 sec_data->map = (elf32_arm_section_map *)
99059e56 6128 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 6129 sec_data->mapcount = 0;
6130 sec_data->mapsize = 1;
6131 }
906e58ca 6132
c7b8f16e 6133 newidx = sec_data->mapcount++;
906e58ca 6134
c7b8f16e
JB		 6135 if (sec_data->mapcount > sec_data->mapsize)
6136 {
6137 sec_data->mapsize *= 2;
21d799b5 6138 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 6139 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
6140 * sizeof (elf32_arm_section_map));
515ef31d
NC		 6141 }
6142
6143 if (sec_data->map)
6144 {
6145 sec_data->map[newidx].vma = vma;
6146 sec_data->map[newidx].type = type;
c7b8f16e 6147 }
c7b8f16e
JB		 6148}
6149
6150
6151/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
6152 veneers are handled for now. */
6153
6154static bfd_vma
6155record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 6156 elf32_vfp11_erratum_list *branch,
6157 bfd *branch_bfd,
6158 asection *branch_sec,
6159 unsigned int offset)
c7b8f16e
JB		 6160{
6161 asection *s;
6162 struct elf32_arm_link_hash_table *hash_table;
6163 char *tmp_name;
6164 struct elf_link_hash_entry *myh;
6165 struct bfd_link_hash_entry *bh;
6166 bfd_vma val;
6167 struct _arm_elf_section_data *sec_data;
c7b8f16e 6168 elf32_vfp11_erratum_list *newerr;
906e58ca 6169
c7b8f16e 6170 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 6171 BFD_ASSERT (hash_table != NULL);
6172 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 6173
3d4d4302 6174 s = bfd_get_linker_section
c7b8f16e 6175 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 6176
c7b8f16e 6177 sec_data = elf32_arm_section_data (s);
906e58ca 6178
c7b8f16e 6179 BFD_ASSERT (s != NULL);
906e58ca 6180
21d799b5 6181 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 6182 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 6183
c7b8f16e 6184 BFD_ASSERT (tmp_name);
906e58ca 6185
c7b8f16e
JB		 6186 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
6187 hash_table->num_vfp11_fixes);
906e58ca 6188
c7b8f16e
JB		 6189 myh = elf_link_hash_lookup
6190 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6191
c7b8f16e 6192 BFD_ASSERT (myh == NULL);
906e58ca 6193
c7b8f16e
JB		 6194 bh = NULL;
6195 val = hash_table->vfp11_erratum_glue_size;
6196 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 6197 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6198 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 6199
6200 myh = (struct elf_link_hash_entry *) bh;
6201 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6202 myh->forced_local = 1;
6203
6204 /* Link veneer back to calling location. */
c7e2358a 6205 sec_data->erratumcount += 1;
21d799b5
NC		 6206 newerr = (elf32_vfp11_erratum_list *)
6207 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 6208
c7b8f16e
JB		 6209 newerr->type = VFP11_ERRATUM_ARM_VENEER;
6210 newerr->vma = -1;
6211 newerr->u.v.branch = branch;
6212 newerr->u.v.id = hash_table->num_vfp11_fixes;
6213 branch->u.b.veneer = newerr;
6214
6215 newerr->next = sec_data->erratumlist;
6216 sec_data->erratumlist = newerr;
6217
6218 /* A symbol for the return from the veneer. */
6219 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
6220 hash_table->num_vfp11_fixes);
6221
6222 myh = elf_link_hash_lookup
6223 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6224
c7b8f16e
JB		 6225 if (myh != NULL)
6226 abort ();
6227
6228 bh = NULL;
6229 val = offset + 4;
6230 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
6231 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 6232
c7b8f16e
JB		 6233 myh = (struct elf_link_hash_entry *) bh;
6234 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6235 myh->forced_local = 1;
6236
6237 free (tmp_name);
906e58ca 6238
c7b8f16e
JB		 6239 /* Generate a mapping symbol for the veneer section, and explicitly add an
6240 entry for that symbol to the code/data map for the section. */
6241 if (hash_table->vfp11_erratum_glue_size == 0)
6242 {
6243 bh = NULL;
6244 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 6245 ever requires this erratum fix. */
c7b8f16e
JB		 6246 _bfd_generic_link_add_one_symbol (link_info,
6247 hash_table->bfd_of_glue_owner, "$a",
6248 BSF_LOCAL, s, 0, NULL,
99059e56 6249 TRUE, FALSE, &bh);
c7b8f16e
JB		 6250
6251 myh = (struct elf_link_hash_entry *) bh;
6252 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
6253 myh->forced_local = 1;
906e58ca 6254
c7b8f16e 6255 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 6256 BFDs. We must make a note of this generated mapping symbol
6257 ourselves so that code byteswapping works properly in
6258 elf32_arm_write_section. */
c7b8f16e
JB		 6259 elf32_arm_section_map_add (s, 'a', 0);
6260 }
906e58ca 6261
c7b8f16e
JB		 6262 s->size += VFP11_ERRATUM_VENEER_SIZE;
6263 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
6264 hash_table->num_vfp11_fixes++;
906e58ca 6265
c7b8f16e
JB		 6266 /* The offset of the veneer. */
6267 return val;
6268}
6269
a504d23a
LA		 6270/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
6271 veneers need to be handled because used only in Cortex-M. */
6272
6273static bfd_vma
6274record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
6275 elf32_stm32l4xx_erratum_list *branch,
6276 bfd *branch_bfd,
6277 asection *branch_sec,
6278 unsigned int offset,
6279 bfd_size_type veneer_size)
6280{
6281 asection *s;
6282 struct elf32_arm_link_hash_table *hash_table;
6283 char *tmp_name;
6284 struct elf_link_hash_entry *myh;
6285 struct bfd_link_hash_entry *bh;
6286 bfd_vma val;
6287 struct _arm_elf_section_data *sec_data;
6288 elf32_stm32l4xx_erratum_list *newerr;
6289
6290 hash_table = elf32_arm_hash_table (link_info);
6291 BFD_ASSERT (hash_table != NULL);
6292 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
6293
6294 s = bfd_get_linker_section
6295 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6296
6297 BFD_ASSERT (s != NULL);
6298
6299 sec_data = elf32_arm_section_data (s);
6300
6301 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
6302 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
6303
6304 BFD_ASSERT (tmp_name);
6305
6306 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
6307 hash_table->num_stm32l4xx_fixes);
6308
6309 myh = elf_link_hash_lookup
6310 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
6311
6312 BFD_ASSERT (myh == NULL);
6313
6314 bh = NULL;
6315 val = hash_table->stm32l4xx_erratum_glue_size;
6316 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
6317 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6318 NULL, TRUE, FALSE, &bh);
6319
6320 myh = (struct elf_link_hash_entry *) bh;
6321 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6322 myh->forced_local = 1;
6323
6324 /* Link veneer back to calling location. */
6325 sec_data->stm32l4xx_erratumcount += 1;
6326 newerr = (elf32_stm32l4xx_erratum_list *)
6327 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
6328
6329 newerr->type = STM32L4XX_ERRATUM_VENEER;
6330 newerr->vma = -1;
6331 newerr->u.v.branch = branch;
6332 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
6333 branch->u.b.veneer = newerr;
6334
6335 newerr->next = sec_data->stm32l4xx_erratumlist;
6336 sec_data->stm32l4xx_erratumlist = newerr;
6337
6338 /* A symbol for the return from the veneer. */
6339 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
6340 hash_table->num_stm32l4xx_fixes);
6341
6342 myh = elf_link_hash_lookup
6343 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
6344
6345 if (myh != NULL)
6346 abort ();
6347
6348 bh = NULL;
6349 val = offset + 4;
6350 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
6351 branch_sec, val, NULL, TRUE, FALSE, &bh);
6352
6353 myh = (struct elf_link_hash_entry *) bh;
6354 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6355 myh->forced_local = 1;
6356
6357 free (tmp_name);
6358
6359 /* Generate a mapping symbol for the veneer section, and explicitly add an
6360 entry for that symbol to the code/data map for the section. */
6361 if (hash_table->stm32l4xx_erratum_glue_size == 0)
6362 {
6363 bh = NULL;
6364 /* Creates a THUMB symbol since there is no other choice. */
6365 _bfd_generic_link_add_one_symbol (link_info,
6366 hash_table->bfd_of_glue_owner, "$t",
6367 BSF_LOCAL, s, 0, NULL,
6368 TRUE, FALSE, &bh);
6369
6370 myh = (struct elf_link_hash_entry *) bh;
6371 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
6372 myh->forced_local = 1;
6373
6374 /* The elf32_arm_init_maps function only cares about symbols from input
6375 BFDs. We must make a note of this generated mapping symbol
6376 ourselves so that code byteswapping works properly in
6377 elf32_arm_write_section. */
6378 elf32_arm_section_map_add (s, 't', 0);
6379 }
6380
6381 s->size += veneer_size;
6382 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
6383 hash_table->num_stm32l4xx_fixes++;
6384
6385 /* The offset of the veneer. */
6386 return val;
6387}
6388
8029a119 6389#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 6390 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
6391 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 6392
6393/* Create a fake section for use by the ARM backend of the linker. */
6394
6395static bfd_boolean
6396arm_make_glue_section (bfd * abfd, const char * name)
6397{
6398 asection * sec;
6399
3d4d4302 6400 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 6401 if (sec != NULL)
6402 /* Already made. */
6403 return TRUE;
6404
3d4d4302 6405 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 6406
6407 if (sec == NULL
6408 || !bfd_set_section_alignment (abfd, sec, 2))
6409 return FALSE;
6410
6411 /* Set the gc mark to prevent the section from being removed by garbage
6412 collection, despite the fact that no relocs refer to this section. */
6413 sec->gc_mark = 1;
6414
6415 return TRUE;
6416}
6417
1db37fe6
YG		 6418/* Set size of .plt entries. This function is called from the
6419 linker scripts in ld/emultempl/{armelf}.em. */
6420
6421void
6422bfd_elf32_arm_use_long_plt (void)
6423{
6424 elf32_arm_use_long_plt_entry = TRUE;
6425}
6426
8afb0e02
NC		 6427/* Add the glue sections to ABFD. This function is called from the
6428 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 6429
b34976b6 6430bfd_boolean
57e8b36a
NC		 6431bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
6432 struct bfd_link_info *info)
252b5132 6433{
a504d23a
LA		 6434 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
6435 bfd_boolean dostm32l4xx = globals
6436 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
6437 bfd_boolean addglue;
6438
8afb0e02
NC		 6439 /* If we are only performing a partial
6440 link do not bother adding the glue. */
0e1862bb 6441 if (bfd_link_relocatable (info))
b34976b6 6442 return TRUE;
252b5132 6443
a504d23a 6444 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 6445 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
6446 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
6447 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 6448
6449 if (!dostm32l4xx)
6450 return addglue;
6451
6452 return addglue
6453 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 6454}
6455
6456/* Select a BFD to be used to hold the sections used by the glue code.
6457 This function is called from the linker scripts in ld/emultempl/
8029a119 6458 {armelf/pe}.em. */
8afb0e02 6459
b34976b6 6460bfd_boolean
57e8b36a 6461bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 6462{
6463 struct elf32_arm_link_hash_table *globals;
6464
6465 /* If we are only performing a partial link
6466 do not bother getting a bfd to hold the glue. */
0e1862bb 6467 if (bfd_link_relocatable (info))
b34976b6 6468 return TRUE;
8afb0e02 6469
b7693d02
DJ		 6470 /* Make sure we don't attach the glue sections to a dynamic object. */
6471 BFD_ASSERT (!(abfd->flags & DYNAMIC));
6472
8afb0e02 6473 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 6474 BFD_ASSERT (globals != NULL);
6475
6476 if (globals->bfd_of_glue_owner != NULL)
b34976b6 6477 return TRUE;
8afb0e02 6478
252b5132
RH		 6479 /* Save the bfd for later use. */
6480 globals->bfd_of_glue_owner = abfd;
cedb70c5 6481
b34976b6 6482 return TRUE;
252b5132
RH		 6483}
6484
906e58ca
NC		 6485static void
6486check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 6487{
2de70689
MGD		 6488 int cpu_arch;
6489
b38cadfb 6490 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 6491 Tag_CPU_arch);
6492
6493 if (globals->fix_arm1176)
6494 {
6495 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
6496 globals->use_blx = 1;
6497 }
6498 else
6499 {
6500 if (cpu_arch > TAG_CPU_ARCH_V4T)
6501 globals->use_blx = 1;
6502 }
39b41c9c
PB		 6503}
6504
b34976b6 6505bfd_boolean
57e8b36a 6506bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 6507 struct bfd_link_info *link_info)
252b5132
RH		 6508{
6509 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 6510 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 6511 Elf_Internal_Rela *irel, *irelend;
6512 bfd_byte *contents = NULL;
252b5132
RH		 6513
6514 asection *sec;
6515 struct elf32_arm_link_hash_table *globals;
6516
6517 /* If we are only performing a partial link do not bother
6518 to construct any glue. */
0e1862bb 6519 if (bfd_link_relocatable (link_info))
b34976b6 6520 return TRUE;
252b5132 6521
39ce1a6a
NC		 6522 /* Here we have a bfd that is to be included on the link. We have a
6523 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 6524 globals = elf32_arm_hash_table (link_info);
252b5132 6525 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 6526
6527 check_use_blx (globals);
252b5132 6528
d504ffc8 6529 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 6530 {
d003868e
AM		 6531 _bfd_error_handler (_("%B: BE8 images only valid in big-endian mode."),
6532 abfd);
e489d0ae
PB		 6533 return FALSE;
6534 }
f21f3fe0 6535
39ce1a6a
NC		 6536 /* PR 5398: If we have not decided to include any loadable sections in
6537 the output then we will not have a glue owner bfd. This is OK, it
6538 just means that there is nothing else for us to do here. */
6539 if (globals->bfd_of_glue_owner == NULL)
6540 return TRUE;
6541
252b5132
RH		 6542 /* Rummage around all the relocs and map the glue vectors. */
6543 sec = abfd->sections;
6544
6545 if (sec == NULL)
b34976b6 6546 return TRUE;
252b5132
RH		 6547
6548 for (; sec != NULL; sec = sec->next)
6549 {
6550 if (sec->reloc_count == 0)
6551 continue;
6552
2f475487
AM		 6553 if ((sec->flags & SEC_EXCLUDE) != 0)
6554 continue;
6555
0ffa91dd 6556 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 6557
9b485d32 6558 /* Load the relocs. */
6cdc0ccc 6559 internal_relocs
906e58ca 6560 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 6561
6cdc0ccc
AM		 6562 if (internal_relocs == NULL)
6563 goto error_return;
252b5132 6564
6cdc0ccc
AM		 6565 irelend = internal_relocs + sec->reloc_count;
6566 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 6567 {
6568 long r_type;
6569 unsigned long r_index;
252b5132
RH		 6570
6571 struct elf_link_hash_entry *h;
6572
6573 r_type = ELF32_R_TYPE (irel->r_info);
6574 r_index = ELF32_R_SYM (irel->r_info);
6575
9b485d32 6576 /* These are the only relocation types we care about. */
ba96a88f 6577 if ( r_type != R_ARM_PC24
845b51d6 6578 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 6579 continue;
6580
6581 /* Get the section contents if we haven't done so already. */
6582 if (contents == NULL)
6583 {
6584 /* Get cached copy if it exists. */
6585 if (elf_section_data (sec)->this_hdr.contents != NULL)
6586 contents = elf_section_data (sec)->this_hdr.contents;
6587 else
6588 {
6589 /* Go get them off disk. */
57e8b36a 6590 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 6591 goto error_return;
6592 }
6593 }
6594
845b51d6
PB		 6595 if (r_type == R_ARM_V4BX)
6596 {
6597 int reg;
6598
6599 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
6600 record_arm_bx_glue (link_info, reg);
6601 continue;
6602 }
6603
a7c10850 6604 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 6605 h = NULL;
6606
9b485d32 6607 /* We don't care about local symbols. */
252b5132
RH		 6608 if (r_index < symtab_hdr->sh_info)
6609 continue;
6610
9b485d32 6611 /* This is an external symbol. */
252b5132
RH		 6612 r_index -= symtab_hdr->sh_info;
6613 h = (struct elf_link_hash_entry *)
6614 elf_sym_hashes (abfd)[r_index];
6615
6616 /* If the relocation is against a static symbol it must be within
6617 the current section and so cannot be a cross ARM/Thumb relocation. */
6618 if (h == NULL)
6619 continue;
6620
d504ffc8
DJ		 6621 /* If the call will go through a PLT entry then we do not need
6622 glue. */
362d30a1 6623 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 6624 continue;
6625
252b5132
RH		 6626 switch (r_type)
6627 {
6628 case R_ARM_PC24:
6629 /* This one is a call from arm code. We need to look up
99059e56
RM		 6630 the target of the call. If it is a thumb target, we
6631 insert glue. */
35fc36a8 6632 if (h->target_internal == ST_BRANCH_TO_THUMB)
252b5132
RH		 6633 record_arm_to_thumb_glue (link_info, h);
6634 break;
6635
252b5132 6636 default:
c6596c5e 6637 abort ();
252b5132
RH		 6638 }
6639 }
6cdc0ccc
AM		 6640
6641 if (contents != NULL
6642 && elf_section_data (sec)->this_hdr.contents != contents)
6643 free (contents);
6644 contents = NULL;
6645
6646 if (internal_relocs != NULL
6647 && elf_section_data (sec)->relocs != internal_relocs)
6648 free (internal_relocs);
6649 internal_relocs = NULL;
252b5132
RH		 6650 }
6651
b34976b6 6652 return TRUE;
9a5aca8c 6653
252b5132 6654error_return:
6cdc0ccc
AM		 6655 if (contents != NULL
6656 && elf_section_data (sec)->this_hdr.contents != contents)
6657 free (contents);
6658 if (internal_relocs != NULL
6659 && elf_section_data (sec)->relocs != internal_relocs)
6660 free (internal_relocs);
9a5aca8c 6661
b34976b6 6662 return FALSE;
252b5132 6663}
7e392df6 6664#endif
252b5132 6665
eb043451 6666
c7b8f16e
JB		 6667/* Initialise maps of ARM/Thumb/data for input BFDs. */
6668
6669void
6670bfd_elf32_arm_init_maps (bfd *abfd)
6671{
6672 Elf_Internal_Sym *isymbuf;
6673 Elf_Internal_Shdr *hdr;
6674 unsigned int i, localsyms;
6675
af1f4419
NC		 6676 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
6677 if (! is_arm_elf (abfd))
6678 return;
6679
c7b8f16e
JB		 6680 if ((abfd->flags & DYNAMIC) != 0)
6681 return;
6682
0ffa91dd 6683 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 6684 localsyms = hdr->sh_info;
6685
6686 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
6687 should contain the number of local symbols, which should come before any
6688 global symbols. Mapping symbols are always local. */
6689 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
6690 NULL);
6691
6692 /* No internal symbols read? Skip this BFD. */
6693 if (isymbuf == NULL)
6694 return;
6695
6696 for (i = 0; i < localsyms; i++)
6697 {
6698 Elf_Internal_Sym *isym = &isymbuf[i];
6699 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
6700 const char *name;
906e58ca 6701
c7b8f16e 6702 if (sec != NULL
99059e56
RM		 6703 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
6704 {
6705 name = bfd_elf_string_from_elf_section (abfd,
6706 hdr->sh_link, isym->st_name);
906e58ca 6707
99059e56 6708 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 6709 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 6710 elf32_arm_section_map_add (sec, name[1], isym->st_value);
6711 }
c7b8f16e
JB		 6712 }
6713}
6714
6715
48229727
JB		 6716/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
6717 say what they wanted. */
6718
6719void
6720bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
6721{
6722 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
6723 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
6724
4dfe6ac6
NC		 6725 if (globals == NULL)
6726 return;
6727
48229727
JB		 6728 if (globals->fix_cortex_a8 == -1)
6729 {
6730 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
6731 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
6732 && (out_attr[Tag_CPU_arch_profile].i == 'A'
6733 || out_attr[Tag_CPU_arch_profile].i == 0))
6734 globals->fix_cortex_a8 = 1;
6735 else
6736 globals->fix_cortex_a8 = 0;
6737 }
6738}
6739
6740
c7b8f16e
JB		 6741void
6742bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
6743{
6744 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 6745 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 6746
4dfe6ac6
NC		 6747 if (globals == NULL)
6748 return;
c7b8f16e
JB		 6749 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
6750 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
6751 {
6752 switch (globals->vfp11_fix)
99059e56
RM		 6753 {
6754 case BFD_ARM_VFP11_FIX_DEFAULT:
6755 case BFD_ARM_VFP11_FIX_NONE:
6756 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
6757 break;
6758
6759 default:
6760 /* Give a warning, but do as the user requests anyway. */
6761 (*_bfd_error_handler) (_("%B: warning: selected VFP11 erratum "
6762 "workaround is not necessary for target architecture"), obfd);
6763 }
c7b8f16e
JB		 6764 }
6765 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
6766 /* For earlier architectures, we might need the workaround, but do not
6767 enable it by default. If users is running with broken hardware, they
6768 must enable the erratum fix explicitly. */
6769 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
6770}
6771
a504d23a
LA		 6772void
6773bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
6774{
6775 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
6776 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
6777
6778 if (globals == NULL)
6779 return;
6780
6781 /* We assume only Cortex-M4 may require the fix. */
6782 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
6783 || out_attr[Tag_CPU_arch_profile].i != 'M')
6784 {
6785 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
6786 /* Give a warning, but do as the user requests anyway. */
6787 (*_bfd_error_handler)
6788 (_("%B: warning: selected STM32L4XX erratum "
6789 "workaround is not necessary for target architecture"), obfd);
6790 }
6791}
c7b8f16e 6792
906e58ca
NC		 6793enum bfd_arm_vfp11_pipe
6794{
c7b8f16e
JB		 6795 VFP11_FMAC,
6796 VFP11_LS,
6797 VFP11_DS,
6798 VFP11_BAD
6799};
6800
6801/* Return a VFP register number. This is encoded as RX:X for single-precision
6802 registers, or X:RX for double-precision registers, where RX is the group of
6803 four bits in the instruction encoding and X is the single extension bit.
6804 RX and X fields are specified using their lowest (starting) bit. The return
6805 value is:
6806
6807 0...31: single-precision registers s0...s31
6808 32...63: double-precision registers d0...d31.
906e58ca 6809
c7b8f16e
JB		 6810 Although X should be zero for VFP11 (encoding d0...d15 only), we might
6811 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 6812
c7b8f16e
JB		 6813static unsigned int
6814bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 6815 unsigned int x)
c7b8f16e
JB		 6816{
6817 if (is_double)
6818 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
6819 else
6820 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
6821}
6822
6823/* Set bits in *WMASK according to a register number REG as encoded by
6824 bfd_arm_vfp11_regno(). Ignore d16-d31. */
6825
6826static void
6827bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
6828{
6829 if (reg < 32)
6830 *wmask |= 1 << reg;
6831 else if (reg < 48)
6832 *wmask |= 3 << ((reg - 32) * 2);
6833}
6834
6835/* Return TRUE if WMASK overwrites anything in REGS. */
6836
6837static bfd_boolean
6838bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
6839{
6840 int i;
906e58ca 6841
c7b8f16e
JB		 6842 for (i = 0; i < numregs; i++)
6843 {
6844 unsigned int reg = regs[i];
6845
6846 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 6847 return TRUE;
906e58ca 6848
c7b8f16e
JB		 6849 reg -= 32;
6850
6851 if (reg >= 16)
99059e56 6852 continue;
906e58ca 6853
c7b8f16e 6854 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 6855 return TRUE;
c7b8f16e 6856 }
906e58ca 6857
c7b8f16e
JB		 6858 return FALSE;
6859}
6860
6861/* In this function, we're interested in two things: finding input registers
6862 for VFP data-processing instructions, and finding the set of registers which
6863 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
6864 hold the written set, so FLDM etc. are easy to deal with (we're only
6865 interested in 32 SP registers or 16 dp registers, due to the VFP version
6866 implemented by the chip in question). DP registers are marked by setting
6867 both SP registers in the write mask). */
6868
6869static enum bfd_arm_vfp11_pipe
6870bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 6871 int *numregs)
c7b8f16e 6872{
91d6fa6a 6873 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 6874 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
6875
6876 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
6877 {
6878 unsigned int pqrs;
6879 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
6880 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
6881
6882 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 6883 | ((insn & 0x00300000) >> 19)
6884 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 6885
6886 switch (pqrs)
99059e56
RM		 6887 {
6888 case 0: /* fmac[sd]. */
6889 case 1: /* fnmac[sd]. */
6890 case 2: /* fmsc[sd]. */
6891 case 3: /* fnmsc[sd]. */
6892 vpipe = VFP11_FMAC;
6893 bfd_arm_vfp11_write_mask (destmask, fd);
6894 regs[0] = fd;
6895 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
6896 regs[2] = fm;
6897 *numregs = 3;
6898 break;
6899
6900 case 4: /* fmul[sd]. */
6901 case 5: /* fnmul[sd]. */
6902 case 6: /* fadd[sd]. */
6903 case 7: /* fsub[sd]. */
6904 vpipe = VFP11_FMAC;
6905 goto vfp_binop;
6906
6907 case 8: /* fdiv[sd]. */
6908 vpipe = VFP11_DS;
6909 vfp_binop:
6910 bfd_arm_vfp11_write_mask (destmask, fd);
6911 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
6912 regs[1] = fm;
6913 *numregs = 2;
6914 break;
6915
6916 case 15: /* extended opcode. */
6917 {
6918 unsigned int extn = ((insn >> 15) & 0x1e)
6919 | ((insn >> 7) & 1);
6920
6921 switch (extn)
6922 {
6923 case 0: /* fcpy[sd]. */
6924 case 1: /* fabs[sd]. */
6925 case 2: /* fneg[sd]. */
6926 case 8: /* fcmp[sd]. */
6927 case 9: /* fcmpe[sd]. */
6928 case 10: /* fcmpz[sd]. */
6929 case 11: /* fcmpez[sd]. */
6930 case 16: /* fuito[sd]. */
6931 case 17: /* fsito[sd]. */
6932 case 24: /* ftoui[sd]. */
6933 case 25: /* ftouiz[sd]. */
6934 case 26: /* ftosi[sd]. */
6935 case 27: /* ftosiz[sd]. */
6936 /* These instructions will not bounce due to underflow. */
6937 *numregs = 0;
6938 vpipe = VFP11_FMAC;
6939 break;
6940
6941 case 3: /* fsqrt[sd]. */
6942 /* fsqrt cannot underflow, but it can (perhaps) overwrite
6943 registers to cause the erratum in previous instructions. */
6944 bfd_arm_vfp11_write_mask (destmask, fd);
6945 vpipe = VFP11_DS;
6946 break;
6947
6948 case 15: /* fcvt{ds,sd}. */
6949 {
6950 int rnum = 0;
6951
6952 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 6953
6954 /* Only FCVTSD can underflow. */
99059e56
RM		 6955 if ((insn & 0x100) != 0)
6956 regs[rnum++] = fm;
c7b8f16e 6957
99059e56 6958 *numregs = rnum;
c7b8f16e 6959
99059e56
RM		 6960 vpipe = VFP11_FMAC;
6961 }
6962 break;
c7b8f16e 6963
99059e56
RM		 6964 default:
6965 return VFP11_BAD;
6966 }
6967 }
6968 break;
c7b8f16e 6969
99059e56
RM		 6970 default:
6971 return VFP11_BAD;
6972 }
c7b8f16e
JB		 6973 }
6974 /* Two-register transfer. */
6975 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
6976 {
6977 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 6978
c7b8f16e
JB		 6979 if ((insn & 0x100000) == 0)
6980 {
99059e56
RM		 6981 if (is_double)
6982 bfd_arm_vfp11_write_mask (destmask, fm);
6983 else
6984 {
6985 bfd_arm_vfp11_write_mask (destmask, fm);
6986 bfd_arm_vfp11_write_mask (destmask, fm + 1);
6987 }
c7b8f16e
JB		 6988 }
6989
91d6fa6a 6990 vpipe = VFP11_LS;
c7b8f16e
JB		 6991 }
6992 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
6993 {
6994 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
6995 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 6996
c7b8f16e 6997 switch (puw)
99059e56
RM		 6998 {
6999 case 0: /* Two-reg transfer. We should catch these above. */
7000 abort ();
906e58ca 7001
99059e56
RM		 7002 case 2: /* fldm[sdx]. */
7003 case 3:
7004 case 5:
7005 {
7006 unsigned int i, offset = insn & 0xff;
c7b8f16e 7007
99059e56
RM		 7008 if (is_double)
7009 offset >>= 1;
c7b8f16e 7010
99059e56
RM		 7011 for (i = fd; i < fd + offset; i++)
7012 bfd_arm_vfp11_write_mask (destmask, i);
7013 }
7014 break;
906e58ca 7015
99059e56
RM		 7016 case 4: /* fld[sd]. */
7017 case 6:
7018 bfd_arm_vfp11_write_mask (destmask, fd);
7019 break;
906e58ca 7020
99059e56
RM		 7021 default:
7022 return VFP11_BAD;
7023 }
c7b8f16e 7024
91d6fa6a 7025 vpipe = VFP11_LS;
c7b8f16e
JB		 7026 }
7027 /* Single-register transfer. Note L==0. */
7028 else if ((insn & 0x0f100e10) == 0x0e000a10)
7029 {
7030 unsigned int opcode = (insn >> 21) & 7;
7031 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
7032
7033 switch (opcode)
99059e56
RM		 7034 {
7035 case 0: /* fmsr/fmdlr. */
7036 case 1: /* fmdhr. */
7037 /* Mark fmdhr and fmdlr as writing to the whole of the DP
7038 destination register. I don't know if this is exactly right,
7039 but it is the conservative choice. */
7040 bfd_arm_vfp11_write_mask (destmask, fn);
7041 break;
7042
7043 case 7: /* fmxr. */
7044 break;
7045 }
c7b8f16e 7046
91d6fa6a 7047 vpipe = VFP11_LS;
c7b8f16e
JB		 7048 }
7049
91d6fa6a 7050 return vpipe;
c7b8f16e
JB		 7051}
7052
7053
7054static int elf32_arm_compare_mapping (const void * a, const void * b);
7055
7056
7057/* Look for potentially-troublesome code sequences which might trigger the
7058 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
7059 (available from ARM) for details of the erratum. A short version is
7060 described in ld.texinfo. */
7061
7062bfd_boolean
7063bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
7064{
7065 asection *sec;
7066 bfd_byte *contents = NULL;
7067 int state = 0;
7068 int regs[3], numregs = 0;
7069 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7070 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 7071
4dfe6ac6
NC		 7072 if (globals == NULL)
7073 return FALSE;
7074
c7b8f16e
JB		 7075 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
7076 The states transition as follows:
906e58ca 7077
c7b8f16e 7078 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 7079 A VFP FMAC-pipeline instruction has been seen. Fill
7080 regs[0]..regs[numregs-1] with its input operands. Remember this
7081 instruction in 'first_fmac'.
c7b8f16e
JB		 7082
7083 1 -> 2
99059e56
RM		 7084 Any instruction, except for a VFP instruction which overwrites
7085 regs[*].
906e58ca 7086
c7b8f16e
JB		 7087 1 -> 3 [ -> 0 ] or
7088 2 -> 3 [ -> 0 ]
99059e56
RM		 7089 A VFP instruction has been seen which overwrites any of regs[*].
7090 We must make a veneer! Reset state to 0 before examining next
7091 instruction.
906e58ca 7092
c7b8f16e 7093 2 -> 0
99059e56
RM		 7094 If we fail to match anything in state 2, reset to state 0 and reset
7095 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 7096
7097 If the VFP11 vector mode is in use, there must be at least two unrelated
7098 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 7099 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 7100
7101 /* If we are only performing a partial link do not bother
7102 to construct any glue. */
0e1862bb 7103 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 7104 return TRUE;
7105
0ffa91dd
NC		 7106 /* Skip if this bfd does not correspond to an ELF image. */
7107 if (! is_arm_elf (abfd))
7108 return TRUE;
906e58ca 7109
c7b8f16e
JB		 7110 /* We should have chosen a fix type by the time we get here. */
7111 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
7112
7113 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
7114 return TRUE;
2e6030b9 7115
33a7ffc2
JM		 7116 /* Skip this BFD if it corresponds to an executable or dynamic object. */
7117 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
7118 return TRUE;
7119
c7b8f16e
JB		 7120 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7121 {
7122 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
7123 struct _arm_elf_section_data *sec_data;
7124
7125 /* If we don't have executable progbits, we're not interested in this
99059e56 7126 section. Also skip if section is to be excluded. */
c7b8f16e 7127 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 7128 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
7129 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 7130 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 7131 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 7132 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
7133 continue;
c7b8f16e
JB		 7134
7135 sec_data = elf32_arm_section_data (sec);
906e58ca 7136
c7b8f16e 7137 if (sec_data->mapcount == 0)
99059e56 7138 continue;
906e58ca 7139
c7b8f16e
JB		 7140 if (elf_section_data (sec)->this_hdr.contents != NULL)
7141 contents = elf_section_data (sec)->this_hdr.contents;
7142 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
7143 goto error_return;
7144
7145 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
7146 elf32_arm_compare_mapping);
7147
7148 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 7149 {
7150 unsigned int span_start = sec_data->map[span].vma;
7151 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 7152 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 7153 char span_type = sec_data->map[span].type;
7154
7155 /* FIXME: Only ARM mode is supported at present. We may need to
7156 support Thumb-2 mode also at some point. */
7157 if (span_type != 'a')
7158 continue;
7159
7160 for (i = span_start; i < span_end;)
7161 {
7162 unsigned int next_i = i + 4;
7163 unsigned int insn = bfd_big_endian (abfd)
7164 ? (contents[i] << 24)
7165 | (contents[i + 1] << 16)
7166 | (contents[i + 2] << 8)
7167 | contents[i + 3]
7168 : (contents[i + 3] << 24)
7169 | (contents[i + 2] << 16)
7170 | (contents[i + 1] << 8)
7171 | contents[i];
7172 unsigned int writemask = 0;
7173 enum bfd_arm_vfp11_pipe vpipe;
7174
7175 switch (state)
7176 {
7177 case 0:
7178 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
7179 &numregs);
7180 /* I'm assuming the VFP11 erratum can trigger with denorm
7181 operands on either the FMAC or the DS pipeline. This might
7182 lead to slightly overenthusiastic veneer insertion. */
7183 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
7184 {
7185 state = use_vector ? 1 : 2;
7186 first_fmac = i;
7187 veneer_of_insn = insn;
7188 }
7189 break;
7190
7191 case 1:
7192 {
7193 int other_regs[3], other_numregs;
7194 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 7195 other_regs,
99059e56
RM		 7196 &other_numregs);
7197 if (vpipe != VFP11_BAD
7198 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 7199 numregs))
99059e56
RM		 7200 state = 3;
7201 else
7202 state = 2;
7203 }
7204 break;
7205
7206 case 2:
7207 {
7208 int other_regs[3], other_numregs;
7209 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 7210 other_regs,
99059e56
RM		 7211 &other_numregs);
7212 if (vpipe != VFP11_BAD
7213 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 7214 numregs))
99059e56
RM		 7215 state = 3;
7216 else
7217 {
7218 state = 0;
7219 next_i = first_fmac + 4;
7220 }
7221 }
7222 break;
7223
7224 case 3:
7225 abort (); /* Should be unreachable. */
7226 }
7227
7228 if (state == 3)
7229 {
7230 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
7231 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
7232
7233 elf32_arm_section_data (sec)->erratumcount += 1;
7234
7235 newerr->u.b.vfp_insn = veneer_of_insn;
7236
7237 switch (span_type)
7238 {
7239 case 'a':
7240 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
7241 break;
7242
7243 default:
7244 abort ();
7245 }
7246
7247 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 7248 first_fmac);
7249
99059e56 7250 newerr->vma = -1;
c7b8f16e 7251
99059e56
RM		 7252 newerr->next = sec_data->erratumlist;
7253 sec_data->erratumlist = newerr;
c7b8f16e 7254
99059e56
RM		 7255 state = 0;
7256 }
c7b8f16e 7257
99059e56
RM		 7258 i = next_i;
7259 }
7260 }
906e58ca 7261
c7b8f16e 7262 if (contents != NULL
99059e56
RM		 7263 && elf_section_data (sec)->this_hdr.contents != contents)
7264 free (contents);
c7b8f16e
JB		 7265 contents = NULL;
7266 }
7267
7268 return TRUE;
7269
7270error_return:
7271 if (contents != NULL
7272 && elf_section_data (sec)->this_hdr.contents != contents)
7273 free (contents);
906e58ca 7274
c7b8f16e
JB		 7275 return FALSE;
7276}
7277
7278/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
7279 after sections have been laid out, using specially-named symbols. */
7280
7281void
7282bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
7283 struct bfd_link_info *link_info)
7284{
7285 asection *sec;
7286 struct elf32_arm_link_hash_table *globals;
7287 char *tmp_name;
906e58ca 7288
0e1862bb 7289 if (bfd_link_relocatable (link_info))
c7b8f16e 7290 return;
2e6030b9
MS		 7291
7292 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 7293 if (! is_arm_elf (abfd))
2e6030b9
MS		 7294 return;
7295
c7b8f16e 7296 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7297 if (globals == NULL)
7298 return;
906e58ca 7299
21d799b5 7300 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7301 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 7302
7303 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7304 {
7305 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7306 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 7307
c7b8f16e 7308 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 7309 {
7310 struct elf_link_hash_entry *myh;
7311 bfd_vma vma;
7312
7313 switch (errnode->type)
7314 {
7315 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
7316 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
7317 /* Find veneer symbol. */
7318 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 7319 errnode->u.b.veneer->u.v.id);
7320
99059e56
RM		 7321 myh = elf_link_hash_lookup
7322 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 7323
a504d23a
LA		 7324 if (myh == NULL)
7325 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
7326 "`%s'"), abfd, tmp_name);
7327
7328 vma = myh->root.u.def.section->output_section->vma
7329 + myh->root.u.def.section->output_offset
7330 + myh->root.u.def.value;
7331
7332 errnode->u.b.veneer->vma = vma;
7333 break;
7334
7335 case VFP11_ERRATUM_ARM_VENEER:
7336 case VFP11_ERRATUM_THUMB_VENEER:
7337 /* Find return location. */
7338 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7339 errnode->u.v.id);
7340
7341 myh = elf_link_hash_lookup
7342 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7343
7344 if (myh == NULL)
7345 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
7346 "`%s'"), abfd, tmp_name);
7347
7348 vma = myh->root.u.def.section->output_section->vma
7349 + myh->root.u.def.section->output_offset
7350 + myh->root.u.def.value;
7351
7352 errnode->u.v.branch->vma = vma;
7353 break;
7354
7355 default:
7356 abort ();
7357 }
7358 }
7359 }
7360
7361 free (tmp_name);
7362}
7363
7364/* Find virtual-memory addresses for STM32L4XX erratum veneers and
7365 return locations after sections have been laid out, using
7366 specially-named symbols. */
7367
7368void
7369bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
7370 struct bfd_link_info *link_info)
7371{
7372 asection *sec;
7373 struct elf32_arm_link_hash_table *globals;
7374 char *tmp_name;
7375
7376 if (bfd_link_relocatable (link_info))
7377 return;
7378
7379 /* Skip if this bfd does not correspond to an ELF image. */
7380 if (! is_arm_elf (abfd))
7381 return;
7382
7383 globals = elf32_arm_hash_table (link_info);
7384 if (globals == NULL)
7385 return;
7386
7387 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7388 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7389
7390 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7391 {
7392 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7393 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
7394
7395 for (; errnode != NULL; errnode = errnode->next)
7396 {
7397 struct elf_link_hash_entry *myh;
7398 bfd_vma vma;
7399
7400 switch (errnode->type)
7401 {
7402 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
7403 /* Find veneer symbol. */
7404 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7405 errnode->u.b.veneer->u.v.id);
7406
7407 myh = elf_link_hash_lookup
7408 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7409
7410 if (myh == NULL)
7411 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
7412 "`%s'"), abfd, tmp_name);
7413
7414 vma = myh->root.u.def.section->output_section->vma
7415 + myh->root.u.def.section->output_offset
7416 + myh->root.u.def.value;
7417
7418 errnode->u.b.veneer->vma = vma;
7419 break;
7420
7421 case STM32L4XX_ERRATUM_VENEER:
7422 /* Find return location. */
7423 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7424 errnode->u.v.id);
7425
7426 myh = elf_link_hash_lookup
7427 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7428
7429 if (myh == NULL)
7430 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
7431 "`%s'"), abfd, tmp_name);
7432
7433 vma = myh->root.u.def.section->output_section->vma
7434 + myh->root.u.def.section->output_offset
7435 + myh->root.u.def.value;
7436
7437 errnode->u.v.branch->vma = vma;
7438 break;
7439
7440 default:
7441 abort ();
7442 }
7443 }
7444 }
7445
7446 free (tmp_name);
7447}
7448
7449static inline bfd_boolean
7450is_thumb2_ldmia (const insn32 insn)
7451{
7452 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
7453 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
7454 return (insn & 0xffd02000) == 0xe8900000;
7455}
7456
7457static inline bfd_boolean
7458is_thumb2_ldmdb (const insn32 insn)
7459{
7460 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
7461 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
7462 return (insn & 0xffd02000) == 0xe9100000;
7463}
7464
7465static inline bfd_boolean
7466is_thumb2_vldm (const insn32 insn)
7467{
7468 /* A6.5 Extension register load or store instruction
7469 A7.7.229
9239bbd3
CM		 7470 We look for SP 32-bit and DP 64-bit registers.
7471 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
7472 <list> is consecutive 64-bit registers
7473 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 7474 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
7475 <list> is consecutive 32-bit registers
7476 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
7477 if P==0 && U==1 && W==1 && Rn=1101 VPOP
7478 if PUW=010 || PUW=011 || PUW=101 VLDM. */
7479 return
9239bbd3
CM		 7480 (((insn & 0xfe100f00) == 0xec100b00) ||
7481 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 7482 && /* (IA without !). */
7483 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 7484 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 7485 || ((((insn << 7) >> 28) & 0xd) == 0x5)
7486 /* (DB with !). */
7487 || ((((insn << 7) >> 28) & 0xd) == 0x9));
7488}
7489
7490/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
7491 VLDM opcode and:
7492 - computes the number and the mode of memory accesses
7493 - decides if the replacement should be done:
7494 . replaces only if > 8-word accesses
7495 . or (testing purposes only) replaces all accesses. */
7496
7497static bfd_boolean
7498stm32l4xx_need_create_replacing_stub (const insn32 insn,
7499 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
7500{
9239bbd3 7501 int nb_words = 0;
a504d23a
LA		 7502
7503 /* The field encoding the register list is the same for both LDMIA
7504 and LDMDB encodings. */
7505 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
9239bbd3 7506 nb_words = popcount (insn & 0x0000ffff);
a504d23a 7507 else if (is_thumb2_vldm (insn))
9239bbd3 7508 nb_words = (insn & 0xff);
a504d23a
LA		 7509
7510 /* DEFAULT mode accounts for the real bug condition situation,
7511 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
7512 return
9239bbd3 7513 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 7514 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
7515}
7516
7517/* Look for potentially-troublesome code sequences which might trigger
7518 the STM STM32L4XX erratum. */
7519
7520bfd_boolean
7521bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
7522 struct bfd_link_info *link_info)
7523{
7524 asection *sec;
7525 bfd_byte *contents = NULL;
7526 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7527
7528 if (globals == NULL)
7529 return FALSE;
7530
7531 /* If we are only performing a partial link do not bother
7532 to construct any glue. */
7533 if (bfd_link_relocatable (link_info))
7534 return TRUE;
7535
7536 /* Skip if this bfd does not correspond to an ELF image. */
7537 if (! is_arm_elf (abfd))
7538 return TRUE;
7539
7540 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
7541 return TRUE;
7542
7543 /* Skip this BFD if it corresponds to an executable or dynamic object. */
7544 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
7545 return TRUE;
7546
7547 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7548 {
7549 unsigned int i, span;
7550 struct _arm_elf_section_data *sec_data;
7551
7552 /* If we don't have executable progbits, we're not interested in this
7553 section. Also skip if section is to be excluded. */
7554 if (elf_section_type (sec) != SHT_PROGBITS
7555 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
7556 || (sec->flags & SEC_EXCLUDE) != 0
7557 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
7558 || sec->output_section == bfd_abs_section_ptr
7559 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
7560 continue;
7561
7562 sec_data = elf32_arm_section_data (sec);
c7b8f16e 7563
a504d23a
LA		 7564 if (sec_data->mapcount == 0)
7565 continue;
c7b8f16e 7566
a504d23a
LA		 7567 if (elf_section_data (sec)->this_hdr.contents != NULL)
7568 contents = elf_section_data (sec)->this_hdr.contents;
7569 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
7570 goto error_return;
c7b8f16e 7571
a504d23a
LA		 7572 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
7573 elf32_arm_compare_mapping);
c7b8f16e 7574
a504d23a
LA		 7575 for (span = 0; span < sec_data->mapcount; span++)
7576 {
7577 unsigned int span_start = sec_data->map[span].vma;
7578 unsigned int span_end = (span == sec_data->mapcount - 1)
7579 ? sec->size : sec_data->map[span + 1].vma;
7580 char span_type = sec_data->map[span].type;
7581 int itblock_current_pos = 0;
c7b8f16e 7582
a504d23a
LA		 7583 /* Only Thumb2 mode need be supported with this CM4 specific
7584 code, we should not encounter any arm mode eg span_type
7585 != 'a'. */
7586 if (span_type != 't')
7587 continue;
c7b8f16e 7588
a504d23a
LA		 7589 for (i = span_start; i < span_end;)
7590 {
7591 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
7592 bfd_boolean insn_32bit = FALSE;
7593 bfd_boolean is_ldm = FALSE;
7594 bfd_boolean is_vldm = FALSE;
7595 bfd_boolean is_not_last_in_it_block = FALSE;
7596
7597 /* The first 16-bits of all 32-bit thumb2 instructions start
7598 with opcode[15..13]=0b111 and the encoded op1 can be anything
7599 except opcode[12..11]!=0b00.
7600 See 32-bit Thumb instruction encoding. */
7601 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
7602 insn_32bit = TRUE;
c7b8f16e 7603
a504d23a
LA		 7604 /* Compute the predicate that tells if the instruction
7605 is concerned by the IT block
7606 - Creates an error if there is a ldm that is not
7607 last in the IT block thus cannot be replaced
7608 - Otherwise we can create a branch at the end of the
7609 IT block, it will be controlled naturally by IT
7610 with the proper pseudo-predicate
7611 - So the only interesting predicate is the one that
7612 tells that we are not on the last item of an IT
7613 block. */
7614 if (itblock_current_pos != 0)
7615 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 7616
a504d23a
LA		 7617 if (insn_32bit)
7618 {
7619 /* Load the rest of the insn (in manual-friendly order). */
7620 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
7621 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
7622 is_vldm = is_thumb2_vldm (insn);
7623
7624 /* Veneers are created for (v)ldm depending on
7625 option flags and memory accesses conditions; but
7626 if the instruction is not the last instruction of
7627 an IT block, we cannot create a jump there, so we
7628 bail out. */
7629 if ((is_ldm || is_vldm) &&
7630 stm32l4xx_need_create_replacing_stub
7631 (insn, globals->stm32l4xx_fix))
7632 {
7633 if (is_not_last_in_it_block)
7634 {
7635 (*_bfd_error_handler)
7636 /* Note - overlong line used here to allow for translation. */
7637 (_("\
7638%B(%A+0x%lx): error: multiple load detected in non-last IT block instruction : STM32L4XX veneer cannot be generated.\n"
7639 "Use gcc option -mrestrict-it to generate only one instruction per IT block.\n"),
7640 abfd, sec, (long)i);
7641 }
7642 else
7643 {
7644 elf32_stm32l4xx_erratum_list *newerr =
7645 (elf32_stm32l4xx_erratum_list *)
7646 bfd_zmalloc
7647 (sizeof (elf32_stm32l4xx_erratum_list));
7648
7649 elf32_arm_section_data (sec)
7650 ->stm32l4xx_erratumcount += 1;
7651 newerr->u.b.insn = insn;
7652 /* We create only thumb branches. */
7653 newerr->type =
7654 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
7655 record_stm32l4xx_erratum_veneer
7656 (link_info, newerr, abfd, sec,
7657 i,
7658 is_ldm ?
7659 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
7660 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
7661 newerr->vma = -1;
7662 newerr->next = sec_data->stm32l4xx_erratumlist;
7663 sec_data->stm32l4xx_erratumlist = newerr;
7664 }
7665 }
7666 }
7667 else
7668 {
7669 /* A7.7.37 IT p208
7670 IT blocks are only encoded in T1
7671 Encoding T1: IT{x{y{z}}} <firstcond>
7672 1 0 1 1 - 1 1 1 1 - firstcond - mask
7673 if mask = '0000' then see 'related encodings'
7674 We don't deal with UNPREDICTABLE, just ignore these.
7675 There can be no nested IT blocks so an IT block
7676 is naturally a new one for which it is worth
7677 computing its size. */
7678 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00) &&
7679 ((insn & 0x000f) != 0x0000);
7680 /* If we have a new IT block we compute its size. */
7681 if (is_newitblock)
7682 {
7683 /* Compute the number of instructions controlled
7684 by the IT block, it will be used to decide
7685 whether we are inside an IT block or not. */
7686 unsigned int mask = insn & 0x000f;
7687 itblock_current_pos = 4 - ctz (mask);
7688 }
7689 }
7690
7691 i += insn_32bit ? 4 : 2;
99059e56
RM		 7692 }
7693 }
a504d23a
LA		 7694
7695 if (contents != NULL
7696 && elf_section_data (sec)->this_hdr.contents != contents)
7697 free (contents);
7698 contents = NULL;
c7b8f16e 7699 }
906e58ca 7700
a504d23a
LA		 7701 return TRUE;
7702
7703error_return:
7704 if (contents != NULL
7705 && elf_section_data (sec)->this_hdr.contents != contents)
7706 free (contents);
c7b8f16e 7707
a504d23a
LA		 7708 return FALSE;
7709}
c7b8f16e 7710
eb043451
PB		 7711/* Set target relocation values needed during linking. */
7712
7713void
bf21ed78
MS		 7714bfd_elf32_arm_set_target_relocs (struct bfd *output_bfd,
7715 struct bfd_link_info *link_info,
eb043451 7716 int target1_is_rel,
319850b4 7717 char * target2_type,
99059e56 7718 int fix_v4bx,
c7b8f16e 7719 int use_blx,
99059e56 7720 bfd_arm_vfp11_fix vfp11_fix,
a504d23a 7721 bfd_arm_stm32l4xx_fix stm32l4xx_fix,
a9dc9481 7722 int no_enum_warn, int no_wchar_warn,
2de70689
MGD		 7723 int pic_veneer, int fix_cortex_a8,
7724 int fix_arm1176)
eb043451
PB		 7725{
7726 struct elf32_arm_link_hash_table *globals;
7727
7728 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7729 if (globals == NULL)
7730 return;
eb043451
PB		 7731
7732 globals->target1_is_rel = target1_is_rel;
7733 if (strcmp (target2_type, "rel") == 0)
7734 globals->target2_reloc = R_ARM_REL32;
eeac373a
PB		 7735 else if (strcmp (target2_type, "abs") == 0)
7736 globals->target2_reloc = R_ARM_ABS32;
eb043451
PB		 7737 else if (strcmp (target2_type, "got-rel") == 0)
7738 globals->target2_reloc = R_ARM_GOT_PREL;
7739 else
7740 {
7741 _bfd_error_handler (_("Invalid TARGET2 relocation type '%s'."),
7742 target2_type);
7743 }
319850b4 7744 globals->fix_v4bx = fix_v4bx;
33bfe774 7745 globals->use_blx |= use_blx;
c7b8f16e 7746 globals->vfp11_fix = vfp11_fix;
a504d23a 7747 globals->stm32l4xx_fix = stm32l4xx_fix;
27e55c4d 7748 globals->pic_veneer = pic_veneer;
48229727 7749 globals->fix_cortex_a8 = fix_cortex_a8;
2de70689 7750 globals->fix_arm1176 = fix_arm1176;
bf21ed78 7751
0ffa91dd
NC		 7752 BFD_ASSERT (is_arm_elf (output_bfd));
7753 elf_arm_tdata (output_bfd)->no_enum_size_warning = no_enum_warn;
a9dc9481 7754 elf_arm_tdata (output_bfd)->no_wchar_size_warning = no_wchar_warn;
eb043451 7755}
eb043451 7756
12a0a0fd 7757/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 7758
12a0a0fd
PB		 7759static void
7760insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
7761{
7762 bfd_vma upper;
7763 bfd_vma lower;
7764 int reloc_sign;
7765
7766 BFD_ASSERT ((offset & 1) == 0);
7767
7768 upper = bfd_get_16 (abfd, insn);
7769 lower = bfd_get_16 (abfd, insn + 2);
7770 reloc_sign = (offset < 0) ? 1 : 0;
7771 upper = (upper & ~(bfd_vma) 0x7ff)
7772 | ((offset >> 12) & 0x3ff)
7773 | (reloc_sign << 10);
906e58ca 7774 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 7775 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
7776 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
7777 | ((offset >> 1) & 0x7ff);
7778 bfd_put_16 (abfd, upper, insn);
7779 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 7780}
7781
9b485d32
NC		 7782/* Thumb code calling an ARM function. */
7783
252b5132 7784static int
57e8b36a
NC		 7785elf32_thumb_to_arm_stub (struct bfd_link_info * info,
7786 const char * name,
7787 bfd * input_bfd,
7788 bfd * output_bfd,
7789 asection * input_section,
7790 bfd_byte * hit_data,
7791 asection * sym_sec,
7792 bfd_vma offset,
7793 bfd_signed_vma addend,
f2a9dd69
DJ		 7794 bfd_vma val,
7795 char **error_message)
252b5132 7796{
bcbdc74c 7797 asection * s = 0;
dc810e39 7798 bfd_vma my_offset;
252b5132 7799 long int ret_offset;
bcbdc74c
NC		 7800 struct elf_link_hash_entry * myh;
7801 struct elf32_arm_link_hash_table * globals;
252b5132 7802
f2a9dd69 7803 myh = find_thumb_glue (info, name, error_message);
252b5132 7804 if (myh == NULL)
b34976b6 7805 return FALSE;
252b5132
RH		 7806
7807 globals = elf32_arm_hash_table (info);
252b5132
RH		 7808 BFD_ASSERT (globals != NULL);
7809 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7810
7811 my_offset = myh->root.u.def.value;
7812
3d4d4302
AM		 7813 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
7814 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 7815
7816 BFD_ASSERT (s != NULL);
7817 BFD_ASSERT (s->contents != NULL);
7818 BFD_ASSERT (s->output_section != NULL);
7819
7820 if ((my_offset & 0x01) == 0x01)
7821 {
7822 if (sym_sec != NULL
7823 && sym_sec->owner != NULL
7824 && !INTERWORK_FLAG (sym_sec->owner))
7825 {
8f615d07 7826 (*_bfd_error_handler)
d003868e 7827 (_("%B(%s): warning: interworking not enabled.\n"
3aaeb7d3 7828 " first occurrence: %B: Thumb call to ARM"),
d003868e 7829 sym_sec->owner, input_bfd, name);
252b5132 7830
b34976b6 7831 return FALSE;
252b5132
RH		 7832 }
7833
7834 --my_offset;
7835 myh->root.u.def.value = my_offset;
7836
52ab56c2
PB		 7837 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
7838 s->contents + my_offset);
252b5132 7839
52ab56c2
PB		 7840 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
7841 s->contents + my_offset + 2);
252b5132
RH		 7842
7843 ret_offset =
9b485d32
NC		 7844 /* Address of destination of the stub. */
7845 ((bfd_signed_vma) val)
252b5132 7846 - ((bfd_signed_vma)
57e8b36a
NC		 7847 /* Offset from the start of the current section
7848 to the start of the stubs. */
9b485d32
NC		 7849 (s->output_offset
7850 /* Offset of the start of this stub from the start of the stubs. */
7851 + my_offset
7852 /* Address of the start of the current section. */
7853 + s->output_section->vma)
7854 /* The branch instruction is 4 bytes into the stub. */
7855 + 4
7856 /* ARM branches work from the pc of the instruction + 8. */
7857 + 8);
252b5132 7858
52ab56c2
PB		 7859 put_arm_insn (globals, output_bfd,
7860 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
7861 s->contents + my_offset + 4);
252b5132
RH		 7862 }
7863
7864 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
7865
427bfd90
NC		 7866 /* Now go back and fix up the original BL insn to point to here. */
7867 ret_offset =
7868 /* Address of where the stub is located. */
7869 (s->output_section->vma + s->output_offset + my_offset)
7870 /* Address of where the BL is located. */
57e8b36a
NC		 7871 - (input_section->output_section->vma + input_section->output_offset
7872 + offset)
427bfd90
NC		 7873 /* Addend in the relocation. */
7874 - addend
7875 /* Biassing for PC-relative addressing. */
7876 - 8;
252b5132 7877
12a0a0fd 7878 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 7879
b34976b6 7880 return TRUE;
252b5132
RH		 7881}
7882
a4fd1a8e 7883/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 7884
a4fd1a8e
PB		 7885static struct elf_link_hash_entry *
7886elf32_arm_create_thumb_stub (struct bfd_link_info * info,
7887 const char * name,
7888 bfd * input_bfd,
7889 bfd * output_bfd,
7890 asection * sym_sec,
7891 bfd_vma val,
8029a119
NC		 7892 asection * s,
7893 char ** error_message)
252b5132 7894{
dc810e39 7895 bfd_vma my_offset;
252b5132 7896 long int ret_offset;
bcbdc74c
NC		 7897 struct elf_link_hash_entry * myh;
7898 struct elf32_arm_link_hash_table * globals;
252b5132 7899
f2a9dd69 7900 myh = find_arm_glue (info, name, error_message);
252b5132 7901 if (myh == NULL)
a4fd1a8e 7902 return NULL;
252b5132
RH		 7903
7904 globals = elf32_arm_hash_table (info);
252b5132
RH		 7905 BFD_ASSERT (globals != NULL);
7906 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7907
7908 my_offset = myh->root.u.def.value;
252b5132
RH		 7909
7910 if ((my_offset & 0x01) == 0x01)
7911 {
7912 if (sym_sec != NULL
7913 && sym_sec->owner != NULL
7914 && !INTERWORK_FLAG (sym_sec->owner))
7915 {
8f615d07 7916 (*_bfd_error_handler)
d003868e
AM		 7917 (_("%B(%s): warning: interworking not enabled.\n"
7918 " first occurrence: %B: arm call to thumb"),
7919 sym_sec->owner, input_bfd, name);
252b5132 7920 }
9b485d32 7921
252b5132
RH		 7922 --my_offset;
7923 myh->root.u.def.value = my_offset;
7924
0e1862bb
L		 7925 if (bfd_link_pic (info)
7926 || globals->root.is_relocatable_executable
27e55c4d 7927 || globals->pic_veneer)
8f6277f5
PB		 7928 {
7929 /* For relocatable objects we can't use absolute addresses,
7930 so construct the address from a relative offset. */
7931 /* TODO: If the offset is small it's probably worth
7932 constructing the address with adds. */
52ab56c2
PB		 7933 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
7934 s->contents + my_offset);
7935 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
7936 s->contents + my_offset + 4);
7937 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
7938 s->contents + my_offset + 8);
8f6277f5
PB		 7939 /* Adjust the offset by 4 for the position of the add,
7940 and 8 for the pipeline offset. */
7941 ret_offset = (val - (s->output_offset
7942 + s->output_section->vma
7943 + my_offset + 12))
7944 | 1;
7945 bfd_put_32 (output_bfd, ret_offset,
7946 s->contents + my_offset + 12);
7947 }
26079076
PB		 7948 else if (globals->use_blx)
7949 {
7950 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
7951 s->contents + my_offset);
7952
7953 /* It's a thumb address. Add the low order bit. */
7954 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
7955 s->contents + my_offset + 4);
7956 }
8f6277f5
PB		 7957 else
7958 {
52ab56c2
PB		 7959 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
7960 s->contents + my_offset);
252b5132 7961
52ab56c2
PB		 7962 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
7963 s->contents + my_offset + 4);
252b5132 7964
8f6277f5
PB		 7965 /* It's a thumb address. Add the low order bit. */
7966 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
7967 s->contents + my_offset + 8);
8029a119
NC		 7968
7969 my_offset += 12;
8f6277f5 7970 }
252b5132
RH		 7971 }
7972
7973 BFD_ASSERT (my_offset <= globals->arm_glue_size);
7974
a4fd1a8e
PB		 7975 return myh;
7976}
7977
7978/* Arm code calling a Thumb function. */
7979
7980static int
7981elf32_arm_to_thumb_stub (struct bfd_link_info * info,
7982 const char * name,
7983 bfd * input_bfd,
7984 bfd * output_bfd,
7985 asection * input_section,
7986 bfd_byte * hit_data,
7987 asection * sym_sec,
7988 bfd_vma offset,
7989 bfd_signed_vma addend,
f2a9dd69
DJ		 7990 bfd_vma val,
7991 char **error_message)
a4fd1a8e
PB		 7992{
7993 unsigned long int tmp;
7994 bfd_vma my_offset;
7995 asection * s;
7996 long int ret_offset;
7997 struct elf_link_hash_entry * myh;
7998 struct elf32_arm_link_hash_table * globals;
7999
8000 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8001 BFD_ASSERT (globals != NULL);
8002 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8003
3d4d4302
AM		 8004 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8005 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8006 BFD_ASSERT (s != NULL);
8007 BFD_ASSERT (s->contents != NULL);
8008 BFD_ASSERT (s->output_section != NULL);
8009
8010 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 8011 sym_sec, val, s, error_message);
a4fd1a8e
PB		 8012 if (!myh)
8013 return FALSE;
8014
8015 my_offset = myh->root.u.def.value;
252b5132
RH		 8016 tmp = bfd_get_32 (input_bfd, hit_data);
8017 tmp = tmp & 0xFF000000;
8018
9b485d32 8019 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 8020 ret_offset = (s->output_offset
8021 + my_offset
8022 + s->output_section->vma
8023 - (input_section->output_offset
8024 + input_section->output_section->vma
8025 + offset + addend)
8026 - 8);
9a5aca8c 8027
252b5132
RH		 8028 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
8029
dc810e39 8030 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 8031
b34976b6 8032 return TRUE;
252b5132
RH		 8033}
8034
a4fd1a8e
PB		 8035/* Populate Arm stub for an exported Thumb function. */
8036
8037static bfd_boolean
8038elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
8039{
8040 struct bfd_link_info * info = (struct bfd_link_info *) inf;
8041 asection * s;
8042 struct elf_link_hash_entry * myh;
8043 struct elf32_arm_link_hash_entry *eh;
8044 struct elf32_arm_link_hash_table * globals;
8045 asection *sec;
8046 bfd_vma val;
f2a9dd69 8047 char *error_message;
a4fd1a8e 8048
906e58ca 8049 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 8050 /* Allocate stubs for exported Thumb functions on v4t. */
8051 if (eh->export_glue == NULL)
8052 return TRUE;
8053
8054 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8055 BFD_ASSERT (globals != NULL);
8056 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8057
3d4d4302
AM		 8058 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8059 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8060 BFD_ASSERT (s != NULL);
8061 BFD_ASSERT (s->contents != NULL);
8062 BFD_ASSERT (s->output_section != NULL);
8063
8064 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 8065
8066 BFD_ASSERT (sec->output_section != NULL);
8067
a4fd1a8e
PB		 8068 val = eh->export_glue->root.u.def.value + sec->output_offset
8069 + sec->output_section->vma;
8029a119 8070
a4fd1a8e
PB		 8071 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
8072 h->root.u.def.section->owner,
f2a9dd69
DJ		 8073 globals->obfd, sec, val, s,
8074 &error_message);
a4fd1a8e
PB		 8075 BFD_ASSERT (myh);
8076 return TRUE;
8077}
8078
845b51d6
PB		 8079/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
8080
8081static bfd_vma
8082elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
8083{
8084 bfd_byte *p;
8085 bfd_vma glue_addr;
8086 asection *s;
8087 struct elf32_arm_link_hash_table *globals;
8088
8089 globals = elf32_arm_hash_table (info);
845b51d6
PB		 8090 BFD_ASSERT (globals != NULL);
8091 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8092
3d4d4302
AM		 8093 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8094 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 8095 BFD_ASSERT (s != NULL);
8096 BFD_ASSERT (s->contents != NULL);
8097 BFD_ASSERT (s->output_section != NULL);
8098
8099 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
8100
8101 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
8102
8103 if ((globals->bx_glue_offset[reg] & 1) == 0)
8104 {
8105 p = s->contents + glue_addr;
8106 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
8107 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
8108 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
8109 globals->bx_glue_offset[reg] |= 1;
8110 }
8111
8112 return glue_addr + s->output_section->vma + s->output_offset;
8113}
8114
a4fd1a8e
PB		 8115/* Generate Arm stubs for exported Thumb symbols. */
8116static void
906e58ca 8117elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 8118 struct bfd_link_info *link_info)
8119{
8120 struct elf32_arm_link_hash_table * globals;
8121
8029a119
NC		 8122 if (link_info == NULL)
8123 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 8124 return;
8125
8126 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8127 if (globals == NULL)
8128 return;
8129
84c08195
PB		 8130 /* If blx is available then exported Thumb symbols are OK and there is
8131 nothing to do. */
a4fd1a8e
PB		 8132 if (globals->use_blx)
8133 return;
8134
8135 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
8136 link_info);
8137}
8138
47beaa6a
RS		 8139/* Reserve space for COUNT dynamic relocations in relocation selection
8140 SRELOC. */
8141
8142static void
8143elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
8144 bfd_size_type count)
8145{
8146 struct elf32_arm_link_hash_table *htab;
8147
8148 htab = elf32_arm_hash_table (info);
8149 BFD_ASSERT (htab->root.dynamic_sections_created);
8150 if (sreloc == NULL)
8151 abort ();
8152 sreloc->size += RELOC_SIZE (htab) * count;
8153}
8154
34e77a92
RS		 8155/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
8156 dynamic, the relocations should go in SRELOC, otherwise they should
8157 go in the special .rel.iplt section. */
8158
8159static void
8160elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
8161 bfd_size_type count)
8162{
8163 struct elf32_arm_link_hash_table *htab;
8164
8165 htab = elf32_arm_hash_table (info);
8166 if (!htab->root.dynamic_sections_created)
8167 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
8168 else
8169 {
8170 BFD_ASSERT (sreloc != NULL);
8171 sreloc->size += RELOC_SIZE (htab) * count;
8172 }
8173}
8174
47beaa6a
RS		 8175/* Add relocation REL to the end of relocation section SRELOC. */
8176
8177static void
8178elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
8179 asection *sreloc, Elf_Internal_Rela *rel)
8180{
8181 bfd_byte *loc;
8182 struct elf32_arm_link_hash_table *htab;
8183
8184 htab = elf32_arm_hash_table (info);
34e77a92
RS		 8185 if (!htab->root.dynamic_sections_created
8186 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
8187 sreloc = htab->root.irelplt;
47beaa6a
RS		 8188 if (sreloc == NULL)
8189 abort ();
8190 loc = sreloc->contents;
8191 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
8192 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
8193 abort ();
8194 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
8195}
8196
34e77a92
RS		 8197/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
8198 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
8199 to .plt. */
8200
8201static void
8202elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
8203 bfd_boolean is_iplt_entry,
8204 union gotplt_union *root_plt,
8205 struct arm_plt_info *arm_plt)
8206{
8207 struct elf32_arm_link_hash_table *htab;
8208 asection *splt;
8209 asection *sgotplt;
8210
8211 htab = elf32_arm_hash_table (info);
8212
8213 if (is_iplt_entry)
8214 {
8215 splt = htab->root.iplt;
8216 sgotplt = htab->root.igotplt;
8217
99059e56
RM		 8218 /* NaCl uses a special first entry in .iplt too. */
8219 if (htab->nacl_p && splt->size == 0)
8220 splt->size += htab->plt_header_size;
8221
34e77a92
RS		 8222 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
8223 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
8224 }
8225 else
8226 {
8227 splt = htab->root.splt;
8228 sgotplt = htab->root.sgotplt;
8229
8230 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
8231 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
8232
8233 /* If this is the first .plt entry, make room for the special
8234 first entry. */
8235 if (splt->size == 0)
8236 splt->size += htab->plt_header_size;
9f19ab6d
WN		 8237
8238 htab->next_tls_desc_index++;
34e77a92
RS		 8239 }
8240
8241 /* Allocate the PLT entry itself, including any leading Thumb stub. */
8242 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
8243 splt->size += PLT_THUMB_STUB_SIZE;
8244 root_plt->offset = splt->size;
8245 splt->size += htab->plt_entry_size;
8246
8247 if (!htab->symbian_p)
8248 {
8249 /* We also need to make an entry in the .got.plt section, which
8250 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 8251 if (is_iplt_entry)
8252 arm_plt->got_offset = sgotplt->size;
8253 else
8254 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 8255 sgotplt->size += 4;
8256 }
8257}
8258
b38cadfb
NC		 8259static bfd_vma
8260arm_movw_immediate (bfd_vma value)
8261{
8262 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
8263}
8264
8265static bfd_vma
8266arm_movt_immediate (bfd_vma value)
8267{
8268 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
8269}
8270
34e77a92
RS		 8271/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
8272 the entry lives in .iplt and resolves to (*SYM_VALUE)().
8273 Otherwise, DYNINDX is the index of the symbol in the dynamic
8274 symbol table and SYM_VALUE is undefined.
8275
8276 ROOT_PLT points to the offset of the PLT entry from the start of its
8277 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 8278 bookkeeping information.
34e77a92 8279
57460bcf
NC		 8280 Returns FALSE if there was a problem. */
8281
8282static bfd_boolean
34e77a92
RS		 8283elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
8284 union gotplt_union *root_plt,
8285 struct arm_plt_info *arm_plt,
8286 int dynindx, bfd_vma sym_value)
8287{
8288 struct elf32_arm_link_hash_table *htab;
8289 asection *sgot;
8290 asection *splt;
8291 asection *srel;
8292 bfd_byte *loc;
8293 bfd_vma plt_index;
8294 Elf_Internal_Rela rel;
8295 bfd_vma plt_header_size;
8296 bfd_vma got_header_size;
8297
8298 htab = elf32_arm_hash_table (info);
8299
8300 /* Pick the appropriate sections and sizes. */
8301 if (dynindx == -1)
8302 {
8303 splt = htab->root.iplt;
8304 sgot = htab->root.igotplt;
8305 srel = htab->root.irelplt;
8306
8307 /* There are no reserved entries in .igot.plt, and no special
8308 first entry in .iplt. */
8309 got_header_size = 0;
8310 plt_header_size = 0;
8311 }
8312 else
8313 {
8314 splt = htab->root.splt;
8315 sgot = htab->root.sgotplt;
8316 srel = htab->root.srelplt;
8317
8318 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
8319 plt_header_size = htab->plt_header_size;
8320 }
8321 BFD_ASSERT (splt != NULL && srel != NULL);
8322
8323 /* Fill in the entry in the procedure linkage table. */
8324 if (htab->symbian_p)
8325 {
8326 BFD_ASSERT (dynindx >= 0);
8327 put_arm_insn (htab, output_bfd,
8328 elf32_arm_symbian_plt_entry[0],
8329 splt->contents + root_plt->offset);
8330 bfd_put_32 (output_bfd,
8331 elf32_arm_symbian_plt_entry[1],
8332 splt->contents + root_plt->offset + 4);
8333
8334 /* Fill in the entry in the .rel.plt section. */
8335 rel.r_offset = (splt->output_section->vma
8336 + splt->output_offset
8337 + root_plt->offset + 4);
8338 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
8339
8340 /* Get the index in the procedure linkage table which
8341 corresponds to this symbol. This is the index of this symbol
8342 in all the symbols for which we are making plt entries. The
8343 first entry in the procedure linkage table is reserved. */
8344 plt_index = ((root_plt->offset - plt_header_size)
8345 / htab->plt_entry_size);
8346 }
8347 else
8348 {
8349 bfd_vma got_offset, got_address, plt_address;
8350 bfd_vma got_displacement, initial_got_entry;
8351 bfd_byte * ptr;
8352
8353 BFD_ASSERT (sgot != NULL);
8354
8355 /* Get the offset into the .(i)got.plt table of the entry that
8356 corresponds to this function. */
8357 got_offset = (arm_plt->got_offset & -2);
8358
8359 /* Get the index in the procedure linkage table which
8360 corresponds to this symbol. This is the index of this symbol
8361 in all the symbols for which we are making plt entries.
8362 After the reserved .got.plt entries, all symbols appear in
8363 the same order as in .plt. */
8364 plt_index = (got_offset - got_header_size) / 4;
8365
8366 /* Calculate the address of the GOT entry. */
8367 got_address = (sgot->output_section->vma
8368 + sgot->output_offset
8369 + got_offset);
8370
8371 /* ...and the address of the PLT entry. */
8372 plt_address = (splt->output_section->vma
8373 + splt->output_offset
8374 + root_plt->offset);
8375
8376 ptr = splt->contents + root_plt->offset;
0e1862bb 8377 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 8378 {
8379 unsigned int i;
8380 bfd_vma val;
8381
8382 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
8383 {
8384 val = elf32_arm_vxworks_shared_plt_entry[i];
8385 if (i == 2)
8386 val |= got_address - sgot->output_section->vma;
8387 if (i == 5)
8388 val |= plt_index * RELOC_SIZE (htab);
8389 if (i == 2 || i == 5)
8390 bfd_put_32 (output_bfd, val, ptr);
8391 else
8392 put_arm_insn (htab, output_bfd, val, ptr);
8393 }
8394 }
8395 else if (htab->vxworks_p)
8396 {
8397 unsigned int i;
8398 bfd_vma val;
8399
8400 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
8401 {
8402 val = elf32_arm_vxworks_exec_plt_entry[i];
8403 if (i == 2)
8404 val |= got_address;
8405 if (i == 4)
8406 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
8407 if (i == 5)
8408 val |= plt_index * RELOC_SIZE (htab);
8409 if (i == 2 || i == 5)
8410 bfd_put_32 (output_bfd, val, ptr);
8411 else
8412 put_arm_insn (htab, output_bfd, val, ptr);
8413 }
8414
8415 loc = (htab->srelplt2->contents
8416 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
8417
8418 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
8419 referencing the GOT for this PLT entry. */
8420 rel.r_offset = plt_address + 8;
8421 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
8422 rel.r_addend = got_offset;
8423 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8424 loc += RELOC_SIZE (htab);
8425
8426 /* Create the R_ARM_ABS32 relocation referencing the
8427 beginning of the PLT for this GOT entry. */
8428 rel.r_offset = got_address;
8429 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
8430 rel.r_addend = 0;
8431 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8432 }
b38cadfb
NC		 8433 else if (htab->nacl_p)
8434 {
8435 /* Calculate the displacement between the PLT slot and the
8436 common tail that's part of the special initial PLT slot. */
6034aab8 8437 int32_t tail_displacement
b38cadfb
NC		 8438 = ((splt->output_section->vma + splt->output_offset
8439 + ARM_NACL_PLT_TAIL_OFFSET)
8440 - (plt_address + htab->plt_entry_size + 4));
8441 BFD_ASSERT ((tail_displacement & 3) == 0);
8442 tail_displacement >>= 2;
8443
8444 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
8445 || (-tail_displacement & 0xff000000) == 0);
8446
8447 /* Calculate the displacement between the PLT slot and the entry
8448 in the GOT. The offset accounts for the value produced by
8449 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 8450 got_displacement = (got_address
99059e56 8451 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 8452
8453 /* NaCl does not support interworking at all. */
8454 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
8455
8456 put_arm_insn (htab, output_bfd,
8457 elf32_arm_nacl_plt_entry[0]
8458 | arm_movw_immediate (got_displacement),
8459 ptr + 0);
8460 put_arm_insn (htab, output_bfd,
8461 elf32_arm_nacl_plt_entry[1]
8462 | arm_movt_immediate (got_displacement),
8463 ptr + 4);
8464 put_arm_insn (htab, output_bfd,
8465 elf32_arm_nacl_plt_entry[2],
8466 ptr + 8);
8467 put_arm_insn (htab, output_bfd,
8468 elf32_arm_nacl_plt_entry[3]
8469 | (tail_displacement & 0x00ffffff),
8470 ptr + 12);
8471 }
57460bcf
NC		 8472 else if (using_thumb_only (htab))
8473 {
eed94f8f 8474 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 8475 if (!using_thumb2 (htab))
eed94f8f
NC		 8476 {
8477 /* FIXME: We ought to be able to generate thumb-1 PLT
8478 instructions... */
8479 _bfd_error_handler (_("%B: Warning: thumb-1 mode PLT generation not currently supported"),
8480 output_bfd);
8481 return FALSE;
8482 }
57460bcf 8483
eed94f8f
NC		 8484 /* Calculate the displacement between the PLT slot and the entry in
8485 the GOT. The 12-byte offset accounts for the value produced by
8486 adding to pc in the 3rd instruction of the PLT stub. */
8487 got_displacement = got_address - (plt_address + 12);
8488
8489 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
8490 instead of 'put_thumb_insn'. */
8491 put_arm_insn (htab, output_bfd,
8492 elf32_thumb2_plt_entry[0]
8493 | ((got_displacement & 0x000000ff) << 16)
8494 | ((got_displacement & 0x00000700) << 20)
8495 | ((got_displacement & 0x00000800) >> 1)
8496 | ((got_displacement & 0x0000f000) >> 12),
8497 ptr + 0);
8498 put_arm_insn (htab, output_bfd,
8499 elf32_thumb2_plt_entry[1]
8500 | ((got_displacement & 0x00ff0000) )
8501 | ((got_displacement & 0x07000000) << 4)
8502 | ((got_displacement & 0x08000000) >> 17)
8503 | ((got_displacement & 0xf0000000) >> 28),
8504 ptr + 4);
8505 put_arm_insn (htab, output_bfd,
8506 elf32_thumb2_plt_entry[2],
8507 ptr + 8);
8508 put_arm_insn (htab, output_bfd,
8509 elf32_thumb2_plt_entry[3],
8510 ptr + 12);
57460bcf 8511 }
34e77a92
RS		 8512 else
8513 {
8514 /* Calculate the displacement between the PLT slot and the
8515 entry in the GOT. The eight-byte offset accounts for the
8516 value produced by adding to pc in the first instruction
8517 of the PLT stub. */
8518 got_displacement = got_address - (plt_address + 8);
8519
34e77a92
RS		 8520 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
8521 {
8522 put_thumb_insn (htab, output_bfd,
8523 elf32_arm_plt_thumb_stub[0], ptr - 4);
8524 put_thumb_insn (htab, output_bfd,
8525 elf32_arm_plt_thumb_stub[1], ptr - 2);
8526 }
8527
1db37fe6
YG		 8528 if (!elf32_arm_use_long_plt_entry)
8529 {
8530 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
8531
8532 put_arm_insn (htab, output_bfd,
8533 elf32_arm_plt_entry_short[0]
8534 | ((got_displacement & 0x0ff00000) >> 20),
8535 ptr + 0);
8536 put_arm_insn (htab, output_bfd,
8537 elf32_arm_plt_entry_short[1]
8538 | ((got_displacement & 0x000ff000) >> 12),
8539 ptr+ 4);
8540 put_arm_insn (htab, output_bfd,
8541 elf32_arm_plt_entry_short[2]
8542 | (got_displacement & 0x00000fff),
8543 ptr + 8);
34e77a92 8544#ifdef FOUR_WORD_PLT
1db37fe6 8545 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 8546#endif
1db37fe6
YG		 8547 }
8548 else
8549 {
8550 put_arm_insn (htab, output_bfd,
8551 elf32_arm_plt_entry_long[0]
8552 | ((got_displacement & 0xf0000000) >> 28),
8553 ptr + 0);
8554 put_arm_insn (htab, output_bfd,
8555 elf32_arm_plt_entry_long[1]
8556 | ((got_displacement & 0x0ff00000) >> 20),
8557 ptr + 4);
8558 put_arm_insn (htab, output_bfd,
8559 elf32_arm_plt_entry_long[2]
8560 | ((got_displacement & 0x000ff000) >> 12),
8561 ptr+ 8);
8562 put_arm_insn (htab, output_bfd,
8563 elf32_arm_plt_entry_long[3]
8564 | (got_displacement & 0x00000fff),
8565 ptr + 12);
8566 }
34e77a92
RS		 8567 }
8568
8569 /* Fill in the entry in the .rel(a).(i)plt section. */
8570 rel.r_offset = got_address;
8571 rel.r_addend = 0;
8572 if (dynindx == -1)
8573 {
8574 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
8575 The dynamic linker or static executable then calls SYM_VALUE
8576 to determine the correct run-time value of the .igot.plt entry. */
8577 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
8578 initial_got_entry = sym_value;
8579 }
8580 else
8581 {
8582 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
8583 initial_got_entry = (splt->output_section->vma
8584 + splt->output_offset);
8585 }
8586
8587 /* Fill in the entry in the global offset table. */
8588 bfd_put_32 (output_bfd, initial_got_entry,
8589 sgot->contents + got_offset);
8590 }
8591
aba8c3de
WN		 8592 if (dynindx == -1)
8593 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
8594 else
8595 {
8596 loc = srel->contents + plt_index * RELOC_SIZE (htab);
8597 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8598 }
57460bcf
NC		 8599
8600 return TRUE;
34e77a92
RS		 8601}
8602
eb043451
PB		 8603/* Some relocations map to different relocations depending on the
8604 target. Return the real relocation. */
8029a119 8605
eb043451
PB		 8606static int
8607arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
8608 int r_type)
8609{
8610 switch (r_type)
8611 {
8612 case R_ARM_TARGET1:
8613 if (globals->target1_is_rel)
8614 return R_ARM_REL32;
8615 else
8616 return R_ARM_ABS32;
8617
8618 case R_ARM_TARGET2:
8619 return globals->target2_reloc;
8620
8621 default:
8622 return r_type;
8623 }
8624}
eb043451 8625
ba93b8ac
DJ		 8626/* Return the base VMA address which should be subtracted from real addresses
8627 when resolving @dtpoff relocation.
8628 This is PT_TLS segment p_vaddr. */
8629
8630static bfd_vma
8631dtpoff_base (struct bfd_link_info *info)
8632{
8633 /* If tls_sec is NULL, we should have signalled an error already. */
8634 if (elf_hash_table (info)->tls_sec == NULL)
8635 return 0;
8636 return elf_hash_table (info)->tls_sec->vma;
8637}
8638
8639/* Return the relocation value for @tpoff relocation
8640 if STT_TLS virtual address is ADDRESS. */
8641
8642static bfd_vma
8643tpoff (struct bfd_link_info *info, bfd_vma address)
8644{
8645 struct elf_link_hash_table *htab = elf_hash_table (info);
8646 bfd_vma base;
8647
8648 /* If tls_sec is NULL, we should have signalled an error already. */
8649 if (htab->tls_sec == NULL)
8650 return 0;
8651 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
8652 return address - htab->tls_sec->vma + base;
8653}
8654
00a97672
RS		 8655/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
8656 VALUE is the relocation value. */
8657
8658static bfd_reloc_status_type
8659elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
8660{
8661 if (value > 0xfff)
8662 return bfd_reloc_overflow;
8663
8664 value |= bfd_get_32 (abfd, data) & 0xfffff000;
8665 bfd_put_32 (abfd, value, data);
8666 return bfd_reloc_ok;
8667}
8668
0855e32b
NS		 8669/* Handle TLS relaxations. Relaxing is possible for symbols that use
8670 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
8671 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
8672
8673 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
8674 is to then call final_link_relocate. Return other values in the
62672b10
NS		 8675 case of error.
8676
8677 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
8678 the pre-relaxed code. It would be nice if the relocs were updated
8679 to match the optimization. */
0855e32b 8680
b38cadfb 8681static bfd_reloc_status_type
0855e32b 8682elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 8683 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 8684 Elf_Internal_Rela *rel, unsigned long is_local)
8685{
8686 unsigned long insn;
b38cadfb 8687
0855e32b
NS		 8688 switch (ELF32_R_TYPE (rel->r_info))
8689 {
8690 default:
8691 return bfd_reloc_notsupported;
b38cadfb 8692
0855e32b
NS		 8693 case R_ARM_TLS_GOTDESC:
8694 if (is_local)
8695 insn = 0;
8696 else
8697 {
8698 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
8699 if (insn & 1)
8700 insn -= 5; /* THUMB */
8701 else
8702 insn -= 8; /* ARM */
8703 }
8704 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
8705 return bfd_reloc_continue;
8706
8707 case R_ARM_THM_TLS_DESCSEQ:
8708 /* Thumb insn. */
8709 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
8710 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
8711 {
8712 if (is_local)
8713 /* nop */
8714 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8715 }
8716 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
8717 {
8718 if (is_local)
8719 /* nop */
8720 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8721 else
8722 /* ldr rx,[ry] */
8723 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
8724 }
8725 else if ((insn & 0xff87) == 0x4780) /* blx rx */
8726 {
8727 if (is_local)
8728 /* nop */
8729 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8730 else
8731 /* mov r0, rx */
8732 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
8733 contents + rel->r_offset);
8734 }
8735 else
8736 {
8737 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
8738 /* It's a 32 bit instruction, fetch the rest of it for
8739 error generation. */
8740 insn = (insn << 16)
8741 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
8742 (*_bfd_error_handler)
8743 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' in TLS trampoline"),
8744 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
8745 return bfd_reloc_notsupported;
8746 }
8747 break;
b38cadfb 8748
0855e32b
NS		 8749 case R_ARM_TLS_DESCSEQ:
8750 /* arm insn. */
8751 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
8752 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
8753 {
8754 if (is_local)
8755 /* mov rx, ry */
8756 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
8757 contents + rel->r_offset);
8758 }
8759 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
8760 {
8761 if (is_local)
8762 /* nop */
8763 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
8764 else
8765 /* ldr rx,[ry] */
8766 bfd_put_32 (input_bfd, insn & 0xfffff000,
8767 contents + rel->r_offset);
8768 }
8769 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
8770 {
8771 if (is_local)
8772 /* nop */
8773 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
8774 else
8775 /* mov r0, rx */
8776 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
8777 contents + rel->r_offset);
8778 }
8779 else
8780 {
8781 (*_bfd_error_handler)
8782 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' in TLS trampoline"),
8783 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
8784 return bfd_reloc_notsupported;
8785 }
8786 break;
8787
8788 case R_ARM_TLS_CALL:
8789 /* GD->IE relaxation, turn the instruction into 'nop' or
8790 'ldr r0, [pc,r0]' */
8791 insn = is_local ? 0xe1a00000 : 0xe79f0000;
8792 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
8793 break;
b38cadfb 8794
0855e32b 8795 case R_ARM_THM_TLS_CALL:
6a631e86 8796 /* GD->IE relaxation. */
0855e32b
NS		 8797 if (!is_local)
8798 /* add r0,pc; ldr r0, [r0] */
8799 insn = 0x44786800;
8800 else if (arch_has_thumb2_nop (globals))
8801 /* nop.w */
8802 insn = 0xf3af8000;
8803 else
8804 /* nop; nop */
8805 insn = 0xbf00bf00;
b38cadfb 8806
0855e32b
NS		 8807 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
8808 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
8809 break;
8810 }
8811 return bfd_reloc_ok;
8812}
8813
4962c51a
MS		 8814/* For a given value of n, calculate the value of G_n as required to
8815 deal with group relocations. We return it in the form of an
8816 encoded constant-and-rotation, together with the final residual. If n is
8817 specified as less than zero, then final_residual is filled with the
8818 input value and no further action is performed. */
8819
8820static bfd_vma
8821calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
8822{
8823 int current_n;
8824 bfd_vma g_n;
8825 bfd_vma encoded_g_n = 0;
8826 bfd_vma residual = value; /* Also known as Y_n. */
8827
8828 for (current_n = 0; current_n <= n; current_n++)
8829 {
8830 int shift;
8831
8832 /* Calculate which part of the value to mask. */
8833 if (residual == 0)
99059e56 8834 shift = 0;
4962c51a 8835 else
99059e56
RM		 8836 {
8837 int msb;
8838
8839 /* Determine the most significant bit in the residual and
8840 align the resulting value to a 2-bit boundary. */
8841 for (msb = 30; msb >= 0; msb -= 2)
8842 if (residual & (3 << msb))
8843 break;
8844
8845 /* The desired shift is now (msb - 6), or zero, whichever
8846 is the greater. */
8847 shift = msb - 6;
8848 if (shift < 0)
8849 shift = 0;
8850 }
4962c51a
MS		 8851
8852 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
8853 g_n = residual & (0xff << shift);
8854 encoded_g_n = (g_n >> shift)
99059e56 8855 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 8856
8857 /* Calculate the residual for the next time around. */
8858 residual &= ~g_n;
8859 }
8860
8861 *final_residual = residual;
8862
8863 return encoded_g_n;
8864}
8865
8866/* Given an ARM instruction, determine whether it is an ADD or a SUB.
8867 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 8868
4962c51a 8869static int
906e58ca 8870identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 8871{
8872 int opcode = insn & 0x1e00000;
8873
8874 if (opcode == 1 << 23) /* ADD */
8875 return 1;
8876
8877 if (opcode == 1 << 22) /* SUB */
8878 return -1;
8879
8880 return 0;
8881}
8882
252b5132 8883/* Perform a relocation as part of a final link. */
9b485d32 8884
252b5132 8885static bfd_reloc_status_type
57e8b36a
NC		 8886elf32_arm_final_link_relocate (reloc_howto_type * howto,
8887 bfd * input_bfd,
8888 bfd * output_bfd,
8889 asection * input_section,
8890 bfd_byte * contents,
8891 Elf_Internal_Rela * rel,
8892 bfd_vma value,
8893 struct bfd_link_info * info,
8894 asection * sym_sec,
8895 const char * sym_name,
34e77a92
RS		 8896 unsigned char st_type,
8897 enum arm_st_branch_type branch_type,
0945cdfd 8898 struct elf_link_hash_entry * h,
f2a9dd69 8899 bfd_boolean * unresolved_reloc_p,
8029a119 8900 char ** error_message)
252b5132
RH		 8901{
8902 unsigned long r_type = howto->type;
8903 unsigned long r_symndx;
8904 bfd_byte * hit_data = contents + rel->r_offset;
252b5132 8905 bfd_vma * local_got_offsets;
0855e32b 8906 bfd_vma * local_tlsdesc_gotents;
34e77a92
RS		 8907 asection * sgot;
8908 asection * splt;
252b5132 8909 asection * sreloc = NULL;
362d30a1 8910 asection * srelgot;
252b5132 8911 bfd_vma addend;
ba96a88f 8912 bfd_signed_vma signed_addend;
34e77a92
RS		 8913 unsigned char dynreloc_st_type;
8914 bfd_vma dynreloc_value;
ba96a88f 8915 struct elf32_arm_link_hash_table * globals;
34e77a92
RS		 8916 struct elf32_arm_link_hash_entry *eh;
8917 union gotplt_union *root_plt;
8918 struct arm_plt_info *arm_plt;
8919 bfd_vma plt_offset;
8920 bfd_vma gotplt_offset;
8921 bfd_boolean has_iplt_entry;
f21f3fe0 8922
9c504268 8923 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 8924 if (globals == NULL)
8925 return bfd_reloc_notsupported;
9c504268 8926
0ffa91dd
NC		 8927 BFD_ASSERT (is_arm_elf (input_bfd));
8928
8929 /* Some relocation types map to different relocations depending on the
9c504268 8930 target. We pick the right one here. */
eb043451 8931 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 8932
8933 /* It is possible to have linker relaxations on some TLS access
8934 models. Update our information here. */
8935 r_type = elf32_arm_tls_transition (info, r_type, h);
8936
eb043451
PB		 8937 if (r_type != howto->type)
8938 howto = elf32_arm_howto_from_type (r_type);
9c504268 8939
34e77a92 8940 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 8941 sgot = globals->root.sgot;
252b5132 8942 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 8943 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
8944
34e77a92
RS		 8945 if (globals->root.dynamic_sections_created)
8946 srelgot = globals->root.srelgot;
8947 else
8948 srelgot = NULL;
8949
252b5132
RH		 8950 r_symndx = ELF32_R_SYM (rel->r_info);
8951
4e7fd91e 8952 if (globals->use_rel)
ba96a88f 8953 {
4e7fd91e
PB		 8954 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
8955
8956 if (addend & ((howto->src_mask + 1) >> 1))
8957 {
8958 signed_addend = -1;
8959 signed_addend &= ~ howto->src_mask;
8960 signed_addend |= addend;
8961 }
8962 else
8963 signed_addend = addend;
ba96a88f
NC		 8964 }
8965 else
4e7fd91e 8966 addend = signed_addend = rel->r_addend;
f21f3fe0 8967
39f21624
NC		 8968 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
8969 are resolving a function call relocation. */
8970 if (using_thumb_only (globals)
8971 && (r_type == R_ARM_THM_CALL
8972 || r_type == R_ARM_THM_JUMP24)
8973 && branch_type == ST_BRANCH_TO_ARM)
8974 branch_type = ST_BRANCH_TO_THUMB;
8975
34e77a92
RS		 8976 /* Record the symbol information that should be used in dynamic
8977 relocations. */
8978 dynreloc_st_type = st_type;
8979 dynreloc_value = value;
8980 if (branch_type == ST_BRANCH_TO_THUMB)
8981 dynreloc_value |= 1;
8982
8983 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
8984 VALUE appropriately for relocations that we resolve at link time. */
8985 has_iplt_entry = FALSE;
8986 if (elf32_arm_get_plt_info (input_bfd, eh, r_symndx, &root_plt, &arm_plt)
8987 && root_plt->offset != (bfd_vma) -1)
8988 {
8989 plt_offset = root_plt->offset;
8990 gotplt_offset = arm_plt->got_offset;
8991
8992 if (h == NULL || eh->is_iplt)
8993 {
8994 has_iplt_entry = TRUE;
8995 splt = globals->root.iplt;
8996
8997 /* Populate .iplt entries here, because not all of them will
8998 be seen by finish_dynamic_symbol. The lower bit is set if
8999 we have already populated the entry. */
9000 if (plt_offset & 1)
9001 plt_offset--;
9002 else
9003 {
57460bcf
NC		 9004 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
9005 -1, dynreloc_value))
9006 root_plt->offset |= 1;
9007 else
9008 return bfd_reloc_notsupported;
34e77a92
RS		 9009 }
9010
9011 /* Static relocations always resolve to the .iplt entry. */
9012 st_type = STT_FUNC;
9013 value = (splt->output_section->vma
9014 + splt->output_offset
9015 + plt_offset);
9016 branch_type = ST_BRANCH_TO_ARM;
9017
9018 /* If there are non-call relocations that resolve to the .iplt
9019 entry, then all dynamic ones must too. */
9020 if (arm_plt->noncall_refcount != 0)
9021 {
9022 dynreloc_st_type = st_type;
9023 dynreloc_value = value;
9024 }
9025 }
9026 else
9027 /* We populate the .plt entry in finish_dynamic_symbol. */
9028 splt = globals->root.splt;
9029 }
9030 else
9031 {
9032 splt = NULL;
9033 plt_offset = (bfd_vma) -1;
9034 gotplt_offset = (bfd_vma) -1;
9035 }
9036
252b5132
RH		 9037 switch (r_type)
9038 {
9039 case R_ARM_NONE:
28a094c2
DJ		 9040 /* We don't need to find a value for this symbol. It's just a
9041 marker. */
9042 *unresolved_reloc_p = FALSE;
252b5132
RH		 9043 return bfd_reloc_ok;
9044
00a97672
RS		 9045 case R_ARM_ABS12:
9046 if (!globals->vxworks_p)
9047 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
9048
252b5132
RH		 9049 case R_ARM_PC24:
9050 case R_ARM_ABS32:
bb224fc3 9051 case R_ARM_ABS32_NOI:
252b5132 9052 case R_ARM_REL32:
bb224fc3 9053 case R_ARM_REL32_NOI:
5b5bb741
PB		 9054 case R_ARM_CALL:
9055 case R_ARM_JUMP24:
dfc5f959 9056 case R_ARM_XPC25:
eb043451 9057 case R_ARM_PREL31:
7359ea65 9058 case R_ARM_PLT32:
7359ea65
DJ		 9059 /* Handle relocations which should use the PLT entry. ABS32/REL32
9060 will use the symbol's value, which may point to a PLT entry, but we
9061 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 9062 branches in this object should go to it, except if the PLT is too
9063 far away, in which case a long branch stub should be inserted. */
bb224fc3 9064 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 9065 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 9066 && r_type != R_ARM_CALL
9067 && r_type != R_ARM_JUMP24
9068 && r_type != R_ARM_PLT32)
34e77a92 9069 && plt_offset != (bfd_vma) -1)
7359ea65 9070 {
34e77a92
RS		 9071 /* If we've created a .plt section, and assigned a PLT entry
9072 to this function, it must either be a STT_GNU_IFUNC reference
9073 or not be known to bind locally. In other cases, we should
9074 have cleared the PLT entry by now. */
9075 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 9076
9077 value = (splt->output_section->vma
9078 + splt->output_offset
34e77a92 9079 + plt_offset);
0945cdfd 9080 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 9081 return _bfd_final_link_relocate (howto, input_bfd, input_section,
9082 contents, rel->r_offset, value,
00a97672 9083 rel->r_addend);
7359ea65
DJ		 9084 }
9085
67687978
PB		 9086 /* When generating a shared object or relocatable executable, these
9087 relocations are copied into the output file to be resolved at
9088 run time. */
0e1862bb
L		 9089 if ((bfd_link_pic (info)
9090 || globals->root.is_relocatable_executable)
7359ea65 9091 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 9092 && !(globals->vxworks_p
3348747a
NS		 9093 && strcmp (input_section->output_section->name,
9094 ".tls_vars") == 0)
bb224fc3 9095 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 9096 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 9097 && !(input_bfd == globals->stub_bfd
9098 && strstr (input_section->name, STUB_SUFFIX))
7359ea65
DJ		 9099 && (h == NULL
9100 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
9101 || h->root.type != bfd_link_hash_undefweak)
9102 && r_type != R_ARM_PC24
5b5bb741
PB		 9103 && r_type != R_ARM_CALL
9104 && r_type != R_ARM_JUMP24
ee06dc07 9105 && r_type != R_ARM_PREL31
7359ea65 9106 && r_type != R_ARM_PLT32)
252b5132 9107 {
947216bf 9108 Elf_Internal_Rela outrel;
b34976b6 9109 bfd_boolean skip, relocate;
f21f3fe0 9110
52db4ec2
JW		 9111 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
9112 && !h->def_regular)
9113 {
9114 char *v = _("shared object");
9115
0e1862bb 9116 if (bfd_link_executable (info))
52db4ec2
JW		 9117 v = _("PIE executable");
9118
9119 (*_bfd_error_handler)
9120 (_("%B: relocation %s against external or undefined symbol `%s'"
9121 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
9122 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
9123 return bfd_reloc_notsupported;
9124 }
9125
0945cdfd
DJ		 9126 *unresolved_reloc_p = FALSE;
9127
34e77a92 9128 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 9129 {
83bac4b0
NC		 9130 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
9131 ! globals->use_rel);
f21f3fe0 9132
83bac4b0 9133 if (sreloc == NULL)
252b5132 9134 return bfd_reloc_notsupported;
252b5132 9135 }
f21f3fe0 9136
b34976b6
AM		 9137 skip = FALSE;
9138 relocate = FALSE;
f21f3fe0 9139
00a97672 9140 outrel.r_addend = addend;
c629eae0
JJ		 9141 outrel.r_offset =
9142 _bfd_elf_section_offset (output_bfd, info, input_section,
9143 rel->r_offset);
9144 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 9145 skip = TRUE;
0bb2d96a 9146 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 9147 skip = TRUE, relocate = TRUE;
252b5132
RH		 9148 outrel.r_offset += (input_section->output_section->vma
9149 + input_section->output_offset);
f21f3fe0 9150
252b5132 9151 if (skip)
0bb2d96a 9152 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 9153 else if (h != NULL
9154 && h->dynindx != -1
0e1862bb 9155 && (!bfd_link_pic (info)
a496fbc8 9156 || !SYMBOLIC_BIND (info, h)
f5385ebf 9157 || !h->def_regular))
5e681ec4 9158 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 9159 else
9160 {
a16385dc
MM		 9161 int symbol;
9162
5e681ec4 9163 /* This symbol is local, or marked to become local. */
34e77a92 9164 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 9165 if (globals->symbian_p)
6366ff1e 9166 {
74541ad4
AM		 9167 asection *osec;
9168
6366ff1e
MM		 9169 /* On Symbian OS, the data segment and text segement
9170 can be relocated independently. Therefore, we
9171 must indicate the segment to which this
9172 relocation is relative. The BPABI allows us to
9173 use any symbol in the right segment; we just use
9174 the section symbol as it is convenient. (We
9175 cannot use the symbol given by "h" directly as it
74541ad4
AM		 9176 will not appear in the dynamic symbol table.)
9177
9178 Note that the dynamic linker ignores the section
9179 symbol value, so we don't subtract osec->vma
9180 from the emitted reloc addend. */
10dbd1f3 9181 if (sym_sec)
74541ad4 9182 osec = sym_sec->output_section;
10dbd1f3 9183 else
74541ad4
AM		 9184 osec = input_section->output_section;
9185 symbol = elf_section_data (osec)->dynindx;
9186 if (symbol == 0)
9187 {
9188 struct elf_link_hash_table *htab = elf_hash_table (info);
9189
9190 if ((osec->flags & SEC_READONLY) == 0
9191 && htab->data_index_section != NULL)
9192 osec = htab->data_index_section;
9193 else
9194 osec = htab->text_index_section;
9195 symbol = elf_section_data (osec)->dynindx;
9196 }
6366ff1e
MM		 9197 BFD_ASSERT (symbol != 0);
9198 }
a16385dc
MM		 9199 else
9200 /* On SVR4-ish systems, the dynamic loader cannot
9201 relocate the text and data segments independently,
9202 so the symbol does not matter. */
9203 symbol = 0;
34e77a92
RS		 9204 if (dynreloc_st_type == STT_GNU_IFUNC)
9205 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
9206 to the .iplt entry. Instead, every non-call reference
9207 must use an R_ARM_IRELATIVE relocation to obtain the
9208 correct run-time address. */
9209 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
9210 else
9211 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 9212 if (globals->use_rel)
9213 relocate = TRUE;
9214 else
34e77a92 9215 outrel.r_addend += dynreloc_value;
252b5132 9216 }
f21f3fe0 9217
47beaa6a 9218 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 9219
f21f3fe0 9220 /* If this reloc is against an external symbol, we do not want to
252b5132 9221 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 9222 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 9223 if (! relocate)
9224 return bfd_reloc_ok;
9a5aca8c 9225
f21f3fe0 9226 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 9227 contents, rel->r_offset,
9228 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 9229 }
9230 else switch (r_type)
9231 {
00a97672
RS		 9232 case R_ARM_ABS12:
9233 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
9234
dfc5f959 9235 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 9236 case R_ARM_CALL:
9237 case R_ARM_JUMP24:
8029a119 9238 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 9239 case R_ARM_PLT32:
906e58ca 9240 {
906e58ca
NC		 9241 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
9242
dfc5f959 9243 if (r_type == R_ARM_XPC25)
252b5132 9244 {
dfc5f959
NC		 9245 /* Check for Arm calling Arm function. */
9246 /* FIXME: Should we translate the instruction into a BL
9247 instruction instead ? */
35fc36a8 9248 if (branch_type != ST_BRANCH_TO_THUMB)
d003868e
AM		 9249 (*_bfd_error_handler)
9250 (_("\%B: Warning: Arm BLX instruction targets Arm function '%s'."),
9251 input_bfd,
9252 h ? h->root.root.string : "(local)");
dfc5f959 9253 }
155d87d7 9254 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 9255 {
9256 /* Check for Arm calling Thumb function. */
35fc36a8 9257 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 9258 {
f2a9dd69
DJ		 9259 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
9260 output_bfd, input_section,
9261 hit_data, sym_sec, rel->r_offset,
9262 signed_addend, value,
9263 error_message))
9264 return bfd_reloc_ok;
9265 else
9266 return bfd_reloc_dangerous;
dfc5f959 9267 }
252b5132 9268 }
ba96a88f 9269
906e58ca 9270 /* Check if a stub has to be inserted because the
8029a119 9271 destination is too far or we are changing mode. */
155d87d7
CL		 9272 if ( r_type == R_ARM_CALL
9273 || r_type == R_ARM_JUMP24
9274 || r_type == R_ARM_PLT32)
906e58ca 9275 {
fe33d2fa
CL		 9276 enum elf32_arm_stub_type stub_type = arm_stub_none;
9277 struct elf32_arm_link_hash_entry *hash;
9278
9279 hash = (struct elf32_arm_link_hash_entry *) h;
9280 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 9281 st_type, &branch_type,
9282 hash, value, sym_sec,
fe33d2fa 9283 input_bfd, sym_name);
5fa9e92f 9284
fe33d2fa 9285 if (stub_type != arm_stub_none)
906e58ca
NC		 9286 {
9287 /* The target is out of reach, so redirect the
9288 branch to the local stub for this function. */
906e58ca
NC		 9289 stub_entry = elf32_arm_get_stub_entry (input_section,
9290 sym_sec, h,
fe33d2fa
CL		 9291 rel, globals,
9292 stub_type);
9cd3e4e5
NC		 9293 {
9294 if (stub_entry != NULL)
9295 value = (stub_entry->stub_offset
9296 + stub_entry->stub_sec->output_offset
9297 + stub_entry->stub_sec->output_section->vma);
9298
9299 if (plt_offset != (bfd_vma) -1)
9300 *unresolved_reloc_p = FALSE;
9301 }
906e58ca 9302 }
fe33d2fa
CL		 9303 else
9304 {
9305 /* If the call goes through a PLT entry, make sure to
9306 check distance to the right destination address. */
34e77a92 9307 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 9308 {
9309 value = (splt->output_section->vma
9310 + splt->output_offset
34e77a92 9311 + plt_offset);
fe33d2fa
CL		 9312 *unresolved_reloc_p = FALSE;
9313 /* The PLT entry is in ARM mode, regardless of the
9314 target function. */
35fc36a8 9315 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 9316 }
9317 }
906e58ca
NC		 9318 }
9319
dea514f5
PB		 9320 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
9321 where:
9322 S is the address of the symbol in the relocation.
9323 P is address of the instruction being relocated.
9324 A is the addend (extracted from the instruction) in bytes.
9325
9326 S is held in 'value'.
9327 P is the base address of the section containing the
9328 instruction plus the offset of the reloc into that
9329 section, ie:
9330 (input_section->output_section->vma +
9331 input_section->output_offset +
9332 rel->r_offset).
9333 A is the addend, converted into bytes, ie:
9334 (signed_addend * 4)
9335
9336 Note: None of these operations have knowledge of the pipeline
9337 size of the processor, thus it is up to the assembler to
9338 encode this information into the addend. */
9339 value -= (input_section->output_section->vma
9340 + input_section->output_offset);
9341 value -= rel->r_offset;
4e7fd91e
PB		 9342 if (globals->use_rel)
9343 value += (signed_addend << howto->size);
9344 else
9345 /* RELA addends do not have to be adjusted by howto->size. */
9346 value += signed_addend;
23080146 9347
dcb5e6e6
NC		 9348 signed_addend = value;
9349 signed_addend >>= howto->rightshift;
9a5aca8c 9350
5ab79981 9351 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 9352 the next instruction unless a PLT entry will be created.
77b4f08f 9353 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 9354 The jump to the next instruction is optimized as a NOP depending
9355 on the architecture. */
ffcb4889 9356 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 9357 && plt_offset == (bfd_vma) -1)
77b4f08f 9358 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 9359 {
cd1dac3d
DG		 9360 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
9361
9362 if (arch_has_arm_nop (globals))
9363 value |= 0x0320f000;
9364 else
9365 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 9366 }
9367 else
59f2c4e7 9368 {
9b485d32 9369 /* Perform a signed range check. */
dcb5e6e6 9370 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 9371 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
9372 return bfd_reloc_overflow;
9a5aca8c 9373
5ab79981 9374 addend = (value & 2);
39b41c9c 9375
5ab79981
PB		 9376 value = (signed_addend & howto->dst_mask)
9377 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 9378
5ab79981
PB		 9379 if (r_type == R_ARM_CALL)
9380 {
155d87d7 9381 /* Set the H bit in the BLX instruction. */
35fc36a8 9382 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 9383 {
9384 if (addend)
9385 value |= (1 << 24);
9386 else
9387 value &= ~(bfd_vma)(1 << 24);
9388 }
9389
5ab79981 9390 /* Select the correct instruction (BL or BLX). */
906e58ca 9391 /* Only if we are not handling a BL to a stub. In this
8029a119 9392 case, mode switching is performed by the stub. */
35fc36a8 9393 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 9394 value |= (1 << 28);
63e1a0fc 9395 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 9396 {
9397 value &= ~(bfd_vma)(1 << 28);
9398 value |= (1 << 24);
9399 }
39b41c9c
PB		 9400 }
9401 }
906e58ca 9402 }
252b5132 9403 break;
f21f3fe0 9404
252b5132
RH		 9405 case R_ARM_ABS32:
9406 value += addend;
35fc36a8 9407 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 9408 value |= 1;
9409 break;
f21f3fe0 9410
bb224fc3
MS		 9411 case R_ARM_ABS32_NOI:
9412 value += addend;
9413 break;
9414
252b5132 9415 case R_ARM_REL32:
a8bc6c78 9416 value += addend;
35fc36a8 9417 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 9418 value |= 1;
252b5132 9419 value -= (input_section->output_section->vma
62efb346 9420 + input_section->output_offset + rel->r_offset);
252b5132 9421 break;
eb043451 9422
bb224fc3
MS		 9423 case R_ARM_REL32_NOI:
9424 value += addend;
9425 value -= (input_section->output_section->vma
9426 + input_section->output_offset + rel->r_offset);
9427 break;
9428
eb043451
PB		 9429 case R_ARM_PREL31:
9430 value -= (input_section->output_section->vma
9431 + input_section->output_offset + rel->r_offset);
9432 value += signed_addend;
9433 if (! h || h->root.type != bfd_link_hash_undefweak)
9434 {
8029a119 9435 /* Check for overflow. */
eb043451
PB		 9436 if ((value ^ (value >> 1)) & (1 << 30))
9437 return bfd_reloc_overflow;
9438 }
9439 value &= 0x7fffffff;
9440 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 9441 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 9442 value |= 1;
9443 break;
252b5132 9444 }
f21f3fe0 9445
252b5132
RH		 9446 bfd_put_32 (input_bfd, value, hit_data);
9447 return bfd_reloc_ok;
9448
9449 case R_ARM_ABS8:
fd0fd00c
MJ		 9450 /* PR 16202: Refectch the addend using the correct size. */
9451 if (globals->use_rel)
9452 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 9453 value += addend;
4e67d4ca
DG		 9454
9455 /* There is no way to tell whether the user intended to use a signed or
9456 unsigned addend. When checking for overflow we accept either,
9457 as specified by the AAELF. */
9458 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 9459 return bfd_reloc_overflow;
9460
9461 bfd_put_8 (input_bfd, value, hit_data);
9462 return bfd_reloc_ok;
9463
9464 case R_ARM_ABS16:
fd0fd00c
MJ		 9465 /* PR 16202: Refectch the addend using the correct size. */
9466 if (globals->use_rel)
9467 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 9468 value += addend;
9469
4e67d4ca
DG		 9470 /* See comment for R_ARM_ABS8. */
9471 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 9472 return bfd_reloc_overflow;
9473
9474 bfd_put_16 (input_bfd, value, hit_data);
9475 return bfd_reloc_ok;
9476
252b5132 9477 case R_ARM_THM_ABS5:
9b485d32 9478 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 9479 if (globals->use_rel)
9480 {
9481 /* Need to refetch addend. */
9482 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
9483 /* ??? Need to determine shift amount from operand size. */
9484 addend >>= howto->rightshift;
9485 }
252b5132
RH		 9486 value += addend;
9487
9488 /* ??? Isn't value unsigned? */
9489 if ((long) value > 0x1f || (long) value < -0x10)
9490 return bfd_reloc_overflow;
9491
9492 /* ??? Value needs to be properly shifted into place first. */
9493 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
9494 bfd_put_16 (input_bfd, value, hit_data);
9495 return bfd_reloc_ok;
9496
2cab6cc3
MS		 9497 case R_ARM_THM_ALU_PREL_11_0:
9498 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
9499 {
9500 bfd_vma insn;
9501 bfd_signed_vma relocation;
9502
9503 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 9504 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 9505
99059e56
RM		 9506 if (globals->use_rel)
9507 {
9508 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
9509 | ((insn & (1 << 26)) >> 15);
9510 if (insn & 0xf00000)
9511 signed_addend = -signed_addend;
9512 }
2cab6cc3
MS		 9513
9514 relocation = value + signed_addend;
79f08007 9515 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9516 + input_section->output_offset
9517 + rel->r_offset);
2cab6cc3 9518
b6518b38 9519 value = relocation;
2cab6cc3 9520
99059e56
RM		 9521 if (value >= 0x1000)
9522 return bfd_reloc_overflow;
2cab6cc3
MS		 9523
9524 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 9525 | ((value & 0x700) << 4)
9526 | ((value & 0x800) << 15);
9527 if (relocation < 0)
9528 insn |= 0xa00000;
2cab6cc3
MS		 9529
9530 bfd_put_16 (input_bfd, insn >> 16, hit_data);
9531 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
9532
99059e56 9533 return bfd_reloc_ok;
2cab6cc3
MS		 9534 }
9535
e1ec24c6
NC		 9536 case R_ARM_THM_PC8:
9537 /* PR 10073: This reloc is not generated by the GNU toolchain,
9538 but it is supported for compatibility with third party libraries
9539 generated by other compilers, specifically the ARM/IAR. */
9540 {
9541 bfd_vma insn;
9542 bfd_signed_vma relocation;
9543
9544 insn = bfd_get_16 (input_bfd, hit_data);
9545
99059e56 9546 if (globals->use_rel)
79f08007 9547 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 9548
9549 relocation = value + addend;
79f08007 9550 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9551 + input_section->output_offset
9552 + rel->r_offset);
e1ec24c6 9553
b6518b38 9554 value = relocation;
e1ec24c6
NC		 9555
9556 /* We do not check for overflow of this reloc. Although strictly
9557 speaking this is incorrect, it appears to be necessary in order
9558 to work with IAR generated relocs. Since GCC and GAS do not
9559 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
9560 a problem for them. */
9561 value &= 0x3fc;
9562
9563 insn = (insn & 0xff00) | (value >> 2);
9564
9565 bfd_put_16 (input_bfd, insn, hit_data);
9566
99059e56 9567 return bfd_reloc_ok;
e1ec24c6
NC		 9568 }
9569
2cab6cc3
MS		 9570 case R_ARM_THM_PC12:
9571 /* Corresponds to: ldr.w reg, [pc, #offset]. */
9572 {
9573 bfd_vma insn;
9574 bfd_signed_vma relocation;
9575
9576 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 9577 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 9578
99059e56
RM		 9579 if (globals->use_rel)
9580 {
9581 signed_addend = insn & 0xfff;
9582 if (!(insn & (1 << 23)))
9583 signed_addend = -signed_addend;
9584 }
2cab6cc3
MS		 9585
9586 relocation = value + signed_addend;
79f08007 9587 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9588 + input_section->output_offset
9589 + rel->r_offset);
2cab6cc3 9590
b6518b38 9591 value = relocation;
2cab6cc3 9592
99059e56
RM		 9593 if (value >= 0x1000)
9594 return bfd_reloc_overflow;
2cab6cc3
MS		 9595
9596 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 9597 if (relocation >= 0)
9598 insn |= (1 << 23);
2cab6cc3
MS		 9599
9600 bfd_put_16 (input_bfd, insn >> 16, hit_data);
9601 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
9602
99059e56 9603 return bfd_reloc_ok;
2cab6cc3
MS		 9604 }
9605
dfc5f959 9606 case R_ARM_THM_XPC22:
c19d1205 9607 case R_ARM_THM_CALL:
bd97cb95 9608 case R_ARM_THM_JUMP24:
dfc5f959 9609 /* Thumb BL (branch long instruction). */
252b5132 9610 {
b34976b6 9611 bfd_vma relocation;
99059e56 9612 bfd_vma reloc_sign;
b34976b6
AM		 9613 bfd_boolean overflow = FALSE;
9614 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
9615 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 9616 bfd_signed_vma reloc_signed_max;
9617 bfd_signed_vma reloc_signed_min;
b34976b6 9618 bfd_vma check;
252b5132 9619 bfd_signed_vma signed_check;
e95de063 9620 int bitsize;
cd1dac3d 9621 const int thumb2 = using_thumb2 (globals);
252b5132 9622
5ab79981 9623 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 9624 the next instruction unless a PLT entry will be created.
9625 The jump to the next instruction is optimized as a NOP.W for
9626 Thumb-2 enabled architectures. */
19540007 9627 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 9628 && plt_offset == (bfd_vma) -1)
5ab79981 9629 {
cd1dac3d
DG		 9630 if (arch_has_thumb2_nop (globals))
9631 {
9632 bfd_put_16 (input_bfd, 0xf3af, hit_data);
9633 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
9634 }
9635 else
9636 {
9637 bfd_put_16 (input_bfd, 0xe000, hit_data);
9638 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
9639 }
5ab79981
PB		 9640 return bfd_reloc_ok;
9641 }
9642
e95de063 9643 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 9644 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 9645 if (globals->use_rel)
9646 {
99059e56
RM		 9647 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
9648 bfd_vma upper = upper_insn & 0x3ff;
9649 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 9650 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
9651 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 9652 bfd_vma i1 = j1 ^ s ? 0 : 1;
9653 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 9654
99059e56
RM		 9655 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
9656 /* Sign extend. */
9657 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 9658
4e7fd91e
PB		 9659 signed_addend = addend;
9660 }
cb1afa5c 9661
dfc5f959
NC		 9662 if (r_type == R_ARM_THM_XPC22)
9663 {
9664 /* Check for Thumb to Thumb call. */
9665 /* FIXME: Should we translate the instruction into a BL
9666 instruction instead ? */
35fc36a8 9667 if (branch_type == ST_BRANCH_TO_THUMB)
d003868e
AM		 9668 (*_bfd_error_handler)
9669 (_("%B: Warning: Thumb BLX instruction targets thumb function '%s'."),
9670 input_bfd,
9671 h ? h->root.root.string : "(local)");
dfc5f959
NC		 9672 }
9673 else
252b5132 9674 {
dfc5f959
NC		 9675 /* If it is not a call to Thumb, assume call to Arm.
9676 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 9677 function call at all, but rather a long jump. Calls through
9678 the PLT do not require stubs. */
34e77a92 9679 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 9680 {
bd97cb95 9681 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 9682 {
9683 /* Convert BL to BLX. */
9684 lower_insn = (lower_insn & ~0x1000) | 0x0800;
9685 }
155d87d7
CL		 9686 else if (( r_type != R_ARM_THM_CALL)
9687 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 9688 {
9689 if (elf32_thumb_to_arm_stub
9690 (info, sym_name, input_bfd, output_bfd, input_section,
9691 hit_data, sym_sec, rel->r_offset, signed_addend, value,
9692 error_message))
9693 return bfd_reloc_ok;
9694 else
9695 return bfd_reloc_dangerous;
9696 }
da5938a2 9697 }
35fc36a8
RS		 9698 else if (branch_type == ST_BRANCH_TO_THUMB
9699 && globals->use_blx
bd97cb95 9700 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 9701 {
9702 /* Make sure this is a BL. */
9703 lower_insn |= 0x1800;
9704 }
252b5132 9705 }
f21f3fe0 9706
fe33d2fa 9707 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 9708 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 9709 {
9710 /* Check if a stub has to be inserted because the destination
8029a119 9711 is too far. */
fe33d2fa
CL		 9712 struct elf32_arm_stub_hash_entry *stub_entry;
9713 struct elf32_arm_link_hash_entry *hash;
9714
9715 hash = (struct elf32_arm_link_hash_entry *) h;
9716
9717 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 9718 st_type, &branch_type,
9719 hash, value, sym_sec,
fe33d2fa
CL		 9720 input_bfd, sym_name);
9721
9722 if (stub_type != arm_stub_none)
906e58ca
NC		 9723 {
9724 /* The target is out of reach or we are changing modes, so
9725 redirect the branch to the local stub for this
9726 function. */
9727 stub_entry = elf32_arm_get_stub_entry (input_section,
9728 sym_sec, h,
fe33d2fa
CL		 9729 rel, globals,
9730 stub_type);
906e58ca 9731 if (stub_entry != NULL)
9cd3e4e5
NC		 9732 {
9733 value = (stub_entry->stub_offset
9734 + stub_entry->stub_sec->output_offset
9735 + stub_entry->stub_sec->output_section->vma);
9736
9737 if (plt_offset != (bfd_vma) -1)
9738 *unresolved_reloc_p = FALSE;
9739 }
906e58ca 9740
f4ac8484 9741 /* If this call becomes a call to Arm, force BLX. */
155d87d7 9742 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 9743 {
9744 if ((stub_entry
9745 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 9746 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 9747 lower_insn = (lower_insn & ~0x1000) | 0x0800;
9748 }
906e58ca
NC		 9749 }
9750 }
9751
fe33d2fa 9752 /* Handle calls via the PLT. */
34e77a92 9753 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 9754 {
9755 value = (splt->output_section->vma
9756 + splt->output_offset
34e77a92 9757 + plt_offset);
fe33d2fa 9758
eed94f8f
NC		 9759 if (globals->use_blx
9760 && r_type == R_ARM_THM_CALL
9761 && ! using_thumb_only (globals))
fe33d2fa
CL		 9762 {
9763 /* If the Thumb BLX instruction is available, convert
9764 the BL to a BLX instruction to call the ARM-mode
9765 PLT entry. */
9766 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 9767 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 9768 }
9769 else
9770 {
eed94f8f
NC		 9771 if (! using_thumb_only (globals))
9772 /* Target the Thumb stub before the ARM PLT entry. */
9773 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 9774 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 9775 }
9776 *unresolved_reloc_p = FALSE;
9777 }
9778
ba96a88f 9779 relocation = value + signed_addend;
f21f3fe0 9780
252b5132 9781 relocation -= (input_section->output_section->vma
ba96a88f
NC		 9782 + input_section->output_offset
9783 + rel->r_offset);
9a5aca8c 9784
252b5132
RH		 9785 check = relocation >> howto->rightshift;
9786
9787 /* If this is a signed value, the rightshift just dropped
9788 leading 1 bits (assuming twos complement). */
9789 if ((bfd_signed_vma) relocation >= 0)
9790 signed_check = check;
9791 else
9792 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
9793
e95de063
MS		 9794 /* Calculate the permissable maximum and minimum values for
9795 this relocation according to whether we're relocating for
9796 Thumb-2 or not. */
9797 bitsize = howto->bitsize;
9798 if (!thumb2)
9799 bitsize -= 2;
f6ebfac0 9800 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 9801 reloc_signed_min = ~reloc_signed_max;
9802
252b5132 9803 /* Assumes two's complement. */
ba96a88f 9804 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 9805 overflow = TRUE;
252b5132 9806
bd97cb95 9807 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 9808 /* For a BLX instruction, make sure that the relocation is rounded up
9809 to a word boundary. This follows the semantics of the instruction
9810 which specifies that bit 1 of the target address will come from bit
9811 1 of the base address. */
9812 relocation = (relocation + 2) & ~ 3;
cb1afa5c 9813
e95de063
MS		 9814 /* Put RELOCATION back into the insn. Assumes two's complement.
9815 We use the Thumb-2 encoding, which is safe even if dealing with
9816 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 9817 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 9818 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 9819 | ((relocation >> 12) & 0x3ff)
9820 | (reloc_sign << 10);
906e58ca 9821 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 9822 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
9823 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
9824 | ((relocation >> 1) & 0x7ff);
c62e1cc3 9825
252b5132
RH		 9826 /* Put the relocated value back in the object file: */
9827 bfd_put_16 (input_bfd, upper_insn, hit_data);
9828 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
9829
9830 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
9831 }
9832 break;
9833
c19d1205
ZW		 9834 case R_ARM_THM_JUMP19:
9835 /* Thumb32 conditional branch instruction. */
9836 {
9837 bfd_vma relocation;
9838 bfd_boolean overflow = FALSE;
9839 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
9840 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 9841 bfd_signed_vma reloc_signed_max = 0xffffe;
9842 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 9843 bfd_signed_vma signed_check;
c5423981
TG		 9844 enum elf32_arm_stub_type stub_type = arm_stub_none;
9845 struct elf32_arm_stub_hash_entry *stub_entry;
9846 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 9847
9848 /* Need to refetch the addend, reconstruct the top three bits,
9849 and squish the two 11 bit pieces together. */
9850 if (globals->use_rel)
9851 {
9852 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 9853 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 9854 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
9855 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
9856 bfd_vma lower = (lower_insn & 0x07ff);
9857
a00a1f35
MS		 9858 upper |= J1 << 6;
9859 upper |= J2 << 7;
9860 upper |= (!S) << 8;
c19d1205
ZW		 9861 upper -= 0x0100; /* Sign extend. */
9862
9863 addend = (upper << 12) | (lower << 1);
9864 signed_addend = addend;
9865 }
9866
bd97cb95 9867 /* Handle calls via the PLT. */
34e77a92 9868 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 9869 {
9870 value = (splt->output_section->vma
9871 + splt->output_offset
34e77a92 9872 + plt_offset);
bd97cb95
DJ		 9873 /* Target the Thumb stub before the ARM PLT entry. */
9874 value -= PLT_THUMB_STUB_SIZE;
9875 *unresolved_reloc_p = FALSE;
9876 }
9877
c5423981
TG		 9878 hash = (struct elf32_arm_link_hash_entry *)h;
9879
9880 stub_type = arm_type_of_stub (info, input_section, rel,
9881 st_type, &branch_type,
9882 hash, value, sym_sec,
9883 input_bfd, sym_name);
9884 if (stub_type != arm_stub_none)
9885 {
9886 stub_entry = elf32_arm_get_stub_entry (input_section,
9887 sym_sec, h,
9888 rel, globals,
9889 stub_type);
9890 if (stub_entry != NULL)
9891 {
9892 value = (stub_entry->stub_offset
9893 + stub_entry->stub_sec->output_offset
9894 + stub_entry->stub_sec->output_section->vma);
9895 }
9896 }
c19d1205 9897
99059e56 9898 relocation = value + signed_addend;
c19d1205
ZW		 9899 relocation -= (input_section->output_section->vma
9900 + input_section->output_offset
9901 + rel->r_offset);
a00a1f35 9902 signed_check = (bfd_signed_vma) relocation;
c19d1205 9903
c19d1205
ZW		 9904 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
9905 overflow = TRUE;
9906
9907 /* Put RELOCATION back into the insn. */
9908 {
9909 bfd_vma S = (relocation & 0x00100000) >> 20;
9910 bfd_vma J2 = (relocation & 0x00080000) >> 19;
9911 bfd_vma J1 = (relocation & 0x00040000) >> 18;
9912 bfd_vma hi = (relocation & 0x0003f000) >> 12;
9913 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
9914
a00a1f35 9915 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 9916 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
9917 }
9918
9919 /* Put the relocated value back in the object file: */
9920 bfd_put_16 (input_bfd, upper_insn, hit_data);
9921 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
9922
9923 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
9924 }
9925
9926 case R_ARM_THM_JUMP11:
9927 case R_ARM_THM_JUMP8:
9928 case R_ARM_THM_JUMP6:
51c5503b
NC		 9929 /* Thumb B (branch) instruction). */
9930 {
6cf9e9fe 9931 bfd_signed_vma relocation;
51c5503b
NC		 9932 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
9933 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 9934 bfd_signed_vma signed_check;
9935
c19d1205
ZW		 9936 /* CZB cannot jump backward. */
9937 if (r_type == R_ARM_THM_JUMP6)
9938 reloc_signed_min = 0;
9939
4e7fd91e 9940 if (globals->use_rel)
6cf9e9fe 9941 {
4e7fd91e
PB		 9942 /* Need to refetch addend. */
9943 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
9944 if (addend & ((howto->src_mask + 1) >> 1))
9945 {
9946 signed_addend = -1;
9947 signed_addend &= ~ howto->src_mask;
9948 signed_addend |= addend;
9949 }
9950 else
9951 signed_addend = addend;
9952 /* The value in the insn has been right shifted. We need to
9953 undo this, so that we can perform the address calculation
9954 in terms of bytes. */
9955 signed_addend <<= howto->rightshift;
6cf9e9fe 9956 }
6cf9e9fe 9957 relocation = value + signed_addend;
51c5503b
NC		 9958
9959 relocation -= (input_section->output_section->vma
9960 + input_section->output_offset
9961 + rel->r_offset);
9962
6cf9e9fe
NC		 9963 relocation >>= howto->rightshift;
9964 signed_check = relocation;
c19d1205
ZW		 9965
9966 if (r_type == R_ARM_THM_JUMP6)
9967 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
9968 else
9969 relocation &= howto->dst_mask;
51c5503b 9970 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 9971
51c5503b
NC		 9972 bfd_put_16 (input_bfd, relocation, hit_data);
9973
9974 /* Assumes two's complement. */
9975 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
9976 return bfd_reloc_overflow;
9977
9978 return bfd_reloc_ok;
9979 }
cedb70c5 9980
8375c36b
PB		 9981 case R_ARM_ALU_PCREL7_0:
9982 case R_ARM_ALU_PCREL15_8:
9983 case R_ARM_ALU_PCREL23_15:
9984 {
9985 bfd_vma insn;
9986 bfd_vma relocation;
9987
9988 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 9989 if (globals->use_rel)
9990 {
9991 /* Extract the addend. */
9992 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
9993 signed_addend = addend;
9994 }
8375c36b
PB		 9995 relocation = value + signed_addend;
9996
9997 relocation -= (input_section->output_section->vma
9998 + input_section->output_offset
9999 + rel->r_offset);
10000 insn = (insn & ~0xfff)
10001 | ((howto->bitpos << 7) & 0xf00)
10002 | ((relocation >> howto->bitpos) & 0xff);
10003 bfd_put_32 (input_bfd, value, hit_data);
10004 }
10005 return bfd_reloc_ok;
10006
252b5132
RH		 10007 case R_ARM_GNU_VTINHERIT:
10008 case R_ARM_GNU_VTENTRY:
10009 return bfd_reloc_ok;
10010
c19d1205 10011 case R_ARM_GOTOFF32:
252b5132 10012 /* Relocation is relative to the start of the
99059e56 10013 global offset table. */
252b5132
RH		 10014
10015 BFD_ASSERT (sgot != NULL);
10016 if (sgot == NULL)
99059e56 10017 return bfd_reloc_notsupported;
9a5aca8c 10018
cedb70c5 10019 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 10020 address by one, so that attempts to call the function pointer will
10021 correctly interpret it as Thumb code. */
35fc36a8 10022 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 10023 value += 1;
10024
252b5132 10025 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 10026 calculation. We always want the start of .got. If we
10027 define _GLOBAL_OFFSET_TABLE in a different way, as is
10028 permitted by the ABI, we might have to change this
10029 calculation. */
252b5132 10030 value -= sgot->output_section->vma;
f21f3fe0 10031 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10032 contents, rel->r_offset, value,
00a97672 10033 rel->r_addend);
252b5132
RH		 10034
10035 case R_ARM_GOTPC:
a7c10850 10036 /* Use global offset table as symbol value. */
252b5132 10037 BFD_ASSERT (sgot != NULL);
f21f3fe0 10038
252b5132 10039 if (sgot == NULL)
99059e56 10040 return bfd_reloc_notsupported;
252b5132 10041
0945cdfd 10042 *unresolved_reloc_p = FALSE;
252b5132 10043 value = sgot->output_section->vma;
f21f3fe0 10044 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10045 contents, rel->r_offset, value,
00a97672 10046 rel->r_addend);
f21f3fe0 10047
252b5132 10048 case R_ARM_GOT32:
eb043451 10049 case R_ARM_GOT_PREL:
252b5132 10050 /* Relocation is to the entry for this symbol in the
99059e56 10051 global offset table. */
252b5132
RH		 10052 if (sgot == NULL)
10053 return bfd_reloc_notsupported;
f21f3fe0 10054
34e77a92
RS		 10055 if (dynreloc_st_type == STT_GNU_IFUNC
10056 && plt_offset != (bfd_vma) -1
10057 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
10058 {
10059 /* We have a relocation against a locally-binding STT_GNU_IFUNC
10060 symbol, and the relocation resolves directly to the runtime
10061 target rather than to the .iplt entry. This means that any
10062 .got entry would be the same value as the .igot.plt entry,
10063 so there's no point creating both. */
10064 sgot = globals->root.igotplt;
10065 value = sgot->output_offset + gotplt_offset;
10066 }
10067 else if (h != NULL)
252b5132
RH		 10068 {
10069 bfd_vma off;
f21f3fe0 10070
252b5132
RH		 10071 off = h->got.offset;
10072 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 10073 if ((off & 1) != 0)
252b5132 10074 {
b436d854
RS		 10075 /* We have already processsed one GOT relocation against
10076 this symbol. */
10077 off &= ~1;
10078 if (globals->root.dynamic_sections_created
10079 && !SYMBOL_REFERENCES_LOCAL (info, h))
10080 *unresolved_reloc_p = FALSE;
10081 }
10082 else
10083 {
10084 Elf_Internal_Rela outrel;
10085
6f820c85 10086 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 10087 {
10088 /* If the symbol doesn't resolve locally in a static
10089 object, we have an undefined reference. If the
10090 symbol doesn't resolve locally in a dynamic object,
10091 it should be resolved by the dynamic linker. */
10092 if (globals->root.dynamic_sections_created)
10093 {
10094 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
10095 *unresolved_reloc_p = FALSE;
10096 }
10097 else
10098 outrel.r_info = 0;
10099 outrel.r_addend = 0;
10100 }
252b5132
RH		 10101 else
10102 {
34e77a92 10103 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 10104 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
0e1862bb 10105 else if (bfd_link_pic (info) &&
31943882
WN		 10106 (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10107 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 10108 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
10109 else
10110 outrel.r_info = 0;
34e77a92 10111 outrel.r_addend = dynreloc_value;
b436d854 10112 }
ee29b9fb 10113
b436d854
RS		 10114 /* The GOT entry is initialized to zero by default.
10115 See if we should install a different value. */
10116 if (outrel.r_addend != 0
10117 && (outrel.r_info == 0 || globals->use_rel))
10118 {
10119 bfd_put_32 (output_bfd, outrel.r_addend,
10120 sgot->contents + off);
10121 outrel.r_addend = 0;
252b5132 10122 }
f21f3fe0 10123
b436d854
RS		 10124 if (outrel.r_info != 0)
10125 {
10126 outrel.r_offset = (sgot->output_section->vma
10127 + sgot->output_offset
10128 + off);
10129 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
10130 }
10131 h->got.offset |= 1;
10132 }
252b5132
RH		 10133 value = sgot->output_offset + off;
10134 }
10135 else
10136 {
10137 bfd_vma off;
f21f3fe0 10138
252b5132
RH		 10139 BFD_ASSERT (local_got_offsets != NULL &&
10140 local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 10141
252b5132 10142 off = local_got_offsets[r_symndx];
f21f3fe0 10143
252b5132
RH		 10144 /* The offset must always be a multiple of 4. We use the
10145 least significant bit to record whether we have already
9b485d32 10146 generated the necessary reloc. */
252b5132
RH		 10147 if ((off & 1) != 0)
10148 off &= ~1;
10149 else
10150 {
00a97672 10151 if (globals->use_rel)
34e77a92 10152 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 10153
0e1862bb 10154 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 10155 {
947216bf 10156 Elf_Internal_Rela outrel;
f21f3fe0 10157
34e77a92 10158 outrel.r_addend = addend + dynreloc_value;
252b5132 10159 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 10160 + sgot->output_offset
252b5132 10161 + off);
34e77a92 10162 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 10163 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 10164 else
10165 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 10166 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 10167 }
f21f3fe0 10168
252b5132
RH		 10169 local_got_offsets[r_symndx] |= 1;
10170 }
f21f3fe0 10171
252b5132
RH		 10172 value = sgot->output_offset + off;
10173 }
eb043451
PB		 10174 if (r_type != R_ARM_GOT32)
10175 value += sgot->output_section->vma;
9a5aca8c 10176
f21f3fe0 10177 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10178 contents, rel->r_offset, value,
00a97672 10179 rel->r_addend);
f21f3fe0 10180
ba93b8ac
DJ		 10181 case R_ARM_TLS_LDO32:
10182 value = value - dtpoff_base (info);
10183
10184 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 10185 contents, rel->r_offset, value,
10186 rel->r_addend);
ba93b8ac
DJ		 10187
10188 case R_ARM_TLS_LDM32:
10189 {
10190 bfd_vma off;
10191
362d30a1 10192 if (sgot == NULL)
ba93b8ac
DJ		 10193 abort ();
10194
10195 off = globals->tls_ldm_got.offset;
10196
10197 if ((off & 1) != 0)
10198 off &= ~1;
10199 else
10200 {
10201 /* If we don't know the module number, create a relocation
10202 for it. */
0e1862bb 10203 if (bfd_link_pic (info))
ba93b8ac
DJ		 10204 {
10205 Elf_Internal_Rela outrel;
ba93b8ac 10206
362d30a1 10207 if (srelgot == NULL)
ba93b8ac
DJ		 10208 abort ();
10209
00a97672 10210 outrel.r_addend = 0;
362d30a1
RS		 10211 outrel.r_offset = (sgot->output_section->vma
10212 + sgot->output_offset + off);
ba93b8ac
DJ		 10213 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
10214
00a97672
RS		 10215 if (globals->use_rel)
10216 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10217 sgot->contents + off);
ba93b8ac 10218
47beaa6a 10219 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10220 }
10221 else
362d30a1 10222 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 10223
10224 globals->tls_ldm_got.offset |= 1;
10225 }
10226
362d30a1 10227 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 10228 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
10229
10230 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10231 contents, rel->r_offset, value,
00a97672 10232 rel->r_addend);
ba93b8ac
DJ		 10233 }
10234
0855e32b
NS		 10235 case R_ARM_TLS_CALL:
10236 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 10237 case R_ARM_TLS_GD32:
10238 case R_ARM_TLS_IE32:
0855e32b
NS		 10239 case R_ARM_TLS_GOTDESC:
10240 case R_ARM_TLS_DESCSEQ:
10241 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 10242 {
0855e32b
NS		 10243 bfd_vma off, offplt;
10244 int indx = 0;
ba93b8ac
DJ		 10245 char tls_type;
10246
0855e32b 10247 BFD_ASSERT (sgot != NULL);
ba93b8ac 10248
ba93b8ac
DJ		 10249 if (h != NULL)
10250 {
10251 bfd_boolean dyn;
10252 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 10253 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
10254 bfd_link_pic (info),
10255 h)
10256 && (!bfd_link_pic (info)
ba93b8ac
DJ		 10257 || !SYMBOL_REFERENCES_LOCAL (info, h)))
10258 {
10259 *unresolved_reloc_p = FALSE;
10260 indx = h->dynindx;
10261 }
10262 off = h->got.offset;
0855e32b 10263 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 10264 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
10265 }
10266 else
10267 {
0855e32b 10268 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 10269 off = local_got_offsets[r_symndx];
0855e32b 10270 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 10271 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
10272 }
10273
0855e32b 10274 /* Linker relaxations happens from one of the
b38cadfb 10275 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 10276 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 10277 tls_type = GOT_TLS_IE;
0855e32b
NS		 10278
10279 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 10280
10281 if ((off & 1) != 0)
10282 off &= ~1;
10283 else
10284 {
10285 bfd_boolean need_relocs = FALSE;
10286 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 10287 int cur_off = off;
10288
10289 /* The GOT entries have not been initialized yet. Do it
10290 now, and emit any relocations. If both an IE GOT and a
10291 GD GOT are necessary, we emit the GD first. */
10292
0e1862bb 10293 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 10294 && (h == NULL
10295 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10296 || h->root.type != bfd_link_hash_undefweak))
10297 {
10298 need_relocs = TRUE;
0855e32b 10299 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 10300 }
10301
0855e32b
NS		 10302 if (tls_type & GOT_TLS_GDESC)
10303 {
47beaa6a
RS		 10304 bfd_byte *loc;
10305
0855e32b
NS		 10306 /* We should have relaxed, unless this is an undefined
10307 weak symbol. */
10308 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 10309 || bfd_link_pic (info));
0855e32b 10310 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 10311 <= globals->root.sgotplt->size);
0855e32b
NS		 10312
10313 outrel.r_addend = 0;
10314 outrel.r_offset = (globals->root.sgotplt->output_section->vma
10315 + globals->root.sgotplt->output_offset
10316 + offplt
10317 + globals->sgotplt_jump_table_size);
b38cadfb 10318
0855e32b
NS		 10319 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
10320 sreloc = globals->root.srelplt;
10321 loc = sreloc->contents;
10322 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
10323 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 10324 <= sreloc->contents + sreloc->size);
0855e32b
NS		 10325
10326 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
10327
10328 /* For globals, the first word in the relocation gets
10329 the relocation index and the top bit set, or zero,
10330 if we're binding now. For locals, it gets the
10331 symbol's offset in the tls section. */
99059e56 10332 bfd_put_32 (output_bfd,
0855e32b
NS		 10333 !h ? value - elf_hash_table (info)->tls_sec->vma
10334 : info->flags & DF_BIND_NOW ? 0
10335 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 10336 globals->root.sgotplt->contents + offplt
10337 + globals->sgotplt_jump_table_size);
10338
0855e32b 10339 /* Second word in the relocation is always zero. */
99059e56 10340 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 10341 globals->root.sgotplt->contents + offplt
10342 + globals->sgotplt_jump_table_size + 4);
0855e32b 10343 }
ba93b8ac
DJ		 10344 if (tls_type & GOT_TLS_GD)
10345 {
10346 if (need_relocs)
10347 {
00a97672 10348 outrel.r_addend = 0;
362d30a1
RS		 10349 outrel.r_offset = (sgot->output_section->vma
10350 + sgot->output_offset
00a97672 10351 + cur_off);
ba93b8ac 10352 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 10353
00a97672
RS		 10354 if (globals->use_rel)
10355 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10356 sgot->contents + cur_off);
00a97672 10357
47beaa6a 10358 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10359
10360 if (indx == 0)
10361 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 10362 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 10363 else
10364 {
00a97672 10365 outrel.r_addend = 0;
ba93b8ac
DJ		 10366 outrel.r_info = ELF32_R_INFO (indx,
10367 R_ARM_TLS_DTPOFF32);
10368 outrel.r_offset += 4;
00a97672
RS		 10369
10370 if (globals->use_rel)
10371 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10372 sgot->contents + cur_off + 4);
00a97672 10373
47beaa6a
RS		 10374 elf32_arm_add_dynreloc (output_bfd, info,
10375 srelgot, &outrel);
ba93b8ac
DJ		 10376 }
10377 }
10378 else
10379 {
10380 /* If we are not emitting relocations for a
10381 general dynamic reference, then we must be in a
10382 static link or an executable link with the
10383 symbol binding locally. Mark it as belonging
10384 to module 1, the executable. */
10385 bfd_put_32 (output_bfd, 1,
362d30a1 10386 sgot->contents + cur_off);
ba93b8ac 10387 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 10388 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 10389 }
10390
10391 cur_off += 8;
10392 }
10393
10394 if (tls_type & GOT_TLS_IE)
10395 {
10396 if (need_relocs)
10397 {
00a97672
RS		 10398 if (indx == 0)
10399 outrel.r_addend = value - dtpoff_base (info);
10400 else
10401 outrel.r_addend = 0;
362d30a1
RS		 10402 outrel.r_offset = (sgot->output_section->vma
10403 + sgot->output_offset
ba93b8ac
DJ		 10404 + cur_off);
10405 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
10406
00a97672
RS		 10407 if (globals->use_rel)
10408 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10409 sgot->contents + cur_off);
ba93b8ac 10410
47beaa6a 10411 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10412 }
10413 else
10414 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 10415 sgot->contents + cur_off);
ba93b8ac
DJ		 10416 cur_off += 4;
10417 }
10418
10419 if (h != NULL)
10420 h->got.offset |= 1;
10421 else
10422 local_got_offsets[r_symndx] |= 1;
10423 }
10424
10425 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
10426 off += 8;
0855e32b
NS		 10427 else if (tls_type & GOT_TLS_GDESC)
10428 off = offplt;
10429
10430 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
10431 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
10432 {
10433 bfd_signed_vma offset;
12352d3f
PB		 10434 /* TLS stubs are arm mode. The original symbol is a
10435 data object, so branch_type is bogus. */
10436 branch_type = ST_BRANCH_TO_ARM;
0855e32b 10437 enum elf32_arm_stub_type stub_type
34e77a92
RS		 10438 = arm_type_of_stub (info, input_section, rel,
10439 st_type, &branch_type,
0855e32b
NS		 10440 (struct elf32_arm_link_hash_entry *)h,
10441 globals->tls_trampoline, globals->root.splt,
10442 input_bfd, sym_name);
10443
10444 if (stub_type != arm_stub_none)
10445 {
10446 struct elf32_arm_stub_hash_entry *stub_entry
10447 = elf32_arm_get_stub_entry
10448 (input_section, globals->root.splt, 0, rel,
10449 globals, stub_type);
10450 offset = (stub_entry->stub_offset
10451 + stub_entry->stub_sec->output_offset
10452 + stub_entry->stub_sec->output_section->vma);
10453 }
10454 else
10455 offset = (globals->root.splt->output_section->vma
10456 + globals->root.splt->output_offset
10457 + globals->tls_trampoline);
10458
10459 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
10460 {
10461 unsigned long inst;
b38cadfb
NC		 10462
10463 offset -= (input_section->output_section->vma
10464 + input_section->output_offset
10465 + rel->r_offset + 8);
0855e32b
NS		 10466
10467 inst = offset >> 2;
10468 inst &= 0x00ffffff;
10469 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
10470 }
10471 else
10472 {
10473 /* Thumb blx encodes the offset in a complicated
10474 fashion. */
10475 unsigned upper_insn, lower_insn;
10476 unsigned neg;
10477
b38cadfb
NC		 10478 offset -= (input_section->output_section->vma
10479 + input_section->output_offset
0855e32b 10480 + rel->r_offset + 4);
b38cadfb 10481
12352d3f
PB		 10482 if (stub_type != arm_stub_none
10483 && arm_stub_is_thumb (stub_type))
10484 {
10485 lower_insn = 0xd000;
10486 }
10487 else
10488 {
10489 lower_insn = 0xc000;
6a631e86 10490 /* Round up the offset to a word boundary. */
12352d3f
PB		 10491 offset = (offset + 2) & ~2;
10492 }
10493
0855e32b
NS		 10494 neg = offset < 0;
10495 upper_insn = (0xf000
10496 | ((offset >> 12) & 0x3ff)
10497 | (neg << 10));
12352d3f 10498 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 10499 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 10500 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 10501 bfd_put_16 (input_bfd, upper_insn, hit_data);
10502 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10503 return bfd_reloc_ok;
10504 }
10505 }
10506 /* These relocations needs special care, as besides the fact
10507 they point somewhere in .gotplt, the addend must be
10508 adjusted accordingly depending on the type of instruction
6a631e86 10509 we refer to. */
0855e32b
NS		 10510 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
10511 {
10512 unsigned long data, insn;
10513 unsigned thumb;
b38cadfb 10514
0855e32b
NS		 10515 data = bfd_get_32 (input_bfd, hit_data);
10516 thumb = data & 1;
10517 data &= ~1u;
b38cadfb 10518
0855e32b
NS		 10519 if (thumb)
10520 {
10521 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
10522 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10523 insn = (insn << 16)
10524 | bfd_get_16 (input_bfd,
10525 contents + rel->r_offset - data + 2);
10526 if ((insn & 0xf800c000) == 0xf000c000)
10527 /* bl/blx */
10528 value = -6;
10529 else if ((insn & 0xffffff00) == 0x4400)
10530 /* add */
10531 value = -5;
10532 else
10533 {
10534 (*_bfd_error_handler)
10535 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' referenced by TLS_GOTDESC"),
10536 input_bfd, input_section,
10537 (unsigned long)rel->r_offset, insn);
10538 return bfd_reloc_notsupported;
10539 }
10540 }
10541 else
10542 {
10543 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
10544
10545 switch (insn >> 24)
10546 {
10547 case 0xeb: /* bl */
10548 case 0xfa: /* blx */
10549 value = -4;
10550 break;
10551
10552 case 0xe0: /* add */
10553 value = -8;
10554 break;
b38cadfb 10555
0855e32b
NS		 10556 default:
10557 (*_bfd_error_handler)
10558 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' referenced by TLS_GOTDESC"),
10559 input_bfd, input_section,
10560 (unsigned long)rel->r_offset, insn);
10561 return bfd_reloc_notsupported;
10562 }
10563 }
b38cadfb 10564
0855e32b
NS		 10565 value += ((globals->root.sgotplt->output_section->vma
10566 + globals->root.sgotplt->output_offset + off)
10567 - (input_section->output_section->vma
10568 + input_section->output_offset
10569 + rel->r_offset)
10570 + globals->sgotplt_jump_table_size);
10571 }
10572 else
10573 value = ((globals->root.sgot->output_section->vma
10574 + globals->root.sgot->output_offset + off)
10575 - (input_section->output_section->vma
10576 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 10577
10578 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10579 contents, rel->r_offset, value,
00a97672 10580 rel->r_addend);
ba93b8ac
DJ		 10581 }
10582
10583 case R_ARM_TLS_LE32:
3cbc1e5e 10584 if (bfd_link_dll (info))
ba93b8ac
DJ		 10585 {
10586 (*_bfd_error_handler)
10587 (_("%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object"),
10588 input_bfd, input_section,
10589 (long) rel->r_offset, howto->name);
46691134 10590 return bfd_reloc_notsupported;
ba93b8ac
DJ		 10591 }
10592 else
10593 value = tpoff (info, value);
906e58ca 10594
ba93b8ac 10595 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 10596 contents, rel->r_offset, value,
10597 rel->r_addend);
ba93b8ac 10598
319850b4
JB		 10599 case R_ARM_V4BX:
10600 if (globals->fix_v4bx)
845b51d6
PB		 10601 {
10602 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 10603
845b51d6
PB		 10604 /* Ensure that we have a BX instruction. */
10605 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 10606
845b51d6
PB		 10607 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
10608 {
10609 /* Branch to veneer. */
10610 bfd_vma glue_addr;
10611 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
10612 glue_addr -= input_section->output_section->vma
10613 + input_section->output_offset
10614 + rel->r_offset + 8;
10615 insn = (insn & 0xf0000000) | 0x0a000000
10616 | ((glue_addr >> 2) & 0x00ffffff);
10617 }
10618 else
10619 {
10620 /* Preserve Rm (lowest four bits) and the condition code
10621 (highest four bits). Other bits encode MOV PC,Rm. */
10622 insn = (insn & 0xf000000f) | 0x01a0f000;
10623 }
319850b4 10624
845b51d6
PB		 10625 bfd_put_32 (input_bfd, insn, hit_data);
10626 }
319850b4
JB		 10627 return bfd_reloc_ok;
10628
b6895b4f
PB		 10629 case R_ARM_MOVW_ABS_NC:
10630 case R_ARM_MOVT_ABS:
10631 case R_ARM_MOVW_PREL_NC:
10632 case R_ARM_MOVT_PREL:
92f5d02b
MS		 10633 /* Until we properly support segment-base-relative addressing then
10634 we assume the segment base to be zero, as for the group relocations.
10635 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
10636 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
10637 case R_ARM_MOVW_BREL_NC:
10638 case R_ARM_MOVW_BREL:
10639 case R_ARM_MOVT_BREL:
b6895b4f
PB		 10640 {
10641 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
10642
10643 if (globals->use_rel)
10644 {
10645 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 10646 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 10647 }
92f5d02b 10648
b6895b4f 10649 value += signed_addend;
b6895b4f
PB		 10650
10651 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
10652 value -= (input_section->output_section->vma
10653 + input_section->output_offset + rel->r_offset);
10654
92f5d02b 10655 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 10656 return bfd_reloc_overflow;
92f5d02b 10657
35fc36a8 10658 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 10659 value |= 1;
10660
10661 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 10662 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 10663 value >>= 16;
10664
10665 insn &= 0xfff0f000;
10666 insn |= value & 0xfff;
10667 insn |= (value & 0xf000) << 4;
10668 bfd_put_32 (input_bfd, insn, hit_data);
10669 }
10670 return bfd_reloc_ok;
10671
10672 case R_ARM_THM_MOVW_ABS_NC:
10673 case R_ARM_THM_MOVT_ABS:
10674 case R_ARM_THM_MOVW_PREL_NC:
10675 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 10676 /* Until we properly support segment-base-relative addressing then
10677 we assume the segment base to be zero, as for the above relocations.
10678 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
10679 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
10680 as R_ARM_THM_MOVT_ABS. */
10681 case R_ARM_THM_MOVW_BREL_NC:
10682 case R_ARM_THM_MOVW_BREL:
10683 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 10684 {
10685 bfd_vma insn;
906e58ca 10686
b6895b4f
PB		 10687 insn = bfd_get_16 (input_bfd, hit_data) << 16;
10688 insn |= bfd_get_16 (input_bfd, hit_data + 2);
10689
10690 if (globals->use_rel)
10691 {
10692 addend = ((insn >> 4) & 0xf000)
10693 | ((insn >> 15) & 0x0800)
10694 | ((insn >> 4) & 0x0700)
10695 | (insn & 0x00ff);
39623e12 10696 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 10697 }
92f5d02b 10698
b6895b4f 10699 value += signed_addend;
b6895b4f
PB		 10700
10701 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
10702 value -= (input_section->output_section->vma
10703 + input_section->output_offset + rel->r_offset);
10704
92f5d02b 10705 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 10706 return bfd_reloc_overflow;
92f5d02b 10707
35fc36a8 10708 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 10709 value |= 1;
10710
10711 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 10712 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 10713 value >>= 16;
10714
10715 insn &= 0xfbf08f00;
10716 insn |= (value & 0xf000) << 4;
10717 insn |= (value & 0x0800) << 15;
10718 insn |= (value & 0x0700) << 4;
10719 insn |= (value & 0x00ff);
10720
10721 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10722 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10723 }
10724 return bfd_reloc_ok;
10725
4962c51a
MS		 10726 case R_ARM_ALU_PC_G0_NC:
10727 case R_ARM_ALU_PC_G1_NC:
10728 case R_ARM_ALU_PC_G0:
10729 case R_ARM_ALU_PC_G1:
10730 case R_ARM_ALU_PC_G2:
10731 case R_ARM_ALU_SB_G0_NC:
10732 case R_ARM_ALU_SB_G1_NC:
10733 case R_ARM_ALU_SB_G0:
10734 case R_ARM_ALU_SB_G1:
10735 case R_ARM_ALU_SB_G2:
10736 {
10737 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10738 bfd_vma pc = input_section->output_section->vma
4962c51a 10739 + input_section->output_offset + rel->r_offset;
31a91d61 10740 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10741 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 10742 bfd_vma residual;
10743 bfd_vma g_n;
4962c51a 10744 bfd_signed_vma signed_value;
99059e56
RM		 10745 int group = 0;
10746
10747 /* Determine which group of bits to select. */
10748 switch (r_type)
10749 {
10750 case R_ARM_ALU_PC_G0_NC:
10751 case R_ARM_ALU_PC_G0:
10752 case R_ARM_ALU_SB_G0_NC:
10753 case R_ARM_ALU_SB_G0:
10754 group = 0;
10755 break;
10756
10757 case R_ARM_ALU_PC_G1_NC:
10758 case R_ARM_ALU_PC_G1:
10759 case R_ARM_ALU_SB_G1_NC:
10760 case R_ARM_ALU_SB_G1:
10761 group = 1;
10762 break;
10763
10764 case R_ARM_ALU_PC_G2:
10765 case R_ARM_ALU_SB_G2:
10766 group = 2;
10767 break;
10768
10769 default:
10770 abort ();
10771 }
10772
10773 /* If REL, extract the addend from the insn. If RELA, it will
10774 have already been fetched for us. */
4962c51a 10775 if (globals->use_rel)
99059e56
RM		 10776 {
10777 int negative;
10778 bfd_vma constant = insn & 0xff;
10779 bfd_vma rotation = (insn & 0xf00) >> 8;
10780
10781 if (rotation == 0)
10782 signed_addend = constant;
10783 else
10784 {
10785 /* Compensate for the fact that in the instruction, the
10786 rotation is stored in multiples of 2 bits. */
10787 rotation *= 2;
10788
10789 /* Rotate "constant" right by "rotation" bits. */
10790 signed_addend = (constant >> rotation) |
10791 (constant << (8 * sizeof (bfd_vma) - rotation));
10792 }
10793
10794 /* Determine if the instruction is an ADD or a SUB.
10795 (For REL, this determines the sign of the addend.) */
10796 negative = identify_add_or_sub (insn);
10797 if (negative == 0)
10798 {
10799 (*_bfd_error_handler)
10800 (_("%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations"),
10801 input_bfd, input_section,
10802 (long) rel->r_offset, howto->name);
10803 return bfd_reloc_overflow;
10804 }
10805
10806 signed_addend *= negative;
10807 }
4962c51a
MS		 10808
10809 /* Compute the value (X) to go in the place. */
99059e56
RM		 10810 if (r_type == R_ARM_ALU_PC_G0_NC
10811 || r_type == R_ARM_ALU_PC_G1_NC
10812 || r_type == R_ARM_ALU_PC_G0
10813 || r_type == R_ARM_ALU_PC_G1
10814 || r_type == R_ARM_ALU_PC_G2)
10815 /* PC relative. */
10816 signed_value = value - pc + signed_addend;
10817 else
10818 /* Section base relative. */
10819 signed_value = value - sb + signed_addend;
10820
10821 /* If the target symbol is a Thumb function, then set the
10822 Thumb bit in the address. */
35fc36a8 10823 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 10824 signed_value |= 1;
10825
99059e56
RM		 10826 /* Calculate the value of the relevant G_n, in encoded
10827 constant-with-rotation format. */
b6518b38
NC		 10828 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
10829 group, &residual);
99059e56
RM		 10830
10831 /* Check for overflow if required. */
10832 if ((r_type == R_ARM_ALU_PC_G0
10833 || r_type == R_ARM_ALU_PC_G1
10834 || r_type == R_ARM_ALU_PC_G2
10835 || r_type == R_ARM_ALU_SB_G0
10836 || r_type == R_ARM_ALU_SB_G1
10837 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
10838 {
10839 (*_bfd_error_handler)
10840 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
10841 input_bfd, input_section,
b6518b38
NC		 10842 (long) rel->r_offset, signed_value < 0 ? - signed_value : signed_value,
10843 howto->name);
99059e56
RM		 10844 return bfd_reloc_overflow;
10845 }
10846
10847 /* Mask out the value and the ADD/SUB part of the opcode; take care
10848 not to destroy the S bit. */
10849 insn &= 0xff1ff000;
10850
10851 /* Set the opcode according to whether the value to go in the
10852 place is negative. */
10853 if (signed_value < 0)
10854 insn |= 1 << 22;
10855 else
10856 insn |= 1 << 23;
10857
10858 /* Encode the offset. */
10859 insn |= g_n;
4962c51a
MS		 10860
10861 bfd_put_32 (input_bfd, insn, hit_data);
10862 }
10863 return bfd_reloc_ok;
10864
10865 case R_ARM_LDR_PC_G0:
10866 case R_ARM_LDR_PC_G1:
10867 case R_ARM_LDR_PC_G2:
10868 case R_ARM_LDR_SB_G0:
10869 case R_ARM_LDR_SB_G1:
10870 case R_ARM_LDR_SB_G2:
10871 {
10872 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10873 bfd_vma pc = input_section->output_section->vma
4962c51a 10874 + input_section->output_offset + rel->r_offset;
31a91d61 10875 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10876 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 10877 bfd_vma residual;
4962c51a 10878 bfd_signed_vma signed_value;
99059e56
RM		 10879 int group = 0;
10880
10881 /* Determine which groups of bits to calculate. */
10882 switch (r_type)
10883 {
10884 case R_ARM_LDR_PC_G0:
10885 case R_ARM_LDR_SB_G0:
10886 group = 0;
10887 break;
10888
10889 case R_ARM_LDR_PC_G1:
10890 case R_ARM_LDR_SB_G1:
10891 group = 1;
10892 break;
10893
10894 case R_ARM_LDR_PC_G2:
10895 case R_ARM_LDR_SB_G2:
10896 group = 2;
10897 break;
10898
10899 default:
10900 abort ();
10901 }
10902
10903 /* If REL, extract the addend from the insn. If RELA, it will
10904 have already been fetched for us. */
4962c51a 10905 if (globals->use_rel)
99059e56
RM		 10906 {
10907 int negative = (insn & (1 << 23)) ? 1 : -1;
10908 signed_addend = negative * (insn & 0xfff);
10909 }
4962c51a
MS		 10910
10911 /* Compute the value (X) to go in the place. */
99059e56
RM		 10912 if (r_type == R_ARM_LDR_PC_G0
10913 || r_type == R_ARM_LDR_PC_G1
10914 || r_type == R_ARM_LDR_PC_G2)
10915 /* PC relative. */
10916 signed_value = value - pc + signed_addend;
10917 else
10918 /* Section base relative. */
10919 signed_value = value - sb + signed_addend;
10920
10921 /* Calculate the value of the relevant G_{n-1} to obtain
10922 the residual at that stage. */
b6518b38
NC		 10923 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
10924 group - 1, &residual);
99059e56
RM		 10925
10926 /* Check for overflow. */
10927 if (residual >= 0x1000)
10928 {
10929 (*_bfd_error_handler)
10930 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 10931 input_bfd, input_section,
10932 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 10933 return bfd_reloc_overflow;
10934 }
10935
10936 /* Mask out the value and U bit. */
10937 insn &= 0xff7ff000;
10938
10939 /* Set the U bit if the value to go in the place is non-negative. */
10940 if (signed_value >= 0)
10941 insn |= 1 << 23;
10942
10943 /* Encode the offset. */
10944 insn |= residual;
4962c51a
MS		 10945
10946 bfd_put_32 (input_bfd, insn, hit_data);
10947 }
10948 return bfd_reloc_ok;
10949
10950 case R_ARM_LDRS_PC_G0:
10951 case R_ARM_LDRS_PC_G1:
10952 case R_ARM_LDRS_PC_G2:
10953 case R_ARM_LDRS_SB_G0:
10954 case R_ARM_LDRS_SB_G1:
10955 case R_ARM_LDRS_SB_G2:
10956 {
10957 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10958 bfd_vma pc = input_section->output_section->vma
4962c51a 10959 + input_section->output_offset + rel->r_offset;
31a91d61 10960 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10961 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 10962 bfd_vma residual;
4962c51a 10963 bfd_signed_vma signed_value;
99059e56
RM		 10964 int group = 0;
10965
10966 /* Determine which groups of bits to calculate. */
10967 switch (r_type)
10968 {
10969 case R_ARM_LDRS_PC_G0:
10970 case R_ARM_LDRS_SB_G0:
10971 group = 0;
10972 break;
10973
10974 case R_ARM_LDRS_PC_G1:
10975 case R_ARM_LDRS_SB_G1:
10976 group = 1;
10977 break;
10978
10979 case R_ARM_LDRS_PC_G2:
10980 case R_ARM_LDRS_SB_G2:
10981 group = 2;
10982 break;
10983
10984 default:
10985 abort ();
10986 }
10987
10988 /* If REL, extract the addend from the insn. If RELA, it will
10989 have already been fetched for us. */
4962c51a 10990 if (globals->use_rel)
99059e56
RM		 10991 {
10992 int negative = (insn & (1 << 23)) ? 1 : -1;
10993 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
10994 }
4962c51a
MS		 10995
10996 /* Compute the value (X) to go in the place. */
99059e56
RM		 10997 if (r_type == R_ARM_LDRS_PC_G0
10998 || r_type == R_ARM_LDRS_PC_G1
10999 || r_type == R_ARM_LDRS_PC_G2)
11000 /* PC relative. */
11001 signed_value = value - pc + signed_addend;
11002 else
11003 /* Section base relative. */
11004 signed_value = value - sb + signed_addend;
11005
11006 /* Calculate the value of the relevant G_{n-1} to obtain
11007 the residual at that stage. */
b6518b38
NC		 11008 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11009 group - 1, &residual);
99059e56
RM		 11010
11011 /* Check for overflow. */
11012 if (residual >= 0x100)
11013 {
11014 (*_bfd_error_handler)
11015 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 11016 input_bfd, input_section,
11017 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11018 return bfd_reloc_overflow;
11019 }
11020
11021 /* Mask out the value and U bit. */
11022 insn &= 0xff7ff0f0;
11023
11024 /* Set the U bit if the value to go in the place is non-negative. */
11025 if (signed_value >= 0)
11026 insn |= 1 << 23;
11027
11028 /* Encode the offset. */
11029 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 11030
11031 bfd_put_32 (input_bfd, insn, hit_data);
11032 }
11033 return bfd_reloc_ok;
11034
11035 case R_ARM_LDC_PC_G0:
11036 case R_ARM_LDC_PC_G1:
11037 case R_ARM_LDC_PC_G2:
11038 case R_ARM_LDC_SB_G0:
11039 case R_ARM_LDC_SB_G1:
11040 case R_ARM_LDC_SB_G2:
11041 {
11042 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11043 bfd_vma pc = input_section->output_section->vma
4962c51a 11044 + input_section->output_offset + rel->r_offset;
31a91d61 11045 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11046 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11047 bfd_vma residual;
4962c51a 11048 bfd_signed_vma signed_value;
99059e56
RM		 11049 int group = 0;
11050
11051 /* Determine which groups of bits to calculate. */
11052 switch (r_type)
11053 {
11054 case R_ARM_LDC_PC_G0:
11055 case R_ARM_LDC_SB_G0:
11056 group = 0;
11057 break;
11058
11059 case R_ARM_LDC_PC_G1:
11060 case R_ARM_LDC_SB_G1:
11061 group = 1;
11062 break;
11063
11064 case R_ARM_LDC_PC_G2:
11065 case R_ARM_LDC_SB_G2:
11066 group = 2;
11067 break;
11068
11069 default:
11070 abort ();
11071 }
11072
11073 /* If REL, extract the addend from the insn. If RELA, it will
11074 have already been fetched for us. */
4962c51a 11075 if (globals->use_rel)
99059e56
RM		 11076 {
11077 int negative = (insn & (1 << 23)) ? 1 : -1;
11078 signed_addend = negative * ((insn & 0xff) << 2);
11079 }
4962c51a
MS		 11080
11081 /* Compute the value (X) to go in the place. */
99059e56
RM		 11082 if (r_type == R_ARM_LDC_PC_G0
11083 || r_type == R_ARM_LDC_PC_G1
11084 || r_type == R_ARM_LDC_PC_G2)
11085 /* PC relative. */
11086 signed_value = value - pc + signed_addend;
11087 else
11088 /* Section base relative. */
11089 signed_value = value - sb + signed_addend;
11090
11091 /* Calculate the value of the relevant G_{n-1} to obtain
11092 the residual at that stage. */
b6518b38
NC		 11093 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11094 group - 1, &residual);
99059e56
RM		 11095
11096 /* Check for overflow. (The absolute value to go in the place must be
11097 divisible by four and, after having been divided by four, must
11098 fit in eight bits.) */
11099 if ((residual & 0x3) != 0 || residual >= 0x400)
11100 {
11101 (*_bfd_error_handler)
11102 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
11103 input_bfd, input_section,
b6518b38 11104 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11105 return bfd_reloc_overflow;
11106 }
11107
11108 /* Mask out the value and U bit. */
11109 insn &= 0xff7fff00;
11110
11111 /* Set the U bit if the value to go in the place is non-negative. */
11112 if (signed_value >= 0)
11113 insn |= 1 << 23;
11114
11115 /* Encode the offset. */
11116 insn |= residual >> 2;
4962c51a
MS		 11117
11118 bfd_put_32 (input_bfd, insn, hit_data);
11119 }
11120 return bfd_reloc_ok;
11121
72d98d16
MG		 11122 case R_ARM_THM_ALU_ABS_G0_NC:
11123 case R_ARM_THM_ALU_ABS_G1_NC:
11124 case R_ARM_THM_ALU_ABS_G2_NC:
11125 case R_ARM_THM_ALU_ABS_G3_NC:
11126 {
11127 const int shift_array[4] = {0, 8, 16, 24};
11128 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
11129 bfd_vma addr = value;
11130 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
11131
11132 /* Compute address. */
11133 if (globals->use_rel)
11134 signed_addend = insn & 0xff;
11135 addr += signed_addend;
11136 if (branch_type == ST_BRANCH_TO_THUMB)
11137 addr |= 1;
11138 /* Clean imm8 insn. */
11139 insn &= 0xff00;
11140 /* And update with correct part of address. */
11141 insn |= (addr >> shift) & 0xff;
11142 /* Update insn. */
11143 bfd_put_16 (input_bfd, insn, hit_data);
11144 }
11145
11146 *unresolved_reloc_p = FALSE;
11147 return bfd_reloc_ok;
11148
252b5132
RH		 11149 default:
11150 return bfd_reloc_notsupported;
11151 }
11152}
11153
98c1d4aa
NC		 11154/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
11155static void
57e8b36a
NC		 11156arm_add_to_rel (bfd * abfd,
11157 bfd_byte * address,
11158 reloc_howto_type * howto,
11159 bfd_signed_vma increment)
98c1d4aa 11160{
98c1d4aa
NC		 11161 bfd_signed_vma addend;
11162
bd97cb95
DJ		 11163 if (howto->type == R_ARM_THM_CALL
11164 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 11165 {
9a5aca8c
AM		 11166 int upper_insn, lower_insn;
11167 int upper, lower;
98c1d4aa 11168
9a5aca8c
AM		 11169 upper_insn = bfd_get_16 (abfd, address);
11170 lower_insn = bfd_get_16 (abfd, address + 2);
11171 upper = upper_insn & 0x7ff;
11172 lower = lower_insn & 0x7ff;
11173
11174 addend = (upper << 12) | (lower << 1);
ddda4409 11175 addend += increment;
9a5aca8c 11176 addend >>= 1;
98c1d4aa 11177
9a5aca8c
AM		 11178 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
11179 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
11180
dc810e39
AM		 11181 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
11182 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 11183 }
11184 else
11185 {
11186 bfd_vma contents;
11187
11188 contents = bfd_get_32 (abfd, address);
11189
11190 /* Get the (signed) value from the instruction. */
11191 addend = contents & howto->src_mask;
11192 if (addend & ((howto->src_mask + 1) >> 1))
11193 {
11194 bfd_signed_vma mask;
11195
11196 mask = -1;
11197 mask &= ~ howto->src_mask;
11198 addend |= mask;
11199 }
11200
11201 /* Add in the increment, (which is a byte value). */
11202 switch (howto->type)
11203 {
11204 default:
11205 addend += increment;
11206 break;
11207
11208 case R_ARM_PC24:
c6596c5e 11209 case R_ARM_PLT32:
5b5bb741
PB		 11210 case R_ARM_CALL:
11211 case R_ARM_JUMP24:
9a5aca8c 11212 addend <<= howto->size;
dc810e39 11213 addend += increment;
9a5aca8c
AM		 11214
11215 /* Should we check for overflow here ? */
11216
11217 /* Drop any undesired bits. */
11218 addend >>= howto->rightshift;
11219 break;
11220 }
11221
11222 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
11223
11224 bfd_put_32 (abfd, contents, address);
ddda4409 11225 }
98c1d4aa 11226}
252b5132 11227
ba93b8ac
DJ		 11228#define IS_ARM_TLS_RELOC(R_TYPE) \
11229 ((R_TYPE) == R_ARM_TLS_GD32 \
11230 || (R_TYPE) == R_ARM_TLS_LDO32 \
11231 || (R_TYPE) == R_ARM_TLS_LDM32 \
11232 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
11233 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
11234 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
11235 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 11236 || (R_TYPE) == R_ARM_TLS_IE32 \
11237 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
11238
11239/* Specific set of relocations for the gnu tls dialect. */
11240#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
11241 ((R_TYPE) == R_ARM_TLS_GOTDESC \
11242 || (R_TYPE) == R_ARM_TLS_CALL \
11243 || (R_TYPE) == R_ARM_THM_TLS_CALL \
11244 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
11245 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 11246
252b5132 11247/* Relocate an ARM ELF section. */
906e58ca 11248
b34976b6 11249static bfd_boolean
57e8b36a
NC		 11250elf32_arm_relocate_section (bfd * output_bfd,
11251 struct bfd_link_info * info,
11252 bfd * input_bfd,
11253 asection * input_section,
11254 bfd_byte * contents,
11255 Elf_Internal_Rela * relocs,
11256 Elf_Internal_Sym * local_syms,
11257 asection ** local_sections)
252b5132 11258{
b34976b6
AM		 11259 Elf_Internal_Shdr *symtab_hdr;
11260 struct elf_link_hash_entry **sym_hashes;
11261 Elf_Internal_Rela *rel;
11262 Elf_Internal_Rela *relend;
11263 const char *name;
b32d3aa2 11264 struct elf32_arm_link_hash_table * globals;
252b5132 11265
4e7fd91e 11266 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 11267 if (globals == NULL)
11268 return FALSE;
b491616a 11269
0ffa91dd 11270 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 11271 sym_hashes = elf_sym_hashes (input_bfd);
11272
11273 rel = relocs;
11274 relend = relocs + input_section->reloc_count;
11275 for (; rel < relend; rel++)
11276 {
ba96a88f
NC		 11277 int r_type;
11278 reloc_howto_type * howto;
11279 unsigned long r_symndx;
11280 Elf_Internal_Sym * sym;
11281 asection * sec;
252b5132 11282 struct elf_link_hash_entry * h;
ba96a88f
NC		 11283 bfd_vma relocation;
11284 bfd_reloc_status_type r;
11285 arelent bfd_reloc;
ba93b8ac 11286 char sym_type;
0945cdfd 11287 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 11288 char *error_message = NULL;
f21f3fe0 11289
252b5132 11290 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 11291 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 11292 r_type = arm_real_reloc_type (globals, r_type);
252b5132 11293
ba96a88f 11294 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 11295 || r_type == R_ARM_GNU_VTINHERIT)
11296 continue;
252b5132 11297
b32d3aa2 11298 bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
ba96a88f 11299 howto = bfd_reloc.howto;
252b5132 11300
252b5132
RH		 11301 h = NULL;
11302 sym = NULL;
11303 sec = NULL;
9b485d32 11304
252b5132
RH		 11305 if (r_symndx < symtab_hdr->sh_info)
11306 {
11307 sym = local_syms + r_symndx;
ba93b8ac 11308 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 11309 sec = local_sections[r_symndx];
ffcb4889
NS		 11310
11311 /* An object file might have a reference to a local
11312 undefined symbol. This is a daft object file, but we
11313 should at least do something about it. V4BX & NONE
11314 relocations do not use the symbol and are explicitly
77b4f08f
TS		 11315 allowed to use the undefined symbol, so allow those.
11316 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 11317 if (r_type != R_ARM_V4BX
11318 && r_type != R_ARM_NONE
77b4f08f 11319 && r_symndx != STN_UNDEF
ffcb4889
NS		 11320 && bfd_is_und_section (sec)
11321 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
11322 {
11323 if (!info->callbacks->undefined_symbol
11324 (info, bfd_elf_string_from_elf_section
11325 (input_bfd, symtab_hdr->sh_link, sym->st_name),
11326 input_bfd, input_section,
11327 rel->r_offset, TRUE))
11328 return FALSE;
11329 }
b38cadfb 11330
4e7fd91e 11331 if (globals->use_rel)
f8df10f4 11332 {
4e7fd91e
PB		 11333 relocation = (sec->output_section->vma
11334 + sec->output_offset
11335 + sym->st_value);
0e1862bb 11336 if (!bfd_link_relocatable (info)
ab96bf03
AM		 11337 && (sec->flags & SEC_MERGE)
11338 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 11339 {
4e7fd91e
PB		 11340 asection *msec;
11341 bfd_vma addend, value;
11342
39623e12 11343 switch (r_type)
4e7fd91e 11344 {
39623e12
PB		 11345 case R_ARM_MOVW_ABS_NC:
11346 case R_ARM_MOVT_ABS:
11347 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
11348 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
11349 addend = (addend ^ 0x8000) - 0x8000;
11350 break;
f8df10f4 11351
39623e12
PB		 11352 case R_ARM_THM_MOVW_ABS_NC:
11353 case R_ARM_THM_MOVT_ABS:
11354 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
11355 << 16;
11356 value |= bfd_get_16 (input_bfd,
11357 contents + rel->r_offset + 2);
11358 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
11359 | ((value & 0x04000000) >> 15);
11360 addend = (addend ^ 0x8000) - 0x8000;
11361 break;
f8df10f4 11362
39623e12
PB		 11363 default:
11364 if (howto->rightshift
11365 || (howto->src_mask & (howto->src_mask + 1)))
11366 {
11367 (*_bfd_error_handler)
11368 (_("%B(%A+0x%lx): %s relocation against SEC_MERGE section"),
11369 input_bfd, input_section,
11370 (long) rel->r_offset, howto->name);
11371 return FALSE;
11372 }
11373
11374 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
11375
11376 /* Get the (signed) value from the instruction. */
11377 addend = value & howto->src_mask;
11378 if (addend & ((howto->src_mask + 1) >> 1))
11379 {
11380 bfd_signed_vma mask;
11381
11382 mask = -1;
11383 mask &= ~ howto->src_mask;
11384 addend |= mask;
11385 }
11386 break;
4e7fd91e 11387 }
39623e12 11388
4e7fd91e
PB		 11389 msec = sec;
11390 addend =
11391 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
11392 - relocation;
11393 addend += msec->output_section->vma + msec->output_offset;
39623e12 11394
cc643b88 11395 /* Cases here must match those in the preceding
39623e12
PB		 11396 switch statement. */
11397 switch (r_type)
11398 {
11399 case R_ARM_MOVW_ABS_NC:
11400 case R_ARM_MOVT_ABS:
11401 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
11402 | (addend & 0xfff);
11403 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
11404 break;
11405
11406 case R_ARM_THM_MOVW_ABS_NC:
11407 case R_ARM_THM_MOVT_ABS:
11408 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
11409 | (addend & 0xff) | ((addend & 0x0800) << 15);
11410 bfd_put_16 (input_bfd, value >> 16,
11411 contents + rel->r_offset);
11412 bfd_put_16 (input_bfd, value,
11413 contents + rel->r_offset + 2);
11414 break;
11415
11416 default:
11417 value = (value & ~ howto->dst_mask)
11418 | (addend & howto->dst_mask);
11419 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
11420 break;
11421 }
f8df10f4 11422 }
f8df10f4 11423 }
4e7fd91e
PB		 11424 else
11425 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 11426 }
11427 else
11428 {
62d887d4 11429 bfd_boolean warned, ignored;
560e09e9 11430
b2a8e766
AM		 11431 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
11432 r_symndx, symtab_hdr, sym_hashes,
11433 h, sec, relocation,
62d887d4 11434 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 11435
11436 sym_type = h->type;
252b5132
RH		 11437 }
11438
dbaa2011 11439 if (sec != NULL && discarded_section (sec))
e4067dbb 11440 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 11441 rel, 1, relend, howto, 0, contents);
ab96bf03 11442
0e1862bb 11443 if (bfd_link_relocatable (info))
ab96bf03
AM		 11444 {
11445 /* This is a relocatable link. We don't have to change
11446 anything, unless the reloc is against a section symbol,
11447 in which case we have to adjust according to where the
11448 section symbol winds up in the output section. */
11449 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
11450 {
11451 if (globals->use_rel)
11452 arm_add_to_rel (input_bfd, contents + rel->r_offset,
11453 howto, (bfd_signed_vma) sec->output_offset);
11454 else
11455 rel->r_addend += sec->output_offset;
11456 }
11457 continue;
11458 }
11459
252b5132
RH		 11460 if (h != NULL)
11461 name = h->root.root.string;
11462 else
11463 {
11464 name = (bfd_elf_string_from_elf_section
11465 (input_bfd, symtab_hdr->sh_link, sym->st_name));
11466 if (name == NULL || *name == '\0')
11467 name = bfd_section_name (input_bfd, sec);
11468 }
f21f3fe0 11469
cf35638d 11470 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 11471 && r_type != R_ARM_NONE
11472 && (h == NULL
11473 || h->root.type == bfd_link_hash_defined
11474 || h->root.type == bfd_link_hash_defweak)
11475 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
11476 {
11477 (*_bfd_error_handler)
11478 ((sym_type == STT_TLS
11479 ? _("%B(%A+0x%lx): %s used with TLS symbol %s")
11480 : _("%B(%A+0x%lx): %s used with non-TLS symbol %s")),
11481 input_bfd,
11482 input_section,
11483 (long) rel->r_offset,
11484 howto->name,
11485 name);
11486 }
11487
0855e32b 11488 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 11489 done, i.e., the relaxation produced the final output we want,
11490 and we won't let anybody mess with it. Also, we have to do
11491 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 11492 both in relaxed and non-relaxed cases. */
0855e32b
NS		 11493 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
11494 || (IS_ARM_TLS_GNU_RELOC (r_type)
b38cadfb 11495 && !((h ? elf32_arm_hash_entry (h)->tls_type :
0855e32b
NS		 11496 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
11497 & GOT_TLS_GDESC)))
11498 {
11499 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
11500 contents, rel, h == NULL);
11501 /* This may have been marked unresolved because it came from
11502 a shared library. But we've just dealt with that. */
11503 unresolved_reloc = 0;
11504 }
11505 else
11506 r = bfd_reloc_continue;
b38cadfb 11507
0855e32b
NS		 11508 if (r == bfd_reloc_continue)
11509 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
11510 input_section, contents, rel,
34e77a92 11511 relocation, info, sec, name, sym_type,
35fc36a8
RS		 11512 (h ? h->target_internal
11513 : ARM_SYM_BRANCH_TYPE (sym)), h,
0855e32b 11514 &unresolved_reloc, &error_message);
0945cdfd
DJ		 11515
11516 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
11517 because such sections are not SEC_ALLOC and thus ld.so will
11518 not process them. */
11519 if (unresolved_reloc
99059e56
RM		 11520 && !((input_section->flags & SEC_DEBUGGING) != 0
11521 && h->def_dynamic)
1d5316ab
AM		 11522 && _bfd_elf_section_offset (output_bfd, info, input_section,
11523 rel->r_offset) != (bfd_vma) -1)
0945cdfd
DJ		 11524 {
11525 (*_bfd_error_handler)
843fe662
L		 11526 (_("%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"),
11527 input_bfd,
11528 input_section,
11529 (long) rel->r_offset,
11530 howto->name,
11531 h->root.root.string);
0945cdfd
DJ		 11532 return FALSE;
11533 }
252b5132
RH		 11534
11535 if (r != bfd_reloc_ok)
11536 {
252b5132
RH		 11537 switch (r)
11538 {
11539 case bfd_reloc_overflow:
cf919dfd
PB		 11540 /* If the overflowing reloc was to an undefined symbol,
11541 we have already printed one error message and there
11542 is no point complaining again. */
11543 if ((! h ||
11544 h->root.type != bfd_link_hash_undefined)
11545 && (!((*info->callbacks->reloc_overflow)
dfeffb9f
L		 11546 (info, (h ? &h->root : NULL), name, howto->name,
11547 (bfd_vma) 0, input_bfd, input_section,
11548 rel->r_offset))))
b34976b6 11549 return FALSE;
252b5132
RH		 11550 break;
11551
11552 case bfd_reloc_undefined:
11553 if (!((*info->callbacks->undefined_symbol)
11554 (info, name, input_bfd, input_section,
b34976b6
AM		 11555 rel->r_offset, TRUE)))
11556 return FALSE;
252b5132
RH		 11557 break;
11558
11559 case bfd_reloc_outofrange:
f2a9dd69 11560 error_message = _("out of range");
252b5132
RH		 11561 goto common_error;
11562
11563 case bfd_reloc_notsupported:
f2a9dd69 11564 error_message = _("unsupported relocation");
252b5132
RH		 11565 goto common_error;
11566
11567 case bfd_reloc_dangerous:
f2a9dd69 11568 /* error_message should already be set. */
252b5132
RH		 11569 goto common_error;
11570
11571 default:
f2a9dd69 11572 error_message = _("unknown error");
8029a119 11573 /* Fall through. */
252b5132
RH		 11574
11575 common_error:
f2a9dd69
DJ		 11576 BFD_ASSERT (error_message != NULL);
11577 if (!((*info->callbacks->reloc_dangerous)
11578 (info, error_message, input_bfd, input_section,
252b5132 11579 rel->r_offset)))
b34976b6 11580 return FALSE;
252b5132
RH		 11581 break;
11582 }
11583 }
11584 }
11585
b34976b6 11586 return TRUE;
252b5132
RH		 11587}
11588
91d6fa6a 11589/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 11590 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 11591 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 11592 maintaining that condition). */
11593
11594static void
11595add_unwind_table_edit (arm_unwind_table_edit **head,
11596 arm_unwind_table_edit **tail,
11597 arm_unwind_edit_type type,
11598 asection *linked_section,
91d6fa6a 11599 unsigned int tindex)
2468f9c9 11600{
21d799b5
NC		 11601 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
11602 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 11603
2468f9c9
PB		 11604 new_edit->type = type;
11605 new_edit->linked_section = linked_section;
91d6fa6a 11606 new_edit->index = tindex;
b38cadfb 11607
91d6fa6a 11608 if (tindex > 0)
2468f9c9
PB		 11609 {
11610 new_edit->next = NULL;
11611
11612 if (*tail)
11613 (*tail)->next = new_edit;
11614
11615 (*tail) = new_edit;
11616
11617 if (!*head)
11618 (*head) = new_edit;
11619 }
11620 else
11621 {
11622 new_edit->next = *head;
11623
11624 if (!*tail)
11625 *tail = new_edit;
11626
11627 *head = new_edit;
11628 }
11629}
11630
11631static _arm_elf_section_data *get_arm_elf_section_data (asection *);
11632
11633/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
11634static void
11635adjust_exidx_size(asection *exidx_sec, int adjust)
11636{
11637 asection *out_sec;
11638
11639 if (!exidx_sec->rawsize)
11640 exidx_sec->rawsize = exidx_sec->size;
11641
11642 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
11643 out_sec = exidx_sec->output_section;
11644 /* Adjust size of output section. */
11645 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
11646}
11647
11648/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
11649static void
11650insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
11651{
11652 struct _arm_elf_section_data *exidx_arm_data;
11653
11654 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
11655 add_unwind_table_edit (
11656 &exidx_arm_data->u.exidx.unwind_edit_list,
11657 &exidx_arm_data->u.exidx.unwind_edit_tail,
11658 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
11659
491d01d3
YU		 11660 exidx_arm_data->additional_reloc_count++;
11661
2468f9c9
PB		 11662 adjust_exidx_size(exidx_sec, 8);
11663}
11664
11665/* Scan .ARM.exidx tables, and create a list describing edits which should be
11666 made to those tables, such that:
b38cadfb 11667
2468f9c9
PB		 11668 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
11669 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 11670 codes which have been inlined into the index).
2468f9c9 11671
85fdf906
AH		 11672 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
11673
2468f9c9 11674 The edits are applied when the tables are written
b38cadfb 11675 (in elf32_arm_write_section). */
2468f9c9
PB		 11676
11677bfd_boolean
11678elf32_arm_fix_exidx_coverage (asection **text_section_order,
11679 unsigned int num_text_sections,
85fdf906
AH		 11680 struct bfd_link_info *info,
11681 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 11682{
11683 bfd *inp;
11684 unsigned int last_second_word = 0, i;
11685 asection *last_exidx_sec = NULL;
11686 asection *last_text_sec = NULL;
11687 int last_unwind_type = -1;
11688
11689 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
11690 text sections. */
c72f2fb2 11691 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 11692 {
11693 asection *sec;
b38cadfb 11694
2468f9c9 11695 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 11696 {
2468f9c9
PB		 11697 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
11698 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 11699
dec9d5df 11700 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 11701 continue;
b38cadfb 11702
2468f9c9
PB		 11703 if (elf_sec->linked_to)
11704 {
11705 Elf_Internal_Shdr *linked_hdr
99059e56 11706 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 11707 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 11708 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 11709
11710 if (linked_sec_arm_data == NULL)
99059e56 11711 continue;
2468f9c9
PB		 11712
11713 /* Link this .ARM.exidx section back from the text section it
99059e56 11714 describes. */
2468f9c9
PB		 11715 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
11716 }
11717 }
11718 }
11719
11720 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
11721 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 11722 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 11723
11724 for (i = 0; i < num_text_sections; i++)
11725 {
11726 asection *sec = text_section_order[i];
11727 asection *exidx_sec;
11728 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
11729 struct _arm_elf_section_data *exidx_arm_data;
11730 bfd_byte *contents = NULL;
11731 int deleted_exidx_bytes = 0;
11732 bfd_vma j;
11733 arm_unwind_table_edit *unwind_edit_head = NULL;
11734 arm_unwind_table_edit *unwind_edit_tail = NULL;
11735 Elf_Internal_Shdr *hdr;
11736 bfd *ibfd;
11737
11738 if (arm_data == NULL)
99059e56 11739 continue;
2468f9c9
PB		 11740
11741 exidx_sec = arm_data->u.text.arm_exidx_sec;
11742 if (exidx_sec == NULL)
11743 {
11744 /* Section has no unwind data. */
11745 if (last_unwind_type == 0 || !last_exidx_sec)
11746 continue;
11747
11748 /* Ignore zero sized sections. */
11749 if (sec->size == 0)
11750 continue;
11751
11752 insert_cantunwind_after(last_text_sec, last_exidx_sec);
11753 last_unwind_type = 0;
11754 continue;
11755 }
11756
22a8f80e
PB		 11757 /* Skip /DISCARD/ sections. */
11758 if (bfd_is_abs_section (exidx_sec->output_section))
11759 continue;
11760
2468f9c9
PB		 11761 hdr = &elf_section_data (exidx_sec)->this_hdr;
11762 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 11763 continue;
b38cadfb 11764
2468f9c9
PB		 11765 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
11766 if (exidx_arm_data == NULL)
99059e56 11767 continue;
b38cadfb 11768
2468f9c9 11769 ibfd = exidx_sec->owner;
b38cadfb 11770
2468f9c9
PB		 11771 if (hdr->contents != NULL)
11772 contents = hdr->contents;
11773 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
11774 /* An error? */
11775 continue;
11776
ac06903d
YU		 11777 if (last_unwind_type > 0)
11778 {
11779 unsigned int first_word = bfd_get_32 (ibfd, contents);
11780 /* Add cantunwind if first unwind item does not match section
11781 start. */
11782 if (first_word != sec->vma)
11783 {
11784 insert_cantunwind_after (last_text_sec, last_exidx_sec);
11785 last_unwind_type = 0;
11786 }
11787 }
11788
2468f9c9
PB		 11789 for (j = 0; j < hdr->sh_size; j += 8)
11790 {
11791 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
11792 int unwind_type;
11793 int elide = 0;
11794
11795 /* An EXIDX_CANTUNWIND entry. */
11796 if (second_word == 1)
11797 {
11798 if (last_unwind_type == 0)
11799 elide = 1;
11800 unwind_type = 0;
11801 }
11802 /* Inlined unwinding data. Merge if equal to previous. */
11803 else if ((second_word & 0x80000000) != 0)
11804 {
85fdf906
AH		 11805 if (merge_exidx_entries
11806 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 11807 elide = 1;
11808 unwind_type = 1;
11809 last_second_word = second_word;
11810 }
11811 /* Normal table entry. In theory we could merge these too,
11812 but duplicate entries are likely to be much less common. */
11813 else
11814 unwind_type = 2;
11815
491d01d3 11816 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 11817 {
11818 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
11819 DELETE_EXIDX_ENTRY, NULL, j / 8);
11820
11821 deleted_exidx_bytes += 8;
11822 }
11823
11824 last_unwind_type = unwind_type;
11825 }
11826
11827 /* Free contents if we allocated it ourselves. */
11828 if (contents != hdr->contents)
99059e56 11829 free (contents);
2468f9c9
PB		 11830
11831 /* Record edits to be applied later (in elf32_arm_write_section). */
11832 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
11833 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 11834
2468f9c9
PB		 11835 if (deleted_exidx_bytes > 0)
11836 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
11837
11838 last_exidx_sec = exidx_sec;
11839 last_text_sec = sec;
11840 }
11841
11842 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 11843 if (!bfd_link_relocatable (info) && last_exidx_sec
11844 && last_unwind_type != 0)
2468f9c9
PB		 11845 insert_cantunwind_after(last_text_sec, last_exidx_sec);
11846
11847 return TRUE;
11848}
11849
3e6b1042
DJ		 11850static bfd_boolean
11851elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
11852 bfd *ibfd, const char *name)
11853{
11854 asection *sec, *osec;
11855
3d4d4302 11856 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 11857 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
11858 return TRUE;
11859
11860 osec = sec->output_section;
11861 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
11862 return TRUE;
11863
11864 if (! bfd_set_section_contents (obfd, osec, sec->contents,
11865 sec->output_offset, sec->size))
11866 return FALSE;
11867
11868 return TRUE;
11869}
11870
11871static bfd_boolean
11872elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
11873{
11874 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 11875 asection *sec, *osec;
3e6b1042 11876
4dfe6ac6
NC		 11877 if (globals == NULL)
11878 return FALSE;
11879
3e6b1042
DJ		 11880 /* Invoke the regular ELF backend linker to do all the work. */
11881 if (!bfd_elf_final_link (abfd, info))
11882 return FALSE;
11883
fe33d2fa
CL		 11884 /* Process stub sections (eg BE8 encoding, ...). */
11885 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 11886 unsigned int i;
cdb21a0a
NS		 11887 for (i=0; i<htab->top_id; i++)
11888 {
11889 sec = htab->stub_group[i].stub_sec;
11890 /* Only process it once, in its link_sec slot. */
11891 if (sec && i == htab->stub_group[i].link_sec->id)
11892 {
11893 osec = sec->output_section;
11894 elf32_arm_write_section (abfd, info, sec, sec->contents);
11895 if (! bfd_set_section_contents (abfd, osec, sec->contents,
11896 sec->output_offset, sec->size))
11897 return FALSE;
11898 }
fe33d2fa 11899 }
fe33d2fa 11900
3e6b1042
DJ		 11901 /* Write out any glue sections now that we have created all the
11902 stubs. */
11903 if (globals->bfd_of_glue_owner != NULL)
11904 {
11905 if (! elf32_arm_output_glue_section (info, abfd,
11906 globals->bfd_of_glue_owner,
11907 ARM2THUMB_GLUE_SECTION_NAME))
11908 return FALSE;
11909
11910 if (! elf32_arm_output_glue_section (info, abfd,
11911 globals->bfd_of_glue_owner,
11912 THUMB2ARM_GLUE_SECTION_NAME))
11913 return FALSE;
11914
11915 if (! elf32_arm_output_glue_section (info, abfd,
11916 globals->bfd_of_glue_owner,
11917 VFP11_ERRATUM_VENEER_SECTION_NAME))
11918 return FALSE;
11919
a504d23a
LA		 11920 if (! elf32_arm_output_glue_section (info, abfd,
11921 globals->bfd_of_glue_owner,
11922 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
11923 return FALSE;
11924
3e6b1042
DJ		 11925 if (! elf32_arm_output_glue_section (info, abfd,
11926 globals->bfd_of_glue_owner,
11927 ARM_BX_GLUE_SECTION_NAME))
11928 return FALSE;
11929 }
11930
11931 return TRUE;
11932}
11933
5968a7b8
NC		 11934/* Return a best guess for the machine number based on the attributes. */
11935
11936static unsigned int
11937bfd_arm_get_mach_from_attributes (bfd * abfd)
11938{
11939 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
11940
11941 switch (arch)
11942 {
11943 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
11944 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
11945 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
11946
11947 case TAG_CPU_ARCH_V5TE:
11948 {
11949 char * name;
11950
11951 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
11952 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
11953
11954 if (name)
11955 {
11956 if (strcmp (name, "IWMMXT2") == 0)
11957 return bfd_mach_arm_iWMMXt2;
11958
11959 if (strcmp (name, "IWMMXT") == 0)
6034aab8 11960 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 11961
11962 if (strcmp (name, "XSCALE") == 0)
11963 {
11964 int wmmx;
11965
11966 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
11967 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
11968 switch (wmmx)
11969 {
11970 case 1: return bfd_mach_arm_iWMMXt;
11971 case 2: return bfd_mach_arm_iWMMXt2;
11972 default: return bfd_mach_arm_XScale;
11973 }
11974 }
5968a7b8
NC		 11975 }
11976
11977 return bfd_mach_arm_5TE;
11978 }
11979
11980 default:
11981 return bfd_mach_arm_unknown;
11982 }
11983}
11984
c178919b
NC		 11985/* Set the right machine number. */
11986
11987static bfd_boolean
57e8b36a 11988elf32_arm_object_p (bfd *abfd)
c178919b 11989{
5a6c6817 11990 unsigned int mach;
57e8b36a 11991
5a6c6817 11992 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 11993
5968a7b8
NC		 11994 if (mach == bfd_mach_arm_unknown)
11995 {
11996 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
11997 mach = bfd_mach_arm_ep9312;
11998 else
11999 mach = bfd_arm_get_mach_from_attributes (abfd);
12000 }
c178919b 12001
5968a7b8 12002 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 12003 return TRUE;
12004}
12005
fc830a83 12006/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 12007
b34976b6 12008static bfd_boolean
57e8b36a 12009elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 12010{
12011 if (elf_flags_init (abfd)
12012 && elf_elfheader (abfd)->e_flags != flags)
12013 {
fc830a83
NC		 12014 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
12015 {
fd2ec330 12016 if (flags & EF_ARM_INTERWORK)
d003868e
AM		 12017 (*_bfd_error_handler)
12018 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
12019 abfd);
fc830a83 12020 else
d003868e
AM		 12021 _bfd_error_handler
12022 (_("Warning: Clearing the interworking flag of %B due to outside request"),
12023 abfd);
fc830a83 12024 }
252b5132
RH		 12025 }
12026 else
12027 {
12028 elf_elfheader (abfd)->e_flags = flags;
b34976b6 12029 elf_flags_init (abfd) = TRUE;
252b5132
RH		 12030 }
12031
b34976b6 12032 return TRUE;
252b5132
RH		 12033}
12034
fc830a83 12035/* Copy backend specific data from one object module to another. */
9b485d32 12036
b34976b6 12037static bfd_boolean
57e8b36a 12038elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 12039{
12040 flagword in_flags;
12041 flagword out_flags;
12042
0ffa91dd 12043 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 12044 return TRUE;
252b5132 12045
fc830a83 12046 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 12047 out_flags = elf_elfheader (obfd)->e_flags;
12048
fc830a83
NC		 12049 if (elf_flags_init (obfd)
12050 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
12051 && in_flags != out_flags)
252b5132 12052 {
252b5132 12053 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 12054 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 12055 return FALSE;
252b5132
RH		 12056
12057 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 12058 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 12059 return FALSE;
252b5132
RH		 12060
12061 /* If the src and dest have different interworking flags
99059e56 12062 then turn off the interworking bit. */
fd2ec330 12063 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 12064 {
fd2ec330 12065 if (out_flags & EF_ARM_INTERWORK)
d003868e
AM		 12066 _bfd_error_handler
12067 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
12068 obfd, ibfd);
252b5132 12069
fd2ec330 12070 in_flags &= ~EF_ARM_INTERWORK;
252b5132 12071 }
1006ba19
PB		 12072
12073 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 12074 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
12075 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 12076 }
12077
12078 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 12079 elf_flags_init (obfd) = TRUE;
252b5132 12080
e2349352 12081 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 12082}
12083
12084/* Values for Tag_ABI_PCS_R9_use. */
12085enum
12086{
12087 AEABI_R9_V6,
12088 AEABI_R9_SB,
12089 AEABI_R9_TLS,
12090 AEABI_R9_unused
12091};
12092
12093/* Values for Tag_ABI_PCS_RW_data. */
12094enum
12095{
12096 AEABI_PCS_RW_data_absolute,
12097 AEABI_PCS_RW_data_PCrel,
12098 AEABI_PCS_RW_data_SBrel,
12099 AEABI_PCS_RW_data_unused
12100};
12101
12102/* Values for Tag_ABI_enum_size. */
12103enum
12104{
12105 AEABI_enum_unused,
12106 AEABI_enum_short,
12107 AEABI_enum_wide,
12108 AEABI_enum_forced_wide
12109};
12110
104d59d1
JM		 12111/* Determine whether an object attribute tag takes an integer, a
12112 string or both. */
906e58ca 12113
104d59d1
JM		 12114static int
12115elf32_arm_obj_attrs_arg_type (int tag)
12116{
12117 if (tag == Tag_compatibility)
3483fe2e 12118 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 12119 else if (tag == Tag_nodefaults)
3483fe2e
AS		 12120 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
12121 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
12122 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 12123 else if (tag < 32)
3483fe2e 12124 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 12125 else
3483fe2e 12126 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 12127}
12128
5aa6ff7c
AS		 12129/* The ABI defines that Tag_conformance should be emitted first, and that
12130 Tag_nodefaults should be second (if either is defined). This sets those
12131 two positions, and bumps up the position of all the remaining tags to
12132 compensate. */
12133static int
12134elf32_arm_obj_attrs_order (int num)
12135{
3de4a297 12136 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 12137 return Tag_conformance;
3de4a297 12138 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 12139 return Tag_nodefaults;
12140 if ((num - 2) < Tag_nodefaults)
12141 return num - 2;
12142 if ((num - 1) < Tag_conformance)
12143 return num - 1;
12144 return num;
12145}
12146
e8b36cd1
JM		 12147/* Attribute numbers >=64 (mod 128) can be safely ignored. */
12148static bfd_boolean
12149elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
12150{
12151 if ((tag & 127) < 64)
12152 {
12153 _bfd_error_handler
12154 (_("%B: Unknown mandatory EABI object attribute %d"),
12155 abfd, tag);
12156 bfd_set_error (bfd_error_bad_value);
12157 return FALSE;
12158 }
12159 else
12160 {
12161 _bfd_error_handler
12162 (_("Warning: %B: Unknown EABI object attribute %d"),
12163 abfd, tag);
12164 return TRUE;
12165 }
12166}
12167
91e22acd
AS		 12168/* Read the architecture from the Tag_also_compatible_with attribute, if any.
12169 Returns -1 if no architecture could be read. */
12170
12171static int
12172get_secondary_compatible_arch (bfd *abfd)
12173{
12174 obj_attribute *attr =
12175 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
12176
12177 /* Note: the tag and its argument below are uleb128 values, though
12178 currently-defined values fit in one byte for each. */
12179 if (attr->s
12180 && attr->s[0] == Tag_CPU_arch
12181 && (attr->s[1] & 128) != 128
12182 && attr->s[2] == 0)
12183 return attr->s[1];
12184
12185 /* This tag is "safely ignorable", so don't complain if it looks funny. */
12186 return -1;
12187}
12188
12189/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
12190 The tag is removed if ARCH is -1. */
12191
8e79c3df 12192static void
91e22acd 12193set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 12194{
91e22acd
AS		 12195 obj_attribute *attr =
12196 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 12197
91e22acd
AS		 12198 if (arch == -1)
12199 {
12200 attr->s = NULL;
12201 return;
8e79c3df 12202 }
91e22acd
AS		 12203
12204 /* Note: the tag and its argument below are uleb128 values, though
12205 currently-defined values fit in one byte for each. */
12206 if (!attr->s)
21d799b5 12207 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 12208 attr->s[0] = Tag_CPU_arch;
12209 attr->s[1] = arch;
12210 attr->s[2] = '\0';
8e79c3df
CM		 12211}
12212
91e22acd
AS		 12213/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
12214 into account. */
12215
12216static int
12217tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
12218 int newtag, int secondary_compat)
8e79c3df 12219{
91e22acd
AS		 12220#define T(X) TAG_CPU_ARCH_##X
12221 int tagl, tagh, result;
12222 const int v6t2[] =
12223 {
12224 T(V6T2), /* PRE_V4. */
12225 T(V6T2), /* V4. */
12226 T(V6T2), /* V4T. */
12227 T(V6T2), /* V5T. */
12228 T(V6T2), /* V5TE. */
12229 T(V6T2), /* V5TEJ. */
12230 T(V6T2), /* V6. */
12231 T(V7), /* V6KZ. */
12232 T(V6T2) /* V6T2. */
12233 };
12234 const int v6k[] =
12235 {
12236 T(V6K), /* PRE_V4. */
12237 T(V6K), /* V4. */
12238 T(V6K), /* V4T. */
12239 T(V6K), /* V5T. */
12240 T(V6K), /* V5TE. */
12241 T(V6K), /* V5TEJ. */
12242 T(V6K), /* V6. */
12243 T(V6KZ), /* V6KZ. */
12244 T(V7), /* V6T2. */
12245 T(V6K) /* V6K. */
12246 };
12247 const int v7[] =
12248 {
12249 T(V7), /* PRE_V4. */
12250 T(V7), /* V4. */
12251 T(V7), /* V4T. */
12252 T(V7), /* V5T. */
12253 T(V7), /* V5TE. */
12254 T(V7), /* V5TEJ. */
12255 T(V7), /* V6. */
12256 T(V7), /* V6KZ. */
12257 T(V7), /* V6T2. */
12258 T(V7), /* V6K. */
12259 T(V7) /* V7. */
12260 };
12261 const int v6_m[] =
12262 {
12263 -1, /* PRE_V4. */
12264 -1, /* V4. */
12265 T(V6K), /* V4T. */
12266 T(V6K), /* V5T. */
12267 T(V6K), /* V5TE. */
12268 T(V6K), /* V5TEJ. */
12269 T(V6K), /* V6. */
12270 T(V6KZ), /* V6KZ. */
12271 T(V7), /* V6T2. */
12272 T(V6K), /* V6K. */
12273 T(V7), /* V7. */
12274 T(V6_M) /* V6_M. */
12275 };
12276 const int v6s_m[] =
12277 {
12278 -1, /* PRE_V4. */
12279 -1, /* V4. */
12280 T(V6K), /* V4T. */
12281 T(V6K), /* V5T. */
12282 T(V6K), /* V5TE. */
12283 T(V6K), /* V5TEJ. */
12284 T(V6K), /* V6. */
12285 T(V6KZ), /* V6KZ. */
12286 T(V7), /* V6T2. */
12287 T(V6K), /* V6K. */
12288 T(V7), /* V7. */
12289 T(V6S_M), /* V6_M. */
12290 T(V6S_M) /* V6S_M. */
12291 };
9e3c6df6
PB		 12292 const int v7e_m[] =
12293 {
12294 -1, /* PRE_V4. */
12295 -1, /* V4. */
12296 T(V7E_M), /* V4T. */
12297 T(V7E_M), /* V5T. */
12298 T(V7E_M), /* V5TE. */
12299 T(V7E_M), /* V5TEJ. */
12300 T(V7E_M), /* V6. */
12301 T(V7E_M), /* V6KZ. */
12302 T(V7E_M), /* V6T2. */
12303 T(V7E_M), /* V6K. */
12304 T(V7E_M), /* V7. */
12305 T(V7E_M), /* V6_M. */
12306 T(V7E_M), /* V6S_M. */
12307 T(V7E_M) /* V7E_M. */
12308 };
bca38921
MGD		 12309 const int v8[] =
12310 {
12311 T(V8), /* PRE_V4. */
12312 T(V8), /* V4. */
12313 T(V8), /* V4T. */
12314 T(V8), /* V5T. */
12315 T(V8), /* V5TE. */
12316 T(V8), /* V5TEJ. */
12317 T(V8), /* V6. */
12318 T(V8), /* V6KZ. */
12319 T(V8), /* V6T2. */
12320 T(V8), /* V6K. */
12321 T(V8), /* V7. */
12322 T(V8), /* V6_M. */
12323 T(V8), /* V6S_M. */
12324 T(V8), /* V7E_M. */
12325 T(V8) /* V8. */
12326 };
2fd158eb
TP		 12327 const int v8m_baseline[] =
12328 {
12329 -1, /* PRE_V4. */
12330 -1, /* V4. */
12331 -1, /* V4T. */
12332 -1, /* V5T. */
12333 -1, /* V5TE. */
12334 -1, /* V5TEJ. */
12335 -1, /* V6. */
12336 -1, /* V6KZ. */
12337 -1, /* V6T2. */
12338 -1, /* V6K. */
12339 -1, /* V7. */
12340 T(V8M_BASE), /* V6_M. */
12341 T(V8M_BASE), /* V6S_M. */
12342 -1, /* V7E_M. */
12343 -1, /* V8. */
12344 -1,
12345 T(V8M_BASE) /* V8-M BASELINE. */
12346 };
12347 const int v8m_mainline[] =
12348 {
12349 -1, /* PRE_V4. */
12350 -1, /* V4. */
12351 -1, /* V4T. */
12352 -1, /* V5T. */
12353 -1, /* V5TE. */
12354 -1, /* V5TEJ. */
12355 -1, /* V6. */
12356 -1, /* V6KZ. */
12357 -1, /* V6T2. */
12358 -1, /* V6K. */
12359 T(V8M_MAIN), /* V7. */
12360 T(V8M_MAIN), /* V6_M. */
12361 T(V8M_MAIN), /* V6S_M. */
12362 T(V8M_MAIN), /* V7E_M. */
12363 -1, /* V8. */
12364 -1,
12365 T(V8M_MAIN), /* V8-M BASELINE. */
12366 T(V8M_MAIN) /* V8-M MAINLINE. */
12367 };
91e22acd
AS		 12368 const int v4t_plus_v6_m[] =
12369 {
12370 -1, /* PRE_V4. */
12371 -1, /* V4. */
12372 T(V4T), /* V4T. */
12373 T(V5T), /* V5T. */
12374 T(V5TE), /* V5TE. */
12375 T(V5TEJ), /* V5TEJ. */
12376 T(V6), /* V6. */
12377 T(V6KZ), /* V6KZ. */
12378 T(V6T2), /* V6T2. */
12379 T(V6K), /* V6K. */
12380 T(V7), /* V7. */
12381 T(V6_M), /* V6_M. */
12382 T(V6S_M), /* V6S_M. */
9e3c6df6 12383 T(V7E_M), /* V7E_M. */
bca38921 12384 T(V8), /* V8. */
4ed7ed8d 12385 -1, /* Unused. */
2fd158eb
TP		 12386 T(V8M_BASE), /* V8-M BASELINE. */
12387 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 12388 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
12389 };
12390 const int *comb[] =
12391 {
12392 v6t2,
12393 v6k,
12394 v7,
12395 v6_m,
12396 v6s_m,
9e3c6df6 12397 v7e_m,
bca38921 12398 v8,
4ed7ed8d 12399 NULL,
2fd158eb
TP		 12400 v8m_baseline,
12401 v8m_mainline,
91e22acd
AS		 12402 /* Pseudo-architecture. */
12403 v4t_plus_v6_m
12404 };
12405
12406 /* Check we've not got a higher architecture than we know about. */
12407
9e3c6df6 12408 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 12409 {
3895f852 12410 _bfd_error_handler (_("error: %B: Unknown CPU architecture"), ibfd);
91e22acd
AS		 12411 return -1;
12412 }
12413
12414 /* Override old tag if we have a Tag_also_compatible_with on the output. */
12415
12416 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
12417 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
12418 oldtag = T(V4T_PLUS_V6_M);
12419
12420 /* And override the new tag if we have a Tag_also_compatible_with on the
12421 input. */
12422
12423 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
12424 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
12425 newtag = T(V4T_PLUS_V6_M);
12426
12427 tagl = (oldtag < newtag) ? oldtag : newtag;
12428 result = tagh = (oldtag > newtag) ? oldtag : newtag;
12429
12430 /* Architectures before V6KZ add features monotonically. */
12431 if (tagh <= TAG_CPU_ARCH_V6KZ)
12432 return result;
12433
4ed7ed8d 12434 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 12435
12436 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
12437 as the canonical version. */
12438 if (result == T(V4T_PLUS_V6_M))
12439 {
12440 result = T(V4T);
12441 *secondary_compat_out = T(V6_M);
12442 }
12443 else
12444 *secondary_compat_out = -1;
12445
12446 if (result == -1)
12447 {
3895f852 12448 _bfd_error_handler (_("error: %B: Conflicting CPU architectures %d/%d"),
91e22acd
AS		 12449 ibfd, oldtag, newtag);
12450 return -1;
12451 }
12452
12453 return result;
12454#undef T
8e79c3df
CM		 12455}
12456
ac56ee8f
MGD		 12457/* Query attributes object to see if integer divide instructions may be
12458 present in an object. */
12459static bfd_boolean
12460elf32_arm_attributes_accept_div (const obj_attribute *attr)
12461{
12462 int arch = attr[Tag_CPU_arch].i;
12463 int profile = attr[Tag_CPU_arch_profile].i;
12464
12465 switch (attr[Tag_DIV_use].i)
12466 {
12467 case 0:
12468 /* Integer divide allowed if instruction contained in archetecture. */
12469 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
12470 return TRUE;
12471 else if (arch >= TAG_CPU_ARCH_V7E_M)
12472 return TRUE;
12473 else
12474 return FALSE;
12475
12476 case 1:
12477 /* Integer divide explicitly prohibited. */
12478 return FALSE;
12479
12480 default:
12481 /* Unrecognised case - treat as allowing divide everywhere. */
12482 case 2:
12483 /* Integer divide allowed in ARM state. */
12484 return TRUE;
12485 }
12486}
12487
12488/* Query attributes object to see if integer divide instructions are
12489 forbidden to be in the object. This is not the inverse of
12490 elf32_arm_attributes_accept_div. */
12491static bfd_boolean
12492elf32_arm_attributes_forbid_div (const obj_attribute *attr)
12493{
12494 return attr[Tag_DIV_use].i == 1;
12495}
12496
ee065d83
PB		 12497/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
12498 are conflicting attributes. */
906e58ca 12499
ee065d83
PB		 12500static bfd_boolean
12501elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd)
12502{
104d59d1
JM		 12503 obj_attribute *in_attr;
12504 obj_attribute *out_attr;
ee065d83
PB		 12505 /* Some tags have 0 = don't care, 1 = strong requirement,
12506 2 = weak requirement. */
91e22acd 12507 static const int order_021[3] = {0, 2, 1};
ee065d83 12508 int i;
91e22acd 12509 bfd_boolean result = TRUE;
9274e9de 12510 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 12511
3e6b1042
DJ		 12512 /* Skip the linker stubs file. This preserves previous behavior
12513 of accepting unknown attributes in the first input file - but
12514 is that a bug? */
12515 if (ibfd->flags & BFD_LINKER_CREATED)
12516 return TRUE;
12517
9274e9de
TG		 12518 /* Skip any input that hasn't attribute section.
12519 This enables to link object files without attribute section with
12520 any others. */
12521 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
12522 return TRUE;
12523
104d59d1 12524 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 12525 {
12526 /* This is the first object. Copy the attributes. */
104d59d1 12527 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 12528
cd21e546
MGD		 12529 out_attr = elf_known_obj_attributes_proc (obfd);
12530
004ae526
PB		 12531 /* Use the Tag_null value to indicate the attributes have been
12532 initialized. */
cd21e546 12533 out_attr[0].i = 1;
004ae526 12534
cd21e546
MGD		 12535 /* We do not output objects with Tag_MPextension_use_legacy - we move
12536 the attribute's value to Tag_MPextension_use. */
12537 if (out_attr[Tag_MPextension_use_legacy].i != 0)
12538 {
12539 if (out_attr[Tag_MPextension_use].i != 0
12540 && out_attr[Tag_MPextension_use_legacy].i
99059e56 12541 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 12542 {
12543 _bfd_error_handler
12544 (_("Error: %B has both the current and legacy "
12545 "Tag_MPextension_use attributes"), ibfd);
12546 result = FALSE;
12547 }
12548
12549 out_attr[Tag_MPextension_use] =
12550 out_attr[Tag_MPextension_use_legacy];
12551 out_attr[Tag_MPextension_use_legacy].type = 0;
12552 out_attr[Tag_MPextension_use_legacy].i = 0;
12553 }
12554
12555 return result;
ee065d83
PB		 12556 }
12557
104d59d1
JM		 12558 in_attr = elf_known_obj_attributes_proc (ibfd);
12559 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 12560 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
12561 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
12562 {
5c294fee
TG		 12563 /* Ignore mismatches if the object doesn't use floating point or is
12564 floating point ABI independent. */
12565 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
12566 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
12567 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 12568 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 12569 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
12570 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 12571 {
12572 _bfd_error_handler
3895f852 12573 (_("error: %B uses VFP register arguments, %B does not"),
deddc40b
NS		 12574 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
12575 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 12576 result = FALSE;
ee065d83
PB		 12577 }
12578 }
12579
3de4a297 12580 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 12581 {
12582 /* Merge this attribute with existing attributes. */
12583 switch (i)
12584 {
12585 case Tag_CPU_raw_name:
12586 case Tag_CPU_name:
6a631e86 12587 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 12588 break;
12589
12590 case Tag_ABI_optimization_goals:
12591 case Tag_ABI_FP_optimization_goals:
12592 /* Use the first value seen. */
12593 break;
12594
12595 case Tag_CPU_arch:
91e22acd
AS		 12596 {
12597 int secondary_compat = -1, secondary_compat_out = -1;
12598 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 12599 int arch_attr;
12600 static const char *name_table[] =
12601 {
91e22acd
AS		 12602 /* These aren't real CPU names, but we can't guess
12603 that from the architecture version alone. */
12604 "Pre v4",
12605 "ARM v4",
12606 "ARM v4T",
12607 "ARM v5T",
12608 "ARM v5TE",
12609 "ARM v5TEJ",
12610 "ARM v6",
12611 "ARM v6KZ",
12612 "ARM v6T2",
12613 "ARM v6K",
12614 "ARM v7",
12615 "ARM v6-M",
bca38921 12616 "ARM v6S-M",
2fd158eb
TP		 12617 "ARM v8",
12618 "",
12619 "ARM v8-M.baseline",
12620 "ARM v8-M.mainline",
91e22acd
AS		 12621 };
12622
12623 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
12624 secondary_compat = get_secondary_compatible_arch (ibfd);
12625 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 12626 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
12627 &secondary_compat_out,
12628 in_attr[i].i,
12629 secondary_compat);
12630
12631 /* Return with error if failed to merge. */
12632 if (arch_attr == -1)
12633 return FALSE;
12634
12635 out_attr[i].i = arch_attr;
12636
91e22acd
AS		 12637 set_secondary_compatible_arch (obfd, secondary_compat_out);
12638
12639 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
12640 if (out_attr[i].i == saved_out_attr)
12641 ; /* Leave the names alone. */
12642 else if (out_attr[i].i == in_attr[i].i)
12643 {
12644 /* The output architecture has been changed to match the
12645 input architecture. Use the input names. */
12646 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
12647 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
12648 : NULL;
12649 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
12650 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
12651 : NULL;
12652 }
12653 else
12654 {
12655 out_attr[Tag_CPU_name].s = NULL;
12656 out_attr[Tag_CPU_raw_name].s = NULL;
12657 }
12658
12659 /* If we still don't have a value for Tag_CPU_name,
12660 make one up now. Tag_CPU_raw_name remains blank. */
12661 if (out_attr[Tag_CPU_name].s == NULL
12662 && out_attr[i].i < ARRAY_SIZE (name_table))
12663 out_attr[Tag_CPU_name].s =
12664 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
12665 }
12666 break;
12667
ee065d83
PB		 12668 case Tag_ARM_ISA_use:
12669 case Tag_THUMB_ISA_use:
ee065d83 12670 case Tag_WMMX_arch:
91e22acd
AS		 12671 case Tag_Advanced_SIMD_arch:
12672 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 12673 case Tag_ABI_FP_rounding:
ee065d83
PB		 12674 case Tag_ABI_FP_exceptions:
12675 case Tag_ABI_FP_user_exceptions:
12676 case Tag_ABI_FP_number_model:
75375b3e 12677 case Tag_FP_HP_extension:
91e22acd
AS		 12678 case Tag_CPU_unaligned_access:
12679 case Tag_T2EE_use:
91e22acd 12680 case Tag_MPextension_use:
ee065d83
PB		 12681 /* Use the largest value specified. */
12682 if (in_attr[i].i > out_attr[i].i)
12683 out_attr[i].i = in_attr[i].i;
12684 break;
12685
75375b3e 12686 case Tag_ABI_align_preserved:
91e22acd
AS		 12687 case Tag_ABI_PCS_RO_data:
12688 /* Use the smallest value specified. */
12689 if (in_attr[i].i < out_attr[i].i)
12690 out_attr[i].i = in_attr[i].i;
12691 break;
12692
75375b3e 12693 case Tag_ABI_align_needed:
91e22acd 12694 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 12695 && (in_attr[Tag_ABI_align_preserved].i == 0
12696 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 12697 {
91e22acd
AS		 12698 /* This error message should be enabled once all non-conformant
12699 binaries in the toolchain have had the attributes set
12700 properly.
ee065d83 12701 _bfd_error_handler
3895f852 12702 (_("error: %B: 8-byte data alignment conflicts with %B"),
91e22acd
AS		 12703 obfd, ibfd);
12704 result = FALSE; */
ee065d83 12705 }
91e22acd
AS		 12706 /* Fall through. */
12707 case Tag_ABI_FP_denormal:
12708 case Tag_ABI_PCS_GOT_use:
12709 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
12710 value if greater than 2 (for future-proofing). */
12711 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
12712 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
12713 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 12714 out_attr[i].i = in_attr[i].i;
12715 break;
91e22acd 12716
75375b3e
MGD		 12717 case Tag_Virtualization_use:
12718 /* The virtualization tag effectively stores two bits of
12719 information: the intended use of TrustZone (in bit 0), and the
12720 intended use of Virtualization (in bit 1). */
12721 if (out_attr[i].i == 0)
12722 out_attr[i].i = in_attr[i].i;
12723 else if (in_attr[i].i != 0
12724 && in_attr[i].i != out_attr[i].i)
12725 {
12726 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
12727 out_attr[i].i = 3;
12728 else
12729 {
12730 _bfd_error_handler
12731 (_("error: %B: unable to merge virtualization attributes "
12732 "with %B"),
12733 obfd, ibfd);
12734 result = FALSE;
12735 }
12736 }
12737 break;
91e22acd
AS		 12738
12739 case Tag_CPU_arch_profile:
12740 if (out_attr[i].i != in_attr[i].i)
12741 {
12742 /* 0 will merge with anything.
12743 'A' and 'S' merge to 'A'.
12744 'R' and 'S' merge to 'R'.
99059e56 12745 'M' and 'A|R|S' is an error. */
91e22acd
AS		 12746 if (out_attr[i].i == 0
12747 || (out_attr[i].i == 'S'
12748 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
12749 out_attr[i].i = in_attr[i].i;
12750 else if (in_attr[i].i == 0
12751 || (in_attr[i].i == 'S'
12752 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 12753 ; /* Do nothing. */
91e22acd
AS		 12754 else
12755 {
12756 _bfd_error_handler
3895f852 12757 (_("error: %B: Conflicting architecture profiles %c/%c"),
91e22acd
AS		 12758 ibfd,
12759 in_attr[i].i ? in_attr[i].i : '0',
12760 out_attr[i].i ? out_attr[i].i : '0');
12761 result = FALSE;
12762 }
12763 }
12764 break;
15afaa63
TP		 12765
12766 case Tag_DSP_extension:
12767 /* No need to change output value if any of:
12768 - pre (<=) ARMv5T input architecture (do not have DSP)
12769 - M input profile not ARMv7E-M and do not have DSP. */
12770 if (in_attr[Tag_CPU_arch].i <= 3
12771 || (in_attr[Tag_CPU_arch_profile].i == 'M'
12772 && in_attr[Tag_CPU_arch].i != 13
12773 && in_attr[i].i == 0))
12774 ; /* Do nothing. */
12775 /* Output value should be 0 if DSP part of architecture, ie.
12776 - post (>=) ARMv5te architecture output
12777 - A, R or S profile output or ARMv7E-M output architecture. */
12778 else if (out_attr[Tag_CPU_arch].i >= 4
12779 && (out_attr[Tag_CPU_arch_profile].i == 'A'
12780 || out_attr[Tag_CPU_arch_profile].i == 'R'
12781 || out_attr[Tag_CPU_arch_profile].i == 'S'
12782 || out_attr[Tag_CPU_arch].i == 13))
12783 out_attr[i].i = 0;
12784 /* Otherwise, DSP instructions are added and not part of output
12785 architecture. */
12786 else
12787 out_attr[i].i = 1;
12788 break;
12789
75375b3e 12790 case Tag_FP_arch:
62f3b8c8 12791 {
4547cb56
NC		 12792 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
12793 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
12794 when it's 0. It might mean absence of FP hardware if
99654aaf 12795 Tag_FP_arch is zero. */
4547cb56 12796
a715796b 12797#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 12798 static const struct
12799 {
12800 int ver;
12801 int regs;
bca38921 12802 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 12803 {
12804 {0, 0},
12805 {1, 16},
12806 {2, 16},
12807 {3, 32},
12808 {3, 16},
12809 {4, 32},
bca38921 12810 {4, 16},
a715796b
TG		 12811 {8, 32},
12812 {8, 16}
62f3b8c8
PB		 12813 };
12814 int ver;
12815 int regs;
12816 int newval;
12817
4547cb56
NC		 12818 /* If the output has no requirement about FP hardware,
12819 follow the requirement of the input. */
12820 if (out_attr[i].i == 0)
12821 {
12822 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
12823 out_attr[i].i = in_attr[i].i;
12824 out_attr[Tag_ABI_HardFP_use].i
12825 = in_attr[Tag_ABI_HardFP_use].i;
12826 break;
12827 }
12828 /* If the input has no requirement about FP hardware, do
12829 nothing. */
12830 else if (in_attr[i].i == 0)
12831 {
12832 BFD_ASSERT (in_attr[Tag_ABI_HardFP_use].i == 0);
12833 break;
12834 }
12835
12836 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 12837 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 12838
12839 /* If both the input and the output have zero Tag_ABI_HardFP_use,
12840 do nothing. */
12841 if (in_attr[Tag_ABI_HardFP_use].i == 0
12842 && out_attr[Tag_ABI_HardFP_use].i == 0)
12843 ;
12844 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 12845 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 12846 else if (in_attr[Tag_ABI_HardFP_use].i
12847 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 12848 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 12849
12850 /* Now we can handle Tag_FP_arch. */
12851
bca38921
MGD		 12852 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
12853 pick the biggest. */
12854 if (in_attr[i].i >= VFP_VERSION_COUNT
12855 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 12856 {
12857 out_attr[i] = in_attr[i];
12858 break;
12859 }
12860 /* The output uses the superset of input features
12861 (ISA version) and registers. */
12862 ver = vfp_versions[in_attr[i].i].ver;
12863 if (ver < vfp_versions[out_attr[i].i].ver)
12864 ver = vfp_versions[out_attr[i].i].ver;
12865 regs = vfp_versions[in_attr[i].i].regs;
12866 if (regs < vfp_versions[out_attr[i].i].regs)
12867 regs = vfp_versions[out_attr[i].i].regs;
12868 /* This assumes all possible supersets are also a valid
99059e56 12869 options. */
bca38921 12870 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 12871 {
12872 if (regs == vfp_versions[newval].regs
12873 && ver == vfp_versions[newval].ver)
12874 break;
12875 }
12876 out_attr[i].i = newval;
12877 }
b1cc4aeb 12878 break;
ee065d83
PB		 12879 case Tag_PCS_config:
12880 if (out_attr[i].i == 0)
12881 out_attr[i].i = in_attr[i].i;
b6009aca 12882 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 12883 {
12884 /* It's sometimes ok to mix different configs, so this is only
99059e56 12885 a warning. */
ee065d83
PB		 12886 _bfd_error_handler
12887 (_("Warning: %B: Conflicting platform configuration"), ibfd);
12888 }
12889 break;
12890 case Tag_ABI_PCS_R9_use:
004ae526
PB		 12891 if (in_attr[i].i != out_attr[i].i
12892 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 12893 && in_attr[i].i != AEABI_R9_unused)
12894 {
12895 _bfd_error_handler
3895f852 12896 (_("error: %B: Conflicting use of R9"), ibfd);
91e22acd 12897 result = FALSE;
ee065d83
PB		 12898 }
12899 if (out_attr[i].i == AEABI_R9_unused)
12900 out_attr[i].i = in_attr[i].i;
12901 break;
12902 case Tag_ABI_PCS_RW_data:
12903 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
12904 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
12905 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
12906 {
12907 _bfd_error_handler
3895f852 12908 (_("error: %B: SB relative addressing conflicts with use of R9"),
ee065d83 12909 ibfd);
91e22acd 12910 result = FALSE;
ee065d83
PB		 12911 }
12912 /* Use the smallest value specified. */
12913 if (in_attr[i].i < out_attr[i].i)
12914 out_attr[i].i = in_attr[i].i;
12915 break;
ee065d83 12916 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 12917 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
12918 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 12919 {
12920 _bfd_error_handler
a9dc9481
JM		 12921 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
12922 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 12923 }
a9dc9481 12924 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 12925 out_attr[i].i = in_attr[i].i;
12926 break;
ee065d83
PB		 12927 case Tag_ABI_enum_size:
12928 if (in_attr[i].i != AEABI_enum_unused)
12929 {
12930 if (out_attr[i].i == AEABI_enum_unused
12931 || out_attr[i].i == AEABI_enum_forced_wide)
12932 {
12933 /* The existing object is compatible with anything.
12934 Use whatever requirements the new object has. */
12935 out_attr[i].i = in_attr[i].i;
12936 }
12937 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 12938 && out_attr[i].i != in_attr[i].i
0ffa91dd 12939 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 12940 {
91e22acd 12941 static const char *aeabi_enum_names[] =
bf21ed78 12942 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 12943 const char *in_name =
12944 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
12945 ? aeabi_enum_names[in_attr[i].i]
12946 : "<unknown>";
12947 const char *out_name =
12948 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
12949 ? aeabi_enum_names[out_attr[i].i]
12950 : "<unknown>";
ee065d83 12951 _bfd_error_handler
bf21ed78 12952 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 12953 ibfd, in_name, out_name);
ee065d83
PB		 12954 }
12955 }
12956 break;
12957 case Tag_ABI_VFP_args:
12958 /* Aready done. */
12959 break;
12960 case Tag_ABI_WMMX_args:
12961 if (in_attr[i].i != out_attr[i].i)
12962 {
12963 _bfd_error_handler
3895f852 12964 (_("error: %B uses iWMMXt register arguments, %B does not"),
ee065d83 12965 ibfd, obfd);
91e22acd 12966 result = FALSE;
ee065d83
PB		 12967 }
12968 break;
7b86a9fa
AS		 12969 case Tag_compatibility:
12970 /* Merged in target-independent code. */
12971 break;
91e22acd 12972 case Tag_ABI_HardFP_use:
4547cb56 12973 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 12974 break;
12975 case Tag_ABI_FP_16bit_format:
12976 if (in_attr[i].i != 0 && out_attr[i].i != 0)
12977 {
12978 if (in_attr[i].i != out_attr[i].i)
12979 {
12980 _bfd_error_handler
3895f852 12981 (_("error: fp16 format mismatch between %B and %B"),
91e22acd
AS		 12982 ibfd, obfd);
12983 result = FALSE;
12984 }
12985 }
12986 if (in_attr[i].i != 0)
12987 out_attr[i].i = in_attr[i].i;
12988 break;
7b86a9fa 12989
cd21e546 12990 case Tag_DIV_use:
ac56ee8f
MGD		 12991 /* A value of zero on input means that the divide instruction may
12992 be used if available in the base architecture as specified via
12993 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
12994 the user did not want divide instructions. A value of 2
12995 explicitly means that divide instructions were allowed in ARM
12996 and Thumb state. */
12997 if (in_attr[i].i == out_attr[i].i)
12998 /* Do nothing. */ ;
12999 else if (elf32_arm_attributes_forbid_div (in_attr)
13000 && !elf32_arm_attributes_accept_div (out_attr))
13001 out_attr[i].i = 1;
13002 else if (elf32_arm_attributes_forbid_div (out_attr)
13003 && elf32_arm_attributes_accept_div (in_attr))
13004 out_attr[i].i = in_attr[i].i;
13005 else if (in_attr[i].i == 2)
13006 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 13007 break;
13008
13009 case Tag_MPextension_use_legacy:
13010 /* We don't output objects with Tag_MPextension_use_legacy - we
13011 move the value to Tag_MPextension_use. */
13012 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
13013 {
13014 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
13015 {
13016 _bfd_error_handler
13017 (_("%B has has both the current and legacy "
b38cadfb 13018 "Tag_MPextension_use attributes"),
cd21e546
MGD		 13019 ibfd);
13020 result = FALSE;
13021 }
13022 }
13023
13024 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
13025 out_attr[Tag_MPextension_use] = in_attr[i];
13026
13027 break;
13028
91e22acd 13029 case Tag_nodefaults:
2d0bb761
AS		 13030 /* This tag is set if it exists, but the value is unused (and is
13031 typically zero). We don't actually need to do anything here -
13032 the merge happens automatically when the type flags are merged
13033 below. */
91e22acd
AS		 13034 break;
13035 case Tag_also_compatible_with:
13036 /* Already done in Tag_CPU_arch. */
13037 break;
13038 case Tag_conformance:
13039 /* Keep the attribute if it matches. Throw it away otherwise.
13040 No attribute means no claim to conform. */
13041 if (!in_attr[i].s || !out_attr[i].s
13042 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
13043 out_attr[i].s = NULL;
13044 break;
3cfad14c 13045
91e22acd 13046 default:
e8b36cd1
JM		 13047 result
13048 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 13049 }
13050
13051 /* If out_attr was copied from in_attr then it won't have a type yet. */
13052 if (in_attr[i].type && !out_attr[i].type)
13053 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 13054 }
13055
104d59d1 13056 /* Merge Tag_compatibility attributes and any common GNU ones. */
5488d830
MGD		 13057 if (!_bfd_elf_merge_object_attributes (ibfd, obfd))
13058 return FALSE;
ee065d83 13059
104d59d1 13060 /* Check for any attributes not known on ARM. */
e8b36cd1 13061 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 13062
91e22acd 13063 return result;
252b5132
RH		 13064}
13065
3a4a14e9
PB		 13066
13067/* Return TRUE if the two EABI versions are incompatible. */
13068
13069static bfd_boolean
13070elf32_arm_versions_compatible (unsigned iver, unsigned over)
13071{
13072 /* v4 and v5 are the same spec before and after it was released,
13073 so allow mixing them. */
13074 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
13075 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
13076 return TRUE;
13077
13078 return (iver == over);
13079}
13080
252b5132
RH		 13081/* Merge backend specific data from an object file to the output
13082 object file when linking. */
9b485d32 13083
b34976b6 13084static bfd_boolean
21d799b5 13085elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd);
252b5132 13086
9b485d32
NC		 13087/* Display the flags field. */
13088
b34976b6 13089static bfd_boolean
57e8b36a 13090elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 13091{
fc830a83
NC		 13092 FILE * file = (FILE *) ptr;
13093 unsigned long flags;
252b5132
RH		 13094
13095 BFD_ASSERT (abfd != NULL && ptr != NULL);
13096
13097 /* Print normal ELF private data. */
13098 _bfd_elf_print_private_bfd_data (abfd, ptr);
13099
fc830a83 13100 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 13101 /* Ignore init flag - it may not be set, despite the flags field
13102 containing valid data. */
252b5132
RH		 13103
13104 /* xgettext:c-format */
9b485d32 13105 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 13106
fc830a83
NC		 13107 switch (EF_ARM_EABI_VERSION (flags))
13108 {
13109 case EF_ARM_EABI_UNKNOWN:
4cc11e76 13110 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 13111 official ARM ELF extended ABI. Hence they are only decoded if
13112 the EABI version is not set. */
fd2ec330 13113 if (flags & EF_ARM_INTERWORK)
9b485d32 13114 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 13115
fd2ec330 13116 if (flags & EF_ARM_APCS_26)
6c571f00 13117 fprintf (file, " [APCS-26]");
fc830a83 13118 else
6c571f00 13119 fprintf (file, " [APCS-32]");
9a5aca8c 13120
96a846ea
RE		 13121 if (flags & EF_ARM_VFP_FLOAT)
13122 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 13123 else if (flags & EF_ARM_MAVERICK_FLOAT)
13124 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 13125 else
13126 fprintf (file, _(" [FPA float format]"));
13127
fd2ec330 13128 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 13129 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 13130
fd2ec330 13131 if (flags & EF_ARM_PIC)
9b485d32 13132 fprintf (file, _(" [position independent]"));
fc830a83 13133
fd2ec330 13134 if (flags & EF_ARM_NEW_ABI)
9b485d32 13135 fprintf (file, _(" [new ABI]"));
9a5aca8c 13136
fd2ec330 13137 if (flags & EF_ARM_OLD_ABI)
9b485d32 13138 fprintf (file, _(" [old ABI]"));
9a5aca8c 13139
fd2ec330 13140 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 13141 fprintf (file, _(" [software FP]"));
9a5aca8c 13142
96a846ea
RE		 13143 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
13144 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 13145 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
13146 | EF_ARM_MAVERICK_FLOAT);
fc830a83 13147 break;
9a5aca8c 13148
fc830a83 13149 case EF_ARM_EABI_VER1:
9b485d32 13150 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 13151
fc830a83 13152 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 13153 fprintf (file, _(" [sorted symbol table]"));
fc830a83 13154 else
9b485d32 13155 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 13156
fc830a83
NC		 13157 flags &= ~ EF_ARM_SYMSARESORTED;
13158 break;
9a5aca8c 13159
fd2ec330
PB		 13160 case EF_ARM_EABI_VER2:
13161 fprintf (file, _(" [Version2 EABI]"));
13162
13163 if (flags & EF_ARM_SYMSARESORTED)
13164 fprintf (file, _(" [sorted symbol table]"));
13165 else
13166 fprintf (file, _(" [unsorted symbol table]"));
13167
13168 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
13169 fprintf (file, _(" [dynamic symbols use segment index]"));
13170
13171 if (flags & EF_ARM_MAPSYMSFIRST)
13172 fprintf (file, _(" [mapping symbols precede others]"));
13173
99e4ae17 13174 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 13175 | EF_ARM_MAPSYMSFIRST);
13176 break;
13177
d507cf36
PB		 13178 case EF_ARM_EABI_VER3:
13179 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 13180 break;
13181
13182 case EF_ARM_EABI_VER4:
13183 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 13184 goto eabi;
d507cf36 13185
3a4a14e9
PB		 13186 case EF_ARM_EABI_VER5:
13187 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 13188
13189 if (flags & EF_ARM_ABI_FLOAT_SOFT)
13190 fprintf (file, _(" [soft-float ABI]"));
13191
13192 if (flags & EF_ARM_ABI_FLOAT_HARD)
13193 fprintf (file, _(" [hard-float ABI]"));
13194
13195 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
13196
3a4a14e9 13197 eabi:
d507cf36
PB		 13198 if (flags & EF_ARM_BE8)
13199 fprintf (file, _(" [BE8]"));
13200
13201 if (flags & EF_ARM_LE8)
13202 fprintf (file, _(" [LE8]"));
13203
13204 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
13205 break;
13206
fc830a83 13207 default:
9b485d32 13208 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 13209 break;
13210 }
252b5132 13211
fc830a83 13212 flags &= ~ EF_ARM_EABIMASK;
252b5132 13213
fc830a83 13214 if (flags & EF_ARM_RELEXEC)
9b485d32 13215 fprintf (file, _(" [relocatable executable]"));
252b5132 13216
a5721edd 13217 flags &= ~EF_ARM_RELEXEC;
fc830a83
NC		 13218
13219 if (flags)
9b485d32 13220 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 13221
252b5132
RH		 13222 fputc ('\n', file);
13223
b34976b6 13224 return TRUE;
252b5132
RH		 13225}
13226
13227static int
57e8b36a 13228elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 13229{
2f0ca46a
NC		 13230 switch (ELF_ST_TYPE (elf_sym->st_info))
13231 {
13232 case STT_ARM_TFUNC:
13233 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 13234
2f0ca46a
NC		 13235 case STT_ARM_16BIT:
13236 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
13237 This allows us to distinguish between data used by Thumb instructions
13238 and non-data (which is probably code) inside Thumb regions of an
13239 executable. */
1a0eb693 13240 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 13241 return ELF_ST_TYPE (elf_sym->st_info);
13242 break;
9a5aca8c 13243
ce855c42
NC		 13244 default:
13245 break;
2f0ca46a
NC		 13246 }
13247
13248 return type;
252b5132 13249}
f21f3fe0 13250
252b5132 13251static asection *
07adf181
AM		 13252elf32_arm_gc_mark_hook (asection *sec,
13253 struct bfd_link_info *info,
13254 Elf_Internal_Rela *rel,
13255 struct elf_link_hash_entry *h,
13256 Elf_Internal_Sym *sym)
252b5132
RH		 13257{
13258 if (h != NULL)
07adf181 13259 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 13260 {
13261 case R_ARM_GNU_VTINHERIT:
13262 case R_ARM_GNU_VTENTRY:
07adf181
AM		 13263 return NULL;
13264 }
9ad5cbcf 13265
07adf181 13266 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 13267}
13268
780a67af
NC		 13269/* Update the got entry reference counts for the section being removed. */
13270
b34976b6 13271static bfd_boolean
ba93b8ac
DJ		 13272elf32_arm_gc_sweep_hook (bfd * abfd,
13273 struct bfd_link_info * info,
13274 asection * sec,
13275 const Elf_Internal_Rela * relocs)
252b5132 13276{
5e681ec4
PB		 13277 Elf_Internal_Shdr *symtab_hdr;
13278 struct elf_link_hash_entry **sym_hashes;
13279 bfd_signed_vma *local_got_refcounts;
13280 const Elf_Internal_Rela *rel, *relend;
eb043451
PB		 13281 struct elf32_arm_link_hash_table * globals;
13282
0e1862bb 13283 if (bfd_link_relocatable (info))
7dda2462
TG		 13284 return TRUE;
13285
eb043451 13286 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13287 if (globals == NULL)
13288 return FALSE;
5e681ec4
PB		 13289
13290 elf_section_data (sec)->local_dynrel = NULL;
13291
0ffa91dd 13292 symtab_hdr = & elf_symtab_hdr (abfd);
5e681ec4
PB		 13293 sym_hashes = elf_sym_hashes (abfd);
13294 local_got_refcounts = elf_local_got_refcounts (abfd);
13295
906e58ca 13296 check_use_blx (globals);
bd97cb95 13297
5e681ec4
PB		 13298 relend = relocs + sec->reloc_count;
13299 for (rel = relocs; rel < relend; rel++)
eb043451 13300 {
3eb128b2
AM		 13301 unsigned long r_symndx;
13302 struct elf_link_hash_entry *h = NULL;
f6e32f6d 13303 struct elf32_arm_link_hash_entry *eh;
eb043451 13304 int r_type;
34e77a92 13305 bfd_boolean call_reloc_p;
f6e32f6d
RS		 13306 bfd_boolean may_become_dynamic_p;
13307 bfd_boolean may_need_local_target_p;
34e77a92
RS		 13308 union gotplt_union *root_plt;
13309 struct arm_plt_info *arm_plt;
5e681ec4 13310
3eb128b2
AM		 13311 r_symndx = ELF32_R_SYM (rel->r_info);
13312 if (r_symndx >= symtab_hdr->sh_info)
13313 {
13314 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
13315 while (h->root.type == bfd_link_hash_indirect
13316 || h->root.type == bfd_link_hash_warning)
13317 h = (struct elf_link_hash_entry *) h->root.u.i.link;
13318 }
f6e32f6d
RS		 13319 eh = (struct elf32_arm_link_hash_entry *) h;
13320
34e77a92 13321 call_reloc_p = FALSE;
f6e32f6d
RS		 13322 may_become_dynamic_p = FALSE;
13323 may_need_local_target_p = FALSE;
3eb128b2 13324
eb043451 13325 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 13326 r_type = arm_real_reloc_type (globals, r_type);
eb043451
PB		 13327 switch (r_type)
13328 {
13329 case R_ARM_GOT32:
eb043451 13330 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 13331 case R_ARM_TLS_GD32:
13332 case R_ARM_TLS_IE32:
3eb128b2 13333 if (h != NULL)
eb043451 13334 {
eb043451
PB		 13335 if (h->got.refcount > 0)
13336 h->got.refcount -= 1;
13337 }
13338 else if (local_got_refcounts != NULL)
13339 {
13340 if (local_got_refcounts[r_symndx] > 0)
13341 local_got_refcounts[r_symndx] -= 1;
13342 }
13343 break;
13344
ba93b8ac 13345 case R_ARM_TLS_LDM32:
4dfe6ac6 13346 globals->tls_ldm_got.refcount -= 1;
ba93b8ac
DJ		 13347 break;
13348
eb043451
PB		 13349 case R_ARM_PC24:
13350 case R_ARM_PLT32:
5b5bb741
PB		 13351 case R_ARM_CALL:
13352 case R_ARM_JUMP24:
eb043451 13353 case R_ARM_PREL31:
c19d1205 13354 case R_ARM_THM_CALL:
bd97cb95
DJ		 13355 case R_ARM_THM_JUMP24:
13356 case R_ARM_THM_JUMP19:
34e77a92 13357 call_reloc_p = TRUE;
f6e32f6d
RS		 13358 may_need_local_target_p = TRUE;
13359 break;
13360
13361 case R_ARM_ABS12:
13362 if (!globals->vxworks_p)
13363 {
13364 may_need_local_target_p = TRUE;
13365 break;
13366 }
13367 /* Fall through. */
13368 case R_ARM_ABS32:
13369 case R_ARM_ABS32_NOI:
13370 case R_ARM_REL32:
13371 case R_ARM_REL32_NOI:
b6895b4f
PB		 13372 case R_ARM_MOVW_ABS_NC:
13373 case R_ARM_MOVT_ABS:
13374 case R_ARM_MOVW_PREL_NC:
13375 case R_ARM_MOVT_PREL:
13376 case R_ARM_THM_MOVW_ABS_NC:
13377 case R_ARM_THM_MOVT_ABS:
13378 case R_ARM_THM_MOVW_PREL_NC:
13379 case R_ARM_THM_MOVT_PREL:
b7693d02 13380 /* Should the interworking branches be here also? */
0e1862bb 13381 if ((bfd_link_pic (info) || globals->root.is_relocatable_executable)
34e77a92
RS		 13382 && (sec->flags & SEC_ALLOC) != 0)
13383 {
13384 if (h == NULL
469a3493 13385 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 13386 {
13387 call_reloc_p = TRUE;
13388 may_need_local_target_p = TRUE;
13389 }
13390 else
13391 may_become_dynamic_p = TRUE;
13392 }
f6e32f6d
RS		 13393 else
13394 may_need_local_target_p = TRUE;
13395 break;
b7693d02 13396
f6e32f6d
RS		 13397 default:
13398 break;
13399 }
5e681ec4 13400
34e77a92
RS		 13401 if (may_need_local_target_p
13402 && elf32_arm_get_plt_info (abfd, eh, r_symndx, &root_plt, &arm_plt))
f6e32f6d 13403 {
27586251
HPN		 13404 /* If PLT refcount book-keeping is wrong and too low, we'll
13405 see a zero value (going to -1) for the root PLT reference
13406 count. */
13407 if (root_plt->refcount >= 0)
13408 {
13409 BFD_ASSERT (root_plt->refcount != 0);
13410 root_plt->refcount -= 1;
13411 }
13412 else
13413 /* A value of -1 means the symbol has become local, forced
13414 or seeing a hidden definition. Any other negative value
13415 is an error. */
13416 BFD_ASSERT (root_plt->refcount == -1);
34e77a92
RS		 13417
13418 if (!call_reloc_p)
13419 arm_plt->noncall_refcount--;
5e681ec4 13420
f6e32f6d 13421 if (r_type == R_ARM_THM_CALL)
34e77a92 13422 arm_plt->maybe_thumb_refcount--;
bd97cb95 13423
f6e32f6d
RS		 13424 if (r_type == R_ARM_THM_JUMP24
13425 || r_type == R_ARM_THM_JUMP19)
34e77a92 13426 arm_plt->thumb_refcount--;
f6e32f6d 13427 }
5e681ec4 13428
34e77a92 13429 if (may_become_dynamic_p)
f6e32f6d
RS		 13430 {
13431 struct elf_dyn_relocs **pp;
13432 struct elf_dyn_relocs *p;
5e681ec4 13433
34e77a92 13434 if (h != NULL)
9c489990 13435 pp = &(eh->dyn_relocs);
34e77a92
RS		 13436 else
13437 {
13438 Elf_Internal_Sym *isym;
13439
13440 isym = bfd_sym_from_r_symndx (&globals->sym_cache,
13441 abfd, r_symndx);
13442 if (isym == NULL)
13443 return FALSE;
13444 pp = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
13445 if (pp == NULL)
13446 return FALSE;
13447 }
9c489990 13448 for (; (p = *pp) != NULL; pp = &p->next)
f6e32f6d
RS		 13449 if (p->sec == sec)
13450 {
13451 /* Everything must go for SEC. */
13452 *pp = p->next;
13453 break;
13454 }
eb043451
PB		 13455 }
13456 }
5e681ec4 13457
b34976b6 13458 return TRUE;
252b5132
RH		 13459}
13460
780a67af
NC		 13461/* Look through the relocs for a section during the first phase. */
13462
b34976b6 13463static bfd_boolean
57e8b36a
NC		 13464elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
13465 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 13466{
b34976b6
AM		 13467 Elf_Internal_Shdr *symtab_hdr;
13468 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 13469 const Elf_Internal_Rela *rel;
13470 const Elf_Internal_Rela *rel_end;
13471 bfd *dynobj;
5e681ec4 13472 asection *sreloc;
5e681ec4 13473 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 13474 bfd_boolean call_reloc_p;
13475 bfd_boolean may_become_dynamic_p;
13476 bfd_boolean may_need_local_target_p;
ce98a316 13477 unsigned long nsyms;
9a5aca8c 13478
0e1862bb 13479 if (bfd_link_relocatable (info))
b34976b6 13480 return TRUE;
9a5aca8c 13481
0ffa91dd
NC		 13482 BFD_ASSERT (is_arm_elf (abfd));
13483
5e681ec4 13484 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13485 if (htab == NULL)
13486 return FALSE;
13487
5e681ec4 13488 sreloc = NULL;
9a5aca8c 13489
67687978
PB		 13490 /* Create dynamic sections for relocatable executables so that we can
13491 copy relocations. */
13492 if (htab->root.is_relocatable_executable
13493 && ! htab->root.dynamic_sections_created)
13494 {
13495 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
13496 return FALSE;
13497 }
13498
cbc704f3
RS		 13499 if (htab->root.dynobj == NULL)
13500 htab->root.dynobj = abfd;
34e77a92
RS		 13501 if (!create_ifunc_sections (info))
13502 return FALSE;
cbc704f3
RS		 13503
13504 dynobj = htab->root.dynobj;
13505
0ffa91dd 13506 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 13507 sym_hashes = elf_sym_hashes (abfd);
ce98a316 13508 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 13509
252b5132
RH		 13510 rel_end = relocs + sec->reloc_count;
13511 for (rel = relocs; rel < rel_end; rel++)
13512 {
34e77a92 13513 Elf_Internal_Sym *isym;
252b5132 13514 struct elf_link_hash_entry *h;
b7693d02 13515 struct elf32_arm_link_hash_entry *eh;
252b5132 13516 unsigned long r_symndx;
eb043451 13517 int r_type;
9a5aca8c 13518
252b5132 13519 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 13520 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 13521 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 13522
ce98a316
NC		 13523 if (r_symndx >= nsyms
13524 /* PR 9934: It is possible to have relocations that do not
13525 refer to symbols, thus it is also possible to have an
13526 object file containing relocations but no symbol table. */
cf35638d 13527 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac
DJ		 13528 {
13529 (*_bfd_error_handler) (_("%B: bad symbol index: %d"), abfd,
ce98a316 13530 r_symndx);
ba93b8ac
DJ		 13531 return FALSE;
13532 }
13533
34e77a92
RS		 13534 h = NULL;
13535 isym = NULL;
13536 if (nsyms > 0)
973a3492 13537 {
34e77a92
RS		 13538 if (r_symndx < symtab_hdr->sh_info)
13539 {
13540 /* A local symbol. */
13541 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
13542 abfd, r_symndx);
13543 if (isym == NULL)
13544 return FALSE;
13545 }
13546 else
13547 {
13548 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
13549 while (h->root.type == bfd_link_hash_indirect
13550 || h->root.type == bfd_link_hash_warning)
13551 h = (struct elf_link_hash_entry *) h->root.u.i.link;
81fbe831
AM		 13552
13553 /* PR15323, ref flags aren't set for references in the
13554 same object. */
13555 h->root.non_ir_ref = 1;
34e77a92 13556 }
973a3492 13557 }
9a5aca8c 13558
b7693d02
DJ		 13559 eh = (struct elf32_arm_link_hash_entry *) h;
13560
f6e32f6d
RS		 13561 call_reloc_p = FALSE;
13562 may_become_dynamic_p = FALSE;
13563 may_need_local_target_p = FALSE;
13564
0855e32b
NS		 13565 /* Could be done earlier, if h were already available. */
13566 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 13567 switch (r_type)
99059e56 13568 {
5e681ec4 13569 case R_ARM_GOT32:
eb043451 13570 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 13571 case R_ARM_TLS_GD32:
13572 case R_ARM_TLS_IE32:
0855e32b
NS		 13573 case R_ARM_TLS_GOTDESC:
13574 case R_ARM_TLS_DESCSEQ:
13575 case R_ARM_THM_TLS_DESCSEQ:
13576 case R_ARM_TLS_CALL:
13577 case R_ARM_THM_TLS_CALL:
5e681ec4 13578 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 13579 {
13580 int tls_type, old_tls_type;
5e681ec4 13581
ba93b8ac
DJ		 13582 switch (r_type)
13583 {
13584 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 13585
ba93b8ac 13586 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 13587
0855e32b
NS		 13588 case R_ARM_TLS_GOTDESC:
13589 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
13590 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
13591 tls_type = GOT_TLS_GDESC; break;
b38cadfb 13592
ba93b8ac
DJ		 13593 default: tls_type = GOT_NORMAL; break;
13594 }
252b5132 13595
0e1862bb 13596 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 13597 info->flags |= DF_STATIC_TLS;
13598
ba93b8ac
DJ		 13599 if (h != NULL)
13600 {
13601 h->got.refcount++;
13602 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
13603 }
13604 else
13605 {
ba93b8ac 13606 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 13607 if (!elf32_arm_allocate_local_sym_info (abfd))
13608 return FALSE;
13609 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 13610 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
13611 }
13612
0855e32b 13613 /* If a variable is accessed with both tls methods, two
99059e56 13614 slots may be created. */
0855e32b
NS		 13615 if (GOT_TLS_GD_ANY_P (old_tls_type)
13616 && GOT_TLS_GD_ANY_P (tls_type))
13617 tls_type |= old_tls_type;
13618
13619 /* We will already have issued an error message if there
13620 is a TLS/non-TLS mismatch, based on the symbol
13621 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 13622 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
13623 && tls_type != GOT_NORMAL)
13624 tls_type |= old_tls_type;
13625
0855e32b 13626 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 13627 method, we're able to relax. Turn off the GDESC flag,
13628 without messing up with any other kind of tls types
6a631e86 13629 that may be involved. */
0855e32b
NS		 13630 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
13631 tls_type &= ~GOT_TLS_GDESC;
13632
ba93b8ac
DJ		 13633 if (old_tls_type != tls_type)
13634 {
13635 if (h != NULL)
13636 elf32_arm_hash_entry (h)->tls_type = tls_type;
13637 else
13638 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
13639 }
13640 }
8029a119 13641 /* Fall through. */
ba93b8ac
DJ		 13642
13643 case R_ARM_TLS_LDM32:
13644 if (r_type == R_ARM_TLS_LDM32)
13645 htab->tls_ldm_got.refcount++;
8029a119 13646 /* Fall through. */
252b5132 13647
c19d1205 13648 case R_ARM_GOTOFF32:
5e681ec4 13649 case R_ARM_GOTPC:
cbc704f3
RS		 13650 if (htab->root.sgot == NULL
13651 && !create_got_section (htab->root.dynobj, info))
13652 return FALSE;
252b5132
RH		 13653 break;
13654
252b5132 13655 case R_ARM_PC24:
7359ea65 13656 case R_ARM_PLT32:
5b5bb741
PB		 13657 case R_ARM_CALL:
13658 case R_ARM_JUMP24:
eb043451 13659 case R_ARM_PREL31:
c19d1205 13660 case R_ARM_THM_CALL:
bd97cb95
DJ		 13661 case R_ARM_THM_JUMP24:
13662 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 13663 call_reloc_p = TRUE;
13664 may_need_local_target_p = TRUE;
13665 break;
13666
13667 case R_ARM_ABS12:
13668 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
13669 ldr __GOTT_INDEX__ offsets. */
13670 if (!htab->vxworks_p)
13671 {
13672 may_need_local_target_p = TRUE;
13673 break;
13674 }
aebf9be7
NC		 13675 else goto jump_over;
13676
f6e32f6d 13677 /* Fall through. */
39623e12 13678
96c23d59
JM		 13679 case R_ARM_MOVW_ABS_NC:
13680 case R_ARM_MOVT_ABS:
13681 case R_ARM_THM_MOVW_ABS_NC:
13682 case R_ARM_THM_MOVT_ABS:
0e1862bb 13683 if (bfd_link_pic (info))
96c23d59
JM		 13684 {
13685 (*_bfd_error_handler)
13686 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
13687 abfd, elf32_arm_howto_table_1[r_type].name,
13688 (h) ? h->root.root.string : "a local symbol");
13689 bfd_set_error (bfd_error_bad_value);
13690 return FALSE;
13691 }
13692
13693 /* Fall through. */
39623e12
PB		 13694 case R_ARM_ABS32:
13695 case R_ARM_ABS32_NOI:
aebf9be7 13696 jump_over:
0e1862bb 13697 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 13698 {
13699 h->pointer_equality_needed = 1;
13700 }
13701 /* Fall through. */
39623e12
PB		 13702 case R_ARM_REL32:
13703 case R_ARM_REL32_NOI:
b6895b4f
PB		 13704 case R_ARM_MOVW_PREL_NC:
13705 case R_ARM_MOVT_PREL:
b6895b4f
PB		 13706 case R_ARM_THM_MOVW_PREL_NC:
13707 case R_ARM_THM_MOVT_PREL:
39623e12 13708
b7693d02 13709 /* Should the interworking branches be listed here? */
0e1862bb 13710 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 13711 && (sec->flags & SEC_ALLOC) != 0)
13712 {
13713 if (h == NULL
469a3493 13714 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 13715 {
13716 /* In shared libraries and relocatable executables,
13717 we treat local relative references as calls;
13718 see the related SYMBOL_CALLS_LOCAL code in
13719 allocate_dynrelocs. */
13720 call_reloc_p = TRUE;
13721 may_need_local_target_p = TRUE;
13722 }
13723 else
13724 /* We are creating a shared library or relocatable
13725 executable, and this is a reloc against a global symbol,
13726 or a non-PC-relative reloc against a local symbol.
13727 We may need to copy the reloc into the output. */
13728 may_become_dynamic_p = TRUE;
13729 }
f6e32f6d
RS		 13730 else
13731 may_need_local_target_p = TRUE;
252b5132
RH		 13732 break;
13733
99059e56
RM		 13734 /* This relocation describes the C++ object vtable hierarchy.
13735 Reconstruct it for later use during GC. */
13736 case R_ARM_GNU_VTINHERIT:
13737 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
13738 return FALSE;
13739 break;
13740
13741 /* This relocation describes which C++ vtable entries are actually
13742 used. Record for later use during GC. */
13743 case R_ARM_GNU_VTENTRY:
13744 BFD_ASSERT (h != NULL);
13745 if (h != NULL
13746 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
13747 return FALSE;
13748 break;
13749 }
f6e32f6d
RS		 13750
13751 if (h != NULL)
13752 {
13753 if (call_reloc_p)
13754 /* We may need a .plt entry if the function this reloc
13755 refers to is in a different object, regardless of the
13756 symbol's type. We can't tell for sure yet, because
13757 something later might force the symbol local. */
13758 h->needs_plt = 1;
13759 else if (may_need_local_target_p)
13760 /* If this reloc is in a read-only section, we might
13761 need a copy reloc. We can't check reliably at this
13762 stage whether the section is read-only, as input
13763 sections have not yet been mapped to output sections.
13764 Tentatively set the flag for now, and correct in
13765 adjust_dynamic_symbol. */
13766 h->non_got_ref = 1;
13767 }
13768
34e77a92
RS		 13769 if (may_need_local_target_p
13770 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 13771 {
34e77a92
RS		 13772 union gotplt_union *root_plt;
13773 struct arm_plt_info *arm_plt;
13774 struct arm_local_iplt_info *local_iplt;
13775
13776 if (h != NULL)
13777 {
13778 root_plt = &h->plt;
13779 arm_plt = &eh->plt;
13780 }
13781 else
13782 {
13783 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
13784 if (local_iplt == NULL)
13785 return FALSE;
13786 root_plt = &local_iplt->root;
13787 arm_plt = &local_iplt->arm;
13788 }
13789
f6e32f6d
RS		 13790 /* If the symbol is a function that doesn't bind locally,
13791 this relocation will need a PLT entry. */
a8c887dd
NC		 13792 if (root_plt->refcount != -1)
13793 root_plt->refcount += 1;
34e77a92
RS		 13794
13795 if (!call_reloc_p)
13796 arm_plt->noncall_refcount++;
f6e32f6d
RS		 13797
13798 /* It's too early to use htab->use_blx here, so we have to
13799 record possible blx references separately from
13800 relocs that definitely need a thumb stub. */
13801
13802 if (r_type == R_ARM_THM_CALL)
34e77a92 13803 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 13804
13805 if (r_type == R_ARM_THM_JUMP24
13806 || r_type == R_ARM_THM_JUMP19)
34e77a92 13807 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 13808 }
13809
13810 if (may_become_dynamic_p)
13811 {
13812 struct elf_dyn_relocs *p, **head;
13813
13814 /* Create a reloc section in dynobj. */
13815 if (sreloc == NULL)
13816 {
13817 sreloc = _bfd_elf_make_dynamic_reloc_section
13818 (sec, dynobj, 2, abfd, ! htab->use_rel);
13819
13820 if (sreloc == NULL)
13821 return FALSE;
13822
13823 /* BPABI objects never have dynamic relocations mapped. */
13824 if (htab->symbian_p)
13825 {
13826 flagword flags;
13827
13828 flags = bfd_get_section_flags (dynobj, sreloc);
13829 flags &= ~(SEC_LOAD | SEC_ALLOC);
13830 bfd_set_section_flags (dynobj, sreloc, flags);
13831 }
13832 }
13833
13834 /* If this is a global symbol, count the number of
13835 relocations we need for this symbol. */
13836 if (h != NULL)
13837 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
13838 else
13839 {
34e77a92
RS		 13840 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
13841 if (head == NULL)
f6e32f6d 13842 return FALSE;
f6e32f6d
RS		 13843 }
13844
13845 p = *head;
13846 if (p == NULL || p->sec != sec)
13847 {
13848 bfd_size_type amt = sizeof *p;
13849
13850 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
13851 if (p == NULL)
13852 return FALSE;
13853 p->next = *head;
13854 *head = p;
13855 p->sec = sec;
13856 p->count = 0;
13857 p->pc_count = 0;
13858 }
13859
469a3493 13860 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 13861 p->pc_count += 1;
13862 p->count += 1;
13863 }
252b5132 13864 }
f21f3fe0 13865
b34976b6 13866 return TRUE;
252b5132
RH		 13867}
13868
6a5bb875
PB		 13869/* Unwinding tables are not referenced directly. This pass marks them as
13870 required if the corresponding code section is marked. */
13871
13872static bfd_boolean
906e58ca
NC		 13873elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
13874 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 13875{
13876 bfd *sub;
13877 Elf_Internal_Shdr **elf_shdrp;
13878 bfd_boolean again;
13879
7f6ab9f8
AM		 13880 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
13881
6a5bb875
PB		 13882 /* Marking EH data may cause additional code sections to be marked,
13883 requiring multiple passes. */
13884 again = TRUE;
13885 while (again)
13886 {
13887 again = FALSE;
c72f2fb2 13888 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 13889 {
13890 asection *o;
13891
0ffa91dd 13892 if (! is_arm_elf (sub))
6a5bb875
PB		 13893 continue;
13894
13895 elf_shdrp = elf_elfsections (sub);
13896 for (o = sub->sections; o != NULL; o = o->next)
13897 {
13898 Elf_Internal_Shdr *hdr;
0ffa91dd 13899
6a5bb875 13900 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 13901 if (hdr->sh_type == SHT_ARM_EXIDX
13902 && hdr->sh_link
13903 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 13904 && !o->gc_mark
13905 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
13906 {
13907 again = TRUE;
13908 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
13909 return FALSE;
13910 }
13911 }
13912 }
13913 }
13914
13915 return TRUE;
13916}
13917
3c9458e9
NC		 13918/* Treat mapping symbols as special target symbols. */
13919
13920static bfd_boolean
13921elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
13922{
b0796911
PB		 13923 return bfd_is_arm_special_symbol_name (sym->name,
13924 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 13925}
13926
0367ecfb
NC		 13927/* This is a copy of elf_find_function() from elf.c except that
13928 ARM mapping symbols are ignored when looking for function names
13929 and STT_ARM_TFUNC is considered to a function type. */
252b5132 13930
0367ecfb
NC		 13931static bfd_boolean
13932arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 13933 asymbol ** symbols,
fb167eb2 13934 asection * section,
0367ecfb
NC		 13935 bfd_vma offset,
13936 const char ** filename_ptr,
13937 const char ** functionname_ptr)
13938{
13939 const char * filename = NULL;
13940 asymbol * func = NULL;
13941 bfd_vma low_func = 0;
13942 asymbol ** p;
252b5132
RH		 13943
13944 for (p = symbols; *p != NULL; p++)
13945 {
13946 elf_symbol_type *q;
13947
13948 q = (elf_symbol_type *) *p;
13949
252b5132
RH		 13950 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
13951 {
13952 default:
13953 break;
13954 case STT_FILE:
13955 filename = bfd_asymbol_name (&q->symbol);
13956 break;
252b5132
RH		 13957 case STT_FUNC:
13958 case STT_ARM_TFUNC:
9d2da7ca 13959 case STT_NOTYPE:
b0796911 13960 /* Skip mapping symbols. */
0367ecfb 13961 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 13962 && bfd_is_arm_special_symbol_name (q->symbol.name,
13963 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 13964 continue;
13965 /* Fall through. */
6b40fcba 13966 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 13967 && q->symbol.value >= low_func
13968 && q->symbol.value <= offset)
13969 {
13970 func = (asymbol *) q;
13971 low_func = q->symbol.value;
13972 }
13973 break;
13974 }
13975 }
13976
13977 if (func == NULL)
b34976b6 13978 return FALSE;
252b5132 13979
0367ecfb
NC		 13980 if (filename_ptr)
13981 *filename_ptr = filename;
13982 if (functionname_ptr)
13983 *functionname_ptr = bfd_asymbol_name (func);
13984
13985 return TRUE;
906e58ca 13986}
0367ecfb
NC		 13987
13988
13989/* Find the nearest line to a particular section and offset, for error
13990 reporting. This code is a duplicate of the code in elf.c, except
13991 that it uses arm_elf_find_function. */
13992
13993static bfd_boolean
13994elf32_arm_find_nearest_line (bfd * abfd,
0367ecfb 13995 asymbol ** symbols,
fb167eb2 13996 asection * section,
0367ecfb
NC		 13997 bfd_vma offset,
13998 const char ** filename_ptr,
13999 const char ** functionname_ptr,
fb167eb2
AM		 14000 unsigned int * line_ptr,
14001 unsigned int * discriminator_ptr)
0367ecfb
NC		 14002{
14003 bfd_boolean found = FALSE;
14004
fb167eb2 14005 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 14006 filename_ptr, functionname_ptr,
fb167eb2
AM		 14007 line_ptr, discriminator_ptr,
14008 dwarf_debug_sections, 0,
0367ecfb
NC		 14009 & elf_tdata (abfd)->dwarf2_find_line_info))
14010 {
14011 if (!*functionname_ptr)
fb167eb2 14012 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 14013 *filename_ptr ? NULL : filename_ptr,
14014 functionname_ptr);
f21f3fe0 14015
0367ecfb
NC		 14016 return TRUE;
14017 }
14018
fb167eb2
AM		 14019 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
14020 uses DWARF1. */
14021
0367ecfb
NC		 14022 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
14023 & found, filename_ptr,
14024 functionname_ptr, line_ptr,
14025 & elf_tdata (abfd)->line_info))
14026 return FALSE;
14027
14028 if (found && (*functionname_ptr || *line_ptr))
14029 return TRUE;
14030
14031 if (symbols == NULL)
14032 return FALSE;
14033
fb167eb2 14034 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 14035 filename_ptr, functionname_ptr))
14036 return FALSE;
14037
14038 *line_ptr = 0;
b34976b6 14039 return TRUE;
252b5132
RH		 14040}
14041
4ab527b0
FF		 14042static bfd_boolean
14043elf32_arm_find_inliner_info (bfd * abfd,
14044 const char ** filename_ptr,
14045 const char ** functionname_ptr,
14046 unsigned int * line_ptr)
14047{
14048 bfd_boolean found;
14049 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
14050 functionname_ptr, line_ptr,
14051 & elf_tdata (abfd)->dwarf2_find_line_info);
14052 return found;
14053}
14054
252b5132
RH		 14055/* Adjust a symbol defined by a dynamic object and referenced by a
14056 regular object. The current definition is in some section of the
14057 dynamic object, but we're not including those sections. We have to
14058 change the definition to something the rest of the link can
14059 understand. */
14060
b34976b6 14061static bfd_boolean
57e8b36a
NC		 14062elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
14063 struct elf_link_hash_entry * h)
252b5132
RH		 14064{
14065 bfd * dynobj;
14066 asection * s;
b7693d02 14067 struct elf32_arm_link_hash_entry * eh;
67687978 14068 struct elf32_arm_link_hash_table *globals;
252b5132 14069
67687978 14070 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14071 if (globals == NULL)
14072 return FALSE;
14073
252b5132
RH		 14074 dynobj = elf_hash_table (info)->dynobj;
14075
14076 /* Make sure we know what is going on here. */
14077 BFD_ASSERT (dynobj != NULL
f5385ebf 14078 && (h->needs_plt
34e77a92 14079 || h->type == STT_GNU_IFUNC
f6e332e6 14080 || h->u.weakdef != NULL
f5385ebf
AM		 14081 || (h->def_dynamic
14082 && h->ref_regular
14083 && !h->def_regular)));
252b5132 14084
b7693d02
DJ		 14085 eh = (struct elf32_arm_link_hash_entry *) h;
14086
252b5132
RH		 14087 /* If this is a function, put it in the procedure linkage table. We
14088 will fill in the contents of the procedure linkage table later,
14089 when we know the address of the .got section. */
34e77a92 14090 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 14091 {
34e77a92
RS		 14092 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
14093 symbol binds locally. */
5e681ec4 14094 if (h->plt.refcount <= 0
34e77a92
RS		 14095 || (h->type != STT_GNU_IFUNC
14096 && (SYMBOL_CALLS_LOCAL (info, h)
14097 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
14098 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 14099 {
14100 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 14101 file, but the symbol was never referred to by a dynamic
14102 object, or if all references were garbage collected. In
14103 such a case, we don't actually need to build a procedure
14104 linkage table, and we can just do a PC24 reloc instead. */
14105 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 14106 eh->plt.thumb_refcount = 0;
14107 eh->plt.maybe_thumb_refcount = 0;
14108 eh->plt.noncall_refcount = 0;
f5385ebf 14109 h->needs_plt = 0;
252b5132
RH		 14110 }
14111
b34976b6 14112 return TRUE;
252b5132 14113 }
5e681ec4 14114 else
b7693d02
DJ		 14115 {
14116 /* It's possible that we incorrectly decided a .plt reloc was
14117 needed for an R_ARM_PC24 or similar reloc to a non-function sym
14118 in check_relocs. We can't decide accurately between function
14119 and non-function syms in check-relocs; Objects loaded later in
14120 the link may change h->type. So fix it now. */
14121 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 14122 eh->plt.thumb_refcount = 0;
14123 eh->plt.maybe_thumb_refcount = 0;
14124 eh->plt.noncall_refcount = 0;
b7693d02 14125 }
252b5132
RH		 14126
14127 /* If this is a weak symbol, and there is a real definition, the
14128 processor independent code will have arranged for us to see the
14129 real definition first, and we can just use the same value. */
f6e332e6 14130 if (h->u.weakdef != NULL)
252b5132 14131 {
f6e332e6
AM		 14132 BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined
14133 || h->u.weakdef->root.type == bfd_link_hash_defweak);
14134 h->root.u.def.section = h->u.weakdef->root.u.def.section;
14135 h->root.u.def.value = h->u.weakdef->root.u.def.value;
b34976b6 14136 return TRUE;
252b5132
RH		 14137 }
14138
ba93b8ac
DJ		 14139 /* If there are no non-GOT references, we do not need a copy
14140 relocation. */
14141 if (!h->non_got_ref)
14142 return TRUE;
14143
252b5132
RH		 14144 /* This is a reference to a symbol defined by a dynamic object which
14145 is not a function. */
14146
14147 /* If we are creating a shared library, we must presume that the
14148 only references to the symbol are via the global offset table.
14149 For such cases we need not do anything here; the relocations will
67687978
PB		 14150 be handled correctly by relocate_section. Relocatable executables
14151 can reference data in shared objects directly, so we don't need to
14152 do anything here. */
0e1862bb 14153 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 14154 return TRUE;
252b5132
RH		 14155
14156 /* We must allocate the symbol in our .dynbss section, which will
14157 become part of the .bss section of the executable. There will be
14158 an entry for this symbol in the .dynsym section. The dynamic
14159 object will contain position independent code, so all references
14160 from the dynamic object to this symbol will go through the global
14161 offset table. The dynamic linker will use the .dynsym entry to
14162 determine the address it must put in the global offset table, so
14163 both the dynamic object and the regular object will refer to the
14164 same memory location for the variable. */
3d4d4302 14165 s = bfd_get_linker_section (dynobj, ".dynbss");
252b5132
RH		 14166 BFD_ASSERT (s != NULL);
14167
5522f910
NC		 14168 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
14169 linker to copy the initial value out of the dynamic object and into
14170 the runtime process image. We need to remember the offset into the
00a97672 14171 .rel(a).bss section we are going to use. */
5522f910
NC		 14172 if (info->nocopyreloc == 0
14173 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 14174 && h->size != 0)
252b5132
RH		 14175 {
14176 asection *srel;
14177
3d4d4302 14178 srel = bfd_get_linker_section (dynobj, RELOC_SECTION (globals, ".bss"));
47beaa6a 14179 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 14180 h->needs_copy = 1;
252b5132
RH		 14181 }
14182
6cabe1ea 14183 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 14184}
14185
5e681ec4
PB		 14186/* Allocate space in .plt, .got and associated reloc sections for
14187 dynamic relocs. */
14188
14189static bfd_boolean
47beaa6a 14190allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 14191{
14192 struct bfd_link_info *info;
14193 struct elf32_arm_link_hash_table *htab;
14194 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 14195 struct elf_dyn_relocs *p;
5e681ec4
PB		 14196
14197 if (h->root.type == bfd_link_hash_indirect)
14198 return TRUE;
14199
e6a6bb22
AM		 14200 eh = (struct elf32_arm_link_hash_entry *) h;
14201
5e681ec4
PB		 14202 info = (struct bfd_link_info *) inf;
14203 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14204 if (htab == NULL)
14205 return FALSE;
5e681ec4 14206
34e77a92 14207 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 14208 && h->plt.refcount > 0)
14209 {
14210 /* Make sure this symbol is output as a dynamic symbol.
14211 Undefined weak syms won't yet be marked as dynamic. */
14212 if (h->dynindx == -1
f5385ebf 14213 && !h->forced_local)
5e681ec4 14214 {
c152c796 14215 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14216 return FALSE;
14217 }
14218
34e77a92
RS		 14219 /* If the call in the PLT entry binds locally, the associated
14220 GOT entry should use an R_ARM_IRELATIVE relocation instead of
14221 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
14222 than the .plt section. */
14223 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
14224 {
14225 eh->is_iplt = 1;
14226 if (eh->plt.noncall_refcount == 0
14227 && SYMBOL_REFERENCES_LOCAL (info, h))
14228 /* All non-call references can be resolved directly.
14229 This means that they can (and in some cases, must)
14230 resolve directly to the run-time target, rather than
14231 to the PLT. That in turns means that any .got entry
14232 would be equal to the .igot.plt entry, so there's
14233 no point having both. */
14234 h->got.refcount = 0;
14235 }
14236
0e1862bb 14237 if (bfd_link_pic (info)
34e77a92 14238 || eh->is_iplt
7359ea65 14239 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 14240 {
34e77a92 14241 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 14242
5e681ec4
PB		 14243 /* If this symbol is not defined in a regular file, and we are
14244 not generating a shared library, then set the symbol to this
14245 location in the .plt. This is required to make function
14246 pointers compare as equal between the normal executable and
14247 the shared library. */
0e1862bb 14248 if (! bfd_link_pic (info)
f5385ebf 14249 && !h->def_regular)
5e681ec4 14250 {
34e77a92 14251 h->root.u.def.section = htab->root.splt;
5e681ec4 14252 h->root.u.def.value = h->plt.offset;
5e681ec4 14253
67d74e43
DJ		 14254 /* Make sure the function is not marked as Thumb, in case
14255 it is the target of an ABS32 relocation, which will
14256 point to the PLT entry. */
35fc36a8 14257 h->target_internal = ST_BRANCH_TO_ARM;
67d74e43 14258 }
022f8312 14259
00a97672
RS		 14260 /* VxWorks executables have a second set of relocations for
14261 each PLT entry. They go in a separate relocation section,
14262 which is processed by the kernel loader. */
0e1862bb 14263 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 14264 {
14265 /* There is a relocation for the initial PLT entry:
14266 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
14267 if (h->plt.offset == htab->plt_header_size)
47beaa6a 14268 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 14269
14270 /* There are two extra relocations for each subsequent
14271 PLT entry: an R_ARM_32 relocation for the GOT entry,
14272 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 14273 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 14274 }
5e681ec4
PB		 14275 }
14276 else
14277 {
14278 h->plt.offset = (bfd_vma) -1;
f5385ebf 14279 h->needs_plt = 0;
5e681ec4
PB		 14280 }
14281 }
14282 else
14283 {
14284 h->plt.offset = (bfd_vma) -1;
f5385ebf 14285 h->needs_plt = 0;
5e681ec4
PB		 14286 }
14287
0855e32b
NS		 14288 eh = (struct elf32_arm_link_hash_entry *) h;
14289 eh->tlsdesc_got = (bfd_vma) -1;
14290
5e681ec4
PB		 14291 if (h->got.refcount > 0)
14292 {
14293 asection *s;
14294 bfd_boolean dyn;
ba93b8ac
DJ		 14295 int tls_type = elf32_arm_hash_entry (h)->tls_type;
14296 int indx;
5e681ec4
PB		 14297
14298 /* Make sure this symbol is output as a dynamic symbol.
14299 Undefined weak syms won't yet be marked as dynamic. */
14300 if (h->dynindx == -1
f5385ebf 14301 && !h->forced_local)
5e681ec4 14302 {
c152c796 14303 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14304 return FALSE;
14305 }
14306
e5a52504
MM		 14307 if (!htab->symbian_p)
14308 {
362d30a1 14309 s = htab->root.sgot;
e5a52504 14310 h->got.offset = s->size;
ba93b8ac
DJ		 14311
14312 if (tls_type == GOT_UNKNOWN)
14313 abort ();
14314
14315 if (tls_type == GOT_NORMAL)
14316 /* Non-TLS symbols need one GOT slot. */
14317 s->size += 4;
14318 else
14319 {
99059e56
RM		 14320 if (tls_type & GOT_TLS_GDESC)
14321 {
0855e32b 14322 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 14323 eh->tlsdesc_got
0855e32b
NS		 14324 = (htab->root.sgotplt->size
14325 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 14326 htab->root.sgotplt->size += 8;
14327 h->got.offset = (bfd_vma) -2;
34e77a92 14328 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 14329 reloc in the middle of .got.plt. */
99059e56
RM		 14330 htab->num_tls_desc++;
14331 }
0855e32b 14332
ba93b8ac 14333 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 14334 {
14335 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
14336 the symbol is both GD and GDESC, got.offset may
14337 have been overwritten. */
14338 h->got.offset = s->size;
14339 s->size += 8;
14340 }
14341
ba93b8ac
DJ		 14342 if (tls_type & GOT_TLS_IE)
14343 /* R_ARM_TLS_IE32 needs one GOT slot. */
14344 s->size += 4;
14345 }
14346
e5a52504 14347 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 14348
14349 indx = 0;
0e1862bb
L		 14350 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
14351 bfd_link_pic (info),
14352 h)
14353 && (!bfd_link_pic (info)
ba93b8ac
DJ		 14354 || !SYMBOL_REFERENCES_LOCAL (info, h)))
14355 indx = h->dynindx;
14356
14357 if (tls_type != GOT_NORMAL
0e1862bb 14358 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 14359 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
14360 || h->root.type != bfd_link_hash_undefweak))
14361 {
14362 if (tls_type & GOT_TLS_IE)
47beaa6a 14363 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 14364
14365 if (tls_type & GOT_TLS_GD)
47beaa6a 14366 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 14367
b38cadfb 14368 if (tls_type & GOT_TLS_GDESC)
0855e32b 14369 {
47beaa6a 14370 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 14371 /* GDESC needs a trampoline to jump to. */
14372 htab->tls_trampoline = -1;
14373 }
14374
14375 /* Only GD needs it. GDESC just emits one relocation per
14376 2 entries. */
b38cadfb 14377 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 14378 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 14379 }
6f820c85 14380 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 14381 {
14382 if (htab->root.dynamic_sections_created)
14383 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
14384 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
14385 }
34e77a92
RS		 14386 else if (h->type == STT_GNU_IFUNC
14387 && eh->plt.noncall_refcount == 0)
14388 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
14389 they all resolve dynamically instead. Reserve room for the
14390 GOT entry's R_ARM_IRELATIVE relocation. */
14391 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 14392 else if (bfd_link_pic (info)
14393 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
14394 || h->root.type != bfd_link_hash_undefweak))
b436d854 14395 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 14396 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 14397 }
5e681ec4
PB		 14398 }
14399 else
14400 h->got.offset = (bfd_vma) -1;
14401
a4fd1a8e
PB		 14402 /* Allocate stubs for exported Thumb functions on v4t. */
14403 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 14404 && h->def_regular
35fc36a8 14405 && h->target_internal == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 14406 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
14407 {
14408 struct elf_link_hash_entry * th;
14409 struct bfd_link_hash_entry * bh;
14410 struct elf_link_hash_entry * myh;
14411 char name[1024];
14412 asection *s;
14413 bh = NULL;
14414 /* Create a new symbol to regist the real location of the function. */
14415 s = h->root.u.def.section;
906e58ca 14416 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 14417 _bfd_generic_link_add_one_symbol (info, s->owner,
14418 name, BSF_GLOBAL, s,
14419 h->root.u.def.value,
14420 NULL, TRUE, FALSE, &bh);
14421
14422 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 14423 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 14424 myh->forced_local = 1;
35fc36a8 14425 myh->target_internal = ST_BRANCH_TO_THUMB;
a4fd1a8e
PB		 14426 eh->export_glue = myh;
14427 th = record_arm_to_thumb_glue (info, h);
14428 /* Point the symbol at the stub. */
14429 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
35fc36a8 14430 h->target_internal = ST_BRANCH_TO_ARM;
a4fd1a8e
PB		 14431 h->root.u.def.section = th->root.u.def.section;
14432 h->root.u.def.value = th->root.u.def.value & ~1;
14433 }
14434
0bdcacaf 14435 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 14436 return TRUE;
14437
14438 /* In the shared -Bsymbolic case, discard space allocated for
14439 dynamic pc-relative relocs against symbols which turn out to be
14440 defined in regular objects. For the normal shared case, discard
14441 space for pc-relative relocs that have become local due to symbol
14442 visibility changes. */
14443
0e1862bb 14444 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 14445 {
469a3493
RM		 14446 /* Relocs that use pc_count are PC-relative forms, which will appear
14447 on something like ".long foo - ." or "movw REG, foo - .". We want
14448 calls to protected symbols to resolve directly to the function
14449 rather than going via the plt. If people want function pointer
14450 comparisons to work as expected then they should avoid writing
14451 assembly like ".long foo - .". */
ba93b8ac
DJ		 14452 if (SYMBOL_CALLS_LOCAL (info, h))
14453 {
0bdcacaf 14454 struct elf_dyn_relocs **pp;
ba93b8ac 14455
0bdcacaf 14456 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 14457 {
14458 p->count -= p->pc_count;
14459 p->pc_count = 0;
14460 if (p->count == 0)
14461 *pp = p->next;
14462 else
14463 pp = &p->next;
14464 }
14465 }
14466
4dfe6ac6 14467 if (htab->vxworks_p)
3348747a 14468 {
0bdcacaf 14469 struct elf_dyn_relocs **pp;
3348747a 14470
0bdcacaf 14471 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 14472 {
0bdcacaf 14473 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 14474 *pp = p->next;
14475 else
14476 pp = &p->next;
14477 }
14478 }
14479
ba93b8ac 14480 /* Also discard relocs on undefined weak syms with non-default
99059e56 14481 visibility. */
0bdcacaf 14482 if (eh->dyn_relocs != NULL
5e681ec4 14483 && h->root.type == bfd_link_hash_undefweak)
22d606e9
AM		 14484 {
14485 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT)
0bdcacaf 14486 eh->dyn_relocs = NULL;
22d606e9
AM		 14487
14488 /* Make sure undefined weak symbols are output as a dynamic
14489 symbol in PIEs. */
14490 else if (h->dynindx == -1
14491 && !h->forced_local)
14492 {
14493 if (! bfd_elf_link_record_dynamic_symbol (info, h))
14494 return FALSE;
14495 }
14496 }
14497
67687978
PB		 14498 else if (htab->root.is_relocatable_executable && h->dynindx == -1
14499 && h->root.type == bfd_link_hash_new)
14500 {
14501 /* Output absolute symbols so that we can create relocations
14502 against them. For normal symbols we output a relocation
14503 against the section that contains them. */
14504 if (! bfd_elf_link_record_dynamic_symbol (info, h))
14505 return FALSE;
14506 }
14507
5e681ec4
PB		 14508 }
14509 else
14510 {
14511 /* For the non-shared case, discard space for relocs against
14512 symbols which turn out to need copy relocs or are not
14513 dynamic. */
14514
f5385ebf
AM		 14515 if (!h->non_got_ref
14516 && ((h->def_dynamic
14517 && !h->def_regular)
5e681ec4
PB		 14518 || (htab->root.dynamic_sections_created
14519 && (h->root.type == bfd_link_hash_undefweak
14520 || h->root.type == bfd_link_hash_undefined))))
14521 {
14522 /* Make sure this symbol is output as a dynamic symbol.
14523 Undefined weak syms won't yet be marked as dynamic. */
14524 if (h->dynindx == -1
f5385ebf 14525 && !h->forced_local)
5e681ec4 14526 {
c152c796 14527 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14528 return FALSE;
14529 }
14530
14531 /* If that succeeded, we know we'll be keeping all the
14532 relocs. */
14533 if (h->dynindx != -1)
14534 goto keep;
14535 }
14536
0bdcacaf 14537 eh->dyn_relocs = NULL;
5e681ec4
PB		 14538
14539 keep: ;
14540 }
14541
14542 /* Finally, allocate space. */
0bdcacaf 14543 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 14544 {
0bdcacaf 14545 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 14546 if (h->type == STT_GNU_IFUNC
14547 && eh->plt.noncall_refcount == 0
14548 && SYMBOL_REFERENCES_LOCAL (info, h))
14549 elf32_arm_allocate_irelocs (info, sreloc, p->count);
14550 else
14551 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 14552 }
14553
14554 return TRUE;
14555}
14556
08d1f311
DJ		 14557/* Find any dynamic relocs that apply to read-only sections. */
14558
14559static bfd_boolean
8029a119 14560elf32_arm_readonly_dynrelocs (struct elf_link_hash_entry * h, void * inf)
08d1f311 14561{
8029a119 14562 struct elf32_arm_link_hash_entry * eh;
0bdcacaf 14563 struct elf_dyn_relocs * p;
08d1f311 14564
08d1f311 14565 eh = (struct elf32_arm_link_hash_entry *) h;
0bdcacaf 14566 for (p = eh->dyn_relocs; p != NULL; p = p->next)
08d1f311 14567 {
0bdcacaf 14568 asection *s = p->sec;
08d1f311
DJ		 14569
14570 if (s != NULL && (s->flags & SEC_READONLY) != 0)
14571 {
14572 struct bfd_link_info *info = (struct bfd_link_info *) inf;
14573
14574 info->flags |= DF_TEXTREL;
14575
14576 /* Not an error, just cut short the traversal. */
14577 return FALSE;
14578 }
14579 }
14580 return TRUE;
14581}
14582
d504ffc8
DJ		 14583void
14584bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
14585 int byteswap_code)
14586{
14587 struct elf32_arm_link_hash_table *globals;
14588
14589 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14590 if (globals == NULL)
14591 return;
14592
d504ffc8
DJ		 14593 globals->byteswap_code = byteswap_code;
14594}
14595
252b5132
RH		 14596/* Set the sizes of the dynamic sections. */
14597
b34976b6 14598static bfd_boolean
57e8b36a
NC		 14599elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
14600 struct bfd_link_info * info)
252b5132
RH		 14601{
14602 bfd * dynobj;
14603 asection * s;
b34976b6
AM		 14604 bfd_boolean plt;
14605 bfd_boolean relocs;
5e681ec4
PB		 14606 bfd *ibfd;
14607 struct elf32_arm_link_hash_table *htab;
252b5132 14608
5e681ec4 14609 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14610 if (htab == NULL)
14611 return FALSE;
14612
252b5132
RH		 14613 dynobj = elf_hash_table (info)->dynobj;
14614 BFD_ASSERT (dynobj != NULL);
39b41c9c 14615 check_use_blx (htab);
252b5132
RH		 14616
14617 if (elf_hash_table (info)->dynamic_sections_created)
14618 {
14619 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 14620 if (bfd_link_executable (info) && !info->nointerp)
252b5132 14621 {
3d4d4302 14622 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 14623 BFD_ASSERT (s != NULL);
eea6121a 14624 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 14625 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
14626 }
14627 }
5e681ec4
PB		 14628
14629 /* Set up .got offsets for local syms, and space for local dynamic
14630 relocs. */
c72f2fb2 14631 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 14632 {
5e681ec4
PB		 14633 bfd_signed_vma *local_got;
14634 bfd_signed_vma *end_local_got;
34e77a92 14635 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 14636 char *local_tls_type;
0855e32b 14637 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 14638 bfd_size_type locsymcount;
14639 Elf_Internal_Shdr *symtab_hdr;
14640 asection *srel;
4dfe6ac6 14641 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 14642 unsigned int symndx;
5e681ec4 14643
0ffa91dd 14644 if (! is_arm_elf (ibfd))
5e681ec4
PB		 14645 continue;
14646
14647 for (s = ibfd->sections; s != NULL; s = s->next)
14648 {
0bdcacaf 14649 struct elf_dyn_relocs *p;
5e681ec4 14650
0bdcacaf 14651 for (p = (struct elf_dyn_relocs *)
99059e56 14652 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 14653 {
0bdcacaf
RS		 14654 if (!bfd_is_abs_section (p->sec)
14655 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 14656 {
14657 /* Input section has been discarded, either because
14658 it is a copy of a linkonce section or due to
14659 linker script /DISCARD/, so we'll be discarding
14660 the relocs too. */
14661 }
3348747a 14662 else if (is_vxworks
0bdcacaf 14663 && strcmp (p->sec->output_section->name,
3348747a
NS		 14664 ".tls_vars") == 0)
14665 {
14666 /* Relocations in vxworks .tls_vars sections are
14667 handled specially by the loader. */
14668 }
5e681ec4
PB		 14669 else if (p->count != 0)
14670 {
0bdcacaf 14671 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 14672 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 14673 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 14674 info->flags |= DF_TEXTREL;
14675 }
14676 }
14677 }
14678
14679 local_got = elf_local_got_refcounts (ibfd);
14680 if (!local_got)
14681 continue;
14682
0ffa91dd 14683 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 14684 locsymcount = symtab_hdr->sh_info;
14685 end_local_got = local_got + locsymcount;
34e77a92 14686 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 14687 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 14688 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 14689 symndx = 0;
362d30a1
RS		 14690 s = htab->root.sgot;
14691 srel = htab->root.srelgot;
0855e32b 14692 for (; local_got < end_local_got;
34e77a92
RS		 14693 ++local_got, ++local_iplt_ptr, ++local_tls_type,
14694 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 14695 {
0855e32b 14696 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 14697 local_iplt = *local_iplt_ptr;
14698 if (local_iplt != NULL)
14699 {
14700 struct elf_dyn_relocs *p;
14701
14702 if (local_iplt->root.refcount > 0)
14703 {
14704 elf32_arm_allocate_plt_entry (info, TRUE,
14705 &local_iplt->root,
14706 &local_iplt->arm);
14707 if (local_iplt->arm.noncall_refcount == 0)
14708 /* All references to the PLT are calls, so all
14709 non-call references can resolve directly to the
14710 run-time target. This means that the .got entry
14711 would be the same as the .igot.plt entry, so there's
14712 no point creating both. */
14713 *local_got = 0;
14714 }
14715 else
14716 {
14717 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
14718 local_iplt->root.offset = (bfd_vma) -1;
14719 }
14720
14721 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
14722 {
14723 asection *psrel;
14724
14725 psrel = elf_section_data (p->sec)->sreloc;
14726 if (local_iplt->arm.noncall_refcount == 0)
14727 elf32_arm_allocate_irelocs (info, psrel, p->count);
14728 else
14729 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
14730 }
14731 }
5e681ec4
PB		 14732 if (*local_got > 0)
14733 {
34e77a92
RS		 14734 Elf_Internal_Sym *isym;
14735
eea6121a 14736 *local_got = s->size;
ba93b8ac
DJ		 14737 if (*local_tls_type & GOT_TLS_GD)
14738 /* TLS_GD relocs need an 8-byte structure in the GOT. */
14739 s->size += 8;
0855e32b
NS		 14740 if (*local_tls_type & GOT_TLS_GDESC)
14741 {
14742 *local_tlsdesc_gotent = htab->root.sgotplt->size
14743 - elf32_arm_compute_jump_table_size (htab);
14744 htab->root.sgotplt->size += 8;
14745 *local_got = (bfd_vma) -2;
34e77a92 14746 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 14747 reloc in the middle of .got.plt. */
99059e56 14748 htab->num_tls_desc++;
0855e32b 14749 }
ba93b8ac
DJ		 14750 if (*local_tls_type & GOT_TLS_IE)
14751 s->size += 4;
ba93b8ac 14752
0855e32b
NS		 14753 if (*local_tls_type & GOT_NORMAL)
14754 {
14755 /* If the symbol is both GD and GDESC, *local_got
14756 may have been overwritten. */
14757 *local_got = s->size;
14758 s->size += 4;
14759 }
14760
34e77a92
RS		 14761 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
14762 if (isym == NULL)
14763 return FALSE;
14764
14765 /* If all references to an STT_GNU_IFUNC PLT are calls,
14766 then all non-call references, including this GOT entry,
14767 resolve directly to the run-time target. */
14768 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
14769 && (local_iplt == NULL
14770 || local_iplt->arm.noncall_refcount == 0))
14771 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 14772 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 14773 {
0e1862bb 14774 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 14775 || *local_tls_type & GOT_TLS_GD)
14776 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 14777
0e1862bb 14778 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 14779 {
14780 elf32_arm_allocate_dynrelocs (info,
14781 htab->root.srelplt, 1);
14782 htab->tls_trampoline = -1;
14783 }
0855e32b 14784 }
5e681ec4
PB		 14785 }
14786 else
14787 *local_got = (bfd_vma) -1;
14788 }
252b5132
RH		 14789 }
14790
ba93b8ac
DJ		 14791 if (htab->tls_ldm_got.refcount > 0)
14792 {
14793 /* Allocate two GOT entries and one dynamic relocation (if necessary)
14794 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 14795 htab->tls_ldm_got.offset = htab->root.sgot->size;
14796 htab->root.sgot->size += 8;
0e1862bb 14797 if (bfd_link_pic (info))
47beaa6a 14798 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 14799 }
14800 else
14801 htab->tls_ldm_got.offset = -1;
14802
5e681ec4
PB		 14803 /* Allocate global sym .plt and .got entries, and space for global
14804 sym dynamic relocs. */
47beaa6a 14805 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 14806
d504ffc8 14807 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 14808 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 14809 {
0ffa91dd 14810 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 14811 continue;
14812
c7b8f16e
JB		 14813 /* Initialise mapping tables for code/data. */
14814 bfd_elf32_arm_init_maps (ibfd);
906e58ca 14815
c7b8f16e 14816 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 14817 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
14818 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
99059e56
RM		 14819 /* xgettext:c-format */
14820 _bfd_error_handler (_("Errors encountered processing file %s"),
c7b8f16e
JB		 14821 ibfd->filename);
14822 }
d504ffc8 14823
3e6b1042
DJ		 14824 /* Allocate space for the glue sections now that we've sized them. */
14825 bfd_elf32_arm_allocate_interworking_sections (info);
14826
0855e32b
NS		 14827 /* For every jump slot reserved in the sgotplt, reloc_count is
14828 incremented. However, when we reserve space for TLS descriptors,
14829 it's not incremented, so in order to compute the space reserved
14830 for them, it suffices to multiply the reloc count by the jump
14831 slot size. */
14832 if (htab->root.srelplt)
14833 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
14834
14835 if (htab->tls_trampoline)
14836 {
14837 if (htab->root.splt->size == 0)
14838 htab->root.splt->size += htab->plt_header_size;
b38cadfb 14839
0855e32b
NS		 14840 htab->tls_trampoline = htab->root.splt->size;
14841 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 14842
0855e32b 14843 /* If we're not using lazy TLS relocations, don't generate the
99059e56 14844 PLT and GOT entries they require. */
0855e32b
NS		 14845 if (!(info->flags & DF_BIND_NOW))
14846 {
14847 htab->dt_tlsdesc_got = htab->root.sgot->size;
14848 htab->root.sgot->size += 4;
14849
14850 htab->dt_tlsdesc_plt = htab->root.splt->size;
14851 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
14852 }
14853 }
14854
252b5132
RH		 14855 /* The check_relocs and adjust_dynamic_symbol entry points have
14856 determined the sizes of the various dynamic sections. Allocate
14857 memory for them. */
b34976b6
AM		 14858 plt = FALSE;
14859 relocs = FALSE;
252b5132
RH		 14860 for (s = dynobj->sections; s != NULL; s = s->next)
14861 {
14862 const char * name;
252b5132
RH		 14863
14864 if ((s->flags & SEC_LINKER_CREATED) == 0)
14865 continue;
14866
14867 /* It's OK to base decisions on the section name, because none
14868 of the dynobj section names depend upon the input files. */
14869 name = bfd_get_section_name (dynobj, s);
14870
34e77a92 14871 if (s == htab->root.splt)
252b5132 14872 {
c456f082
AM		 14873 /* Remember whether there is a PLT. */
14874 plt = s->size != 0;
252b5132 14875 }
0112cd26 14876 else if (CONST_STRNEQ (name, ".rel"))
252b5132 14877 {
c456f082 14878 if (s->size != 0)
252b5132 14879 {
252b5132 14880 /* Remember whether there are any reloc sections other
00a97672 14881 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 14882 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 14883 relocs = TRUE;
252b5132
RH		 14884
14885 /* We use the reloc_count field as a counter if we need
14886 to copy relocs into the output file. */
14887 s->reloc_count = 0;
14888 }
14889 }
34e77a92
RS		 14890 else if (s != htab->root.sgot
14891 && s != htab->root.sgotplt
14892 && s != htab->root.iplt
14893 && s != htab->root.igotplt
14894 && s != htab->sdynbss)
252b5132
RH		 14895 {
14896 /* It's not one of our sections, so don't allocate space. */
14897 continue;
14898 }
14899
c456f082 14900 if (s->size == 0)
252b5132 14901 {
c456f082 14902 /* If we don't need this section, strip it from the
00a97672
RS		 14903 output file. This is mostly to handle .rel(a).bss and
14904 .rel(a).plt. We must create both sections in
c456f082
AM		 14905 create_dynamic_sections, because they must be created
14906 before the linker maps input sections to output
14907 sections. The linker does that before
14908 adjust_dynamic_symbol is called, and it is that
14909 function which decides whether anything needs to go
14910 into these sections. */
8423293d 14911 s->flags |= SEC_EXCLUDE;
252b5132
RH		 14912 continue;
14913 }
14914
c456f082
AM		 14915 if ((s->flags & SEC_HAS_CONTENTS) == 0)
14916 continue;
14917
252b5132 14918 /* Allocate memory for the section contents. */
21d799b5 14919 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 14920 if (s->contents == NULL)
b34976b6 14921 return FALSE;
252b5132
RH		 14922 }
14923
14924 if (elf_hash_table (info)->dynamic_sections_created)
14925 {
14926 /* Add some entries to the .dynamic section. We fill in the
14927 values later, in elf32_arm_finish_dynamic_sections, but we
14928 must add the entries now so that we get the correct size for
14929 the .dynamic section. The DT_DEBUG entry is filled in by the
14930 dynamic linker and used by the debugger. */
dc810e39 14931#define add_dynamic_entry(TAG, VAL) \
5a580b3a 14932 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 14933
0e1862bb 14934 if (bfd_link_executable (info))
252b5132 14935 {
dc810e39 14936 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 14937 return FALSE;
252b5132
RH		 14938 }
14939
14940 if (plt)
14941 {
dc810e39
AM		 14942 if ( !add_dynamic_entry (DT_PLTGOT, 0)
14943 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 14944 || !add_dynamic_entry (DT_PLTREL,
14945 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 14946 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 14947 return FALSE;
0855e32b
NS		 14948
14949 if (htab->dt_tlsdesc_plt &&
b38cadfb 14950 (!add_dynamic_entry (DT_TLSDESC_PLT,0)
0855e32b 14951 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 14952 return FALSE;
252b5132
RH		 14953 }
14954
14955 if (relocs)
14956 {
00a97672
RS		 14957 if (htab->use_rel)
14958 {
14959 if (!add_dynamic_entry (DT_REL, 0)
14960 || !add_dynamic_entry (DT_RELSZ, 0)
14961 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
14962 return FALSE;
14963 }
14964 else
14965 {
14966 if (!add_dynamic_entry (DT_RELA, 0)
14967 || !add_dynamic_entry (DT_RELASZ, 0)
14968 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
14969 return FALSE;
14970 }
252b5132
RH		 14971 }
14972
08d1f311
DJ		 14973 /* If any dynamic relocs apply to a read-only section,
14974 then we need a DT_TEXTREL entry. */
14975 if ((info->flags & DF_TEXTREL) == 0)
8029a119
NC		 14976 elf_link_hash_traverse (& htab->root, elf32_arm_readonly_dynrelocs,
14977 info);
08d1f311 14978
99e4ae17 14979 if ((info->flags & DF_TEXTREL) != 0)
252b5132 14980 {
dc810e39 14981 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 14982 return FALSE;
252b5132 14983 }
7a2b07ff
NS		 14984 if (htab->vxworks_p
14985 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
14986 return FALSE;
252b5132 14987 }
8532796c 14988#undef add_dynamic_entry
252b5132 14989
b34976b6 14990 return TRUE;
252b5132
RH		 14991}
14992
0855e32b
NS		 14993/* Size sections even though they're not dynamic. We use it to setup
14994 _TLS_MODULE_BASE_, if needed. */
14995
14996static bfd_boolean
14997elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 14998 struct bfd_link_info *info)
0855e32b
NS		 14999{
15000 asection *tls_sec;
15001
0e1862bb 15002 if (bfd_link_relocatable (info))
0855e32b
NS		 15003 return TRUE;
15004
15005 tls_sec = elf_hash_table (info)->tls_sec;
15006
15007 if (tls_sec)
15008 {
15009 struct elf_link_hash_entry *tlsbase;
15010
15011 tlsbase = elf_link_hash_lookup
15012 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
15013
15014 if (tlsbase)
99059e56
RM		 15015 {
15016 struct bfd_link_hash_entry *bh = NULL;
0855e32b 15017 const struct elf_backend_data *bed
99059e56 15018 = get_elf_backend_data (output_bfd);
0855e32b 15019
99059e56 15020 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 15021 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
15022 tls_sec, 0, NULL, FALSE,
15023 bed->collect, &bh)))
15024 return FALSE;
b38cadfb 15025
99059e56
RM		 15026 tlsbase->type = STT_TLS;
15027 tlsbase = (struct elf_link_hash_entry *)bh;
15028 tlsbase->def_regular = 1;
15029 tlsbase->other = STV_HIDDEN;
15030 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 15031 }
15032 }
15033 return TRUE;
15034}
15035
252b5132
RH		 15036/* Finish up dynamic symbol handling. We set the contents of various
15037 dynamic sections here. */
15038
b34976b6 15039static bfd_boolean
906e58ca
NC		 15040elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
15041 struct bfd_link_info * info,
15042 struct elf_link_hash_entry * h,
15043 Elf_Internal_Sym * sym)
252b5132 15044{
e5a52504 15045 struct elf32_arm_link_hash_table *htab;
b7693d02 15046 struct elf32_arm_link_hash_entry *eh;
252b5132 15047
e5a52504 15048 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15049 if (htab == NULL)
15050 return FALSE;
15051
b7693d02 15052 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 15053
15054 if (h->plt.offset != (bfd_vma) -1)
15055 {
34e77a92 15056 if (!eh->is_iplt)
e5a52504 15057 {
34e77a92 15058 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 15059 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
15060 h->dynindx, 0))
15061 return FALSE;
e5a52504 15062 }
57e8b36a 15063
f5385ebf 15064 if (!h->def_regular)
252b5132
RH		 15065 {
15066 /* Mark the symbol as undefined, rather than as defined in
3a635617 15067 the .plt section. */
252b5132 15068 sym->st_shndx = SHN_UNDEF;
3a635617 15069 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 15070 Otherwise, the PLT entry would provide a definition for
15071 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 15072 and so the symbol would never be NULL. Leave the value if
15073 there were any relocations where pointer equality matters
15074 (this is a clue for the dynamic linker, to make function
15075 pointer comparisons work between an application and shared
15076 library). */
97323ad1 15077 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 15078 sym->st_value = 0;
252b5132 15079 }
34e77a92
RS		 15080 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
15081 {
15082 /* At least one non-call relocation references this .iplt entry,
15083 so the .iplt entry is the function's canonical address. */
15084 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
15085 sym->st_target_internal = ST_BRANCH_TO_ARM;
15086 sym->st_shndx = (_bfd_elf_section_from_bfd_section
15087 (output_bfd, htab->root.iplt->output_section));
15088 sym->st_value = (h->plt.offset
15089 + htab->root.iplt->output_section->vma
15090 + htab->root.iplt->output_offset);
15091 }
252b5132
RH		 15092 }
15093
f5385ebf 15094 if (h->needs_copy)
252b5132
RH		 15095 {
15096 asection * s;
947216bf 15097 Elf_Internal_Rela rel;
252b5132
RH		 15098
15099 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 15100 BFD_ASSERT (h->dynindx != -1
15101 && (h->root.type == bfd_link_hash_defined
15102 || h->root.type == bfd_link_hash_defweak));
15103
362d30a1 15104 s = htab->srelbss;
252b5132
RH		 15105 BFD_ASSERT (s != NULL);
15106
00a97672 15107 rel.r_addend = 0;
252b5132
RH		 15108 rel.r_offset = (h->root.u.def.value
15109 + h->root.u.def.section->output_section->vma
15110 + h->root.u.def.section->output_offset);
15111 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
47beaa6a 15112 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 15113 }
15114
00a97672
RS		 15115 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
15116 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
15117 to the ".got" section. */
9637f6ef 15118 if (h == htab->root.hdynamic
00a97672 15119 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 15120 sym->st_shndx = SHN_ABS;
15121
b34976b6 15122 return TRUE;
252b5132
RH		 15123}
15124
0855e32b
NS		 15125static void
15126arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
15127 void *contents,
15128 const unsigned long *template, unsigned count)
15129{
15130 unsigned ix;
b38cadfb 15131
0855e32b
NS		 15132 for (ix = 0; ix != count; ix++)
15133 {
15134 unsigned long insn = template[ix];
15135
15136 /* Emit mov pc,rx if bx is not permitted. */
15137 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
15138 insn = (insn & 0xf000000f) | 0x01a0f000;
15139 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
15140 }
15141}
15142
99059e56
RM		 15143/* Install the special first PLT entry for elf32-arm-nacl. Unlike
15144 other variants, NaCl needs this entry in a static executable's
15145 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
15146 zero. For .iplt really only the last bundle is useful, and .iplt
15147 could have a shorter first entry, with each individual PLT entry's
15148 relative branch calculated differently so it targets the last
15149 bundle instead of the instruction before it (labelled .Lplt_tail
15150 above). But it's simpler to keep the size and layout of PLT0
15151 consistent with the dynamic case, at the cost of some dead code at
15152 the start of .iplt and the one dead store to the stack at the start
15153 of .Lplt_tail. */
15154static void
15155arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
15156 asection *plt, bfd_vma got_displacement)
15157{
15158 unsigned int i;
15159
15160 put_arm_insn (htab, output_bfd,
15161 elf32_arm_nacl_plt0_entry[0]
15162 | arm_movw_immediate (got_displacement),
15163 plt->contents + 0);
15164 put_arm_insn (htab, output_bfd,
15165 elf32_arm_nacl_plt0_entry[1]
15166 | arm_movt_immediate (got_displacement),
15167 plt->contents + 4);
15168
15169 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
15170 put_arm_insn (htab, output_bfd,
15171 elf32_arm_nacl_plt0_entry[i],
15172 plt->contents + (i * 4));
15173}
15174
252b5132
RH		 15175/* Finish up the dynamic sections. */
15176
b34976b6 15177static bfd_boolean
57e8b36a 15178elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 15179{
15180 bfd * dynobj;
15181 asection * sgot;
15182 asection * sdyn;
4dfe6ac6
NC		 15183 struct elf32_arm_link_hash_table *htab;
15184
15185 htab = elf32_arm_hash_table (info);
15186 if (htab == NULL)
15187 return FALSE;
252b5132
RH		 15188
15189 dynobj = elf_hash_table (info)->dynobj;
15190
362d30a1 15191 sgot = htab->root.sgotplt;
894891db
NC		 15192 /* A broken linker script might have discarded the dynamic sections.
15193 Catch this here so that we do not seg-fault later on. */
15194 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
15195 return FALSE;
3d4d4302 15196 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 15197
15198 if (elf_hash_table (info)->dynamic_sections_created)
15199 {
15200 asection *splt;
15201 Elf32_External_Dyn *dyncon, *dynconend;
15202
362d30a1 15203 splt = htab->root.splt;
24a1ba0f 15204 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 15205 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 15206
15207 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 15208 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 15209
252b5132
RH		 15210 for (; dyncon < dynconend; dyncon++)
15211 {
15212 Elf_Internal_Dyn dyn;
15213 const char * name;
15214 asection * s;
15215
15216 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
15217
15218 switch (dyn.d_tag)
15219 {
229fcec5
MM		 15220 unsigned int type;
15221
252b5132 15222 default:
7a2b07ff
NS		 15223 if (htab->vxworks_p
15224 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
15225 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 15226 break;
15227
229fcec5
MM		 15228 case DT_HASH:
15229 name = ".hash";
15230 goto get_vma_if_bpabi;
15231 case DT_STRTAB:
15232 name = ".dynstr";
15233 goto get_vma_if_bpabi;
15234 case DT_SYMTAB:
15235 name = ".dynsym";
15236 goto get_vma_if_bpabi;
c0042f5d
MM		 15237 case DT_VERSYM:
15238 name = ".gnu.version";
15239 goto get_vma_if_bpabi;
15240 case DT_VERDEF:
15241 name = ".gnu.version_d";
15242 goto get_vma_if_bpabi;
15243 case DT_VERNEED:
15244 name = ".gnu.version_r";
15245 goto get_vma_if_bpabi;
15246
252b5132
RH		 15247 case DT_PLTGOT:
15248 name = ".got";
15249 goto get_vma;
15250 case DT_JMPREL:
00a97672 15251 name = RELOC_SECTION (htab, ".plt");
252b5132
RH		 15252 get_vma:
15253 s = bfd_get_section_by_name (output_bfd, name);
05456594
NC		 15254 if (s == NULL)
15255 {
15256 /* PR ld/14397: Issue an error message if a required section is missing. */
15257 (*_bfd_error_handler)
15258 (_("error: required section '%s' not found in the linker script"), name);
15259 bfd_set_error (bfd_error_invalid_operation);
15260 return FALSE;
15261 }
229fcec5
MM		 15262 if (!htab->symbian_p)
15263 dyn.d_un.d_ptr = s->vma;
15264 else
15265 /* In the BPABI, tags in the PT_DYNAMIC section point
15266 at the file offset, not the memory address, for the
15267 convenience of the post linker. */
15268 dyn.d_un.d_ptr = s->filepos;
252b5132
RH		 15269 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15270 break;
15271
229fcec5
MM		 15272 get_vma_if_bpabi:
15273 if (htab->symbian_p)
15274 goto get_vma;
15275 break;
15276
252b5132 15277 case DT_PLTRELSZ:
362d30a1 15278 s = htab->root.srelplt;
252b5132 15279 BFD_ASSERT (s != NULL);
eea6121a 15280 dyn.d_un.d_val = s->size;
252b5132
RH		 15281 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15282 break;
906e58ca 15283
252b5132 15284 case DT_RELSZ:
00a97672 15285 case DT_RELASZ:
229fcec5
MM		 15286 if (!htab->symbian_p)
15287 {
15288 /* My reading of the SVR4 ABI indicates that the
15289 procedure linkage table relocs (DT_JMPREL) should be
15290 included in the overall relocs (DT_REL). This is
15291 what Solaris does. However, UnixWare can not handle
15292 that case. Therefore, we override the DT_RELSZ entry
15293 here to make it not include the JMPREL relocs. Since
00a97672 15294 the linker script arranges for .rel(a).plt to follow all
229fcec5
MM		 15295 other relocation sections, we don't have to worry
15296 about changing the DT_REL entry. */
362d30a1 15297 s = htab->root.srelplt;
229fcec5
MM		 15298 if (s != NULL)
15299 dyn.d_un.d_val -= s->size;
15300 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15301 break;
15302 }
8029a119 15303 /* Fall through. */
229fcec5
MM		 15304
15305 case DT_REL:
15306 case DT_RELA:
229fcec5
MM		 15307 /* In the BPABI, the DT_REL tag must point at the file
15308 offset, not the VMA, of the first relocation
15309 section. So, we use code similar to that in
15310 elflink.c, but do not check for SHF_ALLOC on the
15311 relcoation section, since relocations sections are
15312 never allocated under the BPABI. The comments above
15313 about Unixware notwithstanding, we include all of the
15314 relocations here. */
15315 if (htab->symbian_p)
15316 {
15317 unsigned int i;
15318 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
15319 ? SHT_REL : SHT_RELA);
15320 dyn.d_un.d_val = 0;
15321 for (i = 1; i < elf_numsections (output_bfd); i++)
15322 {
906e58ca 15323 Elf_Internal_Shdr *hdr
229fcec5
MM		 15324 = elf_elfsections (output_bfd)[i];
15325 if (hdr->sh_type == type)
15326 {
906e58ca 15327 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 15328 || dyn.d_tag == DT_RELASZ)
15329 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 15330 else if ((ufile_ptr) hdr->sh_offset
15331 <= dyn.d_un.d_val - 1)
229fcec5
MM		 15332 dyn.d_un.d_val = hdr->sh_offset;
15333 }
15334 }
15335 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15336 }
252b5132 15337 break;
88f7bcd5 15338
0855e32b 15339 case DT_TLSDESC_PLT:
99059e56 15340 s = htab->root.splt;
0855e32b
NS		 15341 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
15342 + htab->dt_tlsdesc_plt);
15343 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15344 break;
15345
15346 case DT_TLSDESC_GOT:
99059e56 15347 s = htab->root.sgot;
0855e32b 15348 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 15349 + htab->dt_tlsdesc_got);
0855e32b
NS		 15350 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15351 break;
15352
88f7bcd5
NC		 15353 /* Set the bottom bit of DT_INIT/FINI if the
15354 corresponding function is Thumb. */
15355 case DT_INIT:
15356 name = info->init_function;
15357 goto get_sym;
15358 case DT_FINI:
15359 name = info->fini_function;
15360 get_sym:
15361 /* If it wasn't set by elf_bfd_final_link
4cc11e76 15362 then there is nothing to adjust. */
88f7bcd5
NC		 15363 if (dyn.d_un.d_val != 0)
15364 {
15365 struct elf_link_hash_entry * eh;
15366
15367 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 15368 FALSE, FALSE, TRUE);
35fc36a8 15369 if (eh != NULL && eh->target_internal == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 15370 {
15371 dyn.d_un.d_val |= 1;
b34976b6 15372 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 15373 }
15374 }
15375 break;
252b5132
RH		 15376 }
15377 }
15378
24a1ba0f 15379 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 15380 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 15381 {
00a97672
RS		 15382 const bfd_vma *plt0_entry;
15383 bfd_vma got_address, plt_address, got_displacement;
15384
15385 /* Calculate the addresses of the GOT and PLT. */
15386 got_address = sgot->output_section->vma + sgot->output_offset;
15387 plt_address = splt->output_section->vma + splt->output_offset;
15388
15389 if (htab->vxworks_p)
15390 {
15391 /* The VxWorks GOT is relocated by the dynamic linker.
15392 Therefore, we must emit relocations rather than simply
15393 computing the values now. */
15394 Elf_Internal_Rela rel;
15395
15396 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 15397 put_arm_insn (htab, output_bfd, plt0_entry[0],
15398 splt->contents + 0);
15399 put_arm_insn (htab, output_bfd, plt0_entry[1],
15400 splt->contents + 4);
15401 put_arm_insn (htab, output_bfd, plt0_entry[2],
15402 splt->contents + 8);
00a97672
RS		 15403 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
15404
8029a119 15405 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 15406 rel.r_offset = plt_address + 12;
15407 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
15408 rel.r_addend = 0;
15409 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
15410 htab->srelplt2->contents);
15411 }
b38cadfb 15412 else if (htab->nacl_p)
99059e56
RM		 15413 arm_nacl_put_plt0 (htab, output_bfd, splt,
15414 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 15415 else if (using_thumb_only (htab))
15416 {
15417 got_displacement = got_address - (plt_address + 12);
15418
15419 plt0_entry = elf32_thumb2_plt0_entry;
15420 put_arm_insn (htab, output_bfd, plt0_entry[0],
15421 splt->contents + 0);
15422 put_arm_insn (htab, output_bfd, plt0_entry[1],
15423 splt->contents + 4);
15424 put_arm_insn (htab, output_bfd, plt0_entry[2],
15425 splt->contents + 8);
15426
15427 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
15428 }
00a97672
RS		 15429 else
15430 {
15431 got_displacement = got_address - (plt_address + 16);
15432
15433 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 15434 put_arm_insn (htab, output_bfd, plt0_entry[0],
15435 splt->contents + 0);
15436 put_arm_insn (htab, output_bfd, plt0_entry[1],
15437 splt->contents + 4);
15438 put_arm_insn (htab, output_bfd, plt0_entry[2],
15439 splt->contents + 8);
15440 put_arm_insn (htab, output_bfd, plt0_entry[3],
15441 splt->contents + 12);
5e681ec4 15442
5e681ec4 15443#ifdef FOUR_WORD_PLT
00a97672
RS		 15444 /* The displacement value goes in the otherwise-unused
15445 last word of the second entry. */
15446 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 15447#else
00a97672 15448 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 15449#endif
00a97672 15450 }
f7a74f8c 15451 }
252b5132
RH		 15452
15453 /* UnixWare sets the entsize of .plt to 4, although that doesn't
15454 really seem like the right value. */
74541ad4
AM		 15455 if (splt->output_section->owner == output_bfd)
15456 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 15457
0855e32b
NS		 15458 if (htab->dt_tlsdesc_plt)
15459 {
15460 bfd_vma got_address
15461 = sgot->output_section->vma + sgot->output_offset;
15462 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
15463 + htab->root.sgot->output_offset);
15464 bfd_vma plt_address
15465 = splt->output_section->vma + splt->output_offset;
15466
b38cadfb 15467 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 15468 splt->contents + htab->dt_tlsdesc_plt,
15469 dl_tlsdesc_lazy_trampoline, 6);
15470
15471 bfd_put_32 (output_bfd,
15472 gotplt_address + htab->dt_tlsdesc_got
15473 - (plt_address + htab->dt_tlsdesc_plt)
15474 - dl_tlsdesc_lazy_trampoline[6],
15475 splt->contents + htab->dt_tlsdesc_plt + 24);
15476 bfd_put_32 (output_bfd,
15477 got_address - (plt_address + htab->dt_tlsdesc_plt)
15478 - dl_tlsdesc_lazy_trampoline[7],
15479 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
15480 }
15481
15482 if (htab->tls_trampoline)
15483 {
b38cadfb 15484 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 15485 splt->contents + htab->tls_trampoline,
15486 tls_trampoline, 3);
15487#ifdef FOUR_WORD_PLT
15488 bfd_put_32 (output_bfd, 0x00000000,
15489 splt->contents + htab->tls_trampoline + 12);
b38cadfb 15490#endif
0855e32b
NS		 15491 }
15492
0e1862bb
L		 15493 if (htab->vxworks_p
15494 && !bfd_link_pic (info)
15495 && htab->root.splt->size > 0)
00a97672
RS		 15496 {
15497 /* Correct the .rel(a).plt.unloaded relocations. They will have
15498 incorrect symbol indexes. */
15499 int num_plts;
eed62c48 15500 unsigned char *p;
00a97672 15501
362d30a1 15502 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 15503 / htab->plt_entry_size);
15504 p = htab->srelplt2->contents + RELOC_SIZE (htab);
15505
15506 for (; num_plts; num_plts--)
15507 {
15508 Elf_Internal_Rela rel;
15509
15510 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
15511 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
15512 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
15513 p += RELOC_SIZE (htab);
15514
15515 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
15516 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
15517 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
15518 p += RELOC_SIZE (htab);
15519 }
15520 }
252b5132
RH		 15521 }
15522
99059e56
RM		 15523 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
15524 /* NaCl uses a special first entry in .iplt too. */
15525 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
15526
252b5132 15527 /* Fill in the first three entries in the global offset table. */
229fcec5 15528 if (sgot)
252b5132 15529 {
229fcec5
MM		 15530 if (sgot->size > 0)
15531 {
15532 if (sdyn == NULL)
15533 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
15534 else
15535 bfd_put_32 (output_bfd,
15536 sdyn->output_section->vma + sdyn->output_offset,
15537 sgot->contents);
15538 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
15539 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
15540 }
252b5132 15541
229fcec5
MM		 15542 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
15543 }
252b5132 15544
b34976b6 15545 return TRUE;
252b5132
RH		 15546}
15547
ba96a88f 15548static void
57e8b36a 15549elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 15550{
9b485d32 15551 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 15552 struct elf32_arm_link_hash_table *globals;
ac4c9b04 15553 struct elf_segment_map *m;
ba96a88f
NC		 15554
15555 i_ehdrp = elf_elfheader (abfd);
15556
94a3258f
PB		 15557 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
15558 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
15559 else
7394f108 15560 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 15561 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 15562
93204d3a
PB		 15563 if (link_info)
15564 {
15565 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 15566 if (globals != NULL && globals->byteswap_code)
93204d3a
PB		 15567 i_ehdrp->e_flags |= EF_ARM_BE8;
15568 }
3bfcb652
NC		 15569
15570 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
15571 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
15572 {
15573 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 15574 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 15575 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
15576 else
15577 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
15578 }
ac4c9b04
MG		 15579
15580 /* Scan segment to set p_flags attribute if it contains only sections with
15581 SHF_ARM_NOREAD flag. */
15582 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
15583 {
15584 unsigned int j;
15585
15586 if (m->count == 0)
15587 continue;
15588 for (j = 0; j < m->count; j++)
15589 {
15590 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_NOREAD))
15591 break;
15592 }
15593 if (j == m->count)
15594 {
15595 m->p_flags = PF_X;
15596 m->p_flags_valid = 1;
15597 }
15598 }
ba96a88f
NC		 15599}
15600
99e4ae17 15601static enum elf_reloc_type_class
7e612e98
AM		 15602elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
15603 const asection *rel_sec ATTRIBUTE_UNUSED,
15604 const Elf_Internal_Rela *rela)
99e4ae17 15605{
f51e552e 15606 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 15607 {
15608 case R_ARM_RELATIVE:
15609 return reloc_class_relative;
15610 case R_ARM_JUMP_SLOT:
15611 return reloc_class_plt;
15612 case R_ARM_COPY:
15613 return reloc_class_copy;
109575d7
JW		 15614 case R_ARM_IRELATIVE:
15615 return reloc_class_ifunc;
99e4ae17
AJ		 15616 default:
15617 return reloc_class_normal;
15618 }
15619}
15620
e489d0ae 15621static void
57e8b36a 15622elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 15623{
5a6c6817 15624 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 15625}
15626
40a18ebd
NC		 15627/* Return TRUE if this is an unwinding table entry. */
15628
15629static bfd_boolean
15630is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
15631{
0112cd26
NC		 15632 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
15633 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 15634}
15635
15636
15637/* Set the type and flags for an ARM section. We do this by
15638 the section name, which is a hack, but ought to work. */
15639
15640static bfd_boolean
15641elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
15642{
15643 const char * name;
15644
15645 name = bfd_get_section_name (abfd, sec);
15646
15647 if (is_arm_elf_unwind_section_name (abfd, name))
15648 {
15649 hdr->sh_type = SHT_ARM_EXIDX;
15650 hdr->sh_flags |= SHF_LINK_ORDER;
15651 }
ac4c9b04
MG		 15652
15653 if (sec->flags & SEC_ELF_NOREAD)
15654 hdr->sh_flags |= SHF_ARM_NOREAD;
15655
40a18ebd
NC		 15656 return TRUE;
15657}
15658
6dc132d9
L		 15659/* Handle an ARM specific section when reading an object file. This is
15660 called when bfd_section_from_shdr finds a section with an unknown
15661 type. */
40a18ebd
NC		 15662
15663static bfd_boolean
15664elf32_arm_section_from_shdr (bfd *abfd,
15665 Elf_Internal_Shdr * hdr,
6dc132d9
L		 15666 const char *name,
15667 int shindex)
40a18ebd
NC		 15668{
15669 /* There ought to be a place to keep ELF backend specific flags, but
15670 at the moment there isn't one. We just keep track of the
15671 sections by their name, instead. Fortunately, the ABI gives
15672 names for all the ARM specific sections, so we will probably get
15673 away with this. */
15674 switch (hdr->sh_type)
15675 {
15676 case SHT_ARM_EXIDX:
0951f019
RE		 15677 case SHT_ARM_PREEMPTMAP:
15678 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 15679 break;
15680
15681 default:
15682 return FALSE;
15683 }
15684
6dc132d9 15685 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 15686 return FALSE;
15687
15688 return TRUE;
15689}
e489d0ae 15690
44444f50
NC		 15691static _arm_elf_section_data *
15692get_arm_elf_section_data (asection * sec)
15693{
47b2e99c
JZ		 15694 if (sec && sec->owner && is_arm_elf (sec->owner))
15695 return elf32_arm_section_data (sec);
44444f50
NC		 15696 else
15697 return NULL;
8e3de13a
NC		 15698}
15699
4e617b1e
PB		 15700typedef struct
15701{
57402f1e 15702 void *flaginfo;
4e617b1e 15703 struct bfd_link_info *info;
91a5743d
PB		 15704 asection *sec;
15705 int sec_shndx;
6e0b88f1
AM		 15706 int (*func) (void *, const char *, Elf_Internal_Sym *,
15707 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 15708} output_arch_syminfo;
15709
15710enum map_symbol_type
15711{
15712 ARM_MAP_ARM,
15713 ARM_MAP_THUMB,
15714 ARM_MAP_DATA
15715};
15716
15717
7413f23f 15718/* Output a single mapping symbol. */
4e617b1e
PB		 15719
15720static bfd_boolean
7413f23f
DJ		 15721elf32_arm_output_map_sym (output_arch_syminfo *osi,
15722 enum map_symbol_type type,
15723 bfd_vma offset)
4e617b1e
PB		 15724{
15725 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 15726 Elf_Internal_Sym sym;
15727
91a5743d
PB		 15728 sym.st_value = osi->sec->output_section->vma
15729 + osi->sec->output_offset
15730 + offset;
4e617b1e
PB		 15731 sym.st_size = 0;
15732 sym.st_other = 0;
15733 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 15734 sym.st_shndx = osi->sec_shndx;
35fc36a8 15735 sym.st_target_internal = 0;
fe33d2fa 15736 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 15737 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 15738}
15739
34e77a92
RS		 15740/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
15741 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 15742
15743static bfd_boolean
34e77a92
RS		 15744elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
15745 bfd_boolean is_iplt_entry_p,
15746 union gotplt_union *root_plt,
15747 struct arm_plt_info *arm_plt)
4e617b1e 15748{
4e617b1e 15749 struct elf32_arm_link_hash_table *htab;
34e77a92 15750 bfd_vma addr, plt_header_size;
4e617b1e 15751
34e77a92 15752 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 15753 return TRUE;
15754
4dfe6ac6
NC		 15755 htab = elf32_arm_hash_table (osi->info);
15756 if (htab == NULL)
15757 return FALSE;
15758
34e77a92
RS		 15759 if (is_iplt_entry_p)
15760 {
15761 osi->sec = htab->root.iplt;
15762 plt_header_size = 0;
15763 }
15764 else
15765 {
15766 osi->sec = htab->root.splt;
15767 plt_header_size = htab->plt_header_size;
15768 }
15769 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
15770 (osi->info->output_bfd, osi->sec->output_section));
15771
15772 addr = root_plt->offset & -2;
4e617b1e
PB		 15773 if (htab->symbian_p)
15774 {
7413f23f 15775 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15776 return FALSE;
7413f23f 15777 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 15778 return FALSE;
15779 }
15780 else if (htab->vxworks_p)
15781 {
7413f23f 15782 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15783 return FALSE;
7413f23f 15784 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 15785 return FALSE;
7413f23f 15786 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 15787 return FALSE;
7413f23f 15788 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 15789 return FALSE;
15790 }
b38cadfb
NC		 15791 else if (htab->nacl_p)
15792 {
15793 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
15794 return FALSE;
15795 }
eed94f8f
NC		 15796 else if (using_thumb_only (htab))
15797 {
15798 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
15799 return FALSE;
6a631e86 15800 }
4e617b1e
PB		 15801 else
15802 {
34e77a92 15803 bfd_boolean thumb_stub_p;
bd97cb95 15804
34e77a92
RS		 15805 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
15806 if (thumb_stub_p)
4e617b1e 15807 {
7413f23f 15808 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 15809 return FALSE;
15810 }
15811#ifdef FOUR_WORD_PLT
7413f23f 15812 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15813 return FALSE;
7413f23f 15814 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 15815 return FALSE;
15816#else
906e58ca 15817 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 15818 so only need to output a mapping symbol for the first PLT entry and
15819 entries with thumb thunks. */
34e77a92 15820 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 15821 {
7413f23f 15822 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 15823 return FALSE;
15824 }
15825#endif
15826 }
15827
15828 return TRUE;
15829}
15830
34e77a92
RS		 15831/* Output mapping symbols for PLT entries associated with H. */
15832
15833static bfd_boolean
15834elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
15835{
15836 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
15837 struct elf32_arm_link_hash_entry *eh;
15838
15839 if (h->root.type == bfd_link_hash_indirect)
15840 return TRUE;
15841
15842 if (h->root.type == bfd_link_hash_warning)
15843 /* When warning symbols are created, they **replace** the "real"
15844 entry in the hash table, thus we never get to see the real
15845 symbol in a hash traversal. So look at it now. */
15846 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15847
15848 eh = (struct elf32_arm_link_hash_entry *) h;
15849 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
15850 &h->plt, &eh->plt);
15851}
15852
7413f23f
DJ		 15853/* Output a single local symbol for a generated stub. */
15854
15855static bfd_boolean
15856elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
15857 bfd_vma offset, bfd_vma size)
15858{
7413f23f
DJ		 15859 Elf_Internal_Sym sym;
15860
7413f23f
DJ		 15861 sym.st_value = osi->sec->output_section->vma
15862 + osi->sec->output_offset
15863 + offset;
15864 sym.st_size = size;
15865 sym.st_other = 0;
15866 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
15867 sym.st_shndx = osi->sec_shndx;
35fc36a8 15868 sym.st_target_internal = 0;
57402f1e 15869 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 15870}
4e617b1e 15871
da5938a2 15872static bfd_boolean
8029a119
NC		 15873arm_map_one_stub (struct bfd_hash_entry * gen_entry,
15874 void * in_arg)
da5938a2
NC		 15875{
15876 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 15877 asection *stub_sec;
15878 bfd_vma addr;
7413f23f 15879 char *stub_name;
9a008db3 15880 output_arch_syminfo *osi;
d3ce72d0 15881 const insn_sequence *template_sequence;
461a49ca
DJ		 15882 enum stub_insn_type prev_type;
15883 int size;
15884 int i;
15885 enum map_symbol_type sym_type;
da5938a2
NC		 15886
15887 /* Massage our args to the form they really have. */
15888 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 15889 osi = (output_arch_syminfo *) in_arg;
da5938a2 15890
da5938a2
NC		 15891 stub_sec = stub_entry->stub_sec;
15892
15893 /* Ensure this stub is attached to the current section being
7413f23f 15894 processed. */
da5938a2
NC		 15895 if (stub_sec != osi->sec)
15896 return TRUE;
15897
7413f23f
DJ		 15898 addr = (bfd_vma) stub_entry->stub_offset;
15899 stub_name = stub_entry->output_name;
da5938a2 15900
d3ce72d0
NC		 15901 template_sequence = stub_entry->stub_template;
15902 switch (template_sequence[0].type)
7413f23f 15903 {
461a49ca
DJ		 15904 case ARM_TYPE:
15905 if (!elf32_arm_output_stub_sym (osi, stub_name, addr, stub_entry->stub_size))
da5938a2
NC		 15906 return FALSE;
15907 break;
461a49ca 15908 case THUMB16_TYPE:
48229727 15909 case THUMB32_TYPE:
461a49ca
DJ		 15910 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
15911 stub_entry->stub_size))
da5938a2
NC		 15912 return FALSE;
15913 break;
15914 default:
15915 BFD_FAIL ();
48229727 15916 return 0;
7413f23f 15917 }
da5938a2 15918
461a49ca
DJ		 15919 prev_type = DATA_TYPE;
15920 size = 0;
15921 for (i = 0; i < stub_entry->stub_template_size; i++)
15922 {
d3ce72d0 15923 switch (template_sequence[i].type)
461a49ca
DJ		 15924 {
15925 case ARM_TYPE:
15926 sym_type = ARM_MAP_ARM;
15927 break;
15928
15929 case THUMB16_TYPE:
48229727 15930 case THUMB32_TYPE:
461a49ca
DJ		 15931 sym_type = ARM_MAP_THUMB;
15932 break;
15933
15934 case DATA_TYPE:
15935 sym_type = ARM_MAP_DATA;
15936 break;
15937
15938 default:
15939 BFD_FAIL ();
4e31c731 15940 return FALSE;
461a49ca
DJ		 15941 }
15942
d3ce72d0 15943 if (template_sequence[i].type != prev_type)
461a49ca 15944 {
d3ce72d0 15945 prev_type = template_sequence[i].type;
461a49ca
DJ		 15946 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
15947 return FALSE;
15948 }
15949
d3ce72d0 15950 switch (template_sequence[i].type)
461a49ca
DJ		 15951 {
15952 case ARM_TYPE:
48229727 15953 case THUMB32_TYPE:
461a49ca
DJ		 15954 size += 4;
15955 break;
15956
15957 case THUMB16_TYPE:
15958 size += 2;
15959 break;
15960
15961 case DATA_TYPE:
15962 size += 4;
15963 break;
15964
15965 default:
15966 BFD_FAIL ();
4e31c731 15967 return FALSE;
461a49ca
DJ		 15968 }
15969 }
15970
da5938a2
NC		 15971 return TRUE;
15972}
15973
33811162
DG		 15974/* Output mapping symbols for linker generated sections,
15975 and for those data-only sections that do not have a
15976 $d. */
4e617b1e
PB		 15977
15978static bfd_boolean
15979elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 15980 struct bfd_link_info *info,
57402f1e 15981 void *flaginfo,
6e0b88f1
AM		 15982 int (*func) (void *, const char *,
15983 Elf_Internal_Sym *,
15984 asection *,
15985 struct elf_link_hash_entry *))
4e617b1e
PB		 15986{
15987 output_arch_syminfo osi;
15988 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 15989 bfd_vma offset;
15990 bfd_size_type size;
33811162 15991 bfd *input_bfd;
4e617b1e
PB		 15992
15993 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15994 if (htab == NULL)
15995 return FALSE;
15996
906e58ca 15997 check_use_blx (htab);
91a5743d 15998
57402f1e 15999 osi.flaginfo = flaginfo;
4e617b1e
PB		 16000 osi.info = info;
16001 osi.func = func;
906e58ca 16002
33811162
DG		 16003 /* Add a $d mapping symbol to data-only sections that
16004 don't have any mapping symbol. This may result in (harmless) redundant
16005 mapping symbols. */
16006 for (input_bfd = info->input_bfds;
16007 input_bfd != NULL;
c72f2fb2 16008 input_bfd = input_bfd->link.next)
33811162
DG		 16009 {
16010 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
16011 for (osi.sec = input_bfd->sections;
16012 osi.sec != NULL;
16013 osi.sec = osi.sec->next)
16014 {
16015 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 16016 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
16017 != 0)
33811162
DG		 16018 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
16019 == SEC_HAS_CONTENTS
16020 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 16021 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 16022 && osi.sec->size > 0
16023 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 16024 {
16025 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16026 (output_bfd, osi.sec->output_section);
16027 if (osi.sec_shndx != (int)SHN_BAD)
16028 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
16029 }
16030 }
16031 }
16032
91a5743d
PB		 16033 /* ARM->Thumb glue. */
16034 if (htab->arm_glue_size > 0)
16035 {
3d4d4302
AM		 16036 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
16037 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 16038
16039 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16040 (output_bfd, osi.sec->output_section);
0e1862bb 16041 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 16042 || htab->pic_veneer)
16043 size = ARM2THUMB_PIC_GLUE_SIZE;
16044 else if (htab->use_blx)
16045 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
16046 else
16047 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 16048
91a5743d
PB		 16049 for (offset = 0; offset < htab->arm_glue_size; offset += size)
16050 {
7413f23f
DJ		 16051 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
16052 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 16053 }
16054 }
16055
16056 /* Thumb->ARM glue. */
16057 if (htab->thumb_glue_size > 0)
16058 {
3d4d4302
AM		 16059 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
16060 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 16061
16062 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16063 (output_bfd, osi.sec->output_section);
16064 size = THUMB2ARM_GLUE_SIZE;
16065
16066 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
16067 {
7413f23f
DJ		 16068 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
16069 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 16070 }
16071 }
16072
845b51d6
PB		 16073 /* ARMv4 BX veneers. */
16074 if (htab->bx_glue_size > 0)
16075 {
3d4d4302
AM		 16076 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
16077 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 16078
16079 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16080 (output_bfd, osi.sec->output_section);
16081
7413f23f 16082 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 16083 }
16084
8029a119
NC		 16085 /* Long calls stubs. */
16086 if (htab->stub_bfd && htab->stub_bfd->sections)
16087 {
da5938a2 16088 asection* stub_sec;
8029a119 16089
da5938a2
NC		 16090 for (stub_sec = htab->stub_bfd->sections;
16091 stub_sec != NULL;
8029a119
NC		 16092 stub_sec = stub_sec->next)
16093 {
16094 /* Ignore non-stub sections. */
16095 if (!strstr (stub_sec->name, STUB_SUFFIX))
16096 continue;
da5938a2 16097
8029a119 16098 osi.sec = stub_sec;
da5938a2 16099
8029a119
NC		 16100 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16101 (output_bfd, osi.sec->output_section);
da5938a2 16102
8029a119
NC		 16103 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
16104 }
16105 }
da5938a2 16106
91a5743d 16107 /* Finally, output mapping symbols for the PLT. */
34e77a92 16108 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 16109 {
34e77a92
RS		 16110 osi.sec = htab->root.splt;
16111 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
16112 (output_bfd, osi.sec->output_section));
16113
16114 /* Output mapping symbols for the plt header. SymbianOS does not have a
16115 plt header. */
16116 if (htab->vxworks_p)
16117 {
16118 /* VxWorks shared libraries have no PLT header. */
0e1862bb 16119 if (!bfd_link_pic (info))
34e77a92
RS		 16120 {
16121 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16122 return FALSE;
16123 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
16124 return FALSE;
16125 }
16126 }
b38cadfb
NC		 16127 else if (htab->nacl_p)
16128 {
16129 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16130 return FALSE;
16131 }
eed94f8f
NC		 16132 else if (using_thumb_only (htab))
16133 {
16134 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
16135 return FALSE;
16136 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
16137 return FALSE;
16138 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
16139 return FALSE;
16140 }
34e77a92 16141 else if (!htab->symbian_p)
4e617b1e 16142 {
7413f23f 16143 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 16144 return FALSE;
34e77a92
RS		 16145#ifndef FOUR_WORD_PLT
16146 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 16147 return FALSE;
34e77a92 16148#endif
4e617b1e
PB		 16149 }
16150 }
99059e56
RM		 16151 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
16152 {
16153 /* NaCl uses a special first entry in .iplt too. */
16154 osi.sec = htab->root.iplt;
16155 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
16156 (output_bfd, osi.sec->output_section));
16157 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16158 return FALSE;
16159 }
34e77a92
RS		 16160 if ((htab->root.splt && htab->root.splt->size > 0)
16161 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 16162 {
34e77a92
RS		 16163 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
16164 for (input_bfd = info->input_bfds;
16165 input_bfd != NULL;
c72f2fb2 16166 input_bfd = input_bfd->link.next)
34e77a92
RS		 16167 {
16168 struct arm_local_iplt_info **local_iplt;
16169 unsigned int i, num_syms;
4e617b1e 16170
34e77a92
RS		 16171 local_iplt = elf32_arm_local_iplt (input_bfd);
16172 if (local_iplt != NULL)
16173 {
16174 num_syms = elf_symtab_hdr (input_bfd).sh_info;
16175 for (i = 0; i < num_syms; i++)
16176 if (local_iplt[i] != NULL
16177 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
16178 &local_iplt[i]->root,
16179 &local_iplt[i]->arm))
16180 return FALSE;
16181 }
16182 }
16183 }
0855e32b
NS		 16184 if (htab->dt_tlsdesc_plt != 0)
16185 {
16186 /* Mapping symbols for the lazy tls trampoline. */
16187 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
16188 return FALSE;
b38cadfb 16189
0855e32b
NS		 16190 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
16191 htab->dt_tlsdesc_plt + 24))
16192 return FALSE;
16193 }
16194 if (htab->tls_trampoline != 0)
16195 {
16196 /* Mapping symbols for the tls trampoline. */
16197 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
16198 return FALSE;
16199#ifdef FOUR_WORD_PLT
16200 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
16201 htab->tls_trampoline + 12))
16202 return FALSE;
b38cadfb 16203#endif
0855e32b 16204 }
b38cadfb 16205
4e617b1e
PB		 16206 return TRUE;
16207}
16208
e489d0ae
PB		 16209/* Allocate target specific section data. */
16210
16211static bfd_boolean
16212elf32_arm_new_section_hook (bfd *abfd, asection *sec)
16213{
f592407e
AM		 16214 if (!sec->used_by_bfd)
16215 {
16216 _arm_elf_section_data *sdata;
16217 bfd_size_type amt = sizeof (*sdata);
e489d0ae 16218
21d799b5 16219 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 16220 if (sdata == NULL)
16221 return FALSE;
16222 sec->used_by_bfd = sdata;
16223 }
e489d0ae
PB		 16224
16225 return _bfd_elf_new_section_hook (abfd, sec);
16226}
16227
16228
16229/* Used to order a list of mapping symbols by address. */
16230
16231static int
16232elf32_arm_compare_mapping (const void * a, const void * b)
16233{
7f6a71ff
JM		 16234 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
16235 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
16236
16237 if (amap->vma > bmap->vma)
16238 return 1;
16239 else if (amap->vma < bmap->vma)
16240 return -1;
16241 else if (amap->type > bmap->type)
16242 /* Ensure results do not depend on the host qsort for objects with
16243 multiple mapping symbols at the same address by sorting on type
16244 after vma. */
16245 return 1;
16246 else if (amap->type < bmap->type)
16247 return -1;
16248 else
16249 return 0;
e489d0ae
PB		 16250}
16251
2468f9c9
PB		 16252/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
16253
16254static unsigned long
16255offset_prel31 (unsigned long addr, bfd_vma offset)
16256{
16257 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
16258}
16259
16260/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
16261 relocations. */
16262
16263static void
16264copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
16265{
16266 unsigned long first_word = bfd_get_32 (output_bfd, from);
16267 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 16268
2468f9c9
PB		 16269 /* High bit of first word is supposed to be zero. */
16270 if ((first_word & 0x80000000ul) == 0)
16271 first_word = offset_prel31 (first_word, offset);
b38cadfb 16272
2468f9c9
PB		 16273 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
16274 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
16275 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
16276 second_word = offset_prel31 (second_word, offset);
b38cadfb 16277
2468f9c9
PB		 16278 bfd_put_32 (output_bfd, first_word, to);
16279 bfd_put_32 (output_bfd, second_word, to + 4);
16280}
e489d0ae 16281
48229727
JB		 16282/* Data for make_branch_to_a8_stub(). */
16283
b38cadfb
NC		 16284struct a8_branch_to_stub_data
16285{
48229727
JB		 16286 asection *writing_section;
16287 bfd_byte *contents;
16288};
16289
16290
16291/* Helper to insert branches to Cortex-A8 erratum stubs in the right
16292 places for a particular section. */
16293
16294static bfd_boolean
16295make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 16296 void *in_arg)
48229727
JB		 16297{
16298 struct elf32_arm_stub_hash_entry *stub_entry;
16299 struct a8_branch_to_stub_data *data;
16300 bfd_byte *contents;
16301 unsigned long branch_insn;
16302 bfd_vma veneered_insn_loc, veneer_entry_loc;
16303 bfd_signed_vma branch_offset;
16304 bfd *abfd;
8d9d9490 16305 unsigned int loc;
48229727
JB		 16306
16307 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
16308 data = (struct a8_branch_to_stub_data *) in_arg;
16309
16310 if (stub_entry->target_section != data->writing_section
4563a860 16311 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 16312 return TRUE;
16313
16314 contents = data->contents;
16315
8d9d9490
TP		 16316 /* We use target_section as Cortex-A8 erratum workaround stubs are only
16317 generated when both source and target are in the same section. */
48229727
JB		 16318 veneered_insn_loc = stub_entry->target_section->output_section->vma
16319 + stub_entry->target_section->output_offset
8d9d9490 16320 + stub_entry->source_value;
48229727
JB		 16321
16322 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
16323 + stub_entry->stub_sec->output_offset
16324 + stub_entry->stub_offset;
16325
16326 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
16327 veneered_insn_loc &= ~3u;
16328
16329 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
16330
16331 abfd = stub_entry->target_section->owner;
8d9d9490 16332 loc = stub_entry->source_value;
48229727
JB		 16333
16334 /* We attempt to avoid this condition by setting stubs_always_after_branch
16335 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
16336 This check is just to be on the safe side... */
16337 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
16338 {
16339 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub is "
16340 "allocated in unsafe location"), abfd);
16341 return FALSE;
16342 }
16343
16344 switch (stub_entry->stub_type)
16345 {
16346 case arm_stub_a8_veneer_b:
16347 case arm_stub_a8_veneer_b_cond:
16348 branch_insn = 0xf0009000;
16349 goto jump24;
16350
16351 case arm_stub_a8_veneer_blx:
16352 branch_insn = 0xf000e800;
16353 goto jump24;
16354
16355 case arm_stub_a8_veneer_bl:
16356 {
16357 unsigned int i1, j1, i2, j2, s;
16358
16359 branch_insn = 0xf000d000;
16360
16361 jump24:
16362 if (branch_offset < -16777216 || branch_offset > 16777214)
16363 {
16364 /* There's not much we can do apart from complain if this
16365 happens. */
16366 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub out "
16367 "of range (input file too large)"), abfd);
16368 return FALSE;
16369 }
16370
16371 /* i1 = not(j1 eor s), so:
16372 not i1 = j1 eor s
16373 j1 = (not i1) eor s. */
16374
16375 branch_insn |= (branch_offset >> 1) & 0x7ff;
16376 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
16377 i2 = (branch_offset >> 22) & 1;
16378 i1 = (branch_offset >> 23) & 1;
16379 s = (branch_offset >> 24) & 1;
16380 j1 = (!i1) ^ s;
16381 j2 = (!i2) ^ s;
16382 branch_insn |= j2 << 11;
16383 branch_insn |= j1 << 13;
16384 branch_insn |= s << 26;
16385 }
16386 break;
16387
16388 default:
16389 BFD_FAIL ();
16390 return FALSE;
16391 }
16392
8d9d9490
TP		 16393 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
16394 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 16395
16396 return TRUE;
16397}
16398
a504d23a
LA		 16399/* Beginning of stm32l4xx work-around. */
16400
16401/* Functions encoding instructions necessary for the emission of the
16402 fix-stm32l4xx-629360.
16403 Encoding is extracted from the
16404 ARM (C) Architecture Reference Manual
16405 ARMv7-A and ARMv7-R edition
16406 ARM DDI 0406C.b (ID072512). */
16407
16408static inline bfd_vma
82188b29 16409create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 16410{
16411 /* A8.8.18 B (A8-334)
16412 B target_address (Encoding T4). */
16413 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
16414 /* jump offset is: S:I1:I2:imm10:imm11:0. */
16415 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
16416
a504d23a
LA		 16417 int s = ((branch_offset & 0x1000000) >> 24);
16418 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
16419 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
16420
16421 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
16422 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
16423
16424 bfd_vma patched_inst = 0xf0009000
16425 | s << 26 /* S. */
16426 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
16427 | j1 << 13 /* J1. */
16428 | j2 << 11 /* J2. */
16429 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
16430
16431 return patched_inst;
16432}
16433
16434static inline bfd_vma
16435create_instruction_ldmia (int base_reg, int wback, int reg_mask)
16436{
16437 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
16438 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
16439 bfd_vma patched_inst = 0xe8900000
16440 | (/*W=*/wback << 21)
16441 | (base_reg << 16)
16442 | (reg_mask & 0x0000ffff);
16443
16444 return patched_inst;
16445}
16446
16447static inline bfd_vma
16448create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
16449{
16450 /* A8.8.60 LDMDB/LDMEA (A8-402)
16451 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
16452 bfd_vma patched_inst = 0xe9100000
16453 | (/*W=*/wback << 21)
16454 | (base_reg << 16)
16455 | (reg_mask & 0x0000ffff);
16456
16457 return patched_inst;
16458}
16459
16460static inline bfd_vma
16461create_instruction_mov (int target_reg, int source_reg)
16462{
16463 /* A8.8.103 MOV (register) (A8-486)
16464 MOV Rd, Rm (Encoding T1). */
16465 bfd_vma patched_inst = 0x4600
16466 | (target_reg & 0x7)
16467 | ((target_reg & 0x8) >> 3) << 7
16468 | (source_reg << 3);
16469
16470 return patched_inst;
16471}
16472
16473static inline bfd_vma
16474create_instruction_sub (int target_reg, int source_reg, int value)
16475{
16476 /* A8.8.221 SUB (immediate) (A8-708)
16477 SUB Rd, Rn, #value (Encoding T3). */
16478 bfd_vma patched_inst = 0xf1a00000
16479 | (target_reg << 8)
16480 | (source_reg << 16)
16481 | (/*S=*/0 << 20)
16482 | ((value & 0x800) >> 11) << 26
16483 | ((value & 0x700) >> 8) << 12
16484 | (value & 0x0ff);
16485
16486 return patched_inst;
16487}
16488
16489static inline bfd_vma
9239bbd3 16490create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 16491 int first_reg)
16492{
16493 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 16494 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
16495 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 16496 | (/*W=*/wback << 21)
16497 | (base_reg << 16)
9239bbd3
CM		 16498 | (num_words & 0x000000ff)
16499 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 16500 | (first_reg & 0x00000001) << 22;
16501
16502 return patched_inst;
16503}
16504
16505static inline bfd_vma
9239bbd3
CM		 16506create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
16507 int first_reg)
a504d23a
LA		 16508{
16509 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 16510 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
16511 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 16512 | (base_reg << 16)
9239bbd3
CM		 16513 | (num_words & 0x000000ff)
16514 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 16515 | (first_reg & 0x00000001) << 22;
16516
16517 return patched_inst;
16518}
16519
16520static inline bfd_vma
16521create_instruction_udf_w (int value)
16522{
16523 /* A8.8.247 UDF (A8-758)
16524 Undefined (Encoding T2). */
16525 bfd_vma patched_inst = 0xf7f0a000
16526 | (value & 0x00000fff)
16527 | (value & 0x000f0000) << 16;
16528
16529 return patched_inst;
16530}
16531
16532static inline bfd_vma
16533create_instruction_udf (int value)
16534{
16535 /* A8.8.247 UDF (A8-758)
16536 Undefined (Encoding T1). */
16537 bfd_vma patched_inst = 0xde00
16538 | (value & 0xff);
16539
16540 return patched_inst;
16541}
16542
16543/* Functions writing an instruction in memory, returning the next
16544 memory position to write to. */
16545
16546static inline bfd_byte *
16547push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
16548 bfd * output_bfd, bfd_byte *pt, insn32 insn)
16549{
16550 put_thumb2_insn (htab, output_bfd, insn, pt);
16551 return pt + 4;
16552}
16553
16554static inline bfd_byte *
16555push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
16556 bfd * output_bfd, bfd_byte *pt, insn32 insn)
16557{
16558 put_thumb_insn (htab, output_bfd, insn, pt);
16559 return pt + 2;
16560}
16561
16562/* Function filling up a region in memory with T1 and T2 UDFs taking
16563 care of alignment. */
16564
16565static bfd_byte *
16566stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
16567 bfd * output_bfd,
16568 const bfd_byte * const base_stub_contents,
16569 bfd_byte * const from_stub_contents,
16570 const bfd_byte * const end_stub_contents)
16571{
16572 bfd_byte *current_stub_contents = from_stub_contents;
16573
16574 /* Fill the remaining of the stub with deterministic contents : UDF
16575 instructions.
16576 Check if realignment is needed on modulo 4 frontier using T1, to
16577 further use T2. */
16578 if ((current_stub_contents < end_stub_contents)
16579 && !((current_stub_contents - base_stub_contents) % 2)
16580 && ((current_stub_contents - base_stub_contents) % 4))
16581 current_stub_contents =
16582 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16583 create_instruction_udf (0));
16584
16585 for (; current_stub_contents < end_stub_contents;)
16586 current_stub_contents =
16587 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16588 create_instruction_udf_w (0));
16589
16590 return current_stub_contents;
16591}
16592
16593/* Functions writing the stream of instructions equivalent to the
16594 derived sequence for ldmia, ldmdb, vldm respectively. */
16595
16596static void
16597stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
16598 bfd * output_bfd,
16599 const insn32 initial_insn,
16600 const bfd_byte *const initial_insn_addr,
16601 bfd_byte *const base_stub_contents)
16602{
16603 int wback = (initial_insn & 0x00200000) >> 21;
16604 int ri, rn = (initial_insn & 0x000F0000) >> 16;
16605 int insn_all_registers = initial_insn & 0x0000ffff;
16606 int insn_low_registers, insn_high_registers;
16607 int usable_register_mask;
16608 int nb_registers = popcount (insn_all_registers);
16609 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
16610 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
16611 bfd_byte *current_stub_contents = base_stub_contents;
16612
16613 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
16614
16615 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16616 smaller than 8 registers load sequences that do not cause the
16617 hardware issue. */
16618 if (nb_registers <= 8)
16619 {
16620 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
16621 current_stub_contents =
16622 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16623 initial_insn);
16624
16625 /* B initial_insn_addr+4. */
16626 if (!restore_pc)
16627 current_stub_contents =
16628 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16629 create_instruction_branch_absolute
82188b29
NC		 16630 (initial_insn_addr - current_stub_contents));
16631
a504d23a
LA		 16632
16633 /* Fill the remaining of the stub with deterministic contents. */
16634 current_stub_contents =
16635 stm32l4xx_fill_stub_udf (htab, output_bfd,
16636 base_stub_contents, current_stub_contents,
16637 base_stub_contents +
16638 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16639
16640 return;
16641 }
16642
16643 /* - reg_list[13] == 0. */
16644 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
16645
16646 /* - reg_list[14] & reg_list[15] != 1. */
16647 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
16648
16649 /* - if (wback==1) reg_list[rn] == 0. */
16650 BFD_ASSERT (!wback || !restore_rn);
16651
16652 /* - nb_registers > 8. */
16653 BFD_ASSERT (popcount (insn_all_registers) > 8);
16654
16655 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
16656
16657 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
16658 - One with the 7 lowest registers (register mask 0x007F)
16659 This LDM will finally contain between 2 and 7 registers
16660 - One with the 7 highest registers (register mask 0xDF80)
16661 This ldm will finally contain between 2 and 7 registers. */
16662 insn_low_registers = insn_all_registers & 0x007F;
16663 insn_high_registers = insn_all_registers & 0xDF80;
16664
16665 /* A spare register may be needed during this veneer to temporarily
16666 handle the base register. This register will be restored with the
16667 last LDM operation.
16668 The usable register may be any general purpose register (that
16669 excludes PC, SP, LR : register mask is 0x1FFF). */
16670 usable_register_mask = 0x1FFF;
16671
16672 /* Generate the stub function. */
16673 if (wback)
16674 {
16675 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
16676 current_stub_contents =
16677 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16678 create_instruction_ldmia
16679 (rn, /*wback=*/1, insn_low_registers));
16680
16681 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
16682 current_stub_contents =
16683 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16684 create_instruction_ldmia
16685 (rn, /*wback=*/1, insn_high_registers));
16686 if (!restore_pc)
16687 {
16688 /* B initial_insn_addr+4. */
16689 current_stub_contents =
16690 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16691 create_instruction_branch_absolute
82188b29 16692 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16693 }
16694 }
16695 else /* if (!wback). */
16696 {
16697 ri = rn;
16698
16699 /* If Rn is not part of the high-register-list, move it there. */
16700 if (!(insn_high_registers & (1 << rn)))
16701 {
16702 /* Choose a Ri in the high-register-list that will be restored. */
16703 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16704
16705 /* MOV Ri, Rn. */
16706 current_stub_contents =
16707 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16708 create_instruction_mov (ri, rn));
16709 }
16710
16711 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
16712 current_stub_contents =
16713 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16714 create_instruction_ldmia
16715 (ri, /*wback=*/1, insn_low_registers));
16716
16717 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
16718 current_stub_contents =
16719 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16720 create_instruction_ldmia
16721 (ri, /*wback=*/0, insn_high_registers));
16722
16723 if (!restore_pc)
16724 {
16725 /* B initial_insn_addr+4. */
16726 current_stub_contents =
16727 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16728 create_instruction_branch_absolute
82188b29 16729 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16730 }
16731 }
16732
16733 /* Fill the remaining of the stub with deterministic contents. */
16734 current_stub_contents =
16735 stm32l4xx_fill_stub_udf (htab, output_bfd,
16736 base_stub_contents, current_stub_contents,
16737 base_stub_contents +
16738 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16739}
16740
16741static void
16742stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
16743 bfd * output_bfd,
16744 const insn32 initial_insn,
16745 const bfd_byte *const initial_insn_addr,
16746 bfd_byte *const base_stub_contents)
16747{
16748 int wback = (initial_insn & 0x00200000) >> 21;
16749 int ri, rn = (initial_insn & 0x000f0000) >> 16;
16750 int insn_all_registers = initial_insn & 0x0000ffff;
16751 int insn_low_registers, insn_high_registers;
16752 int usable_register_mask;
16753 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
16754 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
16755 int nb_registers = popcount (insn_all_registers);
16756 bfd_byte *current_stub_contents = base_stub_contents;
16757
16758 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
16759
16760 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16761 smaller than 8 registers load sequences that do not cause the
16762 hardware issue. */
16763 if (nb_registers <= 8)
16764 {
16765 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
16766 current_stub_contents =
16767 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16768 initial_insn);
16769
16770 /* B initial_insn_addr+4. */
16771 current_stub_contents =
16772 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16773 create_instruction_branch_absolute
82188b29 16774 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16775
16776 /* Fill the remaining of the stub with deterministic contents. */
16777 current_stub_contents =
16778 stm32l4xx_fill_stub_udf (htab, output_bfd,
16779 base_stub_contents, current_stub_contents,
16780 base_stub_contents +
16781 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16782
16783 return;
16784 }
16785
16786 /* - reg_list[13] == 0. */
16787 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
16788
16789 /* - reg_list[14] & reg_list[15] != 1. */
16790 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
16791
16792 /* - if (wback==1) reg_list[rn] == 0. */
16793 BFD_ASSERT (!wback || !restore_rn);
16794
16795 /* - nb_registers > 8. */
16796 BFD_ASSERT (popcount (insn_all_registers) > 8);
16797
16798 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
16799
16800 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
16801 - One with the 7 lowest registers (register mask 0x007F)
16802 This LDM will finally contain between 2 and 7 registers
16803 - One with the 7 highest registers (register mask 0xDF80)
16804 This ldm will finally contain between 2 and 7 registers. */
16805 insn_low_registers = insn_all_registers & 0x007F;
16806 insn_high_registers = insn_all_registers & 0xDF80;
16807
16808 /* A spare register may be needed during this veneer to temporarily
16809 handle the base register. This register will be restored with
16810 the last LDM operation.
16811 The usable register may be any general purpose register (that excludes
16812 PC, SP, LR : register mask is 0x1FFF). */
16813 usable_register_mask = 0x1FFF;
16814
16815 /* Generate the stub function. */
16816 if (!wback && !restore_pc && !restore_rn)
16817 {
16818 /* Choose a Ri in the low-register-list that will be restored. */
16819 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
16820
16821 /* MOV Ri, Rn. */
16822 current_stub_contents =
16823 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16824 create_instruction_mov (ri, rn));
16825
16826 /* LDMDB Ri!, {R-high-register-list}. */
16827 current_stub_contents =
16828 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16829 create_instruction_ldmdb
16830 (ri, /*wback=*/1, insn_high_registers));
16831
16832 /* LDMDB Ri, {R-low-register-list}. */
16833 current_stub_contents =
16834 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16835 create_instruction_ldmdb
16836 (ri, /*wback=*/0, insn_low_registers));
16837
16838 /* B initial_insn_addr+4. */
16839 current_stub_contents =
16840 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16841 create_instruction_branch_absolute
82188b29 16842 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16843 }
16844 else if (wback && !restore_pc && !restore_rn)
16845 {
16846 /* LDMDB Rn!, {R-high-register-list}. */
16847 current_stub_contents =
16848 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16849 create_instruction_ldmdb
16850 (rn, /*wback=*/1, insn_high_registers));
16851
16852 /* LDMDB Rn!, {R-low-register-list}. */
16853 current_stub_contents =
16854 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16855 create_instruction_ldmdb
16856 (rn, /*wback=*/1, insn_low_registers));
16857
16858 /* B initial_insn_addr+4. */
16859 current_stub_contents =
16860 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16861 create_instruction_branch_absolute
82188b29 16862 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16863 }
16864 else if (!wback && restore_pc && !restore_rn)
16865 {
16866 /* Choose a Ri in the high-register-list that will be restored. */
16867 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16868
16869 /* SUB Ri, Rn, #(4*nb_registers). */
16870 current_stub_contents =
16871 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16872 create_instruction_sub (ri, rn, (4 * nb_registers)));
16873
16874 /* LDMIA Ri!, {R-low-register-list}. */
16875 current_stub_contents =
16876 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16877 create_instruction_ldmia
16878 (ri, /*wback=*/1, insn_low_registers));
16879
16880 /* LDMIA Ri, {R-high-register-list}. */
16881 current_stub_contents =
16882 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16883 create_instruction_ldmia
16884 (ri, /*wback=*/0, insn_high_registers));
16885 }
16886 else if (wback && restore_pc && !restore_rn)
16887 {
16888 /* Choose a Ri in the high-register-list that will be restored. */
16889 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16890
16891 /* SUB Rn, Rn, #(4*nb_registers) */
16892 current_stub_contents =
16893 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16894 create_instruction_sub (rn, rn, (4 * nb_registers)));
16895
16896 /* MOV Ri, Rn. */
16897 current_stub_contents =
16898 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16899 create_instruction_mov (ri, rn));
16900
16901 /* LDMIA Ri!, {R-low-register-list}. */
16902 current_stub_contents =
16903 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16904 create_instruction_ldmia
16905 (ri, /*wback=*/1, insn_low_registers));
16906
16907 /* LDMIA Ri, {R-high-register-list}. */
16908 current_stub_contents =
16909 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16910 create_instruction_ldmia
16911 (ri, /*wback=*/0, insn_high_registers));
16912 }
16913 else if (!wback && !restore_pc && restore_rn)
16914 {
16915 ri = rn;
16916 if (!(insn_low_registers & (1 << rn)))
16917 {
16918 /* Choose a Ri in the low-register-list that will be restored. */
16919 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
16920
16921 /* MOV Ri, Rn. */
16922 current_stub_contents =
16923 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16924 create_instruction_mov (ri, rn));
16925 }
16926
16927 /* LDMDB Ri!, {R-high-register-list}. */
16928 current_stub_contents =
16929 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16930 create_instruction_ldmdb
16931 (ri, /*wback=*/1, insn_high_registers));
16932
16933 /* LDMDB Ri, {R-low-register-list}. */
16934 current_stub_contents =
16935 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16936 create_instruction_ldmdb
16937 (ri, /*wback=*/0, insn_low_registers));
16938
16939 /* B initial_insn_addr+4. */
16940 current_stub_contents =
16941 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16942 create_instruction_branch_absolute
82188b29 16943 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16944 }
16945 else if (!wback && restore_pc && restore_rn)
16946 {
16947 ri = rn;
16948 if (!(insn_high_registers & (1 << rn)))
16949 {
16950 /* Choose a Ri in the high-register-list that will be restored. */
16951 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16952 }
16953
16954 /* SUB Ri, Rn, #(4*nb_registers). */
16955 current_stub_contents =
16956 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16957 create_instruction_sub (ri, rn, (4 * nb_registers)));
16958
16959 /* LDMIA Ri!, {R-low-register-list}. */
16960 current_stub_contents =
16961 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16962 create_instruction_ldmia
16963 (ri, /*wback=*/1, insn_low_registers));
16964
16965 /* LDMIA Ri, {R-high-register-list}. */
16966 current_stub_contents =
16967 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16968 create_instruction_ldmia
16969 (ri, /*wback=*/0, insn_high_registers));
16970 }
16971 else if (wback && restore_rn)
16972 {
16973 /* The assembler should not have accepted to encode this. */
16974 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
16975 "undefined behavior.\n");
16976 }
16977
16978 /* Fill the remaining of the stub with deterministic contents. */
16979 current_stub_contents =
16980 stm32l4xx_fill_stub_udf (htab, output_bfd,
16981 base_stub_contents, current_stub_contents,
16982 base_stub_contents +
16983 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16984
16985}
16986
16987static void
16988stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
16989 bfd * output_bfd,
16990 const insn32 initial_insn,
16991 const bfd_byte *const initial_insn_addr,
16992 bfd_byte *const base_stub_contents)
16993{
9239bbd3 16994 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 16995 bfd_byte *current_stub_contents = base_stub_contents;
16996
16997 BFD_ASSERT (is_thumb2_vldm (initial_insn));
16998
16999 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 17000 smaller than 8 words load sequences that do not cause the
a504d23a 17001 hardware issue. */
9239bbd3 17002 if (num_words <= 8)
a504d23a
LA		 17003 {
17004 /* Untouched instruction. */
17005 current_stub_contents =
17006 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17007 initial_insn);
17008
17009 /* B initial_insn_addr+4. */
17010 current_stub_contents =
17011 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17012 create_instruction_branch_absolute
82188b29 17013 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17014 }
17015 else
17016 {
9239bbd3
CM		 17017 bfd_boolean is_dp = /* DP encoding. */
17018 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 17019 bfd_boolean is_ia_nobang = /* (IA without !). */
17020 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
17021 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
17022 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
17023 bfd_boolean is_db_bang = /* (DB with !). */
17024 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 17025 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 17026 /* d = UInt (Vd:D);. */
9239bbd3 17027 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 17028 | (((unsigned int)initial_insn << 9) >> 31);
17029
9239bbd3
CM		 17030 /* Compute the number of 8-words chunks needed to split. */
17031 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 17032 int chunk;
17033
17034 /* The test coverage has been done assuming the following
17035 hypothesis that exactly one of the previous is_ predicates is
17036 true. */
9239bbd3
CM		 17037 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
17038 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 17039
9239bbd3 17040 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 17041 cases, then we emit the adjustments:
17042
17043 vldm rx, {...}
17044 -> vldm rx!, {8_words_or_less} for each needed 8_word
17045 -> sub rx, rx, #size (list)
17046
17047 vldm rx!, {...}
17048 -> vldm rx!, {8_words_or_less} for each needed 8_word
17049 This also handles vpop instruction (when rx is sp)
17050
17051 vldmd rx!, {...}
17052 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 17053 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 17054 {
9239bbd3
CM		 17055 bfd_vma new_insn = 0;
17056
a504d23a
LA		 17057 if (is_ia_nobang || is_ia_bang)
17058 {
9239bbd3
CM		 17059 new_insn = create_instruction_vldmia
17060 (base_reg,
17061 is_dp,
17062 /*wback= . */1,
17063 chunks - (chunk + 1) ?
17064 8 : num_words - chunk * 8,
17065 first_reg + chunk * 8);
a504d23a
LA		 17066 }
17067 else if (is_db_bang)
17068 {
9239bbd3
CM		 17069 new_insn = create_instruction_vldmdb
17070 (base_reg,
17071 is_dp,
17072 chunks - (chunk + 1) ?
17073 8 : num_words - chunk * 8,
17074 first_reg + chunk * 8);
a504d23a 17075 }
9239bbd3
CM		 17076
17077 if (new_insn)
17078 current_stub_contents =
17079 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17080 new_insn);
a504d23a
LA		 17081 }
17082
17083 /* Only this case requires the base register compensation
17084 subtract. */
17085 if (is_ia_nobang)
17086 {
17087 current_stub_contents =
17088 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17089 create_instruction_sub
9239bbd3 17090 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 17091 }
17092
17093 /* B initial_insn_addr+4. */
17094 current_stub_contents =
17095 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17096 create_instruction_branch_absolute
82188b29 17097 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17098 }
17099
17100 /* Fill the remaining of the stub with deterministic contents. */
17101 current_stub_contents =
17102 stm32l4xx_fill_stub_udf (htab, output_bfd,
17103 base_stub_contents, current_stub_contents,
17104 base_stub_contents +
17105 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
17106}
17107
17108static void
17109stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
17110 bfd * output_bfd,
17111 const insn32 wrong_insn,
17112 const bfd_byte *const wrong_insn_addr,
17113 bfd_byte *const stub_contents)
17114{
17115 if (is_thumb2_ldmia (wrong_insn))
17116 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
17117 wrong_insn, wrong_insn_addr,
17118 stub_contents);
17119 else if (is_thumb2_ldmdb (wrong_insn))
17120 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
17121 wrong_insn, wrong_insn_addr,
17122 stub_contents);
17123 else if (is_thumb2_vldm (wrong_insn))
17124 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
17125 wrong_insn, wrong_insn_addr,
17126 stub_contents);
17127}
17128
17129/* End of stm32l4xx work-around. */
17130
17131
491d01d3
YU		 17132static void
17133elf32_arm_add_relocation (bfd *output_bfd, struct bfd_link_info *info,
17134 asection *output_sec, Elf_Internal_Rela *rel)
17135{
17136 BFD_ASSERT (output_sec && rel);
17137 struct bfd_elf_section_reloc_data *output_reldata;
17138 struct elf32_arm_link_hash_table *htab;
17139 struct bfd_elf_section_data *oesd = elf_section_data (output_sec);
17140 Elf_Internal_Shdr *rel_hdr;
17141
17142
17143 if (oesd->rel.hdr)
17144 {
17145 rel_hdr = oesd->rel.hdr;
17146 output_reldata = &(oesd->rel);
17147 }
17148 else if (oesd->rela.hdr)
17149 {
17150 rel_hdr = oesd->rela.hdr;
17151 output_reldata = &(oesd->rela);
17152 }
17153 else
17154 {
17155 abort ();
17156 }
17157
17158 bfd_byte *erel = rel_hdr->contents;
17159 erel += output_reldata->count * rel_hdr->sh_entsize;
17160 htab = elf32_arm_hash_table (info);
17161 SWAP_RELOC_OUT (htab) (output_bfd, rel, erel);
17162 output_reldata->count++;
17163}
17164
e489d0ae
PB		 17165/* Do code byteswapping. Return FALSE afterwards so that the section is
17166 written out as normal. */
17167
17168static bfd_boolean
c7b8f16e 17169elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 17170 struct bfd_link_info *link_info,
17171 asection *sec,
e489d0ae
PB		 17172 bfd_byte *contents)
17173{
48229727 17174 unsigned int mapcount, errcount;
8e3de13a 17175 _arm_elf_section_data *arm_data;
c7b8f16e 17176 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 17177 elf32_arm_section_map *map;
c7b8f16e 17178 elf32_vfp11_erratum_list *errnode;
a504d23a 17179 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 17180 bfd_vma ptr;
17181 bfd_vma end;
c7b8f16e 17182 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 17183 bfd_byte tmp;
48229727 17184 unsigned int i;
57e8b36a 17185
4dfe6ac6
NC		 17186 if (globals == NULL)
17187 return FALSE;
17188
8e3de13a
NC		 17189 /* If this section has not been allocated an _arm_elf_section_data
17190 structure then we cannot record anything. */
17191 arm_data = get_arm_elf_section_data (sec);
17192 if (arm_data == NULL)
17193 return FALSE;
17194
17195 mapcount = arm_data->mapcount;
17196 map = arm_data->map;
c7b8f16e
JB		 17197 errcount = arm_data->erratumcount;
17198
17199 if (errcount != 0)
17200 {
17201 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
17202
17203 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 17204 errnode = errnode->next)
17205 {
17206 bfd_vma target = errnode->vma - offset;
17207
17208 switch (errnode->type)
17209 {
17210 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
17211 {
17212 bfd_vma branch_to_veneer;
17213 /* Original condition code of instruction, plus bit mask for
17214 ARM B instruction. */
17215 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
17216 | 0x0a000000;
c7b8f16e
JB		 17217
17218 /* The instruction is before the label. */
91d6fa6a 17219 target -= 4;
c7b8f16e
JB		 17220
17221 /* Above offset included in -4 below. */
17222 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 17223 - errnode->vma - 4;
c7b8f16e
JB		 17224
17225 if ((signed) branch_to_veneer < -(1 << 25)
17226 || (signed) branch_to_veneer >= (1 << 25))
17227 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
17228 "range"), output_bfd);
17229
99059e56
RM		 17230 insn |= (branch_to_veneer >> 2) & 0xffffff;
17231 contents[endianflip ^ target] = insn & 0xff;
17232 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
17233 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
17234 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
17235 }
17236 break;
c7b8f16e
JB		 17237
17238 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 17239 {
17240 bfd_vma branch_from_veneer;
17241 unsigned int insn;
c7b8f16e 17242
99059e56
RM		 17243 /* Take size of veneer into account. */
17244 branch_from_veneer = errnode->u.v.branch->vma
17245 - errnode->vma - 12;
c7b8f16e
JB		 17246
17247 if ((signed) branch_from_veneer < -(1 << 25)
17248 || (signed) branch_from_veneer >= (1 << 25))
17249 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
17250 "range"), output_bfd);
17251
99059e56
RM		 17252 /* Original instruction. */
17253 insn = errnode->u.v.branch->u.b.vfp_insn;
17254 contents[endianflip ^ target] = insn & 0xff;
17255 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
17256 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
17257 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
17258
17259 /* Branch back to insn after original insn. */
17260 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
17261 contents[endianflip ^ (target + 4)] = insn & 0xff;
17262 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
17263 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
17264 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
17265 }
17266 break;
c7b8f16e 17267
99059e56
RM		 17268 default:
17269 abort ();
17270 }
17271 }
c7b8f16e 17272 }
e489d0ae 17273
a504d23a
LA		 17274 if (arm_data->stm32l4xx_erratumcount != 0)
17275 {
17276 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
17277 stm32l4xx_errnode != 0;
17278 stm32l4xx_errnode = stm32l4xx_errnode->next)
17279 {
17280 bfd_vma target = stm32l4xx_errnode->vma - offset;
17281
17282 switch (stm32l4xx_errnode->type)
17283 {
17284 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
17285 {
17286 unsigned int insn;
17287 bfd_vma branch_to_veneer =
17288 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
17289
17290 if ((signed) branch_to_veneer < -(1 << 24)
17291 || (signed) branch_to_veneer >= (1 << 24))
17292 {
17293 bfd_vma out_of_range =
17294 ((signed) branch_to_veneer < -(1 << 24)) ?
17295 - branch_to_veneer - (1 << 24) :
17296 ((signed) branch_to_veneer >= (1 << 24)) ?
17297 branch_to_veneer - (1 << 24) : 0;
17298
17299 (*_bfd_error_handler)
17300 (_("%B(%#x): error: Cannot create STM32L4XX veneer. "
eee926f2 17301 "Jump out of range by %ld bytes. "
a504d23a
LA		 17302 "Cannot encode branch instruction. "),
17303 output_bfd,
eee926f2 17304 (long) (stm32l4xx_errnode->vma - 4),
a504d23a
LA		 17305 out_of_range);
17306 continue;
17307 }
17308
17309 insn = create_instruction_branch_absolute
82188b29 17310 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 17311
17312 /* The instruction is before the label. */
17313 target -= 4;
17314
17315 put_thumb2_insn (globals, output_bfd,
17316 (bfd_vma) insn, contents + target);
17317 }
17318 break;
17319
17320 case STM32L4XX_ERRATUM_VENEER:
17321 {
82188b29
NC		 17322 bfd_byte * veneer;
17323 bfd_byte * veneer_r;
a504d23a
LA		 17324 unsigned int insn;
17325
82188b29
NC		 17326 veneer = contents + target;
17327 veneer_r = veneer
17328 + stm32l4xx_errnode->u.b.veneer->vma
17329 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 17330
17331 if ((signed) (veneer_r - veneer -
17332 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
17333 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
17334 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
17335 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
17336 || (signed) (veneer_r - veneer) >= (1 << 24))
17337 {
17338 (*_bfd_error_handler) (_("%B: error: Cannot create STM32L4XX "
17339 "veneer."), output_bfd);
17340 continue;
17341 }
17342
17343 /* Original instruction. */
17344 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
17345
17346 stm32l4xx_create_replacing_stub
17347 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
17348 }
17349 break;
17350
17351 default:
17352 abort ();
17353 }
17354 }
17355 }
17356
2468f9c9
PB		 17357 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
17358 {
17359 arm_unwind_table_edit *edit_node
99059e56 17360 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 17361 /* Now, sec->size is the size of the section we will write. The original
99059e56 17362 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 17363 markers) was sec->rawsize. (This isn't the case if we perform no
17364 edits, then rawsize will be zero and we should use size). */
21d799b5 17365 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 17366 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
17367 unsigned int in_index, out_index;
17368 bfd_vma add_to_offsets = 0;
17369
17370 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 17371 {
2468f9c9
PB		 17372 if (edit_node)
17373 {
17374 unsigned int edit_index = edit_node->index;
b38cadfb 17375
2468f9c9 17376 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 17377 {
2468f9c9
PB		 17378 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
17379 contents + in_index * 8, add_to_offsets);
17380 out_index++;
17381 in_index++;
17382 }
17383 else if (in_index == edit_index
17384 || (in_index * 8 >= input_size
17385 && edit_index == UINT_MAX))
99059e56 17386 {
2468f9c9
PB		 17387 switch (edit_node->type)
17388 {
17389 case DELETE_EXIDX_ENTRY:
17390 in_index++;
17391 add_to_offsets += 8;
17392 break;
b38cadfb 17393
2468f9c9
PB		 17394 case INSERT_EXIDX_CANTUNWIND_AT_END:
17395 {
99059e56 17396 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 17397 bfd_vma text_offset = text_sec->output_section->vma
17398 + text_sec->output_offset
17399 + text_sec->size;
17400 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 17401 unsigned long prel31_offset;
2468f9c9
PB		 17402
17403 /* Note: this is meant to be equivalent to an
17404 R_ARM_PREL31 relocation. These synthetic
17405 EXIDX_CANTUNWIND markers are not relocated by the
17406 usual BFD method. */
17407 prel31_offset = (text_offset - exidx_offset)
17408 & 0x7ffffffful;
491d01d3
YU		 17409 if (bfd_link_relocatable (link_info))
17410 {
17411 /* Here relocation for new EXIDX_CANTUNWIND is
17412 created, so there is no need to
17413 adjust offset by hand. */
17414 prel31_offset = text_sec->output_offset
17415 + text_sec->size;
17416
17417 /* New relocation entity. */
17418 asection *text_out = text_sec->output_section;
17419 Elf_Internal_Rela rel;
17420 rel.r_addend = 0;
17421 rel.r_offset = exidx_offset;
17422 rel.r_info = ELF32_R_INFO (text_out->target_index,
17423 R_ARM_PREL31);
17424
17425 elf32_arm_add_relocation (output_bfd, link_info,
17426 sec->output_section,
17427 &rel);
17428 }
2468f9c9
PB		 17429
17430 /* First address we can't unwind. */
17431 bfd_put_32 (output_bfd, prel31_offset,
17432 &edited_contents[out_index * 8]);
17433
17434 /* Code for EXIDX_CANTUNWIND. */
17435 bfd_put_32 (output_bfd, 0x1,
17436 &edited_contents[out_index * 8 + 4]);
17437
17438 out_index++;
17439 add_to_offsets -= 8;
17440 }
17441 break;
17442 }
b38cadfb 17443
2468f9c9
PB		 17444 edit_node = edit_node->next;
17445 }
17446 }
17447 else
17448 {
17449 /* No more edits, copy remaining entries verbatim. */
17450 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
17451 contents + in_index * 8, add_to_offsets);
17452 out_index++;
17453 in_index++;
17454 }
17455 }
17456
17457 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
17458 bfd_set_section_contents (output_bfd, sec->output_section,
17459 edited_contents,
17460 (file_ptr) sec->output_offset, sec->size);
17461
17462 return TRUE;
17463 }
17464
48229727
JB		 17465 /* Fix code to point to Cortex-A8 erratum stubs. */
17466 if (globals->fix_cortex_a8)
17467 {
17468 struct a8_branch_to_stub_data data;
17469
17470 data.writing_section = sec;
17471 data.contents = contents;
17472
a504d23a
LA		 17473 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
17474 & data);
48229727
JB		 17475 }
17476
e489d0ae
PB		 17477 if (mapcount == 0)
17478 return FALSE;
17479
c7b8f16e 17480 if (globals->byteswap_code)
e489d0ae 17481 {
c7b8f16e 17482 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 17483
c7b8f16e
JB		 17484 ptr = map[0].vma;
17485 for (i = 0; i < mapcount; i++)
99059e56
RM		 17486 {
17487 if (i == mapcount - 1)
c7b8f16e 17488 end = sec->size;
99059e56
RM		 17489 else
17490 end = map[i + 1].vma;
e489d0ae 17491
99059e56 17492 switch (map[i].type)
e489d0ae 17493 {
c7b8f16e
JB		 17494 case 'a':
17495 /* Byte swap code words. */
17496 while (ptr + 3 < end)
99059e56
RM		 17497 {
17498 tmp = contents[ptr];
17499 contents[ptr] = contents[ptr + 3];
17500 contents[ptr + 3] = tmp;
17501 tmp = contents[ptr + 1];
17502 contents[ptr + 1] = contents[ptr + 2];
17503 contents[ptr + 2] = tmp;
17504 ptr += 4;
17505 }
c7b8f16e 17506 break;
e489d0ae 17507
c7b8f16e
JB		 17508 case 't':
17509 /* Byte swap code halfwords. */
17510 while (ptr + 1 < end)
99059e56
RM		 17511 {
17512 tmp = contents[ptr];
17513 contents[ptr] = contents[ptr + 1];
17514 contents[ptr + 1] = tmp;
17515 ptr += 2;
17516 }
c7b8f16e
JB		 17517 break;
17518
17519 case 'd':
17520 /* Leave data alone. */
17521 break;
17522 }
99059e56
RM		 17523 ptr = end;
17524 }
e489d0ae 17525 }
8e3de13a 17526
93204d3a 17527 free (map);
47b2e99c 17528 arm_data->mapcount = -1;
c7b8f16e 17529 arm_data->mapsize = 0;
8e3de13a 17530 arm_data->map = NULL;
8e3de13a 17531
e489d0ae
PB		 17532 return FALSE;
17533}
17534
0beaef2b
PB		 17535/* Mangle thumb function symbols as we read them in. */
17536
8384fb8f 17537static bfd_boolean
0beaef2b
PB		 17538elf32_arm_swap_symbol_in (bfd * abfd,
17539 const void *psrc,
17540 const void *pshn,
17541 Elf_Internal_Sym *dst)
17542{
8384fb8f
AM		 17543 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
17544 return FALSE;
0beaef2b
PB		 17545
17546 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 17547 the address. */
63e1a0fc
PB		 17548 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
17549 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 17550 {
63e1a0fc
PB		 17551 if (dst->st_value & 1)
17552 {
17553 dst->st_value &= ~(bfd_vma) 1;
17554 dst->st_target_internal = ST_BRANCH_TO_THUMB;
17555 }
17556 else
17557 dst->st_target_internal = ST_BRANCH_TO_ARM;
35fc36a8
RS		 17558 }
17559 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
17560 {
17561 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
17562 dst->st_target_internal = ST_BRANCH_TO_THUMB;
0beaef2b 17563 }
35fc36a8
RS		 17564 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
17565 dst->st_target_internal = ST_BRANCH_LONG;
17566 else
63e1a0fc 17567 dst->st_target_internal = ST_BRANCH_UNKNOWN;
35fc36a8 17568
8384fb8f 17569 return TRUE;
0beaef2b
PB		 17570}
17571
17572
17573/* Mangle thumb function symbols as we write them out. */
17574
17575static void
17576elf32_arm_swap_symbol_out (bfd *abfd,
17577 const Elf_Internal_Sym *src,
17578 void *cdst,
17579 void *shndx)
17580{
17581 Elf_Internal_Sym newsym;
17582
17583 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
17584 of the address set, as per the new EABI. We do this unconditionally
17585 because objcopy does not set the elf header flags until after
17586 it writes out the symbol table. */
35fc36a8 17587 if (src->st_target_internal == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 17588 {
17589 newsym = *src;
34e77a92
RS		 17590 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
17591 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 17592 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 17593 {
17594 /* Do this only for defined symbols. At link type, the static
17595 linker will simulate the work of dynamic linker of resolving
17596 symbols and will carry over the thumbness of found symbols to
17597 the output symbol table. It's not clear how it happens, but
17598 the thumbness of undefined symbols can well be different at
17599 runtime, and writing '1' for them will be confusing for users
17600 and possibly for dynamic linker itself.
17601 */
17602 newsym.st_value |= 1;
17603 }
906e58ca 17604
0beaef2b
PB		 17605 src = &newsym;
17606 }
17607 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
17608}
17609
b294bdf8
MM		 17610/* Add the PT_ARM_EXIDX program header. */
17611
17612static bfd_boolean
906e58ca 17613elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 17614 struct bfd_link_info *info ATTRIBUTE_UNUSED)
17615{
17616 struct elf_segment_map *m;
17617 asection *sec;
17618
17619 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
17620 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
17621 {
17622 /* If there is already a PT_ARM_EXIDX header, then we do not
17623 want to add another one. This situation arises when running
17624 "strip"; the input binary already has the header. */
12bd6957 17625 m = elf_seg_map (abfd);
b294bdf8
MM		 17626 while (m && m->p_type != PT_ARM_EXIDX)
17627 m = m->next;
17628 if (!m)
17629 {
21d799b5 17630 m = (struct elf_segment_map *)
99059e56 17631 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 17632 if (m == NULL)
17633 return FALSE;
17634 m->p_type = PT_ARM_EXIDX;
17635 m->count = 1;
17636 m->sections[0] = sec;
17637
12bd6957
AM		 17638 m->next = elf_seg_map (abfd);
17639 elf_seg_map (abfd) = m;
b294bdf8
MM		 17640 }
17641 }
17642
17643 return TRUE;
17644}
17645
17646/* We may add a PT_ARM_EXIDX program header. */
17647
17648static int
a6b96beb
AM		 17649elf32_arm_additional_program_headers (bfd *abfd,
17650 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 17651{
17652 asection *sec;
17653
17654 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
17655 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
17656 return 1;
17657 else
17658 return 0;
17659}
17660
34e77a92
RS		 17661/* Hook called by the linker routine which adds symbols from an object
17662 file. */
17663
17664static bfd_boolean
17665elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
17666 Elf_Internal_Sym *sym, const char **namep,
17667 flagword *flagsp, asection **secp, bfd_vma *valp)
17668{
f1885d1e
AM		 17669 if ((ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
17670 || ELF_ST_BIND (sym->st_info) == STB_GNU_UNIQUE)
17671 && (abfd->flags & DYNAMIC) == 0
17672 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
13a2df29 17673 elf_tdata (info->output_bfd)->has_gnu_symbols = elf_gnu_symbol_any;
34e77a92 17674
c792917c
NC		 17675 if (elf32_arm_hash_table (info) == NULL)
17676 return FALSE;
17677
34e77a92
RS		 17678 if (elf32_arm_hash_table (info)->vxworks_p
17679 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
17680 flagsp, secp, valp))
17681 return FALSE;
17682
17683 return TRUE;
17684}
17685
0beaef2b 17686/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 17687const struct elf_size_info elf32_arm_size_info =
17688{
0beaef2b
PB		 17689 sizeof (Elf32_External_Ehdr),
17690 sizeof (Elf32_External_Phdr),
17691 sizeof (Elf32_External_Shdr),
17692 sizeof (Elf32_External_Rel),
17693 sizeof (Elf32_External_Rela),
17694 sizeof (Elf32_External_Sym),
17695 sizeof (Elf32_External_Dyn),
17696 sizeof (Elf_External_Note),
17697 4,
17698 1,
17699 32, 2,
17700 ELFCLASS32, EV_CURRENT,
17701 bfd_elf32_write_out_phdrs,
17702 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 17703 bfd_elf32_checksum_contents,
0beaef2b
PB		 17704 bfd_elf32_write_relocs,
17705 elf32_arm_swap_symbol_in,
17706 elf32_arm_swap_symbol_out,
17707 bfd_elf32_slurp_reloc_table,
17708 bfd_elf32_slurp_symbol_table,
17709 bfd_elf32_swap_dyn_in,
17710 bfd_elf32_swap_dyn_out,
17711 bfd_elf32_swap_reloc_in,
17712 bfd_elf32_swap_reloc_out,
17713 bfd_elf32_swap_reloca_in,
17714 bfd_elf32_swap_reloca_out
17715};
17716
685e70ae
VK		 17717static bfd_vma
17718read_code32 (const bfd *abfd, const bfd_byte *addr)
17719{
17720 /* V7 BE8 code is always little endian. */
17721 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
17722 return bfd_getl32 (addr);
17723
17724 return bfd_get_32 (abfd, addr);
17725}
17726
17727static bfd_vma
17728read_code16 (const bfd *abfd, const bfd_byte *addr)
17729{
17730 /* V7 BE8 code is always little endian. */
17731 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
17732 return bfd_getl16 (addr);
17733
17734 return bfd_get_16 (abfd, addr);
17735}
17736
6a631e86
YG		 17737/* Return size of plt0 entry starting at ADDR
17738 or (bfd_vma) -1 if size can not be determined. */
17739
17740static bfd_vma
17741elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
17742{
17743 bfd_vma first_word;
17744 bfd_vma plt0_size;
17745
685e70ae 17746 first_word = read_code32 (abfd, addr);
6a631e86
YG		 17747
17748 if (first_word == elf32_arm_plt0_entry[0])
17749 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
17750 else if (first_word == elf32_thumb2_plt0_entry[0])
17751 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
17752 else
17753 /* We don't yet handle this PLT format. */
17754 return (bfd_vma) -1;
17755
17756 return plt0_size;
17757}
17758
17759/* Return size of plt entry starting at offset OFFSET
17760 of plt section located at address START
17761 or (bfd_vma) -1 if size can not be determined. */
17762
17763static bfd_vma
17764elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
17765{
17766 bfd_vma first_insn;
17767 bfd_vma plt_size = 0;
17768 const bfd_byte *addr = start + offset;
17769
17770 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 17771 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 17772 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
17773
17774 /* Respect Thumb stub if necessary. */
685e70ae 17775 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 17776 {
17777 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
17778 }
17779
17780 /* Strip immediate from first add. */
685e70ae 17781 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 17782
17783#ifdef FOUR_WORD_PLT
17784 if (first_insn == elf32_arm_plt_entry[0])
17785 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
17786#else
17787 if (first_insn == elf32_arm_plt_entry_long[0])
17788 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
17789 else if (first_insn == elf32_arm_plt_entry_short[0])
17790 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
17791#endif
17792 else
17793 /* We don't yet handle this PLT format. */
17794 return (bfd_vma) -1;
17795
17796 return plt_size;
17797}
17798
17799/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
17800
17801static long
17802elf32_arm_get_synthetic_symtab (bfd *abfd,
17803 long symcount ATTRIBUTE_UNUSED,
17804 asymbol **syms ATTRIBUTE_UNUSED,
17805 long dynsymcount,
17806 asymbol **dynsyms,
17807 asymbol **ret)
17808{
17809 asection *relplt;
17810 asymbol *s;
17811 arelent *p;
17812 long count, i, n;
17813 size_t size;
17814 Elf_Internal_Shdr *hdr;
17815 char *names;
17816 asection *plt;
17817 bfd_vma offset;
17818 bfd_byte *data;
17819
17820 *ret = NULL;
17821
17822 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
17823 return 0;
17824
17825 if (dynsymcount <= 0)
17826 return 0;
17827
17828 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
17829 if (relplt == NULL)
17830 return 0;
17831
17832 hdr = &elf_section_data (relplt)->this_hdr;
17833 if (hdr->sh_link != elf_dynsymtab (abfd)
17834 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
17835 return 0;
17836
17837 plt = bfd_get_section_by_name (abfd, ".plt");
17838 if (plt == NULL)
17839 return 0;
17840
17841 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
17842 return -1;
17843
17844 data = plt->contents;
17845 if (data == NULL)
17846 {
17847 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
17848 return -1;
17849 bfd_cache_section_contents((asection *) plt, data);
17850 }
17851
17852 count = relplt->size / hdr->sh_entsize;
17853 size = count * sizeof (asymbol);
17854 p = relplt->relocation;
17855 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
17856 {
17857 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
17858 if (p->addend != 0)
17859 size += sizeof ("+0x") - 1 + 8;
17860 }
17861
17862 s = *ret = (asymbol *) bfd_malloc (size);
17863 if (s == NULL)
17864 return -1;
17865
17866 offset = elf32_arm_plt0_size (abfd, data);
17867 if (offset == (bfd_vma) -1)
17868 return -1;
17869
17870 names = (char *) (s + count);
17871 p = relplt->relocation;
17872 n = 0;
17873 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
17874 {
17875 size_t len;
17876
17877 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
17878 if (plt_size == (bfd_vma) -1)
17879 break;
17880
17881 *s = **p->sym_ptr_ptr;
17882 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
17883 we are defining a symbol, ensure one of them is set. */
17884 if ((s->flags & BSF_LOCAL) == 0)
17885 s->flags |= BSF_GLOBAL;
17886 s->flags |= BSF_SYNTHETIC;
17887 s->section = plt;
17888 s->value = offset;
17889 s->name = names;
17890 s->udata.p = NULL;
17891 len = strlen ((*p->sym_ptr_ptr)->name);
17892 memcpy (names, (*p->sym_ptr_ptr)->name, len);
17893 names += len;
17894 if (p->addend != 0)
17895 {
17896 char buf[30], *a;
17897
17898 memcpy (names, "+0x", sizeof ("+0x") - 1);
17899 names += sizeof ("+0x") - 1;
17900 bfd_sprintf_vma (abfd, buf, p->addend);
17901 for (a = buf; *a == '0'; ++a)
17902 ;
17903 len = strlen (a);
17904 memcpy (names, a, len);
17905 names += len;
17906 }
17907 memcpy (names, "@plt", sizeof ("@plt"));
17908 names += sizeof ("@plt");
17909 ++s, ++n;
17910 offset += plt_size;
17911 }
17912
17913 return n;
17914}
17915
ac4c9b04
MG		 17916static bfd_boolean
17917elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
17918{
17919 if (hdr->sh_flags & SHF_ARM_NOREAD)
17920 *flags |= SEC_ELF_NOREAD;
17921 return TRUE;
17922}
17923
17924static flagword
17925elf32_arm_lookup_section_flags (char *flag_name)
17926{
17927 if (!strcmp (flag_name, "SHF_ARM_NOREAD"))
17928 return SHF_ARM_NOREAD;
17929
17930 return SEC_NO_FLAGS;
17931}
17932
491d01d3
YU		 17933static unsigned int
17934elf32_arm_count_additional_relocs (asection *sec)
17935{
17936 struct _arm_elf_section_data *arm_data;
17937 arm_data = get_arm_elf_section_data (sec);
17938 return arm_data->additional_reloc_count;
17939}
17940
5522f910
NC		 17941/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
17942 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
17943 FALSE otherwise. ISECTION is the best guess matching section from the
17944 input bfd IBFD, but it might be NULL. */
17945
17946static bfd_boolean
17947elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
17948 bfd *obfd ATTRIBUTE_UNUSED,
17949 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
17950 Elf_Internal_Shdr *osection)
17951{
17952 switch (osection->sh_type)
17953 {
17954 case SHT_ARM_EXIDX:
17955 {
17956 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
17957 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
17958 unsigned i = 0;
17959
17960 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
17961 osection->sh_info = 0;
17962
17963 /* The sh_link field must be set to the text section associated with
17964 this index section. Unfortunately the ARM EHABI does not specify
17965 exactly how to determine this association. Our caller does try
17966 to match up OSECTION with its corresponding input section however
17967 so that is a good first guess. */
17968 if (isection != NULL
17969 && osection->bfd_section != NULL
17970 && isection->bfd_section != NULL
17971 && isection->bfd_section->output_section != NULL
17972 && isection->bfd_section->output_section == osection->bfd_section
17973 && iheaders != NULL
17974 && isection->sh_link > 0
17975 && isection->sh_link < elf_numsections (ibfd)
17976 && iheaders[isection->sh_link]->bfd_section != NULL
17977 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
17978 )
17979 {
17980 for (i = elf_numsections (obfd); i-- > 0;)
17981 if (oheaders[i]->bfd_section
17982 == iheaders[isection->sh_link]->bfd_section->output_section)
17983 break;
17984 }
17985
17986 if (i == 0)
17987 {
17988 /* Failing that we have to find a matching section ourselves. If
17989 we had the output section name available we could compare that
17990 with input section names. Unfortunately we don't. So instead
17991 we use a simple heuristic and look for the nearest executable
17992 section before this one. */
17993 for (i = elf_numsections (obfd); i-- > 0;)
17994 if (oheaders[i] == osection)
17995 break;
17996 if (i == 0)
17997 break;
17998
17999 while (i-- > 0)
18000 if (oheaders[i]->sh_type == SHT_PROGBITS
18001 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
18002 == (SHF_ALLOC | SHF_EXECINSTR))
18003 break;
18004 }
18005
18006 if (i)
18007 {
18008 osection->sh_link = i;
18009 /* If the text section was part of a group
18010 then the index section should be too. */
18011 if (oheaders[i]->sh_flags & SHF_GROUP)
18012 osection->sh_flags |= SHF_GROUP;
18013 return TRUE;
18014 }
18015 }
18016 break;
18017
18018 case SHT_ARM_PREEMPTMAP:
18019 osection->sh_flags = SHF_ALLOC;
18020 break;
18021
18022 case SHT_ARM_ATTRIBUTES:
18023 case SHT_ARM_DEBUGOVERLAY:
18024 case SHT_ARM_OVERLAYSECTION:
18025 default:
18026 break;
18027 }
18028
18029 return FALSE;
18030}
18031
18032#undef elf_backend_copy_special_section_fields
18033#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
18034
252b5132 18035#define ELF_ARCH bfd_arch_arm
ae95ffa6 18036#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 18037#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 18038#ifdef __QNXTARGET__
18039#define ELF_MAXPAGESIZE 0x1000
18040#else
7572ca89 18041#define ELF_MAXPAGESIZE 0x10000
d0facd1b 18042#endif
b1342370 18043#define ELF_MINPAGESIZE 0x1000
24718e3b 18044#define ELF_COMMONPAGESIZE 0x1000
252b5132 18045
ba93b8ac
DJ		 18046#define bfd_elf32_mkobject elf32_arm_mkobject
18047
99e4ae17
AJ		 18048#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
18049#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 18050#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
18051#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
18052#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 18053#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 18054#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
252b5132 18055#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
4ab527b0 18056#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 18057#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 18058#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 18059#define bfd_elf32_bfd_final_link elf32_arm_final_link
6a631e86 18060#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132
RH		 18061
18062#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
18063#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 18064#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
252b5132
RH		 18065#define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
18066#define elf_backend_check_relocs elf32_arm_check_relocs
dc810e39 18067#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 18068#define elf_backend_write_section elf32_arm_write_section
252b5132 18069#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
5e681ec4 18070#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 18071#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
18072#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
18073#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 18074#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 18075#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 18076#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 18077#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 18078#define elf_backend_object_p elf32_arm_object_p
40a18ebd
NC		 18079#define elf_backend_fake_sections elf32_arm_fake_sections
18080#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
e16bb312 18081#define elf_backend_final_write_processing elf32_arm_final_write_processing
5e681ec4 18082#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 18083#define elf_backend_size_info elf32_arm_size_info
b294bdf8 18084#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
906e58ca
NC		 18085#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
18086#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
18087#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 18088#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 18089#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
906e58ca
NC		 18090
18091#define elf_backend_can_refcount 1
18092#define elf_backend_can_gc_sections 1
18093#define elf_backend_plt_readonly 1
18094#define elf_backend_want_got_plt 1
18095#define elf_backend_want_plt_sym 0
18096#define elf_backend_may_use_rel_p 1
18097#define elf_backend_may_use_rela_p 0
4e7fd91e 18098#define elf_backend_default_use_rela_p 0
252b5132 18099
04f7c78d 18100#define elf_backend_got_header_size 12
b68a20d6 18101#define elf_backend_extern_protected_data 1
04f7c78d 18102
906e58ca
NC		 18103#undef elf_backend_obj_attrs_vendor
18104#define elf_backend_obj_attrs_vendor "aeabi"
18105#undef elf_backend_obj_attrs_section
18106#define elf_backend_obj_attrs_section ".ARM.attributes"
18107#undef elf_backend_obj_attrs_arg_type
18108#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
18109#undef elf_backend_obj_attrs_section_type
104d59d1 18110#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb
NC		 18111#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
18112#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 18113
ac4c9b04
MG		 18114#undef elf_backend_section_flags
18115#define elf_backend_section_flags elf32_arm_section_flags
18116#undef elf_backend_lookup_section_flags_hook
18117#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
18118
252b5132 18119#include "elf32-target.h"
7f266840 18120
b38cadfb
NC		 18121/* Native Client targets. */
18122
18123#undef TARGET_LITTLE_SYM
6d00b590 18124#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 18125#undef TARGET_LITTLE_NAME
18126#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
18127#undef TARGET_BIG_SYM
6d00b590 18128#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 18129#undef TARGET_BIG_NAME
18130#define TARGET_BIG_NAME "elf32-bigarm-nacl"
18131
18132/* Like elf32_arm_link_hash_table_create -- but overrides
18133 appropriately for NaCl. */
18134
18135static struct bfd_link_hash_table *
18136elf32_arm_nacl_link_hash_table_create (bfd *abfd)
18137{
18138 struct bfd_link_hash_table *ret;
18139
18140 ret = elf32_arm_link_hash_table_create (abfd);
18141 if (ret)
18142 {
18143 struct elf32_arm_link_hash_table *htab
18144 = (struct elf32_arm_link_hash_table *) ret;
18145
18146 htab->nacl_p = 1;
18147
18148 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
18149 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
18150 }
18151 return ret;
18152}
18153
18154/* Since NaCl doesn't use the ARM-specific unwind format, we don't
18155 really need to use elf32_arm_modify_segment_map. But we do it
18156 anyway just to reduce gratuitous differences with the stock ARM backend. */
18157
18158static bfd_boolean
18159elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
18160{
18161 return (elf32_arm_modify_segment_map (abfd, info)
18162 && nacl_modify_segment_map (abfd, info));
18163}
18164
887badb3
RM		 18165static void
18166elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
18167{
18168 elf32_arm_final_write_processing (abfd, linker);
18169 nacl_final_write_processing (abfd, linker);
18170}
18171
6a631e86
YG		 18172static bfd_vma
18173elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
18174 const arelent *rel ATTRIBUTE_UNUSED)
18175{
18176 return plt->vma
18177 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
18178 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
18179}
887badb3 18180
b38cadfb 18181#undef elf32_bed
6a631e86 18182#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 18183#undef bfd_elf32_bfd_link_hash_table_create
18184#define bfd_elf32_bfd_link_hash_table_create \
18185 elf32_arm_nacl_link_hash_table_create
18186#undef elf_backend_plt_alignment
6a631e86 18187#define elf_backend_plt_alignment 4
b38cadfb
NC		 18188#undef elf_backend_modify_segment_map
18189#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
18190#undef elf_backend_modify_program_headers
18191#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 18192#undef elf_backend_final_write_processing
18193#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 18194#undef bfd_elf32_get_synthetic_symtab
18195#undef elf_backend_plt_sym_val
18196#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 18197#undef elf_backend_copy_special_section_fields
b38cadfb 18198
887badb3
RM		 18199#undef ELF_MINPAGESIZE
18200#undef ELF_COMMONPAGESIZE
18201
b38cadfb
NC		 18202
18203#include "elf32-target.h"
18204
18205/* Reset to defaults. */
18206#undef elf_backend_plt_alignment
18207#undef elf_backend_modify_segment_map
18208#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
18209#undef elf_backend_modify_program_headers
887badb3
RM		 18210#undef elf_backend_final_write_processing
18211#define elf_backend_final_write_processing elf32_arm_final_write_processing
18212#undef ELF_MINPAGESIZE
18213#define ELF_MINPAGESIZE 0x1000
18214#undef ELF_COMMONPAGESIZE
18215#define ELF_COMMONPAGESIZE 0x1000
18216
b38cadfb 18217
906e58ca 18218/* VxWorks Targets. */
4e7fd91e 18219
906e58ca 18220#undef TARGET_LITTLE_SYM
6d00b590 18221#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
906e58ca 18222#undef TARGET_LITTLE_NAME
4e7fd91e 18223#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
906e58ca 18224#undef TARGET_BIG_SYM
6d00b590 18225#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
906e58ca 18226#undef TARGET_BIG_NAME
4e7fd91e
PB		 18227#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
18228
18229/* Like elf32_arm_link_hash_table_create -- but overrides
18230 appropriately for VxWorks. */
906e58ca 18231
4e7fd91e
PB		 18232static struct bfd_link_hash_table *
18233elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
18234{
18235 struct bfd_link_hash_table *ret;
18236
18237 ret = elf32_arm_link_hash_table_create (abfd);
18238 if (ret)
18239 {
18240 struct elf32_arm_link_hash_table *htab
00a97672 18241 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 18242 htab->use_rel = 0;
00a97672 18243 htab->vxworks_p = 1;
4e7fd91e
PB		 18244 }
18245 return ret;
906e58ca 18246}
4e7fd91e 18247
00a97672
RS		 18248static void
18249elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
18250{
18251 elf32_arm_final_write_processing (abfd, linker);
18252 elf_vxworks_final_write_processing (abfd, linker);
18253}
18254
906e58ca 18255#undef elf32_bed
4e7fd91e
PB		 18256#define elf32_bed elf32_arm_vxworks_bed
18257
906e58ca
NC		 18258#undef bfd_elf32_bfd_link_hash_table_create
18259#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 18260#undef elf_backend_final_write_processing
18261#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
18262#undef elf_backend_emit_relocs
18263#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 18264
906e58ca 18265#undef elf_backend_may_use_rel_p
00a97672 18266#define elf_backend_may_use_rel_p 0
906e58ca 18267#undef elf_backend_may_use_rela_p
00a97672 18268#define elf_backend_may_use_rela_p 1
906e58ca 18269#undef elf_backend_default_use_rela_p
00a97672 18270#define elf_backend_default_use_rela_p 1
906e58ca 18271#undef elf_backend_want_plt_sym
00a97672 18272#define elf_backend_want_plt_sym 1
906e58ca 18273#undef ELF_MAXPAGESIZE
00a97672 18274#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 18275
18276#include "elf32-target.h"
18277
18278
21d799b5
NC		 18279/* Merge backend specific data from an object file to the output
18280 object file when linking. */
18281
18282static bfd_boolean
18283elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
18284{
18285 flagword out_flags;
18286 flagword in_flags;
18287 bfd_boolean flags_compatible = TRUE;
18288 asection *sec;
18289
cc643b88 18290 /* Check if we have the same endianness. */
21d799b5
NC		 18291 if (! _bfd_generic_verify_endian_match (ibfd, obfd))
18292 return FALSE;
18293
18294 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
18295 return TRUE;
18296
18297 if (!elf32_arm_merge_eabi_attributes (ibfd, obfd))
18298 return FALSE;
18299
18300 /* The input BFD must have had its flags initialised. */
18301 /* The following seems bogus to me -- The flags are initialized in
18302 the assembler but I don't think an elf_flags_init field is
18303 written into the object. */
18304 /* BFD_ASSERT (elf_flags_init (ibfd)); */
18305
18306 in_flags = elf_elfheader (ibfd)->e_flags;
18307 out_flags = elf_elfheader (obfd)->e_flags;
18308
18309 /* In theory there is no reason why we couldn't handle this. However
18310 in practice it isn't even close to working and there is no real
18311 reason to want it. */
18312 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
18313 && !(ibfd->flags & DYNAMIC)
18314 && (in_flags & EF_ARM_BE8))
18315 {
18316 _bfd_error_handler (_("error: %B is already in final BE8 format"),
18317 ibfd);
18318 return FALSE;
18319 }
18320
18321 if (!elf_flags_init (obfd))
18322 {
18323 /* If the input is the default architecture and had the default
18324 flags then do not bother setting the flags for the output
18325 architecture, instead allow future merges to do this. If no
18326 future merges ever set these flags then they will retain their
99059e56
RM		 18327 uninitialised values, which surprise surprise, correspond
18328 to the default values. */
21d799b5
NC		 18329 if (bfd_get_arch_info (ibfd)->the_default
18330 && elf_elfheader (ibfd)->e_flags == 0)
18331 return TRUE;
18332
18333 elf_flags_init (obfd) = TRUE;
18334 elf_elfheader (obfd)->e_flags = in_flags;
18335
18336 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
18337 && bfd_get_arch_info (obfd)->the_default)
18338 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
18339
18340 return TRUE;
18341 }
18342
18343 /* Determine what should happen if the input ARM architecture
18344 does not match the output ARM architecture. */
18345 if (! bfd_arm_merge_machines (ibfd, obfd))
18346 return FALSE;
18347
18348 /* Identical flags must be compatible. */
18349 if (in_flags == out_flags)
18350 return TRUE;
18351
18352 /* Check to see if the input BFD actually contains any sections. If
18353 not, its flags may not have been initialised either, but it
18354 cannot actually cause any incompatiblity. Do not short-circuit
18355 dynamic objects; their section list may be emptied by
18356 elf_link_add_object_symbols.
18357
18358 Also check to see if there are no code sections in the input.
18359 In this case there is no need to check for code specific flags.
18360 XXX - do we need to worry about floating-point format compatability
18361 in data sections ? */
18362 if (!(ibfd->flags & DYNAMIC))
18363 {
18364 bfd_boolean null_input_bfd = TRUE;
18365 bfd_boolean only_data_sections = TRUE;
18366
18367 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
18368 {
18369 /* Ignore synthetic glue sections. */
18370 if (strcmp (sec->name, ".glue_7")
18371 && strcmp (sec->name, ".glue_7t"))
18372 {
18373 if ((bfd_get_section_flags (ibfd, sec)
18374 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
18375 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 18376 only_data_sections = FALSE;
21d799b5
NC		 18377
18378 null_input_bfd = FALSE;
18379 break;
18380 }
18381 }
18382
18383 if (null_input_bfd || only_data_sections)
18384 return TRUE;
18385 }
18386
18387 /* Complain about various flag mismatches. */
18388 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
18389 EF_ARM_EABI_VERSION (out_flags)))
18390 {
18391 _bfd_error_handler
18392 (_("error: Source object %B has EABI version %d, but target %B has EABI version %d"),
18393 ibfd, obfd,
18394 (in_flags & EF_ARM_EABIMASK) >> 24,
18395 (out_flags & EF_ARM_EABIMASK) >> 24);
18396 return FALSE;
18397 }
18398
18399 /* Not sure what needs to be checked for EABI versions >= 1. */
18400 /* VxWorks libraries do not use these flags. */
18401 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
18402 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
18403 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
18404 {
18405 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
18406 {
18407 _bfd_error_handler
18408 (_("error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"),
18409 ibfd, obfd,
18410 in_flags & EF_ARM_APCS_26 ? 26 : 32,
18411 out_flags & EF_ARM_APCS_26 ? 26 : 32);
18412 flags_compatible = FALSE;
18413 }
18414
18415 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
18416 {
18417 if (in_flags & EF_ARM_APCS_FLOAT)
18418 _bfd_error_handler
18419 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
18420 ibfd, obfd);
18421 else
18422 _bfd_error_handler
18423 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
18424 ibfd, obfd);
18425
18426 flags_compatible = FALSE;
18427 }
18428
18429 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
18430 {
18431 if (in_flags & EF_ARM_VFP_FLOAT)
18432 _bfd_error_handler
18433 (_("error: %B uses VFP instructions, whereas %B does not"),
18434 ibfd, obfd);
18435 else
18436 _bfd_error_handler
18437 (_("error: %B uses FPA instructions, whereas %B does not"),
18438 ibfd, obfd);
18439
18440 flags_compatible = FALSE;
18441 }
18442
18443 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
18444 {
18445 if (in_flags & EF_ARM_MAVERICK_FLOAT)
18446 _bfd_error_handler
18447 (_("error: %B uses Maverick instructions, whereas %B does not"),
18448 ibfd, obfd);
18449 else
18450 _bfd_error_handler
18451 (_("error: %B does not use Maverick instructions, whereas %B does"),
18452 ibfd, obfd);
18453
18454 flags_compatible = FALSE;
18455 }
18456
18457#ifdef EF_ARM_SOFT_FLOAT
18458 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
18459 {
18460 /* We can allow interworking between code that is VFP format
18461 layout, and uses either soft float or integer regs for
18462 passing floating point arguments and results. We already
18463 know that the APCS_FLOAT flags match; similarly for VFP
18464 flags. */
18465 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
18466 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
18467 {
18468 if (in_flags & EF_ARM_SOFT_FLOAT)
18469 _bfd_error_handler
18470 (_("error: %B uses software FP, whereas %B uses hardware FP"),
18471 ibfd, obfd);
18472 else
18473 _bfd_error_handler
18474 (_("error: %B uses hardware FP, whereas %B uses software FP"),
18475 ibfd, obfd);
18476
18477 flags_compatible = FALSE;
18478 }
18479 }
18480#endif
18481
18482 /* Interworking mismatch is only a warning. */
18483 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
18484 {
18485 if (in_flags & EF_ARM_INTERWORK)
18486 {
18487 _bfd_error_handler
18488 (_("Warning: %B supports interworking, whereas %B does not"),
18489 ibfd, obfd);
18490 }
18491 else
18492 {
18493 _bfd_error_handler
18494 (_("Warning: %B does not support interworking, whereas %B does"),
18495 ibfd, obfd);
18496 }
18497 }
18498 }
18499
18500 return flags_compatible;
18501}
18502
18503
906e58ca 18504/* Symbian OS Targets. */
7f266840 18505
906e58ca 18506#undef TARGET_LITTLE_SYM
6d00b590 18507#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
906e58ca 18508#undef TARGET_LITTLE_NAME
7f266840 18509#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
906e58ca 18510#undef TARGET_BIG_SYM
6d00b590 18511#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
906e58ca 18512#undef TARGET_BIG_NAME
7f266840
DJ		 18513#define TARGET_BIG_NAME "elf32-bigarm-symbian"
18514
18515/* Like elf32_arm_link_hash_table_create -- but overrides
18516 appropriately for Symbian OS. */
906e58ca 18517
7f266840
DJ		 18518static struct bfd_link_hash_table *
18519elf32_arm_symbian_link_hash_table_create (bfd *abfd)
18520{
18521 struct bfd_link_hash_table *ret;
18522
18523 ret = elf32_arm_link_hash_table_create (abfd);
18524 if (ret)
18525 {
18526 struct elf32_arm_link_hash_table *htab
18527 = (struct elf32_arm_link_hash_table *)ret;
18528 /* There is no PLT header for Symbian OS. */
18529 htab->plt_header_size = 0;
95720a86
DJ		 18530 /* The PLT entries are each one instruction and one word. */
18531 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 18532 htab->symbian_p = 1;
33bfe774
JB		 18533 /* Symbian uses armv5t or above, so use_blx is always true. */
18534 htab->use_blx = 1;
67687978 18535 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 18536 }
18537 return ret;
906e58ca 18538}
7f266840 18539
b35d266b 18540static const struct bfd_elf_special_section
551b43fd 18541elf32_arm_symbian_special_sections[] =
7f266840 18542{
5cd3778d
MM		 18543 /* In a BPABI executable, the dynamic linking sections do not go in
18544 the loadable read-only segment. The post-linker may wish to
18545 refer to these sections, but they are not part of the final
18546 program image. */
0112cd26
NC		 18547 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
18548 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
18549 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
18550 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
18551 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 18552 /* These sections do not need to be writable as the SymbianOS
18553 postlinker will arrange things so that no dynamic relocation is
18554 required. */
0112cd26
NC		 18555 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
18556 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
18557 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
18558 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 18559};
18560
c3c76620 18561static void
906e58ca 18562elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 18563 struct bfd_link_info *link_info)
c3c76620
MM		 18564{
18565 /* BPABI objects are never loaded directly by an OS kernel; they are
18566 processed by a postlinker first, into an OS-specific format. If
18567 the D_PAGED bit is set on the file, BFD will align segments on
18568 page boundaries, so that an OS can directly map the file. With
18569 BPABI objects, that just results in wasted space. In addition,
18570 because we clear the D_PAGED bit, map_sections_to_segments will
18571 recognize that the program headers should not be mapped into any
18572 loadable segment. */
18573 abfd->flags &= ~D_PAGED;
906e58ca 18574 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 18575}
7f266840
DJ		 18576
18577static bfd_boolean
906e58ca 18578elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 18579 struct bfd_link_info *info)
7f266840
DJ		 18580{
18581 struct elf_segment_map *m;
18582 asection *dynsec;
18583
7f266840
DJ		 18584 /* BPABI shared libraries and executables should have a PT_DYNAMIC
18585 segment. However, because the .dynamic section is not marked
18586 with SEC_LOAD, the generic ELF code will not create such a
18587 segment. */
18588 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
18589 if (dynsec)
18590 {
12bd6957 18591 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 18592 if (m->p_type == PT_DYNAMIC)
18593 break;
18594
18595 if (m == NULL)
18596 {
18597 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 18598 m->next = elf_seg_map (abfd);
18599 elf_seg_map (abfd) = m;
8ded5a0f 18600 }
7f266840
DJ		 18601 }
18602
b294bdf8
MM		 18603 /* Also call the generic arm routine. */
18604 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 18605}
18606
95720a86
DJ		 18607/* Return address for Ith PLT stub in section PLT, for relocation REL
18608 or (bfd_vma) -1 if it should not be included. */
18609
18610static bfd_vma
18611elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
18612 const arelent *rel ATTRIBUTE_UNUSED)
18613{
18614 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
18615}
18616
8029a119 18617#undef elf32_bed
7f266840
DJ		 18618#define elf32_bed elf32_arm_symbian_bed
18619
18620/* The dynamic sections are not allocated on SymbianOS; the postlinker
18621 will process them and then discard them. */
906e58ca 18622#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 18623#define ELF_DYNAMIC_SEC_FLAGS \
18624 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
18625
00a97672 18626#undef elf_backend_emit_relocs
c3c76620 18627
906e58ca
NC		 18628#undef bfd_elf32_bfd_link_hash_table_create
18629#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
18630#undef elf_backend_special_sections
18631#define elf_backend_special_sections elf32_arm_symbian_special_sections
18632#undef elf_backend_begin_write_processing
18633#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
18634#undef elf_backend_final_write_processing
18635#define elf_backend_final_write_processing elf32_arm_final_write_processing
18636
18637#undef elf_backend_modify_segment_map
7f266840
DJ		 18638#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
18639
18640/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 18641#undef elf_backend_got_header_size
7f266840
DJ		 18642#define elf_backend_got_header_size 0
18643
18644/* Similarly, there is no .got.plt section. */
906e58ca 18645#undef elf_backend_want_got_plt
7f266840
DJ		 18646#define elf_backend_want_got_plt 0
18647
906e58ca 18648#undef elf_backend_plt_sym_val
95720a86
DJ		 18649#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
18650
906e58ca 18651#undef elf_backend_may_use_rel_p
00a97672 18652#define elf_backend_may_use_rel_p 1
906e58ca 18653#undef elf_backend_may_use_rela_p
00a97672 18654#define elf_backend_may_use_rela_p 0
906e58ca 18655#undef elf_backend_default_use_rela_p
00a97672 18656#define elf_backend_default_use_rela_p 0
906e58ca 18657#undef elf_backend_want_plt_sym
00a97672 18658#define elf_backend_want_plt_sym 0
906e58ca 18659#undef ELF_MAXPAGESIZE
00a97672 18660#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 18661
7f266840 18662#include "elf32-target.h"
GDB Binutils - Deliverables
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