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PR25100, Compile fails in elf64-ppc.c because of single equal sign instead of double...
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
82704155 2 Copyright (C) 1998-2019 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
00a97672 25#include "libiberty.h"
7f266840
DJ		 26#include "libbfd.h"
27#include "elf-bfd.h"
b38cadfb 28#include "elf-nacl.h"
00a97672 29#include "elf-vxworks.h"
ee065d83 30#include "elf/arm.h"
f37164d7
AM		 31#include "elf32-arm.h"
32#include "cpu-arm.h"
7f266840 33
00a97672
RS		 34/* Return the relocation section associated with NAME. HTAB is the
35 bfd's elf32_arm_link_hash_entry. */
36#define RELOC_SECTION(HTAB, NAME) \
37 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
38
39/* Return size of a relocation entry. HTAB is the bfd's
40 elf32_arm_link_hash_entry. */
41#define RELOC_SIZE(HTAB) \
42 ((HTAB)->use_rel \
43 ? sizeof (Elf32_External_Rel) \
44 : sizeof (Elf32_External_Rela))
45
46/* Return function to swap relocations in. HTAB is the bfd's
47 elf32_arm_link_hash_entry. */
48#define SWAP_RELOC_IN(HTAB) \
49 ((HTAB)->use_rel \
50 ? bfd_elf32_swap_reloc_in \
51 : bfd_elf32_swap_reloca_in)
52
53/* Return function to swap relocations out. HTAB is the bfd's
54 elf32_arm_link_hash_entry. */
55#define SWAP_RELOC_OUT(HTAB) \
56 ((HTAB)->use_rel \
57 ? bfd_elf32_swap_reloc_out \
58 : bfd_elf32_swap_reloca_out)
59
f3185997 60#define elf_info_to_howto NULL
07d6d2b8 61#define elf_info_to_howto_rel elf32_arm_info_to_howto
7f266840
DJ		 62
63#define ARM_ELF_ABI_VERSION 0
64#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
65
79f08007
YZ		 66/* The Adjusted Place, as defined by AAELF. */
67#define Pa(X) ((X) & 0xfffffffc)
68
3e6b1042
DJ		 69static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
70 struct bfd_link_info *link_info,
71 asection *sec,
72 bfd_byte *contents);
73
7f266840
DJ		 74/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
75 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
76 in that slot. */
77
c19d1205 78static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 79{
8029a119 80 /* No relocation. */
7f266840
DJ		 81 HOWTO (R_ARM_NONE, /* type */
82 0, /* rightshift */
6346d5ca 83 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 84 0, /* bitsize */
85 FALSE, /* pc_relative */
86 0, /* bitpos */
87 complain_overflow_dont,/* complain_on_overflow */
88 bfd_elf_generic_reloc, /* special_function */
89 "R_ARM_NONE", /* name */
90 FALSE, /* partial_inplace */
91 0, /* src_mask */
92 0, /* dst_mask */
93 FALSE), /* pcrel_offset */
94
95 HOWTO (R_ARM_PC24, /* type */
96 2, /* rightshift */
97 2, /* size (0 = byte, 1 = short, 2 = long) */
98 24, /* bitsize */
99 TRUE, /* pc_relative */
100 0, /* bitpos */
101 complain_overflow_signed,/* complain_on_overflow */
102 bfd_elf_generic_reloc, /* special_function */
103 "R_ARM_PC24", /* name */
104 FALSE, /* partial_inplace */
105 0x00ffffff, /* src_mask */
106 0x00ffffff, /* dst_mask */
107 TRUE), /* pcrel_offset */
108
109 /* 32 bit absolute */
110 HOWTO (R_ARM_ABS32, /* type */
111 0, /* rightshift */
112 2, /* size (0 = byte, 1 = short, 2 = long) */
113 32, /* bitsize */
114 FALSE, /* pc_relative */
115 0, /* bitpos */
116 complain_overflow_bitfield,/* complain_on_overflow */
117 bfd_elf_generic_reloc, /* special_function */
118 "R_ARM_ABS32", /* name */
119 FALSE, /* partial_inplace */
120 0xffffffff, /* src_mask */
121 0xffffffff, /* dst_mask */
122 FALSE), /* pcrel_offset */
123
124 /* standard 32bit pc-relative reloc */
125 HOWTO (R_ARM_REL32, /* type */
126 0, /* rightshift */
127 2, /* size (0 = byte, 1 = short, 2 = long) */
128 32, /* bitsize */
129 TRUE, /* pc_relative */
130 0, /* bitpos */
131 complain_overflow_bitfield,/* complain_on_overflow */
132 bfd_elf_generic_reloc, /* special_function */
133 "R_ARM_REL32", /* name */
134 FALSE, /* partial_inplace */
135 0xffffffff, /* src_mask */
136 0xffffffff, /* dst_mask */
137 TRUE), /* pcrel_offset */
138
c19d1205 139 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 140 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 141 0, /* rightshift */
142 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 143 32, /* bitsize */
144 TRUE, /* pc_relative */
7f266840 145 0, /* bitpos */
4962c51a 146 complain_overflow_dont,/* complain_on_overflow */
7f266840 147 bfd_elf_generic_reloc, /* special_function */
4962c51a 148 "R_ARM_LDR_PC_G0", /* name */
7f266840 149 FALSE, /* partial_inplace */
4962c51a
MS		 150 0xffffffff, /* src_mask */
151 0xffffffff, /* dst_mask */
152 TRUE), /* pcrel_offset */
7f266840
DJ		 153
154 /* 16 bit absolute */
155 HOWTO (R_ARM_ABS16, /* type */
156 0, /* rightshift */
157 1, /* size (0 = byte, 1 = short, 2 = long) */
158 16, /* bitsize */
159 FALSE, /* pc_relative */
160 0, /* bitpos */
161 complain_overflow_bitfield,/* complain_on_overflow */
162 bfd_elf_generic_reloc, /* special_function */
163 "R_ARM_ABS16", /* name */
164 FALSE, /* partial_inplace */
165 0x0000ffff, /* src_mask */
166 0x0000ffff, /* dst_mask */
167 FALSE), /* pcrel_offset */
168
169 /* 12 bit absolute */
170 HOWTO (R_ARM_ABS12, /* type */
171 0, /* rightshift */
172 2, /* size (0 = byte, 1 = short, 2 = long) */
173 12, /* bitsize */
174 FALSE, /* pc_relative */
175 0, /* bitpos */
176 complain_overflow_bitfield,/* complain_on_overflow */
177 bfd_elf_generic_reloc, /* special_function */
178 "R_ARM_ABS12", /* name */
179 FALSE, /* partial_inplace */
00a97672
RS		 180 0x00000fff, /* src_mask */
181 0x00000fff, /* dst_mask */
7f266840
DJ		 182 FALSE), /* pcrel_offset */
183
184 HOWTO (R_ARM_THM_ABS5, /* type */
185 6, /* rightshift */
186 1, /* size (0 = byte, 1 = short, 2 = long) */
187 5, /* bitsize */
188 FALSE, /* pc_relative */
189 0, /* bitpos */
190 complain_overflow_bitfield,/* complain_on_overflow */
191 bfd_elf_generic_reloc, /* special_function */
192 "R_ARM_THM_ABS5", /* name */
193 FALSE, /* partial_inplace */
194 0x000007e0, /* src_mask */
195 0x000007e0, /* dst_mask */
196 FALSE), /* pcrel_offset */
197
198 /* 8 bit absolute */
199 HOWTO (R_ARM_ABS8, /* type */
200 0, /* rightshift */
201 0, /* size (0 = byte, 1 = short, 2 = long) */
202 8, /* bitsize */
203 FALSE, /* pc_relative */
204 0, /* bitpos */
205 complain_overflow_bitfield,/* complain_on_overflow */
206 bfd_elf_generic_reloc, /* special_function */
207 "R_ARM_ABS8", /* name */
208 FALSE, /* partial_inplace */
209 0x000000ff, /* src_mask */
210 0x000000ff, /* dst_mask */
211 FALSE), /* pcrel_offset */
212
213 HOWTO (R_ARM_SBREL32, /* type */
214 0, /* rightshift */
215 2, /* size (0 = byte, 1 = short, 2 = long) */
216 32, /* bitsize */
217 FALSE, /* pc_relative */
218 0, /* bitpos */
219 complain_overflow_dont,/* complain_on_overflow */
220 bfd_elf_generic_reloc, /* special_function */
221 "R_ARM_SBREL32", /* name */
222 FALSE, /* partial_inplace */
223 0xffffffff, /* src_mask */
224 0xffffffff, /* dst_mask */
225 FALSE), /* pcrel_offset */
226
c19d1205 227 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 228 1, /* rightshift */
229 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 230 24, /* bitsize */
7f266840
DJ		 231 TRUE, /* pc_relative */
232 0, /* bitpos */
233 complain_overflow_signed,/* complain_on_overflow */
234 bfd_elf_generic_reloc, /* special_function */
c19d1205 235 "R_ARM_THM_CALL", /* name */
7f266840 236 FALSE, /* partial_inplace */
7f6ab9f8
AM		 237 0x07ff2fff, /* src_mask */
238 0x07ff2fff, /* dst_mask */
7f266840
DJ		 239 TRUE), /* pcrel_offset */
240
07d6d2b8 241 HOWTO (R_ARM_THM_PC8, /* type */
7f266840
DJ		 242 1, /* rightshift */
243 1, /* size (0 = byte, 1 = short, 2 = long) */
244 8, /* bitsize */
245 TRUE, /* pc_relative */
246 0, /* bitpos */
247 complain_overflow_signed,/* complain_on_overflow */
248 bfd_elf_generic_reloc, /* special_function */
249 "R_ARM_THM_PC8", /* name */
250 FALSE, /* partial_inplace */
251 0x000000ff, /* src_mask */
252 0x000000ff, /* dst_mask */
253 TRUE), /* pcrel_offset */
254
c19d1205 255 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 256 1, /* rightshift */
257 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 258 32, /* bitsize */
259 FALSE, /* pc_relative */
7f266840
DJ		 260 0, /* bitpos */
261 complain_overflow_signed,/* complain_on_overflow */
262 bfd_elf_generic_reloc, /* special_function */
c19d1205 263 "R_ARM_BREL_ADJ", /* name */
7f266840 264 FALSE, /* partial_inplace */
c19d1205
ZW		 265 0xffffffff, /* src_mask */
266 0xffffffff, /* dst_mask */
267 FALSE), /* pcrel_offset */
7f266840 268
0855e32b 269 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 270 0, /* rightshift */
0855e32b
NS		 271 2, /* size (0 = byte, 1 = short, 2 = long) */
272 32, /* bitsize */
7f266840
DJ		 273 FALSE, /* pc_relative */
274 0, /* bitpos */
0855e32b 275 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 276 bfd_elf_generic_reloc, /* special_function */
0855e32b 277 "R_ARM_TLS_DESC", /* name */
7f266840 278 FALSE, /* partial_inplace */
0855e32b
NS		 279 0xffffffff, /* src_mask */
280 0xffffffff, /* dst_mask */
7f266840
DJ		 281 FALSE), /* pcrel_offset */
282
283 HOWTO (R_ARM_THM_SWI8, /* type */
284 0, /* rightshift */
285 0, /* size (0 = byte, 1 = short, 2 = long) */
286 0, /* bitsize */
287 FALSE, /* pc_relative */
288 0, /* bitpos */
289 complain_overflow_signed,/* complain_on_overflow */
290 bfd_elf_generic_reloc, /* special_function */
291 "R_ARM_SWI8", /* name */
292 FALSE, /* partial_inplace */
293 0x00000000, /* src_mask */
294 0x00000000, /* dst_mask */
295 FALSE), /* pcrel_offset */
296
297 /* BLX instruction for the ARM. */
298 HOWTO (R_ARM_XPC25, /* type */
299 2, /* rightshift */
300 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 301 24, /* bitsize */
7f266840
DJ		 302 TRUE, /* pc_relative */
303 0, /* bitpos */
304 complain_overflow_signed,/* complain_on_overflow */
305 bfd_elf_generic_reloc, /* special_function */
306 "R_ARM_XPC25", /* name */
307 FALSE, /* partial_inplace */
308 0x00ffffff, /* src_mask */
309 0x00ffffff, /* dst_mask */
310 TRUE), /* pcrel_offset */
311
312 /* BLX instruction for the Thumb. */
313 HOWTO (R_ARM_THM_XPC22, /* type */
314 2, /* rightshift */
315 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 316 24, /* bitsize */
7f266840
DJ		 317 TRUE, /* pc_relative */
318 0, /* bitpos */
319 complain_overflow_signed,/* complain_on_overflow */
320 bfd_elf_generic_reloc, /* special_function */
321 "R_ARM_THM_XPC22", /* name */
322 FALSE, /* partial_inplace */
7f6ab9f8
AM		 323 0x07ff2fff, /* src_mask */
324 0x07ff2fff, /* dst_mask */
7f266840
DJ		 325 TRUE), /* pcrel_offset */
326
ba93b8ac 327 /* Dynamic TLS relocations. */
7f266840 328
ba93b8ac 329 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
07d6d2b8
AM		 330 0, /* rightshift */
331 2, /* size (0 = byte, 1 = short, 2 = long) */
332 32, /* bitsize */
333 FALSE, /* pc_relative */
334 0, /* bitpos */
99059e56
RM		 335 complain_overflow_bitfield,/* complain_on_overflow */
336 bfd_elf_generic_reloc, /* special_function */
337 "R_ARM_TLS_DTPMOD32", /* name */
338 TRUE, /* partial_inplace */
339 0xffffffff, /* src_mask */
340 0xffffffff, /* dst_mask */
07d6d2b8 341 FALSE), /* pcrel_offset */
7f266840 342
ba93b8ac 343 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
07d6d2b8
AM		 344 0, /* rightshift */
345 2, /* size (0 = byte, 1 = short, 2 = long) */
346 32, /* bitsize */
347 FALSE, /* pc_relative */
348 0, /* bitpos */
99059e56
RM		 349 complain_overflow_bitfield,/* complain_on_overflow */
350 bfd_elf_generic_reloc, /* special_function */
351 "R_ARM_TLS_DTPOFF32", /* name */
352 TRUE, /* partial_inplace */
353 0xffffffff, /* src_mask */
354 0xffffffff, /* dst_mask */
07d6d2b8 355 FALSE), /* pcrel_offset */
7f266840 356
ba93b8ac 357 HOWTO (R_ARM_TLS_TPOFF32, /* type */
07d6d2b8
AM		 358 0, /* rightshift */
359 2, /* size (0 = byte, 1 = short, 2 = long) */
360 32, /* bitsize */
361 FALSE, /* pc_relative */
362 0, /* bitpos */
99059e56
RM		 363 complain_overflow_bitfield,/* complain_on_overflow */
364 bfd_elf_generic_reloc, /* special_function */
365 "R_ARM_TLS_TPOFF32", /* name */
366 TRUE, /* partial_inplace */
367 0xffffffff, /* src_mask */
368 0xffffffff, /* dst_mask */
07d6d2b8 369 FALSE), /* pcrel_offset */
7f266840
DJ		 370
371 /* Relocs used in ARM Linux */
372
373 HOWTO (R_ARM_COPY, /* type */
07d6d2b8
AM		 374 0, /* rightshift */
375 2, /* size (0 = byte, 1 = short, 2 = long) */
376 32, /* bitsize */
377 FALSE, /* pc_relative */
378 0, /* bitpos */
99059e56
RM		 379 complain_overflow_bitfield,/* complain_on_overflow */
380 bfd_elf_generic_reloc, /* special_function */
381 "R_ARM_COPY", /* name */
382 TRUE, /* partial_inplace */
383 0xffffffff, /* src_mask */
384 0xffffffff, /* dst_mask */
07d6d2b8 385 FALSE), /* pcrel_offset */
7f266840
DJ		 386
387 HOWTO (R_ARM_GLOB_DAT, /* type */
07d6d2b8
AM		 388 0, /* rightshift */
389 2, /* size (0 = byte, 1 = short, 2 = long) */
390 32, /* bitsize */
391 FALSE, /* pc_relative */
392 0, /* bitpos */
99059e56
RM		 393 complain_overflow_bitfield,/* complain_on_overflow */
394 bfd_elf_generic_reloc, /* special_function */
395 "R_ARM_GLOB_DAT", /* name */
396 TRUE, /* partial_inplace */
397 0xffffffff, /* src_mask */
398 0xffffffff, /* dst_mask */
07d6d2b8 399 FALSE), /* pcrel_offset */
7f266840
DJ		 400
401 HOWTO (R_ARM_JUMP_SLOT, /* type */
07d6d2b8
AM		 402 0, /* rightshift */
403 2, /* size (0 = byte, 1 = short, 2 = long) */
404 32, /* bitsize */
405 FALSE, /* pc_relative */
406 0, /* bitpos */
99059e56
RM		 407 complain_overflow_bitfield,/* complain_on_overflow */
408 bfd_elf_generic_reloc, /* special_function */
409 "R_ARM_JUMP_SLOT", /* name */
410 TRUE, /* partial_inplace */
411 0xffffffff, /* src_mask */
412 0xffffffff, /* dst_mask */
07d6d2b8 413 FALSE), /* pcrel_offset */
7f266840
DJ		 414
415 HOWTO (R_ARM_RELATIVE, /* type */
07d6d2b8
AM		 416 0, /* rightshift */
417 2, /* size (0 = byte, 1 = short, 2 = long) */
418 32, /* bitsize */
419 FALSE, /* pc_relative */
420 0, /* bitpos */
99059e56
RM		 421 complain_overflow_bitfield,/* complain_on_overflow */
422 bfd_elf_generic_reloc, /* special_function */
423 "R_ARM_RELATIVE", /* name */
424 TRUE, /* partial_inplace */
425 0xffffffff, /* src_mask */
426 0xffffffff, /* dst_mask */
07d6d2b8 427 FALSE), /* pcrel_offset */
7f266840 428
c19d1205 429 HOWTO (R_ARM_GOTOFF32, /* type */
07d6d2b8
AM		 430 0, /* rightshift */
431 2, /* size (0 = byte, 1 = short, 2 = long) */
432 32, /* bitsize */
433 FALSE, /* pc_relative */
434 0, /* bitpos */
99059e56
RM		 435 complain_overflow_bitfield,/* complain_on_overflow */
436 bfd_elf_generic_reloc, /* special_function */
437 "R_ARM_GOTOFF32", /* name */
438 TRUE, /* partial_inplace */
439 0xffffffff, /* src_mask */
440 0xffffffff, /* dst_mask */
07d6d2b8 441 FALSE), /* pcrel_offset */
7f266840
DJ		 442
443 HOWTO (R_ARM_GOTPC, /* type */
07d6d2b8
AM		 444 0, /* rightshift */
445 2, /* size (0 = byte, 1 = short, 2 = long) */
446 32, /* bitsize */
99059e56 447 TRUE, /* pc_relative */
07d6d2b8 448 0, /* bitpos */
99059e56
RM		 449 complain_overflow_bitfield,/* complain_on_overflow */
450 bfd_elf_generic_reloc, /* special_function */
451 "R_ARM_GOTPC", /* name */
452 TRUE, /* partial_inplace */
453 0xffffffff, /* src_mask */
454 0xffffffff, /* dst_mask */
455 TRUE), /* pcrel_offset */
7f266840
DJ		 456
457 HOWTO (R_ARM_GOT32, /* type */
07d6d2b8
AM		 458 0, /* rightshift */
459 2, /* size (0 = byte, 1 = short, 2 = long) */
460 32, /* bitsize */
99059e56 461 FALSE, /* pc_relative */
07d6d2b8 462 0, /* bitpos */
99059e56
RM		 463 complain_overflow_bitfield,/* complain_on_overflow */
464 bfd_elf_generic_reloc, /* special_function */
465 "R_ARM_GOT32", /* name */
466 TRUE, /* partial_inplace */
467 0xffffffff, /* src_mask */
468 0xffffffff, /* dst_mask */
469 FALSE), /* pcrel_offset */
7f266840
DJ		 470
471 HOWTO (R_ARM_PLT32, /* type */
07d6d2b8
AM		 472 2, /* rightshift */
473 2, /* size (0 = byte, 1 = short, 2 = long) */
474 24, /* bitsize */
99059e56 475 TRUE, /* pc_relative */
07d6d2b8 476 0, /* bitpos */
99059e56
RM		 477 complain_overflow_bitfield,/* complain_on_overflow */
478 bfd_elf_generic_reloc, /* special_function */
479 "R_ARM_PLT32", /* name */
480 FALSE, /* partial_inplace */
481 0x00ffffff, /* src_mask */
482 0x00ffffff, /* dst_mask */
483 TRUE), /* pcrel_offset */
7f266840
DJ		 484
485 HOWTO (R_ARM_CALL, /* type */
486 2, /* rightshift */
487 2, /* size (0 = byte, 1 = short, 2 = long) */
488 24, /* bitsize */
489 TRUE, /* pc_relative */
490 0, /* bitpos */
491 complain_overflow_signed,/* complain_on_overflow */
492 bfd_elf_generic_reloc, /* special_function */
493 "R_ARM_CALL", /* name */
494 FALSE, /* partial_inplace */
495 0x00ffffff, /* src_mask */
496 0x00ffffff, /* dst_mask */
497 TRUE), /* pcrel_offset */
498
499 HOWTO (R_ARM_JUMP24, /* type */
500 2, /* rightshift */
501 2, /* size (0 = byte, 1 = short, 2 = long) */
502 24, /* bitsize */
503 TRUE, /* pc_relative */
504 0, /* bitpos */
505 complain_overflow_signed,/* complain_on_overflow */
506 bfd_elf_generic_reloc, /* special_function */
507 "R_ARM_JUMP24", /* name */
508 FALSE, /* partial_inplace */
509 0x00ffffff, /* src_mask */
510 0x00ffffff, /* dst_mask */
511 TRUE), /* pcrel_offset */
512
c19d1205
ZW		 513 HOWTO (R_ARM_THM_JUMP24, /* type */
514 1, /* rightshift */
515 2, /* size (0 = byte, 1 = short, 2 = long) */
516 24, /* bitsize */
517 TRUE, /* pc_relative */
7f266840 518 0, /* bitpos */
c19d1205 519 complain_overflow_signed,/* complain_on_overflow */
7f266840 520 bfd_elf_generic_reloc, /* special_function */
c19d1205 521 "R_ARM_THM_JUMP24", /* name */
7f266840 522 FALSE, /* partial_inplace */
c19d1205
ZW		 523 0x07ff2fff, /* src_mask */
524 0x07ff2fff, /* dst_mask */
525 TRUE), /* pcrel_offset */
7f266840 526
c19d1205 527 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 528 0, /* rightshift */
c19d1205
ZW		 529 2, /* size (0 = byte, 1 = short, 2 = long) */
530 32, /* bitsize */
7f266840
DJ		 531 FALSE, /* pc_relative */
532 0, /* bitpos */
533 complain_overflow_dont,/* complain_on_overflow */
534 bfd_elf_generic_reloc, /* special_function */
c19d1205 535 "R_ARM_BASE_ABS", /* name */
7f266840 536 FALSE, /* partial_inplace */
c19d1205
ZW		 537 0xffffffff, /* src_mask */
538 0xffffffff, /* dst_mask */
7f266840
DJ		 539 FALSE), /* pcrel_offset */
540
541 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
542 0, /* rightshift */
543 2, /* size (0 = byte, 1 = short, 2 = long) */
544 12, /* bitsize */
545 TRUE, /* pc_relative */
546 0, /* bitpos */
547 complain_overflow_dont,/* complain_on_overflow */
548 bfd_elf_generic_reloc, /* special_function */
549 "R_ARM_ALU_PCREL_7_0", /* name */
550 FALSE, /* partial_inplace */
551 0x00000fff, /* src_mask */
552 0x00000fff, /* dst_mask */
553 TRUE), /* pcrel_offset */
554
555 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
556 0, /* rightshift */
557 2, /* size (0 = byte, 1 = short, 2 = long) */
558 12, /* bitsize */
559 TRUE, /* pc_relative */
560 8, /* bitpos */
561 complain_overflow_dont,/* complain_on_overflow */
562 bfd_elf_generic_reloc, /* special_function */
563 "R_ARM_ALU_PCREL_15_8",/* name */
564 FALSE, /* partial_inplace */
565 0x00000fff, /* src_mask */
566 0x00000fff, /* dst_mask */
567 TRUE), /* pcrel_offset */
568
569 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
570 0, /* rightshift */
571 2, /* size (0 = byte, 1 = short, 2 = long) */
572 12, /* bitsize */
573 TRUE, /* pc_relative */
574 16, /* bitpos */
575 complain_overflow_dont,/* complain_on_overflow */
576 bfd_elf_generic_reloc, /* special_function */
577 "R_ARM_ALU_PCREL_23_15",/* name */
578 FALSE, /* partial_inplace */
579 0x00000fff, /* src_mask */
580 0x00000fff, /* dst_mask */
581 TRUE), /* pcrel_offset */
582
583 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
584 0, /* rightshift */
585 2, /* size (0 = byte, 1 = short, 2 = long) */
586 12, /* bitsize */
587 FALSE, /* pc_relative */
588 0, /* bitpos */
589 complain_overflow_dont,/* complain_on_overflow */
590 bfd_elf_generic_reloc, /* special_function */
591 "R_ARM_LDR_SBREL_11_0",/* name */
592 FALSE, /* partial_inplace */
593 0x00000fff, /* src_mask */
594 0x00000fff, /* dst_mask */
595 FALSE), /* pcrel_offset */
596
597 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
598 0, /* rightshift */
599 2, /* size (0 = byte, 1 = short, 2 = long) */
600 8, /* bitsize */
601 FALSE, /* pc_relative */
602 12, /* bitpos */
603 complain_overflow_dont,/* complain_on_overflow */
604 bfd_elf_generic_reloc, /* special_function */
605 "R_ARM_ALU_SBREL_19_12",/* name */
606 FALSE, /* partial_inplace */
607 0x000ff000, /* src_mask */
608 0x000ff000, /* dst_mask */
609 FALSE), /* pcrel_offset */
610
611 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
612 0, /* rightshift */
613 2, /* size (0 = byte, 1 = short, 2 = long) */
614 8, /* bitsize */
615 FALSE, /* pc_relative */
616 20, /* bitpos */
617 complain_overflow_dont,/* complain_on_overflow */
618 bfd_elf_generic_reloc, /* special_function */
619 "R_ARM_ALU_SBREL_27_20",/* name */
620 FALSE, /* partial_inplace */
621 0x0ff00000, /* src_mask */
622 0x0ff00000, /* dst_mask */
623 FALSE), /* pcrel_offset */
624
625 HOWTO (R_ARM_TARGET1, /* type */
626 0, /* rightshift */
627 2, /* size (0 = byte, 1 = short, 2 = long) */
628 32, /* bitsize */
629 FALSE, /* pc_relative */
630 0, /* bitpos */
631 complain_overflow_dont,/* complain_on_overflow */
632 bfd_elf_generic_reloc, /* special_function */
633 "R_ARM_TARGET1", /* name */
634 FALSE, /* partial_inplace */
635 0xffffffff, /* src_mask */
636 0xffffffff, /* dst_mask */
637 FALSE), /* pcrel_offset */
638
639 HOWTO (R_ARM_ROSEGREL32, /* type */
640 0, /* rightshift */
641 2, /* size (0 = byte, 1 = short, 2 = long) */
642 32, /* bitsize */
643 FALSE, /* pc_relative */
644 0, /* bitpos */
645 complain_overflow_dont,/* complain_on_overflow */
646 bfd_elf_generic_reloc, /* special_function */
647 "R_ARM_ROSEGREL32", /* name */
648 FALSE, /* partial_inplace */
649 0xffffffff, /* src_mask */
650 0xffffffff, /* dst_mask */
651 FALSE), /* pcrel_offset */
652
653 HOWTO (R_ARM_V4BX, /* type */
654 0, /* rightshift */
655 2, /* size (0 = byte, 1 = short, 2 = long) */
656 32, /* bitsize */
657 FALSE, /* pc_relative */
658 0, /* bitpos */
659 complain_overflow_dont,/* complain_on_overflow */
660 bfd_elf_generic_reloc, /* special_function */
661 "R_ARM_V4BX", /* name */
662 FALSE, /* partial_inplace */
663 0xffffffff, /* src_mask */
664 0xffffffff, /* dst_mask */
665 FALSE), /* pcrel_offset */
666
667 HOWTO (R_ARM_TARGET2, /* type */
668 0, /* rightshift */
669 2, /* size (0 = byte, 1 = short, 2 = long) */
670 32, /* bitsize */
671 FALSE, /* pc_relative */
672 0, /* bitpos */
673 complain_overflow_signed,/* complain_on_overflow */
674 bfd_elf_generic_reloc, /* special_function */
675 "R_ARM_TARGET2", /* name */
676 FALSE, /* partial_inplace */
677 0xffffffff, /* src_mask */
678 0xffffffff, /* dst_mask */
679 TRUE), /* pcrel_offset */
680
681 HOWTO (R_ARM_PREL31, /* type */
682 0, /* rightshift */
683 2, /* size (0 = byte, 1 = short, 2 = long) */
684 31, /* bitsize */
685 TRUE, /* pc_relative */
686 0, /* bitpos */
687 complain_overflow_signed,/* complain_on_overflow */
688 bfd_elf_generic_reloc, /* special_function */
689 "R_ARM_PREL31", /* name */
690 FALSE, /* partial_inplace */
691 0x7fffffff, /* src_mask */
692 0x7fffffff, /* dst_mask */
693 TRUE), /* pcrel_offset */
c19d1205
ZW		 694
695 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
696 0, /* rightshift */
697 2, /* size (0 = byte, 1 = short, 2 = long) */
698 16, /* bitsize */
699 FALSE, /* pc_relative */
700 0, /* bitpos */
701 complain_overflow_dont,/* complain_on_overflow */
702 bfd_elf_generic_reloc, /* special_function */
703 "R_ARM_MOVW_ABS_NC", /* name */
704 FALSE, /* partial_inplace */
39623e12
PB		 705 0x000f0fff, /* src_mask */
706 0x000f0fff, /* dst_mask */
c19d1205
ZW		 707 FALSE), /* pcrel_offset */
708
709 HOWTO (R_ARM_MOVT_ABS, /* type */
710 0, /* rightshift */
711 2, /* size (0 = byte, 1 = short, 2 = long) */
712 16, /* bitsize */
713 FALSE, /* pc_relative */
714 0, /* bitpos */
715 complain_overflow_bitfield,/* complain_on_overflow */
716 bfd_elf_generic_reloc, /* special_function */
717 "R_ARM_MOVT_ABS", /* name */
718 FALSE, /* partial_inplace */
39623e12
PB		 719 0x000f0fff, /* src_mask */
720 0x000f0fff, /* dst_mask */
c19d1205
ZW		 721 FALSE), /* pcrel_offset */
722
723 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
724 0, /* rightshift */
725 2, /* size (0 = byte, 1 = short, 2 = long) */
726 16, /* bitsize */
727 TRUE, /* pc_relative */
728 0, /* bitpos */
729 complain_overflow_dont,/* complain_on_overflow */
730 bfd_elf_generic_reloc, /* special_function */
731 "R_ARM_MOVW_PREL_NC", /* name */
732 FALSE, /* partial_inplace */
39623e12
PB		 733 0x000f0fff, /* src_mask */
734 0x000f0fff, /* dst_mask */
c19d1205
ZW		 735 TRUE), /* pcrel_offset */
736
737 HOWTO (R_ARM_MOVT_PREL, /* type */
738 0, /* rightshift */
739 2, /* size (0 = byte, 1 = short, 2 = long) */
740 16, /* bitsize */
741 TRUE, /* pc_relative */
742 0, /* bitpos */
743 complain_overflow_bitfield,/* complain_on_overflow */
744 bfd_elf_generic_reloc, /* special_function */
745 "R_ARM_MOVT_PREL", /* name */
746 FALSE, /* partial_inplace */
39623e12
PB		 747 0x000f0fff, /* src_mask */
748 0x000f0fff, /* dst_mask */
c19d1205
ZW		 749 TRUE), /* pcrel_offset */
750
751 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
752 0, /* rightshift */
753 2, /* size (0 = byte, 1 = short, 2 = long) */
754 16, /* bitsize */
755 FALSE, /* pc_relative */
756 0, /* bitpos */
757 complain_overflow_dont,/* complain_on_overflow */
758 bfd_elf_generic_reloc, /* special_function */
759 "R_ARM_THM_MOVW_ABS_NC",/* name */
760 FALSE, /* partial_inplace */
761 0x040f70ff, /* src_mask */
762 0x040f70ff, /* dst_mask */
763 FALSE), /* pcrel_offset */
764
765 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
766 0, /* rightshift */
767 2, /* size (0 = byte, 1 = short, 2 = long) */
768 16, /* bitsize */
769 FALSE, /* pc_relative */
770 0, /* bitpos */
771 complain_overflow_bitfield,/* complain_on_overflow */
772 bfd_elf_generic_reloc, /* special_function */
773 "R_ARM_THM_MOVT_ABS", /* name */
774 FALSE, /* partial_inplace */
775 0x040f70ff, /* src_mask */
776 0x040f70ff, /* dst_mask */
777 FALSE), /* pcrel_offset */
778
779 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
780 0, /* rightshift */
781 2, /* size (0 = byte, 1 = short, 2 = long) */
782 16, /* bitsize */
783 TRUE, /* pc_relative */
784 0, /* bitpos */
785 complain_overflow_dont,/* complain_on_overflow */
786 bfd_elf_generic_reloc, /* special_function */
787 "R_ARM_THM_MOVW_PREL_NC",/* name */
788 FALSE, /* partial_inplace */
789 0x040f70ff, /* src_mask */
790 0x040f70ff, /* dst_mask */
791 TRUE), /* pcrel_offset */
792
793 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
794 0, /* rightshift */
795 2, /* size (0 = byte, 1 = short, 2 = long) */
796 16, /* bitsize */
797 TRUE, /* pc_relative */
798 0, /* bitpos */
799 complain_overflow_bitfield,/* complain_on_overflow */
800 bfd_elf_generic_reloc, /* special_function */
801 "R_ARM_THM_MOVT_PREL", /* name */
802 FALSE, /* partial_inplace */
803 0x040f70ff, /* src_mask */
804 0x040f70ff, /* dst_mask */
805 TRUE), /* pcrel_offset */
806
807 HOWTO (R_ARM_THM_JUMP19, /* type */
808 1, /* rightshift */
809 2, /* size (0 = byte, 1 = short, 2 = long) */
810 19, /* bitsize */
811 TRUE, /* pc_relative */
812 0, /* bitpos */
813 complain_overflow_signed,/* complain_on_overflow */
814 bfd_elf_generic_reloc, /* special_function */
815 "R_ARM_THM_JUMP19", /* name */
816 FALSE, /* partial_inplace */
817 0x043f2fff, /* src_mask */
818 0x043f2fff, /* dst_mask */
819 TRUE), /* pcrel_offset */
820
821 HOWTO (R_ARM_THM_JUMP6, /* type */
822 1, /* rightshift */
823 1, /* size (0 = byte, 1 = short, 2 = long) */
824 6, /* bitsize */
825 TRUE, /* pc_relative */
826 0, /* bitpos */
827 complain_overflow_unsigned,/* complain_on_overflow */
828 bfd_elf_generic_reloc, /* special_function */
829 "R_ARM_THM_JUMP6", /* name */
830 FALSE, /* partial_inplace */
831 0x02f8, /* src_mask */
832 0x02f8, /* dst_mask */
833 TRUE), /* pcrel_offset */
834
835 /* These are declared as 13-bit signed relocations because we can
836 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
837 versa. */
838 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
839 0, /* rightshift */
840 2, /* size (0 = byte, 1 = short, 2 = long) */
841 13, /* bitsize */
842 TRUE, /* pc_relative */
843 0, /* bitpos */
2cab6cc3 844 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 845 bfd_elf_generic_reloc, /* special_function */
846 "R_ARM_THM_ALU_PREL_11_0",/* name */
847 FALSE, /* partial_inplace */
2cab6cc3
MS		 848 0xffffffff, /* src_mask */
849 0xffffffff, /* dst_mask */
c19d1205
ZW		 850 TRUE), /* pcrel_offset */
851
852 HOWTO (R_ARM_THM_PC12, /* type */
853 0, /* rightshift */
854 2, /* size (0 = byte, 1 = short, 2 = long) */
855 13, /* bitsize */
856 TRUE, /* pc_relative */
857 0, /* bitpos */
2cab6cc3 858 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 859 bfd_elf_generic_reloc, /* special_function */
860 "R_ARM_THM_PC12", /* name */
861 FALSE, /* partial_inplace */
2cab6cc3
MS		 862 0xffffffff, /* src_mask */
863 0xffffffff, /* dst_mask */
c19d1205
ZW		 864 TRUE), /* pcrel_offset */
865
866 HOWTO (R_ARM_ABS32_NOI, /* type */
867 0, /* rightshift */
868 2, /* size (0 = byte, 1 = short, 2 = long) */
869 32, /* bitsize */
870 FALSE, /* pc_relative */
871 0, /* bitpos */
872 complain_overflow_dont,/* complain_on_overflow */
873 bfd_elf_generic_reloc, /* special_function */
874 "R_ARM_ABS32_NOI", /* name */
875 FALSE, /* partial_inplace */
876 0xffffffff, /* src_mask */
877 0xffffffff, /* dst_mask */
878 FALSE), /* pcrel_offset */
879
880 HOWTO (R_ARM_REL32_NOI, /* type */
881 0, /* rightshift */
882 2, /* size (0 = byte, 1 = short, 2 = long) */
883 32, /* bitsize */
884 TRUE, /* pc_relative */
885 0, /* bitpos */
886 complain_overflow_dont,/* complain_on_overflow */
887 bfd_elf_generic_reloc, /* special_function */
888 "R_ARM_REL32_NOI", /* name */
889 FALSE, /* partial_inplace */
890 0xffffffff, /* src_mask */
891 0xffffffff, /* dst_mask */
892 FALSE), /* pcrel_offset */
7f266840 893
4962c51a
MS		 894 /* Group relocations. */
895
896 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
897 0, /* rightshift */
898 2, /* size (0 = byte, 1 = short, 2 = long) */
899 32, /* bitsize */
900 TRUE, /* pc_relative */
901 0, /* bitpos */
902 complain_overflow_dont,/* complain_on_overflow */
903 bfd_elf_generic_reloc, /* special_function */
904 "R_ARM_ALU_PC_G0_NC", /* name */
905 FALSE, /* partial_inplace */
906 0xffffffff, /* src_mask */
907 0xffffffff, /* dst_mask */
908 TRUE), /* pcrel_offset */
909
07d6d2b8 910 HOWTO (R_ARM_ALU_PC_G0, /* type */
4962c51a
MS		 911 0, /* rightshift */
912 2, /* size (0 = byte, 1 = short, 2 = long) */
913 32, /* bitsize */
914 TRUE, /* pc_relative */
915 0, /* bitpos */
916 complain_overflow_dont,/* complain_on_overflow */
917 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 918 "R_ARM_ALU_PC_G0", /* name */
4962c51a
MS		 919 FALSE, /* partial_inplace */
920 0xffffffff, /* src_mask */
921 0xffffffff, /* dst_mask */
922 TRUE), /* pcrel_offset */
923
924 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
925 0, /* rightshift */
926 2, /* size (0 = byte, 1 = short, 2 = long) */
927 32, /* bitsize */
928 TRUE, /* pc_relative */
929 0, /* bitpos */
930 complain_overflow_dont,/* complain_on_overflow */
931 bfd_elf_generic_reloc, /* special_function */
932 "R_ARM_ALU_PC_G1_NC", /* name */
933 FALSE, /* partial_inplace */
934 0xffffffff, /* src_mask */
935 0xffffffff, /* dst_mask */
936 TRUE), /* pcrel_offset */
937
07d6d2b8 938 HOWTO (R_ARM_ALU_PC_G1, /* type */
4962c51a
MS		 939 0, /* rightshift */
940 2, /* size (0 = byte, 1 = short, 2 = long) */
941 32, /* bitsize */
942 TRUE, /* pc_relative */
943 0, /* bitpos */
944 complain_overflow_dont,/* complain_on_overflow */
945 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 946 "R_ARM_ALU_PC_G1", /* name */
4962c51a
MS		 947 FALSE, /* partial_inplace */
948 0xffffffff, /* src_mask */
949 0xffffffff, /* dst_mask */
950 TRUE), /* pcrel_offset */
951
07d6d2b8 952 HOWTO (R_ARM_ALU_PC_G2, /* type */
4962c51a
MS		 953 0, /* rightshift */
954 2, /* size (0 = byte, 1 = short, 2 = long) */
955 32, /* bitsize */
956 TRUE, /* pc_relative */
957 0, /* bitpos */
958 complain_overflow_dont,/* complain_on_overflow */
959 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 960 "R_ARM_ALU_PC_G2", /* name */
4962c51a
MS		 961 FALSE, /* partial_inplace */
962 0xffffffff, /* src_mask */
963 0xffffffff, /* dst_mask */
964 TRUE), /* pcrel_offset */
965
07d6d2b8 966 HOWTO (R_ARM_LDR_PC_G1, /* type */
4962c51a
MS		 967 0, /* rightshift */
968 2, /* size (0 = byte, 1 = short, 2 = long) */
969 32, /* bitsize */
970 TRUE, /* pc_relative */
971 0, /* bitpos */
972 complain_overflow_dont,/* complain_on_overflow */
973 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 974 "R_ARM_LDR_PC_G1", /* name */
4962c51a
MS		 975 FALSE, /* partial_inplace */
976 0xffffffff, /* src_mask */
977 0xffffffff, /* dst_mask */
978 TRUE), /* pcrel_offset */
979
07d6d2b8 980 HOWTO (R_ARM_LDR_PC_G2, /* type */
4962c51a
MS		 981 0, /* rightshift */
982 2, /* size (0 = byte, 1 = short, 2 = long) */
983 32, /* bitsize */
984 TRUE, /* pc_relative */
985 0, /* bitpos */
986 complain_overflow_dont,/* complain_on_overflow */
987 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 988 "R_ARM_LDR_PC_G2", /* name */
4962c51a
MS		 989 FALSE, /* partial_inplace */
990 0xffffffff, /* src_mask */
991 0xffffffff, /* dst_mask */
992 TRUE), /* pcrel_offset */
993
07d6d2b8 994 HOWTO (R_ARM_LDRS_PC_G0, /* type */
4962c51a
MS		 995 0, /* rightshift */
996 2, /* size (0 = byte, 1 = short, 2 = long) */
997 32, /* bitsize */
998 TRUE, /* pc_relative */
999 0, /* bitpos */
1000 complain_overflow_dont,/* complain_on_overflow */
1001 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1002 "R_ARM_LDRS_PC_G0", /* name */
4962c51a
MS		 1003 FALSE, /* partial_inplace */
1004 0xffffffff, /* src_mask */
1005 0xffffffff, /* dst_mask */
1006 TRUE), /* pcrel_offset */
1007
07d6d2b8 1008 HOWTO (R_ARM_LDRS_PC_G1, /* type */
4962c51a
MS		 1009 0, /* rightshift */
1010 2, /* size (0 = byte, 1 = short, 2 = long) */
1011 32, /* bitsize */
1012 TRUE, /* pc_relative */
1013 0, /* bitpos */
1014 complain_overflow_dont,/* complain_on_overflow */
1015 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1016 "R_ARM_LDRS_PC_G1", /* name */
4962c51a
MS		 1017 FALSE, /* partial_inplace */
1018 0xffffffff, /* src_mask */
1019 0xffffffff, /* dst_mask */
1020 TRUE), /* pcrel_offset */
1021
07d6d2b8 1022 HOWTO (R_ARM_LDRS_PC_G2, /* type */
4962c51a
MS		 1023 0, /* rightshift */
1024 2, /* size (0 = byte, 1 = short, 2 = long) */
1025 32, /* bitsize */
1026 TRUE, /* pc_relative */
1027 0, /* bitpos */
1028 complain_overflow_dont,/* complain_on_overflow */
1029 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1030 "R_ARM_LDRS_PC_G2", /* name */
4962c51a
MS		 1031 FALSE, /* partial_inplace */
1032 0xffffffff, /* src_mask */
1033 0xffffffff, /* dst_mask */
1034 TRUE), /* pcrel_offset */
1035
07d6d2b8 1036 HOWTO (R_ARM_LDC_PC_G0, /* type */
4962c51a
MS		 1037 0, /* rightshift */
1038 2, /* size (0 = byte, 1 = short, 2 = long) */
1039 32, /* bitsize */
1040 TRUE, /* pc_relative */
1041 0, /* bitpos */
1042 complain_overflow_dont,/* complain_on_overflow */
1043 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1044 "R_ARM_LDC_PC_G0", /* name */
4962c51a
MS		 1045 FALSE, /* partial_inplace */
1046 0xffffffff, /* src_mask */
1047 0xffffffff, /* dst_mask */
1048 TRUE), /* pcrel_offset */
1049
07d6d2b8 1050 HOWTO (R_ARM_LDC_PC_G1, /* type */
4962c51a
MS		 1051 0, /* rightshift */
1052 2, /* size (0 = byte, 1 = short, 2 = long) */
1053 32, /* bitsize */
1054 TRUE, /* pc_relative */
1055 0, /* bitpos */
1056 complain_overflow_dont,/* complain_on_overflow */
1057 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1058 "R_ARM_LDC_PC_G1", /* name */
4962c51a
MS		 1059 FALSE, /* partial_inplace */
1060 0xffffffff, /* src_mask */
1061 0xffffffff, /* dst_mask */
1062 TRUE), /* pcrel_offset */
1063
07d6d2b8 1064 HOWTO (R_ARM_LDC_PC_G2, /* type */
4962c51a
MS		 1065 0, /* rightshift */
1066 2, /* size (0 = byte, 1 = short, 2 = long) */
1067 32, /* bitsize */
1068 TRUE, /* pc_relative */
1069 0, /* bitpos */
1070 complain_overflow_dont,/* complain_on_overflow */
1071 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1072 "R_ARM_LDC_PC_G2", /* name */
4962c51a
MS		 1073 FALSE, /* partial_inplace */
1074 0xffffffff, /* src_mask */
1075 0xffffffff, /* dst_mask */
1076 TRUE), /* pcrel_offset */
1077
07d6d2b8 1078 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
4962c51a
MS		 1079 0, /* rightshift */
1080 2, /* size (0 = byte, 1 = short, 2 = long) */
1081 32, /* bitsize */
1082 TRUE, /* pc_relative */
1083 0, /* bitpos */
1084 complain_overflow_dont,/* complain_on_overflow */
1085 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1086 "R_ARM_ALU_SB_G0_NC", /* name */
4962c51a
MS		 1087 FALSE, /* partial_inplace */
1088 0xffffffff, /* src_mask */
1089 0xffffffff, /* dst_mask */
1090 TRUE), /* pcrel_offset */
1091
07d6d2b8 1092 HOWTO (R_ARM_ALU_SB_G0, /* type */
4962c51a
MS		 1093 0, /* rightshift */
1094 2, /* size (0 = byte, 1 = short, 2 = long) */
1095 32, /* bitsize */
1096 TRUE, /* pc_relative */
1097 0, /* bitpos */
1098 complain_overflow_dont,/* complain_on_overflow */
1099 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1100 "R_ARM_ALU_SB_G0", /* name */
4962c51a
MS		 1101 FALSE, /* partial_inplace */
1102 0xffffffff, /* src_mask */
1103 0xffffffff, /* dst_mask */
1104 TRUE), /* pcrel_offset */
1105
07d6d2b8 1106 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
4962c51a
MS		 1107 0, /* rightshift */
1108 2, /* size (0 = byte, 1 = short, 2 = long) */
1109 32, /* bitsize */
1110 TRUE, /* pc_relative */
1111 0, /* bitpos */
1112 complain_overflow_dont,/* complain_on_overflow */
1113 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1114 "R_ARM_ALU_SB_G1_NC", /* name */
4962c51a
MS		 1115 FALSE, /* partial_inplace */
1116 0xffffffff, /* src_mask */
1117 0xffffffff, /* dst_mask */
1118 TRUE), /* pcrel_offset */
1119
07d6d2b8 1120 HOWTO (R_ARM_ALU_SB_G1, /* type */
4962c51a
MS		 1121 0, /* rightshift */
1122 2, /* size (0 = byte, 1 = short, 2 = long) */
1123 32, /* bitsize */
1124 TRUE, /* pc_relative */
1125 0, /* bitpos */
1126 complain_overflow_dont,/* complain_on_overflow */
1127 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1128 "R_ARM_ALU_SB_G1", /* name */
4962c51a
MS		 1129 FALSE, /* partial_inplace */
1130 0xffffffff, /* src_mask */
1131 0xffffffff, /* dst_mask */
1132 TRUE), /* pcrel_offset */
1133
07d6d2b8 1134 HOWTO (R_ARM_ALU_SB_G2, /* type */
4962c51a
MS		 1135 0, /* rightshift */
1136 2, /* size (0 = byte, 1 = short, 2 = long) */
1137 32, /* bitsize */
1138 TRUE, /* pc_relative */
1139 0, /* bitpos */
1140 complain_overflow_dont,/* complain_on_overflow */
1141 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1142 "R_ARM_ALU_SB_G2", /* name */
4962c51a
MS		 1143 FALSE, /* partial_inplace */
1144 0xffffffff, /* src_mask */
1145 0xffffffff, /* dst_mask */
1146 TRUE), /* pcrel_offset */
1147
07d6d2b8 1148 HOWTO (R_ARM_LDR_SB_G0, /* type */
4962c51a
MS		 1149 0, /* rightshift */
1150 2, /* size (0 = byte, 1 = short, 2 = long) */
1151 32, /* bitsize */
1152 TRUE, /* pc_relative */
1153 0, /* bitpos */
1154 complain_overflow_dont,/* complain_on_overflow */
1155 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1156 "R_ARM_LDR_SB_G0", /* name */
4962c51a
MS		 1157 FALSE, /* partial_inplace */
1158 0xffffffff, /* src_mask */
1159 0xffffffff, /* dst_mask */
1160 TRUE), /* pcrel_offset */
1161
07d6d2b8 1162 HOWTO (R_ARM_LDR_SB_G1, /* type */
4962c51a
MS		 1163 0, /* rightshift */
1164 2, /* size (0 = byte, 1 = short, 2 = long) */
1165 32, /* bitsize */
1166 TRUE, /* pc_relative */
1167 0, /* bitpos */
1168 complain_overflow_dont,/* complain_on_overflow */
1169 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1170 "R_ARM_LDR_SB_G1", /* name */
4962c51a
MS		 1171 FALSE, /* partial_inplace */
1172 0xffffffff, /* src_mask */
1173 0xffffffff, /* dst_mask */
1174 TRUE), /* pcrel_offset */
1175
07d6d2b8 1176 HOWTO (R_ARM_LDR_SB_G2, /* type */
4962c51a
MS		 1177 0, /* rightshift */
1178 2, /* size (0 = byte, 1 = short, 2 = long) */
1179 32, /* bitsize */
1180 TRUE, /* pc_relative */
1181 0, /* bitpos */
1182 complain_overflow_dont,/* complain_on_overflow */
1183 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1184 "R_ARM_LDR_SB_G2", /* name */
4962c51a
MS		 1185 FALSE, /* partial_inplace */
1186 0xffffffff, /* src_mask */
1187 0xffffffff, /* dst_mask */
1188 TRUE), /* pcrel_offset */
1189
07d6d2b8 1190 HOWTO (R_ARM_LDRS_SB_G0, /* type */
4962c51a
MS		 1191 0, /* rightshift */
1192 2, /* size (0 = byte, 1 = short, 2 = long) */
1193 32, /* bitsize */
1194 TRUE, /* pc_relative */
1195 0, /* bitpos */
1196 complain_overflow_dont,/* complain_on_overflow */
1197 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1198 "R_ARM_LDRS_SB_G0", /* name */
4962c51a
MS		 1199 FALSE, /* partial_inplace */
1200 0xffffffff, /* src_mask */
1201 0xffffffff, /* dst_mask */
1202 TRUE), /* pcrel_offset */
1203
07d6d2b8 1204 HOWTO (R_ARM_LDRS_SB_G1, /* type */
4962c51a
MS		 1205 0, /* rightshift */
1206 2, /* size (0 = byte, 1 = short, 2 = long) */
1207 32, /* bitsize */
1208 TRUE, /* pc_relative */
1209 0, /* bitpos */
1210 complain_overflow_dont,/* complain_on_overflow */
1211 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1212 "R_ARM_LDRS_SB_G1", /* name */
4962c51a
MS		 1213 FALSE, /* partial_inplace */
1214 0xffffffff, /* src_mask */
1215 0xffffffff, /* dst_mask */
1216 TRUE), /* pcrel_offset */
1217
07d6d2b8 1218 HOWTO (R_ARM_LDRS_SB_G2, /* type */
4962c51a
MS		 1219 0, /* rightshift */
1220 2, /* size (0 = byte, 1 = short, 2 = long) */
1221 32, /* bitsize */
1222 TRUE, /* pc_relative */
1223 0, /* bitpos */
1224 complain_overflow_dont,/* complain_on_overflow */
1225 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1226 "R_ARM_LDRS_SB_G2", /* name */
4962c51a
MS		 1227 FALSE, /* partial_inplace */
1228 0xffffffff, /* src_mask */
1229 0xffffffff, /* dst_mask */
1230 TRUE), /* pcrel_offset */
1231
07d6d2b8 1232 HOWTO (R_ARM_LDC_SB_G0, /* type */
4962c51a
MS		 1233 0, /* rightshift */
1234 2, /* size (0 = byte, 1 = short, 2 = long) */
1235 32, /* bitsize */
1236 TRUE, /* pc_relative */
1237 0, /* bitpos */
1238 complain_overflow_dont,/* complain_on_overflow */
1239 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1240 "R_ARM_LDC_SB_G0", /* name */
4962c51a
MS		 1241 FALSE, /* partial_inplace */
1242 0xffffffff, /* src_mask */
1243 0xffffffff, /* dst_mask */
1244 TRUE), /* pcrel_offset */
1245
07d6d2b8 1246 HOWTO (R_ARM_LDC_SB_G1, /* type */
4962c51a
MS		 1247 0, /* rightshift */
1248 2, /* size (0 = byte, 1 = short, 2 = long) */
1249 32, /* bitsize */
1250 TRUE, /* pc_relative */
1251 0, /* bitpos */
1252 complain_overflow_dont,/* complain_on_overflow */
1253 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1254 "R_ARM_LDC_SB_G1", /* name */
4962c51a
MS		 1255 FALSE, /* partial_inplace */
1256 0xffffffff, /* src_mask */
1257 0xffffffff, /* dst_mask */
1258 TRUE), /* pcrel_offset */
1259
07d6d2b8 1260 HOWTO (R_ARM_LDC_SB_G2, /* type */
4962c51a
MS		 1261 0, /* rightshift */
1262 2, /* size (0 = byte, 1 = short, 2 = long) */
1263 32, /* bitsize */
1264 TRUE, /* pc_relative */
1265 0, /* bitpos */
1266 complain_overflow_dont,/* complain_on_overflow */
1267 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1268 "R_ARM_LDC_SB_G2", /* name */
4962c51a
MS		 1269 FALSE, /* partial_inplace */
1270 0xffffffff, /* src_mask */
1271 0xffffffff, /* dst_mask */
1272 TRUE), /* pcrel_offset */
1273
1274 /* End of group relocations. */
c19d1205 1275
c19d1205
ZW		 1276 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1277 0, /* rightshift */
1278 2, /* size (0 = byte, 1 = short, 2 = long) */
1279 16, /* bitsize */
1280 FALSE, /* pc_relative */
1281 0, /* bitpos */
1282 complain_overflow_dont,/* complain_on_overflow */
1283 bfd_elf_generic_reloc, /* special_function */
1284 "R_ARM_MOVW_BREL_NC", /* name */
1285 FALSE, /* partial_inplace */
1286 0x0000ffff, /* src_mask */
1287 0x0000ffff, /* dst_mask */
1288 FALSE), /* pcrel_offset */
1289
1290 HOWTO (R_ARM_MOVT_BREL, /* type */
1291 0, /* rightshift */
1292 2, /* size (0 = byte, 1 = short, 2 = long) */
1293 16, /* bitsize */
1294 FALSE, /* pc_relative */
1295 0, /* bitpos */
1296 complain_overflow_bitfield,/* complain_on_overflow */
1297 bfd_elf_generic_reloc, /* special_function */
1298 "R_ARM_MOVT_BREL", /* name */
1299 FALSE, /* partial_inplace */
1300 0x0000ffff, /* src_mask */
1301 0x0000ffff, /* dst_mask */
1302 FALSE), /* pcrel_offset */
1303
1304 HOWTO (R_ARM_MOVW_BREL, /* type */
1305 0, /* rightshift */
1306 2, /* size (0 = byte, 1 = short, 2 = long) */
1307 16, /* bitsize */
1308 FALSE, /* pc_relative */
1309 0, /* bitpos */
1310 complain_overflow_dont,/* complain_on_overflow */
1311 bfd_elf_generic_reloc, /* special_function */
1312 "R_ARM_MOVW_BREL", /* name */
1313 FALSE, /* partial_inplace */
1314 0x0000ffff, /* src_mask */
1315 0x0000ffff, /* dst_mask */
1316 FALSE), /* pcrel_offset */
1317
1318 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1319 0, /* rightshift */
1320 2, /* size (0 = byte, 1 = short, 2 = long) */
1321 16, /* bitsize */
1322 FALSE, /* pc_relative */
1323 0, /* bitpos */
1324 complain_overflow_dont,/* complain_on_overflow */
1325 bfd_elf_generic_reloc, /* special_function */
1326 "R_ARM_THM_MOVW_BREL_NC",/* name */
1327 FALSE, /* partial_inplace */
1328 0x040f70ff, /* src_mask */
1329 0x040f70ff, /* dst_mask */
1330 FALSE), /* pcrel_offset */
1331
1332 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1333 0, /* rightshift */
1334 2, /* size (0 = byte, 1 = short, 2 = long) */
1335 16, /* bitsize */
1336 FALSE, /* pc_relative */
1337 0, /* bitpos */
1338 complain_overflow_bitfield,/* complain_on_overflow */
1339 bfd_elf_generic_reloc, /* special_function */
1340 "R_ARM_THM_MOVT_BREL", /* name */
1341 FALSE, /* partial_inplace */
1342 0x040f70ff, /* src_mask */
1343 0x040f70ff, /* dst_mask */
1344 FALSE), /* pcrel_offset */
1345
1346 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1347 0, /* rightshift */
1348 2, /* size (0 = byte, 1 = short, 2 = long) */
1349 16, /* bitsize */
1350 FALSE, /* pc_relative */
1351 0, /* bitpos */
1352 complain_overflow_dont,/* complain_on_overflow */
1353 bfd_elf_generic_reloc, /* special_function */
1354 "R_ARM_THM_MOVW_BREL", /* name */
1355 FALSE, /* partial_inplace */
1356 0x040f70ff, /* src_mask */
1357 0x040f70ff, /* dst_mask */
1358 FALSE), /* pcrel_offset */
1359
0855e32b
NS		 1360 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1361 0, /* rightshift */
1362 2, /* size (0 = byte, 1 = short, 2 = long) */
1363 32, /* bitsize */
1364 FALSE, /* pc_relative */
1365 0, /* bitpos */
1366 complain_overflow_bitfield,/* complain_on_overflow */
1367 NULL, /* special_function */
1368 "R_ARM_TLS_GOTDESC", /* name */
1369 TRUE, /* partial_inplace */
1370 0xffffffff, /* src_mask */
1371 0xffffffff, /* dst_mask */
1372 FALSE), /* pcrel_offset */
1373
1374 HOWTO (R_ARM_TLS_CALL, /* type */
1375 0, /* rightshift */
1376 2, /* size (0 = byte, 1 = short, 2 = long) */
1377 24, /* bitsize */
1378 FALSE, /* pc_relative */
1379 0, /* bitpos */
1380 complain_overflow_dont,/* complain_on_overflow */
1381 bfd_elf_generic_reloc, /* special_function */
1382 "R_ARM_TLS_CALL", /* name */
1383 FALSE, /* partial_inplace */
1384 0x00ffffff, /* src_mask */
1385 0x00ffffff, /* dst_mask */
1386 FALSE), /* pcrel_offset */
1387
1388 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1389 0, /* rightshift */
1390 2, /* size (0 = byte, 1 = short, 2 = long) */
1391 0, /* bitsize */
1392 FALSE, /* pc_relative */
1393 0, /* bitpos */
1394 complain_overflow_bitfield,/* complain_on_overflow */
1395 bfd_elf_generic_reloc, /* special_function */
1396 "R_ARM_TLS_DESCSEQ", /* name */
1397 FALSE, /* partial_inplace */
1398 0x00000000, /* src_mask */
1399 0x00000000, /* dst_mask */
1400 FALSE), /* pcrel_offset */
1401
1402 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1403 0, /* rightshift */
1404 2, /* size (0 = byte, 1 = short, 2 = long) */
1405 24, /* bitsize */
1406 FALSE, /* pc_relative */
1407 0, /* bitpos */
1408 complain_overflow_dont,/* complain_on_overflow */
1409 bfd_elf_generic_reloc, /* special_function */
1410 "R_ARM_THM_TLS_CALL", /* name */
1411 FALSE, /* partial_inplace */
1412 0x07ff07ff, /* src_mask */
1413 0x07ff07ff, /* dst_mask */
1414 FALSE), /* pcrel_offset */
c19d1205
ZW		 1415
1416 HOWTO (R_ARM_PLT32_ABS, /* type */
1417 0, /* rightshift */
1418 2, /* size (0 = byte, 1 = short, 2 = long) */
1419 32, /* bitsize */
1420 FALSE, /* pc_relative */
1421 0, /* bitpos */
1422 complain_overflow_dont,/* complain_on_overflow */
1423 bfd_elf_generic_reloc, /* special_function */
1424 "R_ARM_PLT32_ABS", /* name */
1425 FALSE, /* partial_inplace */
1426 0xffffffff, /* src_mask */
1427 0xffffffff, /* dst_mask */
1428 FALSE), /* pcrel_offset */
1429
1430 HOWTO (R_ARM_GOT_ABS, /* type */
1431 0, /* rightshift */
1432 2, /* size (0 = byte, 1 = short, 2 = long) */
1433 32, /* bitsize */
1434 FALSE, /* pc_relative */
1435 0, /* bitpos */
1436 complain_overflow_dont,/* complain_on_overflow */
1437 bfd_elf_generic_reloc, /* special_function */
1438 "R_ARM_GOT_ABS", /* name */
1439 FALSE, /* partial_inplace */
1440 0xffffffff, /* src_mask */
1441 0xffffffff, /* dst_mask */
1442 FALSE), /* pcrel_offset */
1443
1444 HOWTO (R_ARM_GOT_PREL, /* type */
1445 0, /* rightshift */
1446 2, /* size (0 = byte, 1 = short, 2 = long) */
1447 32, /* bitsize */
1448 TRUE, /* pc_relative */
1449 0, /* bitpos */
1450 complain_overflow_dont, /* complain_on_overflow */
1451 bfd_elf_generic_reloc, /* special_function */
1452 "R_ARM_GOT_PREL", /* name */
1453 FALSE, /* partial_inplace */
1454 0xffffffff, /* src_mask */
1455 0xffffffff, /* dst_mask */
1456 TRUE), /* pcrel_offset */
1457
1458 HOWTO (R_ARM_GOT_BREL12, /* type */
1459 0, /* rightshift */
1460 2, /* size (0 = byte, 1 = short, 2 = long) */
1461 12, /* bitsize */
1462 FALSE, /* pc_relative */
1463 0, /* bitpos */
1464 complain_overflow_bitfield,/* complain_on_overflow */
1465 bfd_elf_generic_reloc, /* special_function */
1466 "R_ARM_GOT_BREL12", /* name */
1467 FALSE, /* partial_inplace */
1468 0x00000fff, /* src_mask */
1469 0x00000fff, /* dst_mask */
1470 FALSE), /* pcrel_offset */
1471
1472 HOWTO (R_ARM_GOTOFF12, /* type */
1473 0, /* rightshift */
1474 2, /* size (0 = byte, 1 = short, 2 = long) */
1475 12, /* bitsize */
1476 FALSE, /* pc_relative */
1477 0, /* bitpos */
1478 complain_overflow_bitfield,/* complain_on_overflow */
1479 bfd_elf_generic_reloc, /* special_function */
1480 "R_ARM_GOTOFF12", /* name */
1481 FALSE, /* partial_inplace */
1482 0x00000fff, /* src_mask */
1483 0x00000fff, /* dst_mask */
1484 FALSE), /* pcrel_offset */
1485
07d6d2b8 1486 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
c19d1205
ZW		 1487
1488 /* GNU extension to record C++ vtable member usage */
07d6d2b8
AM		 1489 HOWTO (R_ARM_GNU_VTENTRY, /* type */
1490 0, /* rightshift */
1491 2, /* size (0 = byte, 1 = short, 2 = long) */
1492 0, /* bitsize */
1493 FALSE, /* pc_relative */
1494 0, /* bitpos */
99059e56 1495 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8
AM		 1496 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1497 "R_ARM_GNU_VTENTRY", /* name */
1498 FALSE, /* partial_inplace */
1499 0, /* src_mask */
1500 0, /* dst_mask */
1501 FALSE), /* pcrel_offset */
c19d1205
ZW		 1502
1503 /* GNU extension to record C++ vtable hierarchy */
1504 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
07d6d2b8
AM		 1505 0, /* rightshift */
1506 2, /* size (0 = byte, 1 = short, 2 = long) */
1507 0, /* bitsize */
1508 FALSE, /* pc_relative */
1509 0, /* bitpos */
99059e56 1510 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8 1511 NULL, /* special_function */
99059e56 1512 "R_ARM_GNU_VTINHERIT", /* name */
07d6d2b8
AM		 1513 FALSE, /* partial_inplace */
1514 0, /* src_mask */
1515 0, /* dst_mask */
1516 FALSE), /* pcrel_offset */
c19d1205
ZW		 1517
1518 HOWTO (R_ARM_THM_JUMP11, /* type */
1519 1, /* rightshift */
1520 1, /* size (0 = byte, 1 = short, 2 = long) */
1521 11, /* bitsize */
1522 TRUE, /* pc_relative */
1523 0, /* bitpos */
1524 complain_overflow_signed, /* complain_on_overflow */
1525 bfd_elf_generic_reloc, /* special_function */
1526 "R_ARM_THM_JUMP11", /* name */
1527 FALSE, /* partial_inplace */
1528 0x000007ff, /* src_mask */
1529 0x000007ff, /* dst_mask */
1530 TRUE), /* pcrel_offset */
1531
1532 HOWTO (R_ARM_THM_JUMP8, /* type */
1533 1, /* rightshift */
1534 1, /* size (0 = byte, 1 = short, 2 = long) */
1535 8, /* bitsize */
1536 TRUE, /* pc_relative */
1537 0, /* bitpos */
1538 complain_overflow_signed, /* complain_on_overflow */
1539 bfd_elf_generic_reloc, /* special_function */
1540 "R_ARM_THM_JUMP8", /* name */
1541 FALSE, /* partial_inplace */
1542 0x000000ff, /* src_mask */
1543 0x000000ff, /* dst_mask */
1544 TRUE), /* pcrel_offset */
ba93b8ac 1545
c19d1205
ZW		 1546 /* TLS relocations */
1547 HOWTO (R_ARM_TLS_GD32, /* type */
07d6d2b8
AM		 1548 0, /* rightshift */
1549 2, /* size (0 = byte, 1 = short, 2 = long) */
1550 32, /* bitsize */
1551 FALSE, /* pc_relative */
1552 0, /* bitpos */
99059e56
RM		 1553 complain_overflow_bitfield,/* complain_on_overflow */
1554 NULL, /* special_function */
1555 "R_ARM_TLS_GD32", /* name */
1556 TRUE, /* partial_inplace */
1557 0xffffffff, /* src_mask */
1558 0xffffffff, /* dst_mask */
07d6d2b8 1559 FALSE), /* pcrel_offset */
ba93b8ac 1560
ba93b8ac 1561 HOWTO (R_ARM_TLS_LDM32, /* type */
07d6d2b8
AM		 1562 0, /* rightshift */
1563 2, /* size (0 = byte, 1 = short, 2 = long) */
1564 32, /* bitsize */
1565 FALSE, /* pc_relative */
1566 0, /* bitpos */
99059e56
RM		 1567 complain_overflow_bitfield,/* complain_on_overflow */
1568 bfd_elf_generic_reloc, /* special_function */
1569 "R_ARM_TLS_LDM32", /* name */
1570 TRUE, /* partial_inplace */
1571 0xffffffff, /* src_mask */
1572 0xffffffff, /* dst_mask */
07d6d2b8 1573 FALSE), /* pcrel_offset */
ba93b8ac 1574
c19d1205 1575 HOWTO (R_ARM_TLS_LDO32, /* type */
07d6d2b8
AM		 1576 0, /* rightshift */
1577 2, /* size (0 = byte, 1 = short, 2 = long) */
1578 32, /* bitsize */
1579 FALSE, /* pc_relative */
1580 0, /* bitpos */
99059e56
RM		 1581 complain_overflow_bitfield,/* complain_on_overflow */
1582 bfd_elf_generic_reloc, /* special_function */
1583 "R_ARM_TLS_LDO32", /* name */
1584 TRUE, /* partial_inplace */
1585 0xffffffff, /* src_mask */
1586 0xffffffff, /* dst_mask */
07d6d2b8 1587 FALSE), /* pcrel_offset */
ba93b8ac 1588
ba93b8ac 1589 HOWTO (R_ARM_TLS_IE32, /* type */
07d6d2b8
AM		 1590 0, /* rightshift */
1591 2, /* size (0 = byte, 1 = short, 2 = long) */
1592 32, /* bitsize */
1593 FALSE, /* pc_relative */
1594 0, /* bitpos */
99059e56
RM		 1595 complain_overflow_bitfield,/* complain_on_overflow */
1596 NULL, /* special_function */
1597 "R_ARM_TLS_IE32", /* name */
1598 TRUE, /* partial_inplace */
1599 0xffffffff, /* src_mask */
1600 0xffffffff, /* dst_mask */
07d6d2b8 1601 FALSE), /* pcrel_offset */
7f266840 1602
c19d1205 1603 HOWTO (R_ARM_TLS_LE32, /* type */
07d6d2b8
AM		 1604 0, /* rightshift */
1605 2, /* size (0 = byte, 1 = short, 2 = long) */
1606 32, /* bitsize */
1607 FALSE, /* pc_relative */
1608 0, /* bitpos */
99059e56 1609 complain_overflow_bitfield,/* complain_on_overflow */
07d6d2b8 1610 NULL, /* special_function */
99059e56
RM		 1611 "R_ARM_TLS_LE32", /* name */
1612 TRUE, /* partial_inplace */
1613 0xffffffff, /* src_mask */
1614 0xffffffff, /* dst_mask */
07d6d2b8 1615 FALSE), /* pcrel_offset */
7f266840 1616
c19d1205
ZW		 1617 HOWTO (R_ARM_TLS_LDO12, /* type */
1618 0, /* rightshift */
1619 2, /* size (0 = byte, 1 = short, 2 = long) */
1620 12, /* bitsize */
1621 FALSE, /* pc_relative */
7f266840 1622 0, /* bitpos */
c19d1205 1623 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1624 bfd_elf_generic_reloc, /* special_function */
c19d1205 1625 "R_ARM_TLS_LDO12", /* name */
7f266840 1626 FALSE, /* partial_inplace */
c19d1205
ZW		 1627 0x00000fff, /* src_mask */
1628 0x00000fff, /* dst_mask */
1629 FALSE), /* pcrel_offset */
7f266840 1630
c19d1205
ZW		 1631 HOWTO (R_ARM_TLS_LE12, /* type */
1632 0, /* rightshift */
1633 2, /* size (0 = byte, 1 = short, 2 = long) */
1634 12, /* bitsize */
1635 FALSE, /* pc_relative */
7f266840 1636 0, /* bitpos */
c19d1205 1637 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1638 bfd_elf_generic_reloc, /* special_function */
c19d1205 1639 "R_ARM_TLS_LE12", /* name */
7f266840 1640 FALSE, /* partial_inplace */
c19d1205
ZW		 1641 0x00000fff, /* src_mask */
1642 0x00000fff, /* dst_mask */
1643 FALSE), /* pcrel_offset */
7f266840 1644
c19d1205 1645 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1646 0, /* rightshift */
1647 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1648 12, /* bitsize */
1649 FALSE, /* pc_relative */
7f266840 1650 0, /* bitpos */
c19d1205 1651 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1652 bfd_elf_generic_reloc, /* special_function */
c19d1205 1653 "R_ARM_TLS_IE12GP", /* name */
7f266840 1654 FALSE, /* partial_inplace */
c19d1205
ZW		 1655 0x00000fff, /* src_mask */
1656 0x00000fff, /* dst_mask */
1657 FALSE), /* pcrel_offset */
0855e32b 1658
34e77a92 1659 /* 112-127 private relocations. */
0855e32b
NS		 1660 EMPTY_HOWTO (112),
1661 EMPTY_HOWTO (113),
1662 EMPTY_HOWTO (114),
1663 EMPTY_HOWTO (115),
1664 EMPTY_HOWTO (116),
1665 EMPTY_HOWTO (117),
1666 EMPTY_HOWTO (118),
1667 EMPTY_HOWTO (119),
1668 EMPTY_HOWTO (120),
1669 EMPTY_HOWTO (121),
1670 EMPTY_HOWTO (122),
1671 EMPTY_HOWTO (123),
1672 EMPTY_HOWTO (124),
1673 EMPTY_HOWTO (125),
1674 EMPTY_HOWTO (126),
1675 EMPTY_HOWTO (127),
34e77a92
RS		 1676
1677 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1678 EMPTY_HOWTO (128),
1679
1680 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1681 0, /* rightshift */
1682 1, /* size (0 = byte, 1 = short, 2 = long) */
1683 0, /* bitsize */
1684 FALSE, /* pc_relative */
1685 0, /* bitpos */
1686 complain_overflow_bitfield,/* complain_on_overflow */
1687 bfd_elf_generic_reloc, /* special_function */
1688 "R_ARM_THM_TLS_DESCSEQ",/* name */
1689 FALSE, /* partial_inplace */
1690 0x00000000, /* src_mask */
1691 0x00000000, /* dst_mask */
1692 FALSE), /* pcrel_offset */
72d98d16
MG		 1693 EMPTY_HOWTO (130),
1694 EMPTY_HOWTO (131),
1695 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1696 0, /* rightshift. */
1697 1, /* size (0 = byte, 1 = short, 2 = long). */
1698 16, /* bitsize. */
1699 FALSE, /* pc_relative. */
1700 0, /* bitpos. */
1701 complain_overflow_bitfield,/* complain_on_overflow. */
1702 bfd_elf_generic_reloc, /* special_function. */
1703 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1704 FALSE, /* partial_inplace. */
1705 0x00000000, /* src_mask. */
1706 0x00000000, /* dst_mask. */
1707 FALSE), /* pcrel_offset. */
1708 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1709 0, /* rightshift. */
1710 1, /* size (0 = byte, 1 = short, 2 = long). */
1711 16, /* bitsize. */
1712 FALSE, /* pc_relative. */
1713 0, /* bitpos. */
1714 complain_overflow_bitfield,/* complain_on_overflow. */
1715 bfd_elf_generic_reloc, /* special_function. */
1716 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1717 FALSE, /* partial_inplace. */
1718 0x00000000, /* src_mask. */
1719 0x00000000, /* dst_mask. */
1720 FALSE), /* pcrel_offset. */
1721 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1722 0, /* rightshift. */
1723 1, /* size (0 = byte, 1 = short, 2 = long). */
1724 16, /* bitsize. */
1725 FALSE, /* pc_relative. */
1726 0, /* bitpos. */
1727 complain_overflow_bitfield,/* complain_on_overflow. */
1728 bfd_elf_generic_reloc, /* special_function. */
1729 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1730 FALSE, /* partial_inplace. */
1731 0x00000000, /* src_mask. */
1732 0x00000000, /* dst_mask. */
1733 FALSE), /* pcrel_offset. */
1734 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1735 0, /* rightshift. */
1736 1, /* size (0 = byte, 1 = short, 2 = long). */
1737 16, /* bitsize. */
1738 FALSE, /* pc_relative. */
1739 0, /* bitpos. */
1740 complain_overflow_bitfield,/* complain_on_overflow. */
1741 bfd_elf_generic_reloc, /* special_function. */
1742 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1743 FALSE, /* partial_inplace. */
1744 0x00000000, /* src_mask. */
1745 0x00000000, /* dst_mask. */
1746 FALSE), /* pcrel_offset. */
e5d6e09e
AV		 1747 /* Relocations for Armv8.1-M Mainline. */
1748 HOWTO (R_ARM_THM_BF16, /* type. */
1749 0, /* rightshift. */
1750 1, /* size (0 = byte, 1 = short, 2 = long). */
1751 16, /* bitsize. */
1752 TRUE, /* pc_relative. */
1753 0, /* bitpos. */
1754 complain_overflow_dont,/* do not complain_on_overflow. */
1755 bfd_elf_generic_reloc, /* special_function. */
1756 "R_ARM_THM_BF16", /* name. */
1757 FALSE, /* partial_inplace. */
1758 0x001f0ffe, /* src_mask. */
1759 0x001f0ffe, /* dst_mask. */
1760 TRUE), /* pcrel_offset. */
1889da70
AV		 1761 HOWTO (R_ARM_THM_BF12, /* type. */
1762 0, /* rightshift. */
1763 1, /* size (0 = byte, 1 = short, 2 = long). */
1764 12, /* bitsize. */
1765 TRUE, /* pc_relative. */
1766 0, /* bitpos. */
1767 complain_overflow_dont,/* do not complain_on_overflow. */
1768 bfd_elf_generic_reloc, /* special_function. */
1769 "R_ARM_THM_BF12", /* name. */
1770 FALSE, /* partial_inplace. */
1771 0x00010ffe, /* src_mask. */
1772 0x00010ffe, /* dst_mask. */
1773 TRUE), /* pcrel_offset. */
1caf72a5
AV		 1774 HOWTO (R_ARM_THM_BF18, /* type. */
1775 0, /* rightshift. */
1776 1, /* size (0 = byte, 1 = short, 2 = long). */
1777 18, /* bitsize. */
1778 TRUE, /* pc_relative. */
1779 0, /* bitpos. */
1780 complain_overflow_dont,/* do not complain_on_overflow. */
1781 bfd_elf_generic_reloc, /* special_function. */
1782 "R_ARM_THM_BF18", /* name. */
1783 FALSE, /* partial_inplace. */
1784 0x007f0ffe, /* src_mask. */
1785 0x007f0ffe, /* dst_mask. */
1786 TRUE), /* pcrel_offset. */
c19d1205
ZW		 1787};
1788
34e77a92 1789/* 160 onwards: */
5c5a4843 1790static reloc_howto_type elf32_arm_howto_table_2[8] =
34e77a92
RS		 1791{
1792 HOWTO (R_ARM_IRELATIVE, /* type */
07d6d2b8
AM		 1793 0, /* rightshift */
1794 2, /* size (0 = byte, 1 = short, 2 = long) */
1795 32, /* bitsize */
1796 FALSE, /* pc_relative */
1797 0, /* bitpos */
99059e56
RM		 1798 complain_overflow_bitfield,/* complain_on_overflow */
1799 bfd_elf_generic_reloc, /* special_function */
1800 "R_ARM_IRELATIVE", /* name */
1801 TRUE, /* partial_inplace */
1802 0xffffffff, /* src_mask */
1803 0xffffffff, /* dst_mask */
188fd7ae
CL		 1804 FALSE), /* pcrel_offset */
1805 HOWTO (R_ARM_GOTFUNCDESC, /* type */
1806 0, /* rightshift */
1807 2, /* size (0 = byte, 1 = short, 2 = long) */
1808 32, /* bitsize */
1809 FALSE, /* pc_relative */
1810 0, /* bitpos */
1811 complain_overflow_bitfield,/* complain_on_overflow */
1812 bfd_elf_generic_reloc, /* special_function */
1813 "R_ARM_GOTFUNCDESC", /* name */
1814 FALSE, /* partial_inplace */
1815 0, /* src_mask */
1816 0xffffffff, /* dst_mask */
1817 FALSE), /* pcrel_offset */
1818 HOWTO (R_ARM_GOTOFFFUNCDESC, /* type */
1819 0, /* rightshift */
1820 2, /* size (0 = byte, 1 = short, 2 = long) */
1821 32, /* bitsize */
1822 FALSE, /* pc_relative */
1823 0, /* bitpos */
1824 complain_overflow_bitfield,/* complain_on_overflow */
1825 bfd_elf_generic_reloc, /* special_function */
1826 "R_ARM_GOTOFFFUNCDESC",/* name */
1827 FALSE, /* partial_inplace */
1828 0, /* src_mask */
1829 0xffffffff, /* dst_mask */
1830 FALSE), /* pcrel_offset */
1831 HOWTO (R_ARM_FUNCDESC, /* type */
1832 0, /* rightshift */
1833 2, /* size (0 = byte, 1 = short, 2 = long) */
1834 32, /* bitsize */
1835 FALSE, /* pc_relative */
1836 0, /* bitpos */
1837 complain_overflow_bitfield,/* complain_on_overflow */
1838 bfd_elf_generic_reloc, /* special_function */
1839 "R_ARM_FUNCDESC", /* name */
1840 FALSE, /* partial_inplace */
1841 0, /* src_mask */
1842 0xffffffff, /* dst_mask */
1843 FALSE), /* pcrel_offset */
1844 HOWTO (R_ARM_FUNCDESC_VALUE, /* type */
1845 0, /* rightshift */
1846 2, /* size (0 = byte, 1 = short, 2 = long) */
1847 64, /* bitsize */
1848 FALSE, /* pc_relative */
1849 0, /* bitpos */
1850 complain_overflow_bitfield,/* complain_on_overflow */
1851 bfd_elf_generic_reloc, /* special_function */
1852 "R_ARM_FUNCDESC_VALUE",/* name */
1853 FALSE, /* partial_inplace */
1854 0, /* src_mask */
1855 0xffffffff, /* dst_mask */
1856 FALSE), /* pcrel_offset */
5c5a4843
CL		 1857 HOWTO (R_ARM_TLS_GD32_FDPIC, /* type */
1858 0, /* rightshift */
1859 2, /* size (0 = byte, 1 = short, 2 = long) */
1860 32, /* bitsize */
1861 FALSE, /* pc_relative */
1862 0, /* bitpos */
1863 complain_overflow_bitfield,/* complain_on_overflow */
1864 bfd_elf_generic_reloc, /* special_function */
1865 "R_ARM_TLS_GD32_FDPIC",/* name */
1866 FALSE, /* partial_inplace */
1867 0, /* src_mask */
1868 0xffffffff, /* dst_mask */
1869 FALSE), /* pcrel_offset */
1870 HOWTO (R_ARM_TLS_LDM32_FDPIC, /* type */
1871 0, /* rightshift */
1872 2, /* size (0 = byte, 1 = short, 2 = long) */
1873 32, /* bitsize */
1874 FALSE, /* pc_relative */
1875 0, /* bitpos */
1876 complain_overflow_bitfield,/* complain_on_overflow */
1877 bfd_elf_generic_reloc, /* special_function */
1878 "R_ARM_TLS_LDM32_FDPIC",/* name */
1879 FALSE, /* partial_inplace */
1880 0, /* src_mask */
1881 0xffffffff, /* dst_mask */
1882 FALSE), /* pcrel_offset */
1883 HOWTO (R_ARM_TLS_IE32_FDPIC, /* type */
1884 0, /* rightshift */
1885 2, /* size (0 = byte, 1 = short, 2 = long) */
1886 32, /* bitsize */
1887 FALSE, /* pc_relative */
1888 0, /* bitpos */
1889 complain_overflow_bitfield,/* complain_on_overflow */
1890 bfd_elf_generic_reloc, /* special_function */
1891 "R_ARM_TLS_IE32_FDPIC",/* name */
1892 FALSE, /* partial_inplace */
1893 0, /* src_mask */
1894 0xffffffff, /* dst_mask */
1895 FALSE), /* pcrel_offset */
34e77a92 1896};
c19d1205 1897
34e77a92
RS		 1898/* 249-255 extended, currently unused, relocations: */
1899static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1900{
1901 HOWTO (R_ARM_RREL32, /* type */
1902 0, /* rightshift */
1903 0, /* size (0 = byte, 1 = short, 2 = long) */
1904 0, /* bitsize */
1905 FALSE, /* pc_relative */
1906 0, /* bitpos */
1907 complain_overflow_dont,/* complain_on_overflow */
1908 bfd_elf_generic_reloc, /* special_function */
1909 "R_ARM_RREL32", /* name */
1910 FALSE, /* partial_inplace */
1911 0, /* src_mask */
1912 0, /* dst_mask */
1913 FALSE), /* pcrel_offset */
1914
1915 HOWTO (R_ARM_RABS32, /* type */
1916 0, /* rightshift */
1917 0, /* size (0 = byte, 1 = short, 2 = long) */
1918 0, /* bitsize */
1919 FALSE, /* pc_relative */
1920 0, /* bitpos */
1921 complain_overflow_dont,/* complain_on_overflow */
1922 bfd_elf_generic_reloc, /* special_function */
1923 "R_ARM_RABS32", /* name */
1924 FALSE, /* partial_inplace */
1925 0, /* src_mask */
1926 0, /* dst_mask */
1927 FALSE), /* pcrel_offset */
1928
1929 HOWTO (R_ARM_RPC24, /* type */
1930 0, /* rightshift */
1931 0, /* size (0 = byte, 1 = short, 2 = long) */
1932 0, /* bitsize */
1933 FALSE, /* pc_relative */
1934 0, /* bitpos */
1935 complain_overflow_dont,/* complain_on_overflow */
1936 bfd_elf_generic_reloc, /* special_function */
1937 "R_ARM_RPC24", /* name */
1938 FALSE, /* partial_inplace */
1939 0, /* src_mask */
1940 0, /* dst_mask */
1941 FALSE), /* pcrel_offset */
1942
1943 HOWTO (R_ARM_RBASE, /* type */
1944 0, /* rightshift */
1945 0, /* size (0 = byte, 1 = short, 2 = long) */
1946 0, /* bitsize */
1947 FALSE, /* pc_relative */
1948 0, /* bitpos */
1949 complain_overflow_dont,/* complain_on_overflow */
1950 bfd_elf_generic_reloc, /* special_function */
1951 "R_ARM_RBASE", /* name */
1952 FALSE, /* partial_inplace */
1953 0, /* src_mask */
1954 0, /* dst_mask */
1955 FALSE) /* pcrel_offset */
1956};
1957
1958static reloc_howto_type *
1959elf32_arm_howto_from_type (unsigned int r_type)
1960{
906e58ca 1961 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1962 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1963
188fd7ae
CL		 1964 if (r_type >= R_ARM_IRELATIVE
1965 && r_type < R_ARM_IRELATIVE + ARRAY_SIZE (elf32_arm_howto_table_2))
34e77a92
RS		 1966 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1967
c19d1205 1968 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1969 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1970 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1971
c19d1205 1972 return NULL;
7f266840
DJ		 1973}
1974
f3185997
NC		 1975static bfd_boolean
1976elf32_arm_info_to_howto (bfd * abfd, arelent * bfd_reloc,
7f266840
DJ		 1977 Elf_Internal_Rela * elf_reloc)
1978{
1979 unsigned int r_type;
1980
1981 r_type = ELF32_R_TYPE (elf_reloc->r_info);
f3185997
NC		 1982 if ((bfd_reloc->howto = elf32_arm_howto_from_type (r_type)) == NULL)
1983 {
1984 /* xgettext:c-format */
1985 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
1986 abfd, r_type);
1987 bfd_set_error (bfd_error_bad_value);
1988 return FALSE;
1989 }
1990 return TRUE;
7f266840
DJ		 1991}
1992
1993struct elf32_arm_reloc_map
1994 {
1995 bfd_reloc_code_real_type bfd_reloc_val;
07d6d2b8 1996 unsigned char elf_reloc_val;
7f266840
DJ		 1997 };
1998
1999/* All entries in this list must also be present in elf32_arm_howto_table. */
2000static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
2001 {
07d6d2b8 2002 {BFD_RELOC_NONE, R_ARM_NONE},
7f266840 2003 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 2004 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
2005 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
07d6d2b8
AM		 2006 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
2007 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
2008 {BFD_RELOC_32, R_ARM_ABS32},
2009 {BFD_RELOC_32_PCREL, R_ARM_REL32},
2010 {BFD_RELOC_8, R_ARM_ABS8},
2011 {BFD_RELOC_16, R_ARM_ABS16},
2012 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
7f266840 2013 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 2014 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
2015 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
2016 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
2017 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
2018 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
2019 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
07d6d2b8
AM		 2020 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
2021 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
2022 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
2023 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
2024 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
2025 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
2026 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
2027 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
7f266840
DJ		 2028 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
2029 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
2030 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
2031 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac 2032 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
07d6d2b8
AM		 2033 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
2034 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
2035 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
0855e32b 2036 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
07d6d2b8 2037 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
0855e32b 2038 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
07d6d2b8 2039 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 2040 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
2041 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
2042 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
2043 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
2044 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
07d6d2b8
AM		 2045 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
2046 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
2047 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
2048 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
188fd7ae
CL		 2049 {BFD_RELOC_ARM_GOTFUNCDESC, R_ARM_GOTFUNCDESC},
2050 {BFD_RELOC_ARM_GOTOFFFUNCDESC, R_ARM_GOTOFFFUNCDESC},
2051 {BFD_RELOC_ARM_FUNCDESC, R_ARM_FUNCDESC},
2052 {BFD_RELOC_ARM_FUNCDESC_VALUE, R_ARM_FUNCDESC_VALUE},
5c5a4843
CL		 2053 {BFD_RELOC_ARM_TLS_GD32_FDPIC, R_ARM_TLS_GD32_FDPIC},
2054 {BFD_RELOC_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_LDM32_FDPIC},
2055 {BFD_RELOC_ARM_TLS_IE32_FDPIC, R_ARM_TLS_IE32_FDPIC},
c19d1205
ZW		 2056 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
2057 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 2058 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
2059 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
2060 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
2061 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
2062 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
2063 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
2064 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
2065 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 2066 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
2067 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
2068 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
2069 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
2070 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
2071 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
2072 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
2073 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
2074 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
2075 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
2076 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
2077 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
2078 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
2079 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
2080 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
2081 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
2082 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
2083 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
2084 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
2085 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
2086 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
2087 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
2088 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
2089 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
2090 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
2091 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
2092 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 2093 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 2094 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
2095 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
2096 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
2097 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
e5d6e09e 2098 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC},
1caf72a5 2099 {BFD_RELOC_ARM_THUMB_BF17, R_ARM_THM_BF16},
1889da70 2100 {BFD_RELOC_ARM_THUMB_BF13, R_ARM_THM_BF12},
1caf72a5 2101 {BFD_RELOC_ARM_THUMB_BF19, R_ARM_THM_BF18}
7f266840
DJ		 2102 };
2103
2104static reloc_howto_type *
f1c71a59
ZW		 2105elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2106 bfd_reloc_code_real_type code)
7f266840
DJ		 2107{
2108 unsigned int i;
8029a119 2109
906e58ca 2110 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 2111 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
2112 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 2113
c19d1205 2114 return NULL;
7f266840
DJ		 2115}
2116
157090f7
AM		 2117static reloc_howto_type *
2118elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2119 const char *r_name)
2120{
2121 unsigned int i;
2122
906e58ca 2123 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 2124 if (elf32_arm_howto_table_1[i].name != NULL
2125 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
2126 return &elf32_arm_howto_table_1[i];
2127
906e58ca 2128 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 2129 if (elf32_arm_howto_table_2[i].name != NULL
2130 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
2131 return &elf32_arm_howto_table_2[i];
2132
34e77a92
RS		 2133 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
2134 if (elf32_arm_howto_table_3[i].name != NULL
2135 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
2136 return &elf32_arm_howto_table_3[i];
2137
157090f7
AM		 2138 return NULL;
2139}
2140
906e58ca
NC		 2141/* Support for core dump NOTE sections. */
2142
7f266840 2143static bfd_boolean
f1c71a59 2144elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2145{
2146 int offset;
2147 size_t size;
2148
2149 switch (note->descsz)
2150 {
2151 default:
2152 return FALSE;
2153
8029a119 2154 case 148: /* Linux/ARM 32-bit. */
7f266840 2155 /* pr_cursig */
228e534f 2156 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2157
2158 /* pr_pid */
228e534f 2159 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2160
2161 /* pr_reg */
2162 offset = 72;
2163 size = 72;
2164
2165 break;
2166 }
2167
2168 /* Make a ".reg/999" section. */
2169 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2170 size, note->descpos + offset);
2171}
2172
2173static bfd_boolean
f1c71a59 2174elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2175{
2176 switch (note->descsz)
2177 {
2178 default:
2179 return FALSE;
2180
8029a119 2181 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2182 elf_tdata (abfd)->core->pid
4395ee08 2183 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2184 elf_tdata (abfd)->core->program
7f266840 2185 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2186 elf_tdata (abfd)->core->command
7f266840
DJ		 2187 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2188 }
2189
2190 /* Note that for some reason, a spurious space is tacked
2191 onto the end of the args in some (at least one anyway)
2192 implementations, so strip it off if it exists. */
7f266840 2193 {
228e534f 2194 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2195 int n = strlen (command);
2196
2197 if (0 < n && command[n - 1] == ' ')
2198 command[n - 1] = '\0';
2199 }
2200
2201 return TRUE;
2202}
2203
1f20dca5
UW		 2204static char *
2205elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2206 int note_type, ...)
2207{
2208 switch (note_type)
2209 {
2210 default:
2211 return NULL;
2212
2213 case NT_PRPSINFO:
2214 {
602f1657 2215 char data[124] ATTRIBUTE_NONSTRING;
1f20dca5
UW		 2216 va_list ap;
2217
2218 va_start (ap, note_type);
2219 memset (data, 0, sizeof (data));
2220 strncpy (data + 28, va_arg (ap, const char *), 16);
be3e27bb 2221#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2222 DIAGNOSTIC_PUSH;
be3e27bb 2223 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
95da9854
L		 2224 -Wstringop-truncation:
2225 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2226 */
95da9854
L		 2227 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2228#endif
1f20dca5 2229 strncpy (data + 44, va_arg (ap, const char *), 80);
be3e27bb 2230#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2231 DIAGNOSTIC_POP;
fe75810f 2232#endif
1f20dca5
UW		 2233 va_end (ap);
2234
2235 return elfcore_write_note (abfd, buf, bufsiz,
2236 "CORE", note_type, data, sizeof (data));
2237 }
2238
2239 case NT_PRSTATUS:
2240 {
2241 char data[148];
2242 va_list ap;
2243 long pid;
2244 int cursig;
2245 const void *greg;
2246
2247 va_start (ap, note_type);
2248 memset (data, 0, sizeof (data));
2249 pid = va_arg (ap, long);
2250 bfd_put_32 (abfd, pid, data + 24);
2251 cursig = va_arg (ap, int);
2252 bfd_put_16 (abfd, cursig, data + 12);
2253 greg = va_arg (ap, const void *);
2254 memcpy (data + 72, greg, 72);
2255 va_end (ap);
2256
2257 return elfcore_write_note (abfd, buf, bufsiz,
2258 "CORE", note_type, data, sizeof (data));
2259 }
2260 }
2261}
2262
07d6d2b8
AM		 2263#define TARGET_LITTLE_SYM arm_elf32_le_vec
2264#define TARGET_LITTLE_NAME "elf32-littlearm"
2265#define TARGET_BIG_SYM arm_elf32_be_vec
2266#define TARGET_BIG_NAME "elf32-bigarm"
7f266840
DJ		 2267
2268#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2269#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2270#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2271
252b5132
RH		 2272typedef unsigned long int insn32;
2273typedef unsigned short int insn16;
2274
3a4a14e9
PB		 2275/* In lieu of proper flags, assume all EABIv4 or later objects are
2276 interworkable. */
57e8b36a 2277#define INTERWORK_FLAG(abfd) \
3a4a14e9 2278 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2279 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2280 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2281
252b5132
RH		 2282/* The linker script knows the section names for placement.
2283 The entry_names are used to do simple name mangling on the stubs.
2284 Given a function name, and its type, the stub can be found. The
9b485d32 2285 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2286#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2287#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2288
2289#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2290#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2291
c7b8f16e
JB		 2292#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2293#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2294
a504d23a
LA		 2295#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2296#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2297
845b51d6
PB		 2298#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2299#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2300
7413f23f
DJ		 2301#define STUB_ENTRY_NAME "__%s_veneer"
2302
4ba2ef8f
TP		 2303#define CMSE_PREFIX "__acle_se_"
2304
4d83e8d9
CL		 2305#define CMSE_STUB_NAME ".gnu.sgstubs"
2306
252b5132
RH		 2307/* The name of the dynamic interpreter. This is put in the .interp
2308 section. */
2309#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2310
cb10292c
CL		 2311/* FDPIC default stack size. */
2312#define DEFAULT_STACK_SIZE 0x8000
2313
0855e32b 2314static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2315{
2316 0xe08e0000, /* add r0, lr, r0 */
2317 0xe5901004, /* ldr r1, [r0,#4] */
2318 0xe12fff11, /* bx r1 */
2319};
0855e32b
NS		 2320
2321static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2322{
2323 0xe52d2004, /* push {r2} */
2324 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2325 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2326 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2327 0xe081100f, /* 2: add r1, pc */
2328 0xe12fff12, /* bx r2 */
2329 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2330 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2331 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2332};
0855e32b 2333
b4e87f2c
TC		 2334/* NOTE: [Thumb nop sequence]
2335 When adding code that transitions from Thumb to Arm the instruction that
2336 should be used for the alignment padding should be 0xe7fd (b .-2) instead of
2337 a nop for performance reasons. */
2338
7801f98f
CL		 2339/* ARM FDPIC PLT entry. */
2340/* The last 5 words contain PLT lazy fragment code and data. */
2341static const bfd_vma elf32_arm_fdpic_plt_entry [] =
2342 {
2343 0xe59fc008, /* ldr r12, .L1 */
2344 0xe08cc009, /* add r12, r12, r9 */
2345 0xe59c9004, /* ldr r9, [r12, #4] */
2346 0xe59cf000, /* ldr pc, [r12] */
2347 0x00000000, /* L1. .word foo(GOTOFFFUNCDESC) */
2348 0x00000000, /* L1. .word foo(funcdesc_value_reloc_offset) */
2349 0xe51fc00c, /* ldr r12, [pc, #-12] */
2350 0xe92d1000, /* push {r12} */
2351 0xe599c004, /* ldr r12, [r9, #4] */
2352 0xe599f000, /* ldr pc, [r9] */
2353 };
2354
59029f57
CL		 2355/* Thumb FDPIC PLT entry. */
2356/* The last 5 words contain PLT lazy fragment code and data. */
2357static const bfd_vma elf32_arm_fdpic_thumb_plt_entry [] =
2358 {
2359 0xc00cf8df, /* ldr.w r12, .L1 */
2360 0x0c09eb0c, /* add.w r12, r12, r9 */
2361 0x9004f8dc, /* ldr.w r9, [r12, #4] */
2362 0xf000f8dc, /* ldr.w pc, [r12] */
2363 0x00000000, /* .L1 .word foo(GOTOFFFUNCDESC) */
2364 0x00000000, /* .L2 .word foo(funcdesc_value_reloc_offset) */
2365 0xc008f85f, /* ldr.w r12, .L2 */
2366 0xcd04f84d, /* push {r12} */
2367 0xc004f8d9, /* ldr.w r12, [r9, #4] */
2368 0xf000f8d9, /* ldr.w pc, [r9] */
2369 };
2370
5e681ec4
PB		 2371#ifdef FOUR_WORD_PLT
2372
252b5132
RH		 2373/* The first entry in a procedure linkage table looks like
2374 this. It is set up so that any shared library function that is
59f2c4e7 2375 called before the relocation has been set up calls the dynamic
9b485d32 2376 linker first. */
e5a52504 2377static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2378{
2379 0xe52de004, /* str lr, [sp, #-4]! */
2380 0xe59fe010, /* ldr lr, [pc, #16] */
2381 0xe08fe00e, /* add lr, pc, lr */
2382 0xe5bef008, /* ldr pc, [lr, #8]! */
2383};
5e681ec4
PB		 2384
2385/* Subsequent entries in a procedure linkage table look like
2386 this. */
e5a52504 2387static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2388{
2389 0xe28fc600, /* add ip, pc, #NN */
2390 0xe28cca00, /* add ip, ip, #NN */
2391 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2392 0x00000000, /* unused */
2393};
5e681ec4 2394
eed94f8f 2395#else /* not FOUR_WORD_PLT */
5e681ec4 2396
5e681ec4
PB		 2397/* The first entry in a procedure linkage table looks like
2398 this. It is set up so that any shared library function that is
2399 called before the relocation has been set up calls the dynamic
2400 linker first. */
e5a52504 2401static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb 2402{
07d6d2b8
AM		 2403 0xe52de004, /* str lr, [sp, #-4]! */
2404 0xe59fe004, /* ldr lr, [pc, #4] */
2405 0xe08fe00e, /* add lr, pc, lr */
2406 0xe5bef008, /* ldr pc, [lr, #8]! */
2407 0x00000000, /* &GOT[0] - . */
b38cadfb 2408};
252b5132 2409
1db37fe6
YG		 2410/* By default subsequent entries in a procedure linkage table look like
2411 this. Offsets that don't fit into 28 bits will cause link error. */
2412static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2413{
2414 0xe28fc600, /* add ip, pc, #0xNN00000 */
2415 0xe28cca00, /* add ip, ip, #0xNN000 */
2416 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2417};
5e681ec4 2418
1db37fe6
YG		 2419/* When explicitly asked, we'll use this "long" entry format
2420 which can cope with arbitrary displacements. */
2421static const bfd_vma elf32_arm_plt_entry_long [] =
2422{
07d6d2b8
AM		 2423 0xe28fc200, /* add ip, pc, #0xN0000000 */
2424 0xe28cc600, /* add ip, ip, #0xNN00000 */
1db37fe6
YG		 2425 0xe28cca00, /* add ip, ip, #0xNN000 */
2426 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2427};
2428
2429static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2430
eed94f8f
NC		 2431#endif /* not FOUR_WORD_PLT */
2432
2433/* The first entry in a procedure linkage table looks like this.
2434 It is set up so that any shared library function that is called before the
2435 relocation has been set up calls the dynamic linker first. */
2436static const bfd_vma elf32_thumb2_plt0_entry [] =
2437{
2438 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2439 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2440 0xf8dfb500, /* push {lr} */
2441 0x44fee008, /* ldr.w lr, [pc, #8] */
2442 /* add lr, pc */
eed94f8f 2443 0xff08f85e, /* ldr.w pc, [lr, #8]! */
07d6d2b8 2444 0x00000000, /* &GOT[0] - . */
eed94f8f
NC		 2445};
2446
2447/* Subsequent entries in a procedure linkage table for thumb only target
2448 look like this. */
2449static const bfd_vma elf32_thumb2_plt_entry [] =
2450{
2451 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2452 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2453 0x0c00f240, /* movw ip, #0xNNNN */
2454 0x0c00f2c0, /* movt ip, #0xNNNN */
2455 0xf8dc44fc, /* add ip, pc */
b4e87f2c
TC		 2456 0xe7fdf000 /* ldr.w pc, [ip] */
2457 /* b .-2 */
eed94f8f 2458};
252b5132 2459
00a97672
RS		 2460/* The format of the first entry in the procedure linkage table
2461 for a VxWorks executable. */
2462static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb 2463{
07d6d2b8
AM		 2464 0xe52dc008, /* str ip,[sp,#-8]! */
2465 0xe59fc000, /* ldr ip,[pc] */
2466 0xe59cf008, /* ldr pc,[ip,#8] */
2467 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
b38cadfb 2468};
00a97672
RS		 2469
2470/* The format of subsequent entries in a VxWorks executable. */
2471static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb 2472{
07d6d2b8
AM		 2473 0xe59fc000, /* ldr ip,[pc] */
2474 0xe59cf000, /* ldr pc,[ip] */
2475 0x00000000, /* .long @got */
2476 0xe59fc000, /* ldr ip,[pc] */
2477 0xea000000, /* b _PLT */
2478 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2479};
00a97672
RS		 2480
2481/* The format of entries in a VxWorks shared library. */
2482static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb 2483{
07d6d2b8
AM		 2484 0xe59fc000, /* ldr ip,[pc] */
2485 0xe79cf009, /* ldr pc,[ip,r9] */
2486 0x00000000, /* .long @got */
2487 0xe59fc000, /* ldr ip,[pc] */
2488 0xe599f008, /* ldr pc,[r9,#8] */
2489 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2490};
00a97672 2491
b7693d02
DJ		 2492/* An initial stub used if the PLT entry is referenced from Thumb code. */
2493#define PLT_THUMB_STUB_SIZE 4
2494static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2495{
2496 0x4778, /* bx pc */
b4e87f2c 2497 0xe7fd /* b .-2 */
b38cadfb 2498};
b7693d02 2499
e5a52504
MM		 2500/* The entries in a PLT when using a DLL-based target with multiple
2501 address spaces. */
906e58ca 2502static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb 2503{
07d6d2b8
AM		 2504 0xe51ff004, /* ldr pc, [pc, #-4] */
2505 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
b38cadfb
NC		 2506};
2507
2508/* The first entry in a procedure linkage table looks like
2509 this. It is set up so that any shared library function that is
2510 called before the relocation has been set up calls the dynamic
2511 linker first. */
2512static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2513{
2514 /* First bundle: */
2515 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2516 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2517 0xe08cc00f, /* add ip, ip, pc */
2518 0xe52dc008, /* str ip, [sp, #-8]! */
2519 /* Second bundle: */
edccdf7c
RM		 2520 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2521 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2522 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2523 0xe12fff1c, /* bx ip */
b38cadfb 2524 /* Third bundle: */
edccdf7c
RM		 2525 0xe320f000, /* nop */
2526 0xe320f000, /* nop */
2527 0xe320f000, /* nop */
b38cadfb
NC		 2528 /* .Lplt_tail: */
2529 0xe50dc004, /* str ip, [sp, #-4] */
2530 /* Fourth bundle: */
edccdf7c
RM		 2531 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2532 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2533 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2534 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2535};
2536#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2537
2538/* Subsequent entries in a procedure linkage table look like this. */
2539static const bfd_vma elf32_arm_nacl_plt_entry [] =
2540{
2541 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2542 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2543 0xe08cc00f, /* add ip, ip, pc */
2544 0xea000000, /* b .Lplt_tail */
2545};
e5a52504 2546
906e58ca
NC		 2547#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2548#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2549#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2550#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2551#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2552#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2553#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2554#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2555
461a49ca 2556enum stub_insn_type
b38cadfb
NC		 2557{
2558 THUMB16_TYPE = 1,
2559 THUMB32_TYPE,
2560 ARM_TYPE,
2561 DATA_TYPE
2562};
461a49ca 2563
48229727
JB		 2564#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2565/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2566 is inserted in arm_build_one_stub(). */
2567#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2568#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2569#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2570#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2571#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2572#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2573#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2574#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2575
2576typedef struct
2577{
07d6d2b8 2578 bfd_vma data;
b38cadfb 2579 enum stub_insn_type type;
07d6d2b8
AM		 2580 unsigned int r_type;
2581 int reloc_addend;
461a49ca
DJ		 2582} insn_sequence;
2583
b4e87f2c
TC		 2584/* See note [Thumb nop sequence] when adding a veneer. */
2585
fea2b4d6
CL		 2586/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2587 to reach the stub if necessary. */
461a49ca 2588static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb 2589{
07d6d2b8 2590 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2591 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2592};
906e58ca 2593
fea2b4d6
CL		 2594/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2595 available. */
461a49ca 2596static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb 2597{
07d6d2b8
AM		 2598 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2599 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2600 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2601};
906e58ca 2602
d3626fb0 2603/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2604static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb 2605{
07d6d2b8
AM		 2606 THUMB16_INSN (0xb401), /* push {r0} */
2607 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2608 THUMB16_INSN (0x4684), /* mov ip, r0 */
2609 THUMB16_INSN (0xbc01), /* pop {r0} */
2610 THUMB16_INSN (0x4760), /* bx ip */
2611 THUMB16_INSN (0xbf00), /* nop */
b38cadfb
NC		 2612 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2613};
906e58ca 2614
80c135e5
TP		 2615/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2616static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2617{
07d6d2b8 2618 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
80c135e5
TP		 2619 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2620};
2621
d5a67c02
AV		 2622/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2623 M-profile architectures. */
2624static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2625{
2626 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2627 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
07d6d2b8 2628 THUMB16_INSN (0x4760), /* bx ip */
d5a67c02
AV		 2629};
2630
d3626fb0
CL		 2631/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2632 allowed. */
2633static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb 2634{
07d6d2b8 2635 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2636 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2637 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2638 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2639 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2640};
d3626fb0 2641
fea2b4d6
CL		 2642/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2643 available. */
461a49ca 2644static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb 2645{
07d6d2b8 2646 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2647 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8 2648 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2649 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2650};
906e58ca 2651
fea2b4d6
CL		 2652/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2653 one, when the destination is close enough. */
461a49ca 2654static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb 2655{
07d6d2b8 2656 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2657 THUMB16_INSN (0xe7fd), /* b .-2 */
b38cadfb
NC		 2658 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2659};
c820be07 2660
cf3eccff 2661/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2662 blx to reach the stub if necessary. */
cf3eccff 2663static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb 2664{
07d6d2b8
AM		 2665 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2666 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
b38cadfb
NC		 2667 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2668};
906e58ca 2669
cf3eccff
DJ		 2670/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2671 blx to reach the stub if necessary. We can not add into pc;
2672 it is not guaranteed to mode switch (different in ARMv6 and
2673 ARMv7). */
2674static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb 2675{
07d6d2b8
AM		 2676 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2677 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2678 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2679 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2680};
cf3eccff 2681
ebe24dd4
CL		 2682/* V4T ARM -> ARM long branch stub, PIC. */
2683static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb 2684{
07d6d2b8
AM		 2685 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2686 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2687 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2688 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2689};
ebe24dd4
CL		 2690
2691/* V4T Thumb -> ARM long branch stub, PIC. */
2692static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb 2693{
07d6d2b8 2694 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2695 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2696 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2697 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
b38cadfb
NC		 2698 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2699};
ebe24dd4 2700
d3626fb0
CL		 2701/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2702 architectures. */
ebe24dd4 2703static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb 2704{
07d6d2b8
AM		 2705 THUMB16_INSN (0xb401), /* push {r0} */
2706 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2707 THUMB16_INSN (0x46fc), /* mov ip, pc */
2708 THUMB16_INSN (0x4484), /* add ip, r0 */
2709 THUMB16_INSN (0xbc01), /* pop {r0} */
2710 THUMB16_INSN (0x4760), /* bx ip */
b38cadfb
NC		 2711 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2712};
ebe24dd4 2713
d3626fb0
CL		 2714/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2715 allowed. */
2716static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb 2717{
07d6d2b8 2718 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2719 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2720 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2721 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2722 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2723 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2724};
d3626fb0 2725
0855e32b
NS		 2726/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2727 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2728static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2729{
07d6d2b8
AM		 2730 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2731 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
b38cadfb 2732 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2733};
2734
2735/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2736 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2737static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2738{
07d6d2b8 2739 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2740 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2741 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2742 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
b38cadfb 2743 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2744};
2745
7a89b94e
NC		 2746/* NaCl ARM -> ARM long branch stub. */
2747static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2748{
2749 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2750 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2751 ARM_INSN (0xe12fff1c), /* bx ip */
2752 ARM_INSN (0xe320f000), /* nop */
2753 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2754 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2755 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2756 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2757};
2758
2759/* NaCl ARM -> ARM long branch stub, PIC. */
2760static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2761{
2762 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
07d6d2b8 2763 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
7a89b94e 2764 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2765 ARM_INSN (0xe12fff1c), /* bx ip */
2766 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2767 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2768 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2769 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2770};
2771
4ba2ef8f
TP		 2772/* Stub used for transition to secure state (aka SG veneer). */
2773static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2774{
2775 THUMB32_INSN (0xe97fe97f), /* sg. */
2776 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2777};
2778
7a89b94e 2779
48229727
JB		 2780/* Cortex-A8 erratum-workaround stubs. */
2781
2782/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2783 can't use a conditional branch to reach this stub). */
2784
2785static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb 2786{
07d6d2b8 2787 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
b38cadfb
NC		 2788 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2789 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2790};
48229727
JB		 2791
2792/* Stub used for b.w and bl.w instructions. */
2793
2794static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2795{
2796 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2797};
48229727
JB		 2798
2799static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2800{
2801 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2802};
48229727
JB		 2803
2804/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2805 instruction (which switches to ARM mode) to point to this stub. Jump to the
2806 real destination using an ARM-mode branch. */
2807
2808static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2809{
2810 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2811};
48229727 2812
9553db3c
NC		 2813/* For each section group there can be a specially created linker section
2814 to hold the stubs for that group. The name of the stub section is based
2815 upon the name of another section within that group with the suffix below
2816 applied.
2817
2818 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2819 create what appeared to be a linker stub section when it actually
2820 contained user code/data. For example, consider this fragment:
b38cadfb 2821
9553db3c
NC		 2822 const char * stubborn_problems[] = { "np" };
2823
2824 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2825 section called:
2826
2827 .data.rel.local.stubborn_problems
2828
2829 This then causes problems in arm32_arm_build_stubs() as it triggers:
2830
2831 // Ignore non-stub sections.
2832 if (!strstr (stub_sec->name, STUB_SUFFIX))
2833 continue;
2834
2835 And so the section would be ignored instead of being processed. Hence
2836 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2837 C identifier. */
2838#define STUB_SUFFIX ".__stub"
906e58ca 2839
738a79f6
CL		 2840/* One entry per long/short branch stub defined above. */
2841#define DEF_STUBS \
2842 DEF_STUB(long_branch_any_any) \
2843 DEF_STUB(long_branch_v4t_arm_thumb) \
2844 DEF_STUB(long_branch_thumb_only) \
2845 DEF_STUB(long_branch_v4t_thumb_thumb) \
2846 DEF_STUB(long_branch_v4t_thumb_arm) \
2847 DEF_STUB(short_branch_v4t_thumb_arm) \
2848 DEF_STUB(long_branch_any_arm_pic) \
2849 DEF_STUB(long_branch_any_thumb_pic) \
2850 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2851 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2852 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2853 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2854 DEF_STUB(long_branch_any_tls_pic) \
2855 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2856 DEF_STUB(long_branch_arm_nacl) \
2857 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2858 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2859 DEF_STUB(a8_veneer_b_cond) \
2860 DEF_STUB(a8_veneer_b) \
2861 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2862 DEF_STUB(a8_veneer_blx) \
2863 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2864 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2865
2866#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2867enum elf32_arm_stub_type
2868{
906e58ca 2869 arm_stub_none,
738a79f6 2870 DEF_STUBS
4f4faa4d 2871 max_stub_type
738a79f6
CL		 2872};
2873#undef DEF_STUB
2874
8d9d9490
TP		 2875/* Note the first a8_veneer type. */
2876const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2877
738a79f6
CL		 2878typedef struct
2879{
d3ce72d0 2880 const insn_sequence* template_sequence;
738a79f6
CL		 2881 int template_size;
2882} stub_def;
2883
2884#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2885static const stub_def stub_definitions[] =
2886{
738a79f6
CL		 2887 {NULL, 0},
2888 DEF_STUBS
906e58ca
NC		 2889};
2890
2891struct elf32_arm_stub_hash_entry
2892{
2893 /* Base hash table entry structure. */
2894 struct bfd_hash_entry root;
2895
2896 /* The stub section. */
2897 asection *stub_sec;
2898
2899 /* Offset within stub_sec of the beginning of this stub. */
2900 bfd_vma stub_offset;
2901
2902 /* Given the symbol's value and its section we can determine its final
2903 value when building the stubs (so the stub knows where to jump). */
2904 bfd_vma target_value;
2905 asection *target_section;
2906
8d9d9490
TP		 2907 /* Same as above but for the source of the branch to the stub. Used for
2908 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2909 such, source section does not need to be recorded since Cortex-A8 erratum
2910 workaround stubs are only generated when both source and target are in the
2911 same section. */
2912 bfd_vma source_value;
48229727
JB		 2913
2914 /* The instruction which caused this stub to be generated (only valid for
2915 Cortex-A8 erratum workaround stubs at present). */
2916 unsigned long orig_insn;
2917
461a49ca 2918 /* The stub type. */
906e58ca 2919 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2920 /* Its encoding size in bytes. */
2921 int stub_size;
2922 /* Its template. */
2923 const insn_sequence *stub_template;
2924 /* The size of the template (number of entries). */
2925 int stub_template_size;
906e58ca
NC		 2926
2927 /* The symbol table entry, if any, that this was derived from. */
2928 struct elf32_arm_link_hash_entry *h;
2929
35fc36a8
RS		 2930 /* Type of branch. */
2931 enum arm_st_branch_type branch_type;
906e58ca
NC		 2932
2933 /* Where this stub is being called from, or, in the case of combined
2934 stub sections, the first input section in the group. */
2935 asection *id_sec;
7413f23f
DJ		 2936
2937 /* The name for the local symbol at the start of this stub. The
2938 stub name in the hash table has to be unique; this does not, so
2939 it can be friendlier. */
2940 char *output_name;
906e58ca
NC		 2941};
2942
e489d0ae
PB		 2943/* Used to build a map of a section. This is required for mixed-endian
2944 code/data. */
2945
2946typedef struct elf32_elf_section_map
2947{
2948 bfd_vma vma;
2949 char type;
2950}
2951elf32_arm_section_map;
2952
c7b8f16e
JB		 2953/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2954
2955typedef enum
2956{
2957 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2958 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2959 VFP11_ERRATUM_ARM_VENEER,
2960 VFP11_ERRATUM_THUMB_VENEER
2961}
2962elf32_vfp11_erratum_type;
2963
2964typedef struct elf32_vfp11_erratum_list
2965{
2966 struct elf32_vfp11_erratum_list *next;
2967 bfd_vma vma;
2968 union
2969 {
2970 struct
2971 {
2972 struct elf32_vfp11_erratum_list *veneer;
2973 unsigned int vfp_insn;
2974 } b;
2975 struct
2976 {
2977 struct elf32_vfp11_erratum_list *branch;
2978 unsigned int id;
2979 } v;
2980 } u;
2981 elf32_vfp11_erratum_type type;
2982}
2983elf32_vfp11_erratum_list;
2984
a504d23a
LA		 2985/* Information about a STM32L4XX erratum veneer, or a branch to such a
2986 veneer. */
2987typedef enum
2988{
2989 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2990 STM32L4XX_ERRATUM_VENEER
2991}
2992elf32_stm32l4xx_erratum_type;
2993
2994typedef struct elf32_stm32l4xx_erratum_list
2995{
2996 struct elf32_stm32l4xx_erratum_list *next;
2997 bfd_vma vma;
2998 union
2999 {
3000 struct
3001 {
3002 struct elf32_stm32l4xx_erratum_list *veneer;
3003 unsigned int insn;
3004 } b;
3005 struct
3006 {
3007 struct elf32_stm32l4xx_erratum_list *branch;
3008 unsigned int id;
3009 } v;
3010 } u;
3011 elf32_stm32l4xx_erratum_type type;
3012}
3013elf32_stm32l4xx_erratum_list;
3014
2468f9c9
PB		 3015typedef enum
3016{
3017 DELETE_EXIDX_ENTRY,
3018 INSERT_EXIDX_CANTUNWIND_AT_END
3019}
3020arm_unwind_edit_type;
3021
3022/* A (sorted) list of edits to apply to an unwind table. */
3023typedef struct arm_unwind_table_edit
3024{
3025 arm_unwind_edit_type type;
3026 /* Note: we sometimes want to insert an unwind entry corresponding to a
3027 section different from the one we're currently writing out, so record the
3028 (text) section this edit relates to here. */
3029 asection *linked_section;
3030 unsigned int index;
3031 struct arm_unwind_table_edit *next;
3032}
3033arm_unwind_table_edit;
3034
8e3de13a 3035typedef struct _arm_elf_section_data
e489d0ae 3036{
2468f9c9 3037 /* Information about mapping symbols. */
e489d0ae 3038 struct bfd_elf_section_data elf;
8e3de13a 3039 unsigned int mapcount;
c7b8f16e 3040 unsigned int mapsize;
e489d0ae 3041 elf32_arm_section_map *map;
2468f9c9 3042 /* Information about CPU errata. */
c7b8f16e
JB		 3043 unsigned int erratumcount;
3044 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 3045 unsigned int stm32l4xx_erratumcount;
3046 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 3047 unsigned int additional_reloc_count;
2468f9c9
PB		 3048 /* Information about unwind tables. */
3049 union
3050 {
3051 /* Unwind info attached to a text section. */
3052 struct
3053 {
3054 asection *arm_exidx_sec;
3055 } text;
3056
3057 /* Unwind info attached to an .ARM.exidx section. */
3058 struct
3059 {
3060 arm_unwind_table_edit *unwind_edit_list;
3061 arm_unwind_table_edit *unwind_edit_tail;
3062 } exidx;
3063 } u;
8e3de13a
NC		 3064}
3065_arm_elf_section_data;
e489d0ae
PB		 3066
3067#define elf32_arm_section_data(sec) \
8e3de13a 3068 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 3069
48229727
JB		 3070/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3071 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3072 so may be created multiple times: we use an array of these entries whilst
3073 relaxing which we can refresh easily, then create stubs for each potentially
3074 erratum-triggering instruction once we've settled on a solution. */
3075
b38cadfb
NC		 3076struct a8_erratum_fix
3077{
48229727
JB		 3078 bfd *input_bfd;
3079 asection *section;
3080 bfd_vma offset;
8d9d9490 3081 bfd_vma target_offset;
48229727
JB		 3082 unsigned long orig_insn;
3083 char *stub_name;
3084 enum elf32_arm_stub_type stub_type;
35fc36a8 3085 enum arm_st_branch_type branch_type;
48229727
JB		 3086};
3087
3088/* A table of relocs applied to branches which might trigger Cortex-A8
3089 erratum. */
3090
b38cadfb
NC		 3091struct a8_erratum_reloc
3092{
48229727
JB		 3093 bfd_vma from;
3094 bfd_vma destination;
92750f34
DJ		 3095 struct elf32_arm_link_hash_entry *hash;
3096 const char *sym_name;
48229727 3097 unsigned int r_type;
35fc36a8 3098 enum arm_st_branch_type branch_type;
48229727
JB		 3099 bfd_boolean non_a8_stub;
3100};
3101
ba93b8ac
DJ		 3102/* The size of the thread control block. */
3103#define TCB_SIZE 8
3104
34e77a92
RS		 3105/* ARM-specific information about a PLT entry, over and above the usual
3106 gotplt_union. */
b38cadfb
NC		 3107struct arm_plt_info
3108{
34e77a92
RS		 3109 /* We reference count Thumb references to a PLT entry separately,
3110 so that we can emit the Thumb trampoline only if needed. */
3111 bfd_signed_vma thumb_refcount;
3112
3113 /* Some references from Thumb code may be eliminated by BL->BLX
3114 conversion, so record them separately. */
3115 bfd_signed_vma maybe_thumb_refcount;
3116
3117 /* How many of the recorded PLT accesses were from non-call relocations.
3118 This information is useful when deciding whether anything takes the
3119 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3120 non-call references to the function should resolve directly to the
3121 real runtime target. */
3122 unsigned int noncall_refcount;
3123
3124 /* Since PLT entries have variable size if the Thumb prologue is
3125 used, we need to record the index into .got.plt instead of
3126 recomputing it from the PLT offset. */
3127 bfd_signed_vma got_offset;
3128};
3129
3130/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 3131struct arm_local_iplt_info
3132{
34e77a92
RS		 3133 /* The information that is usually found in the generic ELF part of
3134 the hash table entry. */
3135 union gotplt_union root;
3136
3137 /* The information that is usually found in the ARM-specific part of
3138 the hash table entry. */
3139 struct arm_plt_info arm;
3140
3141 /* A list of all potential dynamic relocations against this symbol. */
3142 struct elf_dyn_relocs *dyn_relocs;
3143};
3144
e8b09b87
CL		 3145/* Structure to handle FDPIC support for local functions. */
3146struct fdpic_local {
3147 unsigned int funcdesc_cnt;
3148 unsigned int gotofffuncdesc_cnt;
3149 int funcdesc_offset;
3150};
3151
0ffa91dd 3152struct elf_arm_obj_tdata
ba93b8ac
DJ		 3153{
3154 struct elf_obj_tdata root;
3155
3156 /* tls_type for each local got entry. */
3157 char *local_got_tls_type;
ee065d83 3158
0855e32b
NS		 3159 /* GOTPLT entries for TLS descriptors. */
3160 bfd_vma *local_tlsdesc_gotent;
3161
34e77a92
RS		 3162 /* Information for local symbols that need entries in .iplt. */
3163 struct arm_local_iplt_info **local_iplt;
3164
bf21ed78
MS		 3165 /* Zero to warn when linking objects with incompatible enum sizes. */
3166 int no_enum_size_warning;
a9dc9481
JM		 3167
3168 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3169 int no_wchar_size_warning;
e8b09b87
CL		 3170
3171 /* Maintains FDPIC counters and funcdesc info. */
3172 struct fdpic_local *local_fdpic_cnts;
ba93b8ac
DJ		 3173};
3174
0ffa91dd
NC		 3175#define elf_arm_tdata(bfd) \
3176 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 3177
0ffa91dd
NC		 3178#define elf32_arm_local_got_tls_type(bfd) \
3179 (elf_arm_tdata (bfd)->local_got_tls_type)
3180
0855e32b
NS		 3181#define elf32_arm_local_tlsdesc_gotent(bfd) \
3182 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3183
34e77a92
RS		 3184#define elf32_arm_local_iplt(bfd) \
3185 (elf_arm_tdata (bfd)->local_iplt)
3186
e8b09b87
CL		 3187#define elf32_arm_local_fdpic_cnts(bfd) \
3188 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3189
0ffa91dd
NC		 3190#define is_arm_elf(bfd) \
3191 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3192 && elf_tdata (bfd) != NULL \
4dfe6ac6 3193 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 3194
3195static bfd_boolean
3196elf32_arm_mkobject (bfd *abfd)
3197{
0ffa91dd 3198 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 3199 ARM_ELF_DATA);
ba93b8ac
DJ		 3200}
3201
ba93b8ac
DJ		 3202#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3203
e8b09b87
CL		 3204/* Structure to handle FDPIC support for extern functions. */
3205struct fdpic_global {
3206 unsigned int gotofffuncdesc_cnt;
3207 unsigned int gotfuncdesc_cnt;
3208 unsigned int funcdesc_cnt;
3209 int funcdesc_offset;
3210 int gotfuncdesc_offset;
3211};
3212
ba96a88f 3213/* Arm ELF linker hash entry. */
252b5132 3214struct elf32_arm_link_hash_entry
b38cadfb
NC		 3215{
3216 struct elf_link_hash_entry root;
252b5132 3217
b38cadfb
NC		 3218 /* Track dynamic relocs copied for this symbol. */
3219 struct elf_dyn_relocs *dyn_relocs;
b7693d02 3220
b38cadfb
NC		 3221 /* ARM-specific PLT information. */
3222 struct arm_plt_info plt;
ba93b8ac
DJ		 3223
3224#define GOT_UNKNOWN 0
3225#define GOT_NORMAL 1
3226#define GOT_TLS_GD 2
3227#define GOT_TLS_IE 4
0855e32b
NS		 3228#define GOT_TLS_GDESC 8
3229#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3230 unsigned int tls_type : 8;
34e77a92 3231
b38cadfb
NC		 3232 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3233 unsigned int is_iplt : 1;
34e77a92 3234
b38cadfb 3235 unsigned int unused : 23;
a4fd1a8e 3236
b38cadfb
NC		 3237 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3238 starting at the end of the jump table. */
3239 bfd_vma tlsdesc_got;
0855e32b 3240
b38cadfb
NC		 3241 /* The symbol marking the real symbol location for exported thumb
3242 symbols with Arm stubs. */
3243 struct elf_link_hash_entry *export_glue;
906e58ca 3244
b38cadfb 3245 /* A pointer to the most recently used stub hash entry against this
8029a119 3246 symbol. */
b38cadfb 3247 struct elf32_arm_stub_hash_entry *stub_cache;
e8b09b87
CL		 3248
3249 /* Counter for FDPIC relocations against this symbol. */
3250 struct fdpic_global fdpic_cnts;
b38cadfb 3251};
252b5132 3252
252b5132 3253/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3254#define elf32_arm_link_hash_traverse(table, func, info) \
3255 (elf_link_hash_traverse \
3256 (&(table)->root, \
b7693d02 3257 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3258 (info)))
3259
3260/* Get the ARM elf linker hash table from a link_info structure. */
3261#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3262 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3263 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3264
906e58ca
NC		 3265#define arm_stub_hash_lookup(table, string, create, copy) \
3266 ((struct elf32_arm_stub_hash_entry *) \
3267 bfd_hash_lookup ((table), (string), (create), (copy)))
3268
21d799b5
NC		 3269/* Array to keep track of which stub sections have been created, and
3270 information on stub grouping. */
3271struct map_stub
3272{
3273 /* This is the section to which stubs in the group will be
3274 attached. */
3275 asection *link_sec;
3276 /* The stub section. */
3277 asection *stub_sec;
3278};
3279
0855e32b
NS		 3280#define elf32_arm_compute_jump_table_size(htab) \
3281 ((htab)->next_tls_desc_index * 4)
3282
9b485d32 3283/* ARM ELF linker hash table. */
252b5132 3284struct elf32_arm_link_hash_table
906e58ca
NC		 3285{
3286 /* The main hash table. */
3287 struct elf_link_hash_table root;
252b5132 3288
906e58ca
NC		 3289 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3290 bfd_size_type thumb_glue_size;
252b5132 3291
906e58ca
NC		 3292 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3293 bfd_size_type arm_glue_size;
252b5132 3294
906e58ca
NC		 3295 /* The size in bytes of section containing the ARMv4 BX veneers. */
3296 bfd_size_type bx_glue_size;
845b51d6 3297
906e58ca
NC		 3298 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3299 veneer has been populated. */
3300 bfd_vma bx_glue_offset[15];
845b51d6 3301
906e58ca
NC		 3302 /* The size in bytes of the section containing glue for VFP11 erratum
3303 veneers. */
3304 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3305
a504d23a
LA		 3306 /* The size in bytes of the section containing glue for STM32L4XX erratum
3307 veneers. */
3308 bfd_size_type stm32l4xx_erratum_glue_size;
3309
48229727
JB		 3310 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3311 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3312 elf32_arm_write_section(). */
3313 struct a8_erratum_fix *a8_erratum_fixes;
3314 unsigned int num_a8_erratum_fixes;
3315
906e58ca
NC		 3316 /* An arbitrary input BFD chosen to hold the glue sections. */
3317 bfd * bfd_of_glue_owner;
ba96a88f 3318
906e58ca
NC		 3319 /* Nonzero to output a BE8 image. */
3320 int byteswap_code;
e489d0ae 3321
906e58ca
NC		 3322 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3323 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3324 int target1_is_rel;
9c504268 3325
906e58ca
NC		 3326 /* The relocation to use for R_ARM_TARGET2 relocations. */
3327 int target2_reloc;
eb043451 3328
906e58ca
NC		 3329 /* 0 = Ignore R_ARM_V4BX.
3330 1 = Convert BX to MOV PC.
3331 2 = Generate v4 interworing stubs. */
3332 int fix_v4bx;
319850b4 3333
48229727
JB		 3334 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3335 int fix_cortex_a8;
3336
2de70689
MGD		 3337 /* Whether we should fix the ARM1176 BLX immediate issue. */
3338 int fix_arm1176;
3339
906e58ca
NC		 3340 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3341 int use_blx;
33bfe774 3342
906e58ca
NC		 3343 /* What sort of code sequences we should look for which may trigger the
3344 VFP11 denorm erratum. */
3345 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3346
906e58ca
NC		 3347 /* Global counter for the number of fixes we have emitted. */
3348 int num_vfp11_fixes;
c7b8f16e 3349
a504d23a
LA		 3350 /* What sort of code sequences we should look for which may trigger the
3351 STM32L4XX erratum. */
3352 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3353
3354 /* Global counter for the number of fixes we have emitted. */
3355 int num_stm32l4xx_fixes;
3356
906e58ca
NC		 3357 /* Nonzero to force PIC branch veneers. */
3358 int pic_veneer;
27e55c4d 3359
906e58ca
NC		 3360 /* The number of bytes in the initial entry in the PLT. */
3361 bfd_size_type plt_header_size;
e5a52504 3362
906e58ca
NC		 3363 /* The number of bytes in the subsequent PLT etries. */
3364 bfd_size_type plt_entry_size;
e5a52504 3365
906e58ca
NC		 3366 /* True if the target system is VxWorks. */
3367 int vxworks_p;
00a97672 3368
906e58ca
NC		 3369 /* True if the target system is Symbian OS. */
3370 int symbian_p;
e5a52504 3371
b38cadfb
NC		 3372 /* True if the target system is Native Client. */
3373 int nacl_p;
3374
906e58ca 3375 /* True if the target uses REL relocations. */
f3185997 3376 bfd_boolean use_rel;
4e7fd91e 3377
54ddd295
TP		 3378 /* Nonzero if import library must be a secure gateway import library
3379 as per ARMv8-M Security Extensions. */
3380 int cmse_implib;
3381
0955507f
TP		 3382 /* The import library whose symbols' address must remain stable in
3383 the import library generated. */
3384 bfd *in_implib_bfd;
3385
0855e32b
NS		 3386 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3387 bfd_vma next_tls_desc_index;
3388
3389 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3390 bfd_vma num_tls_desc;
3391
906e58ca
NC		 3392 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3393 asection *srelplt2;
00a97672 3394
0855e32b
NS		 3395 /* The offset into splt of the PLT entry for the TLS descriptor
3396 resolver. Special values are 0, if not necessary (or not found
3397 to be necessary yet), and -1 if needed but not determined
3398 yet. */
3399 bfd_vma dt_tlsdesc_plt;
3400
3401 /* The offset into sgot of the GOT entry used by the PLT entry
3402 above. */
b38cadfb 3403 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3404
3405 /* Offset in .plt section of tls_arm_trampoline. */
3406 bfd_vma tls_trampoline;
3407
5c5a4843 3408 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
906e58ca
NC		 3409 union
3410 {
3411 bfd_signed_vma refcount;
3412 bfd_vma offset;
3413 } tls_ldm_got;
b7693d02 3414
87d72d41
AM		 3415 /* Small local sym cache. */
3416 struct sym_cache sym_cache;
906e58ca
NC		 3417
3418 /* For convenience in allocate_dynrelocs. */
3419 bfd * obfd;
3420
0855e32b
NS		 3421 /* The amount of space used by the reserved portion of the sgotplt
3422 section, plus whatever space is used by the jump slots. */
3423 bfd_vma sgotplt_jump_table_size;
3424
906e58ca
NC		 3425 /* The stub hash table. */
3426 struct bfd_hash_table stub_hash_table;
3427
3428 /* Linker stub bfd. */
3429 bfd *stub_bfd;
3430
3431 /* Linker call-backs. */
6bde4c52
TP		 3432 asection * (*add_stub_section) (const char *, asection *, asection *,
3433 unsigned int);
906e58ca
NC		 3434 void (*layout_sections_again) (void);
3435
3436 /* Array to keep track of which stub sections have been created, and
3437 information on stub grouping. */
21d799b5 3438 struct map_stub *stub_group;
906e58ca 3439
4ba2ef8f
TP		 3440 /* Input stub section holding secure gateway veneers. */
3441 asection *cmse_stub_sec;
3442
0955507f
TP		 3443 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3444 start to be allocated. */
3445 bfd_vma new_cmse_stub_offset;
3446
fe33d2fa 3447 /* Number of elements in stub_group. */
7292b3ac 3448 unsigned int top_id;
fe33d2fa 3449
906e58ca
NC		 3450 /* Assorted information used by elf32_arm_size_stubs. */
3451 unsigned int bfd_count;
7292b3ac 3452 unsigned int top_index;
906e58ca 3453 asection **input_list;
617a5ada
CL		 3454
3455 /* True if the target system uses FDPIC. */
3456 int fdpic_p;
e8b09b87
CL		 3457
3458 /* Fixup section. Used for FDPIC. */
3459 asection *srofixup;
906e58ca 3460};
252b5132 3461
e8b09b87
CL		 3462/* Add an FDPIC read-only fixup. */
3463static void
3464arm_elf_add_rofixup (bfd *output_bfd, asection *srofixup, bfd_vma offset)
3465{
3466 bfd_vma fixup_offset;
3467
3468 fixup_offset = srofixup->reloc_count++ * 4;
3469 BFD_ASSERT (fixup_offset < srofixup->size);
3470 bfd_put_32 (output_bfd, offset, srofixup->contents + fixup_offset);
3471}
3472
a504d23a
LA		 3473static inline int
3474ctz (unsigned int mask)
3475{
3476#if GCC_VERSION >= 3004
3477 return __builtin_ctz (mask);
3478#else
3479 unsigned int i;
3480
3481 for (i = 0; i < 8 * sizeof (mask); i++)
3482 {
3483 if (mask & 0x1)
3484 break;
3485 mask = (mask >> 1);
3486 }
3487 return i;
3488#endif
3489}
3490
3491static inline int
b25e998d 3492elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3493{
3494#if GCC_VERSION >= 3004
3495 return __builtin_popcount (mask);
3496#else
b25e998d
CG		 3497 unsigned int i;
3498 int sum = 0;
a504d23a
LA		 3499
3500 for (i = 0; i < 8 * sizeof (mask); i++)
3501 {
3502 if (mask & 0x1)
3503 sum++;
3504 mask = (mask >> 1);
3505 }
3506 return sum;
3507#endif
3508}
3509
e8b09b87
CL		 3510static void elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
3511 asection *sreloc, Elf_Internal_Rela *rel);
3512
3513static void
3514arm_elf_fill_funcdesc(bfd *output_bfd,
3515 struct bfd_link_info *info,
3516 int *funcdesc_offset,
3517 int dynindx,
3518 int offset,
3519 bfd_vma addr,
3520 bfd_vma dynreloc_value,
3521 bfd_vma seg)
3522{
3523 if ((*funcdesc_offset & 1) == 0)
3524 {
3525 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
3526 asection *sgot = globals->root.sgot;
3527
3528 if (bfd_link_pic(info))
3529 {
3530 asection *srelgot = globals->root.srelgot;
3531 Elf_Internal_Rela outrel;
3532
3533 outrel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
3534 outrel.r_offset = sgot->output_section->vma + sgot->output_offset + offset;
3535 outrel.r_addend = 0;
3536
3537 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
3538 bfd_put_32 (output_bfd, addr, sgot->contents + offset);
3539 bfd_put_32 (output_bfd, seg, sgot->contents + offset + 4);
3540 }
3541 else
3542 {
3543 struct elf_link_hash_entry *hgot = globals->root.hgot;
3544 bfd_vma got_value = hgot->root.u.def.value
3545 + hgot->root.u.def.section->output_section->vma
3546 + hgot->root.u.def.section->output_offset;
3547
3548 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3549 sgot->output_section->vma + sgot->output_offset
3550 + offset);
3551 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3552 sgot->output_section->vma + sgot->output_offset
3553 + offset + 4);
3554 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + offset);
3555 bfd_put_32 (output_bfd, got_value, sgot->contents + offset + 4);
3556 }
3557 *funcdesc_offset |= 1;
3558 }
3559}
3560
780a67af
NC		 3561/* Create an entry in an ARM ELF linker hash table. */
3562
3563static struct bfd_hash_entry *
57e8b36a 3564elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3565 struct bfd_hash_table * table,
3566 const char * string)
780a67af
NC		 3567{
3568 struct elf32_arm_link_hash_entry * ret =
3569 (struct elf32_arm_link_hash_entry *) entry;
3570
3571 /* Allocate the structure if it has not already been allocated by a
3572 subclass. */
906e58ca 3573 if (ret == NULL)
21d799b5 3574 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3575 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3576 if (ret == NULL)
780a67af
NC		 3577 return (struct bfd_hash_entry *) ret;
3578
3579 /* Call the allocation method of the superclass. */
3580 ret = ((struct elf32_arm_link_hash_entry *)
3581 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3582 table, string));
57e8b36a 3583 if (ret != NULL)
b7693d02 3584 {
0bdcacaf 3585 ret->dyn_relocs = NULL;
ba93b8ac 3586 ret->tls_type = GOT_UNKNOWN;
0855e32b 3587 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3588 ret->plt.thumb_refcount = 0;
3589 ret->plt.maybe_thumb_refcount = 0;
3590 ret->plt.noncall_refcount = 0;
3591 ret->plt.got_offset = -1;
3592 ret->is_iplt = FALSE;
a4fd1a8e 3593 ret->export_glue = NULL;
906e58ca
NC		 3594
3595 ret->stub_cache = NULL;
e8b09b87
CL		 3596
3597 ret->fdpic_cnts.gotofffuncdesc_cnt = 0;
3598 ret->fdpic_cnts.gotfuncdesc_cnt = 0;
3599 ret->fdpic_cnts.funcdesc_cnt = 0;
3600 ret->fdpic_cnts.funcdesc_offset = -1;
3601 ret->fdpic_cnts.gotfuncdesc_offset = -1;
b7693d02 3602 }
780a67af
NC		 3603
3604 return (struct bfd_hash_entry *) ret;
3605}
3606
34e77a92
RS		 3607/* Ensure that we have allocated bookkeeping structures for ABFD's local
3608 symbols. */
3609
3610static bfd_boolean
3611elf32_arm_allocate_local_sym_info (bfd *abfd)
3612{
3613 if (elf_local_got_refcounts (abfd) == NULL)
3614 {
3615 bfd_size_type num_syms;
3616 bfd_size_type size;
3617 char *data;
3618
3619 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3620 size = num_syms * (sizeof (bfd_signed_vma)
3621 + sizeof (struct arm_local_iplt_info *)
3622 + sizeof (bfd_vma)
e8b09b87
CL		 3623 + sizeof (char)
3624 + sizeof (struct fdpic_local));
34e77a92
RS		 3625 data = bfd_zalloc (abfd, size);
3626 if (data == NULL)
3627 return FALSE;
3628
e8b09b87
CL		 3629 elf32_arm_local_fdpic_cnts (abfd) = (struct fdpic_local *) data;
3630 data += num_syms * sizeof (struct fdpic_local);
3631
34e77a92
RS		 3632 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3633 data += num_syms * sizeof (bfd_signed_vma);
3634
3635 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3636 data += num_syms * sizeof (struct arm_local_iplt_info *);
3637
3638 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3639 data += num_syms * sizeof (bfd_vma);
3640
3641 elf32_arm_local_got_tls_type (abfd) = data;
3642 }
3643 return TRUE;
3644}
3645
3646/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3647 to input bfd ABFD. Create the information if it doesn't already exist.
3648 Return null if an allocation fails. */
3649
3650static struct arm_local_iplt_info *
3651elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3652{
3653 struct arm_local_iplt_info **ptr;
3654
3655 if (!elf32_arm_allocate_local_sym_info (abfd))
3656 return NULL;
3657
3658 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3659 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3660 if (*ptr == NULL)
3661 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3662 return *ptr;
3663}
3664
3665/* Try to obtain PLT information for the symbol with index R_SYMNDX
3666 in ABFD's symbol table. If the symbol is global, H points to its
3667 hash table entry, otherwise H is null.
3668
3669 Return true if the symbol does have PLT information. When returning
3670 true, point *ROOT_PLT at the target-independent reference count/offset
3671 union and *ARM_PLT at the ARM-specific information. */
3672
3673static bfd_boolean
4ba2ef8f
TP		 3674elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3675 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3676 unsigned long r_symndx, union gotplt_union **root_plt,
3677 struct arm_plt_info **arm_plt)
3678{
3679 struct arm_local_iplt_info *local_iplt;
3680
4ba2ef8f
TP		 3681 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3682 return FALSE;
3683
34e77a92
RS		 3684 if (h != NULL)
3685 {
3686 *root_plt = &h->root.plt;
3687 *arm_plt = &h->plt;
3688 return TRUE;
3689 }
3690
3691 if (elf32_arm_local_iplt (abfd) == NULL)
3692 return FALSE;
3693
3694 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3695 if (local_iplt == NULL)
3696 return FALSE;
3697
3698 *root_plt = &local_iplt->root;
3699 *arm_plt = &local_iplt->arm;
3700 return TRUE;
3701}
3702
59029f57
CL		 3703static bfd_boolean using_thumb_only (struct elf32_arm_link_hash_table *globals);
3704
34e77a92
RS		 3705/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3706 before it. */
3707
3708static bfd_boolean
3709elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3710 struct arm_plt_info *arm_plt)
3711{
3712 struct elf32_arm_link_hash_table *htab;
3713
3714 htab = elf32_arm_hash_table (info);
59029f57
CL		 3715
3716 return (!using_thumb_only(htab) && (arm_plt->thumb_refcount != 0
3717 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0)));
34e77a92
RS		 3718}
3719
3720/* Return a pointer to the head of the dynamic reloc list that should
3721 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3722 ABFD's symbol table. Return null if an error occurs. */
3723
3724static struct elf_dyn_relocs **
3725elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3726 Elf_Internal_Sym *isym)
3727{
3728 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3729 {
3730 struct arm_local_iplt_info *local_iplt;
3731
3732 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3733 if (local_iplt == NULL)
3734 return NULL;
3735 return &local_iplt->dyn_relocs;
3736 }
3737 else
3738 {
3739 /* Track dynamic relocs needed for local syms too.
3740 We really need local syms available to do this
3741 easily. Oh well. */
3742 asection *s;
3743 void *vpp;
3744
3745 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3746 if (s == NULL)
3747 abort ();
3748
3749 vpp = &elf_section_data (s)->local_dynrel;
3750 return (struct elf_dyn_relocs **) vpp;
3751 }
3752}
3753
906e58ca
NC		 3754/* Initialize an entry in the stub hash table. */
3755
3756static struct bfd_hash_entry *
3757stub_hash_newfunc (struct bfd_hash_entry *entry,
3758 struct bfd_hash_table *table,
3759 const char *string)
3760{
3761 /* Allocate the structure if it has not already been allocated by a
3762 subclass. */
3763 if (entry == NULL)
3764 {
21d799b5 3765 entry = (struct bfd_hash_entry *)
99059e56 3766 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3767 if (entry == NULL)
3768 return entry;
3769 }
3770
3771 /* Call the allocation method of the superclass. */
3772 entry = bfd_hash_newfunc (entry, table, string);
3773 if (entry != NULL)
3774 {
3775 struct elf32_arm_stub_hash_entry *eh;
3776
3777 /* Initialize the local fields. */
3778 eh = (struct elf32_arm_stub_hash_entry *) entry;
3779 eh->stub_sec = NULL;
0955507f 3780 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3781 eh->source_value = 0;
906e58ca
NC		 3782 eh->target_value = 0;
3783 eh->target_section = NULL;
cedfb179 3784 eh->orig_insn = 0;
906e58ca 3785 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3786 eh->stub_size = 0;
3787 eh->stub_template = NULL;
0955507f 3788 eh->stub_template_size = -1;
906e58ca
NC		 3789 eh->h = NULL;
3790 eh->id_sec = NULL;
d8d2f433 3791 eh->output_name = NULL;
906e58ca
NC		 3792 }
3793
3794 return entry;
3795}
3796
00a97672 3797/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3798 shortcuts to them in our hash table. */
3799
3800static bfd_boolean
57e8b36a 3801create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3802{
3803 struct elf32_arm_link_hash_table *htab;
3804
e5a52504 3805 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3806 if (htab == NULL)
3807 return FALSE;
3808
e5a52504
MM		 3809 /* BPABI objects never have a GOT, or associated sections. */
3810 if (htab->symbian_p)
3811 return TRUE;
3812
5e681ec4
PB		 3813 if (! _bfd_elf_create_got_section (dynobj, info))
3814 return FALSE;
3815
e8b09b87
CL		 3816 /* Also create .rofixup. */
3817 if (htab->fdpic_p)
3818 {
3819 htab->srofixup = bfd_make_section_with_flags (dynobj, ".rofixup",
3820 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS
3821 | SEC_IN_MEMORY | SEC_LINKER_CREATED | SEC_READONLY));
fd361982
AM		 3822 if (htab->srofixup == NULL
3823 || !bfd_set_section_alignment (htab->srofixup, 2))
e8b09b87
CL		 3824 return FALSE;
3825 }
3826
5e681ec4
PB		 3827 return TRUE;
3828}
3829
34e77a92
RS		 3830/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3831
3832static bfd_boolean
3833create_ifunc_sections (struct bfd_link_info *info)
3834{
3835 struct elf32_arm_link_hash_table *htab;
3836 const struct elf_backend_data *bed;
3837 bfd *dynobj;
3838 asection *s;
3839 flagword flags;
b38cadfb 3840
34e77a92
RS		 3841 htab = elf32_arm_hash_table (info);
3842 dynobj = htab->root.dynobj;
3843 bed = get_elf_backend_data (dynobj);
3844 flags = bed->dynamic_sec_flags;
3845
3846 if (htab->root.iplt == NULL)
3847 {
3d4d4302
AM		 3848 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3849 flags | SEC_READONLY | SEC_CODE);
34e77a92 3850 if (s == NULL
fd361982 3851 || !bfd_set_section_alignment (s, bed->plt_alignment))
34e77a92
RS		 3852 return FALSE;
3853 htab->root.iplt = s;
3854 }
3855
3856 if (htab->root.irelplt == NULL)
3857 {
3d4d4302
AM		 3858 s = bfd_make_section_anyway_with_flags (dynobj,
3859 RELOC_SECTION (htab, ".iplt"),
3860 flags | SEC_READONLY);
34e77a92 3861 if (s == NULL
fd361982 3862 || !bfd_set_section_alignment (s, bed->s->log_file_align))
34e77a92
RS		 3863 return FALSE;
3864 htab->root.irelplt = s;
3865 }
3866
3867 if (htab->root.igotplt == NULL)
3868 {
3d4d4302 3869 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92 3870 if (s == NULL
fd361982 3871 || !bfd_set_section_alignment (s, bed->s->log_file_align))
34e77a92
RS		 3872 return FALSE;
3873 htab->root.igotplt = s;
3874 }
3875 return TRUE;
3876}
3877
eed94f8f
NC		 3878/* Determine if we're dealing with a Thumb only architecture. */
3879
3880static bfd_boolean
3881using_thumb_only (struct elf32_arm_link_hash_table *globals)
3882{
2fd158eb
TP		 3883 int arch;
3884 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3885 Tag_CPU_arch_profile);
eed94f8f 3886
2fd158eb
TP		 3887 if (profile)
3888 return profile == 'M';
eed94f8f 3889
2fd158eb 3890 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3891
60a019a0 3892 /* Force return logic to be reviewed for each new architecture. */
031254f2 3893 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0 3894
2fd158eb
TP		 3895 if (arch == TAG_CPU_ARCH_V6_M
3896 || arch == TAG_CPU_ARCH_V6S_M
3897 || arch == TAG_CPU_ARCH_V7E_M
3898 || arch == TAG_CPU_ARCH_V8M_BASE
031254f2
AV		 3899 || arch == TAG_CPU_ARCH_V8M_MAIN
3900 || arch == TAG_CPU_ARCH_V8_1M_MAIN)
2fd158eb 3901 return TRUE;
eed94f8f 3902
2fd158eb 3903 return FALSE;
eed94f8f
NC		 3904}
3905
3906/* Determine if we're dealing with a Thumb-2 object. */
3907
3908static bfd_boolean
3909using_thumb2 (struct elf32_arm_link_hash_table *globals)
3910{
60a019a0
TP		 3911 int arch;
3912 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3913 Tag_THUMB_ISA_use);
3914
3915 if (thumb_isa)
3916 return thumb_isa == 2;
3917
3918 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3919
3920 /* Force return logic to be reviewed for each new architecture. */
031254f2 3921 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 3922
3923 return (arch == TAG_CPU_ARCH_V6T2
3924 || arch == TAG_CPU_ARCH_V7
3925 || arch == TAG_CPU_ARCH_V7E_M
3926 || arch == TAG_CPU_ARCH_V8
bff0500d 3927 || arch == TAG_CPU_ARCH_V8R
031254f2
AV		 3928 || arch == TAG_CPU_ARCH_V8M_MAIN
3929 || arch == TAG_CPU_ARCH_V8_1M_MAIN);
eed94f8f
NC		 3930}
3931
5e866f5a
TP		 3932/* Determine whether Thumb-2 BL instruction is available. */
3933
3934static bfd_boolean
3935using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3936{
3937 int arch =
3938 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3939
3940 /* Force return logic to be reviewed for each new architecture. */
031254f2 3941 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
5e866f5a
TP		 3942
3943 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3944 return (arch == TAG_CPU_ARCH_V6T2
3945 || arch >= TAG_CPU_ARCH_V7);
3946}
3947
00a97672
RS		 3948/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3949 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3950 hash table. */
3951
3952static bfd_boolean
57e8b36a 3953elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3954{
3955 struct elf32_arm_link_hash_table *htab;
3956
3957 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3958 if (htab == NULL)
3959 return FALSE;
3960
362d30a1 3961 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3962 return FALSE;
3963
3964 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3965 return FALSE;
3966
00a97672
RS		 3967 if (htab->vxworks_p)
3968 {
3969 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3970 return FALSE;
3971
0e1862bb 3972 if (bfd_link_pic (info))
00a97672
RS		 3973 {
3974 htab->plt_header_size = 0;
3975 htab->plt_entry_size
3976 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3977 }
3978 else
3979 {
3980 htab->plt_header_size
3981 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3982 htab->plt_entry_size
3983 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3984 }
aebf9be7
NC		 3985
3986 if (elf_elfheader (dynobj))
3987 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3988 }
eed94f8f
NC		 3989 else
3990 {
3991 /* PR ld/16017
3992 Test for thumb only architectures. Note - we cannot just call
3993 using_thumb_only() as the attributes in the output bfd have not been
3994 initialised at this point, so instead we use the input bfd. */
3995 bfd * saved_obfd = htab->obfd;
3996
3997 htab->obfd = dynobj;
3998 if (using_thumb_only (htab))
3999 {
4000 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
4001 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
4002 }
4003 htab->obfd = saved_obfd;
4004 }
5e681ec4 4005
7801f98f
CL		 4006 if (htab->fdpic_p) {
4007 htab->plt_header_size = 0;
4008 if (info->flags & DF_BIND_NOW)
4009 htab->plt_entry_size = 4 * (ARRAY_SIZE(elf32_arm_fdpic_plt_entry) - 5);
4010 else
4011 htab->plt_entry_size = 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry);
4012 }
4013
362d30a1
RS		 4014 if (!htab->root.splt
4015 || !htab->root.srelplt
9d19e4fd
AM		 4016 || !htab->root.sdynbss
4017 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 4018 abort ();
4019
4020 return TRUE;
4021}
4022
906e58ca
NC		 4023/* Copy the extra info we tack onto an elf_link_hash_entry. */
4024
4025static void
4026elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
4027 struct elf_link_hash_entry *dir,
4028 struct elf_link_hash_entry *ind)
4029{
4030 struct elf32_arm_link_hash_entry *edir, *eind;
4031
4032 edir = (struct elf32_arm_link_hash_entry *) dir;
4033 eind = (struct elf32_arm_link_hash_entry *) ind;
4034
0bdcacaf 4035 if (eind->dyn_relocs != NULL)
906e58ca 4036 {
0bdcacaf 4037 if (edir->dyn_relocs != NULL)
906e58ca 4038 {
0bdcacaf
RS		 4039 struct elf_dyn_relocs **pp;
4040 struct elf_dyn_relocs *p;
906e58ca
NC		 4041
4042 /* Add reloc counts against the indirect sym to the direct sym
4043 list. Merge any entries against the same section. */
0bdcacaf 4044 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 4045 {
0bdcacaf 4046 struct elf_dyn_relocs *q;
906e58ca 4047
0bdcacaf
RS		 4048 for (q = edir->dyn_relocs; q != NULL; q = q->next)
4049 if (q->sec == p->sec)
906e58ca
NC		 4050 {
4051 q->pc_count += p->pc_count;
4052 q->count += p->count;
4053 *pp = p->next;
4054 break;
4055 }
4056 if (q == NULL)
4057 pp = &p->next;
4058 }
0bdcacaf 4059 *pp = edir->dyn_relocs;
906e58ca
NC		 4060 }
4061
0bdcacaf
RS		 4062 edir->dyn_relocs = eind->dyn_relocs;
4063 eind->dyn_relocs = NULL;
906e58ca
NC		 4064 }
4065
4066 if (ind->root.type == bfd_link_hash_indirect)
4067 {
4068 /* Copy over PLT info. */
34e77a92
RS		 4069 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
4070 eind->plt.thumb_refcount = 0;
4071 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
4072 eind->plt.maybe_thumb_refcount = 0;
4073 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
4074 eind->plt.noncall_refcount = 0;
4075
e8b09b87
CL		 4076 /* Copy FDPIC counters. */
4077 edir->fdpic_cnts.gotofffuncdesc_cnt += eind->fdpic_cnts.gotofffuncdesc_cnt;
4078 edir->fdpic_cnts.gotfuncdesc_cnt += eind->fdpic_cnts.gotfuncdesc_cnt;
4079 edir->fdpic_cnts.funcdesc_cnt += eind->fdpic_cnts.funcdesc_cnt;
4080
34e77a92
RS		 4081 /* We should only allocate a function to .iplt once the final
4082 symbol information is known. */
4083 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 4084
4085 if (dir->got.refcount <= 0)
4086 {
4087 edir->tls_type = eind->tls_type;
4088 eind->tls_type = GOT_UNKNOWN;
4089 }
4090 }
4091
4092 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
4093}
4094
68faa637
AM		 4095/* Destroy an ARM elf linker hash table. */
4096
4097static void
d495ab0d 4098elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 4099{
4100 struct elf32_arm_link_hash_table *ret
d495ab0d 4101 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 4102
4103 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 4104 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 4105}
4106
906e58ca
NC		 4107/* Create an ARM elf linker hash table. */
4108
4109static struct bfd_link_hash_table *
4110elf32_arm_link_hash_table_create (bfd *abfd)
4111{
4112 struct elf32_arm_link_hash_table *ret;
4113 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
4114
7bf52ea2 4115 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 4116 if (ret == NULL)
4117 return NULL;
4118
4119 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
4120 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 4121 sizeof (struct elf32_arm_link_hash_entry),
4122 ARM_ELF_DATA))
906e58ca
NC		 4123 {
4124 free (ret);
4125 return NULL;
4126 }
4127
906e58ca 4128 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 4129 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 4130#ifdef FOUR_WORD_PLT
4131 ret->plt_header_size = 16;
4132 ret->plt_entry_size = 16;
4133#else
4134 ret->plt_header_size = 20;
1db37fe6 4135 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 4136#endif
f3185997 4137 ret->use_rel = TRUE;
906e58ca 4138 ret->obfd = abfd;
617a5ada 4139 ret->fdpic_p = 0;
906e58ca
NC		 4140
4141 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
4142 sizeof (struct elf32_arm_stub_hash_entry)))
4143 {
d495ab0d 4144 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 4145 return NULL;
4146 }
d495ab0d 4147 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 4148
4149 return &ret->root.root;
4150}
4151
cd1dac3d
DG		 4152/* Determine what kind of NOPs are available. */
4153
4154static bfd_boolean
4155arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
4156{
4157 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
4158 Tag_CPU_arch);
cd1dac3d 4159
60a019a0 4160 /* Force return logic to be reviewed for each new architecture. */
031254f2 4161 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 4162
4163 return (arch == TAG_CPU_ARCH_V6T2
4164 || arch == TAG_CPU_ARCH_V6K
4165 || arch == TAG_CPU_ARCH_V7
bff0500d
TP		 4166 || arch == TAG_CPU_ARCH_V8
4167 || arch == TAG_CPU_ARCH_V8R);
cd1dac3d
DG		 4168}
4169
f4ac8484
DJ		 4170static bfd_boolean
4171arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
4172{
4173 switch (stub_type)
4174 {
fea2b4d6 4175 case arm_stub_long_branch_thumb_only:
80c135e5 4176 case arm_stub_long_branch_thumb2_only:
d5a67c02 4177 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 4178 case arm_stub_long_branch_v4t_thumb_arm:
4179 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 4180 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 4181 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 4182 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 4183 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 4184 return TRUE;
4185 case arm_stub_none:
4186 BFD_FAIL ();
4187 return FALSE;
4188 break;
4189 default:
4190 return FALSE;
4191 }
4192}
4193
906e58ca
NC		 4194/* Determine the type of stub needed, if any, for a call. */
4195
4196static enum elf32_arm_stub_type
4197arm_type_of_stub (struct bfd_link_info *info,
4198 asection *input_sec,
4199 const Elf_Internal_Rela *rel,
34e77a92 4200 unsigned char st_type,
35fc36a8 4201 enum arm_st_branch_type *actual_branch_type,
906e58ca 4202 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 4203 bfd_vma destination,
4204 asection *sym_sec,
4205 bfd *input_bfd,
4206 const char *name)
906e58ca
NC		 4207{
4208 bfd_vma location;
4209 bfd_signed_vma branch_offset;
4210 unsigned int r_type;
4211 struct elf32_arm_link_hash_table * globals;
5e866f5a 4212 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 4213 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 4214 int use_plt = 0;
35fc36a8 4215 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 4216 union gotplt_union *root_plt;
4217 struct arm_plt_info *arm_plt;
d5a67c02
AV		 4218 int arch;
4219 int thumb2_movw;
906e58ca 4220
35fc36a8 4221 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 4222 return stub_type;
4223
906e58ca 4224 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4225 if (globals == NULL)
4226 return stub_type;
906e58ca
NC		 4227
4228 thumb_only = using_thumb_only (globals);
906e58ca 4229 thumb2 = using_thumb2 (globals);
5e866f5a 4230 thumb2_bl = using_thumb2_bl (globals);
906e58ca 4231
d5a67c02
AV		 4232 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
4233
4234 /* True for architectures that implement the thumb2 movw instruction. */
4235 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
4236
906e58ca
NC		 4237 /* Determine where the call point is. */
4238 location = (input_sec->output_offset
4239 + input_sec->output_section->vma
4240 + rel->r_offset);
4241
906e58ca
NC		 4242 r_type = ELF32_R_TYPE (rel->r_info);
4243
39f21624
NC		 4244 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4245 are considering a function call relocation. */
c5423981 4246 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
07d6d2b8 4247 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 4248 && branch_type == ST_BRANCH_TO_ARM)
4249 branch_type = ST_BRANCH_TO_THUMB;
4250
34e77a92
RS		 4251 /* For TLS call relocs, it is the caller's responsibility to provide
4252 the address of the appropriate trampoline. */
4253 if (r_type != R_ARM_TLS_CALL
4254 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 4255 && elf32_arm_get_plt_info (input_bfd, globals, hash,
4256 ELF32_R_SYM (rel->r_info), &root_plt,
4257 &arm_plt)
34e77a92 4258 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 4259 {
34e77a92 4260 asection *splt;
fe33d2fa 4261
34e77a92
RS		 4262 if (hash == NULL || hash->is_iplt)
4263 splt = globals->root.iplt;
4264 else
4265 splt = globals->root.splt;
4266 if (splt != NULL)
b38cadfb 4267 {
34e77a92
RS		 4268 use_plt = 1;
4269
4270 /* Note when dealing with PLT entries: the main PLT stub is in
4271 ARM mode, so if the branch is in Thumb mode, another
4272 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 4273 PLT stub. If a long branch stub is needed, we'll add a
4274 Thumb->Arm one and branch directly to the ARM PLT entry.
4275 Here, we have to check if a pre-PLT Thumb->ARM stub
4276 is needed and if it will be close enough. */
34e77a92
RS		 4277
4278 destination = (splt->output_section->vma
4279 + splt->output_offset
4280 + root_plt->offset);
4281 st_type = STT_FUNC;
2df2751d
CL		 4282
4283 /* Thumb branch/call to PLT: it can become a branch to ARM
4284 or to Thumb. We must perform the same checks and
4285 corrections as in elf32_arm_final_link_relocate. */
4286 if ((r_type == R_ARM_THM_CALL)
4287 || (r_type == R_ARM_THM_JUMP24))
4288 {
4289 if (globals->use_blx
4290 && r_type == R_ARM_THM_CALL
4291 && !thumb_only)
4292 {
4293 /* If the Thumb BLX instruction is available, convert
4294 the BL to a BLX instruction to call the ARM-mode
4295 PLT entry. */
4296 branch_type = ST_BRANCH_TO_ARM;
4297 }
4298 else
4299 {
4300 if (!thumb_only)
4301 /* Target the Thumb stub before the ARM PLT entry. */
4302 destination -= PLT_THUMB_STUB_SIZE;
4303 branch_type = ST_BRANCH_TO_THUMB;
4304 }
4305 }
4306 else
4307 {
4308 branch_type = ST_BRANCH_TO_ARM;
4309 }
34e77a92 4310 }
5fa9e92f 4311 }
34e77a92
RS		 4312 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4313 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 4314
fe33d2fa
CL		 4315 branch_offset = (bfd_signed_vma)(destination - location);
4316
0855e32b 4317 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 4318 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 4319 {
5fa9e92f
CL		 4320 /* Handle cases where:
4321 - this call goes too far (different Thumb/Thumb2 max
99059e56 4322 distance)
155d87d7 4323 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 4324 Thumb->Arm branch (not bl). A stub is needed in this case,
4325 but only if this call is not through a PLT entry. Indeed,
695344c0 4326 PLT stubs handle mode switching already. */
5e866f5a 4327 if ((!thumb2_bl
906e58ca
NC		 4328 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
4329 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 4330 || (thumb2_bl
906e58ca
NC		 4331 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4332 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4333 || (thumb2
4334 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4335 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4336 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4337 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4338 && (((r_type == R_ARM_THM_CALL
4339 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981 4340 || (r_type == R_ARM_THM_JUMP24)
07d6d2b8 4341 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4342 && !use_plt))
906e58ca 4343 {
2df2751d
CL		 4344 /* If we need to insert a Thumb-Thumb long branch stub to a
4345 PLT, use one that branches directly to the ARM PLT
4346 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4347 stub, undo this now. */
695344c0
NC		 4348 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4349 {
4350 branch_type = ST_BRANCH_TO_ARM;
4351 branch_offset += PLT_THUMB_STUB_SIZE;
4352 }
2df2751d 4353
35fc36a8 4354 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4355 {
4356 /* Thumb to thumb. */
4357 if (!thumb_only)
4358 {
d5a67c02 4359 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4360 _bfd_error_handler
871b3ab2 4361 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4362 " section with SHF_ARM_PURECODE section"
4363 " attribute is only supported for M-profile"
90b6238f 4364 " targets that implement the movw instruction"),
10463f39 4365 input_bfd, input_sec);
d5a67c02 4366
0e1862bb 4367 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4368 /* PIC stubs. */
155d87d7 4369 ? ((globals->use_blx
9553db3c 4370 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4371 /* V5T and above. Stub starts with ARM code, so
4372 we must be able to switch mode before
4373 reaching it, which is only possible for 'bl'
4374 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4375 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4376 /* On V4T, use Thumb code only. */
d3626fb0 4377 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4378
4379 /* non-PIC stubs. */
155d87d7 4380 : ((globals->use_blx
9553db3c 4381 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4382 /* V5T and above. */
4383 ? arm_stub_long_branch_any_any
4384 /* V4T. */
d3626fb0 4385 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4386 }
4387 else
4388 {
d5a67c02
AV		 4389 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4390 stub_type = arm_stub_long_branch_thumb2_only_pure;
4391 else
4392 {
4393 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4394 _bfd_error_handler
871b3ab2 4395 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4396 " section with SHF_ARM_PURECODE section"
4397 " attribute is only supported for M-profile"
90b6238f 4398 " targets that implement the movw instruction"),
10463f39 4399 input_bfd, input_sec);
d5a67c02
AV		 4400
4401 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4402 /* PIC stub. */
4403 ? arm_stub_long_branch_thumb_only_pic
4404 /* non-PIC stub. */
4405 : (thumb2 ? arm_stub_long_branch_thumb2_only
4406 : arm_stub_long_branch_thumb_only);
4407 }
906e58ca
NC		 4408 }
4409 }
4410 else
4411 {
d5a67c02 4412 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4413 _bfd_error_handler
871b3ab2 4414 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4415 " section with SHF_ARM_PURECODE section"
4416 " attribute is only supported" " for M-profile"
90b6238f 4417 " targets that implement the movw instruction"),
10463f39 4418 input_bfd, input_sec);
d5a67c02 4419
906e58ca 4420 /* Thumb to arm. */
c820be07
NC		 4421 if (sym_sec != NULL
4422 && sym_sec->owner != NULL
4423 && !INTERWORK_FLAG (sym_sec->owner))
4424 {
4eca0228 4425 _bfd_error_handler
90b6238f
AM		 4426 (_("%pB(%s): warning: interworking not enabled;"
4427 " first occurrence: %pB: %s call to %s"),
4428 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
c820be07
NC		 4429 }
4430
0855e32b 4431 stub_type =
0e1862bb 4432 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4433 /* PIC stubs. */
0855e32b 4434 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4435 /* TLS PIC stubs. */
0855e32b
NS		 4436 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4437 : arm_stub_long_branch_v4t_thumb_tls_pic)
4438 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4439 /* V5T PIC and above. */
4440 ? arm_stub_long_branch_any_arm_pic
4441 /* V4T PIC stub. */
4442 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4443
4444 /* non-PIC stubs. */
0855e32b 4445 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4446 /* V5T and above. */
4447 ? arm_stub_long_branch_any_any
4448 /* V4T. */
4449 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4450
4451 /* Handle v4t short branches. */
fea2b4d6 4452 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4453 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4454 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4455 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4456 }
4457 }
4458 }
fe33d2fa
CL		 4459 else if (r_type == R_ARM_CALL
4460 || r_type == R_ARM_JUMP24
0855e32b
NS		 4461 || r_type == R_ARM_PLT32
4462 || r_type == R_ARM_TLS_CALL)
906e58ca 4463 {
d5a67c02 4464 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4465 _bfd_error_handler
871b3ab2 4466 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4467 " section with SHF_ARM_PURECODE section"
4468 " attribute is only supported for M-profile"
90b6238f 4469 " targets that implement the movw instruction"),
10463f39 4470 input_bfd, input_sec);
35fc36a8 4471 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4472 {
4473 /* Arm to thumb. */
c820be07
NC		 4474
4475 if (sym_sec != NULL
4476 && sym_sec->owner != NULL
4477 && !INTERWORK_FLAG (sym_sec->owner))
4478 {
4eca0228 4479 _bfd_error_handler
90b6238f
AM		 4480 (_("%pB(%s): warning: interworking not enabled;"
4481 " first occurrence: %pB: %s call to %s"),
4482 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
c820be07
NC		 4483 }
4484
4485 /* We have an extra 2-bytes reach because of
4486 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4487 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4488 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4489 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4490 || (r_type == R_ARM_JUMP24)
4491 || (r_type == R_ARM_PLT32))
906e58ca 4492 {
0e1862bb 4493 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4494 /* PIC stubs. */
ebe24dd4
CL		 4495 ? ((globals->use_blx)
4496 /* V5T and above. */
4497 ? arm_stub_long_branch_any_thumb_pic
4498 /* V4T stub. */
4499 : arm_stub_long_branch_v4t_arm_thumb_pic)
4500
c2b4a39d
CL		 4501 /* non-PIC stubs. */
4502 : ((globals->use_blx)
4503 /* V5T and above. */
4504 ? arm_stub_long_branch_any_any
4505 /* V4T. */
4506 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4507 }
4508 }
4509 else
4510 {
4511 /* Arm to arm. */
4512 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4513 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4514 {
0855e32b 4515 stub_type =
0e1862bb 4516 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4517 /* PIC stubs. */
0855e32b 4518 ? (r_type == R_ARM_TLS_CALL
6a631e86 4519 /* TLS PIC Stub. */
0855e32b 4520 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4521 : (globals->nacl_p
4522 ? arm_stub_long_branch_arm_nacl_pic
4523 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4524 /* non-PIC stubs. */
7a89b94e
NC		 4525 : (globals->nacl_p
4526 ? arm_stub_long_branch_arm_nacl
4527 : arm_stub_long_branch_any_any);
906e58ca
NC		 4528 }
4529 }
4530 }
4531
fe33d2fa
CL		 4532 /* If a stub is needed, record the actual destination type. */
4533 if (stub_type != arm_stub_none)
35fc36a8 4534 *actual_branch_type = branch_type;
fe33d2fa 4535
906e58ca
NC		 4536 return stub_type;
4537}
4538
4539/* Build a name for an entry in the stub hash table. */
4540
4541static char *
4542elf32_arm_stub_name (const asection *input_section,
4543 const asection *sym_sec,
4544 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4545 const Elf_Internal_Rela *rel,
4546 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4547{
4548 char *stub_name;
4549 bfd_size_type len;
4550
4551 if (hash)
4552 {
fe33d2fa 4553 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4554 stub_name = (char *) bfd_malloc (len);
906e58ca 4555 if (stub_name != NULL)
fe33d2fa 4556 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4557 input_section->id & 0xffffffff,
4558 hash->root.root.root.string,
fe33d2fa
CL		 4559 (int) rel->r_addend & 0xffffffff,
4560 (int) stub_type);
906e58ca
NC		 4561 }
4562 else
4563 {
fe33d2fa 4564 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4565 stub_name = (char *) bfd_malloc (len);
906e58ca 4566 if (stub_name != NULL)
fe33d2fa 4567 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4568 input_section->id & 0xffffffff,
4569 sym_sec->id & 0xffffffff,
0855e32b
NS		 4570 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4571 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4572 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4573 (int) rel->r_addend & 0xffffffff,
4574 (int) stub_type);
906e58ca
NC		 4575 }
4576
4577 return stub_name;
4578}
4579
4580/* Look up an entry in the stub hash. Stub entries are cached because
4581 creating the stub name takes a bit of time. */
4582
4583static struct elf32_arm_stub_hash_entry *
4584elf32_arm_get_stub_entry (const asection *input_section,
4585 const asection *sym_sec,
4586 struct elf_link_hash_entry *hash,
4587 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4588 struct elf32_arm_link_hash_table *htab,
4589 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4590{
4591 struct elf32_arm_stub_hash_entry *stub_entry;
4592 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4593 const asection *id_sec;
4594
4595 if ((input_section->flags & SEC_CODE) == 0)
4596 return NULL;
4597
4d83e8d9
CL		 4598 /* If the input section is the CMSE stubs one and it needs a long
4599 branch stub to reach it's final destination, give up with an
4600 error message: this is not supported. See PR ld/24709. */
4601 if (!strncmp (input_section->name, CMSE_STUB_NAME, strlen(CMSE_STUB_NAME)))
4602 {
4603 bfd *output_bfd = htab->obfd;
4604 asection *out_sec = bfd_get_section_by_name (output_bfd, CMSE_STUB_NAME);
4605
4606 _bfd_error_handler (_("ERROR: CMSE stub (%s section) too far "
4607 "(%#" PRIx64 ") from destination (%#" PRIx64 ")"),
4608 CMSE_STUB_NAME,
4609 (uint64_t)out_sec->output_section->vma
4610 + out_sec->output_offset,
4611 (uint64_t)sym_sec->output_section->vma
4612 + sym_sec->output_offset
4613 + h->root.root.u.def.value);
4614 /* Exit, rather than leave incompletely processed
4615 relocations. */
4616 xexit(1);
4617 }
4618
906e58ca
NC		 4619 /* If this input section is part of a group of sections sharing one
4620 stub section, then use the id of the first section in the group.
4621 Stub names need to include a section id, as there may well be
4622 more than one stub used to reach say, printf, and we need to
4623 distinguish between them. */
c2abbbeb 4624 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4625 id_sec = htab->stub_group[input_section->id].link_sec;
4626
4627 if (h != NULL && h->stub_cache != NULL
4628 && h->stub_cache->h == h
fe33d2fa
CL		 4629 && h->stub_cache->id_sec == id_sec
4630 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4631 {
4632 stub_entry = h->stub_cache;
4633 }
4634 else
4635 {
4636 char *stub_name;
4637
fe33d2fa 4638 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4639 if (stub_name == NULL)
4640 return NULL;
4641
4642 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4643 stub_name, FALSE, FALSE);
4644 if (h != NULL)
4645 h->stub_cache = stub_entry;
4646
4647 free (stub_name);
4648 }
4649
4650 return stub_entry;
4651}
4652
daa4adae
TP		 4653/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4654 section. */
4655
4656static bfd_boolean
4657arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4658{
4659 if (stub_type >= max_stub_type)
4660 abort (); /* Should be unreachable. */
4661
4ba2ef8f
TP		 4662 switch (stub_type)
4663 {
4664 case arm_stub_cmse_branch_thumb_only:
4665 return TRUE;
4666
4667 default:
4668 return FALSE;
4669 }
4670
4671 abort (); /* Should be unreachable. */
daa4adae
TP		 4672}
4673
4674/* Required alignment (as a power of 2) for the dedicated section holding
4675 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4676 with input sections. */
4677
4678static int
4679arm_dedicated_stub_output_section_required_alignment
4680 (enum elf32_arm_stub_type stub_type)
4681{
4682 if (stub_type >= max_stub_type)
4683 abort (); /* Should be unreachable. */
4684
4ba2ef8f
TP		 4685 switch (stub_type)
4686 {
4687 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4688 boundary. */
4689 case arm_stub_cmse_branch_thumb_only:
4690 return 5;
4691
4692 default:
4693 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4694 return 0;
4695 }
4696
4697 abort (); /* Should be unreachable. */
daa4adae
TP		 4698}
4699
4700/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4701 NULL if veneers of this type are interspersed with input sections. */
4702
4703static const char *
4704arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4705{
4706 if (stub_type >= max_stub_type)
4707 abort (); /* Should be unreachable. */
4708
4ba2ef8f
TP		 4709 switch (stub_type)
4710 {
4711 case arm_stub_cmse_branch_thumb_only:
4d83e8d9 4712 return CMSE_STUB_NAME;
4ba2ef8f
TP		 4713
4714 default:
4715 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4716 return NULL;
4717 }
4718
4719 abort (); /* Should be unreachable. */
daa4adae
TP		 4720}
4721
4722/* If veneers of type STUB_TYPE should go in a dedicated output section,
4723 returns the address of the hash table field in HTAB holding a pointer to the
4724 corresponding input section. Otherwise, returns NULL. */
4725
4726static asection **
4ba2ef8f
TP		 4727arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4728 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4729{
4730 if (stub_type >= max_stub_type)
4731 abort (); /* Should be unreachable. */
4732
4ba2ef8f
TP		 4733 switch (stub_type)
4734 {
4735 case arm_stub_cmse_branch_thumb_only:
4736 return &htab->cmse_stub_sec;
4737
4738 default:
4739 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4740 return NULL;
4741 }
4742
4743 abort (); /* Should be unreachable. */
daa4adae
TP		 4744}
4745
4746/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4747 is the section that branch into veneer and can be NULL if stub should go in
4748 a dedicated output section. Returns a pointer to the stub section, and the
4749 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4750 LINK_SEC_P may be NULL. */
906e58ca 4751
48229727
JB		 4752static asection *
4753elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4754 struct elf32_arm_link_hash_table *htab,
4755 enum elf32_arm_stub_type stub_type)
906e58ca 4756{
daa4adae
TP		 4757 asection *link_sec, *out_sec, **stub_sec_p;
4758 const char *stub_sec_prefix;
4759 bfd_boolean dedicated_output_section =
4760 arm_dedicated_stub_output_section_required (stub_type);
4761 int align;
906e58ca 4762
daa4adae 4763 if (dedicated_output_section)
906e58ca 4764 {
daa4adae
TP		 4765 bfd *output_bfd = htab->obfd;
4766 const char *out_sec_name =
4767 arm_dedicated_stub_output_section_name (stub_type);
4768 link_sec = NULL;
4769 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4770 stub_sec_prefix = out_sec_name;
4771 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4772 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4773 if (out_sec == NULL)
906e58ca 4774 {
90b6238f 4775 _bfd_error_handler (_("no address assigned to the veneers output "
4eca0228 4776 "section %s"), out_sec_name);
daa4adae 4777 return NULL;
906e58ca 4778 }
daa4adae
TP		 4779 }
4780 else
4781 {
c2abbbeb 4782 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4783 link_sec = htab->stub_group[section->id].link_sec;
4784 BFD_ASSERT (link_sec != NULL);
4785 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4786 if (*stub_sec_p == NULL)
4787 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4788 stub_sec_prefix = link_sec->name;
4789 out_sec = link_sec->output_section;
4790 align = htab->nacl_p ? 4 : 3;
906e58ca 4791 }
b38cadfb 4792
daa4adae
TP		 4793 if (*stub_sec_p == NULL)
4794 {
4795 size_t namelen;
4796 bfd_size_type len;
4797 char *s_name;
4798
4799 namelen = strlen (stub_sec_prefix);
4800 len = namelen + sizeof (STUB_SUFFIX);
4801 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4802 if (s_name == NULL)
4803 return NULL;
4804
4805 memcpy (s_name, stub_sec_prefix, namelen);
4806 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4807 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4808 align);
4809 if (*stub_sec_p == NULL)
4810 return NULL;
4811
4812 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4813 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4814 | SEC_KEEP;
4815 }
4816
4817 if (!dedicated_output_section)
4818 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4819
48229727
JB		 4820 if (link_sec_p)
4821 *link_sec_p = link_sec;
b38cadfb 4822
daa4adae 4823 return *stub_sec_p;
48229727
JB		 4824}
4825
4826/* Add a new stub entry to the stub hash. Not all fields of the new
4827 stub entry are initialised. */
4828
4829static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4830elf32_arm_add_stub (const char *stub_name, asection *section,
4831 struct elf32_arm_link_hash_table *htab,
4832 enum elf32_arm_stub_type stub_type)
48229727
JB		 4833{
4834 asection *link_sec;
4835 asection *stub_sec;
4836 struct elf32_arm_stub_hash_entry *stub_entry;
4837
daa4adae
TP		 4838 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4839 stub_type);
48229727
JB		 4840 if (stub_sec == NULL)
4841 return NULL;
906e58ca
NC		 4842
4843 /* Enter this entry into the linker stub hash table. */
4844 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4845 TRUE, FALSE);
4846 if (stub_entry == NULL)
4847 {
6bde4c52
TP		 4848 if (section == NULL)
4849 section = stub_sec;
871b3ab2 4850 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 4851 section->owner, stub_name);
906e58ca
NC		 4852 return NULL;
4853 }
4854
4855 stub_entry->stub_sec = stub_sec;
0955507f 4856 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4857 stub_entry->id_sec = link_sec;
4858
906e58ca
NC		 4859 return stub_entry;
4860}
4861
4862/* Store an Arm insn into an output section not processed by
4863 elf32_arm_write_section. */
4864
4865static void
8029a119
NC		 4866put_arm_insn (struct elf32_arm_link_hash_table * htab,
4867 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4868{
4869 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4870 bfd_putl32 (val, ptr);
4871 else
4872 bfd_putb32 (val, ptr);
4873}
4874
4875/* Store a 16-bit Thumb insn into an output section not processed by
4876 elf32_arm_write_section. */
4877
4878static void
8029a119
NC		 4879put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4880 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4881{
4882 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4883 bfd_putl16 (val, ptr);
4884 else
4885 bfd_putb16 (val, ptr);
4886}
4887
a504d23a
LA		 4888/* Store a Thumb2 insn into an output section not processed by
4889 elf32_arm_write_section. */
4890
4891static void
4892put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4893 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4894{
4895 /* T2 instructions are 16-bit streamed. */
4896 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4897 {
4898 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4899 bfd_putl16 ((val & 0xffff), ptr + 2);
4900 }
4901 else
4902 {
4903 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4904 bfd_putb16 ((val & 0xffff), ptr + 2);
4905 }
4906}
4907
0855e32b
NS		 4908/* If it's possible to change R_TYPE to a more efficient access
4909 model, return the new reloc type. */
4910
4911static unsigned
b38cadfb 4912elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4913 struct elf_link_hash_entry *h)
4914{
4915 int is_local = (h == NULL);
4916
9cb09e33 4917 if (bfd_link_dll (info)
0e1862bb 4918 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4919 return r_type;
4920
b38cadfb 4921 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4922 switch (r_type)
4923 {
4924 case R_ARM_TLS_GOTDESC:
4925 case R_ARM_TLS_CALL:
4926 case R_ARM_THM_TLS_CALL:
4927 case R_ARM_TLS_DESCSEQ:
4928 case R_ARM_THM_TLS_DESCSEQ:
4929 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4930 }
4931
4932 return r_type;
4933}
4934
48229727
JB		 4935static bfd_reloc_status_type elf32_arm_final_link_relocate
4936 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4937 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4938 const char *, unsigned char, enum arm_st_branch_type,
4939 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4940
4563a860
JB		 4941static unsigned int
4942arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4943{
4944 switch (stub_type)
4945 {
4946 case arm_stub_a8_veneer_b_cond:
4947 case arm_stub_a8_veneer_b:
4948 case arm_stub_a8_veneer_bl:
4949 return 2;
4950
4951 case arm_stub_long_branch_any_any:
4952 case arm_stub_long_branch_v4t_arm_thumb:
4953 case arm_stub_long_branch_thumb_only:
80c135e5 4954 case arm_stub_long_branch_thumb2_only:
d5a67c02 4955 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4956 case arm_stub_long_branch_v4t_thumb_thumb:
4957 case arm_stub_long_branch_v4t_thumb_arm:
4958 case arm_stub_short_branch_v4t_thumb_arm:
4959 case arm_stub_long_branch_any_arm_pic:
4960 case arm_stub_long_branch_any_thumb_pic:
4961 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4962 case arm_stub_long_branch_v4t_arm_thumb_pic:
4963 case arm_stub_long_branch_v4t_thumb_arm_pic:
4964 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4965 case arm_stub_long_branch_any_tls_pic:
4966 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4967 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4968 case arm_stub_a8_veneer_blx:
4969 return 4;
b38cadfb 4970
7a89b94e
NC		 4971 case arm_stub_long_branch_arm_nacl:
4972 case arm_stub_long_branch_arm_nacl_pic:
4973 return 16;
4974
4563a860
JB		 4975 default:
4976 abort (); /* Should be unreachable. */
4977 }
4978}
4979
4f4faa4d
TP		 4980/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4981 veneering (TRUE) or have their own symbol (FALSE). */
4982
4983static bfd_boolean
4984arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4985{
4986 if (stub_type >= max_stub_type)
4987 abort (); /* Should be unreachable. */
4988
4ba2ef8f
TP		 4989 switch (stub_type)
4990 {
4991 case arm_stub_cmse_branch_thumb_only:
4992 return TRUE;
4993
4994 default:
4995 return FALSE;
4996 }
4997
4998 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4999}
5000
d7c5bd02
TP		 5001/* Returns the padding needed for the dedicated section used stubs of type
5002 STUB_TYPE. */
5003
5004static int
5005arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
5006{
5007 if (stub_type >= max_stub_type)
5008 abort (); /* Should be unreachable. */
5009
4ba2ef8f
TP		 5010 switch (stub_type)
5011 {
5012 case arm_stub_cmse_branch_thumb_only:
5013 return 32;
5014
5015 default:
5016 return 0;
5017 }
5018
5019 abort (); /* Should be unreachable. */
d7c5bd02
TP		 5020}
5021
0955507f
TP		 5022/* If veneers of type STUB_TYPE should go in a dedicated output section,
5023 returns the address of the hash table field in HTAB holding the offset at
5024 which new veneers should be layed out in the stub section. */
5025
5026static bfd_vma*
5027arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
5028 enum elf32_arm_stub_type stub_type)
5029{
5030 switch (stub_type)
5031 {
5032 case arm_stub_cmse_branch_thumb_only:
5033 return &htab->new_cmse_stub_offset;
5034
5035 default:
5036 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
5037 return NULL;
5038 }
5039}
5040
906e58ca
NC		 5041static bfd_boolean
5042arm_build_one_stub (struct bfd_hash_entry *gen_entry,
5043 void * in_arg)
5044{
7a89b94e 5045#define MAXRELOCS 3
0955507f 5046 bfd_boolean removed_sg_veneer;
906e58ca 5047 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 5048 struct elf32_arm_link_hash_table *globals;
906e58ca 5049 struct bfd_link_info *info;
906e58ca
NC		 5050 asection *stub_sec;
5051 bfd *stub_bfd;
906e58ca
NC		 5052 bfd_byte *loc;
5053 bfd_vma sym_value;
5054 int template_size;
5055 int size;
d3ce72d0 5056 const insn_sequence *template_sequence;
906e58ca 5057 int i;
48229727
JB		 5058 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
5059 int stub_reloc_offset[MAXRELOCS] = {0, 0};
5060 int nrelocs = 0;
0955507f 5061 int just_allocated = 0;
906e58ca
NC		 5062
5063 /* Massage our args to the form they really have. */
5064 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5065 info = (struct bfd_link_info *) in_arg;
5066
5067 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 5068 if (globals == NULL)
5069 return FALSE;
906e58ca 5070
906e58ca
NC		 5071 stub_sec = stub_entry->stub_sec;
5072
4dfe6ac6 5073 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 5074 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
5075 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 5076 return TRUE;
fe33d2fa 5077
0955507f
TP		 5078 /* Assign a slot at the end of section if none assigned yet. */
5079 if (stub_entry->stub_offset == (bfd_vma) -1)
5080 {
5081 stub_entry->stub_offset = stub_sec->size;
5082 just_allocated = 1;
5083 }
906e58ca
NC		 5084 loc = stub_sec->contents + stub_entry->stub_offset;
5085
5086 stub_bfd = stub_sec->owner;
5087
906e58ca
NC		 5088 /* This is the address of the stub destination. */
5089 sym_value = (stub_entry->target_value
5090 + stub_entry->target_section->output_offset
5091 + stub_entry->target_section->output_section->vma);
5092
d3ce72d0 5093 template_sequence = stub_entry->stub_template;
461a49ca 5094 template_size = stub_entry->stub_template_size;
906e58ca
NC		 5095
5096 size = 0;
461a49ca 5097 for (i = 0; i < template_size; i++)
906e58ca 5098 {
d3ce72d0 5099 switch (template_sequence[i].type)
461a49ca
DJ		 5100 {
5101 case THUMB16_TYPE:
48229727 5102 {
d3ce72d0
NC		 5103 bfd_vma data = (bfd_vma) template_sequence[i].data;
5104 if (template_sequence[i].reloc_addend != 0)
48229727 5105 {
99059e56
RM		 5106 /* We've borrowed the reloc_addend field to mean we should
5107 insert a condition code into this (Thumb-1 branch)
5108 instruction. See THUMB16_BCOND_INSN. */
5109 BFD_ASSERT ((data & 0xff00) == 0xd000);
5110 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 5111 }
fe33d2fa 5112 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 5113 size += 2;
5114 }
461a49ca 5115 break;
906e58ca 5116
48229727 5117 case THUMB32_TYPE:
fe33d2fa
CL		 5118 bfd_put_16 (stub_bfd,
5119 (template_sequence[i].data >> 16) & 0xffff,
5120 loc + size);
5121 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
5122 loc + size + 2);
99059e56
RM		 5123 if (template_sequence[i].r_type != R_ARM_NONE)
5124 {
5125 stub_reloc_idx[nrelocs] = i;
5126 stub_reloc_offset[nrelocs++] = size;
5127 }
5128 size += 4;
5129 break;
48229727 5130
461a49ca 5131 case ARM_TYPE:
fe33d2fa
CL		 5132 bfd_put_32 (stub_bfd, template_sequence[i].data,
5133 loc + size);
461a49ca
DJ		 5134 /* Handle cases where the target is encoded within the
5135 instruction. */
d3ce72d0 5136 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 5137 {
48229727
JB		 5138 stub_reloc_idx[nrelocs] = i;
5139 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5140 }
5141 size += 4;
5142 break;
5143
5144 case DATA_TYPE:
d3ce72d0 5145 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 5146 stub_reloc_idx[nrelocs] = i;
5147 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5148 size += 4;
5149 break;
5150
5151 default:
5152 BFD_FAIL ();
5153 return FALSE;
5154 }
906e58ca 5155 }
461a49ca 5156
0955507f
TP		 5157 if (just_allocated)
5158 stub_sec->size += size;
906e58ca 5159
461a49ca
DJ		 5160 /* Stub size has already been computed in arm_size_one_stub. Check
5161 consistency. */
5162 BFD_ASSERT (size == stub_entry->stub_size);
5163
906e58ca 5164 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 5165 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 5166 sym_value |= 1;
5167
0955507f
TP		 5168 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5169 to relocate in each stub. */
5170 removed_sg_veneer =
5171 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5172 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 5173
48229727 5174 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 5175 {
5176 Elf_Internal_Rela rel;
5177 bfd_boolean unresolved_reloc;
5178 char *error_message;
5179 bfd_vma points_to =
5180 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
5181
5182 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
5183 rel.r_info = ELF32_R_INFO (0,
5184 template_sequence[stub_reloc_idx[i]].r_type);
5185 rel.r_addend = 0;
5186
5187 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
5188 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5189 template should refer back to the instruction after the original
5190 branch. We use target_section as Cortex-A8 erratum workaround stubs
5191 are only generated when both source and target are in the same
5192 section. */
5193 points_to = stub_entry->target_section->output_section->vma
5194 + stub_entry->target_section->output_offset
5195 + stub_entry->source_value;
5196
5197 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
5198 (template_sequence[stub_reloc_idx[i]].r_type),
5199 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
5200 points_to, info, stub_entry->target_section, "", STT_FUNC,
5201 stub_entry->branch_type,
5202 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
5203 &error_message);
5204 }
906e58ca
NC		 5205
5206 return TRUE;
48229727 5207#undef MAXRELOCS
906e58ca
NC		 5208}
5209
48229727
JB		 5210/* Calculate the template, template size and instruction size for a stub.
5211 Return value is the instruction size. */
906e58ca 5212
48229727
JB		 5213static unsigned int
5214find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
5215 const insn_sequence **stub_template,
5216 int *stub_template_size)
906e58ca 5217{
d3ce72d0 5218 const insn_sequence *template_sequence = NULL;
48229727
JB		 5219 int template_size = 0, i;
5220 unsigned int size;
906e58ca 5221
d3ce72d0 5222 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 5223 if (stub_template)
5224 *stub_template = template_sequence;
5225
48229727 5226 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 5227 if (stub_template_size)
5228 *stub_template_size = template_size;
906e58ca
NC		 5229
5230 size = 0;
461a49ca
DJ		 5231 for (i = 0; i < template_size; i++)
5232 {
d3ce72d0 5233 switch (template_sequence[i].type)
461a49ca
DJ		 5234 {
5235 case THUMB16_TYPE:
5236 size += 2;
5237 break;
5238
5239 case ARM_TYPE:
48229727 5240 case THUMB32_TYPE:
461a49ca
DJ		 5241 case DATA_TYPE:
5242 size += 4;
5243 break;
5244
5245 default:
5246 BFD_FAIL ();
2a229407 5247 return 0;
461a49ca
DJ		 5248 }
5249 }
5250
48229727
JB		 5251 return size;
5252}
5253
5254/* As above, but don't actually build the stub. Just bump offset so
5255 we know stub section sizes. */
5256
5257static bfd_boolean
5258arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 5259 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 5260{
5261 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 5262 const insn_sequence *template_sequence;
48229727
JB		 5263 int template_size, size;
5264
5265 /* Massage our args to the form they really have. */
5266 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 5267
5268 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
5269 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
5270
d3ce72d0 5271 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 5272 &template_size);
5273
0955507f
TP		 5274 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5275 if (stub_entry->stub_template_size)
5276 {
5277 stub_entry->stub_size = size;
5278 stub_entry->stub_template = template_sequence;
5279 stub_entry->stub_template_size = template_size;
5280 }
5281
5282 /* Already accounted for. */
5283 if (stub_entry->stub_offset != (bfd_vma) -1)
5284 return TRUE;
461a49ca 5285
906e58ca
NC		 5286 size = (size + 7) & ~7;
5287 stub_entry->stub_sec->size += size;
461a49ca 5288
906e58ca
NC		 5289 return TRUE;
5290}
5291
5292/* External entry points for sizing and building linker stubs. */
5293
5294/* Set up various things so that we can make a list of input sections
5295 for each output section included in the link. Returns -1 on error,
5296 0 when no stubs will be needed, and 1 on success. */
5297
5298int
5299elf32_arm_setup_section_lists (bfd *output_bfd,
5300 struct bfd_link_info *info)
5301{
5302 bfd *input_bfd;
5303 unsigned int bfd_count;
7292b3ac 5304 unsigned int top_id, top_index;
906e58ca
NC		 5305 asection *section;
5306 asection **input_list, **list;
5307 bfd_size_type amt;
5308 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5309
4dfe6ac6
NC		 5310 if (htab == NULL)
5311 return 0;
906e58ca
NC		 5312 if (! is_elf_hash_table (htab))
5313 return 0;
5314
5315 /* Count the number of input BFDs and find the top input section id. */
5316 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
5317 input_bfd != NULL;
c72f2fb2 5318 input_bfd = input_bfd->link.next)
906e58ca
NC		 5319 {
5320 bfd_count += 1;
5321 for (section = input_bfd->sections;
5322 section != NULL;
5323 section = section->next)
5324 {
5325 if (top_id < section->id)
5326 top_id = section->id;
5327 }
5328 }
5329 htab->bfd_count = bfd_count;
5330
5331 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 5332 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 5333 if (htab->stub_group == NULL)
5334 return -1;
fe33d2fa 5335 htab->top_id = top_id;
906e58ca
NC		 5336
5337 /* We can't use output_bfd->section_count here to find the top output
5338 section index as some sections may have been removed, and
5339 _bfd_strip_section_from_output doesn't renumber the indices. */
5340 for (section = output_bfd->sections, top_index = 0;
5341 section != NULL;
5342 section = section->next)
5343 {
5344 if (top_index < section->index)
5345 top_index = section->index;
5346 }
5347
5348 htab->top_index = top_index;
5349 amt = sizeof (asection *) * (top_index + 1);
21d799b5 5350 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 5351 htab->input_list = input_list;
5352 if (input_list == NULL)
5353 return -1;
5354
5355 /* For sections we aren't interested in, mark their entries with a
5356 value we can check later. */
5357 list = input_list + top_index;
5358 do
5359 *list = bfd_abs_section_ptr;
5360 while (list-- != input_list);
5361
5362 for (section = output_bfd->sections;
5363 section != NULL;
5364 section = section->next)
5365 {
5366 if ((section->flags & SEC_CODE) != 0)
5367 input_list[section->index] = NULL;
5368 }
5369
5370 return 1;
5371}
5372
5373/* The linker repeatedly calls this function for each input section,
5374 in the order that input sections are linked into output sections.
5375 Build lists of input sections to determine groupings between which
5376 we may insert linker stubs. */
5377
5378void
5379elf32_arm_next_input_section (struct bfd_link_info *info,
5380 asection *isec)
5381{
5382 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5383
4dfe6ac6
NC		 5384 if (htab == NULL)
5385 return;
5386
906e58ca
NC		 5387 if (isec->output_section->index <= htab->top_index)
5388 {
5389 asection **list = htab->input_list + isec->output_section->index;
5390
a7470592 5391 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5392 {
5393 /* Steal the link_sec pointer for our list. */
5394#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5395 /* This happens to make the list in reverse order,
07d72278 5396 which we reverse later. */
906e58ca
NC		 5397 PREV_SEC (isec) = *list;
5398 *list = isec;
5399 }
5400 }
5401}
5402
5403/* See whether we can group stub sections together. Grouping stub
5404 sections may result in fewer stubs. More importantly, we need to
07d72278 5405 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5406 .fini output sections respectively, because glibc splits the
5407 _init and _fini functions into multiple parts. Putting a stub in
5408 the middle of a function is not a good idea. */
5409
5410static void
5411group_sections (struct elf32_arm_link_hash_table *htab,
5412 bfd_size_type stub_group_size,
07d72278 5413 bfd_boolean stubs_always_after_branch)
906e58ca 5414{
07d72278 5415 asection **list = htab->input_list;
906e58ca
NC		 5416
5417 do
5418 {
5419 asection *tail = *list;
07d72278 5420 asection *head;
906e58ca
NC		 5421
5422 if (tail == bfd_abs_section_ptr)
5423 continue;
5424
07d72278
DJ		 5425 /* Reverse the list: we must avoid placing stubs at the
5426 beginning of the section because the beginning of the text
5427 section may be required for an interrupt vector in bare metal
5428 code. */
5429#define NEXT_SEC PREV_SEC
e780aef2
CL		 5430 head = NULL;
5431 while (tail != NULL)
99059e56
RM		 5432 {
5433 /* Pop from tail. */
5434 asection *item = tail;
5435 tail = PREV_SEC (item);
e780aef2 5436
99059e56
RM		 5437 /* Push on head. */
5438 NEXT_SEC (item) = head;
5439 head = item;
5440 }
07d72278
DJ		 5441
5442 while (head != NULL)
906e58ca
NC		 5443 {
5444 asection *curr;
07d72278 5445 asection *next;
e780aef2
CL		 5446 bfd_vma stub_group_start = head->output_offset;
5447 bfd_vma end_of_next;
906e58ca 5448
07d72278 5449 curr = head;
e780aef2 5450 while (NEXT_SEC (curr) != NULL)
8cd931b7 5451 {
e780aef2
CL		 5452 next = NEXT_SEC (curr);
5453 end_of_next = next->output_offset + next->size;
5454 if (end_of_next - stub_group_start >= stub_group_size)
5455 /* End of NEXT is too far from start, so stop. */
8cd931b7 5456 break;
e780aef2
CL		 5457 /* Add NEXT to the group. */
5458 curr = next;
8cd931b7 5459 }
906e58ca 5460
07d72278 5461 /* OK, the size from the start to the start of CURR is less
906e58ca 5462 than stub_group_size and thus can be handled by one stub
07d72278 5463 section. (Or the head section is itself larger than
906e58ca
NC		 5464 stub_group_size, in which case we may be toast.)
5465 We should really be keeping track of the total size of
5466 stubs added here, as stubs contribute to the final output
7fb9f789 5467 section size. */
906e58ca
NC		 5468 do
5469 {
07d72278 5470 next = NEXT_SEC (head);
906e58ca 5471 /* Set up this stub group. */
07d72278 5472 htab->stub_group[head->id].link_sec = curr;
906e58ca 5473 }
07d72278 5474 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5475
5476 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5477 bytes after the stub section can be handled by it too. */
5478 if (!stubs_always_after_branch)
906e58ca 5479 {
e780aef2
CL		 5480 stub_group_start = curr->output_offset + curr->size;
5481
8cd931b7 5482 while (next != NULL)
906e58ca 5483 {
e780aef2
CL		 5484 end_of_next = next->output_offset + next->size;
5485 if (end_of_next - stub_group_start >= stub_group_size)
5486 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5487 break;
e780aef2 5488 /* Add NEXT to the stub group. */
07d72278
DJ		 5489 head = next;
5490 next = NEXT_SEC (head);
5491 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5492 }
5493 }
07d72278 5494 head = next;
906e58ca
NC		 5495 }
5496 }
07d72278 5497 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5498
5499 free (htab->input_list);
5500#undef PREV_SEC
07d72278 5501#undef NEXT_SEC
906e58ca
NC		 5502}
5503
48229727
JB		 5504/* Comparison function for sorting/searching relocations relating to Cortex-A8
5505 erratum fix. */
5506
5507static int
5508a8_reloc_compare (const void *a, const void *b)
5509{
21d799b5
NC		 5510 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5511 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5512
5513 if (ra->from < rb->from)
5514 return -1;
5515 else if (ra->from > rb->from)
5516 return 1;
5517 else
5518 return 0;
5519}
5520
5521static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5522 const char *, char **);
5523
5524/* Helper function to scan code for sequences which might trigger the Cortex-A8
5525 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5526 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5527 otherwise. */
5528
81694485
NC		 5529static bfd_boolean
5530cortex_a8_erratum_scan (bfd *input_bfd,
5531 struct bfd_link_info *info,
48229727
JB		 5532 struct a8_erratum_fix **a8_fixes_p,
5533 unsigned int *num_a8_fixes_p,
5534 unsigned int *a8_fix_table_size_p,
5535 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5536 unsigned int num_a8_relocs,
5537 unsigned prev_num_a8_fixes,
5538 bfd_boolean *stub_changed_p)
48229727
JB		 5539{
5540 asection *section;
5541 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5542 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5543 unsigned int num_a8_fixes = *num_a8_fixes_p;
5544 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5545
4dfe6ac6
NC		 5546 if (htab == NULL)
5547 return FALSE;
5548
48229727
JB		 5549 for (section = input_bfd->sections;
5550 section != NULL;
5551 section = section->next)
5552 {
5553 bfd_byte *contents = NULL;
5554 struct _arm_elf_section_data *sec_data;
5555 unsigned int span;
5556 bfd_vma base_vma;
5557
5558 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5559 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5560 || (section->flags & SEC_EXCLUDE) != 0
5561 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5562 || (section->output_section == bfd_abs_section_ptr))
5563 continue;
48229727
JB		 5564
5565 base_vma = section->output_section->vma + section->output_offset;
5566
5567 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5568 contents = elf_section_data (section)->this_hdr.contents;
48229727 5569 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5570 return TRUE;
48229727
JB		 5571
5572 sec_data = elf32_arm_section_data (section);
5573
5574 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5575 {
5576 unsigned int span_start = sec_data->map[span].vma;
5577 unsigned int span_end = (span == sec_data->mapcount - 1)
5578 ? section->size : sec_data->map[span + 1].vma;
5579 unsigned int i;
5580 char span_type = sec_data->map[span].type;
5581 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5582
5583 if (span_type != 't')
5584 continue;
5585
5586 /* Span is entirely within a single 4KB region: skip scanning. */
5587 if (((base_vma + span_start) & ~0xfff)
48229727 5588 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5589 continue;
5590
5591 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5592
5593 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5594 * The branch target is in the same 4KB region as the
5595 first half of the branch.
5596 * The instruction before the branch is a 32-bit
5597 length non-branch instruction. */
5598 for (i = span_start; i < span_end;)
5599 {
5600 unsigned int insn = bfd_getl16 (&contents[i]);
5601 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5602 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5603
99059e56
RM		 5604 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5605 insn_32bit = TRUE;
48229727
JB		 5606
5607 if (insn_32bit)
99059e56
RM		 5608 {
5609 /* Load the rest of the insn (in manual-friendly order). */
5610 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5611
5612 /* Encoding T4: B<c>.W. */
5613 is_b = (insn & 0xf800d000) == 0xf0009000;
5614 /* Encoding T1: BL<c>.W. */
5615 is_bl = (insn & 0xf800d000) == 0xf000d000;
5616 /* Encoding T2: BLX<c>.W. */
5617 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5618 /* Encoding T3: B<c>.W (not permitted in IT block). */
5619 is_bcc = (insn & 0xf800d000) == 0xf0008000
5620 && (insn & 0x07f00000) != 0x03800000;
5621 }
5622
5623 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5624
99059e56 5625 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5626 && insn_32bit
5627 && is_32bit_branch
5628 && last_was_32bit
5629 && ! last_was_branch)
99059e56
RM		 5630 {
5631 bfd_signed_vma offset = 0;
5632 bfd_boolean force_target_arm = FALSE;
48229727 5633 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5634 bfd_vma target;
5635 enum elf32_arm_stub_type stub_type = arm_stub_none;
5636 struct a8_erratum_reloc key, *found;
5637 bfd_boolean use_plt = FALSE;
48229727 5638
99059e56
RM		 5639 key.from = base_vma + i;
5640 found = (struct a8_erratum_reloc *)
5641 bsearch (&key, a8_relocs, num_a8_relocs,
5642 sizeof (struct a8_erratum_reloc),
5643 &a8_reloc_compare);
48229727
JB		 5644
5645 if (found)
5646 {
5647 char *error_message = NULL;
5648 struct elf_link_hash_entry *entry;
5649
5650 /* We don't care about the error returned from this
99059e56 5651 function, only if there is glue or not. */
48229727
JB		 5652 entry = find_thumb_glue (info, found->sym_name,
5653 &error_message);
5654
5655 if (entry)
5656 found->non_a8_stub = TRUE;
5657
92750f34 5658 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5659 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5660 && found->hash->root.plt.offset != (bfd_vma) -1)
5661 use_plt = TRUE;
5662
5663 if (found->r_type == R_ARM_THM_CALL)
5664 {
35fc36a8
RS		 5665 if (found->branch_type == ST_BRANCH_TO_ARM
5666 || use_plt)
92750f34
DJ		 5667 force_target_arm = TRUE;
5668 else
5669 force_target_thumb = TRUE;
5670 }
48229727
JB		 5671 }
5672
99059e56 5673 /* Check if we have an offending branch instruction. */
48229727
JB		 5674
5675 if (found && found->non_a8_stub)
5676 /* We've already made a stub for this instruction, e.g.
5677 it's a long branch or a Thumb->ARM stub. Assume that
5678 stub will suffice to work around the A8 erratum (see
5679 setting of always_after_branch above). */
5680 ;
99059e56
RM		 5681 else if (is_bcc)
5682 {
5683 offset = (insn & 0x7ff) << 1;
5684 offset |= (insn & 0x3f0000) >> 4;
5685 offset |= (insn & 0x2000) ? 0x40000 : 0;
5686 offset |= (insn & 0x800) ? 0x80000 : 0;
5687 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5688 if (offset & 0x100000)
5689 offset |= ~ ((bfd_signed_vma) 0xfffff);
5690 stub_type = arm_stub_a8_veneer_b_cond;
5691 }
5692 else if (is_b || is_bl || is_blx)
5693 {
5694 int s = (insn & 0x4000000) != 0;
5695 int j1 = (insn & 0x2000) != 0;
5696 int j2 = (insn & 0x800) != 0;
5697 int i1 = !(j1 ^ s);
5698 int i2 = !(j2 ^ s);
5699
5700 offset = (insn & 0x7ff) << 1;
5701 offset |= (insn & 0x3ff0000) >> 4;
5702 offset |= i2 << 22;
5703 offset |= i1 << 23;
5704 offset |= s << 24;
5705 if (offset & 0x1000000)
5706 offset |= ~ ((bfd_signed_vma) 0xffffff);
5707
5708 if (is_blx)
5709 offset &= ~ ((bfd_signed_vma) 3);
5710
5711 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5712 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5713 }
5714
5715 if (stub_type != arm_stub_none)
5716 {
5717 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5718
5719 /* The original instruction is a BL, but the target is
99059e56 5720 an ARM instruction. If we were not making a stub,
48229727
JB		 5721 the BL would have been converted to a BLX. Use the
5722 BLX stub instead in that case. */
5723 if (htab->use_blx && force_target_arm
5724 && stub_type == arm_stub_a8_veneer_bl)
5725 {
5726 stub_type = arm_stub_a8_veneer_blx;
5727 is_blx = TRUE;
5728 is_bl = FALSE;
5729 }
5730 /* Conversely, if the original instruction was
5731 BLX but the target is Thumb mode, use the BL
5732 stub. */
5733 else if (force_target_thumb
5734 && stub_type == arm_stub_a8_veneer_blx)
5735 {
5736 stub_type = arm_stub_a8_veneer_bl;
5737 is_blx = FALSE;
5738 is_bl = TRUE;
5739 }
5740
99059e56
RM		 5741 if (is_blx)
5742 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5743
99059e56
RM		 5744 /* If we found a relocation, use the proper destination,
5745 not the offset in the (unrelocated) instruction.
48229727
JB		 5746 Note this is always done if we switched the stub type
5747 above. */
99059e56
RM		 5748 if (found)
5749 offset =
81694485 5750 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5751
99059e56
RM		 5752 /* If the stub will use a Thumb-mode branch to a
5753 PLT target, redirect it to the preceding Thumb
5754 entry point. */
5755 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5756 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5757
99059e56 5758 target = pc_for_insn + offset;
48229727 5759
99059e56
RM		 5760 /* The BLX stub is ARM-mode code. Adjust the offset to
5761 take the different PC value (+8 instead of +4) into
48229727 5762 account. */
99059e56
RM		 5763 if (stub_type == arm_stub_a8_veneer_blx)
5764 offset += 4;
5765
5766 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5767 {
5768 char *stub_name = NULL;
5769
5770 if (num_a8_fixes == a8_fix_table_size)
5771 {
5772 a8_fix_table_size *= 2;
5773 a8_fixes = (struct a8_erratum_fix *)
5774 bfd_realloc (a8_fixes,
5775 sizeof (struct a8_erratum_fix)
5776 * a8_fix_table_size);
5777 }
48229727 5778
eb7c4339
NS		 5779 if (num_a8_fixes < prev_num_a8_fixes)
5780 {
5781 /* If we're doing a subsequent scan,
5782 check if we've found the same fix as
5783 before, and try and reuse the stub
5784 name. */
5785 stub_name = a8_fixes[num_a8_fixes].stub_name;
5786 if ((a8_fixes[num_a8_fixes].section != section)
5787 || (a8_fixes[num_a8_fixes].offset != i))
5788 {
5789 free (stub_name);
5790 stub_name = NULL;
5791 *stub_changed_p = TRUE;
5792 }
5793 }
5794
5795 if (!stub_name)
5796 {
21d799b5 5797 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5798 if (stub_name != NULL)
5799 sprintf (stub_name, "%x:%x", section->id, i);
5800 }
48229727 5801
99059e56
RM		 5802 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5803 a8_fixes[num_a8_fixes].section = section;
5804 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5805 a8_fixes[num_a8_fixes].target_offset =
5806 target - base_vma;
99059e56
RM		 5807 a8_fixes[num_a8_fixes].orig_insn = insn;
5808 a8_fixes[num_a8_fixes].stub_name = stub_name;
5809 a8_fixes[num_a8_fixes].stub_type = stub_type;
5810 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5811 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5812
99059e56
RM		 5813 num_a8_fixes++;
5814 }
5815 }
5816 }
48229727 5817
99059e56
RM		 5818 i += insn_32bit ? 4 : 2;
5819 last_was_32bit = insn_32bit;
48229727 5820 last_was_branch = is_32bit_branch;
99059e56
RM		 5821 }
5822 }
48229727
JB		 5823
5824 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5825 free (contents);
48229727 5826 }
fe33d2fa 5827
48229727
JB		 5828 *a8_fixes_p = a8_fixes;
5829 *num_a8_fixes_p = num_a8_fixes;
5830 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5831
81694485 5832 return FALSE;
48229727
JB		 5833}
5834
b715f643
TP		 5835/* Create or update a stub entry depending on whether the stub can already be
5836 found in HTAB. The stub is identified by:
5837 - its type STUB_TYPE
5838 - its source branch (note that several can share the same stub) whose
5839 section and relocation (if any) are given by SECTION and IRELA
5840 respectively
5841 - its target symbol whose input section, hash, name, value and branch type
5842 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5843 respectively
5844
5845 If found, the value of the stub's target symbol is updated from SYM_VALUE
5846 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5847 TRUE and the stub entry is initialized.
5848
0955507f
TP		 5849 Returns the stub that was created or updated, or NULL if an error
5850 occurred. */
b715f643 5851
0955507f 5852static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5853elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5854 enum elf32_arm_stub_type stub_type, asection *section,
5855 Elf_Internal_Rela *irela, asection *sym_sec,
5856 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5857 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5858 bfd_boolean *new_stub)
5859{
5860 const asection *id_sec;
5861 char *stub_name;
5862 struct elf32_arm_stub_hash_entry *stub_entry;
5863 unsigned int r_type;
4f4faa4d 5864 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5865
5866 BFD_ASSERT (stub_type != arm_stub_none);
5867 *new_stub = FALSE;
5868
4f4faa4d
TP		 5869 if (sym_claimed)
5870 stub_name = sym_name;
5871 else
5872 {
5873 BFD_ASSERT (irela);
5874 BFD_ASSERT (section);
c2abbbeb 5875 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5876
4f4faa4d
TP		 5877 /* Support for grouping stub sections. */
5878 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5879
4f4faa4d
TP		 5880 /* Get the name of this stub. */
5881 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5882 stub_type);
5883 if (!stub_name)
0955507f 5884 return NULL;
4f4faa4d 5885 }
b715f643
TP		 5886
5887 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5888 FALSE);
5889 /* The proper stub has already been created, just update its value. */
5890 if (stub_entry != NULL)
5891 {
4f4faa4d
TP		 5892 if (!sym_claimed)
5893 free (stub_name);
b715f643 5894 stub_entry->target_value = sym_value;
0955507f 5895 return stub_entry;
b715f643
TP		 5896 }
5897
daa4adae 5898 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5899 if (stub_entry == NULL)
5900 {
4f4faa4d
TP		 5901 if (!sym_claimed)
5902 free (stub_name);
0955507f 5903 return NULL;
b715f643
TP		 5904 }
5905
5906 stub_entry->target_value = sym_value;
5907 stub_entry->target_section = sym_sec;
5908 stub_entry->stub_type = stub_type;
5909 stub_entry->h = hash;
5910 stub_entry->branch_type = branch_type;
5911
4f4faa4d
TP		 5912 if (sym_claimed)
5913 stub_entry->output_name = sym_name;
5914 else
b715f643 5915 {
4f4faa4d
TP		 5916 if (sym_name == NULL)
5917 sym_name = "unnamed";
5918 stub_entry->output_name = (char *)
5919 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5920 + strlen (sym_name));
5921 if (stub_entry->output_name == NULL)
5922 {
5923 free (stub_name);
0955507f 5924 return NULL;
4f4faa4d 5925 }
b715f643 5926
4f4faa4d
TP		 5927 /* For historical reasons, use the existing names for ARM-to-Thumb and
5928 Thumb-to-ARM stubs. */
5929 r_type = ELF32_R_TYPE (irela->r_info);
5930 if ((r_type == (unsigned int) R_ARM_THM_CALL
5931 || r_type == (unsigned int) R_ARM_THM_JUMP24
5932 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5933 && branch_type == ST_BRANCH_TO_ARM)
5934 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5935 else if ((r_type == (unsigned int) R_ARM_CALL
5936 || r_type == (unsigned int) R_ARM_JUMP24)
5937 && branch_type == ST_BRANCH_TO_THUMB)
5938 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5939 else
5940 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5941 }
b715f643
TP		 5942
5943 *new_stub = TRUE;
0955507f 5944 return stub_entry;
b715f643
TP		 5945}
5946
4ba2ef8f
TP		 5947/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5948 gateway veneer to transition from non secure to secure state and create them
5949 accordingly.
5950
5951 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5952 defines the conditions that govern Secure Gateway veneer creation for a
5953 given symbol <SYM> as follows:
5954 - it has function type
5955 - it has non local binding
5956 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5957 same type, binding and value as <SYM> (called normal symbol).
5958 An entry function can handle secure state transition itself in which case
5959 its special symbol would have a different value from the normal symbol.
5960
5961 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5962 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5963 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5964 created.
4ba2ef8f 5965
0955507f 5966 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5967
5968static bfd_boolean
5969cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5970 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5971 int *cmse_stub_created)
4ba2ef8f
TP		 5972{
5973 const struct elf_backend_data *bed;
5974 Elf_Internal_Shdr *symtab_hdr;
5975 unsigned i, j, sym_count, ext_start;
5976 Elf_Internal_Sym *cmse_sym, *local_syms;
5977 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5978 enum arm_st_branch_type branch_type;
5979 char *sym_name, *lsym_name;
5980 bfd_vma sym_value;
5981 asection *section;
0955507f
TP		 5982 struct elf32_arm_stub_hash_entry *stub_entry;
5983 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5984
5985 bed = get_elf_backend_data (input_bfd);
5986 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5987 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5988 ext_start = symtab_hdr->sh_info;
5989 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5990 && out_attr[Tag_CPU_arch_profile].i == 'M');
5991
5992 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5993 if (local_syms == NULL)
5994 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5995 symtab_hdr->sh_info, 0, NULL, NULL,
5996 NULL);
5997 if (symtab_hdr->sh_info && local_syms == NULL)
5998 return FALSE;
5999
6000 /* Scan symbols. */
6001 for (i = 0; i < sym_count; i++)
6002 {
6003 cmse_invalid = FALSE;
6004
6005 if (i < ext_start)
6006 {
6007 cmse_sym = &local_syms[i];
4ba2ef8f
TP		 6008 sym_name = bfd_elf_string_from_elf_section (input_bfd,
6009 symtab_hdr->sh_link,
6010 cmse_sym->st_name);
baf46cd7
AM		 6011 if (!sym_name || !CONST_STRNEQ (sym_name, CMSE_PREFIX))
6012 continue;
6013
4ba2ef8f
TP		 6014 /* Special symbol with local binding. */
6015 cmse_invalid = TRUE;
6016 }
6017 else
6018 {
6019 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
6020 sym_name = (char *) cmse_hash->root.root.root.string;
baf46cd7 6021 if (!CONST_STRNEQ (sym_name, CMSE_PREFIX))
4ba2ef8f
TP		 6022 continue;
6023
6024 /* Special symbol has incorrect binding or type. */
6025 if ((cmse_hash->root.root.type != bfd_link_hash_defined
6026 && cmse_hash->root.root.type != bfd_link_hash_defweak)
6027 || cmse_hash->root.type != STT_FUNC)
6028 cmse_invalid = TRUE;
6029 }
6030
6031 if (!is_v8m)
6032 {
90b6238f
AM		 6033 _bfd_error_handler (_("%pB: special symbol `%s' only allowed for "
6034 "ARMv8-M architecture or later"),
4eca0228 6035 input_bfd, sym_name);
4ba2ef8f
TP		 6036 is_v8m = TRUE; /* Avoid multiple warning. */
6037 ret = FALSE;
6038 }
6039
6040 if (cmse_invalid)
6041 {
90b6238f
AM		 6042 _bfd_error_handler (_("%pB: invalid special symbol `%s'; it must be"
6043 " a global or weak function symbol"),
4eca0228 6044 input_bfd, sym_name);
4ba2ef8f
TP		 6045 ret = FALSE;
6046 if (i < ext_start)
6047 continue;
6048 }
6049
6050 sym_name += strlen (CMSE_PREFIX);
6051 hash = (struct elf32_arm_link_hash_entry *)
6052 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6053
6054 /* No associated normal symbol or it is neither global nor weak. */
6055 if (!hash
6056 || (hash->root.root.type != bfd_link_hash_defined
6057 && hash->root.root.type != bfd_link_hash_defweak)
6058 || hash->root.type != STT_FUNC)
6059 {
6060 /* Initialize here to avoid warning about use of possibly
6061 uninitialized variable. */
6062 j = 0;
6063
6064 if (!hash)
6065 {
6066 /* Searching for a normal symbol with local binding. */
6067 for (; j < ext_start; j++)
6068 {
6069 lsym_name =
6070 bfd_elf_string_from_elf_section (input_bfd,
6071 symtab_hdr->sh_link,
6072 local_syms[j].st_name);
6073 if (!strcmp (sym_name, lsym_name))
6074 break;
6075 }
6076 }
6077
6078 if (hash || j < ext_start)
6079 {
4eca0228 6080 _bfd_error_handler
90b6238f
AM		 6081 (_("%pB: invalid standard symbol `%s'; it must be "
6082 "a global or weak function symbol"),
6083 input_bfd, sym_name);
4ba2ef8f
TP		 6084 }
6085 else
4eca0228 6086 _bfd_error_handler
90b6238f 6087 (_("%pB: absent standard symbol `%s'"), input_bfd, sym_name);
4ba2ef8f
TP		 6088 ret = FALSE;
6089 if (!hash)
6090 continue;
6091 }
6092
6093 sym_value = hash->root.root.u.def.value;
6094 section = hash->root.root.u.def.section;
6095
6096 if (cmse_hash->root.root.u.def.section != section)
6097 {
4eca0228 6098 _bfd_error_handler
90b6238f 6099 (_("%pB: `%s' and its special symbol are in different sections"),
4ba2ef8f
TP		 6100 input_bfd, sym_name);
6101 ret = FALSE;
6102 }
6103 if (cmse_hash->root.root.u.def.value != sym_value)
6104 continue; /* Ignore: could be an entry function starting with SG. */
6105
6106 /* If this section is a link-once section that will be discarded, then
6107 don't create any stubs. */
6108 if (section->output_section == NULL)
6109 {
4eca0228 6110 _bfd_error_handler
90b6238f 6111 (_("%pB: entry function `%s' not output"), input_bfd, sym_name);
4ba2ef8f
TP		 6112 continue;
6113 }
6114
6115 if (hash->root.size == 0)
6116 {
4eca0228 6117 _bfd_error_handler
90b6238f 6118 (_("%pB: entry function `%s' is empty"), input_bfd, sym_name);
4ba2ef8f
TP		 6119 ret = FALSE;
6120 }
6121
6122 if (!ret)
6123 continue;
6124 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 6125 stub_entry
4ba2ef8f
TP		 6126 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6127 NULL, NULL, section, hash, sym_name,
6128 sym_value, branch_type, &new_stub);
6129
0955507f 6130 if (stub_entry == NULL)
4ba2ef8f
TP		 6131 ret = FALSE;
6132 else
6133 {
6134 BFD_ASSERT (new_stub);
0955507f 6135 (*cmse_stub_created)++;
4ba2ef8f
TP		 6136 }
6137 }
6138
6139 if (!symtab_hdr->contents)
6140 free (local_syms);
6141 return ret;
6142}
6143
0955507f
TP		 6144/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6145 code entry function, ie can be called from non secure code without using a
6146 veneer. */
6147
6148static bfd_boolean
6149cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
6150{
42484486 6151 bfd_byte contents[4];
0955507f
TP		 6152 uint32_t first_insn;
6153 asection *section;
6154 file_ptr offset;
6155 bfd *abfd;
6156
6157 /* Defined symbol of function type. */
6158 if (hash->root.root.type != bfd_link_hash_defined
6159 && hash->root.root.type != bfd_link_hash_defweak)
6160 return FALSE;
6161 if (hash->root.type != STT_FUNC)
6162 return FALSE;
6163
6164 /* Read first instruction. */
6165 section = hash->root.root.u.def.section;
6166 abfd = section->owner;
6167 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 6168 if (!bfd_get_section_contents (abfd, section, contents, offset,
6169 sizeof (contents)))
0955507f
TP		 6170 return FALSE;
6171
42484486
TP		 6172 first_insn = bfd_get_32 (abfd, contents);
6173
6174 /* Starts by SG instruction. */
0955507f
TP		 6175 return first_insn == 0xe97fe97f;
6176}
6177
6178/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6179 secure gateway veneers (ie. the veneers was not in the input import library)
6180 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6181
6182static bfd_boolean
6183arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
6184{
6185 struct elf32_arm_stub_hash_entry *stub_entry;
6186 struct bfd_link_info *info;
6187
6188 /* Massage our args to the form they really have. */
6189 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
6190 info = (struct bfd_link_info *) gen_info;
6191
6192 if (info->out_implib_bfd)
6193 return TRUE;
6194
6195 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
6196 return TRUE;
6197
6198 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 6199 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 6200
6201 return TRUE;
6202}
6203
6204/* Set offset of each secure gateway veneers so that its address remain
6205 identical to the one in the input import library referred by
6206 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6207 (present in input import library but absent from the executable being
6208 linked) or if new veneers appeared and there is no output import library
6209 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6210 number of secure gateway veneers found in the input import library.
6211
6212 The function returns whether an error occurred. If no error occurred,
6213 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6214 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6215 veneer observed set for new veneers to be layed out after. */
6216
6217static bfd_boolean
6218set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
6219 struct elf32_arm_link_hash_table *htab,
6220 int *cmse_stub_created)
6221{
6222 long symsize;
6223 char *sym_name;
6224 flagword flags;
6225 long i, symcount;
6226 bfd *in_implib_bfd;
6227 asection *stub_out_sec;
6228 bfd_boolean ret = TRUE;
6229 Elf_Internal_Sym *intsym;
6230 const char *out_sec_name;
6231 bfd_size_type cmse_stub_size;
6232 asymbol **sympp = NULL, *sym;
6233 struct elf32_arm_link_hash_entry *hash;
6234 const insn_sequence *cmse_stub_template;
6235 struct elf32_arm_stub_hash_entry *stub_entry;
6236 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
6237 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
6238 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
6239
6240 /* No input secure gateway import library. */
6241 if (!htab->in_implib_bfd)
6242 return TRUE;
6243
6244 in_implib_bfd = htab->in_implib_bfd;
6245 if (!htab->cmse_implib)
6246 {
871b3ab2 6247 _bfd_error_handler (_("%pB: --in-implib only supported for Secure "
90b6238f 6248 "Gateway import libraries"), in_implib_bfd);
0955507f
TP		 6249 return FALSE;
6250 }
6251
6252 /* Get symbol table size. */
6253 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
6254 if (symsize < 0)
6255 return FALSE;
6256
6257 /* Read in the input secure gateway import library's symbol table. */
6258 sympp = (asymbol **) xmalloc (symsize);
6259 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
6260 if (symcount < 0)
6261 {
6262 ret = FALSE;
6263 goto free_sym_buf;
6264 }
6265
6266 htab->new_cmse_stub_offset = 0;
6267 cmse_stub_size =
6268 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
6269 &cmse_stub_template,
6270 &cmse_stub_template_size);
6271 out_sec_name =
6272 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
6273 stub_out_sec =
6274 bfd_get_section_by_name (htab->obfd, out_sec_name);
6275 if (stub_out_sec != NULL)
6276 cmse_stub_sec_vma = stub_out_sec->vma;
6277
6278 /* Set addresses of veneers mentionned in input secure gateway import
6279 library's symbol table. */
6280 for (i = 0; i < symcount; i++)
6281 {
6282 sym = sympp[i];
6283 flags = sym->flags;
6284 sym_name = (char *) bfd_asymbol_name (sym);
6285 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
6286
6287 if (sym->section != bfd_abs_section_ptr
6288 || !(flags & (BSF_GLOBAL | BSF_WEAK))
6289 || (flags & BSF_FUNCTION) != BSF_FUNCTION
6290 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
6291 != ST_BRANCH_TO_THUMB))
6292 {
90b6238f
AM		 6293 _bfd_error_handler (_("%pB: invalid import library entry: `%s'; "
6294 "symbol should be absolute, global and "
6295 "refer to Thumb functions"),
4eca0228 6296 in_implib_bfd, sym_name);
0955507f
TP		 6297 ret = FALSE;
6298 continue;
6299 }
6300
6301 veneer_value = bfd_asymbol_value (sym);
6302 stub_offset = veneer_value - cmse_stub_sec_vma;
6303 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
6304 FALSE, FALSE);
6305 hash = (struct elf32_arm_link_hash_entry *)
6306 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6307
6308 /* Stub entry should have been created by cmse_scan or the symbol be of
6309 a secure function callable from non secure code. */
6310 if (!stub_entry && !hash)
6311 {
6312 bfd_boolean new_stub;
6313
4eca0228 6314 _bfd_error_handler
90b6238f 6315 (_("entry function `%s' disappeared from secure code"), sym_name);
0955507f
TP		 6316 hash = (struct elf32_arm_link_hash_entry *)
6317 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
6318 stub_entry
6319 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6320 NULL, NULL, bfd_abs_section_ptr, hash,
6321 sym_name, veneer_value,
6322 ST_BRANCH_TO_THUMB, &new_stub);
6323 if (stub_entry == NULL)
6324 ret = FALSE;
6325 else
6326 {
6327 BFD_ASSERT (new_stub);
6328 new_cmse_stubs_created++;
6329 (*cmse_stub_created)++;
6330 }
6331 stub_entry->stub_template_size = stub_entry->stub_size = 0;
6332 stub_entry->stub_offset = stub_offset;
6333 }
6334 /* Symbol found is not callable from non secure code. */
6335 else if (!stub_entry)
6336 {
6337 if (!cmse_entry_fct_p (hash))
6338 {
90b6238f 6339 _bfd_error_handler (_("`%s' refers to a non entry function"),
4eca0228 6340 sym_name);
0955507f
TP		 6341 ret = FALSE;
6342 }
6343 continue;
6344 }
6345 else
6346 {
6347 /* Only stubs for SG veneers should have been created. */
6348 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
6349
6350 /* Check visibility hasn't changed. */
6351 if (!!(flags & BSF_GLOBAL)
6352 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6353 _bfd_error_handler
90b6238f 6354 (_("%pB: visibility of symbol `%s' has changed"), in_implib_bfd,
0955507f
TP		 6355 sym_name);
6356
6357 stub_entry->stub_offset = stub_offset;
6358 }
6359
6360 /* Size should match that of a SG veneer. */
6361 if (intsym->st_size != cmse_stub_size)
6362 {
90b6238f 6363 _bfd_error_handler (_("%pB: incorrect size for symbol `%s'"),
4eca0228 6364 in_implib_bfd, sym_name);
0955507f
TP		 6365 ret = FALSE;
6366 }
6367
6368 /* Previous veneer address is before current SG veneer section. */
6369 if (veneer_value < cmse_stub_sec_vma)
6370 {
6371 /* Avoid offset underflow. */
6372 if (stub_entry)
6373 stub_entry->stub_offset = 0;
6374 stub_offset = 0;
6375 ret = FALSE;
6376 }
6377
6378 /* Complain if stub offset not a multiple of stub size. */
6379 if (stub_offset % cmse_stub_size)
6380 {
4eca0228 6381 _bfd_error_handler
90b6238f
AM		 6382 (_("offset of veneer for entry function `%s' not a multiple of "
6383 "its size"), sym_name);
0955507f
TP		 6384 ret = FALSE;
6385 }
6386
6387 if (!ret)
6388 continue;
6389
6390 new_cmse_stubs_created--;
6391 if (veneer_value < cmse_stub_array_start)
6392 cmse_stub_array_start = veneer_value;
6393 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6394 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6395 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6396 }
6397
6398 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6399 {
6400 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6401 _bfd_error_handler
0955507f
TP		 6402 (_("new entry function(s) introduced but no output import library "
6403 "specified:"));
6404 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6405 }
6406
6407 if (cmse_stub_array_start != cmse_stub_sec_vma)
6408 {
4eca0228 6409 _bfd_error_handler
90b6238f 6410 (_("start address of `%s' is different from previous link"),
0955507f
TP		 6411 out_sec_name);
6412 ret = FALSE;
6413 }
6414
6415free_sym_buf:
6416 free (sympp);
6417 return ret;
6418}
6419
906e58ca
NC		 6420/* Determine and set the size of the stub section for a final link.
6421
6422 The basic idea here is to examine all the relocations looking for
6423 PC-relative calls to a target that is unreachable with a "bl"
6424 instruction. */
6425
6426bfd_boolean
6427elf32_arm_size_stubs (bfd *output_bfd,
6428 bfd *stub_bfd,
6429 struct bfd_link_info *info,
6430 bfd_signed_vma group_size,
7a89b94e 6431 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6432 asection *,
7a89b94e 6433 unsigned int),
906e58ca
NC		 6434 void (*layout_sections_again) (void))
6435{
0955507f 6436 bfd_boolean ret = TRUE;
4ba2ef8f 6437 obj_attribute *out_attr;
0955507f 6438 int cmse_stub_created = 0;
906e58ca 6439 bfd_size_type stub_group_size;
4ba2ef8f 6440 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6441 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6442 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6443 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6444 struct a8_erratum_reloc *a8_relocs = NULL;
6445 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6446
4dfe6ac6
NC		 6447 if (htab == NULL)
6448 return FALSE;
6449
48229727
JB		 6450 if (htab->fix_cortex_a8)
6451 {
21d799b5 6452 a8_fixes = (struct a8_erratum_fix *)
99059e56 6453 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6454 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6455 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6456 }
906e58ca
NC		 6457
6458 /* Propagate mach to stub bfd, because it may not have been
6459 finalized when we created stub_bfd. */
6460 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6461 bfd_get_mach (output_bfd));
6462
6463 /* Stash our params away. */
6464 htab->stub_bfd = stub_bfd;
6465 htab->add_stub_section = add_stub_section;
6466 htab->layout_sections_again = layout_sections_again;
07d72278 6467 stubs_always_after_branch = group_size < 0;
48229727 6468
4ba2ef8f
TP		 6469 out_attr = elf_known_obj_attributes_proc (output_bfd);
6470 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6471
48229727
JB		 6472 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6473 as the first half of a 32-bit branch straddling two 4K pages. This is a
6474 crude way of enforcing that. */
6475 if (htab->fix_cortex_a8)
6476 stubs_always_after_branch = 1;
6477
906e58ca
NC		 6478 if (group_size < 0)
6479 stub_group_size = -group_size;
6480 else
6481 stub_group_size = group_size;
6482
6483 if (stub_group_size == 1)
6484 {
6485 /* Default values. */
6486 /* Thumb branch range is +-4MB has to be used as the default
6487 maximum size (a given section can contain both ARM and Thumb
6488 code, so the worst case has to be taken into account).
6489
6490 This value is 24K less than that, which allows for 2025
6491 12-byte stubs. If we exceed that, then we will fail to link.
6492 The user will have to relink with an explicit group size
6493 option. */
6494 stub_group_size = 4170000;
6495 }
6496
07d72278 6497 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6498
3ae046cc
NS		 6499 /* If we're applying the cortex A8 fix, we need to determine the
6500 program header size now, because we cannot change it later --
6501 that could alter section placements. Notice the A8 erratum fix
6502 ends up requiring the section addresses to remain unchanged
6503 modulo the page size. That's something we cannot represent
6504 inside BFD, and we don't want to force the section alignment to
6505 be the page size. */
6506 if (htab->fix_cortex_a8)
6507 (*htab->layout_sections_again) ();
6508
906e58ca
NC		 6509 while (1)
6510 {
6511 bfd *input_bfd;
6512 unsigned int bfd_indx;
6513 asection *stub_sec;
d7c5bd02 6514 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6515 bfd_boolean stub_changed = FALSE;
6516 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6517
48229727 6518 num_a8_fixes = 0;
906e58ca
NC		 6519 for (input_bfd = info->input_bfds, bfd_indx = 0;
6520 input_bfd != NULL;
c72f2fb2 6521 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6522 {
6523 Elf_Internal_Shdr *symtab_hdr;
6524 asection *section;
6525 Elf_Internal_Sym *local_syms = NULL;
6526
8c246a60
AM		 6527 if (!is_arm_elf (input_bfd)
6528 || (elf_dyn_lib_class (input_bfd) & DYN_AS_NEEDED) != 0)
99059e56 6529 continue;
adbcc655 6530
48229727
JB		 6531 num_a8_relocs = 0;
6532
906e58ca
NC		 6533 /* We'll need the symbol table in a second. */
6534 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6535 if (symtab_hdr->sh_info == 0)
6536 continue;
6537
4ba2ef8f
TP		 6538 /* Limit scan of symbols to object file whose profile is
6539 Microcontroller to not hinder performance in the general case. */
6540 if (m_profile && first_veneer_scan)
6541 {
6542 struct elf_link_hash_entry **sym_hashes;
6543
6544 sym_hashes = elf_sym_hashes (input_bfd);
6545 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6546 &cmse_stub_created))
4ba2ef8f 6547 goto error_ret_free_local;
0955507f
TP		 6548
6549 if (cmse_stub_created != 0)
6550 stub_changed = TRUE;
4ba2ef8f
TP		 6551 }
6552
906e58ca
NC		 6553 /* Walk over each section attached to the input bfd. */
6554 for (section = input_bfd->sections;
6555 section != NULL;
6556 section = section->next)
6557 {
6558 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6559
6560 /* If there aren't any relocs, then there's nothing more
6561 to do. */
6562 if ((section->flags & SEC_RELOC) == 0
6563 || section->reloc_count == 0
6564 || (section->flags & SEC_CODE) == 0)
6565 continue;
6566
6567 /* If this section is a link-once section that will be
6568 discarded, then don't create any stubs. */
6569 if (section->output_section == NULL
6570 || section->output_section->owner != output_bfd)
6571 continue;
6572
6573 /* Get the relocs. */
6574 internal_relocs
6575 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6576 NULL, info->keep_memory);
6577 if (internal_relocs == NULL)
6578 goto error_ret_free_local;
6579
6580 /* Now examine each relocation. */
6581 irela = internal_relocs;
6582 irelaend = irela + section->reloc_count;
6583 for (; irela < irelaend; irela++)
6584 {
6585 unsigned int r_type, r_indx;
906e58ca
NC		 6586 asection *sym_sec;
6587 bfd_vma sym_value;
6588 bfd_vma destination;
6589 struct elf32_arm_link_hash_entry *hash;
7413f23f 6590 const char *sym_name;
34e77a92 6591 unsigned char st_type;
35fc36a8 6592 enum arm_st_branch_type branch_type;
48229727 6593 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6594
6595 r_type = ELF32_R_TYPE (irela->r_info);
6596 r_indx = ELF32_R_SYM (irela->r_info);
6597
6598 if (r_type >= (unsigned int) R_ARM_max)
6599 {
6600 bfd_set_error (bfd_error_bad_value);
6601 error_ret_free_internal:
6602 if (elf_section_data (section)->relocs == NULL)
6603 free (internal_relocs);
15dd01b1
TP		 6604 /* Fall through. */
6605 error_ret_free_local:
6606 if (local_syms != NULL
6607 && (symtab_hdr->contents
6608 != (unsigned char *) local_syms))
6609 free (local_syms);
6610 return FALSE;
906e58ca 6611 }
b38cadfb 6612
0855e32b
NS		 6613 hash = NULL;
6614 if (r_indx >= symtab_hdr->sh_info)
6615 hash = elf32_arm_hash_entry
6616 (elf_sym_hashes (input_bfd)
6617 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6618
0855e32b
NS		 6619 /* Only look for stubs on branch instructions, or
6620 non-relaxed TLSCALL */
906e58ca 6621 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6622 && (r_type != (unsigned int) R_ARM_THM_CALL)
6623 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6624 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6625 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6626 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6627 && (r_type != (unsigned int) R_ARM_PLT32)
6628 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6629 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6630 && r_type == elf32_arm_tls_transition
6631 (info, r_type, &hash->root)
6632 && ((hash ? hash->tls_type
6633 : (elf32_arm_local_got_tls_type
6634 (input_bfd)[r_indx]))
6635 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6636 continue;
6637
6638 /* Now determine the call target, its name, value,
6639 section. */
6640 sym_sec = NULL;
6641 sym_value = 0;
6642 destination = 0;
7413f23f 6643 sym_name = NULL;
b38cadfb 6644
0855e32b
NS		 6645 if (r_type == (unsigned int) R_ARM_TLS_CALL
6646 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6647 {
6648 /* A non-relaxed TLS call. The target is the
6649 plt-resident trampoline and nothing to do
6650 with the symbol. */
6651 BFD_ASSERT (htab->tls_trampoline > 0);
6652 sym_sec = htab->root.splt;
6653 sym_value = htab->tls_trampoline;
6654 hash = 0;
34e77a92 6655 st_type = STT_FUNC;
35fc36a8 6656 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6657 }
6658 else if (!hash)
906e58ca
NC		 6659 {
6660 /* It's a local symbol. */
6661 Elf_Internal_Sym *sym;
906e58ca
NC		 6662
6663 if (local_syms == NULL)
6664 {
6665 local_syms
6666 = (Elf_Internal_Sym *) symtab_hdr->contents;
6667 if (local_syms == NULL)
6668 local_syms
6669 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6670 symtab_hdr->sh_info, 0,
6671 NULL, NULL, NULL);
6672 if (local_syms == NULL)
6673 goto error_ret_free_internal;
6674 }
6675
6676 sym = local_syms + r_indx;
f6d250ce
TS		 6677 if (sym->st_shndx == SHN_UNDEF)
6678 sym_sec = bfd_und_section_ptr;
6679 else if (sym->st_shndx == SHN_ABS)
6680 sym_sec = bfd_abs_section_ptr;
6681 else if (sym->st_shndx == SHN_COMMON)
6682 sym_sec = bfd_com_section_ptr;
6683 else
6684 sym_sec =
6685 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6686
ffcb4889
NS		 6687 if (!sym_sec)
6688 /* This is an undefined symbol. It can never
6a631e86 6689 be resolved. */
ffcb4889 6690 continue;
fe33d2fa 6691
906e58ca
NC		 6692 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6693 sym_value = sym->st_value;
6694 destination = (sym_value + irela->r_addend
6695 + sym_sec->output_offset
6696 + sym_sec->output_section->vma);
34e77a92 6697 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6698 branch_type =
6699 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6700 sym_name
6701 = bfd_elf_string_from_elf_section (input_bfd,
6702 symtab_hdr->sh_link,
6703 sym->st_name);
906e58ca
NC		 6704 }
6705 else
6706 {
6707 /* It's an external symbol. */
906e58ca
NC		 6708 while (hash->root.root.type == bfd_link_hash_indirect
6709 || hash->root.root.type == bfd_link_hash_warning)
6710 hash = ((struct elf32_arm_link_hash_entry *)
6711 hash->root.root.u.i.link);
6712
6713 if (hash->root.root.type == bfd_link_hash_defined
6714 || hash->root.root.type == bfd_link_hash_defweak)
6715 {
6716 sym_sec = hash->root.root.u.def.section;
6717 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6718
6719 struct elf32_arm_link_hash_table *globals =
6720 elf32_arm_hash_table (info);
6721
6722 /* For a destination in a shared library,
6723 use the PLT stub as target address to
6724 decide whether a branch stub is
6725 needed. */
4dfe6ac6 6726 if (globals != NULL
362d30a1 6727 && globals->root.splt != NULL
4dfe6ac6 6728 && hash != NULL
022f8312
CL		 6729 && hash->root.plt.offset != (bfd_vma) -1)
6730 {
362d30a1 6731 sym_sec = globals->root.splt;
022f8312
CL		 6732 sym_value = hash->root.plt.offset;
6733 if (sym_sec->output_section != NULL)
6734 destination = (sym_value
6735 + sym_sec->output_offset
6736 + sym_sec->output_section->vma);
6737 }
6738 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6739 destination = (sym_value + irela->r_addend
6740 + sym_sec->output_offset
6741 + sym_sec->output_section->vma);
6742 }
69c5861e
CL		 6743 else if ((hash->root.root.type == bfd_link_hash_undefined)
6744 || (hash->root.root.type == bfd_link_hash_undefweak))
6745 {
6746 /* For a shared library, use the PLT stub as
6747 target address to decide whether a long
6748 branch stub is needed.
6749 For absolute code, they cannot be handled. */
6750 struct elf32_arm_link_hash_table *globals =
6751 elf32_arm_hash_table (info);
6752
4dfe6ac6 6753 if (globals != NULL
362d30a1 6754 && globals->root.splt != NULL
4dfe6ac6 6755 && hash != NULL
69c5861e
CL		 6756 && hash->root.plt.offset != (bfd_vma) -1)
6757 {
362d30a1 6758 sym_sec = globals->root.splt;
69c5861e
CL		 6759 sym_value = hash->root.plt.offset;
6760 if (sym_sec->output_section != NULL)
6761 destination = (sym_value
6762 + sym_sec->output_offset
6763 + sym_sec->output_section->vma);
6764 }
6765 else
6766 continue;
6767 }
906e58ca
NC		 6768 else
6769 {
6770 bfd_set_error (bfd_error_bad_value);
6771 goto error_ret_free_internal;
6772 }
34e77a92 6773 st_type = hash->root.type;
39d911fc
TP		 6774 branch_type =
6775 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6776 sym_name = hash->root.root.root.string;
906e58ca
NC		 6777 }
6778
48229727 6779 do
7413f23f 6780 {
b715f643 6781 bfd_boolean new_stub;
0955507f 6782 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6783
48229727
JB		 6784 /* Determine what (if any) linker stub is needed. */
6785 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6786 st_type, &branch_type,
6787 hash, destination, sym_sec,
48229727
JB		 6788 input_bfd, sym_name);
6789 if (stub_type == arm_stub_none)
6790 break;
6791
48229727
JB		 6792 /* We've either created a stub for this reloc already,
6793 or we are about to. */
0955507f 6794 stub_entry =
b715f643
TP		 6795 elf32_arm_create_stub (htab, stub_type, section, irela,
6796 sym_sec, hash,
6797 (char *) sym_name, sym_value,
6798 branch_type, &new_stub);
7413f23f 6799
0955507f 6800 created_stub = stub_entry != NULL;
b715f643
TP		 6801 if (!created_stub)
6802 goto error_ret_free_internal;
6803 else if (!new_stub)
6804 break;
99059e56 6805 else
b715f643 6806 stub_changed = TRUE;
99059e56
RM		 6807 }
6808 while (0);
6809
6810 /* Look for relocations which might trigger Cortex-A8
6811 erratum. */
6812 if (htab->fix_cortex_a8
6813 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6814 || r_type == (unsigned int) R_ARM_THM_JUMP19
6815 || r_type == (unsigned int) R_ARM_THM_CALL
6816 || r_type == (unsigned int) R_ARM_THM_XPC22))
6817 {
6818 bfd_vma from = section->output_section->vma
6819 + section->output_offset
6820 + irela->r_offset;
6821
6822 if ((from & 0xfff) == 0xffe)
6823 {
6824 /* Found a candidate. Note we haven't checked the
6825 destination is within 4K here: if we do so (and
6826 don't create an entry in a8_relocs) we can't tell
6827 that a branch should have been relocated when
6828 scanning later. */
6829 if (num_a8_relocs == a8_reloc_table_size)
6830 {
6831 a8_reloc_table_size *= 2;
6832 a8_relocs = (struct a8_erratum_reloc *)
6833 bfd_realloc (a8_relocs,
6834 sizeof (struct a8_erratum_reloc)
6835 * a8_reloc_table_size);
6836 }
6837
6838 a8_relocs[num_a8_relocs].from = from;
6839 a8_relocs[num_a8_relocs].destination = destination;
6840 a8_relocs[num_a8_relocs].r_type = r_type;
6841 a8_relocs[num_a8_relocs].branch_type = branch_type;
6842 a8_relocs[num_a8_relocs].sym_name = sym_name;
6843 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6844 a8_relocs[num_a8_relocs].hash = hash;
6845
6846 num_a8_relocs++;
6847 }
6848 }
906e58ca
NC		 6849 }
6850
99059e56
RM		 6851 /* We're done with the internal relocs, free them. */
6852 if (elf_section_data (section)->relocs == NULL)
6853 free (internal_relocs);
6854 }
48229727 6855
99059e56 6856 if (htab->fix_cortex_a8)
48229727 6857 {
99059e56
RM		 6858 /* Sort relocs which might apply to Cortex-A8 erratum. */
6859 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6860 sizeof (struct a8_erratum_reloc),
99059e56 6861 &a8_reloc_compare);
48229727 6862
99059e56
RM		 6863 /* Scan for branches which might trigger Cortex-A8 erratum. */
6864 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6865 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6866 a8_relocs, num_a8_relocs,
6867 prev_num_a8_fixes, &stub_changed)
6868 != 0)
48229727 6869 goto error_ret_free_local;
5e681ec4 6870 }
7f991970
AM		 6871
6872 if (local_syms != NULL
6873 && symtab_hdr->contents != (unsigned char *) local_syms)
6874 {
6875 if (!info->keep_memory)
6876 free (local_syms);
6877 else
6878 symtab_hdr->contents = (unsigned char *) local_syms;
6879 }
5e681ec4
PB		 6880 }
6881
0955507f
TP		 6882 if (first_veneer_scan
6883 && !set_cmse_veneer_addr_from_implib (info, htab,
6884 &cmse_stub_created))
6885 ret = FALSE;
6886
eb7c4339 6887 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6888 stub_changed = TRUE;
48229727 6889
906e58ca
NC		 6890 if (!stub_changed)
6891 break;
5e681ec4 6892
906e58ca
NC		 6893 /* OK, we've added some stubs. Find out the new size of the
6894 stub sections. */
6895 for (stub_sec = htab->stub_bfd->sections;
6896 stub_sec != NULL;
6897 stub_sec = stub_sec->next)
3e6b1042
DJ		 6898 {
6899 /* Ignore non-stub sections. */
6900 if (!strstr (stub_sec->name, STUB_SUFFIX))
6901 continue;
6902
6903 stub_sec->size = 0;
6904 }
b34b2d70 6905
0955507f
TP		 6906 /* Add new SG veneers after those already in the input import
6907 library. */
6908 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6909 stub_type++)
6910 {
6911 bfd_vma *start_offset_p;
6912 asection **stub_sec_p;
6913
6914 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6915 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6916 if (start_offset_p == NULL)
6917 continue;
6918
6919 BFD_ASSERT (stub_sec_p != NULL);
6920 if (*stub_sec_p != NULL)
6921 (*stub_sec_p)->size = *start_offset_p;
6922 }
6923
d7c5bd02 6924 /* Compute stub section size, considering padding. */
906e58ca 6925 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6926 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6927 stub_type++)
6928 {
6929 int size, padding;
6930 asection **stub_sec_p;
6931
6932 padding = arm_dedicated_stub_section_padding (stub_type);
6933 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6934 /* Skip if no stub input section or no stub section padding
6935 required. */
6936 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6937 continue;
6938 /* Stub section padding required but no dedicated section. */
6939 BFD_ASSERT (stub_sec_p);
6940
6941 size = (*stub_sec_p)->size;
6942 size = (size + padding - 1) & ~(padding - 1);
6943 (*stub_sec_p)->size = size;
6944 }
906e58ca 6945
48229727
JB		 6946 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6947 if (htab->fix_cortex_a8)
99059e56
RM		 6948 for (i = 0; i < num_a8_fixes; i++)
6949 {
48229727 6950 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6951 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6952
6953 if (stub_sec == NULL)
7f991970 6954 return FALSE;
48229727 6955
99059e56
RM		 6956 stub_sec->size
6957 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6958 NULL);
6959 }
48229727
JB		 6960
6961
906e58ca
NC		 6962 /* Ask the linker to do its stuff. */
6963 (*htab->layout_sections_again) ();
4ba2ef8f 6964 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6965 }
6966
48229727
JB		 6967 /* Add stubs for Cortex-A8 erratum fixes now. */
6968 if (htab->fix_cortex_a8)
6969 {
6970 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6971 {
6972 struct elf32_arm_stub_hash_entry *stub_entry;
6973 char *stub_name = a8_fixes[i].stub_name;
6974 asection *section = a8_fixes[i].section;
6975 unsigned int section_id = a8_fixes[i].section->id;
6976 asection *link_sec = htab->stub_group[section_id].link_sec;
6977 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6978 const insn_sequence *template_sequence;
6979 int template_size, size = 0;
6980
6981 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6982 TRUE, FALSE);
6983 if (stub_entry == NULL)
6984 {
871b3ab2 6985 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 6986 section->owner, stub_name);
99059e56
RM		 6987 return FALSE;
6988 }
6989
6990 stub_entry->stub_sec = stub_sec;
0955507f 6991 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6992 stub_entry->id_sec = link_sec;
6993 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6994 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6995 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6996 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6997 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6998 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6999
99059e56
RM		 7000 size = find_stub_size_and_template (a8_fixes[i].stub_type,
7001 &template_sequence,
7002 &template_size);
48229727 7003
99059e56
RM		 7004 stub_entry->stub_size = size;
7005 stub_entry->stub_template = template_sequence;
7006 stub_entry->stub_template_size = template_size;
7007 }
48229727
JB		 7008
7009 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 7010 elf32_arm_write_section(). */
48229727
JB		 7011 htab->a8_erratum_fixes = a8_fixes;
7012 htab->num_a8_erratum_fixes = num_a8_fixes;
7013 }
7014 else
7015 {
7016 htab->a8_erratum_fixes = NULL;
7017 htab->num_a8_erratum_fixes = 0;
7018 }
0955507f 7019 return ret;
5e681ec4
PB		 7020}
7021
906e58ca
NC		 7022/* Build all the stubs associated with the current output file. The
7023 stubs are kept in a hash table attached to the main linker hash
7024 table. We also set up the .plt entries for statically linked PIC
7025 functions here. This function is called via arm_elf_finish in the
7026 linker. */
252b5132 7027
906e58ca
NC		 7028bfd_boolean
7029elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 7030{
906e58ca
NC		 7031 asection *stub_sec;
7032 struct bfd_hash_table *table;
0955507f 7033 enum elf32_arm_stub_type stub_type;
906e58ca 7034 struct elf32_arm_link_hash_table *htab;
252b5132 7035
906e58ca 7036 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 7037 if (htab == NULL)
7038 return FALSE;
252b5132 7039
906e58ca
NC		 7040 for (stub_sec = htab->stub_bfd->sections;
7041 stub_sec != NULL;
7042 stub_sec = stub_sec->next)
252b5132 7043 {
906e58ca
NC		 7044 bfd_size_type size;
7045
8029a119 7046 /* Ignore non-stub sections. */
906e58ca
NC		 7047 if (!strstr (stub_sec->name, STUB_SUFFIX))
7048 continue;
7049
d7c5bd02 7050 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 7051 must at least be done for stub section requiring padding and for SG
7052 veneers to ensure that a non secure code branching to a removed SG
7053 veneer causes an error. */
906e58ca 7054 size = stub_sec->size;
21d799b5 7055 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 7056 if (stub_sec->contents == NULL && size != 0)
7057 return FALSE;
0955507f 7058
906e58ca 7059 stub_sec->size = 0;
252b5132
RH		 7060 }
7061
0955507f
TP		 7062 /* Add new SG veneers after those already in the input import library. */
7063 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7064 {
7065 bfd_vma *start_offset_p;
7066 asection **stub_sec_p;
7067
7068 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
7069 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
7070 if (start_offset_p == NULL)
7071 continue;
7072
7073 BFD_ASSERT (stub_sec_p != NULL);
7074 if (*stub_sec_p != NULL)
7075 (*stub_sec_p)->size = *start_offset_p;
7076 }
7077
906e58ca
NC		 7078 /* Build the stubs as directed by the stub hash table. */
7079 table = &htab->stub_hash_table;
7080 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 7081 if (htab->fix_cortex_a8)
7082 {
7083 /* Place the cortex a8 stubs last. */
7084 htab->fix_cortex_a8 = -1;
7085 bfd_hash_traverse (table, arm_build_one_stub, info);
7086 }
252b5132 7087
906e58ca 7088 return TRUE;
252b5132
RH		 7089}
7090
9b485d32
NC		 7091/* Locate the Thumb encoded calling stub for NAME. */
7092
252b5132 7093static struct elf_link_hash_entry *
57e8b36a
NC		 7094find_thumb_glue (struct bfd_link_info *link_info,
7095 const char *name,
f2a9dd69 7096 char **error_message)
252b5132
RH		 7097{
7098 char *tmp_name;
7099 struct elf_link_hash_entry *hash;
7100 struct elf32_arm_link_hash_table *hash_table;
7101
7102 /* We need a pointer to the armelf specific hash table. */
7103 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7104 if (hash_table == NULL)
7105 return NULL;
252b5132 7106
21d799b5 7107 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7108 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7109
7110 BFD_ASSERT (tmp_name);
7111
7112 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
7113
7114 hash = elf_link_hash_lookup
b34976b6 7115 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7116
b1657152 7117 if (hash == NULL
90b6238f
AM		 7118 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7119 "Thumb", tmp_name, name) == -1)
b1657152 7120 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7121
7122 free (tmp_name);
7123
7124 return hash;
7125}
7126
9b485d32
NC		 7127/* Locate the ARM encoded calling stub for NAME. */
7128
252b5132 7129static struct elf_link_hash_entry *
57e8b36a
NC		 7130find_arm_glue (struct bfd_link_info *link_info,
7131 const char *name,
f2a9dd69 7132 char **error_message)
252b5132
RH		 7133{
7134 char *tmp_name;
7135 struct elf_link_hash_entry *myh;
7136 struct elf32_arm_link_hash_table *hash_table;
7137
7138 /* We need a pointer to the elfarm specific hash table. */
7139 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7140 if (hash_table == NULL)
7141 return NULL;
252b5132 7142
21d799b5 7143 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7144 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7145
7146 BFD_ASSERT (tmp_name);
7147
7148 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7149
7150 myh = elf_link_hash_lookup
b34976b6 7151 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7152
b1657152 7153 if (myh == NULL
90b6238f
AM		 7154 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7155 "ARM", tmp_name, name) == -1)
b1657152 7156 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7157
7158 free (tmp_name);
7159
7160 return myh;
7161}
7162
8f6277f5 7163/* ARM->Thumb glue (static images):
252b5132
RH		 7164
7165 .arm
7166 __func_from_arm:
7167 ldr r12, __func_addr
7168 bx r12
7169 __func_addr:
906e58ca 7170 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 7171
26079076
PB		 7172 (v5t static images)
7173 .arm
7174 __func_from_arm:
7175 ldr pc, __func_addr
7176 __func_addr:
906e58ca 7177 .word func @ behave as if you saw a ARM_32 reloc.
26079076 7178
8f6277f5
PB		 7179 (relocatable images)
7180 .arm
7181 __func_from_arm:
7182 ldr r12, __func_offset
7183 add r12, r12, pc
7184 bx r12
7185 __func_offset:
8029a119 7186 .word func - . */
8f6277f5
PB		 7187
7188#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 7189static const insn32 a2t1_ldr_insn = 0xe59fc000;
7190static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
7191static const insn32 a2t3_func_addr_insn = 0x00000001;
7192
26079076
PB		 7193#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7194static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
7195static const insn32 a2t2v5_func_addr_insn = 0x00000001;
7196
8f6277f5
PB		 7197#define ARM2THUMB_PIC_GLUE_SIZE 16
7198static const insn32 a2t1p_ldr_insn = 0xe59fc004;
7199static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
7200static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
7201
07d6d2b8 7202/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 7203
07d6d2b8
AM		 7204 .thumb .thumb
7205 .align 2 .align 2
7206 __func_from_thumb: __func_from_thumb:
7207 bx pc push {r6, lr}
7208 nop ldr r6, __func_addr
7209 .arm mov lr, pc
7210 b func bx r6
99059e56
RM		 7211 .arm
7212 ;; back_to_thumb
7213 ldmia r13! {r6, lr}
7214 bx lr
7215 __func_addr:
07d6d2b8 7216 .word func */
252b5132
RH		 7217
7218#define THUMB2ARM_GLUE_SIZE 8
7219static const insn16 t2a1_bx_pc_insn = 0x4778;
7220static const insn16 t2a2_noop_insn = 0x46c0;
7221static const insn32 t2a3_b_insn = 0xea000000;
7222
c7b8f16e 7223#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 7224#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7225#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 7226
845b51d6
PB		 7227#define ARM_BX_VENEER_SIZE 12
7228static const insn32 armbx1_tst_insn = 0xe3100001;
7229static const insn32 armbx2_moveq_insn = 0x01a0f000;
7230static const insn32 armbx3_bx_insn = 0xe12fff10;
7231
7e392df6 7232#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 7233static void
7234arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 7235{
7236 asection * s;
8029a119 7237 bfd_byte * contents;
252b5132 7238
8029a119 7239 if (size == 0)
3e6b1042
DJ		 7240 {
7241 /* Do not include empty glue sections in the output. */
7242 if (abfd != NULL)
7243 {
3d4d4302 7244 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 7245 if (s != NULL)
7246 s->flags |= SEC_EXCLUDE;
7247 }
7248 return;
7249 }
252b5132 7250
8029a119 7251 BFD_ASSERT (abfd != NULL);
252b5132 7252
3d4d4302 7253 s = bfd_get_linker_section (abfd, name);
8029a119 7254 BFD_ASSERT (s != NULL);
252b5132 7255
b0f4fbf8 7256 contents = (bfd_byte *) bfd_zalloc (abfd, size);
252b5132 7257
8029a119
NC		 7258 BFD_ASSERT (s->size == size);
7259 s->contents = contents;
7260}
906e58ca 7261
8029a119
NC		 7262bfd_boolean
7263bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
7264{
7265 struct elf32_arm_link_hash_table * globals;
906e58ca 7266
8029a119
NC		 7267 globals = elf32_arm_hash_table (info);
7268 BFD_ASSERT (globals != NULL);
906e58ca 7269
8029a119
NC		 7270 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7271 globals->arm_glue_size,
7272 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 7273
8029a119
NC		 7274 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7275 globals->thumb_glue_size,
7276 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 7277
8029a119
NC		 7278 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7279 globals->vfp11_erratum_glue_size,
7280 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 7281
a504d23a
LA		 7282 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7283 globals->stm32l4xx_erratum_glue_size,
7284 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7285
8029a119
NC		 7286 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7287 globals->bx_glue_size,
845b51d6
PB		 7288 ARM_BX_GLUE_SECTION_NAME);
7289
b34976b6 7290 return TRUE;
252b5132
RH		 7291}
7292
a4fd1a8e 7293/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 7294 returns the symbol identifying the stub. */
7295
a4fd1a8e 7296static struct elf_link_hash_entry *
57e8b36a
NC		 7297record_arm_to_thumb_glue (struct bfd_link_info * link_info,
7298 struct elf_link_hash_entry * h)
252b5132
RH		 7299{
7300 const char * name = h->root.root.string;
63b0f745 7301 asection * s;
252b5132
RH		 7302 char * tmp_name;
7303 struct elf_link_hash_entry * myh;
14a793b2 7304 struct bfd_link_hash_entry * bh;
252b5132 7305 struct elf32_arm_link_hash_table * globals;
dc810e39 7306 bfd_vma val;
2f475487 7307 bfd_size_type size;
252b5132
RH		 7308
7309 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 7310 BFD_ASSERT (globals != NULL);
7311 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7312
3d4d4302 7313 s = bfd_get_linker_section
252b5132
RH		 7314 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
7315
252b5132
RH		 7316 BFD_ASSERT (s != NULL);
7317
21d799b5 7318 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7319 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7320
7321 BFD_ASSERT (tmp_name);
7322
7323 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7324
7325 myh = elf_link_hash_lookup
b34976b6 7326 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 7327
7328 if (myh != NULL)
7329 {
9b485d32 7330 /* We've already seen this guy. */
252b5132 7331 free (tmp_name);
a4fd1a8e 7332 return myh;
252b5132
RH		 7333 }
7334
57e8b36a
NC		 7335 /* The only trick here is using hash_table->arm_glue_size as the value.
7336 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 7337 putting it. The +1 on the value marks that the stub has not been
7338 output yet - not that it is a Thumb function. */
14a793b2 7339 bh = NULL;
dc810e39
AM		 7340 val = globals->arm_glue_size + 1;
7341 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
7342 tmp_name, BSF_GLOBAL, s, val,
b34976b6 7343 NULL, TRUE, FALSE, &bh);
252b5132 7344
b7693d02
DJ		 7345 myh = (struct elf_link_hash_entry *) bh;
7346 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7347 myh->forced_local = 1;
7348
252b5132
RH		 7349 free (tmp_name);
7350
0e1862bb
L		 7351 if (bfd_link_pic (link_info)
7352 || globals->root.is_relocatable_executable
27e55c4d 7353 || globals->pic_veneer)
2f475487 7354 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7355 else if (globals->use_blx)
7356 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7357 else
2f475487
AM		 7358 size = ARM2THUMB_STATIC_GLUE_SIZE;
7359
7360 s->size += size;
7361 globals->arm_glue_size += size;
252b5132 7362
a4fd1a8e 7363 return myh;
252b5132
RH		 7364}
7365
845b51d6
PB		 7366/* Allocate space for ARMv4 BX veneers. */
7367
7368static void
7369record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7370{
7371 asection * s;
7372 struct elf32_arm_link_hash_table *globals;
7373 char *tmp_name;
7374 struct elf_link_hash_entry *myh;
7375 struct bfd_link_hash_entry *bh;
7376 bfd_vma val;
7377
7378 /* BX PC does not need a veneer. */
7379 if (reg == 15)
7380 return;
7381
7382 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7383 BFD_ASSERT (globals != NULL);
7384 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7385
7386 /* Check if this veneer has already been allocated. */
7387 if (globals->bx_glue_offset[reg])
7388 return;
7389
3d4d4302 7390 s = bfd_get_linker_section
845b51d6
PB		 7391 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7392
7393 BFD_ASSERT (s != NULL);
7394
7395 /* Add symbol for veneer. */
21d799b5
NC		 7396 tmp_name = (char *)
7397 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7398
845b51d6 7399 BFD_ASSERT (tmp_name);
906e58ca 7400
845b51d6 7401 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7402
845b51d6
PB		 7403 myh = elf_link_hash_lookup
7404 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7405
845b51d6 7406 BFD_ASSERT (myh == NULL);
906e58ca 7407
845b51d6
PB		 7408 bh = NULL;
7409 val = globals->bx_glue_size;
7410 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7411 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7412 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7413
7414 myh = (struct elf_link_hash_entry *) bh;
7415 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7416 myh->forced_local = 1;
7417
7418 s->size += ARM_BX_VENEER_SIZE;
7419 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7420 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7421}
7422
7423
c7b8f16e
JB		 7424/* Add an entry to the code/data map for section SEC. */
7425
7426static void
7427elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7428{
7429 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7430 unsigned int newidx;
906e58ca 7431
c7b8f16e
JB		 7432 if (sec_data->map == NULL)
7433 {
21d799b5 7434 sec_data->map = (elf32_arm_section_map *)
99059e56 7435 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7436 sec_data->mapcount = 0;
7437 sec_data->mapsize = 1;
7438 }
906e58ca 7439
c7b8f16e 7440 newidx = sec_data->mapcount++;
906e58ca 7441
c7b8f16e
JB		 7442 if (sec_data->mapcount > sec_data->mapsize)
7443 {
7444 sec_data->mapsize *= 2;
21d799b5 7445 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7446 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7447 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7448 }
7449
7450 if (sec_data->map)
7451 {
7452 sec_data->map[newidx].vma = vma;
7453 sec_data->map[newidx].type = type;
c7b8f16e 7454 }
c7b8f16e
JB		 7455}
7456
7457
7458/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7459 veneers are handled for now. */
7460
7461static bfd_vma
7462record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7463 elf32_vfp11_erratum_list *branch,
7464 bfd *branch_bfd,
7465 asection *branch_sec,
7466 unsigned int offset)
c7b8f16e
JB		 7467{
7468 asection *s;
7469 struct elf32_arm_link_hash_table *hash_table;
7470 char *tmp_name;
7471 struct elf_link_hash_entry *myh;
7472 struct bfd_link_hash_entry *bh;
7473 bfd_vma val;
7474 struct _arm_elf_section_data *sec_data;
c7b8f16e 7475 elf32_vfp11_erratum_list *newerr;
906e58ca 7476
c7b8f16e 7477 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7478 BFD_ASSERT (hash_table != NULL);
7479 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7480
3d4d4302 7481 s = bfd_get_linker_section
c7b8f16e 7482 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7483
c7b8f16e 7484 sec_data = elf32_arm_section_data (s);
906e58ca 7485
c7b8f16e 7486 BFD_ASSERT (s != NULL);
906e58ca 7487
21d799b5 7488 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7489 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7490
c7b8f16e 7491 BFD_ASSERT (tmp_name);
906e58ca 7492
c7b8f16e
JB		 7493 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7494 hash_table->num_vfp11_fixes);
906e58ca 7495
c7b8f16e
JB		 7496 myh = elf_link_hash_lookup
7497 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7498
c7b8f16e 7499 BFD_ASSERT (myh == NULL);
906e58ca 7500
c7b8f16e
JB		 7501 bh = NULL;
7502 val = hash_table->vfp11_erratum_glue_size;
7503 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7504 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7505 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7506
7507 myh = (struct elf_link_hash_entry *) bh;
7508 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7509 myh->forced_local = 1;
7510
7511 /* Link veneer back to calling location. */
c7e2358a 7512 sec_data->erratumcount += 1;
21d799b5
NC		 7513 newerr = (elf32_vfp11_erratum_list *)
7514 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7515
c7b8f16e
JB		 7516 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7517 newerr->vma = -1;
7518 newerr->u.v.branch = branch;
7519 newerr->u.v.id = hash_table->num_vfp11_fixes;
7520 branch->u.b.veneer = newerr;
7521
7522 newerr->next = sec_data->erratumlist;
7523 sec_data->erratumlist = newerr;
7524
7525 /* A symbol for the return from the veneer. */
7526 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7527 hash_table->num_vfp11_fixes);
7528
7529 myh = elf_link_hash_lookup
7530 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7531
c7b8f16e
JB		 7532 if (myh != NULL)
7533 abort ();
7534
7535 bh = NULL;
7536 val = offset + 4;
7537 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7538 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7539
c7b8f16e
JB		 7540 myh = (struct elf_link_hash_entry *) bh;
7541 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7542 myh->forced_local = 1;
7543
7544 free (tmp_name);
906e58ca 7545
c7b8f16e
JB		 7546 /* Generate a mapping symbol for the veneer section, and explicitly add an
7547 entry for that symbol to the code/data map for the section. */
7548 if (hash_table->vfp11_erratum_glue_size == 0)
7549 {
7550 bh = NULL;
7551 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7552 ever requires this erratum fix. */
c7b8f16e
JB		 7553 _bfd_generic_link_add_one_symbol (link_info,
7554 hash_table->bfd_of_glue_owner, "$a",
7555 BSF_LOCAL, s, 0, NULL,
99059e56 7556 TRUE, FALSE, &bh);
c7b8f16e
JB		 7557
7558 myh = (struct elf_link_hash_entry *) bh;
7559 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7560 myh->forced_local = 1;
906e58ca 7561
c7b8f16e 7562 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7563 BFDs. We must make a note of this generated mapping symbol
7564 ourselves so that code byteswapping works properly in
7565 elf32_arm_write_section. */
c7b8f16e
JB		 7566 elf32_arm_section_map_add (s, 'a', 0);
7567 }
906e58ca 7568
c7b8f16e
JB		 7569 s->size += VFP11_ERRATUM_VENEER_SIZE;
7570 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7571 hash_table->num_vfp11_fixes++;
906e58ca 7572
c7b8f16e
JB		 7573 /* The offset of the veneer. */
7574 return val;
7575}
7576
a504d23a
LA		 7577/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7578 veneers need to be handled because used only in Cortex-M. */
7579
7580static bfd_vma
7581record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7582 elf32_stm32l4xx_erratum_list *branch,
7583 bfd *branch_bfd,
7584 asection *branch_sec,
7585 unsigned int offset,
7586 bfd_size_type veneer_size)
7587{
7588 asection *s;
7589 struct elf32_arm_link_hash_table *hash_table;
7590 char *tmp_name;
7591 struct elf_link_hash_entry *myh;
7592 struct bfd_link_hash_entry *bh;
7593 bfd_vma val;
7594 struct _arm_elf_section_data *sec_data;
7595 elf32_stm32l4xx_erratum_list *newerr;
7596
7597 hash_table = elf32_arm_hash_table (link_info);
7598 BFD_ASSERT (hash_table != NULL);
7599 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7600
7601 s = bfd_get_linker_section
7602 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7603
7604 BFD_ASSERT (s != NULL);
7605
7606 sec_data = elf32_arm_section_data (s);
7607
7608 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7609 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7610
7611 BFD_ASSERT (tmp_name);
7612
7613 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7614 hash_table->num_stm32l4xx_fixes);
7615
7616 myh = elf_link_hash_lookup
7617 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7618
7619 BFD_ASSERT (myh == NULL);
7620
7621 bh = NULL;
7622 val = hash_table->stm32l4xx_erratum_glue_size;
7623 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7624 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7625 NULL, TRUE, FALSE, &bh);
7626
7627 myh = (struct elf_link_hash_entry *) bh;
7628 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7629 myh->forced_local = 1;
7630
7631 /* Link veneer back to calling location. */
7632 sec_data->stm32l4xx_erratumcount += 1;
7633 newerr = (elf32_stm32l4xx_erratum_list *)
7634 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7635
7636 newerr->type = STM32L4XX_ERRATUM_VENEER;
7637 newerr->vma = -1;
7638 newerr->u.v.branch = branch;
7639 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7640 branch->u.b.veneer = newerr;
7641
7642 newerr->next = sec_data->stm32l4xx_erratumlist;
7643 sec_data->stm32l4xx_erratumlist = newerr;
7644
7645 /* A symbol for the return from the veneer. */
7646 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7647 hash_table->num_stm32l4xx_fixes);
7648
7649 myh = elf_link_hash_lookup
7650 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7651
7652 if (myh != NULL)
7653 abort ();
7654
7655 bh = NULL;
7656 val = offset + 4;
7657 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7658 branch_sec, val, NULL, TRUE, FALSE, &bh);
7659
7660 myh = (struct elf_link_hash_entry *) bh;
7661 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7662 myh->forced_local = 1;
7663
7664 free (tmp_name);
7665
7666 /* Generate a mapping symbol for the veneer section, and explicitly add an
7667 entry for that symbol to the code/data map for the section. */
7668 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7669 {
7670 bh = NULL;
7671 /* Creates a THUMB symbol since there is no other choice. */
7672 _bfd_generic_link_add_one_symbol (link_info,
7673 hash_table->bfd_of_glue_owner, "$t",
7674 BSF_LOCAL, s, 0, NULL,
7675 TRUE, FALSE, &bh);
7676
7677 myh = (struct elf_link_hash_entry *) bh;
7678 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7679 myh->forced_local = 1;
7680
7681 /* The elf32_arm_init_maps function only cares about symbols from input
7682 BFDs. We must make a note of this generated mapping symbol
7683 ourselves so that code byteswapping works properly in
7684 elf32_arm_write_section. */
7685 elf32_arm_section_map_add (s, 't', 0);
7686 }
7687
7688 s->size += veneer_size;
7689 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7690 hash_table->num_stm32l4xx_fixes++;
7691
7692 /* The offset of the veneer. */
7693 return val;
7694}
7695
8029a119 7696#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7697 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7698 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7699
7700/* Create a fake section for use by the ARM backend of the linker. */
7701
7702static bfd_boolean
7703arm_make_glue_section (bfd * abfd, const char * name)
7704{
7705 asection * sec;
7706
3d4d4302 7707 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7708 if (sec != NULL)
7709 /* Already made. */
7710 return TRUE;
7711
3d4d4302 7712 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7713
7714 if (sec == NULL
fd361982 7715 || !bfd_set_section_alignment (sec, 2))
8029a119
NC		 7716 return FALSE;
7717
7718 /* Set the gc mark to prevent the section from being removed by garbage
7719 collection, despite the fact that no relocs refer to this section. */
7720 sec->gc_mark = 1;
7721
7722 return TRUE;
7723}
7724
1db37fe6
YG		 7725/* Set size of .plt entries. This function is called from the
7726 linker scripts in ld/emultempl/{armelf}.em. */
7727
7728void
7729bfd_elf32_arm_use_long_plt (void)
7730{
7731 elf32_arm_use_long_plt_entry = TRUE;
7732}
7733
8afb0e02
NC		 7734/* Add the glue sections to ABFD. This function is called from the
7735 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7736
b34976b6 7737bfd_boolean
57e8b36a
NC		 7738bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7739 struct bfd_link_info *info)
252b5132 7740{
a504d23a
LA		 7741 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7742 bfd_boolean dostm32l4xx = globals
7743 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7744 bfd_boolean addglue;
7745
8afb0e02
NC		 7746 /* If we are only performing a partial
7747 link do not bother adding the glue. */
0e1862bb 7748 if (bfd_link_relocatable (info))
b34976b6 7749 return TRUE;
252b5132 7750
a504d23a 7751 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7752 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7753 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7754 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7755
7756 if (!dostm32l4xx)
7757 return addglue;
7758
7759 return addglue
7760 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7761}
7762
daa4adae
TP		 7763/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7764 ensures they are not marked for deletion by
7765 strip_excluded_output_sections () when veneers are going to be created
7766 later. Not doing so would trigger assert on empty section size in
7767 lang_size_sections_1 (). */
7768
7769void
7770bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7771{
7772 enum elf32_arm_stub_type stub_type;
7773
7774 /* If we are only performing a partial
7775 link do not bother adding the glue. */
7776 if (bfd_link_relocatable (info))
7777 return;
7778
7779 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7780 {
7781 asection *out_sec;
7782 const char *out_sec_name;
7783
7784 if (!arm_dedicated_stub_output_section_required (stub_type))
7785 continue;
7786
7787 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7788 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7789 if (out_sec != NULL)
7790 out_sec->flags |= SEC_KEEP;
7791 }
7792}
7793
8afb0e02
NC		 7794/* Select a BFD to be used to hold the sections used by the glue code.
7795 This function is called from the linker scripts in ld/emultempl/
8029a119 7796 {armelf/pe}.em. */
8afb0e02 7797
b34976b6 7798bfd_boolean
57e8b36a 7799bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7800{
7801 struct elf32_arm_link_hash_table *globals;
7802
7803 /* If we are only performing a partial link
7804 do not bother getting a bfd to hold the glue. */
0e1862bb 7805 if (bfd_link_relocatable (info))
b34976b6 7806 return TRUE;
8afb0e02 7807
b7693d02
DJ		 7808 /* Make sure we don't attach the glue sections to a dynamic object. */
7809 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7810
8afb0e02 7811 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7812 BFD_ASSERT (globals != NULL);
7813
7814 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7815 return TRUE;
8afb0e02 7816
252b5132
RH		 7817 /* Save the bfd for later use. */
7818 globals->bfd_of_glue_owner = abfd;
cedb70c5 7819
b34976b6 7820 return TRUE;
252b5132
RH		 7821}
7822
906e58ca
NC		 7823static void
7824check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7825{
2de70689
MGD		 7826 int cpu_arch;
7827
b38cadfb 7828 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7829 Tag_CPU_arch);
7830
7831 if (globals->fix_arm1176)
7832 {
7833 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7834 globals->use_blx = 1;
7835 }
7836 else
7837 {
7838 if (cpu_arch > TAG_CPU_ARCH_V4T)
7839 globals->use_blx = 1;
7840 }
39b41c9c
PB		 7841}
7842
b34976b6 7843bfd_boolean
57e8b36a 7844bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7845 struct bfd_link_info *link_info)
252b5132
RH		 7846{
7847 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7848 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7849 Elf_Internal_Rela *irel, *irelend;
7850 bfd_byte *contents = NULL;
252b5132
RH		 7851
7852 asection *sec;
7853 struct elf32_arm_link_hash_table *globals;
7854
7855 /* If we are only performing a partial link do not bother
7856 to construct any glue. */
0e1862bb 7857 if (bfd_link_relocatable (link_info))
b34976b6 7858 return TRUE;
252b5132 7859
39ce1a6a
NC		 7860 /* Here we have a bfd that is to be included on the link. We have a
7861 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7862 globals = elf32_arm_hash_table (link_info);
252b5132 7863 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7864
7865 check_use_blx (globals);
252b5132 7866
d504ffc8 7867 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7868 {
90b6238f 7869 _bfd_error_handler (_("%pB: BE8 images only valid in big-endian mode"),
d003868e 7870 abfd);
e489d0ae
PB		 7871 return FALSE;
7872 }
f21f3fe0 7873
39ce1a6a
NC		 7874 /* PR 5398: If we have not decided to include any loadable sections in
7875 the output then we will not have a glue owner bfd. This is OK, it
7876 just means that there is nothing else for us to do here. */
7877 if (globals->bfd_of_glue_owner == NULL)
7878 return TRUE;
7879
252b5132
RH		 7880 /* Rummage around all the relocs and map the glue vectors. */
7881 sec = abfd->sections;
7882
7883 if (sec == NULL)
b34976b6 7884 return TRUE;
252b5132
RH		 7885
7886 for (; sec != NULL; sec = sec->next)
7887 {
7888 if (sec->reloc_count == 0)
7889 continue;
7890
2f475487
AM		 7891 if ((sec->flags & SEC_EXCLUDE) != 0)
7892 continue;
7893
0ffa91dd 7894 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7895
9b485d32 7896 /* Load the relocs. */
6cdc0ccc 7897 internal_relocs
906e58ca 7898 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7899
6cdc0ccc
AM		 7900 if (internal_relocs == NULL)
7901 goto error_return;
252b5132 7902
6cdc0ccc
AM		 7903 irelend = internal_relocs + sec->reloc_count;
7904 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7905 {
7906 long r_type;
7907 unsigned long r_index;
252b5132
RH		 7908
7909 struct elf_link_hash_entry *h;
7910
7911 r_type = ELF32_R_TYPE (irel->r_info);
7912 r_index = ELF32_R_SYM (irel->r_info);
7913
9b485d32 7914 /* These are the only relocation types we care about. */
ba96a88f 7915 if ( r_type != R_ARM_PC24
845b51d6 7916 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7917 continue;
7918
7919 /* Get the section contents if we haven't done so already. */
7920 if (contents == NULL)
7921 {
7922 /* Get cached copy if it exists. */
7923 if (elf_section_data (sec)->this_hdr.contents != NULL)
7924 contents = elf_section_data (sec)->this_hdr.contents;
7925 else
7926 {
7927 /* Go get them off disk. */
57e8b36a 7928 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7929 goto error_return;
7930 }
7931 }
7932
845b51d6
PB		 7933 if (r_type == R_ARM_V4BX)
7934 {
7935 int reg;
7936
7937 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7938 record_arm_bx_glue (link_info, reg);
7939 continue;
7940 }
7941
a7c10850 7942 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7943 h = NULL;
7944
9b485d32 7945 /* We don't care about local symbols. */
252b5132
RH		 7946 if (r_index < symtab_hdr->sh_info)
7947 continue;
7948
9b485d32 7949 /* This is an external symbol. */
252b5132
RH		 7950 r_index -= symtab_hdr->sh_info;
7951 h = (struct elf_link_hash_entry *)
7952 elf_sym_hashes (abfd)[r_index];
7953
7954 /* If the relocation is against a static symbol it must be within
7955 the current section and so cannot be a cross ARM/Thumb relocation. */
7956 if (h == NULL)
7957 continue;
7958
d504ffc8
DJ		 7959 /* If the call will go through a PLT entry then we do not need
7960 glue. */
362d30a1 7961 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7962 continue;
7963
252b5132
RH		 7964 switch (r_type)
7965 {
7966 case R_ARM_PC24:
7967 /* This one is a call from arm code. We need to look up
99059e56
RM		 7968 the target of the call. If it is a thumb target, we
7969 insert glue. */
39d911fc
TP		 7970 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7971 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7972 record_arm_to_thumb_glue (link_info, h);
7973 break;
7974
252b5132 7975 default:
c6596c5e 7976 abort ();
252b5132
RH		 7977 }
7978 }
6cdc0ccc
AM		 7979
7980 if (contents != NULL
7981 && elf_section_data (sec)->this_hdr.contents != contents)
7982 free (contents);
7983 contents = NULL;
7984
7985 if (internal_relocs != NULL
7986 && elf_section_data (sec)->relocs != internal_relocs)
7987 free (internal_relocs);
7988 internal_relocs = NULL;
252b5132
RH		 7989 }
7990
b34976b6 7991 return TRUE;
9a5aca8c 7992
252b5132 7993error_return:
6cdc0ccc
AM		 7994 if (contents != NULL
7995 && elf_section_data (sec)->this_hdr.contents != contents)
7996 free (contents);
7997 if (internal_relocs != NULL
7998 && elf_section_data (sec)->relocs != internal_relocs)
7999 free (internal_relocs);
9a5aca8c 8000
b34976b6 8001 return FALSE;
252b5132 8002}
7e392df6 8003#endif
252b5132 8004
eb043451 8005
c7b8f16e
JB		 8006/* Initialise maps of ARM/Thumb/data for input BFDs. */
8007
8008void
8009bfd_elf32_arm_init_maps (bfd *abfd)
8010{
8011 Elf_Internal_Sym *isymbuf;
8012 Elf_Internal_Shdr *hdr;
8013 unsigned int i, localsyms;
8014
af1f4419
NC		 8015 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
8016 if (! is_arm_elf (abfd))
8017 return;
8018
c7b8f16e
JB		 8019 if ((abfd->flags & DYNAMIC) != 0)
8020 return;
8021
0ffa91dd 8022 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 8023 localsyms = hdr->sh_info;
8024
8025 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
8026 should contain the number of local symbols, which should come before any
8027 global symbols. Mapping symbols are always local. */
8028 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
8029 NULL);
8030
8031 /* No internal symbols read? Skip this BFD. */
8032 if (isymbuf == NULL)
8033 return;
8034
8035 for (i = 0; i < localsyms; i++)
8036 {
8037 Elf_Internal_Sym *isym = &isymbuf[i];
8038 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
8039 const char *name;
906e58ca 8040
c7b8f16e 8041 if (sec != NULL
99059e56
RM		 8042 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
8043 {
8044 name = bfd_elf_string_from_elf_section (abfd,
8045 hdr->sh_link, isym->st_name);
906e58ca 8046
99059e56 8047 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 8048 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 8049 elf32_arm_section_map_add (sec, name[1], isym->st_value);
8050 }
c7b8f16e
JB		 8051 }
8052}
8053
8054
48229727
JB		 8055/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
8056 say what they wanted. */
8057
8058void
8059bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
8060{
8061 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8062 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8063
4dfe6ac6
NC		 8064 if (globals == NULL)
8065 return;
8066
48229727
JB		 8067 if (globals->fix_cortex_a8 == -1)
8068 {
8069 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
8070 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
8071 && (out_attr[Tag_CPU_arch_profile].i == 'A'
8072 || out_attr[Tag_CPU_arch_profile].i == 0))
8073 globals->fix_cortex_a8 = 1;
8074 else
8075 globals->fix_cortex_a8 = 0;
8076 }
8077}
8078
8079
c7b8f16e
JB		 8080void
8081bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
8082{
8083 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 8084 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 8085
4dfe6ac6
NC		 8086 if (globals == NULL)
8087 return;
c7b8f16e
JB		 8088 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8089 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
8090 {
8091 switch (globals->vfp11_fix)
99059e56
RM		 8092 {
8093 case BFD_ARM_VFP11_FIX_DEFAULT:
8094 case BFD_ARM_VFP11_FIX_NONE:
8095 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8096 break;
8097
8098 default:
8099 /* Give a warning, but do as the user requests anyway. */
871b3ab2 8100 _bfd_error_handler (_("%pB: warning: selected VFP11 erratum "
99059e56
RM		 8101 "workaround is not necessary for target architecture"), obfd);
8102 }
c7b8f16e
JB		 8103 }
8104 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
8105 /* For earlier architectures, we might need the workaround, but do not
8106 enable it by default. If users is running with broken hardware, they
8107 must enable the erratum fix explicitly. */
8108 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8109}
8110
a504d23a
LA		 8111void
8112bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
8113{
8114 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8115 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8116
8117 if (globals == NULL)
8118 return;
8119
8120 /* We assume only Cortex-M4 may require the fix. */
8121 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
8122 || out_attr[Tag_CPU_arch_profile].i != 'M')
8123 {
8124 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
8125 /* Give a warning, but do as the user requests anyway. */
4eca0228 8126 _bfd_error_handler
871b3ab2 8127 (_("%pB: warning: selected STM32L4XX erratum "
a504d23a
LA		 8128 "workaround is not necessary for target architecture"), obfd);
8129 }
8130}
c7b8f16e 8131
906e58ca
NC		 8132enum bfd_arm_vfp11_pipe
8133{
c7b8f16e
JB		 8134 VFP11_FMAC,
8135 VFP11_LS,
8136 VFP11_DS,
8137 VFP11_BAD
8138};
8139
8140/* Return a VFP register number. This is encoded as RX:X for single-precision
8141 registers, or X:RX for double-precision registers, where RX is the group of
8142 four bits in the instruction encoding and X is the single extension bit.
8143 RX and X fields are specified using their lowest (starting) bit. The return
8144 value is:
8145
8146 0...31: single-precision registers s0...s31
8147 32...63: double-precision registers d0...d31.
906e58ca 8148
c7b8f16e
JB		 8149 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8150 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 8151
c7b8f16e
JB		 8152static unsigned int
8153bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 8154 unsigned int x)
c7b8f16e
JB		 8155{
8156 if (is_double)
8157 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
8158 else
8159 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
8160}
8161
8162/* Set bits in *WMASK according to a register number REG as encoded by
8163 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8164
8165static void
8166bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
8167{
8168 if (reg < 32)
8169 *wmask |= 1 << reg;
8170 else if (reg < 48)
8171 *wmask |= 3 << ((reg - 32) * 2);
8172}
8173
8174/* Return TRUE if WMASK overwrites anything in REGS. */
8175
8176static bfd_boolean
8177bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
8178{
8179 int i;
906e58ca 8180
c7b8f16e
JB		 8181 for (i = 0; i < numregs; i++)
8182 {
8183 unsigned int reg = regs[i];
8184
8185 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 8186 return TRUE;
906e58ca 8187
c7b8f16e
JB		 8188 reg -= 32;
8189
8190 if (reg >= 16)
99059e56 8191 continue;
906e58ca 8192
c7b8f16e 8193 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 8194 return TRUE;
c7b8f16e 8195 }
906e58ca 8196
c7b8f16e
JB		 8197 return FALSE;
8198}
8199
8200/* In this function, we're interested in two things: finding input registers
8201 for VFP data-processing instructions, and finding the set of registers which
8202 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8203 hold the written set, so FLDM etc. are easy to deal with (we're only
8204 interested in 32 SP registers or 16 dp registers, due to the VFP version
8205 implemented by the chip in question). DP registers are marked by setting
8206 both SP registers in the write mask). */
8207
8208static enum bfd_arm_vfp11_pipe
8209bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 8210 int *numregs)
c7b8f16e 8211{
91d6fa6a 8212 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 8213 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
8214
8215 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
8216 {
8217 unsigned int pqrs;
8218 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8219 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
8220
8221 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 8222 | ((insn & 0x00300000) >> 19)
8223 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 8224
8225 switch (pqrs)
99059e56
RM		 8226 {
8227 case 0: /* fmac[sd]. */
8228 case 1: /* fnmac[sd]. */
8229 case 2: /* fmsc[sd]. */
8230 case 3: /* fnmsc[sd]. */
8231 vpipe = VFP11_FMAC;
8232 bfd_arm_vfp11_write_mask (destmask, fd);
8233 regs[0] = fd;
8234 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8235 regs[2] = fm;
8236 *numregs = 3;
8237 break;
8238
8239 case 4: /* fmul[sd]. */
8240 case 5: /* fnmul[sd]. */
8241 case 6: /* fadd[sd]. */
8242 case 7: /* fsub[sd]. */
8243 vpipe = VFP11_FMAC;
8244 goto vfp_binop;
8245
8246 case 8: /* fdiv[sd]. */
8247 vpipe = VFP11_DS;
8248 vfp_binop:
8249 bfd_arm_vfp11_write_mask (destmask, fd);
8250 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8251 regs[1] = fm;
8252 *numregs = 2;
8253 break;
8254
8255 case 15: /* extended opcode. */
8256 {
8257 unsigned int extn = ((insn >> 15) & 0x1e)
8258 | ((insn >> 7) & 1);
8259
8260 switch (extn)
8261 {
8262 case 0: /* fcpy[sd]. */
8263 case 1: /* fabs[sd]. */
8264 case 2: /* fneg[sd]. */
8265 case 8: /* fcmp[sd]. */
8266 case 9: /* fcmpe[sd]. */
8267 case 10: /* fcmpz[sd]. */
8268 case 11: /* fcmpez[sd]. */
8269 case 16: /* fuito[sd]. */
8270 case 17: /* fsito[sd]. */
8271 case 24: /* ftoui[sd]. */
8272 case 25: /* ftouiz[sd]. */
8273 case 26: /* ftosi[sd]. */
8274 case 27: /* ftosiz[sd]. */
8275 /* These instructions will not bounce due to underflow. */
8276 *numregs = 0;
8277 vpipe = VFP11_FMAC;
8278 break;
8279
8280 case 3: /* fsqrt[sd]. */
8281 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8282 registers to cause the erratum in previous instructions. */
8283 bfd_arm_vfp11_write_mask (destmask, fd);
8284 vpipe = VFP11_DS;
8285 break;
8286
8287 case 15: /* fcvt{ds,sd}. */
8288 {
8289 int rnum = 0;
8290
8291 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 8292
8293 /* Only FCVTSD can underflow. */
99059e56
RM		 8294 if ((insn & 0x100) != 0)
8295 regs[rnum++] = fm;
c7b8f16e 8296
99059e56 8297 *numregs = rnum;
c7b8f16e 8298
99059e56
RM		 8299 vpipe = VFP11_FMAC;
8300 }
8301 break;
c7b8f16e 8302
99059e56
RM		 8303 default:
8304 return VFP11_BAD;
8305 }
8306 }
8307 break;
c7b8f16e 8308
99059e56
RM		 8309 default:
8310 return VFP11_BAD;
8311 }
c7b8f16e
JB		 8312 }
8313 /* Two-register transfer. */
8314 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
8315 {
8316 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 8317
c7b8f16e
JB		 8318 if ((insn & 0x100000) == 0)
8319 {
99059e56
RM		 8320 if (is_double)
8321 bfd_arm_vfp11_write_mask (destmask, fm);
8322 else
8323 {
8324 bfd_arm_vfp11_write_mask (destmask, fm);
8325 bfd_arm_vfp11_write_mask (destmask, fm + 1);
8326 }
c7b8f16e
JB		 8327 }
8328
91d6fa6a 8329 vpipe = VFP11_LS;
c7b8f16e
JB		 8330 }
8331 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
8332 {
8333 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8334 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 8335
c7b8f16e 8336 switch (puw)
99059e56
RM		 8337 {
8338 case 0: /* Two-reg transfer. We should catch these above. */
8339 abort ();
906e58ca 8340
99059e56
RM		 8341 case 2: /* fldm[sdx]. */
8342 case 3:
8343 case 5:
8344 {
8345 unsigned int i, offset = insn & 0xff;
c7b8f16e 8346
99059e56
RM		 8347 if (is_double)
8348 offset >>= 1;
c7b8f16e 8349
99059e56
RM		 8350 for (i = fd; i < fd + offset; i++)
8351 bfd_arm_vfp11_write_mask (destmask, i);
8352 }
8353 break;
906e58ca 8354
99059e56
RM		 8355 case 4: /* fld[sd]. */
8356 case 6:
8357 bfd_arm_vfp11_write_mask (destmask, fd);
8358 break;
906e58ca 8359
99059e56
RM		 8360 default:
8361 return VFP11_BAD;
8362 }
c7b8f16e 8363
91d6fa6a 8364 vpipe = VFP11_LS;
c7b8f16e
JB		 8365 }
8366 /* Single-register transfer. Note L==0. */
8367 else if ((insn & 0x0f100e10) == 0x0e000a10)
8368 {
8369 unsigned int opcode = (insn >> 21) & 7;
8370 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8371
8372 switch (opcode)
99059e56
RM		 8373 {
8374 case 0: /* fmsr/fmdlr. */
8375 case 1: /* fmdhr. */
8376 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8377 destination register. I don't know if this is exactly right,
8378 but it is the conservative choice. */
8379 bfd_arm_vfp11_write_mask (destmask, fn);
8380 break;
8381
8382 case 7: /* fmxr. */
8383 break;
8384 }
c7b8f16e 8385
91d6fa6a 8386 vpipe = VFP11_LS;
c7b8f16e
JB		 8387 }
8388
91d6fa6a 8389 return vpipe;
c7b8f16e
JB		 8390}
8391
8392
8393static int elf32_arm_compare_mapping (const void * a, const void * b);
8394
8395
8396/* Look for potentially-troublesome code sequences which might trigger the
8397 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8398 (available from ARM) for details of the erratum. A short version is
8399 described in ld.texinfo. */
8400
8401bfd_boolean
8402bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8403{
8404 asection *sec;
8405 bfd_byte *contents = NULL;
8406 int state = 0;
8407 int regs[3], numregs = 0;
8408 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8409 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8410
4dfe6ac6
NC		 8411 if (globals == NULL)
8412 return FALSE;
8413
c7b8f16e
JB		 8414 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8415 The states transition as follows:
906e58ca 8416
c7b8f16e 8417 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8418 A VFP FMAC-pipeline instruction has been seen. Fill
8419 regs[0]..regs[numregs-1] with its input operands. Remember this
8420 instruction in 'first_fmac'.
c7b8f16e
JB		 8421
8422 1 -> 2
99059e56
RM		 8423 Any instruction, except for a VFP instruction which overwrites
8424 regs[*].
906e58ca 8425
c7b8f16e
JB		 8426 1 -> 3 [ -> 0 ] or
8427 2 -> 3 [ -> 0 ]
99059e56
RM		 8428 A VFP instruction has been seen which overwrites any of regs[*].
8429 We must make a veneer! Reset state to 0 before examining next
8430 instruction.
906e58ca 8431
c7b8f16e 8432 2 -> 0
99059e56
RM		 8433 If we fail to match anything in state 2, reset to state 0 and reset
8434 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8435
8436 If the VFP11 vector mode is in use, there must be at least two unrelated
8437 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8438 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8439
8440 /* If we are only performing a partial link do not bother
8441 to construct any glue. */
0e1862bb 8442 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8443 return TRUE;
8444
0ffa91dd
NC		 8445 /* Skip if this bfd does not correspond to an ELF image. */
8446 if (! is_arm_elf (abfd))
8447 return TRUE;
906e58ca 8448
c7b8f16e
JB		 8449 /* We should have chosen a fix type by the time we get here. */
8450 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8451
8452 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8453 return TRUE;
2e6030b9 8454
33a7ffc2
JM		 8455 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8456 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8457 return TRUE;
8458
c7b8f16e
JB		 8459 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8460 {
8461 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8462 struct _arm_elf_section_data *sec_data;
8463
8464 /* If we don't have executable progbits, we're not interested in this
99059e56 8465 section. Also skip if section is to be excluded. */
c7b8f16e 8466 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8467 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8468 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8469 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8470 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8471 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8472 continue;
c7b8f16e
JB		 8473
8474 sec_data = elf32_arm_section_data (sec);
906e58ca 8475
c7b8f16e 8476 if (sec_data->mapcount == 0)
99059e56 8477 continue;
906e58ca 8478
c7b8f16e
JB		 8479 if (elf_section_data (sec)->this_hdr.contents != NULL)
8480 contents = elf_section_data (sec)->this_hdr.contents;
8481 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8482 goto error_return;
8483
8484 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8485 elf32_arm_compare_mapping);
8486
8487 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8488 {
8489 unsigned int span_start = sec_data->map[span].vma;
8490 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8491 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8492 char span_type = sec_data->map[span].type;
8493
8494 /* FIXME: Only ARM mode is supported at present. We may need to
8495 support Thumb-2 mode also at some point. */
8496 if (span_type != 'a')
8497 continue;
8498
8499 for (i = span_start; i < span_end;)
8500 {
8501 unsigned int next_i = i + 4;
8502 unsigned int insn = bfd_big_endian (abfd)
8503 ? (contents[i] << 24)
8504 | (contents[i + 1] << 16)
8505 | (contents[i + 2] << 8)
8506 | contents[i + 3]
8507 : (contents[i + 3] << 24)
8508 | (contents[i + 2] << 16)
8509 | (contents[i + 1] << 8)
8510 | contents[i];
8511 unsigned int writemask = 0;
8512 enum bfd_arm_vfp11_pipe vpipe;
8513
8514 switch (state)
8515 {
8516 case 0:
8517 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8518 &numregs);
8519 /* I'm assuming the VFP11 erratum can trigger with denorm
8520 operands on either the FMAC or the DS pipeline. This might
8521 lead to slightly overenthusiastic veneer insertion. */
8522 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8523 {
8524 state = use_vector ? 1 : 2;
8525 first_fmac = i;
8526 veneer_of_insn = insn;
8527 }
8528 break;
8529
8530 case 1:
8531 {
8532 int other_regs[3], other_numregs;
8533 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8534 other_regs,
99059e56
RM		 8535 &other_numregs);
8536 if (vpipe != VFP11_BAD
8537 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8538 numregs))
99059e56
RM		 8539 state = 3;
8540 else
8541 state = 2;
8542 }
8543 break;
8544
8545 case 2:
8546 {
8547 int other_regs[3], other_numregs;
8548 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8549 other_regs,
99059e56
RM		 8550 &other_numregs);
8551 if (vpipe != VFP11_BAD
8552 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8553 numregs))
99059e56
RM		 8554 state = 3;
8555 else
8556 {
8557 state = 0;
8558 next_i = first_fmac + 4;
8559 }
8560 }
8561 break;
8562
8563 case 3:
8564 abort (); /* Should be unreachable. */
8565 }
8566
8567 if (state == 3)
8568 {
8569 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8570 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8571
8572 elf32_arm_section_data (sec)->erratumcount += 1;
8573
8574 newerr->u.b.vfp_insn = veneer_of_insn;
8575
8576 switch (span_type)
8577 {
8578 case 'a':
8579 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8580 break;
8581
8582 default:
8583 abort ();
8584 }
8585
8586 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8587 first_fmac);
8588
99059e56 8589 newerr->vma = -1;
c7b8f16e 8590
99059e56
RM		 8591 newerr->next = sec_data->erratumlist;
8592 sec_data->erratumlist = newerr;
c7b8f16e 8593
99059e56
RM		 8594 state = 0;
8595 }
c7b8f16e 8596
99059e56
RM		 8597 i = next_i;
8598 }
8599 }
906e58ca 8600
c7b8f16e 8601 if (contents != NULL
99059e56
RM		 8602 && elf_section_data (sec)->this_hdr.contents != contents)
8603 free (contents);
c7b8f16e
JB		 8604 contents = NULL;
8605 }
8606
8607 return TRUE;
8608
8609error_return:
8610 if (contents != NULL
8611 && elf_section_data (sec)->this_hdr.contents != contents)
8612 free (contents);
906e58ca 8613
c7b8f16e
JB		 8614 return FALSE;
8615}
8616
8617/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8618 after sections have been laid out, using specially-named symbols. */
8619
8620void
8621bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8622 struct bfd_link_info *link_info)
8623{
8624 asection *sec;
8625 struct elf32_arm_link_hash_table *globals;
8626 char *tmp_name;
906e58ca 8627
0e1862bb 8628 if (bfd_link_relocatable (link_info))
c7b8f16e 8629 return;
2e6030b9
MS		 8630
8631 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8632 if (! is_arm_elf (abfd))
2e6030b9
MS		 8633 return;
8634
c7b8f16e 8635 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8636 if (globals == NULL)
8637 return;
906e58ca 8638
21d799b5 8639 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8640 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8641
8642 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8643 {
8644 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8645 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8646
c7b8f16e 8647 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8648 {
8649 struct elf_link_hash_entry *myh;
8650 bfd_vma vma;
8651
8652 switch (errnode->type)
8653 {
8654 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8655 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8656 /* Find veneer symbol. */
8657 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8658 errnode->u.b.veneer->u.v.id);
8659
99059e56
RM		 8660 myh = elf_link_hash_lookup
8661 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8662
a504d23a 8663 if (myh == NULL)
90b6238f
AM		 8664 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8665 abfd, "VFP11", tmp_name);
a504d23a
LA		 8666
8667 vma = myh->root.u.def.section->output_section->vma
8668 + myh->root.u.def.section->output_offset
8669 + myh->root.u.def.value;
8670
8671 errnode->u.b.veneer->vma = vma;
8672 break;
8673
8674 case VFP11_ERRATUM_ARM_VENEER:
8675 case VFP11_ERRATUM_THUMB_VENEER:
8676 /* Find return location. */
8677 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8678 errnode->u.v.id);
8679
8680 myh = elf_link_hash_lookup
8681 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8682
8683 if (myh == NULL)
90b6238f
AM		 8684 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8685 abfd, "VFP11", tmp_name);
a504d23a
LA		 8686
8687 vma = myh->root.u.def.section->output_section->vma
8688 + myh->root.u.def.section->output_offset
8689 + myh->root.u.def.value;
8690
8691 errnode->u.v.branch->vma = vma;
8692 break;
8693
8694 default:
8695 abort ();
8696 }
8697 }
8698 }
8699
8700 free (tmp_name);
8701}
8702
8703/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8704 return locations after sections have been laid out, using
8705 specially-named symbols. */
8706
8707void
8708bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8709 struct bfd_link_info *link_info)
8710{
8711 asection *sec;
8712 struct elf32_arm_link_hash_table *globals;
8713 char *tmp_name;
8714
8715 if (bfd_link_relocatable (link_info))
8716 return;
8717
8718 /* Skip if this bfd does not correspond to an ELF image. */
8719 if (! is_arm_elf (abfd))
8720 return;
8721
8722 globals = elf32_arm_hash_table (link_info);
8723 if (globals == NULL)
8724 return;
8725
8726 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8727 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8728
8729 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8730 {
8731 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8732 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8733
8734 for (; errnode != NULL; errnode = errnode->next)
8735 {
8736 struct elf_link_hash_entry *myh;
8737 bfd_vma vma;
8738
8739 switch (errnode->type)
8740 {
8741 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8742 /* Find veneer symbol. */
8743 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8744 errnode->u.b.veneer->u.v.id);
8745
8746 myh = elf_link_hash_lookup
8747 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8748
8749 if (myh == NULL)
90b6238f
AM		 8750 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8751 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8752
8753 vma = myh->root.u.def.section->output_section->vma
8754 + myh->root.u.def.section->output_offset
8755 + myh->root.u.def.value;
8756
8757 errnode->u.b.veneer->vma = vma;
8758 break;
8759
8760 case STM32L4XX_ERRATUM_VENEER:
8761 /* Find return location. */
8762 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8763 errnode->u.v.id);
8764
8765 myh = elf_link_hash_lookup
8766 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8767
8768 if (myh == NULL)
90b6238f
AM		 8769 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8770 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8771
8772 vma = myh->root.u.def.section->output_section->vma
8773 + myh->root.u.def.section->output_offset
8774 + myh->root.u.def.value;
8775
8776 errnode->u.v.branch->vma = vma;
8777 break;
8778
8779 default:
8780 abort ();
8781 }
8782 }
8783 }
8784
8785 free (tmp_name);
8786}
8787
8788static inline bfd_boolean
8789is_thumb2_ldmia (const insn32 insn)
8790{
8791 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8792 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8793 return (insn & 0xffd02000) == 0xe8900000;
8794}
8795
8796static inline bfd_boolean
8797is_thumb2_ldmdb (const insn32 insn)
8798{
8799 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8800 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8801 return (insn & 0xffd02000) == 0xe9100000;
8802}
8803
8804static inline bfd_boolean
8805is_thumb2_vldm (const insn32 insn)
8806{
8807 /* A6.5 Extension register load or store instruction
8808 A7.7.229
9239bbd3
CM		 8809 We look for SP 32-bit and DP 64-bit registers.
8810 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8811 <list> is consecutive 64-bit registers
8812 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8813 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8814 <list> is consecutive 32-bit registers
8815 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8816 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8817 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8818 return
9239bbd3
CM		 8819 (((insn & 0xfe100f00) == 0xec100b00) ||
8820 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8821 && /* (IA without !). */
8822 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8823 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8824 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8825 /* (DB with !). */
8826 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8827}
8828
8829/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8830 VLDM opcode and:
8831 - computes the number and the mode of memory accesses
8832 - decides if the replacement should be done:
8833 . replaces only if > 8-word accesses
8834 . or (testing purposes only) replaces all accesses. */
8835
8836static bfd_boolean
8837stm32l4xx_need_create_replacing_stub (const insn32 insn,
8838 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8839{
9239bbd3 8840 int nb_words = 0;
a504d23a
LA		 8841
8842 /* The field encoding the register list is the same for both LDMIA
8843 and LDMDB encodings. */
8844 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8845 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8846 else if (is_thumb2_vldm (insn))
9239bbd3 8847 nb_words = (insn & 0xff);
a504d23a
LA		 8848
8849 /* DEFAULT mode accounts for the real bug condition situation,
8850 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8851 return
9239bbd3 8852 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8853 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8854}
8855
8856/* Look for potentially-troublesome code sequences which might trigger
8857 the STM STM32L4XX erratum. */
8858
8859bfd_boolean
8860bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8861 struct bfd_link_info *link_info)
8862{
8863 asection *sec;
8864 bfd_byte *contents = NULL;
8865 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8866
8867 if (globals == NULL)
8868 return FALSE;
8869
8870 /* If we are only performing a partial link do not bother
8871 to construct any glue. */
8872 if (bfd_link_relocatable (link_info))
8873 return TRUE;
8874
8875 /* Skip if this bfd does not correspond to an ELF image. */
8876 if (! is_arm_elf (abfd))
8877 return TRUE;
8878
8879 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8880 return TRUE;
8881
8882 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8883 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8884 return TRUE;
8885
8886 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8887 {
8888 unsigned int i, span;
8889 struct _arm_elf_section_data *sec_data;
8890
8891 /* If we don't have executable progbits, we're not interested in this
8892 section. Also skip if section is to be excluded. */
8893 if (elf_section_type (sec) != SHT_PROGBITS
8894 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8895 || (sec->flags & SEC_EXCLUDE) != 0
8896 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8897 || sec->output_section == bfd_abs_section_ptr
8898 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8899 continue;
8900
8901 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8902
a504d23a
LA		 8903 if (sec_data->mapcount == 0)
8904 continue;
c7b8f16e 8905
a504d23a
LA		 8906 if (elf_section_data (sec)->this_hdr.contents != NULL)
8907 contents = elf_section_data (sec)->this_hdr.contents;
8908 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8909 goto error_return;
c7b8f16e 8910
a504d23a
LA		 8911 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8912 elf32_arm_compare_mapping);
c7b8f16e 8913
a504d23a
LA		 8914 for (span = 0; span < sec_data->mapcount; span++)
8915 {
8916 unsigned int span_start = sec_data->map[span].vma;
8917 unsigned int span_end = (span == sec_data->mapcount - 1)
8918 ? sec->size : sec_data->map[span + 1].vma;
8919 char span_type = sec_data->map[span].type;
8920 int itblock_current_pos = 0;
c7b8f16e 8921
a504d23a
LA		 8922 /* Only Thumb2 mode need be supported with this CM4 specific
8923 code, we should not encounter any arm mode eg span_type
8924 != 'a'. */
8925 if (span_type != 't')
8926 continue;
c7b8f16e 8927
a504d23a
LA		 8928 for (i = span_start; i < span_end;)
8929 {
8930 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8931 bfd_boolean insn_32bit = FALSE;
8932 bfd_boolean is_ldm = FALSE;
8933 bfd_boolean is_vldm = FALSE;
8934 bfd_boolean is_not_last_in_it_block = FALSE;
8935
8936 /* The first 16-bits of all 32-bit thumb2 instructions start
8937 with opcode[15..13]=0b111 and the encoded op1 can be anything
8938 except opcode[12..11]!=0b00.
8939 See 32-bit Thumb instruction encoding. */
8940 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8941 insn_32bit = TRUE;
c7b8f16e 8942
a504d23a
LA		 8943 /* Compute the predicate that tells if the instruction
8944 is concerned by the IT block
8945 - Creates an error if there is a ldm that is not
8946 last in the IT block thus cannot be replaced
8947 - Otherwise we can create a branch at the end of the
8948 IT block, it will be controlled naturally by IT
8949 with the proper pseudo-predicate
8950 - So the only interesting predicate is the one that
8951 tells that we are not on the last item of an IT
8952 block. */
8953 if (itblock_current_pos != 0)
8954 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8955
a504d23a
LA		 8956 if (insn_32bit)
8957 {
8958 /* Load the rest of the insn (in manual-friendly order). */
8959 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8960 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8961 is_vldm = is_thumb2_vldm (insn);
8962
8963 /* Veneers are created for (v)ldm depending on
8964 option flags and memory accesses conditions; but
8965 if the instruction is not the last instruction of
8966 an IT block, we cannot create a jump there, so we
8967 bail out. */
5025eb7c
AO		 8968 if ((is_ldm || is_vldm)
8969 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8970 (insn, globals->stm32l4xx_fix))
8971 {
8972 if (is_not_last_in_it_block)
8973 {
4eca0228 8974 _bfd_error_handler
695344c0 8975 /* xgettext:c-format */
871b3ab2 8976 (_("%pB(%pA+%#x): error: multiple load detected"
90b6238f
AM		 8977 " in non-last IT block instruction:"
8978 " STM32L4XX veneer cannot be generated; "
8979 "use gcc option -mrestrict-it to generate"
8980 " only one instruction per IT block"),
d42c267e 8981 abfd, sec, i);
a504d23a
LA		 8982 }
8983 else
8984 {
8985 elf32_stm32l4xx_erratum_list *newerr =
8986 (elf32_stm32l4xx_erratum_list *)
8987 bfd_zmalloc
8988 (sizeof (elf32_stm32l4xx_erratum_list));
8989
8990 elf32_arm_section_data (sec)
8991 ->stm32l4xx_erratumcount += 1;
8992 newerr->u.b.insn = insn;
8993 /* We create only thumb branches. */
8994 newerr->type =
8995 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8996 record_stm32l4xx_erratum_veneer
8997 (link_info, newerr, abfd, sec,
8998 i,
8999 is_ldm ?
9000 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
9001 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
9002 newerr->vma = -1;
9003 newerr->next = sec_data->stm32l4xx_erratumlist;
9004 sec_data->stm32l4xx_erratumlist = newerr;
9005 }
9006 }
9007 }
9008 else
9009 {
9010 /* A7.7.37 IT p208
9011 IT blocks are only encoded in T1
9012 Encoding T1: IT{x{y{z}}} <firstcond>
9013 1 0 1 1 - 1 1 1 1 - firstcond - mask
9014 if mask = '0000' then see 'related encodings'
9015 We don't deal with UNPREDICTABLE, just ignore these.
9016 There can be no nested IT blocks so an IT block
9017 is naturally a new one for which it is worth
9018 computing its size. */
5025eb7c
AO		 9019 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
9020 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 9021 /* If we have a new IT block we compute its size. */
9022 if (is_newitblock)
9023 {
9024 /* Compute the number of instructions controlled
9025 by the IT block, it will be used to decide
9026 whether we are inside an IT block or not. */
9027 unsigned int mask = insn & 0x000f;
9028 itblock_current_pos = 4 - ctz (mask);
9029 }
9030 }
9031
9032 i += insn_32bit ? 4 : 2;
99059e56
RM		 9033 }
9034 }
a504d23a
LA		 9035
9036 if (contents != NULL
9037 && elf_section_data (sec)->this_hdr.contents != contents)
9038 free (contents);
9039 contents = NULL;
c7b8f16e 9040 }
906e58ca 9041
a504d23a
LA		 9042 return TRUE;
9043
9044error_return:
9045 if (contents != NULL
9046 && elf_section_data (sec)->this_hdr.contents != contents)
9047 free (contents);
c7b8f16e 9048
a504d23a
LA		 9049 return FALSE;
9050}
c7b8f16e 9051
eb043451
PB		 9052/* Set target relocation values needed during linking. */
9053
9054void
68c39892 9055bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 9056 struct bfd_link_info *link_info,
68c39892 9057 struct elf32_arm_params *params)
eb043451
PB		 9058{
9059 struct elf32_arm_link_hash_table *globals;
9060
9061 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9062 if (globals == NULL)
9063 return;
eb043451 9064
68c39892 9065 globals->target1_is_rel = params->target1_is_rel;
29e9b073
CL		 9066 if (globals->fdpic_p)
9067 globals->target2_reloc = R_ARM_GOT32;
9068 else if (strcmp (params->target2_type, "rel") == 0)
eb043451 9069 globals->target2_reloc = R_ARM_REL32;
68c39892 9070 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 9071 globals->target2_reloc = R_ARM_ABS32;
68c39892 9072 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 9073 globals->target2_reloc = R_ARM_GOT_PREL;
9074 else
9075 {
90b6238f 9076 _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"),
68c39892 9077 params->target2_type);
eb043451 9078 }
68c39892
TP		 9079 globals->fix_v4bx = params->fix_v4bx;
9080 globals->use_blx |= params->use_blx;
9081 globals->vfp11_fix = params->vfp11_denorm_fix;
9082 globals->stm32l4xx_fix = params->stm32l4xx_fix;
e8b09b87
CL		 9083 if (globals->fdpic_p)
9084 globals->pic_veneer = 1;
9085 else
9086 globals->pic_veneer = params->pic_veneer;
68c39892
TP		 9087 globals->fix_cortex_a8 = params->fix_cortex_a8;
9088 globals->fix_arm1176 = params->fix_arm1176;
9089 globals->cmse_implib = params->cmse_implib;
9090 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 9091
0ffa91dd 9092 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 9093 elf_arm_tdata (output_bfd)->no_enum_size_warning
9094 = params->no_enum_size_warning;
9095 elf_arm_tdata (output_bfd)->no_wchar_size_warning
9096 = params->no_wchar_size_warning;
eb043451 9097}
eb043451 9098
12a0a0fd 9099/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 9100
12a0a0fd
PB		 9101static void
9102insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
9103{
9104 bfd_vma upper;
9105 bfd_vma lower;
9106 int reloc_sign;
9107
9108 BFD_ASSERT ((offset & 1) == 0);
9109
9110 upper = bfd_get_16 (abfd, insn);
9111 lower = bfd_get_16 (abfd, insn + 2);
9112 reloc_sign = (offset < 0) ? 1 : 0;
9113 upper = (upper & ~(bfd_vma) 0x7ff)
9114 | ((offset >> 12) & 0x3ff)
9115 | (reloc_sign << 10);
906e58ca 9116 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 9117 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
9118 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
9119 | ((offset >> 1) & 0x7ff);
9120 bfd_put_16 (abfd, upper, insn);
9121 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 9122}
9123
9b485d32
NC		 9124/* Thumb code calling an ARM function. */
9125
252b5132 9126static int
57e8b36a 9127elf32_thumb_to_arm_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9128 const char * name,
9129 bfd * input_bfd,
9130 bfd * output_bfd,
9131 asection * input_section,
9132 bfd_byte * hit_data,
9133 asection * sym_sec,
9134 bfd_vma offset,
9135 bfd_signed_vma addend,
9136 bfd_vma val,
f2a9dd69 9137 char **error_message)
252b5132 9138{
bcbdc74c 9139 asection * s = 0;
dc810e39 9140 bfd_vma my_offset;
252b5132 9141 long int ret_offset;
bcbdc74c
NC		 9142 struct elf_link_hash_entry * myh;
9143 struct elf32_arm_link_hash_table * globals;
252b5132 9144
f2a9dd69 9145 myh = find_thumb_glue (info, name, error_message);
252b5132 9146 if (myh == NULL)
b34976b6 9147 return FALSE;
252b5132
RH		 9148
9149 globals = elf32_arm_hash_table (info);
252b5132
RH		 9150 BFD_ASSERT (globals != NULL);
9151 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9152
9153 my_offset = myh->root.u.def.value;
9154
3d4d4302
AM		 9155 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9156 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 9157
9158 BFD_ASSERT (s != NULL);
9159 BFD_ASSERT (s->contents != NULL);
9160 BFD_ASSERT (s->output_section != NULL);
9161
9162 if ((my_offset & 0x01) == 0x01)
9163 {
9164 if (sym_sec != NULL
9165 && sym_sec->owner != NULL
9166 && !INTERWORK_FLAG (sym_sec->owner))
9167 {
4eca0228 9168 _bfd_error_handler
90b6238f
AM		 9169 (_("%pB(%s): warning: interworking not enabled;"
9170 " first occurrence: %pB: %s call to %s"),
9171 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
252b5132 9172
b34976b6 9173 return FALSE;
252b5132
RH		 9174 }
9175
9176 --my_offset;
9177 myh->root.u.def.value = my_offset;
9178
52ab56c2
PB		 9179 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
9180 s->contents + my_offset);
252b5132 9181
52ab56c2
PB		 9182 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
9183 s->contents + my_offset + 2);
252b5132
RH		 9184
9185 ret_offset =
9b485d32
NC		 9186 /* Address of destination of the stub. */
9187 ((bfd_signed_vma) val)
252b5132 9188 - ((bfd_signed_vma)
57e8b36a
NC		 9189 /* Offset from the start of the current section
9190 to the start of the stubs. */
9b485d32
NC		 9191 (s->output_offset
9192 /* Offset of the start of this stub from the start of the stubs. */
9193 + my_offset
9194 /* Address of the start of the current section. */
9195 + s->output_section->vma)
9196 /* The branch instruction is 4 bytes into the stub. */
9197 + 4
9198 /* ARM branches work from the pc of the instruction + 8. */
9199 + 8);
252b5132 9200
52ab56c2
PB		 9201 put_arm_insn (globals, output_bfd,
9202 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
9203 s->contents + my_offset + 4);
252b5132
RH		 9204 }
9205
9206 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
9207
427bfd90
NC		 9208 /* Now go back and fix up the original BL insn to point to here. */
9209 ret_offset =
9210 /* Address of where the stub is located. */
9211 (s->output_section->vma + s->output_offset + my_offset)
9212 /* Address of where the BL is located. */
57e8b36a
NC		 9213 - (input_section->output_section->vma + input_section->output_offset
9214 + offset)
427bfd90
NC		 9215 /* Addend in the relocation. */
9216 - addend
9217 /* Biassing for PC-relative addressing. */
9218 - 8;
252b5132 9219
12a0a0fd 9220 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 9221
b34976b6 9222 return TRUE;
252b5132
RH		 9223}
9224
a4fd1a8e 9225/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 9226
a4fd1a8e
PB		 9227static struct elf_link_hash_entry *
9228elf32_arm_create_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9229 const char * name,
9230 bfd * input_bfd,
9231 bfd * output_bfd,
9232 asection * sym_sec,
9233 bfd_vma val,
9234 asection * s,
9235 char ** error_message)
252b5132 9236{
dc810e39 9237 bfd_vma my_offset;
252b5132 9238 long int ret_offset;
bcbdc74c
NC		 9239 struct elf_link_hash_entry * myh;
9240 struct elf32_arm_link_hash_table * globals;
252b5132 9241
f2a9dd69 9242 myh = find_arm_glue (info, name, error_message);
252b5132 9243 if (myh == NULL)
a4fd1a8e 9244 return NULL;
252b5132
RH		 9245
9246 globals = elf32_arm_hash_table (info);
252b5132
RH		 9247 BFD_ASSERT (globals != NULL);
9248 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9249
9250 my_offset = myh->root.u.def.value;
252b5132
RH		 9251
9252 if ((my_offset & 0x01) == 0x01)
9253 {
9254 if (sym_sec != NULL
9255 && sym_sec->owner != NULL
9256 && !INTERWORK_FLAG (sym_sec->owner))
9257 {
4eca0228 9258 _bfd_error_handler
90b6238f
AM		 9259 (_("%pB(%s): warning: interworking not enabled;"
9260 " first occurrence: %pB: %s call to %s"),
9261 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
252b5132 9262 }
9b485d32 9263
252b5132
RH		 9264 --my_offset;
9265 myh->root.u.def.value = my_offset;
9266
0e1862bb
L		 9267 if (bfd_link_pic (info)
9268 || globals->root.is_relocatable_executable
27e55c4d 9269 || globals->pic_veneer)
8f6277f5
PB		 9270 {
9271 /* For relocatable objects we can't use absolute addresses,
9272 so construct the address from a relative offset. */
9273 /* TODO: If the offset is small it's probably worth
9274 constructing the address with adds. */
52ab56c2
PB		 9275 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
9276 s->contents + my_offset);
9277 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
9278 s->contents + my_offset + 4);
9279 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
9280 s->contents + my_offset + 8);
8f6277f5
PB		 9281 /* Adjust the offset by 4 for the position of the add,
9282 and 8 for the pipeline offset. */
9283 ret_offset = (val - (s->output_offset
9284 + s->output_section->vma
9285 + my_offset + 12))
9286 | 1;
9287 bfd_put_32 (output_bfd, ret_offset,
9288 s->contents + my_offset + 12);
9289 }
26079076
PB		 9290 else if (globals->use_blx)
9291 {
9292 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
9293 s->contents + my_offset);
9294
9295 /* It's a thumb address. Add the low order bit. */
9296 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
9297 s->contents + my_offset + 4);
9298 }
8f6277f5
PB		 9299 else
9300 {
52ab56c2
PB		 9301 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
9302 s->contents + my_offset);
252b5132 9303
52ab56c2
PB		 9304 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
9305 s->contents + my_offset + 4);
252b5132 9306
8f6277f5
PB		 9307 /* It's a thumb address. Add the low order bit. */
9308 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
9309 s->contents + my_offset + 8);
8029a119
NC		 9310
9311 my_offset += 12;
8f6277f5 9312 }
252b5132
RH		 9313 }
9314
9315 BFD_ASSERT (my_offset <= globals->arm_glue_size);
9316
a4fd1a8e
PB		 9317 return myh;
9318}
9319
9320/* Arm code calling a Thumb function. */
9321
9322static int
9323elf32_arm_to_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9324 const char * name,
9325 bfd * input_bfd,
9326 bfd * output_bfd,
9327 asection * input_section,
9328 bfd_byte * hit_data,
9329 asection * sym_sec,
9330 bfd_vma offset,
9331 bfd_signed_vma addend,
9332 bfd_vma val,
f2a9dd69 9333 char **error_message)
a4fd1a8e
PB		 9334{
9335 unsigned long int tmp;
9336 bfd_vma my_offset;
9337 asection * s;
9338 long int ret_offset;
9339 struct elf_link_hash_entry * myh;
9340 struct elf32_arm_link_hash_table * globals;
9341
9342 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9343 BFD_ASSERT (globals != NULL);
9344 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9345
3d4d4302
AM		 9346 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9347 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9348 BFD_ASSERT (s != NULL);
9349 BFD_ASSERT (s->contents != NULL);
9350 BFD_ASSERT (s->output_section != NULL);
9351
9352 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 9353 sym_sec, val, s, error_message);
a4fd1a8e
PB		 9354 if (!myh)
9355 return FALSE;
9356
9357 my_offset = myh->root.u.def.value;
252b5132
RH		 9358 tmp = bfd_get_32 (input_bfd, hit_data);
9359 tmp = tmp & 0xFF000000;
9360
9b485d32 9361 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9362 ret_offset = (s->output_offset
9363 + my_offset
9364 + s->output_section->vma
9365 - (input_section->output_offset
9366 + input_section->output_section->vma
9367 + offset + addend)
9368 - 8);
9a5aca8c 9369
252b5132
RH		 9370 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9371
dc810e39 9372 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9373
b34976b6 9374 return TRUE;
252b5132
RH		 9375}
9376
a4fd1a8e
PB		 9377/* Populate Arm stub for an exported Thumb function. */
9378
9379static bfd_boolean
9380elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9381{
9382 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9383 asection * s;
9384 struct elf_link_hash_entry * myh;
9385 struct elf32_arm_link_hash_entry *eh;
9386 struct elf32_arm_link_hash_table * globals;
9387 asection *sec;
9388 bfd_vma val;
f2a9dd69 9389 char *error_message;
a4fd1a8e 9390
906e58ca 9391 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9392 /* Allocate stubs for exported Thumb functions on v4t. */
9393 if (eh->export_glue == NULL)
9394 return TRUE;
9395
9396 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9397 BFD_ASSERT (globals != NULL);
9398 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9399
3d4d4302
AM		 9400 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9401 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9402 BFD_ASSERT (s != NULL);
9403 BFD_ASSERT (s->contents != NULL);
9404 BFD_ASSERT (s->output_section != NULL);
9405
9406 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9407
9408 BFD_ASSERT (sec->output_section != NULL);
9409
a4fd1a8e
PB		 9410 val = eh->export_glue->root.u.def.value + sec->output_offset
9411 + sec->output_section->vma;
8029a119 9412
a4fd1a8e
PB		 9413 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9414 h->root.u.def.section->owner,
f2a9dd69
DJ		 9415 globals->obfd, sec, val, s,
9416 &error_message);
a4fd1a8e
PB		 9417 BFD_ASSERT (myh);
9418 return TRUE;
9419}
9420
845b51d6
PB		 9421/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9422
9423static bfd_vma
9424elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9425{
9426 bfd_byte *p;
9427 bfd_vma glue_addr;
9428 asection *s;
9429 struct elf32_arm_link_hash_table *globals;
9430
9431 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9432 BFD_ASSERT (globals != NULL);
9433 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9434
3d4d4302
AM		 9435 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9436 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9437 BFD_ASSERT (s != NULL);
9438 BFD_ASSERT (s->contents != NULL);
9439 BFD_ASSERT (s->output_section != NULL);
9440
9441 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9442
9443 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9444
9445 if ((globals->bx_glue_offset[reg] & 1) == 0)
9446 {
9447 p = s->contents + glue_addr;
9448 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9449 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9450 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9451 globals->bx_glue_offset[reg] |= 1;
9452 }
9453
9454 return glue_addr + s->output_section->vma + s->output_offset;
9455}
9456
a4fd1a8e
PB		 9457/* Generate Arm stubs for exported Thumb symbols. */
9458static void
906e58ca 9459elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9460 struct bfd_link_info *link_info)
9461{
9462 struct elf32_arm_link_hash_table * globals;
9463
8029a119
NC		 9464 if (link_info == NULL)
9465 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9466 return;
9467
9468 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9469 if (globals == NULL)
9470 return;
9471
84c08195
PB		 9472 /* If blx is available then exported Thumb symbols are OK and there is
9473 nothing to do. */
a4fd1a8e
PB		 9474 if (globals->use_blx)
9475 return;
9476
9477 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9478 link_info);
9479}
9480
47beaa6a
RS		 9481/* Reserve space for COUNT dynamic relocations in relocation selection
9482 SRELOC. */
9483
9484static void
9485elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9486 bfd_size_type count)
9487{
9488 struct elf32_arm_link_hash_table *htab;
9489
9490 htab = elf32_arm_hash_table (info);
9491 BFD_ASSERT (htab->root.dynamic_sections_created);
9492 if (sreloc == NULL)
9493 abort ();
9494 sreloc->size += RELOC_SIZE (htab) * count;
9495}
9496
34e77a92
RS		 9497/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9498 dynamic, the relocations should go in SRELOC, otherwise they should
9499 go in the special .rel.iplt section. */
9500
9501static void
9502elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9503 bfd_size_type count)
9504{
9505 struct elf32_arm_link_hash_table *htab;
9506
9507 htab = elf32_arm_hash_table (info);
9508 if (!htab->root.dynamic_sections_created)
9509 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9510 else
9511 {
9512 BFD_ASSERT (sreloc != NULL);
9513 sreloc->size += RELOC_SIZE (htab) * count;
9514 }
9515}
9516
47beaa6a
RS		 9517/* Add relocation REL to the end of relocation section SRELOC. */
9518
9519static void
9520elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9521 asection *sreloc, Elf_Internal_Rela *rel)
9522{
9523 bfd_byte *loc;
9524 struct elf32_arm_link_hash_table *htab;
9525
9526 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9527 if (!htab->root.dynamic_sections_created
9528 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9529 sreloc = htab->root.irelplt;
47beaa6a
RS		 9530 if (sreloc == NULL)
9531 abort ();
9532 loc = sreloc->contents;
9533 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9534 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9535 abort ();
9536 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9537}
9538
34e77a92
RS		 9539/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9540 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9541 to .plt. */
9542
9543static void
9544elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9545 bfd_boolean is_iplt_entry,
9546 union gotplt_union *root_plt,
9547 struct arm_plt_info *arm_plt)
9548{
9549 struct elf32_arm_link_hash_table *htab;
9550 asection *splt;
9551 asection *sgotplt;
9552
9553 htab = elf32_arm_hash_table (info);
9554
9555 if (is_iplt_entry)
9556 {
9557 splt = htab->root.iplt;
9558 sgotplt = htab->root.igotplt;
9559
99059e56
RM		 9560 /* NaCl uses a special first entry in .iplt too. */
9561 if (htab->nacl_p && splt->size == 0)
9562 splt->size += htab->plt_header_size;
9563
34e77a92
RS		 9564 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9565 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9566 }
9567 else
9568 {
9569 splt = htab->root.splt;
9570 sgotplt = htab->root.sgotplt;
9571
7801f98f
CL		 9572 if (htab->fdpic_p)
9573 {
9574 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9575 /* For lazy binding, relocations will be put into .rel.plt, in
9576 .rel.got otherwise. */
9577 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9578 if (info->flags & DF_BIND_NOW)
9579 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
9580 else
9581 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9582 }
9583 else
9584 {
9585 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9586 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9587 }
34e77a92
RS		 9588
9589 /* If this is the first .plt entry, make room for the special
9590 first entry. */
9591 if (splt->size == 0)
9592 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9593
9594 htab->next_tls_desc_index++;
34e77a92
RS		 9595 }
9596
9597 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9598 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9599 splt->size += PLT_THUMB_STUB_SIZE;
9600 root_plt->offset = splt->size;
9601 splt->size += htab->plt_entry_size;
9602
9603 if (!htab->symbian_p)
9604 {
9605 /* We also need to make an entry in the .got.plt section, which
9606 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9607 if (is_iplt_entry)
9608 arm_plt->got_offset = sgotplt->size;
9609 else
9610 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
7801f98f
CL		 9611 if (htab->fdpic_p)
9612 /* Function descriptor takes 64 bits in GOT. */
4b24dd1a 9613 sgotplt->size += 8;
7801f98f
CL		 9614 else
9615 sgotplt->size += 4;
34e77a92
RS		 9616 }
9617}
9618
b38cadfb
NC		 9619static bfd_vma
9620arm_movw_immediate (bfd_vma value)
9621{
9622 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9623}
9624
9625static bfd_vma
9626arm_movt_immediate (bfd_vma value)
9627{
9628 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9629}
9630
34e77a92
RS		 9631/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9632 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9633 Otherwise, DYNINDX is the index of the symbol in the dynamic
9634 symbol table and SYM_VALUE is undefined.
9635
9636 ROOT_PLT points to the offset of the PLT entry from the start of its
9637 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9638 bookkeeping information.
34e77a92 9639
57460bcf
NC		 9640 Returns FALSE if there was a problem. */
9641
9642static bfd_boolean
34e77a92
RS		 9643elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9644 union gotplt_union *root_plt,
9645 struct arm_plt_info *arm_plt,
9646 int dynindx, bfd_vma sym_value)
9647{
9648 struct elf32_arm_link_hash_table *htab;
9649 asection *sgot;
9650 asection *splt;
9651 asection *srel;
9652 bfd_byte *loc;
9653 bfd_vma plt_index;
9654 Elf_Internal_Rela rel;
9655 bfd_vma plt_header_size;
9656 bfd_vma got_header_size;
9657
9658 htab = elf32_arm_hash_table (info);
9659
9660 /* Pick the appropriate sections and sizes. */
9661 if (dynindx == -1)
9662 {
9663 splt = htab->root.iplt;
9664 sgot = htab->root.igotplt;
9665 srel = htab->root.irelplt;
9666
9667 /* There are no reserved entries in .igot.plt, and no special
9668 first entry in .iplt. */
9669 got_header_size = 0;
9670 plt_header_size = 0;
9671 }
9672 else
9673 {
9674 splt = htab->root.splt;
9675 sgot = htab->root.sgotplt;
9676 srel = htab->root.srelplt;
9677
9678 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9679 plt_header_size = htab->plt_header_size;
9680 }
9681 BFD_ASSERT (splt != NULL && srel != NULL);
9682
9683 /* Fill in the entry in the procedure linkage table. */
9684 if (htab->symbian_p)
9685 {
9686 BFD_ASSERT (dynindx >= 0);
9687 put_arm_insn (htab, output_bfd,
9688 elf32_arm_symbian_plt_entry[0],
9689 splt->contents + root_plt->offset);
9690 bfd_put_32 (output_bfd,
9691 elf32_arm_symbian_plt_entry[1],
9692 splt->contents + root_plt->offset + 4);
9693
9694 /* Fill in the entry in the .rel.plt section. */
9695 rel.r_offset = (splt->output_section->vma
9696 + splt->output_offset
9697 + root_plt->offset + 4);
9698 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9699
9700 /* Get the index in the procedure linkage table which
9701 corresponds to this symbol. This is the index of this symbol
9702 in all the symbols for which we are making plt entries. The
9703 first entry in the procedure linkage table is reserved. */
9704 plt_index = ((root_plt->offset - plt_header_size)
9705 / htab->plt_entry_size);
9706 }
9707 else
9708 {
9709 bfd_vma got_offset, got_address, plt_address;
9710 bfd_vma got_displacement, initial_got_entry;
9711 bfd_byte * ptr;
9712
9713 BFD_ASSERT (sgot != NULL);
9714
9715 /* Get the offset into the .(i)got.plt table of the entry that
9716 corresponds to this function. */
9717 got_offset = (arm_plt->got_offset & -2);
9718
9719 /* Get the index in the procedure linkage table which
9720 corresponds to this symbol. This is the index of this symbol
9721 in all the symbols for which we are making plt entries.
9722 After the reserved .got.plt entries, all symbols appear in
9723 the same order as in .plt. */
7801f98f 9724 if (htab->fdpic_p)
4b24dd1a
AM		 9725 /* Function descriptor takes 8 bytes. */
9726 plt_index = (got_offset - got_header_size) / 8;
7801f98f 9727 else
4b24dd1a 9728 plt_index = (got_offset - got_header_size) / 4;
34e77a92
RS		 9729
9730 /* Calculate the address of the GOT entry. */
9731 got_address = (sgot->output_section->vma
9732 + sgot->output_offset
9733 + got_offset);
9734
9735 /* ...and the address of the PLT entry. */
9736 plt_address = (splt->output_section->vma
9737 + splt->output_offset
9738 + root_plt->offset);
9739
9740 ptr = splt->contents + root_plt->offset;
0e1862bb 9741 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9742 {
9743 unsigned int i;
9744 bfd_vma val;
9745
9746 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9747 {
9748 val = elf32_arm_vxworks_shared_plt_entry[i];
9749 if (i == 2)
9750 val |= got_address - sgot->output_section->vma;
9751 if (i == 5)
9752 val |= plt_index * RELOC_SIZE (htab);
9753 if (i == 2 || i == 5)
9754 bfd_put_32 (output_bfd, val, ptr);
9755 else
9756 put_arm_insn (htab, output_bfd, val, ptr);
9757 }
9758 }
9759 else if (htab->vxworks_p)
9760 {
9761 unsigned int i;
9762 bfd_vma val;
9763
9764 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9765 {
9766 val = elf32_arm_vxworks_exec_plt_entry[i];
9767 if (i == 2)
9768 val |= got_address;
9769 if (i == 4)
9770 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9771 if (i == 5)
9772 val |= plt_index * RELOC_SIZE (htab);
9773 if (i == 2 || i == 5)
9774 bfd_put_32 (output_bfd, val, ptr);
9775 else
9776 put_arm_insn (htab, output_bfd, val, ptr);
9777 }
9778
9779 loc = (htab->srelplt2->contents
9780 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9781
9782 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9783 referencing the GOT for this PLT entry. */
9784 rel.r_offset = plt_address + 8;
9785 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9786 rel.r_addend = got_offset;
9787 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9788 loc += RELOC_SIZE (htab);
9789
9790 /* Create the R_ARM_ABS32 relocation referencing the
9791 beginning of the PLT for this GOT entry. */
9792 rel.r_offset = got_address;
9793 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9794 rel.r_addend = 0;
9795 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9796 }
b38cadfb
NC		 9797 else if (htab->nacl_p)
9798 {
9799 /* Calculate the displacement between the PLT slot and the
9800 common tail that's part of the special initial PLT slot. */
6034aab8 9801 int32_t tail_displacement
b38cadfb
NC		 9802 = ((splt->output_section->vma + splt->output_offset
9803 + ARM_NACL_PLT_TAIL_OFFSET)
9804 - (plt_address + htab->plt_entry_size + 4));
9805 BFD_ASSERT ((tail_displacement & 3) == 0);
9806 tail_displacement >>= 2;
9807
9808 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9809 || (-tail_displacement & 0xff000000) == 0);
9810
9811 /* Calculate the displacement between the PLT slot and the entry
9812 in the GOT. The offset accounts for the value produced by
9813 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9814 got_displacement = (got_address
99059e56 9815 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9816
9817 /* NaCl does not support interworking at all. */
9818 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9819
9820 put_arm_insn (htab, output_bfd,
9821 elf32_arm_nacl_plt_entry[0]
9822 | arm_movw_immediate (got_displacement),
9823 ptr + 0);
9824 put_arm_insn (htab, output_bfd,
9825 elf32_arm_nacl_plt_entry[1]
9826 | arm_movt_immediate (got_displacement),
9827 ptr + 4);
9828 put_arm_insn (htab, output_bfd,
9829 elf32_arm_nacl_plt_entry[2],
9830 ptr + 8);
9831 put_arm_insn (htab, output_bfd,
9832 elf32_arm_nacl_plt_entry[3]
9833 | (tail_displacement & 0x00ffffff),
9834 ptr + 12);
9835 }
7801f98f
CL		 9836 else if (htab->fdpic_p)
9837 {
59029f57
CL		 9838 const bfd_vma *plt_entry = using_thumb_only(htab)
9839 ? elf32_arm_fdpic_thumb_plt_entry
9840 : elf32_arm_fdpic_plt_entry;
9841
7801f98f
CL		 9842 /* Fill-up Thumb stub if needed. */
9843 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9844 {
9845 put_thumb_insn (htab, output_bfd,
9846 elf32_arm_plt_thumb_stub[0], ptr - 4);
9847 put_thumb_insn (htab, output_bfd,
9848 elf32_arm_plt_thumb_stub[1], ptr - 2);
9849 }
59029f57
CL		 9850 /* As we are using 32 bit instructions even for the Thumb
9851 version, we have to use 'put_arm_insn' instead of
9852 'put_thumb_insn'. */
9853 put_arm_insn(htab, output_bfd, plt_entry[0], ptr + 0);
9854 put_arm_insn(htab, output_bfd, plt_entry[1], ptr + 4);
9855 put_arm_insn(htab, output_bfd, plt_entry[2], ptr + 8);
9856 put_arm_insn(htab, output_bfd, plt_entry[3], ptr + 12);
7801f98f
CL		 9857 bfd_put_32 (output_bfd, got_offset, ptr + 16);
9858
9859 if (!(info->flags & DF_BIND_NOW))
9860 {
9861 /* funcdesc_value_reloc_offset. */
9862 bfd_put_32 (output_bfd,
9863 htab->root.srelplt->reloc_count * RELOC_SIZE (htab),
9864 ptr + 20);
59029f57
CL		 9865 put_arm_insn(htab, output_bfd, plt_entry[6], ptr + 24);
9866 put_arm_insn(htab, output_bfd, plt_entry[7], ptr + 28);
9867 put_arm_insn(htab, output_bfd, plt_entry[8], ptr + 32);
9868 put_arm_insn(htab, output_bfd, plt_entry[9], ptr + 36);
7801f98f
CL		 9869 }
9870 }
57460bcf
NC		 9871 else if (using_thumb_only (htab))
9872 {
eed94f8f 9873 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9874 if (!using_thumb2 (htab))
eed94f8f
NC		 9875 {
9876 /* FIXME: We ought to be able to generate thumb-1 PLT
9877 instructions... */
90b6238f 9878 _bfd_error_handler (_("%pB: warning: thumb-1 mode PLT generation not currently supported"),
eed94f8f
NC		 9879 output_bfd);
9880 return FALSE;
9881 }
57460bcf 9882
eed94f8f
NC		 9883 /* Calculate the displacement between the PLT slot and the entry in
9884 the GOT. The 12-byte offset accounts for the value produced by
9885 adding to pc in the 3rd instruction of the PLT stub. */
9886 got_displacement = got_address - (plt_address + 12);
9887
9888 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9889 instead of 'put_thumb_insn'. */
9890 put_arm_insn (htab, output_bfd,
9891 elf32_thumb2_plt_entry[0]
9892 | ((got_displacement & 0x000000ff) << 16)
9893 | ((got_displacement & 0x00000700) << 20)
9894 | ((got_displacement & 0x00000800) >> 1)
9895 | ((got_displacement & 0x0000f000) >> 12),
9896 ptr + 0);
9897 put_arm_insn (htab, output_bfd,
9898 elf32_thumb2_plt_entry[1]
9899 | ((got_displacement & 0x00ff0000) )
9900 | ((got_displacement & 0x07000000) << 4)
9901 | ((got_displacement & 0x08000000) >> 17)
9902 | ((got_displacement & 0xf0000000) >> 28),
9903 ptr + 4);
9904 put_arm_insn (htab, output_bfd,
9905 elf32_thumb2_plt_entry[2],
9906 ptr + 8);
9907 put_arm_insn (htab, output_bfd,
9908 elf32_thumb2_plt_entry[3],
9909 ptr + 12);
57460bcf 9910 }
34e77a92
RS		 9911 else
9912 {
9913 /* Calculate the displacement between the PLT slot and the
9914 entry in the GOT. The eight-byte offset accounts for the
9915 value produced by adding to pc in the first instruction
9916 of the PLT stub. */
9917 got_displacement = got_address - (plt_address + 8);
9918
34e77a92
RS		 9919 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9920 {
9921 put_thumb_insn (htab, output_bfd,
9922 elf32_arm_plt_thumb_stub[0], ptr - 4);
9923 put_thumb_insn (htab, output_bfd,
9924 elf32_arm_plt_thumb_stub[1], ptr - 2);
9925 }
9926
1db37fe6
YG		 9927 if (!elf32_arm_use_long_plt_entry)
9928 {
9929 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9930
9931 put_arm_insn (htab, output_bfd,
9932 elf32_arm_plt_entry_short[0]
9933 | ((got_displacement & 0x0ff00000) >> 20),
9934 ptr + 0);
9935 put_arm_insn (htab, output_bfd,
9936 elf32_arm_plt_entry_short[1]
9937 | ((got_displacement & 0x000ff000) >> 12),
9938 ptr+ 4);
9939 put_arm_insn (htab, output_bfd,
9940 elf32_arm_plt_entry_short[2]
9941 | (got_displacement & 0x00000fff),
9942 ptr + 8);
34e77a92 9943#ifdef FOUR_WORD_PLT
1db37fe6 9944 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9945#endif
1db37fe6
YG		 9946 }
9947 else
9948 {
9949 put_arm_insn (htab, output_bfd,
9950 elf32_arm_plt_entry_long[0]
9951 | ((got_displacement & 0xf0000000) >> 28),
9952 ptr + 0);
9953 put_arm_insn (htab, output_bfd,
9954 elf32_arm_plt_entry_long[1]
9955 | ((got_displacement & 0x0ff00000) >> 20),
9956 ptr + 4);
9957 put_arm_insn (htab, output_bfd,
9958 elf32_arm_plt_entry_long[2]
9959 | ((got_displacement & 0x000ff000) >> 12),
9960 ptr+ 8);
9961 put_arm_insn (htab, output_bfd,
9962 elf32_arm_plt_entry_long[3]
9963 | (got_displacement & 0x00000fff),
9964 ptr + 12);
9965 }
34e77a92
RS		 9966 }
9967
9968 /* Fill in the entry in the .rel(a).(i)plt section. */
9969 rel.r_offset = got_address;
9970 rel.r_addend = 0;
9971 if (dynindx == -1)
9972 {
9973 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9974 The dynamic linker or static executable then calls SYM_VALUE
9975 to determine the correct run-time value of the .igot.plt entry. */
9976 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9977 initial_got_entry = sym_value;
9978 }
9979 else
9980 {
7801f98f
CL		 9981 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9982 used by PLT entry. */
9983 if (htab->fdpic_p)
9984 {
9985 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
9986 initial_got_entry = 0;
9987 }
9988 else
9989 {
9990 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9991 initial_got_entry = (splt->output_section->vma
9992 + splt->output_offset);
9993 }
34e77a92
RS		 9994 }
9995
9996 /* Fill in the entry in the global offset table. */
9997 bfd_put_32 (output_bfd, initial_got_entry,
9998 sgot->contents + got_offset);
7801f98f
CL		 9999
10000 if (htab->fdpic_p && !(info->flags & DF_BIND_NOW))
10001 {
10002 /* Setup initial funcdesc value. */
10003 /* FIXME: we don't support lazy binding because there is a
10004 race condition between both words getting written and
10005 some other thread attempting to read them. The ARM
10006 architecture does not have an atomic 64 bit load/store
10007 instruction that could be used to prevent it; it is
10008 recommended that threaded FDPIC applications run with the
10009 LD_BIND_NOW environment variable set. */
10010 bfd_put_32(output_bfd, plt_address + 0x18,
10011 sgot->contents + got_offset);
10012 bfd_put_32(output_bfd, -1 /*TODO*/,
10013 sgot->contents + got_offset + 4);
10014 }
34e77a92
RS		 10015 }
10016
aba8c3de
WN		 10017 if (dynindx == -1)
10018 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
10019 else
10020 {
7801f98f
CL		 10021 if (htab->fdpic_p)
10022 {
10023 /* For FDPIC we put PLT relocationss into .rel.got when not
10024 lazy binding otherwise we put them in .rel.plt. For now,
10025 we don't support lazy binding so put it in .rel.got. */
10026 if (info->flags & DF_BIND_NOW)
10027 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelgot, &rel);
10028 else
10029 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelplt, &rel);
10030 }
10031 else
10032 {
10033 loc = srel->contents + plt_index * RELOC_SIZE (htab);
10034 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
10035 }
aba8c3de 10036 }
57460bcf
NC		 10037
10038 return TRUE;
34e77a92
RS		 10039}
10040
eb043451
PB		 10041/* Some relocations map to different relocations depending on the
10042 target. Return the real relocation. */
8029a119 10043
eb043451
PB		 10044static int
10045arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
10046 int r_type)
10047{
10048 switch (r_type)
10049 {
10050 case R_ARM_TARGET1:
10051 if (globals->target1_is_rel)
10052 return R_ARM_REL32;
10053 else
10054 return R_ARM_ABS32;
10055
10056 case R_ARM_TARGET2:
10057 return globals->target2_reloc;
10058
10059 default:
10060 return r_type;
10061 }
10062}
eb043451 10063
ba93b8ac
DJ		 10064/* Return the base VMA address which should be subtracted from real addresses
10065 when resolving @dtpoff relocation.
10066 This is PT_TLS segment p_vaddr. */
10067
10068static bfd_vma
10069dtpoff_base (struct bfd_link_info *info)
10070{
10071 /* If tls_sec is NULL, we should have signalled an error already. */
10072 if (elf_hash_table (info)->tls_sec == NULL)
10073 return 0;
10074 return elf_hash_table (info)->tls_sec->vma;
10075}
10076
10077/* Return the relocation value for @tpoff relocation
10078 if STT_TLS virtual address is ADDRESS. */
10079
10080static bfd_vma
10081tpoff (struct bfd_link_info *info, bfd_vma address)
10082{
10083 struct elf_link_hash_table *htab = elf_hash_table (info);
10084 bfd_vma base;
10085
10086 /* If tls_sec is NULL, we should have signalled an error already. */
10087 if (htab->tls_sec == NULL)
10088 return 0;
10089 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
10090 return address - htab->tls_sec->vma + base;
10091}
10092
00a97672
RS		 10093/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10094 VALUE is the relocation value. */
10095
10096static bfd_reloc_status_type
10097elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
10098{
10099 if (value > 0xfff)
10100 return bfd_reloc_overflow;
10101
10102 value |= bfd_get_32 (abfd, data) & 0xfffff000;
10103 bfd_put_32 (abfd, value, data);
10104 return bfd_reloc_ok;
10105}
10106
0855e32b
NS		 10107/* Handle TLS relaxations. Relaxing is possible for symbols that use
10108 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10109 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10110
10111 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10112 is to then call final_link_relocate. Return other values in the
62672b10
NS		 10113 case of error.
10114
10115 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10116 the pre-relaxed code. It would be nice if the relocs were updated
10117 to match the optimization. */
0855e32b 10118
b38cadfb 10119static bfd_reloc_status_type
0855e32b 10120elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 10121 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 10122 Elf_Internal_Rela *rel, unsigned long is_local)
10123{
10124 unsigned long insn;
b38cadfb 10125
0855e32b
NS		 10126 switch (ELF32_R_TYPE (rel->r_info))
10127 {
10128 default:
10129 return bfd_reloc_notsupported;
b38cadfb 10130
0855e32b
NS		 10131 case R_ARM_TLS_GOTDESC:
10132 if (is_local)
10133 insn = 0;
10134 else
10135 {
10136 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10137 if (insn & 1)
10138 insn -= 5; /* THUMB */
10139 else
10140 insn -= 8; /* ARM */
10141 }
10142 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10143 return bfd_reloc_continue;
10144
10145 case R_ARM_THM_TLS_DESCSEQ:
10146 /* Thumb insn. */
10147 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
10148 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
10149 {
10150 if (is_local)
10151 /* nop */
10152 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10153 }
10154 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
10155 {
10156 if (is_local)
10157 /* nop */
10158 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10159 else
10160 /* ldr rx,[ry] */
10161 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
10162 }
10163 else if ((insn & 0xff87) == 0x4780) /* blx rx */
10164 {
10165 if (is_local)
10166 /* nop */
10167 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10168 else
10169 /* mov r0, rx */
10170 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
10171 contents + rel->r_offset);
10172 }
10173 else
10174 {
10175 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10176 /* It's a 32 bit instruction, fetch the rest of it for
10177 error generation. */
10178 insn = (insn << 16)
10179 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 10180 _bfd_error_handler
695344c0 10181 /* xgettext:c-format */
2dcf00ce 10182 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10183 "unexpected %s instruction '%#lx' in TLS trampoline"),
10184 input_bfd, input_sec, (uint64_t) rel->r_offset,
10185 "Thumb", insn);
0855e32b
NS		 10186 return bfd_reloc_notsupported;
10187 }
10188 break;
b38cadfb 10189
0855e32b
NS		 10190 case R_ARM_TLS_DESCSEQ:
10191 /* arm insn. */
10192 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10193 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
10194 {
10195 if (is_local)
10196 /* mov rx, ry */
10197 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
10198 contents + rel->r_offset);
10199 }
10200 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
10201 {
10202 if (is_local)
10203 /* nop */
10204 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10205 else
10206 /* ldr rx,[ry] */
10207 bfd_put_32 (input_bfd, insn & 0xfffff000,
10208 contents + rel->r_offset);
10209 }
10210 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
10211 {
10212 if (is_local)
10213 /* nop */
10214 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10215 else
10216 /* mov r0, rx */
10217 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
10218 contents + rel->r_offset);
10219 }
10220 else
10221 {
4eca0228 10222 _bfd_error_handler
695344c0 10223 /* xgettext:c-format */
2dcf00ce 10224 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10225 "unexpected %s instruction '%#lx' in TLS trampoline"),
10226 input_bfd, input_sec, (uint64_t) rel->r_offset,
10227 "ARM", insn);
0855e32b
NS		 10228 return bfd_reloc_notsupported;
10229 }
10230 break;
10231
10232 case R_ARM_TLS_CALL:
10233 /* GD->IE relaxation, turn the instruction into 'nop' or
10234 'ldr r0, [pc,r0]' */
10235 insn = is_local ? 0xe1a00000 : 0xe79f0000;
10236 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10237 break;
b38cadfb 10238
0855e32b 10239 case R_ARM_THM_TLS_CALL:
6a631e86 10240 /* GD->IE relaxation. */
0855e32b
NS		 10241 if (!is_local)
10242 /* add r0,pc; ldr r0, [r0] */
10243 insn = 0x44786800;
60a019a0 10244 else if (using_thumb2 (globals))
0855e32b
NS		 10245 /* nop.w */
10246 insn = 0xf3af8000;
10247 else
10248 /* nop; nop */
10249 insn = 0xbf00bf00;
b38cadfb 10250
0855e32b
NS		 10251 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
10252 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
10253 break;
10254 }
10255 return bfd_reloc_ok;
10256}
10257
4962c51a
MS		 10258/* For a given value of n, calculate the value of G_n as required to
10259 deal with group relocations. We return it in the form of an
10260 encoded constant-and-rotation, together with the final residual. If n is
10261 specified as less than zero, then final_residual is filled with the
10262 input value and no further action is performed. */
10263
10264static bfd_vma
10265calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
10266{
10267 int current_n;
10268 bfd_vma g_n;
10269 bfd_vma encoded_g_n = 0;
10270 bfd_vma residual = value; /* Also known as Y_n. */
10271
10272 for (current_n = 0; current_n <= n; current_n++)
10273 {
10274 int shift;
10275
10276 /* Calculate which part of the value to mask. */
10277 if (residual == 0)
99059e56 10278 shift = 0;
4962c51a 10279 else
99059e56
RM		 10280 {
10281 int msb;
10282
10283 /* Determine the most significant bit in the residual and
10284 align the resulting value to a 2-bit boundary. */
10285 for (msb = 30; msb >= 0; msb -= 2)
10286 if (residual & (3 << msb))
10287 break;
10288
10289 /* The desired shift is now (msb - 6), or zero, whichever
10290 is the greater. */
10291 shift = msb - 6;
10292 if (shift < 0)
10293 shift = 0;
10294 }
4962c51a
MS		 10295
10296 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10297 g_n = residual & (0xff << shift);
10298 encoded_g_n = (g_n >> shift)
99059e56 10299 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 10300
10301 /* Calculate the residual for the next time around. */
10302 residual &= ~g_n;
10303 }
10304
10305 *final_residual = residual;
10306
10307 return encoded_g_n;
10308}
10309
10310/* Given an ARM instruction, determine whether it is an ADD or a SUB.
10311 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 10312
4962c51a 10313static int
906e58ca 10314identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 10315{
10316 int opcode = insn & 0x1e00000;
10317
10318 if (opcode == 1 << 23) /* ADD */
10319 return 1;
10320
10321 if (opcode == 1 << 22) /* SUB */
10322 return -1;
10323
10324 return 0;
10325}
10326
252b5132 10327/* Perform a relocation as part of a final link. */
9b485d32 10328
252b5132 10329static bfd_reloc_status_type
07d6d2b8
AM		 10330elf32_arm_final_link_relocate (reloc_howto_type * howto,
10331 bfd * input_bfd,
10332 bfd * output_bfd,
10333 asection * input_section,
10334 bfd_byte * contents,
10335 Elf_Internal_Rela * rel,
10336 bfd_vma value,
10337 struct bfd_link_info * info,
10338 asection * sym_sec,
10339 const char * sym_name,
10340 unsigned char st_type,
10341 enum arm_st_branch_type branch_type,
0945cdfd 10342 struct elf_link_hash_entry * h,
07d6d2b8
AM		 10343 bfd_boolean * unresolved_reloc_p,
10344 char ** error_message)
10345{
10346 unsigned long r_type = howto->type;
10347 unsigned long r_symndx;
10348 bfd_byte * hit_data = contents + rel->r_offset;
10349 bfd_vma * local_got_offsets;
10350 bfd_vma * local_tlsdesc_gotents;
10351 asection * sgot;
10352 asection * splt;
10353 asection * sreloc = NULL;
10354 asection * srelgot;
10355 bfd_vma addend;
10356 bfd_signed_vma signed_addend;
10357 unsigned char dynreloc_st_type;
10358 bfd_vma dynreloc_value;
ba96a88f 10359 struct elf32_arm_link_hash_table * globals;
34e77a92 10360 struct elf32_arm_link_hash_entry *eh;
07d6d2b8
AM		 10361 union gotplt_union *root_plt;
10362 struct arm_plt_info *arm_plt;
10363 bfd_vma plt_offset;
10364 bfd_vma gotplt_offset;
10365 bfd_boolean has_iplt_entry;
10366 bfd_boolean resolved_to_zero;
f21f3fe0 10367
9c504268 10368 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 10369 if (globals == NULL)
10370 return bfd_reloc_notsupported;
9c504268 10371
0ffa91dd 10372 BFD_ASSERT (is_arm_elf (input_bfd));
47aeb64c 10373 BFD_ASSERT (howto != NULL);
0ffa91dd
NC		 10374
10375 /* Some relocation types map to different relocations depending on the
9c504268 10376 target. We pick the right one here. */
eb043451 10377 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 10378
10379 /* It is possible to have linker relaxations on some TLS access
10380 models. Update our information here. */
10381 r_type = elf32_arm_tls_transition (info, r_type, h);
10382
eb043451
PB		 10383 if (r_type != howto->type)
10384 howto = elf32_arm_howto_from_type (r_type);
9c504268 10385
34e77a92 10386 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 10387 sgot = globals->root.sgot;
252b5132 10388 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 10389 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
10390
34e77a92
RS		 10391 if (globals->root.dynamic_sections_created)
10392 srelgot = globals->root.srelgot;
10393 else
10394 srelgot = NULL;
10395
252b5132
RH		 10396 r_symndx = ELF32_R_SYM (rel->r_info);
10397
4e7fd91e 10398 if (globals->use_rel)
ba96a88f 10399 {
4e7fd91e
PB		 10400 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
10401
10402 if (addend & ((howto->src_mask + 1) >> 1))
10403 {
10404 signed_addend = -1;
10405 signed_addend &= ~ howto->src_mask;
10406 signed_addend |= addend;
10407 }
10408 else
10409 signed_addend = addend;
ba96a88f
NC		 10410 }
10411 else
4e7fd91e 10412 addend = signed_addend = rel->r_addend;
f21f3fe0 10413
39f21624
NC		 10414 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10415 are resolving a function call relocation. */
10416 if (using_thumb_only (globals)
10417 && (r_type == R_ARM_THM_CALL
10418 || r_type == R_ARM_THM_JUMP24)
10419 && branch_type == ST_BRANCH_TO_ARM)
10420 branch_type = ST_BRANCH_TO_THUMB;
10421
34e77a92
RS		 10422 /* Record the symbol information that should be used in dynamic
10423 relocations. */
10424 dynreloc_st_type = st_type;
10425 dynreloc_value = value;
10426 if (branch_type == ST_BRANCH_TO_THUMB)
10427 dynreloc_value |= 1;
10428
10429 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10430 VALUE appropriately for relocations that we resolve at link time. */
10431 has_iplt_entry = FALSE;
4ba2ef8f
TP		 10432 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
10433 &arm_plt)
34e77a92
RS		 10434 && root_plt->offset != (bfd_vma) -1)
10435 {
10436 plt_offset = root_plt->offset;
10437 gotplt_offset = arm_plt->got_offset;
10438
10439 if (h == NULL || eh->is_iplt)
10440 {
10441 has_iplt_entry = TRUE;
10442 splt = globals->root.iplt;
10443
10444 /* Populate .iplt entries here, because not all of them will
10445 be seen by finish_dynamic_symbol. The lower bit is set if
10446 we have already populated the entry. */
10447 if (plt_offset & 1)
10448 plt_offset--;
10449 else
10450 {
57460bcf
NC		 10451 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
10452 -1, dynreloc_value))
10453 root_plt->offset |= 1;
10454 else
10455 return bfd_reloc_notsupported;
34e77a92
RS		 10456 }
10457
10458 /* Static relocations always resolve to the .iplt entry. */
10459 st_type = STT_FUNC;
10460 value = (splt->output_section->vma
10461 + splt->output_offset
10462 + plt_offset);
10463 branch_type = ST_BRANCH_TO_ARM;
10464
10465 /* If there are non-call relocations that resolve to the .iplt
10466 entry, then all dynamic ones must too. */
10467 if (arm_plt->noncall_refcount != 0)
10468 {
10469 dynreloc_st_type = st_type;
10470 dynreloc_value = value;
10471 }
10472 }
10473 else
10474 /* We populate the .plt entry in finish_dynamic_symbol. */
10475 splt = globals->root.splt;
10476 }
10477 else
10478 {
10479 splt = NULL;
10480 plt_offset = (bfd_vma) -1;
10481 gotplt_offset = (bfd_vma) -1;
10482 }
10483
95b03e4a
L		 10484 resolved_to_zero = (h != NULL
10485 && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
10486
252b5132
RH		 10487 switch (r_type)
10488 {
10489 case R_ARM_NONE:
28a094c2
DJ		 10490 /* We don't need to find a value for this symbol. It's just a
10491 marker. */
10492 *unresolved_reloc_p = FALSE;
252b5132
RH		 10493 return bfd_reloc_ok;
10494
00a97672
RS		 10495 case R_ARM_ABS12:
10496 if (!globals->vxworks_p)
10497 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10498 /* Fall through. */
00a97672 10499
252b5132
RH		 10500 case R_ARM_PC24:
10501 case R_ARM_ABS32:
bb224fc3 10502 case R_ARM_ABS32_NOI:
252b5132 10503 case R_ARM_REL32:
bb224fc3 10504 case R_ARM_REL32_NOI:
5b5bb741
PB		 10505 case R_ARM_CALL:
10506 case R_ARM_JUMP24:
dfc5f959 10507 case R_ARM_XPC25:
eb043451 10508 case R_ARM_PREL31:
7359ea65 10509 case R_ARM_PLT32:
7359ea65
DJ		 10510 /* Handle relocations which should use the PLT entry. ABS32/REL32
10511 will use the symbol's value, which may point to a PLT entry, but we
10512 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10513 branches in this object should go to it, except if the PLT is too
10514 far away, in which case a long branch stub should be inserted. */
bb224fc3 10515 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10516 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10517 && r_type != R_ARM_CALL
10518 && r_type != R_ARM_JUMP24
10519 && r_type != R_ARM_PLT32)
34e77a92 10520 && plt_offset != (bfd_vma) -1)
7359ea65 10521 {
34e77a92
RS		 10522 /* If we've created a .plt section, and assigned a PLT entry
10523 to this function, it must either be a STT_GNU_IFUNC reference
10524 or not be known to bind locally. In other cases, we should
10525 have cleared the PLT entry by now. */
10526 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10527
10528 value = (splt->output_section->vma
10529 + splt->output_offset
34e77a92 10530 + plt_offset);
0945cdfd 10531 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10532 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10533 contents, rel->r_offset, value,
00a97672 10534 rel->r_addend);
7359ea65
DJ		 10535 }
10536
67687978
PB		 10537 /* When generating a shared object or relocatable executable, these
10538 relocations are copied into the output file to be resolved at
10539 run time. */
0e1862bb 10540 if ((bfd_link_pic (info)
e8b09b87
CL		 10541 || globals->root.is_relocatable_executable
10542 || globals->fdpic_p)
7359ea65 10543 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10544 && !(globals->vxworks_p
3348747a
NS		 10545 && strcmp (input_section->output_section->name,
10546 ".tls_vars") == 0)
bb224fc3 10547 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10548 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10549 && !(input_bfd == globals->stub_bfd
10550 && strstr (input_section->name, STUB_SUFFIX))
7359ea65 10551 && (h == NULL
95b03e4a
L		 10552 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10553 && !resolved_to_zero)
7359ea65
DJ		 10554 || h->root.type != bfd_link_hash_undefweak)
10555 && r_type != R_ARM_PC24
5b5bb741
PB		 10556 && r_type != R_ARM_CALL
10557 && r_type != R_ARM_JUMP24
ee06dc07 10558 && r_type != R_ARM_PREL31
7359ea65 10559 && r_type != R_ARM_PLT32)
252b5132 10560 {
947216bf 10561 Elf_Internal_Rela outrel;
b34976b6 10562 bfd_boolean skip, relocate;
e8b09b87 10563 int isrofixup = 0;
f21f3fe0 10564
52db4ec2
JW		 10565 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10566 && !h->def_regular)
10567 {
10568 char *v = _("shared object");
10569
0e1862bb 10570 if (bfd_link_executable (info))
52db4ec2
JW		 10571 v = _("PIE executable");
10572
4eca0228 10573 _bfd_error_handler
871b3ab2 10574 (_("%pB: relocation %s against external or undefined symbol `%s'"
52db4ec2
JW		 10575 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10576 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10577 return bfd_reloc_notsupported;
10578 }
10579
0945cdfd
DJ		 10580 *unresolved_reloc_p = FALSE;
10581
34e77a92 10582 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10583 {
83bac4b0
NC		 10584 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10585 ! globals->use_rel);
f21f3fe0 10586
83bac4b0 10587 if (sreloc == NULL)
252b5132 10588 return bfd_reloc_notsupported;
252b5132 10589 }
f21f3fe0 10590
b34976b6
AM		 10591 skip = FALSE;
10592 relocate = FALSE;
f21f3fe0 10593
00a97672 10594 outrel.r_addend = addend;
c629eae0
JJ		 10595 outrel.r_offset =
10596 _bfd_elf_section_offset (output_bfd, info, input_section,
10597 rel->r_offset);
10598 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10599 skip = TRUE;
0bb2d96a 10600 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10601 skip = TRUE, relocate = TRUE;
252b5132
RH		 10602 outrel.r_offset += (input_section->output_section->vma
10603 + input_section->output_offset);
f21f3fe0 10604
252b5132 10605 if (skip)
0bb2d96a 10606 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10607 else if (h != NULL
10608 && h->dynindx != -1
0e1862bb 10609 && (!bfd_link_pic (info)
1dcb9720
JW		 10610 || !(bfd_link_pie (info)
10611 || SYMBOLIC_BIND (info, h))
f5385ebf 10612 || !h->def_regular))
5e681ec4 10613 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10614 else
10615 {
a16385dc
MM		 10616 int symbol;
10617
5e681ec4 10618 /* This symbol is local, or marked to become local. */
e8b09b87
CL		 10619 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI
10620 || (globals->fdpic_p && !bfd_link_pic(info)));
a16385dc 10621 if (globals->symbian_p)
6366ff1e 10622 {
74541ad4
AM		 10623 asection *osec;
10624
6366ff1e
MM		 10625 /* On Symbian OS, the data segment and text segement
10626 can be relocated independently. Therefore, we
10627 must indicate the segment to which this
10628 relocation is relative. The BPABI allows us to
10629 use any symbol in the right segment; we just use
10630 the section symbol as it is convenient. (We
10631 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10632 will not appear in the dynamic symbol table.)
10633
10634 Note that the dynamic linker ignores the section
10635 symbol value, so we don't subtract osec->vma
10636 from the emitted reloc addend. */
10dbd1f3 10637 if (sym_sec)
74541ad4 10638 osec = sym_sec->output_section;
10dbd1f3 10639 else
74541ad4
AM		 10640 osec = input_section->output_section;
10641 symbol = elf_section_data (osec)->dynindx;
10642 if (symbol == 0)
10643 {
10644 struct elf_link_hash_table *htab = elf_hash_table (info);
10645
10646 if ((osec->flags & SEC_READONLY) == 0
10647 && htab->data_index_section != NULL)
10648 osec = htab->data_index_section;
10649 else
10650 osec = htab->text_index_section;
10651 symbol = elf_section_data (osec)->dynindx;
10652 }
6366ff1e
MM		 10653 BFD_ASSERT (symbol != 0);
10654 }
a16385dc
MM		 10655 else
10656 /* On SVR4-ish systems, the dynamic loader cannot
10657 relocate the text and data segments independently,
10658 so the symbol does not matter. */
10659 symbol = 0;
34e77a92
RS		 10660 if (dynreloc_st_type == STT_GNU_IFUNC)
10661 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10662 to the .iplt entry. Instead, every non-call reference
10663 must use an R_ARM_IRELATIVE relocation to obtain the
10664 correct run-time address. */
10665 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
e8b09b87
CL		 10666 else if (globals->fdpic_p && !bfd_link_pic(info))
10667 isrofixup = 1;
34e77a92
RS		 10668 else
10669 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10670 if (globals->use_rel)
10671 relocate = TRUE;
10672 else
34e77a92 10673 outrel.r_addend += dynreloc_value;
252b5132 10674 }
f21f3fe0 10675
e8b09b87
CL		 10676 if (isrofixup)
10677 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
10678 else
10679 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10680
f21f3fe0 10681 /* If this reloc is against an external symbol, we do not want to
252b5132 10682 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10683 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10684 if (! relocate)
10685 return bfd_reloc_ok;
9a5aca8c 10686
f21f3fe0 10687 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10688 contents, rel->r_offset,
10689 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10690 }
10691 else switch (r_type)
10692 {
00a97672
RS		 10693 case R_ARM_ABS12:
10694 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10695
dfc5f959 10696 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10697 case R_ARM_CALL:
10698 case R_ARM_JUMP24:
8029a119 10699 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10700 case R_ARM_PLT32:
906e58ca 10701 {
906e58ca
NC		 10702 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10703
dfc5f959 10704 if (r_type == R_ARM_XPC25)
252b5132 10705 {
dfc5f959
NC		 10706 /* Check for Arm calling Arm function. */
10707 /* FIXME: Should we translate the instruction into a BL
10708 instruction instead ? */
35fc36a8 10709 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10710 _bfd_error_handler
90b6238f
AM		 10711 (_("\%pB: warning: %s BLX instruction targets"
10712 " %s function '%s'"),
10713 input_bfd, "ARM",
10714 "ARM", h ? h->root.root.string : "(local)");
dfc5f959 10715 }
155d87d7 10716 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10717 {
10718 /* Check for Arm calling Thumb function. */
35fc36a8 10719 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10720 {
f2a9dd69
DJ		 10721 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10722 output_bfd, input_section,
10723 hit_data, sym_sec, rel->r_offset,
10724 signed_addend, value,
10725 error_message))
10726 return bfd_reloc_ok;
10727 else
10728 return bfd_reloc_dangerous;
dfc5f959 10729 }
252b5132 10730 }
ba96a88f 10731
906e58ca 10732 /* Check if a stub has to be inserted because the
8029a119 10733 destination is too far or we are changing mode. */
155d87d7
CL		 10734 if ( r_type == R_ARM_CALL
10735 || r_type == R_ARM_JUMP24
10736 || r_type == R_ARM_PLT32)
906e58ca 10737 {
fe33d2fa
CL		 10738 enum elf32_arm_stub_type stub_type = arm_stub_none;
10739 struct elf32_arm_link_hash_entry *hash;
10740
10741 hash = (struct elf32_arm_link_hash_entry *) h;
10742 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10743 st_type, &branch_type,
10744 hash, value, sym_sec,
fe33d2fa 10745 input_bfd, sym_name);
5fa9e92f 10746
fe33d2fa 10747 if (stub_type != arm_stub_none)
906e58ca
NC		 10748 {
10749 /* The target is out of reach, so redirect the
10750 branch to the local stub for this function. */
906e58ca
NC		 10751 stub_entry = elf32_arm_get_stub_entry (input_section,
10752 sym_sec, h,
fe33d2fa
CL		 10753 rel, globals,
10754 stub_type);
9cd3e4e5
NC		 10755 {
10756 if (stub_entry != NULL)
10757 value = (stub_entry->stub_offset
10758 + stub_entry->stub_sec->output_offset
10759 + stub_entry->stub_sec->output_section->vma);
10760
10761 if (plt_offset != (bfd_vma) -1)
10762 *unresolved_reloc_p = FALSE;
10763 }
906e58ca 10764 }
fe33d2fa
CL		 10765 else
10766 {
10767 /* If the call goes through a PLT entry, make sure to
10768 check distance to the right destination address. */
34e77a92 10769 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10770 {
10771 value = (splt->output_section->vma
10772 + splt->output_offset
34e77a92 10773 + plt_offset);
fe33d2fa
CL		 10774 *unresolved_reloc_p = FALSE;
10775 /* The PLT entry is in ARM mode, regardless of the
10776 target function. */
35fc36a8 10777 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10778 }
10779 }
906e58ca
NC		 10780 }
10781
dea514f5
PB		 10782 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10783 where:
10784 S is the address of the symbol in the relocation.
10785 P is address of the instruction being relocated.
10786 A is the addend (extracted from the instruction) in bytes.
10787
10788 S is held in 'value'.
10789 P is the base address of the section containing the
10790 instruction plus the offset of the reloc into that
10791 section, ie:
10792 (input_section->output_section->vma +
10793 input_section->output_offset +
10794 rel->r_offset).
10795 A is the addend, converted into bytes, ie:
10796 (signed_addend * 4)
10797
10798 Note: None of these operations have knowledge of the pipeline
10799 size of the processor, thus it is up to the assembler to
10800 encode this information into the addend. */
10801 value -= (input_section->output_section->vma
10802 + input_section->output_offset);
10803 value -= rel->r_offset;
4e7fd91e
PB		 10804 if (globals->use_rel)
10805 value += (signed_addend << howto->size);
10806 else
10807 /* RELA addends do not have to be adjusted by howto->size. */
10808 value += signed_addend;
23080146 10809
dcb5e6e6
NC		 10810 signed_addend = value;
10811 signed_addend >>= howto->rightshift;
9a5aca8c 10812
5ab79981 10813 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10814 the next instruction unless a PLT entry will be created.
77b4f08f 10815 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10816 The jump to the next instruction is optimized as a NOP depending
10817 on the architecture. */
ffcb4889 10818 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10819 && plt_offset == (bfd_vma) -1)
77b4f08f 10820 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10821 {
cd1dac3d
DG		 10822 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10823
10824 if (arch_has_arm_nop (globals))
10825 value |= 0x0320f000;
10826 else
10827 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10828 }
10829 else
59f2c4e7 10830 {
9b485d32 10831 /* Perform a signed range check. */
dcb5e6e6 10832 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10833 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10834 return bfd_reloc_overflow;
9a5aca8c 10835
5ab79981 10836 addend = (value & 2);
39b41c9c 10837
5ab79981
PB		 10838 value = (signed_addend & howto->dst_mask)
10839 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10840
5ab79981
PB		 10841 if (r_type == R_ARM_CALL)
10842 {
155d87d7 10843 /* Set the H bit in the BLX instruction. */
35fc36a8 10844 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10845 {
10846 if (addend)
10847 value |= (1 << 24);
10848 else
10849 value &= ~(bfd_vma)(1 << 24);
10850 }
10851
5ab79981 10852 /* Select the correct instruction (BL or BLX). */
906e58ca 10853 /* Only if we are not handling a BL to a stub. In this
8029a119 10854 case, mode switching is performed by the stub. */
35fc36a8 10855 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10856 value |= (1 << 28);
63e1a0fc 10857 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10858 {
10859 value &= ~(bfd_vma)(1 << 28);
10860 value |= (1 << 24);
10861 }
39b41c9c
PB		 10862 }
10863 }
906e58ca 10864 }
252b5132 10865 break;
f21f3fe0 10866
252b5132
RH		 10867 case R_ARM_ABS32:
10868 value += addend;
35fc36a8 10869 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10870 value |= 1;
10871 break;
f21f3fe0 10872
bb224fc3
MS		 10873 case R_ARM_ABS32_NOI:
10874 value += addend;
10875 break;
10876
252b5132 10877 case R_ARM_REL32:
a8bc6c78 10878 value += addend;
35fc36a8 10879 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10880 value |= 1;
252b5132 10881 value -= (input_section->output_section->vma
62efb346 10882 + input_section->output_offset + rel->r_offset);
252b5132 10883 break;
eb043451 10884
bb224fc3
MS		 10885 case R_ARM_REL32_NOI:
10886 value += addend;
10887 value -= (input_section->output_section->vma
10888 + input_section->output_offset + rel->r_offset);
10889 break;
10890
eb043451
PB		 10891 case R_ARM_PREL31:
10892 value -= (input_section->output_section->vma
10893 + input_section->output_offset + rel->r_offset);
10894 value += signed_addend;
10895 if (! h || h->root.type != bfd_link_hash_undefweak)
10896 {
8029a119 10897 /* Check for overflow. */
eb043451
PB		 10898 if ((value ^ (value >> 1)) & (1 << 30))
10899 return bfd_reloc_overflow;
10900 }
10901 value &= 0x7fffffff;
10902 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10903 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10904 value |= 1;
10905 break;
252b5132 10906 }
f21f3fe0 10907
252b5132
RH		 10908 bfd_put_32 (input_bfd, value, hit_data);
10909 return bfd_reloc_ok;
10910
10911 case R_ARM_ABS8:
fd0fd00c
MJ		 10912 /* PR 16202: Refectch the addend using the correct size. */
10913 if (globals->use_rel)
10914 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10915 value += addend;
4e67d4ca
DG		 10916
10917 /* There is no way to tell whether the user intended to use a signed or
10918 unsigned addend. When checking for overflow we accept either,
10919 as specified by the AAELF. */
10920 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10921 return bfd_reloc_overflow;
10922
10923 bfd_put_8 (input_bfd, value, hit_data);
10924 return bfd_reloc_ok;
10925
10926 case R_ARM_ABS16:
fd0fd00c
MJ		 10927 /* PR 16202: Refectch the addend using the correct size. */
10928 if (globals->use_rel)
10929 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10930 value += addend;
10931
4e67d4ca
DG		 10932 /* See comment for R_ARM_ABS8. */
10933 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10934 return bfd_reloc_overflow;
10935
10936 bfd_put_16 (input_bfd, value, hit_data);
10937 return bfd_reloc_ok;
10938
252b5132 10939 case R_ARM_THM_ABS5:
9b485d32 10940 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10941 if (globals->use_rel)
10942 {
10943 /* Need to refetch addend. */
10944 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10945 /* ??? Need to determine shift amount from operand size. */
10946 addend >>= howto->rightshift;
10947 }
252b5132
RH		 10948 value += addend;
10949
10950 /* ??? Isn't value unsigned? */
10951 if ((long) value > 0x1f || (long) value < -0x10)
10952 return bfd_reloc_overflow;
10953
10954 /* ??? Value needs to be properly shifted into place first. */
10955 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10956 bfd_put_16 (input_bfd, value, hit_data);
10957 return bfd_reloc_ok;
10958
2cab6cc3
MS		 10959 case R_ARM_THM_ALU_PREL_11_0:
10960 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10961 {
10962 bfd_vma insn;
10963 bfd_signed_vma relocation;
10964
10965 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10966 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10967
99059e56
RM		 10968 if (globals->use_rel)
10969 {
10970 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10971 | ((insn & (1 << 26)) >> 15);
10972 if (insn & 0xf00000)
10973 signed_addend = -signed_addend;
10974 }
2cab6cc3
MS		 10975
10976 relocation = value + signed_addend;
79f08007 10977 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10978 + input_section->output_offset
10979 + rel->r_offset);
2cab6cc3 10980
8c65b54f
CS		 10981 /* PR 21523: Use an absolute value. The user of this reloc will
10982 have already selected an ADD or SUB insn appropriately. */
453f8e1e 10983 value = llabs (relocation);
2cab6cc3 10984
99059e56
RM		 10985 if (value >= 0x1000)
10986 return bfd_reloc_overflow;
2cab6cc3 10987
e645cf40
AG		 10988 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10989 if (branch_type == ST_BRANCH_TO_THUMB)
10990 value |= 1;
10991
2cab6cc3 10992 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10993 | ((value & 0x700) << 4)
10994 | ((value & 0x800) << 15);
10995 if (relocation < 0)
10996 insn |= 0xa00000;
2cab6cc3
MS		 10997
10998 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10999 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11000
99059e56 11001 return bfd_reloc_ok;
2cab6cc3
MS		 11002 }
11003
e1ec24c6
NC		 11004 case R_ARM_THM_PC8:
11005 /* PR 10073: This reloc is not generated by the GNU toolchain,
11006 but it is supported for compatibility with third party libraries
11007 generated by other compilers, specifically the ARM/IAR. */
11008 {
11009 bfd_vma insn;
11010 bfd_signed_vma relocation;
11011
11012 insn = bfd_get_16 (input_bfd, hit_data);
11013
99059e56 11014 if (globals->use_rel)
79f08007 11015 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 11016
11017 relocation = value + addend;
79f08007 11018 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11019 + input_section->output_offset
11020 + rel->r_offset);
e1ec24c6 11021
b6518b38 11022 value = relocation;
e1ec24c6
NC		 11023
11024 /* We do not check for overflow of this reloc. Although strictly
11025 speaking this is incorrect, it appears to be necessary in order
11026 to work with IAR generated relocs. Since GCC and GAS do not
11027 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
11028 a problem for them. */
11029 value &= 0x3fc;
11030
11031 insn = (insn & 0xff00) | (value >> 2);
11032
11033 bfd_put_16 (input_bfd, insn, hit_data);
11034
99059e56 11035 return bfd_reloc_ok;
e1ec24c6
NC		 11036 }
11037
2cab6cc3
MS		 11038 case R_ARM_THM_PC12:
11039 /* Corresponds to: ldr.w reg, [pc, #offset]. */
11040 {
11041 bfd_vma insn;
11042 bfd_signed_vma relocation;
11043
11044 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 11045 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 11046
99059e56
RM		 11047 if (globals->use_rel)
11048 {
11049 signed_addend = insn & 0xfff;
11050 if (!(insn & (1 << 23)))
11051 signed_addend = -signed_addend;
11052 }
2cab6cc3
MS		 11053
11054 relocation = value + signed_addend;
79f08007 11055 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11056 + input_section->output_offset
11057 + rel->r_offset);
2cab6cc3 11058
b6518b38 11059 value = relocation;
2cab6cc3 11060
99059e56
RM		 11061 if (value >= 0x1000)
11062 return bfd_reloc_overflow;
2cab6cc3
MS		 11063
11064 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 11065 if (relocation >= 0)
11066 insn |= (1 << 23);
2cab6cc3
MS		 11067
11068 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11069 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11070
99059e56 11071 return bfd_reloc_ok;
2cab6cc3
MS		 11072 }
11073
dfc5f959 11074 case R_ARM_THM_XPC22:
c19d1205 11075 case R_ARM_THM_CALL:
bd97cb95 11076 case R_ARM_THM_JUMP24:
dfc5f959 11077 /* Thumb BL (branch long instruction). */
252b5132 11078 {
b34976b6 11079 bfd_vma relocation;
99059e56 11080 bfd_vma reloc_sign;
b34976b6
AM		 11081 bfd_boolean overflow = FALSE;
11082 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11083 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 11084 bfd_signed_vma reloc_signed_max;
11085 bfd_signed_vma reloc_signed_min;
b34976b6 11086 bfd_vma check;
252b5132 11087 bfd_signed_vma signed_check;
e95de063 11088 int bitsize;
cd1dac3d 11089 const int thumb2 = using_thumb2 (globals);
5e866f5a 11090 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 11091
5ab79981 11092 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 11093 the next instruction unless a PLT entry will be created.
11094 The jump to the next instruction is optimized as a NOP.W for
11095 Thumb-2 enabled architectures. */
19540007 11096 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 11097 && plt_offset == (bfd_vma) -1)
5ab79981 11098 {
60a019a0 11099 if (thumb2)
cd1dac3d
DG		 11100 {
11101 bfd_put_16 (input_bfd, 0xf3af, hit_data);
11102 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
11103 }
11104 else
11105 {
11106 bfd_put_16 (input_bfd, 0xe000, hit_data);
11107 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
11108 }
5ab79981
PB		 11109 return bfd_reloc_ok;
11110 }
11111
e95de063 11112 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 11113 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 11114 if (globals->use_rel)
11115 {
99059e56
RM		 11116 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
11117 bfd_vma upper = upper_insn & 0x3ff;
11118 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 11119 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
11120 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 11121 bfd_vma i1 = j1 ^ s ? 0 : 1;
11122 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 11123
99059e56
RM		 11124 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
11125 /* Sign extend. */
11126 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 11127
4e7fd91e
PB		 11128 signed_addend = addend;
11129 }
cb1afa5c 11130
dfc5f959
NC		 11131 if (r_type == R_ARM_THM_XPC22)
11132 {
11133 /* Check for Thumb to Thumb call. */
11134 /* FIXME: Should we translate the instruction into a BL
11135 instruction instead ? */
35fc36a8 11136 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 11137 _bfd_error_handler
90b6238f
AM		 11138 (_("%pB: warning: %s BLX instruction targets"
11139 " %s function '%s'"),
11140 input_bfd, "Thumb",
11141 "Thumb", h ? h->root.root.string : "(local)");
dfc5f959
NC		 11142 }
11143 else
252b5132 11144 {
dfc5f959
NC		 11145 /* If it is not a call to Thumb, assume call to Arm.
11146 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 11147 function call at all, but rather a long jump. Calls through
11148 the PLT do not require stubs. */
34e77a92 11149 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 11150 {
bd97cb95 11151 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11152 {
11153 /* Convert BL to BLX. */
11154 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11155 }
155d87d7
CL		 11156 else if (( r_type != R_ARM_THM_CALL)
11157 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 11158 {
11159 if (elf32_thumb_to_arm_stub
11160 (info, sym_name, input_bfd, output_bfd, input_section,
11161 hit_data, sym_sec, rel->r_offset, signed_addend, value,
11162 error_message))
11163 return bfd_reloc_ok;
11164 else
11165 return bfd_reloc_dangerous;
11166 }
da5938a2 11167 }
35fc36a8
RS		 11168 else if (branch_type == ST_BRANCH_TO_THUMB
11169 && globals->use_blx
bd97cb95 11170 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11171 {
11172 /* Make sure this is a BL. */
11173 lower_insn |= 0x1800;
11174 }
252b5132 11175 }
f21f3fe0 11176
fe33d2fa 11177 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 11178 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 11179 {
11180 /* Check if a stub has to be inserted because the destination
8029a119 11181 is too far. */
fe33d2fa
CL		 11182 struct elf32_arm_stub_hash_entry *stub_entry;
11183 struct elf32_arm_link_hash_entry *hash;
11184
11185 hash = (struct elf32_arm_link_hash_entry *) h;
11186
11187 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 11188 st_type, &branch_type,
11189 hash, value, sym_sec,
fe33d2fa
CL		 11190 input_bfd, sym_name);
11191
11192 if (stub_type != arm_stub_none)
906e58ca
NC		 11193 {
11194 /* The target is out of reach or we are changing modes, so
11195 redirect the branch to the local stub for this
11196 function. */
11197 stub_entry = elf32_arm_get_stub_entry (input_section,
11198 sym_sec, h,
fe33d2fa
CL		 11199 rel, globals,
11200 stub_type);
906e58ca 11201 if (stub_entry != NULL)
9cd3e4e5
NC		 11202 {
11203 value = (stub_entry->stub_offset
11204 + stub_entry->stub_sec->output_offset
11205 + stub_entry->stub_sec->output_section->vma);
11206
11207 if (plt_offset != (bfd_vma) -1)
11208 *unresolved_reloc_p = FALSE;
11209 }
906e58ca 11210
f4ac8484 11211 /* If this call becomes a call to Arm, force BLX. */
155d87d7 11212 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 11213 {
11214 if ((stub_entry
11215 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 11216 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 11217 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11218 }
906e58ca
NC		 11219 }
11220 }
11221
fe33d2fa 11222 /* Handle calls via the PLT. */
34e77a92 11223 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 11224 {
11225 value = (splt->output_section->vma
11226 + splt->output_offset
34e77a92 11227 + plt_offset);
fe33d2fa 11228
eed94f8f
NC		 11229 if (globals->use_blx
11230 && r_type == R_ARM_THM_CALL
11231 && ! using_thumb_only (globals))
fe33d2fa
CL		 11232 {
11233 /* If the Thumb BLX instruction is available, convert
11234 the BL to a BLX instruction to call the ARM-mode
11235 PLT entry. */
11236 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 11237 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 11238 }
11239 else
11240 {
eed94f8f
NC		 11241 if (! using_thumb_only (globals))
11242 /* Target the Thumb stub before the ARM PLT entry. */
11243 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 11244 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 11245 }
11246 *unresolved_reloc_p = FALSE;
11247 }
11248
ba96a88f 11249 relocation = value + signed_addend;
f21f3fe0 11250
252b5132 11251 relocation -= (input_section->output_section->vma
ba96a88f
NC		 11252 + input_section->output_offset
11253 + rel->r_offset);
9a5aca8c 11254
252b5132
RH		 11255 check = relocation >> howto->rightshift;
11256
11257 /* If this is a signed value, the rightshift just dropped
11258 leading 1 bits (assuming twos complement). */
11259 if ((bfd_signed_vma) relocation >= 0)
11260 signed_check = check;
11261 else
11262 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
11263
e95de063
MS		 11264 /* Calculate the permissable maximum and minimum values for
11265 this relocation according to whether we're relocating for
11266 Thumb-2 or not. */
11267 bitsize = howto->bitsize;
5e866f5a 11268 if (!thumb2_bl)
e95de063 11269 bitsize -= 2;
f6ebfac0 11270 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 11271 reloc_signed_min = ~reloc_signed_max;
11272
252b5132 11273 /* Assumes two's complement. */
ba96a88f 11274 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 11275 overflow = TRUE;
252b5132 11276
bd97cb95 11277 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 11278 /* For a BLX instruction, make sure that the relocation is rounded up
11279 to a word boundary. This follows the semantics of the instruction
11280 which specifies that bit 1 of the target address will come from bit
11281 1 of the base address. */
11282 relocation = (relocation + 2) & ~ 3;
cb1afa5c 11283
e95de063
MS		 11284 /* Put RELOCATION back into the insn. Assumes two's complement.
11285 We use the Thumb-2 encoding, which is safe even if dealing with
11286 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 11287 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 11288 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 11289 | ((relocation >> 12) & 0x3ff)
11290 | (reloc_sign << 10);
906e58ca 11291 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 11292 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
11293 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
11294 | ((relocation >> 1) & 0x7ff);
c62e1cc3 11295
252b5132
RH		 11296 /* Put the relocated value back in the object file: */
11297 bfd_put_16 (input_bfd, upper_insn, hit_data);
11298 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11299
11300 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11301 }
11302 break;
11303
c19d1205
ZW		 11304 case R_ARM_THM_JUMP19:
11305 /* Thumb32 conditional branch instruction. */
11306 {
11307 bfd_vma relocation;
11308 bfd_boolean overflow = FALSE;
11309 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11310 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 11311 bfd_signed_vma reloc_signed_max = 0xffffe;
11312 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 11313 bfd_signed_vma signed_check;
07d6d2b8 11314 enum elf32_arm_stub_type stub_type = arm_stub_none;
c5423981
TG		 11315 struct elf32_arm_stub_hash_entry *stub_entry;
11316 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 11317
11318 /* Need to refetch the addend, reconstruct the top three bits,
11319 and squish the two 11 bit pieces together. */
11320 if (globals->use_rel)
11321 {
11322 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 11323 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 11324 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
11325 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
11326 bfd_vma lower = (lower_insn & 0x07ff);
11327
a00a1f35
MS		 11328 upper |= J1 << 6;
11329 upper |= J2 << 7;
11330 upper |= (!S) << 8;
c19d1205
ZW		 11331 upper -= 0x0100; /* Sign extend. */
11332
11333 addend = (upper << 12) | (lower << 1);
11334 signed_addend = addend;
11335 }
11336
bd97cb95 11337 /* Handle calls via the PLT. */
34e77a92 11338 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 11339 {
11340 value = (splt->output_section->vma
11341 + splt->output_offset
34e77a92 11342 + plt_offset);
bd97cb95
DJ		 11343 /* Target the Thumb stub before the ARM PLT entry. */
11344 value -= PLT_THUMB_STUB_SIZE;
11345 *unresolved_reloc_p = FALSE;
11346 }
11347
c5423981
TG		 11348 hash = (struct elf32_arm_link_hash_entry *)h;
11349
11350 stub_type = arm_type_of_stub (info, input_section, rel,
07d6d2b8
AM		 11351 st_type, &branch_type,
11352 hash, value, sym_sec,
11353 input_bfd, sym_name);
c5423981
TG		 11354 if (stub_type != arm_stub_none)
11355 {
11356 stub_entry = elf32_arm_get_stub_entry (input_section,
07d6d2b8
AM		 11357 sym_sec, h,
11358 rel, globals,
11359 stub_type);
c5423981
TG		 11360 if (stub_entry != NULL)
11361 {
07d6d2b8
AM		 11362 value = (stub_entry->stub_offset
11363 + stub_entry->stub_sec->output_offset
11364 + stub_entry->stub_sec->output_section->vma);
c5423981
TG		 11365 }
11366 }
c19d1205 11367
99059e56 11368 relocation = value + signed_addend;
c19d1205
ZW		 11369 relocation -= (input_section->output_section->vma
11370 + input_section->output_offset
11371 + rel->r_offset);
a00a1f35 11372 signed_check = (bfd_signed_vma) relocation;
c19d1205 11373
c19d1205
ZW		 11374 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11375 overflow = TRUE;
11376
11377 /* Put RELOCATION back into the insn. */
11378 {
11379 bfd_vma S = (relocation & 0x00100000) >> 20;
11380 bfd_vma J2 = (relocation & 0x00080000) >> 19;
11381 bfd_vma J1 = (relocation & 0x00040000) >> 18;
11382 bfd_vma hi = (relocation & 0x0003f000) >> 12;
11383 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
11384
a00a1f35 11385 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 11386 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
11387 }
11388
11389 /* Put the relocated value back in the object file: */
11390 bfd_put_16 (input_bfd, upper_insn, hit_data);
11391 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11392
11393 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11394 }
11395
11396 case R_ARM_THM_JUMP11:
11397 case R_ARM_THM_JUMP8:
11398 case R_ARM_THM_JUMP6:
51c5503b
NC		 11399 /* Thumb B (branch) instruction). */
11400 {
6cf9e9fe 11401 bfd_signed_vma relocation;
51c5503b
NC		 11402 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
11403 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 11404 bfd_signed_vma signed_check;
11405
c19d1205
ZW		 11406 /* CZB cannot jump backward. */
11407 if (r_type == R_ARM_THM_JUMP6)
11408 reloc_signed_min = 0;
11409
4e7fd91e 11410 if (globals->use_rel)
6cf9e9fe 11411 {
4e7fd91e
PB		 11412 /* Need to refetch addend. */
11413 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
11414 if (addend & ((howto->src_mask + 1) >> 1))
11415 {
11416 signed_addend = -1;
11417 signed_addend &= ~ howto->src_mask;
11418 signed_addend |= addend;
11419 }
11420 else
11421 signed_addend = addend;
11422 /* The value in the insn has been right shifted. We need to
11423 undo this, so that we can perform the address calculation
11424 in terms of bytes. */
11425 signed_addend <<= howto->rightshift;
6cf9e9fe 11426 }
6cf9e9fe 11427 relocation = value + signed_addend;
51c5503b
NC		 11428
11429 relocation -= (input_section->output_section->vma
11430 + input_section->output_offset
11431 + rel->r_offset);
11432
6cf9e9fe
NC		 11433 relocation >>= howto->rightshift;
11434 signed_check = relocation;
c19d1205
ZW		 11435
11436 if (r_type == R_ARM_THM_JUMP6)
11437 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
11438 else
11439 relocation &= howto->dst_mask;
51c5503b 11440 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 11441
51c5503b
NC		 11442 bfd_put_16 (input_bfd, relocation, hit_data);
11443
11444 /* Assumes two's complement. */
11445 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11446 return bfd_reloc_overflow;
11447
11448 return bfd_reloc_ok;
11449 }
cedb70c5 11450
8375c36b
PB		 11451 case R_ARM_ALU_PCREL7_0:
11452 case R_ARM_ALU_PCREL15_8:
11453 case R_ARM_ALU_PCREL23_15:
11454 {
11455 bfd_vma insn;
11456 bfd_vma relocation;
11457
11458 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 11459 if (globals->use_rel)
11460 {
11461 /* Extract the addend. */
11462 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
11463 signed_addend = addend;
11464 }
8375c36b
PB		 11465 relocation = value + signed_addend;
11466
11467 relocation -= (input_section->output_section->vma
11468 + input_section->output_offset
11469 + rel->r_offset);
11470 insn = (insn & ~0xfff)
11471 | ((howto->bitpos << 7) & 0xf00)
11472 | ((relocation >> howto->bitpos) & 0xff);
11473 bfd_put_32 (input_bfd, value, hit_data);
11474 }
11475 return bfd_reloc_ok;
11476
252b5132
RH		 11477 case R_ARM_GNU_VTINHERIT:
11478 case R_ARM_GNU_VTENTRY:
11479 return bfd_reloc_ok;
11480
c19d1205 11481 case R_ARM_GOTOFF32:
252b5132 11482 /* Relocation is relative to the start of the
99059e56 11483 global offset table. */
252b5132
RH		 11484
11485 BFD_ASSERT (sgot != NULL);
11486 if (sgot == NULL)
99059e56 11487 return bfd_reloc_notsupported;
9a5aca8c 11488
cedb70c5 11489 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11490 address by one, so that attempts to call the function pointer will
11491 correctly interpret it as Thumb code. */
35fc36a8 11492 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11493 value += 1;
11494
252b5132 11495 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11496 calculation. We always want the start of .got. If we
11497 define _GLOBAL_OFFSET_TABLE in a different way, as is
11498 permitted by the ABI, we might have to change this
11499 calculation. */
252b5132 11500 value -= sgot->output_section->vma;
f21f3fe0 11501 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11502 contents, rel->r_offset, value,
00a97672 11503 rel->r_addend);
252b5132
RH		 11504
11505 case R_ARM_GOTPC:
a7c10850 11506 /* Use global offset table as symbol value. */
252b5132 11507 BFD_ASSERT (sgot != NULL);
f21f3fe0 11508
252b5132 11509 if (sgot == NULL)
99059e56 11510 return bfd_reloc_notsupported;
252b5132 11511
0945cdfd 11512 *unresolved_reloc_p = FALSE;
252b5132 11513 value = sgot->output_section->vma;
f21f3fe0 11514 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11515 contents, rel->r_offset, value,
00a97672 11516 rel->r_addend);
f21f3fe0 11517
252b5132 11518 case R_ARM_GOT32:
eb043451 11519 case R_ARM_GOT_PREL:
252b5132 11520 /* Relocation is to the entry for this symbol in the
99059e56 11521 global offset table. */
252b5132
RH		 11522 if (sgot == NULL)
11523 return bfd_reloc_notsupported;
f21f3fe0 11524
34e77a92
RS		 11525 if (dynreloc_st_type == STT_GNU_IFUNC
11526 && plt_offset != (bfd_vma) -1
11527 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11528 {
11529 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11530 symbol, and the relocation resolves directly to the runtime
11531 target rather than to the .iplt entry. This means that any
11532 .got entry would be the same value as the .igot.plt entry,
11533 so there's no point creating both. */
11534 sgot = globals->root.igotplt;
11535 value = sgot->output_offset + gotplt_offset;
11536 }
11537 else if (h != NULL)
252b5132
RH		 11538 {
11539 bfd_vma off;
f21f3fe0 11540
252b5132
RH		 11541 off = h->got.offset;
11542 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11543 if ((off & 1) != 0)
252b5132 11544 {
b436d854
RS		 11545 /* We have already processsed one GOT relocation against
11546 this symbol. */
11547 off &= ~1;
11548 if (globals->root.dynamic_sections_created
11549 && !SYMBOL_REFERENCES_LOCAL (info, h))
11550 *unresolved_reloc_p = FALSE;
11551 }
11552 else
11553 {
11554 Elf_Internal_Rela outrel;
e8b09b87 11555 int isrofixup = 0;
b436d854 11556
e8b09b87
CL		 11557 if (((h->dynindx != -1) || globals->fdpic_p)
11558 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11559 {
11560 /* If the symbol doesn't resolve locally in a static
11561 object, we have an undefined reference. If the
11562 symbol doesn't resolve locally in a dynamic object,
11563 it should be resolved by the dynamic linker. */
11564 if (globals->root.dynamic_sections_created)
11565 {
11566 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11567 *unresolved_reloc_p = FALSE;
11568 }
11569 else
11570 outrel.r_info = 0;
11571 outrel.r_addend = 0;
11572 }
252b5132
RH		 11573 else
11574 {
34e77a92 11575 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11576 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c
AO		 11577 else if (bfd_link_pic (info)
11578 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11579 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 11580 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11581 else
2376f038
EB		 11582 {
11583 outrel.r_info = 0;
11584 if (globals->fdpic_p)
11585 isrofixup = 1;
11586 }
34e77a92 11587 outrel.r_addend = dynreloc_value;
b436d854 11588 }
ee29b9fb 11589
b436d854
RS		 11590 /* The GOT entry is initialized to zero by default.
11591 See if we should install a different value. */
11592 if (outrel.r_addend != 0
2376f038 11593 && (globals->use_rel || outrel.r_info == 0))
b436d854
RS		 11594 {
11595 bfd_put_32 (output_bfd, outrel.r_addend,
11596 sgot->contents + off);
11597 outrel.r_addend = 0;
252b5132 11598 }
f21f3fe0 11599
2376f038
EB		 11600 if (isrofixup)
11601 arm_elf_add_rofixup (output_bfd,
11602 elf32_arm_hash_table(info)->srofixup,
11603 sgot->output_section->vma
11604 + sgot->output_offset + off);
11605
11606 else if (outrel.r_info != 0)
b436d854
RS		 11607 {
11608 outrel.r_offset = (sgot->output_section->vma
11609 + sgot->output_offset
11610 + off);
11611 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11612 }
2376f038 11613
b436d854
RS		 11614 h->got.offset |= 1;
11615 }
252b5132
RH		 11616 value = sgot->output_offset + off;
11617 }
11618 else
11619 {
11620 bfd_vma off;
f21f3fe0 11621
5025eb7c
AO		 11622 BFD_ASSERT (local_got_offsets != NULL
11623 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11624
252b5132 11625 off = local_got_offsets[r_symndx];
f21f3fe0 11626
252b5132
RH		 11627 /* The offset must always be a multiple of 4. We use the
11628 least significant bit to record whether we have already
9b485d32 11629 generated the necessary reloc. */
252b5132
RH		 11630 if ((off & 1) != 0)
11631 off &= ~1;
11632 else
11633 {
2376f038
EB		 11634 Elf_Internal_Rela outrel;
11635 int isrofixup = 0;
f21f3fe0 11636
2376f038
EB		 11637 if (dynreloc_st_type == STT_GNU_IFUNC)
11638 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
11639 else if (bfd_link_pic (info))
11640 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11641 else
252b5132 11642 {
2376f038
EB		 11643 outrel.r_info = 0;
11644 if (globals->fdpic_p)
11645 isrofixup = 1;
11646 }
11647
11648 /* The GOT entry is initialized to zero by default.
11649 See if we should install a different value. */
11650 if (globals->use_rel || outrel.r_info == 0)
11651 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
11652
11653 if (isrofixup)
11654 arm_elf_add_rofixup (output_bfd,
11655 globals->srofixup,
11656 sgot->output_section->vma
11657 + sgot->output_offset + off);
f21f3fe0 11658
2376f038
EB		 11659 else if (outrel.r_info != 0)
11660 {
34e77a92 11661 outrel.r_addend = addend + dynreloc_value;
252b5132 11662 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11663 + sgot->output_offset
252b5132 11664 + off);
47beaa6a 11665 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11666 }
f21f3fe0 11667
252b5132
RH		 11668 local_got_offsets[r_symndx] |= 1;
11669 }
f21f3fe0 11670
252b5132
RH		 11671 value = sgot->output_offset + off;
11672 }
eb043451
PB		 11673 if (r_type != R_ARM_GOT32)
11674 value += sgot->output_section->vma;
9a5aca8c 11675
f21f3fe0 11676 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11677 contents, rel->r_offset, value,
00a97672 11678 rel->r_addend);
f21f3fe0 11679
ba93b8ac
DJ		 11680 case R_ARM_TLS_LDO32:
11681 value = value - dtpoff_base (info);
11682
11683 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11684 contents, rel->r_offset, value,
11685 rel->r_addend);
ba93b8ac
DJ		 11686
11687 case R_ARM_TLS_LDM32:
5c5a4843 11688 case R_ARM_TLS_LDM32_FDPIC:
ba93b8ac
DJ		 11689 {
11690 bfd_vma off;
11691
362d30a1 11692 if (sgot == NULL)
ba93b8ac
DJ		 11693 abort ();
11694
11695 off = globals->tls_ldm_got.offset;
11696
11697 if ((off & 1) != 0)
11698 off &= ~1;
11699 else
11700 {
11701 /* If we don't know the module number, create a relocation
11702 for it. */
9cb09e33 11703 if (bfd_link_dll (info))
ba93b8ac
DJ		 11704 {
11705 Elf_Internal_Rela outrel;
ba93b8ac 11706
362d30a1 11707 if (srelgot == NULL)
ba93b8ac
DJ		 11708 abort ();
11709
00a97672 11710 outrel.r_addend = 0;
362d30a1
RS		 11711 outrel.r_offset = (sgot->output_section->vma
11712 + sgot->output_offset + off);
ba93b8ac
DJ		 11713 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11714
00a97672
RS		 11715 if (globals->use_rel)
11716 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11717 sgot->contents + off);
ba93b8ac 11718
47beaa6a 11719 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11720 }
11721 else
362d30a1 11722 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11723
11724 globals->tls_ldm_got.offset |= 1;
11725 }
11726
5c5a4843 11727 if (r_type == R_ARM_TLS_LDM32_FDPIC)
e8b09b87
CL		 11728 {
11729 bfd_put_32(output_bfd,
11730 globals->root.sgot->output_offset + off,
11731 contents + rel->r_offset);
11732
11733 return bfd_reloc_ok;
11734 }
11735 else
11736 {
11737 value = sgot->output_section->vma + sgot->output_offset + off
11738 - (input_section->output_section->vma
11739 + input_section->output_offset + rel->r_offset);
ba93b8ac 11740
e8b09b87
CL		 11741 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11742 contents, rel->r_offset, value,
11743 rel->r_addend);
11744 }
ba93b8ac
DJ		 11745 }
11746
0855e32b
NS		 11747 case R_ARM_TLS_CALL:
11748 case R_ARM_THM_TLS_CALL:
ba93b8ac 11749 case R_ARM_TLS_GD32:
5c5a4843 11750 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 11751 case R_ARM_TLS_IE32:
5c5a4843 11752 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 11753 case R_ARM_TLS_GOTDESC:
11754 case R_ARM_TLS_DESCSEQ:
11755 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11756 {
0855e32b
NS		 11757 bfd_vma off, offplt;
11758 int indx = 0;
ba93b8ac
DJ		 11759 char tls_type;
11760
0855e32b 11761 BFD_ASSERT (sgot != NULL);
ba93b8ac 11762
ba93b8ac
DJ		 11763 if (h != NULL)
11764 {
11765 bfd_boolean dyn;
11766 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11767 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11768 bfd_link_pic (info),
11769 h)
11770 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11771 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11772 {
11773 *unresolved_reloc_p = FALSE;
11774 indx = h->dynindx;
11775 }
11776 off = h->got.offset;
0855e32b 11777 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11778 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11779 }
11780 else
11781 {
0855e32b 11782 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11783 off = local_got_offsets[r_symndx];
0855e32b 11784 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11785 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11786 }
11787
0855e32b 11788 /* Linker relaxations happens from one of the
b38cadfb 11789 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11790 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11791 tls_type = GOT_TLS_IE;
0855e32b
NS		 11792
11793 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11794
11795 if ((off & 1) != 0)
11796 off &= ~1;
11797 else
11798 {
11799 bfd_boolean need_relocs = FALSE;
11800 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11801 int cur_off = off;
11802
11803 /* The GOT entries have not been initialized yet. Do it
11804 now, and emit any relocations. If both an IE GOT and a
11805 GD GOT are necessary, we emit the GD first. */
11806
9cb09e33 11807 if ((bfd_link_dll (info) || indx != 0)
ba93b8ac 11808 && (h == NULL
95b03e4a
L		 11809 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11810 && !resolved_to_zero)
ba93b8ac
DJ		 11811 || h->root.type != bfd_link_hash_undefweak))
11812 {
11813 need_relocs = TRUE;
0855e32b 11814 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11815 }
11816
0855e32b
NS		 11817 if (tls_type & GOT_TLS_GDESC)
11818 {
47beaa6a
RS		 11819 bfd_byte *loc;
11820
0855e32b
NS		 11821 /* We should have relaxed, unless this is an undefined
11822 weak symbol. */
11823 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
9cb09e33 11824 || bfd_link_dll (info));
0855e32b 11825 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11826 <= globals->root.sgotplt->size);
0855e32b
NS		 11827
11828 outrel.r_addend = 0;
11829 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11830 + globals->root.sgotplt->output_offset
11831 + offplt
11832 + globals->sgotplt_jump_table_size);
b38cadfb 11833
0855e32b
NS		 11834 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11835 sreloc = globals->root.srelplt;
11836 loc = sreloc->contents;
11837 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11838 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11839 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11840
11841 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11842
11843 /* For globals, the first word in the relocation gets
11844 the relocation index and the top bit set, or zero,
11845 if we're binding now. For locals, it gets the
11846 symbol's offset in the tls section. */
99059e56 11847 bfd_put_32 (output_bfd,
0855e32b
NS		 11848 !h ? value - elf_hash_table (info)->tls_sec->vma
11849 : info->flags & DF_BIND_NOW ? 0
11850 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11851 globals->root.sgotplt->contents + offplt
11852 + globals->sgotplt_jump_table_size);
11853
0855e32b 11854 /* Second word in the relocation is always zero. */
99059e56 11855 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11856 globals->root.sgotplt->contents + offplt
11857 + globals->sgotplt_jump_table_size + 4);
0855e32b 11858 }
ba93b8ac
DJ		 11859 if (tls_type & GOT_TLS_GD)
11860 {
11861 if (need_relocs)
11862 {
00a97672 11863 outrel.r_addend = 0;
362d30a1
RS		 11864 outrel.r_offset = (sgot->output_section->vma
11865 + sgot->output_offset
00a97672 11866 + cur_off);
ba93b8ac 11867 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11868
00a97672
RS		 11869 if (globals->use_rel)
11870 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11871 sgot->contents + cur_off);
00a97672 11872
47beaa6a 11873 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11874
11875 if (indx == 0)
11876 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11877 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11878 else
11879 {
00a97672 11880 outrel.r_addend = 0;
ba93b8ac
DJ		 11881 outrel.r_info = ELF32_R_INFO (indx,
11882 R_ARM_TLS_DTPOFF32);
11883 outrel.r_offset += 4;
00a97672
RS		 11884
11885 if (globals->use_rel)
11886 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11887 sgot->contents + cur_off + 4);
00a97672 11888
47beaa6a
RS		 11889 elf32_arm_add_dynreloc (output_bfd, info,
11890 srelgot, &outrel);
ba93b8ac
DJ		 11891 }
11892 }
11893 else
11894 {
11895 /* If we are not emitting relocations for a
11896 general dynamic reference, then we must be in a
11897 static link or an executable link with the
11898 symbol binding locally. Mark it as belonging
11899 to module 1, the executable. */
11900 bfd_put_32 (output_bfd, 1,
362d30a1 11901 sgot->contents + cur_off);
ba93b8ac 11902 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11903 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11904 }
11905
11906 cur_off += 8;
11907 }
11908
11909 if (tls_type & GOT_TLS_IE)
11910 {
11911 if (need_relocs)
11912 {
00a97672
RS		 11913 if (indx == 0)
11914 outrel.r_addend = value - dtpoff_base (info);
11915 else
11916 outrel.r_addend = 0;
362d30a1
RS		 11917 outrel.r_offset = (sgot->output_section->vma
11918 + sgot->output_offset
ba93b8ac
DJ		 11919 + cur_off);
11920 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11921
00a97672
RS		 11922 if (globals->use_rel)
11923 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11924 sgot->contents + cur_off);
ba93b8ac 11925
47beaa6a 11926 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11927 }
11928 else
11929 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11930 sgot->contents + cur_off);
ba93b8ac
DJ		 11931 cur_off += 4;
11932 }
11933
11934 if (h != NULL)
11935 h->got.offset |= 1;
11936 else
11937 local_got_offsets[r_symndx] |= 1;
11938 }
11939
5c5a4843 11940 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32 && r_type != R_ARM_TLS_GD32_FDPIC)
ba93b8ac 11941 off += 8;
0855e32b
NS		 11942 else if (tls_type & GOT_TLS_GDESC)
11943 off = offplt;
11944
11945 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11946 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11947 {
11948 bfd_signed_vma offset;
12352d3f
PB		 11949 /* TLS stubs are arm mode. The original symbol is a
11950 data object, so branch_type is bogus. */
11951 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11952 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11953 = arm_type_of_stub (info, input_section, rel,
11954 st_type, &branch_type,
0855e32b
NS		 11955 (struct elf32_arm_link_hash_entry *)h,
11956 globals->tls_trampoline, globals->root.splt,
11957 input_bfd, sym_name);
11958
11959 if (stub_type != arm_stub_none)
11960 {
11961 struct elf32_arm_stub_hash_entry *stub_entry
11962 = elf32_arm_get_stub_entry
11963 (input_section, globals->root.splt, 0, rel,
11964 globals, stub_type);
11965 offset = (stub_entry->stub_offset
11966 + stub_entry->stub_sec->output_offset
11967 + stub_entry->stub_sec->output_section->vma);
11968 }
11969 else
11970 offset = (globals->root.splt->output_section->vma
11971 + globals->root.splt->output_offset
11972 + globals->tls_trampoline);
11973
11974 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11975 {
11976 unsigned long inst;
b38cadfb
NC		 11977
11978 offset -= (input_section->output_section->vma
11979 + input_section->output_offset
11980 + rel->r_offset + 8);
0855e32b
NS		 11981
11982 inst = offset >> 2;
11983 inst &= 0x00ffffff;
11984 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11985 }
11986 else
11987 {
11988 /* Thumb blx encodes the offset in a complicated
11989 fashion. */
11990 unsigned upper_insn, lower_insn;
11991 unsigned neg;
11992
b38cadfb
NC		 11993 offset -= (input_section->output_section->vma
11994 + input_section->output_offset
0855e32b 11995 + rel->r_offset + 4);
b38cadfb 11996
12352d3f
PB		 11997 if (stub_type != arm_stub_none
11998 && arm_stub_is_thumb (stub_type))
11999 {
12000 lower_insn = 0xd000;
12001 }
12002 else
12003 {
12004 lower_insn = 0xc000;
6a631e86 12005 /* Round up the offset to a word boundary. */
12352d3f
PB		 12006 offset = (offset + 2) & ~2;
12007 }
12008
0855e32b
NS		 12009 neg = offset < 0;
12010 upper_insn = (0xf000
12011 | ((offset >> 12) & 0x3ff)
12012 | (neg << 10));
12352d3f 12013 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 12014 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 12015 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 12016 bfd_put_16 (input_bfd, upper_insn, hit_data);
12017 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12018 return bfd_reloc_ok;
12019 }
12020 }
12021 /* These relocations needs special care, as besides the fact
12022 they point somewhere in .gotplt, the addend must be
12023 adjusted accordingly depending on the type of instruction
6a631e86 12024 we refer to. */
0855e32b
NS		 12025 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
12026 {
12027 unsigned long data, insn;
12028 unsigned thumb;
b38cadfb 12029
b627f562 12030 data = bfd_get_signed_32 (input_bfd, hit_data);
0855e32b 12031 thumb = data & 1;
b627f562 12032 data &= ~1ul;
b38cadfb 12033
0855e32b
NS		 12034 if (thumb)
12035 {
12036 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
12037 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
12038 insn = (insn << 16)
12039 | bfd_get_16 (input_bfd,
12040 contents + rel->r_offset - data + 2);
12041 if ((insn & 0xf800c000) == 0xf000c000)
12042 /* bl/blx */
12043 value = -6;
12044 else if ((insn & 0xffffff00) == 0x4400)
12045 /* add */
12046 value = -5;
12047 else
12048 {
4eca0228 12049 _bfd_error_handler
695344c0 12050 /* xgettext:c-format */
2dcf00ce 12051 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12052 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12053 "referenced by TLS_GOTDESC"),
12054 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12055 "Thumb", insn);
0855e32b
NS		 12056 return bfd_reloc_notsupported;
12057 }
12058 }
12059 else
12060 {
12061 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
12062
12063 switch (insn >> 24)
12064 {
12065 case 0xeb: /* bl */
12066 case 0xfa: /* blx */
12067 value = -4;
12068 break;
12069
12070 case 0xe0: /* add */
12071 value = -8;
12072 break;
b38cadfb 12073
0855e32b 12074 default:
4eca0228 12075 _bfd_error_handler
695344c0 12076 /* xgettext:c-format */
2dcf00ce 12077 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12078 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12079 "referenced by TLS_GOTDESC"),
12080 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12081 "ARM", insn);
0855e32b
NS		 12082 return bfd_reloc_notsupported;
12083 }
12084 }
b38cadfb 12085
0855e32b
NS		 12086 value += ((globals->root.sgotplt->output_section->vma
12087 + globals->root.sgotplt->output_offset + off)
12088 - (input_section->output_section->vma
12089 + input_section->output_offset
12090 + rel->r_offset)
12091 + globals->sgotplt_jump_table_size);
12092 }
12093 else
12094 value = ((globals->root.sgot->output_section->vma
12095 + globals->root.sgot->output_offset + off)
12096 - (input_section->output_section->vma
12097 + input_section->output_offset + rel->r_offset));
ba93b8ac 12098
5c5a4843
CL		 12099 if (globals->fdpic_p && (r_type == R_ARM_TLS_GD32_FDPIC ||
12100 r_type == R_ARM_TLS_IE32_FDPIC))
e8b09b87
CL		 12101 {
12102 /* For FDPIC relocations, resolve to the offset of the GOT
12103 entry from the start of GOT. */
12104 bfd_put_32(output_bfd,
12105 globals->root.sgot->output_offset + off,
12106 contents + rel->r_offset);
12107
12108 return bfd_reloc_ok;
12109 }
12110 else
12111 {
12112 return _bfd_final_link_relocate (howto, input_bfd, input_section,
12113 contents, rel->r_offset, value,
12114 rel->r_addend);
12115 }
ba93b8ac
DJ		 12116 }
12117
12118 case R_ARM_TLS_LE32:
3cbc1e5e 12119 if (bfd_link_dll (info))
ba93b8ac 12120 {
4eca0228 12121 _bfd_error_handler
695344c0 12122 /* xgettext:c-format */
2dcf00ce
AM		 12123 (_("%pB(%pA+%#" PRIx64 "): %s relocation not permitted "
12124 "in shared object"),
12125 input_bfd, input_section, (uint64_t) rel->r_offset, howto->name);
46691134 12126 return bfd_reloc_notsupported;
ba93b8ac
DJ		 12127 }
12128 else
12129 value = tpoff (info, value);
906e58ca 12130
ba93b8ac 12131 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 12132 contents, rel->r_offset, value,
12133 rel->r_addend);
ba93b8ac 12134
319850b4
JB		 12135 case R_ARM_V4BX:
12136 if (globals->fix_v4bx)
845b51d6
PB		 12137 {
12138 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 12139
845b51d6
PB		 12140 /* Ensure that we have a BX instruction. */
12141 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 12142
845b51d6
PB		 12143 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
12144 {
12145 /* Branch to veneer. */
12146 bfd_vma glue_addr;
12147 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
12148 glue_addr -= input_section->output_section->vma
12149 + input_section->output_offset
12150 + rel->r_offset + 8;
12151 insn = (insn & 0xf0000000) | 0x0a000000
12152 | ((glue_addr >> 2) & 0x00ffffff);
12153 }
12154 else
12155 {
12156 /* Preserve Rm (lowest four bits) and the condition code
12157 (highest four bits). Other bits encode MOV PC,Rm. */
12158 insn = (insn & 0xf000000f) | 0x01a0f000;
12159 }
319850b4 12160
845b51d6
PB		 12161 bfd_put_32 (input_bfd, insn, hit_data);
12162 }
319850b4
JB		 12163 return bfd_reloc_ok;
12164
b6895b4f
PB		 12165 case R_ARM_MOVW_ABS_NC:
12166 case R_ARM_MOVT_ABS:
12167 case R_ARM_MOVW_PREL_NC:
12168 case R_ARM_MOVT_PREL:
92f5d02b
MS		 12169 /* Until we properly support segment-base-relative addressing then
12170 we assume the segment base to be zero, as for the group relocations.
12171 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12172 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12173 case R_ARM_MOVW_BREL_NC:
12174 case R_ARM_MOVW_BREL:
12175 case R_ARM_MOVT_BREL:
b6895b4f
PB		 12176 {
12177 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
12178
12179 if (globals->use_rel)
12180 {
12181 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 12182 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12183 }
92f5d02b 12184
b6895b4f 12185 value += signed_addend;
b6895b4f
PB		 12186
12187 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
12188 value -= (input_section->output_section->vma
12189 + input_section->output_offset + rel->r_offset);
12190
92f5d02b 12191 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 12192 return bfd_reloc_overflow;
92f5d02b 12193
35fc36a8 12194 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12195 value |= 1;
12196
12197 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 12198 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 12199 value >>= 16;
12200
12201 insn &= 0xfff0f000;
12202 insn |= value & 0xfff;
12203 insn |= (value & 0xf000) << 4;
12204 bfd_put_32 (input_bfd, insn, hit_data);
12205 }
12206 return bfd_reloc_ok;
12207
12208 case R_ARM_THM_MOVW_ABS_NC:
12209 case R_ARM_THM_MOVT_ABS:
12210 case R_ARM_THM_MOVW_PREL_NC:
12211 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 12212 /* Until we properly support segment-base-relative addressing then
12213 we assume the segment base to be zero, as for the above relocations.
12214 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12215 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12216 as R_ARM_THM_MOVT_ABS. */
12217 case R_ARM_THM_MOVW_BREL_NC:
12218 case R_ARM_THM_MOVW_BREL:
12219 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 12220 {
12221 bfd_vma insn;
906e58ca 12222
b6895b4f
PB		 12223 insn = bfd_get_16 (input_bfd, hit_data) << 16;
12224 insn |= bfd_get_16 (input_bfd, hit_data + 2);
12225
12226 if (globals->use_rel)
12227 {
12228 addend = ((insn >> 4) & 0xf000)
12229 | ((insn >> 15) & 0x0800)
12230 | ((insn >> 4) & 0x0700)
07d6d2b8 12231 | (insn & 0x00ff);
39623e12 12232 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12233 }
92f5d02b 12234
b6895b4f 12235 value += signed_addend;
b6895b4f
PB		 12236
12237 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
12238 value -= (input_section->output_section->vma
12239 + input_section->output_offset + rel->r_offset);
12240
92f5d02b 12241 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 12242 return bfd_reloc_overflow;
92f5d02b 12243
35fc36a8 12244 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12245 value |= 1;
12246
12247 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 12248 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 12249 value >>= 16;
12250
12251 insn &= 0xfbf08f00;
12252 insn |= (value & 0xf000) << 4;
12253 insn |= (value & 0x0800) << 15;
12254 insn |= (value & 0x0700) << 4;
12255 insn |= (value & 0x00ff);
12256
12257 bfd_put_16 (input_bfd, insn >> 16, hit_data);
12258 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
12259 }
12260 return bfd_reloc_ok;
12261
4962c51a
MS		 12262 case R_ARM_ALU_PC_G0_NC:
12263 case R_ARM_ALU_PC_G1_NC:
12264 case R_ARM_ALU_PC_G0:
12265 case R_ARM_ALU_PC_G1:
12266 case R_ARM_ALU_PC_G2:
12267 case R_ARM_ALU_SB_G0_NC:
12268 case R_ARM_ALU_SB_G1_NC:
12269 case R_ARM_ALU_SB_G0:
12270 case R_ARM_ALU_SB_G1:
12271 case R_ARM_ALU_SB_G2:
12272 {
12273 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12274 bfd_vma pc = input_section->output_section->vma
4962c51a 12275 + input_section->output_offset + rel->r_offset;
31a91d61 12276 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12277 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 12278 bfd_vma residual;
12279 bfd_vma g_n;
4962c51a 12280 bfd_signed_vma signed_value;
99059e56
RM		 12281 int group = 0;
12282
12283 /* Determine which group of bits to select. */
12284 switch (r_type)
12285 {
12286 case R_ARM_ALU_PC_G0_NC:
12287 case R_ARM_ALU_PC_G0:
12288 case R_ARM_ALU_SB_G0_NC:
12289 case R_ARM_ALU_SB_G0:
12290 group = 0;
12291 break;
12292
12293 case R_ARM_ALU_PC_G1_NC:
12294 case R_ARM_ALU_PC_G1:
12295 case R_ARM_ALU_SB_G1_NC:
12296 case R_ARM_ALU_SB_G1:
12297 group = 1;
12298 break;
12299
12300 case R_ARM_ALU_PC_G2:
12301 case R_ARM_ALU_SB_G2:
12302 group = 2;
12303 break;
12304
12305 default:
12306 abort ();
12307 }
12308
12309 /* If REL, extract the addend from the insn. If RELA, it will
12310 have already been fetched for us. */
4962c51a 12311 if (globals->use_rel)
99059e56
RM		 12312 {
12313 int negative;
12314 bfd_vma constant = insn & 0xff;
12315 bfd_vma rotation = (insn & 0xf00) >> 8;
12316
12317 if (rotation == 0)
12318 signed_addend = constant;
12319 else
12320 {
12321 /* Compensate for the fact that in the instruction, the
12322 rotation is stored in multiples of 2 bits. */
12323 rotation *= 2;
12324
12325 /* Rotate "constant" right by "rotation" bits. */
12326 signed_addend = (constant >> rotation) |
12327 (constant << (8 * sizeof (bfd_vma) - rotation));
12328 }
12329
12330 /* Determine if the instruction is an ADD or a SUB.
12331 (For REL, this determines the sign of the addend.) */
12332 negative = identify_add_or_sub (insn);
12333 if (negative == 0)
12334 {
4eca0228 12335 _bfd_error_handler
695344c0 12336 /* xgettext:c-format */
90b6238f 12337 (_("%pB(%pA+%#" PRIx64 "): only ADD or SUB instructions "
2dcf00ce
AM		 12338 "are allowed for ALU group relocations"),
12339 input_bfd, input_section, (uint64_t) rel->r_offset);
99059e56
RM		 12340 return bfd_reloc_overflow;
12341 }
12342
12343 signed_addend *= negative;
12344 }
4962c51a
MS		 12345
12346 /* Compute the value (X) to go in the place. */
99059e56
RM		 12347 if (r_type == R_ARM_ALU_PC_G0_NC
12348 || r_type == R_ARM_ALU_PC_G1_NC
12349 || r_type == R_ARM_ALU_PC_G0
12350 || r_type == R_ARM_ALU_PC_G1
12351 || r_type == R_ARM_ALU_PC_G2)
12352 /* PC relative. */
12353 signed_value = value - pc + signed_addend;
12354 else
12355 /* Section base relative. */
12356 signed_value = value - sb + signed_addend;
12357
12358 /* If the target symbol is a Thumb function, then set the
12359 Thumb bit in the address. */
35fc36a8 12360 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 12361 signed_value |= 1;
12362
99059e56
RM		 12363 /* Calculate the value of the relevant G_n, in encoded
12364 constant-with-rotation format. */
b6518b38
NC		 12365 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12366 group, &residual);
99059e56
RM		 12367
12368 /* Check for overflow if required. */
12369 if ((r_type == R_ARM_ALU_PC_G0
12370 || r_type == R_ARM_ALU_PC_G1
12371 || r_type == R_ARM_ALU_PC_G2
12372 || r_type == R_ARM_ALU_SB_G0
12373 || r_type == R_ARM_ALU_SB_G1
12374 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
12375 {
4eca0228 12376 _bfd_error_handler
695344c0 12377 /* xgettext:c-format */
90b6238f 12378 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12379 "splitting %#" PRIx64 " for group relocation %s"),
12380 input_bfd, input_section, (uint64_t) rel->r_offset,
12381 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12382 howto->name);
99059e56
RM		 12383 return bfd_reloc_overflow;
12384 }
12385
12386 /* Mask out the value and the ADD/SUB part of the opcode; take care
12387 not to destroy the S bit. */
12388 insn &= 0xff1ff000;
12389
12390 /* Set the opcode according to whether the value to go in the
12391 place is negative. */
12392 if (signed_value < 0)
12393 insn |= 1 << 22;
12394 else
12395 insn |= 1 << 23;
12396
12397 /* Encode the offset. */
12398 insn |= g_n;
4962c51a
MS		 12399
12400 bfd_put_32 (input_bfd, insn, hit_data);
12401 }
12402 return bfd_reloc_ok;
12403
12404 case R_ARM_LDR_PC_G0:
12405 case R_ARM_LDR_PC_G1:
12406 case R_ARM_LDR_PC_G2:
12407 case R_ARM_LDR_SB_G0:
12408 case R_ARM_LDR_SB_G1:
12409 case R_ARM_LDR_SB_G2:
12410 {
12411 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12412 bfd_vma pc = input_section->output_section->vma
4962c51a 12413 + input_section->output_offset + rel->r_offset;
31a91d61 12414 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12415 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12416 bfd_vma residual;
4962c51a 12417 bfd_signed_vma signed_value;
99059e56
RM		 12418 int group = 0;
12419
12420 /* Determine which groups of bits to calculate. */
12421 switch (r_type)
12422 {
12423 case R_ARM_LDR_PC_G0:
12424 case R_ARM_LDR_SB_G0:
12425 group = 0;
12426 break;
12427
12428 case R_ARM_LDR_PC_G1:
12429 case R_ARM_LDR_SB_G1:
12430 group = 1;
12431 break;
12432
12433 case R_ARM_LDR_PC_G2:
12434 case R_ARM_LDR_SB_G2:
12435 group = 2;
12436 break;
12437
12438 default:
12439 abort ();
12440 }
12441
12442 /* If REL, extract the addend from the insn. If RELA, it will
12443 have already been fetched for us. */
4962c51a 12444 if (globals->use_rel)
99059e56
RM		 12445 {
12446 int negative = (insn & (1 << 23)) ? 1 : -1;
12447 signed_addend = negative * (insn & 0xfff);
12448 }
4962c51a
MS		 12449
12450 /* Compute the value (X) to go in the place. */
99059e56
RM		 12451 if (r_type == R_ARM_LDR_PC_G0
12452 || r_type == R_ARM_LDR_PC_G1
12453 || r_type == R_ARM_LDR_PC_G2)
12454 /* PC relative. */
12455 signed_value = value - pc + signed_addend;
12456 else
12457 /* Section base relative. */
12458 signed_value = value - sb + signed_addend;
12459
12460 /* Calculate the value of the relevant G_{n-1} to obtain
12461 the residual at that stage. */
b6518b38
NC		 12462 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12463 group - 1, &residual);
99059e56
RM		 12464
12465 /* Check for overflow. */
12466 if (residual >= 0x1000)
12467 {
4eca0228 12468 _bfd_error_handler
695344c0 12469 /* xgettext:c-format */
90b6238f 12470 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12471 "splitting %#" PRIx64 " for group relocation %s"),
12472 input_bfd, input_section, (uint64_t) rel->r_offset,
12473 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12474 howto->name);
99059e56
RM		 12475 return bfd_reloc_overflow;
12476 }
12477
12478 /* Mask out the value and U bit. */
12479 insn &= 0xff7ff000;
12480
12481 /* Set the U bit if the value to go in the place is non-negative. */
12482 if (signed_value >= 0)
12483 insn |= 1 << 23;
12484
12485 /* Encode the offset. */
12486 insn |= residual;
4962c51a
MS		 12487
12488 bfd_put_32 (input_bfd, insn, hit_data);
12489 }
12490 return bfd_reloc_ok;
12491
12492 case R_ARM_LDRS_PC_G0:
12493 case R_ARM_LDRS_PC_G1:
12494 case R_ARM_LDRS_PC_G2:
12495 case R_ARM_LDRS_SB_G0:
12496 case R_ARM_LDRS_SB_G1:
12497 case R_ARM_LDRS_SB_G2:
12498 {
12499 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12500 bfd_vma pc = input_section->output_section->vma
4962c51a 12501 + input_section->output_offset + rel->r_offset;
31a91d61 12502 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12503 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12504 bfd_vma residual;
4962c51a 12505 bfd_signed_vma signed_value;
99059e56
RM		 12506 int group = 0;
12507
12508 /* Determine which groups of bits to calculate. */
12509 switch (r_type)
12510 {
12511 case R_ARM_LDRS_PC_G0:
12512 case R_ARM_LDRS_SB_G0:
12513 group = 0;
12514 break;
12515
12516 case R_ARM_LDRS_PC_G1:
12517 case R_ARM_LDRS_SB_G1:
12518 group = 1;
12519 break;
12520
12521 case R_ARM_LDRS_PC_G2:
12522 case R_ARM_LDRS_SB_G2:
12523 group = 2;
12524 break;
12525
12526 default:
12527 abort ();
12528 }
12529
12530 /* If REL, extract the addend from the insn. If RELA, it will
12531 have already been fetched for us. */
4962c51a 12532 if (globals->use_rel)
99059e56
RM		 12533 {
12534 int negative = (insn & (1 << 23)) ? 1 : -1;
12535 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
12536 }
4962c51a
MS		 12537
12538 /* Compute the value (X) to go in the place. */
99059e56
RM		 12539 if (r_type == R_ARM_LDRS_PC_G0
12540 || r_type == R_ARM_LDRS_PC_G1
12541 || r_type == R_ARM_LDRS_PC_G2)
12542 /* PC relative. */
12543 signed_value = value - pc + signed_addend;
12544 else
12545 /* Section base relative. */
12546 signed_value = value - sb + signed_addend;
12547
12548 /* Calculate the value of the relevant G_{n-1} to obtain
12549 the residual at that stage. */
b6518b38
NC		 12550 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12551 group - 1, &residual);
99059e56
RM		 12552
12553 /* Check for overflow. */
12554 if (residual >= 0x100)
12555 {
4eca0228 12556 _bfd_error_handler
695344c0 12557 /* xgettext:c-format */
90b6238f 12558 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12559 "splitting %#" PRIx64 " for group relocation %s"),
12560 input_bfd, input_section, (uint64_t) rel->r_offset,
12561 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12562 howto->name);
99059e56
RM		 12563 return bfd_reloc_overflow;
12564 }
12565
12566 /* Mask out the value and U bit. */
12567 insn &= 0xff7ff0f0;
12568
12569 /* Set the U bit if the value to go in the place is non-negative. */
12570 if (signed_value >= 0)
12571 insn |= 1 << 23;
12572
12573 /* Encode the offset. */
12574 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12575
12576 bfd_put_32 (input_bfd, insn, hit_data);
12577 }
12578 return bfd_reloc_ok;
12579
12580 case R_ARM_LDC_PC_G0:
12581 case R_ARM_LDC_PC_G1:
12582 case R_ARM_LDC_PC_G2:
12583 case R_ARM_LDC_SB_G0:
12584 case R_ARM_LDC_SB_G1:
12585 case R_ARM_LDC_SB_G2:
12586 {
12587 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12588 bfd_vma pc = input_section->output_section->vma
4962c51a 12589 + input_section->output_offset + rel->r_offset;
31a91d61 12590 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12591 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12592 bfd_vma residual;
4962c51a 12593 bfd_signed_vma signed_value;
99059e56
RM		 12594 int group = 0;
12595
12596 /* Determine which groups of bits to calculate. */
12597 switch (r_type)
12598 {
12599 case R_ARM_LDC_PC_G0:
12600 case R_ARM_LDC_SB_G0:
12601 group = 0;
12602 break;
12603
12604 case R_ARM_LDC_PC_G1:
12605 case R_ARM_LDC_SB_G1:
12606 group = 1;
12607 break;
12608
12609 case R_ARM_LDC_PC_G2:
12610 case R_ARM_LDC_SB_G2:
12611 group = 2;
12612 break;
12613
12614 default:
12615 abort ();
12616 }
12617
12618 /* If REL, extract the addend from the insn. If RELA, it will
12619 have already been fetched for us. */
4962c51a 12620 if (globals->use_rel)
99059e56
RM		 12621 {
12622 int negative = (insn & (1 << 23)) ? 1 : -1;
12623 signed_addend = negative * ((insn & 0xff) << 2);
12624 }
4962c51a
MS		 12625
12626 /* Compute the value (X) to go in the place. */
99059e56
RM		 12627 if (r_type == R_ARM_LDC_PC_G0
12628 || r_type == R_ARM_LDC_PC_G1
12629 || r_type == R_ARM_LDC_PC_G2)
12630 /* PC relative. */
12631 signed_value = value - pc + signed_addend;
12632 else
12633 /* Section base relative. */
12634 signed_value = value - sb + signed_addend;
12635
12636 /* Calculate the value of the relevant G_{n-1} to obtain
12637 the residual at that stage. */
b6518b38
NC		 12638 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12639 group - 1, &residual);
99059e56
RM		 12640
12641 /* Check for overflow. (The absolute value to go in the place must be
12642 divisible by four and, after having been divided by four, must
12643 fit in eight bits.) */
12644 if ((residual & 0x3) != 0 || residual >= 0x400)
12645 {
4eca0228 12646 _bfd_error_handler
695344c0 12647 /* xgettext:c-format */
90b6238f 12648 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12649 "splitting %#" PRIx64 " for group relocation %s"),
12650 input_bfd, input_section, (uint64_t) rel->r_offset,
12651 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12652 howto->name);
99059e56
RM		 12653 return bfd_reloc_overflow;
12654 }
12655
12656 /* Mask out the value and U bit. */
12657 insn &= 0xff7fff00;
12658
12659 /* Set the U bit if the value to go in the place is non-negative. */
12660 if (signed_value >= 0)
12661 insn |= 1 << 23;
12662
12663 /* Encode the offset. */
12664 insn |= residual >> 2;
4962c51a
MS		 12665
12666 bfd_put_32 (input_bfd, insn, hit_data);
12667 }
12668 return bfd_reloc_ok;
12669
72d98d16
MG		 12670 case R_ARM_THM_ALU_ABS_G0_NC:
12671 case R_ARM_THM_ALU_ABS_G1_NC:
12672 case R_ARM_THM_ALU_ABS_G2_NC:
12673 case R_ARM_THM_ALU_ABS_G3_NC:
12674 {
12675 const int shift_array[4] = {0, 8, 16, 24};
12676 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12677 bfd_vma addr = value;
12678 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12679
12680 /* Compute address. */
12681 if (globals->use_rel)
12682 signed_addend = insn & 0xff;
12683 addr += signed_addend;
12684 if (branch_type == ST_BRANCH_TO_THUMB)
12685 addr |= 1;
12686 /* Clean imm8 insn. */
12687 insn &= 0xff00;
12688 /* And update with correct part of address. */
12689 insn |= (addr >> shift) & 0xff;
12690 /* Update insn. */
12691 bfd_put_16 (input_bfd, insn, hit_data);
12692 }
12693
12694 *unresolved_reloc_p = FALSE;
12695 return bfd_reloc_ok;
12696
e8b09b87
CL		 12697 case R_ARM_GOTOFFFUNCDESC:
12698 {
4b24dd1a 12699 if (h == NULL)
e8b09b87
CL		 12700 {
12701 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12702 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12703 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12704 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12705 bfd_vma seg = -1;
12706
12707 if (bfd_link_pic(info) && dynindx == 0)
12708 abort();
12709
12710 /* Resolve relocation. */
12711 bfd_put_32(output_bfd, (offset + sgot->output_offset)
12712 , contents + rel->r_offset);
12713 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12714 not done yet. */
12715 arm_elf_fill_funcdesc(output_bfd, info,
12716 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12717 dynindx, offset, addr, dynreloc_value, seg);
12718 }
12719 else
12720 {
12721 int dynindx;
12722 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12723 bfd_vma addr;
12724 bfd_vma seg = -1;
12725
12726 /* For static binaries, sym_sec can be null. */
12727 if (sym_sec)
12728 {
12729 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12730 addr = dynreloc_value - sym_sec->output_section->vma;
12731 }
12732 else
12733 {
12734 dynindx = 0;
12735 addr = 0;
12736 }
12737
12738 if (bfd_link_pic(info) && dynindx == 0)
12739 abort();
12740
12741 /* This case cannot occur since funcdesc is allocated by
12742 the dynamic loader so we cannot resolve the relocation. */
12743 if (h->dynindx != -1)
12744 abort();
12745
12746 /* Resolve relocation. */
12747 bfd_put_32(output_bfd, (offset + sgot->output_offset),
12748 contents + rel->r_offset);
12749 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12750 arm_elf_fill_funcdesc(output_bfd, info,
12751 &eh->fdpic_cnts.funcdesc_offset,
12752 dynindx, offset, addr, dynreloc_value, seg);
12753 }
12754 }
12755 *unresolved_reloc_p = FALSE;
12756 return bfd_reloc_ok;
12757
12758 case R_ARM_GOTFUNCDESC:
12759 {
4b24dd1a 12760 if (h != NULL)
e8b09b87
CL		 12761 {
12762 Elf_Internal_Rela outrel;
12763
12764 /* Resolve relocation. */
12765 bfd_put_32(output_bfd, ((eh->fdpic_cnts.gotfuncdesc_offset & ~1)
12766 + sgot->output_offset),
12767 contents + rel->r_offset);
12768 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12769 if(h->dynindx == -1)
12770 {
12771 int dynindx;
12772 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12773 bfd_vma addr;
12774 bfd_vma seg = -1;
12775
12776 /* For static binaries sym_sec can be null. */
12777 if (sym_sec)
12778 {
12779 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12780 addr = dynreloc_value - sym_sec->output_section->vma;
12781 }
12782 else
12783 {
12784 dynindx = 0;
12785 addr = 0;
12786 }
12787
12788 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12789 arm_elf_fill_funcdesc(output_bfd, info,
12790 &eh->fdpic_cnts.funcdesc_offset,
12791 dynindx, offset, addr, dynreloc_value, seg);
12792 }
12793
12794 /* Add a dynamic relocation on GOT entry if not already done. */
12795 if ((eh->fdpic_cnts.gotfuncdesc_offset & 1) == 0)
12796 {
12797 if (h->dynindx == -1)
12798 {
12799 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12800 if (h->root.type == bfd_link_hash_undefweak)
12801 bfd_put_32(output_bfd, 0, sgot->contents
12802 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12803 else
12804 bfd_put_32(output_bfd, sgot->output_section->vma
12805 + sgot->output_offset
12806 + (eh->fdpic_cnts.funcdesc_offset & ~1),
12807 sgot->contents
12808 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12809 }
12810 else
12811 {
12812 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12813 }
12814 outrel.r_offset = sgot->output_section->vma
12815 + sgot->output_offset
12816 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1);
12817 outrel.r_addend = 0;
12818 if (h->dynindx == -1 && !bfd_link_pic(info))
12819 if (h->root.type == bfd_link_hash_undefweak)
4b24dd1a 12820 arm_elf_add_rofixup(output_bfd, globals->srofixup, -1);
e8b09b87 12821 else
4b24dd1a
AM		 12822 arm_elf_add_rofixup(output_bfd, globals->srofixup,
12823 outrel.r_offset);
e8b09b87
CL		 12824 else
12825 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12826 eh->fdpic_cnts.gotfuncdesc_offset |= 1;
12827 }
12828 }
12829 else
12830 {
12831 /* Such relocation on static function should not have been
12832 emitted by the compiler. */
12833 abort();
12834 }
12835 }
12836 *unresolved_reloc_p = FALSE;
12837 return bfd_reloc_ok;
12838
12839 case R_ARM_FUNCDESC:
12840 {
4b24dd1a 12841 if (h == NULL)
e8b09b87
CL		 12842 {
12843 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12844 Elf_Internal_Rela outrel;
12845 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12846 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12847 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12848 bfd_vma seg = -1;
12849
12850 if (bfd_link_pic(info) && dynindx == 0)
12851 abort();
12852
12853 /* Replace static FUNCDESC relocation with a
12854 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12855 executable. */
12856 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12857 outrel.r_offset = input_section->output_section->vma
12858 + input_section->output_offset + rel->r_offset;
12859 outrel.r_addend = 0;
12860 if (bfd_link_pic(info))
12861 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12862 else
12863 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12864
12865 bfd_put_32 (input_bfd, sgot->output_section->vma
12866 + sgot->output_offset + offset, hit_data);
12867
12868 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12869 arm_elf_fill_funcdesc(output_bfd, info,
12870 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12871 dynindx, offset, addr, dynreloc_value, seg);
12872 }
12873 else
12874 {
12875 if (h->dynindx == -1)
12876 {
12877 int dynindx;
12878 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12879 bfd_vma addr;
12880 bfd_vma seg = -1;
12881 Elf_Internal_Rela outrel;
12882
12883 /* For static binaries sym_sec can be null. */
12884 if (sym_sec)
12885 {
12886 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12887 addr = dynreloc_value - sym_sec->output_section->vma;
12888 }
12889 else
12890 {
12891 dynindx = 0;
12892 addr = 0;
12893 }
12894
12895 if (bfd_link_pic(info) && dynindx == 0)
12896 abort();
12897
12898 /* Replace static FUNCDESC relocation with a
12899 R_ARM_RELATIVE dynamic relocation. */
12900 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12901 outrel.r_offset = input_section->output_section->vma
12902 + input_section->output_offset + rel->r_offset;
12903 outrel.r_addend = 0;
12904 if (bfd_link_pic(info))
12905 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12906 else
12907 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12908
12909 bfd_put_32 (input_bfd, sgot->output_section->vma
12910 + sgot->output_offset + offset, hit_data);
12911
12912 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12913 arm_elf_fill_funcdesc(output_bfd, info,
12914 &eh->fdpic_cnts.funcdesc_offset,
12915 dynindx, offset, addr, dynreloc_value, seg);
12916 }
12917 else
12918 {
12919 Elf_Internal_Rela outrel;
12920
12921 /* Add a dynamic relocation. */
12922 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12923 outrel.r_offset = input_section->output_section->vma
12924 + input_section->output_offset + rel->r_offset;
12925 outrel.r_addend = 0;
12926 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12927 }
12928 }
12929 }
12930 *unresolved_reloc_p = FALSE;
12931 return bfd_reloc_ok;
12932
e5d6e09e
AV		 12933 case R_ARM_THM_BF16:
12934 {
12935 bfd_vma relocation;
12936 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12937 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12938
12939 if (globals->use_rel)
12940 {
12941 bfd_vma immA = (upper_insn & 0x001f);
12942 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12943 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12944 addend = (immA << 12);
12945 addend |= (immB << 2);
12946 addend |= (immC << 1);
12947 addend |= 1;
12948 /* Sign extend. */
e6f65e75 12949 signed_addend = (addend & 0x10000) ? addend - (1 << 17) : addend;
e5d6e09e
AV		 12950 }
12951
e6f65e75 12952 relocation = value + signed_addend;
e5d6e09e
AV		 12953 relocation -= (input_section->output_section->vma
12954 + input_section->output_offset
12955 + rel->r_offset);
12956
12957 /* Put RELOCATION back into the insn. */
12958 {
12959 bfd_vma immA = (relocation & 0x0001f000) >> 12;
12960 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12961 bfd_vma immC = (relocation & 0x00000002) >> 1;
12962
12963 upper_insn = (upper_insn & 0xffe0) | immA;
12964 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
12965 }
12966
12967 /* Put the relocated value back in the object file: */
12968 bfd_put_16 (input_bfd, upper_insn, hit_data);
12969 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12970
12971 return bfd_reloc_ok;
12972 }
12973
1889da70
AV		 12974 case R_ARM_THM_BF12:
12975 {
12976 bfd_vma relocation;
12977 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12978 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12979
12980 if (globals->use_rel)
12981 {
12982 bfd_vma immA = (upper_insn & 0x0001);
12983 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12984 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12985 addend = (immA << 12);
12986 addend |= (immB << 2);
12987 addend |= (immC << 1);
12988 addend |= 1;
12989 /* Sign extend. */
12990 addend = (addend & 0x1000) ? addend - (1 << 13) : addend;
e6f65e75 12991 signed_addend = addend;
1889da70
AV		 12992 }
12993
e6f65e75 12994 relocation = value + signed_addend;
1889da70
AV		 12995 relocation -= (input_section->output_section->vma
12996 + input_section->output_offset
12997 + rel->r_offset);
12998
12999 /* Put RELOCATION back into the insn. */
13000 {
13001 bfd_vma immA = (relocation & 0x00001000) >> 12;
13002 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
13003 bfd_vma immC = (relocation & 0x00000002) >> 1;
13004
13005 upper_insn = (upper_insn & 0xfffe) | immA;
13006 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
13007 }
13008
13009 /* Put the relocated value back in the object file: */
13010 bfd_put_16 (input_bfd, upper_insn, hit_data);
13011 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
13012
13013 return bfd_reloc_ok;
13014 }
13015
1caf72a5
AV		 13016 case R_ARM_THM_BF18:
13017 {
13018 bfd_vma relocation;
13019 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
13020 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
13021
13022 if (globals->use_rel)
13023 {
13024 bfd_vma immA = (upper_insn & 0x007f);
13025 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
13026 bfd_vma immC = (lower_insn & 0x0800) >> 11;
13027 addend = (immA << 12);
13028 addend |= (immB << 2);
13029 addend |= (immC << 1);
13030 addend |= 1;
13031 /* Sign extend. */
13032 addend = (addend & 0x40000) ? addend - (1 << 19) : addend;
e6f65e75 13033 signed_addend = addend;
1caf72a5
AV		 13034 }
13035
e6f65e75 13036 relocation = value + signed_addend;
1caf72a5
AV		 13037 relocation -= (input_section->output_section->vma
13038 + input_section->output_offset
13039 + rel->r_offset);
13040
13041 /* Put RELOCATION back into the insn. */
13042 {
13043 bfd_vma immA = (relocation & 0x0007f000) >> 12;
13044 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
13045 bfd_vma immC = (relocation & 0x00000002) >> 1;
13046
13047 upper_insn = (upper_insn & 0xff80) | immA;
13048 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
13049 }
13050
13051 /* Put the relocated value back in the object file: */
13052 bfd_put_16 (input_bfd, upper_insn, hit_data);
13053 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
13054
13055 return bfd_reloc_ok;
13056 }
13057
252b5132
RH		 13058 default:
13059 return bfd_reloc_notsupported;
13060 }
13061}
13062
98c1d4aa
NC		 13063/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
13064static void
07d6d2b8
AM		 13065arm_add_to_rel (bfd * abfd,
13066 bfd_byte * address,
57e8b36a 13067 reloc_howto_type * howto,
07d6d2b8 13068 bfd_signed_vma increment)
98c1d4aa 13069{
98c1d4aa
NC		 13070 bfd_signed_vma addend;
13071
bd97cb95
DJ		 13072 if (howto->type == R_ARM_THM_CALL
13073 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 13074 {
9a5aca8c
AM		 13075 int upper_insn, lower_insn;
13076 int upper, lower;
98c1d4aa 13077
9a5aca8c
AM		 13078 upper_insn = bfd_get_16 (abfd, address);
13079 lower_insn = bfd_get_16 (abfd, address + 2);
13080 upper = upper_insn & 0x7ff;
13081 lower = lower_insn & 0x7ff;
13082
13083 addend = (upper << 12) | (lower << 1);
ddda4409 13084 addend += increment;
9a5aca8c 13085 addend >>= 1;
98c1d4aa 13086
9a5aca8c
AM		 13087 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
13088 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
13089
dc810e39
AM		 13090 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
13091 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 13092 }
13093 else
13094 {
07d6d2b8 13095 bfd_vma contents;
9a5aca8c
AM		 13096
13097 contents = bfd_get_32 (abfd, address);
13098
13099 /* Get the (signed) value from the instruction. */
13100 addend = contents & howto->src_mask;
13101 if (addend & ((howto->src_mask + 1) >> 1))
13102 {
13103 bfd_signed_vma mask;
13104
13105 mask = -1;
13106 mask &= ~ howto->src_mask;
13107 addend |= mask;
13108 }
13109
13110 /* Add in the increment, (which is a byte value). */
13111 switch (howto->type)
13112 {
13113 default:
13114 addend += increment;
13115 break;
13116
13117 case R_ARM_PC24:
c6596c5e 13118 case R_ARM_PLT32:
5b5bb741
PB		 13119 case R_ARM_CALL:
13120 case R_ARM_JUMP24:
9a5aca8c 13121 addend <<= howto->size;
dc810e39 13122 addend += increment;
9a5aca8c
AM		 13123
13124 /* Should we check for overflow here ? */
13125
13126 /* Drop any undesired bits. */
13127 addend >>= howto->rightshift;
13128 break;
13129 }
13130
13131 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
13132
13133 bfd_put_32 (abfd, contents, address);
ddda4409 13134 }
98c1d4aa 13135}
252b5132 13136
ba93b8ac
DJ		 13137#define IS_ARM_TLS_RELOC(R_TYPE) \
13138 ((R_TYPE) == R_ARM_TLS_GD32 \
5c5a4843 13139 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
ba93b8ac
DJ		 13140 || (R_TYPE) == R_ARM_TLS_LDO32 \
13141 || (R_TYPE) == R_ARM_TLS_LDM32 \
5c5a4843 13142 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
ba93b8ac
DJ		 13143 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
13144 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
13145 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
13146 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b 13147 || (R_TYPE) == R_ARM_TLS_IE32 \
5c5a4843 13148 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
0855e32b
NS		 13149 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
13150
13151/* Specific set of relocations for the gnu tls dialect. */
13152#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
13153 ((R_TYPE) == R_ARM_TLS_GOTDESC \
13154 || (R_TYPE) == R_ARM_TLS_CALL \
13155 || (R_TYPE) == R_ARM_THM_TLS_CALL \
13156 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
13157 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 13158
252b5132 13159/* Relocate an ARM ELF section. */
906e58ca 13160
b34976b6 13161static bfd_boolean
07d6d2b8 13162elf32_arm_relocate_section (bfd * output_bfd,
57e8b36a 13163 struct bfd_link_info * info,
07d6d2b8
AM		 13164 bfd * input_bfd,
13165 asection * input_section,
13166 bfd_byte * contents,
13167 Elf_Internal_Rela * relocs,
13168 Elf_Internal_Sym * local_syms,
13169 asection ** local_sections)
252b5132 13170{
b34976b6
AM		 13171 Elf_Internal_Shdr *symtab_hdr;
13172 struct elf_link_hash_entry **sym_hashes;
13173 Elf_Internal_Rela *rel;
13174 Elf_Internal_Rela *relend;
13175 const char *name;
b32d3aa2 13176 struct elf32_arm_link_hash_table * globals;
252b5132 13177
4e7fd91e 13178 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13179 if (globals == NULL)
13180 return FALSE;
b491616a 13181
0ffa91dd 13182 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 13183 sym_hashes = elf_sym_hashes (input_bfd);
13184
13185 rel = relocs;
13186 relend = relocs + input_section->reloc_count;
13187 for (; rel < relend; rel++)
13188 {
07d6d2b8
AM		 13189 int r_type;
13190 reloc_howto_type * howto;
13191 unsigned long r_symndx;
13192 Elf_Internal_Sym * sym;
13193 asection * sec;
252b5132 13194 struct elf_link_hash_entry * h;
07d6d2b8
AM		 13195 bfd_vma relocation;
13196 bfd_reloc_status_type r;
13197 arelent bfd_reloc;
13198 char sym_type;
13199 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 13200 char *error_message = NULL;
f21f3fe0 13201
252b5132 13202 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 13203 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 13204 r_type = arm_real_reloc_type (globals, r_type);
252b5132 13205
ba96a88f 13206 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 13207 || r_type == R_ARM_GNU_VTINHERIT)
13208 continue;
252b5132 13209
47aeb64c
NC		 13210 howto = bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
13211
13212 if (howto == NULL)
13213 return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
252b5132 13214
252b5132
RH		 13215 h = NULL;
13216 sym = NULL;
13217 sec = NULL;
9b485d32 13218
252b5132
RH		 13219 if (r_symndx < symtab_hdr->sh_info)
13220 {
13221 sym = local_syms + r_symndx;
ba93b8ac 13222 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 13223 sec = local_sections[r_symndx];
ffcb4889
NS		 13224
13225 /* An object file might have a reference to a local
13226 undefined symbol. This is a daft object file, but we
13227 should at least do something about it. V4BX & NONE
13228 relocations do not use the symbol and are explicitly
77b4f08f
TS		 13229 allowed to use the undefined symbol, so allow those.
13230 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 13231 if (r_type != R_ARM_V4BX
13232 && r_type != R_ARM_NONE
77b4f08f 13233 && r_symndx != STN_UNDEF
ffcb4889
NS		 13234 && bfd_is_und_section (sec)
13235 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 13236 (*info->callbacks->undefined_symbol)
13237 (info, bfd_elf_string_from_elf_section
13238 (input_bfd, symtab_hdr->sh_link, sym->st_name),
13239 input_bfd, input_section,
13240 rel->r_offset, TRUE);
b38cadfb 13241
4e7fd91e 13242 if (globals->use_rel)
f8df10f4 13243 {
4e7fd91e
PB		 13244 relocation = (sec->output_section->vma
13245 + sec->output_offset
13246 + sym->st_value);
0e1862bb 13247 if (!bfd_link_relocatable (info)
ab96bf03
AM		 13248 && (sec->flags & SEC_MERGE)
13249 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 13250 {
4e7fd91e
PB		 13251 asection *msec;
13252 bfd_vma addend, value;
13253
39623e12 13254 switch (r_type)
4e7fd91e 13255 {
39623e12
PB		 13256 case R_ARM_MOVW_ABS_NC:
13257 case R_ARM_MOVT_ABS:
13258 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13259 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
13260 addend = (addend ^ 0x8000) - 0x8000;
13261 break;
f8df10f4 13262
39623e12
PB		 13263 case R_ARM_THM_MOVW_ABS_NC:
13264 case R_ARM_THM_MOVT_ABS:
13265 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
13266 << 16;
13267 value |= bfd_get_16 (input_bfd,
13268 contents + rel->r_offset + 2);
13269 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
13270 | ((value & 0x04000000) >> 15);
13271 addend = (addend ^ 0x8000) - 0x8000;
13272 break;
f8df10f4 13273
39623e12
PB		 13274 default:
13275 if (howto->rightshift
13276 || (howto->src_mask & (howto->src_mask + 1)))
13277 {
4eca0228 13278 _bfd_error_handler
695344c0 13279 /* xgettext:c-format */
2dcf00ce
AM		 13280 (_("%pB(%pA+%#" PRIx64 "): "
13281 "%s relocation against SEC_MERGE section"),
39623e12 13282 input_bfd, input_section,
2dcf00ce 13283 (uint64_t) rel->r_offset, howto->name);
39623e12
PB		 13284 return FALSE;
13285 }
13286
13287 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13288
13289 /* Get the (signed) value from the instruction. */
13290 addend = value & howto->src_mask;
13291 if (addend & ((howto->src_mask + 1) >> 1))
13292 {
13293 bfd_signed_vma mask;
13294
13295 mask = -1;
13296 mask &= ~ howto->src_mask;
13297 addend |= mask;
13298 }
13299 break;
4e7fd91e 13300 }
39623e12 13301
4e7fd91e
PB		 13302 msec = sec;
13303 addend =
13304 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
13305 - relocation;
13306 addend += msec->output_section->vma + msec->output_offset;
39623e12 13307
cc643b88 13308 /* Cases here must match those in the preceding
39623e12
PB		 13309 switch statement. */
13310 switch (r_type)
13311 {
13312 case R_ARM_MOVW_ABS_NC:
13313 case R_ARM_MOVT_ABS:
13314 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
13315 | (addend & 0xfff);
13316 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13317 break;
13318
13319 case R_ARM_THM_MOVW_ABS_NC:
13320 case R_ARM_THM_MOVT_ABS:
13321 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
13322 | (addend & 0xff) | ((addend & 0x0800) << 15);
13323 bfd_put_16 (input_bfd, value >> 16,
13324 contents + rel->r_offset);
13325 bfd_put_16 (input_bfd, value,
13326 contents + rel->r_offset + 2);
13327 break;
13328
13329 default:
13330 value = (value & ~ howto->dst_mask)
13331 | (addend & howto->dst_mask);
13332 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13333 break;
13334 }
f8df10f4 13335 }
f8df10f4 13336 }
4e7fd91e
PB		 13337 else
13338 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 13339 }
13340 else
13341 {
62d887d4 13342 bfd_boolean warned, ignored;
560e09e9 13343
b2a8e766
AM		 13344 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
13345 r_symndx, symtab_hdr, sym_hashes,
13346 h, sec, relocation,
62d887d4 13347 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 13348
13349 sym_type = h->type;
252b5132
RH		 13350 }
13351
dbaa2011 13352 if (sec != NULL && discarded_section (sec))
e4067dbb 13353 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 13354 rel, 1, relend, howto, 0, contents);
ab96bf03 13355
0e1862bb 13356 if (bfd_link_relocatable (info))
ab96bf03
AM		 13357 {
13358 /* This is a relocatable link. We don't have to change
13359 anything, unless the reloc is against a section symbol,
13360 in which case we have to adjust according to where the
13361 section symbol winds up in the output section. */
13362 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
13363 {
13364 if (globals->use_rel)
13365 arm_add_to_rel (input_bfd, contents + rel->r_offset,
13366 howto, (bfd_signed_vma) sec->output_offset);
13367 else
13368 rel->r_addend += sec->output_offset;
13369 }
13370 continue;
13371 }
13372
252b5132
RH		 13373 if (h != NULL)
13374 name = h->root.root.string;
13375 else
13376 {
13377 name = (bfd_elf_string_from_elf_section
13378 (input_bfd, symtab_hdr->sh_link, sym->st_name));
13379 if (name == NULL || *name == '\0')
fd361982 13380 name = bfd_section_name (sec);
252b5132 13381 }
f21f3fe0 13382
cf35638d 13383 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 13384 && r_type != R_ARM_NONE
13385 && (h == NULL
13386 || h->root.type == bfd_link_hash_defined
13387 || h->root.type == bfd_link_hash_defweak)
13388 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
13389 {
4eca0228 13390 _bfd_error_handler
ba93b8ac 13391 ((sym_type == STT_TLS
695344c0 13392 /* xgettext:c-format */
2dcf00ce 13393 ? _("%pB(%pA+%#" PRIx64 "): %s used with TLS symbol %s")
695344c0 13394 /* xgettext:c-format */
2dcf00ce 13395 : _("%pB(%pA+%#" PRIx64 "): %s used with non-TLS symbol %s")),
ba93b8ac
DJ		 13396 input_bfd,
13397 input_section,
2dcf00ce 13398 (uint64_t) rel->r_offset,
ba93b8ac
DJ		 13399 howto->name,
13400 name);
13401 }
13402
0855e32b 13403 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 13404 done, i.e., the relaxation produced the final output we want,
13405 and we won't let anybody mess with it. Also, we have to do
13406 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 13407 both in relaxed and non-relaxed cases. */
39d911fc
TP		 13408 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
13409 || (IS_ARM_TLS_GNU_RELOC (r_type)
13410 && !((h ? elf32_arm_hash_entry (h)->tls_type :
13411 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
13412 & GOT_TLS_GDESC)))
13413 {
13414 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
13415 contents, rel, h == NULL);
13416 /* This may have been marked unresolved because it came from
13417 a shared library. But we've just dealt with that. */
13418 unresolved_reloc = 0;
13419 }
13420 else
13421 r = bfd_reloc_continue;
b38cadfb 13422
39d911fc
TP		 13423 if (r == bfd_reloc_continue)
13424 {
13425 unsigned char branch_type =
13426 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
13427 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
13428
13429 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
13430 input_section, contents, rel,
13431 relocation, info, sec, name,
13432 sym_type, branch_type, h,
13433 &unresolved_reloc,
13434 &error_message);
13435 }
0945cdfd
DJ		 13436
13437 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13438 because such sections are not SEC_ALLOC and thus ld.so will
13439 not process them. */
13440 if (unresolved_reloc
99059e56
RM		 13441 && !((input_section->flags & SEC_DEBUGGING) != 0
13442 && h->def_dynamic)
1d5316ab
AM		 13443 && _bfd_elf_section_offset (output_bfd, info, input_section,
13444 rel->r_offset) != (bfd_vma) -1)
0945cdfd 13445 {
4eca0228 13446 _bfd_error_handler
695344c0 13447 /* xgettext:c-format */
2dcf00ce
AM		 13448 (_("%pB(%pA+%#" PRIx64 "): "
13449 "unresolvable %s relocation against symbol `%s'"),
843fe662
L		 13450 input_bfd,
13451 input_section,
2dcf00ce 13452 (uint64_t) rel->r_offset,
843fe662
L		 13453 howto->name,
13454 h->root.root.string);
0945cdfd
DJ		 13455 return FALSE;
13456 }
252b5132
RH		 13457
13458 if (r != bfd_reloc_ok)
13459 {
252b5132
RH		 13460 switch (r)
13461 {
13462 case bfd_reloc_overflow:
cf919dfd
PB		 13463 /* If the overflowing reloc was to an undefined symbol,
13464 we have already printed one error message and there
13465 is no point complaining again. */
1a72702b
AM		 13466 if (!h || h->root.type != bfd_link_hash_undefined)
13467 (*info->callbacks->reloc_overflow)
13468 (info, (h ? &h->root : NULL), name, howto->name,
13469 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13470 break;
13471
13472 case bfd_reloc_undefined:
1a72702b
AM		 13473 (*info->callbacks->undefined_symbol)
13474 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 13475 break;
13476
13477 case bfd_reloc_outofrange:
f2a9dd69 13478 error_message = _("out of range");
252b5132
RH		 13479 goto common_error;
13480
13481 case bfd_reloc_notsupported:
f2a9dd69 13482 error_message = _("unsupported relocation");
252b5132
RH		 13483 goto common_error;
13484
13485 case bfd_reloc_dangerous:
f2a9dd69 13486 /* error_message should already be set. */
252b5132
RH		 13487 goto common_error;
13488
13489 default:
f2a9dd69 13490 error_message = _("unknown error");
8029a119 13491 /* Fall through. */
252b5132
RH		 13492
13493 common_error:
f2a9dd69 13494 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 13495 (*info->callbacks->reloc_dangerous)
13496 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13497 break;
13498 }
13499 }
13500 }
13501
b34976b6 13502 return TRUE;
252b5132
RH		 13503}
13504
91d6fa6a 13505/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 13506 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 13507 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 13508 maintaining that condition). */
13509
13510static void
13511add_unwind_table_edit (arm_unwind_table_edit **head,
13512 arm_unwind_table_edit **tail,
13513 arm_unwind_edit_type type,
13514 asection *linked_section,
91d6fa6a 13515 unsigned int tindex)
2468f9c9 13516{
21d799b5
NC		 13517 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
13518 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 13519
2468f9c9
PB		 13520 new_edit->type = type;
13521 new_edit->linked_section = linked_section;
91d6fa6a 13522 new_edit->index = tindex;
b38cadfb 13523
91d6fa6a 13524 if (tindex > 0)
2468f9c9
PB		 13525 {
13526 new_edit->next = NULL;
13527
13528 if (*tail)
13529 (*tail)->next = new_edit;
13530
13531 (*tail) = new_edit;
13532
13533 if (!*head)
13534 (*head) = new_edit;
13535 }
13536 else
13537 {
13538 new_edit->next = *head;
13539
13540 if (!*tail)
13541 *tail = new_edit;
13542
13543 *head = new_edit;
13544 }
13545}
13546
13547static _arm_elf_section_data *get_arm_elf_section_data (asection *);
13548
13549/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13550static void
13551adjust_exidx_size(asection *exidx_sec, int adjust)
13552{
13553 asection *out_sec;
13554
13555 if (!exidx_sec->rawsize)
13556 exidx_sec->rawsize = exidx_sec->size;
13557
fd361982 13558 bfd_set_section_size (exidx_sec, exidx_sec->size + adjust);
2468f9c9
PB		 13559 out_sec = exidx_sec->output_section;
13560 /* Adjust size of output section. */
fd361982 13561 bfd_set_section_size (out_sec, out_sec->size +adjust);
2468f9c9
PB		 13562}
13563
13564/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13565static void
13566insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
13567{
13568 struct _arm_elf_section_data *exidx_arm_data;
13569
13570 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13571 add_unwind_table_edit (
13572 &exidx_arm_data->u.exidx.unwind_edit_list,
13573 &exidx_arm_data->u.exidx.unwind_edit_tail,
13574 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
13575
491d01d3
YU		 13576 exidx_arm_data->additional_reloc_count++;
13577
2468f9c9
PB		 13578 adjust_exidx_size(exidx_sec, 8);
13579}
13580
13581/* Scan .ARM.exidx tables, and create a list describing edits which should be
13582 made to those tables, such that:
b38cadfb 13583
2468f9c9
PB		 13584 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13585 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 13586 codes which have been inlined into the index).
2468f9c9 13587
85fdf906
AH		 13588 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13589
2468f9c9 13590 The edits are applied when the tables are written
b38cadfb 13591 (in elf32_arm_write_section). */
2468f9c9
PB		 13592
13593bfd_boolean
13594elf32_arm_fix_exidx_coverage (asection **text_section_order,
13595 unsigned int num_text_sections,
85fdf906
AH		 13596 struct bfd_link_info *info,
13597 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 13598{
13599 bfd *inp;
13600 unsigned int last_second_word = 0, i;
13601 asection *last_exidx_sec = NULL;
13602 asection *last_text_sec = NULL;
13603 int last_unwind_type = -1;
13604
13605 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13606 text sections. */
c72f2fb2 13607 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 13608 {
13609 asection *sec;
b38cadfb 13610
2468f9c9 13611 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 13612 {
2468f9c9
PB		 13613 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
13614 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 13615
dec9d5df 13616 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 13617 continue;
b38cadfb 13618
2468f9c9
PB		 13619 if (elf_sec->linked_to)
13620 {
13621 Elf_Internal_Shdr *linked_hdr
99059e56 13622 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 13623 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 13624 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 13625
13626 if (linked_sec_arm_data == NULL)
99059e56 13627 continue;
2468f9c9
PB		 13628
13629 /* Link this .ARM.exidx section back from the text section it
99059e56 13630 describes. */
2468f9c9
PB		 13631 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
13632 }
13633 }
13634 }
13635
13636 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13637 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 13638 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 13639
13640 for (i = 0; i < num_text_sections; i++)
13641 {
13642 asection *sec = text_section_order[i];
13643 asection *exidx_sec;
13644 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
13645 struct _arm_elf_section_data *exidx_arm_data;
13646 bfd_byte *contents = NULL;
13647 int deleted_exidx_bytes = 0;
13648 bfd_vma j;
13649 arm_unwind_table_edit *unwind_edit_head = NULL;
13650 arm_unwind_table_edit *unwind_edit_tail = NULL;
13651 Elf_Internal_Shdr *hdr;
13652 bfd *ibfd;
13653
13654 if (arm_data == NULL)
99059e56 13655 continue;
2468f9c9
PB		 13656
13657 exidx_sec = arm_data->u.text.arm_exidx_sec;
13658 if (exidx_sec == NULL)
13659 {
13660 /* Section has no unwind data. */
13661 if (last_unwind_type == 0 || !last_exidx_sec)
13662 continue;
13663
13664 /* Ignore zero sized sections. */
13665 if (sec->size == 0)
13666 continue;
13667
13668 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13669 last_unwind_type = 0;
13670 continue;
13671 }
13672
22a8f80e
PB		 13673 /* Skip /DISCARD/ sections. */
13674 if (bfd_is_abs_section (exidx_sec->output_section))
13675 continue;
13676
2468f9c9
PB		 13677 hdr = &elf_section_data (exidx_sec)->this_hdr;
13678 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 13679 continue;
b38cadfb 13680
2468f9c9
PB		 13681 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13682 if (exidx_arm_data == NULL)
99059e56 13683 continue;
b38cadfb 13684
2468f9c9 13685 ibfd = exidx_sec->owner;
b38cadfb 13686
2468f9c9
PB		 13687 if (hdr->contents != NULL)
13688 contents = hdr->contents;
13689 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
13690 /* An error? */
13691 continue;
13692
ac06903d
YU		 13693 if (last_unwind_type > 0)
13694 {
13695 unsigned int first_word = bfd_get_32 (ibfd, contents);
13696 /* Add cantunwind if first unwind item does not match section
13697 start. */
13698 if (first_word != sec->vma)
13699 {
13700 insert_cantunwind_after (last_text_sec, last_exidx_sec);
13701 last_unwind_type = 0;
13702 }
13703 }
13704
2468f9c9
PB		 13705 for (j = 0; j < hdr->sh_size; j += 8)
13706 {
13707 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
13708 int unwind_type;
13709 int elide = 0;
13710
13711 /* An EXIDX_CANTUNWIND entry. */
13712 if (second_word == 1)
13713 {
13714 if (last_unwind_type == 0)
13715 elide = 1;
13716 unwind_type = 0;
13717 }
13718 /* Inlined unwinding data. Merge if equal to previous. */
13719 else if ((second_word & 0x80000000) != 0)
13720 {
85fdf906
AH		 13721 if (merge_exidx_entries
13722 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 13723 elide = 1;
13724 unwind_type = 1;
13725 last_second_word = second_word;
13726 }
13727 /* Normal table entry. In theory we could merge these too,
13728 but duplicate entries are likely to be much less common. */
13729 else
13730 unwind_type = 2;
13731
491d01d3 13732 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 13733 {
13734 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
13735 DELETE_EXIDX_ENTRY, NULL, j / 8);
13736
13737 deleted_exidx_bytes += 8;
13738 }
13739
13740 last_unwind_type = unwind_type;
13741 }
13742
13743 /* Free contents if we allocated it ourselves. */
13744 if (contents != hdr->contents)
99059e56 13745 free (contents);
2468f9c9
PB		 13746
13747 /* Record edits to be applied later (in elf32_arm_write_section). */
13748 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
13749 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 13750
2468f9c9
PB		 13751 if (deleted_exidx_bytes > 0)
13752 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
13753
13754 last_exidx_sec = exidx_sec;
13755 last_text_sec = sec;
13756 }
13757
13758 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 13759 if (!bfd_link_relocatable (info) && last_exidx_sec
13760 && last_unwind_type != 0)
2468f9c9
PB		 13761 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13762
13763 return TRUE;
13764}
13765
3e6b1042
DJ		 13766static bfd_boolean
13767elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
13768 bfd *ibfd, const char *name)
13769{
13770 asection *sec, *osec;
13771
3d4d4302 13772 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 13773 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
13774 return TRUE;
13775
13776 osec = sec->output_section;
13777 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
13778 return TRUE;
13779
13780 if (! bfd_set_section_contents (obfd, osec, sec->contents,
13781 sec->output_offset, sec->size))
13782 return FALSE;
13783
13784 return TRUE;
13785}
13786
13787static bfd_boolean
13788elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
13789{
13790 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 13791 asection *sec, *osec;
3e6b1042 13792
4dfe6ac6
NC		 13793 if (globals == NULL)
13794 return FALSE;
13795
3e6b1042
DJ		 13796 /* Invoke the regular ELF backend linker to do all the work. */
13797 if (!bfd_elf_final_link (abfd, info))
13798 return FALSE;
13799
fe33d2fa
CL		 13800 /* Process stub sections (eg BE8 encoding, ...). */
13801 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 13802 unsigned int i;
cdb21a0a
NS		 13803 for (i=0; i<htab->top_id; i++)
13804 {
13805 sec = htab->stub_group[i].stub_sec;
13806 /* Only process it once, in its link_sec slot. */
13807 if (sec && i == htab->stub_group[i].link_sec->id)
13808 {
13809 osec = sec->output_section;
13810 elf32_arm_write_section (abfd, info, sec, sec->contents);
13811 if (! bfd_set_section_contents (abfd, osec, sec->contents,
13812 sec->output_offset, sec->size))
13813 return FALSE;
13814 }
fe33d2fa 13815 }
fe33d2fa 13816
3e6b1042
DJ		 13817 /* Write out any glue sections now that we have created all the
13818 stubs. */
13819 if (globals->bfd_of_glue_owner != NULL)
13820 {
13821 if (! elf32_arm_output_glue_section (info, abfd,
13822 globals->bfd_of_glue_owner,
13823 ARM2THUMB_GLUE_SECTION_NAME))
13824 return FALSE;
13825
13826 if (! elf32_arm_output_glue_section (info, abfd,
13827 globals->bfd_of_glue_owner,
13828 THUMB2ARM_GLUE_SECTION_NAME))
13829 return FALSE;
13830
13831 if (! elf32_arm_output_glue_section (info, abfd,
13832 globals->bfd_of_glue_owner,
13833 VFP11_ERRATUM_VENEER_SECTION_NAME))
13834 return FALSE;
13835
a504d23a
LA		 13836 if (! elf32_arm_output_glue_section (info, abfd,
13837 globals->bfd_of_glue_owner,
13838 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13839 return FALSE;
13840
3e6b1042
DJ		 13841 if (! elf32_arm_output_glue_section (info, abfd,
13842 globals->bfd_of_glue_owner,
13843 ARM_BX_GLUE_SECTION_NAME))
13844 return FALSE;
13845 }
13846
13847 return TRUE;
13848}
13849
5968a7b8
NC		 13850/* Return a best guess for the machine number based on the attributes. */
13851
13852static unsigned int
13853bfd_arm_get_mach_from_attributes (bfd * abfd)
13854{
13855 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
13856
13857 switch (arch)
13858 {
c0c468d5 13859 case TAG_CPU_ARCH_PRE_V4: return bfd_mach_arm_3M;
5968a7b8
NC		 13860 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
13861 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
13862 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
13863
13864 case TAG_CPU_ARCH_V5TE:
13865 {
13866 char * name;
13867
13868 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
13869 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
13870
13871 if (name)
13872 {
13873 if (strcmp (name, "IWMMXT2") == 0)
13874 return bfd_mach_arm_iWMMXt2;
13875
13876 if (strcmp (name, "IWMMXT") == 0)
6034aab8 13877 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 13878
13879 if (strcmp (name, "XSCALE") == 0)
13880 {
13881 int wmmx;
13882
13883 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
13884 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
13885 switch (wmmx)
13886 {
13887 case 1: return bfd_mach_arm_iWMMXt;
13888 case 2: return bfd_mach_arm_iWMMXt2;
13889 default: return bfd_mach_arm_XScale;
13890 }
13891 }
5968a7b8
NC		 13892 }
13893
13894 return bfd_mach_arm_5TE;
13895 }
13896
c0c468d5
TP		 13897 case TAG_CPU_ARCH_V5TEJ:
13898 return bfd_mach_arm_5TEJ;
13899 case TAG_CPU_ARCH_V6:
13900 return bfd_mach_arm_6;
13901 case TAG_CPU_ARCH_V6KZ:
13902 return bfd_mach_arm_6KZ;
13903 case TAG_CPU_ARCH_V6T2:
13904 return bfd_mach_arm_6T2;
13905 case TAG_CPU_ARCH_V6K:
13906 return bfd_mach_arm_6K;
13907 case TAG_CPU_ARCH_V7:
13908 return bfd_mach_arm_7;
13909 case TAG_CPU_ARCH_V6_M:
13910 return bfd_mach_arm_6M;
13911 case TAG_CPU_ARCH_V6S_M:
13912 return bfd_mach_arm_6SM;
13913 case TAG_CPU_ARCH_V7E_M:
13914 return bfd_mach_arm_7EM;
13915 case TAG_CPU_ARCH_V8:
13916 return bfd_mach_arm_8;
13917 case TAG_CPU_ARCH_V8R:
13918 return bfd_mach_arm_8R;
13919 case TAG_CPU_ARCH_V8M_BASE:
13920 return bfd_mach_arm_8M_BASE;
13921 case TAG_CPU_ARCH_V8M_MAIN:
13922 return bfd_mach_arm_8M_MAIN;
031254f2
AV		 13923 case TAG_CPU_ARCH_V8_1M_MAIN:
13924 return bfd_mach_arm_8_1M_MAIN;
c0c468d5 13925
5968a7b8 13926 default:
c0c468d5
TP		 13927 /* Force entry to be added for any new known Tag_CPU_arch value. */
13928 BFD_ASSERT (arch > MAX_TAG_CPU_ARCH);
13929
13930 /* Unknown Tag_CPU_arch value. */
5968a7b8
NC		 13931 return bfd_mach_arm_unknown;
13932 }
13933}
13934
c178919b
NC		 13935/* Set the right machine number. */
13936
13937static bfd_boolean
57e8b36a 13938elf32_arm_object_p (bfd *abfd)
c178919b 13939{
5a6c6817 13940 unsigned int mach;
57e8b36a 13941
5a6c6817 13942 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 13943
5968a7b8
NC		 13944 if (mach == bfd_mach_arm_unknown)
13945 {
13946 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13947 mach = bfd_mach_arm_ep9312;
13948 else
13949 mach = bfd_arm_get_mach_from_attributes (abfd);
13950 }
c178919b 13951
5968a7b8 13952 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13953 return TRUE;
13954}
13955
fc830a83 13956/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13957
b34976b6 13958static bfd_boolean
57e8b36a 13959elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13960{
13961 if (elf_flags_init (abfd)
13962 && elf_elfheader (abfd)->e_flags != flags)
13963 {
fc830a83
NC		 13964 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13965 {
fd2ec330 13966 if (flags & EF_ARM_INTERWORK)
4eca0228 13967 _bfd_error_handler
90b6238f 13968 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
d003868e 13969 abfd);
fc830a83 13970 else
d003868e 13971 _bfd_error_handler
90b6238f 13972 (_("warning: clearing the interworking flag of %pB due to outside request"),
d003868e 13973 abfd);
fc830a83 13974 }
252b5132
RH		 13975 }
13976 else
13977 {
13978 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13979 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13980 }
13981
b34976b6 13982 return TRUE;
252b5132
RH		 13983}
13984
fc830a83 13985/* Copy backend specific data from one object module to another. */
9b485d32 13986
b34976b6 13987static bfd_boolean
57e8b36a 13988elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13989{
13990 flagword in_flags;
13991 flagword out_flags;
13992
0ffa91dd 13993 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13994 return TRUE;
252b5132 13995
fc830a83 13996 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13997 out_flags = elf_elfheader (obfd)->e_flags;
13998
fc830a83
NC		 13999 if (elf_flags_init (obfd)
14000 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
14001 && in_flags != out_flags)
252b5132 14002 {
252b5132 14003 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 14004 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 14005 return FALSE;
252b5132
RH		 14006
14007 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 14008 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 14009 return FALSE;
252b5132
RH		 14010
14011 /* If the src and dest have different interworking flags
99059e56 14012 then turn off the interworking bit. */
fd2ec330 14013 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 14014 {
fd2ec330 14015 if (out_flags & EF_ARM_INTERWORK)
d003868e 14016 _bfd_error_handler
90b6238f 14017 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
d003868e 14018 obfd, ibfd);
252b5132 14019
fd2ec330 14020 in_flags &= ~EF_ARM_INTERWORK;
252b5132 14021 }
1006ba19
PB		 14022
14023 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 14024 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
14025 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 14026 }
14027
14028 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 14029 elf_flags_init (obfd) = TRUE;
252b5132 14030
e2349352 14031 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 14032}
14033
14034/* Values for Tag_ABI_PCS_R9_use. */
14035enum
14036{
14037 AEABI_R9_V6,
14038 AEABI_R9_SB,
14039 AEABI_R9_TLS,
14040 AEABI_R9_unused
14041};
14042
14043/* Values for Tag_ABI_PCS_RW_data. */
14044enum
14045{
14046 AEABI_PCS_RW_data_absolute,
14047 AEABI_PCS_RW_data_PCrel,
14048 AEABI_PCS_RW_data_SBrel,
14049 AEABI_PCS_RW_data_unused
14050};
14051
14052/* Values for Tag_ABI_enum_size. */
14053enum
14054{
14055 AEABI_enum_unused,
14056 AEABI_enum_short,
14057 AEABI_enum_wide,
14058 AEABI_enum_forced_wide
14059};
14060
104d59d1
JM		 14061/* Determine whether an object attribute tag takes an integer, a
14062 string or both. */
906e58ca 14063
104d59d1
JM		 14064static int
14065elf32_arm_obj_attrs_arg_type (int tag)
14066{
14067 if (tag == Tag_compatibility)
3483fe2e 14068 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 14069 else if (tag == Tag_nodefaults)
3483fe2e
AS		 14070 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
14071 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
14072 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 14073 else if (tag < 32)
3483fe2e 14074 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 14075 else
3483fe2e 14076 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 14077}
14078
5aa6ff7c
AS		 14079/* The ABI defines that Tag_conformance should be emitted first, and that
14080 Tag_nodefaults should be second (if either is defined). This sets those
14081 two positions, and bumps up the position of all the remaining tags to
14082 compensate. */
14083static int
14084elf32_arm_obj_attrs_order (int num)
14085{
3de4a297 14086 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 14087 return Tag_conformance;
3de4a297 14088 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 14089 return Tag_nodefaults;
14090 if ((num - 2) < Tag_nodefaults)
14091 return num - 2;
14092 if ((num - 1) < Tag_conformance)
14093 return num - 1;
14094 return num;
14095}
14096
e8b36cd1
JM		 14097/* Attribute numbers >=64 (mod 128) can be safely ignored. */
14098static bfd_boolean
14099elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
14100{
14101 if ((tag & 127) < 64)
14102 {
14103 _bfd_error_handler
90b6238f 14104 (_("%pB: unknown mandatory EABI object attribute %d"),
e8b36cd1
JM		 14105 abfd, tag);
14106 bfd_set_error (bfd_error_bad_value);
14107 return FALSE;
14108 }
14109 else
14110 {
14111 _bfd_error_handler
90b6238f 14112 (_("warning: %pB: unknown EABI object attribute %d"),
e8b36cd1
JM		 14113 abfd, tag);
14114 return TRUE;
14115 }
14116}
14117
91e22acd
AS		 14118/* Read the architecture from the Tag_also_compatible_with attribute, if any.
14119 Returns -1 if no architecture could be read. */
14120
14121static int
14122get_secondary_compatible_arch (bfd *abfd)
14123{
14124 obj_attribute *attr =
14125 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
14126
14127 /* Note: the tag and its argument below are uleb128 values, though
14128 currently-defined values fit in one byte for each. */
14129 if (attr->s
14130 && attr->s[0] == Tag_CPU_arch
14131 && (attr->s[1] & 128) != 128
14132 && attr->s[2] == 0)
14133 return attr->s[1];
14134
14135 /* This tag is "safely ignorable", so don't complain if it looks funny. */
14136 return -1;
14137}
14138
14139/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
14140 The tag is removed if ARCH is -1. */
14141
8e79c3df 14142static void
91e22acd 14143set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 14144{
91e22acd
AS		 14145 obj_attribute *attr =
14146 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 14147
91e22acd
AS		 14148 if (arch == -1)
14149 {
14150 attr->s = NULL;
14151 return;
8e79c3df 14152 }
91e22acd
AS		 14153
14154 /* Note: the tag and its argument below are uleb128 values, though
14155 currently-defined values fit in one byte for each. */
14156 if (!attr->s)
21d799b5 14157 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 14158 attr->s[0] = Tag_CPU_arch;
14159 attr->s[1] = arch;
14160 attr->s[2] = '\0';
8e79c3df
CM		 14161}
14162
91e22acd
AS		 14163/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
14164 into account. */
14165
14166static int
14167tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
14168 int newtag, int secondary_compat)
8e79c3df 14169{
91e22acd
AS		 14170#define T(X) TAG_CPU_ARCH_##X
14171 int tagl, tagh, result;
14172 const int v6t2[] =
14173 {
14174 T(V6T2), /* PRE_V4. */
14175 T(V6T2), /* V4. */
14176 T(V6T2), /* V4T. */
14177 T(V6T2), /* V5T. */
14178 T(V6T2), /* V5TE. */
14179 T(V6T2), /* V5TEJ. */
14180 T(V6T2), /* V6. */
14181 T(V7), /* V6KZ. */
14182 T(V6T2) /* V6T2. */
14183 };
14184 const int v6k[] =
14185 {
14186 T(V6K), /* PRE_V4. */
14187 T(V6K), /* V4. */
14188 T(V6K), /* V4T. */
14189 T(V6K), /* V5T. */
14190 T(V6K), /* V5TE. */
14191 T(V6K), /* V5TEJ. */
14192 T(V6K), /* V6. */
14193 T(V6KZ), /* V6KZ. */
14194 T(V7), /* V6T2. */
14195 T(V6K) /* V6K. */
14196 };
14197 const int v7[] =
14198 {
14199 T(V7), /* PRE_V4. */
14200 T(V7), /* V4. */
14201 T(V7), /* V4T. */
14202 T(V7), /* V5T. */
14203 T(V7), /* V5TE. */
14204 T(V7), /* V5TEJ. */
14205 T(V7), /* V6. */
14206 T(V7), /* V6KZ. */
14207 T(V7), /* V6T2. */
14208 T(V7), /* V6K. */
14209 T(V7) /* V7. */
14210 };
14211 const int v6_m[] =
14212 {
07d6d2b8
AM		 14213 -1, /* PRE_V4. */
14214 -1, /* V4. */
91e22acd
AS		 14215 T(V6K), /* V4T. */
14216 T(V6K), /* V5T. */
14217 T(V6K), /* V5TE. */
14218 T(V6K), /* V5TEJ. */
14219 T(V6K), /* V6. */
14220 T(V6KZ), /* V6KZ. */
14221 T(V7), /* V6T2. */
14222 T(V6K), /* V6K. */
14223 T(V7), /* V7. */
14224 T(V6_M) /* V6_M. */
14225 };
14226 const int v6s_m[] =
14227 {
07d6d2b8
AM		 14228 -1, /* PRE_V4. */
14229 -1, /* V4. */
91e22acd
AS		 14230 T(V6K), /* V4T. */
14231 T(V6K), /* V5T. */
14232 T(V6K), /* V5TE. */
14233 T(V6K), /* V5TEJ. */
14234 T(V6K), /* V6. */
14235 T(V6KZ), /* V6KZ. */
14236 T(V7), /* V6T2. */
14237 T(V6K), /* V6K. */
14238 T(V7), /* V7. */
14239 T(V6S_M), /* V6_M. */
14240 T(V6S_M) /* V6S_M. */
14241 };
9e3c6df6
PB		 14242 const int v7e_m[] =
14243 {
07d6d2b8
AM		 14244 -1, /* PRE_V4. */
14245 -1, /* V4. */
9e3c6df6
PB		 14246 T(V7E_M), /* V4T. */
14247 T(V7E_M), /* V5T. */
14248 T(V7E_M), /* V5TE. */
14249 T(V7E_M), /* V5TEJ. */
14250 T(V7E_M), /* V6. */
14251 T(V7E_M), /* V6KZ. */
14252 T(V7E_M), /* V6T2. */
14253 T(V7E_M), /* V6K. */
14254 T(V7E_M), /* V7. */
14255 T(V7E_M), /* V6_M. */
14256 T(V7E_M), /* V6S_M. */
14257 T(V7E_M) /* V7E_M. */
14258 };
bca38921
MGD		 14259 const int v8[] =
14260 {
14261 T(V8), /* PRE_V4. */
14262 T(V8), /* V4. */
14263 T(V8), /* V4T. */
14264 T(V8), /* V5T. */
14265 T(V8), /* V5TE. */
14266 T(V8), /* V5TEJ. */
14267 T(V8), /* V6. */
14268 T(V8), /* V6KZ. */
14269 T(V8), /* V6T2. */
14270 T(V8), /* V6K. */
14271 T(V8), /* V7. */
14272 T(V8), /* V6_M. */
14273 T(V8), /* V6S_M. */
14274 T(V8), /* V7E_M. */
14275 T(V8) /* V8. */
14276 };
bff0500d
TP		 14277 const int v8r[] =
14278 {
14279 T(V8R), /* PRE_V4. */
14280 T(V8R), /* V4. */
14281 T(V8R), /* V4T. */
14282 T(V8R), /* V5T. */
14283 T(V8R), /* V5TE. */
14284 T(V8R), /* V5TEJ. */
14285 T(V8R), /* V6. */
14286 T(V8R), /* V6KZ. */
14287 T(V8R), /* V6T2. */
14288 T(V8R), /* V6K. */
14289 T(V8R), /* V7. */
14290 T(V8R), /* V6_M. */
14291 T(V8R), /* V6S_M. */
14292 T(V8R), /* V7E_M. */
14293 T(V8), /* V8. */
14294 T(V8R), /* V8R. */
14295 };
2fd158eb
TP		 14296 const int v8m_baseline[] =
14297 {
14298 -1, /* PRE_V4. */
14299 -1, /* V4. */
14300 -1, /* V4T. */
14301 -1, /* V5T. */
14302 -1, /* V5TE. */
14303 -1, /* V5TEJ. */
14304 -1, /* V6. */
14305 -1, /* V6KZ. */
14306 -1, /* V6T2. */
14307 -1, /* V6K. */
14308 -1, /* V7. */
14309 T(V8M_BASE), /* V6_M. */
14310 T(V8M_BASE), /* V6S_M. */
14311 -1, /* V7E_M. */
14312 -1, /* V8. */
bff0500d 14313 -1, /* V8R. */
2fd158eb
TP		 14314 T(V8M_BASE) /* V8-M BASELINE. */
14315 };
14316 const int v8m_mainline[] =
14317 {
14318 -1, /* PRE_V4. */
14319 -1, /* V4. */
14320 -1, /* V4T. */
14321 -1, /* V5T. */
14322 -1, /* V5TE. */
14323 -1, /* V5TEJ. */
14324 -1, /* V6. */
14325 -1, /* V6KZ. */
14326 -1, /* V6T2. */
14327 -1, /* V6K. */
14328 T(V8M_MAIN), /* V7. */
14329 T(V8M_MAIN), /* V6_M. */
14330 T(V8M_MAIN), /* V6S_M. */
14331 T(V8M_MAIN), /* V7E_M. */
14332 -1, /* V8. */
bff0500d 14333 -1, /* V8R. */
2fd158eb
TP		 14334 T(V8M_MAIN), /* V8-M BASELINE. */
14335 T(V8M_MAIN) /* V8-M MAINLINE. */
14336 };
031254f2
AV		 14337 const int v8_1m_mainline[] =
14338 {
14339 -1, /* PRE_V4. */
14340 -1, /* V4. */
14341 -1, /* V4T. */
14342 -1, /* V5T. */
14343 -1, /* V5TE. */
14344 -1, /* V5TEJ. */
14345 -1, /* V6. */
14346 -1, /* V6KZ. */
14347 -1, /* V6T2. */
14348 -1, /* V6K. */
14349 T(V8_1M_MAIN), /* V7. */
14350 T(V8_1M_MAIN), /* V6_M. */
14351 T(V8_1M_MAIN), /* V6S_M. */
14352 T(V8_1M_MAIN), /* V7E_M. */
14353 -1, /* V8. */
14354 -1, /* V8R. */
14355 T(V8_1M_MAIN), /* V8-M BASELINE. */
14356 T(V8_1M_MAIN), /* V8-M MAINLINE. */
14357 -1, /* Unused (18). */
14358 -1, /* Unused (19). */
14359 -1, /* Unused (20). */
14360 T(V8_1M_MAIN) /* V8.1-M MAINLINE. */
14361 };
91e22acd
AS		 14362 const int v4t_plus_v6_m[] =
14363 {
14364 -1, /* PRE_V4. */
14365 -1, /* V4. */
14366 T(V4T), /* V4T. */
14367 T(V5T), /* V5T. */
14368 T(V5TE), /* V5TE. */
14369 T(V5TEJ), /* V5TEJ. */
14370 T(V6), /* V6. */
14371 T(V6KZ), /* V6KZ. */
14372 T(V6T2), /* V6T2. */
14373 T(V6K), /* V6K. */
14374 T(V7), /* V7. */
14375 T(V6_M), /* V6_M. */
14376 T(V6S_M), /* V6S_M. */
9e3c6df6 14377 T(V7E_M), /* V7E_M. */
bca38921 14378 T(V8), /* V8. */
bff0500d 14379 -1, /* V8R. */
2fd158eb
TP		 14380 T(V8M_BASE), /* V8-M BASELINE. */
14381 T(V8M_MAIN), /* V8-M MAINLINE. */
031254f2
AV		 14382 -1, /* Unused (18). */
14383 -1, /* Unused (19). */
14384 -1, /* Unused (20). */
14385 T(V8_1M_MAIN), /* V8.1-M MAINLINE. */
91e22acd
AS		 14386 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
14387 };
14388 const int *comb[] =
14389 {
14390 v6t2,
14391 v6k,
14392 v7,
14393 v6_m,
14394 v6s_m,
9e3c6df6 14395 v7e_m,
bca38921 14396 v8,
bff0500d 14397 v8r,
2fd158eb
TP		 14398 v8m_baseline,
14399 v8m_mainline,
031254f2
AV		 14400 NULL,
14401 NULL,
14402 NULL,
14403 v8_1m_mainline,
91e22acd
AS		 14404 /* Pseudo-architecture. */
14405 v4t_plus_v6_m
14406 };
14407
14408 /* Check we've not got a higher architecture than we know about. */
14409
9e3c6df6 14410 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 14411 {
90b6238f 14412 _bfd_error_handler (_("error: %pB: unknown CPU architecture"), ibfd);
91e22acd
AS		 14413 return -1;
14414 }
14415
14416 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14417
14418 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
14419 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
14420 oldtag = T(V4T_PLUS_V6_M);
14421
14422 /* And override the new tag if we have a Tag_also_compatible_with on the
14423 input. */
14424
14425 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
14426 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
14427 newtag = T(V4T_PLUS_V6_M);
14428
14429 tagl = (oldtag < newtag) ? oldtag : newtag;
14430 result = tagh = (oldtag > newtag) ? oldtag : newtag;
14431
14432 /* Architectures before V6KZ add features monotonically. */
14433 if (tagh <= TAG_CPU_ARCH_V6KZ)
14434 return result;
14435
4ed7ed8d 14436 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 14437
14438 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14439 as the canonical version. */
14440 if (result == T(V4T_PLUS_V6_M))
14441 {
14442 result = T(V4T);
14443 *secondary_compat_out = T(V6_M);
14444 }
14445 else
14446 *secondary_compat_out = -1;
14447
14448 if (result == -1)
14449 {
90b6238f 14450 _bfd_error_handler (_("error: %pB: conflicting CPU architectures %d/%d"),
91e22acd
AS		 14451 ibfd, oldtag, newtag);
14452 return -1;
14453 }
14454
14455 return result;
14456#undef T
8e79c3df
CM		 14457}
14458
ac56ee8f
MGD		 14459/* Query attributes object to see if integer divide instructions may be
14460 present in an object. */
14461static bfd_boolean
14462elf32_arm_attributes_accept_div (const obj_attribute *attr)
14463{
14464 int arch = attr[Tag_CPU_arch].i;
14465 int profile = attr[Tag_CPU_arch_profile].i;
14466
14467 switch (attr[Tag_DIV_use].i)
14468 {
14469 case 0:
14470 /* Integer divide allowed if instruction contained in archetecture. */
14471 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
14472 return TRUE;
14473 else if (arch >= TAG_CPU_ARCH_V7E_M)
14474 return TRUE;
14475 else
14476 return FALSE;
14477
14478 case 1:
14479 /* Integer divide explicitly prohibited. */
14480 return FALSE;
14481
14482 default:
14483 /* Unrecognised case - treat as allowing divide everywhere. */
14484 case 2:
14485 /* Integer divide allowed in ARM state. */
14486 return TRUE;
14487 }
14488}
14489
14490/* Query attributes object to see if integer divide instructions are
14491 forbidden to be in the object. This is not the inverse of
14492 elf32_arm_attributes_accept_div. */
14493static bfd_boolean
14494elf32_arm_attributes_forbid_div (const obj_attribute *attr)
14495{
14496 return attr[Tag_DIV_use].i == 1;
14497}
14498
ee065d83
PB		 14499/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14500 are conflicting attributes. */
906e58ca 14501
ee065d83 14502static bfd_boolean
50e03d47 14503elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 14504{
50e03d47 14505 bfd *obfd = info->output_bfd;
104d59d1
JM		 14506 obj_attribute *in_attr;
14507 obj_attribute *out_attr;
ee065d83
PB		 14508 /* Some tags have 0 = don't care, 1 = strong requirement,
14509 2 = weak requirement. */
91e22acd 14510 static const int order_021[3] = {0, 2, 1};
ee065d83 14511 int i;
91e22acd 14512 bfd_boolean result = TRUE;
9274e9de 14513 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 14514
3e6b1042
DJ		 14515 /* Skip the linker stubs file. This preserves previous behavior
14516 of accepting unknown attributes in the first input file - but
14517 is that a bug? */
14518 if (ibfd->flags & BFD_LINKER_CREATED)
14519 return TRUE;
14520
9274e9de
TG		 14521 /* Skip any input that hasn't attribute section.
14522 This enables to link object files without attribute section with
14523 any others. */
14524 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
14525 return TRUE;
14526
104d59d1 14527 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 14528 {
14529 /* This is the first object. Copy the attributes. */
104d59d1 14530 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 14531
cd21e546
MGD		 14532 out_attr = elf_known_obj_attributes_proc (obfd);
14533
004ae526
PB		 14534 /* Use the Tag_null value to indicate the attributes have been
14535 initialized. */
cd21e546 14536 out_attr[0].i = 1;
004ae526 14537
cd21e546
MGD		 14538 /* We do not output objects with Tag_MPextension_use_legacy - we move
14539 the attribute's value to Tag_MPextension_use. */
14540 if (out_attr[Tag_MPextension_use_legacy].i != 0)
14541 {
14542 if (out_attr[Tag_MPextension_use].i != 0
14543 && out_attr[Tag_MPextension_use_legacy].i
99059e56 14544 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 14545 {
14546 _bfd_error_handler
871b3ab2 14547 (_("Error: %pB has both the current and legacy "
cd21e546
MGD		 14548 "Tag_MPextension_use attributes"), ibfd);
14549 result = FALSE;
14550 }
14551
14552 out_attr[Tag_MPextension_use] =
14553 out_attr[Tag_MPextension_use_legacy];
14554 out_attr[Tag_MPextension_use_legacy].type = 0;
14555 out_attr[Tag_MPextension_use_legacy].i = 0;
14556 }
14557
14558 return result;
ee065d83
PB		 14559 }
14560
104d59d1
JM		 14561 in_attr = elf_known_obj_attributes_proc (ibfd);
14562 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 14563 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14564 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
14565 {
5c294fee
TG		 14566 /* Ignore mismatches if the object doesn't use floating point or is
14567 floating point ABI independent. */
14568 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
14569 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14570 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 14571 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 14572 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14573 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 14574 {
14575 _bfd_error_handler
871b3ab2 14576 (_("error: %pB uses VFP register arguments, %pB does not"),
deddc40b
NS		 14577 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
14578 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 14579 result = FALSE;
ee065d83
PB		 14580 }
14581 }
14582
3de4a297 14583 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 14584 {
14585 /* Merge this attribute with existing attributes. */
14586 switch (i)
14587 {
14588 case Tag_CPU_raw_name:
14589 case Tag_CPU_name:
6a631e86 14590 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 14591 break;
14592
14593 case Tag_ABI_optimization_goals:
14594 case Tag_ABI_FP_optimization_goals:
14595 /* Use the first value seen. */
14596 break;
14597
14598 case Tag_CPU_arch:
91e22acd
AS		 14599 {
14600 int secondary_compat = -1, secondary_compat_out = -1;
14601 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 14602 int arch_attr;
14603 static const char *name_table[] =
14604 {
91e22acd
AS		 14605 /* These aren't real CPU names, but we can't guess
14606 that from the architecture version alone. */
14607 "Pre v4",
14608 "ARM v4",
14609 "ARM v4T",
14610 "ARM v5T",
14611 "ARM v5TE",
14612 "ARM v5TEJ",
14613 "ARM v6",
14614 "ARM v6KZ",
14615 "ARM v6T2",
14616 "ARM v6K",
14617 "ARM v7",
14618 "ARM v6-M",
bca38921 14619 "ARM v6S-M",
2fd158eb
TP		 14620 "ARM v8",
14621 "",
14622 "ARM v8-M.baseline",
14623 "ARM v8-M.mainline",
91e22acd
AS		 14624 };
14625
14626 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14627 secondary_compat = get_secondary_compatible_arch (ibfd);
14628 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 14629 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
14630 &secondary_compat_out,
14631 in_attr[i].i,
14632 secondary_compat);
14633
14634 /* Return with error if failed to merge. */
14635 if (arch_attr == -1)
14636 return FALSE;
14637
14638 out_attr[i].i = arch_attr;
14639
91e22acd
AS		 14640 set_secondary_compatible_arch (obfd, secondary_compat_out);
14641
14642 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14643 if (out_attr[i].i == saved_out_attr)
14644 ; /* Leave the names alone. */
14645 else if (out_attr[i].i == in_attr[i].i)
14646 {
14647 /* The output architecture has been changed to match the
14648 input architecture. Use the input names. */
14649 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
14650 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
14651 : NULL;
14652 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
14653 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
14654 : NULL;
14655 }
14656 else
14657 {
14658 out_attr[Tag_CPU_name].s = NULL;
14659 out_attr[Tag_CPU_raw_name].s = NULL;
14660 }
14661
14662 /* If we still don't have a value for Tag_CPU_name,
14663 make one up now. Tag_CPU_raw_name remains blank. */
14664 if (out_attr[Tag_CPU_name].s == NULL
14665 && out_attr[i].i < ARRAY_SIZE (name_table))
14666 out_attr[Tag_CPU_name].s =
14667 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
14668 }
14669 break;
14670
ee065d83
PB		 14671 case Tag_ARM_ISA_use:
14672 case Tag_THUMB_ISA_use:
ee065d83 14673 case Tag_WMMX_arch:
91e22acd
AS		 14674 case Tag_Advanced_SIMD_arch:
14675 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 14676 case Tag_ABI_FP_rounding:
ee065d83
PB		 14677 case Tag_ABI_FP_exceptions:
14678 case Tag_ABI_FP_user_exceptions:
14679 case Tag_ABI_FP_number_model:
75375b3e 14680 case Tag_FP_HP_extension:
91e22acd
AS		 14681 case Tag_CPU_unaligned_access:
14682 case Tag_T2EE_use:
91e22acd 14683 case Tag_MPextension_use:
a7ad558c 14684 case Tag_MVE_arch:
ee065d83
PB		 14685 /* Use the largest value specified. */
14686 if (in_attr[i].i > out_attr[i].i)
14687 out_attr[i].i = in_attr[i].i;
14688 break;
14689
75375b3e 14690 case Tag_ABI_align_preserved:
91e22acd
AS		 14691 case Tag_ABI_PCS_RO_data:
14692 /* Use the smallest value specified. */
14693 if (in_attr[i].i < out_attr[i].i)
14694 out_attr[i].i = in_attr[i].i;
14695 break;
14696
75375b3e 14697 case Tag_ABI_align_needed:
91e22acd 14698 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 14699 && (in_attr[Tag_ABI_align_preserved].i == 0
14700 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 14701 {
91e22acd
AS		 14702 /* This error message should be enabled once all non-conformant
14703 binaries in the toolchain have had the attributes set
14704 properly.
ee065d83 14705 _bfd_error_handler
871b3ab2 14706 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
91e22acd
AS		 14707 obfd, ibfd);
14708 result = FALSE; */
ee065d83 14709 }
91e22acd
AS		 14710 /* Fall through. */
14711 case Tag_ABI_FP_denormal:
14712 case Tag_ABI_PCS_GOT_use:
14713 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14714 value if greater than 2 (for future-proofing). */
14715 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
14716 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
14717 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 14718 out_attr[i].i = in_attr[i].i;
14719 break;
91e22acd 14720
75375b3e
MGD		 14721 case Tag_Virtualization_use:
14722 /* The virtualization tag effectively stores two bits of
14723 information: the intended use of TrustZone (in bit 0), and the
14724 intended use of Virtualization (in bit 1). */
14725 if (out_attr[i].i == 0)
14726 out_attr[i].i = in_attr[i].i;
14727 else if (in_attr[i].i != 0
14728 && in_attr[i].i != out_attr[i].i)
14729 {
14730 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
14731 out_attr[i].i = 3;
14732 else
14733 {
14734 _bfd_error_handler
871b3ab2
AM		 14735 (_("error: %pB: unable to merge virtualization attributes "
14736 "with %pB"),
75375b3e
MGD		 14737 obfd, ibfd);
14738 result = FALSE;
14739 }
14740 }
14741 break;
91e22acd
AS		 14742
14743 case Tag_CPU_arch_profile:
14744 if (out_attr[i].i != in_attr[i].i)
14745 {
14746 /* 0 will merge with anything.
14747 'A' and 'S' merge to 'A'.
14748 'R' and 'S' merge to 'R'.
99059e56 14749 'M' and 'A|R|S' is an error. */
91e22acd
AS		 14750 if (out_attr[i].i == 0
14751 || (out_attr[i].i == 'S'
14752 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
14753 out_attr[i].i = in_attr[i].i;
14754 else if (in_attr[i].i == 0
14755 || (in_attr[i].i == 'S'
14756 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 14757 ; /* Do nothing. */
91e22acd
AS		 14758 else
14759 {
14760 _bfd_error_handler
90b6238f 14761 (_("error: %pB: conflicting architecture profiles %c/%c"),
91e22acd
AS		 14762 ibfd,
14763 in_attr[i].i ? in_attr[i].i : '0',
14764 out_attr[i].i ? out_attr[i].i : '0');
14765 result = FALSE;
14766 }
14767 }
14768 break;
15afaa63
TP		 14769
14770 case Tag_DSP_extension:
14771 /* No need to change output value if any of:
14772 - pre (<=) ARMv5T input architecture (do not have DSP)
14773 - M input profile not ARMv7E-M and do not have DSP. */
14774 if (in_attr[Tag_CPU_arch].i <= 3
14775 || (in_attr[Tag_CPU_arch_profile].i == 'M'
14776 && in_attr[Tag_CPU_arch].i != 13
14777 && in_attr[i].i == 0))
14778 ; /* Do nothing. */
14779 /* Output value should be 0 if DSP part of architecture, ie.
14780 - post (>=) ARMv5te architecture output
14781 - A, R or S profile output or ARMv7E-M output architecture. */
14782 else if (out_attr[Tag_CPU_arch].i >= 4
14783 && (out_attr[Tag_CPU_arch_profile].i == 'A'
14784 || out_attr[Tag_CPU_arch_profile].i == 'R'
14785 || out_attr[Tag_CPU_arch_profile].i == 'S'
14786 || out_attr[Tag_CPU_arch].i == 13))
14787 out_attr[i].i = 0;
14788 /* Otherwise, DSP instructions are added and not part of output
14789 architecture. */
14790 else
14791 out_attr[i].i = 1;
14792 break;
14793
75375b3e 14794 case Tag_FP_arch:
62f3b8c8 14795 {
4547cb56
NC		 14796 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14797 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14798 when it's 0. It might mean absence of FP hardware if
99654aaf 14799 Tag_FP_arch is zero. */
4547cb56 14800
a715796b 14801#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 14802 static const struct
14803 {
14804 int ver;
14805 int regs;
bca38921 14806 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 14807 {
14808 {0, 0},
14809 {1, 16},
14810 {2, 16},
14811 {3, 32},
14812 {3, 16},
14813 {4, 32},
bca38921 14814 {4, 16},
a715796b
TG		 14815 {8, 32},
14816 {8, 16}
62f3b8c8
PB		 14817 };
14818 int ver;
14819 int regs;
14820 int newval;
14821
4547cb56
NC		 14822 /* If the output has no requirement about FP hardware,
14823 follow the requirement of the input. */
14824 if (out_attr[i].i == 0)
14825 {
4ec192e6
RE		 14826 /* This assert is still reasonable, we shouldn't
14827 produce the suspicious build attribute
14828 combination (See below for in_attr). */
4547cb56
NC		 14829 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
14830 out_attr[i].i = in_attr[i].i;
14831 out_attr[Tag_ABI_HardFP_use].i
14832 = in_attr[Tag_ABI_HardFP_use].i;
14833 break;
14834 }
14835 /* If the input has no requirement about FP hardware, do
14836 nothing. */
14837 else if (in_attr[i].i == 0)
14838 {
4ec192e6
RE		 14839 /* We used to assert that Tag_ABI_HardFP_use was
14840 zero here, but we should never assert when
14841 consuming an object file that has suspicious
14842 build attributes. The single precision variant
14843 of 'no FP architecture' is still 'no FP
14844 architecture', so we just ignore the tag in this
14845 case. */
4547cb56
NC		 14846 break;
14847 }
14848
14849 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 14850 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 14851
14852 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14853 do nothing. */
14854 if (in_attr[Tag_ABI_HardFP_use].i == 0
14855 && out_attr[Tag_ABI_HardFP_use].i == 0)
14856 ;
14857 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 14858 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 14859 else if (in_attr[Tag_ABI_HardFP_use].i
14860 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 14861 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 14862
14863 /* Now we can handle Tag_FP_arch. */
14864
bca38921
MGD		 14865 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14866 pick the biggest. */
14867 if (in_attr[i].i >= VFP_VERSION_COUNT
14868 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 14869 {
14870 out_attr[i] = in_attr[i];
14871 break;
14872 }
14873 /* The output uses the superset of input features
14874 (ISA version) and registers. */
14875 ver = vfp_versions[in_attr[i].i].ver;
14876 if (ver < vfp_versions[out_attr[i].i].ver)
14877 ver = vfp_versions[out_attr[i].i].ver;
14878 regs = vfp_versions[in_attr[i].i].regs;
14879 if (regs < vfp_versions[out_attr[i].i].regs)
14880 regs = vfp_versions[out_attr[i].i].regs;
14881 /* This assumes all possible supersets are also a valid
99059e56 14882 options. */
bca38921 14883 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 14884 {
14885 if (regs == vfp_versions[newval].regs
14886 && ver == vfp_versions[newval].ver)
14887 break;
14888 }
14889 out_attr[i].i = newval;
14890 }
b1cc4aeb 14891 break;
ee065d83
PB		 14892 case Tag_PCS_config:
14893 if (out_attr[i].i == 0)
14894 out_attr[i].i = in_attr[i].i;
b6009aca 14895 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 14896 {
14897 /* It's sometimes ok to mix different configs, so this is only
99059e56 14898 a warning. */
ee065d83 14899 _bfd_error_handler
90b6238f 14900 (_("warning: %pB: conflicting platform configuration"), ibfd);
ee065d83
PB		 14901 }
14902 break;
14903 case Tag_ABI_PCS_R9_use:
004ae526
PB		 14904 if (in_attr[i].i != out_attr[i].i
14905 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 14906 && in_attr[i].i != AEABI_R9_unused)
14907 {
14908 _bfd_error_handler
90b6238f 14909 (_("error: %pB: conflicting use of R9"), ibfd);
91e22acd 14910 result = FALSE;
ee065d83
PB		 14911 }
14912 if (out_attr[i].i == AEABI_R9_unused)
14913 out_attr[i].i = in_attr[i].i;
14914 break;
14915 case Tag_ABI_PCS_RW_data:
14916 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
14917 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
14918 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
14919 {
14920 _bfd_error_handler
871b3ab2 14921 (_("error: %pB: SB relative addressing conflicts with use of R9"),
ee065d83 14922 ibfd);
91e22acd 14923 result = FALSE;
ee065d83
PB		 14924 }
14925 /* Use the smallest value specified. */
14926 if (in_attr[i].i < out_attr[i].i)
14927 out_attr[i].i = in_attr[i].i;
14928 break;
ee065d83 14929 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 14930 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
14931 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 14932 {
14933 _bfd_error_handler
871b3ab2 14934 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
a9dc9481 14935 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 14936 }
a9dc9481 14937 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 14938 out_attr[i].i = in_attr[i].i;
14939 break;
ee065d83
PB		 14940 case Tag_ABI_enum_size:
14941 if (in_attr[i].i != AEABI_enum_unused)
14942 {
14943 if (out_attr[i].i == AEABI_enum_unused
14944 || out_attr[i].i == AEABI_enum_forced_wide)
14945 {
14946 /* The existing object is compatible with anything.
14947 Use whatever requirements the new object has. */
14948 out_attr[i].i = in_attr[i].i;
14949 }
14950 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 14951 && out_attr[i].i != in_attr[i].i
0ffa91dd 14952 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 14953 {
91e22acd 14954 static const char *aeabi_enum_names[] =
bf21ed78 14955 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 14956 const char *in_name =
14957 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14958 ? aeabi_enum_names[in_attr[i].i]
14959 : "<unknown>";
14960 const char *out_name =
14961 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14962 ? aeabi_enum_names[out_attr[i].i]
14963 : "<unknown>";
ee065d83 14964 _bfd_error_handler
871b3ab2 14965 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 14966 ibfd, in_name, out_name);
ee065d83
PB		 14967 }
14968 }
14969 break;
14970 case Tag_ABI_VFP_args:
14971 /* Aready done. */
14972 break;
14973 case Tag_ABI_WMMX_args:
14974 if (in_attr[i].i != out_attr[i].i)
14975 {
14976 _bfd_error_handler
871b3ab2 14977 (_("error: %pB uses iWMMXt register arguments, %pB does not"),
ee065d83 14978 ibfd, obfd);
91e22acd 14979 result = FALSE;
ee065d83
PB		 14980 }
14981 break;
7b86a9fa
AS		 14982 case Tag_compatibility:
14983 /* Merged in target-independent code. */
14984 break;
91e22acd 14985 case Tag_ABI_HardFP_use:
4547cb56 14986 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 14987 break;
14988 case Tag_ABI_FP_16bit_format:
14989 if (in_attr[i].i != 0 && out_attr[i].i != 0)
14990 {
14991 if (in_attr[i].i != out_attr[i].i)
14992 {
14993 _bfd_error_handler
871b3ab2 14994 (_("error: fp16 format mismatch between %pB and %pB"),
91e22acd
AS		 14995 ibfd, obfd);
14996 result = FALSE;
14997 }
14998 }
14999 if (in_attr[i].i != 0)
15000 out_attr[i].i = in_attr[i].i;
15001 break;
7b86a9fa 15002
cd21e546 15003 case Tag_DIV_use:
ac56ee8f
MGD		 15004 /* A value of zero on input means that the divide instruction may
15005 be used if available in the base architecture as specified via
15006 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
15007 the user did not want divide instructions. A value of 2
15008 explicitly means that divide instructions were allowed in ARM
15009 and Thumb state. */
15010 if (in_attr[i].i == out_attr[i].i)
15011 /* Do nothing. */ ;
15012 else if (elf32_arm_attributes_forbid_div (in_attr)
15013 && !elf32_arm_attributes_accept_div (out_attr))
15014 out_attr[i].i = 1;
15015 else if (elf32_arm_attributes_forbid_div (out_attr)
15016 && elf32_arm_attributes_accept_div (in_attr))
15017 out_attr[i].i = in_attr[i].i;
15018 else if (in_attr[i].i == 2)
15019 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 15020 break;
15021
15022 case Tag_MPextension_use_legacy:
15023 /* We don't output objects with Tag_MPextension_use_legacy - we
15024 move the value to Tag_MPextension_use. */
15025 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
15026 {
15027 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
15028 {
15029 _bfd_error_handler
871b3ab2 15030 (_("%pB has both the current and legacy "
b38cadfb 15031 "Tag_MPextension_use attributes"),
cd21e546
MGD		 15032 ibfd);
15033 result = FALSE;
15034 }
15035 }
15036
15037 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
15038 out_attr[Tag_MPextension_use] = in_attr[i];
15039
15040 break;
15041
91e22acd 15042 case Tag_nodefaults:
2d0bb761
AS		 15043 /* This tag is set if it exists, but the value is unused (and is
15044 typically zero). We don't actually need to do anything here -
15045 the merge happens automatically when the type flags are merged
15046 below. */
91e22acd
AS		 15047 break;
15048 case Tag_also_compatible_with:
15049 /* Already done in Tag_CPU_arch. */
15050 break;
15051 case Tag_conformance:
15052 /* Keep the attribute if it matches. Throw it away otherwise.
15053 No attribute means no claim to conform. */
15054 if (!in_attr[i].s || !out_attr[i].s
15055 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
15056 out_attr[i].s = NULL;
15057 break;
3cfad14c 15058
91e22acd 15059 default:
e8b36cd1
JM		 15060 result
15061 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 15062 }
15063
15064 /* If out_attr was copied from in_attr then it won't have a type yet. */
15065 if (in_attr[i].type && !out_attr[i].type)
15066 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 15067 }
15068
104d59d1 15069 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 15070 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 15071 return FALSE;
ee065d83 15072
104d59d1 15073 /* Check for any attributes not known on ARM. */
e8b36cd1 15074 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 15075
91e22acd 15076 return result;
252b5132
RH		 15077}
15078
3a4a14e9
PB		 15079
15080/* Return TRUE if the two EABI versions are incompatible. */
15081
15082static bfd_boolean
15083elf32_arm_versions_compatible (unsigned iver, unsigned over)
15084{
15085 /* v4 and v5 are the same spec before and after it was released,
15086 so allow mixing them. */
15087 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
15088 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
15089 return TRUE;
15090
15091 return (iver == over);
15092}
15093
252b5132
RH		 15094/* Merge backend specific data from an object file to the output
15095 object file when linking. */
9b485d32 15096
b34976b6 15097static bfd_boolean
50e03d47 15098elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 15099
9b485d32
NC		 15100/* Display the flags field. */
15101
b34976b6 15102static bfd_boolean
57e8b36a 15103elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 15104{
fc830a83
NC		 15105 FILE * file = (FILE *) ptr;
15106 unsigned long flags;
252b5132
RH		 15107
15108 BFD_ASSERT (abfd != NULL && ptr != NULL);
15109
15110 /* Print normal ELF private data. */
15111 _bfd_elf_print_private_bfd_data (abfd, ptr);
15112
fc830a83 15113 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 15114 /* Ignore init flag - it may not be set, despite the flags field
15115 containing valid data. */
252b5132 15116
9b485d32 15117 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 15118
fc830a83
NC		 15119 switch (EF_ARM_EABI_VERSION (flags))
15120 {
15121 case EF_ARM_EABI_UNKNOWN:
4cc11e76 15122 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 15123 official ARM ELF extended ABI. Hence they are only decoded if
15124 the EABI version is not set. */
fd2ec330 15125 if (flags & EF_ARM_INTERWORK)
9b485d32 15126 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 15127
fd2ec330 15128 if (flags & EF_ARM_APCS_26)
6c571f00 15129 fprintf (file, " [APCS-26]");
fc830a83 15130 else
6c571f00 15131 fprintf (file, " [APCS-32]");
9a5aca8c 15132
96a846ea
RE		 15133 if (flags & EF_ARM_VFP_FLOAT)
15134 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 15135 else if (flags & EF_ARM_MAVERICK_FLOAT)
15136 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 15137 else
15138 fprintf (file, _(" [FPA float format]"));
15139
fd2ec330 15140 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 15141 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 15142
fd2ec330 15143 if (flags & EF_ARM_PIC)
9b485d32 15144 fprintf (file, _(" [position independent]"));
fc830a83 15145
fd2ec330 15146 if (flags & EF_ARM_NEW_ABI)
9b485d32 15147 fprintf (file, _(" [new ABI]"));
9a5aca8c 15148
fd2ec330 15149 if (flags & EF_ARM_OLD_ABI)
9b485d32 15150 fprintf (file, _(" [old ABI]"));
9a5aca8c 15151
fd2ec330 15152 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 15153 fprintf (file, _(" [software FP]"));
9a5aca8c 15154
96a846ea
RE		 15155 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
15156 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 15157 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
15158 | EF_ARM_MAVERICK_FLOAT);
fc830a83 15159 break;
9a5aca8c 15160
fc830a83 15161 case EF_ARM_EABI_VER1:
9b485d32 15162 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 15163
fc830a83 15164 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 15165 fprintf (file, _(" [sorted symbol table]"));
fc830a83 15166 else
9b485d32 15167 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 15168
fc830a83
NC		 15169 flags &= ~ EF_ARM_SYMSARESORTED;
15170 break;
9a5aca8c 15171
fd2ec330
PB		 15172 case EF_ARM_EABI_VER2:
15173 fprintf (file, _(" [Version2 EABI]"));
15174
15175 if (flags & EF_ARM_SYMSARESORTED)
15176 fprintf (file, _(" [sorted symbol table]"));
15177 else
15178 fprintf (file, _(" [unsorted symbol table]"));
15179
15180 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
15181 fprintf (file, _(" [dynamic symbols use segment index]"));
15182
15183 if (flags & EF_ARM_MAPSYMSFIRST)
15184 fprintf (file, _(" [mapping symbols precede others]"));
15185
99e4ae17 15186 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 15187 | EF_ARM_MAPSYMSFIRST);
15188 break;
15189
d507cf36
PB		 15190 case EF_ARM_EABI_VER3:
15191 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 15192 break;
15193
15194 case EF_ARM_EABI_VER4:
15195 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 15196 goto eabi;
d507cf36 15197
3a4a14e9
PB		 15198 case EF_ARM_EABI_VER5:
15199 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 15200
15201 if (flags & EF_ARM_ABI_FLOAT_SOFT)
15202 fprintf (file, _(" [soft-float ABI]"));
15203
15204 if (flags & EF_ARM_ABI_FLOAT_HARD)
15205 fprintf (file, _(" [hard-float ABI]"));
15206
15207 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
15208
3a4a14e9 15209 eabi:
d507cf36
PB		 15210 if (flags & EF_ARM_BE8)
15211 fprintf (file, _(" [BE8]"));
15212
15213 if (flags & EF_ARM_LE8)
15214 fprintf (file, _(" [LE8]"));
15215
15216 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
15217 break;
15218
fc830a83 15219 default:
9b485d32 15220 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 15221 break;
15222 }
252b5132 15223
fc830a83 15224 flags &= ~ EF_ARM_EABIMASK;
252b5132 15225
fc830a83 15226 if (flags & EF_ARM_RELEXEC)
9b485d32 15227 fprintf (file, _(" [relocatable executable]"));
252b5132 15228
18a20338
CL		 15229 if (flags & EF_ARM_PIC)
15230 fprintf (file, _(" [position independent]"));
15231
15232 if (elf_elfheader (abfd)->e_ident[EI_OSABI] == ELFOSABI_ARM_FDPIC)
15233 fprintf (file, _(" [FDPIC ABI supplement]"));
15234
15235 flags &= ~ (EF_ARM_RELEXEC | EF_ARM_PIC);
fc830a83
NC		 15236
15237 if (flags)
9b485d32 15238 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 15239
252b5132
RH		 15240 fputc ('\n', file);
15241
b34976b6 15242 return TRUE;
252b5132
RH		 15243}
15244
15245static int
57e8b36a 15246elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 15247{
2f0ca46a
NC		 15248 switch (ELF_ST_TYPE (elf_sym->st_info))
15249 {
15250 case STT_ARM_TFUNC:
15251 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 15252
2f0ca46a
NC		 15253 case STT_ARM_16BIT:
15254 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15255 This allows us to distinguish between data used by Thumb instructions
15256 and non-data (which is probably code) inside Thumb regions of an
15257 executable. */
1a0eb693 15258 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 15259 return ELF_ST_TYPE (elf_sym->st_info);
15260 break;
9a5aca8c 15261
ce855c42
NC		 15262 default:
15263 break;
2f0ca46a
NC		 15264 }
15265
15266 return type;
252b5132 15267}
f21f3fe0 15268
252b5132 15269static asection *
07adf181
AM		 15270elf32_arm_gc_mark_hook (asection *sec,
15271 struct bfd_link_info *info,
15272 Elf_Internal_Rela *rel,
15273 struct elf_link_hash_entry *h,
15274 Elf_Internal_Sym *sym)
252b5132
RH		 15275{
15276 if (h != NULL)
07adf181 15277 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 15278 {
15279 case R_ARM_GNU_VTINHERIT:
15280 case R_ARM_GNU_VTENTRY:
07adf181
AM		 15281 return NULL;
15282 }
9ad5cbcf 15283
07adf181 15284 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 15285}
15286
780a67af
NC		 15287/* Look through the relocs for a section during the first phase. */
15288
b34976b6 15289static bfd_boolean
57e8b36a
NC		 15290elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
15291 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 15292{
b34976b6
AM		 15293 Elf_Internal_Shdr *symtab_hdr;
15294 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 15295 const Elf_Internal_Rela *rel;
15296 const Elf_Internal_Rela *rel_end;
15297 bfd *dynobj;
5e681ec4 15298 asection *sreloc;
5e681ec4 15299 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 15300 bfd_boolean call_reloc_p;
15301 bfd_boolean may_become_dynamic_p;
15302 bfd_boolean may_need_local_target_p;
ce98a316 15303 unsigned long nsyms;
9a5aca8c 15304
0e1862bb 15305 if (bfd_link_relocatable (info))
b34976b6 15306 return TRUE;
9a5aca8c 15307
0ffa91dd
NC		 15308 BFD_ASSERT (is_arm_elf (abfd));
15309
5e681ec4 15310 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15311 if (htab == NULL)
15312 return FALSE;
15313
5e681ec4 15314 sreloc = NULL;
9a5aca8c 15315
67687978
PB		 15316 /* Create dynamic sections for relocatable executables so that we can
15317 copy relocations. */
15318 if (htab->root.is_relocatable_executable
15319 && ! htab->root.dynamic_sections_created)
15320 {
15321 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
15322 return FALSE;
15323 }
15324
cbc704f3
RS		 15325 if (htab->root.dynobj == NULL)
15326 htab->root.dynobj = abfd;
34e77a92
RS		 15327 if (!create_ifunc_sections (info))
15328 return FALSE;
cbc704f3
RS		 15329
15330 dynobj = htab->root.dynobj;
15331
0ffa91dd 15332 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 15333 sym_hashes = elf_sym_hashes (abfd);
ce98a316 15334 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 15335
252b5132
RH		 15336 rel_end = relocs + sec->reloc_count;
15337 for (rel = relocs; rel < rel_end; rel++)
15338 {
34e77a92 15339 Elf_Internal_Sym *isym;
252b5132 15340 struct elf_link_hash_entry *h;
b7693d02 15341 struct elf32_arm_link_hash_entry *eh;
d42c267e 15342 unsigned int r_symndx;
eb043451 15343 int r_type;
9a5aca8c 15344
252b5132 15345 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 15346 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 15347 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 15348
ce98a316
NC		 15349 if (r_symndx >= nsyms
15350 /* PR 9934: It is possible to have relocations that do not
15351 refer to symbols, thus it is also possible to have an
15352 object file containing relocations but no symbol table. */
cf35638d 15353 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 15354 {
871b3ab2 15355 _bfd_error_handler (_("%pB: bad symbol index: %d"), abfd,
4eca0228 15356 r_symndx);
ba93b8ac
DJ		 15357 return FALSE;
15358 }
15359
34e77a92
RS		 15360 h = NULL;
15361 isym = NULL;
15362 if (nsyms > 0)
973a3492 15363 {
34e77a92
RS		 15364 if (r_symndx < symtab_hdr->sh_info)
15365 {
15366 /* A local symbol. */
15367 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
15368 abfd, r_symndx);
15369 if (isym == NULL)
15370 return FALSE;
15371 }
15372 else
15373 {
15374 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
15375 while (h->root.type == bfd_link_hash_indirect
15376 || h->root.type == bfd_link_hash_warning)
15377 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15378 }
973a3492 15379 }
9a5aca8c 15380
b7693d02
DJ		 15381 eh = (struct elf32_arm_link_hash_entry *) h;
15382
f6e32f6d
RS		 15383 call_reloc_p = FALSE;
15384 may_become_dynamic_p = FALSE;
15385 may_need_local_target_p = FALSE;
15386
0855e32b
NS		 15387 /* Could be done earlier, if h were already available. */
15388 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 15389 switch (r_type)
99059e56 15390 {
e8b09b87
CL		 15391 case R_ARM_GOTOFFFUNCDESC:
15392 {
15393 if (h == NULL)
15394 {
15395 if (!elf32_arm_allocate_local_sym_info (abfd))
15396 return FALSE;
15397 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].gotofffuncdesc_cnt += 1;
15398 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15399 }
15400 else
15401 {
15402 eh->fdpic_cnts.gotofffuncdesc_cnt++;
15403 }
15404 }
15405 break;
15406
15407 case R_ARM_GOTFUNCDESC:
15408 {
15409 if (h == NULL)
15410 {
15411 /* Such a relocation is not supposed to be generated
15412 by gcc on a static function. */
15413 /* Anyway if needed it could be handled. */
15414 abort();
15415 }
15416 else
15417 {
15418 eh->fdpic_cnts.gotfuncdesc_cnt++;
15419 }
15420 }
15421 break;
15422
15423 case R_ARM_FUNCDESC:
15424 {
15425 if (h == NULL)
15426 {
15427 if (!elf32_arm_allocate_local_sym_info (abfd))
15428 return FALSE;
15429 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_cnt += 1;
15430 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15431 }
15432 else
15433 {
15434 eh->fdpic_cnts.funcdesc_cnt++;
15435 }
15436 }
15437 break;
15438
5e681ec4 15439 case R_ARM_GOT32:
eb043451 15440 case R_ARM_GOT_PREL:
ba93b8ac 15441 case R_ARM_TLS_GD32:
5c5a4843 15442 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 15443 case R_ARM_TLS_IE32:
5c5a4843 15444 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 15445 case R_ARM_TLS_GOTDESC:
15446 case R_ARM_TLS_DESCSEQ:
15447 case R_ARM_THM_TLS_DESCSEQ:
15448 case R_ARM_TLS_CALL:
15449 case R_ARM_THM_TLS_CALL:
5e681ec4 15450 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 15451 {
15452 int tls_type, old_tls_type;
5e681ec4 15453
ba93b8ac
DJ		 15454 switch (r_type)
15455 {
15456 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
5c5a4843 15457 case R_ARM_TLS_GD32_FDPIC: tls_type = GOT_TLS_GD; break;
b38cadfb 15458
ba93b8ac 15459 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
5c5a4843 15460 case R_ARM_TLS_IE32_FDPIC: tls_type = GOT_TLS_IE; break;
b38cadfb 15461
0855e32b
NS		 15462 case R_ARM_TLS_GOTDESC:
15463 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
15464 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
15465 tls_type = GOT_TLS_GDESC; break;
b38cadfb 15466
ba93b8ac
DJ		 15467 default: tls_type = GOT_NORMAL; break;
15468 }
252b5132 15469
0e1862bb 15470 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 15471 info->flags |= DF_STATIC_TLS;
15472
ba93b8ac
DJ		 15473 if (h != NULL)
15474 {
15475 h->got.refcount++;
15476 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
15477 }
15478 else
15479 {
ba93b8ac 15480 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 15481 if (!elf32_arm_allocate_local_sym_info (abfd))
15482 return FALSE;
15483 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 15484 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
15485 }
15486
0855e32b 15487 /* If a variable is accessed with both tls methods, two
99059e56 15488 slots may be created. */
0855e32b
NS		 15489 if (GOT_TLS_GD_ANY_P (old_tls_type)
15490 && GOT_TLS_GD_ANY_P (tls_type))
15491 tls_type |= old_tls_type;
15492
15493 /* We will already have issued an error message if there
15494 is a TLS/non-TLS mismatch, based on the symbol
15495 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 15496 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
15497 && tls_type != GOT_NORMAL)
15498 tls_type |= old_tls_type;
15499
0855e32b 15500 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 15501 method, we're able to relax. Turn off the GDESC flag,
15502 without messing up with any other kind of tls types
6a631e86 15503 that may be involved. */
0855e32b
NS		 15504 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
15505 tls_type &= ~GOT_TLS_GDESC;
15506
ba93b8ac
DJ		 15507 if (old_tls_type != tls_type)
15508 {
15509 if (h != NULL)
15510 elf32_arm_hash_entry (h)->tls_type = tls_type;
15511 else
15512 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
15513 }
15514 }
8029a119 15515 /* Fall through. */
ba93b8ac
DJ		 15516
15517 case R_ARM_TLS_LDM32:
5c5a4843
CL		 15518 case R_ARM_TLS_LDM32_FDPIC:
15519 if (r_type == R_ARM_TLS_LDM32 || r_type == R_ARM_TLS_LDM32_FDPIC)
ba93b8ac 15520 htab->tls_ldm_got.refcount++;
8029a119 15521 /* Fall through. */
252b5132 15522
c19d1205 15523 case R_ARM_GOTOFF32:
5e681ec4 15524 case R_ARM_GOTPC:
cbc704f3
RS		 15525 if (htab->root.sgot == NULL
15526 && !create_got_section (htab->root.dynobj, info))
15527 return FALSE;
252b5132
RH		 15528 break;
15529
252b5132 15530 case R_ARM_PC24:
7359ea65 15531 case R_ARM_PLT32:
5b5bb741
PB		 15532 case R_ARM_CALL:
15533 case R_ARM_JUMP24:
eb043451 15534 case R_ARM_PREL31:
c19d1205 15535 case R_ARM_THM_CALL:
bd97cb95
DJ		 15536 case R_ARM_THM_JUMP24:
15537 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 15538 call_reloc_p = TRUE;
15539 may_need_local_target_p = TRUE;
15540 break;
15541
15542 case R_ARM_ABS12:
15543 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15544 ldr __GOTT_INDEX__ offsets. */
15545 if (!htab->vxworks_p)
15546 {
15547 may_need_local_target_p = TRUE;
15548 break;
15549 }
aebf9be7 15550 else goto jump_over;
9eaff861 15551
f6e32f6d 15552 /* Fall through. */
39623e12 15553
96c23d59
JM		 15554 case R_ARM_MOVW_ABS_NC:
15555 case R_ARM_MOVT_ABS:
15556 case R_ARM_THM_MOVW_ABS_NC:
15557 case R_ARM_THM_MOVT_ABS:
0e1862bb 15558 if (bfd_link_pic (info))
96c23d59 15559 {
4eca0228 15560 _bfd_error_handler
871b3ab2 15561 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
96c23d59
JM		 15562 abfd, elf32_arm_howto_table_1[r_type].name,
15563 (h) ? h->root.root.string : "a local symbol");
15564 bfd_set_error (bfd_error_bad_value);
15565 return FALSE;
15566 }
15567
15568 /* Fall through. */
39623e12
PB		 15569 case R_ARM_ABS32:
15570 case R_ARM_ABS32_NOI:
aebf9be7 15571 jump_over:
0e1862bb 15572 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 15573 {
15574 h->pointer_equality_needed = 1;
15575 }
15576 /* Fall through. */
39623e12
PB		 15577 case R_ARM_REL32:
15578 case R_ARM_REL32_NOI:
b6895b4f
PB		 15579 case R_ARM_MOVW_PREL_NC:
15580 case R_ARM_MOVT_PREL:
b6895b4f
PB		 15581 case R_ARM_THM_MOVW_PREL_NC:
15582 case R_ARM_THM_MOVT_PREL:
39623e12 15583
b7693d02 15584 /* Should the interworking branches be listed here? */
e8b09b87
CL		 15585 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable
15586 || htab->fdpic_p)
34e77a92
RS		 15587 && (sec->flags & SEC_ALLOC) != 0)
15588 {
15589 if (h == NULL
469a3493 15590 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 15591 {
15592 /* In shared libraries and relocatable executables,
15593 we treat local relative references as calls;
15594 see the related SYMBOL_CALLS_LOCAL code in
15595 allocate_dynrelocs. */
15596 call_reloc_p = TRUE;
15597 may_need_local_target_p = TRUE;
15598 }
15599 else
15600 /* We are creating a shared library or relocatable
15601 executable, and this is a reloc against a global symbol,
15602 or a non-PC-relative reloc against a local symbol.
15603 We may need to copy the reloc into the output. */
15604 may_become_dynamic_p = TRUE;
15605 }
f6e32f6d
RS		 15606 else
15607 may_need_local_target_p = TRUE;
252b5132
RH		 15608 break;
15609
99059e56
RM		 15610 /* This relocation describes the C++ object vtable hierarchy.
15611 Reconstruct it for later use during GC. */
15612 case R_ARM_GNU_VTINHERIT:
15613 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
15614 return FALSE;
15615 break;
15616
15617 /* This relocation describes which C++ vtable entries are actually
15618 used. Record for later use during GC. */
15619 case R_ARM_GNU_VTENTRY:
a0ea3a14 15620 if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
99059e56
RM		 15621 return FALSE;
15622 break;
15623 }
f6e32f6d
RS		 15624
15625 if (h != NULL)
15626 {
15627 if (call_reloc_p)
15628 /* We may need a .plt entry if the function this reloc
15629 refers to is in a different object, regardless of the
15630 symbol's type. We can't tell for sure yet, because
15631 something later might force the symbol local. */
15632 h->needs_plt = 1;
15633 else if (may_need_local_target_p)
15634 /* If this reloc is in a read-only section, we might
15635 need a copy reloc. We can't check reliably at this
15636 stage whether the section is read-only, as input
15637 sections have not yet been mapped to output sections.
15638 Tentatively set the flag for now, and correct in
15639 adjust_dynamic_symbol. */
15640 h->non_got_ref = 1;
15641 }
15642
34e77a92
RS		 15643 if (may_need_local_target_p
15644 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 15645 {
34e77a92
RS		 15646 union gotplt_union *root_plt;
15647 struct arm_plt_info *arm_plt;
15648 struct arm_local_iplt_info *local_iplt;
15649
15650 if (h != NULL)
15651 {
15652 root_plt = &h->plt;
15653 arm_plt = &eh->plt;
15654 }
15655 else
15656 {
15657 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
15658 if (local_iplt == NULL)
15659 return FALSE;
15660 root_plt = &local_iplt->root;
15661 arm_plt = &local_iplt->arm;
15662 }
15663
f6e32f6d
RS		 15664 /* If the symbol is a function that doesn't bind locally,
15665 this relocation will need a PLT entry. */
a8c887dd
NC		 15666 if (root_plt->refcount != -1)
15667 root_plt->refcount += 1;
34e77a92
RS		 15668
15669 if (!call_reloc_p)
15670 arm_plt->noncall_refcount++;
f6e32f6d
RS		 15671
15672 /* It's too early to use htab->use_blx here, so we have to
15673 record possible blx references separately from
15674 relocs that definitely need a thumb stub. */
15675
15676 if (r_type == R_ARM_THM_CALL)
34e77a92 15677 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 15678
15679 if (r_type == R_ARM_THM_JUMP24
15680 || r_type == R_ARM_THM_JUMP19)
34e77a92 15681 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 15682 }
15683
15684 if (may_become_dynamic_p)
15685 {
15686 struct elf_dyn_relocs *p, **head;
15687
15688 /* Create a reloc section in dynobj. */
15689 if (sreloc == NULL)
15690 {
15691 sreloc = _bfd_elf_make_dynamic_reloc_section
15692 (sec, dynobj, 2, abfd, ! htab->use_rel);
15693
15694 if (sreloc == NULL)
15695 return FALSE;
15696
15697 /* BPABI objects never have dynamic relocations mapped. */
15698 if (htab->symbian_p)
15699 {
15700 flagword flags;
15701
fd361982 15702 flags = bfd_section_flags (sreloc);
f6e32f6d 15703 flags &= ~(SEC_LOAD | SEC_ALLOC);
fd361982 15704 bfd_set_section_flags (sreloc, flags);
f6e32f6d
RS		 15705 }
15706 }
15707
15708 /* If this is a global symbol, count the number of
15709 relocations we need for this symbol. */
15710 if (h != NULL)
15711 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
15712 else
15713 {
34e77a92
RS		 15714 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
15715 if (head == NULL)
f6e32f6d 15716 return FALSE;
f6e32f6d
RS		 15717 }
15718
15719 p = *head;
15720 if (p == NULL || p->sec != sec)
15721 {
15722 bfd_size_type amt = sizeof *p;
15723
15724 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
15725 if (p == NULL)
15726 return FALSE;
15727 p->next = *head;
15728 *head = p;
15729 p->sec = sec;
15730 p->count = 0;
15731 p->pc_count = 0;
15732 }
15733
469a3493 15734 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 15735 p->pc_count += 1;
15736 p->count += 1;
e8b09b87
CL		 15737 if (h == NULL && htab->fdpic_p && !bfd_link_pic(info)
15738 && r_type != R_ARM_ABS32 && r_type != R_ARM_ABS32_NOI) {
15739 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15740 that will become rofixup. */
15741 /* This is due to the fact that we suppose all will become rofixup. */
15742 fprintf(stderr, "FDPIC does not yet support %d relocation to become dynamic for executable\n", r_type);
15743 _bfd_error_handler
15744 (_("FDPIC does not yet support %s relocation"
15745 " to become dynamic for executable"),
15746 elf32_arm_howto_table_1[r_type].name);
15747 abort();
15748 }
f6e32f6d 15749 }
252b5132 15750 }
f21f3fe0 15751
b34976b6 15752 return TRUE;
252b5132
RH		 15753}
15754
9eaff861
AO		 15755static void
15756elf32_arm_update_relocs (asection *o,
15757 struct bfd_elf_section_reloc_data *reldata)
15758{
15759 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
15760 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
15761 const struct elf_backend_data *bed;
15762 _arm_elf_section_data *eado;
15763 struct bfd_link_order *p;
15764 bfd_byte *erela_head, *erela;
15765 Elf_Internal_Rela *irela_head, *irela;
15766 Elf_Internal_Shdr *rel_hdr;
15767 bfd *abfd;
15768 unsigned int count;
15769
15770 eado = get_arm_elf_section_data (o);
15771
15772 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
15773 return;
15774
15775 abfd = o->owner;
15776 bed = get_elf_backend_data (abfd);
15777 rel_hdr = reldata->hdr;
15778
15779 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
15780 {
15781 swap_in = bed->s->swap_reloc_in;
15782 swap_out = bed->s->swap_reloc_out;
15783 }
15784 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
15785 {
15786 swap_in = bed->s->swap_reloca_in;
15787 swap_out = bed->s->swap_reloca_out;
15788 }
15789 else
15790 abort ();
15791
15792 erela_head = rel_hdr->contents;
15793 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
15794 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
15795
15796 erela = erela_head;
15797 irela = irela_head;
15798 count = 0;
15799
15800 for (p = o->map_head.link_order; p; p = p->next)
15801 {
15802 if (p->type == bfd_section_reloc_link_order
15803 || p->type == bfd_symbol_reloc_link_order)
15804 {
15805 (*swap_in) (abfd, erela, irela);
15806 erela += rel_hdr->sh_entsize;
15807 irela++;
15808 count++;
15809 }
15810 else if (p->type == bfd_indirect_link_order)
15811 {
15812 struct bfd_elf_section_reloc_data *input_reldata;
15813 arm_unwind_table_edit *edit_list, *edit_tail;
15814 _arm_elf_section_data *eadi;
15815 bfd_size_type j;
15816 bfd_vma offset;
15817 asection *i;
15818
15819 i = p->u.indirect.section;
15820
15821 eadi = get_arm_elf_section_data (i);
15822 edit_list = eadi->u.exidx.unwind_edit_list;
15823 edit_tail = eadi->u.exidx.unwind_edit_tail;
539300fb 15824 offset = i->output_offset;
9eaff861
AO		 15825
15826 if (eadi->elf.rel.hdr &&
15827 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
15828 input_reldata = &eadi->elf.rel;
15829 else if (eadi->elf.rela.hdr &&
15830 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
15831 input_reldata = &eadi->elf.rela;
15832 else
15833 abort ();
15834
15835 if (edit_list)
15836 {
15837 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15838 {
15839 arm_unwind_table_edit *edit_node, *edit_next;
15840 bfd_vma bias;
c48182bf 15841 bfd_vma reloc_index;
9eaff861
AO		 15842
15843 (*swap_in) (abfd, erela, irela);
c48182bf 15844 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 15845
15846 bias = 0;
15847 edit_node = edit_list;
15848 for (edit_next = edit_list;
c48182bf 15849 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 15850 edit_next = edit_node->next)
15851 {
15852 bias++;
15853 edit_node = edit_next;
15854 }
15855
15856 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 15857 || edit_node->index != reloc_index)
9eaff861
AO		 15858 {
15859 irela->r_offset -= bias * 8;
15860 irela++;
15861 count++;
15862 }
15863
15864 erela += rel_hdr->sh_entsize;
15865 }
15866
15867 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
15868 {
15869 /* New relocation entity. */
15870 asection *text_sec = edit_tail->linked_section;
15871 asection *text_out = text_sec->output_section;
15872 bfd_vma exidx_offset = offset + i->size - 8;
15873
15874 irela->r_addend = 0;
15875 irela->r_offset = exidx_offset;
15876 irela->r_info = ELF32_R_INFO
15877 (text_out->target_index, R_ARM_PREL31);
15878 irela++;
15879 count++;
15880 }
15881 }
15882 else
15883 {
15884 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15885 {
15886 (*swap_in) (abfd, erela, irela);
15887 erela += rel_hdr->sh_entsize;
15888 irela++;
15889 }
15890
15891 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15892 }
15893 }
15894 }
15895
15896 reldata->count = count;
15897 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15898
15899 erela = erela_head;
15900 irela = irela_head;
15901 while (count > 0)
15902 {
15903 (*swap_out) (abfd, irela, erela);
15904 erela += rel_hdr->sh_entsize;
15905 irela++;
15906 count--;
15907 }
15908
15909 free (irela_head);
15910
15911 /* Hashes are no longer valid. */
15912 free (reldata->hashes);
15913 reldata->hashes = NULL;
15914}
15915
6a5bb875 15916/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15917 required if the corresponding code section is marked. Similarly, ARMv8-M
15918 secure entry functions can only be referenced by SG veneers which are
15919 created after the GC process. They need to be marked in case they reside in
15920 their own section (as would be the case if code was compiled with
15921 -ffunction-sections). */
6a5bb875
PB		 15922
15923static bfd_boolean
906e58ca
NC		 15924elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15925 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15926{
15927 bfd *sub;
15928 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15929 asection *cmse_sec;
15930 obj_attribute *out_attr;
15931 Elf_Internal_Shdr *symtab_hdr;
15932 unsigned i, sym_count, ext_start;
15933 const struct elf_backend_data *bed;
15934 struct elf_link_hash_entry **sym_hashes;
15935 struct elf32_arm_link_hash_entry *cmse_hash;
15936 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
bb32413f
SP		 15937 bfd_boolean debug_sec_need_to_be_marked = FALSE;
15938 asection *isec;
6a5bb875 15939
7f6ab9f8
AM		 15940 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15941
4ba2ef8f
TP		 15942 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15943 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15944 && out_attr[Tag_CPU_arch_profile].i == 'M';
15945
6a5bb875
PB		 15946 /* Marking EH data may cause additional code sections to be marked,
15947 requiring multiple passes. */
15948 again = TRUE;
15949 while (again)
15950 {
15951 again = FALSE;
c72f2fb2 15952 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15953 {
15954 asection *o;
15955
0ffa91dd 15956 if (! is_arm_elf (sub))
6a5bb875
PB		 15957 continue;
15958
15959 elf_shdrp = elf_elfsections (sub);
15960 for (o = sub->sections; o != NULL; o = o->next)
15961 {
15962 Elf_Internal_Shdr *hdr;
0ffa91dd 15963
6a5bb875 15964 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15965 if (hdr->sh_type == SHT_ARM_EXIDX
15966 && hdr->sh_link
15967 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15968 && !o->gc_mark
15969 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15970 {
15971 again = TRUE;
15972 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15973 return FALSE;
15974 }
15975 }
4ba2ef8f
TP		 15976
15977 /* Mark section holding ARMv8-M secure entry functions. We mark all
15978 of them so no need for a second browsing. */
15979 if (is_v8m && first_bfd_browse)
15980 {
15981 sym_hashes = elf_sym_hashes (sub);
15982 bed = get_elf_backend_data (sub);
15983 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15984 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15985 ext_start = symtab_hdr->sh_info;
15986
15987 /* Scan symbols. */
15988 for (i = ext_start; i < sym_count; i++)
15989 {
15990 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15991
15992 /* Assume it is a special symbol. If not, cmse_scan will
15993 warn about it and user can do something about it. */
baf46cd7
AM		 15994 if (CONST_STRNEQ (cmse_hash->root.root.root.string,
15995 CMSE_PREFIX))
4ba2ef8f
TP		 15996 {
15997 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 15998 if (!cmse_sec->gc_mark
15999 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f 16000 return FALSE;
bb32413f
SP		 16001 /* The debug sections related to these secure entry
16002 functions are marked on enabling below flag. */
16003 debug_sec_need_to_be_marked = TRUE;
4ba2ef8f
TP		 16004 }
16005 }
bb32413f
SP		 16006
16007 if (debug_sec_need_to_be_marked)
16008 {
16009 /* Looping over all the sections of the object file containing
16010 Armv8-M secure entry functions and marking all the debug
16011 sections. */
16012 for (isec = sub->sections; isec != NULL; isec = isec->next)
16013 {
16014 /* If not a debug sections, skip it. */
16015 if (!isec->gc_mark && (isec->flags & SEC_DEBUGGING))
16016 isec->gc_mark = 1 ;
16017 }
16018 debug_sec_need_to_be_marked = FALSE;
16019 }
4ba2ef8f 16020 }
6a5bb875 16021 }
4ba2ef8f 16022 first_bfd_browse = FALSE;
6a5bb875
PB		 16023 }
16024
16025 return TRUE;
16026}
16027
3c9458e9
NC		 16028/* Treat mapping symbols as special target symbols. */
16029
16030static bfd_boolean
16031elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
16032{
b0796911
PB		 16033 return bfd_is_arm_special_symbol_name (sym->name,
16034 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 16035}
16036
62e0492f 16037/* This is a version of _bfd_elf_find_function() from dwarf2.c except that
0367ecfb
NC		 16038 ARM mapping symbols are ignored when looking for function names
16039 and STT_ARM_TFUNC is considered to a function type. */
252b5132 16040
0367ecfb 16041static bfd_boolean
62e0492f 16042arm_elf_find_function (bfd * abfd,
0367ecfb 16043 asymbol ** symbols,
fb167eb2 16044 asection * section,
07d6d2b8 16045 bfd_vma offset,
0367ecfb
NC		 16046 const char ** filename_ptr,
16047 const char ** functionname_ptr)
16048{
16049 const char * filename = NULL;
16050 asymbol * func = NULL;
16051 bfd_vma low_func = 0;
16052 asymbol ** p;
252b5132 16053
62e0492f
AL		 16054 if (symbols == NULL)
16055 return FALSE;
16056
16057 if (bfd_get_flavour (abfd) != bfd_target_elf_flavour)
16058 return FALSE;
16059
252b5132
RH		 16060 for (p = symbols; *p != NULL; p++)
16061 {
16062 elf_symbol_type *q;
16063
16064 q = (elf_symbol_type *) *p;
16065
252b5132
RH		 16066 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
16067 {
16068 default:
16069 break;
16070 case STT_FILE:
16071 filename = bfd_asymbol_name (&q->symbol);
16072 break;
252b5132
RH		 16073 case STT_FUNC:
16074 case STT_ARM_TFUNC:
9d2da7ca 16075 case STT_NOTYPE:
b0796911 16076 /* Skip mapping symbols. */
0367ecfb 16077 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 16078 && bfd_is_arm_special_symbol_name (q->symbol.name,
16079 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 16080 continue;
16081 /* Fall through. */
e6f7f6d1 16082 if (bfd_asymbol_section (&q->symbol) == section
252b5132
RH		 16083 && q->symbol.value >= low_func
16084 && q->symbol.value <= offset)
16085 {
16086 func = (asymbol *) q;
16087 low_func = q->symbol.value;
16088 }
16089 break;
16090 }
16091 }
16092
16093 if (func == NULL)
b34976b6 16094 return FALSE;
252b5132 16095
0367ecfb
NC		 16096 if (filename_ptr)
16097 *filename_ptr = filename;
16098 if (functionname_ptr)
16099 *functionname_ptr = bfd_asymbol_name (func);
16100
16101 return TRUE;
906e58ca 16102}
0367ecfb
NC		 16103
16104
16105/* Find the nearest line to a particular section and offset, for error
16106 reporting. This code is a duplicate of the code in elf.c, except
16107 that it uses arm_elf_find_function. */
16108
16109static bfd_boolean
07d6d2b8
AM		 16110elf32_arm_find_nearest_line (bfd * abfd,
16111 asymbol ** symbols,
16112 asection * section,
16113 bfd_vma offset,
0367ecfb
NC		 16114 const char ** filename_ptr,
16115 const char ** functionname_ptr,
fb167eb2
AM		 16116 unsigned int * line_ptr,
16117 unsigned int * discriminator_ptr)
0367ecfb
NC		 16118{
16119 bfd_boolean found = FALSE;
16120
fb167eb2 16121 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 16122 filename_ptr, functionname_ptr,
fb167eb2 16123 line_ptr, discriminator_ptr,
9defd221 16124 dwarf_debug_sections,
0367ecfb
NC		 16125 & elf_tdata (abfd)->dwarf2_find_line_info))
16126 {
16127 if (!*functionname_ptr)
fb167eb2 16128 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 16129 *filename_ptr ? NULL : filename_ptr,
16130 functionname_ptr);
f21f3fe0 16131
0367ecfb
NC		 16132 return TRUE;
16133 }
16134
fb167eb2
AM		 16135 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
16136 uses DWARF1. */
16137
0367ecfb
NC		 16138 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
16139 & found, filename_ptr,
16140 functionname_ptr, line_ptr,
16141 & elf_tdata (abfd)->line_info))
16142 return FALSE;
16143
16144 if (found && (*functionname_ptr || *line_ptr))
16145 return TRUE;
16146
16147 if (symbols == NULL)
16148 return FALSE;
16149
fb167eb2 16150 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 16151 filename_ptr, functionname_ptr))
16152 return FALSE;
16153
16154 *line_ptr = 0;
b34976b6 16155 return TRUE;
252b5132
RH		 16156}
16157
4ab527b0 16158static bfd_boolean
07d6d2b8 16159elf32_arm_find_inliner_info (bfd * abfd,
4ab527b0
FF		 16160 const char ** filename_ptr,
16161 const char ** functionname_ptr,
16162 unsigned int * line_ptr)
16163{
16164 bfd_boolean found;
16165 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
16166 functionname_ptr, line_ptr,
16167 & elf_tdata (abfd)->dwarf2_find_line_info);
16168 return found;
16169}
16170
63c1f59d
AM		 16171/* Find dynamic relocs for H that apply to read-only sections. */
16172
16173static asection *
16174readonly_dynrelocs (struct elf_link_hash_entry *h)
16175{
16176 struct elf_dyn_relocs *p;
16177
16178 for (p = elf32_arm_hash_entry (h)->dyn_relocs; p != NULL; p = p->next)
16179 {
16180 asection *s = p->sec->output_section;
16181
16182 if (s != NULL && (s->flags & SEC_READONLY) != 0)
16183 return p->sec;
16184 }
16185 return NULL;
16186}
16187
252b5132
RH		 16188/* Adjust a symbol defined by a dynamic object and referenced by a
16189 regular object. The current definition is in some section of the
16190 dynamic object, but we're not including those sections. We have to
16191 change the definition to something the rest of the link can
16192 understand. */
16193
b34976b6 16194static bfd_boolean
57e8b36a
NC		 16195elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
16196 struct elf_link_hash_entry * h)
252b5132
RH		 16197{
16198 bfd * dynobj;
5474d94f 16199 asection *s, *srel;
b7693d02 16200 struct elf32_arm_link_hash_entry * eh;
67687978 16201 struct elf32_arm_link_hash_table *globals;
252b5132 16202
67687978 16203 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16204 if (globals == NULL)
16205 return FALSE;
16206
252b5132
RH		 16207 dynobj = elf_hash_table (info)->dynobj;
16208
16209 /* Make sure we know what is going on here. */
16210 BFD_ASSERT (dynobj != NULL
f5385ebf 16211 && (h->needs_plt
34e77a92 16212 || h->type == STT_GNU_IFUNC
60d67dc8 16213 || h->is_weakalias
f5385ebf
AM		 16214 || (h->def_dynamic
16215 && h->ref_regular
16216 && !h->def_regular)));
252b5132 16217
b7693d02
DJ		 16218 eh = (struct elf32_arm_link_hash_entry *) h;
16219
252b5132
RH		 16220 /* If this is a function, put it in the procedure linkage table. We
16221 will fill in the contents of the procedure linkage table later,
16222 when we know the address of the .got section. */
34e77a92 16223 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 16224 {
34e77a92
RS		 16225 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
16226 symbol binds locally. */
5e681ec4 16227 if (h->plt.refcount <= 0
34e77a92
RS		 16228 || (h->type != STT_GNU_IFUNC
16229 && (SYMBOL_CALLS_LOCAL (info, h)
16230 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16231 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 16232 {
16233 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 16234 file, but the symbol was never referred to by a dynamic
16235 object, or if all references were garbage collected. In
16236 such a case, we don't actually need to build a procedure
16237 linkage table, and we can just do a PC24 reloc instead. */
16238 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16239 eh->plt.thumb_refcount = 0;
16240 eh->plt.maybe_thumb_refcount = 0;
16241 eh->plt.noncall_refcount = 0;
f5385ebf 16242 h->needs_plt = 0;
252b5132
RH		 16243 }
16244
b34976b6 16245 return TRUE;
252b5132 16246 }
5e681ec4 16247 else
b7693d02
DJ		 16248 {
16249 /* It's possible that we incorrectly decided a .plt reloc was
16250 needed for an R_ARM_PC24 or similar reloc to a non-function sym
16251 in check_relocs. We can't decide accurately between function
16252 and non-function syms in check-relocs; Objects loaded later in
16253 the link may change h->type. So fix it now. */
16254 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16255 eh->plt.thumb_refcount = 0;
16256 eh->plt.maybe_thumb_refcount = 0;
16257 eh->plt.noncall_refcount = 0;
b7693d02 16258 }
252b5132
RH		 16259
16260 /* If this is a weak symbol, and there is a real definition, the
16261 processor independent code will have arranged for us to see the
16262 real definition first, and we can just use the same value. */
60d67dc8 16263 if (h->is_weakalias)
252b5132 16264 {
60d67dc8
AM		 16265 struct elf_link_hash_entry *def = weakdef (h);
16266 BFD_ASSERT (def->root.type == bfd_link_hash_defined);
16267 h->root.u.def.section = def->root.u.def.section;
16268 h->root.u.def.value = def->root.u.def.value;
b34976b6 16269 return TRUE;
252b5132
RH		 16270 }
16271
ba93b8ac
DJ		 16272 /* If there are no non-GOT references, we do not need a copy
16273 relocation. */
16274 if (!h->non_got_ref)
16275 return TRUE;
16276
252b5132
RH		 16277 /* This is a reference to a symbol defined by a dynamic object which
16278 is not a function. */
16279
16280 /* If we are creating a shared library, we must presume that the
16281 only references to the symbol are via the global offset table.
16282 For such cases we need not do anything here; the relocations will
67687978
PB		 16283 be handled correctly by relocate_section. Relocatable executables
16284 can reference data in shared objects directly, so we don't need to
16285 do anything here. */
0e1862bb 16286 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 16287 return TRUE;
252b5132
RH		 16288
16289 /* We must allocate the symbol in our .dynbss section, which will
16290 become part of the .bss section of the executable. There will be
16291 an entry for this symbol in the .dynsym section. The dynamic
16292 object will contain position independent code, so all references
16293 from the dynamic object to this symbol will go through the global
16294 offset table. The dynamic linker will use the .dynsym entry to
16295 determine the address it must put in the global offset table, so
16296 both the dynamic object and the regular object will refer to the
16297 same memory location for the variable. */
5522f910
NC		 16298 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16299 linker to copy the initial value out of the dynamic object and into
16300 the runtime process image. We need to remember the offset into the
00a97672 16301 .rel(a).bss section we are going to use. */
5474d94f
AM		 16302 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
16303 {
16304 s = globals->root.sdynrelro;
16305 srel = globals->root.sreldynrelro;
16306 }
16307 else
16308 {
16309 s = globals->root.sdynbss;
16310 srel = globals->root.srelbss;
16311 }
5522f910
NC		 16312 if (info->nocopyreloc == 0
16313 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 16314 && h->size != 0)
252b5132 16315 {
47beaa6a 16316 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 16317 h->needs_copy = 1;
252b5132
RH		 16318 }
16319
6cabe1ea 16320 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 16321}
16322
5e681ec4
PB		 16323/* Allocate space in .plt, .got and associated reloc sections for
16324 dynamic relocs. */
16325
16326static bfd_boolean
47beaa6a 16327allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 16328{
16329 struct bfd_link_info *info;
16330 struct elf32_arm_link_hash_table *htab;
16331 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 16332 struct elf_dyn_relocs *p;
5e681ec4
PB		 16333
16334 if (h->root.type == bfd_link_hash_indirect)
16335 return TRUE;
16336
e6a6bb22
AM		 16337 eh = (struct elf32_arm_link_hash_entry *) h;
16338
5e681ec4
PB		 16339 info = (struct bfd_link_info *) inf;
16340 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16341 if (htab == NULL)
16342 return FALSE;
5e681ec4 16343
34e77a92 16344 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 16345 && h->plt.refcount > 0)
16346 {
16347 /* Make sure this symbol is output as a dynamic symbol.
16348 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16349 if (h->dynindx == -1 && !h->forced_local
16350 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16351 {
c152c796 16352 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16353 return FALSE;
16354 }
16355
34e77a92
RS		 16356 /* If the call in the PLT entry binds locally, the associated
16357 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16358 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16359 than the .plt section. */
16360 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
16361 {
16362 eh->is_iplt = 1;
16363 if (eh->plt.noncall_refcount == 0
16364 && SYMBOL_REFERENCES_LOCAL (info, h))
16365 /* All non-call references can be resolved directly.
16366 This means that they can (and in some cases, must)
16367 resolve directly to the run-time target, rather than
16368 to the PLT. That in turns means that any .got entry
16369 would be equal to the .igot.plt entry, so there's
16370 no point having both. */
16371 h->got.refcount = 0;
16372 }
16373
0e1862bb 16374 if (bfd_link_pic (info)
34e77a92 16375 || eh->is_iplt
7359ea65 16376 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 16377 {
34e77a92 16378 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 16379
5e681ec4
PB		 16380 /* If this symbol is not defined in a regular file, and we are
16381 not generating a shared library, then set the symbol to this
16382 location in the .plt. This is required to make function
16383 pointers compare as equal between the normal executable and
16384 the shared library. */
0e1862bb 16385 if (! bfd_link_pic (info)
f5385ebf 16386 && !h->def_regular)
5e681ec4 16387 {
34e77a92 16388 h->root.u.def.section = htab->root.splt;
5e681ec4 16389 h->root.u.def.value = h->plt.offset;
5e681ec4 16390
67d74e43
DJ		 16391 /* Make sure the function is not marked as Thumb, in case
16392 it is the target of an ABS32 relocation, which will
16393 point to the PLT entry. */
39d911fc 16394 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 16395 }
022f8312 16396
00a97672
RS		 16397 /* VxWorks executables have a second set of relocations for
16398 each PLT entry. They go in a separate relocation section,
16399 which is processed by the kernel loader. */
0e1862bb 16400 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 16401 {
16402 /* There is a relocation for the initial PLT entry:
16403 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16404 if (h->plt.offset == htab->plt_header_size)
47beaa6a 16405 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 16406
16407 /* There are two extra relocations for each subsequent
16408 PLT entry: an R_ARM_32 relocation for the GOT entry,
16409 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 16410 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 16411 }
5e681ec4
PB		 16412 }
16413 else
16414 {
16415 h->plt.offset = (bfd_vma) -1;
f5385ebf 16416 h->needs_plt = 0;
5e681ec4
PB		 16417 }
16418 }
16419 else
16420 {
16421 h->plt.offset = (bfd_vma) -1;
f5385ebf 16422 h->needs_plt = 0;
5e681ec4
PB		 16423 }
16424
0855e32b
NS		 16425 eh = (struct elf32_arm_link_hash_entry *) h;
16426 eh->tlsdesc_got = (bfd_vma) -1;
16427
5e681ec4
PB		 16428 if (h->got.refcount > 0)
16429 {
16430 asection *s;
16431 bfd_boolean dyn;
ba93b8ac
DJ		 16432 int tls_type = elf32_arm_hash_entry (h)->tls_type;
16433 int indx;
5e681ec4
PB		 16434
16435 /* Make sure this symbol is output as a dynamic symbol.
16436 Undefined weak syms won't yet be marked as dynamic. */
e8b09b87 16437 if (htab->root.dynamic_sections_created && h->dynindx == -1 && !h->forced_local
6c699715 16438 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16439 {
c152c796 16440 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16441 return FALSE;
16442 }
16443
e5a52504
MM		 16444 if (!htab->symbian_p)
16445 {
362d30a1 16446 s = htab->root.sgot;
e5a52504 16447 h->got.offset = s->size;
ba93b8ac
DJ		 16448
16449 if (tls_type == GOT_UNKNOWN)
16450 abort ();
16451
16452 if (tls_type == GOT_NORMAL)
16453 /* Non-TLS symbols need one GOT slot. */
16454 s->size += 4;
16455 else
16456 {
99059e56
RM		 16457 if (tls_type & GOT_TLS_GDESC)
16458 {
0855e32b 16459 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 16460 eh->tlsdesc_got
0855e32b
NS		 16461 = (htab->root.sgotplt->size
16462 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 16463 htab->root.sgotplt->size += 8;
16464 h->got.offset = (bfd_vma) -2;
34e77a92 16465 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16466 reloc in the middle of .got.plt. */
99059e56
RM		 16467 htab->num_tls_desc++;
16468 }
0855e32b 16469
ba93b8ac 16470 if (tls_type & GOT_TLS_GD)
0855e32b 16471 {
5c5a4843
CL		 16472 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16473 consecutive GOT slots. If the symbol is both GD
16474 and GDESC, got.offset may have been
16475 overwritten. */
0855e32b
NS		 16476 h->got.offset = s->size;
16477 s->size += 8;
16478 }
16479
ba93b8ac 16480 if (tls_type & GOT_TLS_IE)
5c5a4843
CL		 16481 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16482 slot. */
ba93b8ac
DJ		 16483 s->size += 4;
16484 }
16485
e5a52504 16486 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 16487
16488 indx = 0;
0e1862bb
L		 16489 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
16490 bfd_link_pic (info),
16491 h)
16492 && (!bfd_link_pic (info)
ba93b8ac
DJ		 16493 || !SYMBOL_REFERENCES_LOCAL (info, h)))
16494 indx = h->dynindx;
16495
16496 if (tls_type != GOT_NORMAL
9cb09e33 16497 && (bfd_link_dll (info) || indx != 0)
ba93b8ac
DJ		 16498 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16499 || h->root.type != bfd_link_hash_undefweak))
16500 {
16501 if (tls_type & GOT_TLS_IE)
47beaa6a 16502 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16503
16504 if (tls_type & GOT_TLS_GD)
47beaa6a 16505 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16506
b38cadfb 16507 if (tls_type & GOT_TLS_GDESC)
0855e32b 16508 {
47beaa6a 16509 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 16510 /* GDESC needs a trampoline to jump to. */
16511 htab->tls_trampoline = -1;
16512 }
16513
16514 /* Only GD needs it. GDESC just emits one relocation per
16515 2 entries. */
b38cadfb 16516 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 16517 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16518 }
e8b09b87
CL		 16519 else if (((indx != -1) || htab->fdpic_p)
16520 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 16521 {
16522 if (htab->root.dynamic_sections_created)
16523 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16524 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16525 }
34e77a92
RS		 16526 else if (h->type == STT_GNU_IFUNC
16527 && eh->plt.noncall_refcount == 0)
16528 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16529 they all resolve dynamically instead. Reserve room for the
16530 GOT entry's R_ARM_IRELATIVE relocation. */
16531 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 16532 else if (bfd_link_pic (info)
16533 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16534 || h->root.type != bfd_link_hash_undefweak))
b436d854 16535 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 16536 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16537 else if (htab->fdpic_p && tls_type == GOT_NORMAL)
16538 /* Reserve room for rofixup for FDPIC executable. */
16539 /* TLS relocs do not need space since they are completely
16540 resolved. */
16541 htab->srofixup->size += 4;
e5a52504 16542 }
5e681ec4
PB		 16543 }
16544 else
16545 h->got.offset = (bfd_vma) -1;
16546
e8b09b87
CL		 16547 /* FDPIC support. */
16548 if (eh->fdpic_cnts.gotofffuncdesc_cnt > 0)
16549 {
16550 /* Symbol musn't be exported. */
16551 if (h->dynindx != -1)
16552 abort();
16553
16554 /* We only allocate one function descriptor with its associated relocation. */
16555 if (eh->fdpic_cnts.funcdesc_offset == -1)
16556 {
16557 asection *s = htab->root.sgot;
16558
16559 eh->fdpic_cnts.funcdesc_offset = s->size;
16560 s->size += 8;
16561 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16562 if (bfd_link_pic(info))
16563 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16564 else
16565 htab->srofixup->size += 8;
16566 }
16567 }
16568
16569 if (eh->fdpic_cnts.gotfuncdesc_cnt > 0)
16570 {
16571 asection *s = htab->root.sgot;
16572
16573 if (htab->root.dynamic_sections_created && h->dynindx == -1
16574 && !h->forced_local)
16575 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16576 return FALSE;
16577
16578 if (h->dynindx == -1)
16579 {
16580 /* We only allocate one function descriptor with its associated relocation. q */
16581 if (eh->fdpic_cnts.funcdesc_offset == -1)
16582 {
16583
16584 eh->fdpic_cnts.funcdesc_offset = s->size;
16585 s->size += 8;
16586 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16587 if (bfd_link_pic(info))
16588 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16589 else
16590 htab->srofixup->size += 8;
16591 }
16592 }
16593
16594 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16595 R_ARM_RELATIVE/rofixup relocation on it. */
16596 eh->fdpic_cnts.gotfuncdesc_offset = s->size;
16597 s->size += 4;
16598 if (h->dynindx == -1 && !bfd_link_pic(info))
4b24dd1a 16599 htab->srofixup->size += 4;
e8b09b87 16600 else
4b24dd1a 16601 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16602 }
16603
16604 if (eh->fdpic_cnts.funcdesc_cnt > 0)
16605 {
16606 if (htab->root.dynamic_sections_created && h->dynindx == -1
16607 && !h->forced_local)
16608 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16609 return FALSE;
16610
16611 if (h->dynindx == -1)
16612 {
16613 /* We only allocate one function descriptor with its associated relocation. */
16614 if (eh->fdpic_cnts.funcdesc_offset == -1)
16615 {
16616 asection *s = htab->root.sgot;
16617
16618 eh->fdpic_cnts.funcdesc_offset = s->size;
16619 s->size += 8;
16620 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16621 if (bfd_link_pic(info))
16622 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16623 else
16624 htab->srofixup->size += 8;
16625 }
16626 }
16627 if (h->dynindx == -1 && !bfd_link_pic(info))
16628 {
16629 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16630 htab->srofixup->size += 4 * eh->fdpic_cnts.funcdesc_cnt;
16631 }
16632 else
16633 {
16634 /* Will need one dynamic reloc per reference. will be either
16635 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16636 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot,
16637 eh->fdpic_cnts.funcdesc_cnt);
16638 }
16639 }
16640
a4fd1a8e
PB		 16641 /* Allocate stubs for exported Thumb functions on v4t. */
16642 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 16643 && h->def_regular
39d911fc 16644 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 16645 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
16646 {
16647 struct elf_link_hash_entry * th;
16648 struct bfd_link_hash_entry * bh;
16649 struct elf_link_hash_entry * myh;
16650 char name[1024];
16651 asection *s;
16652 bh = NULL;
16653 /* Create a new symbol to regist the real location of the function. */
16654 s = h->root.u.def.section;
906e58ca 16655 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 16656 _bfd_generic_link_add_one_symbol (info, s->owner,
16657 name, BSF_GLOBAL, s,
16658 h->root.u.def.value,
16659 NULL, TRUE, FALSE, &bh);
16660
16661 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 16662 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 16663 myh->forced_local = 1;
39d911fc 16664 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 16665 eh->export_glue = myh;
16666 th = record_arm_to_thumb_glue (info, h);
16667 /* Point the symbol at the stub. */
16668 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 16669 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 16670 h->root.u.def.section = th->root.u.def.section;
16671 h->root.u.def.value = th->root.u.def.value & ~1;
16672 }
16673
0bdcacaf 16674 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 16675 return TRUE;
16676
16677 /* In the shared -Bsymbolic case, discard space allocated for
16678 dynamic pc-relative relocs against symbols which turn out to be
16679 defined in regular objects. For the normal shared case, discard
16680 space for pc-relative relocs that have become local due to symbol
16681 visibility changes. */
16682
e8b09b87 16683 if (bfd_link_pic (info) || htab->root.is_relocatable_executable || htab->fdpic_p)
5e681ec4 16684 {
469a3493
RM		 16685 /* Relocs that use pc_count are PC-relative forms, which will appear
16686 on something like ".long foo - ." or "movw REG, foo - .". We want
16687 calls to protected symbols to resolve directly to the function
16688 rather than going via the plt. If people want function pointer
16689 comparisons to work as expected then they should avoid writing
16690 assembly like ".long foo - .". */
ba93b8ac
DJ		 16691 if (SYMBOL_CALLS_LOCAL (info, h))
16692 {
0bdcacaf 16693 struct elf_dyn_relocs **pp;
ba93b8ac 16694
0bdcacaf 16695 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 16696 {
16697 p->count -= p->pc_count;
16698 p->pc_count = 0;
16699 if (p->count == 0)
16700 *pp = p->next;
16701 else
16702 pp = &p->next;
16703 }
16704 }
16705
4dfe6ac6 16706 if (htab->vxworks_p)
3348747a 16707 {
0bdcacaf 16708 struct elf_dyn_relocs **pp;
3348747a 16709
0bdcacaf 16710 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 16711 {
0bdcacaf 16712 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 16713 *pp = p->next;
16714 else
16715 pp = &p->next;
16716 }
16717 }
16718
ba93b8ac 16719 /* Also discard relocs on undefined weak syms with non-default
99059e56 16720 visibility. */
0bdcacaf 16721 if (eh->dyn_relocs != NULL
5e681ec4 16722 && h->root.type == bfd_link_hash_undefweak)
22d606e9 16723 {
95b03e4a
L		 16724 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16725 || UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
0bdcacaf 16726 eh->dyn_relocs = NULL;
22d606e9
AM		 16727
16728 /* Make sure undefined weak symbols are output as a dynamic
16729 symbol in PIEs. */
e8b09b87 16730 else if (htab->root.dynamic_sections_created && h->dynindx == -1
22d606e9
AM		 16731 && !h->forced_local)
16732 {
16733 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16734 return FALSE;
16735 }
16736 }
16737
67687978
PB		 16738 else if (htab->root.is_relocatable_executable && h->dynindx == -1
16739 && h->root.type == bfd_link_hash_new)
16740 {
16741 /* Output absolute symbols so that we can create relocations
16742 against them. For normal symbols we output a relocation
16743 against the section that contains them. */
16744 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16745 return FALSE;
16746 }
16747
5e681ec4
PB		 16748 }
16749 else
16750 {
16751 /* For the non-shared case, discard space for relocs against
16752 symbols which turn out to need copy relocs or are not
16753 dynamic. */
16754
f5385ebf
AM		 16755 if (!h->non_got_ref
16756 && ((h->def_dynamic
16757 && !h->def_regular)
5e681ec4
PB		 16758 || (htab->root.dynamic_sections_created
16759 && (h->root.type == bfd_link_hash_undefweak
16760 || h->root.type == bfd_link_hash_undefined))))
16761 {
16762 /* Make sure this symbol is output as a dynamic symbol.
16763 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16764 if (h->dynindx == -1 && !h->forced_local
16765 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16766 {
c152c796 16767 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16768 return FALSE;
16769 }
16770
16771 /* If that succeeded, we know we'll be keeping all the
16772 relocs. */
16773 if (h->dynindx != -1)
16774 goto keep;
16775 }
16776
0bdcacaf 16777 eh->dyn_relocs = NULL;
5e681ec4
PB		 16778
16779 keep: ;
16780 }
16781
16782 /* Finally, allocate space. */
0bdcacaf 16783 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 16784 {
0bdcacaf 16785 asection *sreloc = elf_section_data (p->sec)->sreloc;
e8b09b87 16786
34e77a92
RS		 16787 if (h->type == STT_GNU_IFUNC
16788 && eh->plt.noncall_refcount == 0
16789 && SYMBOL_REFERENCES_LOCAL (info, h))
16790 elf32_arm_allocate_irelocs (info, sreloc, p->count);
e8b09b87
CL		 16791 else if (h->dynindx != -1 && (!bfd_link_pic(info) || !info->symbolic || !h->def_regular))
16792 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
16793 else if (htab->fdpic_p && !bfd_link_pic(info))
16794 htab->srofixup->size += 4 * p->count;
34e77a92
RS		 16795 else
16796 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 16797 }
16798
16799 return TRUE;
16800}
16801
63c1f59d
AM		 16802/* Set DF_TEXTREL if we find any dynamic relocs that apply to
16803 read-only sections. */
08d1f311
DJ		 16804
16805static bfd_boolean
63c1f59d 16806maybe_set_textrel (struct elf_link_hash_entry *h, void *info_p)
08d1f311 16807{
63c1f59d 16808 asection *sec;
08d1f311 16809
63c1f59d
AM		 16810 if (h->root.type == bfd_link_hash_indirect)
16811 return TRUE;
08d1f311 16812
63c1f59d
AM		 16813 sec = readonly_dynrelocs (h);
16814 if (sec != NULL)
16815 {
16816 struct bfd_link_info *info = (struct bfd_link_info *) info_p;
08d1f311 16817
63c1f59d
AM		 16818 info->flags |= DF_TEXTREL;
16819 info->callbacks->minfo
c1c8c1ef 16820 (_("%pB: dynamic relocation against `%pT' in read-only section `%pA'\n"),
63c1f59d 16821 sec->owner, h->root.root.string, sec);
08d1f311 16822
63c1f59d
AM		 16823 /* Not an error, just cut short the traversal. */
16824 return FALSE;
08d1f311 16825 }
cb10292c 16826
08d1f311
DJ		 16827 return TRUE;
16828}
16829
d504ffc8
DJ		 16830void
16831bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
16832 int byteswap_code)
16833{
16834 struct elf32_arm_link_hash_table *globals;
16835
16836 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16837 if (globals == NULL)
16838 return;
16839
d504ffc8
DJ		 16840 globals->byteswap_code = byteswap_code;
16841}
16842
252b5132
RH		 16843/* Set the sizes of the dynamic sections. */
16844
b34976b6 16845static bfd_boolean
57e8b36a
NC		 16846elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
16847 struct bfd_link_info * info)
252b5132
RH		 16848{
16849 bfd * dynobj;
16850 asection * s;
b34976b6
AM		 16851 bfd_boolean plt;
16852 bfd_boolean relocs;
5e681ec4
PB		 16853 bfd *ibfd;
16854 struct elf32_arm_link_hash_table *htab;
252b5132 16855
5e681ec4 16856 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16857 if (htab == NULL)
16858 return FALSE;
16859
252b5132
RH		 16860 dynobj = elf_hash_table (info)->dynobj;
16861 BFD_ASSERT (dynobj != NULL);
39b41c9c 16862 check_use_blx (htab);
252b5132
RH		 16863
16864 if (elf_hash_table (info)->dynamic_sections_created)
16865 {
16866 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 16867 if (bfd_link_executable (info) && !info->nointerp)
252b5132 16868 {
3d4d4302 16869 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 16870 BFD_ASSERT (s != NULL);
eea6121a 16871 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 16872 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
16873 }
16874 }
5e681ec4
PB		 16875
16876 /* Set up .got offsets for local syms, and space for local dynamic
16877 relocs. */
c72f2fb2 16878 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 16879 {
5e681ec4
PB		 16880 bfd_signed_vma *local_got;
16881 bfd_signed_vma *end_local_got;
34e77a92 16882 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 16883 char *local_tls_type;
0855e32b 16884 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 16885 bfd_size_type locsymcount;
16886 Elf_Internal_Shdr *symtab_hdr;
16887 asection *srel;
4dfe6ac6 16888 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 16889 unsigned int symndx;
e8b09b87 16890 struct fdpic_local *local_fdpic_cnts;
5e681ec4 16891
0ffa91dd 16892 if (! is_arm_elf (ibfd))
5e681ec4
PB		 16893 continue;
16894
16895 for (s = ibfd->sections; s != NULL; s = s->next)
16896 {
0bdcacaf 16897 struct elf_dyn_relocs *p;
5e681ec4 16898
0bdcacaf 16899 for (p = (struct elf_dyn_relocs *)
99059e56 16900 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 16901 {
0bdcacaf
RS		 16902 if (!bfd_is_abs_section (p->sec)
16903 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 16904 {
16905 /* Input section has been discarded, either because
16906 it is a copy of a linkonce section or due to
16907 linker script /DISCARD/, so we'll be discarding
16908 the relocs too. */
16909 }
3348747a 16910 else if (is_vxworks
0bdcacaf 16911 && strcmp (p->sec->output_section->name,
3348747a
NS		 16912 ".tls_vars") == 0)
16913 {
16914 /* Relocations in vxworks .tls_vars sections are
16915 handled specially by the loader. */
16916 }
5e681ec4
PB		 16917 else if (p->count != 0)
16918 {
0bdcacaf 16919 srel = elf_section_data (p->sec)->sreloc;
e8b09b87
CL		 16920 if (htab->fdpic_p && !bfd_link_pic(info))
16921 htab->srofixup->size += 4 * p->count;
16922 else
16923 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 16924 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 16925 info->flags |= DF_TEXTREL;
16926 }
16927 }
16928 }
16929
16930 local_got = elf_local_got_refcounts (ibfd);
16931 if (!local_got)
16932 continue;
16933
0ffa91dd 16934 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 16935 locsymcount = symtab_hdr->sh_info;
16936 end_local_got = local_got + locsymcount;
34e77a92 16937 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 16938 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 16939 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
e8b09b87 16940 local_fdpic_cnts = elf32_arm_local_fdpic_cnts (ibfd);
34e77a92 16941 symndx = 0;
362d30a1
RS		 16942 s = htab->root.sgot;
16943 srel = htab->root.srelgot;
0855e32b 16944 for (; local_got < end_local_got;
34e77a92 16945 ++local_got, ++local_iplt_ptr, ++local_tls_type,
e8b09b87 16946 ++local_tlsdesc_gotent, ++symndx, ++local_fdpic_cnts)
5e681ec4 16947 {
0855e32b 16948 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92 16949 local_iplt = *local_iplt_ptr;
e8b09b87
CL		 16950
16951 /* FDPIC support. */
16952 if (local_fdpic_cnts->gotofffuncdesc_cnt > 0)
16953 {
16954 if (local_fdpic_cnts->funcdesc_offset == -1)
16955 {
16956 local_fdpic_cnts->funcdesc_offset = s->size;
16957 s->size += 8;
16958
16959 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16960 if (bfd_link_pic(info))
16961 elf32_arm_allocate_dynrelocs (info, srel, 1);
16962 else
16963 htab->srofixup->size += 8;
16964 }
16965 }
16966
16967 if (local_fdpic_cnts->funcdesc_cnt > 0)
16968 {
16969 if (local_fdpic_cnts->funcdesc_offset == -1)
16970 {
16971 local_fdpic_cnts->funcdesc_offset = s->size;
16972 s->size += 8;
16973
16974 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16975 if (bfd_link_pic(info))
16976 elf32_arm_allocate_dynrelocs (info, srel, 1);
16977 else
16978 htab->srofixup->size += 8;
16979 }
16980
16981 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16982 if (bfd_link_pic(info))
16983 elf32_arm_allocate_dynrelocs (info, srel, local_fdpic_cnts->funcdesc_cnt);
16984 else
16985 htab->srofixup->size += 4 * local_fdpic_cnts->funcdesc_cnt;
16986 }
16987
34e77a92
RS		 16988 if (local_iplt != NULL)
16989 {
16990 struct elf_dyn_relocs *p;
16991
16992 if (local_iplt->root.refcount > 0)
16993 {
16994 elf32_arm_allocate_plt_entry (info, TRUE,
16995 &local_iplt->root,
16996 &local_iplt->arm);
16997 if (local_iplt->arm.noncall_refcount == 0)
16998 /* All references to the PLT are calls, so all
16999 non-call references can resolve directly to the
17000 run-time target. This means that the .got entry
17001 would be the same as the .igot.plt entry, so there's
17002 no point creating both. */
17003 *local_got = 0;
17004 }
17005 else
17006 {
17007 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
17008 local_iplt->root.offset = (bfd_vma) -1;
17009 }
17010
17011 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
17012 {
17013 asection *psrel;
17014
17015 psrel = elf_section_data (p->sec)->sreloc;
17016 if (local_iplt->arm.noncall_refcount == 0)
17017 elf32_arm_allocate_irelocs (info, psrel, p->count);
17018 else
17019 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
17020 }
17021 }
5e681ec4
PB		 17022 if (*local_got > 0)
17023 {
34e77a92
RS		 17024 Elf_Internal_Sym *isym;
17025
eea6121a 17026 *local_got = s->size;
ba93b8ac
DJ		 17027 if (*local_tls_type & GOT_TLS_GD)
17028 /* TLS_GD relocs need an 8-byte structure in the GOT. */
17029 s->size += 8;
0855e32b
NS		 17030 if (*local_tls_type & GOT_TLS_GDESC)
17031 {
17032 *local_tlsdesc_gotent = htab->root.sgotplt->size
17033 - elf32_arm_compute_jump_table_size (htab);
17034 htab->root.sgotplt->size += 8;
17035 *local_got = (bfd_vma) -2;
34e77a92 17036 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 17037 reloc in the middle of .got.plt. */
99059e56 17038 htab->num_tls_desc++;
0855e32b 17039 }
ba93b8ac
DJ		 17040 if (*local_tls_type & GOT_TLS_IE)
17041 s->size += 4;
ba93b8ac 17042
0855e32b
NS		 17043 if (*local_tls_type & GOT_NORMAL)
17044 {
17045 /* If the symbol is both GD and GDESC, *local_got
17046 may have been overwritten. */
17047 *local_got = s->size;
17048 s->size += 4;
17049 }
17050
34e77a92
RS		 17051 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
17052 if (isym == NULL)
17053 return FALSE;
17054
17055 /* If all references to an STT_GNU_IFUNC PLT are calls,
17056 then all non-call references, including this GOT entry,
17057 resolve directly to the run-time target. */
17058 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
17059 && (local_iplt == NULL
17060 || local_iplt->arm.noncall_refcount == 0))
17061 elf32_arm_allocate_irelocs (info, srel, 1);
e8b09b87 17062 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC || htab->fdpic_p)
0855e32b 17063 {
e8b09b87 17064 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC)))
3064e1ff 17065 elf32_arm_allocate_dynrelocs (info, srel, 1);
e8b09b87
CL		 17066 else if (htab->fdpic_p && *local_tls_type & GOT_NORMAL)
17067 htab->srofixup->size += 4;
99059e56 17068
e8b09b87
CL		 17069 if ((bfd_link_pic (info) || htab->fdpic_p)
17070 && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 17071 {
17072 elf32_arm_allocate_dynrelocs (info,
17073 htab->root.srelplt, 1);
17074 htab->tls_trampoline = -1;
17075 }
0855e32b 17076 }
5e681ec4
PB		 17077 }
17078 else
17079 *local_got = (bfd_vma) -1;
17080 }
252b5132
RH		 17081 }
17082
ba93b8ac
DJ		 17083 if (htab->tls_ldm_got.refcount > 0)
17084 {
17085 /* Allocate two GOT entries and one dynamic relocation (if necessary)
5c5a4843 17086 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
362d30a1
RS		 17087 htab->tls_ldm_got.offset = htab->root.sgot->size;
17088 htab->root.sgot->size += 8;
0e1862bb 17089 if (bfd_link_pic (info))
47beaa6a 17090 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 17091 }
17092 else
17093 htab->tls_ldm_got.offset = -1;
17094
e8b09b87
CL		 17095 /* At the very end of the .rofixup section is a pointer to the GOT,
17096 reserve space for it. */
17097 if (htab->fdpic_p && htab->srofixup != NULL)
17098 htab->srofixup->size += 4;
17099
5e681ec4
PB		 17100 /* Allocate global sym .plt and .got entries, and space for global
17101 sym dynamic relocs. */
47beaa6a 17102 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 17103
d504ffc8 17104 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 17105 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 17106 {
0ffa91dd 17107 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 17108 continue;
17109
c7b8f16e
JB		 17110 /* Initialise mapping tables for code/data. */
17111 bfd_elf32_arm_init_maps (ibfd);
906e58ca 17112
c7b8f16e 17113 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 17114 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
17115 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
90b6238f 17116 _bfd_error_handler (_("errors encountered processing file %pB"), ibfd);
c7b8f16e 17117 }
d504ffc8 17118
3e6b1042
DJ		 17119 /* Allocate space for the glue sections now that we've sized them. */
17120 bfd_elf32_arm_allocate_interworking_sections (info);
17121
0855e32b
NS		 17122 /* For every jump slot reserved in the sgotplt, reloc_count is
17123 incremented. However, when we reserve space for TLS descriptors,
17124 it's not incremented, so in order to compute the space reserved
17125 for them, it suffices to multiply the reloc count by the jump
17126 slot size. */
17127 if (htab->root.srelplt)
17128 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
17129
17130 if (htab->tls_trampoline)
17131 {
17132 if (htab->root.splt->size == 0)
17133 htab->root.splt->size += htab->plt_header_size;
b38cadfb 17134
0855e32b
NS		 17135 htab->tls_trampoline = htab->root.splt->size;
17136 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 17137
0855e32b 17138 /* If we're not using lazy TLS relocations, don't generate the
99059e56 17139 PLT and GOT entries they require. */
0855e32b
NS		 17140 if (!(info->flags & DF_BIND_NOW))
17141 {
17142 htab->dt_tlsdesc_got = htab->root.sgot->size;
17143 htab->root.sgot->size += 4;
17144
17145 htab->dt_tlsdesc_plt = htab->root.splt->size;
17146 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
17147 }
17148 }
17149
252b5132
RH		 17150 /* The check_relocs and adjust_dynamic_symbol entry points have
17151 determined the sizes of the various dynamic sections. Allocate
17152 memory for them. */
b34976b6
AM		 17153 plt = FALSE;
17154 relocs = FALSE;
252b5132
RH		 17155 for (s = dynobj->sections; s != NULL; s = s->next)
17156 {
17157 const char * name;
252b5132
RH		 17158
17159 if ((s->flags & SEC_LINKER_CREATED) == 0)
17160 continue;
17161
17162 /* It's OK to base decisions on the section name, because none
17163 of the dynobj section names depend upon the input files. */
fd361982 17164 name = bfd_section_name (s);
252b5132 17165
34e77a92 17166 if (s == htab->root.splt)
252b5132 17167 {
c456f082
AM		 17168 /* Remember whether there is a PLT. */
17169 plt = s->size != 0;
252b5132 17170 }
0112cd26 17171 else if (CONST_STRNEQ (name, ".rel"))
252b5132 17172 {
c456f082 17173 if (s->size != 0)
252b5132 17174 {
252b5132 17175 /* Remember whether there are any reloc sections other
00a97672 17176 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 17177 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 17178 relocs = TRUE;
252b5132
RH		 17179
17180 /* We use the reloc_count field as a counter if we need
17181 to copy relocs into the output file. */
17182 s->reloc_count = 0;
17183 }
17184 }
34e77a92
RS		 17185 else if (s != htab->root.sgot
17186 && s != htab->root.sgotplt
17187 && s != htab->root.iplt
17188 && s != htab->root.igotplt
5474d94f 17189 && s != htab->root.sdynbss
e8b09b87
CL		 17190 && s != htab->root.sdynrelro
17191 && s != htab->srofixup)
252b5132
RH		 17192 {
17193 /* It's not one of our sections, so don't allocate space. */
17194 continue;
17195 }
17196
c456f082 17197 if (s->size == 0)
252b5132 17198 {
c456f082 17199 /* If we don't need this section, strip it from the
00a97672
RS		 17200 output file. This is mostly to handle .rel(a).bss and
17201 .rel(a).plt. We must create both sections in
c456f082
AM		 17202 create_dynamic_sections, because they must be created
17203 before the linker maps input sections to output
17204 sections. The linker does that before
17205 adjust_dynamic_symbol is called, and it is that
17206 function which decides whether anything needs to go
17207 into these sections. */
8423293d 17208 s->flags |= SEC_EXCLUDE;
252b5132
RH		 17209 continue;
17210 }
17211
c456f082
AM		 17212 if ((s->flags & SEC_HAS_CONTENTS) == 0)
17213 continue;
17214
252b5132 17215 /* Allocate memory for the section contents. */
21d799b5 17216 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 17217 if (s->contents == NULL)
b34976b6 17218 return FALSE;
252b5132
RH		 17219 }
17220
17221 if (elf_hash_table (info)->dynamic_sections_created)
17222 {
17223 /* Add some entries to the .dynamic section. We fill in the
17224 values later, in elf32_arm_finish_dynamic_sections, but we
17225 must add the entries now so that we get the correct size for
17226 the .dynamic section. The DT_DEBUG entry is filled in by the
17227 dynamic linker and used by the debugger. */
dc810e39 17228#define add_dynamic_entry(TAG, VAL) \
5a580b3a 17229 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 17230
0e1862bb 17231 if (bfd_link_executable (info))
252b5132 17232 {
dc810e39 17233 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 17234 return FALSE;
252b5132
RH		 17235 }
17236
17237 if (plt)
17238 {
dc810e39
AM		 17239 if ( !add_dynamic_entry (DT_PLTGOT, 0)
17240 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 17241 || !add_dynamic_entry (DT_PLTREL,
17242 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 17243 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 17244 return FALSE;
0855e32b 17245
5025eb7c
AO		 17246 if (htab->dt_tlsdesc_plt
17247 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
17248 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 17249 return FALSE;
252b5132
RH		 17250 }
17251
17252 if (relocs)
17253 {
00a97672
RS		 17254 if (htab->use_rel)
17255 {
17256 if (!add_dynamic_entry (DT_REL, 0)
17257 || !add_dynamic_entry (DT_RELSZ, 0)
17258 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
17259 return FALSE;
17260 }
17261 else
17262 {
17263 if (!add_dynamic_entry (DT_RELA, 0)
17264 || !add_dynamic_entry (DT_RELASZ, 0)
17265 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
17266 return FALSE;
17267 }
252b5132
RH		 17268 }
17269
08d1f311
DJ		 17270 /* If any dynamic relocs apply to a read-only section,
17271 then we need a DT_TEXTREL entry. */
17272 if ((info->flags & DF_TEXTREL) == 0)
63c1f59d 17273 elf_link_hash_traverse (&htab->root, maybe_set_textrel, info);
08d1f311 17274
99e4ae17 17275 if ((info->flags & DF_TEXTREL) != 0)
252b5132 17276 {
dc810e39 17277 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 17278 return FALSE;
252b5132 17279 }
7a2b07ff
NS		 17280 if (htab->vxworks_p
17281 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
17282 return FALSE;
252b5132 17283 }
8532796c 17284#undef add_dynamic_entry
252b5132 17285
b34976b6 17286 return TRUE;
252b5132
RH		 17287}
17288
0855e32b
NS		 17289/* Size sections even though they're not dynamic. We use it to setup
17290 _TLS_MODULE_BASE_, if needed. */
17291
17292static bfd_boolean
17293elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 17294 struct bfd_link_info *info)
0855e32b
NS		 17295{
17296 asection *tls_sec;
cb10292c
CL		 17297 struct elf32_arm_link_hash_table *htab;
17298
17299 htab = elf32_arm_hash_table (info);
0855e32b 17300
0e1862bb 17301 if (bfd_link_relocatable (info))
0855e32b
NS		 17302 return TRUE;
17303
17304 tls_sec = elf_hash_table (info)->tls_sec;
17305
17306 if (tls_sec)
17307 {
17308 struct elf_link_hash_entry *tlsbase;
17309
17310 tlsbase = elf_link_hash_lookup
17311 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
17312
17313 if (tlsbase)
99059e56
RM		 17314 {
17315 struct bfd_link_hash_entry *bh = NULL;
0855e32b 17316 const struct elf_backend_data *bed
99059e56 17317 = get_elf_backend_data (output_bfd);
0855e32b 17318
99059e56 17319 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 17320 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
17321 tls_sec, 0, NULL, FALSE,
17322 bed->collect, &bh)))
17323 return FALSE;
b38cadfb 17324
99059e56
RM		 17325 tlsbase->type = STT_TLS;
17326 tlsbase = (struct elf_link_hash_entry *)bh;
17327 tlsbase->def_regular = 1;
17328 tlsbase->other = STV_HIDDEN;
17329 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 17330 }
17331 }
cb10292c
CL		 17332
17333 if (htab->fdpic_p && !bfd_link_relocatable (info)
17334 && !bfd_elf_stack_segment_size (output_bfd, info,
17335 "__stacksize", DEFAULT_STACK_SIZE))
17336 return FALSE;
17337
0855e32b
NS		 17338 return TRUE;
17339}
17340
252b5132
RH		 17341/* Finish up dynamic symbol handling. We set the contents of various
17342 dynamic sections here. */
17343
b34976b6 17344static bfd_boolean
906e58ca
NC		 17345elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
17346 struct bfd_link_info * info,
17347 struct elf_link_hash_entry * h,
17348 Elf_Internal_Sym * sym)
252b5132 17349{
e5a52504 17350 struct elf32_arm_link_hash_table *htab;
b7693d02 17351 struct elf32_arm_link_hash_entry *eh;
252b5132 17352
e5a52504 17353 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17354 if (htab == NULL)
17355 return FALSE;
17356
b7693d02 17357 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 17358
17359 if (h->plt.offset != (bfd_vma) -1)
17360 {
34e77a92 17361 if (!eh->is_iplt)
e5a52504 17362 {
34e77a92 17363 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 17364 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
17365 h->dynindx, 0))
17366 return FALSE;
e5a52504 17367 }
57e8b36a 17368
f5385ebf 17369 if (!h->def_regular)
252b5132
RH		 17370 {
17371 /* Mark the symbol as undefined, rather than as defined in
3a635617 17372 the .plt section. */
252b5132 17373 sym->st_shndx = SHN_UNDEF;
3a635617 17374 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 17375 Otherwise, the PLT entry would provide a definition for
17376 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 17377 and so the symbol would never be NULL. Leave the value if
17378 there were any relocations where pointer equality matters
17379 (this is a clue for the dynamic linker, to make function
17380 pointer comparisons work between an application and shared
17381 library). */
97323ad1 17382 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 17383 sym->st_value = 0;
252b5132 17384 }
34e77a92
RS		 17385 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
17386 {
17387 /* At least one non-call relocation references this .iplt entry,
17388 so the .iplt entry is the function's canonical address. */
17389 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 17390 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 17391 sym->st_shndx = (_bfd_elf_section_from_bfd_section
17392 (output_bfd, htab->root.iplt->output_section));
17393 sym->st_value = (h->plt.offset
17394 + htab->root.iplt->output_section->vma
17395 + htab->root.iplt->output_offset);
17396 }
252b5132
RH		 17397 }
17398
f5385ebf 17399 if (h->needs_copy)
252b5132
RH		 17400 {
17401 asection * s;
947216bf 17402 Elf_Internal_Rela rel;
252b5132
RH		 17403
17404 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 17405 BFD_ASSERT (h->dynindx != -1
17406 && (h->root.type == bfd_link_hash_defined
17407 || h->root.type == bfd_link_hash_defweak));
17408
00a97672 17409 rel.r_addend = 0;
252b5132
RH		 17410 rel.r_offset = (h->root.u.def.value
17411 + h->root.u.def.section->output_section->vma
17412 + h->root.u.def.section->output_offset);
17413 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 17414 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 17415 s = htab->root.sreldynrelro;
17416 else
17417 s = htab->root.srelbss;
47beaa6a 17418 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 17419 }
17420
00a97672 17421 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
fac7bd64
CL		 17422 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17423 it is relative to the ".got" section. */
9637f6ef 17424 if (h == htab->root.hdynamic
fac7bd64 17425 || (!htab->fdpic_p && !htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 17426 sym->st_shndx = SHN_ABS;
17427
b34976b6 17428 return TRUE;
252b5132
RH		 17429}
17430
0855e32b
NS		 17431static void
17432arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17433 void *contents,
17434 const unsigned long *template, unsigned count)
17435{
17436 unsigned ix;
b38cadfb 17437
0855e32b
NS		 17438 for (ix = 0; ix != count; ix++)
17439 {
17440 unsigned long insn = template[ix];
17441
17442 /* Emit mov pc,rx if bx is not permitted. */
17443 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
17444 insn = (insn & 0xf000000f) | 0x01a0f000;
17445 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
17446 }
17447}
17448
99059e56
RM		 17449/* Install the special first PLT entry for elf32-arm-nacl. Unlike
17450 other variants, NaCl needs this entry in a static executable's
17451 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17452 zero. For .iplt really only the last bundle is useful, and .iplt
17453 could have a shorter first entry, with each individual PLT entry's
17454 relative branch calculated differently so it targets the last
17455 bundle instead of the instruction before it (labelled .Lplt_tail
17456 above). But it's simpler to keep the size and layout of PLT0
17457 consistent with the dynamic case, at the cost of some dead code at
17458 the start of .iplt and the one dead store to the stack at the start
17459 of .Lplt_tail. */
17460static void
17461arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17462 asection *plt, bfd_vma got_displacement)
17463{
17464 unsigned int i;
17465
17466 put_arm_insn (htab, output_bfd,
17467 elf32_arm_nacl_plt0_entry[0]
17468 | arm_movw_immediate (got_displacement),
17469 plt->contents + 0);
17470 put_arm_insn (htab, output_bfd,
17471 elf32_arm_nacl_plt0_entry[1]
17472 | arm_movt_immediate (got_displacement),
17473 plt->contents + 4);
17474
17475 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
17476 put_arm_insn (htab, output_bfd,
17477 elf32_arm_nacl_plt0_entry[i],
17478 plt->contents + (i * 4));
17479}
17480
252b5132
RH		 17481/* Finish up the dynamic sections. */
17482
b34976b6 17483static bfd_boolean
57e8b36a 17484elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 17485{
17486 bfd * dynobj;
17487 asection * sgot;
17488 asection * sdyn;
4dfe6ac6
NC		 17489 struct elf32_arm_link_hash_table *htab;
17490
17491 htab = elf32_arm_hash_table (info);
17492 if (htab == NULL)
17493 return FALSE;
252b5132
RH		 17494
17495 dynobj = elf_hash_table (info)->dynobj;
17496
362d30a1 17497 sgot = htab->root.sgotplt;
894891db
NC		 17498 /* A broken linker script might have discarded the dynamic sections.
17499 Catch this here so that we do not seg-fault later on. */
17500 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
17501 return FALSE;
3d4d4302 17502 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 17503
17504 if (elf_hash_table (info)->dynamic_sections_created)
17505 {
17506 asection *splt;
17507 Elf32_External_Dyn *dyncon, *dynconend;
17508
362d30a1 17509 splt = htab->root.splt;
24a1ba0f 17510 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 17511 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 17512
17513 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 17514 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 17515
252b5132
RH		 17516 for (; dyncon < dynconend; dyncon++)
17517 {
17518 Elf_Internal_Dyn dyn;
17519 const char * name;
17520 asection * s;
17521
17522 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
17523
17524 switch (dyn.d_tag)
17525 {
229fcec5
MM		 17526 unsigned int type;
17527
252b5132 17528 default:
7a2b07ff
NS		 17529 if (htab->vxworks_p
17530 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
17531 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 17532 break;
17533
229fcec5
MM		 17534 case DT_HASH:
17535 name = ".hash";
17536 goto get_vma_if_bpabi;
17537 case DT_STRTAB:
17538 name = ".dynstr";
17539 goto get_vma_if_bpabi;
17540 case DT_SYMTAB:
17541 name = ".dynsym";
17542 goto get_vma_if_bpabi;
c0042f5d
MM		 17543 case DT_VERSYM:
17544 name = ".gnu.version";
17545 goto get_vma_if_bpabi;
17546 case DT_VERDEF:
17547 name = ".gnu.version_d";
17548 goto get_vma_if_bpabi;
17549 case DT_VERNEED:
17550 name = ".gnu.version_r";
17551 goto get_vma_if_bpabi;
17552
252b5132 17553 case DT_PLTGOT:
4ade44b7 17554 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 17555 goto get_vma;
17556 case DT_JMPREL:
00a97672 17557 name = RELOC_SECTION (htab, ".plt");
252b5132 17558 get_vma:
4ade44b7 17559 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 17560 if (s == NULL)
17561 {
4eca0228 17562 _bfd_error_handler
4ade44b7 17563 (_("could not find section %s"), name);
05456594
NC		 17564 bfd_set_error (bfd_error_invalid_operation);
17565 return FALSE;
17566 }
229fcec5 17567 if (!htab->symbian_p)
4ade44b7 17568 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 17569 else
17570 /* In the BPABI, tags in the PT_DYNAMIC section point
17571 at the file offset, not the memory address, for the
17572 convenience of the post linker. */
4ade44b7 17573 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 17574 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17575 break;
17576
229fcec5
MM		 17577 get_vma_if_bpabi:
17578 if (htab->symbian_p)
17579 goto get_vma;
17580 break;
17581
252b5132 17582 case DT_PLTRELSZ:
362d30a1 17583 s = htab->root.srelplt;
252b5132 17584 BFD_ASSERT (s != NULL);
eea6121a 17585 dyn.d_un.d_val = s->size;
252b5132
RH		 17586 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17587 break;
906e58ca 17588
252b5132 17589 case DT_RELSZ:
00a97672 17590 case DT_RELASZ:
229fcec5
MM		 17591 case DT_REL:
17592 case DT_RELA:
229fcec5
MM		 17593 /* In the BPABI, the DT_REL tag must point at the file
17594 offset, not the VMA, of the first relocation
17595 section. So, we use code similar to that in
17596 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 17597 relocation section, since relocation sections are
17598 never allocated under the BPABI. PLT relocs are also
17599 included. */
229fcec5
MM		 17600 if (htab->symbian_p)
17601 {
17602 unsigned int i;
17603 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
17604 ? SHT_REL : SHT_RELA);
17605 dyn.d_un.d_val = 0;
17606 for (i = 1; i < elf_numsections (output_bfd); i++)
17607 {
906e58ca 17608 Elf_Internal_Shdr *hdr
229fcec5
MM		 17609 = elf_elfsections (output_bfd)[i];
17610 if (hdr->sh_type == type)
17611 {
906e58ca 17612 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 17613 || dyn.d_tag == DT_RELASZ)
17614 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 17615 else if ((ufile_ptr) hdr->sh_offset
17616 <= dyn.d_un.d_val - 1)
229fcec5
MM		 17617 dyn.d_un.d_val = hdr->sh_offset;
17618 }
17619 }
17620 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17621 }
252b5132 17622 break;
88f7bcd5 17623
0855e32b 17624 case DT_TLSDESC_PLT:
99059e56 17625 s = htab->root.splt;
0855e32b
NS		 17626 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
17627 + htab->dt_tlsdesc_plt);
17628 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17629 break;
17630
17631 case DT_TLSDESC_GOT:
99059e56 17632 s = htab->root.sgot;
0855e32b 17633 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 17634 + htab->dt_tlsdesc_got);
0855e32b
NS		 17635 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17636 break;
17637
88f7bcd5
NC		 17638 /* Set the bottom bit of DT_INIT/FINI if the
17639 corresponding function is Thumb. */
17640 case DT_INIT:
17641 name = info->init_function;
17642 goto get_sym;
17643 case DT_FINI:
17644 name = info->fini_function;
17645 get_sym:
17646 /* If it wasn't set by elf_bfd_final_link
4cc11e76 17647 then there is nothing to adjust. */
88f7bcd5
NC		 17648 if (dyn.d_un.d_val != 0)
17649 {
17650 struct elf_link_hash_entry * eh;
17651
17652 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 17653 FALSE, FALSE, TRUE);
39d911fc
TP		 17654 if (eh != NULL
17655 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
17656 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 17657 {
17658 dyn.d_un.d_val |= 1;
b34976b6 17659 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 17660 }
17661 }
17662 break;
252b5132
RH		 17663 }
17664 }
17665
24a1ba0f 17666 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 17667 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 17668 {
00a97672
RS		 17669 const bfd_vma *plt0_entry;
17670 bfd_vma got_address, plt_address, got_displacement;
17671
17672 /* Calculate the addresses of the GOT and PLT. */
17673 got_address = sgot->output_section->vma + sgot->output_offset;
17674 plt_address = splt->output_section->vma + splt->output_offset;
17675
17676 if (htab->vxworks_p)
17677 {
17678 /* The VxWorks GOT is relocated by the dynamic linker.
17679 Therefore, we must emit relocations rather than simply
17680 computing the values now. */
17681 Elf_Internal_Rela rel;
17682
17683 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 17684 put_arm_insn (htab, output_bfd, plt0_entry[0],
17685 splt->contents + 0);
17686 put_arm_insn (htab, output_bfd, plt0_entry[1],
17687 splt->contents + 4);
17688 put_arm_insn (htab, output_bfd, plt0_entry[2],
17689 splt->contents + 8);
00a97672
RS		 17690 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
17691
8029a119 17692 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 17693 rel.r_offset = plt_address + 12;
17694 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17695 rel.r_addend = 0;
17696 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
17697 htab->srelplt2->contents);
17698 }
b38cadfb 17699 else if (htab->nacl_p)
99059e56
RM		 17700 arm_nacl_put_plt0 (htab, output_bfd, splt,
17701 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 17702 else if (using_thumb_only (htab))
17703 {
17704 got_displacement = got_address - (plt_address + 12);
17705
17706 plt0_entry = elf32_thumb2_plt0_entry;
17707 put_arm_insn (htab, output_bfd, plt0_entry[0],
17708 splt->contents + 0);
17709 put_arm_insn (htab, output_bfd, plt0_entry[1],
17710 splt->contents + 4);
17711 put_arm_insn (htab, output_bfd, plt0_entry[2],
17712 splt->contents + 8);
17713
17714 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
17715 }
00a97672
RS		 17716 else
17717 {
17718 got_displacement = got_address - (plt_address + 16);
17719
17720 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 17721 put_arm_insn (htab, output_bfd, plt0_entry[0],
17722 splt->contents + 0);
17723 put_arm_insn (htab, output_bfd, plt0_entry[1],
17724 splt->contents + 4);
17725 put_arm_insn (htab, output_bfd, plt0_entry[2],
17726 splt->contents + 8);
17727 put_arm_insn (htab, output_bfd, plt0_entry[3],
17728 splt->contents + 12);
5e681ec4 17729
5e681ec4 17730#ifdef FOUR_WORD_PLT
00a97672
RS		 17731 /* The displacement value goes in the otherwise-unused
17732 last word of the second entry. */
17733 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 17734#else
00a97672 17735 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 17736#endif
00a97672 17737 }
f7a74f8c 17738 }
252b5132
RH		 17739
17740 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17741 really seem like the right value. */
74541ad4
AM		 17742 if (splt->output_section->owner == output_bfd)
17743 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 17744
0855e32b
NS		 17745 if (htab->dt_tlsdesc_plt)
17746 {
17747 bfd_vma got_address
17748 = sgot->output_section->vma + sgot->output_offset;
17749 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
17750 + htab->root.sgot->output_offset);
17751 bfd_vma plt_address
17752 = splt->output_section->vma + splt->output_offset;
17753
b38cadfb 17754 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17755 splt->contents + htab->dt_tlsdesc_plt,
17756 dl_tlsdesc_lazy_trampoline, 6);
17757
17758 bfd_put_32 (output_bfd,
17759 gotplt_address + htab->dt_tlsdesc_got
17760 - (plt_address + htab->dt_tlsdesc_plt)
17761 - dl_tlsdesc_lazy_trampoline[6],
17762 splt->contents + htab->dt_tlsdesc_plt + 24);
17763 bfd_put_32 (output_bfd,
17764 got_address - (plt_address + htab->dt_tlsdesc_plt)
17765 - dl_tlsdesc_lazy_trampoline[7],
17766 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
17767 }
17768
17769 if (htab->tls_trampoline)
17770 {
b38cadfb 17771 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17772 splt->contents + htab->tls_trampoline,
17773 tls_trampoline, 3);
17774#ifdef FOUR_WORD_PLT
17775 bfd_put_32 (output_bfd, 0x00000000,
17776 splt->contents + htab->tls_trampoline + 12);
b38cadfb 17777#endif
0855e32b
NS		 17778 }
17779
0e1862bb
L		 17780 if (htab->vxworks_p
17781 && !bfd_link_pic (info)
17782 && htab->root.splt->size > 0)
00a97672
RS		 17783 {
17784 /* Correct the .rel(a).plt.unloaded relocations. They will have
17785 incorrect symbol indexes. */
17786 int num_plts;
eed62c48 17787 unsigned char *p;
00a97672 17788
362d30a1 17789 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 17790 / htab->plt_entry_size);
17791 p = htab->srelplt2->contents + RELOC_SIZE (htab);
17792
17793 for (; num_plts; num_plts--)
17794 {
17795 Elf_Internal_Rela rel;
17796
17797 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17798 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17799 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17800 p += RELOC_SIZE (htab);
17801
17802 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17803 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
17804 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17805 p += RELOC_SIZE (htab);
17806 }
17807 }
252b5132
RH		 17808 }
17809
99059e56
RM		 17810 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
17811 /* NaCl uses a special first entry in .iplt too. */
17812 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
17813
252b5132 17814 /* Fill in the first three entries in the global offset table. */
229fcec5 17815 if (sgot)
252b5132 17816 {
229fcec5
MM		 17817 if (sgot->size > 0)
17818 {
17819 if (sdyn == NULL)
17820 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
17821 else
17822 bfd_put_32 (output_bfd,
17823 sdyn->output_section->vma + sdyn->output_offset,
17824 sgot->contents);
17825 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
17826 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
17827 }
252b5132 17828
229fcec5
MM		 17829 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
17830 }
252b5132 17831
e8b09b87
CL		 17832 /* At the very end of the .rofixup section is a pointer to the GOT. */
17833 if (htab->fdpic_p && htab->srofixup != NULL)
17834 {
17835 struct elf_link_hash_entry *hgot = htab->root.hgot;
17836
17837 bfd_vma got_value = hgot->root.u.def.value
17838 + hgot->root.u.def.section->output_section->vma
17839 + hgot->root.u.def.section->output_offset;
17840
17841 arm_elf_add_rofixup(output_bfd, htab->srofixup, got_value);
17842
17843 /* Make sure we allocated and generated the same number of fixups. */
17844 BFD_ASSERT (htab->srofixup->reloc_count * 4 == htab->srofixup->size);
17845 }
17846
b34976b6 17847 return TRUE;
252b5132
RH		 17848}
17849
ba96a88f 17850static void
57e8b36a 17851elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 17852{
9b485d32 17853 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 17854 struct elf32_arm_link_hash_table *globals;
ac4c9b04 17855 struct elf_segment_map *m;
ba96a88f
NC		 17856
17857 i_ehdrp = elf_elfheader (abfd);
17858
94a3258f
PB		 17859 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
17860 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
17861 else
7394f108 17862 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 17863 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 17864
93204d3a
PB		 17865 if (link_info)
17866 {
17867 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 17868 if (globals != NULL && globals->byteswap_code)
93204d3a 17869 i_ehdrp->e_flags |= EF_ARM_BE8;
18a20338
CL		 17870
17871 if (globals->fdpic_p)
17872 i_ehdrp->e_ident[EI_OSABI] |= ELFOSABI_ARM_FDPIC;
93204d3a 17873 }
3bfcb652
NC		 17874
17875 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
17876 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
17877 {
17878 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 17879 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 17880 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
17881 else
17882 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
17883 }
ac4c9b04
MG		 17884
17885 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 17886 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 17887 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
17888 {
17889 unsigned int j;
17890
17891 if (m->count == 0)
17892 continue;
17893 for (j = 0; j < m->count; j++)
17894 {
f0728ee3 17895 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 17896 break;
17897 }
17898 if (j == m->count)
17899 {
17900 m->p_flags = PF_X;
17901 m->p_flags_valid = 1;
17902 }
17903 }
ba96a88f
NC		 17904}
17905
99e4ae17 17906static enum elf_reloc_type_class
7e612e98
AM		 17907elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
17908 const asection *rel_sec ATTRIBUTE_UNUSED,
17909 const Elf_Internal_Rela *rela)
99e4ae17 17910{
f51e552e 17911 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 17912 {
17913 case R_ARM_RELATIVE:
17914 return reloc_class_relative;
17915 case R_ARM_JUMP_SLOT:
17916 return reloc_class_plt;
17917 case R_ARM_COPY:
17918 return reloc_class_copy;
109575d7
JW		 17919 case R_ARM_IRELATIVE:
17920 return reloc_class_ifunc;
99e4ae17
AJ		 17921 default:
17922 return reloc_class_normal;
17923 }
17924}
17925
e489d0ae 17926static void
cc364be6 17927arm_final_write_processing (bfd *abfd)
e16bb312 17928{
5a6c6817 17929 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 17930}
17931
cc364be6
AM		 17932static bfd_boolean
17933elf32_arm_final_write_processing (bfd *abfd)
06f44071 17934{
cc364be6
AM		 17935 arm_final_write_processing (abfd);
17936 return _bfd_elf_final_write_processing (abfd);
06f44071
AM		 17937}
17938
40a18ebd
NC		 17939/* Return TRUE if this is an unwinding table entry. */
17940
17941static bfd_boolean
17942is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
17943{
0112cd26
NC		 17944 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
17945 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 17946}
17947
17948
17949/* Set the type and flags for an ARM section. We do this by
17950 the section name, which is a hack, but ought to work. */
17951
17952static bfd_boolean
17953elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
17954{
17955 const char * name;
17956
fd361982 17957 name = bfd_section_name (sec);
40a18ebd
NC		 17958
17959 if (is_arm_elf_unwind_section_name (abfd, name))
17960 {
17961 hdr->sh_type = SHT_ARM_EXIDX;
17962 hdr->sh_flags |= SHF_LINK_ORDER;
17963 }
ac4c9b04 17964
f0728ee3
AV		 17965 if (sec->flags & SEC_ELF_PURECODE)
17966 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 17967
40a18ebd
NC		 17968 return TRUE;
17969}
17970
6dc132d9
L		 17971/* Handle an ARM specific section when reading an object file. This is
17972 called when bfd_section_from_shdr finds a section with an unknown
17973 type. */
40a18ebd
NC		 17974
17975static bfd_boolean
17976elf32_arm_section_from_shdr (bfd *abfd,
17977 Elf_Internal_Shdr * hdr,
6dc132d9
L		 17978 const char *name,
17979 int shindex)
40a18ebd
NC		 17980{
17981 /* There ought to be a place to keep ELF backend specific flags, but
17982 at the moment there isn't one. We just keep track of the
17983 sections by their name, instead. Fortunately, the ABI gives
17984 names for all the ARM specific sections, so we will probably get
17985 away with this. */
17986 switch (hdr->sh_type)
17987 {
17988 case SHT_ARM_EXIDX:
0951f019
RE		 17989 case SHT_ARM_PREEMPTMAP:
17990 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 17991 break;
17992
17993 default:
17994 return FALSE;
17995 }
17996
6dc132d9 17997 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 17998 return FALSE;
17999
18000 return TRUE;
18001}
e489d0ae 18002
44444f50
NC		 18003static _arm_elf_section_data *
18004get_arm_elf_section_data (asection * sec)
18005{
47b2e99c
JZ		 18006 if (sec && sec->owner && is_arm_elf (sec->owner))
18007 return elf32_arm_section_data (sec);
44444f50
NC		 18008 else
18009 return NULL;
8e3de13a
NC		 18010}
18011
4e617b1e
PB		 18012typedef struct
18013{
57402f1e 18014 void *flaginfo;
4e617b1e 18015 struct bfd_link_info *info;
91a5743d
PB		 18016 asection *sec;
18017 int sec_shndx;
6e0b88f1
AM		 18018 int (*func) (void *, const char *, Elf_Internal_Sym *,
18019 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 18020} output_arch_syminfo;
18021
18022enum map_symbol_type
18023{
18024 ARM_MAP_ARM,
18025 ARM_MAP_THUMB,
18026 ARM_MAP_DATA
18027};
18028
18029
7413f23f 18030/* Output a single mapping symbol. */
4e617b1e
PB		 18031
18032static bfd_boolean
7413f23f
DJ		 18033elf32_arm_output_map_sym (output_arch_syminfo *osi,
18034 enum map_symbol_type type,
18035 bfd_vma offset)
4e617b1e
PB		 18036{
18037 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 18038 Elf_Internal_Sym sym;
18039
91a5743d
PB		 18040 sym.st_value = osi->sec->output_section->vma
18041 + osi->sec->output_offset
18042 + offset;
4e617b1e
PB		 18043 sym.st_size = 0;
18044 sym.st_other = 0;
18045 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 18046 sym.st_shndx = osi->sec_shndx;
35fc36a8 18047 sym.st_target_internal = 0;
fe33d2fa 18048 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 18049 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 18050}
18051
34e77a92
RS		 18052/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
18053 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 18054
18055static bfd_boolean
34e77a92
RS		 18056elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
18057 bfd_boolean is_iplt_entry_p,
18058 union gotplt_union *root_plt,
18059 struct arm_plt_info *arm_plt)
4e617b1e 18060{
4e617b1e 18061 struct elf32_arm_link_hash_table *htab;
34e77a92 18062 bfd_vma addr, plt_header_size;
4e617b1e 18063
34e77a92 18064 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 18065 return TRUE;
18066
4dfe6ac6
NC		 18067 htab = elf32_arm_hash_table (osi->info);
18068 if (htab == NULL)
18069 return FALSE;
18070
34e77a92
RS		 18071 if (is_iplt_entry_p)
18072 {
18073 osi->sec = htab->root.iplt;
18074 plt_header_size = 0;
18075 }
18076 else
18077 {
18078 osi->sec = htab->root.splt;
18079 plt_header_size = htab->plt_header_size;
18080 }
18081 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
18082 (osi->info->output_bfd, osi->sec->output_section));
18083
18084 addr = root_plt->offset & -2;
4e617b1e
PB		 18085 if (htab->symbian_p)
18086 {
7413f23f 18087 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18088 return FALSE;
7413f23f 18089 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 18090 return FALSE;
18091 }
18092 else if (htab->vxworks_p)
18093 {
7413f23f 18094 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18095 return FALSE;
7413f23f 18096 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 18097 return FALSE;
7413f23f 18098 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 18099 return FALSE;
7413f23f 18100 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 18101 return FALSE;
18102 }
b38cadfb
NC		 18103 else if (htab->nacl_p)
18104 {
18105 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
18106 return FALSE;
18107 }
7801f98f
CL		 18108 else if (htab->fdpic_p)
18109 {
59029f57
CL		 18110 enum map_symbol_type type = using_thumb_only(htab)
18111 ? ARM_MAP_THUMB
18112 : ARM_MAP_ARM;
18113
7801f98f 18114 if (elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt))
4b24dd1a
AM		 18115 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
18116 return FALSE;
59029f57 18117 if (!elf32_arm_output_map_sym (osi, type, addr))
4b24dd1a 18118 return FALSE;
7801f98f 18119 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 16))
4b24dd1a 18120 return FALSE;
7801f98f 18121 if (htab->plt_entry_size == 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry))
4b24dd1a
AM		 18122 if (!elf32_arm_output_map_sym (osi, type, addr + 24))
18123 return FALSE;
7801f98f 18124 }
eed94f8f
NC		 18125 else if (using_thumb_only (htab))
18126 {
18127 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
18128 return FALSE;
6a631e86 18129 }
4e617b1e
PB		 18130 else
18131 {
34e77a92 18132 bfd_boolean thumb_stub_p;
bd97cb95 18133
34e77a92
RS		 18134 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
18135 if (thumb_stub_p)
4e617b1e 18136 {
7413f23f 18137 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 18138 return FALSE;
18139 }
18140#ifdef FOUR_WORD_PLT
7413f23f 18141 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18142 return FALSE;
7413f23f 18143 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 18144 return FALSE;
18145#else
906e58ca 18146 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 18147 so only need to output a mapping symbol for the first PLT entry and
18148 entries with thumb thunks. */
34e77a92 18149 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 18150 {
7413f23f 18151 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 18152 return FALSE;
18153 }
18154#endif
18155 }
18156
18157 return TRUE;
18158}
18159
34e77a92
RS		 18160/* Output mapping symbols for PLT entries associated with H. */
18161
18162static bfd_boolean
18163elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
18164{
18165 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
18166 struct elf32_arm_link_hash_entry *eh;
18167
18168 if (h->root.type == bfd_link_hash_indirect)
18169 return TRUE;
18170
18171 if (h->root.type == bfd_link_hash_warning)
18172 /* When warning symbols are created, they **replace** the "real"
18173 entry in the hash table, thus we never get to see the real
18174 symbol in a hash traversal. So look at it now. */
18175 h = (struct elf_link_hash_entry *) h->root.u.i.link;
18176
18177 eh = (struct elf32_arm_link_hash_entry *) h;
18178 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
18179 &h->plt, &eh->plt);
18180}
18181
4f4faa4d
TP		 18182/* Bind a veneered symbol to its veneer identified by its hash entry
18183 STUB_ENTRY. The veneered location thus loose its symbol. */
18184
18185static void
18186arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
18187{
18188 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
18189
18190 BFD_ASSERT (hash);
18191 hash->root.root.u.def.section = stub_entry->stub_sec;
18192 hash->root.root.u.def.value = stub_entry->stub_offset;
18193 hash->root.size = stub_entry->stub_size;
18194}
18195
7413f23f
DJ		 18196/* Output a single local symbol for a generated stub. */
18197
18198static bfd_boolean
18199elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
18200 bfd_vma offset, bfd_vma size)
18201{
7413f23f
DJ		 18202 Elf_Internal_Sym sym;
18203
7413f23f
DJ		 18204 sym.st_value = osi->sec->output_section->vma
18205 + osi->sec->output_offset
18206 + offset;
18207 sym.st_size = size;
18208 sym.st_other = 0;
18209 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
18210 sym.st_shndx = osi->sec_shndx;
35fc36a8 18211 sym.st_target_internal = 0;
57402f1e 18212 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 18213}
4e617b1e 18214
da5938a2 18215static bfd_boolean
8029a119
NC		 18216arm_map_one_stub (struct bfd_hash_entry * gen_entry,
18217 void * in_arg)
da5938a2
NC		 18218{
18219 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 18220 asection *stub_sec;
18221 bfd_vma addr;
7413f23f 18222 char *stub_name;
9a008db3 18223 output_arch_syminfo *osi;
d3ce72d0 18224 const insn_sequence *template_sequence;
461a49ca
DJ		 18225 enum stub_insn_type prev_type;
18226 int size;
18227 int i;
18228 enum map_symbol_type sym_type;
da5938a2
NC		 18229
18230 /* Massage our args to the form they really have. */
18231 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 18232 osi = (output_arch_syminfo *) in_arg;
da5938a2 18233
da5938a2
NC		 18234 stub_sec = stub_entry->stub_sec;
18235
18236 /* Ensure this stub is attached to the current section being
7413f23f 18237 processed. */
da5938a2
NC		 18238 if (stub_sec != osi->sec)
18239 return TRUE;
18240
7413f23f 18241 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 18242 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 18243
18244 if (arm_stub_sym_claimed (stub_entry->stub_type))
18245 arm_stub_claim_sym (stub_entry);
18246 else
7413f23f 18247 {
4f4faa4d
TP		 18248 stub_name = stub_entry->output_name;
18249 switch (template_sequence[0].type)
18250 {
18251 case ARM_TYPE:
18252 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
18253 stub_entry->stub_size))
18254 return FALSE;
18255 break;
18256 case THUMB16_TYPE:
18257 case THUMB32_TYPE:
18258 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
18259 stub_entry->stub_size))
18260 return FALSE;
18261 break;
18262 default:
18263 BFD_FAIL ();
18264 return 0;
18265 }
7413f23f 18266 }
da5938a2 18267
461a49ca
DJ		 18268 prev_type = DATA_TYPE;
18269 size = 0;
18270 for (i = 0; i < stub_entry->stub_template_size; i++)
18271 {
d3ce72d0 18272 switch (template_sequence[i].type)
461a49ca
DJ		 18273 {
18274 case ARM_TYPE:
18275 sym_type = ARM_MAP_ARM;
18276 break;
18277
18278 case THUMB16_TYPE:
48229727 18279 case THUMB32_TYPE:
461a49ca
DJ		 18280 sym_type = ARM_MAP_THUMB;
18281 break;
18282
18283 case DATA_TYPE:
18284 sym_type = ARM_MAP_DATA;
18285 break;
18286
18287 default:
18288 BFD_FAIL ();
4e31c731 18289 return FALSE;
461a49ca
DJ		 18290 }
18291
d3ce72d0 18292 if (template_sequence[i].type != prev_type)
461a49ca 18293 {
d3ce72d0 18294 prev_type = template_sequence[i].type;
461a49ca
DJ		 18295 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
18296 return FALSE;
18297 }
18298
d3ce72d0 18299 switch (template_sequence[i].type)
461a49ca
DJ		 18300 {
18301 case ARM_TYPE:
48229727 18302 case THUMB32_TYPE:
461a49ca
DJ		 18303 size += 4;
18304 break;
18305
18306 case THUMB16_TYPE:
18307 size += 2;
18308 break;
18309
18310 case DATA_TYPE:
18311 size += 4;
18312 break;
18313
18314 default:
18315 BFD_FAIL ();
4e31c731 18316 return FALSE;
461a49ca
DJ		 18317 }
18318 }
18319
da5938a2
NC		 18320 return TRUE;
18321}
18322
33811162
DG		 18323/* Output mapping symbols for linker generated sections,
18324 and for those data-only sections that do not have a
18325 $d. */
4e617b1e
PB		 18326
18327static bfd_boolean
18328elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 18329 struct bfd_link_info *info,
57402f1e 18330 void *flaginfo,
6e0b88f1
AM		 18331 int (*func) (void *, const char *,
18332 Elf_Internal_Sym *,
18333 asection *,
18334 struct elf_link_hash_entry *))
4e617b1e
PB		 18335{
18336 output_arch_syminfo osi;
18337 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 18338 bfd_vma offset;
18339 bfd_size_type size;
33811162 18340 bfd *input_bfd;
4e617b1e
PB		 18341
18342 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 18343 if (htab == NULL)
18344 return FALSE;
18345
906e58ca 18346 check_use_blx (htab);
91a5743d 18347
57402f1e 18348 osi.flaginfo = flaginfo;
4e617b1e
PB		 18349 osi.info = info;
18350 osi.func = func;
906e58ca 18351
33811162
DG		 18352 /* Add a $d mapping symbol to data-only sections that
18353 don't have any mapping symbol. This may result in (harmless) redundant
18354 mapping symbols. */
18355 for (input_bfd = info->input_bfds;
18356 input_bfd != NULL;
c72f2fb2 18357 input_bfd = input_bfd->link.next)
33811162
DG		 18358 {
18359 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
18360 for (osi.sec = input_bfd->sections;
18361 osi.sec != NULL;
18362 osi.sec = osi.sec->next)
18363 {
18364 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 18365 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
18366 != 0)
33811162
DG		 18367 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
18368 == SEC_HAS_CONTENTS
18369 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 18370 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 18371 && osi.sec->size > 0
18372 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 18373 {
18374 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18375 (output_bfd, osi.sec->output_section);
18376 if (osi.sec_shndx != (int)SHN_BAD)
18377 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
18378 }
18379 }
18380 }
18381
91a5743d
PB		 18382 /* ARM->Thumb glue. */
18383 if (htab->arm_glue_size > 0)
18384 {
3d4d4302
AM		 18385 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18386 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 18387
18388 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18389 (output_bfd, osi.sec->output_section);
0e1862bb 18390 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 18391 || htab->pic_veneer)
18392 size = ARM2THUMB_PIC_GLUE_SIZE;
18393 else if (htab->use_blx)
18394 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
18395 else
18396 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 18397
91a5743d
PB		 18398 for (offset = 0; offset < htab->arm_glue_size; offset += size)
18399 {
7413f23f
DJ		 18400 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
18401 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 18402 }
18403 }
18404
18405 /* Thumb->ARM glue. */
18406 if (htab->thumb_glue_size > 0)
18407 {
3d4d4302
AM		 18408 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18409 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 18410
18411 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18412 (output_bfd, osi.sec->output_section);
18413 size = THUMB2ARM_GLUE_SIZE;
18414
18415 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
18416 {
7413f23f
DJ		 18417 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
18418 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 18419 }
18420 }
18421
845b51d6
PB		 18422 /* ARMv4 BX veneers. */
18423 if (htab->bx_glue_size > 0)
18424 {
3d4d4302
AM		 18425 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18426 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 18427
18428 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18429 (output_bfd, osi.sec->output_section);
18430
7413f23f 18431 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 18432 }
18433
8029a119
NC		 18434 /* Long calls stubs. */
18435 if (htab->stub_bfd && htab->stub_bfd->sections)
18436 {
da5938a2 18437 asection* stub_sec;
8029a119 18438
da5938a2
NC		 18439 for (stub_sec = htab->stub_bfd->sections;
18440 stub_sec != NULL;
8029a119
NC		 18441 stub_sec = stub_sec->next)
18442 {
18443 /* Ignore non-stub sections. */
18444 if (!strstr (stub_sec->name, STUB_SUFFIX))
18445 continue;
da5938a2 18446
8029a119 18447 osi.sec = stub_sec;
da5938a2 18448
8029a119
NC		 18449 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18450 (output_bfd, osi.sec->output_section);
da5938a2 18451
8029a119
NC		 18452 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
18453 }
18454 }
da5938a2 18455
91a5743d 18456 /* Finally, output mapping symbols for the PLT. */
34e77a92 18457 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 18458 {
34e77a92
RS		 18459 osi.sec = htab->root.splt;
18460 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18461 (output_bfd, osi.sec->output_section));
18462
18463 /* Output mapping symbols for the plt header. SymbianOS does not have a
18464 plt header. */
18465 if (htab->vxworks_p)
18466 {
18467 /* VxWorks shared libraries have no PLT header. */
0e1862bb 18468 if (!bfd_link_pic (info))
34e77a92
RS		 18469 {
18470 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18471 return FALSE;
18472 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18473 return FALSE;
18474 }
18475 }
b38cadfb
NC		 18476 else if (htab->nacl_p)
18477 {
18478 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18479 return FALSE;
18480 }
59029f57 18481 else if (using_thumb_only (htab) && !htab->fdpic_p)
eed94f8f
NC		 18482 {
18483 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
18484 return FALSE;
18485 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18486 return FALSE;
18487 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
18488 return FALSE;
18489 }
e8b09b87 18490 else if (!htab->symbian_p && !htab->fdpic_p)
4e617b1e 18491 {
7413f23f 18492 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 18493 return FALSE;
34e77a92
RS		 18494#ifndef FOUR_WORD_PLT
18495 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 18496 return FALSE;
34e77a92 18497#endif
4e617b1e
PB		 18498 }
18499 }
99059e56
RM		 18500 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
18501 {
18502 /* NaCl uses a special first entry in .iplt too. */
18503 osi.sec = htab->root.iplt;
18504 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18505 (output_bfd, osi.sec->output_section));
18506 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18507 return FALSE;
18508 }
34e77a92
RS		 18509 if ((htab->root.splt && htab->root.splt->size > 0)
18510 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 18511 {
34e77a92
RS		 18512 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
18513 for (input_bfd = info->input_bfds;
18514 input_bfd != NULL;
c72f2fb2 18515 input_bfd = input_bfd->link.next)
34e77a92
RS		 18516 {
18517 struct arm_local_iplt_info **local_iplt;
18518 unsigned int i, num_syms;
4e617b1e 18519
34e77a92
RS		 18520 local_iplt = elf32_arm_local_iplt (input_bfd);
18521 if (local_iplt != NULL)
18522 {
18523 num_syms = elf_symtab_hdr (input_bfd).sh_info;
18524 for (i = 0; i < num_syms; i++)
18525 if (local_iplt[i] != NULL
18526 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
18527 &local_iplt[i]->root,
18528 &local_iplt[i]->arm))
18529 return FALSE;
18530 }
18531 }
18532 }
0855e32b
NS		 18533 if (htab->dt_tlsdesc_plt != 0)
18534 {
18535 /* Mapping symbols for the lazy tls trampoline. */
18536 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
18537 return FALSE;
b38cadfb 18538
0855e32b
NS		 18539 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18540 htab->dt_tlsdesc_plt + 24))
18541 return FALSE;
18542 }
18543 if (htab->tls_trampoline != 0)
18544 {
18545 /* Mapping symbols for the tls trampoline. */
18546 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
18547 return FALSE;
18548#ifdef FOUR_WORD_PLT
18549 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18550 htab->tls_trampoline + 12))
18551 return FALSE;
b38cadfb 18552#endif
0855e32b 18553 }
b38cadfb 18554
4e617b1e
PB		 18555 return TRUE;
18556}
18557
54ddd295
TP		 18558/* Filter normal symbols of CMSE entry functions of ABFD to include in
18559 the import library. All SYMCOUNT symbols of ABFD can be examined
18560 from their pointers in SYMS. Pointers of symbols to keep should be
18561 stored continuously at the beginning of that array.
18562
18563 Returns the number of symbols to keep. */
18564
18565static unsigned int
18566elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18567 struct bfd_link_info *info,
18568 asymbol **syms, long symcount)
18569{
18570 size_t maxnamelen;
18571 char *cmse_name;
18572 long src_count, dst_count = 0;
18573 struct elf32_arm_link_hash_table *htab;
18574
18575 htab = elf32_arm_hash_table (info);
18576 if (!htab->stub_bfd || !htab->stub_bfd->sections)
18577 symcount = 0;
18578
18579 maxnamelen = 128;
18580 cmse_name = (char *) bfd_malloc (maxnamelen);
18581 for (src_count = 0; src_count < symcount; src_count++)
18582 {
18583 struct elf32_arm_link_hash_entry *cmse_hash;
18584 asymbol *sym;
18585 flagword flags;
18586 char *name;
18587 size_t namelen;
18588
18589 sym = syms[src_count];
18590 flags = sym->flags;
18591 name = (char *) bfd_asymbol_name (sym);
18592
18593 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
18594 continue;
18595 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
18596 continue;
18597
18598 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
18599 if (namelen > maxnamelen)
18600 {
18601 cmse_name = (char *)
18602 bfd_realloc (cmse_name, namelen);
18603 maxnamelen = namelen;
18604 }
18605 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
18606 cmse_hash = (struct elf32_arm_link_hash_entry *)
18607 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
18608
18609 if (!cmse_hash
18610 || (cmse_hash->root.root.type != bfd_link_hash_defined
18611 && cmse_hash->root.root.type != bfd_link_hash_defweak)
18612 || cmse_hash->root.type != STT_FUNC)
18613 continue;
18614
54ddd295
TP		 18615 syms[dst_count++] = sym;
18616 }
18617 free (cmse_name);
18618
18619 syms[dst_count] = NULL;
18620
18621 return dst_count;
18622}
18623
18624/* Filter symbols of ABFD to include in the import library. All
18625 SYMCOUNT symbols of ABFD can be examined from their pointers in
18626 SYMS. Pointers of symbols to keep should be stored continuously at
18627 the beginning of that array.
18628
18629 Returns the number of symbols to keep. */
18630
18631static unsigned int
18632elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18633 struct bfd_link_info *info,
18634 asymbol **syms, long symcount)
18635{
18636 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
18637
046734ff
TP		 18638 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18639 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18640 library to be a relocatable object file. */
18641 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
54ddd295
TP		 18642 if (globals->cmse_implib)
18643 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
18644 else
18645 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
18646}
18647
e489d0ae
PB		 18648/* Allocate target specific section data. */
18649
18650static bfd_boolean
18651elf32_arm_new_section_hook (bfd *abfd, asection *sec)
18652{
f592407e
AM		 18653 if (!sec->used_by_bfd)
18654 {
18655 _arm_elf_section_data *sdata;
18656 bfd_size_type amt = sizeof (*sdata);
e489d0ae 18657
21d799b5 18658 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 18659 if (sdata == NULL)
18660 return FALSE;
18661 sec->used_by_bfd = sdata;
18662 }
e489d0ae
PB		 18663
18664 return _bfd_elf_new_section_hook (abfd, sec);
18665}
18666
18667
18668/* Used to order a list of mapping symbols by address. */
18669
18670static int
18671elf32_arm_compare_mapping (const void * a, const void * b)
18672{
7f6a71ff
JM		 18673 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
18674 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
18675
18676 if (amap->vma > bmap->vma)
18677 return 1;
18678 else if (amap->vma < bmap->vma)
18679 return -1;
18680 else if (amap->type > bmap->type)
18681 /* Ensure results do not depend on the host qsort for objects with
18682 multiple mapping symbols at the same address by sorting on type
18683 after vma. */
18684 return 1;
18685 else if (amap->type < bmap->type)
18686 return -1;
18687 else
18688 return 0;
e489d0ae
PB		 18689}
18690
2468f9c9
PB		 18691/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18692
18693static unsigned long
18694offset_prel31 (unsigned long addr, bfd_vma offset)
18695{
18696 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
18697}
18698
18699/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18700 relocations. */
18701
18702static void
18703copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
18704{
18705 unsigned long first_word = bfd_get_32 (output_bfd, from);
18706 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 18707
2468f9c9
PB		 18708 /* High bit of first word is supposed to be zero. */
18709 if ((first_word & 0x80000000ul) == 0)
18710 first_word = offset_prel31 (first_word, offset);
b38cadfb 18711
2468f9c9
PB		 18712 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18713 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18714 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
18715 second_word = offset_prel31 (second_word, offset);
b38cadfb 18716
2468f9c9
PB		 18717 bfd_put_32 (output_bfd, first_word, to);
18718 bfd_put_32 (output_bfd, second_word, to + 4);
18719}
e489d0ae 18720
48229727
JB		 18721/* Data for make_branch_to_a8_stub(). */
18722
b38cadfb
NC		 18723struct a8_branch_to_stub_data
18724{
48229727
JB		 18725 asection *writing_section;
18726 bfd_byte *contents;
18727};
18728
18729
18730/* Helper to insert branches to Cortex-A8 erratum stubs in the right
18731 places for a particular section. */
18732
18733static bfd_boolean
18734make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 18735 void *in_arg)
48229727
JB		 18736{
18737 struct elf32_arm_stub_hash_entry *stub_entry;
18738 struct a8_branch_to_stub_data *data;
18739 bfd_byte *contents;
18740 unsigned long branch_insn;
18741 bfd_vma veneered_insn_loc, veneer_entry_loc;
18742 bfd_signed_vma branch_offset;
18743 bfd *abfd;
8d9d9490 18744 unsigned int loc;
48229727
JB		 18745
18746 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
18747 data = (struct a8_branch_to_stub_data *) in_arg;
18748
18749 if (stub_entry->target_section != data->writing_section
4563a860 18750 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 18751 return TRUE;
18752
18753 contents = data->contents;
18754
8d9d9490
TP		 18755 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18756 generated when both source and target are in the same section. */
48229727
JB		 18757 veneered_insn_loc = stub_entry->target_section->output_section->vma
18758 + stub_entry->target_section->output_offset
8d9d9490 18759 + stub_entry->source_value;
48229727
JB		 18760
18761 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
18762 + stub_entry->stub_sec->output_offset
18763 + stub_entry->stub_offset;
18764
18765 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
18766 veneered_insn_loc &= ~3u;
18767
18768 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
18769
18770 abfd = stub_entry->target_section->owner;
8d9d9490 18771 loc = stub_entry->source_value;
48229727
JB		 18772
18773 /* We attempt to avoid this condition by setting stubs_always_after_branch
18774 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18775 This check is just to be on the safe side... */
18776 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
18777 {
871b3ab2 18778 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub is "
4eca0228 18779 "allocated in unsafe location"), abfd);
48229727
JB		 18780 return FALSE;
18781 }
18782
18783 switch (stub_entry->stub_type)
18784 {
18785 case arm_stub_a8_veneer_b:
18786 case arm_stub_a8_veneer_b_cond:
18787 branch_insn = 0xf0009000;
18788 goto jump24;
18789
18790 case arm_stub_a8_veneer_blx:
18791 branch_insn = 0xf000e800;
18792 goto jump24;
18793
18794 case arm_stub_a8_veneer_bl:
18795 {
18796 unsigned int i1, j1, i2, j2, s;
18797
18798 branch_insn = 0xf000d000;
18799
18800 jump24:
18801 if (branch_offset < -16777216 || branch_offset > 16777214)
18802 {
18803 /* There's not much we can do apart from complain if this
18804 happens. */
871b3ab2 18805 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub out "
4eca0228 18806 "of range (input file too large)"), abfd);
48229727
JB		 18807 return FALSE;
18808 }
18809
18810 /* i1 = not(j1 eor s), so:
18811 not i1 = j1 eor s
18812 j1 = (not i1) eor s. */
18813
18814 branch_insn |= (branch_offset >> 1) & 0x7ff;
18815 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
18816 i2 = (branch_offset >> 22) & 1;
18817 i1 = (branch_offset >> 23) & 1;
18818 s = (branch_offset >> 24) & 1;
18819 j1 = (!i1) ^ s;
18820 j2 = (!i2) ^ s;
18821 branch_insn |= j2 << 11;
18822 branch_insn |= j1 << 13;
18823 branch_insn |= s << 26;
18824 }
18825 break;
18826
18827 default:
18828 BFD_FAIL ();
18829 return FALSE;
18830 }
18831
8d9d9490
TP		 18832 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
18833 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 18834
18835 return TRUE;
18836}
18837
a504d23a
LA		 18838/* Beginning of stm32l4xx work-around. */
18839
18840/* Functions encoding instructions necessary for the emission of the
18841 fix-stm32l4xx-629360.
18842 Encoding is extracted from the
18843 ARM (C) Architecture Reference Manual
18844 ARMv7-A and ARMv7-R edition
18845 ARM DDI 0406C.b (ID072512). */
18846
18847static inline bfd_vma
82188b29 18848create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 18849{
18850 /* A8.8.18 B (A8-334)
18851 B target_address (Encoding T4). */
18852 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18853 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18854 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18855
a504d23a
LA		 18856 int s = ((branch_offset & 0x1000000) >> 24);
18857 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
18858 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
18859
18860 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
18861 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
18862
18863 bfd_vma patched_inst = 0xf0009000
18864 | s << 26 /* S. */
18865 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
18866 | j1 << 13 /* J1. */
18867 | j2 << 11 /* J2. */
18868 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
18869
18870 return patched_inst;
18871}
18872
18873static inline bfd_vma
18874create_instruction_ldmia (int base_reg, int wback, int reg_mask)
18875{
18876 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18877 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18878 bfd_vma patched_inst = 0xe8900000
18879 | (/*W=*/wback << 21)
18880 | (base_reg << 16)
18881 | (reg_mask & 0x0000ffff);
18882
18883 return patched_inst;
18884}
18885
18886static inline bfd_vma
18887create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
18888{
18889 /* A8.8.60 LDMDB/LDMEA (A8-402)
18890 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18891 bfd_vma patched_inst = 0xe9100000
18892 | (/*W=*/wback << 21)
18893 | (base_reg << 16)
18894 | (reg_mask & 0x0000ffff);
18895
18896 return patched_inst;
18897}
18898
18899static inline bfd_vma
18900create_instruction_mov (int target_reg, int source_reg)
18901{
18902 /* A8.8.103 MOV (register) (A8-486)
18903 MOV Rd, Rm (Encoding T1). */
18904 bfd_vma patched_inst = 0x4600
18905 | (target_reg & 0x7)
18906 | ((target_reg & 0x8) >> 3) << 7
18907 | (source_reg << 3);
18908
18909 return patched_inst;
18910}
18911
18912static inline bfd_vma
18913create_instruction_sub (int target_reg, int source_reg, int value)
18914{
18915 /* A8.8.221 SUB (immediate) (A8-708)
18916 SUB Rd, Rn, #value (Encoding T3). */
18917 bfd_vma patched_inst = 0xf1a00000
18918 | (target_reg << 8)
18919 | (source_reg << 16)
18920 | (/*S=*/0 << 20)
18921 | ((value & 0x800) >> 11) << 26
18922 | ((value & 0x700) >> 8) << 12
18923 | (value & 0x0ff);
18924
18925 return patched_inst;
18926}
18927
18928static inline bfd_vma
9239bbd3 18929create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 18930 int first_reg)
18931{
18932 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18933 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18934 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 18935 | (/*W=*/wback << 21)
18936 | (base_reg << 16)
9239bbd3
CM		 18937 | (num_words & 0x000000ff)
18938 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 18939 | (first_reg & 0x00000001) << 22;
18940
18941 return patched_inst;
18942}
18943
18944static inline bfd_vma
9239bbd3
CM		 18945create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
18946 int first_reg)
a504d23a
LA		 18947{
18948 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18949 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18950 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 18951 | (base_reg << 16)
9239bbd3
CM		 18952 | (num_words & 0x000000ff)
18953 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 18954 | (first_reg & 0x00000001) << 22;
18955
18956 return patched_inst;
18957}
18958
18959static inline bfd_vma
18960create_instruction_udf_w (int value)
18961{
18962 /* A8.8.247 UDF (A8-758)
18963 Undefined (Encoding T2). */
18964 bfd_vma patched_inst = 0xf7f0a000
18965 | (value & 0x00000fff)
18966 | (value & 0x000f0000) << 16;
18967
18968 return patched_inst;
18969}
18970
18971static inline bfd_vma
18972create_instruction_udf (int value)
18973{
18974 /* A8.8.247 UDF (A8-758)
18975 Undefined (Encoding T1). */
18976 bfd_vma patched_inst = 0xde00
18977 | (value & 0xff);
18978
18979 return patched_inst;
18980}
18981
18982/* Functions writing an instruction in memory, returning the next
18983 memory position to write to. */
18984
18985static inline bfd_byte *
18986push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
18987 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18988{
18989 put_thumb2_insn (htab, output_bfd, insn, pt);
18990 return pt + 4;
18991}
18992
18993static inline bfd_byte *
18994push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
18995 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18996{
18997 put_thumb_insn (htab, output_bfd, insn, pt);
18998 return pt + 2;
18999}
19000
19001/* Function filling up a region in memory with T1 and T2 UDFs taking
19002 care of alignment. */
19003
19004static bfd_byte *
19005stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
07d6d2b8
AM		 19006 bfd * output_bfd,
19007 const bfd_byte * const base_stub_contents,
19008 bfd_byte * const from_stub_contents,
19009 const bfd_byte * const end_stub_contents)
a504d23a
LA		 19010{
19011 bfd_byte *current_stub_contents = from_stub_contents;
19012
19013 /* Fill the remaining of the stub with deterministic contents : UDF
19014 instructions.
19015 Check if realignment is needed on modulo 4 frontier using T1, to
19016 further use T2. */
19017 if ((current_stub_contents < end_stub_contents)
19018 && !((current_stub_contents - base_stub_contents) % 2)
19019 && ((current_stub_contents - base_stub_contents) % 4))
19020 current_stub_contents =
19021 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19022 create_instruction_udf (0));
19023
19024 for (; current_stub_contents < end_stub_contents;)
19025 current_stub_contents =
19026 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19027 create_instruction_udf_w (0));
19028
19029 return current_stub_contents;
19030}
19031
19032/* Functions writing the stream of instructions equivalent to the
19033 derived sequence for ldmia, ldmdb, vldm respectively. */
19034
19035static void
19036stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
19037 bfd * output_bfd,
19038 const insn32 initial_insn,
19039 const bfd_byte *const initial_insn_addr,
19040 bfd_byte *const base_stub_contents)
19041{
19042 int wback = (initial_insn & 0x00200000) >> 21;
19043 int ri, rn = (initial_insn & 0x000F0000) >> 16;
19044 int insn_all_registers = initial_insn & 0x0000ffff;
19045 int insn_low_registers, insn_high_registers;
19046 int usable_register_mask;
b25e998d 19047 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 19048 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
19049 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
19050 bfd_byte *current_stub_contents = base_stub_contents;
19051
19052 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
19053
19054 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19055 smaller than 8 registers load sequences that do not cause the
19056 hardware issue. */
19057 if (nb_registers <= 8)
19058 {
19059 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
19060 current_stub_contents =
19061 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19062 initial_insn);
19063
19064 /* B initial_insn_addr+4. */
19065 if (!restore_pc)
19066 current_stub_contents =
19067 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19068 create_instruction_branch_absolute
82188b29 19069 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19070
19071 /* Fill the remaining of the stub with deterministic contents. */
19072 current_stub_contents =
19073 stm32l4xx_fill_stub_udf (htab, output_bfd,
19074 base_stub_contents, current_stub_contents,
19075 base_stub_contents +
19076 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19077
19078 return;
19079 }
19080
19081 /* - reg_list[13] == 0. */
19082 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
19083
19084 /* - reg_list[14] & reg_list[15] != 1. */
19085 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
19086
19087 /* - if (wback==1) reg_list[rn] == 0. */
19088 BFD_ASSERT (!wback || !restore_rn);
19089
19090 /* - nb_registers > 8. */
b25e998d 19091 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19092
19093 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19094
19095 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
19096 - One with the 7 lowest registers (register mask 0x007F)
19097 This LDM will finally contain between 2 and 7 registers
19098 - One with the 7 highest registers (register mask 0xDF80)
19099 This ldm will finally contain between 2 and 7 registers. */
19100 insn_low_registers = insn_all_registers & 0x007F;
19101 insn_high_registers = insn_all_registers & 0xDF80;
19102
19103 /* A spare register may be needed during this veneer to temporarily
19104 handle the base register. This register will be restored with the
19105 last LDM operation.
19106 The usable register may be any general purpose register (that
19107 excludes PC, SP, LR : register mask is 0x1FFF). */
19108 usable_register_mask = 0x1FFF;
19109
19110 /* Generate the stub function. */
19111 if (wback)
19112 {
19113 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
19114 current_stub_contents =
19115 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19116 create_instruction_ldmia
19117 (rn, /*wback=*/1, insn_low_registers));
19118
19119 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
19120 current_stub_contents =
19121 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19122 create_instruction_ldmia
19123 (rn, /*wback=*/1, insn_high_registers));
19124 if (!restore_pc)
19125 {
19126 /* B initial_insn_addr+4. */
19127 current_stub_contents =
19128 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19129 create_instruction_branch_absolute
82188b29 19130 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19131 }
19132 }
19133 else /* if (!wback). */
19134 {
19135 ri = rn;
19136
19137 /* If Rn is not part of the high-register-list, move it there. */
19138 if (!(insn_high_registers & (1 << rn)))
19139 {
19140 /* Choose a Ri in the high-register-list that will be restored. */
19141 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19142
19143 /* MOV Ri, Rn. */
19144 current_stub_contents =
19145 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19146 create_instruction_mov (ri, rn));
19147 }
19148
19149 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
19150 current_stub_contents =
19151 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19152 create_instruction_ldmia
19153 (ri, /*wback=*/1, insn_low_registers));
19154
19155 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
19156 current_stub_contents =
19157 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19158 create_instruction_ldmia
19159 (ri, /*wback=*/0, insn_high_registers));
19160
19161 if (!restore_pc)
19162 {
19163 /* B initial_insn_addr+4. */
19164 current_stub_contents =
19165 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19166 create_instruction_branch_absolute
82188b29 19167 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19168 }
19169 }
19170
19171 /* Fill the remaining of the stub with deterministic contents. */
19172 current_stub_contents =
19173 stm32l4xx_fill_stub_udf (htab, output_bfd,
19174 base_stub_contents, current_stub_contents,
19175 base_stub_contents +
19176 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19177}
19178
19179static void
19180stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
19181 bfd * output_bfd,
19182 const insn32 initial_insn,
19183 const bfd_byte *const initial_insn_addr,
19184 bfd_byte *const base_stub_contents)
19185{
19186 int wback = (initial_insn & 0x00200000) >> 21;
19187 int ri, rn = (initial_insn & 0x000f0000) >> 16;
19188 int insn_all_registers = initial_insn & 0x0000ffff;
19189 int insn_low_registers, insn_high_registers;
19190 int usable_register_mask;
19191 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
19192 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 19193 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 19194 bfd_byte *current_stub_contents = base_stub_contents;
19195
19196 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
19197
19198 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19199 smaller than 8 registers load sequences that do not cause the
19200 hardware issue. */
19201 if (nb_registers <= 8)
19202 {
19203 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
19204 current_stub_contents =
19205 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19206 initial_insn);
19207
19208 /* B initial_insn_addr+4. */
19209 current_stub_contents =
19210 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19211 create_instruction_branch_absolute
82188b29 19212 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19213
19214 /* Fill the remaining of the stub with deterministic contents. */
19215 current_stub_contents =
19216 stm32l4xx_fill_stub_udf (htab, output_bfd,
19217 base_stub_contents, current_stub_contents,
19218 base_stub_contents +
19219 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19220
19221 return;
19222 }
19223
19224 /* - reg_list[13] == 0. */
19225 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
19226
19227 /* - reg_list[14] & reg_list[15] != 1. */
19228 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
19229
19230 /* - if (wback==1) reg_list[rn] == 0. */
19231 BFD_ASSERT (!wback || !restore_rn);
19232
19233 /* - nb_registers > 8. */
b25e998d 19234 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19235
19236 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19237
19238 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
19239 - One with the 7 lowest registers (register mask 0x007F)
19240 This LDM will finally contain between 2 and 7 registers
19241 - One with the 7 highest registers (register mask 0xDF80)
19242 This ldm will finally contain between 2 and 7 registers. */
19243 insn_low_registers = insn_all_registers & 0x007F;
19244 insn_high_registers = insn_all_registers & 0xDF80;
19245
19246 /* A spare register may be needed during this veneer to temporarily
19247 handle the base register. This register will be restored with
19248 the last LDM operation.
19249 The usable register may be any general purpose register (that excludes
19250 PC, SP, LR : register mask is 0x1FFF). */
19251 usable_register_mask = 0x1FFF;
19252
19253 /* Generate the stub function. */
19254 if (!wback && !restore_pc && !restore_rn)
19255 {
19256 /* Choose a Ri in the low-register-list that will be restored. */
19257 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19258
19259 /* MOV Ri, Rn. */
19260 current_stub_contents =
19261 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19262 create_instruction_mov (ri, rn));
19263
19264 /* LDMDB Ri!, {R-high-register-list}. */
19265 current_stub_contents =
19266 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19267 create_instruction_ldmdb
19268 (ri, /*wback=*/1, insn_high_registers));
19269
19270 /* LDMDB Ri, {R-low-register-list}. */
19271 current_stub_contents =
19272 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19273 create_instruction_ldmdb
19274 (ri, /*wback=*/0, insn_low_registers));
19275
19276 /* B initial_insn_addr+4. */
19277 current_stub_contents =
19278 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19279 create_instruction_branch_absolute
82188b29 19280 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19281 }
19282 else if (wback && !restore_pc && !restore_rn)
19283 {
19284 /* LDMDB Rn!, {R-high-register-list}. */
19285 current_stub_contents =
19286 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19287 create_instruction_ldmdb
19288 (rn, /*wback=*/1, insn_high_registers));
19289
19290 /* LDMDB Rn!, {R-low-register-list}. */
19291 current_stub_contents =
19292 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19293 create_instruction_ldmdb
19294 (rn, /*wback=*/1, insn_low_registers));
19295
19296 /* B initial_insn_addr+4. */
19297 current_stub_contents =
19298 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19299 create_instruction_branch_absolute
82188b29 19300 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19301 }
19302 else if (!wback && restore_pc && !restore_rn)
19303 {
19304 /* Choose a Ri in the high-register-list that will be restored. */
19305 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19306
19307 /* SUB Ri, Rn, #(4*nb_registers). */
19308 current_stub_contents =
19309 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19310 create_instruction_sub (ri, rn, (4 * nb_registers)));
19311
19312 /* LDMIA Ri!, {R-low-register-list}. */
19313 current_stub_contents =
19314 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19315 create_instruction_ldmia
19316 (ri, /*wback=*/1, insn_low_registers));
19317
19318 /* LDMIA Ri, {R-high-register-list}. */
19319 current_stub_contents =
19320 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19321 create_instruction_ldmia
19322 (ri, /*wback=*/0, insn_high_registers));
19323 }
19324 else if (wback && restore_pc && !restore_rn)
19325 {
19326 /* Choose a Ri in the high-register-list that will be restored. */
19327 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19328
19329 /* SUB Rn, Rn, #(4*nb_registers) */
19330 current_stub_contents =
19331 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19332 create_instruction_sub (rn, rn, (4 * nb_registers)));
19333
19334 /* MOV Ri, Rn. */
19335 current_stub_contents =
19336 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19337 create_instruction_mov (ri, rn));
19338
19339 /* LDMIA Ri!, {R-low-register-list}. */
19340 current_stub_contents =
19341 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19342 create_instruction_ldmia
19343 (ri, /*wback=*/1, insn_low_registers));
19344
19345 /* LDMIA Ri, {R-high-register-list}. */
19346 current_stub_contents =
19347 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19348 create_instruction_ldmia
19349 (ri, /*wback=*/0, insn_high_registers));
19350 }
19351 else if (!wback && !restore_pc && restore_rn)
19352 {
19353 ri = rn;
19354 if (!(insn_low_registers & (1 << rn)))
19355 {
19356 /* Choose a Ri in the low-register-list that will be restored. */
19357 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19358
19359 /* MOV Ri, Rn. */
19360 current_stub_contents =
19361 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19362 create_instruction_mov (ri, rn));
19363 }
19364
19365 /* LDMDB Ri!, {R-high-register-list}. */
19366 current_stub_contents =
19367 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19368 create_instruction_ldmdb
19369 (ri, /*wback=*/1, insn_high_registers));
19370
19371 /* LDMDB Ri, {R-low-register-list}. */
19372 current_stub_contents =
19373 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19374 create_instruction_ldmdb
19375 (ri, /*wback=*/0, insn_low_registers));
19376
19377 /* B initial_insn_addr+4. */
19378 current_stub_contents =
19379 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19380 create_instruction_branch_absolute
82188b29 19381 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19382 }
19383 else if (!wback && restore_pc && restore_rn)
19384 {
19385 ri = rn;
19386 if (!(insn_high_registers & (1 << rn)))
19387 {
19388 /* Choose a Ri in the high-register-list that will be restored. */
19389 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19390 }
19391
19392 /* SUB Ri, Rn, #(4*nb_registers). */
19393 current_stub_contents =
19394 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19395 create_instruction_sub (ri, rn, (4 * nb_registers)));
19396
19397 /* LDMIA Ri!, {R-low-register-list}. */
19398 current_stub_contents =
19399 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19400 create_instruction_ldmia
19401 (ri, /*wback=*/1, insn_low_registers));
19402
19403 /* LDMIA Ri, {R-high-register-list}. */
19404 current_stub_contents =
19405 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19406 create_instruction_ldmia
19407 (ri, /*wback=*/0, insn_high_registers));
19408 }
19409 else if (wback && restore_rn)
19410 {
19411 /* The assembler should not have accepted to encode this. */
19412 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
19413 "undefined behavior.\n");
19414 }
19415
19416 /* Fill the remaining of the stub with deterministic contents. */
19417 current_stub_contents =
19418 stm32l4xx_fill_stub_udf (htab, output_bfd,
19419 base_stub_contents, current_stub_contents,
19420 base_stub_contents +
19421 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19422
19423}
19424
19425static void
19426stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
19427 bfd * output_bfd,
19428 const insn32 initial_insn,
19429 const bfd_byte *const initial_insn_addr,
19430 bfd_byte *const base_stub_contents)
19431{
9239bbd3 19432 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 19433 bfd_byte *current_stub_contents = base_stub_contents;
19434
19435 BFD_ASSERT (is_thumb2_vldm (initial_insn));
19436
19437 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 19438 smaller than 8 words load sequences that do not cause the
a504d23a 19439 hardware issue. */
9239bbd3 19440 if (num_words <= 8)
a504d23a
LA		 19441 {
19442 /* Untouched instruction. */
19443 current_stub_contents =
19444 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19445 initial_insn);
19446
19447 /* B initial_insn_addr+4. */
19448 current_stub_contents =
19449 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19450 create_instruction_branch_absolute
82188b29 19451 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19452 }
19453 else
19454 {
9eaff861 19455 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 19456 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 19457 bfd_boolean is_ia_nobang = /* (IA without !). */
19458 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
19459 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
19460 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
19461 bfd_boolean is_db_bang = /* (DB with !). */
19462 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 19463 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 19464 /* d = UInt (Vd:D);. */
9239bbd3 19465 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 19466 | (((unsigned int)initial_insn << 9) >> 31);
19467
9239bbd3
CM		 19468 /* Compute the number of 8-words chunks needed to split. */
19469 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 19470 int chunk;
19471
19472 /* The test coverage has been done assuming the following
19473 hypothesis that exactly one of the previous is_ predicates is
19474 true. */
9239bbd3
CM		 19475 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
19476 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 19477
9239bbd3 19478 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 19479 cases, then we emit the adjustments:
19480
19481 vldm rx, {...}
19482 -> vldm rx!, {8_words_or_less} for each needed 8_word
19483 -> sub rx, rx, #size (list)
19484
19485 vldm rx!, {...}
19486 -> vldm rx!, {8_words_or_less} for each needed 8_word
19487 This also handles vpop instruction (when rx is sp)
19488
19489 vldmd rx!, {...}
19490 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 19491 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 19492 {
9239bbd3
CM		 19493 bfd_vma new_insn = 0;
19494
a504d23a
LA		 19495 if (is_ia_nobang || is_ia_bang)
19496 {
9239bbd3
CM		 19497 new_insn = create_instruction_vldmia
19498 (base_reg,
19499 is_dp,
19500 /*wback= . */1,
19501 chunks - (chunk + 1) ?
19502 8 : num_words - chunk * 8,
19503 first_reg + chunk * 8);
a504d23a
LA		 19504 }
19505 else if (is_db_bang)
19506 {
9239bbd3
CM		 19507 new_insn = create_instruction_vldmdb
19508 (base_reg,
19509 is_dp,
19510 chunks - (chunk + 1) ?
19511 8 : num_words - chunk * 8,
19512 first_reg + chunk * 8);
a504d23a 19513 }
9239bbd3
CM		 19514
19515 if (new_insn)
19516 current_stub_contents =
19517 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19518 new_insn);
a504d23a
LA		 19519 }
19520
19521 /* Only this case requires the base register compensation
19522 subtract. */
19523 if (is_ia_nobang)
19524 {
19525 current_stub_contents =
19526 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19527 create_instruction_sub
9239bbd3 19528 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 19529 }
19530
19531 /* B initial_insn_addr+4. */
19532 current_stub_contents =
19533 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19534 create_instruction_branch_absolute
82188b29 19535 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19536 }
19537
19538 /* Fill the remaining of the stub with deterministic contents. */
19539 current_stub_contents =
19540 stm32l4xx_fill_stub_udf (htab, output_bfd,
19541 base_stub_contents, current_stub_contents,
19542 base_stub_contents +
19543 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19544}
19545
19546static void
19547stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
19548 bfd * output_bfd,
19549 const insn32 wrong_insn,
19550 const bfd_byte *const wrong_insn_addr,
19551 bfd_byte *const stub_contents)
19552{
19553 if (is_thumb2_ldmia (wrong_insn))
19554 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
19555 wrong_insn, wrong_insn_addr,
19556 stub_contents);
19557 else if (is_thumb2_ldmdb (wrong_insn))
19558 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
19559 wrong_insn, wrong_insn_addr,
19560 stub_contents);
19561 else if (is_thumb2_vldm (wrong_insn))
19562 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
19563 wrong_insn, wrong_insn_addr,
19564 stub_contents);
19565}
19566
19567/* End of stm32l4xx work-around. */
19568
19569
e489d0ae
PB		 19570/* Do code byteswapping. Return FALSE afterwards so that the section is
19571 written out as normal. */
19572
19573static bfd_boolean
c7b8f16e 19574elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 19575 struct bfd_link_info *link_info,
19576 asection *sec,
e489d0ae
PB		 19577 bfd_byte *contents)
19578{
48229727 19579 unsigned int mapcount, errcount;
8e3de13a 19580 _arm_elf_section_data *arm_data;
c7b8f16e 19581 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 19582 elf32_arm_section_map *map;
c7b8f16e 19583 elf32_vfp11_erratum_list *errnode;
a504d23a 19584 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 19585 bfd_vma ptr;
19586 bfd_vma end;
c7b8f16e 19587 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 19588 bfd_byte tmp;
48229727 19589 unsigned int i;
57e8b36a 19590
4dfe6ac6
NC		 19591 if (globals == NULL)
19592 return FALSE;
19593
8e3de13a
NC		 19594 /* If this section has not been allocated an _arm_elf_section_data
19595 structure then we cannot record anything. */
19596 arm_data = get_arm_elf_section_data (sec);
19597 if (arm_data == NULL)
19598 return FALSE;
19599
19600 mapcount = arm_data->mapcount;
19601 map = arm_data->map;
c7b8f16e
JB		 19602 errcount = arm_data->erratumcount;
19603
19604 if (errcount != 0)
19605 {
19606 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
19607
19608 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 19609 errnode = errnode->next)
19610 {
19611 bfd_vma target = errnode->vma - offset;
19612
19613 switch (errnode->type)
19614 {
19615 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
19616 {
19617 bfd_vma branch_to_veneer;
19618 /* Original condition code of instruction, plus bit mask for
19619 ARM B instruction. */
19620 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
19621 | 0x0a000000;
c7b8f16e
JB		 19622
19623 /* The instruction is before the label. */
91d6fa6a 19624 target -= 4;
c7b8f16e
JB		 19625
19626 /* Above offset included in -4 below. */
19627 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 19628 - errnode->vma - 4;
c7b8f16e
JB		 19629
19630 if ((signed) branch_to_veneer < -(1 << 25)
19631 || (signed) branch_to_veneer >= (1 << 25))
871b3ab2 19632 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19633 "range"), output_bfd);
c7b8f16e 19634
99059e56
RM		 19635 insn |= (branch_to_veneer >> 2) & 0xffffff;
19636 contents[endianflip ^ target] = insn & 0xff;
19637 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19638 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19639 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19640 }
19641 break;
c7b8f16e
JB		 19642
19643 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 19644 {
19645 bfd_vma branch_from_veneer;
19646 unsigned int insn;
c7b8f16e 19647
99059e56
RM		 19648 /* Take size of veneer into account. */
19649 branch_from_veneer = errnode->u.v.branch->vma
19650 - errnode->vma - 12;
c7b8f16e
JB		 19651
19652 if ((signed) branch_from_veneer < -(1 << 25)
19653 || (signed) branch_from_veneer >= (1 << 25))
871b3ab2 19654 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19655 "range"), output_bfd);
c7b8f16e 19656
99059e56
RM		 19657 /* Original instruction. */
19658 insn = errnode->u.v.branch->u.b.vfp_insn;
19659 contents[endianflip ^ target] = insn & 0xff;
19660 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19661 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19662 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19663
19664 /* Branch back to insn after original insn. */
19665 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
19666 contents[endianflip ^ (target + 4)] = insn & 0xff;
19667 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
19668 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
19669 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
19670 }
19671 break;
c7b8f16e 19672
99059e56
RM		 19673 default:
19674 abort ();
19675 }
19676 }
c7b8f16e 19677 }
e489d0ae 19678
a504d23a
LA		 19679 if (arm_data->stm32l4xx_erratumcount != 0)
19680 {
19681 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
19682 stm32l4xx_errnode != 0;
19683 stm32l4xx_errnode = stm32l4xx_errnode->next)
19684 {
19685 bfd_vma target = stm32l4xx_errnode->vma - offset;
19686
19687 switch (stm32l4xx_errnode->type)
19688 {
19689 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
19690 {
19691 unsigned int insn;
19692 bfd_vma branch_to_veneer =
19693 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
19694
19695 if ((signed) branch_to_veneer < -(1 << 24)
19696 || (signed) branch_to_veneer >= (1 << 24))
19697 {
19698 bfd_vma out_of_range =
19699 ((signed) branch_to_veneer < -(1 << 24)) ?
19700 - branch_to_veneer - (1 << 24) :
19701 ((signed) branch_to_veneer >= (1 << 24)) ?
19702 branch_to_veneer - (1 << 24) : 0;
19703
4eca0228 19704 _bfd_error_handler
2dcf00ce 19705 (_("%pB(%#" PRIx64 "): error: "
90b6238f
AM		 19706 "cannot create STM32L4XX veneer; "
19707 "jump out of range by %" PRId64 " bytes; "
19708 "cannot encode branch instruction"),
a504d23a 19709 output_bfd,
2dcf00ce
AM		 19710 (uint64_t) (stm32l4xx_errnode->vma - 4),
19711 (int64_t) out_of_range);
a504d23a
LA		 19712 continue;
19713 }
19714
19715 insn = create_instruction_branch_absolute
82188b29 19716 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a 19717
a2699ef2
AM		 19718 /* The instruction is before the label. */
19719 target -= 4;
19720
a504d23a
LA		 19721 put_thumb2_insn (globals, output_bfd,
19722 (bfd_vma) insn, contents + target);
19723 }
19724 break;
19725
19726 case STM32L4XX_ERRATUM_VENEER:
19727 {
82188b29
NC		 19728 bfd_byte * veneer;
19729 bfd_byte * veneer_r;
a504d23a
LA		 19730 unsigned int insn;
19731
82188b29
NC		 19732 veneer = contents + target;
19733 veneer_r = veneer
19734 + stm32l4xx_errnode->u.b.veneer->vma
19735 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 19736
19737 if ((signed) (veneer_r - veneer -
19738 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19739 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19740 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19741 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
19742 || (signed) (veneer_r - veneer) >= (1 << 24))
19743 {
90b6238f
AM		 19744 _bfd_error_handler (_("%pB: error: cannot create STM32L4XX "
19745 "veneer"), output_bfd);
a504d23a
LA		 19746 continue;
19747 }
19748
19749 /* Original instruction. */
19750 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
19751
19752 stm32l4xx_create_replacing_stub
19753 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
19754 }
19755 break;
19756
19757 default:
19758 abort ();
19759 }
19760 }
19761 }
19762
2468f9c9
PB		 19763 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
19764 {
19765 arm_unwind_table_edit *edit_node
99059e56 19766 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 19767 /* Now, sec->size is the size of the section we will write. The original
99059e56 19768 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 19769 markers) was sec->rawsize. (This isn't the case if we perform no
19770 edits, then rawsize will be zero and we should use size). */
21d799b5 19771 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 19772 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
19773 unsigned int in_index, out_index;
19774 bfd_vma add_to_offsets = 0;
19775
19776 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 19777 {
2468f9c9
PB		 19778 if (edit_node)
19779 {
19780 unsigned int edit_index = edit_node->index;
b38cadfb 19781
2468f9c9 19782 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 19783 {
2468f9c9
PB		 19784 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19785 contents + in_index * 8, add_to_offsets);
19786 out_index++;
19787 in_index++;
19788 }
19789 else if (in_index == edit_index
19790 || (in_index * 8 >= input_size
19791 && edit_index == UINT_MAX))
99059e56 19792 {
2468f9c9
PB		 19793 switch (edit_node->type)
19794 {
19795 case DELETE_EXIDX_ENTRY:
19796 in_index++;
19797 add_to_offsets += 8;
19798 break;
b38cadfb 19799
2468f9c9
PB		 19800 case INSERT_EXIDX_CANTUNWIND_AT_END:
19801 {
99059e56 19802 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 19803 bfd_vma text_offset = text_sec->output_section->vma
19804 + text_sec->output_offset
19805 + text_sec->size;
19806 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 19807 unsigned long prel31_offset;
2468f9c9
PB		 19808
19809 /* Note: this is meant to be equivalent to an
19810 R_ARM_PREL31 relocation. These synthetic
19811 EXIDX_CANTUNWIND markers are not relocated by the
19812 usual BFD method. */
19813 prel31_offset = (text_offset - exidx_offset)
19814 & 0x7ffffffful;
491d01d3
YU		 19815 if (bfd_link_relocatable (link_info))
19816 {
19817 /* Here relocation for new EXIDX_CANTUNWIND is
19818 created, so there is no need to
19819 adjust offset by hand. */
19820 prel31_offset = text_sec->output_offset
19821 + text_sec->size;
491d01d3 19822 }
2468f9c9
PB		 19823
19824 /* First address we can't unwind. */
19825 bfd_put_32 (output_bfd, prel31_offset,
19826 &edited_contents[out_index * 8]);
19827
19828 /* Code for EXIDX_CANTUNWIND. */
19829 bfd_put_32 (output_bfd, 0x1,
19830 &edited_contents[out_index * 8 + 4]);
19831
19832 out_index++;
19833 add_to_offsets -= 8;
19834 }
19835 break;
19836 }
b38cadfb 19837
2468f9c9
PB		 19838 edit_node = edit_node->next;
19839 }
19840 }
19841 else
19842 {
19843 /* No more edits, copy remaining entries verbatim. */
19844 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19845 contents + in_index * 8, add_to_offsets);
19846 out_index++;
19847 in_index++;
19848 }
19849 }
19850
19851 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
19852 bfd_set_section_contents (output_bfd, sec->output_section,
19853 edited_contents,
19854 (file_ptr) sec->output_offset, sec->size);
19855
19856 return TRUE;
19857 }
19858
48229727
JB		 19859 /* Fix code to point to Cortex-A8 erratum stubs. */
19860 if (globals->fix_cortex_a8)
19861 {
19862 struct a8_branch_to_stub_data data;
19863
19864 data.writing_section = sec;
19865 data.contents = contents;
19866
a504d23a
LA		 19867 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
19868 & data);
48229727
JB		 19869 }
19870
e489d0ae
PB		 19871 if (mapcount == 0)
19872 return FALSE;
19873
c7b8f16e 19874 if (globals->byteswap_code)
e489d0ae 19875 {
c7b8f16e 19876 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 19877
c7b8f16e
JB		 19878 ptr = map[0].vma;
19879 for (i = 0; i < mapcount; i++)
99059e56
RM		 19880 {
19881 if (i == mapcount - 1)
c7b8f16e 19882 end = sec->size;
99059e56
RM		 19883 else
19884 end = map[i + 1].vma;
e489d0ae 19885
99059e56 19886 switch (map[i].type)
e489d0ae 19887 {
c7b8f16e
JB		 19888 case 'a':
19889 /* Byte swap code words. */
19890 while (ptr + 3 < end)
99059e56
RM		 19891 {
19892 tmp = contents[ptr];
19893 contents[ptr] = contents[ptr + 3];
19894 contents[ptr + 3] = tmp;
19895 tmp = contents[ptr + 1];
19896 contents[ptr + 1] = contents[ptr + 2];
19897 contents[ptr + 2] = tmp;
19898 ptr += 4;
19899 }
c7b8f16e 19900 break;
e489d0ae 19901
c7b8f16e
JB		 19902 case 't':
19903 /* Byte swap code halfwords. */
19904 while (ptr + 1 < end)
99059e56
RM		 19905 {
19906 tmp = contents[ptr];
19907 contents[ptr] = contents[ptr + 1];
19908 contents[ptr + 1] = tmp;
19909 ptr += 2;
19910 }
c7b8f16e
JB		 19911 break;
19912
19913 case 'd':
19914 /* Leave data alone. */
19915 break;
19916 }
99059e56
RM		 19917 ptr = end;
19918 }
e489d0ae 19919 }
8e3de13a 19920
93204d3a 19921 free (map);
47b2e99c 19922 arm_data->mapcount = -1;
c7b8f16e 19923 arm_data->mapsize = 0;
8e3de13a 19924 arm_data->map = NULL;
8e3de13a 19925
e489d0ae
PB		 19926 return FALSE;
19927}
19928
0beaef2b
PB		 19929/* Mangle thumb function symbols as we read them in. */
19930
8384fb8f 19931static bfd_boolean
0beaef2b
PB		 19932elf32_arm_swap_symbol_in (bfd * abfd,
19933 const void *psrc,
19934 const void *pshn,
19935 Elf_Internal_Sym *dst)
19936{
8384fb8f
AM		 19937 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
19938 return FALSE;
39d911fc 19939 dst->st_target_internal = 0;
0beaef2b
PB		 19940
19941 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 19942 the address. */
63e1a0fc
PB		 19943 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
19944 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 19945 {
63e1a0fc
PB		 19946 if (dst->st_value & 1)
19947 {
19948 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 19949 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
19950 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 19951 }
19952 else
39d911fc 19953 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 19954 }
19955 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
19956 {
19957 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 19958 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 19959 }
35fc36a8 19960 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 19961 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 19962 else
39d911fc 19963 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 19964
8384fb8f 19965 return TRUE;
0beaef2b
PB		 19966}
19967
19968
19969/* Mangle thumb function symbols as we write them out. */
19970
19971static void
19972elf32_arm_swap_symbol_out (bfd *abfd,
19973 const Elf_Internal_Sym *src,
19974 void *cdst,
19975 void *shndx)
19976{
19977 Elf_Internal_Sym newsym;
19978
19979 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19980 of the address set, as per the new EABI. We do this unconditionally
19981 because objcopy does not set the elf header flags until after
19982 it writes out the symbol table. */
39d911fc 19983 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 19984 {
19985 newsym = *src;
34e77a92
RS		 19986 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
19987 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 19988 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 19989 {
19990 /* Do this only for defined symbols. At link type, the static
19991 linker will simulate the work of dynamic linker of resolving
19992 symbols and will carry over the thumbness of found symbols to
19993 the output symbol table. It's not clear how it happens, but
19994 the thumbness of undefined symbols can well be different at
19995 runtime, and writing '1' for them will be confusing for users
19996 and possibly for dynamic linker itself.
19997 */
19998 newsym.st_value |= 1;
19999 }
906e58ca 20000
0beaef2b
PB		 20001 src = &newsym;
20002 }
20003 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
20004}
20005
b294bdf8
MM		 20006/* Add the PT_ARM_EXIDX program header. */
20007
20008static bfd_boolean
906e58ca 20009elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 20010 struct bfd_link_info *info ATTRIBUTE_UNUSED)
20011{
20012 struct elf_segment_map *m;
20013 asection *sec;
20014
20015 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
20016 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
20017 {
20018 /* If there is already a PT_ARM_EXIDX header, then we do not
20019 want to add another one. This situation arises when running
20020 "strip"; the input binary already has the header. */
12bd6957 20021 m = elf_seg_map (abfd);
b294bdf8
MM		 20022 while (m && m->p_type != PT_ARM_EXIDX)
20023 m = m->next;
20024 if (!m)
20025 {
21d799b5 20026 m = (struct elf_segment_map *)
99059e56 20027 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 20028 if (m == NULL)
20029 return FALSE;
20030 m->p_type = PT_ARM_EXIDX;
20031 m->count = 1;
20032 m->sections[0] = sec;
20033
12bd6957
AM		 20034 m->next = elf_seg_map (abfd);
20035 elf_seg_map (abfd) = m;
b294bdf8
MM		 20036 }
20037 }
20038
20039 return TRUE;
20040}
20041
20042/* We may add a PT_ARM_EXIDX program header. */
20043
20044static int
a6b96beb
AM		 20045elf32_arm_additional_program_headers (bfd *abfd,
20046 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 20047{
20048 asection *sec;
20049
20050 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
20051 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
20052 return 1;
20053 else
20054 return 0;
20055}
20056
34e77a92
RS		 20057/* Hook called by the linker routine which adds symbols from an object
20058 file. */
20059
20060static bfd_boolean
20061elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
20062 Elf_Internal_Sym *sym, const char **namep,
20063 flagword *flagsp, asection **secp, bfd_vma *valp)
20064{
c792917c
NC		 20065 if (elf32_arm_hash_table (info) == NULL)
20066 return FALSE;
20067
34e77a92
RS		 20068 if (elf32_arm_hash_table (info)->vxworks_p
20069 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
20070 flagsp, secp, valp))
20071 return FALSE;
20072
20073 return TRUE;
20074}
20075
0beaef2b 20076/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 20077const struct elf_size_info elf32_arm_size_info =
20078{
0beaef2b
PB		 20079 sizeof (Elf32_External_Ehdr),
20080 sizeof (Elf32_External_Phdr),
20081 sizeof (Elf32_External_Shdr),
20082 sizeof (Elf32_External_Rel),
20083 sizeof (Elf32_External_Rela),
20084 sizeof (Elf32_External_Sym),
20085 sizeof (Elf32_External_Dyn),
20086 sizeof (Elf_External_Note),
20087 4,
20088 1,
20089 32, 2,
20090 ELFCLASS32, EV_CURRENT,
20091 bfd_elf32_write_out_phdrs,
20092 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 20093 bfd_elf32_checksum_contents,
0beaef2b
PB		 20094 bfd_elf32_write_relocs,
20095 elf32_arm_swap_symbol_in,
20096 elf32_arm_swap_symbol_out,
20097 bfd_elf32_slurp_reloc_table,
20098 bfd_elf32_slurp_symbol_table,
20099 bfd_elf32_swap_dyn_in,
20100 bfd_elf32_swap_dyn_out,
20101 bfd_elf32_swap_reloc_in,
20102 bfd_elf32_swap_reloc_out,
20103 bfd_elf32_swap_reloca_in,
20104 bfd_elf32_swap_reloca_out
20105};
20106
685e70ae
VK		 20107static bfd_vma
20108read_code32 (const bfd *abfd, const bfd_byte *addr)
20109{
20110 /* V7 BE8 code is always little endian. */
20111 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
20112 return bfd_getl32 (addr);
20113
20114 return bfd_get_32 (abfd, addr);
20115}
20116
20117static bfd_vma
20118read_code16 (const bfd *abfd, const bfd_byte *addr)
20119{
20120 /* V7 BE8 code is always little endian. */
20121 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
20122 return bfd_getl16 (addr);
20123
20124 return bfd_get_16 (abfd, addr);
20125}
20126
6a631e86
YG		 20127/* Return size of plt0 entry starting at ADDR
20128 or (bfd_vma) -1 if size can not be determined. */
20129
20130static bfd_vma
20131elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
20132{
20133 bfd_vma first_word;
20134 bfd_vma plt0_size;
20135
685e70ae 20136 first_word = read_code32 (abfd, addr);
6a631e86
YG		 20137
20138 if (first_word == elf32_arm_plt0_entry[0])
20139 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
20140 else if (first_word == elf32_thumb2_plt0_entry[0])
20141 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
20142 else
20143 /* We don't yet handle this PLT format. */
20144 return (bfd_vma) -1;
20145
20146 return plt0_size;
20147}
20148
20149/* Return size of plt entry starting at offset OFFSET
20150 of plt section located at address START
20151 or (bfd_vma) -1 if size can not be determined. */
20152
20153static bfd_vma
20154elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
20155{
20156 bfd_vma first_insn;
20157 bfd_vma plt_size = 0;
20158 const bfd_byte *addr = start + offset;
20159
20160 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 20161 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 20162 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
20163
20164 /* Respect Thumb stub if necessary. */
685e70ae 20165 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 20166 {
20167 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
20168 }
20169
20170 /* Strip immediate from first add. */
685e70ae 20171 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 20172
20173#ifdef FOUR_WORD_PLT
20174 if (first_insn == elf32_arm_plt_entry[0])
20175 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
20176#else
20177 if (first_insn == elf32_arm_plt_entry_long[0])
20178 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
20179 else if (first_insn == elf32_arm_plt_entry_short[0])
20180 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
20181#endif
20182 else
20183 /* We don't yet handle this PLT format. */
20184 return (bfd_vma) -1;
20185
20186 return plt_size;
20187}
20188
20189/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
20190
20191static long
20192elf32_arm_get_synthetic_symtab (bfd *abfd,
20193 long symcount ATTRIBUTE_UNUSED,
20194 asymbol **syms ATTRIBUTE_UNUSED,
20195 long dynsymcount,
20196 asymbol **dynsyms,
20197 asymbol **ret)
20198{
20199 asection *relplt;
20200 asymbol *s;
20201 arelent *p;
20202 long count, i, n;
20203 size_t size;
20204 Elf_Internal_Shdr *hdr;
20205 char *names;
20206 asection *plt;
20207 bfd_vma offset;
20208 bfd_byte *data;
20209
20210 *ret = NULL;
20211
20212 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
20213 return 0;
20214
20215 if (dynsymcount <= 0)
20216 return 0;
20217
20218 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
20219 if (relplt == NULL)
20220 return 0;
20221
20222 hdr = &elf_section_data (relplt)->this_hdr;
20223 if (hdr->sh_link != elf_dynsymtab (abfd)
20224 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
20225 return 0;
20226
20227 plt = bfd_get_section_by_name (abfd, ".plt");
20228 if (plt == NULL)
20229 return 0;
20230
20231 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
20232 return -1;
20233
20234 data = plt->contents;
20235 if (data == NULL)
20236 {
20237 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
20238 return -1;
20239 bfd_cache_section_contents((asection *) plt, data);
20240 }
20241
20242 count = relplt->size / hdr->sh_entsize;
20243 size = count * sizeof (asymbol);
20244 p = relplt->relocation;
20245 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20246 {
20247 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
20248 if (p->addend != 0)
20249 size += sizeof ("+0x") - 1 + 8;
20250 }
20251
20252 s = *ret = (asymbol *) bfd_malloc (size);
20253 if (s == NULL)
20254 return -1;
20255
20256 offset = elf32_arm_plt0_size (abfd, data);
20257 if (offset == (bfd_vma) -1)
20258 return -1;
20259
20260 names = (char *) (s + count);
20261 p = relplt->relocation;
20262 n = 0;
20263 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20264 {
20265 size_t len;
20266
20267 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
20268 if (plt_size == (bfd_vma) -1)
20269 break;
20270
20271 *s = **p->sym_ptr_ptr;
20272 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20273 we are defining a symbol, ensure one of them is set. */
20274 if ((s->flags & BSF_LOCAL) == 0)
20275 s->flags |= BSF_GLOBAL;
20276 s->flags |= BSF_SYNTHETIC;
20277 s->section = plt;
20278 s->value = offset;
20279 s->name = names;
20280 s->udata.p = NULL;
20281 len = strlen ((*p->sym_ptr_ptr)->name);
20282 memcpy (names, (*p->sym_ptr_ptr)->name, len);
20283 names += len;
20284 if (p->addend != 0)
20285 {
20286 char buf[30], *a;
20287
20288 memcpy (names, "+0x", sizeof ("+0x") - 1);
20289 names += sizeof ("+0x") - 1;
20290 bfd_sprintf_vma (abfd, buf, p->addend);
20291 for (a = buf; *a == '0'; ++a)
20292 ;
20293 len = strlen (a);
20294 memcpy (names, a, len);
20295 names += len;
20296 }
20297 memcpy (names, "@plt", sizeof ("@plt"));
20298 names += sizeof ("@plt");
20299 ++s, ++n;
20300 offset += plt_size;
20301 }
20302
20303 return n;
20304}
20305
ac4c9b04
MG		 20306static bfd_boolean
20307elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
20308{
f0728ee3
AV		 20309 if (hdr->sh_flags & SHF_ARM_PURECODE)
20310 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 20311 return TRUE;
20312}
20313
20314static flagword
20315elf32_arm_lookup_section_flags (char *flag_name)
20316{
f0728ee3
AV		 20317 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
20318 return SHF_ARM_PURECODE;
ac4c9b04
MG		 20319
20320 return SEC_NO_FLAGS;
20321}
20322
491d01d3
YU		 20323static unsigned int
20324elf32_arm_count_additional_relocs (asection *sec)
20325{
20326 struct _arm_elf_section_data *arm_data;
20327 arm_data = get_arm_elf_section_data (sec);
5025eb7c 20328
6342be70 20329 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 20330}
20331
5522f910 20332/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 20333 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 20334 FALSE otherwise. ISECTION is the best guess matching section from the
20335 input bfd IBFD, but it might be NULL. */
20336
20337static bfd_boolean
20338elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
20339 bfd *obfd ATTRIBUTE_UNUSED,
20340 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
20341 Elf_Internal_Shdr *osection)
20342{
20343 switch (osection->sh_type)
20344 {
20345 case SHT_ARM_EXIDX:
20346 {
20347 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
20348 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
20349 unsigned i = 0;
20350
20351 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
20352 osection->sh_info = 0;
20353
20354 /* The sh_link field must be set to the text section associated with
20355 this index section. Unfortunately the ARM EHABI does not specify
20356 exactly how to determine this association. Our caller does try
20357 to match up OSECTION with its corresponding input section however
20358 so that is a good first guess. */
20359 if (isection != NULL
20360 && osection->bfd_section != NULL
20361 && isection->bfd_section != NULL
20362 && isection->bfd_section->output_section != NULL
20363 && isection->bfd_section->output_section == osection->bfd_section
20364 && iheaders != NULL
20365 && isection->sh_link > 0
20366 && isection->sh_link < elf_numsections (ibfd)
20367 && iheaders[isection->sh_link]->bfd_section != NULL
20368 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
20369 )
20370 {
20371 for (i = elf_numsections (obfd); i-- > 0;)
20372 if (oheaders[i]->bfd_section
20373 == iheaders[isection->sh_link]->bfd_section->output_section)
20374 break;
20375 }
9eaff861 20376
5522f910
NC		 20377 if (i == 0)
20378 {
20379 /* Failing that we have to find a matching section ourselves. If
20380 we had the output section name available we could compare that
20381 with input section names. Unfortunately we don't. So instead
20382 we use a simple heuristic and look for the nearest executable
20383 section before this one. */
20384 for (i = elf_numsections (obfd); i-- > 0;)
20385 if (oheaders[i] == osection)
20386 break;
20387 if (i == 0)
20388 break;
20389
20390 while (i-- > 0)
20391 if (oheaders[i]->sh_type == SHT_PROGBITS
20392 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
20393 == (SHF_ALLOC | SHF_EXECINSTR))
20394 break;
20395 }
20396
20397 if (i)
20398 {
20399 osection->sh_link = i;
20400 /* If the text section was part of a group
20401 then the index section should be too. */
20402 if (oheaders[i]->sh_flags & SHF_GROUP)
20403 osection->sh_flags |= SHF_GROUP;
20404 return TRUE;
20405 }
20406 }
20407 break;
20408
20409 case SHT_ARM_PREEMPTMAP:
20410 osection->sh_flags = SHF_ALLOC;
20411 break;
20412
20413 case SHT_ARM_ATTRIBUTES:
20414 case SHT_ARM_DEBUGOVERLAY:
20415 case SHT_ARM_OVERLAYSECTION:
20416 default:
20417 break;
20418 }
20419
20420 return FALSE;
20421}
20422
d691934d
NC		 20423/* Returns TRUE if NAME is an ARM mapping symbol.
20424 Traditionally the symbols $a, $d and $t have been used.
20425 The ARM ELF standard also defines $x (for A64 code). It also allows a
20426 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20427 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20428 not support them here. $t.x indicates the start of ThumbEE instructions. */
20429
20430static bfd_boolean
20431is_arm_mapping_symbol (const char * name)
20432{
20433 return name != NULL /* Paranoia. */
20434 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
20435 the mapping symbols could have acquired a prefix.
20436 We do not support this here, since such symbols no
20437 longer conform to the ARM ELF ABI. */
20438 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
20439 && (name[2] == 0 || name[2] == '.');
20440 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20441 any characters that follow the period are legal characters for the body
20442 of a symbol's name. For now we just assume that this is the case. */
20443}
20444
fca2a38f
NC		 20445/* Make sure that mapping symbols in object files are not removed via the
20446 "strip --strip-unneeded" tool. These symbols are needed in order to
20447 correctly generate interworking veneers, and for byte swapping code
20448 regions. Once an object file has been linked, it is safe to remove the
20449 symbols as they will no longer be needed. */
20450
20451static void
20452elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
20453{
20454 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 20455 && sym->section != bfd_abs_section_ptr
d691934d 20456 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 20457 sym->flags |= BSF_KEEP;
20458}
20459
5522f910
NC		 20460#undef elf_backend_copy_special_section_fields
20461#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20462
252b5132 20463#define ELF_ARCH bfd_arch_arm
ae95ffa6 20464#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 20465#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 20466#ifdef __QNXTARGET__
20467#define ELF_MAXPAGESIZE 0x1000
20468#else
7572ca89 20469#define ELF_MAXPAGESIZE 0x10000
d0facd1b 20470#endif
b1342370 20471#define ELF_MINPAGESIZE 0x1000
24718e3b 20472#define ELF_COMMONPAGESIZE 0x1000
252b5132 20473
07d6d2b8 20474#define bfd_elf32_mkobject elf32_arm_mkobject
ba93b8ac 20475
99e4ae17
AJ		 20476#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20477#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 20478#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20479#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
07d6d2b8 20480#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 20481#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 20482#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
07d6d2b8
AM		 20483#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
20484#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 20485#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 20486#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 20487#define bfd_elf32_bfd_final_link elf32_arm_final_link
07d6d2b8 20488#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132 20489
07d6d2b8
AM		 20490#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
20491#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 20492#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
07d6d2b8 20493#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 20494#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 20495#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 20496#define elf_backend_write_section elf32_arm_write_section
252b5132 20497#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
07d6d2b8 20498#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 20499#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20500#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20501#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 20502#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 20503#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 20504#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 20505#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 20506#define elf_backend_object_p elf32_arm_object_p
07d6d2b8
AM		 20507#define elf_backend_fake_sections elf32_arm_fake_sections
20508#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20509#define elf_backend_final_write_processing elf32_arm_final_write_processing
20510#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 20511#define elf_backend_size_info elf32_arm_size_info
b294bdf8 20512#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
07d6d2b8
AM		 20513#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20514#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 20515#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
07d6d2b8 20516#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 20517#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 20518#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 20519#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 20520
20521#define elf_backend_can_refcount 1
20522#define elf_backend_can_gc_sections 1
20523#define elf_backend_plt_readonly 1
20524#define elf_backend_want_got_plt 1
20525#define elf_backend_want_plt_sym 0
5474d94f 20526#define elf_backend_want_dynrelro 1
906e58ca
NC		 20527#define elf_backend_may_use_rel_p 1
20528#define elf_backend_may_use_rela_p 0
4e7fd91e 20529#define elf_backend_default_use_rela_p 0
64f52338 20530#define elf_backend_dtrel_excludes_plt 1
252b5132 20531
04f7c78d 20532#define elf_backend_got_header_size 12
b68a20d6 20533#define elf_backend_extern_protected_data 1
04f7c78d 20534
07d6d2b8 20535#undef elf_backend_obj_attrs_vendor
906e58ca 20536#define elf_backend_obj_attrs_vendor "aeabi"
07d6d2b8 20537#undef elf_backend_obj_attrs_section
906e58ca 20538#define elf_backend_obj_attrs_section ".ARM.attributes"
07d6d2b8 20539#undef elf_backend_obj_attrs_arg_type
906e58ca 20540#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
07d6d2b8 20541#undef elf_backend_obj_attrs_section_type
104d59d1 20542#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb 20543#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
07d6d2b8 20544#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 20545
07d6d2b8 20546#undef elf_backend_section_flags
ac4c9b04 20547#define elf_backend_section_flags elf32_arm_section_flags
07d6d2b8
AM		 20548#undef elf_backend_lookup_section_flags_hook
20549#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
ac4c9b04 20550
a2f63b2e
MR		 20551#define elf_backend_linux_prpsinfo32_ugid16 TRUE
20552
252b5132 20553#include "elf32-target.h"
7f266840 20554
b38cadfb
NC		 20555/* Native Client targets. */
20556
20557#undef TARGET_LITTLE_SYM
6d00b590 20558#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 20559#undef TARGET_LITTLE_NAME
20560#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
20561#undef TARGET_BIG_SYM
6d00b590 20562#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 20563#undef TARGET_BIG_NAME
20564#define TARGET_BIG_NAME "elf32-bigarm-nacl"
20565
20566/* Like elf32_arm_link_hash_table_create -- but overrides
20567 appropriately for NaCl. */
20568
20569static struct bfd_link_hash_table *
20570elf32_arm_nacl_link_hash_table_create (bfd *abfd)
20571{
20572 struct bfd_link_hash_table *ret;
20573
20574 ret = elf32_arm_link_hash_table_create (abfd);
20575 if (ret)
20576 {
20577 struct elf32_arm_link_hash_table *htab
20578 = (struct elf32_arm_link_hash_table *) ret;
20579
20580 htab->nacl_p = 1;
20581
20582 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
20583 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
20584 }
20585 return ret;
20586}
20587
20588/* Since NaCl doesn't use the ARM-specific unwind format, we don't
20589 really need to use elf32_arm_modify_segment_map. But we do it
20590 anyway just to reduce gratuitous differences with the stock ARM backend. */
20591
20592static bfd_boolean
20593elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
20594{
20595 return (elf32_arm_modify_segment_map (abfd, info)
20596 && nacl_modify_segment_map (abfd, info));
20597}
20598
cc364be6
AM		 20599static bfd_boolean
20600elf32_arm_nacl_final_write_processing (bfd *abfd)
887badb3 20601{
cc364be6
AM		 20602 arm_final_write_processing (abfd);
20603 return nacl_final_write_processing (abfd);
887badb3
RM		 20604}
20605
6a631e86
YG		 20606static bfd_vma
20607elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
20608 const arelent *rel ATTRIBUTE_UNUSED)
20609{
20610 return plt->vma
20611 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
20612 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
20613}
887badb3 20614
b38cadfb 20615#undef elf32_bed
6a631e86 20616#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 20617#undef bfd_elf32_bfd_link_hash_table_create
20618#define bfd_elf32_bfd_link_hash_table_create \
20619 elf32_arm_nacl_link_hash_table_create
20620#undef elf_backend_plt_alignment
6a631e86 20621#define elf_backend_plt_alignment 4
b38cadfb
NC		 20622#undef elf_backend_modify_segment_map
20623#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
20624#undef elf_backend_modify_program_headers
20625#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 20626#undef elf_backend_final_write_processing
20627#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 20628#undef bfd_elf32_get_synthetic_symtab
20629#undef elf_backend_plt_sym_val
20630#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 20631#undef elf_backend_copy_special_section_fields
b38cadfb 20632
887badb3
RM		 20633#undef ELF_MINPAGESIZE
20634#undef ELF_COMMONPAGESIZE
20635
b38cadfb
NC		 20636
20637#include "elf32-target.h"
20638
20639/* Reset to defaults. */
20640#undef elf_backend_plt_alignment
20641#undef elf_backend_modify_segment_map
20642#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20643#undef elf_backend_modify_program_headers
887badb3
RM		 20644#undef elf_backend_final_write_processing
20645#define elf_backend_final_write_processing elf32_arm_final_write_processing
20646#undef ELF_MINPAGESIZE
20647#define ELF_MINPAGESIZE 0x1000
20648#undef ELF_COMMONPAGESIZE
20649#define ELF_COMMONPAGESIZE 0x1000
20650
b38cadfb 20651
617a5ada
CL		 20652/* FDPIC Targets. */
20653
20654#undef TARGET_LITTLE_SYM
20655#define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20656#undef TARGET_LITTLE_NAME
20657#define TARGET_LITTLE_NAME "elf32-littlearm-fdpic"
20658#undef TARGET_BIG_SYM
20659#define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20660#undef TARGET_BIG_NAME
20661#define TARGET_BIG_NAME "elf32-bigarm-fdpic"
20662#undef elf_match_priority
20663#define elf_match_priority 128
18a20338
CL		 20664#undef ELF_OSABI
20665#define ELF_OSABI ELFOSABI_ARM_FDPIC
617a5ada
CL		 20666
20667/* Like elf32_arm_link_hash_table_create -- but overrides
20668 appropriately for FDPIC. */
20669
20670static struct bfd_link_hash_table *
20671elf32_arm_fdpic_link_hash_table_create (bfd *abfd)
20672{
20673 struct bfd_link_hash_table *ret;
20674
20675 ret = elf32_arm_link_hash_table_create (abfd);
20676 if (ret)
20677 {
20678 struct elf32_arm_link_hash_table *htab = (struct elf32_arm_link_hash_table *) ret;
20679
20680 htab->fdpic_p = 1;
20681 }
20682 return ret;
20683}
20684
e8b09b87
CL		 20685/* We need dynamic symbols for every section, since segments can
20686 relocate independently. */
20687static bfd_boolean
20688elf32_arm_fdpic_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
20689 struct bfd_link_info *info
20690 ATTRIBUTE_UNUSED,
20691 asection *p ATTRIBUTE_UNUSED)
20692{
20693 switch (elf_section_data (p)->this_hdr.sh_type)
20694 {
20695 case SHT_PROGBITS:
20696 case SHT_NOBITS:
20697 /* If sh_type is yet undecided, assume it could be
20698 SHT_PROGBITS/SHT_NOBITS. */
20699 case SHT_NULL:
20700 return FALSE;
20701
20702 /* There shouldn't be section relative relocations
20703 against any other section. */
20704 default:
20705 return TRUE;
20706 }
20707}
20708
617a5ada
CL		 20709#undef elf32_bed
20710#define elf32_bed elf32_arm_fdpic_bed
20711
20712#undef bfd_elf32_bfd_link_hash_table_create
4b24dd1a 20713#define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
617a5ada 20714
e8b09b87
CL		 20715#undef elf_backend_omit_section_dynsym
20716#define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20717
617a5ada 20718#include "elf32-target.h"
e8b09b87 20719
617a5ada 20720#undef elf_match_priority
18a20338 20721#undef ELF_OSABI
e8b09b87 20722#undef elf_backend_omit_section_dynsym
617a5ada 20723
906e58ca 20724/* VxWorks Targets. */
4e7fd91e 20725
07d6d2b8
AM		 20726#undef TARGET_LITTLE_SYM
20727#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20728#undef TARGET_LITTLE_NAME
20729#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
20730#undef TARGET_BIG_SYM
20731#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20732#undef TARGET_BIG_NAME
20733#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
4e7fd91e
PB		 20734
20735/* Like elf32_arm_link_hash_table_create -- but overrides
20736 appropriately for VxWorks. */
906e58ca 20737
4e7fd91e
PB		 20738static struct bfd_link_hash_table *
20739elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
20740{
20741 struct bfd_link_hash_table *ret;
20742
20743 ret = elf32_arm_link_hash_table_create (abfd);
20744 if (ret)
20745 {
20746 struct elf32_arm_link_hash_table *htab
00a97672 20747 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 20748 htab->use_rel = 0;
00a97672 20749 htab->vxworks_p = 1;
4e7fd91e
PB		 20750 }
20751 return ret;
906e58ca 20752}
4e7fd91e 20753
cc364be6
AM		 20754static bfd_boolean
20755elf32_arm_vxworks_final_write_processing (bfd *abfd)
00a97672 20756{
cc364be6
AM		 20757 arm_final_write_processing (abfd);
20758 return elf_vxworks_final_write_processing (abfd);
00a97672
RS		 20759}
20760
906e58ca 20761#undef elf32_bed
4e7fd91e
PB		 20762#define elf32_bed elf32_arm_vxworks_bed
20763
906e58ca
NC		 20764#undef bfd_elf32_bfd_link_hash_table_create
20765#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 20766#undef elf_backend_final_write_processing
20767#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20768#undef elf_backend_emit_relocs
9eaff861 20769#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 20770
906e58ca 20771#undef elf_backend_may_use_rel_p
00a97672 20772#define elf_backend_may_use_rel_p 0
906e58ca 20773#undef elf_backend_may_use_rela_p
00a97672 20774#define elf_backend_may_use_rela_p 1
906e58ca 20775#undef elf_backend_default_use_rela_p
00a97672 20776#define elf_backend_default_use_rela_p 1
906e58ca 20777#undef elf_backend_want_plt_sym
00a97672 20778#define elf_backend_want_plt_sym 1
906e58ca 20779#undef ELF_MAXPAGESIZE
00a97672 20780#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 20781
20782#include "elf32-target.h"
20783
20784
21d799b5
NC		 20785/* Merge backend specific data from an object file to the output
20786 object file when linking. */
20787
20788static bfd_boolean
50e03d47 20789elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 20790{
50e03d47 20791 bfd *obfd = info->output_bfd;
21d799b5
NC		 20792 flagword out_flags;
20793 flagword in_flags;
20794 bfd_boolean flags_compatible = TRUE;
20795 asection *sec;
20796
cc643b88 20797 /* Check if we have the same endianness. */
50e03d47 20798 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 20799 return FALSE;
20800
20801 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
20802 return TRUE;
20803
50e03d47 20804 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 20805 return FALSE;
20806
20807 /* The input BFD must have had its flags initialised. */
20808 /* The following seems bogus to me -- The flags are initialized in
20809 the assembler but I don't think an elf_flags_init field is
20810 written into the object. */
20811 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20812
20813 in_flags = elf_elfheader (ibfd)->e_flags;
20814 out_flags = elf_elfheader (obfd)->e_flags;
20815
20816 /* In theory there is no reason why we couldn't handle this. However
20817 in practice it isn't even close to working and there is no real
20818 reason to want it. */
20819 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
20820 && !(ibfd->flags & DYNAMIC)
20821 && (in_flags & EF_ARM_BE8))
20822 {
871b3ab2 20823 _bfd_error_handler (_("error: %pB is already in final BE8 format"),
21d799b5
NC		 20824 ibfd);
20825 return FALSE;
20826 }
20827
20828 if (!elf_flags_init (obfd))
20829 {
20830 /* If the input is the default architecture and had the default
20831 flags then do not bother setting the flags for the output
20832 architecture, instead allow future merges to do this. If no
20833 future merges ever set these flags then they will retain their
99059e56
RM		 20834 uninitialised values, which surprise surprise, correspond
20835 to the default values. */
21d799b5
NC		 20836 if (bfd_get_arch_info (ibfd)->the_default
20837 && elf_elfheader (ibfd)->e_flags == 0)
20838 return TRUE;
20839
20840 elf_flags_init (obfd) = TRUE;
20841 elf_elfheader (obfd)->e_flags = in_flags;
20842
20843 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
20844 && bfd_get_arch_info (obfd)->the_default)
20845 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
20846
20847 return TRUE;
20848 }
20849
20850 /* Determine what should happen if the input ARM architecture
20851 does not match the output ARM architecture. */
20852 if (! bfd_arm_merge_machines (ibfd, obfd))
20853 return FALSE;
20854
20855 /* Identical flags must be compatible. */
20856 if (in_flags == out_flags)
20857 return TRUE;
20858
20859 /* Check to see if the input BFD actually contains any sections. If
20860 not, its flags may not have been initialised either, but it
20861 cannot actually cause any incompatiblity. Do not short-circuit
20862 dynamic objects; their section list may be emptied by
20863 elf_link_add_object_symbols.
20864
20865 Also check to see if there are no code sections in the input.
20866 In this case there is no need to check for code specific flags.
20867 XXX - do we need to worry about floating-point format compatability
20868 in data sections ? */
20869 if (!(ibfd->flags & DYNAMIC))
20870 {
20871 bfd_boolean null_input_bfd = TRUE;
20872 bfd_boolean only_data_sections = TRUE;
20873
20874 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
20875 {
20876 /* Ignore synthetic glue sections. */
20877 if (strcmp (sec->name, ".glue_7")
20878 && strcmp (sec->name, ".glue_7t"))
20879 {
fd361982 20880 if ((bfd_section_flags (sec)
21d799b5
NC		 20881 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
20882 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 20883 only_data_sections = FALSE;
21d799b5
NC		 20884
20885 null_input_bfd = FALSE;
20886 break;
20887 }
20888 }
20889
20890 if (null_input_bfd || only_data_sections)
20891 return TRUE;
20892 }
20893
20894 /* Complain about various flag mismatches. */
20895 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
20896 EF_ARM_EABI_VERSION (out_flags)))
20897 {
20898 _bfd_error_handler
90b6238f 20899 (_("error: source object %pB has EABI version %d, but target %pB has EABI version %d"),
c08bb8dd
AM		 20900 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
20901 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 20902 return FALSE;
20903 }
20904
20905 /* Not sure what needs to be checked for EABI versions >= 1. */
20906 /* VxWorks libraries do not use these flags. */
20907 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
20908 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
20909 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
20910 {
20911 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
20912 {
20913 _bfd_error_handler
871b3ab2 20914 (_("error: %pB is compiled for APCS-%d, whereas target %pB uses APCS-%d"),
c08bb8dd
AM		 20915 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
20916 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 20917 flags_compatible = FALSE;
20918 }
20919
20920 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
20921 {
20922 if (in_flags & EF_ARM_APCS_FLOAT)
20923 _bfd_error_handler
871b3ab2 20924 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
21d799b5
NC		 20925 ibfd, obfd);
20926 else
20927 _bfd_error_handler
871b3ab2 20928 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
21d799b5
NC		 20929 ibfd, obfd);
20930
20931 flags_compatible = FALSE;
20932 }
20933
20934 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
20935 {
20936 if (in_flags & EF_ARM_VFP_FLOAT)
20937 _bfd_error_handler
90b6238f
AM		 20938 (_("error: %pB uses %s instructions, whereas %pB does not"),
20939 ibfd, "VFP", obfd);
21d799b5
NC		 20940 else
20941 _bfd_error_handler
90b6238f
AM		 20942 (_("error: %pB uses %s instructions, whereas %pB does not"),
20943 ibfd, "FPA", obfd);
21d799b5
NC		 20944
20945 flags_compatible = FALSE;
20946 }
20947
20948 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
20949 {
20950 if (in_flags & EF_ARM_MAVERICK_FLOAT)
20951 _bfd_error_handler
90b6238f
AM		 20952 (_("error: %pB uses %s instructions, whereas %pB does not"),
20953 ibfd, "Maverick", obfd);
21d799b5
NC		 20954 else
20955 _bfd_error_handler
90b6238f
AM		 20956 (_("error: %pB does not use %s instructions, whereas %pB does"),
20957 ibfd, "Maverick", obfd);
21d799b5
NC		 20958
20959 flags_compatible = FALSE;
20960 }
20961
20962#ifdef EF_ARM_SOFT_FLOAT
20963 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
20964 {
20965 /* We can allow interworking between code that is VFP format
20966 layout, and uses either soft float or integer regs for
20967 passing floating point arguments and results. We already
20968 know that the APCS_FLOAT flags match; similarly for VFP
20969 flags. */
20970 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
20971 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
20972 {
20973 if (in_flags & EF_ARM_SOFT_FLOAT)
20974 _bfd_error_handler
871b3ab2 20975 (_("error: %pB uses software FP, whereas %pB uses hardware FP"),
21d799b5
NC		 20976 ibfd, obfd);
20977 else
20978 _bfd_error_handler
871b3ab2 20979 (_("error: %pB uses hardware FP, whereas %pB uses software FP"),
21d799b5
NC		 20980 ibfd, obfd);
20981
20982 flags_compatible = FALSE;
20983 }
20984 }
20985#endif
20986
20987 /* Interworking mismatch is only a warning. */
20988 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
20989 {
20990 if (in_flags & EF_ARM_INTERWORK)
20991 {
20992 _bfd_error_handler
90b6238f 20993 (_("warning: %pB supports interworking, whereas %pB does not"),
21d799b5
NC		 20994 ibfd, obfd);
20995 }
20996 else
20997 {
20998 _bfd_error_handler
90b6238f 20999 (_("warning: %pB does not support interworking, whereas %pB does"),
21d799b5
NC		 21000 ibfd, obfd);
21001 }
21002 }
21003 }
21004
21005 return flags_compatible;
21006}
21007
21008
906e58ca 21009/* Symbian OS Targets. */
7f266840 21010
07d6d2b8
AM		 21011#undef TARGET_LITTLE_SYM
21012#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
21013#undef TARGET_LITTLE_NAME
21014#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
21015#undef TARGET_BIG_SYM
21016#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
21017#undef TARGET_BIG_NAME
21018#define TARGET_BIG_NAME "elf32-bigarm-symbian"
7f266840
DJ		 21019
21020/* Like elf32_arm_link_hash_table_create -- but overrides
21021 appropriately for Symbian OS. */
906e58ca 21022
7f266840
DJ		 21023static struct bfd_link_hash_table *
21024elf32_arm_symbian_link_hash_table_create (bfd *abfd)
21025{
21026 struct bfd_link_hash_table *ret;
21027
21028 ret = elf32_arm_link_hash_table_create (abfd);
21029 if (ret)
21030 {
21031 struct elf32_arm_link_hash_table *htab
21032 = (struct elf32_arm_link_hash_table *)ret;
21033 /* There is no PLT header for Symbian OS. */
21034 htab->plt_header_size = 0;
95720a86
DJ		 21035 /* The PLT entries are each one instruction and one word. */
21036 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 21037 htab->symbian_p = 1;
33bfe774
JB		 21038 /* Symbian uses armv5t or above, so use_blx is always true. */
21039 htab->use_blx = 1;
67687978 21040 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 21041 }
21042 return ret;
906e58ca 21043}
7f266840 21044
b35d266b 21045static const struct bfd_elf_special_section
551b43fd 21046elf32_arm_symbian_special_sections[] =
7f266840 21047{
5cd3778d
MM		 21048 /* In a BPABI executable, the dynamic linking sections do not go in
21049 the loadable read-only segment. The post-linker may wish to
21050 refer to these sections, but they are not part of the final
21051 program image. */
07d6d2b8
AM		 21052 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
21053 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
21054 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
21055 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
21056 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 21057 /* These sections do not need to be writable as the SymbianOS
21058 postlinker will arrange things so that no dynamic relocation is
21059 required. */
07d6d2b8
AM		 21060 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
21061 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
0112cd26 21062 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
07d6d2b8 21063 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 21064};
21065
c3c76620 21066static void
906e58ca 21067elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 21068 struct bfd_link_info *link_info)
c3c76620
MM		 21069{
21070 /* BPABI objects are never loaded directly by an OS kernel; they are
21071 processed by a postlinker first, into an OS-specific format. If
21072 the D_PAGED bit is set on the file, BFD will align segments on
21073 page boundaries, so that an OS can directly map the file. With
21074 BPABI objects, that just results in wasted space. In addition,
21075 because we clear the D_PAGED bit, map_sections_to_segments will
21076 recognize that the program headers should not be mapped into any
21077 loadable segment. */
21078 abfd->flags &= ~D_PAGED;
906e58ca 21079 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 21080}
7f266840
DJ		 21081
21082static bfd_boolean
906e58ca 21083elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 21084 struct bfd_link_info *info)
7f266840
DJ		 21085{
21086 struct elf_segment_map *m;
21087 asection *dynsec;
21088
7f266840
DJ		 21089 /* BPABI shared libraries and executables should have a PT_DYNAMIC
21090 segment. However, because the .dynamic section is not marked
21091 with SEC_LOAD, the generic ELF code will not create such a
21092 segment. */
21093 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
21094 if (dynsec)
21095 {
12bd6957 21096 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 21097 if (m->p_type == PT_DYNAMIC)
21098 break;
21099
21100 if (m == NULL)
21101 {
21102 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 21103 m->next = elf_seg_map (abfd);
21104 elf_seg_map (abfd) = m;
8ded5a0f 21105 }
7f266840
DJ		 21106 }
21107
b294bdf8
MM		 21108 /* Also call the generic arm routine. */
21109 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 21110}
21111
95720a86
DJ		 21112/* Return address for Ith PLT stub in section PLT, for relocation REL
21113 or (bfd_vma) -1 if it should not be included. */
21114
21115static bfd_vma
21116elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
21117 const arelent *rel ATTRIBUTE_UNUSED)
21118{
21119 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
21120}
21121
8029a119 21122#undef elf32_bed
7f266840
DJ		 21123#define elf32_bed elf32_arm_symbian_bed
21124
21125/* The dynamic sections are not allocated on SymbianOS; the postlinker
21126 will process them and then discard them. */
906e58ca 21127#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 21128#define ELF_DYNAMIC_SEC_FLAGS \
21129 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
21130
9eaff861 21131#undef elf_backend_emit_relocs
c3c76620 21132
906e58ca
NC		 21133#undef bfd_elf32_bfd_link_hash_table_create
21134#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
21135#undef elf_backend_special_sections
07d6d2b8 21136#define elf_backend_special_sections elf32_arm_symbian_special_sections
906e58ca
NC		 21137#undef elf_backend_begin_write_processing
21138#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
21139#undef elf_backend_final_write_processing
21140#define elf_backend_final_write_processing elf32_arm_final_write_processing
21141
21142#undef elf_backend_modify_segment_map
7f266840
DJ		 21143#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
21144
21145/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 21146#undef elf_backend_got_header_size
7f266840
DJ		 21147#define elf_backend_got_header_size 0
21148
21149/* Similarly, there is no .got.plt section. */
906e58ca 21150#undef elf_backend_want_got_plt
7f266840
DJ		 21151#define elf_backend_want_got_plt 0
21152
906e58ca 21153#undef elf_backend_plt_sym_val
95720a86
DJ		 21154#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
21155
906e58ca 21156#undef elf_backend_may_use_rel_p
00a97672 21157#define elf_backend_may_use_rel_p 1
906e58ca 21158#undef elf_backend_may_use_rela_p
00a97672 21159#define elf_backend_may_use_rela_p 0
906e58ca 21160#undef elf_backend_default_use_rela_p
00a97672 21161#define elf_backend_default_use_rela_p 0
906e58ca 21162#undef elf_backend_want_plt_sym
00a97672 21163#define elf_backend_want_plt_sym 0
64f52338
AM		 21164#undef elf_backend_dtrel_excludes_plt
21165#define elf_backend_dtrel_excludes_plt 0
906e58ca 21166#undef ELF_MAXPAGESIZE
00a97672 21167#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 21168
7f266840 21169#include "elf32-target.h"
GDB Binutils - Deliverables
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