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[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
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252b5132 1/* 32-bit ELF support for ARM
b90efa5b 2 Copyright (C) 1998-2015 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
7f266840
DJ		 59#define elf_info_to_howto 0
60#define elf_info_to_howto_rel elf32_arm_info_to_howto
61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
240 HOWTO (R_ARM_THM_PC8, /* type */
241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
99059e56
RM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
99059e56
RM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
99059e56
RM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
99059e56
RM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
99059e56
RM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
99059e56
RM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
99059e56
RM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
99059e56
RM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
99059e56
RM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
446 TRUE, /* pc_relative */
447 0, /* bitpos */
448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
99059e56
RM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
460 FALSE, /* pc_relative */
461 0, /* bitpos */
462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
99059e56
RM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
474 TRUE, /* pc_relative */
475 0, /* bitpos */
476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
909 HOWTO (R_ARM_ALU_PC_G0, /* type */
910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
917 "R_ARM_ALU_PC_G0", /* name */
918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
937 HOWTO (R_ARM_ALU_PC_G1, /* type */
938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
945 "R_ARM_ALU_PC_G1", /* name */
946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
951 HOWTO (R_ARM_ALU_PC_G2, /* type */
952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
959 "R_ARM_ALU_PC_G2", /* name */
960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
965 HOWTO (R_ARM_LDR_PC_G1, /* type */
966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
973 "R_ARM_LDR_PC_G1", /* name */
974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
979 HOWTO (R_ARM_LDR_PC_G2, /* type */
980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
987 "R_ARM_LDR_PC_G2", /* name */
988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
1001 "R_ARM_LDRS_PC_G0", /* name */
1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
1015 "R_ARM_LDRS_PC_G1", /* name */
1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
1029 "R_ARM_LDRS_PC_G2", /* name */
1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
1043 "R_ARM_LDC_PC_G0", /* name */
1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
1057 "R_ARM_LDC_PC_G1", /* name */
1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
1071 "R_ARM_LDC_PC_G2", /* name */
1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
1085 "R_ARM_ALU_SB_G0_NC", /* name */
1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
1099 "R_ARM_ALU_SB_G0", /* name */
1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
1113 "R_ARM_ALU_SB_G1_NC", /* name */
1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
1127 "R_ARM_ALU_SB_G1", /* name */
1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
1141 "R_ARM_ALU_SB_G2", /* name */
1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
1155 "R_ARM_LDR_SB_G0", /* name */
1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
1169 "R_ARM_LDR_SB_G1", /* name */
1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
1183 "R_ARM_LDR_SB_G2", /* name */
1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
1197 "R_ARM_LDRS_SB_G0", /* name */
1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
1211 "R_ARM_LDRS_SB_G1", /* name */
1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
1225 "R_ARM_LDRS_SB_G2", /* name */
1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
1239 "R_ARM_LDC_SB_G0", /* name */
1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
1253 "R_ARM_LDC_SB_G1", /* name */
1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
1267 "R_ARM_LDC_SB_G2", /* name */
1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
1486
1487 /* GNU extension to record C++ vtable member usage */
1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
99059e56
RM		 1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
1494 complain_overflow_dont, /* complain_on_overflow */
1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
99059e56
RM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
1509 complain_overflow_dont, /* complain_on_overflow */
1510 NULL, /* special_function */
1511 "R_ARM_GNU_VTINHERIT", /* name */
1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
99059e56
RM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
99059e56
RM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
99059e56
RM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
99059e56
RM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
99059e56
RM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
1608 complain_overflow_bitfield,/* complain_on_overflow */
75c11999 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
c19d1205
ZW		 1692};
1693
34e77a92
RS		 1694/* 160 onwards: */
1695static reloc_howto_type elf32_arm_howto_table_2[1] =
1696{
1697 HOWTO (R_ARM_IRELATIVE, /* type */
99059e56
RM		 1698 0, /* rightshift */
1699 2, /* size (0 = byte, 1 = short, 2 = long) */
1700 32, /* bitsize */
1701 FALSE, /* pc_relative */
1702 0, /* bitpos */
1703 complain_overflow_bitfield,/* complain_on_overflow */
1704 bfd_elf_generic_reloc, /* special_function */
1705 "R_ARM_IRELATIVE", /* name */
1706 TRUE, /* partial_inplace */
1707 0xffffffff, /* src_mask */
1708 0xffffffff, /* dst_mask */
1709 FALSE) /* pcrel_offset */
34e77a92 1710};
c19d1205 1711
34e77a92
RS		 1712/* 249-255 extended, currently unused, relocations: */
1713static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1714{
1715 HOWTO (R_ARM_RREL32, /* type */
1716 0, /* rightshift */
1717 0, /* size (0 = byte, 1 = short, 2 = long) */
1718 0, /* bitsize */
1719 FALSE, /* pc_relative */
1720 0, /* bitpos */
1721 complain_overflow_dont,/* complain_on_overflow */
1722 bfd_elf_generic_reloc, /* special_function */
1723 "R_ARM_RREL32", /* name */
1724 FALSE, /* partial_inplace */
1725 0, /* src_mask */
1726 0, /* dst_mask */
1727 FALSE), /* pcrel_offset */
1728
1729 HOWTO (R_ARM_RABS32, /* type */
1730 0, /* rightshift */
1731 0, /* size (0 = byte, 1 = short, 2 = long) */
1732 0, /* bitsize */
1733 FALSE, /* pc_relative */
1734 0, /* bitpos */
1735 complain_overflow_dont,/* complain_on_overflow */
1736 bfd_elf_generic_reloc, /* special_function */
1737 "R_ARM_RABS32", /* name */
1738 FALSE, /* partial_inplace */
1739 0, /* src_mask */
1740 0, /* dst_mask */
1741 FALSE), /* pcrel_offset */
1742
1743 HOWTO (R_ARM_RPC24, /* type */
1744 0, /* rightshift */
1745 0, /* size (0 = byte, 1 = short, 2 = long) */
1746 0, /* bitsize */
1747 FALSE, /* pc_relative */
1748 0, /* bitpos */
1749 complain_overflow_dont,/* complain_on_overflow */
1750 bfd_elf_generic_reloc, /* special_function */
1751 "R_ARM_RPC24", /* name */
1752 FALSE, /* partial_inplace */
1753 0, /* src_mask */
1754 0, /* dst_mask */
1755 FALSE), /* pcrel_offset */
1756
1757 HOWTO (R_ARM_RBASE, /* type */
1758 0, /* rightshift */
1759 0, /* size (0 = byte, 1 = short, 2 = long) */
1760 0, /* bitsize */
1761 FALSE, /* pc_relative */
1762 0, /* bitpos */
1763 complain_overflow_dont,/* complain_on_overflow */
1764 bfd_elf_generic_reloc, /* special_function */
1765 "R_ARM_RBASE", /* name */
1766 FALSE, /* partial_inplace */
1767 0, /* src_mask */
1768 0, /* dst_mask */
1769 FALSE) /* pcrel_offset */
1770};
1771
1772static reloc_howto_type *
1773elf32_arm_howto_from_type (unsigned int r_type)
1774{
906e58ca 1775 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1776 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1777
34e77a92
RS		 1778 if (r_type == R_ARM_IRELATIVE)
1779 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1780
c19d1205 1781 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1782 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1783 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1784
c19d1205 1785 return NULL;
7f266840
DJ		 1786}
1787
1788static void
1789elf32_arm_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, arelent * bfd_reloc,
1790 Elf_Internal_Rela * elf_reloc)
1791{
1792 unsigned int r_type;
1793
1794 r_type = ELF32_R_TYPE (elf_reloc->r_info);
1795 bfd_reloc->howto = elf32_arm_howto_from_type (r_type);
1796}
1797
1798struct elf32_arm_reloc_map
1799 {
1800 bfd_reloc_code_real_type bfd_reloc_val;
1801 unsigned char elf_reloc_val;
1802 };
1803
1804/* All entries in this list must also be present in elf32_arm_howto_table. */
1805static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1806 {
1807 {BFD_RELOC_NONE, R_ARM_NONE},
1808 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1809 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1810 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
7f266840
DJ		 1811 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1812 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1813 {BFD_RELOC_32, R_ARM_ABS32},
1814 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1815 {BFD_RELOC_8, R_ARM_ABS8},
1816 {BFD_RELOC_16, R_ARM_ABS16},
1817 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
1818 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1819 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1820 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1821 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1822 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1823 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1824 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
7f266840
DJ		 1825 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1826 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1827 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
c19d1205 1828 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
7f266840 1829 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
b43420e6 1830 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
7f266840
DJ		 1831 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1832 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1833 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1834 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1835 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1836 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac
DJ		 1837 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
1838 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
0855e32b
NS		 1839 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1840 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
1841 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
1842 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
1843 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
1844 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1845 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1846 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1847 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1848 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1849 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
1850 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1851 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1852 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
34e77a92 1853 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
c19d1205
ZW		 1854 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1855 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1856 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1857 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1858 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1859 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1860 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1861 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1862 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1863 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1864 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1865 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1866 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1867 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1868 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1869 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1870 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1871 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1872 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1873 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1874 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1875 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1876 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1877 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1878 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1879 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1880 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
1881 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
1882 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
1883 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
1884 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
1885 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
1886 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
1887 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
1888 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
1889 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
1890 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6
PB		 1891 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
1892 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX}
7f266840
DJ		 1893 };
1894
1895static reloc_howto_type *
f1c71a59
ZW		 1896elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1897 bfd_reloc_code_real_type code)
7f266840
DJ		 1898{
1899 unsigned int i;
8029a119 1900
906e58ca 1901 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 1902 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
1903 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 1904
c19d1205 1905 return NULL;
7f266840
DJ		 1906}
1907
157090f7
AM		 1908static reloc_howto_type *
1909elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1910 const char *r_name)
1911{
1912 unsigned int i;
1913
906e58ca 1914 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 1915 if (elf32_arm_howto_table_1[i].name != NULL
1916 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
1917 return &elf32_arm_howto_table_1[i];
1918
906e58ca 1919 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 1920 if (elf32_arm_howto_table_2[i].name != NULL
1921 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
1922 return &elf32_arm_howto_table_2[i];
1923
34e77a92
RS		 1924 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
1925 if (elf32_arm_howto_table_3[i].name != NULL
1926 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
1927 return &elf32_arm_howto_table_3[i];
1928
157090f7
AM		 1929 return NULL;
1930}
1931
906e58ca
NC		 1932/* Support for core dump NOTE sections. */
1933
7f266840 1934static bfd_boolean
f1c71a59 1935elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 1936{
1937 int offset;
1938 size_t size;
1939
1940 switch (note->descsz)
1941 {
1942 default:
1943 return FALSE;
1944
8029a119 1945 case 148: /* Linux/ARM 32-bit. */
7f266840 1946 /* pr_cursig */
228e534f 1947 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 1948
1949 /* pr_pid */
228e534f 1950 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 1951
1952 /* pr_reg */
1953 offset = 72;
1954 size = 72;
1955
1956 break;
1957 }
1958
1959 /* Make a ".reg/999" section. */
1960 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
1961 size, note->descpos + offset);
1962}
1963
1964static bfd_boolean
f1c71a59 1965elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 1966{
1967 switch (note->descsz)
1968 {
1969 default:
1970 return FALSE;
1971
8029a119 1972 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 1973 elf_tdata (abfd)->core->pid
4395ee08 1974 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 1975 elf_tdata (abfd)->core->program
7f266840 1976 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 1977 elf_tdata (abfd)->core->command
7f266840
DJ		 1978 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
1979 }
1980
1981 /* Note that for some reason, a spurious space is tacked
1982 onto the end of the args in some (at least one anyway)
1983 implementations, so strip it off if it exists. */
7f266840 1984 {
228e534f 1985 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 1986 int n = strlen (command);
1987
1988 if (0 < n && command[n - 1] == ' ')
1989 command[n - 1] = '\0';
1990 }
1991
1992 return TRUE;
1993}
1994
1f20dca5
UW		 1995static char *
1996elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
1997 int note_type, ...)
1998{
1999 switch (note_type)
2000 {
2001 default:
2002 return NULL;
2003
2004 case NT_PRPSINFO:
2005 {
2006 char data[124];
2007 va_list ap;
2008
2009 va_start (ap, note_type);
2010 memset (data, 0, sizeof (data));
2011 strncpy (data + 28, va_arg (ap, const char *), 16);
2012 strncpy (data + 44, va_arg (ap, const char *), 80);
2013 va_end (ap);
2014
2015 return elfcore_write_note (abfd, buf, bufsiz,
2016 "CORE", note_type, data, sizeof (data));
2017 }
2018
2019 case NT_PRSTATUS:
2020 {
2021 char data[148];
2022 va_list ap;
2023 long pid;
2024 int cursig;
2025 const void *greg;
2026
2027 va_start (ap, note_type);
2028 memset (data, 0, sizeof (data));
2029 pid = va_arg (ap, long);
2030 bfd_put_32 (abfd, pid, data + 24);
2031 cursig = va_arg (ap, int);
2032 bfd_put_16 (abfd, cursig, data + 12);
2033 greg = va_arg (ap, const void *);
2034 memcpy (data + 72, greg, 72);
2035 va_end (ap);
2036
2037 return elfcore_write_note (abfd, buf, bufsiz,
2038 "CORE", note_type, data, sizeof (data));
2039 }
2040 }
2041}
2042
6d00b590 2043#define TARGET_LITTLE_SYM arm_elf32_le_vec
7f266840 2044#define TARGET_LITTLE_NAME "elf32-littlearm"
6d00b590 2045#define TARGET_BIG_SYM arm_elf32_be_vec
7f266840
DJ		 2046#define TARGET_BIG_NAME "elf32-bigarm"
2047
2048#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2049#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2050#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2051
252b5132
RH		 2052typedef unsigned long int insn32;
2053typedef unsigned short int insn16;
2054
3a4a14e9
PB		 2055/* In lieu of proper flags, assume all EABIv4 or later objects are
2056 interworkable. */
57e8b36a 2057#define INTERWORK_FLAG(abfd) \
3a4a14e9 2058 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2059 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2060 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2061
252b5132
RH		 2062/* The linker script knows the section names for placement.
2063 The entry_names are used to do simple name mangling on the stubs.
2064 Given a function name, and its type, the stub can be found. The
9b485d32 2065 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2066#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2067#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2068
2069#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2070#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2071
c7b8f16e
JB		 2072#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2073#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2074
a504d23a
LA		 2075#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2076#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2077
845b51d6
PB		 2078#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2079#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2080
7413f23f
DJ		 2081#define STUB_ENTRY_NAME "__%s_veneer"
2082
252b5132
RH		 2083/* The name of the dynamic interpreter. This is put in the .interp
2084 section. */
2085#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2086
0855e32b 2087static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2088{
2089 0xe08e0000, /* add r0, lr, r0 */
2090 0xe5901004, /* ldr r1, [r0,#4] */
2091 0xe12fff11, /* bx r1 */
2092};
0855e32b
NS		 2093
2094static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2095{
2096 0xe52d2004, /* push {r2} */
2097 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2098 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2099 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2100 0xe081100f, /* 2: add r1, pc */
2101 0xe12fff12, /* bx r2 */
2102 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2103 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2104 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2105};
0855e32b 2106
5e681ec4
PB		 2107#ifdef FOUR_WORD_PLT
2108
252b5132
RH		 2109/* The first entry in a procedure linkage table looks like
2110 this. It is set up so that any shared library function that is
59f2c4e7 2111 called before the relocation has been set up calls the dynamic
9b485d32 2112 linker first. */
e5a52504 2113static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2114{
2115 0xe52de004, /* str lr, [sp, #-4]! */
2116 0xe59fe010, /* ldr lr, [pc, #16] */
2117 0xe08fe00e, /* add lr, pc, lr */
2118 0xe5bef008, /* ldr pc, [lr, #8]! */
2119};
5e681ec4
PB		 2120
2121/* Subsequent entries in a procedure linkage table look like
2122 this. */
e5a52504 2123static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2124{
2125 0xe28fc600, /* add ip, pc, #NN */
2126 0xe28cca00, /* add ip, ip, #NN */
2127 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2128 0x00000000, /* unused */
2129};
5e681ec4 2130
eed94f8f 2131#else /* not FOUR_WORD_PLT */
5e681ec4 2132
5e681ec4
PB		 2133/* The first entry in a procedure linkage table looks like
2134 this. It is set up so that any shared library function that is
2135 called before the relocation has been set up calls the dynamic
2136 linker first. */
e5a52504 2137static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2138{
2139 0xe52de004, /* str lr, [sp, #-4]! */
2140 0xe59fe004, /* ldr lr, [pc, #4] */
2141 0xe08fe00e, /* add lr, pc, lr */
2142 0xe5bef008, /* ldr pc, [lr, #8]! */
2143 0x00000000, /* &GOT[0] - . */
2144};
252b5132 2145
1db37fe6
YG		 2146/* By default subsequent entries in a procedure linkage table look like
2147 this. Offsets that don't fit into 28 bits will cause link error. */
2148static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2149{
2150 0xe28fc600, /* add ip, pc, #0xNN00000 */
2151 0xe28cca00, /* add ip, ip, #0xNN000 */
2152 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2153};
5e681ec4 2154
1db37fe6
YG		 2155/* When explicitly asked, we'll use this "long" entry format
2156 which can cope with arbitrary displacements. */
2157static const bfd_vma elf32_arm_plt_entry_long [] =
2158{
2159 0xe28fc200, /* add ip, pc, #0xN0000000 */
2160 0xe28cc600, /* add ip, ip, #0xNN00000 */
2161 0xe28cca00, /* add ip, ip, #0xNN000 */
2162 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2163};
2164
2165static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2166
eed94f8f
NC		 2167#endif /* not FOUR_WORD_PLT */
2168
2169/* The first entry in a procedure linkage table looks like this.
2170 It is set up so that any shared library function that is called before the
2171 relocation has been set up calls the dynamic linker first. */
2172static const bfd_vma elf32_thumb2_plt0_entry [] =
2173{
2174 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2175 an instruction maybe encoded to one or two array elements. */
2176 0xf8dfb500, /* push {lr} */
2177 0x44fee008, /* ldr.w lr, [pc, #8] */
469a3493 2178 /* add lr, pc */
eed94f8f
NC		 2179 0xff08f85e, /* ldr.w pc, [lr, #8]! */
2180 0x00000000, /* &GOT[0] - . */
2181};
2182
2183/* Subsequent entries in a procedure linkage table for thumb only target
2184 look like this. */
2185static const bfd_vma elf32_thumb2_plt_entry [] =
2186{
2187 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2188 an instruction maybe encoded to one or two array elements. */
2189 0x0c00f240, /* movw ip, #0xNNNN */
2190 0x0c00f2c0, /* movt ip, #0xNNNN */
2191 0xf8dc44fc, /* add ip, pc */
2192 0xbf00f000 /* ldr.w pc, [ip] */
469a3493 2193 /* nop */
eed94f8f 2194};
252b5132 2195
00a97672
RS		 2196/* The format of the first entry in the procedure linkage table
2197 for a VxWorks executable. */
2198static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb
NC		 2199{
2200 0xe52dc008, /* str ip,[sp,#-8]! */
2201 0xe59fc000, /* ldr ip,[pc] */
2202 0xe59cf008, /* ldr pc,[ip,#8] */
2203 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
2204};
00a97672
RS		 2205
2206/* The format of subsequent entries in a VxWorks executable. */
2207static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb
NC		 2208{
2209 0xe59fc000, /* ldr ip,[pc] */
2210 0xe59cf000, /* ldr pc,[ip] */
2211 0x00000000, /* .long @got */
2212 0xe59fc000, /* ldr ip,[pc] */
2213 0xea000000, /* b _PLT */
2214 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2215};
00a97672
RS		 2216
2217/* The format of entries in a VxWorks shared library. */
2218static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb
NC		 2219{
2220 0xe59fc000, /* ldr ip,[pc] */
2221 0xe79cf009, /* ldr pc,[ip,r9] */
2222 0x00000000, /* .long @got */
2223 0xe59fc000, /* ldr ip,[pc] */
2224 0xe599f008, /* ldr pc,[r9,#8] */
2225 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2226};
00a97672 2227
b7693d02
DJ		 2228/* An initial stub used if the PLT entry is referenced from Thumb code. */
2229#define PLT_THUMB_STUB_SIZE 4
2230static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2231{
2232 0x4778, /* bx pc */
2233 0x46c0 /* nop */
2234};
b7693d02 2235
e5a52504
MM		 2236/* The entries in a PLT when using a DLL-based target with multiple
2237 address spaces. */
906e58ca 2238static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb
NC		 2239{
2240 0xe51ff004, /* ldr pc, [pc, #-4] */
2241 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
2242};
2243
2244/* The first entry in a procedure linkage table looks like
2245 this. It is set up so that any shared library function that is
2246 called before the relocation has been set up calls the dynamic
2247 linker first. */
2248static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2249{
2250 /* First bundle: */
2251 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2252 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2253 0xe08cc00f, /* add ip, ip, pc */
2254 0xe52dc008, /* str ip, [sp, #-8]! */
2255 /* Second bundle: */
edccdf7c
RM		 2256 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2257 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2258 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2259 0xe12fff1c, /* bx ip */
b38cadfb 2260 /* Third bundle: */
edccdf7c
RM		 2261 0xe320f000, /* nop */
2262 0xe320f000, /* nop */
2263 0xe320f000, /* nop */
b38cadfb
NC		 2264 /* .Lplt_tail: */
2265 0xe50dc004, /* str ip, [sp, #-4] */
2266 /* Fourth bundle: */
edccdf7c
RM		 2267 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2268 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2269 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2270 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2271};
2272#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2273
2274/* Subsequent entries in a procedure linkage table look like this. */
2275static const bfd_vma elf32_arm_nacl_plt_entry [] =
2276{
2277 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2278 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2279 0xe08cc00f, /* add ip, ip, pc */
2280 0xea000000, /* b .Lplt_tail */
2281};
e5a52504 2282
906e58ca
NC		 2283#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2284#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2285#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2286#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2287#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2288#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2289#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2290#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2291
461a49ca 2292enum stub_insn_type
b38cadfb
NC		 2293{
2294 THUMB16_TYPE = 1,
2295 THUMB32_TYPE,
2296 ARM_TYPE,
2297 DATA_TYPE
2298};
461a49ca 2299
48229727
JB		 2300#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2301/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2302 is inserted in arm_build_one_stub(). */
2303#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2304#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2305#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2306#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2307#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2308#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2309
2310typedef struct
2311{
b38cadfb
NC		 2312 bfd_vma data;
2313 enum stub_insn_type type;
2314 unsigned int r_type;
2315 int reloc_addend;
461a49ca
DJ		 2316} insn_sequence;
2317
fea2b4d6
CL		 2318/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2319 to reach the stub if necessary. */
461a49ca 2320static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb
NC		 2321{
2322 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2323 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2324};
906e58ca 2325
fea2b4d6
CL		 2326/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2327 available. */
461a49ca 2328static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb
NC		 2329{
2330 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2331 ARM_INSN (0xe12fff1c), /* bx ip */
2332 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2333};
906e58ca 2334
d3626fb0 2335/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2336static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb
NC		 2337{
2338 THUMB16_INSN (0xb401), /* push {r0} */
2339 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2340 THUMB16_INSN (0x4684), /* mov ip, r0 */
2341 THUMB16_INSN (0xbc01), /* pop {r0} */
2342 THUMB16_INSN (0x4760), /* bx ip */
2343 THUMB16_INSN (0xbf00), /* nop */
2344 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2345};
906e58ca 2346
d3626fb0
CL		 2347/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2348 allowed. */
2349static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb
NC		 2350{
2351 THUMB16_INSN (0x4778), /* bx pc */
2352 THUMB16_INSN (0x46c0), /* nop */
2353 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2354 ARM_INSN (0xe12fff1c), /* bx ip */
2355 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2356};
d3626fb0 2357
fea2b4d6
CL		 2358/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2359 available. */
461a49ca 2360static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2361{
2362 THUMB16_INSN (0x4778), /* bx pc */
2363 THUMB16_INSN (0x46c0), /* nop */
2364 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2365 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2366};
906e58ca 2367
fea2b4d6
CL		 2368/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2369 one, when the destination is close enough. */
461a49ca 2370static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2371{
2372 THUMB16_INSN (0x4778), /* bx pc */
2373 THUMB16_INSN (0x46c0), /* nop */
2374 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2375};
c820be07 2376
cf3eccff 2377/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2378 blx to reach the stub if necessary. */
cf3eccff 2379static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb
NC		 2380{
2381 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2382 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
2383 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2384};
906e58ca 2385
cf3eccff
DJ		 2386/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2387 blx to reach the stub if necessary. We can not add into pc;
2388 it is not guaranteed to mode switch (different in ARMv6 and
2389 ARMv7). */
2390static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb
NC		 2391{
2392 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2393 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2394 ARM_INSN (0xe12fff1c), /* bx ip */
2395 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2396};
cf3eccff 2397
ebe24dd4
CL		 2398/* V4T ARM -> ARM long branch stub, PIC. */
2399static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb
NC		 2400{
2401 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2402 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2403 ARM_INSN (0xe12fff1c), /* bx ip */
2404 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2405};
ebe24dd4
CL		 2406
2407/* V4T Thumb -> ARM long branch stub, PIC. */
2408static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb
NC		 2409{
2410 THUMB16_INSN (0x4778), /* bx pc */
2411 THUMB16_INSN (0x46c0), /* nop */
2412 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2413 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
2414 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2415};
ebe24dd4 2416
d3626fb0
CL		 2417/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2418 architectures. */
ebe24dd4 2419static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb
NC		 2420{
2421 THUMB16_INSN (0xb401), /* push {r0} */
2422 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2423 THUMB16_INSN (0x46fc), /* mov ip, pc */
2424 THUMB16_INSN (0x4484), /* add ip, r0 */
2425 THUMB16_INSN (0xbc01), /* pop {r0} */
2426 THUMB16_INSN (0x4760), /* bx ip */
2427 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2428};
ebe24dd4 2429
d3626fb0
CL		 2430/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2431 allowed. */
2432static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb
NC		 2433{
2434 THUMB16_INSN (0x4778), /* bx pc */
2435 THUMB16_INSN (0x46c0), /* nop */
2436 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2437 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2438 ARM_INSN (0xe12fff1c), /* bx ip */
2439 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2440};
d3626fb0 2441
0855e32b
NS		 2442/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2443 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2444static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2445{
b38cadfb
NC		 2446 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2447 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
2448 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2449};
2450
2451/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2452 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2453static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2454{
b38cadfb
NC		 2455 THUMB16_INSN (0x4778), /* bx pc */
2456 THUMB16_INSN (0x46c0), /* nop */
2457 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2458 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
2459 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2460};
2461
7a89b94e
NC		 2462/* NaCl ARM -> ARM long branch stub. */
2463static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2464{
2465 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2466 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2467 ARM_INSN (0xe12fff1c), /* bx ip */
2468 ARM_INSN (0xe320f000), /* nop */
2469 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2470 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2471 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2472 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2473};
2474
2475/* NaCl ARM -> ARM long branch stub, PIC. */
2476static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2477{
2478 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2479 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
2480 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2481 ARM_INSN (0xe12fff1c), /* bx ip */
2482 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2483 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2484 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2485 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2486};
2487
2488
48229727
JB		 2489/* Cortex-A8 erratum-workaround stubs. */
2490
2491/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2492 can't use a conditional branch to reach this stub). */
2493
2494static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb
NC		 2495{
2496 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
2497 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2498 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2499};
48229727
JB		 2500
2501/* Stub used for b.w and bl.w instructions. */
2502
2503static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2504{
2505 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2506};
48229727
JB		 2507
2508static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2509{
2510 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2511};
48229727
JB		 2512
2513/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2514 instruction (which switches to ARM mode) to point to this stub. Jump to the
2515 real destination using an ARM-mode branch. */
2516
2517static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2518{
2519 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2520};
48229727 2521
9553db3c
NC		 2522/* For each section group there can be a specially created linker section
2523 to hold the stubs for that group. The name of the stub section is based
2524 upon the name of another section within that group with the suffix below
2525 applied.
2526
2527 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2528 create what appeared to be a linker stub section when it actually
2529 contained user code/data. For example, consider this fragment:
b38cadfb 2530
9553db3c
NC		 2531 const char * stubborn_problems[] = { "np" };
2532
2533 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2534 section called:
2535
2536 .data.rel.local.stubborn_problems
2537
2538 This then causes problems in arm32_arm_build_stubs() as it triggers:
2539
2540 // Ignore non-stub sections.
2541 if (!strstr (stub_sec->name, STUB_SUFFIX))
2542 continue;
2543
2544 And so the section would be ignored instead of being processed. Hence
2545 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2546 C identifier. */
2547#define STUB_SUFFIX ".__stub"
906e58ca 2548
738a79f6
CL		 2549/* One entry per long/short branch stub defined above. */
2550#define DEF_STUBS \
2551 DEF_STUB(long_branch_any_any) \
2552 DEF_STUB(long_branch_v4t_arm_thumb) \
2553 DEF_STUB(long_branch_thumb_only) \
2554 DEF_STUB(long_branch_v4t_thumb_thumb) \
2555 DEF_STUB(long_branch_v4t_thumb_arm) \
2556 DEF_STUB(short_branch_v4t_thumb_arm) \
2557 DEF_STUB(long_branch_any_arm_pic) \
2558 DEF_STUB(long_branch_any_thumb_pic) \
2559 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2560 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2561 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2562 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2563 DEF_STUB(long_branch_any_tls_pic) \
2564 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2565 DEF_STUB(long_branch_arm_nacl) \
2566 DEF_STUB(long_branch_arm_nacl_pic) \
48229727
JB		 2567 DEF_STUB(a8_veneer_b_cond) \
2568 DEF_STUB(a8_veneer_b) \
2569 DEF_STUB(a8_veneer_bl) \
2570 DEF_STUB(a8_veneer_blx)
738a79f6
CL		 2571
2572#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2573enum elf32_arm_stub_type
2574{
906e58ca 2575 arm_stub_none,
738a79f6 2576 DEF_STUBS
6a631e86 2577 /* Note the first a8_veneer type. */
eb7c4339 2578 arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond
738a79f6
CL		 2579};
2580#undef DEF_STUB
2581
2582typedef struct
2583{
d3ce72d0 2584 const insn_sequence* template_sequence;
738a79f6
CL		 2585 int template_size;
2586} stub_def;
2587
2588#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2589static const stub_def stub_definitions[] =
2590{
738a79f6
CL		 2591 {NULL, 0},
2592 DEF_STUBS
906e58ca
NC		 2593};
2594
2595struct elf32_arm_stub_hash_entry
2596{
2597 /* Base hash table entry structure. */
2598 struct bfd_hash_entry root;
2599
2600 /* The stub section. */
2601 asection *stub_sec;
2602
2603 /* Offset within stub_sec of the beginning of this stub. */
2604 bfd_vma stub_offset;
2605
2606 /* Given the symbol's value and its section we can determine its final
2607 value when building the stubs (so the stub knows where to jump). */
2608 bfd_vma target_value;
2609 asection *target_section;
2610
48229727
JB		 2611 /* Offset to apply to relocation referencing target_value. */
2612 bfd_vma target_addend;
2613
2614 /* The instruction which caused this stub to be generated (only valid for
2615 Cortex-A8 erratum workaround stubs at present). */
2616 unsigned long orig_insn;
2617
461a49ca 2618 /* The stub type. */
906e58ca 2619 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2620 /* Its encoding size in bytes. */
2621 int stub_size;
2622 /* Its template. */
2623 const insn_sequence *stub_template;
2624 /* The size of the template (number of entries). */
2625 int stub_template_size;
906e58ca
NC		 2626
2627 /* The symbol table entry, if any, that this was derived from. */
2628 struct elf32_arm_link_hash_entry *h;
2629
35fc36a8
RS		 2630 /* Type of branch. */
2631 enum arm_st_branch_type branch_type;
906e58ca
NC		 2632
2633 /* Where this stub is being called from, or, in the case of combined
2634 stub sections, the first input section in the group. */
2635 asection *id_sec;
7413f23f
DJ		 2636
2637 /* The name for the local symbol at the start of this stub. The
2638 stub name in the hash table has to be unique; this does not, so
2639 it can be friendlier. */
2640 char *output_name;
906e58ca
NC		 2641};
2642
e489d0ae
PB		 2643/* Used to build a map of a section. This is required for mixed-endian
2644 code/data. */
2645
2646typedef struct elf32_elf_section_map
2647{
2648 bfd_vma vma;
2649 char type;
2650}
2651elf32_arm_section_map;
2652
c7b8f16e
JB		 2653/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2654
2655typedef enum
2656{
2657 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2658 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2659 VFP11_ERRATUM_ARM_VENEER,
2660 VFP11_ERRATUM_THUMB_VENEER
2661}
2662elf32_vfp11_erratum_type;
2663
2664typedef struct elf32_vfp11_erratum_list
2665{
2666 struct elf32_vfp11_erratum_list *next;
2667 bfd_vma vma;
2668 union
2669 {
2670 struct
2671 {
2672 struct elf32_vfp11_erratum_list *veneer;
2673 unsigned int vfp_insn;
2674 } b;
2675 struct
2676 {
2677 struct elf32_vfp11_erratum_list *branch;
2678 unsigned int id;
2679 } v;
2680 } u;
2681 elf32_vfp11_erratum_type type;
2682}
2683elf32_vfp11_erratum_list;
2684
a504d23a
LA		 2685/* Information about a STM32L4XX erratum veneer, or a branch to such a
2686 veneer. */
2687typedef enum
2688{
2689 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2690 STM32L4XX_ERRATUM_VENEER
2691}
2692elf32_stm32l4xx_erratum_type;
2693
2694typedef struct elf32_stm32l4xx_erratum_list
2695{
2696 struct elf32_stm32l4xx_erratum_list *next;
2697 bfd_vma vma;
2698 union
2699 {
2700 struct
2701 {
2702 struct elf32_stm32l4xx_erratum_list *veneer;
2703 unsigned int insn;
2704 } b;
2705 struct
2706 {
2707 struct elf32_stm32l4xx_erratum_list *branch;
2708 unsigned int id;
2709 } v;
2710 } u;
2711 elf32_stm32l4xx_erratum_type type;
2712}
2713elf32_stm32l4xx_erratum_list;
2714
2468f9c9
PB		 2715typedef enum
2716{
2717 DELETE_EXIDX_ENTRY,
2718 INSERT_EXIDX_CANTUNWIND_AT_END
2719}
2720arm_unwind_edit_type;
2721
2722/* A (sorted) list of edits to apply to an unwind table. */
2723typedef struct arm_unwind_table_edit
2724{
2725 arm_unwind_edit_type type;
2726 /* Note: we sometimes want to insert an unwind entry corresponding to a
2727 section different from the one we're currently writing out, so record the
2728 (text) section this edit relates to here. */
2729 asection *linked_section;
2730 unsigned int index;
2731 struct arm_unwind_table_edit *next;
2732}
2733arm_unwind_table_edit;
2734
8e3de13a 2735typedef struct _arm_elf_section_data
e489d0ae 2736{
2468f9c9 2737 /* Information about mapping symbols. */
e489d0ae 2738 struct bfd_elf_section_data elf;
8e3de13a 2739 unsigned int mapcount;
c7b8f16e 2740 unsigned int mapsize;
e489d0ae 2741 elf32_arm_section_map *map;
2468f9c9 2742 /* Information about CPU errata. */
c7b8f16e
JB		 2743 unsigned int erratumcount;
2744 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2745 unsigned int stm32l4xx_erratumcount;
2746 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
2468f9c9
PB		 2747 /* Information about unwind tables. */
2748 union
2749 {
2750 /* Unwind info attached to a text section. */
2751 struct
2752 {
2753 asection *arm_exidx_sec;
2754 } text;
2755
2756 /* Unwind info attached to an .ARM.exidx section. */
2757 struct
2758 {
2759 arm_unwind_table_edit *unwind_edit_list;
2760 arm_unwind_table_edit *unwind_edit_tail;
2761 } exidx;
2762 } u;
8e3de13a
NC		 2763}
2764_arm_elf_section_data;
e489d0ae
PB		 2765
2766#define elf32_arm_section_data(sec) \
8e3de13a 2767 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2768
48229727
JB		 2769/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2770 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2771 so may be created multiple times: we use an array of these entries whilst
2772 relaxing which we can refresh easily, then create stubs for each potentially
2773 erratum-triggering instruction once we've settled on a solution. */
2774
b38cadfb
NC		 2775struct a8_erratum_fix
2776{
48229727
JB		 2777 bfd *input_bfd;
2778 asection *section;
2779 bfd_vma offset;
2780 bfd_vma addend;
2781 unsigned long orig_insn;
2782 char *stub_name;
2783 enum elf32_arm_stub_type stub_type;
35fc36a8 2784 enum arm_st_branch_type branch_type;
48229727
JB		 2785};
2786
2787/* A table of relocs applied to branches which might trigger Cortex-A8
2788 erratum. */
2789
b38cadfb
NC		 2790struct a8_erratum_reloc
2791{
48229727
JB		 2792 bfd_vma from;
2793 bfd_vma destination;
92750f34
DJ		 2794 struct elf32_arm_link_hash_entry *hash;
2795 const char *sym_name;
48229727 2796 unsigned int r_type;
35fc36a8 2797 enum arm_st_branch_type branch_type;
48229727
JB		 2798 bfd_boolean non_a8_stub;
2799};
2800
ba93b8ac
DJ		 2801/* The size of the thread control block. */
2802#define TCB_SIZE 8
2803
34e77a92
RS		 2804/* ARM-specific information about a PLT entry, over and above the usual
2805 gotplt_union. */
b38cadfb
NC		 2806struct arm_plt_info
2807{
34e77a92
RS		 2808 /* We reference count Thumb references to a PLT entry separately,
2809 so that we can emit the Thumb trampoline only if needed. */
2810 bfd_signed_vma thumb_refcount;
2811
2812 /* Some references from Thumb code may be eliminated by BL->BLX
2813 conversion, so record them separately. */
2814 bfd_signed_vma maybe_thumb_refcount;
2815
2816 /* How many of the recorded PLT accesses were from non-call relocations.
2817 This information is useful when deciding whether anything takes the
2818 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2819 non-call references to the function should resolve directly to the
2820 real runtime target. */
2821 unsigned int noncall_refcount;
2822
2823 /* Since PLT entries have variable size if the Thumb prologue is
2824 used, we need to record the index into .got.plt instead of
2825 recomputing it from the PLT offset. */
2826 bfd_signed_vma got_offset;
2827};
2828
2829/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2830struct arm_local_iplt_info
2831{
34e77a92
RS		 2832 /* The information that is usually found in the generic ELF part of
2833 the hash table entry. */
2834 union gotplt_union root;
2835
2836 /* The information that is usually found in the ARM-specific part of
2837 the hash table entry. */
2838 struct arm_plt_info arm;
2839
2840 /* A list of all potential dynamic relocations against this symbol. */
2841 struct elf_dyn_relocs *dyn_relocs;
2842};
2843
0ffa91dd 2844struct elf_arm_obj_tdata
ba93b8ac
DJ		 2845{
2846 struct elf_obj_tdata root;
2847
2848 /* tls_type for each local got entry. */
2849 char *local_got_tls_type;
ee065d83 2850
0855e32b
NS		 2851 /* GOTPLT entries for TLS descriptors. */
2852 bfd_vma *local_tlsdesc_gotent;
2853
34e77a92
RS		 2854 /* Information for local symbols that need entries in .iplt. */
2855 struct arm_local_iplt_info **local_iplt;
2856
bf21ed78
MS		 2857 /* Zero to warn when linking objects with incompatible enum sizes. */
2858 int no_enum_size_warning;
a9dc9481
JM		 2859
2860 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2861 int no_wchar_size_warning;
ba93b8ac
DJ		 2862};
2863
0ffa91dd
NC		 2864#define elf_arm_tdata(bfd) \
2865 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 2866
0ffa91dd
NC		 2867#define elf32_arm_local_got_tls_type(bfd) \
2868 (elf_arm_tdata (bfd)->local_got_tls_type)
2869
0855e32b
NS		 2870#define elf32_arm_local_tlsdesc_gotent(bfd) \
2871 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2872
34e77a92
RS		 2873#define elf32_arm_local_iplt(bfd) \
2874 (elf_arm_tdata (bfd)->local_iplt)
2875
0ffa91dd
NC		 2876#define is_arm_elf(bfd) \
2877 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2878 && elf_tdata (bfd) != NULL \
4dfe6ac6 2879 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 2880
2881static bfd_boolean
2882elf32_arm_mkobject (bfd *abfd)
2883{
0ffa91dd 2884 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 2885 ARM_ELF_DATA);
ba93b8ac
DJ		 2886}
2887
ba93b8ac
DJ		 2888#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2889
ba96a88f 2890/* Arm ELF linker hash entry. */
252b5132 2891struct elf32_arm_link_hash_entry
b38cadfb
NC		 2892{
2893 struct elf_link_hash_entry root;
252b5132 2894
b38cadfb
NC		 2895 /* Track dynamic relocs copied for this symbol. */
2896 struct elf_dyn_relocs *dyn_relocs;
b7693d02 2897
b38cadfb
NC		 2898 /* ARM-specific PLT information. */
2899 struct arm_plt_info plt;
ba93b8ac
DJ		 2900
2901#define GOT_UNKNOWN 0
2902#define GOT_NORMAL 1
2903#define GOT_TLS_GD 2
2904#define GOT_TLS_IE 4
0855e32b
NS		 2905#define GOT_TLS_GDESC 8
2906#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 2907 unsigned int tls_type : 8;
34e77a92 2908
b38cadfb
NC		 2909 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
2910 unsigned int is_iplt : 1;
34e77a92 2911
b38cadfb 2912 unsigned int unused : 23;
a4fd1a8e 2913
b38cadfb
NC		 2914 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
2915 starting at the end of the jump table. */
2916 bfd_vma tlsdesc_got;
0855e32b 2917
b38cadfb
NC		 2918 /* The symbol marking the real symbol location for exported thumb
2919 symbols with Arm stubs. */
2920 struct elf_link_hash_entry *export_glue;
906e58ca 2921
b38cadfb 2922 /* A pointer to the most recently used stub hash entry against this
8029a119 2923 symbol. */
b38cadfb
NC		 2924 struct elf32_arm_stub_hash_entry *stub_cache;
2925};
252b5132 2926
252b5132 2927/* Traverse an arm ELF linker hash table. */
252b5132
RH		 2928#define elf32_arm_link_hash_traverse(table, func, info) \
2929 (elf_link_hash_traverse \
2930 (&(table)->root, \
b7693d02 2931 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 2932 (info)))
2933
2934/* Get the ARM elf linker hash table from a link_info structure. */
2935#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 2936 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
2937 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 2938
906e58ca
NC		 2939#define arm_stub_hash_lookup(table, string, create, copy) \
2940 ((struct elf32_arm_stub_hash_entry *) \
2941 bfd_hash_lookup ((table), (string), (create), (copy)))
2942
21d799b5
NC		 2943/* Array to keep track of which stub sections have been created, and
2944 information on stub grouping. */
2945struct map_stub
2946{
2947 /* This is the section to which stubs in the group will be
2948 attached. */
2949 asection *link_sec;
2950 /* The stub section. */
2951 asection *stub_sec;
2952};
2953
0855e32b
NS		 2954#define elf32_arm_compute_jump_table_size(htab) \
2955 ((htab)->next_tls_desc_index * 4)
2956
9b485d32 2957/* ARM ELF linker hash table. */
252b5132 2958struct elf32_arm_link_hash_table
906e58ca
NC		 2959{
2960 /* The main hash table. */
2961 struct elf_link_hash_table root;
252b5132 2962
906e58ca
NC		 2963 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
2964 bfd_size_type thumb_glue_size;
252b5132 2965
906e58ca
NC		 2966 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
2967 bfd_size_type arm_glue_size;
252b5132 2968
906e58ca
NC		 2969 /* The size in bytes of section containing the ARMv4 BX veneers. */
2970 bfd_size_type bx_glue_size;
845b51d6 2971
906e58ca
NC		 2972 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
2973 veneer has been populated. */
2974 bfd_vma bx_glue_offset[15];
845b51d6 2975
906e58ca
NC		 2976 /* The size in bytes of the section containing glue for VFP11 erratum
2977 veneers. */
2978 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 2979
a504d23a
LA		 2980 /* The size in bytes of the section containing glue for STM32L4XX erratum
2981 veneers. */
2982 bfd_size_type stm32l4xx_erratum_glue_size;
2983
48229727
JB		 2984 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
2985 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
2986 elf32_arm_write_section(). */
2987 struct a8_erratum_fix *a8_erratum_fixes;
2988 unsigned int num_a8_erratum_fixes;
2989
906e58ca
NC		 2990 /* An arbitrary input BFD chosen to hold the glue sections. */
2991 bfd * bfd_of_glue_owner;
ba96a88f 2992
906e58ca
NC		 2993 /* Nonzero to output a BE8 image. */
2994 int byteswap_code;
e489d0ae 2995
906e58ca
NC		 2996 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
2997 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
2998 int target1_is_rel;
9c504268 2999
906e58ca
NC		 3000 /* The relocation to use for R_ARM_TARGET2 relocations. */
3001 int target2_reloc;
eb043451 3002
906e58ca
NC		 3003 /* 0 = Ignore R_ARM_V4BX.
3004 1 = Convert BX to MOV PC.
3005 2 = Generate v4 interworing stubs. */
3006 int fix_v4bx;
319850b4 3007
48229727
JB		 3008 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3009 int fix_cortex_a8;
3010
2de70689
MGD		 3011 /* Whether we should fix the ARM1176 BLX immediate issue. */
3012 int fix_arm1176;
3013
906e58ca
NC		 3014 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3015 int use_blx;
33bfe774 3016
906e58ca
NC		 3017 /* What sort of code sequences we should look for which may trigger the
3018 VFP11 denorm erratum. */
3019 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3020
906e58ca
NC		 3021 /* Global counter for the number of fixes we have emitted. */
3022 int num_vfp11_fixes;
c7b8f16e 3023
a504d23a
LA		 3024 /* What sort of code sequences we should look for which may trigger the
3025 STM32L4XX erratum. */
3026 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3027
3028 /* Global counter for the number of fixes we have emitted. */
3029 int num_stm32l4xx_fixes;
3030
906e58ca
NC		 3031 /* Nonzero to force PIC branch veneers. */
3032 int pic_veneer;
27e55c4d 3033
906e58ca
NC		 3034 /* The number of bytes in the initial entry in the PLT. */
3035 bfd_size_type plt_header_size;
e5a52504 3036
906e58ca
NC		 3037 /* The number of bytes in the subsequent PLT etries. */
3038 bfd_size_type plt_entry_size;
e5a52504 3039
906e58ca
NC		 3040 /* True if the target system is VxWorks. */
3041 int vxworks_p;
00a97672 3042
906e58ca
NC		 3043 /* True if the target system is Symbian OS. */
3044 int symbian_p;
e5a52504 3045
b38cadfb
NC		 3046 /* True if the target system is Native Client. */
3047 int nacl_p;
3048
906e58ca
NC		 3049 /* True if the target uses REL relocations. */
3050 int use_rel;
4e7fd91e 3051
0855e32b
NS		 3052 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3053 bfd_vma next_tls_desc_index;
3054
3055 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3056 bfd_vma num_tls_desc;
3057
906e58ca 3058 /* Short-cuts to get to dynamic linker sections. */
906e58ca
NC		 3059 asection *sdynbss;
3060 asection *srelbss;
5e681ec4 3061
906e58ca
NC		 3062 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3063 asection *srelplt2;
00a97672 3064
0855e32b
NS		 3065 /* The offset into splt of the PLT entry for the TLS descriptor
3066 resolver. Special values are 0, if not necessary (or not found
3067 to be necessary yet), and -1 if needed but not determined
3068 yet. */
3069 bfd_vma dt_tlsdesc_plt;
3070
3071 /* The offset into sgot of the GOT entry used by the PLT entry
3072 above. */
b38cadfb 3073 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3074
3075 /* Offset in .plt section of tls_arm_trampoline. */
3076 bfd_vma tls_trampoline;
3077
906e58ca
NC		 3078 /* Data for R_ARM_TLS_LDM32 relocations. */
3079 union
3080 {
3081 bfd_signed_vma refcount;
3082 bfd_vma offset;
3083 } tls_ldm_got;
b7693d02 3084
87d72d41
AM		 3085 /* Small local sym cache. */
3086 struct sym_cache sym_cache;
906e58ca
NC		 3087
3088 /* For convenience in allocate_dynrelocs. */
3089 bfd * obfd;
3090
0855e32b
NS		 3091 /* The amount of space used by the reserved portion of the sgotplt
3092 section, plus whatever space is used by the jump slots. */
3093 bfd_vma sgotplt_jump_table_size;
3094
906e58ca
NC		 3095 /* The stub hash table. */
3096 struct bfd_hash_table stub_hash_table;
3097
3098 /* Linker stub bfd. */
3099 bfd *stub_bfd;
3100
3101 /* Linker call-backs. */
7a89b94e 3102 asection * (*add_stub_section) (const char *, asection *, unsigned int);
906e58ca
NC		 3103 void (*layout_sections_again) (void);
3104
3105 /* Array to keep track of which stub sections have been created, and
3106 information on stub grouping. */
21d799b5 3107 struct map_stub *stub_group;
906e58ca 3108
fe33d2fa 3109 /* Number of elements in stub_group. */
7292b3ac 3110 unsigned int top_id;
fe33d2fa 3111
906e58ca
NC		 3112 /* Assorted information used by elf32_arm_size_stubs. */
3113 unsigned int bfd_count;
7292b3ac 3114 unsigned int top_index;
906e58ca
NC		 3115 asection **input_list;
3116};
252b5132 3117
a504d23a
LA		 3118static inline int
3119ctz (unsigned int mask)
3120{
3121#if GCC_VERSION >= 3004
3122 return __builtin_ctz (mask);
3123#else
3124 unsigned int i;
3125
3126 for (i = 0; i < 8 * sizeof (mask); i++)
3127 {
3128 if (mask & 0x1)
3129 break;
3130 mask = (mask >> 1);
3131 }
3132 return i;
3133#endif
3134}
3135
3136static inline int
3137popcount (unsigned int mask)
3138{
3139#if GCC_VERSION >= 3004
3140 return __builtin_popcount (mask);
3141#else
3142 unsigned int i, sum = 0;
3143
3144 for (i = 0; i < 8 * sizeof (mask); i++)
3145 {
3146 if (mask & 0x1)
3147 sum++;
3148 mask = (mask >> 1);
3149 }
3150 return sum;
3151#endif
3152}
3153
780a67af
NC		 3154/* Create an entry in an ARM ELF linker hash table. */
3155
3156static struct bfd_hash_entry *
57e8b36a 3157elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3158 struct bfd_hash_table * table,
3159 const char * string)
780a67af
NC		 3160{
3161 struct elf32_arm_link_hash_entry * ret =
3162 (struct elf32_arm_link_hash_entry *) entry;
3163
3164 /* Allocate the structure if it has not already been allocated by a
3165 subclass. */
906e58ca 3166 if (ret == NULL)
21d799b5 3167 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3168 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3169 if (ret == NULL)
780a67af
NC		 3170 return (struct bfd_hash_entry *) ret;
3171
3172 /* Call the allocation method of the superclass. */
3173 ret = ((struct elf32_arm_link_hash_entry *)
3174 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3175 table, string));
57e8b36a 3176 if (ret != NULL)
b7693d02 3177 {
0bdcacaf 3178 ret->dyn_relocs = NULL;
ba93b8ac 3179 ret->tls_type = GOT_UNKNOWN;
0855e32b 3180 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3181 ret->plt.thumb_refcount = 0;
3182 ret->plt.maybe_thumb_refcount = 0;
3183 ret->plt.noncall_refcount = 0;
3184 ret->plt.got_offset = -1;
3185 ret->is_iplt = FALSE;
a4fd1a8e 3186 ret->export_glue = NULL;
906e58ca
NC		 3187
3188 ret->stub_cache = NULL;
b7693d02 3189 }
780a67af
NC		 3190
3191 return (struct bfd_hash_entry *) ret;
3192}
3193
34e77a92
RS		 3194/* Ensure that we have allocated bookkeeping structures for ABFD's local
3195 symbols. */
3196
3197static bfd_boolean
3198elf32_arm_allocate_local_sym_info (bfd *abfd)
3199{
3200 if (elf_local_got_refcounts (abfd) == NULL)
3201 {
3202 bfd_size_type num_syms;
3203 bfd_size_type size;
3204 char *data;
3205
3206 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3207 size = num_syms * (sizeof (bfd_signed_vma)
3208 + sizeof (struct arm_local_iplt_info *)
3209 + sizeof (bfd_vma)
3210 + sizeof (char));
3211 data = bfd_zalloc (abfd, size);
3212 if (data == NULL)
3213 return FALSE;
3214
3215 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3216 data += num_syms * sizeof (bfd_signed_vma);
3217
3218 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3219 data += num_syms * sizeof (struct arm_local_iplt_info *);
3220
3221 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3222 data += num_syms * sizeof (bfd_vma);
3223
3224 elf32_arm_local_got_tls_type (abfd) = data;
3225 }
3226 return TRUE;
3227}
3228
3229/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3230 to input bfd ABFD. Create the information if it doesn't already exist.
3231 Return null if an allocation fails. */
3232
3233static struct arm_local_iplt_info *
3234elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3235{
3236 struct arm_local_iplt_info **ptr;
3237
3238 if (!elf32_arm_allocate_local_sym_info (abfd))
3239 return NULL;
3240
3241 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3242 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3243 if (*ptr == NULL)
3244 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3245 return *ptr;
3246}
3247
3248/* Try to obtain PLT information for the symbol with index R_SYMNDX
3249 in ABFD's symbol table. If the symbol is global, H points to its
3250 hash table entry, otherwise H is null.
3251
3252 Return true if the symbol does have PLT information. When returning
3253 true, point *ROOT_PLT at the target-independent reference count/offset
3254 union and *ARM_PLT at the ARM-specific information. */
3255
3256static bfd_boolean
3257elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_entry *h,
3258 unsigned long r_symndx, union gotplt_union **root_plt,
3259 struct arm_plt_info **arm_plt)
3260{
3261 struct arm_local_iplt_info *local_iplt;
3262
3263 if (h != NULL)
3264 {
3265 *root_plt = &h->root.plt;
3266 *arm_plt = &h->plt;
3267 return TRUE;
3268 }
3269
3270 if (elf32_arm_local_iplt (abfd) == NULL)
3271 return FALSE;
3272
3273 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3274 if (local_iplt == NULL)
3275 return FALSE;
3276
3277 *root_plt = &local_iplt->root;
3278 *arm_plt = &local_iplt->arm;
3279 return TRUE;
3280}
3281
3282/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3283 before it. */
3284
3285static bfd_boolean
3286elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3287 struct arm_plt_info *arm_plt)
3288{
3289 struct elf32_arm_link_hash_table *htab;
3290
3291 htab = elf32_arm_hash_table (info);
3292 return (arm_plt->thumb_refcount != 0
3293 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3294}
3295
3296/* Return a pointer to the head of the dynamic reloc list that should
3297 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3298 ABFD's symbol table. Return null if an error occurs. */
3299
3300static struct elf_dyn_relocs **
3301elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3302 Elf_Internal_Sym *isym)
3303{
3304 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3305 {
3306 struct arm_local_iplt_info *local_iplt;
3307
3308 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3309 if (local_iplt == NULL)
3310 return NULL;
3311 return &local_iplt->dyn_relocs;
3312 }
3313 else
3314 {
3315 /* Track dynamic relocs needed for local syms too.
3316 We really need local syms available to do this
3317 easily. Oh well. */
3318 asection *s;
3319 void *vpp;
3320
3321 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3322 if (s == NULL)
3323 abort ();
3324
3325 vpp = &elf_section_data (s)->local_dynrel;
3326 return (struct elf_dyn_relocs **) vpp;
3327 }
3328}
3329
906e58ca
NC		 3330/* Initialize an entry in the stub hash table. */
3331
3332static struct bfd_hash_entry *
3333stub_hash_newfunc (struct bfd_hash_entry *entry,
3334 struct bfd_hash_table *table,
3335 const char *string)
3336{
3337 /* Allocate the structure if it has not already been allocated by a
3338 subclass. */
3339 if (entry == NULL)
3340 {
21d799b5 3341 entry = (struct bfd_hash_entry *)
99059e56 3342 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3343 if (entry == NULL)
3344 return entry;
3345 }
3346
3347 /* Call the allocation method of the superclass. */
3348 entry = bfd_hash_newfunc (entry, table, string);
3349 if (entry != NULL)
3350 {
3351 struct elf32_arm_stub_hash_entry *eh;
3352
3353 /* Initialize the local fields. */
3354 eh = (struct elf32_arm_stub_hash_entry *) entry;
3355 eh->stub_sec = NULL;
3356 eh->stub_offset = 0;
3357 eh->target_value = 0;
3358 eh->target_section = NULL;
cedfb179
DK		 3359 eh->target_addend = 0;
3360 eh->orig_insn = 0;
906e58ca 3361 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3362 eh->stub_size = 0;
3363 eh->stub_template = NULL;
3364 eh->stub_template_size = 0;
906e58ca
NC		 3365 eh->h = NULL;
3366 eh->id_sec = NULL;
d8d2f433 3367 eh->output_name = NULL;
906e58ca
NC		 3368 }
3369
3370 return entry;
3371}
3372
00a97672 3373/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3374 shortcuts to them in our hash table. */
3375
3376static bfd_boolean
57e8b36a 3377create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3378{
3379 struct elf32_arm_link_hash_table *htab;
3380
e5a52504 3381 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3382 if (htab == NULL)
3383 return FALSE;
3384
e5a52504
MM		 3385 /* BPABI objects never have a GOT, or associated sections. */
3386 if (htab->symbian_p)
3387 return TRUE;
3388
5e681ec4
PB		 3389 if (! _bfd_elf_create_got_section (dynobj, info))
3390 return FALSE;
3391
5e681ec4
PB		 3392 return TRUE;
3393}
3394
34e77a92
RS		 3395/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3396
3397static bfd_boolean
3398create_ifunc_sections (struct bfd_link_info *info)
3399{
3400 struct elf32_arm_link_hash_table *htab;
3401 const struct elf_backend_data *bed;
3402 bfd *dynobj;
3403 asection *s;
3404 flagword flags;
b38cadfb 3405
34e77a92
RS		 3406 htab = elf32_arm_hash_table (info);
3407 dynobj = htab->root.dynobj;
3408 bed = get_elf_backend_data (dynobj);
3409 flags = bed->dynamic_sec_flags;
3410
3411 if (htab->root.iplt == NULL)
3412 {
3d4d4302
AM		 3413 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3414 flags | SEC_READONLY | SEC_CODE);
34e77a92 3415 if (s == NULL
a0f49396 3416 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3417 return FALSE;
3418 htab->root.iplt = s;
3419 }
3420
3421 if (htab->root.irelplt == NULL)
3422 {
3d4d4302
AM		 3423 s = bfd_make_section_anyway_with_flags (dynobj,
3424 RELOC_SECTION (htab, ".iplt"),
3425 flags | SEC_READONLY);
34e77a92 3426 if (s == NULL
a0f49396 3427 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3428 return FALSE;
3429 htab->root.irelplt = s;
3430 }
3431
3432 if (htab->root.igotplt == NULL)
3433 {
3d4d4302 3434 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3435 if (s == NULL
3436 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3437 return FALSE;
3438 htab->root.igotplt = s;
3439 }
3440 return TRUE;
3441}
3442
eed94f8f
NC		 3443/* Determine if we're dealing with a Thumb only architecture. */
3444
3445static bfd_boolean
3446using_thumb_only (struct elf32_arm_link_hash_table *globals)
3447{
3448 int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3449 Tag_CPU_arch);
3450 int profile;
3451
3452 if (arch == TAG_CPU_ARCH_V6_M || arch == TAG_CPU_ARCH_V6S_M)
3453 return TRUE;
3454
3455 if (arch != TAG_CPU_ARCH_V7 && arch != TAG_CPU_ARCH_V7E_M)
3456 return FALSE;
3457
3458 profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3459 Tag_CPU_arch_profile);
3460
3461 return profile == 'M';
3462}
3463
3464/* Determine if we're dealing with a Thumb-2 object. */
3465
3466static bfd_boolean
3467using_thumb2 (struct elf32_arm_link_hash_table *globals)
3468{
3469 int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3470 Tag_CPU_arch);
3471 return arch == TAG_CPU_ARCH_V6T2 || arch >= TAG_CPU_ARCH_V7;
3472}
3473
00a97672
RS		 3474/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3475 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3476 hash table. */
3477
3478static bfd_boolean
57e8b36a 3479elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3480{
3481 struct elf32_arm_link_hash_table *htab;
3482
3483 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3484 if (htab == NULL)
3485 return FALSE;
3486
362d30a1 3487 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3488 return FALSE;
3489
3490 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3491 return FALSE;
3492
3d4d4302 3493 htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss");
0e1862bb 3494 if (!bfd_link_pic (info))
3d4d4302
AM		 3495 htab->srelbss = bfd_get_linker_section (dynobj,
3496 RELOC_SECTION (htab, ".bss"));
00a97672
RS		 3497
3498 if (htab->vxworks_p)
3499 {
3500 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3501 return FALSE;
3502
0e1862bb 3503 if (bfd_link_pic (info))
00a97672
RS		 3504 {
3505 htab->plt_header_size = 0;
3506 htab->plt_entry_size
3507 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3508 }
3509 else
3510 {
3511 htab->plt_header_size
3512 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3513 htab->plt_entry_size
3514 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3515 }
3516 }
eed94f8f
NC		 3517 else
3518 {
3519 /* PR ld/16017
3520 Test for thumb only architectures. Note - we cannot just call
3521 using_thumb_only() as the attributes in the output bfd have not been
3522 initialised at this point, so instead we use the input bfd. */
3523 bfd * saved_obfd = htab->obfd;
3524
3525 htab->obfd = dynobj;
3526 if (using_thumb_only (htab))
3527 {
3528 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3529 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3530 }
3531 htab->obfd = saved_obfd;
3532 }
5e681ec4 3533
362d30a1
RS		 3534 if (!htab->root.splt
3535 || !htab->root.srelplt
e5a52504 3536 || !htab->sdynbss
0e1862bb 3537 || (!bfd_link_pic (info) && !htab->srelbss))
5e681ec4
PB		 3538 abort ();
3539
3540 return TRUE;
3541}
3542
906e58ca
NC		 3543/* Copy the extra info we tack onto an elf_link_hash_entry. */
3544
3545static void
3546elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3547 struct elf_link_hash_entry *dir,
3548 struct elf_link_hash_entry *ind)
3549{
3550 struct elf32_arm_link_hash_entry *edir, *eind;
3551
3552 edir = (struct elf32_arm_link_hash_entry *) dir;
3553 eind = (struct elf32_arm_link_hash_entry *) ind;
3554
0bdcacaf 3555 if (eind->dyn_relocs != NULL)
906e58ca 3556 {
0bdcacaf 3557 if (edir->dyn_relocs != NULL)
906e58ca 3558 {
0bdcacaf
RS		 3559 struct elf_dyn_relocs **pp;
3560 struct elf_dyn_relocs *p;
906e58ca
NC		 3561
3562 /* Add reloc counts against the indirect sym to the direct sym
3563 list. Merge any entries against the same section. */
0bdcacaf 3564 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3565 {
0bdcacaf 3566 struct elf_dyn_relocs *q;
906e58ca 3567
0bdcacaf
RS		 3568 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3569 if (q->sec == p->sec)
906e58ca
NC		 3570 {
3571 q->pc_count += p->pc_count;
3572 q->count += p->count;
3573 *pp = p->next;
3574 break;
3575 }
3576 if (q == NULL)
3577 pp = &p->next;
3578 }
0bdcacaf 3579 *pp = edir->dyn_relocs;
906e58ca
NC		 3580 }
3581
0bdcacaf
RS		 3582 edir->dyn_relocs = eind->dyn_relocs;
3583 eind->dyn_relocs = NULL;
906e58ca
NC		 3584 }
3585
3586 if (ind->root.type == bfd_link_hash_indirect)
3587 {
3588 /* Copy over PLT info. */
34e77a92
RS		 3589 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3590 eind->plt.thumb_refcount = 0;
3591 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3592 eind->plt.maybe_thumb_refcount = 0;
3593 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3594 eind->plt.noncall_refcount = 0;
3595
3596 /* We should only allocate a function to .iplt once the final
3597 symbol information is known. */
3598 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3599
3600 if (dir->got.refcount <= 0)
3601 {
3602 edir->tls_type = eind->tls_type;
3603 eind->tls_type = GOT_UNKNOWN;
3604 }
3605 }
3606
3607 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3608}
3609
68faa637
AM		 3610/* Destroy an ARM elf linker hash table. */
3611
3612static void
d495ab0d 3613elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3614{
3615 struct elf32_arm_link_hash_table *ret
d495ab0d 3616 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3617
3618 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3619 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3620}
3621
906e58ca
NC		 3622/* Create an ARM elf linker hash table. */
3623
3624static struct bfd_link_hash_table *
3625elf32_arm_link_hash_table_create (bfd *abfd)
3626{
3627 struct elf32_arm_link_hash_table *ret;
3628 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3629
7bf52ea2 3630 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3631 if (ret == NULL)
3632 return NULL;
3633
3634 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3635 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3636 sizeof (struct elf32_arm_link_hash_entry),
3637 ARM_ELF_DATA))
906e58ca
NC		 3638 {
3639 free (ret);
3640 return NULL;
3641 }
3642
906e58ca 3643 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3644 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3645#ifdef FOUR_WORD_PLT
3646 ret->plt_header_size = 16;
3647 ret->plt_entry_size = 16;
3648#else
3649 ret->plt_header_size = 20;
1db37fe6 3650 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3651#endif
906e58ca 3652 ret->use_rel = 1;
906e58ca 3653 ret->obfd = abfd;
906e58ca
NC		 3654
3655 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3656 sizeof (struct elf32_arm_stub_hash_entry)))
3657 {
d495ab0d 3658 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3659 return NULL;
3660 }
d495ab0d 3661 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3662
3663 return &ret->root.root;
3664}
3665
cd1dac3d
DG		 3666/* Determine what kind of NOPs are available. */
3667
3668static bfd_boolean
3669arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3670{
3671 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3672 Tag_CPU_arch);
3673 return arch == TAG_CPU_ARCH_V6T2
3674 || arch == TAG_CPU_ARCH_V6K
9e3c6df6
PB		 3675 || arch == TAG_CPU_ARCH_V7
3676 || arch == TAG_CPU_ARCH_V7E_M;
cd1dac3d
DG		 3677}
3678
3679static bfd_boolean
3680arch_has_thumb2_nop (struct elf32_arm_link_hash_table *globals)
3681{
3682 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3683 Tag_CPU_arch);
9e3c6df6
PB		 3684 return (arch == TAG_CPU_ARCH_V6T2 || arch == TAG_CPU_ARCH_V7
3685 || arch == TAG_CPU_ARCH_V7E_M);
cd1dac3d
DG		 3686}
3687
f4ac8484
DJ		 3688static bfd_boolean
3689arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3690{
3691 switch (stub_type)
3692 {
fea2b4d6
CL		 3693 case arm_stub_long_branch_thumb_only:
3694 case arm_stub_long_branch_v4t_thumb_arm:
3695 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3696 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3697 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3698 case arm_stub_long_branch_thumb_only_pic:
f4ac8484
DJ		 3699 return TRUE;
3700 case arm_stub_none:
3701 BFD_FAIL ();
3702 return FALSE;
3703 break;
3704 default:
3705 return FALSE;
3706 }
3707}
3708
906e58ca
NC		 3709/* Determine the type of stub needed, if any, for a call. */
3710
3711static enum elf32_arm_stub_type
3712arm_type_of_stub (struct bfd_link_info *info,
3713 asection *input_sec,
3714 const Elf_Internal_Rela *rel,
34e77a92 3715 unsigned char st_type,
35fc36a8 3716 enum arm_st_branch_type *actual_branch_type,
906e58ca 3717 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3718 bfd_vma destination,
3719 asection *sym_sec,
3720 bfd *input_bfd,
3721 const char *name)
906e58ca
NC		 3722{
3723 bfd_vma location;
3724 bfd_signed_vma branch_offset;
3725 unsigned int r_type;
3726 struct elf32_arm_link_hash_table * globals;
3727 int thumb2;
3728 int thumb_only;
3729 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3730 int use_plt = 0;
35fc36a8 3731 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3732 union gotplt_union *root_plt;
3733 struct arm_plt_info *arm_plt;
906e58ca 3734
35fc36a8 3735 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3736 return stub_type;
3737
906e58ca 3738 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3739 if (globals == NULL)
3740 return stub_type;
906e58ca
NC		 3741
3742 thumb_only = using_thumb_only (globals);
3743
3744 thumb2 = using_thumb2 (globals);
3745
3746 /* Determine where the call point is. */
3747 location = (input_sec->output_offset
3748 + input_sec->output_section->vma
3749 + rel->r_offset);
3750
906e58ca
NC		 3751 r_type = ELF32_R_TYPE (rel->r_info);
3752
39f21624
NC		 3753 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3754 are considering a function call relocation. */
c5423981
TG		 3755 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
3756 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3757 && branch_type == ST_BRANCH_TO_ARM)
3758 branch_type = ST_BRANCH_TO_THUMB;
3759
34e77a92
RS		 3760 /* For TLS call relocs, it is the caller's responsibility to provide
3761 the address of the appropriate trampoline. */
3762 if (r_type != R_ARM_TLS_CALL
3763 && r_type != R_ARM_THM_TLS_CALL
3764 && elf32_arm_get_plt_info (input_bfd, hash, ELF32_R_SYM (rel->r_info),
3765 &root_plt, &arm_plt)
3766 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3767 {
34e77a92 3768 asection *splt;
fe33d2fa 3769
34e77a92
RS		 3770 if (hash == NULL || hash->is_iplt)
3771 splt = globals->root.iplt;
3772 else
3773 splt = globals->root.splt;
3774 if (splt != NULL)
b38cadfb 3775 {
34e77a92
RS		 3776 use_plt = 1;
3777
3778 /* Note when dealing with PLT entries: the main PLT stub is in
3779 ARM mode, so if the branch is in Thumb mode, another
3780 Thumb->ARM stub will be inserted later just before the ARM
3781 PLT stub. We don't take this extra distance into account
3782 here, because if a long branch stub is needed, we'll add a
3783 Thumb->Arm one and branch directly to the ARM PLT entry
3784 because it avoids spreading offset corrections in several
3785 places. */
3786
3787 destination = (splt->output_section->vma
3788 + splt->output_offset
3789 + root_plt->offset);
3790 st_type = STT_FUNC;
3791 branch_type = ST_BRANCH_TO_ARM;
3792 }
5fa9e92f 3793 }
34e77a92
RS		 3794 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3795 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 3796
fe33d2fa
CL		 3797 branch_offset = (bfd_signed_vma)(destination - location);
3798
0855e32b 3799 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 3800 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 3801 {
5fa9e92f
CL		 3802 /* Handle cases where:
3803 - this call goes too far (different Thumb/Thumb2 max
99059e56 3804 distance)
155d87d7 3805 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 3806 Thumb->Arm branch (not bl). A stub is needed in this case,
3807 but only if this call is not through a PLT entry. Indeed,
3808 PLT stubs handle mode switching already.
5fa9e92f 3809 */
906e58ca
NC		 3810 if ((!thumb2
3811 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
3812 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
3813 || (thumb2
3814 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
3815 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 3816 || (thumb2
3817 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
3818 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
3819 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 3820 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 3821 && (((r_type == R_ARM_THM_CALL
3822 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981
TG		 3823 || (r_type == R_ARM_THM_JUMP24)
3824 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 3825 && !use_plt))
906e58ca 3826 {
35fc36a8 3827 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 3828 {
3829 /* Thumb to thumb. */
3830 if (!thumb_only)
3831 {
0e1862bb 3832 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3833 /* PIC stubs. */
155d87d7 3834 ? ((globals->use_blx
9553db3c 3835 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 3836 /* V5T and above. Stub starts with ARM code, so
3837 we must be able to switch mode before
3838 reaching it, which is only possible for 'bl'
3839 (ie R_ARM_THM_CALL relocation). */
cf3eccff 3840 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 3841 /* On V4T, use Thumb code only. */
d3626fb0 3842 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 3843
3844 /* non-PIC stubs. */
155d87d7 3845 : ((globals->use_blx
9553db3c 3846 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 3847 /* V5T and above. */
3848 ? arm_stub_long_branch_any_any
3849 /* V4T. */
d3626fb0 3850 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 3851 }
3852 else
3853 {
0e1862bb 3854 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
ebe24dd4
CL		 3855 /* PIC stub. */
3856 ? arm_stub_long_branch_thumb_only_pic
c2b4a39d
CL		 3857 /* non-PIC stub. */
3858 : arm_stub_long_branch_thumb_only;
906e58ca
NC		 3859 }
3860 }
3861 else
3862 {
3863 /* Thumb to arm. */
c820be07
NC		 3864 if (sym_sec != NULL
3865 && sym_sec->owner != NULL
3866 && !INTERWORK_FLAG (sym_sec->owner))
3867 {
3868 (*_bfd_error_handler)
3869 (_("%B(%s): warning: interworking not enabled.\n"
3870 " first occurrence: %B: Thumb call to ARM"),
3871 sym_sec->owner, input_bfd, name);
3872 }
3873
0855e32b 3874 stub_type =
0e1862bb 3875 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3876 /* PIC stubs. */
0855e32b 3877 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 3878 /* TLS PIC stubs. */
0855e32b
NS		 3879 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
3880 : arm_stub_long_branch_v4t_thumb_tls_pic)
3881 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
3882 /* V5T PIC and above. */
3883 ? arm_stub_long_branch_any_arm_pic
3884 /* V4T PIC stub. */
3885 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 3886
3887 /* non-PIC stubs. */
0855e32b 3888 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 3889 /* V5T and above. */
3890 ? arm_stub_long_branch_any_any
3891 /* V4T. */
3892 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 3893
3894 /* Handle v4t short branches. */
fea2b4d6 3895 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 3896 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
3897 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 3898 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 3899 }
3900 }
3901 }
fe33d2fa
CL		 3902 else if (r_type == R_ARM_CALL
3903 || r_type == R_ARM_JUMP24
0855e32b
NS		 3904 || r_type == R_ARM_PLT32
3905 || r_type == R_ARM_TLS_CALL)
906e58ca 3906 {
35fc36a8 3907 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 3908 {
3909 /* Arm to thumb. */
c820be07
NC		 3910
3911 if (sym_sec != NULL
3912 && sym_sec->owner != NULL
3913 && !INTERWORK_FLAG (sym_sec->owner))
3914 {
3915 (*_bfd_error_handler)
3916 (_("%B(%s): warning: interworking not enabled.\n"
c2b4a39d 3917 " first occurrence: %B: ARM call to Thumb"),
c820be07
NC		 3918 sym_sec->owner, input_bfd, name);
3919 }
3920
3921 /* We have an extra 2-bytes reach because of
3922 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 3923 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
3924 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 3925 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 3926 || (r_type == R_ARM_JUMP24)
3927 || (r_type == R_ARM_PLT32))
906e58ca 3928 {
0e1862bb 3929 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3930 /* PIC stubs. */
ebe24dd4
CL		 3931 ? ((globals->use_blx)
3932 /* V5T and above. */
3933 ? arm_stub_long_branch_any_thumb_pic
3934 /* V4T stub. */
3935 : arm_stub_long_branch_v4t_arm_thumb_pic)
3936
c2b4a39d
CL		 3937 /* non-PIC stubs. */
3938 : ((globals->use_blx)
3939 /* V5T and above. */
3940 ? arm_stub_long_branch_any_any
3941 /* V4T. */
3942 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 3943 }
3944 }
3945 else
3946 {
3947 /* Arm to arm. */
3948 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
3949 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
3950 {
0855e32b 3951 stub_type =
0e1862bb 3952 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3953 /* PIC stubs. */
0855e32b 3954 ? (r_type == R_ARM_TLS_CALL
6a631e86 3955 /* TLS PIC Stub. */
0855e32b 3956 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 3957 : (globals->nacl_p
3958 ? arm_stub_long_branch_arm_nacl_pic
3959 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 3960 /* non-PIC stubs. */
7a89b94e
NC		 3961 : (globals->nacl_p
3962 ? arm_stub_long_branch_arm_nacl
3963 : arm_stub_long_branch_any_any);
906e58ca
NC		 3964 }
3965 }
3966 }
3967
fe33d2fa
CL		 3968 /* If a stub is needed, record the actual destination type. */
3969 if (stub_type != arm_stub_none)
35fc36a8 3970 *actual_branch_type = branch_type;
fe33d2fa 3971
906e58ca
NC		 3972 return stub_type;
3973}
3974
3975/* Build a name for an entry in the stub hash table. */
3976
3977static char *
3978elf32_arm_stub_name (const asection *input_section,
3979 const asection *sym_sec,
3980 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 3981 const Elf_Internal_Rela *rel,
3982 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 3983{
3984 char *stub_name;
3985 bfd_size_type len;
3986
3987 if (hash)
3988 {
fe33d2fa 3989 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 3990 stub_name = (char *) bfd_malloc (len);
906e58ca 3991 if (stub_name != NULL)
fe33d2fa 3992 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 3993 input_section->id & 0xffffffff,
3994 hash->root.root.root.string,
fe33d2fa
CL		 3995 (int) rel->r_addend & 0xffffffff,
3996 (int) stub_type);
906e58ca
NC		 3997 }
3998 else
3999 {
fe33d2fa 4000 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4001 stub_name = (char *) bfd_malloc (len);
906e58ca 4002 if (stub_name != NULL)
fe33d2fa 4003 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4004 input_section->id & 0xffffffff,
4005 sym_sec->id & 0xffffffff,
0855e32b
NS		 4006 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4007 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4008 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4009 (int) rel->r_addend & 0xffffffff,
4010 (int) stub_type);
906e58ca
NC		 4011 }
4012
4013 return stub_name;
4014}
4015
4016/* Look up an entry in the stub hash. Stub entries are cached because
4017 creating the stub name takes a bit of time. */
4018
4019static struct elf32_arm_stub_hash_entry *
4020elf32_arm_get_stub_entry (const asection *input_section,
4021 const asection *sym_sec,
4022 struct elf_link_hash_entry *hash,
4023 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4024 struct elf32_arm_link_hash_table *htab,
4025 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4026{
4027 struct elf32_arm_stub_hash_entry *stub_entry;
4028 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4029 const asection *id_sec;
4030
4031 if ((input_section->flags & SEC_CODE) == 0)
4032 return NULL;
4033
4034 /* If this input section is part of a group of sections sharing one
4035 stub section, then use the id of the first section in the group.
4036 Stub names need to include a section id, as there may well be
4037 more than one stub used to reach say, printf, and we need to
4038 distinguish between them. */
4039 id_sec = htab->stub_group[input_section->id].link_sec;
4040
4041 if (h != NULL && h->stub_cache != NULL
4042 && h->stub_cache->h == h
fe33d2fa
CL		 4043 && h->stub_cache->id_sec == id_sec
4044 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4045 {
4046 stub_entry = h->stub_cache;
4047 }
4048 else
4049 {
4050 char *stub_name;
4051
fe33d2fa 4052 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4053 if (stub_name == NULL)
4054 return NULL;
4055
4056 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4057 stub_name, FALSE, FALSE);
4058 if (h != NULL)
4059 h->stub_cache = stub_entry;
4060
4061 free (stub_name);
4062 }
4063
4064 return stub_entry;
4065}
4066
48229727 4067/* Find or create a stub section. Returns a pointer to the stub section, and
b38cadfb 4068 the section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4069 LINK_SEC_P may be NULL. */
906e58ca 4070
48229727
JB		 4071static asection *
4072elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
4073 struct elf32_arm_link_hash_table *htab)
906e58ca
NC		 4074{
4075 asection *link_sec;
4076 asection *stub_sec;
906e58ca
NC		 4077
4078 link_sec = htab->stub_group[section->id].link_sec;
9553db3c 4079 BFD_ASSERT (link_sec != NULL);
906e58ca 4080 stub_sec = htab->stub_group[section->id].stub_sec;
9553db3c 4081
906e58ca
NC		 4082 if (stub_sec == NULL)
4083 {
4084 stub_sec = htab->stub_group[link_sec->id].stub_sec;
4085 if (stub_sec == NULL)
4086 {
4087 size_t namelen;
4088 bfd_size_type len;
4089 char *s_name;
4090
4091 namelen = strlen (link_sec->name);
4092 len = namelen + sizeof (STUB_SUFFIX);
21d799b5 4093 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
906e58ca
NC		 4094 if (s_name == NULL)
4095 return NULL;
4096
4097 memcpy (s_name, link_sec->name, namelen);
4098 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
7a89b94e
NC		 4099 stub_sec = (*htab->add_stub_section) (s_name, link_sec,
4100 htab->nacl_p ? 4 : 3);
906e58ca
NC		 4101 if (stub_sec == NULL)
4102 return NULL;
4103 htab->stub_group[link_sec->id].stub_sec = stub_sec;
4104 }
4105 htab->stub_group[section->id].stub_sec = stub_sec;
4106 }
b38cadfb 4107
48229727
JB		 4108 if (link_sec_p)
4109 *link_sec_p = link_sec;
b38cadfb 4110
48229727
JB		 4111 return stub_sec;
4112}
4113
4114/* Add a new stub entry to the stub hash. Not all fields of the new
4115 stub entry are initialised. */
4116
4117static struct elf32_arm_stub_hash_entry *
4118elf32_arm_add_stub (const char *stub_name,
4119 asection *section,
4120 struct elf32_arm_link_hash_table *htab)
4121{
4122 asection *link_sec;
4123 asection *stub_sec;
4124 struct elf32_arm_stub_hash_entry *stub_entry;
4125
4126 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab);
4127 if (stub_sec == NULL)
4128 return NULL;
906e58ca
NC		 4129
4130 /* Enter this entry into the linker stub hash table. */
4131 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4132 TRUE, FALSE);
4133 if (stub_entry == NULL)
4134 {
4135 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
4136 section->owner,
4137 stub_name);
4138 return NULL;
4139 }
4140
4141 stub_entry->stub_sec = stub_sec;
4142 stub_entry->stub_offset = 0;
4143 stub_entry->id_sec = link_sec;
4144
906e58ca
NC		 4145 return stub_entry;
4146}
4147
4148/* Store an Arm insn into an output section not processed by
4149 elf32_arm_write_section. */
4150
4151static void
8029a119
NC		 4152put_arm_insn (struct elf32_arm_link_hash_table * htab,
4153 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4154{
4155 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4156 bfd_putl32 (val, ptr);
4157 else
4158 bfd_putb32 (val, ptr);
4159}
4160
4161/* Store a 16-bit Thumb insn into an output section not processed by
4162 elf32_arm_write_section. */
4163
4164static void
8029a119
NC		 4165put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4166 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4167{
4168 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4169 bfd_putl16 (val, ptr);
4170 else
4171 bfd_putb16 (val, ptr);
4172}
4173
a504d23a
LA		 4174/* Store a Thumb2 insn into an output section not processed by
4175 elf32_arm_write_section. */
4176
4177static void
4178put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
4179 bfd * output_bfd, bfd_vma val, void * ptr)
4180{
4181 /* T2 instructions are 16-bit streamed. */
4182 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4183 {
4184 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4185 bfd_putl16 ((val & 0xffff), ptr + 2);
4186 }
4187 else
4188 {
4189 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4190 bfd_putb16 ((val & 0xffff), ptr + 2);
4191 }
4192}
4193
0855e32b
NS		 4194/* If it's possible to change R_TYPE to a more efficient access
4195 model, return the new reloc type. */
4196
4197static unsigned
b38cadfb 4198elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4199 struct elf_link_hash_entry *h)
4200{
4201 int is_local = (h == NULL);
4202
0e1862bb
L		 4203 if (bfd_link_pic (info)
4204 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4205 return r_type;
4206
b38cadfb 4207 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4208 switch (r_type)
4209 {
4210 case R_ARM_TLS_GOTDESC:
4211 case R_ARM_TLS_CALL:
4212 case R_ARM_THM_TLS_CALL:
4213 case R_ARM_TLS_DESCSEQ:
4214 case R_ARM_THM_TLS_DESCSEQ:
4215 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4216 }
4217
4218 return r_type;
4219}
4220
48229727
JB		 4221static bfd_reloc_status_type elf32_arm_final_link_relocate
4222 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4223 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4224 const char *, unsigned char, enum arm_st_branch_type,
4225 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4226
4563a860
JB		 4227static unsigned int
4228arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4229{
4230 switch (stub_type)
4231 {
4232 case arm_stub_a8_veneer_b_cond:
4233 case arm_stub_a8_veneer_b:
4234 case arm_stub_a8_veneer_bl:
4235 return 2;
4236
4237 case arm_stub_long_branch_any_any:
4238 case arm_stub_long_branch_v4t_arm_thumb:
4239 case arm_stub_long_branch_thumb_only:
4240 case arm_stub_long_branch_v4t_thumb_thumb:
4241 case arm_stub_long_branch_v4t_thumb_arm:
4242 case arm_stub_short_branch_v4t_thumb_arm:
4243 case arm_stub_long_branch_any_arm_pic:
4244 case arm_stub_long_branch_any_thumb_pic:
4245 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4246 case arm_stub_long_branch_v4t_arm_thumb_pic:
4247 case arm_stub_long_branch_v4t_thumb_arm_pic:
4248 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4249 case arm_stub_long_branch_any_tls_pic:
4250 case arm_stub_long_branch_v4t_thumb_tls_pic:
4563a860
JB		 4251 case arm_stub_a8_veneer_blx:
4252 return 4;
b38cadfb 4253
7a89b94e
NC		 4254 case arm_stub_long_branch_arm_nacl:
4255 case arm_stub_long_branch_arm_nacl_pic:
4256 return 16;
4257
4563a860
JB		 4258 default:
4259 abort (); /* Should be unreachable. */
4260 }
4261}
4262
906e58ca
NC		 4263static bfd_boolean
4264arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4265 void * in_arg)
4266{
7a89b94e 4267#define MAXRELOCS 3
906e58ca 4268 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4269 struct elf32_arm_link_hash_table *globals;
906e58ca 4270 struct bfd_link_info *info;
906e58ca
NC		 4271 asection *stub_sec;
4272 bfd *stub_bfd;
906e58ca
NC		 4273 bfd_byte *loc;
4274 bfd_vma sym_value;
4275 int template_size;
4276 int size;
d3ce72d0 4277 const insn_sequence *template_sequence;
906e58ca 4278 int i;
48229727
JB		 4279 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4280 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4281 int nrelocs = 0;
906e58ca
NC		 4282
4283 /* Massage our args to the form they really have. */
4284 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4285 info = (struct bfd_link_info *) in_arg;
4286
4287 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4288 if (globals == NULL)
4289 return FALSE;
906e58ca 4290
906e58ca
NC		 4291 stub_sec = stub_entry->stub_sec;
4292
4dfe6ac6 4293 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4294 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4295 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4296 return TRUE;
fe33d2fa 4297
906e58ca
NC		 4298 /* Make a note of the offset within the stubs for this entry. */
4299 stub_entry->stub_offset = stub_sec->size;
4300 loc = stub_sec->contents + stub_entry->stub_offset;
4301
4302 stub_bfd = stub_sec->owner;
4303
906e58ca
NC		 4304 /* This is the address of the stub destination. */
4305 sym_value = (stub_entry->target_value
4306 + stub_entry->target_section->output_offset
4307 + stub_entry->target_section->output_section->vma);
4308
d3ce72d0 4309 template_sequence = stub_entry->stub_template;
461a49ca 4310 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4311
4312 size = 0;
461a49ca 4313 for (i = 0; i < template_size; i++)
906e58ca 4314 {
d3ce72d0 4315 switch (template_sequence[i].type)
461a49ca
DJ		 4316 {
4317 case THUMB16_TYPE:
48229727 4318 {
d3ce72d0
NC		 4319 bfd_vma data = (bfd_vma) template_sequence[i].data;
4320 if (template_sequence[i].reloc_addend != 0)
48229727 4321 {
99059e56
RM		 4322 /* We've borrowed the reloc_addend field to mean we should
4323 insert a condition code into this (Thumb-1 branch)
4324 instruction. See THUMB16_BCOND_INSN. */
4325 BFD_ASSERT ((data & 0xff00) == 0xd000);
4326 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4327 }
fe33d2fa 4328 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4329 size += 2;
4330 }
461a49ca 4331 break;
906e58ca 4332
48229727 4333 case THUMB32_TYPE:
fe33d2fa
CL		 4334 bfd_put_16 (stub_bfd,
4335 (template_sequence[i].data >> 16) & 0xffff,
4336 loc + size);
4337 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4338 loc + size + 2);
99059e56
RM		 4339 if (template_sequence[i].r_type != R_ARM_NONE)
4340 {
4341 stub_reloc_idx[nrelocs] = i;
4342 stub_reloc_offset[nrelocs++] = size;
4343 }
4344 size += 4;
4345 break;
48229727 4346
461a49ca 4347 case ARM_TYPE:
fe33d2fa
CL		 4348 bfd_put_32 (stub_bfd, template_sequence[i].data,
4349 loc + size);
461a49ca
DJ		 4350 /* Handle cases where the target is encoded within the
4351 instruction. */
d3ce72d0 4352 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4353 {
48229727
JB		 4354 stub_reloc_idx[nrelocs] = i;
4355 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4356 }
4357 size += 4;
4358 break;
4359
4360 case DATA_TYPE:
d3ce72d0 4361 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4362 stub_reloc_idx[nrelocs] = i;
4363 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4364 size += 4;
4365 break;
4366
4367 default:
4368 BFD_FAIL ();
4369 return FALSE;
4370 }
906e58ca 4371 }
461a49ca 4372
906e58ca
NC		 4373 stub_sec->size += size;
4374
461a49ca
DJ		 4375 /* Stub size has already been computed in arm_size_one_stub. Check
4376 consistency. */
4377 BFD_ASSERT (size == stub_entry->stub_size);
4378
906e58ca 4379 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4380 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4381 sym_value |= 1;
4382
48229727
JB		 4383 /* Assume there is at least one and at most MAXRELOCS entries to relocate
4384 in each stub. */
4385 BFD_ASSERT (nrelocs != 0 && nrelocs <= MAXRELOCS);
c820be07 4386
48229727 4387 for (i = 0; i < nrelocs; i++)
d3ce72d0
NC		 4388 if (template_sequence[stub_reloc_idx[i]].r_type == R_ARM_THM_JUMP24
4389 || template_sequence[stub_reloc_idx[i]].r_type == R_ARM_THM_JUMP19
4390 || template_sequence[stub_reloc_idx[i]].r_type == R_ARM_THM_CALL
4391 || template_sequence[stub_reloc_idx[i]].r_type == R_ARM_THM_XPC22)
48229727
JB		 4392 {
4393 Elf_Internal_Rela rel;
4394 bfd_boolean unresolved_reloc;
4395 char *error_message;
35fc36a8
RS		 4396 enum arm_st_branch_type branch_type
4397 = (template_sequence[stub_reloc_idx[i]].r_type != R_ARM_THM_XPC22
4398 ? ST_BRANCH_TO_THUMB : ST_BRANCH_TO_ARM);
48229727
JB		 4399 bfd_vma points_to = sym_value + stub_entry->target_addend;
4400
4401 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
d3ce72d0 4402 rel.r_info = ELF32_R_INFO (0,
99059e56 4403 template_sequence[stub_reloc_idx[i]].r_type);
d3ce72d0 4404 rel.r_addend = template_sequence[stub_reloc_idx[i]].reloc_addend;
48229727
JB		 4405
4406 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4407 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4408 template should refer back to the instruction after the original
4409 branch. */
4410 points_to = sym_value;
4411
33c6a8fc
JB		 4412 /* There may be unintended consequences if this is not true. */
4413 BFD_ASSERT (stub_entry->h == NULL);
4414
48229727
JB		 4415 /* Note: _bfd_final_link_relocate doesn't handle these relocations
4416 properly. We should probably use this function unconditionally,
4417 rather than only for certain relocations listed in the enclosing
4418 conditional, for the sake of consistency. */
4419 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
d3ce72d0 4420 (template_sequence[stub_reloc_idx[i]].r_type),
48229727 4421 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
34e77a92
RS		 4422 points_to, info, stub_entry->target_section, "", STT_FUNC,
4423 branch_type, (struct elf_link_hash_entry *) stub_entry->h,
4424 &unresolved_reloc, &error_message);
48229727
JB		 4425 }
4426 else
4427 {
fe33d2fa
CL		 4428 Elf_Internal_Rela rel;
4429 bfd_boolean unresolved_reloc;
4430 char *error_message;
4431 bfd_vma points_to = sym_value + stub_entry->target_addend
4432 + template_sequence[stub_reloc_idx[i]].reloc_addend;
4433
4434 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4435 rel.r_info = ELF32_R_INFO (0,
99059e56 4436 template_sequence[stub_reloc_idx[i]].r_type);
fe33d2fa
CL		 4437 rel.r_addend = 0;
4438
4439 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4440 (template_sequence[stub_reloc_idx[i]].r_type),
4441 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
34e77a92 4442 points_to, info, stub_entry->target_section, "", STT_FUNC,
35fc36a8 4443 stub_entry->branch_type,
fe33d2fa
CL		 4444 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4445 &error_message);
48229727 4446 }
906e58ca
NC		 4447
4448 return TRUE;
48229727 4449#undef MAXRELOCS
906e58ca
NC		 4450}
4451
48229727
JB		 4452/* Calculate the template, template size and instruction size for a stub.
4453 Return value is the instruction size. */
906e58ca 4454
48229727
JB		 4455static unsigned int
4456find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4457 const insn_sequence **stub_template,
4458 int *stub_template_size)
906e58ca 4459{
d3ce72d0 4460 const insn_sequence *template_sequence = NULL;
48229727
JB		 4461 int template_size = 0, i;
4462 unsigned int size;
906e58ca 4463
d3ce72d0 4464 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4465 if (stub_template)
4466 *stub_template = template_sequence;
4467
48229727 4468 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4469 if (stub_template_size)
4470 *stub_template_size = template_size;
906e58ca
NC		 4471
4472 size = 0;
461a49ca
DJ		 4473 for (i = 0; i < template_size; i++)
4474 {
d3ce72d0 4475 switch (template_sequence[i].type)
461a49ca
DJ		 4476 {
4477 case THUMB16_TYPE:
4478 size += 2;
4479 break;
4480
4481 case ARM_TYPE:
48229727 4482 case THUMB32_TYPE:
461a49ca
DJ		 4483 case DATA_TYPE:
4484 size += 4;
4485 break;
4486
4487 default:
4488 BFD_FAIL ();
2a229407 4489 return 0;
461a49ca
DJ		 4490 }
4491 }
4492
48229727
JB		 4493 return size;
4494}
4495
4496/* As above, but don't actually build the stub. Just bump offset so
4497 we know stub section sizes. */
4498
4499static bfd_boolean
4500arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4501 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4502{
4503 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4504 const insn_sequence *template_sequence;
48229727
JB		 4505 int template_size, size;
4506
4507 /* Massage our args to the form they really have. */
4508 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4509
4510 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4511 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4512
d3ce72d0 4513 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4514 &template_size);
4515
461a49ca 4516 stub_entry->stub_size = size;
d3ce72d0 4517 stub_entry->stub_template = template_sequence;
461a49ca
DJ		 4518 stub_entry->stub_template_size = template_size;
4519
906e58ca
NC		 4520 size = (size + 7) & ~7;
4521 stub_entry->stub_sec->size += size;
461a49ca 4522
906e58ca
NC		 4523 return TRUE;
4524}
4525
4526/* External entry points for sizing and building linker stubs. */
4527
4528/* Set up various things so that we can make a list of input sections
4529 for each output section included in the link. Returns -1 on error,
4530 0 when no stubs will be needed, and 1 on success. */
4531
4532int
4533elf32_arm_setup_section_lists (bfd *output_bfd,
4534 struct bfd_link_info *info)
4535{
4536 bfd *input_bfd;
4537 unsigned int bfd_count;
7292b3ac 4538 unsigned int top_id, top_index;
906e58ca
NC		 4539 asection *section;
4540 asection **input_list, **list;
4541 bfd_size_type amt;
4542 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4543
4dfe6ac6
NC		 4544 if (htab == NULL)
4545 return 0;
906e58ca
NC		 4546 if (! is_elf_hash_table (htab))
4547 return 0;
4548
4549 /* Count the number of input BFDs and find the top input section id. */
4550 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
4551 input_bfd != NULL;
c72f2fb2 4552 input_bfd = input_bfd->link.next)
906e58ca
NC		 4553 {
4554 bfd_count += 1;
4555 for (section = input_bfd->sections;
4556 section != NULL;
4557 section = section->next)
4558 {
4559 if (top_id < section->id)
4560 top_id = section->id;
4561 }
4562 }
4563 htab->bfd_count = bfd_count;
4564
4565 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 4566 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 4567 if (htab->stub_group == NULL)
4568 return -1;
fe33d2fa 4569 htab->top_id = top_id;
906e58ca
NC		 4570
4571 /* We can't use output_bfd->section_count here to find the top output
4572 section index as some sections may have been removed, and
4573 _bfd_strip_section_from_output doesn't renumber the indices. */
4574 for (section = output_bfd->sections, top_index = 0;
4575 section != NULL;
4576 section = section->next)
4577 {
4578 if (top_index < section->index)
4579 top_index = section->index;
4580 }
4581
4582 htab->top_index = top_index;
4583 amt = sizeof (asection *) * (top_index + 1);
21d799b5 4584 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 4585 htab->input_list = input_list;
4586 if (input_list == NULL)
4587 return -1;
4588
4589 /* For sections we aren't interested in, mark their entries with a
4590 value we can check later. */
4591 list = input_list + top_index;
4592 do
4593 *list = bfd_abs_section_ptr;
4594 while (list-- != input_list);
4595
4596 for (section = output_bfd->sections;
4597 section != NULL;
4598 section = section->next)
4599 {
4600 if ((section->flags & SEC_CODE) != 0)
4601 input_list[section->index] = NULL;
4602 }
4603
4604 return 1;
4605}
4606
4607/* The linker repeatedly calls this function for each input section,
4608 in the order that input sections are linked into output sections.
4609 Build lists of input sections to determine groupings between which
4610 we may insert linker stubs. */
4611
4612void
4613elf32_arm_next_input_section (struct bfd_link_info *info,
4614 asection *isec)
4615{
4616 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4617
4dfe6ac6
NC		 4618 if (htab == NULL)
4619 return;
4620
906e58ca
NC		 4621 if (isec->output_section->index <= htab->top_index)
4622 {
4623 asection **list = htab->input_list + isec->output_section->index;
4624
a7470592 4625 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 4626 {
4627 /* Steal the link_sec pointer for our list. */
4628#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
4629 /* This happens to make the list in reverse order,
07d72278 4630 which we reverse later. */
906e58ca
NC		 4631 PREV_SEC (isec) = *list;
4632 *list = isec;
4633 }
4634 }
4635}
4636
4637/* See whether we can group stub sections together. Grouping stub
4638 sections may result in fewer stubs. More importantly, we need to
07d72278 4639 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 4640 .fini output sections respectively, because glibc splits the
4641 _init and _fini functions into multiple parts. Putting a stub in
4642 the middle of a function is not a good idea. */
4643
4644static void
4645group_sections (struct elf32_arm_link_hash_table *htab,
4646 bfd_size_type stub_group_size,
07d72278 4647 bfd_boolean stubs_always_after_branch)
906e58ca 4648{
07d72278 4649 asection **list = htab->input_list;
906e58ca
NC		 4650
4651 do
4652 {
4653 asection *tail = *list;
07d72278 4654 asection *head;
906e58ca
NC		 4655
4656 if (tail == bfd_abs_section_ptr)
4657 continue;
4658
07d72278
DJ		 4659 /* Reverse the list: we must avoid placing stubs at the
4660 beginning of the section because the beginning of the text
4661 section may be required for an interrupt vector in bare metal
4662 code. */
4663#define NEXT_SEC PREV_SEC
e780aef2
CL		 4664 head = NULL;
4665 while (tail != NULL)
99059e56
RM		 4666 {
4667 /* Pop from tail. */
4668 asection *item = tail;
4669 tail = PREV_SEC (item);
e780aef2 4670
99059e56
RM		 4671 /* Push on head. */
4672 NEXT_SEC (item) = head;
4673 head = item;
4674 }
07d72278
DJ		 4675
4676 while (head != NULL)
906e58ca
NC		 4677 {
4678 asection *curr;
07d72278 4679 asection *next;
e780aef2
CL		 4680 bfd_vma stub_group_start = head->output_offset;
4681 bfd_vma end_of_next;
906e58ca 4682
07d72278 4683 curr = head;
e780aef2 4684 while (NEXT_SEC (curr) != NULL)
8cd931b7 4685 {
e780aef2
CL		 4686 next = NEXT_SEC (curr);
4687 end_of_next = next->output_offset + next->size;
4688 if (end_of_next - stub_group_start >= stub_group_size)
4689 /* End of NEXT is too far from start, so stop. */
8cd931b7 4690 break;
e780aef2
CL		 4691 /* Add NEXT to the group. */
4692 curr = next;
8cd931b7 4693 }
906e58ca 4694
07d72278 4695 /* OK, the size from the start to the start of CURR is less
906e58ca 4696 than stub_group_size and thus can be handled by one stub
07d72278 4697 section. (Or the head section is itself larger than
906e58ca
NC		 4698 stub_group_size, in which case we may be toast.)
4699 We should really be keeping track of the total size of
4700 stubs added here, as stubs contribute to the final output
7fb9f789 4701 section size. */
906e58ca
NC		 4702 do
4703 {
07d72278 4704 next = NEXT_SEC (head);
906e58ca 4705 /* Set up this stub group. */
07d72278 4706 htab->stub_group[head->id].link_sec = curr;
906e58ca 4707 }
07d72278 4708 while (head != curr && (head = next) != NULL);
906e58ca
NC		 4709
4710 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 4711 bytes after the stub section can be handled by it too. */
4712 if (!stubs_always_after_branch)
906e58ca 4713 {
e780aef2
CL		 4714 stub_group_start = curr->output_offset + curr->size;
4715
8cd931b7 4716 while (next != NULL)
906e58ca 4717 {
e780aef2
CL		 4718 end_of_next = next->output_offset + next->size;
4719 if (end_of_next - stub_group_start >= stub_group_size)
4720 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 4721 break;
e780aef2 4722 /* Add NEXT to the stub group. */
07d72278
DJ		 4723 head = next;
4724 next = NEXT_SEC (head);
4725 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 4726 }
4727 }
07d72278 4728 head = next;
906e58ca
NC		 4729 }
4730 }
07d72278 4731 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 4732
4733 free (htab->input_list);
4734#undef PREV_SEC
07d72278 4735#undef NEXT_SEC
906e58ca
NC		 4736}
4737
48229727
JB		 4738/* Comparison function for sorting/searching relocations relating to Cortex-A8
4739 erratum fix. */
4740
4741static int
4742a8_reloc_compare (const void *a, const void *b)
4743{
21d799b5
NC		 4744 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
4745 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 4746
4747 if (ra->from < rb->from)
4748 return -1;
4749 else if (ra->from > rb->from)
4750 return 1;
4751 else
4752 return 0;
4753}
4754
4755static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
4756 const char *, char **);
4757
4758/* Helper function to scan code for sequences which might trigger the Cortex-A8
4759 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 4760 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 4761 otherwise. */
4762
81694485
NC		 4763static bfd_boolean
4764cortex_a8_erratum_scan (bfd *input_bfd,
4765 struct bfd_link_info *info,
48229727
JB		 4766 struct a8_erratum_fix **a8_fixes_p,
4767 unsigned int *num_a8_fixes_p,
4768 unsigned int *a8_fix_table_size_p,
4769 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 4770 unsigned int num_a8_relocs,
4771 unsigned prev_num_a8_fixes,
4772 bfd_boolean *stub_changed_p)
48229727
JB		 4773{
4774 asection *section;
4775 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4776 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
4777 unsigned int num_a8_fixes = *num_a8_fixes_p;
4778 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
4779
4dfe6ac6
NC		 4780 if (htab == NULL)
4781 return FALSE;
4782
48229727
JB		 4783 for (section = input_bfd->sections;
4784 section != NULL;
4785 section = section->next)
4786 {
4787 bfd_byte *contents = NULL;
4788 struct _arm_elf_section_data *sec_data;
4789 unsigned int span;
4790 bfd_vma base_vma;
4791
4792 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 4793 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
4794 || (section->flags & SEC_EXCLUDE) != 0
4795 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
4796 || (section->output_section == bfd_abs_section_ptr))
4797 continue;
48229727
JB		 4798
4799 base_vma = section->output_section->vma + section->output_offset;
4800
4801 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 4802 contents = elf_section_data (section)->this_hdr.contents;
48229727 4803 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 4804 return TRUE;
48229727
JB		 4805
4806 sec_data = elf32_arm_section_data (section);
4807
4808 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 4809 {
4810 unsigned int span_start = sec_data->map[span].vma;
4811 unsigned int span_end = (span == sec_data->mapcount - 1)
4812 ? section->size : sec_data->map[span + 1].vma;
4813 unsigned int i;
4814 char span_type = sec_data->map[span].type;
4815 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
4816
4817 if (span_type != 't')
4818 continue;
4819
4820 /* Span is entirely within a single 4KB region: skip scanning. */
4821 if (((base_vma + span_start) & ~0xfff)
48229727 4822 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 4823 continue;
4824
4825 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
4826
4827 * The opcode is BLX.W, BL.W, B.W, Bcc.W
4828 * The branch target is in the same 4KB region as the
4829 first half of the branch.
4830 * The instruction before the branch is a 32-bit
4831 length non-branch instruction. */
4832 for (i = span_start; i < span_end;)
4833 {
4834 unsigned int insn = bfd_getl16 (&contents[i]);
4835 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 4836 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
4837
99059e56
RM		 4838 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
4839 insn_32bit = TRUE;
48229727
JB		 4840
4841 if (insn_32bit)
99059e56
RM		 4842 {
4843 /* Load the rest of the insn (in manual-friendly order). */
4844 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
4845
4846 /* Encoding T4: B<c>.W. */
4847 is_b = (insn & 0xf800d000) == 0xf0009000;
4848 /* Encoding T1: BL<c>.W. */
4849 is_bl = (insn & 0xf800d000) == 0xf000d000;
4850 /* Encoding T2: BLX<c>.W. */
4851 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 4852 /* Encoding T3: B<c>.W (not permitted in IT block). */
4853 is_bcc = (insn & 0xf800d000) == 0xf0008000
4854 && (insn & 0x07f00000) != 0x03800000;
4855 }
4856
4857 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 4858
99059e56 4859 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 4860 && insn_32bit
4861 && is_32bit_branch
4862 && last_was_32bit
4863 && ! last_was_branch)
99059e56
RM		 4864 {
4865 bfd_signed_vma offset = 0;
4866 bfd_boolean force_target_arm = FALSE;
48229727 4867 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 4868 bfd_vma target;
4869 enum elf32_arm_stub_type stub_type = arm_stub_none;
4870 struct a8_erratum_reloc key, *found;
4871 bfd_boolean use_plt = FALSE;
48229727 4872
99059e56
RM		 4873 key.from = base_vma + i;
4874 found = (struct a8_erratum_reloc *)
4875 bsearch (&key, a8_relocs, num_a8_relocs,
4876 sizeof (struct a8_erratum_reloc),
4877 &a8_reloc_compare);
48229727
JB		 4878
4879 if (found)
4880 {
4881 char *error_message = NULL;
4882 struct elf_link_hash_entry *entry;
4883
4884 /* We don't care about the error returned from this
99059e56 4885 function, only if there is glue or not. */
48229727
JB		 4886 entry = find_thumb_glue (info, found->sym_name,
4887 &error_message);
4888
4889 if (entry)
4890 found->non_a8_stub = TRUE;
4891
92750f34 4892 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 4893 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 4894 && found->hash->root.plt.offset != (bfd_vma) -1)
4895 use_plt = TRUE;
4896
4897 if (found->r_type == R_ARM_THM_CALL)
4898 {
35fc36a8
RS		 4899 if (found->branch_type == ST_BRANCH_TO_ARM
4900 || use_plt)
92750f34
DJ		 4901 force_target_arm = TRUE;
4902 else
4903 force_target_thumb = TRUE;
4904 }
48229727
JB		 4905 }
4906
99059e56 4907 /* Check if we have an offending branch instruction. */
48229727
JB		 4908
4909 if (found && found->non_a8_stub)
4910 /* We've already made a stub for this instruction, e.g.
4911 it's a long branch or a Thumb->ARM stub. Assume that
4912 stub will suffice to work around the A8 erratum (see
4913 setting of always_after_branch above). */
4914 ;
99059e56
RM		 4915 else if (is_bcc)
4916 {
4917 offset = (insn & 0x7ff) << 1;
4918 offset |= (insn & 0x3f0000) >> 4;
4919 offset |= (insn & 0x2000) ? 0x40000 : 0;
4920 offset |= (insn & 0x800) ? 0x80000 : 0;
4921 offset |= (insn & 0x4000000) ? 0x100000 : 0;
4922 if (offset & 0x100000)
4923 offset |= ~ ((bfd_signed_vma) 0xfffff);
4924 stub_type = arm_stub_a8_veneer_b_cond;
4925 }
4926 else if (is_b || is_bl || is_blx)
4927 {
4928 int s = (insn & 0x4000000) != 0;
4929 int j1 = (insn & 0x2000) != 0;
4930 int j2 = (insn & 0x800) != 0;
4931 int i1 = !(j1 ^ s);
4932 int i2 = !(j2 ^ s);
4933
4934 offset = (insn & 0x7ff) << 1;
4935 offset |= (insn & 0x3ff0000) >> 4;
4936 offset |= i2 << 22;
4937 offset |= i1 << 23;
4938 offset |= s << 24;
4939 if (offset & 0x1000000)
4940 offset |= ~ ((bfd_signed_vma) 0xffffff);
4941
4942 if (is_blx)
4943 offset &= ~ ((bfd_signed_vma) 3);
4944
4945 stub_type = is_blx ? arm_stub_a8_veneer_blx :
4946 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
4947 }
4948
4949 if (stub_type != arm_stub_none)
4950 {
4951 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 4952
4953 /* The original instruction is a BL, but the target is
99059e56 4954 an ARM instruction. If we were not making a stub,
48229727
JB		 4955 the BL would have been converted to a BLX. Use the
4956 BLX stub instead in that case. */
4957 if (htab->use_blx && force_target_arm
4958 && stub_type == arm_stub_a8_veneer_bl)
4959 {
4960 stub_type = arm_stub_a8_veneer_blx;
4961 is_blx = TRUE;
4962 is_bl = FALSE;
4963 }
4964 /* Conversely, if the original instruction was
4965 BLX but the target is Thumb mode, use the BL
4966 stub. */
4967 else if (force_target_thumb
4968 && stub_type == arm_stub_a8_veneer_blx)
4969 {
4970 stub_type = arm_stub_a8_veneer_bl;
4971 is_blx = FALSE;
4972 is_bl = TRUE;
4973 }
4974
99059e56
RM		 4975 if (is_blx)
4976 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 4977
99059e56
RM		 4978 /* If we found a relocation, use the proper destination,
4979 not the offset in the (unrelocated) instruction.
48229727
JB		 4980 Note this is always done if we switched the stub type
4981 above. */
99059e56
RM		 4982 if (found)
4983 offset =
81694485 4984 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 4985
99059e56
RM		 4986 /* If the stub will use a Thumb-mode branch to a
4987 PLT target, redirect it to the preceding Thumb
4988 entry point. */
4989 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
4990 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 4991
99059e56 4992 target = pc_for_insn + offset;
48229727 4993
99059e56
RM		 4994 /* The BLX stub is ARM-mode code. Adjust the offset to
4995 take the different PC value (+8 instead of +4) into
48229727 4996 account. */
99059e56
RM		 4997 if (stub_type == arm_stub_a8_veneer_blx)
4998 offset += 4;
4999
5000 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5001 {
5002 char *stub_name = NULL;
5003
5004 if (num_a8_fixes == a8_fix_table_size)
5005 {
5006 a8_fix_table_size *= 2;
5007 a8_fixes = (struct a8_erratum_fix *)
5008 bfd_realloc (a8_fixes,
5009 sizeof (struct a8_erratum_fix)
5010 * a8_fix_table_size);
5011 }
48229727 5012
eb7c4339
NS		 5013 if (num_a8_fixes < prev_num_a8_fixes)
5014 {
5015 /* If we're doing a subsequent scan,
5016 check if we've found the same fix as
5017 before, and try and reuse the stub
5018 name. */
5019 stub_name = a8_fixes[num_a8_fixes].stub_name;
5020 if ((a8_fixes[num_a8_fixes].section != section)
5021 || (a8_fixes[num_a8_fixes].offset != i))
5022 {
5023 free (stub_name);
5024 stub_name = NULL;
5025 *stub_changed_p = TRUE;
5026 }
5027 }
5028
5029 if (!stub_name)
5030 {
21d799b5 5031 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5032 if (stub_name != NULL)
5033 sprintf (stub_name, "%x:%x", section->id, i);
5034 }
48229727 5035
99059e56
RM		 5036 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5037 a8_fixes[num_a8_fixes].section = section;
5038 a8_fixes[num_a8_fixes].offset = i;
5039 a8_fixes[num_a8_fixes].addend = offset;
5040 a8_fixes[num_a8_fixes].orig_insn = insn;
5041 a8_fixes[num_a8_fixes].stub_name = stub_name;
5042 a8_fixes[num_a8_fixes].stub_type = stub_type;
5043 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5044 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5045
99059e56
RM		 5046 num_a8_fixes++;
5047 }
5048 }
5049 }
48229727 5050
99059e56
RM		 5051 i += insn_32bit ? 4 : 2;
5052 last_was_32bit = insn_32bit;
48229727 5053 last_was_branch = is_32bit_branch;
99059e56
RM		 5054 }
5055 }
48229727
JB		 5056
5057 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5058 free (contents);
48229727 5059 }
fe33d2fa 5060
48229727
JB		 5061 *a8_fixes_p = a8_fixes;
5062 *num_a8_fixes_p = num_a8_fixes;
5063 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5064
81694485 5065 return FALSE;
48229727
JB		 5066}
5067
906e58ca
NC		 5068/* Determine and set the size of the stub section for a final link.
5069
5070 The basic idea here is to examine all the relocations looking for
5071 PC-relative calls to a target that is unreachable with a "bl"
5072 instruction. */
5073
5074bfd_boolean
5075elf32_arm_size_stubs (bfd *output_bfd,
5076 bfd *stub_bfd,
5077 struct bfd_link_info *info,
5078 bfd_signed_vma group_size,
7a89b94e
NC		 5079 asection * (*add_stub_section) (const char *, asection *,
5080 unsigned int),
906e58ca
NC		 5081 void (*layout_sections_again) (void))
5082{
5083 bfd_size_type stub_group_size;
07d72278 5084 bfd_boolean stubs_always_after_branch;
906e58ca 5085 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 5086 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 5087 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 5088 struct a8_erratum_reloc *a8_relocs = NULL;
5089 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
5090
4dfe6ac6
NC		 5091 if (htab == NULL)
5092 return FALSE;
5093
48229727
JB		 5094 if (htab->fix_cortex_a8)
5095 {
21d799b5 5096 a8_fixes = (struct a8_erratum_fix *)
99059e56 5097 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 5098 a8_relocs = (struct a8_erratum_reloc *)
99059e56 5099 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 5100 }
906e58ca
NC		 5101
5102 /* Propagate mach to stub bfd, because it may not have been
5103 finalized when we created stub_bfd. */
5104 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
5105 bfd_get_mach (output_bfd));
5106
5107 /* Stash our params away. */
5108 htab->stub_bfd = stub_bfd;
5109 htab->add_stub_section = add_stub_section;
5110 htab->layout_sections_again = layout_sections_again;
07d72278 5111 stubs_always_after_branch = group_size < 0;
48229727
JB		 5112
5113 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
5114 as the first half of a 32-bit branch straddling two 4K pages. This is a
5115 crude way of enforcing that. */
5116 if (htab->fix_cortex_a8)
5117 stubs_always_after_branch = 1;
5118
906e58ca
NC		 5119 if (group_size < 0)
5120 stub_group_size = -group_size;
5121 else
5122 stub_group_size = group_size;
5123
5124 if (stub_group_size == 1)
5125 {
5126 /* Default values. */
5127 /* Thumb branch range is +-4MB has to be used as the default
5128 maximum size (a given section can contain both ARM and Thumb
5129 code, so the worst case has to be taken into account).
5130
5131 This value is 24K less than that, which allows for 2025
5132 12-byte stubs. If we exceed that, then we will fail to link.
5133 The user will have to relink with an explicit group size
5134 option. */
5135 stub_group_size = 4170000;
5136 }
5137
07d72278 5138 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 5139
3ae046cc
NS		 5140 /* If we're applying the cortex A8 fix, we need to determine the
5141 program header size now, because we cannot change it later --
5142 that could alter section placements. Notice the A8 erratum fix
5143 ends up requiring the section addresses to remain unchanged
5144 modulo the page size. That's something we cannot represent
5145 inside BFD, and we don't want to force the section alignment to
5146 be the page size. */
5147 if (htab->fix_cortex_a8)
5148 (*htab->layout_sections_again) ();
5149
906e58ca
NC		 5150 while (1)
5151 {
5152 bfd *input_bfd;
5153 unsigned int bfd_indx;
5154 asection *stub_sec;
eb7c4339
NS		 5155 bfd_boolean stub_changed = FALSE;
5156 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 5157
48229727 5158 num_a8_fixes = 0;
906e58ca
NC		 5159 for (input_bfd = info->input_bfds, bfd_indx = 0;
5160 input_bfd != NULL;
c72f2fb2 5161 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 5162 {
5163 Elf_Internal_Shdr *symtab_hdr;
5164 asection *section;
5165 Elf_Internal_Sym *local_syms = NULL;
5166
99059e56
RM		 5167 if (!is_arm_elf (input_bfd))
5168 continue;
adbcc655 5169
48229727
JB		 5170 num_a8_relocs = 0;
5171
906e58ca
NC		 5172 /* We'll need the symbol table in a second. */
5173 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5174 if (symtab_hdr->sh_info == 0)
5175 continue;
5176
5177 /* Walk over each section attached to the input bfd. */
5178 for (section = input_bfd->sections;
5179 section != NULL;
5180 section = section->next)
5181 {
5182 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
5183
5184 /* If there aren't any relocs, then there's nothing more
5185 to do. */
5186 if ((section->flags & SEC_RELOC) == 0
5187 || section->reloc_count == 0
5188 || (section->flags & SEC_CODE) == 0)
5189 continue;
5190
5191 /* If this section is a link-once section that will be
5192 discarded, then don't create any stubs. */
5193 if (section->output_section == NULL
5194 || section->output_section->owner != output_bfd)
5195 continue;
5196
5197 /* Get the relocs. */
5198 internal_relocs
5199 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
5200 NULL, info->keep_memory);
5201 if (internal_relocs == NULL)
5202 goto error_ret_free_local;
5203
5204 /* Now examine each relocation. */
5205 irela = internal_relocs;
5206 irelaend = irela + section->reloc_count;
5207 for (; irela < irelaend; irela++)
5208 {
5209 unsigned int r_type, r_indx;
5210 enum elf32_arm_stub_type stub_type;
5211 struct elf32_arm_stub_hash_entry *stub_entry;
5212 asection *sym_sec;
5213 bfd_vma sym_value;
5214 bfd_vma destination;
5215 struct elf32_arm_link_hash_entry *hash;
7413f23f 5216 const char *sym_name;
906e58ca
NC		 5217 char *stub_name;
5218 const asection *id_sec;
34e77a92 5219 unsigned char st_type;
35fc36a8 5220 enum arm_st_branch_type branch_type;
48229727 5221 bfd_boolean created_stub = FALSE;
906e58ca
NC		 5222
5223 r_type = ELF32_R_TYPE (irela->r_info);
5224 r_indx = ELF32_R_SYM (irela->r_info);
5225
5226 if (r_type >= (unsigned int) R_ARM_max)
5227 {
5228 bfd_set_error (bfd_error_bad_value);
5229 error_ret_free_internal:
5230 if (elf_section_data (section)->relocs == NULL)
5231 free (internal_relocs);
5232 goto error_ret_free_local;
5233 }
b38cadfb 5234
0855e32b
NS		 5235 hash = NULL;
5236 if (r_indx >= symtab_hdr->sh_info)
5237 hash = elf32_arm_hash_entry
5238 (elf_sym_hashes (input_bfd)
5239 [r_indx - symtab_hdr->sh_info]);
b38cadfb 5240
0855e32b
NS		 5241 /* Only look for stubs on branch instructions, or
5242 non-relaxed TLSCALL */
906e58ca 5243 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 5244 && (r_type != (unsigned int) R_ARM_THM_CALL)
5245 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 5246 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
5247 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 5248 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 5249 && (r_type != (unsigned int) R_ARM_PLT32)
5250 && !((r_type == (unsigned int) R_ARM_TLS_CALL
5251 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
5252 && r_type == elf32_arm_tls_transition
5253 (info, r_type, &hash->root)
5254 && ((hash ? hash->tls_type
5255 : (elf32_arm_local_got_tls_type
5256 (input_bfd)[r_indx]))
5257 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 5258 continue;
5259
5260 /* Now determine the call target, its name, value,
5261 section. */
5262 sym_sec = NULL;
5263 sym_value = 0;
5264 destination = 0;
7413f23f 5265 sym_name = NULL;
b38cadfb 5266
0855e32b
NS		 5267 if (r_type == (unsigned int) R_ARM_TLS_CALL
5268 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
5269 {
5270 /* A non-relaxed TLS call. The target is the
5271 plt-resident trampoline and nothing to do
5272 with the symbol. */
5273 BFD_ASSERT (htab->tls_trampoline > 0);
5274 sym_sec = htab->root.splt;
5275 sym_value = htab->tls_trampoline;
5276 hash = 0;
34e77a92 5277 st_type = STT_FUNC;
35fc36a8 5278 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 5279 }
5280 else if (!hash)
906e58ca
NC		 5281 {
5282 /* It's a local symbol. */
5283 Elf_Internal_Sym *sym;
906e58ca
NC		 5284
5285 if (local_syms == NULL)
5286 {
5287 local_syms
5288 = (Elf_Internal_Sym *) symtab_hdr->contents;
5289 if (local_syms == NULL)
5290 local_syms
5291 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5292 symtab_hdr->sh_info, 0,
5293 NULL, NULL, NULL);
5294 if (local_syms == NULL)
5295 goto error_ret_free_internal;
5296 }
5297
5298 sym = local_syms + r_indx;
f6d250ce
TS		 5299 if (sym->st_shndx == SHN_UNDEF)
5300 sym_sec = bfd_und_section_ptr;
5301 else if (sym->st_shndx == SHN_ABS)
5302 sym_sec = bfd_abs_section_ptr;
5303 else if (sym->st_shndx == SHN_COMMON)
5304 sym_sec = bfd_com_section_ptr;
5305 else
5306 sym_sec =
5307 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
5308
ffcb4889
NS		 5309 if (!sym_sec)
5310 /* This is an undefined symbol. It can never
6a631e86 5311 be resolved. */
ffcb4889 5312 continue;
fe33d2fa 5313
906e58ca
NC		 5314 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
5315 sym_value = sym->st_value;
5316 destination = (sym_value + irela->r_addend
5317 + sym_sec->output_offset
5318 + sym_sec->output_section->vma);
34e77a92 5319 st_type = ELF_ST_TYPE (sym->st_info);
35fc36a8 5320 branch_type = ARM_SYM_BRANCH_TYPE (sym);
7413f23f
DJ		 5321 sym_name
5322 = bfd_elf_string_from_elf_section (input_bfd,
5323 symtab_hdr->sh_link,
5324 sym->st_name);
906e58ca
NC		 5325 }
5326 else
5327 {
5328 /* It's an external symbol. */
906e58ca
NC		 5329 while (hash->root.root.type == bfd_link_hash_indirect
5330 || hash->root.root.type == bfd_link_hash_warning)
5331 hash = ((struct elf32_arm_link_hash_entry *)
5332 hash->root.root.u.i.link);
5333
5334 if (hash->root.root.type == bfd_link_hash_defined
5335 || hash->root.root.type == bfd_link_hash_defweak)
5336 {
5337 sym_sec = hash->root.root.u.def.section;
5338 sym_value = hash->root.root.u.def.value;
022f8312
CL		 5339
5340 struct elf32_arm_link_hash_table *globals =
5341 elf32_arm_hash_table (info);
5342
5343 /* For a destination in a shared library,
5344 use the PLT stub as target address to
5345 decide whether a branch stub is
5346 needed. */
4dfe6ac6 5347 if (globals != NULL
362d30a1 5348 && globals->root.splt != NULL
4dfe6ac6 5349 && hash != NULL
022f8312
CL		 5350 && hash->root.plt.offset != (bfd_vma) -1)
5351 {
362d30a1 5352 sym_sec = globals->root.splt;
022f8312
CL		 5353 sym_value = hash->root.plt.offset;
5354 if (sym_sec->output_section != NULL)
5355 destination = (sym_value
5356 + sym_sec->output_offset
5357 + sym_sec->output_section->vma);
5358 }
5359 else if (sym_sec->output_section != NULL)
906e58ca
NC		 5360 destination = (sym_value + irela->r_addend
5361 + sym_sec->output_offset
5362 + sym_sec->output_section->vma);
5363 }
69c5861e
CL		 5364 else if ((hash->root.root.type == bfd_link_hash_undefined)
5365 || (hash->root.root.type == bfd_link_hash_undefweak))
5366 {
5367 /* For a shared library, use the PLT stub as
5368 target address to decide whether a long
5369 branch stub is needed.
5370 For absolute code, they cannot be handled. */
5371 struct elf32_arm_link_hash_table *globals =
5372 elf32_arm_hash_table (info);
5373
4dfe6ac6 5374 if (globals != NULL
362d30a1 5375 && globals->root.splt != NULL
4dfe6ac6 5376 && hash != NULL
69c5861e
CL		 5377 && hash->root.plt.offset != (bfd_vma) -1)
5378 {
362d30a1 5379 sym_sec = globals->root.splt;
69c5861e
CL		 5380 sym_value = hash->root.plt.offset;
5381 if (sym_sec->output_section != NULL)
5382 destination = (sym_value
5383 + sym_sec->output_offset
5384 + sym_sec->output_section->vma);
5385 }
5386 else
5387 continue;
5388 }
906e58ca
NC		 5389 else
5390 {
5391 bfd_set_error (bfd_error_bad_value);
5392 goto error_ret_free_internal;
5393 }
34e77a92 5394 st_type = hash->root.type;
35fc36a8 5395 branch_type = hash->root.target_internal;
7413f23f 5396 sym_name = hash->root.root.root.string;
906e58ca
NC		 5397 }
5398
48229727 5399 do
7413f23f 5400 {
48229727
JB		 5401 /* Determine what (if any) linker stub is needed. */
5402 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 5403 st_type, &branch_type,
5404 hash, destination, sym_sec,
48229727
JB		 5405 input_bfd, sym_name);
5406 if (stub_type == arm_stub_none)
5407 break;
5408
5409 /* Support for grouping stub sections. */
5410 id_sec = htab->stub_group[section->id].link_sec;
5411
5412 /* Get the name of this stub. */
5413 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash,
fe33d2fa 5414 irela, stub_type);
48229727
JB		 5415 if (!stub_name)
5416 goto error_ret_free_internal;
5417
5418 /* We've either created a stub for this reloc already,
5419 or we are about to. */
5420 created_stub = TRUE;
5421
5422 stub_entry = arm_stub_hash_lookup
5423 (&htab->stub_hash_table, stub_name,
5424 FALSE, FALSE);
5425 if (stub_entry != NULL)
5426 {
5427 /* The proper stub has already been created. */
5428 free (stub_name);
eb7c4339 5429 stub_entry->target_value = sym_value;
48229727
JB		 5430 break;
5431 }
7413f23f 5432
48229727
JB		 5433 stub_entry = elf32_arm_add_stub (stub_name, section,
5434 htab);
5435 if (stub_entry == NULL)
5436 {
5437 free (stub_name);
5438 goto error_ret_free_internal;
5439 }
7413f23f 5440
99059e56
RM		 5441 stub_entry->target_value = sym_value;
5442 stub_entry->target_section = sym_sec;
5443 stub_entry->stub_type = stub_type;
5444 stub_entry->h = hash;
5445 stub_entry->branch_type = branch_type;
5446
5447 if (sym_name == NULL)
5448 sym_name = "unnamed";
5449 stub_entry->output_name = (char *)
5450 bfd_alloc (htab->stub_bfd,
5451 sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5452 + strlen (sym_name));
5453 if (stub_entry->output_name == NULL)
5454 {
5455 free (stub_name);
5456 goto error_ret_free_internal;
5457 }
5458
5459 /* For historical reasons, use the existing names for
5460 ARM-to-Thumb and Thumb-to-ARM stubs. */
5461 if ((r_type == (unsigned int) R_ARM_THM_CALL
c5423981
TG		 5462 || r_type == (unsigned int) R_ARM_THM_JUMP24
5463 || r_type == (unsigned int) R_ARM_THM_JUMP19)
35fc36a8 5464 && branch_type == ST_BRANCH_TO_ARM)
99059e56
RM		 5465 sprintf (stub_entry->output_name,
5466 THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5467 else if ((r_type == (unsigned int) R_ARM_CALL
35fc36a8
RS		 5468 || r_type == (unsigned int) R_ARM_JUMP24)
5469 && branch_type == ST_BRANCH_TO_THUMB)
99059e56
RM		 5470 sprintf (stub_entry->output_name,
5471 ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5472 else
5473 sprintf (stub_entry->output_name, STUB_ENTRY_NAME,
5474 sym_name);
5475
5476 stub_changed = TRUE;
5477 }
5478 while (0);
5479
5480 /* Look for relocations which might trigger Cortex-A8
5481 erratum. */
5482 if (htab->fix_cortex_a8
5483 && (r_type == (unsigned int) R_ARM_THM_JUMP24
5484 || r_type == (unsigned int) R_ARM_THM_JUMP19
5485 || r_type == (unsigned int) R_ARM_THM_CALL
5486 || r_type == (unsigned int) R_ARM_THM_XPC22))
5487 {
5488 bfd_vma from = section->output_section->vma
5489 + section->output_offset
5490 + irela->r_offset;
5491
5492 if ((from & 0xfff) == 0xffe)
5493 {
5494 /* Found a candidate. Note we haven't checked the
5495 destination is within 4K here: if we do so (and
5496 don't create an entry in a8_relocs) we can't tell
5497 that a branch should have been relocated when
5498 scanning later. */
5499 if (num_a8_relocs == a8_reloc_table_size)
5500 {
5501 a8_reloc_table_size *= 2;
5502 a8_relocs = (struct a8_erratum_reloc *)
5503 bfd_realloc (a8_relocs,
5504 sizeof (struct a8_erratum_reloc)
5505 * a8_reloc_table_size);
5506 }
5507
5508 a8_relocs[num_a8_relocs].from = from;
5509 a8_relocs[num_a8_relocs].destination = destination;
5510 a8_relocs[num_a8_relocs].r_type = r_type;
5511 a8_relocs[num_a8_relocs].branch_type = branch_type;
5512 a8_relocs[num_a8_relocs].sym_name = sym_name;
5513 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
5514 a8_relocs[num_a8_relocs].hash = hash;
5515
5516 num_a8_relocs++;
5517 }
5518 }
906e58ca
NC		 5519 }
5520
99059e56
RM		 5521 /* We're done with the internal relocs, free them. */
5522 if (elf_section_data (section)->relocs == NULL)
5523 free (internal_relocs);
5524 }
48229727 5525
99059e56 5526 if (htab->fix_cortex_a8)
48229727 5527 {
99059e56
RM		 5528 /* Sort relocs which might apply to Cortex-A8 erratum. */
5529 qsort (a8_relocs, num_a8_relocs,
eb7c4339 5530 sizeof (struct a8_erratum_reloc),
99059e56 5531 &a8_reloc_compare);
48229727 5532
99059e56
RM		 5533 /* Scan for branches which might trigger Cortex-A8 erratum. */
5534 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 5535 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 5536 a8_relocs, num_a8_relocs,
5537 prev_num_a8_fixes, &stub_changed)
5538 != 0)
48229727 5539 goto error_ret_free_local;
5e681ec4 5540 }
5e681ec4
PB		 5541 }
5542
eb7c4339 5543 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 5544 stub_changed = TRUE;
48229727 5545
906e58ca
NC		 5546 if (!stub_changed)
5547 break;
5e681ec4 5548
906e58ca
NC		 5549 /* OK, we've added some stubs. Find out the new size of the
5550 stub sections. */
5551 for (stub_sec = htab->stub_bfd->sections;
5552 stub_sec != NULL;
5553 stub_sec = stub_sec->next)
3e6b1042
DJ		 5554 {
5555 /* Ignore non-stub sections. */
5556 if (!strstr (stub_sec->name, STUB_SUFFIX))
5557 continue;
5558
5559 stub_sec->size = 0;
5560 }
b34b2d70 5561
906e58ca
NC		 5562 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
5563
48229727
JB		 5564 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
5565 if (htab->fix_cortex_a8)
99059e56
RM		 5566 for (i = 0; i < num_a8_fixes; i++)
5567 {
48229727
JB		 5568 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
5569 a8_fixes[i].section, htab);
5570
5571 if (stub_sec == NULL)
5572 goto error_ret_free_local;
5573
99059e56
RM		 5574 stub_sec->size
5575 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
5576 NULL);
5577 }
48229727
JB		 5578
5579
906e58ca
NC		 5580 /* Ask the linker to do its stuff. */
5581 (*htab->layout_sections_again) ();
ba93b8ac
DJ		 5582 }
5583
48229727
JB		 5584 /* Add stubs for Cortex-A8 erratum fixes now. */
5585 if (htab->fix_cortex_a8)
5586 {
5587 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 5588 {
5589 struct elf32_arm_stub_hash_entry *stub_entry;
5590 char *stub_name = a8_fixes[i].stub_name;
5591 asection *section = a8_fixes[i].section;
5592 unsigned int section_id = a8_fixes[i].section->id;
5593 asection *link_sec = htab->stub_group[section_id].link_sec;
5594 asection *stub_sec = htab->stub_group[section_id].stub_sec;
5595 const insn_sequence *template_sequence;
5596 int template_size, size = 0;
5597
5598 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
5599 TRUE, FALSE);
5600 if (stub_entry == NULL)
5601 {
5602 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
5603 section->owner,
5604 stub_name);
5605 return FALSE;
5606 }
5607
5608 stub_entry->stub_sec = stub_sec;
5609 stub_entry->stub_offset = 0;
5610 stub_entry->id_sec = link_sec;
5611 stub_entry->stub_type = a8_fixes[i].stub_type;
5612 stub_entry->target_section = a8_fixes[i].section;
5613 stub_entry->target_value = a8_fixes[i].offset;
5614 stub_entry->target_addend = a8_fixes[i].addend;
5615 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 5616 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 5617
99059e56
RM		 5618 size = find_stub_size_and_template (a8_fixes[i].stub_type,
5619 &template_sequence,
5620 &template_size);
48229727 5621
99059e56
RM		 5622 stub_entry->stub_size = size;
5623 stub_entry->stub_template = template_sequence;
5624 stub_entry->stub_template_size = template_size;
5625 }
48229727
JB		 5626
5627 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 5628 elf32_arm_write_section(). */
48229727
JB		 5629 htab->a8_erratum_fixes = a8_fixes;
5630 htab->num_a8_erratum_fixes = num_a8_fixes;
5631 }
5632 else
5633 {
5634 htab->a8_erratum_fixes = NULL;
5635 htab->num_a8_erratum_fixes = 0;
5636 }
906e58ca
NC		 5637 return TRUE;
5638
5639 error_ret_free_local:
5640 return FALSE;
5e681ec4
PB		 5641}
5642
906e58ca
NC		 5643/* Build all the stubs associated with the current output file. The
5644 stubs are kept in a hash table attached to the main linker hash
5645 table. We also set up the .plt entries for statically linked PIC
5646 functions here. This function is called via arm_elf_finish in the
5647 linker. */
252b5132 5648
906e58ca
NC		 5649bfd_boolean
5650elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 5651{
906e58ca
NC		 5652 asection *stub_sec;
5653 struct bfd_hash_table *table;
5654 struct elf32_arm_link_hash_table *htab;
252b5132 5655
906e58ca 5656 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 5657 if (htab == NULL)
5658 return FALSE;
252b5132 5659
906e58ca
NC		 5660 for (stub_sec = htab->stub_bfd->sections;
5661 stub_sec != NULL;
5662 stub_sec = stub_sec->next)
252b5132 5663 {
906e58ca
NC		 5664 bfd_size_type size;
5665
8029a119 5666 /* Ignore non-stub sections. */
906e58ca
NC		 5667 if (!strstr (stub_sec->name, STUB_SUFFIX))
5668 continue;
5669
5670 /* Allocate memory to hold the linker stubs. */
5671 size = stub_sec->size;
21d799b5 5672 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 5673 if (stub_sec->contents == NULL && size != 0)
5674 return FALSE;
5675 stub_sec->size = 0;
252b5132
RH		 5676 }
5677
906e58ca
NC		 5678 /* Build the stubs as directed by the stub hash table. */
5679 table = &htab->stub_hash_table;
5680 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 5681 if (htab->fix_cortex_a8)
5682 {
5683 /* Place the cortex a8 stubs last. */
5684 htab->fix_cortex_a8 = -1;
5685 bfd_hash_traverse (table, arm_build_one_stub, info);
5686 }
252b5132 5687
906e58ca 5688 return TRUE;
252b5132
RH		 5689}
5690
9b485d32
NC		 5691/* Locate the Thumb encoded calling stub for NAME. */
5692
252b5132 5693static struct elf_link_hash_entry *
57e8b36a
NC		 5694find_thumb_glue (struct bfd_link_info *link_info,
5695 const char *name,
f2a9dd69 5696 char **error_message)
252b5132
RH		 5697{
5698 char *tmp_name;
5699 struct elf_link_hash_entry *hash;
5700 struct elf32_arm_link_hash_table *hash_table;
5701
5702 /* We need a pointer to the armelf specific hash table. */
5703 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 5704 if (hash_table == NULL)
5705 return NULL;
252b5132 5706
21d799b5 5707 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 5708 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 5709
5710 BFD_ASSERT (tmp_name);
5711
5712 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
5713
5714 hash = elf_link_hash_lookup
b34976b6 5715 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 5716
b1657152
AM		 5717 if (hash == NULL
5718 && asprintf (error_message, _("unable to find THUMB glue '%s' for '%s'"),
5719 tmp_name, name) == -1)
5720 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 5721
5722 free (tmp_name);
5723
5724 return hash;
5725}
5726
9b485d32
NC		 5727/* Locate the ARM encoded calling stub for NAME. */
5728
252b5132 5729static struct elf_link_hash_entry *
57e8b36a
NC		 5730find_arm_glue (struct bfd_link_info *link_info,
5731 const char *name,
f2a9dd69 5732 char **error_message)
252b5132
RH		 5733{
5734 char *tmp_name;
5735 struct elf_link_hash_entry *myh;
5736 struct elf32_arm_link_hash_table *hash_table;
5737
5738 /* We need a pointer to the elfarm specific hash table. */
5739 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 5740 if (hash_table == NULL)
5741 return NULL;
252b5132 5742
21d799b5 5743 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 5744 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 5745
5746 BFD_ASSERT (tmp_name);
5747
5748 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
5749
5750 myh = elf_link_hash_lookup
b34976b6 5751 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 5752
b1657152
AM		 5753 if (myh == NULL
5754 && asprintf (error_message, _("unable to find ARM glue '%s' for '%s'"),
5755 tmp_name, name) == -1)
5756 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 5757
5758 free (tmp_name);
5759
5760 return myh;
5761}
5762
8f6277f5 5763/* ARM->Thumb glue (static images):
252b5132
RH		 5764
5765 .arm
5766 __func_from_arm:
5767 ldr r12, __func_addr
5768 bx r12
5769 __func_addr:
906e58ca 5770 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 5771
26079076
PB		 5772 (v5t static images)
5773 .arm
5774 __func_from_arm:
5775 ldr pc, __func_addr
5776 __func_addr:
906e58ca 5777 .word func @ behave as if you saw a ARM_32 reloc.
26079076 5778
8f6277f5
PB		 5779 (relocatable images)
5780 .arm
5781 __func_from_arm:
5782 ldr r12, __func_offset
5783 add r12, r12, pc
5784 bx r12
5785 __func_offset:
8029a119 5786 .word func - . */
8f6277f5
PB		 5787
5788#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 5789static const insn32 a2t1_ldr_insn = 0xe59fc000;
5790static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
5791static const insn32 a2t3_func_addr_insn = 0x00000001;
5792
26079076
PB		 5793#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
5794static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
5795static const insn32 a2t2v5_func_addr_insn = 0x00000001;
5796
8f6277f5
PB		 5797#define ARM2THUMB_PIC_GLUE_SIZE 16
5798static const insn32 a2t1p_ldr_insn = 0xe59fc004;
5799static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
5800static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
5801
9b485d32 5802/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 5803
8029a119
NC		 5804 .thumb .thumb
5805 .align 2 .align 2
5806 __func_from_thumb: __func_from_thumb:
5807 bx pc push {r6, lr}
5808 nop ldr r6, __func_addr
5809 .arm mov lr, pc
5810 b func bx r6
99059e56
RM		 5811 .arm
5812 ;; back_to_thumb
5813 ldmia r13! {r6, lr}
5814 bx lr
5815 __func_addr:
5816 .word func */
252b5132
RH		 5817
5818#define THUMB2ARM_GLUE_SIZE 8
5819static const insn16 t2a1_bx_pc_insn = 0x4778;
5820static const insn16 t2a2_noop_insn = 0x46c0;
5821static const insn32 t2a3_b_insn = 0xea000000;
5822
c7b8f16e 5823#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 5824#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
5825#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 5826
845b51d6
PB		 5827#define ARM_BX_VENEER_SIZE 12
5828static const insn32 armbx1_tst_insn = 0xe3100001;
5829static const insn32 armbx2_moveq_insn = 0x01a0f000;
5830static const insn32 armbx3_bx_insn = 0xe12fff10;
5831
7e392df6 5832#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 5833static void
5834arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 5835{
5836 asection * s;
8029a119 5837 bfd_byte * contents;
252b5132 5838
8029a119 5839 if (size == 0)
3e6b1042
DJ		 5840 {
5841 /* Do not include empty glue sections in the output. */
5842 if (abfd != NULL)
5843 {
3d4d4302 5844 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 5845 if (s != NULL)
5846 s->flags |= SEC_EXCLUDE;
5847 }
5848 return;
5849 }
252b5132 5850
8029a119 5851 BFD_ASSERT (abfd != NULL);
252b5132 5852
3d4d4302 5853 s = bfd_get_linker_section (abfd, name);
8029a119 5854 BFD_ASSERT (s != NULL);
252b5132 5855
21d799b5 5856 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 5857
8029a119
NC		 5858 BFD_ASSERT (s->size == size);
5859 s->contents = contents;
5860}
906e58ca 5861
8029a119
NC		 5862bfd_boolean
5863bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
5864{
5865 struct elf32_arm_link_hash_table * globals;
906e58ca 5866
8029a119
NC		 5867 globals = elf32_arm_hash_table (info);
5868 BFD_ASSERT (globals != NULL);
906e58ca 5869
8029a119
NC		 5870 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5871 globals->arm_glue_size,
5872 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 5873
8029a119
NC		 5874 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5875 globals->thumb_glue_size,
5876 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 5877
8029a119
NC		 5878 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5879 globals->vfp11_erratum_glue_size,
5880 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 5881
a504d23a
LA		 5882 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5883 globals->stm32l4xx_erratum_glue_size,
5884 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
5885
8029a119
NC		 5886 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5887 globals->bx_glue_size,
845b51d6
PB		 5888 ARM_BX_GLUE_SECTION_NAME);
5889
b34976b6 5890 return TRUE;
252b5132
RH		 5891}
5892
a4fd1a8e 5893/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 5894 returns the symbol identifying the stub. */
5895
a4fd1a8e 5896static struct elf_link_hash_entry *
57e8b36a
NC		 5897record_arm_to_thumb_glue (struct bfd_link_info * link_info,
5898 struct elf_link_hash_entry * h)
252b5132
RH		 5899{
5900 const char * name = h->root.root.string;
63b0f745 5901 asection * s;
252b5132
RH		 5902 char * tmp_name;
5903 struct elf_link_hash_entry * myh;
14a793b2 5904 struct bfd_link_hash_entry * bh;
252b5132 5905 struct elf32_arm_link_hash_table * globals;
dc810e39 5906 bfd_vma val;
2f475487 5907 bfd_size_type size;
252b5132
RH		 5908
5909 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 5910 BFD_ASSERT (globals != NULL);
5911 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
5912
3d4d4302 5913 s = bfd_get_linker_section
252b5132
RH		 5914 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
5915
252b5132
RH		 5916 BFD_ASSERT (s != NULL);
5917
21d799b5 5918 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 5919 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 5920
5921 BFD_ASSERT (tmp_name);
5922
5923 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
5924
5925 myh = elf_link_hash_lookup
b34976b6 5926 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 5927
5928 if (myh != NULL)
5929 {
9b485d32 5930 /* We've already seen this guy. */
252b5132 5931 free (tmp_name);
a4fd1a8e 5932 return myh;
252b5132
RH		 5933 }
5934
57e8b36a
NC		 5935 /* The only trick here is using hash_table->arm_glue_size as the value.
5936 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 5937 putting it. The +1 on the value marks that the stub has not been
5938 output yet - not that it is a Thumb function. */
14a793b2 5939 bh = NULL;
dc810e39
AM		 5940 val = globals->arm_glue_size + 1;
5941 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
5942 tmp_name, BSF_GLOBAL, s, val,
b34976b6 5943 NULL, TRUE, FALSE, &bh);
252b5132 5944
b7693d02
DJ		 5945 myh = (struct elf_link_hash_entry *) bh;
5946 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
5947 myh->forced_local = 1;
5948
252b5132
RH		 5949 free (tmp_name);
5950
0e1862bb
L		 5951 if (bfd_link_pic (link_info)
5952 || globals->root.is_relocatable_executable
27e55c4d 5953 || globals->pic_veneer)
2f475487 5954 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 5955 else if (globals->use_blx)
5956 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 5957 else
2f475487
AM		 5958 size = ARM2THUMB_STATIC_GLUE_SIZE;
5959
5960 s->size += size;
5961 globals->arm_glue_size += size;
252b5132 5962
a4fd1a8e 5963 return myh;
252b5132
RH		 5964}
5965
845b51d6
PB		 5966/* Allocate space for ARMv4 BX veneers. */
5967
5968static void
5969record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
5970{
5971 asection * s;
5972 struct elf32_arm_link_hash_table *globals;
5973 char *tmp_name;
5974 struct elf_link_hash_entry *myh;
5975 struct bfd_link_hash_entry *bh;
5976 bfd_vma val;
5977
5978 /* BX PC does not need a veneer. */
5979 if (reg == 15)
5980 return;
5981
5982 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 5983 BFD_ASSERT (globals != NULL);
5984 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
5985
5986 /* Check if this veneer has already been allocated. */
5987 if (globals->bx_glue_offset[reg])
5988 return;
5989
3d4d4302 5990 s = bfd_get_linker_section
845b51d6
PB		 5991 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
5992
5993 BFD_ASSERT (s != NULL);
5994
5995 /* Add symbol for veneer. */
21d799b5
NC		 5996 tmp_name = (char *)
5997 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 5998
845b51d6 5999 BFD_ASSERT (tmp_name);
906e58ca 6000
845b51d6 6001 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 6002
845b51d6
PB		 6003 myh = elf_link_hash_lookup
6004 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6005
845b51d6 6006 BFD_ASSERT (myh == NULL);
906e58ca 6007
845b51d6
PB		 6008 bh = NULL;
6009 val = globals->bx_glue_size;
6010 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 6011 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6012 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 6013
6014 myh = (struct elf_link_hash_entry *) bh;
6015 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6016 myh->forced_local = 1;
6017
6018 s->size += ARM_BX_VENEER_SIZE;
6019 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
6020 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
6021}
6022
6023
c7b8f16e
JB		 6024/* Add an entry to the code/data map for section SEC. */
6025
6026static void
6027elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
6028{
6029 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
6030 unsigned int newidx;
906e58ca 6031
c7b8f16e
JB		 6032 if (sec_data->map == NULL)
6033 {
21d799b5 6034 sec_data->map = (elf32_arm_section_map *)
99059e56 6035 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 6036 sec_data->mapcount = 0;
6037 sec_data->mapsize = 1;
6038 }
906e58ca 6039
c7b8f16e 6040 newidx = sec_data->mapcount++;
906e58ca 6041
c7b8f16e
JB		 6042 if (sec_data->mapcount > sec_data->mapsize)
6043 {
6044 sec_data->mapsize *= 2;
21d799b5 6045 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 6046 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
6047 * sizeof (elf32_arm_section_map));
515ef31d
NC		 6048 }
6049
6050 if (sec_data->map)
6051 {
6052 sec_data->map[newidx].vma = vma;
6053 sec_data->map[newidx].type = type;
c7b8f16e 6054 }
c7b8f16e
JB		 6055}
6056
6057
6058/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
6059 veneers are handled for now. */
6060
6061static bfd_vma
6062record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 6063 elf32_vfp11_erratum_list *branch,
6064 bfd *branch_bfd,
6065 asection *branch_sec,
6066 unsigned int offset)
c7b8f16e
JB		 6067{
6068 asection *s;
6069 struct elf32_arm_link_hash_table *hash_table;
6070 char *tmp_name;
6071 struct elf_link_hash_entry *myh;
6072 struct bfd_link_hash_entry *bh;
6073 bfd_vma val;
6074 struct _arm_elf_section_data *sec_data;
c7b8f16e 6075 elf32_vfp11_erratum_list *newerr;
906e58ca 6076
c7b8f16e 6077 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 6078 BFD_ASSERT (hash_table != NULL);
6079 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 6080
3d4d4302 6081 s = bfd_get_linker_section
c7b8f16e 6082 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 6083
c7b8f16e 6084 sec_data = elf32_arm_section_data (s);
906e58ca 6085
c7b8f16e 6086 BFD_ASSERT (s != NULL);
906e58ca 6087
21d799b5 6088 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 6089 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 6090
c7b8f16e 6091 BFD_ASSERT (tmp_name);
906e58ca 6092
c7b8f16e
JB		 6093 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
6094 hash_table->num_vfp11_fixes);
906e58ca 6095
c7b8f16e
JB		 6096 myh = elf_link_hash_lookup
6097 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6098
c7b8f16e 6099 BFD_ASSERT (myh == NULL);
906e58ca 6100
c7b8f16e
JB		 6101 bh = NULL;
6102 val = hash_table->vfp11_erratum_glue_size;
6103 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 6104 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6105 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 6106
6107 myh = (struct elf_link_hash_entry *) bh;
6108 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6109 myh->forced_local = 1;
6110
6111 /* Link veneer back to calling location. */
c7e2358a 6112 sec_data->erratumcount += 1;
21d799b5
NC		 6113 newerr = (elf32_vfp11_erratum_list *)
6114 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 6115
c7b8f16e
JB		 6116 newerr->type = VFP11_ERRATUM_ARM_VENEER;
6117 newerr->vma = -1;
6118 newerr->u.v.branch = branch;
6119 newerr->u.v.id = hash_table->num_vfp11_fixes;
6120 branch->u.b.veneer = newerr;
6121
6122 newerr->next = sec_data->erratumlist;
6123 sec_data->erratumlist = newerr;
6124
6125 /* A symbol for the return from the veneer. */
6126 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
6127 hash_table->num_vfp11_fixes);
6128
6129 myh = elf_link_hash_lookup
6130 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6131
c7b8f16e
JB		 6132 if (myh != NULL)
6133 abort ();
6134
6135 bh = NULL;
6136 val = offset + 4;
6137 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
6138 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 6139
c7b8f16e
JB		 6140 myh = (struct elf_link_hash_entry *) bh;
6141 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6142 myh->forced_local = 1;
6143
6144 free (tmp_name);
906e58ca 6145
c7b8f16e
JB		 6146 /* Generate a mapping symbol for the veneer section, and explicitly add an
6147 entry for that symbol to the code/data map for the section. */
6148 if (hash_table->vfp11_erratum_glue_size == 0)
6149 {
6150 bh = NULL;
6151 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 6152 ever requires this erratum fix. */
c7b8f16e
JB		 6153 _bfd_generic_link_add_one_symbol (link_info,
6154 hash_table->bfd_of_glue_owner, "$a",
6155 BSF_LOCAL, s, 0, NULL,
99059e56 6156 TRUE, FALSE, &bh);
c7b8f16e
JB		 6157
6158 myh = (struct elf_link_hash_entry *) bh;
6159 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
6160 myh->forced_local = 1;
906e58ca 6161
c7b8f16e 6162 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 6163 BFDs. We must make a note of this generated mapping symbol
6164 ourselves so that code byteswapping works properly in
6165 elf32_arm_write_section. */
c7b8f16e
JB		 6166 elf32_arm_section_map_add (s, 'a', 0);
6167 }
906e58ca 6168
c7b8f16e
JB		 6169 s->size += VFP11_ERRATUM_VENEER_SIZE;
6170 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
6171 hash_table->num_vfp11_fixes++;
906e58ca 6172
c7b8f16e
JB		 6173 /* The offset of the veneer. */
6174 return val;
6175}
6176
a504d23a
LA		 6177/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
6178 veneers need to be handled because used only in Cortex-M. */
6179
6180static bfd_vma
6181record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
6182 elf32_stm32l4xx_erratum_list *branch,
6183 bfd *branch_bfd,
6184 asection *branch_sec,
6185 unsigned int offset,
6186 bfd_size_type veneer_size)
6187{
6188 asection *s;
6189 struct elf32_arm_link_hash_table *hash_table;
6190 char *tmp_name;
6191 struct elf_link_hash_entry *myh;
6192 struct bfd_link_hash_entry *bh;
6193 bfd_vma val;
6194 struct _arm_elf_section_data *sec_data;
6195 elf32_stm32l4xx_erratum_list *newerr;
6196
6197 hash_table = elf32_arm_hash_table (link_info);
6198 BFD_ASSERT (hash_table != NULL);
6199 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
6200
6201 s = bfd_get_linker_section
6202 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6203
6204 BFD_ASSERT (s != NULL);
6205
6206 sec_data = elf32_arm_section_data (s);
6207
6208 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
6209 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
6210
6211 BFD_ASSERT (tmp_name);
6212
6213 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
6214 hash_table->num_stm32l4xx_fixes);
6215
6216 myh = elf_link_hash_lookup
6217 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
6218
6219 BFD_ASSERT (myh == NULL);
6220
6221 bh = NULL;
6222 val = hash_table->stm32l4xx_erratum_glue_size;
6223 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
6224 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6225 NULL, TRUE, FALSE, &bh);
6226
6227 myh = (struct elf_link_hash_entry *) bh;
6228 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6229 myh->forced_local = 1;
6230
6231 /* Link veneer back to calling location. */
6232 sec_data->stm32l4xx_erratumcount += 1;
6233 newerr = (elf32_stm32l4xx_erratum_list *)
6234 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
6235
6236 newerr->type = STM32L4XX_ERRATUM_VENEER;
6237 newerr->vma = -1;
6238 newerr->u.v.branch = branch;
6239 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
6240 branch->u.b.veneer = newerr;
6241
6242 newerr->next = sec_data->stm32l4xx_erratumlist;
6243 sec_data->stm32l4xx_erratumlist = newerr;
6244
6245 /* A symbol for the return from the veneer. */
6246 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
6247 hash_table->num_stm32l4xx_fixes);
6248
6249 myh = elf_link_hash_lookup
6250 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
6251
6252 if (myh != NULL)
6253 abort ();
6254
6255 bh = NULL;
6256 val = offset + 4;
6257 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
6258 branch_sec, val, NULL, TRUE, FALSE, &bh);
6259
6260 myh = (struct elf_link_hash_entry *) bh;
6261 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6262 myh->forced_local = 1;
6263
6264 free (tmp_name);
6265
6266 /* Generate a mapping symbol for the veneer section, and explicitly add an
6267 entry for that symbol to the code/data map for the section. */
6268 if (hash_table->stm32l4xx_erratum_glue_size == 0)
6269 {
6270 bh = NULL;
6271 /* Creates a THUMB symbol since there is no other choice. */
6272 _bfd_generic_link_add_one_symbol (link_info,
6273 hash_table->bfd_of_glue_owner, "$t",
6274 BSF_LOCAL, s, 0, NULL,
6275 TRUE, FALSE, &bh);
6276
6277 myh = (struct elf_link_hash_entry *) bh;
6278 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
6279 myh->forced_local = 1;
6280
6281 /* The elf32_arm_init_maps function only cares about symbols from input
6282 BFDs. We must make a note of this generated mapping symbol
6283 ourselves so that code byteswapping works properly in
6284 elf32_arm_write_section. */
6285 elf32_arm_section_map_add (s, 't', 0);
6286 }
6287
6288 s->size += veneer_size;
6289 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
6290 hash_table->num_stm32l4xx_fixes++;
6291
6292 /* The offset of the veneer. */
6293 return val;
6294}
6295
8029a119 6296#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 6297 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
6298 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 6299
6300/* Create a fake section for use by the ARM backend of the linker. */
6301
6302static bfd_boolean
6303arm_make_glue_section (bfd * abfd, const char * name)
6304{
6305 asection * sec;
6306
3d4d4302 6307 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 6308 if (sec != NULL)
6309 /* Already made. */
6310 return TRUE;
6311
3d4d4302 6312 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 6313
6314 if (sec == NULL
6315 || !bfd_set_section_alignment (abfd, sec, 2))
6316 return FALSE;
6317
6318 /* Set the gc mark to prevent the section from being removed by garbage
6319 collection, despite the fact that no relocs refer to this section. */
6320 sec->gc_mark = 1;
6321
6322 return TRUE;
6323}
6324
1db37fe6
YG		 6325/* Set size of .plt entries. This function is called from the
6326 linker scripts in ld/emultempl/{armelf}.em. */
6327
6328void
6329bfd_elf32_arm_use_long_plt (void)
6330{
6331 elf32_arm_use_long_plt_entry = TRUE;
6332}
6333
8afb0e02
NC		 6334/* Add the glue sections to ABFD. This function is called from the
6335 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 6336
b34976b6 6337bfd_boolean
57e8b36a
NC		 6338bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
6339 struct bfd_link_info *info)
252b5132 6340{
a504d23a
LA		 6341 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
6342 bfd_boolean dostm32l4xx = globals
6343 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
6344 bfd_boolean addglue;
6345
8afb0e02
NC		 6346 /* If we are only performing a partial
6347 link do not bother adding the glue. */
0e1862bb 6348 if (bfd_link_relocatable (info))
b34976b6 6349 return TRUE;
252b5132 6350
a504d23a 6351 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 6352 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
6353 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
6354 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 6355
6356 if (!dostm32l4xx)
6357 return addglue;
6358
6359 return addglue
6360 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 6361}
6362
6363/* Select a BFD to be used to hold the sections used by the glue code.
6364 This function is called from the linker scripts in ld/emultempl/
8029a119 6365 {armelf/pe}.em. */
8afb0e02 6366
b34976b6 6367bfd_boolean
57e8b36a 6368bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 6369{
6370 struct elf32_arm_link_hash_table *globals;
6371
6372 /* If we are only performing a partial link
6373 do not bother getting a bfd to hold the glue. */
0e1862bb 6374 if (bfd_link_relocatable (info))
b34976b6 6375 return TRUE;
8afb0e02 6376
b7693d02
DJ		 6377 /* Make sure we don't attach the glue sections to a dynamic object. */
6378 BFD_ASSERT (!(abfd->flags & DYNAMIC));
6379
8afb0e02 6380 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 6381 BFD_ASSERT (globals != NULL);
6382
6383 if (globals->bfd_of_glue_owner != NULL)
b34976b6 6384 return TRUE;
8afb0e02 6385
252b5132
RH		 6386 /* Save the bfd for later use. */
6387 globals->bfd_of_glue_owner = abfd;
cedb70c5 6388
b34976b6 6389 return TRUE;
252b5132
RH		 6390}
6391
906e58ca
NC		 6392static void
6393check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 6394{
2de70689
MGD		 6395 int cpu_arch;
6396
b38cadfb 6397 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 6398 Tag_CPU_arch);
6399
6400 if (globals->fix_arm1176)
6401 {
6402 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
6403 globals->use_blx = 1;
6404 }
6405 else
6406 {
6407 if (cpu_arch > TAG_CPU_ARCH_V4T)
6408 globals->use_blx = 1;
6409 }
39b41c9c
PB		 6410}
6411
b34976b6 6412bfd_boolean
57e8b36a 6413bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 6414 struct bfd_link_info *link_info)
252b5132
RH		 6415{
6416 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 6417 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 6418 Elf_Internal_Rela *irel, *irelend;
6419 bfd_byte *contents = NULL;
252b5132
RH		 6420
6421 asection *sec;
6422 struct elf32_arm_link_hash_table *globals;
6423
6424 /* If we are only performing a partial link do not bother
6425 to construct any glue. */
0e1862bb 6426 if (bfd_link_relocatable (link_info))
b34976b6 6427 return TRUE;
252b5132 6428
39ce1a6a
NC		 6429 /* Here we have a bfd that is to be included on the link. We have a
6430 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 6431 globals = elf32_arm_hash_table (link_info);
252b5132 6432 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 6433
6434 check_use_blx (globals);
252b5132 6435
d504ffc8 6436 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 6437 {
d003868e
AM		 6438 _bfd_error_handler (_("%B: BE8 images only valid in big-endian mode."),
6439 abfd);
e489d0ae
PB		 6440 return FALSE;
6441 }
f21f3fe0 6442
39ce1a6a
NC		 6443 /* PR 5398: If we have not decided to include any loadable sections in
6444 the output then we will not have a glue owner bfd. This is OK, it
6445 just means that there is nothing else for us to do here. */
6446 if (globals->bfd_of_glue_owner == NULL)
6447 return TRUE;
6448
252b5132
RH		 6449 /* Rummage around all the relocs and map the glue vectors. */
6450 sec = abfd->sections;
6451
6452 if (sec == NULL)
b34976b6 6453 return TRUE;
252b5132
RH		 6454
6455 for (; sec != NULL; sec = sec->next)
6456 {
6457 if (sec->reloc_count == 0)
6458 continue;
6459
2f475487
AM		 6460 if ((sec->flags & SEC_EXCLUDE) != 0)
6461 continue;
6462
0ffa91dd 6463 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 6464
9b485d32 6465 /* Load the relocs. */
6cdc0ccc 6466 internal_relocs
906e58ca 6467 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 6468
6cdc0ccc
AM		 6469 if (internal_relocs == NULL)
6470 goto error_return;
252b5132 6471
6cdc0ccc
AM		 6472 irelend = internal_relocs + sec->reloc_count;
6473 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 6474 {
6475 long r_type;
6476 unsigned long r_index;
252b5132
RH		 6477
6478 struct elf_link_hash_entry *h;
6479
6480 r_type = ELF32_R_TYPE (irel->r_info);
6481 r_index = ELF32_R_SYM (irel->r_info);
6482
9b485d32 6483 /* These are the only relocation types we care about. */
ba96a88f 6484 if ( r_type != R_ARM_PC24
845b51d6 6485 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 6486 continue;
6487
6488 /* Get the section contents if we haven't done so already. */
6489 if (contents == NULL)
6490 {
6491 /* Get cached copy if it exists. */
6492 if (elf_section_data (sec)->this_hdr.contents != NULL)
6493 contents = elf_section_data (sec)->this_hdr.contents;
6494 else
6495 {
6496 /* Go get them off disk. */
57e8b36a 6497 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 6498 goto error_return;
6499 }
6500 }
6501
845b51d6
PB		 6502 if (r_type == R_ARM_V4BX)
6503 {
6504 int reg;
6505
6506 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
6507 record_arm_bx_glue (link_info, reg);
6508 continue;
6509 }
6510
a7c10850 6511 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 6512 h = NULL;
6513
9b485d32 6514 /* We don't care about local symbols. */
252b5132
RH		 6515 if (r_index < symtab_hdr->sh_info)
6516 continue;
6517
9b485d32 6518 /* This is an external symbol. */
252b5132
RH		 6519 r_index -= symtab_hdr->sh_info;
6520 h = (struct elf_link_hash_entry *)
6521 elf_sym_hashes (abfd)[r_index];
6522
6523 /* If the relocation is against a static symbol it must be within
6524 the current section and so cannot be a cross ARM/Thumb relocation. */
6525 if (h == NULL)
6526 continue;
6527
d504ffc8
DJ		 6528 /* If the call will go through a PLT entry then we do not need
6529 glue. */
362d30a1 6530 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 6531 continue;
6532
252b5132
RH		 6533 switch (r_type)
6534 {
6535 case R_ARM_PC24:
6536 /* This one is a call from arm code. We need to look up
99059e56
RM		 6537 the target of the call. If it is a thumb target, we
6538 insert glue. */
35fc36a8 6539 if (h->target_internal == ST_BRANCH_TO_THUMB)
252b5132
RH		 6540 record_arm_to_thumb_glue (link_info, h);
6541 break;
6542
252b5132 6543 default:
c6596c5e 6544 abort ();
252b5132
RH		 6545 }
6546 }
6cdc0ccc
AM		 6547
6548 if (contents != NULL
6549 && elf_section_data (sec)->this_hdr.contents != contents)
6550 free (contents);
6551 contents = NULL;
6552
6553 if (internal_relocs != NULL
6554 && elf_section_data (sec)->relocs != internal_relocs)
6555 free (internal_relocs);
6556 internal_relocs = NULL;
252b5132
RH		 6557 }
6558
b34976b6 6559 return TRUE;
9a5aca8c 6560
252b5132 6561error_return:
6cdc0ccc
AM		 6562 if (contents != NULL
6563 && elf_section_data (sec)->this_hdr.contents != contents)
6564 free (contents);
6565 if (internal_relocs != NULL
6566 && elf_section_data (sec)->relocs != internal_relocs)
6567 free (internal_relocs);
9a5aca8c 6568
b34976b6 6569 return FALSE;
252b5132 6570}
7e392df6 6571#endif
252b5132 6572
eb043451 6573
c7b8f16e
JB		 6574/* Initialise maps of ARM/Thumb/data for input BFDs. */
6575
6576void
6577bfd_elf32_arm_init_maps (bfd *abfd)
6578{
6579 Elf_Internal_Sym *isymbuf;
6580 Elf_Internal_Shdr *hdr;
6581 unsigned int i, localsyms;
6582
af1f4419
NC		 6583 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
6584 if (! is_arm_elf (abfd))
6585 return;
6586
c7b8f16e
JB		 6587 if ((abfd->flags & DYNAMIC) != 0)
6588 return;
6589
0ffa91dd 6590 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 6591 localsyms = hdr->sh_info;
6592
6593 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
6594 should contain the number of local symbols, which should come before any
6595 global symbols. Mapping symbols are always local. */
6596 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
6597 NULL);
6598
6599 /* No internal symbols read? Skip this BFD. */
6600 if (isymbuf == NULL)
6601 return;
6602
6603 for (i = 0; i < localsyms; i++)
6604 {
6605 Elf_Internal_Sym *isym = &isymbuf[i];
6606 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
6607 const char *name;
906e58ca 6608
c7b8f16e 6609 if (sec != NULL
99059e56
RM		 6610 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
6611 {
6612 name = bfd_elf_string_from_elf_section (abfd,
6613 hdr->sh_link, isym->st_name);
906e58ca 6614
99059e56 6615 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 6616 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 6617 elf32_arm_section_map_add (sec, name[1], isym->st_value);
6618 }
c7b8f16e
JB		 6619 }
6620}
6621
6622
48229727
JB		 6623/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
6624 say what they wanted. */
6625
6626void
6627bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
6628{
6629 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
6630 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
6631
4dfe6ac6
NC		 6632 if (globals == NULL)
6633 return;
6634
48229727
JB		 6635 if (globals->fix_cortex_a8 == -1)
6636 {
6637 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
6638 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
6639 && (out_attr[Tag_CPU_arch_profile].i == 'A'
6640 || out_attr[Tag_CPU_arch_profile].i == 0))
6641 globals->fix_cortex_a8 = 1;
6642 else
6643 globals->fix_cortex_a8 = 0;
6644 }
6645}
6646
6647
c7b8f16e
JB		 6648void
6649bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
6650{
6651 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 6652 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 6653
4dfe6ac6
NC		 6654 if (globals == NULL)
6655 return;
c7b8f16e
JB		 6656 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
6657 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
6658 {
6659 switch (globals->vfp11_fix)
99059e56
RM		 6660 {
6661 case BFD_ARM_VFP11_FIX_DEFAULT:
6662 case BFD_ARM_VFP11_FIX_NONE:
6663 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
6664 break;
6665
6666 default:
6667 /* Give a warning, but do as the user requests anyway. */
6668 (*_bfd_error_handler) (_("%B: warning: selected VFP11 erratum "
6669 "workaround is not necessary for target architecture"), obfd);
6670 }
c7b8f16e
JB		 6671 }
6672 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
6673 /* For earlier architectures, we might need the workaround, but do not
6674 enable it by default. If users is running with broken hardware, they
6675 must enable the erratum fix explicitly. */
6676 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
6677}
6678
a504d23a
LA		 6679void
6680bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
6681{
6682 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
6683 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
6684
6685 if (globals == NULL)
6686 return;
6687
6688 /* We assume only Cortex-M4 may require the fix. */
6689 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
6690 || out_attr[Tag_CPU_arch_profile].i != 'M')
6691 {
6692 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
6693 /* Give a warning, but do as the user requests anyway. */
6694 (*_bfd_error_handler)
6695 (_("%B: warning: selected STM32L4XX erratum "
6696 "workaround is not necessary for target architecture"), obfd);
6697 }
6698}
c7b8f16e 6699
906e58ca
NC		 6700enum bfd_arm_vfp11_pipe
6701{
c7b8f16e
JB		 6702 VFP11_FMAC,
6703 VFP11_LS,
6704 VFP11_DS,
6705 VFP11_BAD
6706};
6707
6708/* Return a VFP register number. This is encoded as RX:X for single-precision
6709 registers, or X:RX for double-precision registers, where RX is the group of
6710 four bits in the instruction encoding and X is the single extension bit.
6711 RX and X fields are specified using their lowest (starting) bit. The return
6712 value is:
6713
6714 0...31: single-precision registers s0...s31
6715 32...63: double-precision registers d0...d31.
906e58ca 6716
c7b8f16e
JB		 6717 Although X should be zero for VFP11 (encoding d0...d15 only), we might
6718 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 6719
c7b8f16e
JB		 6720static unsigned int
6721bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 6722 unsigned int x)
c7b8f16e
JB		 6723{
6724 if (is_double)
6725 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
6726 else
6727 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
6728}
6729
6730/* Set bits in *WMASK according to a register number REG as encoded by
6731 bfd_arm_vfp11_regno(). Ignore d16-d31. */
6732
6733static void
6734bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
6735{
6736 if (reg < 32)
6737 *wmask |= 1 << reg;
6738 else if (reg < 48)
6739 *wmask |= 3 << ((reg - 32) * 2);
6740}
6741
6742/* Return TRUE if WMASK overwrites anything in REGS. */
6743
6744static bfd_boolean
6745bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
6746{
6747 int i;
906e58ca 6748
c7b8f16e
JB		 6749 for (i = 0; i < numregs; i++)
6750 {
6751 unsigned int reg = regs[i];
6752
6753 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 6754 return TRUE;
906e58ca 6755
c7b8f16e
JB		 6756 reg -= 32;
6757
6758 if (reg >= 16)
99059e56 6759 continue;
906e58ca 6760
c7b8f16e 6761 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 6762 return TRUE;
c7b8f16e 6763 }
906e58ca 6764
c7b8f16e
JB		 6765 return FALSE;
6766}
6767
6768/* In this function, we're interested in two things: finding input registers
6769 for VFP data-processing instructions, and finding the set of registers which
6770 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
6771 hold the written set, so FLDM etc. are easy to deal with (we're only
6772 interested in 32 SP registers or 16 dp registers, due to the VFP version
6773 implemented by the chip in question). DP registers are marked by setting
6774 both SP registers in the write mask). */
6775
6776static enum bfd_arm_vfp11_pipe
6777bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 6778 int *numregs)
c7b8f16e 6779{
91d6fa6a 6780 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 6781 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
6782
6783 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
6784 {
6785 unsigned int pqrs;
6786 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
6787 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
6788
6789 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 6790 | ((insn & 0x00300000) >> 19)
6791 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 6792
6793 switch (pqrs)
99059e56
RM		 6794 {
6795 case 0: /* fmac[sd]. */
6796 case 1: /* fnmac[sd]. */
6797 case 2: /* fmsc[sd]. */
6798 case 3: /* fnmsc[sd]. */
6799 vpipe = VFP11_FMAC;
6800 bfd_arm_vfp11_write_mask (destmask, fd);
6801 regs[0] = fd;
6802 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
6803 regs[2] = fm;
6804 *numregs = 3;
6805 break;
6806
6807 case 4: /* fmul[sd]. */
6808 case 5: /* fnmul[sd]. */
6809 case 6: /* fadd[sd]. */
6810 case 7: /* fsub[sd]. */
6811 vpipe = VFP11_FMAC;
6812 goto vfp_binop;
6813
6814 case 8: /* fdiv[sd]. */
6815 vpipe = VFP11_DS;
6816 vfp_binop:
6817 bfd_arm_vfp11_write_mask (destmask, fd);
6818 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
6819 regs[1] = fm;
6820 *numregs = 2;
6821 break;
6822
6823 case 15: /* extended opcode. */
6824 {
6825 unsigned int extn = ((insn >> 15) & 0x1e)
6826 | ((insn >> 7) & 1);
6827
6828 switch (extn)
6829 {
6830 case 0: /* fcpy[sd]. */
6831 case 1: /* fabs[sd]. */
6832 case 2: /* fneg[sd]. */
6833 case 8: /* fcmp[sd]. */
6834 case 9: /* fcmpe[sd]. */
6835 case 10: /* fcmpz[sd]. */
6836 case 11: /* fcmpez[sd]. */
6837 case 16: /* fuito[sd]. */
6838 case 17: /* fsito[sd]. */
6839 case 24: /* ftoui[sd]. */
6840 case 25: /* ftouiz[sd]. */
6841 case 26: /* ftosi[sd]. */
6842 case 27: /* ftosiz[sd]. */
6843 /* These instructions will not bounce due to underflow. */
6844 *numregs = 0;
6845 vpipe = VFP11_FMAC;
6846 break;
6847
6848 case 3: /* fsqrt[sd]. */
6849 /* fsqrt cannot underflow, but it can (perhaps) overwrite
6850 registers to cause the erratum in previous instructions. */
6851 bfd_arm_vfp11_write_mask (destmask, fd);
6852 vpipe = VFP11_DS;
6853 break;
6854
6855 case 15: /* fcvt{ds,sd}. */
6856 {
6857 int rnum = 0;
6858
6859 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 6860
6861 /* Only FCVTSD can underflow. */
99059e56
RM		 6862 if ((insn & 0x100) != 0)
6863 regs[rnum++] = fm;
c7b8f16e 6864
99059e56 6865 *numregs = rnum;
c7b8f16e 6866
99059e56
RM		 6867 vpipe = VFP11_FMAC;
6868 }
6869 break;
c7b8f16e 6870
99059e56
RM		 6871 default:
6872 return VFP11_BAD;
6873 }
6874 }
6875 break;
c7b8f16e 6876
99059e56
RM		 6877 default:
6878 return VFP11_BAD;
6879 }
c7b8f16e
JB		 6880 }
6881 /* Two-register transfer. */
6882 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
6883 {
6884 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 6885
c7b8f16e
JB		 6886 if ((insn & 0x100000) == 0)
6887 {
99059e56
RM		 6888 if (is_double)
6889 bfd_arm_vfp11_write_mask (destmask, fm);
6890 else
6891 {
6892 bfd_arm_vfp11_write_mask (destmask, fm);
6893 bfd_arm_vfp11_write_mask (destmask, fm + 1);
6894 }
c7b8f16e
JB		 6895 }
6896
91d6fa6a 6897 vpipe = VFP11_LS;
c7b8f16e
JB		 6898 }
6899 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
6900 {
6901 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
6902 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 6903
c7b8f16e 6904 switch (puw)
99059e56
RM		 6905 {
6906 case 0: /* Two-reg transfer. We should catch these above. */
6907 abort ();
906e58ca 6908
99059e56
RM		 6909 case 2: /* fldm[sdx]. */
6910 case 3:
6911 case 5:
6912 {
6913 unsigned int i, offset = insn & 0xff;
c7b8f16e 6914
99059e56
RM		 6915 if (is_double)
6916 offset >>= 1;
c7b8f16e 6917
99059e56
RM		 6918 for (i = fd; i < fd + offset; i++)
6919 bfd_arm_vfp11_write_mask (destmask, i);
6920 }
6921 break;
906e58ca 6922
99059e56
RM		 6923 case 4: /* fld[sd]. */
6924 case 6:
6925 bfd_arm_vfp11_write_mask (destmask, fd);
6926 break;
906e58ca 6927
99059e56
RM		 6928 default:
6929 return VFP11_BAD;
6930 }
c7b8f16e 6931
91d6fa6a 6932 vpipe = VFP11_LS;
c7b8f16e
JB		 6933 }
6934 /* Single-register transfer. Note L==0. */
6935 else if ((insn & 0x0f100e10) == 0x0e000a10)
6936 {
6937 unsigned int opcode = (insn >> 21) & 7;
6938 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
6939
6940 switch (opcode)
99059e56
RM		 6941 {
6942 case 0: /* fmsr/fmdlr. */
6943 case 1: /* fmdhr. */
6944 /* Mark fmdhr and fmdlr as writing to the whole of the DP
6945 destination register. I don't know if this is exactly right,
6946 but it is the conservative choice. */
6947 bfd_arm_vfp11_write_mask (destmask, fn);
6948 break;
6949
6950 case 7: /* fmxr. */
6951 break;
6952 }
c7b8f16e 6953
91d6fa6a 6954 vpipe = VFP11_LS;
c7b8f16e
JB		 6955 }
6956
91d6fa6a 6957 return vpipe;
c7b8f16e
JB		 6958}
6959
6960
6961static int elf32_arm_compare_mapping (const void * a, const void * b);
6962
6963
6964/* Look for potentially-troublesome code sequences which might trigger the
6965 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
6966 (available from ARM) for details of the erratum. A short version is
6967 described in ld.texinfo. */
6968
6969bfd_boolean
6970bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
6971{
6972 asection *sec;
6973 bfd_byte *contents = NULL;
6974 int state = 0;
6975 int regs[3], numregs = 0;
6976 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
6977 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 6978
4dfe6ac6
NC		 6979 if (globals == NULL)
6980 return FALSE;
6981
c7b8f16e
JB		 6982 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
6983 The states transition as follows:
906e58ca 6984
c7b8f16e 6985 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 6986 A VFP FMAC-pipeline instruction has been seen. Fill
6987 regs[0]..regs[numregs-1] with its input operands. Remember this
6988 instruction in 'first_fmac'.
c7b8f16e
JB		 6989
6990 1 -> 2
99059e56
RM		 6991 Any instruction, except for a VFP instruction which overwrites
6992 regs[*].
906e58ca 6993
c7b8f16e
JB		 6994 1 -> 3 [ -> 0 ] or
6995 2 -> 3 [ -> 0 ]
99059e56
RM		 6996 A VFP instruction has been seen which overwrites any of regs[*].
6997 We must make a veneer! Reset state to 0 before examining next
6998 instruction.
906e58ca 6999
c7b8f16e 7000 2 -> 0
99059e56
RM		 7001 If we fail to match anything in state 2, reset to state 0 and reset
7002 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 7003
7004 If the VFP11 vector mode is in use, there must be at least two unrelated
7005 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 7006 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 7007
7008 /* If we are only performing a partial link do not bother
7009 to construct any glue. */
0e1862bb 7010 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 7011 return TRUE;
7012
0ffa91dd
NC		 7013 /* Skip if this bfd does not correspond to an ELF image. */
7014 if (! is_arm_elf (abfd))
7015 return TRUE;
906e58ca 7016
c7b8f16e
JB		 7017 /* We should have chosen a fix type by the time we get here. */
7018 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
7019
7020 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
7021 return TRUE;
2e6030b9 7022
33a7ffc2
JM		 7023 /* Skip this BFD if it corresponds to an executable or dynamic object. */
7024 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
7025 return TRUE;
7026
c7b8f16e
JB		 7027 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7028 {
7029 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
7030 struct _arm_elf_section_data *sec_data;
7031
7032 /* If we don't have executable progbits, we're not interested in this
99059e56 7033 section. Also skip if section is to be excluded. */
c7b8f16e 7034 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 7035 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
7036 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 7037 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 7038 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 7039 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
7040 continue;
c7b8f16e
JB		 7041
7042 sec_data = elf32_arm_section_data (sec);
906e58ca 7043
c7b8f16e 7044 if (sec_data->mapcount == 0)
99059e56 7045 continue;
906e58ca 7046
c7b8f16e
JB		 7047 if (elf_section_data (sec)->this_hdr.contents != NULL)
7048 contents = elf_section_data (sec)->this_hdr.contents;
7049 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
7050 goto error_return;
7051
7052 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
7053 elf32_arm_compare_mapping);
7054
7055 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 7056 {
7057 unsigned int span_start = sec_data->map[span].vma;
7058 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 7059 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 7060 char span_type = sec_data->map[span].type;
7061
7062 /* FIXME: Only ARM mode is supported at present. We may need to
7063 support Thumb-2 mode also at some point. */
7064 if (span_type != 'a')
7065 continue;
7066
7067 for (i = span_start; i < span_end;)
7068 {
7069 unsigned int next_i = i + 4;
7070 unsigned int insn = bfd_big_endian (abfd)
7071 ? (contents[i] << 24)
7072 | (contents[i + 1] << 16)
7073 | (contents[i + 2] << 8)
7074 | contents[i + 3]
7075 : (contents[i + 3] << 24)
7076 | (contents[i + 2] << 16)
7077 | (contents[i + 1] << 8)
7078 | contents[i];
7079 unsigned int writemask = 0;
7080 enum bfd_arm_vfp11_pipe vpipe;
7081
7082 switch (state)
7083 {
7084 case 0:
7085 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
7086 &numregs);
7087 /* I'm assuming the VFP11 erratum can trigger with denorm
7088 operands on either the FMAC or the DS pipeline. This might
7089 lead to slightly overenthusiastic veneer insertion. */
7090 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
7091 {
7092 state = use_vector ? 1 : 2;
7093 first_fmac = i;
7094 veneer_of_insn = insn;
7095 }
7096 break;
7097
7098 case 1:
7099 {
7100 int other_regs[3], other_numregs;
7101 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 7102 other_regs,
99059e56
RM		 7103 &other_numregs);
7104 if (vpipe != VFP11_BAD
7105 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 7106 numregs))
99059e56
RM		 7107 state = 3;
7108 else
7109 state = 2;
7110 }
7111 break;
7112
7113 case 2:
7114 {
7115 int other_regs[3], other_numregs;
7116 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 7117 other_regs,
99059e56
RM		 7118 &other_numregs);
7119 if (vpipe != VFP11_BAD
7120 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 7121 numregs))
99059e56
RM		 7122 state = 3;
7123 else
7124 {
7125 state = 0;
7126 next_i = first_fmac + 4;
7127 }
7128 }
7129 break;
7130
7131 case 3:
7132 abort (); /* Should be unreachable. */
7133 }
7134
7135 if (state == 3)
7136 {
7137 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
7138 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
7139
7140 elf32_arm_section_data (sec)->erratumcount += 1;
7141
7142 newerr->u.b.vfp_insn = veneer_of_insn;
7143
7144 switch (span_type)
7145 {
7146 case 'a':
7147 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
7148 break;
7149
7150 default:
7151 abort ();
7152 }
7153
7154 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 7155 first_fmac);
7156
99059e56 7157 newerr->vma = -1;
c7b8f16e 7158
99059e56
RM		 7159 newerr->next = sec_data->erratumlist;
7160 sec_data->erratumlist = newerr;
c7b8f16e 7161
99059e56
RM		 7162 state = 0;
7163 }
c7b8f16e 7164
99059e56
RM		 7165 i = next_i;
7166 }
7167 }
906e58ca 7168
c7b8f16e 7169 if (contents != NULL
99059e56
RM		 7170 && elf_section_data (sec)->this_hdr.contents != contents)
7171 free (contents);
c7b8f16e
JB		 7172 contents = NULL;
7173 }
7174
7175 return TRUE;
7176
7177error_return:
7178 if (contents != NULL
7179 && elf_section_data (sec)->this_hdr.contents != contents)
7180 free (contents);
906e58ca 7181
c7b8f16e
JB		 7182 return FALSE;
7183}
7184
7185/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
7186 after sections have been laid out, using specially-named symbols. */
7187
7188void
7189bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
7190 struct bfd_link_info *link_info)
7191{
7192 asection *sec;
7193 struct elf32_arm_link_hash_table *globals;
7194 char *tmp_name;
906e58ca 7195
0e1862bb 7196 if (bfd_link_relocatable (link_info))
c7b8f16e 7197 return;
2e6030b9
MS		 7198
7199 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 7200 if (! is_arm_elf (abfd))
2e6030b9
MS		 7201 return;
7202
c7b8f16e 7203 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7204 if (globals == NULL)
7205 return;
906e58ca 7206
21d799b5 7207 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7208 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 7209
7210 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7211 {
7212 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7213 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 7214
c7b8f16e 7215 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 7216 {
7217 struct elf_link_hash_entry *myh;
7218 bfd_vma vma;
7219
7220 switch (errnode->type)
7221 {
7222 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
7223 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
7224 /* Find veneer symbol. */
7225 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 7226 errnode->u.b.veneer->u.v.id);
7227
99059e56
RM		 7228 myh = elf_link_hash_lookup
7229 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 7230
a504d23a
LA		 7231 if (myh == NULL)
7232 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
7233 "`%s'"), abfd, tmp_name);
7234
7235 vma = myh->root.u.def.section->output_section->vma
7236 + myh->root.u.def.section->output_offset
7237 + myh->root.u.def.value;
7238
7239 errnode->u.b.veneer->vma = vma;
7240 break;
7241
7242 case VFP11_ERRATUM_ARM_VENEER:
7243 case VFP11_ERRATUM_THUMB_VENEER:
7244 /* Find return location. */
7245 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7246 errnode->u.v.id);
7247
7248 myh = elf_link_hash_lookup
7249 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7250
7251 if (myh == NULL)
7252 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
7253 "`%s'"), abfd, tmp_name);
7254
7255 vma = myh->root.u.def.section->output_section->vma
7256 + myh->root.u.def.section->output_offset
7257 + myh->root.u.def.value;
7258
7259 errnode->u.v.branch->vma = vma;
7260 break;
7261
7262 default:
7263 abort ();
7264 }
7265 }
7266 }
7267
7268 free (tmp_name);
7269}
7270
7271/* Find virtual-memory addresses for STM32L4XX erratum veneers and
7272 return locations after sections have been laid out, using
7273 specially-named symbols. */
7274
7275void
7276bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
7277 struct bfd_link_info *link_info)
7278{
7279 asection *sec;
7280 struct elf32_arm_link_hash_table *globals;
7281 char *tmp_name;
7282
7283 if (bfd_link_relocatable (link_info))
7284 return;
7285
7286 /* Skip if this bfd does not correspond to an ELF image. */
7287 if (! is_arm_elf (abfd))
7288 return;
7289
7290 globals = elf32_arm_hash_table (link_info);
7291 if (globals == NULL)
7292 return;
7293
7294 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7295 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7296
7297 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7298 {
7299 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7300 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
7301
7302 for (; errnode != NULL; errnode = errnode->next)
7303 {
7304 struct elf_link_hash_entry *myh;
7305 bfd_vma vma;
7306
7307 switch (errnode->type)
7308 {
7309 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
7310 /* Find veneer symbol. */
7311 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7312 errnode->u.b.veneer->u.v.id);
7313
7314 myh = elf_link_hash_lookup
7315 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7316
7317 if (myh == NULL)
7318 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
7319 "`%s'"), abfd, tmp_name);
7320
7321 vma = myh->root.u.def.section->output_section->vma
7322 + myh->root.u.def.section->output_offset
7323 + myh->root.u.def.value;
7324
7325 errnode->u.b.veneer->vma = vma;
7326 break;
7327
7328 case STM32L4XX_ERRATUM_VENEER:
7329 /* Find return location. */
7330 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7331 errnode->u.v.id);
7332
7333 myh = elf_link_hash_lookup
7334 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7335
7336 if (myh == NULL)
7337 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
7338 "`%s'"), abfd, tmp_name);
7339
7340 vma = myh->root.u.def.section->output_section->vma
7341 + myh->root.u.def.section->output_offset
7342 + myh->root.u.def.value;
7343
7344 errnode->u.v.branch->vma = vma;
7345 break;
7346
7347 default:
7348 abort ();
7349 }
7350 }
7351 }
7352
7353 free (tmp_name);
7354}
7355
7356static inline bfd_boolean
7357is_thumb2_ldmia (const insn32 insn)
7358{
7359 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
7360 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
7361 return (insn & 0xffd02000) == 0xe8900000;
7362}
7363
7364static inline bfd_boolean
7365is_thumb2_ldmdb (const insn32 insn)
7366{
7367 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
7368 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
7369 return (insn & 0xffd02000) == 0xe9100000;
7370}
7371
7372static inline bfd_boolean
7373is_thumb2_vldm (const insn32 insn)
7374{
7375 /* A6.5 Extension register load or store instruction
7376 A7.7.229
7377 We look only for the 32-bit registers case since the DP (64-bit
7378 registers) are not supported for STM32L4XX
7379 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
7380 <list> is consecutive 32-bit registers
7381 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
7382 if P==0 && U==1 && W==1 && Rn=1101 VPOP
7383 if PUW=010 || PUW=011 || PUW=101 VLDM. */
7384 return
7385 ((insn & 0xfe100f00) == 0xec100a00)
7386 && /* (IA without !). */
7387 (((((insn << 7) >> 28) & 0xd) == 0x4)
7388 /* (IA with !), includes VPOP (when reg number is SP). */
7389 || ((((insn << 7) >> 28) & 0xd) == 0x5)
7390 /* (DB with !). */
7391 || ((((insn << 7) >> 28) & 0xd) == 0x9));
7392}
7393
7394/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
7395 VLDM opcode and:
7396 - computes the number and the mode of memory accesses
7397 - decides if the replacement should be done:
7398 . replaces only if > 8-word accesses
7399 . or (testing purposes only) replaces all accesses. */
7400
7401static bfd_boolean
7402stm32l4xx_need_create_replacing_stub (const insn32 insn,
7403 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
7404{
7405 int nb_regs = 0;
7406
7407 /* The field encoding the register list is the same for both LDMIA
7408 and LDMDB encodings. */
7409 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
7410 nb_regs = popcount (insn & 0x0000ffff);
7411 else if (is_thumb2_vldm (insn))
7412 nb_regs = (insn & 0xff);
7413
7414 /* DEFAULT mode accounts for the real bug condition situation,
7415 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
7416 return
7417 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_regs > 8 :
7418 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
7419}
7420
7421/* Look for potentially-troublesome code sequences which might trigger
7422 the STM STM32L4XX erratum. */
7423
7424bfd_boolean
7425bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
7426 struct bfd_link_info *link_info)
7427{
7428 asection *sec;
7429 bfd_byte *contents = NULL;
7430 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7431
7432 if (globals == NULL)
7433 return FALSE;
7434
7435 /* If we are only performing a partial link do not bother
7436 to construct any glue. */
7437 if (bfd_link_relocatable (link_info))
7438 return TRUE;
7439
7440 /* Skip if this bfd does not correspond to an ELF image. */
7441 if (! is_arm_elf (abfd))
7442 return TRUE;
7443
7444 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
7445 return TRUE;
7446
7447 /* Skip this BFD if it corresponds to an executable or dynamic object. */
7448 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
7449 return TRUE;
7450
7451 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7452 {
7453 unsigned int i, span;
7454 struct _arm_elf_section_data *sec_data;
7455
7456 /* If we don't have executable progbits, we're not interested in this
7457 section. Also skip if section is to be excluded. */
7458 if (elf_section_type (sec) != SHT_PROGBITS
7459 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
7460 || (sec->flags & SEC_EXCLUDE) != 0
7461 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
7462 || sec->output_section == bfd_abs_section_ptr
7463 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
7464 continue;
7465
7466 sec_data = elf32_arm_section_data (sec);
c7b8f16e 7467
a504d23a
LA		 7468 if (sec_data->mapcount == 0)
7469 continue;
c7b8f16e 7470
a504d23a
LA		 7471 if (elf_section_data (sec)->this_hdr.contents != NULL)
7472 contents = elf_section_data (sec)->this_hdr.contents;
7473 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
7474 goto error_return;
c7b8f16e 7475
a504d23a
LA		 7476 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
7477 elf32_arm_compare_mapping);
c7b8f16e 7478
a504d23a
LA		 7479 for (span = 0; span < sec_data->mapcount; span++)
7480 {
7481 unsigned int span_start = sec_data->map[span].vma;
7482 unsigned int span_end = (span == sec_data->mapcount - 1)
7483 ? sec->size : sec_data->map[span + 1].vma;
7484 char span_type = sec_data->map[span].type;
7485 int itblock_current_pos = 0;
c7b8f16e 7486
a504d23a
LA		 7487 /* Only Thumb2 mode need be supported with this CM4 specific
7488 code, we should not encounter any arm mode eg span_type
7489 != 'a'. */
7490 if (span_type != 't')
7491 continue;
c7b8f16e 7492
a504d23a
LA		 7493 for (i = span_start; i < span_end;)
7494 {
7495 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
7496 bfd_boolean insn_32bit = FALSE;
7497 bfd_boolean is_ldm = FALSE;
7498 bfd_boolean is_vldm = FALSE;
7499 bfd_boolean is_not_last_in_it_block = FALSE;
7500
7501 /* The first 16-bits of all 32-bit thumb2 instructions start
7502 with opcode[15..13]=0b111 and the encoded op1 can be anything
7503 except opcode[12..11]!=0b00.
7504 See 32-bit Thumb instruction encoding. */
7505 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
7506 insn_32bit = TRUE;
c7b8f16e 7507
a504d23a
LA		 7508 /* Compute the predicate that tells if the instruction
7509 is concerned by the IT block
7510 - Creates an error if there is a ldm that is not
7511 last in the IT block thus cannot be replaced
7512 - Otherwise we can create a branch at the end of the
7513 IT block, it will be controlled naturally by IT
7514 with the proper pseudo-predicate
7515 - So the only interesting predicate is the one that
7516 tells that we are not on the last item of an IT
7517 block. */
7518 if (itblock_current_pos != 0)
7519 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 7520
a504d23a
LA		 7521 if (insn_32bit)
7522 {
7523 /* Load the rest of the insn (in manual-friendly order). */
7524 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
7525 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
7526 is_vldm = is_thumb2_vldm (insn);
7527
7528 /* Veneers are created for (v)ldm depending on
7529 option flags and memory accesses conditions; but
7530 if the instruction is not the last instruction of
7531 an IT block, we cannot create a jump there, so we
7532 bail out. */
7533 if ((is_ldm || is_vldm) &&
7534 stm32l4xx_need_create_replacing_stub
7535 (insn, globals->stm32l4xx_fix))
7536 {
7537 if (is_not_last_in_it_block)
7538 {
7539 (*_bfd_error_handler)
7540 /* Note - overlong line used here to allow for translation. */
7541 (_("\
7542%B(%A+0x%lx): error: multiple load detected in non-last IT block instruction : STM32L4XX veneer cannot be generated.\n"
7543 "Use gcc option -mrestrict-it to generate only one instruction per IT block.\n"),
7544 abfd, sec, (long)i);
7545 }
7546 else
7547 {
7548 elf32_stm32l4xx_erratum_list *newerr =
7549 (elf32_stm32l4xx_erratum_list *)
7550 bfd_zmalloc
7551 (sizeof (elf32_stm32l4xx_erratum_list));
7552
7553 elf32_arm_section_data (sec)
7554 ->stm32l4xx_erratumcount += 1;
7555 newerr->u.b.insn = insn;
7556 /* We create only thumb branches. */
7557 newerr->type =
7558 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
7559 record_stm32l4xx_erratum_veneer
7560 (link_info, newerr, abfd, sec,
7561 i,
7562 is_ldm ?
7563 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
7564 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
7565 newerr->vma = -1;
7566 newerr->next = sec_data->stm32l4xx_erratumlist;
7567 sec_data->stm32l4xx_erratumlist = newerr;
7568 }
7569 }
7570 }
7571 else
7572 {
7573 /* A7.7.37 IT p208
7574 IT blocks are only encoded in T1
7575 Encoding T1: IT{x{y{z}}} <firstcond>
7576 1 0 1 1 - 1 1 1 1 - firstcond - mask
7577 if mask = '0000' then see 'related encodings'
7578 We don't deal with UNPREDICTABLE, just ignore these.
7579 There can be no nested IT blocks so an IT block
7580 is naturally a new one for which it is worth
7581 computing its size. */
7582 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00) &&
7583 ((insn & 0x000f) != 0x0000);
7584 /* If we have a new IT block we compute its size. */
7585 if (is_newitblock)
7586 {
7587 /* Compute the number of instructions controlled
7588 by the IT block, it will be used to decide
7589 whether we are inside an IT block or not. */
7590 unsigned int mask = insn & 0x000f;
7591 itblock_current_pos = 4 - ctz (mask);
7592 }
7593 }
7594
7595 i += insn_32bit ? 4 : 2;
99059e56
RM		 7596 }
7597 }
a504d23a
LA		 7598
7599 if (contents != NULL
7600 && elf_section_data (sec)->this_hdr.contents != contents)
7601 free (contents);
7602 contents = NULL;
c7b8f16e 7603 }
906e58ca 7604
a504d23a
LA		 7605 return TRUE;
7606
7607error_return:
7608 if (contents != NULL
7609 && elf_section_data (sec)->this_hdr.contents != contents)
7610 free (contents);
c7b8f16e 7611
a504d23a
LA		 7612 return FALSE;
7613}
c7b8f16e 7614
eb043451
PB		 7615/* Set target relocation values needed during linking. */
7616
7617void
bf21ed78
MS		 7618bfd_elf32_arm_set_target_relocs (struct bfd *output_bfd,
7619 struct bfd_link_info *link_info,
eb043451 7620 int target1_is_rel,
319850b4 7621 char * target2_type,
99059e56 7622 int fix_v4bx,
c7b8f16e 7623 int use_blx,
99059e56 7624 bfd_arm_vfp11_fix vfp11_fix,
a504d23a 7625 bfd_arm_stm32l4xx_fix stm32l4xx_fix,
a9dc9481 7626 int no_enum_warn, int no_wchar_warn,
2de70689
MGD		 7627 int pic_veneer, int fix_cortex_a8,
7628 int fix_arm1176)
eb043451
PB		 7629{
7630 struct elf32_arm_link_hash_table *globals;
7631
7632 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7633 if (globals == NULL)
7634 return;
eb043451
PB		 7635
7636 globals->target1_is_rel = target1_is_rel;
7637 if (strcmp (target2_type, "rel") == 0)
7638 globals->target2_reloc = R_ARM_REL32;
eeac373a
PB		 7639 else if (strcmp (target2_type, "abs") == 0)
7640 globals->target2_reloc = R_ARM_ABS32;
eb043451
PB		 7641 else if (strcmp (target2_type, "got-rel") == 0)
7642 globals->target2_reloc = R_ARM_GOT_PREL;
7643 else
7644 {
7645 _bfd_error_handler (_("Invalid TARGET2 relocation type '%s'."),
7646 target2_type);
7647 }
319850b4 7648 globals->fix_v4bx = fix_v4bx;
33bfe774 7649 globals->use_blx |= use_blx;
c7b8f16e 7650 globals->vfp11_fix = vfp11_fix;
a504d23a 7651 globals->stm32l4xx_fix = stm32l4xx_fix;
27e55c4d 7652 globals->pic_veneer = pic_veneer;
48229727 7653 globals->fix_cortex_a8 = fix_cortex_a8;
2de70689 7654 globals->fix_arm1176 = fix_arm1176;
bf21ed78 7655
0ffa91dd
NC		 7656 BFD_ASSERT (is_arm_elf (output_bfd));
7657 elf_arm_tdata (output_bfd)->no_enum_size_warning = no_enum_warn;
a9dc9481 7658 elf_arm_tdata (output_bfd)->no_wchar_size_warning = no_wchar_warn;
eb043451 7659}
eb043451 7660
12a0a0fd 7661/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 7662
12a0a0fd
PB		 7663static void
7664insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
7665{
7666 bfd_vma upper;
7667 bfd_vma lower;
7668 int reloc_sign;
7669
7670 BFD_ASSERT ((offset & 1) == 0);
7671
7672 upper = bfd_get_16 (abfd, insn);
7673 lower = bfd_get_16 (abfd, insn + 2);
7674 reloc_sign = (offset < 0) ? 1 : 0;
7675 upper = (upper & ~(bfd_vma) 0x7ff)
7676 | ((offset >> 12) & 0x3ff)
7677 | (reloc_sign << 10);
906e58ca 7678 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 7679 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
7680 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
7681 | ((offset >> 1) & 0x7ff);
7682 bfd_put_16 (abfd, upper, insn);
7683 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 7684}
7685
9b485d32
NC		 7686/* Thumb code calling an ARM function. */
7687
252b5132 7688static int
57e8b36a
NC		 7689elf32_thumb_to_arm_stub (struct bfd_link_info * info,
7690 const char * name,
7691 bfd * input_bfd,
7692 bfd * output_bfd,
7693 asection * input_section,
7694 bfd_byte * hit_data,
7695 asection * sym_sec,
7696 bfd_vma offset,
7697 bfd_signed_vma addend,
f2a9dd69
DJ		 7698 bfd_vma val,
7699 char **error_message)
252b5132 7700{
bcbdc74c 7701 asection * s = 0;
dc810e39 7702 bfd_vma my_offset;
252b5132 7703 long int ret_offset;
bcbdc74c
NC		 7704 struct elf_link_hash_entry * myh;
7705 struct elf32_arm_link_hash_table * globals;
252b5132 7706
f2a9dd69 7707 myh = find_thumb_glue (info, name, error_message);
252b5132 7708 if (myh == NULL)
b34976b6 7709 return FALSE;
252b5132
RH		 7710
7711 globals = elf32_arm_hash_table (info);
252b5132
RH		 7712 BFD_ASSERT (globals != NULL);
7713 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7714
7715 my_offset = myh->root.u.def.value;
7716
3d4d4302
AM		 7717 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
7718 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 7719
7720 BFD_ASSERT (s != NULL);
7721 BFD_ASSERT (s->contents != NULL);
7722 BFD_ASSERT (s->output_section != NULL);
7723
7724 if ((my_offset & 0x01) == 0x01)
7725 {
7726 if (sym_sec != NULL
7727 && sym_sec->owner != NULL
7728 && !INTERWORK_FLAG (sym_sec->owner))
7729 {
8f615d07 7730 (*_bfd_error_handler)
d003868e 7731 (_("%B(%s): warning: interworking not enabled.\n"
3aaeb7d3 7732 " first occurrence: %B: Thumb call to ARM"),
d003868e 7733 sym_sec->owner, input_bfd, name);
252b5132 7734
b34976b6 7735 return FALSE;
252b5132
RH		 7736 }
7737
7738 --my_offset;
7739 myh->root.u.def.value = my_offset;
7740
52ab56c2
PB		 7741 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
7742 s->contents + my_offset);
252b5132 7743
52ab56c2
PB		 7744 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
7745 s->contents + my_offset + 2);
252b5132
RH		 7746
7747 ret_offset =
9b485d32
NC		 7748 /* Address of destination of the stub. */
7749 ((bfd_signed_vma) val)
252b5132 7750 - ((bfd_signed_vma)
57e8b36a
NC		 7751 /* Offset from the start of the current section
7752 to the start of the stubs. */
9b485d32
NC		 7753 (s->output_offset
7754 /* Offset of the start of this stub from the start of the stubs. */
7755 + my_offset
7756 /* Address of the start of the current section. */
7757 + s->output_section->vma)
7758 /* The branch instruction is 4 bytes into the stub. */
7759 + 4
7760 /* ARM branches work from the pc of the instruction + 8. */
7761 + 8);
252b5132 7762
52ab56c2
PB		 7763 put_arm_insn (globals, output_bfd,
7764 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
7765 s->contents + my_offset + 4);
252b5132
RH		 7766 }
7767
7768 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
7769
427bfd90
NC		 7770 /* Now go back and fix up the original BL insn to point to here. */
7771 ret_offset =
7772 /* Address of where the stub is located. */
7773 (s->output_section->vma + s->output_offset + my_offset)
7774 /* Address of where the BL is located. */
57e8b36a
NC		 7775 - (input_section->output_section->vma + input_section->output_offset
7776 + offset)
427bfd90
NC		 7777 /* Addend in the relocation. */
7778 - addend
7779 /* Biassing for PC-relative addressing. */
7780 - 8;
252b5132 7781
12a0a0fd 7782 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 7783
b34976b6 7784 return TRUE;
252b5132
RH		 7785}
7786
a4fd1a8e 7787/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 7788
a4fd1a8e
PB		 7789static struct elf_link_hash_entry *
7790elf32_arm_create_thumb_stub (struct bfd_link_info * info,
7791 const char * name,
7792 bfd * input_bfd,
7793 bfd * output_bfd,
7794 asection * sym_sec,
7795 bfd_vma val,
8029a119
NC		 7796 asection * s,
7797 char ** error_message)
252b5132 7798{
dc810e39 7799 bfd_vma my_offset;
252b5132 7800 long int ret_offset;
bcbdc74c
NC		 7801 struct elf_link_hash_entry * myh;
7802 struct elf32_arm_link_hash_table * globals;
252b5132 7803
f2a9dd69 7804 myh = find_arm_glue (info, name, error_message);
252b5132 7805 if (myh == NULL)
a4fd1a8e 7806 return NULL;
252b5132
RH		 7807
7808 globals = elf32_arm_hash_table (info);
252b5132
RH		 7809 BFD_ASSERT (globals != NULL);
7810 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7811
7812 my_offset = myh->root.u.def.value;
252b5132
RH		 7813
7814 if ((my_offset & 0x01) == 0x01)
7815 {
7816 if (sym_sec != NULL
7817 && sym_sec->owner != NULL
7818 && !INTERWORK_FLAG (sym_sec->owner))
7819 {
8f615d07 7820 (*_bfd_error_handler)
d003868e
AM		 7821 (_("%B(%s): warning: interworking not enabled.\n"
7822 " first occurrence: %B: arm call to thumb"),
7823 sym_sec->owner, input_bfd, name);
252b5132 7824 }
9b485d32 7825
252b5132
RH		 7826 --my_offset;
7827 myh->root.u.def.value = my_offset;
7828
0e1862bb
L		 7829 if (bfd_link_pic (info)
7830 || globals->root.is_relocatable_executable
27e55c4d 7831 || globals->pic_veneer)
8f6277f5
PB		 7832 {
7833 /* For relocatable objects we can't use absolute addresses,
7834 so construct the address from a relative offset. */
7835 /* TODO: If the offset is small it's probably worth
7836 constructing the address with adds. */
52ab56c2
PB		 7837 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
7838 s->contents + my_offset);
7839 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
7840 s->contents + my_offset + 4);
7841 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
7842 s->contents + my_offset + 8);
8f6277f5
PB		 7843 /* Adjust the offset by 4 for the position of the add,
7844 and 8 for the pipeline offset. */
7845 ret_offset = (val - (s->output_offset
7846 + s->output_section->vma
7847 + my_offset + 12))
7848 | 1;
7849 bfd_put_32 (output_bfd, ret_offset,
7850 s->contents + my_offset + 12);
7851 }
26079076
PB		 7852 else if (globals->use_blx)
7853 {
7854 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
7855 s->contents + my_offset);
7856
7857 /* It's a thumb address. Add the low order bit. */
7858 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
7859 s->contents + my_offset + 4);
7860 }
8f6277f5
PB		 7861 else
7862 {
52ab56c2
PB		 7863 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
7864 s->contents + my_offset);
252b5132 7865
52ab56c2
PB		 7866 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
7867 s->contents + my_offset + 4);
252b5132 7868
8f6277f5
PB		 7869 /* It's a thumb address. Add the low order bit. */
7870 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
7871 s->contents + my_offset + 8);
8029a119
NC		 7872
7873 my_offset += 12;
8f6277f5 7874 }
252b5132
RH		 7875 }
7876
7877 BFD_ASSERT (my_offset <= globals->arm_glue_size);
7878
a4fd1a8e
PB		 7879 return myh;
7880}
7881
7882/* Arm code calling a Thumb function. */
7883
7884static int
7885elf32_arm_to_thumb_stub (struct bfd_link_info * info,
7886 const char * name,
7887 bfd * input_bfd,
7888 bfd * output_bfd,
7889 asection * input_section,
7890 bfd_byte * hit_data,
7891 asection * sym_sec,
7892 bfd_vma offset,
7893 bfd_signed_vma addend,
f2a9dd69
DJ		 7894 bfd_vma val,
7895 char **error_message)
a4fd1a8e
PB		 7896{
7897 unsigned long int tmp;
7898 bfd_vma my_offset;
7899 asection * s;
7900 long int ret_offset;
7901 struct elf_link_hash_entry * myh;
7902 struct elf32_arm_link_hash_table * globals;
7903
7904 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 7905 BFD_ASSERT (globals != NULL);
7906 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7907
3d4d4302
AM		 7908 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
7909 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 7910 BFD_ASSERT (s != NULL);
7911 BFD_ASSERT (s->contents != NULL);
7912 BFD_ASSERT (s->output_section != NULL);
7913
7914 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 7915 sym_sec, val, s, error_message);
a4fd1a8e
PB		 7916 if (!myh)
7917 return FALSE;
7918
7919 my_offset = myh->root.u.def.value;
252b5132
RH		 7920 tmp = bfd_get_32 (input_bfd, hit_data);
7921 tmp = tmp & 0xFF000000;
7922
9b485d32 7923 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 7924 ret_offset = (s->output_offset
7925 + my_offset
7926 + s->output_section->vma
7927 - (input_section->output_offset
7928 + input_section->output_section->vma
7929 + offset + addend)
7930 - 8);
9a5aca8c 7931
252b5132
RH		 7932 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
7933
dc810e39 7934 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 7935
b34976b6 7936 return TRUE;
252b5132
RH		 7937}
7938
a4fd1a8e
PB		 7939/* Populate Arm stub for an exported Thumb function. */
7940
7941static bfd_boolean
7942elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
7943{
7944 struct bfd_link_info * info = (struct bfd_link_info *) inf;
7945 asection * s;
7946 struct elf_link_hash_entry * myh;
7947 struct elf32_arm_link_hash_entry *eh;
7948 struct elf32_arm_link_hash_table * globals;
7949 asection *sec;
7950 bfd_vma val;
f2a9dd69 7951 char *error_message;
a4fd1a8e 7952
906e58ca 7953 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 7954 /* Allocate stubs for exported Thumb functions on v4t. */
7955 if (eh->export_glue == NULL)
7956 return TRUE;
7957
7958 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 7959 BFD_ASSERT (globals != NULL);
7960 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7961
3d4d4302
AM		 7962 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
7963 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 7964 BFD_ASSERT (s != NULL);
7965 BFD_ASSERT (s->contents != NULL);
7966 BFD_ASSERT (s->output_section != NULL);
7967
7968 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 7969
7970 BFD_ASSERT (sec->output_section != NULL);
7971
a4fd1a8e
PB		 7972 val = eh->export_glue->root.u.def.value + sec->output_offset
7973 + sec->output_section->vma;
8029a119 7974
a4fd1a8e
PB		 7975 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
7976 h->root.u.def.section->owner,
f2a9dd69
DJ		 7977 globals->obfd, sec, val, s,
7978 &error_message);
a4fd1a8e
PB		 7979 BFD_ASSERT (myh);
7980 return TRUE;
7981}
7982
845b51d6
PB		 7983/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
7984
7985static bfd_vma
7986elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
7987{
7988 bfd_byte *p;
7989 bfd_vma glue_addr;
7990 asection *s;
7991 struct elf32_arm_link_hash_table *globals;
7992
7993 globals = elf32_arm_hash_table (info);
845b51d6
PB		 7994 BFD_ASSERT (globals != NULL);
7995 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7996
3d4d4302
AM		 7997 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
7998 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 7999 BFD_ASSERT (s != NULL);
8000 BFD_ASSERT (s->contents != NULL);
8001 BFD_ASSERT (s->output_section != NULL);
8002
8003 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
8004
8005 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
8006
8007 if ((globals->bx_glue_offset[reg] & 1) == 0)
8008 {
8009 p = s->contents + glue_addr;
8010 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
8011 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
8012 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
8013 globals->bx_glue_offset[reg] |= 1;
8014 }
8015
8016 return glue_addr + s->output_section->vma + s->output_offset;
8017}
8018
a4fd1a8e
PB		 8019/* Generate Arm stubs for exported Thumb symbols. */
8020static void
906e58ca 8021elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 8022 struct bfd_link_info *link_info)
8023{
8024 struct elf32_arm_link_hash_table * globals;
8025
8029a119
NC		 8026 if (link_info == NULL)
8027 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 8028 return;
8029
8030 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8031 if (globals == NULL)
8032 return;
8033
84c08195
PB		 8034 /* If blx is available then exported Thumb symbols are OK and there is
8035 nothing to do. */
a4fd1a8e
PB		 8036 if (globals->use_blx)
8037 return;
8038
8039 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
8040 link_info);
8041}
8042
47beaa6a
RS		 8043/* Reserve space for COUNT dynamic relocations in relocation selection
8044 SRELOC. */
8045
8046static void
8047elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
8048 bfd_size_type count)
8049{
8050 struct elf32_arm_link_hash_table *htab;
8051
8052 htab = elf32_arm_hash_table (info);
8053 BFD_ASSERT (htab->root.dynamic_sections_created);
8054 if (sreloc == NULL)
8055 abort ();
8056 sreloc->size += RELOC_SIZE (htab) * count;
8057}
8058
34e77a92
RS		 8059/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
8060 dynamic, the relocations should go in SRELOC, otherwise they should
8061 go in the special .rel.iplt section. */
8062
8063static void
8064elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
8065 bfd_size_type count)
8066{
8067 struct elf32_arm_link_hash_table *htab;
8068
8069 htab = elf32_arm_hash_table (info);
8070 if (!htab->root.dynamic_sections_created)
8071 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
8072 else
8073 {
8074 BFD_ASSERT (sreloc != NULL);
8075 sreloc->size += RELOC_SIZE (htab) * count;
8076 }
8077}
8078
47beaa6a
RS		 8079/* Add relocation REL to the end of relocation section SRELOC. */
8080
8081static void
8082elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
8083 asection *sreloc, Elf_Internal_Rela *rel)
8084{
8085 bfd_byte *loc;
8086 struct elf32_arm_link_hash_table *htab;
8087
8088 htab = elf32_arm_hash_table (info);
34e77a92
RS		 8089 if (!htab->root.dynamic_sections_created
8090 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
8091 sreloc = htab->root.irelplt;
47beaa6a
RS		 8092 if (sreloc == NULL)
8093 abort ();
8094 loc = sreloc->contents;
8095 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
8096 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
8097 abort ();
8098 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
8099}
8100
34e77a92
RS		 8101/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
8102 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
8103 to .plt. */
8104
8105static void
8106elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
8107 bfd_boolean is_iplt_entry,
8108 union gotplt_union *root_plt,
8109 struct arm_plt_info *arm_plt)
8110{
8111 struct elf32_arm_link_hash_table *htab;
8112 asection *splt;
8113 asection *sgotplt;
8114
8115 htab = elf32_arm_hash_table (info);
8116
8117 if (is_iplt_entry)
8118 {
8119 splt = htab->root.iplt;
8120 sgotplt = htab->root.igotplt;
8121
99059e56
RM		 8122 /* NaCl uses a special first entry in .iplt too. */
8123 if (htab->nacl_p && splt->size == 0)
8124 splt->size += htab->plt_header_size;
8125
34e77a92
RS		 8126 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
8127 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
8128 }
8129 else
8130 {
8131 splt = htab->root.splt;
8132 sgotplt = htab->root.sgotplt;
8133
8134 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
8135 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
8136
8137 /* If this is the first .plt entry, make room for the special
8138 first entry. */
8139 if (splt->size == 0)
8140 splt->size += htab->plt_header_size;
9f19ab6d
WN		 8141
8142 htab->next_tls_desc_index++;
34e77a92
RS		 8143 }
8144
8145 /* Allocate the PLT entry itself, including any leading Thumb stub. */
8146 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
8147 splt->size += PLT_THUMB_STUB_SIZE;
8148 root_plt->offset = splt->size;
8149 splt->size += htab->plt_entry_size;
8150
8151 if (!htab->symbian_p)
8152 {
8153 /* We also need to make an entry in the .got.plt section, which
8154 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 8155 if (is_iplt_entry)
8156 arm_plt->got_offset = sgotplt->size;
8157 else
8158 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 8159 sgotplt->size += 4;
8160 }
8161}
8162
b38cadfb
NC		 8163static bfd_vma
8164arm_movw_immediate (bfd_vma value)
8165{
8166 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
8167}
8168
8169static bfd_vma
8170arm_movt_immediate (bfd_vma value)
8171{
8172 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
8173}
8174
34e77a92
RS		 8175/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
8176 the entry lives in .iplt and resolves to (*SYM_VALUE)().
8177 Otherwise, DYNINDX is the index of the symbol in the dynamic
8178 symbol table and SYM_VALUE is undefined.
8179
8180 ROOT_PLT points to the offset of the PLT entry from the start of its
8181 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 8182 bookkeeping information.
34e77a92 8183
57460bcf
NC		 8184 Returns FALSE if there was a problem. */
8185
8186static bfd_boolean
34e77a92
RS		 8187elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
8188 union gotplt_union *root_plt,
8189 struct arm_plt_info *arm_plt,
8190 int dynindx, bfd_vma sym_value)
8191{
8192 struct elf32_arm_link_hash_table *htab;
8193 asection *sgot;
8194 asection *splt;
8195 asection *srel;
8196 bfd_byte *loc;
8197 bfd_vma plt_index;
8198 Elf_Internal_Rela rel;
8199 bfd_vma plt_header_size;
8200 bfd_vma got_header_size;
8201
8202 htab = elf32_arm_hash_table (info);
8203
8204 /* Pick the appropriate sections and sizes. */
8205 if (dynindx == -1)
8206 {
8207 splt = htab->root.iplt;
8208 sgot = htab->root.igotplt;
8209 srel = htab->root.irelplt;
8210
8211 /* There are no reserved entries in .igot.plt, and no special
8212 first entry in .iplt. */
8213 got_header_size = 0;
8214 plt_header_size = 0;
8215 }
8216 else
8217 {
8218 splt = htab->root.splt;
8219 sgot = htab->root.sgotplt;
8220 srel = htab->root.srelplt;
8221
8222 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
8223 plt_header_size = htab->plt_header_size;
8224 }
8225 BFD_ASSERT (splt != NULL && srel != NULL);
8226
8227 /* Fill in the entry in the procedure linkage table. */
8228 if (htab->symbian_p)
8229 {
8230 BFD_ASSERT (dynindx >= 0);
8231 put_arm_insn (htab, output_bfd,
8232 elf32_arm_symbian_plt_entry[0],
8233 splt->contents + root_plt->offset);
8234 bfd_put_32 (output_bfd,
8235 elf32_arm_symbian_plt_entry[1],
8236 splt->contents + root_plt->offset + 4);
8237
8238 /* Fill in the entry in the .rel.plt section. */
8239 rel.r_offset = (splt->output_section->vma
8240 + splt->output_offset
8241 + root_plt->offset + 4);
8242 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
8243
8244 /* Get the index in the procedure linkage table which
8245 corresponds to this symbol. This is the index of this symbol
8246 in all the symbols for which we are making plt entries. The
8247 first entry in the procedure linkage table is reserved. */
8248 plt_index = ((root_plt->offset - plt_header_size)
8249 / htab->plt_entry_size);
8250 }
8251 else
8252 {
8253 bfd_vma got_offset, got_address, plt_address;
8254 bfd_vma got_displacement, initial_got_entry;
8255 bfd_byte * ptr;
8256
8257 BFD_ASSERT (sgot != NULL);
8258
8259 /* Get the offset into the .(i)got.plt table of the entry that
8260 corresponds to this function. */
8261 got_offset = (arm_plt->got_offset & -2);
8262
8263 /* Get the index in the procedure linkage table which
8264 corresponds to this symbol. This is the index of this symbol
8265 in all the symbols for which we are making plt entries.
8266 After the reserved .got.plt entries, all symbols appear in
8267 the same order as in .plt. */
8268 plt_index = (got_offset - got_header_size) / 4;
8269
8270 /* Calculate the address of the GOT entry. */
8271 got_address = (sgot->output_section->vma
8272 + sgot->output_offset
8273 + got_offset);
8274
8275 /* ...and the address of the PLT entry. */
8276 plt_address = (splt->output_section->vma
8277 + splt->output_offset
8278 + root_plt->offset);
8279
8280 ptr = splt->contents + root_plt->offset;
0e1862bb 8281 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 8282 {
8283 unsigned int i;
8284 bfd_vma val;
8285
8286 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
8287 {
8288 val = elf32_arm_vxworks_shared_plt_entry[i];
8289 if (i == 2)
8290 val |= got_address - sgot->output_section->vma;
8291 if (i == 5)
8292 val |= plt_index * RELOC_SIZE (htab);
8293 if (i == 2 || i == 5)
8294 bfd_put_32 (output_bfd, val, ptr);
8295 else
8296 put_arm_insn (htab, output_bfd, val, ptr);
8297 }
8298 }
8299 else if (htab->vxworks_p)
8300 {
8301 unsigned int i;
8302 bfd_vma val;
8303
8304 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
8305 {
8306 val = elf32_arm_vxworks_exec_plt_entry[i];
8307 if (i == 2)
8308 val |= got_address;
8309 if (i == 4)
8310 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
8311 if (i == 5)
8312 val |= plt_index * RELOC_SIZE (htab);
8313 if (i == 2 || i == 5)
8314 bfd_put_32 (output_bfd, val, ptr);
8315 else
8316 put_arm_insn (htab, output_bfd, val, ptr);
8317 }
8318
8319 loc = (htab->srelplt2->contents
8320 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
8321
8322 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
8323 referencing the GOT for this PLT entry. */
8324 rel.r_offset = plt_address + 8;
8325 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
8326 rel.r_addend = got_offset;
8327 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8328 loc += RELOC_SIZE (htab);
8329
8330 /* Create the R_ARM_ABS32 relocation referencing the
8331 beginning of the PLT for this GOT entry. */
8332 rel.r_offset = got_address;
8333 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
8334 rel.r_addend = 0;
8335 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8336 }
b38cadfb
NC		 8337 else if (htab->nacl_p)
8338 {
8339 /* Calculate the displacement between the PLT slot and the
8340 common tail that's part of the special initial PLT slot. */
6034aab8 8341 int32_t tail_displacement
b38cadfb
NC		 8342 = ((splt->output_section->vma + splt->output_offset
8343 + ARM_NACL_PLT_TAIL_OFFSET)
8344 - (plt_address + htab->plt_entry_size + 4));
8345 BFD_ASSERT ((tail_displacement & 3) == 0);
8346 tail_displacement >>= 2;
8347
8348 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
8349 || (-tail_displacement & 0xff000000) == 0);
8350
8351 /* Calculate the displacement between the PLT slot and the entry
8352 in the GOT. The offset accounts for the value produced by
8353 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 8354 got_displacement = (got_address
99059e56 8355 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 8356
8357 /* NaCl does not support interworking at all. */
8358 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
8359
8360 put_arm_insn (htab, output_bfd,
8361 elf32_arm_nacl_plt_entry[0]
8362 | arm_movw_immediate (got_displacement),
8363 ptr + 0);
8364 put_arm_insn (htab, output_bfd,
8365 elf32_arm_nacl_plt_entry[1]
8366 | arm_movt_immediate (got_displacement),
8367 ptr + 4);
8368 put_arm_insn (htab, output_bfd,
8369 elf32_arm_nacl_plt_entry[2],
8370 ptr + 8);
8371 put_arm_insn (htab, output_bfd,
8372 elf32_arm_nacl_plt_entry[3]
8373 | (tail_displacement & 0x00ffffff),
8374 ptr + 12);
8375 }
57460bcf
NC		 8376 else if (using_thumb_only (htab))
8377 {
eed94f8f 8378 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 8379 if (!using_thumb2 (htab))
eed94f8f
NC		 8380 {
8381 /* FIXME: We ought to be able to generate thumb-1 PLT
8382 instructions... */
8383 _bfd_error_handler (_("%B: Warning: thumb-1 mode PLT generation not currently supported"),
8384 output_bfd);
8385 return FALSE;
8386 }
57460bcf 8387
eed94f8f
NC		 8388 /* Calculate the displacement between the PLT slot and the entry in
8389 the GOT. The 12-byte offset accounts for the value produced by
8390 adding to pc in the 3rd instruction of the PLT stub. */
8391 got_displacement = got_address - (plt_address + 12);
8392
8393 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
8394 instead of 'put_thumb_insn'. */
8395 put_arm_insn (htab, output_bfd,
8396 elf32_thumb2_plt_entry[0]
8397 | ((got_displacement & 0x000000ff) << 16)
8398 | ((got_displacement & 0x00000700) << 20)
8399 | ((got_displacement & 0x00000800) >> 1)
8400 | ((got_displacement & 0x0000f000) >> 12),
8401 ptr + 0);
8402 put_arm_insn (htab, output_bfd,
8403 elf32_thumb2_plt_entry[1]
8404 | ((got_displacement & 0x00ff0000) )
8405 | ((got_displacement & 0x07000000) << 4)
8406 | ((got_displacement & 0x08000000) >> 17)
8407 | ((got_displacement & 0xf0000000) >> 28),
8408 ptr + 4);
8409 put_arm_insn (htab, output_bfd,
8410 elf32_thumb2_plt_entry[2],
8411 ptr + 8);
8412 put_arm_insn (htab, output_bfd,
8413 elf32_thumb2_plt_entry[3],
8414 ptr + 12);
57460bcf 8415 }
34e77a92
RS		 8416 else
8417 {
8418 /* Calculate the displacement between the PLT slot and the
8419 entry in the GOT. The eight-byte offset accounts for the
8420 value produced by adding to pc in the first instruction
8421 of the PLT stub. */
8422 got_displacement = got_address - (plt_address + 8);
8423
34e77a92
RS		 8424 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
8425 {
8426 put_thumb_insn (htab, output_bfd,
8427 elf32_arm_plt_thumb_stub[0], ptr - 4);
8428 put_thumb_insn (htab, output_bfd,
8429 elf32_arm_plt_thumb_stub[1], ptr - 2);
8430 }
8431
1db37fe6
YG		 8432 if (!elf32_arm_use_long_plt_entry)
8433 {
8434 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
8435
8436 put_arm_insn (htab, output_bfd,
8437 elf32_arm_plt_entry_short[0]
8438 | ((got_displacement & 0x0ff00000) >> 20),
8439 ptr + 0);
8440 put_arm_insn (htab, output_bfd,
8441 elf32_arm_plt_entry_short[1]
8442 | ((got_displacement & 0x000ff000) >> 12),
8443 ptr+ 4);
8444 put_arm_insn (htab, output_bfd,
8445 elf32_arm_plt_entry_short[2]
8446 | (got_displacement & 0x00000fff),
8447 ptr + 8);
34e77a92 8448#ifdef FOUR_WORD_PLT
1db37fe6 8449 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 8450#endif
1db37fe6
YG		 8451 }
8452 else
8453 {
8454 put_arm_insn (htab, output_bfd,
8455 elf32_arm_plt_entry_long[0]
8456 | ((got_displacement & 0xf0000000) >> 28),
8457 ptr + 0);
8458 put_arm_insn (htab, output_bfd,
8459 elf32_arm_plt_entry_long[1]
8460 | ((got_displacement & 0x0ff00000) >> 20),
8461 ptr + 4);
8462 put_arm_insn (htab, output_bfd,
8463 elf32_arm_plt_entry_long[2]
8464 | ((got_displacement & 0x000ff000) >> 12),
8465 ptr+ 8);
8466 put_arm_insn (htab, output_bfd,
8467 elf32_arm_plt_entry_long[3]
8468 | (got_displacement & 0x00000fff),
8469 ptr + 12);
8470 }
34e77a92
RS		 8471 }
8472
8473 /* Fill in the entry in the .rel(a).(i)plt section. */
8474 rel.r_offset = got_address;
8475 rel.r_addend = 0;
8476 if (dynindx == -1)
8477 {
8478 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
8479 The dynamic linker or static executable then calls SYM_VALUE
8480 to determine the correct run-time value of the .igot.plt entry. */
8481 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
8482 initial_got_entry = sym_value;
8483 }
8484 else
8485 {
8486 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
8487 initial_got_entry = (splt->output_section->vma
8488 + splt->output_offset);
8489 }
8490
8491 /* Fill in the entry in the global offset table. */
8492 bfd_put_32 (output_bfd, initial_got_entry,
8493 sgot->contents + got_offset);
8494 }
8495
aba8c3de
WN		 8496 if (dynindx == -1)
8497 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
8498 else
8499 {
8500 loc = srel->contents + plt_index * RELOC_SIZE (htab);
8501 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8502 }
57460bcf
NC		 8503
8504 return TRUE;
34e77a92
RS		 8505}
8506
eb043451
PB		 8507/* Some relocations map to different relocations depending on the
8508 target. Return the real relocation. */
8029a119 8509
eb043451
PB		 8510static int
8511arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
8512 int r_type)
8513{
8514 switch (r_type)
8515 {
8516 case R_ARM_TARGET1:
8517 if (globals->target1_is_rel)
8518 return R_ARM_REL32;
8519 else
8520 return R_ARM_ABS32;
8521
8522 case R_ARM_TARGET2:
8523 return globals->target2_reloc;
8524
8525 default:
8526 return r_type;
8527 }
8528}
eb043451 8529
ba93b8ac
DJ		 8530/* Return the base VMA address which should be subtracted from real addresses
8531 when resolving @dtpoff relocation.
8532 This is PT_TLS segment p_vaddr. */
8533
8534static bfd_vma
8535dtpoff_base (struct bfd_link_info *info)
8536{
8537 /* If tls_sec is NULL, we should have signalled an error already. */
8538 if (elf_hash_table (info)->tls_sec == NULL)
8539 return 0;
8540 return elf_hash_table (info)->tls_sec->vma;
8541}
8542
8543/* Return the relocation value for @tpoff relocation
8544 if STT_TLS virtual address is ADDRESS. */
8545
8546static bfd_vma
8547tpoff (struct bfd_link_info *info, bfd_vma address)
8548{
8549 struct elf_link_hash_table *htab = elf_hash_table (info);
8550 bfd_vma base;
8551
8552 /* If tls_sec is NULL, we should have signalled an error already. */
8553 if (htab->tls_sec == NULL)
8554 return 0;
8555 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
8556 return address - htab->tls_sec->vma + base;
8557}
8558
00a97672
RS		 8559/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
8560 VALUE is the relocation value. */
8561
8562static bfd_reloc_status_type
8563elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
8564{
8565 if (value > 0xfff)
8566 return bfd_reloc_overflow;
8567
8568 value |= bfd_get_32 (abfd, data) & 0xfffff000;
8569 bfd_put_32 (abfd, value, data);
8570 return bfd_reloc_ok;
8571}
8572
0855e32b
NS		 8573/* Handle TLS relaxations. Relaxing is possible for symbols that use
8574 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
8575 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
8576
8577 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
8578 is to then call final_link_relocate. Return other values in the
62672b10
NS		 8579 case of error.
8580
8581 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
8582 the pre-relaxed code. It would be nice if the relocs were updated
8583 to match the optimization. */
0855e32b 8584
b38cadfb 8585static bfd_reloc_status_type
0855e32b 8586elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 8587 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 8588 Elf_Internal_Rela *rel, unsigned long is_local)
8589{
8590 unsigned long insn;
b38cadfb 8591
0855e32b
NS		 8592 switch (ELF32_R_TYPE (rel->r_info))
8593 {
8594 default:
8595 return bfd_reloc_notsupported;
b38cadfb 8596
0855e32b
NS		 8597 case R_ARM_TLS_GOTDESC:
8598 if (is_local)
8599 insn = 0;
8600 else
8601 {
8602 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
8603 if (insn & 1)
8604 insn -= 5; /* THUMB */
8605 else
8606 insn -= 8; /* ARM */
8607 }
8608 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
8609 return bfd_reloc_continue;
8610
8611 case R_ARM_THM_TLS_DESCSEQ:
8612 /* Thumb insn. */
8613 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
8614 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
8615 {
8616 if (is_local)
8617 /* nop */
8618 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8619 }
8620 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
8621 {
8622 if (is_local)
8623 /* nop */
8624 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8625 else
8626 /* ldr rx,[ry] */
8627 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
8628 }
8629 else if ((insn & 0xff87) == 0x4780) /* blx rx */
8630 {
8631 if (is_local)
8632 /* nop */
8633 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8634 else
8635 /* mov r0, rx */
8636 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
8637 contents + rel->r_offset);
8638 }
8639 else
8640 {
8641 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
8642 /* It's a 32 bit instruction, fetch the rest of it for
8643 error generation. */
8644 insn = (insn << 16)
8645 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
8646 (*_bfd_error_handler)
8647 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' in TLS trampoline"),
8648 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
8649 return bfd_reloc_notsupported;
8650 }
8651 break;
b38cadfb 8652
0855e32b
NS		 8653 case R_ARM_TLS_DESCSEQ:
8654 /* arm insn. */
8655 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
8656 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
8657 {
8658 if (is_local)
8659 /* mov rx, ry */
8660 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
8661 contents + rel->r_offset);
8662 }
8663 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
8664 {
8665 if (is_local)
8666 /* nop */
8667 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
8668 else
8669 /* ldr rx,[ry] */
8670 bfd_put_32 (input_bfd, insn & 0xfffff000,
8671 contents + rel->r_offset);
8672 }
8673 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
8674 {
8675 if (is_local)
8676 /* nop */
8677 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
8678 else
8679 /* mov r0, rx */
8680 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
8681 contents + rel->r_offset);
8682 }
8683 else
8684 {
8685 (*_bfd_error_handler)
8686 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' in TLS trampoline"),
8687 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
8688 return bfd_reloc_notsupported;
8689 }
8690 break;
8691
8692 case R_ARM_TLS_CALL:
8693 /* GD->IE relaxation, turn the instruction into 'nop' or
8694 'ldr r0, [pc,r0]' */
8695 insn = is_local ? 0xe1a00000 : 0xe79f0000;
8696 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
8697 break;
b38cadfb 8698
0855e32b 8699 case R_ARM_THM_TLS_CALL:
6a631e86 8700 /* GD->IE relaxation. */
0855e32b
NS		 8701 if (!is_local)
8702 /* add r0,pc; ldr r0, [r0] */
8703 insn = 0x44786800;
8704 else if (arch_has_thumb2_nop (globals))
8705 /* nop.w */
8706 insn = 0xf3af8000;
8707 else
8708 /* nop; nop */
8709 insn = 0xbf00bf00;
b38cadfb 8710
0855e32b
NS		 8711 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
8712 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
8713 break;
8714 }
8715 return bfd_reloc_ok;
8716}
8717
4962c51a
MS		 8718/* For a given value of n, calculate the value of G_n as required to
8719 deal with group relocations. We return it in the form of an
8720 encoded constant-and-rotation, together with the final residual. If n is
8721 specified as less than zero, then final_residual is filled with the
8722 input value and no further action is performed. */
8723
8724static bfd_vma
8725calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
8726{
8727 int current_n;
8728 bfd_vma g_n;
8729 bfd_vma encoded_g_n = 0;
8730 bfd_vma residual = value; /* Also known as Y_n. */
8731
8732 for (current_n = 0; current_n <= n; current_n++)
8733 {
8734 int shift;
8735
8736 /* Calculate which part of the value to mask. */
8737 if (residual == 0)
99059e56 8738 shift = 0;
4962c51a 8739 else
99059e56
RM		 8740 {
8741 int msb;
8742
8743 /* Determine the most significant bit in the residual and
8744 align the resulting value to a 2-bit boundary. */
8745 for (msb = 30; msb >= 0; msb -= 2)
8746 if (residual & (3 << msb))
8747 break;
8748
8749 /* The desired shift is now (msb - 6), or zero, whichever
8750 is the greater. */
8751 shift = msb - 6;
8752 if (shift < 0)
8753 shift = 0;
8754 }
4962c51a
MS		 8755
8756 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
8757 g_n = residual & (0xff << shift);
8758 encoded_g_n = (g_n >> shift)
99059e56 8759 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 8760
8761 /* Calculate the residual for the next time around. */
8762 residual &= ~g_n;
8763 }
8764
8765 *final_residual = residual;
8766
8767 return encoded_g_n;
8768}
8769
8770/* Given an ARM instruction, determine whether it is an ADD or a SUB.
8771 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 8772
4962c51a 8773static int
906e58ca 8774identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 8775{
8776 int opcode = insn & 0x1e00000;
8777
8778 if (opcode == 1 << 23) /* ADD */
8779 return 1;
8780
8781 if (opcode == 1 << 22) /* SUB */
8782 return -1;
8783
8784 return 0;
8785}
8786
252b5132 8787/* Perform a relocation as part of a final link. */
9b485d32 8788
252b5132 8789static bfd_reloc_status_type
57e8b36a
NC		 8790elf32_arm_final_link_relocate (reloc_howto_type * howto,
8791 bfd * input_bfd,
8792 bfd * output_bfd,
8793 asection * input_section,
8794 bfd_byte * contents,
8795 Elf_Internal_Rela * rel,
8796 bfd_vma value,
8797 struct bfd_link_info * info,
8798 asection * sym_sec,
8799 const char * sym_name,
34e77a92
RS		 8800 unsigned char st_type,
8801 enum arm_st_branch_type branch_type,
0945cdfd 8802 struct elf_link_hash_entry * h,
f2a9dd69 8803 bfd_boolean * unresolved_reloc_p,
8029a119 8804 char ** error_message)
252b5132
RH		 8805{
8806 unsigned long r_type = howto->type;
8807 unsigned long r_symndx;
8808 bfd_byte * hit_data = contents + rel->r_offset;
252b5132 8809 bfd_vma * local_got_offsets;
0855e32b 8810 bfd_vma * local_tlsdesc_gotents;
34e77a92
RS		 8811 asection * sgot;
8812 asection * splt;
252b5132 8813 asection * sreloc = NULL;
362d30a1 8814 asection * srelgot;
252b5132 8815 bfd_vma addend;
ba96a88f 8816 bfd_signed_vma signed_addend;
34e77a92
RS		 8817 unsigned char dynreloc_st_type;
8818 bfd_vma dynreloc_value;
ba96a88f 8819 struct elf32_arm_link_hash_table * globals;
34e77a92
RS		 8820 struct elf32_arm_link_hash_entry *eh;
8821 union gotplt_union *root_plt;
8822 struct arm_plt_info *arm_plt;
8823 bfd_vma plt_offset;
8824 bfd_vma gotplt_offset;
8825 bfd_boolean has_iplt_entry;
f21f3fe0 8826
9c504268 8827 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 8828 if (globals == NULL)
8829 return bfd_reloc_notsupported;
9c504268 8830
0ffa91dd
NC		 8831 BFD_ASSERT (is_arm_elf (input_bfd));
8832
8833 /* Some relocation types map to different relocations depending on the
9c504268 8834 target. We pick the right one here. */
eb043451 8835 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 8836
8837 /* It is possible to have linker relaxations on some TLS access
8838 models. Update our information here. */
8839 r_type = elf32_arm_tls_transition (info, r_type, h);
8840
eb043451
PB		 8841 if (r_type != howto->type)
8842 howto = elf32_arm_howto_from_type (r_type);
9c504268 8843
34e77a92 8844 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 8845 sgot = globals->root.sgot;
252b5132 8846 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 8847 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
8848
34e77a92
RS		 8849 if (globals->root.dynamic_sections_created)
8850 srelgot = globals->root.srelgot;
8851 else
8852 srelgot = NULL;
8853
252b5132
RH		 8854 r_symndx = ELF32_R_SYM (rel->r_info);
8855
4e7fd91e 8856 if (globals->use_rel)
ba96a88f 8857 {
4e7fd91e
PB		 8858 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
8859
8860 if (addend & ((howto->src_mask + 1) >> 1))
8861 {
8862 signed_addend = -1;
8863 signed_addend &= ~ howto->src_mask;
8864 signed_addend |= addend;
8865 }
8866 else
8867 signed_addend = addend;
ba96a88f
NC		 8868 }
8869 else
4e7fd91e 8870 addend = signed_addend = rel->r_addend;
f21f3fe0 8871
39f21624
NC		 8872 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
8873 are resolving a function call relocation. */
8874 if (using_thumb_only (globals)
8875 && (r_type == R_ARM_THM_CALL
8876 || r_type == R_ARM_THM_JUMP24)
8877 && branch_type == ST_BRANCH_TO_ARM)
8878 branch_type = ST_BRANCH_TO_THUMB;
8879
34e77a92
RS		 8880 /* Record the symbol information that should be used in dynamic
8881 relocations. */
8882 dynreloc_st_type = st_type;
8883 dynreloc_value = value;
8884 if (branch_type == ST_BRANCH_TO_THUMB)
8885 dynreloc_value |= 1;
8886
8887 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
8888 VALUE appropriately for relocations that we resolve at link time. */
8889 has_iplt_entry = FALSE;
8890 if (elf32_arm_get_plt_info (input_bfd, eh, r_symndx, &root_plt, &arm_plt)
8891 && root_plt->offset != (bfd_vma) -1)
8892 {
8893 plt_offset = root_plt->offset;
8894 gotplt_offset = arm_plt->got_offset;
8895
8896 if (h == NULL || eh->is_iplt)
8897 {
8898 has_iplt_entry = TRUE;
8899 splt = globals->root.iplt;
8900
8901 /* Populate .iplt entries here, because not all of them will
8902 be seen by finish_dynamic_symbol. The lower bit is set if
8903 we have already populated the entry. */
8904 if (plt_offset & 1)
8905 plt_offset--;
8906 else
8907 {
57460bcf
NC		 8908 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
8909 -1, dynreloc_value))
8910 root_plt->offset |= 1;
8911 else
8912 return bfd_reloc_notsupported;
34e77a92
RS		 8913 }
8914
8915 /* Static relocations always resolve to the .iplt entry. */
8916 st_type = STT_FUNC;
8917 value = (splt->output_section->vma
8918 + splt->output_offset
8919 + plt_offset);
8920 branch_type = ST_BRANCH_TO_ARM;
8921
8922 /* If there are non-call relocations that resolve to the .iplt
8923 entry, then all dynamic ones must too. */
8924 if (arm_plt->noncall_refcount != 0)
8925 {
8926 dynreloc_st_type = st_type;
8927 dynreloc_value = value;
8928 }
8929 }
8930 else
8931 /* We populate the .plt entry in finish_dynamic_symbol. */
8932 splt = globals->root.splt;
8933 }
8934 else
8935 {
8936 splt = NULL;
8937 plt_offset = (bfd_vma) -1;
8938 gotplt_offset = (bfd_vma) -1;
8939 }
8940
252b5132
RH		 8941 switch (r_type)
8942 {
8943 case R_ARM_NONE:
28a094c2
DJ		 8944 /* We don't need to find a value for this symbol. It's just a
8945 marker. */
8946 *unresolved_reloc_p = FALSE;
252b5132
RH		 8947 return bfd_reloc_ok;
8948
00a97672
RS		 8949 case R_ARM_ABS12:
8950 if (!globals->vxworks_p)
8951 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
8952
252b5132
RH		 8953 case R_ARM_PC24:
8954 case R_ARM_ABS32:
bb224fc3 8955 case R_ARM_ABS32_NOI:
252b5132 8956 case R_ARM_REL32:
bb224fc3 8957 case R_ARM_REL32_NOI:
5b5bb741
PB		 8958 case R_ARM_CALL:
8959 case R_ARM_JUMP24:
dfc5f959 8960 case R_ARM_XPC25:
eb043451 8961 case R_ARM_PREL31:
7359ea65 8962 case R_ARM_PLT32:
7359ea65
DJ		 8963 /* Handle relocations which should use the PLT entry. ABS32/REL32
8964 will use the symbol's value, which may point to a PLT entry, but we
8965 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 8966 branches in this object should go to it, except if the PLT is too
8967 far away, in which case a long branch stub should be inserted. */
bb224fc3 8968 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 8969 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 8970 && r_type != R_ARM_CALL
8971 && r_type != R_ARM_JUMP24
8972 && r_type != R_ARM_PLT32)
34e77a92 8973 && plt_offset != (bfd_vma) -1)
7359ea65 8974 {
34e77a92
RS		 8975 /* If we've created a .plt section, and assigned a PLT entry
8976 to this function, it must either be a STT_GNU_IFUNC reference
8977 or not be known to bind locally. In other cases, we should
8978 have cleared the PLT entry by now. */
8979 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 8980
8981 value = (splt->output_section->vma
8982 + splt->output_offset
34e77a92 8983 + plt_offset);
0945cdfd 8984 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 8985 return _bfd_final_link_relocate (howto, input_bfd, input_section,
8986 contents, rel->r_offset, value,
00a97672 8987 rel->r_addend);
7359ea65
DJ		 8988 }
8989
67687978
PB		 8990 /* When generating a shared object or relocatable executable, these
8991 relocations are copied into the output file to be resolved at
8992 run time. */
0e1862bb
L		 8993 if ((bfd_link_pic (info)
8994 || globals->root.is_relocatable_executable)
7359ea65 8995 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 8996 && !(globals->vxworks_p
3348747a
NS		 8997 && strcmp (input_section->output_section->name,
8998 ".tls_vars") == 0)
bb224fc3 8999 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 9000 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 9001 && !(input_bfd == globals->stub_bfd
9002 && strstr (input_section->name, STUB_SUFFIX))
7359ea65
DJ		 9003 && (h == NULL
9004 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
9005 || h->root.type != bfd_link_hash_undefweak)
9006 && r_type != R_ARM_PC24
5b5bb741
PB		 9007 && r_type != R_ARM_CALL
9008 && r_type != R_ARM_JUMP24
ee06dc07 9009 && r_type != R_ARM_PREL31
7359ea65 9010 && r_type != R_ARM_PLT32)
252b5132 9011 {
947216bf 9012 Elf_Internal_Rela outrel;
b34976b6 9013 bfd_boolean skip, relocate;
f21f3fe0 9014
52db4ec2
JW		 9015 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
9016 && !h->def_regular)
9017 {
9018 char *v = _("shared object");
9019
0e1862bb 9020 if (bfd_link_executable (info))
52db4ec2
JW		 9021 v = _("PIE executable");
9022
9023 (*_bfd_error_handler)
9024 (_("%B: relocation %s against external or undefined symbol `%s'"
9025 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
9026 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
9027 return bfd_reloc_notsupported;
9028 }
9029
0945cdfd
DJ		 9030 *unresolved_reloc_p = FALSE;
9031
34e77a92 9032 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 9033 {
83bac4b0
NC		 9034 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
9035 ! globals->use_rel);
f21f3fe0 9036
83bac4b0 9037 if (sreloc == NULL)
252b5132 9038 return bfd_reloc_notsupported;
252b5132 9039 }
f21f3fe0 9040
b34976b6
AM		 9041 skip = FALSE;
9042 relocate = FALSE;
f21f3fe0 9043
00a97672 9044 outrel.r_addend = addend;
c629eae0
JJ		 9045 outrel.r_offset =
9046 _bfd_elf_section_offset (output_bfd, info, input_section,
9047 rel->r_offset);
9048 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 9049 skip = TRUE;
0bb2d96a 9050 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 9051 skip = TRUE, relocate = TRUE;
252b5132
RH		 9052 outrel.r_offset += (input_section->output_section->vma
9053 + input_section->output_offset);
f21f3fe0 9054
252b5132 9055 if (skip)
0bb2d96a 9056 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 9057 else if (h != NULL
9058 && h->dynindx != -1
0e1862bb 9059 && (!bfd_link_pic (info)
a496fbc8 9060 || !SYMBOLIC_BIND (info, h)
f5385ebf 9061 || !h->def_regular))
5e681ec4 9062 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 9063 else
9064 {
a16385dc
MM		 9065 int symbol;
9066
5e681ec4 9067 /* This symbol is local, or marked to become local. */
34e77a92 9068 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 9069 if (globals->symbian_p)
6366ff1e 9070 {
74541ad4
AM		 9071 asection *osec;
9072
6366ff1e
MM		 9073 /* On Symbian OS, the data segment and text segement
9074 can be relocated independently. Therefore, we
9075 must indicate the segment to which this
9076 relocation is relative. The BPABI allows us to
9077 use any symbol in the right segment; we just use
9078 the section symbol as it is convenient. (We
9079 cannot use the symbol given by "h" directly as it
74541ad4
AM		 9080 will not appear in the dynamic symbol table.)
9081
9082 Note that the dynamic linker ignores the section
9083 symbol value, so we don't subtract osec->vma
9084 from the emitted reloc addend. */
10dbd1f3 9085 if (sym_sec)
74541ad4 9086 osec = sym_sec->output_section;
10dbd1f3 9087 else
74541ad4
AM		 9088 osec = input_section->output_section;
9089 symbol = elf_section_data (osec)->dynindx;
9090 if (symbol == 0)
9091 {
9092 struct elf_link_hash_table *htab = elf_hash_table (info);
9093
9094 if ((osec->flags & SEC_READONLY) == 0
9095 && htab->data_index_section != NULL)
9096 osec = htab->data_index_section;
9097 else
9098 osec = htab->text_index_section;
9099 symbol = elf_section_data (osec)->dynindx;
9100 }
6366ff1e
MM		 9101 BFD_ASSERT (symbol != 0);
9102 }
a16385dc
MM		 9103 else
9104 /* On SVR4-ish systems, the dynamic loader cannot
9105 relocate the text and data segments independently,
9106 so the symbol does not matter. */
9107 symbol = 0;
34e77a92
RS		 9108 if (dynreloc_st_type == STT_GNU_IFUNC)
9109 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
9110 to the .iplt entry. Instead, every non-call reference
9111 must use an R_ARM_IRELATIVE relocation to obtain the
9112 correct run-time address. */
9113 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
9114 else
9115 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 9116 if (globals->use_rel)
9117 relocate = TRUE;
9118 else
34e77a92 9119 outrel.r_addend += dynreloc_value;
252b5132 9120 }
f21f3fe0 9121
47beaa6a 9122 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 9123
f21f3fe0 9124 /* If this reloc is against an external symbol, we do not want to
252b5132 9125 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 9126 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 9127 if (! relocate)
9128 return bfd_reloc_ok;
9a5aca8c 9129
f21f3fe0 9130 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 9131 contents, rel->r_offset,
9132 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 9133 }
9134 else switch (r_type)
9135 {
00a97672
RS		 9136 case R_ARM_ABS12:
9137 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
9138
dfc5f959 9139 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 9140 case R_ARM_CALL:
9141 case R_ARM_JUMP24:
8029a119 9142 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 9143 case R_ARM_PLT32:
906e58ca 9144 {
906e58ca
NC		 9145 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
9146
dfc5f959 9147 if (r_type == R_ARM_XPC25)
252b5132 9148 {
dfc5f959
NC		 9149 /* Check for Arm calling Arm function. */
9150 /* FIXME: Should we translate the instruction into a BL
9151 instruction instead ? */
35fc36a8 9152 if (branch_type != ST_BRANCH_TO_THUMB)
d003868e
AM		 9153 (*_bfd_error_handler)
9154 (_("\%B: Warning: Arm BLX instruction targets Arm function '%s'."),
9155 input_bfd,
9156 h ? h->root.root.string : "(local)");
dfc5f959 9157 }
155d87d7 9158 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 9159 {
9160 /* Check for Arm calling Thumb function. */
35fc36a8 9161 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 9162 {
f2a9dd69
DJ		 9163 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
9164 output_bfd, input_section,
9165 hit_data, sym_sec, rel->r_offset,
9166 signed_addend, value,
9167 error_message))
9168 return bfd_reloc_ok;
9169 else
9170 return bfd_reloc_dangerous;
dfc5f959 9171 }
252b5132 9172 }
ba96a88f 9173
906e58ca 9174 /* Check if a stub has to be inserted because the
8029a119 9175 destination is too far or we are changing mode. */
155d87d7
CL		 9176 if ( r_type == R_ARM_CALL
9177 || r_type == R_ARM_JUMP24
9178 || r_type == R_ARM_PLT32)
906e58ca 9179 {
fe33d2fa
CL		 9180 enum elf32_arm_stub_type stub_type = arm_stub_none;
9181 struct elf32_arm_link_hash_entry *hash;
9182
9183 hash = (struct elf32_arm_link_hash_entry *) h;
9184 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 9185 st_type, &branch_type,
9186 hash, value, sym_sec,
fe33d2fa 9187 input_bfd, sym_name);
5fa9e92f 9188
fe33d2fa 9189 if (stub_type != arm_stub_none)
906e58ca
NC		 9190 {
9191 /* The target is out of reach, so redirect the
9192 branch to the local stub for this function. */
906e58ca
NC		 9193 stub_entry = elf32_arm_get_stub_entry (input_section,
9194 sym_sec, h,
fe33d2fa
CL		 9195 rel, globals,
9196 stub_type);
9cd3e4e5
NC		 9197 {
9198 if (stub_entry != NULL)
9199 value = (stub_entry->stub_offset
9200 + stub_entry->stub_sec->output_offset
9201 + stub_entry->stub_sec->output_section->vma);
9202
9203 if (plt_offset != (bfd_vma) -1)
9204 *unresolved_reloc_p = FALSE;
9205 }
906e58ca 9206 }
fe33d2fa
CL		 9207 else
9208 {
9209 /* If the call goes through a PLT entry, make sure to
9210 check distance to the right destination address. */
34e77a92 9211 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 9212 {
9213 value = (splt->output_section->vma
9214 + splt->output_offset
34e77a92 9215 + plt_offset);
fe33d2fa
CL		 9216 *unresolved_reloc_p = FALSE;
9217 /* The PLT entry is in ARM mode, regardless of the
9218 target function. */
35fc36a8 9219 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 9220 }
9221 }
906e58ca
NC		 9222 }
9223
dea514f5
PB		 9224 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
9225 where:
9226 S is the address of the symbol in the relocation.
9227 P is address of the instruction being relocated.
9228 A is the addend (extracted from the instruction) in bytes.
9229
9230 S is held in 'value'.
9231 P is the base address of the section containing the
9232 instruction plus the offset of the reloc into that
9233 section, ie:
9234 (input_section->output_section->vma +
9235 input_section->output_offset +
9236 rel->r_offset).
9237 A is the addend, converted into bytes, ie:
9238 (signed_addend * 4)
9239
9240 Note: None of these operations have knowledge of the pipeline
9241 size of the processor, thus it is up to the assembler to
9242 encode this information into the addend. */
9243 value -= (input_section->output_section->vma
9244 + input_section->output_offset);
9245 value -= rel->r_offset;
4e7fd91e
PB		 9246 if (globals->use_rel)
9247 value += (signed_addend << howto->size);
9248 else
9249 /* RELA addends do not have to be adjusted by howto->size. */
9250 value += signed_addend;
23080146 9251
dcb5e6e6
NC		 9252 signed_addend = value;
9253 signed_addend >>= howto->rightshift;
9a5aca8c 9254
5ab79981 9255 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 9256 the next instruction unless a PLT entry will be created.
77b4f08f 9257 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 9258 The jump to the next instruction is optimized as a NOP depending
9259 on the architecture. */
ffcb4889 9260 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 9261 && plt_offset == (bfd_vma) -1)
77b4f08f 9262 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 9263 {
cd1dac3d
DG		 9264 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
9265
9266 if (arch_has_arm_nop (globals))
9267 value |= 0x0320f000;
9268 else
9269 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 9270 }
9271 else
59f2c4e7 9272 {
9b485d32 9273 /* Perform a signed range check. */
dcb5e6e6 9274 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 9275 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
9276 return bfd_reloc_overflow;
9a5aca8c 9277
5ab79981 9278 addend = (value & 2);
39b41c9c 9279
5ab79981
PB		 9280 value = (signed_addend & howto->dst_mask)
9281 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 9282
5ab79981
PB		 9283 if (r_type == R_ARM_CALL)
9284 {
155d87d7 9285 /* Set the H bit in the BLX instruction. */
35fc36a8 9286 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 9287 {
9288 if (addend)
9289 value |= (1 << 24);
9290 else
9291 value &= ~(bfd_vma)(1 << 24);
9292 }
9293
5ab79981 9294 /* Select the correct instruction (BL or BLX). */
906e58ca 9295 /* Only if we are not handling a BL to a stub. In this
8029a119 9296 case, mode switching is performed by the stub. */
35fc36a8 9297 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 9298 value |= (1 << 28);
63e1a0fc 9299 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 9300 {
9301 value &= ~(bfd_vma)(1 << 28);
9302 value |= (1 << 24);
9303 }
39b41c9c
PB		 9304 }
9305 }
906e58ca 9306 }
252b5132 9307 break;
f21f3fe0 9308
252b5132
RH		 9309 case R_ARM_ABS32:
9310 value += addend;
35fc36a8 9311 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 9312 value |= 1;
9313 break;
f21f3fe0 9314
bb224fc3
MS		 9315 case R_ARM_ABS32_NOI:
9316 value += addend;
9317 break;
9318
252b5132 9319 case R_ARM_REL32:
a8bc6c78 9320 value += addend;
35fc36a8 9321 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 9322 value |= 1;
252b5132 9323 value -= (input_section->output_section->vma
62efb346 9324 + input_section->output_offset + rel->r_offset);
252b5132 9325 break;
eb043451 9326
bb224fc3
MS		 9327 case R_ARM_REL32_NOI:
9328 value += addend;
9329 value -= (input_section->output_section->vma
9330 + input_section->output_offset + rel->r_offset);
9331 break;
9332
eb043451
PB		 9333 case R_ARM_PREL31:
9334 value -= (input_section->output_section->vma
9335 + input_section->output_offset + rel->r_offset);
9336 value += signed_addend;
9337 if (! h || h->root.type != bfd_link_hash_undefweak)
9338 {
8029a119 9339 /* Check for overflow. */
eb043451
PB		 9340 if ((value ^ (value >> 1)) & (1 << 30))
9341 return bfd_reloc_overflow;
9342 }
9343 value &= 0x7fffffff;
9344 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 9345 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 9346 value |= 1;
9347 break;
252b5132 9348 }
f21f3fe0 9349
252b5132
RH		 9350 bfd_put_32 (input_bfd, value, hit_data);
9351 return bfd_reloc_ok;
9352
9353 case R_ARM_ABS8:
fd0fd00c
MJ		 9354 /* PR 16202: Refectch the addend using the correct size. */
9355 if (globals->use_rel)
9356 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 9357 value += addend;
4e67d4ca
DG		 9358
9359 /* There is no way to tell whether the user intended to use a signed or
9360 unsigned addend. When checking for overflow we accept either,
9361 as specified by the AAELF. */
9362 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 9363 return bfd_reloc_overflow;
9364
9365 bfd_put_8 (input_bfd, value, hit_data);
9366 return bfd_reloc_ok;
9367
9368 case R_ARM_ABS16:
fd0fd00c
MJ		 9369 /* PR 16202: Refectch the addend using the correct size. */
9370 if (globals->use_rel)
9371 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 9372 value += addend;
9373
4e67d4ca
DG		 9374 /* See comment for R_ARM_ABS8. */
9375 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 9376 return bfd_reloc_overflow;
9377
9378 bfd_put_16 (input_bfd, value, hit_data);
9379 return bfd_reloc_ok;
9380
252b5132 9381 case R_ARM_THM_ABS5:
9b485d32 9382 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 9383 if (globals->use_rel)
9384 {
9385 /* Need to refetch addend. */
9386 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
9387 /* ??? Need to determine shift amount from operand size. */
9388 addend >>= howto->rightshift;
9389 }
252b5132
RH		 9390 value += addend;
9391
9392 /* ??? Isn't value unsigned? */
9393 if ((long) value > 0x1f || (long) value < -0x10)
9394 return bfd_reloc_overflow;
9395
9396 /* ??? Value needs to be properly shifted into place first. */
9397 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
9398 bfd_put_16 (input_bfd, value, hit_data);
9399 return bfd_reloc_ok;
9400
2cab6cc3
MS		 9401 case R_ARM_THM_ALU_PREL_11_0:
9402 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
9403 {
9404 bfd_vma insn;
9405 bfd_signed_vma relocation;
9406
9407 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 9408 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 9409
99059e56
RM		 9410 if (globals->use_rel)
9411 {
9412 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
9413 | ((insn & (1 << 26)) >> 15);
9414 if (insn & 0xf00000)
9415 signed_addend = -signed_addend;
9416 }
2cab6cc3
MS		 9417
9418 relocation = value + signed_addend;
79f08007 9419 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9420 + input_section->output_offset
9421 + rel->r_offset);
2cab6cc3 9422
b6518b38 9423 value = relocation;
2cab6cc3 9424
99059e56
RM		 9425 if (value >= 0x1000)
9426 return bfd_reloc_overflow;
2cab6cc3
MS		 9427
9428 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 9429 | ((value & 0x700) << 4)
9430 | ((value & 0x800) << 15);
9431 if (relocation < 0)
9432 insn |= 0xa00000;
2cab6cc3
MS		 9433
9434 bfd_put_16 (input_bfd, insn >> 16, hit_data);
9435 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
9436
99059e56 9437 return bfd_reloc_ok;
2cab6cc3
MS		 9438 }
9439
e1ec24c6
NC		 9440 case R_ARM_THM_PC8:
9441 /* PR 10073: This reloc is not generated by the GNU toolchain,
9442 but it is supported for compatibility with third party libraries
9443 generated by other compilers, specifically the ARM/IAR. */
9444 {
9445 bfd_vma insn;
9446 bfd_signed_vma relocation;
9447
9448 insn = bfd_get_16 (input_bfd, hit_data);
9449
99059e56 9450 if (globals->use_rel)
79f08007 9451 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 9452
9453 relocation = value + addend;
79f08007 9454 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9455 + input_section->output_offset
9456 + rel->r_offset);
e1ec24c6 9457
b6518b38 9458 value = relocation;
e1ec24c6
NC		 9459
9460 /* We do not check for overflow of this reloc. Although strictly
9461 speaking this is incorrect, it appears to be necessary in order
9462 to work with IAR generated relocs. Since GCC and GAS do not
9463 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
9464 a problem for them. */
9465 value &= 0x3fc;
9466
9467 insn = (insn & 0xff00) | (value >> 2);
9468
9469 bfd_put_16 (input_bfd, insn, hit_data);
9470
99059e56 9471 return bfd_reloc_ok;
e1ec24c6
NC		 9472 }
9473
2cab6cc3
MS		 9474 case R_ARM_THM_PC12:
9475 /* Corresponds to: ldr.w reg, [pc, #offset]. */
9476 {
9477 bfd_vma insn;
9478 bfd_signed_vma relocation;
9479
9480 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 9481 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 9482
99059e56
RM		 9483 if (globals->use_rel)
9484 {
9485 signed_addend = insn & 0xfff;
9486 if (!(insn & (1 << 23)))
9487 signed_addend = -signed_addend;
9488 }
2cab6cc3
MS		 9489
9490 relocation = value + signed_addend;
79f08007 9491 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9492 + input_section->output_offset
9493 + rel->r_offset);
2cab6cc3 9494
b6518b38 9495 value = relocation;
2cab6cc3 9496
99059e56
RM		 9497 if (value >= 0x1000)
9498 return bfd_reloc_overflow;
2cab6cc3
MS		 9499
9500 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 9501 if (relocation >= 0)
9502 insn |= (1 << 23);
2cab6cc3
MS		 9503
9504 bfd_put_16 (input_bfd, insn >> 16, hit_data);
9505 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
9506
99059e56 9507 return bfd_reloc_ok;
2cab6cc3
MS		 9508 }
9509
dfc5f959 9510 case R_ARM_THM_XPC22:
c19d1205 9511 case R_ARM_THM_CALL:
bd97cb95 9512 case R_ARM_THM_JUMP24:
dfc5f959 9513 /* Thumb BL (branch long instruction). */
252b5132 9514 {
b34976b6 9515 bfd_vma relocation;
99059e56 9516 bfd_vma reloc_sign;
b34976b6
AM		 9517 bfd_boolean overflow = FALSE;
9518 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
9519 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 9520 bfd_signed_vma reloc_signed_max;
9521 bfd_signed_vma reloc_signed_min;
b34976b6 9522 bfd_vma check;
252b5132 9523 bfd_signed_vma signed_check;
e95de063 9524 int bitsize;
cd1dac3d 9525 const int thumb2 = using_thumb2 (globals);
252b5132 9526
5ab79981 9527 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 9528 the next instruction unless a PLT entry will be created.
9529 The jump to the next instruction is optimized as a NOP.W for
9530 Thumb-2 enabled architectures. */
19540007 9531 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 9532 && plt_offset == (bfd_vma) -1)
5ab79981 9533 {
cd1dac3d
DG		 9534 if (arch_has_thumb2_nop (globals))
9535 {
9536 bfd_put_16 (input_bfd, 0xf3af, hit_data);
9537 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
9538 }
9539 else
9540 {
9541 bfd_put_16 (input_bfd, 0xe000, hit_data);
9542 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
9543 }
5ab79981
PB		 9544 return bfd_reloc_ok;
9545 }
9546
e95de063 9547 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 9548 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 9549 if (globals->use_rel)
9550 {
99059e56
RM		 9551 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
9552 bfd_vma upper = upper_insn & 0x3ff;
9553 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 9554 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
9555 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 9556 bfd_vma i1 = j1 ^ s ? 0 : 1;
9557 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 9558
99059e56
RM		 9559 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
9560 /* Sign extend. */
9561 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 9562
4e7fd91e
PB		 9563 signed_addend = addend;
9564 }
cb1afa5c 9565
dfc5f959
NC		 9566 if (r_type == R_ARM_THM_XPC22)
9567 {
9568 /* Check for Thumb to Thumb call. */
9569 /* FIXME: Should we translate the instruction into a BL
9570 instruction instead ? */
35fc36a8 9571 if (branch_type == ST_BRANCH_TO_THUMB)
d003868e
AM		 9572 (*_bfd_error_handler)
9573 (_("%B: Warning: Thumb BLX instruction targets thumb function '%s'."),
9574 input_bfd,
9575 h ? h->root.root.string : "(local)");
dfc5f959
NC		 9576 }
9577 else
252b5132 9578 {
dfc5f959
NC		 9579 /* If it is not a call to Thumb, assume call to Arm.
9580 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 9581 function call at all, but rather a long jump. Calls through
9582 the PLT do not require stubs. */
34e77a92 9583 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 9584 {
bd97cb95 9585 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 9586 {
9587 /* Convert BL to BLX. */
9588 lower_insn = (lower_insn & ~0x1000) | 0x0800;
9589 }
155d87d7
CL		 9590 else if (( r_type != R_ARM_THM_CALL)
9591 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 9592 {
9593 if (elf32_thumb_to_arm_stub
9594 (info, sym_name, input_bfd, output_bfd, input_section,
9595 hit_data, sym_sec, rel->r_offset, signed_addend, value,
9596 error_message))
9597 return bfd_reloc_ok;
9598 else
9599 return bfd_reloc_dangerous;
9600 }
da5938a2 9601 }
35fc36a8
RS		 9602 else if (branch_type == ST_BRANCH_TO_THUMB
9603 && globals->use_blx
bd97cb95 9604 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 9605 {
9606 /* Make sure this is a BL. */
9607 lower_insn |= 0x1800;
9608 }
252b5132 9609 }
f21f3fe0 9610
fe33d2fa 9611 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 9612 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 9613 {
9614 /* Check if a stub has to be inserted because the destination
8029a119 9615 is too far. */
fe33d2fa
CL		 9616 struct elf32_arm_stub_hash_entry *stub_entry;
9617 struct elf32_arm_link_hash_entry *hash;
9618
9619 hash = (struct elf32_arm_link_hash_entry *) h;
9620
9621 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 9622 st_type, &branch_type,
9623 hash, value, sym_sec,
fe33d2fa
CL		 9624 input_bfd, sym_name);
9625
9626 if (stub_type != arm_stub_none)
906e58ca
NC		 9627 {
9628 /* The target is out of reach or we are changing modes, so
9629 redirect the branch to the local stub for this
9630 function. */
9631 stub_entry = elf32_arm_get_stub_entry (input_section,
9632 sym_sec, h,
fe33d2fa
CL		 9633 rel, globals,
9634 stub_type);
906e58ca 9635 if (stub_entry != NULL)
9cd3e4e5
NC		 9636 {
9637 value = (stub_entry->stub_offset
9638 + stub_entry->stub_sec->output_offset
9639 + stub_entry->stub_sec->output_section->vma);
9640
9641 if (plt_offset != (bfd_vma) -1)
9642 *unresolved_reloc_p = FALSE;
9643 }
906e58ca 9644
f4ac8484 9645 /* If this call becomes a call to Arm, force BLX. */
155d87d7 9646 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 9647 {
9648 if ((stub_entry
9649 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 9650 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 9651 lower_insn = (lower_insn & ~0x1000) | 0x0800;
9652 }
906e58ca
NC		 9653 }
9654 }
9655
fe33d2fa 9656 /* Handle calls via the PLT. */
34e77a92 9657 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 9658 {
9659 value = (splt->output_section->vma
9660 + splt->output_offset
34e77a92 9661 + plt_offset);
fe33d2fa 9662
eed94f8f
NC		 9663 if (globals->use_blx
9664 && r_type == R_ARM_THM_CALL
9665 && ! using_thumb_only (globals))
fe33d2fa
CL		 9666 {
9667 /* If the Thumb BLX instruction is available, convert
9668 the BL to a BLX instruction to call the ARM-mode
9669 PLT entry. */
9670 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 9671 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 9672 }
9673 else
9674 {
eed94f8f
NC		 9675 if (! using_thumb_only (globals))
9676 /* Target the Thumb stub before the ARM PLT entry. */
9677 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 9678 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 9679 }
9680 *unresolved_reloc_p = FALSE;
9681 }
9682
ba96a88f 9683 relocation = value + signed_addend;
f21f3fe0 9684
252b5132 9685 relocation -= (input_section->output_section->vma
ba96a88f
NC		 9686 + input_section->output_offset
9687 + rel->r_offset);
9a5aca8c 9688
252b5132
RH		 9689 check = relocation >> howto->rightshift;
9690
9691 /* If this is a signed value, the rightshift just dropped
9692 leading 1 bits (assuming twos complement). */
9693 if ((bfd_signed_vma) relocation >= 0)
9694 signed_check = check;
9695 else
9696 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
9697
e95de063
MS		 9698 /* Calculate the permissable maximum and minimum values for
9699 this relocation according to whether we're relocating for
9700 Thumb-2 or not. */
9701 bitsize = howto->bitsize;
9702 if (!thumb2)
9703 bitsize -= 2;
f6ebfac0 9704 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 9705 reloc_signed_min = ~reloc_signed_max;
9706
252b5132 9707 /* Assumes two's complement. */
ba96a88f 9708 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 9709 overflow = TRUE;
252b5132 9710
bd97cb95 9711 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 9712 /* For a BLX instruction, make sure that the relocation is rounded up
9713 to a word boundary. This follows the semantics of the instruction
9714 which specifies that bit 1 of the target address will come from bit
9715 1 of the base address. */
9716 relocation = (relocation + 2) & ~ 3;
cb1afa5c 9717
e95de063
MS		 9718 /* Put RELOCATION back into the insn. Assumes two's complement.
9719 We use the Thumb-2 encoding, which is safe even if dealing with
9720 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 9721 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 9722 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 9723 | ((relocation >> 12) & 0x3ff)
9724 | (reloc_sign << 10);
906e58ca 9725 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 9726 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
9727 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
9728 | ((relocation >> 1) & 0x7ff);
c62e1cc3 9729
252b5132
RH		 9730 /* Put the relocated value back in the object file: */
9731 bfd_put_16 (input_bfd, upper_insn, hit_data);
9732 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
9733
9734 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
9735 }
9736 break;
9737
c19d1205
ZW		 9738 case R_ARM_THM_JUMP19:
9739 /* Thumb32 conditional branch instruction. */
9740 {
9741 bfd_vma relocation;
9742 bfd_boolean overflow = FALSE;
9743 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
9744 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 9745 bfd_signed_vma reloc_signed_max = 0xffffe;
9746 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 9747 bfd_signed_vma signed_check;
c5423981
TG		 9748 enum elf32_arm_stub_type stub_type = arm_stub_none;
9749 struct elf32_arm_stub_hash_entry *stub_entry;
9750 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 9751
9752 /* Need to refetch the addend, reconstruct the top three bits,
9753 and squish the two 11 bit pieces together. */
9754 if (globals->use_rel)
9755 {
9756 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 9757 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 9758 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
9759 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
9760 bfd_vma lower = (lower_insn & 0x07ff);
9761
a00a1f35
MS		 9762 upper |= J1 << 6;
9763 upper |= J2 << 7;
9764 upper |= (!S) << 8;
c19d1205
ZW		 9765 upper -= 0x0100; /* Sign extend. */
9766
9767 addend = (upper << 12) | (lower << 1);
9768 signed_addend = addend;
9769 }
9770
bd97cb95 9771 /* Handle calls via the PLT. */
34e77a92 9772 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 9773 {
9774 value = (splt->output_section->vma
9775 + splt->output_offset
34e77a92 9776 + plt_offset);
bd97cb95
DJ		 9777 /* Target the Thumb stub before the ARM PLT entry. */
9778 value -= PLT_THUMB_STUB_SIZE;
9779 *unresolved_reloc_p = FALSE;
9780 }
9781
c5423981
TG		 9782 hash = (struct elf32_arm_link_hash_entry *)h;
9783
9784 stub_type = arm_type_of_stub (info, input_section, rel,
9785 st_type, &branch_type,
9786 hash, value, sym_sec,
9787 input_bfd, sym_name);
9788 if (stub_type != arm_stub_none)
9789 {
9790 stub_entry = elf32_arm_get_stub_entry (input_section,
9791 sym_sec, h,
9792 rel, globals,
9793 stub_type);
9794 if (stub_entry != NULL)
9795 {
9796 value = (stub_entry->stub_offset
9797 + stub_entry->stub_sec->output_offset
9798 + stub_entry->stub_sec->output_section->vma);
9799 }
9800 }
c19d1205 9801
99059e56 9802 relocation = value + signed_addend;
c19d1205
ZW		 9803 relocation -= (input_section->output_section->vma
9804 + input_section->output_offset
9805 + rel->r_offset);
a00a1f35 9806 signed_check = (bfd_signed_vma) relocation;
c19d1205 9807
c19d1205
ZW		 9808 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
9809 overflow = TRUE;
9810
9811 /* Put RELOCATION back into the insn. */
9812 {
9813 bfd_vma S = (relocation & 0x00100000) >> 20;
9814 bfd_vma J2 = (relocation & 0x00080000) >> 19;
9815 bfd_vma J1 = (relocation & 0x00040000) >> 18;
9816 bfd_vma hi = (relocation & 0x0003f000) >> 12;
9817 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
9818
a00a1f35 9819 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 9820 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
9821 }
9822
9823 /* Put the relocated value back in the object file: */
9824 bfd_put_16 (input_bfd, upper_insn, hit_data);
9825 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
9826
9827 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
9828 }
9829
9830 case R_ARM_THM_JUMP11:
9831 case R_ARM_THM_JUMP8:
9832 case R_ARM_THM_JUMP6:
51c5503b
NC		 9833 /* Thumb B (branch) instruction). */
9834 {
6cf9e9fe 9835 bfd_signed_vma relocation;
51c5503b
NC		 9836 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
9837 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 9838 bfd_signed_vma signed_check;
9839
c19d1205
ZW		 9840 /* CZB cannot jump backward. */
9841 if (r_type == R_ARM_THM_JUMP6)
9842 reloc_signed_min = 0;
9843
4e7fd91e 9844 if (globals->use_rel)
6cf9e9fe 9845 {
4e7fd91e
PB		 9846 /* Need to refetch addend. */
9847 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
9848 if (addend & ((howto->src_mask + 1) >> 1))
9849 {
9850 signed_addend = -1;
9851 signed_addend &= ~ howto->src_mask;
9852 signed_addend |= addend;
9853 }
9854 else
9855 signed_addend = addend;
9856 /* The value in the insn has been right shifted. We need to
9857 undo this, so that we can perform the address calculation
9858 in terms of bytes. */
9859 signed_addend <<= howto->rightshift;
6cf9e9fe 9860 }
6cf9e9fe 9861 relocation = value + signed_addend;
51c5503b
NC		 9862
9863 relocation -= (input_section->output_section->vma
9864 + input_section->output_offset
9865 + rel->r_offset);
9866
6cf9e9fe
NC		 9867 relocation >>= howto->rightshift;
9868 signed_check = relocation;
c19d1205
ZW		 9869
9870 if (r_type == R_ARM_THM_JUMP6)
9871 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
9872 else
9873 relocation &= howto->dst_mask;
51c5503b 9874 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 9875
51c5503b
NC		 9876 bfd_put_16 (input_bfd, relocation, hit_data);
9877
9878 /* Assumes two's complement. */
9879 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
9880 return bfd_reloc_overflow;
9881
9882 return bfd_reloc_ok;
9883 }
cedb70c5 9884
8375c36b
PB		 9885 case R_ARM_ALU_PCREL7_0:
9886 case R_ARM_ALU_PCREL15_8:
9887 case R_ARM_ALU_PCREL23_15:
9888 {
9889 bfd_vma insn;
9890 bfd_vma relocation;
9891
9892 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 9893 if (globals->use_rel)
9894 {
9895 /* Extract the addend. */
9896 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
9897 signed_addend = addend;
9898 }
8375c36b
PB		 9899 relocation = value + signed_addend;
9900
9901 relocation -= (input_section->output_section->vma
9902 + input_section->output_offset
9903 + rel->r_offset);
9904 insn = (insn & ~0xfff)
9905 | ((howto->bitpos << 7) & 0xf00)
9906 | ((relocation >> howto->bitpos) & 0xff);
9907 bfd_put_32 (input_bfd, value, hit_data);
9908 }
9909 return bfd_reloc_ok;
9910
252b5132
RH		 9911 case R_ARM_GNU_VTINHERIT:
9912 case R_ARM_GNU_VTENTRY:
9913 return bfd_reloc_ok;
9914
c19d1205 9915 case R_ARM_GOTOFF32:
252b5132 9916 /* Relocation is relative to the start of the
99059e56 9917 global offset table. */
252b5132
RH		 9918
9919 BFD_ASSERT (sgot != NULL);
9920 if (sgot == NULL)
99059e56 9921 return bfd_reloc_notsupported;
9a5aca8c 9922
cedb70c5 9923 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 9924 address by one, so that attempts to call the function pointer will
9925 correctly interpret it as Thumb code. */
35fc36a8 9926 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 9927 value += 1;
9928
252b5132 9929 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 9930 calculation. We always want the start of .got. If we
9931 define _GLOBAL_OFFSET_TABLE in a different way, as is
9932 permitted by the ABI, we might have to change this
9933 calculation. */
252b5132 9934 value -= sgot->output_section->vma;
f21f3fe0 9935 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 9936 contents, rel->r_offset, value,
00a97672 9937 rel->r_addend);
252b5132
RH		 9938
9939 case R_ARM_GOTPC:
a7c10850 9940 /* Use global offset table as symbol value. */
252b5132 9941 BFD_ASSERT (sgot != NULL);
f21f3fe0 9942
252b5132 9943 if (sgot == NULL)
99059e56 9944 return bfd_reloc_notsupported;
252b5132 9945
0945cdfd 9946 *unresolved_reloc_p = FALSE;
252b5132 9947 value = sgot->output_section->vma;
f21f3fe0 9948 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 9949 contents, rel->r_offset, value,
00a97672 9950 rel->r_addend);
f21f3fe0 9951
252b5132 9952 case R_ARM_GOT32:
eb043451 9953 case R_ARM_GOT_PREL:
252b5132 9954 /* Relocation is to the entry for this symbol in the
99059e56 9955 global offset table. */
252b5132
RH		 9956 if (sgot == NULL)
9957 return bfd_reloc_notsupported;
f21f3fe0 9958
34e77a92
RS		 9959 if (dynreloc_st_type == STT_GNU_IFUNC
9960 && plt_offset != (bfd_vma) -1
9961 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
9962 {
9963 /* We have a relocation against a locally-binding STT_GNU_IFUNC
9964 symbol, and the relocation resolves directly to the runtime
9965 target rather than to the .iplt entry. This means that any
9966 .got entry would be the same value as the .igot.plt entry,
9967 so there's no point creating both. */
9968 sgot = globals->root.igotplt;
9969 value = sgot->output_offset + gotplt_offset;
9970 }
9971 else if (h != NULL)
252b5132
RH		 9972 {
9973 bfd_vma off;
f21f3fe0 9974
252b5132
RH		 9975 off = h->got.offset;
9976 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 9977 if ((off & 1) != 0)
252b5132 9978 {
b436d854
RS		 9979 /* We have already processsed one GOT relocation against
9980 this symbol. */
9981 off &= ~1;
9982 if (globals->root.dynamic_sections_created
9983 && !SYMBOL_REFERENCES_LOCAL (info, h))
9984 *unresolved_reloc_p = FALSE;
9985 }
9986 else
9987 {
9988 Elf_Internal_Rela outrel;
9989
6f820c85 9990 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 9991 {
9992 /* If the symbol doesn't resolve locally in a static
9993 object, we have an undefined reference. If the
9994 symbol doesn't resolve locally in a dynamic object,
9995 it should be resolved by the dynamic linker. */
9996 if (globals->root.dynamic_sections_created)
9997 {
9998 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
9999 *unresolved_reloc_p = FALSE;
10000 }
10001 else
10002 outrel.r_info = 0;
10003 outrel.r_addend = 0;
10004 }
252b5132
RH		 10005 else
10006 {
34e77a92 10007 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 10008 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
0e1862bb 10009 else if (bfd_link_pic (info) &&
31943882
WN		 10010 (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10011 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 10012 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
10013 else
10014 outrel.r_info = 0;
34e77a92 10015 outrel.r_addend = dynreloc_value;
b436d854 10016 }
ee29b9fb 10017
b436d854
RS		 10018 /* The GOT entry is initialized to zero by default.
10019 See if we should install a different value. */
10020 if (outrel.r_addend != 0
10021 && (outrel.r_info == 0 || globals->use_rel))
10022 {
10023 bfd_put_32 (output_bfd, outrel.r_addend,
10024 sgot->contents + off);
10025 outrel.r_addend = 0;
252b5132 10026 }
f21f3fe0 10027
b436d854
RS		 10028 if (outrel.r_info != 0)
10029 {
10030 outrel.r_offset = (sgot->output_section->vma
10031 + sgot->output_offset
10032 + off);
10033 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
10034 }
10035 h->got.offset |= 1;
10036 }
252b5132
RH		 10037 value = sgot->output_offset + off;
10038 }
10039 else
10040 {
10041 bfd_vma off;
f21f3fe0 10042
252b5132
RH		 10043 BFD_ASSERT (local_got_offsets != NULL &&
10044 local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 10045
252b5132 10046 off = local_got_offsets[r_symndx];
f21f3fe0 10047
252b5132
RH		 10048 /* The offset must always be a multiple of 4. We use the
10049 least significant bit to record whether we have already
9b485d32 10050 generated the necessary reloc. */
252b5132
RH		 10051 if ((off & 1) != 0)
10052 off &= ~1;
10053 else
10054 {
00a97672 10055 if (globals->use_rel)
34e77a92 10056 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 10057
0e1862bb 10058 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 10059 {
947216bf 10060 Elf_Internal_Rela outrel;
f21f3fe0 10061
34e77a92 10062 outrel.r_addend = addend + dynreloc_value;
252b5132 10063 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 10064 + sgot->output_offset
252b5132 10065 + off);
34e77a92 10066 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 10067 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 10068 else
10069 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 10070 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 10071 }
f21f3fe0 10072
252b5132
RH		 10073 local_got_offsets[r_symndx] |= 1;
10074 }
f21f3fe0 10075
252b5132
RH		 10076 value = sgot->output_offset + off;
10077 }
eb043451
PB		 10078 if (r_type != R_ARM_GOT32)
10079 value += sgot->output_section->vma;
9a5aca8c 10080
f21f3fe0 10081 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10082 contents, rel->r_offset, value,
00a97672 10083 rel->r_addend);
f21f3fe0 10084
ba93b8ac
DJ		 10085 case R_ARM_TLS_LDO32:
10086 value = value - dtpoff_base (info);
10087
10088 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 10089 contents, rel->r_offset, value,
10090 rel->r_addend);
ba93b8ac
DJ		 10091
10092 case R_ARM_TLS_LDM32:
10093 {
10094 bfd_vma off;
10095
362d30a1 10096 if (sgot == NULL)
ba93b8ac
DJ		 10097 abort ();
10098
10099 off = globals->tls_ldm_got.offset;
10100
10101 if ((off & 1) != 0)
10102 off &= ~1;
10103 else
10104 {
10105 /* If we don't know the module number, create a relocation
10106 for it. */
0e1862bb 10107 if (bfd_link_pic (info))
ba93b8ac
DJ		 10108 {
10109 Elf_Internal_Rela outrel;
ba93b8ac 10110
362d30a1 10111 if (srelgot == NULL)
ba93b8ac
DJ		 10112 abort ();
10113
00a97672 10114 outrel.r_addend = 0;
362d30a1
RS		 10115 outrel.r_offset = (sgot->output_section->vma
10116 + sgot->output_offset + off);
ba93b8ac
DJ		 10117 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
10118
00a97672
RS		 10119 if (globals->use_rel)
10120 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10121 sgot->contents + off);
ba93b8ac 10122
47beaa6a 10123 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10124 }
10125 else
362d30a1 10126 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 10127
10128 globals->tls_ldm_got.offset |= 1;
10129 }
10130
362d30a1 10131 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 10132 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
10133
10134 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10135 contents, rel->r_offset, value,
00a97672 10136 rel->r_addend);
ba93b8ac
DJ		 10137 }
10138
0855e32b
NS		 10139 case R_ARM_TLS_CALL:
10140 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 10141 case R_ARM_TLS_GD32:
10142 case R_ARM_TLS_IE32:
0855e32b
NS		 10143 case R_ARM_TLS_GOTDESC:
10144 case R_ARM_TLS_DESCSEQ:
10145 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 10146 {
0855e32b
NS		 10147 bfd_vma off, offplt;
10148 int indx = 0;
ba93b8ac
DJ		 10149 char tls_type;
10150
0855e32b 10151 BFD_ASSERT (sgot != NULL);
ba93b8ac 10152
ba93b8ac
DJ		 10153 if (h != NULL)
10154 {
10155 bfd_boolean dyn;
10156 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 10157 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
10158 bfd_link_pic (info),
10159 h)
10160 && (!bfd_link_pic (info)
ba93b8ac
DJ		 10161 || !SYMBOL_REFERENCES_LOCAL (info, h)))
10162 {
10163 *unresolved_reloc_p = FALSE;
10164 indx = h->dynindx;
10165 }
10166 off = h->got.offset;
0855e32b 10167 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 10168 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
10169 }
10170 else
10171 {
0855e32b 10172 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 10173 off = local_got_offsets[r_symndx];
0855e32b 10174 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 10175 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
10176 }
10177
0855e32b 10178 /* Linker relaxations happens from one of the
b38cadfb 10179 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 10180 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 10181 tls_type = GOT_TLS_IE;
0855e32b
NS		 10182
10183 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 10184
10185 if ((off & 1) != 0)
10186 off &= ~1;
10187 else
10188 {
10189 bfd_boolean need_relocs = FALSE;
10190 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 10191 int cur_off = off;
10192
10193 /* The GOT entries have not been initialized yet. Do it
10194 now, and emit any relocations. If both an IE GOT and a
10195 GD GOT are necessary, we emit the GD first. */
10196
0e1862bb 10197 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 10198 && (h == NULL
10199 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10200 || h->root.type != bfd_link_hash_undefweak))
10201 {
10202 need_relocs = TRUE;
0855e32b 10203 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 10204 }
10205
0855e32b
NS		 10206 if (tls_type & GOT_TLS_GDESC)
10207 {
47beaa6a
RS		 10208 bfd_byte *loc;
10209
0855e32b
NS		 10210 /* We should have relaxed, unless this is an undefined
10211 weak symbol. */
10212 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 10213 || bfd_link_pic (info));
0855e32b 10214 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 10215 <= globals->root.sgotplt->size);
0855e32b
NS		 10216
10217 outrel.r_addend = 0;
10218 outrel.r_offset = (globals->root.sgotplt->output_section->vma
10219 + globals->root.sgotplt->output_offset
10220 + offplt
10221 + globals->sgotplt_jump_table_size);
b38cadfb 10222
0855e32b
NS		 10223 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
10224 sreloc = globals->root.srelplt;
10225 loc = sreloc->contents;
10226 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
10227 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 10228 <= sreloc->contents + sreloc->size);
0855e32b
NS		 10229
10230 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
10231
10232 /* For globals, the first word in the relocation gets
10233 the relocation index and the top bit set, or zero,
10234 if we're binding now. For locals, it gets the
10235 symbol's offset in the tls section. */
99059e56 10236 bfd_put_32 (output_bfd,
0855e32b
NS		 10237 !h ? value - elf_hash_table (info)->tls_sec->vma
10238 : info->flags & DF_BIND_NOW ? 0
10239 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 10240 globals->root.sgotplt->contents + offplt
10241 + globals->sgotplt_jump_table_size);
10242
0855e32b 10243 /* Second word in the relocation is always zero. */
99059e56 10244 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 10245 globals->root.sgotplt->contents + offplt
10246 + globals->sgotplt_jump_table_size + 4);
0855e32b 10247 }
ba93b8ac
DJ		 10248 if (tls_type & GOT_TLS_GD)
10249 {
10250 if (need_relocs)
10251 {
00a97672 10252 outrel.r_addend = 0;
362d30a1
RS		 10253 outrel.r_offset = (sgot->output_section->vma
10254 + sgot->output_offset
00a97672 10255 + cur_off);
ba93b8ac 10256 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 10257
00a97672
RS		 10258 if (globals->use_rel)
10259 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10260 sgot->contents + cur_off);
00a97672 10261
47beaa6a 10262 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10263
10264 if (indx == 0)
10265 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 10266 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 10267 else
10268 {
00a97672 10269 outrel.r_addend = 0;
ba93b8ac
DJ		 10270 outrel.r_info = ELF32_R_INFO (indx,
10271 R_ARM_TLS_DTPOFF32);
10272 outrel.r_offset += 4;
00a97672
RS		 10273
10274 if (globals->use_rel)
10275 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10276 sgot->contents + cur_off + 4);
00a97672 10277
47beaa6a
RS		 10278 elf32_arm_add_dynreloc (output_bfd, info,
10279 srelgot, &outrel);
ba93b8ac
DJ		 10280 }
10281 }
10282 else
10283 {
10284 /* If we are not emitting relocations for a
10285 general dynamic reference, then we must be in a
10286 static link or an executable link with the
10287 symbol binding locally. Mark it as belonging
10288 to module 1, the executable. */
10289 bfd_put_32 (output_bfd, 1,
362d30a1 10290 sgot->contents + cur_off);
ba93b8ac 10291 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 10292 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 10293 }
10294
10295 cur_off += 8;
10296 }
10297
10298 if (tls_type & GOT_TLS_IE)
10299 {
10300 if (need_relocs)
10301 {
00a97672
RS		 10302 if (indx == 0)
10303 outrel.r_addend = value - dtpoff_base (info);
10304 else
10305 outrel.r_addend = 0;
362d30a1
RS		 10306 outrel.r_offset = (sgot->output_section->vma
10307 + sgot->output_offset
ba93b8ac
DJ		 10308 + cur_off);
10309 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
10310
00a97672
RS		 10311 if (globals->use_rel)
10312 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10313 sgot->contents + cur_off);
ba93b8ac 10314
47beaa6a 10315 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10316 }
10317 else
10318 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 10319 sgot->contents + cur_off);
ba93b8ac
DJ		 10320 cur_off += 4;
10321 }
10322
10323 if (h != NULL)
10324 h->got.offset |= 1;
10325 else
10326 local_got_offsets[r_symndx] |= 1;
10327 }
10328
10329 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
10330 off += 8;
0855e32b
NS		 10331 else if (tls_type & GOT_TLS_GDESC)
10332 off = offplt;
10333
10334 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
10335 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
10336 {
10337 bfd_signed_vma offset;
12352d3f
PB		 10338 /* TLS stubs are arm mode. The original symbol is a
10339 data object, so branch_type is bogus. */
10340 branch_type = ST_BRANCH_TO_ARM;
0855e32b 10341 enum elf32_arm_stub_type stub_type
34e77a92
RS		 10342 = arm_type_of_stub (info, input_section, rel,
10343 st_type, &branch_type,
0855e32b
NS		 10344 (struct elf32_arm_link_hash_entry *)h,
10345 globals->tls_trampoline, globals->root.splt,
10346 input_bfd, sym_name);
10347
10348 if (stub_type != arm_stub_none)
10349 {
10350 struct elf32_arm_stub_hash_entry *stub_entry
10351 = elf32_arm_get_stub_entry
10352 (input_section, globals->root.splt, 0, rel,
10353 globals, stub_type);
10354 offset = (stub_entry->stub_offset
10355 + stub_entry->stub_sec->output_offset
10356 + stub_entry->stub_sec->output_section->vma);
10357 }
10358 else
10359 offset = (globals->root.splt->output_section->vma
10360 + globals->root.splt->output_offset
10361 + globals->tls_trampoline);
10362
10363 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
10364 {
10365 unsigned long inst;
b38cadfb
NC		 10366
10367 offset -= (input_section->output_section->vma
10368 + input_section->output_offset
10369 + rel->r_offset + 8);
0855e32b
NS		 10370
10371 inst = offset >> 2;
10372 inst &= 0x00ffffff;
10373 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
10374 }
10375 else
10376 {
10377 /* Thumb blx encodes the offset in a complicated
10378 fashion. */
10379 unsigned upper_insn, lower_insn;
10380 unsigned neg;
10381
b38cadfb
NC		 10382 offset -= (input_section->output_section->vma
10383 + input_section->output_offset
0855e32b 10384 + rel->r_offset + 4);
b38cadfb 10385
12352d3f
PB		 10386 if (stub_type != arm_stub_none
10387 && arm_stub_is_thumb (stub_type))
10388 {
10389 lower_insn = 0xd000;
10390 }
10391 else
10392 {
10393 lower_insn = 0xc000;
6a631e86 10394 /* Round up the offset to a word boundary. */
12352d3f
PB		 10395 offset = (offset + 2) & ~2;
10396 }
10397
0855e32b
NS		 10398 neg = offset < 0;
10399 upper_insn = (0xf000
10400 | ((offset >> 12) & 0x3ff)
10401 | (neg << 10));
12352d3f 10402 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 10403 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 10404 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 10405 bfd_put_16 (input_bfd, upper_insn, hit_data);
10406 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10407 return bfd_reloc_ok;
10408 }
10409 }
10410 /* These relocations needs special care, as besides the fact
10411 they point somewhere in .gotplt, the addend must be
10412 adjusted accordingly depending on the type of instruction
6a631e86 10413 we refer to. */
0855e32b
NS		 10414 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
10415 {
10416 unsigned long data, insn;
10417 unsigned thumb;
b38cadfb 10418
0855e32b
NS		 10419 data = bfd_get_32 (input_bfd, hit_data);
10420 thumb = data & 1;
10421 data &= ~1u;
b38cadfb 10422
0855e32b
NS		 10423 if (thumb)
10424 {
10425 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
10426 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10427 insn = (insn << 16)
10428 | bfd_get_16 (input_bfd,
10429 contents + rel->r_offset - data + 2);
10430 if ((insn & 0xf800c000) == 0xf000c000)
10431 /* bl/blx */
10432 value = -6;
10433 else if ((insn & 0xffffff00) == 0x4400)
10434 /* add */
10435 value = -5;
10436 else
10437 {
10438 (*_bfd_error_handler)
10439 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' referenced by TLS_GOTDESC"),
10440 input_bfd, input_section,
10441 (unsigned long)rel->r_offset, insn);
10442 return bfd_reloc_notsupported;
10443 }
10444 }
10445 else
10446 {
10447 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
10448
10449 switch (insn >> 24)
10450 {
10451 case 0xeb: /* bl */
10452 case 0xfa: /* blx */
10453 value = -4;
10454 break;
10455
10456 case 0xe0: /* add */
10457 value = -8;
10458 break;
b38cadfb 10459
0855e32b
NS		 10460 default:
10461 (*_bfd_error_handler)
10462 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' referenced by TLS_GOTDESC"),
10463 input_bfd, input_section,
10464 (unsigned long)rel->r_offset, insn);
10465 return bfd_reloc_notsupported;
10466 }
10467 }
b38cadfb 10468
0855e32b
NS		 10469 value += ((globals->root.sgotplt->output_section->vma
10470 + globals->root.sgotplt->output_offset + off)
10471 - (input_section->output_section->vma
10472 + input_section->output_offset
10473 + rel->r_offset)
10474 + globals->sgotplt_jump_table_size);
10475 }
10476 else
10477 value = ((globals->root.sgot->output_section->vma
10478 + globals->root.sgot->output_offset + off)
10479 - (input_section->output_section->vma
10480 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 10481
10482 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10483 contents, rel->r_offset, value,
00a97672 10484 rel->r_addend);
ba93b8ac
DJ		 10485 }
10486
10487 case R_ARM_TLS_LE32:
3cbc1e5e 10488 if (bfd_link_dll (info))
ba93b8ac
DJ		 10489 {
10490 (*_bfd_error_handler)
10491 (_("%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object"),
10492 input_bfd, input_section,
10493 (long) rel->r_offset, howto->name);
46691134 10494 return bfd_reloc_notsupported;
ba93b8ac
DJ		 10495 }
10496 else
10497 value = tpoff (info, value);
906e58ca 10498
ba93b8ac 10499 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 10500 contents, rel->r_offset, value,
10501 rel->r_addend);
ba93b8ac 10502
319850b4
JB		 10503 case R_ARM_V4BX:
10504 if (globals->fix_v4bx)
845b51d6
PB		 10505 {
10506 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 10507
845b51d6
PB		 10508 /* Ensure that we have a BX instruction. */
10509 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 10510
845b51d6
PB		 10511 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
10512 {
10513 /* Branch to veneer. */
10514 bfd_vma glue_addr;
10515 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
10516 glue_addr -= input_section->output_section->vma
10517 + input_section->output_offset
10518 + rel->r_offset + 8;
10519 insn = (insn & 0xf0000000) | 0x0a000000
10520 | ((glue_addr >> 2) & 0x00ffffff);
10521 }
10522 else
10523 {
10524 /* Preserve Rm (lowest four bits) and the condition code
10525 (highest four bits). Other bits encode MOV PC,Rm. */
10526 insn = (insn & 0xf000000f) | 0x01a0f000;
10527 }
319850b4 10528
845b51d6
PB		 10529 bfd_put_32 (input_bfd, insn, hit_data);
10530 }
319850b4
JB		 10531 return bfd_reloc_ok;
10532
b6895b4f
PB		 10533 case R_ARM_MOVW_ABS_NC:
10534 case R_ARM_MOVT_ABS:
10535 case R_ARM_MOVW_PREL_NC:
10536 case R_ARM_MOVT_PREL:
92f5d02b
MS		 10537 /* Until we properly support segment-base-relative addressing then
10538 we assume the segment base to be zero, as for the group relocations.
10539 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
10540 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
10541 case R_ARM_MOVW_BREL_NC:
10542 case R_ARM_MOVW_BREL:
10543 case R_ARM_MOVT_BREL:
b6895b4f
PB		 10544 {
10545 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
10546
10547 if (globals->use_rel)
10548 {
10549 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 10550 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 10551 }
92f5d02b 10552
b6895b4f 10553 value += signed_addend;
b6895b4f
PB		 10554
10555 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
10556 value -= (input_section->output_section->vma
10557 + input_section->output_offset + rel->r_offset);
10558
92f5d02b 10559 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 10560 return bfd_reloc_overflow;
92f5d02b 10561
35fc36a8 10562 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 10563 value |= 1;
10564
10565 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 10566 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 10567 value >>= 16;
10568
10569 insn &= 0xfff0f000;
10570 insn |= value & 0xfff;
10571 insn |= (value & 0xf000) << 4;
10572 bfd_put_32 (input_bfd, insn, hit_data);
10573 }
10574 return bfd_reloc_ok;
10575
10576 case R_ARM_THM_MOVW_ABS_NC:
10577 case R_ARM_THM_MOVT_ABS:
10578 case R_ARM_THM_MOVW_PREL_NC:
10579 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 10580 /* Until we properly support segment-base-relative addressing then
10581 we assume the segment base to be zero, as for the above relocations.
10582 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
10583 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
10584 as R_ARM_THM_MOVT_ABS. */
10585 case R_ARM_THM_MOVW_BREL_NC:
10586 case R_ARM_THM_MOVW_BREL:
10587 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 10588 {
10589 bfd_vma insn;
906e58ca 10590
b6895b4f
PB		 10591 insn = bfd_get_16 (input_bfd, hit_data) << 16;
10592 insn |= bfd_get_16 (input_bfd, hit_data + 2);
10593
10594 if (globals->use_rel)
10595 {
10596 addend = ((insn >> 4) & 0xf000)
10597 | ((insn >> 15) & 0x0800)
10598 | ((insn >> 4) & 0x0700)
10599 | (insn & 0x00ff);
39623e12 10600 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 10601 }
92f5d02b 10602
b6895b4f 10603 value += signed_addend;
b6895b4f
PB		 10604
10605 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
10606 value -= (input_section->output_section->vma
10607 + input_section->output_offset + rel->r_offset);
10608
92f5d02b 10609 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 10610 return bfd_reloc_overflow;
92f5d02b 10611
35fc36a8 10612 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 10613 value |= 1;
10614
10615 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 10616 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 10617 value >>= 16;
10618
10619 insn &= 0xfbf08f00;
10620 insn |= (value & 0xf000) << 4;
10621 insn |= (value & 0x0800) << 15;
10622 insn |= (value & 0x0700) << 4;
10623 insn |= (value & 0x00ff);
10624
10625 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10626 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10627 }
10628 return bfd_reloc_ok;
10629
4962c51a
MS		 10630 case R_ARM_ALU_PC_G0_NC:
10631 case R_ARM_ALU_PC_G1_NC:
10632 case R_ARM_ALU_PC_G0:
10633 case R_ARM_ALU_PC_G1:
10634 case R_ARM_ALU_PC_G2:
10635 case R_ARM_ALU_SB_G0_NC:
10636 case R_ARM_ALU_SB_G1_NC:
10637 case R_ARM_ALU_SB_G0:
10638 case R_ARM_ALU_SB_G1:
10639 case R_ARM_ALU_SB_G2:
10640 {
10641 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10642 bfd_vma pc = input_section->output_section->vma
4962c51a 10643 + input_section->output_offset + rel->r_offset;
31a91d61 10644 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10645 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 10646 bfd_vma residual;
10647 bfd_vma g_n;
4962c51a 10648 bfd_signed_vma signed_value;
99059e56
RM		 10649 int group = 0;
10650
10651 /* Determine which group of bits to select. */
10652 switch (r_type)
10653 {
10654 case R_ARM_ALU_PC_G0_NC:
10655 case R_ARM_ALU_PC_G0:
10656 case R_ARM_ALU_SB_G0_NC:
10657 case R_ARM_ALU_SB_G0:
10658 group = 0;
10659 break;
10660
10661 case R_ARM_ALU_PC_G1_NC:
10662 case R_ARM_ALU_PC_G1:
10663 case R_ARM_ALU_SB_G1_NC:
10664 case R_ARM_ALU_SB_G1:
10665 group = 1;
10666 break;
10667
10668 case R_ARM_ALU_PC_G2:
10669 case R_ARM_ALU_SB_G2:
10670 group = 2;
10671 break;
10672
10673 default:
10674 abort ();
10675 }
10676
10677 /* If REL, extract the addend from the insn. If RELA, it will
10678 have already been fetched for us. */
4962c51a 10679 if (globals->use_rel)
99059e56
RM		 10680 {
10681 int negative;
10682 bfd_vma constant = insn & 0xff;
10683 bfd_vma rotation = (insn & 0xf00) >> 8;
10684
10685 if (rotation == 0)
10686 signed_addend = constant;
10687 else
10688 {
10689 /* Compensate for the fact that in the instruction, the
10690 rotation is stored in multiples of 2 bits. */
10691 rotation *= 2;
10692
10693 /* Rotate "constant" right by "rotation" bits. */
10694 signed_addend = (constant >> rotation) |
10695 (constant << (8 * sizeof (bfd_vma) - rotation));
10696 }
10697
10698 /* Determine if the instruction is an ADD or a SUB.
10699 (For REL, this determines the sign of the addend.) */
10700 negative = identify_add_or_sub (insn);
10701 if (negative == 0)
10702 {
10703 (*_bfd_error_handler)
10704 (_("%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations"),
10705 input_bfd, input_section,
10706 (long) rel->r_offset, howto->name);
10707 return bfd_reloc_overflow;
10708 }
10709
10710 signed_addend *= negative;
10711 }
4962c51a
MS		 10712
10713 /* Compute the value (X) to go in the place. */
99059e56
RM		 10714 if (r_type == R_ARM_ALU_PC_G0_NC
10715 || r_type == R_ARM_ALU_PC_G1_NC
10716 || r_type == R_ARM_ALU_PC_G0
10717 || r_type == R_ARM_ALU_PC_G1
10718 || r_type == R_ARM_ALU_PC_G2)
10719 /* PC relative. */
10720 signed_value = value - pc + signed_addend;
10721 else
10722 /* Section base relative. */
10723 signed_value = value - sb + signed_addend;
10724
10725 /* If the target symbol is a Thumb function, then set the
10726 Thumb bit in the address. */
35fc36a8 10727 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 10728 signed_value |= 1;
10729
99059e56
RM		 10730 /* Calculate the value of the relevant G_n, in encoded
10731 constant-with-rotation format. */
b6518b38
NC		 10732 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
10733 group, &residual);
99059e56
RM		 10734
10735 /* Check for overflow if required. */
10736 if ((r_type == R_ARM_ALU_PC_G0
10737 || r_type == R_ARM_ALU_PC_G1
10738 || r_type == R_ARM_ALU_PC_G2
10739 || r_type == R_ARM_ALU_SB_G0
10740 || r_type == R_ARM_ALU_SB_G1
10741 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
10742 {
10743 (*_bfd_error_handler)
10744 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
10745 input_bfd, input_section,
b6518b38
NC		 10746 (long) rel->r_offset, signed_value < 0 ? - signed_value : signed_value,
10747 howto->name);
99059e56
RM		 10748 return bfd_reloc_overflow;
10749 }
10750
10751 /* Mask out the value and the ADD/SUB part of the opcode; take care
10752 not to destroy the S bit. */
10753 insn &= 0xff1ff000;
10754
10755 /* Set the opcode according to whether the value to go in the
10756 place is negative. */
10757 if (signed_value < 0)
10758 insn |= 1 << 22;
10759 else
10760 insn |= 1 << 23;
10761
10762 /* Encode the offset. */
10763 insn |= g_n;
4962c51a
MS		 10764
10765 bfd_put_32 (input_bfd, insn, hit_data);
10766 }
10767 return bfd_reloc_ok;
10768
10769 case R_ARM_LDR_PC_G0:
10770 case R_ARM_LDR_PC_G1:
10771 case R_ARM_LDR_PC_G2:
10772 case R_ARM_LDR_SB_G0:
10773 case R_ARM_LDR_SB_G1:
10774 case R_ARM_LDR_SB_G2:
10775 {
10776 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10777 bfd_vma pc = input_section->output_section->vma
4962c51a 10778 + input_section->output_offset + rel->r_offset;
31a91d61 10779 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10780 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 10781 bfd_vma residual;
4962c51a 10782 bfd_signed_vma signed_value;
99059e56
RM		 10783 int group = 0;
10784
10785 /* Determine which groups of bits to calculate. */
10786 switch (r_type)
10787 {
10788 case R_ARM_LDR_PC_G0:
10789 case R_ARM_LDR_SB_G0:
10790 group = 0;
10791 break;
10792
10793 case R_ARM_LDR_PC_G1:
10794 case R_ARM_LDR_SB_G1:
10795 group = 1;
10796 break;
10797
10798 case R_ARM_LDR_PC_G2:
10799 case R_ARM_LDR_SB_G2:
10800 group = 2;
10801 break;
10802
10803 default:
10804 abort ();
10805 }
10806
10807 /* If REL, extract the addend from the insn. If RELA, it will
10808 have already been fetched for us. */
4962c51a 10809 if (globals->use_rel)
99059e56
RM		 10810 {
10811 int negative = (insn & (1 << 23)) ? 1 : -1;
10812 signed_addend = negative * (insn & 0xfff);
10813 }
4962c51a
MS		 10814
10815 /* Compute the value (X) to go in the place. */
99059e56
RM		 10816 if (r_type == R_ARM_LDR_PC_G0
10817 || r_type == R_ARM_LDR_PC_G1
10818 || r_type == R_ARM_LDR_PC_G2)
10819 /* PC relative. */
10820 signed_value = value - pc + signed_addend;
10821 else
10822 /* Section base relative. */
10823 signed_value = value - sb + signed_addend;
10824
10825 /* Calculate the value of the relevant G_{n-1} to obtain
10826 the residual at that stage. */
b6518b38
NC		 10827 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
10828 group - 1, &residual);
99059e56
RM		 10829
10830 /* Check for overflow. */
10831 if (residual >= 0x1000)
10832 {
10833 (*_bfd_error_handler)
10834 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 10835 input_bfd, input_section,
10836 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 10837 return bfd_reloc_overflow;
10838 }
10839
10840 /* Mask out the value and U bit. */
10841 insn &= 0xff7ff000;
10842
10843 /* Set the U bit if the value to go in the place is non-negative. */
10844 if (signed_value >= 0)
10845 insn |= 1 << 23;
10846
10847 /* Encode the offset. */
10848 insn |= residual;
4962c51a
MS		 10849
10850 bfd_put_32 (input_bfd, insn, hit_data);
10851 }
10852 return bfd_reloc_ok;
10853
10854 case R_ARM_LDRS_PC_G0:
10855 case R_ARM_LDRS_PC_G1:
10856 case R_ARM_LDRS_PC_G2:
10857 case R_ARM_LDRS_SB_G0:
10858 case R_ARM_LDRS_SB_G1:
10859 case R_ARM_LDRS_SB_G2:
10860 {
10861 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10862 bfd_vma pc = input_section->output_section->vma
4962c51a 10863 + input_section->output_offset + rel->r_offset;
31a91d61 10864 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10865 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 10866 bfd_vma residual;
4962c51a 10867 bfd_signed_vma signed_value;
99059e56
RM		 10868 int group = 0;
10869
10870 /* Determine which groups of bits to calculate. */
10871 switch (r_type)
10872 {
10873 case R_ARM_LDRS_PC_G0:
10874 case R_ARM_LDRS_SB_G0:
10875 group = 0;
10876 break;
10877
10878 case R_ARM_LDRS_PC_G1:
10879 case R_ARM_LDRS_SB_G1:
10880 group = 1;
10881 break;
10882
10883 case R_ARM_LDRS_PC_G2:
10884 case R_ARM_LDRS_SB_G2:
10885 group = 2;
10886 break;
10887
10888 default:
10889 abort ();
10890 }
10891
10892 /* If REL, extract the addend from the insn. If RELA, it will
10893 have already been fetched for us. */
4962c51a 10894 if (globals->use_rel)
99059e56
RM		 10895 {
10896 int negative = (insn & (1 << 23)) ? 1 : -1;
10897 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
10898 }
4962c51a
MS		 10899
10900 /* Compute the value (X) to go in the place. */
99059e56
RM		 10901 if (r_type == R_ARM_LDRS_PC_G0
10902 || r_type == R_ARM_LDRS_PC_G1
10903 || r_type == R_ARM_LDRS_PC_G2)
10904 /* PC relative. */
10905 signed_value = value - pc + signed_addend;
10906 else
10907 /* Section base relative. */
10908 signed_value = value - sb + signed_addend;
10909
10910 /* Calculate the value of the relevant G_{n-1} to obtain
10911 the residual at that stage. */
b6518b38
NC		 10912 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
10913 group - 1, &residual);
99059e56
RM		 10914
10915 /* Check for overflow. */
10916 if (residual >= 0x100)
10917 {
10918 (*_bfd_error_handler)
10919 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 10920 input_bfd, input_section,
10921 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 10922 return bfd_reloc_overflow;
10923 }
10924
10925 /* Mask out the value and U bit. */
10926 insn &= 0xff7ff0f0;
10927
10928 /* Set the U bit if the value to go in the place is non-negative. */
10929 if (signed_value >= 0)
10930 insn |= 1 << 23;
10931
10932 /* Encode the offset. */
10933 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 10934
10935 bfd_put_32 (input_bfd, insn, hit_data);
10936 }
10937 return bfd_reloc_ok;
10938
10939 case R_ARM_LDC_PC_G0:
10940 case R_ARM_LDC_PC_G1:
10941 case R_ARM_LDC_PC_G2:
10942 case R_ARM_LDC_SB_G0:
10943 case R_ARM_LDC_SB_G1:
10944 case R_ARM_LDC_SB_G2:
10945 {
10946 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10947 bfd_vma pc = input_section->output_section->vma
4962c51a 10948 + input_section->output_offset + rel->r_offset;
31a91d61 10949 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10950 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 10951 bfd_vma residual;
4962c51a 10952 bfd_signed_vma signed_value;
99059e56
RM		 10953 int group = 0;
10954
10955 /* Determine which groups of bits to calculate. */
10956 switch (r_type)
10957 {
10958 case R_ARM_LDC_PC_G0:
10959 case R_ARM_LDC_SB_G0:
10960 group = 0;
10961 break;
10962
10963 case R_ARM_LDC_PC_G1:
10964 case R_ARM_LDC_SB_G1:
10965 group = 1;
10966 break;
10967
10968 case R_ARM_LDC_PC_G2:
10969 case R_ARM_LDC_SB_G2:
10970 group = 2;
10971 break;
10972
10973 default:
10974 abort ();
10975 }
10976
10977 /* If REL, extract the addend from the insn. If RELA, it will
10978 have already been fetched for us. */
4962c51a 10979 if (globals->use_rel)
99059e56
RM		 10980 {
10981 int negative = (insn & (1 << 23)) ? 1 : -1;
10982 signed_addend = negative * ((insn & 0xff) << 2);
10983 }
4962c51a
MS		 10984
10985 /* Compute the value (X) to go in the place. */
99059e56
RM		 10986 if (r_type == R_ARM_LDC_PC_G0
10987 || r_type == R_ARM_LDC_PC_G1
10988 || r_type == R_ARM_LDC_PC_G2)
10989 /* PC relative. */
10990 signed_value = value - pc + signed_addend;
10991 else
10992 /* Section base relative. */
10993 signed_value = value - sb + signed_addend;
10994
10995 /* Calculate the value of the relevant G_{n-1} to obtain
10996 the residual at that stage. */
b6518b38
NC		 10997 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
10998 group - 1, &residual);
99059e56
RM		 10999
11000 /* Check for overflow. (The absolute value to go in the place must be
11001 divisible by four and, after having been divided by four, must
11002 fit in eight bits.) */
11003 if ((residual & 0x3) != 0 || residual >= 0x400)
11004 {
11005 (*_bfd_error_handler)
11006 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
11007 input_bfd, input_section,
b6518b38 11008 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11009 return bfd_reloc_overflow;
11010 }
11011
11012 /* Mask out the value and U bit. */
11013 insn &= 0xff7fff00;
11014
11015 /* Set the U bit if the value to go in the place is non-negative. */
11016 if (signed_value >= 0)
11017 insn |= 1 << 23;
11018
11019 /* Encode the offset. */
11020 insn |= residual >> 2;
4962c51a
MS		 11021
11022 bfd_put_32 (input_bfd, insn, hit_data);
11023 }
11024 return bfd_reloc_ok;
11025
252b5132
RH		 11026 default:
11027 return bfd_reloc_notsupported;
11028 }
11029}
11030
98c1d4aa
NC		 11031/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
11032static void
57e8b36a
NC		 11033arm_add_to_rel (bfd * abfd,
11034 bfd_byte * address,
11035 reloc_howto_type * howto,
11036 bfd_signed_vma increment)
98c1d4aa 11037{
98c1d4aa
NC		 11038 bfd_signed_vma addend;
11039
bd97cb95
DJ		 11040 if (howto->type == R_ARM_THM_CALL
11041 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 11042 {
9a5aca8c
AM		 11043 int upper_insn, lower_insn;
11044 int upper, lower;
98c1d4aa 11045
9a5aca8c
AM		 11046 upper_insn = bfd_get_16 (abfd, address);
11047 lower_insn = bfd_get_16 (abfd, address + 2);
11048 upper = upper_insn & 0x7ff;
11049 lower = lower_insn & 0x7ff;
11050
11051 addend = (upper << 12) | (lower << 1);
ddda4409 11052 addend += increment;
9a5aca8c 11053 addend >>= 1;
98c1d4aa 11054
9a5aca8c
AM		 11055 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
11056 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
11057
dc810e39
AM		 11058 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
11059 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 11060 }
11061 else
11062 {
11063 bfd_vma contents;
11064
11065 contents = bfd_get_32 (abfd, address);
11066
11067 /* Get the (signed) value from the instruction. */
11068 addend = contents & howto->src_mask;
11069 if (addend & ((howto->src_mask + 1) >> 1))
11070 {
11071 bfd_signed_vma mask;
11072
11073 mask = -1;
11074 mask &= ~ howto->src_mask;
11075 addend |= mask;
11076 }
11077
11078 /* Add in the increment, (which is a byte value). */
11079 switch (howto->type)
11080 {
11081 default:
11082 addend += increment;
11083 break;
11084
11085 case R_ARM_PC24:
c6596c5e 11086 case R_ARM_PLT32:
5b5bb741
PB		 11087 case R_ARM_CALL:
11088 case R_ARM_JUMP24:
9a5aca8c 11089 addend <<= howto->size;
dc810e39 11090 addend += increment;
9a5aca8c
AM		 11091
11092 /* Should we check for overflow here ? */
11093
11094 /* Drop any undesired bits. */
11095 addend >>= howto->rightshift;
11096 break;
11097 }
11098
11099 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
11100
11101 bfd_put_32 (abfd, contents, address);
ddda4409 11102 }
98c1d4aa 11103}
252b5132 11104
ba93b8ac
DJ		 11105#define IS_ARM_TLS_RELOC(R_TYPE) \
11106 ((R_TYPE) == R_ARM_TLS_GD32 \
11107 || (R_TYPE) == R_ARM_TLS_LDO32 \
11108 || (R_TYPE) == R_ARM_TLS_LDM32 \
11109 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
11110 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
11111 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
11112 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 11113 || (R_TYPE) == R_ARM_TLS_IE32 \
11114 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
11115
11116/* Specific set of relocations for the gnu tls dialect. */
11117#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
11118 ((R_TYPE) == R_ARM_TLS_GOTDESC \
11119 || (R_TYPE) == R_ARM_TLS_CALL \
11120 || (R_TYPE) == R_ARM_THM_TLS_CALL \
11121 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
11122 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 11123
252b5132 11124/* Relocate an ARM ELF section. */
906e58ca 11125
b34976b6 11126static bfd_boolean
57e8b36a
NC		 11127elf32_arm_relocate_section (bfd * output_bfd,
11128 struct bfd_link_info * info,
11129 bfd * input_bfd,
11130 asection * input_section,
11131 bfd_byte * contents,
11132 Elf_Internal_Rela * relocs,
11133 Elf_Internal_Sym * local_syms,
11134 asection ** local_sections)
252b5132 11135{
b34976b6
AM		 11136 Elf_Internal_Shdr *symtab_hdr;
11137 struct elf_link_hash_entry **sym_hashes;
11138 Elf_Internal_Rela *rel;
11139 Elf_Internal_Rela *relend;
11140 const char *name;
b32d3aa2 11141 struct elf32_arm_link_hash_table * globals;
252b5132 11142
4e7fd91e 11143 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 11144 if (globals == NULL)
11145 return FALSE;
b491616a 11146
0ffa91dd 11147 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 11148 sym_hashes = elf_sym_hashes (input_bfd);
11149
11150 rel = relocs;
11151 relend = relocs + input_section->reloc_count;
11152 for (; rel < relend; rel++)
11153 {
ba96a88f
NC		 11154 int r_type;
11155 reloc_howto_type * howto;
11156 unsigned long r_symndx;
11157 Elf_Internal_Sym * sym;
11158 asection * sec;
252b5132 11159 struct elf_link_hash_entry * h;
ba96a88f
NC		 11160 bfd_vma relocation;
11161 bfd_reloc_status_type r;
11162 arelent bfd_reloc;
ba93b8ac 11163 char sym_type;
0945cdfd 11164 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 11165 char *error_message = NULL;
f21f3fe0 11166
252b5132 11167 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 11168 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 11169 r_type = arm_real_reloc_type (globals, r_type);
252b5132 11170
ba96a88f 11171 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 11172 || r_type == R_ARM_GNU_VTINHERIT)
11173 continue;
252b5132 11174
b32d3aa2 11175 bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
ba96a88f 11176 howto = bfd_reloc.howto;
252b5132 11177
252b5132
RH		 11178 h = NULL;
11179 sym = NULL;
11180 sec = NULL;
9b485d32 11181
252b5132
RH		 11182 if (r_symndx < symtab_hdr->sh_info)
11183 {
11184 sym = local_syms + r_symndx;
ba93b8ac 11185 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 11186 sec = local_sections[r_symndx];
ffcb4889
NS		 11187
11188 /* An object file might have a reference to a local
11189 undefined symbol. This is a daft object file, but we
11190 should at least do something about it. V4BX & NONE
11191 relocations do not use the symbol and are explicitly
77b4f08f
TS		 11192 allowed to use the undefined symbol, so allow those.
11193 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 11194 if (r_type != R_ARM_V4BX
11195 && r_type != R_ARM_NONE
77b4f08f 11196 && r_symndx != STN_UNDEF
ffcb4889
NS		 11197 && bfd_is_und_section (sec)
11198 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
11199 {
11200 if (!info->callbacks->undefined_symbol
11201 (info, bfd_elf_string_from_elf_section
11202 (input_bfd, symtab_hdr->sh_link, sym->st_name),
11203 input_bfd, input_section,
11204 rel->r_offset, TRUE))
11205 return FALSE;
11206 }
b38cadfb 11207
4e7fd91e 11208 if (globals->use_rel)
f8df10f4 11209 {
4e7fd91e
PB		 11210 relocation = (sec->output_section->vma
11211 + sec->output_offset
11212 + sym->st_value);
0e1862bb 11213 if (!bfd_link_relocatable (info)
ab96bf03
AM		 11214 && (sec->flags & SEC_MERGE)
11215 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 11216 {
4e7fd91e
PB		 11217 asection *msec;
11218 bfd_vma addend, value;
11219
39623e12 11220 switch (r_type)
4e7fd91e 11221 {
39623e12
PB		 11222 case R_ARM_MOVW_ABS_NC:
11223 case R_ARM_MOVT_ABS:
11224 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
11225 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
11226 addend = (addend ^ 0x8000) - 0x8000;
11227 break;
f8df10f4 11228
39623e12
PB		 11229 case R_ARM_THM_MOVW_ABS_NC:
11230 case R_ARM_THM_MOVT_ABS:
11231 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
11232 << 16;
11233 value |= bfd_get_16 (input_bfd,
11234 contents + rel->r_offset + 2);
11235 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
11236 | ((value & 0x04000000) >> 15);
11237 addend = (addend ^ 0x8000) - 0x8000;
11238 break;
f8df10f4 11239
39623e12
PB		 11240 default:
11241 if (howto->rightshift
11242 || (howto->src_mask & (howto->src_mask + 1)))
11243 {
11244 (*_bfd_error_handler)
11245 (_("%B(%A+0x%lx): %s relocation against SEC_MERGE section"),
11246 input_bfd, input_section,
11247 (long) rel->r_offset, howto->name);
11248 return FALSE;
11249 }
11250
11251 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
11252
11253 /* Get the (signed) value from the instruction. */
11254 addend = value & howto->src_mask;
11255 if (addend & ((howto->src_mask + 1) >> 1))
11256 {
11257 bfd_signed_vma mask;
11258
11259 mask = -1;
11260 mask &= ~ howto->src_mask;
11261 addend |= mask;
11262 }
11263 break;
4e7fd91e 11264 }
39623e12 11265
4e7fd91e
PB		 11266 msec = sec;
11267 addend =
11268 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
11269 - relocation;
11270 addend += msec->output_section->vma + msec->output_offset;
39623e12 11271
cc643b88 11272 /* Cases here must match those in the preceding
39623e12
PB		 11273 switch statement. */
11274 switch (r_type)
11275 {
11276 case R_ARM_MOVW_ABS_NC:
11277 case R_ARM_MOVT_ABS:
11278 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
11279 | (addend & 0xfff);
11280 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
11281 break;
11282
11283 case R_ARM_THM_MOVW_ABS_NC:
11284 case R_ARM_THM_MOVT_ABS:
11285 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
11286 | (addend & 0xff) | ((addend & 0x0800) << 15);
11287 bfd_put_16 (input_bfd, value >> 16,
11288 contents + rel->r_offset);
11289 bfd_put_16 (input_bfd, value,
11290 contents + rel->r_offset + 2);
11291 break;
11292
11293 default:
11294 value = (value & ~ howto->dst_mask)
11295 | (addend & howto->dst_mask);
11296 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
11297 break;
11298 }
f8df10f4 11299 }
f8df10f4 11300 }
4e7fd91e
PB		 11301 else
11302 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 11303 }
11304 else
11305 {
62d887d4 11306 bfd_boolean warned, ignored;
560e09e9 11307
b2a8e766
AM		 11308 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
11309 r_symndx, symtab_hdr, sym_hashes,
11310 h, sec, relocation,
62d887d4 11311 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 11312
11313 sym_type = h->type;
252b5132
RH		 11314 }
11315
dbaa2011 11316 if (sec != NULL && discarded_section (sec))
e4067dbb 11317 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 11318 rel, 1, relend, howto, 0, contents);
ab96bf03 11319
0e1862bb 11320 if (bfd_link_relocatable (info))
ab96bf03
AM		 11321 {
11322 /* This is a relocatable link. We don't have to change
11323 anything, unless the reloc is against a section symbol,
11324 in which case we have to adjust according to where the
11325 section symbol winds up in the output section. */
11326 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
11327 {
11328 if (globals->use_rel)
11329 arm_add_to_rel (input_bfd, contents + rel->r_offset,
11330 howto, (bfd_signed_vma) sec->output_offset);
11331 else
11332 rel->r_addend += sec->output_offset;
11333 }
11334 continue;
11335 }
11336
252b5132
RH		 11337 if (h != NULL)
11338 name = h->root.root.string;
11339 else
11340 {
11341 name = (bfd_elf_string_from_elf_section
11342 (input_bfd, symtab_hdr->sh_link, sym->st_name));
11343 if (name == NULL || *name == '\0')
11344 name = bfd_section_name (input_bfd, sec);
11345 }
f21f3fe0 11346
cf35638d 11347 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 11348 && r_type != R_ARM_NONE
11349 && (h == NULL
11350 || h->root.type == bfd_link_hash_defined
11351 || h->root.type == bfd_link_hash_defweak)
11352 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
11353 {
11354 (*_bfd_error_handler)
11355 ((sym_type == STT_TLS
11356 ? _("%B(%A+0x%lx): %s used with TLS symbol %s")
11357 : _("%B(%A+0x%lx): %s used with non-TLS symbol %s")),
11358 input_bfd,
11359 input_section,
11360 (long) rel->r_offset,
11361 howto->name,
11362 name);
11363 }
11364
0855e32b 11365 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 11366 done, i.e., the relaxation produced the final output we want,
11367 and we won't let anybody mess with it. Also, we have to do
11368 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 11369 both in relaxed and non-relaxed cases. */
0855e32b
NS		 11370 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
11371 || (IS_ARM_TLS_GNU_RELOC (r_type)
b38cadfb 11372 && !((h ? elf32_arm_hash_entry (h)->tls_type :
0855e32b
NS		 11373 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
11374 & GOT_TLS_GDESC)))
11375 {
11376 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
11377 contents, rel, h == NULL);
11378 /* This may have been marked unresolved because it came from
11379 a shared library. But we've just dealt with that. */
11380 unresolved_reloc = 0;
11381 }
11382 else
11383 r = bfd_reloc_continue;
b38cadfb 11384
0855e32b
NS		 11385 if (r == bfd_reloc_continue)
11386 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
11387 input_section, contents, rel,
34e77a92 11388 relocation, info, sec, name, sym_type,
35fc36a8
RS		 11389 (h ? h->target_internal
11390 : ARM_SYM_BRANCH_TYPE (sym)), h,
0855e32b 11391 &unresolved_reloc, &error_message);
0945cdfd
DJ		 11392
11393 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
11394 because such sections are not SEC_ALLOC and thus ld.so will
11395 not process them. */
11396 if (unresolved_reloc
99059e56
RM		 11397 && !((input_section->flags & SEC_DEBUGGING) != 0
11398 && h->def_dynamic)
1d5316ab
AM		 11399 && _bfd_elf_section_offset (output_bfd, info, input_section,
11400 rel->r_offset) != (bfd_vma) -1)
0945cdfd
DJ		 11401 {
11402 (*_bfd_error_handler)
843fe662
L		 11403 (_("%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"),
11404 input_bfd,
11405 input_section,
11406 (long) rel->r_offset,
11407 howto->name,
11408 h->root.root.string);
0945cdfd
DJ		 11409 return FALSE;
11410 }
252b5132
RH		 11411
11412 if (r != bfd_reloc_ok)
11413 {
252b5132
RH		 11414 switch (r)
11415 {
11416 case bfd_reloc_overflow:
cf919dfd
PB		 11417 /* If the overflowing reloc was to an undefined symbol,
11418 we have already printed one error message and there
11419 is no point complaining again. */
11420 if ((! h ||
11421 h->root.type != bfd_link_hash_undefined)
11422 && (!((*info->callbacks->reloc_overflow)
dfeffb9f
L		 11423 (info, (h ? &h->root : NULL), name, howto->name,
11424 (bfd_vma) 0, input_bfd, input_section,
11425 rel->r_offset))))
b34976b6 11426 return FALSE;
252b5132
RH		 11427 break;
11428
11429 case bfd_reloc_undefined:
11430 if (!((*info->callbacks->undefined_symbol)
11431 (info, name, input_bfd, input_section,
b34976b6
AM		 11432 rel->r_offset, TRUE)))
11433 return FALSE;
252b5132
RH		 11434 break;
11435
11436 case bfd_reloc_outofrange:
f2a9dd69 11437 error_message = _("out of range");
252b5132
RH		 11438 goto common_error;
11439
11440 case bfd_reloc_notsupported:
f2a9dd69 11441 error_message = _("unsupported relocation");
252b5132
RH		 11442 goto common_error;
11443
11444 case bfd_reloc_dangerous:
f2a9dd69 11445 /* error_message should already be set. */
252b5132
RH		 11446 goto common_error;
11447
11448 default:
f2a9dd69 11449 error_message = _("unknown error");
8029a119 11450 /* Fall through. */
252b5132
RH		 11451
11452 common_error:
f2a9dd69
DJ		 11453 BFD_ASSERT (error_message != NULL);
11454 if (!((*info->callbacks->reloc_dangerous)
11455 (info, error_message, input_bfd, input_section,
252b5132 11456 rel->r_offset)))
b34976b6 11457 return FALSE;
252b5132
RH		 11458 break;
11459 }
11460 }
11461 }
11462
b34976b6 11463 return TRUE;
252b5132
RH		 11464}
11465
91d6fa6a 11466/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 11467 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 11468 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 11469 maintaining that condition). */
11470
11471static void
11472add_unwind_table_edit (arm_unwind_table_edit **head,
11473 arm_unwind_table_edit **tail,
11474 arm_unwind_edit_type type,
11475 asection *linked_section,
91d6fa6a 11476 unsigned int tindex)
2468f9c9 11477{
21d799b5
NC		 11478 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
11479 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 11480
2468f9c9
PB		 11481 new_edit->type = type;
11482 new_edit->linked_section = linked_section;
91d6fa6a 11483 new_edit->index = tindex;
b38cadfb 11484
91d6fa6a 11485 if (tindex > 0)
2468f9c9
PB		 11486 {
11487 new_edit->next = NULL;
11488
11489 if (*tail)
11490 (*tail)->next = new_edit;
11491
11492 (*tail) = new_edit;
11493
11494 if (!*head)
11495 (*head) = new_edit;
11496 }
11497 else
11498 {
11499 new_edit->next = *head;
11500
11501 if (!*tail)
11502 *tail = new_edit;
11503
11504 *head = new_edit;
11505 }
11506}
11507
11508static _arm_elf_section_data *get_arm_elf_section_data (asection *);
11509
11510/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
11511static void
11512adjust_exidx_size(asection *exidx_sec, int adjust)
11513{
11514 asection *out_sec;
11515
11516 if (!exidx_sec->rawsize)
11517 exidx_sec->rawsize = exidx_sec->size;
11518
11519 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
11520 out_sec = exidx_sec->output_section;
11521 /* Adjust size of output section. */
11522 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
11523}
11524
11525/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
11526static void
11527insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
11528{
11529 struct _arm_elf_section_data *exidx_arm_data;
11530
11531 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
11532 add_unwind_table_edit (
11533 &exidx_arm_data->u.exidx.unwind_edit_list,
11534 &exidx_arm_data->u.exidx.unwind_edit_tail,
11535 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
11536
11537 adjust_exidx_size(exidx_sec, 8);
11538}
11539
11540/* Scan .ARM.exidx tables, and create a list describing edits which should be
11541 made to those tables, such that:
b38cadfb 11542
2468f9c9
PB		 11543 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
11544 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 11545 codes which have been inlined into the index).
2468f9c9 11546
85fdf906
AH		 11547 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
11548
2468f9c9 11549 The edits are applied when the tables are written
b38cadfb 11550 (in elf32_arm_write_section). */
2468f9c9
PB		 11551
11552bfd_boolean
11553elf32_arm_fix_exidx_coverage (asection **text_section_order,
11554 unsigned int num_text_sections,
85fdf906
AH		 11555 struct bfd_link_info *info,
11556 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 11557{
11558 bfd *inp;
11559 unsigned int last_second_word = 0, i;
11560 asection *last_exidx_sec = NULL;
11561 asection *last_text_sec = NULL;
11562 int last_unwind_type = -1;
11563
11564 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
11565 text sections. */
c72f2fb2 11566 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 11567 {
11568 asection *sec;
b38cadfb 11569
2468f9c9 11570 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 11571 {
2468f9c9
PB		 11572 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
11573 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 11574
dec9d5df 11575 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 11576 continue;
b38cadfb 11577
2468f9c9
PB		 11578 if (elf_sec->linked_to)
11579 {
11580 Elf_Internal_Shdr *linked_hdr
99059e56 11581 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 11582 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 11583 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 11584
11585 if (linked_sec_arm_data == NULL)
99059e56 11586 continue;
2468f9c9
PB		 11587
11588 /* Link this .ARM.exidx section back from the text section it
99059e56 11589 describes. */
2468f9c9
PB		 11590 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
11591 }
11592 }
11593 }
11594
11595 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
11596 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 11597 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 11598
11599 for (i = 0; i < num_text_sections; i++)
11600 {
11601 asection *sec = text_section_order[i];
11602 asection *exidx_sec;
11603 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
11604 struct _arm_elf_section_data *exidx_arm_data;
11605 bfd_byte *contents = NULL;
11606 int deleted_exidx_bytes = 0;
11607 bfd_vma j;
11608 arm_unwind_table_edit *unwind_edit_head = NULL;
11609 arm_unwind_table_edit *unwind_edit_tail = NULL;
11610 Elf_Internal_Shdr *hdr;
11611 bfd *ibfd;
11612
11613 if (arm_data == NULL)
99059e56 11614 continue;
2468f9c9
PB		 11615
11616 exidx_sec = arm_data->u.text.arm_exidx_sec;
11617 if (exidx_sec == NULL)
11618 {
11619 /* Section has no unwind data. */
11620 if (last_unwind_type == 0 || !last_exidx_sec)
11621 continue;
11622
11623 /* Ignore zero sized sections. */
11624 if (sec->size == 0)
11625 continue;
11626
11627 insert_cantunwind_after(last_text_sec, last_exidx_sec);
11628 last_unwind_type = 0;
11629 continue;
11630 }
11631
22a8f80e
PB		 11632 /* Skip /DISCARD/ sections. */
11633 if (bfd_is_abs_section (exidx_sec->output_section))
11634 continue;
11635
2468f9c9
PB		 11636 hdr = &elf_section_data (exidx_sec)->this_hdr;
11637 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 11638 continue;
b38cadfb 11639
2468f9c9
PB		 11640 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
11641 if (exidx_arm_data == NULL)
99059e56 11642 continue;
b38cadfb 11643
2468f9c9 11644 ibfd = exidx_sec->owner;
b38cadfb 11645
2468f9c9
PB		 11646 if (hdr->contents != NULL)
11647 contents = hdr->contents;
11648 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
11649 /* An error? */
11650 continue;
11651
11652 for (j = 0; j < hdr->sh_size; j += 8)
11653 {
11654 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
11655 int unwind_type;
11656 int elide = 0;
11657
11658 /* An EXIDX_CANTUNWIND entry. */
11659 if (second_word == 1)
11660 {
11661 if (last_unwind_type == 0)
11662 elide = 1;
11663 unwind_type = 0;
11664 }
11665 /* Inlined unwinding data. Merge if equal to previous. */
11666 else if ((second_word & 0x80000000) != 0)
11667 {
85fdf906
AH		 11668 if (merge_exidx_entries
11669 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 11670 elide = 1;
11671 unwind_type = 1;
11672 last_second_word = second_word;
11673 }
11674 /* Normal table entry. In theory we could merge these too,
11675 but duplicate entries are likely to be much less common. */
11676 else
11677 unwind_type = 2;
11678
11679 if (elide)
11680 {
11681 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
11682 DELETE_EXIDX_ENTRY, NULL, j / 8);
11683
11684 deleted_exidx_bytes += 8;
11685 }
11686
11687 last_unwind_type = unwind_type;
11688 }
11689
11690 /* Free contents if we allocated it ourselves. */
11691 if (contents != hdr->contents)
99059e56 11692 free (contents);
2468f9c9
PB		 11693
11694 /* Record edits to be applied later (in elf32_arm_write_section). */
11695 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
11696 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 11697
2468f9c9
PB		 11698 if (deleted_exidx_bytes > 0)
11699 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
11700
11701 last_exidx_sec = exidx_sec;
11702 last_text_sec = sec;
11703 }
11704
11705 /* Add terminating CANTUNWIND entry. */
11706 if (last_exidx_sec && last_unwind_type != 0)
11707 insert_cantunwind_after(last_text_sec, last_exidx_sec);
11708
11709 return TRUE;
11710}
11711
3e6b1042
DJ		 11712static bfd_boolean
11713elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
11714 bfd *ibfd, const char *name)
11715{
11716 asection *sec, *osec;
11717
3d4d4302 11718 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 11719 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
11720 return TRUE;
11721
11722 osec = sec->output_section;
11723 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
11724 return TRUE;
11725
11726 if (! bfd_set_section_contents (obfd, osec, sec->contents,
11727 sec->output_offset, sec->size))
11728 return FALSE;
11729
11730 return TRUE;
11731}
11732
11733static bfd_boolean
11734elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
11735{
11736 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 11737 asection *sec, *osec;
3e6b1042 11738
4dfe6ac6
NC		 11739 if (globals == NULL)
11740 return FALSE;
11741
3e6b1042
DJ		 11742 /* Invoke the regular ELF backend linker to do all the work. */
11743 if (!bfd_elf_final_link (abfd, info))
11744 return FALSE;
11745
fe33d2fa
CL		 11746 /* Process stub sections (eg BE8 encoding, ...). */
11747 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 11748 unsigned int i;
cdb21a0a
NS		 11749 for (i=0; i<htab->top_id; i++)
11750 {
11751 sec = htab->stub_group[i].stub_sec;
11752 /* Only process it once, in its link_sec slot. */
11753 if (sec && i == htab->stub_group[i].link_sec->id)
11754 {
11755 osec = sec->output_section;
11756 elf32_arm_write_section (abfd, info, sec, sec->contents);
11757 if (! bfd_set_section_contents (abfd, osec, sec->contents,
11758 sec->output_offset, sec->size))
11759 return FALSE;
11760 }
fe33d2fa 11761 }
fe33d2fa 11762
3e6b1042
DJ		 11763 /* Write out any glue sections now that we have created all the
11764 stubs. */
11765 if (globals->bfd_of_glue_owner != NULL)
11766 {
11767 if (! elf32_arm_output_glue_section (info, abfd,
11768 globals->bfd_of_glue_owner,
11769 ARM2THUMB_GLUE_SECTION_NAME))
11770 return FALSE;
11771
11772 if (! elf32_arm_output_glue_section (info, abfd,
11773 globals->bfd_of_glue_owner,
11774 THUMB2ARM_GLUE_SECTION_NAME))
11775 return FALSE;
11776
11777 if (! elf32_arm_output_glue_section (info, abfd,
11778 globals->bfd_of_glue_owner,
11779 VFP11_ERRATUM_VENEER_SECTION_NAME))
11780 return FALSE;
11781
a504d23a
LA		 11782 if (! elf32_arm_output_glue_section (info, abfd,
11783 globals->bfd_of_glue_owner,
11784 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
11785 return FALSE;
11786
3e6b1042
DJ		 11787 if (! elf32_arm_output_glue_section (info, abfd,
11788 globals->bfd_of_glue_owner,
11789 ARM_BX_GLUE_SECTION_NAME))
11790 return FALSE;
11791 }
11792
11793 return TRUE;
11794}
11795
5968a7b8
NC		 11796/* Return a best guess for the machine number based on the attributes. */
11797
11798static unsigned int
11799bfd_arm_get_mach_from_attributes (bfd * abfd)
11800{
11801 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
11802
11803 switch (arch)
11804 {
11805 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
11806 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
11807 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
11808
11809 case TAG_CPU_ARCH_V5TE:
11810 {
11811 char * name;
11812
11813 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
11814 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
11815
11816 if (name)
11817 {
11818 if (strcmp (name, "IWMMXT2") == 0)
11819 return bfd_mach_arm_iWMMXt2;
11820
11821 if (strcmp (name, "IWMMXT") == 0)
6034aab8 11822 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 11823
11824 if (strcmp (name, "XSCALE") == 0)
11825 {
11826 int wmmx;
11827
11828 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
11829 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
11830 switch (wmmx)
11831 {
11832 case 1: return bfd_mach_arm_iWMMXt;
11833 case 2: return bfd_mach_arm_iWMMXt2;
11834 default: return bfd_mach_arm_XScale;
11835 }
11836 }
5968a7b8
NC		 11837 }
11838
11839 return bfd_mach_arm_5TE;
11840 }
11841
11842 default:
11843 return bfd_mach_arm_unknown;
11844 }
11845}
11846
c178919b
NC		 11847/* Set the right machine number. */
11848
11849static bfd_boolean
57e8b36a 11850elf32_arm_object_p (bfd *abfd)
c178919b 11851{
5a6c6817 11852 unsigned int mach;
57e8b36a 11853
5a6c6817 11854 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 11855
5968a7b8
NC		 11856 if (mach == bfd_mach_arm_unknown)
11857 {
11858 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
11859 mach = bfd_mach_arm_ep9312;
11860 else
11861 mach = bfd_arm_get_mach_from_attributes (abfd);
11862 }
c178919b 11863
5968a7b8 11864 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 11865 return TRUE;
11866}
11867
fc830a83 11868/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 11869
b34976b6 11870static bfd_boolean
57e8b36a 11871elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 11872{
11873 if (elf_flags_init (abfd)
11874 && elf_elfheader (abfd)->e_flags != flags)
11875 {
fc830a83
NC		 11876 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
11877 {
fd2ec330 11878 if (flags & EF_ARM_INTERWORK)
d003868e
AM		 11879 (*_bfd_error_handler)
11880 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
11881 abfd);
fc830a83 11882 else
d003868e
AM		 11883 _bfd_error_handler
11884 (_("Warning: Clearing the interworking flag of %B due to outside request"),
11885 abfd);
fc830a83 11886 }
252b5132
RH		 11887 }
11888 else
11889 {
11890 elf_elfheader (abfd)->e_flags = flags;
b34976b6 11891 elf_flags_init (abfd) = TRUE;
252b5132
RH		 11892 }
11893
b34976b6 11894 return TRUE;
252b5132
RH		 11895}
11896
fc830a83 11897/* Copy backend specific data from one object module to another. */
9b485d32 11898
b34976b6 11899static bfd_boolean
57e8b36a 11900elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 11901{
11902 flagword in_flags;
11903 flagword out_flags;
11904
0ffa91dd 11905 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 11906 return TRUE;
252b5132 11907
fc830a83 11908 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 11909 out_flags = elf_elfheader (obfd)->e_flags;
11910
fc830a83
NC		 11911 if (elf_flags_init (obfd)
11912 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
11913 && in_flags != out_flags)
252b5132 11914 {
252b5132 11915 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 11916 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 11917 return FALSE;
252b5132
RH		 11918
11919 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 11920 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 11921 return FALSE;
252b5132
RH		 11922
11923 /* If the src and dest have different interworking flags
99059e56 11924 then turn off the interworking bit. */
fd2ec330 11925 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 11926 {
fd2ec330 11927 if (out_flags & EF_ARM_INTERWORK)
d003868e
AM		 11928 _bfd_error_handler
11929 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
11930 obfd, ibfd);
252b5132 11931
fd2ec330 11932 in_flags &= ~EF_ARM_INTERWORK;
252b5132 11933 }
1006ba19
PB		 11934
11935 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 11936 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
11937 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 11938 }
11939
11940 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 11941 elf_flags_init (obfd) = TRUE;
252b5132 11942
e2349352 11943 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 11944}
11945
11946/* Values for Tag_ABI_PCS_R9_use. */
11947enum
11948{
11949 AEABI_R9_V6,
11950 AEABI_R9_SB,
11951 AEABI_R9_TLS,
11952 AEABI_R9_unused
11953};
11954
11955/* Values for Tag_ABI_PCS_RW_data. */
11956enum
11957{
11958 AEABI_PCS_RW_data_absolute,
11959 AEABI_PCS_RW_data_PCrel,
11960 AEABI_PCS_RW_data_SBrel,
11961 AEABI_PCS_RW_data_unused
11962};
11963
11964/* Values for Tag_ABI_enum_size. */
11965enum
11966{
11967 AEABI_enum_unused,
11968 AEABI_enum_short,
11969 AEABI_enum_wide,
11970 AEABI_enum_forced_wide
11971};
11972
104d59d1
JM		 11973/* Determine whether an object attribute tag takes an integer, a
11974 string or both. */
906e58ca 11975
104d59d1
JM		 11976static int
11977elf32_arm_obj_attrs_arg_type (int tag)
11978{
11979 if (tag == Tag_compatibility)
3483fe2e 11980 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 11981 else if (tag == Tag_nodefaults)
3483fe2e
AS		 11982 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
11983 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
11984 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 11985 else if (tag < 32)
3483fe2e 11986 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 11987 else
3483fe2e 11988 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 11989}
11990
5aa6ff7c
AS		 11991/* The ABI defines that Tag_conformance should be emitted first, and that
11992 Tag_nodefaults should be second (if either is defined). This sets those
11993 two positions, and bumps up the position of all the remaining tags to
11994 compensate. */
11995static int
11996elf32_arm_obj_attrs_order (int num)
11997{
3de4a297 11998 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 11999 return Tag_conformance;
3de4a297 12000 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 12001 return Tag_nodefaults;
12002 if ((num - 2) < Tag_nodefaults)
12003 return num - 2;
12004 if ((num - 1) < Tag_conformance)
12005 return num - 1;
12006 return num;
12007}
12008
e8b36cd1
JM		 12009/* Attribute numbers >=64 (mod 128) can be safely ignored. */
12010static bfd_boolean
12011elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
12012{
12013 if ((tag & 127) < 64)
12014 {
12015 _bfd_error_handler
12016 (_("%B: Unknown mandatory EABI object attribute %d"),
12017 abfd, tag);
12018 bfd_set_error (bfd_error_bad_value);
12019 return FALSE;
12020 }
12021 else
12022 {
12023 _bfd_error_handler
12024 (_("Warning: %B: Unknown EABI object attribute %d"),
12025 abfd, tag);
12026 return TRUE;
12027 }
12028}
12029
91e22acd
AS		 12030/* Read the architecture from the Tag_also_compatible_with attribute, if any.
12031 Returns -1 if no architecture could be read. */
12032
12033static int
12034get_secondary_compatible_arch (bfd *abfd)
12035{
12036 obj_attribute *attr =
12037 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
12038
12039 /* Note: the tag and its argument below are uleb128 values, though
12040 currently-defined values fit in one byte for each. */
12041 if (attr->s
12042 && attr->s[0] == Tag_CPU_arch
12043 && (attr->s[1] & 128) != 128
12044 && attr->s[2] == 0)
12045 return attr->s[1];
12046
12047 /* This tag is "safely ignorable", so don't complain if it looks funny. */
12048 return -1;
12049}
12050
12051/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
12052 The tag is removed if ARCH is -1. */
12053
8e79c3df 12054static void
91e22acd 12055set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 12056{
91e22acd
AS		 12057 obj_attribute *attr =
12058 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 12059
91e22acd
AS		 12060 if (arch == -1)
12061 {
12062 attr->s = NULL;
12063 return;
8e79c3df 12064 }
91e22acd
AS		 12065
12066 /* Note: the tag and its argument below are uleb128 values, though
12067 currently-defined values fit in one byte for each. */
12068 if (!attr->s)
21d799b5 12069 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 12070 attr->s[0] = Tag_CPU_arch;
12071 attr->s[1] = arch;
12072 attr->s[2] = '\0';
8e79c3df
CM		 12073}
12074
91e22acd
AS		 12075/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
12076 into account. */
12077
12078static int
12079tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
12080 int newtag, int secondary_compat)
8e79c3df 12081{
91e22acd
AS		 12082#define T(X) TAG_CPU_ARCH_##X
12083 int tagl, tagh, result;
12084 const int v6t2[] =
12085 {
12086 T(V6T2), /* PRE_V4. */
12087 T(V6T2), /* V4. */
12088 T(V6T2), /* V4T. */
12089 T(V6T2), /* V5T. */
12090 T(V6T2), /* V5TE. */
12091 T(V6T2), /* V5TEJ. */
12092 T(V6T2), /* V6. */
12093 T(V7), /* V6KZ. */
12094 T(V6T2) /* V6T2. */
12095 };
12096 const int v6k[] =
12097 {
12098 T(V6K), /* PRE_V4. */
12099 T(V6K), /* V4. */
12100 T(V6K), /* V4T. */
12101 T(V6K), /* V5T. */
12102 T(V6K), /* V5TE. */
12103 T(V6K), /* V5TEJ. */
12104 T(V6K), /* V6. */
12105 T(V6KZ), /* V6KZ. */
12106 T(V7), /* V6T2. */
12107 T(V6K) /* V6K. */
12108 };
12109 const int v7[] =
12110 {
12111 T(V7), /* PRE_V4. */
12112 T(V7), /* V4. */
12113 T(V7), /* V4T. */
12114 T(V7), /* V5T. */
12115 T(V7), /* V5TE. */
12116 T(V7), /* V5TEJ. */
12117 T(V7), /* V6. */
12118 T(V7), /* V6KZ. */
12119 T(V7), /* V6T2. */
12120 T(V7), /* V6K. */
12121 T(V7) /* V7. */
12122 };
12123 const int v6_m[] =
12124 {
12125 -1, /* PRE_V4. */
12126 -1, /* V4. */
12127 T(V6K), /* V4T. */
12128 T(V6K), /* V5T. */
12129 T(V6K), /* V5TE. */
12130 T(V6K), /* V5TEJ. */
12131 T(V6K), /* V6. */
12132 T(V6KZ), /* V6KZ. */
12133 T(V7), /* V6T2. */
12134 T(V6K), /* V6K. */
12135 T(V7), /* V7. */
12136 T(V6_M) /* V6_M. */
12137 };
12138 const int v6s_m[] =
12139 {
12140 -1, /* PRE_V4. */
12141 -1, /* V4. */
12142 T(V6K), /* V4T. */
12143 T(V6K), /* V5T. */
12144 T(V6K), /* V5TE. */
12145 T(V6K), /* V5TEJ. */
12146 T(V6K), /* V6. */
12147 T(V6KZ), /* V6KZ. */
12148 T(V7), /* V6T2. */
12149 T(V6K), /* V6K. */
12150 T(V7), /* V7. */
12151 T(V6S_M), /* V6_M. */
12152 T(V6S_M) /* V6S_M. */
12153 };
9e3c6df6
PB		 12154 const int v7e_m[] =
12155 {
12156 -1, /* PRE_V4. */
12157 -1, /* V4. */
12158 T(V7E_M), /* V4T. */
12159 T(V7E_M), /* V5T. */
12160 T(V7E_M), /* V5TE. */
12161 T(V7E_M), /* V5TEJ. */
12162 T(V7E_M), /* V6. */
12163 T(V7E_M), /* V6KZ. */
12164 T(V7E_M), /* V6T2. */
12165 T(V7E_M), /* V6K. */
12166 T(V7E_M), /* V7. */
12167 T(V7E_M), /* V6_M. */
12168 T(V7E_M), /* V6S_M. */
12169 T(V7E_M) /* V7E_M. */
12170 };
bca38921
MGD		 12171 const int v8[] =
12172 {
12173 T(V8), /* PRE_V4. */
12174 T(V8), /* V4. */
12175 T(V8), /* V4T. */
12176 T(V8), /* V5T. */
12177 T(V8), /* V5TE. */
12178 T(V8), /* V5TEJ. */
12179 T(V8), /* V6. */
12180 T(V8), /* V6KZ. */
12181 T(V8), /* V6T2. */
12182 T(V8), /* V6K. */
12183 T(V8), /* V7. */
12184 T(V8), /* V6_M. */
12185 T(V8), /* V6S_M. */
12186 T(V8), /* V7E_M. */
12187 T(V8) /* V8. */
12188 };
91e22acd
AS		 12189 const int v4t_plus_v6_m[] =
12190 {
12191 -1, /* PRE_V4. */
12192 -1, /* V4. */
12193 T(V4T), /* V4T. */
12194 T(V5T), /* V5T. */
12195 T(V5TE), /* V5TE. */
12196 T(V5TEJ), /* V5TEJ. */
12197 T(V6), /* V6. */
12198 T(V6KZ), /* V6KZ. */
12199 T(V6T2), /* V6T2. */
12200 T(V6K), /* V6K. */
12201 T(V7), /* V7. */
12202 T(V6_M), /* V6_M. */
12203 T(V6S_M), /* V6S_M. */
9e3c6df6 12204 T(V7E_M), /* V7E_M. */
bca38921 12205 T(V8), /* V8. */
91e22acd
AS		 12206 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
12207 };
12208 const int *comb[] =
12209 {
12210 v6t2,
12211 v6k,
12212 v7,
12213 v6_m,
12214 v6s_m,
9e3c6df6 12215 v7e_m,
bca38921 12216 v8,
91e22acd
AS		 12217 /* Pseudo-architecture. */
12218 v4t_plus_v6_m
12219 };
12220
12221 /* Check we've not got a higher architecture than we know about. */
12222
9e3c6df6 12223 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 12224 {
3895f852 12225 _bfd_error_handler (_("error: %B: Unknown CPU architecture"), ibfd);
91e22acd
AS		 12226 return -1;
12227 }
12228
12229 /* Override old tag if we have a Tag_also_compatible_with on the output. */
12230
12231 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
12232 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
12233 oldtag = T(V4T_PLUS_V6_M);
12234
12235 /* And override the new tag if we have a Tag_also_compatible_with on the
12236 input. */
12237
12238 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
12239 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
12240 newtag = T(V4T_PLUS_V6_M);
12241
12242 tagl = (oldtag < newtag) ? oldtag : newtag;
12243 result = tagh = (oldtag > newtag) ? oldtag : newtag;
12244
12245 /* Architectures before V6KZ add features monotonically. */
12246 if (tagh <= TAG_CPU_ARCH_V6KZ)
12247 return result;
12248
12249 result = comb[tagh - T(V6T2)][tagl];
12250
12251 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
12252 as the canonical version. */
12253 if (result == T(V4T_PLUS_V6_M))
12254 {
12255 result = T(V4T);
12256 *secondary_compat_out = T(V6_M);
12257 }
12258 else
12259 *secondary_compat_out = -1;
12260
12261 if (result == -1)
12262 {
3895f852 12263 _bfd_error_handler (_("error: %B: Conflicting CPU architectures %d/%d"),
91e22acd
AS		 12264 ibfd, oldtag, newtag);
12265 return -1;
12266 }
12267
12268 return result;
12269#undef T
8e79c3df
CM		 12270}
12271
ac56ee8f
MGD		 12272/* Query attributes object to see if integer divide instructions may be
12273 present in an object. */
12274static bfd_boolean
12275elf32_arm_attributes_accept_div (const obj_attribute *attr)
12276{
12277 int arch = attr[Tag_CPU_arch].i;
12278 int profile = attr[Tag_CPU_arch_profile].i;
12279
12280 switch (attr[Tag_DIV_use].i)
12281 {
12282 case 0:
12283 /* Integer divide allowed if instruction contained in archetecture. */
12284 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
12285 return TRUE;
12286 else if (arch >= TAG_CPU_ARCH_V7E_M)
12287 return TRUE;
12288 else
12289 return FALSE;
12290
12291 case 1:
12292 /* Integer divide explicitly prohibited. */
12293 return FALSE;
12294
12295 default:
12296 /* Unrecognised case - treat as allowing divide everywhere. */
12297 case 2:
12298 /* Integer divide allowed in ARM state. */
12299 return TRUE;
12300 }
12301}
12302
12303/* Query attributes object to see if integer divide instructions are
12304 forbidden to be in the object. This is not the inverse of
12305 elf32_arm_attributes_accept_div. */
12306static bfd_boolean
12307elf32_arm_attributes_forbid_div (const obj_attribute *attr)
12308{
12309 return attr[Tag_DIV_use].i == 1;
12310}
12311
ee065d83
PB		 12312/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
12313 are conflicting attributes. */
906e58ca 12314
ee065d83
PB		 12315static bfd_boolean
12316elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd)
12317{
104d59d1
JM		 12318 obj_attribute *in_attr;
12319 obj_attribute *out_attr;
ee065d83
PB		 12320 /* Some tags have 0 = don't care, 1 = strong requirement,
12321 2 = weak requirement. */
91e22acd 12322 static const int order_021[3] = {0, 2, 1};
ee065d83 12323 int i;
91e22acd 12324 bfd_boolean result = TRUE;
9274e9de 12325 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 12326
3e6b1042
DJ		 12327 /* Skip the linker stubs file. This preserves previous behavior
12328 of accepting unknown attributes in the first input file - but
12329 is that a bug? */
12330 if (ibfd->flags & BFD_LINKER_CREATED)
12331 return TRUE;
12332
9274e9de
TG		 12333 /* Skip any input that hasn't attribute section.
12334 This enables to link object files without attribute section with
12335 any others. */
12336 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
12337 return TRUE;
12338
104d59d1 12339 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 12340 {
12341 /* This is the first object. Copy the attributes. */
104d59d1 12342 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 12343
cd21e546
MGD		 12344 out_attr = elf_known_obj_attributes_proc (obfd);
12345
004ae526
PB		 12346 /* Use the Tag_null value to indicate the attributes have been
12347 initialized. */
cd21e546 12348 out_attr[0].i = 1;
004ae526 12349
cd21e546
MGD		 12350 /* We do not output objects with Tag_MPextension_use_legacy - we move
12351 the attribute's value to Tag_MPextension_use. */
12352 if (out_attr[Tag_MPextension_use_legacy].i != 0)
12353 {
12354 if (out_attr[Tag_MPextension_use].i != 0
12355 && out_attr[Tag_MPextension_use_legacy].i
99059e56 12356 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 12357 {
12358 _bfd_error_handler
12359 (_("Error: %B has both the current and legacy "
12360 "Tag_MPextension_use attributes"), ibfd);
12361 result = FALSE;
12362 }
12363
12364 out_attr[Tag_MPextension_use] =
12365 out_attr[Tag_MPextension_use_legacy];
12366 out_attr[Tag_MPextension_use_legacy].type = 0;
12367 out_attr[Tag_MPextension_use_legacy].i = 0;
12368 }
12369
12370 return result;
ee065d83
PB		 12371 }
12372
104d59d1
JM		 12373 in_attr = elf_known_obj_attributes_proc (ibfd);
12374 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 12375 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
12376 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
12377 {
5c294fee
TG		 12378 /* Ignore mismatches if the object doesn't use floating point or is
12379 floating point ABI independent. */
12380 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
12381 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
12382 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 12383 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 12384 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
12385 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 12386 {
12387 _bfd_error_handler
3895f852 12388 (_("error: %B uses VFP register arguments, %B does not"),
deddc40b
NS		 12389 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
12390 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 12391 result = FALSE;
ee065d83
PB		 12392 }
12393 }
12394
3de4a297 12395 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 12396 {
12397 /* Merge this attribute with existing attributes. */
12398 switch (i)
12399 {
12400 case Tag_CPU_raw_name:
12401 case Tag_CPU_name:
6a631e86 12402 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 12403 break;
12404
12405 case Tag_ABI_optimization_goals:
12406 case Tag_ABI_FP_optimization_goals:
12407 /* Use the first value seen. */
12408 break;
12409
12410 case Tag_CPU_arch:
91e22acd
AS		 12411 {
12412 int secondary_compat = -1, secondary_compat_out = -1;
12413 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 12414 int arch_attr;
12415 static const char *name_table[] =
12416 {
91e22acd
AS		 12417 /* These aren't real CPU names, but we can't guess
12418 that from the architecture version alone. */
12419 "Pre v4",
12420 "ARM v4",
12421 "ARM v4T",
12422 "ARM v5T",
12423 "ARM v5TE",
12424 "ARM v5TEJ",
12425 "ARM v6",
12426 "ARM v6KZ",
12427 "ARM v6T2",
12428 "ARM v6K",
12429 "ARM v7",
12430 "ARM v6-M",
bca38921
MGD		 12431 "ARM v6S-M",
12432 "ARM v8"
91e22acd
AS		 12433 };
12434
12435 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
12436 secondary_compat = get_secondary_compatible_arch (ibfd);
12437 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 12438 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
12439 &secondary_compat_out,
12440 in_attr[i].i,
12441 secondary_compat);
12442
12443 /* Return with error if failed to merge. */
12444 if (arch_attr == -1)
12445 return FALSE;
12446
12447 out_attr[i].i = arch_attr;
12448
91e22acd
AS		 12449 set_secondary_compatible_arch (obfd, secondary_compat_out);
12450
12451 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
12452 if (out_attr[i].i == saved_out_attr)
12453 ; /* Leave the names alone. */
12454 else if (out_attr[i].i == in_attr[i].i)
12455 {
12456 /* The output architecture has been changed to match the
12457 input architecture. Use the input names. */
12458 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
12459 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
12460 : NULL;
12461 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
12462 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
12463 : NULL;
12464 }
12465 else
12466 {
12467 out_attr[Tag_CPU_name].s = NULL;
12468 out_attr[Tag_CPU_raw_name].s = NULL;
12469 }
12470
12471 /* If we still don't have a value for Tag_CPU_name,
12472 make one up now. Tag_CPU_raw_name remains blank. */
12473 if (out_attr[Tag_CPU_name].s == NULL
12474 && out_attr[i].i < ARRAY_SIZE (name_table))
12475 out_attr[Tag_CPU_name].s =
12476 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
12477 }
12478 break;
12479
ee065d83
PB		 12480 case Tag_ARM_ISA_use:
12481 case Tag_THUMB_ISA_use:
ee065d83 12482 case Tag_WMMX_arch:
91e22acd
AS		 12483 case Tag_Advanced_SIMD_arch:
12484 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 12485 case Tag_ABI_FP_rounding:
ee065d83
PB		 12486 case Tag_ABI_FP_exceptions:
12487 case Tag_ABI_FP_user_exceptions:
12488 case Tag_ABI_FP_number_model:
75375b3e 12489 case Tag_FP_HP_extension:
91e22acd
AS		 12490 case Tag_CPU_unaligned_access:
12491 case Tag_T2EE_use:
91e22acd 12492 case Tag_MPextension_use:
ee065d83
PB		 12493 /* Use the largest value specified. */
12494 if (in_attr[i].i > out_attr[i].i)
12495 out_attr[i].i = in_attr[i].i;
12496 break;
12497
75375b3e 12498 case Tag_ABI_align_preserved:
91e22acd
AS		 12499 case Tag_ABI_PCS_RO_data:
12500 /* Use the smallest value specified. */
12501 if (in_attr[i].i < out_attr[i].i)
12502 out_attr[i].i = in_attr[i].i;
12503 break;
12504
75375b3e 12505 case Tag_ABI_align_needed:
91e22acd 12506 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 12507 && (in_attr[Tag_ABI_align_preserved].i == 0
12508 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 12509 {
91e22acd
AS		 12510 /* This error message should be enabled once all non-conformant
12511 binaries in the toolchain have had the attributes set
12512 properly.
ee065d83 12513 _bfd_error_handler
3895f852 12514 (_("error: %B: 8-byte data alignment conflicts with %B"),
91e22acd
AS		 12515 obfd, ibfd);
12516 result = FALSE; */
ee065d83 12517 }
91e22acd
AS		 12518 /* Fall through. */
12519 case Tag_ABI_FP_denormal:
12520 case Tag_ABI_PCS_GOT_use:
12521 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
12522 value if greater than 2 (for future-proofing). */
12523 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
12524 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
12525 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 12526 out_attr[i].i = in_attr[i].i;
12527 break;
91e22acd 12528
75375b3e
MGD		 12529 case Tag_Virtualization_use:
12530 /* The virtualization tag effectively stores two bits of
12531 information: the intended use of TrustZone (in bit 0), and the
12532 intended use of Virtualization (in bit 1). */
12533 if (out_attr[i].i == 0)
12534 out_attr[i].i = in_attr[i].i;
12535 else if (in_attr[i].i != 0
12536 && in_attr[i].i != out_attr[i].i)
12537 {
12538 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
12539 out_attr[i].i = 3;
12540 else
12541 {
12542 _bfd_error_handler
12543 (_("error: %B: unable to merge virtualization attributes "
12544 "with %B"),
12545 obfd, ibfd);
12546 result = FALSE;
12547 }
12548 }
12549 break;
91e22acd
AS		 12550
12551 case Tag_CPU_arch_profile:
12552 if (out_attr[i].i != in_attr[i].i)
12553 {
12554 /* 0 will merge with anything.
12555 'A' and 'S' merge to 'A'.
12556 'R' and 'S' merge to 'R'.
99059e56 12557 'M' and 'A|R|S' is an error. */
91e22acd
AS		 12558 if (out_attr[i].i == 0
12559 || (out_attr[i].i == 'S'
12560 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
12561 out_attr[i].i = in_attr[i].i;
12562 else if (in_attr[i].i == 0
12563 || (in_attr[i].i == 'S'
12564 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 12565 ; /* Do nothing. */
91e22acd
AS		 12566 else
12567 {
12568 _bfd_error_handler
3895f852 12569 (_("error: %B: Conflicting architecture profiles %c/%c"),
91e22acd
AS		 12570 ibfd,
12571 in_attr[i].i ? in_attr[i].i : '0',
12572 out_attr[i].i ? out_attr[i].i : '0');
12573 result = FALSE;
12574 }
12575 }
12576 break;
75375b3e 12577 case Tag_FP_arch:
62f3b8c8 12578 {
4547cb56
NC		 12579 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
12580 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
12581 when it's 0. It might mean absence of FP hardware if
99654aaf 12582 Tag_FP_arch is zero. */
4547cb56 12583
a715796b 12584#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 12585 static const struct
12586 {
12587 int ver;
12588 int regs;
bca38921 12589 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 12590 {
12591 {0, 0},
12592 {1, 16},
12593 {2, 16},
12594 {3, 32},
12595 {3, 16},
12596 {4, 32},
bca38921 12597 {4, 16},
a715796b
TG		 12598 {8, 32},
12599 {8, 16}
62f3b8c8
PB		 12600 };
12601 int ver;
12602 int regs;
12603 int newval;
12604
4547cb56
NC		 12605 /* If the output has no requirement about FP hardware,
12606 follow the requirement of the input. */
12607 if (out_attr[i].i == 0)
12608 {
12609 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
12610 out_attr[i].i = in_attr[i].i;
12611 out_attr[Tag_ABI_HardFP_use].i
12612 = in_attr[Tag_ABI_HardFP_use].i;
12613 break;
12614 }
12615 /* If the input has no requirement about FP hardware, do
12616 nothing. */
12617 else if (in_attr[i].i == 0)
12618 {
12619 BFD_ASSERT (in_attr[Tag_ABI_HardFP_use].i == 0);
12620 break;
12621 }
12622
12623 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 12624 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 12625
12626 /* If both the input and the output have zero Tag_ABI_HardFP_use,
12627 do nothing. */
12628 if (in_attr[Tag_ABI_HardFP_use].i == 0
12629 && out_attr[Tag_ABI_HardFP_use].i == 0)
12630 ;
12631 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 12632 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 12633 else if (in_attr[Tag_ABI_HardFP_use].i
12634 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 12635 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 12636
12637 /* Now we can handle Tag_FP_arch. */
12638
bca38921
MGD		 12639 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
12640 pick the biggest. */
12641 if (in_attr[i].i >= VFP_VERSION_COUNT
12642 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 12643 {
12644 out_attr[i] = in_attr[i];
12645 break;
12646 }
12647 /* The output uses the superset of input features
12648 (ISA version) and registers. */
12649 ver = vfp_versions[in_attr[i].i].ver;
12650 if (ver < vfp_versions[out_attr[i].i].ver)
12651 ver = vfp_versions[out_attr[i].i].ver;
12652 regs = vfp_versions[in_attr[i].i].regs;
12653 if (regs < vfp_versions[out_attr[i].i].regs)
12654 regs = vfp_versions[out_attr[i].i].regs;
12655 /* This assumes all possible supersets are also a valid
99059e56 12656 options. */
bca38921 12657 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 12658 {
12659 if (regs == vfp_versions[newval].regs
12660 && ver == vfp_versions[newval].ver)
12661 break;
12662 }
12663 out_attr[i].i = newval;
12664 }
b1cc4aeb 12665 break;
ee065d83
PB		 12666 case Tag_PCS_config:
12667 if (out_attr[i].i == 0)
12668 out_attr[i].i = in_attr[i].i;
b6009aca 12669 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 12670 {
12671 /* It's sometimes ok to mix different configs, so this is only
99059e56 12672 a warning. */
ee065d83
PB		 12673 _bfd_error_handler
12674 (_("Warning: %B: Conflicting platform configuration"), ibfd);
12675 }
12676 break;
12677 case Tag_ABI_PCS_R9_use:
004ae526
PB		 12678 if (in_attr[i].i != out_attr[i].i
12679 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 12680 && in_attr[i].i != AEABI_R9_unused)
12681 {
12682 _bfd_error_handler
3895f852 12683 (_("error: %B: Conflicting use of R9"), ibfd);
91e22acd 12684 result = FALSE;
ee065d83
PB		 12685 }
12686 if (out_attr[i].i == AEABI_R9_unused)
12687 out_attr[i].i = in_attr[i].i;
12688 break;
12689 case Tag_ABI_PCS_RW_data:
12690 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
12691 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
12692 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
12693 {
12694 _bfd_error_handler
3895f852 12695 (_("error: %B: SB relative addressing conflicts with use of R9"),
ee065d83 12696 ibfd);
91e22acd 12697 result = FALSE;
ee065d83
PB		 12698 }
12699 /* Use the smallest value specified. */
12700 if (in_attr[i].i < out_attr[i].i)
12701 out_attr[i].i = in_attr[i].i;
12702 break;
ee065d83 12703 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 12704 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
12705 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 12706 {
12707 _bfd_error_handler
a9dc9481
JM		 12708 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
12709 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 12710 }
a9dc9481 12711 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 12712 out_attr[i].i = in_attr[i].i;
12713 break;
ee065d83
PB		 12714 case Tag_ABI_enum_size:
12715 if (in_attr[i].i != AEABI_enum_unused)
12716 {
12717 if (out_attr[i].i == AEABI_enum_unused
12718 || out_attr[i].i == AEABI_enum_forced_wide)
12719 {
12720 /* The existing object is compatible with anything.
12721 Use whatever requirements the new object has. */
12722 out_attr[i].i = in_attr[i].i;
12723 }
12724 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 12725 && out_attr[i].i != in_attr[i].i
0ffa91dd 12726 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 12727 {
91e22acd 12728 static const char *aeabi_enum_names[] =
bf21ed78 12729 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 12730 const char *in_name =
12731 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
12732 ? aeabi_enum_names[in_attr[i].i]
12733 : "<unknown>";
12734 const char *out_name =
12735 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
12736 ? aeabi_enum_names[out_attr[i].i]
12737 : "<unknown>";
ee065d83 12738 _bfd_error_handler
bf21ed78 12739 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 12740 ibfd, in_name, out_name);
ee065d83
PB		 12741 }
12742 }
12743 break;
12744 case Tag_ABI_VFP_args:
12745 /* Aready done. */
12746 break;
12747 case Tag_ABI_WMMX_args:
12748 if (in_attr[i].i != out_attr[i].i)
12749 {
12750 _bfd_error_handler
3895f852 12751 (_("error: %B uses iWMMXt register arguments, %B does not"),
ee065d83 12752 ibfd, obfd);
91e22acd 12753 result = FALSE;
ee065d83
PB		 12754 }
12755 break;
7b86a9fa
AS		 12756 case Tag_compatibility:
12757 /* Merged in target-independent code. */
12758 break;
91e22acd 12759 case Tag_ABI_HardFP_use:
4547cb56 12760 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 12761 break;
12762 case Tag_ABI_FP_16bit_format:
12763 if (in_attr[i].i != 0 && out_attr[i].i != 0)
12764 {
12765 if (in_attr[i].i != out_attr[i].i)
12766 {
12767 _bfd_error_handler
3895f852 12768 (_("error: fp16 format mismatch between %B and %B"),
91e22acd
AS		 12769 ibfd, obfd);
12770 result = FALSE;
12771 }
12772 }
12773 if (in_attr[i].i != 0)
12774 out_attr[i].i = in_attr[i].i;
12775 break;
7b86a9fa 12776
cd21e546 12777 case Tag_DIV_use:
ac56ee8f
MGD		 12778 /* A value of zero on input means that the divide instruction may
12779 be used if available in the base architecture as specified via
12780 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
12781 the user did not want divide instructions. A value of 2
12782 explicitly means that divide instructions were allowed in ARM
12783 and Thumb state. */
12784 if (in_attr[i].i == out_attr[i].i)
12785 /* Do nothing. */ ;
12786 else if (elf32_arm_attributes_forbid_div (in_attr)
12787 && !elf32_arm_attributes_accept_div (out_attr))
12788 out_attr[i].i = 1;
12789 else if (elf32_arm_attributes_forbid_div (out_attr)
12790 && elf32_arm_attributes_accept_div (in_attr))
12791 out_attr[i].i = in_attr[i].i;
12792 else if (in_attr[i].i == 2)
12793 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 12794 break;
12795
12796 case Tag_MPextension_use_legacy:
12797 /* We don't output objects with Tag_MPextension_use_legacy - we
12798 move the value to Tag_MPextension_use. */
12799 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
12800 {
12801 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
12802 {
12803 _bfd_error_handler
12804 (_("%B has has both the current and legacy "
b38cadfb 12805 "Tag_MPextension_use attributes"),
cd21e546
MGD		 12806 ibfd);
12807 result = FALSE;
12808 }
12809 }
12810
12811 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
12812 out_attr[Tag_MPextension_use] = in_attr[i];
12813
12814 break;
12815
91e22acd 12816 case Tag_nodefaults:
2d0bb761
AS		 12817 /* This tag is set if it exists, but the value is unused (and is
12818 typically zero). We don't actually need to do anything here -
12819 the merge happens automatically when the type flags are merged
12820 below. */
91e22acd
AS		 12821 break;
12822 case Tag_also_compatible_with:
12823 /* Already done in Tag_CPU_arch. */
12824 break;
12825 case Tag_conformance:
12826 /* Keep the attribute if it matches. Throw it away otherwise.
12827 No attribute means no claim to conform. */
12828 if (!in_attr[i].s || !out_attr[i].s
12829 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
12830 out_attr[i].s = NULL;
12831 break;
3cfad14c 12832
91e22acd 12833 default:
e8b36cd1
JM		 12834 result
12835 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 12836 }
12837
12838 /* If out_attr was copied from in_attr then it won't have a type yet. */
12839 if (in_attr[i].type && !out_attr[i].type)
12840 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 12841 }
12842
104d59d1 12843 /* Merge Tag_compatibility attributes and any common GNU ones. */
5488d830
MGD		 12844 if (!_bfd_elf_merge_object_attributes (ibfd, obfd))
12845 return FALSE;
ee065d83 12846
104d59d1 12847 /* Check for any attributes not known on ARM. */
e8b36cd1 12848 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 12849
91e22acd 12850 return result;
252b5132
RH		 12851}
12852
3a4a14e9
PB		 12853
12854/* Return TRUE if the two EABI versions are incompatible. */
12855
12856static bfd_boolean
12857elf32_arm_versions_compatible (unsigned iver, unsigned over)
12858{
12859 /* v4 and v5 are the same spec before and after it was released,
12860 so allow mixing them. */
12861 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
12862 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
12863 return TRUE;
12864
12865 return (iver == over);
12866}
12867
252b5132
RH		 12868/* Merge backend specific data from an object file to the output
12869 object file when linking. */
9b485d32 12870
b34976b6 12871static bfd_boolean
21d799b5 12872elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd);
252b5132 12873
9b485d32
NC		 12874/* Display the flags field. */
12875
b34976b6 12876static bfd_boolean
57e8b36a 12877elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 12878{
fc830a83
NC		 12879 FILE * file = (FILE *) ptr;
12880 unsigned long flags;
252b5132
RH		 12881
12882 BFD_ASSERT (abfd != NULL && ptr != NULL);
12883
12884 /* Print normal ELF private data. */
12885 _bfd_elf_print_private_bfd_data (abfd, ptr);
12886
fc830a83 12887 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 12888 /* Ignore init flag - it may not be set, despite the flags field
12889 containing valid data. */
252b5132
RH		 12890
12891 /* xgettext:c-format */
9b485d32 12892 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 12893
fc830a83
NC		 12894 switch (EF_ARM_EABI_VERSION (flags))
12895 {
12896 case EF_ARM_EABI_UNKNOWN:
4cc11e76 12897 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 12898 official ARM ELF extended ABI. Hence they are only decoded if
12899 the EABI version is not set. */
fd2ec330 12900 if (flags & EF_ARM_INTERWORK)
9b485d32 12901 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 12902
fd2ec330 12903 if (flags & EF_ARM_APCS_26)
6c571f00 12904 fprintf (file, " [APCS-26]");
fc830a83 12905 else
6c571f00 12906 fprintf (file, " [APCS-32]");
9a5aca8c 12907
96a846ea
RE		 12908 if (flags & EF_ARM_VFP_FLOAT)
12909 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 12910 else if (flags & EF_ARM_MAVERICK_FLOAT)
12911 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 12912 else
12913 fprintf (file, _(" [FPA float format]"));
12914
fd2ec330 12915 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 12916 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 12917
fd2ec330 12918 if (flags & EF_ARM_PIC)
9b485d32 12919 fprintf (file, _(" [position independent]"));
fc830a83 12920
fd2ec330 12921 if (flags & EF_ARM_NEW_ABI)
9b485d32 12922 fprintf (file, _(" [new ABI]"));
9a5aca8c 12923
fd2ec330 12924 if (flags & EF_ARM_OLD_ABI)
9b485d32 12925 fprintf (file, _(" [old ABI]"));
9a5aca8c 12926
fd2ec330 12927 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 12928 fprintf (file, _(" [software FP]"));
9a5aca8c 12929
96a846ea
RE		 12930 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
12931 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 12932 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
12933 | EF_ARM_MAVERICK_FLOAT);
fc830a83 12934 break;
9a5aca8c 12935
fc830a83 12936 case EF_ARM_EABI_VER1:
9b485d32 12937 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 12938
fc830a83 12939 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 12940 fprintf (file, _(" [sorted symbol table]"));
fc830a83 12941 else
9b485d32 12942 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 12943
fc830a83
NC		 12944 flags &= ~ EF_ARM_SYMSARESORTED;
12945 break;
9a5aca8c 12946
fd2ec330
PB		 12947 case EF_ARM_EABI_VER2:
12948 fprintf (file, _(" [Version2 EABI]"));
12949
12950 if (flags & EF_ARM_SYMSARESORTED)
12951 fprintf (file, _(" [sorted symbol table]"));
12952 else
12953 fprintf (file, _(" [unsorted symbol table]"));
12954
12955 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
12956 fprintf (file, _(" [dynamic symbols use segment index]"));
12957
12958 if (flags & EF_ARM_MAPSYMSFIRST)
12959 fprintf (file, _(" [mapping symbols precede others]"));
12960
99e4ae17 12961 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 12962 | EF_ARM_MAPSYMSFIRST);
12963 break;
12964
d507cf36
PB		 12965 case EF_ARM_EABI_VER3:
12966 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 12967 break;
12968
12969 case EF_ARM_EABI_VER4:
12970 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 12971 goto eabi;
d507cf36 12972
3a4a14e9
PB		 12973 case EF_ARM_EABI_VER5:
12974 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 12975
12976 if (flags & EF_ARM_ABI_FLOAT_SOFT)
12977 fprintf (file, _(" [soft-float ABI]"));
12978
12979 if (flags & EF_ARM_ABI_FLOAT_HARD)
12980 fprintf (file, _(" [hard-float ABI]"));
12981
12982 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
12983
3a4a14e9 12984 eabi:
d507cf36
PB		 12985 if (flags & EF_ARM_BE8)
12986 fprintf (file, _(" [BE8]"));
12987
12988 if (flags & EF_ARM_LE8)
12989 fprintf (file, _(" [LE8]"));
12990
12991 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
12992 break;
12993
fc830a83 12994 default:
9b485d32 12995 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 12996 break;
12997 }
252b5132 12998
fc830a83 12999 flags &= ~ EF_ARM_EABIMASK;
252b5132 13000
fc830a83 13001 if (flags & EF_ARM_RELEXEC)
9b485d32 13002 fprintf (file, _(" [relocatable executable]"));
252b5132 13003
a5721edd 13004 flags &= ~EF_ARM_RELEXEC;
fc830a83
NC		 13005
13006 if (flags)
9b485d32 13007 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 13008
252b5132
RH		 13009 fputc ('\n', file);
13010
b34976b6 13011 return TRUE;
252b5132
RH		 13012}
13013
13014static int
57e8b36a 13015elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 13016{
2f0ca46a
NC		 13017 switch (ELF_ST_TYPE (elf_sym->st_info))
13018 {
13019 case STT_ARM_TFUNC:
13020 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 13021
2f0ca46a
NC		 13022 case STT_ARM_16BIT:
13023 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
13024 This allows us to distinguish between data used by Thumb instructions
13025 and non-data (which is probably code) inside Thumb regions of an
13026 executable. */
1a0eb693 13027 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 13028 return ELF_ST_TYPE (elf_sym->st_info);
13029 break;
9a5aca8c 13030
ce855c42
NC		 13031 default:
13032 break;
2f0ca46a
NC		 13033 }
13034
13035 return type;
252b5132 13036}
f21f3fe0 13037
252b5132 13038static asection *
07adf181
AM		 13039elf32_arm_gc_mark_hook (asection *sec,
13040 struct bfd_link_info *info,
13041 Elf_Internal_Rela *rel,
13042 struct elf_link_hash_entry *h,
13043 Elf_Internal_Sym *sym)
252b5132
RH		 13044{
13045 if (h != NULL)
07adf181 13046 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 13047 {
13048 case R_ARM_GNU_VTINHERIT:
13049 case R_ARM_GNU_VTENTRY:
07adf181
AM		 13050 return NULL;
13051 }
9ad5cbcf 13052
07adf181 13053 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 13054}
13055
780a67af
NC		 13056/* Update the got entry reference counts for the section being removed. */
13057
b34976b6 13058static bfd_boolean
ba93b8ac
DJ		 13059elf32_arm_gc_sweep_hook (bfd * abfd,
13060 struct bfd_link_info * info,
13061 asection * sec,
13062 const Elf_Internal_Rela * relocs)
252b5132 13063{
5e681ec4
PB		 13064 Elf_Internal_Shdr *symtab_hdr;
13065 struct elf_link_hash_entry **sym_hashes;
13066 bfd_signed_vma *local_got_refcounts;
13067 const Elf_Internal_Rela *rel, *relend;
eb043451
PB		 13068 struct elf32_arm_link_hash_table * globals;
13069
0e1862bb 13070 if (bfd_link_relocatable (info))
7dda2462
TG		 13071 return TRUE;
13072
eb043451 13073 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13074 if (globals == NULL)
13075 return FALSE;
5e681ec4
PB		 13076
13077 elf_section_data (sec)->local_dynrel = NULL;
13078
0ffa91dd 13079 symtab_hdr = & elf_symtab_hdr (abfd);
5e681ec4
PB		 13080 sym_hashes = elf_sym_hashes (abfd);
13081 local_got_refcounts = elf_local_got_refcounts (abfd);
13082
906e58ca 13083 check_use_blx (globals);
bd97cb95 13084
5e681ec4
PB		 13085 relend = relocs + sec->reloc_count;
13086 for (rel = relocs; rel < relend; rel++)
eb043451 13087 {
3eb128b2
AM		 13088 unsigned long r_symndx;
13089 struct elf_link_hash_entry *h = NULL;
f6e32f6d 13090 struct elf32_arm_link_hash_entry *eh;
eb043451 13091 int r_type;
34e77a92 13092 bfd_boolean call_reloc_p;
f6e32f6d
RS		 13093 bfd_boolean may_become_dynamic_p;
13094 bfd_boolean may_need_local_target_p;
34e77a92
RS		 13095 union gotplt_union *root_plt;
13096 struct arm_plt_info *arm_plt;
5e681ec4 13097
3eb128b2
AM		 13098 r_symndx = ELF32_R_SYM (rel->r_info);
13099 if (r_symndx >= symtab_hdr->sh_info)
13100 {
13101 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
13102 while (h->root.type == bfd_link_hash_indirect
13103 || h->root.type == bfd_link_hash_warning)
13104 h = (struct elf_link_hash_entry *) h->root.u.i.link;
13105 }
f6e32f6d
RS		 13106 eh = (struct elf32_arm_link_hash_entry *) h;
13107
34e77a92 13108 call_reloc_p = FALSE;
f6e32f6d
RS		 13109 may_become_dynamic_p = FALSE;
13110 may_need_local_target_p = FALSE;
3eb128b2 13111
eb043451 13112 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 13113 r_type = arm_real_reloc_type (globals, r_type);
eb043451
PB		 13114 switch (r_type)
13115 {
13116 case R_ARM_GOT32:
eb043451 13117 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 13118 case R_ARM_TLS_GD32:
13119 case R_ARM_TLS_IE32:
3eb128b2 13120 if (h != NULL)
eb043451 13121 {
eb043451
PB		 13122 if (h->got.refcount > 0)
13123 h->got.refcount -= 1;
13124 }
13125 else if (local_got_refcounts != NULL)
13126 {
13127 if (local_got_refcounts[r_symndx] > 0)
13128 local_got_refcounts[r_symndx] -= 1;
13129 }
13130 break;
13131
ba93b8ac 13132 case R_ARM_TLS_LDM32:
4dfe6ac6 13133 globals->tls_ldm_got.refcount -= 1;
ba93b8ac
DJ		 13134 break;
13135
eb043451
PB		 13136 case R_ARM_PC24:
13137 case R_ARM_PLT32:
5b5bb741
PB		 13138 case R_ARM_CALL:
13139 case R_ARM_JUMP24:
eb043451 13140 case R_ARM_PREL31:
c19d1205 13141 case R_ARM_THM_CALL:
bd97cb95
DJ		 13142 case R_ARM_THM_JUMP24:
13143 case R_ARM_THM_JUMP19:
34e77a92 13144 call_reloc_p = TRUE;
f6e32f6d
RS		 13145 may_need_local_target_p = TRUE;
13146 break;
13147
13148 case R_ARM_ABS12:
13149 if (!globals->vxworks_p)
13150 {
13151 may_need_local_target_p = TRUE;
13152 break;
13153 }
13154 /* Fall through. */
13155 case R_ARM_ABS32:
13156 case R_ARM_ABS32_NOI:
13157 case R_ARM_REL32:
13158 case R_ARM_REL32_NOI:
b6895b4f
PB		 13159 case R_ARM_MOVW_ABS_NC:
13160 case R_ARM_MOVT_ABS:
13161 case R_ARM_MOVW_PREL_NC:
13162 case R_ARM_MOVT_PREL:
13163 case R_ARM_THM_MOVW_ABS_NC:
13164 case R_ARM_THM_MOVT_ABS:
13165 case R_ARM_THM_MOVW_PREL_NC:
13166 case R_ARM_THM_MOVT_PREL:
b7693d02 13167 /* Should the interworking branches be here also? */
0e1862bb 13168 if ((bfd_link_pic (info) || globals->root.is_relocatable_executable)
34e77a92
RS		 13169 && (sec->flags & SEC_ALLOC) != 0)
13170 {
13171 if (h == NULL
469a3493 13172 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 13173 {
13174 call_reloc_p = TRUE;
13175 may_need_local_target_p = TRUE;
13176 }
13177 else
13178 may_become_dynamic_p = TRUE;
13179 }
f6e32f6d
RS		 13180 else
13181 may_need_local_target_p = TRUE;
13182 break;
b7693d02 13183
f6e32f6d
RS		 13184 default:
13185 break;
13186 }
5e681ec4 13187
34e77a92
RS		 13188 if (may_need_local_target_p
13189 && elf32_arm_get_plt_info (abfd, eh, r_symndx, &root_plt, &arm_plt))
f6e32f6d 13190 {
27586251
HPN		 13191 /* If PLT refcount book-keeping is wrong and too low, we'll
13192 see a zero value (going to -1) for the root PLT reference
13193 count. */
13194 if (root_plt->refcount >= 0)
13195 {
13196 BFD_ASSERT (root_plt->refcount != 0);
13197 root_plt->refcount -= 1;
13198 }
13199 else
13200 /* A value of -1 means the symbol has become local, forced
13201 or seeing a hidden definition. Any other negative value
13202 is an error. */
13203 BFD_ASSERT (root_plt->refcount == -1);
34e77a92
RS		 13204
13205 if (!call_reloc_p)
13206 arm_plt->noncall_refcount--;
5e681ec4 13207
f6e32f6d 13208 if (r_type == R_ARM_THM_CALL)
34e77a92 13209 arm_plt->maybe_thumb_refcount--;
bd97cb95 13210
f6e32f6d
RS		 13211 if (r_type == R_ARM_THM_JUMP24
13212 || r_type == R_ARM_THM_JUMP19)
34e77a92 13213 arm_plt->thumb_refcount--;
f6e32f6d 13214 }
5e681ec4 13215
34e77a92 13216 if (may_become_dynamic_p)
f6e32f6d
RS		 13217 {
13218 struct elf_dyn_relocs **pp;
13219 struct elf_dyn_relocs *p;
5e681ec4 13220
34e77a92 13221 if (h != NULL)
9c489990 13222 pp = &(eh->dyn_relocs);
34e77a92
RS		 13223 else
13224 {
13225 Elf_Internal_Sym *isym;
13226
13227 isym = bfd_sym_from_r_symndx (&globals->sym_cache,
13228 abfd, r_symndx);
13229 if (isym == NULL)
13230 return FALSE;
13231 pp = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
13232 if (pp == NULL)
13233 return FALSE;
13234 }
9c489990 13235 for (; (p = *pp) != NULL; pp = &p->next)
f6e32f6d
RS		 13236 if (p->sec == sec)
13237 {
13238 /* Everything must go for SEC. */
13239 *pp = p->next;
13240 break;
13241 }
eb043451
PB		 13242 }
13243 }
5e681ec4 13244
b34976b6 13245 return TRUE;
252b5132
RH		 13246}
13247
780a67af
NC		 13248/* Look through the relocs for a section during the first phase. */
13249
b34976b6 13250static bfd_boolean
57e8b36a
NC		 13251elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
13252 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 13253{
b34976b6
AM		 13254 Elf_Internal_Shdr *symtab_hdr;
13255 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 13256 const Elf_Internal_Rela *rel;
13257 const Elf_Internal_Rela *rel_end;
13258 bfd *dynobj;
5e681ec4 13259 asection *sreloc;
5e681ec4 13260 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 13261 bfd_boolean call_reloc_p;
13262 bfd_boolean may_become_dynamic_p;
13263 bfd_boolean may_need_local_target_p;
ce98a316 13264 unsigned long nsyms;
9a5aca8c 13265
0e1862bb 13266 if (bfd_link_relocatable (info))
b34976b6 13267 return TRUE;
9a5aca8c 13268
0ffa91dd
NC		 13269 BFD_ASSERT (is_arm_elf (abfd));
13270
5e681ec4 13271 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13272 if (htab == NULL)
13273 return FALSE;
13274
5e681ec4 13275 sreloc = NULL;
9a5aca8c 13276
67687978
PB		 13277 /* Create dynamic sections for relocatable executables so that we can
13278 copy relocations. */
13279 if (htab->root.is_relocatable_executable
13280 && ! htab->root.dynamic_sections_created)
13281 {
13282 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
13283 return FALSE;
13284 }
13285
cbc704f3
RS		 13286 if (htab->root.dynobj == NULL)
13287 htab->root.dynobj = abfd;
34e77a92
RS		 13288 if (!create_ifunc_sections (info))
13289 return FALSE;
cbc704f3
RS		 13290
13291 dynobj = htab->root.dynobj;
13292
0ffa91dd 13293 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 13294 sym_hashes = elf_sym_hashes (abfd);
ce98a316 13295 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 13296
252b5132
RH		 13297 rel_end = relocs + sec->reloc_count;
13298 for (rel = relocs; rel < rel_end; rel++)
13299 {
34e77a92 13300 Elf_Internal_Sym *isym;
252b5132 13301 struct elf_link_hash_entry *h;
b7693d02 13302 struct elf32_arm_link_hash_entry *eh;
252b5132 13303 unsigned long r_symndx;
eb043451 13304 int r_type;
9a5aca8c 13305
252b5132 13306 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 13307 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 13308 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 13309
ce98a316
NC		 13310 if (r_symndx >= nsyms
13311 /* PR 9934: It is possible to have relocations that do not
13312 refer to symbols, thus it is also possible to have an
13313 object file containing relocations but no symbol table. */
cf35638d 13314 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac
DJ		 13315 {
13316 (*_bfd_error_handler) (_("%B: bad symbol index: %d"), abfd,
ce98a316 13317 r_symndx);
ba93b8ac
DJ		 13318 return FALSE;
13319 }
13320
34e77a92
RS		 13321 h = NULL;
13322 isym = NULL;
13323 if (nsyms > 0)
973a3492 13324 {
34e77a92
RS		 13325 if (r_symndx < symtab_hdr->sh_info)
13326 {
13327 /* A local symbol. */
13328 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
13329 abfd, r_symndx);
13330 if (isym == NULL)
13331 return FALSE;
13332 }
13333 else
13334 {
13335 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
13336 while (h->root.type == bfd_link_hash_indirect
13337 || h->root.type == bfd_link_hash_warning)
13338 h = (struct elf_link_hash_entry *) h->root.u.i.link;
81fbe831
AM		 13339
13340 /* PR15323, ref flags aren't set for references in the
13341 same object. */
13342 h->root.non_ir_ref = 1;
34e77a92 13343 }
973a3492 13344 }
9a5aca8c 13345
b7693d02
DJ		 13346 eh = (struct elf32_arm_link_hash_entry *) h;
13347
f6e32f6d
RS		 13348 call_reloc_p = FALSE;
13349 may_become_dynamic_p = FALSE;
13350 may_need_local_target_p = FALSE;
13351
0855e32b
NS		 13352 /* Could be done earlier, if h were already available. */
13353 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 13354 switch (r_type)
99059e56 13355 {
5e681ec4 13356 case R_ARM_GOT32:
eb043451 13357 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 13358 case R_ARM_TLS_GD32:
13359 case R_ARM_TLS_IE32:
0855e32b
NS		 13360 case R_ARM_TLS_GOTDESC:
13361 case R_ARM_TLS_DESCSEQ:
13362 case R_ARM_THM_TLS_DESCSEQ:
13363 case R_ARM_TLS_CALL:
13364 case R_ARM_THM_TLS_CALL:
5e681ec4 13365 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 13366 {
13367 int tls_type, old_tls_type;
5e681ec4 13368
ba93b8ac
DJ		 13369 switch (r_type)
13370 {
13371 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 13372
ba93b8ac 13373 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 13374
0855e32b
NS		 13375 case R_ARM_TLS_GOTDESC:
13376 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
13377 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
13378 tls_type = GOT_TLS_GDESC; break;
b38cadfb 13379
ba93b8ac
DJ		 13380 default: tls_type = GOT_NORMAL; break;
13381 }
252b5132 13382
0e1862bb 13383 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 13384 info->flags |= DF_STATIC_TLS;
13385
ba93b8ac
DJ		 13386 if (h != NULL)
13387 {
13388 h->got.refcount++;
13389 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
13390 }
13391 else
13392 {
ba93b8ac 13393 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 13394 if (!elf32_arm_allocate_local_sym_info (abfd))
13395 return FALSE;
13396 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 13397 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
13398 }
13399
0855e32b 13400 /* If a variable is accessed with both tls methods, two
99059e56 13401 slots may be created. */
0855e32b
NS		 13402 if (GOT_TLS_GD_ANY_P (old_tls_type)
13403 && GOT_TLS_GD_ANY_P (tls_type))
13404 tls_type |= old_tls_type;
13405
13406 /* We will already have issued an error message if there
13407 is a TLS/non-TLS mismatch, based on the symbol
13408 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 13409 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
13410 && tls_type != GOT_NORMAL)
13411 tls_type |= old_tls_type;
13412
0855e32b 13413 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 13414 method, we're able to relax. Turn off the GDESC flag,
13415 without messing up with any other kind of tls types
6a631e86 13416 that may be involved. */
0855e32b
NS		 13417 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
13418 tls_type &= ~GOT_TLS_GDESC;
13419
ba93b8ac
DJ		 13420 if (old_tls_type != tls_type)
13421 {
13422 if (h != NULL)
13423 elf32_arm_hash_entry (h)->tls_type = tls_type;
13424 else
13425 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
13426 }
13427 }
8029a119 13428 /* Fall through. */
ba93b8ac
DJ		 13429
13430 case R_ARM_TLS_LDM32:
13431 if (r_type == R_ARM_TLS_LDM32)
13432 htab->tls_ldm_got.refcount++;
8029a119 13433 /* Fall through. */
252b5132 13434
c19d1205 13435 case R_ARM_GOTOFF32:
5e681ec4 13436 case R_ARM_GOTPC:
cbc704f3
RS		 13437 if (htab->root.sgot == NULL
13438 && !create_got_section (htab->root.dynobj, info))
13439 return FALSE;
252b5132
RH		 13440 break;
13441
252b5132 13442 case R_ARM_PC24:
7359ea65 13443 case R_ARM_PLT32:
5b5bb741
PB		 13444 case R_ARM_CALL:
13445 case R_ARM_JUMP24:
eb043451 13446 case R_ARM_PREL31:
c19d1205 13447 case R_ARM_THM_CALL:
bd97cb95
DJ		 13448 case R_ARM_THM_JUMP24:
13449 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 13450 call_reloc_p = TRUE;
13451 may_need_local_target_p = TRUE;
13452 break;
13453
13454 case R_ARM_ABS12:
13455 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
13456 ldr __GOTT_INDEX__ offsets. */
13457 if (!htab->vxworks_p)
13458 {
13459 may_need_local_target_p = TRUE;
13460 break;
13461 }
13462 /* Fall through. */
39623e12 13463
96c23d59
JM		 13464 case R_ARM_MOVW_ABS_NC:
13465 case R_ARM_MOVT_ABS:
13466 case R_ARM_THM_MOVW_ABS_NC:
13467 case R_ARM_THM_MOVT_ABS:
0e1862bb 13468 if (bfd_link_pic (info))
96c23d59
JM		 13469 {
13470 (*_bfd_error_handler)
13471 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
13472 abfd, elf32_arm_howto_table_1[r_type].name,
13473 (h) ? h->root.root.string : "a local symbol");
13474 bfd_set_error (bfd_error_bad_value);
13475 return FALSE;
13476 }
13477
13478 /* Fall through. */
39623e12
PB		 13479 case R_ARM_ABS32:
13480 case R_ARM_ABS32_NOI:
0e1862bb 13481 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 13482 {
13483 h->pointer_equality_needed = 1;
13484 }
13485 /* Fall through. */
39623e12
PB		 13486 case R_ARM_REL32:
13487 case R_ARM_REL32_NOI:
b6895b4f
PB		 13488 case R_ARM_MOVW_PREL_NC:
13489 case R_ARM_MOVT_PREL:
b6895b4f
PB		 13490 case R_ARM_THM_MOVW_PREL_NC:
13491 case R_ARM_THM_MOVT_PREL:
39623e12 13492
b7693d02 13493 /* Should the interworking branches be listed here? */
0e1862bb 13494 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 13495 && (sec->flags & SEC_ALLOC) != 0)
13496 {
13497 if (h == NULL
469a3493 13498 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 13499 {
13500 /* In shared libraries and relocatable executables,
13501 we treat local relative references as calls;
13502 see the related SYMBOL_CALLS_LOCAL code in
13503 allocate_dynrelocs. */
13504 call_reloc_p = TRUE;
13505 may_need_local_target_p = TRUE;
13506 }
13507 else
13508 /* We are creating a shared library or relocatable
13509 executable, and this is a reloc against a global symbol,
13510 or a non-PC-relative reloc against a local symbol.
13511 We may need to copy the reloc into the output. */
13512 may_become_dynamic_p = TRUE;
13513 }
f6e32f6d
RS		 13514 else
13515 may_need_local_target_p = TRUE;
252b5132
RH		 13516 break;
13517
99059e56
RM		 13518 /* This relocation describes the C++ object vtable hierarchy.
13519 Reconstruct it for later use during GC. */
13520 case R_ARM_GNU_VTINHERIT:
13521 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
13522 return FALSE;
13523 break;
13524
13525 /* This relocation describes which C++ vtable entries are actually
13526 used. Record for later use during GC. */
13527 case R_ARM_GNU_VTENTRY:
13528 BFD_ASSERT (h != NULL);
13529 if (h != NULL
13530 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
13531 return FALSE;
13532 break;
13533 }
f6e32f6d
RS		 13534
13535 if (h != NULL)
13536 {
13537 if (call_reloc_p)
13538 /* We may need a .plt entry if the function this reloc
13539 refers to is in a different object, regardless of the
13540 symbol's type. We can't tell for sure yet, because
13541 something later might force the symbol local. */
13542 h->needs_plt = 1;
13543 else if (may_need_local_target_p)
13544 /* If this reloc is in a read-only section, we might
13545 need a copy reloc. We can't check reliably at this
13546 stage whether the section is read-only, as input
13547 sections have not yet been mapped to output sections.
13548 Tentatively set the flag for now, and correct in
13549 adjust_dynamic_symbol. */
13550 h->non_got_ref = 1;
13551 }
13552
34e77a92
RS		 13553 if (may_need_local_target_p
13554 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 13555 {
34e77a92
RS		 13556 union gotplt_union *root_plt;
13557 struct arm_plt_info *arm_plt;
13558 struct arm_local_iplt_info *local_iplt;
13559
13560 if (h != NULL)
13561 {
13562 root_plt = &h->plt;
13563 arm_plt = &eh->plt;
13564 }
13565 else
13566 {
13567 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
13568 if (local_iplt == NULL)
13569 return FALSE;
13570 root_plt = &local_iplt->root;
13571 arm_plt = &local_iplt->arm;
13572 }
13573
f6e32f6d
RS		 13574 /* If the symbol is a function that doesn't bind locally,
13575 this relocation will need a PLT entry. */
a8c887dd
NC		 13576 if (root_plt->refcount != -1)
13577 root_plt->refcount += 1;
34e77a92
RS		 13578
13579 if (!call_reloc_p)
13580 arm_plt->noncall_refcount++;
f6e32f6d
RS		 13581
13582 /* It's too early to use htab->use_blx here, so we have to
13583 record possible blx references separately from
13584 relocs that definitely need a thumb stub. */
13585
13586 if (r_type == R_ARM_THM_CALL)
34e77a92 13587 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 13588
13589 if (r_type == R_ARM_THM_JUMP24
13590 || r_type == R_ARM_THM_JUMP19)
34e77a92 13591 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 13592 }
13593
13594 if (may_become_dynamic_p)
13595 {
13596 struct elf_dyn_relocs *p, **head;
13597
13598 /* Create a reloc section in dynobj. */
13599 if (sreloc == NULL)
13600 {
13601 sreloc = _bfd_elf_make_dynamic_reloc_section
13602 (sec, dynobj, 2, abfd, ! htab->use_rel);
13603
13604 if (sreloc == NULL)
13605 return FALSE;
13606
13607 /* BPABI objects never have dynamic relocations mapped. */
13608 if (htab->symbian_p)
13609 {
13610 flagword flags;
13611
13612 flags = bfd_get_section_flags (dynobj, sreloc);
13613 flags &= ~(SEC_LOAD | SEC_ALLOC);
13614 bfd_set_section_flags (dynobj, sreloc, flags);
13615 }
13616 }
13617
13618 /* If this is a global symbol, count the number of
13619 relocations we need for this symbol. */
13620 if (h != NULL)
13621 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
13622 else
13623 {
34e77a92
RS		 13624 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
13625 if (head == NULL)
f6e32f6d 13626 return FALSE;
f6e32f6d
RS		 13627 }
13628
13629 p = *head;
13630 if (p == NULL || p->sec != sec)
13631 {
13632 bfd_size_type amt = sizeof *p;
13633
13634 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
13635 if (p == NULL)
13636 return FALSE;
13637 p->next = *head;
13638 *head = p;
13639 p->sec = sec;
13640 p->count = 0;
13641 p->pc_count = 0;
13642 }
13643
469a3493 13644 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 13645 p->pc_count += 1;
13646 p->count += 1;
13647 }
252b5132 13648 }
f21f3fe0 13649
b34976b6 13650 return TRUE;
252b5132
RH		 13651}
13652
6a5bb875
PB		 13653/* Unwinding tables are not referenced directly. This pass marks them as
13654 required if the corresponding code section is marked. */
13655
13656static bfd_boolean
906e58ca
NC		 13657elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
13658 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 13659{
13660 bfd *sub;
13661 Elf_Internal_Shdr **elf_shdrp;
13662 bfd_boolean again;
13663
7f6ab9f8
AM		 13664 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
13665
6a5bb875
PB		 13666 /* Marking EH data may cause additional code sections to be marked,
13667 requiring multiple passes. */
13668 again = TRUE;
13669 while (again)
13670 {
13671 again = FALSE;
c72f2fb2 13672 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 13673 {
13674 asection *o;
13675
0ffa91dd 13676 if (! is_arm_elf (sub))
6a5bb875
PB		 13677 continue;
13678
13679 elf_shdrp = elf_elfsections (sub);
13680 for (o = sub->sections; o != NULL; o = o->next)
13681 {
13682 Elf_Internal_Shdr *hdr;
0ffa91dd 13683
6a5bb875 13684 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 13685 if (hdr->sh_type == SHT_ARM_EXIDX
13686 && hdr->sh_link
13687 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 13688 && !o->gc_mark
13689 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
13690 {
13691 again = TRUE;
13692 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
13693 return FALSE;
13694 }
13695 }
13696 }
13697 }
13698
13699 return TRUE;
13700}
13701
3c9458e9
NC		 13702/* Treat mapping symbols as special target symbols. */
13703
13704static bfd_boolean
13705elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
13706{
b0796911
PB		 13707 return bfd_is_arm_special_symbol_name (sym->name,
13708 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 13709}
13710
0367ecfb
NC		 13711/* This is a copy of elf_find_function() from elf.c except that
13712 ARM mapping symbols are ignored when looking for function names
13713 and STT_ARM_TFUNC is considered to a function type. */
252b5132 13714
0367ecfb
NC		 13715static bfd_boolean
13716arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 13717 asymbol ** symbols,
fb167eb2 13718 asection * section,
0367ecfb
NC		 13719 bfd_vma offset,
13720 const char ** filename_ptr,
13721 const char ** functionname_ptr)
13722{
13723 const char * filename = NULL;
13724 asymbol * func = NULL;
13725 bfd_vma low_func = 0;
13726 asymbol ** p;
252b5132
RH		 13727
13728 for (p = symbols; *p != NULL; p++)
13729 {
13730 elf_symbol_type *q;
13731
13732 q = (elf_symbol_type *) *p;
13733
252b5132
RH		 13734 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
13735 {
13736 default:
13737 break;
13738 case STT_FILE:
13739 filename = bfd_asymbol_name (&q->symbol);
13740 break;
252b5132
RH		 13741 case STT_FUNC:
13742 case STT_ARM_TFUNC:
9d2da7ca 13743 case STT_NOTYPE:
b0796911 13744 /* Skip mapping symbols. */
0367ecfb 13745 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 13746 && bfd_is_arm_special_symbol_name (q->symbol.name,
13747 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 13748 continue;
13749 /* Fall through. */
6b40fcba 13750 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 13751 && q->symbol.value >= low_func
13752 && q->symbol.value <= offset)
13753 {
13754 func = (asymbol *) q;
13755 low_func = q->symbol.value;
13756 }
13757 break;
13758 }
13759 }
13760
13761 if (func == NULL)
b34976b6 13762 return FALSE;
252b5132 13763
0367ecfb
NC		 13764 if (filename_ptr)
13765 *filename_ptr = filename;
13766 if (functionname_ptr)
13767 *functionname_ptr = bfd_asymbol_name (func);
13768
13769 return TRUE;
906e58ca 13770}
0367ecfb
NC		 13771
13772
13773/* Find the nearest line to a particular section and offset, for error
13774 reporting. This code is a duplicate of the code in elf.c, except
13775 that it uses arm_elf_find_function. */
13776
13777static bfd_boolean
13778elf32_arm_find_nearest_line (bfd * abfd,
0367ecfb 13779 asymbol ** symbols,
fb167eb2 13780 asection * section,
0367ecfb
NC		 13781 bfd_vma offset,
13782 const char ** filename_ptr,
13783 const char ** functionname_ptr,
fb167eb2
AM		 13784 unsigned int * line_ptr,
13785 unsigned int * discriminator_ptr)
0367ecfb
NC		 13786{
13787 bfd_boolean found = FALSE;
13788
fb167eb2 13789 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 13790 filename_ptr, functionname_ptr,
fb167eb2
AM		 13791 line_ptr, discriminator_ptr,
13792 dwarf_debug_sections, 0,
0367ecfb
NC		 13793 & elf_tdata (abfd)->dwarf2_find_line_info))
13794 {
13795 if (!*functionname_ptr)
fb167eb2 13796 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 13797 *filename_ptr ? NULL : filename_ptr,
13798 functionname_ptr);
f21f3fe0 13799
0367ecfb
NC		 13800 return TRUE;
13801 }
13802
fb167eb2
AM		 13803 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
13804 uses DWARF1. */
13805
0367ecfb
NC		 13806 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
13807 & found, filename_ptr,
13808 functionname_ptr, line_ptr,
13809 & elf_tdata (abfd)->line_info))
13810 return FALSE;
13811
13812 if (found && (*functionname_ptr || *line_ptr))
13813 return TRUE;
13814
13815 if (symbols == NULL)
13816 return FALSE;
13817
fb167eb2 13818 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 13819 filename_ptr, functionname_ptr))
13820 return FALSE;
13821
13822 *line_ptr = 0;
b34976b6 13823 return TRUE;
252b5132
RH		 13824}
13825
4ab527b0
FF		 13826static bfd_boolean
13827elf32_arm_find_inliner_info (bfd * abfd,
13828 const char ** filename_ptr,
13829 const char ** functionname_ptr,
13830 unsigned int * line_ptr)
13831{
13832 bfd_boolean found;
13833 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
13834 functionname_ptr, line_ptr,
13835 & elf_tdata (abfd)->dwarf2_find_line_info);
13836 return found;
13837}
13838
252b5132
RH		 13839/* Adjust a symbol defined by a dynamic object and referenced by a
13840 regular object. The current definition is in some section of the
13841 dynamic object, but we're not including those sections. We have to
13842 change the definition to something the rest of the link can
13843 understand. */
13844
b34976b6 13845static bfd_boolean
57e8b36a
NC		 13846elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
13847 struct elf_link_hash_entry * h)
252b5132
RH		 13848{
13849 bfd * dynobj;
13850 asection * s;
b7693d02 13851 struct elf32_arm_link_hash_entry * eh;
67687978 13852 struct elf32_arm_link_hash_table *globals;
252b5132 13853
67687978 13854 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13855 if (globals == NULL)
13856 return FALSE;
13857
252b5132
RH		 13858 dynobj = elf_hash_table (info)->dynobj;
13859
13860 /* Make sure we know what is going on here. */
13861 BFD_ASSERT (dynobj != NULL
f5385ebf 13862 && (h->needs_plt
34e77a92 13863 || h->type == STT_GNU_IFUNC
f6e332e6 13864 || h->u.weakdef != NULL
f5385ebf
AM		 13865 || (h->def_dynamic
13866 && h->ref_regular
13867 && !h->def_regular)));
252b5132 13868
b7693d02
DJ		 13869 eh = (struct elf32_arm_link_hash_entry *) h;
13870
252b5132
RH		 13871 /* If this is a function, put it in the procedure linkage table. We
13872 will fill in the contents of the procedure linkage table later,
13873 when we know the address of the .got section. */
34e77a92 13874 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 13875 {
34e77a92
RS		 13876 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
13877 symbol binds locally. */
5e681ec4 13878 if (h->plt.refcount <= 0
34e77a92
RS		 13879 || (h->type != STT_GNU_IFUNC
13880 && (SYMBOL_CALLS_LOCAL (info, h)
13881 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
13882 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 13883 {
13884 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 13885 file, but the symbol was never referred to by a dynamic
13886 object, or if all references were garbage collected. In
13887 such a case, we don't actually need to build a procedure
13888 linkage table, and we can just do a PC24 reloc instead. */
13889 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 13890 eh->plt.thumb_refcount = 0;
13891 eh->plt.maybe_thumb_refcount = 0;
13892 eh->plt.noncall_refcount = 0;
f5385ebf 13893 h->needs_plt = 0;
252b5132
RH		 13894 }
13895
b34976b6 13896 return TRUE;
252b5132 13897 }
5e681ec4 13898 else
b7693d02
DJ		 13899 {
13900 /* It's possible that we incorrectly decided a .plt reloc was
13901 needed for an R_ARM_PC24 or similar reloc to a non-function sym
13902 in check_relocs. We can't decide accurately between function
13903 and non-function syms in check-relocs; Objects loaded later in
13904 the link may change h->type. So fix it now. */
13905 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 13906 eh->plt.thumb_refcount = 0;
13907 eh->plt.maybe_thumb_refcount = 0;
13908 eh->plt.noncall_refcount = 0;
b7693d02 13909 }
252b5132
RH		 13910
13911 /* If this is a weak symbol, and there is a real definition, the
13912 processor independent code will have arranged for us to see the
13913 real definition first, and we can just use the same value. */
f6e332e6 13914 if (h->u.weakdef != NULL)
252b5132 13915 {
f6e332e6
AM		 13916 BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined
13917 || h->u.weakdef->root.type == bfd_link_hash_defweak);
13918 h->root.u.def.section = h->u.weakdef->root.u.def.section;
13919 h->root.u.def.value = h->u.weakdef->root.u.def.value;
b34976b6 13920 return TRUE;
252b5132
RH		 13921 }
13922
ba93b8ac
DJ		 13923 /* If there are no non-GOT references, we do not need a copy
13924 relocation. */
13925 if (!h->non_got_ref)
13926 return TRUE;
13927
252b5132
RH		 13928 /* This is a reference to a symbol defined by a dynamic object which
13929 is not a function. */
13930
13931 /* If we are creating a shared library, we must presume that the
13932 only references to the symbol are via the global offset table.
13933 For such cases we need not do anything here; the relocations will
67687978
PB		 13934 be handled correctly by relocate_section. Relocatable executables
13935 can reference data in shared objects directly, so we don't need to
13936 do anything here. */
0e1862bb 13937 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 13938 return TRUE;
252b5132
RH		 13939
13940 /* We must allocate the symbol in our .dynbss section, which will
13941 become part of the .bss section of the executable. There will be
13942 an entry for this symbol in the .dynsym section. The dynamic
13943 object will contain position independent code, so all references
13944 from the dynamic object to this symbol will go through the global
13945 offset table. The dynamic linker will use the .dynsym entry to
13946 determine the address it must put in the global offset table, so
13947 both the dynamic object and the regular object will refer to the
13948 same memory location for the variable. */
3d4d4302 13949 s = bfd_get_linker_section (dynobj, ".dynbss");
252b5132
RH		 13950 BFD_ASSERT (s != NULL);
13951
13952 /* We must generate a R_ARM_COPY reloc to tell the dynamic linker to
13953 copy the initial value out of the dynamic object and into the
13954 runtime process image. We need to remember the offset into the
00a97672 13955 .rel(a).bss section we are going to use. */
1d7e9d18 13956 if ((h->root.u.def.section->flags & SEC_ALLOC) != 0 && h->size != 0)
252b5132
RH		 13957 {
13958 asection *srel;
13959
3d4d4302 13960 srel = bfd_get_linker_section (dynobj, RELOC_SECTION (globals, ".bss"));
47beaa6a 13961 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 13962 h->needs_copy = 1;
252b5132
RH		 13963 }
13964
6cabe1ea 13965 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 13966}
13967
5e681ec4
PB		 13968/* Allocate space in .plt, .got and associated reloc sections for
13969 dynamic relocs. */
13970
13971static bfd_boolean
47beaa6a 13972allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 13973{
13974 struct bfd_link_info *info;
13975 struct elf32_arm_link_hash_table *htab;
13976 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 13977 struct elf_dyn_relocs *p;
5e681ec4
PB		 13978
13979 if (h->root.type == bfd_link_hash_indirect)
13980 return TRUE;
13981
e6a6bb22
AM		 13982 eh = (struct elf32_arm_link_hash_entry *) h;
13983
5e681ec4
PB		 13984 info = (struct bfd_link_info *) inf;
13985 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13986 if (htab == NULL)
13987 return FALSE;
5e681ec4 13988
34e77a92 13989 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 13990 && h->plt.refcount > 0)
13991 {
13992 /* Make sure this symbol is output as a dynamic symbol.
13993 Undefined weak syms won't yet be marked as dynamic. */
13994 if (h->dynindx == -1
f5385ebf 13995 && !h->forced_local)
5e681ec4 13996 {
c152c796 13997 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 13998 return FALSE;
13999 }
14000
34e77a92
RS		 14001 /* If the call in the PLT entry binds locally, the associated
14002 GOT entry should use an R_ARM_IRELATIVE relocation instead of
14003 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
14004 than the .plt section. */
14005 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
14006 {
14007 eh->is_iplt = 1;
14008 if (eh->plt.noncall_refcount == 0
14009 && SYMBOL_REFERENCES_LOCAL (info, h))
14010 /* All non-call references can be resolved directly.
14011 This means that they can (and in some cases, must)
14012 resolve directly to the run-time target, rather than
14013 to the PLT. That in turns means that any .got entry
14014 would be equal to the .igot.plt entry, so there's
14015 no point having both. */
14016 h->got.refcount = 0;
14017 }
14018
0e1862bb 14019 if (bfd_link_pic (info)
34e77a92 14020 || eh->is_iplt
7359ea65 14021 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 14022 {
34e77a92 14023 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 14024
5e681ec4
PB		 14025 /* If this symbol is not defined in a regular file, and we are
14026 not generating a shared library, then set the symbol to this
14027 location in the .plt. This is required to make function
14028 pointers compare as equal between the normal executable and
14029 the shared library. */
0e1862bb 14030 if (! bfd_link_pic (info)
f5385ebf 14031 && !h->def_regular)
5e681ec4 14032 {
34e77a92 14033 h->root.u.def.section = htab->root.splt;
5e681ec4 14034 h->root.u.def.value = h->plt.offset;
5e681ec4 14035
67d74e43
DJ		 14036 /* Make sure the function is not marked as Thumb, in case
14037 it is the target of an ABS32 relocation, which will
14038 point to the PLT entry. */
35fc36a8 14039 h->target_internal = ST_BRANCH_TO_ARM;
67d74e43 14040 }
022f8312 14041
00a97672
RS		 14042 /* VxWorks executables have a second set of relocations for
14043 each PLT entry. They go in a separate relocation section,
14044 which is processed by the kernel loader. */
0e1862bb 14045 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 14046 {
14047 /* There is a relocation for the initial PLT entry:
14048 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
14049 if (h->plt.offset == htab->plt_header_size)
47beaa6a 14050 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 14051
14052 /* There are two extra relocations for each subsequent
14053 PLT entry: an R_ARM_32 relocation for the GOT entry,
14054 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 14055 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 14056 }
5e681ec4
PB		 14057 }
14058 else
14059 {
14060 h->plt.offset = (bfd_vma) -1;
f5385ebf 14061 h->needs_plt = 0;
5e681ec4
PB		 14062 }
14063 }
14064 else
14065 {
14066 h->plt.offset = (bfd_vma) -1;
f5385ebf 14067 h->needs_plt = 0;
5e681ec4
PB		 14068 }
14069
0855e32b
NS		 14070 eh = (struct elf32_arm_link_hash_entry *) h;
14071 eh->tlsdesc_got = (bfd_vma) -1;
14072
5e681ec4
PB		 14073 if (h->got.refcount > 0)
14074 {
14075 asection *s;
14076 bfd_boolean dyn;
ba93b8ac
DJ		 14077 int tls_type = elf32_arm_hash_entry (h)->tls_type;
14078 int indx;
5e681ec4
PB		 14079
14080 /* Make sure this symbol is output as a dynamic symbol.
14081 Undefined weak syms won't yet be marked as dynamic. */
14082 if (h->dynindx == -1
f5385ebf 14083 && !h->forced_local)
5e681ec4 14084 {
c152c796 14085 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14086 return FALSE;
14087 }
14088
e5a52504
MM		 14089 if (!htab->symbian_p)
14090 {
362d30a1 14091 s = htab->root.sgot;
e5a52504 14092 h->got.offset = s->size;
ba93b8ac
DJ		 14093
14094 if (tls_type == GOT_UNKNOWN)
14095 abort ();
14096
14097 if (tls_type == GOT_NORMAL)
14098 /* Non-TLS symbols need one GOT slot. */
14099 s->size += 4;
14100 else
14101 {
99059e56
RM		 14102 if (tls_type & GOT_TLS_GDESC)
14103 {
0855e32b 14104 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 14105 eh->tlsdesc_got
0855e32b
NS		 14106 = (htab->root.sgotplt->size
14107 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 14108 htab->root.sgotplt->size += 8;
14109 h->got.offset = (bfd_vma) -2;
34e77a92 14110 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 14111 reloc in the middle of .got.plt. */
99059e56
RM		 14112 htab->num_tls_desc++;
14113 }
0855e32b 14114
ba93b8ac 14115 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 14116 {
14117 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
14118 the symbol is both GD and GDESC, got.offset may
14119 have been overwritten. */
14120 h->got.offset = s->size;
14121 s->size += 8;
14122 }
14123
ba93b8ac
DJ		 14124 if (tls_type & GOT_TLS_IE)
14125 /* R_ARM_TLS_IE32 needs one GOT slot. */
14126 s->size += 4;
14127 }
14128
e5a52504 14129 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 14130
14131 indx = 0;
0e1862bb
L		 14132 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
14133 bfd_link_pic (info),
14134 h)
14135 && (!bfd_link_pic (info)
ba93b8ac
DJ		 14136 || !SYMBOL_REFERENCES_LOCAL (info, h)))
14137 indx = h->dynindx;
14138
14139 if (tls_type != GOT_NORMAL
0e1862bb 14140 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 14141 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
14142 || h->root.type != bfd_link_hash_undefweak))
14143 {
14144 if (tls_type & GOT_TLS_IE)
47beaa6a 14145 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 14146
14147 if (tls_type & GOT_TLS_GD)
47beaa6a 14148 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 14149
b38cadfb 14150 if (tls_type & GOT_TLS_GDESC)
0855e32b 14151 {
47beaa6a 14152 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 14153 /* GDESC needs a trampoline to jump to. */
14154 htab->tls_trampoline = -1;
14155 }
14156
14157 /* Only GD needs it. GDESC just emits one relocation per
14158 2 entries. */
b38cadfb 14159 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 14160 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 14161 }
6f820c85 14162 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 14163 {
14164 if (htab->root.dynamic_sections_created)
14165 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
14166 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
14167 }
34e77a92
RS		 14168 else if (h->type == STT_GNU_IFUNC
14169 && eh->plt.noncall_refcount == 0)
14170 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
14171 they all resolve dynamically instead. Reserve room for the
14172 GOT entry's R_ARM_IRELATIVE relocation. */
14173 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 14174 else if (bfd_link_pic (info)
14175 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
14176 || h->root.type != bfd_link_hash_undefweak))
b436d854 14177 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 14178 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 14179 }
5e681ec4
PB		 14180 }
14181 else
14182 h->got.offset = (bfd_vma) -1;
14183
a4fd1a8e
PB		 14184 /* Allocate stubs for exported Thumb functions on v4t. */
14185 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 14186 && h->def_regular
35fc36a8 14187 && h->target_internal == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 14188 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
14189 {
14190 struct elf_link_hash_entry * th;
14191 struct bfd_link_hash_entry * bh;
14192 struct elf_link_hash_entry * myh;
14193 char name[1024];
14194 asection *s;
14195 bh = NULL;
14196 /* Create a new symbol to regist the real location of the function. */
14197 s = h->root.u.def.section;
906e58ca 14198 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 14199 _bfd_generic_link_add_one_symbol (info, s->owner,
14200 name, BSF_GLOBAL, s,
14201 h->root.u.def.value,
14202 NULL, TRUE, FALSE, &bh);
14203
14204 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 14205 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 14206 myh->forced_local = 1;
35fc36a8 14207 myh->target_internal = ST_BRANCH_TO_THUMB;
a4fd1a8e
PB		 14208 eh->export_glue = myh;
14209 th = record_arm_to_thumb_glue (info, h);
14210 /* Point the symbol at the stub. */
14211 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
35fc36a8 14212 h->target_internal = ST_BRANCH_TO_ARM;
a4fd1a8e
PB		 14213 h->root.u.def.section = th->root.u.def.section;
14214 h->root.u.def.value = th->root.u.def.value & ~1;
14215 }
14216
0bdcacaf 14217 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 14218 return TRUE;
14219
14220 /* In the shared -Bsymbolic case, discard space allocated for
14221 dynamic pc-relative relocs against symbols which turn out to be
14222 defined in regular objects. For the normal shared case, discard
14223 space for pc-relative relocs that have become local due to symbol
14224 visibility changes. */
14225
0e1862bb 14226 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 14227 {
469a3493
RM		 14228 /* Relocs that use pc_count are PC-relative forms, which will appear
14229 on something like ".long foo - ." or "movw REG, foo - .". We want
14230 calls to protected symbols to resolve directly to the function
14231 rather than going via the plt. If people want function pointer
14232 comparisons to work as expected then they should avoid writing
14233 assembly like ".long foo - .". */
ba93b8ac
DJ		 14234 if (SYMBOL_CALLS_LOCAL (info, h))
14235 {
0bdcacaf 14236 struct elf_dyn_relocs **pp;
ba93b8ac 14237
0bdcacaf 14238 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 14239 {
14240 p->count -= p->pc_count;
14241 p->pc_count = 0;
14242 if (p->count == 0)
14243 *pp = p->next;
14244 else
14245 pp = &p->next;
14246 }
14247 }
14248
4dfe6ac6 14249 if (htab->vxworks_p)
3348747a 14250 {
0bdcacaf 14251 struct elf_dyn_relocs **pp;
3348747a 14252
0bdcacaf 14253 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 14254 {
0bdcacaf 14255 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 14256 *pp = p->next;
14257 else
14258 pp = &p->next;
14259 }
14260 }
14261
ba93b8ac 14262 /* Also discard relocs on undefined weak syms with non-default
99059e56 14263 visibility. */
0bdcacaf 14264 if (eh->dyn_relocs != NULL
5e681ec4 14265 && h->root.type == bfd_link_hash_undefweak)
22d606e9
AM		 14266 {
14267 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT)
0bdcacaf 14268 eh->dyn_relocs = NULL;
22d606e9
AM		 14269
14270 /* Make sure undefined weak symbols are output as a dynamic
14271 symbol in PIEs. */
14272 else if (h->dynindx == -1
14273 && !h->forced_local)
14274 {
14275 if (! bfd_elf_link_record_dynamic_symbol (info, h))
14276 return FALSE;
14277 }
14278 }
14279
67687978
PB		 14280 else if (htab->root.is_relocatable_executable && h->dynindx == -1
14281 && h->root.type == bfd_link_hash_new)
14282 {
14283 /* Output absolute symbols so that we can create relocations
14284 against them. For normal symbols we output a relocation
14285 against the section that contains them. */
14286 if (! bfd_elf_link_record_dynamic_symbol (info, h))
14287 return FALSE;
14288 }
14289
5e681ec4
PB		 14290 }
14291 else
14292 {
14293 /* For the non-shared case, discard space for relocs against
14294 symbols which turn out to need copy relocs or are not
14295 dynamic. */
14296
f5385ebf
AM		 14297 if (!h->non_got_ref
14298 && ((h->def_dynamic
14299 && !h->def_regular)
5e681ec4
PB		 14300 || (htab->root.dynamic_sections_created
14301 && (h->root.type == bfd_link_hash_undefweak
14302 || h->root.type == bfd_link_hash_undefined))))
14303 {
14304 /* Make sure this symbol is output as a dynamic symbol.
14305 Undefined weak syms won't yet be marked as dynamic. */
14306 if (h->dynindx == -1
f5385ebf 14307 && !h->forced_local)
5e681ec4 14308 {
c152c796 14309 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14310 return FALSE;
14311 }
14312
14313 /* If that succeeded, we know we'll be keeping all the
14314 relocs. */
14315 if (h->dynindx != -1)
14316 goto keep;
14317 }
14318
0bdcacaf 14319 eh->dyn_relocs = NULL;
5e681ec4
PB		 14320
14321 keep: ;
14322 }
14323
14324 /* Finally, allocate space. */
0bdcacaf 14325 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 14326 {
0bdcacaf 14327 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 14328 if (h->type == STT_GNU_IFUNC
14329 && eh->plt.noncall_refcount == 0
14330 && SYMBOL_REFERENCES_LOCAL (info, h))
14331 elf32_arm_allocate_irelocs (info, sreloc, p->count);
14332 else
14333 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 14334 }
14335
14336 return TRUE;
14337}
14338
08d1f311
DJ		 14339/* Find any dynamic relocs that apply to read-only sections. */
14340
14341static bfd_boolean
8029a119 14342elf32_arm_readonly_dynrelocs (struct elf_link_hash_entry * h, void * inf)
08d1f311 14343{
8029a119 14344 struct elf32_arm_link_hash_entry * eh;
0bdcacaf 14345 struct elf_dyn_relocs * p;
08d1f311 14346
08d1f311 14347 eh = (struct elf32_arm_link_hash_entry *) h;
0bdcacaf 14348 for (p = eh->dyn_relocs; p != NULL; p = p->next)
08d1f311 14349 {
0bdcacaf 14350 asection *s = p->sec;
08d1f311
DJ		 14351
14352 if (s != NULL && (s->flags & SEC_READONLY) != 0)
14353 {
14354 struct bfd_link_info *info = (struct bfd_link_info *) inf;
14355
14356 info->flags |= DF_TEXTREL;
14357
14358 /* Not an error, just cut short the traversal. */
14359 return FALSE;
14360 }
14361 }
14362 return TRUE;
14363}
14364
d504ffc8
DJ		 14365void
14366bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
14367 int byteswap_code)
14368{
14369 struct elf32_arm_link_hash_table *globals;
14370
14371 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14372 if (globals == NULL)
14373 return;
14374
d504ffc8
DJ		 14375 globals->byteswap_code = byteswap_code;
14376}
14377
252b5132
RH		 14378/* Set the sizes of the dynamic sections. */
14379
b34976b6 14380static bfd_boolean
57e8b36a
NC		 14381elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
14382 struct bfd_link_info * info)
252b5132
RH		 14383{
14384 bfd * dynobj;
14385 asection * s;
b34976b6
AM		 14386 bfd_boolean plt;
14387 bfd_boolean relocs;
5e681ec4
PB		 14388 bfd *ibfd;
14389 struct elf32_arm_link_hash_table *htab;
252b5132 14390
5e681ec4 14391 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14392 if (htab == NULL)
14393 return FALSE;
14394
252b5132
RH		 14395 dynobj = elf_hash_table (info)->dynobj;
14396 BFD_ASSERT (dynobj != NULL);
39b41c9c 14397 check_use_blx (htab);
252b5132
RH		 14398
14399 if (elf_hash_table (info)->dynamic_sections_created)
14400 {
14401 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 14402 if (bfd_link_executable (info) && !info->nointerp)
252b5132 14403 {
3d4d4302 14404 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 14405 BFD_ASSERT (s != NULL);
eea6121a 14406 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 14407 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
14408 }
14409 }
5e681ec4
PB		 14410
14411 /* Set up .got offsets for local syms, and space for local dynamic
14412 relocs. */
c72f2fb2 14413 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 14414 {
5e681ec4
PB		 14415 bfd_signed_vma *local_got;
14416 bfd_signed_vma *end_local_got;
34e77a92 14417 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 14418 char *local_tls_type;
0855e32b 14419 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 14420 bfd_size_type locsymcount;
14421 Elf_Internal_Shdr *symtab_hdr;
14422 asection *srel;
4dfe6ac6 14423 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 14424 unsigned int symndx;
5e681ec4 14425
0ffa91dd 14426 if (! is_arm_elf (ibfd))
5e681ec4
PB		 14427 continue;
14428
14429 for (s = ibfd->sections; s != NULL; s = s->next)
14430 {
0bdcacaf 14431 struct elf_dyn_relocs *p;
5e681ec4 14432
0bdcacaf 14433 for (p = (struct elf_dyn_relocs *)
99059e56 14434 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 14435 {
0bdcacaf
RS		 14436 if (!bfd_is_abs_section (p->sec)
14437 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 14438 {
14439 /* Input section has been discarded, either because
14440 it is a copy of a linkonce section or due to
14441 linker script /DISCARD/, so we'll be discarding
14442 the relocs too. */
14443 }
3348747a 14444 else if (is_vxworks
0bdcacaf 14445 && strcmp (p->sec->output_section->name,
3348747a
NS		 14446 ".tls_vars") == 0)
14447 {
14448 /* Relocations in vxworks .tls_vars sections are
14449 handled specially by the loader. */
14450 }
5e681ec4
PB		 14451 else if (p->count != 0)
14452 {
0bdcacaf 14453 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 14454 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 14455 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 14456 info->flags |= DF_TEXTREL;
14457 }
14458 }
14459 }
14460
14461 local_got = elf_local_got_refcounts (ibfd);
14462 if (!local_got)
14463 continue;
14464
0ffa91dd 14465 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 14466 locsymcount = symtab_hdr->sh_info;
14467 end_local_got = local_got + locsymcount;
34e77a92 14468 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 14469 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 14470 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 14471 symndx = 0;
362d30a1
RS		 14472 s = htab->root.sgot;
14473 srel = htab->root.srelgot;
0855e32b 14474 for (; local_got < end_local_got;
34e77a92
RS		 14475 ++local_got, ++local_iplt_ptr, ++local_tls_type,
14476 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 14477 {
0855e32b 14478 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 14479 local_iplt = *local_iplt_ptr;
14480 if (local_iplt != NULL)
14481 {
14482 struct elf_dyn_relocs *p;
14483
14484 if (local_iplt->root.refcount > 0)
14485 {
14486 elf32_arm_allocate_plt_entry (info, TRUE,
14487 &local_iplt->root,
14488 &local_iplt->arm);
14489 if (local_iplt->arm.noncall_refcount == 0)
14490 /* All references to the PLT are calls, so all
14491 non-call references can resolve directly to the
14492 run-time target. This means that the .got entry
14493 would be the same as the .igot.plt entry, so there's
14494 no point creating both. */
14495 *local_got = 0;
14496 }
14497 else
14498 {
14499 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
14500 local_iplt->root.offset = (bfd_vma) -1;
14501 }
14502
14503 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
14504 {
14505 asection *psrel;
14506
14507 psrel = elf_section_data (p->sec)->sreloc;
14508 if (local_iplt->arm.noncall_refcount == 0)
14509 elf32_arm_allocate_irelocs (info, psrel, p->count);
14510 else
14511 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
14512 }
14513 }
5e681ec4
PB		 14514 if (*local_got > 0)
14515 {
34e77a92
RS		 14516 Elf_Internal_Sym *isym;
14517
eea6121a 14518 *local_got = s->size;
ba93b8ac
DJ		 14519 if (*local_tls_type & GOT_TLS_GD)
14520 /* TLS_GD relocs need an 8-byte structure in the GOT. */
14521 s->size += 8;
0855e32b
NS		 14522 if (*local_tls_type & GOT_TLS_GDESC)
14523 {
14524 *local_tlsdesc_gotent = htab->root.sgotplt->size
14525 - elf32_arm_compute_jump_table_size (htab);
14526 htab->root.sgotplt->size += 8;
14527 *local_got = (bfd_vma) -2;
34e77a92 14528 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 14529 reloc in the middle of .got.plt. */
99059e56 14530 htab->num_tls_desc++;
0855e32b 14531 }
ba93b8ac
DJ		 14532 if (*local_tls_type & GOT_TLS_IE)
14533 s->size += 4;
ba93b8ac 14534
0855e32b
NS		 14535 if (*local_tls_type & GOT_NORMAL)
14536 {
14537 /* If the symbol is both GD and GDESC, *local_got
14538 may have been overwritten. */
14539 *local_got = s->size;
14540 s->size += 4;
14541 }
14542
34e77a92
RS		 14543 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
14544 if (isym == NULL)
14545 return FALSE;
14546
14547 /* If all references to an STT_GNU_IFUNC PLT are calls,
14548 then all non-call references, including this GOT entry,
14549 resolve directly to the run-time target. */
14550 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
14551 && (local_iplt == NULL
14552 || local_iplt->arm.noncall_refcount == 0))
14553 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 14554 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 14555 {
0e1862bb 14556 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 14557 || *local_tls_type & GOT_TLS_GD)
14558 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 14559
0e1862bb 14560 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 14561 {
14562 elf32_arm_allocate_dynrelocs (info,
14563 htab->root.srelplt, 1);
14564 htab->tls_trampoline = -1;
14565 }
0855e32b 14566 }
5e681ec4
PB		 14567 }
14568 else
14569 *local_got = (bfd_vma) -1;
14570 }
252b5132
RH		 14571 }
14572
ba93b8ac
DJ		 14573 if (htab->tls_ldm_got.refcount > 0)
14574 {
14575 /* Allocate two GOT entries and one dynamic relocation (if necessary)
14576 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 14577 htab->tls_ldm_got.offset = htab->root.sgot->size;
14578 htab->root.sgot->size += 8;
0e1862bb 14579 if (bfd_link_pic (info))
47beaa6a 14580 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 14581 }
14582 else
14583 htab->tls_ldm_got.offset = -1;
14584
5e681ec4
PB		 14585 /* Allocate global sym .plt and .got entries, and space for global
14586 sym dynamic relocs. */
47beaa6a 14587 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 14588
d504ffc8 14589 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 14590 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 14591 {
0ffa91dd 14592 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 14593 continue;
14594
c7b8f16e
JB		 14595 /* Initialise mapping tables for code/data. */
14596 bfd_elf32_arm_init_maps (ibfd);
906e58ca 14597
c7b8f16e 14598 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 14599 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
14600 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
99059e56
RM		 14601 /* xgettext:c-format */
14602 _bfd_error_handler (_("Errors encountered processing file %s"),
c7b8f16e
JB		 14603 ibfd->filename);
14604 }
d504ffc8 14605
3e6b1042
DJ		 14606 /* Allocate space for the glue sections now that we've sized them. */
14607 bfd_elf32_arm_allocate_interworking_sections (info);
14608
0855e32b
NS		 14609 /* For every jump slot reserved in the sgotplt, reloc_count is
14610 incremented. However, when we reserve space for TLS descriptors,
14611 it's not incremented, so in order to compute the space reserved
14612 for them, it suffices to multiply the reloc count by the jump
14613 slot size. */
14614 if (htab->root.srelplt)
14615 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
14616
14617 if (htab->tls_trampoline)
14618 {
14619 if (htab->root.splt->size == 0)
14620 htab->root.splt->size += htab->plt_header_size;
b38cadfb 14621
0855e32b
NS		 14622 htab->tls_trampoline = htab->root.splt->size;
14623 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 14624
0855e32b 14625 /* If we're not using lazy TLS relocations, don't generate the
99059e56 14626 PLT and GOT entries they require. */
0855e32b
NS		 14627 if (!(info->flags & DF_BIND_NOW))
14628 {
14629 htab->dt_tlsdesc_got = htab->root.sgot->size;
14630 htab->root.sgot->size += 4;
14631
14632 htab->dt_tlsdesc_plt = htab->root.splt->size;
14633 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
14634 }
14635 }
14636
252b5132
RH		 14637 /* The check_relocs and adjust_dynamic_symbol entry points have
14638 determined the sizes of the various dynamic sections. Allocate
14639 memory for them. */
b34976b6
AM		 14640 plt = FALSE;
14641 relocs = FALSE;
252b5132
RH		 14642 for (s = dynobj->sections; s != NULL; s = s->next)
14643 {
14644 const char * name;
252b5132
RH		 14645
14646 if ((s->flags & SEC_LINKER_CREATED) == 0)
14647 continue;
14648
14649 /* It's OK to base decisions on the section name, because none
14650 of the dynobj section names depend upon the input files. */
14651 name = bfd_get_section_name (dynobj, s);
14652
34e77a92 14653 if (s == htab->root.splt)
252b5132 14654 {
c456f082
AM		 14655 /* Remember whether there is a PLT. */
14656 plt = s->size != 0;
252b5132 14657 }
0112cd26 14658 else if (CONST_STRNEQ (name, ".rel"))
252b5132 14659 {
c456f082 14660 if (s->size != 0)
252b5132 14661 {
252b5132 14662 /* Remember whether there are any reloc sections other
00a97672 14663 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 14664 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 14665 relocs = TRUE;
252b5132
RH		 14666
14667 /* We use the reloc_count field as a counter if we need
14668 to copy relocs into the output file. */
14669 s->reloc_count = 0;
14670 }
14671 }
34e77a92
RS		 14672 else if (s != htab->root.sgot
14673 && s != htab->root.sgotplt
14674 && s != htab->root.iplt
14675 && s != htab->root.igotplt
14676 && s != htab->sdynbss)
252b5132
RH		 14677 {
14678 /* It's not one of our sections, so don't allocate space. */
14679 continue;
14680 }
14681
c456f082 14682 if (s->size == 0)
252b5132 14683 {
c456f082 14684 /* If we don't need this section, strip it from the
00a97672
RS		 14685 output file. This is mostly to handle .rel(a).bss and
14686 .rel(a).plt. We must create both sections in
c456f082
AM		 14687 create_dynamic_sections, because they must be created
14688 before the linker maps input sections to output
14689 sections. The linker does that before
14690 adjust_dynamic_symbol is called, and it is that
14691 function which decides whether anything needs to go
14692 into these sections. */
8423293d 14693 s->flags |= SEC_EXCLUDE;
252b5132
RH		 14694 continue;
14695 }
14696
c456f082
AM		 14697 if ((s->flags & SEC_HAS_CONTENTS) == 0)
14698 continue;
14699
252b5132 14700 /* Allocate memory for the section contents. */
21d799b5 14701 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 14702 if (s->contents == NULL)
b34976b6 14703 return FALSE;
252b5132
RH		 14704 }
14705
14706 if (elf_hash_table (info)->dynamic_sections_created)
14707 {
14708 /* Add some entries to the .dynamic section. We fill in the
14709 values later, in elf32_arm_finish_dynamic_sections, but we
14710 must add the entries now so that we get the correct size for
14711 the .dynamic section. The DT_DEBUG entry is filled in by the
14712 dynamic linker and used by the debugger. */
dc810e39 14713#define add_dynamic_entry(TAG, VAL) \
5a580b3a 14714 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 14715
0e1862bb 14716 if (bfd_link_executable (info))
252b5132 14717 {
dc810e39 14718 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 14719 return FALSE;
252b5132
RH		 14720 }
14721
14722 if (plt)
14723 {
dc810e39
AM		 14724 if ( !add_dynamic_entry (DT_PLTGOT, 0)
14725 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 14726 || !add_dynamic_entry (DT_PLTREL,
14727 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 14728 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 14729 return FALSE;
0855e32b
NS		 14730
14731 if (htab->dt_tlsdesc_plt &&
b38cadfb 14732 (!add_dynamic_entry (DT_TLSDESC_PLT,0)
0855e32b 14733 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 14734 return FALSE;
252b5132
RH		 14735 }
14736
14737 if (relocs)
14738 {
00a97672
RS		 14739 if (htab->use_rel)
14740 {
14741 if (!add_dynamic_entry (DT_REL, 0)
14742 || !add_dynamic_entry (DT_RELSZ, 0)
14743 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
14744 return FALSE;
14745 }
14746 else
14747 {
14748 if (!add_dynamic_entry (DT_RELA, 0)
14749 || !add_dynamic_entry (DT_RELASZ, 0)
14750 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
14751 return FALSE;
14752 }
252b5132
RH		 14753 }
14754
08d1f311
DJ		 14755 /* If any dynamic relocs apply to a read-only section,
14756 then we need a DT_TEXTREL entry. */
14757 if ((info->flags & DF_TEXTREL) == 0)
8029a119
NC		 14758 elf_link_hash_traverse (& htab->root, elf32_arm_readonly_dynrelocs,
14759 info);
08d1f311 14760
99e4ae17 14761 if ((info->flags & DF_TEXTREL) != 0)
252b5132 14762 {
dc810e39 14763 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 14764 return FALSE;
252b5132 14765 }
7a2b07ff
NS		 14766 if (htab->vxworks_p
14767 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
14768 return FALSE;
252b5132 14769 }
8532796c 14770#undef add_dynamic_entry
252b5132 14771
b34976b6 14772 return TRUE;
252b5132
RH		 14773}
14774
0855e32b
NS		 14775/* Size sections even though they're not dynamic. We use it to setup
14776 _TLS_MODULE_BASE_, if needed. */
14777
14778static bfd_boolean
14779elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 14780 struct bfd_link_info *info)
0855e32b
NS		 14781{
14782 asection *tls_sec;
14783
0e1862bb 14784 if (bfd_link_relocatable (info))
0855e32b
NS		 14785 return TRUE;
14786
14787 tls_sec = elf_hash_table (info)->tls_sec;
14788
14789 if (tls_sec)
14790 {
14791 struct elf_link_hash_entry *tlsbase;
14792
14793 tlsbase = elf_link_hash_lookup
14794 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
14795
14796 if (tlsbase)
99059e56
RM		 14797 {
14798 struct bfd_link_hash_entry *bh = NULL;
0855e32b 14799 const struct elf_backend_data *bed
99059e56 14800 = get_elf_backend_data (output_bfd);
0855e32b 14801
99059e56 14802 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 14803 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
14804 tls_sec, 0, NULL, FALSE,
14805 bed->collect, &bh)))
14806 return FALSE;
b38cadfb 14807
99059e56
RM		 14808 tlsbase->type = STT_TLS;
14809 tlsbase = (struct elf_link_hash_entry *)bh;
14810 tlsbase->def_regular = 1;
14811 tlsbase->other = STV_HIDDEN;
14812 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 14813 }
14814 }
14815 return TRUE;
14816}
14817
252b5132
RH		 14818/* Finish up dynamic symbol handling. We set the contents of various
14819 dynamic sections here. */
14820
b34976b6 14821static bfd_boolean
906e58ca
NC		 14822elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
14823 struct bfd_link_info * info,
14824 struct elf_link_hash_entry * h,
14825 Elf_Internal_Sym * sym)
252b5132 14826{
e5a52504 14827 struct elf32_arm_link_hash_table *htab;
b7693d02 14828 struct elf32_arm_link_hash_entry *eh;
252b5132 14829
e5a52504 14830 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14831 if (htab == NULL)
14832 return FALSE;
14833
b7693d02 14834 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 14835
14836 if (h->plt.offset != (bfd_vma) -1)
14837 {
34e77a92 14838 if (!eh->is_iplt)
e5a52504 14839 {
34e77a92 14840 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 14841 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
14842 h->dynindx, 0))
14843 return FALSE;
e5a52504 14844 }
57e8b36a 14845
f5385ebf 14846 if (!h->def_regular)
252b5132
RH		 14847 {
14848 /* Mark the symbol as undefined, rather than as defined in
3a635617 14849 the .plt section. */
252b5132 14850 sym->st_shndx = SHN_UNDEF;
3a635617 14851 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 14852 Otherwise, the PLT entry would provide a definition for
14853 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 14854 and so the symbol would never be NULL. Leave the value if
14855 there were any relocations where pointer equality matters
14856 (this is a clue for the dynamic linker, to make function
14857 pointer comparisons work between an application and shared
14858 library). */
97323ad1 14859 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 14860 sym->st_value = 0;
252b5132 14861 }
34e77a92
RS		 14862 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
14863 {
14864 /* At least one non-call relocation references this .iplt entry,
14865 so the .iplt entry is the function's canonical address. */
14866 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
14867 sym->st_target_internal = ST_BRANCH_TO_ARM;
14868 sym->st_shndx = (_bfd_elf_section_from_bfd_section
14869 (output_bfd, htab->root.iplt->output_section));
14870 sym->st_value = (h->plt.offset
14871 + htab->root.iplt->output_section->vma
14872 + htab->root.iplt->output_offset);
14873 }
252b5132
RH		 14874 }
14875
f5385ebf 14876 if (h->needs_copy)
252b5132
RH		 14877 {
14878 asection * s;
947216bf 14879 Elf_Internal_Rela rel;
252b5132
RH		 14880
14881 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 14882 BFD_ASSERT (h->dynindx != -1
14883 && (h->root.type == bfd_link_hash_defined
14884 || h->root.type == bfd_link_hash_defweak));
14885
362d30a1 14886 s = htab->srelbss;
252b5132
RH		 14887 BFD_ASSERT (s != NULL);
14888
00a97672 14889 rel.r_addend = 0;
252b5132
RH		 14890 rel.r_offset = (h->root.u.def.value
14891 + h->root.u.def.section->output_section->vma
14892 + h->root.u.def.section->output_offset);
14893 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
47beaa6a 14894 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 14895 }
14896
00a97672
RS		 14897 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
14898 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
14899 to the ".got" section. */
9637f6ef 14900 if (h == htab->root.hdynamic
00a97672 14901 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 14902 sym->st_shndx = SHN_ABS;
14903
b34976b6 14904 return TRUE;
252b5132
RH		 14905}
14906
0855e32b
NS		 14907static void
14908arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
14909 void *contents,
14910 const unsigned long *template, unsigned count)
14911{
14912 unsigned ix;
b38cadfb 14913
0855e32b
NS		 14914 for (ix = 0; ix != count; ix++)
14915 {
14916 unsigned long insn = template[ix];
14917
14918 /* Emit mov pc,rx if bx is not permitted. */
14919 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
14920 insn = (insn & 0xf000000f) | 0x01a0f000;
14921 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
14922 }
14923}
14924
99059e56
RM		 14925/* Install the special first PLT entry for elf32-arm-nacl. Unlike
14926 other variants, NaCl needs this entry in a static executable's
14927 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
14928 zero. For .iplt really only the last bundle is useful, and .iplt
14929 could have a shorter first entry, with each individual PLT entry's
14930 relative branch calculated differently so it targets the last
14931 bundle instead of the instruction before it (labelled .Lplt_tail
14932 above). But it's simpler to keep the size and layout of PLT0
14933 consistent with the dynamic case, at the cost of some dead code at
14934 the start of .iplt and the one dead store to the stack at the start
14935 of .Lplt_tail. */
14936static void
14937arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
14938 asection *plt, bfd_vma got_displacement)
14939{
14940 unsigned int i;
14941
14942 put_arm_insn (htab, output_bfd,
14943 elf32_arm_nacl_plt0_entry[0]
14944 | arm_movw_immediate (got_displacement),
14945 plt->contents + 0);
14946 put_arm_insn (htab, output_bfd,
14947 elf32_arm_nacl_plt0_entry[1]
14948 | arm_movt_immediate (got_displacement),
14949 plt->contents + 4);
14950
14951 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
14952 put_arm_insn (htab, output_bfd,
14953 elf32_arm_nacl_plt0_entry[i],
14954 plt->contents + (i * 4));
14955}
14956
252b5132
RH		 14957/* Finish up the dynamic sections. */
14958
b34976b6 14959static bfd_boolean
57e8b36a 14960elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 14961{
14962 bfd * dynobj;
14963 asection * sgot;
14964 asection * sdyn;
4dfe6ac6
NC		 14965 struct elf32_arm_link_hash_table *htab;
14966
14967 htab = elf32_arm_hash_table (info);
14968 if (htab == NULL)
14969 return FALSE;
252b5132
RH		 14970
14971 dynobj = elf_hash_table (info)->dynobj;
14972
362d30a1 14973 sgot = htab->root.sgotplt;
894891db
NC		 14974 /* A broken linker script might have discarded the dynamic sections.
14975 Catch this here so that we do not seg-fault later on. */
14976 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
14977 return FALSE;
3d4d4302 14978 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 14979
14980 if (elf_hash_table (info)->dynamic_sections_created)
14981 {
14982 asection *splt;
14983 Elf32_External_Dyn *dyncon, *dynconend;
14984
362d30a1 14985 splt = htab->root.splt;
24a1ba0f 14986 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 14987 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 14988
14989 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 14990 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 14991
252b5132
RH		 14992 for (; dyncon < dynconend; dyncon++)
14993 {
14994 Elf_Internal_Dyn dyn;
14995 const char * name;
14996 asection * s;
14997
14998 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
14999
15000 switch (dyn.d_tag)
15001 {
229fcec5
MM		 15002 unsigned int type;
15003
252b5132 15004 default:
7a2b07ff
NS		 15005 if (htab->vxworks_p
15006 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
15007 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 15008 break;
15009
229fcec5
MM		 15010 case DT_HASH:
15011 name = ".hash";
15012 goto get_vma_if_bpabi;
15013 case DT_STRTAB:
15014 name = ".dynstr";
15015 goto get_vma_if_bpabi;
15016 case DT_SYMTAB:
15017 name = ".dynsym";
15018 goto get_vma_if_bpabi;
c0042f5d
MM		 15019 case DT_VERSYM:
15020 name = ".gnu.version";
15021 goto get_vma_if_bpabi;
15022 case DT_VERDEF:
15023 name = ".gnu.version_d";
15024 goto get_vma_if_bpabi;
15025 case DT_VERNEED:
15026 name = ".gnu.version_r";
15027 goto get_vma_if_bpabi;
15028
252b5132
RH		 15029 case DT_PLTGOT:
15030 name = ".got";
15031 goto get_vma;
15032 case DT_JMPREL:
00a97672 15033 name = RELOC_SECTION (htab, ".plt");
252b5132
RH		 15034 get_vma:
15035 s = bfd_get_section_by_name (output_bfd, name);
05456594
NC		 15036 if (s == NULL)
15037 {
15038 /* PR ld/14397: Issue an error message if a required section is missing. */
15039 (*_bfd_error_handler)
15040 (_("error: required section '%s' not found in the linker script"), name);
15041 bfd_set_error (bfd_error_invalid_operation);
15042 return FALSE;
15043 }
229fcec5
MM		 15044 if (!htab->symbian_p)
15045 dyn.d_un.d_ptr = s->vma;
15046 else
15047 /* In the BPABI, tags in the PT_DYNAMIC section point
15048 at the file offset, not the memory address, for the
15049 convenience of the post linker. */
15050 dyn.d_un.d_ptr = s->filepos;
252b5132
RH		 15051 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15052 break;
15053
229fcec5
MM		 15054 get_vma_if_bpabi:
15055 if (htab->symbian_p)
15056 goto get_vma;
15057 break;
15058
252b5132 15059 case DT_PLTRELSZ:
362d30a1 15060 s = htab->root.srelplt;
252b5132 15061 BFD_ASSERT (s != NULL);
eea6121a 15062 dyn.d_un.d_val = s->size;
252b5132
RH		 15063 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15064 break;
906e58ca 15065
252b5132 15066 case DT_RELSZ:
00a97672 15067 case DT_RELASZ:
229fcec5
MM		 15068 if (!htab->symbian_p)
15069 {
15070 /* My reading of the SVR4 ABI indicates that the
15071 procedure linkage table relocs (DT_JMPREL) should be
15072 included in the overall relocs (DT_REL). This is
15073 what Solaris does. However, UnixWare can not handle
15074 that case. Therefore, we override the DT_RELSZ entry
15075 here to make it not include the JMPREL relocs. Since
00a97672 15076 the linker script arranges for .rel(a).plt to follow all
229fcec5
MM		 15077 other relocation sections, we don't have to worry
15078 about changing the DT_REL entry. */
362d30a1 15079 s = htab->root.srelplt;
229fcec5
MM		 15080 if (s != NULL)
15081 dyn.d_un.d_val -= s->size;
15082 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15083 break;
15084 }
8029a119 15085 /* Fall through. */
229fcec5
MM		 15086
15087 case DT_REL:
15088 case DT_RELA:
229fcec5
MM		 15089 /* In the BPABI, the DT_REL tag must point at the file
15090 offset, not the VMA, of the first relocation
15091 section. So, we use code similar to that in
15092 elflink.c, but do not check for SHF_ALLOC on the
15093 relcoation section, since relocations sections are
15094 never allocated under the BPABI. The comments above
15095 about Unixware notwithstanding, we include all of the
15096 relocations here. */
15097 if (htab->symbian_p)
15098 {
15099 unsigned int i;
15100 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
15101 ? SHT_REL : SHT_RELA);
15102 dyn.d_un.d_val = 0;
15103 for (i = 1; i < elf_numsections (output_bfd); i++)
15104 {
906e58ca 15105 Elf_Internal_Shdr *hdr
229fcec5
MM		 15106 = elf_elfsections (output_bfd)[i];
15107 if (hdr->sh_type == type)
15108 {
906e58ca 15109 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 15110 || dyn.d_tag == DT_RELASZ)
15111 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 15112 else if ((ufile_ptr) hdr->sh_offset
15113 <= dyn.d_un.d_val - 1)
229fcec5
MM		 15114 dyn.d_un.d_val = hdr->sh_offset;
15115 }
15116 }
15117 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15118 }
252b5132 15119 break;
88f7bcd5 15120
0855e32b 15121 case DT_TLSDESC_PLT:
99059e56 15122 s = htab->root.splt;
0855e32b
NS		 15123 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
15124 + htab->dt_tlsdesc_plt);
15125 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15126 break;
15127
15128 case DT_TLSDESC_GOT:
99059e56 15129 s = htab->root.sgot;
0855e32b 15130 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 15131 + htab->dt_tlsdesc_got);
0855e32b
NS		 15132 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15133 break;
15134
88f7bcd5
NC		 15135 /* Set the bottom bit of DT_INIT/FINI if the
15136 corresponding function is Thumb. */
15137 case DT_INIT:
15138 name = info->init_function;
15139 goto get_sym;
15140 case DT_FINI:
15141 name = info->fini_function;
15142 get_sym:
15143 /* If it wasn't set by elf_bfd_final_link
4cc11e76 15144 then there is nothing to adjust. */
88f7bcd5
NC		 15145 if (dyn.d_un.d_val != 0)
15146 {
15147 struct elf_link_hash_entry * eh;
15148
15149 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 15150 FALSE, FALSE, TRUE);
35fc36a8 15151 if (eh != NULL && eh->target_internal == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 15152 {
15153 dyn.d_un.d_val |= 1;
b34976b6 15154 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 15155 }
15156 }
15157 break;
252b5132
RH		 15158 }
15159 }
15160
24a1ba0f 15161 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 15162 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 15163 {
00a97672
RS		 15164 const bfd_vma *plt0_entry;
15165 bfd_vma got_address, plt_address, got_displacement;
15166
15167 /* Calculate the addresses of the GOT and PLT. */
15168 got_address = sgot->output_section->vma + sgot->output_offset;
15169 plt_address = splt->output_section->vma + splt->output_offset;
15170
15171 if (htab->vxworks_p)
15172 {
15173 /* The VxWorks GOT is relocated by the dynamic linker.
15174 Therefore, we must emit relocations rather than simply
15175 computing the values now. */
15176 Elf_Internal_Rela rel;
15177
15178 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 15179 put_arm_insn (htab, output_bfd, plt0_entry[0],
15180 splt->contents + 0);
15181 put_arm_insn (htab, output_bfd, plt0_entry[1],
15182 splt->contents + 4);
15183 put_arm_insn (htab, output_bfd, plt0_entry[2],
15184 splt->contents + 8);
00a97672
RS		 15185 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
15186
8029a119 15187 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 15188 rel.r_offset = plt_address + 12;
15189 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
15190 rel.r_addend = 0;
15191 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
15192 htab->srelplt2->contents);
15193 }
b38cadfb 15194 else if (htab->nacl_p)
99059e56
RM		 15195 arm_nacl_put_plt0 (htab, output_bfd, splt,
15196 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 15197 else if (using_thumb_only (htab))
15198 {
15199 got_displacement = got_address - (plt_address + 12);
15200
15201 plt0_entry = elf32_thumb2_plt0_entry;
15202 put_arm_insn (htab, output_bfd, plt0_entry[0],
15203 splt->contents + 0);
15204 put_arm_insn (htab, output_bfd, plt0_entry[1],
15205 splt->contents + 4);
15206 put_arm_insn (htab, output_bfd, plt0_entry[2],
15207 splt->contents + 8);
15208
15209 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
15210 }
00a97672
RS		 15211 else
15212 {
15213 got_displacement = got_address - (plt_address + 16);
15214
15215 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 15216 put_arm_insn (htab, output_bfd, plt0_entry[0],
15217 splt->contents + 0);
15218 put_arm_insn (htab, output_bfd, plt0_entry[1],
15219 splt->contents + 4);
15220 put_arm_insn (htab, output_bfd, plt0_entry[2],
15221 splt->contents + 8);
15222 put_arm_insn (htab, output_bfd, plt0_entry[3],
15223 splt->contents + 12);
5e681ec4 15224
5e681ec4 15225#ifdef FOUR_WORD_PLT
00a97672
RS		 15226 /* The displacement value goes in the otherwise-unused
15227 last word of the second entry. */
15228 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 15229#else
00a97672 15230 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 15231#endif
00a97672 15232 }
f7a74f8c 15233 }
252b5132
RH		 15234
15235 /* UnixWare sets the entsize of .plt to 4, although that doesn't
15236 really seem like the right value. */
74541ad4
AM		 15237 if (splt->output_section->owner == output_bfd)
15238 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 15239
0855e32b
NS		 15240 if (htab->dt_tlsdesc_plt)
15241 {
15242 bfd_vma got_address
15243 = sgot->output_section->vma + sgot->output_offset;
15244 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
15245 + htab->root.sgot->output_offset);
15246 bfd_vma plt_address
15247 = splt->output_section->vma + splt->output_offset;
15248
b38cadfb 15249 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 15250 splt->contents + htab->dt_tlsdesc_plt,
15251 dl_tlsdesc_lazy_trampoline, 6);
15252
15253 bfd_put_32 (output_bfd,
15254 gotplt_address + htab->dt_tlsdesc_got
15255 - (plt_address + htab->dt_tlsdesc_plt)
15256 - dl_tlsdesc_lazy_trampoline[6],
15257 splt->contents + htab->dt_tlsdesc_plt + 24);
15258 bfd_put_32 (output_bfd,
15259 got_address - (plt_address + htab->dt_tlsdesc_plt)
15260 - dl_tlsdesc_lazy_trampoline[7],
15261 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
15262 }
15263
15264 if (htab->tls_trampoline)
15265 {
b38cadfb 15266 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 15267 splt->contents + htab->tls_trampoline,
15268 tls_trampoline, 3);
15269#ifdef FOUR_WORD_PLT
15270 bfd_put_32 (output_bfd, 0x00000000,
15271 splt->contents + htab->tls_trampoline + 12);
b38cadfb 15272#endif
0855e32b
NS		 15273 }
15274
0e1862bb
L		 15275 if (htab->vxworks_p
15276 && !bfd_link_pic (info)
15277 && htab->root.splt->size > 0)
00a97672
RS		 15278 {
15279 /* Correct the .rel(a).plt.unloaded relocations. They will have
15280 incorrect symbol indexes. */
15281 int num_plts;
eed62c48 15282 unsigned char *p;
00a97672 15283
362d30a1 15284 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 15285 / htab->plt_entry_size);
15286 p = htab->srelplt2->contents + RELOC_SIZE (htab);
15287
15288 for (; num_plts; num_plts--)
15289 {
15290 Elf_Internal_Rela rel;
15291
15292 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
15293 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
15294 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
15295 p += RELOC_SIZE (htab);
15296
15297 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
15298 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
15299 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
15300 p += RELOC_SIZE (htab);
15301 }
15302 }
252b5132
RH		 15303 }
15304
99059e56
RM		 15305 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
15306 /* NaCl uses a special first entry in .iplt too. */
15307 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
15308
252b5132 15309 /* Fill in the first three entries in the global offset table. */
229fcec5 15310 if (sgot)
252b5132 15311 {
229fcec5
MM		 15312 if (sgot->size > 0)
15313 {
15314 if (sdyn == NULL)
15315 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
15316 else
15317 bfd_put_32 (output_bfd,
15318 sdyn->output_section->vma + sdyn->output_offset,
15319 sgot->contents);
15320 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
15321 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
15322 }
252b5132 15323
229fcec5
MM		 15324 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
15325 }
252b5132 15326
b34976b6 15327 return TRUE;
252b5132
RH		 15328}
15329
ba96a88f 15330static void
57e8b36a 15331elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 15332{
9b485d32 15333 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 15334 struct elf32_arm_link_hash_table *globals;
ba96a88f
NC		 15335
15336 i_ehdrp = elf_elfheader (abfd);
15337
94a3258f
PB		 15338 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
15339 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
15340 else
7394f108 15341 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 15342 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 15343
93204d3a
PB		 15344 if (link_info)
15345 {
15346 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 15347 if (globals != NULL && globals->byteswap_code)
93204d3a
PB		 15348 i_ehdrp->e_flags |= EF_ARM_BE8;
15349 }
3bfcb652
NC		 15350
15351 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
15352 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
15353 {
15354 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 15355 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 15356 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
15357 else
15358 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
15359 }
ba96a88f
NC		 15360}
15361
99e4ae17 15362static enum elf_reloc_type_class
7e612e98
AM		 15363elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
15364 const asection *rel_sec ATTRIBUTE_UNUSED,
15365 const Elf_Internal_Rela *rela)
99e4ae17 15366{
f51e552e 15367 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 15368 {
15369 case R_ARM_RELATIVE:
15370 return reloc_class_relative;
15371 case R_ARM_JUMP_SLOT:
15372 return reloc_class_plt;
15373 case R_ARM_COPY:
15374 return reloc_class_copy;
15375 default:
15376 return reloc_class_normal;
15377 }
15378}
15379
e489d0ae 15380static void
57e8b36a 15381elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 15382{
5a6c6817 15383 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 15384}
15385
40a18ebd
NC		 15386/* Return TRUE if this is an unwinding table entry. */
15387
15388static bfd_boolean
15389is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
15390{
0112cd26
NC		 15391 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
15392 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 15393}
15394
15395
15396/* Set the type and flags for an ARM section. We do this by
15397 the section name, which is a hack, but ought to work. */
15398
15399static bfd_boolean
15400elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
15401{
15402 const char * name;
15403
15404 name = bfd_get_section_name (abfd, sec);
15405
15406 if (is_arm_elf_unwind_section_name (abfd, name))
15407 {
15408 hdr->sh_type = SHT_ARM_EXIDX;
15409 hdr->sh_flags |= SHF_LINK_ORDER;
15410 }
15411 return TRUE;
15412}
15413
6dc132d9
L		 15414/* Handle an ARM specific section when reading an object file. This is
15415 called when bfd_section_from_shdr finds a section with an unknown
15416 type. */
40a18ebd
NC		 15417
15418static bfd_boolean
15419elf32_arm_section_from_shdr (bfd *abfd,
15420 Elf_Internal_Shdr * hdr,
6dc132d9
L		 15421 const char *name,
15422 int shindex)
40a18ebd
NC		 15423{
15424 /* There ought to be a place to keep ELF backend specific flags, but
15425 at the moment there isn't one. We just keep track of the
15426 sections by their name, instead. Fortunately, the ABI gives
15427 names for all the ARM specific sections, so we will probably get
15428 away with this. */
15429 switch (hdr->sh_type)
15430 {
15431 case SHT_ARM_EXIDX:
0951f019
RE		 15432 case SHT_ARM_PREEMPTMAP:
15433 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 15434 break;
15435
15436 default:
15437 return FALSE;
15438 }
15439
6dc132d9 15440 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 15441 return FALSE;
15442
15443 return TRUE;
15444}
e489d0ae 15445
44444f50
NC		 15446static _arm_elf_section_data *
15447get_arm_elf_section_data (asection * sec)
15448{
47b2e99c
JZ		 15449 if (sec && sec->owner && is_arm_elf (sec->owner))
15450 return elf32_arm_section_data (sec);
44444f50
NC		 15451 else
15452 return NULL;
8e3de13a
NC		 15453}
15454
4e617b1e
PB		 15455typedef struct
15456{
57402f1e 15457 void *flaginfo;
4e617b1e 15458 struct bfd_link_info *info;
91a5743d
PB		 15459 asection *sec;
15460 int sec_shndx;
6e0b88f1
AM		 15461 int (*func) (void *, const char *, Elf_Internal_Sym *,
15462 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 15463} output_arch_syminfo;
15464
15465enum map_symbol_type
15466{
15467 ARM_MAP_ARM,
15468 ARM_MAP_THUMB,
15469 ARM_MAP_DATA
15470};
15471
15472
7413f23f 15473/* Output a single mapping symbol. */
4e617b1e
PB		 15474
15475static bfd_boolean
7413f23f
DJ		 15476elf32_arm_output_map_sym (output_arch_syminfo *osi,
15477 enum map_symbol_type type,
15478 bfd_vma offset)
4e617b1e
PB		 15479{
15480 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 15481 Elf_Internal_Sym sym;
15482
91a5743d
PB		 15483 sym.st_value = osi->sec->output_section->vma
15484 + osi->sec->output_offset
15485 + offset;
4e617b1e
PB		 15486 sym.st_size = 0;
15487 sym.st_other = 0;
15488 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 15489 sym.st_shndx = osi->sec_shndx;
35fc36a8 15490 sym.st_target_internal = 0;
fe33d2fa 15491 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 15492 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 15493}
15494
34e77a92
RS		 15495/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
15496 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 15497
15498static bfd_boolean
34e77a92
RS		 15499elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
15500 bfd_boolean is_iplt_entry_p,
15501 union gotplt_union *root_plt,
15502 struct arm_plt_info *arm_plt)
4e617b1e 15503{
4e617b1e 15504 struct elf32_arm_link_hash_table *htab;
34e77a92 15505 bfd_vma addr, plt_header_size;
4e617b1e 15506
34e77a92 15507 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 15508 return TRUE;
15509
4dfe6ac6
NC		 15510 htab = elf32_arm_hash_table (osi->info);
15511 if (htab == NULL)
15512 return FALSE;
15513
34e77a92
RS		 15514 if (is_iplt_entry_p)
15515 {
15516 osi->sec = htab->root.iplt;
15517 plt_header_size = 0;
15518 }
15519 else
15520 {
15521 osi->sec = htab->root.splt;
15522 plt_header_size = htab->plt_header_size;
15523 }
15524 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
15525 (osi->info->output_bfd, osi->sec->output_section));
15526
15527 addr = root_plt->offset & -2;
4e617b1e
PB		 15528 if (htab->symbian_p)
15529 {
7413f23f 15530 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15531 return FALSE;
7413f23f 15532 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 15533 return FALSE;
15534 }
15535 else if (htab->vxworks_p)
15536 {
7413f23f 15537 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15538 return FALSE;
7413f23f 15539 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 15540 return FALSE;
7413f23f 15541 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 15542 return FALSE;
7413f23f 15543 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 15544 return FALSE;
15545 }
b38cadfb
NC		 15546 else if (htab->nacl_p)
15547 {
15548 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
15549 return FALSE;
15550 }
eed94f8f
NC		 15551 else if (using_thumb_only (htab))
15552 {
15553 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
15554 return FALSE;
6a631e86 15555 }
4e617b1e
PB		 15556 else
15557 {
34e77a92 15558 bfd_boolean thumb_stub_p;
bd97cb95 15559
34e77a92
RS		 15560 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
15561 if (thumb_stub_p)
4e617b1e 15562 {
7413f23f 15563 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 15564 return FALSE;
15565 }
15566#ifdef FOUR_WORD_PLT
7413f23f 15567 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15568 return FALSE;
7413f23f 15569 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 15570 return FALSE;
15571#else
906e58ca 15572 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 15573 so only need to output a mapping symbol for the first PLT entry and
15574 entries with thumb thunks. */
34e77a92 15575 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 15576 {
7413f23f 15577 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 15578 return FALSE;
15579 }
15580#endif
15581 }
15582
15583 return TRUE;
15584}
15585
34e77a92
RS		 15586/* Output mapping symbols for PLT entries associated with H. */
15587
15588static bfd_boolean
15589elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
15590{
15591 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
15592 struct elf32_arm_link_hash_entry *eh;
15593
15594 if (h->root.type == bfd_link_hash_indirect)
15595 return TRUE;
15596
15597 if (h->root.type == bfd_link_hash_warning)
15598 /* When warning symbols are created, they **replace** the "real"
15599 entry in the hash table, thus we never get to see the real
15600 symbol in a hash traversal. So look at it now. */
15601 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15602
15603 eh = (struct elf32_arm_link_hash_entry *) h;
15604 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
15605 &h->plt, &eh->plt);
15606}
15607
7413f23f
DJ		 15608/* Output a single local symbol for a generated stub. */
15609
15610static bfd_boolean
15611elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
15612 bfd_vma offset, bfd_vma size)
15613{
7413f23f
DJ		 15614 Elf_Internal_Sym sym;
15615
7413f23f
DJ		 15616 sym.st_value = osi->sec->output_section->vma
15617 + osi->sec->output_offset
15618 + offset;
15619 sym.st_size = size;
15620 sym.st_other = 0;
15621 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
15622 sym.st_shndx = osi->sec_shndx;
35fc36a8 15623 sym.st_target_internal = 0;
57402f1e 15624 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 15625}
4e617b1e 15626
da5938a2 15627static bfd_boolean
8029a119
NC		 15628arm_map_one_stub (struct bfd_hash_entry * gen_entry,
15629 void * in_arg)
da5938a2
NC		 15630{
15631 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 15632 asection *stub_sec;
15633 bfd_vma addr;
7413f23f 15634 char *stub_name;
9a008db3 15635 output_arch_syminfo *osi;
d3ce72d0 15636 const insn_sequence *template_sequence;
461a49ca
DJ		 15637 enum stub_insn_type prev_type;
15638 int size;
15639 int i;
15640 enum map_symbol_type sym_type;
da5938a2
NC		 15641
15642 /* Massage our args to the form they really have. */
15643 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 15644 osi = (output_arch_syminfo *) in_arg;
da5938a2 15645
da5938a2
NC		 15646 stub_sec = stub_entry->stub_sec;
15647
15648 /* Ensure this stub is attached to the current section being
7413f23f 15649 processed. */
da5938a2
NC		 15650 if (stub_sec != osi->sec)
15651 return TRUE;
15652
7413f23f
DJ		 15653 addr = (bfd_vma) stub_entry->stub_offset;
15654 stub_name = stub_entry->output_name;
da5938a2 15655
d3ce72d0
NC		 15656 template_sequence = stub_entry->stub_template;
15657 switch (template_sequence[0].type)
7413f23f 15658 {
461a49ca
DJ		 15659 case ARM_TYPE:
15660 if (!elf32_arm_output_stub_sym (osi, stub_name, addr, stub_entry->stub_size))
da5938a2
NC		 15661 return FALSE;
15662 break;
461a49ca 15663 case THUMB16_TYPE:
48229727 15664 case THUMB32_TYPE:
461a49ca
DJ		 15665 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
15666 stub_entry->stub_size))
da5938a2
NC		 15667 return FALSE;
15668 break;
15669 default:
15670 BFD_FAIL ();
48229727 15671 return 0;
7413f23f 15672 }
da5938a2 15673
461a49ca
DJ		 15674 prev_type = DATA_TYPE;
15675 size = 0;
15676 for (i = 0; i < stub_entry->stub_template_size; i++)
15677 {
d3ce72d0 15678 switch (template_sequence[i].type)
461a49ca
DJ		 15679 {
15680 case ARM_TYPE:
15681 sym_type = ARM_MAP_ARM;
15682 break;
15683
15684 case THUMB16_TYPE:
48229727 15685 case THUMB32_TYPE:
461a49ca
DJ		 15686 sym_type = ARM_MAP_THUMB;
15687 break;
15688
15689 case DATA_TYPE:
15690 sym_type = ARM_MAP_DATA;
15691 break;
15692
15693 default:
15694 BFD_FAIL ();
4e31c731 15695 return FALSE;
461a49ca
DJ		 15696 }
15697
d3ce72d0 15698 if (template_sequence[i].type != prev_type)
461a49ca 15699 {
d3ce72d0 15700 prev_type = template_sequence[i].type;
461a49ca
DJ		 15701 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
15702 return FALSE;
15703 }
15704
d3ce72d0 15705 switch (template_sequence[i].type)
461a49ca
DJ		 15706 {
15707 case ARM_TYPE:
48229727 15708 case THUMB32_TYPE:
461a49ca
DJ		 15709 size += 4;
15710 break;
15711
15712 case THUMB16_TYPE:
15713 size += 2;
15714 break;
15715
15716 case DATA_TYPE:
15717 size += 4;
15718 break;
15719
15720 default:
15721 BFD_FAIL ();
4e31c731 15722 return FALSE;
461a49ca
DJ		 15723 }
15724 }
15725
da5938a2
NC		 15726 return TRUE;
15727}
15728
33811162
DG		 15729/* Output mapping symbols for linker generated sections,
15730 and for those data-only sections that do not have a
15731 $d. */
4e617b1e
PB		 15732
15733static bfd_boolean
15734elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 15735 struct bfd_link_info *info,
57402f1e 15736 void *flaginfo,
6e0b88f1
AM		 15737 int (*func) (void *, const char *,
15738 Elf_Internal_Sym *,
15739 asection *,
15740 struct elf_link_hash_entry *))
4e617b1e
PB		 15741{
15742 output_arch_syminfo osi;
15743 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 15744 bfd_vma offset;
15745 bfd_size_type size;
33811162 15746 bfd *input_bfd;
4e617b1e
PB		 15747
15748 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15749 if (htab == NULL)
15750 return FALSE;
15751
906e58ca 15752 check_use_blx (htab);
91a5743d 15753
57402f1e 15754 osi.flaginfo = flaginfo;
4e617b1e
PB		 15755 osi.info = info;
15756 osi.func = func;
906e58ca 15757
33811162
DG		 15758 /* Add a $d mapping symbol to data-only sections that
15759 don't have any mapping symbol. This may result in (harmless) redundant
15760 mapping symbols. */
15761 for (input_bfd = info->input_bfds;
15762 input_bfd != NULL;
c72f2fb2 15763 input_bfd = input_bfd->link.next)
33811162
DG		 15764 {
15765 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
15766 for (osi.sec = input_bfd->sections;
15767 osi.sec != NULL;
15768 osi.sec = osi.sec->next)
15769 {
15770 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 15771 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
15772 != 0)
33811162
DG		 15773 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
15774 == SEC_HAS_CONTENTS
15775 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 15776 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 15777 && osi.sec->size > 0
15778 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 15779 {
15780 osi.sec_shndx = _bfd_elf_section_from_bfd_section
15781 (output_bfd, osi.sec->output_section);
15782 if (osi.sec_shndx != (int)SHN_BAD)
15783 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
15784 }
15785 }
15786 }
15787
91a5743d
PB		 15788 /* ARM->Thumb glue. */
15789 if (htab->arm_glue_size > 0)
15790 {
3d4d4302
AM		 15791 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
15792 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 15793
15794 osi.sec_shndx = _bfd_elf_section_from_bfd_section
15795 (output_bfd, osi.sec->output_section);
0e1862bb 15796 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 15797 || htab->pic_veneer)
15798 size = ARM2THUMB_PIC_GLUE_SIZE;
15799 else if (htab->use_blx)
15800 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
15801 else
15802 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 15803
91a5743d
PB		 15804 for (offset = 0; offset < htab->arm_glue_size; offset += size)
15805 {
7413f23f
DJ		 15806 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
15807 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 15808 }
15809 }
15810
15811 /* Thumb->ARM glue. */
15812 if (htab->thumb_glue_size > 0)
15813 {
3d4d4302
AM		 15814 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
15815 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 15816
15817 osi.sec_shndx = _bfd_elf_section_from_bfd_section
15818 (output_bfd, osi.sec->output_section);
15819 size = THUMB2ARM_GLUE_SIZE;
15820
15821 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
15822 {
7413f23f
DJ		 15823 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
15824 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 15825 }
15826 }
15827
845b51d6
PB		 15828 /* ARMv4 BX veneers. */
15829 if (htab->bx_glue_size > 0)
15830 {
3d4d4302
AM		 15831 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
15832 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 15833
15834 osi.sec_shndx = _bfd_elf_section_from_bfd_section
15835 (output_bfd, osi.sec->output_section);
15836
7413f23f 15837 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 15838 }
15839
8029a119
NC		 15840 /* Long calls stubs. */
15841 if (htab->stub_bfd && htab->stub_bfd->sections)
15842 {
da5938a2 15843 asection* stub_sec;
8029a119 15844
da5938a2
NC		 15845 for (stub_sec = htab->stub_bfd->sections;
15846 stub_sec != NULL;
8029a119
NC		 15847 stub_sec = stub_sec->next)
15848 {
15849 /* Ignore non-stub sections. */
15850 if (!strstr (stub_sec->name, STUB_SUFFIX))
15851 continue;
da5938a2 15852
8029a119 15853 osi.sec = stub_sec;
da5938a2 15854
8029a119
NC		 15855 osi.sec_shndx = _bfd_elf_section_from_bfd_section
15856 (output_bfd, osi.sec->output_section);
da5938a2 15857
8029a119
NC		 15858 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
15859 }
15860 }
da5938a2 15861
91a5743d 15862 /* Finally, output mapping symbols for the PLT. */
34e77a92 15863 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 15864 {
34e77a92
RS		 15865 osi.sec = htab->root.splt;
15866 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
15867 (output_bfd, osi.sec->output_section));
15868
15869 /* Output mapping symbols for the plt header. SymbianOS does not have a
15870 plt header. */
15871 if (htab->vxworks_p)
15872 {
15873 /* VxWorks shared libraries have no PLT header. */
0e1862bb 15874 if (!bfd_link_pic (info))
34e77a92
RS		 15875 {
15876 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
15877 return FALSE;
15878 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
15879 return FALSE;
15880 }
15881 }
b38cadfb
NC		 15882 else if (htab->nacl_p)
15883 {
15884 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
15885 return FALSE;
15886 }
eed94f8f
NC		 15887 else if (using_thumb_only (htab))
15888 {
15889 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
15890 return FALSE;
15891 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
15892 return FALSE;
15893 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
15894 return FALSE;
15895 }
34e77a92 15896 else if (!htab->symbian_p)
4e617b1e 15897 {
7413f23f 15898 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 15899 return FALSE;
34e77a92
RS		 15900#ifndef FOUR_WORD_PLT
15901 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 15902 return FALSE;
34e77a92 15903#endif
4e617b1e
PB		 15904 }
15905 }
99059e56
RM		 15906 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
15907 {
15908 /* NaCl uses a special first entry in .iplt too. */
15909 osi.sec = htab->root.iplt;
15910 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
15911 (output_bfd, osi.sec->output_section));
15912 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
15913 return FALSE;
15914 }
34e77a92
RS		 15915 if ((htab->root.splt && htab->root.splt->size > 0)
15916 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 15917 {
34e77a92
RS		 15918 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
15919 for (input_bfd = info->input_bfds;
15920 input_bfd != NULL;
c72f2fb2 15921 input_bfd = input_bfd->link.next)
34e77a92
RS		 15922 {
15923 struct arm_local_iplt_info **local_iplt;
15924 unsigned int i, num_syms;
4e617b1e 15925
34e77a92
RS		 15926 local_iplt = elf32_arm_local_iplt (input_bfd);
15927 if (local_iplt != NULL)
15928 {
15929 num_syms = elf_symtab_hdr (input_bfd).sh_info;
15930 for (i = 0; i < num_syms; i++)
15931 if (local_iplt[i] != NULL
15932 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
15933 &local_iplt[i]->root,
15934 &local_iplt[i]->arm))
15935 return FALSE;
15936 }
15937 }
15938 }
0855e32b
NS		 15939 if (htab->dt_tlsdesc_plt != 0)
15940 {
15941 /* Mapping symbols for the lazy tls trampoline. */
15942 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
15943 return FALSE;
b38cadfb 15944
0855e32b
NS		 15945 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
15946 htab->dt_tlsdesc_plt + 24))
15947 return FALSE;
15948 }
15949 if (htab->tls_trampoline != 0)
15950 {
15951 /* Mapping symbols for the tls trampoline. */
15952 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
15953 return FALSE;
15954#ifdef FOUR_WORD_PLT
15955 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
15956 htab->tls_trampoline + 12))
15957 return FALSE;
b38cadfb 15958#endif
0855e32b 15959 }
b38cadfb 15960
4e617b1e
PB		 15961 return TRUE;
15962}
15963
e489d0ae
PB		 15964/* Allocate target specific section data. */
15965
15966static bfd_boolean
15967elf32_arm_new_section_hook (bfd *abfd, asection *sec)
15968{
f592407e
AM		 15969 if (!sec->used_by_bfd)
15970 {
15971 _arm_elf_section_data *sdata;
15972 bfd_size_type amt = sizeof (*sdata);
e489d0ae 15973
21d799b5 15974 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 15975 if (sdata == NULL)
15976 return FALSE;
15977 sec->used_by_bfd = sdata;
15978 }
e489d0ae
PB		 15979
15980 return _bfd_elf_new_section_hook (abfd, sec);
15981}
15982
15983
15984/* Used to order a list of mapping symbols by address. */
15985
15986static int
15987elf32_arm_compare_mapping (const void * a, const void * b)
15988{
7f6a71ff
JM		 15989 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
15990 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
15991
15992 if (amap->vma > bmap->vma)
15993 return 1;
15994 else if (amap->vma < bmap->vma)
15995 return -1;
15996 else if (amap->type > bmap->type)
15997 /* Ensure results do not depend on the host qsort for objects with
15998 multiple mapping symbols at the same address by sorting on type
15999 after vma. */
16000 return 1;
16001 else if (amap->type < bmap->type)
16002 return -1;
16003 else
16004 return 0;
e489d0ae
PB		 16005}
16006
2468f9c9
PB		 16007/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
16008
16009static unsigned long
16010offset_prel31 (unsigned long addr, bfd_vma offset)
16011{
16012 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
16013}
16014
16015/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
16016 relocations. */
16017
16018static void
16019copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
16020{
16021 unsigned long first_word = bfd_get_32 (output_bfd, from);
16022 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 16023
2468f9c9
PB		 16024 /* High bit of first word is supposed to be zero. */
16025 if ((first_word & 0x80000000ul) == 0)
16026 first_word = offset_prel31 (first_word, offset);
b38cadfb 16027
2468f9c9
PB		 16028 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
16029 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
16030 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
16031 second_word = offset_prel31 (second_word, offset);
b38cadfb 16032
2468f9c9
PB		 16033 bfd_put_32 (output_bfd, first_word, to);
16034 bfd_put_32 (output_bfd, second_word, to + 4);
16035}
e489d0ae 16036
48229727
JB		 16037/* Data for make_branch_to_a8_stub(). */
16038
b38cadfb
NC		 16039struct a8_branch_to_stub_data
16040{
48229727
JB		 16041 asection *writing_section;
16042 bfd_byte *contents;
16043};
16044
16045
16046/* Helper to insert branches to Cortex-A8 erratum stubs in the right
16047 places for a particular section. */
16048
16049static bfd_boolean
16050make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 16051 void *in_arg)
48229727
JB		 16052{
16053 struct elf32_arm_stub_hash_entry *stub_entry;
16054 struct a8_branch_to_stub_data *data;
16055 bfd_byte *contents;
16056 unsigned long branch_insn;
16057 bfd_vma veneered_insn_loc, veneer_entry_loc;
16058 bfd_signed_vma branch_offset;
16059 bfd *abfd;
91d6fa6a 16060 unsigned int target;
48229727
JB		 16061
16062 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
16063 data = (struct a8_branch_to_stub_data *) in_arg;
16064
16065 if (stub_entry->target_section != data->writing_section
4563a860 16066 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 16067 return TRUE;
16068
16069 contents = data->contents;
16070
16071 veneered_insn_loc = stub_entry->target_section->output_section->vma
16072 + stub_entry->target_section->output_offset
16073 + stub_entry->target_value;
16074
16075 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
16076 + stub_entry->stub_sec->output_offset
16077 + stub_entry->stub_offset;
16078
16079 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
16080 veneered_insn_loc &= ~3u;
16081
16082 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
16083
16084 abfd = stub_entry->target_section->owner;
91d6fa6a 16085 target = stub_entry->target_value;
48229727
JB		 16086
16087 /* We attempt to avoid this condition by setting stubs_always_after_branch
16088 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
16089 This check is just to be on the safe side... */
16090 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
16091 {
16092 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub is "
16093 "allocated in unsafe location"), abfd);
16094 return FALSE;
16095 }
16096
16097 switch (stub_entry->stub_type)
16098 {
16099 case arm_stub_a8_veneer_b:
16100 case arm_stub_a8_veneer_b_cond:
16101 branch_insn = 0xf0009000;
16102 goto jump24;
16103
16104 case arm_stub_a8_veneer_blx:
16105 branch_insn = 0xf000e800;
16106 goto jump24;
16107
16108 case arm_stub_a8_veneer_bl:
16109 {
16110 unsigned int i1, j1, i2, j2, s;
16111
16112 branch_insn = 0xf000d000;
16113
16114 jump24:
16115 if (branch_offset < -16777216 || branch_offset > 16777214)
16116 {
16117 /* There's not much we can do apart from complain if this
16118 happens. */
16119 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub out "
16120 "of range (input file too large)"), abfd);
16121 return FALSE;
16122 }
16123
16124 /* i1 = not(j1 eor s), so:
16125 not i1 = j1 eor s
16126 j1 = (not i1) eor s. */
16127
16128 branch_insn |= (branch_offset >> 1) & 0x7ff;
16129 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
16130 i2 = (branch_offset >> 22) & 1;
16131 i1 = (branch_offset >> 23) & 1;
16132 s = (branch_offset >> 24) & 1;
16133 j1 = (!i1) ^ s;
16134 j2 = (!i2) ^ s;
16135 branch_insn |= j2 << 11;
16136 branch_insn |= j1 << 13;
16137 branch_insn |= s << 26;
16138 }
16139 break;
16140
16141 default:
16142 BFD_FAIL ();
16143 return FALSE;
16144 }
16145
91d6fa6a
NC		 16146 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[target]);
16147 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[target + 2]);
48229727
JB		 16148
16149 return TRUE;
16150}
16151
a504d23a
LA		 16152/* Beginning of stm32l4xx work-around. */
16153
16154/* Functions encoding instructions necessary for the emission of the
16155 fix-stm32l4xx-629360.
16156 Encoding is extracted from the
16157 ARM (C) Architecture Reference Manual
16158 ARMv7-A and ARMv7-R edition
16159 ARM DDI 0406C.b (ID072512). */
16160
16161static inline bfd_vma
82188b29 16162create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 16163{
16164 /* A8.8.18 B (A8-334)
16165 B target_address (Encoding T4). */
16166 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
16167 /* jump offset is: S:I1:I2:imm10:imm11:0. */
16168 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
16169
a504d23a
LA		 16170 int s = ((branch_offset & 0x1000000) >> 24);
16171 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
16172 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
16173
16174 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
16175 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
16176
16177 bfd_vma patched_inst = 0xf0009000
16178 | s << 26 /* S. */
16179 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
16180 | j1 << 13 /* J1. */
16181 | j2 << 11 /* J2. */
16182 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
16183
16184 return patched_inst;
16185}
16186
16187static inline bfd_vma
16188create_instruction_ldmia (int base_reg, int wback, int reg_mask)
16189{
16190 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
16191 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
16192 bfd_vma patched_inst = 0xe8900000
16193 | (/*W=*/wback << 21)
16194 | (base_reg << 16)
16195 | (reg_mask & 0x0000ffff);
16196
16197 return patched_inst;
16198}
16199
16200static inline bfd_vma
16201create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
16202{
16203 /* A8.8.60 LDMDB/LDMEA (A8-402)
16204 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
16205 bfd_vma patched_inst = 0xe9100000
16206 | (/*W=*/wback << 21)
16207 | (base_reg << 16)
16208 | (reg_mask & 0x0000ffff);
16209
16210 return patched_inst;
16211}
16212
16213static inline bfd_vma
16214create_instruction_mov (int target_reg, int source_reg)
16215{
16216 /* A8.8.103 MOV (register) (A8-486)
16217 MOV Rd, Rm (Encoding T1). */
16218 bfd_vma patched_inst = 0x4600
16219 | (target_reg & 0x7)
16220 | ((target_reg & 0x8) >> 3) << 7
16221 | (source_reg << 3);
16222
16223 return patched_inst;
16224}
16225
16226static inline bfd_vma
16227create_instruction_sub (int target_reg, int source_reg, int value)
16228{
16229 /* A8.8.221 SUB (immediate) (A8-708)
16230 SUB Rd, Rn, #value (Encoding T3). */
16231 bfd_vma patched_inst = 0xf1a00000
16232 | (target_reg << 8)
16233 | (source_reg << 16)
16234 | (/*S=*/0 << 20)
16235 | ((value & 0x800) >> 11) << 26
16236 | ((value & 0x700) >> 8) << 12
16237 | (value & 0x0ff);
16238
16239 return patched_inst;
16240}
16241
16242static inline bfd_vma
16243create_instruction_vldmia (int base_reg, int wback, int num_regs,
16244 int first_reg)
16245{
16246 /* A8.8.332 VLDM (A8-922)
16247 VLMD{MODE} Rn{!}, {list} (Encoding T2). */
16248 bfd_vma patched_inst = 0xec900a00
16249 | (/*W=*/wback << 21)
16250 | (base_reg << 16)
16251 | (num_regs & 0x000000ff)
16252 | (((unsigned)first_reg>>1) & 0x0000000f) << 12
16253 | (first_reg & 0x00000001) << 22;
16254
16255 return patched_inst;
16256}
16257
16258static inline bfd_vma
16259create_instruction_vldmdb (int base_reg, int num_regs, int first_reg)
16260{
16261 /* A8.8.332 VLDM (A8-922)
16262 VLMD{MODE} Rn!, {} (Encoding T2). */
16263 bfd_vma patched_inst = 0xed300a00
16264 | (base_reg << 16)
16265 | (num_regs & 0x000000ff)
16266 | (((unsigned)first_reg>>1) & 0x0000000f) << 12
16267 | (first_reg & 0x00000001) << 22;
16268
16269 return patched_inst;
16270}
16271
16272static inline bfd_vma
16273create_instruction_udf_w (int value)
16274{
16275 /* A8.8.247 UDF (A8-758)
16276 Undefined (Encoding T2). */
16277 bfd_vma patched_inst = 0xf7f0a000
16278 | (value & 0x00000fff)
16279 | (value & 0x000f0000) << 16;
16280
16281 return patched_inst;
16282}
16283
16284static inline bfd_vma
16285create_instruction_udf (int value)
16286{
16287 /* A8.8.247 UDF (A8-758)
16288 Undefined (Encoding T1). */
16289 bfd_vma patched_inst = 0xde00
16290 | (value & 0xff);
16291
16292 return patched_inst;
16293}
16294
16295/* Functions writing an instruction in memory, returning the next
16296 memory position to write to. */
16297
16298static inline bfd_byte *
16299push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
16300 bfd * output_bfd, bfd_byte *pt, insn32 insn)
16301{
16302 put_thumb2_insn (htab, output_bfd, insn, pt);
16303 return pt + 4;
16304}
16305
16306static inline bfd_byte *
16307push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
16308 bfd * output_bfd, bfd_byte *pt, insn32 insn)
16309{
16310 put_thumb_insn (htab, output_bfd, insn, pt);
16311 return pt + 2;
16312}
16313
16314/* Function filling up a region in memory with T1 and T2 UDFs taking
16315 care of alignment. */
16316
16317static bfd_byte *
16318stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
16319 bfd * output_bfd,
16320 const bfd_byte * const base_stub_contents,
16321 bfd_byte * const from_stub_contents,
16322 const bfd_byte * const end_stub_contents)
16323{
16324 bfd_byte *current_stub_contents = from_stub_contents;
16325
16326 /* Fill the remaining of the stub with deterministic contents : UDF
16327 instructions.
16328 Check if realignment is needed on modulo 4 frontier using T1, to
16329 further use T2. */
16330 if ((current_stub_contents < end_stub_contents)
16331 && !((current_stub_contents - base_stub_contents) % 2)
16332 && ((current_stub_contents - base_stub_contents) % 4))
16333 current_stub_contents =
16334 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16335 create_instruction_udf (0));
16336
16337 for (; current_stub_contents < end_stub_contents;)
16338 current_stub_contents =
16339 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16340 create_instruction_udf_w (0));
16341
16342 return current_stub_contents;
16343}
16344
16345/* Functions writing the stream of instructions equivalent to the
16346 derived sequence for ldmia, ldmdb, vldm respectively. */
16347
16348static void
16349stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
16350 bfd * output_bfd,
16351 const insn32 initial_insn,
16352 const bfd_byte *const initial_insn_addr,
16353 bfd_byte *const base_stub_contents)
16354{
16355 int wback = (initial_insn & 0x00200000) >> 21;
16356 int ri, rn = (initial_insn & 0x000F0000) >> 16;
16357 int insn_all_registers = initial_insn & 0x0000ffff;
16358 int insn_low_registers, insn_high_registers;
16359 int usable_register_mask;
16360 int nb_registers = popcount (insn_all_registers);
16361 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
16362 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
16363 bfd_byte *current_stub_contents = base_stub_contents;
16364
16365 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
16366
16367 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16368 smaller than 8 registers load sequences that do not cause the
16369 hardware issue. */
16370 if (nb_registers <= 8)
16371 {
16372 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
16373 current_stub_contents =
16374 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16375 initial_insn);
16376
16377 /* B initial_insn_addr+4. */
16378 if (!restore_pc)
16379 current_stub_contents =
16380 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16381 create_instruction_branch_absolute
82188b29
NC		 16382 (initial_insn_addr - current_stub_contents));
16383
a504d23a
LA		 16384
16385 /* Fill the remaining of the stub with deterministic contents. */
16386 current_stub_contents =
16387 stm32l4xx_fill_stub_udf (htab, output_bfd,
16388 base_stub_contents, current_stub_contents,
16389 base_stub_contents +
16390 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16391
16392 return;
16393 }
16394
16395 /* - reg_list[13] == 0. */
16396 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
16397
16398 /* - reg_list[14] & reg_list[15] != 1. */
16399 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
16400
16401 /* - if (wback==1) reg_list[rn] == 0. */
16402 BFD_ASSERT (!wback || !restore_rn);
16403
16404 /* - nb_registers > 8. */
16405 BFD_ASSERT (popcount (insn_all_registers) > 8);
16406
16407 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
16408
16409 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
16410 - One with the 7 lowest registers (register mask 0x007F)
16411 This LDM will finally contain between 2 and 7 registers
16412 - One with the 7 highest registers (register mask 0xDF80)
16413 This ldm will finally contain between 2 and 7 registers. */
16414 insn_low_registers = insn_all_registers & 0x007F;
16415 insn_high_registers = insn_all_registers & 0xDF80;
16416
16417 /* A spare register may be needed during this veneer to temporarily
16418 handle the base register. This register will be restored with the
16419 last LDM operation.
16420 The usable register may be any general purpose register (that
16421 excludes PC, SP, LR : register mask is 0x1FFF). */
16422 usable_register_mask = 0x1FFF;
16423
16424 /* Generate the stub function. */
16425 if (wback)
16426 {
16427 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
16428 current_stub_contents =
16429 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16430 create_instruction_ldmia
16431 (rn, /*wback=*/1, insn_low_registers));
16432
16433 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
16434 current_stub_contents =
16435 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16436 create_instruction_ldmia
16437 (rn, /*wback=*/1, insn_high_registers));
16438 if (!restore_pc)
16439 {
16440 /* B initial_insn_addr+4. */
16441 current_stub_contents =
16442 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16443 create_instruction_branch_absolute
82188b29 16444 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16445 }
16446 }
16447 else /* if (!wback). */
16448 {
16449 ri = rn;
16450
16451 /* If Rn is not part of the high-register-list, move it there. */
16452 if (!(insn_high_registers & (1 << rn)))
16453 {
16454 /* Choose a Ri in the high-register-list that will be restored. */
16455 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16456
16457 /* MOV Ri, Rn. */
16458 current_stub_contents =
16459 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16460 create_instruction_mov (ri, rn));
16461 }
16462
16463 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
16464 current_stub_contents =
16465 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16466 create_instruction_ldmia
16467 (ri, /*wback=*/1, insn_low_registers));
16468
16469 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
16470 current_stub_contents =
16471 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16472 create_instruction_ldmia
16473 (ri, /*wback=*/0, insn_high_registers));
16474
16475 if (!restore_pc)
16476 {
16477 /* B initial_insn_addr+4. */
16478 current_stub_contents =
16479 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16480 create_instruction_branch_absolute
82188b29 16481 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16482 }
16483 }
16484
16485 /* Fill the remaining of the stub with deterministic contents. */
16486 current_stub_contents =
16487 stm32l4xx_fill_stub_udf (htab, output_bfd,
16488 base_stub_contents, current_stub_contents,
16489 base_stub_contents +
16490 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16491}
16492
16493static void
16494stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
16495 bfd * output_bfd,
16496 const insn32 initial_insn,
16497 const bfd_byte *const initial_insn_addr,
16498 bfd_byte *const base_stub_contents)
16499{
16500 int wback = (initial_insn & 0x00200000) >> 21;
16501 int ri, rn = (initial_insn & 0x000f0000) >> 16;
16502 int insn_all_registers = initial_insn & 0x0000ffff;
16503 int insn_low_registers, insn_high_registers;
16504 int usable_register_mask;
16505 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
16506 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
16507 int nb_registers = popcount (insn_all_registers);
16508 bfd_byte *current_stub_contents = base_stub_contents;
16509
16510 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
16511
16512 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16513 smaller than 8 registers load sequences that do not cause the
16514 hardware issue. */
16515 if (nb_registers <= 8)
16516 {
16517 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
16518 current_stub_contents =
16519 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16520 initial_insn);
16521
16522 /* B initial_insn_addr+4. */
16523 current_stub_contents =
16524 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16525 create_instruction_branch_absolute
82188b29 16526 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16527
16528 /* Fill the remaining of the stub with deterministic contents. */
16529 current_stub_contents =
16530 stm32l4xx_fill_stub_udf (htab, output_bfd,
16531 base_stub_contents, current_stub_contents,
16532 base_stub_contents +
16533 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16534
16535 return;
16536 }
16537
16538 /* - reg_list[13] == 0. */
16539 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
16540
16541 /* - reg_list[14] & reg_list[15] != 1. */
16542 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
16543
16544 /* - if (wback==1) reg_list[rn] == 0. */
16545 BFD_ASSERT (!wback || !restore_rn);
16546
16547 /* - nb_registers > 8. */
16548 BFD_ASSERT (popcount (insn_all_registers) > 8);
16549
16550 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
16551
16552 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
16553 - One with the 7 lowest registers (register mask 0x007F)
16554 This LDM will finally contain between 2 and 7 registers
16555 - One with the 7 highest registers (register mask 0xDF80)
16556 This ldm will finally contain between 2 and 7 registers. */
16557 insn_low_registers = insn_all_registers & 0x007F;
16558 insn_high_registers = insn_all_registers & 0xDF80;
16559
16560 /* A spare register may be needed during this veneer to temporarily
16561 handle the base register. This register will be restored with
16562 the last LDM operation.
16563 The usable register may be any general purpose register (that excludes
16564 PC, SP, LR : register mask is 0x1FFF). */
16565 usable_register_mask = 0x1FFF;
16566
16567 /* Generate the stub function. */
16568 if (!wback && !restore_pc && !restore_rn)
16569 {
16570 /* Choose a Ri in the low-register-list that will be restored. */
16571 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
16572
16573 /* MOV Ri, Rn. */
16574 current_stub_contents =
16575 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16576 create_instruction_mov (ri, rn));
16577
16578 /* LDMDB Ri!, {R-high-register-list}. */
16579 current_stub_contents =
16580 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16581 create_instruction_ldmdb
16582 (ri, /*wback=*/1, insn_high_registers));
16583
16584 /* LDMDB Ri, {R-low-register-list}. */
16585 current_stub_contents =
16586 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16587 create_instruction_ldmdb
16588 (ri, /*wback=*/0, insn_low_registers));
16589
16590 /* B initial_insn_addr+4. */
16591 current_stub_contents =
16592 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16593 create_instruction_branch_absolute
82188b29 16594 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16595 }
16596 else if (wback && !restore_pc && !restore_rn)
16597 {
16598 /* LDMDB Rn!, {R-high-register-list}. */
16599 current_stub_contents =
16600 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16601 create_instruction_ldmdb
16602 (rn, /*wback=*/1, insn_high_registers));
16603
16604 /* LDMDB Rn!, {R-low-register-list}. */
16605 current_stub_contents =
16606 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16607 create_instruction_ldmdb
16608 (rn, /*wback=*/1, insn_low_registers));
16609
16610 /* B initial_insn_addr+4. */
16611 current_stub_contents =
16612 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16613 create_instruction_branch_absolute
82188b29 16614 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16615 }
16616 else if (!wback && restore_pc && !restore_rn)
16617 {
16618 /* Choose a Ri in the high-register-list that will be restored. */
16619 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16620
16621 /* SUB Ri, Rn, #(4*nb_registers). */
16622 current_stub_contents =
16623 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16624 create_instruction_sub (ri, rn, (4 * nb_registers)));
16625
16626 /* LDMIA Ri!, {R-low-register-list}. */
16627 current_stub_contents =
16628 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16629 create_instruction_ldmia
16630 (ri, /*wback=*/1, insn_low_registers));
16631
16632 /* LDMIA Ri, {R-high-register-list}. */
16633 current_stub_contents =
16634 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16635 create_instruction_ldmia
16636 (ri, /*wback=*/0, insn_high_registers));
16637 }
16638 else if (wback && restore_pc && !restore_rn)
16639 {
16640 /* Choose a Ri in the high-register-list that will be restored. */
16641 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16642
16643 /* SUB Rn, Rn, #(4*nb_registers) */
16644 current_stub_contents =
16645 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16646 create_instruction_sub (rn, rn, (4 * nb_registers)));
16647
16648 /* MOV Ri, Rn. */
16649 current_stub_contents =
16650 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16651 create_instruction_mov (ri, rn));
16652
16653 /* LDMIA Ri!, {R-low-register-list}. */
16654 current_stub_contents =
16655 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16656 create_instruction_ldmia
16657 (ri, /*wback=*/1, insn_low_registers));
16658
16659 /* LDMIA Ri, {R-high-register-list}. */
16660 current_stub_contents =
16661 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16662 create_instruction_ldmia
16663 (ri, /*wback=*/0, insn_high_registers));
16664 }
16665 else if (!wback && !restore_pc && restore_rn)
16666 {
16667 ri = rn;
16668 if (!(insn_low_registers & (1 << rn)))
16669 {
16670 /* Choose a Ri in the low-register-list that will be restored. */
16671 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
16672
16673 /* MOV Ri, Rn. */
16674 current_stub_contents =
16675 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16676 create_instruction_mov (ri, rn));
16677 }
16678
16679 /* LDMDB Ri!, {R-high-register-list}. */
16680 current_stub_contents =
16681 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16682 create_instruction_ldmdb
16683 (ri, /*wback=*/1, insn_high_registers));
16684
16685 /* LDMDB Ri, {R-low-register-list}. */
16686 current_stub_contents =
16687 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16688 create_instruction_ldmdb
16689 (ri, /*wback=*/0, insn_low_registers));
16690
16691 /* B initial_insn_addr+4. */
16692 current_stub_contents =
16693 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16694 create_instruction_branch_absolute
82188b29 16695 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16696 }
16697 else if (!wback && restore_pc && restore_rn)
16698 {
16699 ri = rn;
16700 if (!(insn_high_registers & (1 << rn)))
16701 {
16702 /* Choose a Ri in the high-register-list that will be restored. */
16703 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16704 }
16705
16706 /* SUB Ri, Rn, #(4*nb_registers). */
16707 current_stub_contents =
16708 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16709 create_instruction_sub (ri, rn, (4 * nb_registers)));
16710
16711 /* LDMIA Ri!, {R-low-register-list}. */
16712 current_stub_contents =
16713 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16714 create_instruction_ldmia
16715 (ri, /*wback=*/1, insn_low_registers));
16716
16717 /* LDMIA Ri, {R-high-register-list}. */
16718 current_stub_contents =
16719 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16720 create_instruction_ldmia
16721 (ri, /*wback=*/0, insn_high_registers));
16722 }
16723 else if (wback && restore_rn)
16724 {
16725 /* The assembler should not have accepted to encode this. */
16726 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
16727 "undefined behavior.\n");
16728 }
16729
16730 /* Fill the remaining of the stub with deterministic contents. */
16731 current_stub_contents =
16732 stm32l4xx_fill_stub_udf (htab, output_bfd,
16733 base_stub_contents, current_stub_contents,
16734 base_stub_contents +
16735 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16736
16737}
16738
16739static void
16740stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
16741 bfd * output_bfd,
16742 const insn32 initial_insn,
16743 const bfd_byte *const initial_insn_addr,
16744 bfd_byte *const base_stub_contents)
16745{
16746 int num_regs = ((unsigned int)initial_insn << 24) >> 24;
16747 bfd_byte *current_stub_contents = base_stub_contents;
16748
16749 BFD_ASSERT (is_thumb2_vldm (initial_insn));
16750
16751 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16752 smaller than 8 registers load sequences that do not cause the
16753 hardware issue. */
16754 if (num_regs <= 8)
16755 {
16756 /* Untouched instruction. */
16757 current_stub_contents =
16758 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16759 initial_insn);
16760
16761 /* B initial_insn_addr+4. */
16762 current_stub_contents =
16763 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16764 create_instruction_branch_absolute
82188b29 16765 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16766 }
16767 else
16768 {
16769 bfd_boolean is_ia_nobang = /* (IA without !). */
16770 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
16771 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
16772 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
16773 bfd_boolean is_db_bang = /* (DB with !). */
16774 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
16775 int base_reg = ((unsigned int)initial_insn << 12) >> 28;
16776 /* d = UInt (Vd:D);. */
16777 int first_reg = ((((unsigned int)initial_insn << 16) >> 28) << 1)
16778 | (((unsigned int)initial_insn << 9) >> 31);
16779
16780 /* Compute the number of 8-register chunks needed to split. */
16781 int chunks = (num_regs%8) ? (num_regs/8 + 1) : (num_regs/8);
16782 int chunk;
16783
16784 /* The test coverage has been done assuming the following
16785 hypothesis that exactly one of the previous is_ predicates is
16786 true. */
16787 BFD_ASSERT ((is_ia_nobang ^ is_ia_bang ^ is_db_bang) &&
16788 !(is_ia_nobang & is_ia_bang & is_db_bang));
16789
16790 /* We treat the cutting of the register in one pass for all
16791 cases, then we emit the adjustments:
16792
16793 vldm rx, {...}
16794 -> vldm rx!, {8_words_or_less} for each needed 8_word
16795 -> sub rx, rx, #size (list)
16796
16797 vldm rx!, {...}
16798 -> vldm rx!, {8_words_or_less} for each needed 8_word
16799 This also handles vpop instruction (when rx is sp)
16800
16801 vldmd rx!, {...}
16802 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
16803 for (chunk = 0; chunk<chunks; ++chunk)
16804 {
16805 if (is_ia_nobang || is_ia_bang)
16806 {
16807 current_stub_contents =
16808 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16809 create_instruction_vldmia
16810 (base_reg,
16811 /*wback= . */1,
16812 chunks - (chunk + 1) ?
16813 8 : num_regs - chunk * 8,
16814 first_reg + chunk * 8));
16815 }
16816 else if (is_db_bang)
16817 {
16818 current_stub_contents =
16819 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16820 create_instruction_vldmdb
16821 (base_reg,
16822 chunks - (chunk + 1) ?
16823 8 : num_regs - chunk * 8,
16824 first_reg + chunk * 8));
16825 }
16826 }
16827
16828 /* Only this case requires the base register compensation
16829 subtract. */
16830 if (is_ia_nobang)
16831 {
16832 current_stub_contents =
16833 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16834 create_instruction_sub
16835 (base_reg, base_reg, 4*num_regs));
16836 }
16837
16838 /* B initial_insn_addr+4. */
16839 current_stub_contents =
16840 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16841 create_instruction_branch_absolute
82188b29 16842 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16843 }
16844
16845 /* Fill the remaining of the stub with deterministic contents. */
16846 current_stub_contents =
16847 stm32l4xx_fill_stub_udf (htab, output_bfd,
16848 base_stub_contents, current_stub_contents,
16849 base_stub_contents +
16850 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
16851}
16852
16853static void
16854stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
16855 bfd * output_bfd,
16856 const insn32 wrong_insn,
16857 const bfd_byte *const wrong_insn_addr,
16858 bfd_byte *const stub_contents)
16859{
16860 if (is_thumb2_ldmia (wrong_insn))
16861 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
16862 wrong_insn, wrong_insn_addr,
16863 stub_contents);
16864 else if (is_thumb2_ldmdb (wrong_insn))
16865 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
16866 wrong_insn, wrong_insn_addr,
16867 stub_contents);
16868 else if (is_thumb2_vldm (wrong_insn))
16869 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
16870 wrong_insn, wrong_insn_addr,
16871 stub_contents);
16872}
16873
16874/* End of stm32l4xx work-around. */
16875
16876
e489d0ae
PB		 16877/* Do code byteswapping. Return FALSE afterwards so that the section is
16878 written out as normal. */
16879
16880static bfd_boolean
c7b8f16e 16881elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 16882 struct bfd_link_info *link_info,
16883 asection *sec,
e489d0ae
PB		 16884 bfd_byte *contents)
16885{
48229727 16886 unsigned int mapcount, errcount;
8e3de13a 16887 _arm_elf_section_data *arm_data;
c7b8f16e 16888 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 16889 elf32_arm_section_map *map;
c7b8f16e 16890 elf32_vfp11_erratum_list *errnode;
a504d23a 16891 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 16892 bfd_vma ptr;
16893 bfd_vma end;
c7b8f16e 16894 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 16895 bfd_byte tmp;
48229727 16896 unsigned int i;
57e8b36a 16897
4dfe6ac6
NC		 16898 if (globals == NULL)
16899 return FALSE;
16900
8e3de13a
NC		 16901 /* If this section has not been allocated an _arm_elf_section_data
16902 structure then we cannot record anything. */
16903 arm_data = get_arm_elf_section_data (sec);
16904 if (arm_data == NULL)
16905 return FALSE;
16906
16907 mapcount = arm_data->mapcount;
16908 map = arm_data->map;
c7b8f16e
JB		 16909 errcount = arm_data->erratumcount;
16910
16911 if (errcount != 0)
16912 {
16913 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
16914
16915 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 16916 errnode = errnode->next)
16917 {
16918 bfd_vma target = errnode->vma - offset;
16919
16920 switch (errnode->type)
16921 {
16922 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
16923 {
16924 bfd_vma branch_to_veneer;
16925 /* Original condition code of instruction, plus bit mask for
16926 ARM B instruction. */
16927 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
16928 | 0x0a000000;
c7b8f16e
JB		 16929
16930 /* The instruction is before the label. */
91d6fa6a 16931 target -= 4;
c7b8f16e
JB		 16932
16933 /* Above offset included in -4 below. */
16934 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 16935 - errnode->vma - 4;
c7b8f16e
JB		 16936
16937 if ((signed) branch_to_veneer < -(1 << 25)
16938 || (signed) branch_to_veneer >= (1 << 25))
16939 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
16940 "range"), output_bfd);
16941
99059e56
RM		 16942 insn |= (branch_to_veneer >> 2) & 0xffffff;
16943 contents[endianflip ^ target] = insn & 0xff;
16944 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
16945 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
16946 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
16947 }
16948 break;
c7b8f16e
JB		 16949
16950 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 16951 {
16952 bfd_vma branch_from_veneer;
16953 unsigned int insn;
c7b8f16e 16954
99059e56
RM		 16955 /* Take size of veneer into account. */
16956 branch_from_veneer = errnode->u.v.branch->vma
16957 - errnode->vma - 12;
c7b8f16e
JB		 16958
16959 if ((signed) branch_from_veneer < -(1 << 25)
16960 || (signed) branch_from_veneer >= (1 << 25))
16961 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
16962 "range"), output_bfd);
16963
99059e56
RM		 16964 /* Original instruction. */
16965 insn = errnode->u.v.branch->u.b.vfp_insn;
16966 contents[endianflip ^ target] = insn & 0xff;
16967 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
16968 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
16969 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
16970
16971 /* Branch back to insn after original insn. */
16972 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
16973 contents[endianflip ^ (target + 4)] = insn & 0xff;
16974 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
16975 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
16976 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
16977 }
16978 break;
c7b8f16e 16979
99059e56
RM		 16980 default:
16981 abort ();
16982 }
16983 }
c7b8f16e 16984 }
e489d0ae 16985
a504d23a
LA		 16986 if (arm_data->stm32l4xx_erratumcount != 0)
16987 {
16988 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
16989 stm32l4xx_errnode != 0;
16990 stm32l4xx_errnode = stm32l4xx_errnode->next)
16991 {
16992 bfd_vma target = stm32l4xx_errnode->vma - offset;
16993
16994 switch (stm32l4xx_errnode->type)
16995 {
16996 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
16997 {
16998 unsigned int insn;
16999 bfd_vma branch_to_veneer =
17000 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
17001
17002 if ((signed) branch_to_veneer < -(1 << 24)
17003 || (signed) branch_to_veneer >= (1 << 24))
17004 {
17005 bfd_vma out_of_range =
17006 ((signed) branch_to_veneer < -(1 << 24)) ?
17007 - branch_to_veneer - (1 << 24) :
17008 ((signed) branch_to_veneer >= (1 << 24)) ?
17009 branch_to_veneer - (1 << 24) : 0;
17010
17011 (*_bfd_error_handler)
17012 (_("%B(%#x): error: Cannot create STM32L4XX veneer. "
eee926f2 17013 "Jump out of range by %ld bytes. "
a504d23a
LA		 17014 "Cannot encode branch instruction. "),
17015 output_bfd,
eee926f2 17016 (long) (stm32l4xx_errnode->vma - 4),
a504d23a
LA		 17017 out_of_range);
17018 continue;
17019 }
17020
17021 insn = create_instruction_branch_absolute
82188b29 17022 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 17023
17024 /* The instruction is before the label. */
17025 target -= 4;
17026
17027 put_thumb2_insn (globals, output_bfd,
17028 (bfd_vma) insn, contents + target);
17029 }
17030 break;
17031
17032 case STM32L4XX_ERRATUM_VENEER:
17033 {
82188b29
NC		 17034 bfd_byte * veneer;
17035 bfd_byte * veneer_r;
a504d23a
LA		 17036 unsigned int insn;
17037
82188b29
NC		 17038 veneer = contents + target;
17039 veneer_r = veneer
17040 + stm32l4xx_errnode->u.b.veneer->vma
17041 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 17042
17043 if ((signed) (veneer_r - veneer -
17044 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
17045 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
17046 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
17047 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
17048 || (signed) (veneer_r - veneer) >= (1 << 24))
17049 {
17050 (*_bfd_error_handler) (_("%B: error: Cannot create STM32L4XX "
17051 "veneer."), output_bfd);
17052 continue;
17053 }
17054
17055 /* Original instruction. */
17056 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
17057
17058 stm32l4xx_create_replacing_stub
17059 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
17060 }
17061 break;
17062
17063 default:
17064 abort ();
17065 }
17066 }
17067 }
17068
2468f9c9
PB		 17069 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
17070 {
17071 arm_unwind_table_edit *edit_node
99059e56 17072 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 17073 /* Now, sec->size is the size of the section we will write. The original
99059e56 17074 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 17075 markers) was sec->rawsize. (This isn't the case if we perform no
17076 edits, then rawsize will be zero and we should use size). */
21d799b5 17077 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 17078 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
17079 unsigned int in_index, out_index;
17080 bfd_vma add_to_offsets = 0;
17081
17082 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 17083 {
2468f9c9
PB		 17084 if (edit_node)
17085 {
17086 unsigned int edit_index = edit_node->index;
b38cadfb 17087
2468f9c9 17088 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 17089 {
2468f9c9
PB		 17090 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
17091 contents + in_index * 8, add_to_offsets);
17092 out_index++;
17093 in_index++;
17094 }
17095 else if (in_index == edit_index
17096 || (in_index * 8 >= input_size
17097 && edit_index == UINT_MAX))
99059e56 17098 {
2468f9c9
PB		 17099 switch (edit_node->type)
17100 {
17101 case DELETE_EXIDX_ENTRY:
17102 in_index++;
17103 add_to_offsets += 8;
17104 break;
b38cadfb 17105
2468f9c9
PB		 17106 case INSERT_EXIDX_CANTUNWIND_AT_END:
17107 {
99059e56 17108 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 17109 bfd_vma text_offset = text_sec->output_section->vma
17110 + text_sec->output_offset
17111 + text_sec->size;
17112 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 17113 unsigned long prel31_offset;
2468f9c9
PB		 17114
17115 /* Note: this is meant to be equivalent to an
17116 R_ARM_PREL31 relocation. These synthetic
17117 EXIDX_CANTUNWIND markers are not relocated by the
17118 usual BFD method. */
17119 prel31_offset = (text_offset - exidx_offset)
17120 & 0x7ffffffful;
17121
17122 /* First address we can't unwind. */
17123 bfd_put_32 (output_bfd, prel31_offset,
17124 &edited_contents[out_index * 8]);
17125
17126 /* Code for EXIDX_CANTUNWIND. */
17127 bfd_put_32 (output_bfd, 0x1,
17128 &edited_contents[out_index * 8 + 4]);
17129
17130 out_index++;
17131 add_to_offsets -= 8;
17132 }
17133 break;
17134 }
b38cadfb 17135
2468f9c9
PB		 17136 edit_node = edit_node->next;
17137 }
17138 }
17139 else
17140 {
17141 /* No more edits, copy remaining entries verbatim. */
17142 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
17143 contents + in_index * 8, add_to_offsets);
17144 out_index++;
17145 in_index++;
17146 }
17147 }
17148
17149 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
17150 bfd_set_section_contents (output_bfd, sec->output_section,
17151 edited_contents,
17152 (file_ptr) sec->output_offset, sec->size);
17153
17154 return TRUE;
17155 }
17156
48229727
JB		 17157 /* Fix code to point to Cortex-A8 erratum stubs. */
17158 if (globals->fix_cortex_a8)
17159 {
17160 struct a8_branch_to_stub_data data;
17161
17162 data.writing_section = sec;
17163 data.contents = contents;
17164
a504d23a
LA		 17165 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
17166 & data);
48229727
JB		 17167 }
17168
e489d0ae
PB		 17169 if (mapcount == 0)
17170 return FALSE;
17171
c7b8f16e 17172 if (globals->byteswap_code)
e489d0ae 17173 {
c7b8f16e 17174 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 17175
c7b8f16e
JB		 17176 ptr = map[0].vma;
17177 for (i = 0; i < mapcount; i++)
99059e56
RM		 17178 {
17179 if (i == mapcount - 1)
c7b8f16e 17180 end = sec->size;
99059e56
RM		 17181 else
17182 end = map[i + 1].vma;
e489d0ae 17183
99059e56 17184 switch (map[i].type)
e489d0ae 17185 {
c7b8f16e
JB		 17186 case 'a':
17187 /* Byte swap code words. */
17188 while (ptr + 3 < end)
99059e56
RM		 17189 {
17190 tmp = contents[ptr];
17191 contents[ptr] = contents[ptr + 3];
17192 contents[ptr + 3] = tmp;
17193 tmp = contents[ptr + 1];
17194 contents[ptr + 1] = contents[ptr + 2];
17195 contents[ptr + 2] = tmp;
17196 ptr += 4;
17197 }
c7b8f16e 17198 break;
e489d0ae 17199
c7b8f16e
JB		 17200 case 't':
17201 /* Byte swap code halfwords. */
17202 while (ptr + 1 < end)
99059e56
RM		 17203 {
17204 tmp = contents[ptr];
17205 contents[ptr] = contents[ptr + 1];
17206 contents[ptr + 1] = tmp;
17207 ptr += 2;
17208 }
c7b8f16e
JB		 17209 break;
17210
17211 case 'd':
17212 /* Leave data alone. */
17213 break;
17214 }
99059e56
RM		 17215 ptr = end;
17216 }
e489d0ae 17217 }
8e3de13a 17218
93204d3a 17219 free (map);
47b2e99c 17220 arm_data->mapcount = -1;
c7b8f16e 17221 arm_data->mapsize = 0;
8e3de13a 17222 arm_data->map = NULL;
8e3de13a 17223
e489d0ae
PB		 17224 return FALSE;
17225}
17226
0beaef2b
PB		 17227/* Mangle thumb function symbols as we read them in. */
17228
8384fb8f 17229static bfd_boolean
0beaef2b
PB		 17230elf32_arm_swap_symbol_in (bfd * abfd,
17231 const void *psrc,
17232 const void *pshn,
17233 Elf_Internal_Sym *dst)
17234{
8384fb8f
AM		 17235 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
17236 return FALSE;
0beaef2b
PB		 17237
17238 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 17239 the address. */
63e1a0fc
PB		 17240 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
17241 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 17242 {
63e1a0fc
PB		 17243 if (dst->st_value & 1)
17244 {
17245 dst->st_value &= ~(bfd_vma) 1;
17246 dst->st_target_internal = ST_BRANCH_TO_THUMB;
17247 }
17248 else
17249 dst->st_target_internal = ST_BRANCH_TO_ARM;
35fc36a8
RS		 17250 }
17251 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
17252 {
17253 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
17254 dst->st_target_internal = ST_BRANCH_TO_THUMB;
0beaef2b 17255 }
35fc36a8
RS		 17256 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
17257 dst->st_target_internal = ST_BRANCH_LONG;
17258 else
63e1a0fc 17259 dst->st_target_internal = ST_BRANCH_UNKNOWN;
35fc36a8 17260
8384fb8f 17261 return TRUE;
0beaef2b
PB		 17262}
17263
17264
17265/* Mangle thumb function symbols as we write them out. */
17266
17267static void
17268elf32_arm_swap_symbol_out (bfd *abfd,
17269 const Elf_Internal_Sym *src,
17270 void *cdst,
17271 void *shndx)
17272{
17273 Elf_Internal_Sym newsym;
17274
17275 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
17276 of the address set, as per the new EABI. We do this unconditionally
17277 because objcopy does not set the elf header flags until after
17278 it writes out the symbol table. */
35fc36a8 17279 if (src->st_target_internal == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 17280 {
17281 newsym = *src;
34e77a92
RS		 17282 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
17283 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 17284 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 17285 {
17286 /* Do this only for defined symbols. At link type, the static
17287 linker will simulate the work of dynamic linker of resolving
17288 symbols and will carry over the thumbness of found symbols to
17289 the output symbol table. It's not clear how it happens, but
17290 the thumbness of undefined symbols can well be different at
17291 runtime, and writing '1' for them will be confusing for users
17292 and possibly for dynamic linker itself.
17293 */
17294 newsym.st_value |= 1;
17295 }
906e58ca 17296
0beaef2b
PB		 17297 src = &newsym;
17298 }
17299 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
17300}
17301
b294bdf8
MM		 17302/* Add the PT_ARM_EXIDX program header. */
17303
17304static bfd_boolean
906e58ca 17305elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 17306 struct bfd_link_info *info ATTRIBUTE_UNUSED)
17307{
17308 struct elf_segment_map *m;
17309 asection *sec;
17310
17311 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
17312 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
17313 {
17314 /* If there is already a PT_ARM_EXIDX header, then we do not
17315 want to add another one. This situation arises when running
17316 "strip"; the input binary already has the header. */
12bd6957 17317 m = elf_seg_map (abfd);
b294bdf8
MM		 17318 while (m && m->p_type != PT_ARM_EXIDX)
17319 m = m->next;
17320 if (!m)
17321 {
21d799b5 17322 m = (struct elf_segment_map *)
99059e56 17323 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 17324 if (m == NULL)
17325 return FALSE;
17326 m->p_type = PT_ARM_EXIDX;
17327 m->count = 1;
17328 m->sections[0] = sec;
17329
12bd6957
AM		 17330 m->next = elf_seg_map (abfd);
17331 elf_seg_map (abfd) = m;
b294bdf8
MM		 17332 }
17333 }
17334
17335 return TRUE;
17336}
17337
17338/* We may add a PT_ARM_EXIDX program header. */
17339
17340static int
a6b96beb
AM		 17341elf32_arm_additional_program_headers (bfd *abfd,
17342 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 17343{
17344 asection *sec;
17345
17346 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
17347 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
17348 return 1;
17349 else
17350 return 0;
17351}
17352
34e77a92
RS		 17353/* Hook called by the linker routine which adds symbols from an object
17354 file. */
17355
17356static bfd_boolean
17357elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
17358 Elf_Internal_Sym *sym, const char **namep,
17359 flagword *flagsp, asection **secp, bfd_vma *valp)
17360{
f1885d1e
AM		 17361 if ((ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
17362 || ELF_ST_BIND (sym->st_info) == STB_GNU_UNIQUE)
17363 && (abfd->flags & DYNAMIC) == 0
17364 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
13a2df29 17365 elf_tdata (info->output_bfd)->has_gnu_symbols = elf_gnu_symbol_any;
34e77a92 17366
c792917c
NC		 17367 if (elf32_arm_hash_table (info) == NULL)
17368 return FALSE;
17369
34e77a92
RS		 17370 if (elf32_arm_hash_table (info)->vxworks_p
17371 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
17372 flagsp, secp, valp))
17373 return FALSE;
17374
17375 return TRUE;
17376}
17377
0beaef2b 17378/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 17379const struct elf_size_info elf32_arm_size_info =
17380{
0beaef2b
PB		 17381 sizeof (Elf32_External_Ehdr),
17382 sizeof (Elf32_External_Phdr),
17383 sizeof (Elf32_External_Shdr),
17384 sizeof (Elf32_External_Rel),
17385 sizeof (Elf32_External_Rela),
17386 sizeof (Elf32_External_Sym),
17387 sizeof (Elf32_External_Dyn),
17388 sizeof (Elf_External_Note),
17389 4,
17390 1,
17391 32, 2,
17392 ELFCLASS32, EV_CURRENT,
17393 bfd_elf32_write_out_phdrs,
17394 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 17395 bfd_elf32_checksum_contents,
0beaef2b
PB		 17396 bfd_elf32_write_relocs,
17397 elf32_arm_swap_symbol_in,
17398 elf32_arm_swap_symbol_out,
17399 bfd_elf32_slurp_reloc_table,
17400 bfd_elf32_slurp_symbol_table,
17401 bfd_elf32_swap_dyn_in,
17402 bfd_elf32_swap_dyn_out,
17403 bfd_elf32_swap_reloc_in,
17404 bfd_elf32_swap_reloc_out,
17405 bfd_elf32_swap_reloca_in,
17406 bfd_elf32_swap_reloca_out
17407};
17408
685e70ae
VK		 17409static bfd_vma
17410read_code32 (const bfd *abfd, const bfd_byte *addr)
17411{
17412 /* V7 BE8 code is always little endian. */
17413 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
17414 return bfd_getl32 (addr);
17415
17416 return bfd_get_32 (abfd, addr);
17417}
17418
17419static bfd_vma
17420read_code16 (const bfd *abfd, const bfd_byte *addr)
17421{
17422 /* V7 BE8 code is always little endian. */
17423 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
17424 return bfd_getl16 (addr);
17425
17426 return bfd_get_16 (abfd, addr);
17427}
17428
6a631e86
YG		 17429/* Return size of plt0 entry starting at ADDR
17430 or (bfd_vma) -1 if size can not be determined. */
17431
17432static bfd_vma
17433elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
17434{
17435 bfd_vma first_word;
17436 bfd_vma plt0_size;
17437
685e70ae 17438 first_word = read_code32 (abfd, addr);
6a631e86
YG		 17439
17440 if (first_word == elf32_arm_plt0_entry[0])
17441 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
17442 else if (first_word == elf32_thumb2_plt0_entry[0])
17443 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
17444 else
17445 /* We don't yet handle this PLT format. */
17446 return (bfd_vma) -1;
17447
17448 return plt0_size;
17449}
17450
17451/* Return size of plt entry starting at offset OFFSET
17452 of plt section located at address START
17453 or (bfd_vma) -1 if size can not be determined. */
17454
17455static bfd_vma
17456elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
17457{
17458 bfd_vma first_insn;
17459 bfd_vma plt_size = 0;
17460 const bfd_byte *addr = start + offset;
17461
17462 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 17463 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 17464 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
17465
17466 /* Respect Thumb stub if necessary. */
685e70ae 17467 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 17468 {
17469 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
17470 }
17471
17472 /* Strip immediate from first add. */
685e70ae 17473 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 17474
17475#ifdef FOUR_WORD_PLT
17476 if (first_insn == elf32_arm_plt_entry[0])
17477 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
17478#else
17479 if (first_insn == elf32_arm_plt_entry_long[0])
17480 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
17481 else if (first_insn == elf32_arm_plt_entry_short[0])
17482 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
17483#endif
17484 else
17485 /* We don't yet handle this PLT format. */
17486 return (bfd_vma) -1;
17487
17488 return plt_size;
17489}
17490
17491/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
17492
17493static long
17494elf32_arm_get_synthetic_symtab (bfd *abfd,
17495 long symcount ATTRIBUTE_UNUSED,
17496 asymbol **syms ATTRIBUTE_UNUSED,
17497 long dynsymcount,
17498 asymbol **dynsyms,
17499 asymbol **ret)
17500{
17501 asection *relplt;
17502 asymbol *s;
17503 arelent *p;
17504 long count, i, n;
17505 size_t size;
17506 Elf_Internal_Shdr *hdr;
17507 char *names;
17508 asection *plt;
17509 bfd_vma offset;
17510 bfd_byte *data;
17511
17512 *ret = NULL;
17513
17514 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
17515 return 0;
17516
17517 if (dynsymcount <= 0)
17518 return 0;
17519
17520 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
17521 if (relplt == NULL)
17522 return 0;
17523
17524 hdr = &elf_section_data (relplt)->this_hdr;
17525 if (hdr->sh_link != elf_dynsymtab (abfd)
17526 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
17527 return 0;
17528
17529 plt = bfd_get_section_by_name (abfd, ".plt");
17530 if (plt == NULL)
17531 return 0;
17532
17533 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
17534 return -1;
17535
17536 data = plt->contents;
17537 if (data == NULL)
17538 {
17539 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
17540 return -1;
17541 bfd_cache_section_contents((asection *) plt, data);
17542 }
17543
17544 count = relplt->size / hdr->sh_entsize;
17545 size = count * sizeof (asymbol);
17546 p = relplt->relocation;
17547 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
17548 {
17549 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
17550 if (p->addend != 0)
17551 size += sizeof ("+0x") - 1 + 8;
17552 }
17553
17554 s = *ret = (asymbol *) bfd_malloc (size);
17555 if (s == NULL)
17556 return -1;
17557
17558 offset = elf32_arm_plt0_size (abfd, data);
17559 if (offset == (bfd_vma) -1)
17560 return -1;
17561
17562 names = (char *) (s + count);
17563 p = relplt->relocation;
17564 n = 0;
17565 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
17566 {
17567 size_t len;
17568
17569 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
17570 if (plt_size == (bfd_vma) -1)
17571 break;
17572
17573 *s = **p->sym_ptr_ptr;
17574 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
17575 we are defining a symbol, ensure one of them is set. */
17576 if ((s->flags & BSF_LOCAL) == 0)
17577 s->flags |= BSF_GLOBAL;
17578 s->flags |= BSF_SYNTHETIC;
17579 s->section = plt;
17580 s->value = offset;
17581 s->name = names;
17582 s->udata.p = NULL;
17583 len = strlen ((*p->sym_ptr_ptr)->name);
17584 memcpy (names, (*p->sym_ptr_ptr)->name, len);
17585 names += len;
17586 if (p->addend != 0)
17587 {
17588 char buf[30], *a;
17589
17590 memcpy (names, "+0x", sizeof ("+0x") - 1);
17591 names += sizeof ("+0x") - 1;
17592 bfd_sprintf_vma (abfd, buf, p->addend);
17593 for (a = buf; *a == '0'; ++a)
17594 ;
17595 len = strlen (a);
17596 memcpy (names, a, len);
17597 names += len;
17598 }
17599 memcpy (names, "@plt", sizeof ("@plt"));
17600 names += sizeof ("@plt");
17601 ++s, ++n;
17602 offset += plt_size;
17603 }
17604
17605 return n;
17606}
17607
252b5132 17608#define ELF_ARCH bfd_arch_arm
ae95ffa6 17609#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 17610#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 17611#ifdef __QNXTARGET__
17612#define ELF_MAXPAGESIZE 0x1000
17613#else
7572ca89 17614#define ELF_MAXPAGESIZE 0x10000
d0facd1b 17615#endif
b1342370 17616#define ELF_MINPAGESIZE 0x1000
24718e3b 17617#define ELF_COMMONPAGESIZE 0x1000
252b5132 17618
ba93b8ac
DJ		 17619#define bfd_elf32_mkobject elf32_arm_mkobject
17620
99e4ae17
AJ		 17621#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
17622#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 17623#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
17624#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
17625#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 17626#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 17627#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
252b5132 17628#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
4ab527b0 17629#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 17630#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 17631#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 17632#define bfd_elf32_bfd_final_link elf32_arm_final_link
6a631e86 17633#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132
RH		 17634
17635#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
17636#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 17637#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
252b5132
RH		 17638#define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
17639#define elf_backend_check_relocs elf32_arm_check_relocs
dc810e39 17640#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 17641#define elf_backend_write_section elf32_arm_write_section
252b5132 17642#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
5e681ec4 17643#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 17644#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
17645#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
17646#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 17647#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 17648#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 17649#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 17650#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 17651#define elf_backend_object_p elf32_arm_object_p
40a18ebd
NC		 17652#define elf_backend_fake_sections elf32_arm_fake_sections
17653#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
e16bb312 17654#define elf_backend_final_write_processing elf32_arm_final_write_processing
5e681ec4 17655#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 17656#define elf_backend_size_info elf32_arm_size_info
b294bdf8 17657#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
906e58ca
NC		 17658#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
17659#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
17660#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 17661#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
906e58ca
NC		 17662
17663#define elf_backend_can_refcount 1
17664#define elf_backend_can_gc_sections 1
17665#define elf_backend_plt_readonly 1
17666#define elf_backend_want_got_plt 1
17667#define elf_backend_want_plt_sym 0
17668#define elf_backend_may_use_rel_p 1
17669#define elf_backend_may_use_rela_p 0
4e7fd91e 17670#define elf_backend_default_use_rela_p 0
252b5132 17671
04f7c78d 17672#define elf_backend_got_header_size 12
b68a20d6 17673#define elf_backend_extern_protected_data 1
04f7c78d 17674
906e58ca
NC		 17675#undef elf_backend_obj_attrs_vendor
17676#define elf_backend_obj_attrs_vendor "aeabi"
17677#undef elf_backend_obj_attrs_section
17678#define elf_backend_obj_attrs_section ".ARM.attributes"
17679#undef elf_backend_obj_attrs_arg_type
17680#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
17681#undef elf_backend_obj_attrs_section_type
104d59d1 17682#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb
NC		 17683#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
17684#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 17685
252b5132 17686#include "elf32-target.h"
7f266840 17687
b38cadfb
NC		 17688/* Native Client targets. */
17689
17690#undef TARGET_LITTLE_SYM
6d00b590 17691#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 17692#undef TARGET_LITTLE_NAME
17693#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
17694#undef TARGET_BIG_SYM
6d00b590 17695#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 17696#undef TARGET_BIG_NAME
17697#define TARGET_BIG_NAME "elf32-bigarm-nacl"
17698
17699/* Like elf32_arm_link_hash_table_create -- but overrides
17700 appropriately for NaCl. */
17701
17702static struct bfd_link_hash_table *
17703elf32_arm_nacl_link_hash_table_create (bfd *abfd)
17704{
17705 struct bfd_link_hash_table *ret;
17706
17707 ret = elf32_arm_link_hash_table_create (abfd);
17708 if (ret)
17709 {
17710 struct elf32_arm_link_hash_table *htab
17711 = (struct elf32_arm_link_hash_table *) ret;
17712
17713 htab->nacl_p = 1;
17714
17715 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
17716 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
17717 }
17718 return ret;
17719}
17720
17721/* Since NaCl doesn't use the ARM-specific unwind format, we don't
17722 really need to use elf32_arm_modify_segment_map. But we do it
17723 anyway just to reduce gratuitous differences with the stock ARM backend. */
17724
17725static bfd_boolean
17726elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
17727{
17728 return (elf32_arm_modify_segment_map (abfd, info)
17729 && nacl_modify_segment_map (abfd, info));
17730}
17731
887badb3
RM		 17732static void
17733elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
17734{
17735 elf32_arm_final_write_processing (abfd, linker);
17736 nacl_final_write_processing (abfd, linker);
17737}
17738
6a631e86
YG		 17739static bfd_vma
17740elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
17741 const arelent *rel ATTRIBUTE_UNUSED)
17742{
17743 return plt->vma
17744 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
17745 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
17746}
887badb3 17747
b38cadfb 17748#undef elf32_bed
6a631e86 17749#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 17750#undef bfd_elf32_bfd_link_hash_table_create
17751#define bfd_elf32_bfd_link_hash_table_create \
17752 elf32_arm_nacl_link_hash_table_create
17753#undef elf_backend_plt_alignment
6a631e86 17754#define elf_backend_plt_alignment 4
b38cadfb
NC		 17755#undef elf_backend_modify_segment_map
17756#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
17757#undef elf_backend_modify_program_headers
17758#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 17759#undef elf_backend_final_write_processing
17760#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 17761#undef bfd_elf32_get_synthetic_symtab
17762#undef elf_backend_plt_sym_val
17763#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
b38cadfb 17764
887badb3
RM		 17765#undef ELF_MINPAGESIZE
17766#undef ELF_COMMONPAGESIZE
17767
b38cadfb
NC		 17768
17769#include "elf32-target.h"
17770
17771/* Reset to defaults. */
17772#undef elf_backend_plt_alignment
17773#undef elf_backend_modify_segment_map
17774#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
17775#undef elf_backend_modify_program_headers
887badb3
RM		 17776#undef elf_backend_final_write_processing
17777#define elf_backend_final_write_processing elf32_arm_final_write_processing
17778#undef ELF_MINPAGESIZE
17779#define ELF_MINPAGESIZE 0x1000
17780#undef ELF_COMMONPAGESIZE
17781#define ELF_COMMONPAGESIZE 0x1000
17782
b38cadfb 17783
906e58ca 17784/* VxWorks Targets. */
4e7fd91e 17785
906e58ca 17786#undef TARGET_LITTLE_SYM
6d00b590 17787#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
906e58ca 17788#undef TARGET_LITTLE_NAME
4e7fd91e 17789#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
906e58ca 17790#undef TARGET_BIG_SYM
6d00b590 17791#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
906e58ca 17792#undef TARGET_BIG_NAME
4e7fd91e
PB		 17793#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
17794
17795/* Like elf32_arm_link_hash_table_create -- but overrides
17796 appropriately for VxWorks. */
906e58ca 17797
4e7fd91e
PB		 17798static struct bfd_link_hash_table *
17799elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
17800{
17801 struct bfd_link_hash_table *ret;
17802
17803 ret = elf32_arm_link_hash_table_create (abfd);
17804 if (ret)
17805 {
17806 struct elf32_arm_link_hash_table *htab
00a97672 17807 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 17808 htab->use_rel = 0;
00a97672 17809 htab->vxworks_p = 1;
4e7fd91e
PB		 17810 }
17811 return ret;
906e58ca 17812}
4e7fd91e 17813
00a97672
RS		 17814static void
17815elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
17816{
17817 elf32_arm_final_write_processing (abfd, linker);
17818 elf_vxworks_final_write_processing (abfd, linker);
17819}
17820
906e58ca 17821#undef elf32_bed
4e7fd91e
PB		 17822#define elf32_bed elf32_arm_vxworks_bed
17823
906e58ca
NC		 17824#undef bfd_elf32_bfd_link_hash_table_create
17825#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 17826#undef elf_backend_final_write_processing
17827#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
17828#undef elf_backend_emit_relocs
17829#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 17830
906e58ca 17831#undef elf_backend_may_use_rel_p
00a97672 17832#define elf_backend_may_use_rel_p 0
906e58ca 17833#undef elf_backend_may_use_rela_p
00a97672 17834#define elf_backend_may_use_rela_p 1
906e58ca 17835#undef elf_backend_default_use_rela_p
00a97672 17836#define elf_backend_default_use_rela_p 1
906e58ca 17837#undef elf_backend_want_plt_sym
00a97672 17838#define elf_backend_want_plt_sym 1
906e58ca 17839#undef ELF_MAXPAGESIZE
00a97672 17840#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 17841
17842#include "elf32-target.h"
17843
17844
21d799b5
NC		 17845/* Merge backend specific data from an object file to the output
17846 object file when linking. */
17847
17848static bfd_boolean
17849elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
17850{
17851 flagword out_flags;
17852 flagword in_flags;
17853 bfd_boolean flags_compatible = TRUE;
17854 asection *sec;
17855
cc643b88 17856 /* Check if we have the same endianness. */
21d799b5
NC		 17857 if (! _bfd_generic_verify_endian_match (ibfd, obfd))
17858 return FALSE;
17859
17860 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
17861 return TRUE;
17862
17863 if (!elf32_arm_merge_eabi_attributes (ibfd, obfd))
17864 return FALSE;
17865
17866 /* The input BFD must have had its flags initialised. */
17867 /* The following seems bogus to me -- The flags are initialized in
17868 the assembler but I don't think an elf_flags_init field is
17869 written into the object. */
17870 /* BFD_ASSERT (elf_flags_init (ibfd)); */
17871
17872 in_flags = elf_elfheader (ibfd)->e_flags;
17873 out_flags = elf_elfheader (obfd)->e_flags;
17874
17875 /* In theory there is no reason why we couldn't handle this. However
17876 in practice it isn't even close to working and there is no real
17877 reason to want it. */
17878 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
17879 && !(ibfd->flags & DYNAMIC)
17880 && (in_flags & EF_ARM_BE8))
17881 {
17882 _bfd_error_handler (_("error: %B is already in final BE8 format"),
17883 ibfd);
17884 return FALSE;
17885 }
17886
17887 if (!elf_flags_init (obfd))
17888 {
17889 /* If the input is the default architecture and had the default
17890 flags then do not bother setting the flags for the output
17891 architecture, instead allow future merges to do this. If no
17892 future merges ever set these flags then they will retain their
99059e56
RM		 17893 uninitialised values, which surprise surprise, correspond
17894 to the default values. */
21d799b5
NC		 17895 if (bfd_get_arch_info (ibfd)->the_default
17896 && elf_elfheader (ibfd)->e_flags == 0)
17897 return TRUE;
17898
17899 elf_flags_init (obfd) = TRUE;
17900 elf_elfheader (obfd)->e_flags = in_flags;
17901
17902 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
17903 && bfd_get_arch_info (obfd)->the_default)
17904 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
17905
17906 return TRUE;
17907 }
17908
17909 /* Determine what should happen if the input ARM architecture
17910 does not match the output ARM architecture. */
17911 if (! bfd_arm_merge_machines (ibfd, obfd))
17912 return FALSE;
17913
17914 /* Identical flags must be compatible. */
17915 if (in_flags == out_flags)
17916 return TRUE;
17917
17918 /* Check to see if the input BFD actually contains any sections. If
17919 not, its flags may not have been initialised either, but it
17920 cannot actually cause any incompatiblity. Do not short-circuit
17921 dynamic objects; their section list may be emptied by
17922 elf_link_add_object_symbols.
17923
17924 Also check to see if there are no code sections in the input.
17925 In this case there is no need to check for code specific flags.
17926 XXX - do we need to worry about floating-point format compatability
17927 in data sections ? */
17928 if (!(ibfd->flags & DYNAMIC))
17929 {
17930 bfd_boolean null_input_bfd = TRUE;
17931 bfd_boolean only_data_sections = TRUE;
17932
17933 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
17934 {
17935 /* Ignore synthetic glue sections. */
17936 if (strcmp (sec->name, ".glue_7")
17937 && strcmp (sec->name, ".glue_7t"))
17938 {
17939 if ((bfd_get_section_flags (ibfd, sec)
17940 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
17941 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 17942 only_data_sections = FALSE;
21d799b5
NC		 17943
17944 null_input_bfd = FALSE;
17945 break;
17946 }
17947 }
17948
17949 if (null_input_bfd || only_data_sections)
17950 return TRUE;
17951 }
17952
17953 /* Complain about various flag mismatches. */
17954 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
17955 EF_ARM_EABI_VERSION (out_flags)))
17956 {
17957 _bfd_error_handler
17958 (_("error: Source object %B has EABI version %d, but target %B has EABI version %d"),
17959 ibfd, obfd,
17960 (in_flags & EF_ARM_EABIMASK) >> 24,
17961 (out_flags & EF_ARM_EABIMASK) >> 24);
17962 return FALSE;
17963 }
17964
17965 /* Not sure what needs to be checked for EABI versions >= 1. */
17966 /* VxWorks libraries do not use these flags. */
17967 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
17968 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
17969 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
17970 {
17971 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
17972 {
17973 _bfd_error_handler
17974 (_("error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"),
17975 ibfd, obfd,
17976 in_flags & EF_ARM_APCS_26 ? 26 : 32,
17977 out_flags & EF_ARM_APCS_26 ? 26 : 32);
17978 flags_compatible = FALSE;
17979 }
17980
17981 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
17982 {
17983 if (in_flags & EF_ARM_APCS_FLOAT)
17984 _bfd_error_handler
17985 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
17986 ibfd, obfd);
17987 else
17988 _bfd_error_handler
17989 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
17990 ibfd, obfd);
17991
17992 flags_compatible = FALSE;
17993 }
17994
17995 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
17996 {
17997 if (in_flags & EF_ARM_VFP_FLOAT)
17998 _bfd_error_handler
17999 (_("error: %B uses VFP instructions, whereas %B does not"),
18000 ibfd, obfd);
18001 else
18002 _bfd_error_handler
18003 (_("error: %B uses FPA instructions, whereas %B does not"),
18004 ibfd, obfd);
18005
18006 flags_compatible = FALSE;
18007 }
18008
18009 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
18010 {
18011 if (in_flags & EF_ARM_MAVERICK_FLOAT)
18012 _bfd_error_handler
18013 (_("error: %B uses Maverick instructions, whereas %B does not"),
18014 ibfd, obfd);
18015 else
18016 _bfd_error_handler
18017 (_("error: %B does not use Maverick instructions, whereas %B does"),
18018 ibfd, obfd);
18019
18020 flags_compatible = FALSE;
18021 }
18022
18023#ifdef EF_ARM_SOFT_FLOAT
18024 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
18025 {
18026 /* We can allow interworking between code that is VFP format
18027 layout, and uses either soft float or integer regs for
18028 passing floating point arguments and results. We already
18029 know that the APCS_FLOAT flags match; similarly for VFP
18030 flags. */
18031 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
18032 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
18033 {
18034 if (in_flags & EF_ARM_SOFT_FLOAT)
18035 _bfd_error_handler
18036 (_("error: %B uses software FP, whereas %B uses hardware FP"),
18037 ibfd, obfd);
18038 else
18039 _bfd_error_handler
18040 (_("error: %B uses hardware FP, whereas %B uses software FP"),
18041 ibfd, obfd);
18042
18043 flags_compatible = FALSE;
18044 }
18045 }
18046#endif
18047
18048 /* Interworking mismatch is only a warning. */
18049 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
18050 {
18051 if (in_flags & EF_ARM_INTERWORK)
18052 {
18053 _bfd_error_handler
18054 (_("Warning: %B supports interworking, whereas %B does not"),
18055 ibfd, obfd);
18056 }
18057 else
18058 {
18059 _bfd_error_handler
18060 (_("Warning: %B does not support interworking, whereas %B does"),
18061 ibfd, obfd);
18062 }
18063 }
18064 }
18065
18066 return flags_compatible;
18067}
18068
18069
906e58ca 18070/* Symbian OS Targets. */
7f266840 18071
906e58ca 18072#undef TARGET_LITTLE_SYM
6d00b590 18073#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
906e58ca 18074#undef TARGET_LITTLE_NAME
7f266840 18075#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
906e58ca 18076#undef TARGET_BIG_SYM
6d00b590 18077#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
906e58ca 18078#undef TARGET_BIG_NAME
7f266840
DJ		 18079#define TARGET_BIG_NAME "elf32-bigarm-symbian"
18080
18081/* Like elf32_arm_link_hash_table_create -- but overrides
18082 appropriately for Symbian OS. */
906e58ca 18083
7f266840
DJ		 18084static struct bfd_link_hash_table *
18085elf32_arm_symbian_link_hash_table_create (bfd *abfd)
18086{
18087 struct bfd_link_hash_table *ret;
18088
18089 ret = elf32_arm_link_hash_table_create (abfd);
18090 if (ret)
18091 {
18092 struct elf32_arm_link_hash_table *htab
18093 = (struct elf32_arm_link_hash_table *)ret;
18094 /* There is no PLT header for Symbian OS. */
18095 htab->plt_header_size = 0;
95720a86
DJ		 18096 /* The PLT entries are each one instruction and one word. */
18097 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 18098 htab->symbian_p = 1;
33bfe774
JB		 18099 /* Symbian uses armv5t or above, so use_blx is always true. */
18100 htab->use_blx = 1;
67687978 18101 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 18102 }
18103 return ret;
906e58ca 18104}
7f266840 18105
b35d266b 18106static const struct bfd_elf_special_section
551b43fd 18107elf32_arm_symbian_special_sections[] =
7f266840 18108{
5cd3778d
MM		 18109 /* In a BPABI executable, the dynamic linking sections do not go in
18110 the loadable read-only segment. The post-linker may wish to
18111 refer to these sections, but they are not part of the final
18112 program image. */
0112cd26
NC		 18113 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
18114 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
18115 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
18116 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
18117 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 18118 /* These sections do not need to be writable as the SymbianOS
18119 postlinker will arrange things so that no dynamic relocation is
18120 required. */
0112cd26
NC		 18121 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
18122 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
18123 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
18124 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 18125};
18126
c3c76620 18127static void
906e58ca 18128elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 18129 struct bfd_link_info *link_info)
c3c76620
MM		 18130{
18131 /* BPABI objects are never loaded directly by an OS kernel; they are
18132 processed by a postlinker first, into an OS-specific format. If
18133 the D_PAGED bit is set on the file, BFD will align segments on
18134 page boundaries, so that an OS can directly map the file. With
18135 BPABI objects, that just results in wasted space. In addition,
18136 because we clear the D_PAGED bit, map_sections_to_segments will
18137 recognize that the program headers should not be mapped into any
18138 loadable segment. */
18139 abfd->flags &= ~D_PAGED;
906e58ca 18140 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 18141}
7f266840
DJ		 18142
18143static bfd_boolean
906e58ca 18144elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 18145 struct bfd_link_info *info)
7f266840
DJ		 18146{
18147 struct elf_segment_map *m;
18148 asection *dynsec;
18149
7f266840
DJ		 18150 /* BPABI shared libraries and executables should have a PT_DYNAMIC
18151 segment. However, because the .dynamic section is not marked
18152 with SEC_LOAD, the generic ELF code will not create such a
18153 segment. */
18154 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
18155 if (dynsec)
18156 {
12bd6957 18157 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 18158 if (m->p_type == PT_DYNAMIC)
18159 break;
18160
18161 if (m == NULL)
18162 {
18163 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 18164 m->next = elf_seg_map (abfd);
18165 elf_seg_map (abfd) = m;
8ded5a0f 18166 }
7f266840
DJ		 18167 }
18168
b294bdf8
MM		 18169 /* Also call the generic arm routine. */
18170 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 18171}
18172
95720a86
DJ		 18173/* Return address for Ith PLT stub in section PLT, for relocation REL
18174 or (bfd_vma) -1 if it should not be included. */
18175
18176static bfd_vma
18177elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
18178 const arelent *rel ATTRIBUTE_UNUSED)
18179{
18180 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
18181}
18182
18183
8029a119 18184#undef elf32_bed
7f266840
DJ		 18185#define elf32_bed elf32_arm_symbian_bed
18186
18187/* The dynamic sections are not allocated on SymbianOS; the postlinker
18188 will process them and then discard them. */
906e58ca 18189#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 18190#define ELF_DYNAMIC_SEC_FLAGS \
18191 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
18192
00a97672 18193#undef elf_backend_emit_relocs
c3c76620 18194
906e58ca
NC		 18195#undef bfd_elf32_bfd_link_hash_table_create
18196#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
18197#undef elf_backend_special_sections
18198#define elf_backend_special_sections elf32_arm_symbian_special_sections
18199#undef elf_backend_begin_write_processing
18200#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
18201#undef elf_backend_final_write_processing
18202#define elf_backend_final_write_processing elf32_arm_final_write_processing
18203
18204#undef elf_backend_modify_segment_map
7f266840
DJ		 18205#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
18206
18207/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 18208#undef elf_backend_got_header_size
7f266840
DJ		 18209#define elf_backend_got_header_size 0
18210
18211/* Similarly, there is no .got.plt section. */
906e58ca 18212#undef elf_backend_want_got_plt
7f266840
DJ		 18213#define elf_backend_want_got_plt 0
18214
906e58ca 18215#undef elf_backend_plt_sym_val
95720a86
DJ		 18216#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
18217
906e58ca 18218#undef elf_backend_may_use_rel_p
00a97672 18219#define elf_backend_may_use_rel_p 1
906e58ca 18220#undef elf_backend_may_use_rela_p
00a97672 18221#define elf_backend_may_use_rela_p 0
906e58ca 18222#undef elf_backend_default_use_rela_p
00a97672 18223#define elf_backend_default_use_rela_p 0
906e58ca 18224#undef elf_backend_want_plt_sym
00a97672 18225#define elf_backend_want_plt_sym 0
906e58ca 18226#undef ELF_MAXPAGESIZE
00a97672 18227#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 18228
7f266840 18229#include "elf32-target.h"
GDB Binutils - Deliverables
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