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Fix seg-fault in the linker introduced by the previous delta.
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
6f2750fe 2 Copyright (C) 1998-2016 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
7f266840
DJ		 59#define elf_info_to_howto 0
60#define elf_info_to_howto_rel elf32_arm_info_to_howto
61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
240 HOWTO (R_ARM_THM_PC8, /* type */
241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
99059e56
RM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
99059e56
RM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
99059e56
RM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
99059e56
RM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
99059e56
RM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
99059e56
RM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
99059e56
RM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
99059e56
RM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
99059e56
RM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
446 TRUE, /* pc_relative */
447 0, /* bitpos */
448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
99059e56
RM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
460 FALSE, /* pc_relative */
461 0, /* bitpos */
462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
99059e56
RM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
474 TRUE, /* pc_relative */
475 0, /* bitpos */
476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
909 HOWTO (R_ARM_ALU_PC_G0, /* type */
910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
917 "R_ARM_ALU_PC_G0", /* name */
918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
937 HOWTO (R_ARM_ALU_PC_G1, /* type */
938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
945 "R_ARM_ALU_PC_G1", /* name */
946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
951 HOWTO (R_ARM_ALU_PC_G2, /* type */
952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
959 "R_ARM_ALU_PC_G2", /* name */
960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
965 HOWTO (R_ARM_LDR_PC_G1, /* type */
966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
973 "R_ARM_LDR_PC_G1", /* name */
974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
979 HOWTO (R_ARM_LDR_PC_G2, /* type */
980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
987 "R_ARM_LDR_PC_G2", /* name */
988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
1001 "R_ARM_LDRS_PC_G0", /* name */
1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
1015 "R_ARM_LDRS_PC_G1", /* name */
1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
1029 "R_ARM_LDRS_PC_G2", /* name */
1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
1043 "R_ARM_LDC_PC_G0", /* name */
1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
1057 "R_ARM_LDC_PC_G1", /* name */
1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
1071 "R_ARM_LDC_PC_G2", /* name */
1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
1085 "R_ARM_ALU_SB_G0_NC", /* name */
1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
1099 "R_ARM_ALU_SB_G0", /* name */
1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
1113 "R_ARM_ALU_SB_G1_NC", /* name */
1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
1127 "R_ARM_ALU_SB_G1", /* name */
1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
1141 "R_ARM_ALU_SB_G2", /* name */
1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
1155 "R_ARM_LDR_SB_G0", /* name */
1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
1169 "R_ARM_LDR_SB_G1", /* name */
1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
1183 "R_ARM_LDR_SB_G2", /* name */
1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
1197 "R_ARM_LDRS_SB_G0", /* name */
1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
1211 "R_ARM_LDRS_SB_G1", /* name */
1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
1225 "R_ARM_LDRS_SB_G2", /* name */
1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
1239 "R_ARM_LDC_SB_G0", /* name */
1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
1253 "R_ARM_LDC_SB_G1", /* name */
1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
1267 "R_ARM_LDC_SB_G2", /* name */
1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
1486
1487 /* GNU extension to record C++ vtable member usage */
1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
99059e56
RM		 1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
1494 complain_overflow_dont, /* complain_on_overflow */
1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
99059e56
RM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
1509 complain_overflow_dont, /* complain_on_overflow */
1510 NULL, /* special_function */
1511 "R_ARM_GNU_VTINHERIT", /* name */
1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
99059e56
RM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
99059e56
RM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
99059e56
RM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
99059e56
RM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
99059e56
RM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
1608 complain_overflow_bitfield,/* complain_on_overflow */
75c11999 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92
RS		 1748/* 160 onwards: */
1749static reloc_howto_type elf32_arm_howto_table_2[1] =
1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
99059e56
RM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
1763 FALSE) /* pcrel_offset */
34e77a92 1764};
c19d1205 1765
34e77a92
RS		 1766/* 249-255 extended, currently unused, relocations: */
1767static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1768{
1769 HOWTO (R_ARM_RREL32, /* type */
1770 0, /* rightshift */
1771 0, /* size (0 = byte, 1 = short, 2 = long) */
1772 0, /* bitsize */
1773 FALSE, /* pc_relative */
1774 0, /* bitpos */
1775 complain_overflow_dont,/* complain_on_overflow */
1776 bfd_elf_generic_reloc, /* special_function */
1777 "R_ARM_RREL32", /* name */
1778 FALSE, /* partial_inplace */
1779 0, /* src_mask */
1780 0, /* dst_mask */
1781 FALSE), /* pcrel_offset */
1782
1783 HOWTO (R_ARM_RABS32, /* type */
1784 0, /* rightshift */
1785 0, /* size (0 = byte, 1 = short, 2 = long) */
1786 0, /* bitsize */
1787 FALSE, /* pc_relative */
1788 0, /* bitpos */
1789 complain_overflow_dont,/* complain_on_overflow */
1790 bfd_elf_generic_reloc, /* special_function */
1791 "R_ARM_RABS32", /* name */
1792 FALSE, /* partial_inplace */
1793 0, /* src_mask */
1794 0, /* dst_mask */
1795 FALSE), /* pcrel_offset */
1796
1797 HOWTO (R_ARM_RPC24, /* type */
1798 0, /* rightshift */
1799 0, /* size (0 = byte, 1 = short, 2 = long) */
1800 0, /* bitsize */
1801 FALSE, /* pc_relative */
1802 0, /* bitpos */
1803 complain_overflow_dont,/* complain_on_overflow */
1804 bfd_elf_generic_reloc, /* special_function */
1805 "R_ARM_RPC24", /* name */
1806 FALSE, /* partial_inplace */
1807 0, /* src_mask */
1808 0, /* dst_mask */
1809 FALSE), /* pcrel_offset */
1810
1811 HOWTO (R_ARM_RBASE, /* type */
1812 0, /* rightshift */
1813 0, /* size (0 = byte, 1 = short, 2 = long) */
1814 0, /* bitsize */
1815 FALSE, /* pc_relative */
1816 0, /* bitpos */
1817 complain_overflow_dont,/* complain_on_overflow */
1818 bfd_elf_generic_reloc, /* special_function */
1819 "R_ARM_RBASE", /* name */
1820 FALSE, /* partial_inplace */
1821 0, /* src_mask */
1822 0, /* dst_mask */
1823 FALSE) /* pcrel_offset */
1824};
1825
1826static reloc_howto_type *
1827elf32_arm_howto_from_type (unsigned int r_type)
1828{
906e58ca 1829 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1830 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1831
34e77a92
RS		 1832 if (r_type == R_ARM_IRELATIVE)
1833 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1834
c19d1205 1835 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1836 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1837 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1838
c19d1205 1839 return NULL;
7f266840
DJ		 1840}
1841
1842static void
1843elf32_arm_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, arelent * bfd_reloc,
1844 Elf_Internal_Rela * elf_reloc)
1845{
1846 unsigned int r_type;
1847
1848 r_type = ELF32_R_TYPE (elf_reloc->r_info);
1849 bfd_reloc->howto = elf32_arm_howto_from_type (r_type);
1850}
1851
1852struct elf32_arm_reloc_map
1853 {
1854 bfd_reloc_code_real_type bfd_reloc_val;
1855 unsigned char elf_reloc_val;
1856 };
1857
1858/* All entries in this list must also be present in elf32_arm_howto_table. */
1859static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1860 {
1861 {BFD_RELOC_NONE, R_ARM_NONE},
1862 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1863 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1864 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
7f266840
DJ		 1865 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1866 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1867 {BFD_RELOC_32, R_ARM_ABS32},
1868 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1869 {BFD_RELOC_8, R_ARM_ABS8},
1870 {BFD_RELOC_16, R_ARM_ABS16},
1871 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
1872 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1873 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1874 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1875 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1876 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1877 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1878 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
7f266840
DJ		 1879 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1880 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1881 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
c19d1205 1882 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
7f266840 1883 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
b43420e6 1884 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
7f266840
DJ		 1885 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1886 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1887 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1888 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1889 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1890 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac
DJ		 1891 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
1892 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
0855e32b
NS		 1893 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1894 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
1895 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
1896 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
1897 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
1898 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1899 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1900 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1901 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1902 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1903 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
1904 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1905 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1906 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
34e77a92 1907 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
c19d1205
ZW		 1908 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1909 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1910 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1911 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1912 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1913 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1914 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1915 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1916 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1917 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1918 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1919 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1920 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1921 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1922 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1923 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1924 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1925 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1926 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1927 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1928 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1929 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1930 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1931 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1932 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1933 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1934 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
1935 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
1936 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
1937 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
1938 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
1939 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
1940 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
1941 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
1942 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
1943 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
1944 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 1945 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 1946 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
1947 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
1948 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
1949 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
1950 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 1951 };
1952
1953static reloc_howto_type *
f1c71a59
ZW		 1954elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1955 bfd_reloc_code_real_type code)
7f266840
DJ		 1956{
1957 unsigned int i;
8029a119 1958
906e58ca 1959 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 1960 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
1961 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 1962
c19d1205 1963 return NULL;
7f266840
DJ		 1964}
1965
157090f7
AM		 1966static reloc_howto_type *
1967elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1968 const char *r_name)
1969{
1970 unsigned int i;
1971
906e58ca 1972 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 1973 if (elf32_arm_howto_table_1[i].name != NULL
1974 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
1975 return &elf32_arm_howto_table_1[i];
1976
906e58ca 1977 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 1978 if (elf32_arm_howto_table_2[i].name != NULL
1979 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
1980 return &elf32_arm_howto_table_2[i];
1981
34e77a92
RS		 1982 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
1983 if (elf32_arm_howto_table_3[i].name != NULL
1984 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
1985 return &elf32_arm_howto_table_3[i];
1986
157090f7
AM		 1987 return NULL;
1988}
1989
906e58ca
NC		 1990/* Support for core dump NOTE sections. */
1991
7f266840 1992static bfd_boolean
f1c71a59 1993elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 1994{
1995 int offset;
1996 size_t size;
1997
1998 switch (note->descsz)
1999 {
2000 default:
2001 return FALSE;
2002
8029a119 2003 case 148: /* Linux/ARM 32-bit. */
7f266840 2004 /* pr_cursig */
228e534f 2005 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2006
2007 /* pr_pid */
228e534f 2008 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2009
2010 /* pr_reg */
2011 offset = 72;
2012 size = 72;
2013
2014 break;
2015 }
2016
2017 /* Make a ".reg/999" section. */
2018 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2019 size, note->descpos + offset);
2020}
2021
2022static bfd_boolean
f1c71a59 2023elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2024{
2025 switch (note->descsz)
2026 {
2027 default:
2028 return FALSE;
2029
8029a119 2030 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2031 elf_tdata (abfd)->core->pid
4395ee08 2032 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2033 elf_tdata (abfd)->core->program
7f266840 2034 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2035 elf_tdata (abfd)->core->command
7f266840
DJ		 2036 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2037 }
2038
2039 /* Note that for some reason, a spurious space is tacked
2040 onto the end of the args in some (at least one anyway)
2041 implementations, so strip it off if it exists. */
7f266840 2042 {
228e534f 2043 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2044 int n = strlen (command);
2045
2046 if (0 < n && command[n - 1] == ' ')
2047 command[n - 1] = '\0';
2048 }
2049
2050 return TRUE;
2051}
2052
1f20dca5
UW		 2053static char *
2054elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2055 int note_type, ...)
2056{
2057 switch (note_type)
2058 {
2059 default:
2060 return NULL;
2061
2062 case NT_PRPSINFO:
2063 {
2064 char data[124];
2065 va_list ap;
2066
2067 va_start (ap, note_type);
2068 memset (data, 0, sizeof (data));
2069 strncpy (data + 28, va_arg (ap, const char *), 16);
2070 strncpy (data + 44, va_arg (ap, const char *), 80);
2071 va_end (ap);
2072
2073 return elfcore_write_note (abfd, buf, bufsiz,
2074 "CORE", note_type, data, sizeof (data));
2075 }
2076
2077 case NT_PRSTATUS:
2078 {
2079 char data[148];
2080 va_list ap;
2081 long pid;
2082 int cursig;
2083 const void *greg;
2084
2085 va_start (ap, note_type);
2086 memset (data, 0, sizeof (data));
2087 pid = va_arg (ap, long);
2088 bfd_put_32 (abfd, pid, data + 24);
2089 cursig = va_arg (ap, int);
2090 bfd_put_16 (abfd, cursig, data + 12);
2091 greg = va_arg (ap, const void *);
2092 memcpy (data + 72, greg, 72);
2093 va_end (ap);
2094
2095 return elfcore_write_note (abfd, buf, bufsiz,
2096 "CORE", note_type, data, sizeof (data));
2097 }
2098 }
2099}
2100
6d00b590 2101#define TARGET_LITTLE_SYM arm_elf32_le_vec
7f266840 2102#define TARGET_LITTLE_NAME "elf32-littlearm"
6d00b590 2103#define TARGET_BIG_SYM arm_elf32_be_vec
7f266840
DJ		 2104#define TARGET_BIG_NAME "elf32-bigarm"
2105
2106#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2107#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2108#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2109
252b5132
RH		 2110typedef unsigned long int insn32;
2111typedef unsigned short int insn16;
2112
3a4a14e9
PB		 2113/* In lieu of proper flags, assume all EABIv4 or later objects are
2114 interworkable. */
57e8b36a 2115#define INTERWORK_FLAG(abfd) \
3a4a14e9 2116 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2117 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2118 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2119
252b5132
RH		 2120/* The linker script knows the section names for placement.
2121 The entry_names are used to do simple name mangling on the stubs.
2122 Given a function name, and its type, the stub can be found. The
9b485d32 2123 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2124#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2125#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2126
2127#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2128#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2129
c7b8f16e
JB		 2130#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2131#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2132
a504d23a
LA		 2133#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2134#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2135
845b51d6
PB		 2136#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2137#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2138
7413f23f
DJ		 2139#define STUB_ENTRY_NAME "__%s_veneer"
2140
4ba2ef8f
TP		 2141#define CMSE_PREFIX "__acle_se_"
2142
252b5132
RH		 2143/* The name of the dynamic interpreter. This is put in the .interp
2144 section. */
2145#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2146
0855e32b 2147static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2148{
2149 0xe08e0000, /* add r0, lr, r0 */
2150 0xe5901004, /* ldr r1, [r0,#4] */
2151 0xe12fff11, /* bx r1 */
2152};
0855e32b
NS		 2153
2154static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2155{
2156 0xe52d2004, /* push {r2} */
2157 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2158 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2159 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2160 0xe081100f, /* 2: add r1, pc */
2161 0xe12fff12, /* bx r2 */
2162 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2163 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2164 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2165};
0855e32b 2166
5e681ec4
PB		 2167#ifdef FOUR_WORD_PLT
2168
252b5132
RH		 2169/* The first entry in a procedure linkage table looks like
2170 this. It is set up so that any shared library function that is
59f2c4e7 2171 called before the relocation has been set up calls the dynamic
9b485d32 2172 linker first. */
e5a52504 2173static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2174{
2175 0xe52de004, /* str lr, [sp, #-4]! */
2176 0xe59fe010, /* ldr lr, [pc, #16] */
2177 0xe08fe00e, /* add lr, pc, lr */
2178 0xe5bef008, /* ldr pc, [lr, #8]! */
2179};
5e681ec4
PB		 2180
2181/* Subsequent entries in a procedure linkage table look like
2182 this. */
e5a52504 2183static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2184{
2185 0xe28fc600, /* add ip, pc, #NN */
2186 0xe28cca00, /* add ip, ip, #NN */
2187 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2188 0x00000000, /* unused */
2189};
5e681ec4 2190
eed94f8f 2191#else /* not FOUR_WORD_PLT */
5e681ec4 2192
5e681ec4
PB		 2193/* The first entry in a procedure linkage table looks like
2194 this. It is set up so that any shared library function that is
2195 called before the relocation has been set up calls the dynamic
2196 linker first. */
e5a52504 2197static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2198{
2199 0xe52de004, /* str lr, [sp, #-4]! */
2200 0xe59fe004, /* ldr lr, [pc, #4] */
2201 0xe08fe00e, /* add lr, pc, lr */
2202 0xe5bef008, /* ldr pc, [lr, #8]! */
2203 0x00000000, /* &GOT[0] - . */
2204};
252b5132 2205
1db37fe6
YG		 2206/* By default subsequent entries in a procedure linkage table look like
2207 this. Offsets that don't fit into 28 bits will cause link error. */
2208static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2209{
2210 0xe28fc600, /* add ip, pc, #0xNN00000 */
2211 0xe28cca00, /* add ip, ip, #0xNN000 */
2212 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2213};
5e681ec4 2214
1db37fe6
YG		 2215/* When explicitly asked, we'll use this "long" entry format
2216 which can cope with arbitrary displacements. */
2217static const bfd_vma elf32_arm_plt_entry_long [] =
2218{
2219 0xe28fc200, /* add ip, pc, #0xN0000000 */
2220 0xe28cc600, /* add ip, ip, #0xNN00000 */
2221 0xe28cca00, /* add ip, ip, #0xNN000 */
2222 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2223};
2224
2225static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2226
eed94f8f
NC		 2227#endif /* not FOUR_WORD_PLT */
2228
2229/* The first entry in a procedure linkage table looks like this.
2230 It is set up so that any shared library function that is called before the
2231 relocation has been set up calls the dynamic linker first. */
2232static const bfd_vma elf32_thumb2_plt0_entry [] =
2233{
2234 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2235 an instruction maybe encoded to one or two array elements. */
2236 0xf8dfb500, /* push {lr} */
2237 0x44fee008, /* ldr.w lr, [pc, #8] */
469a3493 2238 /* add lr, pc */
eed94f8f
NC		 2239 0xff08f85e, /* ldr.w pc, [lr, #8]! */
2240 0x00000000, /* &GOT[0] - . */
2241};
2242
2243/* Subsequent entries in a procedure linkage table for thumb only target
2244 look like this. */
2245static const bfd_vma elf32_thumb2_plt_entry [] =
2246{
2247 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2248 an instruction maybe encoded to one or two array elements. */
2249 0x0c00f240, /* movw ip, #0xNNNN */
2250 0x0c00f2c0, /* movt ip, #0xNNNN */
2251 0xf8dc44fc, /* add ip, pc */
2252 0xbf00f000 /* ldr.w pc, [ip] */
469a3493 2253 /* nop */
eed94f8f 2254};
252b5132 2255
00a97672
RS		 2256/* The format of the first entry in the procedure linkage table
2257 for a VxWorks executable. */
2258static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb
NC		 2259{
2260 0xe52dc008, /* str ip,[sp,#-8]! */
2261 0xe59fc000, /* ldr ip,[pc] */
2262 0xe59cf008, /* ldr pc,[ip,#8] */
2263 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
2264};
00a97672
RS		 2265
2266/* The format of subsequent entries in a VxWorks executable. */
2267static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb
NC		 2268{
2269 0xe59fc000, /* ldr ip,[pc] */
2270 0xe59cf000, /* ldr pc,[ip] */
2271 0x00000000, /* .long @got */
2272 0xe59fc000, /* ldr ip,[pc] */
2273 0xea000000, /* b _PLT */
2274 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2275};
00a97672
RS		 2276
2277/* The format of entries in a VxWorks shared library. */
2278static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb
NC		 2279{
2280 0xe59fc000, /* ldr ip,[pc] */
2281 0xe79cf009, /* ldr pc,[ip,r9] */
2282 0x00000000, /* .long @got */
2283 0xe59fc000, /* ldr ip,[pc] */
2284 0xe599f008, /* ldr pc,[r9,#8] */
2285 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2286};
00a97672 2287
b7693d02
DJ		 2288/* An initial stub used if the PLT entry is referenced from Thumb code. */
2289#define PLT_THUMB_STUB_SIZE 4
2290static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2291{
2292 0x4778, /* bx pc */
2293 0x46c0 /* nop */
2294};
b7693d02 2295
e5a52504
MM		 2296/* The entries in a PLT when using a DLL-based target with multiple
2297 address spaces. */
906e58ca 2298static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb
NC		 2299{
2300 0xe51ff004, /* ldr pc, [pc, #-4] */
2301 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
2302};
2303
2304/* The first entry in a procedure linkage table looks like
2305 this. It is set up so that any shared library function that is
2306 called before the relocation has been set up calls the dynamic
2307 linker first. */
2308static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2309{
2310 /* First bundle: */
2311 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2312 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2313 0xe08cc00f, /* add ip, ip, pc */
2314 0xe52dc008, /* str ip, [sp, #-8]! */
2315 /* Second bundle: */
edccdf7c
RM		 2316 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2317 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2318 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2319 0xe12fff1c, /* bx ip */
b38cadfb 2320 /* Third bundle: */
edccdf7c
RM		 2321 0xe320f000, /* nop */
2322 0xe320f000, /* nop */
2323 0xe320f000, /* nop */
b38cadfb
NC		 2324 /* .Lplt_tail: */
2325 0xe50dc004, /* str ip, [sp, #-4] */
2326 /* Fourth bundle: */
edccdf7c
RM		 2327 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2328 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2329 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2330 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2331};
2332#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2333
2334/* Subsequent entries in a procedure linkage table look like this. */
2335static const bfd_vma elf32_arm_nacl_plt_entry [] =
2336{
2337 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2338 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2339 0xe08cc00f, /* add ip, ip, pc */
2340 0xea000000, /* b .Lplt_tail */
2341};
e5a52504 2342
906e58ca
NC		 2343#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2344#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2345#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2346#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2347#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2348#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2349#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2350#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2351
461a49ca 2352enum stub_insn_type
b38cadfb
NC		 2353{
2354 THUMB16_TYPE = 1,
2355 THUMB32_TYPE,
2356 ARM_TYPE,
2357 DATA_TYPE
2358};
461a49ca 2359
48229727
JB		 2360#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2361/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2362 is inserted in arm_build_one_stub(). */
2363#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2364#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2365#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2366#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2367#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2368#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2369#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2370#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2371
2372typedef struct
2373{
b38cadfb
NC		 2374 bfd_vma data;
2375 enum stub_insn_type type;
2376 unsigned int r_type;
2377 int reloc_addend;
461a49ca
DJ		 2378} insn_sequence;
2379
fea2b4d6
CL		 2380/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2381 to reach the stub if necessary. */
461a49ca 2382static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb
NC		 2383{
2384 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2385 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2386};
906e58ca 2387
fea2b4d6
CL		 2388/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2389 available. */
461a49ca 2390static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb
NC		 2391{
2392 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2393 ARM_INSN (0xe12fff1c), /* bx ip */
2394 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2395};
906e58ca 2396
d3626fb0 2397/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2398static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb
NC		 2399{
2400 THUMB16_INSN (0xb401), /* push {r0} */
2401 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2402 THUMB16_INSN (0x4684), /* mov ip, r0 */
2403 THUMB16_INSN (0xbc01), /* pop {r0} */
2404 THUMB16_INSN (0x4760), /* bx ip */
2405 THUMB16_INSN (0xbf00), /* nop */
2406 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2407};
906e58ca 2408
80c135e5
TP		 2409/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2410static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2411{
2412 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
2413 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2414};
2415
d5a67c02
AV		 2416/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2417 M-profile architectures. */
2418static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2419{
2420 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2421 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
2422 THUMB16_INSN (0x4760), /* bx ip */
2423};
2424
d3626fb0
CL		 2425/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2426 allowed. */
2427static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb
NC		 2428{
2429 THUMB16_INSN (0x4778), /* bx pc */
2430 THUMB16_INSN (0x46c0), /* nop */
2431 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2432 ARM_INSN (0xe12fff1c), /* bx ip */
2433 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2434};
d3626fb0 2435
fea2b4d6
CL		 2436/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2437 available. */
461a49ca 2438static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2439{
2440 THUMB16_INSN (0x4778), /* bx pc */
2441 THUMB16_INSN (0x46c0), /* nop */
2442 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2443 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2444};
906e58ca 2445
fea2b4d6
CL		 2446/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2447 one, when the destination is close enough. */
461a49ca 2448static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2449{
2450 THUMB16_INSN (0x4778), /* bx pc */
2451 THUMB16_INSN (0x46c0), /* nop */
2452 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2453};
c820be07 2454
cf3eccff 2455/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2456 blx to reach the stub if necessary. */
cf3eccff 2457static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb
NC		 2458{
2459 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2460 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
2461 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2462};
906e58ca 2463
cf3eccff
DJ		 2464/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2465 blx to reach the stub if necessary. We can not add into pc;
2466 it is not guaranteed to mode switch (different in ARMv6 and
2467 ARMv7). */
2468static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb
NC		 2469{
2470 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2471 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2472 ARM_INSN (0xe12fff1c), /* bx ip */
2473 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2474};
cf3eccff 2475
ebe24dd4
CL		 2476/* V4T ARM -> ARM long branch stub, PIC. */
2477static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb
NC		 2478{
2479 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2480 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2481 ARM_INSN (0xe12fff1c), /* bx ip */
2482 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2483};
ebe24dd4
CL		 2484
2485/* V4T Thumb -> ARM long branch stub, PIC. */
2486static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb
NC		 2487{
2488 THUMB16_INSN (0x4778), /* bx pc */
2489 THUMB16_INSN (0x46c0), /* nop */
2490 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2491 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
2492 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2493};
ebe24dd4 2494
d3626fb0
CL		 2495/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2496 architectures. */
ebe24dd4 2497static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb
NC		 2498{
2499 THUMB16_INSN (0xb401), /* push {r0} */
2500 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2501 THUMB16_INSN (0x46fc), /* mov ip, pc */
2502 THUMB16_INSN (0x4484), /* add ip, r0 */
2503 THUMB16_INSN (0xbc01), /* pop {r0} */
2504 THUMB16_INSN (0x4760), /* bx ip */
2505 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2506};
ebe24dd4 2507
d3626fb0
CL		 2508/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2509 allowed. */
2510static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb
NC		 2511{
2512 THUMB16_INSN (0x4778), /* bx pc */
2513 THUMB16_INSN (0x46c0), /* nop */
2514 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2515 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2516 ARM_INSN (0xe12fff1c), /* bx ip */
2517 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2518};
d3626fb0 2519
0855e32b
NS		 2520/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2521 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2522static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2523{
b38cadfb
NC		 2524 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2525 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
2526 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2527};
2528
2529/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2530 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2531static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2532{
b38cadfb
NC		 2533 THUMB16_INSN (0x4778), /* bx pc */
2534 THUMB16_INSN (0x46c0), /* nop */
2535 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2536 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
2537 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2538};
2539
7a89b94e
NC		 2540/* NaCl ARM -> ARM long branch stub. */
2541static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2542{
2543 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2544 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2545 ARM_INSN (0xe12fff1c), /* bx ip */
2546 ARM_INSN (0xe320f000), /* nop */
2547 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2548 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2549 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2550 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2551};
2552
2553/* NaCl ARM -> ARM long branch stub, PIC. */
2554static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2555{
2556 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2557 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
2558 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2559 ARM_INSN (0xe12fff1c), /* bx ip */
2560 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2561 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2562 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2563 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2564};
2565
4ba2ef8f
TP		 2566/* Stub used for transition to secure state (aka SG veneer). */
2567static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2568{
2569 THUMB32_INSN (0xe97fe97f), /* sg. */
2570 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2571};
2572
7a89b94e 2573
48229727
JB		 2574/* Cortex-A8 erratum-workaround stubs. */
2575
2576/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2577 can't use a conditional branch to reach this stub). */
2578
2579static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb
NC		 2580{
2581 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
2582 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2583 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2584};
48229727
JB		 2585
2586/* Stub used for b.w and bl.w instructions. */
2587
2588static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2589{
2590 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2591};
48229727
JB		 2592
2593static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2594{
2595 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2596};
48229727
JB		 2597
2598/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2599 instruction (which switches to ARM mode) to point to this stub. Jump to the
2600 real destination using an ARM-mode branch. */
2601
2602static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2603{
2604 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2605};
48229727 2606
9553db3c
NC		 2607/* For each section group there can be a specially created linker section
2608 to hold the stubs for that group. The name of the stub section is based
2609 upon the name of another section within that group with the suffix below
2610 applied.
2611
2612 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2613 create what appeared to be a linker stub section when it actually
2614 contained user code/data. For example, consider this fragment:
b38cadfb 2615
9553db3c
NC		 2616 const char * stubborn_problems[] = { "np" };
2617
2618 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2619 section called:
2620
2621 .data.rel.local.stubborn_problems
2622
2623 This then causes problems in arm32_arm_build_stubs() as it triggers:
2624
2625 // Ignore non-stub sections.
2626 if (!strstr (stub_sec->name, STUB_SUFFIX))
2627 continue;
2628
2629 And so the section would be ignored instead of being processed. Hence
2630 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2631 C identifier. */
2632#define STUB_SUFFIX ".__stub"
906e58ca 2633
738a79f6
CL		 2634/* One entry per long/short branch stub defined above. */
2635#define DEF_STUBS \
2636 DEF_STUB(long_branch_any_any) \
2637 DEF_STUB(long_branch_v4t_arm_thumb) \
2638 DEF_STUB(long_branch_thumb_only) \
2639 DEF_STUB(long_branch_v4t_thumb_thumb) \
2640 DEF_STUB(long_branch_v4t_thumb_arm) \
2641 DEF_STUB(short_branch_v4t_thumb_arm) \
2642 DEF_STUB(long_branch_any_arm_pic) \
2643 DEF_STUB(long_branch_any_thumb_pic) \
2644 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2645 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2646 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2647 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2648 DEF_STUB(long_branch_any_tls_pic) \
2649 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2650 DEF_STUB(long_branch_arm_nacl) \
2651 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2652 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2653 DEF_STUB(a8_veneer_b_cond) \
2654 DEF_STUB(a8_veneer_b) \
2655 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2656 DEF_STUB(a8_veneer_blx) \
2657 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2658 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2659
2660#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2661enum elf32_arm_stub_type
2662{
906e58ca 2663 arm_stub_none,
738a79f6 2664 DEF_STUBS
4f4faa4d 2665 max_stub_type
738a79f6
CL		 2666};
2667#undef DEF_STUB
2668
8d9d9490
TP		 2669/* Note the first a8_veneer type. */
2670const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2671
738a79f6
CL		 2672typedef struct
2673{
d3ce72d0 2674 const insn_sequence* template_sequence;
738a79f6
CL		 2675 int template_size;
2676} stub_def;
2677
2678#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2679static const stub_def stub_definitions[] =
2680{
738a79f6
CL		 2681 {NULL, 0},
2682 DEF_STUBS
906e58ca
NC		 2683};
2684
2685struct elf32_arm_stub_hash_entry
2686{
2687 /* Base hash table entry structure. */
2688 struct bfd_hash_entry root;
2689
2690 /* The stub section. */
2691 asection *stub_sec;
2692
2693 /* Offset within stub_sec of the beginning of this stub. */
2694 bfd_vma stub_offset;
2695
2696 /* Given the symbol's value and its section we can determine its final
2697 value when building the stubs (so the stub knows where to jump). */
2698 bfd_vma target_value;
2699 asection *target_section;
2700
8d9d9490
TP		 2701 /* Same as above but for the source of the branch to the stub. Used for
2702 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2703 such, source section does not need to be recorded since Cortex-A8 erratum
2704 workaround stubs are only generated when both source and target are in the
2705 same section. */
2706 bfd_vma source_value;
48229727
JB		 2707
2708 /* The instruction which caused this stub to be generated (only valid for
2709 Cortex-A8 erratum workaround stubs at present). */
2710 unsigned long orig_insn;
2711
461a49ca 2712 /* The stub type. */
906e58ca 2713 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2714 /* Its encoding size in bytes. */
2715 int stub_size;
2716 /* Its template. */
2717 const insn_sequence *stub_template;
2718 /* The size of the template (number of entries). */
2719 int stub_template_size;
906e58ca
NC		 2720
2721 /* The symbol table entry, if any, that this was derived from. */
2722 struct elf32_arm_link_hash_entry *h;
2723
35fc36a8
RS		 2724 /* Type of branch. */
2725 enum arm_st_branch_type branch_type;
906e58ca
NC		 2726
2727 /* Where this stub is being called from, or, in the case of combined
2728 stub sections, the first input section in the group. */
2729 asection *id_sec;
7413f23f
DJ		 2730
2731 /* The name for the local symbol at the start of this stub. The
2732 stub name in the hash table has to be unique; this does not, so
2733 it can be friendlier. */
2734 char *output_name;
906e58ca
NC		 2735};
2736
e489d0ae
PB		 2737/* Used to build a map of a section. This is required for mixed-endian
2738 code/data. */
2739
2740typedef struct elf32_elf_section_map
2741{
2742 bfd_vma vma;
2743 char type;
2744}
2745elf32_arm_section_map;
2746
c7b8f16e
JB		 2747/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2748
2749typedef enum
2750{
2751 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2752 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2753 VFP11_ERRATUM_ARM_VENEER,
2754 VFP11_ERRATUM_THUMB_VENEER
2755}
2756elf32_vfp11_erratum_type;
2757
2758typedef struct elf32_vfp11_erratum_list
2759{
2760 struct elf32_vfp11_erratum_list *next;
2761 bfd_vma vma;
2762 union
2763 {
2764 struct
2765 {
2766 struct elf32_vfp11_erratum_list *veneer;
2767 unsigned int vfp_insn;
2768 } b;
2769 struct
2770 {
2771 struct elf32_vfp11_erratum_list *branch;
2772 unsigned int id;
2773 } v;
2774 } u;
2775 elf32_vfp11_erratum_type type;
2776}
2777elf32_vfp11_erratum_list;
2778
a504d23a
LA		 2779/* Information about a STM32L4XX erratum veneer, or a branch to such a
2780 veneer. */
2781typedef enum
2782{
2783 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2784 STM32L4XX_ERRATUM_VENEER
2785}
2786elf32_stm32l4xx_erratum_type;
2787
2788typedef struct elf32_stm32l4xx_erratum_list
2789{
2790 struct elf32_stm32l4xx_erratum_list *next;
2791 bfd_vma vma;
2792 union
2793 {
2794 struct
2795 {
2796 struct elf32_stm32l4xx_erratum_list *veneer;
2797 unsigned int insn;
2798 } b;
2799 struct
2800 {
2801 struct elf32_stm32l4xx_erratum_list *branch;
2802 unsigned int id;
2803 } v;
2804 } u;
2805 elf32_stm32l4xx_erratum_type type;
2806}
2807elf32_stm32l4xx_erratum_list;
2808
2468f9c9
PB		 2809typedef enum
2810{
2811 DELETE_EXIDX_ENTRY,
2812 INSERT_EXIDX_CANTUNWIND_AT_END
2813}
2814arm_unwind_edit_type;
2815
2816/* A (sorted) list of edits to apply to an unwind table. */
2817typedef struct arm_unwind_table_edit
2818{
2819 arm_unwind_edit_type type;
2820 /* Note: we sometimes want to insert an unwind entry corresponding to a
2821 section different from the one we're currently writing out, so record the
2822 (text) section this edit relates to here. */
2823 asection *linked_section;
2824 unsigned int index;
2825 struct arm_unwind_table_edit *next;
2826}
2827arm_unwind_table_edit;
2828
8e3de13a 2829typedef struct _arm_elf_section_data
e489d0ae 2830{
2468f9c9 2831 /* Information about mapping symbols. */
e489d0ae 2832 struct bfd_elf_section_data elf;
8e3de13a 2833 unsigned int mapcount;
c7b8f16e 2834 unsigned int mapsize;
e489d0ae 2835 elf32_arm_section_map *map;
2468f9c9 2836 /* Information about CPU errata. */
c7b8f16e
JB		 2837 unsigned int erratumcount;
2838 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2839 unsigned int stm32l4xx_erratumcount;
2840 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2841 unsigned int additional_reloc_count;
2468f9c9
PB		 2842 /* Information about unwind tables. */
2843 union
2844 {
2845 /* Unwind info attached to a text section. */
2846 struct
2847 {
2848 asection *arm_exidx_sec;
2849 } text;
2850
2851 /* Unwind info attached to an .ARM.exidx section. */
2852 struct
2853 {
2854 arm_unwind_table_edit *unwind_edit_list;
2855 arm_unwind_table_edit *unwind_edit_tail;
2856 } exidx;
2857 } u;
8e3de13a
NC		 2858}
2859_arm_elf_section_data;
e489d0ae
PB		 2860
2861#define elf32_arm_section_data(sec) \
8e3de13a 2862 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2863
48229727
JB		 2864/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2865 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2866 so may be created multiple times: we use an array of these entries whilst
2867 relaxing which we can refresh easily, then create stubs for each potentially
2868 erratum-triggering instruction once we've settled on a solution. */
2869
b38cadfb
NC		 2870struct a8_erratum_fix
2871{
48229727
JB		 2872 bfd *input_bfd;
2873 asection *section;
2874 bfd_vma offset;
8d9d9490 2875 bfd_vma target_offset;
48229727
JB		 2876 unsigned long orig_insn;
2877 char *stub_name;
2878 enum elf32_arm_stub_type stub_type;
35fc36a8 2879 enum arm_st_branch_type branch_type;
48229727
JB		 2880};
2881
2882/* A table of relocs applied to branches which might trigger Cortex-A8
2883 erratum. */
2884
b38cadfb
NC		 2885struct a8_erratum_reloc
2886{
48229727
JB		 2887 bfd_vma from;
2888 bfd_vma destination;
92750f34
DJ		 2889 struct elf32_arm_link_hash_entry *hash;
2890 const char *sym_name;
48229727 2891 unsigned int r_type;
35fc36a8 2892 enum arm_st_branch_type branch_type;
48229727
JB		 2893 bfd_boolean non_a8_stub;
2894};
2895
ba93b8ac
DJ		 2896/* The size of the thread control block. */
2897#define TCB_SIZE 8
2898
34e77a92
RS		 2899/* ARM-specific information about a PLT entry, over and above the usual
2900 gotplt_union. */
b38cadfb
NC		 2901struct arm_plt_info
2902{
34e77a92
RS		 2903 /* We reference count Thumb references to a PLT entry separately,
2904 so that we can emit the Thumb trampoline only if needed. */
2905 bfd_signed_vma thumb_refcount;
2906
2907 /* Some references from Thumb code may be eliminated by BL->BLX
2908 conversion, so record them separately. */
2909 bfd_signed_vma maybe_thumb_refcount;
2910
2911 /* How many of the recorded PLT accesses were from non-call relocations.
2912 This information is useful when deciding whether anything takes the
2913 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2914 non-call references to the function should resolve directly to the
2915 real runtime target. */
2916 unsigned int noncall_refcount;
2917
2918 /* Since PLT entries have variable size if the Thumb prologue is
2919 used, we need to record the index into .got.plt instead of
2920 recomputing it from the PLT offset. */
2921 bfd_signed_vma got_offset;
2922};
2923
2924/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2925struct arm_local_iplt_info
2926{
34e77a92
RS		 2927 /* The information that is usually found in the generic ELF part of
2928 the hash table entry. */
2929 union gotplt_union root;
2930
2931 /* The information that is usually found in the ARM-specific part of
2932 the hash table entry. */
2933 struct arm_plt_info arm;
2934
2935 /* A list of all potential dynamic relocations against this symbol. */
2936 struct elf_dyn_relocs *dyn_relocs;
2937};
2938
0ffa91dd 2939struct elf_arm_obj_tdata
ba93b8ac
DJ		 2940{
2941 struct elf_obj_tdata root;
2942
2943 /* tls_type for each local got entry. */
2944 char *local_got_tls_type;
ee065d83 2945
0855e32b
NS		 2946 /* GOTPLT entries for TLS descriptors. */
2947 bfd_vma *local_tlsdesc_gotent;
2948
34e77a92
RS		 2949 /* Information for local symbols that need entries in .iplt. */
2950 struct arm_local_iplt_info **local_iplt;
2951
bf21ed78
MS		 2952 /* Zero to warn when linking objects with incompatible enum sizes. */
2953 int no_enum_size_warning;
a9dc9481
JM		 2954
2955 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2956 int no_wchar_size_warning;
ba93b8ac
DJ		 2957};
2958
0ffa91dd
NC		 2959#define elf_arm_tdata(bfd) \
2960 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 2961
0ffa91dd
NC		 2962#define elf32_arm_local_got_tls_type(bfd) \
2963 (elf_arm_tdata (bfd)->local_got_tls_type)
2964
0855e32b
NS		 2965#define elf32_arm_local_tlsdesc_gotent(bfd) \
2966 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2967
34e77a92
RS		 2968#define elf32_arm_local_iplt(bfd) \
2969 (elf_arm_tdata (bfd)->local_iplt)
2970
0ffa91dd
NC		 2971#define is_arm_elf(bfd) \
2972 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2973 && elf_tdata (bfd) != NULL \
4dfe6ac6 2974 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 2975
2976static bfd_boolean
2977elf32_arm_mkobject (bfd *abfd)
2978{
0ffa91dd 2979 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 2980 ARM_ELF_DATA);
ba93b8ac
DJ		 2981}
2982
ba93b8ac
DJ		 2983#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2984
ba96a88f 2985/* Arm ELF linker hash entry. */
252b5132 2986struct elf32_arm_link_hash_entry
b38cadfb
NC		 2987{
2988 struct elf_link_hash_entry root;
252b5132 2989
b38cadfb
NC		 2990 /* Track dynamic relocs copied for this symbol. */
2991 struct elf_dyn_relocs *dyn_relocs;
b7693d02 2992
b38cadfb
NC		 2993 /* ARM-specific PLT information. */
2994 struct arm_plt_info plt;
ba93b8ac
DJ		 2995
2996#define GOT_UNKNOWN 0
2997#define GOT_NORMAL 1
2998#define GOT_TLS_GD 2
2999#define GOT_TLS_IE 4
0855e32b
NS		 3000#define GOT_TLS_GDESC 8
3001#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3002 unsigned int tls_type : 8;
34e77a92 3003
b38cadfb
NC		 3004 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3005 unsigned int is_iplt : 1;
34e77a92 3006
b38cadfb 3007 unsigned int unused : 23;
a4fd1a8e 3008
b38cadfb
NC		 3009 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3010 starting at the end of the jump table. */
3011 bfd_vma tlsdesc_got;
0855e32b 3012
b38cadfb
NC		 3013 /* The symbol marking the real symbol location for exported thumb
3014 symbols with Arm stubs. */
3015 struct elf_link_hash_entry *export_glue;
906e58ca 3016
b38cadfb 3017 /* A pointer to the most recently used stub hash entry against this
8029a119 3018 symbol. */
b38cadfb
NC		 3019 struct elf32_arm_stub_hash_entry *stub_cache;
3020};
252b5132 3021
252b5132 3022/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3023#define elf32_arm_link_hash_traverse(table, func, info) \
3024 (elf_link_hash_traverse \
3025 (&(table)->root, \
b7693d02 3026 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3027 (info)))
3028
3029/* Get the ARM elf linker hash table from a link_info structure. */
3030#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3031 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3032 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3033
906e58ca
NC		 3034#define arm_stub_hash_lookup(table, string, create, copy) \
3035 ((struct elf32_arm_stub_hash_entry *) \
3036 bfd_hash_lookup ((table), (string), (create), (copy)))
3037
21d799b5
NC		 3038/* Array to keep track of which stub sections have been created, and
3039 information on stub grouping. */
3040struct map_stub
3041{
3042 /* This is the section to which stubs in the group will be
3043 attached. */
3044 asection *link_sec;
3045 /* The stub section. */
3046 asection *stub_sec;
3047};
3048
0855e32b
NS		 3049#define elf32_arm_compute_jump_table_size(htab) \
3050 ((htab)->next_tls_desc_index * 4)
3051
9b485d32 3052/* ARM ELF linker hash table. */
252b5132 3053struct elf32_arm_link_hash_table
906e58ca
NC		 3054{
3055 /* The main hash table. */
3056 struct elf_link_hash_table root;
252b5132 3057
906e58ca
NC		 3058 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3059 bfd_size_type thumb_glue_size;
252b5132 3060
906e58ca
NC		 3061 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3062 bfd_size_type arm_glue_size;
252b5132 3063
906e58ca
NC		 3064 /* The size in bytes of section containing the ARMv4 BX veneers. */
3065 bfd_size_type bx_glue_size;
845b51d6 3066
906e58ca
NC		 3067 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3068 veneer has been populated. */
3069 bfd_vma bx_glue_offset[15];
845b51d6 3070
906e58ca
NC		 3071 /* The size in bytes of the section containing glue for VFP11 erratum
3072 veneers. */
3073 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3074
a504d23a
LA		 3075 /* The size in bytes of the section containing glue for STM32L4XX erratum
3076 veneers. */
3077 bfd_size_type stm32l4xx_erratum_glue_size;
3078
48229727
JB		 3079 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3080 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3081 elf32_arm_write_section(). */
3082 struct a8_erratum_fix *a8_erratum_fixes;
3083 unsigned int num_a8_erratum_fixes;
3084
906e58ca
NC		 3085 /* An arbitrary input BFD chosen to hold the glue sections. */
3086 bfd * bfd_of_glue_owner;
ba96a88f 3087
906e58ca
NC		 3088 /* Nonzero to output a BE8 image. */
3089 int byteswap_code;
e489d0ae 3090
906e58ca
NC		 3091 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3092 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3093 int target1_is_rel;
9c504268 3094
906e58ca
NC		 3095 /* The relocation to use for R_ARM_TARGET2 relocations. */
3096 int target2_reloc;
eb043451 3097
906e58ca
NC		 3098 /* 0 = Ignore R_ARM_V4BX.
3099 1 = Convert BX to MOV PC.
3100 2 = Generate v4 interworing stubs. */
3101 int fix_v4bx;
319850b4 3102
48229727
JB		 3103 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3104 int fix_cortex_a8;
3105
2de70689
MGD		 3106 /* Whether we should fix the ARM1176 BLX immediate issue. */
3107 int fix_arm1176;
3108
906e58ca
NC		 3109 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3110 int use_blx;
33bfe774 3111
906e58ca
NC		 3112 /* What sort of code sequences we should look for which may trigger the
3113 VFP11 denorm erratum. */
3114 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3115
906e58ca
NC		 3116 /* Global counter for the number of fixes we have emitted. */
3117 int num_vfp11_fixes;
c7b8f16e 3118
a504d23a
LA		 3119 /* What sort of code sequences we should look for which may trigger the
3120 STM32L4XX erratum. */
3121 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3122
3123 /* Global counter for the number of fixes we have emitted. */
3124 int num_stm32l4xx_fixes;
3125
906e58ca
NC		 3126 /* Nonzero to force PIC branch veneers. */
3127 int pic_veneer;
27e55c4d 3128
906e58ca
NC		 3129 /* The number of bytes in the initial entry in the PLT. */
3130 bfd_size_type plt_header_size;
e5a52504 3131
906e58ca
NC		 3132 /* The number of bytes in the subsequent PLT etries. */
3133 bfd_size_type plt_entry_size;
e5a52504 3134
906e58ca
NC		 3135 /* True if the target system is VxWorks. */
3136 int vxworks_p;
00a97672 3137
906e58ca
NC		 3138 /* True if the target system is Symbian OS. */
3139 int symbian_p;
e5a52504 3140
b38cadfb
NC		 3141 /* True if the target system is Native Client. */
3142 int nacl_p;
3143
906e58ca
NC		 3144 /* True if the target uses REL relocations. */
3145 int use_rel;
4e7fd91e 3146
54ddd295
TP		 3147 /* Nonzero if import library must be a secure gateway import library
3148 as per ARMv8-M Security Extensions. */
3149 int cmse_implib;
3150
0955507f
TP		 3151 /* The import library whose symbols' address must remain stable in
3152 the import library generated. */
3153 bfd *in_implib_bfd;
3154
0855e32b
NS		 3155 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3156 bfd_vma next_tls_desc_index;
3157
3158 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3159 bfd_vma num_tls_desc;
3160
906e58ca 3161 /* Short-cuts to get to dynamic linker sections. */
906e58ca
NC		 3162 asection *sdynbss;
3163 asection *srelbss;
5e681ec4 3164
906e58ca
NC		 3165 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3166 asection *srelplt2;
00a97672 3167
0855e32b
NS		 3168 /* The offset into splt of the PLT entry for the TLS descriptor
3169 resolver. Special values are 0, if not necessary (or not found
3170 to be necessary yet), and -1 if needed but not determined
3171 yet. */
3172 bfd_vma dt_tlsdesc_plt;
3173
3174 /* The offset into sgot of the GOT entry used by the PLT entry
3175 above. */
b38cadfb 3176 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3177
3178 /* Offset in .plt section of tls_arm_trampoline. */
3179 bfd_vma tls_trampoline;
3180
906e58ca
NC		 3181 /* Data for R_ARM_TLS_LDM32 relocations. */
3182 union
3183 {
3184 bfd_signed_vma refcount;
3185 bfd_vma offset;
3186 } tls_ldm_got;
b7693d02 3187
87d72d41
AM		 3188 /* Small local sym cache. */
3189 struct sym_cache sym_cache;
906e58ca
NC		 3190
3191 /* For convenience in allocate_dynrelocs. */
3192 bfd * obfd;
3193
0855e32b
NS		 3194 /* The amount of space used by the reserved portion of the sgotplt
3195 section, plus whatever space is used by the jump slots. */
3196 bfd_vma sgotplt_jump_table_size;
3197
906e58ca
NC		 3198 /* The stub hash table. */
3199 struct bfd_hash_table stub_hash_table;
3200
3201 /* Linker stub bfd. */
3202 bfd *stub_bfd;
3203
3204 /* Linker call-backs. */
6bde4c52
TP		 3205 asection * (*add_stub_section) (const char *, asection *, asection *,
3206 unsigned int);
906e58ca
NC		 3207 void (*layout_sections_again) (void);
3208
3209 /* Array to keep track of which stub sections have been created, and
3210 information on stub grouping. */
21d799b5 3211 struct map_stub *stub_group;
906e58ca 3212
4ba2ef8f
TP		 3213 /* Input stub section holding secure gateway veneers. */
3214 asection *cmse_stub_sec;
3215
0955507f
TP		 3216 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3217 start to be allocated. */
3218 bfd_vma new_cmse_stub_offset;
3219
fe33d2fa 3220 /* Number of elements in stub_group. */
7292b3ac 3221 unsigned int top_id;
fe33d2fa 3222
906e58ca
NC		 3223 /* Assorted information used by elf32_arm_size_stubs. */
3224 unsigned int bfd_count;
7292b3ac 3225 unsigned int top_index;
906e58ca
NC		 3226 asection **input_list;
3227};
252b5132 3228
a504d23a
LA		 3229static inline int
3230ctz (unsigned int mask)
3231{
3232#if GCC_VERSION >= 3004
3233 return __builtin_ctz (mask);
3234#else
3235 unsigned int i;
3236
3237 for (i = 0; i < 8 * sizeof (mask); i++)
3238 {
3239 if (mask & 0x1)
3240 break;
3241 mask = (mask >> 1);
3242 }
3243 return i;
3244#endif
3245}
3246
3247static inline int
3248popcount (unsigned int mask)
3249{
3250#if GCC_VERSION >= 3004
3251 return __builtin_popcount (mask);
3252#else
3253 unsigned int i, sum = 0;
3254
3255 for (i = 0; i < 8 * sizeof (mask); i++)
3256 {
3257 if (mask & 0x1)
3258 sum++;
3259 mask = (mask >> 1);
3260 }
3261 return sum;
3262#endif
3263}
3264
780a67af
NC		 3265/* Create an entry in an ARM ELF linker hash table. */
3266
3267static struct bfd_hash_entry *
57e8b36a 3268elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3269 struct bfd_hash_table * table,
3270 const char * string)
780a67af
NC		 3271{
3272 struct elf32_arm_link_hash_entry * ret =
3273 (struct elf32_arm_link_hash_entry *) entry;
3274
3275 /* Allocate the structure if it has not already been allocated by a
3276 subclass. */
906e58ca 3277 if (ret == NULL)
21d799b5 3278 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3279 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3280 if (ret == NULL)
780a67af
NC		 3281 return (struct bfd_hash_entry *) ret;
3282
3283 /* Call the allocation method of the superclass. */
3284 ret = ((struct elf32_arm_link_hash_entry *)
3285 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3286 table, string));
57e8b36a 3287 if (ret != NULL)
b7693d02 3288 {
0bdcacaf 3289 ret->dyn_relocs = NULL;
ba93b8ac 3290 ret->tls_type = GOT_UNKNOWN;
0855e32b 3291 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3292 ret->plt.thumb_refcount = 0;
3293 ret->plt.maybe_thumb_refcount = 0;
3294 ret->plt.noncall_refcount = 0;
3295 ret->plt.got_offset = -1;
3296 ret->is_iplt = FALSE;
a4fd1a8e 3297 ret->export_glue = NULL;
906e58ca
NC		 3298
3299 ret->stub_cache = NULL;
b7693d02 3300 }
780a67af
NC		 3301
3302 return (struct bfd_hash_entry *) ret;
3303}
3304
34e77a92
RS		 3305/* Ensure that we have allocated bookkeeping structures for ABFD's local
3306 symbols. */
3307
3308static bfd_boolean
3309elf32_arm_allocate_local_sym_info (bfd *abfd)
3310{
3311 if (elf_local_got_refcounts (abfd) == NULL)
3312 {
3313 bfd_size_type num_syms;
3314 bfd_size_type size;
3315 char *data;
3316
3317 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3318 size = num_syms * (sizeof (bfd_signed_vma)
3319 + sizeof (struct arm_local_iplt_info *)
3320 + sizeof (bfd_vma)
3321 + sizeof (char));
3322 data = bfd_zalloc (abfd, size);
3323 if (data == NULL)
3324 return FALSE;
3325
3326 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3327 data += num_syms * sizeof (bfd_signed_vma);
3328
3329 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3330 data += num_syms * sizeof (struct arm_local_iplt_info *);
3331
3332 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3333 data += num_syms * sizeof (bfd_vma);
3334
3335 elf32_arm_local_got_tls_type (abfd) = data;
3336 }
3337 return TRUE;
3338}
3339
3340/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3341 to input bfd ABFD. Create the information if it doesn't already exist.
3342 Return null if an allocation fails. */
3343
3344static struct arm_local_iplt_info *
3345elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3346{
3347 struct arm_local_iplt_info **ptr;
3348
3349 if (!elf32_arm_allocate_local_sym_info (abfd))
3350 return NULL;
3351
3352 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3353 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3354 if (*ptr == NULL)
3355 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3356 return *ptr;
3357}
3358
3359/* Try to obtain PLT information for the symbol with index R_SYMNDX
3360 in ABFD's symbol table. If the symbol is global, H points to its
3361 hash table entry, otherwise H is null.
3362
3363 Return true if the symbol does have PLT information. When returning
3364 true, point *ROOT_PLT at the target-independent reference count/offset
3365 union and *ARM_PLT at the ARM-specific information. */
3366
3367static bfd_boolean
4ba2ef8f
TP		 3368elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3369 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3370 unsigned long r_symndx, union gotplt_union **root_plt,
3371 struct arm_plt_info **arm_plt)
3372{
3373 struct arm_local_iplt_info *local_iplt;
3374
4ba2ef8f
TP		 3375 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3376 return FALSE;
3377
34e77a92
RS		 3378 if (h != NULL)
3379 {
3380 *root_plt = &h->root.plt;
3381 *arm_plt = &h->plt;
3382 return TRUE;
3383 }
3384
3385 if (elf32_arm_local_iplt (abfd) == NULL)
3386 return FALSE;
3387
3388 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3389 if (local_iplt == NULL)
3390 return FALSE;
3391
3392 *root_plt = &local_iplt->root;
3393 *arm_plt = &local_iplt->arm;
3394 return TRUE;
3395}
3396
3397/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3398 before it. */
3399
3400static bfd_boolean
3401elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3402 struct arm_plt_info *arm_plt)
3403{
3404 struct elf32_arm_link_hash_table *htab;
3405
3406 htab = elf32_arm_hash_table (info);
3407 return (arm_plt->thumb_refcount != 0
3408 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3409}
3410
3411/* Return a pointer to the head of the dynamic reloc list that should
3412 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3413 ABFD's symbol table. Return null if an error occurs. */
3414
3415static struct elf_dyn_relocs **
3416elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3417 Elf_Internal_Sym *isym)
3418{
3419 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3420 {
3421 struct arm_local_iplt_info *local_iplt;
3422
3423 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3424 if (local_iplt == NULL)
3425 return NULL;
3426 return &local_iplt->dyn_relocs;
3427 }
3428 else
3429 {
3430 /* Track dynamic relocs needed for local syms too.
3431 We really need local syms available to do this
3432 easily. Oh well. */
3433 asection *s;
3434 void *vpp;
3435
3436 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3437 if (s == NULL)
3438 abort ();
3439
3440 vpp = &elf_section_data (s)->local_dynrel;
3441 return (struct elf_dyn_relocs **) vpp;
3442 }
3443}
3444
906e58ca
NC		 3445/* Initialize an entry in the stub hash table. */
3446
3447static struct bfd_hash_entry *
3448stub_hash_newfunc (struct bfd_hash_entry *entry,
3449 struct bfd_hash_table *table,
3450 const char *string)
3451{
3452 /* Allocate the structure if it has not already been allocated by a
3453 subclass. */
3454 if (entry == NULL)
3455 {
21d799b5 3456 entry = (struct bfd_hash_entry *)
99059e56 3457 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3458 if (entry == NULL)
3459 return entry;
3460 }
3461
3462 /* Call the allocation method of the superclass. */
3463 entry = bfd_hash_newfunc (entry, table, string);
3464 if (entry != NULL)
3465 {
3466 struct elf32_arm_stub_hash_entry *eh;
3467
3468 /* Initialize the local fields. */
3469 eh = (struct elf32_arm_stub_hash_entry *) entry;
3470 eh->stub_sec = NULL;
0955507f 3471 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3472 eh->source_value = 0;
906e58ca
NC		 3473 eh->target_value = 0;
3474 eh->target_section = NULL;
cedfb179 3475 eh->orig_insn = 0;
906e58ca 3476 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3477 eh->stub_size = 0;
3478 eh->stub_template = NULL;
0955507f 3479 eh->stub_template_size = -1;
906e58ca
NC		 3480 eh->h = NULL;
3481 eh->id_sec = NULL;
d8d2f433 3482 eh->output_name = NULL;
906e58ca
NC		 3483 }
3484
3485 return entry;
3486}
3487
00a97672 3488/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3489 shortcuts to them in our hash table. */
3490
3491static bfd_boolean
57e8b36a 3492create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3493{
3494 struct elf32_arm_link_hash_table *htab;
3495
e5a52504 3496 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3497 if (htab == NULL)
3498 return FALSE;
3499
e5a52504
MM		 3500 /* BPABI objects never have a GOT, or associated sections. */
3501 if (htab->symbian_p)
3502 return TRUE;
3503
5e681ec4
PB		 3504 if (! _bfd_elf_create_got_section (dynobj, info))
3505 return FALSE;
3506
5e681ec4
PB		 3507 return TRUE;
3508}
3509
34e77a92
RS		 3510/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3511
3512static bfd_boolean
3513create_ifunc_sections (struct bfd_link_info *info)
3514{
3515 struct elf32_arm_link_hash_table *htab;
3516 const struct elf_backend_data *bed;
3517 bfd *dynobj;
3518 asection *s;
3519 flagword flags;
b38cadfb 3520
34e77a92
RS		 3521 htab = elf32_arm_hash_table (info);
3522 dynobj = htab->root.dynobj;
3523 bed = get_elf_backend_data (dynobj);
3524 flags = bed->dynamic_sec_flags;
3525
3526 if (htab->root.iplt == NULL)
3527 {
3d4d4302
AM		 3528 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3529 flags | SEC_READONLY | SEC_CODE);
34e77a92 3530 if (s == NULL
a0f49396 3531 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3532 return FALSE;
3533 htab->root.iplt = s;
3534 }
3535
3536 if (htab->root.irelplt == NULL)
3537 {
3d4d4302
AM		 3538 s = bfd_make_section_anyway_with_flags (dynobj,
3539 RELOC_SECTION (htab, ".iplt"),
3540 flags | SEC_READONLY);
34e77a92 3541 if (s == NULL
a0f49396 3542 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3543 return FALSE;
3544 htab->root.irelplt = s;
3545 }
3546
3547 if (htab->root.igotplt == NULL)
3548 {
3d4d4302 3549 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3550 if (s == NULL
3551 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3552 return FALSE;
3553 htab->root.igotplt = s;
3554 }
3555 return TRUE;
3556}
3557
eed94f8f
NC		 3558/* Determine if we're dealing with a Thumb only architecture. */
3559
3560static bfd_boolean
3561using_thumb_only (struct elf32_arm_link_hash_table *globals)
3562{
2fd158eb
TP		 3563 int arch;
3564 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3565 Tag_CPU_arch_profile);
eed94f8f 3566
2fd158eb
TP		 3567 if (profile)
3568 return profile == 'M';
eed94f8f 3569
2fd158eb 3570 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3571
60a019a0
TP		 3572 /* Force return logic to be reviewed for each new architecture. */
3573 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3574 || arch == TAG_CPU_ARCH_V8M_BASE
3575 || arch == TAG_CPU_ARCH_V8M_MAIN);
3576
2fd158eb
TP		 3577 if (arch == TAG_CPU_ARCH_V6_M
3578 || arch == TAG_CPU_ARCH_V6S_M
3579 || arch == TAG_CPU_ARCH_V7E_M
3580 || arch == TAG_CPU_ARCH_V8M_BASE
3581 || arch == TAG_CPU_ARCH_V8M_MAIN)
3582 return TRUE;
eed94f8f 3583
2fd158eb 3584 return FALSE;
eed94f8f
NC		 3585}
3586
3587/* Determine if we're dealing with a Thumb-2 object. */
3588
3589static bfd_boolean
3590using_thumb2 (struct elf32_arm_link_hash_table *globals)
3591{
60a019a0
TP		 3592 int arch;
3593 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3594 Tag_THUMB_ISA_use);
3595
3596 if (thumb_isa)
3597 return thumb_isa == 2;
3598
3599 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3600
3601 /* Force return logic to be reviewed for each new architecture. */
3602 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3603 || arch == TAG_CPU_ARCH_V8M_BASE
3604 || arch == TAG_CPU_ARCH_V8M_MAIN);
3605
3606 return (arch == TAG_CPU_ARCH_V6T2
3607 || arch == TAG_CPU_ARCH_V7
3608 || arch == TAG_CPU_ARCH_V7E_M
3609 || arch == TAG_CPU_ARCH_V8
3610 || arch == TAG_CPU_ARCH_V8M_MAIN);
eed94f8f
NC		 3611}
3612
5e866f5a
TP		 3613/* Determine whether Thumb-2 BL instruction is available. */
3614
3615static bfd_boolean
3616using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3617{
3618 int arch =
3619 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3620
3621 /* Force return logic to be reviewed for each new architecture. */
3622 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3623 || arch == TAG_CPU_ARCH_V8M_BASE
3624 || arch == TAG_CPU_ARCH_V8M_MAIN);
3625
3626 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3627 return (arch == TAG_CPU_ARCH_V6T2
3628 || arch >= TAG_CPU_ARCH_V7);
3629}
3630
00a97672
RS		 3631/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3632 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3633 hash table. */
3634
3635static bfd_boolean
57e8b36a 3636elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3637{
3638 struct elf32_arm_link_hash_table *htab;
3639
3640 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3641 if (htab == NULL)
3642 return FALSE;
3643
362d30a1 3644 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3645 return FALSE;
3646
3647 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3648 return FALSE;
3649
3d4d4302 3650 htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss");
0e1862bb 3651 if (!bfd_link_pic (info))
3d4d4302
AM		 3652 htab->srelbss = bfd_get_linker_section (dynobj,
3653 RELOC_SECTION (htab, ".bss"));
00a97672
RS		 3654
3655 if (htab->vxworks_p)
3656 {
3657 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3658 return FALSE;
3659
0e1862bb 3660 if (bfd_link_pic (info))
00a97672
RS		 3661 {
3662 htab->plt_header_size = 0;
3663 htab->plt_entry_size
3664 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3665 }
3666 else
3667 {
3668 htab->plt_header_size
3669 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3670 htab->plt_entry_size
3671 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3672 }
aebf9be7
NC		 3673
3674 if (elf_elfheader (dynobj))
3675 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3676 }
eed94f8f
NC		 3677 else
3678 {
3679 /* PR ld/16017
3680 Test for thumb only architectures. Note - we cannot just call
3681 using_thumb_only() as the attributes in the output bfd have not been
3682 initialised at this point, so instead we use the input bfd. */
3683 bfd * saved_obfd = htab->obfd;
3684
3685 htab->obfd = dynobj;
3686 if (using_thumb_only (htab))
3687 {
3688 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3689 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3690 }
3691 htab->obfd = saved_obfd;
3692 }
5e681ec4 3693
362d30a1
RS		 3694 if (!htab->root.splt
3695 || !htab->root.srelplt
e5a52504 3696 || !htab->sdynbss
0e1862bb 3697 || (!bfd_link_pic (info) && !htab->srelbss))
5e681ec4
PB		 3698 abort ();
3699
3700 return TRUE;
3701}
3702
906e58ca
NC		 3703/* Copy the extra info we tack onto an elf_link_hash_entry. */
3704
3705static void
3706elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3707 struct elf_link_hash_entry *dir,
3708 struct elf_link_hash_entry *ind)
3709{
3710 struct elf32_arm_link_hash_entry *edir, *eind;
3711
3712 edir = (struct elf32_arm_link_hash_entry *) dir;
3713 eind = (struct elf32_arm_link_hash_entry *) ind;
3714
0bdcacaf 3715 if (eind->dyn_relocs != NULL)
906e58ca 3716 {
0bdcacaf 3717 if (edir->dyn_relocs != NULL)
906e58ca 3718 {
0bdcacaf
RS		 3719 struct elf_dyn_relocs **pp;
3720 struct elf_dyn_relocs *p;
906e58ca
NC		 3721
3722 /* Add reloc counts against the indirect sym to the direct sym
3723 list. Merge any entries against the same section. */
0bdcacaf 3724 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3725 {
0bdcacaf 3726 struct elf_dyn_relocs *q;
906e58ca 3727
0bdcacaf
RS		 3728 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3729 if (q->sec == p->sec)
906e58ca
NC		 3730 {
3731 q->pc_count += p->pc_count;
3732 q->count += p->count;
3733 *pp = p->next;
3734 break;
3735 }
3736 if (q == NULL)
3737 pp = &p->next;
3738 }
0bdcacaf 3739 *pp = edir->dyn_relocs;
906e58ca
NC		 3740 }
3741
0bdcacaf
RS		 3742 edir->dyn_relocs = eind->dyn_relocs;
3743 eind->dyn_relocs = NULL;
906e58ca
NC		 3744 }
3745
3746 if (ind->root.type == bfd_link_hash_indirect)
3747 {
3748 /* Copy over PLT info. */
34e77a92
RS		 3749 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3750 eind->plt.thumb_refcount = 0;
3751 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3752 eind->plt.maybe_thumb_refcount = 0;
3753 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3754 eind->plt.noncall_refcount = 0;
3755
3756 /* We should only allocate a function to .iplt once the final
3757 symbol information is known. */
3758 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3759
3760 if (dir->got.refcount <= 0)
3761 {
3762 edir->tls_type = eind->tls_type;
3763 eind->tls_type = GOT_UNKNOWN;
3764 }
3765 }
3766
3767 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3768}
3769
68faa637
AM		 3770/* Destroy an ARM elf linker hash table. */
3771
3772static void
d495ab0d 3773elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3774{
3775 struct elf32_arm_link_hash_table *ret
d495ab0d 3776 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3777
3778 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3779 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3780}
3781
906e58ca
NC		 3782/* Create an ARM elf linker hash table. */
3783
3784static struct bfd_link_hash_table *
3785elf32_arm_link_hash_table_create (bfd *abfd)
3786{
3787 struct elf32_arm_link_hash_table *ret;
3788 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3789
7bf52ea2 3790 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3791 if (ret == NULL)
3792 return NULL;
3793
3794 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3795 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3796 sizeof (struct elf32_arm_link_hash_entry),
3797 ARM_ELF_DATA))
906e58ca
NC		 3798 {
3799 free (ret);
3800 return NULL;
3801 }
3802
906e58ca 3803 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3804 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3805#ifdef FOUR_WORD_PLT
3806 ret->plt_header_size = 16;
3807 ret->plt_entry_size = 16;
3808#else
3809 ret->plt_header_size = 20;
1db37fe6 3810 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3811#endif
906e58ca 3812 ret->use_rel = 1;
906e58ca 3813 ret->obfd = abfd;
906e58ca
NC		 3814
3815 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3816 sizeof (struct elf32_arm_stub_hash_entry)))
3817 {
d495ab0d 3818 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3819 return NULL;
3820 }
d495ab0d 3821 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3822
3823 return &ret->root.root;
3824}
3825
cd1dac3d
DG		 3826/* Determine what kind of NOPs are available. */
3827
3828static bfd_boolean
3829arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3830{
3831 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3832 Tag_CPU_arch);
cd1dac3d 3833
60a019a0
TP		 3834 /* Force return logic to be reviewed for each new architecture. */
3835 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8
3836 || arch == TAG_CPU_ARCH_V8M_BASE
3837 || arch == TAG_CPU_ARCH_V8M_MAIN);
3838
3839 return (arch == TAG_CPU_ARCH_V6T2
3840 || arch == TAG_CPU_ARCH_V6K
3841 || arch == TAG_CPU_ARCH_V7
3842 || arch == TAG_CPU_ARCH_V8);
cd1dac3d
DG		 3843}
3844
f4ac8484
DJ		 3845static bfd_boolean
3846arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3847{
3848 switch (stub_type)
3849 {
fea2b4d6 3850 case arm_stub_long_branch_thumb_only:
80c135e5 3851 case arm_stub_long_branch_thumb2_only:
d5a67c02 3852 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 3853 case arm_stub_long_branch_v4t_thumb_arm:
3854 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3855 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3856 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3857 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 3858 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 3859 return TRUE;
3860 case arm_stub_none:
3861 BFD_FAIL ();
3862 return FALSE;
3863 break;
3864 default:
3865 return FALSE;
3866 }
3867}
3868
906e58ca
NC		 3869/* Determine the type of stub needed, if any, for a call. */
3870
3871static enum elf32_arm_stub_type
3872arm_type_of_stub (struct bfd_link_info *info,
3873 asection *input_sec,
3874 const Elf_Internal_Rela *rel,
34e77a92 3875 unsigned char st_type,
35fc36a8 3876 enum arm_st_branch_type *actual_branch_type,
906e58ca 3877 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3878 bfd_vma destination,
3879 asection *sym_sec,
3880 bfd *input_bfd,
3881 const char *name)
906e58ca
NC		 3882{
3883 bfd_vma location;
3884 bfd_signed_vma branch_offset;
3885 unsigned int r_type;
3886 struct elf32_arm_link_hash_table * globals;
5e866f5a 3887 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 3888 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3889 int use_plt = 0;
35fc36a8 3890 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3891 union gotplt_union *root_plt;
3892 struct arm_plt_info *arm_plt;
d5a67c02
AV		 3893 int arch;
3894 int thumb2_movw;
906e58ca 3895
35fc36a8 3896 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3897 return stub_type;
3898
906e58ca 3899 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3900 if (globals == NULL)
3901 return stub_type;
906e58ca
NC		 3902
3903 thumb_only = using_thumb_only (globals);
906e58ca 3904 thumb2 = using_thumb2 (globals);
5e866f5a 3905 thumb2_bl = using_thumb2_bl (globals);
906e58ca 3906
d5a67c02
AV		 3907 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3908
3909 /* True for architectures that implement the thumb2 movw instruction. */
3910 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
3911
906e58ca
NC		 3912 /* Determine where the call point is. */
3913 location = (input_sec->output_offset
3914 + input_sec->output_section->vma
3915 + rel->r_offset);
3916
906e58ca
NC		 3917 r_type = ELF32_R_TYPE (rel->r_info);
3918
39f21624
NC		 3919 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3920 are considering a function call relocation. */
c5423981
TG		 3921 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
3922 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3923 && branch_type == ST_BRANCH_TO_ARM)
3924 branch_type = ST_BRANCH_TO_THUMB;
3925
34e77a92
RS		 3926 /* For TLS call relocs, it is the caller's responsibility to provide
3927 the address of the appropriate trampoline. */
3928 if (r_type != R_ARM_TLS_CALL
3929 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 3930 && elf32_arm_get_plt_info (input_bfd, globals, hash,
3931 ELF32_R_SYM (rel->r_info), &root_plt,
3932 &arm_plt)
34e77a92 3933 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3934 {
34e77a92 3935 asection *splt;
fe33d2fa 3936
34e77a92
RS		 3937 if (hash == NULL || hash->is_iplt)
3938 splt = globals->root.iplt;
3939 else
3940 splt = globals->root.splt;
3941 if (splt != NULL)
b38cadfb 3942 {
34e77a92
RS		 3943 use_plt = 1;
3944
3945 /* Note when dealing with PLT entries: the main PLT stub is in
3946 ARM mode, so if the branch is in Thumb mode, another
3947 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 3948 PLT stub. If a long branch stub is needed, we'll add a
3949 Thumb->Arm one and branch directly to the ARM PLT entry.
3950 Here, we have to check if a pre-PLT Thumb->ARM stub
3951 is needed and if it will be close enough. */
34e77a92
RS		 3952
3953 destination = (splt->output_section->vma
3954 + splt->output_offset
3955 + root_plt->offset);
3956 st_type = STT_FUNC;
2df2751d
CL		 3957
3958 /* Thumb branch/call to PLT: it can become a branch to ARM
3959 or to Thumb. We must perform the same checks and
3960 corrections as in elf32_arm_final_link_relocate. */
3961 if ((r_type == R_ARM_THM_CALL)
3962 || (r_type == R_ARM_THM_JUMP24))
3963 {
3964 if (globals->use_blx
3965 && r_type == R_ARM_THM_CALL
3966 && !thumb_only)
3967 {
3968 /* If the Thumb BLX instruction is available, convert
3969 the BL to a BLX instruction to call the ARM-mode
3970 PLT entry. */
3971 branch_type = ST_BRANCH_TO_ARM;
3972 }
3973 else
3974 {
3975 if (!thumb_only)
3976 /* Target the Thumb stub before the ARM PLT entry. */
3977 destination -= PLT_THUMB_STUB_SIZE;
3978 branch_type = ST_BRANCH_TO_THUMB;
3979 }
3980 }
3981 else
3982 {
3983 branch_type = ST_BRANCH_TO_ARM;
3984 }
34e77a92 3985 }
5fa9e92f 3986 }
34e77a92
RS		 3987 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3988 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 3989
fe33d2fa
CL		 3990 branch_offset = (bfd_signed_vma)(destination - location);
3991
0855e32b 3992 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 3993 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 3994 {
5fa9e92f
CL		 3995 /* Handle cases where:
3996 - this call goes too far (different Thumb/Thumb2 max
99059e56 3997 distance)
155d87d7 3998 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 3999 Thumb->Arm branch (not bl). A stub is needed in this case,
4000 but only if this call is not through a PLT entry. Indeed,
4001 PLT stubs handle mode switching already.
5fa9e92f 4002 */
5e866f5a 4003 if ((!thumb2_bl
906e58ca
NC		 4004 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
4005 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 4006 || (thumb2_bl
906e58ca
NC		 4007 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4008 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4009 || (thumb2
4010 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4011 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4012 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4013 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4014 && (((r_type == R_ARM_THM_CALL
4015 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981
TG		 4016 || (r_type == R_ARM_THM_JUMP24)
4017 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4018 && !use_plt))
906e58ca 4019 {
2df2751d
CL		 4020 /* If we need to insert a Thumb-Thumb long branch stub to a
4021 PLT, use one that branches directly to the ARM PLT
4022 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4023 stub, undo this now. */
4024 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only) {
4025 branch_type = ST_BRANCH_TO_ARM;
4026 branch_offset += PLT_THUMB_STUB_SIZE;
4027 }
4028
35fc36a8 4029 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4030 {
4031 /* Thumb to thumb. */
4032 if (!thumb_only)
4033 {
d5a67c02
AV		 4034 if (input_sec->flags & SEC_ELF_PURECODE)
4035 (*_bfd_error_handler) (_("%B(%s): warning: long branch "
4036 " veneers used in section with "
4037 "SHF_ARM_PURECODE section "
4038 "attribute is only supported"
4039 " for M-profile targets that "
4040 "implement the movw "
4041 "instruction."));
4042
0e1862bb 4043 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4044 /* PIC stubs. */
155d87d7 4045 ? ((globals->use_blx
9553db3c 4046 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4047 /* V5T and above. Stub starts with ARM code, so
4048 we must be able to switch mode before
4049 reaching it, which is only possible for 'bl'
4050 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4051 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4052 /* On V4T, use Thumb code only. */
d3626fb0 4053 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4054
4055 /* non-PIC stubs. */
155d87d7 4056 : ((globals->use_blx
9553db3c 4057 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4058 /* V5T and above. */
4059 ? arm_stub_long_branch_any_any
4060 /* V4T. */
d3626fb0 4061 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4062 }
4063 else
4064 {
d5a67c02
AV		 4065 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4066 stub_type = arm_stub_long_branch_thumb2_only_pure;
4067 else
4068 {
4069 if (input_sec->flags & SEC_ELF_PURECODE)
4070 (*_bfd_error_handler) (_("%B(%s): warning: long branch "
4071 " veneers used in section with "
4072 "SHF_ARM_PURECODE section "
4073 "attribute is only supported"
4074 " for M-profile targets that "
4075 "implement the movw "
4076 "instruction."));
4077
4078 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4079 /* PIC stub. */
4080 ? arm_stub_long_branch_thumb_only_pic
4081 /* non-PIC stub. */
4082 : (thumb2 ? arm_stub_long_branch_thumb2_only
4083 : arm_stub_long_branch_thumb_only);
4084 }
906e58ca
NC		 4085 }
4086 }
4087 else
4088 {
d5a67c02
AV		 4089 if (input_sec->flags & SEC_ELF_PURECODE)
4090 (*_bfd_error_handler) (_("%B(%s): warning: long branch "
4091 " veneers used in section with "
4092 "SHF_ARM_PURECODE section "
4093 "attribute is only supported"
4094 " for M-profile targets that "
4095 "implement the movw "
4096 "instruction."));
4097
906e58ca 4098 /* Thumb to arm. */
c820be07
NC		 4099 if (sym_sec != NULL
4100 && sym_sec->owner != NULL
4101 && !INTERWORK_FLAG (sym_sec->owner))
4102 {
4103 (*_bfd_error_handler)
4104 (_("%B(%s): warning: interworking not enabled.\n"
4105 " first occurrence: %B: Thumb call to ARM"),
4106 sym_sec->owner, input_bfd, name);
4107 }
4108
0855e32b 4109 stub_type =
0e1862bb 4110 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4111 /* PIC stubs. */
0855e32b 4112 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4113 /* TLS PIC stubs. */
0855e32b
NS		 4114 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4115 : arm_stub_long_branch_v4t_thumb_tls_pic)
4116 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4117 /* V5T PIC and above. */
4118 ? arm_stub_long_branch_any_arm_pic
4119 /* V4T PIC stub. */
4120 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4121
4122 /* non-PIC stubs. */
0855e32b 4123 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4124 /* V5T and above. */
4125 ? arm_stub_long_branch_any_any
4126 /* V4T. */
4127 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4128
4129 /* Handle v4t short branches. */
fea2b4d6 4130 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4131 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4132 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4133 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4134 }
4135 }
4136 }
fe33d2fa
CL		 4137 else if (r_type == R_ARM_CALL
4138 || r_type == R_ARM_JUMP24
0855e32b
NS		 4139 || r_type == R_ARM_PLT32
4140 || r_type == R_ARM_TLS_CALL)
906e58ca 4141 {
d5a67c02
AV		 4142 if (input_sec->flags & SEC_ELF_PURECODE)
4143 (*_bfd_error_handler) (_("%B(%s): warning: long branch "
4144 " veneers used in section with "
4145 "SHF_ARM_PURECODE section "
4146 "attribute is only supported"
4147 " for M-profile targets that "
4148 "implement the movw "
4149 "instruction."));
35fc36a8 4150 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4151 {
4152 /* Arm to thumb. */
c820be07
NC		 4153
4154 if (sym_sec != NULL
4155 && sym_sec->owner != NULL
4156 && !INTERWORK_FLAG (sym_sec->owner))
4157 {
4158 (*_bfd_error_handler)
4159 (_("%B(%s): warning: interworking not enabled.\n"
c2b4a39d 4160 " first occurrence: %B: ARM call to Thumb"),
c820be07
NC		 4161 sym_sec->owner, input_bfd, name);
4162 }
4163
4164 /* We have an extra 2-bytes reach because of
4165 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4166 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4167 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4168 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4169 || (r_type == R_ARM_JUMP24)
4170 || (r_type == R_ARM_PLT32))
906e58ca 4171 {
0e1862bb 4172 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4173 /* PIC stubs. */
ebe24dd4
CL		 4174 ? ((globals->use_blx)
4175 /* V5T and above. */
4176 ? arm_stub_long_branch_any_thumb_pic
4177 /* V4T stub. */
4178 : arm_stub_long_branch_v4t_arm_thumb_pic)
4179
c2b4a39d
CL		 4180 /* non-PIC stubs. */
4181 : ((globals->use_blx)
4182 /* V5T and above. */
4183 ? arm_stub_long_branch_any_any
4184 /* V4T. */
4185 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4186 }
4187 }
4188 else
4189 {
4190 /* Arm to arm. */
4191 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4192 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4193 {
0855e32b 4194 stub_type =
0e1862bb 4195 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4196 /* PIC stubs. */
0855e32b 4197 ? (r_type == R_ARM_TLS_CALL
6a631e86 4198 /* TLS PIC Stub. */
0855e32b 4199 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4200 : (globals->nacl_p
4201 ? arm_stub_long_branch_arm_nacl_pic
4202 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4203 /* non-PIC stubs. */
7a89b94e
NC		 4204 : (globals->nacl_p
4205 ? arm_stub_long_branch_arm_nacl
4206 : arm_stub_long_branch_any_any);
906e58ca
NC		 4207 }
4208 }
4209 }
4210
fe33d2fa
CL		 4211 /* If a stub is needed, record the actual destination type. */
4212 if (stub_type != arm_stub_none)
35fc36a8 4213 *actual_branch_type = branch_type;
fe33d2fa 4214
906e58ca
NC		 4215 return stub_type;
4216}
4217
4218/* Build a name for an entry in the stub hash table. */
4219
4220static char *
4221elf32_arm_stub_name (const asection *input_section,
4222 const asection *sym_sec,
4223 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4224 const Elf_Internal_Rela *rel,
4225 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4226{
4227 char *stub_name;
4228 bfd_size_type len;
4229
4230 if (hash)
4231 {
fe33d2fa 4232 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4233 stub_name = (char *) bfd_malloc (len);
906e58ca 4234 if (stub_name != NULL)
fe33d2fa 4235 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4236 input_section->id & 0xffffffff,
4237 hash->root.root.root.string,
fe33d2fa
CL		 4238 (int) rel->r_addend & 0xffffffff,
4239 (int) stub_type);
906e58ca
NC		 4240 }
4241 else
4242 {
fe33d2fa 4243 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4244 stub_name = (char *) bfd_malloc (len);
906e58ca 4245 if (stub_name != NULL)
fe33d2fa 4246 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4247 input_section->id & 0xffffffff,
4248 sym_sec->id & 0xffffffff,
0855e32b
NS		 4249 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4250 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4251 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4252 (int) rel->r_addend & 0xffffffff,
4253 (int) stub_type);
906e58ca
NC		 4254 }
4255
4256 return stub_name;
4257}
4258
4259/* Look up an entry in the stub hash. Stub entries are cached because
4260 creating the stub name takes a bit of time. */
4261
4262static struct elf32_arm_stub_hash_entry *
4263elf32_arm_get_stub_entry (const asection *input_section,
4264 const asection *sym_sec,
4265 struct elf_link_hash_entry *hash,
4266 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4267 struct elf32_arm_link_hash_table *htab,
4268 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4269{
4270 struct elf32_arm_stub_hash_entry *stub_entry;
4271 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4272 const asection *id_sec;
4273
4274 if ((input_section->flags & SEC_CODE) == 0)
4275 return NULL;
4276
4277 /* If this input section is part of a group of sections sharing one
4278 stub section, then use the id of the first section in the group.
4279 Stub names need to include a section id, as there may well be
4280 more than one stub used to reach say, printf, and we need to
4281 distinguish between them. */
c2abbbeb 4282 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4283 id_sec = htab->stub_group[input_section->id].link_sec;
4284
4285 if (h != NULL && h->stub_cache != NULL
4286 && h->stub_cache->h == h
fe33d2fa
CL		 4287 && h->stub_cache->id_sec == id_sec
4288 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4289 {
4290 stub_entry = h->stub_cache;
4291 }
4292 else
4293 {
4294 char *stub_name;
4295
fe33d2fa 4296 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4297 if (stub_name == NULL)
4298 return NULL;
4299
4300 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4301 stub_name, FALSE, FALSE);
4302 if (h != NULL)
4303 h->stub_cache = stub_entry;
4304
4305 free (stub_name);
4306 }
4307
4308 return stub_entry;
4309}
4310
daa4adae
TP		 4311/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4312 section. */
4313
4314static bfd_boolean
4315arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4316{
4317 if (stub_type >= max_stub_type)
4318 abort (); /* Should be unreachable. */
4319
4ba2ef8f
TP		 4320 switch (stub_type)
4321 {
4322 case arm_stub_cmse_branch_thumb_only:
4323 return TRUE;
4324
4325 default:
4326 return FALSE;
4327 }
4328
4329 abort (); /* Should be unreachable. */
daa4adae
TP		 4330}
4331
4332/* Required alignment (as a power of 2) for the dedicated section holding
4333 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4334 with input sections. */
4335
4336static int
4337arm_dedicated_stub_output_section_required_alignment
4338 (enum elf32_arm_stub_type stub_type)
4339{
4340 if (stub_type >= max_stub_type)
4341 abort (); /* Should be unreachable. */
4342
4ba2ef8f
TP		 4343 switch (stub_type)
4344 {
4345 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4346 boundary. */
4347 case arm_stub_cmse_branch_thumb_only:
4348 return 5;
4349
4350 default:
4351 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4352 return 0;
4353 }
4354
4355 abort (); /* Should be unreachable. */
daa4adae
TP		 4356}
4357
4358/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4359 NULL if veneers of this type are interspersed with input sections. */
4360
4361static const char *
4362arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4363{
4364 if (stub_type >= max_stub_type)
4365 abort (); /* Should be unreachable. */
4366
4ba2ef8f
TP		 4367 switch (stub_type)
4368 {
4369 case arm_stub_cmse_branch_thumb_only:
4370 return ".gnu.sgstubs";
4371
4372 default:
4373 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4374 return NULL;
4375 }
4376
4377 abort (); /* Should be unreachable. */
daa4adae
TP		 4378}
4379
4380/* If veneers of type STUB_TYPE should go in a dedicated output section,
4381 returns the address of the hash table field in HTAB holding a pointer to the
4382 corresponding input section. Otherwise, returns NULL. */
4383
4384static asection **
4ba2ef8f
TP		 4385arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4386 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4387{
4388 if (stub_type >= max_stub_type)
4389 abort (); /* Should be unreachable. */
4390
4ba2ef8f
TP		 4391 switch (stub_type)
4392 {
4393 case arm_stub_cmse_branch_thumb_only:
4394 return &htab->cmse_stub_sec;
4395
4396 default:
4397 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4398 return NULL;
4399 }
4400
4401 abort (); /* Should be unreachable. */
daa4adae
TP		 4402}
4403
4404/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4405 is the section that branch into veneer and can be NULL if stub should go in
4406 a dedicated output section. Returns a pointer to the stub section, and the
4407 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4408 LINK_SEC_P may be NULL. */
906e58ca 4409
48229727
JB		 4410static asection *
4411elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4412 struct elf32_arm_link_hash_table *htab,
4413 enum elf32_arm_stub_type stub_type)
906e58ca 4414{
daa4adae
TP		 4415 asection *link_sec, *out_sec, **stub_sec_p;
4416 const char *stub_sec_prefix;
4417 bfd_boolean dedicated_output_section =
4418 arm_dedicated_stub_output_section_required (stub_type);
4419 int align;
906e58ca 4420
daa4adae 4421 if (dedicated_output_section)
906e58ca 4422 {
daa4adae
TP		 4423 bfd *output_bfd = htab->obfd;
4424 const char *out_sec_name =
4425 arm_dedicated_stub_output_section_name (stub_type);
4426 link_sec = NULL;
4427 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4428 stub_sec_prefix = out_sec_name;
4429 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4430 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4431 if (out_sec == NULL)
906e58ca 4432 {
daa4adae
TP		 4433 (*_bfd_error_handler) (_("No address assigned to the veneers output "
4434 "section %s"), out_sec_name);
4435 return NULL;
906e58ca 4436 }
daa4adae
TP		 4437 }
4438 else
4439 {
c2abbbeb 4440 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4441 link_sec = htab->stub_group[section->id].link_sec;
4442 BFD_ASSERT (link_sec != NULL);
4443 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4444 if (*stub_sec_p == NULL)
4445 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4446 stub_sec_prefix = link_sec->name;
4447 out_sec = link_sec->output_section;
4448 align = htab->nacl_p ? 4 : 3;
906e58ca 4449 }
b38cadfb 4450
daa4adae
TP		 4451 if (*stub_sec_p == NULL)
4452 {
4453 size_t namelen;
4454 bfd_size_type len;
4455 char *s_name;
4456
4457 namelen = strlen (stub_sec_prefix);
4458 len = namelen + sizeof (STUB_SUFFIX);
4459 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4460 if (s_name == NULL)
4461 return NULL;
4462
4463 memcpy (s_name, stub_sec_prefix, namelen);
4464 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4465 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4466 align);
4467 if (*stub_sec_p == NULL)
4468 return NULL;
4469
4470 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4471 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4472 | SEC_KEEP;
4473 }
4474
4475 if (!dedicated_output_section)
4476 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4477
48229727
JB		 4478 if (link_sec_p)
4479 *link_sec_p = link_sec;
b38cadfb 4480
daa4adae 4481 return *stub_sec_p;
48229727
JB		 4482}
4483
4484/* Add a new stub entry to the stub hash. Not all fields of the new
4485 stub entry are initialised. */
4486
4487static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4488elf32_arm_add_stub (const char *stub_name, asection *section,
4489 struct elf32_arm_link_hash_table *htab,
4490 enum elf32_arm_stub_type stub_type)
48229727
JB		 4491{
4492 asection *link_sec;
4493 asection *stub_sec;
4494 struct elf32_arm_stub_hash_entry *stub_entry;
4495
daa4adae
TP		 4496 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4497 stub_type);
48229727
JB		 4498 if (stub_sec == NULL)
4499 return NULL;
906e58ca
NC		 4500
4501 /* Enter this entry into the linker stub hash table. */
4502 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4503 TRUE, FALSE);
4504 if (stub_entry == NULL)
4505 {
6bde4c52
TP		 4506 if (section == NULL)
4507 section = stub_sec;
906e58ca
NC		 4508 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
4509 section->owner,
4510 stub_name);
4511 return NULL;
4512 }
4513
4514 stub_entry->stub_sec = stub_sec;
0955507f 4515 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4516 stub_entry->id_sec = link_sec;
4517
906e58ca
NC		 4518 return stub_entry;
4519}
4520
4521/* Store an Arm insn into an output section not processed by
4522 elf32_arm_write_section. */
4523
4524static void
8029a119
NC		 4525put_arm_insn (struct elf32_arm_link_hash_table * htab,
4526 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4527{
4528 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4529 bfd_putl32 (val, ptr);
4530 else
4531 bfd_putb32 (val, ptr);
4532}
4533
4534/* Store a 16-bit Thumb insn into an output section not processed by
4535 elf32_arm_write_section. */
4536
4537static void
8029a119
NC		 4538put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4539 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4540{
4541 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4542 bfd_putl16 (val, ptr);
4543 else
4544 bfd_putb16 (val, ptr);
4545}
4546
a504d23a
LA		 4547/* Store a Thumb2 insn into an output section not processed by
4548 elf32_arm_write_section. */
4549
4550static void
4551put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4552 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4553{
4554 /* T2 instructions are 16-bit streamed. */
4555 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4556 {
4557 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4558 bfd_putl16 ((val & 0xffff), ptr + 2);
4559 }
4560 else
4561 {
4562 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4563 bfd_putb16 ((val & 0xffff), ptr + 2);
4564 }
4565}
4566
0855e32b
NS		 4567/* If it's possible to change R_TYPE to a more efficient access
4568 model, return the new reloc type. */
4569
4570static unsigned
b38cadfb 4571elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4572 struct elf_link_hash_entry *h)
4573{
4574 int is_local = (h == NULL);
4575
0e1862bb
L		 4576 if (bfd_link_pic (info)
4577 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4578 return r_type;
4579
b38cadfb 4580 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4581 switch (r_type)
4582 {
4583 case R_ARM_TLS_GOTDESC:
4584 case R_ARM_TLS_CALL:
4585 case R_ARM_THM_TLS_CALL:
4586 case R_ARM_TLS_DESCSEQ:
4587 case R_ARM_THM_TLS_DESCSEQ:
4588 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4589 }
4590
4591 return r_type;
4592}
4593
48229727
JB		 4594static bfd_reloc_status_type elf32_arm_final_link_relocate
4595 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4596 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4597 const char *, unsigned char, enum arm_st_branch_type,
4598 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4599
4563a860
JB		 4600static unsigned int
4601arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4602{
4603 switch (stub_type)
4604 {
4605 case arm_stub_a8_veneer_b_cond:
4606 case arm_stub_a8_veneer_b:
4607 case arm_stub_a8_veneer_bl:
4608 return 2;
4609
4610 case arm_stub_long_branch_any_any:
4611 case arm_stub_long_branch_v4t_arm_thumb:
4612 case arm_stub_long_branch_thumb_only:
80c135e5 4613 case arm_stub_long_branch_thumb2_only:
d5a67c02 4614 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4615 case arm_stub_long_branch_v4t_thumb_thumb:
4616 case arm_stub_long_branch_v4t_thumb_arm:
4617 case arm_stub_short_branch_v4t_thumb_arm:
4618 case arm_stub_long_branch_any_arm_pic:
4619 case arm_stub_long_branch_any_thumb_pic:
4620 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4621 case arm_stub_long_branch_v4t_arm_thumb_pic:
4622 case arm_stub_long_branch_v4t_thumb_arm_pic:
4623 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4624 case arm_stub_long_branch_any_tls_pic:
4625 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4626 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4627 case arm_stub_a8_veneer_blx:
4628 return 4;
b38cadfb 4629
7a89b94e
NC		 4630 case arm_stub_long_branch_arm_nacl:
4631 case arm_stub_long_branch_arm_nacl_pic:
4632 return 16;
4633
4563a860
JB		 4634 default:
4635 abort (); /* Should be unreachable. */
4636 }
4637}
4638
4f4faa4d
TP		 4639/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4640 veneering (TRUE) or have their own symbol (FALSE). */
4641
4642static bfd_boolean
4643arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4644{
4645 if (stub_type >= max_stub_type)
4646 abort (); /* Should be unreachable. */
4647
4ba2ef8f
TP		 4648 switch (stub_type)
4649 {
4650 case arm_stub_cmse_branch_thumb_only:
4651 return TRUE;
4652
4653 default:
4654 return FALSE;
4655 }
4656
4657 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4658}
4659
d7c5bd02
TP		 4660/* Returns the padding needed for the dedicated section used stubs of type
4661 STUB_TYPE. */
4662
4663static int
4664arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4665{
4666 if (stub_type >= max_stub_type)
4667 abort (); /* Should be unreachable. */
4668
4ba2ef8f
TP		 4669 switch (stub_type)
4670 {
4671 case arm_stub_cmse_branch_thumb_only:
4672 return 32;
4673
4674 default:
4675 return 0;
4676 }
4677
4678 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4679}
4680
0955507f
TP		 4681/* If veneers of type STUB_TYPE should go in a dedicated output section,
4682 returns the address of the hash table field in HTAB holding the offset at
4683 which new veneers should be layed out in the stub section. */
4684
4685static bfd_vma*
4686arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
4687 enum elf32_arm_stub_type stub_type)
4688{
4689 switch (stub_type)
4690 {
4691 case arm_stub_cmse_branch_thumb_only:
4692 return &htab->new_cmse_stub_offset;
4693
4694 default:
4695 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4696 return NULL;
4697 }
4698}
4699
906e58ca
NC		 4700static bfd_boolean
4701arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4702 void * in_arg)
4703{
7a89b94e 4704#define MAXRELOCS 3
0955507f 4705 bfd_boolean removed_sg_veneer;
906e58ca 4706 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4707 struct elf32_arm_link_hash_table *globals;
906e58ca 4708 struct bfd_link_info *info;
906e58ca
NC		 4709 asection *stub_sec;
4710 bfd *stub_bfd;
906e58ca
NC		 4711 bfd_byte *loc;
4712 bfd_vma sym_value;
4713 int template_size;
4714 int size;
d3ce72d0 4715 const insn_sequence *template_sequence;
906e58ca 4716 int i;
48229727
JB		 4717 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4718 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4719 int nrelocs = 0;
0955507f 4720 int just_allocated = 0;
906e58ca
NC		 4721
4722 /* Massage our args to the form they really have. */
4723 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4724 info = (struct bfd_link_info *) in_arg;
4725
4726 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4727 if (globals == NULL)
4728 return FALSE;
906e58ca 4729
906e58ca
NC		 4730 stub_sec = stub_entry->stub_sec;
4731
4dfe6ac6 4732 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4733 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4734 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4735 return TRUE;
fe33d2fa 4736
0955507f
TP		 4737 /* Assign a slot at the end of section if none assigned yet. */
4738 if (stub_entry->stub_offset == (bfd_vma) -1)
4739 {
4740 stub_entry->stub_offset = stub_sec->size;
4741 just_allocated = 1;
4742 }
906e58ca
NC		 4743 loc = stub_sec->contents + stub_entry->stub_offset;
4744
4745 stub_bfd = stub_sec->owner;
4746
906e58ca
NC		 4747 /* This is the address of the stub destination. */
4748 sym_value = (stub_entry->target_value
4749 + stub_entry->target_section->output_offset
4750 + stub_entry->target_section->output_section->vma);
4751
d3ce72d0 4752 template_sequence = stub_entry->stub_template;
461a49ca 4753 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4754
4755 size = 0;
461a49ca 4756 for (i = 0; i < template_size; i++)
906e58ca 4757 {
d3ce72d0 4758 switch (template_sequence[i].type)
461a49ca
DJ		 4759 {
4760 case THUMB16_TYPE:
48229727 4761 {
d3ce72d0
NC		 4762 bfd_vma data = (bfd_vma) template_sequence[i].data;
4763 if (template_sequence[i].reloc_addend != 0)
48229727 4764 {
99059e56
RM		 4765 /* We've borrowed the reloc_addend field to mean we should
4766 insert a condition code into this (Thumb-1 branch)
4767 instruction. See THUMB16_BCOND_INSN. */
4768 BFD_ASSERT ((data & 0xff00) == 0xd000);
4769 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4770 }
fe33d2fa 4771 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4772 size += 2;
4773 }
461a49ca 4774 break;
906e58ca 4775
48229727 4776 case THUMB32_TYPE:
fe33d2fa
CL		 4777 bfd_put_16 (stub_bfd,
4778 (template_sequence[i].data >> 16) & 0xffff,
4779 loc + size);
4780 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4781 loc + size + 2);
99059e56
RM		 4782 if (template_sequence[i].r_type != R_ARM_NONE)
4783 {
4784 stub_reloc_idx[nrelocs] = i;
4785 stub_reloc_offset[nrelocs++] = size;
4786 }
4787 size += 4;
4788 break;
48229727 4789
461a49ca 4790 case ARM_TYPE:
fe33d2fa
CL		 4791 bfd_put_32 (stub_bfd, template_sequence[i].data,
4792 loc + size);
461a49ca
DJ		 4793 /* Handle cases where the target is encoded within the
4794 instruction. */
d3ce72d0 4795 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4796 {
48229727
JB		 4797 stub_reloc_idx[nrelocs] = i;
4798 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4799 }
4800 size += 4;
4801 break;
4802
4803 case DATA_TYPE:
d3ce72d0 4804 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4805 stub_reloc_idx[nrelocs] = i;
4806 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4807 size += 4;
4808 break;
4809
4810 default:
4811 BFD_FAIL ();
4812 return FALSE;
4813 }
906e58ca 4814 }
461a49ca 4815
0955507f
TP		 4816 if (just_allocated)
4817 stub_sec->size += size;
906e58ca 4818
461a49ca
DJ		 4819 /* Stub size has already been computed in arm_size_one_stub. Check
4820 consistency. */
4821 BFD_ASSERT (size == stub_entry->stub_size);
4822
906e58ca 4823 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4824 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4825 sym_value |= 1;
4826
0955507f
TP		 4827 /* Assume non empty slots have at least one and at most MAXRELOCS entries
4828 to relocate in each stub. */
4829 removed_sg_veneer =
4830 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
4831 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 4832
48229727 4833 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 4834 {
4835 Elf_Internal_Rela rel;
4836 bfd_boolean unresolved_reloc;
4837 char *error_message;
4838 bfd_vma points_to =
4839 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
4840
4841 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4842 rel.r_info = ELF32_R_INFO (0,
4843 template_sequence[stub_reloc_idx[i]].r_type);
4844 rel.r_addend = 0;
4845
4846 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4847 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4848 template should refer back to the instruction after the original
4849 branch. We use target_section as Cortex-A8 erratum workaround stubs
4850 are only generated when both source and target are in the same
4851 section. */
4852 points_to = stub_entry->target_section->output_section->vma
4853 + stub_entry->target_section->output_offset
4854 + stub_entry->source_value;
4855
4856 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4857 (template_sequence[stub_reloc_idx[i]].r_type),
4858 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
4859 points_to, info, stub_entry->target_section, "", STT_FUNC,
4860 stub_entry->branch_type,
4861 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4862 &error_message);
4863 }
906e58ca
NC		 4864
4865 return TRUE;
48229727 4866#undef MAXRELOCS
906e58ca
NC		 4867}
4868
48229727
JB		 4869/* Calculate the template, template size and instruction size for a stub.
4870 Return value is the instruction size. */
906e58ca 4871
48229727
JB		 4872static unsigned int
4873find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4874 const insn_sequence **stub_template,
4875 int *stub_template_size)
906e58ca 4876{
d3ce72d0 4877 const insn_sequence *template_sequence = NULL;
48229727
JB		 4878 int template_size = 0, i;
4879 unsigned int size;
906e58ca 4880
d3ce72d0 4881 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4882 if (stub_template)
4883 *stub_template = template_sequence;
4884
48229727 4885 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4886 if (stub_template_size)
4887 *stub_template_size = template_size;
906e58ca
NC		 4888
4889 size = 0;
461a49ca
DJ		 4890 for (i = 0; i < template_size; i++)
4891 {
d3ce72d0 4892 switch (template_sequence[i].type)
461a49ca
DJ		 4893 {
4894 case THUMB16_TYPE:
4895 size += 2;
4896 break;
4897
4898 case ARM_TYPE:
48229727 4899 case THUMB32_TYPE:
461a49ca
DJ		 4900 case DATA_TYPE:
4901 size += 4;
4902 break;
4903
4904 default:
4905 BFD_FAIL ();
2a229407 4906 return 0;
461a49ca
DJ		 4907 }
4908 }
4909
48229727
JB		 4910 return size;
4911}
4912
4913/* As above, but don't actually build the stub. Just bump offset so
4914 we know stub section sizes. */
4915
4916static bfd_boolean
4917arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4918 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4919{
4920 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4921 const insn_sequence *template_sequence;
48229727
JB		 4922 int template_size, size;
4923
4924 /* Massage our args to the form they really have. */
4925 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4926
4927 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4928 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4929
d3ce72d0 4930 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4931 &template_size);
4932
0955507f
TP		 4933 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
4934 if (stub_entry->stub_template_size)
4935 {
4936 stub_entry->stub_size = size;
4937 stub_entry->stub_template = template_sequence;
4938 stub_entry->stub_template_size = template_size;
4939 }
4940
4941 /* Already accounted for. */
4942 if (stub_entry->stub_offset != (bfd_vma) -1)
4943 return TRUE;
461a49ca 4944
906e58ca
NC		 4945 size = (size + 7) & ~7;
4946 stub_entry->stub_sec->size += size;
461a49ca 4947
906e58ca
NC		 4948 return TRUE;
4949}
4950
4951/* External entry points for sizing and building linker stubs. */
4952
4953/* Set up various things so that we can make a list of input sections
4954 for each output section included in the link. Returns -1 on error,
4955 0 when no stubs will be needed, and 1 on success. */
4956
4957int
4958elf32_arm_setup_section_lists (bfd *output_bfd,
4959 struct bfd_link_info *info)
4960{
4961 bfd *input_bfd;
4962 unsigned int bfd_count;
7292b3ac 4963 unsigned int top_id, top_index;
906e58ca
NC		 4964 asection *section;
4965 asection **input_list, **list;
4966 bfd_size_type amt;
4967 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4968
4dfe6ac6
NC		 4969 if (htab == NULL)
4970 return 0;
906e58ca
NC		 4971 if (! is_elf_hash_table (htab))
4972 return 0;
4973
4974 /* Count the number of input BFDs and find the top input section id. */
4975 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
4976 input_bfd != NULL;
c72f2fb2 4977 input_bfd = input_bfd->link.next)
906e58ca
NC		 4978 {
4979 bfd_count += 1;
4980 for (section = input_bfd->sections;
4981 section != NULL;
4982 section = section->next)
4983 {
4984 if (top_id < section->id)
4985 top_id = section->id;
4986 }
4987 }
4988 htab->bfd_count = bfd_count;
4989
4990 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 4991 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 4992 if (htab->stub_group == NULL)
4993 return -1;
fe33d2fa 4994 htab->top_id = top_id;
906e58ca
NC		 4995
4996 /* We can't use output_bfd->section_count here to find the top output
4997 section index as some sections may have been removed, and
4998 _bfd_strip_section_from_output doesn't renumber the indices. */
4999 for (section = output_bfd->sections, top_index = 0;
5000 section != NULL;
5001 section = section->next)
5002 {
5003 if (top_index < section->index)
5004 top_index = section->index;
5005 }
5006
5007 htab->top_index = top_index;
5008 amt = sizeof (asection *) * (top_index + 1);
21d799b5 5009 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 5010 htab->input_list = input_list;
5011 if (input_list == NULL)
5012 return -1;
5013
5014 /* For sections we aren't interested in, mark their entries with a
5015 value we can check later. */
5016 list = input_list + top_index;
5017 do
5018 *list = bfd_abs_section_ptr;
5019 while (list-- != input_list);
5020
5021 for (section = output_bfd->sections;
5022 section != NULL;
5023 section = section->next)
5024 {
5025 if ((section->flags & SEC_CODE) != 0)
5026 input_list[section->index] = NULL;
5027 }
5028
5029 return 1;
5030}
5031
5032/* The linker repeatedly calls this function for each input section,
5033 in the order that input sections are linked into output sections.
5034 Build lists of input sections to determine groupings between which
5035 we may insert linker stubs. */
5036
5037void
5038elf32_arm_next_input_section (struct bfd_link_info *info,
5039 asection *isec)
5040{
5041 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5042
4dfe6ac6
NC		 5043 if (htab == NULL)
5044 return;
5045
906e58ca
NC		 5046 if (isec->output_section->index <= htab->top_index)
5047 {
5048 asection **list = htab->input_list + isec->output_section->index;
5049
a7470592 5050 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5051 {
5052 /* Steal the link_sec pointer for our list. */
5053#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5054 /* This happens to make the list in reverse order,
07d72278 5055 which we reverse later. */
906e58ca
NC		 5056 PREV_SEC (isec) = *list;
5057 *list = isec;
5058 }
5059 }
5060}
5061
5062/* See whether we can group stub sections together. Grouping stub
5063 sections may result in fewer stubs. More importantly, we need to
07d72278 5064 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5065 .fini output sections respectively, because glibc splits the
5066 _init and _fini functions into multiple parts. Putting a stub in
5067 the middle of a function is not a good idea. */
5068
5069static void
5070group_sections (struct elf32_arm_link_hash_table *htab,
5071 bfd_size_type stub_group_size,
07d72278 5072 bfd_boolean stubs_always_after_branch)
906e58ca 5073{
07d72278 5074 asection **list = htab->input_list;
906e58ca
NC		 5075
5076 do
5077 {
5078 asection *tail = *list;
07d72278 5079 asection *head;
906e58ca
NC		 5080
5081 if (tail == bfd_abs_section_ptr)
5082 continue;
5083
07d72278
DJ		 5084 /* Reverse the list: we must avoid placing stubs at the
5085 beginning of the section because the beginning of the text
5086 section may be required for an interrupt vector in bare metal
5087 code. */
5088#define NEXT_SEC PREV_SEC
e780aef2
CL		 5089 head = NULL;
5090 while (tail != NULL)
99059e56
RM		 5091 {
5092 /* Pop from tail. */
5093 asection *item = tail;
5094 tail = PREV_SEC (item);
e780aef2 5095
99059e56
RM		 5096 /* Push on head. */
5097 NEXT_SEC (item) = head;
5098 head = item;
5099 }
07d72278
DJ		 5100
5101 while (head != NULL)
906e58ca
NC		 5102 {
5103 asection *curr;
07d72278 5104 asection *next;
e780aef2
CL		 5105 bfd_vma stub_group_start = head->output_offset;
5106 bfd_vma end_of_next;
906e58ca 5107
07d72278 5108 curr = head;
e780aef2 5109 while (NEXT_SEC (curr) != NULL)
8cd931b7 5110 {
e780aef2
CL		 5111 next = NEXT_SEC (curr);
5112 end_of_next = next->output_offset + next->size;
5113 if (end_of_next - stub_group_start >= stub_group_size)
5114 /* End of NEXT is too far from start, so stop. */
8cd931b7 5115 break;
e780aef2
CL		 5116 /* Add NEXT to the group. */
5117 curr = next;
8cd931b7 5118 }
906e58ca 5119
07d72278 5120 /* OK, the size from the start to the start of CURR is less
906e58ca 5121 than stub_group_size and thus can be handled by one stub
07d72278 5122 section. (Or the head section is itself larger than
906e58ca
NC		 5123 stub_group_size, in which case we may be toast.)
5124 We should really be keeping track of the total size of
5125 stubs added here, as stubs contribute to the final output
7fb9f789 5126 section size. */
906e58ca
NC		 5127 do
5128 {
07d72278 5129 next = NEXT_SEC (head);
906e58ca 5130 /* Set up this stub group. */
07d72278 5131 htab->stub_group[head->id].link_sec = curr;
906e58ca 5132 }
07d72278 5133 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5134
5135 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5136 bytes after the stub section can be handled by it too. */
5137 if (!stubs_always_after_branch)
906e58ca 5138 {
e780aef2
CL		 5139 stub_group_start = curr->output_offset + curr->size;
5140
8cd931b7 5141 while (next != NULL)
906e58ca 5142 {
e780aef2
CL		 5143 end_of_next = next->output_offset + next->size;
5144 if (end_of_next - stub_group_start >= stub_group_size)
5145 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5146 break;
e780aef2 5147 /* Add NEXT to the stub group. */
07d72278
DJ		 5148 head = next;
5149 next = NEXT_SEC (head);
5150 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5151 }
5152 }
07d72278 5153 head = next;
906e58ca
NC		 5154 }
5155 }
07d72278 5156 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5157
5158 free (htab->input_list);
5159#undef PREV_SEC
07d72278 5160#undef NEXT_SEC
906e58ca
NC		 5161}
5162
48229727
JB		 5163/* Comparison function for sorting/searching relocations relating to Cortex-A8
5164 erratum fix. */
5165
5166static int
5167a8_reloc_compare (const void *a, const void *b)
5168{
21d799b5
NC		 5169 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5170 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5171
5172 if (ra->from < rb->from)
5173 return -1;
5174 else if (ra->from > rb->from)
5175 return 1;
5176 else
5177 return 0;
5178}
5179
5180static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5181 const char *, char **);
5182
5183/* Helper function to scan code for sequences which might trigger the Cortex-A8
5184 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5185 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5186 otherwise. */
5187
81694485
NC		 5188static bfd_boolean
5189cortex_a8_erratum_scan (bfd *input_bfd,
5190 struct bfd_link_info *info,
48229727
JB		 5191 struct a8_erratum_fix **a8_fixes_p,
5192 unsigned int *num_a8_fixes_p,
5193 unsigned int *a8_fix_table_size_p,
5194 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5195 unsigned int num_a8_relocs,
5196 unsigned prev_num_a8_fixes,
5197 bfd_boolean *stub_changed_p)
48229727
JB		 5198{
5199 asection *section;
5200 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5201 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5202 unsigned int num_a8_fixes = *num_a8_fixes_p;
5203 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5204
4dfe6ac6
NC		 5205 if (htab == NULL)
5206 return FALSE;
5207
48229727
JB		 5208 for (section = input_bfd->sections;
5209 section != NULL;
5210 section = section->next)
5211 {
5212 bfd_byte *contents = NULL;
5213 struct _arm_elf_section_data *sec_data;
5214 unsigned int span;
5215 bfd_vma base_vma;
5216
5217 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5218 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5219 || (section->flags & SEC_EXCLUDE) != 0
5220 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5221 || (section->output_section == bfd_abs_section_ptr))
5222 continue;
48229727
JB		 5223
5224 base_vma = section->output_section->vma + section->output_offset;
5225
5226 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5227 contents = elf_section_data (section)->this_hdr.contents;
48229727 5228 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5229 return TRUE;
48229727
JB		 5230
5231 sec_data = elf32_arm_section_data (section);
5232
5233 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5234 {
5235 unsigned int span_start = sec_data->map[span].vma;
5236 unsigned int span_end = (span == sec_data->mapcount - 1)
5237 ? section->size : sec_data->map[span + 1].vma;
5238 unsigned int i;
5239 char span_type = sec_data->map[span].type;
5240 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5241
5242 if (span_type != 't')
5243 continue;
5244
5245 /* Span is entirely within a single 4KB region: skip scanning. */
5246 if (((base_vma + span_start) & ~0xfff)
48229727 5247 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5248 continue;
5249
5250 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5251
5252 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5253 * The branch target is in the same 4KB region as the
5254 first half of the branch.
5255 * The instruction before the branch is a 32-bit
5256 length non-branch instruction. */
5257 for (i = span_start; i < span_end;)
5258 {
5259 unsigned int insn = bfd_getl16 (&contents[i]);
5260 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5261 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5262
99059e56
RM		 5263 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5264 insn_32bit = TRUE;
48229727
JB		 5265
5266 if (insn_32bit)
99059e56
RM		 5267 {
5268 /* Load the rest of the insn (in manual-friendly order). */
5269 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5270
5271 /* Encoding T4: B<c>.W. */
5272 is_b = (insn & 0xf800d000) == 0xf0009000;
5273 /* Encoding T1: BL<c>.W. */
5274 is_bl = (insn & 0xf800d000) == 0xf000d000;
5275 /* Encoding T2: BLX<c>.W. */
5276 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5277 /* Encoding T3: B<c>.W (not permitted in IT block). */
5278 is_bcc = (insn & 0xf800d000) == 0xf0008000
5279 && (insn & 0x07f00000) != 0x03800000;
5280 }
5281
5282 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5283
99059e56 5284 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5285 && insn_32bit
5286 && is_32bit_branch
5287 && last_was_32bit
5288 && ! last_was_branch)
99059e56
RM		 5289 {
5290 bfd_signed_vma offset = 0;
5291 bfd_boolean force_target_arm = FALSE;
48229727 5292 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5293 bfd_vma target;
5294 enum elf32_arm_stub_type stub_type = arm_stub_none;
5295 struct a8_erratum_reloc key, *found;
5296 bfd_boolean use_plt = FALSE;
48229727 5297
99059e56
RM		 5298 key.from = base_vma + i;
5299 found = (struct a8_erratum_reloc *)
5300 bsearch (&key, a8_relocs, num_a8_relocs,
5301 sizeof (struct a8_erratum_reloc),
5302 &a8_reloc_compare);
48229727
JB		 5303
5304 if (found)
5305 {
5306 char *error_message = NULL;
5307 struct elf_link_hash_entry *entry;
5308
5309 /* We don't care about the error returned from this
99059e56 5310 function, only if there is glue or not. */
48229727
JB		 5311 entry = find_thumb_glue (info, found->sym_name,
5312 &error_message);
5313
5314 if (entry)
5315 found->non_a8_stub = TRUE;
5316
92750f34 5317 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5318 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5319 && found->hash->root.plt.offset != (bfd_vma) -1)
5320 use_plt = TRUE;
5321
5322 if (found->r_type == R_ARM_THM_CALL)
5323 {
35fc36a8
RS		 5324 if (found->branch_type == ST_BRANCH_TO_ARM
5325 || use_plt)
92750f34
DJ		 5326 force_target_arm = TRUE;
5327 else
5328 force_target_thumb = TRUE;
5329 }
48229727
JB		 5330 }
5331
99059e56 5332 /* Check if we have an offending branch instruction. */
48229727
JB		 5333
5334 if (found && found->non_a8_stub)
5335 /* We've already made a stub for this instruction, e.g.
5336 it's a long branch or a Thumb->ARM stub. Assume that
5337 stub will suffice to work around the A8 erratum (see
5338 setting of always_after_branch above). */
5339 ;
99059e56
RM		 5340 else if (is_bcc)
5341 {
5342 offset = (insn & 0x7ff) << 1;
5343 offset |= (insn & 0x3f0000) >> 4;
5344 offset |= (insn & 0x2000) ? 0x40000 : 0;
5345 offset |= (insn & 0x800) ? 0x80000 : 0;
5346 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5347 if (offset & 0x100000)
5348 offset |= ~ ((bfd_signed_vma) 0xfffff);
5349 stub_type = arm_stub_a8_veneer_b_cond;
5350 }
5351 else if (is_b || is_bl || is_blx)
5352 {
5353 int s = (insn & 0x4000000) != 0;
5354 int j1 = (insn & 0x2000) != 0;
5355 int j2 = (insn & 0x800) != 0;
5356 int i1 = !(j1 ^ s);
5357 int i2 = !(j2 ^ s);
5358
5359 offset = (insn & 0x7ff) << 1;
5360 offset |= (insn & 0x3ff0000) >> 4;
5361 offset |= i2 << 22;
5362 offset |= i1 << 23;
5363 offset |= s << 24;
5364 if (offset & 0x1000000)
5365 offset |= ~ ((bfd_signed_vma) 0xffffff);
5366
5367 if (is_blx)
5368 offset &= ~ ((bfd_signed_vma) 3);
5369
5370 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5371 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5372 }
5373
5374 if (stub_type != arm_stub_none)
5375 {
5376 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5377
5378 /* The original instruction is a BL, but the target is
99059e56 5379 an ARM instruction. If we were not making a stub,
48229727
JB		 5380 the BL would have been converted to a BLX. Use the
5381 BLX stub instead in that case. */
5382 if (htab->use_blx && force_target_arm
5383 && stub_type == arm_stub_a8_veneer_bl)
5384 {
5385 stub_type = arm_stub_a8_veneer_blx;
5386 is_blx = TRUE;
5387 is_bl = FALSE;
5388 }
5389 /* Conversely, if the original instruction was
5390 BLX but the target is Thumb mode, use the BL
5391 stub. */
5392 else if (force_target_thumb
5393 && stub_type == arm_stub_a8_veneer_blx)
5394 {
5395 stub_type = arm_stub_a8_veneer_bl;
5396 is_blx = FALSE;
5397 is_bl = TRUE;
5398 }
5399
99059e56
RM		 5400 if (is_blx)
5401 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5402
99059e56
RM		 5403 /* If we found a relocation, use the proper destination,
5404 not the offset in the (unrelocated) instruction.
48229727
JB		 5405 Note this is always done if we switched the stub type
5406 above. */
99059e56
RM		 5407 if (found)
5408 offset =
81694485 5409 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5410
99059e56
RM		 5411 /* If the stub will use a Thumb-mode branch to a
5412 PLT target, redirect it to the preceding Thumb
5413 entry point. */
5414 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5415 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5416
99059e56 5417 target = pc_for_insn + offset;
48229727 5418
99059e56
RM		 5419 /* The BLX stub is ARM-mode code. Adjust the offset to
5420 take the different PC value (+8 instead of +4) into
48229727 5421 account. */
99059e56
RM		 5422 if (stub_type == arm_stub_a8_veneer_blx)
5423 offset += 4;
5424
5425 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5426 {
5427 char *stub_name = NULL;
5428
5429 if (num_a8_fixes == a8_fix_table_size)
5430 {
5431 a8_fix_table_size *= 2;
5432 a8_fixes = (struct a8_erratum_fix *)
5433 bfd_realloc (a8_fixes,
5434 sizeof (struct a8_erratum_fix)
5435 * a8_fix_table_size);
5436 }
48229727 5437
eb7c4339
NS		 5438 if (num_a8_fixes < prev_num_a8_fixes)
5439 {
5440 /* If we're doing a subsequent scan,
5441 check if we've found the same fix as
5442 before, and try and reuse the stub
5443 name. */
5444 stub_name = a8_fixes[num_a8_fixes].stub_name;
5445 if ((a8_fixes[num_a8_fixes].section != section)
5446 || (a8_fixes[num_a8_fixes].offset != i))
5447 {
5448 free (stub_name);
5449 stub_name = NULL;
5450 *stub_changed_p = TRUE;
5451 }
5452 }
5453
5454 if (!stub_name)
5455 {
21d799b5 5456 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5457 if (stub_name != NULL)
5458 sprintf (stub_name, "%x:%x", section->id, i);
5459 }
48229727 5460
99059e56
RM		 5461 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5462 a8_fixes[num_a8_fixes].section = section;
5463 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5464 a8_fixes[num_a8_fixes].target_offset =
5465 target - base_vma;
99059e56
RM		 5466 a8_fixes[num_a8_fixes].orig_insn = insn;
5467 a8_fixes[num_a8_fixes].stub_name = stub_name;
5468 a8_fixes[num_a8_fixes].stub_type = stub_type;
5469 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5470 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5471
99059e56
RM		 5472 num_a8_fixes++;
5473 }
5474 }
5475 }
48229727 5476
99059e56
RM		 5477 i += insn_32bit ? 4 : 2;
5478 last_was_32bit = insn_32bit;
48229727 5479 last_was_branch = is_32bit_branch;
99059e56
RM		 5480 }
5481 }
48229727
JB		 5482
5483 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5484 free (contents);
48229727 5485 }
fe33d2fa 5486
48229727
JB		 5487 *a8_fixes_p = a8_fixes;
5488 *num_a8_fixes_p = num_a8_fixes;
5489 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5490
81694485 5491 return FALSE;
48229727
JB		 5492}
5493
b715f643
TP		 5494/* Create or update a stub entry depending on whether the stub can already be
5495 found in HTAB. The stub is identified by:
5496 - its type STUB_TYPE
5497 - its source branch (note that several can share the same stub) whose
5498 section and relocation (if any) are given by SECTION and IRELA
5499 respectively
5500 - its target symbol whose input section, hash, name, value and branch type
5501 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5502 respectively
5503
5504 If found, the value of the stub's target symbol is updated from SYM_VALUE
5505 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5506 TRUE and the stub entry is initialized.
5507
0955507f
TP		 5508 Returns the stub that was created or updated, or NULL if an error
5509 occurred. */
b715f643 5510
0955507f 5511static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5512elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5513 enum elf32_arm_stub_type stub_type, asection *section,
5514 Elf_Internal_Rela *irela, asection *sym_sec,
5515 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5516 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5517 bfd_boolean *new_stub)
5518{
5519 const asection *id_sec;
5520 char *stub_name;
5521 struct elf32_arm_stub_hash_entry *stub_entry;
5522 unsigned int r_type;
4f4faa4d 5523 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5524
5525 BFD_ASSERT (stub_type != arm_stub_none);
5526 *new_stub = FALSE;
5527
4f4faa4d
TP		 5528 if (sym_claimed)
5529 stub_name = sym_name;
5530 else
5531 {
5532 BFD_ASSERT (irela);
5533 BFD_ASSERT (section);
c2abbbeb 5534 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5535
4f4faa4d
TP		 5536 /* Support for grouping stub sections. */
5537 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5538
4f4faa4d
TP		 5539 /* Get the name of this stub. */
5540 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5541 stub_type);
5542 if (!stub_name)
0955507f 5543 return NULL;
4f4faa4d 5544 }
b715f643
TP		 5545
5546 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5547 FALSE);
5548 /* The proper stub has already been created, just update its value. */
5549 if (stub_entry != NULL)
5550 {
4f4faa4d
TP		 5551 if (!sym_claimed)
5552 free (stub_name);
b715f643 5553 stub_entry->target_value = sym_value;
0955507f 5554 return stub_entry;
b715f643
TP		 5555 }
5556
daa4adae 5557 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5558 if (stub_entry == NULL)
5559 {
4f4faa4d
TP		 5560 if (!sym_claimed)
5561 free (stub_name);
0955507f 5562 return NULL;
b715f643
TP		 5563 }
5564
5565 stub_entry->target_value = sym_value;
5566 stub_entry->target_section = sym_sec;
5567 stub_entry->stub_type = stub_type;
5568 stub_entry->h = hash;
5569 stub_entry->branch_type = branch_type;
5570
4f4faa4d
TP		 5571 if (sym_claimed)
5572 stub_entry->output_name = sym_name;
5573 else
b715f643 5574 {
4f4faa4d
TP		 5575 if (sym_name == NULL)
5576 sym_name = "unnamed";
5577 stub_entry->output_name = (char *)
5578 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5579 + strlen (sym_name));
5580 if (stub_entry->output_name == NULL)
5581 {
5582 free (stub_name);
0955507f 5583 return NULL;
4f4faa4d 5584 }
b715f643 5585
4f4faa4d
TP		 5586 /* For historical reasons, use the existing names for ARM-to-Thumb and
5587 Thumb-to-ARM stubs. */
5588 r_type = ELF32_R_TYPE (irela->r_info);
5589 if ((r_type == (unsigned int) R_ARM_THM_CALL
5590 || r_type == (unsigned int) R_ARM_THM_JUMP24
5591 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5592 && branch_type == ST_BRANCH_TO_ARM)
5593 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5594 else if ((r_type == (unsigned int) R_ARM_CALL
5595 || r_type == (unsigned int) R_ARM_JUMP24)
5596 && branch_type == ST_BRANCH_TO_THUMB)
5597 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5598 else
5599 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5600 }
b715f643
TP		 5601
5602 *new_stub = TRUE;
0955507f 5603 return stub_entry;
b715f643
TP		 5604}
5605
4ba2ef8f
TP		 5606/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5607 gateway veneer to transition from non secure to secure state and create them
5608 accordingly.
5609
5610 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5611 defines the conditions that govern Secure Gateway veneer creation for a
5612 given symbol <SYM> as follows:
5613 - it has function type
5614 - it has non local binding
5615 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5616 same type, binding and value as <SYM> (called normal symbol).
5617 An entry function can handle secure state transition itself in which case
5618 its special symbol would have a different value from the normal symbol.
5619
5620 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5621 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5622 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5623 created.
4ba2ef8f 5624
0955507f 5625 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5626
5627static bfd_boolean
5628cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5629 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5630 int *cmse_stub_created)
4ba2ef8f
TP		 5631{
5632 const struct elf_backend_data *bed;
5633 Elf_Internal_Shdr *symtab_hdr;
5634 unsigned i, j, sym_count, ext_start;
5635 Elf_Internal_Sym *cmse_sym, *local_syms;
5636 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5637 enum arm_st_branch_type branch_type;
5638 char *sym_name, *lsym_name;
5639 bfd_vma sym_value;
5640 asection *section;
0955507f
TP		 5641 struct elf32_arm_stub_hash_entry *stub_entry;
5642 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5643
5644 bed = get_elf_backend_data (input_bfd);
5645 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5646 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5647 ext_start = symtab_hdr->sh_info;
5648 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5649 && out_attr[Tag_CPU_arch_profile].i == 'M');
5650
5651 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5652 if (local_syms == NULL)
5653 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5654 symtab_hdr->sh_info, 0, NULL, NULL,
5655 NULL);
5656 if (symtab_hdr->sh_info && local_syms == NULL)
5657 return FALSE;
5658
5659 /* Scan symbols. */
5660 for (i = 0; i < sym_count; i++)
5661 {
5662 cmse_invalid = FALSE;
5663
5664 if (i < ext_start)
5665 {
5666 cmse_sym = &local_syms[i];
5667 /* Not a special symbol. */
5668 if (!ARM_GET_SYM_CMSE_SPCL (cmse_sym->st_target_internal))
5669 continue;
5670 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5671 symtab_hdr->sh_link,
5672 cmse_sym->st_name);
5673 /* Special symbol with local binding. */
5674 cmse_invalid = TRUE;
5675 }
5676 else
5677 {
5678 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5679 sym_name = (char *) cmse_hash->root.root.root.string;
5680
5681 /* Not a special symbol. */
5682 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
5683 continue;
5684
5685 /* Special symbol has incorrect binding or type. */
5686 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5687 && cmse_hash->root.root.type != bfd_link_hash_defweak)
5688 || cmse_hash->root.type != STT_FUNC)
5689 cmse_invalid = TRUE;
5690 }
5691
5692 if (!is_v8m)
5693 {
5694 (*_bfd_error_handler) (_("%B: Special symbol `%s' only allowed for "
5695 "ARMv8-M architecture or later."),
5696 input_bfd, sym_name);
5697 is_v8m = TRUE; /* Avoid multiple warning. */
5698 ret = FALSE;
5699 }
5700
5701 if (cmse_invalid)
5702 {
5703 (*_bfd_error_handler) (_("%B: invalid special symbol `%s'."),
5704 input_bfd, sym_name);
5705 (*_bfd_error_handler) (_("It must be a global or weak function "
5706 "symbol."));
5707 ret = FALSE;
5708 if (i < ext_start)
5709 continue;
5710 }
5711
5712 sym_name += strlen (CMSE_PREFIX);
5713 hash = (struct elf32_arm_link_hash_entry *)
5714 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5715
5716 /* No associated normal symbol or it is neither global nor weak. */
5717 if (!hash
5718 || (hash->root.root.type != bfd_link_hash_defined
5719 && hash->root.root.type != bfd_link_hash_defweak)
5720 || hash->root.type != STT_FUNC)
5721 {
5722 /* Initialize here to avoid warning about use of possibly
5723 uninitialized variable. */
5724 j = 0;
5725
5726 if (!hash)
5727 {
5728 /* Searching for a normal symbol with local binding. */
5729 for (; j < ext_start; j++)
5730 {
5731 lsym_name =
5732 bfd_elf_string_from_elf_section (input_bfd,
5733 symtab_hdr->sh_link,
5734 local_syms[j].st_name);
5735 if (!strcmp (sym_name, lsym_name))
5736 break;
5737 }
5738 }
5739
5740 if (hash || j < ext_start)
5741 {
5742 (*_bfd_error_handler)
5743 (_("%B: invalid standard symbol `%s'."), input_bfd, sym_name);
5744 (*_bfd_error_handler)
5745 (_("It must be a global or weak function symbol."));
5746 }
5747 else
5748 (*_bfd_error_handler)
5749 (_("%B: absent standard symbol `%s'."), input_bfd, sym_name);
5750 ret = FALSE;
5751 if (!hash)
5752 continue;
5753 }
5754
5755 sym_value = hash->root.root.u.def.value;
5756 section = hash->root.root.u.def.section;
5757
5758 if (cmse_hash->root.root.u.def.section != section)
5759 {
5760 (*_bfd_error_handler)
5761 (_("%B: `%s' and its special symbol are in different sections."),
5762 input_bfd, sym_name);
5763 ret = FALSE;
5764 }
5765 if (cmse_hash->root.root.u.def.value != sym_value)
5766 continue; /* Ignore: could be an entry function starting with SG. */
5767
5768 /* If this section is a link-once section that will be discarded, then
5769 don't create any stubs. */
5770 if (section->output_section == NULL)
5771 {
5772 (*_bfd_error_handler)
5773 (_("%B: entry function `%s' not output."), input_bfd, sym_name);
5774 continue;
5775 }
5776
5777 if (hash->root.size == 0)
5778 {
5779 (*_bfd_error_handler)
5780 (_("%B: entry function `%s' is empty."), input_bfd, sym_name);
5781 ret = FALSE;
5782 }
5783
5784 if (!ret)
5785 continue;
5786 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 5787 stub_entry
4ba2ef8f
TP		 5788 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5789 NULL, NULL, section, hash, sym_name,
5790 sym_value, branch_type, &new_stub);
5791
0955507f 5792 if (stub_entry == NULL)
4ba2ef8f
TP		 5793 ret = FALSE;
5794 else
5795 {
5796 BFD_ASSERT (new_stub);
0955507f 5797 (*cmse_stub_created)++;
4ba2ef8f
TP		 5798 }
5799 }
5800
5801 if (!symtab_hdr->contents)
5802 free (local_syms);
5803 return ret;
5804}
5805
0955507f
TP		 5806/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
5807 code entry function, ie can be called from non secure code without using a
5808 veneer. */
5809
5810static bfd_boolean
5811cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
5812{
42484486 5813 bfd_byte contents[4];
0955507f
TP		 5814 uint32_t first_insn;
5815 asection *section;
5816 file_ptr offset;
5817 bfd *abfd;
5818
5819 /* Defined symbol of function type. */
5820 if (hash->root.root.type != bfd_link_hash_defined
5821 && hash->root.root.type != bfd_link_hash_defweak)
5822 return FALSE;
5823 if (hash->root.type != STT_FUNC)
5824 return FALSE;
5825
5826 /* Read first instruction. */
5827 section = hash->root.root.u.def.section;
5828 abfd = section->owner;
5829 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 5830 if (!bfd_get_section_contents (abfd, section, contents, offset,
5831 sizeof (contents)))
0955507f
TP		 5832 return FALSE;
5833
42484486
TP		 5834 first_insn = bfd_get_32 (abfd, contents);
5835
5836 /* Starts by SG instruction. */
0955507f
TP		 5837 return first_insn == 0xe97fe97f;
5838}
5839
5840/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
5841 secure gateway veneers (ie. the veneers was not in the input import library)
5842 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
5843
5844static bfd_boolean
5845arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
5846{
5847 struct elf32_arm_stub_hash_entry *stub_entry;
5848 struct bfd_link_info *info;
5849
5850 /* Massage our args to the form they really have. */
5851 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5852 info = (struct bfd_link_info *) gen_info;
5853
5854 if (info->out_implib_bfd)
5855 return TRUE;
5856
5857 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
5858 return TRUE;
5859
5860 if (stub_entry->stub_offset == (bfd_vma) -1)
5861 (*_bfd_error_handler) (" %s", stub_entry->output_name);
5862
5863 return TRUE;
5864}
5865
5866/* Set offset of each secure gateway veneers so that its address remain
5867 identical to the one in the input import library referred by
5868 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
5869 (present in input import library but absent from the executable being
5870 linked) or if new veneers appeared and there is no output import library
5871 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
5872 number of secure gateway veneers found in the input import library.
5873
5874 The function returns whether an error occurred. If no error occurred,
5875 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
5876 and this function and HTAB->new_cmse_stub_offset is set to the biggest
5877 veneer observed set for new veneers to be layed out after. */
5878
5879static bfd_boolean
5880set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
5881 struct elf32_arm_link_hash_table *htab,
5882 int *cmse_stub_created)
5883{
5884 long symsize;
5885 char *sym_name;
5886 flagword flags;
5887 long i, symcount;
5888 bfd *in_implib_bfd;
5889 asection *stub_out_sec;
5890 bfd_boolean ret = TRUE;
5891 Elf_Internal_Sym *intsym;
5892 const char *out_sec_name;
5893 bfd_size_type cmse_stub_size;
5894 asymbol **sympp = NULL, *sym;
5895 struct elf32_arm_link_hash_entry *hash;
5896 const insn_sequence *cmse_stub_template;
5897 struct elf32_arm_stub_hash_entry *stub_entry;
5898 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
5899 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
5900 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
5901
5902 /* No input secure gateway import library. */
5903 if (!htab->in_implib_bfd)
5904 return TRUE;
5905
5906 in_implib_bfd = htab->in_implib_bfd;
5907 if (!htab->cmse_implib)
5908 {
5909 (*_bfd_error_handler) (_("%B: --in-implib only supported for Secure "
5910 "Gateway import libraries."), in_implib_bfd);
5911 return FALSE;
5912 }
5913
5914 /* Get symbol table size. */
5915 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
5916 if (symsize < 0)
5917 return FALSE;
5918
5919 /* Read in the input secure gateway import library's symbol table. */
5920 sympp = (asymbol **) xmalloc (symsize);
5921 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
5922 if (symcount < 0)
5923 {
5924 ret = FALSE;
5925 goto free_sym_buf;
5926 }
5927
5928 htab->new_cmse_stub_offset = 0;
5929 cmse_stub_size =
5930 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
5931 &cmse_stub_template,
5932 &cmse_stub_template_size);
5933 out_sec_name =
5934 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
5935 stub_out_sec =
5936 bfd_get_section_by_name (htab->obfd, out_sec_name);
5937 if (stub_out_sec != NULL)
5938 cmse_stub_sec_vma = stub_out_sec->vma;
5939
5940 /* Set addresses of veneers mentionned in input secure gateway import
5941 library's symbol table. */
5942 for (i = 0; i < symcount; i++)
5943 {
5944 sym = sympp[i];
5945 flags = sym->flags;
5946 sym_name = (char *) bfd_asymbol_name (sym);
5947 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
5948
5949 if (sym->section != bfd_abs_section_ptr
5950 || !(flags & (BSF_GLOBAL | BSF_WEAK))
5951 || (flags & BSF_FUNCTION) != BSF_FUNCTION
5952 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
5953 != ST_BRANCH_TO_THUMB))
5954 {
5955 (*_bfd_error_handler) (_("%B: invalid import library entry: `%s'."),
5956 in_implib_bfd, sym_name);
5957 (*_bfd_error_handler) (_("Symbol should be absolute, global and "
5958 "refer to Thumb functions."));
5959 ret = FALSE;
5960 continue;
5961 }
5962
5963 veneer_value = bfd_asymbol_value (sym);
5964 stub_offset = veneer_value - cmse_stub_sec_vma;
5965 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
5966 FALSE, FALSE);
5967 hash = (struct elf32_arm_link_hash_entry *)
5968 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5969
5970 /* Stub entry should have been created by cmse_scan or the symbol be of
5971 a secure function callable from non secure code. */
5972 if (!stub_entry && !hash)
5973 {
5974 bfd_boolean new_stub;
5975
5976 (*_bfd_error_handler)
5977 (_("Entry function `%s' disappeared from secure code."), sym_name);
5978 hash = (struct elf32_arm_link_hash_entry *)
5979 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
5980 stub_entry
5981 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5982 NULL, NULL, bfd_abs_section_ptr, hash,
5983 sym_name, veneer_value,
5984 ST_BRANCH_TO_THUMB, &new_stub);
5985 if (stub_entry == NULL)
5986 ret = FALSE;
5987 else
5988 {
5989 BFD_ASSERT (new_stub);
5990 new_cmse_stubs_created++;
5991 (*cmse_stub_created)++;
5992 }
5993 stub_entry->stub_template_size = stub_entry->stub_size = 0;
5994 stub_entry->stub_offset = stub_offset;
5995 }
5996 /* Symbol found is not callable from non secure code. */
5997 else if (!stub_entry)
5998 {
5999 if (!cmse_entry_fct_p (hash))
6000 {
6001 (*_bfd_error_handler) (_("`%s' refers to a non entry function."),
6002 sym_name);
6003 ret = FALSE;
6004 }
6005 continue;
6006 }
6007 else
6008 {
6009 /* Only stubs for SG veneers should have been created. */
6010 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
6011
6012 /* Check visibility hasn't changed. */
6013 if (!!(flags & BSF_GLOBAL)
6014 != (hash->root.root.type == bfd_link_hash_defined))
6015 (*_bfd_error_handler)
6016 (_("%B: visibility of symbol `%s' has changed."), in_implib_bfd,
6017 sym_name);
6018
6019 stub_entry->stub_offset = stub_offset;
6020 }
6021
6022 /* Size should match that of a SG veneer. */
6023 if (intsym->st_size != cmse_stub_size)
6024 {
6025 (*_bfd_error_handler) (_("%B: incorrect size for symbol `%s'."),
6026 in_implib_bfd, sym_name);
6027 ret = FALSE;
6028 }
6029
6030 /* Previous veneer address is before current SG veneer section. */
6031 if (veneer_value < cmse_stub_sec_vma)
6032 {
6033 /* Avoid offset underflow. */
6034 if (stub_entry)
6035 stub_entry->stub_offset = 0;
6036 stub_offset = 0;
6037 ret = FALSE;
6038 }
6039
6040 /* Complain if stub offset not a multiple of stub size. */
6041 if (stub_offset % cmse_stub_size)
6042 {
6043 (*_bfd_error_handler)
6044 (_("Offset of veneer for entry function `%s' not a multiple of "
6045 "its size."), sym_name);
6046 ret = FALSE;
6047 }
6048
6049 if (!ret)
6050 continue;
6051
6052 new_cmse_stubs_created--;
6053 if (veneer_value < cmse_stub_array_start)
6054 cmse_stub_array_start = veneer_value;
6055 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6056 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6057 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6058 }
6059
6060 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6061 {
6062 BFD_ASSERT (new_cmse_stubs_created > 0);
6063 (*_bfd_error_handler)
6064 (_("new entry function(s) introduced but no output import library "
6065 "specified:"));
6066 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6067 }
6068
6069 if (cmse_stub_array_start != cmse_stub_sec_vma)
6070 {
6071 (*_bfd_error_handler)
6072 (_("Start address of `%s' is different from previous link."),
6073 out_sec_name);
6074 ret = FALSE;
6075 }
6076
6077free_sym_buf:
6078 free (sympp);
6079 return ret;
6080}
6081
906e58ca
NC		 6082/* Determine and set the size of the stub section for a final link.
6083
6084 The basic idea here is to examine all the relocations looking for
6085 PC-relative calls to a target that is unreachable with a "bl"
6086 instruction. */
6087
6088bfd_boolean
6089elf32_arm_size_stubs (bfd *output_bfd,
6090 bfd *stub_bfd,
6091 struct bfd_link_info *info,
6092 bfd_signed_vma group_size,
7a89b94e 6093 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6094 asection *,
7a89b94e 6095 unsigned int),
906e58ca
NC		 6096 void (*layout_sections_again) (void))
6097{
0955507f 6098 bfd_boolean ret = TRUE;
4ba2ef8f 6099 obj_attribute *out_attr;
0955507f 6100 int cmse_stub_created = 0;
906e58ca 6101 bfd_size_type stub_group_size;
4ba2ef8f 6102 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6103 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6104 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6105 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6106 struct a8_erratum_reloc *a8_relocs = NULL;
6107 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6108
4dfe6ac6
NC		 6109 if (htab == NULL)
6110 return FALSE;
6111
48229727
JB		 6112 if (htab->fix_cortex_a8)
6113 {
21d799b5 6114 a8_fixes = (struct a8_erratum_fix *)
99059e56 6115 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6116 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6117 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6118 }
906e58ca
NC		 6119
6120 /* Propagate mach to stub bfd, because it may not have been
6121 finalized when we created stub_bfd. */
6122 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6123 bfd_get_mach (output_bfd));
6124
6125 /* Stash our params away. */
6126 htab->stub_bfd = stub_bfd;
6127 htab->add_stub_section = add_stub_section;
6128 htab->layout_sections_again = layout_sections_again;
07d72278 6129 stubs_always_after_branch = group_size < 0;
48229727 6130
4ba2ef8f
TP		 6131 out_attr = elf_known_obj_attributes_proc (output_bfd);
6132 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6133
48229727
JB		 6134 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6135 as the first half of a 32-bit branch straddling two 4K pages. This is a
6136 crude way of enforcing that. */
6137 if (htab->fix_cortex_a8)
6138 stubs_always_after_branch = 1;
6139
906e58ca
NC		 6140 if (group_size < 0)
6141 stub_group_size = -group_size;
6142 else
6143 stub_group_size = group_size;
6144
6145 if (stub_group_size == 1)
6146 {
6147 /* Default values. */
6148 /* Thumb branch range is +-4MB has to be used as the default
6149 maximum size (a given section can contain both ARM and Thumb
6150 code, so the worst case has to be taken into account).
6151
6152 This value is 24K less than that, which allows for 2025
6153 12-byte stubs. If we exceed that, then we will fail to link.
6154 The user will have to relink with an explicit group size
6155 option. */
6156 stub_group_size = 4170000;
6157 }
6158
07d72278 6159 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6160
3ae046cc
NS		 6161 /* If we're applying the cortex A8 fix, we need to determine the
6162 program header size now, because we cannot change it later --
6163 that could alter section placements. Notice the A8 erratum fix
6164 ends up requiring the section addresses to remain unchanged
6165 modulo the page size. That's something we cannot represent
6166 inside BFD, and we don't want to force the section alignment to
6167 be the page size. */
6168 if (htab->fix_cortex_a8)
6169 (*htab->layout_sections_again) ();
6170
906e58ca
NC		 6171 while (1)
6172 {
6173 bfd *input_bfd;
6174 unsigned int bfd_indx;
6175 asection *stub_sec;
d7c5bd02 6176 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6177 bfd_boolean stub_changed = FALSE;
6178 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6179
48229727 6180 num_a8_fixes = 0;
906e58ca
NC		 6181 for (input_bfd = info->input_bfds, bfd_indx = 0;
6182 input_bfd != NULL;
c72f2fb2 6183 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6184 {
6185 Elf_Internal_Shdr *symtab_hdr;
6186 asection *section;
6187 Elf_Internal_Sym *local_syms = NULL;
6188
99059e56
RM		 6189 if (!is_arm_elf (input_bfd))
6190 continue;
adbcc655 6191
48229727
JB		 6192 num_a8_relocs = 0;
6193
906e58ca
NC		 6194 /* We'll need the symbol table in a second. */
6195 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6196 if (symtab_hdr->sh_info == 0)
6197 continue;
6198
4ba2ef8f
TP		 6199 /* Limit scan of symbols to object file whose profile is
6200 Microcontroller to not hinder performance in the general case. */
6201 if (m_profile && first_veneer_scan)
6202 {
6203 struct elf_link_hash_entry **sym_hashes;
6204
6205 sym_hashes = elf_sym_hashes (input_bfd);
6206 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6207 &cmse_stub_created))
4ba2ef8f 6208 goto error_ret_free_local;
0955507f
TP		 6209
6210 if (cmse_stub_created != 0)
6211 stub_changed = TRUE;
4ba2ef8f
TP		 6212 }
6213
906e58ca
NC		 6214 /* Walk over each section attached to the input bfd. */
6215 for (section = input_bfd->sections;
6216 section != NULL;
6217 section = section->next)
6218 {
6219 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6220
6221 /* If there aren't any relocs, then there's nothing more
6222 to do. */
6223 if ((section->flags & SEC_RELOC) == 0
6224 || section->reloc_count == 0
6225 || (section->flags & SEC_CODE) == 0)
6226 continue;
6227
6228 /* If this section is a link-once section that will be
6229 discarded, then don't create any stubs. */
6230 if (section->output_section == NULL
6231 || section->output_section->owner != output_bfd)
6232 continue;
6233
6234 /* Get the relocs. */
6235 internal_relocs
6236 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6237 NULL, info->keep_memory);
6238 if (internal_relocs == NULL)
6239 goto error_ret_free_local;
6240
6241 /* Now examine each relocation. */
6242 irela = internal_relocs;
6243 irelaend = irela + section->reloc_count;
6244 for (; irela < irelaend; irela++)
6245 {
6246 unsigned int r_type, r_indx;
906e58ca
NC		 6247 asection *sym_sec;
6248 bfd_vma sym_value;
6249 bfd_vma destination;
6250 struct elf32_arm_link_hash_entry *hash;
7413f23f 6251 const char *sym_name;
34e77a92 6252 unsigned char st_type;
35fc36a8 6253 enum arm_st_branch_type branch_type;
48229727 6254 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6255
6256 r_type = ELF32_R_TYPE (irela->r_info);
6257 r_indx = ELF32_R_SYM (irela->r_info);
6258
6259 if (r_type >= (unsigned int) R_ARM_max)
6260 {
6261 bfd_set_error (bfd_error_bad_value);
6262 error_ret_free_internal:
6263 if (elf_section_data (section)->relocs == NULL)
6264 free (internal_relocs);
15dd01b1
TP		 6265 /* Fall through. */
6266 error_ret_free_local:
6267 if (local_syms != NULL
6268 && (symtab_hdr->contents
6269 != (unsigned char *) local_syms))
6270 free (local_syms);
6271 return FALSE;
906e58ca 6272 }
b38cadfb 6273
0855e32b
NS		 6274 hash = NULL;
6275 if (r_indx >= symtab_hdr->sh_info)
6276 hash = elf32_arm_hash_entry
6277 (elf_sym_hashes (input_bfd)
6278 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6279
0855e32b
NS		 6280 /* Only look for stubs on branch instructions, or
6281 non-relaxed TLSCALL */
906e58ca 6282 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6283 && (r_type != (unsigned int) R_ARM_THM_CALL)
6284 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6285 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6286 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6287 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6288 && (r_type != (unsigned int) R_ARM_PLT32)
6289 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6290 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6291 && r_type == elf32_arm_tls_transition
6292 (info, r_type, &hash->root)
6293 && ((hash ? hash->tls_type
6294 : (elf32_arm_local_got_tls_type
6295 (input_bfd)[r_indx]))
6296 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6297 continue;
6298
6299 /* Now determine the call target, its name, value,
6300 section. */
6301 sym_sec = NULL;
6302 sym_value = 0;
6303 destination = 0;
7413f23f 6304 sym_name = NULL;
b38cadfb 6305
0855e32b
NS		 6306 if (r_type == (unsigned int) R_ARM_TLS_CALL
6307 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6308 {
6309 /* A non-relaxed TLS call. The target is the
6310 plt-resident trampoline and nothing to do
6311 with the symbol. */
6312 BFD_ASSERT (htab->tls_trampoline > 0);
6313 sym_sec = htab->root.splt;
6314 sym_value = htab->tls_trampoline;
6315 hash = 0;
34e77a92 6316 st_type = STT_FUNC;
35fc36a8 6317 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6318 }
6319 else if (!hash)
906e58ca
NC		 6320 {
6321 /* It's a local symbol. */
6322 Elf_Internal_Sym *sym;
906e58ca
NC		 6323
6324 if (local_syms == NULL)
6325 {
6326 local_syms
6327 = (Elf_Internal_Sym *) symtab_hdr->contents;
6328 if (local_syms == NULL)
6329 local_syms
6330 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6331 symtab_hdr->sh_info, 0,
6332 NULL, NULL, NULL);
6333 if (local_syms == NULL)
6334 goto error_ret_free_internal;
6335 }
6336
6337 sym = local_syms + r_indx;
f6d250ce
TS		 6338 if (sym->st_shndx == SHN_UNDEF)
6339 sym_sec = bfd_und_section_ptr;
6340 else if (sym->st_shndx == SHN_ABS)
6341 sym_sec = bfd_abs_section_ptr;
6342 else if (sym->st_shndx == SHN_COMMON)
6343 sym_sec = bfd_com_section_ptr;
6344 else
6345 sym_sec =
6346 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6347
ffcb4889
NS		 6348 if (!sym_sec)
6349 /* This is an undefined symbol. It can never
6a631e86 6350 be resolved. */
ffcb4889 6351 continue;
fe33d2fa 6352
906e58ca
NC		 6353 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6354 sym_value = sym->st_value;
6355 destination = (sym_value + irela->r_addend
6356 + sym_sec->output_offset
6357 + sym_sec->output_section->vma);
34e77a92 6358 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6359 branch_type =
6360 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6361 sym_name
6362 = bfd_elf_string_from_elf_section (input_bfd,
6363 symtab_hdr->sh_link,
6364 sym->st_name);
906e58ca
NC		 6365 }
6366 else
6367 {
6368 /* It's an external symbol. */
906e58ca
NC		 6369 while (hash->root.root.type == bfd_link_hash_indirect
6370 || hash->root.root.type == bfd_link_hash_warning)
6371 hash = ((struct elf32_arm_link_hash_entry *)
6372 hash->root.root.u.i.link);
6373
6374 if (hash->root.root.type == bfd_link_hash_defined
6375 || hash->root.root.type == bfd_link_hash_defweak)
6376 {
6377 sym_sec = hash->root.root.u.def.section;
6378 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6379
6380 struct elf32_arm_link_hash_table *globals =
6381 elf32_arm_hash_table (info);
6382
6383 /* For a destination in a shared library,
6384 use the PLT stub as target address to
6385 decide whether a branch stub is
6386 needed. */
4dfe6ac6 6387 if (globals != NULL
362d30a1 6388 && globals->root.splt != NULL
4dfe6ac6 6389 && hash != NULL
022f8312
CL		 6390 && hash->root.plt.offset != (bfd_vma) -1)
6391 {
362d30a1 6392 sym_sec = globals->root.splt;
022f8312
CL		 6393 sym_value = hash->root.plt.offset;
6394 if (sym_sec->output_section != NULL)
6395 destination = (sym_value
6396 + sym_sec->output_offset
6397 + sym_sec->output_section->vma);
6398 }
6399 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6400 destination = (sym_value + irela->r_addend
6401 + sym_sec->output_offset
6402 + sym_sec->output_section->vma);
6403 }
69c5861e
CL		 6404 else if ((hash->root.root.type == bfd_link_hash_undefined)
6405 || (hash->root.root.type == bfd_link_hash_undefweak))
6406 {
6407 /* For a shared library, use the PLT stub as
6408 target address to decide whether a long
6409 branch stub is needed.
6410 For absolute code, they cannot be handled. */
6411 struct elf32_arm_link_hash_table *globals =
6412 elf32_arm_hash_table (info);
6413
4dfe6ac6 6414 if (globals != NULL
362d30a1 6415 && globals->root.splt != NULL
4dfe6ac6 6416 && hash != NULL
69c5861e
CL		 6417 && hash->root.plt.offset != (bfd_vma) -1)
6418 {
362d30a1 6419 sym_sec = globals->root.splt;
69c5861e
CL		 6420 sym_value = hash->root.plt.offset;
6421 if (sym_sec->output_section != NULL)
6422 destination = (sym_value
6423 + sym_sec->output_offset
6424 + sym_sec->output_section->vma);
6425 }
6426 else
6427 continue;
6428 }
906e58ca
NC		 6429 else
6430 {
6431 bfd_set_error (bfd_error_bad_value);
6432 goto error_ret_free_internal;
6433 }
34e77a92 6434 st_type = hash->root.type;
39d911fc
TP		 6435 branch_type =
6436 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6437 sym_name = hash->root.root.root.string;
906e58ca
NC		 6438 }
6439
48229727 6440 do
7413f23f 6441 {
b715f643 6442 bfd_boolean new_stub;
0955507f 6443 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6444
48229727
JB		 6445 /* Determine what (if any) linker stub is needed. */
6446 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6447 st_type, &branch_type,
6448 hash, destination, sym_sec,
48229727
JB		 6449 input_bfd, sym_name);
6450 if (stub_type == arm_stub_none)
6451 break;
6452
48229727
JB		 6453 /* We've either created a stub for this reloc already,
6454 or we are about to. */
0955507f 6455 stub_entry =
b715f643
TP		 6456 elf32_arm_create_stub (htab, stub_type, section, irela,
6457 sym_sec, hash,
6458 (char *) sym_name, sym_value,
6459 branch_type, &new_stub);
7413f23f 6460
0955507f 6461 created_stub = stub_entry != NULL;
b715f643
TP		 6462 if (!created_stub)
6463 goto error_ret_free_internal;
6464 else if (!new_stub)
6465 break;
99059e56 6466 else
b715f643 6467 stub_changed = TRUE;
99059e56
RM		 6468 }
6469 while (0);
6470
6471 /* Look for relocations which might trigger Cortex-A8
6472 erratum. */
6473 if (htab->fix_cortex_a8
6474 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6475 || r_type == (unsigned int) R_ARM_THM_JUMP19
6476 || r_type == (unsigned int) R_ARM_THM_CALL
6477 || r_type == (unsigned int) R_ARM_THM_XPC22))
6478 {
6479 bfd_vma from = section->output_section->vma
6480 + section->output_offset
6481 + irela->r_offset;
6482
6483 if ((from & 0xfff) == 0xffe)
6484 {
6485 /* Found a candidate. Note we haven't checked the
6486 destination is within 4K here: if we do so (and
6487 don't create an entry in a8_relocs) we can't tell
6488 that a branch should have been relocated when
6489 scanning later. */
6490 if (num_a8_relocs == a8_reloc_table_size)
6491 {
6492 a8_reloc_table_size *= 2;
6493 a8_relocs = (struct a8_erratum_reloc *)
6494 bfd_realloc (a8_relocs,
6495 sizeof (struct a8_erratum_reloc)
6496 * a8_reloc_table_size);
6497 }
6498
6499 a8_relocs[num_a8_relocs].from = from;
6500 a8_relocs[num_a8_relocs].destination = destination;
6501 a8_relocs[num_a8_relocs].r_type = r_type;
6502 a8_relocs[num_a8_relocs].branch_type = branch_type;
6503 a8_relocs[num_a8_relocs].sym_name = sym_name;
6504 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6505 a8_relocs[num_a8_relocs].hash = hash;
6506
6507 num_a8_relocs++;
6508 }
6509 }
906e58ca
NC		 6510 }
6511
99059e56
RM		 6512 /* We're done with the internal relocs, free them. */
6513 if (elf_section_data (section)->relocs == NULL)
6514 free (internal_relocs);
6515 }
48229727 6516
99059e56 6517 if (htab->fix_cortex_a8)
48229727 6518 {
99059e56
RM		 6519 /* Sort relocs which might apply to Cortex-A8 erratum. */
6520 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6521 sizeof (struct a8_erratum_reloc),
99059e56 6522 &a8_reloc_compare);
48229727 6523
99059e56
RM		 6524 /* Scan for branches which might trigger Cortex-A8 erratum. */
6525 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6526 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6527 a8_relocs, num_a8_relocs,
6528 prev_num_a8_fixes, &stub_changed)
6529 != 0)
48229727 6530 goto error_ret_free_local;
5e681ec4 6531 }
7f991970
AM		 6532
6533 if (local_syms != NULL
6534 && symtab_hdr->contents != (unsigned char *) local_syms)
6535 {
6536 if (!info->keep_memory)
6537 free (local_syms);
6538 else
6539 symtab_hdr->contents = (unsigned char *) local_syms;
6540 }
5e681ec4
PB		 6541 }
6542
0955507f
TP		 6543 if (first_veneer_scan
6544 && !set_cmse_veneer_addr_from_implib (info, htab,
6545 &cmse_stub_created))
6546 ret = FALSE;
6547
eb7c4339 6548 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6549 stub_changed = TRUE;
48229727 6550
906e58ca
NC		 6551 if (!stub_changed)
6552 break;
5e681ec4 6553
906e58ca
NC		 6554 /* OK, we've added some stubs. Find out the new size of the
6555 stub sections. */
6556 for (stub_sec = htab->stub_bfd->sections;
6557 stub_sec != NULL;
6558 stub_sec = stub_sec->next)
3e6b1042
DJ		 6559 {
6560 /* Ignore non-stub sections. */
6561 if (!strstr (stub_sec->name, STUB_SUFFIX))
6562 continue;
6563
6564 stub_sec->size = 0;
6565 }
b34b2d70 6566
0955507f
TP		 6567 /* Add new SG veneers after those already in the input import
6568 library. */
6569 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6570 stub_type++)
6571 {
6572 bfd_vma *start_offset_p;
6573 asection **stub_sec_p;
6574
6575 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6576 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6577 if (start_offset_p == NULL)
6578 continue;
6579
6580 BFD_ASSERT (stub_sec_p != NULL);
6581 if (*stub_sec_p != NULL)
6582 (*stub_sec_p)->size = *start_offset_p;
6583 }
6584
d7c5bd02 6585 /* Compute stub section size, considering padding. */
906e58ca 6586 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6587 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6588 stub_type++)
6589 {
6590 int size, padding;
6591 asection **stub_sec_p;
6592
6593 padding = arm_dedicated_stub_section_padding (stub_type);
6594 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6595 /* Skip if no stub input section or no stub section padding
6596 required. */
6597 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6598 continue;
6599 /* Stub section padding required but no dedicated section. */
6600 BFD_ASSERT (stub_sec_p);
6601
6602 size = (*stub_sec_p)->size;
6603 size = (size + padding - 1) & ~(padding - 1);
6604 (*stub_sec_p)->size = size;
6605 }
906e58ca 6606
48229727
JB		 6607 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6608 if (htab->fix_cortex_a8)
99059e56
RM		 6609 for (i = 0; i < num_a8_fixes; i++)
6610 {
48229727 6611 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6612 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6613
6614 if (stub_sec == NULL)
7f991970 6615 return FALSE;
48229727 6616
99059e56
RM		 6617 stub_sec->size
6618 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6619 NULL);
6620 }
48229727
JB		 6621
6622
906e58ca
NC		 6623 /* Ask the linker to do its stuff. */
6624 (*htab->layout_sections_again) ();
4ba2ef8f 6625 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6626 }
6627
48229727
JB		 6628 /* Add stubs for Cortex-A8 erratum fixes now. */
6629 if (htab->fix_cortex_a8)
6630 {
6631 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6632 {
6633 struct elf32_arm_stub_hash_entry *stub_entry;
6634 char *stub_name = a8_fixes[i].stub_name;
6635 asection *section = a8_fixes[i].section;
6636 unsigned int section_id = a8_fixes[i].section->id;
6637 asection *link_sec = htab->stub_group[section_id].link_sec;
6638 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6639 const insn_sequence *template_sequence;
6640 int template_size, size = 0;
6641
6642 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6643 TRUE, FALSE);
6644 if (stub_entry == NULL)
6645 {
6646 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
6647 section->owner,
6648 stub_name);
6649 return FALSE;
6650 }
6651
6652 stub_entry->stub_sec = stub_sec;
0955507f 6653 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6654 stub_entry->id_sec = link_sec;
6655 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6656 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6657 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6658 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6659 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6660 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6661
99059e56
RM		 6662 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6663 &template_sequence,
6664 &template_size);
48229727 6665
99059e56
RM		 6666 stub_entry->stub_size = size;
6667 stub_entry->stub_template = template_sequence;
6668 stub_entry->stub_template_size = template_size;
6669 }
48229727
JB		 6670
6671 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6672 elf32_arm_write_section(). */
48229727
JB		 6673 htab->a8_erratum_fixes = a8_fixes;
6674 htab->num_a8_erratum_fixes = num_a8_fixes;
6675 }
6676 else
6677 {
6678 htab->a8_erratum_fixes = NULL;
6679 htab->num_a8_erratum_fixes = 0;
6680 }
0955507f 6681 return ret;
5e681ec4
PB		 6682}
6683
906e58ca
NC		 6684/* Build all the stubs associated with the current output file. The
6685 stubs are kept in a hash table attached to the main linker hash
6686 table. We also set up the .plt entries for statically linked PIC
6687 functions here. This function is called via arm_elf_finish in the
6688 linker. */
252b5132 6689
906e58ca
NC		 6690bfd_boolean
6691elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 6692{
906e58ca
NC		 6693 asection *stub_sec;
6694 struct bfd_hash_table *table;
0955507f 6695 enum elf32_arm_stub_type stub_type;
906e58ca 6696 struct elf32_arm_link_hash_table *htab;
252b5132 6697
906e58ca 6698 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 6699 if (htab == NULL)
6700 return FALSE;
252b5132 6701
906e58ca
NC		 6702 for (stub_sec = htab->stub_bfd->sections;
6703 stub_sec != NULL;
6704 stub_sec = stub_sec->next)
252b5132 6705 {
906e58ca
NC		 6706 bfd_size_type size;
6707
8029a119 6708 /* Ignore non-stub sections. */
906e58ca
NC		 6709 if (!strstr (stub_sec->name, STUB_SUFFIX))
6710 continue;
6711
d7c5bd02 6712 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 6713 must at least be done for stub section requiring padding and for SG
6714 veneers to ensure that a non secure code branching to a removed SG
6715 veneer causes an error. */
906e58ca 6716 size = stub_sec->size;
21d799b5 6717 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 6718 if (stub_sec->contents == NULL && size != 0)
6719 return FALSE;
0955507f 6720
906e58ca 6721 stub_sec->size = 0;
252b5132
RH		 6722 }
6723
0955507f
TP		 6724 /* Add new SG veneers after those already in the input import library. */
6725 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
6726 {
6727 bfd_vma *start_offset_p;
6728 asection **stub_sec_p;
6729
6730 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6731 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6732 if (start_offset_p == NULL)
6733 continue;
6734
6735 BFD_ASSERT (stub_sec_p != NULL);
6736 if (*stub_sec_p != NULL)
6737 (*stub_sec_p)->size = *start_offset_p;
6738 }
6739
906e58ca
NC		 6740 /* Build the stubs as directed by the stub hash table. */
6741 table = &htab->stub_hash_table;
6742 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 6743 if (htab->fix_cortex_a8)
6744 {
6745 /* Place the cortex a8 stubs last. */
6746 htab->fix_cortex_a8 = -1;
6747 bfd_hash_traverse (table, arm_build_one_stub, info);
6748 }
252b5132 6749
906e58ca 6750 return TRUE;
252b5132
RH		 6751}
6752
9b485d32
NC		 6753/* Locate the Thumb encoded calling stub for NAME. */
6754
252b5132 6755static struct elf_link_hash_entry *
57e8b36a
NC		 6756find_thumb_glue (struct bfd_link_info *link_info,
6757 const char *name,
f2a9dd69 6758 char **error_message)
252b5132
RH		 6759{
6760 char *tmp_name;
6761 struct elf_link_hash_entry *hash;
6762 struct elf32_arm_link_hash_table *hash_table;
6763
6764 /* We need a pointer to the armelf specific hash table. */
6765 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6766 if (hash_table == NULL)
6767 return NULL;
252b5132 6768
21d799b5 6769 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6770 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6771
6772 BFD_ASSERT (tmp_name);
6773
6774 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
6775
6776 hash = elf_link_hash_lookup
b34976b6 6777 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6778
b1657152
AM		 6779 if (hash == NULL
6780 && asprintf (error_message, _("unable to find THUMB glue '%s' for '%s'"),
6781 tmp_name, name) == -1)
6782 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6783
6784 free (tmp_name);
6785
6786 return hash;
6787}
6788
9b485d32
NC		 6789/* Locate the ARM encoded calling stub for NAME. */
6790
252b5132 6791static struct elf_link_hash_entry *
57e8b36a
NC		 6792find_arm_glue (struct bfd_link_info *link_info,
6793 const char *name,
f2a9dd69 6794 char **error_message)
252b5132
RH		 6795{
6796 char *tmp_name;
6797 struct elf_link_hash_entry *myh;
6798 struct elf32_arm_link_hash_table *hash_table;
6799
6800 /* We need a pointer to the elfarm specific hash table. */
6801 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6802 if (hash_table == NULL)
6803 return NULL;
252b5132 6804
21d799b5 6805 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6806 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6807
6808 BFD_ASSERT (tmp_name);
6809
6810 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6811
6812 myh = elf_link_hash_lookup
b34976b6 6813 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6814
b1657152
AM		 6815 if (myh == NULL
6816 && asprintf (error_message, _("unable to find ARM glue '%s' for '%s'"),
6817 tmp_name, name) == -1)
6818 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6819
6820 free (tmp_name);
6821
6822 return myh;
6823}
6824
8f6277f5 6825/* ARM->Thumb glue (static images):
252b5132
RH		 6826
6827 .arm
6828 __func_from_arm:
6829 ldr r12, __func_addr
6830 bx r12
6831 __func_addr:
906e58ca 6832 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 6833
26079076
PB		 6834 (v5t static images)
6835 .arm
6836 __func_from_arm:
6837 ldr pc, __func_addr
6838 __func_addr:
906e58ca 6839 .word func @ behave as if you saw a ARM_32 reloc.
26079076 6840
8f6277f5
PB		 6841 (relocatable images)
6842 .arm
6843 __func_from_arm:
6844 ldr r12, __func_offset
6845 add r12, r12, pc
6846 bx r12
6847 __func_offset:
8029a119 6848 .word func - . */
8f6277f5
PB		 6849
6850#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 6851static const insn32 a2t1_ldr_insn = 0xe59fc000;
6852static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
6853static const insn32 a2t3_func_addr_insn = 0x00000001;
6854
26079076
PB		 6855#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
6856static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
6857static const insn32 a2t2v5_func_addr_insn = 0x00000001;
6858
8f6277f5
PB		 6859#define ARM2THUMB_PIC_GLUE_SIZE 16
6860static const insn32 a2t1p_ldr_insn = 0xe59fc004;
6861static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
6862static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
6863
9b485d32 6864/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 6865
8029a119
NC		 6866 .thumb .thumb
6867 .align 2 .align 2
6868 __func_from_thumb: __func_from_thumb:
6869 bx pc push {r6, lr}
6870 nop ldr r6, __func_addr
6871 .arm mov lr, pc
6872 b func bx r6
99059e56
RM		 6873 .arm
6874 ;; back_to_thumb
6875 ldmia r13! {r6, lr}
6876 bx lr
6877 __func_addr:
6878 .word func */
252b5132
RH		 6879
6880#define THUMB2ARM_GLUE_SIZE 8
6881static const insn16 t2a1_bx_pc_insn = 0x4778;
6882static const insn16 t2a2_noop_insn = 0x46c0;
6883static const insn32 t2a3_b_insn = 0xea000000;
6884
c7b8f16e 6885#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 6886#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
6887#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 6888
845b51d6
PB		 6889#define ARM_BX_VENEER_SIZE 12
6890static const insn32 armbx1_tst_insn = 0xe3100001;
6891static const insn32 armbx2_moveq_insn = 0x01a0f000;
6892static const insn32 armbx3_bx_insn = 0xe12fff10;
6893
7e392df6 6894#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 6895static void
6896arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 6897{
6898 asection * s;
8029a119 6899 bfd_byte * contents;
252b5132 6900
8029a119 6901 if (size == 0)
3e6b1042
DJ		 6902 {
6903 /* Do not include empty glue sections in the output. */
6904 if (abfd != NULL)
6905 {
3d4d4302 6906 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 6907 if (s != NULL)
6908 s->flags |= SEC_EXCLUDE;
6909 }
6910 return;
6911 }
252b5132 6912
8029a119 6913 BFD_ASSERT (abfd != NULL);
252b5132 6914
3d4d4302 6915 s = bfd_get_linker_section (abfd, name);
8029a119 6916 BFD_ASSERT (s != NULL);
252b5132 6917
21d799b5 6918 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 6919
8029a119
NC		 6920 BFD_ASSERT (s->size == size);
6921 s->contents = contents;
6922}
906e58ca 6923
8029a119
NC		 6924bfd_boolean
6925bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
6926{
6927 struct elf32_arm_link_hash_table * globals;
906e58ca 6928
8029a119
NC		 6929 globals = elf32_arm_hash_table (info);
6930 BFD_ASSERT (globals != NULL);
906e58ca 6931
8029a119
NC		 6932 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6933 globals->arm_glue_size,
6934 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 6935
8029a119
NC		 6936 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6937 globals->thumb_glue_size,
6938 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 6939
8029a119
NC		 6940 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6941 globals->vfp11_erratum_glue_size,
6942 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 6943
a504d23a
LA		 6944 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6945 globals->stm32l4xx_erratum_glue_size,
6946 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6947
8029a119
NC		 6948 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6949 globals->bx_glue_size,
845b51d6
PB		 6950 ARM_BX_GLUE_SECTION_NAME);
6951
b34976b6 6952 return TRUE;
252b5132
RH		 6953}
6954
a4fd1a8e 6955/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 6956 returns the symbol identifying the stub. */
6957
a4fd1a8e 6958static struct elf_link_hash_entry *
57e8b36a
NC		 6959record_arm_to_thumb_glue (struct bfd_link_info * link_info,
6960 struct elf_link_hash_entry * h)
252b5132
RH		 6961{
6962 const char * name = h->root.root.string;
63b0f745 6963 asection * s;
252b5132
RH		 6964 char * tmp_name;
6965 struct elf_link_hash_entry * myh;
14a793b2 6966 struct bfd_link_hash_entry * bh;
252b5132 6967 struct elf32_arm_link_hash_table * globals;
dc810e39 6968 bfd_vma val;
2f475487 6969 bfd_size_type size;
252b5132
RH		 6970
6971 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 6972 BFD_ASSERT (globals != NULL);
6973 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6974
3d4d4302 6975 s = bfd_get_linker_section
252b5132
RH		 6976 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
6977
252b5132
RH		 6978 BFD_ASSERT (s != NULL);
6979
21d799b5 6980 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6981 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6982
6983 BFD_ASSERT (tmp_name);
6984
6985 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6986
6987 myh = elf_link_hash_lookup
b34976b6 6988 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 6989
6990 if (myh != NULL)
6991 {
9b485d32 6992 /* We've already seen this guy. */
252b5132 6993 free (tmp_name);
a4fd1a8e 6994 return myh;
252b5132
RH		 6995 }
6996
57e8b36a
NC		 6997 /* The only trick here is using hash_table->arm_glue_size as the value.
6998 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 6999 putting it. The +1 on the value marks that the stub has not been
7000 output yet - not that it is a Thumb function. */
14a793b2 7001 bh = NULL;
dc810e39
AM		 7002 val = globals->arm_glue_size + 1;
7003 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
7004 tmp_name, BSF_GLOBAL, s, val,
b34976b6 7005 NULL, TRUE, FALSE, &bh);
252b5132 7006
b7693d02
DJ		 7007 myh = (struct elf_link_hash_entry *) bh;
7008 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7009 myh->forced_local = 1;
7010
252b5132
RH		 7011 free (tmp_name);
7012
0e1862bb
L		 7013 if (bfd_link_pic (link_info)
7014 || globals->root.is_relocatable_executable
27e55c4d 7015 || globals->pic_veneer)
2f475487 7016 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7017 else if (globals->use_blx)
7018 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7019 else
2f475487
AM		 7020 size = ARM2THUMB_STATIC_GLUE_SIZE;
7021
7022 s->size += size;
7023 globals->arm_glue_size += size;
252b5132 7024
a4fd1a8e 7025 return myh;
252b5132
RH		 7026}
7027
845b51d6
PB		 7028/* Allocate space for ARMv4 BX veneers. */
7029
7030static void
7031record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7032{
7033 asection * s;
7034 struct elf32_arm_link_hash_table *globals;
7035 char *tmp_name;
7036 struct elf_link_hash_entry *myh;
7037 struct bfd_link_hash_entry *bh;
7038 bfd_vma val;
7039
7040 /* BX PC does not need a veneer. */
7041 if (reg == 15)
7042 return;
7043
7044 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7045 BFD_ASSERT (globals != NULL);
7046 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7047
7048 /* Check if this veneer has already been allocated. */
7049 if (globals->bx_glue_offset[reg])
7050 return;
7051
3d4d4302 7052 s = bfd_get_linker_section
845b51d6
PB		 7053 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7054
7055 BFD_ASSERT (s != NULL);
7056
7057 /* Add symbol for veneer. */
21d799b5
NC		 7058 tmp_name = (char *)
7059 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7060
845b51d6 7061 BFD_ASSERT (tmp_name);
906e58ca 7062
845b51d6 7063 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7064
845b51d6
PB		 7065 myh = elf_link_hash_lookup
7066 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7067
845b51d6 7068 BFD_ASSERT (myh == NULL);
906e58ca 7069
845b51d6
PB		 7070 bh = NULL;
7071 val = globals->bx_glue_size;
7072 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7073 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7074 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7075
7076 myh = (struct elf_link_hash_entry *) bh;
7077 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7078 myh->forced_local = 1;
7079
7080 s->size += ARM_BX_VENEER_SIZE;
7081 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7082 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7083}
7084
7085
c7b8f16e
JB		 7086/* Add an entry to the code/data map for section SEC. */
7087
7088static void
7089elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7090{
7091 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7092 unsigned int newidx;
906e58ca 7093
c7b8f16e
JB		 7094 if (sec_data->map == NULL)
7095 {
21d799b5 7096 sec_data->map = (elf32_arm_section_map *)
99059e56 7097 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7098 sec_data->mapcount = 0;
7099 sec_data->mapsize = 1;
7100 }
906e58ca 7101
c7b8f16e 7102 newidx = sec_data->mapcount++;
906e58ca 7103
c7b8f16e
JB		 7104 if (sec_data->mapcount > sec_data->mapsize)
7105 {
7106 sec_data->mapsize *= 2;
21d799b5 7107 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7108 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7109 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7110 }
7111
7112 if (sec_data->map)
7113 {
7114 sec_data->map[newidx].vma = vma;
7115 sec_data->map[newidx].type = type;
c7b8f16e 7116 }
c7b8f16e
JB		 7117}
7118
7119
7120/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7121 veneers are handled for now. */
7122
7123static bfd_vma
7124record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7125 elf32_vfp11_erratum_list *branch,
7126 bfd *branch_bfd,
7127 asection *branch_sec,
7128 unsigned int offset)
c7b8f16e
JB		 7129{
7130 asection *s;
7131 struct elf32_arm_link_hash_table *hash_table;
7132 char *tmp_name;
7133 struct elf_link_hash_entry *myh;
7134 struct bfd_link_hash_entry *bh;
7135 bfd_vma val;
7136 struct _arm_elf_section_data *sec_data;
c7b8f16e 7137 elf32_vfp11_erratum_list *newerr;
906e58ca 7138
c7b8f16e 7139 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7140 BFD_ASSERT (hash_table != NULL);
7141 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7142
3d4d4302 7143 s = bfd_get_linker_section
c7b8f16e 7144 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7145
c7b8f16e 7146 sec_data = elf32_arm_section_data (s);
906e58ca 7147
c7b8f16e 7148 BFD_ASSERT (s != NULL);
906e58ca 7149
21d799b5 7150 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7151 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7152
c7b8f16e 7153 BFD_ASSERT (tmp_name);
906e58ca 7154
c7b8f16e
JB		 7155 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7156 hash_table->num_vfp11_fixes);
906e58ca 7157
c7b8f16e
JB		 7158 myh = elf_link_hash_lookup
7159 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7160
c7b8f16e 7161 BFD_ASSERT (myh == NULL);
906e58ca 7162
c7b8f16e
JB		 7163 bh = NULL;
7164 val = hash_table->vfp11_erratum_glue_size;
7165 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7166 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7167 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7168
7169 myh = (struct elf_link_hash_entry *) bh;
7170 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7171 myh->forced_local = 1;
7172
7173 /* Link veneer back to calling location. */
c7e2358a 7174 sec_data->erratumcount += 1;
21d799b5
NC		 7175 newerr = (elf32_vfp11_erratum_list *)
7176 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7177
c7b8f16e
JB		 7178 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7179 newerr->vma = -1;
7180 newerr->u.v.branch = branch;
7181 newerr->u.v.id = hash_table->num_vfp11_fixes;
7182 branch->u.b.veneer = newerr;
7183
7184 newerr->next = sec_data->erratumlist;
7185 sec_data->erratumlist = newerr;
7186
7187 /* A symbol for the return from the veneer. */
7188 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7189 hash_table->num_vfp11_fixes);
7190
7191 myh = elf_link_hash_lookup
7192 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7193
c7b8f16e
JB		 7194 if (myh != NULL)
7195 abort ();
7196
7197 bh = NULL;
7198 val = offset + 4;
7199 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7200 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7201
c7b8f16e
JB		 7202 myh = (struct elf_link_hash_entry *) bh;
7203 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7204 myh->forced_local = 1;
7205
7206 free (tmp_name);
906e58ca 7207
c7b8f16e
JB		 7208 /* Generate a mapping symbol for the veneer section, and explicitly add an
7209 entry for that symbol to the code/data map for the section. */
7210 if (hash_table->vfp11_erratum_glue_size == 0)
7211 {
7212 bh = NULL;
7213 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7214 ever requires this erratum fix. */
c7b8f16e
JB		 7215 _bfd_generic_link_add_one_symbol (link_info,
7216 hash_table->bfd_of_glue_owner, "$a",
7217 BSF_LOCAL, s, 0, NULL,
99059e56 7218 TRUE, FALSE, &bh);
c7b8f16e
JB		 7219
7220 myh = (struct elf_link_hash_entry *) bh;
7221 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7222 myh->forced_local = 1;
906e58ca 7223
c7b8f16e 7224 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7225 BFDs. We must make a note of this generated mapping symbol
7226 ourselves so that code byteswapping works properly in
7227 elf32_arm_write_section. */
c7b8f16e
JB		 7228 elf32_arm_section_map_add (s, 'a', 0);
7229 }
906e58ca 7230
c7b8f16e
JB		 7231 s->size += VFP11_ERRATUM_VENEER_SIZE;
7232 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7233 hash_table->num_vfp11_fixes++;
906e58ca 7234
c7b8f16e
JB		 7235 /* The offset of the veneer. */
7236 return val;
7237}
7238
a504d23a
LA		 7239/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7240 veneers need to be handled because used only in Cortex-M. */
7241
7242static bfd_vma
7243record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7244 elf32_stm32l4xx_erratum_list *branch,
7245 bfd *branch_bfd,
7246 asection *branch_sec,
7247 unsigned int offset,
7248 bfd_size_type veneer_size)
7249{
7250 asection *s;
7251 struct elf32_arm_link_hash_table *hash_table;
7252 char *tmp_name;
7253 struct elf_link_hash_entry *myh;
7254 struct bfd_link_hash_entry *bh;
7255 bfd_vma val;
7256 struct _arm_elf_section_data *sec_data;
7257 elf32_stm32l4xx_erratum_list *newerr;
7258
7259 hash_table = elf32_arm_hash_table (link_info);
7260 BFD_ASSERT (hash_table != NULL);
7261 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7262
7263 s = bfd_get_linker_section
7264 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7265
7266 BFD_ASSERT (s != NULL);
7267
7268 sec_data = elf32_arm_section_data (s);
7269
7270 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7271 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7272
7273 BFD_ASSERT (tmp_name);
7274
7275 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7276 hash_table->num_stm32l4xx_fixes);
7277
7278 myh = elf_link_hash_lookup
7279 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7280
7281 BFD_ASSERT (myh == NULL);
7282
7283 bh = NULL;
7284 val = hash_table->stm32l4xx_erratum_glue_size;
7285 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7286 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7287 NULL, TRUE, FALSE, &bh);
7288
7289 myh = (struct elf_link_hash_entry *) bh;
7290 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7291 myh->forced_local = 1;
7292
7293 /* Link veneer back to calling location. */
7294 sec_data->stm32l4xx_erratumcount += 1;
7295 newerr = (elf32_stm32l4xx_erratum_list *)
7296 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7297
7298 newerr->type = STM32L4XX_ERRATUM_VENEER;
7299 newerr->vma = -1;
7300 newerr->u.v.branch = branch;
7301 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7302 branch->u.b.veneer = newerr;
7303
7304 newerr->next = sec_data->stm32l4xx_erratumlist;
7305 sec_data->stm32l4xx_erratumlist = newerr;
7306
7307 /* A symbol for the return from the veneer. */
7308 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7309 hash_table->num_stm32l4xx_fixes);
7310
7311 myh = elf_link_hash_lookup
7312 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7313
7314 if (myh != NULL)
7315 abort ();
7316
7317 bh = NULL;
7318 val = offset + 4;
7319 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7320 branch_sec, val, NULL, TRUE, FALSE, &bh);
7321
7322 myh = (struct elf_link_hash_entry *) bh;
7323 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7324 myh->forced_local = 1;
7325
7326 free (tmp_name);
7327
7328 /* Generate a mapping symbol for the veneer section, and explicitly add an
7329 entry for that symbol to the code/data map for the section. */
7330 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7331 {
7332 bh = NULL;
7333 /* Creates a THUMB symbol since there is no other choice. */
7334 _bfd_generic_link_add_one_symbol (link_info,
7335 hash_table->bfd_of_glue_owner, "$t",
7336 BSF_LOCAL, s, 0, NULL,
7337 TRUE, FALSE, &bh);
7338
7339 myh = (struct elf_link_hash_entry *) bh;
7340 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7341 myh->forced_local = 1;
7342
7343 /* The elf32_arm_init_maps function only cares about symbols from input
7344 BFDs. We must make a note of this generated mapping symbol
7345 ourselves so that code byteswapping works properly in
7346 elf32_arm_write_section. */
7347 elf32_arm_section_map_add (s, 't', 0);
7348 }
7349
7350 s->size += veneer_size;
7351 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7352 hash_table->num_stm32l4xx_fixes++;
7353
7354 /* The offset of the veneer. */
7355 return val;
7356}
7357
8029a119 7358#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7359 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7360 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7361
7362/* Create a fake section for use by the ARM backend of the linker. */
7363
7364static bfd_boolean
7365arm_make_glue_section (bfd * abfd, const char * name)
7366{
7367 asection * sec;
7368
3d4d4302 7369 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7370 if (sec != NULL)
7371 /* Already made. */
7372 return TRUE;
7373
3d4d4302 7374 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7375
7376 if (sec == NULL
7377 || !bfd_set_section_alignment (abfd, sec, 2))
7378 return FALSE;
7379
7380 /* Set the gc mark to prevent the section from being removed by garbage
7381 collection, despite the fact that no relocs refer to this section. */
7382 sec->gc_mark = 1;
7383
7384 return TRUE;
7385}
7386
1db37fe6
YG		 7387/* Set size of .plt entries. This function is called from the
7388 linker scripts in ld/emultempl/{armelf}.em. */
7389
7390void
7391bfd_elf32_arm_use_long_plt (void)
7392{
7393 elf32_arm_use_long_plt_entry = TRUE;
7394}
7395
8afb0e02
NC		 7396/* Add the glue sections to ABFD. This function is called from the
7397 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7398
b34976b6 7399bfd_boolean
57e8b36a
NC		 7400bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7401 struct bfd_link_info *info)
252b5132 7402{
a504d23a
LA		 7403 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7404 bfd_boolean dostm32l4xx = globals
7405 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7406 bfd_boolean addglue;
7407
8afb0e02
NC		 7408 /* If we are only performing a partial
7409 link do not bother adding the glue. */
0e1862bb 7410 if (bfd_link_relocatable (info))
b34976b6 7411 return TRUE;
252b5132 7412
a504d23a 7413 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7414 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7415 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7416 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7417
7418 if (!dostm32l4xx)
7419 return addglue;
7420
7421 return addglue
7422 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7423}
7424
daa4adae
TP		 7425/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7426 ensures they are not marked for deletion by
7427 strip_excluded_output_sections () when veneers are going to be created
7428 later. Not doing so would trigger assert on empty section size in
7429 lang_size_sections_1 (). */
7430
7431void
7432bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7433{
7434 enum elf32_arm_stub_type stub_type;
7435
7436 /* If we are only performing a partial
7437 link do not bother adding the glue. */
7438 if (bfd_link_relocatable (info))
7439 return;
7440
7441 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7442 {
7443 asection *out_sec;
7444 const char *out_sec_name;
7445
7446 if (!arm_dedicated_stub_output_section_required (stub_type))
7447 continue;
7448
7449 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7450 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7451 if (out_sec != NULL)
7452 out_sec->flags |= SEC_KEEP;
7453 }
7454}
7455
8afb0e02
NC		 7456/* Select a BFD to be used to hold the sections used by the glue code.
7457 This function is called from the linker scripts in ld/emultempl/
8029a119 7458 {armelf/pe}.em. */
8afb0e02 7459
b34976b6 7460bfd_boolean
57e8b36a 7461bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7462{
7463 struct elf32_arm_link_hash_table *globals;
7464
7465 /* If we are only performing a partial link
7466 do not bother getting a bfd to hold the glue. */
0e1862bb 7467 if (bfd_link_relocatable (info))
b34976b6 7468 return TRUE;
8afb0e02 7469
b7693d02
DJ		 7470 /* Make sure we don't attach the glue sections to a dynamic object. */
7471 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7472
8afb0e02 7473 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7474 BFD_ASSERT (globals != NULL);
7475
7476 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7477 return TRUE;
8afb0e02 7478
252b5132
RH		 7479 /* Save the bfd for later use. */
7480 globals->bfd_of_glue_owner = abfd;
cedb70c5 7481
b34976b6 7482 return TRUE;
252b5132
RH		 7483}
7484
906e58ca
NC		 7485static void
7486check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7487{
2de70689
MGD		 7488 int cpu_arch;
7489
b38cadfb 7490 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7491 Tag_CPU_arch);
7492
7493 if (globals->fix_arm1176)
7494 {
7495 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7496 globals->use_blx = 1;
7497 }
7498 else
7499 {
7500 if (cpu_arch > TAG_CPU_ARCH_V4T)
7501 globals->use_blx = 1;
7502 }
39b41c9c
PB		 7503}
7504
b34976b6 7505bfd_boolean
57e8b36a 7506bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7507 struct bfd_link_info *link_info)
252b5132
RH		 7508{
7509 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7510 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7511 Elf_Internal_Rela *irel, *irelend;
7512 bfd_byte *contents = NULL;
252b5132
RH		 7513
7514 asection *sec;
7515 struct elf32_arm_link_hash_table *globals;
7516
7517 /* If we are only performing a partial link do not bother
7518 to construct any glue. */
0e1862bb 7519 if (bfd_link_relocatable (link_info))
b34976b6 7520 return TRUE;
252b5132 7521
39ce1a6a
NC		 7522 /* Here we have a bfd that is to be included on the link. We have a
7523 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7524 globals = elf32_arm_hash_table (link_info);
252b5132 7525 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7526
7527 check_use_blx (globals);
252b5132 7528
d504ffc8 7529 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7530 {
d003868e
AM		 7531 _bfd_error_handler (_("%B: BE8 images only valid in big-endian mode."),
7532 abfd);
e489d0ae
PB		 7533 return FALSE;
7534 }
f21f3fe0 7535
39ce1a6a
NC		 7536 /* PR 5398: If we have not decided to include any loadable sections in
7537 the output then we will not have a glue owner bfd. This is OK, it
7538 just means that there is nothing else for us to do here. */
7539 if (globals->bfd_of_glue_owner == NULL)
7540 return TRUE;
7541
252b5132
RH		 7542 /* Rummage around all the relocs and map the glue vectors. */
7543 sec = abfd->sections;
7544
7545 if (sec == NULL)
b34976b6 7546 return TRUE;
252b5132
RH		 7547
7548 for (; sec != NULL; sec = sec->next)
7549 {
7550 if (sec->reloc_count == 0)
7551 continue;
7552
2f475487
AM		 7553 if ((sec->flags & SEC_EXCLUDE) != 0)
7554 continue;
7555
0ffa91dd 7556 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7557
9b485d32 7558 /* Load the relocs. */
6cdc0ccc 7559 internal_relocs
906e58ca 7560 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7561
6cdc0ccc
AM		 7562 if (internal_relocs == NULL)
7563 goto error_return;
252b5132 7564
6cdc0ccc
AM		 7565 irelend = internal_relocs + sec->reloc_count;
7566 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7567 {
7568 long r_type;
7569 unsigned long r_index;
252b5132
RH		 7570
7571 struct elf_link_hash_entry *h;
7572
7573 r_type = ELF32_R_TYPE (irel->r_info);
7574 r_index = ELF32_R_SYM (irel->r_info);
7575
9b485d32 7576 /* These are the only relocation types we care about. */
ba96a88f 7577 if ( r_type != R_ARM_PC24
845b51d6 7578 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7579 continue;
7580
7581 /* Get the section contents if we haven't done so already. */
7582 if (contents == NULL)
7583 {
7584 /* Get cached copy if it exists. */
7585 if (elf_section_data (sec)->this_hdr.contents != NULL)
7586 contents = elf_section_data (sec)->this_hdr.contents;
7587 else
7588 {
7589 /* Go get them off disk. */
57e8b36a 7590 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7591 goto error_return;
7592 }
7593 }
7594
845b51d6
PB		 7595 if (r_type == R_ARM_V4BX)
7596 {
7597 int reg;
7598
7599 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7600 record_arm_bx_glue (link_info, reg);
7601 continue;
7602 }
7603
a7c10850 7604 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7605 h = NULL;
7606
9b485d32 7607 /* We don't care about local symbols. */
252b5132
RH		 7608 if (r_index < symtab_hdr->sh_info)
7609 continue;
7610
9b485d32 7611 /* This is an external symbol. */
252b5132
RH		 7612 r_index -= symtab_hdr->sh_info;
7613 h = (struct elf_link_hash_entry *)
7614 elf_sym_hashes (abfd)[r_index];
7615
7616 /* If the relocation is against a static symbol it must be within
7617 the current section and so cannot be a cross ARM/Thumb relocation. */
7618 if (h == NULL)
7619 continue;
7620
d504ffc8
DJ		 7621 /* If the call will go through a PLT entry then we do not need
7622 glue. */
362d30a1 7623 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7624 continue;
7625
252b5132
RH		 7626 switch (r_type)
7627 {
7628 case R_ARM_PC24:
7629 /* This one is a call from arm code. We need to look up
99059e56
RM		 7630 the target of the call. If it is a thumb target, we
7631 insert glue. */
39d911fc
TP		 7632 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7633 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7634 record_arm_to_thumb_glue (link_info, h);
7635 break;
7636
252b5132 7637 default:
c6596c5e 7638 abort ();
252b5132
RH		 7639 }
7640 }
6cdc0ccc
AM		 7641
7642 if (contents != NULL
7643 && elf_section_data (sec)->this_hdr.contents != contents)
7644 free (contents);
7645 contents = NULL;
7646
7647 if (internal_relocs != NULL
7648 && elf_section_data (sec)->relocs != internal_relocs)
7649 free (internal_relocs);
7650 internal_relocs = NULL;
252b5132
RH		 7651 }
7652
b34976b6 7653 return TRUE;
9a5aca8c 7654
252b5132 7655error_return:
6cdc0ccc
AM		 7656 if (contents != NULL
7657 && elf_section_data (sec)->this_hdr.contents != contents)
7658 free (contents);
7659 if (internal_relocs != NULL
7660 && elf_section_data (sec)->relocs != internal_relocs)
7661 free (internal_relocs);
9a5aca8c 7662
b34976b6 7663 return FALSE;
252b5132 7664}
7e392df6 7665#endif
252b5132 7666
eb043451 7667
c7b8f16e
JB		 7668/* Initialise maps of ARM/Thumb/data for input BFDs. */
7669
7670void
7671bfd_elf32_arm_init_maps (bfd *abfd)
7672{
7673 Elf_Internal_Sym *isymbuf;
7674 Elf_Internal_Shdr *hdr;
7675 unsigned int i, localsyms;
7676
af1f4419
NC		 7677 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7678 if (! is_arm_elf (abfd))
7679 return;
7680
c7b8f16e
JB		 7681 if ((abfd->flags & DYNAMIC) != 0)
7682 return;
7683
0ffa91dd 7684 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7685 localsyms = hdr->sh_info;
7686
7687 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7688 should contain the number of local symbols, which should come before any
7689 global symbols. Mapping symbols are always local. */
7690 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7691 NULL);
7692
7693 /* No internal symbols read? Skip this BFD. */
7694 if (isymbuf == NULL)
7695 return;
7696
7697 for (i = 0; i < localsyms; i++)
7698 {
7699 Elf_Internal_Sym *isym = &isymbuf[i];
7700 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
7701 const char *name;
906e58ca 7702
c7b8f16e 7703 if (sec != NULL
99059e56
RM		 7704 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
7705 {
7706 name = bfd_elf_string_from_elf_section (abfd,
7707 hdr->sh_link, isym->st_name);
906e58ca 7708
99059e56 7709 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 7710 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 7711 elf32_arm_section_map_add (sec, name[1], isym->st_value);
7712 }
c7b8f16e
JB		 7713 }
7714}
7715
7716
48229727
JB		 7717/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
7718 say what they wanted. */
7719
7720void
7721bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
7722{
7723 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7724 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7725
4dfe6ac6
NC		 7726 if (globals == NULL)
7727 return;
7728
48229727
JB		 7729 if (globals->fix_cortex_a8 == -1)
7730 {
7731 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
7732 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
7733 && (out_attr[Tag_CPU_arch_profile].i == 'A'
7734 || out_attr[Tag_CPU_arch_profile].i == 0))
7735 globals->fix_cortex_a8 = 1;
7736 else
7737 globals->fix_cortex_a8 = 0;
7738 }
7739}
7740
7741
c7b8f16e
JB		 7742void
7743bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
7744{
7745 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 7746 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 7747
4dfe6ac6
NC		 7748 if (globals == NULL)
7749 return;
c7b8f16e
JB		 7750 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
7751 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
7752 {
7753 switch (globals->vfp11_fix)
99059e56
RM		 7754 {
7755 case BFD_ARM_VFP11_FIX_DEFAULT:
7756 case BFD_ARM_VFP11_FIX_NONE:
7757 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7758 break;
7759
7760 default:
7761 /* Give a warning, but do as the user requests anyway. */
7762 (*_bfd_error_handler) (_("%B: warning: selected VFP11 erratum "
7763 "workaround is not necessary for target architecture"), obfd);
7764 }
c7b8f16e
JB		 7765 }
7766 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
7767 /* For earlier architectures, we might need the workaround, but do not
7768 enable it by default. If users is running with broken hardware, they
7769 must enable the erratum fix explicitly. */
7770 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7771}
7772
a504d23a
LA		 7773void
7774bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
7775{
7776 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7777 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7778
7779 if (globals == NULL)
7780 return;
7781
7782 /* We assume only Cortex-M4 may require the fix. */
7783 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
7784 || out_attr[Tag_CPU_arch_profile].i != 'M')
7785 {
7786 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
7787 /* Give a warning, but do as the user requests anyway. */
7788 (*_bfd_error_handler)
7789 (_("%B: warning: selected STM32L4XX erratum "
7790 "workaround is not necessary for target architecture"), obfd);
7791 }
7792}
c7b8f16e 7793
906e58ca
NC		 7794enum bfd_arm_vfp11_pipe
7795{
c7b8f16e
JB		 7796 VFP11_FMAC,
7797 VFP11_LS,
7798 VFP11_DS,
7799 VFP11_BAD
7800};
7801
7802/* Return a VFP register number. This is encoded as RX:X for single-precision
7803 registers, or X:RX for double-precision registers, where RX is the group of
7804 four bits in the instruction encoding and X is the single extension bit.
7805 RX and X fields are specified using their lowest (starting) bit. The return
7806 value is:
7807
7808 0...31: single-precision registers s0...s31
7809 32...63: double-precision registers d0...d31.
906e58ca 7810
c7b8f16e
JB		 7811 Although X should be zero for VFP11 (encoding d0...d15 only), we might
7812 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 7813
c7b8f16e
JB		 7814static unsigned int
7815bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 7816 unsigned int x)
c7b8f16e
JB		 7817{
7818 if (is_double)
7819 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
7820 else
7821 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
7822}
7823
7824/* Set bits in *WMASK according to a register number REG as encoded by
7825 bfd_arm_vfp11_regno(). Ignore d16-d31. */
7826
7827static void
7828bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
7829{
7830 if (reg < 32)
7831 *wmask |= 1 << reg;
7832 else if (reg < 48)
7833 *wmask |= 3 << ((reg - 32) * 2);
7834}
7835
7836/* Return TRUE if WMASK overwrites anything in REGS. */
7837
7838static bfd_boolean
7839bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
7840{
7841 int i;
906e58ca 7842
c7b8f16e
JB		 7843 for (i = 0; i < numregs; i++)
7844 {
7845 unsigned int reg = regs[i];
7846
7847 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 7848 return TRUE;
906e58ca 7849
c7b8f16e
JB		 7850 reg -= 32;
7851
7852 if (reg >= 16)
99059e56 7853 continue;
906e58ca 7854
c7b8f16e 7855 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 7856 return TRUE;
c7b8f16e 7857 }
906e58ca 7858
c7b8f16e
JB		 7859 return FALSE;
7860}
7861
7862/* In this function, we're interested in two things: finding input registers
7863 for VFP data-processing instructions, and finding the set of registers which
7864 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
7865 hold the written set, so FLDM etc. are easy to deal with (we're only
7866 interested in 32 SP registers or 16 dp registers, due to the VFP version
7867 implemented by the chip in question). DP registers are marked by setting
7868 both SP registers in the write mask). */
7869
7870static enum bfd_arm_vfp11_pipe
7871bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 7872 int *numregs)
c7b8f16e 7873{
91d6fa6a 7874 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 7875 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
7876
7877 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
7878 {
7879 unsigned int pqrs;
7880 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7881 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
7882
7883 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 7884 | ((insn & 0x00300000) >> 19)
7885 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 7886
7887 switch (pqrs)
99059e56
RM		 7888 {
7889 case 0: /* fmac[sd]. */
7890 case 1: /* fnmac[sd]. */
7891 case 2: /* fmsc[sd]. */
7892 case 3: /* fnmsc[sd]. */
7893 vpipe = VFP11_FMAC;
7894 bfd_arm_vfp11_write_mask (destmask, fd);
7895 regs[0] = fd;
7896 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7897 regs[2] = fm;
7898 *numregs = 3;
7899 break;
7900
7901 case 4: /* fmul[sd]. */
7902 case 5: /* fnmul[sd]. */
7903 case 6: /* fadd[sd]. */
7904 case 7: /* fsub[sd]. */
7905 vpipe = VFP11_FMAC;
7906 goto vfp_binop;
7907
7908 case 8: /* fdiv[sd]. */
7909 vpipe = VFP11_DS;
7910 vfp_binop:
7911 bfd_arm_vfp11_write_mask (destmask, fd);
7912 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7913 regs[1] = fm;
7914 *numregs = 2;
7915 break;
7916
7917 case 15: /* extended opcode. */
7918 {
7919 unsigned int extn = ((insn >> 15) & 0x1e)
7920 | ((insn >> 7) & 1);
7921
7922 switch (extn)
7923 {
7924 case 0: /* fcpy[sd]. */
7925 case 1: /* fabs[sd]. */
7926 case 2: /* fneg[sd]. */
7927 case 8: /* fcmp[sd]. */
7928 case 9: /* fcmpe[sd]. */
7929 case 10: /* fcmpz[sd]. */
7930 case 11: /* fcmpez[sd]. */
7931 case 16: /* fuito[sd]. */
7932 case 17: /* fsito[sd]. */
7933 case 24: /* ftoui[sd]. */
7934 case 25: /* ftouiz[sd]. */
7935 case 26: /* ftosi[sd]. */
7936 case 27: /* ftosiz[sd]. */
7937 /* These instructions will not bounce due to underflow. */
7938 *numregs = 0;
7939 vpipe = VFP11_FMAC;
7940 break;
7941
7942 case 3: /* fsqrt[sd]. */
7943 /* fsqrt cannot underflow, but it can (perhaps) overwrite
7944 registers to cause the erratum in previous instructions. */
7945 bfd_arm_vfp11_write_mask (destmask, fd);
7946 vpipe = VFP11_DS;
7947 break;
7948
7949 case 15: /* fcvt{ds,sd}. */
7950 {
7951 int rnum = 0;
7952
7953 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 7954
7955 /* Only FCVTSD can underflow. */
99059e56
RM		 7956 if ((insn & 0x100) != 0)
7957 regs[rnum++] = fm;
c7b8f16e 7958
99059e56 7959 *numregs = rnum;
c7b8f16e 7960
99059e56
RM		 7961 vpipe = VFP11_FMAC;
7962 }
7963 break;
c7b8f16e 7964
99059e56
RM		 7965 default:
7966 return VFP11_BAD;
7967 }
7968 }
7969 break;
c7b8f16e 7970
99059e56
RM		 7971 default:
7972 return VFP11_BAD;
7973 }
c7b8f16e
JB		 7974 }
7975 /* Two-register transfer. */
7976 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
7977 {
7978 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 7979
c7b8f16e
JB		 7980 if ((insn & 0x100000) == 0)
7981 {
99059e56
RM		 7982 if (is_double)
7983 bfd_arm_vfp11_write_mask (destmask, fm);
7984 else
7985 {
7986 bfd_arm_vfp11_write_mask (destmask, fm);
7987 bfd_arm_vfp11_write_mask (destmask, fm + 1);
7988 }
c7b8f16e
JB		 7989 }
7990
91d6fa6a 7991 vpipe = VFP11_LS;
c7b8f16e
JB		 7992 }
7993 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
7994 {
7995 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7996 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 7997
c7b8f16e 7998 switch (puw)
99059e56
RM		 7999 {
8000 case 0: /* Two-reg transfer. We should catch these above. */
8001 abort ();
906e58ca 8002
99059e56
RM		 8003 case 2: /* fldm[sdx]. */
8004 case 3:
8005 case 5:
8006 {
8007 unsigned int i, offset = insn & 0xff;
c7b8f16e 8008
99059e56
RM		 8009 if (is_double)
8010 offset >>= 1;
c7b8f16e 8011
99059e56
RM		 8012 for (i = fd; i < fd + offset; i++)
8013 bfd_arm_vfp11_write_mask (destmask, i);
8014 }
8015 break;
906e58ca 8016
99059e56
RM		 8017 case 4: /* fld[sd]. */
8018 case 6:
8019 bfd_arm_vfp11_write_mask (destmask, fd);
8020 break;
906e58ca 8021
99059e56
RM		 8022 default:
8023 return VFP11_BAD;
8024 }
c7b8f16e 8025
91d6fa6a 8026 vpipe = VFP11_LS;
c7b8f16e
JB		 8027 }
8028 /* Single-register transfer. Note L==0. */
8029 else if ((insn & 0x0f100e10) == 0x0e000a10)
8030 {
8031 unsigned int opcode = (insn >> 21) & 7;
8032 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8033
8034 switch (opcode)
99059e56
RM		 8035 {
8036 case 0: /* fmsr/fmdlr. */
8037 case 1: /* fmdhr. */
8038 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8039 destination register. I don't know if this is exactly right,
8040 but it is the conservative choice. */
8041 bfd_arm_vfp11_write_mask (destmask, fn);
8042 break;
8043
8044 case 7: /* fmxr. */
8045 break;
8046 }
c7b8f16e 8047
91d6fa6a 8048 vpipe = VFP11_LS;
c7b8f16e
JB		 8049 }
8050
91d6fa6a 8051 return vpipe;
c7b8f16e
JB		 8052}
8053
8054
8055static int elf32_arm_compare_mapping (const void * a, const void * b);
8056
8057
8058/* Look for potentially-troublesome code sequences which might trigger the
8059 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8060 (available from ARM) for details of the erratum. A short version is
8061 described in ld.texinfo. */
8062
8063bfd_boolean
8064bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8065{
8066 asection *sec;
8067 bfd_byte *contents = NULL;
8068 int state = 0;
8069 int regs[3], numregs = 0;
8070 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8071 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8072
4dfe6ac6
NC		 8073 if (globals == NULL)
8074 return FALSE;
8075
c7b8f16e
JB		 8076 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8077 The states transition as follows:
906e58ca 8078
c7b8f16e 8079 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8080 A VFP FMAC-pipeline instruction has been seen. Fill
8081 regs[0]..regs[numregs-1] with its input operands. Remember this
8082 instruction in 'first_fmac'.
c7b8f16e
JB		 8083
8084 1 -> 2
99059e56
RM		 8085 Any instruction, except for a VFP instruction which overwrites
8086 regs[*].
906e58ca 8087
c7b8f16e
JB		 8088 1 -> 3 [ -> 0 ] or
8089 2 -> 3 [ -> 0 ]
99059e56
RM		 8090 A VFP instruction has been seen which overwrites any of regs[*].
8091 We must make a veneer! Reset state to 0 before examining next
8092 instruction.
906e58ca 8093
c7b8f16e 8094 2 -> 0
99059e56
RM		 8095 If we fail to match anything in state 2, reset to state 0 and reset
8096 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8097
8098 If the VFP11 vector mode is in use, there must be at least two unrelated
8099 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8100 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8101
8102 /* If we are only performing a partial link do not bother
8103 to construct any glue. */
0e1862bb 8104 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8105 return TRUE;
8106
0ffa91dd
NC		 8107 /* Skip if this bfd does not correspond to an ELF image. */
8108 if (! is_arm_elf (abfd))
8109 return TRUE;
906e58ca 8110
c7b8f16e
JB		 8111 /* We should have chosen a fix type by the time we get here. */
8112 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8113
8114 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8115 return TRUE;
2e6030b9 8116
33a7ffc2
JM		 8117 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8118 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8119 return TRUE;
8120
c7b8f16e
JB		 8121 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8122 {
8123 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8124 struct _arm_elf_section_data *sec_data;
8125
8126 /* If we don't have executable progbits, we're not interested in this
99059e56 8127 section. Also skip if section is to be excluded. */
c7b8f16e 8128 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8129 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8130 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8131 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8132 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8133 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8134 continue;
c7b8f16e
JB		 8135
8136 sec_data = elf32_arm_section_data (sec);
906e58ca 8137
c7b8f16e 8138 if (sec_data->mapcount == 0)
99059e56 8139 continue;
906e58ca 8140
c7b8f16e
JB		 8141 if (elf_section_data (sec)->this_hdr.contents != NULL)
8142 contents = elf_section_data (sec)->this_hdr.contents;
8143 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8144 goto error_return;
8145
8146 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8147 elf32_arm_compare_mapping);
8148
8149 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8150 {
8151 unsigned int span_start = sec_data->map[span].vma;
8152 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8153 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8154 char span_type = sec_data->map[span].type;
8155
8156 /* FIXME: Only ARM mode is supported at present. We may need to
8157 support Thumb-2 mode also at some point. */
8158 if (span_type != 'a')
8159 continue;
8160
8161 for (i = span_start; i < span_end;)
8162 {
8163 unsigned int next_i = i + 4;
8164 unsigned int insn = bfd_big_endian (abfd)
8165 ? (contents[i] << 24)
8166 | (contents[i + 1] << 16)
8167 | (contents[i + 2] << 8)
8168 | contents[i + 3]
8169 : (contents[i + 3] << 24)
8170 | (contents[i + 2] << 16)
8171 | (contents[i + 1] << 8)
8172 | contents[i];
8173 unsigned int writemask = 0;
8174 enum bfd_arm_vfp11_pipe vpipe;
8175
8176 switch (state)
8177 {
8178 case 0:
8179 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8180 &numregs);
8181 /* I'm assuming the VFP11 erratum can trigger with denorm
8182 operands on either the FMAC or the DS pipeline. This might
8183 lead to slightly overenthusiastic veneer insertion. */
8184 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8185 {
8186 state = use_vector ? 1 : 2;
8187 first_fmac = i;
8188 veneer_of_insn = insn;
8189 }
8190 break;
8191
8192 case 1:
8193 {
8194 int other_regs[3], other_numregs;
8195 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8196 other_regs,
99059e56
RM		 8197 &other_numregs);
8198 if (vpipe != VFP11_BAD
8199 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8200 numregs))
99059e56
RM		 8201 state = 3;
8202 else
8203 state = 2;
8204 }
8205 break;
8206
8207 case 2:
8208 {
8209 int other_regs[3], other_numregs;
8210 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8211 other_regs,
99059e56
RM		 8212 &other_numregs);
8213 if (vpipe != VFP11_BAD
8214 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8215 numregs))
99059e56
RM		 8216 state = 3;
8217 else
8218 {
8219 state = 0;
8220 next_i = first_fmac + 4;
8221 }
8222 }
8223 break;
8224
8225 case 3:
8226 abort (); /* Should be unreachable. */
8227 }
8228
8229 if (state == 3)
8230 {
8231 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8232 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8233
8234 elf32_arm_section_data (sec)->erratumcount += 1;
8235
8236 newerr->u.b.vfp_insn = veneer_of_insn;
8237
8238 switch (span_type)
8239 {
8240 case 'a':
8241 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8242 break;
8243
8244 default:
8245 abort ();
8246 }
8247
8248 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8249 first_fmac);
8250
99059e56 8251 newerr->vma = -1;
c7b8f16e 8252
99059e56
RM		 8253 newerr->next = sec_data->erratumlist;
8254 sec_data->erratumlist = newerr;
c7b8f16e 8255
99059e56
RM		 8256 state = 0;
8257 }
c7b8f16e 8258
99059e56
RM		 8259 i = next_i;
8260 }
8261 }
906e58ca 8262
c7b8f16e 8263 if (contents != NULL
99059e56
RM		 8264 && elf_section_data (sec)->this_hdr.contents != contents)
8265 free (contents);
c7b8f16e
JB		 8266 contents = NULL;
8267 }
8268
8269 return TRUE;
8270
8271error_return:
8272 if (contents != NULL
8273 && elf_section_data (sec)->this_hdr.contents != contents)
8274 free (contents);
906e58ca 8275
c7b8f16e
JB		 8276 return FALSE;
8277}
8278
8279/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8280 after sections have been laid out, using specially-named symbols. */
8281
8282void
8283bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8284 struct bfd_link_info *link_info)
8285{
8286 asection *sec;
8287 struct elf32_arm_link_hash_table *globals;
8288 char *tmp_name;
906e58ca 8289
0e1862bb 8290 if (bfd_link_relocatable (link_info))
c7b8f16e 8291 return;
2e6030b9
MS		 8292
8293 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8294 if (! is_arm_elf (abfd))
2e6030b9
MS		 8295 return;
8296
c7b8f16e 8297 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8298 if (globals == NULL)
8299 return;
906e58ca 8300
21d799b5 8301 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8302 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8303
8304 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8305 {
8306 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8307 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8308
c7b8f16e 8309 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8310 {
8311 struct elf_link_hash_entry *myh;
8312 bfd_vma vma;
8313
8314 switch (errnode->type)
8315 {
8316 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8317 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8318 /* Find veneer symbol. */
8319 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8320 errnode->u.b.veneer->u.v.id);
8321
99059e56
RM		 8322 myh = elf_link_hash_lookup
8323 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8324
a504d23a
LA		 8325 if (myh == NULL)
8326 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
8327 "`%s'"), abfd, tmp_name);
8328
8329 vma = myh->root.u.def.section->output_section->vma
8330 + myh->root.u.def.section->output_offset
8331 + myh->root.u.def.value;
8332
8333 errnode->u.b.veneer->vma = vma;
8334 break;
8335
8336 case VFP11_ERRATUM_ARM_VENEER:
8337 case VFP11_ERRATUM_THUMB_VENEER:
8338 /* Find return location. */
8339 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8340 errnode->u.v.id);
8341
8342 myh = elf_link_hash_lookup
8343 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8344
8345 if (myh == NULL)
8346 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
8347 "`%s'"), abfd, tmp_name);
8348
8349 vma = myh->root.u.def.section->output_section->vma
8350 + myh->root.u.def.section->output_offset
8351 + myh->root.u.def.value;
8352
8353 errnode->u.v.branch->vma = vma;
8354 break;
8355
8356 default:
8357 abort ();
8358 }
8359 }
8360 }
8361
8362 free (tmp_name);
8363}
8364
8365/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8366 return locations after sections have been laid out, using
8367 specially-named symbols. */
8368
8369void
8370bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8371 struct bfd_link_info *link_info)
8372{
8373 asection *sec;
8374 struct elf32_arm_link_hash_table *globals;
8375 char *tmp_name;
8376
8377 if (bfd_link_relocatable (link_info))
8378 return;
8379
8380 /* Skip if this bfd does not correspond to an ELF image. */
8381 if (! is_arm_elf (abfd))
8382 return;
8383
8384 globals = elf32_arm_hash_table (link_info);
8385 if (globals == NULL)
8386 return;
8387
8388 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8389 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8390
8391 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8392 {
8393 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8394 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8395
8396 for (; errnode != NULL; errnode = errnode->next)
8397 {
8398 struct elf_link_hash_entry *myh;
8399 bfd_vma vma;
8400
8401 switch (errnode->type)
8402 {
8403 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8404 /* Find veneer symbol. */
8405 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8406 errnode->u.b.veneer->u.v.id);
8407
8408 myh = elf_link_hash_lookup
8409 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8410
8411 if (myh == NULL)
8412 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
8413 "`%s'"), abfd, tmp_name);
8414
8415 vma = myh->root.u.def.section->output_section->vma
8416 + myh->root.u.def.section->output_offset
8417 + myh->root.u.def.value;
8418
8419 errnode->u.b.veneer->vma = vma;
8420 break;
8421
8422 case STM32L4XX_ERRATUM_VENEER:
8423 /* Find return location. */
8424 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8425 errnode->u.v.id);
8426
8427 myh = elf_link_hash_lookup
8428 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8429
8430 if (myh == NULL)
8431 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
8432 "`%s'"), abfd, tmp_name);
8433
8434 vma = myh->root.u.def.section->output_section->vma
8435 + myh->root.u.def.section->output_offset
8436 + myh->root.u.def.value;
8437
8438 errnode->u.v.branch->vma = vma;
8439 break;
8440
8441 default:
8442 abort ();
8443 }
8444 }
8445 }
8446
8447 free (tmp_name);
8448}
8449
8450static inline bfd_boolean
8451is_thumb2_ldmia (const insn32 insn)
8452{
8453 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8454 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8455 return (insn & 0xffd02000) == 0xe8900000;
8456}
8457
8458static inline bfd_boolean
8459is_thumb2_ldmdb (const insn32 insn)
8460{
8461 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8462 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8463 return (insn & 0xffd02000) == 0xe9100000;
8464}
8465
8466static inline bfd_boolean
8467is_thumb2_vldm (const insn32 insn)
8468{
8469 /* A6.5 Extension register load or store instruction
8470 A7.7.229
9239bbd3
CM		 8471 We look for SP 32-bit and DP 64-bit registers.
8472 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8473 <list> is consecutive 64-bit registers
8474 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8475 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8476 <list> is consecutive 32-bit registers
8477 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8478 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8479 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8480 return
9239bbd3
CM		 8481 (((insn & 0xfe100f00) == 0xec100b00) ||
8482 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8483 && /* (IA without !). */
8484 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8485 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8486 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8487 /* (DB with !). */
8488 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8489}
8490
8491/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8492 VLDM opcode and:
8493 - computes the number and the mode of memory accesses
8494 - decides if the replacement should be done:
8495 . replaces only if > 8-word accesses
8496 . or (testing purposes only) replaces all accesses. */
8497
8498static bfd_boolean
8499stm32l4xx_need_create_replacing_stub (const insn32 insn,
8500 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8501{
9239bbd3 8502 int nb_words = 0;
a504d23a
LA		 8503
8504 /* The field encoding the register list is the same for both LDMIA
8505 and LDMDB encodings. */
8506 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
9239bbd3 8507 nb_words = popcount (insn & 0x0000ffff);
a504d23a 8508 else if (is_thumb2_vldm (insn))
9239bbd3 8509 nb_words = (insn & 0xff);
a504d23a
LA		 8510
8511 /* DEFAULT mode accounts for the real bug condition situation,
8512 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8513 return
9239bbd3 8514 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8515 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8516}
8517
8518/* Look for potentially-troublesome code sequences which might trigger
8519 the STM STM32L4XX erratum. */
8520
8521bfd_boolean
8522bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8523 struct bfd_link_info *link_info)
8524{
8525 asection *sec;
8526 bfd_byte *contents = NULL;
8527 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8528
8529 if (globals == NULL)
8530 return FALSE;
8531
8532 /* If we are only performing a partial link do not bother
8533 to construct any glue. */
8534 if (bfd_link_relocatable (link_info))
8535 return TRUE;
8536
8537 /* Skip if this bfd does not correspond to an ELF image. */
8538 if (! is_arm_elf (abfd))
8539 return TRUE;
8540
8541 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8542 return TRUE;
8543
8544 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8545 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8546 return TRUE;
8547
8548 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8549 {
8550 unsigned int i, span;
8551 struct _arm_elf_section_data *sec_data;
8552
8553 /* If we don't have executable progbits, we're not interested in this
8554 section. Also skip if section is to be excluded. */
8555 if (elf_section_type (sec) != SHT_PROGBITS
8556 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8557 || (sec->flags & SEC_EXCLUDE) != 0
8558 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8559 || sec->output_section == bfd_abs_section_ptr
8560 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8561 continue;
8562
8563 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8564
a504d23a
LA		 8565 if (sec_data->mapcount == 0)
8566 continue;
c7b8f16e 8567
a504d23a
LA		 8568 if (elf_section_data (sec)->this_hdr.contents != NULL)
8569 contents = elf_section_data (sec)->this_hdr.contents;
8570 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8571 goto error_return;
c7b8f16e 8572
a504d23a
LA		 8573 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8574 elf32_arm_compare_mapping);
c7b8f16e 8575
a504d23a
LA		 8576 for (span = 0; span < sec_data->mapcount; span++)
8577 {
8578 unsigned int span_start = sec_data->map[span].vma;
8579 unsigned int span_end = (span == sec_data->mapcount - 1)
8580 ? sec->size : sec_data->map[span + 1].vma;
8581 char span_type = sec_data->map[span].type;
8582 int itblock_current_pos = 0;
c7b8f16e 8583
a504d23a
LA		 8584 /* Only Thumb2 mode need be supported with this CM4 specific
8585 code, we should not encounter any arm mode eg span_type
8586 != 'a'. */
8587 if (span_type != 't')
8588 continue;
c7b8f16e 8589
a504d23a
LA		 8590 for (i = span_start; i < span_end;)
8591 {
8592 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8593 bfd_boolean insn_32bit = FALSE;
8594 bfd_boolean is_ldm = FALSE;
8595 bfd_boolean is_vldm = FALSE;
8596 bfd_boolean is_not_last_in_it_block = FALSE;
8597
8598 /* The first 16-bits of all 32-bit thumb2 instructions start
8599 with opcode[15..13]=0b111 and the encoded op1 can be anything
8600 except opcode[12..11]!=0b00.
8601 See 32-bit Thumb instruction encoding. */
8602 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8603 insn_32bit = TRUE;
c7b8f16e 8604
a504d23a
LA		 8605 /* Compute the predicate that tells if the instruction
8606 is concerned by the IT block
8607 - Creates an error if there is a ldm that is not
8608 last in the IT block thus cannot be replaced
8609 - Otherwise we can create a branch at the end of the
8610 IT block, it will be controlled naturally by IT
8611 with the proper pseudo-predicate
8612 - So the only interesting predicate is the one that
8613 tells that we are not on the last item of an IT
8614 block. */
8615 if (itblock_current_pos != 0)
8616 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8617
a504d23a
LA		 8618 if (insn_32bit)
8619 {
8620 /* Load the rest of the insn (in manual-friendly order). */
8621 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8622 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8623 is_vldm = is_thumb2_vldm (insn);
8624
8625 /* Veneers are created for (v)ldm depending on
8626 option flags and memory accesses conditions; but
8627 if the instruction is not the last instruction of
8628 an IT block, we cannot create a jump there, so we
8629 bail out. */
5025eb7c
AO		 8630 if ((is_ldm || is_vldm)
8631 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8632 (insn, globals->stm32l4xx_fix))
8633 {
8634 if (is_not_last_in_it_block)
8635 {
8636 (*_bfd_error_handler)
8637 /* Note - overlong line used here to allow for translation. */
8638 (_("\
8639%B(%A+0x%lx): error: multiple load detected in non-last IT block instruction : STM32L4XX veneer cannot be generated.\n"
8640 "Use gcc option -mrestrict-it to generate only one instruction per IT block.\n"),
8641 abfd, sec, (long)i);
8642 }
8643 else
8644 {
8645 elf32_stm32l4xx_erratum_list *newerr =
8646 (elf32_stm32l4xx_erratum_list *)
8647 bfd_zmalloc
8648 (sizeof (elf32_stm32l4xx_erratum_list));
8649
8650 elf32_arm_section_data (sec)
8651 ->stm32l4xx_erratumcount += 1;
8652 newerr->u.b.insn = insn;
8653 /* We create only thumb branches. */
8654 newerr->type =
8655 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8656 record_stm32l4xx_erratum_veneer
8657 (link_info, newerr, abfd, sec,
8658 i,
8659 is_ldm ?
8660 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8661 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8662 newerr->vma = -1;
8663 newerr->next = sec_data->stm32l4xx_erratumlist;
8664 sec_data->stm32l4xx_erratumlist = newerr;
8665 }
8666 }
8667 }
8668 else
8669 {
8670 /* A7.7.37 IT p208
8671 IT blocks are only encoded in T1
8672 Encoding T1: IT{x{y{z}}} <firstcond>
8673 1 0 1 1 - 1 1 1 1 - firstcond - mask
8674 if mask = '0000' then see 'related encodings'
8675 We don't deal with UNPREDICTABLE, just ignore these.
8676 There can be no nested IT blocks so an IT block
8677 is naturally a new one for which it is worth
8678 computing its size. */
5025eb7c
AO		 8679 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
8680 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 8681 /* If we have a new IT block we compute its size. */
8682 if (is_newitblock)
8683 {
8684 /* Compute the number of instructions controlled
8685 by the IT block, it will be used to decide
8686 whether we are inside an IT block or not. */
8687 unsigned int mask = insn & 0x000f;
8688 itblock_current_pos = 4 - ctz (mask);
8689 }
8690 }
8691
8692 i += insn_32bit ? 4 : 2;
99059e56
RM		 8693 }
8694 }
a504d23a
LA		 8695
8696 if (contents != NULL
8697 && elf_section_data (sec)->this_hdr.contents != contents)
8698 free (contents);
8699 contents = NULL;
c7b8f16e 8700 }
906e58ca 8701
a504d23a
LA		 8702 return TRUE;
8703
8704error_return:
8705 if (contents != NULL
8706 && elf_section_data (sec)->this_hdr.contents != contents)
8707 free (contents);
c7b8f16e 8708
a504d23a
LA		 8709 return FALSE;
8710}
c7b8f16e 8711
eb043451
PB		 8712/* Set target relocation values needed during linking. */
8713
8714void
68c39892 8715bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 8716 struct bfd_link_info *link_info,
68c39892 8717 struct elf32_arm_params *params)
eb043451
PB		 8718{
8719 struct elf32_arm_link_hash_table *globals;
8720
8721 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8722 if (globals == NULL)
8723 return;
eb043451 8724
68c39892
TP		 8725 globals->target1_is_rel = params->target1_is_rel;
8726 if (strcmp (params->target2_type, "rel") == 0)
eb043451 8727 globals->target2_reloc = R_ARM_REL32;
68c39892 8728 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 8729 globals->target2_reloc = R_ARM_ABS32;
68c39892 8730 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 8731 globals->target2_reloc = R_ARM_GOT_PREL;
8732 else
8733 {
8734 _bfd_error_handler (_("Invalid TARGET2 relocation type '%s'."),
68c39892 8735 params->target2_type);
eb043451 8736 }
68c39892
TP		 8737 globals->fix_v4bx = params->fix_v4bx;
8738 globals->use_blx |= params->use_blx;
8739 globals->vfp11_fix = params->vfp11_denorm_fix;
8740 globals->stm32l4xx_fix = params->stm32l4xx_fix;
8741 globals->pic_veneer = params->pic_veneer;
8742 globals->fix_cortex_a8 = params->fix_cortex_a8;
8743 globals->fix_arm1176 = params->fix_arm1176;
8744 globals->cmse_implib = params->cmse_implib;
8745 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 8746
0ffa91dd 8747 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 8748 elf_arm_tdata (output_bfd)->no_enum_size_warning
8749 = params->no_enum_size_warning;
8750 elf_arm_tdata (output_bfd)->no_wchar_size_warning
8751 = params->no_wchar_size_warning;
eb043451 8752}
eb043451 8753
12a0a0fd 8754/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 8755
12a0a0fd
PB		 8756static void
8757insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
8758{
8759 bfd_vma upper;
8760 bfd_vma lower;
8761 int reloc_sign;
8762
8763 BFD_ASSERT ((offset & 1) == 0);
8764
8765 upper = bfd_get_16 (abfd, insn);
8766 lower = bfd_get_16 (abfd, insn + 2);
8767 reloc_sign = (offset < 0) ? 1 : 0;
8768 upper = (upper & ~(bfd_vma) 0x7ff)
8769 | ((offset >> 12) & 0x3ff)
8770 | (reloc_sign << 10);
906e58ca 8771 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 8772 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
8773 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
8774 | ((offset >> 1) & 0x7ff);
8775 bfd_put_16 (abfd, upper, insn);
8776 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 8777}
8778
9b485d32
NC		 8779/* Thumb code calling an ARM function. */
8780
252b5132 8781static int
57e8b36a
NC		 8782elf32_thumb_to_arm_stub (struct bfd_link_info * info,
8783 const char * name,
8784 bfd * input_bfd,
8785 bfd * output_bfd,
8786 asection * input_section,
8787 bfd_byte * hit_data,
8788 asection * sym_sec,
8789 bfd_vma offset,
8790 bfd_signed_vma addend,
f2a9dd69
DJ		 8791 bfd_vma val,
8792 char **error_message)
252b5132 8793{
bcbdc74c 8794 asection * s = 0;
dc810e39 8795 bfd_vma my_offset;
252b5132 8796 long int ret_offset;
bcbdc74c
NC		 8797 struct elf_link_hash_entry * myh;
8798 struct elf32_arm_link_hash_table * globals;
252b5132 8799
f2a9dd69 8800 myh = find_thumb_glue (info, name, error_message);
252b5132 8801 if (myh == NULL)
b34976b6 8802 return FALSE;
252b5132
RH		 8803
8804 globals = elf32_arm_hash_table (info);
252b5132
RH		 8805 BFD_ASSERT (globals != NULL);
8806 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8807
8808 my_offset = myh->root.u.def.value;
8809
3d4d4302
AM		 8810 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8811 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 8812
8813 BFD_ASSERT (s != NULL);
8814 BFD_ASSERT (s->contents != NULL);
8815 BFD_ASSERT (s->output_section != NULL);
8816
8817 if ((my_offset & 0x01) == 0x01)
8818 {
8819 if (sym_sec != NULL
8820 && sym_sec->owner != NULL
8821 && !INTERWORK_FLAG (sym_sec->owner))
8822 {
8f615d07 8823 (*_bfd_error_handler)
d003868e 8824 (_("%B(%s): warning: interworking not enabled.\n"
3aaeb7d3 8825 " first occurrence: %B: Thumb call to ARM"),
d003868e 8826 sym_sec->owner, input_bfd, name);
252b5132 8827
b34976b6 8828 return FALSE;
252b5132
RH		 8829 }
8830
8831 --my_offset;
8832 myh->root.u.def.value = my_offset;
8833
52ab56c2
PB		 8834 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
8835 s->contents + my_offset);
252b5132 8836
52ab56c2
PB		 8837 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
8838 s->contents + my_offset + 2);
252b5132
RH		 8839
8840 ret_offset =
9b485d32
NC		 8841 /* Address of destination of the stub. */
8842 ((bfd_signed_vma) val)
252b5132 8843 - ((bfd_signed_vma)
57e8b36a
NC		 8844 /* Offset from the start of the current section
8845 to the start of the stubs. */
9b485d32
NC		 8846 (s->output_offset
8847 /* Offset of the start of this stub from the start of the stubs. */
8848 + my_offset
8849 /* Address of the start of the current section. */
8850 + s->output_section->vma)
8851 /* The branch instruction is 4 bytes into the stub. */
8852 + 4
8853 /* ARM branches work from the pc of the instruction + 8. */
8854 + 8);
252b5132 8855
52ab56c2
PB		 8856 put_arm_insn (globals, output_bfd,
8857 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
8858 s->contents + my_offset + 4);
252b5132
RH		 8859 }
8860
8861 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
8862
427bfd90
NC		 8863 /* Now go back and fix up the original BL insn to point to here. */
8864 ret_offset =
8865 /* Address of where the stub is located. */
8866 (s->output_section->vma + s->output_offset + my_offset)
8867 /* Address of where the BL is located. */
57e8b36a
NC		 8868 - (input_section->output_section->vma + input_section->output_offset
8869 + offset)
427bfd90
NC		 8870 /* Addend in the relocation. */
8871 - addend
8872 /* Biassing for PC-relative addressing. */
8873 - 8;
252b5132 8874
12a0a0fd 8875 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 8876
b34976b6 8877 return TRUE;
252b5132
RH		 8878}
8879
a4fd1a8e 8880/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 8881
a4fd1a8e
PB		 8882static struct elf_link_hash_entry *
8883elf32_arm_create_thumb_stub (struct bfd_link_info * info,
8884 const char * name,
8885 bfd * input_bfd,
8886 bfd * output_bfd,
8887 asection * sym_sec,
8888 bfd_vma val,
8029a119
NC		 8889 asection * s,
8890 char ** error_message)
252b5132 8891{
dc810e39 8892 bfd_vma my_offset;
252b5132 8893 long int ret_offset;
bcbdc74c
NC		 8894 struct elf_link_hash_entry * myh;
8895 struct elf32_arm_link_hash_table * globals;
252b5132 8896
f2a9dd69 8897 myh = find_arm_glue (info, name, error_message);
252b5132 8898 if (myh == NULL)
a4fd1a8e 8899 return NULL;
252b5132
RH		 8900
8901 globals = elf32_arm_hash_table (info);
252b5132
RH		 8902 BFD_ASSERT (globals != NULL);
8903 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8904
8905 my_offset = myh->root.u.def.value;
252b5132
RH		 8906
8907 if ((my_offset & 0x01) == 0x01)
8908 {
8909 if (sym_sec != NULL
8910 && sym_sec->owner != NULL
8911 && !INTERWORK_FLAG (sym_sec->owner))
8912 {
8f615d07 8913 (*_bfd_error_handler)
d003868e
AM		 8914 (_("%B(%s): warning: interworking not enabled.\n"
8915 " first occurrence: %B: arm call to thumb"),
8916 sym_sec->owner, input_bfd, name);
252b5132 8917 }
9b485d32 8918
252b5132
RH		 8919 --my_offset;
8920 myh->root.u.def.value = my_offset;
8921
0e1862bb
L		 8922 if (bfd_link_pic (info)
8923 || globals->root.is_relocatable_executable
27e55c4d 8924 || globals->pic_veneer)
8f6277f5
PB		 8925 {
8926 /* For relocatable objects we can't use absolute addresses,
8927 so construct the address from a relative offset. */
8928 /* TODO: If the offset is small it's probably worth
8929 constructing the address with adds. */
52ab56c2
PB		 8930 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
8931 s->contents + my_offset);
8932 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
8933 s->contents + my_offset + 4);
8934 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
8935 s->contents + my_offset + 8);
8f6277f5
PB		 8936 /* Adjust the offset by 4 for the position of the add,
8937 and 8 for the pipeline offset. */
8938 ret_offset = (val - (s->output_offset
8939 + s->output_section->vma
8940 + my_offset + 12))
8941 | 1;
8942 bfd_put_32 (output_bfd, ret_offset,
8943 s->contents + my_offset + 12);
8944 }
26079076
PB		 8945 else if (globals->use_blx)
8946 {
8947 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
8948 s->contents + my_offset);
8949
8950 /* It's a thumb address. Add the low order bit. */
8951 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
8952 s->contents + my_offset + 4);
8953 }
8f6277f5
PB		 8954 else
8955 {
52ab56c2
PB		 8956 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
8957 s->contents + my_offset);
252b5132 8958
52ab56c2
PB		 8959 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
8960 s->contents + my_offset + 4);
252b5132 8961
8f6277f5
PB		 8962 /* It's a thumb address. Add the low order bit. */
8963 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
8964 s->contents + my_offset + 8);
8029a119
NC		 8965
8966 my_offset += 12;
8f6277f5 8967 }
252b5132
RH		 8968 }
8969
8970 BFD_ASSERT (my_offset <= globals->arm_glue_size);
8971
a4fd1a8e
PB		 8972 return myh;
8973}
8974
8975/* Arm code calling a Thumb function. */
8976
8977static int
8978elf32_arm_to_thumb_stub (struct bfd_link_info * info,
8979 const char * name,
8980 bfd * input_bfd,
8981 bfd * output_bfd,
8982 asection * input_section,
8983 bfd_byte * hit_data,
8984 asection * sym_sec,
8985 bfd_vma offset,
8986 bfd_signed_vma addend,
f2a9dd69
DJ		 8987 bfd_vma val,
8988 char **error_message)
a4fd1a8e
PB		 8989{
8990 unsigned long int tmp;
8991 bfd_vma my_offset;
8992 asection * s;
8993 long int ret_offset;
8994 struct elf_link_hash_entry * myh;
8995 struct elf32_arm_link_hash_table * globals;
8996
8997 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8998 BFD_ASSERT (globals != NULL);
8999 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9000
3d4d4302
AM		 9001 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9002 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9003 BFD_ASSERT (s != NULL);
9004 BFD_ASSERT (s->contents != NULL);
9005 BFD_ASSERT (s->output_section != NULL);
9006
9007 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 9008 sym_sec, val, s, error_message);
a4fd1a8e
PB		 9009 if (!myh)
9010 return FALSE;
9011
9012 my_offset = myh->root.u.def.value;
252b5132
RH		 9013 tmp = bfd_get_32 (input_bfd, hit_data);
9014 tmp = tmp & 0xFF000000;
9015
9b485d32 9016 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9017 ret_offset = (s->output_offset
9018 + my_offset
9019 + s->output_section->vma
9020 - (input_section->output_offset
9021 + input_section->output_section->vma
9022 + offset + addend)
9023 - 8);
9a5aca8c 9024
252b5132
RH		 9025 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9026
dc810e39 9027 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9028
b34976b6 9029 return TRUE;
252b5132
RH		 9030}
9031
a4fd1a8e
PB		 9032/* Populate Arm stub for an exported Thumb function. */
9033
9034static bfd_boolean
9035elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9036{
9037 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9038 asection * s;
9039 struct elf_link_hash_entry * myh;
9040 struct elf32_arm_link_hash_entry *eh;
9041 struct elf32_arm_link_hash_table * globals;
9042 asection *sec;
9043 bfd_vma val;
f2a9dd69 9044 char *error_message;
a4fd1a8e 9045
906e58ca 9046 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9047 /* Allocate stubs for exported Thumb functions on v4t. */
9048 if (eh->export_glue == NULL)
9049 return TRUE;
9050
9051 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9052 BFD_ASSERT (globals != NULL);
9053 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9054
3d4d4302
AM		 9055 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9056 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9057 BFD_ASSERT (s != NULL);
9058 BFD_ASSERT (s->contents != NULL);
9059 BFD_ASSERT (s->output_section != NULL);
9060
9061 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9062
9063 BFD_ASSERT (sec->output_section != NULL);
9064
a4fd1a8e
PB		 9065 val = eh->export_glue->root.u.def.value + sec->output_offset
9066 + sec->output_section->vma;
8029a119 9067
a4fd1a8e
PB		 9068 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9069 h->root.u.def.section->owner,
f2a9dd69
DJ		 9070 globals->obfd, sec, val, s,
9071 &error_message);
a4fd1a8e
PB		 9072 BFD_ASSERT (myh);
9073 return TRUE;
9074}
9075
845b51d6
PB		 9076/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9077
9078static bfd_vma
9079elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9080{
9081 bfd_byte *p;
9082 bfd_vma glue_addr;
9083 asection *s;
9084 struct elf32_arm_link_hash_table *globals;
9085
9086 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9087 BFD_ASSERT (globals != NULL);
9088 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9089
3d4d4302
AM		 9090 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9091 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9092 BFD_ASSERT (s != NULL);
9093 BFD_ASSERT (s->contents != NULL);
9094 BFD_ASSERT (s->output_section != NULL);
9095
9096 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9097
9098 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9099
9100 if ((globals->bx_glue_offset[reg] & 1) == 0)
9101 {
9102 p = s->contents + glue_addr;
9103 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9104 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9105 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9106 globals->bx_glue_offset[reg] |= 1;
9107 }
9108
9109 return glue_addr + s->output_section->vma + s->output_offset;
9110}
9111
a4fd1a8e
PB		 9112/* Generate Arm stubs for exported Thumb symbols. */
9113static void
906e58ca 9114elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9115 struct bfd_link_info *link_info)
9116{
9117 struct elf32_arm_link_hash_table * globals;
9118
8029a119
NC		 9119 if (link_info == NULL)
9120 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9121 return;
9122
9123 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9124 if (globals == NULL)
9125 return;
9126
84c08195
PB		 9127 /* If blx is available then exported Thumb symbols are OK and there is
9128 nothing to do. */
a4fd1a8e
PB		 9129 if (globals->use_blx)
9130 return;
9131
9132 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9133 link_info);
9134}
9135
47beaa6a
RS		 9136/* Reserve space for COUNT dynamic relocations in relocation selection
9137 SRELOC. */
9138
9139static void
9140elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9141 bfd_size_type count)
9142{
9143 struct elf32_arm_link_hash_table *htab;
9144
9145 htab = elf32_arm_hash_table (info);
9146 BFD_ASSERT (htab->root.dynamic_sections_created);
9147 if (sreloc == NULL)
9148 abort ();
9149 sreloc->size += RELOC_SIZE (htab) * count;
9150}
9151
34e77a92
RS		 9152/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9153 dynamic, the relocations should go in SRELOC, otherwise they should
9154 go in the special .rel.iplt section. */
9155
9156static void
9157elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9158 bfd_size_type count)
9159{
9160 struct elf32_arm_link_hash_table *htab;
9161
9162 htab = elf32_arm_hash_table (info);
9163 if (!htab->root.dynamic_sections_created)
9164 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9165 else
9166 {
9167 BFD_ASSERT (sreloc != NULL);
9168 sreloc->size += RELOC_SIZE (htab) * count;
9169 }
9170}
9171
47beaa6a
RS		 9172/* Add relocation REL to the end of relocation section SRELOC. */
9173
9174static void
9175elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9176 asection *sreloc, Elf_Internal_Rela *rel)
9177{
9178 bfd_byte *loc;
9179 struct elf32_arm_link_hash_table *htab;
9180
9181 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9182 if (!htab->root.dynamic_sections_created
9183 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9184 sreloc = htab->root.irelplt;
47beaa6a
RS		 9185 if (sreloc == NULL)
9186 abort ();
9187 loc = sreloc->contents;
9188 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9189 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9190 abort ();
9191 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9192}
9193
34e77a92
RS		 9194/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9195 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9196 to .plt. */
9197
9198static void
9199elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9200 bfd_boolean is_iplt_entry,
9201 union gotplt_union *root_plt,
9202 struct arm_plt_info *arm_plt)
9203{
9204 struct elf32_arm_link_hash_table *htab;
9205 asection *splt;
9206 asection *sgotplt;
9207
9208 htab = elf32_arm_hash_table (info);
9209
9210 if (is_iplt_entry)
9211 {
9212 splt = htab->root.iplt;
9213 sgotplt = htab->root.igotplt;
9214
99059e56
RM		 9215 /* NaCl uses a special first entry in .iplt too. */
9216 if (htab->nacl_p && splt->size == 0)
9217 splt->size += htab->plt_header_size;
9218
34e77a92
RS		 9219 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9220 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9221 }
9222 else
9223 {
9224 splt = htab->root.splt;
9225 sgotplt = htab->root.sgotplt;
9226
9227 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9228 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9229
9230 /* If this is the first .plt entry, make room for the special
9231 first entry. */
9232 if (splt->size == 0)
9233 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9234
9235 htab->next_tls_desc_index++;
34e77a92
RS		 9236 }
9237
9238 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9239 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9240 splt->size += PLT_THUMB_STUB_SIZE;
9241 root_plt->offset = splt->size;
9242 splt->size += htab->plt_entry_size;
9243
9244 if (!htab->symbian_p)
9245 {
9246 /* We also need to make an entry in the .got.plt section, which
9247 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9248 if (is_iplt_entry)
9249 arm_plt->got_offset = sgotplt->size;
9250 else
9251 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 9252 sgotplt->size += 4;
9253 }
9254}
9255
b38cadfb
NC		 9256static bfd_vma
9257arm_movw_immediate (bfd_vma value)
9258{
9259 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9260}
9261
9262static bfd_vma
9263arm_movt_immediate (bfd_vma value)
9264{
9265 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9266}
9267
34e77a92
RS		 9268/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9269 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9270 Otherwise, DYNINDX is the index of the symbol in the dynamic
9271 symbol table and SYM_VALUE is undefined.
9272
9273 ROOT_PLT points to the offset of the PLT entry from the start of its
9274 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9275 bookkeeping information.
34e77a92 9276
57460bcf
NC		 9277 Returns FALSE if there was a problem. */
9278
9279static bfd_boolean
34e77a92
RS		 9280elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9281 union gotplt_union *root_plt,
9282 struct arm_plt_info *arm_plt,
9283 int dynindx, bfd_vma sym_value)
9284{
9285 struct elf32_arm_link_hash_table *htab;
9286 asection *sgot;
9287 asection *splt;
9288 asection *srel;
9289 bfd_byte *loc;
9290 bfd_vma plt_index;
9291 Elf_Internal_Rela rel;
9292 bfd_vma plt_header_size;
9293 bfd_vma got_header_size;
9294
9295 htab = elf32_arm_hash_table (info);
9296
9297 /* Pick the appropriate sections and sizes. */
9298 if (dynindx == -1)
9299 {
9300 splt = htab->root.iplt;
9301 sgot = htab->root.igotplt;
9302 srel = htab->root.irelplt;
9303
9304 /* There are no reserved entries in .igot.plt, and no special
9305 first entry in .iplt. */
9306 got_header_size = 0;
9307 plt_header_size = 0;
9308 }
9309 else
9310 {
9311 splt = htab->root.splt;
9312 sgot = htab->root.sgotplt;
9313 srel = htab->root.srelplt;
9314
9315 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9316 plt_header_size = htab->plt_header_size;
9317 }
9318 BFD_ASSERT (splt != NULL && srel != NULL);
9319
9320 /* Fill in the entry in the procedure linkage table. */
9321 if (htab->symbian_p)
9322 {
9323 BFD_ASSERT (dynindx >= 0);
9324 put_arm_insn (htab, output_bfd,
9325 elf32_arm_symbian_plt_entry[0],
9326 splt->contents + root_plt->offset);
9327 bfd_put_32 (output_bfd,
9328 elf32_arm_symbian_plt_entry[1],
9329 splt->contents + root_plt->offset + 4);
9330
9331 /* Fill in the entry in the .rel.plt section. */
9332 rel.r_offset = (splt->output_section->vma
9333 + splt->output_offset
9334 + root_plt->offset + 4);
9335 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9336
9337 /* Get the index in the procedure linkage table which
9338 corresponds to this symbol. This is the index of this symbol
9339 in all the symbols for which we are making plt entries. The
9340 first entry in the procedure linkage table is reserved. */
9341 plt_index = ((root_plt->offset - plt_header_size)
9342 / htab->plt_entry_size);
9343 }
9344 else
9345 {
9346 bfd_vma got_offset, got_address, plt_address;
9347 bfd_vma got_displacement, initial_got_entry;
9348 bfd_byte * ptr;
9349
9350 BFD_ASSERT (sgot != NULL);
9351
9352 /* Get the offset into the .(i)got.plt table of the entry that
9353 corresponds to this function. */
9354 got_offset = (arm_plt->got_offset & -2);
9355
9356 /* Get the index in the procedure linkage table which
9357 corresponds to this symbol. This is the index of this symbol
9358 in all the symbols for which we are making plt entries.
9359 After the reserved .got.plt entries, all symbols appear in
9360 the same order as in .plt. */
9361 plt_index = (got_offset - got_header_size) / 4;
9362
9363 /* Calculate the address of the GOT entry. */
9364 got_address = (sgot->output_section->vma
9365 + sgot->output_offset
9366 + got_offset);
9367
9368 /* ...and the address of the PLT entry. */
9369 plt_address = (splt->output_section->vma
9370 + splt->output_offset
9371 + root_plt->offset);
9372
9373 ptr = splt->contents + root_plt->offset;
0e1862bb 9374 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9375 {
9376 unsigned int i;
9377 bfd_vma val;
9378
9379 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9380 {
9381 val = elf32_arm_vxworks_shared_plt_entry[i];
9382 if (i == 2)
9383 val |= got_address - sgot->output_section->vma;
9384 if (i == 5)
9385 val |= plt_index * RELOC_SIZE (htab);
9386 if (i == 2 || i == 5)
9387 bfd_put_32 (output_bfd, val, ptr);
9388 else
9389 put_arm_insn (htab, output_bfd, val, ptr);
9390 }
9391 }
9392 else if (htab->vxworks_p)
9393 {
9394 unsigned int i;
9395 bfd_vma val;
9396
9397 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9398 {
9399 val = elf32_arm_vxworks_exec_plt_entry[i];
9400 if (i == 2)
9401 val |= got_address;
9402 if (i == 4)
9403 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9404 if (i == 5)
9405 val |= plt_index * RELOC_SIZE (htab);
9406 if (i == 2 || i == 5)
9407 bfd_put_32 (output_bfd, val, ptr);
9408 else
9409 put_arm_insn (htab, output_bfd, val, ptr);
9410 }
9411
9412 loc = (htab->srelplt2->contents
9413 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9414
9415 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9416 referencing the GOT for this PLT entry. */
9417 rel.r_offset = plt_address + 8;
9418 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9419 rel.r_addend = got_offset;
9420 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9421 loc += RELOC_SIZE (htab);
9422
9423 /* Create the R_ARM_ABS32 relocation referencing the
9424 beginning of the PLT for this GOT entry. */
9425 rel.r_offset = got_address;
9426 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9427 rel.r_addend = 0;
9428 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9429 }
b38cadfb
NC		 9430 else if (htab->nacl_p)
9431 {
9432 /* Calculate the displacement between the PLT slot and the
9433 common tail that's part of the special initial PLT slot. */
6034aab8 9434 int32_t tail_displacement
b38cadfb
NC		 9435 = ((splt->output_section->vma + splt->output_offset
9436 + ARM_NACL_PLT_TAIL_OFFSET)
9437 - (plt_address + htab->plt_entry_size + 4));
9438 BFD_ASSERT ((tail_displacement & 3) == 0);
9439 tail_displacement >>= 2;
9440
9441 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9442 || (-tail_displacement & 0xff000000) == 0);
9443
9444 /* Calculate the displacement between the PLT slot and the entry
9445 in the GOT. The offset accounts for the value produced by
9446 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9447 got_displacement = (got_address
99059e56 9448 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9449
9450 /* NaCl does not support interworking at all. */
9451 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9452
9453 put_arm_insn (htab, output_bfd,
9454 elf32_arm_nacl_plt_entry[0]
9455 | arm_movw_immediate (got_displacement),
9456 ptr + 0);
9457 put_arm_insn (htab, output_bfd,
9458 elf32_arm_nacl_plt_entry[1]
9459 | arm_movt_immediate (got_displacement),
9460 ptr + 4);
9461 put_arm_insn (htab, output_bfd,
9462 elf32_arm_nacl_plt_entry[2],
9463 ptr + 8);
9464 put_arm_insn (htab, output_bfd,
9465 elf32_arm_nacl_plt_entry[3]
9466 | (tail_displacement & 0x00ffffff),
9467 ptr + 12);
9468 }
57460bcf
NC		 9469 else if (using_thumb_only (htab))
9470 {
eed94f8f 9471 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9472 if (!using_thumb2 (htab))
eed94f8f
NC		 9473 {
9474 /* FIXME: We ought to be able to generate thumb-1 PLT
9475 instructions... */
9476 _bfd_error_handler (_("%B: Warning: thumb-1 mode PLT generation not currently supported"),
9477 output_bfd);
9478 return FALSE;
9479 }
57460bcf 9480
eed94f8f
NC		 9481 /* Calculate the displacement between the PLT slot and the entry in
9482 the GOT. The 12-byte offset accounts for the value produced by
9483 adding to pc in the 3rd instruction of the PLT stub. */
9484 got_displacement = got_address - (plt_address + 12);
9485
9486 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9487 instead of 'put_thumb_insn'. */
9488 put_arm_insn (htab, output_bfd,
9489 elf32_thumb2_plt_entry[0]
9490 | ((got_displacement & 0x000000ff) << 16)
9491 | ((got_displacement & 0x00000700) << 20)
9492 | ((got_displacement & 0x00000800) >> 1)
9493 | ((got_displacement & 0x0000f000) >> 12),
9494 ptr + 0);
9495 put_arm_insn (htab, output_bfd,
9496 elf32_thumb2_plt_entry[1]
9497 | ((got_displacement & 0x00ff0000) )
9498 | ((got_displacement & 0x07000000) << 4)
9499 | ((got_displacement & 0x08000000) >> 17)
9500 | ((got_displacement & 0xf0000000) >> 28),
9501 ptr + 4);
9502 put_arm_insn (htab, output_bfd,
9503 elf32_thumb2_plt_entry[2],
9504 ptr + 8);
9505 put_arm_insn (htab, output_bfd,
9506 elf32_thumb2_plt_entry[3],
9507 ptr + 12);
57460bcf 9508 }
34e77a92
RS		 9509 else
9510 {
9511 /* Calculate the displacement between the PLT slot and the
9512 entry in the GOT. The eight-byte offset accounts for the
9513 value produced by adding to pc in the first instruction
9514 of the PLT stub. */
9515 got_displacement = got_address - (plt_address + 8);
9516
34e77a92
RS		 9517 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9518 {
9519 put_thumb_insn (htab, output_bfd,
9520 elf32_arm_plt_thumb_stub[0], ptr - 4);
9521 put_thumb_insn (htab, output_bfd,
9522 elf32_arm_plt_thumb_stub[1], ptr - 2);
9523 }
9524
1db37fe6
YG		 9525 if (!elf32_arm_use_long_plt_entry)
9526 {
9527 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9528
9529 put_arm_insn (htab, output_bfd,
9530 elf32_arm_plt_entry_short[0]
9531 | ((got_displacement & 0x0ff00000) >> 20),
9532 ptr + 0);
9533 put_arm_insn (htab, output_bfd,
9534 elf32_arm_plt_entry_short[1]
9535 | ((got_displacement & 0x000ff000) >> 12),
9536 ptr+ 4);
9537 put_arm_insn (htab, output_bfd,
9538 elf32_arm_plt_entry_short[2]
9539 | (got_displacement & 0x00000fff),
9540 ptr + 8);
34e77a92 9541#ifdef FOUR_WORD_PLT
1db37fe6 9542 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9543#endif
1db37fe6
YG		 9544 }
9545 else
9546 {
9547 put_arm_insn (htab, output_bfd,
9548 elf32_arm_plt_entry_long[0]
9549 | ((got_displacement & 0xf0000000) >> 28),
9550 ptr + 0);
9551 put_arm_insn (htab, output_bfd,
9552 elf32_arm_plt_entry_long[1]
9553 | ((got_displacement & 0x0ff00000) >> 20),
9554 ptr + 4);
9555 put_arm_insn (htab, output_bfd,
9556 elf32_arm_plt_entry_long[2]
9557 | ((got_displacement & 0x000ff000) >> 12),
9558 ptr+ 8);
9559 put_arm_insn (htab, output_bfd,
9560 elf32_arm_plt_entry_long[3]
9561 | (got_displacement & 0x00000fff),
9562 ptr + 12);
9563 }
34e77a92
RS		 9564 }
9565
9566 /* Fill in the entry in the .rel(a).(i)plt section. */
9567 rel.r_offset = got_address;
9568 rel.r_addend = 0;
9569 if (dynindx == -1)
9570 {
9571 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9572 The dynamic linker or static executable then calls SYM_VALUE
9573 to determine the correct run-time value of the .igot.plt entry. */
9574 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9575 initial_got_entry = sym_value;
9576 }
9577 else
9578 {
9579 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9580 initial_got_entry = (splt->output_section->vma
9581 + splt->output_offset);
9582 }
9583
9584 /* Fill in the entry in the global offset table. */
9585 bfd_put_32 (output_bfd, initial_got_entry,
9586 sgot->contents + got_offset);
9587 }
9588
aba8c3de
WN		 9589 if (dynindx == -1)
9590 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9591 else
9592 {
9593 loc = srel->contents + plt_index * RELOC_SIZE (htab);
9594 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9595 }
57460bcf
NC		 9596
9597 return TRUE;
34e77a92
RS		 9598}
9599
eb043451
PB		 9600/* Some relocations map to different relocations depending on the
9601 target. Return the real relocation. */
8029a119 9602
eb043451
PB		 9603static int
9604arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
9605 int r_type)
9606{
9607 switch (r_type)
9608 {
9609 case R_ARM_TARGET1:
9610 if (globals->target1_is_rel)
9611 return R_ARM_REL32;
9612 else
9613 return R_ARM_ABS32;
9614
9615 case R_ARM_TARGET2:
9616 return globals->target2_reloc;
9617
9618 default:
9619 return r_type;
9620 }
9621}
eb043451 9622
ba93b8ac
DJ		 9623/* Return the base VMA address which should be subtracted from real addresses
9624 when resolving @dtpoff relocation.
9625 This is PT_TLS segment p_vaddr. */
9626
9627static bfd_vma
9628dtpoff_base (struct bfd_link_info *info)
9629{
9630 /* If tls_sec is NULL, we should have signalled an error already. */
9631 if (elf_hash_table (info)->tls_sec == NULL)
9632 return 0;
9633 return elf_hash_table (info)->tls_sec->vma;
9634}
9635
9636/* Return the relocation value for @tpoff relocation
9637 if STT_TLS virtual address is ADDRESS. */
9638
9639static bfd_vma
9640tpoff (struct bfd_link_info *info, bfd_vma address)
9641{
9642 struct elf_link_hash_table *htab = elf_hash_table (info);
9643 bfd_vma base;
9644
9645 /* If tls_sec is NULL, we should have signalled an error already. */
9646 if (htab->tls_sec == NULL)
9647 return 0;
9648 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
9649 return address - htab->tls_sec->vma + base;
9650}
9651
00a97672
RS		 9652/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
9653 VALUE is the relocation value. */
9654
9655static bfd_reloc_status_type
9656elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
9657{
9658 if (value > 0xfff)
9659 return bfd_reloc_overflow;
9660
9661 value |= bfd_get_32 (abfd, data) & 0xfffff000;
9662 bfd_put_32 (abfd, value, data);
9663 return bfd_reloc_ok;
9664}
9665
0855e32b
NS		 9666/* Handle TLS relaxations. Relaxing is possible for symbols that use
9667 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
9668 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
9669
9670 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
9671 is to then call final_link_relocate. Return other values in the
62672b10
NS		 9672 case of error.
9673
9674 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
9675 the pre-relaxed code. It would be nice if the relocs were updated
9676 to match the optimization. */
0855e32b 9677
b38cadfb 9678static bfd_reloc_status_type
0855e32b 9679elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 9680 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 9681 Elf_Internal_Rela *rel, unsigned long is_local)
9682{
9683 unsigned long insn;
b38cadfb 9684
0855e32b
NS		 9685 switch (ELF32_R_TYPE (rel->r_info))
9686 {
9687 default:
9688 return bfd_reloc_notsupported;
b38cadfb 9689
0855e32b
NS		 9690 case R_ARM_TLS_GOTDESC:
9691 if (is_local)
9692 insn = 0;
9693 else
9694 {
9695 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9696 if (insn & 1)
9697 insn -= 5; /* THUMB */
9698 else
9699 insn -= 8; /* ARM */
9700 }
9701 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9702 return bfd_reloc_continue;
9703
9704 case R_ARM_THM_TLS_DESCSEQ:
9705 /* Thumb insn. */
9706 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
9707 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
9708 {
9709 if (is_local)
9710 /* nop */
9711 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9712 }
9713 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
9714 {
9715 if (is_local)
9716 /* nop */
9717 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9718 else
9719 /* ldr rx,[ry] */
9720 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
9721 }
9722 else if ((insn & 0xff87) == 0x4780) /* blx rx */
9723 {
9724 if (is_local)
9725 /* nop */
9726 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9727 else
9728 /* mov r0, rx */
9729 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
9730 contents + rel->r_offset);
9731 }
9732 else
9733 {
9734 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
9735 /* It's a 32 bit instruction, fetch the rest of it for
9736 error generation. */
9737 insn = (insn << 16)
9738 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
9739 (*_bfd_error_handler)
9740 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' in TLS trampoline"),
9741 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
9742 return bfd_reloc_notsupported;
9743 }
9744 break;
b38cadfb 9745
0855e32b
NS		 9746 case R_ARM_TLS_DESCSEQ:
9747 /* arm insn. */
9748 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9749 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
9750 {
9751 if (is_local)
9752 /* mov rx, ry */
9753 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
9754 contents + rel->r_offset);
9755 }
9756 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
9757 {
9758 if (is_local)
9759 /* nop */
9760 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9761 else
9762 /* ldr rx,[ry] */
9763 bfd_put_32 (input_bfd, insn & 0xfffff000,
9764 contents + rel->r_offset);
9765 }
9766 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
9767 {
9768 if (is_local)
9769 /* nop */
9770 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9771 else
9772 /* mov r0, rx */
9773 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
9774 contents + rel->r_offset);
9775 }
9776 else
9777 {
9778 (*_bfd_error_handler)
9779 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' in TLS trampoline"),
9780 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
9781 return bfd_reloc_notsupported;
9782 }
9783 break;
9784
9785 case R_ARM_TLS_CALL:
9786 /* GD->IE relaxation, turn the instruction into 'nop' or
9787 'ldr r0, [pc,r0]' */
9788 insn = is_local ? 0xe1a00000 : 0xe79f0000;
9789 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9790 break;
b38cadfb 9791
0855e32b 9792 case R_ARM_THM_TLS_CALL:
6a631e86 9793 /* GD->IE relaxation. */
0855e32b
NS		 9794 if (!is_local)
9795 /* add r0,pc; ldr r0, [r0] */
9796 insn = 0x44786800;
60a019a0 9797 else if (using_thumb2 (globals))
0855e32b
NS		 9798 /* nop.w */
9799 insn = 0xf3af8000;
9800 else
9801 /* nop; nop */
9802 insn = 0xbf00bf00;
b38cadfb 9803
0855e32b
NS		 9804 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
9805 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
9806 break;
9807 }
9808 return bfd_reloc_ok;
9809}
9810
4962c51a
MS		 9811/* For a given value of n, calculate the value of G_n as required to
9812 deal with group relocations. We return it in the form of an
9813 encoded constant-and-rotation, together with the final residual. If n is
9814 specified as less than zero, then final_residual is filled with the
9815 input value and no further action is performed. */
9816
9817static bfd_vma
9818calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
9819{
9820 int current_n;
9821 bfd_vma g_n;
9822 bfd_vma encoded_g_n = 0;
9823 bfd_vma residual = value; /* Also known as Y_n. */
9824
9825 for (current_n = 0; current_n <= n; current_n++)
9826 {
9827 int shift;
9828
9829 /* Calculate which part of the value to mask. */
9830 if (residual == 0)
99059e56 9831 shift = 0;
4962c51a 9832 else
99059e56
RM		 9833 {
9834 int msb;
9835
9836 /* Determine the most significant bit in the residual and
9837 align the resulting value to a 2-bit boundary. */
9838 for (msb = 30; msb >= 0; msb -= 2)
9839 if (residual & (3 << msb))
9840 break;
9841
9842 /* The desired shift is now (msb - 6), or zero, whichever
9843 is the greater. */
9844 shift = msb - 6;
9845 if (shift < 0)
9846 shift = 0;
9847 }
4962c51a
MS		 9848
9849 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
9850 g_n = residual & (0xff << shift);
9851 encoded_g_n = (g_n >> shift)
99059e56 9852 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 9853
9854 /* Calculate the residual for the next time around. */
9855 residual &= ~g_n;
9856 }
9857
9858 *final_residual = residual;
9859
9860 return encoded_g_n;
9861}
9862
9863/* Given an ARM instruction, determine whether it is an ADD or a SUB.
9864 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 9865
4962c51a 9866static int
906e58ca 9867identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 9868{
9869 int opcode = insn & 0x1e00000;
9870
9871 if (opcode == 1 << 23) /* ADD */
9872 return 1;
9873
9874 if (opcode == 1 << 22) /* SUB */
9875 return -1;
9876
9877 return 0;
9878}
9879
252b5132 9880/* Perform a relocation as part of a final link. */
9b485d32 9881
252b5132 9882static bfd_reloc_status_type
57e8b36a
NC		 9883elf32_arm_final_link_relocate (reloc_howto_type * howto,
9884 bfd * input_bfd,
9885 bfd * output_bfd,
9886 asection * input_section,
9887 bfd_byte * contents,
9888 Elf_Internal_Rela * rel,
9889 bfd_vma value,
9890 struct bfd_link_info * info,
9891 asection * sym_sec,
9892 const char * sym_name,
34e77a92
RS		 9893 unsigned char st_type,
9894 enum arm_st_branch_type branch_type,
0945cdfd 9895 struct elf_link_hash_entry * h,
f2a9dd69 9896 bfd_boolean * unresolved_reloc_p,
8029a119 9897 char ** error_message)
252b5132
RH		 9898{
9899 unsigned long r_type = howto->type;
9900 unsigned long r_symndx;
9901 bfd_byte * hit_data = contents + rel->r_offset;
252b5132 9902 bfd_vma * local_got_offsets;
0855e32b 9903 bfd_vma * local_tlsdesc_gotents;
34e77a92
RS		 9904 asection * sgot;
9905 asection * splt;
252b5132 9906 asection * sreloc = NULL;
362d30a1 9907 asection * srelgot;
252b5132 9908 bfd_vma addend;
ba96a88f 9909 bfd_signed_vma signed_addend;
34e77a92
RS		 9910 unsigned char dynreloc_st_type;
9911 bfd_vma dynreloc_value;
ba96a88f 9912 struct elf32_arm_link_hash_table * globals;
34e77a92
RS		 9913 struct elf32_arm_link_hash_entry *eh;
9914 union gotplt_union *root_plt;
9915 struct arm_plt_info *arm_plt;
9916 bfd_vma plt_offset;
9917 bfd_vma gotplt_offset;
9918 bfd_boolean has_iplt_entry;
f21f3fe0 9919
9c504268 9920 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 9921 if (globals == NULL)
9922 return bfd_reloc_notsupported;
9c504268 9923
0ffa91dd
NC		 9924 BFD_ASSERT (is_arm_elf (input_bfd));
9925
9926 /* Some relocation types map to different relocations depending on the
9c504268 9927 target. We pick the right one here. */
eb043451 9928 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 9929
9930 /* It is possible to have linker relaxations on some TLS access
9931 models. Update our information here. */
9932 r_type = elf32_arm_tls_transition (info, r_type, h);
9933
eb043451
PB		 9934 if (r_type != howto->type)
9935 howto = elf32_arm_howto_from_type (r_type);
9c504268 9936
34e77a92 9937 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 9938 sgot = globals->root.sgot;
252b5132 9939 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 9940 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
9941
34e77a92
RS		 9942 if (globals->root.dynamic_sections_created)
9943 srelgot = globals->root.srelgot;
9944 else
9945 srelgot = NULL;
9946
252b5132
RH		 9947 r_symndx = ELF32_R_SYM (rel->r_info);
9948
4e7fd91e 9949 if (globals->use_rel)
ba96a88f 9950 {
4e7fd91e
PB		 9951 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
9952
9953 if (addend & ((howto->src_mask + 1) >> 1))
9954 {
9955 signed_addend = -1;
9956 signed_addend &= ~ howto->src_mask;
9957 signed_addend |= addend;
9958 }
9959 else
9960 signed_addend = addend;
ba96a88f
NC		 9961 }
9962 else
4e7fd91e 9963 addend = signed_addend = rel->r_addend;
f21f3fe0 9964
39f21624
NC		 9965 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
9966 are resolving a function call relocation. */
9967 if (using_thumb_only (globals)
9968 && (r_type == R_ARM_THM_CALL
9969 || r_type == R_ARM_THM_JUMP24)
9970 && branch_type == ST_BRANCH_TO_ARM)
9971 branch_type = ST_BRANCH_TO_THUMB;
9972
34e77a92
RS		 9973 /* Record the symbol information that should be used in dynamic
9974 relocations. */
9975 dynreloc_st_type = st_type;
9976 dynreloc_value = value;
9977 if (branch_type == ST_BRANCH_TO_THUMB)
9978 dynreloc_value |= 1;
9979
9980 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
9981 VALUE appropriately for relocations that we resolve at link time. */
9982 has_iplt_entry = FALSE;
4ba2ef8f
TP		 9983 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
9984 &arm_plt)
34e77a92
RS		 9985 && root_plt->offset != (bfd_vma) -1)
9986 {
9987 plt_offset = root_plt->offset;
9988 gotplt_offset = arm_plt->got_offset;
9989
9990 if (h == NULL || eh->is_iplt)
9991 {
9992 has_iplt_entry = TRUE;
9993 splt = globals->root.iplt;
9994
9995 /* Populate .iplt entries here, because not all of them will
9996 be seen by finish_dynamic_symbol. The lower bit is set if
9997 we have already populated the entry. */
9998 if (plt_offset & 1)
9999 plt_offset--;
10000 else
10001 {
57460bcf
NC		 10002 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
10003 -1, dynreloc_value))
10004 root_plt->offset |= 1;
10005 else
10006 return bfd_reloc_notsupported;
34e77a92
RS		 10007 }
10008
10009 /* Static relocations always resolve to the .iplt entry. */
10010 st_type = STT_FUNC;
10011 value = (splt->output_section->vma
10012 + splt->output_offset
10013 + plt_offset);
10014 branch_type = ST_BRANCH_TO_ARM;
10015
10016 /* If there are non-call relocations that resolve to the .iplt
10017 entry, then all dynamic ones must too. */
10018 if (arm_plt->noncall_refcount != 0)
10019 {
10020 dynreloc_st_type = st_type;
10021 dynreloc_value = value;
10022 }
10023 }
10024 else
10025 /* We populate the .plt entry in finish_dynamic_symbol. */
10026 splt = globals->root.splt;
10027 }
10028 else
10029 {
10030 splt = NULL;
10031 plt_offset = (bfd_vma) -1;
10032 gotplt_offset = (bfd_vma) -1;
10033 }
10034
252b5132
RH		 10035 switch (r_type)
10036 {
10037 case R_ARM_NONE:
28a094c2
DJ		 10038 /* We don't need to find a value for this symbol. It's just a
10039 marker. */
10040 *unresolved_reloc_p = FALSE;
252b5132
RH		 10041 return bfd_reloc_ok;
10042
00a97672
RS		 10043 case R_ARM_ABS12:
10044 if (!globals->vxworks_p)
10045 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10046
252b5132
RH		 10047 case R_ARM_PC24:
10048 case R_ARM_ABS32:
bb224fc3 10049 case R_ARM_ABS32_NOI:
252b5132 10050 case R_ARM_REL32:
bb224fc3 10051 case R_ARM_REL32_NOI:
5b5bb741
PB		 10052 case R_ARM_CALL:
10053 case R_ARM_JUMP24:
dfc5f959 10054 case R_ARM_XPC25:
eb043451 10055 case R_ARM_PREL31:
7359ea65 10056 case R_ARM_PLT32:
7359ea65
DJ		 10057 /* Handle relocations which should use the PLT entry. ABS32/REL32
10058 will use the symbol's value, which may point to a PLT entry, but we
10059 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10060 branches in this object should go to it, except if the PLT is too
10061 far away, in which case a long branch stub should be inserted. */
bb224fc3 10062 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10063 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10064 && r_type != R_ARM_CALL
10065 && r_type != R_ARM_JUMP24
10066 && r_type != R_ARM_PLT32)
34e77a92 10067 && plt_offset != (bfd_vma) -1)
7359ea65 10068 {
34e77a92
RS		 10069 /* If we've created a .plt section, and assigned a PLT entry
10070 to this function, it must either be a STT_GNU_IFUNC reference
10071 or not be known to bind locally. In other cases, we should
10072 have cleared the PLT entry by now. */
10073 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10074
10075 value = (splt->output_section->vma
10076 + splt->output_offset
34e77a92 10077 + plt_offset);
0945cdfd 10078 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10079 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10080 contents, rel->r_offset, value,
00a97672 10081 rel->r_addend);
7359ea65
DJ		 10082 }
10083
67687978
PB		 10084 /* When generating a shared object or relocatable executable, these
10085 relocations are copied into the output file to be resolved at
10086 run time. */
0e1862bb
L		 10087 if ((bfd_link_pic (info)
10088 || globals->root.is_relocatable_executable)
7359ea65 10089 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10090 && !(globals->vxworks_p
3348747a
NS		 10091 && strcmp (input_section->output_section->name,
10092 ".tls_vars") == 0)
bb224fc3 10093 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10094 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10095 && !(input_bfd == globals->stub_bfd
10096 && strstr (input_section->name, STUB_SUFFIX))
7359ea65
DJ		 10097 && (h == NULL
10098 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10099 || h->root.type != bfd_link_hash_undefweak)
10100 && r_type != R_ARM_PC24
5b5bb741
PB		 10101 && r_type != R_ARM_CALL
10102 && r_type != R_ARM_JUMP24
ee06dc07 10103 && r_type != R_ARM_PREL31
7359ea65 10104 && r_type != R_ARM_PLT32)
252b5132 10105 {
947216bf 10106 Elf_Internal_Rela outrel;
b34976b6 10107 bfd_boolean skip, relocate;
f21f3fe0 10108
52db4ec2
JW		 10109 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10110 && !h->def_regular)
10111 {
10112 char *v = _("shared object");
10113
0e1862bb 10114 if (bfd_link_executable (info))
52db4ec2
JW		 10115 v = _("PIE executable");
10116
10117 (*_bfd_error_handler)
10118 (_("%B: relocation %s against external or undefined symbol `%s'"
10119 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10120 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10121 return bfd_reloc_notsupported;
10122 }
10123
0945cdfd
DJ		 10124 *unresolved_reloc_p = FALSE;
10125
34e77a92 10126 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10127 {
83bac4b0
NC		 10128 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10129 ! globals->use_rel);
f21f3fe0 10130
83bac4b0 10131 if (sreloc == NULL)
252b5132 10132 return bfd_reloc_notsupported;
252b5132 10133 }
f21f3fe0 10134
b34976b6
AM		 10135 skip = FALSE;
10136 relocate = FALSE;
f21f3fe0 10137
00a97672 10138 outrel.r_addend = addend;
c629eae0
JJ		 10139 outrel.r_offset =
10140 _bfd_elf_section_offset (output_bfd, info, input_section,
10141 rel->r_offset);
10142 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10143 skip = TRUE;
0bb2d96a 10144 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10145 skip = TRUE, relocate = TRUE;
252b5132
RH		 10146 outrel.r_offset += (input_section->output_section->vma
10147 + input_section->output_offset);
f21f3fe0 10148
252b5132 10149 if (skip)
0bb2d96a 10150 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10151 else if (h != NULL
10152 && h->dynindx != -1
0e1862bb 10153 && (!bfd_link_pic (info)
a496fbc8 10154 || !SYMBOLIC_BIND (info, h)
f5385ebf 10155 || !h->def_regular))
5e681ec4 10156 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10157 else
10158 {
a16385dc
MM		 10159 int symbol;
10160
5e681ec4 10161 /* This symbol is local, or marked to become local. */
34e77a92 10162 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 10163 if (globals->symbian_p)
6366ff1e 10164 {
74541ad4
AM		 10165 asection *osec;
10166
6366ff1e
MM		 10167 /* On Symbian OS, the data segment and text segement
10168 can be relocated independently. Therefore, we
10169 must indicate the segment to which this
10170 relocation is relative. The BPABI allows us to
10171 use any symbol in the right segment; we just use
10172 the section symbol as it is convenient. (We
10173 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10174 will not appear in the dynamic symbol table.)
10175
10176 Note that the dynamic linker ignores the section
10177 symbol value, so we don't subtract osec->vma
10178 from the emitted reloc addend. */
10dbd1f3 10179 if (sym_sec)
74541ad4 10180 osec = sym_sec->output_section;
10dbd1f3 10181 else
74541ad4
AM		 10182 osec = input_section->output_section;
10183 symbol = elf_section_data (osec)->dynindx;
10184 if (symbol == 0)
10185 {
10186 struct elf_link_hash_table *htab = elf_hash_table (info);
10187
10188 if ((osec->flags & SEC_READONLY) == 0
10189 && htab->data_index_section != NULL)
10190 osec = htab->data_index_section;
10191 else
10192 osec = htab->text_index_section;
10193 symbol = elf_section_data (osec)->dynindx;
10194 }
6366ff1e
MM		 10195 BFD_ASSERT (symbol != 0);
10196 }
a16385dc
MM		 10197 else
10198 /* On SVR4-ish systems, the dynamic loader cannot
10199 relocate the text and data segments independently,
10200 so the symbol does not matter. */
10201 symbol = 0;
34e77a92
RS		 10202 if (dynreloc_st_type == STT_GNU_IFUNC)
10203 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10204 to the .iplt entry. Instead, every non-call reference
10205 must use an R_ARM_IRELATIVE relocation to obtain the
10206 correct run-time address. */
10207 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
10208 else
10209 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10210 if (globals->use_rel)
10211 relocate = TRUE;
10212 else
34e77a92 10213 outrel.r_addend += dynreloc_value;
252b5132 10214 }
f21f3fe0 10215
47beaa6a 10216 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10217
f21f3fe0 10218 /* If this reloc is against an external symbol, we do not want to
252b5132 10219 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10220 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10221 if (! relocate)
10222 return bfd_reloc_ok;
9a5aca8c 10223
f21f3fe0 10224 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10225 contents, rel->r_offset,
10226 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10227 }
10228 else switch (r_type)
10229 {
00a97672
RS		 10230 case R_ARM_ABS12:
10231 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10232
dfc5f959 10233 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10234 case R_ARM_CALL:
10235 case R_ARM_JUMP24:
8029a119 10236 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10237 case R_ARM_PLT32:
906e58ca 10238 {
906e58ca
NC		 10239 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10240
dfc5f959 10241 if (r_type == R_ARM_XPC25)
252b5132 10242 {
dfc5f959
NC		 10243 /* Check for Arm calling Arm function. */
10244 /* FIXME: Should we translate the instruction into a BL
10245 instruction instead ? */
35fc36a8 10246 if (branch_type != ST_BRANCH_TO_THUMB)
d003868e
AM		 10247 (*_bfd_error_handler)
10248 (_("\%B: Warning: Arm BLX instruction targets Arm function '%s'."),
10249 input_bfd,
10250 h ? h->root.root.string : "(local)");
dfc5f959 10251 }
155d87d7 10252 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10253 {
10254 /* Check for Arm calling Thumb function. */
35fc36a8 10255 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10256 {
f2a9dd69
DJ		 10257 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10258 output_bfd, input_section,
10259 hit_data, sym_sec, rel->r_offset,
10260 signed_addend, value,
10261 error_message))
10262 return bfd_reloc_ok;
10263 else
10264 return bfd_reloc_dangerous;
dfc5f959 10265 }
252b5132 10266 }
ba96a88f 10267
906e58ca 10268 /* Check if a stub has to be inserted because the
8029a119 10269 destination is too far or we are changing mode. */
155d87d7
CL		 10270 if ( r_type == R_ARM_CALL
10271 || r_type == R_ARM_JUMP24
10272 || r_type == R_ARM_PLT32)
906e58ca 10273 {
fe33d2fa
CL		 10274 enum elf32_arm_stub_type stub_type = arm_stub_none;
10275 struct elf32_arm_link_hash_entry *hash;
10276
10277 hash = (struct elf32_arm_link_hash_entry *) h;
10278 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10279 st_type, &branch_type,
10280 hash, value, sym_sec,
fe33d2fa 10281 input_bfd, sym_name);
5fa9e92f 10282
fe33d2fa 10283 if (stub_type != arm_stub_none)
906e58ca
NC		 10284 {
10285 /* The target is out of reach, so redirect the
10286 branch to the local stub for this function. */
906e58ca
NC		 10287 stub_entry = elf32_arm_get_stub_entry (input_section,
10288 sym_sec, h,
fe33d2fa
CL		 10289 rel, globals,
10290 stub_type);
9cd3e4e5
NC		 10291 {
10292 if (stub_entry != NULL)
10293 value = (stub_entry->stub_offset
10294 + stub_entry->stub_sec->output_offset
10295 + stub_entry->stub_sec->output_section->vma);
10296
10297 if (plt_offset != (bfd_vma) -1)
10298 *unresolved_reloc_p = FALSE;
10299 }
906e58ca 10300 }
fe33d2fa
CL		 10301 else
10302 {
10303 /* If the call goes through a PLT entry, make sure to
10304 check distance to the right destination address. */
34e77a92 10305 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10306 {
10307 value = (splt->output_section->vma
10308 + splt->output_offset
34e77a92 10309 + plt_offset);
fe33d2fa
CL		 10310 *unresolved_reloc_p = FALSE;
10311 /* The PLT entry is in ARM mode, regardless of the
10312 target function. */
35fc36a8 10313 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10314 }
10315 }
906e58ca
NC		 10316 }
10317
dea514f5
PB		 10318 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10319 where:
10320 S is the address of the symbol in the relocation.
10321 P is address of the instruction being relocated.
10322 A is the addend (extracted from the instruction) in bytes.
10323
10324 S is held in 'value'.
10325 P is the base address of the section containing the
10326 instruction plus the offset of the reloc into that
10327 section, ie:
10328 (input_section->output_section->vma +
10329 input_section->output_offset +
10330 rel->r_offset).
10331 A is the addend, converted into bytes, ie:
10332 (signed_addend * 4)
10333
10334 Note: None of these operations have knowledge of the pipeline
10335 size of the processor, thus it is up to the assembler to
10336 encode this information into the addend. */
10337 value -= (input_section->output_section->vma
10338 + input_section->output_offset);
10339 value -= rel->r_offset;
4e7fd91e
PB		 10340 if (globals->use_rel)
10341 value += (signed_addend << howto->size);
10342 else
10343 /* RELA addends do not have to be adjusted by howto->size. */
10344 value += signed_addend;
23080146 10345
dcb5e6e6
NC		 10346 signed_addend = value;
10347 signed_addend >>= howto->rightshift;
9a5aca8c 10348
5ab79981 10349 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10350 the next instruction unless a PLT entry will be created.
77b4f08f 10351 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10352 The jump to the next instruction is optimized as a NOP depending
10353 on the architecture. */
ffcb4889 10354 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10355 && plt_offset == (bfd_vma) -1)
77b4f08f 10356 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10357 {
cd1dac3d
DG		 10358 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10359
10360 if (arch_has_arm_nop (globals))
10361 value |= 0x0320f000;
10362 else
10363 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10364 }
10365 else
59f2c4e7 10366 {
9b485d32 10367 /* Perform a signed range check. */
dcb5e6e6 10368 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10369 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10370 return bfd_reloc_overflow;
9a5aca8c 10371
5ab79981 10372 addend = (value & 2);
39b41c9c 10373
5ab79981
PB		 10374 value = (signed_addend & howto->dst_mask)
10375 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10376
5ab79981
PB		 10377 if (r_type == R_ARM_CALL)
10378 {
155d87d7 10379 /* Set the H bit in the BLX instruction. */
35fc36a8 10380 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10381 {
10382 if (addend)
10383 value |= (1 << 24);
10384 else
10385 value &= ~(bfd_vma)(1 << 24);
10386 }
10387
5ab79981 10388 /* Select the correct instruction (BL or BLX). */
906e58ca 10389 /* Only if we are not handling a BL to a stub. In this
8029a119 10390 case, mode switching is performed by the stub. */
35fc36a8 10391 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10392 value |= (1 << 28);
63e1a0fc 10393 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10394 {
10395 value &= ~(bfd_vma)(1 << 28);
10396 value |= (1 << 24);
10397 }
39b41c9c
PB		 10398 }
10399 }
906e58ca 10400 }
252b5132 10401 break;
f21f3fe0 10402
252b5132
RH		 10403 case R_ARM_ABS32:
10404 value += addend;
35fc36a8 10405 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10406 value |= 1;
10407 break;
f21f3fe0 10408
bb224fc3
MS		 10409 case R_ARM_ABS32_NOI:
10410 value += addend;
10411 break;
10412
252b5132 10413 case R_ARM_REL32:
a8bc6c78 10414 value += addend;
35fc36a8 10415 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10416 value |= 1;
252b5132 10417 value -= (input_section->output_section->vma
62efb346 10418 + input_section->output_offset + rel->r_offset);
252b5132 10419 break;
eb043451 10420
bb224fc3
MS		 10421 case R_ARM_REL32_NOI:
10422 value += addend;
10423 value -= (input_section->output_section->vma
10424 + input_section->output_offset + rel->r_offset);
10425 break;
10426
eb043451
PB		 10427 case R_ARM_PREL31:
10428 value -= (input_section->output_section->vma
10429 + input_section->output_offset + rel->r_offset);
10430 value += signed_addend;
10431 if (! h || h->root.type != bfd_link_hash_undefweak)
10432 {
8029a119 10433 /* Check for overflow. */
eb043451
PB		 10434 if ((value ^ (value >> 1)) & (1 << 30))
10435 return bfd_reloc_overflow;
10436 }
10437 value &= 0x7fffffff;
10438 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10439 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10440 value |= 1;
10441 break;
252b5132 10442 }
f21f3fe0 10443
252b5132
RH		 10444 bfd_put_32 (input_bfd, value, hit_data);
10445 return bfd_reloc_ok;
10446
10447 case R_ARM_ABS8:
fd0fd00c
MJ		 10448 /* PR 16202: Refectch the addend using the correct size. */
10449 if (globals->use_rel)
10450 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10451 value += addend;
4e67d4ca
DG		 10452
10453 /* There is no way to tell whether the user intended to use a signed or
10454 unsigned addend. When checking for overflow we accept either,
10455 as specified by the AAELF. */
10456 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10457 return bfd_reloc_overflow;
10458
10459 bfd_put_8 (input_bfd, value, hit_data);
10460 return bfd_reloc_ok;
10461
10462 case R_ARM_ABS16:
fd0fd00c
MJ		 10463 /* PR 16202: Refectch the addend using the correct size. */
10464 if (globals->use_rel)
10465 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10466 value += addend;
10467
4e67d4ca
DG		 10468 /* See comment for R_ARM_ABS8. */
10469 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10470 return bfd_reloc_overflow;
10471
10472 bfd_put_16 (input_bfd, value, hit_data);
10473 return bfd_reloc_ok;
10474
252b5132 10475 case R_ARM_THM_ABS5:
9b485d32 10476 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10477 if (globals->use_rel)
10478 {
10479 /* Need to refetch addend. */
10480 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10481 /* ??? Need to determine shift amount from operand size. */
10482 addend >>= howto->rightshift;
10483 }
252b5132
RH		 10484 value += addend;
10485
10486 /* ??? Isn't value unsigned? */
10487 if ((long) value > 0x1f || (long) value < -0x10)
10488 return bfd_reloc_overflow;
10489
10490 /* ??? Value needs to be properly shifted into place first. */
10491 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10492 bfd_put_16 (input_bfd, value, hit_data);
10493 return bfd_reloc_ok;
10494
2cab6cc3
MS		 10495 case R_ARM_THM_ALU_PREL_11_0:
10496 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10497 {
10498 bfd_vma insn;
10499 bfd_signed_vma relocation;
10500
10501 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10502 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10503
99059e56
RM		 10504 if (globals->use_rel)
10505 {
10506 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10507 | ((insn & (1 << 26)) >> 15);
10508 if (insn & 0xf00000)
10509 signed_addend = -signed_addend;
10510 }
2cab6cc3
MS		 10511
10512 relocation = value + signed_addend;
79f08007 10513 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10514 + input_section->output_offset
10515 + rel->r_offset);
2cab6cc3 10516
b6518b38 10517 value = relocation;
2cab6cc3 10518
99059e56
RM		 10519 if (value >= 0x1000)
10520 return bfd_reloc_overflow;
2cab6cc3
MS		 10521
10522 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10523 | ((value & 0x700) << 4)
10524 | ((value & 0x800) << 15);
10525 if (relocation < 0)
10526 insn |= 0xa00000;
2cab6cc3
MS		 10527
10528 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10529 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10530
99059e56 10531 return bfd_reloc_ok;
2cab6cc3
MS		 10532 }
10533
e1ec24c6
NC		 10534 case R_ARM_THM_PC8:
10535 /* PR 10073: This reloc is not generated by the GNU toolchain,
10536 but it is supported for compatibility with third party libraries
10537 generated by other compilers, specifically the ARM/IAR. */
10538 {
10539 bfd_vma insn;
10540 bfd_signed_vma relocation;
10541
10542 insn = bfd_get_16 (input_bfd, hit_data);
10543
99059e56 10544 if (globals->use_rel)
79f08007 10545 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 10546
10547 relocation = value + addend;
79f08007 10548 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10549 + input_section->output_offset
10550 + rel->r_offset);
e1ec24c6 10551
b6518b38 10552 value = relocation;
e1ec24c6
NC		 10553
10554 /* We do not check for overflow of this reloc. Although strictly
10555 speaking this is incorrect, it appears to be necessary in order
10556 to work with IAR generated relocs. Since GCC and GAS do not
10557 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10558 a problem for them. */
10559 value &= 0x3fc;
10560
10561 insn = (insn & 0xff00) | (value >> 2);
10562
10563 bfd_put_16 (input_bfd, insn, hit_data);
10564
99059e56 10565 return bfd_reloc_ok;
e1ec24c6
NC		 10566 }
10567
2cab6cc3
MS		 10568 case R_ARM_THM_PC12:
10569 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10570 {
10571 bfd_vma insn;
10572 bfd_signed_vma relocation;
10573
10574 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10575 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10576
99059e56
RM		 10577 if (globals->use_rel)
10578 {
10579 signed_addend = insn & 0xfff;
10580 if (!(insn & (1 << 23)))
10581 signed_addend = -signed_addend;
10582 }
2cab6cc3
MS		 10583
10584 relocation = value + signed_addend;
79f08007 10585 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10586 + input_section->output_offset
10587 + rel->r_offset);
2cab6cc3 10588
b6518b38 10589 value = relocation;
2cab6cc3 10590
99059e56
RM		 10591 if (value >= 0x1000)
10592 return bfd_reloc_overflow;
2cab6cc3
MS		 10593
10594 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 10595 if (relocation >= 0)
10596 insn |= (1 << 23);
2cab6cc3
MS		 10597
10598 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10599 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10600
99059e56 10601 return bfd_reloc_ok;
2cab6cc3
MS		 10602 }
10603
dfc5f959 10604 case R_ARM_THM_XPC22:
c19d1205 10605 case R_ARM_THM_CALL:
bd97cb95 10606 case R_ARM_THM_JUMP24:
dfc5f959 10607 /* Thumb BL (branch long instruction). */
252b5132 10608 {
b34976b6 10609 bfd_vma relocation;
99059e56 10610 bfd_vma reloc_sign;
b34976b6
AM		 10611 bfd_boolean overflow = FALSE;
10612 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10613 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 10614 bfd_signed_vma reloc_signed_max;
10615 bfd_signed_vma reloc_signed_min;
b34976b6 10616 bfd_vma check;
252b5132 10617 bfd_signed_vma signed_check;
e95de063 10618 int bitsize;
cd1dac3d 10619 const int thumb2 = using_thumb2 (globals);
5e866f5a 10620 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 10621
5ab79981 10622 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 10623 the next instruction unless a PLT entry will be created.
10624 The jump to the next instruction is optimized as a NOP.W for
10625 Thumb-2 enabled architectures. */
19540007 10626 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 10627 && plt_offset == (bfd_vma) -1)
5ab79981 10628 {
60a019a0 10629 if (thumb2)
cd1dac3d
DG		 10630 {
10631 bfd_put_16 (input_bfd, 0xf3af, hit_data);
10632 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
10633 }
10634 else
10635 {
10636 bfd_put_16 (input_bfd, 0xe000, hit_data);
10637 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
10638 }
5ab79981
PB		 10639 return bfd_reloc_ok;
10640 }
10641
e95de063 10642 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 10643 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 10644 if (globals->use_rel)
10645 {
99059e56
RM		 10646 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
10647 bfd_vma upper = upper_insn & 0x3ff;
10648 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 10649 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
10650 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 10651 bfd_vma i1 = j1 ^ s ? 0 : 1;
10652 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 10653
99059e56
RM		 10654 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
10655 /* Sign extend. */
10656 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 10657
4e7fd91e
PB		 10658 signed_addend = addend;
10659 }
cb1afa5c 10660
dfc5f959
NC		 10661 if (r_type == R_ARM_THM_XPC22)
10662 {
10663 /* Check for Thumb to Thumb call. */
10664 /* FIXME: Should we translate the instruction into a BL
10665 instruction instead ? */
35fc36a8 10666 if (branch_type == ST_BRANCH_TO_THUMB)
d003868e
AM		 10667 (*_bfd_error_handler)
10668 (_("%B: Warning: Thumb BLX instruction targets thumb function '%s'."),
10669 input_bfd,
10670 h ? h->root.root.string : "(local)");
dfc5f959
NC		 10671 }
10672 else
252b5132 10673 {
dfc5f959
NC		 10674 /* If it is not a call to Thumb, assume call to Arm.
10675 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 10676 function call at all, but rather a long jump. Calls through
10677 the PLT do not require stubs. */
34e77a92 10678 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 10679 {
bd97cb95 10680 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10681 {
10682 /* Convert BL to BLX. */
10683 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10684 }
155d87d7
CL		 10685 else if (( r_type != R_ARM_THM_CALL)
10686 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 10687 {
10688 if (elf32_thumb_to_arm_stub
10689 (info, sym_name, input_bfd, output_bfd, input_section,
10690 hit_data, sym_sec, rel->r_offset, signed_addend, value,
10691 error_message))
10692 return bfd_reloc_ok;
10693 else
10694 return bfd_reloc_dangerous;
10695 }
da5938a2 10696 }
35fc36a8
RS		 10697 else if (branch_type == ST_BRANCH_TO_THUMB
10698 && globals->use_blx
bd97cb95 10699 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10700 {
10701 /* Make sure this is a BL. */
10702 lower_insn |= 0x1800;
10703 }
252b5132 10704 }
f21f3fe0 10705
fe33d2fa 10706 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 10707 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 10708 {
10709 /* Check if a stub has to be inserted because the destination
8029a119 10710 is too far. */
fe33d2fa
CL		 10711 struct elf32_arm_stub_hash_entry *stub_entry;
10712 struct elf32_arm_link_hash_entry *hash;
10713
10714 hash = (struct elf32_arm_link_hash_entry *) h;
10715
10716 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10717 st_type, &branch_type,
10718 hash, value, sym_sec,
fe33d2fa
CL		 10719 input_bfd, sym_name);
10720
10721 if (stub_type != arm_stub_none)
906e58ca
NC		 10722 {
10723 /* The target is out of reach or we are changing modes, so
10724 redirect the branch to the local stub for this
10725 function. */
10726 stub_entry = elf32_arm_get_stub_entry (input_section,
10727 sym_sec, h,
fe33d2fa
CL		 10728 rel, globals,
10729 stub_type);
906e58ca 10730 if (stub_entry != NULL)
9cd3e4e5
NC		 10731 {
10732 value = (stub_entry->stub_offset
10733 + stub_entry->stub_sec->output_offset
10734 + stub_entry->stub_sec->output_section->vma);
10735
10736 if (plt_offset != (bfd_vma) -1)
10737 *unresolved_reloc_p = FALSE;
10738 }
906e58ca 10739
f4ac8484 10740 /* If this call becomes a call to Arm, force BLX. */
155d87d7 10741 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 10742 {
10743 if ((stub_entry
10744 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 10745 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 10746 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10747 }
906e58ca
NC		 10748 }
10749 }
10750
fe33d2fa 10751 /* Handle calls via the PLT. */
34e77a92 10752 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10753 {
10754 value = (splt->output_section->vma
10755 + splt->output_offset
34e77a92 10756 + plt_offset);
fe33d2fa 10757
eed94f8f
NC		 10758 if (globals->use_blx
10759 && r_type == R_ARM_THM_CALL
10760 && ! using_thumb_only (globals))
fe33d2fa
CL		 10761 {
10762 /* If the Thumb BLX instruction is available, convert
10763 the BL to a BLX instruction to call the ARM-mode
10764 PLT entry. */
10765 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 10766 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10767 }
10768 else
10769 {
eed94f8f
NC		 10770 if (! using_thumb_only (globals))
10771 /* Target the Thumb stub before the ARM PLT entry. */
10772 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 10773 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 10774 }
10775 *unresolved_reloc_p = FALSE;
10776 }
10777
ba96a88f 10778 relocation = value + signed_addend;
f21f3fe0 10779
252b5132 10780 relocation -= (input_section->output_section->vma
ba96a88f
NC		 10781 + input_section->output_offset
10782 + rel->r_offset);
9a5aca8c 10783
252b5132
RH		 10784 check = relocation >> howto->rightshift;
10785
10786 /* If this is a signed value, the rightshift just dropped
10787 leading 1 bits (assuming twos complement). */
10788 if ((bfd_signed_vma) relocation >= 0)
10789 signed_check = check;
10790 else
10791 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
10792
e95de063
MS		 10793 /* Calculate the permissable maximum and minimum values for
10794 this relocation according to whether we're relocating for
10795 Thumb-2 or not. */
10796 bitsize = howto->bitsize;
5e866f5a 10797 if (!thumb2_bl)
e95de063 10798 bitsize -= 2;
f6ebfac0 10799 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 10800 reloc_signed_min = ~reloc_signed_max;
10801
252b5132 10802 /* Assumes two's complement. */
ba96a88f 10803 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 10804 overflow = TRUE;
252b5132 10805
bd97cb95 10806 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 10807 /* For a BLX instruction, make sure that the relocation is rounded up
10808 to a word boundary. This follows the semantics of the instruction
10809 which specifies that bit 1 of the target address will come from bit
10810 1 of the base address. */
10811 relocation = (relocation + 2) & ~ 3;
cb1afa5c 10812
e95de063
MS		 10813 /* Put RELOCATION back into the insn. Assumes two's complement.
10814 We use the Thumb-2 encoding, which is safe even if dealing with
10815 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 10816 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 10817 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 10818 | ((relocation >> 12) & 0x3ff)
10819 | (reloc_sign << 10);
906e58ca 10820 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 10821 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
10822 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
10823 | ((relocation >> 1) & 0x7ff);
c62e1cc3 10824
252b5132
RH		 10825 /* Put the relocated value back in the object file: */
10826 bfd_put_16 (input_bfd, upper_insn, hit_data);
10827 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10828
10829 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10830 }
10831 break;
10832
c19d1205
ZW		 10833 case R_ARM_THM_JUMP19:
10834 /* Thumb32 conditional branch instruction. */
10835 {
10836 bfd_vma relocation;
10837 bfd_boolean overflow = FALSE;
10838 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10839 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 10840 bfd_signed_vma reloc_signed_max = 0xffffe;
10841 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 10842 bfd_signed_vma signed_check;
c5423981
TG		 10843 enum elf32_arm_stub_type stub_type = arm_stub_none;
10844 struct elf32_arm_stub_hash_entry *stub_entry;
10845 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 10846
10847 /* Need to refetch the addend, reconstruct the top three bits,
10848 and squish the two 11 bit pieces together. */
10849 if (globals->use_rel)
10850 {
10851 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 10852 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 10853 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
10854 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
10855 bfd_vma lower = (lower_insn & 0x07ff);
10856
a00a1f35
MS		 10857 upper |= J1 << 6;
10858 upper |= J2 << 7;
10859 upper |= (!S) << 8;
c19d1205
ZW		 10860 upper -= 0x0100; /* Sign extend. */
10861
10862 addend = (upper << 12) | (lower << 1);
10863 signed_addend = addend;
10864 }
10865
bd97cb95 10866 /* Handle calls via the PLT. */
34e77a92 10867 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 10868 {
10869 value = (splt->output_section->vma
10870 + splt->output_offset
34e77a92 10871 + plt_offset);
bd97cb95
DJ		 10872 /* Target the Thumb stub before the ARM PLT entry. */
10873 value -= PLT_THUMB_STUB_SIZE;
10874 *unresolved_reloc_p = FALSE;
10875 }
10876
c5423981
TG		 10877 hash = (struct elf32_arm_link_hash_entry *)h;
10878
10879 stub_type = arm_type_of_stub (info, input_section, rel,
10880 st_type, &branch_type,
10881 hash, value, sym_sec,
10882 input_bfd, sym_name);
10883 if (stub_type != arm_stub_none)
10884 {
10885 stub_entry = elf32_arm_get_stub_entry (input_section,
10886 sym_sec, h,
10887 rel, globals,
10888 stub_type);
10889 if (stub_entry != NULL)
10890 {
10891 value = (stub_entry->stub_offset
10892 + stub_entry->stub_sec->output_offset
10893 + stub_entry->stub_sec->output_section->vma);
10894 }
10895 }
c19d1205 10896
99059e56 10897 relocation = value + signed_addend;
c19d1205
ZW		 10898 relocation -= (input_section->output_section->vma
10899 + input_section->output_offset
10900 + rel->r_offset);
a00a1f35 10901 signed_check = (bfd_signed_vma) relocation;
c19d1205 10902
c19d1205
ZW		 10903 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10904 overflow = TRUE;
10905
10906 /* Put RELOCATION back into the insn. */
10907 {
10908 bfd_vma S = (relocation & 0x00100000) >> 20;
10909 bfd_vma J2 = (relocation & 0x00080000) >> 19;
10910 bfd_vma J1 = (relocation & 0x00040000) >> 18;
10911 bfd_vma hi = (relocation & 0x0003f000) >> 12;
10912 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
10913
a00a1f35 10914 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 10915 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
10916 }
10917
10918 /* Put the relocated value back in the object file: */
10919 bfd_put_16 (input_bfd, upper_insn, hit_data);
10920 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10921
10922 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10923 }
10924
10925 case R_ARM_THM_JUMP11:
10926 case R_ARM_THM_JUMP8:
10927 case R_ARM_THM_JUMP6:
51c5503b
NC		 10928 /* Thumb B (branch) instruction). */
10929 {
6cf9e9fe 10930 bfd_signed_vma relocation;
51c5503b
NC		 10931 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
10932 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 10933 bfd_signed_vma signed_check;
10934
c19d1205
ZW		 10935 /* CZB cannot jump backward. */
10936 if (r_type == R_ARM_THM_JUMP6)
10937 reloc_signed_min = 0;
10938
4e7fd91e 10939 if (globals->use_rel)
6cf9e9fe 10940 {
4e7fd91e
PB		 10941 /* Need to refetch addend. */
10942 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10943 if (addend & ((howto->src_mask + 1) >> 1))
10944 {
10945 signed_addend = -1;
10946 signed_addend &= ~ howto->src_mask;
10947 signed_addend |= addend;
10948 }
10949 else
10950 signed_addend = addend;
10951 /* The value in the insn has been right shifted. We need to
10952 undo this, so that we can perform the address calculation
10953 in terms of bytes. */
10954 signed_addend <<= howto->rightshift;
6cf9e9fe 10955 }
6cf9e9fe 10956 relocation = value + signed_addend;
51c5503b
NC		 10957
10958 relocation -= (input_section->output_section->vma
10959 + input_section->output_offset
10960 + rel->r_offset);
10961
6cf9e9fe
NC		 10962 relocation >>= howto->rightshift;
10963 signed_check = relocation;
c19d1205
ZW		 10964
10965 if (r_type == R_ARM_THM_JUMP6)
10966 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
10967 else
10968 relocation &= howto->dst_mask;
51c5503b 10969 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 10970
51c5503b
NC		 10971 bfd_put_16 (input_bfd, relocation, hit_data);
10972
10973 /* Assumes two's complement. */
10974 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10975 return bfd_reloc_overflow;
10976
10977 return bfd_reloc_ok;
10978 }
cedb70c5 10979
8375c36b
PB		 10980 case R_ARM_ALU_PCREL7_0:
10981 case R_ARM_ALU_PCREL15_8:
10982 case R_ARM_ALU_PCREL23_15:
10983 {
10984 bfd_vma insn;
10985 bfd_vma relocation;
10986
10987 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 10988 if (globals->use_rel)
10989 {
10990 /* Extract the addend. */
10991 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
10992 signed_addend = addend;
10993 }
8375c36b
PB		 10994 relocation = value + signed_addend;
10995
10996 relocation -= (input_section->output_section->vma
10997 + input_section->output_offset
10998 + rel->r_offset);
10999 insn = (insn & ~0xfff)
11000 | ((howto->bitpos << 7) & 0xf00)
11001 | ((relocation >> howto->bitpos) & 0xff);
11002 bfd_put_32 (input_bfd, value, hit_data);
11003 }
11004 return bfd_reloc_ok;
11005
252b5132
RH		 11006 case R_ARM_GNU_VTINHERIT:
11007 case R_ARM_GNU_VTENTRY:
11008 return bfd_reloc_ok;
11009
c19d1205 11010 case R_ARM_GOTOFF32:
252b5132 11011 /* Relocation is relative to the start of the
99059e56 11012 global offset table. */
252b5132
RH		 11013
11014 BFD_ASSERT (sgot != NULL);
11015 if (sgot == NULL)
99059e56 11016 return bfd_reloc_notsupported;
9a5aca8c 11017
cedb70c5 11018 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11019 address by one, so that attempts to call the function pointer will
11020 correctly interpret it as Thumb code. */
35fc36a8 11021 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11022 value += 1;
11023
252b5132 11024 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11025 calculation. We always want the start of .got. If we
11026 define _GLOBAL_OFFSET_TABLE in a different way, as is
11027 permitted by the ABI, we might have to change this
11028 calculation. */
252b5132 11029 value -= sgot->output_section->vma;
f21f3fe0 11030 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11031 contents, rel->r_offset, value,
00a97672 11032 rel->r_addend);
252b5132
RH		 11033
11034 case R_ARM_GOTPC:
a7c10850 11035 /* Use global offset table as symbol value. */
252b5132 11036 BFD_ASSERT (sgot != NULL);
f21f3fe0 11037
252b5132 11038 if (sgot == NULL)
99059e56 11039 return bfd_reloc_notsupported;
252b5132 11040
0945cdfd 11041 *unresolved_reloc_p = FALSE;
252b5132 11042 value = sgot->output_section->vma;
f21f3fe0 11043 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11044 contents, rel->r_offset, value,
00a97672 11045 rel->r_addend);
f21f3fe0 11046
252b5132 11047 case R_ARM_GOT32:
eb043451 11048 case R_ARM_GOT_PREL:
252b5132 11049 /* Relocation is to the entry for this symbol in the
99059e56 11050 global offset table. */
252b5132
RH		 11051 if (sgot == NULL)
11052 return bfd_reloc_notsupported;
f21f3fe0 11053
34e77a92
RS		 11054 if (dynreloc_st_type == STT_GNU_IFUNC
11055 && plt_offset != (bfd_vma) -1
11056 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11057 {
11058 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11059 symbol, and the relocation resolves directly to the runtime
11060 target rather than to the .iplt entry. This means that any
11061 .got entry would be the same value as the .igot.plt entry,
11062 so there's no point creating both. */
11063 sgot = globals->root.igotplt;
11064 value = sgot->output_offset + gotplt_offset;
11065 }
11066 else if (h != NULL)
252b5132
RH		 11067 {
11068 bfd_vma off;
f21f3fe0 11069
252b5132
RH		 11070 off = h->got.offset;
11071 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11072 if ((off & 1) != 0)
252b5132 11073 {
b436d854
RS		 11074 /* We have already processsed one GOT relocation against
11075 this symbol. */
11076 off &= ~1;
11077 if (globals->root.dynamic_sections_created
11078 && !SYMBOL_REFERENCES_LOCAL (info, h))
11079 *unresolved_reloc_p = FALSE;
11080 }
11081 else
11082 {
11083 Elf_Internal_Rela outrel;
11084
6f820c85 11085 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11086 {
11087 /* If the symbol doesn't resolve locally in a static
11088 object, we have an undefined reference. If the
11089 symbol doesn't resolve locally in a dynamic object,
11090 it should be resolved by the dynamic linker. */
11091 if (globals->root.dynamic_sections_created)
11092 {
11093 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11094 *unresolved_reloc_p = FALSE;
11095 }
11096 else
11097 outrel.r_info = 0;
11098 outrel.r_addend = 0;
11099 }
252b5132
RH		 11100 else
11101 {
34e77a92 11102 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11103 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c
AO		 11104 else if (bfd_link_pic (info)
11105 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11106 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 11107 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11108 else
11109 outrel.r_info = 0;
34e77a92 11110 outrel.r_addend = dynreloc_value;
b436d854 11111 }
ee29b9fb 11112
b436d854
RS		 11113 /* The GOT entry is initialized to zero by default.
11114 See if we should install a different value. */
11115 if (outrel.r_addend != 0
11116 && (outrel.r_info == 0 || globals->use_rel))
11117 {
11118 bfd_put_32 (output_bfd, outrel.r_addend,
11119 sgot->contents + off);
11120 outrel.r_addend = 0;
252b5132 11121 }
f21f3fe0 11122
b436d854
RS		 11123 if (outrel.r_info != 0)
11124 {
11125 outrel.r_offset = (sgot->output_section->vma
11126 + sgot->output_offset
11127 + off);
11128 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11129 }
11130 h->got.offset |= 1;
11131 }
252b5132
RH		 11132 value = sgot->output_offset + off;
11133 }
11134 else
11135 {
11136 bfd_vma off;
f21f3fe0 11137
5025eb7c
AO		 11138 BFD_ASSERT (local_got_offsets != NULL
11139 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11140
252b5132 11141 off = local_got_offsets[r_symndx];
f21f3fe0 11142
252b5132
RH		 11143 /* The offset must always be a multiple of 4. We use the
11144 least significant bit to record whether we have already
9b485d32 11145 generated the necessary reloc. */
252b5132
RH		 11146 if ((off & 1) != 0)
11147 off &= ~1;
11148 else
11149 {
00a97672 11150 if (globals->use_rel)
34e77a92 11151 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 11152
0e1862bb 11153 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 11154 {
947216bf 11155 Elf_Internal_Rela outrel;
f21f3fe0 11156
34e77a92 11157 outrel.r_addend = addend + dynreloc_value;
252b5132 11158 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11159 + sgot->output_offset
252b5132 11160 + off);
34e77a92 11161 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11162 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 11163 else
11164 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 11165 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11166 }
f21f3fe0 11167
252b5132
RH		 11168 local_got_offsets[r_symndx] |= 1;
11169 }
f21f3fe0 11170
252b5132
RH		 11171 value = sgot->output_offset + off;
11172 }
eb043451
PB		 11173 if (r_type != R_ARM_GOT32)
11174 value += sgot->output_section->vma;
9a5aca8c 11175
f21f3fe0 11176 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11177 contents, rel->r_offset, value,
00a97672 11178 rel->r_addend);
f21f3fe0 11179
ba93b8ac
DJ		 11180 case R_ARM_TLS_LDO32:
11181 value = value - dtpoff_base (info);
11182
11183 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11184 contents, rel->r_offset, value,
11185 rel->r_addend);
ba93b8ac
DJ		 11186
11187 case R_ARM_TLS_LDM32:
11188 {
11189 bfd_vma off;
11190
362d30a1 11191 if (sgot == NULL)
ba93b8ac
DJ		 11192 abort ();
11193
11194 off = globals->tls_ldm_got.offset;
11195
11196 if ((off & 1) != 0)
11197 off &= ~1;
11198 else
11199 {
11200 /* If we don't know the module number, create a relocation
11201 for it. */
0e1862bb 11202 if (bfd_link_pic (info))
ba93b8ac
DJ		 11203 {
11204 Elf_Internal_Rela outrel;
ba93b8ac 11205
362d30a1 11206 if (srelgot == NULL)
ba93b8ac
DJ		 11207 abort ();
11208
00a97672 11209 outrel.r_addend = 0;
362d30a1
RS		 11210 outrel.r_offset = (sgot->output_section->vma
11211 + sgot->output_offset + off);
ba93b8ac
DJ		 11212 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11213
00a97672
RS		 11214 if (globals->use_rel)
11215 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11216 sgot->contents + off);
ba93b8ac 11217
47beaa6a 11218 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11219 }
11220 else
362d30a1 11221 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11222
11223 globals->tls_ldm_got.offset |= 1;
11224 }
11225
362d30a1 11226 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 11227 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
11228
11229 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11230 contents, rel->r_offset, value,
00a97672 11231 rel->r_addend);
ba93b8ac
DJ		 11232 }
11233
0855e32b
NS		 11234 case R_ARM_TLS_CALL:
11235 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 11236 case R_ARM_TLS_GD32:
11237 case R_ARM_TLS_IE32:
0855e32b
NS		 11238 case R_ARM_TLS_GOTDESC:
11239 case R_ARM_TLS_DESCSEQ:
11240 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11241 {
0855e32b
NS		 11242 bfd_vma off, offplt;
11243 int indx = 0;
ba93b8ac
DJ		 11244 char tls_type;
11245
0855e32b 11246 BFD_ASSERT (sgot != NULL);
ba93b8ac 11247
ba93b8ac
DJ		 11248 if (h != NULL)
11249 {
11250 bfd_boolean dyn;
11251 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11252 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11253 bfd_link_pic (info),
11254 h)
11255 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11256 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11257 {
11258 *unresolved_reloc_p = FALSE;
11259 indx = h->dynindx;
11260 }
11261 off = h->got.offset;
0855e32b 11262 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11263 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11264 }
11265 else
11266 {
0855e32b 11267 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11268 off = local_got_offsets[r_symndx];
0855e32b 11269 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11270 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11271 }
11272
0855e32b 11273 /* Linker relaxations happens from one of the
b38cadfb 11274 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11275 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11276 tls_type = GOT_TLS_IE;
0855e32b
NS		 11277
11278 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11279
11280 if ((off & 1) != 0)
11281 off &= ~1;
11282 else
11283 {
11284 bfd_boolean need_relocs = FALSE;
11285 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11286 int cur_off = off;
11287
11288 /* The GOT entries have not been initialized yet. Do it
11289 now, and emit any relocations. If both an IE GOT and a
11290 GD GOT are necessary, we emit the GD first. */
11291
0e1862bb 11292 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 11293 && (h == NULL
11294 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11295 || h->root.type != bfd_link_hash_undefweak))
11296 {
11297 need_relocs = TRUE;
0855e32b 11298 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11299 }
11300
0855e32b
NS		 11301 if (tls_type & GOT_TLS_GDESC)
11302 {
47beaa6a
RS		 11303 bfd_byte *loc;
11304
0855e32b
NS		 11305 /* We should have relaxed, unless this is an undefined
11306 weak symbol. */
11307 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 11308 || bfd_link_pic (info));
0855e32b 11309 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11310 <= globals->root.sgotplt->size);
0855e32b
NS		 11311
11312 outrel.r_addend = 0;
11313 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11314 + globals->root.sgotplt->output_offset
11315 + offplt
11316 + globals->sgotplt_jump_table_size);
b38cadfb 11317
0855e32b
NS		 11318 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11319 sreloc = globals->root.srelplt;
11320 loc = sreloc->contents;
11321 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11322 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11323 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11324
11325 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11326
11327 /* For globals, the first word in the relocation gets
11328 the relocation index and the top bit set, or zero,
11329 if we're binding now. For locals, it gets the
11330 symbol's offset in the tls section. */
99059e56 11331 bfd_put_32 (output_bfd,
0855e32b
NS		 11332 !h ? value - elf_hash_table (info)->tls_sec->vma
11333 : info->flags & DF_BIND_NOW ? 0
11334 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11335 globals->root.sgotplt->contents + offplt
11336 + globals->sgotplt_jump_table_size);
11337
0855e32b 11338 /* Second word in the relocation is always zero. */
99059e56 11339 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11340 globals->root.sgotplt->contents + offplt
11341 + globals->sgotplt_jump_table_size + 4);
0855e32b 11342 }
ba93b8ac
DJ		 11343 if (tls_type & GOT_TLS_GD)
11344 {
11345 if (need_relocs)
11346 {
00a97672 11347 outrel.r_addend = 0;
362d30a1
RS		 11348 outrel.r_offset = (sgot->output_section->vma
11349 + sgot->output_offset
00a97672 11350 + cur_off);
ba93b8ac 11351 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11352
00a97672
RS		 11353 if (globals->use_rel)
11354 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11355 sgot->contents + cur_off);
00a97672 11356
47beaa6a 11357 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11358
11359 if (indx == 0)
11360 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11361 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11362 else
11363 {
00a97672 11364 outrel.r_addend = 0;
ba93b8ac
DJ		 11365 outrel.r_info = ELF32_R_INFO (indx,
11366 R_ARM_TLS_DTPOFF32);
11367 outrel.r_offset += 4;
00a97672
RS		 11368
11369 if (globals->use_rel)
11370 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11371 sgot->contents + cur_off + 4);
00a97672 11372
47beaa6a
RS		 11373 elf32_arm_add_dynreloc (output_bfd, info,
11374 srelgot, &outrel);
ba93b8ac
DJ		 11375 }
11376 }
11377 else
11378 {
11379 /* If we are not emitting relocations for a
11380 general dynamic reference, then we must be in a
11381 static link or an executable link with the
11382 symbol binding locally. Mark it as belonging
11383 to module 1, the executable. */
11384 bfd_put_32 (output_bfd, 1,
362d30a1 11385 sgot->contents + cur_off);
ba93b8ac 11386 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11387 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11388 }
11389
11390 cur_off += 8;
11391 }
11392
11393 if (tls_type & GOT_TLS_IE)
11394 {
11395 if (need_relocs)
11396 {
00a97672
RS		 11397 if (indx == 0)
11398 outrel.r_addend = value - dtpoff_base (info);
11399 else
11400 outrel.r_addend = 0;
362d30a1
RS		 11401 outrel.r_offset = (sgot->output_section->vma
11402 + sgot->output_offset
ba93b8ac
DJ		 11403 + cur_off);
11404 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11405
00a97672
RS		 11406 if (globals->use_rel)
11407 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11408 sgot->contents + cur_off);
ba93b8ac 11409
47beaa6a 11410 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11411 }
11412 else
11413 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11414 sgot->contents + cur_off);
ba93b8ac
DJ		 11415 cur_off += 4;
11416 }
11417
11418 if (h != NULL)
11419 h->got.offset |= 1;
11420 else
11421 local_got_offsets[r_symndx] |= 1;
11422 }
11423
11424 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
11425 off += 8;
0855e32b
NS		 11426 else if (tls_type & GOT_TLS_GDESC)
11427 off = offplt;
11428
11429 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11430 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11431 {
11432 bfd_signed_vma offset;
12352d3f
PB		 11433 /* TLS stubs are arm mode. The original symbol is a
11434 data object, so branch_type is bogus. */
11435 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11436 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11437 = arm_type_of_stub (info, input_section, rel,
11438 st_type, &branch_type,
0855e32b
NS		 11439 (struct elf32_arm_link_hash_entry *)h,
11440 globals->tls_trampoline, globals->root.splt,
11441 input_bfd, sym_name);
11442
11443 if (stub_type != arm_stub_none)
11444 {
11445 struct elf32_arm_stub_hash_entry *stub_entry
11446 = elf32_arm_get_stub_entry
11447 (input_section, globals->root.splt, 0, rel,
11448 globals, stub_type);
11449 offset = (stub_entry->stub_offset
11450 + stub_entry->stub_sec->output_offset
11451 + stub_entry->stub_sec->output_section->vma);
11452 }
11453 else
11454 offset = (globals->root.splt->output_section->vma
11455 + globals->root.splt->output_offset
11456 + globals->tls_trampoline);
11457
11458 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11459 {
11460 unsigned long inst;
b38cadfb
NC		 11461
11462 offset -= (input_section->output_section->vma
11463 + input_section->output_offset
11464 + rel->r_offset + 8);
0855e32b
NS		 11465
11466 inst = offset >> 2;
11467 inst &= 0x00ffffff;
11468 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11469 }
11470 else
11471 {
11472 /* Thumb blx encodes the offset in a complicated
11473 fashion. */
11474 unsigned upper_insn, lower_insn;
11475 unsigned neg;
11476
b38cadfb
NC		 11477 offset -= (input_section->output_section->vma
11478 + input_section->output_offset
0855e32b 11479 + rel->r_offset + 4);
b38cadfb 11480
12352d3f
PB		 11481 if (stub_type != arm_stub_none
11482 && arm_stub_is_thumb (stub_type))
11483 {
11484 lower_insn = 0xd000;
11485 }
11486 else
11487 {
11488 lower_insn = 0xc000;
6a631e86 11489 /* Round up the offset to a word boundary. */
12352d3f
PB		 11490 offset = (offset + 2) & ~2;
11491 }
11492
0855e32b
NS		 11493 neg = offset < 0;
11494 upper_insn = (0xf000
11495 | ((offset >> 12) & 0x3ff)
11496 | (neg << 10));
12352d3f 11497 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 11498 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 11499 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 11500 bfd_put_16 (input_bfd, upper_insn, hit_data);
11501 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11502 return bfd_reloc_ok;
11503 }
11504 }
11505 /* These relocations needs special care, as besides the fact
11506 they point somewhere in .gotplt, the addend must be
11507 adjusted accordingly depending on the type of instruction
6a631e86 11508 we refer to. */
0855e32b
NS		 11509 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
11510 {
11511 unsigned long data, insn;
11512 unsigned thumb;
b38cadfb 11513
0855e32b
NS		 11514 data = bfd_get_32 (input_bfd, hit_data);
11515 thumb = data & 1;
11516 data &= ~1u;
b38cadfb 11517
0855e32b
NS		 11518 if (thumb)
11519 {
11520 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
11521 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
11522 insn = (insn << 16)
11523 | bfd_get_16 (input_bfd,
11524 contents + rel->r_offset - data + 2);
11525 if ((insn & 0xf800c000) == 0xf000c000)
11526 /* bl/blx */
11527 value = -6;
11528 else if ((insn & 0xffffff00) == 0x4400)
11529 /* add */
11530 value = -5;
11531 else
11532 {
11533 (*_bfd_error_handler)
11534 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' referenced by TLS_GOTDESC"),
11535 input_bfd, input_section,
11536 (unsigned long)rel->r_offset, insn);
11537 return bfd_reloc_notsupported;
11538 }
11539 }
11540 else
11541 {
11542 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
11543
11544 switch (insn >> 24)
11545 {
11546 case 0xeb: /* bl */
11547 case 0xfa: /* blx */
11548 value = -4;
11549 break;
11550
11551 case 0xe0: /* add */
11552 value = -8;
11553 break;
b38cadfb 11554
0855e32b
NS		 11555 default:
11556 (*_bfd_error_handler)
11557 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' referenced by TLS_GOTDESC"),
11558 input_bfd, input_section,
11559 (unsigned long)rel->r_offset, insn);
11560 return bfd_reloc_notsupported;
11561 }
11562 }
b38cadfb 11563
0855e32b
NS		 11564 value += ((globals->root.sgotplt->output_section->vma
11565 + globals->root.sgotplt->output_offset + off)
11566 - (input_section->output_section->vma
11567 + input_section->output_offset
11568 + rel->r_offset)
11569 + globals->sgotplt_jump_table_size);
11570 }
11571 else
11572 value = ((globals->root.sgot->output_section->vma
11573 + globals->root.sgot->output_offset + off)
11574 - (input_section->output_section->vma
11575 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 11576
11577 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11578 contents, rel->r_offset, value,
00a97672 11579 rel->r_addend);
ba93b8ac
DJ		 11580 }
11581
11582 case R_ARM_TLS_LE32:
3cbc1e5e 11583 if (bfd_link_dll (info))
ba93b8ac
DJ		 11584 {
11585 (*_bfd_error_handler)
11586 (_("%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object"),
11587 input_bfd, input_section,
11588 (long) rel->r_offset, howto->name);
46691134 11589 return bfd_reloc_notsupported;
ba93b8ac
DJ		 11590 }
11591 else
11592 value = tpoff (info, value);
906e58ca 11593
ba93b8ac 11594 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11595 contents, rel->r_offset, value,
11596 rel->r_addend);
ba93b8ac 11597
319850b4
JB		 11598 case R_ARM_V4BX:
11599 if (globals->fix_v4bx)
845b51d6
PB		 11600 {
11601 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 11602
845b51d6
PB		 11603 /* Ensure that we have a BX instruction. */
11604 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 11605
845b51d6
PB		 11606 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
11607 {
11608 /* Branch to veneer. */
11609 bfd_vma glue_addr;
11610 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
11611 glue_addr -= input_section->output_section->vma
11612 + input_section->output_offset
11613 + rel->r_offset + 8;
11614 insn = (insn & 0xf0000000) | 0x0a000000
11615 | ((glue_addr >> 2) & 0x00ffffff);
11616 }
11617 else
11618 {
11619 /* Preserve Rm (lowest four bits) and the condition code
11620 (highest four bits). Other bits encode MOV PC,Rm. */
11621 insn = (insn & 0xf000000f) | 0x01a0f000;
11622 }
319850b4 11623
845b51d6
PB		 11624 bfd_put_32 (input_bfd, insn, hit_data);
11625 }
319850b4
JB		 11626 return bfd_reloc_ok;
11627
b6895b4f
PB		 11628 case R_ARM_MOVW_ABS_NC:
11629 case R_ARM_MOVT_ABS:
11630 case R_ARM_MOVW_PREL_NC:
11631 case R_ARM_MOVT_PREL:
92f5d02b
MS		 11632 /* Until we properly support segment-base-relative addressing then
11633 we assume the segment base to be zero, as for the group relocations.
11634 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
11635 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
11636 case R_ARM_MOVW_BREL_NC:
11637 case R_ARM_MOVW_BREL:
11638 case R_ARM_MOVT_BREL:
b6895b4f
PB		 11639 {
11640 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
11641
11642 if (globals->use_rel)
11643 {
11644 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 11645 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11646 }
92f5d02b 11647
b6895b4f 11648 value += signed_addend;
b6895b4f
PB		 11649
11650 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
11651 value -= (input_section->output_section->vma
11652 + input_section->output_offset + rel->r_offset);
11653
92f5d02b 11654 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 11655 return bfd_reloc_overflow;
92f5d02b 11656
35fc36a8 11657 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11658 value |= 1;
11659
11660 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 11661 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 11662 value >>= 16;
11663
11664 insn &= 0xfff0f000;
11665 insn |= value & 0xfff;
11666 insn |= (value & 0xf000) << 4;
11667 bfd_put_32 (input_bfd, insn, hit_data);
11668 }
11669 return bfd_reloc_ok;
11670
11671 case R_ARM_THM_MOVW_ABS_NC:
11672 case R_ARM_THM_MOVT_ABS:
11673 case R_ARM_THM_MOVW_PREL_NC:
11674 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 11675 /* Until we properly support segment-base-relative addressing then
11676 we assume the segment base to be zero, as for the above relocations.
11677 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
11678 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
11679 as R_ARM_THM_MOVT_ABS. */
11680 case R_ARM_THM_MOVW_BREL_NC:
11681 case R_ARM_THM_MOVW_BREL:
11682 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 11683 {
11684 bfd_vma insn;
906e58ca 11685
b6895b4f
PB		 11686 insn = bfd_get_16 (input_bfd, hit_data) << 16;
11687 insn |= bfd_get_16 (input_bfd, hit_data + 2);
11688
11689 if (globals->use_rel)
11690 {
11691 addend = ((insn >> 4) & 0xf000)
11692 | ((insn >> 15) & 0x0800)
11693 | ((insn >> 4) & 0x0700)
11694 | (insn & 0x00ff);
39623e12 11695 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11696 }
92f5d02b 11697
b6895b4f 11698 value += signed_addend;
b6895b4f
PB		 11699
11700 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
11701 value -= (input_section->output_section->vma
11702 + input_section->output_offset + rel->r_offset);
11703
92f5d02b 11704 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 11705 return bfd_reloc_overflow;
92f5d02b 11706
35fc36a8 11707 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11708 value |= 1;
11709
11710 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 11711 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 11712 value >>= 16;
11713
11714 insn &= 0xfbf08f00;
11715 insn |= (value & 0xf000) << 4;
11716 insn |= (value & 0x0800) << 15;
11717 insn |= (value & 0x0700) << 4;
11718 insn |= (value & 0x00ff);
11719
11720 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11721 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11722 }
11723 return bfd_reloc_ok;
11724
4962c51a
MS		 11725 case R_ARM_ALU_PC_G0_NC:
11726 case R_ARM_ALU_PC_G1_NC:
11727 case R_ARM_ALU_PC_G0:
11728 case R_ARM_ALU_PC_G1:
11729 case R_ARM_ALU_PC_G2:
11730 case R_ARM_ALU_SB_G0_NC:
11731 case R_ARM_ALU_SB_G1_NC:
11732 case R_ARM_ALU_SB_G0:
11733 case R_ARM_ALU_SB_G1:
11734 case R_ARM_ALU_SB_G2:
11735 {
11736 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11737 bfd_vma pc = input_section->output_section->vma
4962c51a 11738 + input_section->output_offset + rel->r_offset;
31a91d61 11739 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11740 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 11741 bfd_vma residual;
11742 bfd_vma g_n;
4962c51a 11743 bfd_signed_vma signed_value;
99059e56
RM		 11744 int group = 0;
11745
11746 /* Determine which group of bits to select. */
11747 switch (r_type)
11748 {
11749 case R_ARM_ALU_PC_G0_NC:
11750 case R_ARM_ALU_PC_G0:
11751 case R_ARM_ALU_SB_G0_NC:
11752 case R_ARM_ALU_SB_G0:
11753 group = 0;
11754 break;
11755
11756 case R_ARM_ALU_PC_G1_NC:
11757 case R_ARM_ALU_PC_G1:
11758 case R_ARM_ALU_SB_G1_NC:
11759 case R_ARM_ALU_SB_G1:
11760 group = 1;
11761 break;
11762
11763 case R_ARM_ALU_PC_G2:
11764 case R_ARM_ALU_SB_G2:
11765 group = 2;
11766 break;
11767
11768 default:
11769 abort ();
11770 }
11771
11772 /* If REL, extract the addend from the insn. If RELA, it will
11773 have already been fetched for us. */
4962c51a 11774 if (globals->use_rel)
99059e56
RM		 11775 {
11776 int negative;
11777 bfd_vma constant = insn & 0xff;
11778 bfd_vma rotation = (insn & 0xf00) >> 8;
11779
11780 if (rotation == 0)
11781 signed_addend = constant;
11782 else
11783 {
11784 /* Compensate for the fact that in the instruction, the
11785 rotation is stored in multiples of 2 bits. */
11786 rotation *= 2;
11787
11788 /* Rotate "constant" right by "rotation" bits. */
11789 signed_addend = (constant >> rotation) |
11790 (constant << (8 * sizeof (bfd_vma) - rotation));
11791 }
11792
11793 /* Determine if the instruction is an ADD or a SUB.
11794 (For REL, this determines the sign of the addend.) */
11795 negative = identify_add_or_sub (insn);
11796 if (negative == 0)
11797 {
11798 (*_bfd_error_handler)
11799 (_("%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations"),
11800 input_bfd, input_section,
11801 (long) rel->r_offset, howto->name);
11802 return bfd_reloc_overflow;
11803 }
11804
11805 signed_addend *= negative;
11806 }
4962c51a
MS		 11807
11808 /* Compute the value (X) to go in the place. */
99059e56
RM		 11809 if (r_type == R_ARM_ALU_PC_G0_NC
11810 || r_type == R_ARM_ALU_PC_G1_NC
11811 || r_type == R_ARM_ALU_PC_G0
11812 || r_type == R_ARM_ALU_PC_G1
11813 || r_type == R_ARM_ALU_PC_G2)
11814 /* PC relative. */
11815 signed_value = value - pc + signed_addend;
11816 else
11817 /* Section base relative. */
11818 signed_value = value - sb + signed_addend;
11819
11820 /* If the target symbol is a Thumb function, then set the
11821 Thumb bit in the address. */
35fc36a8 11822 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 11823 signed_value |= 1;
11824
99059e56
RM		 11825 /* Calculate the value of the relevant G_n, in encoded
11826 constant-with-rotation format. */
b6518b38
NC		 11827 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11828 group, &residual);
99059e56
RM		 11829
11830 /* Check for overflow if required. */
11831 if ((r_type == R_ARM_ALU_PC_G0
11832 || r_type == R_ARM_ALU_PC_G1
11833 || r_type == R_ARM_ALU_PC_G2
11834 || r_type == R_ARM_ALU_SB_G0
11835 || r_type == R_ARM_ALU_SB_G1
11836 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
11837 {
11838 (*_bfd_error_handler)
11839 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
11840 input_bfd, input_section,
b6518b38
NC		 11841 (long) rel->r_offset, signed_value < 0 ? - signed_value : signed_value,
11842 howto->name);
99059e56
RM		 11843 return bfd_reloc_overflow;
11844 }
11845
11846 /* Mask out the value and the ADD/SUB part of the opcode; take care
11847 not to destroy the S bit. */
11848 insn &= 0xff1ff000;
11849
11850 /* Set the opcode according to whether the value to go in the
11851 place is negative. */
11852 if (signed_value < 0)
11853 insn |= 1 << 22;
11854 else
11855 insn |= 1 << 23;
11856
11857 /* Encode the offset. */
11858 insn |= g_n;
4962c51a
MS		 11859
11860 bfd_put_32 (input_bfd, insn, hit_data);
11861 }
11862 return bfd_reloc_ok;
11863
11864 case R_ARM_LDR_PC_G0:
11865 case R_ARM_LDR_PC_G1:
11866 case R_ARM_LDR_PC_G2:
11867 case R_ARM_LDR_SB_G0:
11868 case R_ARM_LDR_SB_G1:
11869 case R_ARM_LDR_SB_G2:
11870 {
11871 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11872 bfd_vma pc = input_section->output_section->vma
4962c51a 11873 + input_section->output_offset + rel->r_offset;
31a91d61 11874 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11875 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11876 bfd_vma residual;
4962c51a 11877 bfd_signed_vma signed_value;
99059e56
RM		 11878 int group = 0;
11879
11880 /* Determine which groups of bits to calculate. */
11881 switch (r_type)
11882 {
11883 case R_ARM_LDR_PC_G0:
11884 case R_ARM_LDR_SB_G0:
11885 group = 0;
11886 break;
11887
11888 case R_ARM_LDR_PC_G1:
11889 case R_ARM_LDR_SB_G1:
11890 group = 1;
11891 break;
11892
11893 case R_ARM_LDR_PC_G2:
11894 case R_ARM_LDR_SB_G2:
11895 group = 2;
11896 break;
11897
11898 default:
11899 abort ();
11900 }
11901
11902 /* If REL, extract the addend from the insn. If RELA, it will
11903 have already been fetched for us. */
4962c51a 11904 if (globals->use_rel)
99059e56
RM		 11905 {
11906 int negative = (insn & (1 << 23)) ? 1 : -1;
11907 signed_addend = negative * (insn & 0xfff);
11908 }
4962c51a
MS		 11909
11910 /* Compute the value (X) to go in the place. */
99059e56
RM		 11911 if (r_type == R_ARM_LDR_PC_G0
11912 || r_type == R_ARM_LDR_PC_G1
11913 || r_type == R_ARM_LDR_PC_G2)
11914 /* PC relative. */
11915 signed_value = value - pc + signed_addend;
11916 else
11917 /* Section base relative. */
11918 signed_value = value - sb + signed_addend;
11919
11920 /* Calculate the value of the relevant G_{n-1} to obtain
11921 the residual at that stage. */
b6518b38
NC		 11922 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11923 group - 1, &residual);
99059e56
RM		 11924
11925 /* Check for overflow. */
11926 if (residual >= 0x1000)
11927 {
11928 (*_bfd_error_handler)
11929 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 11930 input_bfd, input_section,
11931 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11932 return bfd_reloc_overflow;
11933 }
11934
11935 /* Mask out the value and U bit. */
11936 insn &= 0xff7ff000;
11937
11938 /* Set the U bit if the value to go in the place is non-negative. */
11939 if (signed_value >= 0)
11940 insn |= 1 << 23;
11941
11942 /* Encode the offset. */
11943 insn |= residual;
4962c51a
MS		 11944
11945 bfd_put_32 (input_bfd, insn, hit_data);
11946 }
11947 return bfd_reloc_ok;
11948
11949 case R_ARM_LDRS_PC_G0:
11950 case R_ARM_LDRS_PC_G1:
11951 case R_ARM_LDRS_PC_G2:
11952 case R_ARM_LDRS_SB_G0:
11953 case R_ARM_LDRS_SB_G1:
11954 case R_ARM_LDRS_SB_G2:
11955 {
11956 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11957 bfd_vma pc = input_section->output_section->vma
4962c51a 11958 + input_section->output_offset + rel->r_offset;
31a91d61 11959 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11960 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11961 bfd_vma residual;
4962c51a 11962 bfd_signed_vma signed_value;
99059e56
RM		 11963 int group = 0;
11964
11965 /* Determine which groups of bits to calculate. */
11966 switch (r_type)
11967 {
11968 case R_ARM_LDRS_PC_G0:
11969 case R_ARM_LDRS_SB_G0:
11970 group = 0;
11971 break;
11972
11973 case R_ARM_LDRS_PC_G1:
11974 case R_ARM_LDRS_SB_G1:
11975 group = 1;
11976 break;
11977
11978 case R_ARM_LDRS_PC_G2:
11979 case R_ARM_LDRS_SB_G2:
11980 group = 2;
11981 break;
11982
11983 default:
11984 abort ();
11985 }
11986
11987 /* If REL, extract the addend from the insn. If RELA, it will
11988 have already been fetched for us. */
4962c51a 11989 if (globals->use_rel)
99059e56
RM		 11990 {
11991 int negative = (insn & (1 << 23)) ? 1 : -1;
11992 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
11993 }
4962c51a
MS		 11994
11995 /* Compute the value (X) to go in the place. */
99059e56
RM		 11996 if (r_type == R_ARM_LDRS_PC_G0
11997 || r_type == R_ARM_LDRS_PC_G1
11998 || r_type == R_ARM_LDRS_PC_G2)
11999 /* PC relative. */
12000 signed_value = value - pc + signed_addend;
12001 else
12002 /* Section base relative. */
12003 signed_value = value - sb + signed_addend;
12004
12005 /* Calculate the value of the relevant G_{n-1} to obtain
12006 the residual at that stage. */
b6518b38
NC		 12007 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12008 group - 1, &residual);
99059e56
RM		 12009
12010 /* Check for overflow. */
12011 if (residual >= 0x100)
12012 {
12013 (*_bfd_error_handler)
12014 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 12015 input_bfd, input_section,
12016 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 12017 return bfd_reloc_overflow;
12018 }
12019
12020 /* Mask out the value and U bit. */
12021 insn &= 0xff7ff0f0;
12022
12023 /* Set the U bit if the value to go in the place is non-negative. */
12024 if (signed_value >= 0)
12025 insn |= 1 << 23;
12026
12027 /* Encode the offset. */
12028 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12029
12030 bfd_put_32 (input_bfd, insn, hit_data);
12031 }
12032 return bfd_reloc_ok;
12033
12034 case R_ARM_LDC_PC_G0:
12035 case R_ARM_LDC_PC_G1:
12036 case R_ARM_LDC_PC_G2:
12037 case R_ARM_LDC_SB_G0:
12038 case R_ARM_LDC_SB_G1:
12039 case R_ARM_LDC_SB_G2:
12040 {
12041 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12042 bfd_vma pc = input_section->output_section->vma
4962c51a 12043 + input_section->output_offset + rel->r_offset;
31a91d61 12044 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12045 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12046 bfd_vma residual;
4962c51a 12047 bfd_signed_vma signed_value;
99059e56
RM		 12048 int group = 0;
12049
12050 /* Determine which groups of bits to calculate. */
12051 switch (r_type)
12052 {
12053 case R_ARM_LDC_PC_G0:
12054 case R_ARM_LDC_SB_G0:
12055 group = 0;
12056 break;
12057
12058 case R_ARM_LDC_PC_G1:
12059 case R_ARM_LDC_SB_G1:
12060 group = 1;
12061 break;
12062
12063 case R_ARM_LDC_PC_G2:
12064 case R_ARM_LDC_SB_G2:
12065 group = 2;
12066 break;
12067
12068 default:
12069 abort ();
12070 }
12071
12072 /* If REL, extract the addend from the insn. If RELA, it will
12073 have already been fetched for us. */
4962c51a 12074 if (globals->use_rel)
99059e56
RM		 12075 {
12076 int negative = (insn & (1 << 23)) ? 1 : -1;
12077 signed_addend = negative * ((insn & 0xff) << 2);
12078 }
4962c51a
MS		 12079
12080 /* Compute the value (X) to go in the place. */
99059e56
RM		 12081 if (r_type == R_ARM_LDC_PC_G0
12082 || r_type == R_ARM_LDC_PC_G1
12083 || r_type == R_ARM_LDC_PC_G2)
12084 /* PC relative. */
12085 signed_value = value - pc + signed_addend;
12086 else
12087 /* Section base relative. */
12088 signed_value = value - sb + signed_addend;
12089
12090 /* Calculate the value of the relevant G_{n-1} to obtain
12091 the residual at that stage. */
b6518b38
NC		 12092 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12093 group - 1, &residual);
99059e56
RM		 12094
12095 /* Check for overflow. (The absolute value to go in the place must be
12096 divisible by four and, after having been divided by four, must
12097 fit in eight bits.) */
12098 if ((residual & 0x3) != 0 || residual >= 0x400)
12099 {
12100 (*_bfd_error_handler)
12101 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
12102 input_bfd, input_section,
b6518b38 12103 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 12104 return bfd_reloc_overflow;
12105 }
12106
12107 /* Mask out the value and U bit. */
12108 insn &= 0xff7fff00;
12109
12110 /* Set the U bit if the value to go in the place is non-negative. */
12111 if (signed_value >= 0)
12112 insn |= 1 << 23;
12113
12114 /* Encode the offset. */
12115 insn |= residual >> 2;
4962c51a
MS		 12116
12117 bfd_put_32 (input_bfd, insn, hit_data);
12118 }
12119 return bfd_reloc_ok;
12120
72d98d16
MG		 12121 case R_ARM_THM_ALU_ABS_G0_NC:
12122 case R_ARM_THM_ALU_ABS_G1_NC:
12123 case R_ARM_THM_ALU_ABS_G2_NC:
12124 case R_ARM_THM_ALU_ABS_G3_NC:
12125 {
12126 const int shift_array[4] = {0, 8, 16, 24};
12127 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12128 bfd_vma addr = value;
12129 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12130
12131 /* Compute address. */
12132 if (globals->use_rel)
12133 signed_addend = insn & 0xff;
12134 addr += signed_addend;
12135 if (branch_type == ST_BRANCH_TO_THUMB)
12136 addr |= 1;
12137 /* Clean imm8 insn. */
12138 insn &= 0xff00;
12139 /* And update with correct part of address. */
12140 insn |= (addr >> shift) & 0xff;
12141 /* Update insn. */
12142 bfd_put_16 (input_bfd, insn, hit_data);
12143 }
12144
12145 *unresolved_reloc_p = FALSE;
12146 return bfd_reloc_ok;
12147
252b5132
RH		 12148 default:
12149 return bfd_reloc_notsupported;
12150 }
12151}
12152
98c1d4aa
NC		 12153/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
12154static void
57e8b36a
NC		 12155arm_add_to_rel (bfd * abfd,
12156 bfd_byte * address,
12157 reloc_howto_type * howto,
12158 bfd_signed_vma increment)
98c1d4aa 12159{
98c1d4aa
NC		 12160 bfd_signed_vma addend;
12161
bd97cb95
DJ		 12162 if (howto->type == R_ARM_THM_CALL
12163 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 12164 {
9a5aca8c
AM		 12165 int upper_insn, lower_insn;
12166 int upper, lower;
98c1d4aa 12167
9a5aca8c
AM		 12168 upper_insn = bfd_get_16 (abfd, address);
12169 lower_insn = bfd_get_16 (abfd, address + 2);
12170 upper = upper_insn & 0x7ff;
12171 lower = lower_insn & 0x7ff;
12172
12173 addend = (upper << 12) | (lower << 1);
ddda4409 12174 addend += increment;
9a5aca8c 12175 addend >>= 1;
98c1d4aa 12176
9a5aca8c
AM		 12177 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
12178 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
12179
dc810e39
AM		 12180 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
12181 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 12182 }
12183 else
12184 {
12185 bfd_vma contents;
12186
12187 contents = bfd_get_32 (abfd, address);
12188
12189 /* Get the (signed) value from the instruction. */
12190 addend = contents & howto->src_mask;
12191 if (addend & ((howto->src_mask + 1) >> 1))
12192 {
12193 bfd_signed_vma mask;
12194
12195 mask = -1;
12196 mask &= ~ howto->src_mask;
12197 addend |= mask;
12198 }
12199
12200 /* Add in the increment, (which is a byte value). */
12201 switch (howto->type)
12202 {
12203 default:
12204 addend += increment;
12205 break;
12206
12207 case R_ARM_PC24:
c6596c5e 12208 case R_ARM_PLT32:
5b5bb741
PB		 12209 case R_ARM_CALL:
12210 case R_ARM_JUMP24:
9a5aca8c 12211 addend <<= howto->size;
dc810e39 12212 addend += increment;
9a5aca8c
AM		 12213
12214 /* Should we check for overflow here ? */
12215
12216 /* Drop any undesired bits. */
12217 addend >>= howto->rightshift;
12218 break;
12219 }
12220
12221 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
12222
12223 bfd_put_32 (abfd, contents, address);
ddda4409 12224 }
98c1d4aa 12225}
252b5132 12226
ba93b8ac
DJ		 12227#define IS_ARM_TLS_RELOC(R_TYPE) \
12228 ((R_TYPE) == R_ARM_TLS_GD32 \
12229 || (R_TYPE) == R_ARM_TLS_LDO32 \
12230 || (R_TYPE) == R_ARM_TLS_LDM32 \
12231 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
12232 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
12233 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
12234 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 12235 || (R_TYPE) == R_ARM_TLS_IE32 \
12236 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
12237
12238/* Specific set of relocations for the gnu tls dialect. */
12239#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
12240 ((R_TYPE) == R_ARM_TLS_GOTDESC \
12241 || (R_TYPE) == R_ARM_TLS_CALL \
12242 || (R_TYPE) == R_ARM_THM_TLS_CALL \
12243 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
12244 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 12245
252b5132 12246/* Relocate an ARM ELF section. */
906e58ca 12247
b34976b6 12248static bfd_boolean
57e8b36a
NC		 12249elf32_arm_relocate_section (bfd * output_bfd,
12250 struct bfd_link_info * info,
12251 bfd * input_bfd,
12252 asection * input_section,
12253 bfd_byte * contents,
12254 Elf_Internal_Rela * relocs,
12255 Elf_Internal_Sym * local_syms,
12256 asection ** local_sections)
252b5132 12257{
b34976b6
AM		 12258 Elf_Internal_Shdr *symtab_hdr;
12259 struct elf_link_hash_entry **sym_hashes;
12260 Elf_Internal_Rela *rel;
12261 Elf_Internal_Rela *relend;
12262 const char *name;
b32d3aa2 12263 struct elf32_arm_link_hash_table * globals;
252b5132 12264
4e7fd91e 12265 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 12266 if (globals == NULL)
12267 return FALSE;
b491616a 12268
0ffa91dd 12269 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 12270 sym_hashes = elf_sym_hashes (input_bfd);
12271
12272 rel = relocs;
12273 relend = relocs + input_section->reloc_count;
12274 for (; rel < relend; rel++)
12275 {
ba96a88f
NC		 12276 int r_type;
12277 reloc_howto_type * howto;
12278 unsigned long r_symndx;
12279 Elf_Internal_Sym * sym;
12280 asection * sec;
252b5132 12281 struct elf_link_hash_entry * h;
ba96a88f
NC		 12282 bfd_vma relocation;
12283 bfd_reloc_status_type r;
12284 arelent bfd_reloc;
ba93b8ac 12285 char sym_type;
0945cdfd 12286 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 12287 char *error_message = NULL;
f21f3fe0 12288
252b5132 12289 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 12290 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 12291 r_type = arm_real_reloc_type (globals, r_type);
252b5132 12292
ba96a88f 12293 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 12294 || r_type == R_ARM_GNU_VTINHERIT)
12295 continue;
252b5132 12296
b32d3aa2 12297 bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
ba96a88f 12298 howto = bfd_reloc.howto;
252b5132 12299
252b5132
RH		 12300 h = NULL;
12301 sym = NULL;
12302 sec = NULL;
9b485d32 12303
252b5132
RH		 12304 if (r_symndx < symtab_hdr->sh_info)
12305 {
12306 sym = local_syms + r_symndx;
ba93b8ac 12307 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 12308 sec = local_sections[r_symndx];
ffcb4889
NS		 12309
12310 /* An object file might have a reference to a local
12311 undefined symbol. This is a daft object file, but we
12312 should at least do something about it. V4BX & NONE
12313 relocations do not use the symbol and are explicitly
77b4f08f
TS		 12314 allowed to use the undefined symbol, so allow those.
12315 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 12316 if (r_type != R_ARM_V4BX
12317 && r_type != R_ARM_NONE
77b4f08f 12318 && r_symndx != STN_UNDEF
ffcb4889
NS		 12319 && bfd_is_und_section (sec)
12320 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 12321 (*info->callbacks->undefined_symbol)
12322 (info, bfd_elf_string_from_elf_section
12323 (input_bfd, symtab_hdr->sh_link, sym->st_name),
12324 input_bfd, input_section,
12325 rel->r_offset, TRUE);
b38cadfb 12326
4e7fd91e 12327 if (globals->use_rel)
f8df10f4 12328 {
4e7fd91e
PB		 12329 relocation = (sec->output_section->vma
12330 + sec->output_offset
12331 + sym->st_value);
0e1862bb 12332 if (!bfd_link_relocatable (info)
ab96bf03
AM		 12333 && (sec->flags & SEC_MERGE)
12334 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 12335 {
4e7fd91e
PB		 12336 asection *msec;
12337 bfd_vma addend, value;
12338
39623e12 12339 switch (r_type)
4e7fd91e 12340 {
39623e12
PB		 12341 case R_ARM_MOVW_ABS_NC:
12342 case R_ARM_MOVT_ABS:
12343 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12344 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
12345 addend = (addend ^ 0x8000) - 0x8000;
12346 break;
f8df10f4 12347
39623e12
PB		 12348 case R_ARM_THM_MOVW_ABS_NC:
12349 case R_ARM_THM_MOVT_ABS:
12350 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
12351 << 16;
12352 value |= bfd_get_16 (input_bfd,
12353 contents + rel->r_offset + 2);
12354 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
12355 | ((value & 0x04000000) >> 15);
12356 addend = (addend ^ 0x8000) - 0x8000;
12357 break;
f8df10f4 12358
39623e12
PB		 12359 default:
12360 if (howto->rightshift
12361 || (howto->src_mask & (howto->src_mask + 1)))
12362 {
12363 (*_bfd_error_handler)
12364 (_("%B(%A+0x%lx): %s relocation against SEC_MERGE section"),
12365 input_bfd, input_section,
12366 (long) rel->r_offset, howto->name);
12367 return FALSE;
12368 }
12369
12370 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12371
12372 /* Get the (signed) value from the instruction. */
12373 addend = value & howto->src_mask;
12374 if (addend & ((howto->src_mask + 1) >> 1))
12375 {
12376 bfd_signed_vma mask;
12377
12378 mask = -1;
12379 mask &= ~ howto->src_mask;
12380 addend |= mask;
12381 }
12382 break;
4e7fd91e 12383 }
39623e12 12384
4e7fd91e
PB		 12385 msec = sec;
12386 addend =
12387 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
12388 - relocation;
12389 addend += msec->output_section->vma + msec->output_offset;
39623e12 12390
cc643b88 12391 /* Cases here must match those in the preceding
39623e12
PB		 12392 switch statement. */
12393 switch (r_type)
12394 {
12395 case R_ARM_MOVW_ABS_NC:
12396 case R_ARM_MOVT_ABS:
12397 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
12398 | (addend & 0xfff);
12399 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12400 break;
12401
12402 case R_ARM_THM_MOVW_ABS_NC:
12403 case R_ARM_THM_MOVT_ABS:
12404 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
12405 | (addend & 0xff) | ((addend & 0x0800) << 15);
12406 bfd_put_16 (input_bfd, value >> 16,
12407 contents + rel->r_offset);
12408 bfd_put_16 (input_bfd, value,
12409 contents + rel->r_offset + 2);
12410 break;
12411
12412 default:
12413 value = (value & ~ howto->dst_mask)
12414 | (addend & howto->dst_mask);
12415 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12416 break;
12417 }
f8df10f4 12418 }
f8df10f4 12419 }
4e7fd91e
PB		 12420 else
12421 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 12422 }
12423 else
12424 {
62d887d4 12425 bfd_boolean warned, ignored;
560e09e9 12426
b2a8e766
AM		 12427 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
12428 r_symndx, symtab_hdr, sym_hashes,
12429 h, sec, relocation,
62d887d4 12430 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 12431
12432 sym_type = h->type;
252b5132
RH		 12433 }
12434
dbaa2011 12435 if (sec != NULL && discarded_section (sec))
e4067dbb 12436 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 12437 rel, 1, relend, howto, 0, contents);
ab96bf03 12438
0e1862bb 12439 if (bfd_link_relocatable (info))
ab96bf03
AM		 12440 {
12441 /* This is a relocatable link. We don't have to change
12442 anything, unless the reloc is against a section symbol,
12443 in which case we have to adjust according to where the
12444 section symbol winds up in the output section. */
12445 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
12446 {
12447 if (globals->use_rel)
12448 arm_add_to_rel (input_bfd, contents + rel->r_offset,
12449 howto, (bfd_signed_vma) sec->output_offset);
12450 else
12451 rel->r_addend += sec->output_offset;
12452 }
12453 continue;
12454 }
12455
252b5132
RH		 12456 if (h != NULL)
12457 name = h->root.root.string;
12458 else
12459 {
12460 name = (bfd_elf_string_from_elf_section
12461 (input_bfd, symtab_hdr->sh_link, sym->st_name));
12462 if (name == NULL || *name == '\0')
12463 name = bfd_section_name (input_bfd, sec);
12464 }
f21f3fe0 12465
cf35638d 12466 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 12467 && r_type != R_ARM_NONE
12468 && (h == NULL
12469 || h->root.type == bfd_link_hash_defined
12470 || h->root.type == bfd_link_hash_defweak)
12471 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
12472 {
12473 (*_bfd_error_handler)
12474 ((sym_type == STT_TLS
12475 ? _("%B(%A+0x%lx): %s used with TLS symbol %s")
12476 : _("%B(%A+0x%lx): %s used with non-TLS symbol %s")),
12477 input_bfd,
12478 input_section,
12479 (long) rel->r_offset,
12480 howto->name,
12481 name);
12482 }
12483
0855e32b 12484 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 12485 done, i.e., the relaxation produced the final output we want,
12486 and we won't let anybody mess with it. Also, we have to do
12487 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 12488 both in relaxed and non-relaxed cases. */
39d911fc
TP		 12489 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
12490 || (IS_ARM_TLS_GNU_RELOC (r_type)
12491 && !((h ? elf32_arm_hash_entry (h)->tls_type :
12492 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
12493 & GOT_TLS_GDESC)))
12494 {
12495 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
12496 contents, rel, h == NULL);
12497 /* This may have been marked unresolved because it came from
12498 a shared library. But we've just dealt with that. */
12499 unresolved_reloc = 0;
12500 }
12501 else
12502 r = bfd_reloc_continue;
b38cadfb 12503
39d911fc
TP		 12504 if (r == bfd_reloc_continue)
12505 {
12506 unsigned char branch_type =
12507 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
12508 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
12509
12510 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
12511 input_section, contents, rel,
12512 relocation, info, sec, name,
12513 sym_type, branch_type, h,
12514 &unresolved_reloc,
12515 &error_message);
12516 }
0945cdfd
DJ		 12517
12518 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
12519 because such sections are not SEC_ALLOC and thus ld.so will
12520 not process them. */
12521 if (unresolved_reloc
99059e56
RM		 12522 && !((input_section->flags & SEC_DEBUGGING) != 0
12523 && h->def_dynamic)
1d5316ab
AM		 12524 && _bfd_elf_section_offset (output_bfd, info, input_section,
12525 rel->r_offset) != (bfd_vma) -1)
0945cdfd
DJ		 12526 {
12527 (*_bfd_error_handler)
843fe662
L		 12528 (_("%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"),
12529 input_bfd,
12530 input_section,
12531 (long) rel->r_offset,
12532 howto->name,
12533 h->root.root.string);
0945cdfd
DJ		 12534 return FALSE;
12535 }
252b5132
RH		 12536
12537 if (r != bfd_reloc_ok)
12538 {
252b5132
RH		 12539 switch (r)
12540 {
12541 case bfd_reloc_overflow:
cf919dfd
PB		 12542 /* If the overflowing reloc was to an undefined symbol,
12543 we have already printed one error message and there
12544 is no point complaining again. */
1a72702b
AM		 12545 if (!h || h->root.type != bfd_link_hash_undefined)
12546 (*info->callbacks->reloc_overflow)
12547 (info, (h ? &h->root : NULL), name, howto->name,
12548 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12549 break;
12550
12551 case bfd_reloc_undefined:
1a72702b
AM		 12552 (*info->callbacks->undefined_symbol)
12553 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 12554 break;
12555
12556 case bfd_reloc_outofrange:
f2a9dd69 12557 error_message = _("out of range");
252b5132
RH		 12558 goto common_error;
12559
12560 case bfd_reloc_notsupported:
f2a9dd69 12561 error_message = _("unsupported relocation");
252b5132
RH		 12562 goto common_error;
12563
12564 case bfd_reloc_dangerous:
f2a9dd69 12565 /* error_message should already be set. */
252b5132
RH		 12566 goto common_error;
12567
12568 default:
f2a9dd69 12569 error_message = _("unknown error");
8029a119 12570 /* Fall through. */
252b5132
RH		 12571
12572 common_error:
f2a9dd69 12573 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 12574 (*info->callbacks->reloc_dangerous)
12575 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12576 break;
12577 }
12578 }
12579 }
12580
b34976b6 12581 return TRUE;
252b5132
RH		 12582}
12583
91d6fa6a 12584/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 12585 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 12586 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 12587 maintaining that condition). */
12588
12589static void
12590add_unwind_table_edit (arm_unwind_table_edit **head,
12591 arm_unwind_table_edit **tail,
12592 arm_unwind_edit_type type,
12593 asection *linked_section,
91d6fa6a 12594 unsigned int tindex)
2468f9c9 12595{
21d799b5
NC		 12596 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
12597 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 12598
2468f9c9
PB		 12599 new_edit->type = type;
12600 new_edit->linked_section = linked_section;
91d6fa6a 12601 new_edit->index = tindex;
b38cadfb 12602
91d6fa6a 12603 if (tindex > 0)
2468f9c9
PB		 12604 {
12605 new_edit->next = NULL;
12606
12607 if (*tail)
12608 (*tail)->next = new_edit;
12609
12610 (*tail) = new_edit;
12611
12612 if (!*head)
12613 (*head) = new_edit;
12614 }
12615 else
12616 {
12617 new_edit->next = *head;
12618
12619 if (!*tail)
12620 *tail = new_edit;
12621
12622 *head = new_edit;
12623 }
12624}
12625
12626static _arm_elf_section_data *get_arm_elf_section_data (asection *);
12627
12628/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
12629static void
12630adjust_exidx_size(asection *exidx_sec, int adjust)
12631{
12632 asection *out_sec;
12633
12634 if (!exidx_sec->rawsize)
12635 exidx_sec->rawsize = exidx_sec->size;
12636
12637 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
12638 out_sec = exidx_sec->output_section;
12639 /* Adjust size of output section. */
12640 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
12641}
12642
12643/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
12644static void
12645insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
12646{
12647 struct _arm_elf_section_data *exidx_arm_data;
12648
12649 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12650 add_unwind_table_edit (
12651 &exidx_arm_data->u.exidx.unwind_edit_list,
12652 &exidx_arm_data->u.exidx.unwind_edit_tail,
12653 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
12654
491d01d3
YU		 12655 exidx_arm_data->additional_reloc_count++;
12656
2468f9c9
PB		 12657 adjust_exidx_size(exidx_sec, 8);
12658}
12659
12660/* Scan .ARM.exidx tables, and create a list describing edits which should be
12661 made to those tables, such that:
b38cadfb 12662
2468f9c9
PB		 12663 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
12664 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 12665 codes which have been inlined into the index).
2468f9c9 12666
85fdf906
AH		 12667 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
12668
2468f9c9 12669 The edits are applied when the tables are written
b38cadfb 12670 (in elf32_arm_write_section). */
2468f9c9
PB		 12671
12672bfd_boolean
12673elf32_arm_fix_exidx_coverage (asection **text_section_order,
12674 unsigned int num_text_sections,
85fdf906
AH		 12675 struct bfd_link_info *info,
12676 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 12677{
12678 bfd *inp;
12679 unsigned int last_second_word = 0, i;
12680 asection *last_exidx_sec = NULL;
12681 asection *last_text_sec = NULL;
12682 int last_unwind_type = -1;
12683
12684 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
12685 text sections. */
c72f2fb2 12686 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 12687 {
12688 asection *sec;
b38cadfb 12689
2468f9c9 12690 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 12691 {
2468f9c9
PB		 12692 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
12693 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 12694
dec9d5df 12695 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 12696 continue;
b38cadfb 12697
2468f9c9
PB		 12698 if (elf_sec->linked_to)
12699 {
12700 Elf_Internal_Shdr *linked_hdr
99059e56 12701 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 12702 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 12703 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 12704
12705 if (linked_sec_arm_data == NULL)
99059e56 12706 continue;
2468f9c9
PB		 12707
12708 /* Link this .ARM.exidx section back from the text section it
99059e56 12709 describes. */
2468f9c9
PB		 12710 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
12711 }
12712 }
12713 }
12714
12715 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
12716 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 12717 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 12718
12719 for (i = 0; i < num_text_sections; i++)
12720 {
12721 asection *sec = text_section_order[i];
12722 asection *exidx_sec;
12723 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
12724 struct _arm_elf_section_data *exidx_arm_data;
12725 bfd_byte *contents = NULL;
12726 int deleted_exidx_bytes = 0;
12727 bfd_vma j;
12728 arm_unwind_table_edit *unwind_edit_head = NULL;
12729 arm_unwind_table_edit *unwind_edit_tail = NULL;
12730 Elf_Internal_Shdr *hdr;
12731 bfd *ibfd;
12732
12733 if (arm_data == NULL)
99059e56 12734 continue;
2468f9c9
PB		 12735
12736 exidx_sec = arm_data->u.text.arm_exidx_sec;
12737 if (exidx_sec == NULL)
12738 {
12739 /* Section has no unwind data. */
12740 if (last_unwind_type == 0 || !last_exidx_sec)
12741 continue;
12742
12743 /* Ignore zero sized sections. */
12744 if (sec->size == 0)
12745 continue;
12746
12747 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12748 last_unwind_type = 0;
12749 continue;
12750 }
12751
22a8f80e
PB		 12752 /* Skip /DISCARD/ sections. */
12753 if (bfd_is_abs_section (exidx_sec->output_section))
12754 continue;
12755
2468f9c9
PB		 12756 hdr = &elf_section_data (exidx_sec)->this_hdr;
12757 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 12758 continue;
b38cadfb 12759
2468f9c9
PB		 12760 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12761 if (exidx_arm_data == NULL)
99059e56 12762 continue;
b38cadfb 12763
2468f9c9 12764 ibfd = exidx_sec->owner;
b38cadfb 12765
2468f9c9
PB		 12766 if (hdr->contents != NULL)
12767 contents = hdr->contents;
12768 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
12769 /* An error? */
12770 continue;
12771
ac06903d
YU		 12772 if (last_unwind_type > 0)
12773 {
12774 unsigned int first_word = bfd_get_32 (ibfd, contents);
12775 /* Add cantunwind if first unwind item does not match section
12776 start. */
12777 if (first_word != sec->vma)
12778 {
12779 insert_cantunwind_after (last_text_sec, last_exidx_sec);
12780 last_unwind_type = 0;
12781 }
12782 }
12783
2468f9c9
PB		 12784 for (j = 0; j < hdr->sh_size; j += 8)
12785 {
12786 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
12787 int unwind_type;
12788 int elide = 0;
12789
12790 /* An EXIDX_CANTUNWIND entry. */
12791 if (second_word == 1)
12792 {
12793 if (last_unwind_type == 0)
12794 elide = 1;
12795 unwind_type = 0;
12796 }
12797 /* Inlined unwinding data. Merge if equal to previous. */
12798 else if ((second_word & 0x80000000) != 0)
12799 {
85fdf906
AH		 12800 if (merge_exidx_entries
12801 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 12802 elide = 1;
12803 unwind_type = 1;
12804 last_second_word = second_word;
12805 }
12806 /* Normal table entry. In theory we could merge these too,
12807 but duplicate entries are likely to be much less common. */
12808 else
12809 unwind_type = 2;
12810
491d01d3 12811 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 12812 {
12813 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
12814 DELETE_EXIDX_ENTRY, NULL, j / 8);
12815
12816 deleted_exidx_bytes += 8;
12817 }
12818
12819 last_unwind_type = unwind_type;
12820 }
12821
12822 /* Free contents if we allocated it ourselves. */
12823 if (contents != hdr->contents)
99059e56 12824 free (contents);
2468f9c9
PB		 12825
12826 /* Record edits to be applied later (in elf32_arm_write_section). */
12827 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
12828 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 12829
2468f9c9
PB		 12830 if (deleted_exidx_bytes > 0)
12831 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
12832
12833 last_exidx_sec = exidx_sec;
12834 last_text_sec = sec;
12835 }
12836
12837 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 12838 if (!bfd_link_relocatable (info) && last_exidx_sec
12839 && last_unwind_type != 0)
2468f9c9
PB		 12840 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12841
12842 return TRUE;
12843}
12844
3e6b1042
DJ		 12845static bfd_boolean
12846elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
12847 bfd *ibfd, const char *name)
12848{
12849 asection *sec, *osec;
12850
3d4d4302 12851 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 12852 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
12853 return TRUE;
12854
12855 osec = sec->output_section;
12856 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
12857 return TRUE;
12858
12859 if (! bfd_set_section_contents (obfd, osec, sec->contents,
12860 sec->output_offset, sec->size))
12861 return FALSE;
12862
12863 return TRUE;
12864}
12865
12866static bfd_boolean
12867elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
12868{
12869 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 12870 asection *sec, *osec;
3e6b1042 12871
4dfe6ac6
NC		 12872 if (globals == NULL)
12873 return FALSE;
12874
3e6b1042
DJ		 12875 /* Invoke the regular ELF backend linker to do all the work. */
12876 if (!bfd_elf_final_link (abfd, info))
12877 return FALSE;
12878
fe33d2fa
CL		 12879 /* Process stub sections (eg BE8 encoding, ...). */
12880 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 12881 unsigned int i;
cdb21a0a
NS		 12882 for (i=0; i<htab->top_id; i++)
12883 {
12884 sec = htab->stub_group[i].stub_sec;
12885 /* Only process it once, in its link_sec slot. */
12886 if (sec && i == htab->stub_group[i].link_sec->id)
12887 {
12888 osec = sec->output_section;
12889 elf32_arm_write_section (abfd, info, sec, sec->contents);
12890 if (! bfd_set_section_contents (abfd, osec, sec->contents,
12891 sec->output_offset, sec->size))
12892 return FALSE;
12893 }
fe33d2fa 12894 }
fe33d2fa 12895
3e6b1042
DJ		 12896 /* Write out any glue sections now that we have created all the
12897 stubs. */
12898 if (globals->bfd_of_glue_owner != NULL)
12899 {
12900 if (! elf32_arm_output_glue_section (info, abfd,
12901 globals->bfd_of_glue_owner,
12902 ARM2THUMB_GLUE_SECTION_NAME))
12903 return FALSE;
12904
12905 if (! elf32_arm_output_glue_section (info, abfd,
12906 globals->bfd_of_glue_owner,
12907 THUMB2ARM_GLUE_SECTION_NAME))
12908 return FALSE;
12909
12910 if (! elf32_arm_output_glue_section (info, abfd,
12911 globals->bfd_of_glue_owner,
12912 VFP11_ERRATUM_VENEER_SECTION_NAME))
12913 return FALSE;
12914
a504d23a
LA		 12915 if (! elf32_arm_output_glue_section (info, abfd,
12916 globals->bfd_of_glue_owner,
12917 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
12918 return FALSE;
12919
3e6b1042
DJ		 12920 if (! elf32_arm_output_glue_section (info, abfd,
12921 globals->bfd_of_glue_owner,
12922 ARM_BX_GLUE_SECTION_NAME))
12923 return FALSE;
12924 }
12925
12926 return TRUE;
12927}
12928
5968a7b8
NC		 12929/* Return a best guess for the machine number based on the attributes. */
12930
12931static unsigned int
12932bfd_arm_get_mach_from_attributes (bfd * abfd)
12933{
12934 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
12935
12936 switch (arch)
12937 {
12938 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
12939 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
12940 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
12941
12942 case TAG_CPU_ARCH_V5TE:
12943 {
12944 char * name;
12945
12946 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
12947 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
12948
12949 if (name)
12950 {
12951 if (strcmp (name, "IWMMXT2") == 0)
12952 return bfd_mach_arm_iWMMXt2;
12953
12954 if (strcmp (name, "IWMMXT") == 0)
6034aab8 12955 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 12956
12957 if (strcmp (name, "XSCALE") == 0)
12958 {
12959 int wmmx;
12960
12961 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
12962 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
12963 switch (wmmx)
12964 {
12965 case 1: return bfd_mach_arm_iWMMXt;
12966 case 2: return bfd_mach_arm_iWMMXt2;
12967 default: return bfd_mach_arm_XScale;
12968 }
12969 }
5968a7b8
NC		 12970 }
12971
12972 return bfd_mach_arm_5TE;
12973 }
12974
12975 default:
12976 return bfd_mach_arm_unknown;
12977 }
12978}
12979
c178919b
NC		 12980/* Set the right machine number. */
12981
12982static bfd_boolean
57e8b36a 12983elf32_arm_object_p (bfd *abfd)
c178919b 12984{
5a6c6817 12985 unsigned int mach;
57e8b36a 12986
5a6c6817 12987 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 12988
5968a7b8
NC		 12989 if (mach == bfd_mach_arm_unknown)
12990 {
12991 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
12992 mach = bfd_mach_arm_ep9312;
12993 else
12994 mach = bfd_arm_get_mach_from_attributes (abfd);
12995 }
c178919b 12996
5968a7b8 12997 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 12998 return TRUE;
12999}
13000
fc830a83 13001/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13002
b34976b6 13003static bfd_boolean
57e8b36a 13004elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13005{
13006 if (elf_flags_init (abfd)
13007 && elf_elfheader (abfd)->e_flags != flags)
13008 {
fc830a83
NC		 13009 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13010 {
fd2ec330 13011 if (flags & EF_ARM_INTERWORK)
d003868e
AM		 13012 (*_bfd_error_handler)
13013 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
13014 abfd);
fc830a83 13015 else
d003868e
AM		 13016 _bfd_error_handler
13017 (_("Warning: Clearing the interworking flag of %B due to outside request"),
13018 abfd);
fc830a83 13019 }
252b5132
RH		 13020 }
13021 else
13022 {
13023 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13024 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13025 }
13026
b34976b6 13027 return TRUE;
252b5132
RH		 13028}
13029
fc830a83 13030/* Copy backend specific data from one object module to another. */
9b485d32 13031
b34976b6 13032static bfd_boolean
57e8b36a 13033elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13034{
13035 flagword in_flags;
13036 flagword out_flags;
13037
0ffa91dd 13038 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13039 return TRUE;
252b5132 13040
fc830a83 13041 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13042 out_flags = elf_elfheader (obfd)->e_flags;
13043
fc830a83
NC		 13044 if (elf_flags_init (obfd)
13045 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13046 && in_flags != out_flags)
252b5132 13047 {
252b5132 13048 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 13049 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 13050 return FALSE;
252b5132
RH		 13051
13052 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 13053 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 13054 return FALSE;
252b5132
RH		 13055
13056 /* If the src and dest have different interworking flags
99059e56 13057 then turn off the interworking bit. */
fd2ec330 13058 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 13059 {
fd2ec330 13060 if (out_flags & EF_ARM_INTERWORK)
d003868e
AM		 13061 _bfd_error_handler
13062 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
13063 obfd, ibfd);
252b5132 13064
fd2ec330 13065 in_flags &= ~EF_ARM_INTERWORK;
252b5132 13066 }
1006ba19
PB		 13067
13068 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 13069 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
13070 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 13071 }
13072
13073 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 13074 elf_flags_init (obfd) = TRUE;
252b5132 13075
e2349352 13076 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 13077}
13078
13079/* Values for Tag_ABI_PCS_R9_use. */
13080enum
13081{
13082 AEABI_R9_V6,
13083 AEABI_R9_SB,
13084 AEABI_R9_TLS,
13085 AEABI_R9_unused
13086};
13087
13088/* Values for Tag_ABI_PCS_RW_data. */
13089enum
13090{
13091 AEABI_PCS_RW_data_absolute,
13092 AEABI_PCS_RW_data_PCrel,
13093 AEABI_PCS_RW_data_SBrel,
13094 AEABI_PCS_RW_data_unused
13095};
13096
13097/* Values for Tag_ABI_enum_size. */
13098enum
13099{
13100 AEABI_enum_unused,
13101 AEABI_enum_short,
13102 AEABI_enum_wide,
13103 AEABI_enum_forced_wide
13104};
13105
104d59d1
JM		 13106/* Determine whether an object attribute tag takes an integer, a
13107 string or both. */
906e58ca 13108
104d59d1
JM		 13109static int
13110elf32_arm_obj_attrs_arg_type (int tag)
13111{
13112 if (tag == Tag_compatibility)
3483fe2e 13113 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 13114 else if (tag == Tag_nodefaults)
3483fe2e
AS		 13115 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
13116 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
13117 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 13118 else if (tag < 32)
3483fe2e 13119 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 13120 else
3483fe2e 13121 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 13122}
13123
5aa6ff7c
AS		 13124/* The ABI defines that Tag_conformance should be emitted first, and that
13125 Tag_nodefaults should be second (if either is defined). This sets those
13126 two positions, and bumps up the position of all the remaining tags to
13127 compensate. */
13128static int
13129elf32_arm_obj_attrs_order (int num)
13130{
3de4a297 13131 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 13132 return Tag_conformance;
3de4a297 13133 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 13134 return Tag_nodefaults;
13135 if ((num - 2) < Tag_nodefaults)
13136 return num - 2;
13137 if ((num - 1) < Tag_conformance)
13138 return num - 1;
13139 return num;
13140}
13141
e8b36cd1
JM		 13142/* Attribute numbers >=64 (mod 128) can be safely ignored. */
13143static bfd_boolean
13144elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
13145{
13146 if ((tag & 127) < 64)
13147 {
13148 _bfd_error_handler
13149 (_("%B: Unknown mandatory EABI object attribute %d"),
13150 abfd, tag);
13151 bfd_set_error (bfd_error_bad_value);
13152 return FALSE;
13153 }
13154 else
13155 {
13156 _bfd_error_handler
13157 (_("Warning: %B: Unknown EABI object attribute %d"),
13158 abfd, tag);
13159 return TRUE;
13160 }
13161}
13162
91e22acd
AS		 13163/* Read the architecture from the Tag_also_compatible_with attribute, if any.
13164 Returns -1 if no architecture could be read. */
13165
13166static int
13167get_secondary_compatible_arch (bfd *abfd)
13168{
13169 obj_attribute *attr =
13170 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
13171
13172 /* Note: the tag and its argument below are uleb128 values, though
13173 currently-defined values fit in one byte for each. */
13174 if (attr->s
13175 && attr->s[0] == Tag_CPU_arch
13176 && (attr->s[1] & 128) != 128
13177 && attr->s[2] == 0)
13178 return attr->s[1];
13179
13180 /* This tag is "safely ignorable", so don't complain if it looks funny. */
13181 return -1;
13182}
13183
13184/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
13185 The tag is removed if ARCH is -1. */
13186
8e79c3df 13187static void
91e22acd 13188set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 13189{
91e22acd
AS		 13190 obj_attribute *attr =
13191 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 13192
91e22acd
AS		 13193 if (arch == -1)
13194 {
13195 attr->s = NULL;
13196 return;
8e79c3df 13197 }
91e22acd
AS		 13198
13199 /* Note: the tag and its argument below are uleb128 values, though
13200 currently-defined values fit in one byte for each. */
13201 if (!attr->s)
21d799b5 13202 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 13203 attr->s[0] = Tag_CPU_arch;
13204 attr->s[1] = arch;
13205 attr->s[2] = '\0';
8e79c3df
CM		 13206}
13207
91e22acd
AS		 13208/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
13209 into account. */
13210
13211static int
13212tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
13213 int newtag, int secondary_compat)
8e79c3df 13214{
91e22acd
AS		 13215#define T(X) TAG_CPU_ARCH_##X
13216 int tagl, tagh, result;
13217 const int v6t2[] =
13218 {
13219 T(V6T2), /* PRE_V4. */
13220 T(V6T2), /* V4. */
13221 T(V6T2), /* V4T. */
13222 T(V6T2), /* V5T. */
13223 T(V6T2), /* V5TE. */
13224 T(V6T2), /* V5TEJ. */
13225 T(V6T2), /* V6. */
13226 T(V7), /* V6KZ. */
13227 T(V6T2) /* V6T2. */
13228 };
13229 const int v6k[] =
13230 {
13231 T(V6K), /* PRE_V4. */
13232 T(V6K), /* V4. */
13233 T(V6K), /* V4T. */
13234 T(V6K), /* V5T. */
13235 T(V6K), /* V5TE. */
13236 T(V6K), /* V5TEJ. */
13237 T(V6K), /* V6. */
13238 T(V6KZ), /* V6KZ. */
13239 T(V7), /* V6T2. */
13240 T(V6K) /* V6K. */
13241 };
13242 const int v7[] =
13243 {
13244 T(V7), /* PRE_V4. */
13245 T(V7), /* V4. */
13246 T(V7), /* V4T. */
13247 T(V7), /* V5T. */
13248 T(V7), /* V5TE. */
13249 T(V7), /* V5TEJ. */
13250 T(V7), /* V6. */
13251 T(V7), /* V6KZ. */
13252 T(V7), /* V6T2. */
13253 T(V7), /* V6K. */
13254 T(V7) /* V7. */
13255 };
13256 const int v6_m[] =
13257 {
13258 -1, /* PRE_V4. */
13259 -1, /* V4. */
13260 T(V6K), /* V4T. */
13261 T(V6K), /* V5T. */
13262 T(V6K), /* V5TE. */
13263 T(V6K), /* V5TEJ. */
13264 T(V6K), /* V6. */
13265 T(V6KZ), /* V6KZ. */
13266 T(V7), /* V6T2. */
13267 T(V6K), /* V6K. */
13268 T(V7), /* V7. */
13269 T(V6_M) /* V6_M. */
13270 };
13271 const int v6s_m[] =
13272 {
13273 -1, /* PRE_V4. */
13274 -1, /* V4. */
13275 T(V6K), /* V4T. */
13276 T(V6K), /* V5T. */
13277 T(V6K), /* V5TE. */
13278 T(V6K), /* V5TEJ. */
13279 T(V6K), /* V6. */
13280 T(V6KZ), /* V6KZ. */
13281 T(V7), /* V6T2. */
13282 T(V6K), /* V6K. */
13283 T(V7), /* V7. */
13284 T(V6S_M), /* V6_M. */
13285 T(V6S_M) /* V6S_M. */
13286 };
9e3c6df6
PB		 13287 const int v7e_m[] =
13288 {
13289 -1, /* PRE_V4. */
13290 -1, /* V4. */
13291 T(V7E_M), /* V4T. */
13292 T(V7E_M), /* V5T. */
13293 T(V7E_M), /* V5TE. */
13294 T(V7E_M), /* V5TEJ. */
13295 T(V7E_M), /* V6. */
13296 T(V7E_M), /* V6KZ. */
13297 T(V7E_M), /* V6T2. */
13298 T(V7E_M), /* V6K. */
13299 T(V7E_M), /* V7. */
13300 T(V7E_M), /* V6_M. */
13301 T(V7E_M), /* V6S_M. */
13302 T(V7E_M) /* V7E_M. */
13303 };
bca38921
MGD		 13304 const int v8[] =
13305 {
13306 T(V8), /* PRE_V4. */
13307 T(V8), /* V4. */
13308 T(V8), /* V4T. */
13309 T(V8), /* V5T. */
13310 T(V8), /* V5TE. */
13311 T(V8), /* V5TEJ. */
13312 T(V8), /* V6. */
13313 T(V8), /* V6KZ. */
13314 T(V8), /* V6T2. */
13315 T(V8), /* V6K. */
13316 T(V8), /* V7. */
13317 T(V8), /* V6_M. */
13318 T(V8), /* V6S_M. */
13319 T(V8), /* V7E_M. */
13320 T(V8) /* V8. */
13321 };
2fd158eb
TP		 13322 const int v8m_baseline[] =
13323 {
13324 -1, /* PRE_V4. */
13325 -1, /* V4. */
13326 -1, /* V4T. */
13327 -1, /* V5T. */
13328 -1, /* V5TE. */
13329 -1, /* V5TEJ. */
13330 -1, /* V6. */
13331 -1, /* V6KZ. */
13332 -1, /* V6T2. */
13333 -1, /* V6K. */
13334 -1, /* V7. */
13335 T(V8M_BASE), /* V6_M. */
13336 T(V8M_BASE), /* V6S_M. */
13337 -1, /* V7E_M. */
13338 -1, /* V8. */
13339 -1,
13340 T(V8M_BASE) /* V8-M BASELINE. */
13341 };
13342 const int v8m_mainline[] =
13343 {
13344 -1, /* PRE_V4. */
13345 -1, /* V4. */
13346 -1, /* V4T. */
13347 -1, /* V5T. */
13348 -1, /* V5TE. */
13349 -1, /* V5TEJ. */
13350 -1, /* V6. */
13351 -1, /* V6KZ. */
13352 -1, /* V6T2. */
13353 -1, /* V6K. */
13354 T(V8M_MAIN), /* V7. */
13355 T(V8M_MAIN), /* V6_M. */
13356 T(V8M_MAIN), /* V6S_M. */
13357 T(V8M_MAIN), /* V7E_M. */
13358 -1, /* V8. */
13359 -1,
13360 T(V8M_MAIN), /* V8-M BASELINE. */
13361 T(V8M_MAIN) /* V8-M MAINLINE. */
13362 };
91e22acd
AS		 13363 const int v4t_plus_v6_m[] =
13364 {
13365 -1, /* PRE_V4. */
13366 -1, /* V4. */
13367 T(V4T), /* V4T. */
13368 T(V5T), /* V5T. */
13369 T(V5TE), /* V5TE. */
13370 T(V5TEJ), /* V5TEJ. */
13371 T(V6), /* V6. */
13372 T(V6KZ), /* V6KZ. */
13373 T(V6T2), /* V6T2. */
13374 T(V6K), /* V6K. */
13375 T(V7), /* V7. */
13376 T(V6_M), /* V6_M. */
13377 T(V6S_M), /* V6S_M. */
9e3c6df6 13378 T(V7E_M), /* V7E_M. */
bca38921 13379 T(V8), /* V8. */
4ed7ed8d 13380 -1, /* Unused. */
2fd158eb
TP		 13381 T(V8M_BASE), /* V8-M BASELINE. */
13382 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 13383 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
13384 };
13385 const int *comb[] =
13386 {
13387 v6t2,
13388 v6k,
13389 v7,
13390 v6_m,
13391 v6s_m,
9e3c6df6 13392 v7e_m,
bca38921 13393 v8,
4ed7ed8d 13394 NULL,
2fd158eb
TP		 13395 v8m_baseline,
13396 v8m_mainline,
91e22acd
AS		 13397 /* Pseudo-architecture. */
13398 v4t_plus_v6_m
13399 };
13400
13401 /* Check we've not got a higher architecture than we know about. */
13402
9e3c6df6 13403 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 13404 {
3895f852 13405 _bfd_error_handler (_("error: %B: Unknown CPU architecture"), ibfd);
91e22acd
AS		 13406 return -1;
13407 }
13408
13409 /* Override old tag if we have a Tag_also_compatible_with on the output. */
13410
13411 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
13412 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
13413 oldtag = T(V4T_PLUS_V6_M);
13414
13415 /* And override the new tag if we have a Tag_also_compatible_with on the
13416 input. */
13417
13418 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
13419 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
13420 newtag = T(V4T_PLUS_V6_M);
13421
13422 tagl = (oldtag < newtag) ? oldtag : newtag;
13423 result = tagh = (oldtag > newtag) ? oldtag : newtag;
13424
13425 /* Architectures before V6KZ add features monotonically. */
13426 if (tagh <= TAG_CPU_ARCH_V6KZ)
13427 return result;
13428
4ed7ed8d 13429 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 13430
13431 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
13432 as the canonical version. */
13433 if (result == T(V4T_PLUS_V6_M))
13434 {
13435 result = T(V4T);
13436 *secondary_compat_out = T(V6_M);
13437 }
13438 else
13439 *secondary_compat_out = -1;
13440
13441 if (result == -1)
13442 {
3895f852 13443 _bfd_error_handler (_("error: %B: Conflicting CPU architectures %d/%d"),
91e22acd
AS		 13444 ibfd, oldtag, newtag);
13445 return -1;
13446 }
13447
13448 return result;
13449#undef T
8e79c3df
CM		 13450}
13451
ac56ee8f
MGD		 13452/* Query attributes object to see if integer divide instructions may be
13453 present in an object. */
13454static bfd_boolean
13455elf32_arm_attributes_accept_div (const obj_attribute *attr)
13456{
13457 int arch = attr[Tag_CPU_arch].i;
13458 int profile = attr[Tag_CPU_arch_profile].i;
13459
13460 switch (attr[Tag_DIV_use].i)
13461 {
13462 case 0:
13463 /* Integer divide allowed if instruction contained in archetecture. */
13464 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
13465 return TRUE;
13466 else if (arch >= TAG_CPU_ARCH_V7E_M)
13467 return TRUE;
13468 else
13469 return FALSE;
13470
13471 case 1:
13472 /* Integer divide explicitly prohibited. */
13473 return FALSE;
13474
13475 default:
13476 /* Unrecognised case - treat as allowing divide everywhere. */
13477 case 2:
13478 /* Integer divide allowed in ARM state. */
13479 return TRUE;
13480 }
13481}
13482
13483/* Query attributes object to see if integer divide instructions are
13484 forbidden to be in the object. This is not the inverse of
13485 elf32_arm_attributes_accept_div. */
13486static bfd_boolean
13487elf32_arm_attributes_forbid_div (const obj_attribute *attr)
13488{
13489 return attr[Tag_DIV_use].i == 1;
13490}
13491
ee065d83
PB		 13492/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
13493 are conflicting attributes. */
906e58ca 13494
ee065d83
PB		 13495static bfd_boolean
13496elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd)
13497{
104d59d1
JM		 13498 obj_attribute *in_attr;
13499 obj_attribute *out_attr;
ee065d83
PB		 13500 /* Some tags have 0 = don't care, 1 = strong requirement,
13501 2 = weak requirement. */
91e22acd 13502 static const int order_021[3] = {0, 2, 1};
ee065d83 13503 int i;
91e22acd 13504 bfd_boolean result = TRUE;
9274e9de 13505 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 13506
3e6b1042
DJ		 13507 /* Skip the linker stubs file. This preserves previous behavior
13508 of accepting unknown attributes in the first input file - but
13509 is that a bug? */
13510 if (ibfd->flags & BFD_LINKER_CREATED)
13511 return TRUE;
13512
9274e9de
TG		 13513 /* Skip any input that hasn't attribute section.
13514 This enables to link object files without attribute section with
13515 any others. */
13516 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
13517 return TRUE;
13518
104d59d1 13519 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 13520 {
13521 /* This is the first object. Copy the attributes. */
104d59d1 13522 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 13523
cd21e546
MGD		 13524 out_attr = elf_known_obj_attributes_proc (obfd);
13525
004ae526
PB		 13526 /* Use the Tag_null value to indicate the attributes have been
13527 initialized. */
cd21e546 13528 out_attr[0].i = 1;
004ae526 13529
cd21e546
MGD		 13530 /* We do not output objects with Tag_MPextension_use_legacy - we move
13531 the attribute's value to Tag_MPextension_use. */
13532 if (out_attr[Tag_MPextension_use_legacy].i != 0)
13533 {
13534 if (out_attr[Tag_MPextension_use].i != 0
13535 && out_attr[Tag_MPextension_use_legacy].i
99059e56 13536 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 13537 {
13538 _bfd_error_handler
13539 (_("Error: %B has both the current and legacy "
13540 "Tag_MPextension_use attributes"), ibfd);
13541 result = FALSE;
13542 }
13543
13544 out_attr[Tag_MPextension_use] =
13545 out_attr[Tag_MPextension_use_legacy];
13546 out_attr[Tag_MPextension_use_legacy].type = 0;
13547 out_attr[Tag_MPextension_use_legacy].i = 0;
13548 }
13549
13550 return result;
ee065d83
PB		 13551 }
13552
104d59d1
JM		 13553 in_attr = elf_known_obj_attributes_proc (ibfd);
13554 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 13555 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
13556 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
13557 {
5c294fee
TG		 13558 /* Ignore mismatches if the object doesn't use floating point or is
13559 floating point ABI independent. */
13560 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
13561 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13562 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 13563 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 13564 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13565 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 13566 {
13567 _bfd_error_handler
3895f852 13568 (_("error: %B uses VFP register arguments, %B does not"),
deddc40b
NS		 13569 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
13570 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 13571 result = FALSE;
ee065d83
PB		 13572 }
13573 }
13574
3de4a297 13575 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 13576 {
13577 /* Merge this attribute with existing attributes. */
13578 switch (i)
13579 {
13580 case Tag_CPU_raw_name:
13581 case Tag_CPU_name:
6a631e86 13582 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 13583 break;
13584
13585 case Tag_ABI_optimization_goals:
13586 case Tag_ABI_FP_optimization_goals:
13587 /* Use the first value seen. */
13588 break;
13589
13590 case Tag_CPU_arch:
91e22acd
AS		 13591 {
13592 int secondary_compat = -1, secondary_compat_out = -1;
13593 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 13594 int arch_attr;
13595 static const char *name_table[] =
13596 {
91e22acd
AS		 13597 /* These aren't real CPU names, but we can't guess
13598 that from the architecture version alone. */
13599 "Pre v4",
13600 "ARM v4",
13601 "ARM v4T",
13602 "ARM v5T",
13603 "ARM v5TE",
13604 "ARM v5TEJ",
13605 "ARM v6",
13606 "ARM v6KZ",
13607 "ARM v6T2",
13608 "ARM v6K",
13609 "ARM v7",
13610 "ARM v6-M",
bca38921 13611 "ARM v6S-M",
2fd158eb
TP		 13612 "ARM v8",
13613 "",
13614 "ARM v8-M.baseline",
13615 "ARM v8-M.mainline",
91e22acd
AS		 13616 };
13617
13618 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
13619 secondary_compat = get_secondary_compatible_arch (ibfd);
13620 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 13621 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
13622 &secondary_compat_out,
13623 in_attr[i].i,
13624 secondary_compat);
13625
13626 /* Return with error if failed to merge. */
13627 if (arch_attr == -1)
13628 return FALSE;
13629
13630 out_attr[i].i = arch_attr;
13631
91e22acd
AS		 13632 set_secondary_compatible_arch (obfd, secondary_compat_out);
13633
13634 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
13635 if (out_attr[i].i == saved_out_attr)
13636 ; /* Leave the names alone. */
13637 else if (out_attr[i].i == in_attr[i].i)
13638 {
13639 /* The output architecture has been changed to match the
13640 input architecture. Use the input names. */
13641 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
13642 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
13643 : NULL;
13644 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
13645 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
13646 : NULL;
13647 }
13648 else
13649 {
13650 out_attr[Tag_CPU_name].s = NULL;
13651 out_attr[Tag_CPU_raw_name].s = NULL;
13652 }
13653
13654 /* If we still don't have a value for Tag_CPU_name,
13655 make one up now. Tag_CPU_raw_name remains blank. */
13656 if (out_attr[Tag_CPU_name].s == NULL
13657 && out_attr[i].i < ARRAY_SIZE (name_table))
13658 out_attr[Tag_CPU_name].s =
13659 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
13660 }
13661 break;
13662
ee065d83
PB		 13663 case Tag_ARM_ISA_use:
13664 case Tag_THUMB_ISA_use:
ee065d83 13665 case Tag_WMMX_arch:
91e22acd
AS		 13666 case Tag_Advanced_SIMD_arch:
13667 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 13668 case Tag_ABI_FP_rounding:
ee065d83
PB		 13669 case Tag_ABI_FP_exceptions:
13670 case Tag_ABI_FP_user_exceptions:
13671 case Tag_ABI_FP_number_model:
75375b3e 13672 case Tag_FP_HP_extension:
91e22acd
AS		 13673 case Tag_CPU_unaligned_access:
13674 case Tag_T2EE_use:
91e22acd 13675 case Tag_MPextension_use:
ee065d83
PB		 13676 /* Use the largest value specified. */
13677 if (in_attr[i].i > out_attr[i].i)
13678 out_attr[i].i = in_attr[i].i;
13679 break;
13680
75375b3e 13681 case Tag_ABI_align_preserved:
91e22acd
AS		 13682 case Tag_ABI_PCS_RO_data:
13683 /* Use the smallest value specified. */
13684 if (in_attr[i].i < out_attr[i].i)
13685 out_attr[i].i = in_attr[i].i;
13686 break;
13687
75375b3e 13688 case Tag_ABI_align_needed:
91e22acd 13689 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 13690 && (in_attr[Tag_ABI_align_preserved].i == 0
13691 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 13692 {
91e22acd
AS		 13693 /* This error message should be enabled once all non-conformant
13694 binaries in the toolchain have had the attributes set
13695 properly.
ee065d83 13696 _bfd_error_handler
3895f852 13697 (_("error: %B: 8-byte data alignment conflicts with %B"),
91e22acd
AS		 13698 obfd, ibfd);
13699 result = FALSE; */
ee065d83 13700 }
91e22acd
AS		 13701 /* Fall through. */
13702 case Tag_ABI_FP_denormal:
13703 case Tag_ABI_PCS_GOT_use:
13704 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
13705 value if greater than 2 (for future-proofing). */
13706 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
13707 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
13708 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 13709 out_attr[i].i = in_attr[i].i;
13710 break;
91e22acd 13711
75375b3e
MGD		 13712 case Tag_Virtualization_use:
13713 /* The virtualization tag effectively stores two bits of
13714 information: the intended use of TrustZone (in bit 0), and the
13715 intended use of Virtualization (in bit 1). */
13716 if (out_attr[i].i == 0)
13717 out_attr[i].i = in_attr[i].i;
13718 else if (in_attr[i].i != 0
13719 && in_attr[i].i != out_attr[i].i)
13720 {
13721 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
13722 out_attr[i].i = 3;
13723 else
13724 {
13725 _bfd_error_handler
13726 (_("error: %B: unable to merge virtualization attributes "
13727 "with %B"),
13728 obfd, ibfd);
13729 result = FALSE;
13730 }
13731 }
13732 break;
91e22acd
AS		 13733
13734 case Tag_CPU_arch_profile:
13735 if (out_attr[i].i != in_attr[i].i)
13736 {
13737 /* 0 will merge with anything.
13738 'A' and 'S' merge to 'A'.
13739 'R' and 'S' merge to 'R'.
99059e56 13740 'M' and 'A|R|S' is an error. */
91e22acd
AS		 13741 if (out_attr[i].i == 0
13742 || (out_attr[i].i == 'S'
13743 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
13744 out_attr[i].i = in_attr[i].i;
13745 else if (in_attr[i].i == 0
13746 || (in_attr[i].i == 'S'
13747 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 13748 ; /* Do nothing. */
91e22acd
AS		 13749 else
13750 {
13751 _bfd_error_handler
3895f852 13752 (_("error: %B: Conflicting architecture profiles %c/%c"),
91e22acd
AS		 13753 ibfd,
13754 in_attr[i].i ? in_attr[i].i : '0',
13755 out_attr[i].i ? out_attr[i].i : '0');
13756 result = FALSE;
13757 }
13758 }
13759 break;
15afaa63
TP		 13760
13761 case Tag_DSP_extension:
13762 /* No need to change output value if any of:
13763 - pre (<=) ARMv5T input architecture (do not have DSP)
13764 - M input profile not ARMv7E-M and do not have DSP. */
13765 if (in_attr[Tag_CPU_arch].i <= 3
13766 || (in_attr[Tag_CPU_arch_profile].i == 'M'
13767 && in_attr[Tag_CPU_arch].i != 13
13768 && in_attr[i].i == 0))
13769 ; /* Do nothing. */
13770 /* Output value should be 0 if DSP part of architecture, ie.
13771 - post (>=) ARMv5te architecture output
13772 - A, R or S profile output or ARMv7E-M output architecture. */
13773 else if (out_attr[Tag_CPU_arch].i >= 4
13774 && (out_attr[Tag_CPU_arch_profile].i == 'A'
13775 || out_attr[Tag_CPU_arch_profile].i == 'R'
13776 || out_attr[Tag_CPU_arch_profile].i == 'S'
13777 || out_attr[Tag_CPU_arch].i == 13))
13778 out_attr[i].i = 0;
13779 /* Otherwise, DSP instructions are added and not part of output
13780 architecture. */
13781 else
13782 out_attr[i].i = 1;
13783 break;
13784
75375b3e 13785 case Tag_FP_arch:
62f3b8c8 13786 {
4547cb56
NC		 13787 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
13788 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
13789 when it's 0. It might mean absence of FP hardware if
99654aaf 13790 Tag_FP_arch is zero. */
4547cb56 13791
a715796b 13792#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 13793 static const struct
13794 {
13795 int ver;
13796 int regs;
bca38921 13797 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 13798 {
13799 {0, 0},
13800 {1, 16},
13801 {2, 16},
13802 {3, 32},
13803 {3, 16},
13804 {4, 32},
bca38921 13805 {4, 16},
a715796b
TG		 13806 {8, 32},
13807 {8, 16}
62f3b8c8
PB		 13808 };
13809 int ver;
13810 int regs;
13811 int newval;
13812
4547cb56
NC		 13813 /* If the output has no requirement about FP hardware,
13814 follow the requirement of the input. */
13815 if (out_attr[i].i == 0)
13816 {
13817 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
13818 out_attr[i].i = in_attr[i].i;
13819 out_attr[Tag_ABI_HardFP_use].i
13820 = in_attr[Tag_ABI_HardFP_use].i;
13821 break;
13822 }
13823 /* If the input has no requirement about FP hardware, do
13824 nothing. */
13825 else if (in_attr[i].i == 0)
13826 {
13827 BFD_ASSERT (in_attr[Tag_ABI_HardFP_use].i == 0);
13828 break;
13829 }
13830
13831 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 13832 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 13833
13834 /* If both the input and the output have zero Tag_ABI_HardFP_use,
13835 do nothing. */
13836 if (in_attr[Tag_ABI_HardFP_use].i == 0
13837 && out_attr[Tag_ABI_HardFP_use].i == 0)
13838 ;
13839 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 13840 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 13841 else if (in_attr[Tag_ABI_HardFP_use].i
13842 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 13843 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 13844
13845 /* Now we can handle Tag_FP_arch. */
13846
bca38921
MGD		 13847 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
13848 pick the biggest. */
13849 if (in_attr[i].i >= VFP_VERSION_COUNT
13850 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 13851 {
13852 out_attr[i] = in_attr[i];
13853 break;
13854 }
13855 /* The output uses the superset of input features
13856 (ISA version) and registers. */
13857 ver = vfp_versions[in_attr[i].i].ver;
13858 if (ver < vfp_versions[out_attr[i].i].ver)
13859 ver = vfp_versions[out_attr[i].i].ver;
13860 regs = vfp_versions[in_attr[i].i].regs;
13861 if (regs < vfp_versions[out_attr[i].i].regs)
13862 regs = vfp_versions[out_attr[i].i].regs;
13863 /* This assumes all possible supersets are also a valid
99059e56 13864 options. */
bca38921 13865 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 13866 {
13867 if (regs == vfp_versions[newval].regs
13868 && ver == vfp_versions[newval].ver)
13869 break;
13870 }
13871 out_attr[i].i = newval;
13872 }
b1cc4aeb 13873 break;
ee065d83
PB		 13874 case Tag_PCS_config:
13875 if (out_attr[i].i == 0)
13876 out_attr[i].i = in_attr[i].i;
b6009aca 13877 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 13878 {
13879 /* It's sometimes ok to mix different configs, so this is only
99059e56 13880 a warning. */
ee065d83
PB		 13881 _bfd_error_handler
13882 (_("Warning: %B: Conflicting platform configuration"), ibfd);
13883 }
13884 break;
13885 case Tag_ABI_PCS_R9_use:
004ae526
PB		 13886 if (in_attr[i].i != out_attr[i].i
13887 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 13888 && in_attr[i].i != AEABI_R9_unused)
13889 {
13890 _bfd_error_handler
3895f852 13891 (_("error: %B: Conflicting use of R9"), ibfd);
91e22acd 13892 result = FALSE;
ee065d83
PB		 13893 }
13894 if (out_attr[i].i == AEABI_R9_unused)
13895 out_attr[i].i = in_attr[i].i;
13896 break;
13897 case Tag_ABI_PCS_RW_data:
13898 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
13899 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
13900 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
13901 {
13902 _bfd_error_handler
3895f852 13903 (_("error: %B: SB relative addressing conflicts with use of R9"),
ee065d83 13904 ibfd);
91e22acd 13905 result = FALSE;
ee065d83
PB		 13906 }
13907 /* Use the smallest value specified. */
13908 if (in_attr[i].i < out_attr[i].i)
13909 out_attr[i].i = in_attr[i].i;
13910 break;
ee065d83 13911 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 13912 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
13913 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 13914 {
13915 _bfd_error_handler
a9dc9481
JM		 13916 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
13917 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 13918 }
a9dc9481 13919 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 13920 out_attr[i].i = in_attr[i].i;
13921 break;
ee065d83
PB		 13922 case Tag_ABI_enum_size:
13923 if (in_attr[i].i != AEABI_enum_unused)
13924 {
13925 if (out_attr[i].i == AEABI_enum_unused
13926 || out_attr[i].i == AEABI_enum_forced_wide)
13927 {
13928 /* The existing object is compatible with anything.
13929 Use whatever requirements the new object has. */
13930 out_attr[i].i = in_attr[i].i;
13931 }
13932 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 13933 && out_attr[i].i != in_attr[i].i
0ffa91dd 13934 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 13935 {
91e22acd 13936 static const char *aeabi_enum_names[] =
bf21ed78 13937 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 13938 const char *in_name =
13939 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13940 ? aeabi_enum_names[in_attr[i].i]
13941 : "<unknown>";
13942 const char *out_name =
13943 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13944 ? aeabi_enum_names[out_attr[i].i]
13945 : "<unknown>";
ee065d83 13946 _bfd_error_handler
bf21ed78 13947 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 13948 ibfd, in_name, out_name);
ee065d83
PB		 13949 }
13950 }
13951 break;
13952 case Tag_ABI_VFP_args:
13953 /* Aready done. */
13954 break;
13955 case Tag_ABI_WMMX_args:
13956 if (in_attr[i].i != out_attr[i].i)
13957 {
13958 _bfd_error_handler
3895f852 13959 (_("error: %B uses iWMMXt register arguments, %B does not"),
ee065d83 13960 ibfd, obfd);
91e22acd 13961 result = FALSE;
ee065d83
PB		 13962 }
13963 break;
7b86a9fa
AS		 13964 case Tag_compatibility:
13965 /* Merged in target-independent code. */
13966 break;
91e22acd 13967 case Tag_ABI_HardFP_use:
4547cb56 13968 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 13969 break;
13970 case Tag_ABI_FP_16bit_format:
13971 if (in_attr[i].i != 0 && out_attr[i].i != 0)
13972 {
13973 if (in_attr[i].i != out_attr[i].i)
13974 {
13975 _bfd_error_handler
3895f852 13976 (_("error: fp16 format mismatch between %B and %B"),
91e22acd
AS		 13977 ibfd, obfd);
13978 result = FALSE;
13979 }
13980 }
13981 if (in_attr[i].i != 0)
13982 out_attr[i].i = in_attr[i].i;
13983 break;
7b86a9fa 13984
cd21e546 13985 case Tag_DIV_use:
ac56ee8f
MGD		 13986 /* A value of zero on input means that the divide instruction may
13987 be used if available in the base architecture as specified via
13988 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
13989 the user did not want divide instructions. A value of 2
13990 explicitly means that divide instructions were allowed in ARM
13991 and Thumb state. */
13992 if (in_attr[i].i == out_attr[i].i)
13993 /* Do nothing. */ ;
13994 else if (elf32_arm_attributes_forbid_div (in_attr)
13995 && !elf32_arm_attributes_accept_div (out_attr))
13996 out_attr[i].i = 1;
13997 else if (elf32_arm_attributes_forbid_div (out_attr)
13998 && elf32_arm_attributes_accept_div (in_attr))
13999 out_attr[i].i = in_attr[i].i;
14000 else if (in_attr[i].i == 2)
14001 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 14002 break;
14003
14004 case Tag_MPextension_use_legacy:
14005 /* We don't output objects with Tag_MPextension_use_legacy - we
14006 move the value to Tag_MPextension_use. */
14007 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
14008 {
14009 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
14010 {
14011 _bfd_error_handler
14012 (_("%B has has both the current and legacy "
b38cadfb 14013 "Tag_MPextension_use attributes"),
cd21e546
MGD		 14014 ibfd);
14015 result = FALSE;
14016 }
14017 }
14018
14019 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
14020 out_attr[Tag_MPextension_use] = in_attr[i];
14021
14022 break;
14023
91e22acd 14024 case Tag_nodefaults:
2d0bb761
AS		 14025 /* This tag is set if it exists, but the value is unused (and is
14026 typically zero). We don't actually need to do anything here -
14027 the merge happens automatically when the type flags are merged
14028 below. */
91e22acd
AS		 14029 break;
14030 case Tag_also_compatible_with:
14031 /* Already done in Tag_CPU_arch. */
14032 break;
14033 case Tag_conformance:
14034 /* Keep the attribute if it matches. Throw it away otherwise.
14035 No attribute means no claim to conform. */
14036 if (!in_attr[i].s || !out_attr[i].s
14037 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
14038 out_attr[i].s = NULL;
14039 break;
3cfad14c 14040
91e22acd 14041 default:
e8b36cd1
JM		 14042 result
14043 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 14044 }
14045
14046 /* If out_attr was copied from in_attr then it won't have a type yet. */
14047 if (in_attr[i].type && !out_attr[i].type)
14048 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 14049 }
14050
104d59d1 14051 /* Merge Tag_compatibility attributes and any common GNU ones. */
5488d830
MGD		 14052 if (!_bfd_elf_merge_object_attributes (ibfd, obfd))
14053 return FALSE;
ee065d83 14054
104d59d1 14055 /* Check for any attributes not known on ARM. */
e8b36cd1 14056 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 14057
91e22acd 14058 return result;
252b5132
RH		 14059}
14060
3a4a14e9
PB		 14061
14062/* Return TRUE if the two EABI versions are incompatible. */
14063
14064static bfd_boolean
14065elf32_arm_versions_compatible (unsigned iver, unsigned over)
14066{
14067 /* v4 and v5 are the same spec before and after it was released,
14068 so allow mixing them. */
14069 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
14070 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
14071 return TRUE;
14072
14073 return (iver == over);
14074}
14075
252b5132
RH		 14076/* Merge backend specific data from an object file to the output
14077 object file when linking. */
9b485d32 14078
b34976b6 14079static bfd_boolean
21d799b5 14080elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd);
252b5132 14081
9b485d32
NC		 14082/* Display the flags field. */
14083
b34976b6 14084static bfd_boolean
57e8b36a 14085elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 14086{
fc830a83
NC		 14087 FILE * file = (FILE *) ptr;
14088 unsigned long flags;
252b5132
RH		 14089
14090 BFD_ASSERT (abfd != NULL && ptr != NULL);
14091
14092 /* Print normal ELF private data. */
14093 _bfd_elf_print_private_bfd_data (abfd, ptr);
14094
fc830a83 14095 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 14096 /* Ignore init flag - it may not be set, despite the flags field
14097 containing valid data. */
252b5132
RH		 14098
14099 /* xgettext:c-format */
9b485d32 14100 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 14101
fc830a83
NC		 14102 switch (EF_ARM_EABI_VERSION (flags))
14103 {
14104 case EF_ARM_EABI_UNKNOWN:
4cc11e76 14105 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 14106 official ARM ELF extended ABI. Hence they are only decoded if
14107 the EABI version is not set. */
fd2ec330 14108 if (flags & EF_ARM_INTERWORK)
9b485d32 14109 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 14110
fd2ec330 14111 if (flags & EF_ARM_APCS_26)
6c571f00 14112 fprintf (file, " [APCS-26]");
fc830a83 14113 else
6c571f00 14114 fprintf (file, " [APCS-32]");
9a5aca8c 14115
96a846ea
RE		 14116 if (flags & EF_ARM_VFP_FLOAT)
14117 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 14118 else if (flags & EF_ARM_MAVERICK_FLOAT)
14119 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 14120 else
14121 fprintf (file, _(" [FPA float format]"));
14122
fd2ec330 14123 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 14124 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 14125
fd2ec330 14126 if (flags & EF_ARM_PIC)
9b485d32 14127 fprintf (file, _(" [position independent]"));
fc830a83 14128
fd2ec330 14129 if (flags & EF_ARM_NEW_ABI)
9b485d32 14130 fprintf (file, _(" [new ABI]"));
9a5aca8c 14131
fd2ec330 14132 if (flags & EF_ARM_OLD_ABI)
9b485d32 14133 fprintf (file, _(" [old ABI]"));
9a5aca8c 14134
fd2ec330 14135 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 14136 fprintf (file, _(" [software FP]"));
9a5aca8c 14137
96a846ea
RE		 14138 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
14139 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 14140 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
14141 | EF_ARM_MAVERICK_FLOAT);
fc830a83 14142 break;
9a5aca8c 14143
fc830a83 14144 case EF_ARM_EABI_VER1:
9b485d32 14145 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 14146
fc830a83 14147 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 14148 fprintf (file, _(" [sorted symbol table]"));
fc830a83 14149 else
9b485d32 14150 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 14151
fc830a83
NC		 14152 flags &= ~ EF_ARM_SYMSARESORTED;
14153 break;
9a5aca8c 14154
fd2ec330
PB		 14155 case EF_ARM_EABI_VER2:
14156 fprintf (file, _(" [Version2 EABI]"));
14157
14158 if (flags & EF_ARM_SYMSARESORTED)
14159 fprintf (file, _(" [sorted symbol table]"));
14160 else
14161 fprintf (file, _(" [unsorted symbol table]"));
14162
14163 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
14164 fprintf (file, _(" [dynamic symbols use segment index]"));
14165
14166 if (flags & EF_ARM_MAPSYMSFIRST)
14167 fprintf (file, _(" [mapping symbols precede others]"));
14168
99e4ae17 14169 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 14170 | EF_ARM_MAPSYMSFIRST);
14171 break;
14172
d507cf36
PB		 14173 case EF_ARM_EABI_VER3:
14174 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 14175 break;
14176
14177 case EF_ARM_EABI_VER4:
14178 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 14179 goto eabi;
d507cf36 14180
3a4a14e9
PB		 14181 case EF_ARM_EABI_VER5:
14182 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 14183
14184 if (flags & EF_ARM_ABI_FLOAT_SOFT)
14185 fprintf (file, _(" [soft-float ABI]"));
14186
14187 if (flags & EF_ARM_ABI_FLOAT_HARD)
14188 fprintf (file, _(" [hard-float ABI]"));
14189
14190 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
14191
3a4a14e9 14192 eabi:
d507cf36
PB		 14193 if (flags & EF_ARM_BE8)
14194 fprintf (file, _(" [BE8]"));
14195
14196 if (flags & EF_ARM_LE8)
14197 fprintf (file, _(" [LE8]"));
14198
14199 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
14200 break;
14201
fc830a83 14202 default:
9b485d32 14203 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 14204 break;
14205 }
252b5132 14206
fc830a83 14207 flags &= ~ EF_ARM_EABIMASK;
252b5132 14208
fc830a83 14209 if (flags & EF_ARM_RELEXEC)
9b485d32 14210 fprintf (file, _(" [relocatable executable]"));
252b5132 14211
a5721edd 14212 flags &= ~EF_ARM_RELEXEC;
fc830a83
NC		 14213
14214 if (flags)
9b485d32 14215 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 14216
252b5132
RH		 14217 fputc ('\n', file);
14218
b34976b6 14219 return TRUE;
252b5132
RH		 14220}
14221
14222static int
57e8b36a 14223elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 14224{
2f0ca46a
NC		 14225 switch (ELF_ST_TYPE (elf_sym->st_info))
14226 {
14227 case STT_ARM_TFUNC:
14228 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 14229
2f0ca46a
NC		 14230 case STT_ARM_16BIT:
14231 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
14232 This allows us to distinguish between data used by Thumb instructions
14233 and non-data (which is probably code) inside Thumb regions of an
14234 executable. */
1a0eb693 14235 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 14236 return ELF_ST_TYPE (elf_sym->st_info);
14237 break;
9a5aca8c 14238
ce855c42
NC		 14239 default:
14240 break;
2f0ca46a
NC		 14241 }
14242
14243 return type;
252b5132 14244}
f21f3fe0 14245
252b5132 14246static asection *
07adf181
AM		 14247elf32_arm_gc_mark_hook (asection *sec,
14248 struct bfd_link_info *info,
14249 Elf_Internal_Rela *rel,
14250 struct elf_link_hash_entry *h,
14251 Elf_Internal_Sym *sym)
252b5132
RH		 14252{
14253 if (h != NULL)
07adf181 14254 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 14255 {
14256 case R_ARM_GNU_VTINHERIT:
14257 case R_ARM_GNU_VTENTRY:
07adf181
AM		 14258 return NULL;
14259 }
9ad5cbcf 14260
07adf181 14261 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 14262}
14263
780a67af
NC		 14264/* Update the got entry reference counts for the section being removed. */
14265
b34976b6 14266static bfd_boolean
ba93b8ac
DJ		 14267elf32_arm_gc_sweep_hook (bfd * abfd,
14268 struct bfd_link_info * info,
14269 asection * sec,
14270 const Elf_Internal_Rela * relocs)
252b5132 14271{
5e681ec4
PB		 14272 Elf_Internal_Shdr *symtab_hdr;
14273 struct elf_link_hash_entry **sym_hashes;
14274 bfd_signed_vma *local_got_refcounts;
14275 const Elf_Internal_Rela *rel, *relend;
eb043451
PB		 14276 struct elf32_arm_link_hash_table * globals;
14277
0e1862bb 14278 if (bfd_link_relocatable (info))
7dda2462
TG		 14279 return TRUE;
14280
eb043451 14281 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14282 if (globals == NULL)
14283 return FALSE;
5e681ec4
PB		 14284
14285 elf_section_data (sec)->local_dynrel = NULL;
14286
0ffa91dd 14287 symtab_hdr = & elf_symtab_hdr (abfd);
5e681ec4
PB		 14288 sym_hashes = elf_sym_hashes (abfd);
14289 local_got_refcounts = elf_local_got_refcounts (abfd);
14290
906e58ca 14291 check_use_blx (globals);
bd97cb95 14292
5e681ec4
PB		 14293 relend = relocs + sec->reloc_count;
14294 for (rel = relocs; rel < relend; rel++)
eb043451 14295 {
3eb128b2
AM		 14296 unsigned long r_symndx;
14297 struct elf_link_hash_entry *h = NULL;
f6e32f6d 14298 struct elf32_arm_link_hash_entry *eh;
eb043451 14299 int r_type;
34e77a92 14300 bfd_boolean call_reloc_p;
f6e32f6d
RS		 14301 bfd_boolean may_become_dynamic_p;
14302 bfd_boolean may_need_local_target_p;
34e77a92
RS		 14303 union gotplt_union *root_plt;
14304 struct arm_plt_info *arm_plt;
5e681ec4 14305
3eb128b2
AM		 14306 r_symndx = ELF32_R_SYM (rel->r_info);
14307 if (r_symndx >= symtab_hdr->sh_info)
14308 {
14309 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14310 while (h->root.type == bfd_link_hash_indirect
14311 || h->root.type == bfd_link_hash_warning)
14312 h = (struct elf_link_hash_entry *) h->root.u.i.link;
14313 }
f6e32f6d
RS		 14314 eh = (struct elf32_arm_link_hash_entry *) h;
14315
34e77a92 14316 call_reloc_p = FALSE;
f6e32f6d
RS		 14317 may_become_dynamic_p = FALSE;
14318 may_need_local_target_p = FALSE;
3eb128b2 14319
eb043451 14320 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14321 r_type = arm_real_reloc_type (globals, r_type);
eb043451
PB		 14322 switch (r_type)
14323 {
14324 case R_ARM_GOT32:
eb043451 14325 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14326 case R_ARM_TLS_GD32:
14327 case R_ARM_TLS_IE32:
3eb128b2 14328 if (h != NULL)
eb043451 14329 {
eb043451
PB		 14330 if (h->got.refcount > 0)
14331 h->got.refcount -= 1;
14332 }
14333 else if (local_got_refcounts != NULL)
14334 {
14335 if (local_got_refcounts[r_symndx] > 0)
14336 local_got_refcounts[r_symndx] -= 1;
14337 }
14338 break;
14339
ba93b8ac 14340 case R_ARM_TLS_LDM32:
4dfe6ac6 14341 globals->tls_ldm_got.refcount -= 1;
ba93b8ac
DJ		 14342 break;
14343
eb043451
PB		 14344 case R_ARM_PC24:
14345 case R_ARM_PLT32:
5b5bb741
PB		 14346 case R_ARM_CALL:
14347 case R_ARM_JUMP24:
eb043451 14348 case R_ARM_PREL31:
c19d1205 14349 case R_ARM_THM_CALL:
bd97cb95
DJ		 14350 case R_ARM_THM_JUMP24:
14351 case R_ARM_THM_JUMP19:
34e77a92 14352 call_reloc_p = TRUE;
f6e32f6d
RS		 14353 may_need_local_target_p = TRUE;
14354 break;
14355
14356 case R_ARM_ABS12:
14357 if (!globals->vxworks_p)
14358 {
14359 may_need_local_target_p = TRUE;
14360 break;
14361 }
14362 /* Fall through. */
14363 case R_ARM_ABS32:
14364 case R_ARM_ABS32_NOI:
14365 case R_ARM_REL32:
14366 case R_ARM_REL32_NOI:
b6895b4f
PB		 14367 case R_ARM_MOVW_ABS_NC:
14368 case R_ARM_MOVT_ABS:
14369 case R_ARM_MOVW_PREL_NC:
14370 case R_ARM_MOVT_PREL:
14371 case R_ARM_THM_MOVW_ABS_NC:
14372 case R_ARM_THM_MOVT_ABS:
14373 case R_ARM_THM_MOVW_PREL_NC:
14374 case R_ARM_THM_MOVT_PREL:
b7693d02 14375 /* Should the interworking branches be here also? */
0e1862bb 14376 if ((bfd_link_pic (info) || globals->root.is_relocatable_executable)
34e77a92
RS		 14377 && (sec->flags & SEC_ALLOC) != 0)
14378 {
14379 if (h == NULL
469a3493 14380 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14381 {
14382 call_reloc_p = TRUE;
14383 may_need_local_target_p = TRUE;
14384 }
14385 else
14386 may_become_dynamic_p = TRUE;
14387 }
f6e32f6d
RS		 14388 else
14389 may_need_local_target_p = TRUE;
14390 break;
b7693d02 14391
f6e32f6d
RS		 14392 default:
14393 break;
14394 }
5e681ec4 14395
34e77a92 14396 if (may_need_local_target_p
4ba2ef8f
TP		 14397 && elf32_arm_get_plt_info (abfd, globals, eh, r_symndx, &root_plt,
14398 &arm_plt))
f6e32f6d 14399 {
27586251
HPN		 14400 /* If PLT refcount book-keeping is wrong and too low, we'll
14401 see a zero value (going to -1) for the root PLT reference
14402 count. */
14403 if (root_plt->refcount >= 0)
14404 {
14405 BFD_ASSERT (root_plt->refcount != 0);
14406 root_plt->refcount -= 1;
14407 }
14408 else
14409 /* A value of -1 means the symbol has become local, forced
14410 or seeing a hidden definition. Any other negative value
14411 is an error. */
14412 BFD_ASSERT (root_plt->refcount == -1);
34e77a92
RS		 14413
14414 if (!call_reloc_p)
14415 arm_plt->noncall_refcount--;
5e681ec4 14416
f6e32f6d 14417 if (r_type == R_ARM_THM_CALL)
34e77a92 14418 arm_plt->maybe_thumb_refcount--;
bd97cb95 14419
f6e32f6d
RS		 14420 if (r_type == R_ARM_THM_JUMP24
14421 || r_type == R_ARM_THM_JUMP19)
34e77a92 14422 arm_plt->thumb_refcount--;
f6e32f6d 14423 }
5e681ec4 14424
34e77a92 14425 if (may_become_dynamic_p)
f6e32f6d
RS		 14426 {
14427 struct elf_dyn_relocs **pp;
14428 struct elf_dyn_relocs *p;
5e681ec4 14429
34e77a92 14430 if (h != NULL)
9c489990 14431 pp = &(eh->dyn_relocs);
34e77a92
RS		 14432 else
14433 {
14434 Elf_Internal_Sym *isym;
14435
14436 isym = bfd_sym_from_r_symndx (&globals->sym_cache,
14437 abfd, r_symndx);
14438 if (isym == NULL)
14439 return FALSE;
14440 pp = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14441 if (pp == NULL)
14442 return FALSE;
14443 }
9c489990 14444 for (; (p = *pp) != NULL; pp = &p->next)
f6e32f6d
RS		 14445 if (p->sec == sec)
14446 {
14447 /* Everything must go for SEC. */
14448 *pp = p->next;
14449 break;
14450 }
eb043451
PB		 14451 }
14452 }
5e681ec4 14453
b34976b6 14454 return TRUE;
252b5132
RH		 14455}
14456
780a67af
NC		 14457/* Look through the relocs for a section during the first phase. */
14458
b34976b6 14459static bfd_boolean
57e8b36a
NC		 14460elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
14461 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 14462{
b34976b6
AM		 14463 Elf_Internal_Shdr *symtab_hdr;
14464 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 14465 const Elf_Internal_Rela *rel;
14466 const Elf_Internal_Rela *rel_end;
14467 bfd *dynobj;
5e681ec4 14468 asection *sreloc;
5e681ec4 14469 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 14470 bfd_boolean call_reloc_p;
14471 bfd_boolean may_become_dynamic_p;
14472 bfd_boolean may_need_local_target_p;
ce98a316 14473 unsigned long nsyms;
9a5aca8c 14474
0e1862bb 14475 if (bfd_link_relocatable (info))
b34976b6 14476 return TRUE;
9a5aca8c 14477
0ffa91dd
NC		 14478 BFD_ASSERT (is_arm_elf (abfd));
14479
5e681ec4 14480 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14481 if (htab == NULL)
14482 return FALSE;
14483
5e681ec4 14484 sreloc = NULL;
9a5aca8c 14485
67687978
PB		 14486 /* Create dynamic sections for relocatable executables so that we can
14487 copy relocations. */
14488 if (htab->root.is_relocatable_executable
14489 && ! htab->root.dynamic_sections_created)
14490 {
14491 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
14492 return FALSE;
14493 }
14494
cbc704f3
RS		 14495 if (htab->root.dynobj == NULL)
14496 htab->root.dynobj = abfd;
34e77a92
RS		 14497 if (!create_ifunc_sections (info))
14498 return FALSE;
cbc704f3
RS		 14499
14500 dynobj = htab->root.dynobj;
14501
0ffa91dd 14502 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 14503 sym_hashes = elf_sym_hashes (abfd);
ce98a316 14504 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 14505
252b5132
RH		 14506 rel_end = relocs + sec->reloc_count;
14507 for (rel = relocs; rel < rel_end; rel++)
14508 {
34e77a92 14509 Elf_Internal_Sym *isym;
252b5132 14510 struct elf_link_hash_entry *h;
b7693d02 14511 struct elf32_arm_link_hash_entry *eh;
252b5132 14512 unsigned long r_symndx;
eb043451 14513 int r_type;
9a5aca8c 14514
252b5132 14515 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 14516 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14517 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 14518
ce98a316
NC		 14519 if (r_symndx >= nsyms
14520 /* PR 9934: It is possible to have relocations that do not
14521 refer to symbols, thus it is also possible to have an
14522 object file containing relocations but no symbol table. */
cf35638d 14523 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac
DJ		 14524 {
14525 (*_bfd_error_handler) (_("%B: bad symbol index: %d"), abfd,
ce98a316 14526 r_symndx);
ba93b8ac
DJ		 14527 return FALSE;
14528 }
14529
34e77a92
RS		 14530 h = NULL;
14531 isym = NULL;
14532 if (nsyms > 0)
973a3492 14533 {
34e77a92
RS		 14534 if (r_symndx < symtab_hdr->sh_info)
14535 {
14536 /* A local symbol. */
14537 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
14538 abfd, r_symndx);
14539 if (isym == NULL)
14540 return FALSE;
14541 }
14542 else
14543 {
14544 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14545 while (h->root.type == bfd_link_hash_indirect
14546 || h->root.type == bfd_link_hash_warning)
14547 h = (struct elf_link_hash_entry *) h->root.u.i.link;
81fbe831
AM		 14548
14549 /* PR15323, ref flags aren't set for references in the
14550 same object. */
14551 h->root.non_ir_ref = 1;
34e77a92 14552 }
973a3492 14553 }
9a5aca8c 14554
b7693d02
DJ		 14555 eh = (struct elf32_arm_link_hash_entry *) h;
14556
f6e32f6d
RS		 14557 call_reloc_p = FALSE;
14558 may_become_dynamic_p = FALSE;
14559 may_need_local_target_p = FALSE;
14560
0855e32b
NS		 14561 /* Could be done earlier, if h were already available. */
14562 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 14563 switch (r_type)
99059e56 14564 {
5e681ec4 14565 case R_ARM_GOT32:
eb043451 14566 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14567 case R_ARM_TLS_GD32:
14568 case R_ARM_TLS_IE32:
0855e32b
NS		 14569 case R_ARM_TLS_GOTDESC:
14570 case R_ARM_TLS_DESCSEQ:
14571 case R_ARM_THM_TLS_DESCSEQ:
14572 case R_ARM_TLS_CALL:
14573 case R_ARM_THM_TLS_CALL:
5e681ec4 14574 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 14575 {
14576 int tls_type, old_tls_type;
5e681ec4 14577
ba93b8ac
DJ		 14578 switch (r_type)
14579 {
14580 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 14581
ba93b8ac 14582 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 14583
0855e32b
NS		 14584 case R_ARM_TLS_GOTDESC:
14585 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
14586 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
14587 tls_type = GOT_TLS_GDESC; break;
b38cadfb 14588
ba93b8ac
DJ		 14589 default: tls_type = GOT_NORMAL; break;
14590 }
252b5132 14591
0e1862bb 14592 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 14593 info->flags |= DF_STATIC_TLS;
14594
ba93b8ac
DJ		 14595 if (h != NULL)
14596 {
14597 h->got.refcount++;
14598 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
14599 }
14600 else
14601 {
ba93b8ac 14602 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 14603 if (!elf32_arm_allocate_local_sym_info (abfd))
14604 return FALSE;
14605 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 14606 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
14607 }
14608
0855e32b 14609 /* If a variable is accessed with both tls methods, two
99059e56 14610 slots may be created. */
0855e32b
NS		 14611 if (GOT_TLS_GD_ANY_P (old_tls_type)
14612 && GOT_TLS_GD_ANY_P (tls_type))
14613 tls_type |= old_tls_type;
14614
14615 /* We will already have issued an error message if there
14616 is a TLS/non-TLS mismatch, based on the symbol
14617 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 14618 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
14619 && tls_type != GOT_NORMAL)
14620 tls_type |= old_tls_type;
14621
0855e32b 14622 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 14623 method, we're able to relax. Turn off the GDESC flag,
14624 without messing up with any other kind of tls types
6a631e86 14625 that may be involved. */
0855e32b
NS		 14626 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
14627 tls_type &= ~GOT_TLS_GDESC;
14628
ba93b8ac
DJ		 14629 if (old_tls_type != tls_type)
14630 {
14631 if (h != NULL)
14632 elf32_arm_hash_entry (h)->tls_type = tls_type;
14633 else
14634 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
14635 }
14636 }
8029a119 14637 /* Fall through. */
ba93b8ac
DJ		 14638
14639 case R_ARM_TLS_LDM32:
14640 if (r_type == R_ARM_TLS_LDM32)
14641 htab->tls_ldm_got.refcount++;
8029a119 14642 /* Fall through. */
252b5132 14643
c19d1205 14644 case R_ARM_GOTOFF32:
5e681ec4 14645 case R_ARM_GOTPC:
cbc704f3
RS		 14646 if (htab->root.sgot == NULL
14647 && !create_got_section (htab->root.dynobj, info))
14648 return FALSE;
252b5132
RH		 14649 break;
14650
252b5132 14651 case R_ARM_PC24:
7359ea65 14652 case R_ARM_PLT32:
5b5bb741
PB		 14653 case R_ARM_CALL:
14654 case R_ARM_JUMP24:
eb043451 14655 case R_ARM_PREL31:
c19d1205 14656 case R_ARM_THM_CALL:
bd97cb95
DJ		 14657 case R_ARM_THM_JUMP24:
14658 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 14659 call_reloc_p = TRUE;
14660 may_need_local_target_p = TRUE;
14661 break;
14662
14663 case R_ARM_ABS12:
14664 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
14665 ldr __GOTT_INDEX__ offsets. */
14666 if (!htab->vxworks_p)
14667 {
14668 may_need_local_target_p = TRUE;
14669 break;
14670 }
aebf9be7 14671 else goto jump_over;
9eaff861 14672
f6e32f6d 14673 /* Fall through. */
39623e12 14674
96c23d59
JM		 14675 case R_ARM_MOVW_ABS_NC:
14676 case R_ARM_MOVT_ABS:
14677 case R_ARM_THM_MOVW_ABS_NC:
14678 case R_ARM_THM_MOVT_ABS:
0e1862bb 14679 if (bfd_link_pic (info))
96c23d59
JM		 14680 {
14681 (*_bfd_error_handler)
14682 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
14683 abfd, elf32_arm_howto_table_1[r_type].name,
14684 (h) ? h->root.root.string : "a local symbol");
14685 bfd_set_error (bfd_error_bad_value);
14686 return FALSE;
14687 }
14688
14689 /* Fall through. */
39623e12
PB		 14690 case R_ARM_ABS32:
14691 case R_ARM_ABS32_NOI:
aebf9be7 14692 jump_over:
0e1862bb 14693 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 14694 {
14695 h->pointer_equality_needed = 1;
14696 }
14697 /* Fall through. */
39623e12
PB		 14698 case R_ARM_REL32:
14699 case R_ARM_REL32_NOI:
b6895b4f
PB		 14700 case R_ARM_MOVW_PREL_NC:
14701 case R_ARM_MOVT_PREL:
b6895b4f
PB		 14702 case R_ARM_THM_MOVW_PREL_NC:
14703 case R_ARM_THM_MOVT_PREL:
39623e12 14704
b7693d02 14705 /* Should the interworking branches be listed here? */
0e1862bb 14706 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 14707 && (sec->flags & SEC_ALLOC) != 0)
14708 {
14709 if (h == NULL
469a3493 14710 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14711 {
14712 /* In shared libraries and relocatable executables,
14713 we treat local relative references as calls;
14714 see the related SYMBOL_CALLS_LOCAL code in
14715 allocate_dynrelocs. */
14716 call_reloc_p = TRUE;
14717 may_need_local_target_p = TRUE;
14718 }
14719 else
14720 /* We are creating a shared library or relocatable
14721 executable, and this is a reloc against a global symbol,
14722 or a non-PC-relative reloc against a local symbol.
14723 We may need to copy the reloc into the output. */
14724 may_become_dynamic_p = TRUE;
14725 }
f6e32f6d
RS		 14726 else
14727 may_need_local_target_p = TRUE;
252b5132
RH		 14728 break;
14729
99059e56
RM		 14730 /* This relocation describes the C++ object vtable hierarchy.
14731 Reconstruct it for later use during GC. */
14732 case R_ARM_GNU_VTINHERIT:
14733 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
14734 return FALSE;
14735 break;
14736
14737 /* This relocation describes which C++ vtable entries are actually
14738 used. Record for later use during GC. */
14739 case R_ARM_GNU_VTENTRY:
14740 BFD_ASSERT (h != NULL);
14741 if (h != NULL
14742 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
14743 return FALSE;
14744 break;
14745 }
f6e32f6d
RS		 14746
14747 if (h != NULL)
14748 {
14749 if (call_reloc_p)
14750 /* We may need a .plt entry if the function this reloc
14751 refers to is in a different object, regardless of the
14752 symbol's type. We can't tell for sure yet, because
14753 something later might force the symbol local. */
14754 h->needs_plt = 1;
14755 else if (may_need_local_target_p)
14756 /* If this reloc is in a read-only section, we might
14757 need a copy reloc. We can't check reliably at this
14758 stage whether the section is read-only, as input
14759 sections have not yet been mapped to output sections.
14760 Tentatively set the flag for now, and correct in
14761 adjust_dynamic_symbol. */
14762 h->non_got_ref = 1;
14763 }
14764
34e77a92
RS		 14765 if (may_need_local_target_p
14766 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 14767 {
34e77a92
RS		 14768 union gotplt_union *root_plt;
14769 struct arm_plt_info *arm_plt;
14770 struct arm_local_iplt_info *local_iplt;
14771
14772 if (h != NULL)
14773 {
14774 root_plt = &h->plt;
14775 arm_plt = &eh->plt;
14776 }
14777 else
14778 {
14779 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
14780 if (local_iplt == NULL)
14781 return FALSE;
14782 root_plt = &local_iplt->root;
14783 arm_plt = &local_iplt->arm;
14784 }
14785
f6e32f6d
RS		 14786 /* If the symbol is a function that doesn't bind locally,
14787 this relocation will need a PLT entry. */
a8c887dd
NC		 14788 if (root_plt->refcount != -1)
14789 root_plt->refcount += 1;
34e77a92
RS		 14790
14791 if (!call_reloc_p)
14792 arm_plt->noncall_refcount++;
f6e32f6d
RS		 14793
14794 /* It's too early to use htab->use_blx here, so we have to
14795 record possible blx references separately from
14796 relocs that definitely need a thumb stub. */
14797
14798 if (r_type == R_ARM_THM_CALL)
34e77a92 14799 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 14800
14801 if (r_type == R_ARM_THM_JUMP24
14802 || r_type == R_ARM_THM_JUMP19)
34e77a92 14803 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 14804 }
14805
14806 if (may_become_dynamic_p)
14807 {
14808 struct elf_dyn_relocs *p, **head;
14809
14810 /* Create a reloc section in dynobj. */
14811 if (sreloc == NULL)
14812 {
14813 sreloc = _bfd_elf_make_dynamic_reloc_section
14814 (sec, dynobj, 2, abfd, ! htab->use_rel);
14815
14816 if (sreloc == NULL)
14817 return FALSE;
14818
14819 /* BPABI objects never have dynamic relocations mapped. */
14820 if (htab->symbian_p)
14821 {
14822 flagword flags;
14823
14824 flags = bfd_get_section_flags (dynobj, sreloc);
14825 flags &= ~(SEC_LOAD | SEC_ALLOC);
14826 bfd_set_section_flags (dynobj, sreloc, flags);
14827 }
14828 }
14829
14830 /* If this is a global symbol, count the number of
14831 relocations we need for this symbol. */
14832 if (h != NULL)
14833 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
14834 else
14835 {
34e77a92
RS		 14836 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14837 if (head == NULL)
f6e32f6d 14838 return FALSE;
f6e32f6d
RS		 14839 }
14840
14841 p = *head;
14842 if (p == NULL || p->sec != sec)
14843 {
14844 bfd_size_type amt = sizeof *p;
14845
14846 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
14847 if (p == NULL)
14848 return FALSE;
14849 p->next = *head;
14850 *head = p;
14851 p->sec = sec;
14852 p->count = 0;
14853 p->pc_count = 0;
14854 }
14855
469a3493 14856 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 14857 p->pc_count += 1;
14858 p->count += 1;
14859 }
252b5132 14860 }
f21f3fe0 14861
b34976b6 14862 return TRUE;
252b5132
RH		 14863}
14864
9eaff861
AO		 14865static void
14866elf32_arm_update_relocs (asection *o,
14867 struct bfd_elf_section_reloc_data *reldata)
14868{
14869 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
14870 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
14871 const struct elf_backend_data *bed;
14872 _arm_elf_section_data *eado;
14873 struct bfd_link_order *p;
14874 bfd_byte *erela_head, *erela;
14875 Elf_Internal_Rela *irela_head, *irela;
14876 Elf_Internal_Shdr *rel_hdr;
14877 bfd *abfd;
14878 unsigned int count;
14879
14880 eado = get_arm_elf_section_data (o);
14881
14882 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
14883 return;
14884
14885 abfd = o->owner;
14886 bed = get_elf_backend_data (abfd);
14887 rel_hdr = reldata->hdr;
14888
14889 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
14890 {
14891 swap_in = bed->s->swap_reloc_in;
14892 swap_out = bed->s->swap_reloc_out;
14893 }
14894 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
14895 {
14896 swap_in = bed->s->swap_reloca_in;
14897 swap_out = bed->s->swap_reloca_out;
14898 }
14899 else
14900 abort ();
14901
14902 erela_head = rel_hdr->contents;
14903 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
14904 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
14905
14906 erela = erela_head;
14907 irela = irela_head;
14908 count = 0;
14909
14910 for (p = o->map_head.link_order; p; p = p->next)
14911 {
14912 if (p->type == bfd_section_reloc_link_order
14913 || p->type == bfd_symbol_reloc_link_order)
14914 {
14915 (*swap_in) (abfd, erela, irela);
14916 erela += rel_hdr->sh_entsize;
14917 irela++;
14918 count++;
14919 }
14920 else if (p->type == bfd_indirect_link_order)
14921 {
14922 struct bfd_elf_section_reloc_data *input_reldata;
14923 arm_unwind_table_edit *edit_list, *edit_tail;
14924 _arm_elf_section_data *eadi;
14925 bfd_size_type j;
14926 bfd_vma offset;
14927 asection *i;
14928
14929 i = p->u.indirect.section;
14930
14931 eadi = get_arm_elf_section_data (i);
14932 edit_list = eadi->u.exidx.unwind_edit_list;
14933 edit_tail = eadi->u.exidx.unwind_edit_tail;
14934 offset = o->vma + i->output_offset;
14935
14936 if (eadi->elf.rel.hdr &&
14937 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
14938 input_reldata = &eadi->elf.rel;
14939 else if (eadi->elf.rela.hdr &&
14940 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
14941 input_reldata = &eadi->elf.rela;
14942 else
14943 abort ();
14944
14945 if (edit_list)
14946 {
14947 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
14948 {
14949 arm_unwind_table_edit *edit_node, *edit_next;
14950 bfd_vma bias;
14951 bfd_vma index;
14952
14953 (*swap_in) (abfd, erela, irela);
14954 index = (irela->r_offset - offset) / 8;
14955
14956 bias = 0;
14957 edit_node = edit_list;
14958 for (edit_next = edit_list;
14959 edit_next && edit_next->index <= index;
14960 edit_next = edit_node->next)
14961 {
14962 bias++;
14963 edit_node = edit_next;
14964 }
14965
14966 if (edit_node->type != DELETE_EXIDX_ENTRY
14967 || edit_node->index != index)
14968 {
14969 irela->r_offset -= bias * 8;
14970 irela++;
14971 count++;
14972 }
14973
14974 erela += rel_hdr->sh_entsize;
14975 }
14976
14977 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
14978 {
14979 /* New relocation entity. */
14980 asection *text_sec = edit_tail->linked_section;
14981 asection *text_out = text_sec->output_section;
14982 bfd_vma exidx_offset = offset + i->size - 8;
14983
14984 irela->r_addend = 0;
14985 irela->r_offset = exidx_offset;
14986 irela->r_info = ELF32_R_INFO
14987 (text_out->target_index, R_ARM_PREL31);
14988 irela++;
14989 count++;
14990 }
14991 }
14992 else
14993 {
14994 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
14995 {
14996 (*swap_in) (abfd, erela, irela);
14997 erela += rel_hdr->sh_entsize;
14998 irela++;
14999 }
15000
15001 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15002 }
15003 }
15004 }
15005
15006 reldata->count = count;
15007 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15008
15009 erela = erela_head;
15010 irela = irela_head;
15011 while (count > 0)
15012 {
15013 (*swap_out) (abfd, irela, erela);
15014 erela += rel_hdr->sh_entsize;
15015 irela++;
15016 count--;
15017 }
15018
15019 free (irela_head);
15020
15021 /* Hashes are no longer valid. */
15022 free (reldata->hashes);
15023 reldata->hashes = NULL;
15024}
15025
6a5bb875 15026/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15027 required if the corresponding code section is marked. Similarly, ARMv8-M
15028 secure entry functions can only be referenced by SG veneers which are
15029 created after the GC process. They need to be marked in case they reside in
15030 their own section (as would be the case if code was compiled with
15031 -ffunction-sections). */
6a5bb875
PB		 15032
15033static bfd_boolean
906e58ca
NC		 15034elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15035 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15036{
15037 bfd *sub;
15038 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15039 asection *cmse_sec;
15040 obj_attribute *out_attr;
15041 Elf_Internal_Shdr *symtab_hdr;
15042 unsigned i, sym_count, ext_start;
15043 const struct elf_backend_data *bed;
15044 struct elf_link_hash_entry **sym_hashes;
15045 struct elf32_arm_link_hash_entry *cmse_hash;
15046 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
6a5bb875 15047
7f6ab9f8
AM		 15048 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15049
4ba2ef8f
TP		 15050 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15051 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15052 && out_attr[Tag_CPU_arch_profile].i == 'M';
15053
6a5bb875
PB		 15054 /* Marking EH data may cause additional code sections to be marked,
15055 requiring multiple passes. */
15056 again = TRUE;
15057 while (again)
15058 {
15059 again = FALSE;
c72f2fb2 15060 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15061 {
15062 asection *o;
15063
0ffa91dd 15064 if (! is_arm_elf (sub))
6a5bb875
PB		 15065 continue;
15066
15067 elf_shdrp = elf_elfsections (sub);
15068 for (o = sub->sections; o != NULL; o = o->next)
15069 {
15070 Elf_Internal_Shdr *hdr;
0ffa91dd 15071
6a5bb875 15072 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15073 if (hdr->sh_type == SHT_ARM_EXIDX
15074 && hdr->sh_link
15075 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15076 && !o->gc_mark
15077 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15078 {
15079 again = TRUE;
15080 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15081 return FALSE;
15082 }
15083 }
4ba2ef8f
TP		 15084
15085 /* Mark section holding ARMv8-M secure entry functions. We mark all
15086 of them so no need for a second browsing. */
15087 if (is_v8m && first_bfd_browse)
15088 {
15089 sym_hashes = elf_sym_hashes (sub);
15090 bed = get_elf_backend_data (sub);
15091 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15092 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15093 ext_start = symtab_hdr->sh_info;
15094
15095 /* Scan symbols. */
15096 for (i = ext_start; i < sym_count; i++)
15097 {
15098 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15099
15100 /* Assume it is a special symbol. If not, cmse_scan will
15101 warn about it and user can do something about it. */
15102 if (ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
15103 {
15104 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 15105 if (!cmse_sec->gc_mark
15106 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f
TP		 15107 return FALSE;
15108 }
15109 }
15110 }
6a5bb875 15111 }
4ba2ef8f 15112 first_bfd_browse = FALSE;
6a5bb875
PB		 15113 }
15114
15115 return TRUE;
15116}
15117
3c9458e9
NC		 15118/* Treat mapping symbols as special target symbols. */
15119
15120static bfd_boolean
15121elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
15122{
b0796911
PB		 15123 return bfd_is_arm_special_symbol_name (sym->name,
15124 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 15125}
15126
0367ecfb
NC		 15127/* This is a copy of elf_find_function() from elf.c except that
15128 ARM mapping symbols are ignored when looking for function names
15129 and STT_ARM_TFUNC is considered to a function type. */
252b5132 15130
0367ecfb
NC		 15131static bfd_boolean
15132arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 15133 asymbol ** symbols,
fb167eb2 15134 asection * section,
0367ecfb
NC		 15135 bfd_vma offset,
15136 const char ** filename_ptr,
15137 const char ** functionname_ptr)
15138{
15139 const char * filename = NULL;
15140 asymbol * func = NULL;
15141 bfd_vma low_func = 0;
15142 asymbol ** p;
252b5132
RH		 15143
15144 for (p = symbols; *p != NULL; p++)
15145 {
15146 elf_symbol_type *q;
15147
15148 q = (elf_symbol_type *) *p;
15149
252b5132
RH		 15150 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
15151 {
15152 default:
15153 break;
15154 case STT_FILE:
15155 filename = bfd_asymbol_name (&q->symbol);
15156 break;
252b5132
RH		 15157 case STT_FUNC:
15158 case STT_ARM_TFUNC:
9d2da7ca 15159 case STT_NOTYPE:
b0796911 15160 /* Skip mapping symbols. */
0367ecfb 15161 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 15162 && bfd_is_arm_special_symbol_name (q->symbol.name,
15163 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 15164 continue;
15165 /* Fall through. */
6b40fcba 15166 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 15167 && q->symbol.value >= low_func
15168 && q->symbol.value <= offset)
15169 {
15170 func = (asymbol *) q;
15171 low_func = q->symbol.value;
15172 }
15173 break;
15174 }
15175 }
15176
15177 if (func == NULL)
b34976b6 15178 return FALSE;
252b5132 15179
0367ecfb
NC		 15180 if (filename_ptr)
15181 *filename_ptr = filename;
15182 if (functionname_ptr)
15183 *functionname_ptr = bfd_asymbol_name (func);
15184
15185 return TRUE;
906e58ca 15186}
0367ecfb
NC		 15187
15188
15189/* Find the nearest line to a particular section and offset, for error
15190 reporting. This code is a duplicate of the code in elf.c, except
15191 that it uses arm_elf_find_function. */
15192
15193static bfd_boolean
15194elf32_arm_find_nearest_line (bfd * abfd,
0367ecfb 15195 asymbol ** symbols,
fb167eb2 15196 asection * section,
0367ecfb
NC		 15197 bfd_vma offset,
15198 const char ** filename_ptr,
15199 const char ** functionname_ptr,
fb167eb2
AM		 15200 unsigned int * line_ptr,
15201 unsigned int * discriminator_ptr)
0367ecfb
NC		 15202{
15203 bfd_boolean found = FALSE;
15204
fb167eb2 15205 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 15206 filename_ptr, functionname_ptr,
fb167eb2
AM		 15207 line_ptr, discriminator_ptr,
15208 dwarf_debug_sections, 0,
0367ecfb
NC		 15209 & elf_tdata (abfd)->dwarf2_find_line_info))
15210 {
15211 if (!*functionname_ptr)
fb167eb2 15212 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15213 *filename_ptr ? NULL : filename_ptr,
15214 functionname_ptr);
f21f3fe0 15215
0367ecfb
NC		 15216 return TRUE;
15217 }
15218
fb167eb2
AM		 15219 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
15220 uses DWARF1. */
15221
0367ecfb
NC		 15222 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
15223 & found, filename_ptr,
15224 functionname_ptr, line_ptr,
15225 & elf_tdata (abfd)->line_info))
15226 return FALSE;
15227
15228 if (found && (*functionname_ptr || *line_ptr))
15229 return TRUE;
15230
15231 if (symbols == NULL)
15232 return FALSE;
15233
fb167eb2 15234 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15235 filename_ptr, functionname_ptr))
15236 return FALSE;
15237
15238 *line_ptr = 0;
b34976b6 15239 return TRUE;
252b5132
RH		 15240}
15241
4ab527b0
FF		 15242static bfd_boolean
15243elf32_arm_find_inliner_info (bfd * abfd,
15244 const char ** filename_ptr,
15245 const char ** functionname_ptr,
15246 unsigned int * line_ptr)
15247{
15248 bfd_boolean found;
15249 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
15250 functionname_ptr, line_ptr,
15251 & elf_tdata (abfd)->dwarf2_find_line_info);
15252 return found;
15253}
15254
252b5132
RH		 15255/* Adjust a symbol defined by a dynamic object and referenced by a
15256 regular object. The current definition is in some section of the
15257 dynamic object, but we're not including those sections. We have to
15258 change the definition to something the rest of the link can
15259 understand. */
15260
b34976b6 15261static bfd_boolean
57e8b36a
NC		 15262elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
15263 struct elf_link_hash_entry * h)
252b5132
RH		 15264{
15265 bfd * dynobj;
15266 asection * s;
b7693d02 15267 struct elf32_arm_link_hash_entry * eh;
67687978 15268 struct elf32_arm_link_hash_table *globals;
252b5132 15269
67687978 15270 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15271 if (globals == NULL)
15272 return FALSE;
15273
252b5132
RH		 15274 dynobj = elf_hash_table (info)->dynobj;
15275
15276 /* Make sure we know what is going on here. */
15277 BFD_ASSERT (dynobj != NULL
f5385ebf 15278 && (h->needs_plt
34e77a92 15279 || h->type == STT_GNU_IFUNC
f6e332e6 15280 || h->u.weakdef != NULL
f5385ebf
AM		 15281 || (h->def_dynamic
15282 && h->ref_regular
15283 && !h->def_regular)));
252b5132 15284
b7693d02
DJ		 15285 eh = (struct elf32_arm_link_hash_entry *) h;
15286
252b5132
RH		 15287 /* If this is a function, put it in the procedure linkage table. We
15288 will fill in the contents of the procedure linkage table later,
15289 when we know the address of the .got section. */
34e77a92 15290 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 15291 {
34e77a92
RS		 15292 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
15293 symbol binds locally. */
5e681ec4 15294 if (h->plt.refcount <= 0
34e77a92
RS		 15295 || (h->type != STT_GNU_IFUNC
15296 && (SYMBOL_CALLS_LOCAL (info, h)
15297 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
15298 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 15299 {
15300 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 15301 file, but the symbol was never referred to by a dynamic
15302 object, or if all references were garbage collected. In
15303 such a case, we don't actually need to build a procedure
15304 linkage table, and we can just do a PC24 reloc instead. */
15305 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15306 eh->plt.thumb_refcount = 0;
15307 eh->plt.maybe_thumb_refcount = 0;
15308 eh->plt.noncall_refcount = 0;
f5385ebf 15309 h->needs_plt = 0;
252b5132
RH		 15310 }
15311
b34976b6 15312 return TRUE;
252b5132 15313 }
5e681ec4 15314 else
b7693d02
DJ		 15315 {
15316 /* It's possible that we incorrectly decided a .plt reloc was
15317 needed for an R_ARM_PC24 or similar reloc to a non-function sym
15318 in check_relocs. We can't decide accurately between function
15319 and non-function syms in check-relocs; Objects loaded later in
15320 the link may change h->type. So fix it now. */
15321 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15322 eh->plt.thumb_refcount = 0;
15323 eh->plt.maybe_thumb_refcount = 0;
15324 eh->plt.noncall_refcount = 0;
b7693d02 15325 }
252b5132
RH		 15326
15327 /* If this is a weak symbol, and there is a real definition, the
15328 processor independent code will have arranged for us to see the
15329 real definition first, and we can just use the same value. */
f6e332e6 15330 if (h->u.weakdef != NULL)
252b5132 15331 {
f6e332e6
AM		 15332 BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined
15333 || h->u.weakdef->root.type == bfd_link_hash_defweak);
15334 h->root.u.def.section = h->u.weakdef->root.u.def.section;
15335 h->root.u.def.value = h->u.weakdef->root.u.def.value;
b34976b6 15336 return TRUE;
252b5132
RH		 15337 }
15338
ba93b8ac
DJ		 15339 /* If there are no non-GOT references, we do not need a copy
15340 relocation. */
15341 if (!h->non_got_ref)
15342 return TRUE;
15343
252b5132
RH		 15344 /* This is a reference to a symbol defined by a dynamic object which
15345 is not a function. */
15346
15347 /* If we are creating a shared library, we must presume that the
15348 only references to the symbol are via the global offset table.
15349 For such cases we need not do anything here; the relocations will
67687978
PB		 15350 be handled correctly by relocate_section. Relocatable executables
15351 can reference data in shared objects directly, so we don't need to
15352 do anything here. */
0e1862bb 15353 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 15354 return TRUE;
252b5132
RH		 15355
15356 /* We must allocate the symbol in our .dynbss section, which will
15357 become part of the .bss section of the executable. There will be
15358 an entry for this symbol in the .dynsym section. The dynamic
15359 object will contain position independent code, so all references
15360 from the dynamic object to this symbol will go through the global
15361 offset table. The dynamic linker will use the .dynsym entry to
15362 determine the address it must put in the global offset table, so
15363 both the dynamic object and the regular object will refer to the
15364 same memory location for the variable. */
3d4d4302 15365 s = bfd_get_linker_section (dynobj, ".dynbss");
252b5132
RH		 15366 BFD_ASSERT (s != NULL);
15367
5522f910
NC		 15368 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
15369 linker to copy the initial value out of the dynamic object and into
15370 the runtime process image. We need to remember the offset into the
00a97672 15371 .rel(a).bss section we are going to use. */
5522f910
NC		 15372 if (info->nocopyreloc == 0
15373 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 15374 && h->size != 0)
252b5132
RH		 15375 {
15376 asection *srel;
15377
3d4d4302 15378 srel = bfd_get_linker_section (dynobj, RELOC_SECTION (globals, ".bss"));
47beaa6a 15379 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 15380 h->needs_copy = 1;
252b5132
RH		 15381 }
15382
6cabe1ea 15383 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 15384}
15385
5e681ec4
PB		 15386/* Allocate space in .plt, .got and associated reloc sections for
15387 dynamic relocs. */
15388
15389static bfd_boolean
47beaa6a 15390allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 15391{
15392 struct bfd_link_info *info;
15393 struct elf32_arm_link_hash_table *htab;
15394 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 15395 struct elf_dyn_relocs *p;
5e681ec4
PB		 15396
15397 if (h->root.type == bfd_link_hash_indirect)
15398 return TRUE;
15399
e6a6bb22
AM		 15400 eh = (struct elf32_arm_link_hash_entry *) h;
15401
5e681ec4
PB		 15402 info = (struct bfd_link_info *) inf;
15403 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15404 if (htab == NULL)
15405 return FALSE;
5e681ec4 15406
34e77a92 15407 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 15408 && h->plt.refcount > 0)
15409 {
15410 /* Make sure this symbol is output as a dynamic symbol.
15411 Undefined weak syms won't yet be marked as dynamic. */
15412 if (h->dynindx == -1
f5385ebf 15413 && !h->forced_local)
5e681ec4 15414 {
c152c796 15415 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15416 return FALSE;
15417 }
15418
34e77a92
RS		 15419 /* If the call in the PLT entry binds locally, the associated
15420 GOT entry should use an R_ARM_IRELATIVE relocation instead of
15421 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
15422 than the .plt section. */
15423 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
15424 {
15425 eh->is_iplt = 1;
15426 if (eh->plt.noncall_refcount == 0
15427 && SYMBOL_REFERENCES_LOCAL (info, h))
15428 /* All non-call references can be resolved directly.
15429 This means that they can (and in some cases, must)
15430 resolve directly to the run-time target, rather than
15431 to the PLT. That in turns means that any .got entry
15432 would be equal to the .igot.plt entry, so there's
15433 no point having both. */
15434 h->got.refcount = 0;
15435 }
15436
0e1862bb 15437 if (bfd_link_pic (info)
34e77a92 15438 || eh->is_iplt
7359ea65 15439 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 15440 {
34e77a92 15441 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 15442
5e681ec4
PB		 15443 /* If this symbol is not defined in a regular file, and we are
15444 not generating a shared library, then set the symbol to this
15445 location in the .plt. This is required to make function
15446 pointers compare as equal between the normal executable and
15447 the shared library. */
0e1862bb 15448 if (! bfd_link_pic (info)
f5385ebf 15449 && !h->def_regular)
5e681ec4 15450 {
34e77a92 15451 h->root.u.def.section = htab->root.splt;
5e681ec4 15452 h->root.u.def.value = h->plt.offset;
5e681ec4 15453
67d74e43
DJ		 15454 /* Make sure the function is not marked as Thumb, in case
15455 it is the target of an ABS32 relocation, which will
15456 point to the PLT entry. */
39d911fc 15457 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 15458 }
022f8312 15459
00a97672
RS		 15460 /* VxWorks executables have a second set of relocations for
15461 each PLT entry. They go in a separate relocation section,
15462 which is processed by the kernel loader. */
0e1862bb 15463 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 15464 {
15465 /* There is a relocation for the initial PLT entry:
15466 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
15467 if (h->plt.offset == htab->plt_header_size)
47beaa6a 15468 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 15469
15470 /* There are two extra relocations for each subsequent
15471 PLT entry: an R_ARM_32 relocation for the GOT entry,
15472 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 15473 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 15474 }
5e681ec4
PB		 15475 }
15476 else
15477 {
15478 h->plt.offset = (bfd_vma) -1;
f5385ebf 15479 h->needs_plt = 0;
5e681ec4
PB		 15480 }
15481 }
15482 else
15483 {
15484 h->plt.offset = (bfd_vma) -1;
f5385ebf 15485 h->needs_plt = 0;
5e681ec4
PB		 15486 }
15487
0855e32b
NS		 15488 eh = (struct elf32_arm_link_hash_entry *) h;
15489 eh->tlsdesc_got = (bfd_vma) -1;
15490
5e681ec4
PB		 15491 if (h->got.refcount > 0)
15492 {
15493 asection *s;
15494 bfd_boolean dyn;
ba93b8ac
DJ		 15495 int tls_type = elf32_arm_hash_entry (h)->tls_type;
15496 int indx;
5e681ec4
PB		 15497
15498 /* Make sure this symbol is output as a dynamic symbol.
15499 Undefined weak syms won't yet be marked as dynamic. */
15500 if (h->dynindx == -1
f5385ebf 15501 && !h->forced_local)
5e681ec4 15502 {
c152c796 15503 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15504 return FALSE;
15505 }
15506
e5a52504
MM		 15507 if (!htab->symbian_p)
15508 {
362d30a1 15509 s = htab->root.sgot;
e5a52504 15510 h->got.offset = s->size;
ba93b8ac
DJ		 15511
15512 if (tls_type == GOT_UNKNOWN)
15513 abort ();
15514
15515 if (tls_type == GOT_NORMAL)
15516 /* Non-TLS symbols need one GOT slot. */
15517 s->size += 4;
15518 else
15519 {
99059e56
RM		 15520 if (tls_type & GOT_TLS_GDESC)
15521 {
0855e32b 15522 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 15523 eh->tlsdesc_got
0855e32b
NS		 15524 = (htab->root.sgotplt->size
15525 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 15526 htab->root.sgotplt->size += 8;
15527 h->got.offset = (bfd_vma) -2;
34e77a92 15528 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15529 reloc in the middle of .got.plt. */
99059e56
RM		 15530 htab->num_tls_desc++;
15531 }
0855e32b 15532
ba93b8ac 15533 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 15534 {
15535 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
15536 the symbol is both GD and GDESC, got.offset may
15537 have been overwritten. */
15538 h->got.offset = s->size;
15539 s->size += 8;
15540 }
15541
ba93b8ac
DJ		 15542 if (tls_type & GOT_TLS_IE)
15543 /* R_ARM_TLS_IE32 needs one GOT slot. */
15544 s->size += 4;
15545 }
15546
e5a52504 15547 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 15548
15549 indx = 0;
0e1862bb
L		 15550 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
15551 bfd_link_pic (info),
15552 h)
15553 && (!bfd_link_pic (info)
ba93b8ac
DJ		 15554 || !SYMBOL_REFERENCES_LOCAL (info, h)))
15555 indx = h->dynindx;
15556
15557 if (tls_type != GOT_NORMAL
0e1862bb 15558 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 15559 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15560 || h->root.type != bfd_link_hash_undefweak))
15561 {
15562 if (tls_type & GOT_TLS_IE)
47beaa6a 15563 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 15564
15565 if (tls_type & GOT_TLS_GD)
47beaa6a 15566 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15567
b38cadfb 15568 if (tls_type & GOT_TLS_GDESC)
0855e32b 15569 {
47beaa6a 15570 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 15571 /* GDESC needs a trampoline to jump to. */
15572 htab->tls_trampoline = -1;
15573 }
15574
15575 /* Only GD needs it. GDESC just emits one relocation per
15576 2 entries. */
b38cadfb 15577 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 15578 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15579 }
6f820c85 15580 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 15581 {
15582 if (htab->root.dynamic_sections_created)
15583 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
15584 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
15585 }
34e77a92
RS		 15586 else if (h->type == STT_GNU_IFUNC
15587 && eh->plt.noncall_refcount == 0)
15588 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
15589 they all resolve dynamically instead. Reserve room for the
15590 GOT entry's R_ARM_IRELATIVE relocation. */
15591 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 15592 else if (bfd_link_pic (info)
15593 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15594 || h->root.type != bfd_link_hash_undefweak))
b436d854 15595 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 15596 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 15597 }
5e681ec4
PB		 15598 }
15599 else
15600 h->got.offset = (bfd_vma) -1;
15601
a4fd1a8e
PB		 15602 /* Allocate stubs for exported Thumb functions on v4t. */
15603 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 15604 && h->def_regular
39d911fc 15605 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 15606 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
15607 {
15608 struct elf_link_hash_entry * th;
15609 struct bfd_link_hash_entry * bh;
15610 struct elf_link_hash_entry * myh;
15611 char name[1024];
15612 asection *s;
15613 bh = NULL;
15614 /* Create a new symbol to regist the real location of the function. */
15615 s = h->root.u.def.section;
906e58ca 15616 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 15617 _bfd_generic_link_add_one_symbol (info, s->owner,
15618 name, BSF_GLOBAL, s,
15619 h->root.u.def.value,
15620 NULL, TRUE, FALSE, &bh);
15621
15622 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 15623 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 15624 myh->forced_local = 1;
39d911fc 15625 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 15626 eh->export_glue = myh;
15627 th = record_arm_to_thumb_glue (info, h);
15628 /* Point the symbol at the stub. */
15629 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 15630 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 15631 h->root.u.def.section = th->root.u.def.section;
15632 h->root.u.def.value = th->root.u.def.value & ~1;
15633 }
15634
0bdcacaf 15635 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 15636 return TRUE;
15637
15638 /* In the shared -Bsymbolic case, discard space allocated for
15639 dynamic pc-relative relocs against symbols which turn out to be
15640 defined in regular objects. For the normal shared case, discard
15641 space for pc-relative relocs that have become local due to symbol
15642 visibility changes. */
15643
0e1862bb 15644 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 15645 {
469a3493
RM		 15646 /* Relocs that use pc_count are PC-relative forms, which will appear
15647 on something like ".long foo - ." or "movw REG, foo - .". We want
15648 calls to protected symbols to resolve directly to the function
15649 rather than going via the plt. If people want function pointer
15650 comparisons to work as expected then they should avoid writing
15651 assembly like ".long foo - .". */
ba93b8ac
DJ		 15652 if (SYMBOL_CALLS_LOCAL (info, h))
15653 {
0bdcacaf 15654 struct elf_dyn_relocs **pp;
ba93b8ac 15655
0bdcacaf 15656 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 15657 {
15658 p->count -= p->pc_count;
15659 p->pc_count = 0;
15660 if (p->count == 0)
15661 *pp = p->next;
15662 else
15663 pp = &p->next;
15664 }
15665 }
15666
4dfe6ac6 15667 if (htab->vxworks_p)
3348747a 15668 {
0bdcacaf 15669 struct elf_dyn_relocs **pp;
3348747a 15670
0bdcacaf 15671 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 15672 {
0bdcacaf 15673 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 15674 *pp = p->next;
15675 else
15676 pp = &p->next;
15677 }
15678 }
15679
ba93b8ac 15680 /* Also discard relocs on undefined weak syms with non-default
99059e56 15681 visibility. */
0bdcacaf 15682 if (eh->dyn_relocs != NULL
5e681ec4 15683 && h->root.type == bfd_link_hash_undefweak)
22d606e9
AM		 15684 {
15685 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT)
0bdcacaf 15686 eh->dyn_relocs = NULL;
22d606e9
AM		 15687
15688 /* Make sure undefined weak symbols are output as a dynamic
15689 symbol in PIEs. */
15690 else if (h->dynindx == -1
15691 && !h->forced_local)
15692 {
15693 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15694 return FALSE;
15695 }
15696 }
15697
67687978
PB		 15698 else if (htab->root.is_relocatable_executable && h->dynindx == -1
15699 && h->root.type == bfd_link_hash_new)
15700 {
15701 /* Output absolute symbols so that we can create relocations
15702 against them. For normal symbols we output a relocation
15703 against the section that contains them. */
15704 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15705 return FALSE;
15706 }
15707
5e681ec4
PB		 15708 }
15709 else
15710 {
15711 /* For the non-shared case, discard space for relocs against
15712 symbols which turn out to need copy relocs or are not
15713 dynamic. */
15714
f5385ebf
AM		 15715 if (!h->non_got_ref
15716 && ((h->def_dynamic
15717 && !h->def_regular)
5e681ec4
PB		 15718 || (htab->root.dynamic_sections_created
15719 && (h->root.type == bfd_link_hash_undefweak
15720 || h->root.type == bfd_link_hash_undefined))))
15721 {
15722 /* Make sure this symbol is output as a dynamic symbol.
15723 Undefined weak syms won't yet be marked as dynamic. */
15724 if (h->dynindx == -1
f5385ebf 15725 && !h->forced_local)
5e681ec4 15726 {
c152c796 15727 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15728 return FALSE;
15729 }
15730
15731 /* If that succeeded, we know we'll be keeping all the
15732 relocs. */
15733 if (h->dynindx != -1)
15734 goto keep;
15735 }
15736
0bdcacaf 15737 eh->dyn_relocs = NULL;
5e681ec4
PB		 15738
15739 keep: ;
15740 }
15741
15742 /* Finally, allocate space. */
0bdcacaf 15743 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 15744 {
0bdcacaf 15745 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 15746 if (h->type == STT_GNU_IFUNC
15747 && eh->plt.noncall_refcount == 0
15748 && SYMBOL_REFERENCES_LOCAL (info, h))
15749 elf32_arm_allocate_irelocs (info, sreloc, p->count);
15750 else
15751 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 15752 }
15753
15754 return TRUE;
15755}
15756
08d1f311
DJ		 15757/* Find any dynamic relocs that apply to read-only sections. */
15758
15759static bfd_boolean
8029a119 15760elf32_arm_readonly_dynrelocs (struct elf_link_hash_entry * h, void * inf)
08d1f311 15761{
8029a119 15762 struct elf32_arm_link_hash_entry * eh;
0bdcacaf 15763 struct elf_dyn_relocs * p;
08d1f311 15764
08d1f311 15765 eh = (struct elf32_arm_link_hash_entry *) h;
0bdcacaf 15766 for (p = eh->dyn_relocs; p != NULL; p = p->next)
08d1f311 15767 {
0bdcacaf 15768 asection *s = p->sec;
08d1f311
DJ		 15769
15770 if (s != NULL && (s->flags & SEC_READONLY) != 0)
15771 {
15772 struct bfd_link_info *info = (struct bfd_link_info *) inf;
15773
15774 info->flags |= DF_TEXTREL;
15775
15776 /* Not an error, just cut short the traversal. */
15777 return FALSE;
15778 }
15779 }
15780 return TRUE;
15781}
15782
d504ffc8
DJ		 15783void
15784bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
15785 int byteswap_code)
15786{
15787 struct elf32_arm_link_hash_table *globals;
15788
15789 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15790 if (globals == NULL)
15791 return;
15792
d504ffc8
DJ		 15793 globals->byteswap_code = byteswap_code;
15794}
15795
252b5132
RH		 15796/* Set the sizes of the dynamic sections. */
15797
b34976b6 15798static bfd_boolean
57e8b36a
NC		 15799elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
15800 struct bfd_link_info * info)
252b5132
RH		 15801{
15802 bfd * dynobj;
15803 asection * s;
b34976b6
AM		 15804 bfd_boolean plt;
15805 bfd_boolean relocs;
5e681ec4
PB		 15806 bfd *ibfd;
15807 struct elf32_arm_link_hash_table *htab;
252b5132 15808
5e681ec4 15809 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15810 if (htab == NULL)
15811 return FALSE;
15812
252b5132
RH		 15813 dynobj = elf_hash_table (info)->dynobj;
15814 BFD_ASSERT (dynobj != NULL);
39b41c9c 15815 check_use_blx (htab);
252b5132
RH		 15816
15817 if (elf_hash_table (info)->dynamic_sections_created)
15818 {
15819 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 15820 if (bfd_link_executable (info) && !info->nointerp)
252b5132 15821 {
3d4d4302 15822 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 15823 BFD_ASSERT (s != NULL);
eea6121a 15824 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 15825 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
15826 }
15827 }
5e681ec4
PB		 15828
15829 /* Set up .got offsets for local syms, and space for local dynamic
15830 relocs. */
c72f2fb2 15831 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 15832 {
5e681ec4
PB		 15833 bfd_signed_vma *local_got;
15834 bfd_signed_vma *end_local_got;
34e77a92 15835 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 15836 char *local_tls_type;
0855e32b 15837 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 15838 bfd_size_type locsymcount;
15839 Elf_Internal_Shdr *symtab_hdr;
15840 asection *srel;
4dfe6ac6 15841 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 15842 unsigned int symndx;
5e681ec4 15843
0ffa91dd 15844 if (! is_arm_elf (ibfd))
5e681ec4
PB		 15845 continue;
15846
15847 for (s = ibfd->sections; s != NULL; s = s->next)
15848 {
0bdcacaf 15849 struct elf_dyn_relocs *p;
5e681ec4 15850
0bdcacaf 15851 for (p = (struct elf_dyn_relocs *)
99059e56 15852 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 15853 {
0bdcacaf
RS		 15854 if (!bfd_is_abs_section (p->sec)
15855 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 15856 {
15857 /* Input section has been discarded, either because
15858 it is a copy of a linkonce section or due to
15859 linker script /DISCARD/, so we'll be discarding
15860 the relocs too. */
15861 }
3348747a 15862 else if (is_vxworks
0bdcacaf 15863 && strcmp (p->sec->output_section->name,
3348747a
NS		 15864 ".tls_vars") == 0)
15865 {
15866 /* Relocations in vxworks .tls_vars sections are
15867 handled specially by the loader. */
15868 }
5e681ec4
PB		 15869 else if (p->count != 0)
15870 {
0bdcacaf 15871 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 15872 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 15873 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 15874 info->flags |= DF_TEXTREL;
15875 }
15876 }
15877 }
15878
15879 local_got = elf_local_got_refcounts (ibfd);
15880 if (!local_got)
15881 continue;
15882
0ffa91dd 15883 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 15884 locsymcount = symtab_hdr->sh_info;
15885 end_local_got = local_got + locsymcount;
34e77a92 15886 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 15887 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 15888 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 15889 symndx = 0;
362d30a1
RS		 15890 s = htab->root.sgot;
15891 srel = htab->root.srelgot;
0855e32b 15892 for (; local_got < end_local_got;
34e77a92
RS		 15893 ++local_got, ++local_iplt_ptr, ++local_tls_type,
15894 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 15895 {
0855e32b 15896 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 15897 local_iplt = *local_iplt_ptr;
15898 if (local_iplt != NULL)
15899 {
15900 struct elf_dyn_relocs *p;
15901
15902 if (local_iplt->root.refcount > 0)
15903 {
15904 elf32_arm_allocate_plt_entry (info, TRUE,
15905 &local_iplt->root,
15906 &local_iplt->arm);
15907 if (local_iplt->arm.noncall_refcount == 0)
15908 /* All references to the PLT are calls, so all
15909 non-call references can resolve directly to the
15910 run-time target. This means that the .got entry
15911 would be the same as the .igot.plt entry, so there's
15912 no point creating both. */
15913 *local_got = 0;
15914 }
15915 else
15916 {
15917 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
15918 local_iplt->root.offset = (bfd_vma) -1;
15919 }
15920
15921 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
15922 {
15923 asection *psrel;
15924
15925 psrel = elf_section_data (p->sec)->sreloc;
15926 if (local_iplt->arm.noncall_refcount == 0)
15927 elf32_arm_allocate_irelocs (info, psrel, p->count);
15928 else
15929 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
15930 }
15931 }
5e681ec4
PB		 15932 if (*local_got > 0)
15933 {
34e77a92
RS		 15934 Elf_Internal_Sym *isym;
15935
eea6121a 15936 *local_got = s->size;
ba93b8ac
DJ		 15937 if (*local_tls_type & GOT_TLS_GD)
15938 /* TLS_GD relocs need an 8-byte structure in the GOT. */
15939 s->size += 8;
0855e32b
NS		 15940 if (*local_tls_type & GOT_TLS_GDESC)
15941 {
15942 *local_tlsdesc_gotent = htab->root.sgotplt->size
15943 - elf32_arm_compute_jump_table_size (htab);
15944 htab->root.sgotplt->size += 8;
15945 *local_got = (bfd_vma) -2;
34e77a92 15946 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15947 reloc in the middle of .got.plt. */
99059e56 15948 htab->num_tls_desc++;
0855e32b 15949 }
ba93b8ac
DJ		 15950 if (*local_tls_type & GOT_TLS_IE)
15951 s->size += 4;
ba93b8ac 15952
0855e32b
NS		 15953 if (*local_tls_type & GOT_NORMAL)
15954 {
15955 /* If the symbol is both GD and GDESC, *local_got
15956 may have been overwritten. */
15957 *local_got = s->size;
15958 s->size += 4;
15959 }
15960
34e77a92
RS		 15961 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
15962 if (isym == NULL)
15963 return FALSE;
15964
15965 /* If all references to an STT_GNU_IFUNC PLT are calls,
15966 then all non-call references, including this GOT entry,
15967 resolve directly to the run-time target. */
15968 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
15969 && (local_iplt == NULL
15970 || local_iplt->arm.noncall_refcount == 0))
15971 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 15972 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 15973 {
0e1862bb 15974 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 15975 || *local_tls_type & GOT_TLS_GD)
15976 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 15977
0e1862bb 15978 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 15979 {
15980 elf32_arm_allocate_dynrelocs (info,
15981 htab->root.srelplt, 1);
15982 htab->tls_trampoline = -1;
15983 }
0855e32b 15984 }
5e681ec4
PB		 15985 }
15986 else
15987 *local_got = (bfd_vma) -1;
15988 }
252b5132
RH		 15989 }
15990
ba93b8ac
DJ		 15991 if (htab->tls_ldm_got.refcount > 0)
15992 {
15993 /* Allocate two GOT entries and one dynamic relocation (if necessary)
15994 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 15995 htab->tls_ldm_got.offset = htab->root.sgot->size;
15996 htab->root.sgot->size += 8;
0e1862bb 15997 if (bfd_link_pic (info))
47beaa6a 15998 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 15999 }
16000 else
16001 htab->tls_ldm_got.offset = -1;
16002
5e681ec4
PB		 16003 /* Allocate global sym .plt and .got entries, and space for global
16004 sym dynamic relocs. */
47beaa6a 16005 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 16006
d504ffc8 16007 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 16008 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 16009 {
0ffa91dd 16010 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 16011 continue;
16012
c7b8f16e
JB		 16013 /* Initialise mapping tables for code/data. */
16014 bfd_elf32_arm_init_maps (ibfd);
906e58ca 16015
c7b8f16e 16016 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 16017 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
16018 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
99059e56
RM		 16019 /* xgettext:c-format */
16020 _bfd_error_handler (_("Errors encountered processing file %s"),
c7b8f16e
JB		 16021 ibfd->filename);
16022 }
d504ffc8 16023
3e6b1042
DJ		 16024 /* Allocate space for the glue sections now that we've sized them. */
16025 bfd_elf32_arm_allocate_interworking_sections (info);
16026
0855e32b
NS		 16027 /* For every jump slot reserved in the sgotplt, reloc_count is
16028 incremented. However, when we reserve space for TLS descriptors,
16029 it's not incremented, so in order to compute the space reserved
16030 for them, it suffices to multiply the reloc count by the jump
16031 slot size. */
16032 if (htab->root.srelplt)
16033 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
16034
16035 if (htab->tls_trampoline)
16036 {
16037 if (htab->root.splt->size == 0)
16038 htab->root.splt->size += htab->plt_header_size;
b38cadfb 16039
0855e32b
NS		 16040 htab->tls_trampoline = htab->root.splt->size;
16041 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 16042
0855e32b 16043 /* If we're not using lazy TLS relocations, don't generate the
99059e56 16044 PLT and GOT entries they require. */
0855e32b
NS		 16045 if (!(info->flags & DF_BIND_NOW))
16046 {
16047 htab->dt_tlsdesc_got = htab->root.sgot->size;
16048 htab->root.sgot->size += 4;
16049
16050 htab->dt_tlsdesc_plt = htab->root.splt->size;
16051 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
16052 }
16053 }
16054
252b5132
RH		 16055 /* The check_relocs and adjust_dynamic_symbol entry points have
16056 determined the sizes of the various dynamic sections. Allocate
16057 memory for them. */
b34976b6
AM		 16058 plt = FALSE;
16059 relocs = FALSE;
252b5132
RH		 16060 for (s = dynobj->sections; s != NULL; s = s->next)
16061 {
16062 const char * name;
252b5132
RH		 16063
16064 if ((s->flags & SEC_LINKER_CREATED) == 0)
16065 continue;
16066
16067 /* It's OK to base decisions on the section name, because none
16068 of the dynobj section names depend upon the input files. */
16069 name = bfd_get_section_name (dynobj, s);
16070
34e77a92 16071 if (s == htab->root.splt)
252b5132 16072 {
c456f082
AM		 16073 /* Remember whether there is a PLT. */
16074 plt = s->size != 0;
252b5132 16075 }
0112cd26 16076 else if (CONST_STRNEQ (name, ".rel"))
252b5132 16077 {
c456f082 16078 if (s->size != 0)
252b5132 16079 {
252b5132 16080 /* Remember whether there are any reloc sections other
00a97672 16081 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 16082 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 16083 relocs = TRUE;
252b5132
RH		 16084
16085 /* We use the reloc_count field as a counter if we need
16086 to copy relocs into the output file. */
16087 s->reloc_count = 0;
16088 }
16089 }
34e77a92
RS		 16090 else if (s != htab->root.sgot
16091 && s != htab->root.sgotplt
16092 && s != htab->root.iplt
16093 && s != htab->root.igotplt
16094 && s != htab->sdynbss)
252b5132
RH		 16095 {
16096 /* It's not one of our sections, so don't allocate space. */
16097 continue;
16098 }
16099
c456f082 16100 if (s->size == 0)
252b5132 16101 {
c456f082 16102 /* If we don't need this section, strip it from the
00a97672
RS		 16103 output file. This is mostly to handle .rel(a).bss and
16104 .rel(a).plt. We must create both sections in
c456f082
AM		 16105 create_dynamic_sections, because they must be created
16106 before the linker maps input sections to output
16107 sections. The linker does that before
16108 adjust_dynamic_symbol is called, and it is that
16109 function which decides whether anything needs to go
16110 into these sections. */
8423293d 16111 s->flags |= SEC_EXCLUDE;
252b5132
RH		 16112 continue;
16113 }
16114
c456f082
AM		 16115 if ((s->flags & SEC_HAS_CONTENTS) == 0)
16116 continue;
16117
252b5132 16118 /* Allocate memory for the section contents. */
21d799b5 16119 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 16120 if (s->contents == NULL)
b34976b6 16121 return FALSE;
252b5132
RH		 16122 }
16123
16124 if (elf_hash_table (info)->dynamic_sections_created)
16125 {
16126 /* Add some entries to the .dynamic section. We fill in the
16127 values later, in elf32_arm_finish_dynamic_sections, but we
16128 must add the entries now so that we get the correct size for
16129 the .dynamic section. The DT_DEBUG entry is filled in by the
16130 dynamic linker and used by the debugger. */
dc810e39 16131#define add_dynamic_entry(TAG, VAL) \
5a580b3a 16132 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 16133
0e1862bb 16134 if (bfd_link_executable (info))
252b5132 16135 {
dc810e39 16136 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 16137 return FALSE;
252b5132
RH		 16138 }
16139
16140 if (plt)
16141 {
dc810e39
AM		 16142 if ( !add_dynamic_entry (DT_PLTGOT, 0)
16143 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 16144 || !add_dynamic_entry (DT_PLTREL,
16145 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 16146 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 16147 return FALSE;
0855e32b 16148
5025eb7c
AO		 16149 if (htab->dt_tlsdesc_plt
16150 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
16151 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 16152 return FALSE;
252b5132
RH		 16153 }
16154
16155 if (relocs)
16156 {
00a97672
RS		 16157 if (htab->use_rel)
16158 {
16159 if (!add_dynamic_entry (DT_REL, 0)
16160 || !add_dynamic_entry (DT_RELSZ, 0)
16161 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
16162 return FALSE;
16163 }
16164 else
16165 {
16166 if (!add_dynamic_entry (DT_RELA, 0)
16167 || !add_dynamic_entry (DT_RELASZ, 0)
16168 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
16169 return FALSE;
16170 }
252b5132
RH		 16171 }
16172
08d1f311
DJ		 16173 /* If any dynamic relocs apply to a read-only section,
16174 then we need a DT_TEXTREL entry. */
16175 if ((info->flags & DF_TEXTREL) == 0)
8029a119
NC		 16176 elf_link_hash_traverse (& htab->root, elf32_arm_readonly_dynrelocs,
16177 info);
08d1f311 16178
99e4ae17 16179 if ((info->flags & DF_TEXTREL) != 0)
252b5132 16180 {
dc810e39 16181 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 16182 return FALSE;
252b5132 16183 }
7a2b07ff
NS		 16184 if (htab->vxworks_p
16185 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
16186 return FALSE;
252b5132 16187 }
8532796c 16188#undef add_dynamic_entry
252b5132 16189
b34976b6 16190 return TRUE;
252b5132
RH		 16191}
16192
0855e32b
NS		 16193/* Size sections even though they're not dynamic. We use it to setup
16194 _TLS_MODULE_BASE_, if needed. */
16195
16196static bfd_boolean
16197elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 16198 struct bfd_link_info *info)
0855e32b
NS		 16199{
16200 asection *tls_sec;
16201
0e1862bb 16202 if (bfd_link_relocatable (info))
0855e32b
NS		 16203 return TRUE;
16204
16205 tls_sec = elf_hash_table (info)->tls_sec;
16206
16207 if (tls_sec)
16208 {
16209 struct elf_link_hash_entry *tlsbase;
16210
16211 tlsbase = elf_link_hash_lookup
16212 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
16213
16214 if (tlsbase)
99059e56
RM		 16215 {
16216 struct bfd_link_hash_entry *bh = NULL;
0855e32b 16217 const struct elf_backend_data *bed
99059e56 16218 = get_elf_backend_data (output_bfd);
0855e32b 16219
99059e56 16220 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 16221 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
16222 tls_sec, 0, NULL, FALSE,
16223 bed->collect, &bh)))
16224 return FALSE;
b38cadfb 16225
99059e56
RM		 16226 tlsbase->type = STT_TLS;
16227 tlsbase = (struct elf_link_hash_entry *)bh;
16228 tlsbase->def_regular = 1;
16229 tlsbase->other = STV_HIDDEN;
16230 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 16231 }
16232 }
16233 return TRUE;
16234}
16235
252b5132
RH		 16236/* Finish up dynamic symbol handling. We set the contents of various
16237 dynamic sections here. */
16238
b34976b6 16239static bfd_boolean
906e58ca
NC		 16240elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
16241 struct bfd_link_info * info,
16242 struct elf_link_hash_entry * h,
16243 Elf_Internal_Sym * sym)
252b5132 16244{
e5a52504 16245 struct elf32_arm_link_hash_table *htab;
b7693d02 16246 struct elf32_arm_link_hash_entry *eh;
252b5132 16247
e5a52504 16248 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16249 if (htab == NULL)
16250 return FALSE;
16251
b7693d02 16252 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 16253
16254 if (h->plt.offset != (bfd_vma) -1)
16255 {
34e77a92 16256 if (!eh->is_iplt)
e5a52504 16257 {
34e77a92 16258 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 16259 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
16260 h->dynindx, 0))
16261 return FALSE;
e5a52504 16262 }
57e8b36a 16263
f5385ebf 16264 if (!h->def_regular)
252b5132
RH		 16265 {
16266 /* Mark the symbol as undefined, rather than as defined in
3a635617 16267 the .plt section. */
252b5132 16268 sym->st_shndx = SHN_UNDEF;
3a635617 16269 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 16270 Otherwise, the PLT entry would provide a definition for
16271 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 16272 and so the symbol would never be NULL. Leave the value if
16273 there were any relocations where pointer equality matters
16274 (this is a clue for the dynamic linker, to make function
16275 pointer comparisons work between an application and shared
16276 library). */
97323ad1 16277 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 16278 sym->st_value = 0;
252b5132 16279 }
34e77a92
RS		 16280 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
16281 {
16282 /* At least one non-call relocation references this .iplt entry,
16283 so the .iplt entry is the function's canonical address. */
16284 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 16285 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 16286 sym->st_shndx = (_bfd_elf_section_from_bfd_section
16287 (output_bfd, htab->root.iplt->output_section));
16288 sym->st_value = (h->plt.offset
16289 + htab->root.iplt->output_section->vma
16290 + htab->root.iplt->output_offset);
16291 }
252b5132
RH		 16292 }
16293
f5385ebf 16294 if (h->needs_copy)
252b5132
RH		 16295 {
16296 asection * s;
947216bf 16297 Elf_Internal_Rela rel;
252b5132
RH		 16298
16299 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 16300 BFD_ASSERT (h->dynindx != -1
16301 && (h->root.type == bfd_link_hash_defined
16302 || h->root.type == bfd_link_hash_defweak));
16303
362d30a1 16304 s = htab->srelbss;
252b5132
RH		 16305 BFD_ASSERT (s != NULL);
16306
00a97672 16307 rel.r_addend = 0;
252b5132
RH		 16308 rel.r_offset = (h->root.u.def.value
16309 + h->root.u.def.section->output_section->vma
16310 + h->root.u.def.section->output_offset);
16311 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
47beaa6a 16312 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 16313 }
16314
00a97672
RS		 16315 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
16316 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
16317 to the ".got" section. */
9637f6ef 16318 if (h == htab->root.hdynamic
00a97672 16319 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 16320 sym->st_shndx = SHN_ABS;
16321
b34976b6 16322 return TRUE;
252b5132
RH		 16323}
16324
0855e32b
NS		 16325static void
16326arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16327 void *contents,
16328 const unsigned long *template, unsigned count)
16329{
16330 unsigned ix;
b38cadfb 16331
0855e32b
NS		 16332 for (ix = 0; ix != count; ix++)
16333 {
16334 unsigned long insn = template[ix];
16335
16336 /* Emit mov pc,rx if bx is not permitted. */
16337 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
16338 insn = (insn & 0xf000000f) | 0x01a0f000;
16339 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
16340 }
16341}
16342
99059e56
RM		 16343/* Install the special first PLT entry for elf32-arm-nacl. Unlike
16344 other variants, NaCl needs this entry in a static executable's
16345 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
16346 zero. For .iplt really only the last bundle is useful, and .iplt
16347 could have a shorter first entry, with each individual PLT entry's
16348 relative branch calculated differently so it targets the last
16349 bundle instead of the instruction before it (labelled .Lplt_tail
16350 above). But it's simpler to keep the size and layout of PLT0
16351 consistent with the dynamic case, at the cost of some dead code at
16352 the start of .iplt and the one dead store to the stack at the start
16353 of .Lplt_tail. */
16354static void
16355arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16356 asection *plt, bfd_vma got_displacement)
16357{
16358 unsigned int i;
16359
16360 put_arm_insn (htab, output_bfd,
16361 elf32_arm_nacl_plt0_entry[0]
16362 | arm_movw_immediate (got_displacement),
16363 plt->contents + 0);
16364 put_arm_insn (htab, output_bfd,
16365 elf32_arm_nacl_plt0_entry[1]
16366 | arm_movt_immediate (got_displacement),
16367 plt->contents + 4);
16368
16369 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
16370 put_arm_insn (htab, output_bfd,
16371 elf32_arm_nacl_plt0_entry[i],
16372 plt->contents + (i * 4));
16373}
16374
252b5132
RH		 16375/* Finish up the dynamic sections. */
16376
b34976b6 16377static bfd_boolean
57e8b36a 16378elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 16379{
16380 bfd * dynobj;
16381 asection * sgot;
16382 asection * sdyn;
4dfe6ac6
NC		 16383 struct elf32_arm_link_hash_table *htab;
16384
16385 htab = elf32_arm_hash_table (info);
16386 if (htab == NULL)
16387 return FALSE;
252b5132
RH		 16388
16389 dynobj = elf_hash_table (info)->dynobj;
16390
362d30a1 16391 sgot = htab->root.sgotplt;
894891db
NC		 16392 /* A broken linker script might have discarded the dynamic sections.
16393 Catch this here so that we do not seg-fault later on. */
16394 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
16395 return FALSE;
3d4d4302 16396 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 16397
16398 if (elf_hash_table (info)->dynamic_sections_created)
16399 {
16400 asection *splt;
16401 Elf32_External_Dyn *dyncon, *dynconend;
16402
362d30a1 16403 splt = htab->root.splt;
24a1ba0f 16404 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 16405 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 16406
16407 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 16408 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 16409
252b5132
RH		 16410 for (; dyncon < dynconend; dyncon++)
16411 {
16412 Elf_Internal_Dyn dyn;
16413 const char * name;
16414 asection * s;
16415
16416 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
16417
16418 switch (dyn.d_tag)
16419 {
229fcec5
MM		 16420 unsigned int type;
16421
252b5132 16422 default:
7a2b07ff
NS		 16423 if (htab->vxworks_p
16424 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
16425 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 16426 break;
16427
229fcec5
MM		 16428 case DT_HASH:
16429 name = ".hash";
16430 goto get_vma_if_bpabi;
16431 case DT_STRTAB:
16432 name = ".dynstr";
16433 goto get_vma_if_bpabi;
16434 case DT_SYMTAB:
16435 name = ".dynsym";
16436 goto get_vma_if_bpabi;
c0042f5d
MM		 16437 case DT_VERSYM:
16438 name = ".gnu.version";
16439 goto get_vma_if_bpabi;
16440 case DT_VERDEF:
16441 name = ".gnu.version_d";
16442 goto get_vma_if_bpabi;
16443 case DT_VERNEED:
16444 name = ".gnu.version_r";
16445 goto get_vma_if_bpabi;
16446
252b5132 16447 case DT_PLTGOT:
4ade44b7 16448 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 16449 goto get_vma;
16450 case DT_JMPREL:
00a97672 16451 name = RELOC_SECTION (htab, ".plt");
252b5132 16452 get_vma:
4ade44b7 16453 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 16454 if (s == NULL)
16455 {
05456594 16456 (*_bfd_error_handler)
4ade44b7 16457 (_("could not find section %s"), name);
05456594
NC		 16458 bfd_set_error (bfd_error_invalid_operation);
16459 return FALSE;
16460 }
229fcec5 16461 if (!htab->symbian_p)
4ade44b7 16462 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 16463 else
16464 /* In the BPABI, tags in the PT_DYNAMIC section point
16465 at the file offset, not the memory address, for the
16466 convenience of the post linker. */
4ade44b7 16467 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 16468 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16469 break;
16470
229fcec5
MM		 16471 get_vma_if_bpabi:
16472 if (htab->symbian_p)
16473 goto get_vma;
16474 break;
16475
252b5132 16476 case DT_PLTRELSZ:
362d30a1 16477 s = htab->root.srelplt;
252b5132 16478 BFD_ASSERT (s != NULL);
eea6121a 16479 dyn.d_un.d_val = s->size;
252b5132
RH		 16480 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16481 break;
906e58ca 16482
252b5132 16483 case DT_RELSZ:
00a97672 16484 case DT_RELASZ:
229fcec5
MM		 16485 if (!htab->symbian_p)
16486 {
16487 /* My reading of the SVR4 ABI indicates that the
16488 procedure linkage table relocs (DT_JMPREL) should be
16489 included in the overall relocs (DT_REL). This is
16490 what Solaris does. However, UnixWare can not handle
16491 that case. Therefore, we override the DT_RELSZ entry
16492 here to make it not include the JMPREL relocs. Since
00a97672 16493 the linker script arranges for .rel(a).plt to follow all
229fcec5
MM		 16494 other relocation sections, we don't have to worry
16495 about changing the DT_REL entry. */
362d30a1 16496 s = htab->root.srelplt;
229fcec5
MM		 16497 if (s != NULL)
16498 dyn.d_un.d_val -= s->size;
16499 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16500 break;
16501 }
8029a119 16502 /* Fall through. */
229fcec5
MM		 16503
16504 case DT_REL:
16505 case DT_RELA:
229fcec5
MM		 16506 /* In the BPABI, the DT_REL tag must point at the file
16507 offset, not the VMA, of the first relocation
16508 section. So, we use code similar to that in
16509 elflink.c, but do not check for SHF_ALLOC on the
16510 relcoation section, since relocations sections are
16511 never allocated under the BPABI. The comments above
16512 about Unixware notwithstanding, we include all of the
16513 relocations here. */
16514 if (htab->symbian_p)
16515 {
16516 unsigned int i;
16517 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
16518 ? SHT_REL : SHT_RELA);
16519 dyn.d_un.d_val = 0;
16520 for (i = 1; i < elf_numsections (output_bfd); i++)
16521 {
906e58ca 16522 Elf_Internal_Shdr *hdr
229fcec5
MM		 16523 = elf_elfsections (output_bfd)[i];
16524 if (hdr->sh_type == type)
16525 {
906e58ca 16526 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 16527 || dyn.d_tag == DT_RELASZ)
16528 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 16529 else if ((ufile_ptr) hdr->sh_offset
16530 <= dyn.d_un.d_val - 1)
229fcec5
MM		 16531 dyn.d_un.d_val = hdr->sh_offset;
16532 }
16533 }
16534 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16535 }
252b5132 16536 break;
88f7bcd5 16537
0855e32b 16538 case DT_TLSDESC_PLT:
99059e56 16539 s = htab->root.splt;
0855e32b
NS		 16540 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
16541 + htab->dt_tlsdesc_plt);
16542 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16543 break;
16544
16545 case DT_TLSDESC_GOT:
99059e56 16546 s = htab->root.sgot;
0855e32b 16547 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 16548 + htab->dt_tlsdesc_got);
0855e32b
NS		 16549 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16550 break;
16551
88f7bcd5
NC		 16552 /* Set the bottom bit of DT_INIT/FINI if the
16553 corresponding function is Thumb. */
16554 case DT_INIT:
16555 name = info->init_function;
16556 goto get_sym;
16557 case DT_FINI:
16558 name = info->fini_function;
16559 get_sym:
16560 /* If it wasn't set by elf_bfd_final_link
4cc11e76 16561 then there is nothing to adjust. */
88f7bcd5
NC		 16562 if (dyn.d_un.d_val != 0)
16563 {
16564 struct elf_link_hash_entry * eh;
16565
16566 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 16567 FALSE, FALSE, TRUE);
39d911fc
TP		 16568 if (eh != NULL
16569 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
16570 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 16571 {
16572 dyn.d_un.d_val |= 1;
b34976b6 16573 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 16574 }
16575 }
16576 break;
252b5132
RH		 16577 }
16578 }
16579
24a1ba0f 16580 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 16581 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 16582 {
00a97672
RS		 16583 const bfd_vma *plt0_entry;
16584 bfd_vma got_address, plt_address, got_displacement;
16585
16586 /* Calculate the addresses of the GOT and PLT. */
16587 got_address = sgot->output_section->vma + sgot->output_offset;
16588 plt_address = splt->output_section->vma + splt->output_offset;
16589
16590 if (htab->vxworks_p)
16591 {
16592 /* The VxWorks GOT is relocated by the dynamic linker.
16593 Therefore, we must emit relocations rather than simply
16594 computing the values now. */
16595 Elf_Internal_Rela rel;
16596
16597 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 16598 put_arm_insn (htab, output_bfd, plt0_entry[0],
16599 splt->contents + 0);
16600 put_arm_insn (htab, output_bfd, plt0_entry[1],
16601 splt->contents + 4);
16602 put_arm_insn (htab, output_bfd, plt0_entry[2],
16603 splt->contents + 8);
00a97672
RS		 16604 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
16605
8029a119 16606 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 16607 rel.r_offset = plt_address + 12;
16608 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16609 rel.r_addend = 0;
16610 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
16611 htab->srelplt2->contents);
16612 }
b38cadfb 16613 else if (htab->nacl_p)
99059e56
RM		 16614 arm_nacl_put_plt0 (htab, output_bfd, splt,
16615 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 16616 else if (using_thumb_only (htab))
16617 {
16618 got_displacement = got_address - (plt_address + 12);
16619
16620 plt0_entry = elf32_thumb2_plt0_entry;
16621 put_arm_insn (htab, output_bfd, plt0_entry[0],
16622 splt->contents + 0);
16623 put_arm_insn (htab, output_bfd, plt0_entry[1],
16624 splt->contents + 4);
16625 put_arm_insn (htab, output_bfd, plt0_entry[2],
16626 splt->contents + 8);
16627
16628 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
16629 }
00a97672
RS		 16630 else
16631 {
16632 got_displacement = got_address - (plt_address + 16);
16633
16634 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 16635 put_arm_insn (htab, output_bfd, plt0_entry[0],
16636 splt->contents + 0);
16637 put_arm_insn (htab, output_bfd, plt0_entry[1],
16638 splt->contents + 4);
16639 put_arm_insn (htab, output_bfd, plt0_entry[2],
16640 splt->contents + 8);
16641 put_arm_insn (htab, output_bfd, plt0_entry[3],
16642 splt->contents + 12);
5e681ec4 16643
5e681ec4 16644#ifdef FOUR_WORD_PLT
00a97672
RS		 16645 /* The displacement value goes in the otherwise-unused
16646 last word of the second entry. */
16647 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 16648#else
00a97672 16649 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 16650#endif
00a97672 16651 }
f7a74f8c 16652 }
252b5132
RH		 16653
16654 /* UnixWare sets the entsize of .plt to 4, although that doesn't
16655 really seem like the right value. */
74541ad4
AM		 16656 if (splt->output_section->owner == output_bfd)
16657 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 16658
0855e32b
NS		 16659 if (htab->dt_tlsdesc_plt)
16660 {
16661 bfd_vma got_address
16662 = sgot->output_section->vma + sgot->output_offset;
16663 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
16664 + htab->root.sgot->output_offset);
16665 bfd_vma plt_address
16666 = splt->output_section->vma + splt->output_offset;
16667
b38cadfb 16668 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16669 splt->contents + htab->dt_tlsdesc_plt,
16670 dl_tlsdesc_lazy_trampoline, 6);
16671
16672 bfd_put_32 (output_bfd,
16673 gotplt_address + htab->dt_tlsdesc_got
16674 - (plt_address + htab->dt_tlsdesc_plt)
16675 - dl_tlsdesc_lazy_trampoline[6],
16676 splt->contents + htab->dt_tlsdesc_plt + 24);
16677 bfd_put_32 (output_bfd,
16678 got_address - (plt_address + htab->dt_tlsdesc_plt)
16679 - dl_tlsdesc_lazy_trampoline[7],
16680 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
16681 }
16682
16683 if (htab->tls_trampoline)
16684 {
b38cadfb 16685 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16686 splt->contents + htab->tls_trampoline,
16687 tls_trampoline, 3);
16688#ifdef FOUR_WORD_PLT
16689 bfd_put_32 (output_bfd, 0x00000000,
16690 splt->contents + htab->tls_trampoline + 12);
b38cadfb 16691#endif
0855e32b
NS		 16692 }
16693
0e1862bb
L		 16694 if (htab->vxworks_p
16695 && !bfd_link_pic (info)
16696 && htab->root.splt->size > 0)
00a97672
RS		 16697 {
16698 /* Correct the .rel(a).plt.unloaded relocations. They will have
16699 incorrect symbol indexes. */
16700 int num_plts;
eed62c48 16701 unsigned char *p;
00a97672 16702
362d30a1 16703 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 16704 / htab->plt_entry_size);
16705 p = htab->srelplt2->contents + RELOC_SIZE (htab);
16706
16707 for (; num_plts; num_plts--)
16708 {
16709 Elf_Internal_Rela rel;
16710
16711 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16712 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16713 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16714 p += RELOC_SIZE (htab);
16715
16716 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16717 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
16718 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16719 p += RELOC_SIZE (htab);
16720 }
16721 }
252b5132
RH		 16722 }
16723
99059e56
RM		 16724 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
16725 /* NaCl uses a special first entry in .iplt too. */
16726 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
16727
252b5132 16728 /* Fill in the first three entries in the global offset table. */
229fcec5 16729 if (sgot)
252b5132 16730 {
229fcec5
MM		 16731 if (sgot->size > 0)
16732 {
16733 if (sdyn == NULL)
16734 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
16735 else
16736 bfd_put_32 (output_bfd,
16737 sdyn->output_section->vma + sdyn->output_offset,
16738 sgot->contents);
16739 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
16740 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
16741 }
252b5132 16742
229fcec5
MM		 16743 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
16744 }
252b5132 16745
b34976b6 16746 return TRUE;
252b5132
RH		 16747}
16748
ba96a88f 16749static void
57e8b36a 16750elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 16751{
9b485d32 16752 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 16753 struct elf32_arm_link_hash_table *globals;
ac4c9b04 16754 struct elf_segment_map *m;
ba96a88f
NC		 16755
16756 i_ehdrp = elf_elfheader (abfd);
16757
94a3258f
PB		 16758 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
16759 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
16760 else
7394f108 16761 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 16762 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 16763
93204d3a
PB		 16764 if (link_info)
16765 {
16766 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 16767 if (globals != NULL && globals->byteswap_code)
93204d3a
PB		 16768 i_ehdrp->e_flags |= EF_ARM_BE8;
16769 }
3bfcb652
NC		 16770
16771 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
16772 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
16773 {
16774 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 16775 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 16776 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
16777 else
16778 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
16779 }
ac4c9b04
MG		 16780
16781 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 16782 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 16783 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
16784 {
16785 unsigned int j;
16786
16787 if (m->count == 0)
16788 continue;
16789 for (j = 0; j < m->count; j++)
16790 {
f0728ee3 16791 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 16792 break;
16793 }
16794 if (j == m->count)
16795 {
16796 m->p_flags = PF_X;
16797 m->p_flags_valid = 1;
16798 }
16799 }
ba96a88f
NC		 16800}
16801
99e4ae17 16802static enum elf_reloc_type_class
7e612e98
AM		 16803elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
16804 const asection *rel_sec ATTRIBUTE_UNUSED,
16805 const Elf_Internal_Rela *rela)
99e4ae17 16806{
f51e552e 16807 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 16808 {
16809 case R_ARM_RELATIVE:
16810 return reloc_class_relative;
16811 case R_ARM_JUMP_SLOT:
16812 return reloc_class_plt;
16813 case R_ARM_COPY:
16814 return reloc_class_copy;
109575d7
JW		 16815 case R_ARM_IRELATIVE:
16816 return reloc_class_ifunc;
99e4ae17
AJ		 16817 default:
16818 return reloc_class_normal;
16819 }
16820}
16821
e489d0ae 16822static void
57e8b36a 16823elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 16824{
5a6c6817 16825 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 16826}
16827
40a18ebd
NC		 16828/* Return TRUE if this is an unwinding table entry. */
16829
16830static bfd_boolean
16831is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
16832{
0112cd26
NC		 16833 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
16834 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 16835}
16836
16837
16838/* Set the type and flags for an ARM section. We do this by
16839 the section name, which is a hack, but ought to work. */
16840
16841static bfd_boolean
16842elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
16843{
16844 const char * name;
16845
16846 name = bfd_get_section_name (abfd, sec);
16847
16848 if (is_arm_elf_unwind_section_name (abfd, name))
16849 {
16850 hdr->sh_type = SHT_ARM_EXIDX;
16851 hdr->sh_flags |= SHF_LINK_ORDER;
16852 }
ac4c9b04 16853
f0728ee3
AV		 16854 if (sec->flags & SEC_ELF_PURECODE)
16855 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 16856
40a18ebd
NC		 16857 return TRUE;
16858}
16859
6dc132d9
L		 16860/* Handle an ARM specific section when reading an object file. This is
16861 called when bfd_section_from_shdr finds a section with an unknown
16862 type. */
40a18ebd
NC		 16863
16864static bfd_boolean
16865elf32_arm_section_from_shdr (bfd *abfd,
16866 Elf_Internal_Shdr * hdr,
6dc132d9
L		 16867 const char *name,
16868 int shindex)
40a18ebd
NC		 16869{
16870 /* There ought to be a place to keep ELF backend specific flags, but
16871 at the moment there isn't one. We just keep track of the
16872 sections by their name, instead. Fortunately, the ABI gives
16873 names for all the ARM specific sections, so we will probably get
16874 away with this. */
16875 switch (hdr->sh_type)
16876 {
16877 case SHT_ARM_EXIDX:
0951f019
RE		 16878 case SHT_ARM_PREEMPTMAP:
16879 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 16880 break;
16881
16882 default:
16883 return FALSE;
16884 }
16885
6dc132d9 16886 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 16887 return FALSE;
16888
16889 return TRUE;
16890}
e489d0ae 16891
44444f50
NC		 16892static _arm_elf_section_data *
16893get_arm_elf_section_data (asection * sec)
16894{
47b2e99c
JZ		 16895 if (sec && sec->owner && is_arm_elf (sec->owner))
16896 return elf32_arm_section_data (sec);
44444f50
NC		 16897 else
16898 return NULL;
8e3de13a
NC		 16899}
16900
4e617b1e
PB		 16901typedef struct
16902{
57402f1e 16903 void *flaginfo;
4e617b1e 16904 struct bfd_link_info *info;
91a5743d
PB		 16905 asection *sec;
16906 int sec_shndx;
6e0b88f1
AM		 16907 int (*func) (void *, const char *, Elf_Internal_Sym *,
16908 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 16909} output_arch_syminfo;
16910
16911enum map_symbol_type
16912{
16913 ARM_MAP_ARM,
16914 ARM_MAP_THUMB,
16915 ARM_MAP_DATA
16916};
16917
16918
7413f23f 16919/* Output a single mapping symbol. */
4e617b1e
PB		 16920
16921static bfd_boolean
7413f23f
DJ		 16922elf32_arm_output_map_sym (output_arch_syminfo *osi,
16923 enum map_symbol_type type,
16924 bfd_vma offset)
4e617b1e
PB		 16925{
16926 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 16927 Elf_Internal_Sym sym;
16928
91a5743d
PB		 16929 sym.st_value = osi->sec->output_section->vma
16930 + osi->sec->output_offset
16931 + offset;
4e617b1e
PB		 16932 sym.st_size = 0;
16933 sym.st_other = 0;
16934 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 16935 sym.st_shndx = osi->sec_shndx;
35fc36a8 16936 sym.st_target_internal = 0;
fe33d2fa 16937 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 16938 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 16939}
16940
34e77a92
RS		 16941/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
16942 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 16943
16944static bfd_boolean
34e77a92
RS		 16945elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
16946 bfd_boolean is_iplt_entry_p,
16947 union gotplt_union *root_plt,
16948 struct arm_plt_info *arm_plt)
4e617b1e 16949{
4e617b1e 16950 struct elf32_arm_link_hash_table *htab;
34e77a92 16951 bfd_vma addr, plt_header_size;
4e617b1e 16952
34e77a92 16953 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 16954 return TRUE;
16955
4dfe6ac6
NC		 16956 htab = elf32_arm_hash_table (osi->info);
16957 if (htab == NULL)
16958 return FALSE;
16959
34e77a92
RS		 16960 if (is_iplt_entry_p)
16961 {
16962 osi->sec = htab->root.iplt;
16963 plt_header_size = 0;
16964 }
16965 else
16966 {
16967 osi->sec = htab->root.splt;
16968 plt_header_size = htab->plt_header_size;
16969 }
16970 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
16971 (osi->info->output_bfd, osi->sec->output_section));
16972
16973 addr = root_plt->offset & -2;
4e617b1e
PB		 16974 if (htab->symbian_p)
16975 {
7413f23f 16976 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16977 return FALSE;
7413f23f 16978 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 16979 return FALSE;
16980 }
16981 else if (htab->vxworks_p)
16982 {
7413f23f 16983 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16984 return FALSE;
7413f23f 16985 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 16986 return FALSE;
7413f23f 16987 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 16988 return FALSE;
7413f23f 16989 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 16990 return FALSE;
16991 }
b38cadfb
NC		 16992 else if (htab->nacl_p)
16993 {
16994 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
16995 return FALSE;
16996 }
eed94f8f
NC		 16997 else if (using_thumb_only (htab))
16998 {
16999 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
17000 return FALSE;
6a631e86 17001 }
4e617b1e
PB		 17002 else
17003 {
34e77a92 17004 bfd_boolean thumb_stub_p;
bd97cb95 17005
34e77a92
RS		 17006 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
17007 if (thumb_stub_p)
4e617b1e 17008 {
7413f23f 17009 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 17010 return FALSE;
17011 }
17012#ifdef FOUR_WORD_PLT
7413f23f 17013 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 17014 return FALSE;
7413f23f 17015 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 17016 return FALSE;
17017#else
906e58ca 17018 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 17019 so only need to output a mapping symbol for the first PLT entry and
17020 entries with thumb thunks. */
34e77a92 17021 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 17022 {
7413f23f 17023 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 17024 return FALSE;
17025 }
17026#endif
17027 }
17028
17029 return TRUE;
17030}
17031
34e77a92
RS		 17032/* Output mapping symbols for PLT entries associated with H. */
17033
17034static bfd_boolean
17035elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
17036{
17037 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
17038 struct elf32_arm_link_hash_entry *eh;
17039
17040 if (h->root.type == bfd_link_hash_indirect)
17041 return TRUE;
17042
17043 if (h->root.type == bfd_link_hash_warning)
17044 /* When warning symbols are created, they **replace** the "real"
17045 entry in the hash table, thus we never get to see the real
17046 symbol in a hash traversal. So look at it now. */
17047 h = (struct elf_link_hash_entry *) h->root.u.i.link;
17048
17049 eh = (struct elf32_arm_link_hash_entry *) h;
17050 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
17051 &h->plt, &eh->plt);
17052}
17053
4f4faa4d
TP		 17054/* Bind a veneered symbol to its veneer identified by its hash entry
17055 STUB_ENTRY. The veneered location thus loose its symbol. */
17056
17057static void
17058arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
17059{
17060 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
17061
17062 BFD_ASSERT (hash);
17063 hash->root.root.u.def.section = stub_entry->stub_sec;
17064 hash->root.root.u.def.value = stub_entry->stub_offset;
17065 hash->root.size = stub_entry->stub_size;
17066}
17067
7413f23f
DJ		 17068/* Output a single local symbol for a generated stub. */
17069
17070static bfd_boolean
17071elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
17072 bfd_vma offset, bfd_vma size)
17073{
7413f23f
DJ		 17074 Elf_Internal_Sym sym;
17075
7413f23f
DJ		 17076 sym.st_value = osi->sec->output_section->vma
17077 + osi->sec->output_offset
17078 + offset;
17079 sym.st_size = size;
17080 sym.st_other = 0;
17081 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
17082 sym.st_shndx = osi->sec_shndx;
35fc36a8 17083 sym.st_target_internal = 0;
57402f1e 17084 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 17085}
4e617b1e 17086
da5938a2 17087static bfd_boolean
8029a119
NC		 17088arm_map_one_stub (struct bfd_hash_entry * gen_entry,
17089 void * in_arg)
da5938a2
NC		 17090{
17091 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 17092 asection *stub_sec;
17093 bfd_vma addr;
7413f23f 17094 char *stub_name;
9a008db3 17095 output_arch_syminfo *osi;
d3ce72d0 17096 const insn_sequence *template_sequence;
461a49ca
DJ		 17097 enum stub_insn_type prev_type;
17098 int size;
17099 int i;
17100 enum map_symbol_type sym_type;
da5938a2
NC		 17101
17102 /* Massage our args to the form they really have. */
17103 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 17104 osi = (output_arch_syminfo *) in_arg;
da5938a2 17105
da5938a2
NC		 17106 stub_sec = stub_entry->stub_sec;
17107
17108 /* Ensure this stub is attached to the current section being
7413f23f 17109 processed. */
da5938a2
NC		 17110 if (stub_sec != osi->sec)
17111 return TRUE;
17112
7413f23f 17113 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 17114 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 17115
17116 if (arm_stub_sym_claimed (stub_entry->stub_type))
17117 arm_stub_claim_sym (stub_entry);
17118 else
7413f23f 17119 {
4f4faa4d
TP		 17120 stub_name = stub_entry->output_name;
17121 switch (template_sequence[0].type)
17122 {
17123 case ARM_TYPE:
17124 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
17125 stub_entry->stub_size))
17126 return FALSE;
17127 break;
17128 case THUMB16_TYPE:
17129 case THUMB32_TYPE:
17130 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
17131 stub_entry->stub_size))
17132 return FALSE;
17133 break;
17134 default:
17135 BFD_FAIL ();
17136 return 0;
17137 }
7413f23f 17138 }
da5938a2 17139
461a49ca
DJ		 17140 prev_type = DATA_TYPE;
17141 size = 0;
17142 for (i = 0; i < stub_entry->stub_template_size; i++)
17143 {
d3ce72d0 17144 switch (template_sequence[i].type)
461a49ca
DJ		 17145 {
17146 case ARM_TYPE:
17147 sym_type = ARM_MAP_ARM;
17148 break;
17149
17150 case THUMB16_TYPE:
48229727 17151 case THUMB32_TYPE:
461a49ca
DJ		 17152 sym_type = ARM_MAP_THUMB;
17153 break;
17154
17155 case DATA_TYPE:
17156 sym_type = ARM_MAP_DATA;
17157 break;
17158
17159 default:
17160 BFD_FAIL ();
4e31c731 17161 return FALSE;
461a49ca
DJ		 17162 }
17163
d3ce72d0 17164 if (template_sequence[i].type != prev_type)
461a49ca 17165 {
d3ce72d0 17166 prev_type = template_sequence[i].type;
461a49ca
DJ		 17167 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
17168 return FALSE;
17169 }
17170
d3ce72d0 17171 switch (template_sequence[i].type)
461a49ca
DJ		 17172 {
17173 case ARM_TYPE:
48229727 17174 case THUMB32_TYPE:
461a49ca
DJ		 17175 size += 4;
17176 break;
17177
17178 case THUMB16_TYPE:
17179 size += 2;
17180 break;
17181
17182 case DATA_TYPE:
17183 size += 4;
17184 break;
17185
17186 default:
17187 BFD_FAIL ();
4e31c731 17188 return FALSE;
461a49ca
DJ		 17189 }
17190 }
17191
da5938a2
NC		 17192 return TRUE;
17193}
17194
33811162
DG		 17195/* Output mapping symbols for linker generated sections,
17196 and for those data-only sections that do not have a
17197 $d. */
4e617b1e
PB		 17198
17199static bfd_boolean
17200elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 17201 struct bfd_link_info *info,
57402f1e 17202 void *flaginfo,
6e0b88f1
AM		 17203 int (*func) (void *, const char *,
17204 Elf_Internal_Sym *,
17205 asection *,
17206 struct elf_link_hash_entry *))
4e617b1e
PB		 17207{
17208 output_arch_syminfo osi;
17209 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 17210 bfd_vma offset;
17211 bfd_size_type size;
33811162 17212 bfd *input_bfd;
4e617b1e
PB		 17213
17214 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17215 if (htab == NULL)
17216 return FALSE;
17217
906e58ca 17218 check_use_blx (htab);
91a5743d 17219
57402f1e 17220 osi.flaginfo = flaginfo;
4e617b1e
PB		 17221 osi.info = info;
17222 osi.func = func;
906e58ca 17223
33811162
DG		 17224 /* Add a $d mapping symbol to data-only sections that
17225 don't have any mapping symbol. This may result in (harmless) redundant
17226 mapping symbols. */
17227 for (input_bfd = info->input_bfds;
17228 input_bfd != NULL;
c72f2fb2 17229 input_bfd = input_bfd->link.next)
33811162
DG		 17230 {
17231 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
17232 for (osi.sec = input_bfd->sections;
17233 osi.sec != NULL;
17234 osi.sec = osi.sec->next)
17235 {
17236 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 17237 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
17238 != 0)
33811162
DG		 17239 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
17240 == SEC_HAS_CONTENTS
17241 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 17242 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 17243 && osi.sec->size > 0
17244 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 17245 {
17246 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17247 (output_bfd, osi.sec->output_section);
17248 if (osi.sec_shndx != (int)SHN_BAD)
17249 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
17250 }
17251 }
17252 }
17253
91a5743d
PB		 17254 /* ARM->Thumb glue. */
17255 if (htab->arm_glue_size > 0)
17256 {
3d4d4302
AM		 17257 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17258 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 17259
17260 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17261 (output_bfd, osi.sec->output_section);
0e1862bb 17262 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 17263 || htab->pic_veneer)
17264 size = ARM2THUMB_PIC_GLUE_SIZE;
17265 else if (htab->use_blx)
17266 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
17267 else
17268 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 17269
91a5743d
PB		 17270 for (offset = 0; offset < htab->arm_glue_size; offset += size)
17271 {
7413f23f
DJ		 17272 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
17273 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 17274 }
17275 }
17276
17277 /* Thumb->ARM glue. */
17278 if (htab->thumb_glue_size > 0)
17279 {
3d4d4302
AM		 17280 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17281 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 17282
17283 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17284 (output_bfd, osi.sec->output_section);
17285 size = THUMB2ARM_GLUE_SIZE;
17286
17287 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
17288 {
7413f23f
DJ		 17289 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
17290 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 17291 }
17292 }
17293
845b51d6
PB		 17294 /* ARMv4 BX veneers. */
17295 if (htab->bx_glue_size > 0)
17296 {
3d4d4302
AM		 17297 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17298 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 17299
17300 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17301 (output_bfd, osi.sec->output_section);
17302
7413f23f 17303 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 17304 }
17305
8029a119
NC		 17306 /* Long calls stubs. */
17307 if (htab->stub_bfd && htab->stub_bfd->sections)
17308 {
da5938a2 17309 asection* stub_sec;
8029a119 17310
da5938a2
NC		 17311 for (stub_sec = htab->stub_bfd->sections;
17312 stub_sec != NULL;
8029a119
NC		 17313 stub_sec = stub_sec->next)
17314 {
17315 /* Ignore non-stub sections. */
17316 if (!strstr (stub_sec->name, STUB_SUFFIX))
17317 continue;
da5938a2 17318
8029a119 17319 osi.sec = stub_sec;
da5938a2 17320
8029a119
NC		 17321 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17322 (output_bfd, osi.sec->output_section);
da5938a2 17323
8029a119
NC		 17324 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
17325 }
17326 }
da5938a2 17327
91a5743d 17328 /* Finally, output mapping symbols for the PLT. */
34e77a92 17329 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 17330 {
34e77a92
RS		 17331 osi.sec = htab->root.splt;
17332 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17333 (output_bfd, osi.sec->output_section));
17334
17335 /* Output mapping symbols for the plt header. SymbianOS does not have a
17336 plt header. */
17337 if (htab->vxworks_p)
17338 {
17339 /* VxWorks shared libraries have no PLT header. */
0e1862bb 17340 if (!bfd_link_pic (info))
34e77a92
RS		 17341 {
17342 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17343 return FALSE;
17344 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17345 return FALSE;
17346 }
17347 }
b38cadfb
NC		 17348 else if (htab->nacl_p)
17349 {
17350 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17351 return FALSE;
17352 }
eed94f8f
NC		 17353 else if (using_thumb_only (htab))
17354 {
17355 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
17356 return FALSE;
17357 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17358 return FALSE;
17359 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
17360 return FALSE;
17361 }
34e77a92 17362 else if (!htab->symbian_p)
4e617b1e 17363 {
7413f23f 17364 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 17365 return FALSE;
34e77a92
RS		 17366#ifndef FOUR_WORD_PLT
17367 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 17368 return FALSE;
34e77a92 17369#endif
4e617b1e
PB		 17370 }
17371 }
99059e56
RM		 17372 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
17373 {
17374 /* NaCl uses a special first entry in .iplt too. */
17375 osi.sec = htab->root.iplt;
17376 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17377 (output_bfd, osi.sec->output_section));
17378 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17379 return FALSE;
17380 }
34e77a92
RS		 17381 if ((htab->root.splt && htab->root.splt->size > 0)
17382 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 17383 {
34e77a92
RS		 17384 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
17385 for (input_bfd = info->input_bfds;
17386 input_bfd != NULL;
c72f2fb2 17387 input_bfd = input_bfd->link.next)
34e77a92
RS		 17388 {
17389 struct arm_local_iplt_info **local_iplt;
17390 unsigned int i, num_syms;
4e617b1e 17391
34e77a92
RS		 17392 local_iplt = elf32_arm_local_iplt (input_bfd);
17393 if (local_iplt != NULL)
17394 {
17395 num_syms = elf_symtab_hdr (input_bfd).sh_info;
17396 for (i = 0; i < num_syms; i++)
17397 if (local_iplt[i] != NULL
17398 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
17399 &local_iplt[i]->root,
17400 &local_iplt[i]->arm))
17401 return FALSE;
17402 }
17403 }
17404 }
0855e32b
NS		 17405 if (htab->dt_tlsdesc_plt != 0)
17406 {
17407 /* Mapping symbols for the lazy tls trampoline. */
17408 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
17409 return FALSE;
b38cadfb 17410
0855e32b
NS		 17411 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17412 htab->dt_tlsdesc_plt + 24))
17413 return FALSE;
17414 }
17415 if (htab->tls_trampoline != 0)
17416 {
17417 /* Mapping symbols for the tls trampoline. */
17418 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
17419 return FALSE;
17420#ifdef FOUR_WORD_PLT
17421 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17422 htab->tls_trampoline + 12))
17423 return FALSE;
b38cadfb 17424#endif
0855e32b 17425 }
b38cadfb 17426
4e617b1e
PB		 17427 return TRUE;
17428}
17429
54ddd295
TP		 17430/* Filter normal symbols of CMSE entry functions of ABFD to include in
17431 the import library. All SYMCOUNT symbols of ABFD can be examined
17432 from their pointers in SYMS. Pointers of symbols to keep should be
17433 stored continuously at the beginning of that array.
17434
17435 Returns the number of symbols to keep. */
17436
17437static unsigned int
17438elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17439 struct bfd_link_info *info,
17440 asymbol **syms, long symcount)
17441{
17442 size_t maxnamelen;
17443 char *cmse_name;
17444 long src_count, dst_count = 0;
17445 struct elf32_arm_link_hash_table *htab;
17446
17447 htab = elf32_arm_hash_table (info);
17448 if (!htab->stub_bfd || !htab->stub_bfd->sections)
17449 symcount = 0;
17450
17451 maxnamelen = 128;
17452 cmse_name = (char *) bfd_malloc (maxnamelen);
17453 for (src_count = 0; src_count < symcount; src_count++)
17454 {
17455 struct elf32_arm_link_hash_entry *cmse_hash;
17456 asymbol *sym;
17457 flagword flags;
17458 char *name;
17459 size_t namelen;
17460
17461 sym = syms[src_count];
17462 flags = sym->flags;
17463 name = (char *) bfd_asymbol_name (sym);
17464
17465 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
17466 continue;
17467 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
17468 continue;
17469
17470 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
17471 if (namelen > maxnamelen)
17472 {
17473 cmse_name = (char *)
17474 bfd_realloc (cmse_name, namelen);
17475 maxnamelen = namelen;
17476 }
17477 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
17478 cmse_hash = (struct elf32_arm_link_hash_entry *)
17479 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
17480
17481 if (!cmse_hash
17482 || (cmse_hash->root.root.type != bfd_link_hash_defined
17483 && cmse_hash->root.root.type != bfd_link_hash_defweak)
17484 || cmse_hash->root.type != STT_FUNC)
17485 continue;
17486
17487 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
17488 continue;
17489
17490 syms[dst_count++] = sym;
17491 }
17492 free (cmse_name);
17493
17494 syms[dst_count] = NULL;
17495
17496 return dst_count;
17497}
17498
17499/* Filter symbols of ABFD to include in the import library. All
17500 SYMCOUNT symbols of ABFD can be examined from their pointers in
17501 SYMS. Pointers of symbols to keep should be stored continuously at
17502 the beginning of that array.
17503
17504 Returns the number of symbols to keep. */
17505
17506static unsigned int
17507elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17508 struct bfd_link_info *info,
17509 asymbol **syms, long symcount)
17510{
17511 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
17512
17513 if (globals->cmse_implib)
17514 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
17515 else
17516 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
17517}
17518
e489d0ae
PB		 17519/* Allocate target specific section data. */
17520
17521static bfd_boolean
17522elf32_arm_new_section_hook (bfd *abfd, asection *sec)
17523{
f592407e
AM		 17524 if (!sec->used_by_bfd)
17525 {
17526 _arm_elf_section_data *sdata;
17527 bfd_size_type amt = sizeof (*sdata);
e489d0ae 17528
21d799b5 17529 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 17530 if (sdata == NULL)
17531 return FALSE;
17532 sec->used_by_bfd = sdata;
17533 }
e489d0ae
PB		 17534
17535 return _bfd_elf_new_section_hook (abfd, sec);
17536}
17537
17538
17539/* Used to order a list of mapping symbols by address. */
17540
17541static int
17542elf32_arm_compare_mapping (const void * a, const void * b)
17543{
7f6a71ff
JM		 17544 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
17545 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
17546
17547 if (amap->vma > bmap->vma)
17548 return 1;
17549 else if (amap->vma < bmap->vma)
17550 return -1;
17551 else if (amap->type > bmap->type)
17552 /* Ensure results do not depend on the host qsort for objects with
17553 multiple mapping symbols at the same address by sorting on type
17554 after vma. */
17555 return 1;
17556 else if (amap->type < bmap->type)
17557 return -1;
17558 else
17559 return 0;
e489d0ae
PB		 17560}
17561
2468f9c9
PB		 17562/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
17563
17564static unsigned long
17565offset_prel31 (unsigned long addr, bfd_vma offset)
17566{
17567 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
17568}
17569
17570/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
17571 relocations. */
17572
17573static void
17574copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
17575{
17576 unsigned long first_word = bfd_get_32 (output_bfd, from);
17577 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 17578
2468f9c9
PB		 17579 /* High bit of first word is supposed to be zero. */
17580 if ((first_word & 0x80000000ul) == 0)
17581 first_word = offset_prel31 (first_word, offset);
b38cadfb 17582
2468f9c9
PB		 17583 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
17584 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
17585 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
17586 second_word = offset_prel31 (second_word, offset);
b38cadfb 17587
2468f9c9
PB		 17588 bfd_put_32 (output_bfd, first_word, to);
17589 bfd_put_32 (output_bfd, second_word, to + 4);
17590}
e489d0ae 17591
48229727
JB		 17592/* Data for make_branch_to_a8_stub(). */
17593
b38cadfb
NC		 17594struct a8_branch_to_stub_data
17595{
48229727
JB		 17596 asection *writing_section;
17597 bfd_byte *contents;
17598};
17599
17600
17601/* Helper to insert branches to Cortex-A8 erratum stubs in the right
17602 places for a particular section. */
17603
17604static bfd_boolean
17605make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 17606 void *in_arg)
48229727
JB		 17607{
17608 struct elf32_arm_stub_hash_entry *stub_entry;
17609 struct a8_branch_to_stub_data *data;
17610 bfd_byte *contents;
17611 unsigned long branch_insn;
17612 bfd_vma veneered_insn_loc, veneer_entry_loc;
17613 bfd_signed_vma branch_offset;
17614 bfd *abfd;
8d9d9490 17615 unsigned int loc;
48229727
JB		 17616
17617 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
17618 data = (struct a8_branch_to_stub_data *) in_arg;
17619
17620 if (stub_entry->target_section != data->writing_section
4563a860 17621 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 17622 return TRUE;
17623
17624 contents = data->contents;
17625
8d9d9490
TP		 17626 /* We use target_section as Cortex-A8 erratum workaround stubs are only
17627 generated when both source and target are in the same section. */
48229727
JB		 17628 veneered_insn_loc = stub_entry->target_section->output_section->vma
17629 + stub_entry->target_section->output_offset
8d9d9490 17630 + stub_entry->source_value;
48229727
JB		 17631
17632 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
17633 + stub_entry->stub_sec->output_offset
17634 + stub_entry->stub_offset;
17635
17636 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
17637 veneered_insn_loc &= ~3u;
17638
17639 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
17640
17641 abfd = stub_entry->target_section->owner;
8d9d9490 17642 loc = stub_entry->source_value;
48229727
JB		 17643
17644 /* We attempt to avoid this condition by setting stubs_always_after_branch
17645 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
17646 This check is just to be on the safe side... */
17647 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
17648 {
17649 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub is "
17650 "allocated in unsafe location"), abfd);
17651 return FALSE;
17652 }
17653
17654 switch (stub_entry->stub_type)
17655 {
17656 case arm_stub_a8_veneer_b:
17657 case arm_stub_a8_veneer_b_cond:
17658 branch_insn = 0xf0009000;
17659 goto jump24;
17660
17661 case arm_stub_a8_veneer_blx:
17662 branch_insn = 0xf000e800;
17663 goto jump24;
17664
17665 case arm_stub_a8_veneer_bl:
17666 {
17667 unsigned int i1, j1, i2, j2, s;
17668
17669 branch_insn = 0xf000d000;
17670
17671 jump24:
17672 if (branch_offset < -16777216 || branch_offset > 16777214)
17673 {
17674 /* There's not much we can do apart from complain if this
17675 happens. */
17676 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub out "
17677 "of range (input file too large)"), abfd);
17678 return FALSE;
17679 }
17680
17681 /* i1 = not(j1 eor s), so:
17682 not i1 = j1 eor s
17683 j1 = (not i1) eor s. */
17684
17685 branch_insn |= (branch_offset >> 1) & 0x7ff;
17686 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
17687 i2 = (branch_offset >> 22) & 1;
17688 i1 = (branch_offset >> 23) & 1;
17689 s = (branch_offset >> 24) & 1;
17690 j1 = (!i1) ^ s;
17691 j2 = (!i2) ^ s;
17692 branch_insn |= j2 << 11;
17693 branch_insn |= j1 << 13;
17694 branch_insn |= s << 26;
17695 }
17696 break;
17697
17698 default:
17699 BFD_FAIL ();
17700 return FALSE;
17701 }
17702
8d9d9490
TP		 17703 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
17704 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 17705
17706 return TRUE;
17707}
17708
a504d23a
LA		 17709/* Beginning of stm32l4xx work-around. */
17710
17711/* Functions encoding instructions necessary for the emission of the
17712 fix-stm32l4xx-629360.
17713 Encoding is extracted from the
17714 ARM (C) Architecture Reference Manual
17715 ARMv7-A and ARMv7-R edition
17716 ARM DDI 0406C.b (ID072512). */
17717
17718static inline bfd_vma
82188b29 17719create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 17720{
17721 /* A8.8.18 B (A8-334)
17722 B target_address (Encoding T4). */
17723 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
17724 /* jump offset is: S:I1:I2:imm10:imm11:0. */
17725 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
17726
a504d23a
LA		 17727 int s = ((branch_offset & 0x1000000) >> 24);
17728 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
17729 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
17730
17731 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
17732 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
17733
17734 bfd_vma patched_inst = 0xf0009000
17735 | s << 26 /* S. */
17736 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
17737 | j1 << 13 /* J1. */
17738 | j2 << 11 /* J2. */
17739 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
17740
17741 return patched_inst;
17742}
17743
17744static inline bfd_vma
17745create_instruction_ldmia (int base_reg, int wback, int reg_mask)
17746{
17747 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
17748 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
17749 bfd_vma patched_inst = 0xe8900000
17750 | (/*W=*/wback << 21)
17751 | (base_reg << 16)
17752 | (reg_mask & 0x0000ffff);
17753
17754 return patched_inst;
17755}
17756
17757static inline bfd_vma
17758create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
17759{
17760 /* A8.8.60 LDMDB/LDMEA (A8-402)
17761 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
17762 bfd_vma patched_inst = 0xe9100000
17763 | (/*W=*/wback << 21)
17764 | (base_reg << 16)
17765 | (reg_mask & 0x0000ffff);
17766
17767 return patched_inst;
17768}
17769
17770static inline bfd_vma
17771create_instruction_mov (int target_reg, int source_reg)
17772{
17773 /* A8.8.103 MOV (register) (A8-486)
17774 MOV Rd, Rm (Encoding T1). */
17775 bfd_vma patched_inst = 0x4600
17776 | (target_reg & 0x7)
17777 | ((target_reg & 0x8) >> 3) << 7
17778 | (source_reg << 3);
17779
17780 return patched_inst;
17781}
17782
17783static inline bfd_vma
17784create_instruction_sub (int target_reg, int source_reg, int value)
17785{
17786 /* A8.8.221 SUB (immediate) (A8-708)
17787 SUB Rd, Rn, #value (Encoding T3). */
17788 bfd_vma patched_inst = 0xf1a00000
17789 | (target_reg << 8)
17790 | (source_reg << 16)
17791 | (/*S=*/0 << 20)
17792 | ((value & 0x800) >> 11) << 26
17793 | ((value & 0x700) >> 8) << 12
17794 | (value & 0x0ff);
17795
17796 return patched_inst;
17797}
17798
17799static inline bfd_vma
9239bbd3 17800create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 17801 int first_reg)
17802{
17803 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17804 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
17805 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 17806 | (/*W=*/wback << 21)
17807 | (base_reg << 16)
9239bbd3
CM		 17808 | (num_words & 0x000000ff)
17809 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 17810 | (first_reg & 0x00000001) << 22;
17811
17812 return patched_inst;
17813}
17814
17815static inline bfd_vma
9239bbd3
CM		 17816create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
17817 int first_reg)
a504d23a
LA		 17818{
17819 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17820 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
17821 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 17822 | (base_reg << 16)
9239bbd3
CM		 17823 | (num_words & 0x000000ff)
17824 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 17825 | (first_reg & 0x00000001) << 22;
17826
17827 return patched_inst;
17828}
17829
17830static inline bfd_vma
17831create_instruction_udf_w (int value)
17832{
17833 /* A8.8.247 UDF (A8-758)
17834 Undefined (Encoding T2). */
17835 bfd_vma patched_inst = 0xf7f0a000
17836 | (value & 0x00000fff)
17837 | (value & 0x000f0000) << 16;
17838
17839 return patched_inst;
17840}
17841
17842static inline bfd_vma
17843create_instruction_udf (int value)
17844{
17845 /* A8.8.247 UDF (A8-758)
17846 Undefined (Encoding T1). */
17847 bfd_vma patched_inst = 0xde00
17848 | (value & 0xff);
17849
17850 return patched_inst;
17851}
17852
17853/* Functions writing an instruction in memory, returning the next
17854 memory position to write to. */
17855
17856static inline bfd_byte *
17857push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
17858 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17859{
17860 put_thumb2_insn (htab, output_bfd, insn, pt);
17861 return pt + 4;
17862}
17863
17864static inline bfd_byte *
17865push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
17866 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17867{
17868 put_thumb_insn (htab, output_bfd, insn, pt);
17869 return pt + 2;
17870}
17871
17872/* Function filling up a region in memory with T1 and T2 UDFs taking
17873 care of alignment. */
17874
17875static bfd_byte *
17876stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
17877 bfd * output_bfd,
17878 const bfd_byte * const base_stub_contents,
17879 bfd_byte * const from_stub_contents,
17880 const bfd_byte * const end_stub_contents)
17881{
17882 bfd_byte *current_stub_contents = from_stub_contents;
17883
17884 /* Fill the remaining of the stub with deterministic contents : UDF
17885 instructions.
17886 Check if realignment is needed on modulo 4 frontier using T1, to
17887 further use T2. */
17888 if ((current_stub_contents < end_stub_contents)
17889 && !((current_stub_contents - base_stub_contents) % 2)
17890 && ((current_stub_contents - base_stub_contents) % 4))
17891 current_stub_contents =
17892 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17893 create_instruction_udf (0));
17894
17895 for (; current_stub_contents < end_stub_contents;)
17896 current_stub_contents =
17897 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17898 create_instruction_udf_w (0));
17899
17900 return current_stub_contents;
17901}
17902
17903/* Functions writing the stream of instructions equivalent to the
17904 derived sequence for ldmia, ldmdb, vldm respectively. */
17905
17906static void
17907stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
17908 bfd * output_bfd,
17909 const insn32 initial_insn,
17910 const bfd_byte *const initial_insn_addr,
17911 bfd_byte *const base_stub_contents)
17912{
17913 int wback = (initial_insn & 0x00200000) >> 21;
17914 int ri, rn = (initial_insn & 0x000F0000) >> 16;
17915 int insn_all_registers = initial_insn & 0x0000ffff;
17916 int insn_low_registers, insn_high_registers;
17917 int usable_register_mask;
17918 int nb_registers = popcount (insn_all_registers);
17919 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
17920 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
17921 bfd_byte *current_stub_contents = base_stub_contents;
17922
17923 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
17924
17925 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
17926 smaller than 8 registers load sequences that do not cause the
17927 hardware issue. */
17928 if (nb_registers <= 8)
17929 {
17930 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
17931 current_stub_contents =
17932 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17933 initial_insn);
17934
17935 /* B initial_insn_addr+4. */
17936 if (!restore_pc)
17937 current_stub_contents =
17938 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17939 create_instruction_branch_absolute
82188b29 17940 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17941
17942 /* Fill the remaining of the stub with deterministic contents. */
17943 current_stub_contents =
17944 stm32l4xx_fill_stub_udf (htab, output_bfd,
17945 base_stub_contents, current_stub_contents,
17946 base_stub_contents +
17947 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17948
17949 return;
17950 }
17951
17952 /* - reg_list[13] == 0. */
17953 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
17954
17955 /* - reg_list[14] & reg_list[15] != 1. */
17956 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
17957
17958 /* - if (wback==1) reg_list[rn] == 0. */
17959 BFD_ASSERT (!wback || !restore_rn);
17960
17961 /* - nb_registers > 8. */
17962 BFD_ASSERT (popcount (insn_all_registers) > 8);
17963
17964 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
17965
17966 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
17967 - One with the 7 lowest registers (register mask 0x007F)
17968 This LDM will finally contain between 2 and 7 registers
17969 - One with the 7 highest registers (register mask 0xDF80)
17970 This ldm will finally contain between 2 and 7 registers. */
17971 insn_low_registers = insn_all_registers & 0x007F;
17972 insn_high_registers = insn_all_registers & 0xDF80;
17973
17974 /* A spare register may be needed during this veneer to temporarily
17975 handle the base register. This register will be restored with the
17976 last LDM operation.
17977 The usable register may be any general purpose register (that
17978 excludes PC, SP, LR : register mask is 0x1FFF). */
17979 usable_register_mask = 0x1FFF;
17980
17981 /* Generate the stub function. */
17982 if (wback)
17983 {
17984 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
17985 current_stub_contents =
17986 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17987 create_instruction_ldmia
17988 (rn, /*wback=*/1, insn_low_registers));
17989
17990 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
17991 current_stub_contents =
17992 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17993 create_instruction_ldmia
17994 (rn, /*wback=*/1, insn_high_registers));
17995 if (!restore_pc)
17996 {
17997 /* B initial_insn_addr+4. */
17998 current_stub_contents =
17999 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18000 create_instruction_branch_absolute
82188b29 18001 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18002 }
18003 }
18004 else /* if (!wback). */
18005 {
18006 ri = rn;
18007
18008 /* If Rn is not part of the high-register-list, move it there. */
18009 if (!(insn_high_registers & (1 << rn)))
18010 {
18011 /* Choose a Ri in the high-register-list that will be restored. */
18012 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18013
18014 /* MOV Ri, Rn. */
18015 current_stub_contents =
18016 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18017 create_instruction_mov (ri, rn));
18018 }
18019
18020 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
18021 current_stub_contents =
18022 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18023 create_instruction_ldmia
18024 (ri, /*wback=*/1, insn_low_registers));
18025
18026 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
18027 current_stub_contents =
18028 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18029 create_instruction_ldmia
18030 (ri, /*wback=*/0, insn_high_registers));
18031
18032 if (!restore_pc)
18033 {
18034 /* B initial_insn_addr+4. */
18035 current_stub_contents =
18036 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18037 create_instruction_branch_absolute
82188b29 18038 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18039 }
18040 }
18041
18042 /* Fill the remaining of the stub with deterministic contents. */
18043 current_stub_contents =
18044 stm32l4xx_fill_stub_udf (htab, output_bfd,
18045 base_stub_contents, current_stub_contents,
18046 base_stub_contents +
18047 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18048}
18049
18050static void
18051stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
18052 bfd * output_bfd,
18053 const insn32 initial_insn,
18054 const bfd_byte *const initial_insn_addr,
18055 bfd_byte *const base_stub_contents)
18056{
18057 int wback = (initial_insn & 0x00200000) >> 21;
18058 int ri, rn = (initial_insn & 0x000f0000) >> 16;
18059 int insn_all_registers = initial_insn & 0x0000ffff;
18060 int insn_low_registers, insn_high_registers;
18061 int usable_register_mask;
18062 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18063 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
18064 int nb_registers = popcount (insn_all_registers);
18065 bfd_byte *current_stub_contents = base_stub_contents;
18066
18067 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
18068
18069 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18070 smaller than 8 registers load sequences that do not cause the
18071 hardware issue. */
18072 if (nb_registers <= 8)
18073 {
18074 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18075 current_stub_contents =
18076 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18077 initial_insn);
18078
18079 /* B initial_insn_addr+4. */
18080 current_stub_contents =
18081 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18082 create_instruction_branch_absolute
82188b29 18083 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18084
18085 /* Fill the remaining of the stub with deterministic contents. */
18086 current_stub_contents =
18087 stm32l4xx_fill_stub_udf (htab, output_bfd,
18088 base_stub_contents, current_stub_contents,
18089 base_stub_contents +
18090 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18091
18092 return;
18093 }
18094
18095 /* - reg_list[13] == 0. */
18096 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
18097
18098 /* - reg_list[14] & reg_list[15] != 1. */
18099 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
18100
18101 /* - if (wback==1) reg_list[rn] == 0. */
18102 BFD_ASSERT (!wback || !restore_rn);
18103
18104 /* - nb_registers > 8. */
18105 BFD_ASSERT (popcount (insn_all_registers) > 8);
18106
18107 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18108
18109 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
18110 - One with the 7 lowest registers (register mask 0x007F)
18111 This LDM will finally contain between 2 and 7 registers
18112 - One with the 7 highest registers (register mask 0xDF80)
18113 This ldm will finally contain between 2 and 7 registers. */
18114 insn_low_registers = insn_all_registers & 0x007F;
18115 insn_high_registers = insn_all_registers & 0xDF80;
18116
18117 /* A spare register may be needed during this veneer to temporarily
18118 handle the base register. This register will be restored with
18119 the last LDM operation.
18120 The usable register may be any general purpose register (that excludes
18121 PC, SP, LR : register mask is 0x1FFF). */
18122 usable_register_mask = 0x1FFF;
18123
18124 /* Generate the stub function. */
18125 if (!wback && !restore_pc && !restore_rn)
18126 {
18127 /* Choose a Ri in the low-register-list that will be restored. */
18128 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18129
18130 /* MOV Ri, Rn. */
18131 current_stub_contents =
18132 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18133 create_instruction_mov (ri, rn));
18134
18135 /* LDMDB Ri!, {R-high-register-list}. */
18136 current_stub_contents =
18137 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18138 create_instruction_ldmdb
18139 (ri, /*wback=*/1, insn_high_registers));
18140
18141 /* LDMDB Ri, {R-low-register-list}. */
18142 current_stub_contents =
18143 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18144 create_instruction_ldmdb
18145 (ri, /*wback=*/0, insn_low_registers));
18146
18147 /* B initial_insn_addr+4. */
18148 current_stub_contents =
18149 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18150 create_instruction_branch_absolute
82188b29 18151 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18152 }
18153 else if (wback && !restore_pc && !restore_rn)
18154 {
18155 /* LDMDB Rn!, {R-high-register-list}. */
18156 current_stub_contents =
18157 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18158 create_instruction_ldmdb
18159 (rn, /*wback=*/1, insn_high_registers));
18160
18161 /* LDMDB Rn!, {R-low-register-list}. */
18162 current_stub_contents =
18163 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18164 create_instruction_ldmdb
18165 (rn, /*wback=*/1, insn_low_registers));
18166
18167 /* B initial_insn_addr+4. */
18168 current_stub_contents =
18169 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18170 create_instruction_branch_absolute
82188b29 18171 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18172 }
18173 else if (!wback && restore_pc && !restore_rn)
18174 {
18175 /* Choose a Ri in the high-register-list that will be restored. */
18176 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18177
18178 /* SUB Ri, Rn, #(4*nb_registers). */
18179 current_stub_contents =
18180 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18181 create_instruction_sub (ri, rn, (4 * nb_registers)));
18182
18183 /* LDMIA Ri!, {R-low-register-list}. */
18184 current_stub_contents =
18185 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18186 create_instruction_ldmia
18187 (ri, /*wback=*/1, insn_low_registers));
18188
18189 /* LDMIA Ri, {R-high-register-list}. */
18190 current_stub_contents =
18191 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18192 create_instruction_ldmia
18193 (ri, /*wback=*/0, insn_high_registers));
18194 }
18195 else if (wback && restore_pc && !restore_rn)
18196 {
18197 /* Choose a Ri in the high-register-list that will be restored. */
18198 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18199
18200 /* SUB Rn, Rn, #(4*nb_registers) */
18201 current_stub_contents =
18202 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18203 create_instruction_sub (rn, rn, (4 * nb_registers)));
18204
18205 /* MOV Ri, Rn. */
18206 current_stub_contents =
18207 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18208 create_instruction_mov (ri, rn));
18209
18210 /* LDMIA Ri!, {R-low-register-list}. */
18211 current_stub_contents =
18212 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18213 create_instruction_ldmia
18214 (ri, /*wback=*/1, insn_low_registers));
18215
18216 /* LDMIA Ri, {R-high-register-list}. */
18217 current_stub_contents =
18218 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18219 create_instruction_ldmia
18220 (ri, /*wback=*/0, insn_high_registers));
18221 }
18222 else if (!wback && !restore_pc && restore_rn)
18223 {
18224 ri = rn;
18225 if (!(insn_low_registers & (1 << rn)))
18226 {
18227 /* Choose a Ri in the low-register-list that will be restored. */
18228 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18229
18230 /* MOV Ri, Rn. */
18231 current_stub_contents =
18232 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18233 create_instruction_mov (ri, rn));
18234 }
18235
18236 /* LDMDB Ri!, {R-high-register-list}. */
18237 current_stub_contents =
18238 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18239 create_instruction_ldmdb
18240 (ri, /*wback=*/1, insn_high_registers));
18241
18242 /* LDMDB Ri, {R-low-register-list}. */
18243 current_stub_contents =
18244 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18245 create_instruction_ldmdb
18246 (ri, /*wback=*/0, insn_low_registers));
18247
18248 /* B initial_insn_addr+4. */
18249 current_stub_contents =
18250 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18251 create_instruction_branch_absolute
82188b29 18252 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18253 }
18254 else if (!wback && restore_pc && restore_rn)
18255 {
18256 ri = rn;
18257 if (!(insn_high_registers & (1 << rn)))
18258 {
18259 /* Choose a Ri in the high-register-list that will be restored. */
18260 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18261 }
18262
18263 /* SUB Ri, Rn, #(4*nb_registers). */
18264 current_stub_contents =
18265 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18266 create_instruction_sub (ri, rn, (4 * nb_registers)));
18267
18268 /* LDMIA Ri!, {R-low-register-list}. */
18269 current_stub_contents =
18270 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18271 create_instruction_ldmia
18272 (ri, /*wback=*/1, insn_low_registers));
18273
18274 /* LDMIA Ri, {R-high-register-list}. */
18275 current_stub_contents =
18276 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18277 create_instruction_ldmia
18278 (ri, /*wback=*/0, insn_high_registers));
18279 }
18280 else if (wback && restore_rn)
18281 {
18282 /* The assembler should not have accepted to encode this. */
18283 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
18284 "undefined behavior.\n");
18285 }
18286
18287 /* Fill the remaining of the stub with deterministic contents. */
18288 current_stub_contents =
18289 stm32l4xx_fill_stub_udf (htab, output_bfd,
18290 base_stub_contents, current_stub_contents,
18291 base_stub_contents +
18292 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18293
18294}
18295
18296static void
18297stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
18298 bfd * output_bfd,
18299 const insn32 initial_insn,
18300 const bfd_byte *const initial_insn_addr,
18301 bfd_byte *const base_stub_contents)
18302{
9239bbd3 18303 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 18304 bfd_byte *current_stub_contents = base_stub_contents;
18305
18306 BFD_ASSERT (is_thumb2_vldm (initial_insn));
18307
18308 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 18309 smaller than 8 words load sequences that do not cause the
a504d23a 18310 hardware issue. */
9239bbd3 18311 if (num_words <= 8)
a504d23a
LA		 18312 {
18313 /* Untouched instruction. */
18314 current_stub_contents =
18315 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18316 initial_insn);
18317
18318 /* B initial_insn_addr+4. */
18319 current_stub_contents =
18320 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18321 create_instruction_branch_absolute
82188b29 18322 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18323 }
18324 else
18325 {
9eaff861 18326 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 18327 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 18328 bfd_boolean is_ia_nobang = /* (IA without !). */
18329 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
18330 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
18331 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
18332 bfd_boolean is_db_bang = /* (DB with !). */
18333 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 18334 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 18335 /* d = UInt (Vd:D);. */
9239bbd3 18336 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 18337 | (((unsigned int)initial_insn << 9) >> 31);
18338
9239bbd3
CM		 18339 /* Compute the number of 8-words chunks needed to split. */
18340 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 18341 int chunk;
18342
18343 /* The test coverage has been done assuming the following
18344 hypothesis that exactly one of the previous is_ predicates is
18345 true. */
9239bbd3
CM		 18346 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
18347 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 18348
9239bbd3 18349 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 18350 cases, then we emit the adjustments:
18351
18352 vldm rx, {...}
18353 -> vldm rx!, {8_words_or_less} for each needed 8_word
18354 -> sub rx, rx, #size (list)
18355
18356 vldm rx!, {...}
18357 -> vldm rx!, {8_words_or_less} for each needed 8_word
18358 This also handles vpop instruction (when rx is sp)
18359
18360 vldmd rx!, {...}
18361 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 18362 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 18363 {
9239bbd3
CM		 18364 bfd_vma new_insn = 0;
18365
a504d23a
LA		 18366 if (is_ia_nobang || is_ia_bang)
18367 {
9239bbd3
CM		 18368 new_insn = create_instruction_vldmia
18369 (base_reg,
18370 is_dp,
18371 /*wback= . */1,
18372 chunks - (chunk + 1) ?
18373 8 : num_words - chunk * 8,
18374 first_reg + chunk * 8);
a504d23a
LA		 18375 }
18376 else if (is_db_bang)
18377 {
9239bbd3
CM		 18378 new_insn = create_instruction_vldmdb
18379 (base_reg,
18380 is_dp,
18381 chunks - (chunk + 1) ?
18382 8 : num_words - chunk * 8,
18383 first_reg + chunk * 8);
a504d23a 18384 }
9239bbd3
CM		 18385
18386 if (new_insn)
18387 current_stub_contents =
18388 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18389 new_insn);
a504d23a
LA		 18390 }
18391
18392 /* Only this case requires the base register compensation
18393 subtract. */
18394 if (is_ia_nobang)
18395 {
18396 current_stub_contents =
18397 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18398 create_instruction_sub
9239bbd3 18399 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 18400 }
18401
18402 /* B initial_insn_addr+4. */
18403 current_stub_contents =
18404 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18405 create_instruction_branch_absolute
82188b29 18406 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18407 }
18408
18409 /* Fill the remaining of the stub with deterministic contents. */
18410 current_stub_contents =
18411 stm32l4xx_fill_stub_udf (htab, output_bfd,
18412 base_stub_contents, current_stub_contents,
18413 base_stub_contents +
18414 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
18415}
18416
18417static void
18418stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
18419 bfd * output_bfd,
18420 const insn32 wrong_insn,
18421 const bfd_byte *const wrong_insn_addr,
18422 bfd_byte *const stub_contents)
18423{
18424 if (is_thumb2_ldmia (wrong_insn))
18425 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
18426 wrong_insn, wrong_insn_addr,
18427 stub_contents);
18428 else if (is_thumb2_ldmdb (wrong_insn))
18429 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
18430 wrong_insn, wrong_insn_addr,
18431 stub_contents);
18432 else if (is_thumb2_vldm (wrong_insn))
18433 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
18434 wrong_insn, wrong_insn_addr,
18435 stub_contents);
18436}
18437
18438/* End of stm32l4xx work-around. */
18439
18440
e489d0ae
PB		 18441/* Do code byteswapping. Return FALSE afterwards so that the section is
18442 written out as normal. */
18443
18444static bfd_boolean
c7b8f16e 18445elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 18446 struct bfd_link_info *link_info,
18447 asection *sec,
e489d0ae
PB		 18448 bfd_byte *contents)
18449{
48229727 18450 unsigned int mapcount, errcount;
8e3de13a 18451 _arm_elf_section_data *arm_data;
c7b8f16e 18452 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 18453 elf32_arm_section_map *map;
c7b8f16e 18454 elf32_vfp11_erratum_list *errnode;
a504d23a 18455 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 18456 bfd_vma ptr;
18457 bfd_vma end;
c7b8f16e 18458 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 18459 bfd_byte tmp;
48229727 18460 unsigned int i;
57e8b36a 18461
4dfe6ac6
NC		 18462 if (globals == NULL)
18463 return FALSE;
18464
8e3de13a
NC		 18465 /* If this section has not been allocated an _arm_elf_section_data
18466 structure then we cannot record anything. */
18467 arm_data = get_arm_elf_section_data (sec);
18468 if (arm_data == NULL)
18469 return FALSE;
18470
18471 mapcount = arm_data->mapcount;
18472 map = arm_data->map;
c7b8f16e
JB		 18473 errcount = arm_data->erratumcount;
18474
18475 if (errcount != 0)
18476 {
18477 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
18478
18479 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 18480 errnode = errnode->next)
18481 {
18482 bfd_vma target = errnode->vma - offset;
18483
18484 switch (errnode->type)
18485 {
18486 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
18487 {
18488 bfd_vma branch_to_veneer;
18489 /* Original condition code of instruction, plus bit mask for
18490 ARM B instruction. */
18491 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
18492 | 0x0a000000;
c7b8f16e
JB		 18493
18494 /* The instruction is before the label. */
91d6fa6a 18495 target -= 4;
c7b8f16e
JB		 18496
18497 /* Above offset included in -4 below. */
18498 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 18499 - errnode->vma - 4;
c7b8f16e
JB		 18500
18501 if ((signed) branch_to_veneer < -(1 << 25)
18502 || (signed) branch_to_veneer >= (1 << 25))
18503 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
18504 "range"), output_bfd);
18505
99059e56
RM		 18506 insn |= (branch_to_veneer >> 2) & 0xffffff;
18507 contents[endianflip ^ target] = insn & 0xff;
18508 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18509 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18510 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18511 }
18512 break;
c7b8f16e
JB		 18513
18514 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 18515 {
18516 bfd_vma branch_from_veneer;
18517 unsigned int insn;
c7b8f16e 18518
99059e56
RM		 18519 /* Take size of veneer into account. */
18520 branch_from_veneer = errnode->u.v.branch->vma
18521 - errnode->vma - 12;
c7b8f16e
JB		 18522
18523 if ((signed) branch_from_veneer < -(1 << 25)
18524 || (signed) branch_from_veneer >= (1 << 25))
18525 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
18526 "range"), output_bfd);
18527
99059e56
RM		 18528 /* Original instruction. */
18529 insn = errnode->u.v.branch->u.b.vfp_insn;
18530 contents[endianflip ^ target] = insn & 0xff;
18531 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18532 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18533 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18534
18535 /* Branch back to insn after original insn. */
18536 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
18537 contents[endianflip ^ (target + 4)] = insn & 0xff;
18538 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
18539 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
18540 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
18541 }
18542 break;
c7b8f16e 18543
99059e56
RM		 18544 default:
18545 abort ();
18546 }
18547 }
c7b8f16e 18548 }
e489d0ae 18549
a504d23a
LA		 18550 if (arm_data->stm32l4xx_erratumcount != 0)
18551 {
18552 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
18553 stm32l4xx_errnode != 0;
18554 stm32l4xx_errnode = stm32l4xx_errnode->next)
18555 {
18556 bfd_vma target = stm32l4xx_errnode->vma - offset;
18557
18558 switch (stm32l4xx_errnode->type)
18559 {
18560 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
18561 {
18562 unsigned int insn;
18563 bfd_vma branch_to_veneer =
18564 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
18565
18566 if ((signed) branch_to_veneer < -(1 << 24)
18567 || (signed) branch_to_veneer >= (1 << 24))
18568 {
18569 bfd_vma out_of_range =
18570 ((signed) branch_to_veneer < -(1 << 24)) ?
18571 - branch_to_veneer - (1 << 24) :
18572 ((signed) branch_to_veneer >= (1 << 24)) ?
18573 branch_to_veneer - (1 << 24) : 0;
18574
18575 (*_bfd_error_handler)
18576 (_("%B(%#x): error: Cannot create STM32L4XX veneer. "
eee926f2 18577 "Jump out of range by %ld bytes. "
a504d23a
LA		 18578 "Cannot encode branch instruction. "),
18579 output_bfd,
eee926f2 18580 (long) (stm32l4xx_errnode->vma - 4),
a504d23a
LA		 18581 out_of_range);
18582 continue;
18583 }
18584
18585 insn = create_instruction_branch_absolute
82188b29 18586 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 18587
18588 /* The instruction is before the label. */
18589 target -= 4;
18590
18591 put_thumb2_insn (globals, output_bfd,
18592 (bfd_vma) insn, contents + target);
18593 }
18594 break;
18595
18596 case STM32L4XX_ERRATUM_VENEER:
18597 {
82188b29
NC		 18598 bfd_byte * veneer;
18599 bfd_byte * veneer_r;
a504d23a
LA		 18600 unsigned int insn;
18601
82188b29
NC		 18602 veneer = contents + target;
18603 veneer_r = veneer
18604 + stm32l4xx_errnode->u.b.veneer->vma
18605 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 18606
18607 if ((signed) (veneer_r - veneer -
18608 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
18609 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
18610 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
18611 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
18612 || (signed) (veneer_r - veneer) >= (1 << 24))
18613 {
18614 (*_bfd_error_handler) (_("%B: error: Cannot create STM32L4XX "
18615 "veneer."), output_bfd);
18616 continue;
18617 }
18618
18619 /* Original instruction. */
18620 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
18621
18622 stm32l4xx_create_replacing_stub
18623 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
18624 }
18625 break;
18626
18627 default:
18628 abort ();
18629 }
18630 }
18631 }
18632
2468f9c9
PB		 18633 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
18634 {
18635 arm_unwind_table_edit *edit_node
99059e56 18636 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 18637 /* Now, sec->size is the size of the section we will write. The original
99059e56 18638 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 18639 markers) was sec->rawsize. (This isn't the case if we perform no
18640 edits, then rawsize will be zero and we should use size). */
21d799b5 18641 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 18642 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
18643 unsigned int in_index, out_index;
18644 bfd_vma add_to_offsets = 0;
18645
18646 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 18647 {
2468f9c9
PB		 18648 if (edit_node)
18649 {
18650 unsigned int edit_index = edit_node->index;
b38cadfb 18651
2468f9c9 18652 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 18653 {
2468f9c9
PB		 18654 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18655 contents + in_index * 8, add_to_offsets);
18656 out_index++;
18657 in_index++;
18658 }
18659 else if (in_index == edit_index
18660 || (in_index * 8 >= input_size
18661 && edit_index == UINT_MAX))
99059e56 18662 {
2468f9c9
PB		 18663 switch (edit_node->type)
18664 {
18665 case DELETE_EXIDX_ENTRY:
18666 in_index++;
18667 add_to_offsets += 8;
18668 break;
b38cadfb 18669
2468f9c9
PB		 18670 case INSERT_EXIDX_CANTUNWIND_AT_END:
18671 {
99059e56 18672 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 18673 bfd_vma text_offset = text_sec->output_section->vma
18674 + text_sec->output_offset
18675 + text_sec->size;
18676 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 18677 unsigned long prel31_offset;
2468f9c9
PB		 18678
18679 /* Note: this is meant to be equivalent to an
18680 R_ARM_PREL31 relocation. These synthetic
18681 EXIDX_CANTUNWIND markers are not relocated by the
18682 usual BFD method. */
18683 prel31_offset = (text_offset - exidx_offset)
18684 & 0x7ffffffful;
491d01d3
YU		 18685 if (bfd_link_relocatable (link_info))
18686 {
18687 /* Here relocation for new EXIDX_CANTUNWIND is
18688 created, so there is no need to
18689 adjust offset by hand. */
18690 prel31_offset = text_sec->output_offset
18691 + text_sec->size;
491d01d3 18692 }
2468f9c9
PB		 18693
18694 /* First address we can't unwind. */
18695 bfd_put_32 (output_bfd, prel31_offset,
18696 &edited_contents[out_index * 8]);
18697
18698 /* Code for EXIDX_CANTUNWIND. */
18699 bfd_put_32 (output_bfd, 0x1,
18700 &edited_contents[out_index * 8 + 4]);
18701
18702 out_index++;
18703 add_to_offsets -= 8;
18704 }
18705 break;
18706 }
b38cadfb 18707
2468f9c9
PB		 18708 edit_node = edit_node->next;
18709 }
18710 }
18711 else
18712 {
18713 /* No more edits, copy remaining entries verbatim. */
18714 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18715 contents + in_index * 8, add_to_offsets);
18716 out_index++;
18717 in_index++;
18718 }
18719 }
18720
18721 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
18722 bfd_set_section_contents (output_bfd, sec->output_section,
18723 edited_contents,
18724 (file_ptr) sec->output_offset, sec->size);
18725
18726 return TRUE;
18727 }
18728
48229727
JB		 18729 /* Fix code to point to Cortex-A8 erratum stubs. */
18730 if (globals->fix_cortex_a8)
18731 {
18732 struct a8_branch_to_stub_data data;
18733
18734 data.writing_section = sec;
18735 data.contents = contents;
18736
a504d23a
LA		 18737 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
18738 & data);
48229727
JB		 18739 }
18740
e489d0ae
PB		 18741 if (mapcount == 0)
18742 return FALSE;
18743
c7b8f16e 18744 if (globals->byteswap_code)
e489d0ae 18745 {
c7b8f16e 18746 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 18747
c7b8f16e
JB		 18748 ptr = map[0].vma;
18749 for (i = 0; i < mapcount; i++)
99059e56
RM		 18750 {
18751 if (i == mapcount - 1)
c7b8f16e 18752 end = sec->size;
99059e56
RM		 18753 else
18754 end = map[i + 1].vma;
e489d0ae 18755
99059e56 18756 switch (map[i].type)
e489d0ae 18757 {
c7b8f16e
JB		 18758 case 'a':
18759 /* Byte swap code words. */
18760 while (ptr + 3 < end)
99059e56
RM		 18761 {
18762 tmp = contents[ptr];
18763 contents[ptr] = contents[ptr + 3];
18764 contents[ptr + 3] = tmp;
18765 tmp = contents[ptr + 1];
18766 contents[ptr + 1] = contents[ptr + 2];
18767 contents[ptr + 2] = tmp;
18768 ptr += 4;
18769 }
c7b8f16e 18770 break;
e489d0ae 18771
c7b8f16e
JB		 18772 case 't':
18773 /* Byte swap code halfwords. */
18774 while (ptr + 1 < end)
99059e56
RM		 18775 {
18776 tmp = contents[ptr];
18777 contents[ptr] = contents[ptr + 1];
18778 contents[ptr + 1] = tmp;
18779 ptr += 2;
18780 }
c7b8f16e
JB		 18781 break;
18782
18783 case 'd':
18784 /* Leave data alone. */
18785 break;
18786 }
99059e56
RM		 18787 ptr = end;
18788 }
e489d0ae 18789 }
8e3de13a 18790
93204d3a 18791 free (map);
47b2e99c 18792 arm_data->mapcount = -1;
c7b8f16e 18793 arm_data->mapsize = 0;
8e3de13a 18794 arm_data->map = NULL;
8e3de13a 18795
e489d0ae
PB		 18796 return FALSE;
18797}
18798
0beaef2b
PB		 18799/* Mangle thumb function symbols as we read them in. */
18800
8384fb8f 18801static bfd_boolean
0beaef2b
PB		 18802elf32_arm_swap_symbol_in (bfd * abfd,
18803 const void *psrc,
18804 const void *pshn,
18805 Elf_Internal_Sym *dst)
18806{
4ba2ef8f
TP		 18807 Elf_Internal_Shdr *symtab_hdr;
18808 const char *name = NULL;
18809
8384fb8f
AM		 18810 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
18811 return FALSE;
39d911fc 18812 dst->st_target_internal = 0;
0beaef2b
PB		 18813
18814 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 18815 the address. */
63e1a0fc
PB		 18816 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
18817 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 18818 {
63e1a0fc
PB		 18819 if (dst->st_value & 1)
18820 {
18821 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 18822 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
18823 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 18824 }
18825 else
39d911fc 18826 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 18827 }
18828 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
18829 {
18830 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 18831 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 18832 }
35fc36a8 18833 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 18834 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 18835 else
39d911fc 18836 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 18837
4ba2ef8f
TP		 18838 /* Mark CMSE special symbols. */
18839 symtab_hdr = & elf_symtab_hdr (abfd);
18840 if (symtab_hdr->sh_size)
18841 name = bfd_elf_sym_name (abfd, symtab_hdr, dst, NULL);
18842 if (name && CONST_STRNEQ (name, CMSE_PREFIX))
18843 ARM_SET_SYM_CMSE_SPCL (dst->st_target_internal);
18844
8384fb8f 18845 return TRUE;
0beaef2b
PB		 18846}
18847
18848
18849/* Mangle thumb function symbols as we write them out. */
18850
18851static void
18852elf32_arm_swap_symbol_out (bfd *abfd,
18853 const Elf_Internal_Sym *src,
18854 void *cdst,
18855 void *shndx)
18856{
18857 Elf_Internal_Sym newsym;
18858
18859 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
18860 of the address set, as per the new EABI. We do this unconditionally
18861 because objcopy does not set the elf header flags until after
18862 it writes out the symbol table. */
39d911fc 18863 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 18864 {
18865 newsym = *src;
34e77a92
RS		 18866 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
18867 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 18868 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 18869 {
18870 /* Do this only for defined symbols. At link type, the static
18871 linker will simulate the work of dynamic linker of resolving
18872 symbols and will carry over the thumbness of found symbols to
18873 the output symbol table. It's not clear how it happens, but
18874 the thumbness of undefined symbols can well be different at
18875 runtime, and writing '1' for them will be confusing for users
18876 and possibly for dynamic linker itself.
18877 */
18878 newsym.st_value |= 1;
18879 }
906e58ca 18880
0beaef2b
PB		 18881 src = &newsym;
18882 }
18883 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
18884}
18885
b294bdf8
MM		 18886/* Add the PT_ARM_EXIDX program header. */
18887
18888static bfd_boolean
906e58ca 18889elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 18890 struct bfd_link_info *info ATTRIBUTE_UNUSED)
18891{
18892 struct elf_segment_map *m;
18893 asection *sec;
18894
18895 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18896 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18897 {
18898 /* If there is already a PT_ARM_EXIDX header, then we do not
18899 want to add another one. This situation arises when running
18900 "strip"; the input binary already has the header. */
12bd6957 18901 m = elf_seg_map (abfd);
b294bdf8
MM		 18902 while (m && m->p_type != PT_ARM_EXIDX)
18903 m = m->next;
18904 if (!m)
18905 {
21d799b5 18906 m = (struct elf_segment_map *)
99059e56 18907 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 18908 if (m == NULL)
18909 return FALSE;
18910 m->p_type = PT_ARM_EXIDX;
18911 m->count = 1;
18912 m->sections[0] = sec;
18913
12bd6957
AM		 18914 m->next = elf_seg_map (abfd);
18915 elf_seg_map (abfd) = m;
b294bdf8
MM		 18916 }
18917 }
18918
18919 return TRUE;
18920}
18921
18922/* We may add a PT_ARM_EXIDX program header. */
18923
18924static int
a6b96beb
AM		 18925elf32_arm_additional_program_headers (bfd *abfd,
18926 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 18927{
18928 asection *sec;
18929
18930 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18931 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18932 return 1;
18933 else
18934 return 0;
18935}
18936
34e77a92
RS		 18937/* Hook called by the linker routine which adds symbols from an object
18938 file. */
18939
18940static bfd_boolean
18941elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
18942 Elf_Internal_Sym *sym, const char **namep,
18943 flagword *flagsp, asection **secp, bfd_vma *valp)
18944{
a43942db 18945 if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
f1885d1e
AM		 18946 && (abfd->flags & DYNAMIC) == 0
18947 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
a43942db 18948 elf_tdata (info->output_bfd)->has_gnu_symbols |= elf_gnu_symbol_ifunc;
34e77a92 18949
c792917c
NC		 18950 if (elf32_arm_hash_table (info) == NULL)
18951 return FALSE;
18952
34e77a92
RS		 18953 if (elf32_arm_hash_table (info)->vxworks_p
18954 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
18955 flagsp, secp, valp))
18956 return FALSE;
18957
18958 return TRUE;
18959}
18960
0beaef2b 18961/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 18962const struct elf_size_info elf32_arm_size_info =
18963{
0beaef2b
PB		 18964 sizeof (Elf32_External_Ehdr),
18965 sizeof (Elf32_External_Phdr),
18966 sizeof (Elf32_External_Shdr),
18967 sizeof (Elf32_External_Rel),
18968 sizeof (Elf32_External_Rela),
18969 sizeof (Elf32_External_Sym),
18970 sizeof (Elf32_External_Dyn),
18971 sizeof (Elf_External_Note),
18972 4,
18973 1,
18974 32, 2,
18975 ELFCLASS32, EV_CURRENT,
18976 bfd_elf32_write_out_phdrs,
18977 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 18978 bfd_elf32_checksum_contents,
0beaef2b
PB		 18979 bfd_elf32_write_relocs,
18980 elf32_arm_swap_symbol_in,
18981 elf32_arm_swap_symbol_out,
18982 bfd_elf32_slurp_reloc_table,
18983 bfd_elf32_slurp_symbol_table,
18984 bfd_elf32_swap_dyn_in,
18985 bfd_elf32_swap_dyn_out,
18986 bfd_elf32_swap_reloc_in,
18987 bfd_elf32_swap_reloc_out,
18988 bfd_elf32_swap_reloca_in,
18989 bfd_elf32_swap_reloca_out
18990};
18991
685e70ae
VK		 18992static bfd_vma
18993read_code32 (const bfd *abfd, const bfd_byte *addr)
18994{
18995 /* V7 BE8 code is always little endian. */
18996 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18997 return bfd_getl32 (addr);
18998
18999 return bfd_get_32 (abfd, addr);
19000}
19001
19002static bfd_vma
19003read_code16 (const bfd *abfd, const bfd_byte *addr)
19004{
19005 /* V7 BE8 code is always little endian. */
19006 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
19007 return bfd_getl16 (addr);
19008
19009 return bfd_get_16 (abfd, addr);
19010}
19011
6a631e86
YG		 19012/* Return size of plt0 entry starting at ADDR
19013 or (bfd_vma) -1 if size can not be determined. */
19014
19015static bfd_vma
19016elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
19017{
19018 bfd_vma first_word;
19019 bfd_vma plt0_size;
19020
685e70ae 19021 first_word = read_code32 (abfd, addr);
6a631e86
YG		 19022
19023 if (first_word == elf32_arm_plt0_entry[0])
19024 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
19025 else if (first_word == elf32_thumb2_plt0_entry[0])
19026 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
19027 else
19028 /* We don't yet handle this PLT format. */
19029 return (bfd_vma) -1;
19030
19031 return plt0_size;
19032}
19033
19034/* Return size of plt entry starting at offset OFFSET
19035 of plt section located at address START
19036 or (bfd_vma) -1 if size can not be determined. */
19037
19038static bfd_vma
19039elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
19040{
19041 bfd_vma first_insn;
19042 bfd_vma plt_size = 0;
19043 const bfd_byte *addr = start + offset;
19044
19045 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 19046 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 19047 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
19048
19049 /* Respect Thumb stub if necessary. */
685e70ae 19050 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 19051 {
19052 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
19053 }
19054
19055 /* Strip immediate from first add. */
685e70ae 19056 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 19057
19058#ifdef FOUR_WORD_PLT
19059 if (first_insn == elf32_arm_plt_entry[0])
19060 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
19061#else
19062 if (first_insn == elf32_arm_plt_entry_long[0])
19063 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
19064 else if (first_insn == elf32_arm_plt_entry_short[0])
19065 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
19066#endif
19067 else
19068 /* We don't yet handle this PLT format. */
19069 return (bfd_vma) -1;
19070
19071 return plt_size;
19072}
19073
19074/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
19075
19076static long
19077elf32_arm_get_synthetic_symtab (bfd *abfd,
19078 long symcount ATTRIBUTE_UNUSED,
19079 asymbol **syms ATTRIBUTE_UNUSED,
19080 long dynsymcount,
19081 asymbol **dynsyms,
19082 asymbol **ret)
19083{
19084 asection *relplt;
19085 asymbol *s;
19086 arelent *p;
19087 long count, i, n;
19088 size_t size;
19089 Elf_Internal_Shdr *hdr;
19090 char *names;
19091 asection *plt;
19092 bfd_vma offset;
19093 bfd_byte *data;
19094
19095 *ret = NULL;
19096
19097 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
19098 return 0;
19099
19100 if (dynsymcount <= 0)
19101 return 0;
19102
19103 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
19104 if (relplt == NULL)
19105 return 0;
19106
19107 hdr = &elf_section_data (relplt)->this_hdr;
19108 if (hdr->sh_link != elf_dynsymtab (abfd)
19109 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
19110 return 0;
19111
19112 plt = bfd_get_section_by_name (abfd, ".plt");
19113 if (plt == NULL)
19114 return 0;
19115
19116 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
19117 return -1;
19118
19119 data = plt->contents;
19120 if (data == NULL)
19121 {
19122 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
19123 return -1;
19124 bfd_cache_section_contents((asection *) plt, data);
19125 }
19126
19127 count = relplt->size / hdr->sh_entsize;
19128 size = count * sizeof (asymbol);
19129 p = relplt->relocation;
19130 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19131 {
19132 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
19133 if (p->addend != 0)
19134 size += sizeof ("+0x") - 1 + 8;
19135 }
19136
19137 s = *ret = (asymbol *) bfd_malloc (size);
19138 if (s == NULL)
19139 return -1;
19140
19141 offset = elf32_arm_plt0_size (abfd, data);
19142 if (offset == (bfd_vma) -1)
19143 return -1;
19144
19145 names = (char *) (s + count);
19146 p = relplt->relocation;
19147 n = 0;
19148 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19149 {
19150 size_t len;
19151
19152 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
19153 if (plt_size == (bfd_vma) -1)
19154 break;
19155
19156 *s = **p->sym_ptr_ptr;
19157 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
19158 we are defining a symbol, ensure one of them is set. */
19159 if ((s->flags & BSF_LOCAL) == 0)
19160 s->flags |= BSF_GLOBAL;
19161 s->flags |= BSF_SYNTHETIC;
19162 s->section = plt;
19163 s->value = offset;
19164 s->name = names;
19165 s->udata.p = NULL;
19166 len = strlen ((*p->sym_ptr_ptr)->name);
19167 memcpy (names, (*p->sym_ptr_ptr)->name, len);
19168 names += len;
19169 if (p->addend != 0)
19170 {
19171 char buf[30], *a;
19172
19173 memcpy (names, "+0x", sizeof ("+0x") - 1);
19174 names += sizeof ("+0x") - 1;
19175 bfd_sprintf_vma (abfd, buf, p->addend);
19176 for (a = buf; *a == '0'; ++a)
19177 ;
19178 len = strlen (a);
19179 memcpy (names, a, len);
19180 names += len;
19181 }
19182 memcpy (names, "@plt", sizeof ("@plt"));
19183 names += sizeof ("@plt");
19184 ++s, ++n;
19185 offset += plt_size;
19186 }
19187
19188 return n;
19189}
19190
ac4c9b04
MG		 19191static bfd_boolean
19192elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
19193{
f0728ee3
AV		 19194 if (hdr->sh_flags & SHF_ARM_PURECODE)
19195 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 19196 return TRUE;
19197}
19198
19199static flagword
19200elf32_arm_lookup_section_flags (char *flag_name)
19201{
f0728ee3
AV		 19202 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
19203 return SHF_ARM_PURECODE;
ac4c9b04
MG		 19204
19205 return SEC_NO_FLAGS;
19206}
19207
491d01d3
YU		 19208static unsigned int
19209elf32_arm_count_additional_relocs (asection *sec)
19210{
19211 struct _arm_elf_section_data *arm_data;
19212 arm_data = get_arm_elf_section_data (sec);
5025eb7c 19213
6342be70 19214 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 19215}
19216
5522f910 19217/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 19218 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 19219 FALSE otherwise. ISECTION is the best guess matching section from the
19220 input bfd IBFD, but it might be NULL. */
19221
19222static bfd_boolean
19223elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
19224 bfd *obfd ATTRIBUTE_UNUSED,
19225 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
19226 Elf_Internal_Shdr *osection)
19227{
19228 switch (osection->sh_type)
19229 {
19230 case SHT_ARM_EXIDX:
19231 {
19232 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
19233 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
19234 unsigned i = 0;
19235
19236 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
19237 osection->sh_info = 0;
19238
19239 /* The sh_link field must be set to the text section associated with
19240 this index section. Unfortunately the ARM EHABI does not specify
19241 exactly how to determine this association. Our caller does try
19242 to match up OSECTION with its corresponding input section however
19243 so that is a good first guess. */
19244 if (isection != NULL
19245 && osection->bfd_section != NULL
19246 && isection->bfd_section != NULL
19247 && isection->bfd_section->output_section != NULL
19248 && isection->bfd_section->output_section == osection->bfd_section
19249 && iheaders != NULL
19250 && isection->sh_link > 0
19251 && isection->sh_link < elf_numsections (ibfd)
19252 && iheaders[isection->sh_link]->bfd_section != NULL
19253 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
19254 )
19255 {
19256 for (i = elf_numsections (obfd); i-- > 0;)
19257 if (oheaders[i]->bfd_section
19258 == iheaders[isection->sh_link]->bfd_section->output_section)
19259 break;
19260 }
9eaff861 19261
5522f910
NC		 19262 if (i == 0)
19263 {
19264 /* Failing that we have to find a matching section ourselves. If
19265 we had the output section name available we could compare that
19266 with input section names. Unfortunately we don't. So instead
19267 we use a simple heuristic and look for the nearest executable
19268 section before this one. */
19269 for (i = elf_numsections (obfd); i-- > 0;)
19270 if (oheaders[i] == osection)
19271 break;
19272 if (i == 0)
19273 break;
19274
19275 while (i-- > 0)
19276 if (oheaders[i]->sh_type == SHT_PROGBITS
19277 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
19278 == (SHF_ALLOC | SHF_EXECINSTR))
19279 break;
19280 }
19281
19282 if (i)
19283 {
19284 osection->sh_link = i;
19285 /* If the text section was part of a group
19286 then the index section should be too. */
19287 if (oheaders[i]->sh_flags & SHF_GROUP)
19288 osection->sh_flags |= SHF_GROUP;
19289 return TRUE;
19290 }
19291 }
19292 break;
19293
19294 case SHT_ARM_PREEMPTMAP:
19295 osection->sh_flags = SHF_ALLOC;
19296 break;
19297
19298 case SHT_ARM_ATTRIBUTES:
19299 case SHT_ARM_DEBUGOVERLAY:
19300 case SHT_ARM_OVERLAYSECTION:
19301 default:
19302 break;
19303 }
19304
19305 return FALSE;
19306}
19307
d691934d
NC		 19308/* Returns TRUE if NAME is an ARM mapping symbol.
19309 Traditionally the symbols $a, $d and $t have been used.
19310 The ARM ELF standard also defines $x (for A64 code). It also allows a
19311 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
19312 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
19313 not support them here. $t.x indicates the start of ThumbEE instructions. */
19314
19315static bfd_boolean
19316is_arm_mapping_symbol (const char * name)
19317{
19318 return name != NULL /* Paranoia. */
19319 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
19320 the mapping symbols could have acquired a prefix.
19321 We do not support this here, since such symbols no
19322 longer conform to the ARM ELF ABI. */
19323 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
19324 && (name[2] == 0 || name[2] == '.');
19325 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
19326 any characters that follow the period are legal characters for the body
19327 of a symbol's name. For now we just assume that this is the case. */
19328}
19329
fca2a38f
NC		 19330/* Make sure that mapping symbols in object files are not removed via the
19331 "strip --strip-unneeded" tool. These symbols are needed in order to
19332 correctly generate interworking veneers, and for byte swapping code
19333 regions. Once an object file has been linked, it is safe to remove the
19334 symbols as they will no longer be needed. */
19335
19336static void
19337elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
19338{
19339 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 19340 && sym->section != bfd_abs_section_ptr
d691934d 19341 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 19342 sym->flags |= BSF_KEEP;
19343}
19344
5522f910
NC		 19345#undef elf_backend_copy_special_section_fields
19346#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
19347
252b5132 19348#define ELF_ARCH bfd_arch_arm
ae95ffa6 19349#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 19350#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 19351#ifdef __QNXTARGET__
19352#define ELF_MAXPAGESIZE 0x1000
19353#else
7572ca89 19354#define ELF_MAXPAGESIZE 0x10000
d0facd1b 19355#endif
b1342370 19356#define ELF_MINPAGESIZE 0x1000
24718e3b 19357#define ELF_COMMONPAGESIZE 0x1000
252b5132 19358
ba93b8ac
DJ		 19359#define bfd_elf32_mkobject elf32_arm_mkobject
19360
99e4ae17
AJ		 19361#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
19362#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 19363#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
19364#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
19365#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 19366#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 19367#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
252b5132 19368#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
4ab527b0 19369#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 19370#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 19371#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 19372#define bfd_elf32_bfd_final_link elf32_arm_final_link
6a631e86 19373#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132
RH		 19374
19375#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
19376#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 19377#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
252b5132
RH		 19378#define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
19379#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 19380#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 19381#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 19382#define elf_backend_write_section elf32_arm_write_section
252b5132 19383#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
5e681ec4 19384#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 19385#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
19386#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
19387#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 19388#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 19389#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 19390#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 19391#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 19392#define elf_backend_object_p elf32_arm_object_p
40a18ebd
NC		 19393#define elf_backend_fake_sections elf32_arm_fake_sections
19394#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
e16bb312 19395#define elf_backend_final_write_processing elf32_arm_final_write_processing
5e681ec4 19396#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 19397#define elf_backend_size_info elf32_arm_size_info
b294bdf8 19398#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
906e58ca
NC		 19399#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
19400#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 19401#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
906e58ca 19402#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 19403#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 19404#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 19405#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 19406
19407#define elf_backend_can_refcount 1
19408#define elf_backend_can_gc_sections 1
19409#define elf_backend_plt_readonly 1
19410#define elf_backend_want_got_plt 1
19411#define elf_backend_want_plt_sym 0
19412#define elf_backend_may_use_rel_p 1
19413#define elf_backend_may_use_rela_p 0
4e7fd91e 19414#define elf_backend_default_use_rela_p 0
252b5132 19415
04f7c78d 19416#define elf_backend_got_header_size 12
b68a20d6 19417#define elf_backend_extern_protected_data 1
04f7c78d 19418
906e58ca
NC		 19419#undef elf_backend_obj_attrs_vendor
19420#define elf_backend_obj_attrs_vendor "aeabi"
19421#undef elf_backend_obj_attrs_section
19422#define elf_backend_obj_attrs_section ".ARM.attributes"
19423#undef elf_backend_obj_attrs_arg_type
19424#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
19425#undef elf_backend_obj_attrs_section_type
104d59d1 19426#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb
NC		 19427#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
19428#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 19429
5025eb7c 19430#undef elf_backend_section_flags
ac4c9b04 19431#define elf_backend_section_flags elf32_arm_section_flags
5025eb7c 19432#undef elf_backend_lookup_section_flags_hook
ac4c9b04
MG		 19433#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
19434
252b5132 19435#include "elf32-target.h"
7f266840 19436
b38cadfb
NC		 19437/* Native Client targets. */
19438
19439#undef TARGET_LITTLE_SYM
6d00b590 19440#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 19441#undef TARGET_LITTLE_NAME
19442#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
19443#undef TARGET_BIG_SYM
6d00b590 19444#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 19445#undef TARGET_BIG_NAME
19446#define TARGET_BIG_NAME "elf32-bigarm-nacl"
19447
19448/* Like elf32_arm_link_hash_table_create -- but overrides
19449 appropriately for NaCl. */
19450
19451static struct bfd_link_hash_table *
19452elf32_arm_nacl_link_hash_table_create (bfd *abfd)
19453{
19454 struct bfd_link_hash_table *ret;
19455
19456 ret = elf32_arm_link_hash_table_create (abfd);
19457 if (ret)
19458 {
19459 struct elf32_arm_link_hash_table *htab
19460 = (struct elf32_arm_link_hash_table *) ret;
19461
19462 htab->nacl_p = 1;
19463
19464 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
19465 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
19466 }
19467 return ret;
19468}
19469
19470/* Since NaCl doesn't use the ARM-specific unwind format, we don't
19471 really need to use elf32_arm_modify_segment_map. But we do it
19472 anyway just to reduce gratuitous differences with the stock ARM backend. */
19473
19474static bfd_boolean
19475elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
19476{
19477 return (elf32_arm_modify_segment_map (abfd, info)
19478 && nacl_modify_segment_map (abfd, info));
19479}
19480
887badb3
RM		 19481static void
19482elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
19483{
19484 elf32_arm_final_write_processing (abfd, linker);
19485 nacl_final_write_processing (abfd, linker);
19486}
19487
6a631e86
YG		 19488static bfd_vma
19489elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
19490 const arelent *rel ATTRIBUTE_UNUSED)
19491{
19492 return plt->vma
19493 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
19494 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
19495}
887badb3 19496
b38cadfb 19497#undef elf32_bed
6a631e86 19498#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 19499#undef bfd_elf32_bfd_link_hash_table_create
19500#define bfd_elf32_bfd_link_hash_table_create \
19501 elf32_arm_nacl_link_hash_table_create
19502#undef elf_backend_plt_alignment
6a631e86 19503#define elf_backend_plt_alignment 4
b38cadfb
NC		 19504#undef elf_backend_modify_segment_map
19505#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
19506#undef elf_backend_modify_program_headers
19507#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 19508#undef elf_backend_final_write_processing
19509#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 19510#undef bfd_elf32_get_synthetic_symtab
19511#undef elf_backend_plt_sym_val
19512#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 19513#undef elf_backend_copy_special_section_fields
b38cadfb 19514
887badb3
RM		 19515#undef ELF_MINPAGESIZE
19516#undef ELF_COMMONPAGESIZE
19517
b38cadfb
NC		 19518
19519#include "elf32-target.h"
19520
19521/* Reset to defaults. */
19522#undef elf_backend_plt_alignment
19523#undef elf_backend_modify_segment_map
19524#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
19525#undef elf_backend_modify_program_headers
887badb3
RM		 19526#undef elf_backend_final_write_processing
19527#define elf_backend_final_write_processing elf32_arm_final_write_processing
19528#undef ELF_MINPAGESIZE
19529#define ELF_MINPAGESIZE 0x1000
19530#undef ELF_COMMONPAGESIZE
19531#define ELF_COMMONPAGESIZE 0x1000
19532
b38cadfb 19533
906e58ca 19534/* VxWorks Targets. */
4e7fd91e 19535
906e58ca 19536#undef TARGET_LITTLE_SYM
6d00b590 19537#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
906e58ca 19538#undef TARGET_LITTLE_NAME
4e7fd91e 19539#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
906e58ca 19540#undef TARGET_BIG_SYM
6d00b590 19541#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
906e58ca 19542#undef TARGET_BIG_NAME
4e7fd91e
PB		 19543#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
19544
19545/* Like elf32_arm_link_hash_table_create -- but overrides
19546 appropriately for VxWorks. */
906e58ca 19547
4e7fd91e
PB		 19548static struct bfd_link_hash_table *
19549elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
19550{
19551 struct bfd_link_hash_table *ret;
19552
19553 ret = elf32_arm_link_hash_table_create (abfd);
19554 if (ret)
19555 {
19556 struct elf32_arm_link_hash_table *htab
00a97672 19557 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 19558 htab->use_rel = 0;
00a97672 19559 htab->vxworks_p = 1;
4e7fd91e
PB		 19560 }
19561 return ret;
906e58ca 19562}
4e7fd91e 19563
00a97672
RS		 19564static void
19565elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
19566{
19567 elf32_arm_final_write_processing (abfd, linker);
19568 elf_vxworks_final_write_processing (abfd, linker);
19569}
19570
906e58ca 19571#undef elf32_bed
4e7fd91e
PB		 19572#define elf32_bed elf32_arm_vxworks_bed
19573
906e58ca
NC		 19574#undef bfd_elf32_bfd_link_hash_table_create
19575#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 19576#undef elf_backend_final_write_processing
19577#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
19578#undef elf_backend_emit_relocs
9eaff861 19579#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 19580
906e58ca 19581#undef elf_backend_may_use_rel_p
00a97672 19582#define elf_backend_may_use_rel_p 0
906e58ca 19583#undef elf_backend_may_use_rela_p
00a97672 19584#define elf_backend_may_use_rela_p 1
906e58ca 19585#undef elf_backend_default_use_rela_p
00a97672 19586#define elf_backend_default_use_rela_p 1
906e58ca 19587#undef elf_backend_want_plt_sym
00a97672 19588#define elf_backend_want_plt_sym 1
906e58ca 19589#undef ELF_MAXPAGESIZE
00a97672 19590#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 19591
19592#include "elf32-target.h"
19593
19594
21d799b5
NC		 19595/* Merge backend specific data from an object file to the output
19596 object file when linking. */
19597
19598static bfd_boolean
19599elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
19600{
19601 flagword out_flags;
19602 flagword in_flags;
19603 bfd_boolean flags_compatible = TRUE;
19604 asection *sec;
19605
cc643b88 19606 /* Check if we have the same endianness. */
21d799b5
NC		 19607 if (! _bfd_generic_verify_endian_match (ibfd, obfd))
19608 return FALSE;
19609
19610 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
19611 return TRUE;
19612
19613 if (!elf32_arm_merge_eabi_attributes (ibfd, obfd))
19614 return FALSE;
19615
19616 /* The input BFD must have had its flags initialised. */
19617 /* The following seems bogus to me -- The flags are initialized in
19618 the assembler but I don't think an elf_flags_init field is
19619 written into the object. */
19620 /* BFD_ASSERT (elf_flags_init (ibfd)); */
19621
19622 in_flags = elf_elfheader (ibfd)->e_flags;
19623 out_flags = elf_elfheader (obfd)->e_flags;
19624
19625 /* In theory there is no reason why we couldn't handle this. However
19626 in practice it isn't even close to working and there is no real
19627 reason to want it. */
19628 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
19629 && !(ibfd->flags & DYNAMIC)
19630 && (in_flags & EF_ARM_BE8))
19631 {
19632 _bfd_error_handler (_("error: %B is already in final BE8 format"),
19633 ibfd);
19634 return FALSE;
19635 }
19636
19637 if (!elf_flags_init (obfd))
19638 {
19639 /* If the input is the default architecture and had the default
19640 flags then do not bother setting the flags for the output
19641 architecture, instead allow future merges to do this. If no
19642 future merges ever set these flags then they will retain their
99059e56
RM		 19643 uninitialised values, which surprise surprise, correspond
19644 to the default values. */
21d799b5
NC		 19645 if (bfd_get_arch_info (ibfd)->the_default
19646 && elf_elfheader (ibfd)->e_flags == 0)
19647 return TRUE;
19648
19649 elf_flags_init (obfd) = TRUE;
19650 elf_elfheader (obfd)->e_flags = in_flags;
19651
19652 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
19653 && bfd_get_arch_info (obfd)->the_default)
19654 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
19655
19656 return TRUE;
19657 }
19658
19659 /* Determine what should happen if the input ARM architecture
19660 does not match the output ARM architecture. */
19661 if (! bfd_arm_merge_machines (ibfd, obfd))
19662 return FALSE;
19663
19664 /* Identical flags must be compatible. */
19665 if (in_flags == out_flags)
19666 return TRUE;
19667
19668 /* Check to see if the input BFD actually contains any sections. If
19669 not, its flags may not have been initialised either, but it
19670 cannot actually cause any incompatiblity. Do not short-circuit
19671 dynamic objects; their section list may be emptied by
19672 elf_link_add_object_symbols.
19673
19674 Also check to see if there are no code sections in the input.
19675 In this case there is no need to check for code specific flags.
19676 XXX - do we need to worry about floating-point format compatability
19677 in data sections ? */
19678 if (!(ibfd->flags & DYNAMIC))
19679 {
19680 bfd_boolean null_input_bfd = TRUE;
19681 bfd_boolean only_data_sections = TRUE;
19682
19683 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
19684 {
19685 /* Ignore synthetic glue sections. */
19686 if (strcmp (sec->name, ".glue_7")
19687 && strcmp (sec->name, ".glue_7t"))
19688 {
19689 if ((bfd_get_section_flags (ibfd, sec)
19690 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
19691 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 19692 only_data_sections = FALSE;
21d799b5
NC		 19693
19694 null_input_bfd = FALSE;
19695 break;
19696 }
19697 }
19698
19699 if (null_input_bfd || only_data_sections)
19700 return TRUE;
19701 }
19702
19703 /* Complain about various flag mismatches. */
19704 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
19705 EF_ARM_EABI_VERSION (out_flags)))
19706 {
19707 _bfd_error_handler
19708 (_("error: Source object %B has EABI version %d, but target %B has EABI version %d"),
19709 ibfd, obfd,
19710 (in_flags & EF_ARM_EABIMASK) >> 24,
19711 (out_flags & EF_ARM_EABIMASK) >> 24);
19712 return FALSE;
19713 }
19714
19715 /* Not sure what needs to be checked for EABI versions >= 1. */
19716 /* VxWorks libraries do not use these flags. */
19717 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
19718 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
19719 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
19720 {
19721 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
19722 {
19723 _bfd_error_handler
19724 (_("error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"),
19725 ibfd, obfd,
19726 in_flags & EF_ARM_APCS_26 ? 26 : 32,
19727 out_flags & EF_ARM_APCS_26 ? 26 : 32);
19728 flags_compatible = FALSE;
19729 }
19730
19731 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
19732 {
19733 if (in_flags & EF_ARM_APCS_FLOAT)
19734 _bfd_error_handler
19735 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
19736 ibfd, obfd);
19737 else
19738 _bfd_error_handler
19739 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
19740 ibfd, obfd);
19741
19742 flags_compatible = FALSE;
19743 }
19744
19745 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
19746 {
19747 if (in_flags & EF_ARM_VFP_FLOAT)
19748 _bfd_error_handler
19749 (_("error: %B uses VFP instructions, whereas %B does not"),
19750 ibfd, obfd);
19751 else
19752 _bfd_error_handler
19753 (_("error: %B uses FPA instructions, whereas %B does not"),
19754 ibfd, obfd);
19755
19756 flags_compatible = FALSE;
19757 }
19758
19759 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
19760 {
19761 if (in_flags & EF_ARM_MAVERICK_FLOAT)
19762 _bfd_error_handler
19763 (_("error: %B uses Maverick instructions, whereas %B does not"),
19764 ibfd, obfd);
19765 else
19766 _bfd_error_handler
19767 (_("error: %B does not use Maverick instructions, whereas %B does"),
19768 ibfd, obfd);
19769
19770 flags_compatible = FALSE;
19771 }
19772
19773#ifdef EF_ARM_SOFT_FLOAT
19774 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
19775 {
19776 /* We can allow interworking between code that is VFP format
19777 layout, and uses either soft float or integer regs for
19778 passing floating point arguments and results. We already
19779 know that the APCS_FLOAT flags match; similarly for VFP
19780 flags. */
19781 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
19782 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
19783 {
19784 if (in_flags & EF_ARM_SOFT_FLOAT)
19785 _bfd_error_handler
19786 (_("error: %B uses software FP, whereas %B uses hardware FP"),
19787 ibfd, obfd);
19788 else
19789 _bfd_error_handler
19790 (_("error: %B uses hardware FP, whereas %B uses software FP"),
19791 ibfd, obfd);
19792
19793 flags_compatible = FALSE;
19794 }
19795 }
19796#endif
19797
19798 /* Interworking mismatch is only a warning. */
19799 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
19800 {
19801 if (in_flags & EF_ARM_INTERWORK)
19802 {
19803 _bfd_error_handler
19804 (_("Warning: %B supports interworking, whereas %B does not"),
19805 ibfd, obfd);
19806 }
19807 else
19808 {
19809 _bfd_error_handler
19810 (_("Warning: %B does not support interworking, whereas %B does"),
19811 ibfd, obfd);
19812 }
19813 }
19814 }
19815
19816 return flags_compatible;
19817}
19818
19819
906e58ca 19820/* Symbian OS Targets. */
7f266840 19821
906e58ca 19822#undef TARGET_LITTLE_SYM
6d00b590 19823#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
906e58ca 19824#undef TARGET_LITTLE_NAME
7f266840 19825#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
906e58ca 19826#undef TARGET_BIG_SYM
6d00b590 19827#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
906e58ca 19828#undef TARGET_BIG_NAME
7f266840
DJ		 19829#define TARGET_BIG_NAME "elf32-bigarm-symbian"
19830
19831/* Like elf32_arm_link_hash_table_create -- but overrides
19832 appropriately for Symbian OS. */
906e58ca 19833
7f266840
DJ		 19834static struct bfd_link_hash_table *
19835elf32_arm_symbian_link_hash_table_create (bfd *abfd)
19836{
19837 struct bfd_link_hash_table *ret;
19838
19839 ret = elf32_arm_link_hash_table_create (abfd);
19840 if (ret)
19841 {
19842 struct elf32_arm_link_hash_table *htab
19843 = (struct elf32_arm_link_hash_table *)ret;
19844 /* There is no PLT header for Symbian OS. */
19845 htab->plt_header_size = 0;
95720a86
DJ		 19846 /* The PLT entries are each one instruction and one word. */
19847 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 19848 htab->symbian_p = 1;
33bfe774
JB		 19849 /* Symbian uses armv5t or above, so use_blx is always true. */
19850 htab->use_blx = 1;
67687978 19851 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 19852 }
19853 return ret;
906e58ca 19854}
7f266840 19855
b35d266b 19856static const struct bfd_elf_special_section
551b43fd 19857elf32_arm_symbian_special_sections[] =
7f266840 19858{
5cd3778d
MM		 19859 /* In a BPABI executable, the dynamic linking sections do not go in
19860 the loadable read-only segment. The post-linker may wish to
19861 refer to these sections, but they are not part of the final
19862 program image. */
0112cd26
NC		 19863 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
19864 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
19865 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
19866 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
19867 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 19868 /* These sections do not need to be writable as the SymbianOS
19869 postlinker will arrange things so that no dynamic relocation is
19870 required. */
0112cd26
NC		 19871 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
19872 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
19873 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
19874 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 19875};
19876
c3c76620 19877static void
906e58ca 19878elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 19879 struct bfd_link_info *link_info)
c3c76620
MM		 19880{
19881 /* BPABI objects are never loaded directly by an OS kernel; they are
19882 processed by a postlinker first, into an OS-specific format. If
19883 the D_PAGED bit is set on the file, BFD will align segments on
19884 page boundaries, so that an OS can directly map the file. With
19885 BPABI objects, that just results in wasted space. In addition,
19886 because we clear the D_PAGED bit, map_sections_to_segments will
19887 recognize that the program headers should not be mapped into any
19888 loadable segment. */
19889 abfd->flags &= ~D_PAGED;
906e58ca 19890 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 19891}
7f266840
DJ		 19892
19893static bfd_boolean
906e58ca 19894elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 19895 struct bfd_link_info *info)
7f266840
DJ		 19896{
19897 struct elf_segment_map *m;
19898 asection *dynsec;
19899
7f266840
DJ		 19900 /* BPABI shared libraries and executables should have a PT_DYNAMIC
19901 segment. However, because the .dynamic section is not marked
19902 with SEC_LOAD, the generic ELF code will not create such a
19903 segment. */
19904 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
19905 if (dynsec)
19906 {
12bd6957 19907 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 19908 if (m->p_type == PT_DYNAMIC)
19909 break;
19910
19911 if (m == NULL)
19912 {
19913 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 19914 m->next = elf_seg_map (abfd);
19915 elf_seg_map (abfd) = m;
8ded5a0f 19916 }
7f266840
DJ		 19917 }
19918
b294bdf8
MM		 19919 /* Also call the generic arm routine. */
19920 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 19921}
19922
95720a86
DJ		 19923/* Return address for Ith PLT stub in section PLT, for relocation REL
19924 or (bfd_vma) -1 if it should not be included. */
19925
19926static bfd_vma
19927elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
19928 const arelent *rel ATTRIBUTE_UNUSED)
19929{
19930 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
19931}
19932
8029a119 19933#undef elf32_bed
7f266840
DJ		 19934#define elf32_bed elf32_arm_symbian_bed
19935
19936/* The dynamic sections are not allocated on SymbianOS; the postlinker
19937 will process them and then discard them. */
906e58ca 19938#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 19939#define ELF_DYNAMIC_SEC_FLAGS \
19940 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
19941
9eaff861 19942#undef elf_backend_emit_relocs
c3c76620 19943
906e58ca
NC		 19944#undef bfd_elf32_bfd_link_hash_table_create
19945#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
19946#undef elf_backend_special_sections
19947#define elf_backend_special_sections elf32_arm_symbian_special_sections
19948#undef elf_backend_begin_write_processing
19949#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
19950#undef elf_backend_final_write_processing
19951#define elf_backend_final_write_processing elf32_arm_final_write_processing
19952
19953#undef elf_backend_modify_segment_map
7f266840
DJ		 19954#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
19955
19956/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 19957#undef elf_backend_got_header_size
7f266840
DJ		 19958#define elf_backend_got_header_size 0
19959
19960/* Similarly, there is no .got.plt section. */
906e58ca 19961#undef elf_backend_want_got_plt
7f266840
DJ		 19962#define elf_backend_want_got_plt 0
19963
906e58ca 19964#undef elf_backend_plt_sym_val
95720a86
DJ		 19965#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
19966
906e58ca 19967#undef elf_backend_may_use_rel_p
00a97672 19968#define elf_backend_may_use_rel_p 1
906e58ca 19969#undef elf_backend_may_use_rela_p
00a97672 19970#define elf_backend_may_use_rela_p 0
906e58ca 19971#undef elf_backend_default_use_rela_p
00a97672 19972#define elf_backend_default_use_rela_p 0
906e58ca 19973#undef elf_backend_want_plt_sym
00a97672 19974#define elf_backend_want_plt_sym 0
906e58ca 19975#undef ELF_MAXPAGESIZE
00a97672 19976#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 19977
7f266840 19978#include "elf32-target.h"
GDB Binutils - Deliverables
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