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Add support for non-contiguous memory regions
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
b3adc24a 2 Copyright (C) 1998-2020 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
00a97672 25#include "libiberty.h"
7f266840
DJ		 26#include "libbfd.h"
27#include "elf-bfd.h"
b38cadfb 28#include "elf-nacl.h"
00a97672 29#include "elf-vxworks.h"
ee065d83 30#include "elf/arm.h"
f37164d7
AM		 31#include "elf32-arm.h"
32#include "cpu-arm.h"
7f266840 33
00a97672
RS		 34/* Return the relocation section associated with NAME. HTAB is the
35 bfd's elf32_arm_link_hash_entry. */
36#define RELOC_SECTION(HTAB, NAME) \
37 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
38
39/* Return size of a relocation entry. HTAB is the bfd's
40 elf32_arm_link_hash_entry. */
41#define RELOC_SIZE(HTAB) \
42 ((HTAB)->use_rel \
43 ? sizeof (Elf32_External_Rel) \
44 : sizeof (Elf32_External_Rela))
45
46/* Return function to swap relocations in. HTAB is the bfd's
47 elf32_arm_link_hash_entry. */
48#define SWAP_RELOC_IN(HTAB) \
49 ((HTAB)->use_rel \
50 ? bfd_elf32_swap_reloc_in \
51 : bfd_elf32_swap_reloca_in)
52
53/* Return function to swap relocations out. HTAB is the bfd's
54 elf32_arm_link_hash_entry. */
55#define SWAP_RELOC_OUT(HTAB) \
56 ((HTAB)->use_rel \
57 ? bfd_elf32_swap_reloc_out \
58 : bfd_elf32_swap_reloca_out)
59
f3185997 60#define elf_info_to_howto NULL
07d6d2b8 61#define elf_info_to_howto_rel elf32_arm_info_to_howto
7f266840
DJ		 62
63#define ARM_ELF_ABI_VERSION 0
64#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
65
79f08007
YZ		 66/* The Adjusted Place, as defined by AAELF. */
67#define Pa(X) ((X) & 0xfffffffc)
68
3e6b1042
DJ		 69static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
70 struct bfd_link_info *link_info,
71 asection *sec,
72 bfd_byte *contents);
73
7f266840
DJ		 74/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
75 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
76 in that slot. */
77
c19d1205 78static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 79{
8029a119 80 /* No relocation. */
7f266840
DJ		 81 HOWTO (R_ARM_NONE, /* type */
82 0, /* rightshift */
6346d5ca 83 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 84 0, /* bitsize */
85 FALSE, /* pc_relative */
86 0, /* bitpos */
87 complain_overflow_dont,/* complain_on_overflow */
88 bfd_elf_generic_reloc, /* special_function */
89 "R_ARM_NONE", /* name */
90 FALSE, /* partial_inplace */
91 0, /* src_mask */
92 0, /* dst_mask */
93 FALSE), /* pcrel_offset */
94
95 HOWTO (R_ARM_PC24, /* type */
96 2, /* rightshift */
97 2, /* size (0 = byte, 1 = short, 2 = long) */
98 24, /* bitsize */
99 TRUE, /* pc_relative */
100 0, /* bitpos */
101 complain_overflow_signed,/* complain_on_overflow */
102 bfd_elf_generic_reloc, /* special_function */
103 "R_ARM_PC24", /* name */
104 FALSE, /* partial_inplace */
105 0x00ffffff, /* src_mask */
106 0x00ffffff, /* dst_mask */
107 TRUE), /* pcrel_offset */
108
109 /* 32 bit absolute */
110 HOWTO (R_ARM_ABS32, /* type */
111 0, /* rightshift */
112 2, /* size (0 = byte, 1 = short, 2 = long) */
113 32, /* bitsize */
114 FALSE, /* pc_relative */
115 0, /* bitpos */
116 complain_overflow_bitfield,/* complain_on_overflow */
117 bfd_elf_generic_reloc, /* special_function */
118 "R_ARM_ABS32", /* name */
119 FALSE, /* partial_inplace */
120 0xffffffff, /* src_mask */
121 0xffffffff, /* dst_mask */
122 FALSE), /* pcrel_offset */
123
124 /* standard 32bit pc-relative reloc */
125 HOWTO (R_ARM_REL32, /* type */
126 0, /* rightshift */
127 2, /* size (0 = byte, 1 = short, 2 = long) */
128 32, /* bitsize */
129 TRUE, /* pc_relative */
130 0, /* bitpos */
131 complain_overflow_bitfield,/* complain_on_overflow */
132 bfd_elf_generic_reloc, /* special_function */
133 "R_ARM_REL32", /* name */
134 FALSE, /* partial_inplace */
135 0xffffffff, /* src_mask */
136 0xffffffff, /* dst_mask */
137 TRUE), /* pcrel_offset */
138
c19d1205 139 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 140 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 141 0, /* rightshift */
142 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 143 32, /* bitsize */
144 TRUE, /* pc_relative */
7f266840 145 0, /* bitpos */
4962c51a 146 complain_overflow_dont,/* complain_on_overflow */
7f266840 147 bfd_elf_generic_reloc, /* special_function */
4962c51a 148 "R_ARM_LDR_PC_G0", /* name */
7f266840 149 FALSE, /* partial_inplace */
4962c51a
MS		 150 0xffffffff, /* src_mask */
151 0xffffffff, /* dst_mask */
152 TRUE), /* pcrel_offset */
7f266840
DJ		 153
154 /* 16 bit absolute */
155 HOWTO (R_ARM_ABS16, /* type */
156 0, /* rightshift */
157 1, /* size (0 = byte, 1 = short, 2 = long) */
158 16, /* bitsize */
159 FALSE, /* pc_relative */
160 0, /* bitpos */
161 complain_overflow_bitfield,/* complain_on_overflow */
162 bfd_elf_generic_reloc, /* special_function */
163 "R_ARM_ABS16", /* name */
164 FALSE, /* partial_inplace */
165 0x0000ffff, /* src_mask */
166 0x0000ffff, /* dst_mask */
167 FALSE), /* pcrel_offset */
168
169 /* 12 bit absolute */
170 HOWTO (R_ARM_ABS12, /* type */
171 0, /* rightshift */
172 2, /* size (0 = byte, 1 = short, 2 = long) */
173 12, /* bitsize */
174 FALSE, /* pc_relative */
175 0, /* bitpos */
176 complain_overflow_bitfield,/* complain_on_overflow */
177 bfd_elf_generic_reloc, /* special_function */
178 "R_ARM_ABS12", /* name */
179 FALSE, /* partial_inplace */
00a97672
RS		 180 0x00000fff, /* src_mask */
181 0x00000fff, /* dst_mask */
7f266840
DJ		 182 FALSE), /* pcrel_offset */
183
184 HOWTO (R_ARM_THM_ABS5, /* type */
185 6, /* rightshift */
186 1, /* size (0 = byte, 1 = short, 2 = long) */
187 5, /* bitsize */
188 FALSE, /* pc_relative */
189 0, /* bitpos */
190 complain_overflow_bitfield,/* complain_on_overflow */
191 bfd_elf_generic_reloc, /* special_function */
192 "R_ARM_THM_ABS5", /* name */
193 FALSE, /* partial_inplace */
194 0x000007e0, /* src_mask */
195 0x000007e0, /* dst_mask */
196 FALSE), /* pcrel_offset */
197
198 /* 8 bit absolute */
199 HOWTO (R_ARM_ABS8, /* type */
200 0, /* rightshift */
201 0, /* size (0 = byte, 1 = short, 2 = long) */
202 8, /* bitsize */
203 FALSE, /* pc_relative */
204 0, /* bitpos */
205 complain_overflow_bitfield,/* complain_on_overflow */
206 bfd_elf_generic_reloc, /* special_function */
207 "R_ARM_ABS8", /* name */
208 FALSE, /* partial_inplace */
209 0x000000ff, /* src_mask */
210 0x000000ff, /* dst_mask */
211 FALSE), /* pcrel_offset */
212
213 HOWTO (R_ARM_SBREL32, /* type */
214 0, /* rightshift */
215 2, /* size (0 = byte, 1 = short, 2 = long) */
216 32, /* bitsize */
217 FALSE, /* pc_relative */
218 0, /* bitpos */
219 complain_overflow_dont,/* complain_on_overflow */
220 bfd_elf_generic_reloc, /* special_function */
221 "R_ARM_SBREL32", /* name */
222 FALSE, /* partial_inplace */
223 0xffffffff, /* src_mask */
224 0xffffffff, /* dst_mask */
225 FALSE), /* pcrel_offset */
226
c19d1205 227 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 228 1, /* rightshift */
229 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 230 24, /* bitsize */
7f266840
DJ		 231 TRUE, /* pc_relative */
232 0, /* bitpos */
233 complain_overflow_signed,/* complain_on_overflow */
234 bfd_elf_generic_reloc, /* special_function */
c19d1205 235 "R_ARM_THM_CALL", /* name */
7f266840 236 FALSE, /* partial_inplace */
7f6ab9f8
AM		 237 0x07ff2fff, /* src_mask */
238 0x07ff2fff, /* dst_mask */
7f266840
DJ		 239 TRUE), /* pcrel_offset */
240
07d6d2b8 241 HOWTO (R_ARM_THM_PC8, /* type */
7f266840
DJ		 242 1, /* rightshift */
243 1, /* size (0 = byte, 1 = short, 2 = long) */
244 8, /* bitsize */
245 TRUE, /* pc_relative */
246 0, /* bitpos */
247 complain_overflow_signed,/* complain_on_overflow */
248 bfd_elf_generic_reloc, /* special_function */
249 "R_ARM_THM_PC8", /* name */
250 FALSE, /* partial_inplace */
251 0x000000ff, /* src_mask */
252 0x000000ff, /* dst_mask */
253 TRUE), /* pcrel_offset */
254
c19d1205 255 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 256 1, /* rightshift */
257 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 258 32, /* bitsize */
259 FALSE, /* pc_relative */
7f266840
DJ		 260 0, /* bitpos */
261 complain_overflow_signed,/* complain_on_overflow */
262 bfd_elf_generic_reloc, /* special_function */
c19d1205 263 "R_ARM_BREL_ADJ", /* name */
7f266840 264 FALSE, /* partial_inplace */
c19d1205
ZW		 265 0xffffffff, /* src_mask */
266 0xffffffff, /* dst_mask */
267 FALSE), /* pcrel_offset */
7f266840 268
0855e32b 269 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 270 0, /* rightshift */
0855e32b
NS		 271 2, /* size (0 = byte, 1 = short, 2 = long) */
272 32, /* bitsize */
7f266840
DJ		 273 FALSE, /* pc_relative */
274 0, /* bitpos */
0855e32b 275 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 276 bfd_elf_generic_reloc, /* special_function */
0855e32b 277 "R_ARM_TLS_DESC", /* name */
7f266840 278 FALSE, /* partial_inplace */
0855e32b
NS		 279 0xffffffff, /* src_mask */
280 0xffffffff, /* dst_mask */
7f266840
DJ		 281 FALSE), /* pcrel_offset */
282
283 HOWTO (R_ARM_THM_SWI8, /* type */
284 0, /* rightshift */
285 0, /* size (0 = byte, 1 = short, 2 = long) */
286 0, /* bitsize */
287 FALSE, /* pc_relative */
288 0, /* bitpos */
289 complain_overflow_signed,/* complain_on_overflow */
290 bfd_elf_generic_reloc, /* special_function */
291 "R_ARM_SWI8", /* name */
292 FALSE, /* partial_inplace */
293 0x00000000, /* src_mask */
294 0x00000000, /* dst_mask */
295 FALSE), /* pcrel_offset */
296
297 /* BLX instruction for the ARM. */
298 HOWTO (R_ARM_XPC25, /* type */
299 2, /* rightshift */
300 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 301 24, /* bitsize */
7f266840
DJ		 302 TRUE, /* pc_relative */
303 0, /* bitpos */
304 complain_overflow_signed,/* complain_on_overflow */
305 bfd_elf_generic_reloc, /* special_function */
306 "R_ARM_XPC25", /* name */
307 FALSE, /* partial_inplace */
308 0x00ffffff, /* src_mask */
309 0x00ffffff, /* dst_mask */
310 TRUE), /* pcrel_offset */
311
312 /* BLX instruction for the Thumb. */
313 HOWTO (R_ARM_THM_XPC22, /* type */
314 2, /* rightshift */
315 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 316 24, /* bitsize */
7f266840
DJ		 317 TRUE, /* pc_relative */
318 0, /* bitpos */
319 complain_overflow_signed,/* complain_on_overflow */
320 bfd_elf_generic_reloc, /* special_function */
321 "R_ARM_THM_XPC22", /* name */
322 FALSE, /* partial_inplace */
7f6ab9f8
AM		 323 0x07ff2fff, /* src_mask */
324 0x07ff2fff, /* dst_mask */
7f266840
DJ		 325 TRUE), /* pcrel_offset */
326
ba93b8ac 327 /* Dynamic TLS relocations. */
7f266840 328
ba93b8ac 329 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
07d6d2b8
AM		 330 0, /* rightshift */
331 2, /* size (0 = byte, 1 = short, 2 = long) */
332 32, /* bitsize */
333 FALSE, /* pc_relative */
334 0, /* bitpos */
99059e56
RM		 335 complain_overflow_bitfield,/* complain_on_overflow */
336 bfd_elf_generic_reloc, /* special_function */
337 "R_ARM_TLS_DTPMOD32", /* name */
338 TRUE, /* partial_inplace */
339 0xffffffff, /* src_mask */
340 0xffffffff, /* dst_mask */
07d6d2b8 341 FALSE), /* pcrel_offset */
7f266840 342
ba93b8ac 343 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
07d6d2b8
AM		 344 0, /* rightshift */
345 2, /* size (0 = byte, 1 = short, 2 = long) */
346 32, /* bitsize */
347 FALSE, /* pc_relative */
348 0, /* bitpos */
99059e56
RM		 349 complain_overflow_bitfield,/* complain_on_overflow */
350 bfd_elf_generic_reloc, /* special_function */
351 "R_ARM_TLS_DTPOFF32", /* name */
352 TRUE, /* partial_inplace */
353 0xffffffff, /* src_mask */
354 0xffffffff, /* dst_mask */
07d6d2b8 355 FALSE), /* pcrel_offset */
7f266840 356
ba93b8ac 357 HOWTO (R_ARM_TLS_TPOFF32, /* type */
07d6d2b8
AM		 358 0, /* rightshift */
359 2, /* size (0 = byte, 1 = short, 2 = long) */
360 32, /* bitsize */
361 FALSE, /* pc_relative */
362 0, /* bitpos */
99059e56
RM		 363 complain_overflow_bitfield,/* complain_on_overflow */
364 bfd_elf_generic_reloc, /* special_function */
365 "R_ARM_TLS_TPOFF32", /* name */
366 TRUE, /* partial_inplace */
367 0xffffffff, /* src_mask */
368 0xffffffff, /* dst_mask */
07d6d2b8 369 FALSE), /* pcrel_offset */
7f266840
DJ		 370
371 /* Relocs used in ARM Linux */
372
373 HOWTO (R_ARM_COPY, /* type */
07d6d2b8
AM		 374 0, /* rightshift */
375 2, /* size (0 = byte, 1 = short, 2 = long) */
376 32, /* bitsize */
377 FALSE, /* pc_relative */
378 0, /* bitpos */
99059e56
RM		 379 complain_overflow_bitfield,/* complain_on_overflow */
380 bfd_elf_generic_reloc, /* special_function */
381 "R_ARM_COPY", /* name */
382 TRUE, /* partial_inplace */
383 0xffffffff, /* src_mask */
384 0xffffffff, /* dst_mask */
07d6d2b8 385 FALSE), /* pcrel_offset */
7f266840
DJ		 386
387 HOWTO (R_ARM_GLOB_DAT, /* type */
07d6d2b8
AM		 388 0, /* rightshift */
389 2, /* size (0 = byte, 1 = short, 2 = long) */
390 32, /* bitsize */
391 FALSE, /* pc_relative */
392 0, /* bitpos */
99059e56
RM		 393 complain_overflow_bitfield,/* complain_on_overflow */
394 bfd_elf_generic_reloc, /* special_function */
395 "R_ARM_GLOB_DAT", /* name */
396 TRUE, /* partial_inplace */
397 0xffffffff, /* src_mask */
398 0xffffffff, /* dst_mask */
07d6d2b8 399 FALSE), /* pcrel_offset */
7f266840
DJ		 400
401 HOWTO (R_ARM_JUMP_SLOT, /* type */
07d6d2b8
AM		 402 0, /* rightshift */
403 2, /* size (0 = byte, 1 = short, 2 = long) */
404 32, /* bitsize */
405 FALSE, /* pc_relative */
406 0, /* bitpos */
99059e56
RM		 407 complain_overflow_bitfield,/* complain_on_overflow */
408 bfd_elf_generic_reloc, /* special_function */
409 "R_ARM_JUMP_SLOT", /* name */
410 TRUE, /* partial_inplace */
411 0xffffffff, /* src_mask */
412 0xffffffff, /* dst_mask */
07d6d2b8 413 FALSE), /* pcrel_offset */
7f266840
DJ		 414
415 HOWTO (R_ARM_RELATIVE, /* type */
07d6d2b8
AM		 416 0, /* rightshift */
417 2, /* size (0 = byte, 1 = short, 2 = long) */
418 32, /* bitsize */
419 FALSE, /* pc_relative */
420 0, /* bitpos */
99059e56
RM		 421 complain_overflow_bitfield,/* complain_on_overflow */
422 bfd_elf_generic_reloc, /* special_function */
423 "R_ARM_RELATIVE", /* name */
424 TRUE, /* partial_inplace */
425 0xffffffff, /* src_mask */
426 0xffffffff, /* dst_mask */
07d6d2b8 427 FALSE), /* pcrel_offset */
7f266840 428
c19d1205 429 HOWTO (R_ARM_GOTOFF32, /* type */
07d6d2b8
AM		 430 0, /* rightshift */
431 2, /* size (0 = byte, 1 = short, 2 = long) */
432 32, /* bitsize */
433 FALSE, /* pc_relative */
434 0, /* bitpos */
99059e56
RM		 435 complain_overflow_bitfield,/* complain_on_overflow */
436 bfd_elf_generic_reloc, /* special_function */
437 "R_ARM_GOTOFF32", /* name */
438 TRUE, /* partial_inplace */
439 0xffffffff, /* src_mask */
440 0xffffffff, /* dst_mask */
07d6d2b8 441 FALSE), /* pcrel_offset */
7f266840
DJ		 442
443 HOWTO (R_ARM_GOTPC, /* type */
07d6d2b8
AM		 444 0, /* rightshift */
445 2, /* size (0 = byte, 1 = short, 2 = long) */
446 32, /* bitsize */
99059e56 447 TRUE, /* pc_relative */
07d6d2b8 448 0, /* bitpos */
99059e56
RM		 449 complain_overflow_bitfield,/* complain_on_overflow */
450 bfd_elf_generic_reloc, /* special_function */
451 "R_ARM_GOTPC", /* name */
452 TRUE, /* partial_inplace */
453 0xffffffff, /* src_mask */
454 0xffffffff, /* dst_mask */
455 TRUE), /* pcrel_offset */
7f266840
DJ		 456
457 HOWTO (R_ARM_GOT32, /* type */
07d6d2b8
AM		 458 0, /* rightshift */
459 2, /* size (0 = byte, 1 = short, 2 = long) */
460 32, /* bitsize */
99059e56 461 FALSE, /* pc_relative */
07d6d2b8 462 0, /* bitpos */
99059e56
RM		 463 complain_overflow_bitfield,/* complain_on_overflow */
464 bfd_elf_generic_reloc, /* special_function */
465 "R_ARM_GOT32", /* name */
466 TRUE, /* partial_inplace */
467 0xffffffff, /* src_mask */
468 0xffffffff, /* dst_mask */
469 FALSE), /* pcrel_offset */
7f266840
DJ		 470
471 HOWTO (R_ARM_PLT32, /* type */
07d6d2b8
AM		 472 2, /* rightshift */
473 2, /* size (0 = byte, 1 = short, 2 = long) */
474 24, /* bitsize */
99059e56 475 TRUE, /* pc_relative */
07d6d2b8 476 0, /* bitpos */
99059e56
RM		 477 complain_overflow_bitfield,/* complain_on_overflow */
478 bfd_elf_generic_reloc, /* special_function */
479 "R_ARM_PLT32", /* name */
480 FALSE, /* partial_inplace */
481 0x00ffffff, /* src_mask */
482 0x00ffffff, /* dst_mask */
483 TRUE), /* pcrel_offset */
7f266840
DJ		 484
485 HOWTO (R_ARM_CALL, /* type */
486 2, /* rightshift */
487 2, /* size (0 = byte, 1 = short, 2 = long) */
488 24, /* bitsize */
489 TRUE, /* pc_relative */
490 0, /* bitpos */
491 complain_overflow_signed,/* complain_on_overflow */
492 bfd_elf_generic_reloc, /* special_function */
493 "R_ARM_CALL", /* name */
494 FALSE, /* partial_inplace */
495 0x00ffffff, /* src_mask */
496 0x00ffffff, /* dst_mask */
497 TRUE), /* pcrel_offset */
498
499 HOWTO (R_ARM_JUMP24, /* type */
500 2, /* rightshift */
501 2, /* size (0 = byte, 1 = short, 2 = long) */
502 24, /* bitsize */
503 TRUE, /* pc_relative */
504 0, /* bitpos */
505 complain_overflow_signed,/* complain_on_overflow */
506 bfd_elf_generic_reloc, /* special_function */
507 "R_ARM_JUMP24", /* name */
508 FALSE, /* partial_inplace */
509 0x00ffffff, /* src_mask */
510 0x00ffffff, /* dst_mask */
511 TRUE), /* pcrel_offset */
512
c19d1205
ZW		 513 HOWTO (R_ARM_THM_JUMP24, /* type */
514 1, /* rightshift */
515 2, /* size (0 = byte, 1 = short, 2 = long) */
516 24, /* bitsize */
517 TRUE, /* pc_relative */
7f266840 518 0, /* bitpos */
c19d1205 519 complain_overflow_signed,/* complain_on_overflow */
7f266840 520 bfd_elf_generic_reloc, /* special_function */
c19d1205 521 "R_ARM_THM_JUMP24", /* name */
7f266840 522 FALSE, /* partial_inplace */
c19d1205
ZW		 523 0x07ff2fff, /* src_mask */
524 0x07ff2fff, /* dst_mask */
525 TRUE), /* pcrel_offset */
7f266840 526
c19d1205 527 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 528 0, /* rightshift */
c19d1205
ZW		 529 2, /* size (0 = byte, 1 = short, 2 = long) */
530 32, /* bitsize */
7f266840
DJ		 531 FALSE, /* pc_relative */
532 0, /* bitpos */
533 complain_overflow_dont,/* complain_on_overflow */
534 bfd_elf_generic_reloc, /* special_function */
c19d1205 535 "R_ARM_BASE_ABS", /* name */
7f266840 536 FALSE, /* partial_inplace */
c19d1205
ZW		 537 0xffffffff, /* src_mask */
538 0xffffffff, /* dst_mask */
7f266840
DJ		 539 FALSE), /* pcrel_offset */
540
541 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
542 0, /* rightshift */
543 2, /* size (0 = byte, 1 = short, 2 = long) */
544 12, /* bitsize */
545 TRUE, /* pc_relative */
546 0, /* bitpos */
547 complain_overflow_dont,/* complain_on_overflow */
548 bfd_elf_generic_reloc, /* special_function */
549 "R_ARM_ALU_PCREL_7_0", /* name */
550 FALSE, /* partial_inplace */
551 0x00000fff, /* src_mask */
552 0x00000fff, /* dst_mask */
553 TRUE), /* pcrel_offset */
554
555 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
556 0, /* rightshift */
557 2, /* size (0 = byte, 1 = short, 2 = long) */
558 12, /* bitsize */
559 TRUE, /* pc_relative */
560 8, /* bitpos */
561 complain_overflow_dont,/* complain_on_overflow */
562 bfd_elf_generic_reloc, /* special_function */
563 "R_ARM_ALU_PCREL_15_8",/* name */
564 FALSE, /* partial_inplace */
565 0x00000fff, /* src_mask */
566 0x00000fff, /* dst_mask */
567 TRUE), /* pcrel_offset */
568
569 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
570 0, /* rightshift */
571 2, /* size (0 = byte, 1 = short, 2 = long) */
572 12, /* bitsize */
573 TRUE, /* pc_relative */
574 16, /* bitpos */
575 complain_overflow_dont,/* complain_on_overflow */
576 bfd_elf_generic_reloc, /* special_function */
577 "R_ARM_ALU_PCREL_23_15",/* name */
578 FALSE, /* partial_inplace */
579 0x00000fff, /* src_mask */
580 0x00000fff, /* dst_mask */
581 TRUE), /* pcrel_offset */
582
583 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
584 0, /* rightshift */
585 2, /* size (0 = byte, 1 = short, 2 = long) */
586 12, /* bitsize */
587 FALSE, /* pc_relative */
588 0, /* bitpos */
589 complain_overflow_dont,/* complain_on_overflow */
590 bfd_elf_generic_reloc, /* special_function */
591 "R_ARM_LDR_SBREL_11_0",/* name */
592 FALSE, /* partial_inplace */
593 0x00000fff, /* src_mask */
594 0x00000fff, /* dst_mask */
595 FALSE), /* pcrel_offset */
596
597 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
598 0, /* rightshift */
599 2, /* size (0 = byte, 1 = short, 2 = long) */
600 8, /* bitsize */
601 FALSE, /* pc_relative */
602 12, /* bitpos */
603 complain_overflow_dont,/* complain_on_overflow */
604 bfd_elf_generic_reloc, /* special_function */
605 "R_ARM_ALU_SBREL_19_12",/* name */
606 FALSE, /* partial_inplace */
607 0x000ff000, /* src_mask */
608 0x000ff000, /* dst_mask */
609 FALSE), /* pcrel_offset */
610
611 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
612 0, /* rightshift */
613 2, /* size (0 = byte, 1 = short, 2 = long) */
614 8, /* bitsize */
615 FALSE, /* pc_relative */
616 20, /* bitpos */
617 complain_overflow_dont,/* complain_on_overflow */
618 bfd_elf_generic_reloc, /* special_function */
619 "R_ARM_ALU_SBREL_27_20",/* name */
620 FALSE, /* partial_inplace */
621 0x0ff00000, /* src_mask */
622 0x0ff00000, /* dst_mask */
623 FALSE), /* pcrel_offset */
624
625 HOWTO (R_ARM_TARGET1, /* type */
626 0, /* rightshift */
627 2, /* size (0 = byte, 1 = short, 2 = long) */
628 32, /* bitsize */
629 FALSE, /* pc_relative */
630 0, /* bitpos */
631 complain_overflow_dont,/* complain_on_overflow */
632 bfd_elf_generic_reloc, /* special_function */
633 "R_ARM_TARGET1", /* name */
634 FALSE, /* partial_inplace */
635 0xffffffff, /* src_mask */
636 0xffffffff, /* dst_mask */
637 FALSE), /* pcrel_offset */
638
639 HOWTO (R_ARM_ROSEGREL32, /* type */
640 0, /* rightshift */
641 2, /* size (0 = byte, 1 = short, 2 = long) */
642 32, /* bitsize */
643 FALSE, /* pc_relative */
644 0, /* bitpos */
645 complain_overflow_dont,/* complain_on_overflow */
646 bfd_elf_generic_reloc, /* special_function */
647 "R_ARM_ROSEGREL32", /* name */
648 FALSE, /* partial_inplace */
649 0xffffffff, /* src_mask */
650 0xffffffff, /* dst_mask */
651 FALSE), /* pcrel_offset */
652
653 HOWTO (R_ARM_V4BX, /* type */
654 0, /* rightshift */
655 2, /* size (0 = byte, 1 = short, 2 = long) */
656 32, /* bitsize */
657 FALSE, /* pc_relative */
658 0, /* bitpos */
659 complain_overflow_dont,/* complain_on_overflow */
660 bfd_elf_generic_reloc, /* special_function */
661 "R_ARM_V4BX", /* name */
662 FALSE, /* partial_inplace */
663 0xffffffff, /* src_mask */
664 0xffffffff, /* dst_mask */
665 FALSE), /* pcrel_offset */
666
667 HOWTO (R_ARM_TARGET2, /* type */
668 0, /* rightshift */
669 2, /* size (0 = byte, 1 = short, 2 = long) */
670 32, /* bitsize */
671 FALSE, /* pc_relative */
672 0, /* bitpos */
673 complain_overflow_signed,/* complain_on_overflow */
674 bfd_elf_generic_reloc, /* special_function */
675 "R_ARM_TARGET2", /* name */
676 FALSE, /* partial_inplace */
677 0xffffffff, /* src_mask */
678 0xffffffff, /* dst_mask */
679 TRUE), /* pcrel_offset */
680
681 HOWTO (R_ARM_PREL31, /* type */
682 0, /* rightshift */
683 2, /* size (0 = byte, 1 = short, 2 = long) */
684 31, /* bitsize */
685 TRUE, /* pc_relative */
686 0, /* bitpos */
687 complain_overflow_signed,/* complain_on_overflow */
688 bfd_elf_generic_reloc, /* special_function */
689 "R_ARM_PREL31", /* name */
690 FALSE, /* partial_inplace */
691 0x7fffffff, /* src_mask */
692 0x7fffffff, /* dst_mask */
693 TRUE), /* pcrel_offset */
c19d1205
ZW		 694
695 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
696 0, /* rightshift */
697 2, /* size (0 = byte, 1 = short, 2 = long) */
698 16, /* bitsize */
699 FALSE, /* pc_relative */
700 0, /* bitpos */
701 complain_overflow_dont,/* complain_on_overflow */
702 bfd_elf_generic_reloc, /* special_function */
703 "R_ARM_MOVW_ABS_NC", /* name */
704 FALSE, /* partial_inplace */
39623e12
PB		 705 0x000f0fff, /* src_mask */
706 0x000f0fff, /* dst_mask */
c19d1205
ZW		 707 FALSE), /* pcrel_offset */
708
709 HOWTO (R_ARM_MOVT_ABS, /* type */
710 0, /* rightshift */
711 2, /* size (0 = byte, 1 = short, 2 = long) */
712 16, /* bitsize */
713 FALSE, /* pc_relative */
714 0, /* bitpos */
715 complain_overflow_bitfield,/* complain_on_overflow */
716 bfd_elf_generic_reloc, /* special_function */
717 "R_ARM_MOVT_ABS", /* name */
718 FALSE, /* partial_inplace */
39623e12
PB		 719 0x000f0fff, /* src_mask */
720 0x000f0fff, /* dst_mask */
c19d1205
ZW		 721 FALSE), /* pcrel_offset */
722
723 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
724 0, /* rightshift */
725 2, /* size (0 = byte, 1 = short, 2 = long) */
726 16, /* bitsize */
727 TRUE, /* pc_relative */
728 0, /* bitpos */
729 complain_overflow_dont,/* complain_on_overflow */
730 bfd_elf_generic_reloc, /* special_function */
731 "R_ARM_MOVW_PREL_NC", /* name */
732 FALSE, /* partial_inplace */
39623e12
PB		 733 0x000f0fff, /* src_mask */
734 0x000f0fff, /* dst_mask */
c19d1205
ZW		 735 TRUE), /* pcrel_offset */
736
737 HOWTO (R_ARM_MOVT_PREL, /* type */
738 0, /* rightshift */
739 2, /* size (0 = byte, 1 = short, 2 = long) */
740 16, /* bitsize */
741 TRUE, /* pc_relative */
742 0, /* bitpos */
743 complain_overflow_bitfield,/* complain_on_overflow */
744 bfd_elf_generic_reloc, /* special_function */
745 "R_ARM_MOVT_PREL", /* name */
746 FALSE, /* partial_inplace */
39623e12
PB		 747 0x000f0fff, /* src_mask */
748 0x000f0fff, /* dst_mask */
c19d1205
ZW		 749 TRUE), /* pcrel_offset */
750
751 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
752 0, /* rightshift */
753 2, /* size (0 = byte, 1 = short, 2 = long) */
754 16, /* bitsize */
755 FALSE, /* pc_relative */
756 0, /* bitpos */
757 complain_overflow_dont,/* complain_on_overflow */
758 bfd_elf_generic_reloc, /* special_function */
759 "R_ARM_THM_MOVW_ABS_NC",/* name */
760 FALSE, /* partial_inplace */
761 0x040f70ff, /* src_mask */
762 0x040f70ff, /* dst_mask */
763 FALSE), /* pcrel_offset */
764
765 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
766 0, /* rightshift */
767 2, /* size (0 = byte, 1 = short, 2 = long) */
768 16, /* bitsize */
769 FALSE, /* pc_relative */
770 0, /* bitpos */
771 complain_overflow_bitfield,/* complain_on_overflow */
772 bfd_elf_generic_reloc, /* special_function */
773 "R_ARM_THM_MOVT_ABS", /* name */
774 FALSE, /* partial_inplace */
775 0x040f70ff, /* src_mask */
776 0x040f70ff, /* dst_mask */
777 FALSE), /* pcrel_offset */
778
779 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
780 0, /* rightshift */
781 2, /* size (0 = byte, 1 = short, 2 = long) */
782 16, /* bitsize */
783 TRUE, /* pc_relative */
784 0, /* bitpos */
785 complain_overflow_dont,/* complain_on_overflow */
786 bfd_elf_generic_reloc, /* special_function */
787 "R_ARM_THM_MOVW_PREL_NC",/* name */
788 FALSE, /* partial_inplace */
789 0x040f70ff, /* src_mask */
790 0x040f70ff, /* dst_mask */
791 TRUE), /* pcrel_offset */
792
793 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
794 0, /* rightshift */
795 2, /* size (0 = byte, 1 = short, 2 = long) */
796 16, /* bitsize */
797 TRUE, /* pc_relative */
798 0, /* bitpos */
799 complain_overflow_bitfield,/* complain_on_overflow */
800 bfd_elf_generic_reloc, /* special_function */
801 "R_ARM_THM_MOVT_PREL", /* name */
802 FALSE, /* partial_inplace */
803 0x040f70ff, /* src_mask */
804 0x040f70ff, /* dst_mask */
805 TRUE), /* pcrel_offset */
806
807 HOWTO (R_ARM_THM_JUMP19, /* type */
808 1, /* rightshift */
809 2, /* size (0 = byte, 1 = short, 2 = long) */
810 19, /* bitsize */
811 TRUE, /* pc_relative */
812 0, /* bitpos */
813 complain_overflow_signed,/* complain_on_overflow */
814 bfd_elf_generic_reloc, /* special_function */
815 "R_ARM_THM_JUMP19", /* name */
816 FALSE, /* partial_inplace */
817 0x043f2fff, /* src_mask */
818 0x043f2fff, /* dst_mask */
819 TRUE), /* pcrel_offset */
820
821 HOWTO (R_ARM_THM_JUMP6, /* type */
822 1, /* rightshift */
823 1, /* size (0 = byte, 1 = short, 2 = long) */
824 6, /* bitsize */
825 TRUE, /* pc_relative */
826 0, /* bitpos */
827 complain_overflow_unsigned,/* complain_on_overflow */
828 bfd_elf_generic_reloc, /* special_function */
829 "R_ARM_THM_JUMP6", /* name */
830 FALSE, /* partial_inplace */
831 0x02f8, /* src_mask */
832 0x02f8, /* dst_mask */
833 TRUE), /* pcrel_offset */
834
835 /* These are declared as 13-bit signed relocations because we can
836 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
837 versa. */
838 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
839 0, /* rightshift */
840 2, /* size (0 = byte, 1 = short, 2 = long) */
841 13, /* bitsize */
842 TRUE, /* pc_relative */
843 0, /* bitpos */
2cab6cc3 844 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 845 bfd_elf_generic_reloc, /* special_function */
846 "R_ARM_THM_ALU_PREL_11_0",/* name */
847 FALSE, /* partial_inplace */
2cab6cc3
MS		 848 0xffffffff, /* src_mask */
849 0xffffffff, /* dst_mask */
c19d1205
ZW		 850 TRUE), /* pcrel_offset */
851
852 HOWTO (R_ARM_THM_PC12, /* type */
853 0, /* rightshift */
854 2, /* size (0 = byte, 1 = short, 2 = long) */
855 13, /* bitsize */
856 TRUE, /* pc_relative */
857 0, /* bitpos */
2cab6cc3 858 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 859 bfd_elf_generic_reloc, /* special_function */
860 "R_ARM_THM_PC12", /* name */
861 FALSE, /* partial_inplace */
2cab6cc3
MS		 862 0xffffffff, /* src_mask */
863 0xffffffff, /* dst_mask */
c19d1205
ZW		 864 TRUE), /* pcrel_offset */
865
866 HOWTO (R_ARM_ABS32_NOI, /* type */
867 0, /* rightshift */
868 2, /* size (0 = byte, 1 = short, 2 = long) */
869 32, /* bitsize */
870 FALSE, /* pc_relative */
871 0, /* bitpos */
872 complain_overflow_dont,/* complain_on_overflow */
873 bfd_elf_generic_reloc, /* special_function */
874 "R_ARM_ABS32_NOI", /* name */
875 FALSE, /* partial_inplace */
876 0xffffffff, /* src_mask */
877 0xffffffff, /* dst_mask */
878 FALSE), /* pcrel_offset */
879
880 HOWTO (R_ARM_REL32_NOI, /* type */
881 0, /* rightshift */
882 2, /* size (0 = byte, 1 = short, 2 = long) */
883 32, /* bitsize */
884 TRUE, /* pc_relative */
885 0, /* bitpos */
886 complain_overflow_dont,/* complain_on_overflow */
887 bfd_elf_generic_reloc, /* special_function */
888 "R_ARM_REL32_NOI", /* name */
889 FALSE, /* partial_inplace */
890 0xffffffff, /* src_mask */
891 0xffffffff, /* dst_mask */
892 FALSE), /* pcrel_offset */
7f266840 893
4962c51a
MS		 894 /* Group relocations. */
895
896 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
897 0, /* rightshift */
898 2, /* size (0 = byte, 1 = short, 2 = long) */
899 32, /* bitsize */
900 TRUE, /* pc_relative */
901 0, /* bitpos */
902 complain_overflow_dont,/* complain_on_overflow */
903 bfd_elf_generic_reloc, /* special_function */
904 "R_ARM_ALU_PC_G0_NC", /* name */
905 FALSE, /* partial_inplace */
906 0xffffffff, /* src_mask */
907 0xffffffff, /* dst_mask */
908 TRUE), /* pcrel_offset */
909
07d6d2b8 910 HOWTO (R_ARM_ALU_PC_G0, /* type */
4962c51a
MS		 911 0, /* rightshift */
912 2, /* size (0 = byte, 1 = short, 2 = long) */
913 32, /* bitsize */
914 TRUE, /* pc_relative */
915 0, /* bitpos */
916 complain_overflow_dont,/* complain_on_overflow */
917 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 918 "R_ARM_ALU_PC_G0", /* name */
4962c51a
MS		 919 FALSE, /* partial_inplace */
920 0xffffffff, /* src_mask */
921 0xffffffff, /* dst_mask */
922 TRUE), /* pcrel_offset */
923
924 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
925 0, /* rightshift */
926 2, /* size (0 = byte, 1 = short, 2 = long) */
927 32, /* bitsize */
928 TRUE, /* pc_relative */
929 0, /* bitpos */
930 complain_overflow_dont,/* complain_on_overflow */
931 bfd_elf_generic_reloc, /* special_function */
932 "R_ARM_ALU_PC_G1_NC", /* name */
933 FALSE, /* partial_inplace */
934 0xffffffff, /* src_mask */
935 0xffffffff, /* dst_mask */
936 TRUE), /* pcrel_offset */
937
07d6d2b8 938 HOWTO (R_ARM_ALU_PC_G1, /* type */
4962c51a
MS		 939 0, /* rightshift */
940 2, /* size (0 = byte, 1 = short, 2 = long) */
941 32, /* bitsize */
942 TRUE, /* pc_relative */
943 0, /* bitpos */
944 complain_overflow_dont,/* complain_on_overflow */
945 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 946 "R_ARM_ALU_PC_G1", /* name */
4962c51a
MS		 947 FALSE, /* partial_inplace */
948 0xffffffff, /* src_mask */
949 0xffffffff, /* dst_mask */
950 TRUE), /* pcrel_offset */
951
07d6d2b8 952 HOWTO (R_ARM_ALU_PC_G2, /* type */
4962c51a
MS		 953 0, /* rightshift */
954 2, /* size (0 = byte, 1 = short, 2 = long) */
955 32, /* bitsize */
956 TRUE, /* pc_relative */
957 0, /* bitpos */
958 complain_overflow_dont,/* complain_on_overflow */
959 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 960 "R_ARM_ALU_PC_G2", /* name */
4962c51a
MS		 961 FALSE, /* partial_inplace */
962 0xffffffff, /* src_mask */
963 0xffffffff, /* dst_mask */
964 TRUE), /* pcrel_offset */
965
07d6d2b8 966 HOWTO (R_ARM_LDR_PC_G1, /* type */
4962c51a
MS		 967 0, /* rightshift */
968 2, /* size (0 = byte, 1 = short, 2 = long) */
969 32, /* bitsize */
970 TRUE, /* pc_relative */
971 0, /* bitpos */
972 complain_overflow_dont,/* complain_on_overflow */
973 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 974 "R_ARM_LDR_PC_G1", /* name */
4962c51a
MS		 975 FALSE, /* partial_inplace */
976 0xffffffff, /* src_mask */
977 0xffffffff, /* dst_mask */
978 TRUE), /* pcrel_offset */
979
07d6d2b8 980 HOWTO (R_ARM_LDR_PC_G2, /* type */
4962c51a
MS		 981 0, /* rightshift */
982 2, /* size (0 = byte, 1 = short, 2 = long) */
983 32, /* bitsize */
984 TRUE, /* pc_relative */
985 0, /* bitpos */
986 complain_overflow_dont,/* complain_on_overflow */
987 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 988 "R_ARM_LDR_PC_G2", /* name */
4962c51a
MS		 989 FALSE, /* partial_inplace */
990 0xffffffff, /* src_mask */
991 0xffffffff, /* dst_mask */
992 TRUE), /* pcrel_offset */
993
07d6d2b8 994 HOWTO (R_ARM_LDRS_PC_G0, /* type */
4962c51a
MS		 995 0, /* rightshift */
996 2, /* size (0 = byte, 1 = short, 2 = long) */
997 32, /* bitsize */
998 TRUE, /* pc_relative */
999 0, /* bitpos */
1000 complain_overflow_dont,/* complain_on_overflow */
1001 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1002 "R_ARM_LDRS_PC_G0", /* name */
4962c51a
MS		 1003 FALSE, /* partial_inplace */
1004 0xffffffff, /* src_mask */
1005 0xffffffff, /* dst_mask */
1006 TRUE), /* pcrel_offset */
1007
07d6d2b8 1008 HOWTO (R_ARM_LDRS_PC_G1, /* type */
4962c51a
MS		 1009 0, /* rightshift */
1010 2, /* size (0 = byte, 1 = short, 2 = long) */
1011 32, /* bitsize */
1012 TRUE, /* pc_relative */
1013 0, /* bitpos */
1014 complain_overflow_dont,/* complain_on_overflow */
1015 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1016 "R_ARM_LDRS_PC_G1", /* name */
4962c51a
MS		 1017 FALSE, /* partial_inplace */
1018 0xffffffff, /* src_mask */
1019 0xffffffff, /* dst_mask */
1020 TRUE), /* pcrel_offset */
1021
07d6d2b8 1022 HOWTO (R_ARM_LDRS_PC_G2, /* type */
4962c51a
MS		 1023 0, /* rightshift */
1024 2, /* size (0 = byte, 1 = short, 2 = long) */
1025 32, /* bitsize */
1026 TRUE, /* pc_relative */
1027 0, /* bitpos */
1028 complain_overflow_dont,/* complain_on_overflow */
1029 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1030 "R_ARM_LDRS_PC_G2", /* name */
4962c51a
MS		 1031 FALSE, /* partial_inplace */
1032 0xffffffff, /* src_mask */
1033 0xffffffff, /* dst_mask */
1034 TRUE), /* pcrel_offset */
1035
07d6d2b8 1036 HOWTO (R_ARM_LDC_PC_G0, /* type */
4962c51a
MS		 1037 0, /* rightshift */
1038 2, /* size (0 = byte, 1 = short, 2 = long) */
1039 32, /* bitsize */
1040 TRUE, /* pc_relative */
1041 0, /* bitpos */
1042 complain_overflow_dont,/* complain_on_overflow */
1043 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1044 "R_ARM_LDC_PC_G0", /* name */
4962c51a
MS		 1045 FALSE, /* partial_inplace */
1046 0xffffffff, /* src_mask */
1047 0xffffffff, /* dst_mask */
1048 TRUE), /* pcrel_offset */
1049
07d6d2b8 1050 HOWTO (R_ARM_LDC_PC_G1, /* type */
4962c51a
MS		 1051 0, /* rightshift */
1052 2, /* size (0 = byte, 1 = short, 2 = long) */
1053 32, /* bitsize */
1054 TRUE, /* pc_relative */
1055 0, /* bitpos */
1056 complain_overflow_dont,/* complain_on_overflow */
1057 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1058 "R_ARM_LDC_PC_G1", /* name */
4962c51a
MS		 1059 FALSE, /* partial_inplace */
1060 0xffffffff, /* src_mask */
1061 0xffffffff, /* dst_mask */
1062 TRUE), /* pcrel_offset */
1063
07d6d2b8 1064 HOWTO (R_ARM_LDC_PC_G2, /* type */
4962c51a
MS		 1065 0, /* rightshift */
1066 2, /* size (0 = byte, 1 = short, 2 = long) */
1067 32, /* bitsize */
1068 TRUE, /* pc_relative */
1069 0, /* bitpos */
1070 complain_overflow_dont,/* complain_on_overflow */
1071 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1072 "R_ARM_LDC_PC_G2", /* name */
4962c51a
MS		 1073 FALSE, /* partial_inplace */
1074 0xffffffff, /* src_mask */
1075 0xffffffff, /* dst_mask */
1076 TRUE), /* pcrel_offset */
1077
07d6d2b8 1078 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
4962c51a
MS		 1079 0, /* rightshift */
1080 2, /* size (0 = byte, 1 = short, 2 = long) */
1081 32, /* bitsize */
1082 TRUE, /* pc_relative */
1083 0, /* bitpos */
1084 complain_overflow_dont,/* complain_on_overflow */
1085 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1086 "R_ARM_ALU_SB_G0_NC", /* name */
4962c51a
MS		 1087 FALSE, /* partial_inplace */
1088 0xffffffff, /* src_mask */
1089 0xffffffff, /* dst_mask */
1090 TRUE), /* pcrel_offset */
1091
07d6d2b8 1092 HOWTO (R_ARM_ALU_SB_G0, /* type */
4962c51a
MS		 1093 0, /* rightshift */
1094 2, /* size (0 = byte, 1 = short, 2 = long) */
1095 32, /* bitsize */
1096 TRUE, /* pc_relative */
1097 0, /* bitpos */
1098 complain_overflow_dont,/* complain_on_overflow */
1099 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1100 "R_ARM_ALU_SB_G0", /* name */
4962c51a
MS		 1101 FALSE, /* partial_inplace */
1102 0xffffffff, /* src_mask */
1103 0xffffffff, /* dst_mask */
1104 TRUE), /* pcrel_offset */
1105
07d6d2b8 1106 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
4962c51a
MS		 1107 0, /* rightshift */
1108 2, /* size (0 = byte, 1 = short, 2 = long) */
1109 32, /* bitsize */
1110 TRUE, /* pc_relative */
1111 0, /* bitpos */
1112 complain_overflow_dont,/* complain_on_overflow */
1113 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1114 "R_ARM_ALU_SB_G1_NC", /* name */
4962c51a
MS		 1115 FALSE, /* partial_inplace */
1116 0xffffffff, /* src_mask */
1117 0xffffffff, /* dst_mask */
1118 TRUE), /* pcrel_offset */
1119
07d6d2b8 1120 HOWTO (R_ARM_ALU_SB_G1, /* type */
4962c51a
MS		 1121 0, /* rightshift */
1122 2, /* size (0 = byte, 1 = short, 2 = long) */
1123 32, /* bitsize */
1124 TRUE, /* pc_relative */
1125 0, /* bitpos */
1126 complain_overflow_dont,/* complain_on_overflow */
1127 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1128 "R_ARM_ALU_SB_G1", /* name */
4962c51a
MS		 1129 FALSE, /* partial_inplace */
1130 0xffffffff, /* src_mask */
1131 0xffffffff, /* dst_mask */
1132 TRUE), /* pcrel_offset */
1133
07d6d2b8 1134 HOWTO (R_ARM_ALU_SB_G2, /* type */
4962c51a
MS		 1135 0, /* rightshift */
1136 2, /* size (0 = byte, 1 = short, 2 = long) */
1137 32, /* bitsize */
1138 TRUE, /* pc_relative */
1139 0, /* bitpos */
1140 complain_overflow_dont,/* complain_on_overflow */
1141 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1142 "R_ARM_ALU_SB_G2", /* name */
4962c51a
MS		 1143 FALSE, /* partial_inplace */
1144 0xffffffff, /* src_mask */
1145 0xffffffff, /* dst_mask */
1146 TRUE), /* pcrel_offset */
1147
07d6d2b8 1148 HOWTO (R_ARM_LDR_SB_G0, /* type */
4962c51a
MS		 1149 0, /* rightshift */
1150 2, /* size (0 = byte, 1 = short, 2 = long) */
1151 32, /* bitsize */
1152 TRUE, /* pc_relative */
1153 0, /* bitpos */
1154 complain_overflow_dont,/* complain_on_overflow */
1155 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1156 "R_ARM_LDR_SB_G0", /* name */
4962c51a
MS		 1157 FALSE, /* partial_inplace */
1158 0xffffffff, /* src_mask */
1159 0xffffffff, /* dst_mask */
1160 TRUE), /* pcrel_offset */
1161
07d6d2b8 1162 HOWTO (R_ARM_LDR_SB_G1, /* type */
4962c51a
MS		 1163 0, /* rightshift */
1164 2, /* size (0 = byte, 1 = short, 2 = long) */
1165 32, /* bitsize */
1166 TRUE, /* pc_relative */
1167 0, /* bitpos */
1168 complain_overflow_dont,/* complain_on_overflow */
1169 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1170 "R_ARM_LDR_SB_G1", /* name */
4962c51a
MS		 1171 FALSE, /* partial_inplace */
1172 0xffffffff, /* src_mask */
1173 0xffffffff, /* dst_mask */
1174 TRUE), /* pcrel_offset */
1175
07d6d2b8 1176 HOWTO (R_ARM_LDR_SB_G2, /* type */
4962c51a
MS		 1177 0, /* rightshift */
1178 2, /* size (0 = byte, 1 = short, 2 = long) */
1179 32, /* bitsize */
1180 TRUE, /* pc_relative */
1181 0, /* bitpos */
1182 complain_overflow_dont,/* complain_on_overflow */
1183 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1184 "R_ARM_LDR_SB_G2", /* name */
4962c51a
MS		 1185 FALSE, /* partial_inplace */
1186 0xffffffff, /* src_mask */
1187 0xffffffff, /* dst_mask */
1188 TRUE), /* pcrel_offset */
1189
07d6d2b8 1190 HOWTO (R_ARM_LDRS_SB_G0, /* type */
4962c51a
MS		 1191 0, /* rightshift */
1192 2, /* size (0 = byte, 1 = short, 2 = long) */
1193 32, /* bitsize */
1194 TRUE, /* pc_relative */
1195 0, /* bitpos */
1196 complain_overflow_dont,/* complain_on_overflow */
1197 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1198 "R_ARM_LDRS_SB_G0", /* name */
4962c51a
MS		 1199 FALSE, /* partial_inplace */
1200 0xffffffff, /* src_mask */
1201 0xffffffff, /* dst_mask */
1202 TRUE), /* pcrel_offset */
1203
07d6d2b8 1204 HOWTO (R_ARM_LDRS_SB_G1, /* type */
4962c51a
MS		 1205 0, /* rightshift */
1206 2, /* size (0 = byte, 1 = short, 2 = long) */
1207 32, /* bitsize */
1208 TRUE, /* pc_relative */
1209 0, /* bitpos */
1210 complain_overflow_dont,/* complain_on_overflow */
1211 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1212 "R_ARM_LDRS_SB_G1", /* name */
4962c51a
MS		 1213 FALSE, /* partial_inplace */
1214 0xffffffff, /* src_mask */
1215 0xffffffff, /* dst_mask */
1216 TRUE), /* pcrel_offset */
1217
07d6d2b8 1218 HOWTO (R_ARM_LDRS_SB_G2, /* type */
4962c51a
MS		 1219 0, /* rightshift */
1220 2, /* size (0 = byte, 1 = short, 2 = long) */
1221 32, /* bitsize */
1222 TRUE, /* pc_relative */
1223 0, /* bitpos */
1224 complain_overflow_dont,/* complain_on_overflow */
1225 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1226 "R_ARM_LDRS_SB_G2", /* name */
4962c51a
MS		 1227 FALSE, /* partial_inplace */
1228 0xffffffff, /* src_mask */
1229 0xffffffff, /* dst_mask */
1230 TRUE), /* pcrel_offset */
1231
07d6d2b8 1232 HOWTO (R_ARM_LDC_SB_G0, /* type */
4962c51a
MS		 1233 0, /* rightshift */
1234 2, /* size (0 = byte, 1 = short, 2 = long) */
1235 32, /* bitsize */
1236 TRUE, /* pc_relative */
1237 0, /* bitpos */
1238 complain_overflow_dont,/* complain_on_overflow */
1239 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1240 "R_ARM_LDC_SB_G0", /* name */
4962c51a
MS		 1241 FALSE, /* partial_inplace */
1242 0xffffffff, /* src_mask */
1243 0xffffffff, /* dst_mask */
1244 TRUE), /* pcrel_offset */
1245
07d6d2b8 1246 HOWTO (R_ARM_LDC_SB_G1, /* type */
4962c51a
MS		 1247 0, /* rightshift */
1248 2, /* size (0 = byte, 1 = short, 2 = long) */
1249 32, /* bitsize */
1250 TRUE, /* pc_relative */
1251 0, /* bitpos */
1252 complain_overflow_dont,/* complain_on_overflow */
1253 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1254 "R_ARM_LDC_SB_G1", /* name */
4962c51a
MS		 1255 FALSE, /* partial_inplace */
1256 0xffffffff, /* src_mask */
1257 0xffffffff, /* dst_mask */
1258 TRUE), /* pcrel_offset */
1259
07d6d2b8 1260 HOWTO (R_ARM_LDC_SB_G2, /* type */
4962c51a
MS		 1261 0, /* rightshift */
1262 2, /* size (0 = byte, 1 = short, 2 = long) */
1263 32, /* bitsize */
1264 TRUE, /* pc_relative */
1265 0, /* bitpos */
1266 complain_overflow_dont,/* complain_on_overflow */
1267 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1268 "R_ARM_LDC_SB_G2", /* name */
4962c51a
MS		 1269 FALSE, /* partial_inplace */
1270 0xffffffff, /* src_mask */
1271 0xffffffff, /* dst_mask */
1272 TRUE), /* pcrel_offset */
1273
1274 /* End of group relocations. */
c19d1205 1275
c19d1205
ZW		 1276 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1277 0, /* rightshift */
1278 2, /* size (0 = byte, 1 = short, 2 = long) */
1279 16, /* bitsize */
1280 FALSE, /* pc_relative */
1281 0, /* bitpos */
1282 complain_overflow_dont,/* complain_on_overflow */
1283 bfd_elf_generic_reloc, /* special_function */
1284 "R_ARM_MOVW_BREL_NC", /* name */
1285 FALSE, /* partial_inplace */
1286 0x0000ffff, /* src_mask */
1287 0x0000ffff, /* dst_mask */
1288 FALSE), /* pcrel_offset */
1289
1290 HOWTO (R_ARM_MOVT_BREL, /* type */
1291 0, /* rightshift */
1292 2, /* size (0 = byte, 1 = short, 2 = long) */
1293 16, /* bitsize */
1294 FALSE, /* pc_relative */
1295 0, /* bitpos */
1296 complain_overflow_bitfield,/* complain_on_overflow */
1297 bfd_elf_generic_reloc, /* special_function */
1298 "R_ARM_MOVT_BREL", /* name */
1299 FALSE, /* partial_inplace */
1300 0x0000ffff, /* src_mask */
1301 0x0000ffff, /* dst_mask */
1302 FALSE), /* pcrel_offset */
1303
1304 HOWTO (R_ARM_MOVW_BREL, /* type */
1305 0, /* rightshift */
1306 2, /* size (0 = byte, 1 = short, 2 = long) */
1307 16, /* bitsize */
1308 FALSE, /* pc_relative */
1309 0, /* bitpos */
1310 complain_overflow_dont,/* complain_on_overflow */
1311 bfd_elf_generic_reloc, /* special_function */
1312 "R_ARM_MOVW_BREL", /* name */
1313 FALSE, /* partial_inplace */
1314 0x0000ffff, /* src_mask */
1315 0x0000ffff, /* dst_mask */
1316 FALSE), /* pcrel_offset */
1317
1318 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1319 0, /* rightshift */
1320 2, /* size (0 = byte, 1 = short, 2 = long) */
1321 16, /* bitsize */
1322 FALSE, /* pc_relative */
1323 0, /* bitpos */
1324 complain_overflow_dont,/* complain_on_overflow */
1325 bfd_elf_generic_reloc, /* special_function */
1326 "R_ARM_THM_MOVW_BREL_NC",/* name */
1327 FALSE, /* partial_inplace */
1328 0x040f70ff, /* src_mask */
1329 0x040f70ff, /* dst_mask */
1330 FALSE), /* pcrel_offset */
1331
1332 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1333 0, /* rightshift */
1334 2, /* size (0 = byte, 1 = short, 2 = long) */
1335 16, /* bitsize */
1336 FALSE, /* pc_relative */
1337 0, /* bitpos */
1338 complain_overflow_bitfield,/* complain_on_overflow */
1339 bfd_elf_generic_reloc, /* special_function */
1340 "R_ARM_THM_MOVT_BREL", /* name */
1341 FALSE, /* partial_inplace */
1342 0x040f70ff, /* src_mask */
1343 0x040f70ff, /* dst_mask */
1344 FALSE), /* pcrel_offset */
1345
1346 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1347 0, /* rightshift */
1348 2, /* size (0 = byte, 1 = short, 2 = long) */
1349 16, /* bitsize */
1350 FALSE, /* pc_relative */
1351 0, /* bitpos */
1352 complain_overflow_dont,/* complain_on_overflow */
1353 bfd_elf_generic_reloc, /* special_function */
1354 "R_ARM_THM_MOVW_BREL", /* name */
1355 FALSE, /* partial_inplace */
1356 0x040f70ff, /* src_mask */
1357 0x040f70ff, /* dst_mask */
1358 FALSE), /* pcrel_offset */
1359
0855e32b
NS		 1360 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1361 0, /* rightshift */
1362 2, /* size (0 = byte, 1 = short, 2 = long) */
1363 32, /* bitsize */
1364 FALSE, /* pc_relative */
1365 0, /* bitpos */
1366 complain_overflow_bitfield,/* complain_on_overflow */
1367 NULL, /* special_function */
1368 "R_ARM_TLS_GOTDESC", /* name */
1369 TRUE, /* partial_inplace */
1370 0xffffffff, /* src_mask */
1371 0xffffffff, /* dst_mask */
1372 FALSE), /* pcrel_offset */
1373
1374 HOWTO (R_ARM_TLS_CALL, /* type */
1375 0, /* rightshift */
1376 2, /* size (0 = byte, 1 = short, 2 = long) */
1377 24, /* bitsize */
1378 FALSE, /* pc_relative */
1379 0, /* bitpos */
1380 complain_overflow_dont,/* complain_on_overflow */
1381 bfd_elf_generic_reloc, /* special_function */
1382 "R_ARM_TLS_CALL", /* name */
1383 FALSE, /* partial_inplace */
1384 0x00ffffff, /* src_mask */
1385 0x00ffffff, /* dst_mask */
1386 FALSE), /* pcrel_offset */
1387
1388 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1389 0, /* rightshift */
1390 2, /* size (0 = byte, 1 = short, 2 = long) */
1391 0, /* bitsize */
1392 FALSE, /* pc_relative */
1393 0, /* bitpos */
1394 complain_overflow_bitfield,/* complain_on_overflow */
1395 bfd_elf_generic_reloc, /* special_function */
1396 "R_ARM_TLS_DESCSEQ", /* name */
1397 FALSE, /* partial_inplace */
1398 0x00000000, /* src_mask */
1399 0x00000000, /* dst_mask */
1400 FALSE), /* pcrel_offset */
1401
1402 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1403 0, /* rightshift */
1404 2, /* size (0 = byte, 1 = short, 2 = long) */
1405 24, /* bitsize */
1406 FALSE, /* pc_relative */
1407 0, /* bitpos */
1408 complain_overflow_dont,/* complain_on_overflow */
1409 bfd_elf_generic_reloc, /* special_function */
1410 "R_ARM_THM_TLS_CALL", /* name */
1411 FALSE, /* partial_inplace */
1412 0x07ff07ff, /* src_mask */
1413 0x07ff07ff, /* dst_mask */
1414 FALSE), /* pcrel_offset */
c19d1205
ZW		 1415
1416 HOWTO (R_ARM_PLT32_ABS, /* type */
1417 0, /* rightshift */
1418 2, /* size (0 = byte, 1 = short, 2 = long) */
1419 32, /* bitsize */
1420 FALSE, /* pc_relative */
1421 0, /* bitpos */
1422 complain_overflow_dont,/* complain_on_overflow */
1423 bfd_elf_generic_reloc, /* special_function */
1424 "R_ARM_PLT32_ABS", /* name */
1425 FALSE, /* partial_inplace */
1426 0xffffffff, /* src_mask */
1427 0xffffffff, /* dst_mask */
1428 FALSE), /* pcrel_offset */
1429
1430 HOWTO (R_ARM_GOT_ABS, /* type */
1431 0, /* rightshift */
1432 2, /* size (0 = byte, 1 = short, 2 = long) */
1433 32, /* bitsize */
1434 FALSE, /* pc_relative */
1435 0, /* bitpos */
1436 complain_overflow_dont,/* complain_on_overflow */
1437 bfd_elf_generic_reloc, /* special_function */
1438 "R_ARM_GOT_ABS", /* name */
1439 FALSE, /* partial_inplace */
1440 0xffffffff, /* src_mask */
1441 0xffffffff, /* dst_mask */
1442 FALSE), /* pcrel_offset */
1443
1444 HOWTO (R_ARM_GOT_PREL, /* type */
1445 0, /* rightshift */
1446 2, /* size (0 = byte, 1 = short, 2 = long) */
1447 32, /* bitsize */
1448 TRUE, /* pc_relative */
1449 0, /* bitpos */
1450 complain_overflow_dont, /* complain_on_overflow */
1451 bfd_elf_generic_reloc, /* special_function */
1452 "R_ARM_GOT_PREL", /* name */
1453 FALSE, /* partial_inplace */
1454 0xffffffff, /* src_mask */
1455 0xffffffff, /* dst_mask */
1456 TRUE), /* pcrel_offset */
1457
1458 HOWTO (R_ARM_GOT_BREL12, /* type */
1459 0, /* rightshift */
1460 2, /* size (0 = byte, 1 = short, 2 = long) */
1461 12, /* bitsize */
1462 FALSE, /* pc_relative */
1463 0, /* bitpos */
1464 complain_overflow_bitfield,/* complain_on_overflow */
1465 bfd_elf_generic_reloc, /* special_function */
1466 "R_ARM_GOT_BREL12", /* name */
1467 FALSE, /* partial_inplace */
1468 0x00000fff, /* src_mask */
1469 0x00000fff, /* dst_mask */
1470 FALSE), /* pcrel_offset */
1471
1472 HOWTO (R_ARM_GOTOFF12, /* type */
1473 0, /* rightshift */
1474 2, /* size (0 = byte, 1 = short, 2 = long) */
1475 12, /* bitsize */
1476 FALSE, /* pc_relative */
1477 0, /* bitpos */
1478 complain_overflow_bitfield,/* complain_on_overflow */
1479 bfd_elf_generic_reloc, /* special_function */
1480 "R_ARM_GOTOFF12", /* name */
1481 FALSE, /* partial_inplace */
1482 0x00000fff, /* src_mask */
1483 0x00000fff, /* dst_mask */
1484 FALSE), /* pcrel_offset */
1485
07d6d2b8 1486 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
c19d1205
ZW		 1487
1488 /* GNU extension to record C++ vtable member usage */
07d6d2b8
AM		 1489 HOWTO (R_ARM_GNU_VTENTRY, /* type */
1490 0, /* rightshift */
1491 2, /* size (0 = byte, 1 = short, 2 = long) */
1492 0, /* bitsize */
1493 FALSE, /* pc_relative */
1494 0, /* bitpos */
99059e56 1495 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8
AM		 1496 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1497 "R_ARM_GNU_VTENTRY", /* name */
1498 FALSE, /* partial_inplace */
1499 0, /* src_mask */
1500 0, /* dst_mask */
1501 FALSE), /* pcrel_offset */
c19d1205
ZW		 1502
1503 /* GNU extension to record C++ vtable hierarchy */
1504 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
07d6d2b8
AM		 1505 0, /* rightshift */
1506 2, /* size (0 = byte, 1 = short, 2 = long) */
1507 0, /* bitsize */
1508 FALSE, /* pc_relative */
1509 0, /* bitpos */
99059e56 1510 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8 1511 NULL, /* special_function */
99059e56 1512 "R_ARM_GNU_VTINHERIT", /* name */
07d6d2b8
AM		 1513 FALSE, /* partial_inplace */
1514 0, /* src_mask */
1515 0, /* dst_mask */
1516 FALSE), /* pcrel_offset */
c19d1205
ZW		 1517
1518 HOWTO (R_ARM_THM_JUMP11, /* type */
1519 1, /* rightshift */
1520 1, /* size (0 = byte, 1 = short, 2 = long) */
1521 11, /* bitsize */
1522 TRUE, /* pc_relative */
1523 0, /* bitpos */
1524 complain_overflow_signed, /* complain_on_overflow */
1525 bfd_elf_generic_reloc, /* special_function */
1526 "R_ARM_THM_JUMP11", /* name */
1527 FALSE, /* partial_inplace */
1528 0x000007ff, /* src_mask */
1529 0x000007ff, /* dst_mask */
1530 TRUE), /* pcrel_offset */
1531
1532 HOWTO (R_ARM_THM_JUMP8, /* type */
1533 1, /* rightshift */
1534 1, /* size (0 = byte, 1 = short, 2 = long) */
1535 8, /* bitsize */
1536 TRUE, /* pc_relative */
1537 0, /* bitpos */
1538 complain_overflow_signed, /* complain_on_overflow */
1539 bfd_elf_generic_reloc, /* special_function */
1540 "R_ARM_THM_JUMP8", /* name */
1541 FALSE, /* partial_inplace */
1542 0x000000ff, /* src_mask */
1543 0x000000ff, /* dst_mask */
1544 TRUE), /* pcrel_offset */
ba93b8ac 1545
c19d1205
ZW		 1546 /* TLS relocations */
1547 HOWTO (R_ARM_TLS_GD32, /* type */
07d6d2b8
AM		 1548 0, /* rightshift */
1549 2, /* size (0 = byte, 1 = short, 2 = long) */
1550 32, /* bitsize */
1551 FALSE, /* pc_relative */
1552 0, /* bitpos */
99059e56
RM		 1553 complain_overflow_bitfield,/* complain_on_overflow */
1554 NULL, /* special_function */
1555 "R_ARM_TLS_GD32", /* name */
1556 TRUE, /* partial_inplace */
1557 0xffffffff, /* src_mask */
1558 0xffffffff, /* dst_mask */
07d6d2b8 1559 FALSE), /* pcrel_offset */
ba93b8ac 1560
ba93b8ac 1561 HOWTO (R_ARM_TLS_LDM32, /* type */
07d6d2b8
AM		 1562 0, /* rightshift */
1563 2, /* size (0 = byte, 1 = short, 2 = long) */
1564 32, /* bitsize */
1565 FALSE, /* pc_relative */
1566 0, /* bitpos */
99059e56
RM		 1567 complain_overflow_bitfield,/* complain_on_overflow */
1568 bfd_elf_generic_reloc, /* special_function */
1569 "R_ARM_TLS_LDM32", /* name */
1570 TRUE, /* partial_inplace */
1571 0xffffffff, /* src_mask */
1572 0xffffffff, /* dst_mask */
07d6d2b8 1573 FALSE), /* pcrel_offset */
ba93b8ac 1574
c19d1205 1575 HOWTO (R_ARM_TLS_LDO32, /* type */
07d6d2b8
AM		 1576 0, /* rightshift */
1577 2, /* size (0 = byte, 1 = short, 2 = long) */
1578 32, /* bitsize */
1579 FALSE, /* pc_relative */
1580 0, /* bitpos */
99059e56
RM		 1581 complain_overflow_bitfield,/* complain_on_overflow */
1582 bfd_elf_generic_reloc, /* special_function */
1583 "R_ARM_TLS_LDO32", /* name */
1584 TRUE, /* partial_inplace */
1585 0xffffffff, /* src_mask */
1586 0xffffffff, /* dst_mask */
07d6d2b8 1587 FALSE), /* pcrel_offset */
ba93b8ac 1588
ba93b8ac 1589 HOWTO (R_ARM_TLS_IE32, /* type */
07d6d2b8
AM		 1590 0, /* rightshift */
1591 2, /* size (0 = byte, 1 = short, 2 = long) */
1592 32, /* bitsize */
1593 FALSE, /* pc_relative */
1594 0, /* bitpos */
99059e56
RM		 1595 complain_overflow_bitfield,/* complain_on_overflow */
1596 NULL, /* special_function */
1597 "R_ARM_TLS_IE32", /* name */
1598 TRUE, /* partial_inplace */
1599 0xffffffff, /* src_mask */
1600 0xffffffff, /* dst_mask */
07d6d2b8 1601 FALSE), /* pcrel_offset */
7f266840 1602
c19d1205 1603 HOWTO (R_ARM_TLS_LE32, /* type */
07d6d2b8
AM		 1604 0, /* rightshift */
1605 2, /* size (0 = byte, 1 = short, 2 = long) */
1606 32, /* bitsize */
1607 FALSE, /* pc_relative */
1608 0, /* bitpos */
99059e56 1609 complain_overflow_bitfield,/* complain_on_overflow */
07d6d2b8 1610 NULL, /* special_function */
99059e56
RM		 1611 "R_ARM_TLS_LE32", /* name */
1612 TRUE, /* partial_inplace */
1613 0xffffffff, /* src_mask */
1614 0xffffffff, /* dst_mask */
07d6d2b8 1615 FALSE), /* pcrel_offset */
7f266840 1616
c19d1205
ZW		 1617 HOWTO (R_ARM_TLS_LDO12, /* type */
1618 0, /* rightshift */
1619 2, /* size (0 = byte, 1 = short, 2 = long) */
1620 12, /* bitsize */
1621 FALSE, /* pc_relative */
7f266840 1622 0, /* bitpos */
c19d1205 1623 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1624 bfd_elf_generic_reloc, /* special_function */
c19d1205 1625 "R_ARM_TLS_LDO12", /* name */
7f266840 1626 FALSE, /* partial_inplace */
c19d1205
ZW		 1627 0x00000fff, /* src_mask */
1628 0x00000fff, /* dst_mask */
1629 FALSE), /* pcrel_offset */
7f266840 1630
c19d1205
ZW		 1631 HOWTO (R_ARM_TLS_LE12, /* type */
1632 0, /* rightshift */
1633 2, /* size (0 = byte, 1 = short, 2 = long) */
1634 12, /* bitsize */
1635 FALSE, /* pc_relative */
7f266840 1636 0, /* bitpos */
c19d1205 1637 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1638 bfd_elf_generic_reloc, /* special_function */
c19d1205 1639 "R_ARM_TLS_LE12", /* name */
7f266840 1640 FALSE, /* partial_inplace */
c19d1205
ZW		 1641 0x00000fff, /* src_mask */
1642 0x00000fff, /* dst_mask */
1643 FALSE), /* pcrel_offset */
7f266840 1644
c19d1205 1645 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1646 0, /* rightshift */
1647 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1648 12, /* bitsize */
1649 FALSE, /* pc_relative */
7f266840 1650 0, /* bitpos */
c19d1205 1651 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1652 bfd_elf_generic_reloc, /* special_function */
c19d1205 1653 "R_ARM_TLS_IE12GP", /* name */
7f266840 1654 FALSE, /* partial_inplace */
c19d1205
ZW		 1655 0x00000fff, /* src_mask */
1656 0x00000fff, /* dst_mask */
1657 FALSE), /* pcrel_offset */
0855e32b 1658
34e77a92 1659 /* 112-127 private relocations. */
0855e32b
NS		 1660 EMPTY_HOWTO (112),
1661 EMPTY_HOWTO (113),
1662 EMPTY_HOWTO (114),
1663 EMPTY_HOWTO (115),
1664 EMPTY_HOWTO (116),
1665 EMPTY_HOWTO (117),
1666 EMPTY_HOWTO (118),
1667 EMPTY_HOWTO (119),
1668 EMPTY_HOWTO (120),
1669 EMPTY_HOWTO (121),
1670 EMPTY_HOWTO (122),
1671 EMPTY_HOWTO (123),
1672 EMPTY_HOWTO (124),
1673 EMPTY_HOWTO (125),
1674 EMPTY_HOWTO (126),
1675 EMPTY_HOWTO (127),
34e77a92
RS		 1676
1677 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1678 EMPTY_HOWTO (128),
1679
1680 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1681 0, /* rightshift */
1682 1, /* size (0 = byte, 1 = short, 2 = long) */
1683 0, /* bitsize */
1684 FALSE, /* pc_relative */
1685 0, /* bitpos */
1686 complain_overflow_bitfield,/* complain_on_overflow */
1687 bfd_elf_generic_reloc, /* special_function */
1688 "R_ARM_THM_TLS_DESCSEQ",/* name */
1689 FALSE, /* partial_inplace */
1690 0x00000000, /* src_mask */
1691 0x00000000, /* dst_mask */
1692 FALSE), /* pcrel_offset */
72d98d16
MG		 1693 EMPTY_HOWTO (130),
1694 EMPTY_HOWTO (131),
1695 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1696 0, /* rightshift. */
1697 1, /* size (0 = byte, 1 = short, 2 = long). */
1698 16, /* bitsize. */
1699 FALSE, /* pc_relative. */
1700 0, /* bitpos. */
1701 complain_overflow_bitfield,/* complain_on_overflow. */
1702 bfd_elf_generic_reloc, /* special_function. */
1703 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1704 FALSE, /* partial_inplace. */
1705 0x00000000, /* src_mask. */
1706 0x00000000, /* dst_mask. */
1707 FALSE), /* pcrel_offset. */
1708 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1709 0, /* rightshift. */
1710 1, /* size (0 = byte, 1 = short, 2 = long). */
1711 16, /* bitsize. */
1712 FALSE, /* pc_relative. */
1713 0, /* bitpos. */
1714 complain_overflow_bitfield,/* complain_on_overflow. */
1715 bfd_elf_generic_reloc, /* special_function. */
1716 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1717 FALSE, /* partial_inplace. */
1718 0x00000000, /* src_mask. */
1719 0x00000000, /* dst_mask. */
1720 FALSE), /* pcrel_offset. */
1721 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1722 0, /* rightshift. */
1723 1, /* size (0 = byte, 1 = short, 2 = long). */
1724 16, /* bitsize. */
1725 FALSE, /* pc_relative. */
1726 0, /* bitpos. */
1727 complain_overflow_bitfield,/* complain_on_overflow. */
1728 bfd_elf_generic_reloc, /* special_function. */
1729 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1730 FALSE, /* partial_inplace. */
1731 0x00000000, /* src_mask. */
1732 0x00000000, /* dst_mask. */
1733 FALSE), /* pcrel_offset. */
1734 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1735 0, /* rightshift. */
1736 1, /* size (0 = byte, 1 = short, 2 = long). */
1737 16, /* bitsize. */
1738 FALSE, /* pc_relative. */
1739 0, /* bitpos. */
1740 complain_overflow_bitfield,/* complain_on_overflow. */
1741 bfd_elf_generic_reloc, /* special_function. */
1742 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1743 FALSE, /* partial_inplace. */
1744 0x00000000, /* src_mask. */
1745 0x00000000, /* dst_mask. */
1746 FALSE), /* pcrel_offset. */
e5d6e09e
AV		 1747 /* Relocations for Armv8.1-M Mainline. */
1748 HOWTO (R_ARM_THM_BF16, /* type. */
1749 0, /* rightshift. */
1750 1, /* size (0 = byte, 1 = short, 2 = long). */
1751 16, /* bitsize. */
1752 TRUE, /* pc_relative. */
1753 0, /* bitpos. */
1754 complain_overflow_dont,/* do not complain_on_overflow. */
1755 bfd_elf_generic_reloc, /* special_function. */
1756 "R_ARM_THM_BF16", /* name. */
1757 FALSE, /* partial_inplace. */
1758 0x001f0ffe, /* src_mask. */
1759 0x001f0ffe, /* dst_mask. */
1760 TRUE), /* pcrel_offset. */
1889da70
AV		 1761 HOWTO (R_ARM_THM_BF12, /* type. */
1762 0, /* rightshift. */
1763 1, /* size (0 = byte, 1 = short, 2 = long). */
1764 12, /* bitsize. */
1765 TRUE, /* pc_relative. */
1766 0, /* bitpos. */
1767 complain_overflow_dont,/* do not complain_on_overflow. */
1768 bfd_elf_generic_reloc, /* special_function. */
1769 "R_ARM_THM_BF12", /* name. */
1770 FALSE, /* partial_inplace. */
1771 0x00010ffe, /* src_mask. */
1772 0x00010ffe, /* dst_mask. */
1773 TRUE), /* pcrel_offset. */
1caf72a5
AV		 1774 HOWTO (R_ARM_THM_BF18, /* type. */
1775 0, /* rightshift. */
1776 1, /* size (0 = byte, 1 = short, 2 = long). */
1777 18, /* bitsize. */
1778 TRUE, /* pc_relative. */
1779 0, /* bitpos. */
1780 complain_overflow_dont,/* do not complain_on_overflow. */
1781 bfd_elf_generic_reloc, /* special_function. */
1782 "R_ARM_THM_BF18", /* name. */
1783 FALSE, /* partial_inplace. */
1784 0x007f0ffe, /* src_mask. */
1785 0x007f0ffe, /* dst_mask. */
1786 TRUE), /* pcrel_offset. */
c19d1205
ZW		 1787};
1788
34e77a92 1789/* 160 onwards: */
5c5a4843 1790static reloc_howto_type elf32_arm_howto_table_2[8] =
34e77a92
RS		 1791{
1792 HOWTO (R_ARM_IRELATIVE, /* type */
07d6d2b8
AM		 1793 0, /* rightshift */
1794 2, /* size (0 = byte, 1 = short, 2 = long) */
1795 32, /* bitsize */
1796 FALSE, /* pc_relative */
1797 0, /* bitpos */
99059e56
RM		 1798 complain_overflow_bitfield,/* complain_on_overflow */
1799 bfd_elf_generic_reloc, /* special_function */
1800 "R_ARM_IRELATIVE", /* name */
1801 TRUE, /* partial_inplace */
1802 0xffffffff, /* src_mask */
1803 0xffffffff, /* dst_mask */
188fd7ae
CL		 1804 FALSE), /* pcrel_offset */
1805 HOWTO (R_ARM_GOTFUNCDESC, /* type */
1806 0, /* rightshift */
1807 2, /* size (0 = byte, 1 = short, 2 = long) */
1808 32, /* bitsize */
1809 FALSE, /* pc_relative */
1810 0, /* bitpos */
1811 complain_overflow_bitfield,/* complain_on_overflow */
1812 bfd_elf_generic_reloc, /* special_function */
1813 "R_ARM_GOTFUNCDESC", /* name */
1814 FALSE, /* partial_inplace */
1815 0, /* src_mask */
1816 0xffffffff, /* dst_mask */
1817 FALSE), /* pcrel_offset */
1818 HOWTO (R_ARM_GOTOFFFUNCDESC, /* type */
1819 0, /* rightshift */
1820 2, /* size (0 = byte, 1 = short, 2 = long) */
1821 32, /* bitsize */
1822 FALSE, /* pc_relative */
1823 0, /* bitpos */
1824 complain_overflow_bitfield,/* complain_on_overflow */
1825 bfd_elf_generic_reloc, /* special_function */
1826 "R_ARM_GOTOFFFUNCDESC",/* name */
1827 FALSE, /* partial_inplace */
1828 0, /* src_mask */
1829 0xffffffff, /* dst_mask */
1830 FALSE), /* pcrel_offset */
1831 HOWTO (R_ARM_FUNCDESC, /* type */
1832 0, /* rightshift */
1833 2, /* size (0 = byte, 1 = short, 2 = long) */
1834 32, /* bitsize */
1835 FALSE, /* pc_relative */
1836 0, /* bitpos */
1837 complain_overflow_bitfield,/* complain_on_overflow */
1838 bfd_elf_generic_reloc, /* special_function */
1839 "R_ARM_FUNCDESC", /* name */
1840 FALSE, /* partial_inplace */
1841 0, /* src_mask */
1842 0xffffffff, /* dst_mask */
1843 FALSE), /* pcrel_offset */
1844 HOWTO (R_ARM_FUNCDESC_VALUE, /* type */
1845 0, /* rightshift */
1846 2, /* size (0 = byte, 1 = short, 2 = long) */
1847 64, /* bitsize */
1848 FALSE, /* pc_relative */
1849 0, /* bitpos */
1850 complain_overflow_bitfield,/* complain_on_overflow */
1851 bfd_elf_generic_reloc, /* special_function */
1852 "R_ARM_FUNCDESC_VALUE",/* name */
1853 FALSE, /* partial_inplace */
1854 0, /* src_mask */
1855 0xffffffff, /* dst_mask */
1856 FALSE), /* pcrel_offset */
5c5a4843
CL		 1857 HOWTO (R_ARM_TLS_GD32_FDPIC, /* type */
1858 0, /* rightshift */
1859 2, /* size (0 = byte, 1 = short, 2 = long) */
1860 32, /* bitsize */
1861 FALSE, /* pc_relative */
1862 0, /* bitpos */
1863 complain_overflow_bitfield,/* complain_on_overflow */
1864 bfd_elf_generic_reloc, /* special_function */
1865 "R_ARM_TLS_GD32_FDPIC",/* name */
1866 FALSE, /* partial_inplace */
1867 0, /* src_mask */
1868 0xffffffff, /* dst_mask */
1869 FALSE), /* pcrel_offset */
1870 HOWTO (R_ARM_TLS_LDM32_FDPIC, /* type */
1871 0, /* rightshift */
1872 2, /* size (0 = byte, 1 = short, 2 = long) */
1873 32, /* bitsize */
1874 FALSE, /* pc_relative */
1875 0, /* bitpos */
1876 complain_overflow_bitfield,/* complain_on_overflow */
1877 bfd_elf_generic_reloc, /* special_function */
1878 "R_ARM_TLS_LDM32_FDPIC",/* name */
1879 FALSE, /* partial_inplace */
1880 0, /* src_mask */
1881 0xffffffff, /* dst_mask */
1882 FALSE), /* pcrel_offset */
1883 HOWTO (R_ARM_TLS_IE32_FDPIC, /* type */
1884 0, /* rightshift */
1885 2, /* size (0 = byte, 1 = short, 2 = long) */
1886 32, /* bitsize */
1887 FALSE, /* pc_relative */
1888 0, /* bitpos */
1889 complain_overflow_bitfield,/* complain_on_overflow */
1890 bfd_elf_generic_reloc, /* special_function */
1891 "R_ARM_TLS_IE32_FDPIC",/* name */
1892 FALSE, /* partial_inplace */
1893 0, /* src_mask */
1894 0xffffffff, /* dst_mask */
1895 FALSE), /* pcrel_offset */
34e77a92 1896};
c19d1205 1897
34e77a92
RS		 1898/* 249-255 extended, currently unused, relocations: */
1899static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1900{
1901 HOWTO (R_ARM_RREL32, /* type */
1902 0, /* rightshift */
1903 0, /* size (0 = byte, 1 = short, 2 = long) */
1904 0, /* bitsize */
1905 FALSE, /* pc_relative */
1906 0, /* bitpos */
1907 complain_overflow_dont,/* complain_on_overflow */
1908 bfd_elf_generic_reloc, /* special_function */
1909 "R_ARM_RREL32", /* name */
1910 FALSE, /* partial_inplace */
1911 0, /* src_mask */
1912 0, /* dst_mask */
1913 FALSE), /* pcrel_offset */
1914
1915 HOWTO (R_ARM_RABS32, /* type */
1916 0, /* rightshift */
1917 0, /* size (0 = byte, 1 = short, 2 = long) */
1918 0, /* bitsize */
1919 FALSE, /* pc_relative */
1920 0, /* bitpos */
1921 complain_overflow_dont,/* complain_on_overflow */
1922 bfd_elf_generic_reloc, /* special_function */
1923 "R_ARM_RABS32", /* name */
1924 FALSE, /* partial_inplace */
1925 0, /* src_mask */
1926 0, /* dst_mask */
1927 FALSE), /* pcrel_offset */
1928
1929 HOWTO (R_ARM_RPC24, /* type */
1930 0, /* rightshift */
1931 0, /* size (0 = byte, 1 = short, 2 = long) */
1932 0, /* bitsize */
1933 FALSE, /* pc_relative */
1934 0, /* bitpos */
1935 complain_overflow_dont,/* complain_on_overflow */
1936 bfd_elf_generic_reloc, /* special_function */
1937 "R_ARM_RPC24", /* name */
1938 FALSE, /* partial_inplace */
1939 0, /* src_mask */
1940 0, /* dst_mask */
1941 FALSE), /* pcrel_offset */
1942
1943 HOWTO (R_ARM_RBASE, /* type */
1944 0, /* rightshift */
1945 0, /* size (0 = byte, 1 = short, 2 = long) */
1946 0, /* bitsize */
1947 FALSE, /* pc_relative */
1948 0, /* bitpos */
1949 complain_overflow_dont,/* complain_on_overflow */
1950 bfd_elf_generic_reloc, /* special_function */
1951 "R_ARM_RBASE", /* name */
1952 FALSE, /* partial_inplace */
1953 0, /* src_mask */
1954 0, /* dst_mask */
1955 FALSE) /* pcrel_offset */
1956};
1957
1958static reloc_howto_type *
1959elf32_arm_howto_from_type (unsigned int r_type)
1960{
906e58ca 1961 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1962 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1963
188fd7ae
CL		 1964 if (r_type >= R_ARM_IRELATIVE
1965 && r_type < R_ARM_IRELATIVE + ARRAY_SIZE (elf32_arm_howto_table_2))
34e77a92
RS		 1966 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1967
c19d1205 1968 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1969 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1970 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1971
c19d1205 1972 return NULL;
7f266840
DJ		 1973}
1974
f3185997
NC		 1975static bfd_boolean
1976elf32_arm_info_to_howto (bfd * abfd, arelent * bfd_reloc,
7f266840
DJ		 1977 Elf_Internal_Rela * elf_reloc)
1978{
1979 unsigned int r_type;
1980
1981 r_type = ELF32_R_TYPE (elf_reloc->r_info);
f3185997
NC		 1982 if ((bfd_reloc->howto = elf32_arm_howto_from_type (r_type)) == NULL)
1983 {
1984 /* xgettext:c-format */
1985 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
1986 abfd, r_type);
1987 bfd_set_error (bfd_error_bad_value);
1988 return FALSE;
1989 }
1990 return TRUE;
7f266840
DJ		 1991}
1992
1993struct elf32_arm_reloc_map
1994 {
1995 bfd_reloc_code_real_type bfd_reloc_val;
07d6d2b8 1996 unsigned char elf_reloc_val;
7f266840
DJ		 1997 };
1998
1999/* All entries in this list must also be present in elf32_arm_howto_table. */
2000static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
2001 {
07d6d2b8 2002 {BFD_RELOC_NONE, R_ARM_NONE},
7f266840 2003 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 2004 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
2005 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
07d6d2b8
AM		 2006 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
2007 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
2008 {BFD_RELOC_32, R_ARM_ABS32},
2009 {BFD_RELOC_32_PCREL, R_ARM_REL32},
2010 {BFD_RELOC_8, R_ARM_ABS8},
2011 {BFD_RELOC_16, R_ARM_ABS16},
2012 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
7f266840 2013 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 2014 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
2015 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
2016 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
2017 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
2018 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
2019 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
07d6d2b8
AM		 2020 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
2021 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
2022 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
2023 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
2024 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
2025 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
2026 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
2027 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
7f266840
DJ		 2028 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
2029 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
2030 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
2031 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac 2032 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
07d6d2b8
AM		 2033 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
2034 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
2035 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
0855e32b 2036 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
07d6d2b8 2037 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
0855e32b 2038 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
07d6d2b8 2039 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 2040 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
2041 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
2042 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
2043 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
2044 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
07d6d2b8
AM		 2045 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
2046 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
2047 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
2048 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
188fd7ae
CL		 2049 {BFD_RELOC_ARM_GOTFUNCDESC, R_ARM_GOTFUNCDESC},
2050 {BFD_RELOC_ARM_GOTOFFFUNCDESC, R_ARM_GOTOFFFUNCDESC},
2051 {BFD_RELOC_ARM_FUNCDESC, R_ARM_FUNCDESC},
2052 {BFD_RELOC_ARM_FUNCDESC_VALUE, R_ARM_FUNCDESC_VALUE},
5c5a4843
CL		 2053 {BFD_RELOC_ARM_TLS_GD32_FDPIC, R_ARM_TLS_GD32_FDPIC},
2054 {BFD_RELOC_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_LDM32_FDPIC},
2055 {BFD_RELOC_ARM_TLS_IE32_FDPIC, R_ARM_TLS_IE32_FDPIC},
c19d1205
ZW		 2056 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
2057 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 2058 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
2059 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
2060 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
2061 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
2062 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
2063 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
2064 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
2065 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 2066 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
2067 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
2068 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
2069 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
2070 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
2071 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
2072 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
2073 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
2074 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
2075 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
2076 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
2077 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
2078 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
2079 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
2080 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
2081 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
2082 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
2083 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
2084 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
2085 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
2086 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
2087 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
2088 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
2089 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
2090 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
2091 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
2092 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 2093 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 2094 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
2095 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
2096 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
2097 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
e5d6e09e 2098 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC},
1caf72a5 2099 {BFD_RELOC_ARM_THUMB_BF17, R_ARM_THM_BF16},
1889da70 2100 {BFD_RELOC_ARM_THUMB_BF13, R_ARM_THM_BF12},
1caf72a5 2101 {BFD_RELOC_ARM_THUMB_BF19, R_ARM_THM_BF18}
7f266840
DJ		 2102 };
2103
2104static reloc_howto_type *
f1c71a59
ZW		 2105elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2106 bfd_reloc_code_real_type code)
7f266840
DJ		 2107{
2108 unsigned int i;
8029a119 2109
906e58ca 2110 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 2111 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
2112 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 2113
c19d1205 2114 return NULL;
7f266840
DJ		 2115}
2116
157090f7
AM		 2117static reloc_howto_type *
2118elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2119 const char *r_name)
2120{
2121 unsigned int i;
2122
906e58ca 2123 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 2124 if (elf32_arm_howto_table_1[i].name != NULL
2125 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
2126 return &elf32_arm_howto_table_1[i];
2127
906e58ca 2128 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 2129 if (elf32_arm_howto_table_2[i].name != NULL
2130 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
2131 return &elf32_arm_howto_table_2[i];
2132
34e77a92
RS		 2133 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
2134 if (elf32_arm_howto_table_3[i].name != NULL
2135 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
2136 return &elf32_arm_howto_table_3[i];
2137
157090f7
AM		 2138 return NULL;
2139}
2140
906e58ca
NC		 2141/* Support for core dump NOTE sections. */
2142
7f266840 2143static bfd_boolean
f1c71a59 2144elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2145{
2146 int offset;
2147 size_t size;
2148
2149 switch (note->descsz)
2150 {
2151 default:
2152 return FALSE;
2153
8029a119 2154 case 148: /* Linux/ARM 32-bit. */
7f266840 2155 /* pr_cursig */
228e534f 2156 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2157
2158 /* pr_pid */
228e534f 2159 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2160
2161 /* pr_reg */
2162 offset = 72;
2163 size = 72;
2164
2165 break;
2166 }
2167
2168 /* Make a ".reg/999" section. */
2169 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2170 size, note->descpos + offset);
2171}
2172
2173static bfd_boolean
f1c71a59 2174elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2175{
2176 switch (note->descsz)
2177 {
2178 default:
2179 return FALSE;
2180
8029a119 2181 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2182 elf_tdata (abfd)->core->pid
4395ee08 2183 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2184 elf_tdata (abfd)->core->program
7f266840 2185 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2186 elf_tdata (abfd)->core->command
7f266840
DJ		 2187 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2188 }
2189
2190 /* Note that for some reason, a spurious space is tacked
2191 onto the end of the args in some (at least one anyway)
2192 implementations, so strip it off if it exists. */
7f266840 2193 {
228e534f 2194 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2195 int n = strlen (command);
2196
2197 if (0 < n && command[n - 1] == ' ')
2198 command[n - 1] = '\0';
2199 }
2200
2201 return TRUE;
2202}
2203
1f20dca5
UW		 2204static char *
2205elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2206 int note_type, ...)
2207{
2208 switch (note_type)
2209 {
2210 default:
2211 return NULL;
2212
2213 case NT_PRPSINFO:
2214 {
602f1657 2215 char data[124] ATTRIBUTE_NONSTRING;
1f20dca5
UW		 2216 va_list ap;
2217
2218 va_start (ap, note_type);
2219 memset (data, 0, sizeof (data));
2220 strncpy (data + 28, va_arg (ap, const char *), 16);
be3e27bb 2221#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2222 DIAGNOSTIC_PUSH;
be3e27bb 2223 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
95da9854
L		 2224 -Wstringop-truncation:
2225 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2226 */
95da9854
L		 2227 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2228#endif
1f20dca5 2229 strncpy (data + 44, va_arg (ap, const char *), 80);
be3e27bb 2230#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 2231 DIAGNOSTIC_POP;
fe75810f 2232#endif
1f20dca5
UW		 2233 va_end (ap);
2234
2235 return elfcore_write_note (abfd, buf, bufsiz,
2236 "CORE", note_type, data, sizeof (data));
2237 }
2238
2239 case NT_PRSTATUS:
2240 {
2241 char data[148];
2242 va_list ap;
2243 long pid;
2244 int cursig;
2245 const void *greg;
2246
2247 va_start (ap, note_type);
2248 memset (data, 0, sizeof (data));
2249 pid = va_arg (ap, long);
2250 bfd_put_32 (abfd, pid, data + 24);
2251 cursig = va_arg (ap, int);
2252 bfd_put_16 (abfd, cursig, data + 12);
2253 greg = va_arg (ap, const void *);
2254 memcpy (data + 72, greg, 72);
2255 va_end (ap);
2256
2257 return elfcore_write_note (abfd, buf, bufsiz,
2258 "CORE", note_type, data, sizeof (data));
2259 }
2260 }
2261}
2262
07d6d2b8
AM		 2263#define TARGET_LITTLE_SYM arm_elf32_le_vec
2264#define TARGET_LITTLE_NAME "elf32-littlearm"
2265#define TARGET_BIG_SYM arm_elf32_be_vec
2266#define TARGET_BIG_NAME "elf32-bigarm"
7f266840
DJ		 2267
2268#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2269#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2270#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2271
252b5132
RH		 2272typedef unsigned long int insn32;
2273typedef unsigned short int insn16;
2274
3a4a14e9
PB		 2275/* In lieu of proper flags, assume all EABIv4 or later objects are
2276 interworkable. */
57e8b36a 2277#define INTERWORK_FLAG(abfd) \
3a4a14e9 2278 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2279 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2280 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2281
252b5132
RH		 2282/* The linker script knows the section names for placement.
2283 The entry_names are used to do simple name mangling on the stubs.
2284 Given a function name, and its type, the stub can be found. The
9b485d32 2285 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2286#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2287#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2288
2289#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2290#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2291
c7b8f16e
JB		 2292#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2293#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2294
a504d23a
LA		 2295#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2296#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2297
845b51d6
PB		 2298#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2299#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2300
7413f23f
DJ		 2301#define STUB_ENTRY_NAME "__%s_veneer"
2302
4ba2ef8f
TP		 2303#define CMSE_PREFIX "__acle_se_"
2304
4d83e8d9
CL		 2305#define CMSE_STUB_NAME ".gnu.sgstubs"
2306
252b5132
RH		 2307/* The name of the dynamic interpreter. This is put in the .interp
2308 section. */
2309#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2310
cb10292c
CL		 2311/* FDPIC default stack size. */
2312#define DEFAULT_STACK_SIZE 0x8000
2313
0855e32b 2314static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2315{
2316 0xe08e0000, /* add r0, lr, r0 */
2317 0xe5901004, /* ldr r1, [r0,#4] */
2318 0xe12fff11, /* bx r1 */
2319};
0855e32b
NS		 2320
2321static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2322{
2323 0xe52d2004, /* push {r2} */
2324 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2325 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2326 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2327 0xe081100f, /* 2: add r1, pc */
2328 0xe12fff12, /* bx r2 */
2329 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2330 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2331 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2332};
0855e32b 2333
b4e87f2c
TC		 2334/* NOTE: [Thumb nop sequence]
2335 When adding code that transitions from Thumb to Arm the instruction that
2336 should be used for the alignment padding should be 0xe7fd (b .-2) instead of
2337 a nop for performance reasons. */
2338
7801f98f
CL		 2339/* ARM FDPIC PLT entry. */
2340/* The last 5 words contain PLT lazy fragment code and data. */
2341static const bfd_vma elf32_arm_fdpic_plt_entry [] =
2342 {
2343 0xe59fc008, /* ldr r12, .L1 */
2344 0xe08cc009, /* add r12, r12, r9 */
2345 0xe59c9004, /* ldr r9, [r12, #4] */
2346 0xe59cf000, /* ldr pc, [r12] */
2347 0x00000000, /* L1. .word foo(GOTOFFFUNCDESC) */
2348 0x00000000, /* L1. .word foo(funcdesc_value_reloc_offset) */
2349 0xe51fc00c, /* ldr r12, [pc, #-12] */
2350 0xe92d1000, /* push {r12} */
2351 0xe599c004, /* ldr r12, [r9, #4] */
2352 0xe599f000, /* ldr pc, [r9] */
2353 };
2354
59029f57
CL		 2355/* Thumb FDPIC PLT entry. */
2356/* The last 5 words contain PLT lazy fragment code and data. */
2357static const bfd_vma elf32_arm_fdpic_thumb_plt_entry [] =
2358 {
2359 0xc00cf8df, /* ldr.w r12, .L1 */
2360 0x0c09eb0c, /* add.w r12, r12, r9 */
2361 0x9004f8dc, /* ldr.w r9, [r12, #4] */
2362 0xf000f8dc, /* ldr.w pc, [r12] */
2363 0x00000000, /* .L1 .word foo(GOTOFFFUNCDESC) */
2364 0x00000000, /* .L2 .word foo(funcdesc_value_reloc_offset) */
2365 0xc008f85f, /* ldr.w r12, .L2 */
2366 0xcd04f84d, /* push {r12} */
2367 0xc004f8d9, /* ldr.w r12, [r9, #4] */
2368 0xf000f8d9, /* ldr.w pc, [r9] */
2369 };
2370
5e681ec4
PB		 2371#ifdef FOUR_WORD_PLT
2372
252b5132
RH		 2373/* The first entry in a procedure linkage table looks like
2374 this. It is set up so that any shared library function that is
59f2c4e7 2375 called before the relocation has been set up calls the dynamic
9b485d32 2376 linker first. */
e5a52504 2377static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2378{
2379 0xe52de004, /* str lr, [sp, #-4]! */
2380 0xe59fe010, /* ldr lr, [pc, #16] */
2381 0xe08fe00e, /* add lr, pc, lr */
2382 0xe5bef008, /* ldr pc, [lr, #8]! */
2383};
5e681ec4
PB		 2384
2385/* Subsequent entries in a procedure linkage table look like
2386 this. */
e5a52504 2387static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2388{
2389 0xe28fc600, /* add ip, pc, #NN */
2390 0xe28cca00, /* add ip, ip, #NN */
2391 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2392 0x00000000, /* unused */
2393};
5e681ec4 2394
eed94f8f 2395#else /* not FOUR_WORD_PLT */
5e681ec4 2396
5e681ec4
PB		 2397/* The first entry in a procedure linkage table looks like
2398 this. It is set up so that any shared library function that is
2399 called before the relocation has been set up calls the dynamic
2400 linker first. */
e5a52504 2401static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb 2402{
07d6d2b8
AM		 2403 0xe52de004, /* str lr, [sp, #-4]! */
2404 0xe59fe004, /* ldr lr, [pc, #4] */
2405 0xe08fe00e, /* add lr, pc, lr */
2406 0xe5bef008, /* ldr pc, [lr, #8]! */
2407 0x00000000, /* &GOT[0] - . */
b38cadfb 2408};
252b5132 2409
1db37fe6
YG		 2410/* By default subsequent entries in a procedure linkage table look like
2411 this. Offsets that don't fit into 28 bits will cause link error. */
2412static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2413{
2414 0xe28fc600, /* add ip, pc, #0xNN00000 */
2415 0xe28cca00, /* add ip, ip, #0xNN000 */
2416 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2417};
5e681ec4 2418
1db37fe6
YG		 2419/* When explicitly asked, we'll use this "long" entry format
2420 which can cope with arbitrary displacements. */
2421static const bfd_vma elf32_arm_plt_entry_long [] =
2422{
07d6d2b8
AM		 2423 0xe28fc200, /* add ip, pc, #0xN0000000 */
2424 0xe28cc600, /* add ip, ip, #0xNN00000 */
1db37fe6
YG		 2425 0xe28cca00, /* add ip, ip, #0xNN000 */
2426 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2427};
2428
2429static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2430
eed94f8f
NC		 2431#endif /* not FOUR_WORD_PLT */
2432
2433/* The first entry in a procedure linkage table looks like this.
2434 It is set up so that any shared library function that is called before the
2435 relocation has been set up calls the dynamic linker first. */
2436static const bfd_vma elf32_thumb2_plt0_entry [] =
2437{
2438 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2439 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2440 0xf8dfb500, /* push {lr} */
2441 0x44fee008, /* ldr.w lr, [pc, #8] */
2442 /* add lr, pc */
eed94f8f 2443 0xff08f85e, /* ldr.w pc, [lr, #8]! */
07d6d2b8 2444 0x00000000, /* &GOT[0] - . */
eed94f8f
NC		 2445};
2446
2447/* Subsequent entries in a procedure linkage table for thumb only target
2448 look like this. */
2449static const bfd_vma elf32_thumb2_plt_entry [] =
2450{
2451 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2452 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2453 0x0c00f240, /* movw ip, #0xNNNN */
2454 0x0c00f2c0, /* movt ip, #0xNNNN */
2455 0xf8dc44fc, /* add ip, pc */
b4e87f2c
TC		 2456 0xe7fdf000 /* ldr.w pc, [ip] */
2457 /* b .-2 */
eed94f8f 2458};
252b5132 2459
00a97672
RS		 2460/* The format of the first entry in the procedure linkage table
2461 for a VxWorks executable. */
2462static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb 2463{
07d6d2b8
AM		 2464 0xe52dc008, /* str ip,[sp,#-8]! */
2465 0xe59fc000, /* ldr ip,[pc] */
2466 0xe59cf008, /* ldr pc,[ip,#8] */
2467 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
b38cadfb 2468};
00a97672
RS		 2469
2470/* The format of subsequent entries in a VxWorks executable. */
2471static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb 2472{
07d6d2b8
AM		 2473 0xe59fc000, /* ldr ip,[pc] */
2474 0xe59cf000, /* ldr pc,[ip] */
2475 0x00000000, /* .long @got */
2476 0xe59fc000, /* ldr ip,[pc] */
2477 0xea000000, /* b _PLT */
2478 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2479};
00a97672
RS		 2480
2481/* The format of entries in a VxWorks shared library. */
2482static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb 2483{
07d6d2b8
AM		 2484 0xe59fc000, /* ldr ip,[pc] */
2485 0xe79cf009, /* ldr pc,[ip,r9] */
2486 0x00000000, /* .long @got */
2487 0xe59fc000, /* ldr ip,[pc] */
2488 0xe599f008, /* ldr pc,[r9,#8] */
2489 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2490};
00a97672 2491
b7693d02
DJ		 2492/* An initial stub used if the PLT entry is referenced from Thumb code. */
2493#define PLT_THUMB_STUB_SIZE 4
2494static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2495{
2496 0x4778, /* bx pc */
b4e87f2c 2497 0xe7fd /* b .-2 */
b38cadfb 2498};
b7693d02 2499
e5a52504
MM		 2500/* The entries in a PLT when using a DLL-based target with multiple
2501 address spaces. */
906e58ca 2502static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb 2503{
07d6d2b8
AM		 2504 0xe51ff004, /* ldr pc, [pc, #-4] */
2505 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
b38cadfb
NC		 2506};
2507
2508/* The first entry in a procedure linkage table looks like
2509 this. It is set up so that any shared library function that is
2510 called before the relocation has been set up calls the dynamic
2511 linker first. */
2512static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2513{
2514 /* First bundle: */
2515 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2516 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2517 0xe08cc00f, /* add ip, ip, pc */
2518 0xe52dc008, /* str ip, [sp, #-8]! */
2519 /* Second bundle: */
edccdf7c
RM		 2520 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2521 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2522 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2523 0xe12fff1c, /* bx ip */
b38cadfb 2524 /* Third bundle: */
edccdf7c
RM		 2525 0xe320f000, /* nop */
2526 0xe320f000, /* nop */
2527 0xe320f000, /* nop */
b38cadfb
NC		 2528 /* .Lplt_tail: */
2529 0xe50dc004, /* str ip, [sp, #-4] */
2530 /* Fourth bundle: */
edccdf7c
RM		 2531 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2532 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2533 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2534 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2535};
2536#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2537
2538/* Subsequent entries in a procedure linkage table look like this. */
2539static const bfd_vma elf32_arm_nacl_plt_entry [] =
2540{
2541 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2542 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2543 0xe08cc00f, /* add ip, ip, pc */
2544 0xea000000, /* b .Lplt_tail */
2545};
e5a52504 2546
906e58ca
NC		 2547#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2548#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2549#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2550#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2551#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2552#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2553#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2554#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2555
461a49ca 2556enum stub_insn_type
b38cadfb
NC		 2557{
2558 THUMB16_TYPE = 1,
2559 THUMB32_TYPE,
2560 ARM_TYPE,
2561 DATA_TYPE
2562};
461a49ca 2563
48229727
JB		 2564#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2565/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2566 is inserted in arm_build_one_stub(). */
2567#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2568#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2569#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2570#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2571#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2572#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2573#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2574#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2575
2576typedef struct
2577{
07d6d2b8 2578 bfd_vma data;
b38cadfb 2579 enum stub_insn_type type;
07d6d2b8
AM		 2580 unsigned int r_type;
2581 int reloc_addend;
461a49ca
DJ		 2582} insn_sequence;
2583
b4e87f2c
TC		 2584/* See note [Thumb nop sequence] when adding a veneer. */
2585
fea2b4d6
CL		 2586/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2587 to reach the stub if necessary. */
461a49ca 2588static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb 2589{
07d6d2b8 2590 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2591 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2592};
906e58ca 2593
fea2b4d6
CL		 2594/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2595 available. */
461a49ca 2596static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb 2597{
07d6d2b8
AM		 2598 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2599 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2600 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2601};
906e58ca 2602
d3626fb0 2603/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2604static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb 2605{
07d6d2b8
AM		 2606 THUMB16_INSN (0xb401), /* push {r0} */
2607 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2608 THUMB16_INSN (0x4684), /* mov ip, r0 */
2609 THUMB16_INSN (0xbc01), /* pop {r0} */
2610 THUMB16_INSN (0x4760), /* bx ip */
2611 THUMB16_INSN (0xbf00), /* nop */
b38cadfb
NC		 2612 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2613};
906e58ca 2614
80c135e5
TP		 2615/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2616static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2617{
07d6d2b8 2618 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
80c135e5
TP		 2619 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2620};
2621
d5a67c02
AV		 2622/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2623 M-profile architectures. */
2624static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2625{
2626 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2627 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
07d6d2b8 2628 THUMB16_INSN (0x4760), /* bx ip */
d5a67c02
AV		 2629};
2630
d3626fb0
CL		 2631/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2632 allowed. */
2633static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb 2634{
07d6d2b8 2635 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2636 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2637 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2638 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2639 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2640};
d3626fb0 2641
fea2b4d6
CL		 2642/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2643 available. */
461a49ca 2644static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb 2645{
07d6d2b8 2646 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2647 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8 2648 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2649 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2650};
906e58ca 2651
fea2b4d6
CL		 2652/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2653 one, when the destination is close enough. */
461a49ca 2654static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb 2655{
07d6d2b8 2656 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2657 THUMB16_INSN (0xe7fd), /* b .-2 */
b38cadfb
NC		 2658 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2659};
c820be07 2660
cf3eccff 2661/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2662 blx to reach the stub if necessary. */
cf3eccff 2663static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb 2664{
07d6d2b8
AM		 2665 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2666 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
b38cadfb
NC		 2667 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2668};
906e58ca 2669
cf3eccff
DJ		 2670/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2671 blx to reach the stub if necessary. We can not add into pc;
2672 it is not guaranteed to mode switch (different in ARMv6 and
2673 ARMv7). */
2674static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb 2675{
07d6d2b8
AM		 2676 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2677 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2678 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2679 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2680};
cf3eccff 2681
ebe24dd4
CL		 2682/* V4T ARM -> ARM long branch stub, PIC. */
2683static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb 2684{
07d6d2b8
AM		 2685 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2686 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2687 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2688 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2689};
ebe24dd4
CL		 2690
2691/* V4T Thumb -> ARM long branch stub, PIC. */
2692static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb 2693{
07d6d2b8 2694 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2695 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2696 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2697 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
b38cadfb
NC		 2698 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2699};
ebe24dd4 2700
d3626fb0
CL		 2701/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2702 architectures. */
ebe24dd4 2703static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb 2704{
07d6d2b8
AM		 2705 THUMB16_INSN (0xb401), /* push {r0} */
2706 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2707 THUMB16_INSN (0x46fc), /* mov ip, pc */
2708 THUMB16_INSN (0x4484), /* add ip, r0 */
2709 THUMB16_INSN (0xbc01), /* pop {r0} */
2710 THUMB16_INSN (0x4760), /* bx ip */
b38cadfb
NC		 2711 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2712};
ebe24dd4 2713
d3626fb0
CL		 2714/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2715 allowed. */
2716static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb 2717{
07d6d2b8 2718 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2719 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2720 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2721 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2722 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2723 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2724};
d3626fb0 2725
0855e32b
NS		 2726/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2727 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2728static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2729{
07d6d2b8
AM		 2730 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2731 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
b38cadfb 2732 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2733};
2734
2735/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2736 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2737static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2738{
07d6d2b8 2739 THUMB16_INSN (0x4778), /* bx pc */
b4e87f2c 2740 THUMB16_INSN (0xe7fd), /* b .-2 */
07d6d2b8
AM		 2741 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2742 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
b38cadfb 2743 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2744};
2745
7a89b94e
NC		 2746/* NaCl ARM -> ARM long branch stub. */
2747static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2748{
2749 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2750 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2751 ARM_INSN (0xe12fff1c), /* bx ip */
2752 ARM_INSN (0xe320f000), /* nop */
2753 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2754 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2755 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2756 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2757};
2758
2759/* NaCl ARM -> ARM long branch stub, PIC. */
2760static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2761{
2762 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
07d6d2b8 2763 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
7a89b94e 2764 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2765 ARM_INSN (0xe12fff1c), /* bx ip */
2766 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2767 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2768 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2769 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2770};
2771
4ba2ef8f
TP		 2772/* Stub used for transition to secure state (aka SG veneer). */
2773static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2774{
2775 THUMB32_INSN (0xe97fe97f), /* sg. */
2776 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2777};
2778
7a89b94e 2779
48229727
JB		 2780/* Cortex-A8 erratum-workaround stubs. */
2781
2782/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2783 can't use a conditional branch to reach this stub). */
2784
2785static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb 2786{
07d6d2b8 2787 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
b38cadfb
NC		 2788 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2789 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2790};
48229727
JB		 2791
2792/* Stub used for b.w and bl.w instructions. */
2793
2794static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2795{
2796 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2797};
48229727
JB		 2798
2799static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2800{
2801 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2802};
48229727
JB		 2803
2804/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2805 instruction (which switches to ARM mode) to point to this stub. Jump to the
2806 real destination using an ARM-mode branch. */
2807
2808static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2809{
2810 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2811};
48229727 2812
9553db3c
NC		 2813/* For each section group there can be a specially created linker section
2814 to hold the stubs for that group. The name of the stub section is based
2815 upon the name of another section within that group with the suffix below
2816 applied.
2817
2818 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2819 create what appeared to be a linker stub section when it actually
2820 contained user code/data. For example, consider this fragment:
b38cadfb 2821
9553db3c
NC		 2822 const char * stubborn_problems[] = { "np" };
2823
2824 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2825 section called:
2826
2827 .data.rel.local.stubborn_problems
2828
2829 This then causes problems in arm32_arm_build_stubs() as it triggers:
2830
2831 // Ignore non-stub sections.
2832 if (!strstr (stub_sec->name, STUB_SUFFIX))
2833 continue;
2834
2835 And so the section would be ignored instead of being processed. Hence
2836 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2837 C identifier. */
2838#define STUB_SUFFIX ".__stub"
906e58ca 2839
738a79f6
CL		 2840/* One entry per long/short branch stub defined above. */
2841#define DEF_STUBS \
2842 DEF_STUB(long_branch_any_any) \
2843 DEF_STUB(long_branch_v4t_arm_thumb) \
2844 DEF_STUB(long_branch_thumb_only) \
2845 DEF_STUB(long_branch_v4t_thumb_thumb) \
2846 DEF_STUB(long_branch_v4t_thumb_arm) \
2847 DEF_STUB(short_branch_v4t_thumb_arm) \
2848 DEF_STUB(long_branch_any_arm_pic) \
2849 DEF_STUB(long_branch_any_thumb_pic) \
2850 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2851 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2852 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2853 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2854 DEF_STUB(long_branch_any_tls_pic) \
2855 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2856 DEF_STUB(long_branch_arm_nacl) \
2857 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2858 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2859 DEF_STUB(a8_veneer_b_cond) \
2860 DEF_STUB(a8_veneer_b) \
2861 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2862 DEF_STUB(a8_veneer_blx) \
2863 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2864 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2865
2866#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2867enum elf32_arm_stub_type
2868{
906e58ca 2869 arm_stub_none,
738a79f6 2870 DEF_STUBS
4f4faa4d 2871 max_stub_type
738a79f6
CL		 2872};
2873#undef DEF_STUB
2874
8d9d9490
TP		 2875/* Note the first a8_veneer type. */
2876const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2877
738a79f6
CL		 2878typedef struct
2879{
d3ce72d0 2880 const insn_sequence* template_sequence;
738a79f6
CL		 2881 int template_size;
2882} stub_def;
2883
2884#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2885static const stub_def stub_definitions[] =
2886{
738a79f6
CL		 2887 {NULL, 0},
2888 DEF_STUBS
906e58ca
NC		 2889};
2890
2891struct elf32_arm_stub_hash_entry
2892{
2893 /* Base hash table entry structure. */
2894 struct bfd_hash_entry root;
2895
2896 /* The stub section. */
2897 asection *stub_sec;
2898
2899 /* Offset within stub_sec of the beginning of this stub. */
2900 bfd_vma stub_offset;
2901
2902 /* Given the symbol's value and its section we can determine its final
2903 value when building the stubs (so the stub knows where to jump). */
2904 bfd_vma target_value;
2905 asection *target_section;
2906
8d9d9490
TP		 2907 /* Same as above but for the source of the branch to the stub. Used for
2908 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2909 such, source section does not need to be recorded since Cortex-A8 erratum
2910 workaround stubs are only generated when both source and target are in the
2911 same section. */
2912 bfd_vma source_value;
48229727
JB		 2913
2914 /* The instruction which caused this stub to be generated (only valid for
2915 Cortex-A8 erratum workaround stubs at present). */
2916 unsigned long orig_insn;
2917
461a49ca 2918 /* The stub type. */
906e58ca 2919 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2920 /* Its encoding size in bytes. */
2921 int stub_size;
2922 /* Its template. */
2923 const insn_sequence *stub_template;
2924 /* The size of the template (number of entries). */
2925 int stub_template_size;
906e58ca
NC		 2926
2927 /* The symbol table entry, if any, that this was derived from. */
2928 struct elf32_arm_link_hash_entry *h;
2929
35fc36a8
RS		 2930 /* Type of branch. */
2931 enum arm_st_branch_type branch_type;
906e58ca
NC		 2932
2933 /* Where this stub is being called from, or, in the case of combined
2934 stub sections, the first input section in the group. */
2935 asection *id_sec;
7413f23f
DJ		 2936
2937 /* The name for the local symbol at the start of this stub. The
2938 stub name in the hash table has to be unique; this does not, so
2939 it can be friendlier. */
2940 char *output_name;
906e58ca
NC		 2941};
2942
e489d0ae
PB		 2943/* Used to build a map of a section. This is required for mixed-endian
2944 code/data. */
2945
2946typedef struct elf32_elf_section_map
2947{
2948 bfd_vma vma;
2949 char type;
2950}
2951elf32_arm_section_map;
2952
c7b8f16e
JB		 2953/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2954
2955typedef enum
2956{
2957 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2958 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2959 VFP11_ERRATUM_ARM_VENEER,
2960 VFP11_ERRATUM_THUMB_VENEER
2961}
2962elf32_vfp11_erratum_type;
2963
2964typedef struct elf32_vfp11_erratum_list
2965{
2966 struct elf32_vfp11_erratum_list *next;
2967 bfd_vma vma;
2968 union
2969 {
2970 struct
2971 {
2972 struct elf32_vfp11_erratum_list *veneer;
2973 unsigned int vfp_insn;
2974 } b;
2975 struct
2976 {
2977 struct elf32_vfp11_erratum_list *branch;
2978 unsigned int id;
2979 } v;
2980 } u;
2981 elf32_vfp11_erratum_type type;
2982}
2983elf32_vfp11_erratum_list;
2984
a504d23a
LA		 2985/* Information about a STM32L4XX erratum veneer, or a branch to such a
2986 veneer. */
2987typedef enum
2988{
2989 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2990 STM32L4XX_ERRATUM_VENEER
2991}
2992elf32_stm32l4xx_erratum_type;
2993
2994typedef struct elf32_stm32l4xx_erratum_list
2995{
2996 struct elf32_stm32l4xx_erratum_list *next;
2997 bfd_vma vma;
2998 union
2999 {
3000 struct
3001 {
3002 struct elf32_stm32l4xx_erratum_list *veneer;
3003 unsigned int insn;
3004 } b;
3005 struct
3006 {
3007 struct elf32_stm32l4xx_erratum_list *branch;
3008 unsigned int id;
3009 } v;
3010 } u;
3011 elf32_stm32l4xx_erratum_type type;
3012}
3013elf32_stm32l4xx_erratum_list;
3014
2468f9c9
PB		 3015typedef enum
3016{
3017 DELETE_EXIDX_ENTRY,
3018 INSERT_EXIDX_CANTUNWIND_AT_END
3019}
3020arm_unwind_edit_type;
3021
3022/* A (sorted) list of edits to apply to an unwind table. */
3023typedef struct arm_unwind_table_edit
3024{
3025 arm_unwind_edit_type type;
3026 /* Note: we sometimes want to insert an unwind entry corresponding to a
3027 section different from the one we're currently writing out, so record the
3028 (text) section this edit relates to here. */
3029 asection *linked_section;
3030 unsigned int index;
3031 struct arm_unwind_table_edit *next;
3032}
3033arm_unwind_table_edit;
3034
8e3de13a 3035typedef struct _arm_elf_section_data
e489d0ae 3036{
2468f9c9 3037 /* Information about mapping symbols. */
e489d0ae 3038 struct bfd_elf_section_data elf;
8e3de13a 3039 unsigned int mapcount;
c7b8f16e 3040 unsigned int mapsize;
e489d0ae 3041 elf32_arm_section_map *map;
2468f9c9 3042 /* Information about CPU errata. */
c7b8f16e
JB		 3043 unsigned int erratumcount;
3044 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 3045 unsigned int stm32l4xx_erratumcount;
3046 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 3047 unsigned int additional_reloc_count;
2468f9c9
PB		 3048 /* Information about unwind tables. */
3049 union
3050 {
3051 /* Unwind info attached to a text section. */
3052 struct
3053 {
3054 asection *arm_exidx_sec;
3055 } text;
3056
3057 /* Unwind info attached to an .ARM.exidx section. */
3058 struct
3059 {
3060 arm_unwind_table_edit *unwind_edit_list;
3061 arm_unwind_table_edit *unwind_edit_tail;
3062 } exidx;
3063 } u;
8e3de13a
NC		 3064}
3065_arm_elf_section_data;
e489d0ae
PB		 3066
3067#define elf32_arm_section_data(sec) \
8e3de13a 3068 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 3069
48229727
JB		 3070/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3071 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3072 so may be created multiple times: we use an array of these entries whilst
3073 relaxing which we can refresh easily, then create stubs for each potentially
3074 erratum-triggering instruction once we've settled on a solution. */
3075
b38cadfb
NC		 3076struct a8_erratum_fix
3077{
48229727
JB		 3078 bfd *input_bfd;
3079 asection *section;
3080 bfd_vma offset;
8d9d9490 3081 bfd_vma target_offset;
48229727
JB		 3082 unsigned long orig_insn;
3083 char *stub_name;
3084 enum elf32_arm_stub_type stub_type;
35fc36a8 3085 enum arm_st_branch_type branch_type;
48229727
JB		 3086};
3087
3088/* A table of relocs applied to branches which might trigger Cortex-A8
3089 erratum. */
3090
b38cadfb
NC		 3091struct a8_erratum_reloc
3092{
48229727
JB		 3093 bfd_vma from;
3094 bfd_vma destination;
92750f34
DJ		 3095 struct elf32_arm_link_hash_entry *hash;
3096 const char *sym_name;
48229727 3097 unsigned int r_type;
35fc36a8 3098 enum arm_st_branch_type branch_type;
48229727
JB		 3099 bfd_boolean non_a8_stub;
3100};
3101
ba93b8ac
DJ		 3102/* The size of the thread control block. */
3103#define TCB_SIZE 8
3104
34e77a92
RS		 3105/* ARM-specific information about a PLT entry, over and above the usual
3106 gotplt_union. */
b38cadfb
NC		 3107struct arm_plt_info
3108{
34e77a92
RS		 3109 /* We reference count Thumb references to a PLT entry separately,
3110 so that we can emit the Thumb trampoline only if needed. */
3111 bfd_signed_vma thumb_refcount;
3112
3113 /* Some references from Thumb code may be eliminated by BL->BLX
3114 conversion, so record them separately. */
3115 bfd_signed_vma maybe_thumb_refcount;
3116
3117 /* How many of the recorded PLT accesses were from non-call relocations.
3118 This information is useful when deciding whether anything takes the
3119 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3120 non-call references to the function should resolve directly to the
3121 real runtime target. */
3122 unsigned int noncall_refcount;
3123
3124 /* Since PLT entries have variable size if the Thumb prologue is
3125 used, we need to record the index into .got.plt instead of
3126 recomputing it from the PLT offset. */
3127 bfd_signed_vma got_offset;
3128};
3129
3130/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 3131struct arm_local_iplt_info
3132{
34e77a92
RS		 3133 /* The information that is usually found in the generic ELF part of
3134 the hash table entry. */
3135 union gotplt_union root;
3136
3137 /* The information that is usually found in the ARM-specific part of
3138 the hash table entry. */
3139 struct arm_plt_info arm;
3140
3141 /* A list of all potential dynamic relocations against this symbol. */
3142 struct elf_dyn_relocs *dyn_relocs;
3143};
3144
e8b09b87
CL		 3145/* Structure to handle FDPIC support for local functions. */
3146struct fdpic_local {
3147 unsigned int funcdesc_cnt;
3148 unsigned int gotofffuncdesc_cnt;
3149 int funcdesc_offset;
3150};
3151
0ffa91dd 3152struct elf_arm_obj_tdata
ba93b8ac
DJ		 3153{
3154 struct elf_obj_tdata root;
3155
3156 /* tls_type for each local got entry. */
3157 char *local_got_tls_type;
ee065d83 3158
0855e32b
NS		 3159 /* GOTPLT entries for TLS descriptors. */
3160 bfd_vma *local_tlsdesc_gotent;
3161
34e77a92
RS		 3162 /* Information for local symbols that need entries in .iplt. */
3163 struct arm_local_iplt_info **local_iplt;
3164
bf21ed78
MS		 3165 /* Zero to warn when linking objects with incompatible enum sizes. */
3166 int no_enum_size_warning;
a9dc9481
JM		 3167
3168 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3169 int no_wchar_size_warning;
e8b09b87
CL		 3170
3171 /* Maintains FDPIC counters and funcdesc info. */
3172 struct fdpic_local *local_fdpic_cnts;
ba93b8ac
DJ		 3173};
3174
0ffa91dd
NC		 3175#define elf_arm_tdata(bfd) \
3176 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 3177
0ffa91dd
NC		 3178#define elf32_arm_local_got_tls_type(bfd) \
3179 (elf_arm_tdata (bfd)->local_got_tls_type)
3180
0855e32b
NS		 3181#define elf32_arm_local_tlsdesc_gotent(bfd) \
3182 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3183
34e77a92
RS		 3184#define elf32_arm_local_iplt(bfd) \
3185 (elf_arm_tdata (bfd)->local_iplt)
3186
e8b09b87
CL		 3187#define elf32_arm_local_fdpic_cnts(bfd) \
3188 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3189
0ffa91dd
NC		 3190#define is_arm_elf(bfd) \
3191 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3192 && elf_tdata (bfd) != NULL \
4dfe6ac6 3193 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 3194
3195static bfd_boolean
3196elf32_arm_mkobject (bfd *abfd)
3197{
0ffa91dd 3198 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 3199 ARM_ELF_DATA);
ba93b8ac
DJ		 3200}
3201
ba93b8ac
DJ		 3202#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3203
e8b09b87
CL		 3204/* Structure to handle FDPIC support for extern functions. */
3205struct fdpic_global {
3206 unsigned int gotofffuncdesc_cnt;
3207 unsigned int gotfuncdesc_cnt;
3208 unsigned int funcdesc_cnt;
3209 int funcdesc_offset;
3210 int gotfuncdesc_offset;
3211};
3212
ba96a88f 3213/* Arm ELF linker hash entry. */
252b5132 3214struct elf32_arm_link_hash_entry
b38cadfb
NC		 3215{
3216 struct elf_link_hash_entry root;
252b5132 3217
b38cadfb
NC		 3218 /* Track dynamic relocs copied for this symbol. */
3219 struct elf_dyn_relocs *dyn_relocs;
b7693d02 3220
b38cadfb
NC		 3221 /* ARM-specific PLT information. */
3222 struct arm_plt_info plt;
ba93b8ac
DJ		 3223
3224#define GOT_UNKNOWN 0
3225#define GOT_NORMAL 1
3226#define GOT_TLS_GD 2
3227#define GOT_TLS_IE 4
0855e32b
NS		 3228#define GOT_TLS_GDESC 8
3229#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3230 unsigned int tls_type : 8;
34e77a92 3231
b38cadfb
NC		 3232 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3233 unsigned int is_iplt : 1;
34e77a92 3234
b38cadfb 3235 unsigned int unused : 23;
a4fd1a8e 3236
b38cadfb
NC		 3237 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3238 starting at the end of the jump table. */
3239 bfd_vma tlsdesc_got;
0855e32b 3240
b38cadfb
NC		 3241 /* The symbol marking the real symbol location for exported thumb
3242 symbols with Arm stubs. */
3243 struct elf_link_hash_entry *export_glue;
906e58ca 3244
b38cadfb 3245 /* A pointer to the most recently used stub hash entry against this
8029a119 3246 symbol. */
b38cadfb 3247 struct elf32_arm_stub_hash_entry *stub_cache;
e8b09b87
CL		 3248
3249 /* Counter for FDPIC relocations against this symbol. */
3250 struct fdpic_global fdpic_cnts;
b38cadfb 3251};
252b5132 3252
252b5132 3253/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3254#define elf32_arm_link_hash_traverse(table, func, info) \
3255 (elf_link_hash_traverse \
3256 (&(table)->root, \
b7693d02 3257 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3258 (info)))
3259
3260/* Get the ARM elf linker hash table from a link_info structure. */
3261#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3262 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3263 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3264
906e58ca
NC		 3265#define arm_stub_hash_lookup(table, string, create, copy) \
3266 ((struct elf32_arm_stub_hash_entry *) \
3267 bfd_hash_lookup ((table), (string), (create), (copy)))
3268
21d799b5
NC		 3269/* Array to keep track of which stub sections have been created, and
3270 information on stub grouping. */
3271struct map_stub
3272{
3273 /* This is the section to which stubs in the group will be
3274 attached. */
3275 asection *link_sec;
3276 /* The stub section. */
3277 asection *stub_sec;
3278};
3279
0855e32b
NS		 3280#define elf32_arm_compute_jump_table_size(htab) \
3281 ((htab)->next_tls_desc_index * 4)
3282
9b485d32 3283/* ARM ELF linker hash table. */
252b5132 3284struct elf32_arm_link_hash_table
906e58ca
NC		 3285{
3286 /* The main hash table. */
3287 struct elf_link_hash_table root;
252b5132 3288
906e58ca
NC		 3289 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3290 bfd_size_type thumb_glue_size;
252b5132 3291
906e58ca
NC		 3292 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3293 bfd_size_type arm_glue_size;
252b5132 3294
906e58ca
NC		 3295 /* The size in bytes of section containing the ARMv4 BX veneers. */
3296 bfd_size_type bx_glue_size;
845b51d6 3297
906e58ca
NC		 3298 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3299 veneer has been populated. */
3300 bfd_vma bx_glue_offset[15];
845b51d6 3301
906e58ca
NC		 3302 /* The size in bytes of the section containing glue for VFP11 erratum
3303 veneers. */
3304 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3305
a504d23a
LA		 3306 /* The size in bytes of the section containing glue for STM32L4XX erratum
3307 veneers. */
3308 bfd_size_type stm32l4xx_erratum_glue_size;
3309
48229727
JB		 3310 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3311 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3312 elf32_arm_write_section(). */
3313 struct a8_erratum_fix *a8_erratum_fixes;
3314 unsigned int num_a8_erratum_fixes;
3315
906e58ca
NC		 3316 /* An arbitrary input BFD chosen to hold the glue sections. */
3317 bfd * bfd_of_glue_owner;
ba96a88f 3318
906e58ca
NC		 3319 /* Nonzero to output a BE8 image. */
3320 int byteswap_code;
e489d0ae 3321
906e58ca
NC		 3322 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3323 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3324 int target1_is_rel;
9c504268 3325
906e58ca
NC		 3326 /* The relocation to use for R_ARM_TARGET2 relocations. */
3327 int target2_reloc;
eb043451 3328
906e58ca
NC		 3329 /* 0 = Ignore R_ARM_V4BX.
3330 1 = Convert BX to MOV PC.
3331 2 = Generate v4 interworing stubs. */
3332 int fix_v4bx;
319850b4 3333
48229727
JB		 3334 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3335 int fix_cortex_a8;
3336
2de70689
MGD		 3337 /* Whether we should fix the ARM1176 BLX immediate issue. */
3338 int fix_arm1176;
3339
906e58ca
NC		 3340 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3341 int use_blx;
33bfe774 3342
906e58ca
NC		 3343 /* What sort of code sequences we should look for which may trigger the
3344 VFP11 denorm erratum. */
3345 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3346
906e58ca
NC		 3347 /* Global counter for the number of fixes we have emitted. */
3348 int num_vfp11_fixes;
c7b8f16e 3349
a504d23a
LA		 3350 /* What sort of code sequences we should look for which may trigger the
3351 STM32L4XX erratum. */
3352 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3353
3354 /* Global counter for the number of fixes we have emitted. */
3355 int num_stm32l4xx_fixes;
3356
906e58ca
NC		 3357 /* Nonzero to force PIC branch veneers. */
3358 int pic_veneer;
27e55c4d 3359
906e58ca
NC		 3360 /* The number of bytes in the initial entry in the PLT. */
3361 bfd_size_type plt_header_size;
e5a52504 3362
906e58ca
NC		 3363 /* The number of bytes in the subsequent PLT etries. */
3364 bfd_size_type plt_entry_size;
e5a52504 3365
906e58ca
NC		 3366 /* True if the target system is VxWorks. */
3367 int vxworks_p;
00a97672 3368
906e58ca
NC		 3369 /* True if the target system is Symbian OS. */
3370 int symbian_p;
e5a52504 3371
b38cadfb
NC		 3372 /* True if the target system is Native Client. */
3373 int nacl_p;
3374
906e58ca 3375 /* True if the target uses REL relocations. */
f3185997 3376 bfd_boolean use_rel;
4e7fd91e 3377
54ddd295
TP		 3378 /* Nonzero if import library must be a secure gateway import library
3379 as per ARMv8-M Security Extensions. */
3380 int cmse_implib;
3381
0955507f
TP		 3382 /* The import library whose symbols' address must remain stable in
3383 the import library generated. */
3384 bfd *in_implib_bfd;
3385
0855e32b
NS		 3386 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3387 bfd_vma next_tls_desc_index;
3388
3389 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3390 bfd_vma num_tls_desc;
3391
906e58ca
NC		 3392 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3393 asection *srelplt2;
00a97672 3394
0855e32b
NS		 3395 /* The offset into splt of the PLT entry for the TLS descriptor
3396 resolver. Special values are 0, if not necessary (or not found
3397 to be necessary yet), and -1 if needed but not determined
3398 yet. */
3399 bfd_vma dt_tlsdesc_plt;
3400
3401 /* The offset into sgot of the GOT entry used by the PLT entry
3402 above. */
b38cadfb 3403 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3404
3405 /* Offset in .plt section of tls_arm_trampoline. */
3406 bfd_vma tls_trampoline;
3407
5c5a4843 3408 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
906e58ca
NC		 3409 union
3410 {
3411 bfd_signed_vma refcount;
3412 bfd_vma offset;
3413 } tls_ldm_got;
b7693d02 3414
87d72d41
AM		 3415 /* Small local sym cache. */
3416 struct sym_cache sym_cache;
906e58ca
NC		 3417
3418 /* For convenience in allocate_dynrelocs. */
3419 bfd * obfd;
3420
0855e32b
NS		 3421 /* The amount of space used by the reserved portion of the sgotplt
3422 section, plus whatever space is used by the jump slots. */
3423 bfd_vma sgotplt_jump_table_size;
3424
906e58ca
NC		 3425 /* The stub hash table. */
3426 struct bfd_hash_table stub_hash_table;
3427
3428 /* Linker stub bfd. */
3429 bfd *stub_bfd;
3430
3431 /* Linker call-backs. */
6bde4c52
TP		 3432 asection * (*add_stub_section) (const char *, asection *, asection *,
3433 unsigned int);
906e58ca
NC		 3434 void (*layout_sections_again) (void);
3435
3436 /* Array to keep track of which stub sections have been created, and
3437 information on stub grouping. */
21d799b5 3438 struct map_stub *stub_group;
906e58ca 3439
4ba2ef8f
TP		 3440 /* Input stub section holding secure gateway veneers. */
3441 asection *cmse_stub_sec;
3442
0955507f
TP		 3443 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3444 start to be allocated. */
3445 bfd_vma new_cmse_stub_offset;
3446
fe33d2fa 3447 /* Number of elements in stub_group. */
7292b3ac 3448 unsigned int top_id;
fe33d2fa 3449
906e58ca
NC		 3450 /* Assorted information used by elf32_arm_size_stubs. */
3451 unsigned int bfd_count;
7292b3ac 3452 unsigned int top_index;
906e58ca 3453 asection **input_list;
617a5ada
CL		 3454
3455 /* True if the target system uses FDPIC. */
3456 int fdpic_p;
e8b09b87
CL		 3457
3458 /* Fixup section. Used for FDPIC. */
3459 asection *srofixup;
906e58ca 3460};
252b5132 3461
e8b09b87
CL		 3462/* Add an FDPIC read-only fixup. */
3463static void
3464arm_elf_add_rofixup (bfd *output_bfd, asection *srofixup, bfd_vma offset)
3465{
3466 bfd_vma fixup_offset;
3467
3468 fixup_offset = srofixup->reloc_count++ * 4;
3469 BFD_ASSERT (fixup_offset < srofixup->size);
3470 bfd_put_32 (output_bfd, offset, srofixup->contents + fixup_offset);
3471}
3472
a504d23a
LA		 3473static inline int
3474ctz (unsigned int mask)
3475{
3476#if GCC_VERSION >= 3004
3477 return __builtin_ctz (mask);
3478#else
3479 unsigned int i;
3480
3481 for (i = 0; i < 8 * sizeof (mask); i++)
3482 {
3483 if (mask & 0x1)
3484 break;
3485 mask = (mask >> 1);
3486 }
3487 return i;
3488#endif
3489}
3490
3491static inline int
b25e998d 3492elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3493{
3494#if GCC_VERSION >= 3004
3495 return __builtin_popcount (mask);
3496#else
b25e998d
CG		 3497 unsigned int i;
3498 int sum = 0;
a504d23a
LA		 3499
3500 for (i = 0; i < 8 * sizeof (mask); i++)
3501 {
3502 if (mask & 0x1)
3503 sum++;
3504 mask = (mask >> 1);
3505 }
3506 return sum;
3507#endif
3508}
3509
e8b09b87
CL		 3510static void elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
3511 asection *sreloc, Elf_Internal_Rela *rel);
3512
3513static void
3514arm_elf_fill_funcdesc(bfd *output_bfd,
3515 struct bfd_link_info *info,
3516 int *funcdesc_offset,
3517 int dynindx,
3518 int offset,
3519 bfd_vma addr,
3520 bfd_vma dynreloc_value,
3521 bfd_vma seg)
3522{
3523 if ((*funcdesc_offset & 1) == 0)
3524 {
3525 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
3526 asection *sgot = globals->root.sgot;
3527
3528 if (bfd_link_pic(info))
3529 {
3530 asection *srelgot = globals->root.srelgot;
3531 Elf_Internal_Rela outrel;
3532
3533 outrel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
3534 outrel.r_offset = sgot->output_section->vma + sgot->output_offset + offset;
3535 outrel.r_addend = 0;
3536
3537 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
3538 bfd_put_32 (output_bfd, addr, sgot->contents + offset);
3539 bfd_put_32 (output_bfd, seg, sgot->contents + offset + 4);
3540 }
3541 else
3542 {
3543 struct elf_link_hash_entry *hgot = globals->root.hgot;
3544 bfd_vma got_value = hgot->root.u.def.value
3545 + hgot->root.u.def.section->output_section->vma
3546 + hgot->root.u.def.section->output_offset;
3547
3548 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3549 sgot->output_section->vma + sgot->output_offset
3550 + offset);
3551 arm_elf_add_rofixup(output_bfd, globals->srofixup,
3552 sgot->output_section->vma + sgot->output_offset
3553 + offset + 4);
3554 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + offset);
3555 bfd_put_32 (output_bfd, got_value, sgot->contents + offset + 4);
3556 }
3557 *funcdesc_offset |= 1;
3558 }
3559}
3560
780a67af
NC		 3561/* Create an entry in an ARM ELF linker hash table. */
3562
3563static struct bfd_hash_entry *
57e8b36a 3564elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3565 struct bfd_hash_table * table,
3566 const char * string)
780a67af
NC		 3567{
3568 struct elf32_arm_link_hash_entry * ret =
3569 (struct elf32_arm_link_hash_entry *) entry;
3570
3571 /* Allocate the structure if it has not already been allocated by a
3572 subclass. */
906e58ca 3573 if (ret == NULL)
21d799b5 3574 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3575 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3576 if (ret == NULL)
780a67af
NC		 3577 return (struct bfd_hash_entry *) ret;
3578
3579 /* Call the allocation method of the superclass. */
3580 ret = ((struct elf32_arm_link_hash_entry *)
3581 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3582 table, string));
57e8b36a 3583 if (ret != NULL)
b7693d02 3584 {
0bdcacaf 3585 ret->dyn_relocs = NULL;
ba93b8ac 3586 ret->tls_type = GOT_UNKNOWN;
0855e32b 3587 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3588 ret->plt.thumb_refcount = 0;
3589 ret->plt.maybe_thumb_refcount = 0;
3590 ret->plt.noncall_refcount = 0;
3591 ret->plt.got_offset = -1;
3592 ret->is_iplt = FALSE;
a4fd1a8e 3593 ret->export_glue = NULL;
906e58ca
NC		 3594
3595 ret->stub_cache = NULL;
e8b09b87
CL		 3596
3597 ret->fdpic_cnts.gotofffuncdesc_cnt = 0;
3598 ret->fdpic_cnts.gotfuncdesc_cnt = 0;
3599 ret->fdpic_cnts.funcdesc_cnt = 0;
3600 ret->fdpic_cnts.funcdesc_offset = -1;
3601 ret->fdpic_cnts.gotfuncdesc_offset = -1;
b7693d02 3602 }
780a67af
NC		 3603
3604 return (struct bfd_hash_entry *) ret;
3605}
3606
34e77a92
RS		 3607/* Ensure that we have allocated bookkeeping structures for ABFD's local
3608 symbols. */
3609
3610static bfd_boolean
3611elf32_arm_allocate_local_sym_info (bfd *abfd)
3612{
3613 if (elf_local_got_refcounts (abfd) == NULL)
3614 {
3615 bfd_size_type num_syms;
3616 bfd_size_type size;
3617 char *data;
3618
3619 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3620 size = num_syms * (sizeof (bfd_signed_vma)
3621 + sizeof (struct arm_local_iplt_info *)
3622 + sizeof (bfd_vma)
e8b09b87
CL		 3623 + sizeof (char)
3624 + sizeof (struct fdpic_local));
34e77a92
RS		 3625 data = bfd_zalloc (abfd, size);
3626 if (data == NULL)
3627 return FALSE;
3628
e8b09b87
CL		 3629 elf32_arm_local_fdpic_cnts (abfd) = (struct fdpic_local *) data;
3630 data += num_syms * sizeof (struct fdpic_local);
3631
34e77a92
RS		 3632 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3633 data += num_syms * sizeof (bfd_signed_vma);
3634
3635 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3636 data += num_syms * sizeof (struct arm_local_iplt_info *);
3637
3638 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3639 data += num_syms * sizeof (bfd_vma);
3640
3641 elf32_arm_local_got_tls_type (abfd) = data;
3642 }
3643 return TRUE;
3644}
3645
3646/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3647 to input bfd ABFD. Create the information if it doesn't already exist.
3648 Return null if an allocation fails. */
3649
3650static struct arm_local_iplt_info *
3651elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3652{
3653 struct arm_local_iplt_info **ptr;
3654
3655 if (!elf32_arm_allocate_local_sym_info (abfd))
3656 return NULL;
3657
3658 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3659 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3660 if (*ptr == NULL)
3661 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3662 return *ptr;
3663}
3664
3665/* Try to obtain PLT information for the symbol with index R_SYMNDX
3666 in ABFD's symbol table. If the symbol is global, H points to its
3667 hash table entry, otherwise H is null.
3668
3669 Return true if the symbol does have PLT information. When returning
3670 true, point *ROOT_PLT at the target-independent reference count/offset
3671 union and *ARM_PLT at the ARM-specific information. */
3672
3673static bfd_boolean
4ba2ef8f
TP		 3674elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3675 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3676 unsigned long r_symndx, union gotplt_union **root_plt,
3677 struct arm_plt_info **arm_plt)
3678{
3679 struct arm_local_iplt_info *local_iplt;
3680
4ba2ef8f
TP		 3681 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3682 return FALSE;
3683
34e77a92
RS		 3684 if (h != NULL)
3685 {
3686 *root_plt = &h->root.plt;
3687 *arm_plt = &h->plt;
3688 return TRUE;
3689 }
3690
3691 if (elf32_arm_local_iplt (abfd) == NULL)
3692 return FALSE;
3693
3694 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3695 if (local_iplt == NULL)
3696 return FALSE;
3697
3698 *root_plt = &local_iplt->root;
3699 *arm_plt = &local_iplt->arm;
3700 return TRUE;
3701}
3702
59029f57
CL		 3703static bfd_boolean using_thumb_only (struct elf32_arm_link_hash_table *globals);
3704
34e77a92
RS		 3705/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3706 before it. */
3707
3708static bfd_boolean
3709elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3710 struct arm_plt_info *arm_plt)
3711{
3712 struct elf32_arm_link_hash_table *htab;
3713
3714 htab = elf32_arm_hash_table (info);
59029f57
CL		 3715
3716 return (!using_thumb_only(htab) && (arm_plt->thumb_refcount != 0
3717 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0)));
34e77a92
RS		 3718}
3719
3720/* Return a pointer to the head of the dynamic reloc list that should
3721 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3722 ABFD's symbol table. Return null if an error occurs. */
3723
3724static struct elf_dyn_relocs **
3725elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3726 Elf_Internal_Sym *isym)
3727{
3728 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3729 {
3730 struct arm_local_iplt_info *local_iplt;
3731
3732 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3733 if (local_iplt == NULL)
3734 return NULL;
3735 return &local_iplt->dyn_relocs;
3736 }
3737 else
3738 {
3739 /* Track dynamic relocs needed for local syms too.
3740 We really need local syms available to do this
3741 easily. Oh well. */
3742 asection *s;
3743 void *vpp;
3744
3745 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3746 if (s == NULL)
3747 abort ();
3748
3749 vpp = &elf_section_data (s)->local_dynrel;
3750 return (struct elf_dyn_relocs **) vpp;
3751 }
3752}
3753
906e58ca
NC		 3754/* Initialize an entry in the stub hash table. */
3755
3756static struct bfd_hash_entry *
3757stub_hash_newfunc (struct bfd_hash_entry *entry,
3758 struct bfd_hash_table *table,
3759 const char *string)
3760{
3761 /* Allocate the structure if it has not already been allocated by a
3762 subclass. */
3763 if (entry == NULL)
3764 {
21d799b5 3765 entry = (struct bfd_hash_entry *)
99059e56 3766 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3767 if (entry == NULL)
3768 return entry;
3769 }
3770
3771 /* Call the allocation method of the superclass. */
3772 entry = bfd_hash_newfunc (entry, table, string);
3773 if (entry != NULL)
3774 {
3775 struct elf32_arm_stub_hash_entry *eh;
3776
3777 /* Initialize the local fields. */
3778 eh = (struct elf32_arm_stub_hash_entry *) entry;
3779 eh->stub_sec = NULL;
0955507f 3780 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3781 eh->source_value = 0;
906e58ca
NC		 3782 eh->target_value = 0;
3783 eh->target_section = NULL;
cedfb179 3784 eh->orig_insn = 0;
906e58ca 3785 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3786 eh->stub_size = 0;
3787 eh->stub_template = NULL;
0955507f 3788 eh->stub_template_size = -1;
906e58ca
NC		 3789 eh->h = NULL;
3790 eh->id_sec = NULL;
d8d2f433 3791 eh->output_name = NULL;
906e58ca
NC		 3792 }
3793
3794 return entry;
3795}
3796
00a97672 3797/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3798 shortcuts to them in our hash table. */
3799
3800static bfd_boolean
57e8b36a 3801create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3802{
3803 struct elf32_arm_link_hash_table *htab;
3804
e5a52504 3805 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3806 if (htab == NULL)
3807 return FALSE;
3808
e5a52504
MM		 3809 /* BPABI objects never have a GOT, or associated sections. */
3810 if (htab->symbian_p)
3811 return TRUE;
3812
5e681ec4
PB		 3813 if (! _bfd_elf_create_got_section (dynobj, info))
3814 return FALSE;
3815
e8b09b87
CL		 3816 /* Also create .rofixup. */
3817 if (htab->fdpic_p)
3818 {
3819 htab->srofixup = bfd_make_section_with_flags (dynobj, ".rofixup",
3820 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS
3821 | SEC_IN_MEMORY | SEC_LINKER_CREATED | SEC_READONLY));
fd361982
AM		 3822 if (htab->srofixup == NULL
3823 || !bfd_set_section_alignment (htab->srofixup, 2))
e8b09b87
CL		 3824 return FALSE;
3825 }
3826
5e681ec4
PB		 3827 return TRUE;
3828}
3829
34e77a92
RS		 3830/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3831
3832static bfd_boolean
3833create_ifunc_sections (struct bfd_link_info *info)
3834{
3835 struct elf32_arm_link_hash_table *htab;
3836 const struct elf_backend_data *bed;
3837 bfd *dynobj;
3838 asection *s;
3839 flagword flags;
b38cadfb 3840
34e77a92
RS		 3841 htab = elf32_arm_hash_table (info);
3842 dynobj = htab->root.dynobj;
3843 bed = get_elf_backend_data (dynobj);
3844 flags = bed->dynamic_sec_flags;
3845
3846 if (htab->root.iplt == NULL)
3847 {
3d4d4302
AM		 3848 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3849 flags | SEC_READONLY | SEC_CODE);
34e77a92 3850 if (s == NULL
fd361982 3851 || !bfd_set_section_alignment (s, bed->plt_alignment))
34e77a92
RS		 3852 return FALSE;
3853 htab->root.iplt = s;
3854 }
3855
3856 if (htab->root.irelplt == NULL)
3857 {
3d4d4302
AM		 3858 s = bfd_make_section_anyway_with_flags (dynobj,
3859 RELOC_SECTION (htab, ".iplt"),
3860 flags | SEC_READONLY);
34e77a92 3861 if (s == NULL
fd361982 3862 || !bfd_set_section_alignment (s, bed->s->log_file_align))
34e77a92
RS		 3863 return FALSE;
3864 htab->root.irelplt = s;
3865 }
3866
3867 if (htab->root.igotplt == NULL)
3868 {
3d4d4302 3869 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92 3870 if (s == NULL
fd361982 3871 || !bfd_set_section_alignment (s, bed->s->log_file_align))
34e77a92
RS		 3872 return FALSE;
3873 htab->root.igotplt = s;
3874 }
3875 return TRUE;
3876}
3877
eed94f8f
NC		 3878/* Determine if we're dealing with a Thumb only architecture. */
3879
3880static bfd_boolean
3881using_thumb_only (struct elf32_arm_link_hash_table *globals)
3882{
2fd158eb
TP		 3883 int arch;
3884 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3885 Tag_CPU_arch_profile);
eed94f8f 3886
2fd158eb
TP		 3887 if (profile)
3888 return profile == 'M';
eed94f8f 3889
2fd158eb 3890 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3891
60a019a0 3892 /* Force return logic to be reviewed for each new architecture. */
031254f2 3893 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0 3894
2fd158eb
TP		 3895 if (arch == TAG_CPU_ARCH_V6_M
3896 || arch == TAG_CPU_ARCH_V6S_M
3897 || arch == TAG_CPU_ARCH_V7E_M
3898 || arch == TAG_CPU_ARCH_V8M_BASE
031254f2
AV		 3899 || arch == TAG_CPU_ARCH_V8M_MAIN
3900 || arch == TAG_CPU_ARCH_V8_1M_MAIN)
2fd158eb 3901 return TRUE;
eed94f8f 3902
2fd158eb 3903 return FALSE;
eed94f8f
NC		 3904}
3905
3906/* Determine if we're dealing with a Thumb-2 object. */
3907
3908static bfd_boolean
3909using_thumb2 (struct elf32_arm_link_hash_table *globals)
3910{
60a019a0
TP		 3911 int arch;
3912 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3913 Tag_THUMB_ISA_use);
3914
3915 if (thumb_isa)
3916 return thumb_isa == 2;
3917
3918 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3919
3920 /* Force return logic to be reviewed for each new architecture. */
031254f2 3921 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 3922
3923 return (arch == TAG_CPU_ARCH_V6T2
3924 || arch == TAG_CPU_ARCH_V7
3925 || arch == TAG_CPU_ARCH_V7E_M
3926 || arch == TAG_CPU_ARCH_V8
bff0500d 3927 || arch == TAG_CPU_ARCH_V8R
031254f2
AV		 3928 || arch == TAG_CPU_ARCH_V8M_MAIN
3929 || arch == TAG_CPU_ARCH_V8_1M_MAIN);
eed94f8f
NC		 3930}
3931
5e866f5a
TP		 3932/* Determine whether Thumb-2 BL instruction is available. */
3933
3934static bfd_boolean
3935using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3936{
3937 int arch =
3938 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3939
3940 /* Force return logic to be reviewed for each new architecture. */
031254f2 3941 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
5e866f5a
TP		 3942
3943 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3944 return (arch == TAG_CPU_ARCH_V6T2
3945 || arch >= TAG_CPU_ARCH_V7);
3946}
3947
00a97672
RS		 3948/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3949 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3950 hash table. */
3951
3952static bfd_boolean
57e8b36a 3953elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3954{
3955 struct elf32_arm_link_hash_table *htab;
3956
3957 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3958 if (htab == NULL)
3959 return FALSE;
3960
362d30a1 3961 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3962 return FALSE;
3963
3964 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3965 return FALSE;
3966
00a97672
RS		 3967 if (htab->vxworks_p)
3968 {
3969 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3970 return FALSE;
3971
0e1862bb 3972 if (bfd_link_pic (info))
00a97672
RS		 3973 {
3974 htab->plt_header_size = 0;
3975 htab->plt_entry_size
3976 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3977 }
3978 else
3979 {
3980 htab->plt_header_size
3981 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3982 htab->plt_entry_size
3983 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3984 }
aebf9be7
NC		 3985
3986 if (elf_elfheader (dynobj))
3987 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3988 }
eed94f8f
NC		 3989 else
3990 {
3991 /* PR ld/16017
3992 Test for thumb only architectures. Note - we cannot just call
3993 using_thumb_only() as the attributes in the output bfd have not been
3994 initialised at this point, so instead we use the input bfd. */
3995 bfd * saved_obfd = htab->obfd;
3996
3997 htab->obfd = dynobj;
3998 if (using_thumb_only (htab))
3999 {
4000 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
4001 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
4002 }
4003 htab->obfd = saved_obfd;
4004 }
5e681ec4 4005
7801f98f
CL		 4006 if (htab->fdpic_p) {
4007 htab->plt_header_size = 0;
4008 if (info->flags & DF_BIND_NOW)
4009 htab->plt_entry_size = 4 * (ARRAY_SIZE(elf32_arm_fdpic_plt_entry) - 5);
4010 else
4011 htab->plt_entry_size = 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry);
4012 }
4013
362d30a1
RS		 4014 if (!htab->root.splt
4015 || !htab->root.srelplt
9d19e4fd
AM		 4016 || !htab->root.sdynbss
4017 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 4018 abort ();
4019
4020 return TRUE;
4021}
4022
906e58ca
NC		 4023/* Copy the extra info we tack onto an elf_link_hash_entry. */
4024
4025static void
4026elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
4027 struct elf_link_hash_entry *dir,
4028 struct elf_link_hash_entry *ind)
4029{
4030 struct elf32_arm_link_hash_entry *edir, *eind;
4031
4032 edir = (struct elf32_arm_link_hash_entry *) dir;
4033 eind = (struct elf32_arm_link_hash_entry *) ind;
4034
0bdcacaf 4035 if (eind->dyn_relocs != NULL)
906e58ca 4036 {
0bdcacaf 4037 if (edir->dyn_relocs != NULL)
906e58ca 4038 {
0bdcacaf
RS		 4039 struct elf_dyn_relocs **pp;
4040 struct elf_dyn_relocs *p;
906e58ca
NC		 4041
4042 /* Add reloc counts against the indirect sym to the direct sym
4043 list. Merge any entries against the same section. */
0bdcacaf 4044 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 4045 {
0bdcacaf 4046 struct elf_dyn_relocs *q;
906e58ca 4047
0bdcacaf
RS		 4048 for (q = edir->dyn_relocs; q != NULL; q = q->next)
4049 if (q->sec == p->sec)
906e58ca
NC		 4050 {
4051 q->pc_count += p->pc_count;
4052 q->count += p->count;
4053 *pp = p->next;
4054 break;
4055 }
4056 if (q == NULL)
4057 pp = &p->next;
4058 }
0bdcacaf 4059 *pp = edir->dyn_relocs;
906e58ca
NC		 4060 }
4061
0bdcacaf
RS		 4062 edir->dyn_relocs = eind->dyn_relocs;
4063 eind->dyn_relocs = NULL;
906e58ca
NC		 4064 }
4065
4066 if (ind->root.type == bfd_link_hash_indirect)
4067 {
4068 /* Copy over PLT info. */
34e77a92
RS		 4069 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
4070 eind->plt.thumb_refcount = 0;
4071 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
4072 eind->plt.maybe_thumb_refcount = 0;
4073 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
4074 eind->plt.noncall_refcount = 0;
4075
e8b09b87
CL		 4076 /* Copy FDPIC counters. */
4077 edir->fdpic_cnts.gotofffuncdesc_cnt += eind->fdpic_cnts.gotofffuncdesc_cnt;
4078 edir->fdpic_cnts.gotfuncdesc_cnt += eind->fdpic_cnts.gotfuncdesc_cnt;
4079 edir->fdpic_cnts.funcdesc_cnt += eind->fdpic_cnts.funcdesc_cnt;
4080
34e77a92
RS		 4081 /* We should only allocate a function to .iplt once the final
4082 symbol information is known. */
4083 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 4084
4085 if (dir->got.refcount <= 0)
4086 {
4087 edir->tls_type = eind->tls_type;
4088 eind->tls_type = GOT_UNKNOWN;
4089 }
4090 }
4091
4092 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
4093}
4094
68faa637
AM		 4095/* Destroy an ARM elf linker hash table. */
4096
4097static void
d495ab0d 4098elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 4099{
4100 struct elf32_arm_link_hash_table *ret
d495ab0d 4101 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 4102
4103 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 4104 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 4105}
4106
906e58ca
NC		 4107/* Create an ARM elf linker hash table. */
4108
4109static struct bfd_link_hash_table *
4110elf32_arm_link_hash_table_create (bfd *abfd)
4111{
4112 struct elf32_arm_link_hash_table *ret;
986f0783 4113 size_t amt = sizeof (struct elf32_arm_link_hash_table);
906e58ca 4114
7bf52ea2 4115 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 4116 if (ret == NULL)
4117 return NULL;
4118
4119 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
4120 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 4121 sizeof (struct elf32_arm_link_hash_entry),
4122 ARM_ELF_DATA))
906e58ca
NC		 4123 {
4124 free (ret);
4125 return NULL;
4126 }
4127
906e58ca 4128 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 4129 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 4130#ifdef FOUR_WORD_PLT
4131 ret->plt_header_size = 16;
4132 ret->plt_entry_size = 16;
4133#else
4134 ret->plt_header_size = 20;
1db37fe6 4135 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 4136#endif
f3185997 4137 ret->use_rel = TRUE;
906e58ca 4138 ret->obfd = abfd;
617a5ada 4139 ret->fdpic_p = 0;
906e58ca
NC		 4140
4141 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
4142 sizeof (struct elf32_arm_stub_hash_entry)))
4143 {
d495ab0d 4144 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 4145 return NULL;
4146 }
d495ab0d 4147 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 4148
4149 return &ret->root.root;
4150}
4151
cd1dac3d
DG		 4152/* Determine what kind of NOPs are available. */
4153
4154static bfd_boolean
4155arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
4156{
4157 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
4158 Tag_CPU_arch);
cd1dac3d 4159
60a019a0 4160 /* Force return logic to be reviewed for each new architecture. */
031254f2 4161 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
60a019a0
TP		 4162
4163 return (arch == TAG_CPU_ARCH_V6T2
4164 || arch == TAG_CPU_ARCH_V6K
4165 || arch == TAG_CPU_ARCH_V7
bff0500d
TP		 4166 || arch == TAG_CPU_ARCH_V8
4167 || arch == TAG_CPU_ARCH_V8R);
cd1dac3d
DG		 4168}
4169
f4ac8484
DJ		 4170static bfd_boolean
4171arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
4172{
4173 switch (stub_type)
4174 {
fea2b4d6 4175 case arm_stub_long_branch_thumb_only:
80c135e5 4176 case arm_stub_long_branch_thumb2_only:
d5a67c02 4177 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 4178 case arm_stub_long_branch_v4t_thumb_arm:
4179 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 4180 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 4181 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 4182 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 4183 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 4184 return TRUE;
4185 case arm_stub_none:
4186 BFD_FAIL ();
4187 return FALSE;
4188 break;
4189 default:
4190 return FALSE;
4191 }
4192}
4193
906e58ca
NC		 4194/* Determine the type of stub needed, if any, for a call. */
4195
4196static enum elf32_arm_stub_type
4197arm_type_of_stub (struct bfd_link_info *info,
4198 asection *input_sec,
4199 const Elf_Internal_Rela *rel,
34e77a92 4200 unsigned char st_type,
35fc36a8 4201 enum arm_st_branch_type *actual_branch_type,
906e58ca 4202 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 4203 bfd_vma destination,
4204 asection *sym_sec,
4205 bfd *input_bfd,
4206 const char *name)
906e58ca
NC		 4207{
4208 bfd_vma location;
4209 bfd_signed_vma branch_offset;
4210 unsigned int r_type;
4211 struct elf32_arm_link_hash_table * globals;
5e866f5a 4212 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 4213 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 4214 int use_plt = 0;
35fc36a8 4215 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 4216 union gotplt_union *root_plt;
4217 struct arm_plt_info *arm_plt;
d5a67c02
AV		 4218 int arch;
4219 int thumb2_movw;
906e58ca 4220
35fc36a8 4221 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 4222 return stub_type;
4223
906e58ca 4224 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4225 if (globals == NULL)
4226 return stub_type;
906e58ca
NC		 4227
4228 thumb_only = using_thumb_only (globals);
906e58ca 4229 thumb2 = using_thumb2 (globals);
5e866f5a 4230 thumb2_bl = using_thumb2_bl (globals);
906e58ca 4231
d5a67c02
AV		 4232 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
4233
4234 /* True for architectures that implement the thumb2 movw instruction. */
4235 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
4236
906e58ca
NC		 4237 /* Determine where the call point is. */
4238 location = (input_sec->output_offset
4239 + input_sec->output_section->vma
4240 + rel->r_offset);
4241
906e58ca
NC		 4242 r_type = ELF32_R_TYPE (rel->r_info);
4243
39f21624
NC		 4244 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4245 are considering a function call relocation. */
c5423981 4246 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
07d6d2b8 4247 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 4248 && branch_type == ST_BRANCH_TO_ARM)
4249 branch_type = ST_BRANCH_TO_THUMB;
4250
34e77a92
RS		 4251 /* For TLS call relocs, it is the caller's responsibility to provide
4252 the address of the appropriate trampoline. */
4253 if (r_type != R_ARM_TLS_CALL
4254 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 4255 && elf32_arm_get_plt_info (input_bfd, globals, hash,
4256 ELF32_R_SYM (rel->r_info), &root_plt,
4257 &arm_plt)
34e77a92 4258 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 4259 {
34e77a92 4260 asection *splt;
fe33d2fa 4261
34e77a92
RS		 4262 if (hash == NULL || hash->is_iplt)
4263 splt = globals->root.iplt;
4264 else
4265 splt = globals->root.splt;
4266 if (splt != NULL)
b38cadfb 4267 {
34e77a92
RS		 4268 use_plt = 1;
4269
4270 /* Note when dealing with PLT entries: the main PLT stub is in
4271 ARM mode, so if the branch is in Thumb mode, another
4272 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 4273 PLT stub. If a long branch stub is needed, we'll add a
4274 Thumb->Arm one and branch directly to the ARM PLT entry.
4275 Here, we have to check if a pre-PLT Thumb->ARM stub
4276 is needed and if it will be close enough. */
34e77a92
RS		 4277
4278 destination = (splt->output_section->vma
4279 + splt->output_offset
4280 + root_plt->offset);
4281 st_type = STT_FUNC;
2df2751d
CL		 4282
4283 /* Thumb branch/call to PLT: it can become a branch to ARM
4284 or to Thumb. We must perform the same checks and
4285 corrections as in elf32_arm_final_link_relocate. */
4286 if ((r_type == R_ARM_THM_CALL)
4287 || (r_type == R_ARM_THM_JUMP24))
4288 {
4289 if (globals->use_blx
4290 && r_type == R_ARM_THM_CALL
4291 && !thumb_only)
4292 {
4293 /* If the Thumb BLX instruction is available, convert
4294 the BL to a BLX instruction to call the ARM-mode
4295 PLT entry. */
4296 branch_type = ST_BRANCH_TO_ARM;
4297 }
4298 else
4299 {
4300 if (!thumb_only)
4301 /* Target the Thumb stub before the ARM PLT entry. */
4302 destination -= PLT_THUMB_STUB_SIZE;
4303 branch_type = ST_BRANCH_TO_THUMB;
4304 }
4305 }
4306 else
4307 {
4308 branch_type = ST_BRANCH_TO_ARM;
4309 }
34e77a92 4310 }
5fa9e92f 4311 }
34e77a92
RS		 4312 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4313 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 4314
fe33d2fa
CL		 4315 branch_offset = (bfd_signed_vma)(destination - location);
4316
0855e32b 4317 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 4318 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 4319 {
5fa9e92f
CL		 4320 /* Handle cases where:
4321 - this call goes too far (different Thumb/Thumb2 max
99059e56 4322 distance)
155d87d7 4323 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 4324 Thumb->Arm branch (not bl). A stub is needed in this case,
4325 but only if this call is not through a PLT entry. Indeed,
695344c0 4326 PLT stubs handle mode switching already. */
5e866f5a 4327 if ((!thumb2_bl
906e58ca
NC		 4328 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
4329 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 4330 || (thumb2_bl
906e58ca
NC		 4331 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4332 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 4333 || (thumb2
4334 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4335 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4336 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 4337 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 4338 && (((r_type == R_ARM_THM_CALL
4339 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981 4340 || (r_type == R_ARM_THM_JUMP24)
07d6d2b8 4341 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4342 && !use_plt))
906e58ca 4343 {
2df2751d
CL		 4344 /* If we need to insert a Thumb-Thumb long branch stub to a
4345 PLT, use one that branches directly to the ARM PLT
4346 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4347 stub, undo this now. */
695344c0
NC		 4348 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4349 {
4350 branch_type = ST_BRANCH_TO_ARM;
4351 branch_offset += PLT_THUMB_STUB_SIZE;
4352 }
2df2751d 4353
35fc36a8 4354 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4355 {
4356 /* Thumb to thumb. */
4357 if (!thumb_only)
4358 {
d5a67c02 4359 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4360 _bfd_error_handler
871b3ab2 4361 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4362 " section with SHF_ARM_PURECODE section"
4363 " attribute is only supported for M-profile"
90b6238f 4364 " targets that implement the movw instruction"),
10463f39 4365 input_bfd, input_sec);
d5a67c02 4366
0e1862bb 4367 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4368 /* PIC stubs. */
155d87d7 4369 ? ((globals->use_blx
9553db3c 4370 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4371 /* V5T and above. Stub starts with ARM code, so
4372 we must be able to switch mode before
4373 reaching it, which is only possible for 'bl'
4374 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4375 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4376 /* On V4T, use Thumb code only. */
d3626fb0 4377 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4378
4379 /* non-PIC stubs. */
155d87d7 4380 : ((globals->use_blx
9553db3c 4381 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4382 /* V5T and above. */
4383 ? arm_stub_long_branch_any_any
4384 /* V4T. */
d3626fb0 4385 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4386 }
4387 else
4388 {
d5a67c02
AV		 4389 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4390 stub_type = arm_stub_long_branch_thumb2_only_pure;
4391 else
4392 {
4393 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4394 _bfd_error_handler
871b3ab2 4395 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4396 " section with SHF_ARM_PURECODE section"
4397 " attribute is only supported for M-profile"
90b6238f 4398 " targets that implement the movw instruction"),
10463f39 4399 input_bfd, input_sec);
d5a67c02
AV		 4400
4401 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4402 /* PIC stub. */
4403 ? arm_stub_long_branch_thumb_only_pic
4404 /* non-PIC stub. */
4405 : (thumb2 ? arm_stub_long_branch_thumb2_only
4406 : arm_stub_long_branch_thumb_only);
4407 }
906e58ca
NC		 4408 }
4409 }
4410 else
4411 {
d5a67c02 4412 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4413 _bfd_error_handler
871b3ab2 4414 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4415 " section with SHF_ARM_PURECODE section"
4416 " attribute is only supported" " for M-profile"
90b6238f 4417 " targets that implement the movw instruction"),
10463f39 4418 input_bfd, input_sec);
d5a67c02 4419
906e58ca 4420 /* Thumb to arm. */
c820be07
NC		 4421 if (sym_sec != NULL
4422 && sym_sec->owner != NULL
4423 && !INTERWORK_FLAG (sym_sec->owner))
4424 {
4eca0228 4425 _bfd_error_handler
90b6238f
AM		 4426 (_("%pB(%s): warning: interworking not enabled;"
4427 " first occurrence: %pB: %s call to %s"),
4428 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
c820be07
NC		 4429 }
4430
0855e32b 4431 stub_type =
0e1862bb 4432 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4433 /* PIC stubs. */
0855e32b 4434 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4435 /* TLS PIC stubs. */
0855e32b
NS		 4436 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4437 : arm_stub_long_branch_v4t_thumb_tls_pic)
4438 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4439 /* V5T PIC and above. */
4440 ? arm_stub_long_branch_any_arm_pic
4441 /* V4T PIC stub. */
4442 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4443
4444 /* non-PIC stubs. */
0855e32b 4445 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4446 /* V5T and above. */
4447 ? arm_stub_long_branch_any_any
4448 /* V4T. */
4449 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4450
4451 /* Handle v4t short branches. */
fea2b4d6 4452 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4453 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4454 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4455 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4456 }
4457 }
4458 }
fe33d2fa
CL		 4459 else if (r_type == R_ARM_CALL
4460 || r_type == R_ARM_JUMP24
0855e32b
NS		 4461 || r_type == R_ARM_PLT32
4462 || r_type == R_ARM_TLS_CALL)
906e58ca 4463 {
d5a67c02 4464 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4465 _bfd_error_handler
871b3ab2 4466 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4467 " section with SHF_ARM_PURECODE section"
4468 " attribute is only supported for M-profile"
90b6238f 4469 " targets that implement the movw instruction"),
10463f39 4470 input_bfd, input_sec);
35fc36a8 4471 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4472 {
4473 /* Arm to thumb. */
c820be07
NC		 4474
4475 if (sym_sec != NULL
4476 && sym_sec->owner != NULL
4477 && !INTERWORK_FLAG (sym_sec->owner))
4478 {
4eca0228 4479 _bfd_error_handler
90b6238f
AM		 4480 (_("%pB(%s): warning: interworking not enabled;"
4481 " first occurrence: %pB: %s call to %s"),
4482 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
c820be07
NC		 4483 }
4484
4485 /* We have an extra 2-bytes reach because of
4486 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4487 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4488 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4489 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4490 || (r_type == R_ARM_JUMP24)
4491 || (r_type == R_ARM_PLT32))
906e58ca 4492 {
0e1862bb 4493 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4494 /* PIC stubs. */
ebe24dd4
CL		 4495 ? ((globals->use_blx)
4496 /* V5T and above. */
4497 ? arm_stub_long_branch_any_thumb_pic
4498 /* V4T stub. */
4499 : arm_stub_long_branch_v4t_arm_thumb_pic)
4500
c2b4a39d
CL		 4501 /* non-PIC stubs. */
4502 : ((globals->use_blx)
4503 /* V5T and above. */
4504 ? arm_stub_long_branch_any_any
4505 /* V4T. */
4506 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4507 }
4508 }
4509 else
4510 {
4511 /* Arm to arm. */
4512 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4513 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4514 {
0855e32b 4515 stub_type =
0e1862bb 4516 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4517 /* PIC stubs. */
0855e32b 4518 ? (r_type == R_ARM_TLS_CALL
6a631e86 4519 /* TLS PIC Stub. */
0855e32b 4520 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4521 : (globals->nacl_p
4522 ? arm_stub_long_branch_arm_nacl_pic
4523 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4524 /* non-PIC stubs. */
7a89b94e
NC		 4525 : (globals->nacl_p
4526 ? arm_stub_long_branch_arm_nacl
4527 : arm_stub_long_branch_any_any);
906e58ca
NC		 4528 }
4529 }
4530 }
4531
fe33d2fa
CL		 4532 /* If a stub is needed, record the actual destination type. */
4533 if (stub_type != arm_stub_none)
35fc36a8 4534 *actual_branch_type = branch_type;
fe33d2fa 4535
906e58ca
NC		 4536 return stub_type;
4537}
4538
4539/* Build a name for an entry in the stub hash table. */
4540
4541static char *
4542elf32_arm_stub_name (const asection *input_section,
4543 const asection *sym_sec,
4544 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4545 const Elf_Internal_Rela *rel,
4546 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4547{
4548 char *stub_name;
4549 bfd_size_type len;
4550
4551 if (hash)
4552 {
fe33d2fa 4553 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4554 stub_name = (char *) bfd_malloc (len);
906e58ca 4555 if (stub_name != NULL)
fe33d2fa 4556 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4557 input_section->id & 0xffffffff,
4558 hash->root.root.root.string,
fe33d2fa
CL		 4559 (int) rel->r_addend & 0xffffffff,
4560 (int) stub_type);
906e58ca
NC		 4561 }
4562 else
4563 {
fe33d2fa 4564 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4565 stub_name = (char *) bfd_malloc (len);
906e58ca 4566 if (stub_name != NULL)
fe33d2fa 4567 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4568 input_section->id & 0xffffffff,
4569 sym_sec->id & 0xffffffff,
0855e32b
NS		 4570 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4571 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4572 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4573 (int) rel->r_addend & 0xffffffff,
4574 (int) stub_type);
906e58ca
NC		 4575 }
4576
4577 return stub_name;
4578}
4579
4580/* Look up an entry in the stub hash. Stub entries are cached because
4581 creating the stub name takes a bit of time. */
4582
4583static struct elf32_arm_stub_hash_entry *
4584elf32_arm_get_stub_entry (const asection *input_section,
4585 const asection *sym_sec,
4586 struct elf_link_hash_entry *hash,
4587 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4588 struct elf32_arm_link_hash_table *htab,
4589 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4590{
4591 struct elf32_arm_stub_hash_entry *stub_entry;
4592 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4593 const asection *id_sec;
4594
4595 if ((input_section->flags & SEC_CODE) == 0)
4596 return NULL;
4597
4d83e8d9
CL		 4598 /* If the input section is the CMSE stubs one and it needs a long
4599 branch stub to reach it's final destination, give up with an
4600 error message: this is not supported. See PR ld/24709. */
4601 if (!strncmp (input_section->name, CMSE_STUB_NAME, strlen(CMSE_STUB_NAME)))
4602 {
4603 bfd *output_bfd = htab->obfd;
4604 asection *out_sec = bfd_get_section_by_name (output_bfd, CMSE_STUB_NAME);
4605
4606 _bfd_error_handler (_("ERROR: CMSE stub (%s section) too far "
4607 "(%#" PRIx64 ") from destination (%#" PRIx64 ")"),
4608 CMSE_STUB_NAME,
4609 (uint64_t)out_sec->output_section->vma
4610 + out_sec->output_offset,
4611 (uint64_t)sym_sec->output_section->vma
4612 + sym_sec->output_offset
4613 + h->root.root.u.def.value);
4614 /* Exit, rather than leave incompletely processed
4615 relocations. */
4616 xexit(1);
4617 }
4618
906e58ca
NC		 4619 /* If this input section is part of a group of sections sharing one
4620 stub section, then use the id of the first section in the group.
4621 Stub names need to include a section id, as there may well be
4622 more than one stub used to reach say, printf, and we need to
4623 distinguish between them. */
c2abbbeb 4624 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4625 id_sec = htab->stub_group[input_section->id].link_sec;
4626
4627 if (h != NULL && h->stub_cache != NULL
4628 && h->stub_cache->h == h
fe33d2fa
CL		 4629 && h->stub_cache->id_sec == id_sec
4630 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4631 {
4632 stub_entry = h->stub_cache;
4633 }
4634 else
4635 {
4636 char *stub_name;
4637
fe33d2fa 4638 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4639 if (stub_name == NULL)
4640 return NULL;
4641
4642 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4643 stub_name, FALSE, FALSE);
4644 if (h != NULL)
4645 h->stub_cache = stub_entry;
4646
4647 free (stub_name);
4648 }
4649
4650 return stub_entry;
4651}
4652
daa4adae
TP		 4653/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4654 section. */
4655
4656static bfd_boolean
4657arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4658{
4659 if (stub_type >= max_stub_type)
4660 abort (); /* Should be unreachable. */
4661
4ba2ef8f
TP		 4662 switch (stub_type)
4663 {
4664 case arm_stub_cmse_branch_thumb_only:
4665 return TRUE;
4666
4667 default:
4668 return FALSE;
4669 }
4670
4671 abort (); /* Should be unreachable. */
daa4adae
TP		 4672}
4673
4674/* Required alignment (as a power of 2) for the dedicated section holding
4675 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4676 with input sections. */
4677
4678static int
4679arm_dedicated_stub_output_section_required_alignment
4680 (enum elf32_arm_stub_type stub_type)
4681{
4682 if (stub_type >= max_stub_type)
4683 abort (); /* Should be unreachable. */
4684
4ba2ef8f
TP		 4685 switch (stub_type)
4686 {
4687 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4688 boundary. */
4689 case arm_stub_cmse_branch_thumb_only:
4690 return 5;
4691
4692 default:
4693 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4694 return 0;
4695 }
4696
4697 abort (); /* Should be unreachable. */
daa4adae
TP		 4698}
4699
4700/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4701 NULL if veneers of this type are interspersed with input sections. */
4702
4703static const char *
4704arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4705{
4706 if (stub_type >= max_stub_type)
4707 abort (); /* Should be unreachable. */
4708
4ba2ef8f
TP		 4709 switch (stub_type)
4710 {
4711 case arm_stub_cmse_branch_thumb_only:
4d83e8d9 4712 return CMSE_STUB_NAME;
4ba2ef8f
TP		 4713
4714 default:
4715 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4716 return NULL;
4717 }
4718
4719 abort (); /* Should be unreachable. */
daa4adae
TP		 4720}
4721
4722/* If veneers of type STUB_TYPE should go in a dedicated output section,
4723 returns the address of the hash table field in HTAB holding a pointer to the
4724 corresponding input section. Otherwise, returns NULL. */
4725
4726static asection **
4ba2ef8f
TP		 4727arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4728 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4729{
4730 if (stub_type >= max_stub_type)
4731 abort (); /* Should be unreachable. */
4732
4ba2ef8f
TP		 4733 switch (stub_type)
4734 {
4735 case arm_stub_cmse_branch_thumb_only:
4736 return &htab->cmse_stub_sec;
4737
4738 default:
4739 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4740 return NULL;
4741 }
4742
4743 abort (); /* Should be unreachable. */
daa4adae
TP		 4744}
4745
4746/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4747 is the section that branch into veneer and can be NULL if stub should go in
4748 a dedicated output section. Returns a pointer to the stub section, and the
4749 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4750 LINK_SEC_P may be NULL. */
906e58ca 4751
48229727
JB		 4752static asection *
4753elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4754 struct elf32_arm_link_hash_table *htab,
4755 enum elf32_arm_stub_type stub_type)
906e58ca 4756{
daa4adae
TP		 4757 asection *link_sec, *out_sec, **stub_sec_p;
4758 const char *stub_sec_prefix;
4759 bfd_boolean dedicated_output_section =
4760 arm_dedicated_stub_output_section_required (stub_type);
4761 int align;
906e58ca 4762
daa4adae 4763 if (dedicated_output_section)
906e58ca 4764 {
daa4adae
TP		 4765 bfd *output_bfd = htab->obfd;
4766 const char *out_sec_name =
4767 arm_dedicated_stub_output_section_name (stub_type);
4768 link_sec = NULL;
4769 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4770 stub_sec_prefix = out_sec_name;
4771 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4772 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4773 if (out_sec == NULL)
906e58ca 4774 {
90b6238f 4775 _bfd_error_handler (_("no address assigned to the veneers output "
4eca0228 4776 "section %s"), out_sec_name);
daa4adae 4777 return NULL;
906e58ca 4778 }
daa4adae
TP		 4779 }
4780 else
4781 {
c2abbbeb 4782 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4783 link_sec = htab->stub_group[section->id].link_sec;
4784 BFD_ASSERT (link_sec != NULL);
4785 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4786 if (*stub_sec_p == NULL)
4787 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4788 stub_sec_prefix = link_sec->name;
4789 out_sec = link_sec->output_section;
4790 align = htab->nacl_p ? 4 : 3;
906e58ca 4791 }
b38cadfb 4792
daa4adae
TP		 4793 if (*stub_sec_p == NULL)
4794 {
4795 size_t namelen;
4796 bfd_size_type len;
4797 char *s_name;
4798
4799 namelen = strlen (stub_sec_prefix);
4800 len = namelen + sizeof (STUB_SUFFIX);
4801 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4802 if (s_name == NULL)
4803 return NULL;
4804
4805 memcpy (s_name, stub_sec_prefix, namelen);
4806 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4807 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4808 align);
4809 if (*stub_sec_p == NULL)
4810 return NULL;
4811
4812 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4813 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4814 | SEC_KEEP;
4815 }
4816
4817 if (!dedicated_output_section)
4818 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4819
48229727
JB		 4820 if (link_sec_p)
4821 *link_sec_p = link_sec;
b38cadfb 4822
daa4adae 4823 return *stub_sec_p;
48229727
JB		 4824}
4825
4826/* Add a new stub entry to the stub hash. Not all fields of the new
4827 stub entry are initialised. */
4828
4829static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4830elf32_arm_add_stub (const char *stub_name, asection *section,
4831 struct elf32_arm_link_hash_table *htab,
4832 enum elf32_arm_stub_type stub_type)
48229727
JB		 4833{
4834 asection *link_sec;
4835 asection *stub_sec;
4836 struct elf32_arm_stub_hash_entry *stub_entry;
4837
daa4adae
TP		 4838 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4839 stub_type);
48229727
JB		 4840 if (stub_sec == NULL)
4841 return NULL;
906e58ca
NC		 4842
4843 /* Enter this entry into the linker stub hash table. */
4844 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4845 TRUE, FALSE);
4846 if (stub_entry == NULL)
4847 {
6bde4c52
TP		 4848 if (section == NULL)
4849 section = stub_sec;
871b3ab2 4850 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 4851 section->owner, stub_name);
906e58ca
NC		 4852 return NULL;
4853 }
4854
4855 stub_entry->stub_sec = stub_sec;
0955507f 4856 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4857 stub_entry->id_sec = link_sec;
4858
906e58ca
NC		 4859 return stub_entry;
4860}
4861
4862/* Store an Arm insn into an output section not processed by
4863 elf32_arm_write_section. */
4864
4865static void
8029a119
NC		 4866put_arm_insn (struct elf32_arm_link_hash_table * htab,
4867 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4868{
4869 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4870 bfd_putl32 (val, ptr);
4871 else
4872 bfd_putb32 (val, ptr);
4873}
4874
4875/* Store a 16-bit Thumb insn into an output section not processed by
4876 elf32_arm_write_section. */
4877
4878static void
8029a119
NC		 4879put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4880 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4881{
4882 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4883 bfd_putl16 (val, ptr);
4884 else
4885 bfd_putb16 (val, ptr);
4886}
4887
a504d23a
LA		 4888/* Store a Thumb2 insn into an output section not processed by
4889 elf32_arm_write_section. */
4890
4891static void
4892put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4893 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4894{
4895 /* T2 instructions are 16-bit streamed. */
4896 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4897 {
4898 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4899 bfd_putl16 ((val & 0xffff), ptr + 2);
4900 }
4901 else
4902 {
4903 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4904 bfd_putb16 ((val & 0xffff), ptr + 2);
4905 }
4906}
4907
0855e32b
NS		 4908/* If it's possible to change R_TYPE to a more efficient access
4909 model, return the new reloc type. */
4910
4911static unsigned
b38cadfb 4912elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4913 struct elf_link_hash_entry *h)
4914{
4915 int is_local = (h == NULL);
4916
9cb09e33 4917 if (bfd_link_dll (info)
0e1862bb 4918 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4919 return r_type;
4920
b38cadfb 4921 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4922 switch (r_type)
4923 {
4924 case R_ARM_TLS_GOTDESC:
4925 case R_ARM_TLS_CALL:
4926 case R_ARM_THM_TLS_CALL:
4927 case R_ARM_TLS_DESCSEQ:
4928 case R_ARM_THM_TLS_DESCSEQ:
4929 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4930 }
4931
4932 return r_type;
4933}
4934
48229727
JB		 4935static bfd_reloc_status_type elf32_arm_final_link_relocate
4936 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4937 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4938 const char *, unsigned char, enum arm_st_branch_type,
4939 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4940
4563a860
JB		 4941static unsigned int
4942arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4943{
4944 switch (stub_type)
4945 {
4946 case arm_stub_a8_veneer_b_cond:
4947 case arm_stub_a8_veneer_b:
4948 case arm_stub_a8_veneer_bl:
4949 return 2;
4950
4951 case arm_stub_long_branch_any_any:
4952 case arm_stub_long_branch_v4t_arm_thumb:
4953 case arm_stub_long_branch_thumb_only:
80c135e5 4954 case arm_stub_long_branch_thumb2_only:
d5a67c02 4955 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4956 case arm_stub_long_branch_v4t_thumb_thumb:
4957 case arm_stub_long_branch_v4t_thumb_arm:
4958 case arm_stub_short_branch_v4t_thumb_arm:
4959 case arm_stub_long_branch_any_arm_pic:
4960 case arm_stub_long_branch_any_thumb_pic:
4961 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4962 case arm_stub_long_branch_v4t_arm_thumb_pic:
4963 case arm_stub_long_branch_v4t_thumb_arm_pic:
4964 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4965 case arm_stub_long_branch_any_tls_pic:
4966 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4967 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4968 case arm_stub_a8_veneer_blx:
4969 return 4;
b38cadfb 4970
7a89b94e
NC		 4971 case arm_stub_long_branch_arm_nacl:
4972 case arm_stub_long_branch_arm_nacl_pic:
4973 return 16;
4974
4563a860
JB		 4975 default:
4976 abort (); /* Should be unreachable. */
4977 }
4978}
4979
4f4faa4d
TP		 4980/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4981 veneering (TRUE) or have their own symbol (FALSE). */
4982
4983static bfd_boolean
4984arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4985{
4986 if (stub_type >= max_stub_type)
4987 abort (); /* Should be unreachable. */
4988
4ba2ef8f
TP		 4989 switch (stub_type)
4990 {
4991 case arm_stub_cmse_branch_thumb_only:
4992 return TRUE;
4993
4994 default:
4995 return FALSE;
4996 }
4997
4998 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4999}
5000
d7c5bd02
TP		 5001/* Returns the padding needed for the dedicated section used stubs of type
5002 STUB_TYPE. */
5003
5004static int
5005arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
5006{
5007 if (stub_type >= max_stub_type)
5008 abort (); /* Should be unreachable. */
5009
4ba2ef8f
TP		 5010 switch (stub_type)
5011 {
5012 case arm_stub_cmse_branch_thumb_only:
5013 return 32;
5014
5015 default:
5016 return 0;
5017 }
5018
5019 abort (); /* Should be unreachable. */
d7c5bd02
TP		 5020}
5021
0955507f
TP		 5022/* If veneers of type STUB_TYPE should go in a dedicated output section,
5023 returns the address of the hash table field in HTAB holding the offset at
5024 which new veneers should be layed out in the stub section. */
5025
5026static bfd_vma*
5027arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
5028 enum elf32_arm_stub_type stub_type)
5029{
5030 switch (stub_type)
5031 {
5032 case arm_stub_cmse_branch_thumb_only:
5033 return &htab->new_cmse_stub_offset;
5034
5035 default:
5036 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
5037 return NULL;
5038 }
5039}
5040
906e58ca
NC		 5041static bfd_boolean
5042arm_build_one_stub (struct bfd_hash_entry *gen_entry,
5043 void * in_arg)
5044{
7a89b94e 5045#define MAXRELOCS 3
0955507f 5046 bfd_boolean removed_sg_veneer;
906e58ca 5047 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 5048 struct elf32_arm_link_hash_table *globals;
906e58ca 5049 struct bfd_link_info *info;
906e58ca
NC		 5050 asection *stub_sec;
5051 bfd *stub_bfd;
906e58ca
NC		 5052 bfd_byte *loc;
5053 bfd_vma sym_value;
5054 int template_size;
5055 int size;
d3ce72d0 5056 const insn_sequence *template_sequence;
906e58ca 5057 int i;
48229727
JB		 5058 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
5059 int stub_reloc_offset[MAXRELOCS] = {0, 0};
5060 int nrelocs = 0;
0955507f 5061 int just_allocated = 0;
906e58ca
NC		 5062
5063 /* Massage our args to the form they really have. */
5064 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5065 info = (struct bfd_link_info *) in_arg;
5066
abf874aa
CL		 5067 /* Fail if the target section could not be assigned to an output
5068 section. The user should fix his linker script. */
5069 if (stub_entry->target_section->output_section == NULL
5070 && info->non_contiguous_regions)
5071 {
5072 _bfd_error_handler (_("Could not assign '%pA' to an output section. "
5073 "Retry without --enable-non-contiguous-regions.\n"),
5074 stub_entry->target_section);
5075 abort();
5076 }
5077
906e58ca 5078 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 5079 if (globals == NULL)
5080 return FALSE;
906e58ca 5081
906e58ca
NC		 5082 stub_sec = stub_entry->stub_sec;
5083
4dfe6ac6 5084 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 5085 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
5086 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 5087 return TRUE;
fe33d2fa 5088
0955507f
TP		 5089 /* Assign a slot at the end of section if none assigned yet. */
5090 if (stub_entry->stub_offset == (bfd_vma) -1)
5091 {
5092 stub_entry->stub_offset = stub_sec->size;
5093 just_allocated = 1;
5094 }
906e58ca
NC		 5095 loc = stub_sec->contents + stub_entry->stub_offset;
5096
5097 stub_bfd = stub_sec->owner;
5098
906e58ca
NC		 5099 /* This is the address of the stub destination. */
5100 sym_value = (stub_entry->target_value
5101 + stub_entry->target_section->output_offset
5102 + stub_entry->target_section->output_section->vma);
5103
d3ce72d0 5104 template_sequence = stub_entry->stub_template;
461a49ca 5105 template_size = stub_entry->stub_template_size;
906e58ca
NC		 5106
5107 size = 0;
461a49ca 5108 for (i = 0; i < template_size; i++)
906e58ca 5109 {
d3ce72d0 5110 switch (template_sequence[i].type)
461a49ca
DJ		 5111 {
5112 case THUMB16_TYPE:
48229727 5113 {
d3ce72d0
NC		 5114 bfd_vma data = (bfd_vma) template_sequence[i].data;
5115 if (template_sequence[i].reloc_addend != 0)
48229727 5116 {
99059e56
RM		 5117 /* We've borrowed the reloc_addend field to mean we should
5118 insert a condition code into this (Thumb-1 branch)
5119 instruction. See THUMB16_BCOND_INSN. */
5120 BFD_ASSERT ((data & 0xff00) == 0xd000);
5121 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 5122 }
fe33d2fa 5123 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 5124 size += 2;
5125 }
461a49ca 5126 break;
906e58ca 5127
48229727 5128 case THUMB32_TYPE:
fe33d2fa
CL		 5129 bfd_put_16 (stub_bfd,
5130 (template_sequence[i].data >> 16) & 0xffff,
5131 loc + size);
5132 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
5133 loc + size + 2);
99059e56
RM		 5134 if (template_sequence[i].r_type != R_ARM_NONE)
5135 {
5136 stub_reloc_idx[nrelocs] = i;
5137 stub_reloc_offset[nrelocs++] = size;
5138 }
5139 size += 4;
5140 break;
48229727 5141
461a49ca 5142 case ARM_TYPE:
fe33d2fa
CL		 5143 bfd_put_32 (stub_bfd, template_sequence[i].data,
5144 loc + size);
461a49ca
DJ		 5145 /* Handle cases where the target is encoded within the
5146 instruction. */
d3ce72d0 5147 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 5148 {
48229727
JB		 5149 stub_reloc_idx[nrelocs] = i;
5150 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5151 }
5152 size += 4;
5153 break;
5154
5155 case DATA_TYPE:
d3ce72d0 5156 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 5157 stub_reloc_idx[nrelocs] = i;
5158 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 5159 size += 4;
5160 break;
5161
5162 default:
5163 BFD_FAIL ();
5164 return FALSE;
5165 }
906e58ca 5166 }
461a49ca 5167
0955507f
TP		 5168 if (just_allocated)
5169 stub_sec->size += size;
906e58ca 5170
461a49ca
DJ		 5171 /* Stub size has already been computed in arm_size_one_stub. Check
5172 consistency. */
5173 BFD_ASSERT (size == stub_entry->stub_size);
5174
906e58ca 5175 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 5176 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 5177 sym_value |= 1;
5178
0955507f
TP		 5179 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5180 to relocate in each stub. */
5181 removed_sg_veneer =
5182 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5183 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 5184
48229727 5185 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 5186 {
5187 Elf_Internal_Rela rel;
5188 bfd_boolean unresolved_reloc;
5189 char *error_message;
5190 bfd_vma points_to =
5191 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
5192
5193 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
5194 rel.r_info = ELF32_R_INFO (0,
5195 template_sequence[stub_reloc_idx[i]].r_type);
5196 rel.r_addend = 0;
5197
5198 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
5199 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5200 template should refer back to the instruction after the original
5201 branch. We use target_section as Cortex-A8 erratum workaround stubs
5202 are only generated when both source and target are in the same
5203 section. */
5204 points_to = stub_entry->target_section->output_section->vma
5205 + stub_entry->target_section->output_offset
5206 + stub_entry->source_value;
5207
5208 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
5209 (template_sequence[stub_reloc_idx[i]].r_type),
5210 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
5211 points_to, info, stub_entry->target_section, "", STT_FUNC,
5212 stub_entry->branch_type,
5213 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
5214 &error_message);
5215 }
906e58ca
NC		 5216
5217 return TRUE;
48229727 5218#undef MAXRELOCS
906e58ca
NC		 5219}
5220
48229727
JB		 5221/* Calculate the template, template size and instruction size for a stub.
5222 Return value is the instruction size. */
906e58ca 5223
48229727
JB		 5224static unsigned int
5225find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
5226 const insn_sequence **stub_template,
5227 int *stub_template_size)
906e58ca 5228{
d3ce72d0 5229 const insn_sequence *template_sequence = NULL;
48229727
JB		 5230 int template_size = 0, i;
5231 unsigned int size;
906e58ca 5232
d3ce72d0 5233 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 5234 if (stub_template)
5235 *stub_template = template_sequence;
5236
48229727 5237 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 5238 if (stub_template_size)
5239 *stub_template_size = template_size;
906e58ca
NC		 5240
5241 size = 0;
461a49ca
DJ		 5242 for (i = 0; i < template_size; i++)
5243 {
d3ce72d0 5244 switch (template_sequence[i].type)
461a49ca
DJ		 5245 {
5246 case THUMB16_TYPE:
5247 size += 2;
5248 break;
5249
5250 case ARM_TYPE:
48229727 5251 case THUMB32_TYPE:
461a49ca
DJ		 5252 case DATA_TYPE:
5253 size += 4;
5254 break;
5255
5256 default:
5257 BFD_FAIL ();
2a229407 5258 return 0;
461a49ca
DJ		 5259 }
5260 }
5261
48229727
JB		 5262 return size;
5263}
5264
5265/* As above, but don't actually build the stub. Just bump offset so
5266 we know stub section sizes. */
5267
5268static bfd_boolean
5269arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 5270 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 5271{
5272 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 5273 const insn_sequence *template_sequence;
48229727
JB		 5274 int template_size, size;
5275
5276 /* Massage our args to the form they really have. */
5277 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 5278
5279 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
5280 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
5281
d3ce72d0 5282 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 5283 &template_size);
5284
0955507f
TP		 5285 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5286 if (stub_entry->stub_template_size)
5287 {
5288 stub_entry->stub_size = size;
5289 stub_entry->stub_template = template_sequence;
5290 stub_entry->stub_template_size = template_size;
5291 }
5292
5293 /* Already accounted for. */
5294 if (stub_entry->stub_offset != (bfd_vma) -1)
5295 return TRUE;
461a49ca 5296
906e58ca
NC		 5297 size = (size + 7) & ~7;
5298 stub_entry->stub_sec->size += size;
461a49ca 5299
906e58ca
NC		 5300 return TRUE;
5301}
5302
5303/* External entry points for sizing and building linker stubs. */
5304
5305/* Set up various things so that we can make a list of input sections
5306 for each output section included in the link. Returns -1 on error,
5307 0 when no stubs will be needed, and 1 on success. */
5308
5309int
5310elf32_arm_setup_section_lists (bfd *output_bfd,
5311 struct bfd_link_info *info)
5312{
5313 bfd *input_bfd;
5314 unsigned int bfd_count;
7292b3ac 5315 unsigned int top_id, top_index;
906e58ca
NC		 5316 asection *section;
5317 asection **input_list, **list;
986f0783 5318 size_t amt;
906e58ca
NC		 5319 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5320
4dfe6ac6
NC		 5321 if (htab == NULL)
5322 return 0;
906e58ca
NC		 5323 if (! is_elf_hash_table (htab))
5324 return 0;
5325
5326 /* Count the number of input BFDs and find the top input section id. */
5327 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
5328 input_bfd != NULL;
c72f2fb2 5329 input_bfd = input_bfd->link.next)
906e58ca
NC		 5330 {
5331 bfd_count += 1;
5332 for (section = input_bfd->sections;
5333 section != NULL;
5334 section = section->next)
5335 {
5336 if (top_id < section->id)
5337 top_id = section->id;
5338 }
5339 }
5340 htab->bfd_count = bfd_count;
5341
5342 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 5343 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 5344 if (htab->stub_group == NULL)
5345 return -1;
fe33d2fa 5346 htab->top_id = top_id;
906e58ca
NC		 5347
5348 /* We can't use output_bfd->section_count here to find the top output
5349 section index as some sections may have been removed, and
5350 _bfd_strip_section_from_output doesn't renumber the indices. */
5351 for (section = output_bfd->sections, top_index = 0;
5352 section != NULL;
5353 section = section->next)
5354 {
5355 if (top_index < section->index)
5356 top_index = section->index;
5357 }
5358
5359 htab->top_index = top_index;
5360 amt = sizeof (asection *) * (top_index + 1);
21d799b5 5361 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 5362 htab->input_list = input_list;
5363 if (input_list == NULL)
5364 return -1;
5365
5366 /* For sections we aren't interested in, mark their entries with a
5367 value we can check later. */
5368 list = input_list + top_index;
5369 do
5370 *list = bfd_abs_section_ptr;
5371 while (list-- != input_list);
5372
5373 for (section = output_bfd->sections;
5374 section != NULL;
5375 section = section->next)
5376 {
5377 if ((section->flags & SEC_CODE) != 0)
5378 input_list[section->index] = NULL;
5379 }
5380
5381 return 1;
5382}
5383
5384/* The linker repeatedly calls this function for each input section,
5385 in the order that input sections are linked into output sections.
5386 Build lists of input sections to determine groupings between which
5387 we may insert linker stubs. */
5388
5389void
5390elf32_arm_next_input_section (struct bfd_link_info *info,
5391 asection *isec)
5392{
5393 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5394
4dfe6ac6
NC		 5395 if (htab == NULL)
5396 return;
5397
906e58ca
NC		 5398 if (isec->output_section->index <= htab->top_index)
5399 {
5400 asection **list = htab->input_list + isec->output_section->index;
5401
a7470592 5402 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5403 {
5404 /* Steal the link_sec pointer for our list. */
5405#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5406 /* This happens to make the list in reverse order,
07d72278 5407 which we reverse later. */
906e58ca
NC		 5408 PREV_SEC (isec) = *list;
5409 *list = isec;
5410 }
5411 }
5412}
5413
5414/* See whether we can group stub sections together. Grouping stub
5415 sections may result in fewer stubs. More importantly, we need to
07d72278 5416 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5417 .fini output sections respectively, because glibc splits the
5418 _init and _fini functions into multiple parts. Putting a stub in
5419 the middle of a function is not a good idea. */
5420
5421static void
5422group_sections (struct elf32_arm_link_hash_table *htab,
5423 bfd_size_type stub_group_size,
07d72278 5424 bfd_boolean stubs_always_after_branch)
906e58ca 5425{
07d72278 5426 asection **list = htab->input_list;
906e58ca
NC		 5427
5428 do
5429 {
5430 asection *tail = *list;
07d72278 5431 asection *head;
906e58ca
NC		 5432
5433 if (tail == bfd_abs_section_ptr)
5434 continue;
5435
07d72278
DJ		 5436 /* Reverse the list: we must avoid placing stubs at the
5437 beginning of the section because the beginning of the text
5438 section may be required for an interrupt vector in bare metal
5439 code. */
5440#define NEXT_SEC PREV_SEC
e780aef2
CL		 5441 head = NULL;
5442 while (tail != NULL)
99059e56
RM		 5443 {
5444 /* Pop from tail. */
5445 asection *item = tail;
5446 tail = PREV_SEC (item);
e780aef2 5447
99059e56
RM		 5448 /* Push on head. */
5449 NEXT_SEC (item) = head;
5450 head = item;
5451 }
07d72278
DJ		 5452
5453 while (head != NULL)
906e58ca
NC		 5454 {
5455 asection *curr;
07d72278 5456 asection *next;
e780aef2
CL		 5457 bfd_vma stub_group_start = head->output_offset;
5458 bfd_vma end_of_next;
906e58ca 5459
07d72278 5460 curr = head;
e780aef2 5461 while (NEXT_SEC (curr) != NULL)
8cd931b7 5462 {
e780aef2
CL		 5463 next = NEXT_SEC (curr);
5464 end_of_next = next->output_offset + next->size;
5465 if (end_of_next - stub_group_start >= stub_group_size)
5466 /* End of NEXT is too far from start, so stop. */
8cd931b7 5467 break;
e780aef2
CL		 5468 /* Add NEXT to the group. */
5469 curr = next;
8cd931b7 5470 }
906e58ca 5471
07d72278 5472 /* OK, the size from the start to the start of CURR is less
906e58ca 5473 than stub_group_size and thus can be handled by one stub
07d72278 5474 section. (Or the head section is itself larger than
906e58ca
NC		 5475 stub_group_size, in which case we may be toast.)
5476 We should really be keeping track of the total size of
5477 stubs added here, as stubs contribute to the final output
7fb9f789 5478 section size. */
906e58ca
NC		 5479 do
5480 {
07d72278 5481 next = NEXT_SEC (head);
906e58ca 5482 /* Set up this stub group. */
07d72278 5483 htab->stub_group[head->id].link_sec = curr;
906e58ca 5484 }
07d72278 5485 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5486
5487 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5488 bytes after the stub section can be handled by it too. */
5489 if (!stubs_always_after_branch)
906e58ca 5490 {
e780aef2
CL		 5491 stub_group_start = curr->output_offset + curr->size;
5492
8cd931b7 5493 while (next != NULL)
906e58ca 5494 {
e780aef2
CL		 5495 end_of_next = next->output_offset + next->size;
5496 if (end_of_next - stub_group_start >= stub_group_size)
5497 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5498 break;
e780aef2 5499 /* Add NEXT to the stub group. */
07d72278
DJ		 5500 head = next;
5501 next = NEXT_SEC (head);
5502 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5503 }
5504 }
07d72278 5505 head = next;
906e58ca
NC		 5506 }
5507 }
07d72278 5508 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5509
5510 free (htab->input_list);
5511#undef PREV_SEC
07d72278 5512#undef NEXT_SEC
906e58ca
NC		 5513}
5514
48229727
JB		 5515/* Comparison function for sorting/searching relocations relating to Cortex-A8
5516 erratum fix. */
5517
5518static int
5519a8_reloc_compare (const void *a, const void *b)
5520{
21d799b5
NC		 5521 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5522 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5523
5524 if (ra->from < rb->from)
5525 return -1;
5526 else if (ra->from > rb->from)
5527 return 1;
5528 else
5529 return 0;
5530}
5531
5532static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5533 const char *, char **);
5534
5535/* Helper function to scan code for sequences which might trigger the Cortex-A8
5536 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5537 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5538 otherwise. */
5539
81694485
NC		 5540static bfd_boolean
5541cortex_a8_erratum_scan (bfd *input_bfd,
5542 struct bfd_link_info *info,
48229727
JB		 5543 struct a8_erratum_fix **a8_fixes_p,
5544 unsigned int *num_a8_fixes_p,
5545 unsigned int *a8_fix_table_size_p,
5546 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5547 unsigned int num_a8_relocs,
5548 unsigned prev_num_a8_fixes,
5549 bfd_boolean *stub_changed_p)
48229727
JB		 5550{
5551 asection *section;
5552 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5553 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5554 unsigned int num_a8_fixes = *num_a8_fixes_p;
5555 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5556
4dfe6ac6
NC		 5557 if (htab == NULL)
5558 return FALSE;
5559
48229727
JB		 5560 for (section = input_bfd->sections;
5561 section != NULL;
5562 section = section->next)
5563 {
5564 bfd_byte *contents = NULL;
5565 struct _arm_elf_section_data *sec_data;
5566 unsigned int span;
5567 bfd_vma base_vma;
5568
5569 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5570 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5571 || (section->flags & SEC_EXCLUDE) != 0
5572 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5573 || (section->output_section == bfd_abs_section_ptr))
5574 continue;
48229727
JB		 5575
5576 base_vma = section->output_section->vma + section->output_offset;
5577
5578 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5579 contents = elf_section_data (section)->this_hdr.contents;
48229727 5580 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5581 return TRUE;
48229727
JB		 5582
5583 sec_data = elf32_arm_section_data (section);
5584
5585 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5586 {
5587 unsigned int span_start = sec_data->map[span].vma;
5588 unsigned int span_end = (span == sec_data->mapcount - 1)
5589 ? section->size : sec_data->map[span + 1].vma;
5590 unsigned int i;
5591 char span_type = sec_data->map[span].type;
5592 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5593
5594 if (span_type != 't')
5595 continue;
5596
5597 /* Span is entirely within a single 4KB region: skip scanning. */
5598 if (((base_vma + span_start) & ~0xfff)
48229727 5599 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5600 continue;
5601
5602 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5603
5604 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5605 * The branch target is in the same 4KB region as the
5606 first half of the branch.
5607 * The instruction before the branch is a 32-bit
5608 length non-branch instruction. */
5609 for (i = span_start; i < span_end;)
5610 {
5611 unsigned int insn = bfd_getl16 (&contents[i]);
5612 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5613 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5614
99059e56
RM		 5615 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5616 insn_32bit = TRUE;
48229727
JB		 5617
5618 if (insn_32bit)
99059e56
RM		 5619 {
5620 /* Load the rest of the insn (in manual-friendly order). */
5621 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5622
5623 /* Encoding T4: B<c>.W. */
5624 is_b = (insn & 0xf800d000) == 0xf0009000;
5625 /* Encoding T1: BL<c>.W. */
5626 is_bl = (insn & 0xf800d000) == 0xf000d000;
5627 /* Encoding T2: BLX<c>.W. */
5628 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5629 /* Encoding T3: B<c>.W (not permitted in IT block). */
5630 is_bcc = (insn & 0xf800d000) == 0xf0008000
5631 && (insn & 0x07f00000) != 0x03800000;
5632 }
5633
5634 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5635
99059e56 5636 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5637 && insn_32bit
5638 && is_32bit_branch
5639 && last_was_32bit
5640 && ! last_was_branch)
99059e56
RM		 5641 {
5642 bfd_signed_vma offset = 0;
5643 bfd_boolean force_target_arm = FALSE;
48229727 5644 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5645 bfd_vma target;
5646 enum elf32_arm_stub_type stub_type = arm_stub_none;
5647 struct a8_erratum_reloc key, *found;
5648 bfd_boolean use_plt = FALSE;
48229727 5649
99059e56
RM		 5650 key.from = base_vma + i;
5651 found = (struct a8_erratum_reloc *)
5652 bsearch (&key, a8_relocs, num_a8_relocs,
5653 sizeof (struct a8_erratum_reloc),
5654 &a8_reloc_compare);
48229727
JB		 5655
5656 if (found)
5657 {
5658 char *error_message = NULL;
5659 struct elf_link_hash_entry *entry;
5660
5661 /* We don't care about the error returned from this
99059e56 5662 function, only if there is glue or not. */
48229727
JB		 5663 entry = find_thumb_glue (info, found->sym_name,
5664 &error_message);
5665
5666 if (entry)
5667 found->non_a8_stub = TRUE;
5668
92750f34 5669 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5670 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5671 && found->hash->root.plt.offset != (bfd_vma) -1)
5672 use_plt = TRUE;
5673
5674 if (found->r_type == R_ARM_THM_CALL)
5675 {
35fc36a8
RS		 5676 if (found->branch_type == ST_BRANCH_TO_ARM
5677 || use_plt)
92750f34
DJ		 5678 force_target_arm = TRUE;
5679 else
5680 force_target_thumb = TRUE;
5681 }
48229727
JB		 5682 }
5683
99059e56 5684 /* Check if we have an offending branch instruction. */
48229727
JB		 5685
5686 if (found && found->non_a8_stub)
5687 /* We've already made a stub for this instruction, e.g.
5688 it's a long branch or a Thumb->ARM stub. Assume that
5689 stub will suffice to work around the A8 erratum (see
5690 setting of always_after_branch above). */
5691 ;
99059e56
RM		 5692 else if (is_bcc)
5693 {
5694 offset = (insn & 0x7ff) << 1;
5695 offset |= (insn & 0x3f0000) >> 4;
5696 offset |= (insn & 0x2000) ? 0x40000 : 0;
5697 offset |= (insn & 0x800) ? 0x80000 : 0;
5698 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5699 if (offset & 0x100000)
5700 offset |= ~ ((bfd_signed_vma) 0xfffff);
5701 stub_type = arm_stub_a8_veneer_b_cond;
5702 }
5703 else if (is_b || is_bl || is_blx)
5704 {
5705 int s = (insn & 0x4000000) != 0;
5706 int j1 = (insn & 0x2000) != 0;
5707 int j2 = (insn & 0x800) != 0;
5708 int i1 = !(j1 ^ s);
5709 int i2 = !(j2 ^ s);
5710
5711 offset = (insn & 0x7ff) << 1;
5712 offset |= (insn & 0x3ff0000) >> 4;
5713 offset |= i2 << 22;
5714 offset |= i1 << 23;
5715 offset |= s << 24;
5716 if (offset & 0x1000000)
5717 offset |= ~ ((bfd_signed_vma) 0xffffff);
5718
5719 if (is_blx)
5720 offset &= ~ ((bfd_signed_vma) 3);
5721
5722 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5723 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5724 }
5725
5726 if (stub_type != arm_stub_none)
5727 {
5728 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5729
5730 /* The original instruction is a BL, but the target is
99059e56 5731 an ARM instruction. If we were not making a stub,
48229727
JB		 5732 the BL would have been converted to a BLX. Use the
5733 BLX stub instead in that case. */
5734 if (htab->use_blx && force_target_arm
5735 && stub_type == arm_stub_a8_veneer_bl)
5736 {
5737 stub_type = arm_stub_a8_veneer_blx;
5738 is_blx = TRUE;
5739 is_bl = FALSE;
5740 }
5741 /* Conversely, if the original instruction was
5742 BLX but the target is Thumb mode, use the BL
5743 stub. */
5744 else if (force_target_thumb
5745 && stub_type == arm_stub_a8_veneer_blx)
5746 {
5747 stub_type = arm_stub_a8_veneer_bl;
5748 is_blx = FALSE;
5749 is_bl = TRUE;
5750 }
5751
99059e56
RM		 5752 if (is_blx)
5753 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5754
99059e56
RM		 5755 /* If we found a relocation, use the proper destination,
5756 not the offset in the (unrelocated) instruction.
48229727
JB		 5757 Note this is always done if we switched the stub type
5758 above. */
99059e56
RM		 5759 if (found)
5760 offset =
81694485 5761 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5762
99059e56
RM		 5763 /* If the stub will use a Thumb-mode branch to a
5764 PLT target, redirect it to the preceding Thumb
5765 entry point. */
5766 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5767 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5768
99059e56 5769 target = pc_for_insn + offset;
48229727 5770
99059e56
RM		 5771 /* The BLX stub is ARM-mode code. Adjust the offset to
5772 take the different PC value (+8 instead of +4) into
48229727 5773 account. */
99059e56
RM		 5774 if (stub_type == arm_stub_a8_veneer_blx)
5775 offset += 4;
5776
5777 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5778 {
5779 char *stub_name = NULL;
5780
5781 if (num_a8_fixes == a8_fix_table_size)
5782 {
5783 a8_fix_table_size *= 2;
5784 a8_fixes = (struct a8_erratum_fix *)
5785 bfd_realloc (a8_fixes,
5786 sizeof (struct a8_erratum_fix)
5787 * a8_fix_table_size);
5788 }
48229727 5789
eb7c4339
NS		 5790 if (num_a8_fixes < prev_num_a8_fixes)
5791 {
5792 /* If we're doing a subsequent scan,
5793 check if we've found the same fix as
5794 before, and try and reuse the stub
5795 name. */
5796 stub_name = a8_fixes[num_a8_fixes].stub_name;
5797 if ((a8_fixes[num_a8_fixes].section != section)
5798 || (a8_fixes[num_a8_fixes].offset != i))
5799 {
5800 free (stub_name);
5801 stub_name = NULL;
5802 *stub_changed_p = TRUE;
5803 }
5804 }
5805
5806 if (!stub_name)
5807 {
21d799b5 5808 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5809 if (stub_name != NULL)
5810 sprintf (stub_name, "%x:%x", section->id, i);
5811 }
48229727 5812
99059e56
RM		 5813 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5814 a8_fixes[num_a8_fixes].section = section;
5815 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5816 a8_fixes[num_a8_fixes].target_offset =
5817 target - base_vma;
99059e56
RM		 5818 a8_fixes[num_a8_fixes].orig_insn = insn;
5819 a8_fixes[num_a8_fixes].stub_name = stub_name;
5820 a8_fixes[num_a8_fixes].stub_type = stub_type;
5821 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5822 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5823
99059e56
RM		 5824 num_a8_fixes++;
5825 }
5826 }
5827 }
48229727 5828
99059e56
RM		 5829 i += insn_32bit ? 4 : 2;
5830 last_was_32bit = insn_32bit;
48229727 5831 last_was_branch = is_32bit_branch;
99059e56
RM		 5832 }
5833 }
48229727
JB		 5834
5835 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5836 free (contents);
48229727 5837 }
fe33d2fa 5838
48229727
JB		 5839 *a8_fixes_p = a8_fixes;
5840 *num_a8_fixes_p = num_a8_fixes;
5841 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5842
81694485 5843 return FALSE;
48229727
JB		 5844}
5845
b715f643
TP		 5846/* Create or update a stub entry depending on whether the stub can already be
5847 found in HTAB. The stub is identified by:
5848 - its type STUB_TYPE
5849 - its source branch (note that several can share the same stub) whose
5850 section and relocation (if any) are given by SECTION and IRELA
5851 respectively
5852 - its target symbol whose input section, hash, name, value and branch type
5853 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5854 respectively
5855
5856 If found, the value of the stub's target symbol is updated from SYM_VALUE
5857 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5858 TRUE and the stub entry is initialized.
5859
0955507f
TP		 5860 Returns the stub that was created or updated, or NULL if an error
5861 occurred. */
b715f643 5862
0955507f 5863static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5864elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5865 enum elf32_arm_stub_type stub_type, asection *section,
5866 Elf_Internal_Rela *irela, asection *sym_sec,
5867 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5868 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5869 bfd_boolean *new_stub)
5870{
5871 const asection *id_sec;
5872 char *stub_name;
5873 struct elf32_arm_stub_hash_entry *stub_entry;
5874 unsigned int r_type;
4f4faa4d 5875 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5876
5877 BFD_ASSERT (stub_type != arm_stub_none);
5878 *new_stub = FALSE;
5879
4f4faa4d
TP		 5880 if (sym_claimed)
5881 stub_name = sym_name;
5882 else
5883 {
5884 BFD_ASSERT (irela);
5885 BFD_ASSERT (section);
c2abbbeb 5886 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5887
4f4faa4d
TP		 5888 /* Support for grouping stub sections. */
5889 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5890
4f4faa4d
TP		 5891 /* Get the name of this stub. */
5892 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5893 stub_type);
5894 if (!stub_name)
0955507f 5895 return NULL;
4f4faa4d 5896 }
b715f643
TP		 5897
5898 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5899 FALSE);
5900 /* The proper stub has already been created, just update its value. */
5901 if (stub_entry != NULL)
5902 {
4f4faa4d
TP		 5903 if (!sym_claimed)
5904 free (stub_name);
b715f643 5905 stub_entry->target_value = sym_value;
0955507f 5906 return stub_entry;
b715f643
TP		 5907 }
5908
daa4adae 5909 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5910 if (stub_entry == NULL)
5911 {
4f4faa4d
TP		 5912 if (!sym_claimed)
5913 free (stub_name);
0955507f 5914 return NULL;
b715f643
TP		 5915 }
5916
5917 stub_entry->target_value = sym_value;
5918 stub_entry->target_section = sym_sec;
5919 stub_entry->stub_type = stub_type;
5920 stub_entry->h = hash;
5921 stub_entry->branch_type = branch_type;
5922
4f4faa4d
TP		 5923 if (sym_claimed)
5924 stub_entry->output_name = sym_name;
5925 else
b715f643 5926 {
4f4faa4d
TP		 5927 if (sym_name == NULL)
5928 sym_name = "unnamed";
5929 stub_entry->output_name = (char *)
5930 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5931 + strlen (sym_name));
5932 if (stub_entry->output_name == NULL)
5933 {
5934 free (stub_name);
0955507f 5935 return NULL;
4f4faa4d 5936 }
b715f643 5937
4f4faa4d
TP		 5938 /* For historical reasons, use the existing names for ARM-to-Thumb and
5939 Thumb-to-ARM stubs. */
5940 r_type = ELF32_R_TYPE (irela->r_info);
5941 if ((r_type == (unsigned int) R_ARM_THM_CALL
5942 || r_type == (unsigned int) R_ARM_THM_JUMP24
5943 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5944 && branch_type == ST_BRANCH_TO_ARM)
5945 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5946 else if ((r_type == (unsigned int) R_ARM_CALL
5947 || r_type == (unsigned int) R_ARM_JUMP24)
5948 && branch_type == ST_BRANCH_TO_THUMB)
5949 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5950 else
5951 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5952 }
b715f643
TP		 5953
5954 *new_stub = TRUE;
0955507f 5955 return stub_entry;
b715f643
TP		 5956}
5957
4ba2ef8f
TP		 5958/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5959 gateway veneer to transition from non secure to secure state and create them
5960 accordingly.
5961
5962 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5963 defines the conditions that govern Secure Gateway veneer creation for a
5964 given symbol <SYM> as follows:
5965 - it has function type
5966 - it has non local binding
5967 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5968 same type, binding and value as <SYM> (called normal symbol).
5969 An entry function can handle secure state transition itself in which case
5970 its special symbol would have a different value from the normal symbol.
5971
5972 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5973 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5974 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5975 created.
4ba2ef8f 5976
0955507f 5977 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5978
5979static bfd_boolean
5980cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5981 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5982 int *cmse_stub_created)
4ba2ef8f
TP		 5983{
5984 const struct elf_backend_data *bed;
5985 Elf_Internal_Shdr *symtab_hdr;
5986 unsigned i, j, sym_count, ext_start;
5987 Elf_Internal_Sym *cmse_sym, *local_syms;
5988 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5989 enum arm_st_branch_type branch_type;
5990 char *sym_name, *lsym_name;
5991 bfd_vma sym_value;
5992 asection *section;
0955507f
TP		 5993 struct elf32_arm_stub_hash_entry *stub_entry;
5994 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5995
5996 bed = get_elf_backend_data (input_bfd);
5997 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5998 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5999 ext_start = symtab_hdr->sh_info;
6000 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
6001 && out_attr[Tag_CPU_arch_profile].i == 'M');
6002
6003 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
6004 if (local_syms == NULL)
6005 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6006 symtab_hdr->sh_info, 0, NULL, NULL,
6007 NULL);
6008 if (symtab_hdr->sh_info && local_syms == NULL)
6009 return FALSE;
6010
6011 /* Scan symbols. */
6012 for (i = 0; i < sym_count; i++)
6013 {
6014 cmse_invalid = FALSE;
6015
6016 if (i < ext_start)
6017 {
6018 cmse_sym = &local_syms[i];
4ba2ef8f
TP		 6019 sym_name = bfd_elf_string_from_elf_section (input_bfd,
6020 symtab_hdr->sh_link,
6021 cmse_sym->st_name);
baf46cd7
AM		 6022 if (!sym_name || !CONST_STRNEQ (sym_name, CMSE_PREFIX))
6023 continue;
6024
4ba2ef8f
TP		 6025 /* Special symbol with local binding. */
6026 cmse_invalid = TRUE;
6027 }
6028 else
6029 {
6030 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
6031 sym_name = (char *) cmse_hash->root.root.root.string;
baf46cd7 6032 if (!CONST_STRNEQ (sym_name, CMSE_PREFIX))
4ba2ef8f
TP		 6033 continue;
6034
6035 /* Special symbol has incorrect binding or type. */
6036 if ((cmse_hash->root.root.type != bfd_link_hash_defined
6037 && cmse_hash->root.root.type != bfd_link_hash_defweak)
6038 || cmse_hash->root.type != STT_FUNC)
6039 cmse_invalid = TRUE;
6040 }
6041
6042 if (!is_v8m)
6043 {
90b6238f
AM		 6044 _bfd_error_handler (_("%pB: special symbol `%s' only allowed for "
6045 "ARMv8-M architecture or later"),
4eca0228 6046 input_bfd, sym_name);
4ba2ef8f
TP		 6047 is_v8m = TRUE; /* Avoid multiple warning. */
6048 ret = FALSE;
6049 }
6050
6051 if (cmse_invalid)
6052 {
90b6238f
AM		 6053 _bfd_error_handler (_("%pB: invalid special symbol `%s'; it must be"
6054 " a global or weak function symbol"),
4eca0228 6055 input_bfd, sym_name);
4ba2ef8f
TP		 6056 ret = FALSE;
6057 if (i < ext_start)
6058 continue;
6059 }
6060
6061 sym_name += strlen (CMSE_PREFIX);
6062 hash = (struct elf32_arm_link_hash_entry *)
6063 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6064
6065 /* No associated normal symbol or it is neither global nor weak. */
6066 if (!hash
6067 || (hash->root.root.type != bfd_link_hash_defined
6068 && hash->root.root.type != bfd_link_hash_defweak)
6069 || hash->root.type != STT_FUNC)
6070 {
6071 /* Initialize here to avoid warning about use of possibly
6072 uninitialized variable. */
6073 j = 0;
6074
6075 if (!hash)
6076 {
6077 /* Searching for a normal symbol with local binding. */
6078 for (; j < ext_start; j++)
6079 {
6080 lsym_name =
6081 bfd_elf_string_from_elf_section (input_bfd,
6082 symtab_hdr->sh_link,
6083 local_syms[j].st_name);
6084 if (!strcmp (sym_name, lsym_name))
6085 break;
6086 }
6087 }
6088
6089 if (hash || j < ext_start)
6090 {
4eca0228 6091 _bfd_error_handler
90b6238f
AM		 6092 (_("%pB: invalid standard symbol `%s'; it must be "
6093 "a global or weak function symbol"),
6094 input_bfd, sym_name);
4ba2ef8f
TP		 6095 }
6096 else
4eca0228 6097 _bfd_error_handler
90b6238f 6098 (_("%pB: absent standard symbol `%s'"), input_bfd, sym_name);
4ba2ef8f
TP		 6099 ret = FALSE;
6100 if (!hash)
6101 continue;
6102 }
6103
6104 sym_value = hash->root.root.u.def.value;
6105 section = hash->root.root.u.def.section;
6106
6107 if (cmse_hash->root.root.u.def.section != section)
6108 {
4eca0228 6109 _bfd_error_handler
90b6238f 6110 (_("%pB: `%s' and its special symbol are in different sections"),
4ba2ef8f
TP		 6111 input_bfd, sym_name);
6112 ret = FALSE;
6113 }
6114 if (cmse_hash->root.root.u.def.value != sym_value)
6115 continue; /* Ignore: could be an entry function starting with SG. */
6116
6117 /* If this section is a link-once section that will be discarded, then
6118 don't create any stubs. */
6119 if (section->output_section == NULL)
6120 {
4eca0228 6121 _bfd_error_handler
90b6238f 6122 (_("%pB: entry function `%s' not output"), input_bfd, sym_name);
4ba2ef8f
TP		 6123 continue;
6124 }
6125
6126 if (hash->root.size == 0)
6127 {
4eca0228 6128 _bfd_error_handler
90b6238f 6129 (_("%pB: entry function `%s' is empty"), input_bfd, sym_name);
4ba2ef8f
TP		 6130 ret = FALSE;
6131 }
6132
6133 if (!ret)
6134 continue;
6135 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 6136 stub_entry
4ba2ef8f
TP		 6137 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6138 NULL, NULL, section, hash, sym_name,
6139 sym_value, branch_type, &new_stub);
6140
0955507f 6141 if (stub_entry == NULL)
4ba2ef8f
TP		 6142 ret = FALSE;
6143 else
6144 {
6145 BFD_ASSERT (new_stub);
0955507f 6146 (*cmse_stub_created)++;
4ba2ef8f
TP		 6147 }
6148 }
6149
6150 if (!symtab_hdr->contents)
6151 free (local_syms);
6152 return ret;
6153}
6154
0955507f
TP		 6155/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6156 code entry function, ie can be called from non secure code without using a
6157 veneer. */
6158
6159static bfd_boolean
6160cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
6161{
42484486 6162 bfd_byte contents[4];
0955507f
TP		 6163 uint32_t first_insn;
6164 asection *section;
6165 file_ptr offset;
6166 bfd *abfd;
6167
6168 /* Defined symbol of function type. */
6169 if (hash->root.root.type != bfd_link_hash_defined
6170 && hash->root.root.type != bfd_link_hash_defweak)
6171 return FALSE;
6172 if (hash->root.type != STT_FUNC)
6173 return FALSE;
6174
6175 /* Read first instruction. */
6176 section = hash->root.root.u.def.section;
6177 abfd = section->owner;
6178 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 6179 if (!bfd_get_section_contents (abfd, section, contents, offset,
6180 sizeof (contents)))
0955507f
TP		 6181 return FALSE;
6182
42484486
TP		 6183 first_insn = bfd_get_32 (abfd, contents);
6184
6185 /* Starts by SG instruction. */
0955507f
TP		 6186 return first_insn == 0xe97fe97f;
6187}
6188
6189/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6190 secure gateway veneers (ie. the veneers was not in the input import library)
6191 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6192
6193static bfd_boolean
6194arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
6195{
6196 struct elf32_arm_stub_hash_entry *stub_entry;
6197 struct bfd_link_info *info;
6198
6199 /* Massage our args to the form they really have. */
6200 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
6201 info = (struct bfd_link_info *) gen_info;
6202
6203 if (info->out_implib_bfd)
6204 return TRUE;
6205
6206 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
6207 return TRUE;
6208
6209 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 6210 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 6211
6212 return TRUE;
6213}
6214
6215/* Set offset of each secure gateway veneers so that its address remain
6216 identical to the one in the input import library referred by
6217 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6218 (present in input import library but absent from the executable being
6219 linked) or if new veneers appeared and there is no output import library
6220 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6221 number of secure gateway veneers found in the input import library.
6222
6223 The function returns whether an error occurred. If no error occurred,
6224 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6225 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6226 veneer observed set for new veneers to be layed out after. */
6227
6228static bfd_boolean
6229set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
6230 struct elf32_arm_link_hash_table *htab,
6231 int *cmse_stub_created)
6232{
6233 long symsize;
6234 char *sym_name;
6235 flagword flags;
6236 long i, symcount;
6237 bfd *in_implib_bfd;
6238 asection *stub_out_sec;
6239 bfd_boolean ret = TRUE;
6240 Elf_Internal_Sym *intsym;
6241 const char *out_sec_name;
6242 bfd_size_type cmse_stub_size;
6243 asymbol **sympp = NULL, *sym;
6244 struct elf32_arm_link_hash_entry *hash;
6245 const insn_sequence *cmse_stub_template;
6246 struct elf32_arm_stub_hash_entry *stub_entry;
6247 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
6248 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
6249 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
6250
6251 /* No input secure gateway import library. */
6252 if (!htab->in_implib_bfd)
6253 return TRUE;
6254
6255 in_implib_bfd = htab->in_implib_bfd;
6256 if (!htab->cmse_implib)
6257 {
871b3ab2 6258 _bfd_error_handler (_("%pB: --in-implib only supported for Secure "
90b6238f 6259 "Gateway import libraries"), in_implib_bfd);
0955507f
TP		 6260 return FALSE;
6261 }
6262
6263 /* Get symbol table size. */
6264 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
6265 if (symsize < 0)
6266 return FALSE;
6267
6268 /* Read in the input secure gateway import library's symbol table. */
9a733151
AM		 6269 sympp = (asymbol **) bfd_malloc (symsize);
6270 if (sympp == NULL)
6271 return FALSE;
6272
0955507f
TP		 6273 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
6274 if (symcount < 0)
6275 {
6276 ret = FALSE;
6277 goto free_sym_buf;
6278 }
6279
6280 htab->new_cmse_stub_offset = 0;
6281 cmse_stub_size =
6282 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
6283 &cmse_stub_template,
6284 &cmse_stub_template_size);
6285 out_sec_name =
6286 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
6287 stub_out_sec =
6288 bfd_get_section_by_name (htab->obfd, out_sec_name);
6289 if (stub_out_sec != NULL)
6290 cmse_stub_sec_vma = stub_out_sec->vma;
6291
6292 /* Set addresses of veneers mentionned in input secure gateway import
6293 library's symbol table. */
6294 for (i = 0; i < symcount; i++)
6295 {
6296 sym = sympp[i];
6297 flags = sym->flags;
6298 sym_name = (char *) bfd_asymbol_name (sym);
6299 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
6300
6301 if (sym->section != bfd_abs_section_ptr
6302 || !(flags & (BSF_GLOBAL | BSF_WEAK))
6303 || (flags & BSF_FUNCTION) != BSF_FUNCTION
6304 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
6305 != ST_BRANCH_TO_THUMB))
6306 {
90b6238f
AM		 6307 _bfd_error_handler (_("%pB: invalid import library entry: `%s'; "
6308 "symbol should be absolute, global and "
6309 "refer to Thumb functions"),
4eca0228 6310 in_implib_bfd, sym_name);
0955507f
TP		 6311 ret = FALSE;
6312 continue;
6313 }
6314
6315 veneer_value = bfd_asymbol_value (sym);
6316 stub_offset = veneer_value - cmse_stub_sec_vma;
6317 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
6318 FALSE, FALSE);
6319 hash = (struct elf32_arm_link_hash_entry *)
6320 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
6321
6322 /* Stub entry should have been created by cmse_scan or the symbol be of
6323 a secure function callable from non secure code. */
6324 if (!stub_entry && !hash)
6325 {
6326 bfd_boolean new_stub;
6327
4eca0228 6328 _bfd_error_handler
90b6238f 6329 (_("entry function `%s' disappeared from secure code"), sym_name);
0955507f
TP		 6330 hash = (struct elf32_arm_link_hash_entry *)
6331 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
6332 stub_entry
6333 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6334 NULL, NULL, bfd_abs_section_ptr, hash,
6335 sym_name, veneer_value,
6336 ST_BRANCH_TO_THUMB, &new_stub);
6337 if (stub_entry == NULL)
6338 ret = FALSE;
6339 else
6340 {
6341 BFD_ASSERT (new_stub);
6342 new_cmse_stubs_created++;
6343 (*cmse_stub_created)++;
6344 }
6345 stub_entry->stub_template_size = stub_entry->stub_size = 0;
6346 stub_entry->stub_offset = stub_offset;
6347 }
6348 /* Symbol found is not callable from non secure code. */
6349 else if (!stub_entry)
6350 {
6351 if (!cmse_entry_fct_p (hash))
6352 {
90b6238f 6353 _bfd_error_handler (_("`%s' refers to a non entry function"),
4eca0228 6354 sym_name);
0955507f
TP		 6355 ret = FALSE;
6356 }
6357 continue;
6358 }
6359 else
6360 {
6361 /* Only stubs for SG veneers should have been created. */
6362 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
6363
6364 /* Check visibility hasn't changed. */
6365 if (!!(flags & BSF_GLOBAL)
6366 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 6367 _bfd_error_handler
90b6238f 6368 (_("%pB: visibility of symbol `%s' has changed"), in_implib_bfd,
0955507f
TP		 6369 sym_name);
6370
6371 stub_entry->stub_offset = stub_offset;
6372 }
6373
6374 /* Size should match that of a SG veneer. */
6375 if (intsym->st_size != cmse_stub_size)
6376 {
90b6238f 6377 _bfd_error_handler (_("%pB: incorrect size for symbol `%s'"),
4eca0228 6378 in_implib_bfd, sym_name);
0955507f
TP		 6379 ret = FALSE;
6380 }
6381
6382 /* Previous veneer address is before current SG veneer section. */
6383 if (veneer_value < cmse_stub_sec_vma)
6384 {
6385 /* Avoid offset underflow. */
6386 if (stub_entry)
6387 stub_entry->stub_offset = 0;
6388 stub_offset = 0;
6389 ret = FALSE;
6390 }
6391
6392 /* Complain if stub offset not a multiple of stub size. */
6393 if (stub_offset % cmse_stub_size)
6394 {
4eca0228 6395 _bfd_error_handler
90b6238f
AM		 6396 (_("offset of veneer for entry function `%s' not a multiple of "
6397 "its size"), sym_name);
0955507f
TP		 6398 ret = FALSE;
6399 }
6400
6401 if (!ret)
6402 continue;
6403
6404 new_cmse_stubs_created--;
6405 if (veneer_value < cmse_stub_array_start)
6406 cmse_stub_array_start = veneer_value;
6407 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6408 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6409 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6410 }
6411
6412 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6413 {
6414 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6415 _bfd_error_handler
0955507f
TP		 6416 (_("new entry function(s) introduced but no output import library "
6417 "specified:"));
6418 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6419 }
6420
6421 if (cmse_stub_array_start != cmse_stub_sec_vma)
6422 {
4eca0228 6423 _bfd_error_handler
90b6238f 6424 (_("start address of `%s' is different from previous link"),
0955507f
TP		 6425 out_sec_name);
6426 ret = FALSE;
6427 }
6428
dc1e8a47 6429 free_sym_buf:
0955507f
TP		 6430 free (sympp);
6431 return ret;
6432}
6433
906e58ca
NC		 6434/* Determine and set the size of the stub section for a final link.
6435
6436 The basic idea here is to examine all the relocations looking for
6437 PC-relative calls to a target that is unreachable with a "bl"
6438 instruction. */
6439
6440bfd_boolean
6441elf32_arm_size_stubs (bfd *output_bfd,
6442 bfd *stub_bfd,
6443 struct bfd_link_info *info,
6444 bfd_signed_vma group_size,
7a89b94e 6445 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6446 asection *,
7a89b94e 6447 unsigned int),
906e58ca
NC		 6448 void (*layout_sections_again) (void))
6449{
0955507f 6450 bfd_boolean ret = TRUE;
4ba2ef8f 6451 obj_attribute *out_attr;
0955507f 6452 int cmse_stub_created = 0;
906e58ca 6453 bfd_size_type stub_group_size;
4ba2ef8f 6454 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6455 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6456 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6457 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6458 struct a8_erratum_reloc *a8_relocs = NULL;
6459 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6460
4dfe6ac6
NC		 6461 if (htab == NULL)
6462 return FALSE;
6463
48229727
JB		 6464 if (htab->fix_cortex_a8)
6465 {
21d799b5 6466 a8_fixes = (struct a8_erratum_fix *)
99059e56 6467 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6468 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6469 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6470 }
906e58ca
NC		 6471
6472 /* Propagate mach to stub bfd, because it may not have been
6473 finalized when we created stub_bfd. */
6474 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6475 bfd_get_mach (output_bfd));
6476
6477 /* Stash our params away. */
6478 htab->stub_bfd = stub_bfd;
6479 htab->add_stub_section = add_stub_section;
6480 htab->layout_sections_again = layout_sections_again;
07d72278 6481 stubs_always_after_branch = group_size < 0;
48229727 6482
4ba2ef8f
TP		 6483 out_attr = elf_known_obj_attributes_proc (output_bfd);
6484 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6485
48229727
JB		 6486 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6487 as the first half of a 32-bit branch straddling two 4K pages. This is a
6488 crude way of enforcing that. */
6489 if (htab->fix_cortex_a8)
6490 stubs_always_after_branch = 1;
6491
906e58ca
NC		 6492 if (group_size < 0)
6493 stub_group_size = -group_size;
6494 else
6495 stub_group_size = group_size;
6496
6497 if (stub_group_size == 1)
6498 {
6499 /* Default values. */
6500 /* Thumb branch range is +-4MB has to be used as the default
6501 maximum size (a given section can contain both ARM and Thumb
6502 code, so the worst case has to be taken into account).
6503
6504 This value is 24K less than that, which allows for 2025
6505 12-byte stubs. If we exceed that, then we will fail to link.
6506 The user will have to relink with an explicit group size
6507 option. */
6508 stub_group_size = 4170000;
6509 }
6510
07d72278 6511 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6512
3ae046cc
NS		 6513 /* If we're applying the cortex A8 fix, we need to determine the
6514 program header size now, because we cannot change it later --
6515 that could alter section placements. Notice the A8 erratum fix
6516 ends up requiring the section addresses to remain unchanged
6517 modulo the page size. That's something we cannot represent
6518 inside BFD, and we don't want to force the section alignment to
6519 be the page size. */
6520 if (htab->fix_cortex_a8)
6521 (*htab->layout_sections_again) ();
6522
906e58ca
NC		 6523 while (1)
6524 {
6525 bfd *input_bfd;
6526 unsigned int bfd_indx;
6527 asection *stub_sec;
d7c5bd02 6528 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6529 bfd_boolean stub_changed = FALSE;
6530 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6531
48229727 6532 num_a8_fixes = 0;
906e58ca
NC		 6533 for (input_bfd = info->input_bfds, bfd_indx = 0;
6534 input_bfd != NULL;
c72f2fb2 6535 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6536 {
6537 Elf_Internal_Shdr *symtab_hdr;
6538 asection *section;
6539 Elf_Internal_Sym *local_syms = NULL;
6540
73d5efd7
AM		 6541 if (!is_arm_elf (input_bfd))
6542 continue;
6543 if ((input_bfd->flags & DYNAMIC) != 0
6544 && (elf_sym_hashes (input_bfd) == NULL
6545 || (elf_dyn_lib_class (input_bfd) & DYN_AS_NEEDED) != 0))
99059e56 6546 continue;
adbcc655 6547
48229727
JB		 6548 num_a8_relocs = 0;
6549
906e58ca
NC		 6550 /* We'll need the symbol table in a second. */
6551 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6552 if (symtab_hdr->sh_info == 0)
6553 continue;
6554
4ba2ef8f
TP		 6555 /* Limit scan of symbols to object file whose profile is
6556 Microcontroller to not hinder performance in the general case. */
6557 if (m_profile && first_veneer_scan)
6558 {
6559 struct elf_link_hash_entry **sym_hashes;
6560
6561 sym_hashes = elf_sym_hashes (input_bfd);
6562 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6563 &cmse_stub_created))
4ba2ef8f 6564 goto error_ret_free_local;
0955507f
TP		 6565
6566 if (cmse_stub_created != 0)
6567 stub_changed = TRUE;
4ba2ef8f
TP		 6568 }
6569
906e58ca
NC		 6570 /* Walk over each section attached to the input bfd. */
6571 for (section = input_bfd->sections;
6572 section != NULL;
6573 section = section->next)
6574 {
6575 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6576
6577 /* If there aren't any relocs, then there's nothing more
6578 to do. */
6579 if ((section->flags & SEC_RELOC) == 0
6580 || section->reloc_count == 0
6581 || (section->flags & SEC_CODE) == 0)
6582 continue;
6583
6584 /* If this section is a link-once section that will be
6585 discarded, then don't create any stubs. */
6586 if (section->output_section == NULL
6587 || section->output_section->owner != output_bfd)
6588 continue;
6589
6590 /* Get the relocs. */
6591 internal_relocs
6592 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6593 NULL, info->keep_memory);
6594 if (internal_relocs == NULL)
6595 goto error_ret_free_local;
6596
6597 /* Now examine each relocation. */
6598 irela = internal_relocs;
6599 irelaend = irela + section->reloc_count;
6600 for (; irela < irelaend; irela++)
6601 {
6602 unsigned int r_type, r_indx;
906e58ca
NC		 6603 asection *sym_sec;
6604 bfd_vma sym_value;
6605 bfd_vma destination;
6606 struct elf32_arm_link_hash_entry *hash;
7413f23f 6607 const char *sym_name;
34e77a92 6608 unsigned char st_type;
35fc36a8 6609 enum arm_st_branch_type branch_type;
48229727 6610 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6611
6612 r_type = ELF32_R_TYPE (irela->r_info);
6613 r_indx = ELF32_R_SYM (irela->r_info);
6614
6615 if (r_type >= (unsigned int) R_ARM_max)
6616 {
6617 bfd_set_error (bfd_error_bad_value);
6618 error_ret_free_internal:
6619 if (elf_section_data (section)->relocs == NULL)
6620 free (internal_relocs);
15dd01b1
TP		 6621 /* Fall through. */
6622 error_ret_free_local:
6623 if (local_syms != NULL
6624 && (symtab_hdr->contents
6625 != (unsigned char *) local_syms))
6626 free (local_syms);
6627 return FALSE;
906e58ca 6628 }
b38cadfb 6629
0855e32b
NS		 6630 hash = NULL;
6631 if (r_indx >= symtab_hdr->sh_info)
6632 hash = elf32_arm_hash_entry
6633 (elf_sym_hashes (input_bfd)
6634 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6635
0855e32b
NS		 6636 /* Only look for stubs on branch instructions, or
6637 non-relaxed TLSCALL */
906e58ca 6638 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6639 && (r_type != (unsigned int) R_ARM_THM_CALL)
6640 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6641 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6642 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6643 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6644 && (r_type != (unsigned int) R_ARM_PLT32)
6645 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6646 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6647 && r_type == elf32_arm_tls_transition
6648 (info, r_type, &hash->root)
6649 && ((hash ? hash->tls_type
6650 : (elf32_arm_local_got_tls_type
6651 (input_bfd)[r_indx]))
6652 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6653 continue;
6654
6655 /* Now determine the call target, its name, value,
6656 section. */
6657 sym_sec = NULL;
6658 sym_value = 0;
6659 destination = 0;
7413f23f 6660 sym_name = NULL;
b38cadfb 6661
0855e32b
NS		 6662 if (r_type == (unsigned int) R_ARM_TLS_CALL
6663 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6664 {
6665 /* A non-relaxed TLS call. The target is the
6666 plt-resident trampoline and nothing to do
6667 with the symbol. */
6668 BFD_ASSERT (htab->tls_trampoline > 0);
6669 sym_sec = htab->root.splt;
6670 sym_value = htab->tls_trampoline;
6671 hash = 0;
34e77a92 6672 st_type = STT_FUNC;
35fc36a8 6673 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6674 }
6675 else if (!hash)
906e58ca
NC		 6676 {
6677 /* It's a local symbol. */
6678 Elf_Internal_Sym *sym;
906e58ca
NC		 6679
6680 if (local_syms == NULL)
6681 {
6682 local_syms
6683 = (Elf_Internal_Sym *) symtab_hdr->contents;
6684 if (local_syms == NULL)
6685 local_syms
6686 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6687 symtab_hdr->sh_info, 0,
6688 NULL, NULL, NULL);
6689 if (local_syms == NULL)
6690 goto error_ret_free_internal;
6691 }
6692
6693 sym = local_syms + r_indx;
f6d250ce
TS		 6694 if (sym->st_shndx == SHN_UNDEF)
6695 sym_sec = bfd_und_section_ptr;
6696 else if (sym->st_shndx == SHN_ABS)
6697 sym_sec = bfd_abs_section_ptr;
6698 else if (sym->st_shndx == SHN_COMMON)
6699 sym_sec = bfd_com_section_ptr;
6700 else
6701 sym_sec =
6702 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6703
ffcb4889
NS		 6704 if (!sym_sec)
6705 /* This is an undefined symbol. It can never
6a631e86 6706 be resolved. */
ffcb4889 6707 continue;
fe33d2fa 6708
906e58ca
NC		 6709 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6710 sym_value = sym->st_value;
6711 destination = (sym_value + irela->r_addend
6712 + sym_sec->output_offset
6713 + sym_sec->output_section->vma);
34e77a92 6714 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6715 branch_type =
6716 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6717 sym_name
6718 = bfd_elf_string_from_elf_section (input_bfd,
6719 symtab_hdr->sh_link,
6720 sym->st_name);
906e58ca
NC		 6721 }
6722 else
6723 {
6724 /* It's an external symbol. */
906e58ca
NC		 6725 while (hash->root.root.type == bfd_link_hash_indirect
6726 || hash->root.root.type == bfd_link_hash_warning)
6727 hash = ((struct elf32_arm_link_hash_entry *)
6728 hash->root.root.u.i.link);
6729
6730 if (hash->root.root.type == bfd_link_hash_defined
6731 || hash->root.root.type == bfd_link_hash_defweak)
6732 {
6733 sym_sec = hash->root.root.u.def.section;
6734 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6735
6736 struct elf32_arm_link_hash_table *globals =
6737 elf32_arm_hash_table (info);
6738
6739 /* For a destination in a shared library,
6740 use the PLT stub as target address to
6741 decide whether a branch stub is
6742 needed. */
4dfe6ac6 6743 if (globals != NULL
362d30a1 6744 && globals->root.splt != NULL
4dfe6ac6 6745 && hash != NULL
022f8312
CL		 6746 && hash->root.plt.offset != (bfd_vma) -1)
6747 {
362d30a1 6748 sym_sec = globals->root.splt;
022f8312
CL		 6749 sym_value = hash->root.plt.offset;
6750 if (sym_sec->output_section != NULL)
6751 destination = (sym_value
6752 + sym_sec->output_offset
6753 + sym_sec->output_section->vma);
6754 }
6755 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6756 destination = (sym_value + irela->r_addend
6757 + sym_sec->output_offset
6758 + sym_sec->output_section->vma);
6759 }
69c5861e
CL		 6760 else if ((hash->root.root.type == bfd_link_hash_undefined)
6761 || (hash->root.root.type == bfd_link_hash_undefweak))
6762 {
6763 /* For a shared library, use the PLT stub as
6764 target address to decide whether a long
6765 branch stub is needed.
6766 For absolute code, they cannot be handled. */
6767 struct elf32_arm_link_hash_table *globals =
6768 elf32_arm_hash_table (info);
6769
4dfe6ac6 6770 if (globals != NULL
362d30a1 6771 && globals->root.splt != NULL
4dfe6ac6 6772 && hash != NULL
69c5861e
CL		 6773 && hash->root.plt.offset != (bfd_vma) -1)
6774 {
362d30a1 6775 sym_sec = globals->root.splt;
69c5861e
CL		 6776 sym_value = hash->root.plt.offset;
6777 if (sym_sec->output_section != NULL)
6778 destination = (sym_value
6779 + sym_sec->output_offset
6780 + sym_sec->output_section->vma);
6781 }
6782 else
6783 continue;
6784 }
906e58ca
NC		 6785 else
6786 {
6787 bfd_set_error (bfd_error_bad_value);
6788 goto error_ret_free_internal;
6789 }
34e77a92 6790 st_type = hash->root.type;
39d911fc
TP		 6791 branch_type =
6792 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6793 sym_name = hash->root.root.root.string;
906e58ca
NC		 6794 }
6795
48229727 6796 do
7413f23f 6797 {
b715f643 6798 bfd_boolean new_stub;
0955507f 6799 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6800
48229727
JB		 6801 /* Determine what (if any) linker stub is needed. */
6802 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6803 st_type, &branch_type,
6804 hash, destination, sym_sec,
48229727
JB		 6805 input_bfd, sym_name);
6806 if (stub_type == arm_stub_none)
6807 break;
6808
48229727
JB		 6809 /* We've either created a stub for this reloc already,
6810 or we are about to. */
0955507f 6811 stub_entry =
b715f643
TP		 6812 elf32_arm_create_stub (htab, stub_type, section, irela,
6813 sym_sec, hash,
6814 (char *) sym_name, sym_value,
6815 branch_type, &new_stub);
7413f23f 6816
0955507f 6817 created_stub = stub_entry != NULL;
b715f643
TP		 6818 if (!created_stub)
6819 goto error_ret_free_internal;
6820 else if (!new_stub)
6821 break;
99059e56 6822 else
b715f643 6823 stub_changed = TRUE;
99059e56
RM		 6824 }
6825 while (0);
6826
6827 /* Look for relocations which might trigger Cortex-A8
6828 erratum. */
6829 if (htab->fix_cortex_a8
6830 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6831 || r_type == (unsigned int) R_ARM_THM_JUMP19
6832 || r_type == (unsigned int) R_ARM_THM_CALL
6833 || r_type == (unsigned int) R_ARM_THM_XPC22))
6834 {
6835 bfd_vma from = section->output_section->vma
6836 + section->output_offset
6837 + irela->r_offset;
6838
6839 if ((from & 0xfff) == 0xffe)
6840 {
6841 /* Found a candidate. Note we haven't checked the
6842 destination is within 4K here: if we do so (and
6843 don't create an entry in a8_relocs) we can't tell
6844 that a branch should have been relocated when
6845 scanning later. */
6846 if (num_a8_relocs == a8_reloc_table_size)
6847 {
6848 a8_reloc_table_size *= 2;
6849 a8_relocs = (struct a8_erratum_reloc *)
6850 bfd_realloc (a8_relocs,
6851 sizeof (struct a8_erratum_reloc)
6852 * a8_reloc_table_size);
6853 }
6854
6855 a8_relocs[num_a8_relocs].from = from;
6856 a8_relocs[num_a8_relocs].destination = destination;
6857 a8_relocs[num_a8_relocs].r_type = r_type;
6858 a8_relocs[num_a8_relocs].branch_type = branch_type;
6859 a8_relocs[num_a8_relocs].sym_name = sym_name;
6860 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6861 a8_relocs[num_a8_relocs].hash = hash;
6862
6863 num_a8_relocs++;
6864 }
6865 }
906e58ca
NC		 6866 }
6867
99059e56
RM		 6868 /* We're done with the internal relocs, free them. */
6869 if (elf_section_data (section)->relocs == NULL)
6870 free (internal_relocs);
6871 }
48229727 6872
99059e56 6873 if (htab->fix_cortex_a8)
48229727 6874 {
99059e56
RM		 6875 /* Sort relocs which might apply to Cortex-A8 erratum. */
6876 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6877 sizeof (struct a8_erratum_reloc),
99059e56 6878 &a8_reloc_compare);
48229727 6879
99059e56
RM		 6880 /* Scan for branches which might trigger Cortex-A8 erratum. */
6881 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6882 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6883 a8_relocs, num_a8_relocs,
6884 prev_num_a8_fixes, &stub_changed)
6885 != 0)
48229727 6886 goto error_ret_free_local;
5e681ec4 6887 }
7f991970
AM		 6888
6889 if (local_syms != NULL
6890 && symtab_hdr->contents != (unsigned char *) local_syms)
6891 {
6892 if (!info->keep_memory)
6893 free (local_syms);
6894 else
6895 symtab_hdr->contents = (unsigned char *) local_syms;
6896 }
5e681ec4
PB		 6897 }
6898
0955507f
TP		 6899 if (first_veneer_scan
6900 && !set_cmse_veneer_addr_from_implib (info, htab,
6901 &cmse_stub_created))
6902 ret = FALSE;
6903
eb7c4339 6904 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6905 stub_changed = TRUE;
48229727 6906
906e58ca
NC		 6907 if (!stub_changed)
6908 break;
5e681ec4 6909
906e58ca
NC		 6910 /* OK, we've added some stubs. Find out the new size of the
6911 stub sections. */
6912 for (stub_sec = htab->stub_bfd->sections;
6913 stub_sec != NULL;
6914 stub_sec = stub_sec->next)
3e6b1042
DJ		 6915 {
6916 /* Ignore non-stub sections. */
6917 if (!strstr (stub_sec->name, STUB_SUFFIX))
6918 continue;
6919
6920 stub_sec->size = 0;
6921 }
b34b2d70 6922
0955507f
TP		 6923 /* Add new SG veneers after those already in the input import
6924 library. */
6925 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6926 stub_type++)
6927 {
6928 bfd_vma *start_offset_p;
6929 asection **stub_sec_p;
6930
6931 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6932 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6933 if (start_offset_p == NULL)
6934 continue;
6935
6936 BFD_ASSERT (stub_sec_p != NULL);
6937 if (*stub_sec_p != NULL)
6938 (*stub_sec_p)->size = *start_offset_p;
6939 }
6940
d7c5bd02 6941 /* Compute stub section size, considering padding. */
906e58ca 6942 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6943 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6944 stub_type++)
6945 {
6946 int size, padding;
6947 asection **stub_sec_p;
6948
6949 padding = arm_dedicated_stub_section_padding (stub_type);
6950 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6951 /* Skip if no stub input section or no stub section padding
6952 required. */
6953 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6954 continue;
6955 /* Stub section padding required but no dedicated section. */
6956 BFD_ASSERT (stub_sec_p);
6957
6958 size = (*stub_sec_p)->size;
6959 size = (size + padding - 1) & ~(padding - 1);
6960 (*stub_sec_p)->size = size;
6961 }
906e58ca 6962
48229727
JB		 6963 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6964 if (htab->fix_cortex_a8)
99059e56
RM		 6965 for (i = 0; i < num_a8_fixes; i++)
6966 {
48229727 6967 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6968 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6969
6970 if (stub_sec == NULL)
7f991970 6971 return FALSE;
48229727 6972
99059e56
RM		 6973 stub_sec->size
6974 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6975 NULL);
6976 }
48229727
JB		 6977
6978
906e58ca
NC		 6979 /* Ask the linker to do its stuff. */
6980 (*htab->layout_sections_again) ();
4ba2ef8f 6981 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6982 }
6983
48229727
JB		 6984 /* Add stubs for Cortex-A8 erratum fixes now. */
6985 if (htab->fix_cortex_a8)
6986 {
6987 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6988 {
6989 struct elf32_arm_stub_hash_entry *stub_entry;
6990 char *stub_name = a8_fixes[i].stub_name;
6991 asection *section = a8_fixes[i].section;
6992 unsigned int section_id = a8_fixes[i].section->id;
6993 asection *link_sec = htab->stub_group[section_id].link_sec;
6994 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6995 const insn_sequence *template_sequence;
6996 int template_size, size = 0;
6997
6998 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6999 TRUE, FALSE);
7000 if (stub_entry == NULL)
7001 {
871b3ab2 7002 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 7003 section->owner, stub_name);
99059e56
RM		 7004 return FALSE;
7005 }
7006
7007 stub_entry->stub_sec = stub_sec;
0955507f 7008 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 7009 stub_entry->id_sec = link_sec;
7010 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 7011 stub_entry->source_value = a8_fixes[i].offset;
99059e56 7012 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 7013 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 7014 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 7015 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 7016
99059e56
RM		 7017 size = find_stub_size_and_template (a8_fixes[i].stub_type,
7018 &template_sequence,
7019 &template_size);
48229727 7020
99059e56
RM		 7021 stub_entry->stub_size = size;
7022 stub_entry->stub_template = template_sequence;
7023 stub_entry->stub_template_size = template_size;
7024 }
48229727
JB		 7025
7026 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 7027 elf32_arm_write_section(). */
48229727
JB		 7028 htab->a8_erratum_fixes = a8_fixes;
7029 htab->num_a8_erratum_fixes = num_a8_fixes;
7030 }
7031 else
7032 {
7033 htab->a8_erratum_fixes = NULL;
7034 htab->num_a8_erratum_fixes = 0;
7035 }
0955507f 7036 return ret;
5e681ec4
PB		 7037}
7038
906e58ca
NC		 7039/* Build all the stubs associated with the current output file. The
7040 stubs are kept in a hash table attached to the main linker hash
7041 table. We also set up the .plt entries for statically linked PIC
7042 functions here. This function is called via arm_elf_finish in the
7043 linker. */
252b5132 7044
906e58ca
NC		 7045bfd_boolean
7046elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 7047{
906e58ca
NC		 7048 asection *stub_sec;
7049 struct bfd_hash_table *table;
0955507f 7050 enum elf32_arm_stub_type stub_type;
906e58ca 7051 struct elf32_arm_link_hash_table *htab;
252b5132 7052
906e58ca 7053 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 7054 if (htab == NULL)
7055 return FALSE;
252b5132 7056
906e58ca
NC		 7057 for (stub_sec = htab->stub_bfd->sections;
7058 stub_sec != NULL;
7059 stub_sec = stub_sec->next)
252b5132 7060 {
906e58ca
NC		 7061 bfd_size_type size;
7062
8029a119 7063 /* Ignore non-stub sections. */
906e58ca
NC		 7064 if (!strstr (stub_sec->name, STUB_SUFFIX))
7065 continue;
7066
d7c5bd02 7067 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 7068 must at least be done for stub section requiring padding and for SG
7069 veneers to ensure that a non secure code branching to a removed SG
7070 veneer causes an error. */
906e58ca 7071 size = stub_sec->size;
21d799b5 7072 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 7073 if (stub_sec->contents == NULL && size != 0)
7074 return FALSE;
0955507f 7075
906e58ca 7076 stub_sec->size = 0;
252b5132
RH		 7077 }
7078
0955507f
TP		 7079 /* Add new SG veneers after those already in the input import library. */
7080 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7081 {
7082 bfd_vma *start_offset_p;
7083 asection **stub_sec_p;
7084
7085 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
7086 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
7087 if (start_offset_p == NULL)
7088 continue;
7089
7090 BFD_ASSERT (stub_sec_p != NULL);
7091 if (*stub_sec_p != NULL)
7092 (*stub_sec_p)->size = *start_offset_p;
7093 }
7094
906e58ca
NC		 7095 /* Build the stubs as directed by the stub hash table. */
7096 table = &htab->stub_hash_table;
7097 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 7098 if (htab->fix_cortex_a8)
7099 {
7100 /* Place the cortex a8 stubs last. */
7101 htab->fix_cortex_a8 = -1;
7102 bfd_hash_traverse (table, arm_build_one_stub, info);
7103 }
252b5132 7104
906e58ca 7105 return TRUE;
252b5132
RH		 7106}
7107
9b485d32
NC		 7108/* Locate the Thumb encoded calling stub for NAME. */
7109
252b5132 7110static struct elf_link_hash_entry *
57e8b36a
NC		 7111find_thumb_glue (struct bfd_link_info *link_info,
7112 const char *name,
f2a9dd69 7113 char **error_message)
252b5132
RH		 7114{
7115 char *tmp_name;
7116 struct elf_link_hash_entry *hash;
7117 struct elf32_arm_link_hash_table *hash_table;
7118
7119 /* We need a pointer to the armelf specific hash table. */
7120 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7121 if (hash_table == NULL)
7122 return NULL;
252b5132 7123
21d799b5 7124 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7125 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7126
7127 BFD_ASSERT (tmp_name);
7128
7129 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
7130
7131 hash = elf_link_hash_lookup
b34976b6 7132 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7133
b1657152 7134 if (hash == NULL
90b6238f
AM		 7135 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7136 "Thumb", tmp_name, name) == -1)
b1657152 7137 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7138
7139 free (tmp_name);
7140
7141 return hash;
7142}
7143
9b485d32
NC		 7144/* Locate the ARM encoded calling stub for NAME. */
7145
252b5132 7146static struct elf_link_hash_entry *
57e8b36a
NC		 7147find_arm_glue (struct bfd_link_info *link_info,
7148 const char *name,
f2a9dd69 7149 char **error_message)
252b5132
RH		 7150{
7151 char *tmp_name;
7152 struct elf_link_hash_entry *myh;
7153 struct elf32_arm_link_hash_table *hash_table;
7154
7155 /* We need a pointer to the elfarm specific hash table. */
7156 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7157 if (hash_table == NULL)
7158 return NULL;
252b5132 7159
21d799b5 7160 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7161 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7162 BFD_ASSERT (tmp_name);
7163
7164 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7165
7166 myh = elf_link_hash_lookup
b34976b6 7167 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 7168
b1657152 7169 if (myh == NULL
90b6238f
AM		 7170 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7171 "ARM", tmp_name, name) == -1)
b1657152 7172 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 7173
7174 free (tmp_name);
7175
7176 return myh;
7177}
7178
8f6277f5 7179/* ARM->Thumb glue (static images):
252b5132
RH		 7180
7181 .arm
7182 __func_from_arm:
7183 ldr r12, __func_addr
7184 bx r12
7185 __func_addr:
906e58ca 7186 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 7187
26079076
PB		 7188 (v5t static images)
7189 .arm
7190 __func_from_arm:
7191 ldr pc, __func_addr
7192 __func_addr:
906e58ca 7193 .word func @ behave as if you saw a ARM_32 reloc.
26079076 7194
8f6277f5
PB		 7195 (relocatable images)
7196 .arm
7197 __func_from_arm:
7198 ldr r12, __func_offset
7199 add r12, r12, pc
7200 bx r12
7201 __func_offset:
8029a119 7202 .word func - . */
8f6277f5
PB		 7203
7204#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 7205static const insn32 a2t1_ldr_insn = 0xe59fc000;
7206static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
7207static const insn32 a2t3_func_addr_insn = 0x00000001;
7208
26079076
PB		 7209#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7210static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
7211static const insn32 a2t2v5_func_addr_insn = 0x00000001;
7212
8f6277f5
PB		 7213#define ARM2THUMB_PIC_GLUE_SIZE 16
7214static const insn32 a2t1p_ldr_insn = 0xe59fc004;
7215static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
7216static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
7217
07d6d2b8 7218/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 7219
07d6d2b8
AM		 7220 .thumb .thumb
7221 .align 2 .align 2
7222 __func_from_thumb: __func_from_thumb:
7223 bx pc push {r6, lr}
7224 nop ldr r6, __func_addr
7225 .arm mov lr, pc
7226 b func bx r6
99059e56
RM		 7227 .arm
7228 ;; back_to_thumb
7229 ldmia r13! {r6, lr}
7230 bx lr
7231 __func_addr:
07d6d2b8 7232 .word func */
252b5132
RH		 7233
7234#define THUMB2ARM_GLUE_SIZE 8
7235static const insn16 t2a1_bx_pc_insn = 0x4778;
7236static const insn16 t2a2_noop_insn = 0x46c0;
7237static const insn32 t2a3_b_insn = 0xea000000;
7238
c7b8f16e 7239#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 7240#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7241#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 7242
845b51d6
PB		 7243#define ARM_BX_VENEER_SIZE 12
7244static const insn32 armbx1_tst_insn = 0xe3100001;
7245static const insn32 armbx2_moveq_insn = 0x01a0f000;
7246static const insn32 armbx3_bx_insn = 0xe12fff10;
7247
7e392df6 7248#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 7249static void
7250arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 7251{
7252 asection * s;
8029a119 7253 bfd_byte * contents;
252b5132 7254
8029a119 7255 if (size == 0)
3e6b1042
DJ		 7256 {
7257 /* Do not include empty glue sections in the output. */
7258 if (abfd != NULL)
7259 {
3d4d4302 7260 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 7261 if (s != NULL)
7262 s->flags |= SEC_EXCLUDE;
7263 }
7264 return;
7265 }
252b5132 7266
8029a119 7267 BFD_ASSERT (abfd != NULL);
252b5132 7268
3d4d4302 7269 s = bfd_get_linker_section (abfd, name);
8029a119 7270 BFD_ASSERT (s != NULL);
252b5132 7271
b0f4fbf8 7272 contents = (bfd_byte *) bfd_zalloc (abfd, size);
252b5132 7273
8029a119
NC		 7274 BFD_ASSERT (s->size == size);
7275 s->contents = contents;
7276}
906e58ca 7277
8029a119
NC		 7278bfd_boolean
7279bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
7280{
7281 struct elf32_arm_link_hash_table * globals;
906e58ca 7282
8029a119
NC		 7283 globals = elf32_arm_hash_table (info);
7284 BFD_ASSERT (globals != NULL);
906e58ca 7285
8029a119
NC		 7286 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7287 globals->arm_glue_size,
7288 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 7289
8029a119
NC		 7290 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7291 globals->thumb_glue_size,
7292 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 7293
8029a119
NC		 7294 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7295 globals->vfp11_erratum_glue_size,
7296 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 7297
a504d23a
LA		 7298 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7299 globals->stm32l4xx_erratum_glue_size,
7300 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7301
8029a119
NC		 7302 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7303 globals->bx_glue_size,
845b51d6
PB		 7304 ARM_BX_GLUE_SECTION_NAME);
7305
b34976b6 7306 return TRUE;
252b5132
RH		 7307}
7308
a4fd1a8e 7309/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 7310 returns the symbol identifying the stub. */
7311
a4fd1a8e 7312static struct elf_link_hash_entry *
57e8b36a
NC		 7313record_arm_to_thumb_glue (struct bfd_link_info * link_info,
7314 struct elf_link_hash_entry * h)
252b5132
RH		 7315{
7316 const char * name = h->root.root.string;
63b0f745 7317 asection * s;
252b5132
RH		 7318 char * tmp_name;
7319 struct elf_link_hash_entry * myh;
14a793b2 7320 struct bfd_link_hash_entry * bh;
252b5132 7321 struct elf32_arm_link_hash_table * globals;
dc810e39 7322 bfd_vma val;
2f475487 7323 bfd_size_type size;
252b5132
RH		 7324
7325 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 7326 BFD_ASSERT (globals != NULL);
7327 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7328
3d4d4302 7329 s = bfd_get_linker_section
252b5132
RH		 7330 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
7331
252b5132
RH		 7332 BFD_ASSERT (s != NULL);
7333
21d799b5 7334 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 7335 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 7336 BFD_ASSERT (tmp_name);
7337
7338 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7339
7340 myh = elf_link_hash_lookup
b34976b6 7341 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 7342
7343 if (myh != NULL)
7344 {
9b485d32 7345 /* We've already seen this guy. */
252b5132 7346 free (tmp_name);
a4fd1a8e 7347 return myh;
252b5132
RH		 7348 }
7349
57e8b36a
NC		 7350 /* The only trick here is using hash_table->arm_glue_size as the value.
7351 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 7352 putting it. The +1 on the value marks that the stub has not been
7353 output yet - not that it is a Thumb function. */
14a793b2 7354 bh = NULL;
dc810e39
AM		 7355 val = globals->arm_glue_size + 1;
7356 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
7357 tmp_name, BSF_GLOBAL, s, val,
b34976b6 7358 NULL, TRUE, FALSE, &bh);
252b5132 7359
b7693d02
DJ		 7360 myh = (struct elf_link_hash_entry *) bh;
7361 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7362 myh->forced_local = 1;
7363
252b5132
RH		 7364 free (tmp_name);
7365
0e1862bb
L		 7366 if (bfd_link_pic (link_info)
7367 || globals->root.is_relocatable_executable
27e55c4d 7368 || globals->pic_veneer)
2f475487 7369 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 7370 else if (globals->use_blx)
7371 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 7372 else
2f475487
AM		 7373 size = ARM2THUMB_STATIC_GLUE_SIZE;
7374
7375 s->size += size;
7376 globals->arm_glue_size += size;
252b5132 7377
a4fd1a8e 7378 return myh;
252b5132
RH		 7379}
7380
845b51d6
PB		 7381/* Allocate space for ARMv4 BX veneers. */
7382
7383static void
7384record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7385{
7386 asection * s;
7387 struct elf32_arm_link_hash_table *globals;
7388 char *tmp_name;
7389 struct elf_link_hash_entry *myh;
7390 struct bfd_link_hash_entry *bh;
7391 bfd_vma val;
7392
7393 /* BX PC does not need a veneer. */
7394 if (reg == 15)
7395 return;
7396
7397 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7398 BFD_ASSERT (globals != NULL);
7399 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7400
7401 /* Check if this veneer has already been allocated. */
7402 if (globals->bx_glue_offset[reg])
7403 return;
7404
3d4d4302 7405 s = bfd_get_linker_section
845b51d6
PB		 7406 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7407
7408 BFD_ASSERT (s != NULL);
7409
7410 /* Add symbol for veneer. */
21d799b5
NC		 7411 tmp_name = (char *)
7412 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
845b51d6 7413 BFD_ASSERT (tmp_name);
906e58ca 7414
845b51d6 7415 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7416
845b51d6
PB		 7417 myh = elf_link_hash_lookup
7418 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7419
845b51d6 7420 BFD_ASSERT (myh == NULL);
906e58ca 7421
845b51d6
PB		 7422 bh = NULL;
7423 val = globals->bx_glue_size;
7424 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7425 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7426 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7427
7428 myh = (struct elf_link_hash_entry *) bh;
7429 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7430 myh->forced_local = 1;
7431
7432 s->size += ARM_BX_VENEER_SIZE;
7433 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7434 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7435}
7436
7437
c7b8f16e
JB		 7438/* Add an entry to the code/data map for section SEC. */
7439
7440static void
7441elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7442{
7443 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7444 unsigned int newidx;
906e58ca 7445
c7b8f16e
JB		 7446 if (sec_data->map == NULL)
7447 {
21d799b5 7448 sec_data->map = (elf32_arm_section_map *)
99059e56 7449 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7450 sec_data->mapcount = 0;
7451 sec_data->mapsize = 1;
7452 }
906e58ca 7453
c7b8f16e 7454 newidx = sec_data->mapcount++;
906e58ca 7455
c7b8f16e
JB		 7456 if (sec_data->mapcount > sec_data->mapsize)
7457 {
7458 sec_data->mapsize *= 2;
21d799b5 7459 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7460 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7461 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7462 }
7463
7464 if (sec_data->map)
7465 {
7466 sec_data->map[newidx].vma = vma;
7467 sec_data->map[newidx].type = type;
c7b8f16e 7468 }
c7b8f16e
JB		 7469}
7470
7471
7472/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7473 veneers are handled for now. */
7474
7475static bfd_vma
7476record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7477 elf32_vfp11_erratum_list *branch,
7478 bfd *branch_bfd,
7479 asection *branch_sec,
7480 unsigned int offset)
c7b8f16e
JB		 7481{
7482 asection *s;
7483 struct elf32_arm_link_hash_table *hash_table;
7484 char *tmp_name;
7485 struct elf_link_hash_entry *myh;
7486 struct bfd_link_hash_entry *bh;
7487 bfd_vma val;
7488 struct _arm_elf_section_data *sec_data;
c7b8f16e 7489 elf32_vfp11_erratum_list *newerr;
906e58ca 7490
c7b8f16e 7491 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7492 BFD_ASSERT (hash_table != NULL);
7493 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7494
3d4d4302 7495 s = bfd_get_linker_section
c7b8f16e 7496 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7497
c7b8f16e 7498 sec_data = elf32_arm_section_data (s);
906e58ca 7499
c7b8f16e 7500 BFD_ASSERT (s != NULL);
906e58ca 7501
21d799b5 7502 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7503 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e 7504 BFD_ASSERT (tmp_name);
906e58ca 7505
c7b8f16e
JB		 7506 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7507 hash_table->num_vfp11_fixes);
906e58ca 7508
c7b8f16e
JB		 7509 myh = elf_link_hash_lookup
7510 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7511
c7b8f16e 7512 BFD_ASSERT (myh == NULL);
906e58ca 7513
c7b8f16e
JB		 7514 bh = NULL;
7515 val = hash_table->vfp11_erratum_glue_size;
7516 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7517 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7518 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7519
7520 myh = (struct elf_link_hash_entry *) bh;
7521 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7522 myh->forced_local = 1;
7523
7524 /* Link veneer back to calling location. */
c7e2358a 7525 sec_data->erratumcount += 1;
21d799b5
NC		 7526 newerr = (elf32_vfp11_erratum_list *)
7527 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7528
c7b8f16e
JB		 7529 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7530 newerr->vma = -1;
7531 newerr->u.v.branch = branch;
7532 newerr->u.v.id = hash_table->num_vfp11_fixes;
7533 branch->u.b.veneer = newerr;
7534
7535 newerr->next = sec_data->erratumlist;
7536 sec_data->erratumlist = newerr;
7537
7538 /* A symbol for the return from the veneer. */
7539 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7540 hash_table->num_vfp11_fixes);
7541
7542 myh = elf_link_hash_lookup
7543 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7544
c7b8f16e
JB		 7545 if (myh != NULL)
7546 abort ();
7547
7548 bh = NULL;
7549 val = offset + 4;
7550 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7551 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7552
c7b8f16e
JB		 7553 myh = (struct elf_link_hash_entry *) bh;
7554 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7555 myh->forced_local = 1;
7556
7557 free (tmp_name);
906e58ca 7558
c7b8f16e
JB		 7559 /* Generate a mapping symbol for the veneer section, and explicitly add an
7560 entry for that symbol to the code/data map for the section. */
7561 if (hash_table->vfp11_erratum_glue_size == 0)
7562 {
7563 bh = NULL;
7564 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7565 ever requires this erratum fix. */
c7b8f16e
JB		 7566 _bfd_generic_link_add_one_symbol (link_info,
7567 hash_table->bfd_of_glue_owner, "$a",
7568 BSF_LOCAL, s, 0, NULL,
99059e56 7569 TRUE, FALSE, &bh);
c7b8f16e
JB		 7570
7571 myh = (struct elf_link_hash_entry *) bh;
7572 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7573 myh->forced_local = 1;
906e58ca 7574
c7b8f16e 7575 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7576 BFDs. We must make a note of this generated mapping symbol
7577 ourselves so that code byteswapping works properly in
7578 elf32_arm_write_section. */
c7b8f16e
JB		 7579 elf32_arm_section_map_add (s, 'a', 0);
7580 }
906e58ca 7581
c7b8f16e
JB		 7582 s->size += VFP11_ERRATUM_VENEER_SIZE;
7583 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7584 hash_table->num_vfp11_fixes++;
906e58ca 7585
c7b8f16e
JB		 7586 /* The offset of the veneer. */
7587 return val;
7588}
7589
a504d23a
LA		 7590/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7591 veneers need to be handled because used only in Cortex-M. */
7592
7593static bfd_vma
7594record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7595 elf32_stm32l4xx_erratum_list *branch,
7596 bfd *branch_bfd,
7597 asection *branch_sec,
7598 unsigned int offset,
7599 bfd_size_type veneer_size)
7600{
7601 asection *s;
7602 struct elf32_arm_link_hash_table *hash_table;
7603 char *tmp_name;
7604 struct elf_link_hash_entry *myh;
7605 struct bfd_link_hash_entry *bh;
7606 bfd_vma val;
7607 struct _arm_elf_section_data *sec_data;
7608 elf32_stm32l4xx_erratum_list *newerr;
7609
7610 hash_table = elf32_arm_hash_table (link_info);
7611 BFD_ASSERT (hash_table != NULL);
7612 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7613
7614 s = bfd_get_linker_section
7615 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7616
7617 BFD_ASSERT (s != NULL);
7618
7619 sec_data = elf32_arm_section_data (s);
7620
7621 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7622 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
a504d23a
LA		 7623 BFD_ASSERT (tmp_name);
7624
7625 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7626 hash_table->num_stm32l4xx_fixes);
7627
7628 myh = elf_link_hash_lookup
7629 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7630
7631 BFD_ASSERT (myh == NULL);
7632
7633 bh = NULL;
7634 val = hash_table->stm32l4xx_erratum_glue_size;
7635 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7636 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7637 NULL, TRUE, FALSE, &bh);
7638
7639 myh = (struct elf_link_hash_entry *) bh;
7640 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7641 myh->forced_local = 1;
7642
7643 /* Link veneer back to calling location. */
7644 sec_data->stm32l4xx_erratumcount += 1;
7645 newerr = (elf32_stm32l4xx_erratum_list *)
7646 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7647
7648 newerr->type = STM32L4XX_ERRATUM_VENEER;
7649 newerr->vma = -1;
7650 newerr->u.v.branch = branch;
7651 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7652 branch->u.b.veneer = newerr;
7653
7654 newerr->next = sec_data->stm32l4xx_erratumlist;
7655 sec_data->stm32l4xx_erratumlist = newerr;
7656
7657 /* A symbol for the return from the veneer. */
7658 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7659 hash_table->num_stm32l4xx_fixes);
7660
7661 myh = elf_link_hash_lookup
7662 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7663
7664 if (myh != NULL)
7665 abort ();
7666
7667 bh = NULL;
7668 val = offset + 4;
7669 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7670 branch_sec, val, NULL, TRUE, FALSE, &bh);
7671
7672 myh = (struct elf_link_hash_entry *) bh;
7673 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7674 myh->forced_local = 1;
7675
7676 free (tmp_name);
7677
7678 /* Generate a mapping symbol for the veneer section, and explicitly add an
7679 entry for that symbol to the code/data map for the section. */
7680 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7681 {
7682 bh = NULL;
7683 /* Creates a THUMB symbol since there is no other choice. */
7684 _bfd_generic_link_add_one_symbol (link_info,
7685 hash_table->bfd_of_glue_owner, "$t",
7686 BSF_LOCAL, s, 0, NULL,
7687 TRUE, FALSE, &bh);
7688
7689 myh = (struct elf_link_hash_entry *) bh;
7690 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7691 myh->forced_local = 1;
7692
7693 /* The elf32_arm_init_maps function only cares about symbols from input
7694 BFDs. We must make a note of this generated mapping symbol
7695 ourselves so that code byteswapping works properly in
7696 elf32_arm_write_section. */
7697 elf32_arm_section_map_add (s, 't', 0);
7698 }
7699
7700 s->size += veneer_size;
7701 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7702 hash_table->num_stm32l4xx_fixes++;
7703
7704 /* The offset of the veneer. */
7705 return val;
7706}
7707
8029a119 7708#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7709 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7710 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7711
7712/* Create a fake section for use by the ARM backend of the linker. */
7713
7714static bfd_boolean
7715arm_make_glue_section (bfd * abfd, const char * name)
7716{
7717 asection * sec;
7718
3d4d4302 7719 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7720 if (sec != NULL)
7721 /* Already made. */
7722 return TRUE;
7723
3d4d4302 7724 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7725
7726 if (sec == NULL
fd361982 7727 || !bfd_set_section_alignment (sec, 2))
8029a119
NC		 7728 return FALSE;
7729
7730 /* Set the gc mark to prevent the section from being removed by garbage
7731 collection, despite the fact that no relocs refer to this section. */
7732 sec->gc_mark = 1;
7733
7734 return TRUE;
7735}
7736
1db37fe6
YG		 7737/* Set size of .plt entries. This function is called from the
7738 linker scripts in ld/emultempl/{armelf}.em. */
7739
7740void
7741bfd_elf32_arm_use_long_plt (void)
7742{
7743 elf32_arm_use_long_plt_entry = TRUE;
7744}
7745
8afb0e02
NC		 7746/* Add the glue sections to ABFD. This function is called from the
7747 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7748
b34976b6 7749bfd_boolean
57e8b36a
NC		 7750bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7751 struct bfd_link_info *info)
252b5132 7752{
a504d23a
LA		 7753 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7754 bfd_boolean dostm32l4xx = globals
7755 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7756 bfd_boolean addglue;
7757
8afb0e02
NC		 7758 /* If we are only performing a partial
7759 link do not bother adding the glue. */
0e1862bb 7760 if (bfd_link_relocatable (info))
b34976b6 7761 return TRUE;
252b5132 7762
a504d23a 7763 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7764 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7765 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7766 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7767
7768 if (!dostm32l4xx)
7769 return addglue;
7770
7771 return addglue
7772 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7773}
7774
daa4adae
TP		 7775/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7776 ensures they are not marked for deletion by
7777 strip_excluded_output_sections () when veneers are going to be created
7778 later. Not doing so would trigger assert on empty section size in
7779 lang_size_sections_1 (). */
7780
7781void
7782bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7783{
7784 enum elf32_arm_stub_type stub_type;
7785
7786 /* If we are only performing a partial
7787 link do not bother adding the glue. */
7788 if (bfd_link_relocatable (info))
7789 return;
7790
7791 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7792 {
7793 asection *out_sec;
7794 const char *out_sec_name;
7795
7796 if (!arm_dedicated_stub_output_section_required (stub_type))
7797 continue;
7798
7799 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7800 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7801 if (out_sec != NULL)
7802 out_sec->flags |= SEC_KEEP;
7803 }
7804}
7805
8afb0e02
NC		 7806/* Select a BFD to be used to hold the sections used by the glue code.
7807 This function is called from the linker scripts in ld/emultempl/
8029a119 7808 {armelf/pe}.em. */
8afb0e02 7809
b34976b6 7810bfd_boolean
57e8b36a 7811bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7812{
7813 struct elf32_arm_link_hash_table *globals;
7814
7815 /* If we are only performing a partial link
7816 do not bother getting a bfd to hold the glue. */
0e1862bb 7817 if (bfd_link_relocatable (info))
b34976b6 7818 return TRUE;
8afb0e02 7819
b7693d02
DJ		 7820 /* Make sure we don't attach the glue sections to a dynamic object. */
7821 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7822
8afb0e02 7823 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7824 BFD_ASSERT (globals != NULL);
7825
7826 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7827 return TRUE;
8afb0e02 7828
252b5132
RH		 7829 /* Save the bfd for later use. */
7830 globals->bfd_of_glue_owner = abfd;
cedb70c5 7831
b34976b6 7832 return TRUE;
252b5132
RH		 7833}
7834
906e58ca
NC		 7835static void
7836check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7837{
2de70689
MGD		 7838 int cpu_arch;
7839
b38cadfb 7840 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7841 Tag_CPU_arch);
7842
7843 if (globals->fix_arm1176)
7844 {
7845 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7846 globals->use_blx = 1;
7847 }
7848 else
7849 {
7850 if (cpu_arch > TAG_CPU_ARCH_V4T)
7851 globals->use_blx = 1;
7852 }
39b41c9c
PB		 7853}
7854
b34976b6 7855bfd_boolean
57e8b36a 7856bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7857 struct bfd_link_info *link_info)
252b5132
RH		 7858{
7859 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7860 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7861 Elf_Internal_Rela *irel, *irelend;
7862 bfd_byte *contents = NULL;
252b5132
RH		 7863
7864 asection *sec;
7865 struct elf32_arm_link_hash_table *globals;
7866
7867 /* If we are only performing a partial link do not bother
7868 to construct any glue. */
0e1862bb 7869 if (bfd_link_relocatable (link_info))
b34976b6 7870 return TRUE;
252b5132 7871
39ce1a6a
NC		 7872 /* Here we have a bfd that is to be included on the link. We have a
7873 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7874 globals = elf32_arm_hash_table (link_info);
252b5132 7875 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7876
7877 check_use_blx (globals);
252b5132 7878
d504ffc8 7879 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7880 {
90b6238f 7881 _bfd_error_handler (_("%pB: BE8 images only valid in big-endian mode"),
d003868e 7882 abfd);
e489d0ae
PB		 7883 return FALSE;
7884 }
f21f3fe0 7885
39ce1a6a
NC		 7886 /* PR 5398: If we have not decided to include any loadable sections in
7887 the output then we will not have a glue owner bfd. This is OK, it
7888 just means that there is nothing else for us to do here. */
7889 if (globals->bfd_of_glue_owner == NULL)
7890 return TRUE;
7891
252b5132
RH		 7892 /* Rummage around all the relocs and map the glue vectors. */
7893 sec = abfd->sections;
7894
7895 if (sec == NULL)
b34976b6 7896 return TRUE;
252b5132
RH		 7897
7898 for (; sec != NULL; sec = sec->next)
7899 {
7900 if (sec->reloc_count == 0)
7901 continue;
7902
2f475487
AM		 7903 if ((sec->flags & SEC_EXCLUDE) != 0)
7904 continue;
7905
0ffa91dd 7906 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7907
9b485d32 7908 /* Load the relocs. */
6cdc0ccc 7909 internal_relocs
906e58ca 7910 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7911
6cdc0ccc
AM		 7912 if (internal_relocs == NULL)
7913 goto error_return;
252b5132 7914
6cdc0ccc
AM		 7915 irelend = internal_relocs + sec->reloc_count;
7916 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7917 {
7918 long r_type;
7919 unsigned long r_index;
252b5132
RH		 7920
7921 struct elf_link_hash_entry *h;
7922
7923 r_type = ELF32_R_TYPE (irel->r_info);
7924 r_index = ELF32_R_SYM (irel->r_info);
7925
9b485d32 7926 /* These are the only relocation types we care about. */
ba96a88f 7927 if ( r_type != R_ARM_PC24
845b51d6 7928 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7929 continue;
7930
7931 /* Get the section contents if we haven't done so already. */
7932 if (contents == NULL)
7933 {
7934 /* Get cached copy if it exists. */
7935 if (elf_section_data (sec)->this_hdr.contents != NULL)
7936 contents = elf_section_data (sec)->this_hdr.contents;
7937 else
7938 {
7939 /* Go get them off disk. */
57e8b36a 7940 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7941 goto error_return;
7942 }
7943 }
7944
845b51d6
PB		 7945 if (r_type == R_ARM_V4BX)
7946 {
7947 int reg;
7948
7949 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7950 record_arm_bx_glue (link_info, reg);
7951 continue;
7952 }
7953
a7c10850 7954 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7955 h = NULL;
7956
9b485d32 7957 /* We don't care about local symbols. */
252b5132
RH		 7958 if (r_index < symtab_hdr->sh_info)
7959 continue;
7960
9b485d32 7961 /* This is an external symbol. */
252b5132
RH		 7962 r_index -= symtab_hdr->sh_info;
7963 h = (struct elf_link_hash_entry *)
7964 elf_sym_hashes (abfd)[r_index];
7965
7966 /* If the relocation is against a static symbol it must be within
7967 the current section and so cannot be a cross ARM/Thumb relocation. */
7968 if (h == NULL)
7969 continue;
7970
d504ffc8
DJ		 7971 /* If the call will go through a PLT entry then we do not need
7972 glue. */
362d30a1 7973 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7974 continue;
7975
252b5132
RH		 7976 switch (r_type)
7977 {
7978 case R_ARM_PC24:
7979 /* This one is a call from arm code. We need to look up
99059e56
RM		 7980 the target of the call. If it is a thumb target, we
7981 insert glue. */
39d911fc
TP		 7982 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7983 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7984 record_arm_to_thumb_glue (link_info, h);
7985 break;
7986
252b5132 7987 default:
c6596c5e 7988 abort ();
252b5132
RH		 7989 }
7990 }
6cdc0ccc
AM		 7991
7992 if (contents != NULL
7993 && elf_section_data (sec)->this_hdr.contents != contents)
7994 free (contents);
7995 contents = NULL;
7996
7997 if (internal_relocs != NULL
7998 && elf_section_data (sec)->relocs != internal_relocs)
7999 free (internal_relocs);
8000 internal_relocs = NULL;
252b5132
RH		 8001 }
8002
b34976b6 8003 return TRUE;
9a5aca8c 8004
dc1e8a47 8005 error_return:
6cdc0ccc
AM		 8006 if (contents != NULL
8007 && elf_section_data (sec)->this_hdr.contents != contents)
8008 free (contents);
8009 if (internal_relocs != NULL
8010 && elf_section_data (sec)->relocs != internal_relocs)
8011 free (internal_relocs);
9a5aca8c 8012
b34976b6 8013 return FALSE;
252b5132 8014}
7e392df6 8015#endif
252b5132 8016
eb043451 8017
c7b8f16e
JB		 8018/* Initialise maps of ARM/Thumb/data for input BFDs. */
8019
8020void
8021bfd_elf32_arm_init_maps (bfd *abfd)
8022{
8023 Elf_Internal_Sym *isymbuf;
8024 Elf_Internal_Shdr *hdr;
8025 unsigned int i, localsyms;
8026
af1f4419
NC		 8027 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
8028 if (! is_arm_elf (abfd))
8029 return;
8030
c7b8f16e
JB		 8031 if ((abfd->flags & DYNAMIC) != 0)
8032 return;
8033
0ffa91dd 8034 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 8035 localsyms = hdr->sh_info;
8036
8037 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
8038 should contain the number of local symbols, which should come before any
8039 global symbols. Mapping symbols are always local. */
8040 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
8041 NULL);
8042
8043 /* No internal symbols read? Skip this BFD. */
8044 if (isymbuf == NULL)
8045 return;
8046
8047 for (i = 0; i < localsyms; i++)
8048 {
8049 Elf_Internal_Sym *isym = &isymbuf[i];
8050 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
8051 const char *name;
906e58ca 8052
c7b8f16e 8053 if (sec != NULL
99059e56
RM		 8054 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
8055 {
8056 name = bfd_elf_string_from_elf_section (abfd,
8057 hdr->sh_link, isym->st_name);
906e58ca 8058
99059e56 8059 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 8060 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 8061 elf32_arm_section_map_add (sec, name[1], isym->st_value);
8062 }
c7b8f16e
JB		 8063 }
8064}
8065
8066
48229727
JB		 8067/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
8068 say what they wanted. */
8069
8070void
8071bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
8072{
8073 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8074 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8075
4dfe6ac6
NC		 8076 if (globals == NULL)
8077 return;
8078
48229727
JB		 8079 if (globals->fix_cortex_a8 == -1)
8080 {
8081 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
8082 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
8083 && (out_attr[Tag_CPU_arch_profile].i == 'A'
8084 || out_attr[Tag_CPU_arch_profile].i == 0))
8085 globals->fix_cortex_a8 = 1;
8086 else
8087 globals->fix_cortex_a8 = 0;
8088 }
8089}
8090
8091
c7b8f16e
JB		 8092void
8093bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
8094{
8095 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 8096 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 8097
4dfe6ac6
NC		 8098 if (globals == NULL)
8099 return;
c7b8f16e
JB		 8100 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8101 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
8102 {
8103 switch (globals->vfp11_fix)
99059e56
RM		 8104 {
8105 case BFD_ARM_VFP11_FIX_DEFAULT:
8106 case BFD_ARM_VFP11_FIX_NONE:
8107 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8108 break;
8109
8110 default:
8111 /* Give a warning, but do as the user requests anyway. */
871b3ab2 8112 _bfd_error_handler (_("%pB: warning: selected VFP11 erratum "
99059e56
RM		 8113 "workaround is not necessary for target architecture"), obfd);
8114 }
c7b8f16e
JB		 8115 }
8116 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
8117 /* For earlier architectures, we might need the workaround, but do not
8118 enable it by default. If users is running with broken hardware, they
8119 must enable the erratum fix explicitly. */
8120 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8121}
8122
a504d23a
LA		 8123void
8124bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
8125{
8126 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8127 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8128
8129 if (globals == NULL)
8130 return;
8131
8132 /* We assume only Cortex-M4 may require the fix. */
8133 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
8134 || out_attr[Tag_CPU_arch_profile].i != 'M')
8135 {
8136 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
8137 /* Give a warning, but do as the user requests anyway. */
4eca0228 8138 _bfd_error_handler
871b3ab2 8139 (_("%pB: warning: selected STM32L4XX erratum "
a504d23a
LA		 8140 "workaround is not necessary for target architecture"), obfd);
8141 }
8142}
c7b8f16e 8143
906e58ca
NC		 8144enum bfd_arm_vfp11_pipe
8145{
c7b8f16e
JB		 8146 VFP11_FMAC,
8147 VFP11_LS,
8148 VFP11_DS,
8149 VFP11_BAD
8150};
8151
8152/* Return a VFP register number. This is encoded as RX:X for single-precision
8153 registers, or X:RX for double-precision registers, where RX is the group of
8154 four bits in the instruction encoding and X is the single extension bit.
8155 RX and X fields are specified using their lowest (starting) bit. The return
8156 value is:
8157
8158 0...31: single-precision registers s0...s31
8159 32...63: double-precision registers d0...d31.
906e58ca 8160
c7b8f16e
JB		 8161 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8162 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 8163
c7b8f16e
JB		 8164static unsigned int
8165bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 8166 unsigned int x)
c7b8f16e
JB		 8167{
8168 if (is_double)
8169 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
8170 else
8171 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
8172}
8173
8174/* Set bits in *WMASK according to a register number REG as encoded by
8175 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8176
8177static void
8178bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
8179{
8180 if (reg < 32)
8181 *wmask |= 1 << reg;
8182 else if (reg < 48)
8183 *wmask |= 3 << ((reg - 32) * 2);
8184}
8185
8186/* Return TRUE if WMASK overwrites anything in REGS. */
8187
8188static bfd_boolean
8189bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
8190{
8191 int i;
906e58ca 8192
c7b8f16e
JB		 8193 for (i = 0; i < numregs; i++)
8194 {
8195 unsigned int reg = regs[i];
8196
8197 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 8198 return TRUE;
906e58ca 8199
c7b8f16e
JB		 8200 reg -= 32;
8201
8202 if (reg >= 16)
99059e56 8203 continue;
906e58ca 8204
c7b8f16e 8205 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 8206 return TRUE;
c7b8f16e 8207 }
906e58ca 8208
c7b8f16e
JB		 8209 return FALSE;
8210}
8211
8212/* In this function, we're interested in two things: finding input registers
8213 for VFP data-processing instructions, and finding the set of registers which
8214 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8215 hold the written set, so FLDM etc. are easy to deal with (we're only
8216 interested in 32 SP registers or 16 dp registers, due to the VFP version
8217 implemented by the chip in question). DP registers are marked by setting
8218 both SP registers in the write mask). */
8219
8220static enum bfd_arm_vfp11_pipe
8221bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 8222 int *numregs)
c7b8f16e 8223{
91d6fa6a 8224 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 8225 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
8226
8227 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
8228 {
8229 unsigned int pqrs;
8230 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8231 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
8232
8233 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 8234 | ((insn & 0x00300000) >> 19)
8235 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 8236
8237 switch (pqrs)
99059e56
RM		 8238 {
8239 case 0: /* fmac[sd]. */
8240 case 1: /* fnmac[sd]. */
8241 case 2: /* fmsc[sd]. */
8242 case 3: /* fnmsc[sd]. */
8243 vpipe = VFP11_FMAC;
8244 bfd_arm_vfp11_write_mask (destmask, fd);
8245 regs[0] = fd;
8246 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8247 regs[2] = fm;
8248 *numregs = 3;
8249 break;
8250
8251 case 4: /* fmul[sd]. */
8252 case 5: /* fnmul[sd]. */
8253 case 6: /* fadd[sd]. */
8254 case 7: /* fsub[sd]. */
8255 vpipe = VFP11_FMAC;
8256 goto vfp_binop;
8257
8258 case 8: /* fdiv[sd]. */
8259 vpipe = VFP11_DS;
8260 vfp_binop:
8261 bfd_arm_vfp11_write_mask (destmask, fd);
8262 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8263 regs[1] = fm;
8264 *numregs = 2;
8265 break;
8266
8267 case 15: /* extended opcode. */
8268 {
8269 unsigned int extn = ((insn >> 15) & 0x1e)
8270 | ((insn >> 7) & 1);
8271
8272 switch (extn)
8273 {
8274 case 0: /* fcpy[sd]. */
8275 case 1: /* fabs[sd]. */
8276 case 2: /* fneg[sd]. */
8277 case 8: /* fcmp[sd]. */
8278 case 9: /* fcmpe[sd]. */
8279 case 10: /* fcmpz[sd]. */
8280 case 11: /* fcmpez[sd]. */
8281 case 16: /* fuito[sd]. */
8282 case 17: /* fsito[sd]. */
8283 case 24: /* ftoui[sd]. */
8284 case 25: /* ftouiz[sd]. */
8285 case 26: /* ftosi[sd]. */
8286 case 27: /* ftosiz[sd]. */
8287 /* These instructions will not bounce due to underflow. */
8288 *numregs = 0;
8289 vpipe = VFP11_FMAC;
8290 break;
8291
8292 case 3: /* fsqrt[sd]. */
8293 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8294 registers to cause the erratum in previous instructions. */
8295 bfd_arm_vfp11_write_mask (destmask, fd);
8296 vpipe = VFP11_DS;
8297 break;
8298
8299 case 15: /* fcvt{ds,sd}. */
8300 {
8301 int rnum = 0;
8302
8303 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 8304
8305 /* Only FCVTSD can underflow. */
99059e56
RM		 8306 if ((insn & 0x100) != 0)
8307 regs[rnum++] = fm;
c7b8f16e 8308
99059e56 8309 *numregs = rnum;
c7b8f16e 8310
99059e56
RM		 8311 vpipe = VFP11_FMAC;
8312 }
8313 break;
c7b8f16e 8314
99059e56
RM		 8315 default:
8316 return VFP11_BAD;
8317 }
8318 }
8319 break;
c7b8f16e 8320
99059e56
RM		 8321 default:
8322 return VFP11_BAD;
8323 }
c7b8f16e
JB		 8324 }
8325 /* Two-register transfer. */
8326 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
8327 {
8328 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 8329
c7b8f16e
JB		 8330 if ((insn & 0x100000) == 0)
8331 {
99059e56
RM		 8332 if (is_double)
8333 bfd_arm_vfp11_write_mask (destmask, fm);
8334 else
8335 {
8336 bfd_arm_vfp11_write_mask (destmask, fm);
8337 bfd_arm_vfp11_write_mask (destmask, fm + 1);
8338 }
c7b8f16e
JB		 8339 }
8340
91d6fa6a 8341 vpipe = VFP11_LS;
c7b8f16e
JB		 8342 }
8343 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
8344 {
8345 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8346 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 8347
c7b8f16e 8348 switch (puw)
99059e56
RM		 8349 {
8350 case 0: /* Two-reg transfer. We should catch these above. */
8351 abort ();
906e58ca 8352
99059e56
RM		 8353 case 2: /* fldm[sdx]. */
8354 case 3:
8355 case 5:
8356 {
8357 unsigned int i, offset = insn & 0xff;
c7b8f16e 8358
99059e56
RM		 8359 if (is_double)
8360 offset >>= 1;
c7b8f16e 8361
99059e56
RM		 8362 for (i = fd; i < fd + offset; i++)
8363 bfd_arm_vfp11_write_mask (destmask, i);
8364 }
8365 break;
906e58ca 8366
99059e56
RM		 8367 case 4: /* fld[sd]. */
8368 case 6:
8369 bfd_arm_vfp11_write_mask (destmask, fd);
8370 break;
906e58ca 8371
99059e56
RM		 8372 default:
8373 return VFP11_BAD;
8374 }
c7b8f16e 8375
91d6fa6a 8376 vpipe = VFP11_LS;
c7b8f16e
JB		 8377 }
8378 /* Single-register transfer. Note L==0. */
8379 else if ((insn & 0x0f100e10) == 0x0e000a10)
8380 {
8381 unsigned int opcode = (insn >> 21) & 7;
8382 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8383
8384 switch (opcode)
99059e56
RM		 8385 {
8386 case 0: /* fmsr/fmdlr. */
8387 case 1: /* fmdhr. */
8388 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8389 destination register. I don't know if this is exactly right,
8390 but it is the conservative choice. */
8391 bfd_arm_vfp11_write_mask (destmask, fn);
8392 break;
8393
8394 case 7: /* fmxr. */
8395 break;
8396 }
c7b8f16e 8397
91d6fa6a 8398 vpipe = VFP11_LS;
c7b8f16e
JB		 8399 }
8400
91d6fa6a 8401 return vpipe;
c7b8f16e
JB		 8402}
8403
8404
8405static int elf32_arm_compare_mapping (const void * a, const void * b);
8406
8407
8408/* Look for potentially-troublesome code sequences which might trigger the
8409 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8410 (available from ARM) for details of the erratum. A short version is
8411 described in ld.texinfo. */
8412
8413bfd_boolean
8414bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8415{
8416 asection *sec;
8417 bfd_byte *contents = NULL;
8418 int state = 0;
8419 int regs[3], numregs = 0;
8420 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8421 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8422
4dfe6ac6
NC		 8423 if (globals == NULL)
8424 return FALSE;
8425
c7b8f16e
JB		 8426 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8427 The states transition as follows:
906e58ca 8428
c7b8f16e 8429 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8430 A VFP FMAC-pipeline instruction has been seen. Fill
8431 regs[0]..regs[numregs-1] with its input operands. Remember this
8432 instruction in 'first_fmac'.
c7b8f16e
JB		 8433
8434 1 -> 2
99059e56
RM		 8435 Any instruction, except for a VFP instruction which overwrites
8436 regs[*].
906e58ca 8437
c7b8f16e
JB		 8438 1 -> 3 [ -> 0 ] or
8439 2 -> 3 [ -> 0 ]
99059e56
RM		 8440 A VFP instruction has been seen which overwrites any of regs[*].
8441 We must make a veneer! Reset state to 0 before examining next
8442 instruction.
906e58ca 8443
c7b8f16e 8444 2 -> 0
99059e56
RM		 8445 If we fail to match anything in state 2, reset to state 0 and reset
8446 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8447
8448 If the VFP11 vector mode is in use, there must be at least two unrelated
8449 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8450 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8451
8452 /* If we are only performing a partial link do not bother
8453 to construct any glue. */
0e1862bb 8454 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8455 return TRUE;
8456
0ffa91dd
NC		 8457 /* Skip if this bfd does not correspond to an ELF image. */
8458 if (! is_arm_elf (abfd))
8459 return TRUE;
906e58ca 8460
c7b8f16e
JB		 8461 /* We should have chosen a fix type by the time we get here. */
8462 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8463
8464 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8465 return TRUE;
2e6030b9 8466
33a7ffc2
JM		 8467 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8468 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8469 return TRUE;
8470
c7b8f16e
JB		 8471 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8472 {
8473 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8474 struct _arm_elf_section_data *sec_data;
8475
8476 /* If we don't have executable progbits, we're not interested in this
99059e56 8477 section. Also skip if section is to be excluded. */
c7b8f16e 8478 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8479 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8480 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8481 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8482 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8483 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8484 continue;
c7b8f16e
JB		 8485
8486 sec_data = elf32_arm_section_data (sec);
906e58ca 8487
c7b8f16e 8488 if (sec_data->mapcount == 0)
99059e56 8489 continue;
906e58ca 8490
c7b8f16e
JB		 8491 if (elf_section_data (sec)->this_hdr.contents != NULL)
8492 contents = elf_section_data (sec)->this_hdr.contents;
8493 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8494 goto error_return;
8495
8496 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8497 elf32_arm_compare_mapping);
8498
8499 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8500 {
8501 unsigned int span_start = sec_data->map[span].vma;
8502 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8503 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8504 char span_type = sec_data->map[span].type;
8505
8506 /* FIXME: Only ARM mode is supported at present. We may need to
8507 support Thumb-2 mode also at some point. */
8508 if (span_type != 'a')
8509 continue;
8510
8511 for (i = span_start; i < span_end;)
8512 {
8513 unsigned int next_i = i + 4;
8514 unsigned int insn = bfd_big_endian (abfd)
13c9c485
AM		 8515 ? (((unsigned) contents[i] << 24)
8516 | (contents[i + 1] << 16)
8517 | (contents[i + 2] << 8)
8518 | contents[i + 3])
8519 : (((unsigned) contents[i + 3] << 24)
8520 | (contents[i + 2] << 16)
8521 | (contents[i + 1] << 8)
8522 | contents[i]);
99059e56
RM		 8523 unsigned int writemask = 0;
8524 enum bfd_arm_vfp11_pipe vpipe;
8525
8526 switch (state)
8527 {
8528 case 0:
8529 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8530 &numregs);
8531 /* I'm assuming the VFP11 erratum can trigger with denorm
8532 operands on either the FMAC or the DS pipeline. This might
8533 lead to slightly overenthusiastic veneer insertion. */
8534 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8535 {
8536 state = use_vector ? 1 : 2;
8537 first_fmac = i;
8538 veneer_of_insn = insn;
8539 }
8540 break;
8541
8542 case 1:
8543 {
8544 int other_regs[3], other_numregs;
8545 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8546 other_regs,
99059e56
RM		 8547 &other_numregs);
8548 if (vpipe != VFP11_BAD
8549 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8550 numregs))
99059e56
RM		 8551 state = 3;
8552 else
8553 state = 2;
8554 }
8555 break;
8556
8557 case 2:
8558 {
8559 int other_regs[3], other_numregs;
8560 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8561 other_regs,
99059e56
RM		 8562 &other_numregs);
8563 if (vpipe != VFP11_BAD
8564 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8565 numregs))
99059e56
RM		 8566 state = 3;
8567 else
8568 {
8569 state = 0;
8570 next_i = first_fmac + 4;
8571 }
8572 }
8573 break;
8574
8575 case 3:
8576 abort (); /* Should be unreachable. */
8577 }
8578
8579 if (state == 3)
8580 {
8581 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8582 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8583
8584 elf32_arm_section_data (sec)->erratumcount += 1;
8585
8586 newerr->u.b.vfp_insn = veneer_of_insn;
8587
8588 switch (span_type)
8589 {
8590 case 'a':
8591 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8592 break;
8593
8594 default:
8595 abort ();
8596 }
8597
8598 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8599 first_fmac);
8600
99059e56 8601 newerr->vma = -1;
c7b8f16e 8602
99059e56
RM		 8603 newerr->next = sec_data->erratumlist;
8604 sec_data->erratumlist = newerr;
c7b8f16e 8605
99059e56
RM		 8606 state = 0;
8607 }
c7b8f16e 8608
99059e56
RM		 8609 i = next_i;
8610 }
8611 }
906e58ca 8612
c7b8f16e 8613 if (contents != NULL
99059e56
RM		 8614 && elf_section_data (sec)->this_hdr.contents != contents)
8615 free (contents);
c7b8f16e
JB		 8616 contents = NULL;
8617 }
8618
8619 return TRUE;
8620
dc1e8a47 8621 error_return:
c7b8f16e
JB		 8622 if (contents != NULL
8623 && elf_section_data (sec)->this_hdr.contents != contents)
8624 free (contents);
906e58ca 8625
c7b8f16e
JB		 8626 return FALSE;
8627}
8628
8629/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8630 after sections have been laid out, using specially-named symbols. */
8631
8632void
8633bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8634 struct bfd_link_info *link_info)
8635{
8636 asection *sec;
8637 struct elf32_arm_link_hash_table *globals;
8638 char *tmp_name;
906e58ca 8639
0e1862bb 8640 if (bfd_link_relocatable (link_info))
c7b8f16e 8641 return;
2e6030b9
MS		 8642
8643 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8644 if (! is_arm_elf (abfd))
2e6030b9
MS		 8645 return;
8646
c7b8f16e 8647 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8648 if (globals == NULL)
8649 return;
906e58ca 8650
21d799b5 8651 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8652 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
7a0fb7be 8653 BFD_ASSERT (tmp_name);
c7b8f16e
JB		 8654
8655 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8656 {
8657 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8658 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8659
c7b8f16e 8660 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8661 {
8662 struct elf_link_hash_entry *myh;
8663 bfd_vma vma;
8664
8665 switch (errnode->type)
8666 {
8667 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8668 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8669 /* Find veneer symbol. */
8670 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8671 errnode->u.b.veneer->u.v.id);
8672
99059e56
RM		 8673 myh = elf_link_hash_lookup
8674 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8675
a504d23a 8676 if (myh == NULL)
90b6238f
AM		 8677 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8678 abfd, "VFP11", tmp_name);
a504d23a
LA		 8679
8680 vma = myh->root.u.def.section->output_section->vma
8681 + myh->root.u.def.section->output_offset
8682 + myh->root.u.def.value;
8683
8684 errnode->u.b.veneer->vma = vma;
8685 break;
8686
8687 case VFP11_ERRATUM_ARM_VENEER:
8688 case VFP11_ERRATUM_THUMB_VENEER:
8689 /* Find return location. */
8690 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8691 errnode->u.v.id);
8692
8693 myh = elf_link_hash_lookup
8694 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8695
8696 if (myh == NULL)
90b6238f
AM		 8697 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8698 abfd, "VFP11", tmp_name);
a504d23a
LA		 8699
8700 vma = myh->root.u.def.section->output_section->vma
8701 + myh->root.u.def.section->output_offset
8702 + myh->root.u.def.value;
8703
8704 errnode->u.v.branch->vma = vma;
8705 break;
8706
8707 default:
8708 abort ();
8709 }
8710 }
8711 }
8712
8713 free (tmp_name);
8714}
8715
8716/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8717 return locations after sections have been laid out, using
8718 specially-named symbols. */
8719
8720void
8721bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8722 struct bfd_link_info *link_info)
8723{
8724 asection *sec;
8725 struct elf32_arm_link_hash_table *globals;
8726 char *tmp_name;
8727
8728 if (bfd_link_relocatable (link_info))
8729 return;
8730
8731 /* Skip if this bfd does not correspond to an ELF image. */
8732 if (! is_arm_elf (abfd))
8733 return;
8734
8735 globals = elf32_arm_hash_table (link_info);
8736 if (globals == NULL)
8737 return;
8738
8739 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8740 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7a0fb7be 8741 BFD_ASSERT (tmp_name);
a504d23a
LA		 8742
8743 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8744 {
8745 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8746 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8747
8748 for (; errnode != NULL; errnode = errnode->next)
8749 {
8750 struct elf_link_hash_entry *myh;
8751 bfd_vma vma;
8752
8753 switch (errnode->type)
8754 {
8755 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8756 /* Find veneer symbol. */
8757 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8758 errnode->u.b.veneer->u.v.id);
8759
8760 myh = elf_link_hash_lookup
8761 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8762
8763 if (myh == NULL)
90b6238f
AM		 8764 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8765 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8766
8767 vma = myh->root.u.def.section->output_section->vma
8768 + myh->root.u.def.section->output_offset
8769 + myh->root.u.def.value;
8770
8771 errnode->u.b.veneer->vma = vma;
8772 break;
8773
8774 case STM32L4XX_ERRATUM_VENEER:
8775 /* Find return location. */
8776 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8777 errnode->u.v.id);
8778
8779 myh = elf_link_hash_lookup
8780 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8781
8782 if (myh == NULL)
90b6238f
AM		 8783 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8784 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8785
8786 vma = myh->root.u.def.section->output_section->vma
8787 + myh->root.u.def.section->output_offset
8788 + myh->root.u.def.value;
8789
8790 errnode->u.v.branch->vma = vma;
8791 break;
8792
8793 default:
8794 abort ();
8795 }
8796 }
8797 }
8798
8799 free (tmp_name);
8800}
8801
8802static inline bfd_boolean
8803is_thumb2_ldmia (const insn32 insn)
8804{
8805 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8806 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8807 return (insn & 0xffd02000) == 0xe8900000;
8808}
8809
8810static inline bfd_boolean
8811is_thumb2_ldmdb (const insn32 insn)
8812{
8813 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8814 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8815 return (insn & 0xffd02000) == 0xe9100000;
8816}
8817
8818static inline bfd_boolean
8819is_thumb2_vldm (const insn32 insn)
8820{
8821 /* A6.5 Extension register load or store instruction
8822 A7.7.229
9239bbd3
CM		 8823 We look for SP 32-bit and DP 64-bit registers.
8824 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8825 <list> is consecutive 64-bit registers
8826 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8827 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8828 <list> is consecutive 32-bit registers
8829 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8830 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8831 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8832 return
9239bbd3
CM		 8833 (((insn & 0xfe100f00) == 0xec100b00) ||
8834 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8835 && /* (IA without !). */
8836 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8837 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8838 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8839 /* (DB with !). */
8840 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8841}
8842
8843/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8844 VLDM opcode and:
8845 - computes the number and the mode of memory accesses
8846 - decides if the replacement should be done:
8847 . replaces only if > 8-word accesses
8848 . or (testing purposes only) replaces all accesses. */
8849
8850static bfd_boolean
8851stm32l4xx_need_create_replacing_stub (const insn32 insn,
8852 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8853{
9239bbd3 8854 int nb_words = 0;
a504d23a
LA		 8855
8856 /* The field encoding the register list is the same for both LDMIA
8857 and LDMDB encodings. */
8858 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8859 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8860 else if (is_thumb2_vldm (insn))
9239bbd3 8861 nb_words = (insn & 0xff);
a504d23a
LA		 8862
8863 /* DEFAULT mode accounts for the real bug condition situation,
8864 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8865 return
9239bbd3 8866 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8867 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8868}
8869
8870/* Look for potentially-troublesome code sequences which might trigger
8871 the STM STM32L4XX erratum. */
8872
8873bfd_boolean
8874bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8875 struct bfd_link_info *link_info)
8876{
8877 asection *sec;
8878 bfd_byte *contents = NULL;
8879 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8880
8881 if (globals == NULL)
8882 return FALSE;
8883
8884 /* If we are only performing a partial link do not bother
8885 to construct any glue. */
8886 if (bfd_link_relocatable (link_info))
8887 return TRUE;
8888
8889 /* Skip if this bfd does not correspond to an ELF image. */
8890 if (! is_arm_elf (abfd))
8891 return TRUE;
8892
8893 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8894 return TRUE;
8895
8896 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8897 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8898 return TRUE;
8899
8900 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8901 {
8902 unsigned int i, span;
8903 struct _arm_elf_section_data *sec_data;
8904
8905 /* If we don't have executable progbits, we're not interested in this
8906 section. Also skip if section is to be excluded. */
8907 if (elf_section_type (sec) != SHT_PROGBITS
8908 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8909 || (sec->flags & SEC_EXCLUDE) != 0
8910 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8911 || sec->output_section == bfd_abs_section_ptr
8912 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8913 continue;
8914
8915 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8916
a504d23a
LA		 8917 if (sec_data->mapcount == 0)
8918 continue;
c7b8f16e 8919
a504d23a
LA		 8920 if (elf_section_data (sec)->this_hdr.contents != NULL)
8921 contents = elf_section_data (sec)->this_hdr.contents;
8922 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8923 goto error_return;
c7b8f16e 8924
a504d23a
LA		 8925 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8926 elf32_arm_compare_mapping);
c7b8f16e 8927
a504d23a
LA		 8928 for (span = 0; span < sec_data->mapcount; span++)
8929 {
8930 unsigned int span_start = sec_data->map[span].vma;
8931 unsigned int span_end = (span == sec_data->mapcount - 1)
8932 ? sec->size : sec_data->map[span + 1].vma;
8933 char span_type = sec_data->map[span].type;
8934 int itblock_current_pos = 0;
c7b8f16e 8935
a504d23a
LA		 8936 /* Only Thumb2 mode need be supported with this CM4 specific
8937 code, we should not encounter any arm mode eg span_type
8938 != 'a'. */
8939 if (span_type != 't')
8940 continue;
c7b8f16e 8941
a504d23a
LA		 8942 for (i = span_start; i < span_end;)
8943 {
8944 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8945 bfd_boolean insn_32bit = FALSE;
8946 bfd_boolean is_ldm = FALSE;
8947 bfd_boolean is_vldm = FALSE;
8948 bfd_boolean is_not_last_in_it_block = FALSE;
8949
8950 /* The first 16-bits of all 32-bit thumb2 instructions start
8951 with opcode[15..13]=0b111 and the encoded op1 can be anything
8952 except opcode[12..11]!=0b00.
8953 See 32-bit Thumb instruction encoding. */
8954 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8955 insn_32bit = TRUE;
c7b8f16e 8956
a504d23a
LA		 8957 /* Compute the predicate that tells if the instruction
8958 is concerned by the IT block
8959 - Creates an error if there is a ldm that is not
8960 last in the IT block thus cannot be replaced
8961 - Otherwise we can create a branch at the end of the
8962 IT block, it will be controlled naturally by IT
8963 with the proper pseudo-predicate
8964 - So the only interesting predicate is the one that
8965 tells that we are not on the last item of an IT
8966 block. */
8967 if (itblock_current_pos != 0)
8968 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8969
a504d23a
LA		 8970 if (insn_32bit)
8971 {
8972 /* Load the rest of the insn (in manual-friendly order). */
8973 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8974 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8975 is_vldm = is_thumb2_vldm (insn);
8976
8977 /* Veneers are created for (v)ldm depending on
8978 option flags and memory accesses conditions; but
8979 if the instruction is not the last instruction of
8980 an IT block, we cannot create a jump there, so we
8981 bail out. */
5025eb7c
AO		 8982 if ((is_ldm || is_vldm)
8983 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8984 (insn, globals->stm32l4xx_fix))
8985 {
8986 if (is_not_last_in_it_block)
8987 {
4eca0228 8988 _bfd_error_handler
695344c0 8989 /* xgettext:c-format */
871b3ab2 8990 (_("%pB(%pA+%#x): error: multiple load detected"
90b6238f
AM		 8991 " in non-last IT block instruction:"
8992 " STM32L4XX veneer cannot be generated; "
8993 "use gcc option -mrestrict-it to generate"
8994 " only one instruction per IT block"),
d42c267e 8995 abfd, sec, i);
a504d23a
LA		 8996 }
8997 else
8998 {
8999 elf32_stm32l4xx_erratum_list *newerr =
9000 (elf32_stm32l4xx_erratum_list *)
9001 bfd_zmalloc
9002 (sizeof (elf32_stm32l4xx_erratum_list));
9003
9004 elf32_arm_section_data (sec)
9005 ->stm32l4xx_erratumcount += 1;
9006 newerr->u.b.insn = insn;
9007 /* We create only thumb branches. */
9008 newerr->type =
9009 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
9010 record_stm32l4xx_erratum_veneer
9011 (link_info, newerr, abfd, sec,
9012 i,
9013 is_ldm ?
9014 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
9015 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
9016 newerr->vma = -1;
9017 newerr->next = sec_data->stm32l4xx_erratumlist;
9018 sec_data->stm32l4xx_erratumlist = newerr;
9019 }
9020 }
9021 }
9022 else
9023 {
9024 /* A7.7.37 IT p208
9025 IT blocks are only encoded in T1
9026 Encoding T1: IT{x{y{z}}} <firstcond>
9027 1 0 1 1 - 1 1 1 1 - firstcond - mask
9028 if mask = '0000' then see 'related encodings'
9029 We don't deal with UNPREDICTABLE, just ignore these.
9030 There can be no nested IT blocks so an IT block
9031 is naturally a new one for which it is worth
9032 computing its size. */
5025eb7c
AO		 9033 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
9034 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 9035 /* If we have a new IT block we compute its size. */
9036 if (is_newitblock)
9037 {
9038 /* Compute the number of instructions controlled
9039 by the IT block, it will be used to decide
9040 whether we are inside an IT block or not. */
9041 unsigned int mask = insn & 0x000f;
9042 itblock_current_pos = 4 - ctz (mask);
9043 }
9044 }
9045
9046 i += insn_32bit ? 4 : 2;
99059e56
RM		 9047 }
9048 }
a504d23a
LA		 9049
9050 if (contents != NULL
9051 && elf_section_data (sec)->this_hdr.contents != contents)
9052 free (contents);
9053 contents = NULL;
c7b8f16e 9054 }
906e58ca 9055
a504d23a
LA		 9056 return TRUE;
9057
dc1e8a47 9058 error_return:
a504d23a
LA		 9059 if (contents != NULL
9060 && elf_section_data (sec)->this_hdr.contents != contents)
9061 free (contents);
c7b8f16e 9062
a504d23a
LA		 9063 return FALSE;
9064}
c7b8f16e 9065
eb043451
PB		 9066/* Set target relocation values needed during linking. */
9067
9068void
68c39892 9069bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 9070 struct bfd_link_info *link_info,
68c39892 9071 struct elf32_arm_params *params)
eb043451
PB		 9072{
9073 struct elf32_arm_link_hash_table *globals;
9074
9075 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9076 if (globals == NULL)
9077 return;
eb043451 9078
68c39892 9079 globals->target1_is_rel = params->target1_is_rel;
29e9b073
CL		 9080 if (globals->fdpic_p)
9081 globals->target2_reloc = R_ARM_GOT32;
9082 else if (strcmp (params->target2_type, "rel") == 0)
eb043451 9083 globals->target2_reloc = R_ARM_REL32;
68c39892 9084 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 9085 globals->target2_reloc = R_ARM_ABS32;
68c39892 9086 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 9087 globals->target2_reloc = R_ARM_GOT_PREL;
9088 else
9089 {
90b6238f 9090 _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"),
68c39892 9091 params->target2_type);
eb043451 9092 }
68c39892
TP		 9093 globals->fix_v4bx = params->fix_v4bx;
9094 globals->use_blx |= params->use_blx;
9095 globals->vfp11_fix = params->vfp11_denorm_fix;
9096 globals->stm32l4xx_fix = params->stm32l4xx_fix;
e8b09b87
CL		 9097 if (globals->fdpic_p)
9098 globals->pic_veneer = 1;
9099 else
9100 globals->pic_veneer = params->pic_veneer;
68c39892
TP		 9101 globals->fix_cortex_a8 = params->fix_cortex_a8;
9102 globals->fix_arm1176 = params->fix_arm1176;
9103 globals->cmse_implib = params->cmse_implib;
9104 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 9105
0ffa91dd 9106 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 9107 elf_arm_tdata (output_bfd)->no_enum_size_warning
9108 = params->no_enum_size_warning;
9109 elf_arm_tdata (output_bfd)->no_wchar_size_warning
9110 = params->no_wchar_size_warning;
eb043451 9111}
eb043451 9112
12a0a0fd 9113/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 9114
12a0a0fd
PB		 9115static void
9116insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
9117{
9118 bfd_vma upper;
9119 bfd_vma lower;
9120 int reloc_sign;
9121
9122 BFD_ASSERT ((offset & 1) == 0);
9123
9124 upper = bfd_get_16 (abfd, insn);
9125 lower = bfd_get_16 (abfd, insn + 2);
9126 reloc_sign = (offset < 0) ? 1 : 0;
9127 upper = (upper & ~(bfd_vma) 0x7ff)
9128 | ((offset >> 12) & 0x3ff)
9129 | (reloc_sign << 10);
906e58ca 9130 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 9131 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
9132 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
9133 | ((offset >> 1) & 0x7ff);
9134 bfd_put_16 (abfd, upper, insn);
9135 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 9136}
9137
9b485d32
NC		 9138/* Thumb code calling an ARM function. */
9139
252b5132 9140static int
57e8b36a 9141elf32_thumb_to_arm_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9142 const char * name,
9143 bfd * input_bfd,
9144 bfd * output_bfd,
9145 asection * input_section,
9146 bfd_byte * hit_data,
9147 asection * sym_sec,
9148 bfd_vma offset,
9149 bfd_signed_vma addend,
9150 bfd_vma val,
f2a9dd69 9151 char **error_message)
252b5132 9152{
bcbdc74c 9153 asection * s = 0;
dc810e39 9154 bfd_vma my_offset;
252b5132 9155 long int ret_offset;
bcbdc74c
NC		 9156 struct elf_link_hash_entry * myh;
9157 struct elf32_arm_link_hash_table * globals;
252b5132 9158
f2a9dd69 9159 myh = find_thumb_glue (info, name, error_message);
252b5132 9160 if (myh == NULL)
b34976b6 9161 return FALSE;
252b5132
RH		 9162
9163 globals = elf32_arm_hash_table (info);
252b5132
RH		 9164 BFD_ASSERT (globals != NULL);
9165 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9166
9167 my_offset = myh->root.u.def.value;
9168
3d4d4302
AM		 9169 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9170 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 9171
9172 BFD_ASSERT (s != NULL);
9173 BFD_ASSERT (s->contents != NULL);
9174 BFD_ASSERT (s->output_section != NULL);
9175
9176 if ((my_offset & 0x01) == 0x01)
9177 {
9178 if (sym_sec != NULL
9179 && sym_sec->owner != NULL
9180 && !INTERWORK_FLAG (sym_sec->owner))
9181 {
4eca0228 9182 _bfd_error_handler
90b6238f
AM		 9183 (_("%pB(%s): warning: interworking not enabled;"
9184 " first occurrence: %pB: %s call to %s"),
9185 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
252b5132 9186
b34976b6 9187 return FALSE;
252b5132
RH		 9188 }
9189
9190 --my_offset;
9191 myh->root.u.def.value = my_offset;
9192
52ab56c2
PB		 9193 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
9194 s->contents + my_offset);
252b5132 9195
52ab56c2
PB		 9196 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
9197 s->contents + my_offset + 2);
252b5132
RH		 9198
9199 ret_offset =
9b485d32
NC		 9200 /* Address of destination of the stub. */
9201 ((bfd_signed_vma) val)
252b5132 9202 - ((bfd_signed_vma)
57e8b36a
NC		 9203 /* Offset from the start of the current section
9204 to the start of the stubs. */
9b485d32
NC		 9205 (s->output_offset
9206 /* Offset of the start of this stub from the start of the stubs. */
9207 + my_offset
9208 /* Address of the start of the current section. */
9209 + s->output_section->vma)
9210 /* The branch instruction is 4 bytes into the stub. */
9211 + 4
9212 /* ARM branches work from the pc of the instruction + 8. */
9213 + 8);
252b5132 9214
52ab56c2
PB		 9215 put_arm_insn (globals, output_bfd,
9216 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
9217 s->contents + my_offset + 4);
252b5132
RH		 9218 }
9219
9220 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
9221
427bfd90
NC		 9222 /* Now go back and fix up the original BL insn to point to here. */
9223 ret_offset =
9224 /* Address of where the stub is located. */
9225 (s->output_section->vma + s->output_offset + my_offset)
9226 /* Address of where the BL is located. */
57e8b36a
NC		 9227 - (input_section->output_section->vma + input_section->output_offset
9228 + offset)
427bfd90
NC		 9229 /* Addend in the relocation. */
9230 - addend
9231 /* Biassing for PC-relative addressing. */
9232 - 8;
252b5132 9233
12a0a0fd 9234 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 9235
b34976b6 9236 return TRUE;
252b5132
RH		 9237}
9238
a4fd1a8e 9239/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 9240
a4fd1a8e
PB		 9241static struct elf_link_hash_entry *
9242elf32_arm_create_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9243 const char * name,
9244 bfd * input_bfd,
9245 bfd * output_bfd,
9246 asection * sym_sec,
9247 bfd_vma val,
9248 asection * s,
9249 char ** error_message)
252b5132 9250{
dc810e39 9251 bfd_vma my_offset;
252b5132 9252 long int ret_offset;
bcbdc74c
NC		 9253 struct elf_link_hash_entry * myh;
9254 struct elf32_arm_link_hash_table * globals;
252b5132 9255
f2a9dd69 9256 myh = find_arm_glue (info, name, error_message);
252b5132 9257 if (myh == NULL)
a4fd1a8e 9258 return NULL;
252b5132
RH		 9259
9260 globals = elf32_arm_hash_table (info);
252b5132
RH		 9261 BFD_ASSERT (globals != NULL);
9262 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9263
9264 my_offset = myh->root.u.def.value;
252b5132
RH		 9265
9266 if ((my_offset & 0x01) == 0x01)
9267 {
9268 if (sym_sec != NULL
9269 && sym_sec->owner != NULL
9270 && !INTERWORK_FLAG (sym_sec->owner))
9271 {
4eca0228 9272 _bfd_error_handler
90b6238f
AM		 9273 (_("%pB(%s): warning: interworking not enabled;"
9274 " first occurrence: %pB: %s call to %s"),
9275 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
252b5132 9276 }
9b485d32 9277
252b5132
RH		 9278 --my_offset;
9279 myh->root.u.def.value = my_offset;
9280
0e1862bb
L		 9281 if (bfd_link_pic (info)
9282 || globals->root.is_relocatable_executable
27e55c4d 9283 || globals->pic_veneer)
8f6277f5
PB		 9284 {
9285 /* For relocatable objects we can't use absolute addresses,
9286 so construct the address from a relative offset. */
9287 /* TODO: If the offset is small it's probably worth
9288 constructing the address with adds. */
52ab56c2
PB		 9289 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
9290 s->contents + my_offset);
9291 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
9292 s->contents + my_offset + 4);
9293 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
9294 s->contents + my_offset + 8);
8f6277f5
PB		 9295 /* Adjust the offset by 4 for the position of the add,
9296 and 8 for the pipeline offset. */
9297 ret_offset = (val - (s->output_offset
9298 + s->output_section->vma
9299 + my_offset + 12))
9300 | 1;
9301 bfd_put_32 (output_bfd, ret_offset,
9302 s->contents + my_offset + 12);
9303 }
26079076
PB		 9304 else if (globals->use_blx)
9305 {
9306 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
9307 s->contents + my_offset);
9308
9309 /* It's a thumb address. Add the low order bit. */
9310 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
9311 s->contents + my_offset + 4);
9312 }
8f6277f5
PB		 9313 else
9314 {
52ab56c2
PB		 9315 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
9316 s->contents + my_offset);
252b5132 9317
52ab56c2
PB		 9318 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
9319 s->contents + my_offset + 4);
252b5132 9320
8f6277f5
PB		 9321 /* It's a thumb address. Add the low order bit. */
9322 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
9323 s->contents + my_offset + 8);
8029a119
NC		 9324
9325 my_offset += 12;
8f6277f5 9326 }
252b5132
RH		 9327 }
9328
9329 BFD_ASSERT (my_offset <= globals->arm_glue_size);
9330
a4fd1a8e
PB		 9331 return myh;
9332}
9333
9334/* Arm code calling a Thumb function. */
9335
9336static int
9337elf32_arm_to_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 9338 const char * name,
9339 bfd * input_bfd,
9340 bfd * output_bfd,
9341 asection * input_section,
9342 bfd_byte * hit_data,
9343 asection * sym_sec,
9344 bfd_vma offset,
9345 bfd_signed_vma addend,
9346 bfd_vma val,
f2a9dd69 9347 char **error_message)
a4fd1a8e
PB		 9348{
9349 unsigned long int tmp;
9350 bfd_vma my_offset;
9351 asection * s;
9352 long int ret_offset;
9353 struct elf_link_hash_entry * myh;
9354 struct elf32_arm_link_hash_table * globals;
9355
9356 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9357 BFD_ASSERT (globals != NULL);
9358 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9359
3d4d4302
AM		 9360 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9361 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9362 BFD_ASSERT (s != NULL);
9363 BFD_ASSERT (s->contents != NULL);
9364 BFD_ASSERT (s->output_section != NULL);
9365
9366 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 9367 sym_sec, val, s, error_message);
a4fd1a8e
PB		 9368 if (!myh)
9369 return FALSE;
9370
9371 my_offset = myh->root.u.def.value;
252b5132
RH		 9372 tmp = bfd_get_32 (input_bfd, hit_data);
9373 tmp = tmp & 0xFF000000;
9374
9b485d32 9375 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 9376 ret_offset = (s->output_offset
9377 + my_offset
9378 + s->output_section->vma
9379 - (input_section->output_offset
9380 + input_section->output_section->vma
9381 + offset + addend)
9382 - 8);
9a5aca8c 9383
252b5132
RH		 9384 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9385
dc810e39 9386 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9387
b34976b6 9388 return TRUE;
252b5132
RH		 9389}
9390
a4fd1a8e
PB		 9391/* Populate Arm stub for an exported Thumb function. */
9392
9393static bfd_boolean
9394elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9395{
9396 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9397 asection * s;
9398 struct elf_link_hash_entry * myh;
9399 struct elf32_arm_link_hash_entry *eh;
9400 struct elf32_arm_link_hash_table * globals;
9401 asection *sec;
9402 bfd_vma val;
f2a9dd69 9403 char *error_message;
a4fd1a8e 9404
906e58ca 9405 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9406 /* Allocate stubs for exported Thumb functions on v4t. */
9407 if (eh->export_glue == NULL)
9408 return TRUE;
9409
9410 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9411 BFD_ASSERT (globals != NULL);
9412 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9413
3d4d4302
AM		 9414 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9415 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9416 BFD_ASSERT (s != NULL);
9417 BFD_ASSERT (s->contents != NULL);
9418 BFD_ASSERT (s->output_section != NULL);
9419
9420 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9421
9422 BFD_ASSERT (sec->output_section != NULL);
9423
a4fd1a8e
PB		 9424 val = eh->export_glue->root.u.def.value + sec->output_offset
9425 + sec->output_section->vma;
8029a119 9426
a4fd1a8e
PB		 9427 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9428 h->root.u.def.section->owner,
f2a9dd69
DJ		 9429 globals->obfd, sec, val, s,
9430 &error_message);
a4fd1a8e
PB		 9431 BFD_ASSERT (myh);
9432 return TRUE;
9433}
9434
845b51d6
PB		 9435/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9436
9437static bfd_vma
9438elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9439{
9440 bfd_byte *p;
9441 bfd_vma glue_addr;
9442 asection *s;
9443 struct elf32_arm_link_hash_table *globals;
9444
9445 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9446 BFD_ASSERT (globals != NULL);
9447 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9448
3d4d4302
AM		 9449 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9450 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9451 BFD_ASSERT (s != NULL);
9452 BFD_ASSERT (s->contents != NULL);
9453 BFD_ASSERT (s->output_section != NULL);
9454
9455 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9456
9457 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9458
9459 if ((globals->bx_glue_offset[reg] & 1) == 0)
9460 {
9461 p = s->contents + glue_addr;
9462 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9463 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9464 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9465 globals->bx_glue_offset[reg] |= 1;
9466 }
9467
9468 return glue_addr + s->output_section->vma + s->output_offset;
9469}
9470
a4fd1a8e
PB		 9471/* Generate Arm stubs for exported Thumb symbols. */
9472static void
906e58ca 9473elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9474 struct bfd_link_info *link_info)
9475{
9476 struct elf32_arm_link_hash_table * globals;
9477
8029a119
NC		 9478 if (link_info == NULL)
9479 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9480 return;
9481
9482 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9483 if (globals == NULL)
9484 return;
9485
84c08195
PB		 9486 /* If blx is available then exported Thumb symbols are OK and there is
9487 nothing to do. */
a4fd1a8e
PB		 9488 if (globals->use_blx)
9489 return;
9490
9491 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9492 link_info);
9493}
9494
47beaa6a
RS		 9495/* Reserve space for COUNT dynamic relocations in relocation selection
9496 SRELOC. */
9497
9498static void
9499elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9500 bfd_size_type count)
9501{
9502 struct elf32_arm_link_hash_table *htab;
9503
9504 htab = elf32_arm_hash_table (info);
9505 BFD_ASSERT (htab->root.dynamic_sections_created);
9506 if (sreloc == NULL)
9507 abort ();
9508 sreloc->size += RELOC_SIZE (htab) * count;
9509}
9510
34e77a92
RS		 9511/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9512 dynamic, the relocations should go in SRELOC, otherwise they should
9513 go in the special .rel.iplt section. */
9514
9515static void
9516elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9517 bfd_size_type count)
9518{
9519 struct elf32_arm_link_hash_table *htab;
9520
9521 htab = elf32_arm_hash_table (info);
9522 if (!htab->root.dynamic_sections_created)
9523 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9524 else
9525 {
9526 BFD_ASSERT (sreloc != NULL);
9527 sreloc->size += RELOC_SIZE (htab) * count;
9528 }
9529}
9530
47beaa6a
RS		 9531/* Add relocation REL to the end of relocation section SRELOC. */
9532
9533static void
9534elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9535 asection *sreloc, Elf_Internal_Rela *rel)
9536{
9537 bfd_byte *loc;
9538 struct elf32_arm_link_hash_table *htab;
9539
9540 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9541 if (!htab->root.dynamic_sections_created
9542 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9543 sreloc = htab->root.irelplt;
47beaa6a
RS		 9544 if (sreloc == NULL)
9545 abort ();
9546 loc = sreloc->contents;
9547 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9548 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9549 abort ();
9550 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9551}
9552
34e77a92
RS		 9553/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9554 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9555 to .plt. */
9556
9557static void
9558elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9559 bfd_boolean is_iplt_entry,
9560 union gotplt_union *root_plt,
9561 struct arm_plt_info *arm_plt)
9562{
9563 struct elf32_arm_link_hash_table *htab;
9564 asection *splt;
9565 asection *sgotplt;
9566
9567 htab = elf32_arm_hash_table (info);
9568
9569 if (is_iplt_entry)
9570 {
9571 splt = htab->root.iplt;
9572 sgotplt = htab->root.igotplt;
9573
99059e56
RM		 9574 /* NaCl uses a special first entry in .iplt too. */
9575 if (htab->nacl_p && splt->size == 0)
9576 splt->size += htab->plt_header_size;
9577
34e77a92
RS		 9578 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9579 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9580 }
9581 else
9582 {
9583 splt = htab->root.splt;
9584 sgotplt = htab->root.sgotplt;
9585
7801f98f
CL		 9586 if (htab->fdpic_p)
9587 {
9588 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9589 /* For lazy binding, relocations will be put into .rel.plt, in
9590 .rel.got otherwise. */
9591 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9592 if (info->flags & DF_BIND_NOW)
9593 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
9594 else
9595 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9596 }
9597 else
9598 {
9599 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9600 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9601 }
34e77a92
RS		 9602
9603 /* If this is the first .plt entry, make room for the special
9604 first entry. */
9605 if (splt->size == 0)
9606 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9607
9608 htab->next_tls_desc_index++;
34e77a92
RS		 9609 }
9610
9611 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9612 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9613 splt->size += PLT_THUMB_STUB_SIZE;
9614 root_plt->offset = splt->size;
9615 splt->size += htab->plt_entry_size;
9616
9617 if (!htab->symbian_p)
9618 {
9619 /* We also need to make an entry in the .got.plt section, which
9620 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9621 if (is_iplt_entry)
9622 arm_plt->got_offset = sgotplt->size;
9623 else
9624 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
7801f98f
CL		 9625 if (htab->fdpic_p)
9626 /* Function descriptor takes 64 bits in GOT. */
4b24dd1a 9627 sgotplt->size += 8;
7801f98f
CL		 9628 else
9629 sgotplt->size += 4;
34e77a92
RS		 9630 }
9631}
9632
b38cadfb
NC		 9633static bfd_vma
9634arm_movw_immediate (bfd_vma value)
9635{
9636 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9637}
9638
9639static bfd_vma
9640arm_movt_immediate (bfd_vma value)
9641{
9642 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9643}
9644
34e77a92
RS		 9645/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9646 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9647 Otherwise, DYNINDX is the index of the symbol in the dynamic
9648 symbol table and SYM_VALUE is undefined.
9649
9650 ROOT_PLT points to the offset of the PLT entry from the start of its
9651 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9652 bookkeeping information.
34e77a92 9653
57460bcf
NC		 9654 Returns FALSE if there was a problem. */
9655
9656static bfd_boolean
34e77a92
RS		 9657elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9658 union gotplt_union *root_plt,
9659 struct arm_plt_info *arm_plt,
9660 int dynindx, bfd_vma sym_value)
9661{
9662 struct elf32_arm_link_hash_table *htab;
9663 asection *sgot;
9664 asection *splt;
9665 asection *srel;
9666 bfd_byte *loc;
9667 bfd_vma plt_index;
9668 Elf_Internal_Rela rel;
9669 bfd_vma plt_header_size;
9670 bfd_vma got_header_size;
9671
9672 htab = elf32_arm_hash_table (info);
9673
9674 /* Pick the appropriate sections and sizes. */
9675 if (dynindx == -1)
9676 {
9677 splt = htab->root.iplt;
9678 sgot = htab->root.igotplt;
9679 srel = htab->root.irelplt;
9680
9681 /* There are no reserved entries in .igot.plt, and no special
9682 first entry in .iplt. */
9683 got_header_size = 0;
9684 plt_header_size = 0;
9685 }
9686 else
9687 {
9688 splt = htab->root.splt;
9689 sgot = htab->root.sgotplt;
9690 srel = htab->root.srelplt;
9691
9692 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9693 plt_header_size = htab->plt_header_size;
9694 }
9695 BFD_ASSERT (splt != NULL && srel != NULL);
9696
9697 /* Fill in the entry in the procedure linkage table. */
9698 if (htab->symbian_p)
9699 {
9700 BFD_ASSERT (dynindx >= 0);
9701 put_arm_insn (htab, output_bfd,
9702 elf32_arm_symbian_plt_entry[0],
9703 splt->contents + root_plt->offset);
9704 bfd_put_32 (output_bfd,
9705 elf32_arm_symbian_plt_entry[1],
9706 splt->contents + root_plt->offset + 4);
9707
9708 /* Fill in the entry in the .rel.plt section. */
9709 rel.r_offset = (splt->output_section->vma
9710 + splt->output_offset
9711 + root_plt->offset + 4);
9712 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9713
9714 /* Get the index in the procedure linkage table which
9715 corresponds to this symbol. This is the index of this symbol
9716 in all the symbols for which we are making plt entries. The
9717 first entry in the procedure linkage table is reserved. */
9718 plt_index = ((root_plt->offset - plt_header_size)
9719 / htab->plt_entry_size);
9720 }
9721 else
9722 {
9723 bfd_vma got_offset, got_address, plt_address;
9724 bfd_vma got_displacement, initial_got_entry;
9725 bfd_byte * ptr;
9726
9727 BFD_ASSERT (sgot != NULL);
9728
9729 /* Get the offset into the .(i)got.plt table of the entry that
9730 corresponds to this function. */
9731 got_offset = (arm_plt->got_offset & -2);
9732
9733 /* Get the index in the procedure linkage table which
9734 corresponds to this symbol. This is the index of this symbol
9735 in all the symbols for which we are making plt entries.
9736 After the reserved .got.plt entries, all symbols appear in
9737 the same order as in .plt. */
7801f98f 9738 if (htab->fdpic_p)
4b24dd1a
AM		 9739 /* Function descriptor takes 8 bytes. */
9740 plt_index = (got_offset - got_header_size) / 8;
7801f98f 9741 else
4b24dd1a 9742 plt_index = (got_offset - got_header_size) / 4;
34e77a92
RS		 9743
9744 /* Calculate the address of the GOT entry. */
9745 got_address = (sgot->output_section->vma
9746 + sgot->output_offset
9747 + got_offset);
9748
9749 /* ...and the address of the PLT entry. */
9750 plt_address = (splt->output_section->vma
9751 + splt->output_offset
9752 + root_plt->offset);
9753
9754 ptr = splt->contents + root_plt->offset;
0e1862bb 9755 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9756 {
9757 unsigned int i;
9758 bfd_vma val;
9759
9760 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9761 {
9762 val = elf32_arm_vxworks_shared_plt_entry[i];
9763 if (i == 2)
9764 val |= got_address - sgot->output_section->vma;
9765 if (i == 5)
9766 val |= plt_index * RELOC_SIZE (htab);
9767 if (i == 2 || i == 5)
9768 bfd_put_32 (output_bfd, val, ptr);
9769 else
9770 put_arm_insn (htab, output_bfd, val, ptr);
9771 }
9772 }
9773 else if (htab->vxworks_p)
9774 {
9775 unsigned int i;
9776 bfd_vma val;
9777
9778 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9779 {
9780 val = elf32_arm_vxworks_exec_plt_entry[i];
9781 if (i == 2)
9782 val |= got_address;
9783 if (i == 4)
9784 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9785 if (i == 5)
9786 val |= plt_index * RELOC_SIZE (htab);
9787 if (i == 2 || i == 5)
9788 bfd_put_32 (output_bfd, val, ptr);
9789 else
9790 put_arm_insn (htab, output_bfd, val, ptr);
9791 }
9792
9793 loc = (htab->srelplt2->contents
9794 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9795
9796 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9797 referencing the GOT for this PLT entry. */
9798 rel.r_offset = plt_address + 8;
9799 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9800 rel.r_addend = got_offset;
9801 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9802 loc += RELOC_SIZE (htab);
9803
9804 /* Create the R_ARM_ABS32 relocation referencing the
9805 beginning of the PLT for this GOT entry. */
9806 rel.r_offset = got_address;
9807 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9808 rel.r_addend = 0;
9809 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9810 }
b38cadfb
NC		 9811 else if (htab->nacl_p)
9812 {
9813 /* Calculate the displacement between the PLT slot and the
9814 common tail that's part of the special initial PLT slot. */
6034aab8 9815 int32_t tail_displacement
b38cadfb
NC		 9816 = ((splt->output_section->vma + splt->output_offset
9817 + ARM_NACL_PLT_TAIL_OFFSET)
9818 - (plt_address + htab->plt_entry_size + 4));
9819 BFD_ASSERT ((tail_displacement & 3) == 0);
9820 tail_displacement >>= 2;
9821
9822 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9823 || (-tail_displacement & 0xff000000) == 0);
9824
9825 /* Calculate the displacement between the PLT slot and the entry
9826 in the GOT. The offset accounts for the value produced by
9827 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9828 got_displacement = (got_address
99059e56 9829 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9830
9831 /* NaCl does not support interworking at all. */
9832 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9833
9834 put_arm_insn (htab, output_bfd,
9835 elf32_arm_nacl_plt_entry[0]
9836 | arm_movw_immediate (got_displacement),
9837 ptr + 0);
9838 put_arm_insn (htab, output_bfd,
9839 elf32_arm_nacl_plt_entry[1]
9840 | arm_movt_immediate (got_displacement),
9841 ptr + 4);
9842 put_arm_insn (htab, output_bfd,
9843 elf32_arm_nacl_plt_entry[2],
9844 ptr + 8);
9845 put_arm_insn (htab, output_bfd,
9846 elf32_arm_nacl_plt_entry[3]
9847 | (tail_displacement & 0x00ffffff),
9848 ptr + 12);
9849 }
7801f98f
CL		 9850 else if (htab->fdpic_p)
9851 {
59029f57
CL		 9852 const bfd_vma *plt_entry = using_thumb_only(htab)
9853 ? elf32_arm_fdpic_thumb_plt_entry
9854 : elf32_arm_fdpic_plt_entry;
9855
7801f98f
CL		 9856 /* Fill-up Thumb stub if needed. */
9857 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9858 {
9859 put_thumb_insn (htab, output_bfd,
9860 elf32_arm_plt_thumb_stub[0], ptr - 4);
9861 put_thumb_insn (htab, output_bfd,
9862 elf32_arm_plt_thumb_stub[1], ptr - 2);
9863 }
59029f57
CL		 9864 /* As we are using 32 bit instructions even for the Thumb
9865 version, we have to use 'put_arm_insn' instead of
9866 'put_thumb_insn'. */
9867 put_arm_insn(htab, output_bfd, plt_entry[0], ptr + 0);
9868 put_arm_insn(htab, output_bfd, plt_entry[1], ptr + 4);
9869 put_arm_insn(htab, output_bfd, plt_entry[2], ptr + 8);
9870 put_arm_insn(htab, output_bfd, plt_entry[3], ptr + 12);
7801f98f
CL		 9871 bfd_put_32 (output_bfd, got_offset, ptr + 16);
9872
9873 if (!(info->flags & DF_BIND_NOW))
9874 {
9875 /* funcdesc_value_reloc_offset. */
9876 bfd_put_32 (output_bfd,
9877 htab->root.srelplt->reloc_count * RELOC_SIZE (htab),
9878 ptr + 20);
59029f57
CL		 9879 put_arm_insn(htab, output_bfd, plt_entry[6], ptr + 24);
9880 put_arm_insn(htab, output_bfd, plt_entry[7], ptr + 28);
9881 put_arm_insn(htab, output_bfd, plt_entry[8], ptr + 32);
9882 put_arm_insn(htab, output_bfd, plt_entry[9], ptr + 36);
7801f98f
CL		 9883 }
9884 }
57460bcf
NC		 9885 else if (using_thumb_only (htab))
9886 {
eed94f8f 9887 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9888 if (!using_thumb2 (htab))
eed94f8f
NC		 9889 {
9890 /* FIXME: We ought to be able to generate thumb-1 PLT
9891 instructions... */
90b6238f 9892 _bfd_error_handler (_("%pB: warning: thumb-1 mode PLT generation not currently supported"),
eed94f8f
NC		 9893 output_bfd);
9894 return FALSE;
9895 }
57460bcf 9896
eed94f8f
NC		 9897 /* Calculate the displacement between the PLT slot and the entry in
9898 the GOT. The 12-byte offset accounts for the value produced by
9899 adding to pc in the 3rd instruction of the PLT stub. */
9900 got_displacement = got_address - (plt_address + 12);
9901
9902 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9903 instead of 'put_thumb_insn'. */
9904 put_arm_insn (htab, output_bfd,
9905 elf32_thumb2_plt_entry[0]
9906 | ((got_displacement & 0x000000ff) << 16)
9907 | ((got_displacement & 0x00000700) << 20)
9908 | ((got_displacement & 0x00000800) >> 1)
9909 | ((got_displacement & 0x0000f000) >> 12),
9910 ptr + 0);
9911 put_arm_insn (htab, output_bfd,
9912 elf32_thumb2_plt_entry[1]
9913 | ((got_displacement & 0x00ff0000) )
9914 | ((got_displacement & 0x07000000) << 4)
9915 | ((got_displacement & 0x08000000) >> 17)
9916 | ((got_displacement & 0xf0000000) >> 28),
9917 ptr + 4);
9918 put_arm_insn (htab, output_bfd,
9919 elf32_thumb2_plt_entry[2],
9920 ptr + 8);
9921 put_arm_insn (htab, output_bfd,
9922 elf32_thumb2_plt_entry[3],
9923 ptr + 12);
57460bcf 9924 }
34e77a92
RS		 9925 else
9926 {
9927 /* Calculate the displacement between the PLT slot and the
9928 entry in the GOT. The eight-byte offset accounts for the
9929 value produced by adding to pc in the first instruction
9930 of the PLT stub. */
9931 got_displacement = got_address - (plt_address + 8);
9932
34e77a92
RS		 9933 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9934 {
9935 put_thumb_insn (htab, output_bfd,
9936 elf32_arm_plt_thumb_stub[0], ptr - 4);
9937 put_thumb_insn (htab, output_bfd,
9938 elf32_arm_plt_thumb_stub[1], ptr - 2);
9939 }
9940
1db37fe6
YG		 9941 if (!elf32_arm_use_long_plt_entry)
9942 {
9943 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9944
9945 put_arm_insn (htab, output_bfd,
9946 elf32_arm_plt_entry_short[0]
9947 | ((got_displacement & 0x0ff00000) >> 20),
9948 ptr + 0);
9949 put_arm_insn (htab, output_bfd,
9950 elf32_arm_plt_entry_short[1]
9951 | ((got_displacement & 0x000ff000) >> 12),
9952 ptr+ 4);
9953 put_arm_insn (htab, output_bfd,
9954 elf32_arm_plt_entry_short[2]
9955 | (got_displacement & 0x00000fff),
9956 ptr + 8);
34e77a92 9957#ifdef FOUR_WORD_PLT
1db37fe6 9958 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9959#endif
1db37fe6
YG		 9960 }
9961 else
9962 {
9963 put_arm_insn (htab, output_bfd,
9964 elf32_arm_plt_entry_long[0]
9965 | ((got_displacement & 0xf0000000) >> 28),
9966 ptr + 0);
9967 put_arm_insn (htab, output_bfd,
9968 elf32_arm_plt_entry_long[1]
9969 | ((got_displacement & 0x0ff00000) >> 20),
9970 ptr + 4);
9971 put_arm_insn (htab, output_bfd,
9972 elf32_arm_plt_entry_long[2]
9973 | ((got_displacement & 0x000ff000) >> 12),
9974 ptr+ 8);
9975 put_arm_insn (htab, output_bfd,
9976 elf32_arm_plt_entry_long[3]
9977 | (got_displacement & 0x00000fff),
9978 ptr + 12);
9979 }
34e77a92
RS		 9980 }
9981
9982 /* Fill in the entry in the .rel(a).(i)plt section. */
9983 rel.r_offset = got_address;
9984 rel.r_addend = 0;
9985 if (dynindx == -1)
9986 {
9987 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9988 The dynamic linker or static executable then calls SYM_VALUE
9989 to determine the correct run-time value of the .igot.plt entry. */
9990 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9991 initial_got_entry = sym_value;
9992 }
9993 else
9994 {
7801f98f
CL		 9995 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9996 used by PLT entry. */
9997 if (htab->fdpic_p)
9998 {
9999 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
10000 initial_got_entry = 0;
10001 }
10002 else
10003 {
10004 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
10005 initial_got_entry = (splt->output_section->vma
10006 + splt->output_offset);
10007 }
34e77a92
RS		 10008 }
10009
10010 /* Fill in the entry in the global offset table. */
10011 bfd_put_32 (output_bfd, initial_got_entry,
10012 sgot->contents + got_offset);
7801f98f
CL		 10013
10014 if (htab->fdpic_p && !(info->flags & DF_BIND_NOW))
10015 {
10016 /* Setup initial funcdesc value. */
10017 /* FIXME: we don't support lazy binding because there is a
10018 race condition between both words getting written and
10019 some other thread attempting to read them. The ARM
10020 architecture does not have an atomic 64 bit load/store
10021 instruction that could be used to prevent it; it is
10022 recommended that threaded FDPIC applications run with the
10023 LD_BIND_NOW environment variable set. */
10024 bfd_put_32(output_bfd, plt_address + 0x18,
10025 sgot->contents + got_offset);
10026 bfd_put_32(output_bfd, -1 /*TODO*/,
10027 sgot->contents + got_offset + 4);
10028 }
34e77a92
RS		 10029 }
10030
aba8c3de
WN		 10031 if (dynindx == -1)
10032 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
10033 else
10034 {
7801f98f
CL		 10035 if (htab->fdpic_p)
10036 {
10037 /* For FDPIC we put PLT relocationss into .rel.got when not
10038 lazy binding otherwise we put them in .rel.plt. For now,
10039 we don't support lazy binding so put it in .rel.got. */
10040 if (info->flags & DF_BIND_NOW)
10041 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelgot, &rel);
10042 else
10043 elf32_arm_add_dynreloc(output_bfd, info, htab->root.srelplt, &rel);
10044 }
10045 else
10046 {
10047 loc = srel->contents + plt_index * RELOC_SIZE (htab);
10048 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
10049 }
aba8c3de 10050 }
57460bcf
NC		 10051
10052 return TRUE;
34e77a92
RS		 10053}
10054
eb043451
PB		 10055/* Some relocations map to different relocations depending on the
10056 target. Return the real relocation. */
8029a119 10057
eb043451
PB		 10058static int
10059arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
10060 int r_type)
10061{
10062 switch (r_type)
10063 {
10064 case R_ARM_TARGET1:
10065 if (globals->target1_is_rel)
10066 return R_ARM_REL32;
10067 else
10068 return R_ARM_ABS32;
10069
10070 case R_ARM_TARGET2:
10071 return globals->target2_reloc;
10072
10073 default:
10074 return r_type;
10075 }
10076}
eb043451 10077
ba93b8ac
DJ		 10078/* Return the base VMA address which should be subtracted from real addresses
10079 when resolving @dtpoff relocation.
10080 This is PT_TLS segment p_vaddr. */
10081
10082static bfd_vma
10083dtpoff_base (struct bfd_link_info *info)
10084{
10085 /* If tls_sec is NULL, we should have signalled an error already. */
10086 if (elf_hash_table (info)->tls_sec == NULL)
10087 return 0;
10088 return elf_hash_table (info)->tls_sec->vma;
10089}
10090
10091/* Return the relocation value for @tpoff relocation
10092 if STT_TLS virtual address is ADDRESS. */
10093
10094static bfd_vma
10095tpoff (struct bfd_link_info *info, bfd_vma address)
10096{
10097 struct elf_link_hash_table *htab = elf_hash_table (info);
10098 bfd_vma base;
10099
10100 /* If tls_sec is NULL, we should have signalled an error already. */
10101 if (htab->tls_sec == NULL)
10102 return 0;
10103 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
10104 return address - htab->tls_sec->vma + base;
10105}
10106
00a97672
RS		 10107/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10108 VALUE is the relocation value. */
10109
10110static bfd_reloc_status_type
10111elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
10112{
10113 if (value > 0xfff)
10114 return bfd_reloc_overflow;
10115
10116 value |= bfd_get_32 (abfd, data) & 0xfffff000;
10117 bfd_put_32 (abfd, value, data);
10118 return bfd_reloc_ok;
10119}
10120
0855e32b
NS		 10121/* Handle TLS relaxations. Relaxing is possible for symbols that use
10122 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10123 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10124
10125 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10126 is to then call final_link_relocate. Return other values in the
62672b10
NS		 10127 case of error.
10128
10129 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10130 the pre-relaxed code. It would be nice if the relocs were updated
10131 to match the optimization. */
0855e32b 10132
b38cadfb 10133static bfd_reloc_status_type
0855e32b 10134elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 10135 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 10136 Elf_Internal_Rela *rel, unsigned long is_local)
10137{
10138 unsigned long insn;
b38cadfb 10139
0855e32b
NS		 10140 switch (ELF32_R_TYPE (rel->r_info))
10141 {
10142 default:
10143 return bfd_reloc_notsupported;
b38cadfb 10144
0855e32b
NS		 10145 case R_ARM_TLS_GOTDESC:
10146 if (is_local)
10147 insn = 0;
10148 else
10149 {
10150 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10151 if (insn & 1)
10152 insn -= 5; /* THUMB */
10153 else
10154 insn -= 8; /* ARM */
10155 }
10156 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10157 return bfd_reloc_continue;
10158
10159 case R_ARM_THM_TLS_DESCSEQ:
10160 /* Thumb insn. */
10161 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
10162 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
10163 {
10164 if (is_local)
10165 /* nop */
10166 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10167 }
10168 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
10169 {
10170 if (is_local)
10171 /* nop */
10172 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10173 else
10174 /* ldr rx,[ry] */
10175 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
10176 }
10177 else if ((insn & 0xff87) == 0x4780) /* blx rx */
10178 {
10179 if (is_local)
10180 /* nop */
10181 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10182 else
10183 /* mov r0, rx */
10184 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
10185 contents + rel->r_offset);
10186 }
10187 else
10188 {
10189 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10190 /* It's a 32 bit instruction, fetch the rest of it for
10191 error generation. */
10192 insn = (insn << 16)
10193 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 10194 _bfd_error_handler
695344c0 10195 /* xgettext:c-format */
2dcf00ce 10196 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10197 "unexpected %s instruction '%#lx' in TLS trampoline"),
10198 input_bfd, input_sec, (uint64_t) rel->r_offset,
10199 "Thumb", insn);
0855e32b
NS		 10200 return bfd_reloc_notsupported;
10201 }
10202 break;
b38cadfb 10203
0855e32b
NS		 10204 case R_ARM_TLS_DESCSEQ:
10205 /* arm insn. */
10206 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10207 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
10208 {
10209 if (is_local)
10210 /* mov rx, ry */
10211 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
10212 contents + rel->r_offset);
10213 }
10214 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
10215 {
10216 if (is_local)
10217 /* nop */
10218 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10219 else
10220 /* ldr rx,[ry] */
10221 bfd_put_32 (input_bfd, insn & 0xfffff000,
10222 contents + rel->r_offset);
10223 }
10224 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
10225 {
10226 if (is_local)
10227 /* nop */
10228 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10229 else
10230 /* mov r0, rx */
10231 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
10232 contents + rel->r_offset);
10233 }
10234 else
10235 {
4eca0228 10236 _bfd_error_handler
695344c0 10237 /* xgettext:c-format */
2dcf00ce 10238 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 10239 "unexpected %s instruction '%#lx' in TLS trampoline"),
10240 input_bfd, input_sec, (uint64_t) rel->r_offset,
10241 "ARM", insn);
0855e32b
NS		 10242 return bfd_reloc_notsupported;
10243 }
10244 break;
10245
10246 case R_ARM_TLS_CALL:
10247 /* GD->IE relaxation, turn the instruction into 'nop' or
10248 'ldr r0, [pc,r0]' */
10249 insn = is_local ? 0xe1a00000 : 0xe79f0000;
10250 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10251 break;
b38cadfb 10252
0855e32b 10253 case R_ARM_THM_TLS_CALL:
6a631e86 10254 /* GD->IE relaxation. */
0855e32b
NS		 10255 if (!is_local)
10256 /* add r0,pc; ldr r0, [r0] */
10257 insn = 0x44786800;
60a019a0 10258 else if (using_thumb2 (globals))
0855e32b
NS		 10259 /* nop.w */
10260 insn = 0xf3af8000;
10261 else
10262 /* nop; nop */
10263 insn = 0xbf00bf00;
b38cadfb 10264
0855e32b
NS		 10265 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
10266 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
10267 break;
10268 }
10269 return bfd_reloc_ok;
10270}
10271
4962c51a
MS		 10272/* For a given value of n, calculate the value of G_n as required to
10273 deal with group relocations. We return it in the form of an
10274 encoded constant-and-rotation, together with the final residual. If n is
10275 specified as less than zero, then final_residual is filled with the
10276 input value and no further action is performed. */
10277
10278static bfd_vma
10279calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
10280{
10281 int current_n;
10282 bfd_vma g_n;
10283 bfd_vma encoded_g_n = 0;
10284 bfd_vma residual = value; /* Also known as Y_n. */
10285
10286 for (current_n = 0; current_n <= n; current_n++)
10287 {
10288 int shift;
10289
10290 /* Calculate which part of the value to mask. */
10291 if (residual == 0)
99059e56 10292 shift = 0;
4962c51a 10293 else
99059e56
RM		 10294 {
10295 int msb;
10296
10297 /* Determine the most significant bit in the residual and
10298 align the resulting value to a 2-bit boundary. */
10299 for (msb = 30; msb >= 0; msb -= 2)
10300 if (residual & (3 << msb))
10301 break;
10302
10303 /* The desired shift is now (msb - 6), or zero, whichever
10304 is the greater. */
10305 shift = msb - 6;
10306 if (shift < 0)
10307 shift = 0;
10308 }
4962c51a
MS		 10309
10310 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10311 g_n = residual & (0xff << shift);
10312 encoded_g_n = (g_n >> shift)
99059e56 10313 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 10314
10315 /* Calculate the residual for the next time around. */
10316 residual &= ~g_n;
10317 }
10318
10319 *final_residual = residual;
10320
10321 return encoded_g_n;
10322}
10323
10324/* Given an ARM instruction, determine whether it is an ADD or a SUB.
10325 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 10326
4962c51a 10327static int
906e58ca 10328identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 10329{
10330 int opcode = insn & 0x1e00000;
10331
10332 if (opcode == 1 << 23) /* ADD */
10333 return 1;
10334
10335 if (opcode == 1 << 22) /* SUB */
10336 return -1;
10337
10338 return 0;
10339}
10340
252b5132 10341/* Perform a relocation as part of a final link. */
9b485d32 10342
252b5132 10343static bfd_reloc_status_type
07d6d2b8
AM		 10344elf32_arm_final_link_relocate (reloc_howto_type * howto,
10345 bfd * input_bfd,
10346 bfd * output_bfd,
10347 asection * input_section,
10348 bfd_byte * contents,
10349 Elf_Internal_Rela * rel,
10350 bfd_vma value,
10351 struct bfd_link_info * info,
10352 asection * sym_sec,
10353 const char * sym_name,
10354 unsigned char st_type,
10355 enum arm_st_branch_type branch_type,
0945cdfd 10356 struct elf_link_hash_entry * h,
07d6d2b8
AM		 10357 bfd_boolean * unresolved_reloc_p,
10358 char ** error_message)
10359{
10360 unsigned long r_type = howto->type;
10361 unsigned long r_symndx;
10362 bfd_byte * hit_data = contents + rel->r_offset;
10363 bfd_vma * local_got_offsets;
10364 bfd_vma * local_tlsdesc_gotents;
10365 asection * sgot;
10366 asection * splt;
10367 asection * sreloc = NULL;
10368 asection * srelgot;
10369 bfd_vma addend;
10370 bfd_signed_vma signed_addend;
10371 unsigned char dynreloc_st_type;
10372 bfd_vma dynreloc_value;
ba96a88f 10373 struct elf32_arm_link_hash_table * globals;
34e77a92 10374 struct elf32_arm_link_hash_entry *eh;
07d6d2b8
AM		 10375 union gotplt_union *root_plt;
10376 struct arm_plt_info *arm_plt;
10377 bfd_vma plt_offset;
10378 bfd_vma gotplt_offset;
10379 bfd_boolean has_iplt_entry;
10380 bfd_boolean resolved_to_zero;
f21f3fe0 10381
9c504268 10382 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 10383 if (globals == NULL)
10384 return bfd_reloc_notsupported;
9c504268 10385
0ffa91dd 10386 BFD_ASSERT (is_arm_elf (input_bfd));
47aeb64c 10387 BFD_ASSERT (howto != NULL);
0ffa91dd
NC		 10388
10389 /* Some relocation types map to different relocations depending on the
9c504268 10390 target. We pick the right one here. */
eb043451 10391 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 10392
10393 /* It is possible to have linker relaxations on some TLS access
10394 models. Update our information here. */
10395 r_type = elf32_arm_tls_transition (info, r_type, h);
10396
eb043451
PB		 10397 if (r_type != howto->type)
10398 howto = elf32_arm_howto_from_type (r_type);
9c504268 10399
34e77a92 10400 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 10401 sgot = globals->root.sgot;
252b5132 10402 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 10403 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
10404
34e77a92
RS		 10405 if (globals->root.dynamic_sections_created)
10406 srelgot = globals->root.srelgot;
10407 else
10408 srelgot = NULL;
10409
252b5132
RH		 10410 r_symndx = ELF32_R_SYM (rel->r_info);
10411
4e7fd91e 10412 if (globals->use_rel)
ba96a88f 10413 {
4e7fd91e
PB		 10414 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
10415
10416 if (addend & ((howto->src_mask + 1) >> 1))
10417 {
10418 signed_addend = -1;
10419 signed_addend &= ~ howto->src_mask;
10420 signed_addend |= addend;
10421 }
10422 else
10423 signed_addend = addend;
ba96a88f
NC		 10424 }
10425 else
4e7fd91e 10426 addend = signed_addend = rel->r_addend;
f21f3fe0 10427
39f21624
NC		 10428 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10429 are resolving a function call relocation. */
10430 if (using_thumb_only (globals)
10431 && (r_type == R_ARM_THM_CALL
10432 || r_type == R_ARM_THM_JUMP24)
10433 && branch_type == ST_BRANCH_TO_ARM)
10434 branch_type = ST_BRANCH_TO_THUMB;
10435
34e77a92
RS		 10436 /* Record the symbol information that should be used in dynamic
10437 relocations. */
10438 dynreloc_st_type = st_type;
10439 dynreloc_value = value;
10440 if (branch_type == ST_BRANCH_TO_THUMB)
10441 dynreloc_value |= 1;
10442
10443 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10444 VALUE appropriately for relocations that we resolve at link time. */
10445 has_iplt_entry = FALSE;
4ba2ef8f
TP		 10446 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
10447 &arm_plt)
34e77a92
RS		 10448 && root_plt->offset != (bfd_vma) -1)
10449 {
10450 plt_offset = root_plt->offset;
10451 gotplt_offset = arm_plt->got_offset;
10452
10453 if (h == NULL || eh->is_iplt)
10454 {
10455 has_iplt_entry = TRUE;
10456 splt = globals->root.iplt;
10457
10458 /* Populate .iplt entries here, because not all of them will
10459 be seen by finish_dynamic_symbol. The lower bit is set if
10460 we have already populated the entry. */
10461 if (plt_offset & 1)
10462 plt_offset--;
10463 else
10464 {
57460bcf
NC		 10465 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
10466 -1, dynreloc_value))
10467 root_plt->offset |= 1;
10468 else
10469 return bfd_reloc_notsupported;
34e77a92
RS		 10470 }
10471
10472 /* Static relocations always resolve to the .iplt entry. */
10473 st_type = STT_FUNC;
10474 value = (splt->output_section->vma
10475 + splt->output_offset
10476 + plt_offset);
10477 branch_type = ST_BRANCH_TO_ARM;
10478
10479 /* If there are non-call relocations that resolve to the .iplt
10480 entry, then all dynamic ones must too. */
10481 if (arm_plt->noncall_refcount != 0)
10482 {
10483 dynreloc_st_type = st_type;
10484 dynreloc_value = value;
10485 }
10486 }
10487 else
10488 /* We populate the .plt entry in finish_dynamic_symbol. */
10489 splt = globals->root.splt;
10490 }
10491 else
10492 {
10493 splt = NULL;
10494 plt_offset = (bfd_vma) -1;
10495 gotplt_offset = (bfd_vma) -1;
10496 }
10497
95b03e4a
L		 10498 resolved_to_zero = (h != NULL
10499 && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
10500
252b5132
RH		 10501 switch (r_type)
10502 {
10503 case R_ARM_NONE:
28a094c2
DJ		 10504 /* We don't need to find a value for this symbol. It's just a
10505 marker. */
10506 *unresolved_reloc_p = FALSE;
252b5132
RH		 10507 return bfd_reloc_ok;
10508
00a97672
RS		 10509 case R_ARM_ABS12:
10510 if (!globals->vxworks_p)
10511 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10512 /* Fall through. */
00a97672 10513
252b5132
RH		 10514 case R_ARM_PC24:
10515 case R_ARM_ABS32:
bb224fc3 10516 case R_ARM_ABS32_NOI:
252b5132 10517 case R_ARM_REL32:
bb224fc3 10518 case R_ARM_REL32_NOI:
5b5bb741
PB		 10519 case R_ARM_CALL:
10520 case R_ARM_JUMP24:
dfc5f959 10521 case R_ARM_XPC25:
eb043451 10522 case R_ARM_PREL31:
7359ea65 10523 case R_ARM_PLT32:
7359ea65
DJ		 10524 /* Handle relocations which should use the PLT entry. ABS32/REL32
10525 will use the symbol's value, which may point to a PLT entry, but we
10526 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10527 branches in this object should go to it, except if the PLT is too
10528 far away, in which case a long branch stub should be inserted. */
bb224fc3 10529 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10530 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10531 && r_type != R_ARM_CALL
10532 && r_type != R_ARM_JUMP24
10533 && r_type != R_ARM_PLT32)
34e77a92 10534 && plt_offset != (bfd_vma) -1)
7359ea65 10535 {
34e77a92
RS		 10536 /* If we've created a .plt section, and assigned a PLT entry
10537 to this function, it must either be a STT_GNU_IFUNC reference
10538 or not be known to bind locally. In other cases, we should
10539 have cleared the PLT entry by now. */
10540 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10541
10542 value = (splt->output_section->vma
10543 + splt->output_offset
34e77a92 10544 + plt_offset);
0945cdfd 10545 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10546 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10547 contents, rel->r_offset, value,
00a97672 10548 rel->r_addend);
7359ea65
DJ		 10549 }
10550
67687978
PB		 10551 /* When generating a shared object or relocatable executable, these
10552 relocations are copied into the output file to be resolved at
10553 run time. */
0e1862bb 10554 if ((bfd_link_pic (info)
e8b09b87
CL		 10555 || globals->root.is_relocatable_executable
10556 || globals->fdpic_p)
7359ea65 10557 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10558 && !(globals->vxworks_p
3348747a
NS		 10559 && strcmp (input_section->output_section->name,
10560 ".tls_vars") == 0)
bb224fc3 10561 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10562 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10563 && !(input_bfd == globals->stub_bfd
10564 && strstr (input_section->name, STUB_SUFFIX))
7359ea65 10565 && (h == NULL
95b03e4a
L		 10566 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10567 && !resolved_to_zero)
7359ea65
DJ		 10568 || h->root.type != bfd_link_hash_undefweak)
10569 && r_type != R_ARM_PC24
5b5bb741
PB		 10570 && r_type != R_ARM_CALL
10571 && r_type != R_ARM_JUMP24
ee06dc07 10572 && r_type != R_ARM_PREL31
7359ea65 10573 && r_type != R_ARM_PLT32)
252b5132 10574 {
947216bf 10575 Elf_Internal_Rela outrel;
b34976b6 10576 bfd_boolean skip, relocate;
e8b09b87 10577 int isrofixup = 0;
f21f3fe0 10578
52db4ec2
JW		 10579 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10580 && !h->def_regular)
10581 {
10582 char *v = _("shared object");
10583
0e1862bb 10584 if (bfd_link_executable (info))
52db4ec2
JW		 10585 v = _("PIE executable");
10586
4eca0228 10587 _bfd_error_handler
871b3ab2 10588 (_("%pB: relocation %s against external or undefined symbol `%s'"
52db4ec2
JW		 10589 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10590 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10591 return bfd_reloc_notsupported;
10592 }
10593
0945cdfd
DJ		 10594 *unresolved_reloc_p = FALSE;
10595
34e77a92 10596 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10597 {
83bac4b0
NC		 10598 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10599 ! globals->use_rel);
f21f3fe0 10600
83bac4b0 10601 if (sreloc == NULL)
252b5132 10602 return bfd_reloc_notsupported;
252b5132 10603 }
f21f3fe0 10604
b34976b6
AM		 10605 skip = FALSE;
10606 relocate = FALSE;
f21f3fe0 10607
00a97672 10608 outrel.r_addend = addend;
c629eae0
JJ		 10609 outrel.r_offset =
10610 _bfd_elf_section_offset (output_bfd, info, input_section,
10611 rel->r_offset);
10612 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10613 skip = TRUE;
0bb2d96a 10614 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10615 skip = TRUE, relocate = TRUE;
252b5132
RH		 10616 outrel.r_offset += (input_section->output_section->vma
10617 + input_section->output_offset);
f21f3fe0 10618
252b5132 10619 if (skip)
0bb2d96a 10620 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10621 else if (h != NULL
10622 && h->dynindx != -1
0e1862bb 10623 && (!bfd_link_pic (info)
1dcb9720
JW		 10624 || !(bfd_link_pie (info)
10625 || SYMBOLIC_BIND (info, h))
f5385ebf 10626 || !h->def_regular))
5e681ec4 10627 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10628 else
10629 {
a16385dc
MM		 10630 int symbol;
10631
5e681ec4 10632 /* This symbol is local, or marked to become local. */
e8b09b87
CL		 10633 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI
10634 || (globals->fdpic_p && !bfd_link_pic(info)));
a16385dc 10635 if (globals->symbian_p)
6366ff1e 10636 {
74541ad4
AM		 10637 asection *osec;
10638
6366ff1e
MM		 10639 /* On Symbian OS, the data segment and text segement
10640 can be relocated independently. Therefore, we
10641 must indicate the segment to which this
10642 relocation is relative. The BPABI allows us to
10643 use any symbol in the right segment; we just use
10644 the section symbol as it is convenient. (We
10645 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10646 will not appear in the dynamic symbol table.)
10647
10648 Note that the dynamic linker ignores the section
10649 symbol value, so we don't subtract osec->vma
10650 from the emitted reloc addend. */
10dbd1f3 10651 if (sym_sec)
74541ad4 10652 osec = sym_sec->output_section;
10dbd1f3 10653 else
74541ad4
AM		 10654 osec = input_section->output_section;
10655 symbol = elf_section_data (osec)->dynindx;
10656 if (symbol == 0)
10657 {
10658 struct elf_link_hash_table *htab = elf_hash_table (info);
10659
10660 if ((osec->flags & SEC_READONLY) == 0
10661 && htab->data_index_section != NULL)
10662 osec = htab->data_index_section;
10663 else
10664 osec = htab->text_index_section;
10665 symbol = elf_section_data (osec)->dynindx;
10666 }
6366ff1e
MM		 10667 BFD_ASSERT (symbol != 0);
10668 }
a16385dc
MM		 10669 else
10670 /* On SVR4-ish systems, the dynamic loader cannot
10671 relocate the text and data segments independently,
10672 so the symbol does not matter. */
10673 symbol = 0;
34e77a92
RS		 10674 if (dynreloc_st_type == STT_GNU_IFUNC)
10675 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10676 to the .iplt entry. Instead, every non-call reference
10677 must use an R_ARM_IRELATIVE relocation to obtain the
10678 correct run-time address. */
10679 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
e8b09b87
CL		 10680 else if (globals->fdpic_p && !bfd_link_pic(info))
10681 isrofixup = 1;
34e77a92
RS		 10682 else
10683 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10684 if (globals->use_rel)
10685 relocate = TRUE;
10686 else
34e77a92 10687 outrel.r_addend += dynreloc_value;
252b5132 10688 }
f21f3fe0 10689
e8b09b87
CL		 10690 if (isrofixup)
10691 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
10692 else
10693 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10694
f21f3fe0 10695 /* If this reloc is against an external symbol, we do not want to
252b5132 10696 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10697 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10698 if (! relocate)
10699 return bfd_reloc_ok;
9a5aca8c 10700
f21f3fe0 10701 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10702 contents, rel->r_offset,
10703 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10704 }
10705 else switch (r_type)
10706 {
00a97672
RS		 10707 case R_ARM_ABS12:
10708 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10709
dfc5f959 10710 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10711 case R_ARM_CALL:
10712 case R_ARM_JUMP24:
8029a119 10713 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10714 case R_ARM_PLT32:
906e58ca 10715 {
906e58ca
NC		 10716 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10717
dfc5f959 10718 if (r_type == R_ARM_XPC25)
252b5132 10719 {
dfc5f959
NC		 10720 /* Check for Arm calling Arm function. */
10721 /* FIXME: Should we translate the instruction into a BL
10722 instruction instead ? */
35fc36a8 10723 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10724 _bfd_error_handler
90b6238f
AM		 10725 (_("\%pB: warning: %s BLX instruction targets"
10726 " %s function '%s'"),
10727 input_bfd, "ARM",
10728 "ARM", h ? h->root.root.string : "(local)");
dfc5f959 10729 }
155d87d7 10730 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10731 {
10732 /* Check for Arm calling Thumb function. */
35fc36a8 10733 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10734 {
f2a9dd69
DJ		 10735 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10736 output_bfd, input_section,
10737 hit_data, sym_sec, rel->r_offset,
10738 signed_addend, value,
10739 error_message))
10740 return bfd_reloc_ok;
10741 else
10742 return bfd_reloc_dangerous;
dfc5f959 10743 }
252b5132 10744 }
ba96a88f 10745
906e58ca 10746 /* Check if a stub has to be inserted because the
8029a119 10747 destination is too far or we are changing mode. */
155d87d7
CL		 10748 if ( r_type == R_ARM_CALL
10749 || r_type == R_ARM_JUMP24
10750 || r_type == R_ARM_PLT32)
906e58ca 10751 {
fe33d2fa
CL		 10752 enum elf32_arm_stub_type stub_type = arm_stub_none;
10753 struct elf32_arm_link_hash_entry *hash;
10754
10755 hash = (struct elf32_arm_link_hash_entry *) h;
10756 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10757 st_type, &branch_type,
10758 hash, value, sym_sec,
fe33d2fa 10759 input_bfd, sym_name);
5fa9e92f 10760
fe33d2fa 10761 if (stub_type != arm_stub_none)
906e58ca
NC		 10762 {
10763 /* The target is out of reach, so redirect the
10764 branch to the local stub for this function. */
906e58ca
NC		 10765 stub_entry = elf32_arm_get_stub_entry (input_section,
10766 sym_sec, h,
fe33d2fa
CL		 10767 rel, globals,
10768 stub_type);
9cd3e4e5
NC		 10769 {
10770 if (stub_entry != NULL)
10771 value = (stub_entry->stub_offset
10772 + stub_entry->stub_sec->output_offset
10773 + stub_entry->stub_sec->output_section->vma);
10774
10775 if (plt_offset != (bfd_vma) -1)
10776 *unresolved_reloc_p = FALSE;
10777 }
906e58ca 10778 }
fe33d2fa
CL		 10779 else
10780 {
10781 /* If the call goes through a PLT entry, make sure to
10782 check distance to the right destination address. */
34e77a92 10783 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10784 {
10785 value = (splt->output_section->vma
10786 + splt->output_offset
34e77a92 10787 + plt_offset);
fe33d2fa
CL		 10788 *unresolved_reloc_p = FALSE;
10789 /* The PLT entry is in ARM mode, regardless of the
10790 target function. */
35fc36a8 10791 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10792 }
10793 }
906e58ca
NC		 10794 }
10795
dea514f5
PB		 10796 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10797 where:
10798 S is the address of the symbol in the relocation.
10799 P is address of the instruction being relocated.
10800 A is the addend (extracted from the instruction) in bytes.
10801
10802 S is held in 'value'.
10803 P is the base address of the section containing the
10804 instruction plus the offset of the reloc into that
10805 section, ie:
10806 (input_section->output_section->vma +
10807 input_section->output_offset +
10808 rel->r_offset).
10809 A is the addend, converted into bytes, ie:
10810 (signed_addend * 4)
10811
10812 Note: None of these operations have knowledge of the pipeline
10813 size of the processor, thus it is up to the assembler to
10814 encode this information into the addend. */
10815 value -= (input_section->output_section->vma
10816 + input_section->output_offset);
10817 value -= rel->r_offset;
4e7fd91e
PB		 10818 if (globals->use_rel)
10819 value += (signed_addend << howto->size);
10820 else
10821 /* RELA addends do not have to be adjusted by howto->size. */
10822 value += signed_addend;
23080146 10823
dcb5e6e6
NC		 10824 signed_addend = value;
10825 signed_addend >>= howto->rightshift;
9a5aca8c 10826
5ab79981 10827 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10828 the next instruction unless a PLT entry will be created.
77b4f08f 10829 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10830 The jump to the next instruction is optimized as a NOP depending
10831 on the architecture. */
ffcb4889 10832 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10833 && plt_offset == (bfd_vma) -1)
77b4f08f 10834 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10835 {
cd1dac3d
DG		 10836 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10837
10838 if (arch_has_arm_nop (globals))
10839 value |= 0x0320f000;
10840 else
10841 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10842 }
10843 else
59f2c4e7 10844 {
9b485d32 10845 /* Perform a signed range check. */
dcb5e6e6 10846 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10847 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10848 return bfd_reloc_overflow;
9a5aca8c 10849
5ab79981 10850 addend = (value & 2);
39b41c9c 10851
5ab79981
PB		 10852 value = (signed_addend & howto->dst_mask)
10853 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10854
5ab79981
PB		 10855 if (r_type == R_ARM_CALL)
10856 {
155d87d7 10857 /* Set the H bit in the BLX instruction. */
35fc36a8 10858 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10859 {
10860 if (addend)
10861 value |= (1 << 24);
10862 else
10863 value &= ~(bfd_vma)(1 << 24);
10864 }
10865
5ab79981 10866 /* Select the correct instruction (BL or BLX). */
906e58ca 10867 /* Only if we are not handling a BL to a stub. In this
8029a119 10868 case, mode switching is performed by the stub. */
35fc36a8 10869 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10870 value |= (1 << 28);
63e1a0fc 10871 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10872 {
10873 value &= ~(bfd_vma)(1 << 28);
10874 value |= (1 << 24);
10875 }
39b41c9c
PB		 10876 }
10877 }
906e58ca 10878 }
252b5132 10879 break;
f21f3fe0 10880
252b5132
RH		 10881 case R_ARM_ABS32:
10882 value += addend;
35fc36a8 10883 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10884 value |= 1;
10885 break;
f21f3fe0 10886
bb224fc3
MS		 10887 case R_ARM_ABS32_NOI:
10888 value += addend;
10889 break;
10890
252b5132 10891 case R_ARM_REL32:
a8bc6c78 10892 value += addend;
35fc36a8 10893 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10894 value |= 1;
252b5132 10895 value -= (input_section->output_section->vma
62efb346 10896 + input_section->output_offset + rel->r_offset);
252b5132 10897 break;
eb043451 10898
bb224fc3
MS		 10899 case R_ARM_REL32_NOI:
10900 value += addend;
10901 value -= (input_section->output_section->vma
10902 + input_section->output_offset + rel->r_offset);
10903 break;
10904
eb043451
PB		 10905 case R_ARM_PREL31:
10906 value -= (input_section->output_section->vma
10907 + input_section->output_offset + rel->r_offset);
10908 value += signed_addend;
10909 if (! h || h->root.type != bfd_link_hash_undefweak)
10910 {
8029a119 10911 /* Check for overflow. */
eb043451
PB		 10912 if ((value ^ (value >> 1)) & (1 << 30))
10913 return bfd_reloc_overflow;
10914 }
10915 value &= 0x7fffffff;
10916 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10917 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10918 value |= 1;
10919 break;
252b5132 10920 }
f21f3fe0 10921
252b5132
RH		 10922 bfd_put_32 (input_bfd, value, hit_data);
10923 return bfd_reloc_ok;
10924
10925 case R_ARM_ABS8:
fd0fd00c
MJ		 10926 /* PR 16202: Refectch the addend using the correct size. */
10927 if (globals->use_rel)
10928 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10929 value += addend;
4e67d4ca
DG		 10930
10931 /* There is no way to tell whether the user intended to use a signed or
10932 unsigned addend. When checking for overflow we accept either,
10933 as specified by the AAELF. */
10934 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10935 return bfd_reloc_overflow;
10936
10937 bfd_put_8 (input_bfd, value, hit_data);
10938 return bfd_reloc_ok;
10939
10940 case R_ARM_ABS16:
fd0fd00c
MJ		 10941 /* PR 16202: Refectch the addend using the correct size. */
10942 if (globals->use_rel)
10943 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10944 value += addend;
10945
4e67d4ca
DG		 10946 /* See comment for R_ARM_ABS8. */
10947 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10948 return bfd_reloc_overflow;
10949
10950 bfd_put_16 (input_bfd, value, hit_data);
10951 return bfd_reloc_ok;
10952
252b5132 10953 case R_ARM_THM_ABS5:
9b485d32 10954 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10955 if (globals->use_rel)
10956 {
10957 /* Need to refetch addend. */
10958 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10959 /* ??? Need to determine shift amount from operand size. */
10960 addend >>= howto->rightshift;
10961 }
252b5132
RH		 10962 value += addend;
10963
10964 /* ??? Isn't value unsigned? */
10965 if ((long) value > 0x1f || (long) value < -0x10)
10966 return bfd_reloc_overflow;
10967
10968 /* ??? Value needs to be properly shifted into place first. */
10969 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10970 bfd_put_16 (input_bfd, value, hit_data);
10971 return bfd_reloc_ok;
10972
2cab6cc3
MS		 10973 case R_ARM_THM_ALU_PREL_11_0:
10974 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10975 {
10976 bfd_vma insn;
10977 bfd_signed_vma relocation;
10978
10979 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10980 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10981
99059e56
RM		 10982 if (globals->use_rel)
10983 {
10984 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10985 | ((insn & (1 << 26)) >> 15);
10986 if (insn & 0xf00000)
10987 signed_addend = -signed_addend;
10988 }
2cab6cc3
MS		 10989
10990 relocation = value + signed_addend;
79f08007 10991 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10992 + input_section->output_offset
10993 + rel->r_offset);
2cab6cc3 10994
8c65b54f
CS		 10995 /* PR 21523: Use an absolute value. The user of this reloc will
10996 have already selected an ADD or SUB insn appropriately. */
453f8e1e 10997 value = llabs (relocation);
2cab6cc3 10998
99059e56
RM		 10999 if (value >= 0x1000)
11000 return bfd_reloc_overflow;
2cab6cc3 11001
e645cf40
AG		 11002 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
11003 if (branch_type == ST_BRANCH_TO_THUMB)
11004 value |= 1;
11005
2cab6cc3 11006 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 11007 | ((value & 0x700) << 4)
11008 | ((value & 0x800) << 15);
11009 if (relocation < 0)
11010 insn |= 0xa00000;
2cab6cc3
MS		 11011
11012 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11013 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11014
99059e56 11015 return bfd_reloc_ok;
2cab6cc3
MS		 11016 }
11017
e1ec24c6
NC		 11018 case R_ARM_THM_PC8:
11019 /* PR 10073: This reloc is not generated by the GNU toolchain,
11020 but it is supported for compatibility with third party libraries
11021 generated by other compilers, specifically the ARM/IAR. */
11022 {
11023 bfd_vma insn;
11024 bfd_signed_vma relocation;
11025
11026 insn = bfd_get_16 (input_bfd, hit_data);
11027
99059e56 11028 if (globals->use_rel)
79f08007 11029 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 11030
11031 relocation = value + addend;
79f08007 11032 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11033 + input_section->output_offset
11034 + rel->r_offset);
e1ec24c6 11035
b6518b38 11036 value = relocation;
e1ec24c6
NC		 11037
11038 /* We do not check for overflow of this reloc. Although strictly
11039 speaking this is incorrect, it appears to be necessary in order
11040 to work with IAR generated relocs. Since GCC and GAS do not
11041 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
11042 a problem for them. */
11043 value &= 0x3fc;
11044
11045 insn = (insn & 0xff00) | (value >> 2);
11046
11047 bfd_put_16 (input_bfd, insn, hit_data);
11048
99059e56 11049 return bfd_reloc_ok;
e1ec24c6
NC		 11050 }
11051
2cab6cc3
MS		 11052 case R_ARM_THM_PC12:
11053 /* Corresponds to: ldr.w reg, [pc, #offset]. */
11054 {
11055 bfd_vma insn;
11056 bfd_signed_vma relocation;
11057
11058 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 11059 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 11060
99059e56
RM		 11061 if (globals->use_rel)
11062 {
11063 signed_addend = insn & 0xfff;
11064 if (!(insn & (1 << 23)))
11065 signed_addend = -signed_addend;
11066 }
2cab6cc3
MS		 11067
11068 relocation = value + signed_addend;
79f08007 11069 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 11070 + input_section->output_offset
11071 + rel->r_offset);
2cab6cc3 11072
b6518b38 11073 value = relocation;
2cab6cc3 11074
99059e56
RM		 11075 if (value >= 0x1000)
11076 return bfd_reloc_overflow;
2cab6cc3
MS		 11077
11078 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 11079 if (relocation >= 0)
11080 insn |= (1 << 23);
2cab6cc3
MS		 11081
11082 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11083 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11084
99059e56 11085 return bfd_reloc_ok;
2cab6cc3
MS		 11086 }
11087
dfc5f959 11088 case R_ARM_THM_XPC22:
c19d1205 11089 case R_ARM_THM_CALL:
bd97cb95 11090 case R_ARM_THM_JUMP24:
dfc5f959 11091 /* Thumb BL (branch long instruction). */
252b5132 11092 {
b34976b6 11093 bfd_vma relocation;
99059e56 11094 bfd_vma reloc_sign;
b34976b6
AM		 11095 bfd_boolean overflow = FALSE;
11096 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11097 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 11098 bfd_signed_vma reloc_signed_max;
11099 bfd_signed_vma reloc_signed_min;
b34976b6 11100 bfd_vma check;
252b5132 11101 bfd_signed_vma signed_check;
e95de063 11102 int bitsize;
cd1dac3d 11103 const int thumb2 = using_thumb2 (globals);
5e866f5a 11104 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 11105
5ab79981 11106 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 11107 the next instruction unless a PLT entry will be created.
11108 The jump to the next instruction is optimized as a NOP.W for
11109 Thumb-2 enabled architectures. */
19540007 11110 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 11111 && plt_offset == (bfd_vma) -1)
5ab79981 11112 {
60a019a0 11113 if (thumb2)
cd1dac3d
DG		 11114 {
11115 bfd_put_16 (input_bfd, 0xf3af, hit_data);
11116 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
11117 }
11118 else
11119 {
11120 bfd_put_16 (input_bfd, 0xe000, hit_data);
11121 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
11122 }
5ab79981
PB		 11123 return bfd_reloc_ok;
11124 }
11125
e95de063 11126 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 11127 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 11128 if (globals->use_rel)
11129 {
99059e56
RM		 11130 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
11131 bfd_vma upper = upper_insn & 0x3ff;
11132 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 11133 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
11134 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 11135 bfd_vma i1 = j1 ^ s ? 0 : 1;
11136 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 11137
99059e56
RM		 11138 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
11139 /* Sign extend. */
11140 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 11141
4e7fd91e
PB		 11142 signed_addend = addend;
11143 }
cb1afa5c 11144
dfc5f959
NC		 11145 if (r_type == R_ARM_THM_XPC22)
11146 {
11147 /* Check for Thumb to Thumb call. */
11148 /* FIXME: Should we translate the instruction into a BL
11149 instruction instead ? */
35fc36a8 11150 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 11151 _bfd_error_handler
90b6238f
AM		 11152 (_("%pB: warning: %s BLX instruction targets"
11153 " %s function '%s'"),
11154 input_bfd, "Thumb",
11155 "Thumb", h ? h->root.root.string : "(local)");
dfc5f959
NC		 11156 }
11157 else
252b5132 11158 {
dfc5f959
NC		 11159 /* If it is not a call to Thumb, assume call to Arm.
11160 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 11161 function call at all, but rather a long jump. Calls through
11162 the PLT do not require stubs. */
34e77a92 11163 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 11164 {
bd97cb95 11165 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11166 {
11167 /* Convert BL to BLX. */
11168 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11169 }
155d87d7
CL		 11170 else if (( r_type != R_ARM_THM_CALL)
11171 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 11172 {
11173 if (elf32_thumb_to_arm_stub
11174 (info, sym_name, input_bfd, output_bfd, input_section,
11175 hit_data, sym_sec, rel->r_offset, signed_addend, value,
11176 error_message))
11177 return bfd_reloc_ok;
11178 else
11179 return bfd_reloc_dangerous;
11180 }
da5938a2 11181 }
35fc36a8
RS		 11182 else if (branch_type == ST_BRANCH_TO_THUMB
11183 && globals->use_blx
bd97cb95 11184 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 11185 {
11186 /* Make sure this is a BL. */
11187 lower_insn |= 0x1800;
11188 }
252b5132 11189 }
f21f3fe0 11190
fe33d2fa 11191 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 11192 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 11193 {
11194 /* Check if a stub has to be inserted because the destination
8029a119 11195 is too far. */
fe33d2fa
CL		 11196 struct elf32_arm_stub_hash_entry *stub_entry;
11197 struct elf32_arm_link_hash_entry *hash;
11198
11199 hash = (struct elf32_arm_link_hash_entry *) h;
11200
11201 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 11202 st_type, &branch_type,
11203 hash, value, sym_sec,
fe33d2fa
CL		 11204 input_bfd, sym_name);
11205
11206 if (stub_type != arm_stub_none)
906e58ca
NC		 11207 {
11208 /* The target is out of reach or we are changing modes, so
11209 redirect the branch to the local stub for this
11210 function. */
11211 stub_entry = elf32_arm_get_stub_entry (input_section,
11212 sym_sec, h,
fe33d2fa
CL		 11213 rel, globals,
11214 stub_type);
906e58ca 11215 if (stub_entry != NULL)
9cd3e4e5
NC		 11216 {
11217 value = (stub_entry->stub_offset
11218 + stub_entry->stub_sec->output_offset
11219 + stub_entry->stub_sec->output_section->vma);
11220
11221 if (plt_offset != (bfd_vma) -1)
11222 *unresolved_reloc_p = FALSE;
11223 }
906e58ca 11224
f4ac8484 11225 /* If this call becomes a call to Arm, force BLX. */
155d87d7 11226 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 11227 {
11228 if ((stub_entry
11229 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 11230 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 11231 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11232 }
906e58ca
NC		 11233 }
11234 }
11235
fe33d2fa 11236 /* Handle calls via the PLT. */
34e77a92 11237 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 11238 {
11239 value = (splt->output_section->vma
11240 + splt->output_offset
34e77a92 11241 + plt_offset);
fe33d2fa 11242
eed94f8f
NC		 11243 if (globals->use_blx
11244 && r_type == R_ARM_THM_CALL
11245 && ! using_thumb_only (globals))
fe33d2fa
CL		 11246 {
11247 /* If the Thumb BLX instruction is available, convert
11248 the BL to a BLX instruction to call the ARM-mode
11249 PLT entry. */
11250 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 11251 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 11252 }
11253 else
11254 {
eed94f8f
NC		 11255 if (! using_thumb_only (globals))
11256 /* Target the Thumb stub before the ARM PLT entry. */
11257 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 11258 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 11259 }
11260 *unresolved_reloc_p = FALSE;
11261 }
11262
ba96a88f 11263 relocation = value + signed_addend;
f21f3fe0 11264
252b5132 11265 relocation -= (input_section->output_section->vma
ba96a88f
NC		 11266 + input_section->output_offset
11267 + rel->r_offset);
9a5aca8c 11268
252b5132
RH		 11269 check = relocation >> howto->rightshift;
11270
11271 /* If this is a signed value, the rightshift just dropped
11272 leading 1 bits (assuming twos complement). */
11273 if ((bfd_signed_vma) relocation >= 0)
11274 signed_check = check;
11275 else
11276 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
11277
e95de063
MS		 11278 /* Calculate the permissable maximum and minimum values for
11279 this relocation according to whether we're relocating for
11280 Thumb-2 or not. */
11281 bitsize = howto->bitsize;
5e866f5a 11282 if (!thumb2_bl)
e95de063 11283 bitsize -= 2;
f6ebfac0 11284 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 11285 reloc_signed_min = ~reloc_signed_max;
11286
252b5132 11287 /* Assumes two's complement. */
ba96a88f 11288 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 11289 overflow = TRUE;
252b5132 11290
bd97cb95 11291 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 11292 /* For a BLX instruction, make sure that the relocation is rounded up
11293 to a word boundary. This follows the semantics of the instruction
11294 which specifies that bit 1 of the target address will come from bit
11295 1 of the base address. */
11296 relocation = (relocation + 2) & ~ 3;
cb1afa5c 11297
e95de063
MS		 11298 /* Put RELOCATION back into the insn. Assumes two's complement.
11299 We use the Thumb-2 encoding, which is safe even if dealing with
11300 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 11301 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 11302 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 11303 | ((relocation >> 12) & 0x3ff)
11304 | (reloc_sign << 10);
906e58ca 11305 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 11306 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
11307 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
11308 | ((relocation >> 1) & 0x7ff);
c62e1cc3 11309
252b5132
RH		 11310 /* Put the relocated value back in the object file: */
11311 bfd_put_16 (input_bfd, upper_insn, hit_data);
11312 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11313
11314 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11315 }
11316 break;
11317
c19d1205
ZW		 11318 case R_ARM_THM_JUMP19:
11319 /* Thumb32 conditional branch instruction. */
11320 {
11321 bfd_vma relocation;
11322 bfd_boolean overflow = FALSE;
11323 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11324 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 11325 bfd_signed_vma reloc_signed_max = 0xffffe;
11326 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 11327 bfd_signed_vma signed_check;
07d6d2b8 11328 enum elf32_arm_stub_type stub_type = arm_stub_none;
c5423981
TG		 11329 struct elf32_arm_stub_hash_entry *stub_entry;
11330 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 11331
11332 /* Need to refetch the addend, reconstruct the top three bits,
11333 and squish the two 11 bit pieces together. */
11334 if (globals->use_rel)
11335 {
11336 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 11337 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 11338 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
11339 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
11340 bfd_vma lower = (lower_insn & 0x07ff);
11341
a00a1f35
MS		 11342 upper |= J1 << 6;
11343 upper |= J2 << 7;
11344 upper |= (!S) << 8;
c19d1205
ZW		 11345 upper -= 0x0100; /* Sign extend. */
11346
11347 addend = (upper << 12) | (lower << 1);
11348 signed_addend = addend;
11349 }
11350
bd97cb95 11351 /* Handle calls via the PLT. */
34e77a92 11352 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 11353 {
11354 value = (splt->output_section->vma
11355 + splt->output_offset
34e77a92 11356 + plt_offset);
bd97cb95
DJ		 11357 /* Target the Thumb stub before the ARM PLT entry. */
11358 value -= PLT_THUMB_STUB_SIZE;
11359 *unresolved_reloc_p = FALSE;
11360 }
11361
c5423981
TG		 11362 hash = (struct elf32_arm_link_hash_entry *)h;
11363
11364 stub_type = arm_type_of_stub (info, input_section, rel,
07d6d2b8
AM		 11365 st_type, &branch_type,
11366 hash, value, sym_sec,
11367 input_bfd, sym_name);
c5423981
TG		 11368 if (stub_type != arm_stub_none)
11369 {
11370 stub_entry = elf32_arm_get_stub_entry (input_section,
07d6d2b8
AM		 11371 sym_sec, h,
11372 rel, globals,
11373 stub_type);
c5423981
TG		 11374 if (stub_entry != NULL)
11375 {
07d6d2b8
AM		 11376 value = (stub_entry->stub_offset
11377 + stub_entry->stub_sec->output_offset
11378 + stub_entry->stub_sec->output_section->vma);
c5423981
TG		 11379 }
11380 }
c19d1205 11381
99059e56 11382 relocation = value + signed_addend;
c19d1205
ZW		 11383 relocation -= (input_section->output_section->vma
11384 + input_section->output_offset
11385 + rel->r_offset);
a00a1f35 11386 signed_check = (bfd_signed_vma) relocation;
c19d1205 11387
c19d1205
ZW		 11388 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11389 overflow = TRUE;
11390
11391 /* Put RELOCATION back into the insn. */
11392 {
11393 bfd_vma S = (relocation & 0x00100000) >> 20;
11394 bfd_vma J2 = (relocation & 0x00080000) >> 19;
11395 bfd_vma J1 = (relocation & 0x00040000) >> 18;
11396 bfd_vma hi = (relocation & 0x0003f000) >> 12;
11397 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
11398
a00a1f35 11399 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 11400 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
11401 }
11402
11403 /* Put the relocated value back in the object file: */
11404 bfd_put_16 (input_bfd, upper_insn, hit_data);
11405 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11406
11407 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11408 }
11409
11410 case R_ARM_THM_JUMP11:
11411 case R_ARM_THM_JUMP8:
11412 case R_ARM_THM_JUMP6:
51c5503b
NC		 11413 /* Thumb B (branch) instruction). */
11414 {
6cf9e9fe 11415 bfd_signed_vma relocation;
51c5503b
NC		 11416 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
11417 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 11418 bfd_signed_vma signed_check;
11419
c19d1205
ZW		 11420 /* CZB cannot jump backward. */
11421 if (r_type == R_ARM_THM_JUMP6)
11422 reloc_signed_min = 0;
11423
4e7fd91e 11424 if (globals->use_rel)
6cf9e9fe 11425 {
4e7fd91e
PB		 11426 /* Need to refetch addend. */
11427 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
11428 if (addend & ((howto->src_mask + 1) >> 1))
11429 {
11430 signed_addend = -1;
11431 signed_addend &= ~ howto->src_mask;
11432 signed_addend |= addend;
11433 }
11434 else
11435 signed_addend = addend;
11436 /* The value in the insn has been right shifted. We need to
11437 undo this, so that we can perform the address calculation
11438 in terms of bytes. */
11439 signed_addend <<= howto->rightshift;
6cf9e9fe 11440 }
6cf9e9fe 11441 relocation = value + signed_addend;
51c5503b
NC		 11442
11443 relocation -= (input_section->output_section->vma
11444 + input_section->output_offset
11445 + rel->r_offset);
11446
6cf9e9fe
NC		 11447 relocation >>= howto->rightshift;
11448 signed_check = relocation;
c19d1205
ZW		 11449
11450 if (r_type == R_ARM_THM_JUMP6)
11451 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
11452 else
11453 relocation &= howto->dst_mask;
51c5503b 11454 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 11455
51c5503b
NC		 11456 bfd_put_16 (input_bfd, relocation, hit_data);
11457
11458 /* Assumes two's complement. */
11459 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11460 return bfd_reloc_overflow;
11461
11462 return bfd_reloc_ok;
11463 }
cedb70c5 11464
8375c36b
PB		 11465 case R_ARM_ALU_PCREL7_0:
11466 case R_ARM_ALU_PCREL15_8:
11467 case R_ARM_ALU_PCREL23_15:
11468 {
11469 bfd_vma insn;
11470 bfd_vma relocation;
11471
11472 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 11473 if (globals->use_rel)
11474 {
11475 /* Extract the addend. */
11476 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
11477 signed_addend = addend;
11478 }
8375c36b
PB		 11479 relocation = value + signed_addend;
11480
11481 relocation -= (input_section->output_section->vma
11482 + input_section->output_offset
11483 + rel->r_offset);
11484 insn = (insn & ~0xfff)
11485 | ((howto->bitpos << 7) & 0xf00)
11486 | ((relocation >> howto->bitpos) & 0xff);
11487 bfd_put_32 (input_bfd, value, hit_data);
11488 }
11489 return bfd_reloc_ok;
11490
252b5132
RH		 11491 case R_ARM_GNU_VTINHERIT:
11492 case R_ARM_GNU_VTENTRY:
11493 return bfd_reloc_ok;
11494
c19d1205 11495 case R_ARM_GOTOFF32:
252b5132 11496 /* Relocation is relative to the start of the
99059e56 11497 global offset table. */
252b5132
RH		 11498
11499 BFD_ASSERT (sgot != NULL);
11500 if (sgot == NULL)
99059e56 11501 return bfd_reloc_notsupported;
9a5aca8c 11502
cedb70c5 11503 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11504 address by one, so that attempts to call the function pointer will
11505 correctly interpret it as Thumb code. */
35fc36a8 11506 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11507 value += 1;
11508
252b5132 11509 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11510 calculation. We always want the start of .got. If we
11511 define _GLOBAL_OFFSET_TABLE in a different way, as is
11512 permitted by the ABI, we might have to change this
11513 calculation. */
252b5132 11514 value -= sgot->output_section->vma;
f21f3fe0 11515 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11516 contents, rel->r_offset, value,
00a97672 11517 rel->r_addend);
252b5132
RH		 11518
11519 case R_ARM_GOTPC:
a7c10850 11520 /* Use global offset table as symbol value. */
252b5132 11521 BFD_ASSERT (sgot != NULL);
f21f3fe0 11522
252b5132 11523 if (sgot == NULL)
99059e56 11524 return bfd_reloc_notsupported;
252b5132 11525
0945cdfd 11526 *unresolved_reloc_p = FALSE;
252b5132 11527 value = sgot->output_section->vma;
f21f3fe0 11528 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11529 contents, rel->r_offset, value,
00a97672 11530 rel->r_addend);
f21f3fe0 11531
252b5132 11532 case R_ARM_GOT32:
eb043451 11533 case R_ARM_GOT_PREL:
252b5132 11534 /* Relocation is to the entry for this symbol in the
99059e56 11535 global offset table. */
252b5132
RH		 11536 if (sgot == NULL)
11537 return bfd_reloc_notsupported;
f21f3fe0 11538
34e77a92
RS		 11539 if (dynreloc_st_type == STT_GNU_IFUNC
11540 && plt_offset != (bfd_vma) -1
11541 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11542 {
11543 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11544 symbol, and the relocation resolves directly to the runtime
11545 target rather than to the .iplt entry. This means that any
11546 .got entry would be the same value as the .igot.plt entry,
11547 so there's no point creating both. */
11548 sgot = globals->root.igotplt;
11549 value = sgot->output_offset + gotplt_offset;
11550 }
11551 else if (h != NULL)
252b5132
RH		 11552 {
11553 bfd_vma off;
f21f3fe0 11554
252b5132
RH		 11555 off = h->got.offset;
11556 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11557 if ((off & 1) != 0)
252b5132 11558 {
b436d854
RS		 11559 /* We have already processsed one GOT relocation against
11560 this symbol. */
11561 off &= ~1;
11562 if (globals->root.dynamic_sections_created
11563 && !SYMBOL_REFERENCES_LOCAL (info, h))
11564 *unresolved_reloc_p = FALSE;
11565 }
11566 else
11567 {
11568 Elf_Internal_Rela outrel;
e8b09b87 11569 int isrofixup = 0;
b436d854 11570
e8b09b87
CL		 11571 if (((h->dynindx != -1) || globals->fdpic_p)
11572 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11573 {
11574 /* If the symbol doesn't resolve locally in a static
11575 object, we have an undefined reference. If the
11576 symbol doesn't resolve locally in a dynamic object,
11577 it should be resolved by the dynamic linker. */
11578 if (globals->root.dynamic_sections_created)
11579 {
11580 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11581 *unresolved_reloc_p = FALSE;
11582 }
11583 else
11584 outrel.r_info = 0;
11585 outrel.r_addend = 0;
11586 }
252b5132
RH		 11587 else
11588 {
34e77a92 11589 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11590 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c 11591 else if (bfd_link_pic (info)
7f026732 11592 && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
99059e56
RM		 11593 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11594 else
2376f038
EB		 11595 {
11596 outrel.r_info = 0;
11597 if (globals->fdpic_p)
11598 isrofixup = 1;
11599 }
34e77a92 11600 outrel.r_addend = dynreloc_value;
b436d854 11601 }
ee29b9fb 11602
b436d854
RS		 11603 /* The GOT entry is initialized to zero by default.
11604 See if we should install a different value. */
11605 if (outrel.r_addend != 0
2376f038 11606 && (globals->use_rel || outrel.r_info == 0))
b436d854
RS		 11607 {
11608 bfd_put_32 (output_bfd, outrel.r_addend,
11609 sgot->contents + off);
11610 outrel.r_addend = 0;
252b5132 11611 }
f21f3fe0 11612
2376f038
EB		 11613 if (isrofixup)
11614 arm_elf_add_rofixup (output_bfd,
11615 elf32_arm_hash_table(info)->srofixup,
11616 sgot->output_section->vma
11617 + sgot->output_offset + off);
11618
11619 else if (outrel.r_info != 0)
b436d854
RS		 11620 {
11621 outrel.r_offset = (sgot->output_section->vma
11622 + sgot->output_offset
11623 + off);
11624 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11625 }
2376f038 11626
b436d854
RS		 11627 h->got.offset |= 1;
11628 }
252b5132
RH		 11629 value = sgot->output_offset + off;
11630 }
11631 else
11632 {
11633 bfd_vma off;
f21f3fe0 11634
5025eb7c
AO		 11635 BFD_ASSERT (local_got_offsets != NULL
11636 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11637
252b5132 11638 off = local_got_offsets[r_symndx];
f21f3fe0 11639
252b5132
RH		 11640 /* The offset must always be a multiple of 4. We use the
11641 least significant bit to record whether we have already
9b485d32 11642 generated the necessary reloc. */
252b5132
RH		 11643 if ((off & 1) != 0)
11644 off &= ~1;
11645 else
11646 {
2376f038
EB		 11647 Elf_Internal_Rela outrel;
11648 int isrofixup = 0;
f21f3fe0 11649
2376f038
EB		 11650 if (dynreloc_st_type == STT_GNU_IFUNC)
11651 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
11652 else if (bfd_link_pic (info))
11653 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11654 else
252b5132 11655 {
2376f038
EB		 11656 outrel.r_info = 0;
11657 if (globals->fdpic_p)
11658 isrofixup = 1;
11659 }
11660
11661 /* The GOT entry is initialized to zero by default.
11662 See if we should install a different value. */
11663 if (globals->use_rel || outrel.r_info == 0)
11664 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
11665
11666 if (isrofixup)
11667 arm_elf_add_rofixup (output_bfd,
11668 globals->srofixup,
11669 sgot->output_section->vma
11670 + sgot->output_offset + off);
f21f3fe0 11671
2376f038
EB		 11672 else if (outrel.r_info != 0)
11673 {
34e77a92 11674 outrel.r_addend = addend + dynreloc_value;
252b5132 11675 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11676 + sgot->output_offset
252b5132 11677 + off);
47beaa6a 11678 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11679 }
f21f3fe0 11680
252b5132
RH		 11681 local_got_offsets[r_symndx] |= 1;
11682 }
f21f3fe0 11683
252b5132
RH		 11684 value = sgot->output_offset + off;
11685 }
eb043451
PB		 11686 if (r_type != R_ARM_GOT32)
11687 value += sgot->output_section->vma;
9a5aca8c 11688
f21f3fe0 11689 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11690 contents, rel->r_offset, value,
00a97672 11691 rel->r_addend);
f21f3fe0 11692
ba93b8ac
DJ		 11693 case R_ARM_TLS_LDO32:
11694 value = value - dtpoff_base (info);
11695
11696 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11697 contents, rel->r_offset, value,
11698 rel->r_addend);
ba93b8ac
DJ		 11699
11700 case R_ARM_TLS_LDM32:
5c5a4843 11701 case R_ARM_TLS_LDM32_FDPIC:
ba93b8ac
DJ		 11702 {
11703 bfd_vma off;
11704
362d30a1 11705 if (sgot == NULL)
ba93b8ac
DJ		 11706 abort ();
11707
11708 off = globals->tls_ldm_got.offset;
11709
11710 if ((off & 1) != 0)
11711 off &= ~1;
11712 else
11713 {
11714 /* If we don't know the module number, create a relocation
11715 for it. */
9cb09e33 11716 if (bfd_link_dll (info))
ba93b8ac
DJ		 11717 {
11718 Elf_Internal_Rela outrel;
ba93b8ac 11719
362d30a1 11720 if (srelgot == NULL)
ba93b8ac
DJ		 11721 abort ();
11722
00a97672 11723 outrel.r_addend = 0;
362d30a1
RS		 11724 outrel.r_offset = (sgot->output_section->vma
11725 + sgot->output_offset + off);
ba93b8ac
DJ		 11726 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11727
00a97672
RS		 11728 if (globals->use_rel)
11729 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11730 sgot->contents + off);
ba93b8ac 11731
47beaa6a 11732 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11733 }
11734 else
362d30a1 11735 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11736
11737 globals->tls_ldm_got.offset |= 1;
11738 }
11739
5c5a4843 11740 if (r_type == R_ARM_TLS_LDM32_FDPIC)
e8b09b87
CL		 11741 {
11742 bfd_put_32(output_bfd,
11743 globals->root.sgot->output_offset + off,
11744 contents + rel->r_offset);
11745
11746 return bfd_reloc_ok;
11747 }
11748 else
11749 {
11750 value = sgot->output_section->vma + sgot->output_offset + off
11751 - (input_section->output_section->vma
11752 + input_section->output_offset + rel->r_offset);
ba93b8ac 11753
e8b09b87
CL		 11754 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11755 contents, rel->r_offset, value,
11756 rel->r_addend);
11757 }
ba93b8ac
DJ		 11758 }
11759
0855e32b
NS		 11760 case R_ARM_TLS_CALL:
11761 case R_ARM_THM_TLS_CALL:
ba93b8ac 11762 case R_ARM_TLS_GD32:
5c5a4843 11763 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 11764 case R_ARM_TLS_IE32:
5c5a4843 11765 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 11766 case R_ARM_TLS_GOTDESC:
11767 case R_ARM_TLS_DESCSEQ:
11768 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11769 {
0855e32b
NS		 11770 bfd_vma off, offplt;
11771 int indx = 0;
ba93b8ac
DJ		 11772 char tls_type;
11773
0855e32b 11774 BFD_ASSERT (sgot != NULL);
ba93b8ac 11775
ba93b8ac
DJ		 11776 if (h != NULL)
11777 {
11778 bfd_boolean dyn;
11779 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11780 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11781 bfd_link_pic (info),
11782 h)
11783 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11784 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11785 {
11786 *unresolved_reloc_p = FALSE;
11787 indx = h->dynindx;
11788 }
11789 off = h->got.offset;
0855e32b 11790 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11791 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11792 }
11793 else
11794 {
0855e32b 11795 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11796 off = local_got_offsets[r_symndx];
0855e32b 11797 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11798 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11799 }
11800
0855e32b 11801 /* Linker relaxations happens from one of the
b38cadfb 11802 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11803 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11804 tls_type = GOT_TLS_IE;
0855e32b
NS		 11805
11806 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11807
11808 if ((off & 1) != 0)
11809 off &= ~1;
11810 else
11811 {
11812 bfd_boolean need_relocs = FALSE;
11813 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11814 int cur_off = off;
11815
11816 /* The GOT entries have not been initialized yet. Do it
11817 now, and emit any relocations. If both an IE GOT and a
11818 GD GOT are necessary, we emit the GD first. */
11819
9cb09e33 11820 if ((bfd_link_dll (info) || indx != 0)
ba93b8ac 11821 && (h == NULL
95b03e4a
L		 11822 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11823 && !resolved_to_zero)
ba93b8ac
DJ		 11824 || h->root.type != bfd_link_hash_undefweak))
11825 {
11826 need_relocs = TRUE;
0855e32b 11827 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11828 }
11829
0855e32b
NS		 11830 if (tls_type & GOT_TLS_GDESC)
11831 {
47beaa6a
RS		 11832 bfd_byte *loc;
11833
0855e32b
NS		 11834 /* We should have relaxed, unless this is an undefined
11835 weak symbol. */
11836 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
9cb09e33 11837 || bfd_link_dll (info));
0855e32b 11838 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11839 <= globals->root.sgotplt->size);
0855e32b
NS		 11840
11841 outrel.r_addend = 0;
11842 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11843 + globals->root.sgotplt->output_offset
11844 + offplt
11845 + globals->sgotplt_jump_table_size);
b38cadfb 11846
0855e32b
NS		 11847 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11848 sreloc = globals->root.srelplt;
11849 loc = sreloc->contents;
11850 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11851 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11852 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11853
11854 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11855
11856 /* For globals, the first word in the relocation gets
11857 the relocation index and the top bit set, or zero,
11858 if we're binding now. For locals, it gets the
11859 symbol's offset in the tls section. */
99059e56 11860 bfd_put_32 (output_bfd,
0855e32b
NS		 11861 !h ? value - elf_hash_table (info)->tls_sec->vma
11862 : info->flags & DF_BIND_NOW ? 0
11863 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11864 globals->root.sgotplt->contents + offplt
11865 + globals->sgotplt_jump_table_size);
11866
0855e32b 11867 /* Second word in the relocation is always zero. */
99059e56 11868 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11869 globals->root.sgotplt->contents + offplt
11870 + globals->sgotplt_jump_table_size + 4);
0855e32b 11871 }
ba93b8ac
DJ		 11872 if (tls_type & GOT_TLS_GD)
11873 {
11874 if (need_relocs)
11875 {
00a97672 11876 outrel.r_addend = 0;
362d30a1
RS		 11877 outrel.r_offset = (sgot->output_section->vma
11878 + sgot->output_offset
00a97672 11879 + cur_off);
ba93b8ac 11880 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11881
00a97672
RS		 11882 if (globals->use_rel)
11883 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11884 sgot->contents + cur_off);
00a97672 11885
47beaa6a 11886 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11887
11888 if (indx == 0)
11889 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11890 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11891 else
11892 {
00a97672 11893 outrel.r_addend = 0;
ba93b8ac
DJ		 11894 outrel.r_info = ELF32_R_INFO (indx,
11895 R_ARM_TLS_DTPOFF32);
11896 outrel.r_offset += 4;
00a97672
RS		 11897
11898 if (globals->use_rel)
11899 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11900 sgot->contents + cur_off + 4);
00a97672 11901
47beaa6a
RS		 11902 elf32_arm_add_dynreloc (output_bfd, info,
11903 srelgot, &outrel);
ba93b8ac
DJ		 11904 }
11905 }
11906 else
11907 {
11908 /* If we are not emitting relocations for a
11909 general dynamic reference, then we must be in a
11910 static link or an executable link with the
11911 symbol binding locally. Mark it as belonging
11912 to module 1, the executable. */
11913 bfd_put_32 (output_bfd, 1,
362d30a1 11914 sgot->contents + cur_off);
ba93b8ac 11915 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11916 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11917 }
11918
11919 cur_off += 8;
11920 }
11921
11922 if (tls_type & GOT_TLS_IE)
11923 {
11924 if (need_relocs)
11925 {
00a97672
RS		 11926 if (indx == 0)
11927 outrel.r_addend = value - dtpoff_base (info);
11928 else
11929 outrel.r_addend = 0;
362d30a1
RS		 11930 outrel.r_offset = (sgot->output_section->vma
11931 + sgot->output_offset
ba93b8ac
DJ		 11932 + cur_off);
11933 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11934
00a97672
RS		 11935 if (globals->use_rel)
11936 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11937 sgot->contents + cur_off);
ba93b8ac 11938
47beaa6a 11939 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11940 }
11941 else
11942 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11943 sgot->contents + cur_off);
ba93b8ac
DJ		 11944 cur_off += 4;
11945 }
11946
11947 if (h != NULL)
11948 h->got.offset |= 1;
11949 else
11950 local_got_offsets[r_symndx] |= 1;
11951 }
11952
5c5a4843 11953 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32 && r_type != R_ARM_TLS_GD32_FDPIC)
ba93b8ac 11954 off += 8;
0855e32b
NS		 11955 else if (tls_type & GOT_TLS_GDESC)
11956 off = offplt;
11957
11958 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11959 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11960 {
11961 bfd_signed_vma offset;
12352d3f
PB		 11962 /* TLS stubs are arm mode. The original symbol is a
11963 data object, so branch_type is bogus. */
11964 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11965 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11966 = arm_type_of_stub (info, input_section, rel,
11967 st_type, &branch_type,
0855e32b
NS		 11968 (struct elf32_arm_link_hash_entry *)h,
11969 globals->tls_trampoline, globals->root.splt,
11970 input_bfd, sym_name);
11971
11972 if (stub_type != arm_stub_none)
11973 {
11974 struct elf32_arm_stub_hash_entry *stub_entry
11975 = elf32_arm_get_stub_entry
11976 (input_section, globals->root.splt, 0, rel,
11977 globals, stub_type);
11978 offset = (stub_entry->stub_offset
11979 + stub_entry->stub_sec->output_offset
11980 + stub_entry->stub_sec->output_section->vma);
11981 }
11982 else
11983 offset = (globals->root.splt->output_section->vma
11984 + globals->root.splt->output_offset
11985 + globals->tls_trampoline);
11986
11987 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11988 {
11989 unsigned long inst;
b38cadfb
NC		 11990
11991 offset -= (input_section->output_section->vma
11992 + input_section->output_offset
11993 + rel->r_offset + 8);
0855e32b
NS		 11994
11995 inst = offset >> 2;
11996 inst &= 0x00ffffff;
11997 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11998 }
11999 else
12000 {
12001 /* Thumb blx encodes the offset in a complicated
12002 fashion. */
12003 unsigned upper_insn, lower_insn;
12004 unsigned neg;
12005
b38cadfb
NC		 12006 offset -= (input_section->output_section->vma
12007 + input_section->output_offset
0855e32b 12008 + rel->r_offset + 4);
b38cadfb 12009
12352d3f
PB		 12010 if (stub_type != arm_stub_none
12011 && arm_stub_is_thumb (stub_type))
12012 {
12013 lower_insn = 0xd000;
12014 }
12015 else
12016 {
12017 lower_insn = 0xc000;
6a631e86 12018 /* Round up the offset to a word boundary. */
12352d3f
PB		 12019 offset = (offset + 2) & ~2;
12020 }
12021
0855e32b
NS		 12022 neg = offset < 0;
12023 upper_insn = (0xf000
12024 | ((offset >> 12) & 0x3ff)
12025 | (neg << 10));
12352d3f 12026 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 12027 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 12028 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 12029 bfd_put_16 (input_bfd, upper_insn, hit_data);
12030 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12031 return bfd_reloc_ok;
12032 }
12033 }
12034 /* These relocations needs special care, as besides the fact
12035 they point somewhere in .gotplt, the addend must be
12036 adjusted accordingly depending on the type of instruction
6a631e86 12037 we refer to. */
0855e32b
NS		 12038 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
12039 {
12040 unsigned long data, insn;
12041 unsigned thumb;
b38cadfb 12042
b627f562 12043 data = bfd_get_signed_32 (input_bfd, hit_data);
0855e32b 12044 thumb = data & 1;
b627f562 12045 data &= ~1ul;
b38cadfb 12046
0855e32b
NS		 12047 if (thumb)
12048 {
12049 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
12050 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
12051 insn = (insn << 16)
12052 | bfd_get_16 (input_bfd,
12053 contents + rel->r_offset - data + 2);
12054 if ((insn & 0xf800c000) == 0xf000c000)
12055 /* bl/blx */
12056 value = -6;
12057 else if ((insn & 0xffffff00) == 0x4400)
12058 /* add */
12059 value = -5;
12060 else
12061 {
4eca0228 12062 _bfd_error_handler
695344c0 12063 /* xgettext:c-format */
2dcf00ce 12064 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12065 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12066 "referenced by TLS_GOTDESC"),
12067 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12068 "Thumb", insn);
0855e32b
NS		 12069 return bfd_reloc_notsupported;
12070 }
12071 }
12072 else
12073 {
12074 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
12075
12076 switch (insn >> 24)
12077 {
12078 case 0xeb: /* bl */
12079 case 0xfa: /* blx */
12080 value = -4;
12081 break;
12082
12083 case 0xe0: /* add */
12084 value = -8;
12085 break;
b38cadfb 12086
0855e32b 12087 default:
4eca0228 12088 _bfd_error_handler
695344c0 12089 /* xgettext:c-format */
2dcf00ce 12090 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 12091 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 12092 "referenced by TLS_GOTDESC"),
12093 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 12094 "ARM", insn);
0855e32b
NS		 12095 return bfd_reloc_notsupported;
12096 }
12097 }
b38cadfb 12098
0855e32b
NS		 12099 value += ((globals->root.sgotplt->output_section->vma
12100 + globals->root.sgotplt->output_offset + off)
12101 - (input_section->output_section->vma
12102 + input_section->output_offset
12103 + rel->r_offset)
12104 + globals->sgotplt_jump_table_size);
12105 }
12106 else
12107 value = ((globals->root.sgot->output_section->vma
12108 + globals->root.sgot->output_offset + off)
12109 - (input_section->output_section->vma
12110 + input_section->output_offset + rel->r_offset));
ba93b8ac 12111
5c5a4843
CL		 12112 if (globals->fdpic_p && (r_type == R_ARM_TLS_GD32_FDPIC ||
12113 r_type == R_ARM_TLS_IE32_FDPIC))
e8b09b87
CL		 12114 {
12115 /* For FDPIC relocations, resolve to the offset of the GOT
12116 entry from the start of GOT. */
12117 bfd_put_32(output_bfd,
12118 globals->root.sgot->output_offset + off,
12119 contents + rel->r_offset);
12120
12121 return bfd_reloc_ok;
12122 }
12123 else
12124 {
12125 return _bfd_final_link_relocate (howto, input_bfd, input_section,
12126 contents, rel->r_offset, value,
12127 rel->r_addend);
12128 }
ba93b8ac
DJ		 12129 }
12130
12131 case R_ARM_TLS_LE32:
3cbc1e5e 12132 if (bfd_link_dll (info))
ba93b8ac 12133 {
4eca0228 12134 _bfd_error_handler
695344c0 12135 /* xgettext:c-format */
2dcf00ce
AM		 12136 (_("%pB(%pA+%#" PRIx64 "): %s relocation not permitted "
12137 "in shared object"),
12138 input_bfd, input_section, (uint64_t) rel->r_offset, howto->name);
46691134 12139 return bfd_reloc_notsupported;
ba93b8ac
DJ		 12140 }
12141 else
12142 value = tpoff (info, value);
906e58ca 12143
ba93b8ac 12144 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 12145 contents, rel->r_offset, value,
12146 rel->r_addend);
ba93b8ac 12147
319850b4
JB		 12148 case R_ARM_V4BX:
12149 if (globals->fix_v4bx)
845b51d6
PB		 12150 {
12151 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 12152
845b51d6
PB		 12153 /* Ensure that we have a BX instruction. */
12154 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 12155
845b51d6
PB		 12156 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
12157 {
12158 /* Branch to veneer. */
12159 bfd_vma glue_addr;
12160 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
12161 glue_addr -= input_section->output_section->vma
12162 + input_section->output_offset
12163 + rel->r_offset + 8;
12164 insn = (insn & 0xf0000000) | 0x0a000000
12165 | ((glue_addr >> 2) & 0x00ffffff);
12166 }
12167 else
12168 {
12169 /* Preserve Rm (lowest four bits) and the condition code
12170 (highest four bits). Other bits encode MOV PC,Rm. */
12171 insn = (insn & 0xf000000f) | 0x01a0f000;
12172 }
319850b4 12173
845b51d6
PB		 12174 bfd_put_32 (input_bfd, insn, hit_data);
12175 }
319850b4
JB		 12176 return bfd_reloc_ok;
12177
b6895b4f
PB		 12178 case R_ARM_MOVW_ABS_NC:
12179 case R_ARM_MOVT_ABS:
12180 case R_ARM_MOVW_PREL_NC:
12181 case R_ARM_MOVT_PREL:
92f5d02b
MS		 12182 /* Until we properly support segment-base-relative addressing then
12183 we assume the segment base to be zero, as for the group relocations.
12184 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12185 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12186 case R_ARM_MOVW_BREL_NC:
12187 case R_ARM_MOVW_BREL:
12188 case R_ARM_MOVT_BREL:
b6895b4f
PB		 12189 {
12190 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
12191
12192 if (globals->use_rel)
12193 {
12194 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 12195 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12196 }
92f5d02b 12197
b6895b4f 12198 value += signed_addend;
b6895b4f
PB		 12199
12200 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
12201 value -= (input_section->output_section->vma
12202 + input_section->output_offset + rel->r_offset);
12203
92f5d02b 12204 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 12205 return bfd_reloc_overflow;
92f5d02b 12206
35fc36a8 12207 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12208 value |= 1;
12209
12210 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 12211 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 12212 value >>= 16;
12213
12214 insn &= 0xfff0f000;
12215 insn |= value & 0xfff;
12216 insn |= (value & 0xf000) << 4;
12217 bfd_put_32 (input_bfd, insn, hit_data);
12218 }
12219 return bfd_reloc_ok;
12220
12221 case R_ARM_THM_MOVW_ABS_NC:
12222 case R_ARM_THM_MOVT_ABS:
12223 case R_ARM_THM_MOVW_PREL_NC:
12224 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 12225 /* Until we properly support segment-base-relative addressing then
12226 we assume the segment base to be zero, as for the above relocations.
12227 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12228 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12229 as R_ARM_THM_MOVT_ABS. */
12230 case R_ARM_THM_MOVW_BREL_NC:
12231 case R_ARM_THM_MOVW_BREL:
12232 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 12233 {
12234 bfd_vma insn;
906e58ca 12235
b6895b4f
PB		 12236 insn = bfd_get_16 (input_bfd, hit_data) << 16;
12237 insn |= bfd_get_16 (input_bfd, hit_data + 2);
12238
12239 if (globals->use_rel)
12240 {
12241 addend = ((insn >> 4) & 0xf000)
12242 | ((insn >> 15) & 0x0800)
12243 | ((insn >> 4) & 0x0700)
07d6d2b8 12244 | (insn & 0x00ff);
39623e12 12245 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 12246 }
92f5d02b 12247
b6895b4f 12248 value += signed_addend;
b6895b4f
PB		 12249
12250 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
12251 value -= (input_section->output_section->vma
12252 + input_section->output_offset + rel->r_offset);
12253
92f5d02b 12254 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 12255 return bfd_reloc_overflow;
92f5d02b 12256
35fc36a8 12257 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 12258 value |= 1;
12259
12260 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 12261 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 12262 value >>= 16;
12263
12264 insn &= 0xfbf08f00;
12265 insn |= (value & 0xf000) << 4;
12266 insn |= (value & 0x0800) << 15;
12267 insn |= (value & 0x0700) << 4;
12268 insn |= (value & 0x00ff);
12269
12270 bfd_put_16 (input_bfd, insn >> 16, hit_data);
12271 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
12272 }
12273 return bfd_reloc_ok;
12274
4962c51a
MS		 12275 case R_ARM_ALU_PC_G0_NC:
12276 case R_ARM_ALU_PC_G1_NC:
12277 case R_ARM_ALU_PC_G0:
12278 case R_ARM_ALU_PC_G1:
12279 case R_ARM_ALU_PC_G2:
12280 case R_ARM_ALU_SB_G0_NC:
12281 case R_ARM_ALU_SB_G1_NC:
12282 case R_ARM_ALU_SB_G0:
12283 case R_ARM_ALU_SB_G1:
12284 case R_ARM_ALU_SB_G2:
12285 {
12286 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12287 bfd_vma pc = input_section->output_section->vma
4962c51a 12288 + input_section->output_offset + rel->r_offset;
31a91d61 12289 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12290 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 12291 bfd_vma residual;
12292 bfd_vma g_n;
4962c51a 12293 bfd_signed_vma signed_value;
99059e56
RM		 12294 int group = 0;
12295
12296 /* Determine which group of bits to select. */
12297 switch (r_type)
12298 {
12299 case R_ARM_ALU_PC_G0_NC:
12300 case R_ARM_ALU_PC_G0:
12301 case R_ARM_ALU_SB_G0_NC:
12302 case R_ARM_ALU_SB_G0:
12303 group = 0;
12304 break;
12305
12306 case R_ARM_ALU_PC_G1_NC:
12307 case R_ARM_ALU_PC_G1:
12308 case R_ARM_ALU_SB_G1_NC:
12309 case R_ARM_ALU_SB_G1:
12310 group = 1;
12311 break;
12312
12313 case R_ARM_ALU_PC_G2:
12314 case R_ARM_ALU_SB_G2:
12315 group = 2;
12316 break;
12317
12318 default:
12319 abort ();
12320 }
12321
12322 /* If REL, extract the addend from the insn. If RELA, it will
12323 have already been fetched for us. */
4962c51a 12324 if (globals->use_rel)
99059e56
RM		 12325 {
12326 int negative;
12327 bfd_vma constant = insn & 0xff;
12328 bfd_vma rotation = (insn & 0xf00) >> 8;
12329
12330 if (rotation == 0)
12331 signed_addend = constant;
12332 else
12333 {
12334 /* Compensate for the fact that in the instruction, the
12335 rotation is stored in multiples of 2 bits. */
12336 rotation *= 2;
12337
12338 /* Rotate "constant" right by "rotation" bits. */
12339 signed_addend = (constant >> rotation) |
12340 (constant << (8 * sizeof (bfd_vma) - rotation));
12341 }
12342
12343 /* Determine if the instruction is an ADD or a SUB.
12344 (For REL, this determines the sign of the addend.) */
12345 negative = identify_add_or_sub (insn);
12346 if (negative == 0)
12347 {
4eca0228 12348 _bfd_error_handler
695344c0 12349 /* xgettext:c-format */
90b6238f 12350 (_("%pB(%pA+%#" PRIx64 "): only ADD or SUB instructions "
2dcf00ce
AM		 12351 "are allowed for ALU group relocations"),
12352 input_bfd, input_section, (uint64_t) rel->r_offset);
99059e56
RM		 12353 return bfd_reloc_overflow;
12354 }
12355
12356 signed_addend *= negative;
12357 }
4962c51a
MS		 12358
12359 /* Compute the value (X) to go in the place. */
99059e56
RM		 12360 if (r_type == R_ARM_ALU_PC_G0_NC
12361 || r_type == R_ARM_ALU_PC_G1_NC
12362 || r_type == R_ARM_ALU_PC_G0
12363 || r_type == R_ARM_ALU_PC_G1
12364 || r_type == R_ARM_ALU_PC_G2)
12365 /* PC relative. */
12366 signed_value = value - pc + signed_addend;
12367 else
12368 /* Section base relative. */
12369 signed_value = value - sb + signed_addend;
12370
12371 /* If the target symbol is a Thumb function, then set the
12372 Thumb bit in the address. */
35fc36a8 12373 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 12374 signed_value |= 1;
12375
99059e56
RM		 12376 /* Calculate the value of the relevant G_n, in encoded
12377 constant-with-rotation format. */
b6518b38
NC		 12378 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12379 group, &residual);
99059e56
RM		 12380
12381 /* Check for overflow if required. */
12382 if ((r_type == R_ARM_ALU_PC_G0
12383 || r_type == R_ARM_ALU_PC_G1
12384 || r_type == R_ARM_ALU_PC_G2
12385 || r_type == R_ARM_ALU_SB_G0
12386 || r_type == R_ARM_ALU_SB_G1
12387 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
12388 {
4eca0228 12389 _bfd_error_handler
695344c0 12390 /* xgettext:c-format */
90b6238f 12391 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12392 "splitting %#" PRIx64 " for group relocation %s"),
12393 input_bfd, input_section, (uint64_t) rel->r_offset,
12394 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12395 howto->name);
99059e56
RM		 12396 return bfd_reloc_overflow;
12397 }
12398
12399 /* Mask out the value and the ADD/SUB part of the opcode; take care
12400 not to destroy the S bit. */
12401 insn &= 0xff1ff000;
12402
12403 /* Set the opcode according to whether the value to go in the
12404 place is negative. */
12405 if (signed_value < 0)
12406 insn |= 1 << 22;
12407 else
12408 insn |= 1 << 23;
12409
12410 /* Encode the offset. */
12411 insn |= g_n;
4962c51a
MS		 12412
12413 bfd_put_32 (input_bfd, insn, hit_data);
12414 }
12415 return bfd_reloc_ok;
12416
12417 case R_ARM_LDR_PC_G0:
12418 case R_ARM_LDR_PC_G1:
12419 case R_ARM_LDR_PC_G2:
12420 case R_ARM_LDR_SB_G0:
12421 case R_ARM_LDR_SB_G1:
12422 case R_ARM_LDR_SB_G2:
12423 {
12424 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12425 bfd_vma pc = input_section->output_section->vma
4962c51a 12426 + input_section->output_offset + rel->r_offset;
31a91d61 12427 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12428 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12429 bfd_vma residual;
4962c51a 12430 bfd_signed_vma signed_value;
99059e56
RM		 12431 int group = 0;
12432
12433 /* Determine which groups of bits to calculate. */
12434 switch (r_type)
12435 {
12436 case R_ARM_LDR_PC_G0:
12437 case R_ARM_LDR_SB_G0:
12438 group = 0;
12439 break;
12440
12441 case R_ARM_LDR_PC_G1:
12442 case R_ARM_LDR_SB_G1:
12443 group = 1;
12444 break;
12445
12446 case R_ARM_LDR_PC_G2:
12447 case R_ARM_LDR_SB_G2:
12448 group = 2;
12449 break;
12450
12451 default:
12452 abort ();
12453 }
12454
12455 /* If REL, extract the addend from the insn. If RELA, it will
12456 have already been fetched for us. */
4962c51a 12457 if (globals->use_rel)
99059e56
RM		 12458 {
12459 int negative = (insn & (1 << 23)) ? 1 : -1;
12460 signed_addend = negative * (insn & 0xfff);
12461 }
4962c51a
MS		 12462
12463 /* Compute the value (X) to go in the place. */
99059e56
RM		 12464 if (r_type == R_ARM_LDR_PC_G0
12465 || r_type == R_ARM_LDR_PC_G1
12466 || r_type == R_ARM_LDR_PC_G2)
12467 /* PC relative. */
12468 signed_value = value - pc + signed_addend;
12469 else
12470 /* Section base relative. */
12471 signed_value = value - sb + signed_addend;
12472
12473 /* Calculate the value of the relevant G_{n-1} to obtain
12474 the residual at that stage. */
b6518b38
NC		 12475 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12476 group - 1, &residual);
99059e56
RM		 12477
12478 /* Check for overflow. */
12479 if (residual >= 0x1000)
12480 {
4eca0228 12481 _bfd_error_handler
695344c0 12482 /* xgettext:c-format */
90b6238f 12483 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12484 "splitting %#" PRIx64 " for group relocation %s"),
12485 input_bfd, input_section, (uint64_t) rel->r_offset,
12486 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12487 howto->name);
99059e56
RM		 12488 return bfd_reloc_overflow;
12489 }
12490
12491 /* Mask out the value and U bit. */
12492 insn &= 0xff7ff000;
12493
12494 /* Set the U bit if the value to go in the place is non-negative. */
12495 if (signed_value >= 0)
12496 insn |= 1 << 23;
12497
12498 /* Encode the offset. */
12499 insn |= residual;
4962c51a
MS		 12500
12501 bfd_put_32 (input_bfd, insn, hit_data);
12502 }
12503 return bfd_reloc_ok;
12504
12505 case R_ARM_LDRS_PC_G0:
12506 case R_ARM_LDRS_PC_G1:
12507 case R_ARM_LDRS_PC_G2:
12508 case R_ARM_LDRS_SB_G0:
12509 case R_ARM_LDRS_SB_G1:
12510 case R_ARM_LDRS_SB_G2:
12511 {
12512 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12513 bfd_vma pc = input_section->output_section->vma
4962c51a 12514 + input_section->output_offset + rel->r_offset;
31a91d61 12515 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12516 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12517 bfd_vma residual;
4962c51a 12518 bfd_signed_vma signed_value;
99059e56
RM		 12519 int group = 0;
12520
12521 /* Determine which groups of bits to calculate. */
12522 switch (r_type)
12523 {
12524 case R_ARM_LDRS_PC_G0:
12525 case R_ARM_LDRS_SB_G0:
12526 group = 0;
12527 break;
12528
12529 case R_ARM_LDRS_PC_G1:
12530 case R_ARM_LDRS_SB_G1:
12531 group = 1;
12532 break;
12533
12534 case R_ARM_LDRS_PC_G2:
12535 case R_ARM_LDRS_SB_G2:
12536 group = 2;
12537 break;
12538
12539 default:
12540 abort ();
12541 }
12542
12543 /* If REL, extract the addend from the insn. If RELA, it will
12544 have already been fetched for us. */
4962c51a 12545 if (globals->use_rel)
99059e56
RM		 12546 {
12547 int negative = (insn & (1 << 23)) ? 1 : -1;
12548 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
12549 }
4962c51a
MS		 12550
12551 /* Compute the value (X) to go in the place. */
99059e56
RM		 12552 if (r_type == R_ARM_LDRS_PC_G0
12553 || r_type == R_ARM_LDRS_PC_G1
12554 || r_type == R_ARM_LDRS_PC_G2)
12555 /* PC relative. */
12556 signed_value = value - pc + signed_addend;
12557 else
12558 /* Section base relative. */
12559 signed_value = value - sb + signed_addend;
12560
12561 /* Calculate the value of the relevant G_{n-1} to obtain
12562 the residual at that stage. */
b6518b38
NC		 12563 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12564 group - 1, &residual);
99059e56
RM		 12565
12566 /* Check for overflow. */
12567 if (residual >= 0x100)
12568 {
4eca0228 12569 _bfd_error_handler
695344c0 12570 /* xgettext:c-format */
90b6238f 12571 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12572 "splitting %#" PRIx64 " for group relocation %s"),
12573 input_bfd, input_section, (uint64_t) rel->r_offset,
12574 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12575 howto->name);
99059e56
RM		 12576 return bfd_reloc_overflow;
12577 }
12578
12579 /* Mask out the value and U bit. */
12580 insn &= 0xff7ff0f0;
12581
12582 /* Set the U bit if the value to go in the place is non-negative. */
12583 if (signed_value >= 0)
12584 insn |= 1 << 23;
12585
12586 /* Encode the offset. */
12587 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12588
12589 bfd_put_32 (input_bfd, insn, hit_data);
12590 }
12591 return bfd_reloc_ok;
12592
12593 case R_ARM_LDC_PC_G0:
12594 case R_ARM_LDC_PC_G1:
12595 case R_ARM_LDC_PC_G2:
12596 case R_ARM_LDC_SB_G0:
12597 case R_ARM_LDC_SB_G1:
12598 case R_ARM_LDC_SB_G2:
12599 {
12600 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12601 bfd_vma pc = input_section->output_section->vma
4962c51a 12602 + input_section->output_offset + rel->r_offset;
31a91d61 12603 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12604 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12605 bfd_vma residual;
4962c51a 12606 bfd_signed_vma signed_value;
99059e56
RM		 12607 int group = 0;
12608
12609 /* Determine which groups of bits to calculate. */
12610 switch (r_type)
12611 {
12612 case R_ARM_LDC_PC_G0:
12613 case R_ARM_LDC_SB_G0:
12614 group = 0;
12615 break;
12616
12617 case R_ARM_LDC_PC_G1:
12618 case R_ARM_LDC_SB_G1:
12619 group = 1;
12620 break;
12621
12622 case R_ARM_LDC_PC_G2:
12623 case R_ARM_LDC_SB_G2:
12624 group = 2;
12625 break;
12626
12627 default:
12628 abort ();
12629 }
12630
12631 /* If REL, extract the addend from the insn. If RELA, it will
12632 have already been fetched for us. */
4962c51a 12633 if (globals->use_rel)
99059e56
RM		 12634 {
12635 int negative = (insn & (1 << 23)) ? 1 : -1;
12636 signed_addend = negative * ((insn & 0xff) << 2);
12637 }
4962c51a
MS		 12638
12639 /* Compute the value (X) to go in the place. */
99059e56
RM		 12640 if (r_type == R_ARM_LDC_PC_G0
12641 || r_type == R_ARM_LDC_PC_G1
12642 || r_type == R_ARM_LDC_PC_G2)
12643 /* PC relative. */
12644 signed_value = value - pc + signed_addend;
12645 else
12646 /* Section base relative. */
12647 signed_value = value - sb + signed_addend;
12648
12649 /* Calculate the value of the relevant G_{n-1} to obtain
12650 the residual at that stage. */
b6518b38
NC		 12651 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12652 group - 1, &residual);
99059e56
RM		 12653
12654 /* Check for overflow. (The absolute value to go in the place must be
12655 divisible by four and, after having been divided by four, must
12656 fit in eight bits.) */
12657 if ((residual & 0x3) != 0 || residual >= 0x400)
12658 {
4eca0228 12659 _bfd_error_handler
695344c0 12660 /* xgettext:c-format */
90b6238f 12661 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12662 "splitting %#" PRIx64 " for group relocation %s"),
12663 input_bfd, input_section, (uint64_t) rel->r_offset,
12664 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12665 howto->name);
99059e56
RM		 12666 return bfd_reloc_overflow;
12667 }
12668
12669 /* Mask out the value and U bit. */
12670 insn &= 0xff7fff00;
12671
12672 /* Set the U bit if the value to go in the place is non-negative. */
12673 if (signed_value >= 0)
12674 insn |= 1 << 23;
12675
12676 /* Encode the offset. */
12677 insn |= residual >> 2;
4962c51a
MS		 12678
12679 bfd_put_32 (input_bfd, insn, hit_data);
12680 }
12681 return bfd_reloc_ok;
12682
72d98d16
MG		 12683 case R_ARM_THM_ALU_ABS_G0_NC:
12684 case R_ARM_THM_ALU_ABS_G1_NC:
12685 case R_ARM_THM_ALU_ABS_G2_NC:
12686 case R_ARM_THM_ALU_ABS_G3_NC:
12687 {
12688 const int shift_array[4] = {0, 8, 16, 24};
12689 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12690 bfd_vma addr = value;
12691 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12692
12693 /* Compute address. */
12694 if (globals->use_rel)
12695 signed_addend = insn & 0xff;
12696 addr += signed_addend;
12697 if (branch_type == ST_BRANCH_TO_THUMB)
12698 addr |= 1;
12699 /* Clean imm8 insn. */
12700 insn &= 0xff00;
12701 /* And update with correct part of address. */
12702 insn |= (addr >> shift) & 0xff;
12703 /* Update insn. */
12704 bfd_put_16 (input_bfd, insn, hit_data);
12705 }
12706
12707 *unresolved_reloc_p = FALSE;
12708 return bfd_reloc_ok;
12709
e8b09b87
CL		 12710 case R_ARM_GOTOFFFUNCDESC:
12711 {
4b24dd1a 12712 if (h == NULL)
e8b09b87
CL		 12713 {
12714 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12715 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12716 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12717 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12718 bfd_vma seg = -1;
12719
12720 if (bfd_link_pic(info) && dynindx == 0)
12721 abort();
12722
12723 /* Resolve relocation. */
12724 bfd_put_32(output_bfd, (offset + sgot->output_offset)
12725 , contents + rel->r_offset);
12726 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12727 not done yet. */
12728 arm_elf_fill_funcdesc(output_bfd, info,
12729 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12730 dynindx, offset, addr, dynreloc_value, seg);
12731 }
12732 else
12733 {
12734 int dynindx;
12735 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12736 bfd_vma addr;
12737 bfd_vma seg = -1;
12738
12739 /* For static binaries, sym_sec can be null. */
12740 if (sym_sec)
12741 {
12742 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12743 addr = dynreloc_value - sym_sec->output_section->vma;
12744 }
12745 else
12746 {
12747 dynindx = 0;
12748 addr = 0;
12749 }
12750
12751 if (bfd_link_pic(info) && dynindx == 0)
12752 abort();
12753
12754 /* This case cannot occur since funcdesc is allocated by
12755 the dynamic loader so we cannot resolve the relocation. */
12756 if (h->dynindx != -1)
12757 abort();
12758
12759 /* Resolve relocation. */
12760 bfd_put_32(output_bfd, (offset + sgot->output_offset),
12761 contents + rel->r_offset);
12762 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12763 arm_elf_fill_funcdesc(output_bfd, info,
12764 &eh->fdpic_cnts.funcdesc_offset,
12765 dynindx, offset, addr, dynreloc_value, seg);
12766 }
12767 }
12768 *unresolved_reloc_p = FALSE;
12769 return bfd_reloc_ok;
12770
12771 case R_ARM_GOTFUNCDESC:
12772 {
4b24dd1a 12773 if (h != NULL)
e8b09b87
CL		 12774 {
12775 Elf_Internal_Rela outrel;
12776
12777 /* Resolve relocation. */
12778 bfd_put_32(output_bfd, ((eh->fdpic_cnts.gotfuncdesc_offset & ~1)
12779 + sgot->output_offset),
12780 contents + rel->r_offset);
12781 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12782 if(h->dynindx == -1)
12783 {
12784 int dynindx;
12785 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12786 bfd_vma addr;
12787 bfd_vma seg = -1;
12788
12789 /* For static binaries sym_sec can be null. */
12790 if (sym_sec)
12791 {
12792 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12793 addr = dynreloc_value - sym_sec->output_section->vma;
12794 }
12795 else
12796 {
12797 dynindx = 0;
12798 addr = 0;
12799 }
12800
12801 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12802 arm_elf_fill_funcdesc(output_bfd, info,
12803 &eh->fdpic_cnts.funcdesc_offset,
12804 dynindx, offset, addr, dynreloc_value, seg);
12805 }
12806
12807 /* Add a dynamic relocation on GOT entry if not already done. */
12808 if ((eh->fdpic_cnts.gotfuncdesc_offset & 1) == 0)
12809 {
12810 if (h->dynindx == -1)
12811 {
12812 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12813 if (h->root.type == bfd_link_hash_undefweak)
12814 bfd_put_32(output_bfd, 0, sgot->contents
12815 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12816 else
12817 bfd_put_32(output_bfd, sgot->output_section->vma
12818 + sgot->output_offset
12819 + (eh->fdpic_cnts.funcdesc_offset & ~1),
12820 sgot->contents
12821 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12822 }
12823 else
12824 {
12825 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12826 }
12827 outrel.r_offset = sgot->output_section->vma
12828 + sgot->output_offset
12829 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1);
12830 outrel.r_addend = 0;
12831 if (h->dynindx == -1 && !bfd_link_pic(info))
12832 if (h->root.type == bfd_link_hash_undefweak)
4b24dd1a 12833 arm_elf_add_rofixup(output_bfd, globals->srofixup, -1);
e8b09b87 12834 else
4b24dd1a
AM		 12835 arm_elf_add_rofixup(output_bfd, globals->srofixup,
12836 outrel.r_offset);
e8b09b87
CL		 12837 else
12838 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12839 eh->fdpic_cnts.gotfuncdesc_offset |= 1;
12840 }
12841 }
12842 else
12843 {
12844 /* Such relocation on static function should not have been
12845 emitted by the compiler. */
12846 abort();
12847 }
12848 }
12849 *unresolved_reloc_p = FALSE;
12850 return bfd_reloc_ok;
12851
12852 case R_ARM_FUNCDESC:
12853 {
4b24dd1a 12854 if (h == NULL)
e8b09b87
CL		 12855 {
12856 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts(input_bfd);
12857 Elf_Internal_Rela outrel;
12858 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12859 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12860 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12861 bfd_vma seg = -1;
12862
12863 if (bfd_link_pic(info) && dynindx == 0)
12864 abort();
12865
12866 /* Replace static FUNCDESC relocation with a
12867 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12868 executable. */
12869 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12870 outrel.r_offset = input_section->output_section->vma
12871 + input_section->output_offset + rel->r_offset;
12872 outrel.r_addend = 0;
12873 if (bfd_link_pic(info))
12874 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12875 else
12876 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12877
12878 bfd_put_32 (input_bfd, sgot->output_section->vma
12879 + sgot->output_offset + offset, hit_data);
12880
12881 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12882 arm_elf_fill_funcdesc(output_bfd, info,
12883 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12884 dynindx, offset, addr, dynreloc_value, seg);
12885 }
12886 else
12887 {
12888 if (h->dynindx == -1)
12889 {
12890 int dynindx;
12891 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12892 bfd_vma addr;
12893 bfd_vma seg = -1;
12894 Elf_Internal_Rela outrel;
12895
12896 /* For static binaries sym_sec can be null. */
12897 if (sym_sec)
12898 {
12899 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12900 addr = dynreloc_value - sym_sec->output_section->vma;
12901 }
12902 else
12903 {
12904 dynindx = 0;
12905 addr = 0;
12906 }
12907
12908 if (bfd_link_pic(info) && dynindx == 0)
12909 abort();
12910
12911 /* Replace static FUNCDESC relocation with a
12912 R_ARM_RELATIVE dynamic relocation. */
12913 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12914 outrel.r_offset = input_section->output_section->vma
12915 + input_section->output_offset + rel->r_offset;
12916 outrel.r_addend = 0;
12917 if (bfd_link_pic(info))
12918 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12919 else
12920 arm_elf_add_rofixup(output_bfd, globals->srofixup, outrel.r_offset);
12921
12922 bfd_put_32 (input_bfd, sgot->output_section->vma
12923 + sgot->output_offset + offset, hit_data);
12924
12925 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12926 arm_elf_fill_funcdesc(output_bfd, info,
12927 &eh->fdpic_cnts.funcdesc_offset,
12928 dynindx, offset, addr, dynreloc_value, seg);
12929 }
12930 else
12931 {
12932 Elf_Internal_Rela outrel;
12933
12934 /* Add a dynamic relocation. */
12935 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12936 outrel.r_offset = input_section->output_section->vma
12937 + input_section->output_offset + rel->r_offset;
12938 outrel.r_addend = 0;
12939 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12940 }
12941 }
12942 }
12943 *unresolved_reloc_p = FALSE;
12944 return bfd_reloc_ok;
12945
e5d6e09e
AV		 12946 case R_ARM_THM_BF16:
12947 {
12948 bfd_vma relocation;
12949 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12950 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12951
12952 if (globals->use_rel)
12953 {
12954 bfd_vma immA = (upper_insn & 0x001f);
12955 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12956 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12957 addend = (immA << 12);
12958 addend |= (immB << 2);
12959 addend |= (immC << 1);
12960 addend |= 1;
12961 /* Sign extend. */
e6f65e75 12962 signed_addend = (addend & 0x10000) ? addend - (1 << 17) : addend;
e5d6e09e
AV		 12963 }
12964
e6f65e75 12965 relocation = value + signed_addend;
e5d6e09e
AV		 12966 relocation -= (input_section->output_section->vma
12967 + input_section->output_offset
12968 + rel->r_offset);
12969
12970 /* Put RELOCATION back into the insn. */
12971 {
12972 bfd_vma immA = (relocation & 0x0001f000) >> 12;
12973 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12974 bfd_vma immC = (relocation & 0x00000002) >> 1;
12975
12976 upper_insn = (upper_insn & 0xffe0) | immA;
12977 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
12978 }
12979
12980 /* Put the relocated value back in the object file: */
12981 bfd_put_16 (input_bfd, upper_insn, hit_data);
12982 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12983
12984 return bfd_reloc_ok;
12985 }
12986
1889da70
AV		 12987 case R_ARM_THM_BF12:
12988 {
12989 bfd_vma relocation;
12990 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12991 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12992
12993 if (globals->use_rel)
12994 {
12995 bfd_vma immA = (upper_insn & 0x0001);
12996 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12997 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12998 addend = (immA << 12);
12999 addend |= (immB << 2);
13000 addend |= (immC << 1);
13001 addend |= 1;
13002 /* Sign extend. */
13003 addend = (addend & 0x1000) ? addend - (1 << 13) : addend;
e6f65e75 13004 signed_addend = addend;
1889da70
AV		 13005 }
13006
e6f65e75 13007 relocation = value + signed_addend;
1889da70
AV		 13008 relocation -= (input_section->output_section->vma
13009 + input_section->output_offset
13010 + rel->r_offset);
13011
13012 /* Put RELOCATION back into the insn. */
13013 {
13014 bfd_vma immA = (relocation & 0x00001000) >> 12;
13015 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
13016 bfd_vma immC = (relocation & 0x00000002) >> 1;
13017
13018 upper_insn = (upper_insn & 0xfffe) | immA;
13019 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
13020 }
13021
13022 /* Put the relocated value back in the object file: */
13023 bfd_put_16 (input_bfd, upper_insn, hit_data);
13024 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
13025
13026 return bfd_reloc_ok;
13027 }
13028
1caf72a5
AV		 13029 case R_ARM_THM_BF18:
13030 {
13031 bfd_vma relocation;
13032 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
13033 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
13034
13035 if (globals->use_rel)
13036 {
13037 bfd_vma immA = (upper_insn & 0x007f);
13038 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
13039 bfd_vma immC = (lower_insn & 0x0800) >> 11;
13040 addend = (immA << 12);
13041 addend |= (immB << 2);
13042 addend |= (immC << 1);
13043 addend |= 1;
13044 /* Sign extend. */
13045 addend = (addend & 0x40000) ? addend - (1 << 19) : addend;
e6f65e75 13046 signed_addend = addend;
1caf72a5
AV		 13047 }
13048
e6f65e75 13049 relocation = value + signed_addend;
1caf72a5
AV		 13050 relocation -= (input_section->output_section->vma
13051 + input_section->output_offset
13052 + rel->r_offset);
13053
13054 /* Put RELOCATION back into the insn. */
13055 {
13056 bfd_vma immA = (relocation & 0x0007f000) >> 12;
13057 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
13058 bfd_vma immC = (relocation & 0x00000002) >> 1;
13059
13060 upper_insn = (upper_insn & 0xff80) | immA;
13061 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
13062 }
13063
13064 /* Put the relocated value back in the object file: */
13065 bfd_put_16 (input_bfd, upper_insn, hit_data);
13066 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
13067
13068 return bfd_reloc_ok;
13069 }
13070
252b5132
RH		 13071 default:
13072 return bfd_reloc_notsupported;
13073 }
13074}
13075
98c1d4aa
NC		 13076/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
13077static void
07d6d2b8
AM		 13078arm_add_to_rel (bfd * abfd,
13079 bfd_byte * address,
57e8b36a 13080 reloc_howto_type * howto,
07d6d2b8 13081 bfd_signed_vma increment)
98c1d4aa 13082{
98c1d4aa
NC		 13083 bfd_signed_vma addend;
13084
bd97cb95
DJ		 13085 if (howto->type == R_ARM_THM_CALL
13086 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 13087 {
9a5aca8c
AM		 13088 int upper_insn, lower_insn;
13089 int upper, lower;
98c1d4aa 13090
9a5aca8c
AM		 13091 upper_insn = bfd_get_16 (abfd, address);
13092 lower_insn = bfd_get_16 (abfd, address + 2);
13093 upper = upper_insn & 0x7ff;
13094 lower = lower_insn & 0x7ff;
13095
13096 addend = (upper << 12) | (lower << 1);
ddda4409 13097 addend += increment;
9a5aca8c 13098 addend >>= 1;
98c1d4aa 13099
9a5aca8c
AM		 13100 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
13101 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
13102
dc810e39
AM		 13103 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
13104 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 13105 }
13106 else
13107 {
07d6d2b8 13108 bfd_vma contents;
9a5aca8c
AM		 13109
13110 contents = bfd_get_32 (abfd, address);
13111
13112 /* Get the (signed) value from the instruction. */
13113 addend = contents & howto->src_mask;
13114 if (addend & ((howto->src_mask + 1) >> 1))
13115 {
13116 bfd_signed_vma mask;
13117
13118 mask = -1;
13119 mask &= ~ howto->src_mask;
13120 addend |= mask;
13121 }
13122
13123 /* Add in the increment, (which is a byte value). */
13124 switch (howto->type)
13125 {
13126 default:
13127 addend += increment;
13128 break;
13129
13130 case R_ARM_PC24:
c6596c5e 13131 case R_ARM_PLT32:
5b5bb741
PB		 13132 case R_ARM_CALL:
13133 case R_ARM_JUMP24:
9a5aca8c 13134 addend <<= howto->size;
dc810e39 13135 addend += increment;
9a5aca8c
AM		 13136
13137 /* Should we check for overflow here ? */
13138
13139 /* Drop any undesired bits. */
13140 addend >>= howto->rightshift;
13141 break;
13142 }
13143
13144 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
13145
13146 bfd_put_32 (abfd, contents, address);
ddda4409 13147 }
98c1d4aa 13148}
252b5132 13149
ba93b8ac
DJ		 13150#define IS_ARM_TLS_RELOC(R_TYPE) \
13151 ((R_TYPE) == R_ARM_TLS_GD32 \
5c5a4843 13152 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
ba93b8ac
DJ		 13153 || (R_TYPE) == R_ARM_TLS_LDO32 \
13154 || (R_TYPE) == R_ARM_TLS_LDM32 \
5c5a4843 13155 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
ba93b8ac
DJ		 13156 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
13157 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
13158 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
13159 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b 13160 || (R_TYPE) == R_ARM_TLS_IE32 \
5c5a4843 13161 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
0855e32b
NS		 13162 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
13163
13164/* Specific set of relocations for the gnu tls dialect. */
13165#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
13166 ((R_TYPE) == R_ARM_TLS_GOTDESC \
13167 || (R_TYPE) == R_ARM_TLS_CALL \
13168 || (R_TYPE) == R_ARM_THM_TLS_CALL \
13169 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
13170 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 13171
252b5132 13172/* Relocate an ARM ELF section. */
906e58ca 13173
b34976b6 13174static bfd_boolean
07d6d2b8 13175elf32_arm_relocate_section (bfd * output_bfd,
57e8b36a 13176 struct bfd_link_info * info,
07d6d2b8
AM		 13177 bfd * input_bfd,
13178 asection * input_section,
13179 bfd_byte * contents,
13180 Elf_Internal_Rela * relocs,
13181 Elf_Internal_Sym * local_syms,
13182 asection ** local_sections)
252b5132 13183{
b34976b6
AM		 13184 Elf_Internal_Shdr *symtab_hdr;
13185 struct elf_link_hash_entry **sym_hashes;
13186 Elf_Internal_Rela *rel;
13187 Elf_Internal_Rela *relend;
13188 const char *name;
b32d3aa2 13189 struct elf32_arm_link_hash_table * globals;
252b5132 13190
4e7fd91e 13191 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13192 if (globals == NULL)
13193 return FALSE;
b491616a 13194
0ffa91dd 13195 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 13196 sym_hashes = elf_sym_hashes (input_bfd);
13197
13198 rel = relocs;
13199 relend = relocs + input_section->reloc_count;
13200 for (; rel < relend; rel++)
13201 {
07d6d2b8
AM		 13202 int r_type;
13203 reloc_howto_type * howto;
13204 unsigned long r_symndx;
13205 Elf_Internal_Sym * sym;
13206 asection * sec;
252b5132 13207 struct elf_link_hash_entry * h;
07d6d2b8
AM		 13208 bfd_vma relocation;
13209 bfd_reloc_status_type r;
13210 arelent bfd_reloc;
13211 char sym_type;
13212 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 13213 char *error_message = NULL;
f21f3fe0 13214
252b5132 13215 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 13216 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 13217 r_type = arm_real_reloc_type (globals, r_type);
252b5132 13218
ba96a88f 13219 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 13220 || r_type == R_ARM_GNU_VTINHERIT)
13221 continue;
252b5132 13222
47aeb64c
NC		 13223 howto = bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
13224
13225 if (howto == NULL)
13226 return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
252b5132 13227
252b5132
RH		 13228 h = NULL;
13229 sym = NULL;
13230 sec = NULL;
9b485d32 13231
252b5132
RH		 13232 if (r_symndx < symtab_hdr->sh_info)
13233 {
13234 sym = local_syms + r_symndx;
ba93b8ac 13235 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 13236 sec = local_sections[r_symndx];
ffcb4889
NS		 13237
13238 /* An object file might have a reference to a local
13239 undefined symbol. This is a daft object file, but we
13240 should at least do something about it. V4BX & NONE
13241 relocations do not use the symbol and are explicitly
77b4f08f
TS		 13242 allowed to use the undefined symbol, so allow those.
13243 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 13244 if (r_type != R_ARM_V4BX
13245 && r_type != R_ARM_NONE
77b4f08f 13246 && r_symndx != STN_UNDEF
ffcb4889
NS		 13247 && bfd_is_und_section (sec)
13248 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 13249 (*info->callbacks->undefined_symbol)
13250 (info, bfd_elf_string_from_elf_section
13251 (input_bfd, symtab_hdr->sh_link, sym->st_name),
13252 input_bfd, input_section,
13253 rel->r_offset, TRUE);
b38cadfb 13254
4e7fd91e 13255 if (globals->use_rel)
f8df10f4 13256 {
4e7fd91e
PB		 13257 relocation = (sec->output_section->vma
13258 + sec->output_offset
13259 + sym->st_value);
0e1862bb 13260 if (!bfd_link_relocatable (info)
ab96bf03
AM		 13261 && (sec->flags & SEC_MERGE)
13262 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 13263 {
4e7fd91e
PB		 13264 asection *msec;
13265 bfd_vma addend, value;
13266
39623e12 13267 switch (r_type)
4e7fd91e 13268 {
39623e12
PB		 13269 case R_ARM_MOVW_ABS_NC:
13270 case R_ARM_MOVT_ABS:
13271 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13272 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
13273 addend = (addend ^ 0x8000) - 0x8000;
13274 break;
f8df10f4 13275
39623e12
PB		 13276 case R_ARM_THM_MOVW_ABS_NC:
13277 case R_ARM_THM_MOVT_ABS:
13278 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
13279 << 16;
13280 value |= bfd_get_16 (input_bfd,
13281 contents + rel->r_offset + 2);
13282 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
13283 | ((value & 0x04000000) >> 15);
13284 addend = (addend ^ 0x8000) - 0x8000;
13285 break;
f8df10f4 13286
39623e12
PB		 13287 default:
13288 if (howto->rightshift
13289 || (howto->src_mask & (howto->src_mask + 1)))
13290 {
4eca0228 13291 _bfd_error_handler
695344c0 13292 /* xgettext:c-format */
2dcf00ce
AM		 13293 (_("%pB(%pA+%#" PRIx64 "): "
13294 "%s relocation against SEC_MERGE section"),
39623e12 13295 input_bfd, input_section,
2dcf00ce 13296 (uint64_t) rel->r_offset, howto->name);
39623e12
PB		 13297 return FALSE;
13298 }
13299
13300 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13301
13302 /* Get the (signed) value from the instruction. */
13303 addend = value & howto->src_mask;
13304 if (addend & ((howto->src_mask + 1) >> 1))
13305 {
13306 bfd_signed_vma mask;
13307
13308 mask = -1;
13309 mask &= ~ howto->src_mask;
13310 addend |= mask;
13311 }
13312 break;
4e7fd91e 13313 }
39623e12 13314
4e7fd91e
PB		 13315 msec = sec;
13316 addend =
13317 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
13318 - relocation;
13319 addend += msec->output_section->vma + msec->output_offset;
39623e12 13320
cc643b88 13321 /* Cases here must match those in the preceding
39623e12
PB		 13322 switch statement. */
13323 switch (r_type)
13324 {
13325 case R_ARM_MOVW_ABS_NC:
13326 case R_ARM_MOVT_ABS:
13327 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
13328 | (addend & 0xfff);
13329 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13330 break;
13331
13332 case R_ARM_THM_MOVW_ABS_NC:
13333 case R_ARM_THM_MOVT_ABS:
13334 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
13335 | (addend & 0xff) | ((addend & 0x0800) << 15);
13336 bfd_put_16 (input_bfd, value >> 16,
13337 contents + rel->r_offset);
13338 bfd_put_16 (input_bfd, value,
13339 contents + rel->r_offset + 2);
13340 break;
13341
13342 default:
13343 value = (value & ~ howto->dst_mask)
13344 | (addend & howto->dst_mask);
13345 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13346 break;
13347 }
f8df10f4 13348 }
f8df10f4 13349 }
4e7fd91e
PB		 13350 else
13351 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 13352 }
13353 else
13354 {
62d887d4 13355 bfd_boolean warned, ignored;
560e09e9 13356
b2a8e766
AM		 13357 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
13358 r_symndx, symtab_hdr, sym_hashes,
13359 h, sec, relocation,
62d887d4 13360 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 13361
13362 sym_type = h->type;
252b5132
RH		 13363 }
13364
dbaa2011 13365 if (sec != NULL && discarded_section (sec))
e4067dbb 13366 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 13367 rel, 1, relend, howto, 0, contents);
ab96bf03 13368
0e1862bb 13369 if (bfd_link_relocatable (info))
ab96bf03
AM		 13370 {
13371 /* This is a relocatable link. We don't have to change
13372 anything, unless the reloc is against a section symbol,
13373 in which case we have to adjust according to where the
13374 section symbol winds up in the output section. */
13375 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
13376 {
13377 if (globals->use_rel)
13378 arm_add_to_rel (input_bfd, contents + rel->r_offset,
13379 howto, (bfd_signed_vma) sec->output_offset);
13380 else
13381 rel->r_addend += sec->output_offset;
13382 }
13383 continue;
13384 }
13385
252b5132
RH		 13386 if (h != NULL)
13387 name = h->root.root.string;
13388 else
13389 {
13390 name = (bfd_elf_string_from_elf_section
13391 (input_bfd, symtab_hdr->sh_link, sym->st_name));
13392 if (name == NULL || *name == '\0')
fd361982 13393 name = bfd_section_name (sec);
252b5132 13394 }
f21f3fe0 13395
cf35638d 13396 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 13397 && r_type != R_ARM_NONE
13398 && (h == NULL
13399 || h->root.type == bfd_link_hash_defined
13400 || h->root.type == bfd_link_hash_defweak)
13401 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
13402 {
4eca0228 13403 _bfd_error_handler
ba93b8ac 13404 ((sym_type == STT_TLS
695344c0 13405 /* xgettext:c-format */
2dcf00ce 13406 ? _("%pB(%pA+%#" PRIx64 "): %s used with TLS symbol %s")
695344c0 13407 /* xgettext:c-format */
2dcf00ce 13408 : _("%pB(%pA+%#" PRIx64 "): %s used with non-TLS symbol %s")),
ba93b8ac
DJ		 13409 input_bfd,
13410 input_section,
2dcf00ce 13411 (uint64_t) rel->r_offset,
ba93b8ac
DJ		 13412 howto->name,
13413 name);
13414 }
13415
0855e32b 13416 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 13417 done, i.e., the relaxation produced the final output we want,
13418 and we won't let anybody mess with it. Also, we have to do
13419 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 13420 both in relaxed and non-relaxed cases. */
39d911fc
TP		 13421 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
13422 || (IS_ARM_TLS_GNU_RELOC (r_type)
13423 && !((h ? elf32_arm_hash_entry (h)->tls_type :
13424 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
13425 & GOT_TLS_GDESC)))
13426 {
13427 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
13428 contents, rel, h == NULL);
13429 /* This may have been marked unresolved because it came from
13430 a shared library. But we've just dealt with that. */
13431 unresolved_reloc = 0;
13432 }
13433 else
13434 r = bfd_reloc_continue;
b38cadfb 13435
39d911fc
TP		 13436 if (r == bfd_reloc_continue)
13437 {
13438 unsigned char branch_type =
13439 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
13440 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
13441
13442 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
13443 input_section, contents, rel,
13444 relocation, info, sec, name,
13445 sym_type, branch_type, h,
13446 &unresolved_reloc,
13447 &error_message);
13448 }
0945cdfd
DJ		 13449
13450 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13451 because such sections are not SEC_ALLOC and thus ld.so will
13452 not process them. */
13453 if (unresolved_reloc
99059e56
RM		 13454 && !((input_section->flags & SEC_DEBUGGING) != 0
13455 && h->def_dynamic)
1d5316ab
AM		 13456 && _bfd_elf_section_offset (output_bfd, info, input_section,
13457 rel->r_offset) != (bfd_vma) -1)
0945cdfd 13458 {
4eca0228 13459 _bfd_error_handler
695344c0 13460 /* xgettext:c-format */
2dcf00ce
AM		 13461 (_("%pB(%pA+%#" PRIx64 "): "
13462 "unresolvable %s relocation against symbol `%s'"),
843fe662
L		 13463 input_bfd,
13464 input_section,
2dcf00ce 13465 (uint64_t) rel->r_offset,
843fe662
L		 13466 howto->name,
13467 h->root.root.string);
0945cdfd
DJ		 13468 return FALSE;
13469 }
252b5132
RH		 13470
13471 if (r != bfd_reloc_ok)
13472 {
252b5132
RH		 13473 switch (r)
13474 {
13475 case bfd_reloc_overflow:
cf919dfd
PB		 13476 /* If the overflowing reloc was to an undefined symbol,
13477 we have already printed one error message and there
13478 is no point complaining again. */
1a72702b
AM		 13479 if (!h || h->root.type != bfd_link_hash_undefined)
13480 (*info->callbacks->reloc_overflow)
13481 (info, (h ? &h->root : NULL), name, howto->name,
13482 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13483 break;
13484
13485 case bfd_reloc_undefined:
1a72702b
AM		 13486 (*info->callbacks->undefined_symbol)
13487 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 13488 break;
13489
13490 case bfd_reloc_outofrange:
f2a9dd69 13491 error_message = _("out of range");
252b5132
RH		 13492 goto common_error;
13493
13494 case bfd_reloc_notsupported:
f2a9dd69 13495 error_message = _("unsupported relocation");
252b5132
RH		 13496 goto common_error;
13497
13498 case bfd_reloc_dangerous:
f2a9dd69 13499 /* error_message should already be set. */
252b5132
RH		 13500 goto common_error;
13501
13502 default:
f2a9dd69 13503 error_message = _("unknown error");
8029a119 13504 /* Fall through. */
252b5132
RH		 13505
13506 common_error:
f2a9dd69 13507 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 13508 (*info->callbacks->reloc_dangerous)
13509 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 13510 break;
13511 }
13512 }
13513 }
13514
b34976b6 13515 return TRUE;
252b5132
RH		 13516}
13517
91d6fa6a 13518/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 13519 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 13520 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 13521 maintaining that condition). */
13522
13523static void
13524add_unwind_table_edit (arm_unwind_table_edit **head,
13525 arm_unwind_table_edit **tail,
13526 arm_unwind_edit_type type,
13527 asection *linked_section,
91d6fa6a 13528 unsigned int tindex)
2468f9c9 13529{
21d799b5
NC		 13530 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
13531 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 13532
2468f9c9
PB		 13533 new_edit->type = type;
13534 new_edit->linked_section = linked_section;
91d6fa6a 13535 new_edit->index = tindex;
b38cadfb 13536
91d6fa6a 13537 if (tindex > 0)
2468f9c9
PB		 13538 {
13539 new_edit->next = NULL;
13540
13541 if (*tail)
13542 (*tail)->next = new_edit;
13543
13544 (*tail) = new_edit;
13545
13546 if (!*head)
13547 (*head) = new_edit;
13548 }
13549 else
13550 {
13551 new_edit->next = *head;
13552
13553 if (!*tail)
13554 *tail = new_edit;
13555
13556 *head = new_edit;
13557 }
13558}
13559
13560static _arm_elf_section_data *get_arm_elf_section_data (asection *);
13561
13562/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13563static void
13564adjust_exidx_size(asection *exidx_sec, int adjust)
13565{
13566 asection *out_sec;
13567
13568 if (!exidx_sec->rawsize)
13569 exidx_sec->rawsize = exidx_sec->size;
13570
fd361982 13571 bfd_set_section_size (exidx_sec, exidx_sec->size + adjust);
2468f9c9
PB		 13572 out_sec = exidx_sec->output_section;
13573 /* Adjust size of output section. */
fd361982 13574 bfd_set_section_size (out_sec, out_sec->size +adjust);
2468f9c9
PB		 13575}
13576
13577/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13578static void
13579insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
13580{
13581 struct _arm_elf_section_data *exidx_arm_data;
13582
13583 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13584 add_unwind_table_edit (
13585 &exidx_arm_data->u.exidx.unwind_edit_list,
13586 &exidx_arm_data->u.exidx.unwind_edit_tail,
13587 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
13588
491d01d3
YU		 13589 exidx_arm_data->additional_reloc_count++;
13590
2468f9c9
PB		 13591 adjust_exidx_size(exidx_sec, 8);
13592}
13593
13594/* Scan .ARM.exidx tables, and create a list describing edits which should be
13595 made to those tables, such that:
b38cadfb 13596
2468f9c9
PB		 13597 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13598 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 13599 codes which have been inlined into the index).
2468f9c9 13600
85fdf906
AH		 13601 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13602
2468f9c9 13603 The edits are applied when the tables are written
b38cadfb 13604 (in elf32_arm_write_section). */
2468f9c9
PB		 13605
13606bfd_boolean
13607elf32_arm_fix_exidx_coverage (asection **text_section_order,
13608 unsigned int num_text_sections,
85fdf906
AH		 13609 struct bfd_link_info *info,
13610 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 13611{
13612 bfd *inp;
13613 unsigned int last_second_word = 0, i;
13614 asection *last_exidx_sec = NULL;
13615 asection *last_text_sec = NULL;
13616 int last_unwind_type = -1;
13617
13618 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13619 text sections. */
c72f2fb2 13620 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 13621 {
13622 asection *sec;
b38cadfb 13623
2468f9c9 13624 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 13625 {
2468f9c9
PB		 13626 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
13627 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 13628
dec9d5df 13629 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 13630 continue;
b38cadfb 13631
2468f9c9
PB		 13632 if (elf_sec->linked_to)
13633 {
13634 Elf_Internal_Shdr *linked_hdr
99059e56 13635 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 13636 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 13637 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 13638
13639 if (linked_sec_arm_data == NULL)
99059e56 13640 continue;
2468f9c9
PB		 13641
13642 /* Link this .ARM.exidx section back from the text section it
99059e56 13643 describes. */
2468f9c9
PB		 13644 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
13645 }
13646 }
13647 }
13648
13649 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13650 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 13651 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 13652
13653 for (i = 0; i < num_text_sections; i++)
13654 {
13655 asection *sec = text_section_order[i];
13656 asection *exidx_sec;
13657 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
13658 struct _arm_elf_section_data *exidx_arm_data;
13659 bfd_byte *contents = NULL;
13660 int deleted_exidx_bytes = 0;
13661 bfd_vma j;
13662 arm_unwind_table_edit *unwind_edit_head = NULL;
13663 arm_unwind_table_edit *unwind_edit_tail = NULL;
13664 Elf_Internal_Shdr *hdr;
13665 bfd *ibfd;
13666
13667 if (arm_data == NULL)
99059e56 13668 continue;
2468f9c9
PB		 13669
13670 exidx_sec = arm_data->u.text.arm_exidx_sec;
13671 if (exidx_sec == NULL)
13672 {
13673 /* Section has no unwind data. */
13674 if (last_unwind_type == 0 || !last_exidx_sec)
13675 continue;
13676
13677 /* Ignore zero sized sections. */
13678 if (sec->size == 0)
13679 continue;
13680
13681 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13682 last_unwind_type = 0;
13683 continue;
13684 }
13685
22a8f80e
PB		 13686 /* Skip /DISCARD/ sections. */
13687 if (bfd_is_abs_section (exidx_sec->output_section))
13688 continue;
13689
2468f9c9
PB		 13690 hdr = &elf_section_data (exidx_sec)->this_hdr;
13691 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 13692 continue;
b38cadfb 13693
2468f9c9
PB		 13694 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13695 if (exidx_arm_data == NULL)
99059e56 13696 continue;
b38cadfb 13697
2468f9c9 13698 ibfd = exidx_sec->owner;
b38cadfb 13699
2468f9c9
PB		 13700 if (hdr->contents != NULL)
13701 contents = hdr->contents;
13702 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
13703 /* An error? */
13704 continue;
13705
ac06903d
YU		 13706 if (last_unwind_type > 0)
13707 {
13708 unsigned int first_word = bfd_get_32 (ibfd, contents);
13709 /* Add cantunwind if first unwind item does not match section
13710 start. */
13711 if (first_word != sec->vma)
13712 {
13713 insert_cantunwind_after (last_text_sec, last_exidx_sec);
13714 last_unwind_type = 0;
13715 }
13716 }
13717
2468f9c9
PB		 13718 for (j = 0; j < hdr->sh_size; j += 8)
13719 {
13720 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
13721 int unwind_type;
13722 int elide = 0;
13723
13724 /* An EXIDX_CANTUNWIND entry. */
13725 if (second_word == 1)
13726 {
13727 if (last_unwind_type == 0)
13728 elide = 1;
13729 unwind_type = 0;
13730 }
13731 /* Inlined unwinding data. Merge if equal to previous. */
13732 else if ((second_word & 0x80000000) != 0)
13733 {
85fdf906
AH		 13734 if (merge_exidx_entries
13735 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 13736 elide = 1;
13737 unwind_type = 1;
13738 last_second_word = second_word;
13739 }
13740 /* Normal table entry. In theory we could merge these too,
13741 but duplicate entries are likely to be much less common. */
13742 else
13743 unwind_type = 2;
13744
491d01d3 13745 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 13746 {
13747 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
13748 DELETE_EXIDX_ENTRY, NULL, j / 8);
13749
13750 deleted_exidx_bytes += 8;
13751 }
13752
13753 last_unwind_type = unwind_type;
13754 }
13755
13756 /* Free contents if we allocated it ourselves. */
13757 if (contents != hdr->contents)
99059e56 13758 free (contents);
2468f9c9
PB		 13759
13760 /* Record edits to be applied later (in elf32_arm_write_section). */
13761 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
13762 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 13763
2468f9c9
PB		 13764 if (deleted_exidx_bytes > 0)
13765 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
13766
13767 last_exidx_sec = exidx_sec;
13768 last_text_sec = sec;
13769 }
13770
13771 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 13772 if (!bfd_link_relocatable (info) && last_exidx_sec
13773 && last_unwind_type != 0)
2468f9c9
PB		 13774 insert_cantunwind_after(last_text_sec, last_exidx_sec);
13775
13776 return TRUE;
13777}
13778
3e6b1042
DJ		 13779static bfd_boolean
13780elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
13781 bfd *ibfd, const char *name)
13782{
13783 asection *sec, *osec;
13784
3d4d4302 13785 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 13786 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
13787 return TRUE;
13788
13789 osec = sec->output_section;
13790 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
13791 return TRUE;
13792
13793 if (! bfd_set_section_contents (obfd, osec, sec->contents,
13794 sec->output_offset, sec->size))
13795 return FALSE;
13796
13797 return TRUE;
13798}
13799
13800static bfd_boolean
13801elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
13802{
13803 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 13804 asection *sec, *osec;
3e6b1042 13805
4dfe6ac6
NC		 13806 if (globals == NULL)
13807 return FALSE;
13808
3e6b1042
DJ		 13809 /* Invoke the regular ELF backend linker to do all the work. */
13810 if (!bfd_elf_final_link (abfd, info))
13811 return FALSE;
13812
fe33d2fa
CL		 13813 /* Process stub sections (eg BE8 encoding, ...). */
13814 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 13815 unsigned int i;
cdb21a0a
NS		 13816 for (i=0; i<htab->top_id; i++)
13817 {
13818 sec = htab->stub_group[i].stub_sec;
13819 /* Only process it once, in its link_sec slot. */
13820 if (sec && i == htab->stub_group[i].link_sec->id)
13821 {
13822 osec = sec->output_section;
13823 elf32_arm_write_section (abfd, info, sec, sec->contents);
13824 if (! bfd_set_section_contents (abfd, osec, sec->contents,
13825 sec->output_offset, sec->size))
13826 return FALSE;
13827 }
fe33d2fa 13828 }
fe33d2fa 13829
3e6b1042
DJ		 13830 /* Write out any glue sections now that we have created all the
13831 stubs. */
13832 if (globals->bfd_of_glue_owner != NULL)
13833 {
13834 if (! elf32_arm_output_glue_section (info, abfd,
13835 globals->bfd_of_glue_owner,
13836 ARM2THUMB_GLUE_SECTION_NAME))
13837 return FALSE;
13838
13839 if (! elf32_arm_output_glue_section (info, abfd,
13840 globals->bfd_of_glue_owner,
13841 THUMB2ARM_GLUE_SECTION_NAME))
13842 return FALSE;
13843
13844 if (! elf32_arm_output_glue_section (info, abfd,
13845 globals->bfd_of_glue_owner,
13846 VFP11_ERRATUM_VENEER_SECTION_NAME))
13847 return FALSE;
13848
a504d23a
LA		 13849 if (! elf32_arm_output_glue_section (info, abfd,
13850 globals->bfd_of_glue_owner,
13851 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13852 return FALSE;
13853
3e6b1042
DJ		 13854 if (! elf32_arm_output_glue_section (info, abfd,
13855 globals->bfd_of_glue_owner,
13856 ARM_BX_GLUE_SECTION_NAME))
13857 return FALSE;
13858 }
13859
13860 return TRUE;
13861}
13862
5968a7b8
NC		 13863/* Return a best guess for the machine number based on the attributes. */
13864
13865static unsigned int
13866bfd_arm_get_mach_from_attributes (bfd * abfd)
13867{
13868 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
13869
13870 switch (arch)
13871 {
c0c468d5 13872 case TAG_CPU_ARCH_PRE_V4: return bfd_mach_arm_3M;
5968a7b8
NC		 13873 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
13874 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
13875 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
13876
13877 case TAG_CPU_ARCH_V5TE:
13878 {
13879 char * name;
13880
13881 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
13882 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
13883
13884 if (name)
13885 {
13886 if (strcmp (name, "IWMMXT2") == 0)
13887 return bfd_mach_arm_iWMMXt2;
13888
13889 if (strcmp (name, "IWMMXT") == 0)
6034aab8 13890 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 13891
13892 if (strcmp (name, "XSCALE") == 0)
13893 {
13894 int wmmx;
13895
13896 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
13897 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
13898 switch (wmmx)
13899 {
13900 case 1: return bfd_mach_arm_iWMMXt;
13901 case 2: return bfd_mach_arm_iWMMXt2;
13902 default: return bfd_mach_arm_XScale;
13903 }
13904 }
5968a7b8
NC		 13905 }
13906
13907 return bfd_mach_arm_5TE;
13908 }
13909
c0c468d5
TP		 13910 case TAG_CPU_ARCH_V5TEJ:
13911 return bfd_mach_arm_5TEJ;
13912 case TAG_CPU_ARCH_V6:
13913 return bfd_mach_arm_6;
13914 case TAG_CPU_ARCH_V6KZ:
13915 return bfd_mach_arm_6KZ;
13916 case TAG_CPU_ARCH_V6T2:
13917 return bfd_mach_arm_6T2;
13918 case TAG_CPU_ARCH_V6K:
13919 return bfd_mach_arm_6K;
13920 case TAG_CPU_ARCH_V7:
13921 return bfd_mach_arm_7;
13922 case TAG_CPU_ARCH_V6_M:
13923 return bfd_mach_arm_6M;
13924 case TAG_CPU_ARCH_V6S_M:
13925 return bfd_mach_arm_6SM;
13926 case TAG_CPU_ARCH_V7E_M:
13927 return bfd_mach_arm_7EM;
13928 case TAG_CPU_ARCH_V8:
13929 return bfd_mach_arm_8;
13930 case TAG_CPU_ARCH_V8R:
13931 return bfd_mach_arm_8R;
13932 case TAG_CPU_ARCH_V8M_BASE:
13933 return bfd_mach_arm_8M_BASE;
13934 case TAG_CPU_ARCH_V8M_MAIN:
13935 return bfd_mach_arm_8M_MAIN;
031254f2
AV		 13936 case TAG_CPU_ARCH_V8_1M_MAIN:
13937 return bfd_mach_arm_8_1M_MAIN;
c0c468d5 13938
5968a7b8 13939 default:
c0c468d5
TP		 13940 /* Force entry to be added for any new known Tag_CPU_arch value. */
13941 BFD_ASSERT (arch > MAX_TAG_CPU_ARCH);
13942
13943 /* Unknown Tag_CPU_arch value. */
5968a7b8
NC		 13944 return bfd_mach_arm_unknown;
13945 }
13946}
13947
c178919b
NC		 13948/* Set the right machine number. */
13949
13950static bfd_boolean
57e8b36a 13951elf32_arm_object_p (bfd *abfd)
c178919b 13952{
5a6c6817 13953 unsigned int mach;
57e8b36a 13954
5a6c6817 13955 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 13956
5968a7b8
NC		 13957 if (mach == bfd_mach_arm_unknown)
13958 {
13959 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13960 mach = bfd_mach_arm_ep9312;
13961 else
13962 mach = bfd_arm_get_mach_from_attributes (abfd);
13963 }
c178919b 13964
5968a7b8 13965 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13966 return TRUE;
13967}
13968
fc830a83 13969/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13970
b34976b6 13971static bfd_boolean
57e8b36a 13972elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13973{
13974 if (elf_flags_init (abfd)
13975 && elf_elfheader (abfd)->e_flags != flags)
13976 {
fc830a83
NC		 13977 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13978 {
fd2ec330 13979 if (flags & EF_ARM_INTERWORK)
4eca0228 13980 _bfd_error_handler
90b6238f 13981 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
d003868e 13982 abfd);
fc830a83 13983 else
d003868e 13984 _bfd_error_handler
90b6238f 13985 (_("warning: clearing the interworking flag of %pB due to outside request"),
d003868e 13986 abfd);
fc830a83 13987 }
252b5132
RH		 13988 }
13989 else
13990 {
13991 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13992 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13993 }
13994
b34976b6 13995 return TRUE;
252b5132
RH		 13996}
13997
fc830a83 13998/* Copy backend specific data from one object module to another. */
9b485d32 13999
b34976b6 14000static bfd_boolean
57e8b36a 14001elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 14002{
14003 flagword in_flags;
14004 flagword out_flags;
14005
0ffa91dd 14006 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 14007 return TRUE;
252b5132 14008
fc830a83 14009 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 14010 out_flags = elf_elfheader (obfd)->e_flags;
14011
fc830a83
NC		 14012 if (elf_flags_init (obfd)
14013 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
14014 && in_flags != out_flags)
252b5132 14015 {
252b5132 14016 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 14017 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 14018 return FALSE;
252b5132
RH		 14019
14020 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 14021 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 14022 return FALSE;
252b5132
RH		 14023
14024 /* If the src and dest have different interworking flags
99059e56 14025 then turn off the interworking bit. */
fd2ec330 14026 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 14027 {
fd2ec330 14028 if (out_flags & EF_ARM_INTERWORK)
d003868e 14029 _bfd_error_handler
90b6238f 14030 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
d003868e 14031 obfd, ibfd);
252b5132 14032
fd2ec330 14033 in_flags &= ~EF_ARM_INTERWORK;
252b5132 14034 }
1006ba19
PB		 14035
14036 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 14037 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
14038 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 14039 }
14040
14041 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 14042 elf_flags_init (obfd) = TRUE;
252b5132 14043
e2349352 14044 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 14045}
14046
14047/* Values for Tag_ABI_PCS_R9_use. */
14048enum
14049{
14050 AEABI_R9_V6,
14051 AEABI_R9_SB,
14052 AEABI_R9_TLS,
14053 AEABI_R9_unused
14054};
14055
14056/* Values for Tag_ABI_PCS_RW_data. */
14057enum
14058{
14059 AEABI_PCS_RW_data_absolute,
14060 AEABI_PCS_RW_data_PCrel,
14061 AEABI_PCS_RW_data_SBrel,
14062 AEABI_PCS_RW_data_unused
14063};
14064
14065/* Values for Tag_ABI_enum_size. */
14066enum
14067{
14068 AEABI_enum_unused,
14069 AEABI_enum_short,
14070 AEABI_enum_wide,
14071 AEABI_enum_forced_wide
14072};
14073
104d59d1
JM		 14074/* Determine whether an object attribute tag takes an integer, a
14075 string or both. */
906e58ca 14076
104d59d1
JM		 14077static int
14078elf32_arm_obj_attrs_arg_type (int tag)
14079{
14080 if (tag == Tag_compatibility)
3483fe2e 14081 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 14082 else if (tag == Tag_nodefaults)
3483fe2e
AS		 14083 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
14084 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
14085 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 14086 else if (tag < 32)
3483fe2e 14087 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 14088 else
3483fe2e 14089 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 14090}
14091
5aa6ff7c
AS		 14092/* The ABI defines that Tag_conformance should be emitted first, and that
14093 Tag_nodefaults should be second (if either is defined). This sets those
14094 two positions, and bumps up the position of all the remaining tags to
14095 compensate. */
14096static int
14097elf32_arm_obj_attrs_order (int num)
14098{
3de4a297 14099 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 14100 return Tag_conformance;
3de4a297 14101 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 14102 return Tag_nodefaults;
14103 if ((num - 2) < Tag_nodefaults)
14104 return num - 2;
14105 if ((num - 1) < Tag_conformance)
14106 return num - 1;
14107 return num;
14108}
14109
e8b36cd1
JM		 14110/* Attribute numbers >=64 (mod 128) can be safely ignored. */
14111static bfd_boolean
14112elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
14113{
14114 if ((tag & 127) < 64)
14115 {
14116 _bfd_error_handler
90b6238f 14117 (_("%pB: unknown mandatory EABI object attribute %d"),
e8b36cd1
JM		 14118 abfd, tag);
14119 bfd_set_error (bfd_error_bad_value);
14120 return FALSE;
14121 }
14122 else
14123 {
14124 _bfd_error_handler
90b6238f 14125 (_("warning: %pB: unknown EABI object attribute %d"),
e8b36cd1
JM		 14126 abfd, tag);
14127 return TRUE;
14128 }
14129}
14130
91e22acd
AS		 14131/* Read the architecture from the Tag_also_compatible_with attribute, if any.
14132 Returns -1 if no architecture could be read. */
14133
14134static int
14135get_secondary_compatible_arch (bfd *abfd)
14136{
14137 obj_attribute *attr =
14138 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
14139
14140 /* Note: the tag and its argument below are uleb128 values, though
14141 currently-defined values fit in one byte for each. */
14142 if (attr->s
14143 && attr->s[0] == Tag_CPU_arch
14144 && (attr->s[1] & 128) != 128
14145 && attr->s[2] == 0)
14146 return attr->s[1];
14147
14148 /* This tag is "safely ignorable", so don't complain if it looks funny. */
14149 return -1;
14150}
14151
14152/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
14153 The tag is removed if ARCH is -1. */
14154
8e79c3df 14155static void
91e22acd 14156set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 14157{
91e22acd
AS		 14158 obj_attribute *attr =
14159 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 14160
91e22acd
AS		 14161 if (arch == -1)
14162 {
14163 attr->s = NULL;
14164 return;
8e79c3df 14165 }
91e22acd
AS		 14166
14167 /* Note: the tag and its argument below are uleb128 values, though
14168 currently-defined values fit in one byte for each. */
14169 if (!attr->s)
21d799b5 14170 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 14171 attr->s[0] = Tag_CPU_arch;
14172 attr->s[1] = arch;
14173 attr->s[2] = '\0';
8e79c3df
CM		 14174}
14175
91e22acd
AS		 14176/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
14177 into account. */
14178
14179static int
14180tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
14181 int newtag, int secondary_compat)
8e79c3df 14182{
91e22acd
AS		 14183#define T(X) TAG_CPU_ARCH_##X
14184 int tagl, tagh, result;
14185 const int v6t2[] =
14186 {
14187 T(V6T2), /* PRE_V4. */
14188 T(V6T2), /* V4. */
14189 T(V6T2), /* V4T. */
14190 T(V6T2), /* V5T. */
14191 T(V6T2), /* V5TE. */
14192 T(V6T2), /* V5TEJ. */
14193 T(V6T2), /* V6. */
14194 T(V7), /* V6KZ. */
14195 T(V6T2) /* V6T2. */
14196 };
14197 const int v6k[] =
14198 {
14199 T(V6K), /* PRE_V4. */
14200 T(V6K), /* V4. */
14201 T(V6K), /* V4T. */
14202 T(V6K), /* V5T. */
14203 T(V6K), /* V5TE. */
14204 T(V6K), /* V5TEJ. */
14205 T(V6K), /* V6. */
14206 T(V6KZ), /* V6KZ. */
14207 T(V7), /* V6T2. */
14208 T(V6K) /* V6K. */
14209 };
14210 const int v7[] =
14211 {
14212 T(V7), /* PRE_V4. */
14213 T(V7), /* V4. */
14214 T(V7), /* V4T. */
14215 T(V7), /* V5T. */
14216 T(V7), /* V5TE. */
14217 T(V7), /* V5TEJ. */
14218 T(V7), /* V6. */
14219 T(V7), /* V6KZ. */
14220 T(V7), /* V6T2. */
14221 T(V7), /* V6K. */
14222 T(V7) /* V7. */
14223 };
14224 const int v6_m[] =
14225 {
07d6d2b8
AM		 14226 -1, /* PRE_V4. */
14227 -1, /* V4. */
91e22acd
AS		 14228 T(V6K), /* V4T. */
14229 T(V6K), /* V5T. */
14230 T(V6K), /* V5TE. */
14231 T(V6K), /* V5TEJ. */
14232 T(V6K), /* V6. */
14233 T(V6KZ), /* V6KZ. */
14234 T(V7), /* V6T2. */
14235 T(V6K), /* V6K. */
14236 T(V7), /* V7. */
14237 T(V6_M) /* V6_M. */
14238 };
14239 const int v6s_m[] =
14240 {
07d6d2b8
AM		 14241 -1, /* PRE_V4. */
14242 -1, /* V4. */
91e22acd
AS		 14243 T(V6K), /* V4T. */
14244 T(V6K), /* V5T. */
14245 T(V6K), /* V5TE. */
14246 T(V6K), /* V5TEJ. */
14247 T(V6K), /* V6. */
14248 T(V6KZ), /* V6KZ. */
14249 T(V7), /* V6T2. */
14250 T(V6K), /* V6K. */
14251 T(V7), /* V7. */
14252 T(V6S_M), /* V6_M. */
14253 T(V6S_M) /* V6S_M. */
14254 };
9e3c6df6
PB		 14255 const int v7e_m[] =
14256 {
07d6d2b8
AM		 14257 -1, /* PRE_V4. */
14258 -1, /* V4. */
9e3c6df6
PB		 14259 T(V7E_M), /* V4T. */
14260 T(V7E_M), /* V5T. */
14261 T(V7E_M), /* V5TE. */
14262 T(V7E_M), /* V5TEJ. */
14263 T(V7E_M), /* V6. */
14264 T(V7E_M), /* V6KZ. */
14265 T(V7E_M), /* V6T2. */
14266 T(V7E_M), /* V6K. */
14267 T(V7E_M), /* V7. */
14268 T(V7E_M), /* V6_M. */
14269 T(V7E_M), /* V6S_M. */
14270 T(V7E_M) /* V7E_M. */
14271 };
bca38921
MGD		 14272 const int v8[] =
14273 {
14274 T(V8), /* PRE_V4. */
14275 T(V8), /* V4. */
14276 T(V8), /* V4T. */
14277 T(V8), /* V5T. */
14278 T(V8), /* V5TE. */
14279 T(V8), /* V5TEJ. */
14280 T(V8), /* V6. */
14281 T(V8), /* V6KZ. */
14282 T(V8), /* V6T2. */
14283 T(V8), /* V6K. */
14284 T(V8), /* V7. */
14285 T(V8), /* V6_M. */
14286 T(V8), /* V6S_M. */
14287 T(V8), /* V7E_M. */
14288 T(V8) /* V8. */
14289 };
bff0500d
TP		 14290 const int v8r[] =
14291 {
14292 T(V8R), /* PRE_V4. */
14293 T(V8R), /* V4. */
14294 T(V8R), /* V4T. */
14295 T(V8R), /* V5T. */
14296 T(V8R), /* V5TE. */
14297 T(V8R), /* V5TEJ. */
14298 T(V8R), /* V6. */
14299 T(V8R), /* V6KZ. */
14300 T(V8R), /* V6T2. */
14301 T(V8R), /* V6K. */
14302 T(V8R), /* V7. */
14303 T(V8R), /* V6_M. */
14304 T(V8R), /* V6S_M. */
14305 T(V8R), /* V7E_M. */
14306 T(V8), /* V8. */
14307 T(V8R), /* V8R. */
14308 };
2fd158eb
TP		 14309 const int v8m_baseline[] =
14310 {
14311 -1, /* PRE_V4. */
14312 -1, /* V4. */
14313 -1, /* V4T. */
14314 -1, /* V5T. */
14315 -1, /* V5TE. */
14316 -1, /* V5TEJ. */
14317 -1, /* V6. */
14318 -1, /* V6KZ. */
14319 -1, /* V6T2. */
14320 -1, /* V6K. */
14321 -1, /* V7. */
14322 T(V8M_BASE), /* V6_M. */
14323 T(V8M_BASE), /* V6S_M. */
14324 -1, /* V7E_M. */
14325 -1, /* V8. */
bff0500d 14326 -1, /* V8R. */
2fd158eb
TP		 14327 T(V8M_BASE) /* V8-M BASELINE. */
14328 };
14329 const int v8m_mainline[] =
14330 {
14331 -1, /* PRE_V4. */
14332 -1, /* V4. */
14333 -1, /* V4T. */
14334 -1, /* V5T. */
14335 -1, /* V5TE. */
14336 -1, /* V5TEJ. */
14337 -1, /* V6. */
14338 -1, /* V6KZ. */
14339 -1, /* V6T2. */
14340 -1, /* V6K. */
14341 T(V8M_MAIN), /* V7. */
14342 T(V8M_MAIN), /* V6_M. */
14343 T(V8M_MAIN), /* V6S_M. */
14344 T(V8M_MAIN), /* V7E_M. */
14345 -1, /* V8. */
bff0500d 14346 -1, /* V8R. */
2fd158eb
TP		 14347 T(V8M_MAIN), /* V8-M BASELINE. */
14348 T(V8M_MAIN) /* V8-M MAINLINE. */
14349 };
031254f2
AV		 14350 const int v8_1m_mainline[] =
14351 {
14352 -1, /* PRE_V4. */
14353 -1, /* V4. */
14354 -1, /* V4T. */
14355 -1, /* V5T. */
14356 -1, /* V5TE. */
14357 -1, /* V5TEJ. */
14358 -1, /* V6. */
14359 -1, /* V6KZ. */
14360 -1, /* V6T2. */
14361 -1, /* V6K. */
14362 T(V8_1M_MAIN), /* V7. */
14363 T(V8_1M_MAIN), /* V6_M. */
14364 T(V8_1M_MAIN), /* V6S_M. */
14365 T(V8_1M_MAIN), /* V7E_M. */
14366 -1, /* V8. */
14367 -1, /* V8R. */
14368 T(V8_1M_MAIN), /* V8-M BASELINE. */
14369 T(V8_1M_MAIN), /* V8-M MAINLINE. */
14370 -1, /* Unused (18). */
14371 -1, /* Unused (19). */
14372 -1, /* Unused (20). */
14373 T(V8_1M_MAIN) /* V8.1-M MAINLINE. */
14374 };
91e22acd
AS		 14375 const int v4t_plus_v6_m[] =
14376 {
14377 -1, /* PRE_V4. */
14378 -1, /* V4. */
14379 T(V4T), /* V4T. */
14380 T(V5T), /* V5T. */
14381 T(V5TE), /* V5TE. */
14382 T(V5TEJ), /* V5TEJ. */
14383 T(V6), /* V6. */
14384 T(V6KZ), /* V6KZ. */
14385 T(V6T2), /* V6T2. */
14386 T(V6K), /* V6K. */
14387 T(V7), /* V7. */
14388 T(V6_M), /* V6_M. */
14389 T(V6S_M), /* V6S_M. */
9e3c6df6 14390 T(V7E_M), /* V7E_M. */
bca38921 14391 T(V8), /* V8. */
bff0500d 14392 -1, /* V8R. */
2fd158eb
TP		 14393 T(V8M_BASE), /* V8-M BASELINE. */
14394 T(V8M_MAIN), /* V8-M MAINLINE. */
031254f2
AV		 14395 -1, /* Unused (18). */
14396 -1, /* Unused (19). */
14397 -1, /* Unused (20). */
14398 T(V8_1M_MAIN), /* V8.1-M MAINLINE. */
91e22acd
AS		 14399 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
14400 };
14401 const int *comb[] =
14402 {
14403 v6t2,
14404 v6k,
14405 v7,
14406 v6_m,
14407 v6s_m,
9e3c6df6 14408 v7e_m,
bca38921 14409 v8,
bff0500d 14410 v8r,
2fd158eb
TP		 14411 v8m_baseline,
14412 v8m_mainline,
031254f2
AV		 14413 NULL,
14414 NULL,
14415 NULL,
14416 v8_1m_mainline,
91e22acd
AS		 14417 /* Pseudo-architecture. */
14418 v4t_plus_v6_m
14419 };
14420
14421 /* Check we've not got a higher architecture than we know about. */
14422
9e3c6df6 14423 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 14424 {
90b6238f 14425 _bfd_error_handler (_("error: %pB: unknown CPU architecture"), ibfd);
91e22acd
AS		 14426 return -1;
14427 }
14428
14429 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14430
14431 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
14432 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
14433 oldtag = T(V4T_PLUS_V6_M);
14434
14435 /* And override the new tag if we have a Tag_also_compatible_with on the
14436 input. */
14437
14438 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
14439 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
14440 newtag = T(V4T_PLUS_V6_M);
14441
14442 tagl = (oldtag < newtag) ? oldtag : newtag;
14443 result = tagh = (oldtag > newtag) ? oldtag : newtag;
14444
14445 /* Architectures before V6KZ add features monotonically. */
14446 if (tagh <= TAG_CPU_ARCH_V6KZ)
14447 return result;
14448
4ed7ed8d 14449 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 14450
14451 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14452 as the canonical version. */
14453 if (result == T(V4T_PLUS_V6_M))
14454 {
14455 result = T(V4T);
14456 *secondary_compat_out = T(V6_M);
14457 }
14458 else
14459 *secondary_compat_out = -1;
14460
14461 if (result == -1)
14462 {
90b6238f 14463 _bfd_error_handler (_("error: %pB: conflicting CPU architectures %d/%d"),
91e22acd
AS		 14464 ibfd, oldtag, newtag);
14465 return -1;
14466 }
14467
14468 return result;
14469#undef T
8e79c3df
CM		 14470}
14471
ac56ee8f
MGD		 14472/* Query attributes object to see if integer divide instructions may be
14473 present in an object. */
14474static bfd_boolean
14475elf32_arm_attributes_accept_div (const obj_attribute *attr)
14476{
14477 int arch = attr[Tag_CPU_arch].i;
14478 int profile = attr[Tag_CPU_arch_profile].i;
14479
14480 switch (attr[Tag_DIV_use].i)
14481 {
14482 case 0:
14483 /* Integer divide allowed if instruction contained in archetecture. */
14484 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
14485 return TRUE;
14486 else if (arch >= TAG_CPU_ARCH_V7E_M)
14487 return TRUE;
14488 else
14489 return FALSE;
14490
14491 case 1:
14492 /* Integer divide explicitly prohibited. */
14493 return FALSE;
14494
14495 default:
14496 /* Unrecognised case - treat as allowing divide everywhere. */
14497 case 2:
14498 /* Integer divide allowed in ARM state. */
14499 return TRUE;
14500 }
14501}
14502
14503/* Query attributes object to see if integer divide instructions are
14504 forbidden to be in the object. This is not the inverse of
14505 elf32_arm_attributes_accept_div. */
14506static bfd_boolean
14507elf32_arm_attributes_forbid_div (const obj_attribute *attr)
14508{
14509 return attr[Tag_DIV_use].i == 1;
14510}
14511
ee065d83
PB		 14512/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14513 are conflicting attributes. */
906e58ca 14514
ee065d83 14515static bfd_boolean
50e03d47 14516elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 14517{
50e03d47 14518 bfd *obfd = info->output_bfd;
104d59d1
JM		 14519 obj_attribute *in_attr;
14520 obj_attribute *out_attr;
ee065d83
PB		 14521 /* Some tags have 0 = don't care, 1 = strong requirement,
14522 2 = weak requirement. */
91e22acd 14523 static const int order_021[3] = {0, 2, 1};
ee065d83 14524 int i;
91e22acd 14525 bfd_boolean result = TRUE;
9274e9de 14526 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 14527
3e6b1042
DJ		 14528 /* Skip the linker stubs file. This preserves previous behavior
14529 of accepting unknown attributes in the first input file - but
14530 is that a bug? */
14531 if (ibfd->flags & BFD_LINKER_CREATED)
14532 return TRUE;
14533
9274e9de
TG		 14534 /* Skip any input that hasn't attribute section.
14535 This enables to link object files without attribute section with
14536 any others. */
14537 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
14538 return TRUE;
14539
104d59d1 14540 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 14541 {
14542 /* This is the first object. Copy the attributes. */
104d59d1 14543 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 14544
cd21e546
MGD		 14545 out_attr = elf_known_obj_attributes_proc (obfd);
14546
004ae526
PB		 14547 /* Use the Tag_null value to indicate the attributes have been
14548 initialized. */
cd21e546 14549 out_attr[0].i = 1;
004ae526 14550
cd21e546
MGD		 14551 /* We do not output objects with Tag_MPextension_use_legacy - we move
14552 the attribute's value to Tag_MPextension_use. */
14553 if (out_attr[Tag_MPextension_use_legacy].i != 0)
14554 {
14555 if (out_attr[Tag_MPextension_use].i != 0
14556 && out_attr[Tag_MPextension_use_legacy].i
99059e56 14557 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 14558 {
14559 _bfd_error_handler
871b3ab2 14560 (_("Error: %pB has both the current and legacy "
cd21e546
MGD		 14561 "Tag_MPextension_use attributes"), ibfd);
14562 result = FALSE;
14563 }
14564
14565 out_attr[Tag_MPextension_use] =
14566 out_attr[Tag_MPextension_use_legacy];
14567 out_attr[Tag_MPextension_use_legacy].type = 0;
14568 out_attr[Tag_MPextension_use_legacy].i = 0;
14569 }
14570
14571 return result;
ee065d83
PB		 14572 }
14573
104d59d1
JM		 14574 in_attr = elf_known_obj_attributes_proc (ibfd);
14575 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 14576 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14577 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
14578 {
5c294fee
TG		 14579 /* Ignore mismatches if the object doesn't use floating point or is
14580 floating point ABI independent. */
14581 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
14582 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14583 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 14584 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 14585 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14586 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 14587 {
14588 _bfd_error_handler
871b3ab2 14589 (_("error: %pB uses VFP register arguments, %pB does not"),
deddc40b
NS		 14590 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
14591 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 14592 result = FALSE;
ee065d83
PB		 14593 }
14594 }
14595
3de4a297 14596 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 14597 {
14598 /* Merge this attribute with existing attributes. */
14599 switch (i)
14600 {
14601 case Tag_CPU_raw_name:
14602 case Tag_CPU_name:
6a631e86 14603 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 14604 break;
14605
14606 case Tag_ABI_optimization_goals:
14607 case Tag_ABI_FP_optimization_goals:
14608 /* Use the first value seen. */
14609 break;
14610
14611 case Tag_CPU_arch:
91e22acd
AS		 14612 {
14613 int secondary_compat = -1, secondary_compat_out = -1;
14614 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 14615 int arch_attr;
14616 static const char *name_table[] =
14617 {
91e22acd
AS		 14618 /* These aren't real CPU names, but we can't guess
14619 that from the architecture version alone. */
14620 "Pre v4",
14621 "ARM v4",
14622 "ARM v4T",
14623 "ARM v5T",
14624 "ARM v5TE",
14625 "ARM v5TEJ",
14626 "ARM v6",
14627 "ARM v6KZ",
14628 "ARM v6T2",
14629 "ARM v6K",
14630 "ARM v7",
14631 "ARM v6-M",
bca38921 14632 "ARM v6S-M",
2fd158eb
TP		 14633 "ARM v8",
14634 "",
14635 "ARM v8-M.baseline",
14636 "ARM v8-M.mainline",
91e22acd
AS		 14637 };
14638
14639 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14640 secondary_compat = get_secondary_compatible_arch (ibfd);
14641 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 14642 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
14643 &secondary_compat_out,
14644 in_attr[i].i,
14645 secondary_compat);
14646
14647 /* Return with error if failed to merge. */
14648 if (arch_attr == -1)
14649 return FALSE;
14650
14651 out_attr[i].i = arch_attr;
14652
91e22acd
AS		 14653 set_secondary_compatible_arch (obfd, secondary_compat_out);
14654
14655 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14656 if (out_attr[i].i == saved_out_attr)
14657 ; /* Leave the names alone. */
14658 else if (out_attr[i].i == in_attr[i].i)
14659 {
14660 /* The output architecture has been changed to match the
14661 input architecture. Use the input names. */
14662 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
14663 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
14664 : NULL;
14665 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
14666 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
14667 : NULL;
14668 }
14669 else
14670 {
14671 out_attr[Tag_CPU_name].s = NULL;
14672 out_attr[Tag_CPU_raw_name].s = NULL;
14673 }
14674
14675 /* If we still don't have a value for Tag_CPU_name,
14676 make one up now. Tag_CPU_raw_name remains blank. */
14677 if (out_attr[Tag_CPU_name].s == NULL
14678 && out_attr[i].i < ARRAY_SIZE (name_table))
14679 out_attr[Tag_CPU_name].s =
14680 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
14681 }
14682 break;
14683
ee065d83
PB		 14684 case Tag_ARM_ISA_use:
14685 case Tag_THUMB_ISA_use:
ee065d83 14686 case Tag_WMMX_arch:
91e22acd
AS		 14687 case Tag_Advanced_SIMD_arch:
14688 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 14689 case Tag_ABI_FP_rounding:
ee065d83
PB		 14690 case Tag_ABI_FP_exceptions:
14691 case Tag_ABI_FP_user_exceptions:
14692 case Tag_ABI_FP_number_model:
75375b3e 14693 case Tag_FP_HP_extension:
91e22acd
AS		 14694 case Tag_CPU_unaligned_access:
14695 case Tag_T2EE_use:
91e22acd 14696 case Tag_MPextension_use:
a7ad558c 14697 case Tag_MVE_arch:
ee065d83
PB		 14698 /* Use the largest value specified. */
14699 if (in_attr[i].i > out_attr[i].i)
14700 out_attr[i].i = in_attr[i].i;
14701 break;
14702
75375b3e 14703 case Tag_ABI_align_preserved:
91e22acd
AS		 14704 case Tag_ABI_PCS_RO_data:
14705 /* Use the smallest value specified. */
14706 if (in_attr[i].i < out_attr[i].i)
14707 out_attr[i].i = in_attr[i].i;
14708 break;
14709
75375b3e 14710 case Tag_ABI_align_needed:
91e22acd 14711 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 14712 && (in_attr[Tag_ABI_align_preserved].i == 0
14713 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 14714 {
91e22acd
AS		 14715 /* This error message should be enabled once all non-conformant
14716 binaries in the toolchain have had the attributes set
14717 properly.
ee065d83 14718 _bfd_error_handler
871b3ab2 14719 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
91e22acd
AS		 14720 obfd, ibfd);
14721 result = FALSE; */
ee065d83 14722 }
91e22acd
AS		 14723 /* Fall through. */
14724 case Tag_ABI_FP_denormal:
14725 case Tag_ABI_PCS_GOT_use:
14726 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14727 value if greater than 2 (for future-proofing). */
14728 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
14729 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
14730 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 14731 out_attr[i].i = in_attr[i].i;
14732 break;
91e22acd 14733
75375b3e
MGD		 14734 case Tag_Virtualization_use:
14735 /* The virtualization tag effectively stores two bits of
14736 information: the intended use of TrustZone (in bit 0), and the
14737 intended use of Virtualization (in bit 1). */
14738 if (out_attr[i].i == 0)
14739 out_attr[i].i = in_attr[i].i;
14740 else if (in_attr[i].i != 0
14741 && in_attr[i].i != out_attr[i].i)
14742 {
14743 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
14744 out_attr[i].i = 3;
14745 else
14746 {
14747 _bfd_error_handler
871b3ab2
AM		 14748 (_("error: %pB: unable to merge virtualization attributes "
14749 "with %pB"),
75375b3e
MGD		 14750 obfd, ibfd);
14751 result = FALSE;
14752 }
14753 }
14754 break;
91e22acd
AS		 14755
14756 case Tag_CPU_arch_profile:
14757 if (out_attr[i].i != in_attr[i].i)
14758 {
14759 /* 0 will merge with anything.
14760 'A' and 'S' merge to 'A'.
14761 'R' and 'S' merge to 'R'.
99059e56 14762 'M' and 'A|R|S' is an error. */
91e22acd
AS		 14763 if (out_attr[i].i == 0
14764 || (out_attr[i].i == 'S'
14765 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
14766 out_attr[i].i = in_attr[i].i;
14767 else if (in_attr[i].i == 0
14768 || (in_attr[i].i == 'S'
14769 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 14770 ; /* Do nothing. */
91e22acd
AS		 14771 else
14772 {
14773 _bfd_error_handler
90b6238f 14774 (_("error: %pB: conflicting architecture profiles %c/%c"),
91e22acd
AS		 14775 ibfd,
14776 in_attr[i].i ? in_attr[i].i : '0',
14777 out_attr[i].i ? out_attr[i].i : '0');
14778 result = FALSE;
14779 }
14780 }
14781 break;
15afaa63
TP		 14782
14783 case Tag_DSP_extension:
14784 /* No need to change output value if any of:
14785 - pre (<=) ARMv5T input architecture (do not have DSP)
14786 - M input profile not ARMv7E-M and do not have DSP. */
14787 if (in_attr[Tag_CPU_arch].i <= 3
14788 || (in_attr[Tag_CPU_arch_profile].i == 'M'
14789 && in_attr[Tag_CPU_arch].i != 13
14790 && in_attr[i].i == 0))
14791 ; /* Do nothing. */
14792 /* Output value should be 0 if DSP part of architecture, ie.
14793 - post (>=) ARMv5te architecture output
14794 - A, R or S profile output or ARMv7E-M output architecture. */
14795 else if (out_attr[Tag_CPU_arch].i >= 4
14796 && (out_attr[Tag_CPU_arch_profile].i == 'A'
14797 || out_attr[Tag_CPU_arch_profile].i == 'R'
14798 || out_attr[Tag_CPU_arch_profile].i == 'S'
14799 || out_attr[Tag_CPU_arch].i == 13))
14800 out_attr[i].i = 0;
14801 /* Otherwise, DSP instructions are added and not part of output
14802 architecture. */
14803 else
14804 out_attr[i].i = 1;
14805 break;
14806
75375b3e 14807 case Tag_FP_arch:
62f3b8c8 14808 {
4547cb56
NC		 14809 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14810 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14811 when it's 0. It might mean absence of FP hardware if
99654aaf 14812 Tag_FP_arch is zero. */
4547cb56 14813
a715796b 14814#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 14815 static const struct
14816 {
14817 int ver;
14818 int regs;
bca38921 14819 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 14820 {
14821 {0, 0},
14822 {1, 16},
14823 {2, 16},
14824 {3, 32},
14825 {3, 16},
14826 {4, 32},
bca38921 14827 {4, 16},
a715796b
TG		 14828 {8, 32},
14829 {8, 16}
62f3b8c8
PB		 14830 };
14831 int ver;
14832 int regs;
14833 int newval;
14834
4547cb56
NC		 14835 /* If the output has no requirement about FP hardware,
14836 follow the requirement of the input. */
14837 if (out_attr[i].i == 0)
14838 {
4ec192e6
RE		 14839 /* This assert is still reasonable, we shouldn't
14840 produce the suspicious build attribute
14841 combination (See below for in_attr). */
4547cb56
NC		 14842 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
14843 out_attr[i].i = in_attr[i].i;
14844 out_attr[Tag_ABI_HardFP_use].i
14845 = in_attr[Tag_ABI_HardFP_use].i;
14846 break;
14847 }
14848 /* If the input has no requirement about FP hardware, do
14849 nothing. */
14850 else if (in_attr[i].i == 0)
14851 {
4ec192e6
RE		 14852 /* We used to assert that Tag_ABI_HardFP_use was
14853 zero here, but we should never assert when
14854 consuming an object file that has suspicious
14855 build attributes. The single precision variant
14856 of 'no FP architecture' is still 'no FP
14857 architecture', so we just ignore the tag in this
14858 case. */
4547cb56
NC		 14859 break;
14860 }
14861
14862 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 14863 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 14864
14865 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14866 do nothing. */
14867 if (in_attr[Tag_ABI_HardFP_use].i == 0
14868 && out_attr[Tag_ABI_HardFP_use].i == 0)
14869 ;
14870 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 14871 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 14872 else if (in_attr[Tag_ABI_HardFP_use].i
14873 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 14874 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 14875
14876 /* Now we can handle Tag_FP_arch. */
14877
bca38921
MGD		 14878 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14879 pick the biggest. */
14880 if (in_attr[i].i >= VFP_VERSION_COUNT
14881 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 14882 {
14883 out_attr[i] = in_attr[i];
14884 break;
14885 }
14886 /* The output uses the superset of input features
14887 (ISA version) and registers. */
14888 ver = vfp_versions[in_attr[i].i].ver;
14889 if (ver < vfp_versions[out_attr[i].i].ver)
14890 ver = vfp_versions[out_attr[i].i].ver;
14891 regs = vfp_versions[in_attr[i].i].regs;
14892 if (regs < vfp_versions[out_attr[i].i].regs)
14893 regs = vfp_versions[out_attr[i].i].regs;
14894 /* This assumes all possible supersets are also a valid
99059e56 14895 options. */
bca38921 14896 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 14897 {
14898 if (regs == vfp_versions[newval].regs
14899 && ver == vfp_versions[newval].ver)
14900 break;
14901 }
14902 out_attr[i].i = newval;
14903 }
b1cc4aeb 14904 break;
ee065d83
PB		 14905 case Tag_PCS_config:
14906 if (out_attr[i].i == 0)
14907 out_attr[i].i = in_attr[i].i;
b6009aca 14908 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 14909 {
14910 /* It's sometimes ok to mix different configs, so this is only
99059e56 14911 a warning. */
ee065d83 14912 _bfd_error_handler
90b6238f 14913 (_("warning: %pB: conflicting platform configuration"), ibfd);
ee065d83
PB		 14914 }
14915 break;
14916 case Tag_ABI_PCS_R9_use:
004ae526
PB		 14917 if (in_attr[i].i != out_attr[i].i
14918 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 14919 && in_attr[i].i != AEABI_R9_unused)
14920 {
14921 _bfd_error_handler
90b6238f 14922 (_("error: %pB: conflicting use of R9"), ibfd);
91e22acd 14923 result = FALSE;
ee065d83
PB		 14924 }
14925 if (out_attr[i].i == AEABI_R9_unused)
14926 out_attr[i].i = in_attr[i].i;
14927 break;
14928 case Tag_ABI_PCS_RW_data:
14929 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
14930 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
14931 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
14932 {
14933 _bfd_error_handler
871b3ab2 14934 (_("error: %pB: SB relative addressing conflicts with use of R9"),
ee065d83 14935 ibfd);
91e22acd 14936 result = FALSE;
ee065d83
PB		 14937 }
14938 /* Use the smallest value specified. */
14939 if (in_attr[i].i < out_attr[i].i)
14940 out_attr[i].i = in_attr[i].i;
14941 break;
ee065d83 14942 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 14943 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
14944 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 14945 {
14946 _bfd_error_handler
871b3ab2 14947 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
a9dc9481 14948 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 14949 }
a9dc9481 14950 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 14951 out_attr[i].i = in_attr[i].i;
14952 break;
ee065d83
PB		 14953 case Tag_ABI_enum_size:
14954 if (in_attr[i].i != AEABI_enum_unused)
14955 {
14956 if (out_attr[i].i == AEABI_enum_unused
14957 || out_attr[i].i == AEABI_enum_forced_wide)
14958 {
14959 /* The existing object is compatible with anything.
14960 Use whatever requirements the new object has. */
14961 out_attr[i].i = in_attr[i].i;
14962 }
14963 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 14964 && out_attr[i].i != in_attr[i].i
0ffa91dd 14965 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 14966 {
91e22acd 14967 static const char *aeabi_enum_names[] =
bf21ed78 14968 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 14969 const char *in_name =
14970 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14971 ? aeabi_enum_names[in_attr[i].i]
14972 : "<unknown>";
14973 const char *out_name =
14974 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14975 ? aeabi_enum_names[out_attr[i].i]
14976 : "<unknown>";
ee065d83 14977 _bfd_error_handler
871b3ab2 14978 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 14979 ibfd, in_name, out_name);
ee065d83
PB		 14980 }
14981 }
14982 break;
14983 case Tag_ABI_VFP_args:
14984 /* Aready done. */
14985 break;
14986 case Tag_ABI_WMMX_args:
14987 if (in_attr[i].i != out_attr[i].i)
14988 {
14989 _bfd_error_handler
871b3ab2 14990 (_("error: %pB uses iWMMXt register arguments, %pB does not"),
ee065d83 14991 ibfd, obfd);
91e22acd 14992 result = FALSE;
ee065d83
PB		 14993 }
14994 break;
7b86a9fa
AS		 14995 case Tag_compatibility:
14996 /* Merged in target-independent code. */
14997 break;
91e22acd 14998 case Tag_ABI_HardFP_use:
4547cb56 14999 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 15000 break;
15001 case Tag_ABI_FP_16bit_format:
15002 if (in_attr[i].i != 0 && out_attr[i].i != 0)
15003 {
15004 if (in_attr[i].i != out_attr[i].i)
15005 {
15006 _bfd_error_handler
871b3ab2 15007 (_("error: fp16 format mismatch between %pB and %pB"),
91e22acd
AS		 15008 ibfd, obfd);
15009 result = FALSE;
15010 }
15011 }
15012 if (in_attr[i].i != 0)
15013 out_attr[i].i = in_attr[i].i;
15014 break;
7b86a9fa 15015
cd21e546 15016 case Tag_DIV_use:
ac56ee8f
MGD		 15017 /* A value of zero on input means that the divide instruction may
15018 be used if available in the base architecture as specified via
15019 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
15020 the user did not want divide instructions. A value of 2
15021 explicitly means that divide instructions were allowed in ARM
15022 and Thumb state. */
15023 if (in_attr[i].i == out_attr[i].i)
15024 /* Do nothing. */ ;
15025 else if (elf32_arm_attributes_forbid_div (in_attr)
15026 && !elf32_arm_attributes_accept_div (out_attr))
15027 out_attr[i].i = 1;
15028 else if (elf32_arm_attributes_forbid_div (out_attr)
15029 && elf32_arm_attributes_accept_div (in_attr))
15030 out_attr[i].i = in_attr[i].i;
15031 else if (in_attr[i].i == 2)
15032 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 15033 break;
15034
15035 case Tag_MPextension_use_legacy:
15036 /* We don't output objects with Tag_MPextension_use_legacy - we
15037 move the value to Tag_MPextension_use. */
15038 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
15039 {
15040 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
15041 {
15042 _bfd_error_handler
871b3ab2 15043 (_("%pB has both the current and legacy "
b38cadfb 15044 "Tag_MPextension_use attributes"),
cd21e546
MGD		 15045 ibfd);
15046 result = FALSE;
15047 }
15048 }
15049
15050 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
15051 out_attr[Tag_MPextension_use] = in_attr[i];
15052
15053 break;
15054
91e22acd 15055 case Tag_nodefaults:
2d0bb761
AS		 15056 /* This tag is set if it exists, but the value is unused (and is
15057 typically zero). We don't actually need to do anything here -
15058 the merge happens automatically when the type flags are merged
15059 below. */
91e22acd
AS		 15060 break;
15061 case Tag_also_compatible_with:
15062 /* Already done in Tag_CPU_arch. */
15063 break;
15064 case Tag_conformance:
15065 /* Keep the attribute if it matches. Throw it away otherwise.
15066 No attribute means no claim to conform. */
15067 if (!in_attr[i].s || !out_attr[i].s
15068 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
15069 out_attr[i].s = NULL;
15070 break;
3cfad14c 15071
91e22acd 15072 default:
e8b36cd1
JM		 15073 result
15074 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 15075 }
15076
15077 /* If out_attr was copied from in_attr then it won't have a type yet. */
15078 if (in_attr[i].type && !out_attr[i].type)
15079 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 15080 }
15081
104d59d1 15082 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 15083 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 15084 return FALSE;
ee065d83 15085
104d59d1 15086 /* Check for any attributes not known on ARM. */
e8b36cd1 15087 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 15088
91e22acd 15089 return result;
252b5132
RH		 15090}
15091
3a4a14e9
PB		 15092
15093/* Return TRUE if the two EABI versions are incompatible. */
15094
15095static bfd_boolean
15096elf32_arm_versions_compatible (unsigned iver, unsigned over)
15097{
15098 /* v4 and v5 are the same spec before and after it was released,
15099 so allow mixing them. */
15100 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
15101 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
15102 return TRUE;
15103
15104 return (iver == over);
15105}
15106
252b5132
RH		 15107/* Merge backend specific data from an object file to the output
15108 object file when linking. */
9b485d32 15109
b34976b6 15110static bfd_boolean
50e03d47 15111elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 15112
9b485d32
NC		 15113/* Display the flags field. */
15114
b34976b6 15115static bfd_boolean
57e8b36a 15116elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 15117{
fc830a83
NC		 15118 FILE * file = (FILE *) ptr;
15119 unsigned long flags;
252b5132
RH		 15120
15121 BFD_ASSERT (abfd != NULL && ptr != NULL);
15122
15123 /* Print normal ELF private data. */
15124 _bfd_elf_print_private_bfd_data (abfd, ptr);
15125
fc830a83 15126 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 15127 /* Ignore init flag - it may not be set, despite the flags field
15128 containing valid data. */
252b5132 15129
9b485d32 15130 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 15131
fc830a83
NC		 15132 switch (EF_ARM_EABI_VERSION (flags))
15133 {
15134 case EF_ARM_EABI_UNKNOWN:
4cc11e76 15135 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 15136 official ARM ELF extended ABI. Hence they are only decoded if
15137 the EABI version is not set. */
fd2ec330 15138 if (flags & EF_ARM_INTERWORK)
9b485d32 15139 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 15140
fd2ec330 15141 if (flags & EF_ARM_APCS_26)
6c571f00 15142 fprintf (file, " [APCS-26]");
fc830a83 15143 else
6c571f00 15144 fprintf (file, " [APCS-32]");
9a5aca8c 15145
96a846ea
RE		 15146 if (flags & EF_ARM_VFP_FLOAT)
15147 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 15148 else if (flags & EF_ARM_MAVERICK_FLOAT)
15149 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 15150 else
15151 fprintf (file, _(" [FPA float format]"));
15152
fd2ec330 15153 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 15154 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 15155
fd2ec330 15156 if (flags & EF_ARM_PIC)
9b485d32 15157 fprintf (file, _(" [position independent]"));
fc830a83 15158
fd2ec330 15159 if (flags & EF_ARM_NEW_ABI)
9b485d32 15160 fprintf (file, _(" [new ABI]"));
9a5aca8c 15161
fd2ec330 15162 if (flags & EF_ARM_OLD_ABI)
9b485d32 15163 fprintf (file, _(" [old ABI]"));
9a5aca8c 15164
fd2ec330 15165 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 15166 fprintf (file, _(" [software FP]"));
9a5aca8c 15167
96a846ea
RE		 15168 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
15169 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 15170 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
15171 | EF_ARM_MAVERICK_FLOAT);
fc830a83 15172 break;
9a5aca8c 15173
fc830a83 15174 case EF_ARM_EABI_VER1:
9b485d32 15175 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 15176
fc830a83 15177 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 15178 fprintf (file, _(" [sorted symbol table]"));
fc830a83 15179 else
9b485d32 15180 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 15181
fc830a83
NC		 15182 flags &= ~ EF_ARM_SYMSARESORTED;
15183 break;
9a5aca8c 15184
fd2ec330
PB		 15185 case EF_ARM_EABI_VER2:
15186 fprintf (file, _(" [Version2 EABI]"));
15187
15188 if (flags & EF_ARM_SYMSARESORTED)
15189 fprintf (file, _(" [sorted symbol table]"));
15190 else
15191 fprintf (file, _(" [unsorted symbol table]"));
15192
15193 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
15194 fprintf (file, _(" [dynamic symbols use segment index]"));
15195
15196 if (flags & EF_ARM_MAPSYMSFIRST)
15197 fprintf (file, _(" [mapping symbols precede others]"));
15198
99e4ae17 15199 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 15200 | EF_ARM_MAPSYMSFIRST);
15201 break;
15202
d507cf36
PB		 15203 case EF_ARM_EABI_VER3:
15204 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 15205 break;
15206
15207 case EF_ARM_EABI_VER4:
15208 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 15209 goto eabi;
d507cf36 15210
3a4a14e9
PB		 15211 case EF_ARM_EABI_VER5:
15212 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 15213
15214 if (flags & EF_ARM_ABI_FLOAT_SOFT)
15215 fprintf (file, _(" [soft-float ABI]"));
15216
15217 if (flags & EF_ARM_ABI_FLOAT_HARD)
15218 fprintf (file, _(" [hard-float ABI]"));
15219
15220 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
15221
3a4a14e9 15222 eabi:
d507cf36
PB		 15223 if (flags & EF_ARM_BE8)
15224 fprintf (file, _(" [BE8]"));
15225
15226 if (flags & EF_ARM_LE8)
15227 fprintf (file, _(" [LE8]"));
15228
15229 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
15230 break;
15231
fc830a83 15232 default:
9b485d32 15233 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 15234 break;
15235 }
252b5132 15236
fc830a83 15237 flags &= ~ EF_ARM_EABIMASK;
252b5132 15238
fc830a83 15239 if (flags & EF_ARM_RELEXEC)
9b485d32 15240 fprintf (file, _(" [relocatable executable]"));
252b5132 15241
18a20338
CL		 15242 if (flags & EF_ARM_PIC)
15243 fprintf (file, _(" [position independent]"));
15244
15245 if (elf_elfheader (abfd)->e_ident[EI_OSABI] == ELFOSABI_ARM_FDPIC)
15246 fprintf (file, _(" [FDPIC ABI supplement]"));
15247
15248 flags &= ~ (EF_ARM_RELEXEC | EF_ARM_PIC);
fc830a83
NC		 15249
15250 if (flags)
9b485d32 15251 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 15252
252b5132
RH		 15253 fputc ('\n', file);
15254
b34976b6 15255 return TRUE;
252b5132
RH		 15256}
15257
15258static int
57e8b36a 15259elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 15260{
2f0ca46a
NC		 15261 switch (ELF_ST_TYPE (elf_sym->st_info))
15262 {
15263 case STT_ARM_TFUNC:
15264 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 15265
2f0ca46a
NC		 15266 case STT_ARM_16BIT:
15267 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15268 This allows us to distinguish between data used by Thumb instructions
15269 and non-data (which is probably code) inside Thumb regions of an
15270 executable. */
1a0eb693 15271 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 15272 return ELF_ST_TYPE (elf_sym->st_info);
15273 break;
9a5aca8c 15274
ce855c42
NC		 15275 default:
15276 break;
2f0ca46a
NC		 15277 }
15278
15279 return type;
252b5132 15280}
f21f3fe0 15281
252b5132 15282static asection *
07adf181
AM		 15283elf32_arm_gc_mark_hook (asection *sec,
15284 struct bfd_link_info *info,
15285 Elf_Internal_Rela *rel,
15286 struct elf_link_hash_entry *h,
15287 Elf_Internal_Sym *sym)
252b5132
RH		 15288{
15289 if (h != NULL)
07adf181 15290 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 15291 {
15292 case R_ARM_GNU_VTINHERIT:
15293 case R_ARM_GNU_VTENTRY:
07adf181
AM		 15294 return NULL;
15295 }
9ad5cbcf 15296
07adf181 15297 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 15298}
15299
780a67af
NC		 15300/* Look through the relocs for a section during the first phase. */
15301
b34976b6 15302static bfd_boolean
57e8b36a
NC		 15303elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
15304 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 15305{
b34976b6
AM		 15306 Elf_Internal_Shdr *symtab_hdr;
15307 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 15308 const Elf_Internal_Rela *rel;
15309 const Elf_Internal_Rela *rel_end;
15310 bfd *dynobj;
5e681ec4 15311 asection *sreloc;
5e681ec4 15312 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 15313 bfd_boolean call_reloc_p;
15314 bfd_boolean may_become_dynamic_p;
15315 bfd_boolean may_need_local_target_p;
ce98a316 15316 unsigned long nsyms;
9a5aca8c 15317
0e1862bb 15318 if (bfd_link_relocatable (info))
b34976b6 15319 return TRUE;
9a5aca8c 15320
0ffa91dd
NC		 15321 BFD_ASSERT (is_arm_elf (abfd));
15322
5e681ec4 15323 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15324 if (htab == NULL)
15325 return FALSE;
15326
5e681ec4 15327 sreloc = NULL;
9a5aca8c 15328
67687978
PB		 15329 /* Create dynamic sections for relocatable executables so that we can
15330 copy relocations. */
15331 if (htab->root.is_relocatable_executable
15332 && ! htab->root.dynamic_sections_created)
15333 {
15334 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
15335 return FALSE;
15336 }
15337
cbc704f3
RS		 15338 if (htab->root.dynobj == NULL)
15339 htab->root.dynobj = abfd;
34e77a92
RS		 15340 if (!create_ifunc_sections (info))
15341 return FALSE;
cbc704f3
RS		 15342
15343 dynobj = htab->root.dynobj;
15344
0ffa91dd 15345 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 15346 sym_hashes = elf_sym_hashes (abfd);
ce98a316 15347 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 15348
252b5132
RH		 15349 rel_end = relocs + sec->reloc_count;
15350 for (rel = relocs; rel < rel_end; rel++)
15351 {
34e77a92 15352 Elf_Internal_Sym *isym;
252b5132 15353 struct elf_link_hash_entry *h;
b7693d02 15354 struct elf32_arm_link_hash_entry *eh;
d42c267e 15355 unsigned int r_symndx;
eb043451 15356 int r_type;
9a5aca8c 15357
252b5132 15358 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 15359 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 15360 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 15361
ce98a316
NC		 15362 if (r_symndx >= nsyms
15363 /* PR 9934: It is possible to have relocations that do not
15364 refer to symbols, thus it is also possible to have an
15365 object file containing relocations but no symbol table. */
cf35638d 15366 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 15367 {
871b3ab2 15368 _bfd_error_handler (_("%pB: bad symbol index: %d"), abfd,
4eca0228 15369 r_symndx);
ba93b8ac
DJ		 15370 return FALSE;
15371 }
15372
34e77a92
RS		 15373 h = NULL;
15374 isym = NULL;
15375 if (nsyms > 0)
973a3492 15376 {
34e77a92
RS		 15377 if (r_symndx < symtab_hdr->sh_info)
15378 {
15379 /* A local symbol. */
15380 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
15381 abfd, r_symndx);
15382 if (isym == NULL)
15383 return FALSE;
15384 }
15385 else
15386 {
15387 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
15388 while (h->root.type == bfd_link_hash_indirect
15389 || h->root.type == bfd_link_hash_warning)
15390 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15391 }
973a3492 15392 }
9a5aca8c 15393
b7693d02
DJ		 15394 eh = (struct elf32_arm_link_hash_entry *) h;
15395
f6e32f6d
RS		 15396 call_reloc_p = FALSE;
15397 may_become_dynamic_p = FALSE;
15398 may_need_local_target_p = FALSE;
15399
0855e32b
NS		 15400 /* Could be done earlier, if h were already available. */
15401 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 15402 switch (r_type)
99059e56 15403 {
e8b09b87
CL		 15404 case R_ARM_GOTOFFFUNCDESC:
15405 {
15406 if (h == NULL)
15407 {
15408 if (!elf32_arm_allocate_local_sym_info (abfd))
15409 return FALSE;
15410 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].gotofffuncdesc_cnt += 1;
15411 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15412 }
15413 else
15414 {
15415 eh->fdpic_cnts.gotofffuncdesc_cnt++;
15416 }
15417 }
15418 break;
15419
15420 case R_ARM_GOTFUNCDESC:
15421 {
15422 if (h == NULL)
15423 {
15424 /* Such a relocation is not supposed to be generated
15425 by gcc on a static function. */
15426 /* Anyway if needed it could be handled. */
15427 abort();
15428 }
15429 else
15430 {
15431 eh->fdpic_cnts.gotfuncdesc_cnt++;
15432 }
15433 }
15434 break;
15435
15436 case R_ARM_FUNCDESC:
15437 {
15438 if (h == NULL)
15439 {
15440 if (!elf32_arm_allocate_local_sym_info (abfd))
15441 return FALSE;
15442 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_cnt += 1;
15443 elf32_arm_local_fdpic_cnts(abfd)[r_symndx].funcdesc_offset = -1;
15444 }
15445 else
15446 {
15447 eh->fdpic_cnts.funcdesc_cnt++;
15448 }
15449 }
15450 break;
15451
5e681ec4 15452 case R_ARM_GOT32:
eb043451 15453 case R_ARM_GOT_PREL:
ba93b8ac 15454 case R_ARM_TLS_GD32:
5c5a4843 15455 case R_ARM_TLS_GD32_FDPIC:
ba93b8ac 15456 case R_ARM_TLS_IE32:
5c5a4843 15457 case R_ARM_TLS_IE32_FDPIC:
0855e32b
NS		 15458 case R_ARM_TLS_GOTDESC:
15459 case R_ARM_TLS_DESCSEQ:
15460 case R_ARM_THM_TLS_DESCSEQ:
15461 case R_ARM_TLS_CALL:
15462 case R_ARM_THM_TLS_CALL:
5e681ec4 15463 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 15464 {
15465 int tls_type, old_tls_type;
5e681ec4 15466
ba93b8ac
DJ		 15467 switch (r_type)
15468 {
15469 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
5c5a4843 15470 case R_ARM_TLS_GD32_FDPIC: tls_type = GOT_TLS_GD; break;
b38cadfb 15471
ba93b8ac 15472 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
5c5a4843 15473 case R_ARM_TLS_IE32_FDPIC: tls_type = GOT_TLS_IE; break;
b38cadfb 15474
0855e32b
NS		 15475 case R_ARM_TLS_GOTDESC:
15476 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
15477 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
15478 tls_type = GOT_TLS_GDESC; break;
b38cadfb 15479
ba93b8ac
DJ		 15480 default: tls_type = GOT_NORMAL; break;
15481 }
252b5132 15482
0e1862bb 15483 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 15484 info->flags |= DF_STATIC_TLS;
15485
ba93b8ac
DJ		 15486 if (h != NULL)
15487 {
15488 h->got.refcount++;
15489 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
15490 }
15491 else
15492 {
ba93b8ac 15493 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 15494 if (!elf32_arm_allocate_local_sym_info (abfd))
15495 return FALSE;
15496 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 15497 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
15498 }
15499
0855e32b 15500 /* If a variable is accessed with both tls methods, two
99059e56 15501 slots may be created. */
0855e32b
NS		 15502 if (GOT_TLS_GD_ANY_P (old_tls_type)
15503 && GOT_TLS_GD_ANY_P (tls_type))
15504 tls_type |= old_tls_type;
15505
15506 /* We will already have issued an error message if there
15507 is a TLS/non-TLS mismatch, based on the symbol
15508 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 15509 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
15510 && tls_type != GOT_NORMAL)
15511 tls_type |= old_tls_type;
15512
0855e32b 15513 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 15514 method, we're able to relax. Turn off the GDESC flag,
15515 without messing up with any other kind of tls types
6a631e86 15516 that may be involved. */
0855e32b
NS		 15517 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
15518 tls_type &= ~GOT_TLS_GDESC;
15519
ba93b8ac
DJ		 15520 if (old_tls_type != tls_type)
15521 {
15522 if (h != NULL)
15523 elf32_arm_hash_entry (h)->tls_type = tls_type;
15524 else
15525 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
15526 }
15527 }
8029a119 15528 /* Fall through. */
ba93b8ac
DJ		 15529
15530 case R_ARM_TLS_LDM32:
5c5a4843
CL		 15531 case R_ARM_TLS_LDM32_FDPIC:
15532 if (r_type == R_ARM_TLS_LDM32 || r_type == R_ARM_TLS_LDM32_FDPIC)
ba93b8ac 15533 htab->tls_ldm_got.refcount++;
8029a119 15534 /* Fall through. */
252b5132 15535
c19d1205 15536 case R_ARM_GOTOFF32:
5e681ec4 15537 case R_ARM_GOTPC:
cbc704f3
RS		 15538 if (htab->root.sgot == NULL
15539 && !create_got_section (htab->root.dynobj, info))
15540 return FALSE;
252b5132
RH		 15541 break;
15542
252b5132 15543 case R_ARM_PC24:
7359ea65 15544 case R_ARM_PLT32:
5b5bb741
PB		 15545 case R_ARM_CALL:
15546 case R_ARM_JUMP24:
eb043451 15547 case R_ARM_PREL31:
c19d1205 15548 case R_ARM_THM_CALL:
bd97cb95
DJ		 15549 case R_ARM_THM_JUMP24:
15550 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 15551 call_reloc_p = TRUE;
15552 may_need_local_target_p = TRUE;
15553 break;
15554
15555 case R_ARM_ABS12:
15556 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15557 ldr __GOTT_INDEX__ offsets. */
15558 if (!htab->vxworks_p)
15559 {
15560 may_need_local_target_p = TRUE;
15561 break;
15562 }
aebf9be7 15563 else goto jump_over;
9eaff861 15564
f6e32f6d 15565 /* Fall through. */
39623e12 15566
96c23d59
JM		 15567 case R_ARM_MOVW_ABS_NC:
15568 case R_ARM_MOVT_ABS:
15569 case R_ARM_THM_MOVW_ABS_NC:
15570 case R_ARM_THM_MOVT_ABS:
0e1862bb 15571 if (bfd_link_pic (info))
96c23d59 15572 {
4eca0228 15573 _bfd_error_handler
871b3ab2 15574 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
96c23d59
JM		 15575 abfd, elf32_arm_howto_table_1[r_type].name,
15576 (h) ? h->root.root.string : "a local symbol");
15577 bfd_set_error (bfd_error_bad_value);
15578 return FALSE;
15579 }
15580
15581 /* Fall through. */
39623e12
PB		 15582 case R_ARM_ABS32:
15583 case R_ARM_ABS32_NOI:
aebf9be7 15584 jump_over:
0e1862bb 15585 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 15586 {
15587 h->pointer_equality_needed = 1;
15588 }
15589 /* Fall through. */
39623e12
PB		 15590 case R_ARM_REL32:
15591 case R_ARM_REL32_NOI:
b6895b4f
PB		 15592 case R_ARM_MOVW_PREL_NC:
15593 case R_ARM_MOVT_PREL:
b6895b4f
PB		 15594 case R_ARM_THM_MOVW_PREL_NC:
15595 case R_ARM_THM_MOVT_PREL:
39623e12 15596
b7693d02 15597 /* Should the interworking branches be listed here? */
e8b09b87
CL		 15598 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable
15599 || htab->fdpic_p)
34e77a92
RS		 15600 && (sec->flags & SEC_ALLOC) != 0)
15601 {
15602 if (h == NULL
469a3493 15603 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 15604 {
15605 /* In shared libraries and relocatable executables,
15606 we treat local relative references as calls;
15607 see the related SYMBOL_CALLS_LOCAL code in
15608 allocate_dynrelocs. */
15609 call_reloc_p = TRUE;
15610 may_need_local_target_p = TRUE;
15611 }
15612 else
15613 /* We are creating a shared library or relocatable
15614 executable, and this is a reloc against a global symbol,
15615 or a non-PC-relative reloc against a local symbol.
15616 We may need to copy the reloc into the output. */
15617 may_become_dynamic_p = TRUE;
15618 }
f6e32f6d
RS		 15619 else
15620 may_need_local_target_p = TRUE;
252b5132
RH		 15621 break;
15622
99059e56
RM		 15623 /* This relocation describes the C++ object vtable hierarchy.
15624 Reconstruct it for later use during GC. */
15625 case R_ARM_GNU_VTINHERIT:
15626 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
15627 return FALSE;
15628 break;
15629
15630 /* This relocation describes which C++ vtable entries are actually
15631 used. Record for later use during GC. */
15632 case R_ARM_GNU_VTENTRY:
a0ea3a14 15633 if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
99059e56
RM		 15634 return FALSE;
15635 break;
15636 }
f6e32f6d
RS		 15637
15638 if (h != NULL)
15639 {
15640 if (call_reloc_p)
15641 /* We may need a .plt entry if the function this reloc
15642 refers to is in a different object, regardless of the
15643 symbol's type. We can't tell for sure yet, because
15644 something later might force the symbol local. */
15645 h->needs_plt = 1;
15646 else if (may_need_local_target_p)
15647 /* If this reloc is in a read-only section, we might
15648 need a copy reloc. We can't check reliably at this
15649 stage whether the section is read-only, as input
15650 sections have not yet been mapped to output sections.
15651 Tentatively set the flag for now, and correct in
15652 adjust_dynamic_symbol. */
15653 h->non_got_ref = 1;
15654 }
15655
34e77a92
RS		 15656 if (may_need_local_target_p
15657 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 15658 {
34e77a92
RS		 15659 union gotplt_union *root_plt;
15660 struct arm_plt_info *arm_plt;
15661 struct arm_local_iplt_info *local_iplt;
15662
15663 if (h != NULL)
15664 {
15665 root_plt = &h->plt;
15666 arm_plt = &eh->plt;
15667 }
15668 else
15669 {
15670 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
15671 if (local_iplt == NULL)
15672 return FALSE;
15673 root_plt = &local_iplt->root;
15674 arm_plt = &local_iplt->arm;
15675 }
15676
f6e32f6d
RS		 15677 /* If the symbol is a function that doesn't bind locally,
15678 this relocation will need a PLT entry. */
a8c887dd
NC		 15679 if (root_plt->refcount != -1)
15680 root_plt->refcount += 1;
34e77a92
RS		 15681
15682 if (!call_reloc_p)
15683 arm_plt->noncall_refcount++;
f6e32f6d
RS		 15684
15685 /* It's too early to use htab->use_blx here, so we have to
15686 record possible blx references separately from
15687 relocs that definitely need a thumb stub. */
15688
15689 if (r_type == R_ARM_THM_CALL)
34e77a92 15690 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 15691
15692 if (r_type == R_ARM_THM_JUMP24
15693 || r_type == R_ARM_THM_JUMP19)
34e77a92 15694 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 15695 }
15696
15697 if (may_become_dynamic_p)
15698 {
15699 struct elf_dyn_relocs *p, **head;
15700
15701 /* Create a reloc section in dynobj. */
15702 if (sreloc == NULL)
15703 {
15704 sreloc = _bfd_elf_make_dynamic_reloc_section
15705 (sec, dynobj, 2, abfd, ! htab->use_rel);
15706
15707 if (sreloc == NULL)
15708 return FALSE;
15709
15710 /* BPABI objects never have dynamic relocations mapped. */
15711 if (htab->symbian_p)
15712 {
15713 flagword flags;
15714
fd361982 15715 flags = bfd_section_flags (sreloc);
f6e32f6d 15716 flags &= ~(SEC_LOAD | SEC_ALLOC);
fd361982 15717 bfd_set_section_flags (sreloc, flags);
f6e32f6d
RS		 15718 }
15719 }
15720
15721 /* If this is a global symbol, count the number of
15722 relocations we need for this symbol. */
15723 if (h != NULL)
15724 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
15725 else
15726 {
34e77a92
RS		 15727 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
15728 if (head == NULL)
f6e32f6d 15729 return FALSE;
f6e32f6d
RS		 15730 }
15731
15732 p = *head;
15733 if (p == NULL || p->sec != sec)
15734 {
986f0783 15735 size_t amt = sizeof *p;
f6e32f6d
RS		 15736
15737 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
15738 if (p == NULL)
15739 return FALSE;
15740 p->next = *head;
15741 *head = p;
15742 p->sec = sec;
15743 p->count = 0;
15744 p->pc_count = 0;
15745 }
15746
469a3493 15747 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 15748 p->pc_count += 1;
15749 p->count += 1;
e8b09b87
CL		 15750 if (h == NULL && htab->fdpic_p && !bfd_link_pic(info)
15751 && r_type != R_ARM_ABS32 && r_type != R_ARM_ABS32_NOI) {
15752 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15753 that will become rofixup. */
15754 /* This is due to the fact that we suppose all will become rofixup. */
15755 fprintf(stderr, "FDPIC does not yet support %d relocation to become dynamic for executable\n", r_type);
15756 _bfd_error_handler
15757 (_("FDPIC does not yet support %s relocation"
15758 " to become dynamic for executable"),
15759 elf32_arm_howto_table_1[r_type].name);
15760 abort();
15761 }
f6e32f6d 15762 }
252b5132 15763 }
f21f3fe0 15764
b34976b6 15765 return TRUE;
252b5132
RH		 15766}
15767
9eaff861
AO		 15768static void
15769elf32_arm_update_relocs (asection *o,
15770 struct bfd_elf_section_reloc_data *reldata)
15771{
15772 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
15773 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
15774 const struct elf_backend_data *bed;
15775 _arm_elf_section_data *eado;
15776 struct bfd_link_order *p;
15777 bfd_byte *erela_head, *erela;
15778 Elf_Internal_Rela *irela_head, *irela;
15779 Elf_Internal_Shdr *rel_hdr;
15780 bfd *abfd;
15781 unsigned int count;
15782
15783 eado = get_arm_elf_section_data (o);
15784
15785 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
15786 return;
15787
15788 abfd = o->owner;
15789 bed = get_elf_backend_data (abfd);
15790 rel_hdr = reldata->hdr;
15791
15792 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
15793 {
15794 swap_in = bed->s->swap_reloc_in;
15795 swap_out = bed->s->swap_reloc_out;
15796 }
15797 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
15798 {
15799 swap_in = bed->s->swap_reloca_in;
15800 swap_out = bed->s->swap_reloca_out;
15801 }
15802 else
15803 abort ();
15804
15805 erela_head = rel_hdr->contents;
15806 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
15807 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
15808
15809 erela = erela_head;
15810 irela = irela_head;
15811 count = 0;
15812
15813 for (p = o->map_head.link_order; p; p = p->next)
15814 {
15815 if (p->type == bfd_section_reloc_link_order
15816 || p->type == bfd_symbol_reloc_link_order)
15817 {
15818 (*swap_in) (abfd, erela, irela);
15819 erela += rel_hdr->sh_entsize;
15820 irela++;
15821 count++;
15822 }
15823 else if (p->type == bfd_indirect_link_order)
15824 {
15825 struct bfd_elf_section_reloc_data *input_reldata;
15826 arm_unwind_table_edit *edit_list, *edit_tail;
15827 _arm_elf_section_data *eadi;
15828 bfd_size_type j;
15829 bfd_vma offset;
15830 asection *i;
15831
15832 i = p->u.indirect.section;
15833
15834 eadi = get_arm_elf_section_data (i);
15835 edit_list = eadi->u.exidx.unwind_edit_list;
15836 edit_tail = eadi->u.exidx.unwind_edit_tail;
539300fb 15837 offset = i->output_offset;
9eaff861
AO		 15838
15839 if (eadi->elf.rel.hdr &&
15840 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
15841 input_reldata = &eadi->elf.rel;
15842 else if (eadi->elf.rela.hdr &&
15843 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
15844 input_reldata = &eadi->elf.rela;
15845 else
15846 abort ();
15847
15848 if (edit_list)
15849 {
15850 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15851 {
15852 arm_unwind_table_edit *edit_node, *edit_next;
15853 bfd_vma bias;
c48182bf 15854 bfd_vma reloc_index;
9eaff861
AO		 15855
15856 (*swap_in) (abfd, erela, irela);
c48182bf 15857 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 15858
15859 bias = 0;
15860 edit_node = edit_list;
15861 for (edit_next = edit_list;
c48182bf 15862 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 15863 edit_next = edit_node->next)
15864 {
15865 bias++;
15866 edit_node = edit_next;
15867 }
15868
15869 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 15870 || edit_node->index != reloc_index)
9eaff861
AO		 15871 {
15872 irela->r_offset -= bias * 8;
15873 irela++;
15874 count++;
15875 }
15876
15877 erela += rel_hdr->sh_entsize;
15878 }
15879
15880 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
15881 {
15882 /* New relocation entity. */
15883 asection *text_sec = edit_tail->linked_section;
15884 asection *text_out = text_sec->output_section;
15885 bfd_vma exidx_offset = offset + i->size - 8;
15886
15887 irela->r_addend = 0;
15888 irela->r_offset = exidx_offset;
15889 irela->r_info = ELF32_R_INFO
15890 (text_out->target_index, R_ARM_PREL31);
15891 irela++;
15892 count++;
15893 }
15894 }
15895 else
15896 {
15897 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15898 {
15899 (*swap_in) (abfd, erela, irela);
15900 erela += rel_hdr->sh_entsize;
15901 irela++;
15902 }
15903
15904 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15905 }
15906 }
15907 }
15908
15909 reldata->count = count;
15910 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15911
15912 erela = erela_head;
15913 irela = irela_head;
15914 while (count > 0)
15915 {
15916 (*swap_out) (abfd, irela, erela);
15917 erela += rel_hdr->sh_entsize;
15918 irela++;
15919 count--;
15920 }
15921
15922 free (irela_head);
15923
15924 /* Hashes are no longer valid. */
15925 free (reldata->hashes);
15926 reldata->hashes = NULL;
15927}
15928
6a5bb875 15929/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 15930 required if the corresponding code section is marked. Similarly, ARMv8-M
15931 secure entry functions can only be referenced by SG veneers which are
15932 created after the GC process. They need to be marked in case they reside in
15933 their own section (as would be the case if code was compiled with
15934 -ffunction-sections). */
6a5bb875
PB		 15935
15936static bfd_boolean
906e58ca
NC		 15937elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15938 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 15939{
15940 bfd *sub;
15941 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 15942 asection *cmse_sec;
15943 obj_attribute *out_attr;
15944 Elf_Internal_Shdr *symtab_hdr;
15945 unsigned i, sym_count, ext_start;
15946 const struct elf_backend_data *bed;
15947 struct elf_link_hash_entry **sym_hashes;
15948 struct elf32_arm_link_hash_entry *cmse_hash;
15949 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
bb32413f
SP		 15950 bfd_boolean debug_sec_need_to_be_marked = FALSE;
15951 asection *isec;
6a5bb875 15952
7f6ab9f8
AM		 15953 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15954
4ba2ef8f
TP		 15955 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15956 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15957 && out_attr[Tag_CPU_arch_profile].i == 'M';
15958
6a5bb875
PB		 15959 /* Marking EH data may cause additional code sections to be marked,
15960 requiring multiple passes. */
15961 again = TRUE;
15962 while (again)
15963 {
15964 again = FALSE;
c72f2fb2 15965 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 15966 {
15967 asection *o;
15968
0ffa91dd 15969 if (! is_arm_elf (sub))
6a5bb875
PB		 15970 continue;
15971
15972 elf_shdrp = elf_elfsections (sub);
15973 for (o = sub->sections; o != NULL; o = o->next)
15974 {
15975 Elf_Internal_Shdr *hdr;
0ffa91dd 15976
6a5bb875 15977 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 15978 if (hdr->sh_type == SHT_ARM_EXIDX
15979 && hdr->sh_link
15980 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 15981 && !o->gc_mark
15982 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15983 {
15984 again = TRUE;
15985 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15986 return FALSE;
15987 }
15988 }
4ba2ef8f
TP		 15989
15990 /* Mark section holding ARMv8-M secure entry functions. We mark all
15991 of them so no need for a second browsing. */
15992 if (is_v8m && first_bfd_browse)
15993 {
15994 sym_hashes = elf_sym_hashes (sub);
15995 bed = get_elf_backend_data (sub);
15996 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15997 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15998 ext_start = symtab_hdr->sh_info;
15999
16000 /* Scan symbols. */
16001 for (i = ext_start; i < sym_count; i++)
16002 {
16003 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
16004
16005 /* Assume it is a special symbol. If not, cmse_scan will
16006 warn about it and user can do something about it. */
baf46cd7
AM		 16007 if (CONST_STRNEQ (cmse_hash->root.root.root.string,
16008 CMSE_PREFIX))
4ba2ef8f
TP		 16009 {
16010 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 16011 if (!cmse_sec->gc_mark
16012 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f 16013 return FALSE;
bb32413f
SP		 16014 /* The debug sections related to these secure entry
16015 functions are marked on enabling below flag. */
16016 debug_sec_need_to_be_marked = TRUE;
4ba2ef8f
TP		 16017 }
16018 }
bb32413f
SP		 16019
16020 if (debug_sec_need_to_be_marked)
16021 {
16022 /* Looping over all the sections of the object file containing
16023 Armv8-M secure entry functions and marking all the debug
16024 sections. */
16025 for (isec = sub->sections; isec != NULL; isec = isec->next)
16026 {
16027 /* If not a debug sections, skip it. */
16028 if (!isec->gc_mark && (isec->flags & SEC_DEBUGGING))
16029 isec->gc_mark = 1 ;
16030 }
16031 debug_sec_need_to_be_marked = FALSE;
16032 }
4ba2ef8f 16033 }
6a5bb875 16034 }
4ba2ef8f 16035 first_bfd_browse = FALSE;
6a5bb875
PB		 16036 }
16037
16038 return TRUE;
16039}
16040
3c9458e9
NC		 16041/* Treat mapping symbols as special target symbols. */
16042
16043static bfd_boolean
16044elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
16045{
b0796911
PB		 16046 return bfd_is_arm_special_symbol_name (sym->name,
16047 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 16048}
16049
e7679060
AM		 16050/* If the ELF symbol SYM might be a function in SEC, return the
16051 function size and set *CODE_OFF to the function's entry point,
16052 otherwise return zero. */
252b5132 16053
e7679060
AM		 16054static bfd_size_type
16055elf32_arm_maybe_function_sym (const asymbol *sym, asection *sec,
16056 bfd_vma *code_off)
16057{
16058 bfd_size_type size;
252b5132 16059
e7679060
AM		 16060 if ((sym->flags & (BSF_SECTION_SYM | BSF_FILE | BSF_OBJECT
16061 | BSF_THREAD_LOCAL | BSF_RELC | BSF_SRELC)) != 0
16062 || sym->section != sec)
16063 return 0;
252b5132 16064
e7679060
AM		 16065 if (!(sym->flags & BSF_SYNTHETIC))
16066 switch (ELF_ST_TYPE (((elf_symbol_type *) sym)->internal_elf_sym.st_info))
16067 {
252b5132
RH		 16068 case STT_FUNC:
16069 case STT_ARM_TFUNC:
9d2da7ca 16070 case STT_NOTYPE:
252b5132 16071 break;
e7679060
AM		 16072 default:
16073 return 0;
16074 }
0367ecfb 16075
e7679060
AM		 16076 if ((sym->flags & BSF_LOCAL)
16077 && bfd_is_arm_special_symbol_name (sym->name,
16078 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
16079 return 0;
0367ecfb 16080
e7679060
AM		 16081 *code_off = sym->value;
16082 size = 0;
16083 if (!(sym->flags & BSF_SYNTHETIC))
16084 size = ((elf_symbol_type *) sym)->internal_elf_sym.st_size;
16085 if (size == 0)
16086 size = 1;
16087 return size;
252b5132
RH		 16088}
16089
4ab527b0 16090static bfd_boolean
07d6d2b8 16091elf32_arm_find_inliner_info (bfd * abfd,
4ab527b0
FF		 16092 const char ** filename_ptr,
16093 const char ** functionname_ptr,
16094 unsigned int * line_ptr)
16095{
16096 bfd_boolean found;
16097 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
16098 functionname_ptr, line_ptr,
16099 & elf_tdata (abfd)->dwarf2_find_line_info);
16100 return found;
16101}
16102
63c1f59d
AM		 16103/* Find dynamic relocs for H that apply to read-only sections. */
16104
16105static asection *
16106readonly_dynrelocs (struct elf_link_hash_entry *h)
16107{
16108 struct elf_dyn_relocs *p;
16109
16110 for (p = elf32_arm_hash_entry (h)->dyn_relocs; p != NULL; p = p->next)
16111 {
16112 asection *s = p->sec->output_section;
16113
16114 if (s != NULL && (s->flags & SEC_READONLY) != 0)
16115 return p->sec;
16116 }
16117 return NULL;
16118}
16119
252b5132
RH		 16120/* Adjust a symbol defined by a dynamic object and referenced by a
16121 regular object. The current definition is in some section of the
16122 dynamic object, but we're not including those sections. We have to
16123 change the definition to something the rest of the link can
16124 understand. */
16125
b34976b6 16126static bfd_boolean
57e8b36a
NC		 16127elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
16128 struct elf_link_hash_entry * h)
252b5132
RH		 16129{
16130 bfd * dynobj;
5474d94f 16131 asection *s, *srel;
b7693d02 16132 struct elf32_arm_link_hash_entry * eh;
67687978 16133 struct elf32_arm_link_hash_table *globals;
252b5132 16134
67687978 16135 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16136 if (globals == NULL)
16137 return FALSE;
16138
252b5132
RH		 16139 dynobj = elf_hash_table (info)->dynobj;
16140
16141 /* Make sure we know what is going on here. */
16142 BFD_ASSERT (dynobj != NULL
f5385ebf 16143 && (h->needs_plt
34e77a92 16144 || h->type == STT_GNU_IFUNC
60d67dc8 16145 || h->is_weakalias
f5385ebf
AM		 16146 || (h->def_dynamic
16147 && h->ref_regular
16148 && !h->def_regular)));
252b5132 16149
b7693d02
DJ		 16150 eh = (struct elf32_arm_link_hash_entry *) h;
16151
252b5132
RH		 16152 /* If this is a function, put it in the procedure linkage table. We
16153 will fill in the contents of the procedure linkage table later,
16154 when we know the address of the .got section. */
34e77a92 16155 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 16156 {
34e77a92
RS		 16157 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
16158 symbol binds locally. */
5e681ec4 16159 if (h->plt.refcount <= 0
34e77a92
RS		 16160 || (h->type != STT_GNU_IFUNC
16161 && (SYMBOL_CALLS_LOCAL (info, h)
16162 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16163 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 16164 {
16165 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 16166 file, but the symbol was never referred to by a dynamic
16167 object, or if all references were garbage collected. In
16168 such a case, we don't actually need to build a procedure
16169 linkage table, and we can just do a PC24 reloc instead. */
16170 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16171 eh->plt.thumb_refcount = 0;
16172 eh->plt.maybe_thumb_refcount = 0;
16173 eh->plt.noncall_refcount = 0;
f5385ebf 16174 h->needs_plt = 0;
252b5132
RH		 16175 }
16176
b34976b6 16177 return TRUE;
252b5132 16178 }
5e681ec4 16179 else
b7693d02
DJ		 16180 {
16181 /* It's possible that we incorrectly decided a .plt reloc was
16182 needed for an R_ARM_PC24 or similar reloc to a non-function sym
16183 in check_relocs. We can't decide accurately between function
16184 and non-function syms in check-relocs; Objects loaded later in
16185 the link may change h->type. So fix it now. */
16186 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 16187 eh->plt.thumb_refcount = 0;
16188 eh->plt.maybe_thumb_refcount = 0;
16189 eh->plt.noncall_refcount = 0;
b7693d02 16190 }
252b5132
RH		 16191
16192 /* If this is a weak symbol, and there is a real definition, the
16193 processor independent code will have arranged for us to see the
16194 real definition first, and we can just use the same value. */
60d67dc8 16195 if (h->is_weakalias)
252b5132 16196 {
60d67dc8
AM		 16197 struct elf_link_hash_entry *def = weakdef (h);
16198 BFD_ASSERT (def->root.type == bfd_link_hash_defined);
16199 h->root.u.def.section = def->root.u.def.section;
16200 h->root.u.def.value = def->root.u.def.value;
b34976b6 16201 return TRUE;
252b5132
RH		 16202 }
16203
ba93b8ac
DJ		 16204 /* If there are no non-GOT references, we do not need a copy
16205 relocation. */
16206 if (!h->non_got_ref)
16207 return TRUE;
16208
252b5132
RH		 16209 /* This is a reference to a symbol defined by a dynamic object which
16210 is not a function. */
16211
16212 /* If we are creating a shared library, we must presume that the
16213 only references to the symbol are via the global offset table.
16214 For such cases we need not do anything here; the relocations will
67687978
PB		 16215 be handled correctly by relocate_section. Relocatable executables
16216 can reference data in shared objects directly, so we don't need to
16217 do anything here. */
0e1862bb 16218 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 16219 return TRUE;
252b5132
RH		 16220
16221 /* We must allocate the symbol in our .dynbss section, which will
16222 become part of the .bss section of the executable. There will be
16223 an entry for this symbol in the .dynsym section. The dynamic
16224 object will contain position independent code, so all references
16225 from the dynamic object to this symbol will go through the global
16226 offset table. The dynamic linker will use the .dynsym entry to
16227 determine the address it must put in the global offset table, so
16228 both the dynamic object and the regular object will refer to the
16229 same memory location for the variable. */
5522f910
NC		 16230 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16231 linker to copy the initial value out of the dynamic object and into
16232 the runtime process image. We need to remember the offset into the
00a97672 16233 .rel(a).bss section we are going to use. */
5474d94f
AM		 16234 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
16235 {
16236 s = globals->root.sdynrelro;
16237 srel = globals->root.sreldynrelro;
16238 }
16239 else
16240 {
16241 s = globals->root.sdynbss;
16242 srel = globals->root.srelbss;
16243 }
5522f910
NC		 16244 if (info->nocopyreloc == 0
16245 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 16246 && h->size != 0)
252b5132 16247 {
47beaa6a 16248 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 16249 h->needs_copy = 1;
252b5132
RH		 16250 }
16251
6cabe1ea 16252 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 16253}
16254
5e681ec4
PB		 16255/* Allocate space in .plt, .got and associated reloc sections for
16256 dynamic relocs. */
16257
16258static bfd_boolean
47beaa6a 16259allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 16260{
16261 struct bfd_link_info *info;
16262 struct elf32_arm_link_hash_table *htab;
16263 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 16264 struct elf_dyn_relocs *p;
5e681ec4
PB		 16265
16266 if (h->root.type == bfd_link_hash_indirect)
16267 return TRUE;
16268
e6a6bb22
AM		 16269 eh = (struct elf32_arm_link_hash_entry *) h;
16270
5e681ec4
PB		 16271 info = (struct bfd_link_info *) inf;
16272 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16273 if (htab == NULL)
16274 return FALSE;
5e681ec4 16275
34e77a92 16276 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 16277 && h->plt.refcount > 0)
16278 {
16279 /* Make sure this symbol is output as a dynamic symbol.
16280 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16281 if (h->dynindx == -1 && !h->forced_local
16282 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16283 {
c152c796 16284 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16285 return FALSE;
16286 }
16287
34e77a92
RS		 16288 /* If the call in the PLT entry binds locally, the associated
16289 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16290 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16291 than the .plt section. */
16292 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
16293 {
16294 eh->is_iplt = 1;
16295 if (eh->plt.noncall_refcount == 0
16296 && SYMBOL_REFERENCES_LOCAL (info, h))
16297 /* All non-call references can be resolved directly.
16298 This means that they can (and in some cases, must)
16299 resolve directly to the run-time target, rather than
16300 to the PLT. That in turns means that any .got entry
16301 would be equal to the .igot.plt entry, so there's
16302 no point having both. */
16303 h->got.refcount = 0;
16304 }
16305
0e1862bb 16306 if (bfd_link_pic (info)
34e77a92 16307 || eh->is_iplt
7359ea65 16308 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 16309 {
34e77a92 16310 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 16311
5e681ec4
PB		 16312 /* If this symbol is not defined in a regular file, and we are
16313 not generating a shared library, then set the symbol to this
16314 location in the .plt. This is required to make function
16315 pointers compare as equal between the normal executable and
16316 the shared library. */
0e1862bb 16317 if (! bfd_link_pic (info)
f5385ebf 16318 && !h->def_regular)
5e681ec4 16319 {
34e77a92 16320 h->root.u.def.section = htab->root.splt;
5e681ec4 16321 h->root.u.def.value = h->plt.offset;
5e681ec4 16322
67d74e43
DJ		 16323 /* Make sure the function is not marked as Thumb, in case
16324 it is the target of an ABS32 relocation, which will
16325 point to the PLT entry. */
39d911fc 16326 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 16327 }
022f8312 16328
00a97672
RS		 16329 /* VxWorks executables have a second set of relocations for
16330 each PLT entry. They go in a separate relocation section,
16331 which is processed by the kernel loader. */
0e1862bb 16332 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 16333 {
16334 /* There is a relocation for the initial PLT entry:
16335 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16336 if (h->plt.offset == htab->plt_header_size)
47beaa6a 16337 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 16338
16339 /* There are two extra relocations for each subsequent
16340 PLT entry: an R_ARM_32 relocation for the GOT entry,
16341 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 16342 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 16343 }
5e681ec4
PB		 16344 }
16345 else
16346 {
16347 h->plt.offset = (bfd_vma) -1;
f5385ebf 16348 h->needs_plt = 0;
5e681ec4
PB		 16349 }
16350 }
16351 else
16352 {
16353 h->plt.offset = (bfd_vma) -1;
f5385ebf 16354 h->needs_plt = 0;
5e681ec4
PB		 16355 }
16356
0855e32b
NS		 16357 eh = (struct elf32_arm_link_hash_entry *) h;
16358 eh->tlsdesc_got = (bfd_vma) -1;
16359
5e681ec4
PB		 16360 if (h->got.refcount > 0)
16361 {
16362 asection *s;
16363 bfd_boolean dyn;
ba93b8ac
DJ		 16364 int tls_type = elf32_arm_hash_entry (h)->tls_type;
16365 int indx;
5e681ec4
PB		 16366
16367 /* Make sure this symbol is output as a dynamic symbol.
16368 Undefined weak syms won't yet be marked as dynamic. */
e8b09b87 16369 if (htab->root.dynamic_sections_created && h->dynindx == -1 && !h->forced_local
6c699715 16370 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16371 {
c152c796 16372 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16373 return FALSE;
16374 }
16375
e5a52504
MM		 16376 if (!htab->symbian_p)
16377 {
362d30a1 16378 s = htab->root.sgot;
e5a52504 16379 h->got.offset = s->size;
ba93b8ac
DJ		 16380
16381 if (tls_type == GOT_UNKNOWN)
16382 abort ();
16383
16384 if (tls_type == GOT_NORMAL)
16385 /* Non-TLS symbols need one GOT slot. */
16386 s->size += 4;
16387 else
16388 {
99059e56
RM		 16389 if (tls_type & GOT_TLS_GDESC)
16390 {
0855e32b 16391 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 16392 eh->tlsdesc_got
0855e32b
NS		 16393 = (htab->root.sgotplt->size
16394 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 16395 htab->root.sgotplt->size += 8;
16396 h->got.offset = (bfd_vma) -2;
34e77a92 16397 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16398 reloc in the middle of .got.plt. */
99059e56
RM		 16399 htab->num_tls_desc++;
16400 }
0855e32b 16401
ba93b8ac 16402 if (tls_type & GOT_TLS_GD)
0855e32b 16403 {
5c5a4843
CL		 16404 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16405 consecutive GOT slots. If the symbol is both GD
16406 and GDESC, got.offset may have been
16407 overwritten. */
0855e32b
NS		 16408 h->got.offset = s->size;
16409 s->size += 8;
16410 }
16411
ba93b8ac 16412 if (tls_type & GOT_TLS_IE)
5c5a4843
CL		 16413 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16414 slot. */
ba93b8ac
DJ		 16415 s->size += 4;
16416 }
16417
e5a52504 16418 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 16419
16420 indx = 0;
0e1862bb
L		 16421 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
16422 bfd_link_pic (info),
16423 h)
16424 && (!bfd_link_pic (info)
ba93b8ac
DJ		 16425 || !SYMBOL_REFERENCES_LOCAL (info, h)))
16426 indx = h->dynindx;
16427
16428 if (tls_type != GOT_NORMAL
9cb09e33 16429 && (bfd_link_dll (info) || indx != 0)
ba93b8ac
DJ		 16430 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16431 || h->root.type != bfd_link_hash_undefweak))
16432 {
16433 if (tls_type & GOT_TLS_IE)
47beaa6a 16434 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 16435
16436 if (tls_type & GOT_TLS_GD)
47beaa6a 16437 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16438
b38cadfb 16439 if (tls_type & GOT_TLS_GDESC)
0855e32b 16440 {
47beaa6a 16441 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 16442 /* GDESC needs a trampoline to jump to. */
16443 htab->tls_trampoline = -1;
16444 }
16445
16446 /* Only GD needs it. GDESC just emits one relocation per
16447 2 entries. */
b38cadfb 16448 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 16449 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 16450 }
e8b09b87
CL		 16451 else if (((indx != -1) || htab->fdpic_p)
16452 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 16453 {
16454 if (htab->root.dynamic_sections_created)
16455 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16456 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16457 }
34e77a92
RS		 16458 else if (h->type == STT_GNU_IFUNC
16459 && eh->plt.noncall_refcount == 0)
16460 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16461 they all resolve dynamically instead. Reserve room for the
16462 GOT entry's R_ARM_IRELATIVE relocation. */
16463 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb 16464 else if (bfd_link_pic (info)
7f026732 16465 && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
b436d854 16466 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 16467 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16468 else if (htab->fdpic_p && tls_type == GOT_NORMAL)
16469 /* Reserve room for rofixup for FDPIC executable. */
16470 /* TLS relocs do not need space since they are completely
16471 resolved. */
16472 htab->srofixup->size += 4;
e5a52504 16473 }
5e681ec4
PB		 16474 }
16475 else
16476 h->got.offset = (bfd_vma) -1;
16477
e8b09b87
CL		 16478 /* FDPIC support. */
16479 if (eh->fdpic_cnts.gotofffuncdesc_cnt > 0)
16480 {
16481 /* Symbol musn't be exported. */
16482 if (h->dynindx != -1)
16483 abort();
16484
16485 /* We only allocate one function descriptor with its associated relocation. */
16486 if (eh->fdpic_cnts.funcdesc_offset == -1)
16487 {
16488 asection *s = htab->root.sgot;
16489
16490 eh->fdpic_cnts.funcdesc_offset = s->size;
16491 s->size += 8;
16492 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16493 if (bfd_link_pic(info))
16494 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16495 else
16496 htab->srofixup->size += 8;
16497 }
16498 }
16499
16500 if (eh->fdpic_cnts.gotfuncdesc_cnt > 0)
16501 {
16502 asection *s = htab->root.sgot;
16503
16504 if (htab->root.dynamic_sections_created && h->dynindx == -1
16505 && !h->forced_local)
16506 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16507 return FALSE;
16508
16509 if (h->dynindx == -1)
16510 {
16511 /* We only allocate one function descriptor with its associated relocation. q */
16512 if (eh->fdpic_cnts.funcdesc_offset == -1)
16513 {
16514
16515 eh->fdpic_cnts.funcdesc_offset = s->size;
16516 s->size += 8;
16517 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16518 if (bfd_link_pic(info))
16519 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16520 else
16521 htab->srofixup->size += 8;
16522 }
16523 }
16524
16525 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16526 R_ARM_RELATIVE/rofixup relocation on it. */
16527 eh->fdpic_cnts.gotfuncdesc_offset = s->size;
16528 s->size += 4;
16529 if (h->dynindx == -1 && !bfd_link_pic(info))
4b24dd1a 16530 htab->srofixup->size += 4;
e8b09b87 16531 else
4b24dd1a 16532 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e8b09b87
CL		 16533 }
16534
16535 if (eh->fdpic_cnts.funcdesc_cnt > 0)
16536 {
16537 if (htab->root.dynamic_sections_created && h->dynindx == -1
16538 && !h->forced_local)
16539 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16540 return FALSE;
16541
16542 if (h->dynindx == -1)
16543 {
16544 /* We only allocate one function descriptor with its associated relocation. */
16545 if (eh->fdpic_cnts.funcdesc_offset == -1)
16546 {
16547 asection *s = htab->root.sgot;
16548
16549 eh->fdpic_cnts.funcdesc_offset = s->size;
16550 s->size += 8;
16551 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16552 if (bfd_link_pic(info))
16553 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16554 else
16555 htab->srofixup->size += 8;
16556 }
16557 }
16558 if (h->dynindx == -1 && !bfd_link_pic(info))
16559 {
16560 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16561 htab->srofixup->size += 4 * eh->fdpic_cnts.funcdesc_cnt;
16562 }
16563 else
16564 {
16565 /* Will need one dynamic reloc per reference. will be either
16566 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16567 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot,
16568 eh->fdpic_cnts.funcdesc_cnt);
16569 }
16570 }
16571
a4fd1a8e
PB		 16572 /* Allocate stubs for exported Thumb functions on v4t. */
16573 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 16574 && h->def_regular
39d911fc 16575 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 16576 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
16577 {
16578 struct elf_link_hash_entry * th;
16579 struct bfd_link_hash_entry * bh;
16580 struct elf_link_hash_entry * myh;
16581 char name[1024];
16582 asection *s;
16583 bh = NULL;
16584 /* Create a new symbol to regist the real location of the function. */
16585 s = h->root.u.def.section;
906e58ca 16586 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 16587 _bfd_generic_link_add_one_symbol (info, s->owner,
16588 name, BSF_GLOBAL, s,
16589 h->root.u.def.value,
16590 NULL, TRUE, FALSE, &bh);
16591
16592 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 16593 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 16594 myh->forced_local = 1;
39d911fc 16595 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 16596 eh->export_glue = myh;
16597 th = record_arm_to_thumb_glue (info, h);
16598 /* Point the symbol at the stub. */
16599 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 16600 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 16601 h->root.u.def.section = th->root.u.def.section;
16602 h->root.u.def.value = th->root.u.def.value & ~1;
16603 }
16604
0bdcacaf 16605 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 16606 return TRUE;
16607
16608 /* In the shared -Bsymbolic case, discard space allocated for
16609 dynamic pc-relative relocs against symbols which turn out to be
16610 defined in regular objects. For the normal shared case, discard
16611 space for pc-relative relocs that have become local due to symbol
16612 visibility changes. */
16613
e8b09b87 16614 if (bfd_link_pic (info) || htab->root.is_relocatable_executable || htab->fdpic_p)
5e681ec4 16615 {
469a3493
RM		 16616 /* Relocs that use pc_count are PC-relative forms, which will appear
16617 on something like ".long foo - ." or "movw REG, foo - .". We want
16618 calls to protected symbols to resolve directly to the function
16619 rather than going via the plt. If people want function pointer
16620 comparisons to work as expected then they should avoid writing
16621 assembly like ".long foo - .". */
ba93b8ac
DJ		 16622 if (SYMBOL_CALLS_LOCAL (info, h))
16623 {
0bdcacaf 16624 struct elf_dyn_relocs **pp;
ba93b8ac 16625
0bdcacaf 16626 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 16627 {
16628 p->count -= p->pc_count;
16629 p->pc_count = 0;
16630 if (p->count == 0)
16631 *pp = p->next;
16632 else
16633 pp = &p->next;
16634 }
16635 }
16636
4dfe6ac6 16637 if (htab->vxworks_p)
3348747a 16638 {
0bdcacaf 16639 struct elf_dyn_relocs **pp;
3348747a 16640
0bdcacaf 16641 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 16642 {
0bdcacaf 16643 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 16644 *pp = p->next;
16645 else
16646 pp = &p->next;
16647 }
16648 }
16649
ba93b8ac 16650 /* Also discard relocs on undefined weak syms with non-default
99059e56 16651 visibility. */
0bdcacaf 16652 if (eh->dyn_relocs != NULL
5e681ec4 16653 && h->root.type == bfd_link_hash_undefweak)
22d606e9 16654 {
95b03e4a
L		 16655 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16656 || UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
0bdcacaf 16657 eh->dyn_relocs = NULL;
22d606e9
AM		 16658
16659 /* Make sure undefined weak symbols are output as a dynamic
16660 symbol in PIEs. */
e8b09b87 16661 else if (htab->root.dynamic_sections_created && h->dynindx == -1
22d606e9
AM		 16662 && !h->forced_local)
16663 {
16664 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16665 return FALSE;
16666 }
16667 }
16668
67687978
PB		 16669 else if (htab->root.is_relocatable_executable && h->dynindx == -1
16670 && h->root.type == bfd_link_hash_new)
16671 {
16672 /* Output absolute symbols so that we can create relocations
16673 against them. For normal symbols we output a relocation
16674 against the section that contains them. */
16675 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16676 return FALSE;
16677 }
16678
5e681ec4
PB		 16679 }
16680 else
16681 {
16682 /* For the non-shared case, discard space for relocs against
16683 symbols which turn out to need copy relocs or are not
16684 dynamic. */
16685
f5385ebf
AM		 16686 if (!h->non_got_ref
16687 && ((h->def_dynamic
16688 && !h->def_regular)
5e681ec4
PB		 16689 || (htab->root.dynamic_sections_created
16690 && (h->root.type == bfd_link_hash_undefweak
16691 || h->root.type == bfd_link_hash_undefined))))
16692 {
16693 /* Make sure this symbol is output as a dynamic symbol.
16694 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 16695 if (h->dynindx == -1 && !h->forced_local
16696 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 16697 {
c152c796 16698 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 16699 return FALSE;
16700 }
16701
16702 /* If that succeeded, we know we'll be keeping all the
16703 relocs. */
16704 if (h->dynindx != -1)
16705 goto keep;
16706 }
16707
0bdcacaf 16708 eh->dyn_relocs = NULL;
5e681ec4
PB		 16709
16710 keep: ;
16711 }
16712
16713 /* Finally, allocate space. */
0bdcacaf 16714 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 16715 {
0bdcacaf 16716 asection *sreloc = elf_section_data (p->sec)->sreloc;
e8b09b87 16717
34e77a92
RS		 16718 if (h->type == STT_GNU_IFUNC
16719 && eh->plt.noncall_refcount == 0
16720 && SYMBOL_REFERENCES_LOCAL (info, h))
16721 elf32_arm_allocate_irelocs (info, sreloc, p->count);
e8b09b87
CL		 16722 else if (h->dynindx != -1 && (!bfd_link_pic(info) || !info->symbolic || !h->def_regular))
16723 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
16724 else if (htab->fdpic_p && !bfd_link_pic(info))
16725 htab->srofixup->size += 4 * p->count;
34e77a92
RS		 16726 else
16727 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 16728 }
16729
16730 return TRUE;
16731}
16732
63c1f59d
AM		 16733/* Set DF_TEXTREL if we find any dynamic relocs that apply to
16734 read-only sections. */
08d1f311
DJ		 16735
16736static bfd_boolean
63c1f59d 16737maybe_set_textrel (struct elf_link_hash_entry *h, void *info_p)
08d1f311 16738{
63c1f59d 16739 asection *sec;
08d1f311 16740
63c1f59d
AM		 16741 if (h->root.type == bfd_link_hash_indirect)
16742 return TRUE;
08d1f311 16743
63c1f59d
AM		 16744 sec = readonly_dynrelocs (h);
16745 if (sec != NULL)
16746 {
16747 struct bfd_link_info *info = (struct bfd_link_info *) info_p;
08d1f311 16748
63c1f59d
AM		 16749 info->flags |= DF_TEXTREL;
16750 info->callbacks->minfo
c1c8c1ef 16751 (_("%pB: dynamic relocation against `%pT' in read-only section `%pA'\n"),
63c1f59d 16752 sec->owner, h->root.root.string, sec);
08d1f311 16753
63c1f59d
AM		 16754 /* Not an error, just cut short the traversal. */
16755 return FALSE;
08d1f311 16756 }
cb10292c 16757
08d1f311
DJ		 16758 return TRUE;
16759}
16760
d504ffc8
DJ		 16761void
16762bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
16763 int byteswap_code)
16764{
16765 struct elf32_arm_link_hash_table *globals;
16766
16767 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16768 if (globals == NULL)
16769 return;
16770
d504ffc8
DJ		 16771 globals->byteswap_code = byteswap_code;
16772}
16773
252b5132
RH		 16774/* Set the sizes of the dynamic sections. */
16775
b34976b6 16776static bfd_boolean
57e8b36a
NC		 16777elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
16778 struct bfd_link_info * info)
252b5132
RH		 16779{
16780 bfd * dynobj;
16781 asection * s;
b34976b6
AM		 16782 bfd_boolean plt;
16783 bfd_boolean relocs;
5e681ec4
PB		 16784 bfd *ibfd;
16785 struct elf32_arm_link_hash_table *htab;
252b5132 16786
5e681ec4 16787 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16788 if (htab == NULL)
16789 return FALSE;
16790
252b5132
RH		 16791 dynobj = elf_hash_table (info)->dynobj;
16792 BFD_ASSERT (dynobj != NULL);
39b41c9c 16793 check_use_blx (htab);
252b5132
RH		 16794
16795 if (elf_hash_table (info)->dynamic_sections_created)
16796 {
16797 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 16798 if (bfd_link_executable (info) && !info->nointerp)
252b5132 16799 {
3d4d4302 16800 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 16801 BFD_ASSERT (s != NULL);
eea6121a 16802 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 16803 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
16804 }
16805 }
5e681ec4
PB		 16806
16807 /* Set up .got offsets for local syms, and space for local dynamic
16808 relocs. */
c72f2fb2 16809 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 16810 {
5e681ec4
PB		 16811 bfd_signed_vma *local_got;
16812 bfd_signed_vma *end_local_got;
34e77a92 16813 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 16814 char *local_tls_type;
0855e32b 16815 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 16816 bfd_size_type locsymcount;
16817 Elf_Internal_Shdr *symtab_hdr;
16818 asection *srel;
4dfe6ac6 16819 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 16820 unsigned int symndx;
e8b09b87 16821 struct fdpic_local *local_fdpic_cnts;
5e681ec4 16822
0ffa91dd 16823 if (! is_arm_elf (ibfd))
5e681ec4
PB		 16824 continue;
16825
16826 for (s = ibfd->sections; s != NULL; s = s->next)
16827 {
0bdcacaf 16828 struct elf_dyn_relocs *p;
5e681ec4 16829
0bdcacaf 16830 for (p = (struct elf_dyn_relocs *)
99059e56 16831 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 16832 {
0bdcacaf
RS		 16833 if (!bfd_is_abs_section (p->sec)
16834 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 16835 {
16836 /* Input section has been discarded, either because
16837 it is a copy of a linkonce section or due to
16838 linker script /DISCARD/, so we'll be discarding
16839 the relocs too. */
16840 }
3348747a 16841 else if (is_vxworks
0bdcacaf 16842 && strcmp (p->sec->output_section->name,
3348747a
NS		 16843 ".tls_vars") == 0)
16844 {
16845 /* Relocations in vxworks .tls_vars sections are
16846 handled specially by the loader. */
16847 }
5e681ec4
PB		 16848 else if (p->count != 0)
16849 {
0bdcacaf 16850 srel = elf_section_data (p->sec)->sreloc;
e8b09b87
CL		 16851 if (htab->fdpic_p && !bfd_link_pic(info))
16852 htab->srofixup->size += 4 * p->count;
16853 else
16854 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 16855 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 16856 info->flags |= DF_TEXTREL;
16857 }
16858 }
16859 }
16860
16861 local_got = elf_local_got_refcounts (ibfd);
16862 if (!local_got)
16863 continue;
16864
0ffa91dd 16865 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 16866 locsymcount = symtab_hdr->sh_info;
16867 end_local_got = local_got + locsymcount;
34e77a92 16868 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 16869 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 16870 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
e8b09b87 16871 local_fdpic_cnts = elf32_arm_local_fdpic_cnts (ibfd);
34e77a92 16872 symndx = 0;
362d30a1
RS		 16873 s = htab->root.sgot;
16874 srel = htab->root.srelgot;
0855e32b 16875 for (; local_got < end_local_got;
34e77a92 16876 ++local_got, ++local_iplt_ptr, ++local_tls_type,
e8b09b87 16877 ++local_tlsdesc_gotent, ++symndx, ++local_fdpic_cnts)
5e681ec4 16878 {
0855e32b 16879 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92 16880 local_iplt = *local_iplt_ptr;
e8b09b87
CL		 16881
16882 /* FDPIC support. */
16883 if (local_fdpic_cnts->gotofffuncdesc_cnt > 0)
16884 {
16885 if (local_fdpic_cnts->funcdesc_offset == -1)
16886 {
16887 local_fdpic_cnts->funcdesc_offset = s->size;
16888 s->size += 8;
16889
16890 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16891 if (bfd_link_pic(info))
16892 elf32_arm_allocate_dynrelocs (info, srel, 1);
16893 else
16894 htab->srofixup->size += 8;
16895 }
16896 }
16897
16898 if (local_fdpic_cnts->funcdesc_cnt > 0)
16899 {
16900 if (local_fdpic_cnts->funcdesc_offset == -1)
16901 {
16902 local_fdpic_cnts->funcdesc_offset = s->size;
16903 s->size += 8;
16904
16905 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16906 if (bfd_link_pic(info))
16907 elf32_arm_allocate_dynrelocs (info, srel, 1);
16908 else
16909 htab->srofixup->size += 8;
16910 }
16911
16912 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16913 if (bfd_link_pic(info))
16914 elf32_arm_allocate_dynrelocs (info, srel, local_fdpic_cnts->funcdesc_cnt);
16915 else
16916 htab->srofixup->size += 4 * local_fdpic_cnts->funcdesc_cnt;
16917 }
16918
34e77a92
RS		 16919 if (local_iplt != NULL)
16920 {
16921 struct elf_dyn_relocs *p;
16922
16923 if (local_iplt->root.refcount > 0)
16924 {
16925 elf32_arm_allocate_plt_entry (info, TRUE,
16926 &local_iplt->root,
16927 &local_iplt->arm);
16928 if (local_iplt->arm.noncall_refcount == 0)
16929 /* All references to the PLT are calls, so all
16930 non-call references can resolve directly to the
16931 run-time target. This means that the .got entry
16932 would be the same as the .igot.plt entry, so there's
16933 no point creating both. */
16934 *local_got = 0;
16935 }
16936 else
16937 {
16938 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
16939 local_iplt->root.offset = (bfd_vma) -1;
16940 }
16941
16942 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
16943 {
16944 asection *psrel;
16945
16946 psrel = elf_section_data (p->sec)->sreloc;
16947 if (local_iplt->arm.noncall_refcount == 0)
16948 elf32_arm_allocate_irelocs (info, psrel, p->count);
16949 else
16950 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
16951 }
16952 }
5e681ec4
PB		 16953 if (*local_got > 0)
16954 {
34e77a92
RS		 16955 Elf_Internal_Sym *isym;
16956
eea6121a 16957 *local_got = s->size;
ba93b8ac
DJ		 16958 if (*local_tls_type & GOT_TLS_GD)
16959 /* TLS_GD relocs need an 8-byte structure in the GOT. */
16960 s->size += 8;
0855e32b
NS		 16961 if (*local_tls_type & GOT_TLS_GDESC)
16962 {
16963 *local_tlsdesc_gotent = htab->root.sgotplt->size
16964 - elf32_arm_compute_jump_table_size (htab);
16965 htab->root.sgotplt->size += 8;
16966 *local_got = (bfd_vma) -2;
34e77a92 16967 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 16968 reloc in the middle of .got.plt. */
99059e56 16969 htab->num_tls_desc++;
0855e32b 16970 }
ba93b8ac
DJ		 16971 if (*local_tls_type & GOT_TLS_IE)
16972 s->size += 4;
ba93b8ac 16973
0855e32b
NS		 16974 if (*local_tls_type & GOT_NORMAL)
16975 {
16976 /* If the symbol is both GD and GDESC, *local_got
16977 may have been overwritten. */
16978 *local_got = s->size;
16979 s->size += 4;
16980 }
16981
34e77a92
RS		 16982 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
16983 if (isym == NULL)
16984 return FALSE;
16985
16986 /* If all references to an STT_GNU_IFUNC PLT are calls,
16987 then all non-call references, including this GOT entry,
16988 resolve directly to the run-time target. */
16989 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
16990 && (local_iplt == NULL
16991 || local_iplt->arm.noncall_refcount == 0))
16992 elf32_arm_allocate_irelocs (info, srel, 1);
e8b09b87 16993 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC || htab->fdpic_p)
0855e32b 16994 {
e8b09b87 16995 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC)))
3064e1ff 16996 elf32_arm_allocate_dynrelocs (info, srel, 1);
e8b09b87
CL		 16997 else if (htab->fdpic_p && *local_tls_type & GOT_NORMAL)
16998 htab->srofixup->size += 4;
99059e56 16999
e8b09b87
CL		 17000 if ((bfd_link_pic (info) || htab->fdpic_p)
17001 && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 17002 {
17003 elf32_arm_allocate_dynrelocs (info,
17004 htab->root.srelplt, 1);
17005 htab->tls_trampoline = -1;
17006 }
0855e32b 17007 }
5e681ec4
PB		 17008 }
17009 else
17010 *local_got = (bfd_vma) -1;
17011 }
252b5132
RH		 17012 }
17013
ba93b8ac
DJ		 17014 if (htab->tls_ldm_got.refcount > 0)
17015 {
17016 /* Allocate two GOT entries and one dynamic relocation (if necessary)
5c5a4843 17017 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
362d30a1
RS		 17018 htab->tls_ldm_got.offset = htab->root.sgot->size;
17019 htab->root.sgot->size += 8;
0e1862bb 17020 if (bfd_link_pic (info))
47beaa6a 17021 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 17022 }
17023 else
17024 htab->tls_ldm_got.offset = -1;
17025
e8b09b87
CL		 17026 /* At the very end of the .rofixup section is a pointer to the GOT,
17027 reserve space for it. */
17028 if (htab->fdpic_p && htab->srofixup != NULL)
17029 htab->srofixup->size += 4;
17030
5e681ec4
PB		 17031 /* Allocate global sym .plt and .got entries, and space for global
17032 sym dynamic relocs. */
47beaa6a 17033 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 17034
d504ffc8 17035 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 17036 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 17037 {
0ffa91dd 17038 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 17039 continue;
17040
c7b8f16e
JB		 17041 /* Initialise mapping tables for code/data. */
17042 bfd_elf32_arm_init_maps (ibfd);
906e58ca 17043
c7b8f16e 17044 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 17045 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
17046 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
90b6238f 17047 _bfd_error_handler (_("errors encountered processing file %pB"), ibfd);
c7b8f16e 17048 }
d504ffc8 17049
3e6b1042
DJ		 17050 /* Allocate space for the glue sections now that we've sized them. */
17051 bfd_elf32_arm_allocate_interworking_sections (info);
17052
0855e32b
NS		 17053 /* For every jump slot reserved in the sgotplt, reloc_count is
17054 incremented. However, when we reserve space for TLS descriptors,
17055 it's not incremented, so in order to compute the space reserved
17056 for them, it suffices to multiply the reloc count by the jump
17057 slot size. */
17058 if (htab->root.srelplt)
17059 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
17060
17061 if (htab->tls_trampoline)
17062 {
17063 if (htab->root.splt->size == 0)
17064 htab->root.splt->size += htab->plt_header_size;
b38cadfb 17065
0855e32b
NS		 17066 htab->tls_trampoline = htab->root.splt->size;
17067 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 17068
0855e32b 17069 /* If we're not using lazy TLS relocations, don't generate the
99059e56 17070 PLT and GOT entries they require. */
0855e32b
NS		 17071 if (!(info->flags & DF_BIND_NOW))
17072 {
17073 htab->dt_tlsdesc_got = htab->root.sgot->size;
17074 htab->root.sgot->size += 4;
17075
17076 htab->dt_tlsdesc_plt = htab->root.splt->size;
17077 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
17078 }
17079 }
17080
252b5132
RH		 17081 /* The check_relocs and adjust_dynamic_symbol entry points have
17082 determined the sizes of the various dynamic sections. Allocate
17083 memory for them. */
b34976b6
AM		 17084 plt = FALSE;
17085 relocs = FALSE;
252b5132
RH		 17086 for (s = dynobj->sections; s != NULL; s = s->next)
17087 {
17088 const char * name;
252b5132
RH		 17089
17090 if ((s->flags & SEC_LINKER_CREATED) == 0)
17091 continue;
17092
17093 /* It's OK to base decisions on the section name, because none
17094 of the dynobj section names depend upon the input files. */
fd361982 17095 name = bfd_section_name (s);
252b5132 17096
34e77a92 17097 if (s == htab->root.splt)
252b5132 17098 {
c456f082
AM		 17099 /* Remember whether there is a PLT. */
17100 plt = s->size != 0;
252b5132 17101 }
0112cd26 17102 else if (CONST_STRNEQ (name, ".rel"))
252b5132 17103 {
c456f082 17104 if (s->size != 0)
252b5132 17105 {
252b5132 17106 /* Remember whether there are any reloc sections other
00a97672 17107 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 17108 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 17109 relocs = TRUE;
252b5132
RH		 17110
17111 /* We use the reloc_count field as a counter if we need
17112 to copy relocs into the output file. */
17113 s->reloc_count = 0;
17114 }
17115 }
34e77a92
RS		 17116 else if (s != htab->root.sgot
17117 && s != htab->root.sgotplt
17118 && s != htab->root.iplt
17119 && s != htab->root.igotplt
5474d94f 17120 && s != htab->root.sdynbss
e8b09b87
CL		 17121 && s != htab->root.sdynrelro
17122 && s != htab->srofixup)
252b5132
RH		 17123 {
17124 /* It's not one of our sections, so don't allocate space. */
17125 continue;
17126 }
17127
c456f082 17128 if (s->size == 0)
252b5132 17129 {
c456f082 17130 /* If we don't need this section, strip it from the
00a97672
RS		 17131 output file. This is mostly to handle .rel(a).bss and
17132 .rel(a).plt. We must create both sections in
c456f082
AM		 17133 create_dynamic_sections, because they must be created
17134 before the linker maps input sections to output
17135 sections. The linker does that before
17136 adjust_dynamic_symbol is called, and it is that
17137 function which decides whether anything needs to go
17138 into these sections. */
8423293d 17139 s->flags |= SEC_EXCLUDE;
252b5132
RH		 17140 continue;
17141 }
17142
c456f082
AM		 17143 if ((s->flags & SEC_HAS_CONTENTS) == 0)
17144 continue;
17145
252b5132 17146 /* Allocate memory for the section contents. */
21d799b5 17147 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 17148 if (s->contents == NULL)
b34976b6 17149 return FALSE;
252b5132
RH		 17150 }
17151
17152 if (elf_hash_table (info)->dynamic_sections_created)
17153 {
17154 /* Add some entries to the .dynamic section. We fill in the
17155 values later, in elf32_arm_finish_dynamic_sections, but we
17156 must add the entries now so that we get the correct size for
17157 the .dynamic section. The DT_DEBUG entry is filled in by the
17158 dynamic linker and used by the debugger. */
dc810e39 17159#define add_dynamic_entry(TAG, VAL) \
5a580b3a 17160 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 17161
0e1862bb 17162 if (bfd_link_executable (info))
252b5132 17163 {
dc810e39 17164 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 17165 return FALSE;
252b5132
RH		 17166 }
17167
17168 if (plt)
17169 {
dc810e39
AM		 17170 if ( !add_dynamic_entry (DT_PLTGOT, 0)
17171 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 17172 || !add_dynamic_entry (DT_PLTREL,
17173 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 17174 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 17175 return FALSE;
0855e32b 17176
5025eb7c
AO		 17177 if (htab->dt_tlsdesc_plt
17178 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
17179 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 17180 return FALSE;
252b5132
RH		 17181 }
17182
17183 if (relocs)
17184 {
00a97672
RS		 17185 if (htab->use_rel)
17186 {
17187 if (!add_dynamic_entry (DT_REL, 0)
17188 || !add_dynamic_entry (DT_RELSZ, 0)
17189 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
17190 return FALSE;
17191 }
17192 else
17193 {
17194 if (!add_dynamic_entry (DT_RELA, 0)
17195 || !add_dynamic_entry (DT_RELASZ, 0)
17196 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
17197 return FALSE;
17198 }
252b5132
RH		 17199 }
17200
08d1f311
DJ		 17201 /* If any dynamic relocs apply to a read-only section,
17202 then we need a DT_TEXTREL entry. */
17203 if ((info->flags & DF_TEXTREL) == 0)
63c1f59d 17204 elf_link_hash_traverse (&htab->root, maybe_set_textrel, info);
08d1f311 17205
99e4ae17 17206 if ((info->flags & DF_TEXTREL) != 0)
252b5132 17207 {
dc810e39 17208 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 17209 return FALSE;
252b5132 17210 }
7a2b07ff
NS		 17211 if (htab->vxworks_p
17212 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
17213 return FALSE;
252b5132 17214 }
8532796c 17215#undef add_dynamic_entry
252b5132 17216
b34976b6 17217 return TRUE;
252b5132
RH		 17218}
17219
0855e32b
NS		 17220/* Size sections even though they're not dynamic. We use it to setup
17221 _TLS_MODULE_BASE_, if needed. */
17222
17223static bfd_boolean
17224elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 17225 struct bfd_link_info *info)
0855e32b
NS		 17226{
17227 asection *tls_sec;
cb10292c
CL		 17228 struct elf32_arm_link_hash_table *htab;
17229
17230 htab = elf32_arm_hash_table (info);
0855e32b 17231
0e1862bb 17232 if (bfd_link_relocatable (info))
0855e32b
NS		 17233 return TRUE;
17234
17235 tls_sec = elf_hash_table (info)->tls_sec;
17236
17237 if (tls_sec)
17238 {
17239 struct elf_link_hash_entry *tlsbase;
17240
17241 tlsbase = elf_link_hash_lookup
17242 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
17243
17244 if (tlsbase)
99059e56
RM		 17245 {
17246 struct bfd_link_hash_entry *bh = NULL;
0855e32b 17247 const struct elf_backend_data *bed
99059e56 17248 = get_elf_backend_data (output_bfd);
0855e32b 17249
99059e56 17250 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 17251 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
17252 tls_sec, 0, NULL, FALSE,
17253 bed->collect, &bh)))
17254 return FALSE;
b38cadfb 17255
99059e56
RM		 17256 tlsbase->type = STT_TLS;
17257 tlsbase = (struct elf_link_hash_entry *)bh;
17258 tlsbase->def_regular = 1;
17259 tlsbase->other = STV_HIDDEN;
17260 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 17261 }
17262 }
cb10292c
CL		 17263
17264 if (htab->fdpic_p && !bfd_link_relocatable (info)
17265 && !bfd_elf_stack_segment_size (output_bfd, info,
17266 "__stacksize", DEFAULT_STACK_SIZE))
17267 return FALSE;
17268
0855e32b
NS		 17269 return TRUE;
17270}
17271
252b5132
RH		 17272/* Finish up dynamic symbol handling. We set the contents of various
17273 dynamic sections here. */
17274
b34976b6 17275static bfd_boolean
906e58ca
NC		 17276elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
17277 struct bfd_link_info * info,
17278 struct elf_link_hash_entry * h,
17279 Elf_Internal_Sym * sym)
252b5132 17280{
e5a52504 17281 struct elf32_arm_link_hash_table *htab;
b7693d02 17282 struct elf32_arm_link_hash_entry *eh;
252b5132 17283
e5a52504 17284 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17285 if (htab == NULL)
17286 return FALSE;
17287
b7693d02 17288 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 17289
17290 if (h->plt.offset != (bfd_vma) -1)
17291 {
34e77a92 17292 if (!eh->is_iplt)
e5a52504 17293 {
34e77a92 17294 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 17295 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
17296 h->dynindx, 0))
17297 return FALSE;
e5a52504 17298 }
57e8b36a 17299
f5385ebf 17300 if (!h->def_regular)
252b5132
RH		 17301 {
17302 /* Mark the symbol as undefined, rather than as defined in
3a635617 17303 the .plt section. */
252b5132 17304 sym->st_shndx = SHN_UNDEF;
3a635617 17305 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 17306 Otherwise, the PLT entry would provide a definition for
17307 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 17308 and so the symbol would never be NULL. Leave the value if
17309 there were any relocations where pointer equality matters
17310 (this is a clue for the dynamic linker, to make function
17311 pointer comparisons work between an application and shared
17312 library). */
97323ad1 17313 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 17314 sym->st_value = 0;
252b5132 17315 }
34e77a92
RS		 17316 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
17317 {
17318 /* At least one non-call relocation references this .iplt entry,
17319 so the .iplt entry is the function's canonical address. */
17320 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 17321 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 17322 sym->st_shndx = (_bfd_elf_section_from_bfd_section
17323 (output_bfd, htab->root.iplt->output_section));
17324 sym->st_value = (h->plt.offset
17325 + htab->root.iplt->output_section->vma
17326 + htab->root.iplt->output_offset);
17327 }
252b5132
RH		 17328 }
17329
f5385ebf 17330 if (h->needs_copy)
252b5132
RH		 17331 {
17332 asection * s;
947216bf 17333 Elf_Internal_Rela rel;
252b5132
RH		 17334
17335 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 17336 BFD_ASSERT (h->dynindx != -1
17337 && (h->root.type == bfd_link_hash_defined
17338 || h->root.type == bfd_link_hash_defweak));
17339
00a97672 17340 rel.r_addend = 0;
252b5132
RH		 17341 rel.r_offset = (h->root.u.def.value
17342 + h->root.u.def.section->output_section->vma
17343 + h->root.u.def.section->output_offset);
17344 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 17345 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 17346 s = htab->root.sreldynrelro;
17347 else
17348 s = htab->root.srelbss;
47beaa6a 17349 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 17350 }
17351
00a97672 17352 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
fac7bd64
CL		 17353 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17354 it is relative to the ".got" section. */
9637f6ef 17355 if (h == htab->root.hdynamic
fac7bd64 17356 || (!htab->fdpic_p && !htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 17357 sym->st_shndx = SHN_ABS;
17358
b34976b6 17359 return TRUE;
252b5132
RH		 17360}
17361
0855e32b
NS		 17362static void
17363arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17364 void *contents,
17365 const unsigned long *template, unsigned count)
17366{
17367 unsigned ix;
b38cadfb 17368
0855e32b
NS		 17369 for (ix = 0; ix != count; ix++)
17370 {
17371 unsigned long insn = template[ix];
17372
17373 /* Emit mov pc,rx if bx is not permitted. */
17374 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
17375 insn = (insn & 0xf000000f) | 0x01a0f000;
17376 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
17377 }
17378}
17379
99059e56
RM		 17380/* Install the special first PLT entry for elf32-arm-nacl. Unlike
17381 other variants, NaCl needs this entry in a static executable's
17382 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17383 zero. For .iplt really only the last bundle is useful, and .iplt
17384 could have a shorter first entry, with each individual PLT entry's
17385 relative branch calculated differently so it targets the last
17386 bundle instead of the instruction before it (labelled .Lplt_tail
17387 above). But it's simpler to keep the size and layout of PLT0
17388 consistent with the dynamic case, at the cost of some dead code at
17389 the start of .iplt and the one dead store to the stack at the start
17390 of .Lplt_tail. */
17391static void
17392arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17393 asection *plt, bfd_vma got_displacement)
17394{
17395 unsigned int i;
17396
17397 put_arm_insn (htab, output_bfd,
17398 elf32_arm_nacl_plt0_entry[0]
17399 | arm_movw_immediate (got_displacement),
17400 plt->contents + 0);
17401 put_arm_insn (htab, output_bfd,
17402 elf32_arm_nacl_plt0_entry[1]
17403 | arm_movt_immediate (got_displacement),
17404 plt->contents + 4);
17405
17406 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
17407 put_arm_insn (htab, output_bfd,
17408 elf32_arm_nacl_plt0_entry[i],
17409 plt->contents + (i * 4));
17410}
17411
252b5132
RH		 17412/* Finish up the dynamic sections. */
17413
b34976b6 17414static bfd_boolean
57e8b36a 17415elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 17416{
17417 bfd * dynobj;
17418 asection * sgot;
17419 asection * sdyn;
4dfe6ac6
NC		 17420 struct elf32_arm_link_hash_table *htab;
17421
17422 htab = elf32_arm_hash_table (info);
17423 if (htab == NULL)
17424 return FALSE;
252b5132
RH		 17425
17426 dynobj = elf_hash_table (info)->dynobj;
17427
362d30a1 17428 sgot = htab->root.sgotplt;
894891db
NC		 17429 /* A broken linker script might have discarded the dynamic sections.
17430 Catch this here so that we do not seg-fault later on. */
17431 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
17432 return FALSE;
3d4d4302 17433 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 17434
17435 if (elf_hash_table (info)->dynamic_sections_created)
17436 {
17437 asection *splt;
17438 Elf32_External_Dyn *dyncon, *dynconend;
17439
362d30a1 17440 splt = htab->root.splt;
24a1ba0f 17441 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 17442 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 17443
17444 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 17445 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 17446
252b5132
RH		 17447 for (; dyncon < dynconend; dyncon++)
17448 {
17449 Elf_Internal_Dyn dyn;
17450 const char * name;
17451 asection * s;
17452
17453 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
17454
17455 switch (dyn.d_tag)
17456 {
229fcec5
MM		 17457 unsigned int type;
17458
252b5132 17459 default:
7a2b07ff
NS		 17460 if (htab->vxworks_p
17461 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
17462 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 17463 break;
17464
229fcec5
MM		 17465 case DT_HASH:
17466 name = ".hash";
17467 goto get_vma_if_bpabi;
17468 case DT_STRTAB:
17469 name = ".dynstr";
17470 goto get_vma_if_bpabi;
17471 case DT_SYMTAB:
17472 name = ".dynsym";
17473 goto get_vma_if_bpabi;
c0042f5d
MM		 17474 case DT_VERSYM:
17475 name = ".gnu.version";
17476 goto get_vma_if_bpabi;
17477 case DT_VERDEF:
17478 name = ".gnu.version_d";
17479 goto get_vma_if_bpabi;
17480 case DT_VERNEED:
17481 name = ".gnu.version_r";
17482 goto get_vma_if_bpabi;
17483
252b5132 17484 case DT_PLTGOT:
4ade44b7 17485 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 17486 goto get_vma;
17487 case DT_JMPREL:
00a97672 17488 name = RELOC_SECTION (htab, ".plt");
252b5132 17489 get_vma:
4ade44b7 17490 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 17491 if (s == NULL)
17492 {
4eca0228 17493 _bfd_error_handler
4ade44b7 17494 (_("could not find section %s"), name);
05456594
NC		 17495 bfd_set_error (bfd_error_invalid_operation);
17496 return FALSE;
17497 }
229fcec5 17498 if (!htab->symbian_p)
4ade44b7 17499 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 17500 else
17501 /* In the BPABI, tags in the PT_DYNAMIC section point
17502 at the file offset, not the memory address, for the
17503 convenience of the post linker. */
4ade44b7 17504 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 17505 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17506 break;
17507
229fcec5
MM		 17508 get_vma_if_bpabi:
17509 if (htab->symbian_p)
17510 goto get_vma;
17511 break;
17512
252b5132 17513 case DT_PLTRELSZ:
362d30a1 17514 s = htab->root.srelplt;
252b5132 17515 BFD_ASSERT (s != NULL);
eea6121a 17516 dyn.d_un.d_val = s->size;
252b5132
RH		 17517 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17518 break;
906e58ca 17519
252b5132 17520 case DT_RELSZ:
00a97672 17521 case DT_RELASZ:
229fcec5
MM		 17522 case DT_REL:
17523 case DT_RELA:
229fcec5
MM		 17524 /* In the BPABI, the DT_REL tag must point at the file
17525 offset, not the VMA, of the first relocation
17526 section. So, we use code similar to that in
17527 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 17528 relocation section, since relocation sections are
17529 never allocated under the BPABI. PLT relocs are also
17530 included. */
229fcec5
MM		 17531 if (htab->symbian_p)
17532 {
17533 unsigned int i;
17534 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
17535 ? SHT_REL : SHT_RELA);
17536 dyn.d_un.d_val = 0;
17537 for (i = 1; i < elf_numsections (output_bfd); i++)
17538 {
906e58ca 17539 Elf_Internal_Shdr *hdr
229fcec5
MM		 17540 = elf_elfsections (output_bfd)[i];
17541 if (hdr->sh_type == type)
17542 {
906e58ca 17543 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 17544 || dyn.d_tag == DT_RELASZ)
17545 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 17546 else if ((ufile_ptr) hdr->sh_offset
17547 <= dyn.d_un.d_val - 1)
229fcec5
MM		 17548 dyn.d_un.d_val = hdr->sh_offset;
17549 }
17550 }
17551 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17552 }
252b5132 17553 break;
88f7bcd5 17554
0855e32b 17555 case DT_TLSDESC_PLT:
99059e56 17556 s = htab->root.splt;
0855e32b
NS		 17557 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
17558 + htab->dt_tlsdesc_plt);
17559 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17560 break;
17561
17562 case DT_TLSDESC_GOT:
99059e56 17563 s = htab->root.sgot;
0855e32b 17564 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 17565 + htab->dt_tlsdesc_got);
0855e32b
NS		 17566 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17567 break;
17568
88f7bcd5
NC		 17569 /* Set the bottom bit of DT_INIT/FINI if the
17570 corresponding function is Thumb. */
17571 case DT_INIT:
17572 name = info->init_function;
17573 goto get_sym;
17574 case DT_FINI:
17575 name = info->fini_function;
17576 get_sym:
17577 /* If it wasn't set by elf_bfd_final_link
4cc11e76 17578 then there is nothing to adjust. */
88f7bcd5
NC		 17579 if (dyn.d_un.d_val != 0)
17580 {
17581 struct elf_link_hash_entry * eh;
17582
17583 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 17584 FALSE, FALSE, TRUE);
39d911fc
TP		 17585 if (eh != NULL
17586 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
17587 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 17588 {
17589 dyn.d_un.d_val |= 1;
b34976b6 17590 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 17591 }
17592 }
17593 break;
252b5132
RH		 17594 }
17595 }
17596
24a1ba0f 17597 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 17598 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 17599 {
00a97672
RS		 17600 const bfd_vma *plt0_entry;
17601 bfd_vma got_address, plt_address, got_displacement;
17602
17603 /* Calculate the addresses of the GOT and PLT. */
17604 got_address = sgot->output_section->vma + sgot->output_offset;
17605 plt_address = splt->output_section->vma + splt->output_offset;
17606
17607 if (htab->vxworks_p)
17608 {
17609 /* The VxWorks GOT is relocated by the dynamic linker.
17610 Therefore, we must emit relocations rather than simply
17611 computing the values now. */
17612 Elf_Internal_Rela rel;
17613
17614 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 17615 put_arm_insn (htab, output_bfd, plt0_entry[0],
17616 splt->contents + 0);
17617 put_arm_insn (htab, output_bfd, plt0_entry[1],
17618 splt->contents + 4);
17619 put_arm_insn (htab, output_bfd, plt0_entry[2],
17620 splt->contents + 8);
00a97672
RS		 17621 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
17622
8029a119 17623 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 17624 rel.r_offset = plt_address + 12;
17625 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17626 rel.r_addend = 0;
17627 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
17628 htab->srelplt2->contents);
17629 }
b38cadfb 17630 else if (htab->nacl_p)
99059e56
RM		 17631 arm_nacl_put_plt0 (htab, output_bfd, splt,
17632 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 17633 else if (using_thumb_only (htab))
17634 {
17635 got_displacement = got_address - (plt_address + 12);
17636
17637 plt0_entry = elf32_thumb2_plt0_entry;
17638 put_arm_insn (htab, output_bfd, plt0_entry[0],
17639 splt->contents + 0);
17640 put_arm_insn (htab, output_bfd, plt0_entry[1],
17641 splt->contents + 4);
17642 put_arm_insn (htab, output_bfd, plt0_entry[2],
17643 splt->contents + 8);
17644
17645 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
17646 }
00a97672
RS		 17647 else
17648 {
17649 got_displacement = got_address - (plt_address + 16);
17650
17651 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 17652 put_arm_insn (htab, output_bfd, plt0_entry[0],
17653 splt->contents + 0);
17654 put_arm_insn (htab, output_bfd, plt0_entry[1],
17655 splt->contents + 4);
17656 put_arm_insn (htab, output_bfd, plt0_entry[2],
17657 splt->contents + 8);
17658 put_arm_insn (htab, output_bfd, plt0_entry[3],
17659 splt->contents + 12);
5e681ec4 17660
5e681ec4 17661#ifdef FOUR_WORD_PLT
00a97672
RS		 17662 /* The displacement value goes in the otherwise-unused
17663 last word of the second entry. */
17664 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 17665#else
00a97672 17666 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 17667#endif
00a97672 17668 }
f7a74f8c 17669 }
252b5132
RH		 17670
17671 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17672 really seem like the right value. */
74541ad4
AM		 17673 if (splt->output_section->owner == output_bfd)
17674 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 17675
0855e32b
NS		 17676 if (htab->dt_tlsdesc_plt)
17677 {
17678 bfd_vma got_address
17679 = sgot->output_section->vma + sgot->output_offset;
17680 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
17681 + htab->root.sgot->output_offset);
17682 bfd_vma plt_address
17683 = splt->output_section->vma + splt->output_offset;
17684
b38cadfb 17685 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17686 splt->contents + htab->dt_tlsdesc_plt,
17687 dl_tlsdesc_lazy_trampoline, 6);
17688
17689 bfd_put_32 (output_bfd,
17690 gotplt_address + htab->dt_tlsdesc_got
17691 - (plt_address + htab->dt_tlsdesc_plt)
17692 - dl_tlsdesc_lazy_trampoline[6],
17693 splt->contents + htab->dt_tlsdesc_plt + 24);
17694 bfd_put_32 (output_bfd,
17695 got_address - (plt_address + htab->dt_tlsdesc_plt)
17696 - dl_tlsdesc_lazy_trampoline[7],
17697 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
17698 }
17699
17700 if (htab->tls_trampoline)
17701 {
b38cadfb 17702 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 17703 splt->contents + htab->tls_trampoline,
17704 tls_trampoline, 3);
17705#ifdef FOUR_WORD_PLT
17706 bfd_put_32 (output_bfd, 0x00000000,
17707 splt->contents + htab->tls_trampoline + 12);
b38cadfb 17708#endif
0855e32b
NS		 17709 }
17710
0e1862bb
L		 17711 if (htab->vxworks_p
17712 && !bfd_link_pic (info)
17713 && htab->root.splt->size > 0)
00a97672
RS		 17714 {
17715 /* Correct the .rel(a).plt.unloaded relocations. They will have
17716 incorrect symbol indexes. */
17717 int num_plts;
eed62c48 17718 unsigned char *p;
00a97672 17719
362d30a1 17720 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 17721 / htab->plt_entry_size);
17722 p = htab->srelplt2->contents + RELOC_SIZE (htab);
17723
17724 for (; num_plts; num_plts--)
17725 {
17726 Elf_Internal_Rela rel;
17727
17728 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17729 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17730 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17731 p += RELOC_SIZE (htab);
17732
17733 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17734 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
17735 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17736 p += RELOC_SIZE (htab);
17737 }
17738 }
252b5132
RH		 17739 }
17740
99059e56
RM		 17741 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
17742 /* NaCl uses a special first entry in .iplt too. */
17743 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
17744
252b5132 17745 /* Fill in the first three entries in the global offset table. */
229fcec5 17746 if (sgot)
252b5132 17747 {
229fcec5
MM		 17748 if (sgot->size > 0)
17749 {
17750 if (sdyn == NULL)
17751 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
17752 else
17753 bfd_put_32 (output_bfd,
17754 sdyn->output_section->vma + sdyn->output_offset,
17755 sgot->contents);
17756 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
17757 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
17758 }
252b5132 17759
229fcec5
MM		 17760 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
17761 }
252b5132 17762
e8b09b87
CL		 17763 /* At the very end of the .rofixup section is a pointer to the GOT. */
17764 if (htab->fdpic_p && htab->srofixup != NULL)
17765 {
17766 struct elf_link_hash_entry *hgot = htab->root.hgot;
17767
17768 bfd_vma got_value = hgot->root.u.def.value
17769 + hgot->root.u.def.section->output_section->vma
17770 + hgot->root.u.def.section->output_offset;
17771
17772 arm_elf_add_rofixup(output_bfd, htab->srofixup, got_value);
17773
17774 /* Make sure we allocated and generated the same number of fixups. */
17775 BFD_ASSERT (htab->srofixup->reloc_count * 4 == htab->srofixup->size);
17776 }
17777
b34976b6 17778 return TRUE;
252b5132
RH		 17779}
17780
ed7e9d0b
AM		 17781static bfd_boolean
17782elf32_arm_init_file_header (bfd *abfd, struct bfd_link_info *link_info)
ba96a88f 17783{
9b485d32 17784 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 17785 struct elf32_arm_link_hash_table *globals;
ac4c9b04 17786 struct elf_segment_map *m;
ba96a88f 17787
ed7e9d0b
AM		 17788 if (!_bfd_elf_init_file_header (abfd, link_info))
17789 return FALSE;
17790
ba96a88f
NC		 17791 i_ehdrp = elf_elfheader (abfd);
17792
94a3258f
PB		 17793 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
17794 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
ba96a88f 17795 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 17796
93204d3a
PB		 17797 if (link_info)
17798 {
17799 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 17800 if (globals != NULL && globals->byteswap_code)
93204d3a 17801 i_ehdrp->e_flags |= EF_ARM_BE8;
18a20338
CL		 17802
17803 if (globals->fdpic_p)
17804 i_ehdrp->e_ident[EI_OSABI] |= ELFOSABI_ARM_FDPIC;
93204d3a 17805 }
3bfcb652
NC		 17806
17807 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
17808 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
17809 {
17810 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 17811 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 17812 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
17813 else
17814 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
17815 }
ac4c9b04
MG		 17816
17817 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 17818 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 17819 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
17820 {
17821 unsigned int j;
17822
17823 if (m->count == 0)
17824 continue;
17825 for (j = 0; j < m->count; j++)
17826 {
f0728ee3 17827 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 17828 break;
17829 }
17830 if (j == m->count)
17831 {
17832 m->p_flags = PF_X;
17833 m->p_flags_valid = 1;
17834 }
17835 }
ed7e9d0b 17836 return TRUE;
ba96a88f
NC		 17837}
17838
99e4ae17 17839static enum elf_reloc_type_class
7e612e98
AM		 17840elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
17841 const asection *rel_sec ATTRIBUTE_UNUSED,
17842 const Elf_Internal_Rela *rela)
99e4ae17 17843{
f51e552e 17844 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 17845 {
17846 case R_ARM_RELATIVE:
17847 return reloc_class_relative;
17848 case R_ARM_JUMP_SLOT:
17849 return reloc_class_plt;
17850 case R_ARM_COPY:
17851 return reloc_class_copy;
109575d7
JW		 17852 case R_ARM_IRELATIVE:
17853 return reloc_class_ifunc;
99e4ae17
AJ		 17854 default:
17855 return reloc_class_normal;
17856 }
17857}
17858
e489d0ae 17859static void
cc364be6 17860arm_final_write_processing (bfd *abfd)
e16bb312 17861{
5a6c6817 17862 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 17863}
17864
cc364be6
AM		 17865static bfd_boolean
17866elf32_arm_final_write_processing (bfd *abfd)
06f44071 17867{
cc364be6
AM		 17868 arm_final_write_processing (abfd);
17869 return _bfd_elf_final_write_processing (abfd);
06f44071
AM		 17870}
17871
40a18ebd
NC		 17872/* Return TRUE if this is an unwinding table entry. */
17873
17874static bfd_boolean
17875is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
17876{
0112cd26
NC		 17877 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
17878 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 17879}
17880
17881
17882/* Set the type and flags for an ARM section. We do this by
17883 the section name, which is a hack, but ought to work. */
17884
17885static bfd_boolean
17886elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
17887{
17888 const char * name;
17889
fd361982 17890 name = bfd_section_name (sec);
40a18ebd
NC		 17891
17892 if (is_arm_elf_unwind_section_name (abfd, name))
17893 {
17894 hdr->sh_type = SHT_ARM_EXIDX;
17895 hdr->sh_flags |= SHF_LINK_ORDER;
17896 }
ac4c9b04 17897
f0728ee3
AV		 17898 if (sec->flags & SEC_ELF_PURECODE)
17899 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 17900
40a18ebd
NC		 17901 return TRUE;
17902}
17903
6dc132d9
L		 17904/* Handle an ARM specific section when reading an object file. This is
17905 called when bfd_section_from_shdr finds a section with an unknown
17906 type. */
40a18ebd
NC		 17907
17908static bfd_boolean
17909elf32_arm_section_from_shdr (bfd *abfd,
17910 Elf_Internal_Shdr * hdr,
6dc132d9
L		 17911 const char *name,
17912 int shindex)
40a18ebd
NC		 17913{
17914 /* There ought to be a place to keep ELF backend specific flags, but
17915 at the moment there isn't one. We just keep track of the
17916 sections by their name, instead. Fortunately, the ABI gives
17917 names for all the ARM specific sections, so we will probably get
17918 away with this. */
17919 switch (hdr->sh_type)
17920 {
17921 case SHT_ARM_EXIDX:
0951f019
RE		 17922 case SHT_ARM_PREEMPTMAP:
17923 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 17924 break;
17925
17926 default:
17927 return FALSE;
17928 }
17929
6dc132d9 17930 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 17931 return FALSE;
17932
17933 return TRUE;
17934}
e489d0ae 17935
44444f50
NC		 17936static _arm_elf_section_data *
17937get_arm_elf_section_data (asection * sec)
17938{
47b2e99c
JZ		 17939 if (sec && sec->owner && is_arm_elf (sec->owner))
17940 return elf32_arm_section_data (sec);
44444f50
NC		 17941 else
17942 return NULL;
8e3de13a
NC		 17943}
17944
4e617b1e
PB		 17945typedef struct
17946{
57402f1e 17947 void *flaginfo;
4e617b1e 17948 struct bfd_link_info *info;
91a5743d
PB		 17949 asection *sec;
17950 int sec_shndx;
6e0b88f1
AM		 17951 int (*func) (void *, const char *, Elf_Internal_Sym *,
17952 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 17953} output_arch_syminfo;
17954
17955enum map_symbol_type
17956{
17957 ARM_MAP_ARM,
17958 ARM_MAP_THUMB,
17959 ARM_MAP_DATA
17960};
17961
17962
7413f23f 17963/* Output a single mapping symbol. */
4e617b1e
PB		 17964
17965static bfd_boolean
7413f23f
DJ		 17966elf32_arm_output_map_sym (output_arch_syminfo *osi,
17967 enum map_symbol_type type,
17968 bfd_vma offset)
4e617b1e
PB		 17969{
17970 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 17971 Elf_Internal_Sym sym;
17972
91a5743d
PB		 17973 sym.st_value = osi->sec->output_section->vma
17974 + osi->sec->output_offset
17975 + offset;
4e617b1e
PB		 17976 sym.st_size = 0;
17977 sym.st_other = 0;
17978 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 17979 sym.st_shndx = osi->sec_shndx;
35fc36a8 17980 sym.st_target_internal = 0;
fe33d2fa 17981 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 17982 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 17983}
17984
34e77a92
RS		 17985/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
17986 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 17987
17988static bfd_boolean
34e77a92
RS		 17989elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
17990 bfd_boolean is_iplt_entry_p,
17991 union gotplt_union *root_plt,
17992 struct arm_plt_info *arm_plt)
4e617b1e 17993{
4e617b1e 17994 struct elf32_arm_link_hash_table *htab;
34e77a92 17995 bfd_vma addr, plt_header_size;
4e617b1e 17996
34e77a92 17997 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 17998 return TRUE;
17999
4dfe6ac6
NC		 18000 htab = elf32_arm_hash_table (osi->info);
18001 if (htab == NULL)
18002 return FALSE;
18003
34e77a92
RS		 18004 if (is_iplt_entry_p)
18005 {
18006 osi->sec = htab->root.iplt;
18007 plt_header_size = 0;
18008 }
18009 else
18010 {
18011 osi->sec = htab->root.splt;
18012 plt_header_size = htab->plt_header_size;
18013 }
18014 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
18015 (osi->info->output_bfd, osi->sec->output_section));
18016
18017 addr = root_plt->offset & -2;
4e617b1e
PB		 18018 if (htab->symbian_p)
18019 {
7413f23f 18020 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18021 return FALSE;
7413f23f 18022 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 18023 return FALSE;
18024 }
18025 else if (htab->vxworks_p)
18026 {
7413f23f 18027 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18028 return FALSE;
7413f23f 18029 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 18030 return FALSE;
7413f23f 18031 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 18032 return FALSE;
7413f23f 18033 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 18034 return FALSE;
18035 }
b38cadfb
NC		 18036 else if (htab->nacl_p)
18037 {
18038 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
18039 return FALSE;
18040 }
7801f98f
CL		 18041 else if (htab->fdpic_p)
18042 {
59029f57
CL		 18043 enum map_symbol_type type = using_thumb_only(htab)
18044 ? ARM_MAP_THUMB
18045 : ARM_MAP_ARM;
18046
7801f98f 18047 if (elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt))
4b24dd1a
AM		 18048 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
18049 return FALSE;
59029f57 18050 if (!elf32_arm_output_map_sym (osi, type, addr))
4b24dd1a 18051 return FALSE;
7801f98f 18052 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 16))
4b24dd1a 18053 return FALSE;
7801f98f 18054 if (htab->plt_entry_size == 4 * ARRAY_SIZE(elf32_arm_fdpic_plt_entry))
4b24dd1a
AM		 18055 if (!elf32_arm_output_map_sym (osi, type, addr + 24))
18056 return FALSE;
7801f98f 18057 }
eed94f8f
NC		 18058 else if (using_thumb_only (htab))
18059 {
18060 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
18061 return FALSE;
6a631e86 18062 }
4e617b1e
PB		 18063 else
18064 {
34e77a92 18065 bfd_boolean thumb_stub_p;
bd97cb95 18066
34e77a92
RS		 18067 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
18068 if (thumb_stub_p)
4e617b1e 18069 {
7413f23f 18070 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 18071 return FALSE;
18072 }
18073#ifdef FOUR_WORD_PLT
7413f23f 18074 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 18075 return FALSE;
7413f23f 18076 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 18077 return FALSE;
18078#else
906e58ca 18079 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 18080 so only need to output a mapping symbol for the first PLT entry and
18081 entries with thumb thunks. */
34e77a92 18082 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 18083 {
7413f23f 18084 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 18085 return FALSE;
18086 }
18087#endif
18088 }
18089
18090 return TRUE;
18091}
18092
34e77a92
RS		 18093/* Output mapping symbols for PLT entries associated with H. */
18094
18095static bfd_boolean
18096elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
18097{
18098 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
18099 struct elf32_arm_link_hash_entry *eh;
18100
18101 if (h->root.type == bfd_link_hash_indirect)
18102 return TRUE;
18103
18104 if (h->root.type == bfd_link_hash_warning)
18105 /* When warning symbols are created, they **replace** the "real"
18106 entry in the hash table, thus we never get to see the real
18107 symbol in a hash traversal. So look at it now. */
18108 h = (struct elf_link_hash_entry *) h->root.u.i.link;
18109
18110 eh = (struct elf32_arm_link_hash_entry *) h;
18111 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
18112 &h->plt, &eh->plt);
18113}
18114
4f4faa4d
TP		 18115/* Bind a veneered symbol to its veneer identified by its hash entry
18116 STUB_ENTRY. The veneered location thus loose its symbol. */
18117
18118static void
18119arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
18120{
18121 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
18122
18123 BFD_ASSERT (hash);
18124 hash->root.root.u.def.section = stub_entry->stub_sec;
18125 hash->root.root.u.def.value = stub_entry->stub_offset;
18126 hash->root.size = stub_entry->stub_size;
18127}
18128
7413f23f
DJ		 18129/* Output a single local symbol for a generated stub. */
18130
18131static bfd_boolean
18132elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
18133 bfd_vma offset, bfd_vma size)
18134{
7413f23f
DJ		 18135 Elf_Internal_Sym sym;
18136
7413f23f
DJ		 18137 sym.st_value = osi->sec->output_section->vma
18138 + osi->sec->output_offset
18139 + offset;
18140 sym.st_size = size;
18141 sym.st_other = 0;
18142 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
18143 sym.st_shndx = osi->sec_shndx;
35fc36a8 18144 sym.st_target_internal = 0;
57402f1e 18145 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 18146}
4e617b1e 18147
da5938a2 18148static bfd_boolean
8029a119
NC		 18149arm_map_one_stub (struct bfd_hash_entry * gen_entry,
18150 void * in_arg)
da5938a2
NC		 18151{
18152 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 18153 asection *stub_sec;
18154 bfd_vma addr;
7413f23f 18155 char *stub_name;
9a008db3 18156 output_arch_syminfo *osi;
d3ce72d0 18157 const insn_sequence *template_sequence;
461a49ca
DJ		 18158 enum stub_insn_type prev_type;
18159 int size;
18160 int i;
18161 enum map_symbol_type sym_type;
da5938a2
NC		 18162
18163 /* Massage our args to the form they really have. */
18164 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 18165 osi = (output_arch_syminfo *) in_arg;
da5938a2 18166
da5938a2
NC		 18167 stub_sec = stub_entry->stub_sec;
18168
18169 /* Ensure this stub is attached to the current section being
7413f23f 18170 processed. */
da5938a2
NC		 18171 if (stub_sec != osi->sec)
18172 return TRUE;
18173
7413f23f 18174 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 18175 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 18176
18177 if (arm_stub_sym_claimed (stub_entry->stub_type))
18178 arm_stub_claim_sym (stub_entry);
18179 else
7413f23f 18180 {
4f4faa4d
TP		 18181 stub_name = stub_entry->output_name;
18182 switch (template_sequence[0].type)
18183 {
18184 case ARM_TYPE:
18185 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
18186 stub_entry->stub_size))
18187 return FALSE;
18188 break;
18189 case THUMB16_TYPE:
18190 case THUMB32_TYPE:
18191 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
18192 stub_entry->stub_size))
18193 return FALSE;
18194 break;
18195 default:
18196 BFD_FAIL ();
18197 return 0;
18198 }
7413f23f 18199 }
da5938a2 18200
461a49ca
DJ		 18201 prev_type = DATA_TYPE;
18202 size = 0;
18203 for (i = 0; i < stub_entry->stub_template_size; i++)
18204 {
d3ce72d0 18205 switch (template_sequence[i].type)
461a49ca
DJ		 18206 {
18207 case ARM_TYPE:
18208 sym_type = ARM_MAP_ARM;
18209 break;
18210
18211 case THUMB16_TYPE:
48229727 18212 case THUMB32_TYPE:
461a49ca
DJ		 18213 sym_type = ARM_MAP_THUMB;
18214 break;
18215
18216 case DATA_TYPE:
18217 sym_type = ARM_MAP_DATA;
18218 break;
18219
18220 default:
18221 BFD_FAIL ();
4e31c731 18222 return FALSE;
461a49ca
DJ		 18223 }
18224
d3ce72d0 18225 if (template_sequence[i].type != prev_type)
461a49ca 18226 {
d3ce72d0 18227 prev_type = template_sequence[i].type;
461a49ca
DJ		 18228 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
18229 return FALSE;
18230 }
18231
d3ce72d0 18232 switch (template_sequence[i].type)
461a49ca
DJ		 18233 {
18234 case ARM_TYPE:
48229727 18235 case THUMB32_TYPE:
461a49ca
DJ		 18236 size += 4;
18237 break;
18238
18239 case THUMB16_TYPE:
18240 size += 2;
18241 break;
18242
18243 case DATA_TYPE:
18244 size += 4;
18245 break;
18246
18247 default:
18248 BFD_FAIL ();
4e31c731 18249 return FALSE;
461a49ca
DJ		 18250 }
18251 }
18252
da5938a2
NC		 18253 return TRUE;
18254}
18255
33811162
DG		 18256/* Output mapping symbols for linker generated sections,
18257 and for those data-only sections that do not have a
18258 $d. */
4e617b1e
PB		 18259
18260static bfd_boolean
18261elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 18262 struct bfd_link_info *info,
57402f1e 18263 void *flaginfo,
6e0b88f1
AM		 18264 int (*func) (void *, const char *,
18265 Elf_Internal_Sym *,
18266 asection *,
18267 struct elf_link_hash_entry *))
4e617b1e
PB		 18268{
18269 output_arch_syminfo osi;
18270 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 18271 bfd_vma offset;
18272 bfd_size_type size;
33811162 18273 bfd *input_bfd;
4e617b1e
PB		 18274
18275 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 18276 if (htab == NULL)
18277 return FALSE;
18278
906e58ca 18279 check_use_blx (htab);
91a5743d 18280
57402f1e 18281 osi.flaginfo = flaginfo;
4e617b1e
PB		 18282 osi.info = info;
18283 osi.func = func;
906e58ca 18284
33811162
DG		 18285 /* Add a $d mapping symbol to data-only sections that
18286 don't have any mapping symbol. This may result in (harmless) redundant
18287 mapping symbols. */
18288 for (input_bfd = info->input_bfds;
18289 input_bfd != NULL;
c72f2fb2 18290 input_bfd = input_bfd->link.next)
33811162
DG		 18291 {
18292 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
18293 for (osi.sec = input_bfd->sections;
18294 osi.sec != NULL;
18295 osi.sec = osi.sec->next)
18296 {
18297 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 18298 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
18299 != 0)
33811162
DG		 18300 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
18301 == SEC_HAS_CONTENTS
18302 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 18303 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 18304 && osi.sec->size > 0
18305 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 18306 {
18307 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18308 (output_bfd, osi.sec->output_section);
18309 if (osi.sec_shndx != (int)SHN_BAD)
18310 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
18311 }
18312 }
18313 }
18314
91a5743d
PB		 18315 /* ARM->Thumb glue. */
18316 if (htab->arm_glue_size > 0)
18317 {
3d4d4302
AM		 18318 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18319 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 18320
18321 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18322 (output_bfd, osi.sec->output_section);
0e1862bb 18323 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 18324 || htab->pic_veneer)
18325 size = ARM2THUMB_PIC_GLUE_SIZE;
18326 else if (htab->use_blx)
18327 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
18328 else
18329 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 18330
91a5743d
PB		 18331 for (offset = 0; offset < htab->arm_glue_size; offset += size)
18332 {
7413f23f
DJ		 18333 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
18334 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 18335 }
18336 }
18337
18338 /* Thumb->ARM glue. */
18339 if (htab->thumb_glue_size > 0)
18340 {
3d4d4302
AM		 18341 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18342 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 18343
18344 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18345 (output_bfd, osi.sec->output_section);
18346 size = THUMB2ARM_GLUE_SIZE;
18347
18348 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
18349 {
7413f23f
DJ		 18350 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
18351 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 18352 }
18353 }
18354
845b51d6
PB		 18355 /* ARMv4 BX veneers. */
18356 if (htab->bx_glue_size > 0)
18357 {
3d4d4302
AM		 18358 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18359 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 18360
18361 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18362 (output_bfd, osi.sec->output_section);
18363
7413f23f 18364 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 18365 }
18366
8029a119
NC		 18367 /* Long calls stubs. */
18368 if (htab->stub_bfd && htab->stub_bfd->sections)
18369 {
da5938a2 18370 asection* stub_sec;
8029a119 18371
da5938a2
NC		 18372 for (stub_sec = htab->stub_bfd->sections;
18373 stub_sec != NULL;
8029a119
NC		 18374 stub_sec = stub_sec->next)
18375 {
18376 /* Ignore non-stub sections. */
18377 if (!strstr (stub_sec->name, STUB_SUFFIX))
18378 continue;
da5938a2 18379
8029a119 18380 osi.sec = stub_sec;
da5938a2 18381
8029a119
NC		 18382 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18383 (output_bfd, osi.sec->output_section);
da5938a2 18384
8029a119
NC		 18385 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
18386 }
18387 }
da5938a2 18388
91a5743d 18389 /* Finally, output mapping symbols for the PLT. */
34e77a92 18390 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 18391 {
34e77a92
RS		 18392 osi.sec = htab->root.splt;
18393 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18394 (output_bfd, osi.sec->output_section));
18395
18396 /* Output mapping symbols for the plt header. SymbianOS does not have a
18397 plt header. */
18398 if (htab->vxworks_p)
18399 {
18400 /* VxWorks shared libraries have no PLT header. */
0e1862bb 18401 if (!bfd_link_pic (info))
34e77a92
RS		 18402 {
18403 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18404 return FALSE;
18405 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18406 return FALSE;
18407 }
18408 }
b38cadfb
NC		 18409 else if (htab->nacl_p)
18410 {
18411 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18412 return FALSE;
18413 }
59029f57 18414 else if (using_thumb_only (htab) && !htab->fdpic_p)
eed94f8f
NC		 18415 {
18416 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
18417 return FALSE;
18418 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18419 return FALSE;
18420 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
18421 return FALSE;
18422 }
e8b09b87 18423 else if (!htab->symbian_p && !htab->fdpic_p)
4e617b1e 18424 {
7413f23f 18425 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 18426 return FALSE;
34e77a92
RS		 18427#ifndef FOUR_WORD_PLT
18428 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 18429 return FALSE;
34e77a92 18430#endif
4e617b1e
PB		 18431 }
18432 }
99059e56
RM		 18433 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
18434 {
18435 /* NaCl uses a special first entry in .iplt too. */
18436 osi.sec = htab->root.iplt;
18437 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18438 (output_bfd, osi.sec->output_section));
18439 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18440 return FALSE;
18441 }
34e77a92
RS		 18442 if ((htab->root.splt && htab->root.splt->size > 0)
18443 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 18444 {
34e77a92
RS		 18445 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
18446 for (input_bfd = info->input_bfds;
18447 input_bfd != NULL;
c72f2fb2 18448 input_bfd = input_bfd->link.next)
34e77a92
RS		 18449 {
18450 struct arm_local_iplt_info **local_iplt;
18451 unsigned int i, num_syms;
4e617b1e 18452
34e77a92
RS		 18453 local_iplt = elf32_arm_local_iplt (input_bfd);
18454 if (local_iplt != NULL)
18455 {
18456 num_syms = elf_symtab_hdr (input_bfd).sh_info;
18457 for (i = 0; i < num_syms; i++)
18458 if (local_iplt[i] != NULL
18459 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
18460 &local_iplt[i]->root,
18461 &local_iplt[i]->arm))
18462 return FALSE;
18463 }
18464 }
18465 }
0855e32b
NS		 18466 if (htab->dt_tlsdesc_plt != 0)
18467 {
18468 /* Mapping symbols for the lazy tls trampoline. */
18469 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
18470 return FALSE;
b38cadfb 18471
0855e32b
NS		 18472 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18473 htab->dt_tlsdesc_plt + 24))
18474 return FALSE;
18475 }
18476 if (htab->tls_trampoline != 0)
18477 {
18478 /* Mapping symbols for the tls trampoline. */
18479 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
18480 return FALSE;
18481#ifdef FOUR_WORD_PLT
18482 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18483 htab->tls_trampoline + 12))
18484 return FALSE;
b38cadfb 18485#endif
0855e32b 18486 }
b38cadfb 18487
4e617b1e
PB		 18488 return TRUE;
18489}
18490
54ddd295
TP		 18491/* Filter normal symbols of CMSE entry functions of ABFD to include in
18492 the import library. All SYMCOUNT symbols of ABFD can be examined
18493 from their pointers in SYMS. Pointers of symbols to keep should be
18494 stored continuously at the beginning of that array.
18495
18496 Returns the number of symbols to keep. */
18497
18498static unsigned int
18499elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18500 struct bfd_link_info *info,
18501 asymbol **syms, long symcount)
18502{
18503 size_t maxnamelen;
18504 char *cmse_name;
18505 long src_count, dst_count = 0;
18506 struct elf32_arm_link_hash_table *htab;
18507
18508 htab = elf32_arm_hash_table (info);
18509 if (!htab->stub_bfd || !htab->stub_bfd->sections)
18510 symcount = 0;
18511
18512 maxnamelen = 128;
18513 cmse_name = (char *) bfd_malloc (maxnamelen);
7a0fb7be
NC		 18514 BFD_ASSERT (cmse_name);
18515
54ddd295
TP		 18516 for (src_count = 0; src_count < symcount; src_count++)
18517 {
18518 struct elf32_arm_link_hash_entry *cmse_hash;
18519 asymbol *sym;
18520 flagword flags;
18521 char *name;
18522 size_t namelen;
18523
18524 sym = syms[src_count];
18525 flags = sym->flags;
18526 name = (char *) bfd_asymbol_name (sym);
18527
18528 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
18529 continue;
18530 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
18531 continue;
18532
18533 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
18534 if (namelen > maxnamelen)
18535 {
18536 cmse_name = (char *)
18537 bfd_realloc (cmse_name, namelen);
18538 maxnamelen = namelen;
18539 }
18540 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
18541 cmse_hash = (struct elf32_arm_link_hash_entry *)
18542 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
18543
18544 if (!cmse_hash
18545 || (cmse_hash->root.root.type != bfd_link_hash_defined
18546 && cmse_hash->root.root.type != bfd_link_hash_defweak)
18547 || cmse_hash->root.type != STT_FUNC)
18548 continue;
18549
54ddd295
TP		 18550 syms[dst_count++] = sym;
18551 }
18552 free (cmse_name);
18553
18554 syms[dst_count] = NULL;
18555
18556 return dst_count;
18557}
18558
18559/* Filter symbols of ABFD to include in the import library. All
18560 SYMCOUNT symbols of ABFD can be examined from their pointers in
18561 SYMS. Pointers of symbols to keep should be stored continuously at
18562 the beginning of that array.
18563
18564 Returns the number of symbols to keep. */
18565
18566static unsigned int
18567elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18568 struct bfd_link_info *info,
18569 asymbol **syms, long symcount)
18570{
18571 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
18572
046734ff
TP		 18573 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18574 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18575 library to be a relocatable object file. */
18576 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
54ddd295
TP		 18577 if (globals->cmse_implib)
18578 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
18579 else
18580 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
18581}
18582
e489d0ae
PB		 18583/* Allocate target specific section data. */
18584
18585static bfd_boolean
18586elf32_arm_new_section_hook (bfd *abfd, asection *sec)
18587{
f592407e
AM		 18588 if (!sec->used_by_bfd)
18589 {
18590 _arm_elf_section_data *sdata;
986f0783 18591 size_t amt = sizeof (*sdata);
e489d0ae 18592
21d799b5 18593 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 18594 if (sdata == NULL)
18595 return FALSE;
18596 sec->used_by_bfd = sdata;
18597 }
e489d0ae
PB		 18598
18599 return _bfd_elf_new_section_hook (abfd, sec);
18600}
18601
18602
18603/* Used to order a list of mapping symbols by address. */
18604
18605static int
18606elf32_arm_compare_mapping (const void * a, const void * b)
18607{
7f6a71ff
JM		 18608 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
18609 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
18610
18611 if (amap->vma > bmap->vma)
18612 return 1;
18613 else if (amap->vma < bmap->vma)
18614 return -1;
18615 else if (amap->type > bmap->type)
18616 /* Ensure results do not depend on the host qsort for objects with
18617 multiple mapping symbols at the same address by sorting on type
18618 after vma. */
18619 return 1;
18620 else if (amap->type < bmap->type)
18621 return -1;
18622 else
18623 return 0;
e489d0ae
PB		 18624}
18625
2468f9c9
PB		 18626/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18627
18628static unsigned long
18629offset_prel31 (unsigned long addr, bfd_vma offset)
18630{
18631 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
18632}
18633
18634/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18635 relocations. */
18636
18637static void
18638copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
18639{
18640 unsigned long first_word = bfd_get_32 (output_bfd, from);
18641 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 18642
2468f9c9
PB		 18643 /* High bit of first word is supposed to be zero. */
18644 if ((first_word & 0x80000000ul) == 0)
18645 first_word = offset_prel31 (first_word, offset);
b38cadfb 18646
2468f9c9
PB		 18647 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18648 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18649 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
18650 second_word = offset_prel31 (second_word, offset);
b38cadfb 18651
2468f9c9
PB		 18652 bfd_put_32 (output_bfd, first_word, to);
18653 bfd_put_32 (output_bfd, second_word, to + 4);
18654}
e489d0ae 18655
48229727
JB		 18656/* Data for make_branch_to_a8_stub(). */
18657
b38cadfb
NC		 18658struct a8_branch_to_stub_data
18659{
48229727
JB		 18660 asection *writing_section;
18661 bfd_byte *contents;
18662};
18663
18664
18665/* Helper to insert branches to Cortex-A8 erratum stubs in the right
18666 places for a particular section. */
18667
18668static bfd_boolean
18669make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 18670 void *in_arg)
48229727
JB		 18671{
18672 struct elf32_arm_stub_hash_entry *stub_entry;
18673 struct a8_branch_to_stub_data *data;
18674 bfd_byte *contents;
18675 unsigned long branch_insn;
18676 bfd_vma veneered_insn_loc, veneer_entry_loc;
18677 bfd_signed_vma branch_offset;
18678 bfd *abfd;
8d9d9490 18679 unsigned int loc;
48229727
JB		 18680
18681 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
18682 data = (struct a8_branch_to_stub_data *) in_arg;
18683
18684 if (stub_entry->target_section != data->writing_section
4563a860 18685 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 18686 return TRUE;
18687
18688 contents = data->contents;
18689
8d9d9490
TP		 18690 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18691 generated when both source and target are in the same section. */
48229727
JB		 18692 veneered_insn_loc = stub_entry->target_section->output_section->vma
18693 + stub_entry->target_section->output_offset
8d9d9490 18694 + stub_entry->source_value;
48229727
JB		 18695
18696 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
18697 + stub_entry->stub_sec->output_offset
18698 + stub_entry->stub_offset;
18699
18700 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
18701 veneered_insn_loc &= ~3u;
18702
18703 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
18704
18705 abfd = stub_entry->target_section->owner;
8d9d9490 18706 loc = stub_entry->source_value;
48229727
JB		 18707
18708 /* We attempt to avoid this condition by setting stubs_always_after_branch
18709 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18710 This check is just to be on the safe side... */
18711 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
18712 {
871b3ab2 18713 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub is "
4eca0228 18714 "allocated in unsafe location"), abfd);
48229727
JB		 18715 return FALSE;
18716 }
18717
18718 switch (stub_entry->stub_type)
18719 {
18720 case arm_stub_a8_veneer_b:
18721 case arm_stub_a8_veneer_b_cond:
18722 branch_insn = 0xf0009000;
18723 goto jump24;
18724
18725 case arm_stub_a8_veneer_blx:
18726 branch_insn = 0xf000e800;
18727 goto jump24;
18728
18729 case arm_stub_a8_veneer_bl:
18730 {
18731 unsigned int i1, j1, i2, j2, s;
18732
18733 branch_insn = 0xf000d000;
18734
18735 jump24:
18736 if (branch_offset < -16777216 || branch_offset > 16777214)
18737 {
18738 /* There's not much we can do apart from complain if this
18739 happens. */
871b3ab2 18740 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub out "
4eca0228 18741 "of range (input file too large)"), abfd);
48229727
JB		 18742 return FALSE;
18743 }
18744
18745 /* i1 = not(j1 eor s), so:
18746 not i1 = j1 eor s
18747 j1 = (not i1) eor s. */
18748
18749 branch_insn |= (branch_offset >> 1) & 0x7ff;
18750 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
18751 i2 = (branch_offset >> 22) & 1;
18752 i1 = (branch_offset >> 23) & 1;
18753 s = (branch_offset >> 24) & 1;
18754 j1 = (!i1) ^ s;
18755 j2 = (!i2) ^ s;
18756 branch_insn |= j2 << 11;
18757 branch_insn |= j1 << 13;
18758 branch_insn |= s << 26;
18759 }
18760 break;
18761
18762 default:
18763 BFD_FAIL ();
18764 return FALSE;
18765 }
18766
8d9d9490
TP		 18767 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
18768 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 18769
18770 return TRUE;
18771}
18772
a504d23a
LA		 18773/* Beginning of stm32l4xx work-around. */
18774
18775/* Functions encoding instructions necessary for the emission of the
18776 fix-stm32l4xx-629360.
18777 Encoding is extracted from the
18778 ARM (C) Architecture Reference Manual
18779 ARMv7-A and ARMv7-R edition
18780 ARM DDI 0406C.b (ID072512). */
18781
18782static inline bfd_vma
82188b29 18783create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 18784{
18785 /* A8.8.18 B (A8-334)
18786 B target_address (Encoding T4). */
18787 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18788 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18789 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18790
a504d23a
LA		 18791 int s = ((branch_offset & 0x1000000) >> 24);
18792 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
18793 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
18794
18795 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
18796 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
18797
18798 bfd_vma patched_inst = 0xf0009000
18799 | s << 26 /* S. */
18800 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
18801 | j1 << 13 /* J1. */
18802 | j2 << 11 /* J2. */
18803 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
18804
18805 return patched_inst;
18806}
18807
18808static inline bfd_vma
18809create_instruction_ldmia (int base_reg, int wback, int reg_mask)
18810{
18811 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18812 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18813 bfd_vma patched_inst = 0xe8900000
18814 | (/*W=*/wback << 21)
18815 | (base_reg << 16)
18816 | (reg_mask & 0x0000ffff);
18817
18818 return patched_inst;
18819}
18820
18821static inline bfd_vma
18822create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
18823{
18824 /* A8.8.60 LDMDB/LDMEA (A8-402)
18825 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18826 bfd_vma patched_inst = 0xe9100000
18827 | (/*W=*/wback << 21)
18828 | (base_reg << 16)
18829 | (reg_mask & 0x0000ffff);
18830
18831 return patched_inst;
18832}
18833
18834static inline bfd_vma
18835create_instruction_mov (int target_reg, int source_reg)
18836{
18837 /* A8.8.103 MOV (register) (A8-486)
18838 MOV Rd, Rm (Encoding T1). */
18839 bfd_vma patched_inst = 0x4600
18840 | (target_reg & 0x7)
18841 | ((target_reg & 0x8) >> 3) << 7
18842 | (source_reg << 3);
18843
18844 return patched_inst;
18845}
18846
18847static inline bfd_vma
18848create_instruction_sub (int target_reg, int source_reg, int value)
18849{
18850 /* A8.8.221 SUB (immediate) (A8-708)
18851 SUB Rd, Rn, #value (Encoding T3). */
18852 bfd_vma patched_inst = 0xf1a00000
18853 | (target_reg << 8)
18854 | (source_reg << 16)
18855 | (/*S=*/0 << 20)
18856 | ((value & 0x800) >> 11) << 26
18857 | ((value & 0x700) >> 8) << 12
18858 | (value & 0x0ff);
18859
18860 return patched_inst;
18861}
18862
18863static inline bfd_vma
9239bbd3 18864create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 18865 int first_reg)
18866{
18867 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18868 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18869 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 18870 | (/*W=*/wback << 21)
18871 | (base_reg << 16)
9239bbd3
CM		 18872 | (num_words & 0x000000ff)
18873 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 18874 | (first_reg & 0x00000001) << 22;
18875
18876 return patched_inst;
18877}
18878
18879static inline bfd_vma
9239bbd3
CM		 18880create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
18881 int first_reg)
a504d23a
LA		 18882{
18883 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 18884 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18885 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 18886 | (base_reg << 16)
9239bbd3
CM		 18887 | (num_words & 0x000000ff)
18888 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 18889 | (first_reg & 0x00000001) << 22;
18890
18891 return patched_inst;
18892}
18893
18894static inline bfd_vma
18895create_instruction_udf_w (int value)
18896{
18897 /* A8.8.247 UDF (A8-758)
18898 Undefined (Encoding T2). */
18899 bfd_vma patched_inst = 0xf7f0a000
18900 | (value & 0x00000fff)
18901 | (value & 0x000f0000) << 16;
18902
18903 return patched_inst;
18904}
18905
18906static inline bfd_vma
18907create_instruction_udf (int value)
18908{
18909 /* A8.8.247 UDF (A8-758)
18910 Undefined (Encoding T1). */
18911 bfd_vma patched_inst = 0xde00
18912 | (value & 0xff);
18913
18914 return patched_inst;
18915}
18916
18917/* Functions writing an instruction in memory, returning the next
18918 memory position to write to. */
18919
18920static inline bfd_byte *
18921push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
18922 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18923{
18924 put_thumb2_insn (htab, output_bfd, insn, pt);
18925 return pt + 4;
18926}
18927
18928static inline bfd_byte *
18929push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
18930 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18931{
18932 put_thumb_insn (htab, output_bfd, insn, pt);
18933 return pt + 2;
18934}
18935
18936/* Function filling up a region in memory with T1 and T2 UDFs taking
18937 care of alignment. */
18938
18939static bfd_byte *
18940stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
07d6d2b8
AM		 18941 bfd * output_bfd,
18942 const bfd_byte * const base_stub_contents,
18943 bfd_byte * const from_stub_contents,
18944 const bfd_byte * const end_stub_contents)
a504d23a
LA		 18945{
18946 bfd_byte *current_stub_contents = from_stub_contents;
18947
18948 /* Fill the remaining of the stub with deterministic contents : UDF
18949 instructions.
18950 Check if realignment is needed on modulo 4 frontier using T1, to
18951 further use T2. */
18952 if ((current_stub_contents < end_stub_contents)
18953 && !((current_stub_contents - base_stub_contents) % 2)
18954 && ((current_stub_contents - base_stub_contents) % 4))
18955 current_stub_contents =
18956 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18957 create_instruction_udf (0));
18958
18959 for (; current_stub_contents < end_stub_contents;)
18960 current_stub_contents =
18961 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18962 create_instruction_udf_w (0));
18963
18964 return current_stub_contents;
18965}
18966
18967/* Functions writing the stream of instructions equivalent to the
18968 derived sequence for ldmia, ldmdb, vldm respectively. */
18969
18970static void
18971stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
18972 bfd * output_bfd,
18973 const insn32 initial_insn,
18974 const bfd_byte *const initial_insn_addr,
18975 bfd_byte *const base_stub_contents)
18976{
18977 int wback = (initial_insn & 0x00200000) >> 21;
18978 int ri, rn = (initial_insn & 0x000F0000) >> 16;
18979 int insn_all_registers = initial_insn & 0x0000ffff;
18980 int insn_low_registers, insn_high_registers;
18981 int usable_register_mask;
b25e998d 18982 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 18983 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18984 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
18985 bfd_byte *current_stub_contents = base_stub_contents;
18986
18987 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
18988
18989 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18990 smaller than 8 registers load sequences that do not cause the
18991 hardware issue. */
18992 if (nb_registers <= 8)
18993 {
18994 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18995 current_stub_contents =
18996 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18997 initial_insn);
18998
18999 /* B initial_insn_addr+4. */
19000 if (!restore_pc)
19001 current_stub_contents =
19002 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19003 create_instruction_branch_absolute
82188b29 19004 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19005
19006 /* Fill the remaining of the stub with deterministic contents. */
19007 current_stub_contents =
19008 stm32l4xx_fill_stub_udf (htab, output_bfd,
19009 base_stub_contents, current_stub_contents,
19010 base_stub_contents +
19011 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19012
19013 return;
19014 }
19015
19016 /* - reg_list[13] == 0. */
19017 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
19018
19019 /* - reg_list[14] & reg_list[15] != 1. */
19020 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
19021
19022 /* - if (wback==1) reg_list[rn] == 0. */
19023 BFD_ASSERT (!wback || !restore_rn);
19024
19025 /* - nb_registers > 8. */
b25e998d 19026 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19027
19028 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19029
19030 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
19031 - One with the 7 lowest registers (register mask 0x007F)
19032 This LDM will finally contain between 2 and 7 registers
19033 - One with the 7 highest registers (register mask 0xDF80)
19034 This ldm will finally contain between 2 and 7 registers. */
19035 insn_low_registers = insn_all_registers & 0x007F;
19036 insn_high_registers = insn_all_registers & 0xDF80;
19037
19038 /* A spare register may be needed during this veneer to temporarily
19039 handle the base register. This register will be restored with the
19040 last LDM operation.
19041 The usable register may be any general purpose register (that
19042 excludes PC, SP, LR : register mask is 0x1FFF). */
19043 usable_register_mask = 0x1FFF;
19044
19045 /* Generate the stub function. */
19046 if (wback)
19047 {
19048 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
19049 current_stub_contents =
19050 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19051 create_instruction_ldmia
19052 (rn, /*wback=*/1, insn_low_registers));
19053
19054 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
19055 current_stub_contents =
19056 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19057 create_instruction_ldmia
19058 (rn, /*wback=*/1, insn_high_registers));
19059 if (!restore_pc)
19060 {
19061 /* B initial_insn_addr+4. */
19062 current_stub_contents =
19063 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19064 create_instruction_branch_absolute
82188b29 19065 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19066 }
19067 }
19068 else /* if (!wback). */
19069 {
19070 ri = rn;
19071
19072 /* If Rn is not part of the high-register-list, move it there. */
19073 if (!(insn_high_registers & (1 << rn)))
19074 {
19075 /* Choose a Ri in the high-register-list that will be restored. */
19076 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19077
19078 /* MOV Ri, Rn. */
19079 current_stub_contents =
19080 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19081 create_instruction_mov (ri, rn));
19082 }
19083
19084 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
19085 current_stub_contents =
19086 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19087 create_instruction_ldmia
19088 (ri, /*wback=*/1, insn_low_registers));
19089
19090 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
19091 current_stub_contents =
19092 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19093 create_instruction_ldmia
19094 (ri, /*wback=*/0, insn_high_registers));
19095
19096 if (!restore_pc)
19097 {
19098 /* B initial_insn_addr+4. */
19099 current_stub_contents =
19100 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19101 create_instruction_branch_absolute
82188b29 19102 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19103 }
19104 }
19105
19106 /* Fill the remaining of the stub with deterministic contents. */
19107 current_stub_contents =
19108 stm32l4xx_fill_stub_udf (htab, output_bfd,
19109 base_stub_contents, current_stub_contents,
19110 base_stub_contents +
19111 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19112}
19113
19114static void
19115stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
19116 bfd * output_bfd,
19117 const insn32 initial_insn,
19118 const bfd_byte *const initial_insn_addr,
19119 bfd_byte *const base_stub_contents)
19120{
19121 int wback = (initial_insn & 0x00200000) >> 21;
19122 int ri, rn = (initial_insn & 0x000f0000) >> 16;
19123 int insn_all_registers = initial_insn & 0x0000ffff;
19124 int insn_low_registers, insn_high_registers;
19125 int usable_register_mask;
19126 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
19127 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 19128 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 19129 bfd_byte *current_stub_contents = base_stub_contents;
19130
19131 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
19132
19133 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19134 smaller than 8 registers load sequences that do not cause the
19135 hardware issue. */
19136 if (nb_registers <= 8)
19137 {
19138 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
19139 current_stub_contents =
19140 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19141 initial_insn);
19142
19143 /* B initial_insn_addr+4. */
19144 current_stub_contents =
19145 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19146 create_instruction_branch_absolute
82188b29 19147 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19148
19149 /* Fill the remaining of the stub with deterministic contents. */
19150 current_stub_contents =
19151 stm32l4xx_fill_stub_udf (htab, output_bfd,
19152 base_stub_contents, current_stub_contents,
19153 base_stub_contents +
19154 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19155
19156 return;
19157 }
19158
19159 /* - reg_list[13] == 0. */
19160 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
19161
19162 /* - reg_list[14] & reg_list[15] != 1. */
19163 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
19164
19165 /* - if (wback==1) reg_list[rn] == 0. */
19166 BFD_ASSERT (!wback || !restore_rn);
19167
19168 /* - nb_registers > 8. */
b25e998d 19169 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 19170
19171 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19172
19173 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
19174 - One with the 7 lowest registers (register mask 0x007F)
19175 This LDM will finally contain between 2 and 7 registers
19176 - One with the 7 highest registers (register mask 0xDF80)
19177 This ldm will finally contain between 2 and 7 registers. */
19178 insn_low_registers = insn_all_registers & 0x007F;
19179 insn_high_registers = insn_all_registers & 0xDF80;
19180
19181 /* A spare register may be needed during this veneer to temporarily
19182 handle the base register. This register will be restored with
19183 the last LDM operation.
19184 The usable register may be any general purpose register (that excludes
19185 PC, SP, LR : register mask is 0x1FFF). */
19186 usable_register_mask = 0x1FFF;
19187
19188 /* Generate the stub function. */
19189 if (!wback && !restore_pc && !restore_rn)
19190 {
19191 /* Choose a Ri in the low-register-list that will be restored. */
19192 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19193
19194 /* MOV Ri, Rn. */
19195 current_stub_contents =
19196 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19197 create_instruction_mov (ri, rn));
19198
19199 /* LDMDB Ri!, {R-high-register-list}. */
19200 current_stub_contents =
19201 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19202 create_instruction_ldmdb
19203 (ri, /*wback=*/1, insn_high_registers));
19204
19205 /* LDMDB Ri, {R-low-register-list}. */
19206 current_stub_contents =
19207 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19208 create_instruction_ldmdb
19209 (ri, /*wback=*/0, insn_low_registers));
19210
19211 /* B initial_insn_addr+4. */
19212 current_stub_contents =
19213 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19214 create_instruction_branch_absolute
82188b29 19215 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19216 }
19217 else if (wback && !restore_pc && !restore_rn)
19218 {
19219 /* LDMDB Rn!, {R-high-register-list}. */
19220 current_stub_contents =
19221 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19222 create_instruction_ldmdb
19223 (rn, /*wback=*/1, insn_high_registers));
19224
19225 /* LDMDB Rn!, {R-low-register-list}. */
19226 current_stub_contents =
19227 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19228 create_instruction_ldmdb
19229 (rn, /*wback=*/1, insn_low_registers));
19230
19231 /* B initial_insn_addr+4. */
19232 current_stub_contents =
19233 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19234 create_instruction_branch_absolute
82188b29 19235 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19236 }
19237 else if (!wback && restore_pc && !restore_rn)
19238 {
19239 /* Choose a Ri in the high-register-list that will be restored. */
19240 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19241
19242 /* SUB Ri, Rn, #(4*nb_registers). */
19243 current_stub_contents =
19244 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19245 create_instruction_sub (ri, rn, (4 * nb_registers)));
19246
19247 /* LDMIA Ri!, {R-low-register-list}. */
19248 current_stub_contents =
19249 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19250 create_instruction_ldmia
19251 (ri, /*wback=*/1, insn_low_registers));
19252
19253 /* LDMIA Ri, {R-high-register-list}. */
19254 current_stub_contents =
19255 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19256 create_instruction_ldmia
19257 (ri, /*wback=*/0, insn_high_registers));
19258 }
19259 else if (wback && restore_pc && !restore_rn)
19260 {
19261 /* Choose a Ri in the high-register-list that will be restored. */
19262 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19263
19264 /* SUB Rn, Rn, #(4*nb_registers) */
19265 current_stub_contents =
19266 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19267 create_instruction_sub (rn, rn, (4 * nb_registers)));
19268
19269 /* MOV Ri, Rn. */
19270 current_stub_contents =
19271 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19272 create_instruction_mov (ri, rn));
19273
19274 /* LDMIA Ri!, {R-low-register-list}. */
19275 current_stub_contents =
19276 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19277 create_instruction_ldmia
19278 (ri, /*wback=*/1, insn_low_registers));
19279
19280 /* LDMIA Ri, {R-high-register-list}. */
19281 current_stub_contents =
19282 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19283 create_instruction_ldmia
19284 (ri, /*wback=*/0, insn_high_registers));
19285 }
19286 else if (!wback && !restore_pc && restore_rn)
19287 {
19288 ri = rn;
19289 if (!(insn_low_registers & (1 << rn)))
19290 {
19291 /* Choose a Ri in the low-register-list that will be restored. */
19292 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19293
19294 /* MOV Ri, Rn. */
19295 current_stub_contents =
19296 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19297 create_instruction_mov (ri, rn));
19298 }
19299
19300 /* LDMDB Ri!, {R-high-register-list}. */
19301 current_stub_contents =
19302 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19303 create_instruction_ldmdb
19304 (ri, /*wback=*/1, insn_high_registers));
19305
19306 /* LDMDB Ri, {R-low-register-list}. */
19307 current_stub_contents =
19308 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19309 create_instruction_ldmdb
19310 (ri, /*wback=*/0, insn_low_registers));
19311
19312 /* B initial_insn_addr+4. */
19313 current_stub_contents =
19314 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19315 create_instruction_branch_absolute
82188b29 19316 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19317 }
19318 else if (!wback && restore_pc && restore_rn)
19319 {
19320 ri = rn;
19321 if (!(insn_high_registers & (1 << rn)))
19322 {
19323 /* Choose a Ri in the high-register-list that will be restored. */
19324 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19325 }
19326
19327 /* SUB Ri, Rn, #(4*nb_registers). */
19328 current_stub_contents =
19329 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19330 create_instruction_sub (ri, rn, (4 * nb_registers)));
19331
19332 /* LDMIA Ri!, {R-low-register-list}. */
19333 current_stub_contents =
19334 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19335 create_instruction_ldmia
19336 (ri, /*wback=*/1, insn_low_registers));
19337
19338 /* LDMIA Ri, {R-high-register-list}. */
19339 current_stub_contents =
19340 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19341 create_instruction_ldmia
19342 (ri, /*wback=*/0, insn_high_registers));
19343 }
19344 else if (wback && restore_rn)
19345 {
19346 /* The assembler should not have accepted to encode this. */
19347 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
19348 "undefined behavior.\n");
19349 }
19350
19351 /* Fill the remaining of the stub with deterministic contents. */
19352 current_stub_contents =
19353 stm32l4xx_fill_stub_udf (htab, output_bfd,
19354 base_stub_contents, current_stub_contents,
19355 base_stub_contents +
19356 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19357
19358}
19359
19360static void
19361stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
19362 bfd * output_bfd,
19363 const insn32 initial_insn,
19364 const bfd_byte *const initial_insn_addr,
19365 bfd_byte *const base_stub_contents)
19366{
13c9c485 19367 int num_words = initial_insn & 0xff;
a504d23a
LA		 19368 bfd_byte *current_stub_contents = base_stub_contents;
19369
19370 BFD_ASSERT (is_thumb2_vldm (initial_insn));
19371
19372 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 19373 smaller than 8 words load sequences that do not cause the
a504d23a 19374 hardware issue. */
9239bbd3 19375 if (num_words <= 8)
a504d23a
LA		 19376 {
19377 /* Untouched instruction. */
19378 current_stub_contents =
19379 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19380 initial_insn);
19381
19382 /* B initial_insn_addr+4. */
19383 current_stub_contents =
19384 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19385 create_instruction_branch_absolute
82188b29 19386 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19387 }
19388 else
19389 {
9eaff861 19390 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 19391 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 19392 bfd_boolean is_ia_nobang = /* (IA without !). */
19393 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
19394 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
19395 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
19396 bfd_boolean is_db_bang = /* (DB with !). */
19397 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 19398 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 19399 /* d = UInt (Vd:D);. */
9239bbd3 19400 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 19401 | (((unsigned int)initial_insn << 9) >> 31);
19402
9239bbd3
CM		 19403 /* Compute the number of 8-words chunks needed to split. */
19404 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 19405 int chunk;
19406
19407 /* The test coverage has been done assuming the following
19408 hypothesis that exactly one of the previous is_ predicates is
19409 true. */
9239bbd3
CM		 19410 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
19411 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 19412
9239bbd3 19413 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 19414 cases, then we emit the adjustments:
19415
19416 vldm rx, {...}
19417 -> vldm rx!, {8_words_or_less} for each needed 8_word
19418 -> sub rx, rx, #size (list)
19419
19420 vldm rx!, {...}
19421 -> vldm rx!, {8_words_or_less} for each needed 8_word
19422 This also handles vpop instruction (when rx is sp)
19423
19424 vldmd rx!, {...}
19425 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 19426 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 19427 {
9239bbd3
CM		 19428 bfd_vma new_insn = 0;
19429
a504d23a
LA		 19430 if (is_ia_nobang || is_ia_bang)
19431 {
9239bbd3
CM		 19432 new_insn = create_instruction_vldmia
19433 (base_reg,
19434 is_dp,
19435 /*wback= . */1,
19436 chunks - (chunk + 1) ?
19437 8 : num_words - chunk * 8,
19438 first_reg + chunk * 8);
a504d23a
LA		 19439 }
19440 else if (is_db_bang)
19441 {
9239bbd3
CM		 19442 new_insn = create_instruction_vldmdb
19443 (base_reg,
19444 is_dp,
19445 chunks - (chunk + 1) ?
19446 8 : num_words - chunk * 8,
19447 first_reg + chunk * 8);
a504d23a 19448 }
9239bbd3
CM		 19449
19450 if (new_insn)
19451 current_stub_contents =
19452 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19453 new_insn);
a504d23a
LA		 19454 }
19455
19456 /* Only this case requires the base register compensation
19457 subtract. */
19458 if (is_ia_nobang)
19459 {
19460 current_stub_contents =
19461 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19462 create_instruction_sub
9239bbd3 19463 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 19464 }
19465
19466 /* B initial_insn_addr+4. */
19467 current_stub_contents =
19468 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19469 create_instruction_branch_absolute
82188b29 19470 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 19471 }
19472
19473 /* Fill the remaining of the stub with deterministic contents. */
19474 current_stub_contents =
19475 stm32l4xx_fill_stub_udf (htab, output_bfd,
19476 base_stub_contents, current_stub_contents,
19477 base_stub_contents +
19478 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19479}
19480
19481static void
19482stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
19483 bfd * output_bfd,
19484 const insn32 wrong_insn,
19485 const bfd_byte *const wrong_insn_addr,
19486 bfd_byte *const stub_contents)
19487{
19488 if (is_thumb2_ldmia (wrong_insn))
19489 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
19490 wrong_insn, wrong_insn_addr,
19491 stub_contents);
19492 else if (is_thumb2_ldmdb (wrong_insn))
19493 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
19494 wrong_insn, wrong_insn_addr,
19495 stub_contents);
19496 else if (is_thumb2_vldm (wrong_insn))
19497 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
19498 wrong_insn, wrong_insn_addr,
19499 stub_contents);
19500}
19501
19502/* End of stm32l4xx work-around. */
19503
19504
e489d0ae
PB		 19505/* Do code byteswapping. Return FALSE afterwards so that the section is
19506 written out as normal. */
19507
19508static bfd_boolean
c7b8f16e 19509elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 19510 struct bfd_link_info *link_info,
19511 asection *sec,
e489d0ae
PB		 19512 bfd_byte *contents)
19513{
48229727 19514 unsigned int mapcount, errcount;
8e3de13a 19515 _arm_elf_section_data *arm_data;
c7b8f16e 19516 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 19517 elf32_arm_section_map *map;
c7b8f16e 19518 elf32_vfp11_erratum_list *errnode;
a504d23a 19519 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 19520 bfd_vma ptr;
19521 bfd_vma end;
c7b8f16e 19522 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 19523 bfd_byte tmp;
48229727 19524 unsigned int i;
57e8b36a 19525
4dfe6ac6
NC		 19526 if (globals == NULL)
19527 return FALSE;
19528
8e3de13a
NC		 19529 /* If this section has not been allocated an _arm_elf_section_data
19530 structure then we cannot record anything. */
19531 arm_data = get_arm_elf_section_data (sec);
19532 if (arm_data == NULL)
19533 return FALSE;
19534
19535 mapcount = arm_data->mapcount;
19536 map = arm_data->map;
c7b8f16e
JB		 19537 errcount = arm_data->erratumcount;
19538
19539 if (errcount != 0)
19540 {
19541 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
19542
19543 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 19544 errnode = errnode->next)
19545 {
19546 bfd_vma target = errnode->vma - offset;
19547
19548 switch (errnode->type)
19549 {
19550 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
19551 {
19552 bfd_vma branch_to_veneer;
19553 /* Original condition code of instruction, plus bit mask for
19554 ARM B instruction. */
19555 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
19556 | 0x0a000000;
c7b8f16e
JB		 19557
19558 /* The instruction is before the label. */
91d6fa6a 19559 target -= 4;
c7b8f16e
JB		 19560
19561 /* Above offset included in -4 below. */
19562 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 19563 - errnode->vma - 4;
c7b8f16e
JB		 19564
19565 if ((signed) branch_to_veneer < -(1 << 25)
19566 || (signed) branch_to_veneer >= (1 << 25))
871b3ab2 19567 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19568 "range"), output_bfd);
c7b8f16e 19569
99059e56
RM		 19570 insn |= (branch_to_veneer >> 2) & 0xffffff;
19571 contents[endianflip ^ target] = insn & 0xff;
19572 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19573 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19574 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19575 }
19576 break;
c7b8f16e
JB		 19577
19578 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 19579 {
19580 bfd_vma branch_from_veneer;
19581 unsigned int insn;
c7b8f16e 19582
99059e56
RM		 19583 /* Take size of veneer into account. */
19584 branch_from_veneer = errnode->u.v.branch->vma
19585 - errnode->vma - 12;
c7b8f16e
JB		 19586
19587 if ((signed) branch_from_veneer < -(1 << 25)
19588 || (signed) branch_from_veneer >= (1 << 25))
871b3ab2 19589 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 19590 "range"), output_bfd);
c7b8f16e 19591
99059e56
RM		 19592 /* Original instruction. */
19593 insn = errnode->u.v.branch->u.b.vfp_insn;
19594 contents[endianflip ^ target] = insn & 0xff;
19595 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19596 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19597 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19598
19599 /* Branch back to insn after original insn. */
19600 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
19601 contents[endianflip ^ (target + 4)] = insn & 0xff;
19602 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
19603 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
19604 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
19605 }
19606 break;
c7b8f16e 19607
99059e56
RM		 19608 default:
19609 abort ();
19610 }
19611 }
c7b8f16e 19612 }
e489d0ae 19613
a504d23a
LA		 19614 if (arm_data->stm32l4xx_erratumcount != 0)
19615 {
19616 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
19617 stm32l4xx_errnode != 0;
19618 stm32l4xx_errnode = stm32l4xx_errnode->next)
19619 {
19620 bfd_vma target = stm32l4xx_errnode->vma - offset;
19621
19622 switch (stm32l4xx_errnode->type)
19623 {
19624 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
19625 {
19626 unsigned int insn;
19627 bfd_vma branch_to_veneer =
19628 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
19629
19630 if ((signed) branch_to_veneer < -(1 << 24)
19631 || (signed) branch_to_veneer >= (1 << 24))
19632 {
19633 bfd_vma out_of_range =
19634 ((signed) branch_to_veneer < -(1 << 24)) ?
19635 - branch_to_veneer - (1 << 24) :
19636 ((signed) branch_to_veneer >= (1 << 24)) ?
19637 branch_to_veneer - (1 << 24) : 0;
19638
4eca0228 19639 _bfd_error_handler
2dcf00ce 19640 (_("%pB(%#" PRIx64 "): error: "
90b6238f
AM		 19641 "cannot create STM32L4XX veneer; "
19642 "jump out of range by %" PRId64 " bytes; "
19643 "cannot encode branch instruction"),
a504d23a 19644 output_bfd,
2dcf00ce
AM		 19645 (uint64_t) (stm32l4xx_errnode->vma - 4),
19646 (int64_t) out_of_range);
a504d23a
LA		 19647 continue;
19648 }
19649
19650 insn = create_instruction_branch_absolute
82188b29 19651 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a 19652
a2699ef2
AM		 19653 /* The instruction is before the label. */
19654 target -= 4;
19655
a504d23a
LA		 19656 put_thumb2_insn (globals, output_bfd,
19657 (bfd_vma) insn, contents + target);
19658 }
19659 break;
19660
19661 case STM32L4XX_ERRATUM_VENEER:
19662 {
82188b29
NC		 19663 bfd_byte * veneer;
19664 bfd_byte * veneer_r;
a504d23a
LA		 19665 unsigned int insn;
19666
82188b29
NC		 19667 veneer = contents + target;
19668 veneer_r = veneer
19669 + stm32l4xx_errnode->u.b.veneer->vma
19670 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 19671
19672 if ((signed) (veneer_r - veneer -
19673 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19674 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19675 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19676 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
19677 || (signed) (veneer_r - veneer) >= (1 << 24))
19678 {
90b6238f
AM		 19679 _bfd_error_handler (_("%pB: error: cannot create STM32L4XX "
19680 "veneer"), output_bfd);
a504d23a
LA		 19681 continue;
19682 }
19683
19684 /* Original instruction. */
19685 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
19686
19687 stm32l4xx_create_replacing_stub
19688 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
19689 }
19690 break;
19691
19692 default:
19693 abort ();
19694 }
19695 }
19696 }
19697
2468f9c9
PB		 19698 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
19699 {
19700 arm_unwind_table_edit *edit_node
99059e56 19701 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 19702 /* Now, sec->size is the size of the section we will write. The original
99059e56 19703 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 19704 markers) was sec->rawsize. (This isn't the case if we perform no
19705 edits, then rawsize will be zero and we should use size). */
21d799b5 19706 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 19707 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
19708 unsigned int in_index, out_index;
19709 bfd_vma add_to_offsets = 0;
19710
7a0fb7be
NC		 19711 if (edited_contents == NULL)
19712 return FALSE;
2468f9c9 19713 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 19714 {
2468f9c9
PB		 19715 if (edit_node)
19716 {
19717 unsigned int edit_index = edit_node->index;
b38cadfb 19718
2468f9c9 19719 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 19720 {
2468f9c9
PB		 19721 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19722 contents + in_index * 8, add_to_offsets);
19723 out_index++;
19724 in_index++;
19725 }
19726 else if (in_index == edit_index
19727 || (in_index * 8 >= input_size
19728 && edit_index == UINT_MAX))
99059e56 19729 {
2468f9c9
PB		 19730 switch (edit_node->type)
19731 {
19732 case DELETE_EXIDX_ENTRY:
19733 in_index++;
19734 add_to_offsets += 8;
19735 break;
b38cadfb 19736
2468f9c9
PB		 19737 case INSERT_EXIDX_CANTUNWIND_AT_END:
19738 {
99059e56 19739 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 19740 bfd_vma text_offset = text_sec->output_section->vma
19741 + text_sec->output_offset
19742 + text_sec->size;
19743 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 19744 unsigned long prel31_offset;
2468f9c9
PB		 19745
19746 /* Note: this is meant to be equivalent to an
19747 R_ARM_PREL31 relocation. These synthetic
19748 EXIDX_CANTUNWIND markers are not relocated by the
19749 usual BFD method. */
19750 prel31_offset = (text_offset - exidx_offset)
19751 & 0x7ffffffful;
491d01d3
YU		 19752 if (bfd_link_relocatable (link_info))
19753 {
19754 /* Here relocation for new EXIDX_CANTUNWIND is
19755 created, so there is no need to
19756 adjust offset by hand. */
19757 prel31_offset = text_sec->output_offset
19758 + text_sec->size;
491d01d3 19759 }
2468f9c9
PB		 19760
19761 /* First address we can't unwind. */
19762 bfd_put_32 (output_bfd, prel31_offset,
19763 &edited_contents[out_index * 8]);
19764
19765 /* Code for EXIDX_CANTUNWIND. */
19766 bfd_put_32 (output_bfd, 0x1,
19767 &edited_contents[out_index * 8 + 4]);
19768
19769 out_index++;
19770 add_to_offsets -= 8;
19771 }
19772 break;
19773 }
b38cadfb 19774
2468f9c9
PB		 19775 edit_node = edit_node->next;
19776 }
19777 }
19778 else
19779 {
19780 /* No more edits, copy remaining entries verbatim. */
19781 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19782 contents + in_index * 8, add_to_offsets);
19783 out_index++;
19784 in_index++;
19785 }
19786 }
19787
19788 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
19789 bfd_set_section_contents (output_bfd, sec->output_section,
19790 edited_contents,
19791 (file_ptr) sec->output_offset, sec->size);
19792
19793 return TRUE;
19794 }
19795
48229727
JB		 19796 /* Fix code to point to Cortex-A8 erratum stubs. */
19797 if (globals->fix_cortex_a8)
19798 {
19799 struct a8_branch_to_stub_data data;
19800
19801 data.writing_section = sec;
19802 data.contents = contents;
19803
a504d23a
LA		 19804 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
19805 & data);
48229727
JB		 19806 }
19807
e489d0ae
PB		 19808 if (mapcount == 0)
19809 return FALSE;
19810
c7b8f16e 19811 if (globals->byteswap_code)
e489d0ae 19812 {
c7b8f16e 19813 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 19814
c7b8f16e
JB		 19815 ptr = map[0].vma;
19816 for (i = 0; i < mapcount; i++)
99059e56
RM		 19817 {
19818 if (i == mapcount - 1)
c7b8f16e 19819 end = sec->size;
99059e56
RM		 19820 else
19821 end = map[i + 1].vma;
e489d0ae 19822
99059e56 19823 switch (map[i].type)
e489d0ae 19824 {
c7b8f16e
JB		 19825 case 'a':
19826 /* Byte swap code words. */
19827 while (ptr + 3 < end)
99059e56
RM		 19828 {
19829 tmp = contents[ptr];
19830 contents[ptr] = contents[ptr + 3];
19831 contents[ptr + 3] = tmp;
19832 tmp = contents[ptr + 1];
19833 contents[ptr + 1] = contents[ptr + 2];
19834 contents[ptr + 2] = tmp;
19835 ptr += 4;
19836 }
c7b8f16e 19837 break;
e489d0ae 19838
c7b8f16e
JB		 19839 case 't':
19840 /* Byte swap code halfwords. */
19841 while (ptr + 1 < end)
99059e56
RM		 19842 {
19843 tmp = contents[ptr];
19844 contents[ptr] = contents[ptr + 1];
19845 contents[ptr + 1] = tmp;
19846 ptr += 2;
19847 }
c7b8f16e
JB		 19848 break;
19849
19850 case 'd':
19851 /* Leave data alone. */
19852 break;
19853 }
99059e56
RM		 19854 ptr = end;
19855 }
e489d0ae 19856 }
8e3de13a 19857
93204d3a 19858 free (map);
47b2e99c 19859 arm_data->mapcount = -1;
c7b8f16e 19860 arm_data->mapsize = 0;
8e3de13a 19861 arm_data->map = NULL;
8e3de13a 19862
e489d0ae
PB		 19863 return FALSE;
19864}
19865
0beaef2b
PB		 19866/* Mangle thumb function symbols as we read them in. */
19867
8384fb8f 19868static bfd_boolean
0beaef2b
PB		 19869elf32_arm_swap_symbol_in (bfd * abfd,
19870 const void *psrc,
19871 const void *pshn,
19872 Elf_Internal_Sym *dst)
19873{
8384fb8f
AM		 19874 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
19875 return FALSE;
39d911fc 19876 dst->st_target_internal = 0;
0beaef2b
PB		 19877
19878 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 19879 the address. */
63e1a0fc
PB		 19880 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
19881 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 19882 {
63e1a0fc
PB		 19883 if (dst->st_value & 1)
19884 {
19885 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 19886 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
19887 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 19888 }
19889 else
39d911fc 19890 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 19891 }
19892 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
19893 {
19894 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 19895 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 19896 }
35fc36a8 19897 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 19898 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 19899 else
39d911fc 19900 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 19901
8384fb8f 19902 return TRUE;
0beaef2b
PB		 19903}
19904
19905
19906/* Mangle thumb function symbols as we write them out. */
19907
19908static void
19909elf32_arm_swap_symbol_out (bfd *abfd,
19910 const Elf_Internal_Sym *src,
19911 void *cdst,
19912 void *shndx)
19913{
19914 Elf_Internal_Sym newsym;
19915
19916 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19917 of the address set, as per the new EABI. We do this unconditionally
19918 because objcopy does not set the elf header flags until after
19919 it writes out the symbol table. */
39d911fc 19920 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 19921 {
19922 newsym = *src;
34e77a92
RS		 19923 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
19924 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 19925 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 19926 {
19927 /* Do this only for defined symbols. At link type, the static
19928 linker will simulate the work of dynamic linker of resolving
19929 symbols and will carry over the thumbness of found symbols to
19930 the output symbol table. It's not clear how it happens, but
19931 the thumbness of undefined symbols can well be different at
19932 runtime, and writing '1' for them will be confusing for users
19933 and possibly for dynamic linker itself.
19934 */
19935 newsym.st_value |= 1;
19936 }
906e58ca 19937
0beaef2b
PB		 19938 src = &newsym;
19939 }
19940 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
19941}
19942
b294bdf8
MM		 19943/* Add the PT_ARM_EXIDX program header. */
19944
19945static bfd_boolean
906e58ca 19946elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 19947 struct bfd_link_info *info ATTRIBUTE_UNUSED)
19948{
19949 struct elf_segment_map *m;
19950 asection *sec;
19951
19952 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19953 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19954 {
19955 /* If there is already a PT_ARM_EXIDX header, then we do not
19956 want to add another one. This situation arises when running
19957 "strip"; the input binary already has the header. */
12bd6957 19958 m = elf_seg_map (abfd);
b294bdf8
MM		 19959 while (m && m->p_type != PT_ARM_EXIDX)
19960 m = m->next;
19961 if (!m)
19962 {
21d799b5 19963 m = (struct elf_segment_map *)
99059e56 19964 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 19965 if (m == NULL)
19966 return FALSE;
19967 m->p_type = PT_ARM_EXIDX;
19968 m->count = 1;
19969 m->sections[0] = sec;
19970
12bd6957
AM		 19971 m->next = elf_seg_map (abfd);
19972 elf_seg_map (abfd) = m;
b294bdf8
MM		 19973 }
19974 }
19975
19976 return TRUE;
19977}
19978
19979/* We may add a PT_ARM_EXIDX program header. */
19980
19981static int
a6b96beb
AM		 19982elf32_arm_additional_program_headers (bfd *abfd,
19983 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 19984{
19985 asection *sec;
19986
19987 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19988 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19989 return 1;
19990 else
19991 return 0;
19992}
19993
34e77a92
RS		 19994/* Hook called by the linker routine which adds symbols from an object
19995 file. */
19996
19997static bfd_boolean
19998elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
19999 Elf_Internal_Sym *sym, const char **namep,
20000 flagword *flagsp, asection **secp, bfd_vma *valp)
20001{
c792917c
NC		 20002 if (elf32_arm_hash_table (info) == NULL)
20003 return FALSE;
20004
34e77a92
RS		 20005 if (elf32_arm_hash_table (info)->vxworks_p
20006 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
20007 flagsp, secp, valp))
20008 return FALSE;
20009
20010 return TRUE;
20011}
20012
0beaef2b 20013/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 20014const struct elf_size_info elf32_arm_size_info =
20015{
0beaef2b
PB		 20016 sizeof (Elf32_External_Ehdr),
20017 sizeof (Elf32_External_Phdr),
20018 sizeof (Elf32_External_Shdr),
20019 sizeof (Elf32_External_Rel),
20020 sizeof (Elf32_External_Rela),
20021 sizeof (Elf32_External_Sym),
20022 sizeof (Elf32_External_Dyn),
20023 sizeof (Elf_External_Note),
20024 4,
20025 1,
20026 32, 2,
20027 ELFCLASS32, EV_CURRENT,
20028 bfd_elf32_write_out_phdrs,
20029 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 20030 bfd_elf32_checksum_contents,
0beaef2b
PB		 20031 bfd_elf32_write_relocs,
20032 elf32_arm_swap_symbol_in,
20033 elf32_arm_swap_symbol_out,
20034 bfd_elf32_slurp_reloc_table,
20035 bfd_elf32_slurp_symbol_table,
20036 bfd_elf32_swap_dyn_in,
20037 bfd_elf32_swap_dyn_out,
20038 bfd_elf32_swap_reloc_in,
20039 bfd_elf32_swap_reloc_out,
20040 bfd_elf32_swap_reloca_in,
20041 bfd_elf32_swap_reloca_out
20042};
20043
685e70ae
VK		 20044static bfd_vma
20045read_code32 (const bfd *abfd, const bfd_byte *addr)
20046{
20047 /* V7 BE8 code is always little endian. */
20048 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
20049 return bfd_getl32 (addr);
20050
20051 return bfd_get_32 (abfd, addr);
20052}
20053
20054static bfd_vma
20055read_code16 (const bfd *abfd, const bfd_byte *addr)
20056{
20057 /* V7 BE8 code is always little endian. */
20058 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
20059 return bfd_getl16 (addr);
20060
20061 return bfd_get_16 (abfd, addr);
20062}
20063
6a631e86
YG		 20064/* Return size of plt0 entry starting at ADDR
20065 or (bfd_vma) -1 if size can not be determined. */
20066
20067static bfd_vma
20068elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
20069{
20070 bfd_vma first_word;
20071 bfd_vma plt0_size;
20072
685e70ae 20073 first_word = read_code32 (abfd, addr);
6a631e86
YG		 20074
20075 if (first_word == elf32_arm_plt0_entry[0])
20076 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
20077 else if (first_word == elf32_thumb2_plt0_entry[0])
20078 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
20079 else
20080 /* We don't yet handle this PLT format. */
20081 return (bfd_vma) -1;
20082
20083 return plt0_size;
20084}
20085
20086/* Return size of plt entry starting at offset OFFSET
20087 of plt section located at address START
20088 or (bfd_vma) -1 if size can not be determined. */
20089
20090static bfd_vma
20091elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
20092{
20093 bfd_vma first_insn;
20094 bfd_vma plt_size = 0;
20095 const bfd_byte *addr = start + offset;
20096
20097 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 20098 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 20099 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
20100
20101 /* Respect Thumb stub if necessary. */
685e70ae 20102 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 20103 {
20104 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
20105 }
20106
20107 /* Strip immediate from first add. */
685e70ae 20108 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 20109
20110#ifdef FOUR_WORD_PLT
20111 if (first_insn == elf32_arm_plt_entry[0])
20112 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
20113#else
20114 if (first_insn == elf32_arm_plt_entry_long[0])
20115 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
20116 else if (first_insn == elf32_arm_plt_entry_short[0])
20117 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
20118#endif
20119 else
20120 /* We don't yet handle this PLT format. */
20121 return (bfd_vma) -1;
20122
20123 return plt_size;
20124}
20125
20126/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
20127
20128static long
20129elf32_arm_get_synthetic_symtab (bfd *abfd,
20130 long symcount ATTRIBUTE_UNUSED,
20131 asymbol **syms ATTRIBUTE_UNUSED,
20132 long dynsymcount,
20133 asymbol **dynsyms,
20134 asymbol **ret)
20135{
20136 asection *relplt;
20137 asymbol *s;
20138 arelent *p;
20139 long count, i, n;
20140 size_t size;
20141 Elf_Internal_Shdr *hdr;
20142 char *names;
20143 asection *plt;
20144 bfd_vma offset;
20145 bfd_byte *data;
20146
20147 *ret = NULL;
20148
20149 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
20150 return 0;
20151
20152 if (dynsymcount <= 0)
20153 return 0;
20154
20155 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
20156 if (relplt == NULL)
20157 return 0;
20158
20159 hdr = &elf_section_data (relplt)->this_hdr;
20160 if (hdr->sh_link != elf_dynsymtab (abfd)
20161 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
20162 return 0;
20163
20164 plt = bfd_get_section_by_name (abfd, ".plt");
20165 if (plt == NULL)
20166 return 0;
20167
20168 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
20169 return -1;
20170
20171 data = plt->contents;
20172 if (data == NULL)
20173 {
20174 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
20175 return -1;
20176 bfd_cache_section_contents((asection *) plt, data);
20177 }
20178
20179 count = relplt->size / hdr->sh_entsize;
20180 size = count * sizeof (asymbol);
20181 p = relplt->relocation;
20182 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20183 {
20184 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
20185 if (p->addend != 0)
20186 size += sizeof ("+0x") - 1 + 8;
20187 }
20188
20189 s = *ret = (asymbol *) bfd_malloc (size);
20190 if (s == NULL)
20191 return -1;
20192
20193 offset = elf32_arm_plt0_size (abfd, data);
20194 if (offset == (bfd_vma) -1)
20195 return -1;
20196
20197 names = (char *) (s + count);
20198 p = relplt->relocation;
20199 n = 0;
20200 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20201 {
20202 size_t len;
20203
20204 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
20205 if (plt_size == (bfd_vma) -1)
20206 break;
20207
20208 *s = **p->sym_ptr_ptr;
20209 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20210 we are defining a symbol, ensure one of them is set. */
20211 if ((s->flags & BSF_LOCAL) == 0)
20212 s->flags |= BSF_GLOBAL;
20213 s->flags |= BSF_SYNTHETIC;
20214 s->section = plt;
20215 s->value = offset;
20216 s->name = names;
20217 s->udata.p = NULL;
20218 len = strlen ((*p->sym_ptr_ptr)->name);
20219 memcpy (names, (*p->sym_ptr_ptr)->name, len);
20220 names += len;
20221 if (p->addend != 0)
20222 {
20223 char buf[30], *a;
20224
20225 memcpy (names, "+0x", sizeof ("+0x") - 1);
20226 names += sizeof ("+0x") - 1;
20227 bfd_sprintf_vma (abfd, buf, p->addend);
20228 for (a = buf; *a == '0'; ++a)
20229 ;
20230 len = strlen (a);
20231 memcpy (names, a, len);
20232 names += len;
20233 }
20234 memcpy (names, "@plt", sizeof ("@plt"));
20235 names += sizeof ("@plt");
20236 ++s, ++n;
20237 offset += plt_size;
20238 }
20239
20240 return n;
20241}
20242
ac4c9b04 20243static bfd_boolean
8c803a2d 20244elf32_arm_section_flags (const Elf_Internal_Shdr *hdr)
ac4c9b04 20245{
f0728ee3 20246 if (hdr->sh_flags & SHF_ARM_PURECODE)
8c803a2d 20247 hdr->bfd_section->flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 20248 return TRUE;
20249}
20250
20251static flagword
20252elf32_arm_lookup_section_flags (char *flag_name)
20253{
f0728ee3
AV		 20254 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
20255 return SHF_ARM_PURECODE;
ac4c9b04
MG		 20256
20257 return SEC_NO_FLAGS;
20258}
20259
491d01d3
YU		 20260static unsigned int
20261elf32_arm_count_additional_relocs (asection *sec)
20262{
20263 struct _arm_elf_section_data *arm_data;
20264 arm_data = get_arm_elf_section_data (sec);
5025eb7c 20265
6342be70 20266 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 20267}
20268
5522f910 20269/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 20270 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 20271 FALSE otherwise. ISECTION is the best guess matching section from the
20272 input bfd IBFD, but it might be NULL. */
20273
20274static bfd_boolean
20275elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
20276 bfd *obfd ATTRIBUTE_UNUSED,
20277 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
20278 Elf_Internal_Shdr *osection)
20279{
20280 switch (osection->sh_type)
20281 {
20282 case SHT_ARM_EXIDX:
20283 {
20284 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
20285 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
20286 unsigned i = 0;
20287
20288 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
20289 osection->sh_info = 0;
20290
20291 /* The sh_link field must be set to the text section associated with
20292 this index section. Unfortunately the ARM EHABI does not specify
20293 exactly how to determine this association. Our caller does try
20294 to match up OSECTION with its corresponding input section however
20295 so that is a good first guess. */
20296 if (isection != NULL
20297 && osection->bfd_section != NULL
20298 && isection->bfd_section != NULL
20299 && isection->bfd_section->output_section != NULL
20300 && isection->bfd_section->output_section == osection->bfd_section
20301 && iheaders != NULL
20302 && isection->sh_link > 0
20303 && isection->sh_link < elf_numsections (ibfd)
20304 && iheaders[isection->sh_link]->bfd_section != NULL
20305 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
20306 )
20307 {
20308 for (i = elf_numsections (obfd); i-- > 0;)
20309 if (oheaders[i]->bfd_section
20310 == iheaders[isection->sh_link]->bfd_section->output_section)
20311 break;
20312 }
9eaff861 20313
5522f910
NC		 20314 if (i == 0)
20315 {
20316 /* Failing that we have to find a matching section ourselves. If
20317 we had the output section name available we could compare that
20318 with input section names. Unfortunately we don't. So instead
20319 we use a simple heuristic and look for the nearest executable
20320 section before this one. */
20321 for (i = elf_numsections (obfd); i-- > 0;)
20322 if (oheaders[i] == osection)
20323 break;
20324 if (i == 0)
20325 break;
20326
20327 while (i-- > 0)
20328 if (oheaders[i]->sh_type == SHT_PROGBITS
20329 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
20330 == (SHF_ALLOC | SHF_EXECINSTR))
20331 break;
20332 }
20333
20334 if (i)
20335 {
20336 osection->sh_link = i;
20337 /* If the text section was part of a group
20338 then the index section should be too. */
20339 if (oheaders[i]->sh_flags & SHF_GROUP)
20340 osection->sh_flags |= SHF_GROUP;
20341 return TRUE;
20342 }
20343 }
20344 break;
20345
20346 case SHT_ARM_PREEMPTMAP:
20347 osection->sh_flags = SHF_ALLOC;
20348 break;
20349
20350 case SHT_ARM_ATTRIBUTES:
20351 case SHT_ARM_DEBUGOVERLAY:
20352 case SHT_ARM_OVERLAYSECTION:
20353 default:
20354 break;
20355 }
20356
20357 return FALSE;
20358}
20359
d691934d
NC		 20360/* Returns TRUE if NAME is an ARM mapping symbol.
20361 Traditionally the symbols $a, $d and $t have been used.
20362 The ARM ELF standard also defines $x (for A64 code). It also allows a
20363 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20364 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20365 not support them here. $t.x indicates the start of ThumbEE instructions. */
20366
20367static bfd_boolean
20368is_arm_mapping_symbol (const char * name)
20369{
20370 return name != NULL /* Paranoia. */
20371 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
20372 the mapping symbols could have acquired a prefix.
20373 We do not support this here, since such symbols no
20374 longer conform to the ARM ELF ABI. */
20375 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
20376 && (name[2] == 0 || name[2] == '.');
20377 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20378 any characters that follow the period are legal characters for the body
20379 of a symbol's name. For now we just assume that this is the case. */
20380}
20381
fca2a38f
NC		 20382/* Make sure that mapping symbols in object files are not removed via the
20383 "strip --strip-unneeded" tool. These symbols are needed in order to
20384 correctly generate interworking veneers, and for byte swapping code
20385 regions. Once an object file has been linked, it is safe to remove the
20386 symbols as they will no longer be needed. */
20387
20388static void
20389elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
20390{
20391 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 20392 && sym->section != bfd_abs_section_ptr
d691934d 20393 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 20394 sym->flags |= BSF_KEEP;
20395}
20396
5522f910
NC		 20397#undef elf_backend_copy_special_section_fields
20398#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20399
252b5132 20400#define ELF_ARCH bfd_arch_arm
ae95ffa6 20401#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 20402#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 20403#ifdef __QNXTARGET__
20404#define ELF_MAXPAGESIZE 0x1000
20405#else
7572ca89 20406#define ELF_MAXPAGESIZE 0x10000
d0facd1b 20407#endif
b1342370 20408#define ELF_MINPAGESIZE 0x1000
24718e3b 20409#define ELF_COMMONPAGESIZE 0x1000
252b5132 20410
07d6d2b8 20411#define bfd_elf32_mkobject elf32_arm_mkobject
ba93b8ac 20412
99e4ae17
AJ		 20413#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20414#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 20415#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20416#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
07d6d2b8 20417#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 20418#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 20419#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
07d6d2b8 20420#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 20421#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 20422#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 20423#define bfd_elf32_bfd_final_link elf32_arm_final_link
07d6d2b8 20424#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132 20425
07d6d2b8 20426#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
e7679060 20427#define elf_backend_maybe_function_sym elf32_arm_maybe_function_sym
07d6d2b8 20428#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 20429#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
07d6d2b8 20430#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 20431#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 20432#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 20433#define elf_backend_write_section elf32_arm_write_section
252b5132 20434#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
07d6d2b8 20435#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 20436#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20437#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20438#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 20439#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 20440#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ed7e9d0b 20441#define elf_backend_init_file_header elf32_arm_init_file_header
99e4ae17 20442#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 20443#define elf_backend_object_p elf32_arm_object_p
07d6d2b8
AM		 20444#define elf_backend_fake_sections elf32_arm_fake_sections
20445#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20446#define elf_backend_final_write_processing elf32_arm_final_write_processing
20447#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 20448#define elf_backend_size_info elf32_arm_size_info
b294bdf8 20449#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
07d6d2b8
AM		 20450#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20451#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 20452#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
07d6d2b8 20453#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 20454#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 20455#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 20456#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 20457
20458#define elf_backend_can_refcount 1
20459#define elf_backend_can_gc_sections 1
20460#define elf_backend_plt_readonly 1
20461#define elf_backend_want_got_plt 1
20462#define elf_backend_want_plt_sym 0
5474d94f 20463#define elf_backend_want_dynrelro 1
906e58ca
NC		 20464#define elf_backend_may_use_rel_p 1
20465#define elf_backend_may_use_rela_p 0
4e7fd91e 20466#define elf_backend_default_use_rela_p 0
64f52338 20467#define elf_backend_dtrel_excludes_plt 1
252b5132 20468
04f7c78d 20469#define elf_backend_got_header_size 12
b68a20d6 20470#define elf_backend_extern_protected_data 1
04f7c78d 20471
07d6d2b8 20472#undef elf_backend_obj_attrs_vendor
906e58ca 20473#define elf_backend_obj_attrs_vendor "aeabi"
07d6d2b8 20474#undef elf_backend_obj_attrs_section
906e58ca 20475#define elf_backend_obj_attrs_section ".ARM.attributes"
07d6d2b8 20476#undef elf_backend_obj_attrs_arg_type
906e58ca 20477#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
07d6d2b8 20478#undef elf_backend_obj_attrs_section_type
104d59d1 20479#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb 20480#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
07d6d2b8 20481#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 20482
07d6d2b8 20483#undef elf_backend_section_flags
ac4c9b04 20484#define elf_backend_section_flags elf32_arm_section_flags
07d6d2b8
AM		 20485#undef elf_backend_lookup_section_flags_hook
20486#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
ac4c9b04 20487
a2f63b2e
MR		 20488#define elf_backend_linux_prpsinfo32_ugid16 TRUE
20489
252b5132 20490#include "elf32-target.h"
7f266840 20491
b38cadfb
NC		 20492/* Native Client targets. */
20493
20494#undef TARGET_LITTLE_SYM
6d00b590 20495#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 20496#undef TARGET_LITTLE_NAME
20497#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
20498#undef TARGET_BIG_SYM
6d00b590 20499#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 20500#undef TARGET_BIG_NAME
20501#define TARGET_BIG_NAME "elf32-bigarm-nacl"
20502
20503/* Like elf32_arm_link_hash_table_create -- but overrides
20504 appropriately for NaCl. */
20505
20506static struct bfd_link_hash_table *
20507elf32_arm_nacl_link_hash_table_create (bfd *abfd)
20508{
20509 struct bfd_link_hash_table *ret;
20510
20511 ret = elf32_arm_link_hash_table_create (abfd);
20512 if (ret)
20513 {
20514 struct elf32_arm_link_hash_table *htab
20515 = (struct elf32_arm_link_hash_table *) ret;
20516
20517 htab->nacl_p = 1;
20518
20519 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
20520 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
20521 }
20522 return ret;
20523}
20524
20525/* Since NaCl doesn't use the ARM-specific unwind format, we don't
20526 really need to use elf32_arm_modify_segment_map. But we do it
20527 anyway just to reduce gratuitous differences with the stock ARM backend. */
20528
20529static bfd_boolean
20530elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
20531{
20532 return (elf32_arm_modify_segment_map (abfd, info)
20533 && nacl_modify_segment_map (abfd, info));
20534}
20535
cc364be6
AM		 20536static bfd_boolean
20537elf32_arm_nacl_final_write_processing (bfd *abfd)
887badb3 20538{
cc364be6
AM		 20539 arm_final_write_processing (abfd);
20540 return nacl_final_write_processing (abfd);
887badb3
RM		 20541}
20542
6a631e86
YG		 20543static bfd_vma
20544elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
20545 const arelent *rel ATTRIBUTE_UNUSED)
20546{
20547 return plt->vma
20548 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
20549 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
20550}
887badb3 20551
b38cadfb 20552#undef elf32_bed
6a631e86 20553#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 20554#undef bfd_elf32_bfd_link_hash_table_create
20555#define bfd_elf32_bfd_link_hash_table_create \
20556 elf32_arm_nacl_link_hash_table_create
20557#undef elf_backend_plt_alignment
6a631e86 20558#define elf_backend_plt_alignment 4
b38cadfb
NC		 20559#undef elf_backend_modify_segment_map
20560#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
6d6c25c8
AM		 20561#undef elf_backend_modify_headers
20562#define elf_backend_modify_headers nacl_modify_headers
887badb3
RM		 20563#undef elf_backend_final_write_processing
20564#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 20565#undef bfd_elf32_get_synthetic_symtab
20566#undef elf_backend_plt_sym_val
20567#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 20568#undef elf_backend_copy_special_section_fields
b38cadfb 20569
887badb3
RM		 20570#undef ELF_MINPAGESIZE
20571#undef ELF_COMMONPAGESIZE
20572
b38cadfb
NC		 20573
20574#include "elf32-target.h"
20575
20576/* Reset to defaults. */
20577#undef elf_backend_plt_alignment
20578#undef elf_backend_modify_segment_map
20579#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
6d6c25c8 20580#undef elf_backend_modify_headers
887badb3
RM		 20581#undef elf_backend_final_write_processing
20582#define elf_backend_final_write_processing elf32_arm_final_write_processing
20583#undef ELF_MINPAGESIZE
20584#define ELF_MINPAGESIZE 0x1000
20585#undef ELF_COMMONPAGESIZE
20586#define ELF_COMMONPAGESIZE 0x1000
20587
b38cadfb 20588
617a5ada
CL		 20589/* FDPIC Targets. */
20590
20591#undef TARGET_LITTLE_SYM
20592#define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20593#undef TARGET_LITTLE_NAME
20594#define TARGET_LITTLE_NAME "elf32-littlearm-fdpic"
20595#undef TARGET_BIG_SYM
20596#define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20597#undef TARGET_BIG_NAME
20598#define TARGET_BIG_NAME "elf32-bigarm-fdpic"
20599#undef elf_match_priority
20600#define elf_match_priority 128
18a20338
CL		 20601#undef ELF_OSABI
20602#define ELF_OSABI ELFOSABI_ARM_FDPIC
617a5ada
CL		 20603
20604/* Like elf32_arm_link_hash_table_create -- but overrides
20605 appropriately for FDPIC. */
20606
20607static struct bfd_link_hash_table *
20608elf32_arm_fdpic_link_hash_table_create (bfd *abfd)
20609{
20610 struct bfd_link_hash_table *ret;
20611
20612 ret = elf32_arm_link_hash_table_create (abfd);
20613 if (ret)
20614 {
20615 struct elf32_arm_link_hash_table *htab = (struct elf32_arm_link_hash_table *) ret;
20616
20617 htab->fdpic_p = 1;
20618 }
20619 return ret;
20620}
20621
e8b09b87
CL		 20622/* We need dynamic symbols for every section, since segments can
20623 relocate independently. */
20624static bfd_boolean
20625elf32_arm_fdpic_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
20626 struct bfd_link_info *info
20627 ATTRIBUTE_UNUSED,
20628 asection *p ATTRIBUTE_UNUSED)
20629{
20630 switch (elf_section_data (p)->this_hdr.sh_type)
20631 {
20632 case SHT_PROGBITS:
20633 case SHT_NOBITS:
20634 /* If sh_type is yet undecided, assume it could be
20635 SHT_PROGBITS/SHT_NOBITS. */
20636 case SHT_NULL:
20637 return FALSE;
20638
20639 /* There shouldn't be section relative relocations
20640 against any other section. */
20641 default:
20642 return TRUE;
20643 }
20644}
20645
617a5ada
CL		 20646#undef elf32_bed
20647#define elf32_bed elf32_arm_fdpic_bed
20648
20649#undef bfd_elf32_bfd_link_hash_table_create
4b24dd1a 20650#define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
617a5ada 20651
e8b09b87
CL		 20652#undef elf_backend_omit_section_dynsym
20653#define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20654
617a5ada 20655#include "elf32-target.h"
e8b09b87 20656
617a5ada 20657#undef elf_match_priority
18a20338 20658#undef ELF_OSABI
e8b09b87 20659#undef elf_backend_omit_section_dynsym
617a5ada 20660
906e58ca 20661/* VxWorks Targets. */
4e7fd91e 20662
07d6d2b8
AM		 20663#undef TARGET_LITTLE_SYM
20664#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20665#undef TARGET_LITTLE_NAME
20666#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
20667#undef TARGET_BIG_SYM
20668#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20669#undef TARGET_BIG_NAME
20670#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
4e7fd91e
PB		 20671
20672/* Like elf32_arm_link_hash_table_create -- but overrides
20673 appropriately for VxWorks. */
906e58ca 20674
4e7fd91e
PB		 20675static struct bfd_link_hash_table *
20676elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
20677{
20678 struct bfd_link_hash_table *ret;
20679
20680 ret = elf32_arm_link_hash_table_create (abfd);
20681 if (ret)
20682 {
20683 struct elf32_arm_link_hash_table *htab
00a97672 20684 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 20685 htab->use_rel = 0;
00a97672 20686 htab->vxworks_p = 1;
4e7fd91e
PB		 20687 }
20688 return ret;
906e58ca 20689}
4e7fd91e 20690
cc364be6
AM		 20691static bfd_boolean
20692elf32_arm_vxworks_final_write_processing (bfd *abfd)
00a97672 20693{
cc364be6
AM		 20694 arm_final_write_processing (abfd);
20695 return elf_vxworks_final_write_processing (abfd);
00a97672
RS		 20696}
20697
906e58ca 20698#undef elf32_bed
4e7fd91e
PB		 20699#define elf32_bed elf32_arm_vxworks_bed
20700
906e58ca
NC		 20701#undef bfd_elf32_bfd_link_hash_table_create
20702#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 20703#undef elf_backend_final_write_processing
20704#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20705#undef elf_backend_emit_relocs
9eaff861 20706#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 20707
906e58ca 20708#undef elf_backend_may_use_rel_p
00a97672 20709#define elf_backend_may_use_rel_p 0
906e58ca 20710#undef elf_backend_may_use_rela_p
00a97672 20711#define elf_backend_may_use_rela_p 1
906e58ca 20712#undef elf_backend_default_use_rela_p
00a97672 20713#define elf_backend_default_use_rela_p 1
906e58ca 20714#undef elf_backend_want_plt_sym
00a97672 20715#define elf_backend_want_plt_sym 1
906e58ca 20716#undef ELF_MAXPAGESIZE
00a97672 20717#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 20718
20719#include "elf32-target.h"
20720
20721
21d799b5
NC		 20722/* Merge backend specific data from an object file to the output
20723 object file when linking. */
20724
20725static bfd_boolean
50e03d47 20726elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 20727{
50e03d47 20728 bfd *obfd = info->output_bfd;
21d799b5
NC		 20729 flagword out_flags;
20730 flagword in_flags;
20731 bfd_boolean flags_compatible = TRUE;
20732 asection *sec;
20733
cc643b88 20734 /* Check if we have the same endianness. */
50e03d47 20735 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 20736 return FALSE;
20737
20738 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
20739 return TRUE;
20740
50e03d47 20741 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 20742 return FALSE;
20743
20744 /* The input BFD must have had its flags initialised. */
20745 /* The following seems bogus to me -- The flags are initialized in
20746 the assembler but I don't think an elf_flags_init field is
20747 written into the object. */
20748 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20749
20750 in_flags = elf_elfheader (ibfd)->e_flags;
20751 out_flags = elf_elfheader (obfd)->e_flags;
20752
20753 /* In theory there is no reason why we couldn't handle this. However
20754 in practice it isn't even close to working and there is no real
20755 reason to want it. */
20756 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
20757 && !(ibfd->flags & DYNAMIC)
20758 && (in_flags & EF_ARM_BE8))
20759 {
871b3ab2 20760 _bfd_error_handler (_("error: %pB is already in final BE8 format"),
21d799b5
NC		 20761 ibfd);
20762 return FALSE;
20763 }
20764
20765 if (!elf_flags_init (obfd))
20766 {
20767 /* If the input is the default architecture and had the default
20768 flags then do not bother setting the flags for the output
20769 architecture, instead allow future merges to do this. If no
20770 future merges ever set these flags then they will retain their
99059e56
RM		 20771 uninitialised values, which surprise surprise, correspond
20772 to the default values. */
21d799b5
NC		 20773 if (bfd_get_arch_info (ibfd)->the_default
20774 && elf_elfheader (ibfd)->e_flags == 0)
20775 return TRUE;
20776
20777 elf_flags_init (obfd) = TRUE;
20778 elf_elfheader (obfd)->e_flags = in_flags;
20779
20780 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
20781 && bfd_get_arch_info (obfd)->the_default)
20782 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
20783
20784 return TRUE;
20785 }
20786
20787 /* Determine what should happen if the input ARM architecture
20788 does not match the output ARM architecture. */
20789 if (! bfd_arm_merge_machines (ibfd, obfd))
20790 return FALSE;
20791
20792 /* Identical flags must be compatible. */
20793 if (in_flags == out_flags)
20794 return TRUE;
20795
20796 /* Check to see if the input BFD actually contains any sections. If
20797 not, its flags may not have been initialised either, but it
20798 cannot actually cause any incompatiblity. Do not short-circuit
20799 dynamic objects; their section list may be emptied by
20800 elf_link_add_object_symbols.
20801
20802 Also check to see if there are no code sections in the input.
20803 In this case there is no need to check for code specific flags.
20804 XXX - do we need to worry about floating-point format compatability
20805 in data sections ? */
20806 if (!(ibfd->flags & DYNAMIC))
20807 {
20808 bfd_boolean null_input_bfd = TRUE;
20809 bfd_boolean only_data_sections = TRUE;
20810
20811 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
20812 {
20813 /* Ignore synthetic glue sections. */
20814 if (strcmp (sec->name, ".glue_7")
20815 && strcmp (sec->name, ".glue_7t"))
20816 {
fd361982 20817 if ((bfd_section_flags (sec)
21d799b5
NC		 20818 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
20819 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 20820 only_data_sections = FALSE;
21d799b5
NC		 20821
20822 null_input_bfd = FALSE;
20823 break;
20824 }
20825 }
20826
20827 if (null_input_bfd || only_data_sections)
20828 return TRUE;
20829 }
20830
20831 /* Complain about various flag mismatches. */
20832 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
20833 EF_ARM_EABI_VERSION (out_flags)))
20834 {
20835 _bfd_error_handler
90b6238f 20836 (_("error: source object %pB has EABI version %d, but target %pB has EABI version %d"),
c08bb8dd
AM		 20837 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
20838 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 20839 return FALSE;
20840 }
20841
20842 /* Not sure what needs to be checked for EABI versions >= 1. */
20843 /* VxWorks libraries do not use these flags. */
20844 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
20845 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
20846 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
20847 {
20848 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
20849 {
20850 _bfd_error_handler
871b3ab2 20851 (_("error: %pB is compiled for APCS-%d, whereas target %pB uses APCS-%d"),
c08bb8dd
AM		 20852 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
20853 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 20854 flags_compatible = FALSE;
20855 }
20856
20857 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
20858 {
20859 if (in_flags & EF_ARM_APCS_FLOAT)
20860 _bfd_error_handler
871b3ab2 20861 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
21d799b5
NC		 20862 ibfd, obfd);
20863 else
20864 _bfd_error_handler
871b3ab2 20865 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
21d799b5
NC		 20866 ibfd, obfd);
20867
20868 flags_compatible = FALSE;
20869 }
20870
20871 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
20872 {
20873 if (in_flags & EF_ARM_VFP_FLOAT)
20874 _bfd_error_handler
90b6238f
AM		 20875 (_("error: %pB uses %s instructions, whereas %pB does not"),
20876 ibfd, "VFP", obfd);
21d799b5
NC		 20877 else
20878 _bfd_error_handler
90b6238f
AM		 20879 (_("error: %pB uses %s instructions, whereas %pB does not"),
20880 ibfd, "FPA", obfd);
21d799b5
NC		 20881
20882 flags_compatible = FALSE;
20883 }
20884
20885 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
20886 {
20887 if (in_flags & EF_ARM_MAVERICK_FLOAT)
20888 _bfd_error_handler
90b6238f
AM		 20889 (_("error: %pB uses %s instructions, whereas %pB does not"),
20890 ibfd, "Maverick", obfd);
21d799b5
NC		 20891 else
20892 _bfd_error_handler
90b6238f
AM		 20893 (_("error: %pB does not use %s instructions, whereas %pB does"),
20894 ibfd, "Maverick", obfd);
21d799b5
NC		 20895
20896 flags_compatible = FALSE;
20897 }
20898
20899#ifdef EF_ARM_SOFT_FLOAT
20900 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
20901 {
20902 /* We can allow interworking between code that is VFP format
20903 layout, and uses either soft float or integer regs for
20904 passing floating point arguments and results. We already
20905 know that the APCS_FLOAT flags match; similarly for VFP
20906 flags. */
20907 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
20908 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
20909 {
20910 if (in_flags & EF_ARM_SOFT_FLOAT)
20911 _bfd_error_handler
871b3ab2 20912 (_("error: %pB uses software FP, whereas %pB uses hardware FP"),
21d799b5
NC		 20913 ibfd, obfd);
20914 else
20915 _bfd_error_handler
871b3ab2 20916 (_("error: %pB uses hardware FP, whereas %pB uses software FP"),
21d799b5
NC		 20917 ibfd, obfd);
20918
20919 flags_compatible = FALSE;
20920 }
20921 }
20922#endif
20923
20924 /* Interworking mismatch is only a warning. */
20925 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
20926 {
20927 if (in_flags & EF_ARM_INTERWORK)
20928 {
20929 _bfd_error_handler
90b6238f 20930 (_("warning: %pB supports interworking, whereas %pB does not"),
21d799b5
NC		 20931 ibfd, obfd);
20932 }
20933 else
20934 {
20935 _bfd_error_handler
90b6238f 20936 (_("warning: %pB does not support interworking, whereas %pB does"),
21d799b5
NC		 20937 ibfd, obfd);
20938 }
20939 }
20940 }
20941
20942 return flags_compatible;
20943}
20944
20945
906e58ca 20946/* Symbian OS Targets. */
7f266840 20947
07d6d2b8
AM		 20948#undef TARGET_LITTLE_SYM
20949#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
20950#undef TARGET_LITTLE_NAME
20951#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
20952#undef TARGET_BIG_SYM
20953#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
20954#undef TARGET_BIG_NAME
20955#define TARGET_BIG_NAME "elf32-bigarm-symbian"
7f266840
DJ		 20956
20957/* Like elf32_arm_link_hash_table_create -- but overrides
20958 appropriately for Symbian OS. */
906e58ca 20959
7f266840
DJ		 20960static struct bfd_link_hash_table *
20961elf32_arm_symbian_link_hash_table_create (bfd *abfd)
20962{
20963 struct bfd_link_hash_table *ret;
20964
20965 ret = elf32_arm_link_hash_table_create (abfd);
20966 if (ret)
20967 {
20968 struct elf32_arm_link_hash_table *htab
20969 = (struct elf32_arm_link_hash_table *)ret;
20970 /* There is no PLT header for Symbian OS. */
20971 htab->plt_header_size = 0;
95720a86
DJ		 20972 /* The PLT entries are each one instruction and one word. */
20973 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 20974 htab->symbian_p = 1;
33bfe774
JB		 20975 /* Symbian uses armv5t or above, so use_blx is always true. */
20976 htab->use_blx = 1;
67687978 20977 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 20978 }
20979 return ret;
906e58ca 20980}
7f266840 20981
b35d266b 20982static const struct bfd_elf_special_section
551b43fd 20983elf32_arm_symbian_special_sections[] =
7f266840 20984{
5cd3778d
MM		 20985 /* In a BPABI executable, the dynamic linking sections do not go in
20986 the loadable read-only segment. The post-linker may wish to
20987 refer to these sections, but they are not part of the final
20988 program image. */
07d6d2b8
AM		 20989 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
20990 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
20991 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
20992 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
20993 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 20994 /* These sections do not need to be writable as the SymbianOS
20995 postlinker will arrange things so that no dynamic relocation is
20996 required. */
07d6d2b8
AM		 20997 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
20998 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
0112cd26 20999 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
07d6d2b8 21000 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 21001};
21002
c3c76620 21003static void
906e58ca 21004elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 21005 struct bfd_link_info *link_info)
c3c76620
MM		 21006{
21007 /* BPABI objects are never loaded directly by an OS kernel; they are
21008 processed by a postlinker first, into an OS-specific format. If
21009 the D_PAGED bit is set on the file, BFD will align segments on
21010 page boundaries, so that an OS can directly map the file. With
21011 BPABI objects, that just results in wasted space. In addition,
21012 because we clear the D_PAGED bit, map_sections_to_segments will
21013 recognize that the program headers should not be mapped into any
21014 loadable segment. */
21015 abfd->flags &= ~D_PAGED;
906e58ca 21016 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 21017}
7f266840
DJ		 21018
21019static bfd_boolean
906e58ca 21020elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 21021 struct bfd_link_info *info)
7f266840
DJ		 21022{
21023 struct elf_segment_map *m;
21024 asection *dynsec;
21025
7f266840
DJ		 21026 /* BPABI shared libraries and executables should have a PT_DYNAMIC
21027 segment. However, because the .dynamic section is not marked
21028 with SEC_LOAD, the generic ELF code will not create such a
21029 segment. */
21030 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
21031 if (dynsec)
21032 {
12bd6957 21033 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 21034 if (m->p_type == PT_DYNAMIC)
21035 break;
21036
21037 if (m == NULL)
21038 {
21039 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 21040 m->next = elf_seg_map (abfd);
21041 elf_seg_map (abfd) = m;
8ded5a0f 21042 }
7f266840
DJ		 21043 }
21044
b294bdf8
MM		 21045 /* Also call the generic arm routine. */
21046 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 21047}
21048
95720a86
DJ		 21049/* Return address for Ith PLT stub in section PLT, for relocation REL
21050 or (bfd_vma) -1 if it should not be included. */
21051
21052static bfd_vma
21053elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
21054 const arelent *rel ATTRIBUTE_UNUSED)
21055{
21056 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
21057}
21058
8029a119 21059#undef elf32_bed
7f266840
DJ		 21060#define elf32_bed elf32_arm_symbian_bed
21061
21062/* The dynamic sections are not allocated on SymbianOS; the postlinker
21063 will process them and then discard them. */
906e58ca 21064#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 21065#define ELF_DYNAMIC_SEC_FLAGS \
21066 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
21067
9eaff861 21068#undef elf_backend_emit_relocs
c3c76620 21069
906e58ca
NC		 21070#undef bfd_elf32_bfd_link_hash_table_create
21071#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
21072#undef elf_backend_special_sections
07d6d2b8 21073#define elf_backend_special_sections elf32_arm_symbian_special_sections
906e58ca
NC		 21074#undef elf_backend_begin_write_processing
21075#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
21076#undef elf_backend_final_write_processing
21077#define elf_backend_final_write_processing elf32_arm_final_write_processing
21078
21079#undef elf_backend_modify_segment_map
7f266840
DJ		 21080#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
21081
21082/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 21083#undef elf_backend_got_header_size
7f266840
DJ		 21084#define elf_backend_got_header_size 0
21085
21086/* Similarly, there is no .got.plt section. */
906e58ca 21087#undef elf_backend_want_got_plt
7f266840
DJ		 21088#define elf_backend_want_got_plt 0
21089
906e58ca 21090#undef elf_backend_plt_sym_val
95720a86
DJ		 21091#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
21092
906e58ca 21093#undef elf_backend_may_use_rel_p
00a97672 21094#define elf_backend_may_use_rel_p 1
906e58ca 21095#undef elf_backend_may_use_rela_p
00a97672 21096#define elf_backend_may_use_rela_p 0
906e58ca 21097#undef elf_backend_default_use_rela_p
00a97672 21098#define elf_backend_default_use_rela_p 0
906e58ca 21099#undef elf_backend_want_plt_sym
00a97672 21100#define elf_backend_want_plt_sym 0
64f52338
AM		 21101#undef elf_backend_dtrel_excludes_plt
21102#define elf_backend_dtrel_excludes_plt 0
906e58ca 21103#undef ELF_MAXPAGESIZE
00a97672 21104#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 21105
7f266840 21106#include "elf32-target.h"
GDB Binutils - Deliverables
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