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[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
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252b5132 1/* 32-bit ELF support for ARM
219d1afa 2 Copyright (C) 1998-2018 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
07d6d2b8
AM		 59#define elf_info_to_howto 0
60#define elf_info_to_howto_rel elf32_arm_info_to_howto
7f266840
DJ		 61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
07d6d2b8 240 HOWTO (R_ARM_THM_PC8, /* type */
7f266840
DJ		 241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
07d6d2b8
AM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
99059e56
RM		 334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
07d6d2b8 340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
07d6d2b8
AM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
99059e56
RM		 348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
07d6d2b8 354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
07d6d2b8
AM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
99059e56
RM		 362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
07d6d2b8 368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
07d6d2b8
AM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
99059e56
RM		 378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
07d6d2b8 384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
07d6d2b8
AM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
99059e56
RM		 392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
07d6d2b8 398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
07d6d2b8
AM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
99059e56
RM		 406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
07d6d2b8 412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
07d6d2b8
AM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
99059e56
RM		 420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
07d6d2b8 426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
07d6d2b8
AM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
99059e56
RM		 434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
07d6d2b8 440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
07d6d2b8
AM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
99059e56 446 TRUE, /* pc_relative */
07d6d2b8 447 0, /* bitpos */
99059e56
RM		 448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
07d6d2b8
AM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
99059e56 460 FALSE, /* pc_relative */
07d6d2b8 461 0, /* bitpos */
99059e56
RM		 462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
07d6d2b8
AM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
99059e56 474 TRUE, /* pc_relative */
07d6d2b8 475 0, /* bitpos */
99059e56
RM		 476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
07d6d2b8 909 HOWTO (R_ARM_ALU_PC_G0, /* type */
4962c51a
MS		 910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 917 "R_ARM_ALU_PC_G0", /* name */
4962c51a
MS		 918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
07d6d2b8 937 HOWTO (R_ARM_ALU_PC_G1, /* type */
4962c51a
MS		 938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 945 "R_ARM_ALU_PC_G1", /* name */
4962c51a
MS		 946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
07d6d2b8 951 HOWTO (R_ARM_ALU_PC_G2, /* type */
4962c51a
MS		 952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 959 "R_ARM_ALU_PC_G2", /* name */
4962c51a
MS		 960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
07d6d2b8 965 HOWTO (R_ARM_LDR_PC_G1, /* type */
4962c51a
MS		 966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 973 "R_ARM_LDR_PC_G1", /* name */
4962c51a
MS		 974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
07d6d2b8 979 HOWTO (R_ARM_LDR_PC_G2, /* type */
4962c51a
MS		 980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 987 "R_ARM_LDR_PC_G2", /* name */
4962c51a
MS		 988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
07d6d2b8 993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
4962c51a
MS		 994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1001 "R_ARM_LDRS_PC_G0", /* name */
4962c51a
MS		 1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
07d6d2b8 1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
4962c51a
MS		 1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1015 "R_ARM_LDRS_PC_G1", /* name */
4962c51a
MS		 1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
07d6d2b8 1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
4962c51a
MS		 1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1029 "R_ARM_LDRS_PC_G2", /* name */
4962c51a
MS		 1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
07d6d2b8 1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
4962c51a
MS		 1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1043 "R_ARM_LDC_PC_G0", /* name */
4962c51a
MS		 1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
07d6d2b8 1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
4962c51a
MS		 1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1057 "R_ARM_LDC_PC_G1", /* name */
4962c51a
MS		 1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
07d6d2b8 1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
4962c51a
MS		 1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1071 "R_ARM_LDC_PC_G2", /* name */
4962c51a
MS		 1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
07d6d2b8 1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
4962c51a
MS		 1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1085 "R_ARM_ALU_SB_G0_NC", /* name */
4962c51a
MS		 1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
07d6d2b8 1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
4962c51a
MS		 1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1099 "R_ARM_ALU_SB_G0", /* name */
4962c51a
MS		 1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
07d6d2b8 1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
4962c51a
MS		 1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1113 "R_ARM_ALU_SB_G1_NC", /* name */
4962c51a
MS		 1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
07d6d2b8 1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
4962c51a
MS		 1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1127 "R_ARM_ALU_SB_G1", /* name */
4962c51a
MS		 1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
07d6d2b8 1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
4962c51a
MS		 1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1141 "R_ARM_ALU_SB_G2", /* name */
4962c51a
MS		 1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
07d6d2b8 1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
4962c51a
MS		 1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1155 "R_ARM_LDR_SB_G0", /* name */
4962c51a
MS		 1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
07d6d2b8 1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
4962c51a
MS		 1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1169 "R_ARM_LDR_SB_G1", /* name */
4962c51a
MS		 1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
07d6d2b8 1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
4962c51a
MS		 1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1183 "R_ARM_LDR_SB_G2", /* name */
4962c51a
MS		 1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
07d6d2b8 1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
4962c51a
MS		 1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1197 "R_ARM_LDRS_SB_G0", /* name */
4962c51a
MS		 1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
07d6d2b8 1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
4962c51a
MS		 1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1211 "R_ARM_LDRS_SB_G1", /* name */
4962c51a
MS		 1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
07d6d2b8 1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
4962c51a
MS		 1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1225 "R_ARM_LDRS_SB_G2", /* name */
4962c51a
MS		 1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
07d6d2b8 1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
4962c51a
MS		 1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1239 "R_ARM_LDC_SB_G0", /* name */
4962c51a
MS		 1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
07d6d2b8 1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
4962c51a
MS		 1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1253 "R_ARM_LDC_SB_G1", /* name */
4962c51a
MS		 1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
07d6d2b8 1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
4962c51a
MS		 1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
07d6d2b8 1267 "R_ARM_LDC_SB_G2", /* name */
4962c51a
MS		 1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
07d6d2b8 1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
c19d1205
ZW		 1486
1487 /* GNU extension to record C++ vtable member usage */
07d6d2b8
AM		 1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
99059e56 1494 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8
AM		 1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
07d6d2b8
AM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
99059e56 1509 complain_overflow_dont, /* complain_on_overflow */
07d6d2b8 1510 NULL, /* special_function */
99059e56 1511 "R_ARM_GNU_VTINHERIT", /* name */
07d6d2b8
AM		 1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
07d6d2b8
AM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
99059e56
RM		 1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
07d6d2b8 1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
07d6d2b8
AM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
99059e56
RM		 1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
07d6d2b8 1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
07d6d2b8
AM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
99059e56
RM		 1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
07d6d2b8 1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
07d6d2b8
AM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
99059e56
RM		 1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
07d6d2b8 1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
07d6d2b8
AM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
99059e56 1608 complain_overflow_bitfield,/* complain_on_overflow */
07d6d2b8 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
07d6d2b8 1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92
RS		 1748/* 160 onwards: */
1749static reloc_howto_type elf32_arm_howto_table_2[1] =
1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
07d6d2b8
AM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
99059e56
RM		 1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
1763 FALSE) /* pcrel_offset */
34e77a92 1764};
c19d1205 1765
34e77a92
RS		 1766/* 249-255 extended, currently unused, relocations: */
1767static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1768{
1769 HOWTO (R_ARM_RREL32, /* type */
1770 0, /* rightshift */
1771 0, /* size (0 = byte, 1 = short, 2 = long) */
1772 0, /* bitsize */
1773 FALSE, /* pc_relative */
1774 0, /* bitpos */
1775 complain_overflow_dont,/* complain_on_overflow */
1776 bfd_elf_generic_reloc, /* special_function */
1777 "R_ARM_RREL32", /* name */
1778 FALSE, /* partial_inplace */
1779 0, /* src_mask */
1780 0, /* dst_mask */
1781 FALSE), /* pcrel_offset */
1782
1783 HOWTO (R_ARM_RABS32, /* type */
1784 0, /* rightshift */
1785 0, /* size (0 = byte, 1 = short, 2 = long) */
1786 0, /* bitsize */
1787 FALSE, /* pc_relative */
1788 0, /* bitpos */
1789 complain_overflow_dont,/* complain_on_overflow */
1790 bfd_elf_generic_reloc, /* special_function */
1791 "R_ARM_RABS32", /* name */
1792 FALSE, /* partial_inplace */
1793 0, /* src_mask */
1794 0, /* dst_mask */
1795 FALSE), /* pcrel_offset */
1796
1797 HOWTO (R_ARM_RPC24, /* type */
1798 0, /* rightshift */
1799 0, /* size (0 = byte, 1 = short, 2 = long) */
1800 0, /* bitsize */
1801 FALSE, /* pc_relative */
1802 0, /* bitpos */
1803 complain_overflow_dont,/* complain_on_overflow */
1804 bfd_elf_generic_reloc, /* special_function */
1805 "R_ARM_RPC24", /* name */
1806 FALSE, /* partial_inplace */
1807 0, /* src_mask */
1808 0, /* dst_mask */
1809 FALSE), /* pcrel_offset */
1810
1811 HOWTO (R_ARM_RBASE, /* type */
1812 0, /* rightshift */
1813 0, /* size (0 = byte, 1 = short, 2 = long) */
1814 0, /* bitsize */
1815 FALSE, /* pc_relative */
1816 0, /* bitpos */
1817 complain_overflow_dont,/* complain_on_overflow */
1818 bfd_elf_generic_reloc, /* special_function */
1819 "R_ARM_RBASE", /* name */
1820 FALSE, /* partial_inplace */
1821 0, /* src_mask */
1822 0, /* dst_mask */
1823 FALSE) /* pcrel_offset */
1824};
1825
1826static reloc_howto_type *
1827elf32_arm_howto_from_type (unsigned int r_type)
1828{
906e58ca 1829 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1830 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1831
34e77a92
RS		 1832 if (r_type == R_ARM_IRELATIVE)
1833 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1834
c19d1205 1835 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1836 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1837 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1838
c19d1205 1839 return NULL;
7f266840
DJ		 1840}
1841
1842static void
1843elf32_arm_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, arelent * bfd_reloc,
1844 Elf_Internal_Rela * elf_reloc)
1845{
1846 unsigned int r_type;
1847
1848 r_type = ELF32_R_TYPE (elf_reloc->r_info);
1849 bfd_reloc->howto = elf32_arm_howto_from_type (r_type);
1850}
1851
1852struct elf32_arm_reloc_map
1853 {
1854 bfd_reloc_code_real_type bfd_reloc_val;
07d6d2b8 1855 unsigned char elf_reloc_val;
7f266840
DJ		 1856 };
1857
1858/* All entries in this list must also be present in elf32_arm_howto_table. */
1859static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1860 {
07d6d2b8 1861 {BFD_RELOC_NONE, R_ARM_NONE},
7f266840 1862 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1863 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1864 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
07d6d2b8
AM		 1865 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1866 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1867 {BFD_RELOC_32, R_ARM_ABS32},
1868 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1869 {BFD_RELOC_8, R_ARM_ABS8},
1870 {BFD_RELOC_16, R_ARM_ABS16},
1871 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
7f266840 1872 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1873 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1874 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1875 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1876 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1877 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1878 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
07d6d2b8
AM		 1879 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1880 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1881 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
1882 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
1883 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
1884 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
1885 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1886 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
7f266840
DJ		 1887 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1888 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1889 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1890 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac 1891 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
07d6d2b8
AM		 1892 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1893 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1894 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
0855e32b 1895 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
07d6d2b8 1896 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
0855e32b 1897 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
07d6d2b8 1898 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1899 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1900 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1901 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1902 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1903 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
07d6d2b8
AM		 1904 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1905 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1906 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
1907 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
c19d1205
ZW		 1908 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1909 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1910 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1911 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1912 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1913 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1914 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1915 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1916 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1917 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1918 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1919 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1920 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1921 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1922 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1923 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1924 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1925 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1926 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1927 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1928 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1929 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1930 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1931 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1932 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1933 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1934 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
1935 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
1936 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
1937 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
1938 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
1939 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
1940 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
1941 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
1942 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
1943 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
1944 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 1945 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 1946 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
1947 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
1948 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
1949 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
1950 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 1951 };
1952
1953static reloc_howto_type *
f1c71a59
ZW		 1954elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1955 bfd_reloc_code_real_type code)
7f266840
DJ		 1956{
1957 unsigned int i;
8029a119 1958
906e58ca 1959 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 1960 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
1961 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 1962
c19d1205 1963 return NULL;
7f266840
DJ		 1964}
1965
157090f7
AM		 1966static reloc_howto_type *
1967elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1968 const char *r_name)
1969{
1970 unsigned int i;
1971
906e58ca 1972 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 1973 if (elf32_arm_howto_table_1[i].name != NULL
1974 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
1975 return &elf32_arm_howto_table_1[i];
1976
906e58ca 1977 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 1978 if (elf32_arm_howto_table_2[i].name != NULL
1979 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
1980 return &elf32_arm_howto_table_2[i];
1981
34e77a92
RS		 1982 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
1983 if (elf32_arm_howto_table_3[i].name != NULL
1984 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
1985 return &elf32_arm_howto_table_3[i];
1986
157090f7
AM		 1987 return NULL;
1988}
1989
906e58ca
NC		 1990/* Support for core dump NOTE sections. */
1991
7f266840 1992static bfd_boolean
f1c71a59 1993elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 1994{
1995 int offset;
1996 size_t size;
1997
1998 switch (note->descsz)
1999 {
2000 default:
2001 return FALSE;
2002
8029a119 2003 case 148: /* Linux/ARM 32-bit. */
7f266840 2004 /* pr_cursig */
228e534f 2005 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2006
2007 /* pr_pid */
228e534f 2008 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2009
2010 /* pr_reg */
2011 offset = 72;
2012 size = 72;
2013
2014 break;
2015 }
2016
2017 /* Make a ".reg/999" section. */
2018 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2019 size, note->descpos + offset);
2020}
2021
2022static bfd_boolean
f1c71a59 2023elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2024{
2025 switch (note->descsz)
2026 {
2027 default:
2028 return FALSE;
2029
8029a119 2030 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2031 elf_tdata (abfd)->core->pid
4395ee08 2032 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2033 elf_tdata (abfd)->core->program
7f266840 2034 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2035 elf_tdata (abfd)->core->command
7f266840
DJ		 2036 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2037 }
2038
2039 /* Note that for some reason, a spurious space is tacked
2040 onto the end of the args in some (at least one anyway)
2041 implementations, so strip it off if it exists. */
7f266840 2042 {
228e534f 2043 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2044 int n = strlen (command);
2045
2046 if (0 < n && command[n - 1] == ' ')
2047 command[n - 1] = '\0';
2048 }
2049
2050 return TRUE;
2051}
2052
1f20dca5
UW		 2053static char *
2054elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2055 int note_type, ...)
2056{
2057 switch (note_type)
2058 {
2059 default:
2060 return NULL;
2061
2062 case NT_PRPSINFO:
2063 {
2064 char data[124];
2065 va_list ap;
2066
2067 va_start (ap, note_type);
2068 memset (data, 0, sizeof (data));
2069 strncpy (data + 28, va_arg (ap, const char *), 16);
2070 strncpy (data + 44, va_arg (ap, const char *), 80);
2071 va_end (ap);
2072
2073 return elfcore_write_note (abfd, buf, bufsiz,
2074 "CORE", note_type, data, sizeof (data));
2075 }
2076
2077 case NT_PRSTATUS:
2078 {
2079 char data[148];
2080 va_list ap;
2081 long pid;
2082 int cursig;
2083 const void *greg;
2084
2085 va_start (ap, note_type);
2086 memset (data, 0, sizeof (data));
2087 pid = va_arg (ap, long);
2088 bfd_put_32 (abfd, pid, data + 24);
2089 cursig = va_arg (ap, int);
2090 bfd_put_16 (abfd, cursig, data + 12);
2091 greg = va_arg (ap, const void *);
2092 memcpy (data + 72, greg, 72);
2093 va_end (ap);
2094
2095 return elfcore_write_note (abfd, buf, bufsiz,
2096 "CORE", note_type, data, sizeof (data));
2097 }
2098 }
2099}
2100
07d6d2b8
AM		 2101#define TARGET_LITTLE_SYM arm_elf32_le_vec
2102#define TARGET_LITTLE_NAME "elf32-littlearm"
2103#define TARGET_BIG_SYM arm_elf32_be_vec
2104#define TARGET_BIG_NAME "elf32-bigarm"
7f266840
DJ		 2105
2106#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2107#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2108#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2109
252b5132
RH		 2110typedef unsigned long int insn32;
2111typedef unsigned short int insn16;
2112
3a4a14e9
PB		 2113/* In lieu of proper flags, assume all EABIv4 or later objects are
2114 interworkable. */
57e8b36a 2115#define INTERWORK_FLAG(abfd) \
3a4a14e9 2116 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2117 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2118 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2119
252b5132
RH		 2120/* The linker script knows the section names for placement.
2121 The entry_names are used to do simple name mangling on the stubs.
2122 Given a function name, and its type, the stub can be found. The
9b485d32 2123 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2124#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2125#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2126
2127#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2128#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2129
c7b8f16e
JB		 2130#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2131#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2132
a504d23a
LA		 2133#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2134#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2135
845b51d6
PB		 2136#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2137#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2138
7413f23f
DJ		 2139#define STUB_ENTRY_NAME "__%s_veneer"
2140
4ba2ef8f
TP		 2141#define CMSE_PREFIX "__acle_se_"
2142
252b5132
RH		 2143/* The name of the dynamic interpreter. This is put in the .interp
2144 section. */
2145#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2146
0855e32b 2147static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2148{
2149 0xe08e0000, /* add r0, lr, r0 */
2150 0xe5901004, /* ldr r1, [r0,#4] */
2151 0xe12fff11, /* bx r1 */
2152};
0855e32b
NS		 2153
2154static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2155{
2156 0xe52d2004, /* push {r2} */
2157 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2158 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2159 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2160 0xe081100f, /* 2: add r1, pc */
2161 0xe12fff12, /* bx r2 */
2162 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2163 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2164 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2165};
0855e32b 2166
5e681ec4
PB		 2167#ifdef FOUR_WORD_PLT
2168
252b5132
RH		 2169/* The first entry in a procedure linkage table looks like
2170 this. It is set up so that any shared library function that is
59f2c4e7 2171 called before the relocation has been set up calls the dynamic
9b485d32 2172 linker first. */
e5a52504 2173static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2174{
2175 0xe52de004, /* str lr, [sp, #-4]! */
2176 0xe59fe010, /* ldr lr, [pc, #16] */
2177 0xe08fe00e, /* add lr, pc, lr */
2178 0xe5bef008, /* ldr pc, [lr, #8]! */
2179};
5e681ec4
PB		 2180
2181/* Subsequent entries in a procedure linkage table look like
2182 this. */
e5a52504 2183static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2184{
2185 0xe28fc600, /* add ip, pc, #NN */
2186 0xe28cca00, /* add ip, ip, #NN */
2187 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2188 0x00000000, /* unused */
2189};
5e681ec4 2190
eed94f8f 2191#else /* not FOUR_WORD_PLT */
5e681ec4 2192
5e681ec4
PB		 2193/* The first entry in a procedure linkage table looks like
2194 this. It is set up so that any shared library function that is
2195 called before the relocation has been set up calls the dynamic
2196 linker first. */
e5a52504 2197static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb 2198{
07d6d2b8
AM		 2199 0xe52de004, /* str lr, [sp, #-4]! */
2200 0xe59fe004, /* ldr lr, [pc, #4] */
2201 0xe08fe00e, /* add lr, pc, lr */
2202 0xe5bef008, /* ldr pc, [lr, #8]! */
2203 0x00000000, /* &GOT[0] - . */
b38cadfb 2204};
252b5132 2205
1db37fe6
YG		 2206/* By default subsequent entries in a procedure linkage table look like
2207 this. Offsets that don't fit into 28 bits will cause link error. */
2208static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2209{
2210 0xe28fc600, /* add ip, pc, #0xNN00000 */
2211 0xe28cca00, /* add ip, ip, #0xNN000 */
2212 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2213};
5e681ec4 2214
1db37fe6
YG		 2215/* When explicitly asked, we'll use this "long" entry format
2216 which can cope with arbitrary displacements. */
2217static const bfd_vma elf32_arm_plt_entry_long [] =
2218{
07d6d2b8
AM		 2219 0xe28fc200, /* add ip, pc, #0xN0000000 */
2220 0xe28cc600, /* add ip, ip, #0xNN00000 */
1db37fe6
YG		 2221 0xe28cca00, /* add ip, ip, #0xNN000 */
2222 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2223};
2224
2225static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2226
eed94f8f
NC		 2227#endif /* not FOUR_WORD_PLT */
2228
2229/* The first entry in a procedure linkage table looks like this.
2230 It is set up so that any shared library function that is called before the
2231 relocation has been set up calls the dynamic linker first. */
2232static const bfd_vma elf32_thumb2_plt0_entry [] =
2233{
2234 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2235 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2236 0xf8dfb500, /* push {lr} */
2237 0x44fee008, /* ldr.w lr, [pc, #8] */
2238 /* add lr, pc */
eed94f8f 2239 0xff08f85e, /* ldr.w pc, [lr, #8]! */
07d6d2b8 2240 0x00000000, /* &GOT[0] - . */
eed94f8f
NC		 2241};
2242
2243/* Subsequent entries in a procedure linkage table for thumb only target
2244 look like this. */
2245static const bfd_vma elf32_thumb2_plt_entry [] =
2246{
2247 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2248 an instruction maybe encoded to one or two array elements. */
07d6d2b8
AM		 2249 0x0c00f240, /* movw ip, #0xNNNN */
2250 0x0c00f2c0, /* movt ip, #0xNNNN */
2251 0xf8dc44fc, /* add ip, pc */
2252 0xbf00f000 /* ldr.w pc, [ip] */
2253 /* nop */
eed94f8f 2254};
252b5132 2255
00a97672
RS		 2256/* The format of the first entry in the procedure linkage table
2257 for a VxWorks executable. */
2258static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb 2259{
07d6d2b8
AM		 2260 0xe52dc008, /* str ip,[sp,#-8]! */
2261 0xe59fc000, /* ldr ip,[pc] */
2262 0xe59cf008, /* ldr pc,[ip,#8] */
2263 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
b38cadfb 2264};
00a97672
RS		 2265
2266/* The format of subsequent entries in a VxWorks executable. */
2267static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb 2268{
07d6d2b8
AM		 2269 0xe59fc000, /* ldr ip,[pc] */
2270 0xe59cf000, /* ldr pc,[ip] */
2271 0x00000000, /* .long @got */
2272 0xe59fc000, /* ldr ip,[pc] */
2273 0xea000000, /* b _PLT */
2274 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2275};
00a97672
RS		 2276
2277/* The format of entries in a VxWorks shared library. */
2278static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb 2279{
07d6d2b8
AM		 2280 0xe59fc000, /* ldr ip,[pc] */
2281 0xe79cf009, /* ldr pc,[ip,r9] */
2282 0x00000000, /* .long @got */
2283 0xe59fc000, /* ldr ip,[pc] */
2284 0xe599f008, /* ldr pc,[r9,#8] */
2285 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
b38cadfb 2286};
00a97672 2287
b7693d02
DJ		 2288/* An initial stub used if the PLT entry is referenced from Thumb code. */
2289#define PLT_THUMB_STUB_SIZE 4
2290static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2291{
2292 0x4778, /* bx pc */
2293 0x46c0 /* nop */
2294};
b7693d02 2295
e5a52504
MM		 2296/* The entries in a PLT when using a DLL-based target with multiple
2297 address spaces. */
906e58ca 2298static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb 2299{
07d6d2b8
AM		 2300 0xe51ff004, /* ldr pc, [pc, #-4] */
2301 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
b38cadfb
NC		 2302};
2303
2304/* The first entry in a procedure linkage table looks like
2305 this. It is set up so that any shared library function that is
2306 called before the relocation has been set up calls the dynamic
2307 linker first. */
2308static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2309{
2310 /* First bundle: */
2311 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2312 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2313 0xe08cc00f, /* add ip, ip, pc */
2314 0xe52dc008, /* str ip, [sp, #-8]! */
2315 /* Second bundle: */
edccdf7c
RM		 2316 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2317 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2318 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2319 0xe12fff1c, /* bx ip */
b38cadfb 2320 /* Third bundle: */
edccdf7c
RM		 2321 0xe320f000, /* nop */
2322 0xe320f000, /* nop */
2323 0xe320f000, /* nop */
b38cadfb
NC		 2324 /* .Lplt_tail: */
2325 0xe50dc004, /* str ip, [sp, #-4] */
2326 /* Fourth bundle: */
edccdf7c
RM		 2327 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2328 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2329 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2330 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2331};
2332#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2333
2334/* Subsequent entries in a procedure linkage table look like this. */
2335static const bfd_vma elf32_arm_nacl_plt_entry [] =
2336{
2337 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2338 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2339 0xe08cc00f, /* add ip, ip, pc */
2340 0xea000000, /* b .Lplt_tail */
2341};
e5a52504 2342
906e58ca
NC		 2343#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2344#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2345#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2346#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2347#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2348#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2349#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2350#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2351
461a49ca 2352enum stub_insn_type
b38cadfb
NC		 2353{
2354 THUMB16_TYPE = 1,
2355 THUMB32_TYPE,
2356 ARM_TYPE,
2357 DATA_TYPE
2358};
461a49ca 2359
48229727
JB		 2360#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2361/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2362 is inserted in arm_build_one_stub(). */
2363#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2364#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
d5a67c02
AV		 2365#define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2366#define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
48229727
JB		 2367#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2368#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2369#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2370#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2371
2372typedef struct
2373{
07d6d2b8 2374 bfd_vma data;
b38cadfb 2375 enum stub_insn_type type;
07d6d2b8
AM		 2376 unsigned int r_type;
2377 int reloc_addend;
461a49ca
DJ		 2378} insn_sequence;
2379
fea2b4d6
CL		 2380/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2381 to reach the stub if necessary. */
461a49ca 2382static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb 2383{
07d6d2b8 2384 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2385 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2386};
906e58ca 2387
fea2b4d6
CL		 2388/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2389 available. */
461a49ca 2390static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb 2391{
07d6d2b8
AM		 2392 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2393 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2394 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2395};
906e58ca 2396
d3626fb0 2397/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2398static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb 2399{
07d6d2b8
AM		 2400 THUMB16_INSN (0xb401), /* push {r0} */
2401 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2402 THUMB16_INSN (0x4684), /* mov ip, r0 */
2403 THUMB16_INSN (0xbc01), /* pop {r0} */
2404 THUMB16_INSN (0x4760), /* bx ip */
2405 THUMB16_INSN (0xbf00), /* nop */
b38cadfb
NC		 2406 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2407};
906e58ca 2408
80c135e5
TP		 2409/* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2410static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2411{
07d6d2b8 2412 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
80c135e5
TP		 2413 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2414};
2415
d5a67c02
AV		 2416/* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2417 M-profile architectures. */
2418static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2419{
2420 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2421 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
07d6d2b8 2422 THUMB16_INSN (0x4760), /* bx ip */
d5a67c02
AV		 2423};
2424
d3626fb0
CL		 2425/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2426 allowed. */
2427static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb 2428{
07d6d2b8
AM		 2429 THUMB16_INSN (0x4778), /* bx pc */
2430 THUMB16_INSN (0x46c0), /* nop */
2431 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2432 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2433 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2434};
d3626fb0 2435
fea2b4d6
CL		 2436/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2437 available. */
461a49ca 2438static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb 2439{
07d6d2b8
AM		 2440 THUMB16_INSN (0x4778), /* bx pc */
2441 THUMB16_INSN (0x46c0), /* nop */
2442 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
b38cadfb
NC		 2443 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2444};
906e58ca 2445
fea2b4d6
CL		 2446/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2447 one, when the destination is close enough. */
461a49ca 2448static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb 2449{
07d6d2b8
AM		 2450 THUMB16_INSN (0x4778), /* bx pc */
2451 THUMB16_INSN (0x46c0), /* nop */
b38cadfb
NC		 2452 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2453};
c820be07 2454
cf3eccff 2455/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2456 blx to reach the stub if necessary. */
cf3eccff 2457static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb 2458{
07d6d2b8
AM		 2459 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2460 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
b38cadfb
NC		 2461 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2462};
906e58ca 2463
cf3eccff
DJ		 2464/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2465 blx to reach the stub if necessary. We can not add into pc;
2466 it is not guaranteed to mode switch (different in ARMv6 and
2467 ARMv7). */
2468static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb 2469{
07d6d2b8
AM		 2470 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2471 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2472 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2473 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2474};
cf3eccff 2475
ebe24dd4
CL		 2476/* V4T ARM -> ARM long branch stub, PIC. */
2477static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb 2478{
07d6d2b8
AM		 2479 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2480 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2481 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2482 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2483};
ebe24dd4
CL		 2484
2485/* V4T Thumb -> ARM long branch stub, PIC. */
2486static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb 2487{
07d6d2b8
AM		 2488 THUMB16_INSN (0x4778), /* bx pc */
2489 THUMB16_INSN (0x46c0), /* nop */
2490 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2491 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
b38cadfb
NC		 2492 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2493};
ebe24dd4 2494
d3626fb0
CL		 2495/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2496 architectures. */
ebe24dd4 2497static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb 2498{
07d6d2b8
AM		 2499 THUMB16_INSN (0xb401), /* push {r0} */
2500 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2501 THUMB16_INSN (0x46fc), /* mov ip, pc */
2502 THUMB16_INSN (0x4484), /* add ip, r0 */
2503 THUMB16_INSN (0xbc01), /* pop {r0} */
2504 THUMB16_INSN (0x4760), /* bx ip */
b38cadfb
NC		 2505 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2506};
ebe24dd4 2507
d3626fb0
CL		 2508/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2509 allowed. */
2510static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb 2511{
07d6d2b8
AM		 2512 THUMB16_INSN (0x4778), /* bx pc */
2513 THUMB16_INSN (0x46c0), /* nop */
2514 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2515 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2516 ARM_INSN (0xe12fff1c), /* bx ip */
b38cadfb
NC		 2517 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2518};
d3626fb0 2519
0855e32b
NS		 2520/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2521 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2522static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2523{
07d6d2b8
AM		 2524 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2525 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
b38cadfb 2526 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2527};
2528
2529/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2530 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2531static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2532{
07d6d2b8
AM		 2533 THUMB16_INSN (0x4778), /* bx pc */
2534 THUMB16_INSN (0x46c0), /* nop */
2535 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2536 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
b38cadfb 2537 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2538};
2539
7a89b94e
NC		 2540/* NaCl ARM -> ARM long branch stub. */
2541static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2542{
2543 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2544 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2545 ARM_INSN (0xe12fff1c), /* bx ip */
2546 ARM_INSN (0xe320f000), /* nop */
2547 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2548 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2549 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2550 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2551};
2552
2553/* NaCl ARM -> ARM long branch stub, PIC. */
2554static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2555{
2556 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
07d6d2b8 2557 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
7a89b94e 2558 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
07d6d2b8
AM		 2559 ARM_INSN (0xe12fff1c), /* bx ip */
2560 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2561 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2562 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2563 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
7a89b94e
NC		 2564};
2565
4ba2ef8f
TP		 2566/* Stub used for transition to secure state (aka SG veneer). */
2567static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2568{
2569 THUMB32_INSN (0xe97fe97f), /* sg. */
2570 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2571};
2572
7a89b94e 2573
48229727
JB		 2574/* Cortex-A8 erratum-workaround stubs. */
2575
2576/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2577 can't use a conditional branch to reach this stub). */
2578
2579static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb 2580{
07d6d2b8 2581 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
b38cadfb
NC		 2582 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2583 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2584};
48229727
JB		 2585
2586/* Stub used for b.w and bl.w instructions. */
2587
2588static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2589{
2590 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2591};
48229727
JB		 2592
2593static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2594{
2595 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2596};
48229727
JB		 2597
2598/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2599 instruction (which switches to ARM mode) to point to this stub. Jump to the
2600 real destination using an ARM-mode branch. */
2601
2602static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2603{
2604 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2605};
48229727 2606
9553db3c
NC		 2607/* For each section group there can be a specially created linker section
2608 to hold the stubs for that group. The name of the stub section is based
2609 upon the name of another section within that group with the suffix below
2610 applied.
2611
2612 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2613 create what appeared to be a linker stub section when it actually
2614 contained user code/data. For example, consider this fragment:
b38cadfb 2615
9553db3c
NC		 2616 const char * stubborn_problems[] = { "np" };
2617
2618 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2619 section called:
2620
2621 .data.rel.local.stubborn_problems
2622
2623 This then causes problems in arm32_arm_build_stubs() as it triggers:
2624
2625 // Ignore non-stub sections.
2626 if (!strstr (stub_sec->name, STUB_SUFFIX))
2627 continue;
2628
2629 And so the section would be ignored instead of being processed. Hence
2630 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2631 C identifier. */
2632#define STUB_SUFFIX ".__stub"
906e58ca 2633
738a79f6
CL		 2634/* One entry per long/short branch stub defined above. */
2635#define DEF_STUBS \
2636 DEF_STUB(long_branch_any_any) \
2637 DEF_STUB(long_branch_v4t_arm_thumb) \
2638 DEF_STUB(long_branch_thumb_only) \
2639 DEF_STUB(long_branch_v4t_thumb_thumb) \
2640 DEF_STUB(long_branch_v4t_thumb_arm) \
2641 DEF_STUB(short_branch_v4t_thumb_arm) \
2642 DEF_STUB(long_branch_any_arm_pic) \
2643 DEF_STUB(long_branch_any_thumb_pic) \
2644 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2645 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2646 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2647 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2648 DEF_STUB(long_branch_any_tls_pic) \
2649 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2650 DEF_STUB(long_branch_arm_nacl) \
2651 DEF_STUB(long_branch_arm_nacl_pic) \
4ba2ef8f 2652 DEF_STUB(cmse_branch_thumb_only) \
48229727
JB		 2653 DEF_STUB(a8_veneer_b_cond) \
2654 DEF_STUB(a8_veneer_b) \
2655 DEF_STUB(a8_veneer_bl) \
80c135e5
TP		 2656 DEF_STUB(a8_veneer_blx) \
2657 DEF_STUB(long_branch_thumb2_only) \
d5a67c02 2658 DEF_STUB(long_branch_thumb2_only_pure)
738a79f6
CL		 2659
2660#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2661enum elf32_arm_stub_type
2662{
906e58ca 2663 arm_stub_none,
738a79f6 2664 DEF_STUBS
4f4faa4d 2665 max_stub_type
738a79f6
CL		 2666};
2667#undef DEF_STUB
2668
8d9d9490
TP		 2669/* Note the first a8_veneer type. */
2670const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2671
738a79f6
CL		 2672typedef struct
2673{
d3ce72d0 2674 const insn_sequence* template_sequence;
738a79f6
CL		 2675 int template_size;
2676} stub_def;
2677
2678#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2679static const stub_def stub_definitions[] =
2680{
738a79f6
CL		 2681 {NULL, 0},
2682 DEF_STUBS
906e58ca
NC		 2683};
2684
2685struct elf32_arm_stub_hash_entry
2686{
2687 /* Base hash table entry structure. */
2688 struct bfd_hash_entry root;
2689
2690 /* The stub section. */
2691 asection *stub_sec;
2692
2693 /* Offset within stub_sec of the beginning of this stub. */
2694 bfd_vma stub_offset;
2695
2696 /* Given the symbol's value and its section we can determine its final
2697 value when building the stubs (so the stub knows where to jump). */
2698 bfd_vma target_value;
2699 asection *target_section;
2700
8d9d9490
TP		 2701 /* Same as above but for the source of the branch to the stub. Used for
2702 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2703 such, source section does not need to be recorded since Cortex-A8 erratum
2704 workaround stubs are only generated when both source and target are in the
2705 same section. */
2706 bfd_vma source_value;
48229727
JB		 2707
2708 /* The instruction which caused this stub to be generated (only valid for
2709 Cortex-A8 erratum workaround stubs at present). */
2710 unsigned long orig_insn;
2711
461a49ca 2712 /* The stub type. */
906e58ca 2713 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2714 /* Its encoding size in bytes. */
2715 int stub_size;
2716 /* Its template. */
2717 const insn_sequence *stub_template;
2718 /* The size of the template (number of entries). */
2719 int stub_template_size;
906e58ca
NC		 2720
2721 /* The symbol table entry, if any, that this was derived from. */
2722 struct elf32_arm_link_hash_entry *h;
2723
35fc36a8
RS		 2724 /* Type of branch. */
2725 enum arm_st_branch_type branch_type;
906e58ca
NC		 2726
2727 /* Where this stub is being called from, or, in the case of combined
2728 stub sections, the first input section in the group. */
2729 asection *id_sec;
7413f23f
DJ		 2730
2731 /* The name for the local symbol at the start of this stub. The
2732 stub name in the hash table has to be unique; this does not, so
2733 it can be friendlier. */
2734 char *output_name;
906e58ca
NC		 2735};
2736
e489d0ae
PB		 2737/* Used to build a map of a section. This is required for mixed-endian
2738 code/data. */
2739
2740typedef struct elf32_elf_section_map
2741{
2742 bfd_vma vma;
2743 char type;
2744}
2745elf32_arm_section_map;
2746
c7b8f16e
JB		 2747/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2748
2749typedef enum
2750{
2751 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2752 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2753 VFP11_ERRATUM_ARM_VENEER,
2754 VFP11_ERRATUM_THUMB_VENEER
2755}
2756elf32_vfp11_erratum_type;
2757
2758typedef struct elf32_vfp11_erratum_list
2759{
2760 struct elf32_vfp11_erratum_list *next;
2761 bfd_vma vma;
2762 union
2763 {
2764 struct
2765 {
2766 struct elf32_vfp11_erratum_list *veneer;
2767 unsigned int vfp_insn;
2768 } b;
2769 struct
2770 {
2771 struct elf32_vfp11_erratum_list *branch;
2772 unsigned int id;
2773 } v;
2774 } u;
2775 elf32_vfp11_erratum_type type;
2776}
2777elf32_vfp11_erratum_list;
2778
a504d23a
LA		 2779/* Information about a STM32L4XX erratum veneer, or a branch to such a
2780 veneer. */
2781typedef enum
2782{
2783 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2784 STM32L4XX_ERRATUM_VENEER
2785}
2786elf32_stm32l4xx_erratum_type;
2787
2788typedef struct elf32_stm32l4xx_erratum_list
2789{
2790 struct elf32_stm32l4xx_erratum_list *next;
2791 bfd_vma vma;
2792 union
2793 {
2794 struct
2795 {
2796 struct elf32_stm32l4xx_erratum_list *veneer;
2797 unsigned int insn;
2798 } b;
2799 struct
2800 {
2801 struct elf32_stm32l4xx_erratum_list *branch;
2802 unsigned int id;
2803 } v;
2804 } u;
2805 elf32_stm32l4xx_erratum_type type;
2806}
2807elf32_stm32l4xx_erratum_list;
2808
2468f9c9
PB		 2809typedef enum
2810{
2811 DELETE_EXIDX_ENTRY,
2812 INSERT_EXIDX_CANTUNWIND_AT_END
2813}
2814arm_unwind_edit_type;
2815
2816/* A (sorted) list of edits to apply to an unwind table. */
2817typedef struct arm_unwind_table_edit
2818{
2819 arm_unwind_edit_type type;
2820 /* Note: we sometimes want to insert an unwind entry corresponding to a
2821 section different from the one we're currently writing out, so record the
2822 (text) section this edit relates to here. */
2823 asection *linked_section;
2824 unsigned int index;
2825 struct arm_unwind_table_edit *next;
2826}
2827arm_unwind_table_edit;
2828
8e3de13a 2829typedef struct _arm_elf_section_data
e489d0ae 2830{
2468f9c9 2831 /* Information about mapping symbols. */
e489d0ae 2832 struct bfd_elf_section_data elf;
8e3de13a 2833 unsigned int mapcount;
c7b8f16e 2834 unsigned int mapsize;
e489d0ae 2835 elf32_arm_section_map *map;
2468f9c9 2836 /* Information about CPU errata. */
c7b8f16e
JB		 2837 unsigned int erratumcount;
2838 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2839 unsigned int stm32l4xx_erratumcount;
2840 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2841 unsigned int additional_reloc_count;
2468f9c9
PB		 2842 /* Information about unwind tables. */
2843 union
2844 {
2845 /* Unwind info attached to a text section. */
2846 struct
2847 {
2848 asection *arm_exidx_sec;
2849 } text;
2850
2851 /* Unwind info attached to an .ARM.exidx section. */
2852 struct
2853 {
2854 arm_unwind_table_edit *unwind_edit_list;
2855 arm_unwind_table_edit *unwind_edit_tail;
2856 } exidx;
2857 } u;
8e3de13a
NC		 2858}
2859_arm_elf_section_data;
e489d0ae
PB		 2860
2861#define elf32_arm_section_data(sec) \
8e3de13a 2862 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2863
48229727
JB		 2864/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2865 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2866 so may be created multiple times: we use an array of these entries whilst
2867 relaxing which we can refresh easily, then create stubs for each potentially
2868 erratum-triggering instruction once we've settled on a solution. */
2869
b38cadfb
NC		 2870struct a8_erratum_fix
2871{
48229727
JB		 2872 bfd *input_bfd;
2873 asection *section;
2874 bfd_vma offset;
8d9d9490 2875 bfd_vma target_offset;
48229727
JB		 2876 unsigned long orig_insn;
2877 char *stub_name;
2878 enum elf32_arm_stub_type stub_type;
35fc36a8 2879 enum arm_st_branch_type branch_type;
48229727
JB		 2880};
2881
2882/* A table of relocs applied to branches which might trigger Cortex-A8
2883 erratum. */
2884
b38cadfb
NC		 2885struct a8_erratum_reloc
2886{
48229727
JB		 2887 bfd_vma from;
2888 bfd_vma destination;
92750f34
DJ		 2889 struct elf32_arm_link_hash_entry *hash;
2890 const char *sym_name;
48229727 2891 unsigned int r_type;
35fc36a8 2892 enum arm_st_branch_type branch_type;
48229727
JB		 2893 bfd_boolean non_a8_stub;
2894};
2895
ba93b8ac
DJ		 2896/* The size of the thread control block. */
2897#define TCB_SIZE 8
2898
34e77a92
RS		 2899/* ARM-specific information about a PLT entry, over and above the usual
2900 gotplt_union. */
b38cadfb
NC		 2901struct arm_plt_info
2902{
34e77a92
RS		 2903 /* We reference count Thumb references to a PLT entry separately,
2904 so that we can emit the Thumb trampoline only if needed. */
2905 bfd_signed_vma thumb_refcount;
2906
2907 /* Some references from Thumb code may be eliminated by BL->BLX
2908 conversion, so record them separately. */
2909 bfd_signed_vma maybe_thumb_refcount;
2910
2911 /* How many of the recorded PLT accesses were from non-call relocations.
2912 This information is useful when deciding whether anything takes the
2913 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2914 non-call references to the function should resolve directly to the
2915 real runtime target. */
2916 unsigned int noncall_refcount;
2917
2918 /* Since PLT entries have variable size if the Thumb prologue is
2919 used, we need to record the index into .got.plt instead of
2920 recomputing it from the PLT offset. */
2921 bfd_signed_vma got_offset;
2922};
2923
2924/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2925struct arm_local_iplt_info
2926{
34e77a92
RS		 2927 /* The information that is usually found in the generic ELF part of
2928 the hash table entry. */
2929 union gotplt_union root;
2930
2931 /* The information that is usually found in the ARM-specific part of
2932 the hash table entry. */
2933 struct arm_plt_info arm;
2934
2935 /* A list of all potential dynamic relocations against this symbol. */
2936 struct elf_dyn_relocs *dyn_relocs;
2937};
2938
0ffa91dd 2939struct elf_arm_obj_tdata
ba93b8ac
DJ		 2940{
2941 struct elf_obj_tdata root;
2942
2943 /* tls_type for each local got entry. */
2944 char *local_got_tls_type;
ee065d83 2945
0855e32b
NS		 2946 /* GOTPLT entries for TLS descriptors. */
2947 bfd_vma *local_tlsdesc_gotent;
2948
34e77a92
RS		 2949 /* Information for local symbols that need entries in .iplt. */
2950 struct arm_local_iplt_info **local_iplt;
2951
bf21ed78
MS		 2952 /* Zero to warn when linking objects with incompatible enum sizes. */
2953 int no_enum_size_warning;
a9dc9481
JM		 2954
2955 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2956 int no_wchar_size_warning;
ba93b8ac
DJ		 2957};
2958
0ffa91dd
NC		 2959#define elf_arm_tdata(bfd) \
2960 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 2961
0ffa91dd
NC		 2962#define elf32_arm_local_got_tls_type(bfd) \
2963 (elf_arm_tdata (bfd)->local_got_tls_type)
2964
0855e32b
NS		 2965#define elf32_arm_local_tlsdesc_gotent(bfd) \
2966 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2967
34e77a92
RS		 2968#define elf32_arm_local_iplt(bfd) \
2969 (elf_arm_tdata (bfd)->local_iplt)
2970
0ffa91dd
NC		 2971#define is_arm_elf(bfd) \
2972 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2973 && elf_tdata (bfd) != NULL \
4dfe6ac6 2974 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 2975
2976static bfd_boolean
2977elf32_arm_mkobject (bfd *abfd)
2978{
0ffa91dd 2979 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 2980 ARM_ELF_DATA);
ba93b8ac
DJ		 2981}
2982
ba93b8ac
DJ		 2983#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2984
ba96a88f 2985/* Arm ELF linker hash entry. */
252b5132 2986struct elf32_arm_link_hash_entry
b38cadfb
NC		 2987{
2988 struct elf_link_hash_entry root;
252b5132 2989
b38cadfb
NC		 2990 /* Track dynamic relocs copied for this symbol. */
2991 struct elf_dyn_relocs *dyn_relocs;
b7693d02 2992
b38cadfb
NC		 2993 /* ARM-specific PLT information. */
2994 struct arm_plt_info plt;
ba93b8ac
DJ		 2995
2996#define GOT_UNKNOWN 0
2997#define GOT_NORMAL 1
2998#define GOT_TLS_GD 2
2999#define GOT_TLS_IE 4
0855e32b
NS		 3000#define GOT_TLS_GDESC 8
3001#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 3002 unsigned int tls_type : 8;
34e77a92 3003
b38cadfb
NC		 3004 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3005 unsigned int is_iplt : 1;
34e77a92 3006
b38cadfb 3007 unsigned int unused : 23;
a4fd1a8e 3008
b38cadfb
NC		 3009 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3010 starting at the end of the jump table. */
3011 bfd_vma tlsdesc_got;
0855e32b 3012
b38cadfb
NC		 3013 /* The symbol marking the real symbol location for exported thumb
3014 symbols with Arm stubs. */
3015 struct elf_link_hash_entry *export_glue;
906e58ca 3016
b38cadfb 3017 /* A pointer to the most recently used stub hash entry against this
8029a119 3018 symbol. */
b38cadfb
NC		 3019 struct elf32_arm_stub_hash_entry *stub_cache;
3020};
252b5132 3021
252b5132 3022/* Traverse an arm ELF linker hash table. */
252b5132
RH		 3023#define elf32_arm_link_hash_traverse(table, func, info) \
3024 (elf_link_hash_traverse \
3025 (&(table)->root, \
b7693d02 3026 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 3027 (info)))
3028
3029/* Get the ARM elf linker hash table from a link_info structure. */
3030#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3031 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3032 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3033
906e58ca
NC		 3034#define arm_stub_hash_lookup(table, string, create, copy) \
3035 ((struct elf32_arm_stub_hash_entry *) \
3036 bfd_hash_lookup ((table), (string), (create), (copy)))
3037
21d799b5
NC		 3038/* Array to keep track of which stub sections have been created, and
3039 information on stub grouping. */
3040struct map_stub
3041{
3042 /* This is the section to which stubs in the group will be
3043 attached. */
3044 asection *link_sec;
3045 /* The stub section. */
3046 asection *stub_sec;
3047};
3048
0855e32b
NS		 3049#define elf32_arm_compute_jump_table_size(htab) \
3050 ((htab)->next_tls_desc_index * 4)
3051
9b485d32 3052/* ARM ELF linker hash table. */
252b5132 3053struct elf32_arm_link_hash_table
906e58ca
NC		 3054{
3055 /* The main hash table. */
3056 struct elf_link_hash_table root;
252b5132 3057
906e58ca
NC		 3058 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3059 bfd_size_type thumb_glue_size;
252b5132 3060
906e58ca
NC		 3061 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3062 bfd_size_type arm_glue_size;
252b5132 3063
906e58ca
NC		 3064 /* The size in bytes of section containing the ARMv4 BX veneers. */
3065 bfd_size_type bx_glue_size;
845b51d6 3066
906e58ca
NC		 3067 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3068 veneer has been populated. */
3069 bfd_vma bx_glue_offset[15];
845b51d6 3070
906e58ca
NC		 3071 /* The size in bytes of the section containing glue for VFP11 erratum
3072 veneers. */
3073 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3074
a504d23a
LA		 3075 /* The size in bytes of the section containing glue for STM32L4XX erratum
3076 veneers. */
3077 bfd_size_type stm32l4xx_erratum_glue_size;
3078
48229727
JB		 3079 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3080 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3081 elf32_arm_write_section(). */
3082 struct a8_erratum_fix *a8_erratum_fixes;
3083 unsigned int num_a8_erratum_fixes;
3084
906e58ca
NC		 3085 /* An arbitrary input BFD chosen to hold the glue sections. */
3086 bfd * bfd_of_glue_owner;
ba96a88f 3087
906e58ca
NC		 3088 /* Nonzero to output a BE8 image. */
3089 int byteswap_code;
e489d0ae 3090
906e58ca
NC		 3091 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3092 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3093 int target1_is_rel;
9c504268 3094
906e58ca
NC		 3095 /* The relocation to use for R_ARM_TARGET2 relocations. */
3096 int target2_reloc;
eb043451 3097
906e58ca
NC		 3098 /* 0 = Ignore R_ARM_V4BX.
3099 1 = Convert BX to MOV PC.
3100 2 = Generate v4 interworing stubs. */
3101 int fix_v4bx;
319850b4 3102
48229727
JB		 3103 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3104 int fix_cortex_a8;
3105
2de70689
MGD		 3106 /* Whether we should fix the ARM1176 BLX immediate issue. */
3107 int fix_arm1176;
3108
906e58ca
NC		 3109 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3110 int use_blx;
33bfe774 3111
906e58ca
NC		 3112 /* What sort of code sequences we should look for which may trigger the
3113 VFP11 denorm erratum. */
3114 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3115
906e58ca
NC		 3116 /* Global counter for the number of fixes we have emitted. */
3117 int num_vfp11_fixes;
c7b8f16e 3118
a504d23a
LA		 3119 /* What sort of code sequences we should look for which may trigger the
3120 STM32L4XX erratum. */
3121 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3122
3123 /* Global counter for the number of fixes we have emitted. */
3124 int num_stm32l4xx_fixes;
3125
906e58ca
NC		 3126 /* Nonzero to force PIC branch veneers. */
3127 int pic_veneer;
27e55c4d 3128
906e58ca
NC		 3129 /* The number of bytes in the initial entry in the PLT. */
3130 bfd_size_type plt_header_size;
e5a52504 3131
906e58ca
NC		 3132 /* The number of bytes in the subsequent PLT etries. */
3133 bfd_size_type plt_entry_size;
e5a52504 3134
906e58ca
NC		 3135 /* True if the target system is VxWorks. */
3136 int vxworks_p;
00a97672 3137
906e58ca
NC		 3138 /* True if the target system is Symbian OS. */
3139 int symbian_p;
e5a52504 3140
b38cadfb
NC		 3141 /* True if the target system is Native Client. */
3142 int nacl_p;
3143
906e58ca
NC		 3144 /* True if the target uses REL relocations. */
3145 int use_rel;
4e7fd91e 3146
54ddd295
TP		 3147 /* Nonzero if import library must be a secure gateway import library
3148 as per ARMv8-M Security Extensions. */
3149 int cmse_implib;
3150
0955507f
TP		 3151 /* The import library whose symbols' address must remain stable in
3152 the import library generated. */
3153 bfd *in_implib_bfd;
3154
0855e32b
NS		 3155 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3156 bfd_vma next_tls_desc_index;
3157
3158 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3159 bfd_vma num_tls_desc;
3160
906e58ca
NC		 3161 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3162 asection *srelplt2;
00a97672 3163
0855e32b
NS		 3164 /* The offset into splt of the PLT entry for the TLS descriptor
3165 resolver. Special values are 0, if not necessary (or not found
3166 to be necessary yet), and -1 if needed but not determined
3167 yet. */
3168 bfd_vma dt_tlsdesc_plt;
3169
3170 /* The offset into sgot of the GOT entry used by the PLT entry
3171 above. */
b38cadfb 3172 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3173
3174 /* Offset in .plt section of tls_arm_trampoline. */
3175 bfd_vma tls_trampoline;
3176
906e58ca
NC		 3177 /* Data for R_ARM_TLS_LDM32 relocations. */
3178 union
3179 {
3180 bfd_signed_vma refcount;
3181 bfd_vma offset;
3182 } tls_ldm_got;
b7693d02 3183
87d72d41
AM		 3184 /* Small local sym cache. */
3185 struct sym_cache sym_cache;
906e58ca
NC		 3186
3187 /* For convenience in allocate_dynrelocs. */
3188 bfd * obfd;
3189
0855e32b
NS		 3190 /* The amount of space used by the reserved portion of the sgotplt
3191 section, plus whatever space is used by the jump slots. */
3192 bfd_vma sgotplt_jump_table_size;
3193
906e58ca
NC		 3194 /* The stub hash table. */
3195 struct bfd_hash_table stub_hash_table;
3196
3197 /* Linker stub bfd. */
3198 bfd *stub_bfd;
3199
3200 /* Linker call-backs. */
6bde4c52
TP		 3201 asection * (*add_stub_section) (const char *, asection *, asection *,
3202 unsigned int);
906e58ca
NC		 3203 void (*layout_sections_again) (void);
3204
3205 /* Array to keep track of which stub sections have been created, and
3206 information on stub grouping. */
21d799b5 3207 struct map_stub *stub_group;
906e58ca 3208
4ba2ef8f
TP		 3209 /* Input stub section holding secure gateway veneers. */
3210 asection *cmse_stub_sec;
3211
0955507f
TP		 3212 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3213 start to be allocated. */
3214 bfd_vma new_cmse_stub_offset;
3215
fe33d2fa 3216 /* Number of elements in stub_group. */
7292b3ac 3217 unsigned int top_id;
fe33d2fa 3218
906e58ca
NC		 3219 /* Assorted information used by elf32_arm_size_stubs. */
3220 unsigned int bfd_count;
7292b3ac 3221 unsigned int top_index;
906e58ca
NC		 3222 asection **input_list;
3223};
252b5132 3224
a504d23a
LA		 3225static inline int
3226ctz (unsigned int mask)
3227{
3228#if GCC_VERSION >= 3004
3229 return __builtin_ctz (mask);
3230#else
3231 unsigned int i;
3232
3233 for (i = 0; i < 8 * sizeof (mask); i++)
3234 {
3235 if (mask & 0x1)
3236 break;
3237 mask = (mask >> 1);
3238 }
3239 return i;
3240#endif
3241}
3242
3243static inline int
b25e998d 3244elf32_arm_popcount (unsigned int mask)
a504d23a
LA		 3245{
3246#if GCC_VERSION >= 3004
3247 return __builtin_popcount (mask);
3248#else
b25e998d
CG		 3249 unsigned int i;
3250 int sum = 0;
a504d23a
LA		 3251
3252 for (i = 0; i < 8 * sizeof (mask); i++)
3253 {
3254 if (mask & 0x1)
3255 sum++;
3256 mask = (mask >> 1);
3257 }
3258 return sum;
3259#endif
3260}
3261
780a67af
NC		 3262/* Create an entry in an ARM ELF linker hash table. */
3263
3264static struct bfd_hash_entry *
57e8b36a 3265elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3266 struct bfd_hash_table * table,
3267 const char * string)
780a67af
NC		 3268{
3269 struct elf32_arm_link_hash_entry * ret =
3270 (struct elf32_arm_link_hash_entry *) entry;
3271
3272 /* Allocate the structure if it has not already been allocated by a
3273 subclass. */
906e58ca 3274 if (ret == NULL)
21d799b5 3275 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3276 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3277 if (ret == NULL)
780a67af
NC		 3278 return (struct bfd_hash_entry *) ret;
3279
3280 /* Call the allocation method of the superclass. */
3281 ret = ((struct elf32_arm_link_hash_entry *)
3282 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3283 table, string));
57e8b36a 3284 if (ret != NULL)
b7693d02 3285 {
0bdcacaf 3286 ret->dyn_relocs = NULL;
ba93b8ac 3287 ret->tls_type = GOT_UNKNOWN;
0855e32b 3288 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3289 ret->plt.thumb_refcount = 0;
3290 ret->plt.maybe_thumb_refcount = 0;
3291 ret->plt.noncall_refcount = 0;
3292 ret->plt.got_offset = -1;
3293 ret->is_iplt = FALSE;
a4fd1a8e 3294 ret->export_glue = NULL;
906e58ca
NC		 3295
3296 ret->stub_cache = NULL;
b7693d02 3297 }
780a67af
NC		 3298
3299 return (struct bfd_hash_entry *) ret;
3300}
3301
34e77a92
RS		 3302/* Ensure that we have allocated bookkeeping structures for ABFD's local
3303 symbols. */
3304
3305static bfd_boolean
3306elf32_arm_allocate_local_sym_info (bfd *abfd)
3307{
3308 if (elf_local_got_refcounts (abfd) == NULL)
3309 {
3310 bfd_size_type num_syms;
3311 bfd_size_type size;
3312 char *data;
3313
3314 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3315 size = num_syms * (sizeof (bfd_signed_vma)
3316 + sizeof (struct arm_local_iplt_info *)
3317 + sizeof (bfd_vma)
3318 + sizeof (char));
3319 data = bfd_zalloc (abfd, size);
3320 if (data == NULL)
3321 return FALSE;
3322
3323 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3324 data += num_syms * sizeof (bfd_signed_vma);
3325
3326 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3327 data += num_syms * sizeof (struct arm_local_iplt_info *);
3328
3329 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3330 data += num_syms * sizeof (bfd_vma);
3331
3332 elf32_arm_local_got_tls_type (abfd) = data;
3333 }
3334 return TRUE;
3335}
3336
3337/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3338 to input bfd ABFD. Create the information if it doesn't already exist.
3339 Return null if an allocation fails. */
3340
3341static struct arm_local_iplt_info *
3342elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3343{
3344 struct arm_local_iplt_info **ptr;
3345
3346 if (!elf32_arm_allocate_local_sym_info (abfd))
3347 return NULL;
3348
3349 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3350 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3351 if (*ptr == NULL)
3352 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3353 return *ptr;
3354}
3355
3356/* Try to obtain PLT information for the symbol with index R_SYMNDX
3357 in ABFD's symbol table. If the symbol is global, H points to its
3358 hash table entry, otherwise H is null.
3359
3360 Return true if the symbol does have PLT information. When returning
3361 true, point *ROOT_PLT at the target-independent reference count/offset
3362 union and *ARM_PLT at the ARM-specific information. */
3363
3364static bfd_boolean
4ba2ef8f
TP		 3365elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3366 struct elf32_arm_link_hash_entry *h,
34e77a92
RS		 3367 unsigned long r_symndx, union gotplt_union **root_plt,
3368 struct arm_plt_info **arm_plt)
3369{
3370 struct arm_local_iplt_info *local_iplt;
3371
4ba2ef8f
TP		 3372 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3373 return FALSE;
3374
34e77a92
RS		 3375 if (h != NULL)
3376 {
3377 *root_plt = &h->root.plt;
3378 *arm_plt = &h->plt;
3379 return TRUE;
3380 }
3381
3382 if (elf32_arm_local_iplt (abfd) == NULL)
3383 return FALSE;
3384
3385 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3386 if (local_iplt == NULL)
3387 return FALSE;
3388
3389 *root_plt = &local_iplt->root;
3390 *arm_plt = &local_iplt->arm;
3391 return TRUE;
3392}
3393
3394/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3395 before it. */
3396
3397static bfd_boolean
3398elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3399 struct arm_plt_info *arm_plt)
3400{
3401 struct elf32_arm_link_hash_table *htab;
3402
3403 htab = elf32_arm_hash_table (info);
3404 return (arm_plt->thumb_refcount != 0
3405 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3406}
3407
3408/* Return a pointer to the head of the dynamic reloc list that should
3409 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3410 ABFD's symbol table. Return null if an error occurs. */
3411
3412static struct elf_dyn_relocs **
3413elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3414 Elf_Internal_Sym *isym)
3415{
3416 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3417 {
3418 struct arm_local_iplt_info *local_iplt;
3419
3420 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3421 if (local_iplt == NULL)
3422 return NULL;
3423 return &local_iplt->dyn_relocs;
3424 }
3425 else
3426 {
3427 /* Track dynamic relocs needed for local syms too.
3428 We really need local syms available to do this
3429 easily. Oh well. */
3430 asection *s;
3431 void *vpp;
3432
3433 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3434 if (s == NULL)
3435 abort ();
3436
3437 vpp = &elf_section_data (s)->local_dynrel;
3438 return (struct elf_dyn_relocs **) vpp;
3439 }
3440}
3441
906e58ca
NC		 3442/* Initialize an entry in the stub hash table. */
3443
3444static struct bfd_hash_entry *
3445stub_hash_newfunc (struct bfd_hash_entry *entry,
3446 struct bfd_hash_table *table,
3447 const char *string)
3448{
3449 /* Allocate the structure if it has not already been allocated by a
3450 subclass. */
3451 if (entry == NULL)
3452 {
21d799b5 3453 entry = (struct bfd_hash_entry *)
99059e56 3454 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3455 if (entry == NULL)
3456 return entry;
3457 }
3458
3459 /* Call the allocation method of the superclass. */
3460 entry = bfd_hash_newfunc (entry, table, string);
3461 if (entry != NULL)
3462 {
3463 struct elf32_arm_stub_hash_entry *eh;
3464
3465 /* Initialize the local fields. */
3466 eh = (struct elf32_arm_stub_hash_entry *) entry;
3467 eh->stub_sec = NULL;
0955507f 3468 eh->stub_offset = (bfd_vma) -1;
8d9d9490 3469 eh->source_value = 0;
906e58ca
NC		 3470 eh->target_value = 0;
3471 eh->target_section = NULL;
cedfb179 3472 eh->orig_insn = 0;
906e58ca 3473 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3474 eh->stub_size = 0;
3475 eh->stub_template = NULL;
0955507f 3476 eh->stub_template_size = -1;
906e58ca
NC		 3477 eh->h = NULL;
3478 eh->id_sec = NULL;
d8d2f433 3479 eh->output_name = NULL;
906e58ca
NC		 3480 }
3481
3482 return entry;
3483}
3484
00a97672 3485/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3486 shortcuts to them in our hash table. */
3487
3488static bfd_boolean
57e8b36a 3489create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3490{
3491 struct elf32_arm_link_hash_table *htab;
3492
e5a52504 3493 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3494 if (htab == NULL)
3495 return FALSE;
3496
e5a52504
MM		 3497 /* BPABI objects never have a GOT, or associated sections. */
3498 if (htab->symbian_p)
3499 return TRUE;
3500
5e681ec4
PB		 3501 if (! _bfd_elf_create_got_section (dynobj, info))
3502 return FALSE;
3503
5e681ec4
PB		 3504 return TRUE;
3505}
3506
34e77a92
RS		 3507/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3508
3509static bfd_boolean
3510create_ifunc_sections (struct bfd_link_info *info)
3511{
3512 struct elf32_arm_link_hash_table *htab;
3513 const struct elf_backend_data *bed;
3514 bfd *dynobj;
3515 asection *s;
3516 flagword flags;
b38cadfb 3517
34e77a92
RS		 3518 htab = elf32_arm_hash_table (info);
3519 dynobj = htab->root.dynobj;
3520 bed = get_elf_backend_data (dynobj);
3521 flags = bed->dynamic_sec_flags;
3522
3523 if (htab->root.iplt == NULL)
3524 {
3d4d4302
AM		 3525 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3526 flags | SEC_READONLY | SEC_CODE);
34e77a92 3527 if (s == NULL
a0f49396 3528 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3529 return FALSE;
3530 htab->root.iplt = s;
3531 }
3532
3533 if (htab->root.irelplt == NULL)
3534 {
3d4d4302
AM		 3535 s = bfd_make_section_anyway_with_flags (dynobj,
3536 RELOC_SECTION (htab, ".iplt"),
3537 flags | SEC_READONLY);
34e77a92 3538 if (s == NULL
a0f49396 3539 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3540 return FALSE;
3541 htab->root.irelplt = s;
3542 }
3543
3544 if (htab->root.igotplt == NULL)
3545 {
3d4d4302 3546 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3547 if (s == NULL
3548 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3549 return FALSE;
3550 htab->root.igotplt = s;
3551 }
3552 return TRUE;
3553}
3554
eed94f8f
NC		 3555/* Determine if we're dealing with a Thumb only architecture. */
3556
3557static bfd_boolean
3558using_thumb_only (struct elf32_arm_link_hash_table *globals)
3559{
2fd158eb
TP		 3560 int arch;
3561 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3562 Tag_CPU_arch_profile);
eed94f8f 3563
2fd158eb
TP		 3564 if (profile)
3565 return profile == 'M';
eed94f8f 3566
2fd158eb 3567 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3568
60a019a0 3569 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3570 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0 3571
2fd158eb
TP		 3572 if (arch == TAG_CPU_ARCH_V6_M
3573 || arch == TAG_CPU_ARCH_V6S_M
3574 || arch == TAG_CPU_ARCH_V7E_M
3575 || arch == TAG_CPU_ARCH_V8M_BASE
3576 || arch == TAG_CPU_ARCH_V8M_MAIN)
3577 return TRUE;
eed94f8f 3578
2fd158eb 3579 return FALSE;
eed94f8f
NC		 3580}
3581
3582/* Determine if we're dealing with a Thumb-2 object. */
3583
3584static bfd_boolean
3585using_thumb2 (struct elf32_arm_link_hash_table *globals)
3586{
60a019a0
TP		 3587 int arch;
3588 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3589 Tag_THUMB_ISA_use);
3590
3591 if (thumb_isa)
3592 return thumb_isa == 2;
3593
3594 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3595
3596 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3597 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0
TP		 3598
3599 return (arch == TAG_CPU_ARCH_V6T2
3600 || arch == TAG_CPU_ARCH_V7
3601 || arch == TAG_CPU_ARCH_V7E_M
3602 || arch == TAG_CPU_ARCH_V8
bff0500d 3603 || arch == TAG_CPU_ARCH_V8R
60a019a0 3604 || arch == TAG_CPU_ARCH_V8M_MAIN);
eed94f8f
NC		 3605}
3606
5e866f5a
TP		 3607/* Determine whether Thumb-2 BL instruction is available. */
3608
3609static bfd_boolean
3610using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3611{
3612 int arch =
3613 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3614
3615 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3616 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
5e866f5a
TP		 3617
3618 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3619 return (arch == TAG_CPU_ARCH_V6T2
3620 || arch >= TAG_CPU_ARCH_V7);
3621}
3622
00a97672
RS		 3623/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3624 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3625 hash table. */
3626
3627static bfd_boolean
57e8b36a 3628elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3629{
3630 struct elf32_arm_link_hash_table *htab;
3631
3632 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3633 if (htab == NULL)
3634 return FALSE;
3635
362d30a1 3636 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3637 return FALSE;
3638
3639 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3640 return FALSE;
3641
00a97672
RS		 3642 if (htab->vxworks_p)
3643 {
3644 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3645 return FALSE;
3646
0e1862bb 3647 if (bfd_link_pic (info))
00a97672
RS		 3648 {
3649 htab->plt_header_size = 0;
3650 htab->plt_entry_size
3651 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3652 }
3653 else
3654 {
3655 htab->plt_header_size
3656 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3657 htab->plt_entry_size
3658 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3659 }
aebf9be7
NC		 3660
3661 if (elf_elfheader (dynobj))
3662 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3663 }
eed94f8f
NC		 3664 else
3665 {
3666 /* PR ld/16017
3667 Test for thumb only architectures. Note - we cannot just call
3668 using_thumb_only() as the attributes in the output bfd have not been
3669 initialised at this point, so instead we use the input bfd. */
3670 bfd * saved_obfd = htab->obfd;
3671
3672 htab->obfd = dynobj;
3673 if (using_thumb_only (htab))
3674 {
3675 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3676 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3677 }
3678 htab->obfd = saved_obfd;
3679 }
5e681ec4 3680
362d30a1
RS		 3681 if (!htab->root.splt
3682 || !htab->root.srelplt
9d19e4fd
AM		 3683 || !htab->root.sdynbss
3684 || (!bfd_link_pic (info) && !htab->root.srelbss))
5e681ec4
PB		 3685 abort ();
3686
3687 return TRUE;
3688}
3689
906e58ca
NC		 3690/* Copy the extra info we tack onto an elf_link_hash_entry. */
3691
3692static void
3693elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3694 struct elf_link_hash_entry *dir,
3695 struct elf_link_hash_entry *ind)
3696{
3697 struct elf32_arm_link_hash_entry *edir, *eind;
3698
3699 edir = (struct elf32_arm_link_hash_entry *) dir;
3700 eind = (struct elf32_arm_link_hash_entry *) ind;
3701
0bdcacaf 3702 if (eind->dyn_relocs != NULL)
906e58ca 3703 {
0bdcacaf 3704 if (edir->dyn_relocs != NULL)
906e58ca 3705 {
0bdcacaf
RS		 3706 struct elf_dyn_relocs **pp;
3707 struct elf_dyn_relocs *p;
906e58ca
NC		 3708
3709 /* Add reloc counts against the indirect sym to the direct sym
3710 list. Merge any entries against the same section. */
0bdcacaf 3711 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3712 {
0bdcacaf 3713 struct elf_dyn_relocs *q;
906e58ca 3714
0bdcacaf
RS		 3715 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3716 if (q->sec == p->sec)
906e58ca
NC		 3717 {
3718 q->pc_count += p->pc_count;
3719 q->count += p->count;
3720 *pp = p->next;
3721 break;
3722 }
3723 if (q == NULL)
3724 pp = &p->next;
3725 }
0bdcacaf 3726 *pp = edir->dyn_relocs;
906e58ca
NC		 3727 }
3728
0bdcacaf
RS		 3729 edir->dyn_relocs = eind->dyn_relocs;
3730 eind->dyn_relocs = NULL;
906e58ca
NC		 3731 }
3732
3733 if (ind->root.type == bfd_link_hash_indirect)
3734 {
3735 /* Copy over PLT info. */
34e77a92
RS		 3736 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3737 eind->plt.thumb_refcount = 0;
3738 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3739 eind->plt.maybe_thumb_refcount = 0;
3740 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3741 eind->plt.noncall_refcount = 0;
3742
3743 /* We should only allocate a function to .iplt once the final
3744 symbol information is known. */
3745 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3746
3747 if (dir->got.refcount <= 0)
3748 {
3749 edir->tls_type = eind->tls_type;
3750 eind->tls_type = GOT_UNKNOWN;
3751 }
3752 }
3753
3754 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3755}
3756
68faa637
AM		 3757/* Destroy an ARM elf linker hash table. */
3758
3759static void
d495ab0d 3760elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3761{
3762 struct elf32_arm_link_hash_table *ret
d495ab0d 3763 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3764
3765 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3766 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3767}
3768
906e58ca
NC		 3769/* Create an ARM elf linker hash table. */
3770
3771static struct bfd_link_hash_table *
3772elf32_arm_link_hash_table_create (bfd *abfd)
3773{
3774 struct elf32_arm_link_hash_table *ret;
3775 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3776
7bf52ea2 3777 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3778 if (ret == NULL)
3779 return NULL;
3780
3781 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3782 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3783 sizeof (struct elf32_arm_link_hash_entry),
3784 ARM_ELF_DATA))
906e58ca
NC		 3785 {
3786 free (ret);
3787 return NULL;
3788 }
3789
906e58ca 3790 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3791 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3792#ifdef FOUR_WORD_PLT
3793 ret->plt_header_size = 16;
3794 ret->plt_entry_size = 16;
3795#else
3796 ret->plt_header_size = 20;
1db37fe6 3797 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3798#endif
906e58ca 3799 ret->use_rel = 1;
906e58ca 3800 ret->obfd = abfd;
906e58ca
NC		 3801
3802 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3803 sizeof (struct elf32_arm_stub_hash_entry)))
3804 {
d495ab0d 3805 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3806 return NULL;
3807 }
d495ab0d 3808 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3809
3810 return &ret->root.root;
3811}
3812
cd1dac3d
DG		 3813/* Determine what kind of NOPs are available. */
3814
3815static bfd_boolean
3816arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3817{
3818 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3819 Tag_CPU_arch);
cd1dac3d 3820
60a019a0 3821 /* Force return logic to be reviewed for each new architecture. */
bff0500d 3822 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
60a019a0
TP		 3823
3824 return (arch == TAG_CPU_ARCH_V6T2
3825 || arch == TAG_CPU_ARCH_V6K
3826 || arch == TAG_CPU_ARCH_V7
bff0500d
TP		 3827 || arch == TAG_CPU_ARCH_V8
3828 || arch == TAG_CPU_ARCH_V8R);
cd1dac3d
DG		 3829}
3830
f4ac8484
DJ		 3831static bfd_boolean
3832arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3833{
3834 switch (stub_type)
3835 {
fea2b4d6 3836 case arm_stub_long_branch_thumb_only:
80c135e5 3837 case arm_stub_long_branch_thumb2_only:
d5a67c02 3838 case arm_stub_long_branch_thumb2_only_pure:
fea2b4d6
CL		 3839 case arm_stub_long_branch_v4t_thumb_arm:
3840 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3841 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3842 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3843 case arm_stub_long_branch_thumb_only_pic:
4ba2ef8f 3844 case arm_stub_cmse_branch_thumb_only:
f4ac8484
DJ		 3845 return TRUE;
3846 case arm_stub_none:
3847 BFD_FAIL ();
3848 return FALSE;
3849 break;
3850 default:
3851 return FALSE;
3852 }
3853}
3854
906e58ca
NC		 3855/* Determine the type of stub needed, if any, for a call. */
3856
3857static enum elf32_arm_stub_type
3858arm_type_of_stub (struct bfd_link_info *info,
3859 asection *input_sec,
3860 const Elf_Internal_Rela *rel,
34e77a92 3861 unsigned char st_type,
35fc36a8 3862 enum arm_st_branch_type *actual_branch_type,
906e58ca 3863 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3864 bfd_vma destination,
3865 asection *sym_sec,
3866 bfd *input_bfd,
3867 const char *name)
906e58ca
NC		 3868{
3869 bfd_vma location;
3870 bfd_signed_vma branch_offset;
3871 unsigned int r_type;
3872 struct elf32_arm_link_hash_table * globals;
5e866f5a 3873 bfd_boolean thumb2, thumb2_bl, thumb_only;
906e58ca 3874 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3875 int use_plt = 0;
35fc36a8 3876 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3877 union gotplt_union *root_plt;
3878 struct arm_plt_info *arm_plt;
d5a67c02
AV		 3879 int arch;
3880 int thumb2_movw;
906e58ca 3881
35fc36a8 3882 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3883 return stub_type;
3884
906e58ca 3885 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3886 if (globals == NULL)
3887 return stub_type;
906e58ca
NC		 3888
3889 thumb_only = using_thumb_only (globals);
906e58ca 3890 thumb2 = using_thumb2 (globals);
5e866f5a 3891 thumb2_bl = using_thumb2_bl (globals);
906e58ca 3892
d5a67c02
AV		 3893 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3894
3895 /* True for architectures that implement the thumb2 movw instruction. */
3896 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
3897
906e58ca
NC		 3898 /* Determine where the call point is. */
3899 location = (input_sec->output_offset
3900 + input_sec->output_section->vma
3901 + rel->r_offset);
3902
906e58ca
NC		 3903 r_type = ELF32_R_TYPE (rel->r_info);
3904
39f21624
NC		 3905 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3906 are considering a function call relocation. */
c5423981 3907 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
07d6d2b8 3908 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3909 && branch_type == ST_BRANCH_TO_ARM)
3910 branch_type = ST_BRANCH_TO_THUMB;
3911
34e77a92
RS		 3912 /* For TLS call relocs, it is the caller's responsibility to provide
3913 the address of the appropriate trampoline. */
3914 if (r_type != R_ARM_TLS_CALL
3915 && r_type != R_ARM_THM_TLS_CALL
4ba2ef8f
TP		 3916 && elf32_arm_get_plt_info (input_bfd, globals, hash,
3917 ELF32_R_SYM (rel->r_info), &root_plt,
3918 &arm_plt)
34e77a92 3919 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3920 {
34e77a92 3921 asection *splt;
fe33d2fa 3922
34e77a92
RS		 3923 if (hash == NULL || hash->is_iplt)
3924 splt = globals->root.iplt;
3925 else
3926 splt = globals->root.splt;
3927 if (splt != NULL)
b38cadfb 3928 {
34e77a92
RS		 3929 use_plt = 1;
3930
3931 /* Note when dealing with PLT entries: the main PLT stub is in
3932 ARM mode, so if the branch is in Thumb mode, another
3933 Thumb->ARM stub will be inserted later just before the ARM
2df2751d
CL		 3934 PLT stub. If a long branch stub is needed, we'll add a
3935 Thumb->Arm one and branch directly to the ARM PLT entry.
3936 Here, we have to check if a pre-PLT Thumb->ARM stub
3937 is needed and if it will be close enough. */
34e77a92
RS		 3938
3939 destination = (splt->output_section->vma
3940 + splt->output_offset
3941 + root_plt->offset);
3942 st_type = STT_FUNC;
2df2751d
CL		 3943
3944 /* Thumb branch/call to PLT: it can become a branch to ARM
3945 or to Thumb. We must perform the same checks and
3946 corrections as in elf32_arm_final_link_relocate. */
3947 if ((r_type == R_ARM_THM_CALL)
3948 || (r_type == R_ARM_THM_JUMP24))
3949 {
3950 if (globals->use_blx
3951 && r_type == R_ARM_THM_CALL
3952 && !thumb_only)
3953 {
3954 /* If the Thumb BLX instruction is available, convert
3955 the BL to a BLX instruction to call the ARM-mode
3956 PLT entry. */
3957 branch_type = ST_BRANCH_TO_ARM;
3958 }
3959 else
3960 {
3961 if (!thumb_only)
3962 /* Target the Thumb stub before the ARM PLT entry. */
3963 destination -= PLT_THUMB_STUB_SIZE;
3964 branch_type = ST_BRANCH_TO_THUMB;
3965 }
3966 }
3967 else
3968 {
3969 branch_type = ST_BRANCH_TO_ARM;
3970 }
34e77a92 3971 }
5fa9e92f 3972 }
34e77a92
RS		 3973 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3974 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 3975
fe33d2fa
CL		 3976 branch_offset = (bfd_signed_vma)(destination - location);
3977
0855e32b 3978 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 3979 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 3980 {
5fa9e92f
CL		 3981 /* Handle cases where:
3982 - this call goes too far (different Thumb/Thumb2 max
99059e56 3983 distance)
155d87d7 3984 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 3985 Thumb->Arm branch (not bl). A stub is needed in this case,
3986 but only if this call is not through a PLT entry. Indeed,
695344c0 3987 PLT stubs handle mode switching already. */
5e866f5a 3988 if ((!thumb2_bl
906e58ca
NC		 3989 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
3990 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
5e866f5a 3991 || (thumb2_bl
906e58ca
NC		 3992 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
3993 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 3994 || (thumb2
3995 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
3996 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
3997 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 3998 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 3999 && (((r_type == R_ARM_THM_CALL
4000 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981 4001 || (r_type == R_ARM_THM_JUMP24)
07d6d2b8 4002 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 4003 && !use_plt))
906e58ca 4004 {
2df2751d
CL		 4005 /* If we need to insert a Thumb-Thumb long branch stub to a
4006 PLT, use one that branches directly to the ARM PLT
4007 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4008 stub, undo this now. */
695344c0
NC		 4009 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4010 {
4011 branch_type = ST_BRANCH_TO_ARM;
4012 branch_offset += PLT_THUMB_STUB_SIZE;
4013 }
2df2751d 4014
35fc36a8 4015 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4016 {
4017 /* Thumb to thumb. */
4018 if (!thumb_only)
4019 {
d5a67c02 4020 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4021 _bfd_error_handler
871b3ab2 4022 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4023 " section with SHF_ARM_PURECODE section"
4024 " attribute is only supported for M-profile"
90b6238f 4025 " targets that implement the movw instruction"),
10463f39 4026 input_bfd, input_sec);
d5a67c02 4027
0e1862bb 4028 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4029 /* PIC stubs. */
155d87d7 4030 ? ((globals->use_blx
9553db3c 4031 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 4032 /* V5T and above. Stub starts with ARM code, so
4033 we must be able to switch mode before
4034 reaching it, which is only possible for 'bl'
4035 (ie R_ARM_THM_CALL relocation). */
cf3eccff 4036 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 4037 /* On V4T, use Thumb code only. */
d3626fb0 4038 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 4039
4040 /* non-PIC stubs. */
155d87d7 4041 : ((globals->use_blx
9553db3c 4042 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 4043 /* V5T and above. */
4044 ? arm_stub_long_branch_any_any
4045 /* V4T. */
d3626fb0 4046 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 4047 }
4048 else
4049 {
d5a67c02
AV		 4050 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4051 stub_type = arm_stub_long_branch_thumb2_only_pure;
4052 else
4053 {
4054 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4055 _bfd_error_handler
871b3ab2 4056 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4057 " section with SHF_ARM_PURECODE section"
4058 " attribute is only supported for M-profile"
90b6238f 4059 " targets that implement the movw instruction"),
10463f39 4060 input_bfd, input_sec);
d5a67c02
AV		 4061
4062 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4063 /* PIC stub. */
4064 ? arm_stub_long_branch_thumb_only_pic
4065 /* non-PIC stub. */
4066 : (thumb2 ? arm_stub_long_branch_thumb2_only
4067 : arm_stub_long_branch_thumb_only);
4068 }
906e58ca
NC		 4069 }
4070 }
4071 else
4072 {
d5a67c02 4073 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4074 _bfd_error_handler
871b3ab2 4075 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4076 " section with SHF_ARM_PURECODE section"
4077 " attribute is only supported" " for M-profile"
90b6238f 4078 " targets that implement the movw instruction"),
10463f39 4079 input_bfd, input_sec);
d5a67c02 4080
906e58ca 4081 /* Thumb to arm. */
c820be07
NC		 4082 if (sym_sec != NULL
4083 && sym_sec->owner != NULL
4084 && !INTERWORK_FLAG (sym_sec->owner))
4085 {
4eca0228 4086 _bfd_error_handler
90b6238f
AM		 4087 (_("%pB(%s): warning: interworking not enabled;"
4088 " first occurrence: %pB: %s call to %s"),
4089 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
c820be07
NC		 4090 }
4091
0855e32b 4092 stub_type =
0e1862bb 4093 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4094 /* PIC stubs. */
0855e32b 4095 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 4096 /* TLS PIC stubs. */
0855e32b
NS		 4097 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4098 : arm_stub_long_branch_v4t_thumb_tls_pic)
4099 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4100 /* V5T PIC and above. */
4101 ? arm_stub_long_branch_any_arm_pic
4102 /* V4T PIC stub. */
4103 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 4104
4105 /* non-PIC stubs. */
0855e32b 4106 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 4107 /* V5T and above. */
4108 ? arm_stub_long_branch_any_any
4109 /* V4T. */
4110 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 4111
4112 /* Handle v4t short branches. */
fea2b4d6 4113 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 4114 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4115 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 4116 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 4117 }
4118 }
4119 }
fe33d2fa
CL		 4120 else if (r_type == R_ARM_CALL
4121 || r_type == R_ARM_JUMP24
0855e32b
NS		 4122 || r_type == R_ARM_PLT32
4123 || r_type == R_ARM_TLS_CALL)
906e58ca 4124 {
d5a67c02 4125 if (input_sec->flags & SEC_ELF_PURECODE)
10463f39 4126 _bfd_error_handler
871b3ab2 4127 (_("%pB(%pA): warning: long branch veneers used in"
10463f39
AM		 4128 " section with SHF_ARM_PURECODE section"
4129 " attribute is only supported for M-profile"
90b6238f 4130 " targets that implement the movw instruction"),
10463f39 4131 input_bfd, input_sec);
35fc36a8 4132 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4133 {
4134 /* Arm to thumb. */
c820be07
NC		 4135
4136 if (sym_sec != NULL
4137 && sym_sec->owner != NULL
4138 && !INTERWORK_FLAG (sym_sec->owner))
4139 {
4eca0228 4140 _bfd_error_handler
90b6238f
AM		 4141 (_("%pB(%s): warning: interworking not enabled;"
4142 " first occurrence: %pB: %s call to %s"),
4143 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
c820be07
NC		 4144 }
4145
4146 /* We have an extra 2-bytes reach because of
4147 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 4148 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4149 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 4150 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 4151 || (r_type == R_ARM_JUMP24)
4152 || (r_type == R_ARM_PLT32))
906e58ca 4153 {
0e1862bb 4154 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4155 /* PIC stubs. */
ebe24dd4
CL		 4156 ? ((globals->use_blx)
4157 /* V5T and above. */
4158 ? arm_stub_long_branch_any_thumb_pic
4159 /* V4T stub. */
4160 : arm_stub_long_branch_v4t_arm_thumb_pic)
4161
c2b4a39d
CL		 4162 /* non-PIC stubs. */
4163 : ((globals->use_blx)
4164 /* V5T and above. */
4165 ? arm_stub_long_branch_any_any
4166 /* V4T. */
4167 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4168 }
4169 }
4170 else
4171 {
4172 /* Arm to arm. */
4173 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4174 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4175 {
0855e32b 4176 stub_type =
0e1862bb 4177 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4178 /* PIC stubs. */
0855e32b 4179 ? (r_type == R_ARM_TLS_CALL
6a631e86 4180 /* TLS PIC Stub. */
0855e32b 4181 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4182 : (globals->nacl_p
4183 ? arm_stub_long_branch_arm_nacl_pic
4184 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4185 /* non-PIC stubs. */
7a89b94e
NC		 4186 : (globals->nacl_p
4187 ? arm_stub_long_branch_arm_nacl
4188 : arm_stub_long_branch_any_any);
906e58ca
NC		 4189 }
4190 }
4191 }
4192
fe33d2fa
CL		 4193 /* If a stub is needed, record the actual destination type. */
4194 if (stub_type != arm_stub_none)
35fc36a8 4195 *actual_branch_type = branch_type;
fe33d2fa 4196
906e58ca
NC		 4197 return stub_type;
4198}
4199
4200/* Build a name for an entry in the stub hash table. */
4201
4202static char *
4203elf32_arm_stub_name (const asection *input_section,
4204 const asection *sym_sec,
4205 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4206 const Elf_Internal_Rela *rel,
4207 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4208{
4209 char *stub_name;
4210 bfd_size_type len;
4211
4212 if (hash)
4213 {
fe33d2fa 4214 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4215 stub_name = (char *) bfd_malloc (len);
906e58ca 4216 if (stub_name != NULL)
fe33d2fa 4217 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4218 input_section->id & 0xffffffff,
4219 hash->root.root.root.string,
fe33d2fa
CL		 4220 (int) rel->r_addend & 0xffffffff,
4221 (int) stub_type);
906e58ca
NC		 4222 }
4223 else
4224 {
fe33d2fa 4225 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4226 stub_name = (char *) bfd_malloc (len);
906e58ca 4227 if (stub_name != NULL)
fe33d2fa 4228 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4229 input_section->id & 0xffffffff,
4230 sym_sec->id & 0xffffffff,
0855e32b
NS		 4231 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4232 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4233 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4234 (int) rel->r_addend & 0xffffffff,
4235 (int) stub_type);
906e58ca
NC		 4236 }
4237
4238 return stub_name;
4239}
4240
4241/* Look up an entry in the stub hash. Stub entries are cached because
4242 creating the stub name takes a bit of time. */
4243
4244static struct elf32_arm_stub_hash_entry *
4245elf32_arm_get_stub_entry (const asection *input_section,
4246 const asection *sym_sec,
4247 struct elf_link_hash_entry *hash,
4248 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4249 struct elf32_arm_link_hash_table *htab,
4250 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4251{
4252 struct elf32_arm_stub_hash_entry *stub_entry;
4253 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4254 const asection *id_sec;
4255
4256 if ((input_section->flags & SEC_CODE) == 0)
4257 return NULL;
4258
4259 /* If this input section is part of a group of sections sharing one
4260 stub section, then use the id of the first section in the group.
4261 Stub names need to include a section id, as there may well be
4262 more than one stub used to reach say, printf, and we need to
4263 distinguish between them. */
c2abbbeb 4264 BFD_ASSERT (input_section->id <= htab->top_id);
906e58ca
NC		 4265 id_sec = htab->stub_group[input_section->id].link_sec;
4266
4267 if (h != NULL && h->stub_cache != NULL
4268 && h->stub_cache->h == h
fe33d2fa
CL		 4269 && h->stub_cache->id_sec == id_sec
4270 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4271 {
4272 stub_entry = h->stub_cache;
4273 }
4274 else
4275 {
4276 char *stub_name;
4277
fe33d2fa 4278 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4279 if (stub_name == NULL)
4280 return NULL;
4281
4282 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4283 stub_name, FALSE, FALSE);
4284 if (h != NULL)
4285 h->stub_cache = stub_entry;
4286
4287 free (stub_name);
4288 }
4289
4290 return stub_entry;
4291}
4292
daa4adae
TP		 4293/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4294 section. */
4295
4296static bfd_boolean
4297arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4298{
4299 if (stub_type >= max_stub_type)
4300 abort (); /* Should be unreachable. */
4301
4ba2ef8f
TP		 4302 switch (stub_type)
4303 {
4304 case arm_stub_cmse_branch_thumb_only:
4305 return TRUE;
4306
4307 default:
4308 return FALSE;
4309 }
4310
4311 abort (); /* Should be unreachable. */
daa4adae
TP		 4312}
4313
4314/* Required alignment (as a power of 2) for the dedicated section holding
4315 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4316 with input sections. */
4317
4318static int
4319arm_dedicated_stub_output_section_required_alignment
4320 (enum elf32_arm_stub_type stub_type)
4321{
4322 if (stub_type >= max_stub_type)
4323 abort (); /* Should be unreachable. */
4324
4ba2ef8f
TP		 4325 switch (stub_type)
4326 {
4327 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4328 boundary. */
4329 case arm_stub_cmse_branch_thumb_only:
4330 return 5;
4331
4332 default:
4333 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4334 return 0;
4335 }
4336
4337 abort (); /* Should be unreachable. */
daa4adae
TP		 4338}
4339
4340/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4341 NULL if veneers of this type are interspersed with input sections. */
4342
4343static const char *
4344arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4345{
4346 if (stub_type >= max_stub_type)
4347 abort (); /* Should be unreachable. */
4348
4ba2ef8f
TP		 4349 switch (stub_type)
4350 {
4351 case arm_stub_cmse_branch_thumb_only:
4352 return ".gnu.sgstubs";
4353
4354 default:
4355 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4356 return NULL;
4357 }
4358
4359 abort (); /* Should be unreachable. */
daa4adae
TP		 4360}
4361
4362/* If veneers of type STUB_TYPE should go in a dedicated output section,
4363 returns the address of the hash table field in HTAB holding a pointer to the
4364 corresponding input section. Otherwise, returns NULL. */
4365
4366static asection **
4ba2ef8f
TP		 4367arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4368 enum elf32_arm_stub_type stub_type)
daa4adae
TP		 4369{
4370 if (stub_type >= max_stub_type)
4371 abort (); /* Should be unreachable. */
4372
4ba2ef8f
TP		 4373 switch (stub_type)
4374 {
4375 case arm_stub_cmse_branch_thumb_only:
4376 return &htab->cmse_stub_sec;
4377
4378 default:
4379 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4380 return NULL;
4381 }
4382
4383 abort (); /* Should be unreachable. */
daa4adae
TP		 4384}
4385
4386/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4387 is the section that branch into veneer and can be NULL if stub should go in
4388 a dedicated output section. Returns a pointer to the stub section, and the
4389 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4390 LINK_SEC_P may be NULL. */
906e58ca 4391
48229727
JB		 4392static asection *
4393elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4394 struct elf32_arm_link_hash_table *htab,
4395 enum elf32_arm_stub_type stub_type)
906e58ca 4396{
daa4adae
TP		 4397 asection *link_sec, *out_sec, **stub_sec_p;
4398 const char *stub_sec_prefix;
4399 bfd_boolean dedicated_output_section =
4400 arm_dedicated_stub_output_section_required (stub_type);
4401 int align;
906e58ca 4402
daa4adae 4403 if (dedicated_output_section)
906e58ca 4404 {
daa4adae
TP		 4405 bfd *output_bfd = htab->obfd;
4406 const char *out_sec_name =
4407 arm_dedicated_stub_output_section_name (stub_type);
4408 link_sec = NULL;
4409 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4410 stub_sec_prefix = out_sec_name;
4411 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4412 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4413 if (out_sec == NULL)
906e58ca 4414 {
90b6238f 4415 _bfd_error_handler (_("no address assigned to the veneers output "
4eca0228 4416 "section %s"), out_sec_name);
daa4adae 4417 return NULL;
906e58ca 4418 }
daa4adae
TP		 4419 }
4420 else
4421 {
c2abbbeb 4422 BFD_ASSERT (section->id <= htab->top_id);
daa4adae
TP		 4423 link_sec = htab->stub_group[section->id].link_sec;
4424 BFD_ASSERT (link_sec != NULL);
4425 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4426 if (*stub_sec_p == NULL)
4427 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4428 stub_sec_prefix = link_sec->name;
4429 out_sec = link_sec->output_section;
4430 align = htab->nacl_p ? 4 : 3;
906e58ca 4431 }
b38cadfb 4432
daa4adae
TP		 4433 if (*stub_sec_p == NULL)
4434 {
4435 size_t namelen;
4436 bfd_size_type len;
4437 char *s_name;
4438
4439 namelen = strlen (stub_sec_prefix);
4440 len = namelen + sizeof (STUB_SUFFIX);
4441 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4442 if (s_name == NULL)
4443 return NULL;
4444
4445 memcpy (s_name, stub_sec_prefix, namelen);
4446 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4447 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4448 align);
4449 if (*stub_sec_p == NULL)
4450 return NULL;
4451
4452 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4453 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4454 | SEC_KEEP;
4455 }
4456
4457 if (!dedicated_output_section)
4458 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4459
48229727
JB		 4460 if (link_sec_p)
4461 *link_sec_p = link_sec;
b38cadfb 4462
daa4adae 4463 return *stub_sec_p;
48229727
JB		 4464}
4465
4466/* Add a new stub entry to the stub hash. Not all fields of the new
4467 stub entry are initialised. */
4468
4469static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4470elf32_arm_add_stub (const char *stub_name, asection *section,
4471 struct elf32_arm_link_hash_table *htab,
4472 enum elf32_arm_stub_type stub_type)
48229727
JB		 4473{
4474 asection *link_sec;
4475 asection *stub_sec;
4476 struct elf32_arm_stub_hash_entry *stub_entry;
4477
daa4adae
TP		 4478 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4479 stub_type);
48229727
JB		 4480 if (stub_sec == NULL)
4481 return NULL;
906e58ca
NC		 4482
4483 /* Enter this entry into the linker stub hash table. */
4484 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4485 TRUE, FALSE);
4486 if (stub_entry == NULL)
4487 {
6bde4c52
TP		 4488 if (section == NULL)
4489 section = stub_sec;
871b3ab2 4490 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 4491 section->owner, stub_name);
906e58ca
NC		 4492 return NULL;
4493 }
4494
4495 stub_entry->stub_sec = stub_sec;
0955507f 4496 stub_entry->stub_offset = (bfd_vma) -1;
906e58ca
NC		 4497 stub_entry->id_sec = link_sec;
4498
906e58ca
NC		 4499 return stub_entry;
4500}
4501
4502/* Store an Arm insn into an output section not processed by
4503 elf32_arm_write_section. */
4504
4505static void
8029a119
NC		 4506put_arm_insn (struct elf32_arm_link_hash_table * htab,
4507 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4508{
4509 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4510 bfd_putl32 (val, ptr);
4511 else
4512 bfd_putb32 (val, ptr);
4513}
4514
4515/* Store a 16-bit Thumb insn into an output section not processed by
4516 elf32_arm_write_section. */
4517
4518static void
8029a119
NC		 4519put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4520 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4521{
4522 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4523 bfd_putl16 (val, ptr);
4524 else
4525 bfd_putb16 (val, ptr);
4526}
4527
a504d23a
LA		 4528/* Store a Thumb2 insn into an output section not processed by
4529 elf32_arm_write_section. */
4530
4531static void
4532put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4533 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4534{
4535 /* T2 instructions are 16-bit streamed. */
4536 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4537 {
4538 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4539 bfd_putl16 ((val & 0xffff), ptr + 2);
4540 }
4541 else
4542 {
4543 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4544 bfd_putb16 ((val & 0xffff), ptr + 2);
4545 }
4546}
4547
0855e32b
NS		 4548/* If it's possible to change R_TYPE to a more efficient access
4549 model, return the new reloc type. */
4550
4551static unsigned
b38cadfb 4552elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4553 struct elf_link_hash_entry *h)
4554{
4555 int is_local = (h == NULL);
4556
0e1862bb
L		 4557 if (bfd_link_pic (info)
4558 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4559 return r_type;
4560
b38cadfb 4561 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4562 switch (r_type)
4563 {
4564 case R_ARM_TLS_GOTDESC:
4565 case R_ARM_TLS_CALL:
4566 case R_ARM_THM_TLS_CALL:
4567 case R_ARM_TLS_DESCSEQ:
4568 case R_ARM_THM_TLS_DESCSEQ:
4569 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4570 }
4571
4572 return r_type;
4573}
4574
48229727
JB		 4575static bfd_reloc_status_type elf32_arm_final_link_relocate
4576 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4577 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4578 const char *, unsigned char, enum arm_st_branch_type,
4579 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4580
4563a860
JB		 4581static unsigned int
4582arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4583{
4584 switch (stub_type)
4585 {
4586 case arm_stub_a8_veneer_b_cond:
4587 case arm_stub_a8_veneer_b:
4588 case arm_stub_a8_veneer_bl:
4589 return 2;
4590
4591 case arm_stub_long_branch_any_any:
4592 case arm_stub_long_branch_v4t_arm_thumb:
4593 case arm_stub_long_branch_thumb_only:
80c135e5 4594 case arm_stub_long_branch_thumb2_only:
d5a67c02 4595 case arm_stub_long_branch_thumb2_only_pure:
4563a860
JB		 4596 case arm_stub_long_branch_v4t_thumb_thumb:
4597 case arm_stub_long_branch_v4t_thumb_arm:
4598 case arm_stub_short_branch_v4t_thumb_arm:
4599 case arm_stub_long_branch_any_arm_pic:
4600 case arm_stub_long_branch_any_thumb_pic:
4601 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4602 case arm_stub_long_branch_v4t_arm_thumb_pic:
4603 case arm_stub_long_branch_v4t_thumb_arm_pic:
4604 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4605 case arm_stub_long_branch_any_tls_pic:
4606 case arm_stub_long_branch_v4t_thumb_tls_pic:
4ba2ef8f 4607 case arm_stub_cmse_branch_thumb_only:
4563a860
JB		 4608 case arm_stub_a8_veneer_blx:
4609 return 4;
b38cadfb 4610
7a89b94e
NC		 4611 case arm_stub_long_branch_arm_nacl:
4612 case arm_stub_long_branch_arm_nacl_pic:
4613 return 16;
4614
4563a860
JB		 4615 default:
4616 abort (); /* Should be unreachable. */
4617 }
4618}
4619
4f4faa4d
TP		 4620/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4621 veneering (TRUE) or have their own symbol (FALSE). */
4622
4623static bfd_boolean
4624arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4625{
4626 if (stub_type >= max_stub_type)
4627 abort (); /* Should be unreachable. */
4628
4ba2ef8f
TP		 4629 switch (stub_type)
4630 {
4631 case arm_stub_cmse_branch_thumb_only:
4632 return TRUE;
4633
4634 default:
4635 return FALSE;
4636 }
4637
4638 abort (); /* Should be unreachable. */
4f4faa4d
TP		 4639}
4640
d7c5bd02
TP		 4641/* Returns the padding needed for the dedicated section used stubs of type
4642 STUB_TYPE. */
4643
4644static int
4645arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4646{
4647 if (stub_type >= max_stub_type)
4648 abort (); /* Should be unreachable. */
4649
4ba2ef8f
TP		 4650 switch (stub_type)
4651 {
4652 case arm_stub_cmse_branch_thumb_only:
4653 return 32;
4654
4655 default:
4656 return 0;
4657 }
4658
4659 abort (); /* Should be unreachable. */
d7c5bd02
TP		 4660}
4661
0955507f
TP		 4662/* If veneers of type STUB_TYPE should go in a dedicated output section,
4663 returns the address of the hash table field in HTAB holding the offset at
4664 which new veneers should be layed out in the stub section. */
4665
4666static bfd_vma*
4667arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
4668 enum elf32_arm_stub_type stub_type)
4669{
4670 switch (stub_type)
4671 {
4672 case arm_stub_cmse_branch_thumb_only:
4673 return &htab->new_cmse_stub_offset;
4674
4675 default:
4676 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4677 return NULL;
4678 }
4679}
4680
906e58ca
NC		 4681static bfd_boolean
4682arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4683 void * in_arg)
4684{
7a89b94e 4685#define MAXRELOCS 3
0955507f 4686 bfd_boolean removed_sg_veneer;
906e58ca 4687 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4688 struct elf32_arm_link_hash_table *globals;
906e58ca 4689 struct bfd_link_info *info;
906e58ca
NC		 4690 asection *stub_sec;
4691 bfd *stub_bfd;
906e58ca
NC		 4692 bfd_byte *loc;
4693 bfd_vma sym_value;
4694 int template_size;
4695 int size;
d3ce72d0 4696 const insn_sequence *template_sequence;
906e58ca 4697 int i;
48229727
JB		 4698 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4699 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4700 int nrelocs = 0;
0955507f 4701 int just_allocated = 0;
906e58ca
NC		 4702
4703 /* Massage our args to the form they really have. */
4704 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4705 info = (struct bfd_link_info *) in_arg;
4706
4707 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4708 if (globals == NULL)
4709 return FALSE;
906e58ca 4710
906e58ca
NC		 4711 stub_sec = stub_entry->stub_sec;
4712
4dfe6ac6 4713 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4714 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4715 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4716 return TRUE;
fe33d2fa 4717
0955507f
TP		 4718 /* Assign a slot at the end of section if none assigned yet. */
4719 if (stub_entry->stub_offset == (bfd_vma) -1)
4720 {
4721 stub_entry->stub_offset = stub_sec->size;
4722 just_allocated = 1;
4723 }
906e58ca
NC		 4724 loc = stub_sec->contents + stub_entry->stub_offset;
4725
4726 stub_bfd = stub_sec->owner;
4727
906e58ca
NC		 4728 /* This is the address of the stub destination. */
4729 sym_value = (stub_entry->target_value
4730 + stub_entry->target_section->output_offset
4731 + stub_entry->target_section->output_section->vma);
4732
d3ce72d0 4733 template_sequence = stub_entry->stub_template;
461a49ca 4734 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4735
4736 size = 0;
461a49ca 4737 for (i = 0; i < template_size; i++)
906e58ca 4738 {
d3ce72d0 4739 switch (template_sequence[i].type)
461a49ca
DJ		 4740 {
4741 case THUMB16_TYPE:
48229727 4742 {
d3ce72d0
NC		 4743 bfd_vma data = (bfd_vma) template_sequence[i].data;
4744 if (template_sequence[i].reloc_addend != 0)
48229727 4745 {
99059e56
RM		 4746 /* We've borrowed the reloc_addend field to mean we should
4747 insert a condition code into this (Thumb-1 branch)
4748 instruction. See THUMB16_BCOND_INSN. */
4749 BFD_ASSERT ((data & 0xff00) == 0xd000);
4750 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4751 }
fe33d2fa 4752 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4753 size += 2;
4754 }
461a49ca 4755 break;
906e58ca 4756
48229727 4757 case THUMB32_TYPE:
fe33d2fa
CL		 4758 bfd_put_16 (stub_bfd,
4759 (template_sequence[i].data >> 16) & 0xffff,
4760 loc + size);
4761 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4762 loc + size + 2);
99059e56
RM		 4763 if (template_sequence[i].r_type != R_ARM_NONE)
4764 {
4765 stub_reloc_idx[nrelocs] = i;
4766 stub_reloc_offset[nrelocs++] = size;
4767 }
4768 size += 4;
4769 break;
48229727 4770
461a49ca 4771 case ARM_TYPE:
fe33d2fa
CL		 4772 bfd_put_32 (stub_bfd, template_sequence[i].data,
4773 loc + size);
461a49ca
DJ		 4774 /* Handle cases where the target is encoded within the
4775 instruction. */
d3ce72d0 4776 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4777 {
48229727
JB		 4778 stub_reloc_idx[nrelocs] = i;
4779 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4780 }
4781 size += 4;
4782 break;
4783
4784 case DATA_TYPE:
d3ce72d0 4785 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4786 stub_reloc_idx[nrelocs] = i;
4787 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4788 size += 4;
4789 break;
4790
4791 default:
4792 BFD_FAIL ();
4793 return FALSE;
4794 }
906e58ca 4795 }
461a49ca 4796
0955507f
TP		 4797 if (just_allocated)
4798 stub_sec->size += size;
906e58ca 4799
461a49ca
DJ		 4800 /* Stub size has already been computed in arm_size_one_stub. Check
4801 consistency. */
4802 BFD_ASSERT (size == stub_entry->stub_size);
4803
906e58ca 4804 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4805 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4806 sym_value |= 1;
4807
0955507f
TP		 4808 /* Assume non empty slots have at least one and at most MAXRELOCS entries
4809 to relocate in each stub. */
4810 removed_sg_veneer =
4811 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
4812 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
c820be07 4813
48229727 4814 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 4815 {
4816 Elf_Internal_Rela rel;
4817 bfd_boolean unresolved_reloc;
4818 char *error_message;
4819 bfd_vma points_to =
4820 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
4821
4822 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4823 rel.r_info = ELF32_R_INFO (0,
4824 template_sequence[stub_reloc_idx[i]].r_type);
4825 rel.r_addend = 0;
4826
4827 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4828 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4829 template should refer back to the instruction after the original
4830 branch. We use target_section as Cortex-A8 erratum workaround stubs
4831 are only generated when both source and target are in the same
4832 section. */
4833 points_to = stub_entry->target_section->output_section->vma
4834 + stub_entry->target_section->output_offset
4835 + stub_entry->source_value;
4836
4837 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4838 (template_sequence[stub_reloc_idx[i]].r_type),
4839 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
4840 points_to, info, stub_entry->target_section, "", STT_FUNC,
4841 stub_entry->branch_type,
4842 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4843 &error_message);
4844 }
906e58ca
NC		 4845
4846 return TRUE;
48229727 4847#undef MAXRELOCS
906e58ca
NC		 4848}
4849
48229727
JB		 4850/* Calculate the template, template size and instruction size for a stub.
4851 Return value is the instruction size. */
906e58ca 4852
48229727
JB		 4853static unsigned int
4854find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4855 const insn_sequence **stub_template,
4856 int *stub_template_size)
906e58ca 4857{
d3ce72d0 4858 const insn_sequence *template_sequence = NULL;
48229727
JB		 4859 int template_size = 0, i;
4860 unsigned int size;
906e58ca 4861
d3ce72d0 4862 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4863 if (stub_template)
4864 *stub_template = template_sequence;
4865
48229727 4866 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4867 if (stub_template_size)
4868 *stub_template_size = template_size;
906e58ca
NC		 4869
4870 size = 0;
461a49ca
DJ		 4871 for (i = 0; i < template_size; i++)
4872 {
d3ce72d0 4873 switch (template_sequence[i].type)
461a49ca
DJ		 4874 {
4875 case THUMB16_TYPE:
4876 size += 2;
4877 break;
4878
4879 case ARM_TYPE:
48229727 4880 case THUMB32_TYPE:
461a49ca
DJ		 4881 case DATA_TYPE:
4882 size += 4;
4883 break;
4884
4885 default:
4886 BFD_FAIL ();
2a229407 4887 return 0;
461a49ca
DJ		 4888 }
4889 }
4890
48229727
JB		 4891 return size;
4892}
4893
4894/* As above, but don't actually build the stub. Just bump offset so
4895 we know stub section sizes. */
4896
4897static bfd_boolean
4898arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4899 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4900{
4901 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4902 const insn_sequence *template_sequence;
48229727
JB		 4903 int template_size, size;
4904
4905 /* Massage our args to the form they really have. */
4906 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4907
4908 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4909 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4910
d3ce72d0 4911 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4912 &template_size);
4913
0955507f
TP		 4914 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
4915 if (stub_entry->stub_template_size)
4916 {
4917 stub_entry->stub_size = size;
4918 stub_entry->stub_template = template_sequence;
4919 stub_entry->stub_template_size = template_size;
4920 }
4921
4922 /* Already accounted for. */
4923 if (stub_entry->stub_offset != (bfd_vma) -1)
4924 return TRUE;
461a49ca 4925
906e58ca
NC		 4926 size = (size + 7) & ~7;
4927 stub_entry->stub_sec->size += size;
461a49ca 4928
906e58ca
NC		 4929 return TRUE;
4930}
4931
4932/* External entry points for sizing and building linker stubs. */
4933
4934/* Set up various things so that we can make a list of input sections
4935 for each output section included in the link. Returns -1 on error,
4936 0 when no stubs will be needed, and 1 on success. */
4937
4938int
4939elf32_arm_setup_section_lists (bfd *output_bfd,
4940 struct bfd_link_info *info)
4941{
4942 bfd *input_bfd;
4943 unsigned int bfd_count;
7292b3ac 4944 unsigned int top_id, top_index;
906e58ca
NC		 4945 asection *section;
4946 asection **input_list, **list;
4947 bfd_size_type amt;
4948 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4949
4dfe6ac6
NC		 4950 if (htab == NULL)
4951 return 0;
906e58ca
NC		 4952 if (! is_elf_hash_table (htab))
4953 return 0;
4954
4955 /* Count the number of input BFDs and find the top input section id. */
4956 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
4957 input_bfd != NULL;
c72f2fb2 4958 input_bfd = input_bfd->link.next)
906e58ca
NC		 4959 {
4960 bfd_count += 1;
4961 for (section = input_bfd->sections;
4962 section != NULL;
4963 section = section->next)
4964 {
4965 if (top_id < section->id)
4966 top_id = section->id;
4967 }
4968 }
4969 htab->bfd_count = bfd_count;
4970
4971 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 4972 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 4973 if (htab->stub_group == NULL)
4974 return -1;
fe33d2fa 4975 htab->top_id = top_id;
906e58ca
NC		 4976
4977 /* We can't use output_bfd->section_count here to find the top output
4978 section index as some sections may have been removed, and
4979 _bfd_strip_section_from_output doesn't renumber the indices. */
4980 for (section = output_bfd->sections, top_index = 0;
4981 section != NULL;
4982 section = section->next)
4983 {
4984 if (top_index < section->index)
4985 top_index = section->index;
4986 }
4987
4988 htab->top_index = top_index;
4989 amt = sizeof (asection *) * (top_index + 1);
21d799b5 4990 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 4991 htab->input_list = input_list;
4992 if (input_list == NULL)
4993 return -1;
4994
4995 /* For sections we aren't interested in, mark their entries with a
4996 value we can check later. */
4997 list = input_list + top_index;
4998 do
4999 *list = bfd_abs_section_ptr;
5000 while (list-- != input_list);
5001
5002 for (section = output_bfd->sections;
5003 section != NULL;
5004 section = section->next)
5005 {
5006 if ((section->flags & SEC_CODE) != 0)
5007 input_list[section->index] = NULL;
5008 }
5009
5010 return 1;
5011}
5012
5013/* The linker repeatedly calls this function for each input section,
5014 in the order that input sections are linked into output sections.
5015 Build lists of input sections to determine groupings between which
5016 we may insert linker stubs. */
5017
5018void
5019elf32_arm_next_input_section (struct bfd_link_info *info,
5020 asection *isec)
5021{
5022 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5023
4dfe6ac6
NC		 5024 if (htab == NULL)
5025 return;
5026
906e58ca
NC		 5027 if (isec->output_section->index <= htab->top_index)
5028 {
5029 asection **list = htab->input_list + isec->output_section->index;
5030
a7470592 5031 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 5032 {
5033 /* Steal the link_sec pointer for our list. */
5034#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5035 /* This happens to make the list in reverse order,
07d72278 5036 which we reverse later. */
906e58ca
NC		 5037 PREV_SEC (isec) = *list;
5038 *list = isec;
5039 }
5040 }
5041}
5042
5043/* See whether we can group stub sections together. Grouping stub
5044 sections may result in fewer stubs. More importantly, we need to
07d72278 5045 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 5046 .fini output sections respectively, because glibc splits the
5047 _init and _fini functions into multiple parts. Putting a stub in
5048 the middle of a function is not a good idea. */
5049
5050static void
5051group_sections (struct elf32_arm_link_hash_table *htab,
5052 bfd_size_type stub_group_size,
07d72278 5053 bfd_boolean stubs_always_after_branch)
906e58ca 5054{
07d72278 5055 asection **list = htab->input_list;
906e58ca
NC		 5056
5057 do
5058 {
5059 asection *tail = *list;
07d72278 5060 asection *head;
906e58ca
NC		 5061
5062 if (tail == bfd_abs_section_ptr)
5063 continue;
5064
07d72278
DJ		 5065 /* Reverse the list: we must avoid placing stubs at the
5066 beginning of the section because the beginning of the text
5067 section may be required for an interrupt vector in bare metal
5068 code. */
5069#define NEXT_SEC PREV_SEC
e780aef2
CL		 5070 head = NULL;
5071 while (tail != NULL)
99059e56
RM		 5072 {
5073 /* Pop from tail. */
5074 asection *item = tail;
5075 tail = PREV_SEC (item);
e780aef2 5076
99059e56
RM		 5077 /* Push on head. */
5078 NEXT_SEC (item) = head;
5079 head = item;
5080 }
07d72278
DJ		 5081
5082 while (head != NULL)
906e58ca
NC		 5083 {
5084 asection *curr;
07d72278 5085 asection *next;
e780aef2
CL		 5086 bfd_vma stub_group_start = head->output_offset;
5087 bfd_vma end_of_next;
906e58ca 5088
07d72278 5089 curr = head;
e780aef2 5090 while (NEXT_SEC (curr) != NULL)
8cd931b7 5091 {
e780aef2
CL		 5092 next = NEXT_SEC (curr);
5093 end_of_next = next->output_offset + next->size;
5094 if (end_of_next - stub_group_start >= stub_group_size)
5095 /* End of NEXT is too far from start, so stop. */
8cd931b7 5096 break;
e780aef2
CL		 5097 /* Add NEXT to the group. */
5098 curr = next;
8cd931b7 5099 }
906e58ca 5100
07d72278 5101 /* OK, the size from the start to the start of CURR is less
906e58ca 5102 than stub_group_size and thus can be handled by one stub
07d72278 5103 section. (Or the head section is itself larger than
906e58ca
NC		 5104 stub_group_size, in which case we may be toast.)
5105 We should really be keeping track of the total size of
5106 stubs added here, as stubs contribute to the final output
7fb9f789 5107 section size. */
906e58ca
NC		 5108 do
5109 {
07d72278 5110 next = NEXT_SEC (head);
906e58ca 5111 /* Set up this stub group. */
07d72278 5112 htab->stub_group[head->id].link_sec = curr;
906e58ca 5113 }
07d72278 5114 while (head != curr && (head = next) != NULL);
906e58ca
NC		 5115
5116 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 5117 bytes after the stub section can be handled by it too. */
5118 if (!stubs_always_after_branch)
906e58ca 5119 {
e780aef2
CL		 5120 stub_group_start = curr->output_offset + curr->size;
5121
8cd931b7 5122 while (next != NULL)
906e58ca 5123 {
e780aef2
CL		 5124 end_of_next = next->output_offset + next->size;
5125 if (end_of_next - stub_group_start >= stub_group_size)
5126 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 5127 break;
e780aef2 5128 /* Add NEXT to the stub group. */
07d72278
DJ		 5129 head = next;
5130 next = NEXT_SEC (head);
5131 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 5132 }
5133 }
07d72278 5134 head = next;
906e58ca
NC		 5135 }
5136 }
07d72278 5137 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 5138
5139 free (htab->input_list);
5140#undef PREV_SEC
07d72278 5141#undef NEXT_SEC
906e58ca
NC		 5142}
5143
48229727
JB		 5144/* Comparison function for sorting/searching relocations relating to Cortex-A8
5145 erratum fix. */
5146
5147static int
5148a8_reloc_compare (const void *a, const void *b)
5149{
21d799b5
NC		 5150 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5151 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 5152
5153 if (ra->from < rb->from)
5154 return -1;
5155 else if (ra->from > rb->from)
5156 return 1;
5157 else
5158 return 0;
5159}
5160
5161static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5162 const char *, char **);
5163
5164/* Helper function to scan code for sequences which might trigger the Cortex-A8
5165 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 5166 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 5167 otherwise. */
5168
81694485
NC		 5169static bfd_boolean
5170cortex_a8_erratum_scan (bfd *input_bfd,
5171 struct bfd_link_info *info,
48229727
JB		 5172 struct a8_erratum_fix **a8_fixes_p,
5173 unsigned int *num_a8_fixes_p,
5174 unsigned int *a8_fix_table_size_p,
5175 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 5176 unsigned int num_a8_relocs,
5177 unsigned prev_num_a8_fixes,
5178 bfd_boolean *stub_changed_p)
48229727
JB		 5179{
5180 asection *section;
5181 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5182 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5183 unsigned int num_a8_fixes = *num_a8_fixes_p;
5184 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5185
4dfe6ac6
NC		 5186 if (htab == NULL)
5187 return FALSE;
5188
48229727
JB		 5189 for (section = input_bfd->sections;
5190 section != NULL;
5191 section = section->next)
5192 {
5193 bfd_byte *contents = NULL;
5194 struct _arm_elf_section_data *sec_data;
5195 unsigned int span;
5196 bfd_vma base_vma;
5197
5198 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 5199 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5200 || (section->flags & SEC_EXCLUDE) != 0
5201 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5202 || (section->output_section == bfd_abs_section_ptr))
5203 continue;
48229727
JB		 5204
5205 base_vma = section->output_section->vma + section->output_offset;
5206
5207 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 5208 contents = elf_section_data (section)->this_hdr.contents;
48229727 5209 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 5210 return TRUE;
48229727
JB		 5211
5212 sec_data = elf32_arm_section_data (section);
5213
5214 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 5215 {
5216 unsigned int span_start = sec_data->map[span].vma;
5217 unsigned int span_end = (span == sec_data->mapcount - 1)
5218 ? section->size : sec_data->map[span + 1].vma;
5219 unsigned int i;
5220 char span_type = sec_data->map[span].type;
5221 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
5222
5223 if (span_type != 't')
5224 continue;
5225
5226 /* Span is entirely within a single 4KB region: skip scanning. */
5227 if (((base_vma + span_start) & ~0xfff)
48229727 5228 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 5229 continue;
5230
5231 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5232
5233 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5234 * The branch target is in the same 4KB region as the
5235 first half of the branch.
5236 * The instruction before the branch is a 32-bit
5237 length non-branch instruction. */
5238 for (i = span_start; i < span_end;)
5239 {
5240 unsigned int insn = bfd_getl16 (&contents[i]);
5241 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 5242 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
5243
99059e56
RM		 5244 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5245 insn_32bit = TRUE;
48229727
JB		 5246
5247 if (insn_32bit)
99059e56
RM		 5248 {
5249 /* Load the rest of the insn (in manual-friendly order). */
5250 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5251
5252 /* Encoding T4: B<c>.W. */
5253 is_b = (insn & 0xf800d000) == 0xf0009000;
5254 /* Encoding T1: BL<c>.W. */
5255 is_bl = (insn & 0xf800d000) == 0xf000d000;
5256 /* Encoding T2: BLX<c>.W. */
5257 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5258 /* Encoding T3: B<c>.W (not permitted in IT block). */
5259 is_bcc = (insn & 0xf800d000) == 0xf0008000
5260 && (insn & 0x07f00000) != 0x03800000;
5261 }
5262
5263 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5264
99059e56 5265 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5266 && insn_32bit
5267 && is_32bit_branch
5268 && last_was_32bit
5269 && ! last_was_branch)
99059e56
RM		 5270 {
5271 bfd_signed_vma offset = 0;
5272 bfd_boolean force_target_arm = FALSE;
48229727 5273 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5274 bfd_vma target;
5275 enum elf32_arm_stub_type stub_type = arm_stub_none;
5276 struct a8_erratum_reloc key, *found;
5277 bfd_boolean use_plt = FALSE;
48229727 5278
99059e56
RM		 5279 key.from = base_vma + i;
5280 found = (struct a8_erratum_reloc *)
5281 bsearch (&key, a8_relocs, num_a8_relocs,
5282 sizeof (struct a8_erratum_reloc),
5283 &a8_reloc_compare);
48229727
JB		 5284
5285 if (found)
5286 {
5287 char *error_message = NULL;
5288 struct elf_link_hash_entry *entry;
5289
5290 /* We don't care about the error returned from this
99059e56 5291 function, only if there is glue or not. */
48229727
JB		 5292 entry = find_thumb_glue (info, found->sym_name,
5293 &error_message);
5294
5295 if (entry)
5296 found->non_a8_stub = TRUE;
5297
92750f34 5298 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5299 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5300 && found->hash->root.plt.offset != (bfd_vma) -1)
5301 use_plt = TRUE;
5302
5303 if (found->r_type == R_ARM_THM_CALL)
5304 {
35fc36a8
RS		 5305 if (found->branch_type == ST_BRANCH_TO_ARM
5306 || use_plt)
92750f34
DJ		 5307 force_target_arm = TRUE;
5308 else
5309 force_target_thumb = TRUE;
5310 }
48229727
JB		 5311 }
5312
99059e56 5313 /* Check if we have an offending branch instruction. */
48229727
JB		 5314
5315 if (found && found->non_a8_stub)
5316 /* We've already made a stub for this instruction, e.g.
5317 it's a long branch or a Thumb->ARM stub. Assume that
5318 stub will suffice to work around the A8 erratum (see
5319 setting of always_after_branch above). */
5320 ;
99059e56
RM		 5321 else if (is_bcc)
5322 {
5323 offset = (insn & 0x7ff) << 1;
5324 offset |= (insn & 0x3f0000) >> 4;
5325 offset |= (insn & 0x2000) ? 0x40000 : 0;
5326 offset |= (insn & 0x800) ? 0x80000 : 0;
5327 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5328 if (offset & 0x100000)
5329 offset |= ~ ((bfd_signed_vma) 0xfffff);
5330 stub_type = arm_stub_a8_veneer_b_cond;
5331 }
5332 else if (is_b || is_bl || is_blx)
5333 {
5334 int s = (insn & 0x4000000) != 0;
5335 int j1 = (insn & 0x2000) != 0;
5336 int j2 = (insn & 0x800) != 0;
5337 int i1 = !(j1 ^ s);
5338 int i2 = !(j2 ^ s);
5339
5340 offset = (insn & 0x7ff) << 1;
5341 offset |= (insn & 0x3ff0000) >> 4;
5342 offset |= i2 << 22;
5343 offset |= i1 << 23;
5344 offset |= s << 24;
5345 if (offset & 0x1000000)
5346 offset |= ~ ((bfd_signed_vma) 0xffffff);
5347
5348 if (is_blx)
5349 offset &= ~ ((bfd_signed_vma) 3);
5350
5351 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5352 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5353 }
5354
5355 if (stub_type != arm_stub_none)
5356 {
5357 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5358
5359 /* The original instruction is a BL, but the target is
99059e56 5360 an ARM instruction. If we were not making a stub,
48229727
JB		 5361 the BL would have been converted to a BLX. Use the
5362 BLX stub instead in that case. */
5363 if (htab->use_blx && force_target_arm
5364 && stub_type == arm_stub_a8_veneer_bl)
5365 {
5366 stub_type = arm_stub_a8_veneer_blx;
5367 is_blx = TRUE;
5368 is_bl = FALSE;
5369 }
5370 /* Conversely, if the original instruction was
5371 BLX but the target is Thumb mode, use the BL
5372 stub. */
5373 else if (force_target_thumb
5374 && stub_type == arm_stub_a8_veneer_blx)
5375 {
5376 stub_type = arm_stub_a8_veneer_bl;
5377 is_blx = FALSE;
5378 is_bl = TRUE;
5379 }
5380
99059e56
RM		 5381 if (is_blx)
5382 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5383
99059e56
RM		 5384 /* If we found a relocation, use the proper destination,
5385 not the offset in the (unrelocated) instruction.
48229727
JB		 5386 Note this is always done if we switched the stub type
5387 above. */
99059e56
RM		 5388 if (found)
5389 offset =
81694485 5390 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5391
99059e56
RM		 5392 /* If the stub will use a Thumb-mode branch to a
5393 PLT target, redirect it to the preceding Thumb
5394 entry point. */
5395 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5396 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5397
99059e56 5398 target = pc_for_insn + offset;
48229727 5399
99059e56
RM		 5400 /* The BLX stub is ARM-mode code. Adjust the offset to
5401 take the different PC value (+8 instead of +4) into
48229727 5402 account. */
99059e56
RM		 5403 if (stub_type == arm_stub_a8_veneer_blx)
5404 offset += 4;
5405
5406 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5407 {
5408 char *stub_name = NULL;
5409
5410 if (num_a8_fixes == a8_fix_table_size)
5411 {
5412 a8_fix_table_size *= 2;
5413 a8_fixes = (struct a8_erratum_fix *)
5414 bfd_realloc (a8_fixes,
5415 sizeof (struct a8_erratum_fix)
5416 * a8_fix_table_size);
5417 }
48229727 5418
eb7c4339
NS		 5419 if (num_a8_fixes < prev_num_a8_fixes)
5420 {
5421 /* If we're doing a subsequent scan,
5422 check if we've found the same fix as
5423 before, and try and reuse the stub
5424 name. */
5425 stub_name = a8_fixes[num_a8_fixes].stub_name;
5426 if ((a8_fixes[num_a8_fixes].section != section)
5427 || (a8_fixes[num_a8_fixes].offset != i))
5428 {
5429 free (stub_name);
5430 stub_name = NULL;
5431 *stub_changed_p = TRUE;
5432 }
5433 }
5434
5435 if (!stub_name)
5436 {
21d799b5 5437 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5438 if (stub_name != NULL)
5439 sprintf (stub_name, "%x:%x", section->id, i);
5440 }
48229727 5441
99059e56
RM		 5442 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5443 a8_fixes[num_a8_fixes].section = section;
5444 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5445 a8_fixes[num_a8_fixes].target_offset =
5446 target - base_vma;
99059e56
RM		 5447 a8_fixes[num_a8_fixes].orig_insn = insn;
5448 a8_fixes[num_a8_fixes].stub_name = stub_name;
5449 a8_fixes[num_a8_fixes].stub_type = stub_type;
5450 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5451 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5452
99059e56
RM		 5453 num_a8_fixes++;
5454 }
5455 }
5456 }
48229727 5457
99059e56
RM		 5458 i += insn_32bit ? 4 : 2;
5459 last_was_32bit = insn_32bit;
48229727 5460 last_was_branch = is_32bit_branch;
99059e56
RM		 5461 }
5462 }
48229727
JB		 5463
5464 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5465 free (contents);
48229727 5466 }
fe33d2fa 5467
48229727
JB		 5468 *a8_fixes_p = a8_fixes;
5469 *num_a8_fixes_p = num_a8_fixes;
5470 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5471
81694485 5472 return FALSE;
48229727
JB		 5473}
5474
b715f643
TP		 5475/* Create or update a stub entry depending on whether the stub can already be
5476 found in HTAB. The stub is identified by:
5477 - its type STUB_TYPE
5478 - its source branch (note that several can share the same stub) whose
5479 section and relocation (if any) are given by SECTION and IRELA
5480 respectively
5481 - its target symbol whose input section, hash, name, value and branch type
5482 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5483 respectively
5484
5485 If found, the value of the stub's target symbol is updated from SYM_VALUE
5486 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5487 TRUE and the stub entry is initialized.
5488
0955507f
TP		 5489 Returns the stub that was created or updated, or NULL if an error
5490 occurred. */
b715f643 5491
0955507f 5492static struct elf32_arm_stub_hash_entry *
b715f643
TP		 5493elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5494 enum elf32_arm_stub_type stub_type, asection *section,
5495 Elf_Internal_Rela *irela, asection *sym_sec,
5496 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5497 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5498 bfd_boolean *new_stub)
5499{
5500 const asection *id_sec;
5501 char *stub_name;
5502 struct elf32_arm_stub_hash_entry *stub_entry;
5503 unsigned int r_type;
4f4faa4d 5504 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5505
5506 BFD_ASSERT (stub_type != arm_stub_none);
5507 *new_stub = FALSE;
5508
4f4faa4d
TP		 5509 if (sym_claimed)
5510 stub_name = sym_name;
5511 else
5512 {
5513 BFD_ASSERT (irela);
5514 BFD_ASSERT (section);
c2abbbeb 5515 BFD_ASSERT (section->id <= htab->top_id);
b715f643 5516
4f4faa4d
TP		 5517 /* Support for grouping stub sections. */
5518 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5519
4f4faa4d
TP		 5520 /* Get the name of this stub. */
5521 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5522 stub_type);
5523 if (!stub_name)
0955507f 5524 return NULL;
4f4faa4d 5525 }
b715f643
TP		 5526
5527 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5528 FALSE);
5529 /* The proper stub has already been created, just update its value. */
5530 if (stub_entry != NULL)
5531 {
4f4faa4d
TP		 5532 if (!sym_claimed)
5533 free (stub_name);
b715f643 5534 stub_entry->target_value = sym_value;
0955507f 5535 return stub_entry;
b715f643
TP		 5536 }
5537
daa4adae 5538 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5539 if (stub_entry == NULL)
5540 {
4f4faa4d
TP		 5541 if (!sym_claimed)
5542 free (stub_name);
0955507f 5543 return NULL;
b715f643
TP		 5544 }
5545
5546 stub_entry->target_value = sym_value;
5547 stub_entry->target_section = sym_sec;
5548 stub_entry->stub_type = stub_type;
5549 stub_entry->h = hash;
5550 stub_entry->branch_type = branch_type;
5551
4f4faa4d
TP		 5552 if (sym_claimed)
5553 stub_entry->output_name = sym_name;
5554 else
b715f643 5555 {
4f4faa4d
TP		 5556 if (sym_name == NULL)
5557 sym_name = "unnamed";
5558 stub_entry->output_name = (char *)
5559 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5560 + strlen (sym_name));
5561 if (stub_entry->output_name == NULL)
5562 {
5563 free (stub_name);
0955507f 5564 return NULL;
4f4faa4d 5565 }
b715f643 5566
4f4faa4d
TP		 5567 /* For historical reasons, use the existing names for ARM-to-Thumb and
5568 Thumb-to-ARM stubs. */
5569 r_type = ELF32_R_TYPE (irela->r_info);
5570 if ((r_type == (unsigned int) R_ARM_THM_CALL
5571 || r_type == (unsigned int) R_ARM_THM_JUMP24
5572 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5573 && branch_type == ST_BRANCH_TO_ARM)
5574 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5575 else if ((r_type == (unsigned int) R_ARM_CALL
5576 || r_type == (unsigned int) R_ARM_JUMP24)
5577 && branch_type == ST_BRANCH_TO_THUMB)
5578 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5579 else
5580 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5581 }
b715f643
TP		 5582
5583 *new_stub = TRUE;
0955507f 5584 return stub_entry;
b715f643
TP		 5585}
5586
4ba2ef8f
TP		 5587/* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5588 gateway veneer to transition from non secure to secure state and create them
5589 accordingly.
5590
5591 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5592 defines the conditions that govern Secure Gateway veneer creation for a
5593 given symbol <SYM> as follows:
5594 - it has function type
5595 - it has non local binding
5596 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5597 same type, binding and value as <SYM> (called normal symbol).
5598 An entry function can handle secure state transition itself in which case
5599 its special symbol would have a different value from the normal symbol.
5600
5601 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5602 entry mapping while HTAB gives the name to hash entry mapping.
0955507f
TP		 5603 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5604 created.
4ba2ef8f 5605
0955507f 5606 The return value gives whether a stub failed to be allocated. */
4ba2ef8f
TP		 5607
5608static bfd_boolean
5609cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5610 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
0955507f 5611 int *cmse_stub_created)
4ba2ef8f
TP		 5612{
5613 const struct elf_backend_data *bed;
5614 Elf_Internal_Shdr *symtab_hdr;
5615 unsigned i, j, sym_count, ext_start;
5616 Elf_Internal_Sym *cmse_sym, *local_syms;
5617 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5618 enum arm_st_branch_type branch_type;
5619 char *sym_name, *lsym_name;
5620 bfd_vma sym_value;
5621 asection *section;
0955507f
TP		 5622 struct elf32_arm_stub_hash_entry *stub_entry;
5623 bfd_boolean is_v8m, new_stub, cmse_invalid, ret = TRUE;
4ba2ef8f
TP		 5624
5625 bed = get_elf_backend_data (input_bfd);
5626 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5627 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5628 ext_start = symtab_hdr->sh_info;
5629 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5630 && out_attr[Tag_CPU_arch_profile].i == 'M');
5631
5632 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5633 if (local_syms == NULL)
5634 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5635 symtab_hdr->sh_info, 0, NULL, NULL,
5636 NULL);
5637 if (symtab_hdr->sh_info && local_syms == NULL)
5638 return FALSE;
5639
5640 /* Scan symbols. */
5641 for (i = 0; i < sym_count; i++)
5642 {
5643 cmse_invalid = FALSE;
5644
5645 if (i < ext_start)
5646 {
5647 cmse_sym = &local_syms[i];
5648 /* Not a special symbol. */
5649 if (!ARM_GET_SYM_CMSE_SPCL (cmse_sym->st_target_internal))
5650 continue;
5651 sym_name = bfd_elf_string_from_elf_section (input_bfd,
5652 symtab_hdr->sh_link,
5653 cmse_sym->st_name);
5654 /* Special symbol with local binding. */
5655 cmse_invalid = TRUE;
5656 }
5657 else
5658 {
5659 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
5660 sym_name = (char *) cmse_hash->root.root.root.string;
5661
5662 /* Not a special symbol. */
5663 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
5664 continue;
5665
5666 /* Special symbol has incorrect binding or type. */
5667 if ((cmse_hash->root.root.type != bfd_link_hash_defined
5668 && cmse_hash->root.root.type != bfd_link_hash_defweak)
5669 || cmse_hash->root.type != STT_FUNC)
5670 cmse_invalid = TRUE;
5671 }
5672
5673 if (!is_v8m)
5674 {
90b6238f
AM		 5675 _bfd_error_handler (_("%pB: special symbol `%s' only allowed for "
5676 "ARMv8-M architecture or later"),
4eca0228 5677 input_bfd, sym_name);
4ba2ef8f
TP		 5678 is_v8m = TRUE; /* Avoid multiple warning. */
5679 ret = FALSE;
5680 }
5681
5682 if (cmse_invalid)
5683 {
90b6238f
AM		 5684 _bfd_error_handler (_("%pB: invalid special symbol `%s'; it must be"
5685 " a global or weak function symbol"),
4eca0228 5686 input_bfd, sym_name);
4ba2ef8f
TP		 5687 ret = FALSE;
5688 if (i < ext_start)
5689 continue;
5690 }
5691
5692 sym_name += strlen (CMSE_PREFIX);
5693 hash = (struct elf32_arm_link_hash_entry *)
5694 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5695
5696 /* No associated normal symbol or it is neither global nor weak. */
5697 if (!hash
5698 || (hash->root.root.type != bfd_link_hash_defined
5699 && hash->root.root.type != bfd_link_hash_defweak)
5700 || hash->root.type != STT_FUNC)
5701 {
5702 /* Initialize here to avoid warning about use of possibly
5703 uninitialized variable. */
5704 j = 0;
5705
5706 if (!hash)
5707 {
5708 /* Searching for a normal symbol with local binding. */
5709 for (; j < ext_start; j++)
5710 {
5711 lsym_name =
5712 bfd_elf_string_from_elf_section (input_bfd,
5713 symtab_hdr->sh_link,
5714 local_syms[j].st_name);
5715 if (!strcmp (sym_name, lsym_name))
5716 break;
5717 }
5718 }
5719
5720 if (hash || j < ext_start)
5721 {
4eca0228 5722 _bfd_error_handler
90b6238f
AM		 5723 (_("%pB: invalid standard symbol `%s'; it must be "
5724 "a global or weak function symbol"),
5725 input_bfd, sym_name);
4ba2ef8f
TP		 5726 }
5727 else
4eca0228 5728 _bfd_error_handler
90b6238f 5729 (_("%pB: absent standard symbol `%s'"), input_bfd, sym_name);
4ba2ef8f
TP		 5730 ret = FALSE;
5731 if (!hash)
5732 continue;
5733 }
5734
5735 sym_value = hash->root.root.u.def.value;
5736 section = hash->root.root.u.def.section;
5737
5738 if (cmse_hash->root.root.u.def.section != section)
5739 {
4eca0228 5740 _bfd_error_handler
90b6238f 5741 (_("%pB: `%s' and its special symbol are in different sections"),
4ba2ef8f
TP		 5742 input_bfd, sym_name);
5743 ret = FALSE;
5744 }
5745 if (cmse_hash->root.root.u.def.value != sym_value)
5746 continue; /* Ignore: could be an entry function starting with SG. */
5747
5748 /* If this section is a link-once section that will be discarded, then
5749 don't create any stubs. */
5750 if (section->output_section == NULL)
5751 {
4eca0228 5752 _bfd_error_handler
90b6238f 5753 (_("%pB: entry function `%s' not output"), input_bfd, sym_name);
4ba2ef8f
TP		 5754 continue;
5755 }
5756
5757 if (hash->root.size == 0)
5758 {
4eca0228 5759 _bfd_error_handler
90b6238f 5760 (_("%pB: entry function `%s' is empty"), input_bfd, sym_name);
4ba2ef8f
TP		 5761 ret = FALSE;
5762 }
5763
5764 if (!ret)
5765 continue;
5766 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
0955507f 5767 stub_entry
4ba2ef8f
TP		 5768 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5769 NULL, NULL, section, hash, sym_name,
5770 sym_value, branch_type, &new_stub);
5771
0955507f 5772 if (stub_entry == NULL)
4ba2ef8f
TP		 5773 ret = FALSE;
5774 else
5775 {
5776 BFD_ASSERT (new_stub);
0955507f 5777 (*cmse_stub_created)++;
4ba2ef8f
TP		 5778 }
5779 }
5780
5781 if (!symtab_hdr->contents)
5782 free (local_syms);
5783 return ret;
5784}
5785
0955507f
TP		 5786/* Return TRUE iff a symbol identified by its linker HASH entry is a secure
5787 code entry function, ie can be called from non secure code without using a
5788 veneer. */
5789
5790static bfd_boolean
5791cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
5792{
42484486 5793 bfd_byte contents[4];
0955507f
TP		 5794 uint32_t first_insn;
5795 asection *section;
5796 file_ptr offset;
5797 bfd *abfd;
5798
5799 /* Defined symbol of function type. */
5800 if (hash->root.root.type != bfd_link_hash_defined
5801 && hash->root.root.type != bfd_link_hash_defweak)
5802 return FALSE;
5803 if (hash->root.type != STT_FUNC)
5804 return FALSE;
5805
5806 /* Read first instruction. */
5807 section = hash->root.root.u.def.section;
5808 abfd = section->owner;
5809 offset = hash->root.root.u.def.value - section->vma;
42484486
TP		 5810 if (!bfd_get_section_contents (abfd, section, contents, offset,
5811 sizeof (contents)))
0955507f
TP		 5812 return FALSE;
5813
42484486
TP		 5814 first_insn = bfd_get_32 (abfd, contents);
5815
5816 /* Starts by SG instruction. */
0955507f
TP		 5817 return first_insn == 0xe97fe97f;
5818}
5819
5820/* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
5821 secure gateway veneers (ie. the veneers was not in the input import library)
5822 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
5823
5824static bfd_boolean
5825arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
5826{
5827 struct elf32_arm_stub_hash_entry *stub_entry;
5828 struct bfd_link_info *info;
5829
5830 /* Massage our args to the form they really have. */
5831 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5832 info = (struct bfd_link_info *) gen_info;
5833
5834 if (info->out_implib_bfd)
5835 return TRUE;
5836
5837 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
5838 return TRUE;
5839
5840 if (stub_entry->stub_offset == (bfd_vma) -1)
4eca0228 5841 _bfd_error_handler (" %s", stub_entry->output_name);
0955507f
TP		 5842
5843 return TRUE;
5844}
5845
5846/* Set offset of each secure gateway veneers so that its address remain
5847 identical to the one in the input import library referred by
5848 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
5849 (present in input import library but absent from the executable being
5850 linked) or if new veneers appeared and there is no output import library
5851 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
5852 number of secure gateway veneers found in the input import library.
5853
5854 The function returns whether an error occurred. If no error occurred,
5855 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
5856 and this function and HTAB->new_cmse_stub_offset is set to the biggest
5857 veneer observed set for new veneers to be layed out after. */
5858
5859static bfd_boolean
5860set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
5861 struct elf32_arm_link_hash_table *htab,
5862 int *cmse_stub_created)
5863{
5864 long symsize;
5865 char *sym_name;
5866 flagword flags;
5867 long i, symcount;
5868 bfd *in_implib_bfd;
5869 asection *stub_out_sec;
5870 bfd_boolean ret = TRUE;
5871 Elf_Internal_Sym *intsym;
5872 const char *out_sec_name;
5873 bfd_size_type cmse_stub_size;
5874 asymbol **sympp = NULL, *sym;
5875 struct elf32_arm_link_hash_entry *hash;
5876 const insn_sequence *cmse_stub_template;
5877 struct elf32_arm_stub_hash_entry *stub_entry;
5878 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
5879 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
5880 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
5881
5882 /* No input secure gateway import library. */
5883 if (!htab->in_implib_bfd)
5884 return TRUE;
5885
5886 in_implib_bfd = htab->in_implib_bfd;
5887 if (!htab->cmse_implib)
5888 {
871b3ab2 5889 _bfd_error_handler (_("%pB: --in-implib only supported for Secure "
90b6238f 5890 "Gateway import libraries"), in_implib_bfd);
0955507f
TP		 5891 return FALSE;
5892 }
5893
5894 /* Get symbol table size. */
5895 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
5896 if (symsize < 0)
5897 return FALSE;
5898
5899 /* Read in the input secure gateway import library's symbol table. */
5900 sympp = (asymbol **) xmalloc (symsize);
5901 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
5902 if (symcount < 0)
5903 {
5904 ret = FALSE;
5905 goto free_sym_buf;
5906 }
5907
5908 htab->new_cmse_stub_offset = 0;
5909 cmse_stub_size =
5910 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
5911 &cmse_stub_template,
5912 &cmse_stub_template_size);
5913 out_sec_name =
5914 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
5915 stub_out_sec =
5916 bfd_get_section_by_name (htab->obfd, out_sec_name);
5917 if (stub_out_sec != NULL)
5918 cmse_stub_sec_vma = stub_out_sec->vma;
5919
5920 /* Set addresses of veneers mentionned in input secure gateway import
5921 library's symbol table. */
5922 for (i = 0; i < symcount; i++)
5923 {
5924 sym = sympp[i];
5925 flags = sym->flags;
5926 sym_name = (char *) bfd_asymbol_name (sym);
5927 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
5928
5929 if (sym->section != bfd_abs_section_ptr
5930 || !(flags & (BSF_GLOBAL | BSF_WEAK))
5931 || (flags & BSF_FUNCTION) != BSF_FUNCTION
5932 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
5933 != ST_BRANCH_TO_THUMB))
5934 {
90b6238f
AM		 5935 _bfd_error_handler (_("%pB: invalid import library entry: `%s'; "
5936 "symbol should be absolute, global and "
5937 "refer to Thumb functions"),
4eca0228 5938 in_implib_bfd, sym_name);
0955507f
TP		 5939 ret = FALSE;
5940 continue;
5941 }
5942
5943 veneer_value = bfd_asymbol_value (sym);
5944 stub_offset = veneer_value - cmse_stub_sec_vma;
5945 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
5946 FALSE, FALSE);
5947 hash = (struct elf32_arm_link_hash_entry *)
5948 elf_link_hash_lookup (&(htab)->root, sym_name, FALSE, FALSE, TRUE);
5949
5950 /* Stub entry should have been created by cmse_scan or the symbol be of
5951 a secure function callable from non secure code. */
5952 if (!stub_entry && !hash)
5953 {
5954 bfd_boolean new_stub;
5955
4eca0228 5956 _bfd_error_handler
90b6238f 5957 (_("entry function `%s' disappeared from secure code"), sym_name);
0955507f
TP		 5958 hash = (struct elf32_arm_link_hash_entry *)
5959 elf_link_hash_lookup (&(htab)->root, sym_name, TRUE, TRUE, TRUE);
5960 stub_entry
5961 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
5962 NULL, NULL, bfd_abs_section_ptr, hash,
5963 sym_name, veneer_value,
5964 ST_BRANCH_TO_THUMB, &new_stub);
5965 if (stub_entry == NULL)
5966 ret = FALSE;
5967 else
5968 {
5969 BFD_ASSERT (new_stub);
5970 new_cmse_stubs_created++;
5971 (*cmse_stub_created)++;
5972 }
5973 stub_entry->stub_template_size = stub_entry->stub_size = 0;
5974 stub_entry->stub_offset = stub_offset;
5975 }
5976 /* Symbol found is not callable from non secure code. */
5977 else if (!stub_entry)
5978 {
5979 if (!cmse_entry_fct_p (hash))
5980 {
90b6238f 5981 _bfd_error_handler (_("`%s' refers to a non entry function"),
4eca0228 5982 sym_name);
0955507f
TP		 5983 ret = FALSE;
5984 }
5985 continue;
5986 }
5987 else
5988 {
5989 /* Only stubs for SG veneers should have been created. */
5990 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5991
5992 /* Check visibility hasn't changed. */
5993 if (!!(flags & BSF_GLOBAL)
5994 != (hash->root.root.type == bfd_link_hash_defined))
4eca0228 5995 _bfd_error_handler
90b6238f 5996 (_("%pB: visibility of symbol `%s' has changed"), in_implib_bfd,
0955507f
TP		 5997 sym_name);
5998
5999 stub_entry->stub_offset = stub_offset;
6000 }
6001
6002 /* Size should match that of a SG veneer. */
6003 if (intsym->st_size != cmse_stub_size)
6004 {
90b6238f 6005 _bfd_error_handler (_("%pB: incorrect size for symbol `%s'"),
4eca0228 6006 in_implib_bfd, sym_name);
0955507f
TP		 6007 ret = FALSE;
6008 }
6009
6010 /* Previous veneer address is before current SG veneer section. */
6011 if (veneer_value < cmse_stub_sec_vma)
6012 {
6013 /* Avoid offset underflow. */
6014 if (stub_entry)
6015 stub_entry->stub_offset = 0;
6016 stub_offset = 0;
6017 ret = FALSE;
6018 }
6019
6020 /* Complain if stub offset not a multiple of stub size. */
6021 if (stub_offset % cmse_stub_size)
6022 {
4eca0228 6023 _bfd_error_handler
90b6238f
AM		 6024 (_("offset of veneer for entry function `%s' not a multiple of "
6025 "its size"), sym_name);
0955507f
TP		 6026 ret = FALSE;
6027 }
6028
6029 if (!ret)
6030 continue;
6031
6032 new_cmse_stubs_created--;
6033 if (veneer_value < cmse_stub_array_start)
6034 cmse_stub_array_start = veneer_value;
6035 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6036 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6037 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6038 }
6039
6040 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6041 {
6042 BFD_ASSERT (new_cmse_stubs_created > 0);
4eca0228 6043 _bfd_error_handler
0955507f
TP		 6044 (_("new entry function(s) introduced but no output import library "
6045 "specified:"));
6046 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6047 }
6048
6049 if (cmse_stub_array_start != cmse_stub_sec_vma)
6050 {
4eca0228 6051 _bfd_error_handler
90b6238f 6052 (_("start address of `%s' is different from previous link"),
0955507f
TP		 6053 out_sec_name);
6054 ret = FALSE;
6055 }
6056
6057free_sym_buf:
6058 free (sympp);
6059 return ret;
6060}
6061
906e58ca
NC		 6062/* Determine and set the size of the stub section for a final link.
6063
6064 The basic idea here is to examine all the relocations looking for
6065 PC-relative calls to a target that is unreachable with a "bl"
6066 instruction. */
6067
6068bfd_boolean
6069elf32_arm_size_stubs (bfd *output_bfd,
6070 bfd *stub_bfd,
6071 struct bfd_link_info *info,
6072 bfd_signed_vma group_size,
7a89b94e 6073 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 6074 asection *,
7a89b94e 6075 unsigned int),
906e58ca
NC		 6076 void (*layout_sections_again) (void))
6077{
0955507f 6078 bfd_boolean ret = TRUE;
4ba2ef8f 6079 obj_attribute *out_attr;
0955507f 6080 int cmse_stub_created = 0;
906e58ca 6081 bfd_size_type stub_group_size;
4ba2ef8f 6082 bfd_boolean m_profile, stubs_always_after_branch, first_veneer_scan = TRUE;
906e58ca 6083 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 6084 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 6085 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 6086 struct a8_erratum_reloc *a8_relocs = NULL;
6087 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6088
4dfe6ac6
NC		 6089 if (htab == NULL)
6090 return FALSE;
6091
48229727
JB		 6092 if (htab->fix_cortex_a8)
6093 {
21d799b5 6094 a8_fixes = (struct a8_erratum_fix *)
99059e56 6095 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 6096 a8_relocs = (struct a8_erratum_reloc *)
99059e56 6097 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 6098 }
906e58ca
NC		 6099
6100 /* Propagate mach to stub bfd, because it may not have been
6101 finalized when we created stub_bfd. */
6102 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6103 bfd_get_mach (output_bfd));
6104
6105 /* Stash our params away. */
6106 htab->stub_bfd = stub_bfd;
6107 htab->add_stub_section = add_stub_section;
6108 htab->layout_sections_again = layout_sections_again;
07d72278 6109 stubs_always_after_branch = group_size < 0;
48229727 6110
4ba2ef8f
TP		 6111 out_attr = elf_known_obj_attributes_proc (output_bfd);
6112 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
0955507f 6113
48229727
JB		 6114 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6115 as the first half of a 32-bit branch straddling two 4K pages. This is a
6116 crude way of enforcing that. */
6117 if (htab->fix_cortex_a8)
6118 stubs_always_after_branch = 1;
6119
906e58ca
NC		 6120 if (group_size < 0)
6121 stub_group_size = -group_size;
6122 else
6123 stub_group_size = group_size;
6124
6125 if (stub_group_size == 1)
6126 {
6127 /* Default values. */
6128 /* Thumb branch range is +-4MB has to be used as the default
6129 maximum size (a given section can contain both ARM and Thumb
6130 code, so the worst case has to be taken into account).
6131
6132 This value is 24K less than that, which allows for 2025
6133 12-byte stubs. If we exceed that, then we will fail to link.
6134 The user will have to relink with an explicit group size
6135 option. */
6136 stub_group_size = 4170000;
6137 }
6138
07d72278 6139 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 6140
3ae046cc
NS		 6141 /* If we're applying the cortex A8 fix, we need to determine the
6142 program header size now, because we cannot change it later --
6143 that could alter section placements. Notice the A8 erratum fix
6144 ends up requiring the section addresses to remain unchanged
6145 modulo the page size. That's something we cannot represent
6146 inside BFD, and we don't want to force the section alignment to
6147 be the page size. */
6148 if (htab->fix_cortex_a8)
6149 (*htab->layout_sections_again) ();
6150
906e58ca
NC		 6151 while (1)
6152 {
6153 bfd *input_bfd;
6154 unsigned int bfd_indx;
6155 asection *stub_sec;
d7c5bd02 6156 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 6157 bfd_boolean stub_changed = FALSE;
6158 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 6159
48229727 6160 num_a8_fixes = 0;
906e58ca
NC		 6161 for (input_bfd = info->input_bfds, bfd_indx = 0;
6162 input_bfd != NULL;
c72f2fb2 6163 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 6164 {
6165 Elf_Internal_Shdr *symtab_hdr;
6166 asection *section;
6167 Elf_Internal_Sym *local_syms = NULL;
6168
99059e56
RM		 6169 if (!is_arm_elf (input_bfd))
6170 continue;
adbcc655 6171
48229727
JB		 6172 num_a8_relocs = 0;
6173
906e58ca
NC		 6174 /* We'll need the symbol table in a second. */
6175 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6176 if (symtab_hdr->sh_info == 0)
6177 continue;
6178
4ba2ef8f
TP		 6179 /* Limit scan of symbols to object file whose profile is
6180 Microcontroller to not hinder performance in the general case. */
6181 if (m_profile && first_veneer_scan)
6182 {
6183 struct elf_link_hash_entry **sym_hashes;
6184
6185 sym_hashes = elf_sym_hashes (input_bfd);
6186 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
0955507f 6187 &cmse_stub_created))
4ba2ef8f 6188 goto error_ret_free_local;
0955507f
TP		 6189
6190 if (cmse_stub_created != 0)
6191 stub_changed = TRUE;
4ba2ef8f
TP		 6192 }
6193
906e58ca
NC		 6194 /* Walk over each section attached to the input bfd. */
6195 for (section = input_bfd->sections;
6196 section != NULL;
6197 section = section->next)
6198 {
6199 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6200
6201 /* If there aren't any relocs, then there's nothing more
6202 to do. */
6203 if ((section->flags & SEC_RELOC) == 0
6204 || section->reloc_count == 0
6205 || (section->flags & SEC_CODE) == 0)
6206 continue;
6207
6208 /* If this section is a link-once section that will be
6209 discarded, then don't create any stubs. */
6210 if (section->output_section == NULL
6211 || section->output_section->owner != output_bfd)
6212 continue;
6213
6214 /* Get the relocs. */
6215 internal_relocs
6216 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6217 NULL, info->keep_memory);
6218 if (internal_relocs == NULL)
6219 goto error_ret_free_local;
6220
6221 /* Now examine each relocation. */
6222 irela = internal_relocs;
6223 irelaend = irela + section->reloc_count;
6224 for (; irela < irelaend; irela++)
6225 {
6226 unsigned int r_type, r_indx;
906e58ca
NC		 6227 asection *sym_sec;
6228 bfd_vma sym_value;
6229 bfd_vma destination;
6230 struct elf32_arm_link_hash_entry *hash;
7413f23f 6231 const char *sym_name;
34e77a92 6232 unsigned char st_type;
35fc36a8 6233 enum arm_st_branch_type branch_type;
48229727 6234 bfd_boolean created_stub = FALSE;
906e58ca
NC		 6235
6236 r_type = ELF32_R_TYPE (irela->r_info);
6237 r_indx = ELF32_R_SYM (irela->r_info);
6238
6239 if (r_type >= (unsigned int) R_ARM_max)
6240 {
6241 bfd_set_error (bfd_error_bad_value);
6242 error_ret_free_internal:
6243 if (elf_section_data (section)->relocs == NULL)
6244 free (internal_relocs);
15dd01b1
TP		 6245 /* Fall through. */
6246 error_ret_free_local:
6247 if (local_syms != NULL
6248 && (symtab_hdr->contents
6249 != (unsigned char *) local_syms))
6250 free (local_syms);
6251 return FALSE;
906e58ca 6252 }
b38cadfb 6253
0855e32b
NS		 6254 hash = NULL;
6255 if (r_indx >= symtab_hdr->sh_info)
6256 hash = elf32_arm_hash_entry
6257 (elf_sym_hashes (input_bfd)
6258 [r_indx - symtab_hdr->sh_info]);
b38cadfb 6259
0855e32b
NS		 6260 /* Only look for stubs on branch instructions, or
6261 non-relaxed TLSCALL */
906e58ca 6262 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 6263 && (r_type != (unsigned int) R_ARM_THM_CALL)
6264 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 6265 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6266 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 6267 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 6268 && (r_type != (unsigned int) R_ARM_PLT32)
6269 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6270 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6271 && r_type == elf32_arm_tls_transition
6272 (info, r_type, &hash->root)
6273 && ((hash ? hash->tls_type
6274 : (elf32_arm_local_got_tls_type
6275 (input_bfd)[r_indx]))
6276 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 6277 continue;
6278
6279 /* Now determine the call target, its name, value,
6280 section. */
6281 sym_sec = NULL;
6282 sym_value = 0;
6283 destination = 0;
7413f23f 6284 sym_name = NULL;
b38cadfb 6285
0855e32b
NS		 6286 if (r_type == (unsigned int) R_ARM_TLS_CALL
6287 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6288 {
6289 /* A non-relaxed TLS call. The target is the
6290 plt-resident trampoline and nothing to do
6291 with the symbol. */
6292 BFD_ASSERT (htab->tls_trampoline > 0);
6293 sym_sec = htab->root.splt;
6294 sym_value = htab->tls_trampoline;
6295 hash = 0;
34e77a92 6296 st_type = STT_FUNC;
35fc36a8 6297 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 6298 }
6299 else if (!hash)
906e58ca
NC		 6300 {
6301 /* It's a local symbol. */
6302 Elf_Internal_Sym *sym;
906e58ca
NC		 6303
6304 if (local_syms == NULL)
6305 {
6306 local_syms
6307 = (Elf_Internal_Sym *) symtab_hdr->contents;
6308 if (local_syms == NULL)
6309 local_syms
6310 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6311 symtab_hdr->sh_info, 0,
6312 NULL, NULL, NULL);
6313 if (local_syms == NULL)
6314 goto error_ret_free_internal;
6315 }
6316
6317 sym = local_syms + r_indx;
f6d250ce
TS		 6318 if (sym->st_shndx == SHN_UNDEF)
6319 sym_sec = bfd_und_section_ptr;
6320 else if (sym->st_shndx == SHN_ABS)
6321 sym_sec = bfd_abs_section_ptr;
6322 else if (sym->st_shndx == SHN_COMMON)
6323 sym_sec = bfd_com_section_ptr;
6324 else
6325 sym_sec =
6326 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6327
ffcb4889
NS		 6328 if (!sym_sec)
6329 /* This is an undefined symbol. It can never
6a631e86 6330 be resolved. */
ffcb4889 6331 continue;
fe33d2fa 6332
906e58ca
NC		 6333 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6334 sym_value = sym->st_value;
6335 destination = (sym_value + irela->r_addend
6336 + sym_sec->output_offset
6337 + sym_sec->output_section->vma);
34e77a92 6338 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 6339 branch_type =
6340 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 6341 sym_name
6342 = bfd_elf_string_from_elf_section (input_bfd,
6343 symtab_hdr->sh_link,
6344 sym->st_name);
906e58ca
NC		 6345 }
6346 else
6347 {
6348 /* It's an external symbol. */
906e58ca
NC		 6349 while (hash->root.root.type == bfd_link_hash_indirect
6350 || hash->root.root.type == bfd_link_hash_warning)
6351 hash = ((struct elf32_arm_link_hash_entry *)
6352 hash->root.root.u.i.link);
6353
6354 if (hash->root.root.type == bfd_link_hash_defined
6355 || hash->root.root.type == bfd_link_hash_defweak)
6356 {
6357 sym_sec = hash->root.root.u.def.section;
6358 sym_value = hash->root.root.u.def.value;
022f8312
CL		 6359
6360 struct elf32_arm_link_hash_table *globals =
6361 elf32_arm_hash_table (info);
6362
6363 /* For a destination in a shared library,
6364 use the PLT stub as target address to
6365 decide whether a branch stub is
6366 needed. */
4dfe6ac6 6367 if (globals != NULL
362d30a1 6368 && globals->root.splt != NULL
4dfe6ac6 6369 && hash != NULL
022f8312
CL		 6370 && hash->root.plt.offset != (bfd_vma) -1)
6371 {
362d30a1 6372 sym_sec = globals->root.splt;
022f8312
CL		 6373 sym_value = hash->root.plt.offset;
6374 if (sym_sec->output_section != NULL)
6375 destination = (sym_value
6376 + sym_sec->output_offset
6377 + sym_sec->output_section->vma);
6378 }
6379 else if (sym_sec->output_section != NULL)
906e58ca
NC		 6380 destination = (sym_value + irela->r_addend
6381 + sym_sec->output_offset
6382 + sym_sec->output_section->vma);
6383 }
69c5861e
CL		 6384 else if ((hash->root.root.type == bfd_link_hash_undefined)
6385 || (hash->root.root.type == bfd_link_hash_undefweak))
6386 {
6387 /* For a shared library, use the PLT stub as
6388 target address to decide whether a long
6389 branch stub is needed.
6390 For absolute code, they cannot be handled. */
6391 struct elf32_arm_link_hash_table *globals =
6392 elf32_arm_hash_table (info);
6393
4dfe6ac6 6394 if (globals != NULL
362d30a1 6395 && globals->root.splt != NULL
4dfe6ac6 6396 && hash != NULL
69c5861e
CL		 6397 && hash->root.plt.offset != (bfd_vma) -1)
6398 {
362d30a1 6399 sym_sec = globals->root.splt;
69c5861e
CL		 6400 sym_value = hash->root.plt.offset;
6401 if (sym_sec->output_section != NULL)
6402 destination = (sym_value
6403 + sym_sec->output_offset
6404 + sym_sec->output_section->vma);
6405 }
6406 else
6407 continue;
6408 }
906e58ca
NC		 6409 else
6410 {
6411 bfd_set_error (bfd_error_bad_value);
6412 goto error_ret_free_internal;
6413 }
34e77a92 6414 st_type = hash->root.type;
39d911fc
TP		 6415 branch_type =
6416 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 6417 sym_name = hash->root.root.root.string;
906e58ca
NC		 6418 }
6419
48229727 6420 do
7413f23f 6421 {
b715f643 6422 bfd_boolean new_stub;
0955507f 6423 struct elf32_arm_stub_hash_entry *stub_entry;
b715f643 6424
48229727
JB		 6425 /* Determine what (if any) linker stub is needed. */
6426 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 6427 st_type, &branch_type,
6428 hash, destination, sym_sec,
48229727
JB		 6429 input_bfd, sym_name);
6430 if (stub_type == arm_stub_none)
6431 break;
6432
48229727
JB		 6433 /* We've either created a stub for this reloc already,
6434 or we are about to. */
0955507f 6435 stub_entry =
b715f643
TP		 6436 elf32_arm_create_stub (htab, stub_type, section, irela,
6437 sym_sec, hash,
6438 (char *) sym_name, sym_value,
6439 branch_type, &new_stub);
7413f23f 6440
0955507f 6441 created_stub = stub_entry != NULL;
b715f643
TP		 6442 if (!created_stub)
6443 goto error_ret_free_internal;
6444 else if (!new_stub)
6445 break;
99059e56 6446 else
b715f643 6447 stub_changed = TRUE;
99059e56
RM		 6448 }
6449 while (0);
6450
6451 /* Look for relocations which might trigger Cortex-A8
6452 erratum. */
6453 if (htab->fix_cortex_a8
6454 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6455 || r_type == (unsigned int) R_ARM_THM_JUMP19
6456 || r_type == (unsigned int) R_ARM_THM_CALL
6457 || r_type == (unsigned int) R_ARM_THM_XPC22))
6458 {
6459 bfd_vma from = section->output_section->vma
6460 + section->output_offset
6461 + irela->r_offset;
6462
6463 if ((from & 0xfff) == 0xffe)
6464 {
6465 /* Found a candidate. Note we haven't checked the
6466 destination is within 4K here: if we do so (and
6467 don't create an entry in a8_relocs) we can't tell
6468 that a branch should have been relocated when
6469 scanning later. */
6470 if (num_a8_relocs == a8_reloc_table_size)
6471 {
6472 a8_reloc_table_size *= 2;
6473 a8_relocs = (struct a8_erratum_reloc *)
6474 bfd_realloc (a8_relocs,
6475 sizeof (struct a8_erratum_reloc)
6476 * a8_reloc_table_size);
6477 }
6478
6479 a8_relocs[num_a8_relocs].from = from;
6480 a8_relocs[num_a8_relocs].destination = destination;
6481 a8_relocs[num_a8_relocs].r_type = r_type;
6482 a8_relocs[num_a8_relocs].branch_type = branch_type;
6483 a8_relocs[num_a8_relocs].sym_name = sym_name;
6484 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6485 a8_relocs[num_a8_relocs].hash = hash;
6486
6487 num_a8_relocs++;
6488 }
6489 }
906e58ca
NC		 6490 }
6491
99059e56
RM		 6492 /* We're done with the internal relocs, free them. */
6493 if (elf_section_data (section)->relocs == NULL)
6494 free (internal_relocs);
6495 }
48229727 6496
99059e56 6497 if (htab->fix_cortex_a8)
48229727 6498 {
99059e56
RM		 6499 /* Sort relocs which might apply to Cortex-A8 erratum. */
6500 qsort (a8_relocs, num_a8_relocs,
eb7c4339 6501 sizeof (struct a8_erratum_reloc),
99059e56 6502 &a8_reloc_compare);
48229727 6503
99059e56
RM		 6504 /* Scan for branches which might trigger Cortex-A8 erratum. */
6505 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 6506 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 6507 a8_relocs, num_a8_relocs,
6508 prev_num_a8_fixes, &stub_changed)
6509 != 0)
48229727 6510 goto error_ret_free_local;
5e681ec4 6511 }
7f991970
AM		 6512
6513 if (local_syms != NULL
6514 && symtab_hdr->contents != (unsigned char *) local_syms)
6515 {
6516 if (!info->keep_memory)
6517 free (local_syms);
6518 else
6519 symtab_hdr->contents = (unsigned char *) local_syms;
6520 }
5e681ec4
PB		 6521 }
6522
0955507f
TP		 6523 if (first_veneer_scan
6524 && !set_cmse_veneer_addr_from_implib (info, htab,
6525 &cmse_stub_created))
6526 ret = FALSE;
6527
eb7c4339 6528 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 6529 stub_changed = TRUE;
48229727 6530
906e58ca
NC		 6531 if (!stub_changed)
6532 break;
5e681ec4 6533
906e58ca
NC		 6534 /* OK, we've added some stubs. Find out the new size of the
6535 stub sections. */
6536 for (stub_sec = htab->stub_bfd->sections;
6537 stub_sec != NULL;
6538 stub_sec = stub_sec->next)
3e6b1042
DJ		 6539 {
6540 /* Ignore non-stub sections. */
6541 if (!strstr (stub_sec->name, STUB_SUFFIX))
6542 continue;
6543
6544 stub_sec->size = 0;
6545 }
b34b2d70 6546
0955507f
TP		 6547 /* Add new SG veneers after those already in the input import
6548 library. */
6549 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6550 stub_type++)
6551 {
6552 bfd_vma *start_offset_p;
6553 asection **stub_sec_p;
6554
6555 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6556 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6557 if (start_offset_p == NULL)
6558 continue;
6559
6560 BFD_ASSERT (stub_sec_p != NULL);
6561 if (*stub_sec_p != NULL)
6562 (*stub_sec_p)->size = *start_offset_p;
6563 }
6564
d7c5bd02 6565 /* Compute stub section size, considering padding. */
906e58ca 6566 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 6567 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6568 stub_type++)
6569 {
6570 int size, padding;
6571 asection **stub_sec_p;
6572
6573 padding = arm_dedicated_stub_section_padding (stub_type);
6574 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6575 /* Skip if no stub input section or no stub section padding
6576 required. */
6577 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6578 continue;
6579 /* Stub section padding required but no dedicated section. */
6580 BFD_ASSERT (stub_sec_p);
6581
6582 size = (*stub_sec_p)->size;
6583 size = (size + padding - 1) & ~(padding - 1);
6584 (*stub_sec_p)->size = size;
6585 }
906e58ca 6586
48229727
JB		 6587 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6588 if (htab->fix_cortex_a8)
99059e56
RM		 6589 for (i = 0; i < num_a8_fixes; i++)
6590 {
48229727 6591 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 6592 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 6593
6594 if (stub_sec == NULL)
7f991970 6595 return FALSE;
48229727 6596
99059e56
RM		 6597 stub_sec->size
6598 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6599 NULL);
6600 }
48229727
JB		 6601
6602
906e58ca
NC		 6603 /* Ask the linker to do its stuff. */
6604 (*htab->layout_sections_again) ();
4ba2ef8f 6605 first_veneer_scan = FALSE;
ba93b8ac
DJ		 6606 }
6607
48229727
JB		 6608 /* Add stubs for Cortex-A8 erratum fixes now. */
6609 if (htab->fix_cortex_a8)
6610 {
6611 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 6612 {
6613 struct elf32_arm_stub_hash_entry *stub_entry;
6614 char *stub_name = a8_fixes[i].stub_name;
6615 asection *section = a8_fixes[i].section;
6616 unsigned int section_id = a8_fixes[i].section->id;
6617 asection *link_sec = htab->stub_group[section_id].link_sec;
6618 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6619 const insn_sequence *template_sequence;
6620 int template_size, size = 0;
6621
6622 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6623 TRUE, FALSE);
6624 if (stub_entry == NULL)
6625 {
871b3ab2 6626 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4eca0228 6627 section->owner, stub_name);
99059e56
RM		 6628 return FALSE;
6629 }
6630
6631 stub_entry->stub_sec = stub_sec;
0955507f 6632 stub_entry->stub_offset = (bfd_vma) -1;
99059e56
RM		 6633 stub_entry->id_sec = link_sec;
6634 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 6635 stub_entry->source_value = a8_fixes[i].offset;
99059e56 6636 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 6637 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 6638 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 6639 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 6640
99059e56
RM		 6641 size = find_stub_size_and_template (a8_fixes[i].stub_type,
6642 &template_sequence,
6643 &template_size);
48229727 6644
99059e56
RM		 6645 stub_entry->stub_size = size;
6646 stub_entry->stub_template = template_sequence;
6647 stub_entry->stub_template_size = template_size;
6648 }
48229727
JB		 6649
6650 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 6651 elf32_arm_write_section(). */
48229727
JB		 6652 htab->a8_erratum_fixes = a8_fixes;
6653 htab->num_a8_erratum_fixes = num_a8_fixes;
6654 }
6655 else
6656 {
6657 htab->a8_erratum_fixes = NULL;
6658 htab->num_a8_erratum_fixes = 0;
6659 }
0955507f 6660 return ret;
5e681ec4
PB		 6661}
6662
906e58ca
NC		 6663/* Build all the stubs associated with the current output file. The
6664 stubs are kept in a hash table attached to the main linker hash
6665 table. We also set up the .plt entries for statically linked PIC
6666 functions here. This function is called via arm_elf_finish in the
6667 linker. */
252b5132 6668
906e58ca
NC		 6669bfd_boolean
6670elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 6671{
906e58ca
NC		 6672 asection *stub_sec;
6673 struct bfd_hash_table *table;
0955507f 6674 enum elf32_arm_stub_type stub_type;
906e58ca 6675 struct elf32_arm_link_hash_table *htab;
252b5132 6676
906e58ca 6677 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 6678 if (htab == NULL)
6679 return FALSE;
252b5132 6680
906e58ca
NC		 6681 for (stub_sec = htab->stub_bfd->sections;
6682 stub_sec != NULL;
6683 stub_sec = stub_sec->next)
252b5132 6684 {
906e58ca
NC		 6685 bfd_size_type size;
6686
8029a119 6687 /* Ignore non-stub sections. */
906e58ca
NC		 6688 if (!strstr (stub_sec->name, STUB_SUFFIX))
6689 continue;
6690
d7c5bd02 6691 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
0955507f
TP		 6692 must at least be done for stub section requiring padding and for SG
6693 veneers to ensure that a non secure code branching to a removed SG
6694 veneer causes an error. */
906e58ca 6695 size = stub_sec->size;
21d799b5 6696 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 6697 if (stub_sec->contents == NULL && size != 0)
6698 return FALSE;
0955507f 6699
906e58ca 6700 stub_sec->size = 0;
252b5132
RH		 6701 }
6702
0955507f
TP		 6703 /* Add new SG veneers after those already in the input import library. */
6704 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
6705 {
6706 bfd_vma *start_offset_p;
6707 asection **stub_sec_p;
6708
6709 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6710 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6711 if (start_offset_p == NULL)
6712 continue;
6713
6714 BFD_ASSERT (stub_sec_p != NULL);
6715 if (*stub_sec_p != NULL)
6716 (*stub_sec_p)->size = *start_offset_p;
6717 }
6718
906e58ca
NC		 6719 /* Build the stubs as directed by the stub hash table. */
6720 table = &htab->stub_hash_table;
6721 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 6722 if (htab->fix_cortex_a8)
6723 {
6724 /* Place the cortex a8 stubs last. */
6725 htab->fix_cortex_a8 = -1;
6726 bfd_hash_traverse (table, arm_build_one_stub, info);
6727 }
252b5132 6728
906e58ca 6729 return TRUE;
252b5132
RH		 6730}
6731
9b485d32
NC		 6732/* Locate the Thumb encoded calling stub for NAME. */
6733
252b5132 6734static struct elf_link_hash_entry *
57e8b36a
NC		 6735find_thumb_glue (struct bfd_link_info *link_info,
6736 const char *name,
f2a9dd69 6737 char **error_message)
252b5132
RH		 6738{
6739 char *tmp_name;
6740 struct elf_link_hash_entry *hash;
6741 struct elf32_arm_link_hash_table *hash_table;
6742
6743 /* We need a pointer to the armelf specific hash table. */
6744 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6745 if (hash_table == NULL)
6746 return NULL;
252b5132 6747
21d799b5 6748 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6749 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6750
6751 BFD_ASSERT (tmp_name);
6752
6753 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
6754
6755 hash = elf_link_hash_lookup
b34976b6 6756 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6757
b1657152 6758 if (hash == NULL
90b6238f
AM		 6759 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
6760 "Thumb", tmp_name, name) == -1)
b1657152 6761 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6762
6763 free (tmp_name);
6764
6765 return hash;
6766}
6767
9b485d32
NC		 6768/* Locate the ARM encoded calling stub for NAME. */
6769
252b5132 6770static struct elf_link_hash_entry *
57e8b36a
NC		 6771find_arm_glue (struct bfd_link_info *link_info,
6772 const char *name,
f2a9dd69 6773 char **error_message)
252b5132
RH		 6774{
6775 char *tmp_name;
6776 struct elf_link_hash_entry *myh;
6777 struct elf32_arm_link_hash_table *hash_table;
6778
6779 /* We need a pointer to the elfarm specific hash table. */
6780 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 6781 if (hash_table == NULL)
6782 return NULL;
252b5132 6783
21d799b5 6784 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6785 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6786
6787 BFD_ASSERT (tmp_name);
6788
6789 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6790
6791 myh = elf_link_hash_lookup
b34976b6 6792 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6793
b1657152 6794 if (myh == NULL
90b6238f
AM		 6795 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
6796 "ARM", tmp_name, name) == -1)
b1657152 6797 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6798
6799 free (tmp_name);
6800
6801 return myh;
6802}
6803
8f6277f5 6804/* ARM->Thumb glue (static images):
252b5132
RH		 6805
6806 .arm
6807 __func_from_arm:
6808 ldr r12, __func_addr
6809 bx r12
6810 __func_addr:
906e58ca 6811 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 6812
26079076
PB		 6813 (v5t static images)
6814 .arm
6815 __func_from_arm:
6816 ldr pc, __func_addr
6817 __func_addr:
906e58ca 6818 .word func @ behave as if you saw a ARM_32 reloc.
26079076 6819
8f6277f5
PB		 6820 (relocatable images)
6821 .arm
6822 __func_from_arm:
6823 ldr r12, __func_offset
6824 add r12, r12, pc
6825 bx r12
6826 __func_offset:
8029a119 6827 .word func - . */
8f6277f5
PB		 6828
6829#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 6830static const insn32 a2t1_ldr_insn = 0xe59fc000;
6831static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
6832static const insn32 a2t3_func_addr_insn = 0x00000001;
6833
26079076
PB		 6834#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
6835static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
6836static const insn32 a2t2v5_func_addr_insn = 0x00000001;
6837
8f6277f5
PB		 6838#define ARM2THUMB_PIC_GLUE_SIZE 16
6839static const insn32 a2t1p_ldr_insn = 0xe59fc004;
6840static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
6841static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
6842
07d6d2b8 6843/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 6844
07d6d2b8
AM		 6845 .thumb .thumb
6846 .align 2 .align 2
6847 __func_from_thumb: __func_from_thumb:
6848 bx pc push {r6, lr}
6849 nop ldr r6, __func_addr
6850 .arm mov lr, pc
6851 b func bx r6
99059e56
RM		 6852 .arm
6853 ;; back_to_thumb
6854 ldmia r13! {r6, lr}
6855 bx lr
6856 __func_addr:
07d6d2b8 6857 .word func */
252b5132
RH		 6858
6859#define THUMB2ARM_GLUE_SIZE 8
6860static const insn16 t2a1_bx_pc_insn = 0x4778;
6861static const insn16 t2a2_noop_insn = 0x46c0;
6862static const insn32 t2a3_b_insn = 0xea000000;
6863
c7b8f16e 6864#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 6865#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
6866#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 6867
845b51d6
PB		 6868#define ARM_BX_VENEER_SIZE 12
6869static const insn32 armbx1_tst_insn = 0xe3100001;
6870static const insn32 armbx2_moveq_insn = 0x01a0f000;
6871static const insn32 armbx3_bx_insn = 0xe12fff10;
6872
7e392df6 6873#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 6874static void
6875arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 6876{
6877 asection * s;
8029a119 6878 bfd_byte * contents;
252b5132 6879
8029a119 6880 if (size == 0)
3e6b1042
DJ		 6881 {
6882 /* Do not include empty glue sections in the output. */
6883 if (abfd != NULL)
6884 {
3d4d4302 6885 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 6886 if (s != NULL)
6887 s->flags |= SEC_EXCLUDE;
6888 }
6889 return;
6890 }
252b5132 6891
8029a119 6892 BFD_ASSERT (abfd != NULL);
252b5132 6893
3d4d4302 6894 s = bfd_get_linker_section (abfd, name);
8029a119 6895 BFD_ASSERT (s != NULL);
252b5132 6896
21d799b5 6897 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 6898
8029a119
NC		 6899 BFD_ASSERT (s->size == size);
6900 s->contents = contents;
6901}
906e58ca 6902
8029a119
NC		 6903bfd_boolean
6904bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
6905{
6906 struct elf32_arm_link_hash_table * globals;
906e58ca 6907
8029a119
NC		 6908 globals = elf32_arm_hash_table (info);
6909 BFD_ASSERT (globals != NULL);
906e58ca 6910
8029a119
NC		 6911 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6912 globals->arm_glue_size,
6913 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 6914
8029a119
NC		 6915 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6916 globals->thumb_glue_size,
6917 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 6918
8029a119
NC		 6919 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6920 globals->vfp11_erratum_glue_size,
6921 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 6922
a504d23a
LA		 6923 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6924 globals->stm32l4xx_erratum_glue_size,
6925 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6926
8029a119
NC		 6927 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6928 globals->bx_glue_size,
845b51d6
PB		 6929 ARM_BX_GLUE_SECTION_NAME);
6930
b34976b6 6931 return TRUE;
252b5132
RH		 6932}
6933
a4fd1a8e 6934/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 6935 returns the symbol identifying the stub. */
6936
a4fd1a8e 6937static struct elf_link_hash_entry *
57e8b36a
NC		 6938record_arm_to_thumb_glue (struct bfd_link_info * link_info,
6939 struct elf_link_hash_entry * h)
252b5132
RH		 6940{
6941 const char * name = h->root.root.string;
63b0f745 6942 asection * s;
252b5132
RH		 6943 char * tmp_name;
6944 struct elf_link_hash_entry * myh;
14a793b2 6945 struct bfd_link_hash_entry * bh;
252b5132 6946 struct elf32_arm_link_hash_table * globals;
dc810e39 6947 bfd_vma val;
2f475487 6948 bfd_size_type size;
252b5132
RH		 6949
6950 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 6951 BFD_ASSERT (globals != NULL);
6952 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6953
3d4d4302 6954 s = bfd_get_linker_section
252b5132
RH		 6955 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
6956
252b5132
RH		 6957 BFD_ASSERT (s != NULL);
6958
21d799b5 6959 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6960 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6961
6962 BFD_ASSERT (tmp_name);
6963
6964 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6965
6966 myh = elf_link_hash_lookup
b34976b6 6967 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 6968
6969 if (myh != NULL)
6970 {
9b485d32 6971 /* We've already seen this guy. */
252b5132 6972 free (tmp_name);
a4fd1a8e 6973 return myh;
252b5132
RH		 6974 }
6975
57e8b36a
NC		 6976 /* The only trick here is using hash_table->arm_glue_size as the value.
6977 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 6978 putting it. The +1 on the value marks that the stub has not been
6979 output yet - not that it is a Thumb function. */
14a793b2 6980 bh = NULL;
dc810e39
AM		 6981 val = globals->arm_glue_size + 1;
6982 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
6983 tmp_name, BSF_GLOBAL, s, val,
b34976b6 6984 NULL, TRUE, FALSE, &bh);
252b5132 6985
b7693d02
DJ		 6986 myh = (struct elf_link_hash_entry *) bh;
6987 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6988 myh->forced_local = 1;
6989
252b5132
RH		 6990 free (tmp_name);
6991
0e1862bb
L		 6992 if (bfd_link_pic (link_info)
6993 || globals->root.is_relocatable_executable
27e55c4d 6994 || globals->pic_veneer)
2f475487 6995 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 6996 else if (globals->use_blx)
6997 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 6998 else
2f475487
AM		 6999 size = ARM2THUMB_STATIC_GLUE_SIZE;
7000
7001 s->size += size;
7002 globals->arm_glue_size += size;
252b5132 7003
a4fd1a8e 7004 return myh;
252b5132
RH		 7005}
7006
845b51d6
PB		 7007/* Allocate space for ARMv4 BX veneers. */
7008
7009static void
7010record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7011{
7012 asection * s;
7013 struct elf32_arm_link_hash_table *globals;
7014 char *tmp_name;
7015 struct elf_link_hash_entry *myh;
7016 struct bfd_link_hash_entry *bh;
7017 bfd_vma val;
7018
7019 /* BX PC does not need a veneer. */
7020 if (reg == 15)
7021 return;
7022
7023 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 7024 BFD_ASSERT (globals != NULL);
7025 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7026
7027 /* Check if this veneer has already been allocated. */
7028 if (globals->bx_glue_offset[reg])
7029 return;
7030
3d4d4302 7031 s = bfd_get_linker_section
845b51d6
PB		 7032 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7033
7034 BFD_ASSERT (s != NULL);
7035
7036 /* Add symbol for veneer. */
21d799b5
NC		 7037 tmp_name = (char *)
7038 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 7039
845b51d6 7040 BFD_ASSERT (tmp_name);
906e58ca 7041
845b51d6 7042 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 7043
845b51d6
PB		 7044 myh = elf_link_hash_lookup
7045 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7046
845b51d6 7047 BFD_ASSERT (myh == NULL);
906e58ca 7048
845b51d6
PB		 7049 bh = NULL;
7050 val = globals->bx_glue_size;
7051 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 7052 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7053 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 7054
7055 myh = (struct elf_link_hash_entry *) bh;
7056 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7057 myh->forced_local = 1;
7058
7059 s->size += ARM_BX_VENEER_SIZE;
7060 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7061 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7062}
7063
7064
c7b8f16e
JB		 7065/* Add an entry to the code/data map for section SEC. */
7066
7067static void
7068elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7069{
7070 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7071 unsigned int newidx;
906e58ca 7072
c7b8f16e
JB		 7073 if (sec_data->map == NULL)
7074 {
21d799b5 7075 sec_data->map = (elf32_arm_section_map *)
99059e56 7076 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 7077 sec_data->mapcount = 0;
7078 sec_data->mapsize = 1;
7079 }
906e58ca 7080
c7b8f16e 7081 newidx = sec_data->mapcount++;
906e58ca 7082
c7b8f16e
JB		 7083 if (sec_data->mapcount > sec_data->mapsize)
7084 {
7085 sec_data->mapsize *= 2;
21d799b5 7086 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 7087 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7088 * sizeof (elf32_arm_section_map));
515ef31d
NC		 7089 }
7090
7091 if (sec_data->map)
7092 {
7093 sec_data->map[newidx].vma = vma;
7094 sec_data->map[newidx].type = type;
c7b8f16e 7095 }
c7b8f16e
JB		 7096}
7097
7098
7099/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7100 veneers are handled for now. */
7101
7102static bfd_vma
7103record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 7104 elf32_vfp11_erratum_list *branch,
7105 bfd *branch_bfd,
7106 asection *branch_sec,
7107 unsigned int offset)
c7b8f16e
JB		 7108{
7109 asection *s;
7110 struct elf32_arm_link_hash_table *hash_table;
7111 char *tmp_name;
7112 struct elf_link_hash_entry *myh;
7113 struct bfd_link_hash_entry *bh;
7114 bfd_vma val;
7115 struct _arm_elf_section_data *sec_data;
c7b8f16e 7116 elf32_vfp11_erratum_list *newerr;
906e58ca 7117
c7b8f16e 7118 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 7119 BFD_ASSERT (hash_table != NULL);
7120 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 7121
3d4d4302 7122 s = bfd_get_linker_section
c7b8f16e 7123 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 7124
c7b8f16e 7125 sec_data = elf32_arm_section_data (s);
906e58ca 7126
c7b8f16e 7127 BFD_ASSERT (s != NULL);
906e58ca 7128
21d799b5 7129 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7130 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 7131
c7b8f16e 7132 BFD_ASSERT (tmp_name);
906e58ca 7133
c7b8f16e
JB		 7134 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7135 hash_table->num_vfp11_fixes);
906e58ca 7136
c7b8f16e
JB		 7137 myh = elf_link_hash_lookup
7138 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7139
c7b8f16e 7140 BFD_ASSERT (myh == NULL);
906e58ca 7141
c7b8f16e
JB		 7142 bh = NULL;
7143 val = hash_table->vfp11_erratum_glue_size;
7144 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 7145 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7146 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 7147
7148 myh = (struct elf_link_hash_entry *) bh;
7149 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7150 myh->forced_local = 1;
7151
7152 /* Link veneer back to calling location. */
c7e2358a 7153 sec_data->erratumcount += 1;
21d799b5
NC		 7154 newerr = (elf32_vfp11_erratum_list *)
7155 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 7156
c7b8f16e
JB		 7157 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7158 newerr->vma = -1;
7159 newerr->u.v.branch = branch;
7160 newerr->u.v.id = hash_table->num_vfp11_fixes;
7161 branch->u.b.veneer = newerr;
7162
7163 newerr->next = sec_data->erratumlist;
7164 sec_data->erratumlist = newerr;
7165
7166 /* A symbol for the return from the veneer. */
7167 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7168 hash_table->num_vfp11_fixes);
7169
7170 myh = elf_link_hash_lookup
7171 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 7172
c7b8f16e
JB		 7173 if (myh != NULL)
7174 abort ();
7175
7176 bh = NULL;
7177 val = offset + 4;
7178 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7179 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 7180
c7b8f16e
JB		 7181 myh = (struct elf_link_hash_entry *) bh;
7182 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7183 myh->forced_local = 1;
7184
7185 free (tmp_name);
906e58ca 7186
c7b8f16e
JB		 7187 /* Generate a mapping symbol for the veneer section, and explicitly add an
7188 entry for that symbol to the code/data map for the section. */
7189 if (hash_table->vfp11_erratum_glue_size == 0)
7190 {
7191 bh = NULL;
7192 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 7193 ever requires this erratum fix. */
c7b8f16e
JB		 7194 _bfd_generic_link_add_one_symbol (link_info,
7195 hash_table->bfd_of_glue_owner, "$a",
7196 BSF_LOCAL, s, 0, NULL,
99059e56 7197 TRUE, FALSE, &bh);
c7b8f16e
JB		 7198
7199 myh = (struct elf_link_hash_entry *) bh;
7200 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7201 myh->forced_local = 1;
906e58ca 7202
c7b8f16e 7203 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 7204 BFDs. We must make a note of this generated mapping symbol
7205 ourselves so that code byteswapping works properly in
7206 elf32_arm_write_section. */
c7b8f16e
JB		 7207 elf32_arm_section_map_add (s, 'a', 0);
7208 }
906e58ca 7209
c7b8f16e
JB		 7210 s->size += VFP11_ERRATUM_VENEER_SIZE;
7211 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7212 hash_table->num_vfp11_fixes++;
906e58ca 7213
c7b8f16e
JB		 7214 /* The offset of the veneer. */
7215 return val;
7216}
7217
a504d23a
LA		 7218/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7219 veneers need to be handled because used only in Cortex-M. */
7220
7221static bfd_vma
7222record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7223 elf32_stm32l4xx_erratum_list *branch,
7224 bfd *branch_bfd,
7225 asection *branch_sec,
7226 unsigned int offset,
7227 bfd_size_type veneer_size)
7228{
7229 asection *s;
7230 struct elf32_arm_link_hash_table *hash_table;
7231 char *tmp_name;
7232 struct elf_link_hash_entry *myh;
7233 struct bfd_link_hash_entry *bh;
7234 bfd_vma val;
7235 struct _arm_elf_section_data *sec_data;
7236 elf32_stm32l4xx_erratum_list *newerr;
7237
7238 hash_table = elf32_arm_hash_table (link_info);
7239 BFD_ASSERT (hash_table != NULL);
7240 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7241
7242 s = bfd_get_linker_section
7243 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7244
7245 BFD_ASSERT (s != NULL);
7246
7247 sec_data = elf32_arm_section_data (s);
7248
7249 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7250 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7251
7252 BFD_ASSERT (tmp_name);
7253
7254 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7255 hash_table->num_stm32l4xx_fixes);
7256
7257 myh = elf_link_hash_lookup
7258 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7259
7260 BFD_ASSERT (myh == NULL);
7261
7262 bh = NULL;
7263 val = hash_table->stm32l4xx_erratum_glue_size;
7264 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7265 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7266 NULL, TRUE, FALSE, &bh);
7267
7268 myh = (struct elf_link_hash_entry *) bh;
7269 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7270 myh->forced_local = 1;
7271
7272 /* Link veneer back to calling location. */
7273 sec_data->stm32l4xx_erratumcount += 1;
7274 newerr = (elf32_stm32l4xx_erratum_list *)
7275 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7276
7277 newerr->type = STM32L4XX_ERRATUM_VENEER;
7278 newerr->vma = -1;
7279 newerr->u.v.branch = branch;
7280 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7281 branch->u.b.veneer = newerr;
7282
7283 newerr->next = sec_data->stm32l4xx_erratumlist;
7284 sec_data->stm32l4xx_erratumlist = newerr;
7285
7286 /* A symbol for the return from the veneer. */
7287 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7288 hash_table->num_stm32l4xx_fixes);
7289
7290 myh = elf_link_hash_lookup
7291 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
7292
7293 if (myh != NULL)
7294 abort ();
7295
7296 bh = NULL;
7297 val = offset + 4;
7298 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7299 branch_sec, val, NULL, TRUE, FALSE, &bh);
7300
7301 myh = (struct elf_link_hash_entry *) bh;
7302 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7303 myh->forced_local = 1;
7304
7305 free (tmp_name);
7306
7307 /* Generate a mapping symbol for the veneer section, and explicitly add an
7308 entry for that symbol to the code/data map for the section. */
7309 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7310 {
7311 bh = NULL;
7312 /* Creates a THUMB symbol since there is no other choice. */
7313 _bfd_generic_link_add_one_symbol (link_info,
7314 hash_table->bfd_of_glue_owner, "$t",
7315 BSF_LOCAL, s, 0, NULL,
7316 TRUE, FALSE, &bh);
7317
7318 myh = (struct elf_link_hash_entry *) bh;
7319 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7320 myh->forced_local = 1;
7321
7322 /* The elf32_arm_init_maps function only cares about symbols from input
7323 BFDs. We must make a note of this generated mapping symbol
7324 ourselves so that code byteswapping works properly in
7325 elf32_arm_write_section. */
7326 elf32_arm_section_map_add (s, 't', 0);
7327 }
7328
7329 s->size += veneer_size;
7330 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7331 hash_table->num_stm32l4xx_fixes++;
7332
7333 /* The offset of the veneer. */
7334 return val;
7335}
7336
8029a119 7337#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 7338 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7339 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 7340
7341/* Create a fake section for use by the ARM backend of the linker. */
7342
7343static bfd_boolean
7344arm_make_glue_section (bfd * abfd, const char * name)
7345{
7346 asection * sec;
7347
3d4d4302 7348 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 7349 if (sec != NULL)
7350 /* Already made. */
7351 return TRUE;
7352
3d4d4302 7353 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 7354
7355 if (sec == NULL
7356 || !bfd_set_section_alignment (abfd, sec, 2))
7357 return FALSE;
7358
7359 /* Set the gc mark to prevent the section from being removed by garbage
7360 collection, despite the fact that no relocs refer to this section. */
7361 sec->gc_mark = 1;
7362
7363 return TRUE;
7364}
7365
1db37fe6
YG		 7366/* Set size of .plt entries. This function is called from the
7367 linker scripts in ld/emultempl/{armelf}.em. */
7368
7369void
7370bfd_elf32_arm_use_long_plt (void)
7371{
7372 elf32_arm_use_long_plt_entry = TRUE;
7373}
7374
8afb0e02
NC		 7375/* Add the glue sections to ABFD. This function is called from the
7376 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 7377
b34976b6 7378bfd_boolean
57e8b36a
NC		 7379bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7380 struct bfd_link_info *info)
252b5132 7381{
a504d23a
LA		 7382 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7383 bfd_boolean dostm32l4xx = globals
7384 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7385 bfd_boolean addglue;
7386
8afb0e02
NC		 7387 /* If we are only performing a partial
7388 link do not bother adding the glue. */
0e1862bb 7389 if (bfd_link_relocatable (info))
b34976b6 7390 return TRUE;
252b5132 7391
a504d23a 7392 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 7393 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7394 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7395 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 7396
7397 if (!dostm32l4xx)
7398 return addglue;
7399
7400 return addglue
7401 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 7402}
7403
daa4adae
TP		 7404/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7405 ensures they are not marked for deletion by
7406 strip_excluded_output_sections () when veneers are going to be created
7407 later. Not doing so would trigger assert on empty section size in
7408 lang_size_sections_1 (). */
7409
7410void
7411bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7412{
7413 enum elf32_arm_stub_type stub_type;
7414
7415 /* If we are only performing a partial
7416 link do not bother adding the glue. */
7417 if (bfd_link_relocatable (info))
7418 return;
7419
7420 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7421 {
7422 asection *out_sec;
7423 const char *out_sec_name;
7424
7425 if (!arm_dedicated_stub_output_section_required (stub_type))
7426 continue;
7427
7428 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7429 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7430 if (out_sec != NULL)
7431 out_sec->flags |= SEC_KEEP;
7432 }
7433}
7434
8afb0e02
NC		 7435/* Select a BFD to be used to hold the sections used by the glue code.
7436 This function is called from the linker scripts in ld/emultempl/
8029a119 7437 {armelf/pe}.em. */
8afb0e02 7438
b34976b6 7439bfd_boolean
57e8b36a 7440bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 7441{
7442 struct elf32_arm_link_hash_table *globals;
7443
7444 /* If we are only performing a partial link
7445 do not bother getting a bfd to hold the glue. */
0e1862bb 7446 if (bfd_link_relocatable (info))
b34976b6 7447 return TRUE;
8afb0e02 7448
b7693d02
DJ		 7449 /* Make sure we don't attach the glue sections to a dynamic object. */
7450 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7451
8afb0e02 7452 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 7453 BFD_ASSERT (globals != NULL);
7454
7455 if (globals->bfd_of_glue_owner != NULL)
b34976b6 7456 return TRUE;
8afb0e02 7457
252b5132
RH		 7458 /* Save the bfd for later use. */
7459 globals->bfd_of_glue_owner = abfd;
cedb70c5 7460
b34976b6 7461 return TRUE;
252b5132
RH		 7462}
7463
906e58ca
NC		 7464static void
7465check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 7466{
2de70689
MGD		 7467 int cpu_arch;
7468
b38cadfb 7469 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 7470 Tag_CPU_arch);
7471
7472 if (globals->fix_arm1176)
7473 {
7474 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7475 globals->use_blx = 1;
7476 }
7477 else
7478 {
7479 if (cpu_arch > TAG_CPU_ARCH_V4T)
7480 globals->use_blx = 1;
7481 }
39b41c9c
PB		 7482}
7483
b34976b6 7484bfd_boolean
57e8b36a 7485bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 7486 struct bfd_link_info *link_info)
252b5132
RH		 7487{
7488 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 7489 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 7490 Elf_Internal_Rela *irel, *irelend;
7491 bfd_byte *contents = NULL;
252b5132
RH		 7492
7493 asection *sec;
7494 struct elf32_arm_link_hash_table *globals;
7495
7496 /* If we are only performing a partial link do not bother
7497 to construct any glue. */
0e1862bb 7498 if (bfd_link_relocatable (link_info))
b34976b6 7499 return TRUE;
252b5132 7500
39ce1a6a
NC		 7501 /* Here we have a bfd that is to be included on the link. We have a
7502 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 7503 globals = elf32_arm_hash_table (link_info);
252b5132 7504 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 7505
7506 check_use_blx (globals);
252b5132 7507
d504ffc8 7508 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 7509 {
90b6238f 7510 _bfd_error_handler (_("%pB: BE8 images only valid in big-endian mode"),
d003868e 7511 abfd);
e489d0ae
PB		 7512 return FALSE;
7513 }
f21f3fe0 7514
39ce1a6a
NC		 7515 /* PR 5398: If we have not decided to include any loadable sections in
7516 the output then we will not have a glue owner bfd. This is OK, it
7517 just means that there is nothing else for us to do here. */
7518 if (globals->bfd_of_glue_owner == NULL)
7519 return TRUE;
7520
252b5132
RH		 7521 /* Rummage around all the relocs and map the glue vectors. */
7522 sec = abfd->sections;
7523
7524 if (sec == NULL)
b34976b6 7525 return TRUE;
252b5132
RH		 7526
7527 for (; sec != NULL; sec = sec->next)
7528 {
7529 if (sec->reloc_count == 0)
7530 continue;
7531
2f475487
AM		 7532 if ((sec->flags & SEC_EXCLUDE) != 0)
7533 continue;
7534
0ffa91dd 7535 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 7536
9b485d32 7537 /* Load the relocs. */
6cdc0ccc 7538 internal_relocs
906e58ca 7539 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 7540
6cdc0ccc
AM		 7541 if (internal_relocs == NULL)
7542 goto error_return;
252b5132 7543
6cdc0ccc
AM		 7544 irelend = internal_relocs + sec->reloc_count;
7545 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 7546 {
7547 long r_type;
7548 unsigned long r_index;
252b5132
RH		 7549
7550 struct elf_link_hash_entry *h;
7551
7552 r_type = ELF32_R_TYPE (irel->r_info);
7553 r_index = ELF32_R_SYM (irel->r_info);
7554
9b485d32 7555 /* These are the only relocation types we care about. */
ba96a88f 7556 if ( r_type != R_ARM_PC24
845b51d6 7557 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 7558 continue;
7559
7560 /* Get the section contents if we haven't done so already. */
7561 if (contents == NULL)
7562 {
7563 /* Get cached copy if it exists. */
7564 if (elf_section_data (sec)->this_hdr.contents != NULL)
7565 contents = elf_section_data (sec)->this_hdr.contents;
7566 else
7567 {
7568 /* Go get them off disk. */
57e8b36a 7569 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 7570 goto error_return;
7571 }
7572 }
7573
845b51d6
PB		 7574 if (r_type == R_ARM_V4BX)
7575 {
7576 int reg;
7577
7578 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7579 record_arm_bx_glue (link_info, reg);
7580 continue;
7581 }
7582
a7c10850 7583 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 7584 h = NULL;
7585
9b485d32 7586 /* We don't care about local symbols. */
252b5132
RH		 7587 if (r_index < symtab_hdr->sh_info)
7588 continue;
7589
9b485d32 7590 /* This is an external symbol. */
252b5132
RH		 7591 r_index -= symtab_hdr->sh_info;
7592 h = (struct elf_link_hash_entry *)
7593 elf_sym_hashes (abfd)[r_index];
7594
7595 /* If the relocation is against a static symbol it must be within
7596 the current section and so cannot be a cross ARM/Thumb relocation. */
7597 if (h == NULL)
7598 continue;
7599
d504ffc8
DJ		 7600 /* If the call will go through a PLT entry then we do not need
7601 glue. */
362d30a1 7602 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 7603 continue;
7604
252b5132
RH		 7605 switch (r_type)
7606 {
7607 case R_ARM_PC24:
7608 /* This one is a call from arm code. We need to look up
99059e56
RM		 7609 the target of the call. If it is a thumb target, we
7610 insert glue. */
39d911fc
TP		 7611 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7612 == ST_BRANCH_TO_THUMB)
252b5132
RH		 7613 record_arm_to_thumb_glue (link_info, h);
7614 break;
7615
252b5132 7616 default:
c6596c5e 7617 abort ();
252b5132
RH		 7618 }
7619 }
6cdc0ccc
AM		 7620
7621 if (contents != NULL
7622 && elf_section_data (sec)->this_hdr.contents != contents)
7623 free (contents);
7624 contents = NULL;
7625
7626 if (internal_relocs != NULL
7627 && elf_section_data (sec)->relocs != internal_relocs)
7628 free (internal_relocs);
7629 internal_relocs = NULL;
252b5132
RH		 7630 }
7631
b34976b6 7632 return TRUE;
9a5aca8c 7633
252b5132 7634error_return:
6cdc0ccc
AM		 7635 if (contents != NULL
7636 && elf_section_data (sec)->this_hdr.contents != contents)
7637 free (contents);
7638 if (internal_relocs != NULL
7639 && elf_section_data (sec)->relocs != internal_relocs)
7640 free (internal_relocs);
9a5aca8c 7641
b34976b6 7642 return FALSE;
252b5132 7643}
7e392df6 7644#endif
252b5132 7645
eb043451 7646
c7b8f16e
JB		 7647/* Initialise maps of ARM/Thumb/data for input BFDs. */
7648
7649void
7650bfd_elf32_arm_init_maps (bfd *abfd)
7651{
7652 Elf_Internal_Sym *isymbuf;
7653 Elf_Internal_Shdr *hdr;
7654 unsigned int i, localsyms;
7655
af1f4419
NC		 7656 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
7657 if (! is_arm_elf (abfd))
7658 return;
7659
c7b8f16e
JB		 7660 if ((abfd->flags & DYNAMIC) != 0)
7661 return;
7662
0ffa91dd 7663 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 7664 localsyms = hdr->sh_info;
7665
7666 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
7667 should contain the number of local symbols, which should come before any
7668 global symbols. Mapping symbols are always local. */
7669 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
7670 NULL);
7671
7672 /* No internal symbols read? Skip this BFD. */
7673 if (isymbuf == NULL)
7674 return;
7675
7676 for (i = 0; i < localsyms; i++)
7677 {
7678 Elf_Internal_Sym *isym = &isymbuf[i];
7679 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
7680 const char *name;
906e58ca 7681
c7b8f16e 7682 if (sec != NULL
99059e56
RM		 7683 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
7684 {
7685 name = bfd_elf_string_from_elf_section (abfd,
7686 hdr->sh_link, isym->st_name);
906e58ca 7687
99059e56 7688 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 7689 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 7690 elf32_arm_section_map_add (sec, name[1], isym->st_value);
7691 }
c7b8f16e
JB		 7692 }
7693}
7694
7695
48229727
JB		 7696/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
7697 say what they wanted. */
7698
7699void
7700bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
7701{
7702 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7703 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7704
4dfe6ac6
NC		 7705 if (globals == NULL)
7706 return;
7707
48229727
JB		 7708 if (globals->fix_cortex_a8 == -1)
7709 {
7710 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
7711 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
7712 && (out_attr[Tag_CPU_arch_profile].i == 'A'
7713 || out_attr[Tag_CPU_arch_profile].i == 0))
7714 globals->fix_cortex_a8 = 1;
7715 else
7716 globals->fix_cortex_a8 = 0;
7717 }
7718}
7719
7720
c7b8f16e
JB		 7721void
7722bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
7723{
7724 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 7725 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 7726
4dfe6ac6
NC		 7727 if (globals == NULL)
7728 return;
c7b8f16e
JB		 7729 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
7730 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
7731 {
7732 switch (globals->vfp11_fix)
99059e56
RM		 7733 {
7734 case BFD_ARM_VFP11_FIX_DEFAULT:
7735 case BFD_ARM_VFP11_FIX_NONE:
7736 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7737 break;
7738
7739 default:
7740 /* Give a warning, but do as the user requests anyway. */
871b3ab2 7741 _bfd_error_handler (_("%pB: warning: selected VFP11 erratum "
99059e56
RM		 7742 "workaround is not necessary for target architecture"), obfd);
7743 }
c7b8f16e
JB		 7744 }
7745 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
7746 /* For earlier architectures, we might need the workaround, but do not
7747 enable it by default. If users is running with broken hardware, they
7748 must enable the erratum fix explicitly. */
7749 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
7750}
7751
a504d23a
LA		 7752void
7753bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
7754{
7755 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7756 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
7757
7758 if (globals == NULL)
7759 return;
7760
7761 /* We assume only Cortex-M4 may require the fix. */
7762 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
7763 || out_attr[Tag_CPU_arch_profile].i != 'M')
7764 {
7765 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
7766 /* Give a warning, but do as the user requests anyway. */
4eca0228 7767 _bfd_error_handler
871b3ab2 7768 (_("%pB: warning: selected STM32L4XX erratum "
a504d23a
LA		 7769 "workaround is not necessary for target architecture"), obfd);
7770 }
7771}
c7b8f16e 7772
906e58ca
NC		 7773enum bfd_arm_vfp11_pipe
7774{
c7b8f16e
JB		 7775 VFP11_FMAC,
7776 VFP11_LS,
7777 VFP11_DS,
7778 VFP11_BAD
7779};
7780
7781/* Return a VFP register number. This is encoded as RX:X for single-precision
7782 registers, or X:RX for double-precision registers, where RX is the group of
7783 four bits in the instruction encoding and X is the single extension bit.
7784 RX and X fields are specified using their lowest (starting) bit. The return
7785 value is:
7786
7787 0...31: single-precision registers s0...s31
7788 32...63: double-precision registers d0...d31.
906e58ca 7789
c7b8f16e
JB		 7790 Although X should be zero for VFP11 (encoding d0...d15 only), we might
7791 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 7792
c7b8f16e
JB		 7793static unsigned int
7794bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 7795 unsigned int x)
c7b8f16e
JB		 7796{
7797 if (is_double)
7798 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
7799 else
7800 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
7801}
7802
7803/* Set bits in *WMASK according to a register number REG as encoded by
7804 bfd_arm_vfp11_regno(). Ignore d16-d31. */
7805
7806static void
7807bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
7808{
7809 if (reg < 32)
7810 *wmask |= 1 << reg;
7811 else if (reg < 48)
7812 *wmask |= 3 << ((reg - 32) * 2);
7813}
7814
7815/* Return TRUE if WMASK overwrites anything in REGS. */
7816
7817static bfd_boolean
7818bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
7819{
7820 int i;
906e58ca 7821
c7b8f16e
JB		 7822 for (i = 0; i < numregs; i++)
7823 {
7824 unsigned int reg = regs[i];
7825
7826 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 7827 return TRUE;
906e58ca 7828
c7b8f16e
JB		 7829 reg -= 32;
7830
7831 if (reg >= 16)
99059e56 7832 continue;
906e58ca 7833
c7b8f16e 7834 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 7835 return TRUE;
c7b8f16e 7836 }
906e58ca 7837
c7b8f16e
JB		 7838 return FALSE;
7839}
7840
7841/* In this function, we're interested in two things: finding input registers
7842 for VFP data-processing instructions, and finding the set of registers which
7843 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
7844 hold the written set, so FLDM etc. are easy to deal with (we're only
7845 interested in 32 SP registers or 16 dp registers, due to the VFP version
7846 implemented by the chip in question). DP registers are marked by setting
7847 both SP registers in the write mask). */
7848
7849static enum bfd_arm_vfp11_pipe
7850bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 7851 int *numregs)
c7b8f16e 7852{
91d6fa6a 7853 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 7854 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
7855
7856 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
7857 {
7858 unsigned int pqrs;
7859 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7860 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
7861
7862 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 7863 | ((insn & 0x00300000) >> 19)
7864 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 7865
7866 switch (pqrs)
99059e56
RM		 7867 {
7868 case 0: /* fmac[sd]. */
7869 case 1: /* fnmac[sd]. */
7870 case 2: /* fmsc[sd]. */
7871 case 3: /* fnmsc[sd]. */
7872 vpipe = VFP11_FMAC;
7873 bfd_arm_vfp11_write_mask (destmask, fd);
7874 regs[0] = fd;
7875 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7876 regs[2] = fm;
7877 *numregs = 3;
7878 break;
7879
7880 case 4: /* fmul[sd]. */
7881 case 5: /* fnmul[sd]. */
7882 case 6: /* fadd[sd]. */
7883 case 7: /* fsub[sd]. */
7884 vpipe = VFP11_FMAC;
7885 goto vfp_binop;
7886
7887 case 8: /* fdiv[sd]. */
7888 vpipe = VFP11_DS;
7889 vfp_binop:
7890 bfd_arm_vfp11_write_mask (destmask, fd);
7891 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7892 regs[1] = fm;
7893 *numregs = 2;
7894 break;
7895
7896 case 15: /* extended opcode. */
7897 {
7898 unsigned int extn = ((insn >> 15) & 0x1e)
7899 | ((insn >> 7) & 1);
7900
7901 switch (extn)
7902 {
7903 case 0: /* fcpy[sd]. */
7904 case 1: /* fabs[sd]. */
7905 case 2: /* fneg[sd]. */
7906 case 8: /* fcmp[sd]. */
7907 case 9: /* fcmpe[sd]. */
7908 case 10: /* fcmpz[sd]. */
7909 case 11: /* fcmpez[sd]. */
7910 case 16: /* fuito[sd]. */
7911 case 17: /* fsito[sd]. */
7912 case 24: /* ftoui[sd]. */
7913 case 25: /* ftouiz[sd]. */
7914 case 26: /* ftosi[sd]. */
7915 case 27: /* ftosiz[sd]. */
7916 /* These instructions will not bounce due to underflow. */
7917 *numregs = 0;
7918 vpipe = VFP11_FMAC;
7919 break;
7920
7921 case 3: /* fsqrt[sd]. */
7922 /* fsqrt cannot underflow, but it can (perhaps) overwrite
7923 registers to cause the erratum in previous instructions. */
7924 bfd_arm_vfp11_write_mask (destmask, fd);
7925 vpipe = VFP11_DS;
7926 break;
7927
7928 case 15: /* fcvt{ds,sd}. */
7929 {
7930 int rnum = 0;
7931
7932 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 7933
7934 /* Only FCVTSD can underflow. */
99059e56
RM		 7935 if ((insn & 0x100) != 0)
7936 regs[rnum++] = fm;
c7b8f16e 7937
99059e56 7938 *numregs = rnum;
c7b8f16e 7939
99059e56
RM		 7940 vpipe = VFP11_FMAC;
7941 }
7942 break;
c7b8f16e 7943
99059e56
RM		 7944 default:
7945 return VFP11_BAD;
7946 }
7947 }
7948 break;
c7b8f16e 7949
99059e56
RM		 7950 default:
7951 return VFP11_BAD;
7952 }
c7b8f16e
JB		 7953 }
7954 /* Two-register transfer. */
7955 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
7956 {
7957 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 7958
c7b8f16e
JB		 7959 if ((insn & 0x100000) == 0)
7960 {
99059e56
RM		 7961 if (is_double)
7962 bfd_arm_vfp11_write_mask (destmask, fm);
7963 else
7964 {
7965 bfd_arm_vfp11_write_mask (destmask, fm);
7966 bfd_arm_vfp11_write_mask (destmask, fm + 1);
7967 }
c7b8f16e
JB		 7968 }
7969
91d6fa6a 7970 vpipe = VFP11_LS;
c7b8f16e
JB		 7971 }
7972 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
7973 {
7974 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7975 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 7976
c7b8f16e 7977 switch (puw)
99059e56
RM		 7978 {
7979 case 0: /* Two-reg transfer. We should catch these above. */
7980 abort ();
906e58ca 7981
99059e56
RM		 7982 case 2: /* fldm[sdx]. */
7983 case 3:
7984 case 5:
7985 {
7986 unsigned int i, offset = insn & 0xff;
c7b8f16e 7987
99059e56
RM		 7988 if (is_double)
7989 offset >>= 1;
c7b8f16e 7990
99059e56
RM		 7991 for (i = fd; i < fd + offset; i++)
7992 bfd_arm_vfp11_write_mask (destmask, i);
7993 }
7994 break;
906e58ca 7995
99059e56
RM		 7996 case 4: /* fld[sd]. */
7997 case 6:
7998 bfd_arm_vfp11_write_mask (destmask, fd);
7999 break;
906e58ca 8000
99059e56
RM		 8001 default:
8002 return VFP11_BAD;
8003 }
c7b8f16e 8004
91d6fa6a 8005 vpipe = VFP11_LS;
c7b8f16e
JB		 8006 }
8007 /* Single-register transfer. Note L==0. */
8008 else if ((insn & 0x0f100e10) == 0x0e000a10)
8009 {
8010 unsigned int opcode = (insn >> 21) & 7;
8011 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8012
8013 switch (opcode)
99059e56
RM		 8014 {
8015 case 0: /* fmsr/fmdlr. */
8016 case 1: /* fmdhr. */
8017 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8018 destination register. I don't know if this is exactly right,
8019 but it is the conservative choice. */
8020 bfd_arm_vfp11_write_mask (destmask, fn);
8021 break;
8022
8023 case 7: /* fmxr. */
8024 break;
8025 }
c7b8f16e 8026
91d6fa6a 8027 vpipe = VFP11_LS;
c7b8f16e
JB		 8028 }
8029
91d6fa6a 8030 return vpipe;
c7b8f16e
JB		 8031}
8032
8033
8034static int elf32_arm_compare_mapping (const void * a, const void * b);
8035
8036
8037/* Look for potentially-troublesome code sequences which might trigger the
8038 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8039 (available from ARM) for details of the erratum. A short version is
8040 described in ld.texinfo. */
8041
8042bfd_boolean
8043bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8044{
8045 asection *sec;
8046 bfd_byte *contents = NULL;
8047 int state = 0;
8048 int regs[3], numregs = 0;
8049 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8050 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 8051
4dfe6ac6
NC		 8052 if (globals == NULL)
8053 return FALSE;
8054
c7b8f16e
JB		 8055 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8056 The states transition as follows:
906e58ca 8057
c7b8f16e 8058 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 8059 A VFP FMAC-pipeline instruction has been seen. Fill
8060 regs[0]..regs[numregs-1] with its input operands. Remember this
8061 instruction in 'first_fmac'.
c7b8f16e
JB		 8062
8063 1 -> 2
99059e56
RM		 8064 Any instruction, except for a VFP instruction which overwrites
8065 regs[*].
906e58ca 8066
c7b8f16e
JB		 8067 1 -> 3 [ -> 0 ] or
8068 2 -> 3 [ -> 0 ]
99059e56
RM		 8069 A VFP instruction has been seen which overwrites any of regs[*].
8070 We must make a veneer! Reset state to 0 before examining next
8071 instruction.
906e58ca 8072
c7b8f16e 8073 2 -> 0
99059e56
RM		 8074 If we fail to match anything in state 2, reset to state 0 and reset
8075 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 8076
8077 If the VFP11 vector mode is in use, there must be at least two unrelated
8078 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 8079 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 8080
8081 /* If we are only performing a partial link do not bother
8082 to construct any glue. */
0e1862bb 8083 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 8084 return TRUE;
8085
0ffa91dd
NC		 8086 /* Skip if this bfd does not correspond to an ELF image. */
8087 if (! is_arm_elf (abfd))
8088 return TRUE;
906e58ca 8089
c7b8f16e
JB		 8090 /* We should have chosen a fix type by the time we get here. */
8091 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8092
8093 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8094 return TRUE;
2e6030b9 8095
33a7ffc2
JM		 8096 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8097 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8098 return TRUE;
8099
c7b8f16e
JB		 8100 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8101 {
8102 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8103 struct _arm_elf_section_data *sec_data;
8104
8105 /* If we don't have executable progbits, we're not interested in this
99059e56 8106 section. Also skip if section is to be excluded. */
c7b8f16e 8107 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 8108 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8109 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 8110 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 8111 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 8112 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8113 continue;
c7b8f16e
JB		 8114
8115 sec_data = elf32_arm_section_data (sec);
906e58ca 8116
c7b8f16e 8117 if (sec_data->mapcount == 0)
99059e56 8118 continue;
906e58ca 8119
c7b8f16e
JB		 8120 if (elf_section_data (sec)->this_hdr.contents != NULL)
8121 contents = elf_section_data (sec)->this_hdr.contents;
8122 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8123 goto error_return;
8124
8125 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8126 elf32_arm_compare_mapping);
8127
8128 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 8129 {
8130 unsigned int span_start = sec_data->map[span].vma;
8131 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 8132 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 8133 char span_type = sec_data->map[span].type;
8134
8135 /* FIXME: Only ARM mode is supported at present. We may need to
8136 support Thumb-2 mode also at some point. */
8137 if (span_type != 'a')
8138 continue;
8139
8140 for (i = span_start; i < span_end;)
8141 {
8142 unsigned int next_i = i + 4;
8143 unsigned int insn = bfd_big_endian (abfd)
8144 ? (contents[i] << 24)
8145 | (contents[i + 1] << 16)
8146 | (contents[i + 2] << 8)
8147 | contents[i + 3]
8148 : (contents[i + 3] << 24)
8149 | (contents[i + 2] << 16)
8150 | (contents[i + 1] << 8)
8151 | contents[i];
8152 unsigned int writemask = 0;
8153 enum bfd_arm_vfp11_pipe vpipe;
8154
8155 switch (state)
8156 {
8157 case 0:
8158 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8159 &numregs);
8160 /* I'm assuming the VFP11 erratum can trigger with denorm
8161 operands on either the FMAC or the DS pipeline. This might
8162 lead to slightly overenthusiastic veneer insertion. */
8163 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8164 {
8165 state = use_vector ? 1 : 2;
8166 first_fmac = i;
8167 veneer_of_insn = insn;
8168 }
8169 break;
8170
8171 case 1:
8172 {
8173 int other_regs[3], other_numregs;
8174 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8175 other_regs,
99059e56
RM		 8176 &other_numregs);
8177 if (vpipe != VFP11_BAD
8178 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8179 numregs))
99059e56
RM		 8180 state = 3;
8181 else
8182 state = 2;
8183 }
8184 break;
8185
8186 case 2:
8187 {
8188 int other_regs[3], other_numregs;
8189 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 8190 other_regs,
99059e56
RM		 8191 &other_numregs);
8192 if (vpipe != VFP11_BAD
8193 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 8194 numregs))
99059e56
RM		 8195 state = 3;
8196 else
8197 {
8198 state = 0;
8199 next_i = first_fmac + 4;
8200 }
8201 }
8202 break;
8203
8204 case 3:
8205 abort (); /* Should be unreachable. */
8206 }
8207
8208 if (state == 3)
8209 {
8210 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8211 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8212
8213 elf32_arm_section_data (sec)->erratumcount += 1;
8214
8215 newerr->u.b.vfp_insn = veneer_of_insn;
8216
8217 switch (span_type)
8218 {
8219 case 'a':
8220 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8221 break;
8222
8223 default:
8224 abort ();
8225 }
8226
8227 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 8228 first_fmac);
8229
99059e56 8230 newerr->vma = -1;
c7b8f16e 8231
99059e56
RM		 8232 newerr->next = sec_data->erratumlist;
8233 sec_data->erratumlist = newerr;
c7b8f16e 8234
99059e56
RM		 8235 state = 0;
8236 }
c7b8f16e 8237
99059e56
RM		 8238 i = next_i;
8239 }
8240 }
906e58ca 8241
c7b8f16e 8242 if (contents != NULL
99059e56
RM		 8243 && elf_section_data (sec)->this_hdr.contents != contents)
8244 free (contents);
c7b8f16e
JB		 8245 contents = NULL;
8246 }
8247
8248 return TRUE;
8249
8250error_return:
8251 if (contents != NULL
8252 && elf_section_data (sec)->this_hdr.contents != contents)
8253 free (contents);
906e58ca 8254
c7b8f16e
JB		 8255 return FALSE;
8256}
8257
8258/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8259 after sections have been laid out, using specially-named symbols. */
8260
8261void
8262bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8263 struct bfd_link_info *link_info)
8264{
8265 asection *sec;
8266 struct elf32_arm_link_hash_table *globals;
8267 char *tmp_name;
906e58ca 8268
0e1862bb 8269 if (bfd_link_relocatable (link_info))
c7b8f16e 8270 return;
2e6030b9
MS		 8271
8272 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 8273 if (! is_arm_elf (abfd))
2e6030b9
MS		 8274 return;
8275
c7b8f16e 8276 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8277 if (globals == NULL)
8278 return;
906e58ca 8279
21d799b5 8280 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 8281 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 8282
8283 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8284 {
8285 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8286 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 8287
c7b8f16e 8288 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 8289 {
8290 struct elf_link_hash_entry *myh;
8291 bfd_vma vma;
8292
8293 switch (errnode->type)
8294 {
8295 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8296 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8297 /* Find veneer symbol. */
8298 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 8299 errnode->u.b.veneer->u.v.id);
8300
99059e56
RM		 8301 myh = elf_link_hash_lookup
8302 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 8303
a504d23a 8304 if (myh == NULL)
90b6238f
AM		 8305 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8306 abfd, "VFP11", tmp_name);
a504d23a
LA		 8307
8308 vma = myh->root.u.def.section->output_section->vma
8309 + myh->root.u.def.section->output_offset
8310 + myh->root.u.def.value;
8311
8312 errnode->u.b.veneer->vma = vma;
8313 break;
8314
8315 case VFP11_ERRATUM_ARM_VENEER:
8316 case VFP11_ERRATUM_THUMB_VENEER:
8317 /* Find return location. */
8318 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8319 errnode->u.v.id);
8320
8321 myh = elf_link_hash_lookup
8322 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8323
8324 if (myh == NULL)
90b6238f
AM		 8325 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8326 abfd, "VFP11", tmp_name);
a504d23a
LA		 8327
8328 vma = myh->root.u.def.section->output_section->vma
8329 + myh->root.u.def.section->output_offset
8330 + myh->root.u.def.value;
8331
8332 errnode->u.v.branch->vma = vma;
8333 break;
8334
8335 default:
8336 abort ();
8337 }
8338 }
8339 }
8340
8341 free (tmp_name);
8342}
8343
8344/* Find virtual-memory addresses for STM32L4XX erratum veneers and
8345 return locations after sections have been laid out, using
8346 specially-named symbols. */
8347
8348void
8349bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8350 struct bfd_link_info *link_info)
8351{
8352 asection *sec;
8353 struct elf32_arm_link_hash_table *globals;
8354 char *tmp_name;
8355
8356 if (bfd_link_relocatable (link_info))
8357 return;
8358
8359 /* Skip if this bfd does not correspond to an ELF image. */
8360 if (! is_arm_elf (abfd))
8361 return;
8362
8363 globals = elf32_arm_hash_table (link_info);
8364 if (globals == NULL)
8365 return;
8366
8367 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8368 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8369
8370 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8371 {
8372 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8373 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8374
8375 for (; errnode != NULL; errnode = errnode->next)
8376 {
8377 struct elf_link_hash_entry *myh;
8378 bfd_vma vma;
8379
8380 switch (errnode->type)
8381 {
8382 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8383 /* Find veneer symbol. */
8384 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8385 errnode->u.b.veneer->u.v.id);
8386
8387 myh = elf_link_hash_lookup
8388 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8389
8390 if (myh == NULL)
90b6238f
AM		 8391 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8392 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8393
8394 vma = myh->root.u.def.section->output_section->vma
8395 + myh->root.u.def.section->output_offset
8396 + myh->root.u.def.value;
8397
8398 errnode->u.b.veneer->vma = vma;
8399 break;
8400
8401 case STM32L4XX_ERRATUM_VENEER:
8402 /* Find return location. */
8403 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8404 errnode->u.v.id);
8405
8406 myh = elf_link_hash_lookup
8407 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
8408
8409 if (myh == NULL)
90b6238f
AM		 8410 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8411 abfd, "STM32L4XX", tmp_name);
a504d23a
LA		 8412
8413 vma = myh->root.u.def.section->output_section->vma
8414 + myh->root.u.def.section->output_offset
8415 + myh->root.u.def.value;
8416
8417 errnode->u.v.branch->vma = vma;
8418 break;
8419
8420 default:
8421 abort ();
8422 }
8423 }
8424 }
8425
8426 free (tmp_name);
8427}
8428
8429static inline bfd_boolean
8430is_thumb2_ldmia (const insn32 insn)
8431{
8432 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8433 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8434 return (insn & 0xffd02000) == 0xe8900000;
8435}
8436
8437static inline bfd_boolean
8438is_thumb2_ldmdb (const insn32 insn)
8439{
8440 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8441 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8442 return (insn & 0xffd02000) == 0xe9100000;
8443}
8444
8445static inline bfd_boolean
8446is_thumb2_vldm (const insn32 insn)
8447{
8448 /* A6.5 Extension register load or store instruction
8449 A7.7.229
9239bbd3
CM		 8450 We look for SP 32-bit and DP 64-bit registers.
8451 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8452 <list> is consecutive 64-bit registers
8453 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 8454 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8455 <list> is consecutive 32-bit registers
8456 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8457 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8458 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8459 return
9239bbd3
CM		 8460 (((insn & 0xfe100f00) == 0xec100b00) ||
8461 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 8462 && /* (IA without !). */
8463 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 8464 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 8465 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8466 /* (DB with !). */
8467 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8468}
8469
8470/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8471 VLDM opcode and:
8472 - computes the number and the mode of memory accesses
8473 - decides if the replacement should be done:
8474 . replaces only if > 8-word accesses
8475 . or (testing purposes only) replaces all accesses. */
8476
8477static bfd_boolean
8478stm32l4xx_need_create_replacing_stub (const insn32 insn,
8479 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8480{
9239bbd3 8481 int nb_words = 0;
a504d23a
LA		 8482
8483 /* The field encoding the register list is the same for both LDMIA
8484 and LDMDB encodings. */
8485 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
b25e998d 8486 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
a504d23a 8487 else if (is_thumb2_vldm (insn))
9239bbd3 8488 nb_words = (insn & 0xff);
a504d23a
LA		 8489
8490 /* DEFAULT mode accounts for the real bug condition situation,
8491 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8492 return
9239bbd3 8493 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 8494 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
8495}
8496
8497/* Look for potentially-troublesome code sequences which might trigger
8498 the STM STM32L4XX erratum. */
8499
8500bfd_boolean
8501bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8502 struct bfd_link_info *link_info)
8503{
8504 asection *sec;
8505 bfd_byte *contents = NULL;
8506 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8507
8508 if (globals == NULL)
8509 return FALSE;
8510
8511 /* If we are only performing a partial link do not bother
8512 to construct any glue. */
8513 if (bfd_link_relocatable (link_info))
8514 return TRUE;
8515
8516 /* Skip if this bfd does not correspond to an ELF image. */
8517 if (! is_arm_elf (abfd))
8518 return TRUE;
8519
8520 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8521 return TRUE;
8522
8523 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8524 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8525 return TRUE;
8526
8527 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8528 {
8529 unsigned int i, span;
8530 struct _arm_elf_section_data *sec_data;
8531
8532 /* If we don't have executable progbits, we're not interested in this
8533 section. Also skip if section is to be excluded. */
8534 if (elf_section_type (sec) != SHT_PROGBITS
8535 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8536 || (sec->flags & SEC_EXCLUDE) != 0
8537 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8538 || sec->output_section == bfd_abs_section_ptr
8539 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8540 continue;
8541
8542 sec_data = elf32_arm_section_data (sec);
c7b8f16e 8543
a504d23a
LA		 8544 if (sec_data->mapcount == 0)
8545 continue;
c7b8f16e 8546
a504d23a
LA		 8547 if (elf_section_data (sec)->this_hdr.contents != NULL)
8548 contents = elf_section_data (sec)->this_hdr.contents;
8549 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8550 goto error_return;
c7b8f16e 8551
a504d23a
LA		 8552 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8553 elf32_arm_compare_mapping);
c7b8f16e 8554
a504d23a
LA		 8555 for (span = 0; span < sec_data->mapcount; span++)
8556 {
8557 unsigned int span_start = sec_data->map[span].vma;
8558 unsigned int span_end = (span == sec_data->mapcount - 1)
8559 ? sec->size : sec_data->map[span + 1].vma;
8560 char span_type = sec_data->map[span].type;
8561 int itblock_current_pos = 0;
c7b8f16e 8562
a504d23a
LA		 8563 /* Only Thumb2 mode need be supported with this CM4 specific
8564 code, we should not encounter any arm mode eg span_type
8565 != 'a'. */
8566 if (span_type != 't')
8567 continue;
c7b8f16e 8568
a504d23a
LA		 8569 for (i = span_start; i < span_end;)
8570 {
8571 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8572 bfd_boolean insn_32bit = FALSE;
8573 bfd_boolean is_ldm = FALSE;
8574 bfd_boolean is_vldm = FALSE;
8575 bfd_boolean is_not_last_in_it_block = FALSE;
8576
8577 /* The first 16-bits of all 32-bit thumb2 instructions start
8578 with opcode[15..13]=0b111 and the encoded op1 can be anything
8579 except opcode[12..11]!=0b00.
8580 See 32-bit Thumb instruction encoding. */
8581 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8582 insn_32bit = TRUE;
c7b8f16e 8583
a504d23a
LA		 8584 /* Compute the predicate that tells if the instruction
8585 is concerned by the IT block
8586 - Creates an error if there is a ldm that is not
8587 last in the IT block thus cannot be replaced
8588 - Otherwise we can create a branch at the end of the
8589 IT block, it will be controlled naturally by IT
8590 with the proper pseudo-predicate
8591 - So the only interesting predicate is the one that
8592 tells that we are not on the last item of an IT
8593 block. */
8594 if (itblock_current_pos != 0)
8595 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 8596
a504d23a
LA		 8597 if (insn_32bit)
8598 {
8599 /* Load the rest of the insn (in manual-friendly order). */
8600 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8601 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8602 is_vldm = is_thumb2_vldm (insn);
8603
8604 /* Veneers are created for (v)ldm depending on
8605 option flags and memory accesses conditions; but
8606 if the instruction is not the last instruction of
8607 an IT block, we cannot create a jump there, so we
8608 bail out. */
5025eb7c
AO		 8609 if ((is_ldm || is_vldm)
8610 && stm32l4xx_need_create_replacing_stub
a504d23a
LA		 8611 (insn, globals->stm32l4xx_fix))
8612 {
8613 if (is_not_last_in_it_block)
8614 {
4eca0228 8615 _bfd_error_handler
695344c0 8616 /* xgettext:c-format */
871b3ab2 8617 (_("%pB(%pA+%#x): error: multiple load detected"
90b6238f
AM		 8618 " in non-last IT block instruction:"
8619 " STM32L4XX veneer cannot be generated; "
8620 "use gcc option -mrestrict-it to generate"
8621 " only one instruction per IT block"),
d42c267e 8622 abfd, sec, i);
a504d23a
LA		 8623 }
8624 else
8625 {
8626 elf32_stm32l4xx_erratum_list *newerr =
8627 (elf32_stm32l4xx_erratum_list *)
8628 bfd_zmalloc
8629 (sizeof (elf32_stm32l4xx_erratum_list));
8630
8631 elf32_arm_section_data (sec)
8632 ->stm32l4xx_erratumcount += 1;
8633 newerr->u.b.insn = insn;
8634 /* We create only thumb branches. */
8635 newerr->type =
8636 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8637 record_stm32l4xx_erratum_veneer
8638 (link_info, newerr, abfd, sec,
8639 i,
8640 is_ldm ?
8641 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8642 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8643 newerr->vma = -1;
8644 newerr->next = sec_data->stm32l4xx_erratumlist;
8645 sec_data->stm32l4xx_erratumlist = newerr;
8646 }
8647 }
8648 }
8649 else
8650 {
8651 /* A7.7.37 IT p208
8652 IT blocks are only encoded in T1
8653 Encoding T1: IT{x{y{z}}} <firstcond>
8654 1 0 1 1 - 1 1 1 1 - firstcond - mask
8655 if mask = '0000' then see 'related encodings'
8656 We don't deal with UNPREDICTABLE, just ignore these.
8657 There can be no nested IT blocks so an IT block
8658 is naturally a new one for which it is worth
8659 computing its size. */
5025eb7c
AO		 8660 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00)
8661 && ((insn & 0x000f) != 0x0000);
a504d23a
LA		 8662 /* If we have a new IT block we compute its size. */
8663 if (is_newitblock)
8664 {
8665 /* Compute the number of instructions controlled
8666 by the IT block, it will be used to decide
8667 whether we are inside an IT block or not. */
8668 unsigned int mask = insn & 0x000f;
8669 itblock_current_pos = 4 - ctz (mask);
8670 }
8671 }
8672
8673 i += insn_32bit ? 4 : 2;
99059e56
RM		 8674 }
8675 }
a504d23a
LA		 8676
8677 if (contents != NULL
8678 && elf_section_data (sec)->this_hdr.contents != contents)
8679 free (contents);
8680 contents = NULL;
c7b8f16e 8681 }
906e58ca 8682
a504d23a
LA		 8683 return TRUE;
8684
8685error_return:
8686 if (contents != NULL
8687 && elf_section_data (sec)->this_hdr.contents != contents)
8688 free (contents);
c7b8f16e 8689
a504d23a
LA		 8690 return FALSE;
8691}
c7b8f16e 8692
eb043451
PB		 8693/* Set target relocation values needed during linking. */
8694
8695void
68c39892 8696bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
bf21ed78 8697 struct bfd_link_info *link_info,
68c39892 8698 struct elf32_arm_params *params)
eb043451
PB		 8699{
8700 struct elf32_arm_link_hash_table *globals;
8701
8702 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8703 if (globals == NULL)
8704 return;
eb043451 8705
68c39892
TP		 8706 globals->target1_is_rel = params->target1_is_rel;
8707 if (strcmp (params->target2_type, "rel") == 0)
eb043451 8708 globals->target2_reloc = R_ARM_REL32;
68c39892 8709 else if (strcmp (params->target2_type, "abs") == 0)
eeac373a 8710 globals->target2_reloc = R_ARM_ABS32;
68c39892 8711 else if (strcmp (params->target2_type, "got-rel") == 0)
eb043451
PB		 8712 globals->target2_reloc = R_ARM_GOT_PREL;
8713 else
8714 {
90b6238f 8715 _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"),
68c39892 8716 params->target2_type);
eb043451 8717 }
68c39892
TP		 8718 globals->fix_v4bx = params->fix_v4bx;
8719 globals->use_blx |= params->use_blx;
8720 globals->vfp11_fix = params->vfp11_denorm_fix;
8721 globals->stm32l4xx_fix = params->stm32l4xx_fix;
8722 globals->pic_veneer = params->pic_veneer;
8723 globals->fix_cortex_a8 = params->fix_cortex_a8;
8724 globals->fix_arm1176 = params->fix_arm1176;
8725 globals->cmse_implib = params->cmse_implib;
8726 globals->in_implib_bfd = params->in_implib_bfd;
bf21ed78 8727
0ffa91dd 8728 BFD_ASSERT (is_arm_elf (output_bfd));
68c39892
TP		 8729 elf_arm_tdata (output_bfd)->no_enum_size_warning
8730 = params->no_enum_size_warning;
8731 elf_arm_tdata (output_bfd)->no_wchar_size_warning
8732 = params->no_wchar_size_warning;
eb043451 8733}
eb043451 8734
12a0a0fd 8735/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 8736
12a0a0fd
PB		 8737static void
8738insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
8739{
8740 bfd_vma upper;
8741 bfd_vma lower;
8742 int reloc_sign;
8743
8744 BFD_ASSERT ((offset & 1) == 0);
8745
8746 upper = bfd_get_16 (abfd, insn);
8747 lower = bfd_get_16 (abfd, insn + 2);
8748 reloc_sign = (offset < 0) ? 1 : 0;
8749 upper = (upper & ~(bfd_vma) 0x7ff)
8750 | ((offset >> 12) & 0x3ff)
8751 | (reloc_sign << 10);
906e58ca 8752 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 8753 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
8754 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
8755 | ((offset >> 1) & 0x7ff);
8756 bfd_put_16 (abfd, upper, insn);
8757 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 8758}
8759
9b485d32
NC		 8760/* Thumb code calling an ARM function. */
8761
252b5132 8762static int
57e8b36a 8763elf32_thumb_to_arm_stub (struct bfd_link_info * info,
07d6d2b8
AM		 8764 const char * name,
8765 bfd * input_bfd,
8766 bfd * output_bfd,
8767 asection * input_section,
8768 bfd_byte * hit_data,
8769 asection * sym_sec,
8770 bfd_vma offset,
8771 bfd_signed_vma addend,
8772 bfd_vma val,
f2a9dd69 8773 char **error_message)
252b5132 8774{
bcbdc74c 8775 asection * s = 0;
dc810e39 8776 bfd_vma my_offset;
252b5132 8777 long int ret_offset;
bcbdc74c
NC		 8778 struct elf_link_hash_entry * myh;
8779 struct elf32_arm_link_hash_table * globals;
252b5132 8780
f2a9dd69 8781 myh = find_thumb_glue (info, name, error_message);
252b5132 8782 if (myh == NULL)
b34976b6 8783 return FALSE;
252b5132
RH		 8784
8785 globals = elf32_arm_hash_table (info);
252b5132
RH		 8786 BFD_ASSERT (globals != NULL);
8787 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8788
8789 my_offset = myh->root.u.def.value;
8790
3d4d4302
AM		 8791 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8792 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 8793
8794 BFD_ASSERT (s != NULL);
8795 BFD_ASSERT (s->contents != NULL);
8796 BFD_ASSERT (s->output_section != NULL);
8797
8798 if ((my_offset & 0x01) == 0x01)
8799 {
8800 if (sym_sec != NULL
8801 && sym_sec->owner != NULL
8802 && !INTERWORK_FLAG (sym_sec->owner))
8803 {
4eca0228 8804 _bfd_error_handler
90b6238f
AM		 8805 (_("%pB(%s): warning: interworking not enabled;"
8806 " first occurrence: %pB: %s call to %s"),
8807 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
252b5132 8808
b34976b6 8809 return FALSE;
252b5132
RH		 8810 }
8811
8812 --my_offset;
8813 myh->root.u.def.value = my_offset;
8814
52ab56c2
PB		 8815 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
8816 s->contents + my_offset);
252b5132 8817
52ab56c2
PB		 8818 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
8819 s->contents + my_offset + 2);
252b5132
RH		 8820
8821 ret_offset =
9b485d32
NC		 8822 /* Address of destination of the stub. */
8823 ((bfd_signed_vma) val)
252b5132 8824 - ((bfd_signed_vma)
57e8b36a
NC		 8825 /* Offset from the start of the current section
8826 to the start of the stubs. */
9b485d32
NC		 8827 (s->output_offset
8828 /* Offset of the start of this stub from the start of the stubs. */
8829 + my_offset
8830 /* Address of the start of the current section. */
8831 + s->output_section->vma)
8832 /* The branch instruction is 4 bytes into the stub. */
8833 + 4
8834 /* ARM branches work from the pc of the instruction + 8. */
8835 + 8);
252b5132 8836
52ab56c2
PB		 8837 put_arm_insn (globals, output_bfd,
8838 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
8839 s->contents + my_offset + 4);
252b5132
RH		 8840 }
8841
8842 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
8843
427bfd90
NC		 8844 /* Now go back and fix up the original BL insn to point to here. */
8845 ret_offset =
8846 /* Address of where the stub is located. */
8847 (s->output_section->vma + s->output_offset + my_offset)
8848 /* Address of where the BL is located. */
57e8b36a
NC		 8849 - (input_section->output_section->vma + input_section->output_offset
8850 + offset)
427bfd90
NC		 8851 /* Addend in the relocation. */
8852 - addend
8853 /* Biassing for PC-relative addressing. */
8854 - 8;
252b5132 8855
12a0a0fd 8856 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 8857
b34976b6 8858 return TRUE;
252b5132
RH		 8859}
8860
a4fd1a8e 8861/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 8862
a4fd1a8e
PB		 8863static struct elf_link_hash_entry *
8864elf32_arm_create_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 8865 const char * name,
8866 bfd * input_bfd,
8867 bfd * output_bfd,
8868 asection * sym_sec,
8869 bfd_vma val,
8870 asection * s,
8871 char ** error_message)
252b5132 8872{
dc810e39 8873 bfd_vma my_offset;
252b5132 8874 long int ret_offset;
bcbdc74c
NC		 8875 struct elf_link_hash_entry * myh;
8876 struct elf32_arm_link_hash_table * globals;
252b5132 8877
f2a9dd69 8878 myh = find_arm_glue (info, name, error_message);
252b5132 8879 if (myh == NULL)
a4fd1a8e 8880 return NULL;
252b5132
RH		 8881
8882 globals = elf32_arm_hash_table (info);
252b5132
RH		 8883 BFD_ASSERT (globals != NULL);
8884 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8885
8886 my_offset = myh->root.u.def.value;
252b5132
RH		 8887
8888 if ((my_offset & 0x01) == 0x01)
8889 {
8890 if (sym_sec != NULL
8891 && sym_sec->owner != NULL
8892 && !INTERWORK_FLAG (sym_sec->owner))
8893 {
4eca0228 8894 _bfd_error_handler
90b6238f
AM		 8895 (_("%pB(%s): warning: interworking not enabled;"
8896 " first occurrence: %pB: %s call to %s"),
8897 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
252b5132 8898 }
9b485d32 8899
252b5132
RH		 8900 --my_offset;
8901 myh->root.u.def.value = my_offset;
8902
0e1862bb
L		 8903 if (bfd_link_pic (info)
8904 || globals->root.is_relocatable_executable
27e55c4d 8905 || globals->pic_veneer)
8f6277f5
PB		 8906 {
8907 /* For relocatable objects we can't use absolute addresses,
8908 so construct the address from a relative offset. */
8909 /* TODO: If the offset is small it's probably worth
8910 constructing the address with adds. */
52ab56c2
PB		 8911 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
8912 s->contents + my_offset);
8913 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
8914 s->contents + my_offset + 4);
8915 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
8916 s->contents + my_offset + 8);
8f6277f5
PB		 8917 /* Adjust the offset by 4 for the position of the add,
8918 and 8 for the pipeline offset. */
8919 ret_offset = (val - (s->output_offset
8920 + s->output_section->vma
8921 + my_offset + 12))
8922 | 1;
8923 bfd_put_32 (output_bfd, ret_offset,
8924 s->contents + my_offset + 12);
8925 }
26079076
PB		 8926 else if (globals->use_blx)
8927 {
8928 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
8929 s->contents + my_offset);
8930
8931 /* It's a thumb address. Add the low order bit. */
8932 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
8933 s->contents + my_offset + 4);
8934 }
8f6277f5
PB		 8935 else
8936 {
52ab56c2
PB		 8937 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
8938 s->contents + my_offset);
252b5132 8939
52ab56c2
PB		 8940 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
8941 s->contents + my_offset + 4);
252b5132 8942
8f6277f5
PB		 8943 /* It's a thumb address. Add the low order bit. */
8944 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
8945 s->contents + my_offset + 8);
8029a119
NC		 8946
8947 my_offset += 12;
8f6277f5 8948 }
252b5132
RH		 8949 }
8950
8951 BFD_ASSERT (my_offset <= globals->arm_glue_size);
8952
a4fd1a8e
PB		 8953 return myh;
8954}
8955
8956/* Arm code calling a Thumb function. */
8957
8958static int
8959elf32_arm_to_thumb_stub (struct bfd_link_info * info,
07d6d2b8
AM		 8960 const char * name,
8961 bfd * input_bfd,
8962 bfd * output_bfd,
8963 asection * input_section,
8964 bfd_byte * hit_data,
8965 asection * sym_sec,
8966 bfd_vma offset,
8967 bfd_signed_vma addend,
8968 bfd_vma val,
f2a9dd69 8969 char **error_message)
a4fd1a8e
PB		 8970{
8971 unsigned long int tmp;
8972 bfd_vma my_offset;
8973 asection * s;
8974 long int ret_offset;
8975 struct elf_link_hash_entry * myh;
8976 struct elf32_arm_link_hash_table * globals;
8977
8978 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8979 BFD_ASSERT (globals != NULL);
8980 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8981
3d4d4302
AM		 8982 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8983 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8984 BFD_ASSERT (s != NULL);
8985 BFD_ASSERT (s->contents != NULL);
8986 BFD_ASSERT (s->output_section != NULL);
8987
8988 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 8989 sym_sec, val, s, error_message);
a4fd1a8e
PB		 8990 if (!myh)
8991 return FALSE;
8992
8993 my_offset = myh->root.u.def.value;
252b5132
RH		 8994 tmp = bfd_get_32 (input_bfd, hit_data);
8995 tmp = tmp & 0xFF000000;
8996
9b485d32 8997 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 8998 ret_offset = (s->output_offset
8999 + my_offset
9000 + s->output_section->vma
9001 - (input_section->output_offset
9002 + input_section->output_section->vma
9003 + offset + addend)
9004 - 8);
9a5aca8c 9005
252b5132
RH		 9006 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9007
dc810e39 9008 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 9009
b34976b6 9010 return TRUE;
252b5132
RH		 9011}
9012
a4fd1a8e
PB		 9013/* Populate Arm stub for an exported Thumb function. */
9014
9015static bfd_boolean
9016elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9017{
9018 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9019 asection * s;
9020 struct elf_link_hash_entry * myh;
9021 struct elf32_arm_link_hash_entry *eh;
9022 struct elf32_arm_link_hash_table * globals;
9023 asection *sec;
9024 bfd_vma val;
f2a9dd69 9025 char *error_message;
a4fd1a8e 9026
906e58ca 9027 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 9028 /* Allocate stubs for exported Thumb functions on v4t. */
9029 if (eh->export_glue == NULL)
9030 return TRUE;
9031
9032 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 9033 BFD_ASSERT (globals != NULL);
9034 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9035
3d4d4302
AM		 9036 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9037 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 9038 BFD_ASSERT (s != NULL);
9039 BFD_ASSERT (s->contents != NULL);
9040 BFD_ASSERT (s->output_section != NULL);
9041
9042 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 9043
9044 BFD_ASSERT (sec->output_section != NULL);
9045
a4fd1a8e
PB		 9046 val = eh->export_glue->root.u.def.value + sec->output_offset
9047 + sec->output_section->vma;
8029a119 9048
a4fd1a8e
PB		 9049 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9050 h->root.u.def.section->owner,
f2a9dd69
DJ		 9051 globals->obfd, sec, val, s,
9052 &error_message);
a4fd1a8e
PB		 9053 BFD_ASSERT (myh);
9054 return TRUE;
9055}
9056
845b51d6
PB		 9057/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9058
9059static bfd_vma
9060elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9061{
9062 bfd_byte *p;
9063 bfd_vma glue_addr;
9064 asection *s;
9065 struct elf32_arm_link_hash_table *globals;
9066
9067 globals = elf32_arm_hash_table (info);
845b51d6
PB		 9068 BFD_ASSERT (globals != NULL);
9069 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9070
3d4d4302
AM		 9071 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9072 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 9073 BFD_ASSERT (s != NULL);
9074 BFD_ASSERT (s->contents != NULL);
9075 BFD_ASSERT (s->output_section != NULL);
9076
9077 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9078
9079 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9080
9081 if ((globals->bx_glue_offset[reg] & 1) == 0)
9082 {
9083 p = s->contents + glue_addr;
9084 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9085 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9086 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9087 globals->bx_glue_offset[reg] |= 1;
9088 }
9089
9090 return glue_addr + s->output_section->vma + s->output_offset;
9091}
9092
a4fd1a8e
PB		 9093/* Generate Arm stubs for exported Thumb symbols. */
9094static void
906e58ca 9095elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 9096 struct bfd_link_info *link_info)
9097{
9098 struct elf32_arm_link_hash_table * globals;
9099
8029a119
NC		 9100 if (link_info == NULL)
9101 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 9102 return;
9103
9104 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 9105 if (globals == NULL)
9106 return;
9107
84c08195
PB		 9108 /* If blx is available then exported Thumb symbols are OK and there is
9109 nothing to do. */
a4fd1a8e
PB		 9110 if (globals->use_blx)
9111 return;
9112
9113 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9114 link_info);
9115}
9116
47beaa6a
RS		 9117/* Reserve space for COUNT dynamic relocations in relocation selection
9118 SRELOC. */
9119
9120static void
9121elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9122 bfd_size_type count)
9123{
9124 struct elf32_arm_link_hash_table *htab;
9125
9126 htab = elf32_arm_hash_table (info);
9127 BFD_ASSERT (htab->root.dynamic_sections_created);
9128 if (sreloc == NULL)
9129 abort ();
9130 sreloc->size += RELOC_SIZE (htab) * count;
9131}
9132
34e77a92
RS		 9133/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9134 dynamic, the relocations should go in SRELOC, otherwise they should
9135 go in the special .rel.iplt section. */
9136
9137static void
9138elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9139 bfd_size_type count)
9140{
9141 struct elf32_arm_link_hash_table *htab;
9142
9143 htab = elf32_arm_hash_table (info);
9144 if (!htab->root.dynamic_sections_created)
9145 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9146 else
9147 {
9148 BFD_ASSERT (sreloc != NULL);
9149 sreloc->size += RELOC_SIZE (htab) * count;
9150 }
9151}
9152
47beaa6a
RS		 9153/* Add relocation REL to the end of relocation section SRELOC. */
9154
9155static void
9156elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9157 asection *sreloc, Elf_Internal_Rela *rel)
9158{
9159 bfd_byte *loc;
9160 struct elf32_arm_link_hash_table *htab;
9161
9162 htab = elf32_arm_hash_table (info);
34e77a92
RS		 9163 if (!htab->root.dynamic_sections_created
9164 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9165 sreloc = htab->root.irelplt;
47beaa6a
RS		 9166 if (sreloc == NULL)
9167 abort ();
9168 loc = sreloc->contents;
9169 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9170 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9171 abort ();
9172 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9173}
9174
34e77a92
RS		 9175/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9176 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9177 to .plt. */
9178
9179static void
9180elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9181 bfd_boolean is_iplt_entry,
9182 union gotplt_union *root_plt,
9183 struct arm_plt_info *arm_plt)
9184{
9185 struct elf32_arm_link_hash_table *htab;
9186 asection *splt;
9187 asection *sgotplt;
9188
9189 htab = elf32_arm_hash_table (info);
9190
9191 if (is_iplt_entry)
9192 {
9193 splt = htab->root.iplt;
9194 sgotplt = htab->root.igotplt;
9195
99059e56
RM		 9196 /* NaCl uses a special first entry in .iplt too. */
9197 if (htab->nacl_p && splt->size == 0)
9198 splt->size += htab->plt_header_size;
9199
34e77a92
RS		 9200 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9201 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9202 }
9203 else
9204 {
9205 splt = htab->root.splt;
9206 sgotplt = htab->root.sgotplt;
9207
9208 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9209 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9210
9211 /* If this is the first .plt entry, make room for the special
9212 first entry. */
9213 if (splt->size == 0)
9214 splt->size += htab->plt_header_size;
9f19ab6d
WN		 9215
9216 htab->next_tls_desc_index++;
34e77a92
RS		 9217 }
9218
9219 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9220 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9221 splt->size += PLT_THUMB_STUB_SIZE;
9222 root_plt->offset = splt->size;
9223 splt->size += htab->plt_entry_size;
9224
9225 if (!htab->symbian_p)
9226 {
9227 /* We also need to make an entry in the .got.plt section, which
9228 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 9229 if (is_iplt_entry)
9230 arm_plt->got_offset = sgotplt->size;
9231 else
9232 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 9233 sgotplt->size += 4;
9234 }
9235}
9236
b38cadfb
NC		 9237static bfd_vma
9238arm_movw_immediate (bfd_vma value)
9239{
9240 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9241}
9242
9243static bfd_vma
9244arm_movt_immediate (bfd_vma value)
9245{
9246 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9247}
9248
34e77a92
RS		 9249/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9250 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9251 Otherwise, DYNINDX is the index of the symbol in the dynamic
9252 symbol table and SYM_VALUE is undefined.
9253
9254 ROOT_PLT points to the offset of the PLT entry from the start of its
9255 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 9256 bookkeeping information.
34e77a92 9257
57460bcf
NC		 9258 Returns FALSE if there was a problem. */
9259
9260static bfd_boolean
34e77a92
RS		 9261elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9262 union gotplt_union *root_plt,
9263 struct arm_plt_info *arm_plt,
9264 int dynindx, bfd_vma sym_value)
9265{
9266 struct elf32_arm_link_hash_table *htab;
9267 asection *sgot;
9268 asection *splt;
9269 asection *srel;
9270 bfd_byte *loc;
9271 bfd_vma plt_index;
9272 Elf_Internal_Rela rel;
9273 bfd_vma plt_header_size;
9274 bfd_vma got_header_size;
9275
9276 htab = elf32_arm_hash_table (info);
9277
9278 /* Pick the appropriate sections and sizes. */
9279 if (dynindx == -1)
9280 {
9281 splt = htab->root.iplt;
9282 sgot = htab->root.igotplt;
9283 srel = htab->root.irelplt;
9284
9285 /* There are no reserved entries in .igot.plt, and no special
9286 first entry in .iplt. */
9287 got_header_size = 0;
9288 plt_header_size = 0;
9289 }
9290 else
9291 {
9292 splt = htab->root.splt;
9293 sgot = htab->root.sgotplt;
9294 srel = htab->root.srelplt;
9295
9296 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9297 plt_header_size = htab->plt_header_size;
9298 }
9299 BFD_ASSERT (splt != NULL && srel != NULL);
9300
9301 /* Fill in the entry in the procedure linkage table. */
9302 if (htab->symbian_p)
9303 {
9304 BFD_ASSERT (dynindx >= 0);
9305 put_arm_insn (htab, output_bfd,
9306 elf32_arm_symbian_plt_entry[0],
9307 splt->contents + root_plt->offset);
9308 bfd_put_32 (output_bfd,
9309 elf32_arm_symbian_plt_entry[1],
9310 splt->contents + root_plt->offset + 4);
9311
9312 /* Fill in the entry in the .rel.plt section. */
9313 rel.r_offset = (splt->output_section->vma
9314 + splt->output_offset
9315 + root_plt->offset + 4);
9316 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
9317
9318 /* Get the index in the procedure linkage table which
9319 corresponds to this symbol. This is the index of this symbol
9320 in all the symbols for which we are making plt entries. The
9321 first entry in the procedure linkage table is reserved. */
9322 plt_index = ((root_plt->offset - plt_header_size)
9323 / htab->plt_entry_size);
9324 }
9325 else
9326 {
9327 bfd_vma got_offset, got_address, plt_address;
9328 bfd_vma got_displacement, initial_got_entry;
9329 bfd_byte * ptr;
9330
9331 BFD_ASSERT (sgot != NULL);
9332
9333 /* Get the offset into the .(i)got.plt table of the entry that
9334 corresponds to this function. */
9335 got_offset = (arm_plt->got_offset & -2);
9336
9337 /* Get the index in the procedure linkage table which
9338 corresponds to this symbol. This is the index of this symbol
9339 in all the symbols for which we are making plt entries.
9340 After the reserved .got.plt entries, all symbols appear in
9341 the same order as in .plt. */
9342 plt_index = (got_offset - got_header_size) / 4;
9343
9344 /* Calculate the address of the GOT entry. */
9345 got_address = (sgot->output_section->vma
9346 + sgot->output_offset
9347 + got_offset);
9348
9349 /* ...and the address of the PLT entry. */
9350 plt_address = (splt->output_section->vma
9351 + splt->output_offset
9352 + root_plt->offset);
9353
9354 ptr = splt->contents + root_plt->offset;
0e1862bb 9355 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 9356 {
9357 unsigned int i;
9358 bfd_vma val;
9359
9360 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9361 {
9362 val = elf32_arm_vxworks_shared_plt_entry[i];
9363 if (i == 2)
9364 val |= got_address - sgot->output_section->vma;
9365 if (i == 5)
9366 val |= plt_index * RELOC_SIZE (htab);
9367 if (i == 2 || i == 5)
9368 bfd_put_32 (output_bfd, val, ptr);
9369 else
9370 put_arm_insn (htab, output_bfd, val, ptr);
9371 }
9372 }
9373 else if (htab->vxworks_p)
9374 {
9375 unsigned int i;
9376 bfd_vma val;
9377
9378 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9379 {
9380 val = elf32_arm_vxworks_exec_plt_entry[i];
9381 if (i == 2)
9382 val |= got_address;
9383 if (i == 4)
9384 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9385 if (i == 5)
9386 val |= plt_index * RELOC_SIZE (htab);
9387 if (i == 2 || i == 5)
9388 bfd_put_32 (output_bfd, val, ptr);
9389 else
9390 put_arm_insn (htab, output_bfd, val, ptr);
9391 }
9392
9393 loc = (htab->srelplt2->contents
9394 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9395
9396 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9397 referencing the GOT for this PLT entry. */
9398 rel.r_offset = plt_address + 8;
9399 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9400 rel.r_addend = got_offset;
9401 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9402 loc += RELOC_SIZE (htab);
9403
9404 /* Create the R_ARM_ABS32 relocation referencing the
9405 beginning of the PLT for this GOT entry. */
9406 rel.r_offset = got_address;
9407 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9408 rel.r_addend = 0;
9409 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9410 }
b38cadfb
NC		 9411 else if (htab->nacl_p)
9412 {
9413 /* Calculate the displacement between the PLT slot and the
9414 common tail that's part of the special initial PLT slot. */
6034aab8 9415 int32_t tail_displacement
b38cadfb
NC		 9416 = ((splt->output_section->vma + splt->output_offset
9417 + ARM_NACL_PLT_TAIL_OFFSET)
9418 - (plt_address + htab->plt_entry_size + 4));
9419 BFD_ASSERT ((tail_displacement & 3) == 0);
9420 tail_displacement >>= 2;
9421
9422 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9423 || (-tail_displacement & 0xff000000) == 0);
9424
9425 /* Calculate the displacement between the PLT slot and the entry
9426 in the GOT. The offset accounts for the value produced by
9427 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 9428 got_displacement = (got_address
99059e56 9429 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 9430
9431 /* NaCl does not support interworking at all. */
9432 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9433
9434 put_arm_insn (htab, output_bfd,
9435 elf32_arm_nacl_plt_entry[0]
9436 | arm_movw_immediate (got_displacement),
9437 ptr + 0);
9438 put_arm_insn (htab, output_bfd,
9439 elf32_arm_nacl_plt_entry[1]
9440 | arm_movt_immediate (got_displacement),
9441 ptr + 4);
9442 put_arm_insn (htab, output_bfd,
9443 elf32_arm_nacl_plt_entry[2],
9444 ptr + 8);
9445 put_arm_insn (htab, output_bfd,
9446 elf32_arm_nacl_plt_entry[3]
9447 | (tail_displacement & 0x00ffffff),
9448 ptr + 12);
9449 }
57460bcf
NC		 9450 else if (using_thumb_only (htab))
9451 {
eed94f8f 9452 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 9453 if (!using_thumb2 (htab))
eed94f8f
NC		 9454 {
9455 /* FIXME: We ought to be able to generate thumb-1 PLT
9456 instructions... */
90b6238f 9457 _bfd_error_handler (_("%pB: warning: thumb-1 mode PLT generation not currently supported"),
eed94f8f
NC		 9458 output_bfd);
9459 return FALSE;
9460 }
57460bcf 9461
eed94f8f
NC		 9462 /* Calculate the displacement between the PLT slot and the entry in
9463 the GOT. The 12-byte offset accounts for the value produced by
9464 adding to pc in the 3rd instruction of the PLT stub. */
9465 got_displacement = got_address - (plt_address + 12);
9466
9467 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9468 instead of 'put_thumb_insn'. */
9469 put_arm_insn (htab, output_bfd,
9470 elf32_thumb2_plt_entry[0]
9471 | ((got_displacement & 0x000000ff) << 16)
9472 | ((got_displacement & 0x00000700) << 20)
9473 | ((got_displacement & 0x00000800) >> 1)
9474 | ((got_displacement & 0x0000f000) >> 12),
9475 ptr + 0);
9476 put_arm_insn (htab, output_bfd,
9477 elf32_thumb2_plt_entry[1]
9478 | ((got_displacement & 0x00ff0000) )
9479 | ((got_displacement & 0x07000000) << 4)
9480 | ((got_displacement & 0x08000000) >> 17)
9481 | ((got_displacement & 0xf0000000) >> 28),
9482 ptr + 4);
9483 put_arm_insn (htab, output_bfd,
9484 elf32_thumb2_plt_entry[2],
9485 ptr + 8);
9486 put_arm_insn (htab, output_bfd,
9487 elf32_thumb2_plt_entry[3],
9488 ptr + 12);
57460bcf 9489 }
34e77a92
RS		 9490 else
9491 {
9492 /* Calculate the displacement between the PLT slot and the
9493 entry in the GOT. The eight-byte offset accounts for the
9494 value produced by adding to pc in the first instruction
9495 of the PLT stub. */
9496 got_displacement = got_address - (plt_address + 8);
9497
34e77a92
RS		 9498 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9499 {
9500 put_thumb_insn (htab, output_bfd,
9501 elf32_arm_plt_thumb_stub[0], ptr - 4);
9502 put_thumb_insn (htab, output_bfd,
9503 elf32_arm_plt_thumb_stub[1], ptr - 2);
9504 }
9505
1db37fe6
YG		 9506 if (!elf32_arm_use_long_plt_entry)
9507 {
9508 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9509
9510 put_arm_insn (htab, output_bfd,
9511 elf32_arm_plt_entry_short[0]
9512 | ((got_displacement & 0x0ff00000) >> 20),
9513 ptr + 0);
9514 put_arm_insn (htab, output_bfd,
9515 elf32_arm_plt_entry_short[1]
9516 | ((got_displacement & 0x000ff000) >> 12),
9517 ptr+ 4);
9518 put_arm_insn (htab, output_bfd,
9519 elf32_arm_plt_entry_short[2]
9520 | (got_displacement & 0x00000fff),
9521 ptr + 8);
34e77a92 9522#ifdef FOUR_WORD_PLT
1db37fe6 9523 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 9524#endif
1db37fe6
YG		 9525 }
9526 else
9527 {
9528 put_arm_insn (htab, output_bfd,
9529 elf32_arm_plt_entry_long[0]
9530 | ((got_displacement & 0xf0000000) >> 28),
9531 ptr + 0);
9532 put_arm_insn (htab, output_bfd,
9533 elf32_arm_plt_entry_long[1]
9534 | ((got_displacement & 0x0ff00000) >> 20),
9535 ptr + 4);
9536 put_arm_insn (htab, output_bfd,
9537 elf32_arm_plt_entry_long[2]
9538 | ((got_displacement & 0x000ff000) >> 12),
9539 ptr+ 8);
9540 put_arm_insn (htab, output_bfd,
9541 elf32_arm_plt_entry_long[3]
9542 | (got_displacement & 0x00000fff),
9543 ptr + 12);
9544 }
34e77a92
RS		 9545 }
9546
9547 /* Fill in the entry in the .rel(a).(i)plt section. */
9548 rel.r_offset = got_address;
9549 rel.r_addend = 0;
9550 if (dynindx == -1)
9551 {
9552 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9553 The dynamic linker or static executable then calls SYM_VALUE
9554 to determine the correct run-time value of the .igot.plt entry. */
9555 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9556 initial_got_entry = sym_value;
9557 }
9558 else
9559 {
9560 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9561 initial_got_entry = (splt->output_section->vma
9562 + splt->output_offset);
9563 }
9564
9565 /* Fill in the entry in the global offset table. */
9566 bfd_put_32 (output_bfd, initial_got_entry,
9567 sgot->contents + got_offset);
9568 }
9569
aba8c3de
WN		 9570 if (dynindx == -1)
9571 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9572 else
9573 {
9574 loc = srel->contents + plt_index * RELOC_SIZE (htab);
9575 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9576 }
57460bcf
NC		 9577
9578 return TRUE;
34e77a92
RS		 9579}
9580
eb043451
PB		 9581/* Some relocations map to different relocations depending on the
9582 target. Return the real relocation. */
8029a119 9583
eb043451
PB		 9584static int
9585arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
9586 int r_type)
9587{
9588 switch (r_type)
9589 {
9590 case R_ARM_TARGET1:
9591 if (globals->target1_is_rel)
9592 return R_ARM_REL32;
9593 else
9594 return R_ARM_ABS32;
9595
9596 case R_ARM_TARGET2:
9597 return globals->target2_reloc;
9598
9599 default:
9600 return r_type;
9601 }
9602}
eb043451 9603
ba93b8ac
DJ		 9604/* Return the base VMA address which should be subtracted from real addresses
9605 when resolving @dtpoff relocation.
9606 This is PT_TLS segment p_vaddr. */
9607
9608static bfd_vma
9609dtpoff_base (struct bfd_link_info *info)
9610{
9611 /* If tls_sec is NULL, we should have signalled an error already. */
9612 if (elf_hash_table (info)->tls_sec == NULL)
9613 return 0;
9614 return elf_hash_table (info)->tls_sec->vma;
9615}
9616
9617/* Return the relocation value for @tpoff relocation
9618 if STT_TLS virtual address is ADDRESS. */
9619
9620static bfd_vma
9621tpoff (struct bfd_link_info *info, bfd_vma address)
9622{
9623 struct elf_link_hash_table *htab = elf_hash_table (info);
9624 bfd_vma base;
9625
9626 /* If tls_sec is NULL, we should have signalled an error already. */
9627 if (htab->tls_sec == NULL)
9628 return 0;
9629 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
9630 return address - htab->tls_sec->vma + base;
9631}
9632
00a97672
RS		 9633/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
9634 VALUE is the relocation value. */
9635
9636static bfd_reloc_status_type
9637elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
9638{
9639 if (value > 0xfff)
9640 return bfd_reloc_overflow;
9641
9642 value |= bfd_get_32 (abfd, data) & 0xfffff000;
9643 bfd_put_32 (abfd, value, data);
9644 return bfd_reloc_ok;
9645}
9646
0855e32b
NS		 9647/* Handle TLS relaxations. Relaxing is possible for symbols that use
9648 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
9649 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
9650
9651 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
9652 is to then call final_link_relocate. Return other values in the
62672b10
NS		 9653 case of error.
9654
9655 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
9656 the pre-relaxed code. It would be nice if the relocs were updated
9657 to match the optimization. */
0855e32b 9658
b38cadfb 9659static bfd_reloc_status_type
0855e32b 9660elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 9661 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 9662 Elf_Internal_Rela *rel, unsigned long is_local)
9663{
9664 unsigned long insn;
b38cadfb 9665
0855e32b
NS		 9666 switch (ELF32_R_TYPE (rel->r_info))
9667 {
9668 default:
9669 return bfd_reloc_notsupported;
b38cadfb 9670
0855e32b
NS		 9671 case R_ARM_TLS_GOTDESC:
9672 if (is_local)
9673 insn = 0;
9674 else
9675 {
9676 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9677 if (insn & 1)
9678 insn -= 5; /* THUMB */
9679 else
9680 insn -= 8; /* ARM */
9681 }
9682 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9683 return bfd_reloc_continue;
9684
9685 case R_ARM_THM_TLS_DESCSEQ:
9686 /* Thumb insn. */
9687 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
9688 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
9689 {
9690 if (is_local)
9691 /* nop */
9692 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9693 }
9694 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
9695 {
9696 if (is_local)
9697 /* nop */
9698 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9699 else
9700 /* ldr rx,[ry] */
9701 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
9702 }
9703 else if ((insn & 0xff87) == 0x4780) /* blx rx */
9704 {
9705 if (is_local)
9706 /* nop */
9707 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
9708 else
9709 /* mov r0, rx */
9710 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
9711 contents + rel->r_offset);
9712 }
9713 else
9714 {
9715 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
9716 /* It's a 32 bit instruction, fetch the rest of it for
9717 error generation. */
9718 insn = (insn << 16)
9719 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
4eca0228 9720 _bfd_error_handler
695344c0 9721 /* xgettext:c-format */
2dcf00ce 9722 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 9723 "unexpected %s instruction '%#lx' in TLS trampoline"),
9724 input_bfd, input_sec, (uint64_t) rel->r_offset,
9725 "Thumb", insn);
0855e32b
NS		 9726 return bfd_reloc_notsupported;
9727 }
9728 break;
b38cadfb 9729
0855e32b
NS		 9730 case R_ARM_TLS_DESCSEQ:
9731 /* arm insn. */
9732 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
9733 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
9734 {
9735 if (is_local)
9736 /* mov rx, ry */
9737 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
9738 contents + rel->r_offset);
9739 }
9740 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
9741 {
9742 if (is_local)
9743 /* nop */
9744 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9745 else
9746 /* ldr rx,[ry] */
9747 bfd_put_32 (input_bfd, insn & 0xfffff000,
9748 contents + rel->r_offset);
9749 }
9750 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
9751 {
9752 if (is_local)
9753 /* nop */
9754 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
9755 else
9756 /* mov r0, rx */
9757 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
9758 contents + rel->r_offset);
9759 }
9760 else
9761 {
4eca0228 9762 _bfd_error_handler
695344c0 9763 /* xgettext:c-format */
2dcf00ce 9764 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f
AM		 9765 "unexpected %s instruction '%#lx' in TLS trampoline"),
9766 input_bfd, input_sec, (uint64_t) rel->r_offset,
9767 "ARM", insn);
0855e32b
NS		 9768 return bfd_reloc_notsupported;
9769 }
9770 break;
9771
9772 case R_ARM_TLS_CALL:
9773 /* GD->IE relaxation, turn the instruction into 'nop' or
9774 'ldr r0, [pc,r0]' */
9775 insn = is_local ? 0xe1a00000 : 0xe79f0000;
9776 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
9777 break;
b38cadfb 9778
0855e32b 9779 case R_ARM_THM_TLS_CALL:
6a631e86 9780 /* GD->IE relaxation. */
0855e32b
NS		 9781 if (!is_local)
9782 /* add r0,pc; ldr r0, [r0] */
9783 insn = 0x44786800;
60a019a0 9784 else if (using_thumb2 (globals))
0855e32b
NS		 9785 /* nop.w */
9786 insn = 0xf3af8000;
9787 else
9788 /* nop; nop */
9789 insn = 0xbf00bf00;
b38cadfb 9790
0855e32b
NS		 9791 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
9792 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
9793 break;
9794 }
9795 return bfd_reloc_ok;
9796}
9797
4962c51a
MS		 9798/* For a given value of n, calculate the value of G_n as required to
9799 deal with group relocations. We return it in the form of an
9800 encoded constant-and-rotation, together with the final residual. If n is
9801 specified as less than zero, then final_residual is filled with the
9802 input value and no further action is performed. */
9803
9804static bfd_vma
9805calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
9806{
9807 int current_n;
9808 bfd_vma g_n;
9809 bfd_vma encoded_g_n = 0;
9810 bfd_vma residual = value; /* Also known as Y_n. */
9811
9812 for (current_n = 0; current_n <= n; current_n++)
9813 {
9814 int shift;
9815
9816 /* Calculate which part of the value to mask. */
9817 if (residual == 0)
99059e56 9818 shift = 0;
4962c51a 9819 else
99059e56
RM		 9820 {
9821 int msb;
9822
9823 /* Determine the most significant bit in the residual and
9824 align the resulting value to a 2-bit boundary. */
9825 for (msb = 30; msb >= 0; msb -= 2)
9826 if (residual & (3 << msb))
9827 break;
9828
9829 /* The desired shift is now (msb - 6), or zero, whichever
9830 is the greater. */
9831 shift = msb - 6;
9832 if (shift < 0)
9833 shift = 0;
9834 }
4962c51a
MS		 9835
9836 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
9837 g_n = residual & (0xff << shift);
9838 encoded_g_n = (g_n >> shift)
99059e56 9839 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 9840
9841 /* Calculate the residual for the next time around. */
9842 residual &= ~g_n;
9843 }
9844
9845 *final_residual = residual;
9846
9847 return encoded_g_n;
9848}
9849
9850/* Given an ARM instruction, determine whether it is an ADD or a SUB.
9851 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 9852
4962c51a 9853static int
906e58ca 9854identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 9855{
9856 int opcode = insn & 0x1e00000;
9857
9858 if (opcode == 1 << 23) /* ADD */
9859 return 1;
9860
9861 if (opcode == 1 << 22) /* SUB */
9862 return -1;
9863
9864 return 0;
9865}
9866
252b5132 9867/* Perform a relocation as part of a final link. */
9b485d32 9868
252b5132 9869static bfd_reloc_status_type
07d6d2b8
AM		 9870elf32_arm_final_link_relocate (reloc_howto_type * howto,
9871 bfd * input_bfd,
9872 bfd * output_bfd,
9873 asection * input_section,
9874 bfd_byte * contents,
9875 Elf_Internal_Rela * rel,
9876 bfd_vma value,
9877 struct bfd_link_info * info,
9878 asection * sym_sec,
9879 const char * sym_name,
9880 unsigned char st_type,
9881 enum arm_st_branch_type branch_type,
0945cdfd 9882 struct elf_link_hash_entry * h,
07d6d2b8
AM		 9883 bfd_boolean * unresolved_reloc_p,
9884 char ** error_message)
9885{
9886 unsigned long r_type = howto->type;
9887 unsigned long r_symndx;
9888 bfd_byte * hit_data = contents + rel->r_offset;
9889 bfd_vma * local_got_offsets;
9890 bfd_vma * local_tlsdesc_gotents;
9891 asection * sgot;
9892 asection * splt;
9893 asection * sreloc = NULL;
9894 asection * srelgot;
9895 bfd_vma addend;
9896 bfd_signed_vma signed_addend;
9897 unsigned char dynreloc_st_type;
9898 bfd_vma dynreloc_value;
ba96a88f 9899 struct elf32_arm_link_hash_table * globals;
34e77a92 9900 struct elf32_arm_link_hash_entry *eh;
07d6d2b8
AM		 9901 union gotplt_union *root_plt;
9902 struct arm_plt_info *arm_plt;
9903 bfd_vma plt_offset;
9904 bfd_vma gotplt_offset;
9905 bfd_boolean has_iplt_entry;
9906 bfd_boolean resolved_to_zero;
f21f3fe0 9907
9c504268 9908 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 9909 if (globals == NULL)
9910 return bfd_reloc_notsupported;
9c504268 9911
0ffa91dd 9912 BFD_ASSERT (is_arm_elf (input_bfd));
47aeb64c 9913 BFD_ASSERT (howto != NULL);
0ffa91dd
NC		 9914
9915 /* Some relocation types map to different relocations depending on the
9c504268 9916 target. We pick the right one here. */
eb043451 9917 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 9918
9919 /* It is possible to have linker relaxations on some TLS access
9920 models. Update our information here. */
9921 r_type = elf32_arm_tls_transition (info, r_type, h);
9922
eb043451
PB		 9923 if (r_type != howto->type)
9924 howto = elf32_arm_howto_from_type (r_type);
9c504268 9925
34e77a92 9926 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 9927 sgot = globals->root.sgot;
252b5132 9928 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 9929 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
9930
34e77a92
RS		 9931 if (globals->root.dynamic_sections_created)
9932 srelgot = globals->root.srelgot;
9933 else
9934 srelgot = NULL;
9935
252b5132
RH		 9936 r_symndx = ELF32_R_SYM (rel->r_info);
9937
4e7fd91e 9938 if (globals->use_rel)
ba96a88f 9939 {
4e7fd91e
PB		 9940 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
9941
9942 if (addend & ((howto->src_mask + 1) >> 1))
9943 {
9944 signed_addend = -1;
9945 signed_addend &= ~ howto->src_mask;
9946 signed_addend |= addend;
9947 }
9948 else
9949 signed_addend = addend;
ba96a88f
NC		 9950 }
9951 else
4e7fd91e 9952 addend = signed_addend = rel->r_addend;
f21f3fe0 9953
39f21624
NC		 9954 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
9955 are resolving a function call relocation. */
9956 if (using_thumb_only (globals)
9957 && (r_type == R_ARM_THM_CALL
9958 || r_type == R_ARM_THM_JUMP24)
9959 && branch_type == ST_BRANCH_TO_ARM)
9960 branch_type = ST_BRANCH_TO_THUMB;
9961
34e77a92
RS		 9962 /* Record the symbol information that should be used in dynamic
9963 relocations. */
9964 dynreloc_st_type = st_type;
9965 dynreloc_value = value;
9966 if (branch_type == ST_BRANCH_TO_THUMB)
9967 dynreloc_value |= 1;
9968
9969 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
9970 VALUE appropriately for relocations that we resolve at link time. */
9971 has_iplt_entry = FALSE;
4ba2ef8f
TP		 9972 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
9973 &arm_plt)
34e77a92
RS		 9974 && root_plt->offset != (bfd_vma) -1)
9975 {
9976 plt_offset = root_plt->offset;
9977 gotplt_offset = arm_plt->got_offset;
9978
9979 if (h == NULL || eh->is_iplt)
9980 {
9981 has_iplt_entry = TRUE;
9982 splt = globals->root.iplt;
9983
9984 /* Populate .iplt entries here, because not all of them will
9985 be seen by finish_dynamic_symbol. The lower bit is set if
9986 we have already populated the entry. */
9987 if (plt_offset & 1)
9988 plt_offset--;
9989 else
9990 {
57460bcf
NC		 9991 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
9992 -1, dynreloc_value))
9993 root_plt->offset |= 1;
9994 else
9995 return bfd_reloc_notsupported;
34e77a92
RS		 9996 }
9997
9998 /* Static relocations always resolve to the .iplt entry. */
9999 st_type = STT_FUNC;
10000 value = (splt->output_section->vma
10001 + splt->output_offset
10002 + plt_offset);
10003 branch_type = ST_BRANCH_TO_ARM;
10004
10005 /* If there are non-call relocations that resolve to the .iplt
10006 entry, then all dynamic ones must too. */
10007 if (arm_plt->noncall_refcount != 0)
10008 {
10009 dynreloc_st_type = st_type;
10010 dynreloc_value = value;
10011 }
10012 }
10013 else
10014 /* We populate the .plt entry in finish_dynamic_symbol. */
10015 splt = globals->root.splt;
10016 }
10017 else
10018 {
10019 splt = NULL;
10020 plt_offset = (bfd_vma) -1;
10021 gotplt_offset = (bfd_vma) -1;
10022 }
10023
95b03e4a
L		 10024 resolved_to_zero = (h != NULL
10025 && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
10026
252b5132
RH		 10027 switch (r_type)
10028 {
10029 case R_ARM_NONE:
28a094c2
DJ		 10030 /* We don't need to find a value for this symbol. It's just a
10031 marker. */
10032 *unresolved_reloc_p = FALSE;
252b5132
RH		 10033 return bfd_reloc_ok;
10034
00a97672
RS		 10035 case R_ARM_ABS12:
10036 if (!globals->vxworks_p)
10037 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
1a0670f3 10038 /* Fall through. */
00a97672 10039
252b5132
RH		 10040 case R_ARM_PC24:
10041 case R_ARM_ABS32:
bb224fc3 10042 case R_ARM_ABS32_NOI:
252b5132 10043 case R_ARM_REL32:
bb224fc3 10044 case R_ARM_REL32_NOI:
5b5bb741
PB		 10045 case R_ARM_CALL:
10046 case R_ARM_JUMP24:
dfc5f959 10047 case R_ARM_XPC25:
eb043451 10048 case R_ARM_PREL31:
7359ea65 10049 case R_ARM_PLT32:
7359ea65
DJ		 10050 /* Handle relocations which should use the PLT entry. ABS32/REL32
10051 will use the symbol's value, which may point to a PLT entry, but we
10052 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 10053 branches in this object should go to it, except if the PLT is too
10054 far away, in which case a long branch stub should be inserted. */
bb224fc3 10055 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 10056 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 10057 && r_type != R_ARM_CALL
10058 && r_type != R_ARM_JUMP24
10059 && r_type != R_ARM_PLT32)
34e77a92 10060 && plt_offset != (bfd_vma) -1)
7359ea65 10061 {
34e77a92
RS		 10062 /* If we've created a .plt section, and assigned a PLT entry
10063 to this function, it must either be a STT_GNU_IFUNC reference
10064 or not be known to bind locally. In other cases, we should
10065 have cleared the PLT entry by now. */
10066 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 10067
10068 value = (splt->output_section->vma
10069 + splt->output_offset
34e77a92 10070 + plt_offset);
0945cdfd 10071 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 10072 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10073 contents, rel->r_offset, value,
00a97672 10074 rel->r_addend);
7359ea65
DJ		 10075 }
10076
67687978
PB		 10077 /* When generating a shared object or relocatable executable, these
10078 relocations are copied into the output file to be resolved at
10079 run time. */
0e1862bb
L		 10080 if ((bfd_link_pic (info)
10081 || globals->root.is_relocatable_executable)
7359ea65 10082 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 10083 && !(globals->vxworks_p
3348747a
NS		 10084 && strcmp (input_section->output_section->name,
10085 ".tls_vars") == 0)
bb224fc3 10086 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 10087 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 10088 && !(input_bfd == globals->stub_bfd
10089 && strstr (input_section->name, STUB_SUFFIX))
7359ea65 10090 && (h == NULL
95b03e4a
L		 10091 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10092 && !resolved_to_zero)
7359ea65
DJ		 10093 || h->root.type != bfd_link_hash_undefweak)
10094 && r_type != R_ARM_PC24
5b5bb741
PB		 10095 && r_type != R_ARM_CALL
10096 && r_type != R_ARM_JUMP24
ee06dc07 10097 && r_type != R_ARM_PREL31
7359ea65 10098 && r_type != R_ARM_PLT32)
252b5132 10099 {
947216bf 10100 Elf_Internal_Rela outrel;
b34976b6 10101 bfd_boolean skip, relocate;
f21f3fe0 10102
52db4ec2
JW		 10103 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10104 && !h->def_regular)
10105 {
10106 char *v = _("shared object");
10107
0e1862bb 10108 if (bfd_link_executable (info))
52db4ec2
JW		 10109 v = _("PIE executable");
10110
4eca0228 10111 _bfd_error_handler
871b3ab2 10112 (_("%pB: relocation %s against external or undefined symbol `%s'"
52db4ec2
JW		 10113 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10114 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10115 return bfd_reloc_notsupported;
10116 }
10117
0945cdfd
DJ		 10118 *unresolved_reloc_p = FALSE;
10119
34e77a92 10120 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 10121 {
83bac4b0
NC		 10122 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10123 ! globals->use_rel);
f21f3fe0 10124
83bac4b0 10125 if (sreloc == NULL)
252b5132 10126 return bfd_reloc_notsupported;
252b5132 10127 }
f21f3fe0 10128
b34976b6
AM		 10129 skip = FALSE;
10130 relocate = FALSE;
f21f3fe0 10131
00a97672 10132 outrel.r_addend = addend;
c629eae0
JJ		 10133 outrel.r_offset =
10134 _bfd_elf_section_offset (output_bfd, info, input_section,
10135 rel->r_offset);
10136 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 10137 skip = TRUE;
0bb2d96a 10138 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 10139 skip = TRUE, relocate = TRUE;
252b5132
RH		 10140 outrel.r_offset += (input_section->output_section->vma
10141 + input_section->output_offset);
f21f3fe0 10142
252b5132 10143 if (skip)
0bb2d96a 10144 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 10145 else if (h != NULL
10146 && h->dynindx != -1
0e1862bb 10147 && (!bfd_link_pic (info)
1dcb9720
JW		 10148 || !(bfd_link_pie (info)
10149 || SYMBOLIC_BIND (info, h))
f5385ebf 10150 || !h->def_regular))
5e681ec4 10151 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 10152 else
10153 {
a16385dc
MM		 10154 int symbol;
10155
5e681ec4 10156 /* This symbol is local, or marked to become local. */
34e77a92 10157 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 10158 if (globals->symbian_p)
6366ff1e 10159 {
74541ad4
AM		 10160 asection *osec;
10161
6366ff1e
MM		 10162 /* On Symbian OS, the data segment and text segement
10163 can be relocated independently. Therefore, we
10164 must indicate the segment to which this
10165 relocation is relative. The BPABI allows us to
10166 use any symbol in the right segment; we just use
10167 the section symbol as it is convenient. (We
10168 cannot use the symbol given by "h" directly as it
74541ad4
AM		 10169 will not appear in the dynamic symbol table.)
10170
10171 Note that the dynamic linker ignores the section
10172 symbol value, so we don't subtract osec->vma
10173 from the emitted reloc addend. */
10dbd1f3 10174 if (sym_sec)
74541ad4 10175 osec = sym_sec->output_section;
10dbd1f3 10176 else
74541ad4
AM		 10177 osec = input_section->output_section;
10178 symbol = elf_section_data (osec)->dynindx;
10179 if (symbol == 0)
10180 {
10181 struct elf_link_hash_table *htab = elf_hash_table (info);
10182
10183 if ((osec->flags & SEC_READONLY) == 0
10184 && htab->data_index_section != NULL)
10185 osec = htab->data_index_section;
10186 else
10187 osec = htab->text_index_section;
10188 symbol = elf_section_data (osec)->dynindx;
10189 }
6366ff1e
MM		 10190 BFD_ASSERT (symbol != 0);
10191 }
a16385dc
MM		 10192 else
10193 /* On SVR4-ish systems, the dynamic loader cannot
10194 relocate the text and data segments independently,
10195 so the symbol does not matter. */
10196 symbol = 0;
34e77a92
RS		 10197 if (dynreloc_st_type == STT_GNU_IFUNC)
10198 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10199 to the .iplt entry. Instead, every non-call reference
10200 must use an R_ARM_IRELATIVE relocation to obtain the
10201 correct run-time address. */
10202 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
10203 else
10204 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 10205 if (globals->use_rel)
10206 relocate = TRUE;
10207 else
34e77a92 10208 outrel.r_addend += dynreloc_value;
252b5132 10209 }
f21f3fe0 10210
47beaa6a 10211 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 10212
f21f3fe0 10213 /* If this reloc is against an external symbol, we do not want to
252b5132 10214 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 10215 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 10216 if (! relocate)
10217 return bfd_reloc_ok;
9a5aca8c 10218
f21f3fe0 10219 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 10220 contents, rel->r_offset,
10221 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 10222 }
10223 else switch (r_type)
10224 {
00a97672
RS		 10225 case R_ARM_ABS12:
10226 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10227
dfc5f959 10228 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 10229 case R_ARM_CALL:
10230 case R_ARM_JUMP24:
8029a119 10231 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 10232 case R_ARM_PLT32:
906e58ca 10233 {
906e58ca
NC		 10234 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10235
dfc5f959 10236 if (r_type == R_ARM_XPC25)
252b5132 10237 {
dfc5f959
NC		 10238 /* Check for Arm calling Arm function. */
10239 /* FIXME: Should we translate the instruction into a BL
10240 instruction instead ? */
35fc36a8 10241 if (branch_type != ST_BRANCH_TO_THUMB)
4eca0228 10242 _bfd_error_handler
90b6238f
AM		 10243 (_("\%pB: warning: %s BLX instruction targets"
10244 " %s function '%s'"),
10245 input_bfd, "ARM",
10246 "ARM", h ? h->root.root.string : "(local)");
dfc5f959 10247 }
155d87d7 10248 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 10249 {
10250 /* Check for Arm calling Thumb function. */
35fc36a8 10251 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 10252 {
f2a9dd69
DJ		 10253 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10254 output_bfd, input_section,
10255 hit_data, sym_sec, rel->r_offset,
10256 signed_addend, value,
10257 error_message))
10258 return bfd_reloc_ok;
10259 else
10260 return bfd_reloc_dangerous;
dfc5f959 10261 }
252b5132 10262 }
ba96a88f 10263
906e58ca 10264 /* Check if a stub has to be inserted because the
8029a119 10265 destination is too far or we are changing mode. */
155d87d7
CL		 10266 if ( r_type == R_ARM_CALL
10267 || r_type == R_ARM_JUMP24
10268 || r_type == R_ARM_PLT32)
906e58ca 10269 {
fe33d2fa
CL		 10270 enum elf32_arm_stub_type stub_type = arm_stub_none;
10271 struct elf32_arm_link_hash_entry *hash;
10272
10273 hash = (struct elf32_arm_link_hash_entry *) h;
10274 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10275 st_type, &branch_type,
10276 hash, value, sym_sec,
fe33d2fa 10277 input_bfd, sym_name);
5fa9e92f 10278
fe33d2fa 10279 if (stub_type != arm_stub_none)
906e58ca
NC		 10280 {
10281 /* The target is out of reach, so redirect the
10282 branch to the local stub for this function. */
906e58ca
NC		 10283 stub_entry = elf32_arm_get_stub_entry (input_section,
10284 sym_sec, h,
fe33d2fa
CL		 10285 rel, globals,
10286 stub_type);
9cd3e4e5
NC		 10287 {
10288 if (stub_entry != NULL)
10289 value = (stub_entry->stub_offset
10290 + stub_entry->stub_sec->output_offset
10291 + stub_entry->stub_sec->output_section->vma);
10292
10293 if (plt_offset != (bfd_vma) -1)
10294 *unresolved_reloc_p = FALSE;
10295 }
906e58ca 10296 }
fe33d2fa
CL		 10297 else
10298 {
10299 /* If the call goes through a PLT entry, make sure to
10300 check distance to the right destination address. */
34e77a92 10301 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10302 {
10303 value = (splt->output_section->vma
10304 + splt->output_offset
34e77a92 10305 + plt_offset);
fe33d2fa
CL		 10306 *unresolved_reloc_p = FALSE;
10307 /* The PLT entry is in ARM mode, regardless of the
10308 target function. */
35fc36a8 10309 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10310 }
10311 }
906e58ca
NC		 10312 }
10313
dea514f5
PB		 10314 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10315 where:
10316 S is the address of the symbol in the relocation.
10317 P is address of the instruction being relocated.
10318 A is the addend (extracted from the instruction) in bytes.
10319
10320 S is held in 'value'.
10321 P is the base address of the section containing the
10322 instruction plus the offset of the reloc into that
10323 section, ie:
10324 (input_section->output_section->vma +
10325 input_section->output_offset +
10326 rel->r_offset).
10327 A is the addend, converted into bytes, ie:
10328 (signed_addend * 4)
10329
10330 Note: None of these operations have knowledge of the pipeline
10331 size of the processor, thus it is up to the assembler to
10332 encode this information into the addend. */
10333 value -= (input_section->output_section->vma
10334 + input_section->output_offset);
10335 value -= rel->r_offset;
4e7fd91e
PB		 10336 if (globals->use_rel)
10337 value += (signed_addend << howto->size);
10338 else
10339 /* RELA addends do not have to be adjusted by howto->size. */
10340 value += signed_addend;
23080146 10341
dcb5e6e6
NC		 10342 signed_addend = value;
10343 signed_addend >>= howto->rightshift;
9a5aca8c 10344
5ab79981 10345 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 10346 the next instruction unless a PLT entry will be created.
77b4f08f 10347 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 10348 The jump to the next instruction is optimized as a NOP depending
10349 on the architecture. */
ffcb4889 10350 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 10351 && plt_offset == (bfd_vma) -1)
77b4f08f 10352 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 10353 {
cd1dac3d
DG		 10354 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10355
10356 if (arch_has_arm_nop (globals))
10357 value |= 0x0320f000;
10358 else
10359 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 10360 }
10361 else
59f2c4e7 10362 {
9b485d32 10363 /* Perform a signed range check. */
dcb5e6e6 10364 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 10365 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10366 return bfd_reloc_overflow;
9a5aca8c 10367
5ab79981 10368 addend = (value & 2);
39b41c9c 10369
5ab79981
PB		 10370 value = (signed_addend & howto->dst_mask)
10371 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 10372
5ab79981
PB		 10373 if (r_type == R_ARM_CALL)
10374 {
155d87d7 10375 /* Set the H bit in the BLX instruction. */
35fc36a8 10376 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 10377 {
10378 if (addend)
10379 value |= (1 << 24);
10380 else
10381 value &= ~(bfd_vma)(1 << 24);
10382 }
10383
5ab79981 10384 /* Select the correct instruction (BL or BLX). */
906e58ca 10385 /* Only if we are not handling a BL to a stub. In this
8029a119 10386 case, mode switching is performed by the stub. */
35fc36a8 10387 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 10388 value |= (1 << 28);
63e1a0fc 10389 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 10390 {
10391 value &= ~(bfd_vma)(1 << 28);
10392 value |= (1 << 24);
10393 }
39b41c9c
PB		 10394 }
10395 }
906e58ca 10396 }
252b5132 10397 break;
f21f3fe0 10398
252b5132
RH		 10399 case R_ARM_ABS32:
10400 value += addend;
35fc36a8 10401 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 10402 value |= 1;
10403 break;
f21f3fe0 10404
bb224fc3
MS		 10405 case R_ARM_ABS32_NOI:
10406 value += addend;
10407 break;
10408
252b5132 10409 case R_ARM_REL32:
a8bc6c78 10410 value += addend;
35fc36a8 10411 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 10412 value |= 1;
252b5132 10413 value -= (input_section->output_section->vma
62efb346 10414 + input_section->output_offset + rel->r_offset);
252b5132 10415 break;
eb043451 10416
bb224fc3
MS		 10417 case R_ARM_REL32_NOI:
10418 value += addend;
10419 value -= (input_section->output_section->vma
10420 + input_section->output_offset + rel->r_offset);
10421 break;
10422
eb043451
PB		 10423 case R_ARM_PREL31:
10424 value -= (input_section->output_section->vma
10425 + input_section->output_offset + rel->r_offset);
10426 value += signed_addend;
10427 if (! h || h->root.type != bfd_link_hash_undefweak)
10428 {
8029a119 10429 /* Check for overflow. */
eb043451
PB		 10430 if ((value ^ (value >> 1)) & (1 << 30))
10431 return bfd_reloc_overflow;
10432 }
10433 value &= 0x7fffffff;
10434 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 10435 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 10436 value |= 1;
10437 break;
252b5132 10438 }
f21f3fe0 10439
252b5132
RH		 10440 bfd_put_32 (input_bfd, value, hit_data);
10441 return bfd_reloc_ok;
10442
10443 case R_ARM_ABS8:
fd0fd00c
MJ		 10444 /* PR 16202: Refectch the addend using the correct size. */
10445 if (globals->use_rel)
10446 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 10447 value += addend;
4e67d4ca
DG		 10448
10449 /* There is no way to tell whether the user intended to use a signed or
10450 unsigned addend. When checking for overflow we accept either,
10451 as specified by the AAELF. */
10452 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 10453 return bfd_reloc_overflow;
10454
10455 bfd_put_8 (input_bfd, value, hit_data);
10456 return bfd_reloc_ok;
10457
10458 case R_ARM_ABS16:
fd0fd00c
MJ		 10459 /* PR 16202: Refectch the addend using the correct size. */
10460 if (globals->use_rel)
10461 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 10462 value += addend;
10463
4e67d4ca
DG		 10464 /* See comment for R_ARM_ABS8. */
10465 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 10466 return bfd_reloc_overflow;
10467
10468 bfd_put_16 (input_bfd, value, hit_data);
10469 return bfd_reloc_ok;
10470
252b5132 10471 case R_ARM_THM_ABS5:
9b485d32 10472 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 10473 if (globals->use_rel)
10474 {
10475 /* Need to refetch addend. */
10476 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10477 /* ??? Need to determine shift amount from operand size. */
10478 addend >>= howto->rightshift;
10479 }
252b5132
RH		 10480 value += addend;
10481
10482 /* ??? Isn't value unsigned? */
10483 if ((long) value > 0x1f || (long) value < -0x10)
10484 return bfd_reloc_overflow;
10485
10486 /* ??? Value needs to be properly shifted into place first. */
10487 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10488 bfd_put_16 (input_bfd, value, hit_data);
10489 return bfd_reloc_ok;
10490
2cab6cc3
MS		 10491 case R_ARM_THM_ALU_PREL_11_0:
10492 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10493 {
10494 bfd_vma insn;
10495 bfd_signed_vma relocation;
10496
10497 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10498 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10499
99059e56
RM		 10500 if (globals->use_rel)
10501 {
10502 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10503 | ((insn & (1 << 26)) >> 15);
10504 if (insn & 0xf00000)
10505 signed_addend = -signed_addend;
10506 }
2cab6cc3
MS		 10507
10508 relocation = value + signed_addend;
79f08007 10509 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10510 + input_section->output_offset
10511 + rel->r_offset);
2cab6cc3 10512
8c65b54f
CS		 10513 /* PR 21523: Use an absolute value. The user of this reloc will
10514 have already selected an ADD or SUB insn appropriately. */
e652757b 10515 value = labs (relocation);
2cab6cc3 10516
99059e56
RM		 10517 if (value >= 0x1000)
10518 return bfd_reloc_overflow;
2cab6cc3 10519
e645cf40
AG		 10520 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10521 if (branch_type == ST_BRANCH_TO_THUMB)
10522 value |= 1;
10523
2cab6cc3 10524 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 10525 | ((value & 0x700) << 4)
10526 | ((value & 0x800) << 15);
10527 if (relocation < 0)
10528 insn |= 0xa00000;
2cab6cc3
MS		 10529
10530 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10531 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10532
99059e56 10533 return bfd_reloc_ok;
2cab6cc3
MS		 10534 }
10535
e1ec24c6
NC		 10536 case R_ARM_THM_PC8:
10537 /* PR 10073: This reloc is not generated by the GNU toolchain,
10538 but it is supported for compatibility with third party libraries
10539 generated by other compilers, specifically the ARM/IAR. */
10540 {
10541 bfd_vma insn;
10542 bfd_signed_vma relocation;
10543
10544 insn = bfd_get_16 (input_bfd, hit_data);
10545
99059e56 10546 if (globals->use_rel)
79f08007 10547 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 10548
10549 relocation = value + addend;
79f08007 10550 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10551 + input_section->output_offset
10552 + rel->r_offset);
e1ec24c6 10553
b6518b38 10554 value = relocation;
e1ec24c6
NC		 10555
10556 /* We do not check for overflow of this reloc. Although strictly
10557 speaking this is incorrect, it appears to be necessary in order
10558 to work with IAR generated relocs. Since GCC and GAS do not
10559 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10560 a problem for them. */
10561 value &= 0x3fc;
10562
10563 insn = (insn & 0xff00) | (value >> 2);
10564
10565 bfd_put_16 (input_bfd, insn, hit_data);
10566
99059e56 10567 return bfd_reloc_ok;
e1ec24c6
NC		 10568 }
10569
2cab6cc3
MS		 10570 case R_ARM_THM_PC12:
10571 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10572 {
10573 bfd_vma insn;
10574 bfd_signed_vma relocation;
10575
10576 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 10577 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 10578
99059e56
RM		 10579 if (globals->use_rel)
10580 {
10581 signed_addend = insn & 0xfff;
10582 if (!(insn & (1 << 23)))
10583 signed_addend = -signed_addend;
10584 }
2cab6cc3
MS		 10585
10586 relocation = value + signed_addend;
79f08007 10587 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 10588 + input_section->output_offset
10589 + rel->r_offset);
2cab6cc3 10590
b6518b38 10591 value = relocation;
2cab6cc3 10592
99059e56
RM		 10593 if (value >= 0x1000)
10594 return bfd_reloc_overflow;
2cab6cc3
MS		 10595
10596 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 10597 if (relocation >= 0)
10598 insn |= (1 << 23);
2cab6cc3
MS		 10599
10600 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10601 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10602
99059e56 10603 return bfd_reloc_ok;
2cab6cc3
MS		 10604 }
10605
dfc5f959 10606 case R_ARM_THM_XPC22:
c19d1205 10607 case R_ARM_THM_CALL:
bd97cb95 10608 case R_ARM_THM_JUMP24:
dfc5f959 10609 /* Thumb BL (branch long instruction). */
252b5132 10610 {
b34976b6 10611 bfd_vma relocation;
99059e56 10612 bfd_vma reloc_sign;
b34976b6
AM		 10613 bfd_boolean overflow = FALSE;
10614 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10615 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 10616 bfd_signed_vma reloc_signed_max;
10617 bfd_signed_vma reloc_signed_min;
b34976b6 10618 bfd_vma check;
252b5132 10619 bfd_signed_vma signed_check;
e95de063 10620 int bitsize;
cd1dac3d 10621 const int thumb2 = using_thumb2 (globals);
5e866f5a 10622 const int thumb2_bl = using_thumb2_bl (globals);
252b5132 10623
5ab79981 10624 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 10625 the next instruction unless a PLT entry will be created.
10626 The jump to the next instruction is optimized as a NOP.W for
10627 Thumb-2 enabled architectures. */
19540007 10628 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 10629 && plt_offset == (bfd_vma) -1)
5ab79981 10630 {
60a019a0 10631 if (thumb2)
cd1dac3d
DG		 10632 {
10633 bfd_put_16 (input_bfd, 0xf3af, hit_data);
10634 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
10635 }
10636 else
10637 {
10638 bfd_put_16 (input_bfd, 0xe000, hit_data);
10639 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
10640 }
5ab79981
PB		 10641 return bfd_reloc_ok;
10642 }
10643
e95de063 10644 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 10645 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 10646 if (globals->use_rel)
10647 {
99059e56
RM		 10648 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
10649 bfd_vma upper = upper_insn & 0x3ff;
10650 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 10651 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
10652 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 10653 bfd_vma i1 = j1 ^ s ? 0 : 1;
10654 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 10655
99059e56
RM		 10656 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
10657 /* Sign extend. */
10658 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 10659
4e7fd91e
PB		 10660 signed_addend = addend;
10661 }
cb1afa5c 10662
dfc5f959
NC		 10663 if (r_type == R_ARM_THM_XPC22)
10664 {
10665 /* Check for Thumb to Thumb call. */
10666 /* FIXME: Should we translate the instruction into a BL
10667 instruction instead ? */
35fc36a8 10668 if (branch_type == ST_BRANCH_TO_THUMB)
4eca0228 10669 _bfd_error_handler
90b6238f
AM		 10670 (_("%pB: warning: %s BLX instruction targets"
10671 " %s function '%s'"),
10672 input_bfd, "Thumb",
10673 "Thumb", h ? h->root.root.string : "(local)");
dfc5f959
NC		 10674 }
10675 else
252b5132 10676 {
dfc5f959
NC		 10677 /* If it is not a call to Thumb, assume call to Arm.
10678 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 10679 function call at all, but rather a long jump. Calls through
10680 the PLT do not require stubs. */
34e77a92 10681 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 10682 {
bd97cb95 10683 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10684 {
10685 /* Convert BL to BLX. */
10686 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10687 }
155d87d7
CL		 10688 else if (( r_type != R_ARM_THM_CALL)
10689 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 10690 {
10691 if (elf32_thumb_to_arm_stub
10692 (info, sym_name, input_bfd, output_bfd, input_section,
10693 hit_data, sym_sec, rel->r_offset, signed_addend, value,
10694 error_message))
10695 return bfd_reloc_ok;
10696 else
10697 return bfd_reloc_dangerous;
10698 }
da5938a2 10699 }
35fc36a8
RS		 10700 else if (branch_type == ST_BRANCH_TO_THUMB
10701 && globals->use_blx
bd97cb95 10702 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 10703 {
10704 /* Make sure this is a BL. */
10705 lower_insn |= 0x1800;
10706 }
252b5132 10707 }
f21f3fe0 10708
fe33d2fa 10709 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 10710 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 10711 {
10712 /* Check if a stub has to be inserted because the destination
8029a119 10713 is too far. */
fe33d2fa
CL		 10714 struct elf32_arm_stub_hash_entry *stub_entry;
10715 struct elf32_arm_link_hash_entry *hash;
10716
10717 hash = (struct elf32_arm_link_hash_entry *) h;
10718
10719 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 10720 st_type, &branch_type,
10721 hash, value, sym_sec,
fe33d2fa
CL		 10722 input_bfd, sym_name);
10723
10724 if (stub_type != arm_stub_none)
906e58ca
NC		 10725 {
10726 /* The target is out of reach or we are changing modes, so
10727 redirect the branch to the local stub for this
10728 function. */
10729 stub_entry = elf32_arm_get_stub_entry (input_section,
10730 sym_sec, h,
fe33d2fa
CL		 10731 rel, globals,
10732 stub_type);
906e58ca 10733 if (stub_entry != NULL)
9cd3e4e5
NC		 10734 {
10735 value = (stub_entry->stub_offset
10736 + stub_entry->stub_sec->output_offset
10737 + stub_entry->stub_sec->output_section->vma);
10738
10739 if (plt_offset != (bfd_vma) -1)
10740 *unresolved_reloc_p = FALSE;
10741 }
906e58ca 10742
f4ac8484 10743 /* If this call becomes a call to Arm, force BLX. */
155d87d7 10744 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 10745 {
10746 if ((stub_entry
10747 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 10748 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 10749 lower_insn = (lower_insn & ~0x1000) | 0x0800;
10750 }
906e58ca
NC		 10751 }
10752 }
10753
fe33d2fa 10754 /* Handle calls via the PLT. */
34e77a92 10755 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 10756 {
10757 value = (splt->output_section->vma
10758 + splt->output_offset
34e77a92 10759 + plt_offset);
fe33d2fa 10760
eed94f8f
NC		 10761 if (globals->use_blx
10762 && r_type == R_ARM_THM_CALL
10763 && ! using_thumb_only (globals))
fe33d2fa
CL		 10764 {
10765 /* If the Thumb BLX instruction is available, convert
10766 the BL to a BLX instruction to call the ARM-mode
10767 PLT entry. */
10768 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 10769 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 10770 }
10771 else
10772 {
eed94f8f
NC		 10773 if (! using_thumb_only (globals))
10774 /* Target the Thumb stub before the ARM PLT entry. */
10775 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 10776 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 10777 }
10778 *unresolved_reloc_p = FALSE;
10779 }
10780
ba96a88f 10781 relocation = value + signed_addend;
f21f3fe0 10782
252b5132 10783 relocation -= (input_section->output_section->vma
ba96a88f
NC		 10784 + input_section->output_offset
10785 + rel->r_offset);
9a5aca8c 10786
252b5132
RH		 10787 check = relocation >> howto->rightshift;
10788
10789 /* If this is a signed value, the rightshift just dropped
10790 leading 1 bits (assuming twos complement). */
10791 if ((bfd_signed_vma) relocation >= 0)
10792 signed_check = check;
10793 else
10794 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
10795
e95de063
MS		 10796 /* Calculate the permissable maximum and minimum values for
10797 this relocation according to whether we're relocating for
10798 Thumb-2 or not. */
10799 bitsize = howto->bitsize;
5e866f5a 10800 if (!thumb2_bl)
e95de063 10801 bitsize -= 2;
f6ebfac0 10802 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 10803 reloc_signed_min = ~reloc_signed_max;
10804
252b5132 10805 /* Assumes two's complement. */
ba96a88f 10806 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 10807 overflow = TRUE;
252b5132 10808
bd97cb95 10809 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 10810 /* For a BLX instruction, make sure that the relocation is rounded up
10811 to a word boundary. This follows the semantics of the instruction
10812 which specifies that bit 1 of the target address will come from bit
10813 1 of the base address. */
10814 relocation = (relocation + 2) & ~ 3;
cb1afa5c 10815
e95de063
MS		 10816 /* Put RELOCATION back into the insn. Assumes two's complement.
10817 We use the Thumb-2 encoding, which is safe even if dealing with
10818 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 10819 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 10820 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 10821 | ((relocation >> 12) & 0x3ff)
10822 | (reloc_sign << 10);
906e58ca 10823 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 10824 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
10825 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
10826 | ((relocation >> 1) & 0x7ff);
c62e1cc3 10827
252b5132
RH		 10828 /* Put the relocated value back in the object file: */
10829 bfd_put_16 (input_bfd, upper_insn, hit_data);
10830 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10831
10832 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10833 }
10834 break;
10835
c19d1205
ZW		 10836 case R_ARM_THM_JUMP19:
10837 /* Thumb32 conditional branch instruction. */
10838 {
10839 bfd_vma relocation;
10840 bfd_boolean overflow = FALSE;
10841 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10842 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 10843 bfd_signed_vma reloc_signed_max = 0xffffe;
10844 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 10845 bfd_signed_vma signed_check;
07d6d2b8 10846 enum elf32_arm_stub_type stub_type = arm_stub_none;
c5423981
TG		 10847 struct elf32_arm_stub_hash_entry *stub_entry;
10848 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 10849
10850 /* Need to refetch the addend, reconstruct the top three bits,
10851 and squish the two 11 bit pieces together. */
10852 if (globals->use_rel)
10853 {
10854 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 10855 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 10856 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
10857 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
10858 bfd_vma lower = (lower_insn & 0x07ff);
10859
a00a1f35
MS		 10860 upper |= J1 << 6;
10861 upper |= J2 << 7;
10862 upper |= (!S) << 8;
c19d1205
ZW		 10863 upper -= 0x0100; /* Sign extend. */
10864
10865 addend = (upper << 12) | (lower << 1);
10866 signed_addend = addend;
10867 }
10868
bd97cb95 10869 /* Handle calls via the PLT. */
34e77a92 10870 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 10871 {
10872 value = (splt->output_section->vma
10873 + splt->output_offset
34e77a92 10874 + plt_offset);
bd97cb95
DJ		 10875 /* Target the Thumb stub before the ARM PLT entry. */
10876 value -= PLT_THUMB_STUB_SIZE;
10877 *unresolved_reloc_p = FALSE;
10878 }
10879
c5423981
TG		 10880 hash = (struct elf32_arm_link_hash_entry *)h;
10881
10882 stub_type = arm_type_of_stub (info, input_section, rel,
07d6d2b8
AM		 10883 st_type, &branch_type,
10884 hash, value, sym_sec,
10885 input_bfd, sym_name);
c5423981
TG		 10886 if (stub_type != arm_stub_none)
10887 {
10888 stub_entry = elf32_arm_get_stub_entry (input_section,
07d6d2b8
AM		 10889 sym_sec, h,
10890 rel, globals,
10891 stub_type);
c5423981
TG		 10892 if (stub_entry != NULL)
10893 {
07d6d2b8
AM		 10894 value = (stub_entry->stub_offset
10895 + stub_entry->stub_sec->output_offset
10896 + stub_entry->stub_sec->output_section->vma);
c5423981
TG		 10897 }
10898 }
c19d1205 10899
99059e56 10900 relocation = value + signed_addend;
c19d1205
ZW		 10901 relocation -= (input_section->output_section->vma
10902 + input_section->output_offset
10903 + rel->r_offset);
a00a1f35 10904 signed_check = (bfd_signed_vma) relocation;
c19d1205 10905
c19d1205
ZW		 10906 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10907 overflow = TRUE;
10908
10909 /* Put RELOCATION back into the insn. */
10910 {
10911 bfd_vma S = (relocation & 0x00100000) >> 20;
10912 bfd_vma J2 = (relocation & 0x00080000) >> 19;
10913 bfd_vma J1 = (relocation & 0x00040000) >> 18;
10914 bfd_vma hi = (relocation & 0x0003f000) >> 12;
10915 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
10916
a00a1f35 10917 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 10918 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
10919 }
10920
10921 /* Put the relocated value back in the object file: */
10922 bfd_put_16 (input_bfd, upper_insn, hit_data);
10923 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10924
10925 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10926 }
10927
10928 case R_ARM_THM_JUMP11:
10929 case R_ARM_THM_JUMP8:
10930 case R_ARM_THM_JUMP6:
51c5503b
NC		 10931 /* Thumb B (branch) instruction). */
10932 {
6cf9e9fe 10933 bfd_signed_vma relocation;
51c5503b
NC		 10934 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
10935 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 10936 bfd_signed_vma signed_check;
10937
c19d1205
ZW		 10938 /* CZB cannot jump backward. */
10939 if (r_type == R_ARM_THM_JUMP6)
10940 reloc_signed_min = 0;
10941
4e7fd91e 10942 if (globals->use_rel)
6cf9e9fe 10943 {
4e7fd91e
PB		 10944 /* Need to refetch addend. */
10945 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10946 if (addend & ((howto->src_mask + 1) >> 1))
10947 {
10948 signed_addend = -1;
10949 signed_addend &= ~ howto->src_mask;
10950 signed_addend |= addend;
10951 }
10952 else
10953 signed_addend = addend;
10954 /* The value in the insn has been right shifted. We need to
10955 undo this, so that we can perform the address calculation
10956 in terms of bytes. */
10957 signed_addend <<= howto->rightshift;
6cf9e9fe 10958 }
6cf9e9fe 10959 relocation = value + signed_addend;
51c5503b
NC		 10960
10961 relocation -= (input_section->output_section->vma
10962 + input_section->output_offset
10963 + rel->r_offset);
10964
6cf9e9fe
NC		 10965 relocation >>= howto->rightshift;
10966 signed_check = relocation;
c19d1205
ZW		 10967
10968 if (r_type == R_ARM_THM_JUMP6)
10969 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
10970 else
10971 relocation &= howto->dst_mask;
51c5503b 10972 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 10973
51c5503b
NC		 10974 bfd_put_16 (input_bfd, relocation, hit_data);
10975
10976 /* Assumes two's complement. */
10977 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10978 return bfd_reloc_overflow;
10979
10980 return bfd_reloc_ok;
10981 }
cedb70c5 10982
8375c36b
PB		 10983 case R_ARM_ALU_PCREL7_0:
10984 case R_ARM_ALU_PCREL15_8:
10985 case R_ARM_ALU_PCREL23_15:
10986 {
10987 bfd_vma insn;
10988 bfd_vma relocation;
10989
10990 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 10991 if (globals->use_rel)
10992 {
10993 /* Extract the addend. */
10994 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
10995 signed_addend = addend;
10996 }
8375c36b
PB		 10997 relocation = value + signed_addend;
10998
10999 relocation -= (input_section->output_section->vma
11000 + input_section->output_offset
11001 + rel->r_offset);
11002 insn = (insn & ~0xfff)
11003 | ((howto->bitpos << 7) & 0xf00)
11004 | ((relocation >> howto->bitpos) & 0xff);
11005 bfd_put_32 (input_bfd, value, hit_data);
11006 }
11007 return bfd_reloc_ok;
11008
252b5132
RH		 11009 case R_ARM_GNU_VTINHERIT:
11010 case R_ARM_GNU_VTENTRY:
11011 return bfd_reloc_ok;
11012
c19d1205 11013 case R_ARM_GOTOFF32:
252b5132 11014 /* Relocation is relative to the start of the
99059e56 11015 global offset table. */
252b5132
RH		 11016
11017 BFD_ASSERT (sgot != NULL);
11018 if (sgot == NULL)
99059e56 11019 return bfd_reloc_notsupported;
9a5aca8c 11020
cedb70c5 11021 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 11022 address by one, so that attempts to call the function pointer will
11023 correctly interpret it as Thumb code. */
35fc36a8 11024 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 11025 value += 1;
11026
252b5132 11027 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 11028 calculation. We always want the start of .got. If we
11029 define _GLOBAL_OFFSET_TABLE in a different way, as is
11030 permitted by the ABI, we might have to change this
11031 calculation. */
252b5132 11032 value -= sgot->output_section->vma;
f21f3fe0 11033 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11034 contents, rel->r_offset, value,
00a97672 11035 rel->r_addend);
252b5132
RH		 11036
11037 case R_ARM_GOTPC:
a7c10850 11038 /* Use global offset table as symbol value. */
252b5132 11039 BFD_ASSERT (sgot != NULL);
f21f3fe0 11040
252b5132 11041 if (sgot == NULL)
99059e56 11042 return bfd_reloc_notsupported;
252b5132 11043
0945cdfd 11044 *unresolved_reloc_p = FALSE;
252b5132 11045 value = sgot->output_section->vma;
f21f3fe0 11046 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11047 contents, rel->r_offset, value,
00a97672 11048 rel->r_addend);
f21f3fe0 11049
252b5132 11050 case R_ARM_GOT32:
eb043451 11051 case R_ARM_GOT_PREL:
252b5132 11052 /* Relocation is to the entry for this symbol in the
99059e56 11053 global offset table. */
252b5132
RH		 11054 if (sgot == NULL)
11055 return bfd_reloc_notsupported;
f21f3fe0 11056
34e77a92
RS		 11057 if (dynreloc_st_type == STT_GNU_IFUNC
11058 && plt_offset != (bfd_vma) -1
11059 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11060 {
11061 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11062 symbol, and the relocation resolves directly to the runtime
11063 target rather than to the .iplt entry. This means that any
11064 .got entry would be the same value as the .igot.plt entry,
11065 so there's no point creating both. */
11066 sgot = globals->root.igotplt;
11067 value = sgot->output_offset + gotplt_offset;
11068 }
11069 else if (h != NULL)
252b5132
RH		 11070 {
11071 bfd_vma off;
f21f3fe0 11072
252b5132
RH		 11073 off = h->got.offset;
11074 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 11075 if ((off & 1) != 0)
252b5132 11076 {
b436d854
RS		 11077 /* We have already processsed one GOT relocation against
11078 this symbol. */
11079 off &= ~1;
11080 if (globals->root.dynamic_sections_created
11081 && !SYMBOL_REFERENCES_LOCAL (info, h))
11082 *unresolved_reloc_p = FALSE;
11083 }
11084 else
11085 {
11086 Elf_Internal_Rela outrel;
11087
6f820c85 11088 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 11089 {
11090 /* If the symbol doesn't resolve locally in a static
11091 object, we have an undefined reference. If the
11092 symbol doesn't resolve locally in a dynamic object,
11093 it should be resolved by the dynamic linker. */
11094 if (globals->root.dynamic_sections_created)
11095 {
11096 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11097 *unresolved_reloc_p = FALSE;
11098 }
11099 else
11100 outrel.r_info = 0;
11101 outrel.r_addend = 0;
11102 }
252b5132
RH		 11103 else
11104 {
34e77a92 11105 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11106 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
5025eb7c
AO		 11107 else if (bfd_link_pic (info)
11108 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11109 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 11110 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11111 else
11112 outrel.r_info = 0;
34e77a92 11113 outrel.r_addend = dynreloc_value;
b436d854 11114 }
ee29b9fb 11115
b436d854
RS		 11116 /* The GOT entry is initialized to zero by default.
11117 See if we should install a different value. */
11118 if (outrel.r_addend != 0
11119 && (outrel.r_info == 0 || globals->use_rel))
11120 {
11121 bfd_put_32 (output_bfd, outrel.r_addend,
11122 sgot->contents + off);
11123 outrel.r_addend = 0;
252b5132 11124 }
f21f3fe0 11125
b436d854
RS		 11126 if (outrel.r_info != 0)
11127 {
11128 outrel.r_offset = (sgot->output_section->vma
11129 + sgot->output_offset
11130 + off);
11131 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11132 }
11133 h->got.offset |= 1;
11134 }
252b5132
RH		 11135 value = sgot->output_offset + off;
11136 }
11137 else
11138 {
11139 bfd_vma off;
f21f3fe0 11140
5025eb7c
AO		 11141 BFD_ASSERT (local_got_offsets != NULL
11142 && local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 11143
252b5132 11144 off = local_got_offsets[r_symndx];
f21f3fe0 11145
252b5132
RH		 11146 /* The offset must always be a multiple of 4. We use the
11147 least significant bit to record whether we have already
9b485d32 11148 generated the necessary reloc. */
252b5132
RH		 11149 if ((off & 1) != 0)
11150 off &= ~1;
11151 else
11152 {
00a97672 11153 if (globals->use_rel)
34e77a92 11154 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 11155
0e1862bb 11156 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 11157 {
947216bf 11158 Elf_Internal_Rela outrel;
f21f3fe0 11159
34e77a92 11160 outrel.r_addend = addend + dynreloc_value;
252b5132 11161 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 11162 + sgot->output_offset
252b5132 11163 + off);
34e77a92 11164 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 11165 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 11166 else
11167 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 11168 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 11169 }
f21f3fe0 11170
252b5132
RH		 11171 local_got_offsets[r_symndx] |= 1;
11172 }
f21f3fe0 11173
252b5132
RH		 11174 value = sgot->output_offset + off;
11175 }
eb043451
PB		 11176 if (r_type != R_ARM_GOT32)
11177 value += sgot->output_section->vma;
9a5aca8c 11178
f21f3fe0 11179 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 11180 contents, rel->r_offset, value,
00a97672 11181 rel->r_addend);
f21f3fe0 11182
ba93b8ac
DJ		 11183 case R_ARM_TLS_LDO32:
11184 value = value - dtpoff_base (info);
11185
11186 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11187 contents, rel->r_offset, value,
11188 rel->r_addend);
ba93b8ac
DJ		 11189
11190 case R_ARM_TLS_LDM32:
11191 {
11192 bfd_vma off;
11193
362d30a1 11194 if (sgot == NULL)
ba93b8ac
DJ		 11195 abort ();
11196
11197 off = globals->tls_ldm_got.offset;
11198
11199 if ((off & 1) != 0)
11200 off &= ~1;
11201 else
11202 {
11203 /* If we don't know the module number, create a relocation
11204 for it. */
0e1862bb 11205 if (bfd_link_pic (info))
ba93b8ac
DJ		 11206 {
11207 Elf_Internal_Rela outrel;
ba93b8ac 11208
362d30a1 11209 if (srelgot == NULL)
ba93b8ac
DJ		 11210 abort ();
11211
00a97672 11212 outrel.r_addend = 0;
362d30a1
RS		 11213 outrel.r_offset = (sgot->output_section->vma
11214 + sgot->output_offset + off);
ba93b8ac
DJ		 11215 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11216
00a97672
RS		 11217 if (globals->use_rel)
11218 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11219 sgot->contents + off);
ba93b8ac 11220
47beaa6a 11221 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11222 }
11223 else
362d30a1 11224 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 11225
11226 globals->tls_ldm_got.offset |= 1;
11227 }
11228
362d30a1 11229 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 11230 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
11231
11232 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11233 contents, rel->r_offset, value,
00a97672 11234 rel->r_addend);
ba93b8ac
DJ		 11235 }
11236
0855e32b
NS		 11237 case R_ARM_TLS_CALL:
11238 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 11239 case R_ARM_TLS_GD32:
11240 case R_ARM_TLS_IE32:
0855e32b
NS		 11241 case R_ARM_TLS_GOTDESC:
11242 case R_ARM_TLS_DESCSEQ:
11243 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 11244 {
0855e32b
NS		 11245 bfd_vma off, offplt;
11246 int indx = 0;
ba93b8ac
DJ		 11247 char tls_type;
11248
0855e32b 11249 BFD_ASSERT (sgot != NULL);
ba93b8ac 11250
ba93b8ac
DJ		 11251 if (h != NULL)
11252 {
11253 bfd_boolean dyn;
11254 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 11255 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11256 bfd_link_pic (info),
11257 h)
11258 && (!bfd_link_pic (info)
ba93b8ac
DJ		 11259 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11260 {
11261 *unresolved_reloc_p = FALSE;
11262 indx = h->dynindx;
11263 }
11264 off = h->got.offset;
0855e32b 11265 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 11266 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11267 }
11268 else
11269 {
0855e32b 11270 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 11271 off = local_got_offsets[r_symndx];
0855e32b 11272 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 11273 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11274 }
11275
0855e32b 11276 /* Linker relaxations happens from one of the
b38cadfb 11277 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 11278 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 11279 tls_type = GOT_TLS_IE;
0855e32b
NS		 11280
11281 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 11282
11283 if ((off & 1) != 0)
11284 off &= ~1;
11285 else
11286 {
11287 bfd_boolean need_relocs = FALSE;
11288 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 11289 int cur_off = off;
11290
11291 /* The GOT entries have not been initialized yet. Do it
11292 now, and emit any relocations. If both an IE GOT and a
11293 GD GOT are necessary, we emit the GD first. */
11294
0e1862bb 11295 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac 11296 && (h == NULL
95b03e4a
L		 11297 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11298 && !resolved_to_zero)
ba93b8ac
DJ		 11299 || h->root.type != bfd_link_hash_undefweak))
11300 {
11301 need_relocs = TRUE;
0855e32b 11302 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 11303 }
11304
0855e32b
NS		 11305 if (tls_type & GOT_TLS_GDESC)
11306 {
47beaa6a
RS		 11307 bfd_byte *loc;
11308
0855e32b
NS		 11309 /* We should have relaxed, unless this is an undefined
11310 weak symbol. */
11311 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 11312 || bfd_link_pic (info));
0855e32b 11313 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 11314 <= globals->root.sgotplt->size);
0855e32b
NS		 11315
11316 outrel.r_addend = 0;
11317 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11318 + globals->root.sgotplt->output_offset
11319 + offplt
11320 + globals->sgotplt_jump_table_size);
b38cadfb 11321
0855e32b
NS		 11322 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11323 sreloc = globals->root.srelplt;
11324 loc = sreloc->contents;
11325 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11326 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 11327 <= sreloc->contents + sreloc->size);
0855e32b
NS		 11328
11329 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11330
11331 /* For globals, the first word in the relocation gets
11332 the relocation index and the top bit set, or zero,
11333 if we're binding now. For locals, it gets the
11334 symbol's offset in the tls section. */
99059e56 11335 bfd_put_32 (output_bfd,
0855e32b
NS		 11336 !h ? value - elf_hash_table (info)->tls_sec->vma
11337 : info->flags & DF_BIND_NOW ? 0
11338 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 11339 globals->root.sgotplt->contents + offplt
11340 + globals->sgotplt_jump_table_size);
11341
0855e32b 11342 /* Second word in the relocation is always zero. */
99059e56 11343 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 11344 globals->root.sgotplt->contents + offplt
11345 + globals->sgotplt_jump_table_size + 4);
0855e32b 11346 }
ba93b8ac
DJ		 11347 if (tls_type & GOT_TLS_GD)
11348 {
11349 if (need_relocs)
11350 {
00a97672 11351 outrel.r_addend = 0;
362d30a1
RS		 11352 outrel.r_offset = (sgot->output_section->vma
11353 + sgot->output_offset
00a97672 11354 + cur_off);
ba93b8ac 11355 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 11356
00a97672
RS		 11357 if (globals->use_rel)
11358 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11359 sgot->contents + cur_off);
00a97672 11360
47beaa6a 11361 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11362
11363 if (indx == 0)
11364 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11365 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11366 else
11367 {
00a97672 11368 outrel.r_addend = 0;
ba93b8ac
DJ		 11369 outrel.r_info = ELF32_R_INFO (indx,
11370 R_ARM_TLS_DTPOFF32);
11371 outrel.r_offset += 4;
00a97672
RS		 11372
11373 if (globals->use_rel)
11374 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11375 sgot->contents + cur_off + 4);
00a97672 11376
47beaa6a
RS		 11377 elf32_arm_add_dynreloc (output_bfd, info,
11378 srelgot, &outrel);
ba93b8ac
DJ		 11379 }
11380 }
11381 else
11382 {
11383 /* If we are not emitting relocations for a
11384 general dynamic reference, then we must be in a
11385 static link or an executable link with the
11386 symbol binding locally. Mark it as belonging
11387 to module 1, the executable. */
11388 bfd_put_32 (output_bfd, 1,
362d30a1 11389 sgot->contents + cur_off);
ba93b8ac 11390 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 11391 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 11392 }
11393
11394 cur_off += 8;
11395 }
11396
11397 if (tls_type & GOT_TLS_IE)
11398 {
11399 if (need_relocs)
11400 {
00a97672
RS		 11401 if (indx == 0)
11402 outrel.r_addend = value - dtpoff_base (info);
11403 else
11404 outrel.r_addend = 0;
362d30a1
RS		 11405 outrel.r_offset = (sgot->output_section->vma
11406 + sgot->output_offset
ba93b8ac
DJ		 11407 + cur_off);
11408 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11409
00a97672
RS		 11410 if (globals->use_rel)
11411 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 11412 sgot->contents + cur_off);
ba93b8ac 11413
47beaa6a 11414 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 11415 }
11416 else
11417 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 11418 sgot->contents + cur_off);
ba93b8ac
DJ		 11419 cur_off += 4;
11420 }
11421
11422 if (h != NULL)
11423 h->got.offset |= 1;
11424 else
11425 local_got_offsets[r_symndx] |= 1;
11426 }
11427
11428 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
11429 off += 8;
0855e32b
NS		 11430 else if (tls_type & GOT_TLS_GDESC)
11431 off = offplt;
11432
11433 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
11434 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
11435 {
11436 bfd_signed_vma offset;
12352d3f
PB		 11437 /* TLS stubs are arm mode. The original symbol is a
11438 data object, so branch_type is bogus. */
11439 branch_type = ST_BRANCH_TO_ARM;
0855e32b 11440 enum elf32_arm_stub_type stub_type
34e77a92
RS		 11441 = arm_type_of_stub (info, input_section, rel,
11442 st_type, &branch_type,
0855e32b
NS		 11443 (struct elf32_arm_link_hash_entry *)h,
11444 globals->tls_trampoline, globals->root.splt,
11445 input_bfd, sym_name);
11446
11447 if (stub_type != arm_stub_none)
11448 {
11449 struct elf32_arm_stub_hash_entry *stub_entry
11450 = elf32_arm_get_stub_entry
11451 (input_section, globals->root.splt, 0, rel,
11452 globals, stub_type);
11453 offset = (stub_entry->stub_offset
11454 + stub_entry->stub_sec->output_offset
11455 + stub_entry->stub_sec->output_section->vma);
11456 }
11457 else
11458 offset = (globals->root.splt->output_section->vma
11459 + globals->root.splt->output_offset
11460 + globals->tls_trampoline);
11461
11462 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
11463 {
11464 unsigned long inst;
b38cadfb
NC		 11465
11466 offset -= (input_section->output_section->vma
11467 + input_section->output_offset
11468 + rel->r_offset + 8);
0855e32b
NS		 11469
11470 inst = offset >> 2;
11471 inst &= 0x00ffffff;
11472 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11473 }
11474 else
11475 {
11476 /* Thumb blx encodes the offset in a complicated
11477 fashion. */
11478 unsigned upper_insn, lower_insn;
11479 unsigned neg;
11480
b38cadfb
NC		 11481 offset -= (input_section->output_section->vma
11482 + input_section->output_offset
0855e32b 11483 + rel->r_offset + 4);
b38cadfb 11484
12352d3f
PB		 11485 if (stub_type != arm_stub_none
11486 && arm_stub_is_thumb (stub_type))
11487 {
11488 lower_insn = 0xd000;
11489 }
11490 else
11491 {
11492 lower_insn = 0xc000;
6a631e86 11493 /* Round up the offset to a word boundary. */
12352d3f
PB		 11494 offset = (offset + 2) & ~2;
11495 }
11496
0855e32b
NS		 11497 neg = offset < 0;
11498 upper_insn = (0xf000
11499 | ((offset >> 12) & 0x3ff)
11500 | (neg << 10));
12352d3f 11501 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 11502 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 11503 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 11504 bfd_put_16 (input_bfd, upper_insn, hit_data);
11505 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11506 return bfd_reloc_ok;
11507 }
11508 }
11509 /* These relocations needs special care, as besides the fact
11510 they point somewhere in .gotplt, the addend must be
11511 adjusted accordingly depending on the type of instruction
6a631e86 11512 we refer to. */
0855e32b
NS		 11513 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
11514 {
11515 unsigned long data, insn;
11516 unsigned thumb;
b38cadfb 11517
0855e32b
NS		 11518 data = bfd_get_32 (input_bfd, hit_data);
11519 thumb = data & 1;
11520 data &= ~1u;
b38cadfb 11521
0855e32b
NS		 11522 if (thumb)
11523 {
11524 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
11525 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
11526 insn = (insn << 16)
11527 | bfd_get_16 (input_bfd,
11528 contents + rel->r_offset - data + 2);
11529 if ((insn & 0xf800c000) == 0xf000c000)
11530 /* bl/blx */
11531 value = -6;
11532 else if ((insn & 0xffffff00) == 0x4400)
11533 /* add */
11534 value = -5;
11535 else
11536 {
4eca0228 11537 _bfd_error_handler
695344c0 11538 /* xgettext:c-format */
2dcf00ce 11539 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 11540 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 11541 "referenced by TLS_GOTDESC"),
11542 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 11543 "Thumb", insn);
0855e32b
NS		 11544 return bfd_reloc_notsupported;
11545 }
11546 }
11547 else
11548 {
11549 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
11550
11551 switch (insn >> 24)
11552 {
11553 case 0xeb: /* bl */
11554 case 0xfa: /* blx */
11555 value = -4;
11556 break;
11557
11558 case 0xe0: /* add */
11559 value = -8;
11560 break;
b38cadfb 11561
0855e32b 11562 default:
4eca0228 11563 _bfd_error_handler
695344c0 11564 /* xgettext:c-format */
2dcf00ce 11565 (_("%pB(%pA+%#" PRIx64 "): "
90b6238f 11566 "unexpected %s instruction '%#lx' "
2dcf00ce
AM		 11567 "referenced by TLS_GOTDESC"),
11568 input_bfd, input_section, (uint64_t) rel->r_offset,
90b6238f 11569 "ARM", insn);
0855e32b
NS		 11570 return bfd_reloc_notsupported;
11571 }
11572 }
b38cadfb 11573
0855e32b
NS		 11574 value += ((globals->root.sgotplt->output_section->vma
11575 + globals->root.sgotplt->output_offset + off)
11576 - (input_section->output_section->vma
11577 + input_section->output_offset
11578 + rel->r_offset)
11579 + globals->sgotplt_jump_table_size);
11580 }
11581 else
11582 value = ((globals->root.sgot->output_section->vma
11583 + globals->root.sgot->output_offset + off)
11584 - (input_section->output_section->vma
11585 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 11586
11587 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11588 contents, rel->r_offset, value,
00a97672 11589 rel->r_addend);
ba93b8ac
DJ		 11590 }
11591
11592 case R_ARM_TLS_LE32:
3cbc1e5e 11593 if (bfd_link_dll (info))
ba93b8ac 11594 {
4eca0228 11595 _bfd_error_handler
695344c0 11596 /* xgettext:c-format */
2dcf00ce
AM		 11597 (_("%pB(%pA+%#" PRIx64 "): %s relocation not permitted "
11598 "in shared object"),
11599 input_bfd, input_section, (uint64_t) rel->r_offset, howto->name);
46691134 11600 return bfd_reloc_notsupported;
ba93b8ac
DJ		 11601 }
11602 else
11603 value = tpoff (info, value);
906e58ca 11604
ba93b8ac 11605 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 11606 contents, rel->r_offset, value,
11607 rel->r_addend);
ba93b8ac 11608
319850b4
JB		 11609 case R_ARM_V4BX:
11610 if (globals->fix_v4bx)
845b51d6
PB		 11611 {
11612 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 11613
845b51d6
PB		 11614 /* Ensure that we have a BX instruction. */
11615 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 11616
845b51d6
PB		 11617 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
11618 {
11619 /* Branch to veneer. */
11620 bfd_vma glue_addr;
11621 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
11622 glue_addr -= input_section->output_section->vma
11623 + input_section->output_offset
11624 + rel->r_offset + 8;
11625 insn = (insn & 0xf0000000) | 0x0a000000
11626 | ((glue_addr >> 2) & 0x00ffffff);
11627 }
11628 else
11629 {
11630 /* Preserve Rm (lowest four bits) and the condition code
11631 (highest four bits). Other bits encode MOV PC,Rm. */
11632 insn = (insn & 0xf000000f) | 0x01a0f000;
11633 }
319850b4 11634
845b51d6
PB		 11635 bfd_put_32 (input_bfd, insn, hit_data);
11636 }
319850b4
JB		 11637 return bfd_reloc_ok;
11638
b6895b4f
PB		 11639 case R_ARM_MOVW_ABS_NC:
11640 case R_ARM_MOVT_ABS:
11641 case R_ARM_MOVW_PREL_NC:
11642 case R_ARM_MOVT_PREL:
92f5d02b
MS		 11643 /* Until we properly support segment-base-relative addressing then
11644 we assume the segment base to be zero, as for the group relocations.
11645 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
11646 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
11647 case R_ARM_MOVW_BREL_NC:
11648 case R_ARM_MOVW_BREL:
11649 case R_ARM_MOVT_BREL:
b6895b4f
PB		 11650 {
11651 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
11652
11653 if (globals->use_rel)
11654 {
11655 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 11656 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11657 }
92f5d02b 11658
b6895b4f 11659 value += signed_addend;
b6895b4f
PB		 11660
11661 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
11662 value -= (input_section->output_section->vma
11663 + input_section->output_offset + rel->r_offset);
11664
92f5d02b 11665 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 11666 return bfd_reloc_overflow;
92f5d02b 11667
35fc36a8 11668 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11669 value |= 1;
11670
11671 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 11672 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 11673 value >>= 16;
11674
11675 insn &= 0xfff0f000;
11676 insn |= value & 0xfff;
11677 insn |= (value & 0xf000) << 4;
11678 bfd_put_32 (input_bfd, insn, hit_data);
11679 }
11680 return bfd_reloc_ok;
11681
11682 case R_ARM_THM_MOVW_ABS_NC:
11683 case R_ARM_THM_MOVT_ABS:
11684 case R_ARM_THM_MOVW_PREL_NC:
11685 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 11686 /* Until we properly support segment-base-relative addressing then
11687 we assume the segment base to be zero, as for the above relocations.
11688 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
11689 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
11690 as R_ARM_THM_MOVT_ABS. */
11691 case R_ARM_THM_MOVW_BREL_NC:
11692 case R_ARM_THM_MOVW_BREL:
11693 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 11694 {
11695 bfd_vma insn;
906e58ca 11696
b6895b4f
PB		 11697 insn = bfd_get_16 (input_bfd, hit_data) << 16;
11698 insn |= bfd_get_16 (input_bfd, hit_data + 2);
11699
11700 if (globals->use_rel)
11701 {
11702 addend = ((insn >> 4) & 0xf000)
11703 | ((insn >> 15) & 0x0800)
11704 | ((insn >> 4) & 0x0700)
07d6d2b8 11705 | (insn & 0x00ff);
39623e12 11706 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 11707 }
92f5d02b 11708
b6895b4f 11709 value += signed_addend;
b6895b4f
PB		 11710
11711 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
11712 value -= (input_section->output_section->vma
11713 + input_section->output_offset + rel->r_offset);
11714
92f5d02b 11715 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 11716 return bfd_reloc_overflow;
92f5d02b 11717
35fc36a8 11718 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 11719 value |= 1;
11720
11721 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 11722 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 11723 value >>= 16;
11724
11725 insn &= 0xfbf08f00;
11726 insn |= (value & 0xf000) << 4;
11727 insn |= (value & 0x0800) << 15;
11728 insn |= (value & 0x0700) << 4;
11729 insn |= (value & 0x00ff);
11730
11731 bfd_put_16 (input_bfd, insn >> 16, hit_data);
11732 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
11733 }
11734 return bfd_reloc_ok;
11735
4962c51a
MS		 11736 case R_ARM_ALU_PC_G0_NC:
11737 case R_ARM_ALU_PC_G1_NC:
11738 case R_ARM_ALU_PC_G0:
11739 case R_ARM_ALU_PC_G1:
11740 case R_ARM_ALU_PC_G2:
11741 case R_ARM_ALU_SB_G0_NC:
11742 case R_ARM_ALU_SB_G1_NC:
11743 case R_ARM_ALU_SB_G0:
11744 case R_ARM_ALU_SB_G1:
11745 case R_ARM_ALU_SB_G2:
11746 {
11747 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11748 bfd_vma pc = input_section->output_section->vma
4962c51a 11749 + input_section->output_offset + rel->r_offset;
31a91d61 11750 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11751 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 11752 bfd_vma residual;
11753 bfd_vma g_n;
4962c51a 11754 bfd_signed_vma signed_value;
99059e56
RM		 11755 int group = 0;
11756
11757 /* Determine which group of bits to select. */
11758 switch (r_type)
11759 {
11760 case R_ARM_ALU_PC_G0_NC:
11761 case R_ARM_ALU_PC_G0:
11762 case R_ARM_ALU_SB_G0_NC:
11763 case R_ARM_ALU_SB_G0:
11764 group = 0;
11765 break;
11766
11767 case R_ARM_ALU_PC_G1_NC:
11768 case R_ARM_ALU_PC_G1:
11769 case R_ARM_ALU_SB_G1_NC:
11770 case R_ARM_ALU_SB_G1:
11771 group = 1;
11772 break;
11773
11774 case R_ARM_ALU_PC_G2:
11775 case R_ARM_ALU_SB_G2:
11776 group = 2;
11777 break;
11778
11779 default:
11780 abort ();
11781 }
11782
11783 /* If REL, extract the addend from the insn. If RELA, it will
11784 have already been fetched for us. */
4962c51a 11785 if (globals->use_rel)
99059e56
RM		 11786 {
11787 int negative;
11788 bfd_vma constant = insn & 0xff;
11789 bfd_vma rotation = (insn & 0xf00) >> 8;
11790
11791 if (rotation == 0)
11792 signed_addend = constant;
11793 else
11794 {
11795 /* Compensate for the fact that in the instruction, the
11796 rotation is stored in multiples of 2 bits. */
11797 rotation *= 2;
11798
11799 /* Rotate "constant" right by "rotation" bits. */
11800 signed_addend = (constant >> rotation) |
11801 (constant << (8 * sizeof (bfd_vma) - rotation));
11802 }
11803
11804 /* Determine if the instruction is an ADD or a SUB.
11805 (For REL, this determines the sign of the addend.) */
11806 negative = identify_add_or_sub (insn);
11807 if (negative == 0)
11808 {
4eca0228 11809 _bfd_error_handler
695344c0 11810 /* xgettext:c-format */
90b6238f 11811 (_("%pB(%pA+%#" PRIx64 "): only ADD or SUB instructions "
2dcf00ce
AM		 11812 "are allowed for ALU group relocations"),
11813 input_bfd, input_section, (uint64_t) rel->r_offset);
99059e56
RM		 11814 return bfd_reloc_overflow;
11815 }
11816
11817 signed_addend *= negative;
11818 }
4962c51a
MS		 11819
11820 /* Compute the value (X) to go in the place. */
99059e56
RM		 11821 if (r_type == R_ARM_ALU_PC_G0_NC
11822 || r_type == R_ARM_ALU_PC_G1_NC
11823 || r_type == R_ARM_ALU_PC_G0
11824 || r_type == R_ARM_ALU_PC_G1
11825 || r_type == R_ARM_ALU_PC_G2)
11826 /* PC relative. */
11827 signed_value = value - pc + signed_addend;
11828 else
11829 /* Section base relative. */
11830 signed_value = value - sb + signed_addend;
11831
11832 /* If the target symbol is a Thumb function, then set the
11833 Thumb bit in the address. */
35fc36a8 11834 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 11835 signed_value |= 1;
11836
99059e56
RM		 11837 /* Calculate the value of the relevant G_n, in encoded
11838 constant-with-rotation format. */
b6518b38
NC		 11839 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11840 group, &residual);
99059e56
RM		 11841
11842 /* Check for overflow if required. */
11843 if ((r_type == R_ARM_ALU_PC_G0
11844 || r_type == R_ARM_ALU_PC_G1
11845 || r_type == R_ARM_ALU_PC_G2
11846 || r_type == R_ARM_ALU_SB_G0
11847 || r_type == R_ARM_ALU_SB_G1
11848 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
11849 {
4eca0228 11850 _bfd_error_handler
695344c0 11851 /* xgettext:c-format */
90b6238f 11852 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 11853 "splitting %#" PRIx64 " for group relocation %s"),
11854 input_bfd, input_section, (uint64_t) rel->r_offset,
11855 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
11856 howto->name);
99059e56
RM		 11857 return bfd_reloc_overflow;
11858 }
11859
11860 /* Mask out the value and the ADD/SUB part of the opcode; take care
11861 not to destroy the S bit. */
11862 insn &= 0xff1ff000;
11863
11864 /* Set the opcode according to whether the value to go in the
11865 place is negative. */
11866 if (signed_value < 0)
11867 insn |= 1 << 22;
11868 else
11869 insn |= 1 << 23;
11870
11871 /* Encode the offset. */
11872 insn |= g_n;
4962c51a
MS		 11873
11874 bfd_put_32 (input_bfd, insn, hit_data);
11875 }
11876 return bfd_reloc_ok;
11877
11878 case R_ARM_LDR_PC_G0:
11879 case R_ARM_LDR_PC_G1:
11880 case R_ARM_LDR_PC_G2:
11881 case R_ARM_LDR_SB_G0:
11882 case R_ARM_LDR_SB_G1:
11883 case R_ARM_LDR_SB_G2:
11884 {
11885 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11886 bfd_vma pc = input_section->output_section->vma
4962c51a 11887 + input_section->output_offset + rel->r_offset;
31a91d61 11888 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11889 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11890 bfd_vma residual;
4962c51a 11891 bfd_signed_vma signed_value;
99059e56
RM		 11892 int group = 0;
11893
11894 /* Determine which groups of bits to calculate. */
11895 switch (r_type)
11896 {
11897 case R_ARM_LDR_PC_G0:
11898 case R_ARM_LDR_SB_G0:
11899 group = 0;
11900 break;
11901
11902 case R_ARM_LDR_PC_G1:
11903 case R_ARM_LDR_SB_G1:
11904 group = 1;
11905 break;
11906
11907 case R_ARM_LDR_PC_G2:
11908 case R_ARM_LDR_SB_G2:
11909 group = 2;
11910 break;
11911
11912 default:
11913 abort ();
11914 }
11915
11916 /* If REL, extract the addend from the insn. If RELA, it will
11917 have already been fetched for us. */
4962c51a 11918 if (globals->use_rel)
99059e56
RM		 11919 {
11920 int negative = (insn & (1 << 23)) ? 1 : -1;
11921 signed_addend = negative * (insn & 0xfff);
11922 }
4962c51a
MS		 11923
11924 /* Compute the value (X) to go in the place. */
99059e56
RM		 11925 if (r_type == R_ARM_LDR_PC_G0
11926 || r_type == R_ARM_LDR_PC_G1
11927 || r_type == R_ARM_LDR_PC_G2)
11928 /* PC relative. */
11929 signed_value = value - pc + signed_addend;
11930 else
11931 /* Section base relative. */
11932 signed_value = value - sb + signed_addend;
11933
11934 /* Calculate the value of the relevant G_{n-1} to obtain
11935 the residual at that stage. */
b6518b38
NC		 11936 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11937 group - 1, &residual);
99059e56
RM		 11938
11939 /* Check for overflow. */
11940 if (residual >= 0x1000)
11941 {
4eca0228 11942 _bfd_error_handler
695344c0 11943 /* xgettext:c-format */
90b6238f 11944 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 11945 "splitting %#" PRIx64 " for group relocation %s"),
11946 input_bfd, input_section, (uint64_t) rel->r_offset,
11947 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
11948 howto->name);
99059e56
RM		 11949 return bfd_reloc_overflow;
11950 }
11951
11952 /* Mask out the value and U bit. */
11953 insn &= 0xff7ff000;
11954
11955 /* Set the U bit if the value to go in the place is non-negative. */
11956 if (signed_value >= 0)
11957 insn |= 1 << 23;
11958
11959 /* Encode the offset. */
11960 insn |= residual;
4962c51a
MS		 11961
11962 bfd_put_32 (input_bfd, insn, hit_data);
11963 }
11964 return bfd_reloc_ok;
11965
11966 case R_ARM_LDRS_PC_G0:
11967 case R_ARM_LDRS_PC_G1:
11968 case R_ARM_LDRS_PC_G2:
11969 case R_ARM_LDRS_SB_G0:
11970 case R_ARM_LDRS_SB_G1:
11971 case R_ARM_LDRS_SB_G2:
11972 {
11973 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11974 bfd_vma pc = input_section->output_section->vma
4962c51a 11975 + input_section->output_offset + rel->r_offset;
31a91d61 11976 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11977 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11978 bfd_vma residual;
4962c51a 11979 bfd_signed_vma signed_value;
99059e56
RM		 11980 int group = 0;
11981
11982 /* Determine which groups of bits to calculate. */
11983 switch (r_type)
11984 {
11985 case R_ARM_LDRS_PC_G0:
11986 case R_ARM_LDRS_SB_G0:
11987 group = 0;
11988 break;
11989
11990 case R_ARM_LDRS_PC_G1:
11991 case R_ARM_LDRS_SB_G1:
11992 group = 1;
11993 break;
11994
11995 case R_ARM_LDRS_PC_G2:
11996 case R_ARM_LDRS_SB_G2:
11997 group = 2;
11998 break;
11999
12000 default:
12001 abort ();
12002 }
12003
12004 /* If REL, extract the addend from the insn. If RELA, it will
12005 have already been fetched for us. */
4962c51a 12006 if (globals->use_rel)
99059e56
RM		 12007 {
12008 int negative = (insn & (1 << 23)) ? 1 : -1;
12009 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
12010 }
4962c51a
MS		 12011
12012 /* Compute the value (X) to go in the place. */
99059e56
RM		 12013 if (r_type == R_ARM_LDRS_PC_G0
12014 || r_type == R_ARM_LDRS_PC_G1
12015 || r_type == R_ARM_LDRS_PC_G2)
12016 /* PC relative. */
12017 signed_value = value - pc + signed_addend;
12018 else
12019 /* Section base relative. */
12020 signed_value = value - sb + signed_addend;
12021
12022 /* Calculate the value of the relevant G_{n-1} to obtain
12023 the residual at that stage. */
b6518b38
NC		 12024 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12025 group - 1, &residual);
99059e56
RM		 12026
12027 /* Check for overflow. */
12028 if (residual >= 0x100)
12029 {
4eca0228 12030 _bfd_error_handler
695344c0 12031 /* xgettext:c-format */
90b6238f 12032 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12033 "splitting %#" PRIx64 " for group relocation %s"),
12034 input_bfd, input_section, (uint64_t) rel->r_offset,
12035 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12036 howto->name);
99059e56
RM		 12037 return bfd_reloc_overflow;
12038 }
12039
12040 /* Mask out the value and U bit. */
12041 insn &= 0xff7ff0f0;
12042
12043 /* Set the U bit if the value to go in the place is non-negative. */
12044 if (signed_value >= 0)
12045 insn |= 1 << 23;
12046
12047 /* Encode the offset. */
12048 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 12049
12050 bfd_put_32 (input_bfd, insn, hit_data);
12051 }
12052 return bfd_reloc_ok;
12053
12054 case R_ARM_LDC_PC_G0:
12055 case R_ARM_LDC_PC_G1:
12056 case R_ARM_LDC_PC_G2:
12057 case R_ARM_LDC_SB_G0:
12058 case R_ARM_LDC_SB_G1:
12059 case R_ARM_LDC_SB_G2:
12060 {
12061 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 12062 bfd_vma pc = input_section->output_section->vma
4962c51a 12063 + input_section->output_offset + rel->r_offset;
31a91d61 12064 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 12065 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 12066 bfd_vma residual;
4962c51a 12067 bfd_signed_vma signed_value;
99059e56
RM		 12068 int group = 0;
12069
12070 /* Determine which groups of bits to calculate. */
12071 switch (r_type)
12072 {
12073 case R_ARM_LDC_PC_G0:
12074 case R_ARM_LDC_SB_G0:
12075 group = 0;
12076 break;
12077
12078 case R_ARM_LDC_PC_G1:
12079 case R_ARM_LDC_SB_G1:
12080 group = 1;
12081 break;
12082
12083 case R_ARM_LDC_PC_G2:
12084 case R_ARM_LDC_SB_G2:
12085 group = 2;
12086 break;
12087
12088 default:
12089 abort ();
12090 }
12091
12092 /* If REL, extract the addend from the insn. If RELA, it will
12093 have already been fetched for us. */
4962c51a 12094 if (globals->use_rel)
99059e56
RM		 12095 {
12096 int negative = (insn & (1 << 23)) ? 1 : -1;
12097 signed_addend = negative * ((insn & 0xff) << 2);
12098 }
4962c51a
MS		 12099
12100 /* Compute the value (X) to go in the place. */
99059e56
RM		 12101 if (r_type == R_ARM_LDC_PC_G0
12102 || r_type == R_ARM_LDC_PC_G1
12103 || r_type == R_ARM_LDC_PC_G2)
12104 /* PC relative. */
12105 signed_value = value - pc + signed_addend;
12106 else
12107 /* Section base relative. */
12108 signed_value = value - sb + signed_addend;
12109
12110 /* Calculate the value of the relevant G_{n-1} to obtain
12111 the residual at that stage. */
b6518b38
NC		 12112 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12113 group - 1, &residual);
99059e56
RM		 12114
12115 /* Check for overflow. (The absolute value to go in the place must be
12116 divisible by four and, after having been divided by four, must
12117 fit in eight bits.) */
12118 if ((residual & 0x3) != 0 || residual >= 0x400)
12119 {
4eca0228 12120 _bfd_error_handler
695344c0 12121 /* xgettext:c-format */
90b6238f 12122 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
2dcf00ce
AM		 12123 "splitting %#" PRIx64 " for group relocation %s"),
12124 input_bfd, input_section, (uint64_t) rel->r_offset,
12125 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12126 howto->name);
99059e56
RM		 12127 return bfd_reloc_overflow;
12128 }
12129
12130 /* Mask out the value and U bit. */
12131 insn &= 0xff7fff00;
12132
12133 /* Set the U bit if the value to go in the place is non-negative. */
12134 if (signed_value >= 0)
12135 insn |= 1 << 23;
12136
12137 /* Encode the offset. */
12138 insn |= residual >> 2;
4962c51a
MS		 12139
12140 bfd_put_32 (input_bfd, insn, hit_data);
12141 }
12142 return bfd_reloc_ok;
12143
72d98d16
MG		 12144 case R_ARM_THM_ALU_ABS_G0_NC:
12145 case R_ARM_THM_ALU_ABS_G1_NC:
12146 case R_ARM_THM_ALU_ABS_G2_NC:
12147 case R_ARM_THM_ALU_ABS_G3_NC:
12148 {
12149 const int shift_array[4] = {0, 8, 16, 24};
12150 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12151 bfd_vma addr = value;
12152 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12153
12154 /* Compute address. */
12155 if (globals->use_rel)
12156 signed_addend = insn & 0xff;
12157 addr += signed_addend;
12158 if (branch_type == ST_BRANCH_TO_THUMB)
12159 addr |= 1;
12160 /* Clean imm8 insn. */
12161 insn &= 0xff00;
12162 /* And update with correct part of address. */
12163 insn |= (addr >> shift) & 0xff;
12164 /* Update insn. */
12165 bfd_put_16 (input_bfd, insn, hit_data);
12166 }
12167
12168 *unresolved_reloc_p = FALSE;
12169 return bfd_reloc_ok;
12170
252b5132
RH		 12171 default:
12172 return bfd_reloc_notsupported;
12173 }
12174}
12175
98c1d4aa
NC		 12176/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
12177static void
07d6d2b8
AM		 12178arm_add_to_rel (bfd * abfd,
12179 bfd_byte * address,
57e8b36a 12180 reloc_howto_type * howto,
07d6d2b8 12181 bfd_signed_vma increment)
98c1d4aa 12182{
98c1d4aa
NC		 12183 bfd_signed_vma addend;
12184
bd97cb95
DJ		 12185 if (howto->type == R_ARM_THM_CALL
12186 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 12187 {
9a5aca8c
AM		 12188 int upper_insn, lower_insn;
12189 int upper, lower;
98c1d4aa 12190
9a5aca8c
AM		 12191 upper_insn = bfd_get_16 (abfd, address);
12192 lower_insn = bfd_get_16 (abfd, address + 2);
12193 upper = upper_insn & 0x7ff;
12194 lower = lower_insn & 0x7ff;
12195
12196 addend = (upper << 12) | (lower << 1);
ddda4409 12197 addend += increment;
9a5aca8c 12198 addend >>= 1;
98c1d4aa 12199
9a5aca8c
AM		 12200 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
12201 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
12202
dc810e39
AM		 12203 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
12204 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 12205 }
12206 else
12207 {
07d6d2b8 12208 bfd_vma contents;
9a5aca8c
AM		 12209
12210 contents = bfd_get_32 (abfd, address);
12211
12212 /* Get the (signed) value from the instruction. */
12213 addend = contents & howto->src_mask;
12214 if (addend & ((howto->src_mask + 1) >> 1))
12215 {
12216 bfd_signed_vma mask;
12217
12218 mask = -1;
12219 mask &= ~ howto->src_mask;
12220 addend |= mask;
12221 }
12222
12223 /* Add in the increment, (which is a byte value). */
12224 switch (howto->type)
12225 {
12226 default:
12227 addend += increment;
12228 break;
12229
12230 case R_ARM_PC24:
c6596c5e 12231 case R_ARM_PLT32:
5b5bb741
PB		 12232 case R_ARM_CALL:
12233 case R_ARM_JUMP24:
9a5aca8c 12234 addend <<= howto->size;
dc810e39 12235 addend += increment;
9a5aca8c
AM		 12236
12237 /* Should we check for overflow here ? */
12238
12239 /* Drop any undesired bits. */
12240 addend >>= howto->rightshift;
12241 break;
12242 }
12243
12244 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
12245
12246 bfd_put_32 (abfd, contents, address);
ddda4409 12247 }
98c1d4aa 12248}
252b5132 12249
ba93b8ac
DJ		 12250#define IS_ARM_TLS_RELOC(R_TYPE) \
12251 ((R_TYPE) == R_ARM_TLS_GD32 \
12252 || (R_TYPE) == R_ARM_TLS_LDO32 \
12253 || (R_TYPE) == R_ARM_TLS_LDM32 \
12254 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
12255 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
12256 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
12257 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 12258 || (R_TYPE) == R_ARM_TLS_IE32 \
12259 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
12260
12261/* Specific set of relocations for the gnu tls dialect. */
12262#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
12263 ((R_TYPE) == R_ARM_TLS_GOTDESC \
12264 || (R_TYPE) == R_ARM_TLS_CALL \
12265 || (R_TYPE) == R_ARM_THM_TLS_CALL \
12266 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
12267 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 12268
252b5132 12269/* Relocate an ARM ELF section. */
906e58ca 12270
b34976b6 12271static bfd_boolean
07d6d2b8 12272elf32_arm_relocate_section (bfd * output_bfd,
57e8b36a 12273 struct bfd_link_info * info,
07d6d2b8
AM		 12274 bfd * input_bfd,
12275 asection * input_section,
12276 bfd_byte * contents,
12277 Elf_Internal_Rela * relocs,
12278 Elf_Internal_Sym * local_syms,
12279 asection ** local_sections)
252b5132 12280{
b34976b6
AM		 12281 Elf_Internal_Shdr *symtab_hdr;
12282 struct elf_link_hash_entry **sym_hashes;
12283 Elf_Internal_Rela *rel;
12284 Elf_Internal_Rela *relend;
12285 const char *name;
b32d3aa2 12286 struct elf32_arm_link_hash_table * globals;
252b5132 12287
4e7fd91e 12288 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 12289 if (globals == NULL)
12290 return FALSE;
b491616a 12291
0ffa91dd 12292 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 12293 sym_hashes = elf_sym_hashes (input_bfd);
12294
12295 rel = relocs;
12296 relend = relocs + input_section->reloc_count;
12297 for (; rel < relend; rel++)
12298 {
07d6d2b8
AM		 12299 int r_type;
12300 reloc_howto_type * howto;
12301 unsigned long r_symndx;
12302 Elf_Internal_Sym * sym;
12303 asection * sec;
252b5132 12304 struct elf_link_hash_entry * h;
07d6d2b8
AM		 12305 bfd_vma relocation;
12306 bfd_reloc_status_type r;
12307 arelent bfd_reloc;
12308 char sym_type;
12309 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 12310 char *error_message = NULL;
f21f3fe0 12311
252b5132 12312 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 12313 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 12314 r_type = arm_real_reloc_type (globals, r_type);
252b5132 12315
ba96a88f 12316 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 12317 || r_type == R_ARM_GNU_VTINHERIT)
12318 continue;
252b5132 12319
47aeb64c
NC		 12320 howto = bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
12321
12322 if (howto == NULL)
12323 return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
252b5132 12324
252b5132
RH		 12325 h = NULL;
12326 sym = NULL;
12327 sec = NULL;
9b485d32 12328
252b5132
RH		 12329 if (r_symndx < symtab_hdr->sh_info)
12330 {
12331 sym = local_syms + r_symndx;
ba93b8ac 12332 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 12333 sec = local_sections[r_symndx];
ffcb4889
NS		 12334
12335 /* An object file might have a reference to a local
12336 undefined symbol. This is a daft object file, but we
12337 should at least do something about it. V4BX & NONE
12338 relocations do not use the symbol and are explicitly
77b4f08f
TS		 12339 allowed to use the undefined symbol, so allow those.
12340 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 12341 if (r_type != R_ARM_V4BX
12342 && r_type != R_ARM_NONE
77b4f08f 12343 && r_symndx != STN_UNDEF
ffcb4889
NS		 12344 && bfd_is_und_section (sec)
12345 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
1a72702b
AM		 12346 (*info->callbacks->undefined_symbol)
12347 (info, bfd_elf_string_from_elf_section
12348 (input_bfd, symtab_hdr->sh_link, sym->st_name),
12349 input_bfd, input_section,
12350 rel->r_offset, TRUE);
b38cadfb 12351
4e7fd91e 12352 if (globals->use_rel)
f8df10f4 12353 {
4e7fd91e
PB		 12354 relocation = (sec->output_section->vma
12355 + sec->output_offset
12356 + sym->st_value);
0e1862bb 12357 if (!bfd_link_relocatable (info)
ab96bf03
AM		 12358 && (sec->flags & SEC_MERGE)
12359 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 12360 {
4e7fd91e
PB		 12361 asection *msec;
12362 bfd_vma addend, value;
12363
39623e12 12364 switch (r_type)
4e7fd91e 12365 {
39623e12
PB		 12366 case R_ARM_MOVW_ABS_NC:
12367 case R_ARM_MOVT_ABS:
12368 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12369 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
12370 addend = (addend ^ 0x8000) - 0x8000;
12371 break;
f8df10f4 12372
39623e12
PB		 12373 case R_ARM_THM_MOVW_ABS_NC:
12374 case R_ARM_THM_MOVT_ABS:
12375 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
12376 << 16;
12377 value |= bfd_get_16 (input_bfd,
12378 contents + rel->r_offset + 2);
12379 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
12380 | ((value & 0x04000000) >> 15);
12381 addend = (addend ^ 0x8000) - 0x8000;
12382 break;
f8df10f4 12383
39623e12
PB		 12384 default:
12385 if (howto->rightshift
12386 || (howto->src_mask & (howto->src_mask + 1)))
12387 {
4eca0228 12388 _bfd_error_handler
695344c0 12389 /* xgettext:c-format */
2dcf00ce
AM		 12390 (_("%pB(%pA+%#" PRIx64 "): "
12391 "%s relocation against SEC_MERGE section"),
39623e12 12392 input_bfd, input_section,
2dcf00ce 12393 (uint64_t) rel->r_offset, howto->name);
39623e12
PB		 12394 return FALSE;
12395 }
12396
12397 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
12398
12399 /* Get the (signed) value from the instruction. */
12400 addend = value & howto->src_mask;
12401 if (addend & ((howto->src_mask + 1) >> 1))
12402 {
12403 bfd_signed_vma mask;
12404
12405 mask = -1;
12406 mask &= ~ howto->src_mask;
12407 addend |= mask;
12408 }
12409 break;
4e7fd91e 12410 }
39623e12 12411
4e7fd91e
PB		 12412 msec = sec;
12413 addend =
12414 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
12415 - relocation;
12416 addend += msec->output_section->vma + msec->output_offset;
39623e12 12417
cc643b88 12418 /* Cases here must match those in the preceding
39623e12
PB		 12419 switch statement. */
12420 switch (r_type)
12421 {
12422 case R_ARM_MOVW_ABS_NC:
12423 case R_ARM_MOVT_ABS:
12424 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
12425 | (addend & 0xfff);
12426 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12427 break;
12428
12429 case R_ARM_THM_MOVW_ABS_NC:
12430 case R_ARM_THM_MOVT_ABS:
12431 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
12432 | (addend & 0xff) | ((addend & 0x0800) << 15);
12433 bfd_put_16 (input_bfd, value >> 16,
12434 contents + rel->r_offset);
12435 bfd_put_16 (input_bfd, value,
12436 contents + rel->r_offset + 2);
12437 break;
12438
12439 default:
12440 value = (value & ~ howto->dst_mask)
12441 | (addend & howto->dst_mask);
12442 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
12443 break;
12444 }
f8df10f4 12445 }
f8df10f4 12446 }
4e7fd91e
PB		 12447 else
12448 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 12449 }
12450 else
12451 {
62d887d4 12452 bfd_boolean warned, ignored;
560e09e9 12453
b2a8e766
AM		 12454 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
12455 r_symndx, symtab_hdr, sym_hashes,
12456 h, sec, relocation,
62d887d4 12457 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 12458
12459 sym_type = h->type;
252b5132
RH		 12460 }
12461
dbaa2011 12462 if (sec != NULL && discarded_section (sec))
e4067dbb 12463 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 12464 rel, 1, relend, howto, 0, contents);
ab96bf03 12465
0e1862bb 12466 if (bfd_link_relocatable (info))
ab96bf03
AM		 12467 {
12468 /* This is a relocatable link. We don't have to change
12469 anything, unless the reloc is against a section symbol,
12470 in which case we have to adjust according to where the
12471 section symbol winds up in the output section. */
12472 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
12473 {
12474 if (globals->use_rel)
12475 arm_add_to_rel (input_bfd, contents + rel->r_offset,
12476 howto, (bfd_signed_vma) sec->output_offset);
12477 else
12478 rel->r_addend += sec->output_offset;
12479 }
12480 continue;
12481 }
12482
252b5132
RH		 12483 if (h != NULL)
12484 name = h->root.root.string;
12485 else
12486 {
12487 name = (bfd_elf_string_from_elf_section
12488 (input_bfd, symtab_hdr->sh_link, sym->st_name));
12489 if (name == NULL || *name == '\0')
12490 name = bfd_section_name (input_bfd, sec);
12491 }
f21f3fe0 12492
cf35638d 12493 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 12494 && r_type != R_ARM_NONE
12495 && (h == NULL
12496 || h->root.type == bfd_link_hash_defined
12497 || h->root.type == bfd_link_hash_defweak)
12498 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
12499 {
4eca0228 12500 _bfd_error_handler
ba93b8ac 12501 ((sym_type == STT_TLS
695344c0 12502 /* xgettext:c-format */
2dcf00ce 12503 ? _("%pB(%pA+%#" PRIx64 "): %s used with TLS symbol %s")
695344c0 12504 /* xgettext:c-format */
2dcf00ce 12505 : _("%pB(%pA+%#" PRIx64 "): %s used with non-TLS symbol %s")),
ba93b8ac
DJ		 12506 input_bfd,
12507 input_section,
2dcf00ce 12508 (uint64_t) rel->r_offset,
ba93b8ac
DJ		 12509 howto->name,
12510 name);
12511 }
12512
0855e32b 12513 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 12514 done, i.e., the relaxation produced the final output we want,
12515 and we won't let anybody mess with it. Also, we have to do
12516 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 12517 both in relaxed and non-relaxed cases. */
39d911fc
TP		 12518 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
12519 || (IS_ARM_TLS_GNU_RELOC (r_type)
12520 && !((h ? elf32_arm_hash_entry (h)->tls_type :
12521 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
12522 & GOT_TLS_GDESC)))
12523 {
12524 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
12525 contents, rel, h == NULL);
12526 /* This may have been marked unresolved because it came from
12527 a shared library. But we've just dealt with that. */
12528 unresolved_reloc = 0;
12529 }
12530 else
12531 r = bfd_reloc_continue;
b38cadfb 12532
39d911fc
TP		 12533 if (r == bfd_reloc_continue)
12534 {
12535 unsigned char branch_type =
12536 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
12537 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
12538
12539 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
12540 input_section, contents, rel,
12541 relocation, info, sec, name,
12542 sym_type, branch_type, h,
12543 &unresolved_reloc,
12544 &error_message);
12545 }
0945cdfd
DJ		 12546
12547 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
12548 because such sections are not SEC_ALLOC and thus ld.so will
12549 not process them. */
12550 if (unresolved_reloc
99059e56
RM		 12551 && !((input_section->flags & SEC_DEBUGGING) != 0
12552 && h->def_dynamic)
1d5316ab
AM		 12553 && _bfd_elf_section_offset (output_bfd, info, input_section,
12554 rel->r_offset) != (bfd_vma) -1)
0945cdfd 12555 {
4eca0228 12556 _bfd_error_handler
695344c0 12557 /* xgettext:c-format */
2dcf00ce
AM		 12558 (_("%pB(%pA+%#" PRIx64 "): "
12559 "unresolvable %s relocation against symbol `%s'"),
843fe662
L		 12560 input_bfd,
12561 input_section,
2dcf00ce 12562 (uint64_t) rel->r_offset,
843fe662
L		 12563 howto->name,
12564 h->root.root.string);
0945cdfd
DJ		 12565 return FALSE;
12566 }
252b5132
RH		 12567
12568 if (r != bfd_reloc_ok)
12569 {
252b5132
RH		 12570 switch (r)
12571 {
12572 case bfd_reloc_overflow:
cf919dfd
PB		 12573 /* If the overflowing reloc was to an undefined symbol,
12574 we have already printed one error message and there
12575 is no point complaining again. */
1a72702b
AM		 12576 if (!h || h->root.type != bfd_link_hash_undefined)
12577 (*info->callbacks->reloc_overflow)
12578 (info, (h ? &h->root : NULL), name, howto->name,
12579 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12580 break;
12581
12582 case bfd_reloc_undefined:
1a72702b
AM		 12583 (*info->callbacks->undefined_symbol)
12584 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
252b5132
RH		 12585 break;
12586
12587 case bfd_reloc_outofrange:
f2a9dd69 12588 error_message = _("out of range");
252b5132
RH		 12589 goto common_error;
12590
12591 case bfd_reloc_notsupported:
f2a9dd69 12592 error_message = _("unsupported relocation");
252b5132
RH		 12593 goto common_error;
12594
12595 case bfd_reloc_dangerous:
f2a9dd69 12596 /* error_message should already be set. */
252b5132
RH		 12597 goto common_error;
12598
12599 default:
f2a9dd69 12600 error_message = _("unknown error");
8029a119 12601 /* Fall through. */
252b5132
RH		 12602
12603 common_error:
f2a9dd69 12604 BFD_ASSERT (error_message != NULL);
1a72702b
AM		 12605 (*info->callbacks->reloc_dangerous)
12606 (info, error_message, input_bfd, input_section, rel->r_offset);
252b5132
RH		 12607 break;
12608 }
12609 }
12610 }
12611
b34976b6 12612 return TRUE;
252b5132
RH		 12613}
12614
91d6fa6a 12615/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 12616 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 12617 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 12618 maintaining that condition). */
12619
12620static void
12621add_unwind_table_edit (arm_unwind_table_edit **head,
12622 arm_unwind_table_edit **tail,
12623 arm_unwind_edit_type type,
12624 asection *linked_section,
91d6fa6a 12625 unsigned int tindex)
2468f9c9 12626{
21d799b5
NC		 12627 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
12628 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 12629
2468f9c9
PB		 12630 new_edit->type = type;
12631 new_edit->linked_section = linked_section;
91d6fa6a 12632 new_edit->index = tindex;
b38cadfb 12633
91d6fa6a 12634 if (tindex > 0)
2468f9c9
PB		 12635 {
12636 new_edit->next = NULL;
12637
12638 if (*tail)
12639 (*tail)->next = new_edit;
12640
12641 (*tail) = new_edit;
12642
12643 if (!*head)
12644 (*head) = new_edit;
12645 }
12646 else
12647 {
12648 new_edit->next = *head;
12649
12650 if (!*tail)
12651 *tail = new_edit;
12652
12653 *head = new_edit;
12654 }
12655}
12656
12657static _arm_elf_section_data *get_arm_elf_section_data (asection *);
12658
12659/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
12660static void
12661adjust_exidx_size(asection *exidx_sec, int adjust)
12662{
12663 asection *out_sec;
12664
12665 if (!exidx_sec->rawsize)
12666 exidx_sec->rawsize = exidx_sec->size;
12667
12668 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
12669 out_sec = exidx_sec->output_section;
12670 /* Adjust size of output section. */
12671 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
12672}
12673
12674/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
12675static void
12676insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
12677{
12678 struct _arm_elf_section_data *exidx_arm_data;
12679
12680 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12681 add_unwind_table_edit (
12682 &exidx_arm_data->u.exidx.unwind_edit_list,
12683 &exidx_arm_data->u.exidx.unwind_edit_tail,
12684 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
12685
491d01d3
YU		 12686 exidx_arm_data->additional_reloc_count++;
12687
2468f9c9
PB		 12688 adjust_exidx_size(exidx_sec, 8);
12689}
12690
12691/* Scan .ARM.exidx tables, and create a list describing edits which should be
12692 made to those tables, such that:
b38cadfb 12693
2468f9c9
PB		 12694 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
12695 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 12696 codes which have been inlined into the index).
2468f9c9 12697
85fdf906
AH		 12698 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
12699
2468f9c9 12700 The edits are applied when the tables are written
b38cadfb 12701 (in elf32_arm_write_section). */
2468f9c9
PB		 12702
12703bfd_boolean
12704elf32_arm_fix_exidx_coverage (asection **text_section_order,
12705 unsigned int num_text_sections,
85fdf906
AH		 12706 struct bfd_link_info *info,
12707 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 12708{
12709 bfd *inp;
12710 unsigned int last_second_word = 0, i;
12711 asection *last_exidx_sec = NULL;
12712 asection *last_text_sec = NULL;
12713 int last_unwind_type = -1;
12714
12715 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
12716 text sections. */
c72f2fb2 12717 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 12718 {
12719 asection *sec;
b38cadfb 12720
2468f9c9 12721 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 12722 {
2468f9c9
PB		 12723 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
12724 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 12725
dec9d5df 12726 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 12727 continue;
b38cadfb 12728
2468f9c9
PB		 12729 if (elf_sec->linked_to)
12730 {
12731 Elf_Internal_Shdr *linked_hdr
99059e56 12732 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 12733 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 12734 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 12735
12736 if (linked_sec_arm_data == NULL)
99059e56 12737 continue;
2468f9c9
PB		 12738
12739 /* Link this .ARM.exidx section back from the text section it
99059e56 12740 describes. */
2468f9c9
PB		 12741 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
12742 }
12743 }
12744 }
12745
12746 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
12747 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 12748 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 12749
12750 for (i = 0; i < num_text_sections; i++)
12751 {
12752 asection *sec = text_section_order[i];
12753 asection *exidx_sec;
12754 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
12755 struct _arm_elf_section_data *exidx_arm_data;
12756 bfd_byte *contents = NULL;
12757 int deleted_exidx_bytes = 0;
12758 bfd_vma j;
12759 arm_unwind_table_edit *unwind_edit_head = NULL;
12760 arm_unwind_table_edit *unwind_edit_tail = NULL;
12761 Elf_Internal_Shdr *hdr;
12762 bfd *ibfd;
12763
12764 if (arm_data == NULL)
99059e56 12765 continue;
2468f9c9
PB		 12766
12767 exidx_sec = arm_data->u.text.arm_exidx_sec;
12768 if (exidx_sec == NULL)
12769 {
12770 /* Section has no unwind data. */
12771 if (last_unwind_type == 0 || !last_exidx_sec)
12772 continue;
12773
12774 /* Ignore zero sized sections. */
12775 if (sec->size == 0)
12776 continue;
12777
12778 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12779 last_unwind_type = 0;
12780 continue;
12781 }
12782
22a8f80e
PB		 12783 /* Skip /DISCARD/ sections. */
12784 if (bfd_is_abs_section (exidx_sec->output_section))
12785 continue;
12786
2468f9c9
PB		 12787 hdr = &elf_section_data (exidx_sec)->this_hdr;
12788 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 12789 continue;
b38cadfb 12790
2468f9c9
PB		 12791 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
12792 if (exidx_arm_data == NULL)
99059e56 12793 continue;
b38cadfb 12794
2468f9c9 12795 ibfd = exidx_sec->owner;
b38cadfb 12796
2468f9c9
PB		 12797 if (hdr->contents != NULL)
12798 contents = hdr->contents;
12799 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
12800 /* An error? */
12801 continue;
12802
ac06903d
YU		 12803 if (last_unwind_type > 0)
12804 {
12805 unsigned int first_word = bfd_get_32 (ibfd, contents);
12806 /* Add cantunwind if first unwind item does not match section
12807 start. */
12808 if (first_word != sec->vma)
12809 {
12810 insert_cantunwind_after (last_text_sec, last_exidx_sec);
12811 last_unwind_type = 0;
12812 }
12813 }
12814
2468f9c9
PB		 12815 for (j = 0; j < hdr->sh_size; j += 8)
12816 {
12817 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
12818 int unwind_type;
12819 int elide = 0;
12820
12821 /* An EXIDX_CANTUNWIND entry. */
12822 if (second_word == 1)
12823 {
12824 if (last_unwind_type == 0)
12825 elide = 1;
12826 unwind_type = 0;
12827 }
12828 /* Inlined unwinding data. Merge if equal to previous. */
12829 else if ((second_word & 0x80000000) != 0)
12830 {
85fdf906
AH		 12831 if (merge_exidx_entries
12832 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 12833 elide = 1;
12834 unwind_type = 1;
12835 last_second_word = second_word;
12836 }
12837 /* Normal table entry. In theory we could merge these too,
12838 but duplicate entries are likely to be much less common. */
12839 else
12840 unwind_type = 2;
12841
491d01d3 12842 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 12843 {
12844 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
12845 DELETE_EXIDX_ENTRY, NULL, j / 8);
12846
12847 deleted_exidx_bytes += 8;
12848 }
12849
12850 last_unwind_type = unwind_type;
12851 }
12852
12853 /* Free contents if we allocated it ourselves. */
12854 if (contents != hdr->contents)
99059e56 12855 free (contents);
2468f9c9
PB		 12856
12857 /* Record edits to be applied later (in elf32_arm_write_section). */
12858 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
12859 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 12860
2468f9c9
PB		 12861 if (deleted_exidx_bytes > 0)
12862 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
12863
12864 last_exidx_sec = exidx_sec;
12865 last_text_sec = sec;
12866 }
12867
12868 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 12869 if (!bfd_link_relocatable (info) && last_exidx_sec
12870 && last_unwind_type != 0)
2468f9c9
PB		 12871 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12872
12873 return TRUE;
12874}
12875
3e6b1042
DJ		 12876static bfd_boolean
12877elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
12878 bfd *ibfd, const char *name)
12879{
12880 asection *sec, *osec;
12881
3d4d4302 12882 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 12883 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
12884 return TRUE;
12885
12886 osec = sec->output_section;
12887 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
12888 return TRUE;
12889
12890 if (! bfd_set_section_contents (obfd, osec, sec->contents,
12891 sec->output_offset, sec->size))
12892 return FALSE;
12893
12894 return TRUE;
12895}
12896
12897static bfd_boolean
12898elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
12899{
12900 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 12901 asection *sec, *osec;
3e6b1042 12902
4dfe6ac6
NC		 12903 if (globals == NULL)
12904 return FALSE;
12905
3e6b1042
DJ		 12906 /* Invoke the regular ELF backend linker to do all the work. */
12907 if (!bfd_elf_final_link (abfd, info))
12908 return FALSE;
12909
fe33d2fa
CL		 12910 /* Process stub sections (eg BE8 encoding, ...). */
12911 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 12912 unsigned int i;
cdb21a0a
NS		 12913 for (i=0; i<htab->top_id; i++)
12914 {
12915 sec = htab->stub_group[i].stub_sec;
12916 /* Only process it once, in its link_sec slot. */
12917 if (sec && i == htab->stub_group[i].link_sec->id)
12918 {
12919 osec = sec->output_section;
12920 elf32_arm_write_section (abfd, info, sec, sec->contents);
12921 if (! bfd_set_section_contents (abfd, osec, sec->contents,
12922 sec->output_offset, sec->size))
12923 return FALSE;
12924 }
fe33d2fa 12925 }
fe33d2fa 12926
3e6b1042
DJ		 12927 /* Write out any glue sections now that we have created all the
12928 stubs. */
12929 if (globals->bfd_of_glue_owner != NULL)
12930 {
12931 if (! elf32_arm_output_glue_section (info, abfd,
12932 globals->bfd_of_glue_owner,
12933 ARM2THUMB_GLUE_SECTION_NAME))
12934 return FALSE;
12935
12936 if (! elf32_arm_output_glue_section (info, abfd,
12937 globals->bfd_of_glue_owner,
12938 THUMB2ARM_GLUE_SECTION_NAME))
12939 return FALSE;
12940
12941 if (! elf32_arm_output_glue_section (info, abfd,
12942 globals->bfd_of_glue_owner,
12943 VFP11_ERRATUM_VENEER_SECTION_NAME))
12944 return FALSE;
12945
a504d23a
LA		 12946 if (! elf32_arm_output_glue_section (info, abfd,
12947 globals->bfd_of_glue_owner,
12948 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
12949 return FALSE;
12950
3e6b1042
DJ		 12951 if (! elf32_arm_output_glue_section (info, abfd,
12952 globals->bfd_of_glue_owner,
12953 ARM_BX_GLUE_SECTION_NAME))
12954 return FALSE;
12955 }
12956
12957 return TRUE;
12958}
12959
5968a7b8
NC		 12960/* Return a best guess for the machine number based on the attributes. */
12961
12962static unsigned int
12963bfd_arm_get_mach_from_attributes (bfd * abfd)
12964{
12965 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
12966
12967 switch (arch)
12968 {
12969 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
12970 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
12971 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
12972
12973 case TAG_CPU_ARCH_V5TE:
12974 {
12975 char * name;
12976
12977 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
12978 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
12979
12980 if (name)
12981 {
12982 if (strcmp (name, "IWMMXT2") == 0)
12983 return bfd_mach_arm_iWMMXt2;
12984
12985 if (strcmp (name, "IWMMXT") == 0)
6034aab8 12986 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 12987
12988 if (strcmp (name, "XSCALE") == 0)
12989 {
12990 int wmmx;
12991
12992 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
12993 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
12994 switch (wmmx)
12995 {
12996 case 1: return bfd_mach_arm_iWMMXt;
12997 case 2: return bfd_mach_arm_iWMMXt2;
12998 default: return bfd_mach_arm_XScale;
12999 }
13000 }
5968a7b8
NC		 13001 }
13002
13003 return bfd_mach_arm_5TE;
13004 }
13005
13006 default:
13007 return bfd_mach_arm_unknown;
13008 }
13009}
13010
c178919b
NC		 13011/* Set the right machine number. */
13012
13013static bfd_boolean
57e8b36a 13014elf32_arm_object_p (bfd *abfd)
c178919b 13015{
5a6c6817 13016 unsigned int mach;
57e8b36a 13017
5a6c6817 13018 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 13019
5968a7b8
NC		 13020 if (mach == bfd_mach_arm_unknown)
13021 {
13022 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13023 mach = bfd_mach_arm_ep9312;
13024 else
13025 mach = bfd_arm_get_mach_from_attributes (abfd);
13026 }
c178919b 13027
5968a7b8 13028 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 13029 return TRUE;
13030}
13031
fc830a83 13032/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 13033
b34976b6 13034static bfd_boolean
57e8b36a 13035elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 13036{
13037 if (elf_flags_init (abfd)
13038 && elf_elfheader (abfd)->e_flags != flags)
13039 {
fc830a83
NC		 13040 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13041 {
fd2ec330 13042 if (flags & EF_ARM_INTERWORK)
4eca0228 13043 _bfd_error_handler
90b6238f 13044 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
d003868e 13045 abfd);
fc830a83 13046 else
d003868e 13047 _bfd_error_handler
90b6238f 13048 (_("warning: clearing the interworking flag of %pB due to outside request"),
d003868e 13049 abfd);
fc830a83 13050 }
252b5132
RH		 13051 }
13052 else
13053 {
13054 elf_elfheader (abfd)->e_flags = flags;
b34976b6 13055 elf_flags_init (abfd) = TRUE;
252b5132
RH		 13056 }
13057
b34976b6 13058 return TRUE;
252b5132
RH		 13059}
13060
fc830a83 13061/* Copy backend specific data from one object module to another. */
9b485d32 13062
b34976b6 13063static bfd_boolean
57e8b36a 13064elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 13065{
13066 flagword in_flags;
13067 flagword out_flags;
13068
0ffa91dd 13069 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 13070 return TRUE;
252b5132 13071
fc830a83 13072 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 13073 out_flags = elf_elfheader (obfd)->e_flags;
13074
fc830a83
NC		 13075 if (elf_flags_init (obfd)
13076 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13077 && in_flags != out_flags)
252b5132 13078 {
252b5132 13079 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 13080 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 13081 return FALSE;
252b5132
RH		 13082
13083 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 13084 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 13085 return FALSE;
252b5132
RH		 13086
13087 /* If the src and dest have different interworking flags
99059e56 13088 then turn off the interworking bit. */
fd2ec330 13089 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 13090 {
fd2ec330 13091 if (out_flags & EF_ARM_INTERWORK)
d003868e 13092 _bfd_error_handler
90b6238f 13093 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
d003868e 13094 obfd, ibfd);
252b5132 13095
fd2ec330 13096 in_flags &= ~EF_ARM_INTERWORK;
252b5132 13097 }
1006ba19
PB		 13098
13099 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 13100 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
13101 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 13102 }
13103
13104 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 13105 elf_flags_init (obfd) = TRUE;
252b5132 13106
e2349352 13107 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 13108}
13109
13110/* Values for Tag_ABI_PCS_R9_use. */
13111enum
13112{
13113 AEABI_R9_V6,
13114 AEABI_R9_SB,
13115 AEABI_R9_TLS,
13116 AEABI_R9_unused
13117};
13118
13119/* Values for Tag_ABI_PCS_RW_data. */
13120enum
13121{
13122 AEABI_PCS_RW_data_absolute,
13123 AEABI_PCS_RW_data_PCrel,
13124 AEABI_PCS_RW_data_SBrel,
13125 AEABI_PCS_RW_data_unused
13126};
13127
13128/* Values for Tag_ABI_enum_size. */
13129enum
13130{
13131 AEABI_enum_unused,
13132 AEABI_enum_short,
13133 AEABI_enum_wide,
13134 AEABI_enum_forced_wide
13135};
13136
104d59d1
JM		 13137/* Determine whether an object attribute tag takes an integer, a
13138 string or both. */
906e58ca 13139
104d59d1
JM		 13140static int
13141elf32_arm_obj_attrs_arg_type (int tag)
13142{
13143 if (tag == Tag_compatibility)
3483fe2e 13144 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 13145 else if (tag == Tag_nodefaults)
3483fe2e
AS		 13146 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
13147 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
13148 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 13149 else if (tag < 32)
3483fe2e 13150 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 13151 else
3483fe2e 13152 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 13153}
13154
5aa6ff7c
AS		 13155/* The ABI defines that Tag_conformance should be emitted first, and that
13156 Tag_nodefaults should be second (if either is defined). This sets those
13157 two positions, and bumps up the position of all the remaining tags to
13158 compensate. */
13159static int
13160elf32_arm_obj_attrs_order (int num)
13161{
3de4a297 13162 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 13163 return Tag_conformance;
3de4a297 13164 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 13165 return Tag_nodefaults;
13166 if ((num - 2) < Tag_nodefaults)
13167 return num - 2;
13168 if ((num - 1) < Tag_conformance)
13169 return num - 1;
13170 return num;
13171}
13172
e8b36cd1
JM		 13173/* Attribute numbers >=64 (mod 128) can be safely ignored. */
13174static bfd_boolean
13175elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
13176{
13177 if ((tag & 127) < 64)
13178 {
13179 _bfd_error_handler
90b6238f 13180 (_("%pB: unknown mandatory EABI object attribute %d"),
e8b36cd1
JM		 13181 abfd, tag);
13182 bfd_set_error (bfd_error_bad_value);
13183 return FALSE;
13184 }
13185 else
13186 {
13187 _bfd_error_handler
90b6238f 13188 (_("warning: %pB: unknown EABI object attribute %d"),
e8b36cd1
JM		 13189 abfd, tag);
13190 return TRUE;
13191 }
13192}
13193
91e22acd
AS		 13194/* Read the architecture from the Tag_also_compatible_with attribute, if any.
13195 Returns -1 if no architecture could be read. */
13196
13197static int
13198get_secondary_compatible_arch (bfd *abfd)
13199{
13200 obj_attribute *attr =
13201 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
13202
13203 /* Note: the tag and its argument below are uleb128 values, though
13204 currently-defined values fit in one byte for each. */
13205 if (attr->s
13206 && attr->s[0] == Tag_CPU_arch
13207 && (attr->s[1] & 128) != 128
13208 && attr->s[2] == 0)
13209 return attr->s[1];
13210
13211 /* This tag is "safely ignorable", so don't complain if it looks funny. */
13212 return -1;
13213}
13214
13215/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
13216 The tag is removed if ARCH is -1. */
13217
8e79c3df 13218static void
91e22acd 13219set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 13220{
91e22acd
AS		 13221 obj_attribute *attr =
13222 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 13223
91e22acd
AS		 13224 if (arch == -1)
13225 {
13226 attr->s = NULL;
13227 return;
8e79c3df 13228 }
91e22acd
AS		 13229
13230 /* Note: the tag and its argument below are uleb128 values, though
13231 currently-defined values fit in one byte for each. */
13232 if (!attr->s)
21d799b5 13233 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 13234 attr->s[0] = Tag_CPU_arch;
13235 attr->s[1] = arch;
13236 attr->s[2] = '\0';
8e79c3df
CM		 13237}
13238
91e22acd
AS		 13239/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
13240 into account. */
13241
13242static int
13243tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
13244 int newtag, int secondary_compat)
8e79c3df 13245{
91e22acd
AS		 13246#define T(X) TAG_CPU_ARCH_##X
13247 int tagl, tagh, result;
13248 const int v6t2[] =
13249 {
13250 T(V6T2), /* PRE_V4. */
13251 T(V6T2), /* V4. */
13252 T(V6T2), /* V4T. */
13253 T(V6T2), /* V5T. */
13254 T(V6T2), /* V5TE. */
13255 T(V6T2), /* V5TEJ. */
13256 T(V6T2), /* V6. */
13257 T(V7), /* V6KZ. */
13258 T(V6T2) /* V6T2. */
13259 };
13260 const int v6k[] =
13261 {
13262 T(V6K), /* PRE_V4. */
13263 T(V6K), /* V4. */
13264 T(V6K), /* V4T. */
13265 T(V6K), /* V5T. */
13266 T(V6K), /* V5TE. */
13267 T(V6K), /* V5TEJ. */
13268 T(V6K), /* V6. */
13269 T(V6KZ), /* V6KZ. */
13270 T(V7), /* V6T2. */
13271 T(V6K) /* V6K. */
13272 };
13273 const int v7[] =
13274 {
13275 T(V7), /* PRE_V4. */
13276 T(V7), /* V4. */
13277 T(V7), /* V4T. */
13278 T(V7), /* V5T. */
13279 T(V7), /* V5TE. */
13280 T(V7), /* V5TEJ. */
13281 T(V7), /* V6. */
13282 T(V7), /* V6KZ. */
13283 T(V7), /* V6T2. */
13284 T(V7), /* V6K. */
13285 T(V7) /* V7. */
13286 };
13287 const int v6_m[] =
13288 {
07d6d2b8
AM		 13289 -1, /* PRE_V4. */
13290 -1, /* V4. */
91e22acd
AS		 13291 T(V6K), /* V4T. */
13292 T(V6K), /* V5T. */
13293 T(V6K), /* V5TE. */
13294 T(V6K), /* V5TEJ. */
13295 T(V6K), /* V6. */
13296 T(V6KZ), /* V6KZ. */
13297 T(V7), /* V6T2. */
13298 T(V6K), /* V6K. */
13299 T(V7), /* V7. */
13300 T(V6_M) /* V6_M. */
13301 };
13302 const int v6s_m[] =
13303 {
07d6d2b8
AM		 13304 -1, /* PRE_V4. */
13305 -1, /* V4. */
91e22acd
AS		 13306 T(V6K), /* V4T. */
13307 T(V6K), /* V5T. */
13308 T(V6K), /* V5TE. */
13309 T(V6K), /* V5TEJ. */
13310 T(V6K), /* V6. */
13311 T(V6KZ), /* V6KZ. */
13312 T(V7), /* V6T2. */
13313 T(V6K), /* V6K. */
13314 T(V7), /* V7. */
13315 T(V6S_M), /* V6_M. */
13316 T(V6S_M) /* V6S_M. */
13317 };
9e3c6df6
PB		 13318 const int v7e_m[] =
13319 {
07d6d2b8
AM		 13320 -1, /* PRE_V4. */
13321 -1, /* V4. */
9e3c6df6
PB		 13322 T(V7E_M), /* V4T. */
13323 T(V7E_M), /* V5T. */
13324 T(V7E_M), /* V5TE. */
13325 T(V7E_M), /* V5TEJ. */
13326 T(V7E_M), /* V6. */
13327 T(V7E_M), /* V6KZ. */
13328 T(V7E_M), /* V6T2. */
13329 T(V7E_M), /* V6K. */
13330 T(V7E_M), /* V7. */
13331 T(V7E_M), /* V6_M. */
13332 T(V7E_M), /* V6S_M. */
13333 T(V7E_M) /* V7E_M. */
13334 };
bca38921
MGD		 13335 const int v8[] =
13336 {
13337 T(V8), /* PRE_V4. */
13338 T(V8), /* V4. */
13339 T(V8), /* V4T. */
13340 T(V8), /* V5T. */
13341 T(V8), /* V5TE. */
13342 T(V8), /* V5TEJ. */
13343 T(V8), /* V6. */
13344 T(V8), /* V6KZ. */
13345 T(V8), /* V6T2. */
13346 T(V8), /* V6K. */
13347 T(V8), /* V7. */
13348 T(V8), /* V6_M. */
13349 T(V8), /* V6S_M. */
13350 T(V8), /* V7E_M. */
13351 T(V8) /* V8. */
13352 };
bff0500d
TP		 13353 const int v8r[] =
13354 {
13355 T(V8R), /* PRE_V4. */
13356 T(V8R), /* V4. */
13357 T(V8R), /* V4T. */
13358 T(V8R), /* V5T. */
13359 T(V8R), /* V5TE. */
13360 T(V8R), /* V5TEJ. */
13361 T(V8R), /* V6. */
13362 T(V8R), /* V6KZ. */
13363 T(V8R), /* V6T2. */
13364 T(V8R), /* V6K. */
13365 T(V8R), /* V7. */
13366 T(V8R), /* V6_M. */
13367 T(V8R), /* V6S_M. */
13368 T(V8R), /* V7E_M. */
13369 T(V8), /* V8. */
13370 T(V8R), /* V8R. */
13371 };
2fd158eb
TP		 13372 const int v8m_baseline[] =
13373 {
13374 -1, /* PRE_V4. */
13375 -1, /* V4. */
13376 -1, /* V4T. */
13377 -1, /* V5T. */
13378 -1, /* V5TE. */
13379 -1, /* V5TEJ. */
13380 -1, /* V6. */
13381 -1, /* V6KZ. */
13382 -1, /* V6T2. */
13383 -1, /* V6K. */
13384 -1, /* V7. */
13385 T(V8M_BASE), /* V6_M. */
13386 T(V8M_BASE), /* V6S_M. */
13387 -1, /* V7E_M. */
13388 -1, /* V8. */
bff0500d 13389 -1, /* V8R. */
2fd158eb
TP		 13390 T(V8M_BASE) /* V8-M BASELINE. */
13391 };
13392 const int v8m_mainline[] =
13393 {
13394 -1, /* PRE_V4. */
13395 -1, /* V4. */
13396 -1, /* V4T. */
13397 -1, /* V5T. */
13398 -1, /* V5TE. */
13399 -1, /* V5TEJ. */
13400 -1, /* V6. */
13401 -1, /* V6KZ. */
13402 -1, /* V6T2. */
13403 -1, /* V6K. */
13404 T(V8M_MAIN), /* V7. */
13405 T(V8M_MAIN), /* V6_M. */
13406 T(V8M_MAIN), /* V6S_M. */
13407 T(V8M_MAIN), /* V7E_M. */
13408 -1, /* V8. */
bff0500d 13409 -1, /* V8R. */
2fd158eb
TP		 13410 T(V8M_MAIN), /* V8-M BASELINE. */
13411 T(V8M_MAIN) /* V8-M MAINLINE. */
13412 };
91e22acd
AS		 13413 const int v4t_plus_v6_m[] =
13414 {
13415 -1, /* PRE_V4. */
13416 -1, /* V4. */
13417 T(V4T), /* V4T. */
13418 T(V5T), /* V5T. */
13419 T(V5TE), /* V5TE. */
13420 T(V5TEJ), /* V5TEJ. */
13421 T(V6), /* V6. */
13422 T(V6KZ), /* V6KZ. */
13423 T(V6T2), /* V6T2. */
13424 T(V6K), /* V6K. */
13425 T(V7), /* V7. */
13426 T(V6_M), /* V6_M. */
13427 T(V6S_M), /* V6S_M. */
9e3c6df6 13428 T(V7E_M), /* V7E_M. */
bca38921 13429 T(V8), /* V8. */
bff0500d 13430 -1, /* V8R. */
2fd158eb
TP		 13431 T(V8M_BASE), /* V8-M BASELINE. */
13432 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 13433 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
13434 };
13435 const int *comb[] =
13436 {
13437 v6t2,
13438 v6k,
13439 v7,
13440 v6_m,
13441 v6s_m,
9e3c6df6 13442 v7e_m,
bca38921 13443 v8,
bff0500d 13444 v8r,
2fd158eb
TP		 13445 v8m_baseline,
13446 v8m_mainline,
91e22acd
AS		 13447 /* Pseudo-architecture. */
13448 v4t_plus_v6_m
13449 };
13450
13451 /* Check we've not got a higher architecture than we know about. */
13452
9e3c6df6 13453 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 13454 {
90b6238f 13455 _bfd_error_handler (_("error: %pB: unknown CPU architecture"), ibfd);
91e22acd
AS		 13456 return -1;
13457 }
13458
13459 /* Override old tag if we have a Tag_also_compatible_with on the output. */
13460
13461 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
13462 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
13463 oldtag = T(V4T_PLUS_V6_M);
13464
13465 /* And override the new tag if we have a Tag_also_compatible_with on the
13466 input. */
13467
13468 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
13469 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
13470 newtag = T(V4T_PLUS_V6_M);
13471
13472 tagl = (oldtag < newtag) ? oldtag : newtag;
13473 result = tagh = (oldtag > newtag) ? oldtag : newtag;
13474
13475 /* Architectures before V6KZ add features monotonically. */
13476 if (tagh <= TAG_CPU_ARCH_V6KZ)
13477 return result;
13478
4ed7ed8d 13479 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 13480
13481 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
13482 as the canonical version. */
13483 if (result == T(V4T_PLUS_V6_M))
13484 {
13485 result = T(V4T);
13486 *secondary_compat_out = T(V6_M);
13487 }
13488 else
13489 *secondary_compat_out = -1;
13490
13491 if (result == -1)
13492 {
90b6238f 13493 _bfd_error_handler (_("error: %pB: conflicting CPU architectures %d/%d"),
91e22acd
AS		 13494 ibfd, oldtag, newtag);
13495 return -1;
13496 }
13497
13498 return result;
13499#undef T
8e79c3df
CM		 13500}
13501
ac56ee8f
MGD		 13502/* Query attributes object to see if integer divide instructions may be
13503 present in an object. */
13504static bfd_boolean
13505elf32_arm_attributes_accept_div (const obj_attribute *attr)
13506{
13507 int arch = attr[Tag_CPU_arch].i;
13508 int profile = attr[Tag_CPU_arch_profile].i;
13509
13510 switch (attr[Tag_DIV_use].i)
13511 {
13512 case 0:
13513 /* Integer divide allowed if instruction contained in archetecture. */
13514 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
13515 return TRUE;
13516 else if (arch >= TAG_CPU_ARCH_V7E_M)
13517 return TRUE;
13518 else
13519 return FALSE;
13520
13521 case 1:
13522 /* Integer divide explicitly prohibited. */
13523 return FALSE;
13524
13525 default:
13526 /* Unrecognised case - treat as allowing divide everywhere. */
13527 case 2:
13528 /* Integer divide allowed in ARM state. */
13529 return TRUE;
13530 }
13531}
13532
13533/* Query attributes object to see if integer divide instructions are
13534 forbidden to be in the object. This is not the inverse of
13535 elf32_arm_attributes_accept_div. */
13536static bfd_boolean
13537elf32_arm_attributes_forbid_div (const obj_attribute *attr)
13538{
13539 return attr[Tag_DIV_use].i == 1;
13540}
13541
ee065d83
PB		 13542/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
13543 are conflicting attributes. */
906e58ca 13544
ee065d83 13545static bfd_boolean
50e03d47 13546elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
ee065d83 13547{
50e03d47 13548 bfd *obfd = info->output_bfd;
104d59d1
JM		 13549 obj_attribute *in_attr;
13550 obj_attribute *out_attr;
ee065d83
PB		 13551 /* Some tags have 0 = don't care, 1 = strong requirement,
13552 2 = weak requirement. */
91e22acd 13553 static const int order_021[3] = {0, 2, 1};
ee065d83 13554 int i;
91e22acd 13555 bfd_boolean result = TRUE;
9274e9de 13556 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 13557
3e6b1042
DJ		 13558 /* Skip the linker stubs file. This preserves previous behavior
13559 of accepting unknown attributes in the first input file - but
13560 is that a bug? */
13561 if (ibfd->flags & BFD_LINKER_CREATED)
13562 return TRUE;
13563
9274e9de
TG		 13564 /* Skip any input that hasn't attribute section.
13565 This enables to link object files without attribute section with
13566 any others. */
13567 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
13568 return TRUE;
13569
104d59d1 13570 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 13571 {
13572 /* This is the first object. Copy the attributes. */
104d59d1 13573 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 13574
cd21e546
MGD		 13575 out_attr = elf_known_obj_attributes_proc (obfd);
13576
004ae526
PB		 13577 /* Use the Tag_null value to indicate the attributes have been
13578 initialized. */
cd21e546 13579 out_attr[0].i = 1;
004ae526 13580
cd21e546
MGD		 13581 /* We do not output objects with Tag_MPextension_use_legacy - we move
13582 the attribute's value to Tag_MPextension_use. */
13583 if (out_attr[Tag_MPextension_use_legacy].i != 0)
13584 {
13585 if (out_attr[Tag_MPextension_use].i != 0
13586 && out_attr[Tag_MPextension_use_legacy].i
99059e56 13587 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 13588 {
13589 _bfd_error_handler
871b3ab2 13590 (_("Error: %pB has both the current and legacy "
cd21e546
MGD		 13591 "Tag_MPextension_use attributes"), ibfd);
13592 result = FALSE;
13593 }
13594
13595 out_attr[Tag_MPextension_use] =
13596 out_attr[Tag_MPextension_use_legacy];
13597 out_attr[Tag_MPextension_use_legacy].type = 0;
13598 out_attr[Tag_MPextension_use_legacy].i = 0;
13599 }
13600
13601 return result;
ee065d83
PB		 13602 }
13603
104d59d1
JM		 13604 in_attr = elf_known_obj_attributes_proc (ibfd);
13605 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 13606 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
13607 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
13608 {
5c294fee
TG		 13609 /* Ignore mismatches if the object doesn't use floating point or is
13610 floating point ABI independent. */
13611 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
13612 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13613 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 13614 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 13615 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
13616 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 13617 {
13618 _bfd_error_handler
871b3ab2 13619 (_("error: %pB uses VFP register arguments, %pB does not"),
deddc40b
NS		 13620 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
13621 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 13622 result = FALSE;
ee065d83
PB		 13623 }
13624 }
13625
3de4a297 13626 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 13627 {
13628 /* Merge this attribute with existing attributes. */
13629 switch (i)
13630 {
13631 case Tag_CPU_raw_name:
13632 case Tag_CPU_name:
6a631e86 13633 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 13634 break;
13635
13636 case Tag_ABI_optimization_goals:
13637 case Tag_ABI_FP_optimization_goals:
13638 /* Use the first value seen. */
13639 break;
13640
13641 case Tag_CPU_arch:
91e22acd
AS		 13642 {
13643 int secondary_compat = -1, secondary_compat_out = -1;
13644 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 13645 int arch_attr;
13646 static const char *name_table[] =
13647 {
91e22acd
AS		 13648 /* These aren't real CPU names, but we can't guess
13649 that from the architecture version alone. */
13650 "Pre v4",
13651 "ARM v4",
13652 "ARM v4T",
13653 "ARM v5T",
13654 "ARM v5TE",
13655 "ARM v5TEJ",
13656 "ARM v6",
13657 "ARM v6KZ",
13658 "ARM v6T2",
13659 "ARM v6K",
13660 "ARM v7",
13661 "ARM v6-M",
bca38921 13662 "ARM v6S-M",
2fd158eb
TP		 13663 "ARM v8",
13664 "",
13665 "ARM v8-M.baseline",
13666 "ARM v8-M.mainline",
91e22acd
AS		 13667 };
13668
13669 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
13670 secondary_compat = get_secondary_compatible_arch (ibfd);
13671 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 13672 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
13673 &secondary_compat_out,
13674 in_attr[i].i,
13675 secondary_compat);
13676
13677 /* Return with error if failed to merge. */
13678 if (arch_attr == -1)
13679 return FALSE;
13680
13681 out_attr[i].i = arch_attr;
13682
91e22acd
AS		 13683 set_secondary_compatible_arch (obfd, secondary_compat_out);
13684
13685 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
13686 if (out_attr[i].i == saved_out_attr)
13687 ; /* Leave the names alone. */
13688 else if (out_attr[i].i == in_attr[i].i)
13689 {
13690 /* The output architecture has been changed to match the
13691 input architecture. Use the input names. */
13692 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
13693 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
13694 : NULL;
13695 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
13696 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
13697 : NULL;
13698 }
13699 else
13700 {
13701 out_attr[Tag_CPU_name].s = NULL;
13702 out_attr[Tag_CPU_raw_name].s = NULL;
13703 }
13704
13705 /* If we still don't have a value for Tag_CPU_name,
13706 make one up now. Tag_CPU_raw_name remains blank. */
13707 if (out_attr[Tag_CPU_name].s == NULL
13708 && out_attr[i].i < ARRAY_SIZE (name_table))
13709 out_attr[Tag_CPU_name].s =
13710 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
13711 }
13712 break;
13713
ee065d83
PB		 13714 case Tag_ARM_ISA_use:
13715 case Tag_THUMB_ISA_use:
ee065d83 13716 case Tag_WMMX_arch:
91e22acd
AS		 13717 case Tag_Advanced_SIMD_arch:
13718 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 13719 case Tag_ABI_FP_rounding:
ee065d83
PB		 13720 case Tag_ABI_FP_exceptions:
13721 case Tag_ABI_FP_user_exceptions:
13722 case Tag_ABI_FP_number_model:
75375b3e 13723 case Tag_FP_HP_extension:
91e22acd
AS		 13724 case Tag_CPU_unaligned_access:
13725 case Tag_T2EE_use:
91e22acd 13726 case Tag_MPextension_use:
ee065d83
PB		 13727 /* Use the largest value specified. */
13728 if (in_attr[i].i > out_attr[i].i)
13729 out_attr[i].i = in_attr[i].i;
13730 break;
13731
75375b3e 13732 case Tag_ABI_align_preserved:
91e22acd
AS		 13733 case Tag_ABI_PCS_RO_data:
13734 /* Use the smallest value specified. */
13735 if (in_attr[i].i < out_attr[i].i)
13736 out_attr[i].i = in_attr[i].i;
13737 break;
13738
75375b3e 13739 case Tag_ABI_align_needed:
91e22acd 13740 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 13741 && (in_attr[Tag_ABI_align_preserved].i == 0
13742 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 13743 {
91e22acd
AS		 13744 /* This error message should be enabled once all non-conformant
13745 binaries in the toolchain have had the attributes set
13746 properly.
ee065d83 13747 _bfd_error_handler
871b3ab2 13748 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
91e22acd
AS		 13749 obfd, ibfd);
13750 result = FALSE; */
ee065d83 13751 }
91e22acd
AS		 13752 /* Fall through. */
13753 case Tag_ABI_FP_denormal:
13754 case Tag_ABI_PCS_GOT_use:
13755 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
13756 value if greater than 2 (for future-proofing). */
13757 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
13758 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
13759 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 13760 out_attr[i].i = in_attr[i].i;
13761 break;
91e22acd 13762
75375b3e
MGD		 13763 case Tag_Virtualization_use:
13764 /* The virtualization tag effectively stores two bits of
13765 information: the intended use of TrustZone (in bit 0), and the
13766 intended use of Virtualization (in bit 1). */
13767 if (out_attr[i].i == 0)
13768 out_attr[i].i = in_attr[i].i;
13769 else if (in_attr[i].i != 0
13770 && in_attr[i].i != out_attr[i].i)
13771 {
13772 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
13773 out_attr[i].i = 3;
13774 else
13775 {
13776 _bfd_error_handler
871b3ab2
AM		 13777 (_("error: %pB: unable to merge virtualization attributes "
13778 "with %pB"),
75375b3e
MGD		 13779 obfd, ibfd);
13780 result = FALSE;
13781 }
13782 }
13783 break;
91e22acd
AS		 13784
13785 case Tag_CPU_arch_profile:
13786 if (out_attr[i].i != in_attr[i].i)
13787 {
13788 /* 0 will merge with anything.
13789 'A' and 'S' merge to 'A'.
13790 'R' and 'S' merge to 'R'.
99059e56 13791 'M' and 'A|R|S' is an error. */
91e22acd
AS		 13792 if (out_attr[i].i == 0
13793 || (out_attr[i].i == 'S'
13794 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
13795 out_attr[i].i = in_attr[i].i;
13796 else if (in_attr[i].i == 0
13797 || (in_attr[i].i == 'S'
13798 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 13799 ; /* Do nothing. */
91e22acd
AS		 13800 else
13801 {
13802 _bfd_error_handler
90b6238f 13803 (_("error: %pB: conflicting architecture profiles %c/%c"),
91e22acd
AS		 13804 ibfd,
13805 in_attr[i].i ? in_attr[i].i : '0',
13806 out_attr[i].i ? out_attr[i].i : '0');
13807 result = FALSE;
13808 }
13809 }
13810 break;
15afaa63
TP		 13811
13812 case Tag_DSP_extension:
13813 /* No need to change output value if any of:
13814 - pre (<=) ARMv5T input architecture (do not have DSP)
13815 - M input profile not ARMv7E-M and do not have DSP. */
13816 if (in_attr[Tag_CPU_arch].i <= 3
13817 || (in_attr[Tag_CPU_arch_profile].i == 'M'
13818 && in_attr[Tag_CPU_arch].i != 13
13819 && in_attr[i].i == 0))
13820 ; /* Do nothing. */
13821 /* Output value should be 0 if DSP part of architecture, ie.
13822 - post (>=) ARMv5te architecture output
13823 - A, R or S profile output or ARMv7E-M output architecture. */
13824 else if (out_attr[Tag_CPU_arch].i >= 4
13825 && (out_attr[Tag_CPU_arch_profile].i == 'A'
13826 || out_attr[Tag_CPU_arch_profile].i == 'R'
13827 || out_attr[Tag_CPU_arch_profile].i == 'S'
13828 || out_attr[Tag_CPU_arch].i == 13))
13829 out_attr[i].i = 0;
13830 /* Otherwise, DSP instructions are added and not part of output
13831 architecture. */
13832 else
13833 out_attr[i].i = 1;
13834 break;
13835
75375b3e 13836 case Tag_FP_arch:
62f3b8c8 13837 {
4547cb56
NC		 13838 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
13839 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
13840 when it's 0. It might mean absence of FP hardware if
99654aaf 13841 Tag_FP_arch is zero. */
4547cb56 13842
a715796b 13843#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 13844 static const struct
13845 {
13846 int ver;
13847 int regs;
bca38921 13848 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 13849 {
13850 {0, 0},
13851 {1, 16},
13852 {2, 16},
13853 {3, 32},
13854 {3, 16},
13855 {4, 32},
bca38921 13856 {4, 16},
a715796b
TG		 13857 {8, 32},
13858 {8, 16}
62f3b8c8
PB		 13859 };
13860 int ver;
13861 int regs;
13862 int newval;
13863
4547cb56
NC		 13864 /* If the output has no requirement about FP hardware,
13865 follow the requirement of the input. */
13866 if (out_attr[i].i == 0)
13867 {
4ec192e6
RE		 13868 /* This assert is still reasonable, we shouldn't
13869 produce the suspicious build attribute
13870 combination (See below for in_attr). */
4547cb56
NC		 13871 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
13872 out_attr[i].i = in_attr[i].i;
13873 out_attr[Tag_ABI_HardFP_use].i
13874 = in_attr[Tag_ABI_HardFP_use].i;
13875 break;
13876 }
13877 /* If the input has no requirement about FP hardware, do
13878 nothing. */
13879 else if (in_attr[i].i == 0)
13880 {
4ec192e6
RE		 13881 /* We used to assert that Tag_ABI_HardFP_use was
13882 zero here, but we should never assert when
13883 consuming an object file that has suspicious
13884 build attributes. The single precision variant
13885 of 'no FP architecture' is still 'no FP
13886 architecture', so we just ignore the tag in this
13887 case. */
4547cb56
NC		 13888 break;
13889 }
13890
13891 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 13892 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 13893
13894 /* If both the input and the output have zero Tag_ABI_HardFP_use,
13895 do nothing. */
13896 if (in_attr[Tag_ABI_HardFP_use].i == 0
13897 && out_attr[Tag_ABI_HardFP_use].i == 0)
13898 ;
13899 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 13900 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 13901 else if (in_attr[Tag_ABI_HardFP_use].i
13902 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 13903 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 13904
13905 /* Now we can handle Tag_FP_arch. */
13906
bca38921
MGD		 13907 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
13908 pick the biggest. */
13909 if (in_attr[i].i >= VFP_VERSION_COUNT
13910 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 13911 {
13912 out_attr[i] = in_attr[i];
13913 break;
13914 }
13915 /* The output uses the superset of input features
13916 (ISA version) and registers. */
13917 ver = vfp_versions[in_attr[i].i].ver;
13918 if (ver < vfp_versions[out_attr[i].i].ver)
13919 ver = vfp_versions[out_attr[i].i].ver;
13920 regs = vfp_versions[in_attr[i].i].regs;
13921 if (regs < vfp_versions[out_attr[i].i].regs)
13922 regs = vfp_versions[out_attr[i].i].regs;
13923 /* This assumes all possible supersets are also a valid
99059e56 13924 options. */
bca38921 13925 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 13926 {
13927 if (regs == vfp_versions[newval].regs
13928 && ver == vfp_versions[newval].ver)
13929 break;
13930 }
13931 out_attr[i].i = newval;
13932 }
b1cc4aeb 13933 break;
ee065d83
PB		 13934 case Tag_PCS_config:
13935 if (out_attr[i].i == 0)
13936 out_attr[i].i = in_attr[i].i;
b6009aca 13937 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 13938 {
13939 /* It's sometimes ok to mix different configs, so this is only
99059e56 13940 a warning. */
ee065d83 13941 _bfd_error_handler
90b6238f 13942 (_("warning: %pB: conflicting platform configuration"), ibfd);
ee065d83
PB		 13943 }
13944 break;
13945 case Tag_ABI_PCS_R9_use:
004ae526
PB		 13946 if (in_attr[i].i != out_attr[i].i
13947 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 13948 && in_attr[i].i != AEABI_R9_unused)
13949 {
13950 _bfd_error_handler
90b6238f 13951 (_("error: %pB: conflicting use of R9"), ibfd);
91e22acd 13952 result = FALSE;
ee065d83
PB		 13953 }
13954 if (out_attr[i].i == AEABI_R9_unused)
13955 out_attr[i].i = in_attr[i].i;
13956 break;
13957 case Tag_ABI_PCS_RW_data:
13958 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
13959 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
13960 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
13961 {
13962 _bfd_error_handler
871b3ab2 13963 (_("error: %pB: SB relative addressing conflicts with use of R9"),
ee065d83 13964 ibfd);
91e22acd 13965 result = FALSE;
ee065d83
PB		 13966 }
13967 /* Use the smallest value specified. */
13968 if (in_attr[i].i < out_attr[i].i)
13969 out_attr[i].i = in_attr[i].i;
13970 break;
ee065d83 13971 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 13972 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
13973 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 13974 {
13975 _bfd_error_handler
871b3ab2 13976 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
a9dc9481 13977 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 13978 }
a9dc9481 13979 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 13980 out_attr[i].i = in_attr[i].i;
13981 break;
ee065d83
PB		 13982 case Tag_ABI_enum_size:
13983 if (in_attr[i].i != AEABI_enum_unused)
13984 {
13985 if (out_attr[i].i == AEABI_enum_unused
13986 || out_attr[i].i == AEABI_enum_forced_wide)
13987 {
13988 /* The existing object is compatible with anything.
13989 Use whatever requirements the new object has. */
13990 out_attr[i].i = in_attr[i].i;
13991 }
13992 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 13993 && out_attr[i].i != in_attr[i].i
0ffa91dd 13994 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 13995 {
91e22acd 13996 static const char *aeabi_enum_names[] =
bf21ed78 13997 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 13998 const char *in_name =
13999 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14000 ? aeabi_enum_names[in_attr[i].i]
14001 : "<unknown>";
14002 const char *out_name =
14003 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
14004 ? aeabi_enum_names[out_attr[i].i]
14005 : "<unknown>";
ee065d83 14006 _bfd_error_handler
871b3ab2 14007 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 14008 ibfd, in_name, out_name);
ee065d83
PB		 14009 }
14010 }
14011 break;
14012 case Tag_ABI_VFP_args:
14013 /* Aready done. */
14014 break;
14015 case Tag_ABI_WMMX_args:
14016 if (in_attr[i].i != out_attr[i].i)
14017 {
14018 _bfd_error_handler
871b3ab2 14019 (_("error: %pB uses iWMMXt register arguments, %pB does not"),
ee065d83 14020 ibfd, obfd);
91e22acd 14021 result = FALSE;
ee065d83
PB		 14022 }
14023 break;
7b86a9fa
AS		 14024 case Tag_compatibility:
14025 /* Merged in target-independent code. */
14026 break;
91e22acd 14027 case Tag_ABI_HardFP_use:
4547cb56 14028 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 14029 break;
14030 case Tag_ABI_FP_16bit_format:
14031 if (in_attr[i].i != 0 && out_attr[i].i != 0)
14032 {
14033 if (in_attr[i].i != out_attr[i].i)
14034 {
14035 _bfd_error_handler
871b3ab2 14036 (_("error: fp16 format mismatch between %pB and %pB"),
91e22acd
AS		 14037 ibfd, obfd);
14038 result = FALSE;
14039 }
14040 }
14041 if (in_attr[i].i != 0)
14042 out_attr[i].i = in_attr[i].i;
14043 break;
7b86a9fa 14044
cd21e546 14045 case Tag_DIV_use:
ac56ee8f
MGD		 14046 /* A value of zero on input means that the divide instruction may
14047 be used if available in the base architecture as specified via
14048 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
14049 the user did not want divide instructions. A value of 2
14050 explicitly means that divide instructions were allowed in ARM
14051 and Thumb state. */
14052 if (in_attr[i].i == out_attr[i].i)
14053 /* Do nothing. */ ;
14054 else if (elf32_arm_attributes_forbid_div (in_attr)
14055 && !elf32_arm_attributes_accept_div (out_attr))
14056 out_attr[i].i = 1;
14057 else if (elf32_arm_attributes_forbid_div (out_attr)
14058 && elf32_arm_attributes_accept_div (in_attr))
14059 out_attr[i].i = in_attr[i].i;
14060 else if (in_attr[i].i == 2)
14061 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 14062 break;
14063
14064 case Tag_MPextension_use_legacy:
14065 /* We don't output objects with Tag_MPextension_use_legacy - we
14066 move the value to Tag_MPextension_use. */
14067 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
14068 {
14069 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
14070 {
14071 _bfd_error_handler
871b3ab2 14072 (_("%pB has both the current and legacy "
b38cadfb 14073 "Tag_MPextension_use attributes"),
cd21e546
MGD		 14074 ibfd);
14075 result = FALSE;
14076 }
14077 }
14078
14079 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
14080 out_attr[Tag_MPextension_use] = in_attr[i];
14081
14082 break;
14083
91e22acd 14084 case Tag_nodefaults:
2d0bb761
AS		 14085 /* This tag is set if it exists, but the value is unused (and is
14086 typically zero). We don't actually need to do anything here -
14087 the merge happens automatically when the type flags are merged
14088 below. */
91e22acd
AS		 14089 break;
14090 case Tag_also_compatible_with:
14091 /* Already done in Tag_CPU_arch. */
14092 break;
14093 case Tag_conformance:
14094 /* Keep the attribute if it matches. Throw it away otherwise.
14095 No attribute means no claim to conform. */
14096 if (!in_attr[i].s || !out_attr[i].s
14097 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
14098 out_attr[i].s = NULL;
14099 break;
3cfad14c 14100
91e22acd 14101 default:
e8b36cd1
JM		 14102 result
14103 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 14104 }
14105
14106 /* If out_attr was copied from in_attr then it won't have a type yet. */
14107 if (in_attr[i].type && !out_attr[i].type)
14108 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 14109 }
14110
104d59d1 14111 /* Merge Tag_compatibility attributes and any common GNU ones. */
50e03d47 14112 if (!_bfd_elf_merge_object_attributes (ibfd, info))
5488d830 14113 return FALSE;
ee065d83 14114
104d59d1 14115 /* Check for any attributes not known on ARM. */
e8b36cd1 14116 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 14117
91e22acd 14118 return result;
252b5132
RH		 14119}
14120
3a4a14e9
PB		 14121
14122/* Return TRUE if the two EABI versions are incompatible. */
14123
14124static bfd_boolean
14125elf32_arm_versions_compatible (unsigned iver, unsigned over)
14126{
14127 /* v4 and v5 are the same spec before and after it was released,
14128 so allow mixing them. */
14129 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
14130 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
14131 return TRUE;
14132
14133 return (iver == over);
14134}
14135
252b5132
RH		 14136/* Merge backend specific data from an object file to the output
14137 object file when linking. */
9b485d32 14138
b34976b6 14139static bfd_boolean
50e03d47 14140elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
252b5132 14141
9b485d32
NC		 14142/* Display the flags field. */
14143
b34976b6 14144static bfd_boolean
57e8b36a 14145elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 14146{
fc830a83
NC		 14147 FILE * file = (FILE *) ptr;
14148 unsigned long flags;
252b5132
RH		 14149
14150 BFD_ASSERT (abfd != NULL && ptr != NULL);
14151
14152 /* Print normal ELF private data. */
14153 _bfd_elf_print_private_bfd_data (abfd, ptr);
14154
fc830a83 14155 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 14156 /* Ignore init flag - it may not be set, despite the flags field
14157 containing valid data. */
252b5132 14158
9b485d32 14159 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 14160
fc830a83
NC		 14161 switch (EF_ARM_EABI_VERSION (flags))
14162 {
14163 case EF_ARM_EABI_UNKNOWN:
4cc11e76 14164 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 14165 official ARM ELF extended ABI. Hence they are only decoded if
14166 the EABI version is not set. */
fd2ec330 14167 if (flags & EF_ARM_INTERWORK)
9b485d32 14168 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 14169
fd2ec330 14170 if (flags & EF_ARM_APCS_26)
6c571f00 14171 fprintf (file, " [APCS-26]");
fc830a83 14172 else
6c571f00 14173 fprintf (file, " [APCS-32]");
9a5aca8c 14174
96a846ea
RE		 14175 if (flags & EF_ARM_VFP_FLOAT)
14176 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 14177 else if (flags & EF_ARM_MAVERICK_FLOAT)
14178 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 14179 else
14180 fprintf (file, _(" [FPA float format]"));
14181
fd2ec330 14182 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 14183 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 14184
fd2ec330 14185 if (flags & EF_ARM_PIC)
9b485d32 14186 fprintf (file, _(" [position independent]"));
fc830a83 14187
fd2ec330 14188 if (flags & EF_ARM_NEW_ABI)
9b485d32 14189 fprintf (file, _(" [new ABI]"));
9a5aca8c 14190
fd2ec330 14191 if (flags & EF_ARM_OLD_ABI)
9b485d32 14192 fprintf (file, _(" [old ABI]"));
9a5aca8c 14193
fd2ec330 14194 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 14195 fprintf (file, _(" [software FP]"));
9a5aca8c 14196
96a846ea
RE		 14197 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
14198 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 14199 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
14200 | EF_ARM_MAVERICK_FLOAT);
fc830a83 14201 break;
9a5aca8c 14202
fc830a83 14203 case EF_ARM_EABI_VER1:
9b485d32 14204 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 14205
fc830a83 14206 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 14207 fprintf (file, _(" [sorted symbol table]"));
fc830a83 14208 else
9b485d32 14209 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 14210
fc830a83
NC		 14211 flags &= ~ EF_ARM_SYMSARESORTED;
14212 break;
9a5aca8c 14213
fd2ec330
PB		 14214 case EF_ARM_EABI_VER2:
14215 fprintf (file, _(" [Version2 EABI]"));
14216
14217 if (flags & EF_ARM_SYMSARESORTED)
14218 fprintf (file, _(" [sorted symbol table]"));
14219 else
14220 fprintf (file, _(" [unsorted symbol table]"));
14221
14222 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
14223 fprintf (file, _(" [dynamic symbols use segment index]"));
14224
14225 if (flags & EF_ARM_MAPSYMSFIRST)
14226 fprintf (file, _(" [mapping symbols precede others]"));
14227
99e4ae17 14228 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 14229 | EF_ARM_MAPSYMSFIRST);
14230 break;
14231
d507cf36
PB		 14232 case EF_ARM_EABI_VER3:
14233 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 14234 break;
14235
14236 case EF_ARM_EABI_VER4:
14237 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 14238 goto eabi;
d507cf36 14239
3a4a14e9
PB		 14240 case EF_ARM_EABI_VER5:
14241 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 14242
14243 if (flags & EF_ARM_ABI_FLOAT_SOFT)
14244 fprintf (file, _(" [soft-float ABI]"));
14245
14246 if (flags & EF_ARM_ABI_FLOAT_HARD)
14247 fprintf (file, _(" [hard-float ABI]"));
14248
14249 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
14250
3a4a14e9 14251 eabi:
d507cf36
PB		 14252 if (flags & EF_ARM_BE8)
14253 fprintf (file, _(" [BE8]"));
14254
14255 if (flags & EF_ARM_LE8)
14256 fprintf (file, _(" [LE8]"));
14257
14258 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
14259 break;
14260
fc830a83 14261 default:
9b485d32 14262 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 14263 break;
14264 }
252b5132 14265
fc830a83 14266 flags &= ~ EF_ARM_EABIMASK;
252b5132 14267
fc830a83 14268 if (flags & EF_ARM_RELEXEC)
9b485d32 14269 fprintf (file, _(" [relocatable executable]"));
252b5132 14270
a5721edd 14271 flags &= ~EF_ARM_RELEXEC;
fc830a83
NC		 14272
14273 if (flags)
9b485d32 14274 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 14275
252b5132
RH		 14276 fputc ('\n', file);
14277
b34976b6 14278 return TRUE;
252b5132
RH		 14279}
14280
14281static int
57e8b36a 14282elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 14283{
2f0ca46a
NC		 14284 switch (ELF_ST_TYPE (elf_sym->st_info))
14285 {
14286 case STT_ARM_TFUNC:
14287 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 14288
2f0ca46a
NC		 14289 case STT_ARM_16BIT:
14290 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
14291 This allows us to distinguish between data used by Thumb instructions
14292 and non-data (which is probably code) inside Thumb regions of an
14293 executable. */
1a0eb693 14294 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 14295 return ELF_ST_TYPE (elf_sym->st_info);
14296 break;
9a5aca8c 14297
ce855c42
NC		 14298 default:
14299 break;
2f0ca46a
NC		 14300 }
14301
14302 return type;
252b5132 14303}
f21f3fe0 14304
252b5132 14305static asection *
07adf181
AM		 14306elf32_arm_gc_mark_hook (asection *sec,
14307 struct bfd_link_info *info,
14308 Elf_Internal_Rela *rel,
14309 struct elf_link_hash_entry *h,
14310 Elf_Internal_Sym *sym)
252b5132
RH		 14311{
14312 if (h != NULL)
07adf181 14313 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 14314 {
14315 case R_ARM_GNU_VTINHERIT:
14316 case R_ARM_GNU_VTENTRY:
07adf181
AM		 14317 return NULL;
14318 }
9ad5cbcf 14319
07adf181 14320 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 14321}
14322
780a67af
NC		 14323/* Look through the relocs for a section during the first phase. */
14324
b34976b6 14325static bfd_boolean
57e8b36a
NC		 14326elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
14327 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 14328{
b34976b6
AM		 14329 Elf_Internal_Shdr *symtab_hdr;
14330 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 14331 const Elf_Internal_Rela *rel;
14332 const Elf_Internal_Rela *rel_end;
14333 bfd *dynobj;
5e681ec4 14334 asection *sreloc;
5e681ec4 14335 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 14336 bfd_boolean call_reloc_p;
14337 bfd_boolean may_become_dynamic_p;
14338 bfd_boolean may_need_local_target_p;
ce98a316 14339 unsigned long nsyms;
9a5aca8c 14340
0e1862bb 14341 if (bfd_link_relocatable (info))
b34976b6 14342 return TRUE;
9a5aca8c 14343
0ffa91dd
NC		 14344 BFD_ASSERT (is_arm_elf (abfd));
14345
5e681ec4 14346 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14347 if (htab == NULL)
14348 return FALSE;
14349
5e681ec4 14350 sreloc = NULL;
9a5aca8c 14351
67687978
PB		 14352 /* Create dynamic sections for relocatable executables so that we can
14353 copy relocations. */
14354 if (htab->root.is_relocatable_executable
14355 && ! htab->root.dynamic_sections_created)
14356 {
14357 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
14358 return FALSE;
14359 }
14360
cbc704f3
RS		 14361 if (htab->root.dynobj == NULL)
14362 htab->root.dynobj = abfd;
34e77a92
RS		 14363 if (!create_ifunc_sections (info))
14364 return FALSE;
cbc704f3
RS		 14365
14366 dynobj = htab->root.dynobj;
14367
0ffa91dd 14368 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 14369 sym_hashes = elf_sym_hashes (abfd);
ce98a316 14370 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 14371
252b5132
RH		 14372 rel_end = relocs + sec->reloc_count;
14373 for (rel = relocs; rel < rel_end; rel++)
14374 {
34e77a92 14375 Elf_Internal_Sym *isym;
252b5132 14376 struct elf_link_hash_entry *h;
b7693d02 14377 struct elf32_arm_link_hash_entry *eh;
d42c267e 14378 unsigned int r_symndx;
eb043451 14379 int r_type;
9a5aca8c 14380
252b5132 14381 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 14382 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 14383 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 14384
ce98a316
NC		 14385 if (r_symndx >= nsyms
14386 /* PR 9934: It is possible to have relocations that do not
14387 refer to symbols, thus it is also possible to have an
14388 object file containing relocations but no symbol table. */
cf35638d 14389 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac 14390 {
871b3ab2 14391 _bfd_error_handler (_("%pB: bad symbol index: %d"), abfd,
4eca0228 14392 r_symndx);
ba93b8ac
DJ		 14393 return FALSE;
14394 }
14395
34e77a92
RS		 14396 h = NULL;
14397 isym = NULL;
14398 if (nsyms > 0)
973a3492 14399 {
34e77a92
RS		 14400 if (r_symndx < symtab_hdr->sh_info)
14401 {
14402 /* A local symbol. */
14403 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
14404 abfd, r_symndx);
14405 if (isym == NULL)
14406 return FALSE;
14407 }
14408 else
14409 {
14410 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
14411 while (h->root.type == bfd_link_hash_indirect
14412 || h->root.type == bfd_link_hash_warning)
14413 h = (struct elf_link_hash_entry *) h->root.u.i.link;
14414 }
973a3492 14415 }
9a5aca8c 14416
b7693d02
DJ		 14417 eh = (struct elf32_arm_link_hash_entry *) h;
14418
f6e32f6d
RS		 14419 call_reloc_p = FALSE;
14420 may_become_dynamic_p = FALSE;
14421 may_need_local_target_p = FALSE;
14422
0855e32b
NS		 14423 /* Could be done earlier, if h were already available. */
14424 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 14425 switch (r_type)
99059e56 14426 {
5e681ec4 14427 case R_ARM_GOT32:
eb043451 14428 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 14429 case R_ARM_TLS_GD32:
14430 case R_ARM_TLS_IE32:
0855e32b
NS		 14431 case R_ARM_TLS_GOTDESC:
14432 case R_ARM_TLS_DESCSEQ:
14433 case R_ARM_THM_TLS_DESCSEQ:
14434 case R_ARM_TLS_CALL:
14435 case R_ARM_THM_TLS_CALL:
5e681ec4 14436 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 14437 {
14438 int tls_type, old_tls_type;
5e681ec4 14439
ba93b8ac
DJ		 14440 switch (r_type)
14441 {
14442 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 14443
ba93b8ac 14444 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 14445
0855e32b
NS		 14446 case R_ARM_TLS_GOTDESC:
14447 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
14448 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
14449 tls_type = GOT_TLS_GDESC; break;
b38cadfb 14450
ba93b8ac
DJ		 14451 default: tls_type = GOT_NORMAL; break;
14452 }
252b5132 14453
0e1862bb 14454 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 14455 info->flags |= DF_STATIC_TLS;
14456
ba93b8ac
DJ		 14457 if (h != NULL)
14458 {
14459 h->got.refcount++;
14460 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
14461 }
14462 else
14463 {
ba93b8ac 14464 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 14465 if (!elf32_arm_allocate_local_sym_info (abfd))
14466 return FALSE;
14467 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 14468 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
14469 }
14470
0855e32b 14471 /* If a variable is accessed with both tls methods, two
99059e56 14472 slots may be created. */
0855e32b
NS		 14473 if (GOT_TLS_GD_ANY_P (old_tls_type)
14474 && GOT_TLS_GD_ANY_P (tls_type))
14475 tls_type |= old_tls_type;
14476
14477 /* We will already have issued an error message if there
14478 is a TLS/non-TLS mismatch, based on the symbol
14479 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 14480 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
14481 && tls_type != GOT_NORMAL)
14482 tls_type |= old_tls_type;
14483
0855e32b 14484 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 14485 method, we're able to relax. Turn off the GDESC flag,
14486 without messing up with any other kind of tls types
6a631e86 14487 that may be involved. */
0855e32b
NS		 14488 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
14489 tls_type &= ~GOT_TLS_GDESC;
14490
ba93b8ac
DJ		 14491 if (old_tls_type != tls_type)
14492 {
14493 if (h != NULL)
14494 elf32_arm_hash_entry (h)->tls_type = tls_type;
14495 else
14496 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
14497 }
14498 }
8029a119 14499 /* Fall through. */
ba93b8ac
DJ		 14500
14501 case R_ARM_TLS_LDM32:
14502 if (r_type == R_ARM_TLS_LDM32)
14503 htab->tls_ldm_got.refcount++;
8029a119 14504 /* Fall through. */
252b5132 14505
c19d1205 14506 case R_ARM_GOTOFF32:
5e681ec4 14507 case R_ARM_GOTPC:
cbc704f3
RS		 14508 if (htab->root.sgot == NULL
14509 && !create_got_section (htab->root.dynobj, info))
14510 return FALSE;
252b5132
RH		 14511 break;
14512
252b5132 14513 case R_ARM_PC24:
7359ea65 14514 case R_ARM_PLT32:
5b5bb741
PB		 14515 case R_ARM_CALL:
14516 case R_ARM_JUMP24:
eb043451 14517 case R_ARM_PREL31:
c19d1205 14518 case R_ARM_THM_CALL:
bd97cb95
DJ		 14519 case R_ARM_THM_JUMP24:
14520 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 14521 call_reloc_p = TRUE;
14522 may_need_local_target_p = TRUE;
14523 break;
14524
14525 case R_ARM_ABS12:
14526 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
14527 ldr __GOTT_INDEX__ offsets. */
14528 if (!htab->vxworks_p)
14529 {
14530 may_need_local_target_p = TRUE;
14531 break;
14532 }
aebf9be7 14533 else goto jump_over;
9eaff861 14534
f6e32f6d 14535 /* Fall through. */
39623e12 14536
96c23d59
JM		 14537 case R_ARM_MOVW_ABS_NC:
14538 case R_ARM_MOVT_ABS:
14539 case R_ARM_THM_MOVW_ABS_NC:
14540 case R_ARM_THM_MOVT_ABS:
0e1862bb 14541 if (bfd_link_pic (info))
96c23d59 14542 {
4eca0228 14543 _bfd_error_handler
871b3ab2 14544 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
96c23d59
JM		 14545 abfd, elf32_arm_howto_table_1[r_type].name,
14546 (h) ? h->root.root.string : "a local symbol");
14547 bfd_set_error (bfd_error_bad_value);
14548 return FALSE;
14549 }
14550
14551 /* Fall through. */
39623e12
PB		 14552 case R_ARM_ABS32:
14553 case R_ARM_ABS32_NOI:
aebf9be7 14554 jump_over:
0e1862bb 14555 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 14556 {
14557 h->pointer_equality_needed = 1;
14558 }
14559 /* Fall through. */
39623e12
PB		 14560 case R_ARM_REL32:
14561 case R_ARM_REL32_NOI:
b6895b4f
PB		 14562 case R_ARM_MOVW_PREL_NC:
14563 case R_ARM_MOVT_PREL:
b6895b4f
PB		 14564 case R_ARM_THM_MOVW_PREL_NC:
14565 case R_ARM_THM_MOVT_PREL:
39623e12 14566
b7693d02 14567 /* Should the interworking branches be listed here? */
0e1862bb 14568 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 14569 && (sec->flags & SEC_ALLOC) != 0)
14570 {
14571 if (h == NULL
469a3493 14572 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 14573 {
14574 /* In shared libraries and relocatable executables,
14575 we treat local relative references as calls;
14576 see the related SYMBOL_CALLS_LOCAL code in
14577 allocate_dynrelocs. */
14578 call_reloc_p = TRUE;
14579 may_need_local_target_p = TRUE;
14580 }
14581 else
14582 /* We are creating a shared library or relocatable
14583 executable, and this is a reloc against a global symbol,
14584 or a non-PC-relative reloc against a local symbol.
14585 We may need to copy the reloc into the output. */
14586 may_become_dynamic_p = TRUE;
14587 }
f6e32f6d
RS		 14588 else
14589 may_need_local_target_p = TRUE;
252b5132
RH		 14590 break;
14591
99059e56
RM		 14592 /* This relocation describes the C++ object vtable hierarchy.
14593 Reconstruct it for later use during GC. */
14594 case R_ARM_GNU_VTINHERIT:
14595 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
14596 return FALSE;
14597 break;
14598
14599 /* This relocation describes which C++ vtable entries are actually
14600 used. Record for later use during GC. */
14601 case R_ARM_GNU_VTENTRY:
14602 BFD_ASSERT (h != NULL);
14603 if (h != NULL
14604 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
14605 return FALSE;
14606 break;
14607 }
f6e32f6d
RS		 14608
14609 if (h != NULL)
14610 {
14611 if (call_reloc_p)
14612 /* We may need a .plt entry if the function this reloc
14613 refers to is in a different object, regardless of the
14614 symbol's type. We can't tell for sure yet, because
14615 something later might force the symbol local. */
14616 h->needs_plt = 1;
14617 else if (may_need_local_target_p)
14618 /* If this reloc is in a read-only section, we might
14619 need a copy reloc. We can't check reliably at this
14620 stage whether the section is read-only, as input
14621 sections have not yet been mapped to output sections.
14622 Tentatively set the flag for now, and correct in
14623 adjust_dynamic_symbol. */
14624 h->non_got_ref = 1;
14625 }
14626
34e77a92
RS		 14627 if (may_need_local_target_p
14628 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 14629 {
34e77a92
RS		 14630 union gotplt_union *root_plt;
14631 struct arm_plt_info *arm_plt;
14632 struct arm_local_iplt_info *local_iplt;
14633
14634 if (h != NULL)
14635 {
14636 root_plt = &h->plt;
14637 arm_plt = &eh->plt;
14638 }
14639 else
14640 {
14641 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
14642 if (local_iplt == NULL)
14643 return FALSE;
14644 root_plt = &local_iplt->root;
14645 arm_plt = &local_iplt->arm;
14646 }
14647
f6e32f6d
RS		 14648 /* If the symbol is a function that doesn't bind locally,
14649 this relocation will need a PLT entry. */
a8c887dd
NC		 14650 if (root_plt->refcount != -1)
14651 root_plt->refcount += 1;
34e77a92
RS		 14652
14653 if (!call_reloc_p)
14654 arm_plt->noncall_refcount++;
f6e32f6d
RS		 14655
14656 /* It's too early to use htab->use_blx here, so we have to
14657 record possible blx references separately from
14658 relocs that definitely need a thumb stub. */
14659
14660 if (r_type == R_ARM_THM_CALL)
34e77a92 14661 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 14662
14663 if (r_type == R_ARM_THM_JUMP24
14664 || r_type == R_ARM_THM_JUMP19)
34e77a92 14665 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 14666 }
14667
14668 if (may_become_dynamic_p)
14669 {
14670 struct elf_dyn_relocs *p, **head;
14671
14672 /* Create a reloc section in dynobj. */
14673 if (sreloc == NULL)
14674 {
14675 sreloc = _bfd_elf_make_dynamic_reloc_section
14676 (sec, dynobj, 2, abfd, ! htab->use_rel);
14677
14678 if (sreloc == NULL)
14679 return FALSE;
14680
14681 /* BPABI objects never have dynamic relocations mapped. */
14682 if (htab->symbian_p)
14683 {
14684 flagword flags;
14685
14686 flags = bfd_get_section_flags (dynobj, sreloc);
14687 flags &= ~(SEC_LOAD | SEC_ALLOC);
14688 bfd_set_section_flags (dynobj, sreloc, flags);
14689 }
14690 }
14691
14692 /* If this is a global symbol, count the number of
14693 relocations we need for this symbol. */
14694 if (h != NULL)
14695 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
14696 else
14697 {
34e77a92
RS		 14698 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14699 if (head == NULL)
f6e32f6d 14700 return FALSE;
f6e32f6d
RS		 14701 }
14702
14703 p = *head;
14704 if (p == NULL || p->sec != sec)
14705 {
14706 bfd_size_type amt = sizeof *p;
14707
14708 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
14709 if (p == NULL)
14710 return FALSE;
14711 p->next = *head;
14712 *head = p;
14713 p->sec = sec;
14714 p->count = 0;
14715 p->pc_count = 0;
14716 }
14717
469a3493 14718 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 14719 p->pc_count += 1;
14720 p->count += 1;
14721 }
252b5132 14722 }
f21f3fe0 14723
b34976b6 14724 return TRUE;
252b5132
RH		 14725}
14726
9eaff861
AO		 14727static void
14728elf32_arm_update_relocs (asection *o,
14729 struct bfd_elf_section_reloc_data *reldata)
14730{
14731 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
14732 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
14733 const struct elf_backend_data *bed;
14734 _arm_elf_section_data *eado;
14735 struct bfd_link_order *p;
14736 bfd_byte *erela_head, *erela;
14737 Elf_Internal_Rela *irela_head, *irela;
14738 Elf_Internal_Shdr *rel_hdr;
14739 bfd *abfd;
14740 unsigned int count;
14741
14742 eado = get_arm_elf_section_data (o);
14743
14744 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
14745 return;
14746
14747 abfd = o->owner;
14748 bed = get_elf_backend_data (abfd);
14749 rel_hdr = reldata->hdr;
14750
14751 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
14752 {
14753 swap_in = bed->s->swap_reloc_in;
14754 swap_out = bed->s->swap_reloc_out;
14755 }
14756 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
14757 {
14758 swap_in = bed->s->swap_reloca_in;
14759 swap_out = bed->s->swap_reloca_out;
14760 }
14761 else
14762 abort ();
14763
14764 erela_head = rel_hdr->contents;
14765 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
14766 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
14767
14768 erela = erela_head;
14769 irela = irela_head;
14770 count = 0;
14771
14772 for (p = o->map_head.link_order; p; p = p->next)
14773 {
14774 if (p->type == bfd_section_reloc_link_order
14775 || p->type == bfd_symbol_reloc_link_order)
14776 {
14777 (*swap_in) (abfd, erela, irela);
14778 erela += rel_hdr->sh_entsize;
14779 irela++;
14780 count++;
14781 }
14782 else if (p->type == bfd_indirect_link_order)
14783 {
14784 struct bfd_elf_section_reloc_data *input_reldata;
14785 arm_unwind_table_edit *edit_list, *edit_tail;
14786 _arm_elf_section_data *eadi;
14787 bfd_size_type j;
14788 bfd_vma offset;
14789 asection *i;
14790
14791 i = p->u.indirect.section;
14792
14793 eadi = get_arm_elf_section_data (i);
14794 edit_list = eadi->u.exidx.unwind_edit_list;
14795 edit_tail = eadi->u.exidx.unwind_edit_tail;
14796 offset = o->vma + i->output_offset;
14797
14798 if (eadi->elf.rel.hdr &&
14799 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
14800 input_reldata = &eadi->elf.rel;
14801 else if (eadi->elf.rela.hdr &&
14802 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
14803 input_reldata = &eadi->elf.rela;
14804 else
14805 abort ();
14806
14807 if (edit_list)
14808 {
14809 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
14810 {
14811 arm_unwind_table_edit *edit_node, *edit_next;
14812 bfd_vma bias;
c48182bf 14813 bfd_vma reloc_index;
9eaff861
AO		 14814
14815 (*swap_in) (abfd, erela, irela);
c48182bf 14816 reloc_index = (irela->r_offset - offset) / 8;
9eaff861
AO		 14817
14818 bias = 0;
14819 edit_node = edit_list;
14820 for (edit_next = edit_list;
c48182bf 14821 edit_next && edit_next->index <= reloc_index;
9eaff861
AO		 14822 edit_next = edit_node->next)
14823 {
14824 bias++;
14825 edit_node = edit_next;
14826 }
14827
14828 if (edit_node->type != DELETE_EXIDX_ENTRY
c48182bf 14829 || edit_node->index != reloc_index)
9eaff861
AO		 14830 {
14831 irela->r_offset -= bias * 8;
14832 irela++;
14833 count++;
14834 }
14835
14836 erela += rel_hdr->sh_entsize;
14837 }
14838
14839 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
14840 {
14841 /* New relocation entity. */
14842 asection *text_sec = edit_tail->linked_section;
14843 asection *text_out = text_sec->output_section;
14844 bfd_vma exidx_offset = offset + i->size - 8;
14845
14846 irela->r_addend = 0;
14847 irela->r_offset = exidx_offset;
14848 irela->r_info = ELF32_R_INFO
14849 (text_out->target_index, R_ARM_PREL31);
14850 irela++;
14851 count++;
14852 }
14853 }
14854 else
14855 {
14856 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
14857 {
14858 (*swap_in) (abfd, erela, irela);
14859 erela += rel_hdr->sh_entsize;
14860 irela++;
14861 }
14862
14863 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
14864 }
14865 }
14866 }
14867
14868 reldata->count = count;
14869 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
14870
14871 erela = erela_head;
14872 irela = irela_head;
14873 while (count > 0)
14874 {
14875 (*swap_out) (abfd, irela, erela);
14876 erela += rel_hdr->sh_entsize;
14877 irela++;
14878 count--;
14879 }
14880
14881 free (irela_head);
14882
14883 /* Hashes are no longer valid. */
14884 free (reldata->hashes);
14885 reldata->hashes = NULL;
14886}
14887
6a5bb875 14888/* Unwinding tables are not referenced directly. This pass marks them as
4ba2ef8f
TP		 14889 required if the corresponding code section is marked. Similarly, ARMv8-M
14890 secure entry functions can only be referenced by SG veneers which are
14891 created after the GC process. They need to be marked in case they reside in
14892 their own section (as would be the case if code was compiled with
14893 -ffunction-sections). */
6a5bb875
PB		 14894
14895static bfd_boolean
906e58ca
NC		 14896elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
14897 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 14898{
14899 bfd *sub;
14900 Elf_Internal_Shdr **elf_shdrp;
4ba2ef8f
TP		 14901 asection *cmse_sec;
14902 obj_attribute *out_attr;
14903 Elf_Internal_Shdr *symtab_hdr;
14904 unsigned i, sym_count, ext_start;
14905 const struct elf_backend_data *bed;
14906 struct elf_link_hash_entry **sym_hashes;
14907 struct elf32_arm_link_hash_entry *cmse_hash;
14908 bfd_boolean again, is_v8m, first_bfd_browse = TRUE;
6a5bb875 14909
7f6ab9f8
AM		 14910 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
14911
4ba2ef8f
TP		 14912 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
14913 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
14914 && out_attr[Tag_CPU_arch_profile].i == 'M';
14915
6a5bb875
PB		 14916 /* Marking EH data may cause additional code sections to be marked,
14917 requiring multiple passes. */
14918 again = TRUE;
14919 while (again)
14920 {
14921 again = FALSE;
c72f2fb2 14922 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 14923 {
14924 asection *o;
14925
0ffa91dd 14926 if (! is_arm_elf (sub))
6a5bb875
PB		 14927 continue;
14928
14929 elf_shdrp = elf_elfsections (sub);
14930 for (o = sub->sections; o != NULL; o = o->next)
14931 {
14932 Elf_Internal_Shdr *hdr;
0ffa91dd 14933
6a5bb875 14934 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 14935 if (hdr->sh_type == SHT_ARM_EXIDX
14936 && hdr->sh_link
14937 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 14938 && !o->gc_mark
14939 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
14940 {
14941 again = TRUE;
14942 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
14943 return FALSE;
14944 }
14945 }
4ba2ef8f
TP		 14946
14947 /* Mark section holding ARMv8-M secure entry functions. We mark all
14948 of them so no need for a second browsing. */
14949 if (is_v8m && first_bfd_browse)
14950 {
14951 sym_hashes = elf_sym_hashes (sub);
14952 bed = get_elf_backend_data (sub);
14953 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
14954 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
14955 ext_start = symtab_hdr->sh_info;
14956
14957 /* Scan symbols. */
14958 for (i = ext_start; i < sym_count; i++)
14959 {
14960 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
14961
14962 /* Assume it is a special symbol. If not, cmse_scan will
14963 warn about it and user can do something about it. */
14964 if (ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
14965 {
14966 cmse_sec = cmse_hash->root.root.u.def.section;
5025eb7c
AO		 14967 if (!cmse_sec->gc_mark
14968 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
4ba2ef8f
TP		 14969 return FALSE;
14970 }
14971 }
14972 }
6a5bb875 14973 }
4ba2ef8f 14974 first_bfd_browse = FALSE;
6a5bb875
PB		 14975 }
14976
14977 return TRUE;
14978}
14979
3c9458e9
NC		 14980/* Treat mapping symbols as special target symbols. */
14981
14982static bfd_boolean
14983elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
14984{
b0796911
PB		 14985 return bfd_is_arm_special_symbol_name (sym->name,
14986 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 14987}
14988
0367ecfb
NC		 14989/* This is a copy of elf_find_function() from elf.c except that
14990 ARM mapping symbols are ignored when looking for function names
14991 and STT_ARM_TFUNC is considered to a function type. */
252b5132 14992
0367ecfb 14993static bfd_boolean
07d6d2b8 14994arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 14995 asymbol ** symbols,
fb167eb2 14996 asection * section,
07d6d2b8 14997 bfd_vma offset,
0367ecfb
NC		 14998 const char ** filename_ptr,
14999 const char ** functionname_ptr)
15000{
15001 const char * filename = NULL;
15002 asymbol * func = NULL;
15003 bfd_vma low_func = 0;
15004 asymbol ** p;
252b5132
RH		 15005
15006 for (p = symbols; *p != NULL; p++)
15007 {
15008 elf_symbol_type *q;
15009
15010 q = (elf_symbol_type *) *p;
15011
252b5132
RH		 15012 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
15013 {
15014 default:
15015 break;
15016 case STT_FILE:
15017 filename = bfd_asymbol_name (&q->symbol);
15018 break;
252b5132
RH		 15019 case STT_FUNC:
15020 case STT_ARM_TFUNC:
9d2da7ca 15021 case STT_NOTYPE:
b0796911 15022 /* Skip mapping symbols. */
0367ecfb 15023 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 15024 && bfd_is_arm_special_symbol_name (q->symbol.name,
15025 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 15026 continue;
15027 /* Fall through. */
6b40fcba 15028 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 15029 && q->symbol.value >= low_func
15030 && q->symbol.value <= offset)
15031 {
15032 func = (asymbol *) q;
15033 low_func = q->symbol.value;
15034 }
15035 break;
15036 }
15037 }
15038
15039 if (func == NULL)
b34976b6 15040 return FALSE;
252b5132 15041
0367ecfb
NC		 15042 if (filename_ptr)
15043 *filename_ptr = filename;
15044 if (functionname_ptr)
15045 *functionname_ptr = bfd_asymbol_name (func);
15046
15047 return TRUE;
906e58ca 15048}
0367ecfb
NC		 15049
15050
15051/* Find the nearest line to a particular section and offset, for error
15052 reporting. This code is a duplicate of the code in elf.c, except
15053 that it uses arm_elf_find_function. */
15054
15055static bfd_boolean
07d6d2b8
AM		 15056elf32_arm_find_nearest_line (bfd * abfd,
15057 asymbol ** symbols,
15058 asection * section,
15059 bfd_vma offset,
0367ecfb
NC		 15060 const char ** filename_ptr,
15061 const char ** functionname_ptr,
fb167eb2
AM		 15062 unsigned int * line_ptr,
15063 unsigned int * discriminator_ptr)
0367ecfb
NC		 15064{
15065 bfd_boolean found = FALSE;
15066
fb167eb2 15067 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 15068 filename_ptr, functionname_ptr,
fb167eb2
AM		 15069 line_ptr, discriminator_ptr,
15070 dwarf_debug_sections, 0,
0367ecfb
NC		 15071 & elf_tdata (abfd)->dwarf2_find_line_info))
15072 {
15073 if (!*functionname_ptr)
fb167eb2 15074 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15075 *filename_ptr ? NULL : filename_ptr,
15076 functionname_ptr);
f21f3fe0 15077
0367ecfb
NC		 15078 return TRUE;
15079 }
15080
fb167eb2
AM		 15081 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
15082 uses DWARF1. */
15083
0367ecfb
NC		 15084 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
15085 & found, filename_ptr,
15086 functionname_ptr, line_ptr,
15087 & elf_tdata (abfd)->line_info))
15088 return FALSE;
15089
15090 if (found && (*functionname_ptr || *line_ptr))
15091 return TRUE;
15092
15093 if (symbols == NULL)
15094 return FALSE;
15095
fb167eb2 15096 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 15097 filename_ptr, functionname_ptr))
15098 return FALSE;
15099
15100 *line_ptr = 0;
b34976b6 15101 return TRUE;
252b5132
RH		 15102}
15103
4ab527b0 15104static bfd_boolean
07d6d2b8 15105elf32_arm_find_inliner_info (bfd * abfd,
4ab527b0
FF		 15106 const char ** filename_ptr,
15107 const char ** functionname_ptr,
15108 unsigned int * line_ptr)
15109{
15110 bfd_boolean found;
15111 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
15112 functionname_ptr, line_ptr,
15113 & elf_tdata (abfd)->dwarf2_find_line_info);
15114 return found;
15115}
15116
63c1f59d
AM		 15117/* Find dynamic relocs for H that apply to read-only sections. */
15118
15119static asection *
15120readonly_dynrelocs (struct elf_link_hash_entry *h)
15121{
15122 struct elf_dyn_relocs *p;
15123
15124 for (p = elf32_arm_hash_entry (h)->dyn_relocs; p != NULL; p = p->next)
15125 {
15126 asection *s = p->sec->output_section;
15127
15128 if (s != NULL && (s->flags & SEC_READONLY) != 0)
15129 return p->sec;
15130 }
15131 return NULL;
15132}
15133
252b5132
RH		 15134/* Adjust a symbol defined by a dynamic object and referenced by a
15135 regular object. The current definition is in some section of the
15136 dynamic object, but we're not including those sections. We have to
15137 change the definition to something the rest of the link can
15138 understand. */
15139
b34976b6 15140static bfd_boolean
57e8b36a
NC		 15141elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
15142 struct elf_link_hash_entry * h)
252b5132
RH		 15143{
15144 bfd * dynobj;
5474d94f 15145 asection *s, *srel;
b7693d02 15146 struct elf32_arm_link_hash_entry * eh;
67687978 15147 struct elf32_arm_link_hash_table *globals;
252b5132 15148
67687978 15149 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15150 if (globals == NULL)
15151 return FALSE;
15152
252b5132
RH		 15153 dynobj = elf_hash_table (info)->dynobj;
15154
15155 /* Make sure we know what is going on here. */
15156 BFD_ASSERT (dynobj != NULL
f5385ebf 15157 && (h->needs_plt
34e77a92 15158 || h->type == STT_GNU_IFUNC
60d67dc8 15159 || h->is_weakalias
f5385ebf
AM		 15160 || (h->def_dynamic
15161 && h->ref_regular
15162 && !h->def_regular)));
252b5132 15163
b7693d02
DJ		 15164 eh = (struct elf32_arm_link_hash_entry *) h;
15165
252b5132
RH		 15166 /* If this is a function, put it in the procedure linkage table. We
15167 will fill in the contents of the procedure linkage table later,
15168 when we know the address of the .got section. */
34e77a92 15169 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 15170 {
34e77a92
RS		 15171 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
15172 symbol binds locally. */
5e681ec4 15173 if (h->plt.refcount <= 0
34e77a92
RS		 15174 || (h->type != STT_GNU_IFUNC
15175 && (SYMBOL_CALLS_LOCAL (info, h)
15176 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
15177 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 15178 {
15179 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 15180 file, but the symbol was never referred to by a dynamic
15181 object, or if all references were garbage collected. In
15182 such a case, we don't actually need to build a procedure
15183 linkage table, and we can just do a PC24 reloc instead. */
15184 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15185 eh->plt.thumb_refcount = 0;
15186 eh->plt.maybe_thumb_refcount = 0;
15187 eh->plt.noncall_refcount = 0;
f5385ebf 15188 h->needs_plt = 0;
252b5132
RH		 15189 }
15190
b34976b6 15191 return TRUE;
252b5132 15192 }
5e681ec4 15193 else
b7693d02
DJ		 15194 {
15195 /* It's possible that we incorrectly decided a .plt reloc was
15196 needed for an R_ARM_PC24 or similar reloc to a non-function sym
15197 in check_relocs. We can't decide accurately between function
15198 and non-function syms in check-relocs; Objects loaded later in
15199 the link may change h->type. So fix it now. */
15200 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 15201 eh->plt.thumb_refcount = 0;
15202 eh->plt.maybe_thumb_refcount = 0;
15203 eh->plt.noncall_refcount = 0;
b7693d02 15204 }
252b5132
RH		 15205
15206 /* If this is a weak symbol, and there is a real definition, the
15207 processor independent code will have arranged for us to see the
15208 real definition first, and we can just use the same value. */
60d67dc8 15209 if (h->is_weakalias)
252b5132 15210 {
60d67dc8
AM		 15211 struct elf_link_hash_entry *def = weakdef (h);
15212 BFD_ASSERT (def->root.type == bfd_link_hash_defined);
15213 h->root.u.def.section = def->root.u.def.section;
15214 h->root.u.def.value = def->root.u.def.value;
b34976b6 15215 return TRUE;
252b5132
RH		 15216 }
15217
ba93b8ac
DJ		 15218 /* If there are no non-GOT references, we do not need a copy
15219 relocation. */
15220 if (!h->non_got_ref)
15221 return TRUE;
15222
252b5132
RH		 15223 /* This is a reference to a symbol defined by a dynamic object which
15224 is not a function. */
15225
15226 /* If we are creating a shared library, we must presume that the
15227 only references to the symbol are via the global offset table.
15228 For such cases we need not do anything here; the relocations will
67687978
PB		 15229 be handled correctly by relocate_section. Relocatable executables
15230 can reference data in shared objects directly, so we don't need to
15231 do anything here. */
0e1862bb 15232 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 15233 return TRUE;
252b5132
RH		 15234
15235 /* We must allocate the symbol in our .dynbss section, which will
15236 become part of the .bss section of the executable. There will be
15237 an entry for this symbol in the .dynsym section. The dynamic
15238 object will contain position independent code, so all references
15239 from the dynamic object to this symbol will go through the global
15240 offset table. The dynamic linker will use the .dynsym entry to
15241 determine the address it must put in the global offset table, so
15242 both the dynamic object and the regular object will refer to the
15243 same memory location for the variable. */
5522f910
NC		 15244 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
15245 linker to copy the initial value out of the dynamic object and into
15246 the runtime process image. We need to remember the offset into the
00a97672 15247 .rel(a).bss section we are going to use. */
5474d94f
AM		 15248 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
15249 {
15250 s = globals->root.sdynrelro;
15251 srel = globals->root.sreldynrelro;
15252 }
15253 else
15254 {
15255 s = globals->root.sdynbss;
15256 srel = globals->root.srelbss;
15257 }
5522f910
NC		 15258 if (info->nocopyreloc == 0
15259 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 15260 && h->size != 0)
252b5132 15261 {
47beaa6a 15262 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 15263 h->needs_copy = 1;
252b5132
RH		 15264 }
15265
6cabe1ea 15266 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 15267}
15268
5e681ec4
PB		 15269/* Allocate space in .plt, .got and associated reloc sections for
15270 dynamic relocs. */
15271
15272static bfd_boolean
47beaa6a 15273allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 15274{
15275 struct bfd_link_info *info;
15276 struct elf32_arm_link_hash_table *htab;
15277 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 15278 struct elf_dyn_relocs *p;
5e681ec4
PB		 15279
15280 if (h->root.type == bfd_link_hash_indirect)
15281 return TRUE;
15282
e6a6bb22
AM		 15283 eh = (struct elf32_arm_link_hash_entry *) h;
15284
5e681ec4
PB		 15285 info = (struct bfd_link_info *) inf;
15286 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15287 if (htab == NULL)
15288 return FALSE;
5e681ec4 15289
34e77a92 15290 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 15291 && h->plt.refcount > 0)
15292 {
15293 /* Make sure this symbol is output as a dynamic symbol.
15294 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 15295 if (h->dynindx == -1 && !h->forced_local
15296 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 15297 {
c152c796 15298 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15299 return FALSE;
15300 }
15301
34e77a92
RS		 15302 /* If the call in the PLT entry binds locally, the associated
15303 GOT entry should use an R_ARM_IRELATIVE relocation instead of
15304 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
15305 than the .plt section. */
15306 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
15307 {
15308 eh->is_iplt = 1;
15309 if (eh->plt.noncall_refcount == 0
15310 && SYMBOL_REFERENCES_LOCAL (info, h))
15311 /* All non-call references can be resolved directly.
15312 This means that they can (and in some cases, must)
15313 resolve directly to the run-time target, rather than
15314 to the PLT. That in turns means that any .got entry
15315 would be equal to the .igot.plt entry, so there's
15316 no point having both. */
15317 h->got.refcount = 0;
15318 }
15319
0e1862bb 15320 if (bfd_link_pic (info)
34e77a92 15321 || eh->is_iplt
7359ea65 15322 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 15323 {
34e77a92 15324 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 15325
5e681ec4
PB		 15326 /* If this symbol is not defined in a regular file, and we are
15327 not generating a shared library, then set the symbol to this
15328 location in the .plt. This is required to make function
15329 pointers compare as equal between the normal executable and
15330 the shared library. */
0e1862bb 15331 if (! bfd_link_pic (info)
f5385ebf 15332 && !h->def_regular)
5e681ec4 15333 {
34e77a92 15334 h->root.u.def.section = htab->root.splt;
5e681ec4 15335 h->root.u.def.value = h->plt.offset;
5e681ec4 15336
67d74e43
DJ		 15337 /* Make sure the function is not marked as Thumb, in case
15338 it is the target of an ABS32 relocation, which will
15339 point to the PLT entry. */
39d911fc 15340 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 15341 }
022f8312 15342
00a97672
RS		 15343 /* VxWorks executables have a second set of relocations for
15344 each PLT entry. They go in a separate relocation section,
15345 which is processed by the kernel loader. */
0e1862bb 15346 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 15347 {
15348 /* There is a relocation for the initial PLT entry:
15349 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
15350 if (h->plt.offset == htab->plt_header_size)
47beaa6a 15351 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 15352
15353 /* There are two extra relocations for each subsequent
15354 PLT entry: an R_ARM_32 relocation for the GOT entry,
15355 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 15356 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 15357 }
5e681ec4
PB		 15358 }
15359 else
15360 {
15361 h->plt.offset = (bfd_vma) -1;
f5385ebf 15362 h->needs_plt = 0;
5e681ec4
PB		 15363 }
15364 }
15365 else
15366 {
15367 h->plt.offset = (bfd_vma) -1;
f5385ebf 15368 h->needs_plt = 0;
5e681ec4
PB		 15369 }
15370
0855e32b
NS		 15371 eh = (struct elf32_arm_link_hash_entry *) h;
15372 eh->tlsdesc_got = (bfd_vma) -1;
15373
5e681ec4
PB		 15374 if (h->got.refcount > 0)
15375 {
15376 asection *s;
15377 bfd_boolean dyn;
ba93b8ac
DJ		 15378 int tls_type = elf32_arm_hash_entry (h)->tls_type;
15379 int indx;
5e681ec4
PB		 15380
15381 /* Make sure this symbol is output as a dynamic symbol.
15382 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 15383 if (h->dynindx == -1 && !h->forced_local
15384 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 15385 {
c152c796 15386 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15387 return FALSE;
15388 }
15389
e5a52504
MM		 15390 if (!htab->symbian_p)
15391 {
362d30a1 15392 s = htab->root.sgot;
e5a52504 15393 h->got.offset = s->size;
ba93b8ac
DJ		 15394
15395 if (tls_type == GOT_UNKNOWN)
15396 abort ();
15397
15398 if (tls_type == GOT_NORMAL)
15399 /* Non-TLS symbols need one GOT slot. */
15400 s->size += 4;
15401 else
15402 {
99059e56
RM		 15403 if (tls_type & GOT_TLS_GDESC)
15404 {
0855e32b 15405 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 15406 eh->tlsdesc_got
0855e32b
NS		 15407 = (htab->root.sgotplt->size
15408 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 15409 htab->root.sgotplt->size += 8;
15410 h->got.offset = (bfd_vma) -2;
34e77a92 15411 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15412 reloc in the middle of .got.plt. */
99059e56
RM		 15413 htab->num_tls_desc++;
15414 }
0855e32b 15415
ba93b8ac 15416 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 15417 {
15418 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
15419 the symbol is both GD and GDESC, got.offset may
15420 have been overwritten. */
15421 h->got.offset = s->size;
15422 s->size += 8;
15423 }
15424
ba93b8ac
DJ		 15425 if (tls_type & GOT_TLS_IE)
15426 /* R_ARM_TLS_IE32 needs one GOT slot. */
15427 s->size += 4;
15428 }
15429
e5a52504 15430 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 15431
15432 indx = 0;
0e1862bb
L		 15433 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
15434 bfd_link_pic (info),
15435 h)
15436 && (!bfd_link_pic (info)
ba93b8ac
DJ		 15437 || !SYMBOL_REFERENCES_LOCAL (info, h)))
15438 indx = h->dynindx;
15439
15440 if (tls_type != GOT_NORMAL
0e1862bb 15441 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 15442 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15443 || h->root.type != bfd_link_hash_undefweak))
15444 {
15445 if (tls_type & GOT_TLS_IE)
47beaa6a 15446 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 15447
15448 if (tls_type & GOT_TLS_GD)
47beaa6a 15449 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15450
b38cadfb 15451 if (tls_type & GOT_TLS_GDESC)
0855e32b 15452 {
47beaa6a 15453 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 15454 /* GDESC needs a trampoline to jump to. */
15455 htab->tls_trampoline = -1;
15456 }
15457
15458 /* Only GD needs it. GDESC just emits one relocation per
15459 2 entries. */
b38cadfb 15460 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 15461 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 15462 }
6f820c85 15463 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 15464 {
15465 if (htab->root.dynamic_sections_created)
15466 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
15467 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
15468 }
34e77a92
RS		 15469 else if (h->type == STT_GNU_IFUNC
15470 && eh->plt.noncall_refcount == 0)
15471 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
15472 they all resolve dynamically instead. Reserve room for the
15473 GOT entry's R_ARM_IRELATIVE relocation. */
15474 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 15475 else if (bfd_link_pic (info)
15476 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
15477 || h->root.type != bfd_link_hash_undefweak))
b436d854 15478 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 15479 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 15480 }
5e681ec4
PB		 15481 }
15482 else
15483 h->got.offset = (bfd_vma) -1;
15484
a4fd1a8e
PB		 15485 /* Allocate stubs for exported Thumb functions on v4t. */
15486 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 15487 && h->def_regular
39d911fc 15488 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 15489 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
15490 {
15491 struct elf_link_hash_entry * th;
15492 struct bfd_link_hash_entry * bh;
15493 struct elf_link_hash_entry * myh;
15494 char name[1024];
15495 asection *s;
15496 bh = NULL;
15497 /* Create a new symbol to regist the real location of the function. */
15498 s = h->root.u.def.section;
906e58ca 15499 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 15500 _bfd_generic_link_add_one_symbol (info, s->owner,
15501 name, BSF_GLOBAL, s,
15502 h->root.u.def.value,
15503 NULL, TRUE, FALSE, &bh);
15504
15505 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 15506 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 15507 myh->forced_local = 1;
39d911fc 15508 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 15509 eh->export_glue = myh;
15510 th = record_arm_to_thumb_glue (info, h);
15511 /* Point the symbol at the stub. */
15512 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 15513 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 15514 h->root.u.def.section = th->root.u.def.section;
15515 h->root.u.def.value = th->root.u.def.value & ~1;
15516 }
15517
0bdcacaf 15518 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 15519 return TRUE;
15520
15521 /* In the shared -Bsymbolic case, discard space allocated for
15522 dynamic pc-relative relocs against symbols which turn out to be
15523 defined in regular objects. For the normal shared case, discard
15524 space for pc-relative relocs that have become local due to symbol
15525 visibility changes. */
15526
0e1862bb 15527 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 15528 {
469a3493
RM		 15529 /* Relocs that use pc_count are PC-relative forms, which will appear
15530 on something like ".long foo - ." or "movw REG, foo - .". We want
15531 calls to protected symbols to resolve directly to the function
15532 rather than going via the plt. If people want function pointer
15533 comparisons to work as expected then they should avoid writing
15534 assembly like ".long foo - .". */
ba93b8ac
DJ		 15535 if (SYMBOL_CALLS_LOCAL (info, h))
15536 {
0bdcacaf 15537 struct elf_dyn_relocs **pp;
ba93b8ac 15538
0bdcacaf 15539 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 15540 {
15541 p->count -= p->pc_count;
15542 p->pc_count = 0;
15543 if (p->count == 0)
15544 *pp = p->next;
15545 else
15546 pp = &p->next;
15547 }
15548 }
15549
4dfe6ac6 15550 if (htab->vxworks_p)
3348747a 15551 {
0bdcacaf 15552 struct elf_dyn_relocs **pp;
3348747a 15553
0bdcacaf 15554 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 15555 {
0bdcacaf 15556 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 15557 *pp = p->next;
15558 else
15559 pp = &p->next;
15560 }
15561 }
15562
ba93b8ac 15563 /* Also discard relocs on undefined weak syms with non-default
99059e56 15564 visibility. */
0bdcacaf 15565 if (eh->dyn_relocs != NULL
5e681ec4 15566 && h->root.type == bfd_link_hash_undefweak)
22d606e9 15567 {
95b03e4a
L		 15568 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
15569 || UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
0bdcacaf 15570 eh->dyn_relocs = NULL;
22d606e9
AM		 15571
15572 /* Make sure undefined weak symbols are output as a dynamic
15573 symbol in PIEs. */
15574 else if (h->dynindx == -1
15575 && !h->forced_local)
15576 {
15577 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15578 return FALSE;
15579 }
15580 }
15581
67687978
PB		 15582 else if (htab->root.is_relocatable_executable && h->dynindx == -1
15583 && h->root.type == bfd_link_hash_new)
15584 {
15585 /* Output absolute symbols so that we can create relocations
15586 against them. For normal symbols we output a relocation
15587 against the section that contains them. */
15588 if (! bfd_elf_link_record_dynamic_symbol (info, h))
15589 return FALSE;
15590 }
15591
5e681ec4
PB		 15592 }
15593 else
15594 {
15595 /* For the non-shared case, discard space for relocs against
15596 symbols which turn out to need copy relocs or are not
15597 dynamic. */
15598
f5385ebf
AM		 15599 if (!h->non_got_ref
15600 && ((h->def_dynamic
15601 && !h->def_regular)
5e681ec4
PB		 15602 || (htab->root.dynamic_sections_created
15603 && (h->root.type == bfd_link_hash_undefweak
15604 || h->root.type == bfd_link_hash_undefined))))
15605 {
15606 /* Make sure this symbol is output as a dynamic symbol.
15607 Undefined weak syms won't yet be marked as dynamic. */
6c699715
RL		 15608 if (h->dynindx == -1 && !h->forced_local
15609 && h->root.type == bfd_link_hash_undefweak)
5e681ec4 15610 {
c152c796 15611 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 15612 return FALSE;
15613 }
15614
15615 /* If that succeeded, we know we'll be keeping all the
15616 relocs. */
15617 if (h->dynindx != -1)
15618 goto keep;
15619 }
15620
0bdcacaf 15621 eh->dyn_relocs = NULL;
5e681ec4
PB		 15622
15623 keep: ;
15624 }
15625
15626 /* Finally, allocate space. */
0bdcacaf 15627 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 15628 {
0bdcacaf 15629 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 15630 if (h->type == STT_GNU_IFUNC
15631 && eh->plt.noncall_refcount == 0
15632 && SYMBOL_REFERENCES_LOCAL (info, h))
15633 elf32_arm_allocate_irelocs (info, sreloc, p->count);
15634 else
15635 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 15636 }
15637
15638 return TRUE;
15639}
15640
63c1f59d
AM		 15641/* Set DF_TEXTREL if we find any dynamic relocs that apply to
15642 read-only sections. */
08d1f311
DJ		 15643
15644static bfd_boolean
63c1f59d 15645maybe_set_textrel (struct elf_link_hash_entry *h, void *info_p)
08d1f311 15646{
63c1f59d 15647 asection *sec;
08d1f311 15648
63c1f59d
AM		 15649 if (h->root.type == bfd_link_hash_indirect)
15650 return TRUE;
08d1f311 15651
63c1f59d
AM		 15652 sec = readonly_dynrelocs (h);
15653 if (sec != NULL)
15654 {
15655 struct bfd_link_info *info = (struct bfd_link_info *) info_p;
08d1f311 15656
63c1f59d
AM		 15657 info->flags |= DF_TEXTREL;
15658 info->callbacks->minfo
c1c8c1ef 15659 (_("%pB: dynamic relocation against `%pT' in read-only section `%pA'\n"),
63c1f59d 15660 sec->owner, h->root.root.string, sec);
08d1f311 15661
63c1f59d
AM		 15662 /* Not an error, just cut short the traversal. */
15663 return FALSE;
08d1f311
DJ		 15664 }
15665 return TRUE;
15666}
15667
d504ffc8
DJ		 15668void
15669bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
15670 int byteswap_code)
15671{
15672 struct elf32_arm_link_hash_table *globals;
15673
15674 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15675 if (globals == NULL)
15676 return;
15677
d504ffc8
DJ		 15678 globals->byteswap_code = byteswap_code;
15679}
15680
252b5132
RH		 15681/* Set the sizes of the dynamic sections. */
15682
b34976b6 15683static bfd_boolean
57e8b36a
NC		 15684elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
15685 struct bfd_link_info * info)
252b5132
RH		 15686{
15687 bfd * dynobj;
15688 asection * s;
b34976b6
AM		 15689 bfd_boolean plt;
15690 bfd_boolean relocs;
5e681ec4
PB		 15691 bfd *ibfd;
15692 struct elf32_arm_link_hash_table *htab;
252b5132 15693
5e681ec4 15694 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15695 if (htab == NULL)
15696 return FALSE;
15697
252b5132
RH		 15698 dynobj = elf_hash_table (info)->dynobj;
15699 BFD_ASSERT (dynobj != NULL);
39b41c9c 15700 check_use_blx (htab);
252b5132
RH		 15701
15702 if (elf_hash_table (info)->dynamic_sections_created)
15703 {
15704 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 15705 if (bfd_link_executable (info) && !info->nointerp)
252b5132 15706 {
3d4d4302 15707 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 15708 BFD_ASSERT (s != NULL);
eea6121a 15709 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 15710 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
15711 }
15712 }
5e681ec4
PB		 15713
15714 /* Set up .got offsets for local syms, and space for local dynamic
15715 relocs. */
c72f2fb2 15716 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 15717 {
5e681ec4
PB		 15718 bfd_signed_vma *local_got;
15719 bfd_signed_vma *end_local_got;
34e77a92 15720 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 15721 char *local_tls_type;
0855e32b 15722 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 15723 bfd_size_type locsymcount;
15724 Elf_Internal_Shdr *symtab_hdr;
15725 asection *srel;
4dfe6ac6 15726 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 15727 unsigned int symndx;
5e681ec4 15728
0ffa91dd 15729 if (! is_arm_elf (ibfd))
5e681ec4
PB		 15730 continue;
15731
15732 for (s = ibfd->sections; s != NULL; s = s->next)
15733 {
0bdcacaf 15734 struct elf_dyn_relocs *p;
5e681ec4 15735
0bdcacaf 15736 for (p = (struct elf_dyn_relocs *)
99059e56 15737 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 15738 {
0bdcacaf
RS		 15739 if (!bfd_is_abs_section (p->sec)
15740 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 15741 {
15742 /* Input section has been discarded, either because
15743 it is a copy of a linkonce section or due to
15744 linker script /DISCARD/, so we'll be discarding
15745 the relocs too. */
15746 }
3348747a 15747 else if (is_vxworks
0bdcacaf 15748 && strcmp (p->sec->output_section->name,
3348747a
NS		 15749 ".tls_vars") == 0)
15750 {
15751 /* Relocations in vxworks .tls_vars sections are
15752 handled specially by the loader. */
15753 }
5e681ec4
PB		 15754 else if (p->count != 0)
15755 {
0bdcacaf 15756 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 15757 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 15758 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 15759 info->flags |= DF_TEXTREL;
15760 }
15761 }
15762 }
15763
15764 local_got = elf_local_got_refcounts (ibfd);
15765 if (!local_got)
15766 continue;
15767
0ffa91dd 15768 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 15769 locsymcount = symtab_hdr->sh_info;
15770 end_local_got = local_got + locsymcount;
34e77a92 15771 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 15772 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 15773 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 15774 symndx = 0;
362d30a1
RS		 15775 s = htab->root.sgot;
15776 srel = htab->root.srelgot;
0855e32b 15777 for (; local_got < end_local_got;
34e77a92
RS		 15778 ++local_got, ++local_iplt_ptr, ++local_tls_type,
15779 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 15780 {
0855e32b 15781 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 15782 local_iplt = *local_iplt_ptr;
15783 if (local_iplt != NULL)
15784 {
15785 struct elf_dyn_relocs *p;
15786
15787 if (local_iplt->root.refcount > 0)
15788 {
15789 elf32_arm_allocate_plt_entry (info, TRUE,
15790 &local_iplt->root,
15791 &local_iplt->arm);
15792 if (local_iplt->arm.noncall_refcount == 0)
15793 /* All references to the PLT are calls, so all
15794 non-call references can resolve directly to the
15795 run-time target. This means that the .got entry
15796 would be the same as the .igot.plt entry, so there's
15797 no point creating both. */
15798 *local_got = 0;
15799 }
15800 else
15801 {
15802 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
15803 local_iplt->root.offset = (bfd_vma) -1;
15804 }
15805
15806 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
15807 {
15808 asection *psrel;
15809
15810 psrel = elf_section_data (p->sec)->sreloc;
15811 if (local_iplt->arm.noncall_refcount == 0)
15812 elf32_arm_allocate_irelocs (info, psrel, p->count);
15813 else
15814 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
15815 }
15816 }
5e681ec4
PB		 15817 if (*local_got > 0)
15818 {
34e77a92
RS		 15819 Elf_Internal_Sym *isym;
15820
eea6121a 15821 *local_got = s->size;
ba93b8ac
DJ		 15822 if (*local_tls_type & GOT_TLS_GD)
15823 /* TLS_GD relocs need an 8-byte structure in the GOT. */
15824 s->size += 8;
0855e32b
NS		 15825 if (*local_tls_type & GOT_TLS_GDESC)
15826 {
15827 *local_tlsdesc_gotent = htab->root.sgotplt->size
15828 - elf32_arm_compute_jump_table_size (htab);
15829 htab->root.sgotplt->size += 8;
15830 *local_got = (bfd_vma) -2;
34e77a92 15831 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 15832 reloc in the middle of .got.plt. */
99059e56 15833 htab->num_tls_desc++;
0855e32b 15834 }
ba93b8ac
DJ		 15835 if (*local_tls_type & GOT_TLS_IE)
15836 s->size += 4;
ba93b8ac 15837
0855e32b
NS		 15838 if (*local_tls_type & GOT_NORMAL)
15839 {
15840 /* If the symbol is both GD and GDESC, *local_got
15841 may have been overwritten. */
15842 *local_got = s->size;
15843 s->size += 4;
15844 }
15845
34e77a92
RS		 15846 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
15847 if (isym == NULL)
15848 return FALSE;
15849
15850 /* If all references to an STT_GNU_IFUNC PLT are calls,
15851 then all non-call references, including this GOT entry,
15852 resolve directly to the run-time target. */
15853 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
15854 && (local_iplt == NULL
15855 || local_iplt->arm.noncall_refcount == 0))
15856 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 15857 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 15858 {
0e1862bb 15859 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 15860 || *local_tls_type & GOT_TLS_GD)
15861 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 15862
0e1862bb 15863 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 15864 {
15865 elf32_arm_allocate_dynrelocs (info,
15866 htab->root.srelplt, 1);
15867 htab->tls_trampoline = -1;
15868 }
0855e32b 15869 }
5e681ec4
PB		 15870 }
15871 else
15872 *local_got = (bfd_vma) -1;
15873 }
252b5132
RH		 15874 }
15875
ba93b8ac
DJ		 15876 if (htab->tls_ldm_got.refcount > 0)
15877 {
15878 /* Allocate two GOT entries and one dynamic relocation (if necessary)
15879 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 15880 htab->tls_ldm_got.offset = htab->root.sgot->size;
15881 htab->root.sgot->size += 8;
0e1862bb 15882 if (bfd_link_pic (info))
47beaa6a 15883 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 15884 }
15885 else
15886 htab->tls_ldm_got.offset = -1;
15887
5e681ec4
PB		 15888 /* Allocate global sym .plt and .got entries, and space for global
15889 sym dynamic relocs. */
47beaa6a 15890 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 15891
d504ffc8 15892 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 15893 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 15894 {
0ffa91dd 15895 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 15896 continue;
15897
c7b8f16e
JB		 15898 /* Initialise mapping tables for code/data. */
15899 bfd_elf32_arm_init_maps (ibfd);
906e58ca 15900
c7b8f16e 15901 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 15902 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
15903 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
90b6238f 15904 _bfd_error_handler (_("errors encountered processing file %pB"), ibfd);
c7b8f16e 15905 }
d504ffc8 15906
3e6b1042
DJ		 15907 /* Allocate space for the glue sections now that we've sized them. */
15908 bfd_elf32_arm_allocate_interworking_sections (info);
15909
0855e32b
NS		 15910 /* For every jump slot reserved in the sgotplt, reloc_count is
15911 incremented. However, when we reserve space for TLS descriptors,
15912 it's not incremented, so in order to compute the space reserved
15913 for them, it suffices to multiply the reloc count by the jump
15914 slot size. */
15915 if (htab->root.srelplt)
15916 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
15917
15918 if (htab->tls_trampoline)
15919 {
15920 if (htab->root.splt->size == 0)
15921 htab->root.splt->size += htab->plt_header_size;
b38cadfb 15922
0855e32b
NS		 15923 htab->tls_trampoline = htab->root.splt->size;
15924 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 15925
0855e32b 15926 /* If we're not using lazy TLS relocations, don't generate the
99059e56 15927 PLT and GOT entries they require. */
0855e32b
NS		 15928 if (!(info->flags & DF_BIND_NOW))
15929 {
15930 htab->dt_tlsdesc_got = htab->root.sgot->size;
15931 htab->root.sgot->size += 4;
15932
15933 htab->dt_tlsdesc_plt = htab->root.splt->size;
15934 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
15935 }
15936 }
15937
252b5132
RH		 15938 /* The check_relocs and adjust_dynamic_symbol entry points have
15939 determined the sizes of the various dynamic sections. Allocate
15940 memory for them. */
b34976b6
AM		 15941 plt = FALSE;
15942 relocs = FALSE;
252b5132
RH		 15943 for (s = dynobj->sections; s != NULL; s = s->next)
15944 {
15945 const char * name;
252b5132
RH		 15946
15947 if ((s->flags & SEC_LINKER_CREATED) == 0)
15948 continue;
15949
15950 /* It's OK to base decisions on the section name, because none
15951 of the dynobj section names depend upon the input files. */
15952 name = bfd_get_section_name (dynobj, s);
15953
34e77a92 15954 if (s == htab->root.splt)
252b5132 15955 {
c456f082
AM		 15956 /* Remember whether there is a PLT. */
15957 plt = s->size != 0;
252b5132 15958 }
0112cd26 15959 else if (CONST_STRNEQ (name, ".rel"))
252b5132 15960 {
c456f082 15961 if (s->size != 0)
252b5132 15962 {
252b5132 15963 /* Remember whether there are any reloc sections other
00a97672 15964 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 15965 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 15966 relocs = TRUE;
252b5132
RH		 15967
15968 /* We use the reloc_count field as a counter if we need
15969 to copy relocs into the output file. */
15970 s->reloc_count = 0;
15971 }
15972 }
34e77a92
RS		 15973 else if (s != htab->root.sgot
15974 && s != htab->root.sgotplt
15975 && s != htab->root.iplt
15976 && s != htab->root.igotplt
5474d94f
AM		 15977 && s != htab->root.sdynbss
15978 && s != htab->root.sdynrelro)
252b5132
RH		 15979 {
15980 /* It's not one of our sections, so don't allocate space. */
15981 continue;
15982 }
15983
c456f082 15984 if (s->size == 0)
252b5132 15985 {
c456f082 15986 /* If we don't need this section, strip it from the
00a97672
RS		 15987 output file. This is mostly to handle .rel(a).bss and
15988 .rel(a).plt. We must create both sections in
c456f082
AM		 15989 create_dynamic_sections, because they must be created
15990 before the linker maps input sections to output
15991 sections. The linker does that before
15992 adjust_dynamic_symbol is called, and it is that
15993 function which decides whether anything needs to go
15994 into these sections. */
8423293d 15995 s->flags |= SEC_EXCLUDE;
252b5132
RH		 15996 continue;
15997 }
15998
c456f082
AM		 15999 if ((s->flags & SEC_HAS_CONTENTS) == 0)
16000 continue;
16001
252b5132 16002 /* Allocate memory for the section contents. */
21d799b5 16003 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 16004 if (s->contents == NULL)
b34976b6 16005 return FALSE;
252b5132
RH		 16006 }
16007
16008 if (elf_hash_table (info)->dynamic_sections_created)
16009 {
16010 /* Add some entries to the .dynamic section. We fill in the
16011 values later, in elf32_arm_finish_dynamic_sections, but we
16012 must add the entries now so that we get the correct size for
16013 the .dynamic section. The DT_DEBUG entry is filled in by the
16014 dynamic linker and used by the debugger. */
dc810e39 16015#define add_dynamic_entry(TAG, VAL) \
5a580b3a 16016 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 16017
0e1862bb 16018 if (bfd_link_executable (info))
252b5132 16019 {
dc810e39 16020 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 16021 return FALSE;
252b5132
RH		 16022 }
16023
16024 if (plt)
16025 {
dc810e39
AM		 16026 if ( !add_dynamic_entry (DT_PLTGOT, 0)
16027 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 16028 || !add_dynamic_entry (DT_PLTREL,
16029 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 16030 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 16031 return FALSE;
0855e32b 16032
5025eb7c
AO		 16033 if (htab->dt_tlsdesc_plt
16034 && (!add_dynamic_entry (DT_TLSDESC_PLT,0)
16035 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 16036 return FALSE;
252b5132
RH		 16037 }
16038
16039 if (relocs)
16040 {
00a97672
RS		 16041 if (htab->use_rel)
16042 {
16043 if (!add_dynamic_entry (DT_REL, 0)
16044 || !add_dynamic_entry (DT_RELSZ, 0)
16045 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
16046 return FALSE;
16047 }
16048 else
16049 {
16050 if (!add_dynamic_entry (DT_RELA, 0)
16051 || !add_dynamic_entry (DT_RELASZ, 0)
16052 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
16053 return FALSE;
16054 }
252b5132
RH		 16055 }
16056
08d1f311
DJ		 16057 /* If any dynamic relocs apply to a read-only section,
16058 then we need a DT_TEXTREL entry. */
16059 if ((info->flags & DF_TEXTREL) == 0)
63c1f59d 16060 elf_link_hash_traverse (&htab->root, maybe_set_textrel, info);
08d1f311 16061
99e4ae17 16062 if ((info->flags & DF_TEXTREL) != 0)
252b5132 16063 {
dc810e39 16064 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 16065 return FALSE;
252b5132 16066 }
7a2b07ff
NS		 16067 if (htab->vxworks_p
16068 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
16069 return FALSE;
252b5132 16070 }
8532796c 16071#undef add_dynamic_entry
252b5132 16072
b34976b6 16073 return TRUE;
252b5132
RH		 16074}
16075
0855e32b
NS		 16076/* Size sections even though they're not dynamic. We use it to setup
16077 _TLS_MODULE_BASE_, if needed. */
16078
16079static bfd_boolean
16080elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 16081 struct bfd_link_info *info)
0855e32b
NS		 16082{
16083 asection *tls_sec;
16084
0e1862bb 16085 if (bfd_link_relocatable (info))
0855e32b
NS		 16086 return TRUE;
16087
16088 tls_sec = elf_hash_table (info)->tls_sec;
16089
16090 if (tls_sec)
16091 {
16092 struct elf_link_hash_entry *tlsbase;
16093
16094 tlsbase = elf_link_hash_lookup
16095 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
16096
16097 if (tlsbase)
99059e56
RM		 16098 {
16099 struct bfd_link_hash_entry *bh = NULL;
0855e32b 16100 const struct elf_backend_data *bed
99059e56 16101 = get_elf_backend_data (output_bfd);
0855e32b 16102
99059e56 16103 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 16104 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
16105 tls_sec, 0, NULL, FALSE,
16106 bed->collect, &bh)))
16107 return FALSE;
b38cadfb 16108
99059e56
RM		 16109 tlsbase->type = STT_TLS;
16110 tlsbase = (struct elf_link_hash_entry *)bh;
16111 tlsbase->def_regular = 1;
16112 tlsbase->other = STV_HIDDEN;
16113 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 16114 }
16115 }
16116 return TRUE;
16117}
16118
252b5132
RH		 16119/* Finish up dynamic symbol handling. We set the contents of various
16120 dynamic sections here. */
16121
b34976b6 16122static bfd_boolean
906e58ca
NC		 16123elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
16124 struct bfd_link_info * info,
16125 struct elf_link_hash_entry * h,
16126 Elf_Internal_Sym * sym)
252b5132 16127{
e5a52504 16128 struct elf32_arm_link_hash_table *htab;
b7693d02 16129 struct elf32_arm_link_hash_entry *eh;
252b5132 16130
e5a52504 16131 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16132 if (htab == NULL)
16133 return FALSE;
16134
b7693d02 16135 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 16136
16137 if (h->plt.offset != (bfd_vma) -1)
16138 {
34e77a92 16139 if (!eh->is_iplt)
e5a52504 16140 {
34e77a92 16141 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 16142 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
16143 h->dynindx, 0))
16144 return FALSE;
e5a52504 16145 }
57e8b36a 16146
f5385ebf 16147 if (!h->def_regular)
252b5132
RH		 16148 {
16149 /* Mark the symbol as undefined, rather than as defined in
3a635617 16150 the .plt section. */
252b5132 16151 sym->st_shndx = SHN_UNDEF;
3a635617 16152 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 16153 Otherwise, the PLT entry would provide a definition for
16154 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 16155 and so the symbol would never be NULL. Leave the value if
16156 there were any relocations where pointer equality matters
16157 (this is a clue for the dynamic linker, to make function
16158 pointer comparisons work between an application and shared
16159 library). */
97323ad1 16160 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 16161 sym->st_value = 0;
252b5132 16162 }
34e77a92
RS		 16163 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
16164 {
16165 /* At least one non-call relocation references this .iplt entry,
16166 so the .iplt entry is the function's canonical address. */
16167 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 16168 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 16169 sym->st_shndx = (_bfd_elf_section_from_bfd_section
16170 (output_bfd, htab->root.iplt->output_section));
16171 sym->st_value = (h->plt.offset
16172 + htab->root.iplt->output_section->vma
16173 + htab->root.iplt->output_offset);
16174 }
252b5132
RH		 16175 }
16176
f5385ebf 16177 if (h->needs_copy)
252b5132
RH		 16178 {
16179 asection * s;
947216bf 16180 Elf_Internal_Rela rel;
252b5132
RH		 16181
16182 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 16183 BFD_ASSERT (h->dynindx != -1
16184 && (h->root.type == bfd_link_hash_defined
16185 || h->root.type == bfd_link_hash_defweak));
16186
00a97672 16187 rel.r_addend = 0;
252b5132
RH		 16188 rel.r_offset = (h->root.u.def.value
16189 + h->root.u.def.section->output_section->vma
16190 + h->root.u.def.section->output_offset);
16191 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
afbf7e8e 16192 if (h->root.u.def.section == htab->root.sdynrelro)
5474d94f
AM		 16193 s = htab->root.sreldynrelro;
16194 else
16195 s = htab->root.srelbss;
47beaa6a 16196 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 16197 }
16198
00a97672
RS		 16199 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
16200 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
16201 to the ".got" section. */
9637f6ef 16202 if (h == htab->root.hdynamic
00a97672 16203 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 16204 sym->st_shndx = SHN_ABS;
16205
b34976b6 16206 return TRUE;
252b5132
RH		 16207}
16208
0855e32b
NS		 16209static void
16210arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16211 void *contents,
16212 const unsigned long *template, unsigned count)
16213{
16214 unsigned ix;
b38cadfb 16215
0855e32b
NS		 16216 for (ix = 0; ix != count; ix++)
16217 {
16218 unsigned long insn = template[ix];
16219
16220 /* Emit mov pc,rx if bx is not permitted. */
16221 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
16222 insn = (insn & 0xf000000f) | 0x01a0f000;
16223 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
16224 }
16225}
16226
99059e56
RM		 16227/* Install the special first PLT entry for elf32-arm-nacl. Unlike
16228 other variants, NaCl needs this entry in a static executable's
16229 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
16230 zero. For .iplt really only the last bundle is useful, and .iplt
16231 could have a shorter first entry, with each individual PLT entry's
16232 relative branch calculated differently so it targets the last
16233 bundle instead of the instruction before it (labelled .Lplt_tail
16234 above). But it's simpler to keep the size and layout of PLT0
16235 consistent with the dynamic case, at the cost of some dead code at
16236 the start of .iplt and the one dead store to the stack at the start
16237 of .Lplt_tail. */
16238static void
16239arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
16240 asection *plt, bfd_vma got_displacement)
16241{
16242 unsigned int i;
16243
16244 put_arm_insn (htab, output_bfd,
16245 elf32_arm_nacl_plt0_entry[0]
16246 | arm_movw_immediate (got_displacement),
16247 plt->contents + 0);
16248 put_arm_insn (htab, output_bfd,
16249 elf32_arm_nacl_plt0_entry[1]
16250 | arm_movt_immediate (got_displacement),
16251 plt->contents + 4);
16252
16253 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
16254 put_arm_insn (htab, output_bfd,
16255 elf32_arm_nacl_plt0_entry[i],
16256 plt->contents + (i * 4));
16257}
16258
252b5132
RH		 16259/* Finish up the dynamic sections. */
16260
b34976b6 16261static bfd_boolean
57e8b36a 16262elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 16263{
16264 bfd * dynobj;
16265 asection * sgot;
16266 asection * sdyn;
4dfe6ac6
NC		 16267 struct elf32_arm_link_hash_table *htab;
16268
16269 htab = elf32_arm_hash_table (info);
16270 if (htab == NULL)
16271 return FALSE;
252b5132
RH		 16272
16273 dynobj = elf_hash_table (info)->dynobj;
16274
362d30a1 16275 sgot = htab->root.sgotplt;
894891db
NC		 16276 /* A broken linker script might have discarded the dynamic sections.
16277 Catch this here so that we do not seg-fault later on. */
16278 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
16279 return FALSE;
3d4d4302 16280 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 16281
16282 if (elf_hash_table (info)->dynamic_sections_created)
16283 {
16284 asection *splt;
16285 Elf32_External_Dyn *dyncon, *dynconend;
16286
362d30a1 16287 splt = htab->root.splt;
24a1ba0f 16288 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 16289 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 16290
16291 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 16292 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 16293
252b5132
RH		 16294 for (; dyncon < dynconend; dyncon++)
16295 {
16296 Elf_Internal_Dyn dyn;
16297 const char * name;
16298 asection * s;
16299
16300 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
16301
16302 switch (dyn.d_tag)
16303 {
229fcec5
MM		 16304 unsigned int type;
16305
252b5132 16306 default:
7a2b07ff
NS		 16307 if (htab->vxworks_p
16308 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
16309 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 16310 break;
16311
229fcec5
MM		 16312 case DT_HASH:
16313 name = ".hash";
16314 goto get_vma_if_bpabi;
16315 case DT_STRTAB:
16316 name = ".dynstr";
16317 goto get_vma_if_bpabi;
16318 case DT_SYMTAB:
16319 name = ".dynsym";
16320 goto get_vma_if_bpabi;
c0042f5d
MM		 16321 case DT_VERSYM:
16322 name = ".gnu.version";
16323 goto get_vma_if_bpabi;
16324 case DT_VERDEF:
16325 name = ".gnu.version_d";
16326 goto get_vma_if_bpabi;
16327 case DT_VERNEED:
16328 name = ".gnu.version_r";
16329 goto get_vma_if_bpabi;
16330
252b5132 16331 case DT_PLTGOT:
4ade44b7 16332 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 16333 goto get_vma;
16334 case DT_JMPREL:
00a97672 16335 name = RELOC_SECTION (htab, ".plt");
252b5132 16336 get_vma:
4ade44b7 16337 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 16338 if (s == NULL)
16339 {
4eca0228 16340 _bfd_error_handler
4ade44b7 16341 (_("could not find section %s"), name);
05456594
NC		 16342 bfd_set_error (bfd_error_invalid_operation);
16343 return FALSE;
16344 }
229fcec5 16345 if (!htab->symbian_p)
4ade44b7 16346 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 16347 else
16348 /* In the BPABI, tags in the PT_DYNAMIC section point
16349 at the file offset, not the memory address, for the
16350 convenience of the post linker. */
4ade44b7 16351 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 16352 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16353 break;
16354
229fcec5
MM		 16355 get_vma_if_bpabi:
16356 if (htab->symbian_p)
16357 goto get_vma;
16358 break;
16359
252b5132 16360 case DT_PLTRELSZ:
362d30a1 16361 s = htab->root.srelplt;
252b5132 16362 BFD_ASSERT (s != NULL);
eea6121a 16363 dyn.d_un.d_val = s->size;
252b5132
RH		 16364 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16365 break;
906e58ca 16366
252b5132 16367 case DT_RELSZ:
00a97672 16368 case DT_RELASZ:
229fcec5
MM		 16369 case DT_REL:
16370 case DT_RELA:
229fcec5
MM		 16371 /* In the BPABI, the DT_REL tag must point at the file
16372 offset, not the VMA, of the first relocation
16373 section. So, we use code similar to that in
16374 elflink.c, but do not check for SHF_ALLOC on the
64f52338
AM		 16375 relocation section, since relocation sections are
16376 never allocated under the BPABI. PLT relocs are also
16377 included. */
229fcec5
MM		 16378 if (htab->symbian_p)
16379 {
16380 unsigned int i;
16381 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
16382 ? SHT_REL : SHT_RELA);
16383 dyn.d_un.d_val = 0;
16384 for (i = 1; i < elf_numsections (output_bfd); i++)
16385 {
906e58ca 16386 Elf_Internal_Shdr *hdr
229fcec5
MM		 16387 = elf_elfsections (output_bfd)[i];
16388 if (hdr->sh_type == type)
16389 {
906e58ca 16390 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 16391 || dyn.d_tag == DT_RELASZ)
16392 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 16393 else if ((ufile_ptr) hdr->sh_offset
16394 <= dyn.d_un.d_val - 1)
229fcec5
MM		 16395 dyn.d_un.d_val = hdr->sh_offset;
16396 }
16397 }
16398 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16399 }
252b5132 16400 break;
88f7bcd5 16401
0855e32b 16402 case DT_TLSDESC_PLT:
99059e56 16403 s = htab->root.splt;
0855e32b
NS		 16404 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
16405 + htab->dt_tlsdesc_plt);
16406 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16407 break;
16408
16409 case DT_TLSDESC_GOT:
99059e56 16410 s = htab->root.sgot;
0855e32b 16411 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 16412 + htab->dt_tlsdesc_got);
0855e32b
NS		 16413 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
16414 break;
16415
88f7bcd5
NC		 16416 /* Set the bottom bit of DT_INIT/FINI if the
16417 corresponding function is Thumb. */
16418 case DT_INIT:
16419 name = info->init_function;
16420 goto get_sym;
16421 case DT_FINI:
16422 name = info->fini_function;
16423 get_sym:
16424 /* If it wasn't set by elf_bfd_final_link
4cc11e76 16425 then there is nothing to adjust. */
88f7bcd5
NC		 16426 if (dyn.d_un.d_val != 0)
16427 {
16428 struct elf_link_hash_entry * eh;
16429
16430 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 16431 FALSE, FALSE, TRUE);
39d911fc
TP		 16432 if (eh != NULL
16433 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
16434 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 16435 {
16436 dyn.d_un.d_val |= 1;
b34976b6 16437 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 16438 }
16439 }
16440 break;
252b5132
RH		 16441 }
16442 }
16443
24a1ba0f 16444 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 16445 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 16446 {
00a97672
RS		 16447 const bfd_vma *plt0_entry;
16448 bfd_vma got_address, plt_address, got_displacement;
16449
16450 /* Calculate the addresses of the GOT and PLT. */
16451 got_address = sgot->output_section->vma + sgot->output_offset;
16452 plt_address = splt->output_section->vma + splt->output_offset;
16453
16454 if (htab->vxworks_p)
16455 {
16456 /* The VxWorks GOT is relocated by the dynamic linker.
16457 Therefore, we must emit relocations rather than simply
16458 computing the values now. */
16459 Elf_Internal_Rela rel;
16460
16461 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 16462 put_arm_insn (htab, output_bfd, plt0_entry[0],
16463 splt->contents + 0);
16464 put_arm_insn (htab, output_bfd, plt0_entry[1],
16465 splt->contents + 4);
16466 put_arm_insn (htab, output_bfd, plt0_entry[2],
16467 splt->contents + 8);
00a97672
RS		 16468 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
16469
8029a119 16470 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 16471 rel.r_offset = plt_address + 12;
16472 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16473 rel.r_addend = 0;
16474 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
16475 htab->srelplt2->contents);
16476 }
b38cadfb 16477 else if (htab->nacl_p)
99059e56
RM		 16478 arm_nacl_put_plt0 (htab, output_bfd, splt,
16479 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 16480 else if (using_thumb_only (htab))
16481 {
16482 got_displacement = got_address - (plt_address + 12);
16483
16484 plt0_entry = elf32_thumb2_plt0_entry;
16485 put_arm_insn (htab, output_bfd, plt0_entry[0],
16486 splt->contents + 0);
16487 put_arm_insn (htab, output_bfd, plt0_entry[1],
16488 splt->contents + 4);
16489 put_arm_insn (htab, output_bfd, plt0_entry[2],
16490 splt->contents + 8);
16491
16492 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
16493 }
00a97672
RS		 16494 else
16495 {
16496 got_displacement = got_address - (plt_address + 16);
16497
16498 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 16499 put_arm_insn (htab, output_bfd, plt0_entry[0],
16500 splt->contents + 0);
16501 put_arm_insn (htab, output_bfd, plt0_entry[1],
16502 splt->contents + 4);
16503 put_arm_insn (htab, output_bfd, plt0_entry[2],
16504 splt->contents + 8);
16505 put_arm_insn (htab, output_bfd, plt0_entry[3],
16506 splt->contents + 12);
5e681ec4 16507
5e681ec4 16508#ifdef FOUR_WORD_PLT
00a97672
RS		 16509 /* The displacement value goes in the otherwise-unused
16510 last word of the second entry. */
16511 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 16512#else
00a97672 16513 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 16514#endif
00a97672 16515 }
f7a74f8c 16516 }
252b5132
RH		 16517
16518 /* UnixWare sets the entsize of .plt to 4, although that doesn't
16519 really seem like the right value. */
74541ad4
AM		 16520 if (splt->output_section->owner == output_bfd)
16521 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 16522
0855e32b
NS		 16523 if (htab->dt_tlsdesc_plt)
16524 {
16525 bfd_vma got_address
16526 = sgot->output_section->vma + sgot->output_offset;
16527 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
16528 + htab->root.sgot->output_offset);
16529 bfd_vma plt_address
16530 = splt->output_section->vma + splt->output_offset;
16531
b38cadfb 16532 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16533 splt->contents + htab->dt_tlsdesc_plt,
16534 dl_tlsdesc_lazy_trampoline, 6);
16535
16536 bfd_put_32 (output_bfd,
16537 gotplt_address + htab->dt_tlsdesc_got
16538 - (plt_address + htab->dt_tlsdesc_plt)
16539 - dl_tlsdesc_lazy_trampoline[6],
16540 splt->contents + htab->dt_tlsdesc_plt + 24);
16541 bfd_put_32 (output_bfd,
16542 got_address - (plt_address + htab->dt_tlsdesc_plt)
16543 - dl_tlsdesc_lazy_trampoline[7],
16544 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
16545 }
16546
16547 if (htab->tls_trampoline)
16548 {
b38cadfb 16549 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 16550 splt->contents + htab->tls_trampoline,
16551 tls_trampoline, 3);
16552#ifdef FOUR_WORD_PLT
16553 bfd_put_32 (output_bfd, 0x00000000,
16554 splt->contents + htab->tls_trampoline + 12);
b38cadfb 16555#endif
0855e32b
NS		 16556 }
16557
0e1862bb
L		 16558 if (htab->vxworks_p
16559 && !bfd_link_pic (info)
16560 && htab->root.splt->size > 0)
00a97672
RS		 16561 {
16562 /* Correct the .rel(a).plt.unloaded relocations. They will have
16563 incorrect symbol indexes. */
16564 int num_plts;
eed62c48 16565 unsigned char *p;
00a97672 16566
362d30a1 16567 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 16568 / htab->plt_entry_size);
16569 p = htab->srelplt2->contents + RELOC_SIZE (htab);
16570
16571 for (; num_plts; num_plts--)
16572 {
16573 Elf_Internal_Rela rel;
16574
16575 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16576 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
16577 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16578 p += RELOC_SIZE (htab);
16579
16580 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
16581 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
16582 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
16583 p += RELOC_SIZE (htab);
16584 }
16585 }
252b5132
RH		 16586 }
16587
99059e56
RM		 16588 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
16589 /* NaCl uses a special first entry in .iplt too. */
16590 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
16591
252b5132 16592 /* Fill in the first three entries in the global offset table. */
229fcec5 16593 if (sgot)
252b5132 16594 {
229fcec5
MM		 16595 if (sgot->size > 0)
16596 {
16597 if (sdyn == NULL)
16598 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
16599 else
16600 bfd_put_32 (output_bfd,
16601 sdyn->output_section->vma + sdyn->output_offset,
16602 sgot->contents);
16603 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
16604 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
16605 }
252b5132 16606
229fcec5
MM		 16607 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
16608 }
252b5132 16609
b34976b6 16610 return TRUE;
252b5132
RH		 16611}
16612
ba96a88f 16613static void
57e8b36a 16614elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 16615{
9b485d32 16616 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 16617 struct elf32_arm_link_hash_table *globals;
ac4c9b04 16618 struct elf_segment_map *m;
ba96a88f
NC		 16619
16620 i_ehdrp = elf_elfheader (abfd);
16621
94a3258f
PB		 16622 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
16623 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
16624 else
7394f108 16625 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 16626 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 16627
93204d3a
PB		 16628 if (link_info)
16629 {
16630 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 16631 if (globals != NULL && globals->byteswap_code)
93204d3a
PB		 16632 i_ehdrp->e_flags |= EF_ARM_BE8;
16633 }
3bfcb652
NC		 16634
16635 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
16636 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
16637 {
16638 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 16639 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 16640 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
16641 else
16642 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
16643 }
ac4c9b04
MG		 16644
16645 /* Scan segment to set p_flags attribute if it contains only sections with
f0728ee3 16646 SHF_ARM_PURECODE flag. */
ac4c9b04
MG		 16647 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
16648 {
16649 unsigned int j;
16650
16651 if (m->count == 0)
16652 continue;
16653 for (j = 0; j < m->count; j++)
16654 {
f0728ee3 16655 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
ac4c9b04
MG		 16656 break;
16657 }
16658 if (j == m->count)
16659 {
16660 m->p_flags = PF_X;
16661 m->p_flags_valid = 1;
16662 }
16663 }
ba96a88f
NC		 16664}
16665
99e4ae17 16666static enum elf_reloc_type_class
7e612e98
AM		 16667elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
16668 const asection *rel_sec ATTRIBUTE_UNUSED,
16669 const Elf_Internal_Rela *rela)
99e4ae17 16670{
f51e552e 16671 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 16672 {
16673 case R_ARM_RELATIVE:
16674 return reloc_class_relative;
16675 case R_ARM_JUMP_SLOT:
16676 return reloc_class_plt;
16677 case R_ARM_COPY:
16678 return reloc_class_copy;
109575d7
JW		 16679 case R_ARM_IRELATIVE:
16680 return reloc_class_ifunc;
99e4ae17
AJ		 16681 default:
16682 return reloc_class_normal;
16683 }
16684}
16685
e489d0ae 16686static void
57e8b36a 16687elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 16688{
5a6c6817 16689 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 16690}
16691
40a18ebd
NC		 16692/* Return TRUE if this is an unwinding table entry. */
16693
16694static bfd_boolean
16695is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
16696{
0112cd26
NC		 16697 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
16698 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 16699}
16700
16701
16702/* Set the type and flags for an ARM section. We do this by
16703 the section name, which is a hack, but ought to work. */
16704
16705static bfd_boolean
16706elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
16707{
16708 const char * name;
16709
16710 name = bfd_get_section_name (abfd, sec);
16711
16712 if (is_arm_elf_unwind_section_name (abfd, name))
16713 {
16714 hdr->sh_type = SHT_ARM_EXIDX;
16715 hdr->sh_flags |= SHF_LINK_ORDER;
16716 }
ac4c9b04 16717
f0728ee3
AV		 16718 if (sec->flags & SEC_ELF_PURECODE)
16719 hdr->sh_flags |= SHF_ARM_PURECODE;
ac4c9b04 16720
40a18ebd
NC		 16721 return TRUE;
16722}
16723
6dc132d9
L		 16724/* Handle an ARM specific section when reading an object file. This is
16725 called when bfd_section_from_shdr finds a section with an unknown
16726 type. */
40a18ebd
NC		 16727
16728static bfd_boolean
16729elf32_arm_section_from_shdr (bfd *abfd,
16730 Elf_Internal_Shdr * hdr,
6dc132d9
L		 16731 const char *name,
16732 int shindex)
40a18ebd
NC		 16733{
16734 /* There ought to be a place to keep ELF backend specific flags, but
16735 at the moment there isn't one. We just keep track of the
16736 sections by their name, instead. Fortunately, the ABI gives
16737 names for all the ARM specific sections, so we will probably get
16738 away with this. */
16739 switch (hdr->sh_type)
16740 {
16741 case SHT_ARM_EXIDX:
0951f019
RE		 16742 case SHT_ARM_PREEMPTMAP:
16743 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 16744 break;
16745
16746 default:
16747 return FALSE;
16748 }
16749
6dc132d9 16750 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 16751 return FALSE;
16752
16753 return TRUE;
16754}
e489d0ae 16755
44444f50
NC		 16756static _arm_elf_section_data *
16757get_arm_elf_section_data (asection * sec)
16758{
47b2e99c
JZ		 16759 if (sec && sec->owner && is_arm_elf (sec->owner))
16760 return elf32_arm_section_data (sec);
44444f50
NC		 16761 else
16762 return NULL;
8e3de13a
NC		 16763}
16764
4e617b1e
PB		 16765typedef struct
16766{
57402f1e 16767 void *flaginfo;
4e617b1e 16768 struct bfd_link_info *info;
91a5743d
PB		 16769 asection *sec;
16770 int sec_shndx;
6e0b88f1
AM		 16771 int (*func) (void *, const char *, Elf_Internal_Sym *,
16772 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 16773} output_arch_syminfo;
16774
16775enum map_symbol_type
16776{
16777 ARM_MAP_ARM,
16778 ARM_MAP_THUMB,
16779 ARM_MAP_DATA
16780};
16781
16782
7413f23f 16783/* Output a single mapping symbol. */
4e617b1e
PB		 16784
16785static bfd_boolean
7413f23f
DJ		 16786elf32_arm_output_map_sym (output_arch_syminfo *osi,
16787 enum map_symbol_type type,
16788 bfd_vma offset)
4e617b1e
PB		 16789{
16790 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 16791 Elf_Internal_Sym sym;
16792
91a5743d
PB		 16793 sym.st_value = osi->sec->output_section->vma
16794 + osi->sec->output_offset
16795 + offset;
4e617b1e
PB		 16796 sym.st_size = 0;
16797 sym.st_other = 0;
16798 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 16799 sym.st_shndx = osi->sec_shndx;
35fc36a8 16800 sym.st_target_internal = 0;
fe33d2fa 16801 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 16802 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 16803}
16804
34e77a92
RS		 16805/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
16806 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 16807
16808static bfd_boolean
34e77a92
RS		 16809elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
16810 bfd_boolean is_iplt_entry_p,
16811 union gotplt_union *root_plt,
16812 struct arm_plt_info *arm_plt)
4e617b1e 16813{
4e617b1e 16814 struct elf32_arm_link_hash_table *htab;
34e77a92 16815 bfd_vma addr, plt_header_size;
4e617b1e 16816
34e77a92 16817 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 16818 return TRUE;
16819
4dfe6ac6
NC		 16820 htab = elf32_arm_hash_table (osi->info);
16821 if (htab == NULL)
16822 return FALSE;
16823
34e77a92
RS		 16824 if (is_iplt_entry_p)
16825 {
16826 osi->sec = htab->root.iplt;
16827 plt_header_size = 0;
16828 }
16829 else
16830 {
16831 osi->sec = htab->root.splt;
16832 plt_header_size = htab->plt_header_size;
16833 }
16834 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
16835 (osi->info->output_bfd, osi->sec->output_section));
16836
16837 addr = root_plt->offset & -2;
4e617b1e
PB		 16838 if (htab->symbian_p)
16839 {
7413f23f 16840 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16841 return FALSE;
7413f23f 16842 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 16843 return FALSE;
16844 }
16845 else if (htab->vxworks_p)
16846 {
7413f23f 16847 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16848 return FALSE;
7413f23f 16849 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 16850 return FALSE;
7413f23f 16851 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 16852 return FALSE;
7413f23f 16853 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 16854 return FALSE;
16855 }
b38cadfb
NC		 16856 else if (htab->nacl_p)
16857 {
16858 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
16859 return FALSE;
16860 }
eed94f8f
NC		 16861 else if (using_thumb_only (htab))
16862 {
16863 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
16864 return FALSE;
6a631e86 16865 }
4e617b1e
PB		 16866 else
16867 {
34e77a92 16868 bfd_boolean thumb_stub_p;
bd97cb95 16869
34e77a92
RS		 16870 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
16871 if (thumb_stub_p)
4e617b1e 16872 {
7413f23f 16873 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 16874 return FALSE;
16875 }
16876#ifdef FOUR_WORD_PLT
7413f23f 16877 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16878 return FALSE;
7413f23f 16879 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 16880 return FALSE;
16881#else
906e58ca 16882 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 16883 so only need to output a mapping symbol for the first PLT entry and
16884 entries with thumb thunks. */
34e77a92 16885 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 16886 {
7413f23f 16887 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 16888 return FALSE;
16889 }
16890#endif
16891 }
16892
16893 return TRUE;
16894}
16895
34e77a92
RS		 16896/* Output mapping symbols for PLT entries associated with H. */
16897
16898static bfd_boolean
16899elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
16900{
16901 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
16902 struct elf32_arm_link_hash_entry *eh;
16903
16904 if (h->root.type == bfd_link_hash_indirect)
16905 return TRUE;
16906
16907 if (h->root.type == bfd_link_hash_warning)
16908 /* When warning symbols are created, they **replace** the "real"
16909 entry in the hash table, thus we never get to see the real
16910 symbol in a hash traversal. So look at it now. */
16911 h = (struct elf_link_hash_entry *) h->root.u.i.link;
16912
16913 eh = (struct elf32_arm_link_hash_entry *) h;
16914 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
16915 &h->plt, &eh->plt);
16916}
16917
4f4faa4d
TP		 16918/* Bind a veneered symbol to its veneer identified by its hash entry
16919 STUB_ENTRY. The veneered location thus loose its symbol. */
16920
16921static void
16922arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
16923{
16924 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
16925
16926 BFD_ASSERT (hash);
16927 hash->root.root.u.def.section = stub_entry->stub_sec;
16928 hash->root.root.u.def.value = stub_entry->stub_offset;
16929 hash->root.size = stub_entry->stub_size;
16930}
16931
7413f23f
DJ		 16932/* Output a single local symbol for a generated stub. */
16933
16934static bfd_boolean
16935elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
16936 bfd_vma offset, bfd_vma size)
16937{
7413f23f
DJ		 16938 Elf_Internal_Sym sym;
16939
7413f23f
DJ		 16940 sym.st_value = osi->sec->output_section->vma
16941 + osi->sec->output_offset
16942 + offset;
16943 sym.st_size = size;
16944 sym.st_other = 0;
16945 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
16946 sym.st_shndx = osi->sec_shndx;
35fc36a8 16947 sym.st_target_internal = 0;
57402f1e 16948 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 16949}
4e617b1e 16950
da5938a2 16951static bfd_boolean
8029a119
NC		 16952arm_map_one_stub (struct bfd_hash_entry * gen_entry,
16953 void * in_arg)
da5938a2
NC		 16954{
16955 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 16956 asection *stub_sec;
16957 bfd_vma addr;
7413f23f 16958 char *stub_name;
9a008db3 16959 output_arch_syminfo *osi;
d3ce72d0 16960 const insn_sequence *template_sequence;
461a49ca
DJ		 16961 enum stub_insn_type prev_type;
16962 int size;
16963 int i;
16964 enum map_symbol_type sym_type;
da5938a2
NC		 16965
16966 /* Massage our args to the form they really have. */
16967 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 16968 osi = (output_arch_syminfo *) in_arg;
da5938a2 16969
da5938a2
NC		 16970 stub_sec = stub_entry->stub_sec;
16971
16972 /* Ensure this stub is attached to the current section being
7413f23f 16973 processed. */
da5938a2
NC		 16974 if (stub_sec != osi->sec)
16975 return TRUE;
16976
7413f23f 16977 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 16978 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 16979
16980 if (arm_stub_sym_claimed (stub_entry->stub_type))
16981 arm_stub_claim_sym (stub_entry);
16982 else
7413f23f 16983 {
4f4faa4d
TP		 16984 stub_name = stub_entry->output_name;
16985 switch (template_sequence[0].type)
16986 {
16987 case ARM_TYPE:
16988 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
16989 stub_entry->stub_size))
16990 return FALSE;
16991 break;
16992 case THUMB16_TYPE:
16993 case THUMB32_TYPE:
16994 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
16995 stub_entry->stub_size))
16996 return FALSE;
16997 break;
16998 default:
16999 BFD_FAIL ();
17000 return 0;
17001 }
7413f23f 17002 }
da5938a2 17003
461a49ca
DJ		 17004 prev_type = DATA_TYPE;
17005 size = 0;
17006 for (i = 0; i < stub_entry->stub_template_size; i++)
17007 {
d3ce72d0 17008 switch (template_sequence[i].type)
461a49ca
DJ		 17009 {
17010 case ARM_TYPE:
17011 sym_type = ARM_MAP_ARM;
17012 break;
17013
17014 case THUMB16_TYPE:
48229727 17015 case THUMB32_TYPE:
461a49ca
DJ		 17016 sym_type = ARM_MAP_THUMB;
17017 break;
17018
17019 case DATA_TYPE:
17020 sym_type = ARM_MAP_DATA;
17021 break;
17022
17023 default:
17024 BFD_FAIL ();
4e31c731 17025 return FALSE;
461a49ca
DJ		 17026 }
17027
d3ce72d0 17028 if (template_sequence[i].type != prev_type)
461a49ca 17029 {
d3ce72d0 17030 prev_type = template_sequence[i].type;
461a49ca
DJ		 17031 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
17032 return FALSE;
17033 }
17034
d3ce72d0 17035 switch (template_sequence[i].type)
461a49ca
DJ		 17036 {
17037 case ARM_TYPE:
48229727 17038 case THUMB32_TYPE:
461a49ca
DJ		 17039 size += 4;
17040 break;
17041
17042 case THUMB16_TYPE:
17043 size += 2;
17044 break;
17045
17046 case DATA_TYPE:
17047 size += 4;
17048 break;
17049
17050 default:
17051 BFD_FAIL ();
4e31c731 17052 return FALSE;
461a49ca
DJ		 17053 }
17054 }
17055
da5938a2
NC		 17056 return TRUE;
17057}
17058
33811162
DG		 17059/* Output mapping symbols for linker generated sections,
17060 and for those data-only sections that do not have a
17061 $d. */
4e617b1e
PB		 17062
17063static bfd_boolean
17064elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 17065 struct bfd_link_info *info,
57402f1e 17066 void *flaginfo,
6e0b88f1
AM		 17067 int (*func) (void *, const char *,
17068 Elf_Internal_Sym *,
17069 asection *,
17070 struct elf_link_hash_entry *))
4e617b1e
PB		 17071{
17072 output_arch_syminfo osi;
17073 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 17074 bfd_vma offset;
17075 bfd_size_type size;
33811162 17076 bfd *input_bfd;
4e617b1e
PB		 17077
17078 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 17079 if (htab == NULL)
17080 return FALSE;
17081
906e58ca 17082 check_use_blx (htab);
91a5743d 17083
57402f1e 17084 osi.flaginfo = flaginfo;
4e617b1e
PB		 17085 osi.info = info;
17086 osi.func = func;
906e58ca 17087
33811162
DG		 17088 /* Add a $d mapping symbol to data-only sections that
17089 don't have any mapping symbol. This may result in (harmless) redundant
17090 mapping symbols. */
17091 for (input_bfd = info->input_bfds;
17092 input_bfd != NULL;
c72f2fb2 17093 input_bfd = input_bfd->link.next)
33811162
DG		 17094 {
17095 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
17096 for (osi.sec = input_bfd->sections;
17097 osi.sec != NULL;
17098 osi.sec = osi.sec->next)
17099 {
17100 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 17101 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
17102 != 0)
33811162
DG		 17103 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
17104 == SEC_HAS_CONTENTS
17105 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 17106 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 17107 && osi.sec->size > 0
17108 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 17109 {
17110 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17111 (output_bfd, osi.sec->output_section);
17112 if (osi.sec_shndx != (int)SHN_BAD)
17113 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
17114 }
17115 }
17116 }
17117
91a5743d
PB		 17118 /* ARM->Thumb glue. */
17119 if (htab->arm_glue_size > 0)
17120 {
3d4d4302
AM		 17121 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17122 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 17123
17124 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17125 (output_bfd, osi.sec->output_section);
0e1862bb 17126 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 17127 || htab->pic_veneer)
17128 size = ARM2THUMB_PIC_GLUE_SIZE;
17129 else if (htab->use_blx)
17130 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
17131 else
17132 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 17133
91a5743d
PB		 17134 for (offset = 0; offset < htab->arm_glue_size; offset += size)
17135 {
7413f23f
DJ		 17136 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
17137 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 17138 }
17139 }
17140
17141 /* Thumb->ARM glue. */
17142 if (htab->thumb_glue_size > 0)
17143 {
3d4d4302
AM		 17144 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17145 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 17146
17147 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17148 (output_bfd, osi.sec->output_section);
17149 size = THUMB2ARM_GLUE_SIZE;
17150
17151 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
17152 {
7413f23f
DJ		 17153 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
17154 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 17155 }
17156 }
17157
845b51d6
PB		 17158 /* ARMv4 BX veneers. */
17159 if (htab->bx_glue_size > 0)
17160 {
3d4d4302
AM		 17161 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
17162 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 17163
17164 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17165 (output_bfd, osi.sec->output_section);
17166
7413f23f 17167 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 17168 }
17169
8029a119
NC		 17170 /* Long calls stubs. */
17171 if (htab->stub_bfd && htab->stub_bfd->sections)
17172 {
da5938a2 17173 asection* stub_sec;
8029a119 17174
da5938a2
NC		 17175 for (stub_sec = htab->stub_bfd->sections;
17176 stub_sec != NULL;
8029a119
NC		 17177 stub_sec = stub_sec->next)
17178 {
17179 /* Ignore non-stub sections. */
17180 if (!strstr (stub_sec->name, STUB_SUFFIX))
17181 continue;
da5938a2 17182
8029a119 17183 osi.sec = stub_sec;
da5938a2 17184
8029a119
NC		 17185 osi.sec_shndx = _bfd_elf_section_from_bfd_section
17186 (output_bfd, osi.sec->output_section);
da5938a2 17187
8029a119
NC		 17188 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
17189 }
17190 }
da5938a2 17191
91a5743d 17192 /* Finally, output mapping symbols for the PLT. */
34e77a92 17193 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 17194 {
34e77a92
RS		 17195 osi.sec = htab->root.splt;
17196 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17197 (output_bfd, osi.sec->output_section));
17198
17199 /* Output mapping symbols for the plt header. SymbianOS does not have a
17200 plt header. */
17201 if (htab->vxworks_p)
17202 {
17203 /* VxWorks shared libraries have no PLT header. */
0e1862bb 17204 if (!bfd_link_pic (info))
34e77a92
RS		 17205 {
17206 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17207 return FALSE;
17208 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17209 return FALSE;
17210 }
17211 }
b38cadfb
NC		 17212 else if (htab->nacl_p)
17213 {
17214 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17215 return FALSE;
17216 }
eed94f8f
NC		 17217 else if (using_thumb_only (htab))
17218 {
17219 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
17220 return FALSE;
17221 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
17222 return FALSE;
17223 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
17224 return FALSE;
17225 }
34e77a92 17226 else if (!htab->symbian_p)
4e617b1e 17227 {
7413f23f 17228 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 17229 return FALSE;
34e77a92
RS		 17230#ifndef FOUR_WORD_PLT
17231 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 17232 return FALSE;
34e77a92 17233#endif
4e617b1e
PB		 17234 }
17235 }
99059e56
RM		 17236 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
17237 {
17238 /* NaCl uses a special first entry in .iplt too. */
17239 osi.sec = htab->root.iplt;
17240 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
17241 (output_bfd, osi.sec->output_section));
17242 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
17243 return FALSE;
17244 }
34e77a92
RS		 17245 if ((htab->root.splt && htab->root.splt->size > 0)
17246 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 17247 {
34e77a92
RS		 17248 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
17249 for (input_bfd = info->input_bfds;
17250 input_bfd != NULL;
c72f2fb2 17251 input_bfd = input_bfd->link.next)
34e77a92
RS		 17252 {
17253 struct arm_local_iplt_info **local_iplt;
17254 unsigned int i, num_syms;
4e617b1e 17255
34e77a92
RS		 17256 local_iplt = elf32_arm_local_iplt (input_bfd);
17257 if (local_iplt != NULL)
17258 {
17259 num_syms = elf_symtab_hdr (input_bfd).sh_info;
17260 for (i = 0; i < num_syms; i++)
17261 if (local_iplt[i] != NULL
17262 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
17263 &local_iplt[i]->root,
17264 &local_iplt[i]->arm))
17265 return FALSE;
17266 }
17267 }
17268 }
0855e32b
NS		 17269 if (htab->dt_tlsdesc_plt != 0)
17270 {
17271 /* Mapping symbols for the lazy tls trampoline. */
17272 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
17273 return FALSE;
b38cadfb 17274
0855e32b
NS		 17275 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17276 htab->dt_tlsdesc_plt + 24))
17277 return FALSE;
17278 }
17279 if (htab->tls_trampoline != 0)
17280 {
17281 /* Mapping symbols for the tls trampoline. */
17282 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
17283 return FALSE;
17284#ifdef FOUR_WORD_PLT
17285 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
17286 htab->tls_trampoline + 12))
17287 return FALSE;
b38cadfb 17288#endif
0855e32b 17289 }
b38cadfb 17290
4e617b1e
PB		 17291 return TRUE;
17292}
17293
54ddd295
TP		 17294/* Filter normal symbols of CMSE entry functions of ABFD to include in
17295 the import library. All SYMCOUNT symbols of ABFD can be examined
17296 from their pointers in SYMS. Pointers of symbols to keep should be
17297 stored continuously at the beginning of that array.
17298
17299 Returns the number of symbols to keep. */
17300
17301static unsigned int
17302elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17303 struct bfd_link_info *info,
17304 asymbol **syms, long symcount)
17305{
17306 size_t maxnamelen;
17307 char *cmse_name;
17308 long src_count, dst_count = 0;
17309 struct elf32_arm_link_hash_table *htab;
17310
17311 htab = elf32_arm_hash_table (info);
17312 if (!htab->stub_bfd || !htab->stub_bfd->sections)
17313 symcount = 0;
17314
17315 maxnamelen = 128;
17316 cmse_name = (char *) bfd_malloc (maxnamelen);
17317 for (src_count = 0; src_count < symcount; src_count++)
17318 {
17319 struct elf32_arm_link_hash_entry *cmse_hash;
17320 asymbol *sym;
17321 flagword flags;
17322 char *name;
17323 size_t namelen;
17324
17325 sym = syms[src_count];
17326 flags = sym->flags;
17327 name = (char *) bfd_asymbol_name (sym);
17328
17329 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
17330 continue;
17331 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
17332 continue;
17333
17334 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
17335 if (namelen > maxnamelen)
17336 {
17337 cmse_name = (char *)
17338 bfd_realloc (cmse_name, namelen);
17339 maxnamelen = namelen;
17340 }
17341 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
17342 cmse_hash = (struct elf32_arm_link_hash_entry *)
17343 elf_link_hash_lookup (&(htab)->root, cmse_name, FALSE, FALSE, TRUE);
17344
17345 if (!cmse_hash
17346 || (cmse_hash->root.root.type != bfd_link_hash_defined
17347 && cmse_hash->root.root.type != bfd_link_hash_defweak)
17348 || cmse_hash->root.type != STT_FUNC)
17349 continue;
17350
17351 if (!ARM_GET_SYM_CMSE_SPCL (cmse_hash->root.target_internal))
17352 continue;
17353
17354 syms[dst_count++] = sym;
17355 }
17356 free (cmse_name);
17357
17358 syms[dst_count] = NULL;
17359
17360 return dst_count;
17361}
17362
17363/* Filter symbols of ABFD to include in the import library. All
17364 SYMCOUNT symbols of ABFD can be examined from their pointers in
17365 SYMS. Pointers of symbols to keep should be stored continuously at
17366 the beginning of that array.
17367
17368 Returns the number of symbols to keep. */
17369
17370static unsigned int
17371elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
17372 struct bfd_link_info *info,
17373 asymbol **syms, long symcount)
17374{
17375 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
17376
046734ff
TP		 17377 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
17378 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
17379 library to be a relocatable object file. */
17380 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
54ddd295
TP		 17381 if (globals->cmse_implib)
17382 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
17383 else
17384 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
17385}
17386
e489d0ae
PB		 17387/* Allocate target specific section data. */
17388
17389static bfd_boolean
17390elf32_arm_new_section_hook (bfd *abfd, asection *sec)
17391{
f592407e
AM		 17392 if (!sec->used_by_bfd)
17393 {
17394 _arm_elf_section_data *sdata;
17395 bfd_size_type amt = sizeof (*sdata);
e489d0ae 17396
21d799b5 17397 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 17398 if (sdata == NULL)
17399 return FALSE;
17400 sec->used_by_bfd = sdata;
17401 }
e489d0ae
PB		 17402
17403 return _bfd_elf_new_section_hook (abfd, sec);
17404}
17405
17406
17407/* Used to order a list of mapping symbols by address. */
17408
17409static int
17410elf32_arm_compare_mapping (const void * a, const void * b)
17411{
7f6a71ff
JM		 17412 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
17413 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
17414
17415 if (amap->vma > bmap->vma)
17416 return 1;
17417 else if (amap->vma < bmap->vma)
17418 return -1;
17419 else if (amap->type > bmap->type)
17420 /* Ensure results do not depend on the host qsort for objects with
17421 multiple mapping symbols at the same address by sorting on type
17422 after vma. */
17423 return 1;
17424 else if (amap->type < bmap->type)
17425 return -1;
17426 else
17427 return 0;
e489d0ae
PB		 17428}
17429
2468f9c9
PB		 17430/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
17431
17432static unsigned long
17433offset_prel31 (unsigned long addr, bfd_vma offset)
17434{
17435 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
17436}
17437
17438/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
17439 relocations. */
17440
17441static void
17442copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
17443{
17444 unsigned long first_word = bfd_get_32 (output_bfd, from);
17445 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 17446
2468f9c9
PB		 17447 /* High bit of first word is supposed to be zero. */
17448 if ((first_word & 0x80000000ul) == 0)
17449 first_word = offset_prel31 (first_word, offset);
b38cadfb 17450
2468f9c9
PB		 17451 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
17452 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
17453 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
17454 second_word = offset_prel31 (second_word, offset);
b38cadfb 17455
2468f9c9
PB		 17456 bfd_put_32 (output_bfd, first_word, to);
17457 bfd_put_32 (output_bfd, second_word, to + 4);
17458}
e489d0ae 17459
48229727
JB		 17460/* Data for make_branch_to_a8_stub(). */
17461
b38cadfb
NC		 17462struct a8_branch_to_stub_data
17463{
48229727
JB		 17464 asection *writing_section;
17465 bfd_byte *contents;
17466};
17467
17468
17469/* Helper to insert branches to Cortex-A8 erratum stubs in the right
17470 places for a particular section. */
17471
17472static bfd_boolean
17473make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 17474 void *in_arg)
48229727
JB		 17475{
17476 struct elf32_arm_stub_hash_entry *stub_entry;
17477 struct a8_branch_to_stub_data *data;
17478 bfd_byte *contents;
17479 unsigned long branch_insn;
17480 bfd_vma veneered_insn_loc, veneer_entry_loc;
17481 bfd_signed_vma branch_offset;
17482 bfd *abfd;
8d9d9490 17483 unsigned int loc;
48229727
JB		 17484
17485 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
17486 data = (struct a8_branch_to_stub_data *) in_arg;
17487
17488 if (stub_entry->target_section != data->writing_section
4563a860 17489 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 17490 return TRUE;
17491
17492 contents = data->contents;
17493
8d9d9490
TP		 17494 /* We use target_section as Cortex-A8 erratum workaround stubs are only
17495 generated when both source and target are in the same section. */
48229727
JB		 17496 veneered_insn_loc = stub_entry->target_section->output_section->vma
17497 + stub_entry->target_section->output_offset
8d9d9490 17498 + stub_entry->source_value;
48229727
JB		 17499
17500 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
17501 + stub_entry->stub_sec->output_offset
17502 + stub_entry->stub_offset;
17503
17504 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
17505 veneered_insn_loc &= ~3u;
17506
17507 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
17508
17509 abfd = stub_entry->target_section->owner;
8d9d9490 17510 loc = stub_entry->source_value;
48229727
JB		 17511
17512 /* We attempt to avoid this condition by setting stubs_always_after_branch
17513 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
17514 This check is just to be on the safe side... */
17515 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
17516 {
871b3ab2 17517 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub is "
4eca0228 17518 "allocated in unsafe location"), abfd);
48229727
JB		 17519 return FALSE;
17520 }
17521
17522 switch (stub_entry->stub_type)
17523 {
17524 case arm_stub_a8_veneer_b:
17525 case arm_stub_a8_veneer_b_cond:
17526 branch_insn = 0xf0009000;
17527 goto jump24;
17528
17529 case arm_stub_a8_veneer_blx:
17530 branch_insn = 0xf000e800;
17531 goto jump24;
17532
17533 case arm_stub_a8_veneer_bl:
17534 {
17535 unsigned int i1, j1, i2, j2, s;
17536
17537 branch_insn = 0xf000d000;
17538
17539 jump24:
17540 if (branch_offset < -16777216 || branch_offset > 16777214)
17541 {
17542 /* There's not much we can do apart from complain if this
17543 happens. */
871b3ab2 17544 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub out "
4eca0228 17545 "of range (input file too large)"), abfd);
48229727
JB		 17546 return FALSE;
17547 }
17548
17549 /* i1 = not(j1 eor s), so:
17550 not i1 = j1 eor s
17551 j1 = (not i1) eor s. */
17552
17553 branch_insn |= (branch_offset >> 1) & 0x7ff;
17554 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
17555 i2 = (branch_offset >> 22) & 1;
17556 i1 = (branch_offset >> 23) & 1;
17557 s = (branch_offset >> 24) & 1;
17558 j1 = (!i1) ^ s;
17559 j2 = (!i2) ^ s;
17560 branch_insn |= j2 << 11;
17561 branch_insn |= j1 << 13;
17562 branch_insn |= s << 26;
17563 }
17564 break;
17565
17566 default:
17567 BFD_FAIL ();
17568 return FALSE;
17569 }
17570
8d9d9490
TP		 17571 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
17572 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 17573
17574 return TRUE;
17575}
17576
a504d23a
LA		 17577/* Beginning of stm32l4xx work-around. */
17578
17579/* Functions encoding instructions necessary for the emission of the
17580 fix-stm32l4xx-629360.
17581 Encoding is extracted from the
17582 ARM (C) Architecture Reference Manual
17583 ARMv7-A and ARMv7-R edition
17584 ARM DDI 0406C.b (ID072512). */
17585
17586static inline bfd_vma
82188b29 17587create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 17588{
17589 /* A8.8.18 B (A8-334)
17590 B target_address (Encoding T4). */
17591 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
17592 /* jump offset is: S:I1:I2:imm10:imm11:0. */
17593 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
17594
a504d23a
LA		 17595 int s = ((branch_offset & 0x1000000) >> 24);
17596 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
17597 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
17598
17599 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
17600 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
17601
17602 bfd_vma patched_inst = 0xf0009000
17603 | s << 26 /* S. */
17604 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
17605 | j1 << 13 /* J1. */
17606 | j2 << 11 /* J2. */
17607 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
17608
17609 return patched_inst;
17610}
17611
17612static inline bfd_vma
17613create_instruction_ldmia (int base_reg, int wback, int reg_mask)
17614{
17615 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
17616 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
17617 bfd_vma patched_inst = 0xe8900000
17618 | (/*W=*/wback << 21)
17619 | (base_reg << 16)
17620 | (reg_mask & 0x0000ffff);
17621
17622 return patched_inst;
17623}
17624
17625static inline bfd_vma
17626create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
17627{
17628 /* A8.8.60 LDMDB/LDMEA (A8-402)
17629 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
17630 bfd_vma patched_inst = 0xe9100000
17631 | (/*W=*/wback << 21)
17632 | (base_reg << 16)
17633 | (reg_mask & 0x0000ffff);
17634
17635 return patched_inst;
17636}
17637
17638static inline bfd_vma
17639create_instruction_mov (int target_reg, int source_reg)
17640{
17641 /* A8.8.103 MOV (register) (A8-486)
17642 MOV Rd, Rm (Encoding T1). */
17643 bfd_vma patched_inst = 0x4600
17644 | (target_reg & 0x7)
17645 | ((target_reg & 0x8) >> 3) << 7
17646 | (source_reg << 3);
17647
17648 return patched_inst;
17649}
17650
17651static inline bfd_vma
17652create_instruction_sub (int target_reg, int source_reg, int value)
17653{
17654 /* A8.8.221 SUB (immediate) (A8-708)
17655 SUB Rd, Rn, #value (Encoding T3). */
17656 bfd_vma patched_inst = 0xf1a00000
17657 | (target_reg << 8)
17658 | (source_reg << 16)
17659 | (/*S=*/0 << 20)
17660 | ((value & 0x800) >> 11) << 26
17661 | ((value & 0x700) >> 8) << 12
17662 | (value & 0x0ff);
17663
17664 return patched_inst;
17665}
17666
17667static inline bfd_vma
9239bbd3 17668create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 17669 int first_reg)
17670{
17671 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17672 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
17673 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 17674 | (/*W=*/wback << 21)
17675 | (base_reg << 16)
9239bbd3
CM		 17676 | (num_words & 0x000000ff)
17677 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 17678 | (first_reg & 0x00000001) << 22;
17679
17680 return patched_inst;
17681}
17682
17683static inline bfd_vma
9239bbd3
CM		 17684create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
17685 int first_reg)
a504d23a
LA		 17686{
17687 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 17688 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
17689 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 17690 | (base_reg << 16)
9239bbd3
CM		 17691 | (num_words & 0x000000ff)
17692 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 17693 | (first_reg & 0x00000001) << 22;
17694
17695 return patched_inst;
17696}
17697
17698static inline bfd_vma
17699create_instruction_udf_w (int value)
17700{
17701 /* A8.8.247 UDF (A8-758)
17702 Undefined (Encoding T2). */
17703 bfd_vma patched_inst = 0xf7f0a000
17704 | (value & 0x00000fff)
17705 | (value & 0x000f0000) << 16;
17706
17707 return patched_inst;
17708}
17709
17710static inline bfd_vma
17711create_instruction_udf (int value)
17712{
17713 /* A8.8.247 UDF (A8-758)
17714 Undefined (Encoding T1). */
17715 bfd_vma patched_inst = 0xde00
17716 | (value & 0xff);
17717
17718 return patched_inst;
17719}
17720
17721/* Functions writing an instruction in memory, returning the next
17722 memory position to write to. */
17723
17724static inline bfd_byte *
17725push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
17726 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17727{
17728 put_thumb2_insn (htab, output_bfd, insn, pt);
17729 return pt + 4;
17730}
17731
17732static inline bfd_byte *
17733push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
17734 bfd * output_bfd, bfd_byte *pt, insn32 insn)
17735{
17736 put_thumb_insn (htab, output_bfd, insn, pt);
17737 return pt + 2;
17738}
17739
17740/* Function filling up a region in memory with T1 and T2 UDFs taking
17741 care of alignment. */
17742
17743static bfd_byte *
17744stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
07d6d2b8
AM		 17745 bfd * output_bfd,
17746 const bfd_byte * const base_stub_contents,
17747 bfd_byte * const from_stub_contents,
17748 const bfd_byte * const end_stub_contents)
a504d23a
LA		 17749{
17750 bfd_byte *current_stub_contents = from_stub_contents;
17751
17752 /* Fill the remaining of the stub with deterministic contents : UDF
17753 instructions.
17754 Check if realignment is needed on modulo 4 frontier using T1, to
17755 further use T2. */
17756 if ((current_stub_contents < end_stub_contents)
17757 && !((current_stub_contents - base_stub_contents) % 2)
17758 && ((current_stub_contents - base_stub_contents) % 4))
17759 current_stub_contents =
17760 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17761 create_instruction_udf (0));
17762
17763 for (; current_stub_contents < end_stub_contents;)
17764 current_stub_contents =
17765 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17766 create_instruction_udf_w (0));
17767
17768 return current_stub_contents;
17769}
17770
17771/* Functions writing the stream of instructions equivalent to the
17772 derived sequence for ldmia, ldmdb, vldm respectively. */
17773
17774static void
17775stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
17776 bfd * output_bfd,
17777 const insn32 initial_insn,
17778 const bfd_byte *const initial_insn_addr,
17779 bfd_byte *const base_stub_contents)
17780{
17781 int wback = (initial_insn & 0x00200000) >> 21;
17782 int ri, rn = (initial_insn & 0x000F0000) >> 16;
17783 int insn_all_registers = initial_insn & 0x0000ffff;
17784 int insn_low_registers, insn_high_registers;
17785 int usable_register_mask;
b25e998d 17786 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 17787 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
17788 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
17789 bfd_byte *current_stub_contents = base_stub_contents;
17790
17791 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
17792
17793 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
17794 smaller than 8 registers load sequences that do not cause the
17795 hardware issue. */
17796 if (nb_registers <= 8)
17797 {
17798 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
17799 current_stub_contents =
17800 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17801 initial_insn);
17802
17803 /* B initial_insn_addr+4. */
17804 if (!restore_pc)
17805 current_stub_contents =
17806 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17807 create_instruction_branch_absolute
82188b29 17808 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17809
17810 /* Fill the remaining of the stub with deterministic contents. */
17811 current_stub_contents =
17812 stm32l4xx_fill_stub_udf (htab, output_bfd,
17813 base_stub_contents, current_stub_contents,
17814 base_stub_contents +
17815 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17816
17817 return;
17818 }
17819
17820 /* - reg_list[13] == 0. */
17821 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
17822
17823 /* - reg_list[14] & reg_list[15] != 1. */
17824 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
17825
17826 /* - if (wback==1) reg_list[rn] == 0. */
17827 BFD_ASSERT (!wback || !restore_rn);
17828
17829 /* - nb_registers > 8. */
b25e998d 17830 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 17831
17832 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
17833
17834 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
17835 - One with the 7 lowest registers (register mask 0x007F)
17836 This LDM will finally contain between 2 and 7 registers
17837 - One with the 7 highest registers (register mask 0xDF80)
17838 This ldm will finally contain between 2 and 7 registers. */
17839 insn_low_registers = insn_all_registers & 0x007F;
17840 insn_high_registers = insn_all_registers & 0xDF80;
17841
17842 /* A spare register may be needed during this veneer to temporarily
17843 handle the base register. This register will be restored with the
17844 last LDM operation.
17845 The usable register may be any general purpose register (that
17846 excludes PC, SP, LR : register mask is 0x1FFF). */
17847 usable_register_mask = 0x1FFF;
17848
17849 /* Generate the stub function. */
17850 if (wback)
17851 {
17852 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
17853 current_stub_contents =
17854 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17855 create_instruction_ldmia
17856 (rn, /*wback=*/1, insn_low_registers));
17857
17858 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
17859 current_stub_contents =
17860 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17861 create_instruction_ldmia
17862 (rn, /*wback=*/1, insn_high_registers));
17863 if (!restore_pc)
17864 {
17865 /* B initial_insn_addr+4. */
17866 current_stub_contents =
17867 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17868 create_instruction_branch_absolute
82188b29 17869 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17870 }
17871 }
17872 else /* if (!wback). */
17873 {
17874 ri = rn;
17875
17876 /* If Rn is not part of the high-register-list, move it there. */
17877 if (!(insn_high_registers & (1 << rn)))
17878 {
17879 /* Choose a Ri in the high-register-list that will be restored. */
17880 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
17881
17882 /* MOV Ri, Rn. */
17883 current_stub_contents =
17884 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17885 create_instruction_mov (ri, rn));
17886 }
17887
17888 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
17889 current_stub_contents =
17890 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17891 create_instruction_ldmia
17892 (ri, /*wback=*/1, insn_low_registers));
17893
17894 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
17895 current_stub_contents =
17896 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17897 create_instruction_ldmia
17898 (ri, /*wback=*/0, insn_high_registers));
17899
17900 if (!restore_pc)
17901 {
17902 /* B initial_insn_addr+4. */
17903 current_stub_contents =
17904 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17905 create_instruction_branch_absolute
82188b29 17906 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17907 }
17908 }
17909
17910 /* Fill the remaining of the stub with deterministic contents. */
17911 current_stub_contents =
17912 stm32l4xx_fill_stub_udf (htab, output_bfd,
17913 base_stub_contents, current_stub_contents,
17914 base_stub_contents +
17915 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17916}
17917
17918static void
17919stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
17920 bfd * output_bfd,
17921 const insn32 initial_insn,
17922 const bfd_byte *const initial_insn_addr,
17923 bfd_byte *const base_stub_contents)
17924{
17925 int wback = (initial_insn & 0x00200000) >> 21;
17926 int ri, rn = (initial_insn & 0x000f0000) >> 16;
17927 int insn_all_registers = initial_insn & 0x0000ffff;
17928 int insn_low_registers, insn_high_registers;
17929 int usable_register_mask;
17930 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
17931 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
b25e998d 17932 int nb_registers = elf32_arm_popcount (insn_all_registers);
a504d23a
LA		 17933 bfd_byte *current_stub_contents = base_stub_contents;
17934
17935 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
17936
17937 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
17938 smaller than 8 registers load sequences that do not cause the
17939 hardware issue. */
17940 if (nb_registers <= 8)
17941 {
17942 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
17943 current_stub_contents =
17944 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17945 initial_insn);
17946
17947 /* B initial_insn_addr+4. */
17948 current_stub_contents =
17949 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17950 create_instruction_branch_absolute
82188b29 17951 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17952
17953 /* Fill the remaining of the stub with deterministic contents. */
17954 current_stub_contents =
17955 stm32l4xx_fill_stub_udf (htab, output_bfd,
17956 base_stub_contents, current_stub_contents,
17957 base_stub_contents +
17958 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17959
17960 return;
17961 }
17962
17963 /* - reg_list[13] == 0. */
17964 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
17965
17966 /* - reg_list[14] & reg_list[15] != 1. */
17967 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
17968
17969 /* - if (wback==1) reg_list[rn] == 0. */
17970 BFD_ASSERT (!wback || !restore_rn);
17971
17972 /* - nb_registers > 8. */
b25e998d 17973 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
a504d23a
LA		 17974
17975 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
17976
17977 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
17978 - One with the 7 lowest registers (register mask 0x007F)
17979 This LDM will finally contain between 2 and 7 registers
17980 - One with the 7 highest registers (register mask 0xDF80)
17981 This ldm will finally contain between 2 and 7 registers. */
17982 insn_low_registers = insn_all_registers & 0x007F;
17983 insn_high_registers = insn_all_registers & 0xDF80;
17984
17985 /* A spare register may be needed during this veneer to temporarily
17986 handle the base register. This register will be restored with
17987 the last LDM operation.
17988 The usable register may be any general purpose register (that excludes
17989 PC, SP, LR : register mask is 0x1FFF). */
17990 usable_register_mask = 0x1FFF;
17991
17992 /* Generate the stub function. */
17993 if (!wback && !restore_pc && !restore_rn)
17994 {
17995 /* Choose a Ri in the low-register-list that will be restored. */
17996 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
17997
17998 /* MOV Ri, Rn. */
17999 current_stub_contents =
18000 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18001 create_instruction_mov (ri, rn));
18002
18003 /* LDMDB Ri!, {R-high-register-list}. */
18004 current_stub_contents =
18005 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18006 create_instruction_ldmdb
18007 (ri, /*wback=*/1, insn_high_registers));
18008
18009 /* LDMDB Ri, {R-low-register-list}. */
18010 current_stub_contents =
18011 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18012 create_instruction_ldmdb
18013 (ri, /*wback=*/0, insn_low_registers));
18014
18015 /* B initial_insn_addr+4. */
18016 current_stub_contents =
18017 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18018 create_instruction_branch_absolute
82188b29 18019 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18020 }
18021 else if (wback && !restore_pc && !restore_rn)
18022 {
18023 /* LDMDB Rn!, {R-high-register-list}. */
18024 current_stub_contents =
18025 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18026 create_instruction_ldmdb
18027 (rn, /*wback=*/1, insn_high_registers));
18028
18029 /* LDMDB Rn!, {R-low-register-list}. */
18030 current_stub_contents =
18031 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18032 create_instruction_ldmdb
18033 (rn, /*wback=*/1, insn_low_registers));
18034
18035 /* B initial_insn_addr+4. */
18036 current_stub_contents =
18037 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18038 create_instruction_branch_absolute
82188b29 18039 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18040 }
18041 else if (!wback && restore_pc && !restore_rn)
18042 {
18043 /* Choose a Ri in the high-register-list that will be restored. */
18044 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18045
18046 /* SUB Ri, Rn, #(4*nb_registers). */
18047 current_stub_contents =
18048 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18049 create_instruction_sub (ri, rn, (4 * nb_registers)));
18050
18051 /* LDMIA Ri!, {R-low-register-list}. */
18052 current_stub_contents =
18053 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18054 create_instruction_ldmia
18055 (ri, /*wback=*/1, insn_low_registers));
18056
18057 /* LDMIA Ri, {R-high-register-list}. */
18058 current_stub_contents =
18059 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18060 create_instruction_ldmia
18061 (ri, /*wback=*/0, insn_high_registers));
18062 }
18063 else if (wback && restore_pc && !restore_rn)
18064 {
18065 /* Choose a Ri in the high-register-list that will be restored. */
18066 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18067
18068 /* SUB Rn, Rn, #(4*nb_registers) */
18069 current_stub_contents =
18070 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18071 create_instruction_sub (rn, rn, (4 * nb_registers)));
18072
18073 /* MOV Ri, Rn. */
18074 current_stub_contents =
18075 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18076 create_instruction_mov (ri, rn));
18077
18078 /* LDMIA Ri!, {R-low-register-list}. */
18079 current_stub_contents =
18080 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18081 create_instruction_ldmia
18082 (ri, /*wback=*/1, insn_low_registers));
18083
18084 /* LDMIA Ri, {R-high-register-list}. */
18085 current_stub_contents =
18086 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18087 create_instruction_ldmia
18088 (ri, /*wback=*/0, insn_high_registers));
18089 }
18090 else if (!wback && !restore_pc && restore_rn)
18091 {
18092 ri = rn;
18093 if (!(insn_low_registers & (1 << rn)))
18094 {
18095 /* Choose a Ri in the low-register-list that will be restored. */
18096 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
18097
18098 /* MOV Ri, Rn. */
18099 current_stub_contents =
18100 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18101 create_instruction_mov (ri, rn));
18102 }
18103
18104 /* LDMDB Ri!, {R-high-register-list}. */
18105 current_stub_contents =
18106 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18107 create_instruction_ldmdb
18108 (ri, /*wback=*/1, insn_high_registers));
18109
18110 /* LDMDB Ri, {R-low-register-list}. */
18111 current_stub_contents =
18112 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18113 create_instruction_ldmdb
18114 (ri, /*wback=*/0, insn_low_registers));
18115
18116 /* B initial_insn_addr+4. */
18117 current_stub_contents =
18118 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18119 create_instruction_branch_absolute
82188b29 18120 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18121 }
18122 else if (!wback && restore_pc && restore_rn)
18123 {
18124 ri = rn;
18125 if (!(insn_high_registers & (1 << rn)))
18126 {
18127 /* Choose a Ri in the high-register-list that will be restored. */
18128 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18129 }
18130
18131 /* SUB Ri, Rn, #(4*nb_registers). */
18132 current_stub_contents =
18133 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18134 create_instruction_sub (ri, rn, (4 * nb_registers)));
18135
18136 /* LDMIA Ri!, {R-low-register-list}. */
18137 current_stub_contents =
18138 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18139 create_instruction_ldmia
18140 (ri, /*wback=*/1, insn_low_registers));
18141
18142 /* LDMIA Ri, {R-high-register-list}. */
18143 current_stub_contents =
18144 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18145 create_instruction_ldmia
18146 (ri, /*wback=*/0, insn_high_registers));
18147 }
18148 else if (wback && restore_rn)
18149 {
18150 /* The assembler should not have accepted to encode this. */
18151 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
18152 "undefined behavior.\n");
18153 }
18154
18155 /* Fill the remaining of the stub with deterministic contents. */
18156 current_stub_contents =
18157 stm32l4xx_fill_stub_udf (htab, output_bfd,
18158 base_stub_contents, current_stub_contents,
18159 base_stub_contents +
18160 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18161
18162}
18163
18164static void
18165stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
18166 bfd * output_bfd,
18167 const insn32 initial_insn,
18168 const bfd_byte *const initial_insn_addr,
18169 bfd_byte *const base_stub_contents)
18170{
9239bbd3 18171 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 18172 bfd_byte *current_stub_contents = base_stub_contents;
18173
18174 BFD_ASSERT (is_thumb2_vldm (initial_insn));
18175
18176 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 18177 smaller than 8 words load sequences that do not cause the
a504d23a 18178 hardware issue. */
9239bbd3 18179 if (num_words <= 8)
a504d23a
LA		 18180 {
18181 /* Untouched instruction. */
18182 current_stub_contents =
18183 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18184 initial_insn);
18185
18186 /* B initial_insn_addr+4. */
18187 current_stub_contents =
18188 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18189 create_instruction_branch_absolute
82188b29 18190 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18191 }
18192 else
18193 {
9eaff861 18194 bfd_boolean is_dp = /* DP encoding. */
9239bbd3 18195 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 18196 bfd_boolean is_ia_nobang = /* (IA without !). */
18197 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
18198 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
18199 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
18200 bfd_boolean is_db_bang = /* (DB with !). */
18201 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 18202 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 18203 /* d = UInt (Vd:D);. */
9239bbd3 18204 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 18205 | (((unsigned int)initial_insn << 9) >> 31);
18206
9239bbd3
CM		 18207 /* Compute the number of 8-words chunks needed to split. */
18208 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 18209 int chunk;
18210
18211 /* The test coverage has been done assuming the following
18212 hypothesis that exactly one of the previous is_ predicates is
18213 true. */
9239bbd3
CM		 18214 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
18215 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 18216
9239bbd3 18217 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 18218 cases, then we emit the adjustments:
18219
18220 vldm rx, {...}
18221 -> vldm rx!, {8_words_or_less} for each needed 8_word
18222 -> sub rx, rx, #size (list)
18223
18224 vldm rx!, {...}
18225 -> vldm rx!, {8_words_or_less} for each needed 8_word
18226 This also handles vpop instruction (when rx is sp)
18227
18228 vldmd rx!, {...}
18229 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 18230 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 18231 {
9239bbd3
CM		 18232 bfd_vma new_insn = 0;
18233
a504d23a
LA		 18234 if (is_ia_nobang || is_ia_bang)
18235 {
9239bbd3
CM		 18236 new_insn = create_instruction_vldmia
18237 (base_reg,
18238 is_dp,
18239 /*wback= . */1,
18240 chunks - (chunk + 1) ?
18241 8 : num_words - chunk * 8,
18242 first_reg + chunk * 8);
a504d23a
LA		 18243 }
18244 else if (is_db_bang)
18245 {
9239bbd3
CM		 18246 new_insn = create_instruction_vldmdb
18247 (base_reg,
18248 is_dp,
18249 chunks - (chunk + 1) ?
18250 8 : num_words - chunk * 8,
18251 first_reg + chunk * 8);
a504d23a 18252 }
9239bbd3
CM		 18253
18254 if (new_insn)
18255 current_stub_contents =
18256 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18257 new_insn);
a504d23a
LA		 18258 }
18259
18260 /* Only this case requires the base register compensation
18261 subtract. */
18262 if (is_ia_nobang)
18263 {
18264 current_stub_contents =
18265 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18266 create_instruction_sub
9239bbd3 18267 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 18268 }
18269
18270 /* B initial_insn_addr+4. */
18271 current_stub_contents =
18272 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18273 create_instruction_branch_absolute
82188b29 18274 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 18275 }
18276
18277 /* Fill the remaining of the stub with deterministic contents. */
18278 current_stub_contents =
18279 stm32l4xx_fill_stub_udf (htab, output_bfd,
18280 base_stub_contents, current_stub_contents,
18281 base_stub_contents +
18282 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
18283}
18284
18285static void
18286stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
18287 bfd * output_bfd,
18288 const insn32 wrong_insn,
18289 const bfd_byte *const wrong_insn_addr,
18290 bfd_byte *const stub_contents)
18291{
18292 if (is_thumb2_ldmia (wrong_insn))
18293 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
18294 wrong_insn, wrong_insn_addr,
18295 stub_contents);
18296 else if (is_thumb2_ldmdb (wrong_insn))
18297 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
18298 wrong_insn, wrong_insn_addr,
18299 stub_contents);
18300 else if (is_thumb2_vldm (wrong_insn))
18301 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
18302 wrong_insn, wrong_insn_addr,
18303 stub_contents);
18304}
18305
18306/* End of stm32l4xx work-around. */
18307
18308
e489d0ae
PB		 18309/* Do code byteswapping. Return FALSE afterwards so that the section is
18310 written out as normal. */
18311
18312static bfd_boolean
c7b8f16e 18313elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 18314 struct bfd_link_info *link_info,
18315 asection *sec,
e489d0ae
PB		 18316 bfd_byte *contents)
18317{
48229727 18318 unsigned int mapcount, errcount;
8e3de13a 18319 _arm_elf_section_data *arm_data;
c7b8f16e 18320 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 18321 elf32_arm_section_map *map;
c7b8f16e 18322 elf32_vfp11_erratum_list *errnode;
a504d23a 18323 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 18324 bfd_vma ptr;
18325 bfd_vma end;
c7b8f16e 18326 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 18327 bfd_byte tmp;
48229727 18328 unsigned int i;
57e8b36a 18329
4dfe6ac6
NC		 18330 if (globals == NULL)
18331 return FALSE;
18332
8e3de13a
NC		 18333 /* If this section has not been allocated an _arm_elf_section_data
18334 structure then we cannot record anything. */
18335 arm_data = get_arm_elf_section_data (sec);
18336 if (arm_data == NULL)
18337 return FALSE;
18338
18339 mapcount = arm_data->mapcount;
18340 map = arm_data->map;
c7b8f16e
JB		 18341 errcount = arm_data->erratumcount;
18342
18343 if (errcount != 0)
18344 {
18345 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
18346
18347 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 18348 errnode = errnode->next)
18349 {
18350 bfd_vma target = errnode->vma - offset;
18351
18352 switch (errnode->type)
18353 {
18354 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
18355 {
18356 bfd_vma branch_to_veneer;
18357 /* Original condition code of instruction, plus bit mask for
18358 ARM B instruction. */
18359 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
18360 | 0x0a000000;
c7b8f16e
JB		 18361
18362 /* The instruction is before the label. */
91d6fa6a 18363 target -= 4;
c7b8f16e
JB		 18364
18365 /* Above offset included in -4 below. */
18366 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 18367 - errnode->vma - 4;
c7b8f16e
JB		 18368
18369 if ((signed) branch_to_veneer < -(1 << 25)
18370 || (signed) branch_to_veneer >= (1 << 25))
871b3ab2 18371 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 18372 "range"), output_bfd);
c7b8f16e 18373
99059e56
RM		 18374 insn |= (branch_to_veneer >> 2) & 0xffffff;
18375 contents[endianflip ^ target] = insn & 0xff;
18376 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18377 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18378 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18379 }
18380 break;
c7b8f16e
JB		 18381
18382 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 18383 {
18384 bfd_vma branch_from_veneer;
18385 unsigned int insn;
c7b8f16e 18386
99059e56
RM		 18387 /* Take size of veneer into account. */
18388 branch_from_veneer = errnode->u.v.branch->vma
18389 - errnode->vma - 12;
c7b8f16e
JB		 18390
18391 if ((signed) branch_from_veneer < -(1 << 25)
18392 || (signed) branch_from_veneer >= (1 << 25))
871b3ab2 18393 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
4eca0228 18394 "range"), output_bfd);
c7b8f16e 18395
99059e56
RM		 18396 /* Original instruction. */
18397 insn = errnode->u.v.branch->u.b.vfp_insn;
18398 contents[endianflip ^ target] = insn & 0xff;
18399 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
18400 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
18401 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
18402
18403 /* Branch back to insn after original insn. */
18404 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
18405 contents[endianflip ^ (target + 4)] = insn & 0xff;
18406 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
18407 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
18408 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
18409 }
18410 break;
c7b8f16e 18411
99059e56
RM		 18412 default:
18413 abort ();
18414 }
18415 }
c7b8f16e 18416 }
e489d0ae 18417
a504d23a
LA		 18418 if (arm_data->stm32l4xx_erratumcount != 0)
18419 {
18420 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
18421 stm32l4xx_errnode != 0;
18422 stm32l4xx_errnode = stm32l4xx_errnode->next)
18423 {
18424 bfd_vma target = stm32l4xx_errnode->vma - offset;
18425
18426 switch (stm32l4xx_errnode->type)
18427 {
18428 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
18429 {
18430 unsigned int insn;
18431 bfd_vma branch_to_veneer =
18432 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
18433
18434 if ((signed) branch_to_veneer < -(1 << 24)
18435 || (signed) branch_to_veneer >= (1 << 24))
18436 {
18437 bfd_vma out_of_range =
18438 ((signed) branch_to_veneer < -(1 << 24)) ?
18439 - branch_to_veneer - (1 << 24) :
18440 ((signed) branch_to_veneer >= (1 << 24)) ?
18441 branch_to_veneer - (1 << 24) : 0;
18442
4eca0228 18443 _bfd_error_handler
2dcf00ce 18444 (_("%pB(%#" PRIx64 "): error: "
90b6238f
AM		 18445 "cannot create STM32L4XX veneer; "
18446 "jump out of range by %" PRId64 " bytes; "
18447 "cannot encode branch instruction"),
a504d23a 18448 output_bfd,
2dcf00ce
AM		 18449 (uint64_t) (stm32l4xx_errnode->vma - 4),
18450 (int64_t) out_of_range);
a504d23a
LA		 18451 continue;
18452 }
18453
18454 insn = create_instruction_branch_absolute
82188b29 18455 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 18456
18457 /* The instruction is before the label. */
18458 target -= 4;
18459
18460 put_thumb2_insn (globals, output_bfd,
18461 (bfd_vma) insn, contents + target);
18462 }
18463 break;
18464
18465 case STM32L4XX_ERRATUM_VENEER:
18466 {
82188b29
NC		 18467 bfd_byte * veneer;
18468 bfd_byte * veneer_r;
a504d23a
LA		 18469 unsigned int insn;
18470
82188b29
NC		 18471 veneer = contents + target;
18472 veneer_r = veneer
18473 + stm32l4xx_errnode->u.b.veneer->vma
18474 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 18475
18476 if ((signed) (veneer_r - veneer -
18477 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
18478 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
18479 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
18480 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
18481 || (signed) (veneer_r - veneer) >= (1 << 24))
18482 {
90b6238f
AM		 18483 _bfd_error_handler (_("%pB: error: cannot create STM32L4XX "
18484 "veneer"), output_bfd);
a504d23a
LA		 18485 continue;
18486 }
18487
18488 /* Original instruction. */
18489 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
18490
18491 stm32l4xx_create_replacing_stub
18492 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
18493 }
18494 break;
18495
18496 default:
18497 abort ();
18498 }
18499 }
18500 }
18501
2468f9c9
PB		 18502 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
18503 {
18504 arm_unwind_table_edit *edit_node
99059e56 18505 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 18506 /* Now, sec->size is the size of the section we will write. The original
99059e56 18507 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 18508 markers) was sec->rawsize. (This isn't the case if we perform no
18509 edits, then rawsize will be zero and we should use size). */
21d799b5 18510 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 18511 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
18512 unsigned int in_index, out_index;
18513 bfd_vma add_to_offsets = 0;
18514
18515 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 18516 {
2468f9c9
PB		 18517 if (edit_node)
18518 {
18519 unsigned int edit_index = edit_node->index;
b38cadfb 18520
2468f9c9 18521 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 18522 {
2468f9c9
PB		 18523 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18524 contents + in_index * 8, add_to_offsets);
18525 out_index++;
18526 in_index++;
18527 }
18528 else if (in_index == edit_index
18529 || (in_index * 8 >= input_size
18530 && edit_index == UINT_MAX))
99059e56 18531 {
2468f9c9
PB		 18532 switch (edit_node->type)
18533 {
18534 case DELETE_EXIDX_ENTRY:
18535 in_index++;
18536 add_to_offsets += 8;
18537 break;
b38cadfb 18538
2468f9c9
PB		 18539 case INSERT_EXIDX_CANTUNWIND_AT_END:
18540 {
99059e56 18541 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 18542 bfd_vma text_offset = text_sec->output_section->vma
18543 + text_sec->output_offset
18544 + text_sec->size;
18545 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 18546 unsigned long prel31_offset;
2468f9c9
PB		 18547
18548 /* Note: this is meant to be equivalent to an
18549 R_ARM_PREL31 relocation. These synthetic
18550 EXIDX_CANTUNWIND markers are not relocated by the
18551 usual BFD method. */
18552 prel31_offset = (text_offset - exidx_offset)
18553 & 0x7ffffffful;
491d01d3
YU		 18554 if (bfd_link_relocatable (link_info))
18555 {
18556 /* Here relocation for new EXIDX_CANTUNWIND is
18557 created, so there is no need to
18558 adjust offset by hand. */
18559 prel31_offset = text_sec->output_offset
18560 + text_sec->size;
491d01d3 18561 }
2468f9c9
PB		 18562
18563 /* First address we can't unwind. */
18564 bfd_put_32 (output_bfd, prel31_offset,
18565 &edited_contents[out_index * 8]);
18566
18567 /* Code for EXIDX_CANTUNWIND. */
18568 bfd_put_32 (output_bfd, 0x1,
18569 &edited_contents[out_index * 8 + 4]);
18570
18571 out_index++;
18572 add_to_offsets -= 8;
18573 }
18574 break;
18575 }
b38cadfb 18576
2468f9c9
PB		 18577 edit_node = edit_node->next;
18578 }
18579 }
18580 else
18581 {
18582 /* No more edits, copy remaining entries verbatim. */
18583 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
18584 contents + in_index * 8, add_to_offsets);
18585 out_index++;
18586 in_index++;
18587 }
18588 }
18589
18590 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
18591 bfd_set_section_contents (output_bfd, sec->output_section,
18592 edited_contents,
18593 (file_ptr) sec->output_offset, sec->size);
18594
18595 return TRUE;
18596 }
18597
48229727
JB		 18598 /* Fix code to point to Cortex-A8 erratum stubs. */
18599 if (globals->fix_cortex_a8)
18600 {
18601 struct a8_branch_to_stub_data data;
18602
18603 data.writing_section = sec;
18604 data.contents = contents;
18605
a504d23a
LA		 18606 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
18607 & data);
48229727
JB		 18608 }
18609
e489d0ae
PB		 18610 if (mapcount == 0)
18611 return FALSE;
18612
c7b8f16e 18613 if (globals->byteswap_code)
e489d0ae 18614 {
c7b8f16e 18615 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 18616
c7b8f16e
JB		 18617 ptr = map[0].vma;
18618 for (i = 0; i < mapcount; i++)
99059e56
RM		 18619 {
18620 if (i == mapcount - 1)
c7b8f16e 18621 end = sec->size;
99059e56
RM		 18622 else
18623 end = map[i + 1].vma;
e489d0ae 18624
99059e56 18625 switch (map[i].type)
e489d0ae 18626 {
c7b8f16e
JB		 18627 case 'a':
18628 /* Byte swap code words. */
18629 while (ptr + 3 < end)
99059e56
RM		 18630 {
18631 tmp = contents[ptr];
18632 contents[ptr] = contents[ptr + 3];
18633 contents[ptr + 3] = tmp;
18634 tmp = contents[ptr + 1];
18635 contents[ptr + 1] = contents[ptr + 2];
18636 contents[ptr + 2] = tmp;
18637 ptr += 4;
18638 }
c7b8f16e 18639 break;
e489d0ae 18640
c7b8f16e
JB		 18641 case 't':
18642 /* Byte swap code halfwords. */
18643 while (ptr + 1 < end)
99059e56
RM		 18644 {
18645 tmp = contents[ptr];
18646 contents[ptr] = contents[ptr + 1];
18647 contents[ptr + 1] = tmp;
18648 ptr += 2;
18649 }
c7b8f16e
JB		 18650 break;
18651
18652 case 'd':
18653 /* Leave data alone. */
18654 break;
18655 }
99059e56
RM		 18656 ptr = end;
18657 }
e489d0ae 18658 }
8e3de13a 18659
93204d3a 18660 free (map);
47b2e99c 18661 arm_data->mapcount = -1;
c7b8f16e 18662 arm_data->mapsize = 0;
8e3de13a 18663 arm_data->map = NULL;
8e3de13a 18664
e489d0ae
PB		 18665 return FALSE;
18666}
18667
0beaef2b
PB		 18668/* Mangle thumb function symbols as we read them in. */
18669
8384fb8f 18670static bfd_boolean
0beaef2b
PB		 18671elf32_arm_swap_symbol_in (bfd * abfd,
18672 const void *psrc,
18673 const void *pshn,
18674 Elf_Internal_Sym *dst)
18675{
4ba2ef8f
TP		 18676 Elf_Internal_Shdr *symtab_hdr;
18677 const char *name = NULL;
18678
8384fb8f
AM		 18679 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
18680 return FALSE;
39d911fc 18681 dst->st_target_internal = 0;
0beaef2b
PB		 18682
18683 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 18684 the address. */
63e1a0fc
PB		 18685 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
18686 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 18687 {
63e1a0fc
PB		 18688 if (dst->st_value & 1)
18689 {
18690 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 18691 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
18692 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 18693 }
18694 else
39d911fc 18695 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 18696 }
18697 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
18698 {
18699 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 18700 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 18701 }
35fc36a8 18702 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 18703 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 18704 else
39d911fc 18705 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 18706
4ba2ef8f
TP		 18707 /* Mark CMSE special symbols. */
18708 symtab_hdr = & elf_symtab_hdr (abfd);
18709 if (symtab_hdr->sh_size)
18710 name = bfd_elf_sym_name (abfd, symtab_hdr, dst, NULL);
18711 if (name && CONST_STRNEQ (name, CMSE_PREFIX))
18712 ARM_SET_SYM_CMSE_SPCL (dst->st_target_internal);
18713
8384fb8f 18714 return TRUE;
0beaef2b
PB		 18715}
18716
18717
18718/* Mangle thumb function symbols as we write them out. */
18719
18720static void
18721elf32_arm_swap_symbol_out (bfd *abfd,
18722 const Elf_Internal_Sym *src,
18723 void *cdst,
18724 void *shndx)
18725{
18726 Elf_Internal_Sym newsym;
18727
18728 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
18729 of the address set, as per the new EABI. We do this unconditionally
18730 because objcopy does not set the elf header flags until after
18731 it writes out the symbol table. */
39d911fc 18732 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 18733 {
18734 newsym = *src;
34e77a92
RS		 18735 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
18736 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 18737 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 18738 {
18739 /* Do this only for defined symbols. At link type, the static
18740 linker will simulate the work of dynamic linker of resolving
18741 symbols and will carry over the thumbness of found symbols to
18742 the output symbol table. It's not clear how it happens, but
18743 the thumbness of undefined symbols can well be different at
18744 runtime, and writing '1' for them will be confusing for users
18745 and possibly for dynamic linker itself.
18746 */
18747 newsym.st_value |= 1;
18748 }
906e58ca 18749
0beaef2b
PB		 18750 src = &newsym;
18751 }
18752 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
18753}
18754
b294bdf8
MM		 18755/* Add the PT_ARM_EXIDX program header. */
18756
18757static bfd_boolean
906e58ca 18758elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 18759 struct bfd_link_info *info ATTRIBUTE_UNUSED)
18760{
18761 struct elf_segment_map *m;
18762 asection *sec;
18763
18764 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18765 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18766 {
18767 /* If there is already a PT_ARM_EXIDX header, then we do not
18768 want to add another one. This situation arises when running
18769 "strip"; the input binary already has the header. */
12bd6957 18770 m = elf_seg_map (abfd);
b294bdf8
MM		 18771 while (m && m->p_type != PT_ARM_EXIDX)
18772 m = m->next;
18773 if (!m)
18774 {
21d799b5 18775 m = (struct elf_segment_map *)
99059e56 18776 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 18777 if (m == NULL)
18778 return FALSE;
18779 m->p_type = PT_ARM_EXIDX;
18780 m->count = 1;
18781 m->sections[0] = sec;
18782
12bd6957
AM		 18783 m->next = elf_seg_map (abfd);
18784 elf_seg_map (abfd) = m;
b294bdf8
MM		 18785 }
18786 }
18787
18788 return TRUE;
18789}
18790
18791/* We may add a PT_ARM_EXIDX program header. */
18792
18793static int
a6b96beb
AM		 18794elf32_arm_additional_program_headers (bfd *abfd,
18795 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 18796{
18797 asection *sec;
18798
18799 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
18800 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
18801 return 1;
18802 else
18803 return 0;
18804}
18805
34e77a92
RS		 18806/* Hook called by the linker routine which adds symbols from an object
18807 file. */
18808
18809static bfd_boolean
18810elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
18811 Elf_Internal_Sym *sym, const char **namep,
18812 flagword *flagsp, asection **secp, bfd_vma *valp)
18813{
a43942db 18814 if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
f1885d1e
AM		 18815 && (abfd->flags & DYNAMIC) == 0
18816 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
a43942db 18817 elf_tdata (info->output_bfd)->has_gnu_symbols |= elf_gnu_symbol_ifunc;
34e77a92 18818
c792917c
NC		 18819 if (elf32_arm_hash_table (info) == NULL)
18820 return FALSE;
18821
34e77a92
RS		 18822 if (elf32_arm_hash_table (info)->vxworks_p
18823 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
18824 flagsp, secp, valp))
18825 return FALSE;
18826
18827 return TRUE;
18828}
18829
0beaef2b 18830/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 18831const struct elf_size_info elf32_arm_size_info =
18832{
0beaef2b
PB		 18833 sizeof (Elf32_External_Ehdr),
18834 sizeof (Elf32_External_Phdr),
18835 sizeof (Elf32_External_Shdr),
18836 sizeof (Elf32_External_Rel),
18837 sizeof (Elf32_External_Rela),
18838 sizeof (Elf32_External_Sym),
18839 sizeof (Elf32_External_Dyn),
18840 sizeof (Elf_External_Note),
18841 4,
18842 1,
18843 32, 2,
18844 ELFCLASS32, EV_CURRENT,
18845 bfd_elf32_write_out_phdrs,
18846 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 18847 bfd_elf32_checksum_contents,
0beaef2b
PB		 18848 bfd_elf32_write_relocs,
18849 elf32_arm_swap_symbol_in,
18850 elf32_arm_swap_symbol_out,
18851 bfd_elf32_slurp_reloc_table,
18852 bfd_elf32_slurp_symbol_table,
18853 bfd_elf32_swap_dyn_in,
18854 bfd_elf32_swap_dyn_out,
18855 bfd_elf32_swap_reloc_in,
18856 bfd_elf32_swap_reloc_out,
18857 bfd_elf32_swap_reloca_in,
18858 bfd_elf32_swap_reloca_out
18859};
18860
685e70ae
VK		 18861static bfd_vma
18862read_code32 (const bfd *abfd, const bfd_byte *addr)
18863{
18864 /* V7 BE8 code is always little endian. */
18865 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18866 return bfd_getl32 (addr);
18867
18868 return bfd_get_32 (abfd, addr);
18869}
18870
18871static bfd_vma
18872read_code16 (const bfd *abfd, const bfd_byte *addr)
18873{
18874 /* V7 BE8 code is always little endian. */
18875 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
18876 return bfd_getl16 (addr);
18877
18878 return bfd_get_16 (abfd, addr);
18879}
18880
6a631e86
YG		 18881/* Return size of plt0 entry starting at ADDR
18882 or (bfd_vma) -1 if size can not be determined. */
18883
18884static bfd_vma
18885elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
18886{
18887 bfd_vma first_word;
18888 bfd_vma plt0_size;
18889
685e70ae 18890 first_word = read_code32 (abfd, addr);
6a631e86
YG		 18891
18892 if (first_word == elf32_arm_plt0_entry[0])
18893 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
18894 else if (first_word == elf32_thumb2_plt0_entry[0])
18895 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
18896 else
18897 /* We don't yet handle this PLT format. */
18898 return (bfd_vma) -1;
18899
18900 return plt0_size;
18901}
18902
18903/* Return size of plt entry starting at offset OFFSET
18904 of plt section located at address START
18905 or (bfd_vma) -1 if size can not be determined. */
18906
18907static bfd_vma
18908elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
18909{
18910 bfd_vma first_insn;
18911 bfd_vma plt_size = 0;
18912 const bfd_byte *addr = start + offset;
18913
18914 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 18915 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 18916 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
18917
18918 /* Respect Thumb stub if necessary. */
685e70ae 18919 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 18920 {
18921 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
18922 }
18923
18924 /* Strip immediate from first add. */
685e70ae 18925 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 18926
18927#ifdef FOUR_WORD_PLT
18928 if (first_insn == elf32_arm_plt_entry[0])
18929 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
18930#else
18931 if (first_insn == elf32_arm_plt_entry_long[0])
18932 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
18933 else if (first_insn == elf32_arm_plt_entry_short[0])
18934 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
18935#endif
18936 else
18937 /* We don't yet handle this PLT format. */
18938 return (bfd_vma) -1;
18939
18940 return plt_size;
18941}
18942
18943/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
18944
18945static long
18946elf32_arm_get_synthetic_symtab (bfd *abfd,
18947 long symcount ATTRIBUTE_UNUSED,
18948 asymbol **syms ATTRIBUTE_UNUSED,
18949 long dynsymcount,
18950 asymbol **dynsyms,
18951 asymbol **ret)
18952{
18953 asection *relplt;
18954 asymbol *s;
18955 arelent *p;
18956 long count, i, n;
18957 size_t size;
18958 Elf_Internal_Shdr *hdr;
18959 char *names;
18960 asection *plt;
18961 bfd_vma offset;
18962 bfd_byte *data;
18963
18964 *ret = NULL;
18965
18966 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
18967 return 0;
18968
18969 if (dynsymcount <= 0)
18970 return 0;
18971
18972 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
18973 if (relplt == NULL)
18974 return 0;
18975
18976 hdr = &elf_section_data (relplt)->this_hdr;
18977 if (hdr->sh_link != elf_dynsymtab (abfd)
18978 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
18979 return 0;
18980
18981 plt = bfd_get_section_by_name (abfd, ".plt");
18982 if (plt == NULL)
18983 return 0;
18984
18985 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
18986 return -1;
18987
18988 data = plt->contents;
18989 if (data == NULL)
18990 {
18991 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
18992 return -1;
18993 bfd_cache_section_contents((asection *) plt, data);
18994 }
18995
18996 count = relplt->size / hdr->sh_entsize;
18997 size = count * sizeof (asymbol);
18998 p = relplt->relocation;
18999 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19000 {
19001 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
19002 if (p->addend != 0)
19003 size += sizeof ("+0x") - 1 + 8;
19004 }
19005
19006 s = *ret = (asymbol *) bfd_malloc (size);
19007 if (s == NULL)
19008 return -1;
19009
19010 offset = elf32_arm_plt0_size (abfd, data);
19011 if (offset == (bfd_vma) -1)
19012 return -1;
19013
19014 names = (char *) (s + count);
19015 p = relplt->relocation;
19016 n = 0;
19017 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
19018 {
19019 size_t len;
19020
19021 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
19022 if (plt_size == (bfd_vma) -1)
19023 break;
19024
19025 *s = **p->sym_ptr_ptr;
19026 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
19027 we are defining a symbol, ensure one of them is set. */
19028 if ((s->flags & BSF_LOCAL) == 0)
19029 s->flags |= BSF_GLOBAL;
19030 s->flags |= BSF_SYNTHETIC;
19031 s->section = plt;
19032 s->value = offset;
19033 s->name = names;
19034 s->udata.p = NULL;
19035 len = strlen ((*p->sym_ptr_ptr)->name);
19036 memcpy (names, (*p->sym_ptr_ptr)->name, len);
19037 names += len;
19038 if (p->addend != 0)
19039 {
19040 char buf[30], *a;
19041
19042 memcpy (names, "+0x", sizeof ("+0x") - 1);
19043 names += sizeof ("+0x") - 1;
19044 bfd_sprintf_vma (abfd, buf, p->addend);
19045 for (a = buf; *a == '0'; ++a)
19046 ;
19047 len = strlen (a);
19048 memcpy (names, a, len);
19049 names += len;
19050 }
19051 memcpy (names, "@plt", sizeof ("@plt"));
19052 names += sizeof ("@plt");
19053 ++s, ++n;
19054 offset += plt_size;
19055 }
19056
19057 return n;
19058}
19059
ac4c9b04
MG		 19060static bfd_boolean
19061elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
19062{
f0728ee3
AV		 19063 if (hdr->sh_flags & SHF_ARM_PURECODE)
19064 *flags |= SEC_ELF_PURECODE;
ac4c9b04
MG		 19065 return TRUE;
19066}
19067
19068static flagword
19069elf32_arm_lookup_section_flags (char *flag_name)
19070{
f0728ee3
AV		 19071 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
19072 return SHF_ARM_PURECODE;
ac4c9b04
MG		 19073
19074 return SEC_NO_FLAGS;
19075}
19076
491d01d3
YU		 19077static unsigned int
19078elf32_arm_count_additional_relocs (asection *sec)
19079{
19080 struct _arm_elf_section_data *arm_data;
19081 arm_data = get_arm_elf_section_data (sec);
5025eb7c 19082
6342be70 19083 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
491d01d3
YU		 19084}
19085
5522f910 19086/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
9eaff861 19087 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
5522f910
NC		 19088 FALSE otherwise. ISECTION is the best guess matching section from the
19089 input bfd IBFD, but it might be NULL. */
19090
19091static bfd_boolean
19092elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
19093 bfd *obfd ATTRIBUTE_UNUSED,
19094 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
19095 Elf_Internal_Shdr *osection)
19096{
19097 switch (osection->sh_type)
19098 {
19099 case SHT_ARM_EXIDX:
19100 {
19101 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
19102 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
19103 unsigned i = 0;
19104
19105 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
19106 osection->sh_info = 0;
19107
19108 /* The sh_link field must be set to the text section associated with
19109 this index section. Unfortunately the ARM EHABI does not specify
19110 exactly how to determine this association. Our caller does try
19111 to match up OSECTION with its corresponding input section however
19112 so that is a good first guess. */
19113 if (isection != NULL
19114 && osection->bfd_section != NULL
19115 && isection->bfd_section != NULL
19116 && isection->bfd_section->output_section != NULL
19117 && isection->bfd_section->output_section == osection->bfd_section
19118 && iheaders != NULL
19119 && isection->sh_link > 0
19120 && isection->sh_link < elf_numsections (ibfd)
19121 && iheaders[isection->sh_link]->bfd_section != NULL
19122 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
19123 )
19124 {
19125 for (i = elf_numsections (obfd); i-- > 0;)
19126 if (oheaders[i]->bfd_section
19127 == iheaders[isection->sh_link]->bfd_section->output_section)
19128 break;
19129 }
9eaff861 19130
5522f910
NC		 19131 if (i == 0)
19132 {
19133 /* Failing that we have to find a matching section ourselves. If
19134 we had the output section name available we could compare that
19135 with input section names. Unfortunately we don't. So instead
19136 we use a simple heuristic and look for the nearest executable
19137 section before this one. */
19138 for (i = elf_numsections (obfd); i-- > 0;)
19139 if (oheaders[i] == osection)
19140 break;
19141 if (i == 0)
19142 break;
19143
19144 while (i-- > 0)
19145 if (oheaders[i]->sh_type == SHT_PROGBITS
19146 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
19147 == (SHF_ALLOC | SHF_EXECINSTR))
19148 break;
19149 }
19150
19151 if (i)
19152 {
19153 osection->sh_link = i;
19154 /* If the text section was part of a group
19155 then the index section should be too. */
19156 if (oheaders[i]->sh_flags & SHF_GROUP)
19157 osection->sh_flags |= SHF_GROUP;
19158 return TRUE;
19159 }
19160 }
19161 break;
19162
19163 case SHT_ARM_PREEMPTMAP:
19164 osection->sh_flags = SHF_ALLOC;
19165 break;
19166
19167 case SHT_ARM_ATTRIBUTES:
19168 case SHT_ARM_DEBUGOVERLAY:
19169 case SHT_ARM_OVERLAYSECTION:
19170 default:
19171 break;
19172 }
19173
19174 return FALSE;
19175}
19176
d691934d
NC		 19177/* Returns TRUE if NAME is an ARM mapping symbol.
19178 Traditionally the symbols $a, $d and $t have been used.
19179 The ARM ELF standard also defines $x (for A64 code). It also allows a
19180 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
19181 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
19182 not support them here. $t.x indicates the start of ThumbEE instructions. */
19183
19184static bfd_boolean
19185is_arm_mapping_symbol (const char * name)
19186{
19187 return name != NULL /* Paranoia. */
19188 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
19189 the mapping symbols could have acquired a prefix.
19190 We do not support this here, since such symbols no
19191 longer conform to the ARM ELF ABI. */
19192 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
19193 && (name[2] == 0 || name[2] == '.');
19194 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
19195 any characters that follow the period are legal characters for the body
19196 of a symbol's name. For now we just assume that this is the case. */
19197}
19198
fca2a38f
NC		 19199/* Make sure that mapping symbols in object files are not removed via the
19200 "strip --strip-unneeded" tool. These symbols are needed in order to
19201 correctly generate interworking veneers, and for byte swapping code
19202 regions. Once an object file has been linked, it is safe to remove the
19203 symbols as they will no longer be needed. */
19204
19205static void
19206elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
19207{
19208 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
fca2a38f 19209 && sym->section != bfd_abs_section_ptr
d691934d 19210 && is_arm_mapping_symbol (sym->name))
fca2a38f
NC		 19211 sym->flags |= BSF_KEEP;
19212}
19213
5522f910
NC		 19214#undef elf_backend_copy_special_section_fields
19215#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
19216
252b5132 19217#define ELF_ARCH bfd_arch_arm
ae95ffa6 19218#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 19219#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 19220#ifdef __QNXTARGET__
19221#define ELF_MAXPAGESIZE 0x1000
19222#else
7572ca89 19223#define ELF_MAXPAGESIZE 0x10000
d0facd1b 19224#endif
b1342370 19225#define ELF_MINPAGESIZE 0x1000
24718e3b 19226#define ELF_COMMONPAGESIZE 0x1000
252b5132 19227
07d6d2b8 19228#define bfd_elf32_mkobject elf32_arm_mkobject
ba93b8ac 19229
99e4ae17
AJ		 19230#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
19231#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 19232#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
19233#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
07d6d2b8 19234#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 19235#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 19236#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
07d6d2b8
AM		 19237#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
19238#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 19239#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 19240#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 19241#define bfd_elf32_bfd_final_link elf32_arm_final_link
07d6d2b8 19242#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132 19243
07d6d2b8
AM		 19244#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
19245#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 19246#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
07d6d2b8 19247#define elf_backend_check_relocs elf32_arm_check_relocs
9eaff861 19248#define elf_backend_update_relocs elf32_arm_update_relocs
dc810e39 19249#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 19250#define elf_backend_write_section elf32_arm_write_section
252b5132 19251#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
07d6d2b8 19252#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 19253#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
19254#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
19255#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 19256#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 19257#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 19258#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 19259#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 19260#define elf_backend_object_p elf32_arm_object_p
07d6d2b8
AM		 19261#define elf_backend_fake_sections elf32_arm_fake_sections
19262#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
19263#define elf_backend_final_write_processing elf32_arm_final_write_processing
19264#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 19265#define elf_backend_size_info elf32_arm_size_info
b294bdf8 19266#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
07d6d2b8
AM		 19267#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
19268#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
54ddd295 19269#define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
07d6d2b8 19270#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 19271#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 19272#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
fca2a38f 19273#define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
906e58ca
NC		 19274
19275#define elf_backend_can_refcount 1
19276#define elf_backend_can_gc_sections 1
19277#define elf_backend_plt_readonly 1
19278#define elf_backend_want_got_plt 1
19279#define elf_backend_want_plt_sym 0
5474d94f 19280#define elf_backend_want_dynrelro 1
906e58ca
NC		 19281#define elf_backend_may_use_rel_p 1
19282#define elf_backend_may_use_rela_p 0
4e7fd91e 19283#define elf_backend_default_use_rela_p 0
64f52338 19284#define elf_backend_dtrel_excludes_plt 1
252b5132 19285
04f7c78d 19286#define elf_backend_got_header_size 12
b68a20d6 19287#define elf_backend_extern_protected_data 1
04f7c78d 19288
07d6d2b8 19289#undef elf_backend_obj_attrs_vendor
906e58ca 19290#define elf_backend_obj_attrs_vendor "aeabi"
07d6d2b8 19291#undef elf_backend_obj_attrs_section
906e58ca 19292#define elf_backend_obj_attrs_section ".ARM.attributes"
07d6d2b8 19293#undef elf_backend_obj_attrs_arg_type
906e58ca 19294#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
07d6d2b8 19295#undef elf_backend_obj_attrs_section_type
104d59d1 19296#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb 19297#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
07d6d2b8 19298#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 19299
07d6d2b8 19300#undef elf_backend_section_flags
ac4c9b04 19301#define elf_backend_section_flags elf32_arm_section_flags
07d6d2b8
AM		 19302#undef elf_backend_lookup_section_flags_hook
19303#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
ac4c9b04 19304
a2f63b2e
MR		 19305#define elf_backend_linux_prpsinfo32_ugid16 TRUE
19306
252b5132 19307#include "elf32-target.h"
7f266840 19308
b38cadfb
NC		 19309/* Native Client targets. */
19310
19311#undef TARGET_LITTLE_SYM
6d00b590 19312#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 19313#undef TARGET_LITTLE_NAME
19314#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
19315#undef TARGET_BIG_SYM
6d00b590 19316#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 19317#undef TARGET_BIG_NAME
19318#define TARGET_BIG_NAME "elf32-bigarm-nacl"
19319
19320/* Like elf32_arm_link_hash_table_create -- but overrides
19321 appropriately for NaCl. */
19322
19323static struct bfd_link_hash_table *
19324elf32_arm_nacl_link_hash_table_create (bfd *abfd)
19325{
19326 struct bfd_link_hash_table *ret;
19327
19328 ret = elf32_arm_link_hash_table_create (abfd);
19329 if (ret)
19330 {
19331 struct elf32_arm_link_hash_table *htab
19332 = (struct elf32_arm_link_hash_table *) ret;
19333
19334 htab->nacl_p = 1;
19335
19336 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
19337 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
19338 }
19339 return ret;
19340}
19341
19342/* Since NaCl doesn't use the ARM-specific unwind format, we don't
19343 really need to use elf32_arm_modify_segment_map. But we do it
19344 anyway just to reduce gratuitous differences with the stock ARM backend. */
19345
19346static bfd_boolean
19347elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
19348{
19349 return (elf32_arm_modify_segment_map (abfd, info)
19350 && nacl_modify_segment_map (abfd, info));
19351}
19352
887badb3
RM		 19353static void
19354elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
19355{
19356 elf32_arm_final_write_processing (abfd, linker);
19357 nacl_final_write_processing (abfd, linker);
19358}
19359
6a631e86
YG		 19360static bfd_vma
19361elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
19362 const arelent *rel ATTRIBUTE_UNUSED)
19363{
19364 return plt->vma
19365 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
19366 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
19367}
887badb3 19368
b38cadfb 19369#undef elf32_bed
6a631e86 19370#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 19371#undef bfd_elf32_bfd_link_hash_table_create
19372#define bfd_elf32_bfd_link_hash_table_create \
19373 elf32_arm_nacl_link_hash_table_create
19374#undef elf_backend_plt_alignment
6a631e86 19375#define elf_backend_plt_alignment 4
b38cadfb
NC		 19376#undef elf_backend_modify_segment_map
19377#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
19378#undef elf_backend_modify_program_headers
19379#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 19380#undef elf_backend_final_write_processing
19381#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 19382#undef bfd_elf32_get_synthetic_symtab
19383#undef elf_backend_plt_sym_val
19384#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 19385#undef elf_backend_copy_special_section_fields
b38cadfb 19386
887badb3
RM		 19387#undef ELF_MINPAGESIZE
19388#undef ELF_COMMONPAGESIZE
19389
b38cadfb
NC		 19390
19391#include "elf32-target.h"
19392
19393/* Reset to defaults. */
19394#undef elf_backend_plt_alignment
19395#undef elf_backend_modify_segment_map
19396#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
19397#undef elf_backend_modify_program_headers
887badb3
RM		 19398#undef elf_backend_final_write_processing
19399#define elf_backend_final_write_processing elf32_arm_final_write_processing
19400#undef ELF_MINPAGESIZE
19401#define ELF_MINPAGESIZE 0x1000
19402#undef ELF_COMMONPAGESIZE
19403#define ELF_COMMONPAGESIZE 0x1000
19404
b38cadfb 19405
906e58ca 19406/* VxWorks Targets. */
4e7fd91e 19407
07d6d2b8
AM		 19408#undef TARGET_LITTLE_SYM
19409#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
19410#undef TARGET_LITTLE_NAME
19411#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
19412#undef TARGET_BIG_SYM
19413#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
19414#undef TARGET_BIG_NAME
19415#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
4e7fd91e
PB		 19416
19417/* Like elf32_arm_link_hash_table_create -- but overrides
19418 appropriately for VxWorks. */
906e58ca 19419
4e7fd91e
PB		 19420static struct bfd_link_hash_table *
19421elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
19422{
19423 struct bfd_link_hash_table *ret;
19424
19425 ret = elf32_arm_link_hash_table_create (abfd);
19426 if (ret)
19427 {
19428 struct elf32_arm_link_hash_table *htab
00a97672 19429 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 19430 htab->use_rel = 0;
00a97672 19431 htab->vxworks_p = 1;
4e7fd91e
PB		 19432 }
19433 return ret;
906e58ca 19434}
4e7fd91e 19435
00a97672
RS		 19436static void
19437elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
19438{
19439 elf32_arm_final_write_processing (abfd, linker);
19440 elf_vxworks_final_write_processing (abfd, linker);
19441}
19442
906e58ca 19443#undef elf32_bed
4e7fd91e
PB		 19444#define elf32_bed elf32_arm_vxworks_bed
19445
906e58ca
NC		 19446#undef bfd_elf32_bfd_link_hash_table_create
19447#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 19448#undef elf_backend_final_write_processing
19449#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
19450#undef elf_backend_emit_relocs
9eaff861 19451#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 19452
906e58ca 19453#undef elf_backend_may_use_rel_p
00a97672 19454#define elf_backend_may_use_rel_p 0
906e58ca 19455#undef elf_backend_may_use_rela_p
00a97672 19456#define elf_backend_may_use_rela_p 1
906e58ca 19457#undef elf_backend_default_use_rela_p
00a97672 19458#define elf_backend_default_use_rela_p 1
906e58ca 19459#undef elf_backend_want_plt_sym
00a97672 19460#define elf_backend_want_plt_sym 1
906e58ca 19461#undef ELF_MAXPAGESIZE
00a97672 19462#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 19463
19464#include "elf32-target.h"
19465
19466
21d799b5
NC		 19467/* Merge backend specific data from an object file to the output
19468 object file when linking. */
19469
19470static bfd_boolean
50e03d47 19471elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
21d799b5 19472{
50e03d47 19473 bfd *obfd = info->output_bfd;
21d799b5
NC		 19474 flagword out_flags;
19475 flagword in_flags;
19476 bfd_boolean flags_compatible = TRUE;
19477 asection *sec;
19478
cc643b88 19479 /* Check if we have the same endianness. */
50e03d47 19480 if (! _bfd_generic_verify_endian_match (ibfd, info))
21d799b5
NC		 19481 return FALSE;
19482
19483 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
19484 return TRUE;
19485
50e03d47 19486 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
21d799b5
NC		 19487 return FALSE;
19488
19489 /* The input BFD must have had its flags initialised. */
19490 /* The following seems bogus to me -- The flags are initialized in
19491 the assembler but I don't think an elf_flags_init field is
19492 written into the object. */
19493 /* BFD_ASSERT (elf_flags_init (ibfd)); */
19494
19495 in_flags = elf_elfheader (ibfd)->e_flags;
19496 out_flags = elf_elfheader (obfd)->e_flags;
19497
19498 /* In theory there is no reason why we couldn't handle this. However
19499 in practice it isn't even close to working and there is no real
19500 reason to want it. */
19501 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
19502 && !(ibfd->flags & DYNAMIC)
19503 && (in_flags & EF_ARM_BE8))
19504 {
871b3ab2 19505 _bfd_error_handler (_("error: %pB is already in final BE8 format"),
21d799b5
NC		 19506 ibfd);
19507 return FALSE;
19508 }
19509
19510 if (!elf_flags_init (obfd))
19511 {
19512 /* If the input is the default architecture and had the default
19513 flags then do not bother setting the flags for the output
19514 architecture, instead allow future merges to do this. If no
19515 future merges ever set these flags then they will retain their
99059e56
RM		 19516 uninitialised values, which surprise surprise, correspond
19517 to the default values. */
21d799b5
NC		 19518 if (bfd_get_arch_info (ibfd)->the_default
19519 && elf_elfheader (ibfd)->e_flags == 0)
19520 return TRUE;
19521
19522 elf_flags_init (obfd) = TRUE;
19523 elf_elfheader (obfd)->e_flags = in_flags;
19524
19525 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
19526 && bfd_get_arch_info (obfd)->the_default)
19527 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
19528
19529 return TRUE;
19530 }
19531
19532 /* Determine what should happen if the input ARM architecture
19533 does not match the output ARM architecture. */
19534 if (! bfd_arm_merge_machines (ibfd, obfd))
19535 return FALSE;
19536
19537 /* Identical flags must be compatible. */
19538 if (in_flags == out_flags)
19539 return TRUE;
19540
19541 /* Check to see if the input BFD actually contains any sections. If
19542 not, its flags may not have been initialised either, but it
19543 cannot actually cause any incompatiblity. Do not short-circuit
19544 dynamic objects; their section list may be emptied by
19545 elf_link_add_object_symbols.
19546
19547 Also check to see if there are no code sections in the input.
19548 In this case there is no need to check for code specific flags.
19549 XXX - do we need to worry about floating-point format compatability
19550 in data sections ? */
19551 if (!(ibfd->flags & DYNAMIC))
19552 {
19553 bfd_boolean null_input_bfd = TRUE;
19554 bfd_boolean only_data_sections = TRUE;
19555
19556 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
19557 {
19558 /* Ignore synthetic glue sections. */
19559 if (strcmp (sec->name, ".glue_7")
19560 && strcmp (sec->name, ".glue_7t"))
19561 {
19562 if ((bfd_get_section_flags (ibfd, sec)
19563 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
19564 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 19565 only_data_sections = FALSE;
21d799b5
NC		 19566
19567 null_input_bfd = FALSE;
19568 break;
19569 }
19570 }
19571
19572 if (null_input_bfd || only_data_sections)
19573 return TRUE;
19574 }
19575
19576 /* Complain about various flag mismatches. */
19577 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
19578 EF_ARM_EABI_VERSION (out_flags)))
19579 {
19580 _bfd_error_handler
90b6238f 19581 (_("error: source object %pB has EABI version %d, but target %pB has EABI version %d"),
c08bb8dd
AM		 19582 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
19583 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
21d799b5
NC		 19584 return FALSE;
19585 }
19586
19587 /* Not sure what needs to be checked for EABI versions >= 1. */
19588 /* VxWorks libraries do not use these flags. */
19589 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
19590 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
19591 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
19592 {
19593 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
19594 {
19595 _bfd_error_handler
871b3ab2 19596 (_("error: %pB is compiled for APCS-%d, whereas target %pB uses APCS-%d"),
c08bb8dd
AM		 19597 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
19598 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
21d799b5
NC		 19599 flags_compatible = FALSE;
19600 }
19601
19602 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
19603 {
19604 if (in_flags & EF_ARM_APCS_FLOAT)
19605 _bfd_error_handler
871b3ab2 19606 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
21d799b5
NC		 19607 ibfd, obfd);
19608 else
19609 _bfd_error_handler
871b3ab2 19610 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
21d799b5
NC		 19611 ibfd, obfd);
19612
19613 flags_compatible = FALSE;
19614 }
19615
19616 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
19617 {
19618 if (in_flags & EF_ARM_VFP_FLOAT)
19619 _bfd_error_handler
90b6238f
AM		 19620 (_("error: %pB uses %s instructions, whereas %pB does not"),
19621 ibfd, "VFP", obfd);
21d799b5
NC		 19622 else
19623 _bfd_error_handler
90b6238f
AM		 19624 (_("error: %pB uses %s instructions, whereas %pB does not"),
19625 ibfd, "FPA", obfd);
21d799b5
NC		 19626
19627 flags_compatible = FALSE;
19628 }
19629
19630 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
19631 {
19632 if (in_flags & EF_ARM_MAVERICK_FLOAT)
19633 _bfd_error_handler
90b6238f
AM		 19634 (_("error: %pB uses %s instructions, whereas %pB does not"),
19635 ibfd, "Maverick", obfd);
21d799b5
NC		 19636 else
19637 _bfd_error_handler
90b6238f
AM		 19638 (_("error: %pB does not use %s instructions, whereas %pB does"),
19639 ibfd, "Maverick", obfd);
21d799b5
NC		 19640
19641 flags_compatible = FALSE;
19642 }
19643
19644#ifdef EF_ARM_SOFT_FLOAT
19645 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
19646 {
19647 /* We can allow interworking between code that is VFP format
19648 layout, and uses either soft float or integer regs for
19649 passing floating point arguments and results. We already
19650 know that the APCS_FLOAT flags match; similarly for VFP
19651 flags. */
19652 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
19653 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
19654 {
19655 if (in_flags & EF_ARM_SOFT_FLOAT)
19656 _bfd_error_handler
871b3ab2 19657 (_("error: %pB uses software FP, whereas %pB uses hardware FP"),
21d799b5
NC		 19658 ibfd, obfd);
19659 else
19660 _bfd_error_handler
871b3ab2 19661 (_("error: %pB uses hardware FP, whereas %pB uses software FP"),
21d799b5
NC		 19662 ibfd, obfd);
19663
19664 flags_compatible = FALSE;
19665 }
19666 }
19667#endif
19668
19669 /* Interworking mismatch is only a warning. */
19670 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
19671 {
19672 if (in_flags & EF_ARM_INTERWORK)
19673 {
19674 _bfd_error_handler
90b6238f 19675 (_("warning: %pB supports interworking, whereas %pB does not"),
21d799b5
NC		 19676 ibfd, obfd);
19677 }
19678 else
19679 {
19680 _bfd_error_handler
90b6238f 19681 (_("warning: %pB does not support interworking, whereas %pB does"),
21d799b5
NC		 19682 ibfd, obfd);
19683 }
19684 }
19685 }
19686
19687 return flags_compatible;
19688}
19689
19690
906e58ca 19691/* Symbian OS Targets. */
7f266840 19692
07d6d2b8
AM		 19693#undef TARGET_LITTLE_SYM
19694#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
19695#undef TARGET_LITTLE_NAME
19696#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
19697#undef TARGET_BIG_SYM
19698#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
19699#undef TARGET_BIG_NAME
19700#define TARGET_BIG_NAME "elf32-bigarm-symbian"
7f266840
DJ		 19701
19702/* Like elf32_arm_link_hash_table_create -- but overrides
19703 appropriately for Symbian OS. */
906e58ca 19704
7f266840
DJ		 19705static struct bfd_link_hash_table *
19706elf32_arm_symbian_link_hash_table_create (bfd *abfd)
19707{
19708 struct bfd_link_hash_table *ret;
19709
19710 ret = elf32_arm_link_hash_table_create (abfd);
19711 if (ret)
19712 {
19713 struct elf32_arm_link_hash_table *htab
19714 = (struct elf32_arm_link_hash_table *)ret;
19715 /* There is no PLT header for Symbian OS. */
19716 htab->plt_header_size = 0;
95720a86
DJ		 19717 /* The PLT entries are each one instruction and one word. */
19718 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 19719 htab->symbian_p = 1;
33bfe774
JB		 19720 /* Symbian uses armv5t or above, so use_blx is always true. */
19721 htab->use_blx = 1;
67687978 19722 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 19723 }
19724 return ret;
906e58ca 19725}
7f266840 19726
b35d266b 19727static const struct bfd_elf_special_section
551b43fd 19728elf32_arm_symbian_special_sections[] =
7f266840 19729{
5cd3778d
MM		 19730 /* In a BPABI executable, the dynamic linking sections do not go in
19731 the loadable read-only segment. The post-linker may wish to
19732 refer to these sections, but they are not part of the final
19733 program image. */
07d6d2b8
AM		 19734 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
19735 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
19736 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
19737 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
19738 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 19739 /* These sections do not need to be writable as the SymbianOS
19740 postlinker will arrange things so that no dynamic relocation is
19741 required. */
07d6d2b8
AM		 19742 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
19743 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
0112cd26 19744 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
07d6d2b8 19745 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 19746};
19747
c3c76620 19748static void
906e58ca 19749elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 19750 struct bfd_link_info *link_info)
c3c76620
MM		 19751{
19752 /* BPABI objects are never loaded directly by an OS kernel; they are
19753 processed by a postlinker first, into an OS-specific format. If
19754 the D_PAGED bit is set on the file, BFD will align segments on
19755 page boundaries, so that an OS can directly map the file. With
19756 BPABI objects, that just results in wasted space. In addition,
19757 because we clear the D_PAGED bit, map_sections_to_segments will
19758 recognize that the program headers should not be mapped into any
19759 loadable segment. */
19760 abfd->flags &= ~D_PAGED;
906e58ca 19761 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 19762}
7f266840
DJ		 19763
19764static bfd_boolean
906e58ca 19765elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 19766 struct bfd_link_info *info)
7f266840
DJ		 19767{
19768 struct elf_segment_map *m;
19769 asection *dynsec;
19770
7f266840
DJ		 19771 /* BPABI shared libraries and executables should have a PT_DYNAMIC
19772 segment. However, because the .dynamic section is not marked
19773 with SEC_LOAD, the generic ELF code will not create such a
19774 segment. */
19775 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
19776 if (dynsec)
19777 {
12bd6957 19778 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 19779 if (m->p_type == PT_DYNAMIC)
19780 break;
19781
19782 if (m == NULL)
19783 {
19784 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 19785 m->next = elf_seg_map (abfd);
19786 elf_seg_map (abfd) = m;
8ded5a0f 19787 }
7f266840
DJ		 19788 }
19789
b294bdf8
MM		 19790 /* Also call the generic arm routine. */
19791 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 19792}
19793
95720a86
DJ		 19794/* Return address for Ith PLT stub in section PLT, for relocation REL
19795 or (bfd_vma) -1 if it should not be included. */
19796
19797static bfd_vma
19798elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
19799 const arelent *rel ATTRIBUTE_UNUSED)
19800{
19801 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
19802}
19803
8029a119 19804#undef elf32_bed
7f266840
DJ		 19805#define elf32_bed elf32_arm_symbian_bed
19806
19807/* The dynamic sections are not allocated on SymbianOS; the postlinker
19808 will process them and then discard them. */
906e58ca 19809#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 19810#define ELF_DYNAMIC_SEC_FLAGS \
19811 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
19812
9eaff861 19813#undef elf_backend_emit_relocs
c3c76620 19814
906e58ca
NC		 19815#undef bfd_elf32_bfd_link_hash_table_create
19816#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
19817#undef elf_backend_special_sections
07d6d2b8 19818#define elf_backend_special_sections elf32_arm_symbian_special_sections
906e58ca
NC		 19819#undef elf_backend_begin_write_processing
19820#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
19821#undef elf_backend_final_write_processing
19822#define elf_backend_final_write_processing elf32_arm_final_write_processing
19823
19824#undef elf_backend_modify_segment_map
7f266840
DJ		 19825#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
19826
19827/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 19828#undef elf_backend_got_header_size
7f266840
DJ		 19829#define elf_backend_got_header_size 0
19830
19831/* Similarly, there is no .got.plt section. */
906e58ca 19832#undef elf_backend_want_got_plt
7f266840
DJ		 19833#define elf_backend_want_got_plt 0
19834
906e58ca 19835#undef elf_backend_plt_sym_val
95720a86
DJ		 19836#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
19837
906e58ca 19838#undef elf_backend_may_use_rel_p
00a97672 19839#define elf_backend_may_use_rel_p 1
906e58ca 19840#undef elf_backend_may_use_rela_p
00a97672 19841#define elf_backend_may_use_rela_p 0
906e58ca 19842#undef elf_backend_default_use_rela_p
00a97672 19843#define elf_backend_default_use_rela_p 0
906e58ca 19844#undef elf_backend_want_plt_sym
00a97672 19845#define elf_backend_want_plt_sym 0
64f52338
AM		 19846#undef elf_backend_dtrel_excludes_plt
19847#define elf_backend_dtrel_excludes_plt 0
906e58ca 19848#undef ELF_MAXPAGESIZE
00a97672 19849#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 19850
7f266840 19851#include "elf32-target.h"
GDB Binutils - Deliverables
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