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Factor our stub creation in ARM backend
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
6f2750fe 2 Copyright (C) 1998-2016 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
7f266840
DJ		 59#define elf_info_to_howto 0
60#define elf_info_to_howto_rel elf32_arm_info_to_howto
61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
240 HOWTO (R_ARM_THM_PC8, /* type */
241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
99059e56
RM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
99059e56
RM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
99059e56
RM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
99059e56
RM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
99059e56
RM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
99059e56
RM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
99059e56
RM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
99059e56
RM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
99059e56
RM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
446 TRUE, /* pc_relative */
447 0, /* bitpos */
448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
99059e56
RM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
460 FALSE, /* pc_relative */
461 0, /* bitpos */
462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
99059e56
RM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
474 TRUE, /* pc_relative */
475 0, /* bitpos */
476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
909 HOWTO (R_ARM_ALU_PC_G0, /* type */
910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
917 "R_ARM_ALU_PC_G0", /* name */
918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
937 HOWTO (R_ARM_ALU_PC_G1, /* type */
938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
945 "R_ARM_ALU_PC_G1", /* name */
946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
951 HOWTO (R_ARM_ALU_PC_G2, /* type */
952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
959 "R_ARM_ALU_PC_G2", /* name */
960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
965 HOWTO (R_ARM_LDR_PC_G1, /* type */
966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
973 "R_ARM_LDR_PC_G1", /* name */
974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
979 HOWTO (R_ARM_LDR_PC_G2, /* type */
980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
987 "R_ARM_LDR_PC_G2", /* name */
988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
1001 "R_ARM_LDRS_PC_G0", /* name */
1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
1015 "R_ARM_LDRS_PC_G1", /* name */
1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
1029 "R_ARM_LDRS_PC_G2", /* name */
1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
1043 "R_ARM_LDC_PC_G0", /* name */
1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
1057 "R_ARM_LDC_PC_G1", /* name */
1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
1071 "R_ARM_LDC_PC_G2", /* name */
1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
1085 "R_ARM_ALU_SB_G0_NC", /* name */
1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
1099 "R_ARM_ALU_SB_G0", /* name */
1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
1113 "R_ARM_ALU_SB_G1_NC", /* name */
1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
1127 "R_ARM_ALU_SB_G1", /* name */
1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
1141 "R_ARM_ALU_SB_G2", /* name */
1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
1155 "R_ARM_LDR_SB_G0", /* name */
1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
1169 "R_ARM_LDR_SB_G1", /* name */
1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
1183 "R_ARM_LDR_SB_G2", /* name */
1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
1197 "R_ARM_LDRS_SB_G0", /* name */
1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
1211 "R_ARM_LDRS_SB_G1", /* name */
1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
1225 "R_ARM_LDRS_SB_G2", /* name */
1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
1239 "R_ARM_LDC_SB_G0", /* name */
1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
1253 "R_ARM_LDC_SB_G1", /* name */
1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
1267 "R_ARM_LDC_SB_G2", /* name */
1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
1486
1487 /* GNU extension to record C++ vtable member usage */
1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
99059e56
RM		 1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
1494 complain_overflow_dont, /* complain_on_overflow */
1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
99059e56
RM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
1509 complain_overflow_dont, /* complain_on_overflow */
1510 NULL, /* special_function */
1511 "R_ARM_GNU_VTINHERIT", /* name */
1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
99059e56
RM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
99059e56
RM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
99059e56
RM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
99059e56
RM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
99059e56
RM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
1608 complain_overflow_bitfield,/* complain_on_overflow */
75c11999 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92
RS		 1748/* 160 onwards: */
1749static reloc_howto_type elf32_arm_howto_table_2[1] =
1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
99059e56
RM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
1763 FALSE) /* pcrel_offset */
34e77a92 1764};
c19d1205 1765
34e77a92
RS		 1766/* 249-255 extended, currently unused, relocations: */
1767static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1768{
1769 HOWTO (R_ARM_RREL32, /* type */
1770 0, /* rightshift */
1771 0, /* size (0 = byte, 1 = short, 2 = long) */
1772 0, /* bitsize */
1773 FALSE, /* pc_relative */
1774 0, /* bitpos */
1775 complain_overflow_dont,/* complain_on_overflow */
1776 bfd_elf_generic_reloc, /* special_function */
1777 "R_ARM_RREL32", /* name */
1778 FALSE, /* partial_inplace */
1779 0, /* src_mask */
1780 0, /* dst_mask */
1781 FALSE), /* pcrel_offset */
1782
1783 HOWTO (R_ARM_RABS32, /* type */
1784 0, /* rightshift */
1785 0, /* size (0 = byte, 1 = short, 2 = long) */
1786 0, /* bitsize */
1787 FALSE, /* pc_relative */
1788 0, /* bitpos */
1789 complain_overflow_dont,/* complain_on_overflow */
1790 bfd_elf_generic_reloc, /* special_function */
1791 "R_ARM_RABS32", /* name */
1792 FALSE, /* partial_inplace */
1793 0, /* src_mask */
1794 0, /* dst_mask */
1795 FALSE), /* pcrel_offset */
1796
1797 HOWTO (R_ARM_RPC24, /* type */
1798 0, /* rightshift */
1799 0, /* size (0 = byte, 1 = short, 2 = long) */
1800 0, /* bitsize */
1801 FALSE, /* pc_relative */
1802 0, /* bitpos */
1803 complain_overflow_dont,/* complain_on_overflow */
1804 bfd_elf_generic_reloc, /* special_function */
1805 "R_ARM_RPC24", /* name */
1806 FALSE, /* partial_inplace */
1807 0, /* src_mask */
1808 0, /* dst_mask */
1809 FALSE), /* pcrel_offset */
1810
1811 HOWTO (R_ARM_RBASE, /* type */
1812 0, /* rightshift */
1813 0, /* size (0 = byte, 1 = short, 2 = long) */
1814 0, /* bitsize */
1815 FALSE, /* pc_relative */
1816 0, /* bitpos */
1817 complain_overflow_dont,/* complain_on_overflow */
1818 bfd_elf_generic_reloc, /* special_function */
1819 "R_ARM_RBASE", /* name */
1820 FALSE, /* partial_inplace */
1821 0, /* src_mask */
1822 0, /* dst_mask */
1823 FALSE) /* pcrel_offset */
1824};
1825
1826static reloc_howto_type *
1827elf32_arm_howto_from_type (unsigned int r_type)
1828{
906e58ca 1829 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1830 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1831
34e77a92
RS		 1832 if (r_type == R_ARM_IRELATIVE)
1833 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1834
c19d1205 1835 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1836 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1837 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1838
c19d1205 1839 return NULL;
7f266840
DJ		 1840}
1841
1842static void
1843elf32_arm_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, arelent * bfd_reloc,
1844 Elf_Internal_Rela * elf_reloc)
1845{
1846 unsigned int r_type;
1847
1848 r_type = ELF32_R_TYPE (elf_reloc->r_info);
1849 bfd_reloc->howto = elf32_arm_howto_from_type (r_type);
1850}
1851
1852struct elf32_arm_reloc_map
1853 {
1854 bfd_reloc_code_real_type bfd_reloc_val;
1855 unsigned char elf_reloc_val;
1856 };
1857
1858/* All entries in this list must also be present in elf32_arm_howto_table. */
1859static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1860 {
1861 {BFD_RELOC_NONE, R_ARM_NONE},
1862 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1863 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1864 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
7f266840
DJ		 1865 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1866 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1867 {BFD_RELOC_32, R_ARM_ABS32},
1868 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1869 {BFD_RELOC_8, R_ARM_ABS8},
1870 {BFD_RELOC_16, R_ARM_ABS16},
1871 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
1872 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1873 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1874 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1875 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1876 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1877 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1878 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
7f266840
DJ		 1879 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1880 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1881 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
c19d1205 1882 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
7f266840 1883 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
b43420e6 1884 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
7f266840
DJ		 1885 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1886 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1887 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1888 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1889 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1890 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac
DJ		 1891 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
1892 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
0855e32b
NS		 1893 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1894 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
1895 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
1896 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
1897 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
1898 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1899 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1900 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1901 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1902 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1903 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
1904 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1905 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1906 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
34e77a92 1907 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
c19d1205
ZW		 1908 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1909 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1910 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1911 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1912 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1913 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1914 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1915 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1916 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1917 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1918 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1919 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1920 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1921 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1922 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1923 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1924 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1925 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1926 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1927 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1928 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1929 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1930 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1931 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1932 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1933 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1934 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
1935 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
1936 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
1937 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
1938 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
1939 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
1940 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
1941 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
1942 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
1943 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
1944 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 1945 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 1946 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
1947 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
1948 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
1949 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
1950 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 1951 };
1952
1953static reloc_howto_type *
f1c71a59
ZW		 1954elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1955 bfd_reloc_code_real_type code)
7f266840
DJ		 1956{
1957 unsigned int i;
8029a119 1958
906e58ca 1959 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 1960 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
1961 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 1962
c19d1205 1963 return NULL;
7f266840
DJ		 1964}
1965
157090f7
AM		 1966static reloc_howto_type *
1967elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1968 const char *r_name)
1969{
1970 unsigned int i;
1971
906e58ca 1972 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 1973 if (elf32_arm_howto_table_1[i].name != NULL
1974 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
1975 return &elf32_arm_howto_table_1[i];
1976
906e58ca 1977 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 1978 if (elf32_arm_howto_table_2[i].name != NULL
1979 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
1980 return &elf32_arm_howto_table_2[i];
1981
34e77a92
RS		 1982 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
1983 if (elf32_arm_howto_table_3[i].name != NULL
1984 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
1985 return &elf32_arm_howto_table_3[i];
1986
157090f7
AM		 1987 return NULL;
1988}
1989
906e58ca
NC		 1990/* Support for core dump NOTE sections. */
1991
7f266840 1992static bfd_boolean
f1c71a59 1993elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 1994{
1995 int offset;
1996 size_t size;
1997
1998 switch (note->descsz)
1999 {
2000 default:
2001 return FALSE;
2002
8029a119 2003 case 148: /* Linux/ARM 32-bit. */
7f266840 2004 /* pr_cursig */
228e534f 2005 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2006
2007 /* pr_pid */
228e534f 2008 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2009
2010 /* pr_reg */
2011 offset = 72;
2012 size = 72;
2013
2014 break;
2015 }
2016
2017 /* Make a ".reg/999" section. */
2018 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2019 size, note->descpos + offset);
2020}
2021
2022static bfd_boolean
f1c71a59 2023elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2024{
2025 switch (note->descsz)
2026 {
2027 default:
2028 return FALSE;
2029
8029a119 2030 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2031 elf_tdata (abfd)->core->pid
4395ee08 2032 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2033 elf_tdata (abfd)->core->program
7f266840 2034 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2035 elf_tdata (abfd)->core->command
7f266840
DJ		 2036 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2037 }
2038
2039 /* Note that for some reason, a spurious space is tacked
2040 onto the end of the args in some (at least one anyway)
2041 implementations, so strip it off if it exists. */
7f266840 2042 {
228e534f 2043 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2044 int n = strlen (command);
2045
2046 if (0 < n && command[n - 1] == ' ')
2047 command[n - 1] = '\0';
2048 }
2049
2050 return TRUE;
2051}
2052
1f20dca5
UW		 2053static char *
2054elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2055 int note_type, ...)
2056{
2057 switch (note_type)
2058 {
2059 default:
2060 return NULL;
2061
2062 case NT_PRPSINFO:
2063 {
2064 char data[124];
2065 va_list ap;
2066
2067 va_start (ap, note_type);
2068 memset (data, 0, sizeof (data));
2069 strncpy (data + 28, va_arg (ap, const char *), 16);
2070 strncpy (data + 44, va_arg (ap, const char *), 80);
2071 va_end (ap);
2072
2073 return elfcore_write_note (abfd, buf, bufsiz,
2074 "CORE", note_type, data, sizeof (data));
2075 }
2076
2077 case NT_PRSTATUS:
2078 {
2079 char data[148];
2080 va_list ap;
2081 long pid;
2082 int cursig;
2083 const void *greg;
2084
2085 va_start (ap, note_type);
2086 memset (data, 0, sizeof (data));
2087 pid = va_arg (ap, long);
2088 bfd_put_32 (abfd, pid, data + 24);
2089 cursig = va_arg (ap, int);
2090 bfd_put_16 (abfd, cursig, data + 12);
2091 greg = va_arg (ap, const void *);
2092 memcpy (data + 72, greg, 72);
2093 va_end (ap);
2094
2095 return elfcore_write_note (abfd, buf, bufsiz,
2096 "CORE", note_type, data, sizeof (data));
2097 }
2098 }
2099}
2100
6d00b590 2101#define TARGET_LITTLE_SYM arm_elf32_le_vec
7f266840 2102#define TARGET_LITTLE_NAME "elf32-littlearm"
6d00b590 2103#define TARGET_BIG_SYM arm_elf32_be_vec
7f266840
DJ		 2104#define TARGET_BIG_NAME "elf32-bigarm"
2105
2106#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2107#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2108#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2109
252b5132
RH		 2110typedef unsigned long int insn32;
2111typedef unsigned short int insn16;
2112
3a4a14e9
PB		 2113/* In lieu of proper flags, assume all EABIv4 or later objects are
2114 interworkable. */
57e8b36a 2115#define INTERWORK_FLAG(abfd) \
3a4a14e9 2116 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2117 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2118 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2119
252b5132
RH		 2120/* The linker script knows the section names for placement.
2121 The entry_names are used to do simple name mangling on the stubs.
2122 Given a function name, and its type, the stub can be found. The
9b485d32 2123 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2124#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2125#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2126
2127#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2128#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2129
c7b8f16e
JB		 2130#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2131#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2132
a504d23a
LA		 2133#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2134#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2135
845b51d6
PB		 2136#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2137#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2138
7413f23f
DJ		 2139#define STUB_ENTRY_NAME "__%s_veneer"
2140
252b5132
RH		 2141/* The name of the dynamic interpreter. This is put in the .interp
2142 section. */
2143#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2144
0855e32b 2145static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2146{
2147 0xe08e0000, /* add r0, lr, r0 */
2148 0xe5901004, /* ldr r1, [r0,#4] */
2149 0xe12fff11, /* bx r1 */
2150};
0855e32b
NS		 2151
2152static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2153{
2154 0xe52d2004, /* push {r2} */
2155 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2156 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2157 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2158 0xe081100f, /* 2: add r1, pc */
2159 0xe12fff12, /* bx r2 */
2160 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2161 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2162 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2163};
0855e32b 2164
5e681ec4
PB		 2165#ifdef FOUR_WORD_PLT
2166
252b5132
RH		 2167/* The first entry in a procedure linkage table looks like
2168 this. It is set up so that any shared library function that is
59f2c4e7 2169 called before the relocation has been set up calls the dynamic
9b485d32 2170 linker first. */
e5a52504 2171static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2172{
2173 0xe52de004, /* str lr, [sp, #-4]! */
2174 0xe59fe010, /* ldr lr, [pc, #16] */
2175 0xe08fe00e, /* add lr, pc, lr */
2176 0xe5bef008, /* ldr pc, [lr, #8]! */
2177};
5e681ec4
PB		 2178
2179/* Subsequent entries in a procedure linkage table look like
2180 this. */
e5a52504 2181static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2182{
2183 0xe28fc600, /* add ip, pc, #NN */
2184 0xe28cca00, /* add ip, ip, #NN */
2185 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2186 0x00000000, /* unused */
2187};
5e681ec4 2188
eed94f8f 2189#else /* not FOUR_WORD_PLT */
5e681ec4 2190
5e681ec4
PB		 2191/* The first entry in a procedure linkage table looks like
2192 this. It is set up so that any shared library function that is
2193 called before the relocation has been set up calls the dynamic
2194 linker first. */
e5a52504 2195static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2196{
2197 0xe52de004, /* str lr, [sp, #-4]! */
2198 0xe59fe004, /* ldr lr, [pc, #4] */
2199 0xe08fe00e, /* add lr, pc, lr */
2200 0xe5bef008, /* ldr pc, [lr, #8]! */
2201 0x00000000, /* &GOT[0] - . */
2202};
252b5132 2203
1db37fe6
YG		 2204/* By default subsequent entries in a procedure linkage table look like
2205 this. Offsets that don't fit into 28 bits will cause link error. */
2206static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2207{
2208 0xe28fc600, /* add ip, pc, #0xNN00000 */
2209 0xe28cca00, /* add ip, ip, #0xNN000 */
2210 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2211};
5e681ec4 2212
1db37fe6
YG		 2213/* When explicitly asked, we'll use this "long" entry format
2214 which can cope with arbitrary displacements. */
2215static const bfd_vma elf32_arm_plt_entry_long [] =
2216{
2217 0xe28fc200, /* add ip, pc, #0xN0000000 */
2218 0xe28cc600, /* add ip, ip, #0xNN00000 */
2219 0xe28cca00, /* add ip, ip, #0xNN000 */
2220 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2221};
2222
2223static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2224
eed94f8f
NC		 2225#endif /* not FOUR_WORD_PLT */
2226
2227/* The first entry in a procedure linkage table looks like this.
2228 It is set up so that any shared library function that is called before the
2229 relocation has been set up calls the dynamic linker first. */
2230static const bfd_vma elf32_thumb2_plt0_entry [] =
2231{
2232 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2233 an instruction maybe encoded to one or two array elements. */
2234 0xf8dfb500, /* push {lr} */
2235 0x44fee008, /* ldr.w lr, [pc, #8] */
469a3493 2236 /* add lr, pc */
eed94f8f
NC		 2237 0xff08f85e, /* ldr.w pc, [lr, #8]! */
2238 0x00000000, /* &GOT[0] - . */
2239};
2240
2241/* Subsequent entries in a procedure linkage table for thumb only target
2242 look like this. */
2243static const bfd_vma elf32_thumb2_plt_entry [] =
2244{
2245 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2246 an instruction maybe encoded to one or two array elements. */
2247 0x0c00f240, /* movw ip, #0xNNNN */
2248 0x0c00f2c0, /* movt ip, #0xNNNN */
2249 0xf8dc44fc, /* add ip, pc */
2250 0xbf00f000 /* ldr.w pc, [ip] */
469a3493 2251 /* nop */
eed94f8f 2252};
252b5132 2253
00a97672
RS		 2254/* The format of the first entry in the procedure linkage table
2255 for a VxWorks executable. */
2256static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb
NC		 2257{
2258 0xe52dc008, /* str ip,[sp,#-8]! */
2259 0xe59fc000, /* ldr ip,[pc] */
2260 0xe59cf008, /* ldr pc,[ip,#8] */
2261 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
2262};
00a97672
RS		 2263
2264/* The format of subsequent entries in a VxWorks executable. */
2265static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb
NC		 2266{
2267 0xe59fc000, /* ldr ip,[pc] */
2268 0xe59cf000, /* ldr pc,[ip] */
2269 0x00000000, /* .long @got */
2270 0xe59fc000, /* ldr ip,[pc] */
2271 0xea000000, /* b _PLT */
2272 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2273};
00a97672
RS		 2274
2275/* The format of entries in a VxWorks shared library. */
2276static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb
NC		 2277{
2278 0xe59fc000, /* ldr ip,[pc] */
2279 0xe79cf009, /* ldr pc,[ip,r9] */
2280 0x00000000, /* .long @got */
2281 0xe59fc000, /* ldr ip,[pc] */
2282 0xe599f008, /* ldr pc,[r9,#8] */
2283 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2284};
00a97672 2285
b7693d02
DJ		 2286/* An initial stub used if the PLT entry is referenced from Thumb code. */
2287#define PLT_THUMB_STUB_SIZE 4
2288static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2289{
2290 0x4778, /* bx pc */
2291 0x46c0 /* nop */
2292};
b7693d02 2293
e5a52504
MM		 2294/* The entries in a PLT when using a DLL-based target with multiple
2295 address spaces. */
906e58ca 2296static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb
NC		 2297{
2298 0xe51ff004, /* ldr pc, [pc, #-4] */
2299 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
2300};
2301
2302/* The first entry in a procedure linkage table looks like
2303 this. It is set up so that any shared library function that is
2304 called before the relocation has been set up calls the dynamic
2305 linker first. */
2306static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2307{
2308 /* First bundle: */
2309 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2310 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2311 0xe08cc00f, /* add ip, ip, pc */
2312 0xe52dc008, /* str ip, [sp, #-8]! */
2313 /* Second bundle: */
edccdf7c
RM		 2314 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2315 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2316 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2317 0xe12fff1c, /* bx ip */
b38cadfb 2318 /* Third bundle: */
edccdf7c
RM		 2319 0xe320f000, /* nop */
2320 0xe320f000, /* nop */
2321 0xe320f000, /* nop */
b38cadfb
NC		 2322 /* .Lplt_tail: */
2323 0xe50dc004, /* str ip, [sp, #-4] */
2324 /* Fourth bundle: */
edccdf7c
RM		 2325 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2326 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2327 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2328 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2329};
2330#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2331
2332/* Subsequent entries in a procedure linkage table look like this. */
2333static const bfd_vma elf32_arm_nacl_plt_entry [] =
2334{
2335 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2336 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2337 0xe08cc00f, /* add ip, ip, pc */
2338 0xea000000, /* b .Lplt_tail */
2339};
e5a52504 2340
906e58ca
NC		 2341#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2342#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2343#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2344#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2345#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2346#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2347#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2348#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2349
461a49ca 2350enum stub_insn_type
b38cadfb
NC		 2351{
2352 THUMB16_TYPE = 1,
2353 THUMB32_TYPE,
2354 ARM_TYPE,
2355 DATA_TYPE
2356};
461a49ca 2357
48229727
JB		 2358#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2359/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2360 is inserted in arm_build_one_stub(). */
2361#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2362#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2363#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2364#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2365#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2366#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2367
2368typedef struct
2369{
b38cadfb
NC		 2370 bfd_vma data;
2371 enum stub_insn_type type;
2372 unsigned int r_type;
2373 int reloc_addend;
461a49ca
DJ		 2374} insn_sequence;
2375
fea2b4d6
CL		 2376/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2377 to reach the stub if necessary. */
461a49ca 2378static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb
NC		 2379{
2380 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2381 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2382};
906e58ca 2383
fea2b4d6
CL		 2384/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2385 available. */
461a49ca 2386static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb
NC		 2387{
2388 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2389 ARM_INSN (0xe12fff1c), /* bx ip */
2390 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2391};
906e58ca 2392
d3626fb0 2393/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2394static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb
NC		 2395{
2396 THUMB16_INSN (0xb401), /* push {r0} */
2397 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2398 THUMB16_INSN (0x4684), /* mov ip, r0 */
2399 THUMB16_INSN (0xbc01), /* pop {r0} */
2400 THUMB16_INSN (0x4760), /* bx ip */
2401 THUMB16_INSN (0xbf00), /* nop */
2402 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2403};
906e58ca 2404
d3626fb0
CL		 2405/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2406 allowed. */
2407static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb
NC		 2408{
2409 THUMB16_INSN (0x4778), /* bx pc */
2410 THUMB16_INSN (0x46c0), /* nop */
2411 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2412 ARM_INSN (0xe12fff1c), /* bx ip */
2413 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2414};
d3626fb0 2415
fea2b4d6
CL		 2416/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2417 available. */
461a49ca 2418static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2419{
2420 THUMB16_INSN (0x4778), /* bx pc */
2421 THUMB16_INSN (0x46c0), /* nop */
2422 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2423 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2424};
906e58ca 2425
fea2b4d6
CL		 2426/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2427 one, when the destination is close enough. */
461a49ca 2428static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2429{
2430 THUMB16_INSN (0x4778), /* bx pc */
2431 THUMB16_INSN (0x46c0), /* nop */
2432 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2433};
c820be07 2434
cf3eccff 2435/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2436 blx to reach the stub if necessary. */
cf3eccff 2437static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb
NC		 2438{
2439 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2440 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
2441 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2442};
906e58ca 2443
cf3eccff
DJ		 2444/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2445 blx to reach the stub if necessary. We can not add into pc;
2446 it is not guaranteed to mode switch (different in ARMv6 and
2447 ARMv7). */
2448static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb
NC		 2449{
2450 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2451 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2452 ARM_INSN (0xe12fff1c), /* bx ip */
2453 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2454};
cf3eccff 2455
ebe24dd4
CL		 2456/* V4T ARM -> ARM long branch stub, PIC. */
2457static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb
NC		 2458{
2459 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2460 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2461 ARM_INSN (0xe12fff1c), /* bx ip */
2462 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2463};
ebe24dd4
CL		 2464
2465/* V4T Thumb -> ARM long branch stub, PIC. */
2466static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb
NC		 2467{
2468 THUMB16_INSN (0x4778), /* bx pc */
2469 THUMB16_INSN (0x46c0), /* nop */
2470 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2471 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
2472 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2473};
ebe24dd4 2474
d3626fb0
CL		 2475/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2476 architectures. */
ebe24dd4 2477static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb
NC		 2478{
2479 THUMB16_INSN (0xb401), /* push {r0} */
2480 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2481 THUMB16_INSN (0x46fc), /* mov ip, pc */
2482 THUMB16_INSN (0x4484), /* add ip, r0 */
2483 THUMB16_INSN (0xbc01), /* pop {r0} */
2484 THUMB16_INSN (0x4760), /* bx ip */
2485 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2486};
ebe24dd4 2487
d3626fb0
CL		 2488/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2489 allowed. */
2490static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb
NC		 2491{
2492 THUMB16_INSN (0x4778), /* bx pc */
2493 THUMB16_INSN (0x46c0), /* nop */
2494 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2495 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2496 ARM_INSN (0xe12fff1c), /* bx ip */
2497 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2498};
d3626fb0 2499
0855e32b
NS		 2500/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2501 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2502static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2503{
b38cadfb
NC		 2504 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2505 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
2506 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2507};
2508
2509/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2510 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2511static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2512{
b38cadfb
NC		 2513 THUMB16_INSN (0x4778), /* bx pc */
2514 THUMB16_INSN (0x46c0), /* nop */
2515 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2516 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
2517 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2518};
2519
7a89b94e
NC		 2520/* NaCl ARM -> ARM long branch stub. */
2521static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2522{
2523 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2524 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2525 ARM_INSN (0xe12fff1c), /* bx ip */
2526 ARM_INSN (0xe320f000), /* nop */
2527 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2528 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2529 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2530 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2531};
2532
2533/* NaCl ARM -> ARM long branch stub, PIC. */
2534static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2535{
2536 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2537 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
2538 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2539 ARM_INSN (0xe12fff1c), /* bx ip */
2540 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2541 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2542 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2543 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2544};
2545
2546
48229727
JB		 2547/* Cortex-A8 erratum-workaround stubs. */
2548
2549/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2550 can't use a conditional branch to reach this stub). */
2551
2552static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb
NC		 2553{
2554 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
2555 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2556 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2557};
48229727
JB		 2558
2559/* Stub used for b.w and bl.w instructions. */
2560
2561static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2562{
2563 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2564};
48229727
JB		 2565
2566static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2567{
2568 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2569};
48229727
JB		 2570
2571/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2572 instruction (which switches to ARM mode) to point to this stub. Jump to the
2573 real destination using an ARM-mode branch. */
2574
2575static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2576{
2577 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2578};
48229727 2579
9553db3c
NC		 2580/* For each section group there can be a specially created linker section
2581 to hold the stubs for that group. The name of the stub section is based
2582 upon the name of another section within that group with the suffix below
2583 applied.
2584
2585 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2586 create what appeared to be a linker stub section when it actually
2587 contained user code/data. For example, consider this fragment:
b38cadfb 2588
9553db3c
NC		 2589 const char * stubborn_problems[] = { "np" };
2590
2591 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2592 section called:
2593
2594 .data.rel.local.stubborn_problems
2595
2596 This then causes problems in arm32_arm_build_stubs() as it triggers:
2597
2598 // Ignore non-stub sections.
2599 if (!strstr (stub_sec->name, STUB_SUFFIX))
2600 continue;
2601
2602 And so the section would be ignored instead of being processed. Hence
2603 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2604 C identifier. */
2605#define STUB_SUFFIX ".__stub"
906e58ca 2606
738a79f6
CL		 2607/* One entry per long/short branch stub defined above. */
2608#define DEF_STUBS \
2609 DEF_STUB(long_branch_any_any) \
2610 DEF_STUB(long_branch_v4t_arm_thumb) \
2611 DEF_STUB(long_branch_thumb_only) \
2612 DEF_STUB(long_branch_v4t_thumb_thumb) \
2613 DEF_STUB(long_branch_v4t_thumb_arm) \
2614 DEF_STUB(short_branch_v4t_thumb_arm) \
2615 DEF_STUB(long_branch_any_arm_pic) \
2616 DEF_STUB(long_branch_any_thumb_pic) \
2617 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2618 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2619 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2620 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2621 DEF_STUB(long_branch_any_tls_pic) \
2622 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2623 DEF_STUB(long_branch_arm_nacl) \
2624 DEF_STUB(long_branch_arm_nacl_pic) \
48229727
JB		 2625 DEF_STUB(a8_veneer_b_cond) \
2626 DEF_STUB(a8_veneer_b) \
2627 DEF_STUB(a8_veneer_bl) \
2628 DEF_STUB(a8_veneer_blx)
738a79f6
CL		 2629
2630#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2631enum elf32_arm_stub_type
2632{
906e58ca 2633 arm_stub_none,
738a79f6
CL		 2634 DEF_STUBS
2635};
2636#undef DEF_STUB
2637
8d9d9490
TP		 2638/* Note the first a8_veneer type. */
2639const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2640
738a79f6
CL		 2641typedef struct
2642{
d3ce72d0 2643 const insn_sequence* template_sequence;
738a79f6
CL		 2644 int template_size;
2645} stub_def;
2646
2647#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2648static const stub_def stub_definitions[] =
2649{
738a79f6
CL		 2650 {NULL, 0},
2651 DEF_STUBS
906e58ca
NC		 2652};
2653
2654struct elf32_arm_stub_hash_entry
2655{
2656 /* Base hash table entry structure. */
2657 struct bfd_hash_entry root;
2658
2659 /* The stub section. */
2660 asection *stub_sec;
2661
2662 /* Offset within stub_sec of the beginning of this stub. */
2663 bfd_vma stub_offset;
2664
2665 /* Given the symbol's value and its section we can determine its final
2666 value when building the stubs (so the stub knows where to jump). */
2667 bfd_vma target_value;
2668 asection *target_section;
2669
8d9d9490
TP		 2670 /* Same as above but for the source of the branch to the stub. Used for
2671 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2672 such, source section does not need to be recorded since Cortex-A8 erratum
2673 workaround stubs are only generated when both source and target are in the
2674 same section. */
2675 bfd_vma source_value;
48229727
JB		 2676
2677 /* The instruction which caused this stub to be generated (only valid for
2678 Cortex-A8 erratum workaround stubs at present). */
2679 unsigned long orig_insn;
2680
461a49ca 2681 /* The stub type. */
906e58ca 2682 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2683 /* Its encoding size in bytes. */
2684 int stub_size;
2685 /* Its template. */
2686 const insn_sequence *stub_template;
2687 /* The size of the template (number of entries). */
2688 int stub_template_size;
906e58ca
NC		 2689
2690 /* The symbol table entry, if any, that this was derived from. */
2691 struct elf32_arm_link_hash_entry *h;
2692
35fc36a8
RS		 2693 /* Type of branch. */
2694 enum arm_st_branch_type branch_type;
906e58ca
NC		 2695
2696 /* Where this stub is being called from, or, in the case of combined
2697 stub sections, the first input section in the group. */
2698 asection *id_sec;
7413f23f
DJ		 2699
2700 /* The name for the local symbol at the start of this stub. The
2701 stub name in the hash table has to be unique; this does not, so
2702 it can be friendlier. */
2703 char *output_name;
906e58ca
NC		 2704};
2705
e489d0ae
PB		 2706/* Used to build a map of a section. This is required for mixed-endian
2707 code/data. */
2708
2709typedef struct elf32_elf_section_map
2710{
2711 bfd_vma vma;
2712 char type;
2713}
2714elf32_arm_section_map;
2715
c7b8f16e
JB		 2716/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2717
2718typedef enum
2719{
2720 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2721 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2722 VFP11_ERRATUM_ARM_VENEER,
2723 VFP11_ERRATUM_THUMB_VENEER
2724}
2725elf32_vfp11_erratum_type;
2726
2727typedef struct elf32_vfp11_erratum_list
2728{
2729 struct elf32_vfp11_erratum_list *next;
2730 bfd_vma vma;
2731 union
2732 {
2733 struct
2734 {
2735 struct elf32_vfp11_erratum_list *veneer;
2736 unsigned int vfp_insn;
2737 } b;
2738 struct
2739 {
2740 struct elf32_vfp11_erratum_list *branch;
2741 unsigned int id;
2742 } v;
2743 } u;
2744 elf32_vfp11_erratum_type type;
2745}
2746elf32_vfp11_erratum_list;
2747
a504d23a
LA		 2748/* Information about a STM32L4XX erratum veneer, or a branch to such a
2749 veneer. */
2750typedef enum
2751{
2752 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2753 STM32L4XX_ERRATUM_VENEER
2754}
2755elf32_stm32l4xx_erratum_type;
2756
2757typedef struct elf32_stm32l4xx_erratum_list
2758{
2759 struct elf32_stm32l4xx_erratum_list *next;
2760 bfd_vma vma;
2761 union
2762 {
2763 struct
2764 {
2765 struct elf32_stm32l4xx_erratum_list *veneer;
2766 unsigned int insn;
2767 } b;
2768 struct
2769 {
2770 struct elf32_stm32l4xx_erratum_list *branch;
2771 unsigned int id;
2772 } v;
2773 } u;
2774 elf32_stm32l4xx_erratum_type type;
2775}
2776elf32_stm32l4xx_erratum_list;
2777
2468f9c9
PB		 2778typedef enum
2779{
2780 DELETE_EXIDX_ENTRY,
2781 INSERT_EXIDX_CANTUNWIND_AT_END
2782}
2783arm_unwind_edit_type;
2784
2785/* A (sorted) list of edits to apply to an unwind table. */
2786typedef struct arm_unwind_table_edit
2787{
2788 arm_unwind_edit_type type;
2789 /* Note: we sometimes want to insert an unwind entry corresponding to a
2790 section different from the one we're currently writing out, so record the
2791 (text) section this edit relates to here. */
2792 asection *linked_section;
2793 unsigned int index;
2794 struct arm_unwind_table_edit *next;
2795}
2796arm_unwind_table_edit;
2797
8e3de13a 2798typedef struct _arm_elf_section_data
e489d0ae 2799{
2468f9c9 2800 /* Information about mapping symbols. */
e489d0ae 2801 struct bfd_elf_section_data elf;
8e3de13a 2802 unsigned int mapcount;
c7b8f16e 2803 unsigned int mapsize;
e489d0ae 2804 elf32_arm_section_map *map;
2468f9c9 2805 /* Information about CPU errata. */
c7b8f16e
JB		 2806 unsigned int erratumcount;
2807 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2808 unsigned int stm32l4xx_erratumcount;
2809 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2810 unsigned int additional_reloc_count;
2468f9c9
PB		 2811 /* Information about unwind tables. */
2812 union
2813 {
2814 /* Unwind info attached to a text section. */
2815 struct
2816 {
2817 asection *arm_exidx_sec;
2818 } text;
2819
2820 /* Unwind info attached to an .ARM.exidx section. */
2821 struct
2822 {
2823 arm_unwind_table_edit *unwind_edit_list;
2824 arm_unwind_table_edit *unwind_edit_tail;
2825 } exidx;
2826 } u;
8e3de13a
NC		 2827}
2828_arm_elf_section_data;
e489d0ae
PB		 2829
2830#define elf32_arm_section_data(sec) \
8e3de13a 2831 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2832
48229727
JB		 2833/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2834 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2835 so may be created multiple times: we use an array of these entries whilst
2836 relaxing which we can refresh easily, then create stubs for each potentially
2837 erratum-triggering instruction once we've settled on a solution. */
2838
b38cadfb
NC		 2839struct a8_erratum_fix
2840{
48229727
JB		 2841 bfd *input_bfd;
2842 asection *section;
2843 bfd_vma offset;
8d9d9490 2844 bfd_vma target_offset;
48229727
JB		 2845 unsigned long orig_insn;
2846 char *stub_name;
2847 enum elf32_arm_stub_type stub_type;
35fc36a8 2848 enum arm_st_branch_type branch_type;
48229727
JB		 2849};
2850
2851/* A table of relocs applied to branches which might trigger Cortex-A8
2852 erratum. */
2853
b38cadfb
NC		 2854struct a8_erratum_reloc
2855{
48229727
JB		 2856 bfd_vma from;
2857 bfd_vma destination;
92750f34
DJ		 2858 struct elf32_arm_link_hash_entry *hash;
2859 const char *sym_name;
48229727 2860 unsigned int r_type;
35fc36a8 2861 enum arm_st_branch_type branch_type;
48229727
JB		 2862 bfd_boolean non_a8_stub;
2863};
2864
ba93b8ac
DJ		 2865/* The size of the thread control block. */
2866#define TCB_SIZE 8
2867
34e77a92
RS		 2868/* ARM-specific information about a PLT entry, over and above the usual
2869 gotplt_union. */
b38cadfb
NC		 2870struct arm_plt_info
2871{
34e77a92
RS		 2872 /* We reference count Thumb references to a PLT entry separately,
2873 so that we can emit the Thumb trampoline only if needed. */
2874 bfd_signed_vma thumb_refcount;
2875
2876 /* Some references from Thumb code may be eliminated by BL->BLX
2877 conversion, so record them separately. */
2878 bfd_signed_vma maybe_thumb_refcount;
2879
2880 /* How many of the recorded PLT accesses were from non-call relocations.
2881 This information is useful when deciding whether anything takes the
2882 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2883 non-call references to the function should resolve directly to the
2884 real runtime target. */
2885 unsigned int noncall_refcount;
2886
2887 /* Since PLT entries have variable size if the Thumb prologue is
2888 used, we need to record the index into .got.plt instead of
2889 recomputing it from the PLT offset. */
2890 bfd_signed_vma got_offset;
2891};
2892
2893/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2894struct arm_local_iplt_info
2895{
34e77a92
RS		 2896 /* The information that is usually found in the generic ELF part of
2897 the hash table entry. */
2898 union gotplt_union root;
2899
2900 /* The information that is usually found in the ARM-specific part of
2901 the hash table entry. */
2902 struct arm_plt_info arm;
2903
2904 /* A list of all potential dynamic relocations against this symbol. */
2905 struct elf_dyn_relocs *dyn_relocs;
2906};
2907
0ffa91dd 2908struct elf_arm_obj_tdata
ba93b8ac
DJ		 2909{
2910 struct elf_obj_tdata root;
2911
2912 /* tls_type for each local got entry. */
2913 char *local_got_tls_type;
ee065d83 2914
0855e32b
NS		 2915 /* GOTPLT entries for TLS descriptors. */
2916 bfd_vma *local_tlsdesc_gotent;
2917
34e77a92
RS		 2918 /* Information for local symbols that need entries in .iplt. */
2919 struct arm_local_iplt_info **local_iplt;
2920
bf21ed78
MS		 2921 /* Zero to warn when linking objects with incompatible enum sizes. */
2922 int no_enum_size_warning;
a9dc9481
JM		 2923
2924 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2925 int no_wchar_size_warning;
ba93b8ac
DJ		 2926};
2927
0ffa91dd
NC		 2928#define elf_arm_tdata(bfd) \
2929 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 2930
0ffa91dd
NC		 2931#define elf32_arm_local_got_tls_type(bfd) \
2932 (elf_arm_tdata (bfd)->local_got_tls_type)
2933
0855e32b
NS		 2934#define elf32_arm_local_tlsdesc_gotent(bfd) \
2935 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2936
34e77a92
RS		 2937#define elf32_arm_local_iplt(bfd) \
2938 (elf_arm_tdata (bfd)->local_iplt)
2939
0ffa91dd
NC		 2940#define is_arm_elf(bfd) \
2941 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2942 && elf_tdata (bfd) != NULL \
4dfe6ac6 2943 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 2944
2945static bfd_boolean
2946elf32_arm_mkobject (bfd *abfd)
2947{
0ffa91dd 2948 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 2949 ARM_ELF_DATA);
ba93b8ac
DJ		 2950}
2951
ba93b8ac
DJ		 2952#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2953
ba96a88f 2954/* Arm ELF linker hash entry. */
252b5132 2955struct elf32_arm_link_hash_entry
b38cadfb
NC		 2956{
2957 struct elf_link_hash_entry root;
252b5132 2958
b38cadfb
NC		 2959 /* Track dynamic relocs copied for this symbol. */
2960 struct elf_dyn_relocs *dyn_relocs;
b7693d02 2961
b38cadfb
NC		 2962 /* ARM-specific PLT information. */
2963 struct arm_plt_info plt;
ba93b8ac
DJ		 2964
2965#define GOT_UNKNOWN 0
2966#define GOT_NORMAL 1
2967#define GOT_TLS_GD 2
2968#define GOT_TLS_IE 4
0855e32b
NS		 2969#define GOT_TLS_GDESC 8
2970#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 2971 unsigned int tls_type : 8;
34e77a92 2972
b38cadfb
NC		 2973 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
2974 unsigned int is_iplt : 1;
34e77a92 2975
b38cadfb 2976 unsigned int unused : 23;
a4fd1a8e 2977
b38cadfb
NC		 2978 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
2979 starting at the end of the jump table. */
2980 bfd_vma tlsdesc_got;
0855e32b 2981
b38cadfb
NC		 2982 /* The symbol marking the real symbol location for exported thumb
2983 symbols with Arm stubs. */
2984 struct elf_link_hash_entry *export_glue;
906e58ca 2985
b38cadfb 2986 /* A pointer to the most recently used stub hash entry against this
8029a119 2987 symbol. */
b38cadfb
NC		 2988 struct elf32_arm_stub_hash_entry *stub_cache;
2989};
252b5132 2990
252b5132 2991/* Traverse an arm ELF linker hash table. */
252b5132
RH		 2992#define elf32_arm_link_hash_traverse(table, func, info) \
2993 (elf_link_hash_traverse \
2994 (&(table)->root, \
b7693d02 2995 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 2996 (info)))
2997
2998/* Get the ARM elf linker hash table from a link_info structure. */
2999#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3000 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3001 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3002
906e58ca
NC		 3003#define arm_stub_hash_lookup(table, string, create, copy) \
3004 ((struct elf32_arm_stub_hash_entry *) \
3005 bfd_hash_lookup ((table), (string), (create), (copy)))
3006
21d799b5
NC		 3007/* Array to keep track of which stub sections have been created, and
3008 information on stub grouping. */
3009struct map_stub
3010{
3011 /* This is the section to which stubs in the group will be
3012 attached. */
3013 asection *link_sec;
3014 /* The stub section. */
3015 asection *stub_sec;
3016};
3017
0855e32b
NS		 3018#define elf32_arm_compute_jump_table_size(htab) \
3019 ((htab)->next_tls_desc_index * 4)
3020
9b485d32 3021/* ARM ELF linker hash table. */
252b5132 3022struct elf32_arm_link_hash_table
906e58ca
NC		 3023{
3024 /* The main hash table. */
3025 struct elf_link_hash_table root;
252b5132 3026
906e58ca
NC		 3027 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3028 bfd_size_type thumb_glue_size;
252b5132 3029
906e58ca
NC		 3030 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3031 bfd_size_type arm_glue_size;
252b5132 3032
906e58ca
NC		 3033 /* The size in bytes of section containing the ARMv4 BX veneers. */
3034 bfd_size_type bx_glue_size;
845b51d6 3035
906e58ca
NC		 3036 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3037 veneer has been populated. */
3038 bfd_vma bx_glue_offset[15];
845b51d6 3039
906e58ca
NC		 3040 /* The size in bytes of the section containing glue for VFP11 erratum
3041 veneers. */
3042 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3043
a504d23a
LA		 3044 /* The size in bytes of the section containing glue for STM32L4XX erratum
3045 veneers. */
3046 bfd_size_type stm32l4xx_erratum_glue_size;
3047
48229727
JB		 3048 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3049 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3050 elf32_arm_write_section(). */
3051 struct a8_erratum_fix *a8_erratum_fixes;
3052 unsigned int num_a8_erratum_fixes;
3053
906e58ca
NC		 3054 /* An arbitrary input BFD chosen to hold the glue sections. */
3055 bfd * bfd_of_glue_owner;
ba96a88f 3056
906e58ca
NC		 3057 /* Nonzero to output a BE8 image. */
3058 int byteswap_code;
e489d0ae 3059
906e58ca
NC		 3060 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3061 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3062 int target1_is_rel;
9c504268 3063
906e58ca
NC		 3064 /* The relocation to use for R_ARM_TARGET2 relocations. */
3065 int target2_reloc;
eb043451 3066
906e58ca
NC		 3067 /* 0 = Ignore R_ARM_V4BX.
3068 1 = Convert BX to MOV PC.
3069 2 = Generate v4 interworing stubs. */
3070 int fix_v4bx;
319850b4 3071
48229727
JB		 3072 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3073 int fix_cortex_a8;
3074
2de70689
MGD		 3075 /* Whether we should fix the ARM1176 BLX immediate issue. */
3076 int fix_arm1176;
3077
906e58ca
NC		 3078 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3079 int use_blx;
33bfe774 3080
906e58ca
NC		 3081 /* What sort of code sequences we should look for which may trigger the
3082 VFP11 denorm erratum. */
3083 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3084
906e58ca
NC		 3085 /* Global counter for the number of fixes we have emitted. */
3086 int num_vfp11_fixes;
c7b8f16e 3087
a504d23a
LA		 3088 /* What sort of code sequences we should look for which may trigger the
3089 STM32L4XX erratum. */
3090 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3091
3092 /* Global counter for the number of fixes we have emitted. */
3093 int num_stm32l4xx_fixes;
3094
906e58ca
NC		 3095 /* Nonzero to force PIC branch veneers. */
3096 int pic_veneer;
27e55c4d 3097
906e58ca
NC		 3098 /* The number of bytes in the initial entry in the PLT. */
3099 bfd_size_type plt_header_size;
e5a52504 3100
906e58ca
NC		 3101 /* The number of bytes in the subsequent PLT etries. */
3102 bfd_size_type plt_entry_size;
e5a52504 3103
906e58ca
NC		 3104 /* True if the target system is VxWorks. */
3105 int vxworks_p;
00a97672 3106
906e58ca
NC		 3107 /* True if the target system is Symbian OS. */
3108 int symbian_p;
e5a52504 3109
b38cadfb
NC		 3110 /* True if the target system is Native Client. */
3111 int nacl_p;
3112
906e58ca
NC		 3113 /* True if the target uses REL relocations. */
3114 int use_rel;
4e7fd91e 3115
0855e32b
NS		 3116 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3117 bfd_vma next_tls_desc_index;
3118
3119 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3120 bfd_vma num_tls_desc;
3121
906e58ca 3122 /* Short-cuts to get to dynamic linker sections. */
906e58ca
NC		 3123 asection *sdynbss;
3124 asection *srelbss;
5e681ec4 3125
906e58ca
NC		 3126 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3127 asection *srelplt2;
00a97672 3128
0855e32b
NS		 3129 /* The offset into splt of the PLT entry for the TLS descriptor
3130 resolver. Special values are 0, if not necessary (or not found
3131 to be necessary yet), and -1 if needed but not determined
3132 yet. */
3133 bfd_vma dt_tlsdesc_plt;
3134
3135 /* The offset into sgot of the GOT entry used by the PLT entry
3136 above. */
b38cadfb 3137 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3138
3139 /* Offset in .plt section of tls_arm_trampoline. */
3140 bfd_vma tls_trampoline;
3141
906e58ca
NC		 3142 /* Data for R_ARM_TLS_LDM32 relocations. */
3143 union
3144 {
3145 bfd_signed_vma refcount;
3146 bfd_vma offset;
3147 } tls_ldm_got;
b7693d02 3148
87d72d41
AM		 3149 /* Small local sym cache. */
3150 struct sym_cache sym_cache;
906e58ca
NC		 3151
3152 /* For convenience in allocate_dynrelocs. */
3153 bfd * obfd;
3154
0855e32b
NS		 3155 /* The amount of space used by the reserved portion of the sgotplt
3156 section, plus whatever space is used by the jump slots. */
3157 bfd_vma sgotplt_jump_table_size;
3158
906e58ca
NC		 3159 /* The stub hash table. */
3160 struct bfd_hash_table stub_hash_table;
3161
3162 /* Linker stub bfd. */
3163 bfd *stub_bfd;
3164
3165 /* Linker call-backs. */
7a89b94e 3166 asection * (*add_stub_section) (const char *, asection *, unsigned int);
906e58ca
NC		 3167 void (*layout_sections_again) (void);
3168
3169 /* Array to keep track of which stub sections have been created, and
3170 information on stub grouping. */
21d799b5 3171 struct map_stub *stub_group;
906e58ca 3172
fe33d2fa 3173 /* Number of elements in stub_group. */
7292b3ac 3174 unsigned int top_id;
fe33d2fa 3175
906e58ca
NC		 3176 /* Assorted information used by elf32_arm_size_stubs. */
3177 unsigned int bfd_count;
7292b3ac 3178 unsigned int top_index;
906e58ca
NC		 3179 asection **input_list;
3180};
252b5132 3181
a504d23a
LA		 3182static inline int
3183ctz (unsigned int mask)
3184{
3185#if GCC_VERSION >= 3004
3186 return __builtin_ctz (mask);
3187#else
3188 unsigned int i;
3189
3190 for (i = 0; i < 8 * sizeof (mask); i++)
3191 {
3192 if (mask & 0x1)
3193 break;
3194 mask = (mask >> 1);
3195 }
3196 return i;
3197#endif
3198}
3199
3200static inline int
3201popcount (unsigned int mask)
3202{
3203#if GCC_VERSION >= 3004
3204 return __builtin_popcount (mask);
3205#else
3206 unsigned int i, sum = 0;
3207
3208 for (i = 0; i < 8 * sizeof (mask); i++)
3209 {
3210 if (mask & 0x1)
3211 sum++;
3212 mask = (mask >> 1);
3213 }
3214 return sum;
3215#endif
3216}
3217
780a67af
NC		 3218/* Create an entry in an ARM ELF linker hash table. */
3219
3220static struct bfd_hash_entry *
57e8b36a 3221elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3222 struct bfd_hash_table * table,
3223 const char * string)
780a67af
NC		 3224{
3225 struct elf32_arm_link_hash_entry * ret =
3226 (struct elf32_arm_link_hash_entry *) entry;
3227
3228 /* Allocate the structure if it has not already been allocated by a
3229 subclass. */
906e58ca 3230 if (ret == NULL)
21d799b5 3231 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3232 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3233 if (ret == NULL)
780a67af
NC		 3234 return (struct bfd_hash_entry *) ret;
3235
3236 /* Call the allocation method of the superclass. */
3237 ret = ((struct elf32_arm_link_hash_entry *)
3238 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3239 table, string));
57e8b36a 3240 if (ret != NULL)
b7693d02 3241 {
0bdcacaf 3242 ret->dyn_relocs = NULL;
ba93b8ac 3243 ret->tls_type = GOT_UNKNOWN;
0855e32b 3244 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3245 ret->plt.thumb_refcount = 0;
3246 ret->plt.maybe_thumb_refcount = 0;
3247 ret->plt.noncall_refcount = 0;
3248 ret->plt.got_offset = -1;
3249 ret->is_iplt = FALSE;
a4fd1a8e 3250 ret->export_glue = NULL;
906e58ca
NC		 3251
3252 ret->stub_cache = NULL;
b7693d02 3253 }
780a67af
NC		 3254
3255 return (struct bfd_hash_entry *) ret;
3256}
3257
34e77a92
RS		 3258/* Ensure that we have allocated bookkeeping structures for ABFD's local
3259 symbols. */
3260
3261static bfd_boolean
3262elf32_arm_allocate_local_sym_info (bfd *abfd)
3263{
3264 if (elf_local_got_refcounts (abfd) == NULL)
3265 {
3266 bfd_size_type num_syms;
3267 bfd_size_type size;
3268 char *data;
3269
3270 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3271 size = num_syms * (sizeof (bfd_signed_vma)
3272 + sizeof (struct arm_local_iplt_info *)
3273 + sizeof (bfd_vma)
3274 + sizeof (char));
3275 data = bfd_zalloc (abfd, size);
3276 if (data == NULL)
3277 return FALSE;
3278
3279 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3280 data += num_syms * sizeof (bfd_signed_vma);
3281
3282 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3283 data += num_syms * sizeof (struct arm_local_iplt_info *);
3284
3285 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3286 data += num_syms * sizeof (bfd_vma);
3287
3288 elf32_arm_local_got_tls_type (abfd) = data;
3289 }
3290 return TRUE;
3291}
3292
3293/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3294 to input bfd ABFD. Create the information if it doesn't already exist.
3295 Return null if an allocation fails. */
3296
3297static struct arm_local_iplt_info *
3298elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3299{
3300 struct arm_local_iplt_info **ptr;
3301
3302 if (!elf32_arm_allocate_local_sym_info (abfd))
3303 return NULL;
3304
3305 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3306 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3307 if (*ptr == NULL)
3308 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3309 return *ptr;
3310}
3311
3312/* Try to obtain PLT information for the symbol with index R_SYMNDX
3313 in ABFD's symbol table. If the symbol is global, H points to its
3314 hash table entry, otherwise H is null.
3315
3316 Return true if the symbol does have PLT information. When returning
3317 true, point *ROOT_PLT at the target-independent reference count/offset
3318 union and *ARM_PLT at the ARM-specific information. */
3319
3320static bfd_boolean
3321elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_entry *h,
3322 unsigned long r_symndx, union gotplt_union **root_plt,
3323 struct arm_plt_info **arm_plt)
3324{
3325 struct arm_local_iplt_info *local_iplt;
3326
3327 if (h != NULL)
3328 {
3329 *root_plt = &h->root.plt;
3330 *arm_plt = &h->plt;
3331 return TRUE;
3332 }
3333
3334 if (elf32_arm_local_iplt (abfd) == NULL)
3335 return FALSE;
3336
3337 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3338 if (local_iplt == NULL)
3339 return FALSE;
3340
3341 *root_plt = &local_iplt->root;
3342 *arm_plt = &local_iplt->arm;
3343 return TRUE;
3344}
3345
3346/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3347 before it. */
3348
3349static bfd_boolean
3350elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3351 struct arm_plt_info *arm_plt)
3352{
3353 struct elf32_arm_link_hash_table *htab;
3354
3355 htab = elf32_arm_hash_table (info);
3356 return (arm_plt->thumb_refcount != 0
3357 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3358}
3359
3360/* Return a pointer to the head of the dynamic reloc list that should
3361 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3362 ABFD's symbol table. Return null if an error occurs. */
3363
3364static struct elf_dyn_relocs **
3365elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3366 Elf_Internal_Sym *isym)
3367{
3368 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3369 {
3370 struct arm_local_iplt_info *local_iplt;
3371
3372 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3373 if (local_iplt == NULL)
3374 return NULL;
3375 return &local_iplt->dyn_relocs;
3376 }
3377 else
3378 {
3379 /* Track dynamic relocs needed for local syms too.
3380 We really need local syms available to do this
3381 easily. Oh well. */
3382 asection *s;
3383 void *vpp;
3384
3385 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3386 if (s == NULL)
3387 abort ();
3388
3389 vpp = &elf_section_data (s)->local_dynrel;
3390 return (struct elf_dyn_relocs **) vpp;
3391 }
3392}
3393
906e58ca
NC		 3394/* Initialize an entry in the stub hash table. */
3395
3396static struct bfd_hash_entry *
3397stub_hash_newfunc (struct bfd_hash_entry *entry,
3398 struct bfd_hash_table *table,
3399 const char *string)
3400{
3401 /* Allocate the structure if it has not already been allocated by a
3402 subclass. */
3403 if (entry == NULL)
3404 {
21d799b5 3405 entry = (struct bfd_hash_entry *)
99059e56 3406 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3407 if (entry == NULL)
3408 return entry;
3409 }
3410
3411 /* Call the allocation method of the superclass. */
3412 entry = bfd_hash_newfunc (entry, table, string);
3413 if (entry != NULL)
3414 {
3415 struct elf32_arm_stub_hash_entry *eh;
3416
3417 /* Initialize the local fields. */
3418 eh = (struct elf32_arm_stub_hash_entry *) entry;
3419 eh->stub_sec = NULL;
3420 eh->stub_offset = 0;
8d9d9490 3421 eh->source_value = 0;
906e58ca
NC		 3422 eh->target_value = 0;
3423 eh->target_section = NULL;
cedfb179 3424 eh->orig_insn = 0;
906e58ca 3425 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3426 eh->stub_size = 0;
3427 eh->stub_template = NULL;
3428 eh->stub_template_size = 0;
906e58ca
NC		 3429 eh->h = NULL;
3430 eh->id_sec = NULL;
d8d2f433 3431 eh->output_name = NULL;
906e58ca
NC		 3432 }
3433
3434 return entry;
3435}
3436
00a97672 3437/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3438 shortcuts to them in our hash table. */
3439
3440static bfd_boolean
57e8b36a 3441create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3442{
3443 struct elf32_arm_link_hash_table *htab;
3444
e5a52504 3445 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3446 if (htab == NULL)
3447 return FALSE;
3448
e5a52504
MM		 3449 /* BPABI objects never have a GOT, or associated sections. */
3450 if (htab->symbian_p)
3451 return TRUE;
3452
5e681ec4
PB		 3453 if (! _bfd_elf_create_got_section (dynobj, info))
3454 return FALSE;
3455
5e681ec4
PB		 3456 return TRUE;
3457}
3458
34e77a92
RS		 3459/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3460
3461static bfd_boolean
3462create_ifunc_sections (struct bfd_link_info *info)
3463{
3464 struct elf32_arm_link_hash_table *htab;
3465 const struct elf_backend_data *bed;
3466 bfd *dynobj;
3467 asection *s;
3468 flagword flags;
b38cadfb 3469
34e77a92
RS		 3470 htab = elf32_arm_hash_table (info);
3471 dynobj = htab->root.dynobj;
3472 bed = get_elf_backend_data (dynobj);
3473 flags = bed->dynamic_sec_flags;
3474
3475 if (htab->root.iplt == NULL)
3476 {
3d4d4302
AM		 3477 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3478 flags | SEC_READONLY | SEC_CODE);
34e77a92 3479 if (s == NULL
a0f49396 3480 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3481 return FALSE;
3482 htab->root.iplt = s;
3483 }
3484
3485 if (htab->root.irelplt == NULL)
3486 {
3d4d4302
AM		 3487 s = bfd_make_section_anyway_with_flags (dynobj,
3488 RELOC_SECTION (htab, ".iplt"),
3489 flags | SEC_READONLY);
34e77a92 3490 if (s == NULL
a0f49396 3491 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3492 return FALSE;
3493 htab->root.irelplt = s;
3494 }
3495
3496 if (htab->root.igotplt == NULL)
3497 {
3d4d4302 3498 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3499 if (s == NULL
3500 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3501 return FALSE;
3502 htab->root.igotplt = s;
3503 }
3504 return TRUE;
3505}
3506
eed94f8f
NC		 3507/* Determine if we're dealing with a Thumb only architecture. */
3508
3509static bfd_boolean
3510using_thumb_only (struct elf32_arm_link_hash_table *globals)
3511{
2fd158eb
TP		 3512 int arch;
3513 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3514 Tag_CPU_arch_profile);
eed94f8f 3515
2fd158eb
TP		 3516 if (profile)
3517 return profile == 'M';
eed94f8f 3518
2fd158eb 3519 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3520
2fd158eb
TP		 3521 if (arch == TAG_CPU_ARCH_V6_M
3522 || arch == TAG_CPU_ARCH_V6S_M
3523 || arch == TAG_CPU_ARCH_V7E_M
3524 || arch == TAG_CPU_ARCH_V8M_BASE
3525 || arch == TAG_CPU_ARCH_V8M_MAIN)
3526 return TRUE;
eed94f8f 3527
2fd158eb 3528 return FALSE;
eed94f8f
NC		 3529}
3530
3531/* Determine if we're dealing with a Thumb-2 object. */
3532
3533static bfd_boolean
3534using_thumb2 (struct elf32_arm_link_hash_table *globals)
3535{
3536 int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3537 Tag_CPU_arch);
3538 return arch == TAG_CPU_ARCH_V6T2 || arch >= TAG_CPU_ARCH_V7;
3539}
3540
00a97672
RS		 3541/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3542 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3543 hash table. */
3544
3545static bfd_boolean
57e8b36a 3546elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3547{
3548 struct elf32_arm_link_hash_table *htab;
3549
3550 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3551 if (htab == NULL)
3552 return FALSE;
3553
362d30a1 3554 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3555 return FALSE;
3556
3557 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3558 return FALSE;
3559
3d4d4302 3560 htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss");
0e1862bb 3561 if (!bfd_link_pic (info))
3d4d4302
AM		 3562 htab->srelbss = bfd_get_linker_section (dynobj,
3563 RELOC_SECTION (htab, ".bss"));
00a97672
RS		 3564
3565 if (htab->vxworks_p)
3566 {
3567 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3568 return FALSE;
3569
0e1862bb 3570 if (bfd_link_pic (info))
00a97672
RS		 3571 {
3572 htab->plt_header_size = 0;
3573 htab->plt_entry_size
3574 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3575 }
3576 else
3577 {
3578 htab->plt_header_size
3579 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3580 htab->plt_entry_size
3581 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3582 }
aebf9be7
NC		 3583
3584 if (elf_elfheader (dynobj))
3585 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3586 }
eed94f8f
NC		 3587 else
3588 {
3589 /* PR ld/16017
3590 Test for thumb only architectures. Note - we cannot just call
3591 using_thumb_only() as the attributes in the output bfd have not been
3592 initialised at this point, so instead we use the input bfd. */
3593 bfd * saved_obfd = htab->obfd;
3594
3595 htab->obfd = dynobj;
3596 if (using_thumb_only (htab))
3597 {
3598 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3599 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3600 }
3601 htab->obfd = saved_obfd;
3602 }
5e681ec4 3603
362d30a1
RS		 3604 if (!htab->root.splt
3605 || !htab->root.srelplt
e5a52504 3606 || !htab->sdynbss
0e1862bb 3607 || (!bfd_link_pic (info) && !htab->srelbss))
5e681ec4
PB		 3608 abort ();
3609
3610 return TRUE;
3611}
3612
906e58ca
NC		 3613/* Copy the extra info we tack onto an elf_link_hash_entry. */
3614
3615static void
3616elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3617 struct elf_link_hash_entry *dir,
3618 struct elf_link_hash_entry *ind)
3619{
3620 struct elf32_arm_link_hash_entry *edir, *eind;
3621
3622 edir = (struct elf32_arm_link_hash_entry *) dir;
3623 eind = (struct elf32_arm_link_hash_entry *) ind;
3624
0bdcacaf 3625 if (eind->dyn_relocs != NULL)
906e58ca 3626 {
0bdcacaf 3627 if (edir->dyn_relocs != NULL)
906e58ca 3628 {
0bdcacaf
RS		 3629 struct elf_dyn_relocs **pp;
3630 struct elf_dyn_relocs *p;
906e58ca
NC		 3631
3632 /* Add reloc counts against the indirect sym to the direct sym
3633 list. Merge any entries against the same section. */
0bdcacaf 3634 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3635 {
0bdcacaf 3636 struct elf_dyn_relocs *q;
906e58ca 3637
0bdcacaf
RS		 3638 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3639 if (q->sec == p->sec)
906e58ca
NC		 3640 {
3641 q->pc_count += p->pc_count;
3642 q->count += p->count;
3643 *pp = p->next;
3644 break;
3645 }
3646 if (q == NULL)
3647 pp = &p->next;
3648 }
0bdcacaf 3649 *pp = edir->dyn_relocs;
906e58ca
NC		 3650 }
3651
0bdcacaf
RS		 3652 edir->dyn_relocs = eind->dyn_relocs;
3653 eind->dyn_relocs = NULL;
906e58ca
NC		 3654 }
3655
3656 if (ind->root.type == bfd_link_hash_indirect)
3657 {
3658 /* Copy over PLT info. */
34e77a92
RS		 3659 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3660 eind->plt.thumb_refcount = 0;
3661 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3662 eind->plt.maybe_thumb_refcount = 0;
3663 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3664 eind->plt.noncall_refcount = 0;
3665
3666 /* We should only allocate a function to .iplt once the final
3667 symbol information is known. */
3668 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3669
3670 if (dir->got.refcount <= 0)
3671 {
3672 edir->tls_type = eind->tls_type;
3673 eind->tls_type = GOT_UNKNOWN;
3674 }
3675 }
3676
3677 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3678}
3679
68faa637
AM		 3680/* Destroy an ARM elf linker hash table. */
3681
3682static void
d495ab0d 3683elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3684{
3685 struct elf32_arm_link_hash_table *ret
d495ab0d 3686 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3687
3688 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3689 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3690}
3691
906e58ca
NC		 3692/* Create an ARM elf linker hash table. */
3693
3694static struct bfd_link_hash_table *
3695elf32_arm_link_hash_table_create (bfd *abfd)
3696{
3697 struct elf32_arm_link_hash_table *ret;
3698 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3699
7bf52ea2 3700 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3701 if (ret == NULL)
3702 return NULL;
3703
3704 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3705 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3706 sizeof (struct elf32_arm_link_hash_entry),
3707 ARM_ELF_DATA))
906e58ca
NC		 3708 {
3709 free (ret);
3710 return NULL;
3711 }
3712
906e58ca 3713 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3714 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3715#ifdef FOUR_WORD_PLT
3716 ret->plt_header_size = 16;
3717 ret->plt_entry_size = 16;
3718#else
3719 ret->plt_header_size = 20;
1db37fe6 3720 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3721#endif
906e58ca 3722 ret->use_rel = 1;
906e58ca 3723 ret->obfd = abfd;
906e58ca
NC		 3724
3725 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3726 sizeof (struct elf32_arm_stub_hash_entry)))
3727 {
d495ab0d 3728 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3729 return NULL;
3730 }
d495ab0d 3731 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3732
3733 return &ret->root.root;
3734}
3735
cd1dac3d
DG		 3736/* Determine what kind of NOPs are available. */
3737
3738static bfd_boolean
3739arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3740{
3741 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3742 Tag_CPU_arch);
3743 return arch == TAG_CPU_ARCH_V6T2
3744 || arch == TAG_CPU_ARCH_V6K
9e3c6df6
PB		 3745 || arch == TAG_CPU_ARCH_V7
3746 || arch == TAG_CPU_ARCH_V7E_M;
cd1dac3d
DG		 3747}
3748
3749static bfd_boolean
3750arch_has_thumb2_nop (struct elf32_arm_link_hash_table *globals)
3751{
3752 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3753 Tag_CPU_arch);
9e3c6df6
PB		 3754 return (arch == TAG_CPU_ARCH_V6T2 || arch == TAG_CPU_ARCH_V7
3755 || arch == TAG_CPU_ARCH_V7E_M);
cd1dac3d
DG		 3756}
3757
f4ac8484
DJ		 3758static bfd_boolean
3759arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3760{
3761 switch (stub_type)
3762 {
fea2b4d6
CL		 3763 case arm_stub_long_branch_thumb_only:
3764 case arm_stub_long_branch_v4t_thumb_arm:
3765 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3766 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3767 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3768 case arm_stub_long_branch_thumb_only_pic:
f4ac8484
DJ		 3769 return TRUE;
3770 case arm_stub_none:
3771 BFD_FAIL ();
3772 return FALSE;
3773 break;
3774 default:
3775 return FALSE;
3776 }
3777}
3778
906e58ca
NC		 3779/* Determine the type of stub needed, if any, for a call. */
3780
3781static enum elf32_arm_stub_type
3782arm_type_of_stub (struct bfd_link_info *info,
3783 asection *input_sec,
3784 const Elf_Internal_Rela *rel,
34e77a92 3785 unsigned char st_type,
35fc36a8 3786 enum arm_st_branch_type *actual_branch_type,
906e58ca 3787 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3788 bfd_vma destination,
3789 asection *sym_sec,
3790 bfd *input_bfd,
3791 const char *name)
906e58ca
NC		 3792{
3793 bfd_vma location;
3794 bfd_signed_vma branch_offset;
3795 unsigned int r_type;
3796 struct elf32_arm_link_hash_table * globals;
3797 int thumb2;
3798 int thumb_only;
3799 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3800 int use_plt = 0;
35fc36a8 3801 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3802 union gotplt_union *root_plt;
3803 struct arm_plt_info *arm_plt;
906e58ca 3804
35fc36a8 3805 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3806 return stub_type;
3807
906e58ca 3808 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3809 if (globals == NULL)
3810 return stub_type;
906e58ca
NC		 3811
3812 thumb_only = using_thumb_only (globals);
3813
3814 thumb2 = using_thumb2 (globals);
3815
3816 /* Determine where the call point is. */
3817 location = (input_sec->output_offset
3818 + input_sec->output_section->vma
3819 + rel->r_offset);
3820
906e58ca
NC		 3821 r_type = ELF32_R_TYPE (rel->r_info);
3822
39f21624
NC		 3823 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3824 are considering a function call relocation. */
c5423981
TG		 3825 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
3826 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3827 && branch_type == ST_BRANCH_TO_ARM)
3828 branch_type = ST_BRANCH_TO_THUMB;
3829
34e77a92
RS		 3830 /* For TLS call relocs, it is the caller's responsibility to provide
3831 the address of the appropriate trampoline. */
3832 if (r_type != R_ARM_TLS_CALL
3833 && r_type != R_ARM_THM_TLS_CALL
3834 && elf32_arm_get_plt_info (input_bfd, hash, ELF32_R_SYM (rel->r_info),
3835 &root_plt, &arm_plt)
3836 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3837 {
34e77a92 3838 asection *splt;
fe33d2fa 3839
34e77a92
RS		 3840 if (hash == NULL || hash->is_iplt)
3841 splt = globals->root.iplt;
3842 else
3843 splt = globals->root.splt;
3844 if (splt != NULL)
b38cadfb 3845 {
34e77a92
RS		 3846 use_plt = 1;
3847
3848 /* Note when dealing with PLT entries: the main PLT stub is in
3849 ARM mode, so if the branch is in Thumb mode, another
3850 Thumb->ARM stub will be inserted later just before the ARM
3851 PLT stub. We don't take this extra distance into account
3852 here, because if a long branch stub is needed, we'll add a
3853 Thumb->Arm one and branch directly to the ARM PLT entry
3854 because it avoids spreading offset corrections in several
3855 places. */
3856
3857 destination = (splt->output_section->vma
3858 + splt->output_offset
3859 + root_plt->offset);
3860 st_type = STT_FUNC;
3861 branch_type = ST_BRANCH_TO_ARM;
3862 }
5fa9e92f 3863 }
34e77a92
RS		 3864 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3865 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 3866
fe33d2fa
CL		 3867 branch_offset = (bfd_signed_vma)(destination - location);
3868
0855e32b 3869 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 3870 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 3871 {
5fa9e92f
CL		 3872 /* Handle cases where:
3873 - this call goes too far (different Thumb/Thumb2 max
99059e56 3874 distance)
155d87d7 3875 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 3876 Thumb->Arm branch (not bl). A stub is needed in this case,
3877 but only if this call is not through a PLT entry. Indeed,
3878 PLT stubs handle mode switching already.
5fa9e92f 3879 */
906e58ca
NC		 3880 if ((!thumb2
3881 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
3882 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
3883 || (thumb2
3884 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
3885 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 3886 || (thumb2
3887 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
3888 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
3889 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 3890 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 3891 && (((r_type == R_ARM_THM_CALL
3892 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981
TG		 3893 || (r_type == R_ARM_THM_JUMP24)
3894 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 3895 && !use_plt))
906e58ca 3896 {
35fc36a8 3897 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 3898 {
3899 /* Thumb to thumb. */
3900 if (!thumb_only)
3901 {
0e1862bb 3902 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3903 /* PIC stubs. */
155d87d7 3904 ? ((globals->use_blx
9553db3c 3905 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 3906 /* V5T and above. Stub starts with ARM code, so
3907 we must be able to switch mode before
3908 reaching it, which is only possible for 'bl'
3909 (ie R_ARM_THM_CALL relocation). */
cf3eccff 3910 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 3911 /* On V4T, use Thumb code only. */
d3626fb0 3912 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 3913
3914 /* non-PIC stubs. */
155d87d7 3915 : ((globals->use_blx
9553db3c 3916 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 3917 /* V5T and above. */
3918 ? arm_stub_long_branch_any_any
3919 /* V4T. */
d3626fb0 3920 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 3921 }
3922 else
3923 {
0e1862bb 3924 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
ebe24dd4
CL		 3925 /* PIC stub. */
3926 ? arm_stub_long_branch_thumb_only_pic
c2b4a39d
CL		 3927 /* non-PIC stub. */
3928 : arm_stub_long_branch_thumb_only;
906e58ca
NC		 3929 }
3930 }
3931 else
3932 {
3933 /* Thumb to arm. */
c820be07
NC		 3934 if (sym_sec != NULL
3935 && sym_sec->owner != NULL
3936 && !INTERWORK_FLAG (sym_sec->owner))
3937 {
3938 (*_bfd_error_handler)
3939 (_("%B(%s): warning: interworking not enabled.\n"
3940 " first occurrence: %B: Thumb call to ARM"),
3941 sym_sec->owner, input_bfd, name);
3942 }
3943
0855e32b 3944 stub_type =
0e1862bb 3945 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3946 /* PIC stubs. */
0855e32b 3947 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 3948 /* TLS PIC stubs. */
0855e32b
NS		 3949 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
3950 : arm_stub_long_branch_v4t_thumb_tls_pic)
3951 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
3952 /* V5T PIC and above. */
3953 ? arm_stub_long_branch_any_arm_pic
3954 /* V4T PIC stub. */
3955 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 3956
3957 /* non-PIC stubs. */
0855e32b 3958 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 3959 /* V5T and above. */
3960 ? arm_stub_long_branch_any_any
3961 /* V4T. */
3962 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 3963
3964 /* Handle v4t short branches. */
fea2b4d6 3965 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 3966 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
3967 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 3968 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 3969 }
3970 }
3971 }
fe33d2fa
CL		 3972 else if (r_type == R_ARM_CALL
3973 || r_type == R_ARM_JUMP24
0855e32b
NS		 3974 || r_type == R_ARM_PLT32
3975 || r_type == R_ARM_TLS_CALL)
906e58ca 3976 {
35fc36a8 3977 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 3978 {
3979 /* Arm to thumb. */
c820be07
NC		 3980
3981 if (sym_sec != NULL
3982 && sym_sec->owner != NULL
3983 && !INTERWORK_FLAG (sym_sec->owner))
3984 {
3985 (*_bfd_error_handler)
3986 (_("%B(%s): warning: interworking not enabled.\n"
c2b4a39d 3987 " first occurrence: %B: ARM call to Thumb"),
c820be07
NC		 3988 sym_sec->owner, input_bfd, name);
3989 }
3990
3991 /* We have an extra 2-bytes reach because of
3992 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 3993 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
3994 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 3995 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 3996 || (r_type == R_ARM_JUMP24)
3997 || (r_type == R_ARM_PLT32))
906e58ca 3998 {
0e1862bb 3999 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4000 /* PIC stubs. */
ebe24dd4
CL		 4001 ? ((globals->use_blx)
4002 /* V5T and above. */
4003 ? arm_stub_long_branch_any_thumb_pic
4004 /* V4T stub. */
4005 : arm_stub_long_branch_v4t_arm_thumb_pic)
4006
c2b4a39d
CL		 4007 /* non-PIC stubs. */
4008 : ((globals->use_blx)
4009 /* V5T and above. */
4010 ? arm_stub_long_branch_any_any
4011 /* V4T. */
4012 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4013 }
4014 }
4015 else
4016 {
4017 /* Arm to arm. */
4018 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4019 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4020 {
0855e32b 4021 stub_type =
0e1862bb 4022 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4023 /* PIC stubs. */
0855e32b 4024 ? (r_type == R_ARM_TLS_CALL
6a631e86 4025 /* TLS PIC Stub. */
0855e32b 4026 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4027 : (globals->nacl_p
4028 ? arm_stub_long_branch_arm_nacl_pic
4029 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4030 /* non-PIC stubs. */
7a89b94e
NC		 4031 : (globals->nacl_p
4032 ? arm_stub_long_branch_arm_nacl
4033 : arm_stub_long_branch_any_any);
906e58ca
NC		 4034 }
4035 }
4036 }
4037
fe33d2fa
CL		 4038 /* If a stub is needed, record the actual destination type. */
4039 if (stub_type != arm_stub_none)
35fc36a8 4040 *actual_branch_type = branch_type;
fe33d2fa 4041
906e58ca
NC		 4042 return stub_type;
4043}
4044
4045/* Build a name for an entry in the stub hash table. */
4046
4047static char *
4048elf32_arm_stub_name (const asection *input_section,
4049 const asection *sym_sec,
4050 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4051 const Elf_Internal_Rela *rel,
4052 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4053{
4054 char *stub_name;
4055 bfd_size_type len;
4056
4057 if (hash)
4058 {
fe33d2fa 4059 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4060 stub_name = (char *) bfd_malloc (len);
906e58ca 4061 if (stub_name != NULL)
fe33d2fa 4062 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4063 input_section->id & 0xffffffff,
4064 hash->root.root.root.string,
fe33d2fa
CL		 4065 (int) rel->r_addend & 0xffffffff,
4066 (int) stub_type);
906e58ca
NC		 4067 }
4068 else
4069 {
fe33d2fa 4070 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4071 stub_name = (char *) bfd_malloc (len);
906e58ca 4072 if (stub_name != NULL)
fe33d2fa 4073 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4074 input_section->id & 0xffffffff,
4075 sym_sec->id & 0xffffffff,
0855e32b
NS		 4076 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4077 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4078 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4079 (int) rel->r_addend & 0xffffffff,
4080 (int) stub_type);
906e58ca
NC		 4081 }
4082
4083 return stub_name;
4084}
4085
4086/* Look up an entry in the stub hash. Stub entries are cached because
4087 creating the stub name takes a bit of time. */
4088
4089static struct elf32_arm_stub_hash_entry *
4090elf32_arm_get_stub_entry (const asection *input_section,
4091 const asection *sym_sec,
4092 struct elf_link_hash_entry *hash,
4093 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4094 struct elf32_arm_link_hash_table *htab,
4095 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4096{
4097 struct elf32_arm_stub_hash_entry *stub_entry;
4098 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4099 const asection *id_sec;
4100
4101 if ((input_section->flags & SEC_CODE) == 0)
4102 return NULL;
4103
4104 /* If this input section is part of a group of sections sharing one
4105 stub section, then use the id of the first section in the group.
4106 Stub names need to include a section id, as there may well be
4107 more than one stub used to reach say, printf, and we need to
4108 distinguish between them. */
4109 id_sec = htab->stub_group[input_section->id].link_sec;
4110
4111 if (h != NULL && h->stub_cache != NULL
4112 && h->stub_cache->h == h
fe33d2fa
CL		 4113 && h->stub_cache->id_sec == id_sec
4114 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4115 {
4116 stub_entry = h->stub_cache;
4117 }
4118 else
4119 {
4120 char *stub_name;
4121
fe33d2fa 4122 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4123 if (stub_name == NULL)
4124 return NULL;
4125
4126 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4127 stub_name, FALSE, FALSE);
4128 if (h != NULL)
4129 h->stub_cache = stub_entry;
4130
4131 free (stub_name);
4132 }
4133
4134 return stub_entry;
4135}
4136
48229727 4137/* Find or create a stub section. Returns a pointer to the stub section, and
b38cadfb 4138 the section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4139 LINK_SEC_P may be NULL. */
906e58ca 4140
48229727
JB		 4141static asection *
4142elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
4143 struct elf32_arm_link_hash_table *htab)
906e58ca
NC		 4144{
4145 asection *link_sec;
4146 asection *stub_sec;
906e58ca
NC		 4147
4148 link_sec = htab->stub_group[section->id].link_sec;
9553db3c 4149 BFD_ASSERT (link_sec != NULL);
906e58ca 4150 stub_sec = htab->stub_group[section->id].stub_sec;
9553db3c 4151
906e58ca
NC		 4152 if (stub_sec == NULL)
4153 {
4154 stub_sec = htab->stub_group[link_sec->id].stub_sec;
4155 if (stub_sec == NULL)
4156 {
4157 size_t namelen;
4158 bfd_size_type len;
4159 char *s_name;
4160
4161 namelen = strlen (link_sec->name);
4162 len = namelen + sizeof (STUB_SUFFIX);
21d799b5 4163 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
906e58ca
NC		 4164 if (s_name == NULL)
4165 return NULL;
4166
4167 memcpy (s_name, link_sec->name, namelen);
4168 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
7a89b94e
NC		 4169 stub_sec = (*htab->add_stub_section) (s_name, link_sec,
4170 htab->nacl_p ? 4 : 3);
906e58ca
NC		 4171 if (stub_sec == NULL)
4172 return NULL;
4173 htab->stub_group[link_sec->id].stub_sec = stub_sec;
4174 }
4175 htab->stub_group[section->id].stub_sec = stub_sec;
4176 }
b38cadfb 4177
48229727
JB		 4178 if (link_sec_p)
4179 *link_sec_p = link_sec;
b38cadfb 4180
48229727
JB		 4181 return stub_sec;
4182}
4183
4184/* Add a new stub entry to the stub hash. Not all fields of the new
4185 stub entry are initialised. */
4186
4187static struct elf32_arm_stub_hash_entry *
4188elf32_arm_add_stub (const char *stub_name,
4189 asection *section,
4190 struct elf32_arm_link_hash_table *htab)
4191{
4192 asection *link_sec;
4193 asection *stub_sec;
4194 struct elf32_arm_stub_hash_entry *stub_entry;
4195
4196 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab);
4197 if (stub_sec == NULL)
4198 return NULL;
906e58ca
NC		 4199
4200 /* Enter this entry into the linker stub hash table. */
4201 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4202 TRUE, FALSE);
4203 if (stub_entry == NULL)
4204 {
4205 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
4206 section->owner,
4207 stub_name);
4208 return NULL;
4209 }
4210
4211 stub_entry->stub_sec = stub_sec;
4212 stub_entry->stub_offset = 0;
4213 stub_entry->id_sec = link_sec;
4214
906e58ca
NC		 4215 return stub_entry;
4216}
4217
4218/* Store an Arm insn into an output section not processed by
4219 elf32_arm_write_section. */
4220
4221static void
8029a119
NC		 4222put_arm_insn (struct elf32_arm_link_hash_table * htab,
4223 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4224{
4225 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4226 bfd_putl32 (val, ptr);
4227 else
4228 bfd_putb32 (val, ptr);
4229}
4230
4231/* Store a 16-bit Thumb insn into an output section not processed by
4232 elf32_arm_write_section. */
4233
4234static void
8029a119
NC		 4235put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4236 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4237{
4238 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4239 bfd_putl16 (val, ptr);
4240 else
4241 bfd_putb16 (val, ptr);
4242}
4243
a504d23a
LA		 4244/* Store a Thumb2 insn into an output section not processed by
4245 elf32_arm_write_section. */
4246
4247static void
4248put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4249 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4250{
4251 /* T2 instructions are 16-bit streamed. */
4252 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4253 {
4254 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4255 bfd_putl16 ((val & 0xffff), ptr + 2);
4256 }
4257 else
4258 {
4259 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4260 bfd_putb16 ((val & 0xffff), ptr + 2);
4261 }
4262}
4263
0855e32b
NS		 4264/* If it's possible to change R_TYPE to a more efficient access
4265 model, return the new reloc type. */
4266
4267static unsigned
b38cadfb 4268elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4269 struct elf_link_hash_entry *h)
4270{
4271 int is_local = (h == NULL);
4272
0e1862bb
L		 4273 if (bfd_link_pic (info)
4274 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4275 return r_type;
4276
b38cadfb 4277 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4278 switch (r_type)
4279 {
4280 case R_ARM_TLS_GOTDESC:
4281 case R_ARM_TLS_CALL:
4282 case R_ARM_THM_TLS_CALL:
4283 case R_ARM_TLS_DESCSEQ:
4284 case R_ARM_THM_TLS_DESCSEQ:
4285 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4286 }
4287
4288 return r_type;
4289}
4290
48229727
JB		 4291static bfd_reloc_status_type elf32_arm_final_link_relocate
4292 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4293 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4294 const char *, unsigned char, enum arm_st_branch_type,
4295 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4296
4563a860
JB		 4297static unsigned int
4298arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4299{
4300 switch (stub_type)
4301 {
4302 case arm_stub_a8_veneer_b_cond:
4303 case arm_stub_a8_veneer_b:
4304 case arm_stub_a8_veneer_bl:
4305 return 2;
4306
4307 case arm_stub_long_branch_any_any:
4308 case arm_stub_long_branch_v4t_arm_thumb:
4309 case arm_stub_long_branch_thumb_only:
4310 case arm_stub_long_branch_v4t_thumb_thumb:
4311 case arm_stub_long_branch_v4t_thumb_arm:
4312 case arm_stub_short_branch_v4t_thumb_arm:
4313 case arm_stub_long_branch_any_arm_pic:
4314 case arm_stub_long_branch_any_thumb_pic:
4315 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4316 case arm_stub_long_branch_v4t_arm_thumb_pic:
4317 case arm_stub_long_branch_v4t_thumb_arm_pic:
4318 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4319 case arm_stub_long_branch_any_tls_pic:
4320 case arm_stub_long_branch_v4t_thumb_tls_pic:
4563a860
JB		 4321 case arm_stub_a8_veneer_blx:
4322 return 4;
b38cadfb 4323
7a89b94e
NC		 4324 case arm_stub_long_branch_arm_nacl:
4325 case arm_stub_long_branch_arm_nacl_pic:
4326 return 16;
4327
4563a860
JB		 4328 default:
4329 abort (); /* Should be unreachable. */
4330 }
4331}
4332
906e58ca
NC		 4333static bfd_boolean
4334arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4335 void * in_arg)
4336{
7a89b94e 4337#define MAXRELOCS 3
906e58ca 4338 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4339 struct elf32_arm_link_hash_table *globals;
906e58ca 4340 struct bfd_link_info *info;
906e58ca
NC		 4341 asection *stub_sec;
4342 bfd *stub_bfd;
906e58ca
NC		 4343 bfd_byte *loc;
4344 bfd_vma sym_value;
4345 int template_size;
4346 int size;
d3ce72d0 4347 const insn_sequence *template_sequence;
906e58ca 4348 int i;
48229727
JB		 4349 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4350 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4351 int nrelocs = 0;
906e58ca
NC		 4352
4353 /* Massage our args to the form they really have. */
4354 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4355 info = (struct bfd_link_info *) in_arg;
4356
4357 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4358 if (globals == NULL)
4359 return FALSE;
906e58ca 4360
906e58ca
NC		 4361 stub_sec = stub_entry->stub_sec;
4362
4dfe6ac6 4363 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4364 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4365 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4366 return TRUE;
fe33d2fa 4367
906e58ca
NC		 4368 /* Make a note of the offset within the stubs for this entry. */
4369 stub_entry->stub_offset = stub_sec->size;
4370 loc = stub_sec->contents + stub_entry->stub_offset;
4371
4372 stub_bfd = stub_sec->owner;
4373
906e58ca
NC		 4374 /* This is the address of the stub destination. */
4375 sym_value = (stub_entry->target_value
4376 + stub_entry->target_section->output_offset
4377 + stub_entry->target_section->output_section->vma);
4378
d3ce72d0 4379 template_sequence = stub_entry->stub_template;
461a49ca 4380 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4381
4382 size = 0;
461a49ca 4383 for (i = 0; i < template_size; i++)
906e58ca 4384 {
d3ce72d0 4385 switch (template_sequence[i].type)
461a49ca
DJ		 4386 {
4387 case THUMB16_TYPE:
48229727 4388 {
d3ce72d0
NC		 4389 bfd_vma data = (bfd_vma) template_sequence[i].data;
4390 if (template_sequence[i].reloc_addend != 0)
48229727 4391 {
99059e56
RM		 4392 /* We've borrowed the reloc_addend field to mean we should
4393 insert a condition code into this (Thumb-1 branch)
4394 instruction. See THUMB16_BCOND_INSN. */
4395 BFD_ASSERT ((data & 0xff00) == 0xd000);
4396 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4397 }
fe33d2fa 4398 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4399 size += 2;
4400 }
461a49ca 4401 break;
906e58ca 4402
48229727 4403 case THUMB32_TYPE:
fe33d2fa
CL		 4404 bfd_put_16 (stub_bfd,
4405 (template_sequence[i].data >> 16) & 0xffff,
4406 loc + size);
4407 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4408 loc + size + 2);
99059e56
RM		 4409 if (template_sequence[i].r_type != R_ARM_NONE)
4410 {
4411 stub_reloc_idx[nrelocs] = i;
4412 stub_reloc_offset[nrelocs++] = size;
4413 }
4414 size += 4;
4415 break;
48229727 4416
461a49ca 4417 case ARM_TYPE:
fe33d2fa
CL		 4418 bfd_put_32 (stub_bfd, template_sequence[i].data,
4419 loc + size);
461a49ca
DJ		 4420 /* Handle cases where the target is encoded within the
4421 instruction. */
d3ce72d0 4422 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4423 {
48229727
JB		 4424 stub_reloc_idx[nrelocs] = i;
4425 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4426 }
4427 size += 4;
4428 break;
4429
4430 case DATA_TYPE:
d3ce72d0 4431 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4432 stub_reloc_idx[nrelocs] = i;
4433 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4434 size += 4;
4435 break;
4436
4437 default:
4438 BFD_FAIL ();
4439 return FALSE;
4440 }
906e58ca 4441 }
461a49ca 4442
906e58ca
NC		 4443 stub_sec->size += size;
4444
461a49ca
DJ		 4445 /* Stub size has already been computed in arm_size_one_stub. Check
4446 consistency. */
4447 BFD_ASSERT (size == stub_entry->stub_size);
4448
906e58ca 4449 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4450 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4451 sym_value |= 1;
4452
48229727
JB		 4453 /* Assume there is at least one and at most MAXRELOCS entries to relocate
4454 in each stub. */
4455 BFD_ASSERT (nrelocs != 0 && nrelocs <= MAXRELOCS);
c820be07 4456
48229727 4457 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 4458 {
4459 Elf_Internal_Rela rel;
4460 bfd_boolean unresolved_reloc;
4461 char *error_message;
4462 bfd_vma points_to =
4463 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
4464
4465 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4466 rel.r_info = ELF32_R_INFO (0,
4467 template_sequence[stub_reloc_idx[i]].r_type);
4468 rel.r_addend = 0;
4469
4470 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4471 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4472 template should refer back to the instruction after the original
4473 branch. We use target_section as Cortex-A8 erratum workaround stubs
4474 are only generated when both source and target are in the same
4475 section. */
4476 points_to = stub_entry->target_section->output_section->vma
4477 + stub_entry->target_section->output_offset
4478 + stub_entry->source_value;
4479
4480 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4481 (template_sequence[stub_reloc_idx[i]].r_type),
4482 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
4483 points_to, info, stub_entry->target_section, "", STT_FUNC,
4484 stub_entry->branch_type,
4485 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4486 &error_message);
4487 }
906e58ca
NC		 4488
4489 return TRUE;
48229727 4490#undef MAXRELOCS
906e58ca
NC		 4491}
4492
48229727
JB		 4493/* Calculate the template, template size and instruction size for a stub.
4494 Return value is the instruction size. */
906e58ca 4495
48229727
JB		 4496static unsigned int
4497find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4498 const insn_sequence **stub_template,
4499 int *stub_template_size)
906e58ca 4500{
d3ce72d0 4501 const insn_sequence *template_sequence = NULL;
48229727
JB		 4502 int template_size = 0, i;
4503 unsigned int size;
906e58ca 4504
d3ce72d0 4505 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4506 if (stub_template)
4507 *stub_template = template_sequence;
4508
48229727 4509 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4510 if (stub_template_size)
4511 *stub_template_size = template_size;
906e58ca
NC		 4512
4513 size = 0;
461a49ca
DJ		 4514 for (i = 0; i < template_size; i++)
4515 {
d3ce72d0 4516 switch (template_sequence[i].type)
461a49ca
DJ		 4517 {
4518 case THUMB16_TYPE:
4519 size += 2;
4520 break;
4521
4522 case ARM_TYPE:
48229727 4523 case THUMB32_TYPE:
461a49ca
DJ		 4524 case DATA_TYPE:
4525 size += 4;
4526 break;
4527
4528 default:
4529 BFD_FAIL ();
2a229407 4530 return 0;
461a49ca
DJ		 4531 }
4532 }
4533
48229727
JB		 4534 return size;
4535}
4536
4537/* As above, but don't actually build the stub. Just bump offset so
4538 we know stub section sizes. */
4539
4540static bfd_boolean
4541arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4542 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4543{
4544 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4545 const insn_sequence *template_sequence;
48229727
JB		 4546 int template_size, size;
4547
4548 /* Massage our args to the form they really have. */
4549 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4550
4551 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4552 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4553
d3ce72d0 4554 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4555 &template_size);
4556
461a49ca 4557 stub_entry->stub_size = size;
d3ce72d0 4558 stub_entry->stub_template = template_sequence;
461a49ca
DJ		 4559 stub_entry->stub_template_size = template_size;
4560
906e58ca
NC		 4561 size = (size + 7) & ~7;
4562 stub_entry->stub_sec->size += size;
461a49ca 4563
906e58ca
NC		 4564 return TRUE;
4565}
4566
4567/* External entry points for sizing and building linker stubs. */
4568
4569/* Set up various things so that we can make a list of input sections
4570 for each output section included in the link. Returns -1 on error,
4571 0 when no stubs will be needed, and 1 on success. */
4572
4573int
4574elf32_arm_setup_section_lists (bfd *output_bfd,
4575 struct bfd_link_info *info)
4576{
4577 bfd *input_bfd;
4578 unsigned int bfd_count;
7292b3ac 4579 unsigned int top_id, top_index;
906e58ca
NC		 4580 asection *section;
4581 asection **input_list, **list;
4582 bfd_size_type amt;
4583 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4584
4dfe6ac6
NC		 4585 if (htab == NULL)
4586 return 0;
906e58ca
NC		 4587 if (! is_elf_hash_table (htab))
4588 return 0;
4589
4590 /* Count the number of input BFDs and find the top input section id. */
4591 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
4592 input_bfd != NULL;
c72f2fb2 4593 input_bfd = input_bfd->link.next)
906e58ca
NC		 4594 {
4595 bfd_count += 1;
4596 for (section = input_bfd->sections;
4597 section != NULL;
4598 section = section->next)
4599 {
4600 if (top_id < section->id)
4601 top_id = section->id;
4602 }
4603 }
4604 htab->bfd_count = bfd_count;
4605
4606 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 4607 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 4608 if (htab->stub_group == NULL)
4609 return -1;
fe33d2fa 4610 htab->top_id = top_id;
906e58ca
NC		 4611
4612 /* We can't use output_bfd->section_count here to find the top output
4613 section index as some sections may have been removed, and
4614 _bfd_strip_section_from_output doesn't renumber the indices. */
4615 for (section = output_bfd->sections, top_index = 0;
4616 section != NULL;
4617 section = section->next)
4618 {
4619 if (top_index < section->index)
4620 top_index = section->index;
4621 }
4622
4623 htab->top_index = top_index;
4624 amt = sizeof (asection *) * (top_index + 1);
21d799b5 4625 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 4626 htab->input_list = input_list;
4627 if (input_list == NULL)
4628 return -1;
4629
4630 /* For sections we aren't interested in, mark their entries with a
4631 value we can check later. */
4632 list = input_list + top_index;
4633 do
4634 *list = bfd_abs_section_ptr;
4635 while (list-- != input_list);
4636
4637 for (section = output_bfd->sections;
4638 section != NULL;
4639 section = section->next)
4640 {
4641 if ((section->flags & SEC_CODE) != 0)
4642 input_list[section->index] = NULL;
4643 }
4644
4645 return 1;
4646}
4647
4648/* The linker repeatedly calls this function for each input section,
4649 in the order that input sections are linked into output sections.
4650 Build lists of input sections to determine groupings between which
4651 we may insert linker stubs. */
4652
4653void
4654elf32_arm_next_input_section (struct bfd_link_info *info,
4655 asection *isec)
4656{
4657 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4658
4dfe6ac6
NC		 4659 if (htab == NULL)
4660 return;
4661
906e58ca
NC		 4662 if (isec->output_section->index <= htab->top_index)
4663 {
4664 asection **list = htab->input_list + isec->output_section->index;
4665
a7470592 4666 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 4667 {
4668 /* Steal the link_sec pointer for our list. */
4669#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
4670 /* This happens to make the list in reverse order,
07d72278 4671 which we reverse later. */
906e58ca
NC		 4672 PREV_SEC (isec) = *list;
4673 *list = isec;
4674 }
4675 }
4676}
4677
4678/* See whether we can group stub sections together. Grouping stub
4679 sections may result in fewer stubs. More importantly, we need to
07d72278 4680 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 4681 .fini output sections respectively, because glibc splits the
4682 _init and _fini functions into multiple parts. Putting a stub in
4683 the middle of a function is not a good idea. */
4684
4685static void
4686group_sections (struct elf32_arm_link_hash_table *htab,
4687 bfd_size_type stub_group_size,
07d72278 4688 bfd_boolean stubs_always_after_branch)
906e58ca 4689{
07d72278 4690 asection **list = htab->input_list;
906e58ca
NC		 4691
4692 do
4693 {
4694 asection *tail = *list;
07d72278 4695 asection *head;
906e58ca
NC		 4696
4697 if (tail == bfd_abs_section_ptr)
4698 continue;
4699
07d72278
DJ		 4700 /* Reverse the list: we must avoid placing stubs at the
4701 beginning of the section because the beginning of the text
4702 section may be required for an interrupt vector in bare metal
4703 code. */
4704#define NEXT_SEC PREV_SEC
e780aef2
CL		 4705 head = NULL;
4706 while (tail != NULL)
99059e56
RM		 4707 {
4708 /* Pop from tail. */
4709 asection *item = tail;
4710 tail = PREV_SEC (item);
e780aef2 4711
99059e56
RM		 4712 /* Push on head. */
4713 NEXT_SEC (item) = head;
4714 head = item;
4715 }
07d72278
DJ		 4716
4717 while (head != NULL)
906e58ca
NC		 4718 {
4719 asection *curr;
07d72278 4720 asection *next;
e780aef2
CL		 4721 bfd_vma stub_group_start = head->output_offset;
4722 bfd_vma end_of_next;
906e58ca 4723
07d72278 4724 curr = head;
e780aef2 4725 while (NEXT_SEC (curr) != NULL)
8cd931b7 4726 {
e780aef2
CL		 4727 next = NEXT_SEC (curr);
4728 end_of_next = next->output_offset + next->size;
4729 if (end_of_next - stub_group_start >= stub_group_size)
4730 /* End of NEXT is too far from start, so stop. */
8cd931b7 4731 break;
e780aef2
CL		 4732 /* Add NEXT to the group. */
4733 curr = next;
8cd931b7 4734 }
906e58ca 4735
07d72278 4736 /* OK, the size from the start to the start of CURR is less
906e58ca 4737 than stub_group_size and thus can be handled by one stub
07d72278 4738 section. (Or the head section is itself larger than
906e58ca
NC		 4739 stub_group_size, in which case we may be toast.)
4740 We should really be keeping track of the total size of
4741 stubs added here, as stubs contribute to the final output
7fb9f789 4742 section size. */
906e58ca
NC		 4743 do
4744 {
07d72278 4745 next = NEXT_SEC (head);
906e58ca 4746 /* Set up this stub group. */
07d72278 4747 htab->stub_group[head->id].link_sec = curr;
906e58ca 4748 }
07d72278 4749 while (head != curr && (head = next) != NULL);
906e58ca
NC		 4750
4751 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 4752 bytes after the stub section can be handled by it too. */
4753 if (!stubs_always_after_branch)
906e58ca 4754 {
e780aef2
CL		 4755 stub_group_start = curr->output_offset + curr->size;
4756
8cd931b7 4757 while (next != NULL)
906e58ca 4758 {
e780aef2
CL		 4759 end_of_next = next->output_offset + next->size;
4760 if (end_of_next - stub_group_start >= stub_group_size)
4761 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 4762 break;
e780aef2 4763 /* Add NEXT to the stub group. */
07d72278
DJ		 4764 head = next;
4765 next = NEXT_SEC (head);
4766 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 4767 }
4768 }
07d72278 4769 head = next;
906e58ca
NC		 4770 }
4771 }
07d72278 4772 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 4773
4774 free (htab->input_list);
4775#undef PREV_SEC
07d72278 4776#undef NEXT_SEC
906e58ca
NC		 4777}
4778
48229727
JB		 4779/* Comparison function for sorting/searching relocations relating to Cortex-A8
4780 erratum fix. */
4781
4782static int
4783a8_reloc_compare (const void *a, const void *b)
4784{
21d799b5
NC		 4785 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
4786 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 4787
4788 if (ra->from < rb->from)
4789 return -1;
4790 else if (ra->from > rb->from)
4791 return 1;
4792 else
4793 return 0;
4794}
4795
4796static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
4797 const char *, char **);
4798
4799/* Helper function to scan code for sequences which might trigger the Cortex-A8
4800 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 4801 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 4802 otherwise. */
4803
81694485
NC		 4804static bfd_boolean
4805cortex_a8_erratum_scan (bfd *input_bfd,
4806 struct bfd_link_info *info,
48229727
JB		 4807 struct a8_erratum_fix **a8_fixes_p,
4808 unsigned int *num_a8_fixes_p,
4809 unsigned int *a8_fix_table_size_p,
4810 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 4811 unsigned int num_a8_relocs,
4812 unsigned prev_num_a8_fixes,
4813 bfd_boolean *stub_changed_p)
48229727
JB		 4814{
4815 asection *section;
4816 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4817 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
4818 unsigned int num_a8_fixes = *num_a8_fixes_p;
4819 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
4820
4dfe6ac6
NC		 4821 if (htab == NULL)
4822 return FALSE;
4823
48229727
JB		 4824 for (section = input_bfd->sections;
4825 section != NULL;
4826 section = section->next)
4827 {
4828 bfd_byte *contents = NULL;
4829 struct _arm_elf_section_data *sec_data;
4830 unsigned int span;
4831 bfd_vma base_vma;
4832
4833 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 4834 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
4835 || (section->flags & SEC_EXCLUDE) != 0
4836 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
4837 || (section->output_section == bfd_abs_section_ptr))
4838 continue;
48229727
JB		 4839
4840 base_vma = section->output_section->vma + section->output_offset;
4841
4842 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 4843 contents = elf_section_data (section)->this_hdr.contents;
48229727 4844 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 4845 return TRUE;
48229727
JB		 4846
4847 sec_data = elf32_arm_section_data (section);
4848
4849 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 4850 {
4851 unsigned int span_start = sec_data->map[span].vma;
4852 unsigned int span_end = (span == sec_data->mapcount - 1)
4853 ? section->size : sec_data->map[span + 1].vma;
4854 unsigned int i;
4855 char span_type = sec_data->map[span].type;
4856 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
4857
4858 if (span_type != 't')
4859 continue;
4860
4861 /* Span is entirely within a single 4KB region: skip scanning. */
4862 if (((base_vma + span_start) & ~0xfff)
48229727 4863 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 4864 continue;
4865
4866 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
4867
4868 * The opcode is BLX.W, BL.W, B.W, Bcc.W
4869 * The branch target is in the same 4KB region as the
4870 first half of the branch.
4871 * The instruction before the branch is a 32-bit
4872 length non-branch instruction. */
4873 for (i = span_start; i < span_end;)
4874 {
4875 unsigned int insn = bfd_getl16 (&contents[i]);
4876 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 4877 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
4878
99059e56
RM		 4879 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
4880 insn_32bit = TRUE;
48229727
JB		 4881
4882 if (insn_32bit)
99059e56
RM		 4883 {
4884 /* Load the rest of the insn (in manual-friendly order). */
4885 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
4886
4887 /* Encoding T4: B<c>.W. */
4888 is_b = (insn & 0xf800d000) == 0xf0009000;
4889 /* Encoding T1: BL<c>.W. */
4890 is_bl = (insn & 0xf800d000) == 0xf000d000;
4891 /* Encoding T2: BLX<c>.W. */
4892 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 4893 /* Encoding T3: B<c>.W (not permitted in IT block). */
4894 is_bcc = (insn & 0xf800d000) == 0xf0008000
4895 && (insn & 0x07f00000) != 0x03800000;
4896 }
4897
4898 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 4899
99059e56 4900 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 4901 && insn_32bit
4902 && is_32bit_branch
4903 && last_was_32bit
4904 && ! last_was_branch)
99059e56
RM		 4905 {
4906 bfd_signed_vma offset = 0;
4907 bfd_boolean force_target_arm = FALSE;
48229727 4908 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 4909 bfd_vma target;
4910 enum elf32_arm_stub_type stub_type = arm_stub_none;
4911 struct a8_erratum_reloc key, *found;
4912 bfd_boolean use_plt = FALSE;
48229727 4913
99059e56
RM		 4914 key.from = base_vma + i;
4915 found = (struct a8_erratum_reloc *)
4916 bsearch (&key, a8_relocs, num_a8_relocs,
4917 sizeof (struct a8_erratum_reloc),
4918 &a8_reloc_compare);
48229727
JB		 4919
4920 if (found)
4921 {
4922 char *error_message = NULL;
4923 struct elf_link_hash_entry *entry;
4924
4925 /* We don't care about the error returned from this
99059e56 4926 function, only if there is glue or not. */
48229727
JB		 4927 entry = find_thumb_glue (info, found->sym_name,
4928 &error_message);
4929
4930 if (entry)
4931 found->non_a8_stub = TRUE;
4932
92750f34 4933 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 4934 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 4935 && found->hash->root.plt.offset != (bfd_vma) -1)
4936 use_plt = TRUE;
4937
4938 if (found->r_type == R_ARM_THM_CALL)
4939 {
35fc36a8
RS		 4940 if (found->branch_type == ST_BRANCH_TO_ARM
4941 || use_plt)
92750f34
DJ		 4942 force_target_arm = TRUE;
4943 else
4944 force_target_thumb = TRUE;
4945 }
48229727
JB		 4946 }
4947
99059e56 4948 /* Check if we have an offending branch instruction. */
48229727
JB		 4949
4950 if (found && found->non_a8_stub)
4951 /* We've already made a stub for this instruction, e.g.
4952 it's a long branch or a Thumb->ARM stub. Assume that
4953 stub will suffice to work around the A8 erratum (see
4954 setting of always_after_branch above). */
4955 ;
99059e56
RM		 4956 else if (is_bcc)
4957 {
4958 offset = (insn & 0x7ff) << 1;
4959 offset |= (insn & 0x3f0000) >> 4;
4960 offset |= (insn & 0x2000) ? 0x40000 : 0;
4961 offset |= (insn & 0x800) ? 0x80000 : 0;
4962 offset |= (insn & 0x4000000) ? 0x100000 : 0;
4963 if (offset & 0x100000)
4964 offset |= ~ ((bfd_signed_vma) 0xfffff);
4965 stub_type = arm_stub_a8_veneer_b_cond;
4966 }
4967 else if (is_b || is_bl || is_blx)
4968 {
4969 int s = (insn & 0x4000000) != 0;
4970 int j1 = (insn & 0x2000) != 0;
4971 int j2 = (insn & 0x800) != 0;
4972 int i1 = !(j1 ^ s);
4973 int i2 = !(j2 ^ s);
4974
4975 offset = (insn & 0x7ff) << 1;
4976 offset |= (insn & 0x3ff0000) >> 4;
4977 offset |= i2 << 22;
4978 offset |= i1 << 23;
4979 offset |= s << 24;
4980 if (offset & 0x1000000)
4981 offset |= ~ ((bfd_signed_vma) 0xffffff);
4982
4983 if (is_blx)
4984 offset &= ~ ((bfd_signed_vma) 3);
4985
4986 stub_type = is_blx ? arm_stub_a8_veneer_blx :
4987 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
4988 }
4989
4990 if (stub_type != arm_stub_none)
4991 {
4992 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 4993
4994 /* The original instruction is a BL, but the target is
99059e56 4995 an ARM instruction. If we were not making a stub,
48229727
JB		 4996 the BL would have been converted to a BLX. Use the
4997 BLX stub instead in that case. */
4998 if (htab->use_blx && force_target_arm
4999 && stub_type == arm_stub_a8_veneer_bl)
5000 {
5001 stub_type = arm_stub_a8_veneer_blx;
5002 is_blx = TRUE;
5003 is_bl = FALSE;
5004 }
5005 /* Conversely, if the original instruction was
5006 BLX but the target is Thumb mode, use the BL
5007 stub. */
5008 else if (force_target_thumb
5009 && stub_type == arm_stub_a8_veneer_blx)
5010 {
5011 stub_type = arm_stub_a8_veneer_bl;
5012 is_blx = FALSE;
5013 is_bl = TRUE;
5014 }
5015
99059e56
RM		 5016 if (is_blx)
5017 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5018
99059e56
RM		 5019 /* If we found a relocation, use the proper destination,
5020 not the offset in the (unrelocated) instruction.
48229727
JB		 5021 Note this is always done if we switched the stub type
5022 above. */
99059e56
RM		 5023 if (found)
5024 offset =
81694485 5025 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5026
99059e56
RM		 5027 /* If the stub will use a Thumb-mode branch to a
5028 PLT target, redirect it to the preceding Thumb
5029 entry point. */
5030 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5031 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5032
99059e56 5033 target = pc_for_insn + offset;
48229727 5034
99059e56
RM		 5035 /* The BLX stub is ARM-mode code. Adjust the offset to
5036 take the different PC value (+8 instead of +4) into
48229727 5037 account. */
99059e56
RM		 5038 if (stub_type == arm_stub_a8_veneer_blx)
5039 offset += 4;
5040
5041 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5042 {
5043 char *stub_name = NULL;
5044
5045 if (num_a8_fixes == a8_fix_table_size)
5046 {
5047 a8_fix_table_size *= 2;
5048 a8_fixes = (struct a8_erratum_fix *)
5049 bfd_realloc (a8_fixes,
5050 sizeof (struct a8_erratum_fix)
5051 * a8_fix_table_size);
5052 }
48229727 5053
eb7c4339
NS		 5054 if (num_a8_fixes < prev_num_a8_fixes)
5055 {
5056 /* If we're doing a subsequent scan,
5057 check if we've found the same fix as
5058 before, and try and reuse the stub
5059 name. */
5060 stub_name = a8_fixes[num_a8_fixes].stub_name;
5061 if ((a8_fixes[num_a8_fixes].section != section)
5062 || (a8_fixes[num_a8_fixes].offset != i))
5063 {
5064 free (stub_name);
5065 stub_name = NULL;
5066 *stub_changed_p = TRUE;
5067 }
5068 }
5069
5070 if (!stub_name)
5071 {
21d799b5 5072 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5073 if (stub_name != NULL)
5074 sprintf (stub_name, "%x:%x", section->id, i);
5075 }
48229727 5076
99059e56
RM		 5077 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5078 a8_fixes[num_a8_fixes].section = section;
5079 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5080 a8_fixes[num_a8_fixes].target_offset =
5081 target - base_vma;
99059e56
RM		 5082 a8_fixes[num_a8_fixes].orig_insn = insn;
5083 a8_fixes[num_a8_fixes].stub_name = stub_name;
5084 a8_fixes[num_a8_fixes].stub_type = stub_type;
5085 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5086 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5087
99059e56
RM		 5088 num_a8_fixes++;
5089 }
5090 }
5091 }
48229727 5092
99059e56
RM		 5093 i += insn_32bit ? 4 : 2;
5094 last_was_32bit = insn_32bit;
48229727 5095 last_was_branch = is_32bit_branch;
99059e56
RM		 5096 }
5097 }
48229727
JB		 5098
5099 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5100 free (contents);
48229727 5101 }
fe33d2fa 5102
48229727
JB		 5103 *a8_fixes_p = a8_fixes;
5104 *num_a8_fixes_p = num_a8_fixes;
5105 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5106
81694485 5107 return FALSE;
48229727
JB		 5108}
5109
b715f643
TP		 5110/* Create or update a stub entry depending on whether the stub can already be
5111 found in HTAB. The stub is identified by:
5112 - its type STUB_TYPE
5113 - its source branch (note that several can share the same stub) whose
5114 section and relocation (if any) are given by SECTION and IRELA
5115 respectively
5116 - its target symbol whose input section, hash, name, value and branch type
5117 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5118 respectively
5119
5120 If found, the value of the stub's target symbol is updated from SYM_VALUE
5121 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5122 TRUE and the stub entry is initialized.
5123
5124 Returns whether the stub could be successfully created or updated, or FALSE
5125 if an error occured. */
5126
5127static bfd_boolean
5128elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5129 enum elf32_arm_stub_type stub_type, asection *section,
5130 Elf_Internal_Rela *irela, asection *sym_sec,
5131 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5132 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5133 bfd_boolean *new_stub)
5134{
5135 const asection *id_sec;
5136 char *stub_name;
5137 struct elf32_arm_stub_hash_entry *stub_entry;
5138 unsigned int r_type;
5139
5140 BFD_ASSERT (stub_type != arm_stub_none);
5141 *new_stub = FALSE;
5142
5143 BFD_ASSERT (irela);
5144 BFD_ASSERT (section);
5145
5146 /* Support for grouping stub sections. */
5147 id_sec = htab->stub_group[section->id].link_sec;
5148
5149 /* Get the name of this stub. */
5150 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela, stub_type);
5151 if (!stub_name)
5152 return FALSE;
5153
5154 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5155 FALSE);
5156 /* The proper stub has already been created, just update its value. */
5157 if (stub_entry != NULL)
5158 {
5159 free (stub_name);
5160 stub_entry->target_value = sym_value;
5161 return TRUE;
5162 }
5163
5164 stub_entry = elf32_arm_add_stub (stub_name, section, htab);
5165 if (stub_entry == NULL)
5166 {
5167 free (stub_name);
5168 return FALSE;
5169 }
5170
5171 stub_entry->target_value = sym_value;
5172 stub_entry->target_section = sym_sec;
5173 stub_entry->stub_type = stub_type;
5174 stub_entry->h = hash;
5175 stub_entry->branch_type = branch_type;
5176
5177 if (sym_name == NULL)
5178 sym_name = "unnamed";
5179 stub_entry->output_name = (char *)
5180 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5181 + strlen (sym_name));
5182 if (stub_entry->output_name == NULL)
5183 {
5184 free (stub_name);
5185 return FALSE;
5186 }
5187
5188 /* For historical reasons, use the existing names for ARM-to-Thumb and
5189 Thumb-to-ARM stubs. */
5190 r_type = ELF32_R_TYPE (irela->r_info);
5191 if ((r_type == (unsigned int) R_ARM_THM_CALL
5192 || r_type == (unsigned int) R_ARM_THM_JUMP24
5193 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5194 && branch_type == ST_BRANCH_TO_ARM)
5195 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5196 else if ((r_type == (unsigned int) R_ARM_CALL
5197 || r_type == (unsigned int) R_ARM_JUMP24)
5198 && branch_type == ST_BRANCH_TO_THUMB)
5199 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5200 else
5201 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5202
5203 *new_stub = TRUE;
5204 return TRUE;
5205}
5206
906e58ca
NC		 5207/* Determine and set the size of the stub section for a final link.
5208
5209 The basic idea here is to examine all the relocations looking for
5210 PC-relative calls to a target that is unreachable with a "bl"
5211 instruction. */
5212
5213bfd_boolean
5214elf32_arm_size_stubs (bfd *output_bfd,
5215 bfd *stub_bfd,
5216 struct bfd_link_info *info,
5217 bfd_signed_vma group_size,
7a89b94e
NC		 5218 asection * (*add_stub_section) (const char *, asection *,
5219 unsigned int),
906e58ca
NC		 5220 void (*layout_sections_again) (void))
5221{
5222 bfd_size_type stub_group_size;
07d72278 5223 bfd_boolean stubs_always_after_branch;
906e58ca 5224 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 5225 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 5226 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 5227 struct a8_erratum_reloc *a8_relocs = NULL;
5228 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
5229
4dfe6ac6
NC		 5230 if (htab == NULL)
5231 return FALSE;
5232
48229727
JB		 5233 if (htab->fix_cortex_a8)
5234 {
21d799b5 5235 a8_fixes = (struct a8_erratum_fix *)
99059e56 5236 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 5237 a8_relocs = (struct a8_erratum_reloc *)
99059e56 5238 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 5239 }
906e58ca
NC		 5240
5241 /* Propagate mach to stub bfd, because it may not have been
5242 finalized when we created stub_bfd. */
5243 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
5244 bfd_get_mach (output_bfd));
5245
5246 /* Stash our params away. */
5247 htab->stub_bfd = stub_bfd;
5248 htab->add_stub_section = add_stub_section;
5249 htab->layout_sections_again = layout_sections_again;
07d72278 5250 stubs_always_after_branch = group_size < 0;
48229727
JB		 5251
5252 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
5253 as the first half of a 32-bit branch straddling two 4K pages. This is a
5254 crude way of enforcing that. */
5255 if (htab->fix_cortex_a8)
5256 stubs_always_after_branch = 1;
5257
906e58ca
NC		 5258 if (group_size < 0)
5259 stub_group_size = -group_size;
5260 else
5261 stub_group_size = group_size;
5262
5263 if (stub_group_size == 1)
5264 {
5265 /* Default values. */
5266 /* Thumb branch range is +-4MB has to be used as the default
5267 maximum size (a given section can contain both ARM and Thumb
5268 code, so the worst case has to be taken into account).
5269
5270 This value is 24K less than that, which allows for 2025
5271 12-byte stubs. If we exceed that, then we will fail to link.
5272 The user will have to relink with an explicit group size
5273 option. */
5274 stub_group_size = 4170000;
5275 }
5276
07d72278 5277 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 5278
3ae046cc
NS		 5279 /* If we're applying the cortex A8 fix, we need to determine the
5280 program header size now, because we cannot change it later --
5281 that could alter section placements. Notice the A8 erratum fix
5282 ends up requiring the section addresses to remain unchanged
5283 modulo the page size. That's something we cannot represent
5284 inside BFD, and we don't want to force the section alignment to
5285 be the page size. */
5286 if (htab->fix_cortex_a8)
5287 (*htab->layout_sections_again) ();
5288
906e58ca
NC		 5289 while (1)
5290 {
5291 bfd *input_bfd;
5292 unsigned int bfd_indx;
5293 asection *stub_sec;
eb7c4339
NS		 5294 bfd_boolean stub_changed = FALSE;
5295 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 5296
48229727 5297 num_a8_fixes = 0;
906e58ca
NC		 5298 for (input_bfd = info->input_bfds, bfd_indx = 0;
5299 input_bfd != NULL;
c72f2fb2 5300 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 5301 {
5302 Elf_Internal_Shdr *symtab_hdr;
5303 asection *section;
5304 Elf_Internal_Sym *local_syms = NULL;
5305
99059e56
RM		 5306 if (!is_arm_elf (input_bfd))
5307 continue;
adbcc655 5308
48229727
JB		 5309 num_a8_relocs = 0;
5310
906e58ca
NC		 5311 /* We'll need the symbol table in a second. */
5312 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5313 if (symtab_hdr->sh_info == 0)
5314 continue;
5315
5316 /* Walk over each section attached to the input bfd. */
5317 for (section = input_bfd->sections;
5318 section != NULL;
5319 section = section->next)
5320 {
5321 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
5322
5323 /* If there aren't any relocs, then there's nothing more
5324 to do. */
5325 if ((section->flags & SEC_RELOC) == 0
5326 || section->reloc_count == 0
5327 || (section->flags & SEC_CODE) == 0)
5328 continue;
5329
5330 /* If this section is a link-once section that will be
5331 discarded, then don't create any stubs. */
5332 if (section->output_section == NULL
5333 || section->output_section->owner != output_bfd)
5334 continue;
5335
5336 /* Get the relocs. */
5337 internal_relocs
5338 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
5339 NULL, info->keep_memory);
5340 if (internal_relocs == NULL)
5341 goto error_ret_free_local;
5342
5343 /* Now examine each relocation. */
5344 irela = internal_relocs;
5345 irelaend = irela + section->reloc_count;
5346 for (; irela < irelaend; irela++)
5347 {
5348 unsigned int r_type, r_indx;
5349 enum elf32_arm_stub_type stub_type;
906e58ca
NC		 5350 asection *sym_sec;
5351 bfd_vma sym_value;
5352 bfd_vma destination;
5353 struct elf32_arm_link_hash_entry *hash;
7413f23f 5354 const char *sym_name;
34e77a92 5355 unsigned char st_type;
35fc36a8 5356 enum arm_st_branch_type branch_type;
48229727 5357 bfd_boolean created_stub = FALSE;
906e58ca
NC		 5358
5359 r_type = ELF32_R_TYPE (irela->r_info);
5360 r_indx = ELF32_R_SYM (irela->r_info);
5361
5362 if (r_type >= (unsigned int) R_ARM_max)
5363 {
5364 bfd_set_error (bfd_error_bad_value);
5365 error_ret_free_internal:
5366 if (elf_section_data (section)->relocs == NULL)
5367 free (internal_relocs);
15dd01b1
TP		 5368 /* Fall through. */
5369 error_ret_free_local:
5370 if (local_syms != NULL
5371 && (symtab_hdr->contents
5372 != (unsigned char *) local_syms))
5373 free (local_syms);
5374 return FALSE;
906e58ca 5375 }
b38cadfb 5376
0855e32b
NS		 5377 hash = NULL;
5378 if (r_indx >= symtab_hdr->sh_info)
5379 hash = elf32_arm_hash_entry
5380 (elf_sym_hashes (input_bfd)
5381 [r_indx - symtab_hdr->sh_info]);
b38cadfb 5382
0855e32b
NS		 5383 /* Only look for stubs on branch instructions, or
5384 non-relaxed TLSCALL */
906e58ca 5385 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 5386 && (r_type != (unsigned int) R_ARM_THM_CALL)
5387 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 5388 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
5389 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 5390 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 5391 && (r_type != (unsigned int) R_ARM_PLT32)
5392 && !((r_type == (unsigned int) R_ARM_TLS_CALL
5393 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
5394 && r_type == elf32_arm_tls_transition
5395 (info, r_type, &hash->root)
5396 && ((hash ? hash->tls_type
5397 : (elf32_arm_local_got_tls_type
5398 (input_bfd)[r_indx]))
5399 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 5400 continue;
5401
5402 /* Now determine the call target, its name, value,
5403 section. */
5404 sym_sec = NULL;
5405 sym_value = 0;
5406 destination = 0;
7413f23f 5407 sym_name = NULL;
b38cadfb 5408
0855e32b
NS		 5409 if (r_type == (unsigned int) R_ARM_TLS_CALL
5410 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
5411 {
5412 /* A non-relaxed TLS call. The target is the
5413 plt-resident trampoline and nothing to do
5414 with the symbol. */
5415 BFD_ASSERT (htab->tls_trampoline > 0);
5416 sym_sec = htab->root.splt;
5417 sym_value = htab->tls_trampoline;
5418 hash = 0;
34e77a92 5419 st_type = STT_FUNC;
35fc36a8 5420 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 5421 }
5422 else if (!hash)
906e58ca
NC		 5423 {
5424 /* It's a local symbol. */
5425 Elf_Internal_Sym *sym;
906e58ca
NC		 5426
5427 if (local_syms == NULL)
5428 {
5429 local_syms
5430 = (Elf_Internal_Sym *) symtab_hdr->contents;
5431 if (local_syms == NULL)
5432 local_syms
5433 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5434 symtab_hdr->sh_info, 0,
5435 NULL, NULL, NULL);
5436 if (local_syms == NULL)
5437 goto error_ret_free_internal;
5438 }
5439
5440 sym = local_syms + r_indx;
f6d250ce
TS		 5441 if (sym->st_shndx == SHN_UNDEF)
5442 sym_sec = bfd_und_section_ptr;
5443 else if (sym->st_shndx == SHN_ABS)
5444 sym_sec = bfd_abs_section_ptr;
5445 else if (sym->st_shndx == SHN_COMMON)
5446 sym_sec = bfd_com_section_ptr;
5447 else
5448 sym_sec =
5449 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
5450
ffcb4889
NS		 5451 if (!sym_sec)
5452 /* This is an undefined symbol. It can never
6a631e86 5453 be resolved. */
ffcb4889 5454 continue;
fe33d2fa 5455
906e58ca
NC		 5456 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
5457 sym_value = sym->st_value;
5458 destination = (sym_value + irela->r_addend
5459 + sym_sec->output_offset
5460 + sym_sec->output_section->vma);
34e77a92 5461 st_type = ELF_ST_TYPE (sym->st_info);
35fc36a8 5462 branch_type = ARM_SYM_BRANCH_TYPE (sym);
7413f23f
DJ		 5463 sym_name
5464 = bfd_elf_string_from_elf_section (input_bfd,
5465 symtab_hdr->sh_link,
5466 sym->st_name);
906e58ca
NC		 5467 }
5468 else
5469 {
5470 /* It's an external symbol. */
906e58ca
NC		 5471 while (hash->root.root.type == bfd_link_hash_indirect
5472 || hash->root.root.type == bfd_link_hash_warning)
5473 hash = ((struct elf32_arm_link_hash_entry *)
5474 hash->root.root.u.i.link);
5475
5476 if (hash->root.root.type == bfd_link_hash_defined
5477 || hash->root.root.type == bfd_link_hash_defweak)
5478 {
5479 sym_sec = hash->root.root.u.def.section;
5480 sym_value = hash->root.root.u.def.value;
022f8312
CL		 5481
5482 struct elf32_arm_link_hash_table *globals =
5483 elf32_arm_hash_table (info);
5484
5485 /* For a destination in a shared library,
5486 use the PLT stub as target address to
5487 decide whether a branch stub is
5488 needed. */
4dfe6ac6 5489 if (globals != NULL
362d30a1 5490 && globals->root.splt != NULL
4dfe6ac6 5491 && hash != NULL
022f8312
CL		 5492 && hash->root.plt.offset != (bfd_vma) -1)
5493 {
362d30a1 5494 sym_sec = globals->root.splt;
022f8312
CL		 5495 sym_value = hash->root.plt.offset;
5496 if (sym_sec->output_section != NULL)
5497 destination = (sym_value
5498 + sym_sec->output_offset
5499 + sym_sec->output_section->vma);
5500 }
5501 else if (sym_sec->output_section != NULL)
906e58ca
NC		 5502 destination = (sym_value + irela->r_addend
5503 + sym_sec->output_offset
5504 + sym_sec->output_section->vma);
5505 }
69c5861e
CL		 5506 else if ((hash->root.root.type == bfd_link_hash_undefined)
5507 || (hash->root.root.type == bfd_link_hash_undefweak))
5508 {
5509 /* For a shared library, use the PLT stub as
5510 target address to decide whether a long
5511 branch stub is needed.
5512 For absolute code, they cannot be handled. */
5513 struct elf32_arm_link_hash_table *globals =
5514 elf32_arm_hash_table (info);
5515
4dfe6ac6 5516 if (globals != NULL
362d30a1 5517 && globals->root.splt != NULL
4dfe6ac6 5518 && hash != NULL
69c5861e
CL		 5519 && hash->root.plt.offset != (bfd_vma) -1)
5520 {
362d30a1 5521 sym_sec = globals->root.splt;
69c5861e
CL		 5522 sym_value = hash->root.plt.offset;
5523 if (sym_sec->output_section != NULL)
5524 destination = (sym_value
5525 + sym_sec->output_offset
5526 + sym_sec->output_section->vma);
5527 }
5528 else
5529 continue;
5530 }
906e58ca
NC		 5531 else
5532 {
5533 bfd_set_error (bfd_error_bad_value);
5534 goto error_ret_free_internal;
5535 }
34e77a92 5536 st_type = hash->root.type;
35fc36a8 5537 branch_type = hash->root.target_internal;
7413f23f 5538 sym_name = hash->root.root.root.string;
906e58ca
NC		 5539 }
5540
48229727 5541 do
7413f23f 5542 {
b715f643
TP		 5543 bfd_boolean new_stub;
5544
48229727
JB		 5545 /* Determine what (if any) linker stub is needed. */
5546 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 5547 st_type, &branch_type,
5548 hash, destination, sym_sec,
48229727
JB		 5549 input_bfd, sym_name);
5550 if (stub_type == arm_stub_none)
5551 break;
5552
48229727
JB		 5553 /* We've either created a stub for this reloc already,
5554 or we are about to. */
b715f643
TP		 5555 created_stub =
5556 elf32_arm_create_stub (htab, stub_type, section, irela,
5557 sym_sec, hash,
5558 (char *) sym_name, sym_value,
5559 branch_type, &new_stub);
7413f23f 5560
b715f643
TP		 5561 if (!created_stub)
5562 goto error_ret_free_internal;
5563 else if (!new_stub)
5564 break;
99059e56 5565 else
b715f643 5566 stub_changed = TRUE;
99059e56
RM		 5567 }
5568 while (0);
5569
5570 /* Look for relocations which might trigger Cortex-A8
5571 erratum. */
5572 if (htab->fix_cortex_a8
5573 && (r_type == (unsigned int) R_ARM_THM_JUMP24
5574 || r_type == (unsigned int) R_ARM_THM_JUMP19
5575 || r_type == (unsigned int) R_ARM_THM_CALL
5576 || r_type == (unsigned int) R_ARM_THM_XPC22))
5577 {
5578 bfd_vma from = section->output_section->vma
5579 + section->output_offset
5580 + irela->r_offset;
5581
5582 if ((from & 0xfff) == 0xffe)
5583 {
5584 /* Found a candidate. Note we haven't checked the
5585 destination is within 4K here: if we do so (and
5586 don't create an entry in a8_relocs) we can't tell
5587 that a branch should have been relocated when
5588 scanning later. */
5589 if (num_a8_relocs == a8_reloc_table_size)
5590 {
5591 a8_reloc_table_size *= 2;
5592 a8_relocs = (struct a8_erratum_reloc *)
5593 bfd_realloc (a8_relocs,
5594 sizeof (struct a8_erratum_reloc)
5595 * a8_reloc_table_size);
5596 }
5597
5598 a8_relocs[num_a8_relocs].from = from;
5599 a8_relocs[num_a8_relocs].destination = destination;
5600 a8_relocs[num_a8_relocs].r_type = r_type;
5601 a8_relocs[num_a8_relocs].branch_type = branch_type;
5602 a8_relocs[num_a8_relocs].sym_name = sym_name;
5603 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
5604 a8_relocs[num_a8_relocs].hash = hash;
5605
5606 num_a8_relocs++;
5607 }
5608 }
906e58ca
NC		 5609 }
5610
99059e56
RM		 5611 /* We're done with the internal relocs, free them. */
5612 if (elf_section_data (section)->relocs == NULL)
5613 free (internal_relocs);
5614 }
48229727 5615
99059e56 5616 if (htab->fix_cortex_a8)
48229727 5617 {
99059e56
RM		 5618 /* Sort relocs which might apply to Cortex-A8 erratum. */
5619 qsort (a8_relocs, num_a8_relocs,
eb7c4339 5620 sizeof (struct a8_erratum_reloc),
99059e56 5621 &a8_reloc_compare);
48229727 5622
99059e56
RM		 5623 /* Scan for branches which might trigger Cortex-A8 erratum. */
5624 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 5625 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 5626 a8_relocs, num_a8_relocs,
5627 prev_num_a8_fixes, &stub_changed)
5628 != 0)
48229727 5629 goto error_ret_free_local;
5e681ec4 5630 }
5e681ec4
PB		 5631 }
5632
eb7c4339 5633 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 5634 stub_changed = TRUE;
48229727 5635
906e58ca
NC		 5636 if (!stub_changed)
5637 break;
5e681ec4 5638
906e58ca
NC		 5639 /* OK, we've added some stubs. Find out the new size of the
5640 stub sections. */
5641 for (stub_sec = htab->stub_bfd->sections;
5642 stub_sec != NULL;
5643 stub_sec = stub_sec->next)
3e6b1042
DJ		 5644 {
5645 /* Ignore non-stub sections. */
5646 if (!strstr (stub_sec->name, STUB_SUFFIX))
5647 continue;
5648
5649 stub_sec->size = 0;
5650 }
b34b2d70 5651
906e58ca
NC		 5652 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
5653
48229727
JB		 5654 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
5655 if (htab->fix_cortex_a8)
99059e56
RM		 5656 for (i = 0; i < num_a8_fixes; i++)
5657 {
48229727
JB		 5658 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
5659 a8_fixes[i].section, htab);
5660
5661 if (stub_sec == NULL)
5662 goto error_ret_free_local;
5663
99059e56
RM		 5664 stub_sec->size
5665 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
5666 NULL);
5667 }
48229727
JB		 5668
5669
906e58ca
NC		 5670 /* Ask the linker to do its stuff. */
5671 (*htab->layout_sections_again) ();
ba93b8ac
DJ		 5672 }
5673
48229727
JB		 5674 /* Add stubs for Cortex-A8 erratum fixes now. */
5675 if (htab->fix_cortex_a8)
5676 {
5677 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 5678 {
5679 struct elf32_arm_stub_hash_entry *stub_entry;
5680 char *stub_name = a8_fixes[i].stub_name;
5681 asection *section = a8_fixes[i].section;
5682 unsigned int section_id = a8_fixes[i].section->id;
5683 asection *link_sec = htab->stub_group[section_id].link_sec;
5684 asection *stub_sec = htab->stub_group[section_id].stub_sec;
5685 const insn_sequence *template_sequence;
5686 int template_size, size = 0;
5687
5688 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
5689 TRUE, FALSE);
5690 if (stub_entry == NULL)
5691 {
5692 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
5693 section->owner,
5694 stub_name);
5695 return FALSE;
5696 }
5697
5698 stub_entry->stub_sec = stub_sec;
5699 stub_entry->stub_offset = 0;
5700 stub_entry->id_sec = link_sec;
5701 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 5702 stub_entry->source_value = a8_fixes[i].offset;
99059e56 5703 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 5704 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 5705 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 5706 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 5707
99059e56
RM		 5708 size = find_stub_size_and_template (a8_fixes[i].stub_type,
5709 &template_sequence,
5710 &template_size);
48229727 5711
99059e56
RM		 5712 stub_entry->stub_size = size;
5713 stub_entry->stub_template = template_sequence;
5714 stub_entry->stub_template_size = template_size;
5715 }
48229727
JB		 5716
5717 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 5718 elf32_arm_write_section(). */
48229727
JB		 5719 htab->a8_erratum_fixes = a8_fixes;
5720 htab->num_a8_erratum_fixes = num_a8_fixes;
5721 }
5722 else
5723 {
5724 htab->a8_erratum_fixes = NULL;
5725 htab->num_a8_erratum_fixes = 0;
5726 }
906e58ca 5727 return TRUE;
5e681ec4
PB		 5728}
5729
906e58ca
NC		 5730/* Build all the stubs associated with the current output file. The
5731 stubs are kept in a hash table attached to the main linker hash
5732 table. We also set up the .plt entries for statically linked PIC
5733 functions here. This function is called via arm_elf_finish in the
5734 linker. */
252b5132 5735
906e58ca
NC		 5736bfd_boolean
5737elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 5738{
906e58ca
NC		 5739 asection *stub_sec;
5740 struct bfd_hash_table *table;
5741 struct elf32_arm_link_hash_table *htab;
252b5132 5742
906e58ca 5743 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 5744 if (htab == NULL)
5745 return FALSE;
252b5132 5746
906e58ca
NC		 5747 for (stub_sec = htab->stub_bfd->sections;
5748 stub_sec != NULL;
5749 stub_sec = stub_sec->next)
252b5132 5750 {
906e58ca
NC		 5751 bfd_size_type size;
5752
8029a119 5753 /* Ignore non-stub sections. */
906e58ca
NC		 5754 if (!strstr (stub_sec->name, STUB_SUFFIX))
5755 continue;
5756
5757 /* Allocate memory to hold the linker stubs. */
5758 size = stub_sec->size;
21d799b5 5759 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 5760 if (stub_sec->contents == NULL && size != 0)
5761 return FALSE;
5762 stub_sec->size = 0;
252b5132
RH		 5763 }
5764
906e58ca
NC		 5765 /* Build the stubs as directed by the stub hash table. */
5766 table = &htab->stub_hash_table;
5767 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 5768 if (htab->fix_cortex_a8)
5769 {
5770 /* Place the cortex a8 stubs last. */
5771 htab->fix_cortex_a8 = -1;
5772 bfd_hash_traverse (table, arm_build_one_stub, info);
5773 }
252b5132 5774
906e58ca 5775 return TRUE;
252b5132
RH		 5776}
5777
9b485d32
NC		 5778/* Locate the Thumb encoded calling stub for NAME. */
5779
252b5132 5780static struct elf_link_hash_entry *
57e8b36a
NC		 5781find_thumb_glue (struct bfd_link_info *link_info,
5782 const char *name,
f2a9dd69 5783 char **error_message)
252b5132
RH		 5784{
5785 char *tmp_name;
5786 struct elf_link_hash_entry *hash;
5787 struct elf32_arm_link_hash_table *hash_table;
5788
5789 /* We need a pointer to the armelf specific hash table. */
5790 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 5791 if (hash_table == NULL)
5792 return NULL;
252b5132 5793
21d799b5 5794 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 5795 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 5796
5797 BFD_ASSERT (tmp_name);
5798
5799 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
5800
5801 hash = elf_link_hash_lookup
b34976b6 5802 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 5803
b1657152
AM		 5804 if (hash == NULL
5805 && asprintf (error_message, _("unable to find THUMB glue '%s' for '%s'"),
5806 tmp_name, name) == -1)
5807 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 5808
5809 free (tmp_name);
5810
5811 return hash;
5812}
5813
9b485d32
NC		 5814/* Locate the ARM encoded calling stub for NAME. */
5815
252b5132 5816static struct elf_link_hash_entry *
57e8b36a
NC		 5817find_arm_glue (struct bfd_link_info *link_info,
5818 const char *name,
f2a9dd69 5819 char **error_message)
252b5132
RH		 5820{
5821 char *tmp_name;
5822 struct elf_link_hash_entry *myh;
5823 struct elf32_arm_link_hash_table *hash_table;
5824
5825 /* We need a pointer to the elfarm specific hash table. */
5826 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 5827 if (hash_table == NULL)
5828 return NULL;
252b5132 5829
21d799b5 5830 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 5831 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 5832
5833 BFD_ASSERT (tmp_name);
5834
5835 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
5836
5837 myh = elf_link_hash_lookup
b34976b6 5838 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 5839
b1657152
AM		 5840 if (myh == NULL
5841 && asprintf (error_message, _("unable to find ARM glue '%s' for '%s'"),
5842 tmp_name, name) == -1)
5843 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 5844
5845 free (tmp_name);
5846
5847 return myh;
5848}
5849
8f6277f5 5850/* ARM->Thumb glue (static images):
252b5132
RH		 5851
5852 .arm
5853 __func_from_arm:
5854 ldr r12, __func_addr
5855 bx r12
5856 __func_addr:
906e58ca 5857 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 5858
26079076
PB		 5859 (v5t static images)
5860 .arm
5861 __func_from_arm:
5862 ldr pc, __func_addr
5863 __func_addr:
906e58ca 5864 .word func @ behave as if you saw a ARM_32 reloc.
26079076 5865
8f6277f5
PB		 5866 (relocatable images)
5867 .arm
5868 __func_from_arm:
5869 ldr r12, __func_offset
5870 add r12, r12, pc
5871 bx r12
5872 __func_offset:
8029a119 5873 .word func - . */
8f6277f5
PB		 5874
5875#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 5876static const insn32 a2t1_ldr_insn = 0xe59fc000;
5877static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
5878static const insn32 a2t3_func_addr_insn = 0x00000001;
5879
26079076
PB		 5880#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
5881static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
5882static const insn32 a2t2v5_func_addr_insn = 0x00000001;
5883
8f6277f5
PB		 5884#define ARM2THUMB_PIC_GLUE_SIZE 16
5885static const insn32 a2t1p_ldr_insn = 0xe59fc004;
5886static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
5887static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
5888
9b485d32 5889/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 5890
8029a119
NC		 5891 .thumb .thumb
5892 .align 2 .align 2
5893 __func_from_thumb: __func_from_thumb:
5894 bx pc push {r6, lr}
5895 nop ldr r6, __func_addr
5896 .arm mov lr, pc
5897 b func bx r6
99059e56
RM		 5898 .arm
5899 ;; back_to_thumb
5900 ldmia r13! {r6, lr}
5901 bx lr
5902 __func_addr:
5903 .word func */
252b5132
RH		 5904
5905#define THUMB2ARM_GLUE_SIZE 8
5906static const insn16 t2a1_bx_pc_insn = 0x4778;
5907static const insn16 t2a2_noop_insn = 0x46c0;
5908static const insn32 t2a3_b_insn = 0xea000000;
5909
c7b8f16e 5910#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 5911#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
5912#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 5913
845b51d6
PB		 5914#define ARM_BX_VENEER_SIZE 12
5915static const insn32 armbx1_tst_insn = 0xe3100001;
5916static const insn32 armbx2_moveq_insn = 0x01a0f000;
5917static const insn32 armbx3_bx_insn = 0xe12fff10;
5918
7e392df6 5919#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 5920static void
5921arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 5922{
5923 asection * s;
8029a119 5924 bfd_byte * contents;
252b5132 5925
8029a119 5926 if (size == 0)
3e6b1042
DJ		 5927 {
5928 /* Do not include empty glue sections in the output. */
5929 if (abfd != NULL)
5930 {
3d4d4302 5931 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 5932 if (s != NULL)
5933 s->flags |= SEC_EXCLUDE;
5934 }
5935 return;
5936 }
252b5132 5937
8029a119 5938 BFD_ASSERT (abfd != NULL);
252b5132 5939
3d4d4302 5940 s = bfd_get_linker_section (abfd, name);
8029a119 5941 BFD_ASSERT (s != NULL);
252b5132 5942
21d799b5 5943 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 5944
8029a119
NC		 5945 BFD_ASSERT (s->size == size);
5946 s->contents = contents;
5947}
906e58ca 5948
8029a119
NC		 5949bfd_boolean
5950bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
5951{
5952 struct elf32_arm_link_hash_table * globals;
906e58ca 5953
8029a119
NC		 5954 globals = elf32_arm_hash_table (info);
5955 BFD_ASSERT (globals != NULL);
906e58ca 5956
8029a119
NC		 5957 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5958 globals->arm_glue_size,
5959 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 5960
8029a119
NC		 5961 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5962 globals->thumb_glue_size,
5963 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 5964
8029a119
NC		 5965 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5966 globals->vfp11_erratum_glue_size,
5967 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 5968
a504d23a
LA		 5969 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5970 globals->stm32l4xx_erratum_glue_size,
5971 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
5972
8029a119
NC		 5973 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5974 globals->bx_glue_size,
845b51d6
PB		 5975 ARM_BX_GLUE_SECTION_NAME);
5976
b34976b6 5977 return TRUE;
252b5132
RH		 5978}
5979
a4fd1a8e 5980/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 5981 returns the symbol identifying the stub. */
5982
a4fd1a8e 5983static struct elf_link_hash_entry *
57e8b36a
NC		 5984record_arm_to_thumb_glue (struct bfd_link_info * link_info,
5985 struct elf_link_hash_entry * h)
252b5132
RH		 5986{
5987 const char * name = h->root.root.string;
63b0f745 5988 asection * s;
252b5132
RH		 5989 char * tmp_name;
5990 struct elf_link_hash_entry * myh;
14a793b2 5991 struct bfd_link_hash_entry * bh;
252b5132 5992 struct elf32_arm_link_hash_table * globals;
dc810e39 5993 bfd_vma val;
2f475487 5994 bfd_size_type size;
252b5132
RH		 5995
5996 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 5997 BFD_ASSERT (globals != NULL);
5998 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
5999
3d4d4302 6000 s = bfd_get_linker_section
252b5132
RH		 6001 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
6002
252b5132
RH		 6003 BFD_ASSERT (s != NULL);
6004
21d799b5 6005 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6006 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6007
6008 BFD_ASSERT (tmp_name);
6009
6010 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6011
6012 myh = elf_link_hash_lookup
b34976b6 6013 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 6014
6015 if (myh != NULL)
6016 {
9b485d32 6017 /* We've already seen this guy. */
252b5132 6018 free (tmp_name);
a4fd1a8e 6019 return myh;
252b5132
RH		 6020 }
6021
57e8b36a
NC		 6022 /* The only trick here is using hash_table->arm_glue_size as the value.
6023 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 6024 putting it. The +1 on the value marks that the stub has not been
6025 output yet - not that it is a Thumb function. */
14a793b2 6026 bh = NULL;
dc810e39
AM		 6027 val = globals->arm_glue_size + 1;
6028 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
6029 tmp_name, BSF_GLOBAL, s, val,
b34976b6 6030 NULL, TRUE, FALSE, &bh);
252b5132 6031
b7693d02
DJ		 6032 myh = (struct elf_link_hash_entry *) bh;
6033 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6034 myh->forced_local = 1;
6035
252b5132
RH		 6036 free (tmp_name);
6037
0e1862bb
L		 6038 if (bfd_link_pic (link_info)
6039 || globals->root.is_relocatable_executable
27e55c4d 6040 || globals->pic_veneer)
2f475487 6041 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 6042 else if (globals->use_blx)
6043 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 6044 else
2f475487
AM		 6045 size = ARM2THUMB_STATIC_GLUE_SIZE;
6046
6047 s->size += size;
6048 globals->arm_glue_size += size;
252b5132 6049
a4fd1a8e 6050 return myh;
252b5132
RH		 6051}
6052
845b51d6
PB		 6053/* Allocate space for ARMv4 BX veneers. */
6054
6055static void
6056record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
6057{
6058 asection * s;
6059 struct elf32_arm_link_hash_table *globals;
6060 char *tmp_name;
6061 struct elf_link_hash_entry *myh;
6062 struct bfd_link_hash_entry *bh;
6063 bfd_vma val;
6064
6065 /* BX PC does not need a veneer. */
6066 if (reg == 15)
6067 return;
6068
6069 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 6070 BFD_ASSERT (globals != NULL);
6071 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6072
6073 /* Check if this veneer has already been allocated. */
6074 if (globals->bx_glue_offset[reg])
6075 return;
6076
3d4d4302 6077 s = bfd_get_linker_section
845b51d6
PB		 6078 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
6079
6080 BFD_ASSERT (s != NULL);
6081
6082 /* Add symbol for veneer. */
21d799b5
NC		 6083 tmp_name = (char *)
6084 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 6085
845b51d6 6086 BFD_ASSERT (tmp_name);
906e58ca 6087
845b51d6 6088 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 6089
845b51d6
PB		 6090 myh = elf_link_hash_lookup
6091 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6092
845b51d6 6093 BFD_ASSERT (myh == NULL);
906e58ca 6094
845b51d6
PB		 6095 bh = NULL;
6096 val = globals->bx_glue_size;
6097 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 6098 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6099 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 6100
6101 myh = (struct elf_link_hash_entry *) bh;
6102 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6103 myh->forced_local = 1;
6104
6105 s->size += ARM_BX_VENEER_SIZE;
6106 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
6107 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
6108}
6109
6110
c7b8f16e
JB		 6111/* Add an entry to the code/data map for section SEC. */
6112
6113static void
6114elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
6115{
6116 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
6117 unsigned int newidx;
906e58ca 6118
c7b8f16e
JB		 6119 if (sec_data->map == NULL)
6120 {
21d799b5 6121 sec_data->map = (elf32_arm_section_map *)
99059e56 6122 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 6123 sec_data->mapcount = 0;
6124 sec_data->mapsize = 1;
6125 }
906e58ca 6126
c7b8f16e 6127 newidx = sec_data->mapcount++;
906e58ca 6128
c7b8f16e
JB		 6129 if (sec_data->mapcount > sec_data->mapsize)
6130 {
6131 sec_data->mapsize *= 2;
21d799b5 6132 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 6133 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
6134 * sizeof (elf32_arm_section_map));
515ef31d
NC		 6135 }
6136
6137 if (sec_data->map)
6138 {
6139 sec_data->map[newidx].vma = vma;
6140 sec_data->map[newidx].type = type;
c7b8f16e 6141 }
c7b8f16e
JB		 6142}
6143
6144
6145/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
6146 veneers are handled for now. */
6147
6148static bfd_vma
6149record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 6150 elf32_vfp11_erratum_list *branch,
6151 bfd *branch_bfd,
6152 asection *branch_sec,
6153 unsigned int offset)
c7b8f16e
JB		 6154{
6155 asection *s;
6156 struct elf32_arm_link_hash_table *hash_table;
6157 char *tmp_name;
6158 struct elf_link_hash_entry *myh;
6159 struct bfd_link_hash_entry *bh;
6160 bfd_vma val;
6161 struct _arm_elf_section_data *sec_data;
c7b8f16e 6162 elf32_vfp11_erratum_list *newerr;
906e58ca 6163
c7b8f16e 6164 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 6165 BFD_ASSERT (hash_table != NULL);
6166 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 6167
3d4d4302 6168 s = bfd_get_linker_section
c7b8f16e 6169 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 6170
c7b8f16e 6171 sec_data = elf32_arm_section_data (s);
906e58ca 6172
c7b8f16e 6173 BFD_ASSERT (s != NULL);
906e58ca 6174
21d799b5 6175 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 6176 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 6177
c7b8f16e 6178 BFD_ASSERT (tmp_name);
906e58ca 6179
c7b8f16e
JB		 6180 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
6181 hash_table->num_vfp11_fixes);
906e58ca 6182
c7b8f16e
JB		 6183 myh = elf_link_hash_lookup
6184 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6185
c7b8f16e 6186 BFD_ASSERT (myh == NULL);
906e58ca 6187
c7b8f16e
JB		 6188 bh = NULL;
6189 val = hash_table->vfp11_erratum_glue_size;
6190 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 6191 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6192 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 6193
6194 myh = (struct elf_link_hash_entry *) bh;
6195 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6196 myh->forced_local = 1;
6197
6198 /* Link veneer back to calling location. */
c7e2358a 6199 sec_data->erratumcount += 1;
21d799b5
NC		 6200 newerr = (elf32_vfp11_erratum_list *)
6201 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 6202
c7b8f16e
JB		 6203 newerr->type = VFP11_ERRATUM_ARM_VENEER;
6204 newerr->vma = -1;
6205 newerr->u.v.branch = branch;
6206 newerr->u.v.id = hash_table->num_vfp11_fixes;
6207 branch->u.b.veneer = newerr;
6208
6209 newerr->next = sec_data->erratumlist;
6210 sec_data->erratumlist = newerr;
6211
6212 /* A symbol for the return from the veneer. */
6213 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
6214 hash_table->num_vfp11_fixes);
6215
6216 myh = elf_link_hash_lookup
6217 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6218
c7b8f16e
JB		 6219 if (myh != NULL)
6220 abort ();
6221
6222 bh = NULL;
6223 val = offset + 4;
6224 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
6225 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 6226
c7b8f16e
JB		 6227 myh = (struct elf_link_hash_entry *) bh;
6228 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6229 myh->forced_local = 1;
6230
6231 free (tmp_name);
906e58ca 6232
c7b8f16e
JB		 6233 /* Generate a mapping symbol for the veneer section, and explicitly add an
6234 entry for that symbol to the code/data map for the section. */
6235 if (hash_table->vfp11_erratum_glue_size == 0)
6236 {
6237 bh = NULL;
6238 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 6239 ever requires this erratum fix. */
c7b8f16e
JB		 6240 _bfd_generic_link_add_one_symbol (link_info,
6241 hash_table->bfd_of_glue_owner, "$a",
6242 BSF_LOCAL, s, 0, NULL,
99059e56 6243 TRUE, FALSE, &bh);
c7b8f16e
JB		 6244
6245 myh = (struct elf_link_hash_entry *) bh;
6246 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
6247 myh->forced_local = 1;
906e58ca 6248
c7b8f16e 6249 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 6250 BFDs. We must make a note of this generated mapping symbol
6251 ourselves so that code byteswapping works properly in
6252 elf32_arm_write_section. */
c7b8f16e
JB		 6253 elf32_arm_section_map_add (s, 'a', 0);
6254 }
906e58ca 6255
c7b8f16e
JB		 6256 s->size += VFP11_ERRATUM_VENEER_SIZE;
6257 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
6258 hash_table->num_vfp11_fixes++;
906e58ca 6259
c7b8f16e
JB		 6260 /* The offset of the veneer. */
6261 return val;
6262}
6263
a504d23a
LA		 6264/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
6265 veneers need to be handled because used only in Cortex-M. */
6266
6267static bfd_vma
6268record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
6269 elf32_stm32l4xx_erratum_list *branch,
6270 bfd *branch_bfd,
6271 asection *branch_sec,
6272 unsigned int offset,
6273 bfd_size_type veneer_size)
6274{
6275 asection *s;
6276 struct elf32_arm_link_hash_table *hash_table;
6277 char *tmp_name;
6278 struct elf_link_hash_entry *myh;
6279 struct bfd_link_hash_entry *bh;
6280 bfd_vma val;
6281 struct _arm_elf_section_data *sec_data;
6282 elf32_stm32l4xx_erratum_list *newerr;
6283
6284 hash_table = elf32_arm_hash_table (link_info);
6285 BFD_ASSERT (hash_table != NULL);
6286 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
6287
6288 s = bfd_get_linker_section
6289 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6290
6291 BFD_ASSERT (s != NULL);
6292
6293 sec_data = elf32_arm_section_data (s);
6294
6295 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
6296 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
6297
6298 BFD_ASSERT (tmp_name);
6299
6300 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
6301 hash_table->num_stm32l4xx_fixes);
6302
6303 myh = elf_link_hash_lookup
6304 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
6305
6306 BFD_ASSERT (myh == NULL);
6307
6308 bh = NULL;
6309 val = hash_table->stm32l4xx_erratum_glue_size;
6310 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
6311 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6312 NULL, TRUE, FALSE, &bh);
6313
6314 myh = (struct elf_link_hash_entry *) bh;
6315 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6316 myh->forced_local = 1;
6317
6318 /* Link veneer back to calling location. */
6319 sec_data->stm32l4xx_erratumcount += 1;
6320 newerr = (elf32_stm32l4xx_erratum_list *)
6321 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
6322
6323 newerr->type = STM32L4XX_ERRATUM_VENEER;
6324 newerr->vma = -1;
6325 newerr->u.v.branch = branch;
6326 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
6327 branch->u.b.veneer = newerr;
6328
6329 newerr->next = sec_data->stm32l4xx_erratumlist;
6330 sec_data->stm32l4xx_erratumlist = newerr;
6331
6332 /* A symbol for the return from the veneer. */
6333 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
6334 hash_table->num_stm32l4xx_fixes);
6335
6336 myh = elf_link_hash_lookup
6337 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
6338
6339 if (myh != NULL)
6340 abort ();
6341
6342 bh = NULL;
6343 val = offset + 4;
6344 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
6345 branch_sec, val, NULL, TRUE, FALSE, &bh);
6346
6347 myh = (struct elf_link_hash_entry *) bh;
6348 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6349 myh->forced_local = 1;
6350
6351 free (tmp_name);
6352
6353 /* Generate a mapping symbol for the veneer section, and explicitly add an
6354 entry for that symbol to the code/data map for the section. */
6355 if (hash_table->stm32l4xx_erratum_glue_size == 0)
6356 {
6357 bh = NULL;
6358 /* Creates a THUMB symbol since there is no other choice. */
6359 _bfd_generic_link_add_one_symbol (link_info,
6360 hash_table->bfd_of_glue_owner, "$t",
6361 BSF_LOCAL, s, 0, NULL,
6362 TRUE, FALSE, &bh);
6363
6364 myh = (struct elf_link_hash_entry *) bh;
6365 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
6366 myh->forced_local = 1;
6367
6368 /* The elf32_arm_init_maps function only cares about symbols from input
6369 BFDs. We must make a note of this generated mapping symbol
6370 ourselves so that code byteswapping works properly in
6371 elf32_arm_write_section. */
6372 elf32_arm_section_map_add (s, 't', 0);
6373 }
6374
6375 s->size += veneer_size;
6376 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
6377 hash_table->num_stm32l4xx_fixes++;
6378
6379 /* The offset of the veneer. */
6380 return val;
6381}
6382
8029a119 6383#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 6384 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
6385 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 6386
6387/* Create a fake section for use by the ARM backend of the linker. */
6388
6389static bfd_boolean
6390arm_make_glue_section (bfd * abfd, const char * name)
6391{
6392 asection * sec;
6393
3d4d4302 6394 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 6395 if (sec != NULL)
6396 /* Already made. */
6397 return TRUE;
6398
3d4d4302 6399 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 6400
6401 if (sec == NULL
6402 || !bfd_set_section_alignment (abfd, sec, 2))
6403 return FALSE;
6404
6405 /* Set the gc mark to prevent the section from being removed by garbage
6406 collection, despite the fact that no relocs refer to this section. */
6407 sec->gc_mark = 1;
6408
6409 return TRUE;
6410}
6411
1db37fe6
YG		 6412/* Set size of .plt entries. This function is called from the
6413 linker scripts in ld/emultempl/{armelf}.em. */
6414
6415void
6416bfd_elf32_arm_use_long_plt (void)
6417{
6418 elf32_arm_use_long_plt_entry = TRUE;
6419}
6420
8afb0e02
NC		 6421/* Add the glue sections to ABFD. This function is called from the
6422 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 6423
b34976b6 6424bfd_boolean
57e8b36a
NC		 6425bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
6426 struct bfd_link_info *info)
252b5132 6427{
a504d23a
LA		 6428 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
6429 bfd_boolean dostm32l4xx = globals
6430 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
6431 bfd_boolean addglue;
6432
8afb0e02
NC		 6433 /* If we are only performing a partial
6434 link do not bother adding the glue. */
0e1862bb 6435 if (bfd_link_relocatable (info))
b34976b6 6436 return TRUE;
252b5132 6437
a504d23a 6438 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 6439 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
6440 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
6441 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 6442
6443 if (!dostm32l4xx)
6444 return addglue;
6445
6446 return addglue
6447 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 6448}
6449
6450/* Select a BFD to be used to hold the sections used by the glue code.
6451 This function is called from the linker scripts in ld/emultempl/
8029a119 6452 {armelf/pe}.em. */
8afb0e02 6453
b34976b6 6454bfd_boolean
57e8b36a 6455bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 6456{
6457 struct elf32_arm_link_hash_table *globals;
6458
6459 /* If we are only performing a partial link
6460 do not bother getting a bfd to hold the glue. */
0e1862bb 6461 if (bfd_link_relocatable (info))
b34976b6 6462 return TRUE;
8afb0e02 6463
b7693d02
DJ		 6464 /* Make sure we don't attach the glue sections to a dynamic object. */
6465 BFD_ASSERT (!(abfd->flags & DYNAMIC));
6466
8afb0e02 6467 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 6468 BFD_ASSERT (globals != NULL);
6469
6470 if (globals->bfd_of_glue_owner != NULL)
b34976b6 6471 return TRUE;
8afb0e02 6472
252b5132
RH		 6473 /* Save the bfd for later use. */
6474 globals->bfd_of_glue_owner = abfd;
cedb70c5 6475
b34976b6 6476 return TRUE;
252b5132
RH		 6477}
6478
906e58ca
NC		 6479static void
6480check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 6481{
2de70689
MGD		 6482 int cpu_arch;
6483
b38cadfb 6484 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 6485 Tag_CPU_arch);
6486
6487 if (globals->fix_arm1176)
6488 {
6489 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
6490 globals->use_blx = 1;
6491 }
6492 else
6493 {
6494 if (cpu_arch > TAG_CPU_ARCH_V4T)
6495 globals->use_blx = 1;
6496 }
39b41c9c
PB		 6497}
6498
b34976b6 6499bfd_boolean
57e8b36a 6500bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 6501 struct bfd_link_info *link_info)
252b5132
RH		 6502{
6503 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 6504 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 6505 Elf_Internal_Rela *irel, *irelend;
6506 bfd_byte *contents = NULL;
252b5132
RH		 6507
6508 asection *sec;
6509 struct elf32_arm_link_hash_table *globals;
6510
6511 /* If we are only performing a partial link do not bother
6512 to construct any glue. */
0e1862bb 6513 if (bfd_link_relocatable (link_info))
b34976b6 6514 return TRUE;
252b5132 6515
39ce1a6a
NC		 6516 /* Here we have a bfd that is to be included on the link. We have a
6517 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 6518 globals = elf32_arm_hash_table (link_info);
252b5132 6519 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 6520
6521 check_use_blx (globals);
252b5132 6522
d504ffc8 6523 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 6524 {
d003868e
AM		 6525 _bfd_error_handler (_("%B: BE8 images only valid in big-endian mode."),
6526 abfd);
e489d0ae
PB		 6527 return FALSE;
6528 }
f21f3fe0 6529
39ce1a6a
NC		 6530 /* PR 5398: If we have not decided to include any loadable sections in
6531 the output then we will not have a glue owner bfd. This is OK, it
6532 just means that there is nothing else for us to do here. */
6533 if (globals->bfd_of_glue_owner == NULL)
6534 return TRUE;
6535
252b5132
RH		 6536 /* Rummage around all the relocs and map the glue vectors. */
6537 sec = abfd->sections;
6538
6539 if (sec == NULL)
b34976b6 6540 return TRUE;
252b5132
RH		 6541
6542 for (; sec != NULL; sec = sec->next)
6543 {
6544 if (sec->reloc_count == 0)
6545 continue;
6546
2f475487
AM		 6547 if ((sec->flags & SEC_EXCLUDE) != 0)
6548 continue;
6549
0ffa91dd 6550 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 6551
9b485d32 6552 /* Load the relocs. */
6cdc0ccc 6553 internal_relocs
906e58ca 6554 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 6555
6cdc0ccc
AM		 6556 if (internal_relocs == NULL)
6557 goto error_return;
252b5132 6558
6cdc0ccc
AM		 6559 irelend = internal_relocs + sec->reloc_count;
6560 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 6561 {
6562 long r_type;
6563 unsigned long r_index;
252b5132
RH		 6564
6565 struct elf_link_hash_entry *h;
6566
6567 r_type = ELF32_R_TYPE (irel->r_info);
6568 r_index = ELF32_R_SYM (irel->r_info);
6569
9b485d32 6570 /* These are the only relocation types we care about. */
ba96a88f 6571 if ( r_type != R_ARM_PC24
845b51d6 6572 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 6573 continue;
6574
6575 /* Get the section contents if we haven't done so already. */
6576 if (contents == NULL)
6577 {
6578 /* Get cached copy if it exists. */
6579 if (elf_section_data (sec)->this_hdr.contents != NULL)
6580 contents = elf_section_data (sec)->this_hdr.contents;
6581 else
6582 {
6583 /* Go get them off disk. */
57e8b36a 6584 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 6585 goto error_return;
6586 }
6587 }
6588
845b51d6
PB		 6589 if (r_type == R_ARM_V4BX)
6590 {
6591 int reg;
6592
6593 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
6594 record_arm_bx_glue (link_info, reg);
6595 continue;
6596 }
6597
a7c10850 6598 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 6599 h = NULL;
6600
9b485d32 6601 /* We don't care about local symbols. */
252b5132
RH		 6602 if (r_index < symtab_hdr->sh_info)
6603 continue;
6604
9b485d32 6605 /* This is an external symbol. */
252b5132
RH		 6606 r_index -= symtab_hdr->sh_info;
6607 h = (struct elf_link_hash_entry *)
6608 elf_sym_hashes (abfd)[r_index];
6609
6610 /* If the relocation is against a static symbol it must be within
6611 the current section and so cannot be a cross ARM/Thumb relocation. */
6612 if (h == NULL)
6613 continue;
6614
d504ffc8
DJ		 6615 /* If the call will go through a PLT entry then we do not need
6616 glue. */
362d30a1 6617 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 6618 continue;
6619
252b5132
RH		 6620 switch (r_type)
6621 {
6622 case R_ARM_PC24:
6623 /* This one is a call from arm code. We need to look up
99059e56
RM		 6624 the target of the call. If it is a thumb target, we
6625 insert glue. */
35fc36a8 6626 if (h->target_internal == ST_BRANCH_TO_THUMB)
252b5132
RH		 6627 record_arm_to_thumb_glue (link_info, h);
6628 break;
6629
252b5132 6630 default:
c6596c5e 6631 abort ();
252b5132
RH		 6632 }
6633 }
6cdc0ccc
AM		 6634
6635 if (contents != NULL
6636 && elf_section_data (sec)->this_hdr.contents != contents)
6637 free (contents);
6638 contents = NULL;
6639
6640 if (internal_relocs != NULL
6641 && elf_section_data (sec)->relocs != internal_relocs)
6642 free (internal_relocs);
6643 internal_relocs = NULL;
252b5132
RH		 6644 }
6645
b34976b6 6646 return TRUE;
9a5aca8c 6647
252b5132 6648error_return:
6cdc0ccc
AM		 6649 if (contents != NULL
6650 && elf_section_data (sec)->this_hdr.contents != contents)
6651 free (contents);
6652 if (internal_relocs != NULL
6653 && elf_section_data (sec)->relocs != internal_relocs)
6654 free (internal_relocs);
9a5aca8c 6655
b34976b6 6656 return FALSE;
252b5132 6657}
7e392df6 6658#endif
252b5132 6659
eb043451 6660
c7b8f16e
JB		 6661/* Initialise maps of ARM/Thumb/data for input BFDs. */
6662
6663void
6664bfd_elf32_arm_init_maps (bfd *abfd)
6665{
6666 Elf_Internal_Sym *isymbuf;
6667 Elf_Internal_Shdr *hdr;
6668 unsigned int i, localsyms;
6669
af1f4419
NC		 6670 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
6671 if (! is_arm_elf (abfd))
6672 return;
6673
c7b8f16e
JB		 6674 if ((abfd->flags & DYNAMIC) != 0)
6675 return;
6676
0ffa91dd 6677 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 6678 localsyms = hdr->sh_info;
6679
6680 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
6681 should contain the number of local symbols, which should come before any
6682 global symbols. Mapping symbols are always local. */
6683 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
6684 NULL);
6685
6686 /* No internal symbols read? Skip this BFD. */
6687 if (isymbuf == NULL)
6688 return;
6689
6690 for (i = 0; i < localsyms; i++)
6691 {
6692 Elf_Internal_Sym *isym = &isymbuf[i];
6693 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
6694 const char *name;
906e58ca 6695
c7b8f16e 6696 if (sec != NULL
99059e56
RM		 6697 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
6698 {
6699 name = bfd_elf_string_from_elf_section (abfd,
6700 hdr->sh_link, isym->st_name);
906e58ca 6701
99059e56 6702 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 6703 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 6704 elf32_arm_section_map_add (sec, name[1], isym->st_value);
6705 }
c7b8f16e
JB		 6706 }
6707}
6708
6709
48229727
JB		 6710/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
6711 say what they wanted. */
6712
6713void
6714bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
6715{
6716 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
6717 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
6718
4dfe6ac6
NC		 6719 if (globals == NULL)
6720 return;
6721
48229727
JB		 6722 if (globals->fix_cortex_a8 == -1)
6723 {
6724 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
6725 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
6726 && (out_attr[Tag_CPU_arch_profile].i == 'A'
6727 || out_attr[Tag_CPU_arch_profile].i == 0))
6728 globals->fix_cortex_a8 = 1;
6729 else
6730 globals->fix_cortex_a8 = 0;
6731 }
6732}
6733
6734
c7b8f16e
JB		 6735void
6736bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
6737{
6738 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 6739 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 6740
4dfe6ac6
NC		 6741 if (globals == NULL)
6742 return;
c7b8f16e
JB		 6743 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
6744 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
6745 {
6746 switch (globals->vfp11_fix)
99059e56
RM		 6747 {
6748 case BFD_ARM_VFP11_FIX_DEFAULT:
6749 case BFD_ARM_VFP11_FIX_NONE:
6750 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
6751 break;
6752
6753 default:
6754 /* Give a warning, but do as the user requests anyway. */
6755 (*_bfd_error_handler) (_("%B: warning: selected VFP11 erratum "
6756 "workaround is not necessary for target architecture"), obfd);
6757 }
c7b8f16e
JB		 6758 }
6759 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
6760 /* For earlier architectures, we might need the workaround, but do not
6761 enable it by default. If users is running with broken hardware, they
6762 must enable the erratum fix explicitly. */
6763 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
6764}
6765
a504d23a
LA		 6766void
6767bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
6768{
6769 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
6770 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
6771
6772 if (globals == NULL)
6773 return;
6774
6775 /* We assume only Cortex-M4 may require the fix. */
6776 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
6777 || out_attr[Tag_CPU_arch_profile].i != 'M')
6778 {
6779 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
6780 /* Give a warning, but do as the user requests anyway. */
6781 (*_bfd_error_handler)
6782 (_("%B: warning: selected STM32L4XX erratum "
6783 "workaround is not necessary for target architecture"), obfd);
6784 }
6785}
c7b8f16e 6786
906e58ca
NC		 6787enum bfd_arm_vfp11_pipe
6788{
c7b8f16e
JB		 6789 VFP11_FMAC,
6790 VFP11_LS,
6791 VFP11_DS,
6792 VFP11_BAD
6793};
6794
6795/* Return a VFP register number. This is encoded as RX:X for single-precision
6796 registers, or X:RX for double-precision registers, where RX is the group of
6797 four bits in the instruction encoding and X is the single extension bit.
6798 RX and X fields are specified using their lowest (starting) bit. The return
6799 value is:
6800
6801 0...31: single-precision registers s0...s31
6802 32...63: double-precision registers d0...d31.
906e58ca 6803
c7b8f16e
JB		 6804 Although X should be zero for VFP11 (encoding d0...d15 only), we might
6805 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 6806
c7b8f16e
JB		 6807static unsigned int
6808bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 6809 unsigned int x)
c7b8f16e
JB		 6810{
6811 if (is_double)
6812 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
6813 else
6814 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
6815}
6816
6817/* Set bits in *WMASK according to a register number REG as encoded by
6818 bfd_arm_vfp11_regno(). Ignore d16-d31. */
6819
6820static void
6821bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
6822{
6823 if (reg < 32)
6824 *wmask |= 1 << reg;
6825 else if (reg < 48)
6826 *wmask |= 3 << ((reg - 32) * 2);
6827}
6828
6829/* Return TRUE if WMASK overwrites anything in REGS. */
6830
6831static bfd_boolean
6832bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
6833{
6834 int i;
906e58ca 6835
c7b8f16e
JB		 6836 for (i = 0; i < numregs; i++)
6837 {
6838 unsigned int reg = regs[i];
6839
6840 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 6841 return TRUE;
906e58ca 6842
c7b8f16e
JB		 6843 reg -= 32;
6844
6845 if (reg >= 16)
99059e56 6846 continue;
906e58ca 6847
c7b8f16e 6848 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 6849 return TRUE;
c7b8f16e 6850 }
906e58ca 6851
c7b8f16e
JB		 6852 return FALSE;
6853}
6854
6855/* In this function, we're interested in two things: finding input registers
6856 for VFP data-processing instructions, and finding the set of registers which
6857 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
6858 hold the written set, so FLDM etc. are easy to deal with (we're only
6859 interested in 32 SP registers or 16 dp registers, due to the VFP version
6860 implemented by the chip in question). DP registers are marked by setting
6861 both SP registers in the write mask). */
6862
6863static enum bfd_arm_vfp11_pipe
6864bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 6865 int *numregs)
c7b8f16e 6866{
91d6fa6a 6867 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 6868 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
6869
6870 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
6871 {
6872 unsigned int pqrs;
6873 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
6874 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
6875
6876 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 6877 | ((insn & 0x00300000) >> 19)
6878 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 6879
6880 switch (pqrs)
99059e56
RM		 6881 {
6882 case 0: /* fmac[sd]. */
6883 case 1: /* fnmac[sd]. */
6884 case 2: /* fmsc[sd]. */
6885 case 3: /* fnmsc[sd]. */
6886 vpipe = VFP11_FMAC;
6887 bfd_arm_vfp11_write_mask (destmask, fd);
6888 regs[0] = fd;
6889 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
6890 regs[2] = fm;
6891 *numregs = 3;
6892 break;
6893
6894 case 4: /* fmul[sd]. */
6895 case 5: /* fnmul[sd]. */
6896 case 6: /* fadd[sd]. */
6897 case 7: /* fsub[sd]. */
6898 vpipe = VFP11_FMAC;
6899 goto vfp_binop;
6900
6901 case 8: /* fdiv[sd]. */
6902 vpipe = VFP11_DS;
6903 vfp_binop:
6904 bfd_arm_vfp11_write_mask (destmask, fd);
6905 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
6906 regs[1] = fm;
6907 *numregs = 2;
6908 break;
6909
6910 case 15: /* extended opcode. */
6911 {
6912 unsigned int extn = ((insn >> 15) & 0x1e)
6913 | ((insn >> 7) & 1);
6914
6915 switch (extn)
6916 {
6917 case 0: /* fcpy[sd]. */
6918 case 1: /* fabs[sd]. */
6919 case 2: /* fneg[sd]. */
6920 case 8: /* fcmp[sd]. */
6921 case 9: /* fcmpe[sd]. */
6922 case 10: /* fcmpz[sd]. */
6923 case 11: /* fcmpez[sd]. */
6924 case 16: /* fuito[sd]. */
6925 case 17: /* fsito[sd]. */
6926 case 24: /* ftoui[sd]. */
6927 case 25: /* ftouiz[sd]. */
6928 case 26: /* ftosi[sd]. */
6929 case 27: /* ftosiz[sd]. */
6930 /* These instructions will not bounce due to underflow. */
6931 *numregs = 0;
6932 vpipe = VFP11_FMAC;
6933 break;
6934
6935 case 3: /* fsqrt[sd]. */
6936 /* fsqrt cannot underflow, but it can (perhaps) overwrite
6937 registers to cause the erratum in previous instructions. */
6938 bfd_arm_vfp11_write_mask (destmask, fd);
6939 vpipe = VFP11_DS;
6940 break;
6941
6942 case 15: /* fcvt{ds,sd}. */
6943 {
6944 int rnum = 0;
6945
6946 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 6947
6948 /* Only FCVTSD can underflow. */
99059e56
RM		 6949 if ((insn & 0x100) != 0)
6950 regs[rnum++] = fm;
c7b8f16e 6951
99059e56 6952 *numregs = rnum;
c7b8f16e 6953
99059e56
RM		 6954 vpipe = VFP11_FMAC;
6955 }
6956 break;
c7b8f16e 6957
99059e56
RM		 6958 default:
6959 return VFP11_BAD;
6960 }
6961 }
6962 break;
c7b8f16e 6963
99059e56
RM		 6964 default:
6965 return VFP11_BAD;
6966 }
c7b8f16e
JB		 6967 }
6968 /* Two-register transfer. */
6969 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
6970 {
6971 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 6972
c7b8f16e
JB		 6973 if ((insn & 0x100000) == 0)
6974 {
99059e56
RM		 6975 if (is_double)
6976 bfd_arm_vfp11_write_mask (destmask, fm);
6977 else
6978 {
6979 bfd_arm_vfp11_write_mask (destmask, fm);
6980 bfd_arm_vfp11_write_mask (destmask, fm + 1);
6981 }
c7b8f16e
JB		 6982 }
6983
91d6fa6a 6984 vpipe = VFP11_LS;
c7b8f16e
JB		 6985 }
6986 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
6987 {
6988 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
6989 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 6990
c7b8f16e 6991 switch (puw)
99059e56
RM		 6992 {
6993 case 0: /* Two-reg transfer. We should catch these above. */
6994 abort ();
906e58ca 6995
99059e56
RM		 6996 case 2: /* fldm[sdx]. */
6997 case 3:
6998 case 5:
6999 {
7000 unsigned int i, offset = insn & 0xff;
c7b8f16e 7001
99059e56
RM		 7002 if (is_double)
7003 offset >>= 1;
c7b8f16e 7004
99059e56
RM		 7005 for (i = fd; i < fd + offset; i++)
7006 bfd_arm_vfp11_write_mask (destmask, i);
7007 }
7008 break;
906e58ca 7009
99059e56
RM		 7010 case 4: /* fld[sd]. */
7011 case 6:
7012 bfd_arm_vfp11_write_mask (destmask, fd);
7013 break;
906e58ca 7014
99059e56
RM		 7015 default:
7016 return VFP11_BAD;
7017 }
c7b8f16e 7018
91d6fa6a 7019 vpipe = VFP11_LS;
c7b8f16e
JB		 7020 }
7021 /* Single-register transfer. Note L==0. */
7022 else if ((insn & 0x0f100e10) == 0x0e000a10)
7023 {
7024 unsigned int opcode = (insn >> 21) & 7;
7025 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
7026
7027 switch (opcode)
99059e56
RM		 7028 {
7029 case 0: /* fmsr/fmdlr. */
7030 case 1: /* fmdhr. */
7031 /* Mark fmdhr and fmdlr as writing to the whole of the DP
7032 destination register. I don't know if this is exactly right,
7033 but it is the conservative choice. */
7034 bfd_arm_vfp11_write_mask (destmask, fn);
7035 break;
7036
7037 case 7: /* fmxr. */
7038 break;
7039 }
c7b8f16e 7040
91d6fa6a 7041 vpipe = VFP11_LS;
c7b8f16e
JB		 7042 }
7043
91d6fa6a 7044 return vpipe;
c7b8f16e
JB		 7045}
7046
7047
7048static int elf32_arm_compare_mapping (const void * a, const void * b);
7049
7050
7051/* Look for potentially-troublesome code sequences which might trigger the
7052 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
7053 (available from ARM) for details of the erratum. A short version is
7054 described in ld.texinfo. */
7055
7056bfd_boolean
7057bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
7058{
7059 asection *sec;
7060 bfd_byte *contents = NULL;
7061 int state = 0;
7062 int regs[3], numregs = 0;
7063 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7064 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 7065
4dfe6ac6
NC		 7066 if (globals == NULL)
7067 return FALSE;
7068
c7b8f16e
JB		 7069 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
7070 The states transition as follows:
906e58ca 7071
c7b8f16e 7072 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 7073 A VFP FMAC-pipeline instruction has been seen. Fill
7074 regs[0]..regs[numregs-1] with its input operands. Remember this
7075 instruction in 'first_fmac'.
c7b8f16e
JB		 7076
7077 1 -> 2
99059e56
RM		 7078 Any instruction, except for a VFP instruction which overwrites
7079 regs[*].
906e58ca 7080
c7b8f16e
JB		 7081 1 -> 3 [ -> 0 ] or
7082 2 -> 3 [ -> 0 ]
99059e56
RM		 7083 A VFP instruction has been seen which overwrites any of regs[*].
7084 We must make a veneer! Reset state to 0 before examining next
7085 instruction.
906e58ca 7086
c7b8f16e 7087 2 -> 0
99059e56
RM		 7088 If we fail to match anything in state 2, reset to state 0 and reset
7089 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 7090
7091 If the VFP11 vector mode is in use, there must be at least two unrelated
7092 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 7093 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 7094
7095 /* If we are only performing a partial link do not bother
7096 to construct any glue. */
0e1862bb 7097 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 7098 return TRUE;
7099
0ffa91dd
NC		 7100 /* Skip if this bfd does not correspond to an ELF image. */
7101 if (! is_arm_elf (abfd))
7102 return TRUE;
906e58ca 7103
c7b8f16e
JB		 7104 /* We should have chosen a fix type by the time we get here. */
7105 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
7106
7107 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
7108 return TRUE;
2e6030b9 7109
33a7ffc2
JM		 7110 /* Skip this BFD if it corresponds to an executable or dynamic object. */
7111 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
7112 return TRUE;
7113
c7b8f16e
JB		 7114 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7115 {
7116 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
7117 struct _arm_elf_section_data *sec_data;
7118
7119 /* If we don't have executable progbits, we're not interested in this
99059e56 7120 section. Also skip if section is to be excluded. */
c7b8f16e 7121 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 7122 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
7123 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 7124 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 7125 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 7126 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
7127 continue;
c7b8f16e
JB		 7128
7129 sec_data = elf32_arm_section_data (sec);
906e58ca 7130
c7b8f16e 7131 if (sec_data->mapcount == 0)
99059e56 7132 continue;
906e58ca 7133
c7b8f16e
JB		 7134 if (elf_section_data (sec)->this_hdr.contents != NULL)
7135 contents = elf_section_data (sec)->this_hdr.contents;
7136 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
7137 goto error_return;
7138
7139 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
7140 elf32_arm_compare_mapping);
7141
7142 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 7143 {
7144 unsigned int span_start = sec_data->map[span].vma;
7145 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 7146 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 7147 char span_type = sec_data->map[span].type;
7148
7149 /* FIXME: Only ARM mode is supported at present. We may need to
7150 support Thumb-2 mode also at some point. */
7151 if (span_type != 'a')
7152 continue;
7153
7154 for (i = span_start; i < span_end;)
7155 {
7156 unsigned int next_i = i + 4;
7157 unsigned int insn = bfd_big_endian (abfd)
7158 ? (contents[i] << 24)
7159 | (contents[i + 1] << 16)
7160 | (contents[i + 2] << 8)
7161 | contents[i + 3]
7162 : (contents[i + 3] << 24)
7163 | (contents[i + 2] << 16)
7164 | (contents[i + 1] << 8)
7165 | contents[i];
7166 unsigned int writemask = 0;
7167 enum bfd_arm_vfp11_pipe vpipe;
7168
7169 switch (state)
7170 {
7171 case 0:
7172 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
7173 &numregs);
7174 /* I'm assuming the VFP11 erratum can trigger with denorm
7175 operands on either the FMAC or the DS pipeline. This might
7176 lead to slightly overenthusiastic veneer insertion. */
7177 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
7178 {
7179 state = use_vector ? 1 : 2;
7180 first_fmac = i;
7181 veneer_of_insn = insn;
7182 }
7183 break;
7184
7185 case 1:
7186 {
7187 int other_regs[3], other_numregs;
7188 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 7189 other_regs,
99059e56
RM		 7190 &other_numregs);
7191 if (vpipe != VFP11_BAD
7192 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 7193 numregs))
99059e56
RM		 7194 state = 3;
7195 else
7196 state = 2;
7197 }
7198 break;
7199
7200 case 2:
7201 {
7202 int other_regs[3], other_numregs;
7203 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 7204 other_regs,
99059e56
RM		 7205 &other_numregs);
7206 if (vpipe != VFP11_BAD
7207 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 7208 numregs))
99059e56
RM		 7209 state = 3;
7210 else
7211 {
7212 state = 0;
7213 next_i = first_fmac + 4;
7214 }
7215 }
7216 break;
7217
7218 case 3:
7219 abort (); /* Should be unreachable. */
7220 }
7221
7222 if (state == 3)
7223 {
7224 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
7225 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
7226
7227 elf32_arm_section_data (sec)->erratumcount += 1;
7228
7229 newerr->u.b.vfp_insn = veneer_of_insn;
7230
7231 switch (span_type)
7232 {
7233 case 'a':
7234 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
7235 break;
7236
7237 default:
7238 abort ();
7239 }
7240
7241 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 7242 first_fmac);
7243
99059e56 7244 newerr->vma = -1;
c7b8f16e 7245
99059e56
RM		 7246 newerr->next = sec_data->erratumlist;
7247 sec_data->erratumlist = newerr;
c7b8f16e 7248
99059e56
RM		 7249 state = 0;
7250 }
c7b8f16e 7251
99059e56
RM		 7252 i = next_i;
7253 }
7254 }
906e58ca 7255
c7b8f16e 7256 if (contents != NULL
99059e56
RM		 7257 && elf_section_data (sec)->this_hdr.contents != contents)
7258 free (contents);
c7b8f16e
JB		 7259 contents = NULL;
7260 }
7261
7262 return TRUE;
7263
7264error_return:
7265 if (contents != NULL
7266 && elf_section_data (sec)->this_hdr.contents != contents)
7267 free (contents);
906e58ca 7268
c7b8f16e
JB		 7269 return FALSE;
7270}
7271
7272/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
7273 after sections have been laid out, using specially-named symbols. */
7274
7275void
7276bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
7277 struct bfd_link_info *link_info)
7278{
7279 asection *sec;
7280 struct elf32_arm_link_hash_table *globals;
7281 char *tmp_name;
906e58ca 7282
0e1862bb 7283 if (bfd_link_relocatable (link_info))
c7b8f16e 7284 return;
2e6030b9
MS		 7285
7286 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 7287 if (! is_arm_elf (abfd))
2e6030b9
MS		 7288 return;
7289
c7b8f16e 7290 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7291 if (globals == NULL)
7292 return;
906e58ca 7293
21d799b5 7294 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7295 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 7296
7297 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7298 {
7299 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7300 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 7301
c7b8f16e 7302 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 7303 {
7304 struct elf_link_hash_entry *myh;
7305 bfd_vma vma;
7306
7307 switch (errnode->type)
7308 {
7309 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
7310 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
7311 /* Find veneer symbol. */
7312 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 7313 errnode->u.b.veneer->u.v.id);
7314
99059e56
RM		 7315 myh = elf_link_hash_lookup
7316 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 7317
a504d23a
LA		 7318 if (myh == NULL)
7319 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
7320 "`%s'"), abfd, tmp_name);
7321
7322 vma = myh->root.u.def.section->output_section->vma
7323 + myh->root.u.def.section->output_offset
7324 + myh->root.u.def.value;
7325
7326 errnode->u.b.veneer->vma = vma;
7327 break;
7328
7329 case VFP11_ERRATUM_ARM_VENEER:
7330 case VFP11_ERRATUM_THUMB_VENEER:
7331 /* Find return location. */
7332 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7333 errnode->u.v.id);
7334
7335 myh = elf_link_hash_lookup
7336 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7337
7338 if (myh == NULL)
7339 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
7340 "`%s'"), abfd, tmp_name);
7341
7342 vma = myh->root.u.def.section->output_section->vma
7343 + myh->root.u.def.section->output_offset
7344 + myh->root.u.def.value;
7345
7346 errnode->u.v.branch->vma = vma;
7347 break;
7348
7349 default:
7350 abort ();
7351 }
7352 }
7353 }
7354
7355 free (tmp_name);
7356}
7357
7358/* Find virtual-memory addresses for STM32L4XX erratum veneers and
7359 return locations after sections have been laid out, using
7360 specially-named symbols. */
7361
7362void
7363bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
7364 struct bfd_link_info *link_info)
7365{
7366 asection *sec;
7367 struct elf32_arm_link_hash_table *globals;
7368 char *tmp_name;
7369
7370 if (bfd_link_relocatable (link_info))
7371 return;
7372
7373 /* Skip if this bfd does not correspond to an ELF image. */
7374 if (! is_arm_elf (abfd))
7375 return;
7376
7377 globals = elf32_arm_hash_table (link_info);
7378 if (globals == NULL)
7379 return;
7380
7381 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7382 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7383
7384 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7385 {
7386 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7387 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
7388
7389 for (; errnode != NULL; errnode = errnode->next)
7390 {
7391 struct elf_link_hash_entry *myh;
7392 bfd_vma vma;
7393
7394 switch (errnode->type)
7395 {
7396 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
7397 /* Find veneer symbol. */
7398 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7399 errnode->u.b.veneer->u.v.id);
7400
7401 myh = elf_link_hash_lookup
7402 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7403
7404 if (myh == NULL)
7405 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
7406 "`%s'"), abfd, tmp_name);
7407
7408 vma = myh->root.u.def.section->output_section->vma
7409 + myh->root.u.def.section->output_offset
7410 + myh->root.u.def.value;
7411
7412 errnode->u.b.veneer->vma = vma;
7413 break;
7414
7415 case STM32L4XX_ERRATUM_VENEER:
7416 /* Find return location. */
7417 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7418 errnode->u.v.id);
7419
7420 myh = elf_link_hash_lookup
7421 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7422
7423 if (myh == NULL)
7424 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
7425 "`%s'"), abfd, tmp_name);
7426
7427 vma = myh->root.u.def.section->output_section->vma
7428 + myh->root.u.def.section->output_offset
7429 + myh->root.u.def.value;
7430
7431 errnode->u.v.branch->vma = vma;
7432 break;
7433
7434 default:
7435 abort ();
7436 }
7437 }
7438 }
7439
7440 free (tmp_name);
7441}
7442
7443static inline bfd_boolean
7444is_thumb2_ldmia (const insn32 insn)
7445{
7446 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
7447 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
7448 return (insn & 0xffd02000) == 0xe8900000;
7449}
7450
7451static inline bfd_boolean
7452is_thumb2_ldmdb (const insn32 insn)
7453{
7454 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
7455 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
7456 return (insn & 0xffd02000) == 0xe9100000;
7457}
7458
7459static inline bfd_boolean
7460is_thumb2_vldm (const insn32 insn)
7461{
7462 /* A6.5 Extension register load or store instruction
7463 A7.7.229
9239bbd3
CM		 7464 We look for SP 32-bit and DP 64-bit registers.
7465 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
7466 <list> is consecutive 64-bit registers
7467 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 7468 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
7469 <list> is consecutive 32-bit registers
7470 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
7471 if P==0 && U==1 && W==1 && Rn=1101 VPOP
7472 if PUW=010 || PUW=011 || PUW=101 VLDM. */
7473 return
9239bbd3
CM		 7474 (((insn & 0xfe100f00) == 0xec100b00) ||
7475 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 7476 && /* (IA without !). */
7477 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 7478 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 7479 || ((((insn << 7) >> 28) & 0xd) == 0x5)
7480 /* (DB with !). */
7481 || ((((insn << 7) >> 28) & 0xd) == 0x9));
7482}
7483
7484/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
7485 VLDM opcode and:
7486 - computes the number and the mode of memory accesses
7487 - decides if the replacement should be done:
7488 . replaces only if > 8-word accesses
7489 . or (testing purposes only) replaces all accesses. */
7490
7491static bfd_boolean
7492stm32l4xx_need_create_replacing_stub (const insn32 insn,
7493 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
7494{
9239bbd3 7495 int nb_words = 0;
a504d23a
LA		 7496
7497 /* The field encoding the register list is the same for both LDMIA
7498 and LDMDB encodings. */
7499 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
9239bbd3 7500 nb_words = popcount (insn & 0x0000ffff);
a504d23a 7501 else if (is_thumb2_vldm (insn))
9239bbd3 7502 nb_words = (insn & 0xff);
a504d23a
LA		 7503
7504 /* DEFAULT mode accounts for the real bug condition situation,
7505 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
7506 return
9239bbd3 7507 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 7508 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
7509}
7510
7511/* Look for potentially-troublesome code sequences which might trigger
7512 the STM STM32L4XX erratum. */
7513
7514bfd_boolean
7515bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
7516 struct bfd_link_info *link_info)
7517{
7518 asection *sec;
7519 bfd_byte *contents = NULL;
7520 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7521
7522 if (globals == NULL)
7523 return FALSE;
7524
7525 /* If we are only performing a partial link do not bother
7526 to construct any glue. */
7527 if (bfd_link_relocatable (link_info))
7528 return TRUE;
7529
7530 /* Skip if this bfd does not correspond to an ELF image. */
7531 if (! is_arm_elf (abfd))
7532 return TRUE;
7533
7534 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
7535 return TRUE;
7536
7537 /* Skip this BFD if it corresponds to an executable or dynamic object. */
7538 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
7539 return TRUE;
7540
7541 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7542 {
7543 unsigned int i, span;
7544 struct _arm_elf_section_data *sec_data;
7545
7546 /* If we don't have executable progbits, we're not interested in this
7547 section. Also skip if section is to be excluded. */
7548 if (elf_section_type (sec) != SHT_PROGBITS
7549 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
7550 || (sec->flags & SEC_EXCLUDE) != 0
7551 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
7552 || sec->output_section == bfd_abs_section_ptr
7553 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
7554 continue;
7555
7556 sec_data = elf32_arm_section_data (sec);
c7b8f16e 7557
a504d23a
LA		 7558 if (sec_data->mapcount == 0)
7559 continue;
c7b8f16e 7560
a504d23a
LA		 7561 if (elf_section_data (sec)->this_hdr.contents != NULL)
7562 contents = elf_section_data (sec)->this_hdr.contents;
7563 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
7564 goto error_return;
c7b8f16e 7565
a504d23a
LA		 7566 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
7567 elf32_arm_compare_mapping);
c7b8f16e 7568
a504d23a
LA		 7569 for (span = 0; span < sec_data->mapcount; span++)
7570 {
7571 unsigned int span_start = sec_data->map[span].vma;
7572 unsigned int span_end = (span == sec_data->mapcount - 1)
7573 ? sec->size : sec_data->map[span + 1].vma;
7574 char span_type = sec_data->map[span].type;
7575 int itblock_current_pos = 0;
c7b8f16e 7576
a504d23a
LA		 7577 /* Only Thumb2 mode need be supported with this CM4 specific
7578 code, we should not encounter any arm mode eg span_type
7579 != 'a'. */
7580 if (span_type != 't')
7581 continue;
c7b8f16e 7582
a504d23a
LA		 7583 for (i = span_start; i < span_end;)
7584 {
7585 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
7586 bfd_boolean insn_32bit = FALSE;
7587 bfd_boolean is_ldm = FALSE;
7588 bfd_boolean is_vldm = FALSE;
7589 bfd_boolean is_not_last_in_it_block = FALSE;
7590
7591 /* The first 16-bits of all 32-bit thumb2 instructions start
7592 with opcode[15..13]=0b111 and the encoded op1 can be anything
7593 except opcode[12..11]!=0b00.
7594 See 32-bit Thumb instruction encoding. */
7595 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
7596 insn_32bit = TRUE;
c7b8f16e 7597
a504d23a
LA		 7598 /* Compute the predicate that tells if the instruction
7599 is concerned by the IT block
7600 - Creates an error if there is a ldm that is not
7601 last in the IT block thus cannot be replaced
7602 - Otherwise we can create a branch at the end of the
7603 IT block, it will be controlled naturally by IT
7604 with the proper pseudo-predicate
7605 - So the only interesting predicate is the one that
7606 tells that we are not on the last item of an IT
7607 block. */
7608 if (itblock_current_pos != 0)
7609 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 7610
a504d23a
LA		 7611 if (insn_32bit)
7612 {
7613 /* Load the rest of the insn (in manual-friendly order). */
7614 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
7615 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
7616 is_vldm = is_thumb2_vldm (insn);
7617
7618 /* Veneers are created for (v)ldm depending on
7619 option flags and memory accesses conditions; but
7620 if the instruction is not the last instruction of
7621 an IT block, we cannot create a jump there, so we
7622 bail out. */
7623 if ((is_ldm || is_vldm) &&
7624 stm32l4xx_need_create_replacing_stub
7625 (insn, globals->stm32l4xx_fix))
7626 {
7627 if (is_not_last_in_it_block)
7628 {
7629 (*_bfd_error_handler)
7630 /* Note - overlong line used here to allow for translation. */
7631 (_("\
7632%B(%A+0x%lx): error: multiple load detected in non-last IT block instruction : STM32L4XX veneer cannot be generated.\n"
7633 "Use gcc option -mrestrict-it to generate only one instruction per IT block.\n"),
7634 abfd, sec, (long)i);
7635 }
7636 else
7637 {
7638 elf32_stm32l4xx_erratum_list *newerr =
7639 (elf32_stm32l4xx_erratum_list *)
7640 bfd_zmalloc
7641 (sizeof (elf32_stm32l4xx_erratum_list));
7642
7643 elf32_arm_section_data (sec)
7644 ->stm32l4xx_erratumcount += 1;
7645 newerr->u.b.insn = insn;
7646 /* We create only thumb branches. */
7647 newerr->type =
7648 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
7649 record_stm32l4xx_erratum_veneer
7650 (link_info, newerr, abfd, sec,
7651 i,
7652 is_ldm ?
7653 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
7654 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
7655 newerr->vma = -1;
7656 newerr->next = sec_data->stm32l4xx_erratumlist;
7657 sec_data->stm32l4xx_erratumlist = newerr;
7658 }
7659 }
7660 }
7661 else
7662 {
7663 /* A7.7.37 IT p208
7664 IT blocks are only encoded in T1
7665 Encoding T1: IT{x{y{z}}} <firstcond>
7666 1 0 1 1 - 1 1 1 1 - firstcond - mask
7667 if mask = '0000' then see 'related encodings'
7668 We don't deal with UNPREDICTABLE, just ignore these.
7669 There can be no nested IT blocks so an IT block
7670 is naturally a new one for which it is worth
7671 computing its size. */
7672 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00) &&
7673 ((insn & 0x000f) != 0x0000);
7674 /* If we have a new IT block we compute its size. */
7675 if (is_newitblock)
7676 {
7677 /* Compute the number of instructions controlled
7678 by the IT block, it will be used to decide
7679 whether we are inside an IT block or not. */
7680 unsigned int mask = insn & 0x000f;
7681 itblock_current_pos = 4 - ctz (mask);
7682 }
7683 }
7684
7685 i += insn_32bit ? 4 : 2;
99059e56
RM		 7686 }
7687 }
a504d23a
LA		 7688
7689 if (contents != NULL
7690 && elf_section_data (sec)->this_hdr.contents != contents)
7691 free (contents);
7692 contents = NULL;
c7b8f16e 7693 }
906e58ca 7694
a504d23a
LA		 7695 return TRUE;
7696
7697error_return:
7698 if (contents != NULL
7699 && elf_section_data (sec)->this_hdr.contents != contents)
7700 free (contents);
c7b8f16e 7701
a504d23a
LA		 7702 return FALSE;
7703}
c7b8f16e 7704
eb043451
PB		 7705/* Set target relocation values needed during linking. */
7706
7707void
bf21ed78
MS		 7708bfd_elf32_arm_set_target_relocs (struct bfd *output_bfd,
7709 struct bfd_link_info *link_info,
eb043451 7710 int target1_is_rel,
319850b4 7711 char * target2_type,
99059e56 7712 int fix_v4bx,
c7b8f16e 7713 int use_blx,
99059e56 7714 bfd_arm_vfp11_fix vfp11_fix,
a504d23a 7715 bfd_arm_stm32l4xx_fix stm32l4xx_fix,
a9dc9481 7716 int no_enum_warn, int no_wchar_warn,
2de70689
MGD		 7717 int pic_veneer, int fix_cortex_a8,
7718 int fix_arm1176)
eb043451
PB		 7719{
7720 struct elf32_arm_link_hash_table *globals;
7721
7722 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7723 if (globals == NULL)
7724 return;
eb043451
PB		 7725
7726 globals->target1_is_rel = target1_is_rel;
7727 if (strcmp (target2_type, "rel") == 0)
7728 globals->target2_reloc = R_ARM_REL32;
eeac373a
PB		 7729 else if (strcmp (target2_type, "abs") == 0)
7730 globals->target2_reloc = R_ARM_ABS32;
eb043451
PB		 7731 else if (strcmp (target2_type, "got-rel") == 0)
7732 globals->target2_reloc = R_ARM_GOT_PREL;
7733 else
7734 {
7735 _bfd_error_handler (_("Invalid TARGET2 relocation type '%s'."),
7736 target2_type);
7737 }
319850b4 7738 globals->fix_v4bx = fix_v4bx;
33bfe774 7739 globals->use_blx |= use_blx;
c7b8f16e 7740 globals->vfp11_fix = vfp11_fix;
a504d23a 7741 globals->stm32l4xx_fix = stm32l4xx_fix;
27e55c4d 7742 globals->pic_veneer = pic_veneer;
48229727 7743 globals->fix_cortex_a8 = fix_cortex_a8;
2de70689 7744 globals->fix_arm1176 = fix_arm1176;
bf21ed78 7745
0ffa91dd
NC		 7746 BFD_ASSERT (is_arm_elf (output_bfd));
7747 elf_arm_tdata (output_bfd)->no_enum_size_warning = no_enum_warn;
a9dc9481 7748 elf_arm_tdata (output_bfd)->no_wchar_size_warning = no_wchar_warn;
eb043451 7749}
eb043451 7750
12a0a0fd 7751/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 7752
12a0a0fd
PB		 7753static void
7754insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
7755{
7756 bfd_vma upper;
7757 bfd_vma lower;
7758 int reloc_sign;
7759
7760 BFD_ASSERT ((offset & 1) == 0);
7761
7762 upper = bfd_get_16 (abfd, insn);
7763 lower = bfd_get_16 (abfd, insn + 2);
7764 reloc_sign = (offset < 0) ? 1 : 0;
7765 upper = (upper & ~(bfd_vma) 0x7ff)
7766 | ((offset >> 12) & 0x3ff)
7767 | (reloc_sign << 10);
906e58ca 7768 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 7769 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
7770 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
7771 | ((offset >> 1) & 0x7ff);
7772 bfd_put_16 (abfd, upper, insn);
7773 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 7774}
7775
9b485d32
NC		 7776/* Thumb code calling an ARM function. */
7777
252b5132 7778static int
57e8b36a
NC		 7779elf32_thumb_to_arm_stub (struct bfd_link_info * info,
7780 const char * name,
7781 bfd * input_bfd,
7782 bfd * output_bfd,
7783 asection * input_section,
7784 bfd_byte * hit_data,
7785 asection * sym_sec,
7786 bfd_vma offset,
7787 bfd_signed_vma addend,
f2a9dd69
DJ		 7788 bfd_vma val,
7789 char **error_message)
252b5132 7790{
bcbdc74c 7791 asection * s = 0;
dc810e39 7792 bfd_vma my_offset;
252b5132 7793 long int ret_offset;
bcbdc74c
NC		 7794 struct elf_link_hash_entry * myh;
7795 struct elf32_arm_link_hash_table * globals;
252b5132 7796
f2a9dd69 7797 myh = find_thumb_glue (info, name, error_message);
252b5132 7798 if (myh == NULL)
b34976b6 7799 return FALSE;
252b5132
RH		 7800
7801 globals = elf32_arm_hash_table (info);
252b5132
RH		 7802 BFD_ASSERT (globals != NULL);
7803 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7804
7805 my_offset = myh->root.u.def.value;
7806
3d4d4302
AM		 7807 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
7808 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 7809
7810 BFD_ASSERT (s != NULL);
7811 BFD_ASSERT (s->contents != NULL);
7812 BFD_ASSERT (s->output_section != NULL);
7813
7814 if ((my_offset & 0x01) == 0x01)
7815 {
7816 if (sym_sec != NULL
7817 && sym_sec->owner != NULL
7818 && !INTERWORK_FLAG (sym_sec->owner))
7819 {
8f615d07 7820 (*_bfd_error_handler)
d003868e 7821 (_("%B(%s): warning: interworking not enabled.\n"
3aaeb7d3 7822 " first occurrence: %B: Thumb call to ARM"),
d003868e 7823 sym_sec->owner, input_bfd, name);
252b5132 7824
b34976b6 7825 return FALSE;
252b5132
RH		 7826 }
7827
7828 --my_offset;
7829 myh->root.u.def.value = my_offset;
7830
52ab56c2
PB		 7831 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
7832 s->contents + my_offset);
252b5132 7833
52ab56c2
PB		 7834 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
7835 s->contents + my_offset + 2);
252b5132
RH		 7836
7837 ret_offset =
9b485d32
NC		 7838 /* Address of destination of the stub. */
7839 ((bfd_signed_vma) val)
252b5132 7840 - ((bfd_signed_vma)
57e8b36a
NC		 7841 /* Offset from the start of the current section
7842 to the start of the stubs. */
9b485d32
NC		 7843 (s->output_offset
7844 /* Offset of the start of this stub from the start of the stubs. */
7845 + my_offset
7846 /* Address of the start of the current section. */
7847 + s->output_section->vma)
7848 /* The branch instruction is 4 bytes into the stub. */
7849 + 4
7850 /* ARM branches work from the pc of the instruction + 8. */
7851 + 8);
252b5132 7852
52ab56c2
PB		 7853 put_arm_insn (globals, output_bfd,
7854 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
7855 s->contents + my_offset + 4);
252b5132
RH		 7856 }
7857
7858 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
7859
427bfd90
NC		 7860 /* Now go back and fix up the original BL insn to point to here. */
7861 ret_offset =
7862 /* Address of where the stub is located. */
7863 (s->output_section->vma + s->output_offset + my_offset)
7864 /* Address of where the BL is located. */
57e8b36a
NC		 7865 - (input_section->output_section->vma + input_section->output_offset
7866 + offset)
427bfd90
NC		 7867 /* Addend in the relocation. */
7868 - addend
7869 /* Biassing for PC-relative addressing. */
7870 - 8;
252b5132 7871
12a0a0fd 7872 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 7873
b34976b6 7874 return TRUE;
252b5132
RH		 7875}
7876
a4fd1a8e 7877/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 7878
a4fd1a8e
PB		 7879static struct elf_link_hash_entry *
7880elf32_arm_create_thumb_stub (struct bfd_link_info * info,
7881 const char * name,
7882 bfd * input_bfd,
7883 bfd * output_bfd,
7884 asection * sym_sec,
7885 bfd_vma val,
8029a119
NC		 7886 asection * s,
7887 char ** error_message)
252b5132 7888{
dc810e39 7889 bfd_vma my_offset;
252b5132 7890 long int ret_offset;
bcbdc74c
NC		 7891 struct elf_link_hash_entry * myh;
7892 struct elf32_arm_link_hash_table * globals;
252b5132 7893
f2a9dd69 7894 myh = find_arm_glue (info, name, error_message);
252b5132 7895 if (myh == NULL)
a4fd1a8e 7896 return NULL;
252b5132
RH		 7897
7898 globals = elf32_arm_hash_table (info);
252b5132
RH		 7899 BFD_ASSERT (globals != NULL);
7900 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7901
7902 my_offset = myh->root.u.def.value;
252b5132
RH		 7903
7904 if ((my_offset & 0x01) == 0x01)
7905 {
7906 if (sym_sec != NULL
7907 && sym_sec->owner != NULL
7908 && !INTERWORK_FLAG (sym_sec->owner))
7909 {
8f615d07 7910 (*_bfd_error_handler)
d003868e
AM		 7911 (_("%B(%s): warning: interworking not enabled.\n"
7912 " first occurrence: %B: arm call to thumb"),
7913 sym_sec->owner, input_bfd, name);
252b5132 7914 }
9b485d32 7915
252b5132
RH		 7916 --my_offset;
7917 myh->root.u.def.value = my_offset;
7918
0e1862bb
L		 7919 if (bfd_link_pic (info)
7920 || globals->root.is_relocatable_executable
27e55c4d 7921 || globals->pic_veneer)
8f6277f5
PB		 7922 {
7923 /* For relocatable objects we can't use absolute addresses,
7924 so construct the address from a relative offset. */
7925 /* TODO: If the offset is small it's probably worth
7926 constructing the address with adds. */
52ab56c2
PB		 7927 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
7928 s->contents + my_offset);
7929 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
7930 s->contents + my_offset + 4);
7931 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
7932 s->contents + my_offset + 8);
8f6277f5
PB		 7933 /* Adjust the offset by 4 for the position of the add,
7934 and 8 for the pipeline offset. */
7935 ret_offset = (val - (s->output_offset
7936 + s->output_section->vma
7937 + my_offset + 12))
7938 | 1;
7939 bfd_put_32 (output_bfd, ret_offset,
7940 s->contents + my_offset + 12);
7941 }
26079076
PB		 7942 else if (globals->use_blx)
7943 {
7944 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
7945 s->contents + my_offset);
7946
7947 /* It's a thumb address. Add the low order bit. */
7948 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
7949 s->contents + my_offset + 4);
7950 }
8f6277f5
PB		 7951 else
7952 {
52ab56c2
PB		 7953 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
7954 s->contents + my_offset);
252b5132 7955
52ab56c2
PB		 7956 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
7957 s->contents + my_offset + 4);
252b5132 7958
8f6277f5
PB		 7959 /* It's a thumb address. Add the low order bit. */
7960 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
7961 s->contents + my_offset + 8);
8029a119
NC		 7962
7963 my_offset += 12;
8f6277f5 7964 }
252b5132
RH		 7965 }
7966
7967 BFD_ASSERT (my_offset <= globals->arm_glue_size);
7968
a4fd1a8e
PB		 7969 return myh;
7970}
7971
7972/* Arm code calling a Thumb function. */
7973
7974static int
7975elf32_arm_to_thumb_stub (struct bfd_link_info * info,
7976 const char * name,
7977 bfd * input_bfd,
7978 bfd * output_bfd,
7979 asection * input_section,
7980 bfd_byte * hit_data,
7981 asection * sym_sec,
7982 bfd_vma offset,
7983 bfd_signed_vma addend,
f2a9dd69
DJ		 7984 bfd_vma val,
7985 char **error_message)
a4fd1a8e
PB		 7986{
7987 unsigned long int tmp;
7988 bfd_vma my_offset;
7989 asection * s;
7990 long int ret_offset;
7991 struct elf_link_hash_entry * myh;
7992 struct elf32_arm_link_hash_table * globals;
7993
7994 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 7995 BFD_ASSERT (globals != NULL);
7996 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7997
3d4d4302
AM		 7998 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
7999 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8000 BFD_ASSERT (s != NULL);
8001 BFD_ASSERT (s->contents != NULL);
8002 BFD_ASSERT (s->output_section != NULL);
8003
8004 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 8005 sym_sec, val, s, error_message);
a4fd1a8e
PB		 8006 if (!myh)
8007 return FALSE;
8008
8009 my_offset = myh->root.u.def.value;
252b5132
RH		 8010 tmp = bfd_get_32 (input_bfd, hit_data);
8011 tmp = tmp & 0xFF000000;
8012
9b485d32 8013 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 8014 ret_offset = (s->output_offset
8015 + my_offset
8016 + s->output_section->vma
8017 - (input_section->output_offset
8018 + input_section->output_section->vma
8019 + offset + addend)
8020 - 8);
9a5aca8c 8021
252b5132
RH		 8022 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
8023
dc810e39 8024 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 8025
b34976b6 8026 return TRUE;
252b5132
RH		 8027}
8028
a4fd1a8e
PB		 8029/* Populate Arm stub for an exported Thumb function. */
8030
8031static bfd_boolean
8032elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
8033{
8034 struct bfd_link_info * info = (struct bfd_link_info *) inf;
8035 asection * s;
8036 struct elf_link_hash_entry * myh;
8037 struct elf32_arm_link_hash_entry *eh;
8038 struct elf32_arm_link_hash_table * globals;
8039 asection *sec;
8040 bfd_vma val;
f2a9dd69 8041 char *error_message;
a4fd1a8e 8042
906e58ca 8043 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 8044 /* Allocate stubs for exported Thumb functions on v4t. */
8045 if (eh->export_glue == NULL)
8046 return TRUE;
8047
8048 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8049 BFD_ASSERT (globals != NULL);
8050 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8051
3d4d4302
AM		 8052 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8053 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8054 BFD_ASSERT (s != NULL);
8055 BFD_ASSERT (s->contents != NULL);
8056 BFD_ASSERT (s->output_section != NULL);
8057
8058 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 8059
8060 BFD_ASSERT (sec->output_section != NULL);
8061
a4fd1a8e
PB		 8062 val = eh->export_glue->root.u.def.value + sec->output_offset
8063 + sec->output_section->vma;
8029a119 8064
a4fd1a8e
PB		 8065 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
8066 h->root.u.def.section->owner,
f2a9dd69
DJ		 8067 globals->obfd, sec, val, s,
8068 &error_message);
a4fd1a8e
PB		 8069 BFD_ASSERT (myh);
8070 return TRUE;
8071}
8072
845b51d6
PB		 8073/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
8074
8075static bfd_vma
8076elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
8077{
8078 bfd_byte *p;
8079 bfd_vma glue_addr;
8080 asection *s;
8081 struct elf32_arm_link_hash_table *globals;
8082
8083 globals = elf32_arm_hash_table (info);
845b51d6
PB		 8084 BFD_ASSERT (globals != NULL);
8085 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8086
3d4d4302
AM		 8087 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8088 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 8089 BFD_ASSERT (s != NULL);
8090 BFD_ASSERT (s->contents != NULL);
8091 BFD_ASSERT (s->output_section != NULL);
8092
8093 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
8094
8095 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
8096
8097 if ((globals->bx_glue_offset[reg] & 1) == 0)
8098 {
8099 p = s->contents + glue_addr;
8100 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
8101 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
8102 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
8103 globals->bx_glue_offset[reg] |= 1;
8104 }
8105
8106 return glue_addr + s->output_section->vma + s->output_offset;
8107}
8108
a4fd1a8e
PB		 8109/* Generate Arm stubs for exported Thumb symbols. */
8110static void
906e58ca 8111elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 8112 struct bfd_link_info *link_info)
8113{
8114 struct elf32_arm_link_hash_table * globals;
8115
8029a119
NC		 8116 if (link_info == NULL)
8117 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 8118 return;
8119
8120 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8121 if (globals == NULL)
8122 return;
8123
84c08195
PB		 8124 /* If blx is available then exported Thumb symbols are OK and there is
8125 nothing to do. */
a4fd1a8e
PB		 8126 if (globals->use_blx)
8127 return;
8128
8129 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
8130 link_info);
8131}
8132
47beaa6a
RS		 8133/* Reserve space for COUNT dynamic relocations in relocation selection
8134 SRELOC. */
8135
8136static void
8137elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
8138 bfd_size_type count)
8139{
8140 struct elf32_arm_link_hash_table *htab;
8141
8142 htab = elf32_arm_hash_table (info);
8143 BFD_ASSERT (htab->root.dynamic_sections_created);
8144 if (sreloc == NULL)
8145 abort ();
8146 sreloc->size += RELOC_SIZE (htab) * count;
8147}
8148
34e77a92
RS		 8149/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
8150 dynamic, the relocations should go in SRELOC, otherwise they should
8151 go in the special .rel.iplt section. */
8152
8153static void
8154elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
8155 bfd_size_type count)
8156{
8157 struct elf32_arm_link_hash_table *htab;
8158
8159 htab = elf32_arm_hash_table (info);
8160 if (!htab->root.dynamic_sections_created)
8161 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
8162 else
8163 {
8164 BFD_ASSERT (sreloc != NULL);
8165 sreloc->size += RELOC_SIZE (htab) * count;
8166 }
8167}
8168
47beaa6a
RS		 8169/* Add relocation REL to the end of relocation section SRELOC. */
8170
8171static void
8172elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
8173 asection *sreloc, Elf_Internal_Rela *rel)
8174{
8175 bfd_byte *loc;
8176 struct elf32_arm_link_hash_table *htab;
8177
8178 htab = elf32_arm_hash_table (info);
34e77a92
RS		 8179 if (!htab->root.dynamic_sections_created
8180 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
8181 sreloc = htab->root.irelplt;
47beaa6a
RS		 8182 if (sreloc == NULL)
8183 abort ();
8184 loc = sreloc->contents;
8185 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
8186 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
8187 abort ();
8188 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
8189}
8190
34e77a92
RS		 8191/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
8192 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
8193 to .plt. */
8194
8195static void
8196elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
8197 bfd_boolean is_iplt_entry,
8198 union gotplt_union *root_plt,
8199 struct arm_plt_info *arm_plt)
8200{
8201 struct elf32_arm_link_hash_table *htab;
8202 asection *splt;
8203 asection *sgotplt;
8204
8205 htab = elf32_arm_hash_table (info);
8206
8207 if (is_iplt_entry)
8208 {
8209 splt = htab->root.iplt;
8210 sgotplt = htab->root.igotplt;
8211
99059e56
RM		 8212 /* NaCl uses a special first entry in .iplt too. */
8213 if (htab->nacl_p && splt->size == 0)
8214 splt->size += htab->plt_header_size;
8215
34e77a92
RS		 8216 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
8217 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
8218 }
8219 else
8220 {
8221 splt = htab->root.splt;
8222 sgotplt = htab->root.sgotplt;
8223
8224 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
8225 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
8226
8227 /* If this is the first .plt entry, make room for the special
8228 first entry. */
8229 if (splt->size == 0)
8230 splt->size += htab->plt_header_size;
9f19ab6d
WN		 8231
8232 htab->next_tls_desc_index++;
34e77a92
RS		 8233 }
8234
8235 /* Allocate the PLT entry itself, including any leading Thumb stub. */
8236 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
8237 splt->size += PLT_THUMB_STUB_SIZE;
8238 root_plt->offset = splt->size;
8239 splt->size += htab->plt_entry_size;
8240
8241 if (!htab->symbian_p)
8242 {
8243 /* We also need to make an entry in the .got.plt section, which
8244 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 8245 if (is_iplt_entry)
8246 arm_plt->got_offset = sgotplt->size;
8247 else
8248 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 8249 sgotplt->size += 4;
8250 }
8251}
8252
b38cadfb
NC		 8253static bfd_vma
8254arm_movw_immediate (bfd_vma value)
8255{
8256 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
8257}
8258
8259static bfd_vma
8260arm_movt_immediate (bfd_vma value)
8261{
8262 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
8263}
8264
34e77a92
RS		 8265/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
8266 the entry lives in .iplt and resolves to (*SYM_VALUE)().
8267 Otherwise, DYNINDX is the index of the symbol in the dynamic
8268 symbol table and SYM_VALUE is undefined.
8269
8270 ROOT_PLT points to the offset of the PLT entry from the start of its
8271 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 8272 bookkeeping information.
34e77a92 8273
57460bcf
NC		 8274 Returns FALSE if there was a problem. */
8275
8276static bfd_boolean
34e77a92
RS		 8277elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
8278 union gotplt_union *root_plt,
8279 struct arm_plt_info *arm_plt,
8280 int dynindx, bfd_vma sym_value)
8281{
8282 struct elf32_arm_link_hash_table *htab;
8283 asection *sgot;
8284 asection *splt;
8285 asection *srel;
8286 bfd_byte *loc;
8287 bfd_vma plt_index;
8288 Elf_Internal_Rela rel;
8289 bfd_vma plt_header_size;
8290 bfd_vma got_header_size;
8291
8292 htab = elf32_arm_hash_table (info);
8293
8294 /* Pick the appropriate sections and sizes. */
8295 if (dynindx == -1)
8296 {
8297 splt = htab->root.iplt;
8298 sgot = htab->root.igotplt;
8299 srel = htab->root.irelplt;
8300
8301 /* There are no reserved entries in .igot.plt, and no special
8302 first entry in .iplt. */
8303 got_header_size = 0;
8304 plt_header_size = 0;
8305 }
8306 else
8307 {
8308 splt = htab->root.splt;
8309 sgot = htab->root.sgotplt;
8310 srel = htab->root.srelplt;
8311
8312 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
8313 plt_header_size = htab->plt_header_size;
8314 }
8315 BFD_ASSERT (splt != NULL && srel != NULL);
8316
8317 /* Fill in the entry in the procedure linkage table. */
8318 if (htab->symbian_p)
8319 {
8320 BFD_ASSERT (dynindx >= 0);
8321 put_arm_insn (htab, output_bfd,
8322 elf32_arm_symbian_plt_entry[0],
8323 splt->contents + root_plt->offset);
8324 bfd_put_32 (output_bfd,
8325 elf32_arm_symbian_plt_entry[1],
8326 splt->contents + root_plt->offset + 4);
8327
8328 /* Fill in the entry in the .rel.plt section. */
8329 rel.r_offset = (splt->output_section->vma
8330 + splt->output_offset
8331 + root_plt->offset + 4);
8332 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
8333
8334 /* Get the index in the procedure linkage table which
8335 corresponds to this symbol. This is the index of this symbol
8336 in all the symbols for which we are making plt entries. The
8337 first entry in the procedure linkage table is reserved. */
8338 plt_index = ((root_plt->offset - plt_header_size)
8339 / htab->plt_entry_size);
8340 }
8341 else
8342 {
8343 bfd_vma got_offset, got_address, plt_address;
8344 bfd_vma got_displacement, initial_got_entry;
8345 bfd_byte * ptr;
8346
8347 BFD_ASSERT (sgot != NULL);
8348
8349 /* Get the offset into the .(i)got.plt table of the entry that
8350 corresponds to this function. */
8351 got_offset = (arm_plt->got_offset & -2);
8352
8353 /* Get the index in the procedure linkage table which
8354 corresponds to this symbol. This is the index of this symbol
8355 in all the symbols for which we are making plt entries.
8356 After the reserved .got.plt entries, all symbols appear in
8357 the same order as in .plt. */
8358 plt_index = (got_offset - got_header_size) / 4;
8359
8360 /* Calculate the address of the GOT entry. */
8361 got_address = (sgot->output_section->vma
8362 + sgot->output_offset
8363 + got_offset);
8364
8365 /* ...and the address of the PLT entry. */
8366 plt_address = (splt->output_section->vma
8367 + splt->output_offset
8368 + root_plt->offset);
8369
8370 ptr = splt->contents + root_plt->offset;
0e1862bb 8371 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 8372 {
8373 unsigned int i;
8374 bfd_vma val;
8375
8376 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
8377 {
8378 val = elf32_arm_vxworks_shared_plt_entry[i];
8379 if (i == 2)
8380 val |= got_address - sgot->output_section->vma;
8381 if (i == 5)
8382 val |= plt_index * RELOC_SIZE (htab);
8383 if (i == 2 || i == 5)
8384 bfd_put_32 (output_bfd, val, ptr);
8385 else
8386 put_arm_insn (htab, output_bfd, val, ptr);
8387 }
8388 }
8389 else if (htab->vxworks_p)
8390 {
8391 unsigned int i;
8392 bfd_vma val;
8393
8394 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
8395 {
8396 val = elf32_arm_vxworks_exec_plt_entry[i];
8397 if (i == 2)
8398 val |= got_address;
8399 if (i == 4)
8400 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
8401 if (i == 5)
8402 val |= plt_index * RELOC_SIZE (htab);
8403 if (i == 2 || i == 5)
8404 bfd_put_32 (output_bfd, val, ptr);
8405 else
8406 put_arm_insn (htab, output_bfd, val, ptr);
8407 }
8408
8409 loc = (htab->srelplt2->contents
8410 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
8411
8412 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
8413 referencing the GOT for this PLT entry. */
8414 rel.r_offset = plt_address + 8;
8415 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
8416 rel.r_addend = got_offset;
8417 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8418 loc += RELOC_SIZE (htab);
8419
8420 /* Create the R_ARM_ABS32 relocation referencing the
8421 beginning of the PLT for this GOT entry. */
8422 rel.r_offset = got_address;
8423 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
8424 rel.r_addend = 0;
8425 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8426 }
b38cadfb
NC		 8427 else if (htab->nacl_p)
8428 {
8429 /* Calculate the displacement between the PLT slot and the
8430 common tail that's part of the special initial PLT slot. */
6034aab8 8431 int32_t tail_displacement
b38cadfb
NC		 8432 = ((splt->output_section->vma + splt->output_offset
8433 + ARM_NACL_PLT_TAIL_OFFSET)
8434 - (plt_address + htab->plt_entry_size + 4));
8435 BFD_ASSERT ((tail_displacement & 3) == 0);
8436 tail_displacement >>= 2;
8437
8438 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
8439 || (-tail_displacement & 0xff000000) == 0);
8440
8441 /* Calculate the displacement between the PLT slot and the entry
8442 in the GOT. The offset accounts for the value produced by
8443 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 8444 got_displacement = (got_address
99059e56 8445 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 8446
8447 /* NaCl does not support interworking at all. */
8448 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
8449
8450 put_arm_insn (htab, output_bfd,
8451 elf32_arm_nacl_plt_entry[0]
8452 | arm_movw_immediate (got_displacement),
8453 ptr + 0);
8454 put_arm_insn (htab, output_bfd,
8455 elf32_arm_nacl_plt_entry[1]
8456 | arm_movt_immediate (got_displacement),
8457 ptr + 4);
8458 put_arm_insn (htab, output_bfd,
8459 elf32_arm_nacl_plt_entry[2],
8460 ptr + 8);
8461 put_arm_insn (htab, output_bfd,
8462 elf32_arm_nacl_plt_entry[3]
8463 | (tail_displacement & 0x00ffffff),
8464 ptr + 12);
8465 }
57460bcf
NC		 8466 else if (using_thumb_only (htab))
8467 {
eed94f8f 8468 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 8469 if (!using_thumb2 (htab))
eed94f8f
NC		 8470 {
8471 /* FIXME: We ought to be able to generate thumb-1 PLT
8472 instructions... */
8473 _bfd_error_handler (_("%B: Warning: thumb-1 mode PLT generation not currently supported"),
8474 output_bfd);
8475 return FALSE;
8476 }
57460bcf 8477
eed94f8f
NC		 8478 /* Calculate the displacement between the PLT slot and the entry in
8479 the GOT. The 12-byte offset accounts for the value produced by
8480 adding to pc in the 3rd instruction of the PLT stub. */
8481 got_displacement = got_address - (plt_address + 12);
8482
8483 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
8484 instead of 'put_thumb_insn'. */
8485 put_arm_insn (htab, output_bfd,
8486 elf32_thumb2_plt_entry[0]
8487 | ((got_displacement & 0x000000ff) << 16)
8488 | ((got_displacement & 0x00000700) << 20)
8489 | ((got_displacement & 0x00000800) >> 1)
8490 | ((got_displacement & 0x0000f000) >> 12),
8491 ptr + 0);
8492 put_arm_insn (htab, output_bfd,
8493 elf32_thumb2_plt_entry[1]
8494 | ((got_displacement & 0x00ff0000) )
8495 | ((got_displacement & 0x07000000) << 4)
8496 | ((got_displacement & 0x08000000) >> 17)
8497 | ((got_displacement & 0xf0000000) >> 28),
8498 ptr + 4);
8499 put_arm_insn (htab, output_bfd,
8500 elf32_thumb2_plt_entry[2],
8501 ptr + 8);
8502 put_arm_insn (htab, output_bfd,
8503 elf32_thumb2_plt_entry[3],
8504 ptr + 12);
57460bcf 8505 }
34e77a92
RS		 8506 else
8507 {
8508 /* Calculate the displacement between the PLT slot and the
8509 entry in the GOT. The eight-byte offset accounts for the
8510 value produced by adding to pc in the first instruction
8511 of the PLT stub. */
8512 got_displacement = got_address - (plt_address + 8);
8513
34e77a92
RS		 8514 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
8515 {
8516 put_thumb_insn (htab, output_bfd,
8517 elf32_arm_plt_thumb_stub[0], ptr - 4);
8518 put_thumb_insn (htab, output_bfd,
8519 elf32_arm_plt_thumb_stub[1], ptr - 2);
8520 }
8521
1db37fe6
YG		 8522 if (!elf32_arm_use_long_plt_entry)
8523 {
8524 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
8525
8526 put_arm_insn (htab, output_bfd,
8527 elf32_arm_plt_entry_short[0]
8528 | ((got_displacement & 0x0ff00000) >> 20),
8529 ptr + 0);
8530 put_arm_insn (htab, output_bfd,
8531 elf32_arm_plt_entry_short[1]
8532 | ((got_displacement & 0x000ff000) >> 12),
8533 ptr+ 4);
8534 put_arm_insn (htab, output_bfd,
8535 elf32_arm_plt_entry_short[2]
8536 | (got_displacement & 0x00000fff),
8537 ptr + 8);
34e77a92 8538#ifdef FOUR_WORD_PLT
1db37fe6 8539 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 8540#endif
1db37fe6
YG		 8541 }
8542 else
8543 {
8544 put_arm_insn (htab, output_bfd,
8545 elf32_arm_plt_entry_long[0]
8546 | ((got_displacement & 0xf0000000) >> 28),
8547 ptr + 0);
8548 put_arm_insn (htab, output_bfd,
8549 elf32_arm_plt_entry_long[1]
8550 | ((got_displacement & 0x0ff00000) >> 20),
8551 ptr + 4);
8552 put_arm_insn (htab, output_bfd,
8553 elf32_arm_plt_entry_long[2]
8554 | ((got_displacement & 0x000ff000) >> 12),
8555 ptr+ 8);
8556 put_arm_insn (htab, output_bfd,
8557 elf32_arm_plt_entry_long[3]
8558 | (got_displacement & 0x00000fff),
8559 ptr + 12);
8560 }
34e77a92
RS		 8561 }
8562
8563 /* Fill in the entry in the .rel(a).(i)plt section. */
8564 rel.r_offset = got_address;
8565 rel.r_addend = 0;
8566 if (dynindx == -1)
8567 {
8568 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
8569 The dynamic linker or static executable then calls SYM_VALUE
8570 to determine the correct run-time value of the .igot.plt entry. */
8571 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
8572 initial_got_entry = sym_value;
8573 }
8574 else
8575 {
8576 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
8577 initial_got_entry = (splt->output_section->vma
8578 + splt->output_offset);
8579 }
8580
8581 /* Fill in the entry in the global offset table. */
8582 bfd_put_32 (output_bfd, initial_got_entry,
8583 sgot->contents + got_offset);
8584 }
8585
aba8c3de
WN		 8586 if (dynindx == -1)
8587 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
8588 else
8589 {
8590 loc = srel->contents + plt_index * RELOC_SIZE (htab);
8591 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8592 }
57460bcf
NC		 8593
8594 return TRUE;
34e77a92
RS		 8595}
8596
eb043451
PB		 8597/* Some relocations map to different relocations depending on the
8598 target. Return the real relocation. */
8029a119 8599
eb043451
PB		 8600static int
8601arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
8602 int r_type)
8603{
8604 switch (r_type)
8605 {
8606 case R_ARM_TARGET1:
8607 if (globals->target1_is_rel)
8608 return R_ARM_REL32;
8609 else
8610 return R_ARM_ABS32;
8611
8612 case R_ARM_TARGET2:
8613 return globals->target2_reloc;
8614
8615 default:
8616 return r_type;
8617 }
8618}
eb043451 8619
ba93b8ac
DJ		 8620/* Return the base VMA address which should be subtracted from real addresses
8621 when resolving @dtpoff relocation.
8622 This is PT_TLS segment p_vaddr. */
8623
8624static bfd_vma
8625dtpoff_base (struct bfd_link_info *info)
8626{
8627 /* If tls_sec is NULL, we should have signalled an error already. */
8628 if (elf_hash_table (info)->tls_sec == NULL)
8629 return 0;
8630 return elf_hash_table (info)->tls_sec->vma;
8631}
8632
8633/* Return the relocation value for @tpoff relocation
8634 if STT_TLS virtual address is ADDRESS. */
8635
8636static bfd_vma
8637tpoff (struct bfd_link_info *info, bfd_vma address)
8638{
8639 struct elf_link_hash_table *htab = elf_hash_table (info);
8640 bfd_vma base;
8641
8642 /* If tls_sec is NULL, we should have signalled an error already. */
8643 if (htab->tls_sec == NULL)
8644 return 0;
8645 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
8646 return address - htab->tls_sec->vma + base;
8647}
8648
00a97672
RS		 8649/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
8650 VALUE is the relocation value. */
8651
8652static bfd_reloc_status_type
8653elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
8654{
8655 if (value > 0xfff)
8656 return bfd_reloc_overflow;
8657
8658 value |= bfd_get_32 (abfd, data) & 0xfffff000;
8659 bfd_put_32 (abfd, value, data);
8660 return bfd_reloc_ok;
8661}
8662
0855e32b
NS		 8663/* Handle TLS relaxations. Relaxing is possible for symbols that use
8664 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
8665 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
8666
8667 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
8668 is to then call final_link_relocate. Return other values in the
62672b10
NS		 8669 case of error.
8670
8671 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
8672 the pre-relaxed code. It would be nice if the relocs were updated
8673 to match the optimization. */
0855e32b 8674
b38cadfb 8675static bfd_reloc_status_type
0855e32b 8676elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 8677 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 8678 Elf_Internal_Rela *rel, unsigned long is_local)
8679{
8680 unsigned long insn;
b38cadfb 8681
0855e32b
NS		 8682 switch (ELF32_R_TYPE (rel->r_info))
8683 {
8684 default:
8685 return bfd_reloc_notsupported;
b38cadfb 8686
0855e32b
NS		 8687 case R_ARM_TLS_GOTDESC:
8688 if (is_local)
8689 insn = 0;
8690 else
8691 {
8692 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
8693 if (insn & 1)
8694 insn -= 5; /* THUMB */
8695 else
8696 insn -= 8; /* ARM */
8697 }
8698 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
8699 return bfd_reloc_continue;
8700
8701 case R_ARM_THM_TLS_DESCSEQ:
8702 /* Thumb insn. */
8703 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
8704 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
8705 {
8706 if (is_local)
8707 /* nop */
8708 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8709 }
8710 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
8711 {
8712 if (is_local)
8713 /* nop */
8714 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8715 else
8716 /* ldr rx,[ry] */
8717 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
8718 }
8719 else if ((insn & 0xff87) == 0x4780) /* blx rx */
8720 {
8721 if (is_local)
8722 /* nop */
8723 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8724 else
8725 /* mov r0, rx */
8726 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
8727 contents + rel->r_offset);
8728 }
8729 else
8730 {
8731 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
8732 /* It's a 32 bit instruction, fetch the rest of it for
8733 error generation. */
8734 insn = (insn << 16)
8735 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
8736 (*_bfd_error_handler)
8737 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' in TLS trampoline"),
8738 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
8739 return bfd_reloc_notsupported;
8740 }
8741 break;
b38cadfb 8742
0855e32b
NS		 8743 case R_ARM_TLS_DESCSEQ:
8744 /* arm insn. */
8745 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
8746 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
8747 {
8748 if (is_local)
8749 /* mov rx, ry */
8750 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
8751 contents + rel->r_offset);
8752 }
8753 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
8754 {
8755 if (is_local)
8756 /* nop */
8757 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
8758 else
8759 /* ldr rx,[ry] */
8760 bfd_put_32 (input_bfd, insn & 0xfffff000,
8761 contents + rel->r_offset);
8762 }
8763 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
8764 {
8765 if (is_local)
8766 /* nop */
8767 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
8768 else
8769 /* mov r0, rx */
8770 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
8771 contents + rel->r_offset);
8772 }
8773 else
8774 {
8775 (*_bfd_error_handler)
8776 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' in TLS trampoline"),
8777 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
8778 return bfd_reloc_notsupported;
8779 }
8780 break;
8781
8782 case R_ARM_TLS_CALL:
8783 /* GD->IE relaxation, turn the instruction into 'nop' or
8784 'ldr r0, [pc,r0]' */
8785 insn = is_local ? 0xe1a00000 : 0xe79f0000;
8786 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
8787 break;
b38cadfb 8788
0855e32b 8789 case R_ARM_THM_TLS_CALL:
6a631e86 8790 /* GD->IE relaxation. */
0855e32b
NS		 8791 if (!is_local)
8792 /* add r0,pc; ldr r0, [r0] */
8793 insn = 0x44786800;
8794 else if (arch_has_thumb2_nop (globals))
8795 /* nop.w */
8796 insn = 0xf3af8000;
8797 else
8798 /* nop; nop */
8799 insn = 0xbf00bf00;
b38cadfb 8800
0855e32b
NS		 8801 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
8802 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
8803 break;
8804 }
8805 return bfd_reloc_ok;
8806}
8807
4962c51a
MS		 8808/* For a given value of n, calculate the value of G_n as required to
8809 deal with group relocations. We return it in the form of an
8810 encoded constant-and-rotation, together with the final residual. If n is
8811 specified as less than zero, then final_residual is filled with the
8812 input value and no further action is performed. */
8813
8814static bfd_vma
8815calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
8816{
8817 int current_n;
8818 bfd_vma g_n;
8819 bfd_vma encoded_g_n = 0;
8820 bfd_vma residual = value; /* Also known as Y_n. */
8821
8822 for (current_n = 0; current_n <= n; current_n++)
8823 {
8824 int shift;
8825
8826 /* Calculate which part of the value to mask. */
8827 if (residual == 0)
99059e56 8828 shift = 0;
4962c51a 8829 else
99059e56
RM		 8830 {
8831 int msb;
8832
8833 /* Determine the most significant bit in the residual and
8834 align the resulting value to a 2-bit boundary. */
8835 for (msb = 30; msb >= 0; msb -= 2)
8836 if (residual & (3 << msb))
8837 break;
8838
8839 /* The desired shift is now (msb - 6), or zero, whichever
8840 is the greater. */
8841 shift = msb - 6;
8842 if (shift < 0)
8843 shift = 0;
8844 }
4962c51a
MS		 8845
8846 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
8847 g_n = residual & (0xff << shift);
8848 encoded_g_n = (g_n >> shift)
99059e56 8849 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 8850
8851 /* Calculate the residual for the next time around. */
8852 residual &= ~g_n;
8853 }
8854
8855 *final_residual = residual;
8856
8857 return encoded_g_n;
8858}
8859
8860/* Given an ARM instruction, determine whether it is an ADD or a SUB.
8861 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 8862
4962c51a 8863static int
906e58ca 8864identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 8865{
8866 int opcode = insn & 0x1e00000;
8867
8868 if (opcode == 1 << 23) /* ADD */
8869 return 1;
8870
8871 if (opcode == 1 << 22) /* SUB */
8872 return -1;
8873
8874 return 0;
8875}
8876
252b5132 8877/* Perform a relocation as part of a final link. */
9b485d32 8878
252b5132 8879static bfd_reloc_status_type
57e8b36a
NC		 8880elf32_arm_final_link_relocate (reloc_howto_type * howto,
8881 bfd * input_bfd,
8882 bfd * output_bfd,
8883 asection * input_section,
8884 bfd_byte * contents,
8885 Elf_Internal_Rela * rel,
8886 bfd_vma value,
8887 struct bfd_link_info * info,
8888 asection * sym_sec,
8889 const char * sym_name,
34e77a92
RS		 8890 unsigned char st_type,
8891 enum arm_st_branch_type branch_type,
0945cdfd 8892 struct elf_link_hash_entry * h,
f2a9dd69 8893 bfd_boolean * unresolved_reloc_p,
8029a119 8894 char ** error_message)
252b5132
RH		 8895{
8896 unsigned long r_type = howto->type;
8897 unsigned long r_symndx;
8898 bfd_byte * hit_data = contents + rel->r_offset;
252b5132 8899 bfd_vma * local_got_offsets;
0855e32b 8900 bfd_vma * local_tlsdesc_gotents;
34e77a92
RS		 8901 asection * sgot;
8902 asection * splt;
252b5132 8903 asection * sreloc = NULL;
362d30a1 8904 asection * srelgot;
252b5132 8905 bfd_vma addend;
ba96a88f 8906 bfd_signed_vma signed_addend;
34e77a92
RS		 8907 unsigned char dynreloc_st_type;
8908 bfd_vma dynreloc_value;
ba96a88f 8909 struct elf32_arm_link_hash_table * globals;
34e77a92
RS		 8910 struct elf32_arm_link_hash_entry *eh;
8911 union gotplt_union *root_plt;
8912 struct arm_plt_info *arm_plt;
8913 bfd_vma plt_offset;
8914 bfd_vma gotplt_offset;
8915 bfd_boolean has_iplt_entry;
f21f3fe0 8916
9c504268 8917 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 8918 if (globals == NULL)
8919 return bfd_reloc_notsupported;
9c504268 8920
0ffa91dd
NC		 8921 BFD_ASSERT (is_arm_elf (input_bfd));
8922
8923 /* Some relocation types map to different relocations depending on the
9c504268 8924 target. We pick the right one here. */
eb043451 8925 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 8926
8927 /* It is possible to have linker relaxations on some TLS access
8928 models. Update our information here. */
8929 r_type = elf32_arm_tls_transition (info, r_type, h);
8930
eb043451
PB		 8931 if (r_type != howto->type)
8932 howto = elf32_arm_howto_from_type (r_type);
9c504268 8933
34e77a92 8934 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 8935 sgot = globals->root.sgot;
252b5132 8936 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 8937 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
8938
34e77a92
RS		 8939 if (globals->root.dynamic_sections_created)
8940 srelgot = globals->root.srelgot;
8941 else
8942 srelgot = NULL;
8943
252b5132
RH		 8944 r_symndx = ELF32_R_SYM (rel->r_info);
8945
4e7fd91e 8946 if (globals->use_rel)
ba96a88f 8947 {
4e7fd91e
PB		 8948 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
8949
8950 if (addend & ((howto->src_mask + 1) >> 1))
8951 {
8952 signed_addend = -1;
8953 signed_addend &= ~ howto->src_mask;
8954 signed_addend |= addend;
8955 }
8956 else
8957 signed_addend = addend;
ba96a88f
NC		 8958 }
8959 else
4e7fd91e 8960 addend = signed_addend = rel->r_addend;
f21f3fe0 8961
39f21624
NC		 8962 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
8963 are resolving a function call relocation. */
8964 if (using_thumb_only (globals)
8965 && (r_type == R_ARM_THM_CALL
8966 || r_type == R_ARM_THM_JUMP24)
8967 && branch_type == ST_BRANCH_TO_ARM)
8968 branch_type = ST_BRANCH_TO_THUMB;
8969
34e77a92
RS		 8970 /* Record the symbol information that should be used in dynamic
8971 relocations. */
8972 dynreloc_st_type = st_type;
8973 dynreloc_value = value;
8974 if (branch_type == ST_BRANCH_TO_THUMB)
8975 dynreloc_value |= 1;
8976
8977 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
8978 VALUE appropriately for relocations that we resolve at link time. */
8979 has_iplt_entry = FALSE;
8980 if (elf32_arm_get_plt_info (input_bfd, eh, r_symndx, &root_plt, &arm_plt)
8981 && root_plt->offset != (bfd_vma) -1)
8982 {
8983 plt_offset = root_plt->offset;
8984 gotplt_offset = arm_plt->got_offset;
8985
8986 if (h == NULL || eh->is_iplt)
8987 {
8988 has_iplt_entry = TRUE;
8989 splt = globals->root.iplt;
8990
8991 /* Populate .iplt entries here, because not all of them will
8992 be seen by finish_dynamic_symbol. The lower bit is set if
8993 we have already populated the entry. */
8994 if (plt_offset & 1)
8995 plt_offset--;
8996 else
8997 {
57460bcf
NC		 8998 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
8999 -1, dynreloc_value))
9000 root_plt->offset |= 1;
9001 else
9002 return bfd_reloc_notsupported;
34e77a92
RS		 9003 }
9004
9005 /* Static relocations always resolve to the .iplt entry. */
9006 st_type = STT_FUNC;
9007 value = (splt->output_section->vma
9008 + splt->output_offset
9009 + plt_offset);
9010 branch_type = ST_BRANCH_TO_ARM;
9011
9012 /* If there are non-call relocations that resolve to the .iplt
9013 entry, then all dynamic ones must too. */
9014 if (arm_plt->noncall_refcount != 0)
9015 {
9016 dynreloc_st_type = st_type;
9017 dynreloc_value = value;
9018 }
9019 }
9020 else
9021 /* We populate the .plt entry in finish_dynamic_symbol. */
9022 splt = globals->root.splt;
9023 }
9024 else
9025 {
9026 splt = NULL;
9027 plt_offset = (bfd_vma) -1;
9028 gotplt_offset = (bfd_vma) -1;
9029 }
9030
252b5132
RH		 9031 switch (r_type)
9032 {
9033 case R_ARM_NONE:
28a094c2
DJ		 9034 /* We don't need to find a value for this symbol. It's just a
9035 marker. */
9036 *unresolved_reloc_p = FALSE;
252b5132
RH		 9037 return bfd_reloc_ok;
9038
00a97672
RS		 9039 case R_ARM_ABS12:
9040 if (!globals->vxworks_p)
9041 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
9042
252b5132
RH		 9043 case R_ARM_PC24:
9044 case R_ARM_ABS32:
bb224fc3 9045 case R_ARM_ABS32_NOI:
252b5132 9046 case R_ARM_REL32:
bb224fc3 9047 case R_ARM_REL32_NOI:
5b5bb741
PB		 9048 case R_ARM_CALL:
9049 case R_ARM_JUMP24:
dfc5f959 9050 case R_ARM_XPC25:
eb043451 9051 case R_ARM_PREL31:
7359ea65 9052 case R_ARM_PLT32:
7359ea65
DJ		 9053 /* Handle relocations which should use the PLT entry. ABS32/REL32
9054 will use the symbol's value, which may point to a PLT entry, but we
9055 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 9056 branches in this object should go to it, except if the PLT is too
9057 far away, in which case a long branch stub should be inserted. */
bb224fc3 9058 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 9059 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 9060 && r_type != R_ARM_CALL
9061 && r_type != R_ARM_JUMP24
9062 && r_type != R_ARM_PLT32)
34e77a92 9063 && plt_offset != (bfd_vma) -1)
7359ea65 9064 {
34e77a92
RS		 9065 /* If we've created a .plt section, and assigned a PLT entry
9066 to this function, it must either be a STT_GNU_IFUNC reference
9067 or not be known to bind locally. In other cases, we should
9068 have cleared the PLT entry by now. */
9069 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 9070
9071 value = (splt->output_section->vma
9072 + splt->output_offset
34e77a92 9073 + plt_offset);
0945cdfd 9074 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 9075 return _bfd_final_link_relocate (howto, input_bfd, input_section,
9076 contents, rel->r_offset, value,
00a97672 9077 rel->r_addend);
7359ea65
DJ		 9078 }
9079
67687978
PB		 9080 /* When generating a shared object or relocatable executable, these
9081 relocations are copied into the output file to be resolved at
9082 run time. */
0e1862bb
L		 9083 if ((bfd_link_pic (info)
9084 || globals->root.is_relocatable_executable)
7359ea65 9085 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 9086 && !(globals->vxworks_p
3348747a
NS		 9087 && strcmp (input_section->output_section->name,
9088 ".tls_vars") == 0)
bb224fc3 9089 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 9090 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 9091 && !(input_bfd == globals->stub_bfd
9092 && strstr (input_section->name, STUB_SUFFIX))
7359ea65
DJ		 9093 && (h == NULL
9094 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
9095 || h->root.type != bfd_link_hash_undefweak)
9096 && r_type != R_ARM_PC24
5b5bb741
PB		 9097 && r_type != R_ARM_CALL
9098 && r_type != R_ARM_JUMP24
ee06dc07 9099 && r_type != R_ARM_PREL31
7359ea65 9100 && r_type != R_ARM_PLT32)
252b5132 9101 {
947216bf 9102 Elf_Internal_Rela outrel;
b34976b6 9103 bfd_boolean skip, relocate;
f21f3fe0 9104
52db4ec2
JW		 9105 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
9106 && !h->def_regular)
9107 {
9108 char *v = _("shared object");
9109
0e1862bb 9110 if (bfd_link_executable (info))
52db4ec2
JW		 9111 v = _("PIE executable");
9112
9113 (*_bfd_error_handler)
9114 (_("%B: relocation %s against external or undefined symbol `%s'"
9115 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
9116 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
9117 return bfd_reloc_notsupported;
9118 }
9119
0945cdfd
DJ		 9120 *unresolved_reloc_p = FALSE;
9121
34e77a92 9122 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 9123 {
83bac4b0
NC		 9124 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
9125 ! globals->use_rel);
f21f3fe0 9126
83bac4b0 9127 if (sreloc == NULL)
252b5132 9128 return bfd_reloc_notsupported;
252b5132 9129 }
f21f3fe0 9130
b34976b6
AM		 9131 skip = FALSE;
9132 relocate = FALSE;
f21f3fe0 9133
00a97672 9134 outrel.r_addend = addend;
c629eae0
JJ		 9135 outrel.r_offset =
9136 _bfd_elf_section_offset (output_bfd, info, input_section,
9137 rel->r_offset);
9138 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 9139 skip = TRUE;
0bb2d96a 9140 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 9141 skip = TRUE, relocate = TRUE;
252b5132
RH		 9142 outrel.r_offset += (input_section->output_section->vma
9143 + input_section->output_offset);
f21f3fe0 9144
252b5132 9145 if (skip)
0bb2d96a 9146 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 9147 else if (h != NULL
9148 && h->dynindx != -1
0e1862bb 9149 && (!bfd_link_pic (info)
a496fbc8 9150 || !SYMBOLIC_BIND (info, h)
f5385ebf 9151 || !h->def_regular))
5e681ec4 9152 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 9153 else
9154 {
a16385dc
MM		 9155 int symbol;
9156
5e681ec4 9157 /* This symbol is local, or marked to become local. */
34e77a92 9158 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 9159 if (globals->symbian_p)
6366ff1e 9160 {
74541ad4
AM		 9161 asection *osec;
9162
6366ff1e
MM		 9163 /* On Symbian OS, the data segment and text segement
9164 can be relocated independently. Therefore, we
9165 must indicate the segment to which this
9166 relocation is relative. The BPABI allows us to
9167 use any symbol in the right segment; we just use
9168 the section symbol as it is convenient. (We
9169 cannot use the symbol given by "h" directly as it
74541ad4
AM		 9170 will not appear in the dynamic symbol table.)
9171
9172 Note that the dynamic linker ignores the section
9173 symbol value, so we don't subtract osec->vma
9174 from the emitted reloc addend. */
10dbd1f3 9175 if (sym_sec)
74541ad4 9176 osec = sym_sec->output_section;
10dbd1f3 9177 else
74541ad4
AM		 9178 osec = input_section->output_section;
9179 symbol = elf_section_data (osec)->dynindx;
9180 if (symbol == 0)
9181 {
9182 struct elf_link_hash_table *htab = elf_hash_table (info);
9183
9184 if ((osec->flags & SEC_READONLY) == 0
9185 && htab->data_index_section != NULL)
9186 osec = htab->data_index_section;
9187 else
9188 osec = htab->text_index_section;
9189 symbol = elf_section_data (osec)->dynindx;
9190 }
6366ff1e
MM		 9191 BFD_ASSERT (symbol != 0);
9192 }
a16385dc
MM		 9193 else
9194 /* On SVR4-ish systems, the dynamic loader cannot
9195 relocate the text and data segments independently,
9196 so the symbol does not matter. */
9197 symbol = 0;
34e77a92
RS		 9198 if (dynreloc_st_type == STT_GNU_IFUNC)
9199 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
9200 to the .iplt entry. Instead, every non-call reference
9201 must use an R_ARM_IRELATIVE relocation to obtain the
9202 correct run-time address. */
9203 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
9204 else
9205 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 9206 if (globals->use_rel)
9207 relocate = TRUE;
9208 else
34e77a92 9209 outrel.r_addend += dynreloc_value;
252b5132 9210 }
f21f3fe0 9211
47beaa6a 9212 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 9213
f21f3fe0 9214 /* If this reloc is against an external symbol, we do not want to
252b5132 9215 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 9216 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 9217 if (! relocate)
9218 return bfd_reloc_ok;
9a5aca8c 9219
f21f3fe0 9220 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 9221 contents, rel->r_offset,
9222 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 9223 }
9224 else switch (r_type)
9225 {
00a97672
RS		 9226 case R_ARM_ABS12:
9227 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
9228
dfc5f959 9229 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 9230 case R_ARM_CALL:
9231 case R_ARM_JUMP24:
8029a119 9232 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 9233 case R_ARM_PLT32:
906e58ca 9234 {
906e58ca
NC		 9235 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
9236
dfc5f959 9237 if (r_type == R_ARM_XPC25)
252b5132 9238 {
dfc5f959
NC		 9239 /* Check for Arm calling Arm function. */
9240 /* FIXME: Should we translate the instruction into a BL
9241 instruction instead ? */
35fc36a8 9242 if (branch_type != ST_BRANCH_TO_THUMB)
d003868e
AM		 9243 (*_bfd_error_handler)
9244 (_("\%B: Warning: Arm BLX instruction targets Arm function '%s'."),
9245 input_bfd,
9246 h ? h->root.root.string : "(local)");
dfc5f959 9247 }
155d87d7 9248 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 9249 {
9250 /* Check for Arm calling Thumb function. */
35fc36a8 9251 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 9252 {
f2a9dd69
DJ		 9253 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
9254 output_bfd, input_section,
9255 hit_data, sym_sec, rel->r_offset,
9256 signed_addend, value,
9257 error_message))
9258 return bfd_reloc_ok;
9259 else
9260 return bfd_reloc_dangerous;
dfc5f959 9261 }
252b5132 9262 }
ba96a88f 9263
906e58ca 9264 /* Check if a stub has to be inserted because the
8029a119 9265 destination is too far or we are changing mode. */
155d87d7
CL		 9266 if ( r_type == R_ARM_CALL
9267 || r_type == R_ARM_JUMP24
9268 || r_type == R_ARM_PLT32)
906e58ca 9269 {
fe33d2fa
CL		 9270 enum elf32_arm_stub_type stub_type = arm_stub_none;
9271 struct elf32_arm_link_hash_entry *hash;
9272
9273 hash = (struct elf32_arm_link_hash_entry *) h;
9274 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 9275 st_type, &branch_type,
9276 hash, value, sym_sec,
fe33d2fa 9277 input_bfd, sym_name);
5fa9e92f 9278
fe33d2fa 9279 if (stub_type != arm_stub_none)
906e58ca
NC		 9280 {
9281 /* The target is out of reach, so redirect the
9282 branch to the local stub for this function. */
906e58ca
NC		 9283 stub_entry = elf32_arm_get_stub_entry (input_section,
9284 sym_sec, h,
fe33d2fa
CL		 9285 rel, globals,
9286 stub_type);
9cd3e4e5
NC		 9287 {
9288 if (stub_entry != NULL)
9289 value = (stub_entry->stub_offset
9290 + stub_entry->stub_sec->output_offset
9291 + stub_entry->stub_sec->output_section->vma);
9292
9293 if (plt_offset != (bfd_vma) -1)
9294 *unresolved_reloc_p = FALSE;
9295 }
906e58ca 9296 }
fe33d2fa
CL		 9297 else
9298 {
9299 /* If the call goes through a PLT entry, make sure to
9300 check distance to the right destination address. */
34e77a92 9301 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 9302 {
9303 value = (splt->output_section->vma
9304 + splt->output_offset
34e77a92 9305 + plt_offset);
fe33d2fa
CL		 9306 *unresolved_reloc_p = FALSE;
9307 /* The PLT entry is in ARM mode, regardless of the
9308 target function. */
35fc36a8 9309 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 9310 }
9311 }
906e58ca
NC		 9312 }
9313
dea514f5
PB		 9314 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
9315 where:
9316 S is the address of the symbol in the relocation.
9317 P is address of the instruction being relocated.
9318 A is the addend (extracted from the instruction) in bytes.
9319
9320 S is held in 'value'.
9321 P is the base address of the section containing the
9322 instruction plus the offset of the reloc into that
9323 section, ie:
9324 (input_section->output_section->vma +
9325 input_section->output_offset +
9326 rel->r_offset).
9327 A is the addend, converted into bytes, ie:
9328 (signed_addend * 4)
9329
9330 Note: None of these operations have knowledge of the pipeline
9331 size of the processor, thus it is up to the assembler to
9332 encode this information into the addend. */
9333 value -= (input_section->output_section->vma
9334 + input_section->output_offset);
9335 value -= rel->r_offset;
4e7fd91e
PB		 9336 if (globals->use_rel)
9337 value += (signed_addend << howto->size);
9338 else
9339 /* RELA addends do not have to be adjusted by howto->size. */
9340 value += signed_addend;
23080146 9341
dcb5e6e6
NC		 9342 signed_addend = value;
9343 signed_addend >>= howto->rightshift;
9a5aca8c 9344
5ab79981 9345 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 9346 the next instruction unless a PLT entry will be created.
77b4f08f 9347 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 9348 The jump to the next instruction is optimized as a NOP depending
9349 on the architecture. */
ffcb4889 9350 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 9351 && plt_offset == (bfd_vma) -1)
77b4f08f 9352 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 9353 {
cd1dac3d
DG		 9354 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
9355
9356 if (arch_has_arm_nop (globals))
9357 value |= 0x0320f000;
9358 else
9359 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 9360 }
9361 else
59f2c4e7 9362 {
9b485d32 9363 /* Perform a signed range check. */
dcb5e6e6 9364 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 9365 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
9366 return bfd_reloc_overflow;
9a5aca8c 9367
5ab79981 9368 addend = (value & 2);
39b41c9c 9369
5ab79981
PB		 9370 value = (signed_addend & howto->dst_mask)
9371 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 9372
5ab79981
PB		 9373 if (r_type == R_ARM_CALL)
9374 {
155d87d7 9375 /* Set the H bit in the BLX instruction. */
35fc36a8 9376 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 9377 {
9378 if (addend)
9379 value |= (1 << 24);
9380 else
9381 value &= ~(bfd_vma)(1 << 24);
9382 }
9383
5ab79981 9384 /* Select the correct instruction (BL or BLX). */
906e58ca 9385 /* Only if we are not handling a BL to a stub. In this
8029a119 9386 case, mode switching is performed by the stub. */
35fc36a8 9387 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 9388 value |= (1 << 28);
63e1a0fc 9389 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 9390 {
9391 value &= ~(bfd_vma)(1 << 28);
9392 value |= (1 << 24);
9393 }
39b41c9c
PB		 9394 }
9395 }
906e58ca 9396 }
252b5132 9397 break;
f21f3fe0 9398
252b5132
RH		 9399 case R_ARM_ABS32:
9400 value += addend;
35fc36a8 9401 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 9402 value |= 1;
9403 break;
f21f3fe0 9404
bb224fc3
MS		 9405 case R_ARM_ABS32_NOI:
9406 value += addend;
9407 break;
9408
252b5132 9409 case R_ARM_REL32:
a8bc6c78 9410 value += addend;
35fc36a8 9411 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 9412 value |= 1;
252b5132 9413 value -= (input_section->output_section->vma
62efb346 9414 + input_section->output_offset + rel->r_offset);
252b5132 9415 break;
eb043451 9416
bb224fc3
MS		 9417 case R_ARM_REL32_NOI:
9418 value += addend;
9419 value -= (input_section->output_section->vma
9420 + input_section->output_offset + rel->r_offset);
9421 break;
9422
eb043451
PB		 9423 case R_ARM_PREL31:
9424 value -= (input_section->output_section->vma
9425 + input_section->output_offset + rel->r_offset);
9426 value += signed_addend;
9427 if (! h || h->root.type != bfd_link_hash_undefweak)
9428 {
8029a119 9429 /* Check for overflow. */
eb043451
PB		 9430 if ((value ^ (value >> 1)) & (1 << 30))
9431 return bfd_reloc_overflow;
9432 }
9433 value &= 0x7fffffff;
9434 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 9435 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 9436 value |= 1;
9437 break;
252b5132 9438 }
f21f3fe0 9439
252b5132
RH		 9440 bfd_put_32 (input_bfd, value, hit_data);
9441 return bfd_reloc_ok;
9442
9443 case R_ARM_ABS8:
fd0fd00c
MJ		 9444 /* PR 16202: Refectch the addend using the correct size. */
9445 if (globals->use_rel)
9446 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 9447 value += addend;
4e67d4ca
DG		 9448
9449 /* There is no way to tell whether the user intended to use a signed or
9450 unsigned addend. When checking for overflow we accept either,
9451 as specified by the AAELF. */
9452 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 9453 return bfd_reloc_overflow;
9454
9455 bfd_put_8 (input_bfd, value, hit_data);
9456 return bfd_reloc_ok;
9457
9458 case R_ARM_ABS16:
fd0fd00c
MJ		 9459 /* PR 16202: Refectch the addend using the correct size. */
9460 if (globals->use_rel)
9461 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 9462 value += addend;
9463
4e67d4ca
DG		 9464 /* See comment for R_ARM_ABS8. */
9465 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 9466 return bfd_reloc_overflow;
9467
9468 bfd_put_16 (input_bfd, value, hit_data);
9469 return bfd_reloc_ok;
9470
252b5132 9471 case R_ARM_THM_ABS5:
9b485d32 9472 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 9473 if (globals->use_rel)
9474 {
9475 /* Need to refetch addend. */
9476 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
9477 /* ??? Need to determine shift amount from operand size. */
9478 addend >>= howto->rightshift;
9479 }
252b5132
RH		 9480 value += addend;
9481
9482 /* ??? Isn't value unsigned? */
9483 if ((long) value > 0x1f || (long) value < -0x10)
9484 return bfd_reloc_overflow;
9485
9486 /* ??? Value needs to be properly shifted into place first. */
9487 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
9488 bfd_put_16 (input_bfd, value, hit_data);
9489 return bfd_reloc_ok;
9490
2cab6cc3
MS		 9491 case R_ARM_THM_ALU_PREL_11_0:
9492 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
9493 {
9494 bfd_vma insn;
9495 bfd_signed_vma relocation;
9496
9497 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 9498 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 9499
99059e56
RM		 9500 if (globals->use_rel)
9501 {
9502 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
9503 | ((insn & (1 << 26)) >> 15);
9504 if (insn & 0xf00000)
9505 signed_addend = -signed_addend;
9506 }
2cab6cc3
MS		 9507
9508 relocation = value + signed_addend;
79f08007 9509 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9510 + input_section->output_offset
9511 + rel->r_offset);
2cab6cc3 9512
b6518b38 9513 value = relocation;
2cab6cc3 9514
99059e56
RM		 9515 if (value >= 0x1000)
9516 return bfd_reloc_overflow;
2cab6cc3
MS		 9517
9518 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 9519 | ((value & 0x700) << 4)
9520 | ((value & 0x800) << 15);
9521 if (relocation < 0)
9522 insn |= 0xa00000;
2cab6cc3
MS		 9523
9524 bfd_put_16 (input_bfd, insn >> 16, hit_data);
9525 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
9526
99059e56 9527 return bfd_reloc_ok;
2cab6cc3
MS		 9528 }
9529
e1ec24c6
NC		 9530 case R_ARM_THM_PC8:
9531 /* PR 10073: This reloc is not generated by the GNU toolchain,
9532 but it is supported for compatibility with third party libraries
9533 generated by other compilers, specifically the ARM/IAR. */
9534 {
9535 bfd_vma insn;
9536 bfd_signed_vma relocation;
9537
9538 insn = bfd_get_16 (input_bfd, hit_data);
9539
99059e56 9540 if (globals->use_rel)
79f08007 9541 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 9542
9543 relocation = value + addend;
79f08007 9544 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9545 + input_section->output_offset
9546 + rel->r_offset);
e1ec24c6 9547
b6518b38 9548 value = relocation;
e1ec24c6
NC		 9549
9550 /* We do not check for overflow of this reloc. Although strictly
9551 speaking this is incorrect, it appears to be necessary in order
9552 to work with IAR generated relocs. Since GCC and GAS do not
9553 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
9554 a problem for them. */
9555 value &= 0x3fc;
9556
9557 insn = (insn & 0xff00) | (value >> 2);
9558
9559 bfd_put_16 (input_bfd, insn, hit_data);
9560
99059e56 9561 return bfd_reloc_ok;
e1ec24c6
NC		 9562 }
9563
2cab6cc3
MS		 9564 case R_ARM_THM_PC12:
9565 /* Corresponds to: ldr.w reg, [pc, #offset]. */
9566 {
9567 bfd_vma insn;
9568 bfd_signed_vma relocation;
9569
9570 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 9571 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 9572
99059e56
RM		 9573 if (globals->use_rel)
9574 {
9575 signed_addend = insn & 0xfff;
9576 if (!(insn & (1 << 23)))
9577 signed_addend = -signed_addend;
9578 }
2cab6cc3
MS		 9579
9580 relocation = value + signed_addend;
79f08007 9581 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9582 + input_section->output_offset
9583 + rel->r_offset);
2cab6cc3 9584
b6518b38 9585 value = relocation;
2cab6cc3 9586
99059e56
RM		 9587 if (value >= 0x1000)
9588 return bfd_reloc_overflow;
2cab6cc3
MS		 9589
9590 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 9591 if (relocation >= 0)
9592 insn |= (1 << 23);
2cab6cc3
MS		 9593
9594 bfd_put_16 (input_bfd, insn >> 16, hit_data);
9595 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
9596
99059e56 9597 return bfd_reloc_ok;
2cab6cc3
MS		 9598 }
9599
dfc5f959 9600 case R_ARM_THM_XPC22:
c19d1205 9601 case R_ARM_THM_CALL:
bd97cb95 9602 case R_ARM_THM_JUMP24:
dfc5f959 9603 /* Thumb BL (branch long instruction). */
252b5132 9604 {
b34976b6 9605 bfd_vma relocation;
99059e56 9606 bfd_vma reloc_sign;
b34976b6
AM		 9607 bfd_boolean overflow = FALSE;
9608 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
9609 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 9610 bfd_signed_vma reloc_signed_max;
9611 bfd_signed_vma reloc_signed_min;
b34976b6 9612 bfd_vma check;
252b5132 9613 bfd_signed_vma signed_check;
e95de063 9614 int bitsize;
cd1dac3d 9615 const int thumb2 = using_thumb2 (globals);
252b5132 9616
5ab79981 9617 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 9618 the next instruction unless a PLT entry will be created.
9619 The jump to the next instruction is optimized as a NOP.W for
9620 Thumb-2 enabled architectures. */
19540007 9621 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 9622 && plt_offset == (bfd_vma) -1)
5ab79981 9623 {
cd1dac3d
DG		 9624 if (arch_has_thumb2_nop (globals))
9625 {
9626 bfd_put_16 (input_bfd, 0xf3af, hit_data);
9627 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
9628 }
9629 else
9630 {
9631 bfd_put_16 (input_bfd, 0xe000, hit_data);
9632 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
9633 }
5ab79981
PB		 9634 return bfd_reloc_ok;
9635 }
9636
e95de063 9637 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 9638 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 9639 if (globals->use_rel)
9640 {
99059e56
RM		 9641 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
9642 bfd_vma upper = upper_insn & 0x3ff;
9643 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 9644 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
9645 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 9646 bfd_vma i1 = j1 ^ s ? 0 : 1;
9647 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 9648
99059e56
RM		 9649 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
9650 /* Sign extend. */
9651 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 9652
4e7fd91e
PB		 9653 signed_addend = addend;
9654 }
cb1afa5c 9655
dfc5f959
NC		 9656 if (r_type == R_ARM_THM_XPC22)
9657 {
9658 /* Check for Thumb to Thumb call. */
9659 /* FIXME: Should we translate the instruction into a BL
9660 instruction instead ? */
35fc36a8 9661 if (branch_type == ST_BRANCH_TO_THUMB)
d003868e
AM		 9662 (*_bfd_error_handler)
9663 (_("%B: Warning: Thumb BLX instruction targets thumb function '%s'."),
9664 input_bfd,
9665 h ? h->root.root.string : "(local)");
dfc5f959
NC		 9666 }
9667 else
252b5132 9668 {
dfc5f959
NC		 9669 /* If it is not a call to Thumb, assume call to Arm.
9670 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 9671 function call at all, but rather a long jump. Calls through
9672 the PLT do not require stubs. */
34e77a92 9673 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 9674 {
bd97cb95 9675 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 9676 {
9677 /* Convert BL to BLX. */
9678 lower_insn = (lower_insn & ~0x1000) | 0x0800;
9679 }
155d87d7
CL		 9680 else if (( r_type != R_ARM_THM_CALL)
9681 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 9682 {
9683 if (elf32_thumb_to_arm_stub
9684 (info, sym_name, input_bfd, output_bfd, input_section,
9685 hit_data, sym_sec, rel->r_offset, signed_addend, value,
9686 error_message))
9687 return bfd_reloc_ok;
9688 else
9689 return bfd_reloc_dangerous;
9690 }
da5938a2 9691 }
35fc36a8
RS		 9692 else if (branch_type == ST_BRANCH_TO_THUMB
9693 && globals->use_blx
bd97cb95 9694 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 9695 {
9696 /* Make sure this is a BL. */
9697 lower_insn |= 0x1800;
9698 }
252b5132 9699 }
f21f3fe0 9700
fe33d2fa 9701 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 9702 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 9703 {
9704 /* Check if a stub has to be inserted because the destination
8029a119 9705 is too far. */
fe33d2fa
CL		 9706 struct elf32_arm_stub_hash_entry *stub_entry;
9707 struct elf32_arm_link_hash_entry *hash;
9708
9709 hash = (struct elf32_arm_link_hash_entry *) h;
9710
9711 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 9712 st_type, &branch_type,
9713 hash, value, sym_sec,
fe33d2fa
CL		 9714 input_bfd, sym_name);
9715
9716 if (stub_type != arm_stub_none)
906e58ca
NC		 9717 {
9718 /* The target is out of reach or we are changing modes, so
9719 redirect the branch to the local stub for this
9720 function. */
9721 stub_entry = elf32_arm_get_stub_entry (input_section,
9722 sym_sec, h,
fe33d2fa
CL		 9723 rel, globals,
9724 stub_type);
906e58ca 9725 if (stub_entry != NULL)
9cd3e4e5
NC		 9726 {
9727 value = (stub_entry->stub_offset
9728 + stub_entry->stub_sec->output_offset
9729 + stub_entry->stub_sec->output_section->vma);
9730
9731 if (plt_offset != (bfd_vma) -1)
9732 *unresolved_reloc_p = FALSE;
9733 }
906e58ca 9734
f4ac8484 9735 /* If this call becomes a call to Arm, force BLX. */
155d87d7 9736 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 9737 {
9738 if ((stub_entry
9739 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 9740 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 9741 lower_insn = (lower_insn & ~0x1000) | 0x0800;
9742 }
906e58ca
NC		 9743 }
9744 }
9745
fe33d2fa 9746 /* Handle calls via the PLT. */
34e77a92 9747 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 9748 {
9749 value = (splt->output_section->vma
9750 + splt->output_offset
34e77a92 9751 + plt_offset);
fe33d2fa 9752
eed94f8f
NC		 9753 if (globals->use_blx
9754 && r_type == R_ARM_THM_CALL
9755 && ! using_thumb_only (globals))
fe33d2fa
CL		 9756 {
9757 /* If the Thumb BLX instruction is available, convert
9758 the BL to a BLX instruction to call the ARM-mode
9759 PLT entry. */
9760 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 9761 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 9762 }
9763 else
9764 {
eed94f8f
NC		 9765 if (! using_thumb_only (globals))
9766 /* Target the Thumb stub before the ARM PLT entry. */
9767 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 9768 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 9769 }
9770 *unresolved_reloc_p = FALSE;
9771 }
9772
ba96a88f 9773 relocation = value + signed_addend;
f21f3fe0 9774
252b5132 9775 relocation -= (input_section->output_section->vma
ba96a88f
NC		 9776 + input_section->output_offset
9777 + rel->r_offset);
9a5aca8c 9778
252b5132
RH		 9779 check = relocation >> howto->rightshift;
9780
9781 /* If this is a signed value, the rightshift just dropped
9782 leading 1 bits (assuming twos complement). */
9783 if ((bfd_signed_vma) relocation >= 0)
9784 signed_check = check;
9785 else
9786 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
9787
e95de063
MS		 9788 /* Calculate the permissable maximum and minimum values for
9789 this relocation according to whether we're relocating for
9790 Thumb-2 or not. */
9791 bitsize = howto->bitsize;
9792 if (!thumb2)
9793 bitsize -= 2;
f6ebfac0 9794 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 9795 reloc_signed_min = ~reloc_signed_max;
9796
252b5132 9797 /* Assumes two's complement. */
ba96a88f 9798 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 9799 overflow = TRUE;
252b5132 9800
bd97cb95 9801 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 9802 /* For a BLX instruction, make sure that the relocation is rounded up
9803 to a word boundary. This follows the semantics of the instruction
9804 which specifies that bit 1 of the target address will come from bit
9805 1 of the base address. */
9806 relocation = (relocation + 2) & ~ 3;
cb1afa5c 9807
e95de063
MS		 9808 /* Put RELOCATION back into the insn. Assumes two's complement.
9809 We use the Thumb-2 encoding, which is safe even if dealing with
9810 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 9811 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 9812 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 9813 | ((relocation >> 12) & 0x3ff)
9814 | (reloc_sign << 10);
906e58ca 9815 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 9816 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
9817 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
9818 | ((relocation >> 1) & 0x7ff);
c62e1cc3 9819
252b5132
RH		 9820 /* Put the relocated value back in the object file: */
9821 bfd_put_16 (input_bfd, upper_insn, hit_data);
9822 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
9823
9824 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
9825 }
9826 break;
9827
c19d1205
ZW		 9828 case R_ARM_THM_JUMP19:
9829 /* Thumb32 conditional branch instruction. */
9830 {
9831 bfd_vma relocation;
9832 bfd_boolean overflow = FALSE;
9833 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
9834 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 9835 bfd_signed_vma reloc_signed_max = 0xffffe;
9836 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 9837 bfd_signed_vma signed_check;
c5423981
TG		 9838 enum elf32_arm_stub_type stub_type = arm_stub_none;
9839 struct elf32_arm_stub_hash_entry *stub_entry;
9840 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 9841
9842 /* Need to refetch the addend, reconstruct the top three bits,
9843 and squish the two 11 bit pieces together. */
9844 if (globals->use_rel)
9845 {
9846 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 9847 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 9848 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
9849 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
9850 bfd_vma lower = (lower_insn & 0x07ff);
9851
a00a1f35
MS		 9852 upper |= J1 << 6;
9853 upper |= J2 << 7;
9854 upper |= (!S) << 8;
c19d1205
ZW		 9855 upper -= 0x0100; /* Sign extend. */
9856
9857 addend = (upper << 12) | (lower << 1);
9858 signed_addend = addend;
9859 }
9860
bd97cb95 9861 /* Handle calls via the PLT. */
34e77a92 9862 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 9863 {
9864 value = (splt->output_section->vma
9865 + splt->output_offset
34e77a92 9866 + plt_offset);
bd97cb95
DJ		 9867 /* Target the Thumb stub before the ARM PLT entry. */
9868 value -= PLT_THUMB_STUB_SIZE;
9869 *unresolved_reloc_p = FALSE;
9870 }
9871
c5423981
TG		 9872 hash = (struct elf32_arm_link_hash_entry *)h;
9873
9874 stub_type = arm_type_of_stub (info, input_section, rel,
9875 st_type, &branch_type,
9876 hash, value, sym_sec,
9877 input_bfd, sym_name);
9878 if (stub_type != arm_stub_none)
9879 {
9880 stub_entry = elf32_arm_get_stub_entry (input_section,
9881 sym_sec, h,
9882 rel, globals,
9883 stub_type);
9884 if (stub_entry != NULL)
9885 {
9886 value = (stub_entry->stub_offset
9887 + stub_entry->stub_sec->output_offset
9888 + stub_entry->stub_sec->output_section->vma);
9889 }
9890 }
c19d1205 9891
99059e56 9892 relocation = value + signed_addend;
c19d1205
ZW		 9893 relocation -= (input_section->output_section->vma
9894 + input_section->output_offset
9895 + rel->r_offset);
a00a1f35 9896 signed_check = (bfd_signed_vma) relocation;
c19d1205 9897
c19d1205
ZW		 9898 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
9899 overflow = TRUE;
9900
9901 /* Put RELOCATION back into the insn. */
9902 {
9903 bfd_vma S = (relocation & 0x00100000) >> 20;
9904 bfd_vma J2 = (relocation & 0x00080000) >> 19;
9905 bfd_vma J1 = (relocation & 0x00040000) >> 18;
9906 bfd_vma hi = (relocation & 0x0003f000) >> 12;
9907 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
9908
a00a1f35 9909 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 9910 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
9911 }
9912
9913 /* Put the relocated value back in the object file: */
9914 bfd_put_16 (input_bfd, upper_insn, hit_data);
9915 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
9916
9917 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
9918 }
9919
9920 case R_ARM_THM_JUMP11:
9921 case R_ARM_THM_JUMP8:
9922 case R_ARM_THM_JUMP6:
51c5503b
NC		 9923 /* Thumb B (branch) instruction). */
9924 {
6cf9e9fe 9925 bfd_signed_vma relocation;
51c5503b
NC		 9926 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
9927 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 9928 bfd_signed_vma signed_check;
9929
c19d1205
ZW		 9930 /* CZB cannot jump backward. */
9931 if (r_type == R_ARM_THM_JUMP6)
9932 reloc_signed_min = 0;
9933
4e7fd91e 9934 if (globals->use_rel)
6cf9e9fe 9935 {
4e7fd91e
PB		 9936 /* Need to refetch addend. */
9937 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
9938 if (addend & ((howto->src_mask + 1) >> 1))
9939 {
9940 signed_addend = -1;
9941 signed_addend &= ~ howto->src_mask;
9942 signed_addend |= addend;
9943 }
9944 else
9945 signed_addend = addend;
9946 /* The value in the insn has been right shifted. We need to
9947 undo this, so that we can perform the address calculation
9948 in terms of bytes. */
9949 signed_addend <<= howto->rightshift;
6cf9e9fe 9950 }
6cf9e9fe 9951 relocation = value + signed_addend;
51c5503b
NC		 9952
9953 relocation -= (input_section->output_section->vma
9954 + input_section->output_offset
9955 + rel->r_offset);
9956
6cf9e9fe
NC		 9957 relocation >>= howto->rightshift;
9958 signed_check = relocation;
c19d1205
ZW		 9959
9960 if (r_type == R_ARM_THM_JUMP6)
9961 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
9962 else
9963 relocation &= howto->dst_mask;
51c5503b 9964 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 9965
51c5503b
NC		 9966 bfd_put_16 (input_bfd, relocation, hit_data);
9967
9968 /* Assumes two's complement. */
9969 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
9970 return bfd_reloc_overflow;
9971
9972 return bfd_reloc_ok;
9973 }
cedb70c5 9974
8375c36b
PB		 9975 case R_ARM_ALU_PCREL7_0:
9976 case R_ARM_ALU_PCREL15_8:
9977 case R_ARM_ALU_PCREL23_15:
9978 {
9979 bfd_vma insn;
9980 bfd_vma relocation;
9981
9982 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 9983 if (globals->use_rel)
9984 {
9985 /* Extract the addend. */
9986 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
9987 signed_addend = addend;
9988 }
8375c36b
PB		 9989 relocation = value + signed_addend;
9990
9991 relocation -= (input_section->output_section->vma
9992 + input_section->output_offset
9993 + rel->r_offset);
9994 insn = (insn & ~0xfff)
9995 | ((howto->bitpos << 7) & 0xf00)
9996 | ((relocation >> howto->bitpos) & 0xff);
9997 bfd_put_32 (input_bfd, value, hit_data);
9998 }
9999 return bfd_reloc_ok;
10000
252b5132
RH		 10001 case R_ARM_GNU_VTINHERIT:
10002 case R_ARM_GNU_VTENTRY:
10003 return bfd_reloc_ok;
10004
c19d1205 10005 case R_ARM_GOTOFF32:
252b5132 10006 /* Relocation is relative to the start of the
99059e56 10007 global offset table. */
252b5132
RH		 10008
10009 BFD_ASSERT (sgot != NULL);
10010 if (sgot == NULL)
99059e56 10011 return bfd_reloc_notsupported;
9a5aca8c 10012
cedb70c5 10013 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 10014 address by one, so that attempts to call the function pointer will
10015 correctly interpret it as Thumb code. */
35fc36a8 10016 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 10017 value += 1;
10018
252b5132 10019 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 10020 calculation. We always want the start of .got. If we
10021 define _GLOBAL_OFFSET_TABLE in a different way, as is
10022 permitted by the ABI, we might have to change this
10023 calculation. */
252b5132 10024 value -= sgot->output_section->vma;
f21f3fe0 10025 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10026 contents, rel->r_offset, value,
00a97672 10027 rel->r_addend);
252b5132
RH		 10028
10029 case R_ARM_GOTPC:
a7c10850 10030 /* Use global offset table as symbol value. */
252b5132 10031 BFD_ASSERT (sgot != NULL);
f21f3fe0 10032
252b5132 10033 if (sgot == NULL)
99059e56 10034 return bfd_reloc_notsupported;
252b5132 10035
0945cdfd 10036 *unresolved_reloc_p = FALSE;
252b5132 10037 value = sgot->output_section->vma;
f21f3fe0 10038 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10039 contents, rel->r_offset, value,
00a97672 10040 rel->r_addend);
f21f3fe0 10041
252b5132 10042 case R_ARM_GOT32:
eb043451 10043 case R_ARM_GOT_PREL:
252b5132 10044 /* Relocation is to the entry for this symbol in the
99059e56 10045 global offset table. */
252b5132
RH		 10046 if (sgot == NULL)
10047 return bfd_reloc_notsupported;
f21f3fe0 10048
34e77a92
RS		 10049 if (dynreloc_st_type == STT_GNU_IFUNC
10050 && plt_offset != (bfd_vma) -1
10051 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
10052 {
10053 /* We have a relocation against a locally-binding STT_GNU_IFUNC
10054 symbol, and the relocation resolves directly to the runtime
10055 target rather than to the .iplt entry. This means that any
10056 .got entry would be the same value as the .igot.plt entry,
10057 so there's no point creating both. */
10058 sgot = globals->root.igotplt;
10059 value = sgot->output_offset + gotplt_offset;
10060 }
10061 else if (h != NULL)
252b5132
RH		 10062 {
10063 bfd_vma off;
f21f3fe0 10064
252b5132
RH		 10065 off = h->got.offset;
10066 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 10067 if ((off & 1) != 0)
252b5132 10068 {
b436d854
RS		 10069 /* We have already processsed one GOT relocation against
10070 this symbol. */
10071 off &= ~1;
10072 if (globals->root.dynamic_sections_created
10073 && !SYMBOL_REFERENCES_LOCAL (info, h))
10074 *unresolved_reloc_p = FALSE;
10075 }
10076 else
10077 {
10078 Elf_Internal_Rela outrel;
10079
6f820c85 10080 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 10081 {
10082 /* If the symbol doesn't resolve locally in a static
10083 object, we have an undefined reference. If the
10084 symbol doesn't resolve locally in a dynamic object,
10085 it should be resolved by the dynamic linker. */
10086 if (globals->root.dynamic_sections_created)
10087 {
10088 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
10089 *unresolved_reloc_p = FALSE;
10090 }
10091 else
10092 outrel.r_info = 0;
10093 outrel.r_addend = 0;
10094 }
252b5132
RH		 10095 else
10096 {
34e77a92 10097 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 10098 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
0e1862bb 10099 else if (bfd_link_pic (info) &&
31943882
WN		 10100 (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10101 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 10102 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
10103 else
10104 outrel.r_info = 0;
34e77a92 10105 outrel.r_addend = dynreloc_value;
b436d854 10106 }
ee29b9fb 10107
b436d854
RS		 10108 /* The GOT entry is initialized to zero by default.
10109 See if we should install a different value. */
10110 if (outrel.r_addend != 0
10111 && (outrel.r_info == 0 || globals->use_rel))
10112 {
10113 bfd_put_32 (output_bfd, outrel.r_addend,
10114 sgot->contents + off);
10115 outrel.r_addend = 0;
252b5132 10116 }
f21f3fe0 10117
b436d854
RS		 10118 if (outrel.r_info != 0)
10119 {
10120 outrel.r_offset = (sgot->output_section->vma
10121 + sgot->output_offset
10122 + off);
10123 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
10124 }
10125 h->got.offset |= 1;
10126 }
252b5132
RH		 10127 value = sgot->output_offset + off;
10128 }
10129 else
10130 {
10131 bfd_vma off;
f21f3fe0 10132
252b5132
RH		 10133 BFD_ASSERT (local_got_offsets != NULL &&
10134 local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 10135
252b5132 10136 off = local_got_offsets[r_symndx];
f21f3fe0 10137
252b5132
RH		 10138 /* The offset must always be a multiple of 4. We use the
10139 least significant bit to record whether we have already
9b485d32 10140 generated the necessary reloc. */
252b5132
RH		 10141 if ((off & 1) != 0)
10142 off &= ~1;
10143 else
10144 {
00a97672 10145 if (globals->use_rel)
34e77a92 10146 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 10147
0e1862bb 10148 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 10149 {
947216bf 10150 Elf_Internal_Rela outrel;
f21f3fe0 10151
34e77a92 10152 outrel.r_addend = addend + dynreloc_value;
252b5132 10153 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 10154 + sgot->output_offset
252b5132 10155 + off);
34e77a92 10156 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 10157 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 10158 else
10159 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 10160 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 10161 }
f21f3fe0 10162
252b5132
RH		 10163 local_got_offsets[r_symndx] |= 1;
10164 }
f21f3fe0 10165
252b5132
RH		 10166 value = sgot->output_offset + off;
10167 }
eb043451
PB		 10168 if (r_type != R_ARM_GOT32)
10169 value += sgot->output_section->vma;
9a5aca8c 10170
f21f3fe0 10171 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10172 contents, rel->r_offset, value,
00a97672 10173 rel->r_addend);
f21f3fe0 10174
ba93b8ac
DJ		 10175 case R_ARM_TLS_LDO32:
10176 value = value - dtpoff_base (info);
10177
10178 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 10179 contents, rel->r_offset, value,
10180 rel->r_addend);
ba93b8ac
DJ		 10181
10182 case R_ARM_TLS_LDM32:
10183 {
10184 bfd_vma off;
10185
362d30a1 10186 if (sgot == NULL)
ba93b8ac
DJ		 10187 abort ();
10188
10189 off = globals->tls_ldm_got.offset;
10190
10191 if ((off & 1) != 0)
10192 off &= ~1;
10193 else
10194 {
10195 /* If we don't know the module number, create a relocation
10196 for it. */
0e1862bb 10197 if (bfd_link_pic (info))
ba93b8ac
DJ		 10198 {
10199 Elf_Internal_Rela outrel;
ba93b8ac 10200
362d30a1 10201 if (srelgot == NULL)
ba93b8ac
DJ		 10202 abort ();
10203
00a97672 10204 outrel.r_addend = 0;
362d30a1
RS		 10205 outrel.r_offset = (sgot->output_section->vma
10206 + sgot->output_offset + off);
ba93b8ac
DJ		 10207 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
10208
00a97672
RS		 10209 if (globals->use_rel)
10210 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10211 sgot->contents + off);
ba93b8ac 10212
47beaa6a 10213 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10214 }
10215 else
362d30a1 10216 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 10217
10218 globals->tls_ldm_got.offset |= 1;
10219 }
10220
362d30a1 10221 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 10222 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
10223
10224 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10225 contents, rel->r_offset, value,
00a97672 10226 rel->r_addend);
ba93b8ac
DJ		 10227 }
10228
0855e32b
NS		 10229 case R_ARM_TLS_CALL:
10230 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 10231 case R_ARM_TLS_GD32:
10232 case R_ARM_TLS_IE32:
0855e32b
NS		 10233 case R_ARM_TLS_GOTDESC:
10234 case R_ARM_TLS_DESCSEQ:
10235 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 10236 {
0855e32b
NS		 10237 bfd_vma off, offplt;
10238 int indx = 0;
ba93b8ac
DJ		 10239 char tls_type;
10240
0855e32b 10241 BFD_ASSERT (sgot != NULL);
ba93b8ac 10242
ba93b8ac
DJ		 10243 if (h != NULL)
10244 {
10245 bfd_boolean dyn;
10246 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 10247 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
10248 bfd_link_pic (info),
10249 h)
10250 && (!bfd_link_pic (info)
ba93b8ac
DJ		 10251 || !SYMBOL_REFERENCES_LOCAL (info, h)))
10252 {
10253 *unresolved_reloc_p = FALSE;
10254 indx = h->dynindx;
10255 }
10256 off = h->got.offset;
0855e32b 10257 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 10258 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
10259 }
10260 else
10261 {
0855e32b 10262 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 10263 off = local_got_offsets[r_symndx];
0855e32b 10264 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 10265 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
10266 }
10267
0855e32b 10268 /* Linker relaxations happens from one of the
b38cadfb 10269 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 10270 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 10271 tls_type = GOT_TLS_IE;
0855e32b
NS		 10272
10273 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 10274
10275 if ((off & 1) != 0)
10276 off &= ~1;
10277 else
10278 {
10279 bfd_boolean need_relocs = FALSE;
10280 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 10281 int cur_off = off;
10282
10283 /* The GOT entries have not been initialized yet. Do it
10284 now, and emit any relocations. If both an IE GOT and a
10285 GD GOT are necessary, we emit the GD first. */
10286
0e1862bb 10287 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 10288 && (h == NULL
10289 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10290 || h->root.type != bfd_link_hash_undefweak))
10291 {
10292 need_relocs = TRUE;
0855e32b 10293 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 10294 }
10295
0855e32b
NS		 10296 if (tls_type & GOT_TLS_GDESC)
10297 {
47beaa6a
RS		 10298 bfd_byte *loc;
10299
0855e32b
NS		 10300 /* We should have relaxed, unless this is an undefined
10301 weak symbol. */
10302 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 10303 || bfd_link_pic (info));
0855e32b 10304 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 10305 <= globals->root.sgotplt->size);
0855e32b
NS		 10306
10307 outrel.r_addend = 0;
10308 outrel.r_offset = (globals->root.sgotplt->output_section->vma
10309 + globals->root.sgotplt->output_offset
10310 + offplt
10311 + globals->sgotplt_jump_table_size);
b38cadfb 10312
0855e32b
NS		 10313 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
10314 sreloc = globals->root.srelplt;
10315 loc = sreloc->contents;
10316 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
10317 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 10318 <= sreloc->contents + sreloc->size);
0855e32b
NS		 10319
10320 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
10321
10322 /* For globals, the first word in the relocation gets
10323 the relocation index and the top bit set, or zero,
10324 if we're binding now. For locals, it gets the
10325 symbol's offset in the tls section. */
99059e56 10326 bfd_put_32 (output_bfd,
0855e32b
NS		 10327 !h ? value - elf_hash_table (info)->tls_sec->vma
10328 : info->flags & DF_BIND_NOW ? 0
10329 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 10330 globals->root.sgotplt->contents + offplt
10331 + globals->sgotplt_jump_table_size);
10332
0855e32b 10333 /* Second word in the relocation is always zero. */
99059e56 10334 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 10335 globals->root.sgotplt->contents + offplt
10336 + globals->sgotplt_jump_table_size + 4);
0855e32b 10337 }
ba93b8ac
DJ		 10338 if (tls_type & GOT_TLS_GD)
10339 {
10340 if (need_relocs)
10341 {
00a97672 10342 outrel.r_addend = 0;
362d30a1
RS		 10343 outrel.r_offset = (sgot->output_section->vma
10344 + sgot->output_offset
00a97672 10345 + cur_off);
ba93b8ac 10346 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 10347
00a97672
RS		 10348 if (globals->use_rel)
10349 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10350 sgot->contents + cur_off);
00a97672 10351
47beaa6a 10352 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10353
10354 if (indx == 0)
10355 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 10356 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 10357 else
10358 {
00a97672 10359 outrel.r_addend = 0;
ba93b8ac
DJ		 10360 outrel.r_info = ELF32_R_INFO (indx,
10361 R_ARM_TLS_DTPOFF32);
10362 outrel.r_offset += 4;
00a97672
RS		 10363
10364 if (globals->use_rel)
10365 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10366 sgot->contents + cur_off + 4);
00a97672 10367
47beaa6a
RS		 10368 elf32_arm_add_dynreloc (output_bfd, info,
10369 srelgot, &outrel);
ba93b8ac
DJ		 10370 }
10371 }
10372 else
10373 {
10374 /* If we are not emitting relocations for a
10375 general dynamic reference, then we must be in a
10376 static link or an executable link with the
10377 symbol binding locally. Mark it as belonging
10378 to module 1, the executable. */
10379 bfd_put_32 (output_bfd, 1,
362d30a1 10380 sgot->contents + cur_off);
ba93b8ac 10381 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 10382 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 10383 }
10384
10385 cur_off += 8;
10386 }
10387
10388 if (tls_type & GOT_TLS_IE)
10389 {
10390 if (need_relocs)
10391 {
00a97672
RS		 10392 if (indx == 0)
10393 outrel.r_addend = value - dtpoff_base (info);
10394 else
10395 outrel.r_addend = 0;
362d30a1
RS		 10396 outrel.r_offset = (sgot->output_section->vma
10397 + sgot->output_offset
ba93b8ac
DJ		 10398 + cur_off);
10399 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
10400
00a97672
RS		 10401 if (globals->use_rel)
10402 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10403 sgot->contents + cur_off);
ba93b8ac 10404
47beaa6a 10405 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10406 }
10407 else
10408 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 10409 sgot->contents + cur_off);
ba93b8ac
DJ		 10410 cur_off += 4;
10411 }
10412
10413 if (h != NULL)
10414 h->got.offset |= 1;
10415 else
10416 local_got_offsets[r_symndx] |= 1;
10417 }
10418
10419 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
10420 off += 8;
0855e32b
NS		 10421 else if (tls_type & GOT_TLS_GDESC)
10422 off = offplt;
10423
10424 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
10425 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
10426 {
10427 bfd_signed_vma offset;
12352d3f
PB		 10428 /* TLS stubs are arm mode. The original symbol is a
10429 data object, so branch_type is bogus. */
10430 branch_type = ST_BRANCH_TO_ARM;
0855e32b 10431 enum elf32_arm_stub_type stub_type
34e77a92
RS		 10432 = arm_type_of_stub (info, input_section, rel,
10433 st_type, &branch_type,
0855e32b
NS		 10434 (struct elf32_arm_link_hash_entry *)h,
10435 globals->tls_trampoline, globals->root.splt,
10436 input_bfd, sym_name);
10437
10438 if (stub_type != arm_stub_none)
10439 {
10440 struct elf32_arm_stub_hash_entry *stub_entry
10441 = elf32_arm_get_stub_entry
10442 (input_section, globals->root.splt, 0, rel,
10443 globals, stub_type);
10444 offset = (stub_entry->stub_offset
10445 + stub_entry->stub_sec->output_offset
10446 + stub_entry->stub_sec->output_section->vma);
10447 }
10448 else
10449 offset = (globals->root.splt->output_section->vma
10450 + globals->root.splt->output_offset
10451 + globals->tls_trampoline);
10452
10453 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
10454 {
10455 unsigned long inst;
b38cadfb
NC		 10456
10457 offset -= (input_section->output_section->vma
10458 + input_section->output_offset
10459 + rel->r_offset + 8);
0855e32b
NS		 10460
10461 inst = offset >> 2;
10462 inst &= 0x00ffffff;
10463 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
10464 }
10465 else
10466 {
10467 /* Thumb blx encodes the offset in a complicated
10468 fashion. */
10469 unsigned upper_insn, lower_insn;
10470 unsigned neg;
10471
b38cadfb
NC		 10472 offset -= (input_section->output_section->vma
10473 + input_section->output_offset
0855e32b 10474 + rel->r_offset + 4);
b38cadfb 10475
12352d3f
PB		 10476 if (stub_type != arm_stub_none
10477 && arm_stub_is_thumb (stub_type))
10478 {
10479 lower_insn = 0xd000;
10480 }
10481 else
10482 {
10483 lower_insn = 0xc000;
6a631e86 10484 /* Round up the offset to a word boundary. */
12352d3f
PB		 10485 offset = (offset + 2) & ~2;
10486 }
10487
0855e32b
NS		 10488 neg = offset < 0;
10489 upper_insn = (0xf000
10490 | ((offset >> 12) & 0x3ff)
10491 | (neg << 10));
12352d3f 10492 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 10493 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 10494 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 10495 bfd_put_16 (input_bfd, upper_insn, hit_data);
10496 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10497 return bfd_reloc_ok;
10498 }
10499 }
10500 /* These relocations needs special care, as besides the fact
10501 they point somewhere in .gotplt, the addend must be
10502 adjusted accordingly depending on the type of instruction
6a631e86 10503 we refer to. */
0855e32b
NS		 10504 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
10505 {
10506 unsigned long data, insn;
10507 unsigned thumb;
b38cadfb 10508
0855e32b
NS		 10509 data = bfd_get_32 (input_bfd, hit_data);
10510 thumb = data & 1;
10511 data &= ~1u;
b38cadfb 10512
0855e32b
NS		 10513 if (thumb)
10514 {
10515 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
10516 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10517 insn = (insn << 16)
10518 | bfd_get_16 (input_bfd,
10519 contents + rel->r_offset - data + 2);
10520 if ((insn & 0xf800c000) == 0xf000c000)
10521 /* bl/blx */
10522 value = -6;
10523 else if ((insn & 0xffffff00) == 0x4400)
10524 /* add */
10525 value = -5;
10526 else
10527 {
10528 (*_bfd_error_handler)
10529 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' referenced by TLS_GOTDESC"),
10530 input_bfd, input_section,
10531 (unsigned long)rel->r_offset, insn);
10532 return bfd_reloc_notsupported;
10533 }
10534 }
10535 else
10536 {
10537 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
10538
10539 switch (insn >> 24)
10540 {
10541 case 0xeb: /* bl */
10542 case 0xfa: /* blx */
10543 value = -4;
10544 break;
10545
10546 case 0xe0: /* add */
10547 value = -8;
10548 break;
b38cadfb 10549
0855e32b
NS		 10550 default:
10551 (*_bfd_error_handler)
10552 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' referenced by TLS_GOTDESC"),
10553 input_bfd, input_section,
10554 (unsigned long)rel->r_offset, insn);
10555 return bfd_reloc_notsupported;
10556 }
10557 }
b38cadfb 10558
0855e32b
NS		 10559 value += ((globals->root.sgotplt->output_section->vma
10560 + globals->root.sgotplt->output_offset + off)
10561 - (input_section->output_section->vma
10562 + input_section->output_offset
10563 + rel->r_offset)
10564 + globals->sgotplt_jump_table_size);
10565 }
10566 else
10567 value = ((globals->root.sgot->output_section->vma
10568 + globals->root.sgot->output_offset + off)
10569 - (input_section->output_section->vma
10570 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 10571
10572 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10573 contents, rel->r_offset, value,
00a97672 10574 rel->r_addend);
ba93b8ac
DJ		 10575 }
10576
10577 case R_ARM_TLS_LE32:
3cbc1e5e 10578 if (bfd_link_dll (info))
ba93b8ac
DJ		 10579 {
10580 (*_bfd_error_handler)
10581 (_("%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object"),
10582 input_bfd, input_section,
10583 (long) rel->r_offset, howto->name);
46691134 10584 return bfd_reloc_notsupported;
ba93b8ac
DJ		 10585 }
10586 else
10587 value = tpoff (info, value);
906e58ca 10588
ba93b8ac 10589 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 10590 contents, rel->r_offset, value,
10591 rel->r_addend);
ba93b8ac 10592
319850b4
JB		 10593 case R_ARM_V4BX:
10594 if (globals->fix_v4bx)
845b51d6
PB		 10595 {
10596 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 10597
845b51d6
PB		 10598 /* Ensure that we have a BX instruction. */
10599 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 10600
845b51d6
PB		 10601 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
10602 {
10603 /* Branch to veneer. */
10604 bfd_vma glue_addr;
10605 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
10606 glue_addr -= input_section->output_section->vma
10607 + input_section->output_offset
10608 + rel->r_offset + 8;
10609 insn = (insn & 0xf0000000) | 0x0a000000
10610 | ((glue_addr >> 2) & 0x00ffffff);
10611 }
10612 else
10613 {
10614 /* Preserve Rm (lowest four bits) and the condition code
10615 (highest four bits). Other bits encode MOV PC,Rm. */
10616 insn = (insn & 0xf000000f) | 0x01a0f000;
10617 }
319850b4 10618
845b51d6
PB		 10619 bfd_put_32 (input_bfd, insn, hit_data);
10620 }
319850b4
JB		 10621 return bfd_reloc_ok;
10622
b6895b4f
PB		 10623 case R_ARM_MOVW_ABS_NC:
10624 case R_ARM_MOVT_ABS:
10625 case R_ARM_MOVW_PREL_NC:
10626 case R_ARM_MOVT_PREL:
92f5d02b
MS		 10627 /* Until we properly support segment-base-relative addressing then
10628 we assume the segment base to be zero, as for the group relocations.
10629 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
10630 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
10631 case R_ARM_MOVW_BREL_NC:
10632 case R_ARM_MOVW_BREL:
10633 case R_ARM_MOVT_BREL:
b6895b4f
PB		 10634 {
10635 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
10636
10637 if (globals->use_rel)
10638 {
10639 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 10640 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 10641 }
92f5d02b 10642
b6895b4f 10643 value += signed_addend;
b6895b4f
PB		 10644
10645 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
10646 value -= (input_section->output_section->vma
10647 + input_section->output_offset + rel->r_offset);
10648
92f5d02b 10649 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 10650 return bfd_reloc_overflow;
92f5d02b 10651
35fc36a8 10652 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 10653 value |= 1;
10654
10655 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 10656 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 10657 value >>= 16;
10658
10659 insn &= 0xfff0f000;
10660 insn |= value & 0xfff;
10661 insn |= (value & 0xf000) << 4;
10662 bfd_put_32 (input_bfd, insn, hit_data);
10663 }
10664 return bfd_reloc_ok;
10665
10666 case R_ARM_THM_MOVW_ABS_NC:
10667 case R_ARM_THM_MOVT_ABS:
10668 case R_ARM_THM_MOVW_PREL_NC:
10669 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 10670 /* Until we properly support segment-base-relative addressing then
10671 we assume the segment base to be zero, as for the above relocations.
10672 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
10673 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
10674 as R_ARM_THM_MOVT_ABS. */
10675 case R_ARM_THM_MOVW_BREL_NC:
10676 case R_ARM_THM_MOVW_BREL:
10677 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 10678 {
10679 bfd_vma insn;
906e58ca 10680
b6895b4f
PB		 10681 insn = bfd_get_16 (input_bfd, hit_data) << 16;
10682 insn |= bfd_get_16 (input_bfd, hit_data + 2);
10683
10684 if (globals->use_rel)
10685 {
10686 addend = ((insn >> 4) & 0xf000)
10687 | ((insn >> 15) & 0x0800)
10688 | ((insn >> 4) & 0x0700)
10689 | (insn & 0x00ff);
39623e12 10690 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 10691 }
92f5d02b 10692
b6895b4f 10693 value += signed_addend;
b6895b4f
PB		 10694
10695 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
10696 value -= (input_section->output_section->vma
10697 + input_section->output_offset + rel->r_offset);
10698
92f5d02b 10699 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 10700 return bfd_reloc_overflow;
92f5d02b 10701
35fc36a8 10702 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 10703 value |= 1;
10704
10705 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 10706 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 10707 value >>= 16;
10708
10709 insn &= 0xfbf08f00;
10710 insn |= (value & 0xf000) << 4;
10711 insn |= (value & 0x0800) << 15;
10712 insn |= (value & 0x0700) << 4;
10713 insn |= (value & 0x00ff);
10714
10715 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10716 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10717 }
10718 return bfd_reloc_ok;
10719
4962c51a
MS		 10720 case R_ARM_ALU_PC_G0_NC:
10721 case R_ARM_ALU_PC_G1_NC:
10722 case R_ARM_ALU_PC_G0:
10723 case R_ARM_ALU_PC_G1:
10724 case R_ARM_ALU_PC_G2:
10725 case R_ARM_ALU_SB_G0_NC:
10726 case R_ARM_ALU_SB_G1_NC:
10727 case R_ARM_ALU_SB_G0:
10728 case R_ARM_ALU_SB_G1:
10729 case R_ARM_ALU_SB_G2:
10730 {
10731 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10732 bfd_vma pc = input_section->output_section->vma
4962c51a 10733 + input_section->output_offset + rel->r_offset;
31a91d61 10734 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10735 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 10736 bfd_vma residual;
10737 bfd_vma g_n;
4962c51a 10738 bfd_signed_vma signed_value;
99059e56
RM		 10739 int group = 0;
10740
10741 /* Determine which group of bits to select. */
10742 switch (r_type)
10743 {
10744 case R_ARM_ALU_PC_G0_NC:
10745 case R_ARM_ALU_PC_G0:
10746 case R_ARM_ALU_SB_G0_NC:
10747 case R_ARM_ALU_SB_G0:
10748 group = 0;
10749 break;
10750
10751 case R_ARM_ALU_PC_G1_NC:
10752 case R_ARM_ALU_PC_G1:
10753 case R_ARM_ALU_SB_G1_NC:
10754 case R_ARM_ALU_SB_G1:
10755 group = 1;
10756 break;
10757
10758 case R_ARM_ALU_PC_G2:
10759 case R_ARM_ALU_SB_G2:
10760 group = 2;
10761 break;
10762
10763 default:
10764 abort ();
10765 }
10766
10767 /* If REL, extract the addend from the insn. If RELA, it will
10768 have already been fetched for us. */
4962c51a 10769 if (globals->use_rel)
99059e56
RM		 10770 {
10771 int negative;
10772 bfd_vma constant = insn & 0xff;
10773 bfd_vma rotation = (insn & 0xf00) >> 8;
10774
10775 if (rotation == 0)
10776 signed_addend = constant;
10777 else
10778 {
10779 /* Compensate for the fact that in the instruction, the
10780 rotation is stored in multiples of 2 bits. */
10781 rotation *= 2;
10782
10783 /* Rotate "constant" right by "rotation" bits. */
10784 signed_addend = (constant >> rotation) |
10785 (constant << (8 * sizeof (bfd_vma) - rotation));
10786 }
10787
10788 /* Determine if the instruction is an ADD or a SUB.
10789 (For REL, this determines the sign of the addend.) */
10790 negative = identify_add_or_sub (insn);
10791 if (negative == 0)
10792 {
10793 (*_bfd_error_handler)
10794 (_("%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations"),
10795 input_bfd, input_section,
10796 (long) rel->r_offset, howto->name);
10797 return bfd_reloc_overflow;
10798 }
10799
10800 signed_addend *= negative;
10801 }
4962c51a
MS		 10802
10803 /* Compute the value (X) to go in the place. */
99059e56
RM		 10804 if (r_type == R_ARM_ALU_PC_G0_NC
10805 || r_type == R_ARM_ALU_PC_G1_NC
10806 || r_type == R_ARM_ALU_PC_G0
10807 || r_type == R_ARM_ALU_PC_G1
10808 || r_type == R_ARM_ALU_PC_G2)
10809 /* PC relative. */
10810 signed_value = value - pc + signed_addend;
10811 else
10812 /* Section base relative. */
10813 signed_value = value - sb + signed_addend;
10814
10815 /* If the target symbol is a Thumb function, then set the
10816 Thumb bit in the address. */
35fc36a8 10817 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 10818 signed_value |= 1;
10819
99059e56
RM		 10820 /* Calculate the value of the relevant G_n, in encoded
10821 constant-with-rotation format. */
b6518b38
NC		 10822 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
10823 group, &residual);
99059e56
RM		 10824
10825 /* Check for overflow if required. */
10826 if ((r_type == R_ARM_ALU_PC_G0
10827 || r_type == R_ARM_ALU_PC_G1
10828 || r_type == R_ARM_ALU_PC_G2
10829 || r_type == R_ARM_ALU_SB_G0
10830 || r_type == R_ARM_ALU_SB_G1
10831 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
10832 {
10833 (*_bfd_error_handler)
10834 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
10835 input_bfd, input_section,
b6518b38
NC		 10836 (long) rel->r_offset, signed_value < 0 ? - signed_value : signed_value,
10837 howto->name);
99059e56
RM		 10838 return bfd_reloc_overflow;
10839 }
10840
10841 /* Mask out the value and the ADD/SUB part of the opcode; take care
10842 not to destroy the S bit. */
10843 insn &= 0xff1ff000;
10844
10845 /* Set the opcode according to whether the value to go in the
10846 place is negative. */
10847 if (signed_value < 0)
10848 insn |= 1 << 22;
10849 else
10850 insn |= 1 << 23;
10851
10852 /* Encode the offset. */
10853 insn |= g_n;
4962c51a
MS		 10854
10855 bfd_put_32 (input_bfd, insn, hit_data);
10856 }
10857 return bfd_reloc_ok;
10858
10859 case R_ARM_LDR_PC_G0:
10860 case R_ARM_LDR_PC_G1:
10861 case R_ARM_LDR_PC_G2:
10862 case R_ARM_LDR_SB_G0:
10863 case R_ARM_LDR_SB_G1:
10864 case R_ARM_LDR_SB_G2:
10865 {
10866 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10867 bfd_vma pc = input_section->output_section->vma
4962c51a 10868 + input_section->output_offset + rel->r_offset;
31a91d61 10869 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10870 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 10871 bfd_vma residual;
4962c51a 10872 bfd_signed_vma signed_value;
99059e56
RM		 10873 int group = 0;
10874
10875 /* Determine which groups of bits to calculate. */
10876 switch (r_type)
10877 {
10878 case R_ARM_LDR_PC_G0:
10879 case R_ARM_LDR_SB_G0:
10880 group = 0;
10881 break;
10882
10883 case R_ARM_LDR_PC_G1:
10884 case R_ARM_LDR_SB_G1:
10885 group = 1;
10886 break;
10887
10888 case R_ARM_LDR_PC_G2:
10889 case R_ARM_LDR_SB_G2:
10890 group = 2;
10891 break;
10892
10893 default:
10894 abort ();
10895 }
10896
10897 /* If REL, extract the addend from the insn. If RELA, it will
10898 have already been fetched for us. */
4962c51a 10899 if (globals->use_rel)
99059e56
RM		 10900 {
10901 int negative = (insn & (1 << 23)) ? 1 : -1;
10902 signed_addend = negative * (insn & 0xfff);
10903 }
4962c51a
MS		 10904
10905 /* Compute the value (X) to go in the place. */
99059e56
RM		 10906 if (r_type == R_ARM_LDR_PC_G0
10907 || r_type == R_ARM_LDR_PC_G1
10908 || r_type == R_ARM_LDR_PC_G2)
10909 /* PC relative. */
10910 signed_value = value - pc + signed_addend;
10911 else
10912 /* Section base relative. */
10913 signed_value = value - sb + signed_addend;
10914
10915 /* Calculate the value of the relevant G_{n-1} to obtain
10916 the residual at that stage. */
b6518b38
NC		 10917 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
10918 group - 1, &residual);
99059e56
RM		 10919
10920 /* Check for overflow. */
10921 if (residual >= 0x1000)
10922 {
10923 (*_bfd_error_handler)
10924 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 10925 input_bfd, input_section,
10926 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 10927 return bfd_reloc_overflow;
10928 }
10929
10930 /* Mask out the value and U bit. */
10931 insn &= 0xff7ff000;
10932
10933 /* Set the U bit if the value to go in the place is non-negative. */
10934 if (signed_value >= 0)
10935 insn |= 1 << 23;
10936
10937 /* Encode the offset. */
10938 insn |= residual;
4962c51a
MS		 10939
10940 bfd_put_32 (input_bfd, insn, hit_data);
10941 }
10942 return bfd_reloc_ok;
10943
10944 case R_ARM_LDRS_PC_G0:
10945 case R_ARM_LDRS_PC_G1:
10946 case R_ARM_LDRS_PC_G2:
10947 case R_ARM_LDRS_SB_G0:
10948 case R_ARM_LDRS_SB_G1:
10949 case R_ARM_LDRS_SB_G2:
10950 {
10951 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10952 bfd_vma pc = input_section->output_section->vma
4962c51a 10953 + input_section->output_offset + rel->r_offset;
31a91d61 10954 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10955 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 10956 bfd_vma residual;
4962c51a 10957 bfd_signed_vma signed_value;
99059e56
RM		 10958 int group = 0;
10959
10960 /* Determine which groups of bits to calculate. */
10961 switch (r_type)
10962 {
10963 case R_ARM_LDRS_PC_G0:
10964 case R_ARM_LDRS_SB_G0:
10965 group = 0;
10966 break;
10967
10968 case R_ARM_LDRS_PC_G1:
10969 case R_ARM_LDRS_SB_G1:
10970 group = 1;
10971 break;
10972
10973 case R_ARM_LDRS_PC_G2:
10974 case R_ARM_LDRS_SB_G2:
10975 group = 2;
10976 break;
10977
10978 default:
10979 abort ();
10980 }
10981
10982 /* If REL, extract the addend from the insn. If RELA, it will
10983 have already been fetched for us. */
4962c51a 10984 if (globals->use_rel)
99059e56
RM		 10985 {
10986 int negative = (insn & (1 << 23)) ? 1 : -1;
10987 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
10988 }
4962c51a
MS		 10989
10990 /* Compute the value (X) to go in the place. */
99059e56
RM		 10991 if (r_type == R_ARM_LDRS_PC_G0
10992 || r_type == R_ARM_LDRS_PC_G1
10993 || r_type == R_ARM_LDRS_PC_G2)
10994 /* PC relative. */
10995 signed_value = value - pc + signed_addend;
10996 else
10997 /* Section base relative. */
10998 signed_value = value - sb + signed_addend;
10999
11000 /* Calculate the value of the relevant G_{n-1} to obtain
11001 the residual at that stage. */
b6518b38
NC		 11002 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11003 group - 1, &residual);
99059e56
RM		 11004
11005 /* Check for overflow. */
11006 if (residual >= 0x100)
11007 {
11008 (*_bfd_error_handler)
11009 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 11010 input_bfd, input_section,
11011 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11012 return bfd_reloc_overflow;
11013 }
11014
11015 /* Mask out the value and U bit. */
11016 insn &= 0xff7ff0f0;
11017
11018 /* Set the U bit if the value to go in the place is non-negative. */
11019 if (signed_value >= 0)
11020 insn |= 1 << 23;
11021
11022 /* Encode the offset. */
11023 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 11024
11025 bfd_put_32 (input_bfd, insn, hit_data);
11026 }
11027 return bfd_reloc_ok;
11028
11029 case R_ARM_LDC_PC_G0:
11030 case R_ARM_LDC_PC_G1:
11031 case R_ARM_LDC_PC_G2:
11032 case R_ARM_LDC_SB_G0:
11033 case R_ARM_LDC_SB_G1:
11034 case R_ARM_LDC_SB_G2:
11035 {
11036 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11037 bfd_vma pc = input_section->output_section->vma
4962c51a 11038 + input_section->output_offset + rel->r_offset;
31a91d61 11039 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11040 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11041 bfd_vma residual;
4962c51a 11042 bfd_signed_vma signed_value;
99059e56
RM		 11043 int group = 0;
11044
11045 /* Determine which groups of bits to calculate. */
11046 switch (r_type)
11047 {
11048 case R_ARM_LDC_PC_G0:
11049 case R_ARM_LDC_SB_G0:
11050 group = 0;
11051 break;
11052
11053 case R_ARM_LDC_PC_G1:
11054 case R_ARM_LDC_SB_G1:
11055 group = 1;
11056 break;
11057
11058 case R_ARM_LDC_PC_G2:
11059 case R_ARM_LDC_SB_G2:
11060 group = 2;
11061 break;
11062
11063 default:
11064 abort ();
11065 }
11066
11067 /* If REL, extract the addend from the insn. If RELA, it will
11068 have already been fetched for us. */
4962c51a 11069 if (globals->use_rel)
99059e56
RM		 11070 {
11071 int negative = (insn & (1 << 23)) ? 1 : -1;
11072 signed_addend = negative * ((insn & 0xff) << 2);
11073 }
4962c51a
MS		 11074
11075 /* Compute the value (X) to go in the place. */
99059e56
RM		 11076 if (r_type == R_ARM_LDC_PC_G0
11077 || r_type == R_ARM_LDC_PC_G1
11078 || r_type == R_ARM_LDC_PC_G2)
11079 /* PC relative. */
11080 signed_value = value - pc + signed_addend;
11081 else
11082 /* Section base relative. */
11083 signed_value = value - sb + signed_addend;
11084
11085 /* Calculate the value of the relevant G_{n-1} to obtain
11086 the residual at that stage. */
b6518b38
NC		 11087 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11088 group - 1, &residual);
99059e56
RM		 11089
11090 /* Check for overflow. (The absolute value to go in the place must be
11091 divisible by four and, after having been divided by four, must
11092 fit in eight bits.) */
11093 if ((residual & 0x3) != 0 || residual >= 0x400)
11094 {
11095 (*_bfd_error_handler)
11096 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
11097 input_bfd, input_section,
b6518b38 11098 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11099 return bfd_reloc_overflow;
11100 }
11101
11102 /* Mask out the value and U bit. */
11103 insn &= 0xff7fff00;
11104
11105 /* Set the U bit if the value to go in the place is non-negative. */
11106 if (signed_value >= 0)
11107 insn |= 1 << 23;
11108
11109 /* Encode the offset. */
11110 insn |= residual >> 2;
4962c51a
MS		 11111
11112 bfd_put_32 (input_bfd, insn, hit_data);
11113 }
11114 return bfd_reloc_ok;
11115
72d98d16
MG		 11116 case R_ARM_THM_ALU_ABS_G0_NC:
11117 case R_ARM_THM_ALU_ABS_G1_NC:
11118 case R_ARM_THM_ALU_ABS_G2_NC:
11119 case R_ARM_THM_ALU_ABS_G3_NC:
11120 {
11121 const int shift_array[4] = {0, 8, 16, 24};
11122 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
11123 bfd_vma addr = value;
11124 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
11125
11126 /* Compute address. */
11127 if (globals->use_rel)
11128 signed_addend = insn & 0xff;
11129 addr += signed_addend;
11130 if (branch_type == ST_BRANCH_TO_THUMB)
11131 addr |= 1;
11132 /* Clean imm8 insn. */
11133 insn &= 0xff00;
11134 /* And update with correct part of address. */
11135 insn |= (addr >> shift) & 0xff;
11136 /* Update insn. */
11137 bfd_put_16 (input_bfd, insn, hit_data);
11138 }
11139
11140 *unresolved_reloc_p = FALSE;
11141 return bfd_reloc_ok;
11142
252b5132
RH		 11143 default:
11144 return bfd_reloc_notsupported;
11145 }
11146}
11147
98c1d4aa
NC		 11148/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
11149static void
57e8b36a
NC		 11150arm_add_to_rel (bfd * abfd,
11151 bfd_byte * address,
11152 reloc_howto_type * howto,
11153 bfd_signed_vma increment)
98c1d4aa 11154{
98c1d4aa
NC		 11155 bfd_signed_vma addend;
11156
bd97cb95
DJ		 11157 if (howto->type == R_ARM_THM_CALL
11158 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 11159 {
9a5aca8c
AM		 11160 int upper_insn, lower_insn;
11161 int upper, lower;
98c1d4aa 11162
9a5aca8c
AM		 11163 upper_insn = bfd_get_16 (abfd, address);
11164 lower_insn = bfd_get_16 (abfd, address + 2);
11165 upper = upper_insn & 0x7ff;
11166 lower = lower_insn & 0x7ff;
11167
11168 addend = (upper << 12) | (lower << 1);
ddda4409 11169 addend += increment;
9a5aca8c 11170 addend >>= 1;
98c1d4aa 11171
9a5aca8c
AM		 11172 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
11173 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
11174
dc810e39
AM		 11175 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
11176 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 11177 }
11178 else
11179 {
11180 bfd_vma contents;
11181
11182 contents = bfd_get_32 (abfd, address);
11183
11184 /* Get the (signed) value from the instruction. */
11185 addend = contents & howto->src_mask;
11186 if (addend & ((howto->src_mask + 1) >> 1))
11187 {
11188 bfd_signed_vma mask;
11189
11190 mask = -1;
11191 mask &= ~ howto->src_mask;
11192 addend |= mask;
11193 }
11194
11195 /* Add in the increment, (which is a byte value). */
11196 switch (howto->type)
11197 {
11198 default:
11199 addend += increment;
11200 break;
11201
11202 case R_ARM_PC24:
c6596c5e 11203 case R_ARM_PLT32:
5b5bb741
PB		 11204 case R_ARM_CALL:
11205 case R_ARM_JUMP24:
9a5aca8c 11206 addend <<= howto->size;
dc810e39 11207 addend += increment;
9a5aca8c
AM		 11208
11209 /* Should we check for overflow here ? */
11210
11211 /* Drop any undesired bits. */
11212 addend >>= howto->rightshift;
11213 break;
11214 }
11215
11216 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
11217
11218 bfd_put_32 (abfd, contents, address);
ddda4409 11219 }
98c1d4aa 11220}
252b5132 11221
ba93b8ac
DJ		 11222#define IS_ARM_TLS_RELOC(R_TYPE) \
11223 ((R_TYPE) == R_ARM_TLS_GD32 \
11224 || (R_TYPE) == R_ARM_TLS_LDO32 \
11225 || (R_TYPE) == R_ARM_TLS_LDM32 \
11226 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
11227 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
11228 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
11229 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 11230 || (R_TYPE) == R_ARM_TLS_IE32 \
11231 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
11232
11233/* Specific set of relocations for the gnu tls dialect. */
11234#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
11235 ((R_TYPE) == R_ARM_TLS_GOTDESC \
11236 || (R_TYPE) == R_ARM_TLS_CALL \
11237 || (R_TYPE) == R_ARM_THM_TLS_CALL \
11238 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
11239 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 11240
252b5132 11241/* Relocate an ARM ELF section. */
906e58ca 11242
b34976b6 11243static bfd_boolean
57e8b36a
NC		 11244elf32_arm_relocate_section (bfd * output_bfd,
11245 struct bfd_link_info * info,
11246 bfd * input_bfd,
11247 asection * input_section,
11248 bfd_byte * contents,
11249 Elf_Internal_Rela * relocs,
11250 Elf_Internal_Sym * local_syms,
11251 asection ** local_sections)
252b5132 11252{
b34976b6
AM		 11253 Elf_Internal_Shdr *symtab_hdr;
11254 struct elf_link_hash_entry **sym_hashes;
11255 Elf_Internal_Rela *rel;
11256 Elf_Internal_Rela *relend;
11257 const char *name;
b32d3aa2 11258 struct elf32_arm_link_hash_table * globals;
252b5132 11259
4e7fd91e 11260 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 11261 if (globals == NULL)
11262 return FALSE;
b491616a 11263
0ffa91dd 11264 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 11265 sym_hashes = elf_sym_hashes (input_bfd);
11266
11267 rel = relocs;
11268 relend = relocs + input_section->reloc_count;
11269 for (; rel < relend; rel++)
11270 {
ba96a88f
NC		 11271 int r_type;
11272 reloc_howto_type * howto;
11273 unsigned long r_symndx;
11274 Elf_Internal_Sym * sym;
11275 asection * sec;
252b5132 11276 struct elf_link_hash_entry * h;
ba96a88f
NC		 11277 bfd_vma relocation;
11278 bfd_reloc_status_type r;
11279 arelent bfd_reloc;
ba93b8ac 11280 char sym_type;
0945cdfd 11281 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 11282 char *error_message = NULL;
f21f3fe0 11283
252b5132 11284 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 11285 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 11286 r_type = arm_real_reloc_type (globals, r_type);
252b5132 11287
ba96a88f 11288 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 11289 || r_type == R_ARM_GNU_VTINHERIT)
11290 continue;
252b5132 11291
b32d3aa2 11292 bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
ba96a88f 11293 howto = bfd_reloc.howto;
252b5132 11294
252b5132
RH		 11295 h = NULL;
11296 sym = NULL;
11297 sec = NULL;
9b485d32 11298
252b5132
RH		 11299 if (r_symndx < symtab_hdr->sh_info)
11300 {
11301 sym = local_syms + r_symndx;
ba93b8ac 11302 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 11303 sec = local_sections[r_symndx];
ffcb4889
NS		 11304
11305 /* An object file might have a reference to a local
11306 undefined symbol. This is a daft object file, but we
11307 should at least do something about it. V4BX & NONE
11308 relocations do not use the symbol and are explicitly
77b4f08f
TS		 11309 allowed to use the undefined symbol, so allow those.
11310 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 11311 if (r_type != R_ARM_V4BX
11312 && r_type != R_ARM_NONE
77b4f08f 11313 && r_symndx != STN_UNDEF
ffcb4889
NS		 11314 && bfd_is_und_section (sec)
11315 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
11316 {
11317 if (!info->callbacks->undefined_symbol
11318 (info, bfd_elf_string_from_elf_section
11319 (input_bfd, symtab_hdr->sh_link, sym->st_name),
11320 input_bfd, input_section,
11321 rel->r_offset, TRUE))
11322 return FALSE;
11323 }
b38cadfb 11324
4e7fd91e 11325 if (globals->use_rel)
f8df10f4 11326 {
4e7fd91e
PB		 11327 relocation = (sec->output_section->vma
11328 + sec->output_offset
11329 + sym->st_value);
0e1862bb 11330 if (!bfd_link_relocatable (info)
ab96bf03
AM		 11331 && (sec->flags & SEC_MERGE)
11332 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 11333 {
4e7fd91e
PB		 11334 asection *msec;
11335 bfd_vma addend, value;
11336
39623e12 11337 switch (r_type)
4e7fd91e 11338 {
39623e12
PB		 11339 case R_ARM_MOVW_ABS_NC:
11340 case R_ARM_MOVT_ABS:
11341 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
11342 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
11343 addend = (addend ^ 0x8000) - 0x8000;
11344 break;
f8df10f4 11345
39623e12
PB		 11346 case R_ARM_THM_MOVW_ABS_NC:
11347 case R_ARM_THM_MOVT_ABS:
11348 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
11349 << 16;
11350 value |= bfd_get_16 (input_bfd,
11351 contents + rel->r_offset + 2);
11352 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
11353 | ((value & 0x04000000) >> 15);
11354 addend = (addend ^ 0x8000) - 0x8000;
11355 break;
f8df10f4 11356
39623e12
PB		 11357 default:
11358 if (howto->rightshift
11359 || (howto->src_mask & (howto->src_mask + 1)))
11360 {
11361 (*_bfd_error_handler)
11362 (_("%B(%A+0x%lx): %s relocation against SEC_MERGE section"),
11363 input_bfd, input_section,
11364 (long) rel->r_offset, howto->name);
11365 return FALSE;
11366 }
11367
11368 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
11369
11370 /* Get the (signed) value from the instruction. */
11371 addend = value & howto->src_mask;
11372 if (addend & ((howto->src_mask + 1) >> 1))
11373 {
11374 bfd_signed_vma mask;
11375
11376 mask = -1;
11377 mask &= ~ howto->src_mask;
11378 addend |= mask;
11379 }
11380 break;
4e7fd91e 11381 }
39623e12 11382
4e7fd91e
PB		 11383 msec = sec;
11384 addend =
11385 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
11386 - relocation;
11387 addend += msec->output_section->vma + msec->output_offset;
39623e12 11388
cc643b88 11389 /* Cases here must match those in the preceding
39623e12
PB		 11390 switch statement. */
11391 switch (r_type)
11392 {
11393 case R_ARM_MOVW_ABS_NC:
11394 case R_ARM_MOVT_ABS:
11395 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
11396 | (addend & 0xfff);
11397 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
11398 break;
11399
11400 case R_ARM_THM_MOVW_ABS_NC:
11401 case R_ARM_THM_MOVT_ABS:
11402 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
11403 | (addend & 0xff) | ((addend & 0x0800) << 15);
11404 bfd_put_16 (input_bfd, value >> 16,
11405 contents + rel->r_offset);
11406 bfd_put_16 (input_bfd, value,
11407 contents + rel->r_offset + 2);
11408 break;
11409
11410 default:
11411 value = (value & ~ howto->dst_mask)
11412 | (addend & howto->dst_mask);
11413 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
11414 break;
11415 }
f8df10f4 11416 }
f8df10f4 11417 }
4e7fd91e
PB		 11418 else
11419 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 11420 }
11421 else
11422 {
62d887d4 11423 bfd_boolean warned, ignored;
560e09e9 11424
b2a8e766
AM		 11425 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
11426 r_symndx, symtab_hdr, sym_hashes,
11427 h, sec, relocation,
62d887d4 11428 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 11429
11430 sym_type = h->type;
252b5132
RH		 11431 }
11432
dbaa2011 11433 if (sec != NULL && discarded_section (sec))
e4067dbb 11434 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 11435 rel, 1, relend, howto, 0, contents);
ab96bf03 11436
0e1862bb 11437 if (bfd_link_relocatable (info))
ab96bf03
AM		 11438 {
11439 /* This is a relocatable link. We don't have to change
11440 anything, unless the reloc is against a section symbol,
11441 in which case we have to adjust according to where the
11442 section symbol winds up in the output section. */
11443 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
11444 {
11445 if (globals->use_rel)
11446 arm_add_to_rel (input_bfd, contents + rel->r_offset,
11447 howto, (bfd_signed_vma) sec->output_offset);
11448 else
11449 rel->r_addend += sec->output_offset;
11450 }
11451 continue;
11452 }
11453
252b5132
RH		 11454 if (h != NULL)
11455 name = h->root.root.string;
11456 else
11457 {
11458 name = (bfd_elf_string_from_elf_section
11459 (input_bfd, symtab_hdr->sh_link, sym->st_name));
11460 if (name == NULL || *name == '\0')
11461 name = bfd_section_name (input_bfd, sec);
11462 }
f21f3fe0 11463
cf35638d 11464 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 11465 && r_type != R_ARM_NONE
11466 && (h == NULL
11467 || h->root.type == bfd_link_hash_defined
11468 || h->root.type == bfd_link_hash_defweak)
11469 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
11470 {
11471 (*_bfd_error_handler)
11472 ((sym_type == STT_TLS
11473 ? _("%B(%A+0x%lx): %s used with TLS symbol %s")
11474 : _("%B(%A+0x%lx): %s used with non-TLS symbol %s")),
11475 input_bfd,
11476 input_section,
11477 (long) rel->r_offset,
11478 howto->name,
11479 name);
11480 }
11481
0855e32b 11482 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 11483 done, i.e., the relaxation produced the final output we want,
11484 and we won't let anybody mess with it. Also, we have to do
11485 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 11486 both in relaxed and non-relaxed cases. */
0855e32b
NS		 11487 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
11488 || (IS_ARM_TLS_GNU_RELOC (r_type)
b38cadfb 11489 && !((h ? elf32_arm_hash_entry (h)->tls_type :
0855e32b
NS		 11490 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
11491 & GOT_TLS_GDESC)))
11492 {
11493 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
11494 contents, rel, h == NULL);
11495 /* This may have been marked unresolved because it came from
11496 a shared library. But we've just dealt with that. */
11497 unresolved_reloc = 0;
11498 }
11499 else
11500 r = bfd_reloc_continue;
b38cadfb 11501
0855e32b
NS		 11502 if (r == bfd_reloc_continue)
11503 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
11504 input_section, contents, rel,
34e77a92 11505 relocation, info, sec, name, sym_type,
35fc36a8
RS		 11506 (h ? h->target_internal
11507 : ARM_SYM_BRANCH_TYPE (sym)), h,
0855e32b 11508 &unresolved_reloc, &error_message);
0945cdfd
DJ		 11509
11510 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
11511 because such sections are not SEC_ALLOC and thus ld.so will
11512 not process them. */
11513 if (unresolved_reloc
99059e56
RM		 11514 && !((input_section->flags & SEC_DEBUGGING) != 0
11515 && h->def_dynamic)
1d5316ab
AM		 11516 && _bfd_elf_section_offset (output_bfd, info, input_section,
11517 rel->r_offset) != (bfd_vma) -1)
0945cdfd
DJ		 11518 {
11519 (*_bfd_error_handler)
843fe662
L		 11520 (_("%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"),
11521 input_bfd,
11522 input_section,
11523 (long) rel->r_offset,
11524 howto->name,
11525 h->root.root.string);
0945cdfd
DJ		 11526 return FALSE;
11527 }
252b5132
RH		 11528
11529 if (r != bfd_reloc_ok)
11530 {
252b5132
RH		 11531 switch (r)
11532 {
11533 case bfd_reloc_overflow:
cf919dfd
PB		 11534 /* If the overflowing reloc was to an undefined symbol,
11535 we have already printed one error message and there
11536 is no point complaining again. */
11537 if ((! h ||
11538 h->root.type != bfd_link_hash_undefined)
11539 && (!((*info->callbacks->reloc_overflow)
dfeffb9f
L		 11540 (info, (h ? &h->root : NULL), name, howto->name,
11541 (bfd_vma) 0, input_bfd, input_section,
11542 rel->r_offset))))
b34976b6 11543 return FALSE;
252b5132
RH		 11544 break;
11545
11546 case bfd_reloc_undefined:
11547 if (!((*info->callbacks->undefined_symbol)
11548 (info, name, input_bfd, input_section,
b34976b6
AM		 11549 rel->r_offset, TRUE)))
11550 return FALSE;
252b5132
RH		 11551 break;
11552
11553 case bfd_reloc_outofrange:
f2a9dd69 11554 error_message = _("out of range");
252b5132
RH		 11555 goto common_error;
11556
11557 case bfd_reloc_notsupported:
f2a9dd69 11558 error_message = _("unsupported relocation");
252b5132
RH		 11559 goto common_error;
11560
11561 case bfd_reloc_dangerous:
f2a9dd69 11562 /* error_message should already be set. */
252b5132
RH		 11563 goto common_error;
11564
11565 default:
f2a9dd69 11566 error_message = _("unknown error");
8029a119 11567 /* Fall through. */
252b5132
RH		 11568
11569 common_error:
f2a9dd69
DJ		 11570 BFD_ASSERT (error_message != NULL);
11571 if (!((*info->callbacks->reloc_dangerous)
11572 (info, error_message, input_bfd, input_section,
252b5132 11573 rel->r_offset)))
b34976b6 11574 return FALSE;
252b5132
RH		 11575 break;
11576 }
11577 }
11578 }
11579
b34976b6 11580 return TRUE;
252b5132
RH		 11581}
11582
91d6fa6a 11583/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 11584 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 11585 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 11586 maintaining that condition). */
11587
11588static void
11589add_unwind_table_edit (arm_unwind_table_edit **head,
11590 arm_unwind_table_edit **tail,
11591 arm_unwind_edit_type type,
11592 asection *linked_section,
91d6fa6a 11593 unsigned int tindex)
2468f9c9 11594{
21d799b5
NC		 11595 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
11596 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 11597
2468f9c9
PB		 11598 new_edit->type = type;
11599 new_edit->linked_section = linked_section;
91d6fa6a 11600 new_edit->index = tindex;
b38cadfb 11601
91d6fa6a 11602 if (tindex > 0)
2468f9c9
PB		 11603 {
11604 new_edit->next = NULL;
11605
11606 if (*tail)
11607 (*tail)->next = new_edit;
11608
11609 (*tail) = new_edit;
11610
11611 if (!*head)
11612 (*head) = new_edit;
11613 }
11614 else
11615 {
11616 new_edit->next = *head;
11617
11618 if (!*tail)
11619 *tail = new_edit;
11620
11621 *head = new_edit;
11622 }
11623}
11624
11625static _arm_elf_section_data *get_arm_elf_section_data (asection *);
11626
11627/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
11628static void
11629adjust_exidx_size(asection *exidx_sec, int adjust)
11630{
11631 asection *out_sec;
11632
11633 if (!exidx_sec->rawsize)
11634 exidx_sec->rawsize = exidx_sec->size;
11635
11636 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
11637 out_sec = exidx_sec->output_section;
11638 /* Adjust size of output section. */
11639 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
11640}
11641
11642/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
11643static void
11644insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
11645{
11646 struct _arm_elf_section_data *exidx_arm_data;
11647
11648 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
11649 add_unwind_table_edit (
11650 &exidx_arm_data->u.exidx.unwind_edit_list,
11651 &exidx_arm_data->u.exidx.unwind_edit_tail,
11652 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
11653
491d01d3
YU		 11654 exidx_arm_data->additional_reloc_count++;
11655
2468f9c9
PB		 11656 adjust_exidx_size(exidx_sec, 8);
11657}
11658
11659/* Scan .ARM.exidx tables, and create a list describing edits which should be
11660 made to those tables, such that:
b38cadfb 11661
2468f9c9
PB		 11662 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
11663 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 11664 codes which have been inlined into the index).
2468f9c9 11665
85fdf906
AH		 11666 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
11667
2468f9c9 11668 The edits are applied when the tables are written
b38cadfb 11669 (in elf32_arm_write_section). */
2468f9c9
PB		 11670
11671bfd_boolean
11672elf32_arm_fix_exidx_coverage (asection **text_section_order,
11673 unsigned int num_text_sections,
85fdf906
AH		 11674 struct bfd_link_info *info,
11675 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 11676{
11677 bfd *inp;
11678 unsigned int last_second_word = 0, i;
11679 asection *last_exidx_sec = NULL;
11680 asection *last_text_sec = NULL;
11681 int last_unwind_type = -1;
11682
11683 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
11684 text sections. */
c72f2fb2 11685 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 11686 {
11687 asection *sec;
b38cadfb 11688
2468f9c9 11689 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 11690 {
2468f9c9
PB		 11691 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
11692 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 11693
dec9d5df 11694 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 11695 continue;
b38cadfb 11696
2468f9c9
PB		 11697 if (elf_sec->linked_to)
11698 {
11699 Elf_Internal_Shdr *linked_hdr
99059e56 11700 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 11701 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 11702 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 11703
11704 if (linked_sec_arm_data == NULL)
99059e56 11705 continue;
2468f9c9
PB		 11706
11707 /* Link this .ARM.exidx section back from the text section it
99059e56 11708 describes. */
2468f9c9
PB		 11709 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
11710 }
11711 }
11712 }
11713
11714 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
11715 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 11716 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 11717
11718 for (i = 0; i < num_text_sections; i++)
11719 {
11720 asection *sec = text_section_order[i];
11721 asection *exidx_sec;
11722 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
11723 struct _arm_elf_section_data *exidx_arm_data;
11724 bfd_byte *contents = NULL;
11725 int deleted_exidx_bytes = 0;
11726 bfd_vma j;
11727 arm_unwind_table_edit *unwind_edit_head = NULL;
11728 arm_unwind_table_edit *unwind_edit_tail = NULL;
11729 Elf_Internal_Shdr *hdr;
11730 bfd *ibfd;
11731
11732 if (arm_data == NULL)
99059e56 11733 continue;
2468f9c9
PB		 11734
11735 exidx_sec = arm_data->u.text.arm_exidx_sec;
11736 if (exidx_sec == NULL)
11737 {
11738 /* Section has no unwind data. */
11739 if (last_unwind_type == 0 || !last_exidx_sec)
11740 continue;
11741
11742 /* Ignore zero sized sections. */
11743 if (sec->size == 0)
11744 continue;
11745
11746 insert_cantunwind_after(last_text_sec, last_exidx_sec);
11747 last_unwind_type = 0;
11748 continue;
11749 }
11750
22a8f80e
PB		 11751 /* Skip /DISCARD/ sections. */
11752 if (bfd_is_abs_section (exidx_sec->output_section))
11753 continue;
11754
2468f9c9
PB		 11755 hdr = &elf_section_data (exidx_sec)->this_hdr;
11756 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 11757 continue;
b38cadfb 11758
2468f9c9
PB		 11759 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
11760 if (exidx_arm_data == NULL)
99059e56 11761 continue;
b38cadfb 11762
2468f9c9 11763 ibfd = exidx_sec->owner;
b38cadfb 11764
2468f9c9
PB		 11765 if (hdr->contents != NULL)
11766 contents = hdr->contents;
11767 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
11768 /* An error? */
11769 continue;
11770
ac06903d
YU		 11771 if (last_unwind_type > 0)
11772 {
11773 unsigned int first_word = bfd_get_32 (ibfd, contents);
11774 /* Add cantunwind if first unwind item does not match section
11775 start. */
11776 if (first_word != sec->vma)
11777 {
11778 insert_cantunwind_after (last_text_sec, last_exidx_sec);
11779 last_unwind_type = 0;
11780 }
11781 }
11782
2468f9c9
PB		 11783 for (j = 0; j < hdr->sh_size; j += 8)
11784 {
11785 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
11786 int unwind_type;
11787 int elide = 0;
11788
11789 /* An EXIDX_CANTUNWIND entry. */
11790 if (second_word == 1)
11791 {
11792 if (last_unwind_type == 0)
11793 elide = 1;
11794 unwind_type = 0;
11795 }
11796 /* Inlined unwinding data. Merge if equal to previous. */
11797 else if ((second_word & 0x80000000) != 0)
11798 {
85fdf906
AH		 11799 if (merge_exidx_entries
11800 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 11801 elide = 1;
11802 unwind_type = 1;
11803 last_second_word = second_word;
11804 }
11805 /* Normal table entry. In theory we could merge these too,
11806 but duplicate entries are likely to be much less common. */
11807 else
11808 unwind_type = 2;
11809
491d01d3 11810 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 11811 {
11812 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
11813 DELETE_EXIDX_ENTRY, NULL, j / 8);
11814
11815 deleted_exidx_bytes += 8;
11816 }
11817
11818 last_unwind_type = unwind_type;
11819 }
11820
11821 /* Free contents if we allocated it ourselves. */
11822 if (contents != hdr->contents)
99059e56 11823 free (contents);
2468f9c9
PB		 11824
11825 /* Record edits to be applied later (in elf32_arm_write_section). */
11826 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
11827 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 11828
2468f9c9
PB		 11829 if (deleted_exidx_bytes > 0)
11830 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
11831
11832 last_exidx_sec = exidx_sec;
11833 last_text_sec = sec;
11834 }
11835
11836 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 11837 if (!bfd_link_relocatable (info) && last_exidx_sec
11838 && last_unwind_type != 0)
2468f9c9
PB		 11839 insert_cantunwind_after(last_text_sec, last_exidx_sec);
11840
11841 return TRUE;
11842}
11843
3e6b1042
DJ		 11844static bfd_boolean
11845elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
11846 bfd *ibfd, const char *name)
11847{
11848 asection *sec, *osec;
11849
3d4d4302 11850 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 11851 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
11852 return TRUE;
11853
11854 osec = sec->output_section;
11855 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
11856 return TRUE;
11857
11858 if (! bfd_set_section_contents (obfd, osec, sec->contents,
11859 sec->output_offset, sec->size))
11860 return FALSE;
11861
11862 return TRUE;
11863}
11864
11865static bfd_boolean
11866elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
11867{
11868 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 11869 asection *sec, *osec;
3e6b1042 11870
4dfe6ac6
NC		 11871 if (globals == NULL)
11872 return FALSE;
11873
3e6b1042
DJ		 11874 /* Invoke the regular ELF backend linker to do all the work. */
11875 if (!bfd_elf_final_link (abfd, info))
11876 return FALSE;
11877
fe33d2fa
CL		 11878 /* Process stub sections (eg BE8 encoding, ...). */
11879 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 11880 unsigned int i;
cdb21a0a
NS		 11881 for (i=0; i<htab->top_id; i++)
11882 {
11883 sec = htab->stub_group[i].stub_sec;
11884 /* Only process it once, in its link_sec slot. */
11885 if (sec && i == htab->stub_group[i].link_sec->id)
11886 {
11887 osec = sec->output_section;
11888 elf32_arm_write_section (abfd, info, sec, sec->contents);
11889 if (! bfd_set_section_contents (abfd, osec, sec->contents,
11890 sec->output_offset, sec->size))
11891 return FALSE;
11892 }
fe33d2fa 11893 }
fe33d2fa 11894
3e6b1042
DJ		 11895 /* Write out any glue sections now that we have created all the
11896 stubs. */
11897 if (globals->bfd_of_glue_owner != NULL)
11898 {
11899 if (! elf32_arm_output_glue_section (info, abfd,
11900 globals->bfd_of_glue_owner,
11901 ARM2THUMB_GLUE_SECTION_NAME))
11902 return FALSE;
11903
11904 if (! elf32_arm_output_glue_section (info, abfd,
11905 globals->bfd_of_glue_owner,
11906 THUMB2ARM_GLUE_SECTION_NAME))
11907 return FALSE;
11908
11909 if (! elf32_arm_output_glue_section (info, abfd,
11910 globals->bfd_of_glue_owner,
11911 VFP11_ERRATUM_VENEER_SECTION_NAME))
11912 return FALSE;
11913
a504d23a
LA		 11914 if (! elf32_arm_output_glue_section (info, abfd,
11915 globals->bfd_of_glue_owner,
11916 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
11917 return FALSE;
11918
3e6b1042
DJ		 11919 if (! elf32_arm_output_glue_section (info, abfd,
11920 globals->bfd_of_glue_owner,
11921 ARM_BX_GLUE_SECTION_NAME))
11922 return FALSE;
11923 }
11924
11925 return TRUE;
11926}
11927
5968a7b8
NC		 11928/* Return a best guess for the machine number based on the attributes. */
11929
11930static unsigned int
11931bfd_arm_get_mach_from_attributes (bfd * abfd)
11932{
11933 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
11934
11935 switch (arch)
11936 {
11937 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
11938 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
11939 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
11940
11941 case TAG_CPU_ARCH_V5TE:
11942 {
11943 char * name;
11944
11945 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
11946 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
11947
11948 if (name)
11949 {
11950 if (strcmp (name, "IWMMXT2") == 0)
11951 return bfd_mach_arm_iWMMXt2;
11952
11953 if (strcmp (name, "IWMMXT") == 0)
6034aab8 11954 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 11955
11956 if (strcmp (name, "XSCALE") == 0)
11957 {
11958 int wmmx;
11959
11960 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
11961 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
11962 switch (wmmx)
11963 {
11964 case 1: return bfd_mach_arm_iWMMXt;
11965 case 2: return bfd_mach_arm_iWMMXt2;
11966 default: return bfd_mach_arm_XScale;
11967 }
11968 }
5968a7b8
NC		 11969 }
11970
11971 return bfd_mach_arm_5TE;
11972 }
11973
11974 default:
11975 return bfd_mach_arm_unknown;
11976 }
11977}
11978
c178919b
NC		 11979/* Set the right machine number. */
11980
11981static bfd_boolean
57e8b36a 11982elf32_arm_object_p (bfd *abfd)
c178919b 11983{
5a6c6817 11984 unsigned int mach;
57e8b36a 11985
5a6c6817 11986 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 11987
5968a7b8
NC		 11988 if (mach == bfd_mach_arm_unknown)
11989 {
11990 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
11991 mach = bfd_mach_arm_ep9312;
11992 else
11993 mach = bfd_arm_get_mach_from_attributes (abfd);
11994 }
c178919b 11995
5968a7b8 11996 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 11997 return TRUE;
11998}
11999
fc830a83 12000/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 12001
b34976b6 12002static bfd_boolean
57e8b36a 12003elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 12004{
12005 if (elf_flags_init (abfd)
12006 && elf_elfheader (abfd)->e_flags != flags)
12007 {
fc830a83
NC		 12008 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
12009 {
fd2ec330 12010 if (flags & EF_ARM_INTERWORK)
d003868e
AM		 12011 (*_bfd_error_handler)
12012 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
12013 abfd);
fc830a83 12014 else
d003868e
AM		 12015 _bfd_error_handler
12016 (_("Warning: Clearing the interworking flag of %B due to outside request"),
12017 abfd);
fc830a83 12018 }
252b5132
RH		 12019 }
12020 else
12021 {
12022 elf_elfheader (abfd)->e_flags = flags;
b34976b6 12023 elf_flags_init (abfd) = TRUE;
252b5132
RH		 12024 }
12025
b34976b6 12026 return TRUE;
252b5132
RH		 12027}
12028
fc830a83 12029/* Copy backend specific data from one object module to another. */
9b485d32 12030
b34976b6 12031static bfd_boolean
57e8b36a 12032elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 12033{
12034 flagword in_flags;
12035 flagword out_flags;
12036
0ffa91dd 12037 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 12038 return TRUE;
252b5132 12039
fc830a83 12040 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 12041 out_flags = elf_elfheader (obfd)->e_flags;
12042
fc830a83
NC		 12043 if (elf_flags_init (obfd)
12044 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
12045 && in_flags != out_flags)
252b5132 12046 {
252b5132 12047 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 12048 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 12049 return FALSE;
252b5132
RH		 12050
12051 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 12052 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 12053 return FALSE;
252b5132
RH		 12054
12055 /* If the src and dest have different interworking flags
99059e56 12056 then turn off the interworking bit. */
fd2ec330 12057 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 12058 {
fd2ec330 12059 if (out_flags & EF_ARM_INTERWORK)
d003868e
AM		 12060 _bfd_error_handler
12061 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
12062 obfd, ibfd);
252b5132 12063
fd2ec330 12064 in_flags &= ~EF_ARM_INTERWORK;
252b5132 12065 }
1006ba19
PB		 12066
12067 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 12068 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
12069 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 12070 }
12071
12072 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 12073 elf_flags_init (obfd) = TRUE;
252b5132 12074
e2349352 12075 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 12076}
12077
12078/* Values for Tag_ABI_PCS_R9_use. */
12079enum
12080{
12081 AEABI_R9_V6,
12082 AEABI_R9_SB,
12083 AEABI_R9_TLS,
12084 AEABI_R9_unused
12085};
12086
12087/* Values for Tag_ABI_PCS_RW_data. */
12088enum
12089{
12090 AEABI_PCS_RW_data_absolute,
12091 AEABI_PCS_RW_data_PCrel,
12092 AEABI_PCS_RW_data_SBrel,
12093 AEABI_PCS_RW_data_unused
12094};
12095
12096/* Values for Tag_ABI_enum_size. */
12097enum
12098{
12099 AEABI_enum_unused,
12100 AEABI_enum_short,
12101 AEABI_enum_wide,
12102 AEABI_enum_forced_wide
12103};
12104
104d59d1
JM		 12105/* Determine whether an object attribute tag takes an integer, a
12106 string or both. */
906e58ca 12107
104d59d1
JM		 12108static int
12109elf32_arm_obj_attrs_arg_type (int tag)
12110{
12111 if (tag == Tag_compatibility)
3483fe2e 12112 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 12113 else if (tag == Tag_nodefaults)
3483fe2e
AS		 12114 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
12115 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
12116 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 12117 else if (tag < 32)
3483fe2e 12118 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 12119 else
3483fe2e 12120 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 12121}
12122
5aa6ff7c
AS		 12123/* The ABI defines that Tag_conformance should be emitted first, and that
12124 Tag_nodefaults should be second (if either is defined). This sets those
12125 two positions, and bumps up the position of all the remaining tags to
12126 compensate. */
12127static int
12128elf32_arm_obj_attrs_order (int num)
12129{
3de4a297 12130 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 12131 return Tag_conformance;
3de4a297 12132 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 12133 return Tag_nodefaults;
12134 if ((num - 2) < Tag_nodefaults)
12135 return num - 2;
12136 if ((num - 1) < Tag_conformance)
12137 return num - 1;
12138 return num;
12139}
12140
e8b36cd1
JM		 12141/* Attribute numbers >=64 (mod 128) can be safely ignored. */
12142static bfd_boolean
12143elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
12144{
12145 if ((tag & 127) < 64)
12146 {
12147 _bfd_error_handler
12148 (_("%B: Unknown mandatory EABI object attribute %d"),
12149 abfd, tag);
12150 bfd_set_error (bfd_error_bad_value);
12151 return FALSE;
12152 }
12153 else
12154 {
12155 _bfd_error_handler
12156 (_("Warning: %B: Unknown EABI object attribute %d"),
12157 abfd, tag);
12158 return TRUE;
12159 }
12160}
12161
91e22acd
AS		 12162/* Read the architecture from the Tag_also_compatible_with attribute, if any.
12163 Returns -1 if no architecture could be read. */
12164
12165static int
12166get_secondary_compatible_arch (bfd *abfd)
12167{
12168 obj_attribute *attr =
12169 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
12170
12171 /* Note: the tag and its argument below are uleb128 values, though
12172 currently-defined values fit in one byte for each. */
12173 if (attr->s
12174 && attr->s[0] == Tag_CPU_arch
12175 && (attr->s[1] & 128) != 128
12176 && attr->s[2] == 0)
12177 return attr->s[1];
12178
12179 /* This tag is "safely ignorable", so don't complain if it looks funny. */
12180 return -1;
12181}
12182
12183/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
12184 The tag is removed if ARCH is -1. */
12185
8e79c3df 12186static void
91e22acd 12187set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 12188{
91e22acd
AS		 12189 obj_attribute *attr =
12190 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 12191
91e22acd
AS		 12192 if (arch == -1)
12193 {
12194 attr->s = NULL;
12195 return;
8e79c3df 12196 }
91e22acd
AS		 12197
12198 /* Note: the tag and its argument below are uleb128 values, though
12199 currently-defined values fit in one byte for each. */
12200 if (!attr->s)
21d799b5 12201 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 12202 attr->s[0] = Tag_CPU_arch;
12203 attr->s[1] = arch;
12204 attr->s[2] = '\0';
8e79c3df
CM		 12205}
12206
91e22acd
AS		 12207/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
12208 into account. */
12209
12210static int
12211tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
12212 int newtag, int secondary_compat)
8e79c3df 12213{
91e22acd
AS		 12214#define T(X) TAG_CPU_ARCH_##X
12215 int tagl, tagh, result;
12216 const int v6t2[] =
12217 {
12218 T(V6T2), /* PRE_V4. */
12219 T(V6T2), /* V4. */
12220 T(V6T2), /* V4T. */
12221 T(V6T2), /* V5T. */
12222 T(V6T2), /* V5TE. */
12223 T(V6T2), /* V5TEJ. */
12224 T(V6T2), /* V6. */
12225 T(V7), /* V6KZ. */
12226 T(V6T2) /* V6T2. */
12227 };
12228 const int v6k[] =
12229 {
12230 T(V6K), /* PRE_V4. */
12231 T(V6K), /* V4. */
12232 T(V6K), /* V4T. */
12233 T(V6K), /* V5T. */
12234 T(V6K), /* V5TE. */
12235 T(V6K), /* V5TEJ. */
12236 T(V6K), /* V6. */
12237 T(V6KZ), /* V6KZ. */
12238 T(V7), /* V6T2. */
12239 T(V6K) /* V6K. */
12240 };
12241 const int v7[] =
12242 {
12243 T(V7), /* PRE_V4. */
12244 T(V7), /* V4. */
12245 T(V7), /* V4T. */
12246 T(V7), /* V5T. */
12247 T(V7), /* V5TE. */
12248 T(V7), /* V5TEJ. */
12249 T(V7), /* V6. */
12250 T(V7), /* V6KZ. */
12251 T(V7), /* V6T2. */
12252 T(V7), /* V6K. */
12253 T(V7) /* V7. */
12254 };
12255 const int v6_m[] =
12256 {
12257 -1, /* PRE_V4. */
12258 -1, /* V4. */
12259 T(V6K), /* V4T. */
12260 T(V6K), /* V5T. */
12261 T(V6K), /* V5TE. */
12262 T(V6K), /* V5TEJ. */
12263 T(V6K), /* V6. */
12264 T(V6KZ), /* V6KZ. */
12265 T(V7), /* V6T2. */
12266 T(V6K), /* V6K. */
12267 T(V7), /* V7. */
12268 T(V6_M) /* V6_M. */
12269 };
12270 const int v6s_m[] =
12271 {
12272 -1, /* PRE_V4. */
12273 -1, /* V4. */
12274 T(V6K), /* V4T. */
12275 T(V6K), /* V5T. */
12276 T(V6K), /* V5TE. */
12277 T(V6K), /* V5TEJ. */
12278 T(V6K), /* V6. */
12279 T(V6KZ), /* V6KZ. */
12280 T(V7), /* V6T2. */
12281 T(V6K), /* V6K. */
12282 T(V7), /* V7. */
12283 T(V6S_M), /* V6_M. */
12284 T(V6S_M) /* V6S_M. */
12285 };
9e3c6df6
PB		 12286 const int v7e_m[] =
12287 {
12288 -1, /* PRE_V4. */
12289 -1, /* V4. */
12290 T(V7E_M), /* V4T. */
12291 T(V7E_M), /* V5T. */
12292 T(V7E_M), /* V5TE. */
12293 T(V7E_M), /* V5TEJ. */
12294 T(V7E_M), /* V6. */
12295 T(V7E_M), /* V6KZ. */
12296 T(V7E_M), /* V6T2. */
12297 T(V7E_M), /* V6K. */
12298 T(V7E_M), /* V7. */
12299 T(V7E_M), /* V6_M. */
12300 T(V7E_M), /* V6S_M. */
12301 T(V7E_M) /* V7E_M. */
12302 };
bca38921
MGD		 12303 const int v8[] =
12304 {
12305 T(V8), /* PRE_V4. */
12306 T(V8), /* V4. */
12307 T(V8), /* V4T. */
12308 T(V8), /* V5T. */
12309 T(V8), /* V5TE. */
12310 T(V8), /* V5TEJ. */
12311 T(V8), /* V6. */
12312 T(V8), /* V6KZ. */
12313 T(V8), /* V6T2. */
12314 T(V8), /* V6K. */
12315 T(V8), /* V7. */
12316 T(V8), /* V6_M. */
12317 T(V8), /* V6S_M. */
12318 T(V8), /* V7E_M. */
12319 T(V8) /* V8. */
12320 };
2fd158eb
TP		 12321 const int v8m_baseline[] =
12322 {
12323 -1, /* PRE_V4. */
12324 -1, /* V4. */
12325 -1, /* V4T. */
12326 -1, /* V5T. */
12327 -1, /* V5TE. */
12328 -1, /* V5TEJ. */
12329 -1, /* V6. */
12330 -1, /* V6KZ. */
12331 -1, /* V6T2. */
12332 -1, /* V6K. */
12333 -1, /* V7. */
12334 T(V8M_BASE), /* V6_M. */
12335 T(V8M_BASE), /* V6S_M. */
12336 -1, /* V7E_M. */
12337 -1, /* V8. */
12338 -1,
12339 T(V8M_BASE) /* V8-M BASELINE. */
12340 };
12341 const int v8m_mainline[] =
12342 {
12343 -1, /* PRE_V4. */
12344 -1, /* V4. */
12345 -1, /* V4T. */
12346 -1, /* V5T. */
12347 -1, /* V5TE. */
12348 -1, /* V5TEJ. */
12349 -1, /* V6. */
12350 -1, /* V6KZ. */
12351 -1, /* V6T2. */
12352 -1, /* V6K. */
12353 T(V8M_MAIN), /* V7. */
12354 T(V8M_MAIN), /* V6_M. */
12355 T(V8M_MAIN), /* V6S_M. */
12356 T(V8M_MAIN), /* V7E_M. */
12357 -1, /* V8. */
12358 -1,
12359 T(V8M_MAIN), /* V8-M BASELINE. */
12360 T(V8M_MAIN) /* V8-M MAINLINE. */
12361 };
91e22acd
AS		 12362 const int v4t_plus_v6_m[] =
12363 {
12364 -1, /* PRE_V4. */
12365 -1, /* V4. */
12366 T(V4T), /* V4T. */
12367 T(V5T), /* V5T. */
12368 T(V5TE), /* V5TE. */
12369 T(V5TEJ), /* V5TEJ. */
12370 T(V6), /* V6. */
12371 T(V6KZ), /* V6KZ. */
12372 T(V6T2), /* V6T2. */
12373 T(V6K), /* V6K. */
12374 T(V7), /* V7. */
12375 T(V6_M), /* V6_M. */
12376 T(V6S_M), /* V6S_M. */
9e3c6df6 12377 T(V7E_M), /* V7E_M. */
bca38921 12378 T(V8), /* V8. */
4ed7ed8d 12379 -1, /* Unused. */
2fd158eb
TP		 12380 T(V8M_BASE), /* V8-M BASELINE. */
12381 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 12382 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
12383 };
12384 const int *comb[] =
12385 {
12386 v6t2,
12387 v6k,
12388 v7,
12389 v6_m,
12390 v6s_m,
9e3c6df6 12391 v7e_m,
bca38921 12392 v8,
4ed7ed8d 12393 NULL,
2fd158eb
TP		 12394 v8m_baseline,
12395 v8m_mainline,
91e22acd
AS		 12396 /* Pseudo-architecture. */
12397 v4t_plus_v6_m
12398 };
12399
12400 /* Check we've not got a higher architecture than we know about. */
12401
9e3c6df6 12402 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 12403 {
3895f852 12404 _bfd_error_handler (_("error: %B: Unknown CPU architecture"), ibfd);
91e22acd
AS		 12405 return -1;
12406 }
12407
12408 /* Override old tag if we have a Tag_also_compatible_with on the output. */
12409
12410 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
12411 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
12412 oldtag = T(V4T_PLUS_V6_M);
12413
12414 /* And override the new tag if we have a Tag_also_compatible_with on the
12415 input. */
12416
12417 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
12418 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
12419 newtag = T(V4T_PLUS_V6_M);
12420
12421 tagl = (oldtag < newtag) ? oldtag : newtag;
12422 result = tagh = (oldtag > newtag) ? oldtag : newtag;
12423
12424 /* Architectures before V6KZ add features monotonically. */
12425 if (tagh <= TAG_CPU_ARCH_V6KZ)
12426 return result;
12427
4ed7ed8d 12428 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 12429
12430 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
12431 as the canonical version. */
12432 if (result == T(V4T_PLUS_V6_M))
12433 {
12434 result = T(V4T);
12435 *secondary_compat_out = T(V6_M);
12436 }
12437 else
12438 *secondary_compat_out = -1;
12439
12440 if (result == -1)
12441 {
3895f852 12442 _bfd_error_handler (_("error: %B: Conflicting CPU architectures %d/%d"),
91e22acd
AS		 12443 ibfd, oldtag, newtag);
12444 return -1;
12445 }
12446
12447 return result;
12448#undef T
8e79c3df
CM		 12449}
12450
ac56ee8f
MGD		 12451/* Query attributes object to see if integer divide instructions may be
12452 present in an object. */
12453static bfd_boolean
12454elf32_arm_attributes_accept_div (const obj_attribute *attr)
12455{
12456 int arch = attr[Tag_CPU_arch].i;
12457 int profile = attr[Tag_CPU_arch_profile].i;
12458
12459 switch (attr[Tag_DIV_use].i)
12460 {
12461 case 0:
12462 /* Integer divide allowed if instruction contained in archetecture. */
12463 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
12464 return TRUE;
12465 else if (arch >= TAG_CPU_ARCH_V7E_M)
12466 return TRUE;
12467 else
12468 return FALSE;
12469
12470 case 1:
12471 /* Integer divide explicitly prohibited. */
12472 return FALSE;
12473
12474 default:
12475 /* Unrecognised case - treat as allowing divide everywhere. */
12476 case 2:
12477 /* Integer divide allowed in ARM state. */
12478 return TRUE;
12479 }
12480}
12481
12482/* Query attributes object to see if integer divide instructions are
12483 forbidden to be in the object. This is not the inverse of
12484 elf32_arm_attributes_accept_div. */
12485static bfd_boolean
12486elf32_arm_attributes_forbid_div (const obj_attribute *attr)
12487{
12488 return attr[Tag_DIV_use].i == 1;
12489}
12490
ee065d83
PB		 12491/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
12492 are conflicting attributes. */
906e58ca 12493
ee065d83
PB		 12494static bfd_boolean
12495elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd)
12496{
104d59d1
JM		 12497 obj_attribute *in_attr;
12498 obj_attribute *out_attr;
ee065d83
PB		 12499 /* Some tags have 0 = don't care, 1 = strong requirement,
12500 2 = weak requirement. */
91e22acd 12501 static const int order_021[3] = {0, 2, 1};
ee065d83 12502 int i;
91e22acd 12503 bfd_boolean result = TRUE;
9274e9de 12504 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 12505
3e6b1042
DJ		 12506 /* Skip the linker stubs file. This preserves previous behavior
12507 of accepting unknown attributes in the first input file - but
12508 is that a bug? */
12509 if (ibfd->flags & BFD_LINKER_CREATED)
12510 return TRUE;
12511
9274e9de
TG		 12512 /* Skip any input that hasn't attribute section.
12513 This enables to link object files without attribute section with
12514 any others. */
12515 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
12516 return TRUE;
12517
104d59d1 12518 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 12519 {
12520 /* This is the first object. Copy the attributes. */
104d59d1 12521 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 12522
cd21e546
MGD		 12523 out_attr = elf_known_obj_attributes_proc (obfd);
12524
004ae526
PB		 12525 /* Use the Tag_null value to indicate the attributes have been
12526 initialized. */
cd21e546 12527 out_attr[0].i = 1;
004ae526 12528
cd21e546
MGD		 12529 /* We do not output objects with Tag_MPextension_use_legacy - we move
12530 the attribute's value to Tag_MPextension_use. */
12531 if (out_attr[Tag_MPextension_use_legacy].i != 0)
12532 {
12533 if (out_attr[Tag_MPextension_use].i != 0
12534 && out_attr[Tag_MPextension_use_legacy].i
99059e56 12535 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 12536 {
12537 _bfd_error_handler
12538 (_("Error: %B has both the current and legacy "
12539 "Tag_MPextension_use attributes"), ibfd);
12540 result = FALSE;
12541 }
12542
12543 out_attr[Tag_MPextension_use] =
12544 out_attr[Tag_MPextension_use_legacy];
12545 out_attr[Tag_MPextension_use_legacy].type = 0;
12546 out_attr[Tag_MPextension_use_legacy].i = 0;
12547 }
12548
12549 return result;
ee065d83
PB		 12550 }
12551
104d59d1
JM		 12552 in_attr = elf_known_obj_attributes_proc (ibfd);
12553 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 12554 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
12555 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
12556 {
5c294fee
TG		 12557 /* Ignore mismatches if the object doesn't use floating point or is
12558 floating point ABI independent. */
12559 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
12560 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
12561 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 12562 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 12563 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
12564 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 12565 {
12566 _bfd_error_handler
3895f852 12567 (_("error: %B uses VFP register arguments, %B does not"),
deddc40b
NS		 12568 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
12569 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 12570 result = FALSE;
ee065d83
PB		 12571 }
12572 }
12573
3de4a297 12574 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 12575 {
12576 /* Merge this attribute with existing attributes. */
12577 switch (i)
12578 {
12579 case Tag_CPU_raw_name:
12580 case Tag_CPU_name:
6a631e86 12581 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 12582 break;
12583
12584 case Tag_ABI_optimization_goals:
12585 case Tag_ABI_FP_optimization_goals:
12586 /* Use the first value seen. */
12587 break;
12588
12589 case Tag_CPU_arch:
91e22acd
AS		 12590 {
12591 int secondary_compat = -1, secondary_compat_out = -1;
12592 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 12593 int arch_attr;
12594 static const char *name_table[] =
12595 {
91e22acd
AS		 12596 /* These aren't real CPU names, but we can't guess
12597 that from the architecture version alone. */
12598 "Pre v4",
12599 "ARM v4",
12600 "ARM v4T",
12601 "ARM v5T",
12602 "ARM v5TE",
12603 "ARM v5TEJ",
12604 "ARM v6",
12605 "ARM v6KZ",
12606 "ARM v6T2",
12607 "ARM v6K",
12608 "ARM v7",
12609 "ARM v6-M",
bca38921 12610 "ARM v6S-M",
2fd158eb
TP		 12611 "ARM v8",
12612 "",
12613 "ARM v8-M.baseline",
12614 "ARM v8-M.mainline",
91e22acd
AS		 12615 };
12616
12617 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
12618 secondary_compat = get_secondary_compatible_arch (ibfd);
12619 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 12620 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
12621 &secondary_compat_out,
12622 in_attr[i].i,
12623 secondary_compat);
12624
12625 /* Return with error if failed to merge. */
12626 if (arch_attr == -1)
12627 return FALSE;
12628
12629 out_attr[i].i = arch_attr;
12630
91e22acd
AS		 12631 set_secondary_compatible_arch (obfd, secondary_compat_out);
12632
12633 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
12634 if (out_attr[i].i == saved_out_attr)
12635 ; /* Leave the names alone. */
12636 else if (out_attr[i].i == in_attr[i].i)
12637 {
12638 /* The output architecture has been changed to match the
12639 input architecture. Use the input names. */
12640 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
12641 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
12642 : NULL;
12643 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
12644 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
12645 : NULL;
12646 }
12647 else
12648 {
12649 out_attr[Tag_CPU_name].s = NULL;
12650 out_attr[Tag_CPU_raw_name].s = NULL;
12651 }
12652
12653 /* If we still don't have a value for Tag_CPU_name,
12654 make one up now. Tag_CPU_raw_name remains blank. */
12655 if (out_attr[Tag_CPU_name].s == NULL
12656 && out_attr[i].i < ARRAY_SIZE (name_table))
12657 out_attr[Tag_CPU_name].s =
12658 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
12659 }
12660 break;
12661
ee065d83
PB		 12662 case Tag_ARM_ISA_use:
12663 case Tag_THUMB_ISA_use:
ee065d83 12664 case Tag_WMMX_arch:
91e22acd
AS		 12665 case Tag_Advanced_SIMD_arch:
12666 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 12667 case Tag_ABI_FP_rounding:
ee065d83
PB		 12668 case Tag_ABI_FP_exceptions:
12669 case Tag_ABI_FP_user_exceptions:
12670 case Tag_ABI_FP_number_model:
75375b3e 12671 case Tag_FP_HP_extension:
91e22acd
AS		 12672 case Tag_CPU_unaligned_access:
12673 case Tag_T2EE_use:
91e22acd 12674 case Tag_MPextension_use:
ee065d83
PB		 12675 /* Use the largest value specified. */
12676 if (in_attr[i].i > out_attr[i].i)
12677 out_attr[i].i = in_attr[i].i;
12678 break;
12679
75375b3e 12680 case Tag_ABI_align_preserved:
91e22acd
AS		 12681 case Tag_ABI_PCS_RO_data:
12682 /* Use the smallest value specified. */
12683 if (in_attr[i].i < out_attr[i].i)
12684 out_attr[i].i = in_attr[i].i;
12685 break;
12686
75375b3e 12687 case Tag_ABI_align_needed:
91e22acd 12688 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 12689 && (in_attr[Tag_ABI_align_preserved].i == 0
12690 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 12691 {
91e22acd
AS		 12692 /* This error message should be enabled once all non-conformant
12693 binaries in the toolchain have had the attributes set
12694 properly.
ee065d83 12695 _bfd_error_handler
3895f852 12696 (_("error: %B: 8-byte data alignment conflicts with %B"),
91e22acd
AS		 12697 obfd, ibfd);
12698 result = FALSE; */
ee065d83 12699 }
91e22acd
AS		 12700 /* Fall through. */
12701 case Tag_ABI_FP_denormal:
12702 case Tag_ABI_PCS_GOT_use:
12703 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
12704 value if greater than 2 (for future-proofing). */
12705 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
12706 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
12707 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 12708 out_attr[i].i = in_attr[i].i;
12709 break;
91e22acd 12710
75375b3e
MGD		 12711 case Tag_Virtualization_use:
12712 /* The virtualization tag effectively stores two bits of
12713 information: the intended use of TrustZone (in bit 0), and the
12714 intended use of Virtualization (in bit 1). */
12715 if (out_attr[i].i == 0)
12716 out_attr[i].i = in_attr[i].i;
12717 else if (in_attr[i].i != 0
12718 && in_attr[i].i != out_attr[i].i)
12719 {
12720 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
12721 out_attr[i].i = 3;
12722 else
12723 {
12724 _bfd_error_handler
12725 (_("error: %B: unable to merge virtualization attributes "
12726 "with %B"),
12727 obfd, ibfd);
12728 result = FALSE;
12729 }
12730 }
12731 break;
91e22acd
AS		 12732
12733 case Tag_CPU_arch_profile:
12734 if (out_attr[i].i != in_attr[i].i)
12735 {
12736 /* 0 will merge with anything.
12737 'A' and 'S' merge to 'A'.
12738 'R' and 'S' merge to 'R'.
99059e56 12739 'M' and 'A|R|S' is an error. */
91e22acd
AS		 12740 if (out_attr[i].i == 0
12741 || (out_attr[i].i == 'S'
12742 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
12743 out_attr[i].i = in_attr[i].i;
12744 else if (in_attr[i].i == 0
12745 || (in_attr[i].i == 'S'
12746 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 12747 ; /* Do nothing. */
91e22acd
AS		 12748 else
12749 {
12750 _bfd_error_handler
3895f852 12751 (_("error: %B: Conflicting architecture profiles %c/%c"),
91e22acd
AS		 12752 ibfd,
12753 in_attr[i].i ? in_attr[i].i : '0',
12754 out_attr[i].i ? out_attr[i].i : '0');
12755 result = FALSE;
12756 }
12757 }
12758 break;
15afaa63
TP		 12759
12760 case Tag_DSP_extension:
12761 /* No need to change output value if any of:
12762 - pre (<=) ARMv5T input architecture (do not have DSP)
12763 - M input profile not ARMv7E-M and do not have DSP. */
12764 if (in_attr[Tag_CPU_arch].i <= 3
12765 || (in_attr[Tag_CPU_arch_profile].i == 'M'
12766 && in_attr[Tag_CPU_arch].i != 13
12767 && in_attr[i].i == 0))
12768 ; /* Do nothing. */
12769 /* Output value should be 0 if DSP part of architecture, ie.
12770 - post (>=) ARMv5te architecture output
12771 - A, R or S profile output or ARMv7E-M output architecture. */
12772 else if (out_attr[Tag_CPU_arch].i >= 4
12773 && (out_attr[Tag_CPU_arch_profile].i == 'A'
12774 || out_attr[Tag_CPU_arch_profile].i == 'R'
12775 || out_attr[Tag_CPU_arch_profile].i == 'S'
12776 || out_attr[Tag_CPU_arch].i == 13))
12777 out_attr[i].i = 0;
12778 /* Otherwise, DSP instructions are added and not part of output
12779 architecture. */
12780 else
12781 out_attr[i].i = 1;
12782 break;
12783
75375b3e 12784 case Tag_FP_arch:
62f3b8c8 12785 {
4547cb56
NC		 12786 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
12787 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
12788 when it's 0. It might mean absence of FP hardware if
99654aaf 12789 Tag_FP_arch is zero. */
4547cb56 12790
a715796b 12791#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 12792 static const struct
12793 {
12794 int ver;
12795 int regs;
bca38921 12796 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 12797 {
12798 {0, 0},
12799 {1, 16},
12800 {2, 16},
12801 {3, 32},
12802 {3, 16},
12803 {4, 32},
bca38921 12804 {4, 16},
a715796b
TG		 12805 {8, 32},
12806 {8, 16}
62f3b8c8
PB		 12807 };
12808 int ver;
12809 int regs;
12810 int newval;
12811
4547cb56
NC		 12812 /* If the output has no requirement about FP hardware,
12813 follow the requirement of the input. */
12814 if (out_attr[i].i == 0)
12815 {
12816 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
12817 out_attr[i].i = in_attr[i].i;
12818 out_attr[Tag_ABI_HardFP_use].i
12819 = in_attr[Tag_ABI_HardFP_use].i;
12820 break;
12821 }
12822 /* If the input has no requirement about FP hardware, do
12823 nothing. */
12824 else if (in_attr[i].i == 0)
12825 {
12826 BFD_ASSERT (in_attr[Tag_ABI_HardFP_use].i == 0);
12827 break;
12828 }
12829
12830 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 12831 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 12832
12833 /* If both the input and the output have zero Tag_ABI_HardFP_use,
12834 do nothing. */
12835 if (in_attr[Tag_ABI_HardFP_use].i == 0
12836 && out_attr[Tag_ABI_HardFP_use].i == 0)
12837 ;
12838 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 12839 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 12840 else if (in_attr[Tag_ABI_HardFP_use].i
12841 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 12842 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 12843
12844 /* Now we can handle Tag_FP_arch. */
12845
bca38921
MGD		 12846 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
12847 pick the biggest. */
12848 if (in_attr[i].i >= VFP_VERSION_COUNT
12849 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 12850 {
12851 out_attr[i] = in_attr[i];
12852 break;
12853 }
12854 /* The output uses the superset of input features
12855 (ISA version) and registers. */
12856 ver = vfp_versions[in_attr[i].i].ver;
12857 if (ver < vfp_versions[out_attr[i].i].ver)
12858 ver = vfp_versions[out_attr[i].i].ver;
12859 regs = vfp_versions[in_attr[i].i].regs;
12860 if (regs < vfp_versions[out_attr[i].i].regs)
12861 regs = vfp_versions[out_attr[i].i].regs;
12862 /* This assumes all possible supersets are also a valid
99059e56 12863 options. */
bca38921 12864 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 12865 {
12866 if (regs == vfp_versions[newval].regs
12867 && ver == vfp_versions[newval].ver)
12868 break;
12869 }
12870 out_attr[i].i = newval;
12871 }
b1cc4aeb 12872 break;
ee065d83
PB		 12873 case Tag_PCS_config:
12874 if (out_attr[i].i == 0)
12875 out_attr[i].i = in_attr[i].i;
b6009aca 12876 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 12877 {
12878 /* It's sometimes ok to mix different configs, so this is only
99059e56 12879 a warning. */
ee065d83
PB		 12880 _bfd_error_handler
12881 (_("Warning: %B: Conflicting platform configuration"), ibfd);
12882 }
12883 break;
12884 case Tag_ABI_PCS_R9_use:
004ae526
PB		 12885 if (in_attr[i].i != out_attr[i].i
12886 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 12887 && in_attr[i].i != AEABI_R9_unused)
12888 {
12889 _bfd_error_handler
3895f852 12890 (_("error: %B: Conflicting use of R9"), ibfd);
91e22acd 12891 result = FALSE;
ee065d83
PB		 12892 }
12893 if (out_attr[i].i == AEABI_R9_unused)
12894 out_attr[i].i = in_attr[i].i;
12895 break;
12896 case Tag_ABI_PCS_RW_data:
12897 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
12898 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
12899 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
12900 {
12901 _bfd_error_handler
3895f852 12902 (_("error: %B: SB relative addressing conflicts with use of R9"),
ee065d83 12903 ibfd);
91e22acd 12904 result = FALSE;
ee065d83
PB		 12905 }
12906 /* Use the smallest value specified. */
12907 if (in_attr[i].i < out_attr[i].i)
12908 out_attr[i].i = in_attr[i].i;
12909 break;
ee065d83 12910 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 12911 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
12912 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 12913 {
12914 _bfd_error_handler
a9dc9481
JM		 12915 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
12916 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 12917 }
a9dc9481 12918 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 12919 out_attr[i].i = in_attr[i].i;
12920 break;
ee065d83
PB		 12921 case Tag_ABI_enum_size:
12922 if (in_attr[i].i != AEABI_enum_unused)
12923 {
12924 if (out_attr[i].i == AEABI_enum_unused
12925 || out_attr[i].i == AEABI_enum_forced_wide)
12926 {
12927 /* The existing object is compatible with anything.
12928 Use whatever requirements the new object has. */
12929 out_attr[i].i = in_attr[i].i;
12930 }
12931 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 12932 && out_attr[i].i != in_attr[i].i
0ffa91dd 12933 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 12934 {
91e22acd 12935 static const char *aeabi_enum_names[] =
bf21ed78 12936 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 12937 const char *in_name =
12938 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
12939 ? aeabi_enum_names[in_attr[i].i]
12940 : "<unknown>";
12941 const char *out_name =
12942 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
12943 ? aeabi_enum_names[out_attr[i].i]
12944 : "<unknown>";
ee065d83 12945 _bfd_error_handler
bf21ed78 12946 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 12947 ibfd, in_name, out_name);
ee065d83
PB		 12948 }
12949 }
12950 break;
12951 case Tag_ABI_VFP_args:
12952 /* Aready done. */
12953 break;
12954 case Tag_ABI_WMMX_args:
12955 if (in_attr[i].i != out_attr[i].i)
12956 {
12957 _bfd_error_handler
3895f852 12958 (_("error: %B uses iWMMXt register arguments, %B does not"),
ee065d83 12959 ibfd, obfd);
91e22acd 12960 result = FALSE;
ee065d83
PB		 12961 }
12962 break;
7b86a9fa
AS		 12963 case Tag_compatibility:
12964 /* Merged in target-independent code. */
12965 break;
91e22acd 12966 case Tag_ABI_HardFP_use:
4547cb56 12967 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 12968 break;
12969 case Tag_ABI_FP_16bit_format:
12970 if (in_attr[i].i != 0 && out_attr[i].i != 0)
12971 {
12972 if (in_attr[i].i != out_attr[i].i)
12973 {
12974 _bfd_error_handler
3895f852 12975 (_("error: fp16 format mismatch between %B and %B"),
91e22acd
AS		 12976 ibfd, obfd);
12977 result = FALSE;
12978 }
12979 }
12980 if (in_attr[i].i != 0)
12981 out_attr[i].i = in_attr[i].i;
12982 break;
7b86a9fa 12983
cd21e546 12984 case Tag_DIV_use:
ac56ee8f
MGD		 12985 /* A value of zero on input means that the divide instruction may
12986 be used if available in the base architecture as specified via
12987 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
12988 the user did not want divide instructions. A value of 2
12989 explicitly means that divide instructions were allowed in ARM
12990 and Thumb state. */
12991 if (in_attr[i].i == out_attr[i].i)
12992 /* Do nothing. */ ;
12993 else if (elf32_arm_attributes_forbid_div (in_attr)
12994 && !elf32_arm_attributes_accept_div (out_attr))
12995 out_attr[i].i = 1;
12996 else if (elf32_arm_attributes_forbid_div (out_attr)
12997 && elf32_arm_attributes_accept_div (in_attr))
12998 out_attr[i].i = in_attr[i].i;
12999 else if (in_attr[i].i == 2)
13000 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 13001 break;
13002
13003 case Tag_MPextension_use_legacy:
13004 /* We don't output objects with Tag_MPextension_use_legacy - we
13005 move the value to Tag_MPextension_use. */
13006 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
13007 {
13008 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
13009 {
13010 _bfd_error_handler
13011 (_("%B has has both the current and legacy "
b38cadfb 13012 "Tag_MPextension_use attributes"),
cd21e546
MGD		 13013 ibfd);
13014 result = FALSE;
13015 }
13016 }
13017
13018 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
13019 out_attr[Tag_MPextension_use] = in_attr[i];
13020
13021 break;
13022
91e22acd 13023 case Tag_nodefaults:
2d0bb761
AS		 13024 /* This tag is set if it exists, but the value is unused (and is
13025 typically zero). We don't actually need to do anything here -
13026 the merge happens automatically when the type flags are merged
13027 below. */
91e22acd
AS		 13028 break;
13029 case Tag_also_compatible_with:
13030 /* Already done in Tag_CPU_arch. */
13031 break;
13032 case Tag_conformance:
13033 /* Keep the attribute if it matches. Throw it away otherwise.
13034 No attribute means no claim to conform. */
13035 if (!in_attr[i].s || !out_attr[i].s
13036 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
13037 out_attr[i].s = NULL;
13038 break;
3cfad14c 13039
91e22acd 13040 default:
e8b36cd1
JM		 13041 result
13042 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 13043 }
13044
13045 /* If out_attr was copied from in_attr then it won't have a type yet. */
13046 if (in_attr[i].type && !out_attr[i].type)
13047 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 13048 }
13049
104d59d1 13050 /* Merge Tag_compatibility attributes and any common GNU ones. */
5488d830
MGD		 13051 if (!_bfd_elf_merge_object_attributes (ibfd, obfd))
13052 return FALSE;
ee065d83 13053
104d59d1 13054 /* Check for any attributes not known on ARM. */
e8b36cd1 13055 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 13056
91e22acd 13057 return result;
252b5132
RH		 13058}
13059
3a4a14e9
PB		 13060
13061/* Return TRUE if the two EABI versions are incompatible. */
13062
13063static bfd_boolean
13064elf32_arm_versions_compatible (unsigned iver, unsigned over)
13065{
13066 /* v4 and v5 are the same spec before and after it was released,
13067 so allow mixing them. */
13068 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
13069 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
13070 return TRUE;
13071
13072 return (iver == over);
13073}
13074
252b5132
RH		 13075/* Merge backend specific data from an object file to the output
13076 object file when linking. */
9b485d32 13077
b34976b6 13078static bfd_boolean
21d799b5 13079elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd);
252b5132 13080
9b485d32
NC		 13081/* Display the flags field. */
13082
b34976b6 13083static bfd_boolean
57e8b36a 13084elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 13085{
fc830a83
NC		 13086 FILE * file = (FILE *) ptr;
13087 unsigned long flags;
252b5132
RH		 13088
13089 BFD_ASSERT (abfd != NULL && ptr != NULL);
13090
13091 /* Print normal ELF private data. */
13092 _bfd_elf_print_private_bfd_data (abfd, ptr);
13093
fc830a83 13094 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 13095 /* Ignore init flag - it may not be set, despite the flags field
13096 containing valid data. */
252b5132
RH		 13097
13098 /* xgettext:c-format */
9b485d32 13099 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 13100
fc830a83
NC		 13101 switch (EF_ARM_EABI_VERSION (flags))
13102 {
13103 case EF_ARM_EABI_UNKNOWN:
4cc11e76 13104 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 13105 official ARM ELF extended ABI. Hence they are only decoded if
13106 the EABI version is not set. */
fd2ec330 13107 if (flags & EF_ARM_INTERWORK)
9b485d32 13108 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 13109
fd2ec330 13110 if (flags & EF_ARM_APCS_26)
6c571f00 13111 fprintf (file, " [APCS-26]");
fc830a83 13112 else
6c571f00 13113 fprintf (file, " [APCS-32]");
9a5aca8c 13114
96a846ea
RE		 13115 if (flags & EF_ARM_VFP_FLOAT)
13116 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 13117 else if (flags & EF_ARM_MAVERICK_FLOAT)
13118 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 13119 else
13120 fprintf (file, _(" [FPA float format]"));
13121
fd2ec330 13122 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 13123 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 13124
fd2ec330 13125 if (flags & EF_ARM_PIC)
9b485d32 13126 fprintf (file, _(" [position independent]"));
fc830a83 13127
fd2ec330 13128 if (flags & EF_ARM_NEW_ABI)
9b485d32 13129 fprintf (file, _(" [new ABI]"));
9a5aca8c 13130
fd2ec330 13131 if (flags & EF_ARM_OLD_ABI)
9b485d32 13132 fprintf (file, _(" [old ABI]"));
9a5aca8c 13133
fd2ec330 13134 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 13135 fprintf (file, _(" [software FP]"));
9a5aca8c 13136
96a846ea
RE		 13137 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
13138 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 13139 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
13140 | EF_ARM_MAVERICK_FLOAT);
fc830a83 13141 break;
9a5aca8c 13142
fc830a83 13143 case EF_ARM_EABI_VER1:
9b485d32 13144 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 13145
fc830a83 13146 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 13147 fprintf (file, _(" [sorted symbol table]"));
fc830a83 13148 else
9b485d32 13149 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 13150
fc830a83
NC		 13151 flags &= ~ EF_ARM_SYMSARESORTED;
13152 break;
9a5aca8c 13153
fd2ec330
PB		 13154 case EF_ARM_EABI_VER2:
13155 fprintf (file, _(" [Version2 EABI]"));
13156
13157 if (flags & EF_ARM_SYMSARESORTED)
13158 fprintf (file, _(" [sorted symbol table]"));
13159 else
13160 fprintf (file, _(" [unsorted symbol table]"));
13161
13162 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
13163 fprintf (file, _(" [dynamic symbols use segment index]"));
13164
13165 if (flags & EF_ARM_MAPSYMSFIRST)
13166 fprintf (file, _(" [mapping symbols precede others]"));
13167
99e4ae17 13168 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 13169 | EF_ARM_MAPSYMSFIRST);
13170 break;
13171
d507cf36
PB		 13172 case EF_ARM_EABI_VER3:
13173 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 13174 break;
13175
13176 case EF_ARM_EABI_VER4:
13177 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 13178 goto eabi;
d507cf36 13179
3a4a14e9
PB		 13180 case EF_ARM_EABI_VER5:
13181 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 13182
13183 if (flags & EF_ARM_ABI_FLOAT_SOFT)
13184 fprintf (file, _(" [soft-float ABI]"));
13185
13186 if (flags & EF_ARM_ABI_FLOAT_HARD)
13187 fprintf (file, _(" [hard-float ABI]"));
13188
13189 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
13190
3a4a14e9 13191 eabi:
d507cf36
PB		 13192 if (flags & EF_ARM_BE8)
13193 fprintf (file, _(" [BE8]"));
13194
13195 if (flags & EF_ARM_LE8)
13196 fprintf (file, _(" [LE8]"));
13197
13198 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
13199 break;
13200
fc830a83 13201 default:
9b485d32 13202 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 13203 break;
13204 }
252b5132 13205
fc830a83 13206 flags &= ~ EF_ARM_EABIMASK;
252b5132 13207
fc830a83 13208 if (flags & EF_ARM_RELEXEC)
9b485d32 13209 fprintf (file, _(" [relocatable executable]"));
252b5132 13210
a5721edd 13211 flags &= ~EF_ARM_RELEXEC;
fc830a83
NC		 13212
13213 if (flags)
9b485d32 13214 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 13215
252b5132
RH		 13216 fputc ('\n', file);
13217
b34976b6 13218 return TRUE;
252b5132
RH		 13219}
13220
13221static int
57e8b36a 13222elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 13223{
2f0ca46a
NC		 13224 switch (ELF_ST_TYPE (elf_sym->st_info))
13225 {
13226 case STT_ARM_TFUNC:
13227 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 13228
2f0ca46a
NC		 13229 case STT_ARM_16BIT:
13230 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
13231 This allows us to distinguish between data used by Thumb instructions
13232 and non-data (which is probably code) inside Thumb regions of an
13233 executable. */
1a0eb693 13234 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 13235 return ELF_ST_TYPE (elf_sym->st_info);
13236 break;
9a5aca8c 13237
ce855c42
NC		 13238 default:
13239 break;
2f0ca46a
NC		 13240 }
13241
13242 return type;
252b5132 13243}
f21f3fe0 13244
252b5132 13245static asection *
07adf181
AM		 13246elf32_arm_gc_mark_hook (asection *sec,
13247 struct bfd_link_info *info,
13248 Elf_Internal_Rela *rel,
13249 struct elf_link_hash_entry *h,
13250 Elf_Internal_Sym *sym)
252b5132
RH		 13251{
13252 if (h != NULL)
07adf181 13253 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 13254 {
13255 case R_ARM_GNU_VTINHERIT:
13256 case R_ARM_GNU_VTENTRY:
07adf181
AM		 13257 return NULL;
13258 }
9ad5cbcf 13259
07adf181 13260 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 13261}
13262
780a67af
NC		 13263/* Update the got entry reference counts for the section being removed. */
13264
b34976b6 13265static bfd_boolean
ba93b8ac
DJ		 13266elf32_arm_gc_sweep_hook (bfd * abfd,
13267 struct bfd_link_info * info,
13268 asection * sec,
13269 const Elf_Internal_Rela * relocs)
252b5132 13270{
5e681ec4
PB		 13271 Elf_Internal_Shdr *symtab_hdr;
13272 struct elf_link_hash_entry **sym_hashes;
13273 bfd_signed_vma *local_got_refcounts;
13274 const Elf_Internal_Rela *rel, *relend;
eb043451
PB		 13275 struct elf32_arm_link_hash_table * globals;
13276
0e1862bb 13277 if (bfd_link_relocatable (info))
7dda2462
TG		 13278 return TRUE;
13279
eb043451 13280 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13281 if (globals == NULL)
13282 return FALSE;
5e681ec4
PB		 13283
13284 elf_section_data (sec)->local_dynrel = NULL;
13285
0ffa91dd 13286 symtab_hdr = & elf_symtab_hdr (abfd);
5e681ec4
PB		 13287 sym_hashes = elf_sym_hashes (abfd);
13288 local_got_refcounts = elf_local_got_refcounts (abfd);
13289
906e58ca 13290 check_use_blx (globals);
bd97cb95 13291
5e681ec4
PB		 13292 relend = relocs + sec->reloc_count;
13293 for (rel = relocs; rel < relend; rel++)
eb043451 13294 {
3eb128b2
AM		 13295 unsigned long r_symndx;
13296 struct elf_link_hash_entry *h = NULL;
f6e32f6d 13297 struct elf32_arm_link_hash_entry *eh;
eb043451 13298 int r_type;
34e77a92 13299 bfd_boolean call_reloc_p;
f6e32f6d
RS		 13300 bfd_boolean may_become_dynamic_p;
13301 bfd_boolean may_need_local_target_p;
34e77a92
RS		 13302 union gotplt_union *root_plt;
13303 struct arm_plt_info *arm_plt;
5e681ec4 13304
3eb128b2
AM		 13305 r_symndx = ELF32_R_SYM (rel->r_info);
13306 if (r_symndx >= symtab_hdr->sh_info)
13307 {
13308 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
13309 while (h->root.type == bfd_link_hash_indirect
13310 || h->root.type == bfd_link_hash_warning)
13311 h = (struct elf_link_hash_entry *) h->root.u.i.link;
13312 }
f6e32f6d
RS		 13313 eh = (struct elf32_arm_link_hash_entry *) h;
13314
34e77a92 13315 call_reloc_p = FALSE;
f6e32f6d
RS		 13316 may_become_dynamic_p = FALSE;
13317 may_need_local_target_p = FALSE;
3eb128b2 13318
eb043451 13319 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 13320 r_type = arm_real_reloc_type (globals, r_type);
eb043451
PB		 13321 switch (r_type)
13322 {
13323 case R_ARM_GOT32:
eb043451 13324 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 13325 case R_ARM_TLS_GD32:
13326 case R_ARM_TLS_IE32:
3eb128b2 13327 if (h != NULL)
eb043451 13328 {
eb043451
PB		 13329 if (h->got.refcount > 0)
13330 h->got.refcount -= 1;
13331 }
13332 else if (local_got_refcounts != NULL)
13333 {
13334 if (local_got_refcounts[r_symndx] > 0)
13335 local_got_refcounts[r_symndx] -= 1;
13336 }
13337 break;
13338
ba93b8ac 13339 case R_ARM_TLS_LDM32:
4dfe6ac6 13340 globals->tls_ldm_got.refcount -= 1;
ba93b8ac
DJ		 13341 break;
13342
eb043451
PB		 13343 case R_ARM_PC24:
13344 case R_ARM_PLT32:
5b5bb741
PB		 13345 case R_ARM_CALL:
13346 case R_ARM_JUMP24:
eb043451 13347 case R_ARM_PREL31:
c19d1205 13348 case R_ARM_THM_CALL:
bd97cb95
DJ		 13349 case R_ARM_THM_JUMP24:
13350 case R_ARM_THM_JUMP19:
34e77a92 13351 call_reloc_p = TRUE;
f6e32f6d
RS		 13352 may_need_local_target_p = TRUE;
13353 break;
13354
13355 case R_ARM_ABS12:
13356 if (!globals->vxworks_p)
13357 {
13358 may_need_local_target_p = TRUE;
13359 break;
13360 }
13361 /* Fall through. */
13362 case R_ARM_ABS32:
13363 case R_ARM_ABS32_NOI:
13364 case R_ARM_REL32:
13365 case R_ARM_REL32_NOI:
b6895b4f
PB		 13366 case R_ARM_MOVW_ABS_NC:
13367 case R_ARM_MOVT_ABS:
13368 case R_ARM_MOVW_PREL_NC:
13369 case R_ARM_MOVT_PREL:
13370 case R_ARM_THM_MOVW_ABS_NC:
13371 case R_ARM_THM_MOVT_ABS:
13372 case R_ARM_THM_MOVW_PREL_NC:
13373 case R_ARM_THM_MOVT_PREL:
b7693d02 13374 /* Should the interworking branches be here also? */
0e1862bb 13375 if ((bfd_link_pic (info) || globals->root.is_relocatable_executable)
34e77a92
RS		 13376 && (sec->flags & SEC_ALLOC) != 0)
13377 {
13378 if (h == NULL
469a3493 13379 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 13380 {
13381 call_reloc_p = TRUE;
13382 may_need_local_target_p = TRUE;
13383 }
13384 else
13385 may_become_dynamic_p = TRUE;
13386 }
f6e32f6d
RS		 13387 else
13388 may_need_local_target_p = TRUE;
13389 break;
b7693d02 13390
f6e32f6d
RS		 13391 default:
13392 break;
13393 }
5e681ec4 13394
34e77a92
RS		 13395 if (may_need_local_target_p
13396 && elf32_arm_get_plt_info (abfd, eh, r_symndx, &root_plt, &arm_plt))
f6e32f6d 13397 {
27586251
HPN		 13398 /* If PLT refcount book-keeping is wrong and too low, we'll
13399 see a zero value (going to -1) for the root PLT reference
13400 count. */
13401 if (root_plt->refcount >= 0)
13402 {
13403 BFD_ASSERT (root_plt->refcount != 0);
13404 root_plt->refcount -= 1;
13405 }
13406 else
13407 /* A value of -1 means the symbol has become local, forced
13408 or seeing a hidden definition. Any other negative value
13409 is an error. */
13410 BFD_ASSERT (root_plt->refcount == -1);
34e77a92
RS		 13411
13412 if (!call_reloc_p)
13413 arm_plt->noncall_refcount--;
5e681ec4 13414
f6e32f6d 13415 if (r_type == R_ARM_THM_CALL)
34e77a92 13416 arm_plt->maybe_thumb_refcount--;
bd97cb95 13417
f6e32f6d
RS		 13418 if (r_type == R_ARM_THM_JUMP24
13419 || r_type == R_ARM_THM_JUMP19)
34e77a92 13420 arm_plt->thumb_refcount--;
f6e32f6d 13421 }
5e681ec4 13422
34e77a92 13423 if (may_become_dynamic_p)
f6e32f6d
RS		 13424 {
13425 struct elf_dyn_relocs **pp;
13426 struct elf_dyn_relocs *p;
5e681ec4 13427
34e77a92 13428 if (h != NULL)
9c489990 13429 pp = &(eh->dyn_relocs);
34e77a92
RS		 13430 else
13431 {
13432 Elf_Internal_Sym *isym;
13433
13434 isym = bfd_sym_from_r_symndx (&globals->sym_cache,
13435 abfd, r_symndx);
13436 if (isym == NULL)
13437 return FALSE;
13438 pp = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
13439 if (pp == NULL)
13440 return FALSE;
13441 }
9c489990 13442 for (; (p = *pp) != NULL; pp = &p->next)
f6e32f6d
RS		 13443 if (p->sec == sec)
13444 {
13445 /* Everything must go for SEC. */
13446 *pp = p->next;
13447 break;
13448 }
eb043451
PB		 13449 }
13450 }
5e681ec4 13451
b34976b6 13452 return TRUE;
252b5132
RH		 13453}
13454
780a67af
NC		 13455/* Look through the relocs for a section during the first phase. */
13456
b34976b6 13457static bfd_boolean
57e8b36a
NC		 13458elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
13459 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 13460{
b34976b6
AM		 13461 Elf_Internal_Shdr *symtab_hdr;
13462 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 13463 const Elf_Internal_Rela *rel;
13464 const Elf_Internal_Rela *rel_end;
13465 bfd *dynobj;
5e681ec4 13466 asection *sreloc;
5e681ec4 13467 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 13468 bfd_boolean call_reloc_p;
13469 bfd_boolean may_become_dynamic_p;
13470 bfd_boolean may_need_local_target_p;
ce98a316 13471 unsigned long nsyms;
9a5aca8c 13472
0e1862bb 13473 if (bfd_link_relocatable (info))
b34976b6 13474 return TRUE;
9a5aca8c 13475
0ffa91dd
NC		 13476 BFD_ASSERT (is_arm_elf (abfd));
13477
5e681ec4 13478 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13479 if (htab == NULL)
13480 return FALSE;
13481
5e681ec4 13482 sreloc = NULL;
9a5aca8c 13483
67687978
PB		 13484 /* Create dynamic sections for relocatable executables so that we can
13485 copy relocations. */
13486 if (htab->root.is_relocatable_executable
13487 && ! htab->root.dynamic_sections_created)
13488 {
13489 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
13490 return FALSE;
13491 }
13492
cbc704f3
RS		 13493 if (htab->root.dynobj == NULL)
13494 htab->root.dynobj = abfd;
34e77a92
RS		 13495 if (!create_ifunc_sections (info))
13496 return FALSE;
cbc704f3
RS		 13497
13498 dynobj = htab->root.dynobj;
13499
0ffa91dd 13500 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 13501 sym_hashes = elf_sym_hashes (abfd);
ce98a316 13502 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 13503
252b5132
RH		 13504 rel_end = relocs + sec->reloc_count;
13505 for (rel = relocs; rel < rel_end; rel++)
13506 {
34e77a92 13507 Elf_Internal_Sym *isym;
252b5132 13508 struct elf_link_hash_entry *h;
b7693d02 13509 struct elf32_arm_link_hash_entry *eh;
252b5132 13510 unsigned long r_symndx;
eb043451 13511 int r_type;
9a5aca8c 13512
252b5132 13513 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 13514 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 13515 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 13516
ce98a316
NC		 13517 if (r_symndx >= nsyms
13518 /* PR 9934: It is possible to have relocations that do not
13519 refer to symbols, thus it is also possible to have an
13520 object file containing relocations but no symbol table. */
cf35638d 13521 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac
DJ		 13522 {
13523 (*_bfd_error_handler) (_("%B: bad symbol index: %d"), abfd,
ce98a316 13524 r_symndx);
ba93b8ac
DJ		 13525 return FALSE;
13526 }
13527
34e77a92
RS		 13528 h = NULL;
13529 isym = NULL;
13530 if (nsyms > 0)
973a3492 13531 {
34e77a92
RS		 13532 if (r_symndx < symtab_hdr->sh_info)
13533 {
13534 /* A local symbol. */
13535 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
13536 abfd, r_symndx);
13537 if (isym == NULL)
13538 return FALSE;
13539 }
13540 else
13541 {
13542 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
13543 while (h->root.type == bfd_link_hash_indirect
13544 || h->root.type == bfd_link_hash_warning)
13545 h = (struct elf_link_hash_entry *) h->root.u.i.link;
81fbe831
AM		 13546
13547 /* PR15323, ref flags aren't set for references in the
13548 same object. */
13549 h->root.non_ir_ref = 1;
34e77a92 13550 }
973a3492 13551 }
9a5aca8c 13552
b7693d02
DJ		 13553 eh = (struct elf32_arm_link_hash_entry *) h;
13554
f6e32f6d
RS		 13555 call_reloc_p = FALSE;
13556 may_become_dynamic_p = FALSE;
13557 may_need_local_target_p = FALSE;
13558
0855e32b
NS		 13559 /* Could be done earlier, if h were already available. */
13560 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 13561 switch (r_type)
99059e56 13562 {
5e681ec4 13563 case R_ARM_GOT32:
eb043451 13564 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 13565 case R_ARM_TLS_GD32:
13566 case R_ARM_TLS_IE32:
0855e32b
NS		 13567 case R_ARM_TLS_GOTDESC:
13568 case R_ARM_TLS_DESCSEQ:
13569 case R_ARM_THM_TLS_DESCSEQ:
13570 case R_ARM_TLS_CALL:
13571 case R_ARM_THM_TLS_CALL:
5e681ec4 13572 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 13573 {
13574 int tls_type, old_tls_type;
5e681ec4 13575
ba93b8ac
DJ		 13576 switch (r_type)
13577 {
13578 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 13579
ba93b8ac 13580 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 13581
0855e32b
NS		 13582 case R_ARM_TLS_GOTDESC:
13583 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
13584 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
13585 tls_type = GOT_TLS_GDESC; break;
b38cadfb 13586
ba93b8ac
DJ		 13587 default: tls_type = GOT_NORMAL; break;
13588 }
252b5132 13589
0e1862bb 13590 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 13591 info->flags |= DF_STATIC_TLS;
13592
ba93b8ac
DJ		 13593 if (h != NULL)
13594 {
13595 h->got.refcount++;
13596 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
13597 }
13598 else
13599 {
ba93b8ac 13600 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 13601 if (!elf32_arm_allocate_local_sym_info (abfd))
13602 return FALSE;
13603 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 13604 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
13605 }
13606
0855e32b 13607 /* If a variable is accessed with both tls methods, two
99059e56 13608 slots may be created. */
0855e32b
NS		 13609 if (GOT_TLS_GD_ANY_P (old_tls_type)
13610 && GOT_TLS_GD_ANY_P (tls_type))
13611 tls_type |= old_tls_type;
13612
13613 /* We will already have issued an error message if there
13614 is a TLS/non-TLS mismatch, based on the symbol
13615 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 13616 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
13617 && tls_type != GOT_NORMAL)
13618 tls_type |= old_tls_type;
13619
0855e32b 13620 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 13621 method, we're able to relax. Turn off the GDESC flag,
13622 without messing up with any other kind of tls types
6a631e86 13623 that may be involved. */
0855e32b
NS		 13624 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
13625 tls_type &= ~GOT_TLS_GDESC;
13626
ba93b8ac
DJ		 13627 if (old_tls_type != tls_type)
13628 {
13629 if (h != NULL)
13630 elf32_arm_hash_entry (h)->tls_type = tls_type;
13631 else
13632 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
13633 }
13634 }
8029a119 13635 /* Fall through. */
ba93b8ac
DJ		 13636
13637 case R_ARM_TLS_LDM32:
13638 if (r_type == R_ARM_TLS_LDM32)
13639 htab->tls_ldm_got.refcount++;
8029a119 13640 /* Fall through. */
252b5132 13641
c19d1205 13642 case R_ARM_GOTOFF32:
5e681ec4 13643 case R_ARM_GOTPC:
cbc704f3
RS		 13644 if (htab->root.sgot == NULL
13645 && !create_got_section (htab->root.dynobj, info))
13646 return FALSE;
252b5132
RH		 13647 break;
13648
252b5132 13649 case R_ARM_PC24:
7359ea65 13650 case R_ARM_PLT32:
5b5bb741
PB		 13651 case R_ARM_CALL:
13652 case R_ARM_JUMP24:
eb043451 13653 case R_ARM_PREL31:
c19d1205 13654 case R_ARM_THM_CALL:
bd97cb95
DJ		 13655 case R_ARM_THM_JUMP24:
13656 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 13657 call_reloc_p = TRUE;
13658 may_need_local_target_p = TRUE;
13659 break;
13660
13661 case R_ARM_ABS12:
13662 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
13663 ldr __GOTT_INDEX__ offsets. */
13664 if (!htab->vxworks_p)
13665 {
13666 may_need_local_target_p = TRUE;
13667 break;
13668 }
aebf9be7
NC		 13669 else goto jump_over;
13670
f6e32f6d 13671 /* Fall through. */
39623e12 13672
96c23d59
JM		 13673 case R_ARM_MOVW_ABS_NC:
13674 case R_ARM_MOVT_ABS:
13675 case R_ARM_THM_MOVW_ABS_NC:
13676 case R_ARM_THM_MOVT_ABS:
0e1862bb 13677 if (bfd_link_pic (info))
96c23d59
JM		 13678 {
13679 (*_bfd_error_handler)
13680 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
13681 abfd, elf32_arm_howto_table_1[r_type].name,
13682 (h) ? h->root.root.string : "a local symbol");
13683 bfd_set_error (bfd_error_bad_value);
13684 return FALSE;
13685 }
13686
13687 /* Fall through. */
39623e12
PB		 13688 case R_ARM_ABS32:
13689 case R_ARM_ABS32_NOI:
aebf9be7 13690 jump_over:
0e1862bb 13691 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 13692 {
13693 h->pointer_equality_needed = 1;
13694 }
13695 /* Fall through. */
39623e12
PB		 13696 case R_ARM_REL32:
13697 case R_ARM_REL32_NOI:
b6895b4f
PB		 13698 case R_ARM_MOVW_PREL_NC:
13699 case R_ARM_MOVT_PREL:
b6895b4f
PB		 13700 case R_ARM_THM_MOVW_PREL_NC:
13701 case R_ARM_THM_MOVT_PREL:
39623e12 13702
b7693d02 13703 /* Should the interworking branches be listed here? */
0e1862bb 13704 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 13705 && (sec->flags & SEC_ALLOC) != 0)
13706 {
13707 if (h == NULL
469a3493 13708 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 13709 {
13710 /* In shared libraries and relocatable executables,
13711 we treat local relative references as calls;
13712 see the related SYMBOL_CALLS_LOCAL code in
13713 allocate_dynrelocs. */
13714 call_reloc_p = TRUE;
13715 may_need_local_target_p = TRUE;
13716 }
13717 else
13718 /* We are creating a shared library or relocatable
13719 executable, and this is a reloc against a global symbol,
13720 or a non-PC-relative reloc against a local symbol.
13721 We may need to copy the reloc into the output. */
13722 may_become_dynamic_p = TRUE;
13723 }
f6e32f6d
RS		 13724 else
13725 may_need_local_target_p = TRUE;
252b5132
RH		 13726 break;
13727
99059e56
RM		 13728 /* This relocation describes the C++ object vtable hierarchy.
13729 Reconstruct it for later use during GC. */
13730 case R_ARM_GNU_VTINHERIT:
13731 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
13732 return FALSE;
13733 break;
13734
13735 /* This relocation describes which C++ vtable entries are actually
13736 used. Record for later use during GC. */
13737 case R_ARM_GNU_VTENTRY:
13738 BFD_ASSERT (h != NULL);
13739 if (h != NULL
13740 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
13741 return FALSE;
13742 break;
13743 }
f6e32f6d
RS		 13744
13745 if (h != NULL)
13746 {
13747 if (call_reloc_p)
13748 /* We may need a .plt entry if the function this reloc
13749 refers to is in a different object, regardless of the
13750 symbol's type. We can't tell for sure yet, because
13751 something later might force the symbol local. */
13752 h->needs_plt = 1;
13753 else if (may_need_local_target_p)
13754 /* If this reloc is in a read-only section, we might
13755 need a copy reloc. We can't check reliably at this
13756 stage whether the section is read-only, as input
13757 sections have not yet been mapped to output sections.
13758 Tentatively set the flag for now, and correct in
13759 adjust_dynamic_symbol. */
13760 h->non_got_ref = 1;
13761 }
13762
34e77a92
RS		 13763 if (may_need_local_target_p
13764 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 13765 {
34e77a92
RS		 13766 union gotplt_union *root_plt;
13767 struct arm_plt_info *arm_plt;
13768 struct arm_local_iplt_info *local_iplt;
13769
13770 if (h != NULL)
13771 {
13772 root_plt = &h->plt;
13773 arm_plt = &eh->plt;
13774 }
13775 else
13776 {
13777 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
13778 if (local_iplt == NULL)
13779 return FALSE;
13780 root_plt = &local_iplt->root;
13781 arm_plt = &local_iplt->arm;
13782 }
13783
f6e32f6d
RS		 13784 /* If the symbol is a function that doesn't bind locally,
13785 this relocation will need a PLT entry. */
a8c887dd
NC		 13786 if (root_plt->refcount != -1)
13787 root_plt->refcount += 1;
34e77a92
RS		 13788
13789 if (!call_reloc_p)
13790 arm_plt->noncall_refcount++;
f6e32f6d
RS		 13791
13792 /* It's too early to use htab->use_blx here, so we have to
13793 record possible blx references separately from
13794 relocs that definitely need a thumb stub. */
13795
13796 if (r_type == R_ARM_THM_CALL)
34e77a92 13797 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 13798
13799 if (r_type == R_ARM_THM_JUMP24
13800 || r_type == R_ARM_THM_JUMP19)
34e77a92 13801 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 13802 }
13803
13804 if (may_become_dynamic_p)
13805 {
13806 struct elf_dyn_relocs *p, **head;
13807
13808 /* Create a reloc section in dynobj. */
13809 if (sreloc == NULL)
13810 {
13811 sreloc = _bfd_elf_make_dynamic_reloc_section
13812 (sec, dynobj, 2, abfd, ! htab->use_rel);
13813
13814 if (sreloc == NULL)
13815 return FALSE;
13816
13817 /* BPABI objects never have dynamic relocations mapped. */
13818 if (htab->symbian_p)
13819 {
13820 flagword flags;
13821
13822 flags = bfd_get_section_flags (dynobj, sreloc);
13823 flags &= ~(SEC_LOAD | SEC_ALLOC);
13824 bfd_set_section_flags (dynobj, sreloc, flags);
13825 }
13826 }
13827
13828 /* If this is a global symbol, count the number of
13829 relocations we need for this symbol. */
13830 if (h != NULL)
13831 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
13832 else
13833 {
34e77a92
RS		 13834 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
13835 if (head == NULL)
f6e32f6d 13836 return FALSE;
f6e32f6d
RS		 13837 }
13838
13839 p = *head;
13840 if (p == NULL || p->sec != sec)
13841 {
13842 bfd_size_type amt = sizeof *p;
13843
13844 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
13845 if (p == NULL)
13846 return FALSE;
13847 p->next = *head;
13848 *head = p;
13849 p->sec = sec;
13850 p->count = 0;
13851 p->pc_count = 0;
13852 }
13853
469a3493 13854 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 13855 p->pc_count += 1;
13856 p->count += 1;
13857 }
252b5132 13858 }
f21f3fe0 13859
b34976b6 13860 return TRUE;
252b5132
RH		 13861}
13862
6a5bb875
PB		 13863/* Unwinding tables are not referenced directly. This pass marks them as
13864 required if the corresponding code section is marked. */
13865
13866static bfd_boolean
906e58ca
NC		 13867elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
13868 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 13869{
13870 bfd *sub;
13871 Elf_Internal_Shdr **elf_shdrp;
13872 bfd_boolean again;
13873
7f6ab9f8
AM		 13874 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
13875
6a5bb875
PB		 13876 /* Marking EH data may cause additional code sections to be marked,
13877 requiring multiple passes. */
13878 again = TRUE;
13879 while (again)
13880 {
13881 again = FALSE;
c72f2fb2 13882 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 13883 {
13884 asection *o;
13885
0ffa91dd 13886 if (! is_arm_elf (sub))
6a5bb875
PB		 13887 continue;
13888
13889 elf_shdrp = elf_elfsections (sub);
13890 for (o = sub->sections; o != NULL; o = o->next)
13891 {
13892 Elf_Internal_Shdr *hdr;
0ffa91dd 13893
6a5bb875 13894 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 13895 if (hdr->sh_type == SHT_ARM_EXIDX
13896 && hdr->sh_link
13897 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 13898 && !o->gc_mark
13899 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
13900 {
13901 again = TRUE;
13902 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
13903 return FALSE;
13904 }
13905 }
13906 }
13907 }
13908
13909 return TRUE;
13910}
13911
3c9458e9
NC		 13912/* Treat mapping symbols as special target symbols. */
13913
13914static bfd_boolean
13915elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
13916{
b0796911
PB		 13917 return bfd_is_arm_special_symbol_name (sym->name,
13918 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 13919}
13920
0367ecfb
NC		 13921/* This is a copy of elf_find_function() from elf.c except that
13922 ARM mapping symbols are ignored when looking for function names
13923 and STT_ARM_TFUNC is considered to a function type. */
252b5132 13924
0367ecfb
NC		 13925static bfd_boolean
13926arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 13927 asymbol ** symbols,
fb167eb2 13928 asection * section,
0367ecfb
NC		 13929 bfd_vma offset,
13930 const char ** filename_ptr,
13931 const char ** functionname_ptr)
13932{
13933 const char * filename = NULL;
13934 asymbol * func = NULL;
13935 bfd_vma low_func = 0;
13936 asymbol ** p;
252b5132
RH		 13937
13938 for (p = symbols; *p != NULL; p++)
13939 {
13940 elf_symbol_type *q;
13941
13942 q = (elf_symbol_type *) *p;
13943
252b5132
RH		 13944 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
13945 {
13946 default:
13947 break;
13948 case STT_FILE:
13949 filename = bfd_asymbol_name (&q->symbol);
13950 break;
252b5132
RH		 13951 case STT_FUNC:
13952 case STT_ARM_TFUNC:
9d2da7ca 13953 case STT_NOTYPE:
b0796911 13954 /* Skip mapping symbols. */
0367ecfb 13955 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 13956 && bfd_is_arm_special_symbol_name (q->symbol.name,
13957 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 13958 continue;
13959 /* Fall through. */
6b40fcba 13960 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 13961 && q->symbol.value >= low_func
13962 && q->symbol.value <= offset)
13963 {
13964 func = (asymbol *) q;
13965 low_func = q->symbol.value;
13966 }
13967 break;
13968 }
13969 }
13970
13971 if (func == NULL)
b34976b6 13972 return FALSE;
252b5132 13973
0367ecfb
NC		 13974 if (filename_ptr)
13975 *filename_ptr = filename;
13976 if (functionname_ptr)
13977 *functionname_ptr = bfd_asymbol_name (func);
13978
13979 return TRUE;
906e58ca 13980}
0367ecfb
NC		 13981
13982
13983/* Find the nearest line to a particular section and offset, for error
13984 reporting. This code is a duplicate of the code in elf.c, except
13985 that it uses arm_elf_find_function. */
13986
13987static bfd_boolean
13988elf32_arm_find_nearest_line (bfd * abfd,
0367ecfb 13989 asymbol ** symbols,
fb167eb2 13990 asection * section,
0367ecfb
NC		 13991 bfd_vma offset,
13992 const char ** filename_ptr,
13993 const char ** functionname_ptr,
fb167eb2
AM		 13994 unsigned int * line_ptr,
13995 unsigned int * discriminator_ptr)
0367ecfb
NC		 13996{
13997 bfd_boolean found = FALSE;
13998
fb167eb2 13999 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 14000 filename_ptr, functionname_ptr,
fb167eb2
AM		 14001 line_ptr, discriminator_ptr,
14002 dwarf_debug_sections, 0,
0367ecfb
NC		 14003 & elf_tdata (abfd)->dwarf2_find_line_info))
14004 {
14005 if (!*functionname_ptr)
fb167eb2 14006 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 14007 *filename_ptr ? NULL : filename_ptr,
14008 functionname_ptr);
f21f3fe0 14009
0367ecfb
NC		 14010 return TRUE;
14011 }
14012
fb167eb2
AM		 14013 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
14014 uses DWARF1. */
14015
0367ecfb
NC		 14016 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
14017 & found, filename_ptr,
14018 functionname_ptr, line_ptr,
14019 & elf_tdata (abfd)->line_info))
14020 return FALSE;
14021
14022 if (found && (*functionname_ptr || *line_ptr))
14023 return TRUE;
14024
14025 if (symbols == NULL)
14026 return FALSE;
14027
fb167eb2 14028 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 14029 filename_ptr, functionname_ptr))
14030 return FALSE;
14031
14032 *line_ptr = 0;
b34976b6 14033 return TRUE;
252b5132
RH		 14034}
14035
4ab527b0
FF		 14036static bfd_boolean
14037elf32_arm_find_inliner_info (bfd * abfd,
14038 const char ** filename_ptr,
14039 const char ** functionname_ptr,
14040 unsigned int * line_ptr)
14041{
14042 bfd_boolean found;
14043 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
14044 functionname_ptr, line_ptr,
14045 & elf_tdata (abfd)->dwarf2_find_line_info);
14046 return found;
14047}
14048
252b5132
RH		 14049/* Adjust a symbol defined by a dynamic object and referenced by a
14050 regular object. The current definition is in some section of the
14051 dynamic object, but we're not including those sections. We have to
14052 change the definition to something the rest of the link can
14053 understand. */
14054
b34976b6 14055static bfd_boolean
57e8b36a
NC		 14056elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
14057 struct elf_link_hash_entry * h)
252b5132
RH		 14058{
14059 bfd * dynobj;
14060 asection * s;
b7693d02 14061 struct elf32_arm_link_hash_entry * eh;
67687978 14062 struct elf32_arm_link_hash_table *globals;
252b5132 14063
67687978 14064 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14065 if (globals == NULL)
14066 return FALSE;
14067
252b5132
RH		 14068 dynobj = elf_hash_table (info)->dynobj;
14069
14070 /* Make sure we know what is going on here. */
14071 BFD_ASSERT (dynobj != NULL
f5385ebf 14072 && (h->needs_plt
34e77a92 14073 || h->type == STT_GNU_IFUNC
f6e332e6 14074 || h->u.weakdef != NULL
f5385ebf
AM		 14075 || (h->def_dynamic
14076 && h->ref_regular
14077 && !h->def_regular)));
252b5132 14078
b7693d02
DJ		 14079 eh = (struct elf32_arm_link_hash_entry *) h;
14080
252b5132
RH		 14081 /* If this is a function, put it in the procedure linkage table. We
14082 will fill in the contents of the procedure linkage table later,
14083 when we know the address of the .got section. */
34e77a92 14084 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 14085 {
34e77a92
RS		 14086 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
14087 symbol binds locally. */
5e681ec4 14088 if (h->plt.refcount <= 0
34e77a92
RS		 14089 || (h->type != STT_GNU_IFUNC
14090 && (SYMBOL_CALLS_LOCAL (info, h)
14091 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
14092 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 14093 {
14094 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 14095 file, but the symbol was never referred to by a dynamic
14096 object, or if all references were garbage collected. In
14097 such a case, we don't actually need to build a procedure
14098 linkage table, and we can just do a PC24 reloc instead. */
14099 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 14100 eh->plt.thumb_refcount = 0;
14101 eh->plt.maybe_thumb_refcount = 0;
14102 eh->plt.noncall_refcount = 0;
f5385ebf 14103 h->needs_plt = 0;
252b5132
RH		 14104 }
14105
b34976b6 14106 return TRUE;
252b5132 14107 }
5e681ec4 14108 else
b7693d02
DJ		 14109 {
14110 /* It's possible that we incorrectly decided a .plt reloc was
14111 needed for an R_ARM_PC24 or similar reloc to a non-function sym
14112 in check_relocs. We can't decide accurately between function
14113 and non-function syms in check-relocs; Objects loaded later in
14114 the link may change h->type. So fix it now. */
14115 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 14116 eh->plt.thumb_refcount = 0;
14117 eh->plt.maybe_thumb_refcount = 0;
14118 eh->plt.noncall_refcount = 0;
b7693d02 14119 }
252b5132
RH		 14120
14121 /* If this is a weak symbol, and there is a real definition, the
14122 processor independent code will have arranged for us to see the
14123 real definition first, and we can just use the same value. */
f6e332e6 14124 if (h->u.weakdef != NULL)
252b5132 14125 {
f6e332e6
AM		 14126 BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined
14127 || h->u.weakdef->root.type == bfd_link_hash_defweak);
14128 h->root.u.def.section = h->u.weakdef->root.u.def.section;
14129 h->root.u.def.value = h->u.weakdef->root.u.def.value;
b34976b6 14130 return TRUE;
252b5132
RH		 14131 }
14132
ba93b8ac
DJ		 14133 /* If there are no non-GOT references, we do not need a copy
14134 relocation. */
14135 if (!h->non_got_ref)
14136 return TRUE;
14137
252b5132
RH		 14138 /* This is a reference to a symbol defined by a dynamic object which
14139 is not a function. */
14140
14141 /* If we are creating a shared library, we must presume that the
14142 only references to the symbol are via the global offset table.
14143 For such cases we need not do anything here; the relocations will
67687978
PB		 14144 be handled correctly by relocate_section. Relocatable executables
14145 can reference data in shared objects directly, so we don't need to
14146 do anything here. */
0e1862bb 14147 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 14148 return TRUE;
252b5132
RH		 14149
14150 /* We must allocate the symbol in our .dynbss section, which will
14151 become part of the .bss section of the executable. There will be
14152 an entry for this symbol in the .dynsym section. The dynamic
14153 object will contain position independent code, so all references
14154 from the dynamic object to this symbol will go through the global
14155 offset table. The dynamic linker will use the .dynsym entry to
14156 determine the address it must put in the global offset table, so
14157 both the dynamic object and the regular object will refer to the
14158 same memory location for the variable. */
3d4d4302 14159 s = bfd_get_linker_section (dynobj, ".dynbss");
252b5132
RH		 14160 BFD_ASSERT (s != NULL);
14161
5522f910
NC		 14162 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
14163 linker to copy the initial value out of the dynamic object and into
14164 the runtime process image. We need to remember the offset into the
00a97672 14165 .rel(a).bss section we are going to use. */
5522f910
NC		 14166 if (info->nocopyreloc == 0
14167 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 14168 && h->size != 0)
252b5132
RH		 14169 {
14170 asection *srel;
14171
3d4d4302 14172 srel = bfd_get_linker_section (dynobj, RELOC_SECTION (globals, ".bss"));
47beaa6a 14173 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 14174 h->needs_copy = 1;
252b5132
RH		 14175 }
14176
6cabe1ea 14177 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 14178}
14179
5e681ec4
PB		 14180/* Allocate space in .plt, .got and associated reloc sections for
14181 dynamic relocs. */
14182
14183static bfd_boolean
47beaa6a 14184allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 14185{
14186 struct bfd_link_info *info;
14187 struct elf32_arm_link_hash_table *htab;
14188 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 14189 struct elf_dyn_relocs *p;
5e681ec4
PB		 14190
14191 if (h->root.type == bfd_link_hash_indirect)
14192 return TRUE;
14193
e6a6bb22
AM		 14194 eh = (struct elf32_arm_link_hash_entry *) h;
14195
5e681ec4
PB		 14196 info = (struct bfd_link_info *) inf;
14197 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14198 if (htab == NULL)
14199 return FALSE;
5e681ec4 14200
34e77a92 14201 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 14202 && h->plt.refcount > 0)
14203 {
14204 /* Make sure this symbol is output as a dynamic symbol.
14205 Undefined weak syms won't yet be marked as dynamic. */
14206 if (h->dynindx == -1
f5385ebf 14207 && !h->forced_local)
5e681ec4 14208 {
c152c796 14209 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14210 return FALSE;
14211 }
14212
34e77a92
RS		 14213 /* If the call in the PLT entry binds locally, the associated
14214 GOT entry should use an R_ARM_IRELATIVE relocation instead of
14215 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
14216 than the .plt section. */
14217 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
14218 {
14219 eh->is_iplt = 1;
14220 if (eh->plt.noncall_refcount == 0
14221 && SYMBOL_REFERENCES_LOCAL (info, h))
14222 /* All non-call references can be resolved directly.
14223 This means that they can (and in some cases, must)
14224 resolve directly to the run-time target, rather than
14225 to the PLT. That in turns means that any .got entry
14226 would be equal to the .igot.plt entry, so there's
14227 no point having both. */
14228 h->got.refcount = 0;
14229 }
14230
0e1862bb 14231 if (bfd_link_pic (info)
34e77a92 14232 || eh->is_iplt
7359ea65 14233 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 14234 {
34e77a92 14235 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 14236
5e681ec4
PB		 14237 /* If this symbol is not defined in a regular file, and we are
14238 not generating a shared library, then set the symbol to this
14239 location in the .plt. This is required to make function
14240 pointers compare as equal between the normal executable and
14241 the shared library. */
0e1862bb 14242 if (! bfd_link_pic (info)
f5385ebf 14243 && !h->def_regular)
5e681ec4 14244 {
34e77a92 14245 h->root.u.def.section = htab->root.splt;
5e681ec4 14246 h->root.u.def.value = h->plt.offset;
5e681ec4 14247
67d74e43
DJ		 14248 /* Make sure the function is not marked as Thumb, in case
14249 it is the target of an ABS32 relocation, which will
14250 point to the PLT entry. */
35fc36a8 14251 h->target_internal = ST_BRANCH_TO_ARM;
67d74e43 14252 }
022f8312 14253
00a97672
RS		 14254 /* VxWorks executables have a second set of relocations for
14255 each PLT entry. They go in a separate relocation section,
14256 which is processed by the kernel loader. */
0e1862bb 14257 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 14258 {
14259 /* There is a relocation for the initial PLT entry:
14260 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
14261 if (h->plt.offset == htab->plt_header_size)
47beaa6a 14262 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 14263
14264 /* There are two extra relocations for each subsequent
14265 PLT entry: an R_ARM_32 relocation for the GOT entry,
14266 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 14267 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 14268 }
5e681ec4
PB		 14269 }
14270 else
14271 {
14272 h->plt.offset = (bfd_vma) -1;
f5385ebf 14273 h->needs_plt = 0;
5e681ec4
PB		 14274 }
14275 }
14276 else
14277 {
14278 h->plt.offset = (bfd_vma) -1;
f5385ebf 14279 h->needs_plt = 0;
5e681ec4
PB		 14280 }
14281
0855e32b
NS		 14282 eh = (struct elf32_arm_link_hash_entry *) h;
14283 eh->tlsdesc_got = (bfd_vma) -1;
14284
5e681ec4
PB		 14285 if (h->got.refcount > 0)
14286 {
14287 asection *s;
14288 bfd_boolean dyn;
ba93b8ac
DJ		 14289 int tls_type = elf32_arm_hash_entry (h)->tls_type;
14290 int indx;
5e681ec4
PB		 14291
14292 /* Make sure this symbol is output as a dynamic symbol.
14293 Undefined weak syms won't yet be marked as dynamic. */
14294 if (h->dynindx == -1
f5385ebf 14295 && !h->forced_local)
5e681ec4 14296 {
c152c796 14297 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14298 return FALSE;
14299 }
14300
e5a52504
MM		 14301 if (!htab->symbian_p)
14302 {
362d30a1 14303 s = htab->root.sgot;
e5a52504 14304 h->got.offset = s->size;
ba93b8ac
DJ		 14305
14306 if (tls_type == GOT_UNKNOWN)
14307 abort ();
14308
14309 if (tls_type == GOT_NORMAL)
14310 /* Non-TLS symbols need one GOT slot. */
14311 s->size += 4;
14312 else
14313 {
99059e56
RM		 14314 if (tls_type & GOT_TLS_GDESC)
14315 {
0855e32b 14316 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 14317 eh->tlsdesc_got
0855e32b
NS		 14318 = (htab->root.sgotplt->size
14319 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 14320 htab->root.sgotplt->size += 8;
14321 h->got.offset = (bfd_vma) -2;
34e77a92 14322 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 14323 reloc in the middle of .got.plt. */
99059e56
RM		 14324 htab->num_tls_desc++;
14325 }
0855e32b 14326
ba93b8ac 14327 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 14328 {
14329 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
14330 the symbol is both GD and GDESC, got.offset may
14331 have been overwritten. */
14332 h->got.offset = s->size;
14333 s->size += 8;
14334 }
14335
ba93b8ac
DJ		 14336 if (tls_type & GOT_TLS_IE)
14337 /* R_ARM_TLS_IE32 needs one GOT slot. */
14338 s->size += 4;
14339 }
14340
e5a52504 14341 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 14342
14343 indx = 0;
0e1862bb
L		 14344 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
14345 bfd_link_pic (info),
14346 h)
14347 && (!bfd_link_pic (info)
ba93b8ac
DJ		 14348 || !SYMBOL_REFERENCES_LOCAL (info, h)))
14349 indx = h->dynindx;
14350
14351 if (tls_type != GOT_NORMAL
0e1862bb 14352 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 14353 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
14354 || h->root.type != bfd_link_hash_undefweak))
14355 {
14356 if (tls_type & GOT_TLS_IE)
47beaa6a 14357 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 14358
14359 if (tls_type & GOT_TLS_GD)
47beaa6a 14360 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 14361
b38cadfb 14362 if (tls_type & GOT_TLS_GDESC)
0855e32b 14363 {
47beaa6a 14364 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 14365 /* GDESC needs a trampoline to jump to. */
14366 htab->tls_trampoline = -1;
14367 }
14368
14369 /* Only GD needs it. GDESC just emits one relocation per
14370 2 entries. */
b38cadfb 14371 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 14372 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 14373 }
6f820c85 14374 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 14375 {
14376 if (htab->root.dynamic_sections_created)
14377 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
14378 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
14379 }
34e77a92
RS		 14380 else if (h->type == STT_GNU_IFUNC
14381 && eh->plt.noncall_refcount == 0)
14382 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
14383 they all resolve dynamically instead. Reserve room for the
14384 GOT entry's R_ARM_IRELATIVE relocation. */
14385 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 14386 else if (bfd_link_pic (info)
14387 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
14388 || h->root.type != bfd_link_hash_undefweak))
b436d854 14389 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 14390 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 14391 }
5e681ec4
PB		 14392 }
14393 else
14394 h->got.offset = (bfd_vma) -1;
14395
a4fd1a8e
PB		 14396 /* Allocate stubs for exported Thumb functions on v4t. */
14397 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 14398 && h->def_regular
35fc36a8 14399 && h->target_internal == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 14400 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
14401 {
14402 struct elf_link_hash_entry * th;
14403 struct bfd_link_hash_entry * bh;
14404 struct elf_link_hash_entry * myh;
14405 char name[1024];
14406 asection *s;
14407 bh = NULL;
14408 /* Create a new symbol to regist the real location of the function. */
14409 s = h->root.u.def.section;
906e58ca 14410 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 14411 _bfd_generic_link_add_one_symbol (info, s->owner,
14412 name, BSF_GLOBAL, s,
14413 h->root.u.def.value,
14414 NULL, TRUE, FALSE, &bh);
14415
14416 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 14417 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 14418 myh->forced_local = 1;
35fc36a8 14419 myh->target_internal = ST_BRANCH_TO_THUMB;
a4fd1a8e
PB		 14420 eh->export_glue = myh;
14421 th = record_arm_to_thumb_glue (info, h);
14422 /* Point the symbol at the stub. */
14423 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
35fc36a8 14424 h->target_internal = ST_BRANCH_TO_ARM;
a4fd1a8e
PB		 14425 h->root.u.def.section = th->root.u.def.section;
14426 h->root.u.def.value = th->root.u.def.value & ~1;
14427 }
14428
0bdcacaf 14429 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 14430 return TRUE;
14431
14432 /* In the shared -Bsymbolic case, discard space allocated for
14433 dynamic pc-relative relocs against symbols which turn out to be
14434 defined in regular objects. For the normal shared case, discard
14435 space for pc-relative relocs that have become local due to symbol
14436 visibility changes. */
14437
0e1862bb 14438 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 14439 {
469a3493
RM		 14440 /* Relocs that use pc_count are PC-relative forms, which will appear
14441 on something like ".long foo - ." or "movw REG, foo - .". We want
14442 calls to protected symbols to resolve directly to the function
14443 rather than going via the plt. If people want function pointer
14444 comparisons to work as expected then they should avoid writing
14445 assembly like ".long foo - .". */
ba93b8ac
DJ		 14446 if (SYMBOL_CALLS_LOCAL (info, h))
14447 {
0bdcacaf 14448 struct elf_dyn_relocs **pp;
ba93b8ac 14449
0bdcacaf 14450 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 14451 {
14452 p->count -= p->pc_count;
14453 p->pc_count = 0;
14454 if (p->count == 0)
14455 *pp = p->next;
14456 else
14457 pp = &p->next;
14458 }
14459 }
14460
4dfe6ac6 14461 if (htab->vxworks_p)
3348747a 14462 {
0bdcacaf 14463 struct elf_dyn_relocs **pp;
3348747a 14464
0bdcacaf 14465 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 14466 {
0bdcacaf 14467 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 14468 *pp = p->next;
14469 else
14470 pp = &p->next;
14471 }
14472 }
14473
ba93b8ac 14474 /* Also discard relocs on undefined weak syms with non-default
99059e56 14475 visibility. */
0bdcacaf 14476 if (eh->dyn_relocs != NULL
5e681ec4 14477 && h->root.type == bfd_link_hash_undefweak)
22d606e9
AM		 14478 {
14479 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT)
0bdcacaf 14480 eh->dyn_relocs = NULL;
22d606e9
AM		 14481
14482 /* Make sure undefined weak symbols are output as a dynamic
14483 symbol in PIEs. */
14484 else if (h->dynindx == -1
14485 && !h->forced_local)
14486 {
14487 if (! bfd_elf_link_record_dynamic_symbol (info, h))
14488 return FALSE;
14489 }
14490 }
14491
67687978
PB		 14492 else if (htab->root.is_relocatable_executable && h->dynindx == -1
14493 && h->root.type == bfd_link_hash_new)
14494 {
14495 /* Output absolute symbols so that we can create relocations
14496 against them. For normal symbols we output a relocation
14497 against the section that contains them. */
14498 if (! bfd_elf_link_record_dynamic_symbol (info, h))
14499 return FALSE;
14500 }
14501
5e681ec4
PB		 14502 }
14503 else
14504 {
14505 /* For the non-shared case, discard space for relocs against
14506 symbols which turn out to need copy relocs or are not
14507 dynamic. */
14508
f5385ebf
AM		 14509 if (!h->non_got_ref
14510 && ((h->def_dynamic
14511 && !h->def_regular)
5e681ec4
PB		 14512 || (htab->root.dynamic_sections_created
14513 && (h->root.type == bfd_link_hash_undefweak
14514 || h->root.type == bfd_link_hash_undefined))))
14515 {
14516 /* Make sure this symbol is output as a dynamic symbol.
14517 Undefined weak syms won't yet be marked as dynamic. */
14518 if (h->dynindx == -1
f5385ebf 14519 && !h->forced_local)
5e681ec4 14520 {
c152c796 14521 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14522 return FALSE;
14523 }
14524
14525 /* If that succeeded, we know we'll be keeping all the
14526 relocs. */
14527 if (h->dynindx != -1)
14528 goto keep;
14529 }
14530
0bdcacaf 14531 eh->dyn_relocs = NULL;
5e681ec4
PB		 14532
14533 keep: ;
14534 }
14535
14536 /* Finally, allocate space. */
0bdcacaf 14537 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 14538 {
0bdcacaf 14539 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 14540 if (h->type == STT_GNU_IFUNC
14541 && eh->plt.noncall_refcount == 0
14542 && SYMBOL_REFERENCES_LOCAL (info, h))
14543 elf32_arm_allocate_irelocs (info, sreloc, p->count);
14544 else
14545 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 14546 }
14547
14548 return TRUE;
14549}
14550
08d1f311
DJ		 14551/* Find any dynamic relocs that apply to read-only sections. */
14552
14553static bfd_boolean
8029a119 14554elf32_arm_readonly_dynrelocs (struct elf_link_hash_entry * h, void * inf)
08d1f311 14555{
8029a119 14556 struct elf32_arm_link_hash_entry * eh;
0bdcacaf 14557 struct elf_dyn_relocs * p;
08d1f311 14558
08d1f311 14559 eh = (struct elf32_arm_link_hash_entry *) h;
0bdcacaf 14560 for (p = eh->dyn_relocs; p != NULL; p = p->next)
08d1f311 14561 {
0bdcacaf 14562 asection *s = p->sec;
08d1f311
DJ		 14563
14564 if (s != NULL && (s->flags & SEC_READONLY) != 0)
14565 {
14566 struct bfd_link_info *info = (struct bfd_link_info *) inf;
14567
14568 info->flags |= DF_TEXTREL;
14569
14570 /* Not an error, just cut short the traversal. */
14571 return FALSE;
14572 }
14573 }
14574 return TRUE;
14575}
14576
d504ffc8
DJ		 14577void
14578bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
14579 int byteswap_code)
14580{
14581 struct elf32_arm_link_hash_table *globals;
14582
14583 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14584 if (globals == NULL)
14585 return;
14586
d504ffc8
DJ		 14587 globals->byteswap_code = byteswap_code;
14588}
14589
252b5132
RH		 14590/* Set the sizes of the dynamic sections. */
14591
b34976b6 14592static bfd_boolean
57e8b36a
NC		 14593elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
14594 struct bfd_link_info * info)
252b5132
RH		 14595{
14596 bfd * dynobj;
14597 asection * s;
b34976b6
AM		 14598 bfd_boolean plt;
14599 bfd_boolean relocs;
5e681ec4
PB		 14600 bfd *ibfd;
14601 struct elf32_arm_link_hash_table *htab;
252b5132 14602
5e681ec4 14603 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14604 if (htab == NULL)
14605 return FALSE;
14606
252b5132
RH		 14607 dynobj = elf_hash_table (info)->dynobj;
14608 BFD_ASSERT (dynobj != NULL);
39b41c9c 14609 check_use_blx (htab);
252b5132
RH		 14610
14611 if (elf_hash_table (info)->dynamic_sections_created)
14612 {
14613 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 14614 if (bfd_link_executable (info) && !info->nointerp)
252b5132 14615 {
3d4d4302 14616 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 14617 BFD_ASSERT (s != NULL);
eea6121a 14618 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 14619 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
14620 }
14621 }
5e681ec4
PB		 14622
14623 /* Set up .got offsets for local syms, and space for local dynamic
14624 relocs. */
c72f2fb2 14625 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 14626 {
5e681ec4
PB		 14627 bfd_signed_vma *local_got;
14628 bfd_signed_vma *end_local_got;
34e77a92 14629 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 14630 char *local_tls_type;
0855e32b 14631 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 14632 bfd_size_type locsymcount;
14633 Elf_Internal_Shdr *symtab_hdr;
14634 asection *srel;
4dfe6ac6 14635 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 14636 unsigned int symndx;
5e681ec4 14637
0ffa91dd 14638 if (! is_arm_elf (ibfd))
5e681ec4
PB		 14639 continue;
14640
14641 for (s = ibfd->sections; s != NULL; s = s->next)
14642 {
0bdcacaf 14643 struct elf_dyn_relocs *p;
5e681ec4 14644
0bdcacaf 14645 for (p = (struct elf_dyn_relocs *)
99059e56 14646 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 14647 {
0bdcacaf
RS		 14648 if (!bfd_is_abs_section (p->sec)
14649 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 14650 {
14651 /* Input section has been discarded, either because
14652 it is a copy of a linkonce section or due to
14653 linker script /DISCARD/, so we'll be discarding
14654 the relocs too. */
14655 }
3348747a 14656 else if (is_vxworks
0bdcacaf 14657 && strcmp (p->sec->output_section->name,
3348747a
NS		 14658 ".tls_vars") == 0)
14659 {
14660 /* Relocations in vxworks .tls_vars sections are
14661 handled specially by the loader. */
14662 }
5e681ec4
PB		 14663 else if (p->count != 0)
14664 {
0bdcacaf 14665 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 14666 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 14667 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 14668 info->flags |= DF_TEXTREL;
14669 }
14670 }
14671 }
14672
14673 local_got = elf_local_got_refcounts (ibfd);
14674 if (!local_got)
14675 continue;
14676
0ffa91dd 14677 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 14678 locsymcount = symtab_hdr->sh_info;
14679 end_local_got = local_got + locsymcount;
34e77a92 14680 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 14681 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 14682 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 14683 symndx = 0;
362d30a1
RS		 14684 s = htab->root.sgot;
14685 srel = htab->root.srelgot;
0855e32b 14686 for (; local_got < end_local_got;
34e77a92
RS		 14687 ++local_got, ++local_iplt_ptr, ++local_tls_type,
14688 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 14689 {
0855e32b 14690 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 14691 local_iplt = *local_iplt_ptr;
14692 if (local_iplt != NULL)
14693 {
14694 struct elf_dyn_relocs *p;
14695
14696 if (local_iplt->root.refcount > 0)
14697 {
14698 elf32_arm_allocate_plt_entry (info, TRUE,
14699 &local_iplt->root,
14700 &local_iplt->arm);
14701 if (local_iplt->arm.noncall_refcount == 0)
14702 /* All references to the PLT are calls, so all
14703 non-call references can resolve directly to the
14704 run-time target. This means that the .got entry
14705 would be the same as the .igot.plt entry, so there's
14706 no point creating both. */
14707 *local_got = 0;
14708 }
14709 else
14710 {
14711 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
14712 local_iplt->root.offset = (bfd_vma) -1;
14713 }
14714
14715 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
14716 {
14717 asection *psrel;
14718
14719 psrel = elf_section_data (p->sec)->sreloc;
14720 if (local_iplt->arm.noncall_refcount == 0)
14721 elf32_arm_allocate_irelocs (info, psrel, p->count);
14722 else
14723 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
14724 }
14725 }
5e681ec4
PB		 14726 if (*local_got > 0)
14727 {
34e77a92
RS		 14728 Elf_Internal_Sym *isym;
14729
eea6121a 14730 *local_got = s->size;
ba93b8ac
DJ		 14731 if (*local_tls_type & GOT_TLS_GD)
14732 /* TLS_GD relocs need an 8-byte structure in the GOT. */
14733 s->size += 8;
0855e32b
NS		 14734 if (*local_tls_type & GOT_TLS_GDESC)
14735 {
14736 *local_tlsdesc_gotent = htab->root.sgotplt->size
14737 - elf32_arm_compute_jump_table_size (htab);
14738 htab->root.sgotplt->size += 8;
14739 *local_got = (bfd_vma) -2;
34e77a92 14740 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 14741 reloc in the middle of .got.plt. */
99059e56 14742 htab->num_tls_desc++;
0855e32b 14743 }
ba93b8ac
DJ		 14744 if (*local_tls_type & GOT_TLS_IE)
14745 s->size += 4;
ba93b8ac 14746
0855e32b
NS		 14747 if (*local_tls_type & GOT_NORMAL)
14748 {
14749 /* If the symbol is both GD and GDESC, *local_got
14750 may have been overwritten. */
14751 *local_got = s->size;
14752 s->size += 4;
14753 }
14754
34e77a92
RS		 14755 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
14756 if (isym == NULL)
14757 return FALSE;
14758
14759 /* If all references to an STT_GNU_IFUNC PLT are calls,
14760 then all non-call references, including this GOT entry,
14761 resolve directly to the run-time target. */
14762 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
14763 && (local_iplt == NULL
14764 || local_iplt->arm.noncall_refcount == 0))
14765 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 14766 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 14767 {
0e1862bb 14768 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 14769 || *local_tls_type & GOT_TLS_GD)
14770 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 14771
0e1862bb 14772 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 14773 {
14774 elf32_arm_allocate_dynrelocs (info,
14775 htab->root.srelplt, 1);
14776 htab->tls_trampoline = -1;
14777 }
0855e32b 14778 }
5e681ec4
PB		 14779 }
14780 else
14781 *local_got = (bfd_vma) -1;
14782 }
252b5132
RH		 14783 }
14784
ba93b8ac
DJ		 14785 if (htab->tls_ldm_got.refcount > 0)
14786 {
14787 /* Allocate two GOT entries and one dynamic relocation (if necessary)
14788 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 14789 htab->tls_ldm_got.offset = htab->root.sgot->size;
14790 htab->root.sgot->size += 8;
0e1862bb 14791 if (bfd_link_pic (info))
47beaa6a 14792 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 14793 }
14794 else
14795 htab->tls_ldm_got.offset = -1;
14796
5e681ec4
PB		 14797 /* Allocate global sym .plt and .got entries, and space for global
14798 sym dynamic relocs. */
47beaa6a 14799 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 14800
d504ffc8 14801 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 14802 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 14803 {
0ffa91dd 14804 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 14805 continue;
14806
c7b8f16e
JB		 14807 /* Initialise mapping tables for code/data. */
14808 bfd_elf32_arm_init_maps (ibfd);
906e58ca 14809
c7b8f16e 14810 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 14811 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
14812 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
99059e56
RM		 14813 /* xgettext:c-format */
14814 _bfd_error_handler (_("Errors encountered processing file %s"),
c7b8f16e
JB		 14815 ibfd->filename);
14816 }
d504ffc8 14817
3e6b1042
DJ		 14818 /* Allocate space for the glue sections now that we've sized them. */
14819 bfd_elf32_arm_allocate_interworking_sections (info);
14820
0855e32b
NS		 14821 /* For every jump slot reserved in the sgotplt, reloc_count is
14822 incremented. However, when we reserve space for TLS descriptors,
14823 it's not incremented, so in order to compute the space reserved
14824 for them, it suffices to multiply the reloc count by the jump
14825 slot size. */
14826 if (htab->root.srelplt)
14827 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
14828
14829 if (htab->tls_trampoline)
14830 {
14831 if (htab->root.splt->size == 0)
14832 htab->root.splt->size += htab->plt_header_size;
b38cadfb 14833
0855e32b
NS		 14834 htab->tls_trampoline = htab->root.splt->size;
14835 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 14836
0855e32b 14837 /* If we're not using lazy TLS relocations, don't generate the
99059e56 14838 PLT and GOT entries they require. */
0855e32b
NS		 14839 if (!(info->flags & DF_BIND_NOW))
14840 {
14841 htab->dt_tlsdesc_got = htab->root.sgot->size;
14842 htab->root.sgot->size += 4;
14843
14844 htab->dt_tlsdesc_plt = htab->root.splt->size;
14845 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
14846 }
14847 }
14848
252b5132
RH		 14849 /* The check_relocs and adjust_dynamic_symbol entry points have
14850 determined the sizes of the various dynamic sections. Allocate
14851 memory for them. */
b34976b6
AM		 14852 plt = FALSE;
14853 relocs = FALSE;
252b5132
RH		 14854 for (s = dynobj->sections; s != NULL; s = s->next)
14855 {
14856 const char * name;
252b5132
RH		 14857
14858 if ((s->flags & SEC_LINKER_CREATED) == 0)
14859 continue;
14860
14861 /* It's OK to base decisions on the section name, because none
14862 of the dynobj section names depend upon the input files. */
14863 name = bfd_get_section_name (dynobj, s);
14864
34e77a92 14865 if (s == htab->root.splt)
252b5132 14866 {
c456f082
AM		 14867 /* Remember whether there is a PLT. */
14868 plt = s->size != 0;
252b5132 14869 }
0112cd26 14870 else if (CONST_STRNEQ (name, ".rel"))
252b5132 14871 {
c456f082 14872 if (s->size != 0)
252b5132 14873 {
252b5132 14874 /* Remember whether there are any reloc sections other
00a97672 14875 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 14876 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 14877 relocs = TRUE;
252b5132
RH		 14878
14879 /* We use the reloc_count field as a counter if we need
14880 to copy relocs into the output file. */
14881 s->reloc_count = 0;
14882 }
14883 }
34e77a92
RS		 14884 else if (s != htab->root.sgot
14885 && s != htab->root.sgotplt
14886 && s != htab->root.iplt
14887 && s != htab->root.igotplt
14888 && s != htab->sdynbss)
252b5132
RH		 14889 {
14890 /* It's not one of our sections, so don't allocate space. */
14891 continue;
14892 }
14893
c456f082 14894 if (s->size == 0)
252b5132 14895 {
c456f082 14896 /* If we don't need this section, strip it from the
00a97672
RS		 14897 output file. This is mostly to handle .rel(a).bss and
14898 .rel(a).plt. We must create both sections in
c456f082
AM		 14899 create_dynamic_sections, because they must be created
14900 before the linker maps input sections to output
14901 sections. The linker does that before
14902 adjust_dynamic_symbol is called, and it is that
14903 function which decides whether anything needs to go
14904 into these sections. */
8423293d 14905 s->flags |= SEC_EXCLUDE;
252b5132
RH		 14906 continue;
14907 }
14908
c456f082
AM		 14909 if ((s->flags & SEC_HAS_CONTENTS) == 0)
14910 continue;
14911
252b5132 14912 /* Allocate memory for the section contents. */
21d799b5 14913 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 14914 if (s->contents == NULL)
b34976b6 14915 return FALSE;
252b5132
RH		 14916 }
14917
14918 if (elf_hash_table (info)->dynamic_sections_created)
14919 {
14920 /* Add some entries to the .dynamic section. We fill in the
14921 values later, in elf32_arm_finish_dynamic_sections, but we
14922 must add the entries now so that we get the correct size for
14923 the .dynamic section. The DT_DEBUG entry is filled in by the
14924 dynamic linker and used by the debugger. */
dc810e39 14925#define add_dynamic_entry(TAG, VAL) \
5a580b3a 14926 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 14927
0e1862bb 14928 if (bfd_link_executable (info))
252b5132 14929 {
dc810e39 14930 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 14931 return FALSE;
252b5132
RH		 14932 }
14933
14934 if (plt)
14935 {
dc810e39
AM		 14936 if ( !add_dynamic_entry (DT_PLTGOT, 0)
14937 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 14938 || !add_dynamic_entry (DT_PLTREL,
14939 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 14940 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 14941 return FALSE;
0855e32b
NS		 14942
14943 if (htab->dt_tlsdesc_plt &&
b38cadfb 14944 (!add_dynamic_entry (DT_TLSDESC_PLT,0)
0855e32b 14945 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 14946 return FALSE;
252b5132
RH		 14947 }
14948
14949 if (relocs)
14950 {
00a97672
RS		 14951 if (htab->use_rel)
14952 {
14953 if (!add_dynamic_entry (DT_REL, 0)
14954 || !add_dynamic_entry (DT_RELSZ, 0)
14955 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
14956 return FALSE;
14957 }
14958 else
14959 {
14960 if (!add_dynamic_entry (DT_RELA, 0)
14961 || !add_dynamic_entry (DT_RELASZ, 0)
14962 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
14963 return FALSE;
14964 }
252b5132
RH		 14965 }
14966
08d1f311
DJ		 14967 /* If any dynamic relocs apply to a read-only section,
14968 then we need a DT_TEXTREL entry. */
14969 if ((info->flags & DF_TEXTREL) == 0)
8029a119
NC		 14970 elf_link_hash_traverse (& htab->root, elf32_arm_readonly_dynrelocs,
14971 info);
08d1f311 14972
99e4ae17 14973 if ((info->flags & DF_TEXTREL) != 0)
252b5132 14974 {
dc810e39 14975 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 14976 return FALSE;
252b5132 14977 }
7a2b07ff
NS		 14978 if (htab->vxworks_p
14979 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
14980 return FALSE;
252b5132 14981 }
8532796c 14982#undef add_dynamic_entry
252b5132 14983
b34976b6 14984 return TRUE;
252b5132
RH		 14985}
14986
0855e32b
NS		 14987/* Size sections even though they're not dynamic. We use it to setup
14988 _TLS_MODULE_BASE_, if needed. */
14989
14990static bfd_boolean
14991elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 14992 struct bfd_link_info *info)
0855e32b
NS		 14993{
14994 asection *tls_sec;
14995
0e1862bb 14996 if (bfd_link_relocatable (info))
0855e32b
NS		 14997 return TRUE;
14998
14999 tls_sec = elf_hash_table (info)->tls_sec;
15000
15001 if (tls_sec)
15002 {
15003 struct elf_link_hash_entry *tlsbase;
15004
15005 tlsbase = elf_link_hash_lookup
15006 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
15007
15008 if (tlsbase)
99059e56
RM		 15009 {
15010 struct bfd_link_hash_entry *bh = NULL;
0855e32b 15011 const struct elf_backend_data *bed
99059e56 15012 = get_elf_backend_data (output_bfd);
0855e32b 15013
99059e56 15014 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 15015 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
15016 tls_sec, 0, NULL, FALSE,
15017 bed->collect, &bh)))
15018 return FALSE;
b38cadfb 15019
99059e56
RM		 15020 tlsbase->type = STT_TLS;
15021 tlsbase = (struct elf_link_hash_entry *)bh;
15022 tlsbase->def_regular = 1;
15023 tlsbase->other = STV_HIDDEN;
15024 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 15025 }
15026 }
15027 return TRUE;
15028}
15029
252b5132
RH		 15030/* Finish up dynamic symbol handling. We set the contents of various
15031 dynamic sections here. */
15032
b34976b6 15033static bfd_boolean
906e58ca
NC		 15034elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
15035 struct bfd_link_info * info,
15036 struct elf_link_hash_entry * h,
15037 Elf_Internal_Sym * sym)
252b5132 15038{
e5a52504 15039 struct elf32_arm_link_hash_table *htab;
b7693d02 15040 struct elf32_arm_link_hash_entry *eh;
252b5132 15041
e5a52504 15042 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15043 if (htab == NULL)
15044 return FALSE;
15045
b7693d02 15046 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 15047
15048 if (h->plt.offset != (bfd_vma) -1)
15049 {
34e77a92 15050 if (!eh->is_iplt)
e5a52504 15051 {
34e77a92 15052 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 15053 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
15054 h->dynindx, 0))
15055 return FALSE;
e5a52504 15056 }
57e8b36a 15057
f5385ebf 15058 if (!h->def_regular)
252b5132
RH		 15059 {
15060 /* Mark the symbol as undefined, rather than as defined in
3a635617 15061 the .plt section. */
252b5132 15062 sym->st_shndx = SHN_UNDEF;
3a635617 15063 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 15064 Otherwise, the PLT entry would provide a definition for
15065 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 15066 and so the symbol would never be NULL. Leave the value if
15067 there were any relocations where pointer equality matters
15068 (this is a clue for the dynamic linker, to make function
15069 pointer comparisons work between an application and shared
15070 library). */
97323ad1 15071 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 15072 sym->st_value = 0;
252b5132 15073 }
34e77a92
RS		 15074 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
15075 {
15076 /* At least one non-call relocation references this .iplt entry,
15077 so the .iplt entry is the function's canonical address. */
15078 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
15079 sym->st_target_internal = ST_BRANCH_TO_ARM;
15080 sym->st_shndx = (_bfd_elf_section_from_bfd_section
15081 (output_bfd, htab->root.iplt->output_section));
15082 sym->st_value = (h->plt.offset
15083 + htab->root.iplt->output_section->vma
15084 + htab->root.iplt->output_offset);
15085 }
252b5132
RH		 15086 }
15087
f5385ebf 15088 if (h->needs_copy)
252b5132
RH		 15089 {
15090 asection * s;
947216bf 15091 Elf_Internal_Rela rel;
252b5132
RH		 15092
15093 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 15094 BFD_ASSERT (h->dynindx != -1
15095 && (h->root.type == bfd_link_hash_defined
15096 || h->root.type == bfd_link_hash_defweak));
15097
362d30a1 15098 s = htab->srelbss;
252b5132
RH		 15099 BFD_ASSERT (s != NULL);
15100
00a97672 15101 rel.r_addend = 0;
252b5132
RH		 15102 rel.r_offset = (h->root.u.def.value
15103 + h->root.u.def.section->output_section->vma
15104 + h->root.u.def.section->output_offset);
15105 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
47beaa6a 15106 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 15107 }
15108
00a97672
RS		 15109 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
15110 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
15111 to the ".got" section. */
9637f6ef 15112 if (h == htab->root.hdynamic
00a97672 15113 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 15114 sym->st_shndx = SHN_ABS;
15115
b34976b6 15116 return TRUE;
252b5132
RH		 15117}
15118
0855e32b
NS		 15119static void
15120arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
15121 void *contents,
15122 const unsigned long *template, unsigned count)
15123{
15124 unsigned ix;
b38cadfb 15125
0855e32b
NS		 15126 for (ix = 0; ix != count; ix++)
15127 {
15128 unsigned long insn = template[ix];
15129
15130 /* Emit mov pc,rx if bx is not permitted. */
15131 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
15132 insn = (insn & 0xf000000f) | 0x01a0f000;
15133 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
15134 }
15135}
15136
99059e56
RM		 15137/* Install the special first PLT entry for elf32-arm-nacl. Unlike
15138 other variants, NaCl needs this entry in a static executable's
15139 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
15140 zero. For .iplt really only the last bundle is useful, and .iplt
15141 could have a shorter first entry, with each individual PLT entry's
15142 relative branch calculated differently so it targets the last
15143 bundle instead of the instruction before it (labelled .Lplt_tail
15144 above). But it's simpler to keep the size and layout of PLT0
15145 consistent with the dynamic case, at the cost of some dead code at
15146 the start of .iplt and the one dead store to the stack at the start
15147 of .Lplt_tail. */
15148static void
15149arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
15150 asection *plt, bfd_vma got_displacement)
15151{
15152 unsigned int i;
15153
15154 put_arm_insn (htab, output_bfd,
15155 elf32_arm_nacl_plt0_entry[0]
15156 | arm_movw_immediate (got_displacement),
15157 plt->contents + 0);
15158 put_arm_insn (htab, output_bfd,
15159 elf32_arm_nacl_plt0_entry[1]
15160 | arm_movt_immediate (got_displacement),
15161 plt->contents + 4);
15162
15163 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
15164 put_arm_insn (htab, output_bfd,
15165 elf32_arm_nacl_plt0_entry[i],
15166 plt->contents + (i * 4));
15167}
15168
252b5132
RH		 15169/* Finish up the dynamic sections. */
15170
b34976b6 15171static bfd_boolean
57e8b36a 15172elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 15173{
15174 bfd * dynobj;
15175 asection * sgot;
15176 asection * sdyn;
4dfe6ac6
NC		 15177 struct elf32_arm_link_hash_table *htab;
15178
15179 htab = elf32_arm_hash_table (info);
15180 if (htab == NULL)
15181 return FALSE;
252b5132
RH		 15182
15183 dynobj = elf_hash_table (info)->dynobj;
15184
362d30a1 15185 sgot = htab->root.sgotplt;
894891db
NC		 15186 /* A broken linker script might have discarded the dynamic sections.
15187 Catch this here so that we do not seg-fault later on. */
15188 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
15189 return FALSE;
3d4d4302 15190 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 15191
15192 if (elf_hash_table (info)->dynamic_sections_created)
15193 {
15194 asection *splt;
15195 Elf32_External_Dyn *dyncon, *dynconend;
15196
362d30a1 15197 splt = htab->root.splt;
24a1ba0f 15198 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 15199 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 15200
15201 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 15202 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 15203
252b5132
RH		 15204 for (; dyncon < dynconend; dyncon++)
15205 {
15206 Elf_Internal_Dyn dyn;
15207 const char * name;
15208 asection * s;
15209
15210 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
15211
15212 switch (dyn.d_tag)
15213 {
229fcec5
MM		 15214 unsigned int type;
15215
252b5132 15216 default:
7a2b07ff
NS		 15217 if (htab->vxworks_p
15218 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
15219 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 15220 break;
15221
229fcec5
MM		 15222 case DT_HASH:
15223 name = ".hash";
15224 goto get_vma_if_bpabi;
15225 case DT_STRTAB:
15226 name = ".dynstr";
15227 goto get_vma_if_bpabi;
15228 case DT_SYMTAB:
15229 name = ".dynsym";
15230 goto get_vma_if_bpabi;
c0042f5d
MM		 15231 case DT_VERSYM:
15232 name = ".gnu.version";
15233 goto get_vma_if_bpabi;
15234 case DT_VERDEF:
15235 name = ".gnu.version_d";
15236 goto get_vma_if_bpabi;
15237 case DT_VERNEED:
15238 name = ".gnu.version_r";
15239 goto get_vma_if_bpabi;
15240
252b5132
RH		 15241 case DT_PLTGOT:
15242 name = ".got";
15243 goto get_vma;
15244 case DT_JMPREL:
00a97672 15245 name = RELOC_SECTION (htab, ".plt");
252b5132
RH		 15246 get_vma:
15247 s = bfd_get_section_by_name (output_bfd, name);
05456594
NC		 15248 if (s == NULL)
15249 {
15250 /* PR ld/14397: Issue an error message if a required section is missing. */
15251 (*_bfd_error_handler)
15252 (_("error: required section '%s' not found in the linker script"), name);
15253 bfd_set_error (bfd_error_invalid_operation);
15254 return FALSE;
15255 }
229fcec5
MM		 15256 if (!htab->symbian_p)
15257 dyn.d_un.d_ptr = s->vma;
15258 else
15259 /* In the BPABI, tags in the PT_DYNAMIC section point
15260 at the file offset, not the memory address, for the
15261 convenience of the post linker. */
15262 dyn.d_un.d_ptr = s->filepos;
252b5132
RH		 15263 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15264 break;
15265
229fcec5
MM		 15266 get_vma_if_bpabi:
15267 if (htab->symbian_p)
15268 goto get_vma;
15269 break;
15270
252b5132 15271 case DT_PLTRELSZ:
362d30a1 15272 s = htab->root.srelplt;
252b5132 15273 BFD_ASSERT (s != NULL);
eea6121a 15274 dyn.d_un.d_val = s->size;
252b5132
RH		 15275 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15276 break;
906e58ca 15277
252b5132 15278 case DT_RELSZ:
00a97672 15279 case DT_RELASZ:
229fcec5
MM		 15280 if (!htab->symbian_p)
15281 {
15282 /* My reading of the SVR4 ABI indicates that the
15283 procedure linkage table relocs (DT_JMPREL) should be
15284 included in the overall relocs (DT_REL). This is
15285 what Solaris does. However, UnixWare can not handle
15286 that case. Therefore, we override the DT_RELSZ entry
15287 here to make it not include the JMPREL relocs. Since
00a97672 15288 the linker script arranges for .rel(a).plt to follow all
229fcec5
MM		 15289 other relocation sections, we don't have to worry
15290 about changing the DT_REL entry. */
362d30a1 15291 s = htab->root.srelplt;
229fcec5
MM		 15292 if (s != NULL)
15293 dyn.d_un.d_val -= s->size;
15294 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15295 break;
15296 }
8029a119 15297 /* Fall through. */
229fcec5
MM		 15298
15299 case DT_REL:
15300 case DT_RELA:
229fcec5
MM		 15301 /* In the BPABI, the DT_REL tag must point at the file
15302 offset, not the VMA, of the first relocation
15303 section. So, we use code similar to that in
15304 elflink.c, but do not check for SHF_ALLOC on the
15305 relcoation section, since relocations sections are
15306 never allocated under the BPABI. The comments above
15307 about Unixware notwithstanding, we include all of the
15308 relocations here. */
15309 if (htab->symbian_p)
15310 {
15311 unsigned int i;
15312 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
15313 ? SHT_REL : SHT_RELA);
15314 dyn.d_un.d_val = 0;
15315 for (i = 1; i < elf_numsections (output_bfd); i++)
15316 {
906e58ca 15317 Elf_Internal_Shdr *hdr
229fcec5
MM		 15318 = elf_elfsections (output_bfd)[i];
15319 if (hdr->sh_type == type)
15320 {
906e58ca 15321 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 15322 || dyn.d_tag == DT_RELASZ)
15323 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 15324 else if ((ufile_ptr) hdr->sh_offset
15325 <= dyn.d_un.d_val - 1)
229fcec5
MM		 15326 dyn.d_un.d_val = hdr->sh_offset;
15327 }
15328 }
15329 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15330 }
252b5132 15331 break;
88f7bcd5 15332
0855e32b 15333 case DT_TLSDESC_PLT:
99059e56 15334 s = htab->root.splt;
0855e32b
NS		 15335 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
15336 + htab->dt_tlsdesc_plt);
15337 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15338 break;
15339
15340 case DT_TLSDESC_GOT:
99059e56 15341 s = htab->root.sgot;
0855e32b 15342 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 15343 + htab->dt_tlsdesc_got);
0855e32b
NS		 15344 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15345 break;
15346
88f7bcd5
NC		 15347 /* Set the bottom bit of DT_INIT/FINI if the
15348 corresponding function is Thumb. */
15349 case DT_INIT:
15350 name = info->init_function;
15351 goto get_sym;
15352 case DT_FINI:
15353 name = info->fini_function;
15354 get_sym:
15355 /* If it wasn't set by elf_bfd_final_link
4cc11e76 15356 then there is nothing to adjust. */
88f7bcd5
NC		 15357 if (dyn.d_un.d_val != 0)
15358 {
15359 struct elf_link_hash_entry * eh;
15360
15361 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 15362 FALSE, FALSE, TRUE);
35fc36a8 15363 if (eh != NULL && eh->target_internal == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 15364 {
15365 dyn.d_un.d_val |= 1;
b34976b6 15366 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 15367 }
15368 }
15369 break;
252b5132
RH		 15370 }
15371 }
15372
24a1ba0f 15373 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 15374 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 15375 {
00a97672
RS		 15376 const bfd_vma *plt0_entry;
15377 bfd_vma got_address, plt_address, got_displacement;
15378
15379 /* Calculate the addresses of the GOT and PLT. */
15380 got_address = sgot->output_section->vma + sgot->output_offset;
15381 plt_address = splt->output_section->vma + splt->output_offset;
15382
15383 if (htab->vxworks_p)
15384 {
15385 /* The VxWorks GOT is relocated by the dynamic linker.
15386 Therefore, we must emit relocations rather than simply
15387 computing the values now. */
15388 Elf_Internal_Rela rel;
15389
15390 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 15391 put_arm_insn (htab, output_bfd, plt0_entry[0],
15392 splt->contents + 0);
15393 put_arm_insn (htab, output_bfd, plt0_entry[1],
15394 splt->contents + 4);
15395 put_arm_insn (htab, output_bfd, plt0_entry[2],
15396 splt->contents + 8);
00a97672
RS		 15397 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
15398
8029a119 15399 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 15400 rel.r_offset = plt_address + 12;
15401 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
15402 rel.r_addend = 0;
15403 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
15404 htab->srelplt2->contents);
15405 }
b38cadfb 15406 else if (htab->nacl_p)
99059e56
RM		 15407 arm_nacl_put_plt0 (htab, output_bfd, splt,
15408 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 15409 else if (using_thumb_only (htab))
15410 {
15411 got_displacement = got_address - (plt_address + 12);
15412
15413 plt0_entry = elf32_thumb2_plt0_entry;
15414 put_arm_insn (htab, output_bfd, plt0_entry[0],
15415 splt->contents + 0);
15416 put_arm_insn (htab, output_bfd, plt0_entry[1],
15417 splt->contents + 4);
15418 put_arm_insn (htab, output_bfd, plt0_entry[2],
15419 splt->contents + 8);
15420
15421 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
15422 }
00a97672
RS		 15423 else
15424 {
15425 got_displacement = got_address - (plt_address + 16);
15426
15427 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 15428 put_arm_insn (htab, output_bfd, plt0_entry[0],
15429 splt->contents + 0);
15430 put_arm_insn (htab, output_bfd, plt0_entry[1],
15431 splt->contents + 4);
15432 put_arm_insn (htab, output_bfd, plt0_entry[2],
15433 splt->contents + 8);
15434 put_arm_insn (htab, output_bfd, plt0_entry[3],
15435 splt->contents + 12);
5e681ec4 15436
5e681ec4 15437#ifdef FOUR_WORD_PLT
00a97672
RS		 15438 /* The displacement value goes in the otherwise-unused
15439 last word of the second entry. */
15440 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 15441#else
00a97672 15442 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 15443#endif
00a97672 15444 }
f7a74f8c 15445 }
252b5132
RH		 15446
15447 /* UnixWare sets the entsize of .plt to 4, although that doesn't
15448 really seem like the right value. */
74541ad4
AM		 15449 if (splt->output_section->owner == output_bfd)
15450 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 15451
0855e32b
NS		 15452 if (htab->dt_tlsdesc_plt)
15453 {
15454 bfd_vma got_address
15455 = sgot->output_section->vma + sgot->output_offset;
15456 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
15457 + htab->root.sgot->output_offset);
15458 bfd_vma plt_address
15459 = splt->output_section->vma + splt->output_offset;
15460
b38cadfb 15461 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 15462 splt->contents + htab->dt_tlsdesc_plt,
15463 dl_tlsdesc_lazy_trampoline, 6);
15464
15465 bfd_put_32 (output_bfd,
15466 gotplt_address + htab->dt_tlsdesc_got
15467 - (plt_address + htab->dt_tlsdesc_plt)
15468 - dl_tlsdesc_lazy_trampoline[6],
15469 splt->contents + htab->dt_tlsdesc_plt + 24);
15470 bfd_put_32 (output_bfd,
15471 got_address - (plt_address + htab->dt_tlsdesc_plt)
15472 - dl_tlsdesc_lazy_trampoline[7],
15473 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
15474 }
15475
15476 if (htab->tls_trampoline)
15477 {
b38cadfb 15478 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 15479 splt->contents + htab->tls_trampoline,
15480 tls_trampoline, 3);
15481#ifdef FOUR_WORD_PLT
15482 bfd_put_32 (output_bfd, 0x00000000,
15483 splt->contents + htab->tls_trampoline + 12);
b38cadfb 15484#endif
0855e32b
NS		 15485 }
15486
0e1862bb
L		 15487 if (htab->vxworks_p
15488 && !bfd_link_pic (info)
15489 && htab->root.splt->size > 0)
00a97672
RS		 15490 {
15491 /* Correct the .rel(a).plt.unloaded relocations. They will have
15492 incorrect symbol indexes. */
15493 int num_plts;
eed62c48 15494 unsigned char *p;
00a97672 15495
362d30a1 15496 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 15497 / htab->plt_entry_size);
15498 p = htab->srelplt2->contents + RELOC_SIZE (htab);
15499
15500 for (; num_plts; num_plts--)
15501 {
15502 Elf_Internal_Rela rel;
15503
15504 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
15505 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
15506 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
15507 p += RELOC_SIZE (htab);
15508
15509 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
15510 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
15511 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
15512 p += RELOC_SIZE (htab);
15513 }
15514 }
252b5132
RH		 15515 }
15516
99059e56
RM		 15517 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
15518 /* NaCl uses a special first entry in .iplt too. */
15519 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
15520
252b5132 15521 /* Fill in the first three entries in the global offset table. */
229fcec5 15522 if (sgot)
252b5132 15523 {
229fcec5
MM		 15524 if (sgot->size > 0)
15525 {
15526 if (sdyn == NULL)
15527 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
15528 else
15529 bfd_put_32 (output_bfd,
15530 sdyn->output_section->vma + sdyn->output_offset,
15531 sgot->contents);
15532 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
15533 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
15534 }
252b5132 15535
229fcec5
MM		 15536 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
15537 }
252b5132 15538
b34976b6 15539 return TRUE;
252b5132
RH		 15540}
15541
ba96a88f 15542static void
57e8b36a 15543elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 15544{
9b485d32 15545 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 15546 struct elf32_arm_link_hash_table *globals;
ac4c9b04 15547 struct elf_segment_map *m;
ba96a88f
NC		 15548
15549 i_ehdrp = elf_elfheader (abfd);
15550
94a3258f
PB		 15551 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
15552 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
15553 else
7394f108 15554 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 15555 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 15556
93204d3a
PB		 15557 if (link_info)
15558 {
15559 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 15560 if (globals != NULL && globals->byteswap_code)
93204d3a
PB		 15561 i_ehdrp->e_flags |= EF_ARM_BE8;
15562 }
3bfcb652
NC		 15563
15564 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
15565 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
15566 {
15567 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 15568 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 15569 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
15570 else
15571 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
15572 }
ac4c9b04
MG		 15573
15574 /* Scan segment to set p_flags attribute if it contains only sections with
15575 SHF_ARM_NOREAD flag. */
15576 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
15577 {
15578 unsigned int j;
15579
15580 if (m->count == 0)
15581 continue;
15582 for (j = 0; j < m->count; j++)
15583 {
15584 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_NOREAD))
15585 break;
15586 }
15587 if (j == m->count)
15588 {
15589 m->p_flags = PF_X;
15590 m->p_flags_valid = 1;
15591 }
15592 }
ba96a88f
NC		 15593}
15594
99e4ae17 15595static enum elf_reloc_type_class
7e612e98
AM		 15596elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
15597 const asection *rel_sec ATTRIBUTE_UNUSED,
15598 const Elf_Internal_Rela *rela)
99e4ae17 15599{
f51e552e 15600 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 15601 {
15602 case R_ARM_RELATIVE:
15603 return reloc_class_relative;
15604 case R_ARM_JUMP_SLOT:
15605 return reloc_class_plt;
15606 case R_ARM_COPY:
15607 return reloc_class_copy;
109575d7
JW		 15608 case R_ARM_IRELATIVE:
15609 return reloc_class_ifunc;
99e4ae17
AJ		 15610 default:
15611 return reloc_class_normal;
15612 }
15613}
15614
e489d0ae 15615static void
57e8b36a 15616elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 15617{
5a6c6817 15618 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 15619}
15620
40a18ebd
NC		 15621/* Return TRUE if this is an unwinding table entry. */
15622
15623static bfd_boolean
15624is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
15625{
0112cd26
NC		 15626 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
15627 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 15628}
15629
15630
15631/* Set the type and flags for an ARM section. We do this by
15632 the section name, which is a hack, but ought to work. */
15633
15634static bfd_boolean
15635elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
15636{
15637 const char * name;
15638
15639 name = bfd_get_section_name (abfd, sec);
15640
15641 if (is_arm_elf_unwind_section_name (abfd, name))
15642 {
15643 hdr->sh_type = SHT_ARM_EXIDX;
15644 hdr->sh_flags |= SHF_LINK_ORDER;
15645 }
ac4c9b04
MG		 15646
15647 if (sec->flags & SEC_ELF_NOREAD)
15648 hdr->sh_flags |= SHF_ARM_NOREAD;
15649
40a18ebd
NC		 15650 return TRUE;
15651}
15652
6dc132d9
L		 15653/* Handle an ARM specific section when reading an object file. This is
15654 called when bfd_section_from_shdr finds a section with an unknown
15655 type. */
40a18ebd
NC		 15656
15657static bfd_boolean
15658elf32_arm_section_from_shdr (bfd *abfd,
15659 Elf_Internal_Shdr * hdr,
6dc132d9
L		 15660 const char *name,
15661 int shindex)
40a18ebd
NC		 15662{
15663 /* There ought to be a place to keep ELF backend specific flags, but
15664 at the moment there isn't one. We just keep track of the
15665 sections by their name, instead. Fortunately, the ABI gives
15666 names for all the ARM specific sections, so we will probably get
15667 away with this. */
15668 switch (hdr->sh_type)
15669 {
15670 case SHT_ARM_EXIDX:
0951f019
RE		 15671 case SHT_ARM_PREEMPTMAP:
15672 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 15673 break;
15674
15675 default:
15676 return FALSE;
15677 }
15678
6dc132d9 15679 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 15680 return FALSE;
15681
15682 return TRUE;
15683}
e489d0ae 15684
44444f50
NC		 15685static _arm_elf_section_data *
15686get_arm_elf_section_data (asection * sec)
15687{
47b2e99c
JZ		 15688 if (sec && sec->owner && is_arm_elf (sec->owner))
15689 return elf32_arm_section_data (sec);
44444f50
NC		 15690 else
15691 return NULL;
8e3de13a
NC		 15692}
15693
4e617b1e
PB		 15694typedef struct
15695{
57402f1e 15696 void *flaginfo;
4e617b1e 15697 struct bfd_link_info *info;
91a5743d
PB		 15698 asection *sec;
15699 int sec_shndx;
6e0b88f1
AM		 15700 int (*func) (void *, const char *, Elf_Internal_Sym *,
15701 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 15702} output_arch_syminfo;
15703
15704enum map_symbol_type
15705{
15706 ARM_MAP_ARM,
15707 ARM_MAP_THUMB,
15708 ARM_MAP_DATA
15709};
15710
15711
7413f23f 15712/* Output a single mapping symbol. */
4e617b1e
PB		 15713
15714static bfd_boolean
7413f23f
DJ		 15715elf32_arm_output_map_sym (output_arch_syminfo *osi,
15716 enum map_symbol_type type,
15717 bfd_vma offset)
4e617b1e
PB		 15718{
15719 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 15720 Elf_Internal_Sym sym;
15721
91a5743d
PB		 15722 sym.st_value = osi->sec->output_section->vma
15723 + osi->sec->output_offset
15724 + offset;
4e617b1e
PB		 15725 sym.st_size = 0;
15726 sym.st_other = 0;
15727 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 15728 sym.st_shndx = osi->sec_shndx;
35fc36a8 15729 sym.st_target_internal = 0;
fe33d2fa 15730 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 15731 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 15732}
15733
34e77a92
RS		 15734/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
15735 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 15736
15737static bfd_boolean
34e77a92
RS		 15738elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
15739 bfd_boolean is_iplt_entry_p,
15740 union gotplt_union *root_plt,
15741 struct arm_plt_info *arm_plt)
4e617b1e 15742{
4e617b1e 15743 struct elf32_arm_link_hash_table *htab;
34e77a92 15744 bfd_vma addr, plt_header_size;
4e617b1e 15745
34e77a92 15746 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 15747 return TRUE;
15748
4dfe6ac6
NC		 15749 htab = elf32_arm_hash_table (osi->info);
15750 if (htab == NULL)
15751 return FALSE;
15752
34e77a92
RS		 15753 if (is_iplt_entry_p)
15754 {
15755 osi->sec = htab->root.iplt;
15756 plt_header_size = 0;
15757 }
15758 else
15759 {
15760 osi->sec = htab->root.splt;
15761 plt_header_size = htab->plt_header_size;
15762 }
15763 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
15764 (osi->info->output_bfd, osi->sec->output_section));
15765
15766 addr = root_plt->offset & -2;
4e617b1e
PB		 15767 if (htab->symbian_p)
15768 {
7413f23f 15769 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15770 return FALSE;
7413f23f 15771 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 15772 return FALSE;
15773 }
15774 else if (htab->vxworks_p)
15775 {
7413f23f 15776 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15777 return FALSE;
7413f23f 15778 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 15779 return FALSE;
7413f23f 15780 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 15781 return FALSE;
7413f23f 15782 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 15783 return FALSE;
15784 }
b38cadfb
NC		 15785 else if (htab->nacl_p)
15786 {
15787 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
15788 return FALSE;
15789 }
eed94f8f
NC		 15790 else if (using_thumb_only (htab))
15791 {
15792 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
15793 return FALSE;
6a631e86 15794 }
4e617b1e
PB		 15795 else
15796 {
34e77a92 15797 bfd_boolean thumb_stub_p;
bd97cb95 15798
34e77a92
RS		 15799 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
15800 if (thumb_stub_p)
4e617b1e 15801 {
7413f23f 15802 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 15803 return FALSE;
15804 }
15805#ifdef FOUR_WORD_PLT
7413f23f 15806 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15807 return FALSE;
7413f23f 15808 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 15809 return FALSE;
15810#else
906e58ca 15811 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 15812 so only need to output a mapping symbol for the first PLT entry and
15813 entries with thumb thunks. */
34e77a92 15814 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 15815 {
7413f23f 15816 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 15817 return FALSE;
15818 }
15819#endif
15820 }
15821
15822 return TRUE;
15823}
15824
34e77a92
RS		 15825/* Output mapping symbols for PLT entries associated with H. */
15826
15827static bfd_boolean
15828elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
15829{
15830 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
15831 struct elf32_arm_link_hash_entry *eh;
15832
15833 if (h->root.type == bfd_link_hash_indirect)
15834 return TRUE;
15835
15836 if (h->root.type == bfd_link_hash_warning)
15837 /* When warning symbols are created, they **replace** the "real"
15838 entry in the hash table, thus we never get to see the real
15839 symbol in a hash traversal. So look at it now. */
15840 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15841
15842 eh = (struct elf32_arm_link_hash_entry *) h;
15843 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
15844 &h->plt, &eh->plt);
15845}
15846
7413f23f
DJ		 15847/* Output a single local symbol for a generated stub. */
15848
15849static bfd_boolean
15850elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
15851 bfd_vma offset, bfd_vma size)
15852{
7413f23f
DJ		 15853 Elf_Internal_Sym sym;
15854
7413f23f
DJ		 15855 sym.st_value = osi->sec->output_section->vma
15856 + osi->sec->output_offset
15857 + offset;
15858 sym.st_size = size;
15859 sym.st_other = 0;
15860 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
15861 sym.st_shndx = osi->sec_shndx;
35fc36a8 15862 sym.st_target_internal = 0;
57402f1e 15863 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 15864}
4e617b1e 15865
da5938a2 15866static bfd_boolean
8029a119
NC		 15867arm_map_one_stub (struct bfd_hash_entry * gen_entry,
15868 void * in_arg)
da5938a2
NC		 15869{
15870 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 15871 asection *stub_sec;
15872 bfd_vma addr;
7413f23f 15873 char *stub_name;
9a008db3 15874 output_arch_syminfo *osi;
d3ce72d0 15875 const insn_sequence *template_sequence;
461a49ca
DJ		 15876 enum stub_insn_type prev_type;
15877 int size;
15878 int i;
15879 enum map_symbol_type sym_type;
da5938a2
NC		 15880
15881 /* Massage our args to the form they really have. */
15882 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 15883 osi = (output_arch_syminfo *) in_arg;
da5938a2 15884
da5938a2
NC		 15885 stub_sec = stub_entry->stub_sec;
15886
15887 /* Ensure this stub is attached to the current section being
7413f23f 15888 processed. */
da5938a2
NC		 15889 if (stub_sec != osi->sec)
15890 return TRUE;
15891
7413f23f
DJ		 15892 addr = (bfd_vma) stub_entry->stub_offset;
15893 stub_name = stub_entry->output_name;
da5938a2 15894
d3ce72d0
NC		 15895 template_sequence = stub_entry->stub_template;
15896 switch (template_sequence[0].type)
7413f23f 15897 {
461a49ca
DJ		 15898 case ARM_TYPE:
15899 if (!elf32_arm_output_stub_sym (osi, stub_name, addr, stub_entry->stub_size))
da5938a2
NC		 15900 return FALSE;
15901 break;
461a49ca 15902 case THUMB16_TYPE:
48229727 15903 case THUMB32_TYPE:
461a49ca
DJ		 15904 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
15905 stub_entry->stub_size))
da5938a2
NC		 15906 return FALSE;
15907 break;
15908 default:
15909 BFD_FAIL ();
48229727 15910 return 0;
7413f23f 15911 }
da5938a2 15912
461a49ca
DJ		 15913 prev_type = DATA_TYPE;
15914 size = 0;
15915 for (i = 0; i < stub_entry->stub_template_size; i++)
15916 {
d3ce72d0 15917 switch (template_sequence[i].type)
461a49ca
DJ		 15918 {
15919 case ARM_TYPE:
15920 sym_type = ARM_MAP_ARM;
15921 break;
15922
15923 case THUMB16_TYPE:
48229727 15924 case THUMB32_TYPE:
461a49ca
DJ		 15925 sym_type = ARM_MAP_THUMB;
15926 break;
15927
15928 case DATA_TYPE:
15929 sym_type = ARM_MAP_DATA;
15930 break;
15931
15932 default:
15933 BFD_FAIL ();
4e31c731 15934 return FALSE;
461a49ca
DJ		 15935 }
15936
d3ce72d0 15937 if (template_sequence[i].type != prev_type)
461a49ca 15938 {
d3ce72d0 15939 prev_type = template_sequence[i].type;
461a49ca
DJ		 15940 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
15941 return FALSE;
15942 }
15943
d3ce72d0 15944 switch (template_sequence[i].type)
461a49ca
DJ		 15945 {
15946 case ARM_TYPE:
48229727 15947 case THUMB32_TYPE:
461a49ca
DJ		 15948 size += 4;
15949 break;
15950
15951 case THUMB16_TYPE:
15952 size += 2;
15953 break;
15954
15955 case DATA_TYPE:
15956 size += 4;
15957 break;
15958
15959 default:
15960 BFD_FAIL ();
4e31c731 15961 return FALSE;
461a49ca
DJ		 15962 }
15963 }
15964
da5938a2
NC		 15965 return TRUE;
15966}
15967
33811162
DG		 15968/* Output mapping symbols for linker generated sections,
15969 and for those data-only sections that do not have a
15970 $d. */
4e617b1e
PB		 15971
15972static bfd_boolean
15973elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 15974 struct bfd_link_info *info,
57402f1e 15975 void *flaginfo,
6e0b88f1
AM		 15976 int (*func) (void *, const char *,
15977 Elf_Internal_Sym *,
15978 asection *,
15979 struct elf_link_hash_entry *))
4e617b1e
PB		 15980{
15981 output_arch_syminfo osi;
15982 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 15983 bfd_vma offset;
15984 bfd_size_type size;
33811162 15985 bfd *input_bfd;
4e617b1e
PB		 15986
15987 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15988 if (htab == NULL)
15989 return FALSE;
15990
906e58ca 15991 check_use_blx (htab);
91a5743d 15992
57402f1e 15993 osi.flaginfo = flaginfo;
4e617b1e
PB		 15994 osi.info = info;
15995 osi.func = func;
906e58ca 15996
33811162
DG		 15997 /* Add a $d mapping symbol to data-only sections that
15998 don't have any mapping symbol. This may result in (harmless) redundant
15999 mapping symbols. */
16000 for (input_bfd = info->input_bfds;
16001 input_bfd != NULL;
c72f2fb2 16002 input_bfd = input_bfd->link.next)
33811162
DG		 16003 {
16004 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
16005 for (osi.sec = input_bfd->sections;
16006 osi.sec != NULL;
16007 osi.sec = osi.sec->next)
16008 {
16009 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 16010 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
16011 != 0)
33811162
DG		 16012 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
16013 == SEC_HAS_CONTENTS
16014 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 16015 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 16016 && osi.sec->size > 0
16017 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 16018 {
16019 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16020 (output_bfd, osi.sec->output_section);
16021 if (osi.sec_shndx != (int)SHN_BAD)
16022 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
16023 }
16024 }
16025 }
16026
91a5743d
PB		 16027 /* ARM->Thumb glue. */
16028 if (htab->arm_glue_size > 0)
16029 {
3d4d4302
AM		 16030 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
16031 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 16032
16033 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16034 (output_bfd, osi.sec->output_section);
0e1862bb 16035 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 16036 || htab->pic_veneer)
16037 size = ARM2THUMB_PIC_GLUE_SIZE;
16038 else if (htab->use_blx)
16039 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
16040 else
16041 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 16042
91a5743d
PB		 16043 for (offset = 0; offset < htab->arm_glue_size; offset += size)
16044 {
7413f23f
DJ		 16045 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
16046 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 16047 }
16048 }
16049
16050 /* Thumb->ARM glue. */
16051 if (htab->thumb_glue_size > 0)
16052 {
3d4d4302
AM		 16053 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
16054 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 16055
16056 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16057 (output_bfd, osi.sec->output_section);
16058 size = THUMB2ARM_GLUE_SIZE;
16059
16060 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
16061 {
7413f23f
DJ		 16062 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
16063 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 16064 }
16065 }
16066
845b51d6
PB		 16067 /* ARMv4 BX veneers. */
16068 if (htab->bx_glue_size > 0)
16069 {
3d4d4302
AM		 16070 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
16071 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 16072
16073 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16074 (output_bfd, osi.sec->output_section);
16075
7413f23f 16076 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 16077 }
16078
8029a119
NC		 16079 /* Long calls stubs. */
16080 if (htab->stub_bfd && htab->stub_bfd->sections)
16081 {
da5938a2 16082 asection* stub_sec;
8029a119 16083
da5938a2
NC		 16084 for (stub_sec = htab->stub_bfd->sections;
16085 stub_sec != NULL;
8029a119
NC		 16086 stub_sec = stub_sec->next)
16087 {
16088 /* Ignore non-stub sections. */
16089 if (!strstr (stub_sec->name, STUB_SUFFIX))
16090 continue;
da5938a2 16091
8029a119 16092 osi.sec = stub_sec;
da5938a2 16093
8029a119
NC		 16094 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16095 (output_bfd, osi.sec->output_section);
da5938a2 16096
8029a119
NC		 16097 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
16098 }
16099 }
da5938a2 16100
91a5743d 16101 /* Finally, output mapping symbols for the PLT. */
34e77a92 16102 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 16103 {
34e77a92
RS		 16104 osi.sec = htab->root.splt;
16105 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
16106 (output_bfd, osi.sec->output_section));
16107
16108 /* Output mapping symbols for the plt header. SymbianOS does not have a
16109 plt header. */
16110 if (htab->vxworks_p)
16111 {
16112 /* VxWorks shared libraries have no PLT header. */
0e1862bb 16113 if (!bfd_link_pic (info))
34e77a92
RS		 16114 {
16115 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16116 return FALSE;
16117 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
16118 return FALSE;
16119 }
16120 }
b38cadfb
NC		 16121 else if (htab->nacl_p)
16122 {
16123 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16124 return FALSE;
16125 }
eed94f8f
NC		 16126 else if (using_thumb_only (htab))
16127 {
16128 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
16129 return FALSE;
16130 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
16131 return FALSE;
16132 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
16133 return FALSE;
16134 }
34e77a92 16135 else if (!htab->symbian_p)
4e617b1e 16136 {
7413f23f 16137 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 16138 return FALSE;
34e77a92
RS		 16139#ifndef FOUR_WORD_PLT
16140 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 16141 return FALSE;
34e77a92 16142#endif
4e617b1e
PB		 16143 }
16144 }
99059e56
RM		 16145 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
16146 {
16147 /* NaCl uses a special first entry in .iplt too. */
16148 osi.sec = htab->root.iplt;
16149 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
16150 (output_bfd, osi.sec->output_section));
16151 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16152 return FALSE;
16153 }
34e77a92
RS		 16154 if ((htab->root.splt && htab->root.splt->size > 0)
16155 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 16156 {
34e77a92
RS		 16157 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
16158 for (input_bfd = info->input_bfds;
16159 input_bfd != NULL;
c72f2fb2 16160 input_bfd = input_bfd->link.next)
34e77a92
RS		 16161 {
16162 struct arm_local_iplt_info **local_iplt;
16163 unsigned int i, num_syms;
4e617b1e 16164
34e77a92
RS		 16165 local_iplt = elf32_arm_local_iplt (input_bfd);
16166 if (local_iplt != NULL)
16167 {
16168 num_syms = elf_symtab_hdr (input_bfd).sh_info;
16169 for (i = 0; i < num_syms; i++)
16170 if (local_iplt[i] != NULL
16171 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
16172 &local_iplt[i]->root,
16173 &local_iplt[i]->arm))
16174 return FALSE;
16175 }
16176 }
16177 }
0855e32b
NS		 16178 if (htab->dt_tlsdesc_plt != 0)
16179 {
16180 /* Mapping symbols for the lazy tls trampoline. */
16181 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
16182 return FALSE;
b38cadfb 16183
0855e32b
NS		 16184 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
16185 htab->dt_tlsdesc_plt + 24))
16186 return FALSE;
16187 }
16188 if (htab->tls_trampoline != 0)
16189 {
16190 /* Mapping symbols for the tls trampoline. */
16191 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
16192 return FALSE;
16193#ifdef FOUR_WORD_PLT
16194 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
16195 htab->tls_trampoline + 12))
16196 return FALSE;
b38cadfb 16197#endif
0855e32b 16198 }
b38cadfb 16199
4e617b1e
PB		 16200 return TRUE;
16201}
16202
e489d0ae
PB		 16203/* Allocate target specific section data. */
16204
16205static bfd_boolean
16206elf32_arm_new_section_hook (bfd *abfd, asection *sec)
16207{
f592407e
AM		 16208 if (!sec->used_by_bfd)
16209 {
16210 _arm_elf_section_data *sdata;
16211 bfd_size_type amt = sizeof (*sdata);
e489d0ae 16212
21d799b5 16213 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 16214 if (sdata == NULL)
16215 return FALSE;
16216 sec->used_by_bfd = sdata;
16217 }
e489d0ae
PB		 16218
16219 return _bfd_elf_new_section_hook (abfd, sec);
16220}
16221
16222
16223/* Used to order a list of mapping symbols by address. */
16224
16225static int
16226elf32_arm_compare_mapping (const void * a, const void * b)
16227{
7f6a71ff
JM		 16228 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
16229 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
16230
16231 if (amap->vma > bmap->vma)
16232 return 1;
16233 else if (amap->vma < bmap->vma)
16234 return -1;
16235 else if (amap->type > bmap->type)
16236 /* Ensure results do not depend on the host qsort for objects with
16237 multiple mapping symbols at the same address by sorting on type
16238 after vma. */
16239 return 1;
16240 else if (amap->type < bmap->type)
16241 return -1;
16242 else
16243 return 0;
e489d0ae
PB		 16244}
16245
2468f9c9
PB		 16246/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
16247
16248static unsigned long
16249offset_prel31 (unsigned long addr, bfd_vma offset)
16250{
16251 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
16252}
16253
16254/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
16255 relocations. */
16256
16257static void
16258copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
16259{
16260 unsigned long first_word = bfd_get_32 (output_bfd, from);
16261 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 16262
2468f9c9
PB		 16263 /* High bit of first word is supposed to be zero. */
16264 if ((first_word & 0x80000000ul) == 0)
16265 first_word = offset_prel31 (first_word, offset);
b38cadfb 16266
2468f9c9
PB		 16267 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
16268 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
16269 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
16270 second_word = offset_prel31 (second_word, offset);
b38cadfb 16271
2468f9c9
PB		 16272 bfd_put_32 (output_bfd, first_word, to);
16273 bfd_put_32 (output_bfd, second_word, to + 4);
16274}
e489d0ae 16275
48229727
JB		 16276/* Data for make_branch_to_a8_stub(). */
16277
b38cadfb
NC		 16278struct a8_branch_to_stub_data
16279{
48229727
JB		 16280 asection *writing_section;
16281 bfd_byte *contents;
16282};
16283
16284
16285/* Helper to insert branches to Cortex-A8 erratum stubs in the right
16286 places for a particular section. */
16287
16288static bfd_boolean
16289make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 16290 void *in_arg)
48229727
JB		 16291{
16292 struct elf32_arm_stub_hash_entry *stub_entry;
16293 struct a8_branch_to_stub_data *data;
16294 bfd_byte *contents;
16295 unsigned long branch_insn;
16296 bfd_vma veneered_insn_loc, veneer_entry_loc;
16297 bfd_signed_vma branch_offset;
16298 bfd *abfd;
8d9d9490 16299 unsigned int loc;
48229727
JB		 16300
16301 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
16302 data = (struct a8_branch_to_stub_data *) in_arg;
16303
16304 if (stub_entry->target_section != data->writing_section
4563a860 16305 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 16306 return TRUE;
16307
16308 contents = data->contents;
16309
8d9d9490
TP		 16310 /* We use target_section as Cortex-A8 erratum workaround stubs are only
16311 generated when both source and target are in the same section. */
48229727
JB		 16312 veneered_insn_loc = stub_entry->target_section->output_section->vma
16313 + stub_entry->target_section->output_offset
8d9d9490 16314 + stub_entry->source_value;
48229727
JB		 16315
16316 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
16317 + stub_entry->stub_sec->output_offset
16318 + stub_entry->stub_offset;
16319
16320 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
16321 veneered_insn_loc &= ~3u;
16322
16323 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
16324
16325 abfd = stub_entry->target_section->owner;
8d9d9490 16326 loc = stub_entry->source_value;
48229727
JB		 16327
16328 /* We attempt to avoid this condition by setting stubs_always_after_branch
16329 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
16330 This check is just to be on the safe side... */
16331 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
16332 {
16333 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub is "
16334 "allocated in unsafe location"), abfd);
16335 return FALSE;
16336 }
16337
16338 switch (stub_entry->stub_type)
16339 {
16340 case arm_stub_a8_veneer_b:
16341 case arm_stub_a8_veneer_b_cond:
16342 branch_insn = 0xf0009000;
16343 goto jump24;
16344
16345 case arm_stub_a8_veneer_blx:
16346 branch_insn = 0xf000e800;
16347 goto jump24;
16348
16349 case arm_stub_a8_veneer_bl:
16350 {
16351 unsigned int i1, j1, i2, j2, s;
16352
16353 branch_insn = 0xf000d000;
16354
16355 jump24:
16356 if (branch_offset < -16777216 || branch_offset > 16777214)
16357 {
16358 /* There's not much we can do apart from complain if this
16359 happens. */
16360 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub out "
16361 "of range (input file too large)"), abfd);
16362 return FALSE;
16363 }
16364
16365 /* i1 = not(j1 eor s), so:
16366 not i1 = j1 eor s
16367 j1 = (not i1) eor s. */
16368
16369 branch_insn |= (branch_offset >> 1) & 0x7ff;
16370 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
16371 i2 = (branch_offset >> 22) & 1;
16372 i1 = (branch_offset >> 23) & 1;
16373 s = (branch_offset >> 24) & 1;
16374 j1 = (!i1) ^ s;
16375 j2 = (!i2) ^ s;
16376 branch_insn |= j2 << 11;
16377 branch_insn |= j1 << 13;
16378 branch_insn |= s << 26;
16379 }
16380 break;
16381
16382 default:
16383 BFD_FAIL ();
16384 return FALSE;
16385 }
16386
8d9d9490
TP		 16387 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
16388 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 16389
16390 return TRUE;
16391}
16392
a504d23a
LA		 16393/* Beginning of stm32l4xx work-around. */
16394
16395/* Functions encoding instructions necessary for the emission of the
16396 fix-stm32l4xx-629360.
16397 Encoding is extracted from the
16398 ARM (C) Architecture Reference Manual
16399 ARMv7-A and ARMv7-R edition
16400 ARM DDI 0406C.b (ID072512). */
16401
16402static inline bfd_vma
82188b29 16403create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 16404{
16405 /* A8.8.18 B (A8-334)
16406 B target_address (Encoding T4). */
16407 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
16408 /* jump offset is: S:I1:I2:imm10:imm11:0. */
16409 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
16410
a504d23a
LA		 16411 int s = ((branch_offset & 0x1000000) >> 24);
16412 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
16413 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
16414
16415 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
16416 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
16417
16418 bfd_vma patched_inst = 0xf0009000
16419 | s << 26 /* S. */
16420 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
16421 | j1 << 13 /* J1. */
16422 | j2 << 11 /* J2. */
16423 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
16424
16425 return patched_inst;
16426}
16427
16428static inline bfd_vma
16429create_instruction_ldmia (int base_reg, int wback, int reg_mask)
16430{
16431 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
16432 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
16433 bfd_vma patched_inst = 0xe8900000
16434 | (/*W=*/wback << 21)
16435 | (base_reg << 16)
16436 | (reg_mask & 0x0000ffff);
16437
16438 return patched_inst;
16439}
16440
16441static inline bfd_vma
16442create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
16443{
16444 /* A8.8.60 LDMDB/LDMEA (A8-402)
16445 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
16446 bfd_vma patched_inst = 0xe9100000
16447 | (/*W=*/wback << 21)
16448 | (base_reg << 16)
16449 | (reg_mask & 0x0000ffff);
16450
16451 return patched_inst;
16452}
16453
16454static inline bfd_vma
16455create_instruction_mov (int target_reg, int source_reg)
16456{
16457 /* A8.8.103 MOV (register) (A8-486)
16458 MOV Rd, Rm (Encoding T1). */
16459 bfd_vma patched_inst = 0x4600
16460 | (target_reg & 0x7)
16461 | ((target_reg & 0x8) >> 3) << 7
16462 | (source_reg << 3);
16463
16464 return patched_inst;
16465}
16466
16467static inline bfd_vma
16468create_instruction_sub (int target_reg, int source_reg, int value)
16469{
16470 /* A8.8.221 SUB (immediate) (A8-708)
16471 SUB Rd, Rn, #value (Encoding T3). */
16472 bfd_vma patched_inst = 0xf1a00000
16473 | (target_reg << 8)
16474 | (source_reg << 16)
16475 | (/*S=*/0 << 20)
16476 | ((value & 0x800) >> 11) << 26
16477 | ((value & 0x700) >> 8) << 12
16478 | (value & 0x0ff);
16479
16480 return patched_inst;
16481}
16482
16483static inline bfd_vma
9239bbd3 16484create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 16485 int first_reg)
16486{
16487 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 16488 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
16489 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 16490 | (/*W=*/wback << 21)
16491 | (base_reg << 16)
9239bbd3
CM		 16492 | (num_words & 0x000000ff)
16493 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 16494 | (first_reg & 0x00000001) << 22;
16495
16496 return patched_inst;
16497}
16498
16499static inline bfd_vma
9239bbd3
CM		 16500create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
16501 int first_reg)
a504d23a
LA		 16502{
16503 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 16504 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
16505 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 16506 | (base_reg << 16)
9239bbd3
CM		 16507 | (num_words & 0x000000ff)
16508 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 16509 | (first_reg & 0x00000001) << 22;
16510
16511 return patched_inst;
16512}
16513
16514static inline bfd_vma
16515create_instruction_udf_w (int value)
16516{
16517 /* A8.8.247 UDF (A8-758)
16518 Undefined (Encoding T2). */
16519 bfd_vma patched_inst = 0xf7f0a000
16520 | (value & 0x00000fff)
16521 | (value & 0x000f0000) << 16;
16522
16523 return patched_inst;
16524}
16525
16526static inline bfd_vma
16527create_instruction_udf (int value)
16528{
16529 /* A8.8.247 UDF (A8-758)
16530 Undefined (Encoding T1). */
16531 bfd_vma patched_inst = 0xde00
16532 | (value & 0xff);
16533
16534 return patched_inst;
16535}
16536
16537/* Functions writing an instruction in memory, returning the next
16538 memory position to write to. */
16539
16540static inline bfd_byte *
16541push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
16542 bfd * output_bfd, bfd_byte *pt, insn32 insn)
16543{
16544 put_thumb2_insn (htab, output_bfd, insn, pt);
16545 return pt + 4;
16546}
16547
16548static inline bfd_byte *
16549push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
16550 bfd * output_bfd, bfd_byte *pt, insn32 insn)
16551{
16552 put_thumb_insn (htab, output_bfd, insn, pt);
16553 return pt + 2;
16554}
16555
16556/* Function filling up a region in memory with T1 and T2 UDFs taking
16557 care of alignment. */
16558
16559static bfd_byte *
16560stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
16561 bfd * output_bfd,
16562 const bfd_byte * const base_stub_contents,
16563 bfd_byte * const from_stub_contents,
16564 const bfd_byte * const end_stub_contents)
16565{
16566 bfd_byte *current_stub_contents = from_stub_contents;
16567
16568 /* Fill the remaining of the stub with deterministic contents : UDF
16569 instructions.
16570 Check if realignment is needed on modulo 4 frontier using T1, to
16571 further use T2. */
16572 if ((current_stub_contents < end_stub_contents)
16573 && !((current_stub_contents - base_stub_contents) % 2)
16574 && ((current_stub_contents - base_stub_contents) % 4))
16575 current_stub_contents =
16576 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16577 create_instruction_udf (0));
16578
16579 for (; current_stub_contents < end_stub_contents;)
16580 current_stub_contents =
16581 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16582 create_instruction_udf_w (0));
16583
16584 return current_stub_contents;
16585}
16586
16587/* Functions writing the stream of instructions equivalent to the
16588 derived sequence for ldmia, ldmdb, vldm respectively. */
16589
16590static void
16591stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
16592 bfd * output_bfd,
16593 const insn32 initial_insn,
16594 const bfd_byte *const initial_insn_addr,
16595 bfd_byte *const base_stub_contents)
16596{
16597 int wback = (initial_insn & 0x00200000) >> 21;
16598 int ri, rn = (initial_insn & 0x000F0000) >> 16;
16599 int insn_all_registers = initial_insn & 0x0000ffff;
16600 int insn_low_registers, insn_high_registers;
16601 int usable_register_mask;
16602 int nb_registers = popcount (insn_all_registers);
16603 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
16604 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
16605 bfd_byte *current_stub_contents = base_stub_contents;
16606
16607 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
16608
16609 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16610 smaller than 8 registers load sequences that do not cause the
16611 hardware issue. */
16612 if (nb_registers <= 8)
16613 {
16614 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
16615 current_stub_contents =
16616 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16617 initial_insn);
16618
16619 /* B initial_insn_addr+4. */
16620 if (!restore_pc)
16621 current_stub_contents =
16622 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16623 create_instruction_branch_absolute
82188b29
NC		 16624 (initial_insn_addr - current_stub_contents));
16625
a504d23a
LA		 16626
16627 /* Fill the remaining of the stub with deterministic contents. */
16628 current_stub_contents =
16629 stm32l4xx_fill_stub_udf (htab, output_bfd,
16630 base_stub_contents, current_stub_contents,
16631 base_stub_contents +
16632 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16633
16634 return;
16635 }
16636
16637 /* - reg_list[13] == 0. */
16638 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
16639
16640 /* - reg_list[14] & reg_list[15] != 1. */
16641 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
16642
16643 /* - if (wback==1) reg_list[rn] == 0. */
16644 BFD_ASSERT (!wback || !restore_rn);
16645
16646 /* - nb_registers > 8. */
16647 BFD_ASSERT (popcount (insn_all_registers) > 8);
16648
16649 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
16650
16651 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
16652 - One with the 7 lowest registers (register mask 0x007F)
16653 This LDM will finally contain between 2 and 7 registers
16654 - One with the 7 highest registers (register mask 0xDF80)
16655 This ldm will finally contain between 2 and 7 registers. */
16656 insn_low_registers = insn_all_registers & 0x007F;
16657 insn_high_registers = insn_all_registers & 0xDF80;
16658
16659 /* A spare register may be needed during this veneer to temporarily
16660 handle the base register. This register will be restored with the
16661 last LDM operation.
16662 The usable register may be any general purpose register (that
16663 excludes PC, SP, LR : register mask is 0x1FFF). */
16664 usable_register_mask = 0x1FFF;
16665
16666 /* Generate the stub function. */
16667 if (wback)
16668 {
16669 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
16670 current_stub_contents =
16671 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16672 create_instruction_ldmia
16673 (rn, /*wback=*/1, insn_low_registers));
16674
16675 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
16676 current_stub_contents =
16677 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16678 create_instruction_ldmia
16679 (rn, /*wback=*/1, insn_high_registers));
16680 if (!restore_pc)
16681 {
16682 /* B initial_insn_addr+4. */
16683 current_stub_contents =
16684 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16685 create_instruction_branch_absolute
82188b29 16686 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16687 }
16688 }
16689 else /* if (!wback). */
16690 {
16691 ri = rn;
16692
16693 /* If Rn is not part of the high-register-list, move it there. */
16694 if (!(insn_high_registers & (1 << rn)))
16695 {
16696 /* Choose a Ri in the high-register-list that will be restored. */
16697 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16698
16699 /* MOV Ri, Rn. */
16700 current_stub_contents =
16701 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16702 create_instruction_mov (ri, rn));
16703 }
16704
16705 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
16706 current_stub_contents =
16707 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16708 create_instruction_ldmia
16709 (ri, /*wback=*/1, insn_low_registers));
16710
16711 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
16712 current_stub_contents =
16713 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16714 create_instruction_ldmia
16715 (ri, /*wback=*/0, insn_high_registers));
16716
16717 if (!restore_pc)
16718 {
16719 /* B initial_insn_addr+4. */
16720 current_stub_contents =
16721 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16722 create_instruction_branch_absolute
82188b29 16723 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16724 }
16725 }
16726
16727 /* Fill the remaining of the stub with deterministic contents. */
16728 current_stub_contents =
16729 stm32l4xx_fill_stub_udf (htab, output_bfd,
16730 base_stub_contents, current_stub_contents,
16731 base_stub_contents +
16732 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16733}
16734
16735static void
16736stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
16737 bfd * output_bfd,
16738 const insn32 initial_insn,
16739 const bfd_byte *const initial_insn_addr,
16740 bfd_byte *const base_stub_contents)
16741{
16742 int wback = (initial_insn & 0x00200000) >> 21;
16743 int ri, rn = (initial_insn & 0x000f0000) >> 16;
16744 int insn_all_registers = initial_insn & 0x0000ffff;
16745 int insn_low_registers, insn_high_registers;
16746 int usable_register_mask;
16747 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
16748 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
16749 int nb_registers = popcount (insn_all_registers);
16750 bfd_byte *current_stub_contents = base_stub_contents;
16751
16752 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
16753
16754 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16755 smaller than 8 registers load sequences that do not cause the
16756 hardware issue. */
16757 if (nb_registers <= 8)
16758 {
16759 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
16760 current_stub_contents =
16761 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16762 initial_insn);
16763
16764 /* B initial_insn_addr+4. */
16765 current_stub_contents =
16766 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16767 create_instruction_branch_absolute
82188b29 16768 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16769
16770 /* Fill the remaining of the stub with deterministic contents. */
16771 current_stub_contents =
16772 stm32l4xx_fill_stub_udf (htab, output_bfd,
16773 base_stub_contents, current_stub_contents,
16774 base_stub_contents +
16775 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16776
16777 return;
16778 }
16779
16780 /* - reg_list[13] == 0. */
16781 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
16782
16783 /* - reg_list[14] & reg_list[15] != 1. */
16784 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
16785
16786 /* - if (wback==1) reg_list[rn] == 0. */
16787 BFD_ASSERT (!wback || !restore_rn);
16788
16789 /* - nb_registers > 8. */
16790 BFD_ASSERT (popcount (insn_all_registers) > 8);
16791
16792 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
16793
16794 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
16795 - One with the 7 lowest registers (register mask 0x007F)
16796 This LDM will finally contain between 2 and 7 registers
16797 - One with the 7 highest registers (register mask 0xDF80)
16798 This ldm will finally contain between 2 and 7 registers. */
16799 insn_low_registers = insn_all_registers & 0x007F;
16800 insn_high_registers = insn_all_registers & 0xDF80;
16801
16802 /* A spare register may be needed during this veneer to temporarily
16803 handle the base register. This register will be restored with
16804 the last LDM operation.
16805 The usable register may be any general purpose register (that excludes
16806 PC, SP, LR : register mask is 0x1FFF). */
16807 usable_register_mask = 0x1FFF;
16808
16809 /* Generate the stub function. */
16810 if (!wback && !restore_pc && !restore_rn)
16811 {
16812 /* Choose a Ri in the low-register-list that will be restored. */
16813 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
16814
16815 /* MOV Ri, Rn. */
16816 current_stub_contents =
16817 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16818 create_instruction_mov (ri, rn));
16819
16820 /* LDMDB Ri!, {R-high-register-list}. */
16821 current_stub_contents =
16822 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16823 create_instruction_ldmdb
16824 (ri, /*wback=*/1, insn_high_registers));
16825
16826 /* LDMDB Ri, {R-low-register-list}. */
16827 current_stub_contents =
16828 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16829 create_instruction_ldmdb
16830 (ri, /*wback=*/0, insn_low_registers));
16831
16832 /* B initial_insn_addr+4. */
16833 current_stub_contents =
16834 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16835 create_instruction_branch_absolute
82188b29 16836 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16837 }
16838 else if (wback && !restore_pc && !restore_rn)
16839 {
16840 /* LDMDB Rn!, {R-high-register-list}. */
16841 current_stub_contents =
16842 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16843 create_instruction_ldmdb
16844 (rn, /*wback=*/1, insn_high_registers));
16845
16846 /* LDMDB Rn!, {R-low-register-list}. */
16847 current_stub_contents =
16848 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16849 create_instruction_ldmdb
16850 (rn, /*wback=*/1, insn_low_registers));
16851
16852 /* B initial_insn_addr+4. */
16853 current_stub_contents =
16854 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16855 create_instruction_branch_absolute
82188b29 16856 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16857 }
16858 else if (!wback && restore_pc && !restore_rn)
16859 {
16860 /* Choose a Ri in the high-register-list that will be restored. */
16861 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16862
16863 /* SUB Ri, Rn, #(4*nb_registers). */
16864 current_stub_contents =
16865 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16866 create_instruction_sub (ri, rn, (4 * nb_registers)));
16867
16868 /* LDMIA Ri!, {R-low-register-list}. */
16869 current_stub_contents =
16870 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16871 create_instruction_ldmia
16872 (ri, /*wback=*/1, insn_low_registers));
16873
16874 /* LDMIA Ri, {R-high-register-list}. */
16875 current_stub_contents =
16876 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16877 create_instruction_ldmia
16878 (ri, /*wback=*/0, insn_high_registers));
16879 }
16880 else if (wback && restore_pc && !restore_rn)
16881 {
16882 /* Choose a Ri in the high-register-list that will be restored. */
16883 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16884
16885 /* SUB Rn, Rn, #(4*nb_registers) */
16886 current_stub_contents =
16887 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16888 create_instruction_sub (rn, rn, (4 * nb_registers)));
16889
16890 /* MOV Ri, Rn. */
16891 current_stub_contents =
16892 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16893 create_instruction_mov (ri, rn));
16894
16895 /* LDMIA Ri!, {R-low-register-list}. */
16896 current_stub_contents =
16897 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16898 create_instruction_ldmia
16899 (ri, /*wback=*/1, insn_low_registers));
16900
16901 /* LDMIA Ri, {R-high-register-list}. */
16902 current_stub_contents =
16903 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16904 create_instruction_ldmia
16905 (ri, /*wback=*/0, insn_high_registers));
16906 }
16907 else if (!wback && !restore_pc && restore_rn)
16908 {
16909 ri = rn;
16910 if (!(insn_low_registers & (1 << rn)))
16911 {
16912 /* Choose a Ri in the low-register-list that will be restored. */
16913 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
16914
16915 /* MOV Ri, Rn. */
16916 current_stub_contents =
16917 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16918 create_instruction_mov (ri, rn));
16919 }
16920
16921 /* LDMDB Ri!, {R-high-register-list}. */
16922 current_stub_contents =
16923 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16924 create_instruction_ldmdb
16925 (ri, /*wback=*/1, insn_high_registers));
16926
16927 /* LDMDB Ri, {R-low-register-list}. */
16928 current_stub_contents =
16929 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16930 create_instruction_ldmdb
16931 (ri, /*wback=*/0, insn_low_registers));
16932
16933 /* B initial_insn_addr+4. */
16934 current_stub_contents =
16935 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16936 create_instruction_branch_absolute
82188b29 16937 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16938 }
16939 else if (!wback && restore_pc && restore_rn)
16940 {
16941 ri = rn;
16942 if (!(insn_high_registers & (1 << rn)))
16943 {
16944 /* Choose a Ri in the high-register-list that will be restored. */
16945 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16946 }
16947
16948 /* SUB Ri, Rn, #(4*nb_registers). */
16949 current_stub_contents =
16950 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16951 create_instruction_sub (ri, rn, (4 * nb_registers)));
16952
16953 /* LDMIA Ri!, {R-low-register-list}. */
16954 current_stub_contents =
16955 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16956 create_instruction_ldmia
16957 (ri, /*wback=*/1, insn_low_registers));
16958
16959 /* LDMIA Ri, {R-high-register-list}. */
16960 current_stub_contents =
16961 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16962 create_instruction_ldmia
16963 (ri, /*wback=*/0, insn_high_registers));
16964 }
16965 else if (wback && restore_rn)
16966 {
16967 /* The assembler should not have accepted to encode this. */
16968 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
16969 "undefined behavior.\n");
16970 }
16971
16972 /* Fill the remaining of the stub with deterministic contents. */
16973 current_stub_contents =
16974 stm32l4xx_fill_stub_udf (htab, output_bfd,
16975 base_stub_contents, current_stub_contents,
16976 base_stub_contents +
16977 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16978
16979}
16980
16981static void
16982stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
16983 bfd * output_bfd,
16984 const insn32 initial_insn,
16985 const bfd_byte *const initial_insn_addr,
16986 bfd_byte *const base_stub_contents)
16987{
9239bbd3 16988 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 16989 bfd_byte *current_stub_contents = base_stub_contents;
16990
16991 BFD_ASSERT (is_thumb2_vldm (initial_insn));
16992
16993 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 16994 smaller than 8 words load sequences that do not cause the
a504d23a 16995 hardware issue. */
9239bbd3 16996 if (num_words <= 8)
a504d23a
LA		 16997 {
16998 /* Untouched instruction. */
16999 current_stub_contents =
17000 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17001 initial_insn);
17002
17003 /* B initial_insn_addr+4. */
17004 current_stub_contents =
17005 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17006 create_instruction_branch_absolute
82188b29 17007 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17008 }
17009 else
17010 {
9239bbd3
CM		 17011 bfd_boolean is_dp = /* DP encoding. */
17012 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 17013 bfd_boolean is_ia_nobang = /* (IA without !). */
17014 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
17015 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
17016 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
17017 bfd_boolean is_db_bang = /* (DB with !). */
17018 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 17019 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 17020 /* d = UInt (Vd:D);. */
9239bbd3 17021 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 17022 | (((unsigned int)initial_insn << 9) >> 31);
17023
9239bbd3
CM		 17024 /* Compute the number of 8-words chunks needed to split. */
17025 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 17026 int chunk;
17027
17028 /* The test coverage has been done assuming the following
17029 hypothesis that exactly one of the previous is_ predicates is
17030 true. */
9239bbd3
CM		 17031 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
17032 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 17033
9239bbd3 17034 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 17035 cases, then we emit the adjustments:
17036
17037 vldm rx, {...}
17038 -> vldm rx!, {8_words_or_less} for each needed 8_word
17039 -> sub rx, rx, #size (list)
17040
17041 vldm rx!, {...}
17042 -> vldm rx!, {8_words_or_less} for each needed 8_word
17043 This also handles vpop instruction (when rx is sp)
17044
17045 vldmd rx!, {...}
17046 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 17047 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 17048 {
9239bbd3
CM		 17049 bfd_vma new_insn = 0;
17050
a504d23a
LA		 17051 if (is_ia_nobang || is_ia_bang)
17052 {
9239bbd3
CM		 17053 new_insn = create_instruction_vldmia
17054 (base_reg,
17055 is_dp,
17056 /*wback= . */1,
17057 chunks - (chunk + 1) ?
17058 8 : num_words - chunk * 8,
17059 first_reg + chunk * 8);
a504d23a
LA		 17060 }
17061 else if (is_db_bang)
17062 {
9239bbd3
CM		 17063 new_insn = create_instruction_vldmdb
17064 (base_reg,
17065 is_dp,
17066 chunks - (chunk + 1) ?
17067 8 : num_words - chunk * 8,
17068 first_reg + chunk * 8);
a504d23a 17069 }
9239bbd3
CM		 17070
17071 if (new_insn)
17072 current_stub_contents =
17073 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17074 new_insn);
a504d23a
LA		 17075 }
17076
17077 /* Only this case requires the base register compensation
17078 subtract. */
17079 if (is_ia_nobang)
17080 {
17081 current_stub_contents =
17082 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17083 create_instruction_sub
9239bbd3 17084 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 17085 }
17086
17087 /* B initial_insn_addr+4. */
17088 current_stub_contents =
17089 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17090 create_instruction_branch_absolute
82188b29 17091 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17092 }
17093
17094 /* Fill the remaining of the stub with deterministic contents. */
17095 current_stub_contents =
17096 stm32l4xx_fill_stub_udf (htab, output_bfd,
17097 base_stub_contents, current_stub_contents,
17098 base_stub_contents +
17099 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
17100}
17101
17102static void
17103stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
17104 bfd * output_bfd,
17105 const insn32 wrong_insn,
17106 const bfd_byte *const wrong_insn_addr,
17107 bfd_byte *const stub_contents)
17108{
17109 if (is_thumb2_ldmia (wrong_insn))
17110 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
17111 wrong_insn, wrong_insn_addr,
17112 stub_contents);
17113 else if (is_thumb2_ldmdb (wrong_insn))
17114 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
17115 wrong_insn, wrong_insn_addr,
17116 stub_contents);
17117 else if (is_thumb2_vldm (wrong_insn))
17118 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
17119 wrong_insn, wrong_insn_addr,
17120 stub_contents);
17121}
17122
17123/* End of stm32l4xx work-around. */
17124
17125
491d01d3
YU		 17126static void
17127elf32_arm_add_relocation (bfd *output_bfd, struct bfd_link_info *info,
17128 asection *output_sec, Elf_Internal_Rela *rel)
17129{
17130 BFD_ASSERT (output_sec && rel);
17131 struct bfd_elf_section_reloc_data *output_reldata;
17132 struct elf32_arm_link_hash_table *htab;
17133 struct bfd_elf_section_data *oesd = elf_section_data (output_sec);
17134 Elf_Internal_Shdr *rel_hdr;
17135
17136
17137 if (oesd->rel.hdr)
17138 {
17139 rel_hdr = oesd->rel.hdr;
17140 output_reldata = &(oesd->rel);
17141 }
17142 else if (oesd->rela.hdr)
17143 {
17144 rel_hdr = oesd->rela.hdr;
17145 output_reldata = &(oesd->rela);
17146 }
17147 else
17148 {
17149 abort ();
17150 }
17151
17152 bfd_byte *erel = rel_hdr->contents;
17153 erel += output_reldata->count * rel_hdr->sh_entsize;
17154 htab = elf32_arm_hash_table (info);
17155 SWAP_RELOC_OUT (htab) (output_bfd, rel, erel);
17156 output_reldata->count++;
17157}
17158
e489d0ae
PB		 17159/* Do code byteswapping. Return FALSE afterwards so that the section is
17160 written out as normal. */
17161
17162static bfd_boolean
c7b8f16e 17163elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 17164 struct bfd_link_info *link_info,
17165 asection *sec,
e489d0ae
PB		 17166 bfd_byte *contents)
17167{
48229727 17168 unsigned int mapcount, errcount;
8e3de13a 17169 _arm_elf_section_data *arm_data;
c7b8f16e 17170 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 17171 elf32_arm_section_map *map;
c7b8f16e 17172 elf32_vfp11_erratum_list *errnode;
a504d23a 17173 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 17174 bfd_vma ptr;
17175 bfd_vma end;
c7b8f16e 17176 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 17177 bfd_byte tmp;
48229727 17178 unsigned int i;
57e8b36a 17179
4dfe6ac6
NC		 17180 if (globals == NULL)
17181 return FALSE;
17182
8e3de13a
NC		 17183 /* If this section has not been allocated an _arm_elf_section_data
17184 structure then we cannot record anything. */
17185 arm_data = get_arm_elf_section_data (sec);
17186 if (arm_data == NULL)
17187 return FALSE;
17188
17189 mapcount = arm_data->mapcount;
17190 map = arm_data->map;
c7b8f16e
JB		 17191 errcount = arm_data->erratumcount;
17192
17193 if (errcount != 0)
17194 {
17195 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
17196
17197 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 17198 errnode = errnode->next)
17199 {
17200 bfd_vma target = errnode->vma - offset;
17201
17202 switch (errnode->type)
17203 {
17204 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
17205 {
17206 bfd_vma branch_to_veneer;
17207 /* Original condition code of instruction, plus bit mask for
17208 ARM B instruction. */
17209 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
17210 | 0x0a000000;
c7b8f16e
JB		 17211
17212 /* The instruction is before the label. */
91d6fa6a 17213 target -= 4;
c7b8f16e
JB		 17214
17215 /* Above offset included in -4 below. */
17216 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 17217 - errnode->vma - 4;
c7b8f16e
JB		 17218
17219 if ((signed) branch_to_veneer < -(1 << 25)
17220 || (signed) branch_to_veneer >= (1 << 25))
17221 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
17222 "range"), output_bfd);
17223
99059e56
RM		 17224 insn |= (branch_to_veneer >> 2) & 0xffffff;
17225 contents[endianflip ^ target] = insn & 0xff;
17226 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
17227 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
17228 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
17229 }
17230 break;
c7b8f16e
JB		 17231
17232 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 17233 {
17234 bfd_vma branch_from_veneer;
17235 unsigned int insn;
c7b8f16e 17236
99059e56
RM		 17237 /* Take size of veneer into account. */
17238 branch_from_veneer = errnode->u.v.branch->vma
17239 - errnode->vma - 12;
c7b8f16e
JB		 17240
17241 if ((signed) branch_from_veneer < -(1 << 25)
17242 || (signed) branch_from_veneer >= (1 << 25))
17243 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
17244 "range"), output_bfd);
17245
99059e56
RM		 17246 /* Original instruction. */
17247 insn = errnode->u.v.branch->u.b.vfp_insn;
17248 contents[endianflip ^ target] = insn & 0xff;
17249 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
17250 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
17251 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
17252
17253 /* Branch back to insn after original insn. */
17254 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
17255 contents[endianflip ^ (target + 4)] = insn & 0xff;
17256 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
17257 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
17258 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
17259 }
17260 break;
c7b8f16e 17261
99059e56
RM		 17262 default:
17263 abort ();
17264 }
17265 }
c7b8f16e 17266 }
e489d0ae 17267
a504d23a
LA		 17268 if (arm_data->stm32l4xx_erratumcount != 0)
17269 {
17270 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
17271 stm32l4xx_errnode != 0;
17272 stm32l4xx_errnode = stm32l4xx_errnode->next)
17273 {
17274 bfd_vma target = stm32l4xx_errnode->vma - offset;
17275
17276 switch (stm32l4xx_errnode->type)
17277 {
17278 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
17279 {
17280 unsigned int insn;
17281 bfd_vma branch_to_veneer =
17282 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
17283
17284 if ((signed) branch_to_veneer < -(1 << 24)
17285 || (signed) branch_to_veneer >= (1 << 24))
17286 {
17287 bfd_vma out_of_range =
17288 ((signed) branch_to_veneer < -(1 << 24)) ?
17289 - branch_to_veneer - (1 << 24) :
17290 ((signed) branch_to_veneer >= (1 << 24)) ?
17291 branch_to_veneer - (1 << 24) : 0;
17292
17293 (*_bfd_error_handler)
17294 (_("%B(%#x): error: Cannot create STM32L4XX veneer. "
eee926f2 17295 "Jump out of range by %ld bytes. "
a504d23a
LA		 17296 "Cannot encode branch instruction. "),
17297 output_bfd,
eee926f2 17298 (long) (stm32l4xx_errnode->vma - 4),
a504d23a
LA		 17299 out_of_range);
17300 continue;
17301 }
17302
17303 insn = create_instruction_branch_absolute
82188b29 17304 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 17305
17306 /* The instruction is before the label. */
17307 target -= 4;
17308
17309 put_thumb2_insn (globals, output_bfd,
17310 (bfd_vma) insn, contents + target);
17311 }
17312 break;
17313
17314 case STM32L4XX_ERRATUM_VENEER:
17315 {
82188b29
NC		 17316 bfd_byte * veneer;
17317 bfd_byte * veneer_r;
a504d23a
LA		 17318 unsigned int insn;
17319
82188b29
NC		 17320 veneer = contents + target;
17321 veneer_r = veneer
17322 + stm32l4xx_errnode->u.b.veneer->vma
17323 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 17324
17325 if ((signed) (veneer_r - veneer -
17326 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
17327 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
17328 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
17329 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
17330 || (signed) (veneer_r - veneer) >= (1 << 24))
17331 {
17332 (*_bfd_error_handler) (_("%B: error: Cannot create STM32L4XX "
17333 "veneer."), output_bfd);
17334 continue;
17335 }
17336
17337 /* Original instruction. */
17338 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
17339
17340 stm32l4xx_create_replacing_stub
17341 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
17342 }
17343 break;
17344
17345 default:
17346 abort ();
17347 }
17348 }
17349 }
17350
2468f9c9
PB		 17351 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
17352 {
17353 arm_unwind_table_edit *edit_node
99059e56 17354 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 17355 /* Now, sec->size is the size of the section we will write. The original
99059e56 17356 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 17357 markers) was sec->rawsize. (This isn't the case if we perform no
17358 edits, then rawsize will be zero and we should use size). */
21d799b5 17359 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 17360 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
17361 unsigned int in_index, out_index;
17362 bfd_vma add_to_offsets = 0;
17363
17364 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 17365 {
2468f9c9
PB		 17366 if (edit_node)
17367 {
17368 unsigned int edit_index = edit_node->index;
b38cadfb 17369
2468f9c9 17370 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 17371 {
2468f9c9
PB		 17372 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
17373 contents + in_index * 8, add_to_offsets);
17374 out_index++;
17375 in_index++;
17376 }
17377 else if (in_index == edit_index
17378 || (in_index * 8 >= input_size
17379 && edit_index == UINT_MAX))
99059e56 17380 {
2468f9c9
PB		 17381 switch (edit_node->type)
17382 {
17383 case DELETE_EXIDX_ENTRY:
17384 in_index++;
17385 add_to_offsets += 8;
17386 break;
b38cadfb 17387
2468f9c9
PB		 17388 case INSERT_EXIDX_CANTUNWIND_AT_END:
17389 {
99059e56 17390 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 17391 bfd_vma text_offset = text_sec->output_section->vma
17392 + text_sec->output_offset
17393 + text_sec->size;
17394 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 17395 unsigned long prel31_offset;
2468f9c9
PB		 17396
17397 /* Note: this is meant to be equivalent to an
17398 R_ARM_PREL31 relocation. These synthetic
17399 EXIDX_CANTUNWIND markers are not relocated by the
17400 usual BFD method. */
17401 prel31_offset = (text_offset - exidx_offset)
17402 & 0x7ffffffful;
491d01d3
YU		 17403 if (bfd_link_relocatable (link_info))
17404 {
17405 /* Here relocation for new EXIDX_CANTUNWIND is
17406 created, so there is no need to
17407 adjust offset by hand. */
17408 prel31_offset = text_sec->output_offset
17409 + text_sec->size;
17410
17411 /* New relocation entity. */
17412 asection *text_out = text_sec->output_section;
17413 Elf_Internal_Rela rel;
17414 rel.r_addend = 0;
17415 rel.r_offset = exidx_offset;
17416 rel.r_info = ELF32_R_INFO (text_out->target_index,
17417 R_ARM_PREL31);
17418
17419 elf32_arm_add_relocation (output_bfd, link_info,
17420 sec->output_section,
17421 &rel);
17422 }
2468f9c9
PB		 17423
17424 /* First address we can't unwind. */
17425 bfd_put_32 (output_bfd, prel31_offset,
17426 &edited_contents[out_index * 8]);
17427
17428 /* Code for EXIDX_CANTUNWIND. */
17429 bfd_put_32 (output_bfd, 0x1,
17430 &edited_contents[out_index * 8 + 4]);
17431
17432 out_index++;
17433 add_to_offsets -= 8;
17434 }
17435 break;
17436 }
b38cadfb 17437
2468f9c9
PB		 17438 edit_node = edit_node->next;
17439 }
17440 }
17441 else
17442 {
17443 /* No more edits, copy remaining entries verbatim. */
17444 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
17445 contents + in_index * 8, add_to_offsets);
17446 out_index++;
17447 in_index++;
17448 }
17449 }
17450
17451 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
17452 bfd_set_section_contents (output_bfd, sec->output_section,
17453 edited_contents,
17454 (file_ptr) sec->output_offset, sec->size);
17455
17456 return TRUE;
17457 }
17458
48229727
JB		 17459 /* Fix code to point to Cortex-A8 erratum stubs. */
17460 if (globals->fix_cortex_a8)
17461 {
17462 struct a8_branch_to_stub_data data;
17463
17464 data.writing_section = sec;
17465 data.contents = contents;
17466
a504d23a
LA		 17467 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
17468 & data);
48229727
JB		 17469 }
17470
e489d0ae
PB		 17471 if (mapcount == 0)
17472 return FALSE;
17473
c7b8f16e 17474 if (globals->byteswap_code)
e489d0ae 17475 {
c7b8f16e 17476 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 17477
c7b8f16e
JB		 17478 ptr = map[0].vma;
17479 for (i = 0; i < mapcount; i++)
99059e56
RM		 17480 {
17481 if (i == mapcount - 1)
c7b8f16e 17482 end = sec->size;
99059e56
RM		 17483 else
17484 end = map[i + 1].vma;
e489d0ae 17485
99059e56 17486 switch (map[i].type)
e489d0ae 17487 {
c7b8f16e
JB		 17488 case 'a':
17489 /* Byte swap code words. */
17490 while (ptr + 3 < end)
99059e56
RM		 17491 {
17492 tmp = contents[ptr];
17493 contents[ptr] = contents[ptr + 3];
17494 contents[ptr + 3] = tmp;
17495 tmp = contents[ptr + 1];
17496 contents[ptr + 1] = contents[ptr + 2];
17497 contents[ptr + 2] = tmp;
17498 ptr += 4;
17499 }
c7b8f16e 17500 break;
e489d0ae 17501
c7b8f16e
JB		 17502 case 't':
17503 /* Byte swap code halfwords. */
17504 while (ptr + 1 < end)
99059e56
RM		 17505 {
17506 tmp = contents[ptr];
17507 contents[ptr] = contents[ptr + 1];
17508 contents[ptr + 1] = tmp;
17509 ptr += 2;
17510 }
c7b8f16e
JB		 17511 break;
17512
17513 case 'd':
17514 /* Leave data alone. */
17515 break;
17516 }
99059e56
RM		 17517 ptr = end;
17518 }
e489d0ae 17519 }
8e3de13a 17520
93204d3a 17521 free (map);
47b2e99c 17522 arm_data->mapcount = -1;
c7b8f16e 17523 arm_data->mapsize = 0;
8e3de13a 17524 arm_data->map = NULL;
8e3de13a 17525
e489d0ae
PB		 17526 return FALSE;
17527}
17528
0beaef2b
PB		 17529/* Mangle thumb function symbols as we read them in. */
17530
8384fb8f 17531static bfd_boolean
0beaef2b
PB		 17532elf32_arm_swap_symbol_in (bfd * abfd,
17533 const void *psrc,
17534 const void *pshn,
17535 Elf_Internal_Sym *dst)
17536{
8384fb8f
AM		 17537 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
17538 return FALSE;
0beaef2b
PB		 17539
17540 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 17541 the address. */
63e1a0fc
PB		 17542 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
17543 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 17544 {
63e1a0fc
PB		 17545 if (dst->st_value & 1)
17546 {
17547 dst->st_value &= ~(bfd_vma) 1;
17548 dst->st_target_internal = ST_BRANCH_TO_THUMB;
17549 }
17550 else
17551 dst->st_target_internal = ST_BRANCH_TO_ARM;
35fc36a8
RS		 17552 }
17553 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
17554 {
17555 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
17556 dst->st_target_internal = ST_BRANCH_TO_THUMB;
0beaef2b 17557 }
35fc36a8
RS		 17558 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
17559 dst->st_target_internal = ST_BRANCH_LONG;
17560 else
63e1a0fc 17561 dst->st_target_internal = ST_BRANCH_UNKNOWN;
35fc36a8 17562
8384fb8f 17563 return TRUE;
0beaef2b
PB		 17564}
17565
17566
17567/* Mangle thumb function symbols as we write them out. */
17568
17569static void
17570elf32_arm_swap_symbol_out (bfd *abfd,
17571 const Elf_Internal_Sym *src,
17572 void *cdst,
17573 void *shndx)
17574{
17575 Elf_Internal_Sym newsym;
17576
17577 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
17578 of the address set, as per the new EABI. We do this unconditionally
17579 because objcopy does not set the elf header flags until after
17580 it writes out the symbol table. */
35fc36a8 17581 if (src->st_target_internal == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 17582 {
17583 newsym = *src;
34e77a92
RS		 17584 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
17585 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 17586 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 17587 {
17588 /* Do this only for defined symbols. At link type, the static
17589 linker will simulate the work of dynamic linker of resolving
17590 symbols and will carry over the thumbness of found symbols to
17591 the output symbol table. It's not clear how it happens, but
17592 the thumbness of undefined symbols can well be different at
17593 runtime, and writing '1' for them will be confusing for users
17594 and possibly for dynamic linker itself.
17595 */
17596 newsym.st_value |= 1;
17597 }
906e58ca 17598
0beaef2b
PB		 17599 src = &newsym;
17600 }
17601 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
17602}
17603
b294bdf8
MM		 17604/* Add the PT_ARM_EXIDX program header. */
17605
17606static bfd_boolean
906e58ca 17607elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 17608 struct bfd_link_info *info ATTRIBUTE_UNUSED)
17609{
17610 struct elf_segment_map *m;
17611 asection *sec;
17612
17613 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
17614 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
17615 {
17616 /* If there is already a PT_ARM_EXIDX header, then we do not
17617 want to add another one. This situation arises when running
17618 "strip"; the input binary already has the header. */
12bd6957 17619 m = elf_seg_map (abfd);
b294bdf8
MM		 17620 while (m && m->p_type != PT_ARM_EXIDX)
17621 m = m->next;
17622 if (!m)
17623 {
21d799b5 17624 m = (struct elf_segment_map *)
99059e56 17625 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 17626 if (m == NULL)
17627 return FALSE;
17628 m->p_type = PT_ARM_EXIDX;
17629 m->count = 1;
17630 m->sections[0] = sec;
17631
12bd6957
AM		 17632 m->next = elf_seg_map (abfd);
17633 elf_seg_map (abfd) = m;
b294bdf8
MM		 17634 }
17635 }
17636
17637 return TRUE;
17638}
17639
17640/* We may add a PT_ARM_EXIDX program header. */
17641
17642static int
a6b96beb
AM		 17643elf32_arm_additional_program_headers (bfd *abfd,
17644 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 17645{
17646 asection *sec;
17647
17648 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
17649 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
17650 return 1;
17651 else
17652 return 0;
17653}
17654
34e77a92
RS		 17655/* Hook called by the linker routine which adds symbols from an object
17656 file. */
17657
17658static bfd_boolean
17659elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
17660 Elf_Internal_Sym *sym, const char **namep,
17661 flagword *flagsp, asection **secp, bfd_vma *valp)
17662{
f1885d1e
AM		 17663 if ((ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
17664 || ELF_ST_BIND (sym->st_info) == STB_GNU_UNIQUE)
17665 && (abfd->flags & DYNAMIC) == 0
17666 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
13a2df29 17667 elf_tdata (info->output_bfd)->has_gnu_symbols = elf_gnu_symbol_any;
34e77a92 17668
c792917c
NC		 17669 if (elf32_arm_hash_table (info) == NULL)
17670 return FALSE;
17671
34e77a92
RS		 17672 if (elf32_arm_hash_table (info)->vxworks_p
17673 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
17674 flagsp, secp, valp))
17675 return FALSE;
17676
17677 return TRUE;
17678}
17679
0beaef2b 17680/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 17681const struct elf_size_info elf32_arm_size_info =
17682{
0beaef2b
PB		 17683 sizeof (Elf32_External_Ehdr),
17684 sizeof (Elf32_External_Phdr),
17685 sizeof (Elf32_External_Shdr),
17686 sizeof (Elf32_External_Rel),
17687 sizeof (Elf32_External_Rela),
17688 sizeof (Elf32_External_Sym),
17689 sizeof (Elf32_External_Dyn),
17690 sizeof (Elf_External_Note),
17691 4,
17692 1,
17693 32, 2,
17694 ELFCLASS32, EV_CURRENT,
17695 bfd_elf32_write_out_phdrs,
17696 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 17697 bfd_elf32_checksum_contents,
0beaef2b
PB		 17698 bfd_elf32_write_relocs,
17699 elf32_arm_swap_symbol_in,
17700 elf32_arm_swap_symbol_out,
17701 bfd_elf32_slurp_reloc_table,
17702 bfd_elf32_slurp_symbol_table,
17703 bfd_elf32_swap_dyn_in,
17704 bfd_elf32_swap_dyn_out,
17705 bfd_elf32_swap_reloc_in,
17706 bfd_elf32_swap_reloc_out,
17707 bfd_elf32_swap_reloca_in,
17708 bfd_elf32_swap_reloca_out
17709};
17710
685e70ae
VK		 17711static bfd_vma
17712read_code32 (const bfd *abfd, const bfd_byte *addr)
17713{
17714 /* V7 BE8 code is always little endian. */
17715 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
17716 return bfd_getl32 (addr);
17717
17718 return bfd_get_32 (abfd, addr);
17719}
17720
17721static bfd_vma
17722read_code16 (const bfd *abfd, const bfd_byte *addr)
17723{
17724 /* V7 BE8 code is always little endian. */
17725 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
17726 return bfd_getl16 (addr);
17727
17728 return bfd_get_16 (abfd, addr);
17729}
17730
6a631e86
YG		 17731/* Return size of plt0 entry starting at ADDR
17732 or (bfd_vma) -1 if size can not be determined. */
17733
17734static bfd_vma
17735elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
17736{
17737 bfd_vma first_word;
17738 bfd_vma plt0_size;
17739
685e70ae 17740 first_word = read_code32 (abfd, addr);
6a631e86
YG		 17741
17742 if (first_word == elf32_arm_plt0_entry[0])
17743 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
17744 else if (first_word == elf32_thumb2_plt0_entry[0])
17745 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
17746 else
17747 /* We don't yet handle this PLT format. */
17748 return (bfd_vma) -1;
17749
17750 return plt0_size;
17751}
17752
17753/* Return size of plt entry starting at offset OFFSET
17754 of plt section located at address START
17755 or (bfd_vma) -1 if size can not be determined. */
17756
17757static bfd_vma
17758elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
17759{
17760 bfd_vma first_insn;
17761 bfd_vma plt_size = 0;
17762 const bfd_byte *addr = start + offset;
17763
17764 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 17765 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 17766 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
17767
17768 /* Respect Thumb stub if necessary. */
685e70ae 17769 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 17770 {
17771 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
17772 }
17773
17774 /* Strip immediate from first add. */
685e70ae 17775 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 17776
17777#ifdef FOUR_WORD_PLT
17778 if (first_insn == elf32_arm_plt_entry[0])
17779 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
17780#else
17781 if (first_insn == elf32_arm_plt_entry_long[0])
17782 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
17783 else if (first_insn == elf32_arm_plt_entry_short[0])
17784 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
17785#endif
17786 else
17787 /* We don't yet handle this PLT format. */
17788 return (bfd_vma) -1;
17789
17790 return plt_size;
17791}
17792
17793/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
17794
17795static long
17796elf32_arm_get_synthetic_symtab (bfd *abfd,
17797 long symcount ATTRIBUTE_UNUSED,
17798 asymbol **syms ATTRIBUTE_UNUSED,
17799 long dynsymcount,
17800 asymbol **dynsyms,
17801 asymbol **ret)
17802{
17803 asection *relplt;
17804 asymbol *s;
17805 arelent *p;
17806 long count, i, n;
17807 size_t size;
17808 Elf_Internal_Shdr *hdr;
17809 char *names;
17810 asection *plt;
17811 bfd_vma offset;
17812 bfd_byte *data;
17813
17814 *ret = NULL;
17815
17816 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
17817 return 0;
17818
17819 if (dynsymcount <= 0)
17820 return 0;
17821
17822 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
17823 if (relplt == NULL)
17824 return 0;
17825
17826 hdr = &elf_section_data (relplt)->this_hdr;
17827 if (hdr->sh_link != elf_dynsymtab (abfd)
17828 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
17829 return 0;
17830
17831 plt = bfd_get_section_by_name (abfd, ".plt");
17832 if (plt == NULL)
17833 return 0;
17834
17835 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
17836 return -1;
17837
17838 data = plt->contents;
17839 if (data == NULL)
17840 {
17841 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
17842 return -1;
17843 bfd_cache_section_contents((asection *) plt, data);
17844 }
17845
17846 count = relplt->size / hdr->sh_entsize;
17847 size = count * sizeof (asymbol);
17848 p = relplt->relocation;
17849 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
17850 {
17851 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
17852 if (p->addend != 0)
17853 size += sizeof ("+0x") - 1 + 8;
17854 }
17855
17856 s = *ret = (asymbol *) bfd_malloc (size);
17857 if (s == NULL)
17858 return -1;
17859
17860 offset = elf32_arm_plt0_size (abfd, data);
17861 if (offset == (bfd_vma) -1)
17862 return -1;
17863
17864 names = (char *) (s + count);
17865 p = relplt->relocation;
17866 n = 0;
17867 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
17868 {
17869 size_t len;
17870
17871 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
17872 if (plt_size == (bfd_vma) -1)
17873 break;
17874
17875 *s = **p->sym_ptr_ptr;
17876 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
17877 we are defining a symbol, ensure one of them is set. */
17878 if ((s->flags & BSF_LOCAL) == 0)
17879 s->flags |= BSF_GLOBAL;
17880 s->flags |= BSF_SYNTHETIC;
17881 s->section = plt;
17882 s->value = offset;
17883 s->name = names;
17884 s->udata.p = NULL;
17885 len = strlen ((*p->sym_ptr_ptr)->name);
17886 memcpy (names, (*p->sym_ptr_ptr)->name, len);
17887 names += len;
17888 if (p->addend != 0)
17889 {
17890 char buf[30], *a;
17891
17892 memcpy (names, "+0x", sizeof ("+0x") - 1);
17893 names += sizeof ("+0x") - 1;
17894 bfd_sprintf_vma (abfd, buf, p->addend);
17895 for (a = buf; *a == '0'; ++a)
17896 ;
17897 len = strlen (a);
17898 memcpy (names, a, len);
17899 names += len;
17900 }
17901 memcpy (names, "@plt", sizeof ("@plt"));
17902 names += sizeof ("@plt");
17903 ++s, ++n;
17904 offset += plt_size;
17905 }
17906
17907 return n;
17908}
17909
ac4c9b04
MG		 17910static bfd_boolean
17911elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
17912{
17913 if (hdr->sh_flags & SHF_ARM_NOREAD)
17914 *flags |= SEC_ELF_NOREAD;
17915 return TRUE;
17916}
17917
17918static flagword
17919elf32_arm_lookup_section_flags (char *flag_name)
17920{
17921 if (!strcmp (flag_name, "SHF_ARM_NOREAD"))
17922 return SHF_ARM_NOREAD;
17923
17924 return SEC_NO_FLAGS;
17925}
17926
491d01d3
YU		 17927static unsigned int
17928elf32_arm_count_additional_relocs (asection *sec)
17929{
17930 struct _arm_elf_section_data *arm_data;
17931 arm_data = get_arm_elf_section_data (sec);
17932 return arm_data->additional_reloc_count;
17933}
17934
5522f910
NC		 17935/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
17936 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
17937 FALSE otherwise. ISECTION is the best guess matching section from the
17938 input bfd IBFD, but it might be NULL. */
17939
17940static bfd_boolean
17941elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
17942 bfd *obfd ATTRIBUTE_UNUSED,
17943 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
17944 Elf_Internal_Shdr *osection)
17945{
17946 switch (osection->sh_type)
17947 {
17948 case SHT_ARM_EXIDX:
17949 {
17950 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
17951 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
17952 unsigned i = 0;
17953
17954 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
17955 osection->sh_info = 0;
17956
17957 /* The sh_link field must be set to the text section associated with
17958 this index section. Unfortunately the ARM EHABI does not specify
17959 exactly how to determine this association. Our caller does try
17960 to match up OSECTION with its corresponding input section however
17961 so that is a good first guess. */
17962 if (isection != NULL
17963 && osection->bfd_section != NULL
17964 && isection->bfd_section != NULL
17965 && isection->bfd_section->output_section != NULL
17966 && isection->bfd_section->output_section == osection->bfd_section
17967 && iheaders != NULL
17968 && isection->sh_link > 0
17969 && isection->sh_link < elf_numsections (ibfd)
17970 && iheaders[isection->sh_link]->bfd_section != NULL
17971 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
17972 )
17973 {
17974 for (i = elf_numsections (obfd); i-- > 0;)
17975 if (oheaders[i]->bfd_section
17976 == iheaders[isection->sh_link]->bfd_section->output_section)
17977 break;
17978 }
17979
17980 if (i == 0)
17981 {
17982 /* Failing that we have to find a matching section ourselves. If
17983 we had the output section name available we could compare that
17984 with input section names. Unfortunately we don't. So instead
17985 we use a simple heuristic and look for the nearest executable
17986 section before this one. */
17987 for (i = elf_numsections (obfd); i-- > 0;)
17988 if (oheaders[i] == osection)
17989 break;
17990 if (i == 0)
17991 break;
17992
17993 while (i-- > 0)
17994 if (oheaders[i]->sh_type == SHT_PROGBITS
17995 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
17996 == (SHF_ALLOC | SHF_EXECINSTR))
17997 break;
17998 }
17999
18000 if (i)
18001 {
18002 osection->sh_link = i;
18003 /* If the text section was part of a group
18004 then the index section should be too. */
18005 if (oheaders[i]->sh_flags & SHF_GROUP)
18006 osection->sh_flags |= SHF_GROUP;
18007 return TRUE;
18008 }
18009 }
18010 break;
18011
18012 case SHT_ARM_PREEMPTMAP:
18013 osection->sh_flags = SHF_ALLOC;
18014 break;
18015
18016 case SHT_ARM_ATTRIBUTES:
18017 case SHT_ARM_DEBUGOVERLAY:
18018 case SHT_ARM_OVERLAYSECTION:
18019 default:
18020 break;
18021 }
18022
18023 return FALSE;
18024}
18025
18026#undef elf_backend_copy_special_section_fields
18027#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
18028
252b5132 18029#define ELF_ARCH bfd_arch_arm
ae95ffa6 18030#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 18031#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 18032#ifdef __QNXTARGET__
18033#define ELF_MAXPAGESIZE 0x1000
18034#else
7572ca89 18035#define ELF_MAXPAGESIZE 0x10000
d0facd1b 18036#endif
b1342370 18037#define ELF_MINPAGESIZE 0x1000
24718e3b 18038#define ELF_COMMONPAGESIZE 0x1000
252b5132 18039
ba93b8ac
DJ		 18040#define bfd_elf32_mkobject elf32_arm_mkobject
18041
99e4ae17
AJ		 18042#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
18043#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 18044#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
18045#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
18046#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 18047#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 18048#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
252b5132 18049#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
4ab527b0 18050#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 18051#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 18052#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 18053#define bfd_elf32_bfd_final_link elf32_arm_final_link
6a631e86 18054#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132
RH		 18055
18056#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
18057#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 18058#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
252b5132
RH		 18059#define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
18060#define elf_backend_check_relocs elf32_arm_check_relocs
dc810e39 18061#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 18062#define elf_backend_write_section elf32_arm_write_section
252b5132 18063#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
5e681ec4 18064#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 18065#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
18066#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
18067#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 18068#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 18069#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 18070#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 18071#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 18072#define elf_backend_object_p elf32_arm_object_p
40a18ebd
NC		 18073#define elf_backend_fake_sections elf32_arm_fake_sections
18074#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
e16bb312 18075#define elf_backend_final_write_processing elf32_arm_final_write_processing
5e681ec4 18076#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 18077#define elf_backend_size_info elf32_arm_size_info
b294bdf8 18078#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
906e58ca
NC		 18079#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
18080#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
18081#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 18082#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 18083#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
906e58ca
NC		 18084
18085#define elf_backend_can_refcount 1
18086#define elf_backend_can_gc_sections 1
18087#define elf_backend_plt_readonly 1
18088#define elf_backend_want_got_plt 1
18089#define elf_backend_want_plt_sym 0
18090#define elf_backend_may_use_rel_p 1
18091#define elf_backend_may_use_rela_p 0
4e7fd91e 18092#define elf_backend_default_use_rela_p 0
252b5132 18093
04f7c78d 18094#define elf_backend_got_header_size 12
b68a20d6 18095#define elf_backend_extern_protected_data 1
04f7c78d 18096
906e58ca
NC		 18097#undef elf_backend_obj_attrs_vendor
18098#define elf_backend_obj_attrs_vendor "aeabi"
18099#undef elf_backend_obj_attrs_section
18100#define elf_backend_obj_attrs_section ".ARM.attributes"
18101#undef elf_backend_obj_attrs_arg_type
18102#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
18103#undef elf_backend_obj_attrs_section_type
104d59d1 18104#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb
NC		 18105#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
18106#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 18107
ac4c9b04
MG		 18108#undef elf_backend_section_flags
18109#define elf_backend_section_flags elf32_arm_section_flags
18110#undef elf_backend_lookup_section_flags_hook
18111#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
18112
252b5132 18113#include "elf32-target.h"
7f266840 18114
b38cadfb
NC		 18115/* Native Client targets. */
18116
18117#undef TARGET_LITTLE_SYM
6d00b590 18118#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 18119#undef TARGET_LITTLE_NAME
18120#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
18121#undef TARGET_BIG_SYM
6d00b590 18122#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 18123#undef TARGET_BIG_NAME
18124#define TARGET_BIG_NAME "elf32-bigarm-nacl"
18125
18126/* Like elf32_arm_link_hash_table_create -- but overrides
18127 appropriately for NaCl. */
18128
18129static struct bfd_link_hash_table *
18130elf32_arm_nacl_link_hash_table_create (bfd *abfd)
18131{
18132 struct bfd_link_hash_table *ret;
18133
18134 ret = elf32_arm_link_hash_table_create (abfd);
18135 if (ret)
18136 {
18137 struct elf32_arm_link_hash_table *htab
18138 = (struct elf32_arm_link_hash_table *) ret;
18139
18140 htab->nacl_p = 1;
18141
18142 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
18143 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
18144 }
18145 return ret;
18146}
18147
18148/* Since NaCl doesn't use the ARM-specific unwind format, we don't
18149 really need to use elf32_arm_modify_segment_map. But we do it
18150 anyway just to reduce gratuitous differences with the stock ARM backend. */
18151
18152static bfd_boolean
18153elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
18154{
18155 return (elf32_arm_modify_segment_map (abfd, info)
18156 && nacl_modify_segment_map (abfd, info));
18157}
18158
887badb3
RM		 18159static void
18160elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
18161{
18162 elf32_arm_final_write_processing (abfd, linker);
18163 nacl_final_write_processing (abfd, linker);
18164}
18165
6a631e86
YG		 18166static bfd_vma
18167elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
18168 const arelent *rel ATTRIBUTE_UNUSED)
18169{
18170 return plt->vma
18171 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
18172 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
18173}
887badb3 18174
b38cadfb 18175#undef elf32_bed
6a631e86 18176#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 18177#undef bfd_elf32_bfd_link_hash_table_create
18178#define bfd_elf32_bfd_link_hash_table_create \
18179 elf32_arm_nacl_link_hash_table_create
18180#undef elf_backend_plt_alignment
6a631e86 18181#define elf_backend_plt_alignment 4
b38cadfb
NC		 18182#undef elf_backend_modify_segment_map
18183#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
18184#undef elf_backend_modify_program_headers
18185#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 18186#undef elf_backend_final_write_processing
18187#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 18188#undef bfd_elf32_get_synthetic_symtab
18189#undef elf_backend_plt_sym_val
18190#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 18191#undef elf_backend_copy_special_section_fields
b38cadfb 18192
887badb3
RM		 18193#undef ELF_MINPAGESIZE
18194#undef ELF_COMMONPAGESIZE
18195
b38cadfb
NC		 18196
18197#include "elf32-target.h"
18198
18199/* Reset to defaults. */
18200#undef elf_backend_plt_alignment
18201#undef elf_backend_modify_segment_map
18202#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
18203#undef elf_backend_modify_program_headers
887badb3
RM		 18204#undef elf_backend_final_write_processing
18205#define elf_backend_final_write_processing elf32_arm_final_write_processing
18206#undef ELF_MINPAGESIZE
18207#define ELF_MINPAGESIZE 0x1000
18208#undef ELF_COMMONPAGESIZE
18209#define ELF_COMMONPAGESIZE 0x1000
18210
b38cadfb 18211
906e58ca 18212/* VxWorks Targets. */
4e7fd91e 18213
906e58ca 18214#undef TARGET_LITTLE_SYM
6d00b590 18215#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
906e58ca 18216#undef TARGET_LITTLE_NAME
4e7fd91e 18217#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
906e58ca 18218#undef TARGET_BIG_SYM
6d00b590 18219#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
906e58ca 18220#undef TARGET_BIG_NAME
4e7fd91e
PB		 18221#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
18222
18223/* Like elf32_arm_link_hash_table_create -- but overrides
18224 appropriately for VxWorks. */
906e58ca 18225
4e7fd91e
PB		 18226static struct bfd_link_hash_table *
18227elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
18228{
18229 struct bfd_link_hash_table *ret;
18230
18231 ret = elf32_arm_link_hash_table_create (abfd);
18232 if (ret)
18233 {
18234 struct elf32_arm_link_hash_table *htab
00a97672 18235 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 18236 htab->use_rel = 0;
00a97672 18237 htab->vxworks_p = 1;
4e7fd91e
PB		 18238 }
18239 return ret;
906e58ca 18240}
4e7fd91e 18241
00a97672
RS		 18242static void
18243elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
18244{
18245 elf32_arm_final_write_processing (abfd, linker);
18246 elf_vxworks_final_write_processing (abfd, linker);
18247}
18248
906e58ca 18249#undef elf32_bed
4e7fd91e
PB		 18250#define elf32_bed elf32_arm_vxworks_bed
18251
906e58ca
NC		 18252#undef bfd_elf32_bfd_link_hash_table_create
18253#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 18254#undef elf_backend_final_write_processing
18255#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
18256#undef elf_backend_emit_relocs
18257#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 18258
906e58ca 18259#undef elf_backend_may_use_rel_p
00a97672 18260#define elf_backend_may_use_rel_p 0
906e58ca 18261#undef elf_backend_may_use_rela_p
00a97672 18262#define elf_backend_may_use_rela_p 1
906e58ca 18263#undef elf_backend_default_use_rela_p
00a97672 18264#define elf_backend_default_use_rela_p 1
906e58ca 18265#undef elf_backend_want_plt_sym
00a97672 18266#define elf_backend_want_plt_sym 1
906e58ca 18267#undef ELF_MAXPAGESIZE
00a97672 18268#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 18269
18270#include "elf32-target.h"
18271
18272
21d799b5
NC		 18273/* Merge backend specific data from an object file to the output
18274 object file when linking. */
18275
18276static bfd_boolean
18277elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
18278{
18279 flagword out_flags;
18280 flagword in_flags;
18281 bfd_boolean flags_compatible = TRUE;
18282 asection *sec;
18283
cc643b88 18284 /* Check if we have the same endianness. */
21d799b5
NC		 18285 if (! _bfd_generic_verify_endian_match (ibfd, obfd))
18286 return FALSE;
18287
18288 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
18289 return TRUE;
18290
18291 if (!elf32_arm_merge_eabi_attributes (ibfd, obfd))
18292 return FALSE;
18293
18294 /* The input BFD must have had its flags initialised. */
18295 /* The following seems bogus to me -- The flags are initialized in
18296 the assembler but I don't think an elf_flags_init field is
18297 written into the object. */
18298 /* BFD_ASSERT (elf_flags_init (ibfd)); */
18299
18300 in_flags = elf_elfheader (ibfd)->e_flags;
18301 out_flags = elf_elfheader (obfd)->e_flags;
18302
18303 /* In theory there is no reason why we couldn't handle this. However
18304 in practice it isn't even close to working and there is no real
18305 reason to want it. */
18306 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
18307 && !(ibfd->flags & DYNAMIC)
18308 && (in_flags & EF_ARM_BE8))
18309 {
18310 _bfd_error_handler (_("error: %B is already in final BE8 format"),
18311 ibfd);
18312 return FALSE;
18313 }
18314
18315 if (!elf_flags_init (obfd))
18316 {
18317 /* If the input is the default architecture and had the default
18318 flags then do not bother setting the flags for the output
18319 architecture, instead allow future merges to do this. If no
18320 future merges ever set these flags then they will retain their
99059e56
RM		 18321 uninitialised values, which surprise surprise, correspond
18322 to the default values. */
21d799b5
NC		 18323 if (bfd_get_arch_info (ibfd)->the_default
18324 && elf_elfheader (ibfd)->e_flags == 0)
18325 return TRUE;
18326
18327 elf_flags_init (obfd) = TRUE;
18328 elf_elfheader (obfd)->e_flags = in_flags;
18329
18330 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
18331 && bfd_get_arch_info (obfd)->the_default)
18332 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
18333
18334 return TRUE;
18335 }
18336
18337 /* Determine what should happen if the input ARM architecture
18338 does not match the output ARM architecture. */
18339 if (! bfd_arm_merge_machines (ibfd, obfd))
18340 return FALSE;
18341
18342 /* Identical flags must be compatible. */
18343 if (in_flags == out_flags)
18344 return TRUE;
18345
18346 /* Check to see if the input BFD actually contains any sections. If
18347 not, its flags may not have been initialised either, but it
18348 cannot actually cause any incompatiblity. Do not short-circuit
18349 dynamic objects; their section list may be emptied by
18350 elf_link_add_object_symbols.
18351
18352 Also check to see if there are no code sections in the input.
18353 In this case there is no need to check for code specific flags.
18354 XXX - do we need to worry about floating-point format compatability
18355 in data sections ? */
18356 if (!(ibfd->flags & DYNAMIC))
18357 {
18358 bfd_boolean null_input_bfd = TRUE;
18359 bfd_boolean only_data_sections = TRUE;
18360
18361 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
18362 {
18363 /* Ignore synthetic glue sections. */
18364 if (strcmp (sec->name, ".glue_7")
18365 && strcmp (sec->name, ".glue_7t"))
18366 {
18367 if ((bfd_get_section_flags (ibfd, sec)
18368 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
18369 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 18370 only_data_sections = FALSE;
21d799b5
NC		 18371
18372 null_input_bfd = FALSE;
18373 break;
18374 }
18375 }
18376
18377 if (null_input_bfd || only_data_sections)
18378 return TRUE;
18379 }
18380
18381 /* Complain about various flag mismatches. */
18382 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
18383 EF_ARM_EABI_VERSION (out_flags)))
18384 {
18385 _bfd_error_handler
18386 (_("error: Source object %B has EABI version %d, but target %B has EABI version %d"),
18387 ibfd, obfd,
18388 (in_flags & EF_ARM_EABIMASK) >> 24,
18389 (out_flags & EF_ARM_EABIMASK) >> 24);
18390 return FALSE;
18391 }
18392
18393 /* Not sure what needs to be checked for EABI versions >= 1. */
18394 /* VxWorks libraries do not use these flags. */
18395 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
18396 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
18397 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
18398 {
18399 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
18400 {
18401 _bfd_error_handler
18402 (_("error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"),
18403 ibfd, obfd,
18404 in_flags & EF_ARM_APCS_26 ? 26 : 32,
18405 out_flags & EF_ARM_APCS_26 ? 26 : 32);
18406 flags_compatible = FALSE;
18407 }
18408
18409 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
18410 {
18411 if (in_flags & EF_ARM_APCS_FLOAT)
18412 _bfd_error_handler
18413 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
18414 ibfd, obfd);
18415 else
18416 _bfd_error_handler
18417 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
18418 ibfd, obfd);
18419
18420 flags_compatible = FALSE;
18421 }
18422
18423 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
18424 {
18425 if (in_flags & EF_ARM_VFP_FLOAT)
18426 _bfd_error_handler
18427 (_("error: %B uses VFP instructions, whereas %B does not"),
18428 ibfd, obfd);
18429 else
18430 _bfd_error_handler
18431 (_("error: %B uses FPA instructions, whereas %B does not"),
18432 ibfd, obfd);
18433
18434 flags_compatible = FALSE;
18435 }
18436
18437 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
18438 {
18439 if (in_flags & EF_ARM_MAVERICK_FLOAT)
18440 _bfd_error_handler
18441 (_("error: %B uses Maverick instructions, whereas %B does not"),
18442 ibfd, obfd);
18443 else
18444 _bfd_error_handler
18445 (_("error: %B does not use Maverick instructions, whereas %B does"),
18446 ibfd, obfd);
18447
18448 flags_compatible = FALSE;
18449 }
18450
18451#ifdef EF_ARM_SOFT_FLOAT
18452 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
18453 {
18454 /* We can allow interworking between code that is VFP format
18455 layout, and uses either soft float or integer regs for
18456 passing floating point arguments and results. We already
18457 know that the APCS_FLOAT flags match; similarly for VFP
18458 flags. */
18459 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
18460 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
18461 {
18462 if (in_flags & EF_ARM_SOFT_FLOAT)
18463 _bfd_error_handler
18464 (_("error: %B uses software FP, whereas %B uses hardware FP"),
18465 ibfd, obfd);
18466 else
18467 _bfd_error_handler
18468 (_("error: %B uses hardware FP, whereas %B uses software FP"),
18469 ibfd, obfd);
18470
18471 flags_compatible = FALSE;
18472 }
18473 }
18474#endif
18475
18476 /* Interworking mismatch is only a warning. */
18477 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
18478 {
18479 if (in_flags & EF_ARM_INTERWORK)
18480 {
18481 _bfd_error_handler
18482 (_("Warning: %B supports interworking, whereas %B does not"),
18483 ibfd, obfd);
18484 }
18485 else
18486 {
18487 _bfd_error_handler
18488 (_("Warning: %B does not support interworking, whereas %B does"),
18489 ibfd, obfd);
18490 }
18491 }
18492 }
18493
18494 return flags_compatible;
18495}
18496
18497
906e58ca 18498/* Symbian OS Targets. */
7f266840 18499
906e58ca 18500#undef TARGET_LITTLE_SYM
6d00b590 18501#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
906e58ca 18502#undef TARGET_LITTLE_NAME
7f266840 18503#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
906e58ca 18504#undef TARGET_BIG_SYM
6d00b590 18505#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
906e58ca 18506#undef TARGET_BIG_NAME
7f266840
DJ		 18507#define TARGET_BIG_NAME "elf32-bigarm-symbian"
18508
18509/* Like elf32_arm_link_hash_table_create -- but overrides
18510 appropriately for Symbian OS. */
906e58ca 18511
7f266840
DJ		 18512static struct bfd_link_hash_table *
18513elf32_arm_symbian_link_hash_table_create (bfd *abfd)
18514{
18515 struct bfd_link_hash_table *ret;
18516
18517 ret = elf32_arm_link_hash_table_create (abfd);
18518 if (ret)
18519 {
18520 struct elf32_arm_link_hash_table *htab
18521 = (struct elf32_arm_link_hash_table *)ret;
18522 /* There is no PLT header for Symbian OS. */
18523 htab->plt_header_size = 0;
95720a86
DJ		 18524 /* The PLT entries are each one instruction and one word. */
18525 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 18526 htab->symbian_p = 1;
33bfe774
JB		 18527 /* Symbian uses armv5t or above, so use_blx is always true. */
18528 htab->use_blx = 1;
67687978 18529 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 18530 }
18531 return ret;
906e58ca 18532}
7f266840 18533
b35d266b 18534static const struct bfd_elf_special_section
551b43fd 18535elf32_arm_symbian_special_sections[] =
7f266840 18536{
5cd3778d
MM		 18537 /* In a BPABI executable, the dynamic linking sections do not go in
18538 the loadable read-only segment. The post-linker may wish to
18539 refer to these sections, but they are not part of the final
18540 program image. */
0112cd26
NC		 18541 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
18542 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
18543 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
18544 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
18545 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 18546 /* These sections do not need to be writable as the SymbianOS
18547 postlinker will arrange things so that no dynamic relocation is
18548 required. */
0112cd26
NC		 18549 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
18550 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
18551 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
18552 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 18553};
18554
c3c76620 18555static void
906e58ca 18556elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 18557 struct bfd_link_info *link_info)
c3c76620
MM		 18558{
18559 /* BPABI objects are never loaded directly by an OS kernel; they are
18560 processed by a postlinker first, into an OS-specific format. If
18561 the D_PAGED bit is set on the file, BFD will align segments on
18562 page boundaries, so that an OS can directly map the file. With
18563 BPABI objects, that just results in wasted space. In addition,
18564 because we clear the D_PAGED bit, map_sections_to_segments will
18565 recognize that the program headers should not be mapped into any
18566 loadable segment. */
18567 abfd->flags &= ~D_PAGED;
906e58ca 18568 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 18569}
7f266840
DJ		 18570
18571static bfd_boolean
906e58ca 18572elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 18573 struct bfd_link_info *info)
7f266840
DJ		 18574{
18575 struct elf_segment_map *m;
18576 asection *dynsec;
18577
7f266840
DJ		 18578 /* BPABI shared libraries and executables should have a PT_DYNAMIC
18579 segment. However, because the .dynamic section is not marked
18580 with SEC_LOAD, the generic ELF code will not create such a
18581 segment. */
18582 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
18583 if (dynsec)
18584 {
12bd6957 18585 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 18586 if (m->p_type == PT_DYNAMIC)
18587 break;
18588
18589 if (m == NULL)
18590 {
18591 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 18592 m->next = elf_seg_map (abfd);
18593 elf_seg_map (abfd) = m;
8ded5a0f 18594 }
7f266840
DJ		 18595 }
18596
b294bdf8
MM		 18597 /* Also call the generic arm routine. */
18598 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 18599}
18600
95720a86
DJ		 18601/* Return address for Ith PLT stub in section PLT, for relocation REL
18602 or (bfd_vma) -1 if it should not be included. */
18603
18604static bfd_vma
18605elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
18606 const arelent *rel ATTRIBUTE_UNUSED)
18607{
18608 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
18609}
18610
8029a119 18611#undef elf32_bed
7f266840
DJ		 18612#define elf32_bed elf32_arm_symbian_bed
18613
18614/* The dynamic sections are not allocated on SymbianOS; the postlinker
18615 will process them and then discard them. */
906e58ca 18616#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 18617#define ELF_DYNAMIC_SEC_FLAGS \
18618 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
18619
00a97672 18620#undef elf_backend_emit_relocs
c3c76620 18621
906e58ca
NC		 18622#undef bfd_elf32_bfd_link_hash_table_create
18623#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
18624#undef elf_backend_special_sections
18625#define elf_backend_special_sections elf32_arm_symbian_special_sections
18626#undef elf_backend_begin_write_processing
18627#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
18628#undef elf_backend_final_write_processing
18629#define elf_backend_final_write_processing elf32_arm_final_write_processing
18630
18631#undef elf_backend_modify_segment_map
7f266840
DJ		 18632#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
18633
18634/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 18635#undef elf_backend_got_header_size
7f266840
DJ		 18636#define elf_backend_got_header_size 0
18637
18638/* Similarly, there is no .got.plt section. */
906e58ca 18639#undef elf_backend_want_got_plt
7f266840
DJ		 18640#define elf_backend_want_got_plt 0
18641
906e58ca 18642#undef elf_backend_plt_sym_val
95720a86
DJ		 18643#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
18644
906e58ca 18645#undef elf_backend_may_use_rel_p
00a97672 18646#define elf_backend_may_use_rel_p 1
906e58ca 18647#undef elf_backend_may_use_rela_p
00a97672 18648#define elf_backend_may_use_rela_p 0
906e58ca 18649#undef elf_backend_default_use_rela_p
00a97672 18650#define elf_backend_default_use_rela_p 0
906e58ca 18651#undef elf_backend_want_plt_sym
00a97672 18652#define elf_backend_want_plt_sym 0
906e58ca 18653#undef ELF_MAXPAGESIZE
00a97672 18654#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 18655
7f266840 18656#include "elf32-target.h"
GDB Binutils - Deliverables
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