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[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
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252b5132 1/* 32-bit ELF support for ARM
6f2750fe 2 Copyright (C) 1998-2016 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
7f266840
DJ		 59#define elf_info_to_howto 0
60#define elf_info_to_howto_rel elf32_arm_info_to_howto
61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
240 HOWTO (R_ARM_THM_PC8, /* type */
241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
99059e56
RM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
99059e56
RM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
99059e56
RM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
99059e56
RM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
99059e56
RM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
99059e56
RM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
99059e56
RM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
99059e56
RM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
99059e56
RM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
446 TRUE, /* pc_relative */
447 0, /* bitpos */
448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
99059e56
RM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
460 FALSE, /* pc_relative */
461 0, /* bitpos */
462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
99059e56
RM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
474 TRUE, /* pc_relative */
475 0, /* bitpos */
476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
909 HOWTO (R_ARM_ALU_PC_G0, /* type */
910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
917 "R_ARM_ALU_PC_G0", /* name */
918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
937 HOWTO (R_ARM_ALU_PC_G1, /* type */
938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
945 "R_ARM_ALU_PC_G1", /* name */
946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
951 HOWTO (R_ARM_ALU_PC_G2, /* type */
952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
959 "R_ARM_ALU_PC_G2", /* name */
960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
965 HOWTO (R_ARM_LDR_PC_G1, /* type */
966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
973 "R_ARM_LDR_PC_G1", /* name */
974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
979 HOWTO (R_ARM_LDR_PC_G2, /* type */
980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
987 "R_ARM_LDR_PC_G2", /* name */
988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
1001 "R_ARM_LDRS_PC_G0", /* name */
1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
1015 "R_ARM_LDRS_PC_G1", /* name */
1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
1029 "R_ARM_LDRS_PC_G2", /* name */
1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
1043 "R_ARM_LDC_PC_G0", /* name */
1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
1057 "R_ARM_LDC_PC_G1", /* name */
1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
1071 "R_ARM_LDC_PC_G2", /* name */
1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
1085 "R_ARM_ALU_SB_G0_NC", /* name */
1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
1099 "R_ARM_ALU_SB_G0", /* name */
1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
1113 "R_ARM_ALU_SB_G1_NC", /* name */
1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
1127 "R_ARM_ALU_SB_G1", /* name */
1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
1141 "R_ARM_ALU_SB_G2", /* name */
1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
1155 "R_ARM_LDR_SB_G0", /* name */
1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
1169 "R_ARM_LDR_SB_G1", /* name */
1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
1183 "R_ARM_LDR_SB_G2", /* name */
1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
1197 "R_ARM_LDRS_SB_G0", /* name */
1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
1211 "R_ARM_LDRS_SB_G1", /* name */
1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
1225 "R_ARM_LDRS_SB_G2", /* name */
1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
1239 "R_ARM_LDC_SB_G0", /* name */
1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
1253 "R_ARM_LDC_SB_G1", /* name */
1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
1267 "R_ARM_LDC_SB_G2", /* name */
1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
1486
1487 /* GNU extension to record C++ vtable member usage */
1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
99059e56
RM		 1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
1494 complain_overflow_dont, /* complain_on_overflow */
1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
99059e56
RM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
1509 complain_overflow_dont, /* complain_on_overflow */
1510 NULL, /* special_function */
1511 "R_ARM_GNU_VTINHERIT", /* name */
1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
99059e56
RM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
99059e56
RM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
99059e56
RM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
99059e56
RM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
99059e56
RM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
1608 complain_overflow_bitfield,/* complain_on_overflow */
75c11999 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92
RS		 1748/* 160 onwards: */
1749static reloc_howto_type elf32_arm_howto_table_2[1] =
1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
99059e56
RM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
1763 FALSE) /* pcrel_offset */
34e77a92 1764};
c19d1205 1765
34e77a92
RS		 1766/* 249-255 extended, currently unused, relocations: */
1767static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1768{
1769 HOWTO (R_ARM_RREL32, /* type */
1770 0, /* rightshift */
1771 0, /* size (0 = byte, 1 = short, 2 = long) */
1772 0, /* bitsize */
1773 FALSE, /* pc_relative */
1774 0, /* bitpos */
1775 complain_overflow_dont,/* complain_on_overflow */
1776 bfd_elf_generic_reloc, /* special_function */
1777 "R_ARM_RREL32", /* name */
1778 FALSE, /* partial_inplace */
1779 0, /* src_mask */
1780 0, /* dst_mask */
1781 FALSE), /* pcrel_offset */
1782
1783 HOWTO (R_ARM_RABS32, /* type */
1784 0, /* rightshift */
1785 0, /* size (0 = byte, 1 = short, 2 = long) */
1786 0, /* bitsize */
1787 FALSE, /* pc_relative */
1788 0, /* bitpos */
1789 complain_overflow_dont,/* complain_on_overflow */
1790 bfd_elf_generic_reloc, /* special_function */
1791 "R_ARM_RABS32", /* name */
1792 FALSE, /* partial_inplace */
1793 0, /* src_mask */
1794 0, /* dst_mask */
1795 FALSE), /* pcrel_offset */
1796
1797 HOWTO (R_ARM_RPC24, /* type */
1798 0, /* rightshift */
1799 0, /* size (0 = byte, 1 = short, 2 = long) */
1800 0, /* bitsize */
1801 FALSE, /* pc_relative */
1802 0, /* bitpos */
1803 complain_overflow_dont,/* complain_on_overflow */
1804 bfd_elf_generic_reloc, /* special_function */
1805 "R_ARM_RPC24", /* name */
1806 FALSE, /* partial_inplace */
1807 0, /* src_mask */
1808 0, /* dst_mask */
1809 FALSE), /* pcrel_offset */
1810
1811 HOWTO (R_ARM_RBASE, /* type */
1812 0, /* rightshift */
1813 0, /* size (0 = byte, 1 = short, 2 = long) */
1814 0, /* bitsize */
1815 FALSE, /* pc_relative */
1816 0, /* bitpos */
1817 complain_overflow_dont,/* complain_on_overflow */
1818 bfd_elf_generic_reloc, /* special_function */
1819 "R_ARM_RBASE", /* name */
1820 FALSE, /* partial_inplace */
1821 0, /* src_mask */
1822 0, /* dst_mask */
1823 FALSE) /* pcrel_offset */
1824};
1825
1826static reloc_howto_type *
1827elf32_arm_howto_from_type (unsigned int r_type)
1828{
906e58ca 1829 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1830 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1831
34e77a92
RS		 1832 if (r_type == R_ARM_IRELATIVE)
1833 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1834
c19d1205 1835 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1836 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1837 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1838
c19d1205 1839 return NULL;
7f266840
DJ		 1840}
1841
1842static void
1843elf32_arm_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, arelent * bfd_reloc,
1844 Elf_Internal_Rela * elf_reloc)
1845{
1846 unsigned int r_type;
1847
1848 r_type = ELF32_R_TYPE (elf_reloc->r_info);
1849 bfd_reloc->howto = elf32_arm_howto_from_type (r_type);
1850}
1851
1852struct elf32_arm_reloc_map
1853 {
1854 bfd_reloc_code_real_type bfd_reloc_val;
1855 unsigned char elf_reloc_val;
1856 };
1857
1858/* All entries in this list must also be present in elf32_arm_howto_table. */
1859static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1860 {
1861 {BFD_RELOC_NONE, R_ARM_NONE},
1862 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1863 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1864 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
7f266840
DJ		 1865 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1866 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1867 {BFD_RELOC_32, R_ARM_ABS32},
1868 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1869 {BFD_RELOC_8, R_ARM_ABS8},
1870 {BFD_RELOC_16, R_ARM_ABS16},
1871 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
1872 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1873 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1874 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1875 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1876 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1877 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1878 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
7f266840
DJ		 1879 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1880 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1881 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
c19d1205 1882 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
7f266840 1883 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
b43420e6 1884 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
7f266840
DJ		 1885 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1886 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1887 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1888 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1889 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1890 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac
DJ		 1891 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
1892 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
0855e32b
NS		 1893 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1894 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
1895 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
1896 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
1897 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
1898 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1899 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1900 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1901 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1902 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1903 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
1904 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1905 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1906 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
34e77a92 1907 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
c19d1205
ZW		 1908 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1909 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1910 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1911 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1912 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1913 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1914 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1915 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1916 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1917 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1918 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1919 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1920 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1921 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1922 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1923 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1924 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1925 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1926 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1927 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1928 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1929 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1930 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1931 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1932 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1933 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1934 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
1935 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
1936 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
1937 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
1938 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
1939 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
1940 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
1941 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
1942 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
1943 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
1944 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 1945 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 1946 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
1947 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
1948 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
1949 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
1950 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 1951 };
1952
1953static reloc_howto_type *
f1c71a59
ZW		 1954elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1955 bfd_reloc_code_real_type code)
7f266840
DJ		 1956{
1957 unsigned int i;
8029a119 1958
906e58ca 1959 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 1960 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
1961 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 1962
c19d1205 1963 return NULL;
7f266840
DJ		 1964}
1965
157090f7
AM		 1966static reloc_howto_type *
1967elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1968 const char *r_name)
1969{
1970 unsigned int i;
1971
906e58ca 1972 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 1973 if (elf32_arm_howto_table_1[i].name != NULL
1974 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
1975 return &elf32_arm_howto_table_1[i];
1976
906e58ca 1977 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 1978 if (elf32_arm_howto_table_2[i].name != NULL
1979 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
1980 return &elf32_arm_howto_table_2[i];
1981
34e77a92
RS		 1982 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
1983 if (elf32_arm_howto_table_3[i].name != NULL
1984 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
1985 return &elf32_arm_howto_table_3[i];
1986
157090f7
AM		 1987 return NULL;
1988}
1989
906e58ca
NC		 1990/* Support for core dump NOTE sections. */
1991
7f266840 1992static bfd_boolean
f1c71a59 1993elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 1994{
1995 int offset;
1996 size_t size;
1997
1998 switch (note->descsz)
1999 {
2000 default:
2001 return FALSE;
2002
8029a119 2003 case 148: /* Linux/ARM 32-bit. */
7f266840 2004 /* pr_cursig */
228e534f 2005 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2006
2007 /* pr_pid */
228e534f 2008 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2009
2010 /* pr_reg */
2011 offset = 72;
2012 size = 72;
2013
2014 break;
2015 }
2016
2017 /* Make a ".reg/999" section. */
2018 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2019 size, note->descpos + offset);
2020}
2021
2022static bfd_boolean
f1c71a59 2023elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2024{
2025 switch (note->descsz)
2026 {
2027 default:
2028 return FALSE;
2029
8029a119 2030 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2031 elf_tdata (abfd)->core->pid
4395ee08 2032 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2033 elf_tdata (abfd)->core->program
7f266840 2034 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2035 elf_tdata (abfd)->core->command
7f266840
DJ		 2036 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2037 }
2038
2039 /* Note that for some reason, a spurious space is tacked
2040 onto the end of the args in some (at least one anyway)
2041 implementations, so strip it off if it exists. */
7f266840 2042 {
228e534f 2043 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2044 int n = strlen (command);
2045
2046 if (0 < n && command[n - 1] == ' ')
2047 command[n - 1] = '\0';
2048 }
2049
2050 return TRUE;
2051}
2052
1f20dca5
UW		 2053static char *
2054elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2055 int note_type, ...)
2056{
2057 switch (note_type)
2058 {
2059 default:
2060 return NULL;
2061
2062 case NT_PRPSINFO:
2063 {
2064 char data[124];
2065 va_list ap;
2066
2067 va_start (ap, note_type);
2068 memset (data, 0, sizeof (data));
2069 strncpy (data + 28, va_arg (ap, const char *), 16);
2070 strncpy (data + 44, va_arg (ap, const char *), 80);
2071 va_end (ap);
2072
2073 return elfcore_write_note (abfd, buf, bufsiz,
2074 "CORE", note_type, data, sizeof (data));
2075 }
2076
2077 case NT_PRSTATUS:
2078 {
2079 char data[148];
2080 va_list ap;
2081 long pid;
2082 int cursig;
2083 const void *greg;
2084
2085 va_start (ap, note_type);
2086 memset (data, 0, sizeof (data));
2087 pid = va_arg (ap, long);
2088 bfd_put_32 (abfd, pid, data + 24);
2089 cursig = va_arg (ap, int);
2090 bfd_put_16 (abfd, cursig, data + 12);
2091 greg = va_arg (ap, const void *);
2092 memcpy (data + 72, greg, 72);
2093 va_end (ap);
2094
2095 return elfcore_write_note (abfd, buf, bufsiz,
2096 "CORE", note_type, data, sizeof (data));
2097 }
2098 }
2099}
2100
6d00b590 2101#define TARGET_LITTLE_SYM arm_elf32_le_vec
7f266840 2102#define TARGET_LITTLE_NAME "elf32-littlearm"
6d00b590 2103#define TARGET_BIG_SYM arm_elf32_be_vec
7f266840
DJ		 2104#define TARGET_BIG_NAME "elf32-bigarm"
2105
2106#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2107#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2108#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2109
252b5132
RH		 2110typedef unsigned long int insn32;
2111typedef unsigned short int insn16;
2112
3a4a14e9
PB		 2113/* In lieu of proper flags, assume all EABIv4 or later objects are
2114 interworkable. */
57e8b36a 2115#define INTERWORK_FLAG(abfd) \
3a4a14e9 2116 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2117 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2118 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2119
252b5132
RH		 2120/* The linker script knows the section names for placement.
2121 The entry_names are used to do simple name mangling on the stubs.
2122 Given a function name, and its type, the stub can be found. The
9b485d32 2123 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2124#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2125#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2126
2127#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2128#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2129
c7b8f16e
JB		 2130#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2131#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2132
a504d23a
LA		 2133#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2134#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2135
845b51d6
PB		 2136#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2137#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2138
7413f23f
DJ		 2139#define STUB_ENTRY_NAME "__%s_veneer"
2140
252b5132
RH		 2141/* The name of the dynamic interpreter. This is put in the .interp
2142 section. */
2143#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2144
0855e32b 2145static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2146{
2147 0xe08e0000, /* add r0, lr, r0 */
2148 0xe5901004, /* ldr r1, [r0,#4] */
2149 0xe12fff11, /* bx r1 */
2150};
0855e32b
NS		 2151
2152static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2153{
2154 0xe52d2004, /* push {r2} */
2155 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2156 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2157 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2158 0xe081100f, /* 2: add r1, pc */
2159 0xe12fff12, /* bx r2 */
2160 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2161 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2162 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2163};
0855e32b 2164
5e681ec4
PB		 2165#ifdef FOUR_WORD_PLT
2166
252b5132
RH		 2167/* The first entry in a procedure linkage table looks like
2168 this. It is set up so that any shared library function that is
59f2c4e7 2169 called before the relocation has been set up calls the dynamic
9b485d32 2170 linker first. */
e5a52504 2171static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2172{
2173 0xe52de004, /* str lr, [sp, #-4]! */
2174 0xe59fe010, /* ldr lr, [pc, #16] */
2175 0xe08fe00e, /* add lr, pc, lr */
2176 0xe5bef008, /* ldr pc, [lr, #8]! */
2177};
5e681ec4
PB		 2178
2179/* Subsequent entries in a procedure linkage table look like
2180 this. */
e5a52504 2181static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2182{
2183 0xe28fc600, /* add ip, pc, #NN */
2184 0xe28cca00, /* add ip, ip, #NN */
2185 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2186 0x00000000, /* unused */
2187};
5e681ec4 2188
eed94f8f 2189#else /* not FOUR_WORD_PLT */
5e681ec4 2190
5e681ec4
PB		 2191/* The first entry in a procedure linkage table looks like
2192 this. It is set up so that any shared library function that is
2193 called before the relocation has been set up calls the dynamic
2194 linker first. */
e5a52504 2195static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2196{
2197 0xe52de004, /* str lr, [sp, #-4]! */
2198 0xe59fe004, /* ldr lr, [pc, #4] */
2199 0xe08fe00e, /* add lr, pc, lr */
2200 0xe5bef008, /* ldr pc, [lr, #8]! */
2201 0x00000000, /* &GOT[0] - . */
2202};
252b5132 2203
1db37fe6
YG		 2204/* By default subsequent entries in a procedure linkage table look like
2205 this. Offsets that don't fit into 28 bits will cause link error. */
2206static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2207{
2208 0xe28fc600, /* add ip, pc, #0xNN00000 */
2209 0xe28cca00, /* add ip, ip, #0xNN000 */
2210 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2211};
5e681ec4 2212
1db37fe6
YG		 2213/* When explicitly asked, we'll use this "long" entry format
2214 which can cope with arbitrary displacements. */
2215static const bfd_vma elf32_arm_plt_entry_long [] =
2216{
2217 0xe28fc200, /* add ip, pc, #0xN0000000 */
2218 0xe28cc600, /* add ip, ip, #0xNN00000 */
2219 0xe28cca00, /* add ip, ip, #0xNN000 */
2220 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2221};
2222
2223static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2224
eed94f8f
NC		 2225#endif /* not FOUR_WORD_PLT */
2226
2227/* The first entry in a procedure linkage table looks like this.
2228 It is set up so that any shared library function that is called before the
2229 relocation has been set up calls the dynamic linker first. */
2230static const bfd_vma elf32_thumb2_plt0_entry [] =
2231{
2232 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2233 an instruction maybe encoded to one or two array elements. */
2234 0xf8dfb500, /* push {lr} */
2235 0x44fee008, /* ldr.w lr, [pc, #8] */
469a3493 2236 /* add lr, pc */
eed94f8f
NC		 2237 0xff08f85e, /* ldr.w pc, [lr, #8]! */
2238 0x00000000, /* &GOT[0] - . */
2239};
2240
2241/* Subsequent entries in a procedure linkage table for thumb only target
2242 look like this. */
2243static const bfd_vma elf32_thumb2_plt_entry [] =
2244{
2245 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2246 an instruction maybe encoded to one or two array elements. */
2247 0x0c00f240, /* movw ip, #0xNNNN */
2248 0x0c00f2c0, /* movt ip, #0xNNNN */
2249 0xf8dc44fc, /* add ip, pc */
2250 0xbf00f000 /* ldr.w pc, [ip] */
469a3493 2251 /* nop */
eed94f8f 2252};
252b5132 2253
00a97672
RS		 2254/* The format of the first entry in the procedure linkage table
2255 for a VxWorks executable. */
2256static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb
NC		 2257{
2258 0xe52dc008, /* str ip,[sp,#-8]! */
2259 0xe59fc000, /* ldr ip,[pc] */
2260 0xe59cf008, /* ldr pc,[ip,#8] */
2261 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
2262};
00a97672
RS		 2263
2264/* The format of subsequent entries in a VxWorks executable. */
2265static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb
NC		 2266{
2267 0xe59fc000, /* ldr ip,[pc] */
2268 0xe59cf000, /* ldr pc,[ip] */
2269 0x00000000, /* .long @got */
2270 0xe59fc000, /* ldr ip,[pc] */
2271 0xea000000, /* b _PLT */
2272 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2273};
00a97672
RS		 2274
2275/* The format of entries in a VxWorks shared library. */
2276static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb
NC		 2277{
2278 0xe59fc000, /* ldr ip,[pc] */
2279 0xe79cf009, /* ldr pc,[ip,r9] */
2280 0x00000000, /* .long @got */
2281 0xe59fc000, /* ldr ip,[pc] */
2282 0xe599f008, /* ldr pc,[r9,#8] */
2283 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2284};
00a97672 2285
b7693d02
DJ		 2286/* An initial stub used if the PLT entry is referenced from Thumb code. */
2287#define PLT_THUMB_STUB_SIZE 4
2288static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2289{
2290 0x4778, /* bx pc */
2291 0x46c0 /* nop */
2292};
b7693d02 2293
e5a52504
MM		 2294/* The entries in a PLT when using a DLL-based target with multiple
2295 address spaces. */
906e58ca 2296static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb
NC		 2297{
2298 0xe51ff004, /* ldr pc, [pc, #-4] */
2299 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
2300};
2301
2302/* The first entry in a procedure linkage table looks like
2303 this. It is set up so that any shared library function that is
2304 called before the relocation has been set up calls the dynamic
2305 linker first. */
2306static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2307{
2308 /* First bundle: */
2309 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2310 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2311 0xe08cc00f, /* add ip, ip, pc */
2312 0xe52dc008, /* str ip, [sp, #-8]! */
2313 /* Second bundle: */
edccdf7c
RM		 2314 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2315 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2316 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2317 0xe12fff1c, /* bx ip */
b38cadfb 2318 /* Third bundle: */
edccdf7c
RM		 2319 0xe320f000, /* nop */
2320 0xe320f000, /* nop */
2321 0xe320f000, /* nop */
b38cadfb
NC		 2322 /* .Lplt_tail: */
2323 0xe50dc004, /* str ip, [sp, #-4] */
2324 /* Fourth bundle: */
edccdf7c
RM		 2325 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2326 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2327 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2328 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2329};
2330#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2331
2332/* Subsequent entries in a procedure linkage table look like this. */
2333static const bfd_vma elf32_arm_nacl_plt_entry [] =
2334{
2335 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2336 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2337 0xe08cc00f, /* add ip, ip, pc */
2338 0xea000000, /* b .Lplt_tail */
2339};
e5a52504 2340
906e58ca
NC		 2341#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2342#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2343#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2344#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2345#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2346#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2347#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2348#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2349
461a49ca 2350enum stub_insn_type
b38cadfb
NC		 2351{
2352 THUMB16_TYPE = 1,
2353 THUMB32_TYPE,
2354 ARM_TYPE,
2355 DATA_TYPE
2356};
461a49ca 2357
48229727
JB		 2358#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2359/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2360 is inserted in arm_build_one_stub(). */
2361#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2362#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2363#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2364#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2365#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2366#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2367
2368typedef struct
2369{
b38cadfb
NC		 2370 bfd_vma data;
2371 enum stub_insn_type type;
2372 unsigned int r_type;
2373 int reloc_addend;
461a49ca
DJ		 2374} insn_sequence;
2375
fea2b4d6
CL		 2376/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2377 to reach the stub if necessary. */
461a49ca 2378static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb
NC		 2379{
2380 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2381 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2382};
906e58ca 2383
fea2b4d6
CL		 2384/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2385 available. */
461a49ca 2386static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb
NC		 2387{
2388 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2389 ARM_INSN (0xe12fff1c), /* bx ip */
2390 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2391};
906e58ca 2392
d3626fb0 2393/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2394static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb
NC		 2395{
2396 THUMB16_INSN (0xb401), /* push {r0} */
2397 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2398 THUMB16_INSN (0x4684), /* mov ip, r0 */
2399 THUMB16_INSN (0xbc01), /* pop {r0} */
2400 THUMB16_INSN (0x4760), /* bx ip */
2401 THUMB16_INSN (0xbf00), /* nop */
2402 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2403};
906e58ca 2404
d3626fb0
CL		 2405/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2406 allowed. */
2407static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb
NC		 2408{
2409 THUMB16_INSN (0x4778), /* bx pc */
2410 THUMB16_INSN (0x46c0), /* nop */
2411 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2412 ARM_INSN (0xe12fff1c), /* bx ip */
2413 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2414};
d3626fb0 2415
fea2b4d6
CL		 2416/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2417 available. */
461a49ca 2418static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2419{
2420 THUMB16_INSN (0x4778), /* bx pc */
2421 THUMB16_INSN (0x46c0), /* nop */
2422 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2423 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2424};
906e58ca 2425
fea2b4d6
CL		 2426/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2427 one, when the destination is close enough. */
461a49ca 2428static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2429{
2430 THUMB16_INSN (0x4778), /* bx pc */
2431 THUMB16_INSN (0x46c0), /* nop */
2432 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2433};
c820be07 2434
cf3eccff 2435/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2436 blx to reach the stub if necessary. */
cf3eccff 2437static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb
NC		 2438{
2439 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2440 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
2441 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2442};
906e58ca 2443
cf3eccff
DJ		 2444/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2445 blx to reach the stub if necessary. We can not add into pc;
2446 it is not guaranteed to mode switch (different in ARMv6 and
2447 ARMv7). */
2448static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb
NC		 2449{
2450 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2451 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2452 ARM_INSN (0xe12fff1c), /* bx ip */
2453 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2454};
cf3eccff 2455
ebe24dd4
CL		 2456/* V4T ARM -> ARM long branch stub, PIC. */
2457static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb
NC		 2458{
2459 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2460 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2461 ARM_INSN (0xe12fff1c), /* bx ip */
2462 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2463};
ebe24dd4
CL		 2464
2465/* V4T Thumb -> ARM long branch stub, PIC. */
2466static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb
NC		 2467{
2468 THUMB16_INSN (0x4778), /* bx pc */
2469 THUMB16_INSN (0x46c0), /* nop */
2470 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2471 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
2472 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2473};
ebe24dd4 2474
d3626fb0
CL		 2475/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2476 architectures. */
ebe24dd4 2477static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb
NC		 2478{
2479 THUMB16_INSN (0xb401), /* push {r0} */
2480 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2481 THUMB16_INSN (0x46fc), /* mov ip, pc */
2482 THUMB16_INSN (0x4484), /* add ip, r0 */
2483 THUMB16_INSN (0xbc01), /* pop {r0} */
2484 THUMB16_INSN (0x4760), /* bx ip */
2485 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2486};
ebe24dd4 2487
d3626fb0
CL		 2488/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2489 allowed. */
2490static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb
NC		 2491{
2492 THUMB16_INSN (0x4778), /* bx pc */
2493 THUMB16_INSN (0x46c0), /* nop */
2494 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2495 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2496 ARM_INSN (0xe12fff1c), /* bx ip */
2497 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2498};
d3626fb0 2499
0855e32b
NS		 2500/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2501 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2502static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2503{
b38cadfb
NC		 2504 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2505 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
2506 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2507};
2508
2509/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2510 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2511static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2512{
b38cadfb
NC		 2513 THUMB16_INSN (0x4778), /* bx pc */
2514 THUMB16_INSN (0x46c0), /* nop */
2515 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2516 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
2517 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2518};
2519
7a89b94e
NC		 2520/* NaCl ARM -> ARM long branch stub. */
2521static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2522{
2523 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2524 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2525 ARM_INSN (0xe12fff1c), /* bx ip */
2526 ARM_INSN (0xe320f000), /* nop */
2527 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2528 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2529 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2530 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2531};
2532
2533/* NaCl ARM -> ARM long branch stub, PIC. */
2534static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2535{
2536 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2537 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
2538 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2539 ARM_INSN (0xe12fff1c), /* bx ip */
2540 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2541 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2542 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2543 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2544};
2545
2546
48229727
JB		 2547/* Cortex-A8 erratum-workaround stubs. */
2548
2549/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2550 can't use a conditional branch to reach this stub). */
2551
2552static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb
NC		 2553{
2554 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
2555 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2556 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2557};
48229727
JB		 2558
2559/* Stub used for b.w and bl.w instructions. */
2560
2561static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2562{
2563 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2564};
48229727
JB		 2565
2566static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2567{
2568 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2569};
48229727
JB		 2570
2571/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2572 instruction (which switches to ARM mode) to point to this stub. Jump to the
2573 real destination using an ARM-mode branch. */
2574
2575static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2576{
2577 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2578};
48229727 2579
9553db3c
NC		 2580/* For each section group there can be a specially created linker section
2581 to hold the stubs for that group. The name of the stub section is based
2582 upon the name of another section within that group with the suffix below
2583 applied.
2584
2585 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2586 create what appeared to be a linker stub section when it actually
2587 contained user code/data. For example, consider this fragment:
b38cadfb 2588
9553db3c
NC		 2589 const char * stubborn_problems[] = { "np" };
2590
2591 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2592 section called:
2593
2594 .data.rel.local.stubborn_problems
2595
2596 This then causes problems in arm32_arm_build_stubs() as it triggers:
2597
2598 // Ignore non-stub sections.
2599 if (!strstr (stub_sec->name, STUB_SUFFIX))
2600 continue;
2601
2602 And so the section would be ignored instead of being processed. Hence
2603 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2604 C identifier. */
2605#define STUB_SUFFIX ".__stub"
906e58ca 2606
738a79f6
CL		 2607/* One entry per long/short branch stub defined above. */
2608#define DEF_STUBS \
2609 DEF_STUB(long_branch_any_any) \
2610 DEF_STUB(long_branch_v4t_arm_thumb) \
2611 DEF_STUB(long_branch_thumb_only) \
2612 DEF_STUB(long_branch_v4t_thumb_thumb) \
2613 DEF_STUB(long_branch_v4t_thumb_arm) \
2614 DEF_STUB(short_branch_v4t_thumb_arm) \
2615 DEF_STUB(long_branch_any_arm_pic) \
2616 DEF_STUB(long_branch_any_thumb_pic) \
2617 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2618 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2619 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2620 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2621 DEF_STUB(long_branch_any_tls_pic) \
2622 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2623 DEF_STUB(long_branch_arm_nacl) \
2624 DEF_STUB(long_branch_arm_nacl_pic) \
48229727
JB		 2625 DEF_STUB(a8_veneer_b_cond) \
2626 DEF_STUB(a8_veneer_b) \
2627 DEF_STUB(a8_veneer_bl) \
2628 DEF_STUB(a8_veneer_blx)
738a79f6
CL		 2629
2630#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2631enum elf32_arm_stub_type
2632{
906e58ca 2633 arm_stub_none,
738a79f6 2634 DEF_STUBS
4f4faa4d 2635 max_stub_type
738a79f6
CL		 2636};
2637#undef DEF_STUB
2638
8d9d9490
TP		 2639/* Note the first a8_veneer type. */
2640const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2641
738a79f6
CL		 2642typedef struct
2643{
d3ce72d0 2644 const insn_sequence* template_sequence;
738a79f6
CL		 2645 int template_size;
2646} stub_def;
2647
2648#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2649static const stub_def stub_definitions[] =
2650{
738a79f6
CL		 2651 {NULL, 0},
2652 DEF_STUBS
906e58ca
NC		 2653};
2654
2655struct elf32_arm_stub_hash_entry
2656{
2657 /* Base hash table entry structure. */
2658 struct bfd_hash_entry root;
2659
2660 /* The stub section. */
2661 asection *stub_sec;
2662
2663 /* Offset within stub_sec of the beginning of this stub. */
2664 bfd_vma stub_offset;
2665
2666 /* Given the symbol's value and its section we can determine its final
2667 value when building the stubs (so the stub knows where to jump). */
2668 bfd_vma target_value;
2669 asection *target_section;
2670
8d9d9490
TP		 2671 /* Same as above but for the source of the branch to the stub. Used for
2672 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2673 such, source section does not need to be recorded since Cortex-A8 erratum
2674 workaround stubs are only generated when both source and target are in the
2675 same section. */
2676 bfd_vma source_value;
48229727
JB		 2677
2678 /* The instruction which caused this stub to be generated (only valid for
2679 Cortex-A8 erratum workaround stubs at present). */
2680 unsigned long orig_insn;
2681
461a49ca 2682 /* The stub type. */
906e58ca 2683 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2684 /* Its encoding size in bytes. */
2685 int stub_size;
2686 /* Its template. */
2687 const insn_sequence *stub_template;
2688 /* The size of the template (number of entries). */
2689 int stub_template_size;
906e58ca
NC		 2690
2691 /* The symbol table entry, if any, that this was derived from. */
2692 struct elf32_arm_link_hash_entry *h;
2693
35fc36a8
RS		 2694 /* Type of branch. */
2695 enum arm_st_branch_type branch_type;
906e58ca
NC		 2696
2697 /* Where this stub is being called from, or, in the case of combined
2698 stub sections, the first input section in the group. */
2699 asection *id_sec;
7413f23f
DJ		 2700
2701 /* The name for the local symbol at the start of this stub. The
2702 stub name in the hash table has to be unique; this does not, so
2703 it can be friendlier. */
2704 char *output_name;
906e58ca
NC		 2705};
2706
e489d0ae
PB		 2707/* Used to build a map of a section. This is required for mixed-endian
2708 code/data. */
2709
2710typedef struct elf32_elf_section_map
2711{
2712 bfd_vma vma;
2713 char type;
2714}
2715elf32_arm_section_map;
2716
c7b8f16e
JB		 2717/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2718
2719typedef enum
2720{
2721 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2722 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2723 VFP11_ERRATUM_ARM_VENEER,
2724 VFP11_ERRATUM_THUMB_VENEER
2725}
2726elf32_vfp11_erratum_type;
2727
2728typedef struct elf32_vfp11_erratum_list
2729{
2730 struct elf32_vfp11_erratum_list *next;
2731 bfd_vma vma;
2732 union
2733 {
2734 struct
2735 {
2736 struct elf32_vfp11_erratum_list *veneer;
2737 unsigned int vfp_insn;
2738 } b;
2739 struct
2740 {
2741 struct elf32_vfp11_erratum_list *branch;
2742 unsigned int id;
2743 } v;
2744 } u;
2745 elf32_vfp11_erratum_type type;
2746}
2747elf32_vfp11_erratum_list;
2748
a504d23a
LA		 2749/* Information about a STM32L4XX erratum veneer, or a branch to such a
2750 veneer. */
2751typedef enum
2752{
2753 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2754 STM32L4XX_ERRATUM_VENEER
2755}
2756elf32_stm32l4xx_erratum_type;
2757
2758typedef struct elf32_stm32l4xx_erratum_list
2759{
2760 struct elf32_stm32l4xx_erratum_list *next;
2761 bfd_vma vma;
2762 union
2763 {
2764 struct
2765 {
2766 struct elf32_stm32l4xx_erratum_list *veneer;
2767 unsigned int insn;
2768 } b;
2769 struct
2770 {
2771 struct elf32_stm32l4xx_erratum_list *branch;
2772 unsigned int id;
2773 } v;
2774 } u;
2775 elf32_stm32l4xx_erratum_type type;
2776}
2777elf32_stm32l4xx_erratum_list;
2778
2468f9c9
PB		 2779typedef enum
2780{
2781 DELETE_EXIDX_ENTRY,
2782 INSERT_EXIDX_CANTUNWIND_AT_END
2783}
2784arm_unwind_edit_type;
2785
2786/* A (sorted) list of edits to apply to an unwind table. */
2787typedef struct arm_unwind_table_edit
2788{
2789 arm_unwind_edit_type type;
2790 /* Note: we sometimes want to insert an unwind entry corresponding to a
2791 section different from the one we're currently writing out, so record the
2792 (text) section this edit relates to here. */
2793 asection *linked_section;
2794 unsigned int index;
2795 struct arm_unwind_table_edit *next;
2796}
2797arm_unwind_table_edit;
2798
8e3de13a 2799typedef struct _arm_elf_section_data
e489d0ae 2800{
2468f9c9 2801 /* Information about mapping symbols. */
e489d0ae 2802 struct bfd_elf_section_data elf;
8e3de13a 2803 unsigned int mapcount;
c7b8f16e 2804 unsigned int mapsize;
e489d0ae 2805 elf32_arm_section_map *map;
2468f9c9 2806 /* Information about CPU errata. */
c7b8f16e
JB		 2807 unsigned int erratumcount;
2808 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2809 unsigned int stm32l4xx_erratumcount;
2810 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2811 unsigned int additional_reloc_count;
2468f9c9
PB		 2812 /* Information about unwind tables. */
2813 union
2814 {
2815 /* Unwind info attached to a text section. */
2816 struct
2817 {
2818 asection *arm_exidx_sec;
2819 } text;
2820
2821 /* Unwind info attached to an .ARM.exidx section. */
2822 struct
2823 {
2824 arm_unwind_table_edit *unwind_edit_list;
2825 arm_unwind_table_edit *unwind_edit_tail;
2826 } exidx;
2827 } u;
8e3de13a
NC		 2828}
2829_arm_elf_section_data;
e489d0ae
PB		 2830
2831#define elf32_arm_section_data(sec) \
8e3de13a 2832 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2833
48229727
JB		 2834/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2835 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2836 so may be created multiple times: we use an array of these entries whilst
2837 relaxing which we can refresh easily, then create stubs for each potentially
2838 erratum-triggering instruction once we've settled on a solution. */
2839
b38cadfb
NC		 2840struct a8_erratum_fix
2841{
48229727
JB		 2842 bfd *input_bfd;
2843 asection *section;
2844 bfd_vma offset;
8d9d9490 2845 bfd_vma target_offset;
48229727
JB		 2846 unsigned long orig_insn;
2847 char *stub_name;
2848 enum elf32_arm_stub_type stub_type;
35fc36a8 2849 enum arm_st_branch_type branch_type;
48229727
JB		 2850};
2851
2852/* A table of relocs applied to branches which might trigger Cortex-A8
2853 erratum. */
2854
b38cadfb
NC		 2855struct a8_erratum_reloc
2856{
48229727
JB		 2857 bfd_vma from;
2858 bfd_vma destination;
92750f34
DJ		 2859 struct elf32_arm_link_hash_entry *hash;
2860 const char *sym_name;
48229727 2861 unsigned int r_type;
35fc36a8 2862 enum arm_st_branch_type branch_type;
48229727
JB		 2863 bfd_boolean non_a8_stub;
2864};
2865
ba93b8ac
DJ		 2866/* The size of the thread control block. */
2867#define TCB_SIZE 8
2868
34e77a92
RS		 2869/* ARM-specific information about a PLT entry, over and above the usual
2870 gotplt_union. */
b38cadfb
NC		 2871struct arm_plt_info
2872{
34e77a92
RS		 2873 /* We reference count Thumb references to a PLT entry separately,
2874 so that we can emit the Thumb trampoline only if needed. */
2875 bfd_signed_vma thumb_refcount;
2876
2877 /* Some references from Thumb code may be eliminated by BL->BLX
2878 conversion, so record them separately. */
2879 bfd_signed_vma maybe_thumb_refcount;
2880
2881 /* How many of the recorded PLT accesses were from non-call relocations.
2882 This information is useful when deciding whether anything takes the
2883 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2884 non-call references to the function should resolve directly to the
2885 real runtime target. */
2886 unsigned int noncall_refcount;
2887
2888 /* Since PLT entries have variable size if the Thumb prologue is
2889 used, we need to record the index into .got.plt instead of
2890 recomputing it from the PLT offset. */
2891 bfd_signed_vma got_offset;
2892};
2893
2894/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2895struct arm_local_iplt_info
2896{
34e77a92
RS		 2897 /* The information that is usually found in the generic ELF part of
2898 the hash table entry. */
2899 union gotplt_union root;
2900
2901 /* The information that is usually found in the ARM-specific part of
2902 the hash table entry. */
2903 struct arm_plt_info arm;
2904
2905 /* A list of all potential dynamic relocations against this symbol. */
2906 struct elf_dyn_relocs *dyn_relocs;
2907};
2908
0ffa91dd 2909struct elf_arm_obj_tdata
ba93b8ac
DJ		 2910{
2911 struct elf_obj_tdata root;
2912
2913 /* tls_type for each local got entry. */
2914 char *local_got_tls_type;
ee065d83 2915
0855e32b
NS		 2916 /* GOTPLT entries for TLS descriptors. */
2917 bfd_vma *local_tlsdesc_gotent;
2918
34e77a92
RS		 2919 /* Information for local symbols that need entries in .iplt. */
2920 struct arm_local_iplt_info **local_iplt;
2921
bf21ed78
MS		 2922 /* Zero to warn when linking objects with incompatible enum sizes. */
2923 int no_enum_size_warning;
a9dc9481
JM		 2924
2925 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2926 int no_wchar_size_warning;
ba93b8ac
DJ		 2927};
2928
0ffa91dd
NC		 2929#define elf_arm_tdata(bfd) \
2930 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 2931
0ffa91dd
NC		 2932#define elf32_arm_local_got_tls_type(bfd) \
2933 (elf_arm_tdata (bfd)->local_got_tls_type)
2934
0855e32b
NS		 2935#define elf32_arm_local_tlsdesc_gotent(bfd) \
2936 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2937
34e77a92
RS		 2938#define elf32_arm_local_iplt(bfd) \
2939 (elf_arm_tdata (bfd)->local_iplt)
2940
0ffa91dd
NC		 2941#define is_arm_elf(bfd) \
2942 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2943 && elf_tdata (bfd) != NULL \
4dfe6ac6 2944 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 2945
2946static bfd_boolean
2947elf32_arm_mkobject (bfd *abfd)
2948{
0ffa91dd 2949 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 2950 ARM_ELF_DATA);
ba93b8ac
DJ		 2951}
2952
ba93b8ac
DJ		 2953#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2954
ba96a88f 2955/* Arm ELF linker hash entry. */
252b5132 2956struct elf32_arm_link_hash_entry
b38cadfb
NC		 2957{
2958 struct elf_link_hash_entry root;
252b5132 2959
b38cadfb
NC		 2960 /* Track dynamic relocs copied for this symbol. */
2961 struct elf_dyn_relocs *dyn_relocs;
b7693d02 2962
b38cadfb
NC		 2963 /* ARM-specific PLT information. */
2964 struct arm_plt_info plt;
ba93b8ac
DJ		 2965
2966#define GOT_UNKNOWN 0
2967#define GOT_NORMAL 1
2968#define GOT_TLS_GD 2
2969#define GOT_TLS_IE 4
0855e32b
NS		 2970#define GOT_TLS_GDESC 8
2971#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 2972 unsigned int tls_type : 8;
34e77a92 2973
b38cadfb
NC		 2974 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
2975 unsigned int is_iplt : 1;
34e77a92 2976
b38cadfb 2977 unsigned int unused : 23;
a4fd1a8e 2978
b38cadfb
NC		 2979 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
2980 starting at the end of the jump table. */
2981 bfd_vma tlsdesc_got;
0855e32b 2982
b38cadfb
NC		 2983 /* The symbol marking the real symbol location for exported thumb
2984 symbols with Arm stubs. */
2985 struct elf_link_hash_entry *export_glue;
906e58ca 2986
b38cadfb 2987 /* A pointer to the most recently used stub hash entry against this
8029a119 2988 symbol. */
b38cadfb
NC		 2989 struct elf32_arm_stub_hash_entry *stub_cache;
2990};
252b5132 2991
252b5132 2992/* Traverse an arm ELF linker hash table. */
252b5132
RH		 2993#define elf32_arm_link_hash_traverse(table, func, info) \
2994 (elf_link_hash_traverse \
2995 (&(table)->root, \
b7693d02 2996 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 2997 (info)))
2998
2999/* Get the ARM elf linker hash table from a link_info structure. */
3000#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 3001 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
3002 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 3003
906e58ca
NC		 3004#define arm_stub_hash_lookup(table, string, create, copy) \
3005 ((struct elf32_arm_stub_hash_entry *) \
3006 bfd_hash_lookup ((table), (string), (create), (copy)))
3007
21d799b5
NC		 3008/* Array to keep track of which stub sections have been created, and
3009 information on stub grouping. */
3010struct map_stub
3011{
3012 /* This is the section to which stubs in the group will be
3013 attached. */
3014 asection *link_sec;
3015 /* The stub section. */
3016 asection *stub_sec;
3017};
3018
0855e32b
NS		 3019#define elf32_arm_compute_jump_table_size(htab) \
3020 ((htab)->next_tls_desc_index * 4)
3021
9b485d32 3022/* ARM ELF linker hash table. */
252b5132 3023struct elf32_arm_link_hash_table
906e58ca
NC		 3024{
3025 /* The main hash table. */
3026 struct elf_link_hash_table root;
252b5132 3027
906e58ca
NC		 3028 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3029 bfd_size_type thumb_glue_size;
252b5132 3030
906e58ca
NC		 3031 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3032 bfd_size_type arm_glue_size;
252b5132 3033
906e58ca
NC		 3034 /* The size in bytes of section containing the ARMv4 BX veneers. */
3035 bfd_size_type bx_glue_size;
845b51d6 3036
906e58ca
NC		 3037 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3038 veneer has been populated. */
3039 bfd_vma bx_glue_offset[15];
845b51d6 3040
906e58ca
NC		 3041 /* The size in bytes of the section containing glue for VFP11 erratum
3042 veneers. */
3043 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3044
a504d23a
LA		 3045 /* The size in bytes of the section containing glue for STM32L4XX erratum
3046 veneers. */
3047 bfd_size_type stm32l4xx_erratum_glue_size;
3048
48229727
JB		 3049 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3050 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3051 elf32_arm_write_section(). */
3052 struct a8_erratum_fix *a8_erratum_fixes;
3053 unsigned int num_a8_erratum_fixes;
3054
906e58ca
NC		 3055 /* An arbitrary input BFD chosen to hold the glue sections. */
3056 bfd * bfd_of_glue_owner;
ba96a88f 3057
906e58ca
NC		 3058 /* Nonzero to output a BE8 image. */
3059 int byteswap_code;
e489d0ae 3060
906e58ca
NC		 3061 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3062 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3063 int target1_is_rel;
9c504268 3064
906e58ca
NC		 3065 /* The relocation to use for R_ARM_TARGET2 relocations. */
3066 int target2_reloc;
eb043451 3067
906e58ca
NC		 3068 /* 0 = Ignore R_ARM_V4BX.
3069 1 = Convert BX to MOV PC.
3070 2 = Generate v4 interworing stubs. */
3071 int fix_v4bx;
319850b4 3072
48229727
JB		 3073 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3074 int fix_cortex_a8;
3075
2de70689
MGD		 3076 /* Whether we should fix the ARM1176 BLX immediate issue. */
3077 int fix_arm1176;
3078
906e58ca
NC		 3079 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3080 int use_blx;
33bfe774 3081
906e58ca
NC		 3082 /* What sort of code sequences we should look for which may trigger the
3083 VFP11 denorm erratum. */
3084 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3085
906e58ca
NC		 3086 /* Global counter for the number of fixes we have emitted. */
3087 int num_vfp11_fixes;
c7b8f16e 3088
a504d23a
LA		 3089 /* What sort of code sequences we should look for which may trigger the
3090 STM32L4XX erratum. */
3091 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3092
3093 /* Global counter for the number of fixes we have emitted. */
3094 int num_stm32l4xx_fixes;
3095
906e58ca
NC		 3096 /* Nonzero to force PIC branch veneers. */
3097 int pic_veneer;
27e55c4d 3098
906e58ca
NC		 3099 /* The number of bytes in the initial entry in the PLT. */
3100 bfd_size_type plt_header_size;
e5a52504 3101
906e58ca
NC		 3102 /* The number of bytes in the subsequent PLT etries. */
3103 bfd_size_type plt_entry_size;
e5a52504 3104
906e58ca
NC		 3105 /* True if the target system is VxWorks. */
3106 int vxworks_p;
00a97672 3107
906e58ca
NC		 3108 /* True if the target system is Symbian OS. */
3109 int symbian_p;
e5a52504 3110
b38cadfb
NC		 3111 /* True if the target system is Native Client. */
3112 int nacl_p;
3113
906e58ca
NC		 3114 /* True if the target uses REL relocations. */
3115 int use_rel;
4e7fd91e 3116
0855e32b
NS		 3117 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3118 bfd_vma next_tls_desc_index;
3119
3120 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3121 bfd_vma num_tls_desc;
3122
906e58ca 3123 /* Short-cuts to get to dynamic linker sections. */
906e58ca
NC		 3124 asection *sdynbss;
3125 asection *srelbss;
5e681ec4 3126
906e58ca
NC		 3127 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3128 asection *srelplt2;
00a97672 3129
0855e32b
NS		 3130 /* The offset into splt of the PLT entry for the TLS descriptor
3131 resolver. Special values are 0, if not necessary (or not found
3132 to be necessary yet), and -1 if needed but not determined
3133 yet. */
3134 bfd_vma dt_tlsdesc_plt;
3135
3136 /* The offset into sgot of the GOT entry used by the PLT entry
3137 above. */
b38cadfb 3138 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3139
3140 /* Offset in .plt section of tls_arm_trampoline. */
3141 bfd_vma tls_trampoline;
3142
906e58ca
NC		 3143 /* Data for R_ARM_TLS_LDM32 relocations. */
3144 union
3145 {
3146 bfd_signed_vma refcount;
3147 bfd_vma offset;
3148 } tls_ldm_got;
b7693d02 3149
87d72d41
AM		 3150 /* Small local sym cache. */
3151 struct sym_cache sym_cache;
906e58ca
NC		 3152
3153 /* For convenience in allocate_dynrelocs. */
3154 bfd * obfd;
3155
0855e32b
NS		 3156 /* The amount of space used by the reserved portion of the sgotplt
3157 section, plus whatever space is used by the jump slots. */
3158 bfd_vma sgotplt_jump_table_size;
3159
906e58ca
NC		 3160 /* The stub hash table. */
3161 struct bfd_hash_table stub_hash_table;
3162
3163 /* Linker stub bfd. */
3164 bfd *stub_bfd;
3165
3166 /* Linker call-backs. */
6bde4c52
TP		 3167 asection * (*add_stub_section) (const char *, asection *, asection *,
3168 unsigned int);
906e58ca
NC		 3169 void (*layout_sections_again) (void);
3170
3171 /* Array to keep track of which stub sections have been created, and
3172 information on stub grouping. */
21d799b5 3173 struct map_stub *stub_group;
906e58ca 3174
fe33d2fa 3175 /* Number of elements in stub_group. */
7292b3ac 3176 unsigned int top_id;
fe33d2fa 3177
906e58ca
NC		 3178 /* Assorted information used by elf32_arm_size_stubs. */
3179 unsigned int bfd_count;
7292b3ac 3180 unsigned int top_index;
906e58ca
NC		 3181 asection **input_list;
3182};
252b5132 3183
a504d23a
LA		 3184static inline int
3185ctz (unsigned int mask)
3186{
3187#if GCC_VERSION >= 3004
3188 return __builtin_ctz (mask);
3189#else
3190 unsigned int i;
3191
3192 for (i = 0; i < 8 * sizeof (mask); i++)
3193 {
3194 if (mask & 0x1)
3195 break;
3196 mask = (mask >> 1);
3197 }
3198 return i;
3199#endif
3200}
3201
3202static inline int
3203popcount (unsigned int mask)
3204{
3205#if GCC_VERSION >= 3004
3206 return __builtin_popcount (mask);
3207#else
3208 unsigned int i, sum = 0;
3209
3210 for (i = 0; i < 8 * sizeof (mask); i++)
3211 {
3212 if (mask & 0x1)
3213 sum++;
3214 mask = (mask >> 1);
3215 }
3216 return sum;
3217#endif
3218}
3219
780a67af
NC		 3220/* Create an entry in an ARM ELF linker hash table. */
3221
3222static struct bfd_hash_entry *
57e8b36a 3223elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3224 struct bfd_hash_table * table,
3225 const char * string)
780a67af
NC		 3226{
3227 struct elf32_arm_link_hash_entry * ret =
3228 (struct elf32_arm_link_hash_entry *) entry;
3229
3230 /* Allocate the structure if it has not already been allocated by a
3231 subclass. */
906e58ca 3232 if (ret == NULL)
21d799b5 3233 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3234 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3235 if (ret == NULL)
780a67af
NC		 3236 return (struct bfd_hash_entry *) ret;
3237
3238 /* Call the allocation method of the superclass. */
3239 ret = ((struct elf32_arm_link_hash_entry *)
3240 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3241 table, string));
57e8b36a 3242 if (ret != NULL)
b7693d02 3243 {
0bdcacaf 3244 ret->dyn_relocs = NULL;
ba93b8ac 3245 ret->tls_type = GOT_UNKNOWN;
0855e32b 3246 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3247 ret->plt.thumb_refcount = 0;
3248 ret->plt.maybe_thumb_refcount = 0;
3249 ret->plt.noncall_refcount = 0;
3250 ret->plt.got_offset = -1;
3251 ret->is_iplt = FALSE;
a4fd1a8e 3252 ret->export_glue = NULL;
906e58ca
NC		 3253
3254 ret->stub_cache = NULL;
b7693d02 3255 }
780a67af
NC		 3256
3257 return (struct bfd_hash_entry *) ret;
3258}
3259
34e77a92
RS		 3260/* Ensure that we have allocated bookkeeping structures for ABFD's local
3261 symbols. */
3262
3263static bfd_boolean
3264elf32_arm_allocate_local_sym_info (bfd *abfd)
3265{
3266 if (elf_local_got_refcounts (abfd) == NULL)
3267 {
3268 bfd_size_type num_syms;
3269 bfd_size_type size;
3270 char *data;
3271
3272 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3273 size = num_syms * (sizeof (bfd_signed_vma)
3274 + sizeof (struct arm_local_iplt_info *)
3275 + sizeof (bfd_vma)
3276 + sizeof (char));
3277 data = bfd_zalloc (abfd, size);
3278 if (data == NULL)
3279 return FALSE;
3280
3281 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3282 data += num_syms * sizeof (bfd_signed_vma);
3283
3284 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3285 data += num_syms * sizeof (struct arm_local_iplt_info *);
3286
3287 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3288 data += num_syms * sizeof (bfd_vma);
3289
3290 elf32_arm_local_got_tls_type (abfd) = data;
3291 }
3292 return TRUE;
3293}
3294
3295/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3296 to input bfd ABFD. Create the information if it doesn't already exist.
3297 Return null if an allocation fails. */
3298
3299static struct arm_local_iplt_info *
3300elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3301{
3302 struct arm_local_iplt_info **ptr;
3303
3304 if (!elf32_arm_allocate_local_sym_info (abfd))
3305 return NULL;
3306
3307 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3308 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3309 if (*ptr == NULL)
3310 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3311 return *ptr;
3312}
3313
3314/* Try to obtain PLT information for the symbol with index R_SYMNDX
3315 in ABFD's symbol table. If the symbol is global, H points to its
3316 hash table entry, otherwise H is null.
3317
3318 Return true if the symbol does have PLT information. When returning
3319 true, point *ROOT_PLT at the target-independent reference count/offset
3320 union and *ARM_PLT at the ARM-specific information. */
3321
3322static bfd_boolean
3323elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_entry *h,
3324 unsigned long r_symndx, union gotplt_union **root_plt,
3325 struct arm_plt_info **arm_plt)
3326{
3327 struct arm_local_iplt_info *local_iplt;
3328
3329 if (h != NULL)
3330 {
3331 *root_plt = &h->root.plt;
3332 *arm_plt = &h->plt;
3333 return TRUE;
3334 }
3335
3336 if (elf32_arm_local_iplt (abfd) == NULL)
3337 return FALSE;
3338
3339 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3340 if (local_iplt == NULL)
3341 return FALSE;
3342
3343 *root_plt = &local_iplt->root;
3344 *arm_plt = &local_iplt->arm;
3345 return TRUE;
3346}
3347
3348/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3349 before it. */
3350
3351static bfd_boolean
3352elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3353 struct arm_plt_info *arm_plt)
3354{
3355 struct elf32_arm_link_hash_table *htab;
3356
3357 htab = elf32_arm_hash_table (info);
3358 return (arm_plt->thumb_refcount != 0
3359 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3360}
3361
3362/* Return a pointer to the head of the dynamic reloc list that should
3363 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3364 ABFD's symbol table. Return null if an error occurs. */
3365
3366static struct elf_dyn_relocs **
3367elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3368 Elf_Internal_Sym *isym)
3369{
3370 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3371 {
3372 struct arm_local_iplt_info *local_iplt;
3373
3374 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3375 if (local_iplt == NULL)
3376 return NULL;
3377 return &local_iplt->dyn_relocs;
3378 }
3379 else
3380 {
3381 /* Track dynamic relocs needed for local syms too.
3382 We really need local syms available to do this
3383 easily. Oh well. */
3384 asection *s;
3385 void *vpp;
3386
3387 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3388 if (s == NULL)
3389 abort ();
3390
3391 vpp = &elf_section_data (s)->local_dynrel;
3392 return (struct elf_dyn_relocs **) vpp;
3393 }
3394}
3395
906e58ca
NC		 3396/* Initialize an entry in the stub hash table. */
3397
3398static struct bfd_hash_entry *
3399stub_hash_newfunc (struct bfd_hash_entry *entry,
3400 struct bfd_hash_table *table,
3401 const char *string)
3402{
3403 /* Allocate the structure if it has not already been allocated by a
3404 subclass. */
3405 if (entry == NULL)
3406 {
21d799b5 3407 entry = (struct bfd_hash_entry *)
99059e56 3408 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3409 if (entry == NULL)
3410 return entry;
3411 }
3412
3413 /* Call the allocation method of the superclass. */
3414 entry = bfd_hash_newfunc (entry, table, string);
3415 if (entry != NULL)
3416 {
3417 struct elf32_arm_stub_hash_entry *eh;
3418
3419 /* Initialize the local fields. */
3420 eh = (struct elf32_arm_stub_hash_entry *) entry;
3421 eh->stub_sec = NULL;
3422 eh->stub_offset = 0;
8d9d9490 3423 eh->source_value = 0;
906e58ca
NC		 3424 eh->target_value = 0;
3425 eh->target_section = NULL;
cedfb179 3426 eh->orig_insn = 0;
906e58ca 3427 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3428 eh->stub_size = 0;
3429 eh->stub_template = NULL;
3430 eh->stub_template_size = 0;
906e58ca
NC		 3431 eh->h = NULL;
3432 eh->id_sec = NULL;
d8d2f433 3433 eh->output_name = NULL;
906e58ca
NC		 3434 }
3435
3436 return entry;
3437}
3438
00a97672 3439/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3440 shortcuts to them in our hash table. */
3441
3442static bfd_boolean
57e8b36a 3443create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3444{
3445 struct elf32_arm_link_hash_table *htab;
3446
e5a52504 3447 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3448 if (htab == NULL)
3449 return FALSE;
3450
e5a52504
MM		 3451 /* BPABI objects never have a GOT, or associated sections. */
3452 if (htab->symbian_p)
3453 return TRUE;
3454
5e681ec4
PB		 3455 if (! _bfd_elf_create_got_section (dynobj, info))
3456 return FALSE;
3457
5e681ec4
PB		 3458 return TRUE;
3459}
3460
34e77a92
RS		 3461/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3462
3463static bfd_boolean
3464create_ifunc_sections (struct bfd_link_info *info)
3465{
3466 struct elf32_arm_link_hash_table *htab;
3467 const struct elf_backend_data *bed;
3468 bfd *dynobj;
3469 asection *s;
3470 flagword flags;
b38cadfb 3471
34e77a92
RS		 3472 htab = elf32_arm_hash_table (info);
3473 dynobj = htab->root.dynobj;
3474 bed = get_elf_backend_data (dynobj);
3475 flags = bed->dynamic_sec_flags;
3476
3477 if (htab->root.iplt == NULL)
3478 {
3d4d4302
AM		 3479 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3480 flags | SEC_READONLY | SEC_CODE);
34e77a92 3481 if (s == NULL
a0f49396 3482 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3483 return FALSE;
3484 htab->root.iplt = s;
3485 }
3486
3487 if (htab->root.irelplt == NULL)
3488 {
3d4d4302
AM		 3489 s = bfd_make_section_anyway_with_flags (dynobj,
3490 RELOC_SECTION (htab, ".iplt"),
3491 flags | SEC_READONLY);
34e77a92 3492 if (s == NULL
a0f49396 3493 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3494 return FALSE;
3495 htab->root.irelplt = s;
3496 }
3497
3498 if (htab->root.igotplt == NULL)
3499 {
3d4d4302 3500 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3501 if (s == NULL
3502 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3503 return FALSE;
3504 htab->root.igotplt = s;
3505 }
3506 return TRUE;
3507}
3508
eed94f8f
NC		 3509/* Determine if we're dealing with a Thumb only architecture. */
3510
3511static bfd_boolean
3512using_thumb_only (struct elf32_arm_link_hash_table *globals)
3513{
2fd158eb
TP		 3514 int arch;
3515 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3516 Tag_CPU_arch_profile);
eed94f8f 3517
2fd158eb
TP		 3518 if (profile)
3519 return profile == 'M';
eed94f8f 3520
2fd158eb 3521 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
eed94f8f 3522
2fd158eb
TP		 3523 if (arch == TAG_CPU_ARCH_V6_M
3524 || arch == TAG_CPU_ARCH_V6S_M
3525 || arch == TAG_CPU_ARCH_V7E_M
3526 || arch == TAG_CPU_ARCH_V8M_BASE
3527 || arch == TAG_CPU_ARCH_V8M_MAIN)
3528 return TRUE;
eed94f8f 3529
2fd158eb 3530 return FALSE;
eed94f8f
NC		 3531}
3532
3533/* Determine if we're dealing with a Thumb-2 object. */
3534
3535static bfd_boolean
3536using_thumb2 (struct elf32_arm_link_hash_table *globals)
3537{
3538 int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3539 Tag_CPU_arch);
3540 return arch == TAG_CPU_ARCH_V6T2 || arch >= TAG_CPU_ARCH_V7;
3541}
3542
00a97672
RS		 3543/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3544 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3545 hash table. */
3546
3547static bfd_boolean
57e8b36a 3548elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3549{
3550 struct elf32_arm_link_hash_table *htab;
3551
3552 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3553 if (htab == NULL)
3554 return FALSE;
3555
362d30a1 3556 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3557 return FALSE;
3558
3559 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3560 return FALSE;
3561
3d4d4302 3562 htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss");
0e1862bb 3563 if (!bfd_link_pic (info))
3d4d4302
AM		 3564 htab->srelbss = bfd_get_linker_section (dynobj,
3565 RELOC_SECTION (htab, ".bss"));
00a97672
RS		 3566
3567 if (htab->vxworks_p)
3568 {
3569 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3570 return FALSE;
3571
0e1862bb 3572 if (bfd_link_pic (info))
00a97672
RS		 3573 {
3574 htab->plt_header_size = 0;
3575 htab->plt_entry_size
3576 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3577 }
3578 else
3579 {
3580 htab->plt_header_size
3581 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3582 htab->plt_entry_size
3583 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3584 }
aebf9be7
NC		 3585
3586 if (elf_elfheader (dynobj))
3587 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
00a97672 3588 }
eed94f8f
NC		 3589 else
3590 {
3591 /* PR ld/16017
3592 Test for thumb only architectures. Note - we cannot just call
3593 using_thumb_only() as the attributes in the output bfd have not been
3594 initialised at this point, so instead we use the input bfd. */
3595 bfd * saved_obfd = htab->obfd;
3596
3597 htab->obfd = dynobj;
3598 if (using_thumb_only (htab))
3599 {
3600 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3601 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3602 }
3603 htab->obfd = saved_obfd;
3604 }
5e681ec4 3605
362d30a1
RS		 3606 if (!htab->root.splt
3607 || !htab->root.srelplt
e5a52504 3608 || !htab->sdynbss
0e1862bb 3609 || (!bfd_link_pic (info) && !htab->srelbss))
5e681ec4
PB		 3610 abort ();
3611
3612 return TRUE;
3613}
3614
906e58ca
NC		 3615/* Copy the extra info we tack onto an elf_link_hash_entry. */
3616
3617static void
3618elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3619 struct elf_link_hash_entry *dir,
3620 struct elf_link_hash_entry *ind)
3621{
3622 struct elf32_arm_link_hash_entry *edir, *eind;
3623
3624 edir = (struct elf32_arm_link_hash_entry *) dir;
3625 eind = (struct elf32_arm_link_hash_entry *) ind;
3626
0bdcacaf 3627 if (eind->dyn_relocs != NULL)
906e58ca 3628 {
0bdcacaf 3629 if (edir->dyn_relocs != NULL)
906e58ca 3630 {
0bdcacaf
RS		 3631 struct elf_dyn_relocs **pp;
3632 struct elf_dyn_relocs *p;
906e58ca
NC		 3633
3634 /* Add reloc counts against the indirect sym to the direct sym
3635 list. Merge any entries against the same section. */
0bdcacaf 3636 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3637 {
0bdcacaf 3638 struct elf_dyn_relocs *q;
906e58ca 3639
0bdcacaf
RS		 3640 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3641 if (q->sec == p->sec)
906e58ca
NC		 3642 {
3643 q->pc_count += p->pc_count;
3644 q->count += p->count;
3645 *pp = p->next;
3646 break;
3647 }
3648 if (q == NULL)
3649 pp = &p->next;
3650 }
0bdcacaf 3651 *pp = edir->dyn_relocs;
906e58ca
NC		 3652 }
3653
0bdcacaf
RS		 3654 edir->dyn_relocs = eind->dyn_relocs;
3655 eind->dyn_relocs = NULL;
906e58ca
NC		 3656 }
3657
3658 if (ind->root.type == bfd_link_hash_indirect)
3659 {
3660 /* Copy over PLT info. */
34e77a92
RS		 3661 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3662 eind->plt.thumb_refcount = 0;
3663 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3664 eind->plt.maybe_thumb_refcount = 0;
3665 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3666 eind->plt.noncall_refcount = 0;
3667
3668 /* We should only allocate a function to .iplt once the final
3669 symbol information is known. */
3670 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3671
3672 if (dir->got.refcount <= 0)
3673 {
3674 edir->tls_type = eind->tls_type;
3675 eind->tls_type = GOT_UNKNOWN;
3676 }
3677 }
3678
3679 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3680}
3681
68faa637
AM		 3682/* Destroy an ARM elf linker hash table. */
3683
3684static void
d495ab0d 3685elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3686{
3687 struct elf32_arm_link_hash_table *ret
d495ab0d 3688 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3689
3690 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3691 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3692}
3693
906e58ca
NC		 3694/* Create an ARM elf linker hash table. */
3695
3696static struct bfd_link_hash_table *
3697elf32_arm_link_hash_table_create (bfd *abfd)
3698{
3699 struct elf32_arm_link_hash_table *ret;
3700 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3701
7bf52ea2 3702 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3703 if (ret == NULL)
3704 return NULL;
3705
3706 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3707 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3708 sizeof (struct elf32_arm_link_hash_entry),
3709 ARM_ELF_DATA))
906e58ca
NC		 3710 {
3711 free (ret);
3712 return NULL;
3713 }
3714
906e58ca 3715 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3716 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3717#ifdef FOUR_WORD_PLT
3718 ret->plt_header_size = 16;
3719 ret->plt_entry_size = 16;
3720#else
3721 ret->plt_header_size = 20;
1db37fe6 3722 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3723#endif
906e58ca 3724 ret->use_rel = 1;
906e58ca 3725 ret->obfd = abfd;
906e58ca
NC		 3726
3727 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3728 sizeof (struct elf32_arm_stub_hash_entry)))
3729 {
d495ab0d 3730 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3731 return NULL;
3732 }
d495ab0d 3733 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3734
3735 return &ret->root.root;
3736}
3737
cd1dac3d
DG		 3738/* Determine what kind of NOPs are available. */
3739
3740static bfd_boolean
3741arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3742{
3743 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3744 Tag_CPU_arch);
3745 return arch == TAG_CPU_ARCH_V6T2
3746 || arch == TAG_CPU_ARCH_V6K
9e3c6df6
PB		 3747 || arch == TAG_CPU_ARCH_V7
3748 || arch == TAG_CPU_ARCH_V7E_M;
cd1dac3d
DG		 3749}
3750
3751static bfd_boolean
3752arch_has_thumb2_nop (struct elf32_arm_link_hash_table *globals)
3753{
3754 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3755 Tag_CPU_arch);
9e3c6df6
PB		 3756 return (arch == TAG_CPU_ARCH_V6T2 || arch == TAG_CPU_ARCH_V7
3757 || arch == TAG_CPU_ARCH_V7E_M);
cd1dac3d
DG		 3758}
3759
f4ac8484
DJ		 3760static bfd_boolean
3761arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3762{
3763 switch (stub_type)
3764 {
fea2b4d6
CL		 3765 case arm_stub_long_branch_thumb_only:
3766 case arm_stub_long_branch_v4t_thumb_arm:
3767 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3768 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3769 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3770 case arm_stub_long_branch_thumb_only_pic:
f4ac8484
DJ		 3771 return TRUE;
3772 case arm_stub_none:
3773 BFD_FAIL ();
3774 return FALSE;
3775 break;
3776 default:
3777 return FALSE;
3778 }
3779}
3780
906e58ca
NC		 3781/* Determine the type of stub needed, if any, for a call. */
3782
3783static enum elf32_arm_stub_type
3784arm_type_of_stub (struct bfd_link_info *info,
3785 asection *input_sec,
3786 const Elf_Internal_Rela *rel,
34e77a92 3787 unsigned char st_type,
35fc36a8 3788 enum arm_st_branch_type *actual_branch_type,
906e58ca 3789 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3790 bfd_vma destination,
3791 asection *sym_sec,
3792 bfd *input_bfd,
3793 const char *name)
906e58ca
NC		 3794{
3795 bfd_vma location;
3796 bfd_signed_vma branch_offset;
3797 unsigned int r_type;
3798 struct elf32_arm_link_hash_table * globals;
3799 int thumb2;
3800 int thumb_only;
3801 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3802 int use_plt = 0;
35fc36a8 3803 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3804 union gotplt_union *root_plt;
3805 struct arm_plt_info *arm_plt;
906e58ca 3806
35fc36a8 3807 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3808 return stub_type;
3809
906e58ca 3810 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3811 if (globals == NULL)
3812 return stub_type;
906e58ca
NC		 3813
3814 thumb_only = using_thumb_only (globals);
3815
3816 thumb2 = using_thumb2 (globals);
3817
3818 /* Determine where the call point is. */
3819 location = (input_sec->output_offset
3820 + input_sec->output_section->vma
3821 + rel->r_offset);
3822
906e58ca
NC		 3823 r_type = ELF32_R_TYPE (rel->r_info);
3824
39f21624
NC		 3825 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3826 are considering a function call relocation. */
c5423981
TG		 3827 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
3828 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3829 && branch_type == ST_BRANCH_TO_ARM)
3830 branch_type = ST_BRANCH_TO_THUMB;
3831
34e77a92
RS		 3832 /* For TLS call relocs, it is the caller's responsibility to provide
3833 the address of the appropriate trampoline. */
3834 if (r_type != R_ARM_TLS_CALL
3835 && r_type != R_ARM_THM_TLS_CALL
3836 && elf32_arm_get_plt_info (input_bfd, hash, ELF32_R_SYM (rel->r_info),
3837 &root_plt, &arm_plt)
3838 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3839 {
34e77a92 3840 asection *splt;
fe33d2fa 3841
34e77a92
RS		 3842 if (hash == NULL || hash->is_iplt)
3843 splt = globals->root.iplt;
3844 else
3845 splt = globals->root.splt;
3846 if (splt != NULL)
b38cadfb 3847 {
34e77a92
RS		 3848 use_plt = 1;
3849
3850 /* Note when dealing with PLT entries: the main PLT stub is in
3851 ARM mode, so if the branch is in Thumb mode, another
3852 Thumb->ARM stub will be inserted later just before the ARM
3853 PLT stub. We don't take this extra distance into account
3854 here, because if a long branch stub is needed, we'll add a
3855 Thumb->Arm one and branch directly to the ARM PLT entry
3856 because it avoids spreading offset corrections in several
3857 places. */
3858
3859 destination = (splt->output_section->vma
3860 + splt->output_offset
3861 + root_plt->offset);
3862 st_type = STT_FUNC;
3863 branch_type = ST_BRANCH_TO_ARM;
3864 }
5fa9e92f 3865 }
34e77a92
RS		 3866 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3867 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 3868
fe33d2fa
CL		 3869 branch_offset = (bfd_signed_vma)(destination - location);
3870
0855e32b 3871 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 3872 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 3873 {
5fa9e92f
CL		 3874 /* Handle cases where:
3875 - this call goes too far (different Thumb/Thumb2 max
99059e56 3876 distance)
155d87d7 3877 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 3878 Thumb->Arm branch (not bl). A stub is needed in this case,
3879 but only if this call is not through a PLT entry. Indeed,
3880 PLT stubs handle mode switching already.
5fa9e92f 3881 */
906e58ca
NC		 3882 if ((!thumb2
3883 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
3884 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
3885 || (thumb2
3886 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
3887 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 3888 || (thumb2
3889 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
3890 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
3891 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 3892 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 3893 && (((r_type == R_ARM_THM_CALL
3894 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981
TG		 3895 || (r_type == R_ARM_THM_JUMP24)
3896 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 3897 && !use_plt))
906e58ca 3898 {
35fc36a8 3899 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 3900 {
3901 /* Thumb to thumb. */
3902 if (!thumb_only)
3903 {
0e1862bb 3904 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3905 /* PIC stubs. */
155d87d7 3906 ? ((globals->use_blx
9553db3c 3907 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 3908 /* V5T and above. Stub starts with ARM code, so
3909 we must be able to switch mode before
3910 reaching it, which is only possible for 'bl'
3911 (ie R_ARM_THM_CALL relocation). */
cf3eccff 3912 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 3913 /* On V4T, use Thumb code only. */
d3626fb0 3914 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 3915
3916 /* non-PIC stubs. */
155d87d7 3917 : ((globals->use_blx
9553db3c 3918 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 3919 /* V5T and above. */
3920 ? arm_stub_long_branch_any_any
3921 /* V4T. */
d3626fb0 3922 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 3923 }
3924 else
3925 {
0e1862bb 3926 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
ebe24dd4
CL		 3927 /* PIC stub. */
3928 ? arm_stub_long_branch_thumb_only_pic
c2b4a39d
CL		 3929 /* non-PIC stub. */
3930 : arm_stub_long_branch_thumb_only;
906e58ca
NC		 3931 }
3932 }
3933 else
3934 {
3935 /* Thumb to arm. */
c820be07
NC		 3936 if (sym_sec != NULL
3937 && sym_sec->owner != NULL
3938 && !INTERWORK_FLAG (sym_sec->owner))
3939 {
3940 (*_bfd_error_handler)
3941 (_("%B(%s): warning: interworking not enabled.\n"
3942 " first occurrence: %B: Thumb call to ARM"),
3943 sym_sec->owner, input_bfd, name);
3944 }
3945
0855e32b 3946 stub_type =
0e1862bb 3947 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3948 /* PIC stubs. */
0855e32b 3949 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 3950 /* TLS PIC stubs. */
0855e32b
NS		 3951 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
3952 : arm_stub_long_branch_v4t_thumb_tls_pic)
3953 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
3954 /* V5T PIC and above. */
3955 ? arm_stub_long_branch_any_arm_pic
3956 /* V4T PIC stub. */
3957 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 3958
3959 /* non-PIC stubs. */
0855e32b 3960 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 3961 /* V5T and above. */
3962 ? arm_stub_long_branch_any_any
3963 /* V4T. */
3964 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 3965
3966 /* Handle v4t short branches. */
fea2b4d6 3967 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 3968 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
3969 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 3970 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 3971 }
3972 }
3973 }
fe33d2fa
CL		 3974 else if (r_type == R_ARM_CALL
3975 || r_type == R_ARM_JUMP24
0855e32b
NS		 3976 || r_type == R_ARM_PLT32
3977 || r_type == R_ARM_TLS_CALL)
906e58ca 3978 {
35fc36a8 3979 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 3980 {
3981 /* Arm to thumb. */
c820be07
NC		 3982
3983 if (sym_sec != NULL
3984 && sym_sec->owner != NULL
3985 && !INTERWORK_FLAG (sym_sec->owner))
3986 {
3987 (*_bfd_error_handler)
3988 (_("%B(%s): warning: interworking not enabled.\n"
c2b4a39d 3989 " first occurrence: %B: ARM call to Thumb"),
c820be07
NC		 3990 sym_sec->owner, input_bfd, name);
3991 }
3992
3993 /* We have an extra 2-bytes reach because of
3994 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 3995 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
3996 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 3997 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 3998 || (r_type == R_ARM_JUMP24)
3999 || (r_type == R_ARM_PLT32))
906e58ca 4000 {
0e1862bb 4001 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4002 /* PIC stubs. */
ebe24dd4
CL		 4003 ? ((globals->use_blx)
4004 /* V5T and above. */
4005 ? arm_stub_long_branch_any_thumb_pic
4006 /* V4T stub. */
4007 : arm_stub_long_branch_v4t_arm_thumb_pic)
4008
c2b4a39d
CL		 4009 /* non-PIC stubs. */
4010 : ((globals->use_blx)
4011 /* V5T and above. */
4012 ? arm_stub_long_branch_any_any
4013 /* V4T. */
4014 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4015 }
4016 }
4017 else
4018 {
4019 /* Arm to arm. */
4020 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4021 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4022 {
0855e32b 4023 stub_type =
0e1862bb 4024 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4025 /* PIC stubs. */
0855e32b 4026 ? (r_type == R_ARM_TLS_CALL
6a631e86 4027 /* TLS PIC Stub. */
0855e32b 4028 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4029 : (globals->nacl_p
4030 ? arm_stub_long_branch_arm_nacl_pic
4031 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4032 /* non-PIC stubs. */
7a89b94e
NC		 4033 : (globals->nacl_p
4034 ? arm_stub_long_branch_arm_nacl
4035 : arm_stub_long_branch_any_any);
906e58ca
NC		 4036 }
4037 }
4038 }
4039
fe33d2fa
CL		 4040 /* If a stub is needed, record the actual destination type. */
4041 if (stub_type != arm_stub_none)
35fc36a8 4042 *actual_branch_type = branch_type;
fe33d2fa 4043
906e58ca
NC		 4044 return stub_type;
4045}
4046
4047/* Build a name for an entry in the stub hash table. */
4048
4049static char *
4050elf32_arm_stub_name (const asection *input_section,
4051 const asection *sym_sec,
4052 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4053 const Elf_Internal_Rela *rel,
4054 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4055{
4056 char *stub_name;
4057 bfd_size_type len;
4058
4059 if (hash)
4060 {
fe33d2fa 4061 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4062 stub_name = (char *) bfd_malloc (len);
906e58ca 4063 if (stub_name != NULL)
fe33d2fa 4064 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4065 input_section->id & 0xffffffff,
4066 hash->root.root.root.string,
fe33d2fa
CL		 4067 (int) rel->r_addend & 0xffffffff,
4068 (int) stub_type);
906e58ca
NC		 4069 }
4070 else
4071 {
fe33d2fa 4072 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4073 stub_name = (char *) bfd_malloc (len);
906e58ca 4074 if (stub_name != NULL)
fe33d2fa 4075 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4076 input_section->id & 0xffffffff,
4077 sym_sec->id & 0xffffffff,
0855e32b
NS		 4078 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4079 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4080 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4081 (int) rel->r_addend & 0xffffffff,
4082 (int) stub_type);
906e58ca
NC		 4083 }
4084
4085 return stub_name;
4086}
4087
4088/* Look up an entry in the stub hash. Stub entries are cached because
4089 creating the stub name takes a bit of time. */
4090
4091static struct elf32_arm_stub_hash_entry *
4092elf32_arm_get_stub_entry (const asection *input_section,
4093 const asection *sym_sec,
4094 struct elf_link_hash_entry *hash,
4095 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4096 struct elf32_arm_link_hash_table *htab,
4097 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4098{
4099 struct elf32_arm_stub_hash_entry *stub_entry;
4100 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4101 const asection *id_sec;
4102
4103 if ((input_section->flags & SEC_CODE) == 0)
4104 return NULL;
4105
4106 /* If this input section is part of a group of sections sharing one
4107 stub section, then use the id of the first section in the group.
4108 Stub names need to include a section id, as there may well be
4109 more than one stub used to reach say, printf, and we need to
4110 distinguish between them. */
4111 id_sec = htab->stub_group[input_section->id].link_sec;
4112
4113 if (h != NULL && h->stub_cache != NULL
4114 && h->stub_cache->h == h
fe33d2fa
CL		 4115 && h->stub_cache->id_sec == id_sec
4116 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4117 {
4118 stub_entry = h->stub_cache;
4119 }
4120 else
4121 {
4122 char *stub_name;
4123
fe33d2fa 4124 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4125 if (stub_name == NULL)
4126 return NULL;
4127
4128 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4129 stub_name, FALSE, FALSE);
4130 if (h != NULL)
4131 h->stub_cache = stub_entry;
4132
4133 free (stub_name);
4134 }
4135
4136 return stub_entry;
4137}
4138
daa4adae
TP		 4139/* Whether veneers of type STUB_TYPE require to be in a dedicated output
4140 section. */
4141
4142static bfd_boolean
4143arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4144{
4145 if (stub_type >= max_stub_type)
4146 abort (); /* Should be unreachable. */
4147
4148 return FALSE;
4149}
4150
4151/* Required alignment (as a power of 2) for the dedicated section holding
4152 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4153 with input sections. */
4154
4155static int
4156arm_dedicated_stub_output_section_required_alignment
4157 (enum elf32_arm_stub_type stub_type)
4158{
4159 if (stub_type >= max_stub_type)
4160 abort (); /* Should be unreachable. */
4161
4162 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4163 return 0;
4164}
4165
4166/* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4167 NULL if veneers of this type are interspersed with input sections. */
4168
4169static const char *
4170arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4171{
4172 if (stub_type >= max_stub_type)
4173 abort (); /* Should be unreachable. */
4174
4175 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4176 return NULL;
4177}
4178
4179/* If veneers of type STUB_TYPE should go in a dedicated output section,
4180 returns the address of the hash table field in HTAB holding a pointer to the
4181 corresponding input section. Otherwise, returns NULL. */
4182
4183static asection **
4184arm_dedicated_stub_input_section_ptr
4185 (struct elf32_arm_link_hash_table *htab ATTRIBUTE_UNUSED,
4186 enum elf32_arm_stub_type stub_type)
4187{
4188 if (stub_type >= max_stub_type)
4189 abort (); /* Should be unreachable. */
4190
4191 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4192 return NULL;
4193}
4194
4195/* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4196 is the section that branch into veneer and can be NULL if stub should go in
4197 a dedicated output section. Returns a pointer to the stub section, and the
4198 section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4199 LINK_SEC_P may be NULL. */
906e58ca 4200
48229727
JB		 4201static asection *
4202elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
daa4adae
TP		 4203 struct elf32_arm_link_hash_table *htab,
4204 enum elf32_arm_stub_type stub_type)
906e58ca 4205{
daa4adae
TP		 4206 asection *link_sec, *out_sec, **stub_sec_p;
4207 const char *stub_sec_prefix;
4208 bfd_boolean dedicated_output_section =
4209 arm_dedicated_stub_output_section_required (stub_type);
4210 int align;
906e58ca 4211
daa4adae 4212 if (dedicated_output_section)
906e58ca 4213 {
daa4adae
TP		 4214 bfd *output_bfd = htab->obfd;
4215 const char *out_sec_name =
4216 arm_dedicated_stub_output_section_name (stub_type);
4217 link_sec = NULL;
4218 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4219 stub_sec_prefix = out_sec_name;
4220 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4221 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4222 if (out_sec == NULL)
906e58ca 4223 {
daa4adae
TP		 4224 (*_bfd_error_handler) (_("No address assigned to the veneers output "
4225 "section %s"), out_sec_name);
4226 return NULL;
906e58ca 4227 }
daa4adae
TP		 4228 }
4229 else
4230 {
4231 link_sec = htab->stub_group[section->id].link_sec;
4232 BFD_ASSERT (link_sec != NULL);
4233 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4234 if (*stub_sec_p == NULL)
4235 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4236 stub_sec_prefix = link_sec->name;
4237 out_sec = link_sec->output_section;
4238 align = htab->nacl_p ? 4 : 3;
906e58ca 4239 }
b38cadfb 4240
daa4adae
TP		 4241 if (*stub_sec_p == NULL)
4242 {
4243 size_t namelen;
4244 bfd_size_type len;
4245 char *s_name;
4246
4247 namelen = strlen (stub_sec_prefix);
4248 len = namelen + sizeof (STUB_SUFFIX);
4249 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4250 if (s_name == NULL)
4251 return NULL;
4252
4253 memcpy (s_name, stub_sec_prefix, namelen);
4254 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4255 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4256 align);
4257 if (*stub_sec_p == NULL)
4258 return NULL;
4259
4260 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4261 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4262 | SEC_KEEP;
4263 }
4264
4265 if (!dedicated_output_section)
4266 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4267
48229727
JB		 4268 if (link_sec_p)
4269 *link_sec_p = link_sec;
b38cadfb 4270
daa4adae 4271 return *stub_sec_p;
48229727
JB		 4272}
4273
4274/* Add a new stub entry to the stub hash. Not all fields of the new
4275 stub entry are initialised. */
4276
4277static struct elf32_arm_stub_hash_entry *
daa4adae
TP		 4278elf32_arm_add_stub (const char *stub_name, asection *section,
4279 struct elf32_arm_link_hash_table *htab,
4280 enum elf32_arm_stub_type stub_type)
48229727
JB		 4281{
4282 asection *link_sec;
4283 asection *stub_sec;
4284 struct elf32_arm_stub_hash_entry *stub_entry;
4285
daa4adae
TP		 4286 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4287 stub_type);
48229727
JB		 4288 if (stub_sec == NULL)
4289 return NULL;
906e58ca
NC		 4290
4291 /* Enter this entry into the linker stub hash table. */
4292 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4293 TRUE, FALSE);
4294 if (stub_entry == NULL)
4295 {
6bde4c52
TP		 4296 if (section == NULL)
4297 section = stub_sec;
906e58ca
NC		 4298 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
4299 section->owner,
4300 stub_name);
4301 return NULL;
4302 }
4303
4304 stub_entry->stub_sec = stub_sec;
4305 stub_entry->stub_offset = 0;
4306 stub_entry->id_sec = link_sec;
4307
906e58ca
NC		 4308 return stub_entry;
4309}
4310
4311/* Store an Arm insn into an output section not processed by
4312 elf32_arm_write_section. */
4313
4314static void
8029a119
NC		 4315put_arm_insn (struct elf32_arm_link_hash_table * htab,
4316 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4317{
4318 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4319 bfd_putl32 (val, ptr);
4320 else
4321 bfd_putb32 (val, ptr);
4322}
4323
4324/* Store a 16-bit Thumb insn into an output section not processed by
4325 elf32_arm_write_section. */
4326
4327static void
8029a119
NC		 4328put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4329 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4330{
4331 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4332 bfd_putl16 (val, ptr);
4333 else
4334 bfd_putb16 (val, ptr);
4335}
4336
a504d23a
LA		 4337/* Store a Thumb2 insn into an output section not processed by
4338 elf32_arm_write_section. */
4339
4340static void
4341put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
b98e6871 4342 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
a504d23a
LA		 4343{
4344 /* T2 instructions are 16-bit streamed. */
4345 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4346 {
4347 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4348 bfd_putl16 ((val & 0xffff), ptr + 2);
4349 }
4350 else
4351 {
4352 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4353 bfd_putb16 ((val & 0xffff), ptr + 2);
4354 }
4355}
4356
0855e32b
NS		 4357/* If it's possible to change R_TYPE to a more efficient access
4358 model, return the new reloc type. */
4359
4360static unsigned
b38cadfb 4361elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4362 struct elf_link_hash_entry *h)
4363{
4364 int is_local = (h == NULL);
4365
0e1862bb
L		 4366 if (bfd_link_pic (info)
4367 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4368 return r_type;
4369
b38cadfb 4370 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4371 switch (r_type)
4372 {
4373 case R_ARM_TLS_GOTDESC:
4374 case R_ARM_TLS_CALL:
4375 case R_ARM_THM_TLS_CALL:
4376 case R_ARM_TLS_DESCSEQ:
4377 case R_ARM_THM_TLS_DESCSEQ:
4378 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4379 }
4380
4381 return r_type;
4382}
4383
48229727
JB		 4384static bfd_reloc_status_type elf32_arm_final_link_relocate
4385 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4386 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4387 const char *, unsigned char, enum arm_st_branch_type,
4388 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4389
4563a860
JB		 4390static unsigned int
4391arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4392{
4393 switch (stub_type)
4394 {
4395 case arm_stub_a8_veneer_b_cond:
4396 case arm_stub_a8_veneer_b:
4397 case arm_stub_a8_veneer_bl:
4398 return 2;
4399
4400 case arm_stub_long_branch_any_any:
4401 case arm_stub_long_branch_v4t_arm_thumb:
4402 case arm_stub_long_branch_thumb_only:
4403 case arm_stub_long_branch_v4t_thumb_thumb:
4404 case arm_stub_long_branch_v4t_thumb_arm:
4405 case arm_stub_short_branch_v4t_thumb_arm:
4406 case arm_stub_long_branch_any_arm_pic:
4407 case arm_stub_long_branch_any_thumb_pic:
4408 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4409 case arm_stub_long_branch_v4t_arm_thumb_pic:
4410 case arm_stub_long_branch_v4t_thumb_arm_pic:
4411 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4412 case arm_stub_long_branch_any_tls_pic:
4413 case arm_stub_long_branch_v4t_thumb_tls_pic:
4563a860
JB		 4414 case arm_stub_a8_veneer_blx:
4415 return 4;
b38cadfb 4416
7a89b94e
NC		 4417 case arm_stub_long_branch_arm_nacl:
4418 case arm_stub_long_branch_arm_nacl_pic:
4419 return 16;
4420
4563a860
JB		 4421 default:
4422 abort (); /* Should be unreachable. */
4423 }
4424}
4425
4f4faa4d
TP		 4426/* Returns whether stubs of type STUB_TYPE take over the symbol they are
4427 veneering (TRUE) or have their own symbol (FALSE). */
4428
4429static bfd_boolean
4430arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4431{
4432 if (stub_type >= max_stub_type)
4433 abort (); /* Should be unreachable. */
4434
4435 return FALSE;
4436}
4437
d7c5bd02
TP		 4438/* Returns the padding needed for the dedicated section used stubs of type
4439 STUB_TYPE. */
4440
4441static int
4442arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4443{
4444 if (stub_type >= max_stub_type)
4445 abort (); /* Should be unreachable. */
4446
4447 return 0;
4448}
4449
906e58ca
NC		 4450static bfd_boolean
4451arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4452 void * in_arg)
4453{
7a89b94e 4454#define MAXRELOCS 3
906e58ca 4455 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4456 struct elf32_arm_link_hash_table *globals;
906e58ca 4457 struct bfd_link_info *info;
906e58ca
NC		 4458 asection *stub_sec;
4459 bfd *stub_bfd;
906e58ca
NC		 4460 bfd_byte *loc;
4461 bfd_vma sym_value;
4462 int template_size;
4463 int size;
d3ce72d0 4464 const insn_sequence *template_sequence;
906e58ca 4465 int i;
48229727
JB		 4466 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4467 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4468 int nrelocs = 0;
906e58ca
NC		 4469
4470 /* Massage our args to the form they really have. */
4471 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4472 info = (struct bfd_link_info *) in_arg;
4473
4474 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4475 if (globals == NULL)
4476 return FALSE;
906e58ca 4477
906e58ca
NC		 4478 stub_sec = stub_entry->stub_sec;
4479
4dfe6ac6 4480 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4481 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4482 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4483 return TRUE;
fe33d2fa 4484
906e58ca
NC		 4485 /* Make a note of the offset within the stubs for this entry. */
4486 stub_entry->stub_offset = stub_sec->size;
4487 loc = stub_sec->contents + stub_entry->stub_offset;
4488
4489 stub_bfd = stub_sec->owner;
4490
906e58ca
NC		 4491 /* This is the address of the stub destination. */
4492 sym_value = (stub_entry->target_value
4493 + stub_entry->target_section->output_offset
4494 + stub_entry->target_section->output_section->vma);
4495
d3ce72d0 4496 template_sequence = stub_entry->stub_template;
461a49ca 4497 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4498
4499 size = 0;
461a49ca 4500 for (i = 0; i < template_size; i++)
906e58ca 4501 {
d3ce72d0 4502 switch (template_sequence[i].type)
461a49ca
DJ		 4503 {
4504 case THUMB16_TYPE:
48229727 4505 {
d3ce72d0
NC		 4506 bfd_vma data = (bfd_vma) template_sequence[i].data;
4507 if (template_sequence[i].reloc_addend != 0)
48229727 4508 {
99059e56
RM		 4509 /* We've borrowed the reloc_addend field to mean we should
4510 insert a condition code into this (Thumb-1 branch)
4511 instruction. See THUMB16_BCOND_INSN. */
4512 BFD_ASSERT ((data & 0xff00) == 0xd000);
4513 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4514 }
fe33d2fa 4515 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4516 size += 2;
4517 }
461a49ca 4518 break;
906e58ca 4519
48229727 4520 case THUMB32_TYPE:
fe33d2fa
CL		 4521 bfd_put_16 (stub_bfd,
4522 (template_sequence[i].data >> 16) & 0xffff,
4523 loc + size);
4524 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4525 loc + size + 2);
99059e56
RM		 4526 if (template_sequence[i].r_type != R_ARM_NONE)
4527 {
4528 stub_reloc_idx[nrelocs] = i;
4529 stub_reloc_offset[nrelocs++] = size;
4530 }
4531 size += 4;
4532 break;
48229727 4533
461a49ca 4534 case ARM_TYPE:
fe33d2fa
CL		 4535 bfd_put_32 (stub_bfd, template_sequence[i].data,
4536 loc + size);
461a49ca
DJ		 4537 /* Handle cases where the target is encoded within the
4538 instruction. */
d3ce72d0 4539 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4540 {
48229727
JB		 4541 stub_reloc_idx[nrelocs] = i;
4542 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4543 }
4544 size += 4;
4545 break;
4546
4547 case DATA_TYPE:
d3ce72d0 4548 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4549 stub_reloc_idx[nrelocs] = i;
4550 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4551 size += 4;
4552 break;
4553
4554 default:
4555 BFD_FAIL ();
4556 return FALSE;
4557 }
906e58ca 4558 }
461a49ca 4559
906e58ca
NC		 4560 stub_sec->size += size;
4561
461a49ca
DJ		 4562 /* Stub size has already been computed in arm_size_one_stub. Check
4563 consistency. */
4564 BFD_ASSERT (size == stub_entry->stub_size);
4565
906e58ca 4566 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4567 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4568 sym_value |= 1;
4569
48229727
JB		 4570 /* Assume there is at least one and at most MAXRELOCS entries to relocate
4571 in each stub. */
4572 BFD_ASSERT (nrelocs != 0 && nrelocs <= MAXRELOCS);
c820be07 4573
48229727 4574 for (i = 0; i < nrelocs; i++)
8d9d9490
TP		 4575 {
4576 Elf_Internal_Rela rel;
4577 bfd_boolean unresolved_reloc;
4578 char *error_message;
4579 bfd_vma points_to =
4580 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
4581
4582 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4583 rel.r_info = ELF32_R_INFO (0,
4584 template_sequence[stub_reloc_idx[i]].r_type);
4585 rel.r_addend = 0;
4586
4587 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4588 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4589 template should refer back to the instruction after the original
4590 branch. We use target_section as Cortex-A8 erratum workaround stubs
4591 are only generated when both source and target are in the same
4592 section. */
4593 points_to = stub_entry->target_section->output_section->vma
4594 + stub_entry->target_section->output_offset
4595 + stub_entry->source_value;
4596
4597 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4598 (template_sequence[stub_reloc_idx[i]].r_type),
4599 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
4600 points_to, info, stub_entry->target_section, "", STT_FUNC,
4601 stub_entry->branch_type,
4602 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4603 &error_message);
4604 }
906e58ca
NC		 4605
4606 return TRUE;
48229727 4607#undef MAXRELOCS
906e58ca
NC		 4608}
4609
48229727
JB		 4610/* Calculate the template, template size and instruction size for a stub.
4611 Return value is the instruction size. */
906e58ca 4612
48229727
JB		 4613static unsigned int
4614find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4615 const insn_sequence **stub_template,
4616 int *stub_template_size)
906e58ca 4617{
d3ce72d0 4618 const insn_sequence *template_sequence = NULL;
48229727
JB		 4619 int template_size = 0, i;
4620 unsigned int size;
906e58ca 4621
d3ce72d0 4622 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4623 if (stub_template)
4624 *stub_template = template_sequence;
4625
48229727 4626 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4627 if (stub_template_size)
4628 *stub_template_size = template_size;
906e58ca
NC		 4629
4630 size = 0;
461a49ca
DJ		 4631 for (i = 0; i < template_size; i++)
4632 {
d3ce72d0 4633 switch (template_sequence[i].type)
461a49ca
DJ		 4634 {
4635 case THUMB16_TYPE:
4636 size += 2;
4637 break;
4638
4639 case ARM_TYPE:
48229727 4640 case THUMB32_TYPE:
461a49ca
DJ		 4641 case DATA_TYPE:
4642 size += 4;
4643 break;
4644
4645 default:
4646 BFD_FAIL ();
2a229407 4647 return 0;
461a49ca
DJ		 4648 }
4649 }
4650
48229727
JB		 4651 return size;
4652}
4653
4654/* As above, but don't actually build the stub. Just bump offset so
4655 we know stub section sizes. */
4656
4657static bfd_boolean
4658arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4659 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4660{
4661 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4662 const insn_sequence *template_sequence;
48229727
JB		 4663 int template_size, size;
4664
4665 /* Massage our args to the form they really have. */
4666 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4667
4668 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4669 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4670
d3ce72d0 4671 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4672 &template_size);
4673
461a49ca 4674 stub_entry->stub_size = size;
d3ce72d0 4675 stub_entry->stub_template = template_sequence;
461a49ca
DJ		 4676 stub_entry->stub_template_size = template_size;
4677
906e58ca
NC		 4678 size = (size + 7) & ~7;
4679 stub_entry->stub_sec->size += size;
461a49ca 4680
906e58ca
NC		 4681 return TRUE;
4682}
4683
4684/* External entry points for sizing and building linker stubs. */
4685
4686/* Set up various things so that we can make a list of input sections
4687 for each output section included in the link. Returns -1 on error,
4688 0 when no stubs will be needed, and 1 on success. */
4689
4690int
4691elf32_arm_setup_section_lists (bfd *output_bfd,
4692 struct bfd_link_info *info)
4693{
4694 bfd *input_bfd;
4695 unsigned int bfd_count;
7292b3ac 4696 unsigned int top_id, top_index;
906e58ca
NC		 4697 asection *section;
4698 asection **input_list, **list;
4699 bfd_size_type amt;
4700 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4701
4dfe6ac6
NC		 4702 if (htab == NULL)
4703 return 0;
906e58ca
NC		 4704 if (! is_elf_hash_table (htab))
4705 return 0;
4706
4707 /* Count the number of input BFDs and find the top input section id. */
4708 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
4709 input_bfd != NULL;
c72f2fb2 4710 input_bfd = input_bfd->link.next)
906e58ca
NC		 4711 {
4712 bfd_count += 1;
4713 for (section = input_bfd->sections;
4714 section != NULL;
4715 section = section->next)
4716 {
4717 if (top_id < section->id)
4718 top_id = section->id;
4719 }
4720 }
4721 htab->bfd_count = bfd_count;
4722
4723 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 4724 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 4725 if (htab->stub_group == NULL)
4726 return -1;
fe33d2fa 4727 htab->top_id = top_id;
906e58ca
NC		 4728
4729 /* We can't use output_bfd->section_count here to find the top output
4730 section index as some sections may have been removed, and
4731 _bfd_strip_section_from_output doesn't renumber the indices. */
4732 for (section = output_bfd->sections, top_index = 0;
4733 section != NULL;
4734 section = section->next)
4735 {
4736 if (top_index < section->index)
4737 top_index = section->index;
4738 }
4739
4740 htab->top_index = top_index;
4741 amt = sizeof (asection *) * (top_index + 1);
21d799b5 4742 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 4743 htab->input_list = input_list;
4744 if (input_list == NULL)
4745 return -1;
4746
4747 /* For sections we aren't interested in, mark their entries with a
4748 value we can check later. */
4749 list = input_list + top_index;
4750 do
4751 *list = bfd_abs_section_ptr;
4752 while (list-- != input_list);
4753
4754 for (section = output_bfd->sections;
4755 section != NULL;
4756 section = section->next)
4757 {
4758 if ((section->flags & SEC_CODE) != 0)
4759 input_list[section->index] = NULL;
4760 }
4761
4762 return 1;
4763}
4764
4765/* The linker repeatedly calls this function for each input section,
4766 in the order that input sections are linked into output sections.
4767 Build lists of input sections to determine groupings between which
4768 we may insert linker stubs. */
4769
4770void
4771elf32_arm_next_input_section (struct bfd_link_info *info,
4772 asection *isec)
4773{
4774 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4775
4dfe6ac6
NC		 4776 if (htab == NULL)
4777 return;
4778
906e58ca
NC		 4779 if (isec->output_section->index <= htab->top_index)
4780 {
4781 asection **list = htab->input_list + isec->output_section->index;
4782
a7470592 4783 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 4784 {
4785 /* Steal the link_sec pointer for our list. */
4786#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
4787 /* This happens to make the list in reverse order,
07d72278 4788 which we reverse later. */
906e58ca
NC		 4789 PREV_SEC (isec) = *list;
4790 *list = isec;
4791 }
4792 }
4793}
4794
4795/* See whether we can group stub sections together. Grouping stub
4796 sections may result in fewer stubs. More importantly, we need to
07d72278 4797 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 4798 .fini output sections respectively, because glibc splits the
4799 _init and _fini functions into multiple parts. Putting a stub in
4800 the middle of a function is not a good idea. */
4801
4802static void
4803group_sections (struct elf32_arm_link_hash_table *htab,
4804 bfd_size_type stub_group_size,
07d72278 4805 bfd_boolean stubs_always_after_branch)
906e58ca 4806{
07d72278 4807 asection **list = htab->input_list;
906e58ca
NC		 4808
4809 do
4810 {
4811 asection *tail = *list;
07d72278 4812 asection *head;
906e58ca
NC		 4813
4814 if (tail == bfd_abs_section_ptr)
4815 continue;
4816
07d72278
DJ		 4817 /* Reverse the list: we must avoid placing stubs at the
4818 beginning of the section because the beginning of the text
4819 section may be required for an interrupt vector in bare metal
4820 code. */
4821#define NEXT_SEC PREV_SEC
e780aef2
CL		 4822 head = NULL;
4823 while (tail != NULL)
99059e56
RM		 4824 {
4825 /* Pop from tail. */
4826 asection *item = tail;
4827 tail = PREV_SEC (item);
e780aef2 4828
99059e56
RM		 4829 /* Push on head. */
4830 NEXT_SEC (item) = head;
4831 head = item;
4832 }
07d72278
DJ		 4833
4834 while (head != NULL)
906e58ca
NC		 4835 {
4836 asection *curr;
07d72278 4837 asection *next;
e780aef2
CL		 4838 bfd_vma stub_group_start = head->output_offset;
4839 bfd_vma end_of_next;
906e58ca 4840
07d72278 4841 curr = head;
e780aef2 4842 while (NEXT_SEC (curr) != NULL)
8cd931b7 4843 {
e780aef2
CL		 4844 next = NEXT_SEC (curr);
4845 end_of_next = next->output_offset + next->size;
4846 if (end_of_next - stub_group_start >= stub_group_size)
4847 /* End of NEXT is too far from start, so stop. */
8cd931b7 4848 break;
e780aef2
CL		 4849 /* Add NEXT to the group. */
4850 curr = next;
8cd931b7 4851 }
906e58ca 4852
07d72278 4853 /* OK, the size from the start to the start of CURR is less
906e58ca 4854 than stub_group_size and thus can be handled by one stub
07d72278 4855 section. (Or the head section is itself larger than
906e58ca
NC		 4856 stub_group_size, in which case we may be toast.)
4857 We should really be keeping track of the total size of
4858 stubs added here, as stubs contribute to the final output
7fb9f789 4859 section size. */
906e58ca
NC		 4860 do
4861 {
07d72278 4862 next = NEXT_SEC (head);
906e58ca 4863 /* Set up this stub group. */
07d72278 4864 htab->stub_group[head->id].link_sec = curr;
906e58ca 4865 }
07d72278 4866 while (head != curr && (head = next) != NULL);
906e58ca
NC		 4867
4868 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 4869 bytes after the stub section can be handled by it too. */
4870 if (!stubs_always_after_branch)
906e58ca 4871 {
e780aef2
CL		 4872 stub_group_start = curr->output_offset + curr->size;
4873
8cd931b7 4874 while (next != NULL)
906e58ca 4875 {
e780aef2
CL		 4876 end_of_next = next->output_offset + next->size;
4877 if (end_of_next - stub_group_start >= stub_group_size)
4878 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 4879 break;
e780aef2 4880 /* Add NEXT to the stub group. */
07d72278
DJ		 4881 head = next;
4882 next = NEXT_SEC (head);
4883 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 4884 }
4885 }
07d72278 4886 head = next;
906e58ca
NC		 4887 }
4888 }
07d72278 4889 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 4890
4891 free (htab->input_list);
4892#undef PREV_SEC
07d72278 4893#undef NEXT_SEC
906e58ca
NC		 4894}
4895
48229727
JB		 4896/* Comparison function for sorting/searching relocations relating to Cortex-A8
4897 erratum fix. */
4898
4899static int
4900a8_reloc_compare (const void *a, const void *b)
4901{
21d799b5
NC		 4902 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
4903 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 4904
4905 if (ra->from < rb->from)
4906 return -1;
4907 else if (ra->from > rb->from)
4908 return 1;
4909 else
4910 return 0;
4911}
4912
4913static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
4914 const char *, char **);
4915
4916/* Helper function to scan code for sequences which might trigger the Cortex-A8
4917 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 4918 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 4919 otherwise. */
4920
81694485
NC		 4921static bfd_boolean
4922cortex_a8_erratum_scan (bfd *input_bfd,
4923 struct bfd_link_info *info,
48229727
JB		 4924 struct a8_erratum_fix **a8_fixes_p,
4925 unsigned int *num_a8_fixes_p,
4926 unsigned int *a8_fix_table_size_p,
4927 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 4928 unsigned int num_a8_relocs,
4929 unsigned prev_num_a8_fixes,
4930 bfd_boolean *stub_changed_p)
48229727
JB		 4931{
4932 asection *section;
4933 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4934 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
4935 unsigned int num_a8_fixes = *num_a8_fixes_p;
4936 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
4937
4dfe6ac6
NC		 4938 if (htab == NULL)
4939 return FALSE;
4940
48229727
JB		 4941 for (section = input_bfd->sections;
4942 section != NULL;
4943 section = section->next)
4944 {
4945 bfd_byte *contents = NULL;
4946 struct _arm_elf_section_data *sec_data;
4947 unsigned int span;
4948 bfd_vma base_vma;
4949
4950 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 4951 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
4952 || (section->flags & SEC_EXCLUDE) != 0
4953 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
4954 || (section->output_section == bfd_abs_section_ptr))
4955 continue;
48229727
JB		 4956
4957 base_vma = section->output_section->vma + section->output_offset;
4958
4959 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 4960 contents = elf_section_data (section)->this_hdr.contents;
48229727 4961 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 4962 return TRUE;
48229727
JB		 4963
4964 sec_data = elf32_arm_section_data (section);
4965
4966 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 4967 {
4968 unsigned int span_start = sec_data->map[span].vma;
4969 unsigned int span_end = (span == sec_data->mapcount - 1)
4970 ? section->size : sec_data->map[span + 1].vma;
4971 unsigned int i;
4972 char span_type = sec_data->map[span].type;
4973 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
4974
4975 if (span_type != 't')
4976 continue;
4977
4978 /* Span is entirely within a single 4KB region: skip scanning. */
4979 if (((base_vma + span_start) & ~0xfff)
48229727 4980 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 4981 continue;
4982
4983 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
4984
4985 * The opcode is BLX.W, BL.W, B.W, Bcc.W
4986 * The branch target is in the same 4KB region as the
4987 first half of the branch.
4988 * The instruction before the branch is a 32-bit
4989 length non-branch instruction. */
4990 for (i = span_start; i < span_end;)
4991 {
4992 unsigned int insn = bfd_getl16 (&contents[i]);
4993 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 4994 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
4995
99059e56
RM		 4996 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
4997 insn_32bit = TRUE;
48229727
JB		 4998
4999 if (insn_32bit)
99059e56
RM		 5000 {
5001 /* Load the rest of the insn (in manual-friendly order). */
5002 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5003
5004 /* Encoding T4: B<c>.W. */
5005 is_b = (insn & 0xf800d000) == 0xf0009000;
5006 /* Encoding T1: BL<c>.W. */
5007 is_bl = (insn & 0xf800d000) == 0xf000d000;
5008 /* Encoding T2: BLX<c>.W. */
5009 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 5010 /* Encoding T3: B<c>.W (not permitted in IT block). */
5011 is_bcc = (insn & 0xf800d000) == 0xf0008000
5012 && (insn & 0x07f00000) != 0x03800000;
5013 }
5014
5015 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 5016
99059e56 5017 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 5018 && insn_32bit
5019 && is_32bit_branch
5020 && last_was_32bit
5021 && ! last_was_branch)
99059e56
RM		 5022 {
5023 bfd_signed_vma offset = 0;
5024 bfd_boolean force_target_arm = FALSE;
48229727 5025 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 5026 bfd_vma target;
5027 enum elf32_arm_stub_type stub_type = arm_stub_none;
5028 struct a8_erratum_reloc key, *found;
5029 bfd_boolean use_plt = FALSE;
48229727 5030
99059e56
RM		 5031 key.from = base_vma + i;
5032 found = (struct a8_erratum_reloc *)
5033 bsearch (&key, a8_relocs, num_a8_relocs,
5034 sizeof (struct a8_erratum_reloc),
5035 &a8_reloc_compare);
48229727
JB		 5036
5037 if (found)
5038 {
5039 char *error_message = NULL;
5040 struct elf_link_hash_entry *entry;
5041
5042 /* We don't care about the error returned from this
99059e56 5043 function, only if there is glue or not. */
48229727
JB		 5044 entry = find_thumb_glue (info, found->sym_name,
5045 &error_message);
5046
5047 if (entry)
5048 found->non_a8_stub = TRUE;
5049
92750f34 5050 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 5051 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 5052 && found->hash->root.plt.offset != (bfd_vma) -1)
5053 use_plt = TRUE;
5054
5055 if (found->r_type == R_ARM_THM_CALL)
5056 {
35fc36a8
RS		 5057 if (found->branch_type == ST_BRANCH_TO_ARM
5058 || use_plt)
92750f34
DJ		 5059 force_target_arm = TRUE;
5060 else
5061 force_target_thumb = TRUE;
5062 }
48229727
JB		 5063 }
5064
99059e56 5065 /* Check if we have an offending branch instruction. */
48229727
JB		 5066
5067 if (found && found->non_a8_stub)
5068 /* We've already made a stub for this instruction, e.g.
5069 it's a long branch or a Thumb->ARM stub. Assume that
5070 stub will suffice to work around the A8 erratum (see
5071 setting of always_after_branch above). */
5072 ;
99059e56
RM		 5073 else if (is_bcc)
5074 {
5075 offset = (insn & 0x7ff) << 1;
5076 offset |= (insn & 0x3f0000) >> 4;
5077 offset |= (insn & 0x2000) ? 0x40000 : 0;
5078 offset |= (insn & 0x800) ? 0x80000 : 0;
5079 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5080 if (offset & 0x100000)
5081 offset |= ~ ((bfd_signed_vma) 0xfffff);
5082 stub_type = arm_stub_a8_veneer_b_cond;
5083 }
5084 else if (is_b || is_bl || is_blx)
5085 {
5086 int s = (insn & 0x4000000) != 0;
5087 int j1 = (insn & 0x2000) != 0;
5088 int j2 = (insn & 0x800) != 0;
5089 int i1 = !(j1 ^ s);
5090 int i2 = !(j2 ^ s);
5091
5092 offset = (insn & 0x7ff) << 1;
5093 offset |= (insn & 0x3ff0000) >> 4;
5094 offset |= i2 << 22;
5095 offset |= i1 << 23;
5096 offset |= s << 24;
5097 if (offset & 0x1000000)
5098 offset |= ~ ((bfd_signed_vma) 0xffffff);
5099
5100 if (is_blx)
5101 offset &= ~ ((bfd_signed_vma) 3);
5102
5103 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5104 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5105 }
5106
5107 if (stub_type != arm_stub_none)
5108 {
5109 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5110
5111 /* The original instruction is a BL, but the target is
99059e56 5112 an ARM instruction. If we were not making a stub,
48229727
JB		 5113 the BL would have been converted to a BLX. Use the
5114 BLX stub instead in that case. */
5115 if (htab->use_blx && force_target_arm
5116 && stub_type == arm_stub_a8_veneer_bl)
5117 {
5118 stub_type = arm_stub_a8_veneer_blx;
5119 is_blx = TRUE;
5120 is_bl = FALSE;
5121 }
5122 /* Conversely, if the original instruction was
5123 BLX but the target is Thumb mode, use the BL
5124 stub. */
5125 else if (force_target_thumb
5126 && stub_type == arm_stub_a8_veneer_blx)
5127 {
5128 stub_type = arm_stub_a8_veneer_bl;
5129 is_blx = FALSE;
5130 is_bl = TRUE;
5131 }
5132
99059e56
RM		 5133 if (is_blx)
5134 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5135
99059e56
RM		 5136 /* If we found a relocation, use the proper destination,
5137 not the offset in the (unrelocated) instruction.
48229727
JB		 5138 Note this is always done if we switched the stub type
5139 above. */
99059e56
RM		 5140 if (found)
5141 offset =
81694485 5142 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5143
99059e56
RM		 5144 /* If the stub will use a Thumb-mode branch to a
5145 PLT target, redirect it to the preceding Thumb
5146 entry point. */
5147 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5148 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5149
99059e56 5150 target = pc_for_insn + offset;
48229727 5151
99059e56
RM		 5152 /* The BLX stub is ARM-mode code. Adjust the offset to
5153 take the different PC value (+8 instead of +4) into
48229727 5154 account. */
99059e56
RM		 5155 if (stub_type == arm_stub_a8_veneer_blx)
5156 offset += 4;
5157
5158 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5159 {
5160 char *stub_name = NULL;
5161
5162 if (num_a8_fixes == a8_fix_table_size)
5163 {
5164 a8_fix_table_size *= 2;
5165 a8_fixes = (struct a8_erratum_fix *)
5166 bfd_realloc (a8_fixes,
5167 sizeof (struct a8_erratum_fix)
5168 * a8_fix_table_size);
5169 }
48229727 5170
eb7c4339
NS		 5171 if (num_a8_fixes < prev_num_a8_fixes)
5172 {
5173 /* If we're doing a subsequent scan,
5174 check if we've found the same fix as
5175 before, and try and reuse the stub
5176 name. */
5177 stub_name = a8_fixes[num_a8_fixes].stub_name;
5178 if ((a8_fixes[num_a8_fixes].section != section)
5179 || (a8_fixes[num_a8_fixes].offset != i))
5180 {
5181 free (stub_name);
5182 stub_name = NULL;
5183 *stub_changed_p = TRUE;
5184 }
5185 }
5186
5187 if (!stub_name)
5188 {
21d799b5 5189 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5190 if (stub_name != NULL)
5191 sprintf (stub_name, "%x:%x", section->id, i);
5192 }
48229727 5193
99059e56
RM		 5194 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5195 a8_fixes[num_a8_fixes].section = section;
5196 a8_fixes[num_a8_fixes].offset = i;
8d9d9490
TP		 5197 a8_fixes[num_a8_fixes].target_offset =
5198 target - base_vma;
99059e56
RM		 5199 a8_fixes[num_a8_fixes].orig_insn = insn;
5200 a8_fixes[num_a8_fixes].stub_name = stub_name;
5201 a8_fixes[num_a8_fixes].stub_type = stub_type;
5202 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5203 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5204
99059e56
RM		 5205 num_a8_fixes++;
5206 }
5207 }
5208 }
48229727 5209
99059e56
RM		 5210 i += insn_32bit ? 4 : 2;
5211 last_was_32bit = insn_32bit;
48229727 5212 last_was_branch = is_32bit_branch;
99059e56
RM		 5213 }
5214 }
48229727
JB		 5215
5216 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5217 free (contents);
48229727 5218 }
fe33d2fa 5219
48229727
JB		 5220 *a8_fixes_p = a8_fixes;
5221 *num_a8_fixes_p = num_a8_fixes;
5222 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5223
81694485 5224 return FALSE;
48229727
JB		 5225}
5226
b715f643
TP		 5227/* Create or update a stub entry depending on whether the stub can already be
5228 found in HTAB. The stub is identified by:
5229 - its type STUB_TYPE
5230 - its source branch (note that several can share the same stub) whose
5231 section and relocation (if any) are given by SECTION and IRELA
5232 respectively
5233 - its target symbol whose input section, hash, name, value and branch type
5234 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5235 respectively
5236
5237 If found, the value of the stub's target symbol is updated from SYM_VALUE
5238 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5239 TRUE and the stub entry is initialized.
5240
5241 Returns whether the stub could be successfully created or updated, or FALSE
5242 if an error occured. */
5243
5244static bfd_boolean
5245elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5246 enum elf32_arm_stub_type stub_type, asection *section,
5247 Elf_Internal_Rela *irela, asection *sym_sec,
5248 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5249 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5250 bfd_boolean *new_stub)
5251{
5252 const asection *id_sec;
5253 char *stub_name;
5254 struct elf32_arm_stub_hash_entry *stub_entry;
5255 unsigned int r_type;
4f4faa4d 5256 bfd_boolean sym_claimed = arm_stub_sym_claimed (stub_type);
b715f643
TP		 5257
5258 BFD_ASSERT (stub_type != arm_stub_none);
5259 *new_stub = FALSE;
5260
4f4faa4d
TP		 5261 if (sym_claimed)
5262 stub_name = sym_name;
5263 else
5264 {
5265 BFD_ASSERT (irela);
5266 BFD_ASSERT (section);
b715f643 5267
4f4faa4d
TP		 5268 /* Support for grouping stub sections. */
5269 id_sec = htab->stub_group[section->id].link_sec;
b715f643 5270
4f4faa4d
TP		 5271 /* Get the name of this stub. */
5272 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5273 stub_type);
5274 if (!stub_name)
5275 return FALSE;
5276 }
b715f643
TP		 5277
5278 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, FALSE,
5279 FALSE);
5280 /* The proper stub has already been created, just update its value. */
5281 if (stub_entry != NULL)
5282 {
4f4faa4d
TP		 5283 if (!sym_claimed)
5284 free (stub_name);
b715f643
TP		 5285 stub_entry->target_value = sym_value;
5286 return TRUE;
5287 }
5288
daa4adae 5289 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
b715f643
TP		 5290 if (stub_entry == NULL)
5291 {
4f4faa4d
TP		 5292 if (!sym_claimed)
5293 free (stub_name);
b715f643
TP		 5294 return FALSE;
5295 }
5296
5297 stub_entry->target_value = sym_value;
5298 stub_entry->target_section = sym_sec;
5299 stub_entry->stub_type = stub_type;
5300 stub_entry->h = hash;
5301 stub_entry->branch_type = branch_type;
5302
4f4faa4d
TP		 5303 if (sym_claimed)
5304 stub_entry->output_name = sym_name;
5305 else
b715f643 5306 {
4f4faa4d
TP		 5307 if (sym_name == NULL)
5308 sym_name = "unnamed";
5309 stub_entry->output_name = (char *)
5310 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5311 + strlen (sym_name));
5312 if (stub_entry->output_name == NULL)
5313 {
5314 free (stub_name);
5315 return FALSE;
5316 }
b715f643 5317
4f4faa4d
TP		 5318 /* For historical reasons, use the existing names for ARM-to-Thumb and
5319 Thumb-to-ARM stubs. */
5320 r_type = ELF32_R_TYPE (irela->r_info);
5321 if ((r_type == (unsigned int) R_ARM_THM_CALL
5322 || r_type == (unsigned int) R_ARM_THM_JUMP24
5323 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5324 && branch_type == ST_BRANCH_TO_ARM)
5325 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5326 else if ((r_type == (unsigned int) R_ARM_CALL
5327 || r_type == (unsigned int) R_ARM_JUMP24)
5328 && branch_type == ST_BRANCH_TO_THUMB)
5329 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5330 else
5331 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5332 }
b715f643
TP		 5333
5334 *new_stub = TRUE;
5335 return TRUE;
5336}
5337
906e58ca
NC		 5338/* Determine and set the size of the stub section for a final link.
5339
5340 The basic idea here is to examine all the relocations looking for
5341 PC-relative calls to a target that is unreachable with a "bl"
5342 instruction. */
5343
5344bfd_boolean
5345elf32_arm_size_stubs (bfd *output_bfd,
5346 bfd *stub_bfd,
5347 struct bfd_link_info *info,
5348 bfd_signed_vma group_size,
7a89b94e 5349 asection * (*add_stub_section) (const char *, asection *,
6bde4c52 5350 asection *,
7a89b94e 5351 unsigned int),
906e58ca
NC		 5352 void (*layout_sections_again) (void))
5353{
5354 bfd_size_type stub_group_size;
07d72278 5355 bfd_boolean stubs_always_after_branch;
906e58ca 5356 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 5357 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 5358 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 5359 struct a8_erratum_reloc *a8_relocs = NULL;
5360 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
5361
4dfe6ac6
NC		 5362 if (htab == NULL)
5363 return FALSE;
5364
48229727
JB		 5365 if (htab->fix_cortex_a8)
5366 {
21d799b5 5367 a8_fixes = (struct a8_erratum_fix *)
99059e56 5368 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 5369 a8_relocs = (struct a8_erratum_reloc *)
99059e56 5370 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 5371 }
906e58ca
NC		 5372
5373 /* Propagate mach to stub bfd, because it may not have been
5374 finalized when we created stub_bfd. */
5375 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
5376 bfd_get_mach (output_bfd));
5377
5378 /* Stash our params away. */
5379 htab->stub_bfd = stub_bfd;
5380 htab->add_stub_section = add_stub_section;
5381 htab->layout_sections_again = layout_sections_again;
07d72278 5382 stubs_always_after_branch = group_size < 0;
48229727
JB		 5383
5384 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
5385 as the first half of a 32-bit branch straddling two 4K pages. This is a
5386 crude way of enforcing that. */
5387 if (htab->fix_cortex_a8)
5388 stubs_always_after_branch = 1;
5389
906e58ca
NC		 5390 if (group_size < 0)
5391 stub_group_size = -group_size;
5392 else
5393 stub_group_size = group_size;
5394
5395 if (stub_group_size == 1)
5396 {
5397 /* Default values. */
5398 /* Thumb branch range is +-4MB has to be used as the default
5399 maximum size (a given section can contain both ARM and Thumb
5400 code, so the worst case has to be taken into account).
5401
5402 This value is 24K less than that, which allows for 2025
5403 12-byte stubs. If we exceed that, then we will fail to link.
5404 The user will have to relink with an explicit group size
5405 option. */
5406 stub_group_size = 4170000;
5407 }
5408
07d72278 5409 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 5410
3ae046cc
NS		 5411 /* If we're applying the cortex A8 fix, we need to determine the
5412 program header size now, because we cannot change it later --
5413 that could alter section placements. Notice the A8 erratum fix
5414 ends up requiring the section addresses to remain unchanged
5415 modulo the page size. That's something we cannot represent
5416 inside BFD, and we don't want to force the section alignment to
5417 be the page size. */
5418 if (htab->fix_cortex_a8)
5419 (*htab->layout_sections_again) ();
5420
906e58ca
NC		 5421 while (1)
5422 {
5423 bfd *input_bfd;
5424 unsigned int bfd_indx;
5425 asection *stub_sec;
d7c5bd02 5426 enum elf32_arm_stub_type stub_type;
eb7c4339
NS		 5427 bfd_boolean stub_changed = FALSE;
5428 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 5429
48229727 5430 num_a8_fixes = 0;
906e58ca
NC		 5431 for (input_bfd = info->input_bfds, bfd_indx = 0;
5432 input_bfd != NULL;
c72f2fb2 5433 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 5434 {
5435 Elf_Internal_Shdr *symtab_hdr;
5436 asection *section;
5437 Elf_Internal_Sym *local_syms = NULL;
5438
99059e56
RM		 5439 if (!is_arm_elf (input_bfd))
5440 continue;
adbcc655 5441
48229727
JB		 5442 num_a8_relocs = 0;
5443
906e58ca
NC		 5444 /* We'll need the symbol table in a second. */
5445 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5446 if (symtab_hdr->sh_info == 0)
5447 continue;
5448
5449 /* Walk over each section attached to the input bfd. */
5450 for (section = input_bfd->sections;
5451 section != NULL;
5452 section = section->next)
5453 {
5454 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
5455
5456 /* If there aren't any relocs, then there's nothing more
5457 to do. */
5458 if ((section->flags & SEC_RELOC) == 0
5459 || section->reloc_count == 0
5460 || (section->flags & SEC_CODE) == 0)
5461 continue;
5462
5463 /* If this section is a link-once section that will be
5464 discarded, then don't create any stubs. */
5465 if (section->output_section == NULL
5466 || section->output_section->owner != output_bfd)
5467 continue;
5468
5469 /* Get the relocs. */
5470 internal_relocs
5471 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
5472 NULL, info->keep_memory);
5473 if (internal_relocs == NULL)
5474 goto error_ret_free_local;
5475
5476 /* Now examine each relocation. */
5477 irela = internal_relocs;
5478 irelaend = irela + section->reloc_count;
5479 for (; irela < irelaend; irela++)
5480 {
5481 unsigned int r_type, r_indx;
906e58ca
NC		 5482 asection *sym_sec;
5483 bfd_vma sym_value;
5484 bfd_vma destination;
5485 struct elf32_arm_link_hash_entry *hash;
7413f23f 5486 const char *sym_name;
34e77a92 5487 unsigned char st_type;
35fc36a8 5488 enum arm_st_branch_type branch_type;
48229727 5489 bfd_boolean created_stub = FALSE;
906e58ca
NC		 5490
5491 r_type = ELF32_R_TYPE (irela->r_info);
5492 r_indx = ELF32_R_SYM (irela->r_info);
5493
5494 if (r_type >= (unsigned int) R_ARM_max)
5495 {
5496 bfd_set_error (bfd_error_bad_value);
5497 error_ret_free_internal:
5498 if (elf_section_data (section)->relocs == NULL)
5499 free (internal_relocs);
15dd01b1
TP		 5500 /* Fall through. */
5501 error_ret_free_local:
5502 if (local_syms != NULL
5503 && (symtab_hdr->contents
5504 != (unsigned char *) local_syms))
5505 free (local_syms);
5506 return FALSE;
906e58ca 5507 }
b38cadfb 5508
0855e32b
NS		 5509 hash = NULL;
5510 if (r_indx >= symtab_hdr->sh_info)
5511 hash = elf32_arm_hash_entry
5512 (elf_sym_hashes (input_bfd)
5513 [r_indx - symtab_hdr->sh_info]);
b38cadfb 5514
0855e32b
NS		 5515 /* Only look for stubs on branch instructions, or
5516 non-relaxed TLSCALL */
906e58ca 5517 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 5518 && (r_type != (unsigned int) R_ARM_THM_CALL)
5519 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 5520 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
5521 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 5522 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 5523 && (r_type != (unsigned int) R_ARM_PLT32)
5524 && !((r_type == (unsigned int) R_ARM_TLS_CALL
5525 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
5526 && r_type == elf32_arm_tls_transition
5527 (info, r_type, &hash->root)
5528 && ((hash ? hash->tls_type
5529 : (elf32_arm_local_got_tls_type
5530 (input_bfd)[r_indx]))
5531 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 5532 continue;
5533
5534 /* Now determine the call target, its name, value,
5535 section. */
5536 sym_sec = NULL;
5537 sym_value = 0;
5538 destination = 0;
7413f23f 5539 sym_name = NULL;
b38cadfb 5540
0855e32b
NS		 5541 if (r_type == (unsigned int) R_ARM_TLS_CALL
5542 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
5543 {
5544 /* A non-relaxed TLS call. The target is the
5545 plt-resident trampoline and nothing to do
5546 with the symbol. */
5547 BFD_ASSERT (htab->tls_trampoline > 0);
5548 sym_sec = htab->root.splt;
5549 sym_value = htab->tls_trampoline;
5550 hash = 0;
34e77a92 5551 st_type = STT_FUNC;
35fc36a8 5552 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 5553 }
5554 else if (!hash)
906e58ca
NC		 5555 {
5556 /* It's a local symbol. */
5557 Elf_Internal_Sym *sym;
906e58ca
NC		 5558
5559 if (local_syms == NULL)
5560 {
5561 local_syms
5562 = (Elf_Internal_Sym *) symtab_hdr->contents;
5563 if (local_syms == NULL)
5564 local_syms
5565 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5566 symtab_hdr->sh_info, 0,
5567 NULL, NULL, NULL);
5568 if (local_syms == NULL)
5569 goto error_ret_free_internal;
5570 }
5571
5572 sym = local_syms + r_indx;
f6d250ce
TS		 5573 if (sym->st_shndx == SHN_UNDEF)
5574 sym_sec = bfd_und_section_ptr;
5575 else if (sym->st_shndx == SHN_ABS)
5576 sym_sec = bfd_abs_section_ptr;
5577 else if (sym->st_shndx == SHN_COMMON)
5578 sym_sec = bfd_com_section_ptr;
5579 else
5580 sym_sec =
5581 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
5582
ffcb4889
NS		 5583 if (!sym_sec)
5584 /* This is an undefined symbol. It can never
6a631e86 5585 be resolved. */
ffcb4889 5586 continue;
fe33d2fa 5587
906e58ca
NC		 5588 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
5589 sym_value = sym->st_value;
5590 destination = (sym_value + irela->r_addend
5591 + sym_sec->output_offset
5592 + sym_sec->output_section->vma);
34e77a92 5593 st_type = ELF_ST_TYPE (sym->st_info);
39d911fc
TP		 5594 branch_type =
5595 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
7413f23f
DJ		 5596 sym_name
5597 = bfd_elf_string_from_elf_section (input_bfd,
5598 symtab_hdr->sh_link,
5599 sym->st_name);
906e58ca
NC		 5600 }
5601 else
5602 {
5603 /* It's an external symbol. */
906e58ca
NC		 5604 while (hash->root.root.type == bfd_link_hash_indirect
5605 || hash->root.root.type == bfd_link_hash_warning)
5606 hash = ((struct elf32_arm_link_hash_entry *)
5607 hash->root.root.u.i.link);
5608
5609 if (hash->root.root.type == bfd_link_hash_defined
5610 || hash->root.root.type == bfd_link_hash_defweak)
5611 {
5612 sym_sec = hash->root.root.u.def.section;
5613 sym_value = hash->root.root.u.def.value;
022f8312
CL		 5614
5615 struct elf32_arm_link_hash_table *globals =
5616 elf32_arm_hash_table (info);
5617
5618 /* For a destination in a shared library,
5619 use the PLT stub as target address to
5620 decide whether a branch stub is
5621 needed. */
4dfe6ac6 5622 if (globals != NULL
362d30a1 5623 && globals->root.splt != NULL
4dfe6ac6 5624 && hash != NULL
022f8312
CL		 5625 && hash->root.plt.offset != (bfd_vma) -1)
5626 {
362d30a1 5627 sym_sec = globals->root.splt;
022f8312
CL		 5628 sym_value = hash->root.plt.offset;
5629 if (sym_sec->output_section != NULL)
5630 destination = (sym_value
5631 + sym_sec->output_offset
5632 + sym_sec->output_section->vma);
5633 }
5634 else if (sym_sec->output_section != NULL)
906e58ca
NC		 5635 destination = (sym_value + irela->r_addend
5636 + sym_sec->output_offset
5637 + sym_sec->output_section->vma);
5638 }
69c5861e
CL		 5639 else if ((hash->root.root.type == bfd_link_hash_undefined)
5640 || (hash->root.root.type == bfd_link_hash_undefweak))
5641 {
5642 /* For a shared library, use the PLT stub as
5643 target address to decide whether a long
5644 branch stub is needed.
5645 For absolute code, they cannot be handled. */
5646 struct elf32_arm_link_hash_table *globals =
5647 elf32_arm_hash_table (info);
5648
4dfe6ac6 5649 if (globals != NULL
362d30a1 5650 && globals->root.splt != NULL
4dfe6ac6 5651 && hash != NULL
69c5861e
CL		 5652 && hash->root.plt.offset != (bfd_vma) -1)
5653 {
362d30a1 5654 sym_sec = globals->root.splt;
69c5861e
CL		 5655 sym_value = hash->root.plt.offset;
5656 if (sym_sec->output_section != NULL)
5657 destination = (sym_value
5658 + sym_sec->output_offset
5659 + sym_sec->output_section->vma);
5660 }
5661 else
5662 continue;
5663 }
906e58ca
NC		 5664 else
5665 {
5666 bfd_set_error (bfd_error_bad_value);
5667 goto error_ret_free_internal;
5668 }
34e77a92 5669 st_type = hash->root.type;
39d911fc
TP		 5670 branch_type =
5671 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
7413f23f 5672 sym_name = hash->root.root.root.string;
906e58ca
NC		 5673 }
5674
48229727 5675 do
7413f23f 5676 {
b715f643
TP		 5677 bfd_boolean new_stub;
5678
48229727
JB		 5679 /* Determine what (if any) linker stub is needed. */
5680 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 5681 st_type, &branch_type,
5682 hash, destination, sym_sec,
48229727
JB		 5683 input_bfd, sym_name);
5684 if (stub_type == arm_stub_none)
5685 break;
5686
48229727
JB		 5687 /* We've either created a stub for this reloc already,
5688 or we are about to. */
b715f643
TP		 5689 created_stub =
5690 elf32_arm_create_stub (htab, stub_type, section, irela,
5691 sym_sec, hash,
5692 (char *) sym_name, sym_value,
5693 branch_type, &new_stub);
7413f23f 5694
b715f643
TP		 5695 if (!created_stub)
5696 goto error_ret_free_internal;
5697 else if (!new_stub)
5698 break;
99059e56 5699 else
b715f643 5700 stub_changed = TRUE;
99059e56
RM		 5701 }
5702 while (0);
5703
5704 /* Look for relocations which might trigger Cortex-A8
5705 erratum. */
5706 if (htab->fix_cortex_a8
5707 && (r_type == (unsigned int) R_ARM_THM_JUMP24
5708 || r_type == (unsigned int) R_ARM_THM_JUMP19
5709 || r_type == (unsigned int) R_ARM_THM_CALL
5710 || r_type == (unsigned int) R_ARM_THM_XPC22))
5711 {
5712 bfd_vma from = section->output_section->vma
5713 + section->output_offset
5714 + irela->r_offset;
5715
5716 if ((from & 0xfff) == 0xffe)
5717 {
5718 /* Found a candidate. Note we haven't checked the
5719 destination is within 4K here: if we do so (and
5720 don't create an entry in a8_relocs) we can't tell
5721 that a branch should have been relocated when
5722 scanning later. */
5723 if (num_a8_relocs == a8_reloc_table_size)
5724 {
5725 a8_reloc_table_size *= 2;
5726 a8_relocs = (struct a8_erratum_reloc *)
5727 bfd_realloc (a8_relocs,
5728 sizeof (struct a8_erratum_reloc)
5729 * a8_reloc_table_size);
5730 }
5731
5732 a8_relocs[num_a8_relocs].from = from;
5733 a8_relocs[num_a8_relocs].destination = destination;
5734 a8_relocs[num_a8_relocs].r_type = r_type;
5735 a8_relocs[num_a8_relocs].branch_type = branch_type;
5736 a8_relocs[num_a8_relocs].sym_name = sym_name;
5737 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
5738 a8_relocs[num_a8_relocs].hash = hash;
5739
5740 num_a8_relocs++;
5741 }
5742 }
906e58ca
NC		 5743 }
5744
99059e56
RM		 5745 /* We're done with the internal relocs, free them. */
5746 if (elf_section_data (section)->relocs == NULL)
5747 free (internal_relocs);
5748 }
48229727 5749
99059e56 5750 if (htab->fix_cortex_a8)
48229727 5751 {
99059e56
RM		 5752 /* Sort relocs which might apply to Cortex-A8 erratum. */
5753 qsort (a8_relocs, num_a8_relocs,
eb7c4339 5754 sizeof (struct a8_erratum_reloc),
99059e56 5755 &a8_reloc_compare);
48229727 5756
99059e56
RM		 5757 /* Scan for branches which might trigger Cortex-A8 erratum. */
5758 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 5759 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 5760 a8_relocs, num_a8_relocs,
5761 prev_num_a8_fixes, &stub_changed)
5762 != 0)
48229727 5763 goto error_ret_free_local;
5e681ec4 5764 }
7f991970
AM		 5765
5766 if (local_syms != NULL
5767 && symtab_hdr->contents != (unsigned char *) local_syms)
5768 {
5769 if (!info->keep_memory)
5770 free (local_syms);
5771 else
5772 symtab_hdr->contents = (unsigned char *) local_syms;
5773 }
5e681ec4
PB		 5774 }
5775
eb7c4339 5776 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 5777 stub_changed = TRUE;
48229727 5778
906e58ca
NC		 5779 if (!stub_changed)
5780 break;
5e681ec4 5781
906e58ca
NC		 5782 /* OK, we've added some stubs. Find out the new size of the
5783 stub sections. */
5784 for (stub_sec = htab->stub_bfd->sections;
5785 stub_sec != NULL;
5786 stub_sec = stub_sec->next)
3e6b1042
DJ		 5787 {
5788 /* Ignore non-stub sections. */
5789 if (!strstr (stub_sec->name, STUB_SUFFIX))
5790 continue;
5791
5792 stub_sec->size = 0;
5793 }
b34b2d70 5794
d7c5bd02 5795 /* Compute stub section size, considering padding. */
906e58ca 5796 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
d7c5bd02
TP		 5797 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
5798 stub_type++)
5799 {
5800 int size, padding;
5801 asection **stub_sec_p;
5802
5803 padding = arm_dedicated_stub_section_padding (stub_type);
5804 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
5805 /* Skip if no stub input section or no stub section padding
5806 required. */
5807 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
5808 continue;
5809 /* Stub section padding required but no dedicated section. */
5810 BFD_ASSERT (stub_sec_p);
5811
5812 size = (*stub_sec_p)->size;
5813 size = (size + padding - 1) & ~(padding - 1);
5814 (*stub_sec_p)->size = size;
5815 }
906e58ca 5816
48229727
JB		 5817 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
5818 if (htab->fix_cortex_a8)
99059e56
RM		 5819 for (i = 0; i < num_a8_fixes; i++)
5820 {
48229727 5821 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
daa4adae 5822 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
48229727
JB		 5823
5824 if (stub_sec == NULL)
7f991970 5825 return FALSE;
48229727 5826
99059e56
RM		 5827 stub_sec->size
5828 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
5829 NULL);
5830 }
48229727
JB		 5831
5832
906e58ca
NC		 5833 /* Ask the linker to do its stuff. */
5834 (*htab->layout_sections_again) ();
ba93b8ac
DJ		 5835 }
5836
48229727
JB		 5837 /* Add stubs for Cortex-A8 erratum fixes now. */
5838 if (htab->fix_cortex_a8)
5839 {
5840 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 5841 {
5842 struct elf32_arm_stub_hash_entry *stub_entry;
5843 char *stub_name = a8_fixes[i].stub_name;
5844 asection *section = a8_fixes[i].section;
5845 unsigned int section_id = a8_fixes[i].section->id;
5846 asection *link_sec = htab->stub_group[section_id].link_sec;
5847 asection *stub_sec = htab->stub_group[section_id].stub_sec;
5848 const insn_sequence *template_sequence;
5849 int template_size, size = 0;
5850
5851 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
5852 TRUE, FALSE);
5853 if (stub_entry == NULL)
5854 {
5855 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
5856 section->owner,
5857 stub_name);
5858 return FALSE;
5859 }
5860
5861 stub_entry->stub_sec = stub_sec;
5862 stub_entry->stub_offset = 0;
5863 stub_entry->id_sec = link_sec;
5864 stub_entry->stub_type = a8_fixes[i].stub_type;
8d9d9490 5865 stub_entry->source_value = a8_fixes[i].offset;
99059e56 5866 stub_entry->target_section = a8_fixes[i].section;
8d9d9490 5867 stub_entry->target_value = a8_fixes[i].target_offset;
99059e56 5868 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 5869 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 5870
99059e56
RM		 5871 size = find_stub_size_and_template (a8_fixes[i].stub_type,
5872 &template_sequence,
5873 &template_size);
48229727 5874
99059e56
RM		 5875 stub_entry->stub_size = size;
5876 stub_entry->stub_template = template_sequence;
5877 stub_entry->stub_template_size = template_size;
5878 }
48229727
JB		 5879
5880 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 5881 elf32_arm_write_section(). */
48229727
JB		 5882 htab->a8_erratum_fixes = a8_fixes;
5883 htab->num_a8_erratum_fixes = num_a8_fixes;
5884 }
5885 else
5886 {
5887 htab->a8_erratum_fixes = NULL;
5888 htab->num_a8_erratum_fixes = 0;
5889 }
906e58ca 5890 return TRUE;
5e681ec4
PB		 5891}
5892
906e58ca
NC		 5893/* Build all the stubs associated with the current output file. The
5894 stubs are kept in a hash table attached to the main linker hash
5895 table. We also set up the .plt entries for statically linked PIC
5896 functions here. This function is called via arm_elf_finish in the
5897 linker. */
252b5132 5898
906e58ca
NC		 5899bfd_boolean
5900elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 5901{
906e58ca
NC		 5902 asection *stub_sec;
5903 struct bfd_hash_table *table;
5904 struct elf32_arm_link_hash_table *htab;
252b5132 5905
906e58ca 5906 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 5907 if (htab == NULL)
5908 return FALSE;
252b5132 5909
906e58ca
NC		 5910 for (stub_sec = htab->stub_bfd->sections;
5911 stub_sec != NULL;
5912 stub_sec = stub_sec->next)
252b5132 5913 {
906e58ca
NC		 5914 bfd_size_type size;
5915
8029a119 5916 /* Ignore non-stub sections. */
906e58ca
NC		 5917 if (!strstr (stub_sec->name, STUB_SUFFIX))
5918 continue;
5919
d7c5bd02
TP		 5920 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
5921 must at least be done for stub section requiring padding. */
906e58ca 5922 size = stub_sec->size;
21d799b5 5923 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 5924 if (stub_sec->contents == NULL && size != 0)
5925 return FALSE;
5926 stub_sec->size = 0;
252b5132
RH		 5927 }
5928
906e58ca
NC		 5929 /* Build the stubs as directed by the stub hash table. */
5930 table = &htab->stub_hash_table;
5931 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 5932 if (htab->fix_cortex_a8)
5933 {
5934 /* Place the cortex a8 stubs last. */
5935 htab->fix_cortex_a8 = -1;
5936 bfd_hash_traverse (table, arm_build_one_stub, info);
5937 }
252b5132 5938
906e58ca 5939 return TRUE;
252b5132
RH		 5940}
5941
9b485d32
NC		 5942/* Locate the Thumb encoded calling stub for NAME. */
5943
252b5132 5944static struct elf_link_hash_entry *
57e8b36a
NC		 5945find_thumb_glue (struct bfd_link_info *link_info,
5946 const char *name,
f2a9dd69 5947 char **error_message)
252b5132
RH		 5948{
5949 char *tmp_name;
5950 struct elf_link_hash_entry *hash;
5951 struct elf32_arm_link_hash_table *hash_table;
5952
5953 /* We need a pointer to the armelf specific hash table. */
5954 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 5955 if (hash_table == NULL)
5956 return NULL;
252b5132 5957
21d799b5 5958 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 5959 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 5960
5961 BFD_ASSERT (tmp_name);
5962
5963 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
5964
5965 hash = elf_link_hash_lookup
b34976b6 5966 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 5967
b1657152
AM		 5968 if (hash == NULL
5969 && asprintf (error_message, _("unable to find THUMB glue '%s' for '%s'"),
5970 tmp_name, name) == -1)
5971 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 5972
5973 free (tmp_name);
5974
5975 return hash;
5976}
5977
9b485d32
NC		 5978/* Locate the ARM encoded calling stub for NAME. */
5979
252b5132 5980static struct elf_link_hash_entry *
57e8b36a
NC		 5981find_arm_glue (struct bfd_link_info *link_info,
5982 const char *name,
f2a9dd69 5983 char **error_message)
252b5132
RH		 5984{
5985 char *tmp_name;
5986 struct elf_link_hash_entry *myh;
5987 struct elf32_arm_link_hash_table *hash_table;
5988
5989 /* We need a pointer to the elfarm specific hash table. */
5990 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 5991 if (hash_table == NULL)
5992 return NULL;
252b5132 5993
21d799b5 5994 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 5995 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 5996
5997 BFD_ASSERT (tmp_name);
5998
5999 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6000
6001 myh = elf_link_hash_lookup
b34976b6 6002 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 6003
b1657152
AM		 6004 if (myh == NULL
6005 && asprintf (error_message, _("unable to find ARM glue '%s' for '%s'"),
6006 tmp_name, name) == -1)
6007 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 6008
6009 free (tmp_name);
6010
6011 return myh;
6012}
6013
8f6277f5 6014/* ARM->Thumb glue (static images):
252b5132
RH		 6015
6016 .arm
6017 __func_from_arm:
6018 ldr r12, __func_addr
6019 bx r12
6020 __func_addr:
906e58ca 6021 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 6022
26079076
PB		 6023 (v5t static images)
6024 .arm
6025 __func_from_arm:
6026 ldr pc, __func_addr
6027 __func_addr:
906e58ca 6028 .word func @ behave as if you saw a ARM_32 reloc.
26079076 6029
8f6277f5
PB		 6030 (relocatable images)
6031 .arm
6032 __func_from_arm:
6033 ldr r12, __func_offset
6034 add r12, r12, pc
6035 bx r12
6036 __func_offset:
8029a119 6037 .word func - . */
8f6277f5
PB		 6038
6039#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 6040static const insn32 a2t1_ldr_insn = 0xe59fc000;
6041static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
6042static const insn32 a2t3_func_addr_insn = 0x00000001;
6043
26079076
PB		 6044#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
6045static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
6046static const insn32 a2t2v5_func_addr_insn = 0x00000001;
6047
8f6277f5
PB		 6048#define ARM2THUMB_PIC_GLUE_SIZE 16
6049static const insn32 a2t1p_ldr_insn = 0xe59fc004;
6050static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
6051static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
6052
9b485d32 6053/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 6054
8029a119
NC		 6055 .thumb .thumb
6056 .align 2 .align 2
6057 __func_from_thumb: __func_from_thumb:
6058 bx pc push {r6, lr}
6059 nop ldr r6, __func_addr
6060 .arm mov lr, pc
6061 b func bx r6
99059e56
RM		 6062 .arm
6063 ;; back_to_thumb
6064 ldmia r13! {r6, lr}
6065 bx lr
6066 __func_addr:
6067 .word func */
252b5132
RH		 6068
6069#define THUMB2ARM_GLUE_SIZE 8
6070static const insn16 t2a1_bx_pc_insn = 0x4778;
6071static const insn16 t2a2_noop_insn = 0x46c0;
6072static const insn32 t2a3_b_insn = 0xea000000;
6073
c7b8f16e 6074#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 6075#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
6076#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 6077
845b51d6
PB		 6078#define ARM_BX_VENEER_SIZE 12
6079static const insn32 armbx1_tst_insn = 0xe3100001;
6080static const insn32 armbx2_moveq_insn = 0x01a0f000;
6081static const insn32 armbx3_bx_insn = 0xe12fff10;
6082
7e392df6 6083#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 6084static void
6085arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 6086{
6087 asection * s;
8029a119 6088 bfd_byte * contents;
252b5132 6089
8029a119 6090 if (size == 0)
3e6b1042
DJ		 6091 {
6092 /* Do not include empty glue sections in the output. */
6093 if (abfd != NULL)
6094 {
3d4d4302 6095 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 6096 if (s != NULL)
6097 s->flags |= SEC_EXCLUDE;
6098 }
6099 return;
6100 }
252b5132 6101
8029a119 6102 BFD_ASSERT (abfd != NULL);
252b5132 6103
3d4d4302 6104 s = bfd_get_linker_section (abfd, name);
8029a119 6105 BFD_ASSERT (s != NULL);
252b5132 6106
21d799b5 6107 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 6108
8029a119
NC		 6109 BFD_ASSERT (s->size == size);
6110 s->contents = contents;
6111}
906e58ca 6112
8029a119
NC		 6113bfd_boolean
6114bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
6115{
6116 struct elf32_arm_link_hash_table * globals;
906e58ca 6117
8029a119
NC		 6118 globals = elf32_arm_hash_table (info);
6119 BFD_ASSERT (globals != NULL);
906e58ca 6120
8029a119
NC		 6121 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6122 globals->arm_glue_size,
6123 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 6124
8029a119
NC		 6125 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6126 globals->thumb_glue_size,
6127 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 6128
8029a119
NC		 6129 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6130 globals->vfp11_erratum_glue_size,
6131 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 6132
a504d23a
LA		 6133 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6134 globals->stm32l4xx_erratum_glue_size,
6135 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6136
8029a119
NC		 6137 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
6138 globals->bx_glue_size,
845b51d6
PB		 6139 ARM_BX_GLUE_SECTION_NAME);
6140
b34976b6 6141 return TRUE;
252b5132
RH		 6142}
6143
a4fd1a8e 6144/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 6145 returns the symbol identifying the stub. */
6146
a4fd1a8e 6147static struct elf_link_hash_entry *
57e8b36a
NC		 6148record_arm_to_thumb_glue (struct bfd_link_info * link_info,
6149 struct elf_link_hash_entry * h)
252b5132
RH		 6150{
6151 const char * name = h->root.root.string;
63b0f745 6152 asection * s;
252b5132
RH		 6153 char * tmp_name;
6154 struct elf_link_hash_entry * myh;
14a793b2 6155 struct bfd_link_hash_entry * bh;
252b5132 6156 struct elf32_arm_link_hash_table * globals;
dc810e39 6157 bfd_vma val;
2f475487 6158 bfd_size_type size;
252b5132
RH		 6159
6160 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 6161 BFD_ASSERT (globals != NULL);
6162 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6163
3d4d4302 6164 s = bfd_get_linker_section
252b5132
RH		 6165 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
6166
252b5132
RH		 6167 BFD_ASSERT (s != NULL);
6168
21d799b5 6169 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 6170 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 6171
6172 BFD_ASSERT (tmp_name);
6173
6174 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
6175
6176 myh = elf_link_hash_lookup
b34976b6 6177 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 6178
6179 if (myh != NULL)
6180 {
9b485d32 6181 /* We've already seen this guy. */
252b5132 6182 free (tmp_name);
a4fd1a8e 6183 return myh;
252b5132
RH		 6184 }
6185
57e8b36a
NC		 6186 /* The only trick here is using hash_table->arm_glue_size as the value.
6187 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 6188 putting it. The +1 on the value marks that the stub has not been
6189 output yet - not that it is a Thumb function. */
14a793b2 6190 bh = NULL;
dc810e39
AM		 6191 val = globals->arm_glue_size + 1;
6192 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
6193 tmp_name, BSF_GLOBAL, s, val,
b34976b6 6194 NULL, TRUE, FALSE, &bh);
252b5132 6195
b7693d02
DJ		 6196 myh = (struct elf_link_hash_entry *) bh;
6197 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6198 myh->forced_local = 1;
6199
252b5132
RH		 6200 free (tmp_name);
6201
0e1862bb
L		 6202 if (bfd_link_pic (link_info)
6203 || globals->root.is_relocatable_executable
27e55c4d 6204 || globals->pic_veneer)
2f475487 6205 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 6206 else if (globals->use_blx)
6207 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 6208 else
2f475487
AM		 6209 size = ARM2THUMB_STATIC_GLUE_SIZE;
6210
6211 s->size += size;
6212 globals->arm_glue_size += size;
252b5132 6213
a4fd1a8e 6214 return myh;
252b5132
RH		 6215}
6216
845b51d6
PB		 6217/* Allocate space for ARMv4 BX veneers. */
6218
6219static void
6220record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
6221{
6222 asection * s;
6223 struct elf32_arm_link_hash_table *globals;
6224 char *tmp_name;
6225 struct elf_link_hash_entry *myh;
6226 struct bfd_link_hash_entry *bh;
6227 bfd_vma val;
6228
6229 /* BX PC does not need a veneer. */
6230 if (reg == 15)
6231 return;
6232
6233 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 6234 BFD_ASSERT (globals != NULL);
6235 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6236
6237 /* Check if this veneer has already been allocated. */
6238 if (globals->bx_glue_offset[reg])
6239 return;
6240
3d4d4302 6241 s = bfd_get_linker_section
845b51d6
PB		 6242 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
6243
6244 BFD_ASSERT (s != NULL);
6245
6246 /* Add symbol for veneer. */
21d799b5
NC		 6247 tmp_name = (char *)
6248 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 6249
845b51d6 6250 BFD_ASSERT (tmp_name);
906e58ca 6251
845b51d6 6252 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 6253
845b51d6
PB		 6254 myh = elf_link_hash_lookup
6255 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6256
845b51d6 6257 BFD_ASSERT (myh == NULL);
906e58ca 6258
845b51d6
PB		 6259 bh = NULL;
6260 val = globals->bx_glue_size;
6261 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 6262 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6263 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 6264
6265 myh = (struct elf_link_hash_entry *) bh;
6266 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6267 myh->forced_local = 1;
6268
6269 s->size += ARM_BX_VENEER_SIZE;
6270 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
6271 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
6272}
6273
6274
c7b8f16e
JB		 6275/* Add an entry to the code/data map for section SEC. */
6276
6277static void
6278elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
6279{
6280 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
6281 unsigned int newidx;
906e58ca 6282
c7b8f16e
JB		 6283 if (sec_data->map == NULL)
6284 {
21d799b5 6285 sec_data->map = (elf32_arm_section_map *)
99059e56 6286 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 6287 sec_data->mapcount = 0;
6288 sec_data->mapsize = 1;
6289 }
906e58ca 6290
c7b8f16e 6291 newidx = sec_data->mapcount++;
906e58ca 6292
c7b8f16e
JB		 6293 if (sec_data->mapcount > sec_data->mapsize)
6294 {
6295 sec_data->mapsize *= 2;
21d799b5 6296 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 6297 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
6298 * sizeof (elf32_arm_section_map));
515ef31d
NC		 6299 }
6300
6301 if (sec_data->map)
6302 {
6303 sec_data->map[newidx].vma = vma;
6304 sec_data->map[newidx].type = type;
c7b8f16e 6305 }
c7b8f16e
JB		 6306}
6307
6308
6309/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
6310 veneers are handled for now. */
6311
6312static bfd_vma
6313record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 6314 elf32_vfp11_erratum_list *branch,
6315 bfd *branch_bfd,
6316 asection *branch_sec,
6317 unsigned int offset)
c7b8f16e
JB		 6318{
6319 asection *s;
6320 struct elf32_arm_link_hash_table *hash_table;
6321 char *tmp_name;
6322 struct elf_link_hash_entry *myh;
6323 struct bfd_link_hash_entry *bh;
6324 bfd_vma val;
6325 struct _arm_elf_section_data *sec_data;
c7b8f16e 6326 elf32_vfp11_erratum_list *newerr;
906e58ca 6327
c7b8f16e 6328 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 6329 BFD_ASSERT (hash_table != NULL);
6330 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 6331
3d4d4302 6332 s = bfd_get_linker_section
c7b8f16e 6333 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 6334
c7b8f16e 6335 sec_data = elf32_arm_section_data (s);
906e58ca 6336
c7b8f16e 6337 BFD_ASSERT (s != NULL);
906e58ca 6338
21d799b5 6339 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 6340 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 6341
c7b8f16e 6342 BFD_ASSERT (tmp_name);
906e58ca 6343
c7b8f16e
JB		 6344 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
6345 hash_table->num_vfp11_fixes);
906e58ca 6346
c7b8f16e
JB		 6347 myh = elf_link_hash_lookup
6348 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6349
c7b8f16e 6350 BFD_ASSERT (myh == NULL);
906e58ca 6351
c7b8f16e
JB		 6352 bh = NULL;
6353 val = hash_table->vfp11_erratum_glue_size;
6354 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 6355 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6356 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 6357
6358 myh = (struct elf_link_hash_entry *) bh;
6359 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6360 myh->forced_local = 1;
6361
6362 /* Link veneer back to calling location. */
c7e2358a 6363 sec_data->erratumcount += 1;
21d799b5
NC		 6364 newerr = (elf32_vfp11_erratum_list *)
6365 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 6366
c7b8f16e
JB		 6367 newerr->type = VFP11_ERRATUM_ARM_VENEER;
6368 newerr->vma = -1;
6369 newerr->u.v.branch = branch;
6370 newerr->u.v.id = hash_table->num_vfp11_fixes;
6371 branch->u.b.veneer = newerr;
6372
6373 newerr->next = sec_data->erratumlist;
6374 sec_data->erratumlist = newerr;
6375
6376 /* A symbol for the return from the veneer. */
6377 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
6378 hash_table->num_vfp11_fixes);
6379
6380 myh = elf_link_hash_lookup
6381 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6382
c7b8f16e
JB		 6383 if (myh != NULL)
6384 abort ();
6385
6386 bh = NULL;
6387 val = offset + 4;
6388 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
6389 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 6390
c7b8f16e
JB		 6391 myh = (struct elf_link_hash_entry *) bh;
6392 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6393 myh->forced_local = 1;
6394
6395 free (tmp_name);
906e58ca 6396
c7b8f16e
JB		 6397 /* Generate a mapping symbol for the veneer section, and explicitly add an
6398 entry for that symbol to the code/data map for the section. */
6399 if (hash_table->vfp11_erratum_glue_size == 0)
6400 {
6401 bh = NULL;
6402 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 6403 ever requires this erratum fix. */
c7b8f16e
JB		 6404 _bfd_generic_link_add_one_symbol (link_info,
6405 hash_table->bfd_of_glue_owner, "$a",
6406 BSF_LOCAL, s, 0, NULL,
99059e56 6407 TRUE, FALSE, &bh);
c7b8f16e
JB		 6408
6409 myh = (struct elf_link_hash_entry *) bh;
6410 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
6411 myh->forced_local = 1;
906e58ca 6412
c7b8f16e 6413 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 6414 BFDs. We must make a note of this generated mapping symbol
6415 ourselves so that code byteswapping works properly in
6416 elf32_arm_write_section. */
c7b8f16e
JB		 6417 elf32_arm_section_map_add (s, 'a', 0);
6418 }
906e58ca 6419
c7b8f16e
JB		 6420 s->size += VFP11_ERRATUM_VENEER_SIZE;
6421 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
6422 hash_table->num_vfp11_fixes++;
906e58ca 6423
c7b8f16e
JB		 6424 /* The offset of the veneer. */
6425 return val;
6426}
6427
a504d23a
LA		 6428/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
6429 veneers need to be handled because used only in Cortex-M. */
6430
6431static bfd_vma
6432record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
6433 elf32_stm32l4xx_erratum_list *branch,
6434 bfd *branch_bfd,
6435 asection *branch_sec,
6436 unsigned int offset,
6437 bfd_size_type veneer_size)
6438{
6439 asection *s;
6440 struct elf32_arm_link_hash_table *hash_table;
6441 char *tmp_name;
6442 struct elf_link_hash_entry *myh;
6443 struct bfd_link_hash_entry *bh;
6444 bfd_vma val;
6445 struct _arm_elf_section_data *sec_data;
6446 elf32_stm32l4xx_erratum_list *newerr;
6447
6448 hash_table = elf32_arm_hash_table (link_info);
6449 BFD_ASSERT (hash_table != NULL);
6450 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
6451
6452 s = bfd_get_linker_section
6453 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6454
6455 BFD_ASSERT (s != NULL);
6456
6457 sec_data = elf32_arm_section_data (s);
6458
6459 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
6460 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
6461
6462 BFD_ASSERT (tmp_name);
6463
6464 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
6465 hash_table->num_stm32l4xx_fixes);
6466
6467 myh = elf_link_hash_lookup
6468 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
6469
6470 BFD_ASSERT (myh == NULL);
6471
6472 bh = NULL;
6473 val = hash_table->stm32l4xx_erratum_glue_size;
6474 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
6475 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6476 NULL, TRUE, FALSE, &bh);
6477
6478 myh = (struct elf_link_hash_entry *) bh;
6479 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6480 myh->forced_local = 1;
6481
6482 /* Link veneer back to calling location. */
6483 sec_data->stm32l4xx_erratumcount += 1;
6484 newerr = (elf32_stm32l4xx_erratum_list *)
6485 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
6486
6487 newerr->type = STM32L4XX_ERRATUM_VENEER;
6488 newerr->vma = -1;
6489 newerr->u.v.branch = branch;
6490 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
6491 branch->u.b.veneer = newerr;
6492
6493 newerr->next = sec_data->stm32l4xx_erratumlist;
6494 sec_data->stm32l4xx_erratumlist = newerr;
6495
6496 /* A symbol for the return from the veneer. */
6497 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
6498 hash_table->num_stm32l4xx_fixes);
6499
6500 myh = elf_link_hash_lookup
6501 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
6502
6503 if (myh != NULL)
6504 abort ();
6505
6506 bh = NULL;
6507 val = offset + 4;
6508 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
6509 branch_sec, val, NULL, TRUE, FALSE, &bh);
6510
6511 myh = (struct elf_link_hash_entry *) bh;
6512 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6513 myh->forced_local = 1;
6514
6515 free (tmp_name);
6516
6517 /* Generate a mapping symbol for the veneer section, and explicitly add an
6518 entry for that symbol to the code/data map for the section. */
6519 if (hash_table->stm32l4xx_erratum_glue_size == 0)
6520 {
6521 bh = NULL;
6522 /* Creates a THUMB symbol since there is no other choice. */
6523 _bfd_generic_link_add_one_symbol (link_info,
6524 hash_table->bfd_of_glue_owner, "$t",
6525 BSF_LOCAL, s, 0, NULL,
6526 TRUE, FALSE, &bh);
6527
6528 myh = (struct elf_link_hash_entry *) bh;
6529 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
6530 myh->forced_local = 1;
6531
6532 /* The elf32_arm_init_maps function only cares about symbols from input
6533 BFDs. We must make a note of this generated mapping symbol
6534 ourselves so that code byteswapping works properly in
6535 elf32_arm_write_section. */
6536 elf32_arm_section_map_add (s, 't', 0);
6537 }
6538
6539 s->size += veneer_size;
6540 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
6541 hash_table->num_stm32l4xx_fixes++;
6542
6543 /* The offset of the veneer. */
6544 return val;
6545}
6546
8029a119 6547#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 6548 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
6549 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 6550
6551/* Create a fake section for use by the ARM backend of the linker. */
6552
6553static bfd_boolean
6554arm_make_glue_section (bfd * abfd, const char * name)
6555{
6556 asection * sec;
6557
3d4d4302 6558 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 6559 if (sec != NULL)
6560 /* Already made. */
6561 return TRUE;
6562
3d4d4302 6563 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 6564
6565 if (sec == NULL
6566 || !bfd_set_section_alignment (abfd, sec, 2))
6567 return FALSE;
6568
6569 /* Set the gc mark to prevent the section from being removed by garbage
6570 collection, despite the fact that no relocs refer to this section. */
6571 sec->gc_mark = 1;
6572
6573 return TRUE;
6574}
6575
1db37fe6
YG		 6576/* Set size of .plt entries. This function is called from the
6577 linker scripts in ld/emultempl/{armelf}.em. */
6578
6579void
6580bfd_elf32_arm_use_long_plt (void)
6581{
6582 elf32_arm_use_long_plt_entry = TRUE;
6583}
6584
8afb0e02
NC		 6585/* Add the glue sections to ABFD. This function is called from the
6586 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 6587
b34976b6 6588bfd_boolean
57e8b36a
NC		 6589bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
6590 struct bfd_link_info *info)
252b5132 6591{
a504d23a
LA		 6592 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
6593 bfd_boolean dostm32l4xx = globals
6594 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
6595 bfd_boolean addglue;
6596
8afb0e02
NC		 6597 /* If we are only performing a partial
6598 link do not bother adding the glue. */
0e1862bb 6599 if (bfd_link_relocatable (info))
b34976b6 6600 return TRUE;
252b5132 6601
a504d23a 6602 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 6603 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
6604 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
6605 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 6606
6607 if (!dostm32l4xx)
6608 return addglue;
6609
6610 return addglue
6611 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 6612}
6613
daa4adae
TP		 6614/* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
6615 ensures they are not marked for deletion by
6616 strip_excluded_output_sections () when veneers are going to be created
6617 later. Not doing so would trigger assert on empty section size in
6618 lang_size_sections_1 (). */
6619
6620void
6621bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
6622{
6623 enum elf32_arm_stub_type stub_type;
6624
6625 /* If we are only performing a partial
6626 link do not bother adding the glue. */
6627 if (bfd_link_relocatable (info))
6628 return;
6629
6630 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
6631 {
6632 asection *out_sec;
6633 const char *out_sec_name;
6634
6635 if (!arm_dedicated_stub_output_section_required (stub_type))
6636 continue;
6637
6638 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
6639 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
6640 if (out_sec != NULL)
6641 out_sec->flags |= SEC_KEEP;
6642 }
6643}
6644
8afb0e02
NC		 6645/* Select a BFD to be used to hold the sections used by the glue code.
6646 This function is called from the linker scripts in ld/emultempl/
8029a119 6647 {armelf/pe}.em. */
8afb0e02 6648
b34976b6 6649bfd_boolean
57e8b36a 6650bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 6651{
6652 struct elf32_arm_link_hash_table *globals;
6653
6654 /* If we are only performing a partial link
6655 do not bother getting a bfd to hold the glue. */
0e1862bb 6656 if (bfd_link_relocatable (info))
b34976b6 6657 return TRUE;
8afb0e02 6658
b7693d02
DJ		 6659 /* Make sure we don't attach the glue sections to a dynamic object. */
6660 BFD_ASSERT (!(abfd->flags & DYNAMIC));
6661
8afb0e02 6662 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 6663 BFD_ASSERT (globals != NULL);
6664
6665 if (globals->bfd_of_glue_owner != NULL)
b34976b6 6666 return TRUE;
8afb0e02 6667
252b5132
RH		 6668 /* Save the bfd for later use. */
6669 globals->bfd_of_glue_owner = abfd;
cedb70c5 6670
b34976b6 6671 return TRUE;
252b5132
RH		 6672}
6673
906e58ca
NC		 6674static void
6675check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 6676{
2de70689
MGD		 6677 int cpu_arch;
6678
b38cadfb 6679 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 6680 Tag_CPU_arch);
6681
6682 if (globals->fix_arm1176)
6683 {
6684 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
6685 globals->use_blx = 1;
6686 }
6687 else
6688 {
6689 if (cpu_arch > TAG_CPU_ARCH_V4T)
6690 globals->use_blx = 1;
6691 }
39b41c9c
PB		 6692}
6693
b34976b6 6694bfd_boolean
57e8b36a 6695bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 6696 struct bfd_link_info *link_info)
252b5132
RH		 6697{
6698 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 6699 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 6700 Elf_Internal_Rela *irel, *irelend;
6701 bfd_byte *contents = NULL;
252b5132
RH		 6702
6703 asection *sec;
6704 struct elf32_arm_link_hash_table *globals;
6705
6706 /* If we are only performing a partial link do not bother
6707 to construct any glue. */
0e1862bb 6708 if (bfd_link_relocatable (link_info))
b34976b6 6709 return TRUE;
252b5132 6710
39ce1a6a
NC		 6711 /* Here we have a bfd that is to be included on the link. We have a
6712 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 6713 globals = elf32_arm_hash_table (link_info);
252b5132 6714 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 6715
6716 check_use_blx (globals);
252b5132 6717
d504ffc8 6718 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 6719 {
d003868e
AM		 6720 _bfd_error_handler (_("%B: BE8 images only valid in big-endian mode."),
6721 abfd);
e489d0ae
PB		 6722 return FALSE;
6723 }
f21f3fe0 6724
39ce1a6a
NC		 6725 /* PR 5398: If we have not decided to include any loadable sections in
6726 the output then we will not have a glue owner bfd. This is OK, it
6727 just means that there is nothing else for us to do here. */
6728 if (globals->bfd_of_glue_owner == NULL)
6729 return TRUE;
6730
252b5132
RH		 6731 /* Rummage around all the relocs and map the glue vectors. */
6732 sec = abfd->sections;
6733
6734 if (sec == NULL)
b34976b6 6735 return TRUE;
252b5132
RH		 6736
6737 for (; sec != NULL; sec = sec->next)
6738 {
6739 if (sec->reloc_count == 0)
6740 continue;
6741
2f475487
AM		 6742 if ((sec->flags & SEC_EXCLUDE) != 0)
6743 continue;
6744
0ffa91dd 6745 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 6746
9b485d32 6747 /* Load the relocs. */
6cdc0ccc 6748 internal_relocs
906e58ca 6749 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 6750
6cdc0ccc
AM		 6751 if (internal_relocs == NULL)
6752 goto error_return;
252b5132 6753
6cdc0ccc
AM		 6754 irelend = internal_relocs + sec->reloc_count;
6755 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 6756 {
6757 long r_type;
6758 unsigned long r_index;
252b5132
RH		 6759
6760 struct elf_link_hash_entry *h;
6761
6762 r_type = ELF32_R_TYPE (irel->r_info);
6763 r_index = ELF32_R_SYM (irel->r_info);
6764
9b485d32 6765 /* These are the only relocation types we care about. */
ba96a88f 6766 if ( r_type != R_ARM_PC24
845b51d6 6767 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 6768 continue;
6769
6770 /* Get the section contents if we haven't done so already. */
6771 if (contents == NULL)
6772 {
6773 /* Get cached copy if it exists. */
6774 if (elf_section_data (sec)->this_hdr.contents != NULL)
6775 contents = elf_section_data (sec)->this_hdr.contents;
6776 else
6777 {
6778 /* Go get them off disk. */
57e8b36a 6779 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 6780 goto error_return;
6781 }
6782 }
6783
845b51d6
PB		 6784 if (r_type == R_ARM_V4BX)
6785 {
6786 int reg;
6787
6788 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
6789 record_arm_bx_glue (link_info, reg);
6790 continue;
6791 }
6792
a7c10850 6793 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 6794 h = NULL;
6795
9b485d32 6796 /* We don't care about local symbols. */
252b5132
RH		 6797 if (r_index < symtab_hdr->sh_info)
6798 continue;
6799
9b485d32 6800 /* This is an external symbol. */
252b5132
RH		 6801 r_index -= symtab_hdr->sh_info;
6802 h = (struct elf_link_hash_entry *)
6803 elf_sym_hashes (abfd)[r_index];
6804
6805 /* If the relocation is against a static symbol it must be within
6806 the current section and so cannot be a cross ARM/Thumb relocation. */
6807 if (h == NULL)
6808 continue;
6809
d504ffc8
DJ		 6810 /* If the call will go through a PLT entry then we do not need
6811 glue. */
362d30a1 6812 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 6813 continue;
6814
252b5132
RH		 6815 switch (r_type)
6816 {
6817 case R_ARM_PC24:
6818 /* This one is a call from arm code. We need to look up
99059e56
RM		 6819 the target of the call. If it is a thumb target, we
6820 insert glue. */
39d911fc
TP		 6821 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
6822 == ST_BRANCH_TO_THUMB)
252b5132
RH		 6823 record_arm_to_thumb_glue (link_info, h);
6824 break;
6825
252b5132 6826 default:
c6596c5e 6827 abort ();
252b5132
RH		 6828 }
6829 }
6cdc0ccc
AM		 6830
6831 if (contents != NULL
6832 && elf_section_data (sec)->this_hdr.contents != contents)
6833 free (contents);
6834 contents = NULL;
6835
6836 if (internal_relocs != NULL
6837 && elf_section_data (sec)->relocs != internal_relocs)
6838 free (internal_relocs);
6839 internal_relocs = NULL;
252b5132
RH		 6840 }
6841
b34976b6 6842 return TRUE;
9a5aca8c 6843
252b5132 6844error_return:
6cdc0ccc
AM		 6845 if (contents != NULL
6846 && elf_section_data (sec)->this_hdr.contents != contents)
6847 free (contents);
6848 if (internal_relocs != NULL
6849 && elf_section_data (sec)->relocs != internal_relocs)
6850 free (internal_relocs);
9a5aca8c 6851
b34976b6 6852 return FALSE;
252b5132 6853}
7e392df6 6854#endif
252b5132 6855
eb043451 6856
c7b8f16e
JB		 6857/* Initialise maps of ARM/Thumb/data for input BFDs. */
6858
6859void
6860bfd_elf32_arm_init_maps (bfd *abfd)
6861{
6862 Elf_Internal_Sym *isymbuf;
6863 Elf_Internal_Shdr *hdr;
6864 unsigned int i, localsyms;
6865
af1f4419
NC		 6866 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
6867 if (! is_arm_elf (abfd))
6868 return;
6869
c7b8f16e
JB		 6870 if ((abfd->flags & DYNAMIC) != 0)
6871 return;
6872
0ffa91dd 6873 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 6874 localsyms = hdr->sh_info;
6875
6876 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
6877 should contain the number of local symbols, which should come before any
6878 global symbols. Mapping symbols are always local. */
6879 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
6880 NULL);
6881
6882 /* No internal symbols read? Skip this BFD. */
6883 if (isymbuf == NULL)
6884 return;
6885
6886 for (i = 0; i < localsyms; i++)
6887 {
6888 Elf_Internal_Sym *isym = &isymbuf[i];
6889 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
6890 const char *name;
906e58ca 6891
c7b8f16e 6892 if (sec != NULL
99059e56
RM		 6893 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
6894 {
6895 name = bfd_elf_string_from_elf_section (abfd,
6896 hdr->sh_link, isym->st_name);
906e58ca 6897
99059e56 6898 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 6899 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 6900 elf32_arm_section_map_add (sec, name[1], isym->st_value);
6901 }
c7b8f16e
JB		 6902 }
6903}
6904
6905
48229727
JB		 6906/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
6907 say what they wanted. */
6908
6909void
6910bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
6911{
6912 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
6913 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
6914
4dfe6ac6
NC		 6915 if (globals == NULL)
6916 return;
6917
48229727
JB		 6918 if (globals->fix_cortex_a8 == -1)
6919 {
6920 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
6921 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
6922 && (out_attr[Tag_CPU_arch_profile].i == 'A'
6923 || out_attr[Tag_CPU_arch_profile].i == 0))
6924 globals->fix_cortex_a8 = 1;
6925 else
6926 globals->fix_cortex_a8 = 0;
6927 }
6928}
6929
6930
c7b8f16e
JB		 6931void
6932bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
6933{
6934 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 6935 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 6936
4dfe6ac6
NC		 6937 if (globals == NULL)
6938 return;
c7b8f16e
JB		 6939 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
6940 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
6941 {
6942 switch (globals->vfp11_fix)
99059e56
RM		 6943 {
6944 case BFD_ARM_VFP11_FIX_DEFAULT:
6945 case BFD_ARM_VFP11_FIX_NONE:
6946 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
6947 break;
6948
6949 default:
6950 /* Give a warning, but do as the user requests anyway. */
6951 (*_bfd_error_handler) (_("%B: warning: selected VFP11 erratum "
6952 "workaround is not necessary for target architecture"), obfd);
6953 }
c7b8f16e
JB		 6954 }
6955 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
6956 /* For earlier architectures, we might need the workaround, but do not
6957 enable it by default. If users is running with broken hardware, they
6958 must enable the erratum fix explicitly. */
6959 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
6960}
6961
a504d23a
LA		 6962void
6963bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
6964{
6965 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
6966 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
6967
6968 if (globals == NULL)
6969 return;
6970
6971 /* We assume only Cortex-M4 may require the fix. */
6972 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
6973 || out_attr[Tag_CPU_arch_profile].i != 'M')
6974 {
6975 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
6976 /* Give a warning, but do as the user requests anyway. */
6977 (*_bfd_error_handler)
6978 (_("%B: warning: selected STM32L4XX erratum "
6979 "workaround is not necessary for target architecture"), obfd);
6980 }
6981}
c7b8f16e 6982
906e58ca
NC		 6983enum bfd_arm_vfp11_pipe
6984{
c7b8f16e
JB		 6985 VFP11_FMAC,
6986 VFP11_LS,
6987 VFP11_DS,
6988 VFP11_BAD
6989};
6990
6991/* Return a VFP register number. This is encoded as RX:X for single-precision
6992 registers, or X:RX for double-precision registers, where RX is the group of
6993 four bits in the instruction encoding and X is the single extension bit.
6994 RX and X fields are specified using their lowest (starting) bit. The return
6995 value is:
6996
6997 0...31: single-precision registers s0...s31
6998 32...63: double-precision registers d0...d31.
906e58ca 6999
c7b8f16e
JB		 7000 Although X should be zero for VFP11 (encoding d0...d15 only), we might
7001 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 7002
c7b8f16e
JB		 7003static unsigned int
7004bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 7005 unsigned int x)
c7b8f16e
JB		 7006{
7007 if (is_double)
7008 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
7009 else
7010 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
7011}
7012
7013/* Set bits in *WMASK according to a register number REG as encoded by
7014 bfd_arm_vfp11_regno(). Ignore d16-d31. */
7015
7016static void
7017bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
7018{
7019 if (reg < 32)
7020 *wmask |= 1 << reg;
7021 else if (reg < 48)
7022 *wmask |= 3 << ((reg - 32) * 2);
7023}
7024
7025/* Return TRUE if WMASK overwrites anything in REGS. */
7026
7027static bfd_boolean
7028bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
7029{
7030 int i;
906e58ca 7031
c7b8f16e
JB		 7032 for (i = 0; i < numregs; i++)
7033 {
7034 unsigned int reg = regs[i];
7035
7036 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 7037 return TRUE;
906e58ca 7038
c7b8f16e
JB		 7039 reg -= 32;
7040
7041 if (reg >= 16)
99059e56 7042 continue;
906e58ca 7043
c7b8f16e 7044 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 7045 return TRUE;
c7b8f16e 7046 }
906e58ca 7047
c7b8f16e
JB		 7048 return FALSE;
7049}
7050
7051/* In this function, we're interested in two things: finding input registers
7052 for VFP data-processing instructions, and finding the set of registers which
7053 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
7054 hold the written set, so FLDM etc. are easy to deal with (we're only
7055 interested in 32 SP registers or 16 dp registers, due to the VFP version
7056 implemented by the chip in question). DP registers are marked by setting
7057 both SP registers in the write mask). */
7058
7059static enum bfd_arm_vfp11_pipe
7060bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 7061 int *numregs)
c7b8f16e 7062{
91d6fa6a 7063 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 7064 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
7065
7066 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
7067 {
7068 unsigned int pqrs;
7069 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7070 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
7071
7072 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 7073 | ((insn & 0x00300000) >> 19)
7074 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 7075
7076 switch (pqrs)
99059e56
RM		 7077 {
7078 case 0: /* fmac[sd]. */
7079 case 1: /* fnmac[sd]. */
7080 case 2: /* fmsc[sd]. */
7081 case 3: /* fnmsc[sd]. */
7082 vpipe = VFP11_FMAC;
7083 bfd_arm_vfp11_write_mask (destmask, fd);
7084 regs[0] = fd;
7085 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7086 regs[2] = fm;
7087 *numregs = 3;
7088 break;
7089
7090 case 4: /* fmul[sd]. */
7091 case 5: /* fnmul[sd]. */
7092 case 6: /* fadd[sd]. */
7093 case 7: /* fsub[sd]. */
7094 vpipe = VFP11_FMAC;
7095 goto vfp_binop;
7096
7097 case 8: /* fdiv[sd]. */
7098 vpipe = VFP11_DS;
7099 vfp_binop:
7100 bfd_arm_vfp11_write_mask (destmask, fd);
7101 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
7102 regs[1] = fm;
7103 *numregs = 2;
7104 break;
7105
7106 case 15: /* extended opcode. */
7107 {
7108 unsigned int extn = ((insn >> 15) & 0x1e)
7109 | ((insn >> 7) & 1);
7110
7111 switch (extn)
7112 {
7113 case 0: /* fcpy[sd]. */
7114 case 1: /* fabs[sd]. */
7115 case 2: /* fneg[sd]. */
7116 case 8: /* fcmp[sd]. */
7117 case 9: /* fcmpe[sd]. */
7118 case 10: /* fcmpz[sd]. */
7119 case 11: /* fcmpez[sd]. */
7120 case 16: /* fuito[sd]. */
7121 case 17: /* fsito[sd]. */
7122 case 24: /* ftoui[sd]. */
7123 case 25: /* ftouiz[sd]. */
7124 case 26: /* ftosi[sd]. */
7125 case 27: /* ftosiz[sd]. */
7126 /* These instructions will not bounce due to underflow. */
7127 *numregs = 0;
7128 vpipe = VFP11_FMAC;
7129 break;
7130
7131 case 3: /* fsqrt[sd]. */
7132 /* fsqrt cannot underflow, but it can (perhaps) overwrite
7133 registers to cause the erratum in previous instructions. */
7134 bfd_arm_vfp11_write_mask (destmask, fd);
7135 vpipe = VFP11_DS;
7136 break;
7137
7138 case 15: /* fcvt{ds,sd}. */
7139 {
7140 int rnum = 0;
7141
7142 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 7143
7144 /* Only FCVTSD can underflow. */
99059e56
RM		 7145 if ((insn & 0x100) != 0)
7146 regs[rnum++] = fm;
c7b8f16e 7147
99059e56 7148 *numregs = rnum;
c7b8f16e 7149
99059e56
RM		 7150 vpipe = VFP11_FMAC;
7151 }
7152 break;
c7b8f16e 7153
99059e56
RM		 7154 default:
7155 return VFP11_BAD;
7156 }
7157 }
7158 break;
c7b8f16e 7159
99059e56
RM		 7160 default:
7161 return VFP11_BAD;
7162 }
c7b8f16e
JB		 7163 }
7164 /* Two-register transfer. */
7165 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
7166 {
7167 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 7168
c7b8f16e
JB		 7169 if ((insn & 0x100000) == 0)
7170 {
99059e56
RM		 7171 if (is_double)
7172 bfd_arm_vfp11_write_mask (destmask, fm);
7173 else
7174 {
7175 bfd_arm_vfp11_write_mask (destmask, fm);
7176 bfd_arm_vfp11_write_mask (destmask, fm + 1);
7177 }
c7b8f16e
JB		 7178 }
7179
91d6fa6a 7180 vpipe = VFP11_LS;
c7b8f16e
JB		 7181 }
7182 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
7183 {
7184 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
7185 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 7186
c7b8f16e 7187 switch (puw)
99059e56
RM		 7188 {
7189 case 0: /* Two-reg transfer. We should catch these above. */
7190 abort ();
906e58ca 7191
99059e56
RM		 7192 case 2: /* fldm[sdx]. */
7193 case 3:
7194 case 5:
7195 {
7196 unsigned int i, offset = insn & 0xff;
c7b8f16e 7197
99059e56
RM		 7198 if (is_double)
7199 offset >>= 1;
c7b8f16e 7200
99059e56
RM		 7201 for (i = fd; i < fd + offset; i++)
7202 bfd_arm_vfp11_write_mask (destmask, i);
7203 }
7204 break;
906e58ca 7205
99059e56
RM		 7206 case 4: /* fld[sd]. */
7207 case 6:
7208 bfd_arm_vfp11_write_mask (destmask, fd);
7209 break;
906e58ca 7210
99059e56
RM		 7211 default:
7212 return VFP11_BAD;
7213 }
c7b8f16e 7214
91d6fa6a 7215 vpipe = VFP11_LS;
c7b8f16e
JB		 7216 }
7217 /* Single-register transfer. Note L==0. */
7218 else if ((insn & 0x0f100e10) == 0x0e000a10)
7219 {
7220 unsigned int opcode = (insn >> 21) & 7;
7221 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
7222
7223 switch (opcode)
99059e56
RM		 7224 {
7225 case 0: /* fmsr/fmdlr. */
7226 case 1: /* fmdhr. */
7227 /* Mark fmdhr and fmdlr as writing to the whole of the DP
7228 destination register. I don't know if this is exactly right,
7229 but it is the conservative choice. */
7230 bfd_arm_vfp11_write_mask (destmask, fn);
7231 break;
7232
7233 case 7: /* fmxr. */
7234 break;
7235 }
c7b8f16e 7236
91d6fa6a 7237 vpipe = VFP11_LS;
c7b8f16e
JB		 7238 }
7239
91d6fa6a 7240 return vpipe;
c7b8f16e
JB		 7241}
7242
7243
7244static int elf32_arm_compare_mapping (const void * a, const void * b);
7245
7246
7247/* Look for potentially-troublesome code sequences which might trigger the
7248 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
7249 (available from ARM) for details of the erratum. A short version is
7250 described in ld.texinfo. */
7251
7252bfd_boolean
7253bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
7254{
7255 asection *sec;
7256 bfd_byte *contents = NULL;
7257 int state = 0;
7258 int regs[3], numregs = 0;
7259 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7260 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 7261
4dfe6ac6
NC		 7262 if (globals == NULL)
7263 return FALSE;
7264
c7b8f16e
JB		 7265 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
7266 The states transition as follows:
906e58ca 7267
c7b8f16e 7268 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 7269 A VFP FMAC-pipeline instruction has been seen. Fill
7270 regs[0]..regs[numregs-1] with its input operands. Remember this
7271 instruction in 'first_fmac'.
c7b8f16e
JB		 7272
7273 1 -> 2
99059e56
RM		 7274 Any instruction, except for a VFP instruction which overwrites
7275 regs[*].
906e58ca 7276
c7b8f16e
JB		 7277 1 -> 3 [ -> 0 ] or
7278 2 -> 3 [ -> 0 ]
99059e56
RM		 7279 A VFP instruction has been seen which overwrites any of regs[*].
7280 We must make a veneer! Reset state to 0 before examining next
7281 instruction.
906e58ca 7282
c7b8f16e 7283 2 -> 0
99059e56
RM		 7284 If we fail to match anything in state 2, reset to state 0 and reset
7285 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 7286
7287 If the VFP11 vector mode is in use, there must be at least two unrelated
7288 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 7289 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 7290
7291 /* If we are only performing a partial link do not bother
7292 to construct any glue. */
0e1862bb 7293 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 7294 return TRUE;
7295
0ffa91dd
NC		 7296 /* Skip if this bfd does not correspond to an ELF image. */
7297 if (! is_arm_elf (abfd))
7298 return TRUE;
906e58ca 7299
c7b8f16e
JB		 7300 /* We should have chosen a fix type by the time we get here. */
7301 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
7302
7303 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
7304 return TRUE;
2e6030b9 7305
33a7ffc2
JM		 7306 /* Skip this BFD if it corresponds to an executable or dynamic object. */
7307 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
7308 return TRUE;
7309
c7b8f16e
JB		 7310 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7311 {
7312 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
7313 struct _arm_elf_section_data *sec_data;
7314
7315 /* If we don't have executable progbits, we're not interested in this
99059e56 7316 section. Also skip if section is to be excluded. */
c7b8f16e 7317 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 7318 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
7319 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 7320 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 7321 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 7322 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
7323 continue;
c7b8f16e
JB		 7324
7325 sec_data = elf32_arm_section_data (sec);
906e58ca 7326
c7b8f16e 7327 if (sec_data->mapcount == 0)
99059e56 7328 continue;
906e58ca 7329
c7b8f16e
JB		 7330 if (elf_section_data (sec)->this_hdr.contents != NULL)
7331 contents = elf_section_data (sec)->this_hdr.contents;
7332 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
7333 goto error_return;
7334
7335 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
7336 elf32_arm_compare_mapping);
7337
7338 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 7339 {
7340 unsigned int span_start = sec_data->map[span].vma;
7341 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 7342 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 7343 char span_type = sec_data->map[span].type;
7344
7345 /* FIXME: Only ARM mode is supported at present. We may need to
7346 support Thumb-2 mode also at some point. */
7347 if (span_type != 'a')
7348 continue;
7349
7350 for (i = span_start; i < span_end;)
7351 {
7352 unsigned int next_i = i + 4;
7353 unsigned int insn = bfd_big_endian (abfd)
7354 ? (contents[i] << 24)
7355 | (contents[i + 1] << 16)
7356 | (contents[i + 2] << 8)
7357 | contents[i + 3]
7358 : (contents[i + 3] << 24)
7359 | (contents[i + 2] << 16)
7360 | (contents[i + 1] << 8)
7361 | contents[i];
7362 unsigned int writemask = 0;
7363 enum bfd_arm_vfp11_pipe vpipe;
7364
7365 switch (state)
7366 {
7367 case 0:
7368 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
7369 &numregs);
7370 /* I'm assuming the VFP11 erratum can trigger with denorm
7371 operands on either the FMAC or the DS pipeline. This might
7372 lead to slightly overenthusiastic veneer insertion. */
7373 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
7374 {
7375 state = use_vector ? 1 : 2;
7376 first_fmac = i;
7377 veneer_of_insn = insn;
7378 }
7379 break;
7380
7381 case 1:
7382 {
7383 int other_regs[3], other_numregs;
7384 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 7385 other_regs,
99059e56
RM		 7386 &other_numregs);
7387 if (vpipe != VFP11_BAD
7388 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 7389 numregs))
99059e56
RM		 7390 state = 3;
7391 else
7392 state = 2;
7393 }
7394 break;
7395
7396 case 2:
7397 {
7398 int other_regs[3], other_numregs;
7399 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 7400 other_regs,
99059e56
RM		 7401 &other_numregs);
7402 if (vpipe != VFP11_BAD
7403 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 7404 numregs))
99059e56
RM		 7405 state = 3;
7406 else
7407 {
7408 state = 0;
7409 next_i = first_fmac + 4;
7410 }
7411 }
7412 break;
7413
7414 case 3:
7415 abort (); /* Should be unreachable. */
7416 }
7417
7418 if (state == 3)
7419 {
7420 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
7421 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
7422
7423 elf32_arm_section_data (sec)->erratumcount += 1;
7424
7425 newerr->u.b.vfp_insn = veneer_of_insn;
7426
7427 switch (span_type)
7428 {
7429 case 'a':
7430 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
7431 break;
7432
7433 default:
7434 abort ();
7435 }
7436
7437 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 7438 first_fmac);
7439
99059e56 7440 newerr->vma = -1;
c7b8f16e 7441
99059e56
RM		 7442 newerr->next = sec_data->erratumlist;
7443 sec_data->erratumlist = newerr;
c7b8f16e 7444
99059e56
RM		 7445 state = 0;
7446 }
c7b8f16e 7447
99059e56
RM		 7448 i = next_i;
7449 }
7450 }
906e58ca 7451
c7b8f16e 7452 if (contents != NULL
99059e56
RM		 7453 && elf_section_data (sec)->this_hdr.contents != contents)
7454 free (contents);
c7b8f16e
JB		 7455 contents = NULL;
7456 }
7457
7458 return TRUE;
7459
7460error_return:
7461 if (contents != NULL
7462 && elf_section_data (sec)->this_hdr.contents != contents)
7463 free (contents);
906e58ca 7464
c7b8f16e
JB		 7465 return FALSE;
7466}
7467
7468/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
7469 after sections have been laid out, using specially-named symbols. */
7470
7471void
7472bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
7473 struct bfd_link_info *link_info)
7474{
7475 asection *sec;
7476 struct elf32_arm_link_hash_table *globals;
7477 char *tmp_name;
906e58ca 7478
0e1862bb 7479 if (bfd_link_relocatable (link_info))
c7b8f16e 7480 return;
2e6030b9
MS		 7481
7482 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 7483 if (! is_arm_elf (abfd))
2e6030b9
MS		 7484 return;
7485
c7b8f16e 7486 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7487 if (globals == NULL)
7488 return;
906e58ca 7489
21d799b5 7490 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7491 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 7492
7493 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7494 {
7495 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7496 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 7497
c7b8f16e 7498 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 7499 {
7500 struct elf_link_hash_entry *myh;
7501 bfd_vma vma;
7502
7503 switch (errnode->type)
7504 {
7505 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
7506 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
7507 /* Find veneer symbol. */
7508 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 7509 errnode->u.b.veneer->u.v.id);
7510
99059e56
RM		 7511 myh = elf_link_hash_lookup
7512 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 7513
a504d23a
LA		 7514 if (myh == NULL)
7515 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
7516 "`%s'"), abfd, tmp_name);
7517
7518 vma = myh->root.u.def.section->output_section->vma
7519 + myh->root.u.def.section->output_offset
7520 + myh->root.u.def.value;
7521
7522 errnode->u.b.veneer->vma = vma;
7523 break;
7524
7525 case VFP11_ERRATUM_ARM_VENEER:
7526 case VFP11_ERRATUM_THUMB_VENEER:
7527 /* Find return location. */
7528 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7529 errnode->u.v.id);
7530
7531 myh = elf_link_hash_lookup
7532 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7533
7534 if (myh == NULL)
7535 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
7536 "`%s'"), abfd, tmp_name);
7537
7538 vma = myh->root.u.def.section->output_section->vma
7539 + myh->root.u.def.section->output_offset
7540 + myh->root.u.def.value;
7541
7542 errnode->u.v.branch->vma = vma;
7543 break;
7544
7545 default:
7546 abort ();
7547 }
7548 }
7549 }
7550
7551 free (tmp_name);
7552}
7553
7554/* Find virtual-memory addresses for STM32L4XX erratum veneers and
7555 return locations after sections have been laid out, using
7556 specially-named symbols. */
7557
7558void
7559bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
7560 struct bfd_link_info *link_info)
7561{
7562 asection *sec;
7563 struct elf32_arm_link_hash_table *globals;
7564 char *tmp_name;
7565
7566 if (bfd_link_relocatable (link_info))
7567 return;
7568
7569 /* Skip if this bfd does not correspond to an ELF image. */
7570 if (! is_arm_elf (abfd))
7571 return;
7572
7573 globals = elf32_arm_hash_table (link_info);
7574 if (globals == NULL)
7575 return;
7576
7577 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7578 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7579
7580 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7581 {
7582 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7583 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
7584
7585 for (; errnode != NULL; errnode = errnode->next)
7586 {
7587 struct elf_link_hash_entry *myh;
7588 bfd_vma vma;
7589
7590 switch (errnode->type)
7591 {
7592 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
7593 /* Find veneer symbol. */
7594 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7595 errnode->u.b.veneer->u.v.id);
7596
7597 myh = elf_link_hash_lookup
7598 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7599
7600 if (myh == NULL)
7601 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
7602 "`%s'"), abfd, tmp_name);
7603
7604 vma = myh->root.u.def.section->output_section->vma
7605 + myh->root.u.def.section->output_offset
7606 + myh->root.u.def.value;
7607
7608 errnode->u.b.veneer->vma = vma;
7609 break;
7610
7611 case STM32L4XX_ERRATUM_VENEER:
7612 /* Find return location. */
7613 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7614 errnode->u.v.id);
7615
7616 myh = elf_link_hash_lookup
7617 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7618
7619 if (myh == NULL)
7620 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
7621 "`%s'"), abfd, tmp_name);
7622
7623 vma = myh->root.u.def.section->output_section->vma
7624 + myh->root.u.def.section->output_offset
7625 + myh->root.u.def.value;
7626
7627 errnode->u.v.branch->vma = vma;
7628 break;
7629
7630 default:
7631 abort ();
7632 }
7633 }
7634 }
7635
7636 free (tmp_name);
7637}
7638
7639static inline bfd_boolean
7640is_thumb2_ldmia (const insn32 insn)
7641{
7642 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
7643 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
7644 return (insn & 0xffd02000) == 0xe8900000;
7645}
7646
7647static inline bfd_boolean
7648is_thumb2_ldmdb (const insn32 insn)
7649{
7650 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
7651 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
7652 return (insn & 0xffd02000) == 0xe9100000;
7653}
7654
7655static inline bfd_boolean
7656is_thumb2_vldm (const insn32 insn)
7657{
7658 /* A6.5 Extension register load or store instruction
7659 A7.7.229
9239bbd3
CM		 7660 We look for SP 32-bit and DP 64-bit registers.
7661 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
7662 <list> is consecutive 64-bit registers
7663 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
a504d23a
LA		 7664 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
7665 <list> is consecutive 32-bit registers
7666 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
7667 if P==0 && U==1 && W==1 && Rn=1101 VPOP
7668 if PUW=010 || PUW=011 || PUW=101 VLDM. */
7669 return
9239bbd3
CM		 7670 (((insn & 0xfe100f00) == 0xec100b00) ||
7671 ((insn & 0xfe100f00) == 0xec100a00))
a504d23a
LA		 7672 && /* (IA without !). */
7673 (((((insn << 7) >> 28) & 0xd) == 0x4)
9239bbd3 7674 /* (IA with !), includes VPOP (when reg number is SP). */
a504d23a
LA		 7675 || ((((insn << 7) >> 28) & 0xd) == 0x5)
7676 /* (DB with !). */
7677 || ((((insn << 7) >> 28) & 0xd) == 0x9));
7678}
7679
7680/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
7681 VLDM opcode and:
7682 - computes the number and the mode of memory accesses
7683 - decides if the replacement should be done:
7684 . replaces only if > 8-word accesses
7685 . or (testing purposes only) replaces all accesses. */
7686
7687static bfd_boolean
7688stm32l4xx_need_create_replacing_stub (const insn32 insn,
7689 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
7690{
9239bbd3 7691 int nb_words = 0;
a504d23a
LA		 7692
7693 /* The field encoding the register list is the same for both LDMIA
7694 and LDMDB encodings. */
7695 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
9239bbd3 7696 nb_words = popcount (insn & 0x0000ffff);
a504d23a 7697 else if (is_thumb2_vldm (insn))
9239bbd3 7698 nb_words = (insn & 0xff);
a504d23a
LA		 7699
7700 /* DEFAULT mode accounts for the real bug condition situation,
7701 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
7702 return
9239bbd3 7703 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_words > 8 :
a504d23a
LA		 7704 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
7705}
7706
7707/* Look for potentially-troublesome code sequences which might trigger
7708 the STM STM32L4XX erratum. */
7709
7710bfd_boolean
7711bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
7712 struct bfd_link_info *link_info)
7713{
7714 asection *sec;
7715 bfd_byte *contents = NULL;
7716 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7717
7718 if (globals == NULL)
7719 return FALSE;
7720
7721 /* If we are only performing a partial link do not bother
7722 to construct any glue. */
7723 if (bfd_link_relocatable (link_info))
7724 return TRUE;
7725
7726 /* Skip if this bfd does not correspond to an ELF image. */
7727 if (! is_arm_elf (abfd))
7728 return TRUE;
7729
7730 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
7731 return TRUE;
7732
7733 /* Skip this BFD if it corresponds to an executable or dynamic object. */
7734 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
7735 return TRUE;
7736
7737 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7738 {
7739 unsigned int i, span;
7740 struct _arm_elf_section_data *sec_data;
7741
7742 /* If we don't have executable progbits, we're not interested in this
7743 section. Also skip if section is to be excluded. */
7744 if (elf_section_type (sec) != SHT_PROGBITS
7745 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
7746 || (sec->flags & SEC_EXCLUDE) != 0
7747 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
7748 || sec->output_section == bfd_abs_section_ptr
7749 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
7750 continue;
7751
7752 sec_data = elf32_arm_section_data (sec);
c7b8f16e 7753
a504d23a
LA		 7754 if (sec_data->mapcount == 0)
7755 continue;
c7b8f16e 7756
a504d23a
LA		 7757 if (elf_section_data (sec)->this_hdr.contents != NULL)
7758 contents = elf_section_data (sec)->this_hdr.contents;
7759 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
7760 goto error_return;
c7b8f16e 7761
a504d23a
LA		 7762 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
7763 elf32_arm_compare_mapping);
c7b8f16e 7764
a504d23a
LA		 7765 for (span = 0; span < sec_data->mapcount; span++)
7766 {
7767 unsigned int span_start = sec_data->map[span].vma;
7768 unsigned int span_end = (span == sec_data->mapcount - 1)
7769 ? sec->size : sec_data->map[span + 1].vma;
7770 char span_type = sec_data->map[span].type;
7771 int itblock_current_pos = 0;
c7b8f16e 7772
a504d23a
LA		 7773 /* Only Thumb2 mode need be supported with this CM4 specific
7774 code, we should not encounter any arm mode eg span_type
7775 != 'a'. */
7776 if (span_type != 't')
7777 continue;
c7b8f16e 7778
a504d23a
LA		 7779 for (i = span_start; i < span_end;)
7780 {
7781 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
7782 bfd_boolean insn_32bit = FALSE;
7783 bfd_boolean is_ldm = FALSE;
7784 bfd_boolean is_vldm = FALSE;
7785 bfd_boolean is_not_last_in_it_block = FALSE;
7786
7787 /* The first 16-bits of all 32-bit thumb2 instructions start
7788 with opcode[15..13]=0b111 and the encoded op1 can be anything
7789 except opcode[12..11]!=0b00.
7790 See 32-bit Thumb instruction encoding. */
7791 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
7792 insn_32bit = TRUE;
c7b8f16e 7793
a504d23a
LA		 7794 /* Compute the predicate that tells if the instruction
7795 is concerned by the IT block
7796 - Creates an error if there is a ldm that is not
7797 last in the IT block thus cannot be replaced
7798 - Otherwise we can create a branch at the end of the
7799 IT block, it will be controlled naturally by IT
7800 with the proper pseudo-predicate
7801 - So the only interesting predicate is the one that
7802 tells that we are not on the last item of an IT
7803 block. */
7804 if (itblock_current_pos != 0)
7805 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 7806
a504d23a
LA		 7807 if (insn_32bit)
7808 {
7809 /* Load the rest of the insn (in manual-friendly order). */
7810 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
7811 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
7812 is_vldm = is_thumb2_vldm (insn);
7813
7814 /* Veneers are created for (v)ldm depending on
7815 option flags and memory accesses conditions; but
7816 if the instruction is not the last instruction of
7817 an IT block, we cannot create a jump there, so we
7818 bail out. */
7819 if ((is_ldm || is_vldm) &&
7820 stm32l4xx_need_create_replacing_stub
7821 (insn, globals->stm32l4xx_fix))
7822 {
7823 if (is_not_last_in_it_block)
7824 {
7825 (*_bfd_error_handler)
7826 /* Note - overlong line used here to allow for translation. */
7827 (_("\
7828%B(%A+0x%lx): error: multiple load detected in non-last IT block instruction : STM32L4XX veneer cannot be generated.\n"
7829 "Use gcc option -mrestrict-it to generate only one instruction per IT block.\n"),
7830 abfd, sec, (long)i);
7831 }
7832 else
7833 {
7834 elf32_stm32l4xx_erratum_list *newerr =
7835 (elf32_stm32l4xx_erratum_list *)
7836 bfd_zmalloc
7837 (sizeof (elf32_stm32l4xx_erratum_list));
7838
7839 elf32_arm_section_data (sec)
7840 ->stm32l4xx_erratumcount += 1;
7841 newerr->u.b.insn = insn;
7842 /* We create only thumb branches. */
7843 newerr->type =
7844 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
7845 record_stm32l4xx_erratum_veneer
7846 (link_info, newerr, abfd, sec,
7847 i,
7848 is_ldm ?
7849 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
7850 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
7851 newerr->vma = -1;
7852 newerr->next = sec_data->stm32l4xx_erratumlist;
7853 sec_data->stm32l4xx_erratumlist = newerr;
7854 }
7855 }
7856 }
7857 else
7858 {
7859 /* A7.7.37 IT p208
7860 IT blocks are only encoded in T1
7861 Encoding T1: IT{x{y{z}}} <firstcond>
7862 1 0 1 1 - 1 1 1 1 - firstcond - mask
7863 if mask = '0000' then see 'related encodings'
7864 We don't deal with UNPREDICTABLE, just ignore these.
7865 There can be no nested IT blocks so an IT block
7866 is naturally a new one for which it is worth
7867 computing its size. */
7868 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00) &&
7869 ((insn & 0x000f) != 0x0000);
7870 /* If we have a new IT block we compute its size. */
7871 if (is_newitblock)
7872 {
7873 /* Compute the number of instructions controlled
7874 by the IT block, it will be used to decide
7875 whether we are inside an IT block or not. */
7876 unsigned int mask = insn & 0x000f;
7877 itblock_current_pos = 4 - ctz (mask);
7878 }
7879 }
7880
7881 i += insn_32bit ? 4 : 2;
99059e56
RM		 7882 }
7883 }
a504d23a
LA		 7884
7885 if (contents != NULL
7886 && elf_section_data (sec)->this_hdr.contents != contents)
7887 free (contents);
7888 contents = NULL;
c7b8f16e 7889 }
906e58ca 7890
a504d23a
LA		 7891 return TRUE;
7892
7893error_return:
7894 if (contents != NULL
7895 && elf_section_data (sec)->this_hdr.contents != contents)
7896 free (contents);
c7b8f16e 7897
a504d23a
LA		 7898 return FALSE;
7899}
c7b8f16e 7900
eb043451
PB		 7901/* Set target relocation values needed during linking. */
7902
7903void
bf21ed78
MS		 7904bfd_elf32_arm_set_target_relocs (struct bfd *output_bfd,
7905 struct bfd_link_info *link_info,
eb043451 7906 int target1_is_rel,
319850b4 7907 char * target2_type,
99059e56 7908 int fix_v4bx,
c7b8f16e 7909 int use_blx,
99059e56 7910 bfd_arm_vfp11_fix vfp11_fix,
a504d23a 7911 bfd_arm_stm32l4xx_fix stm32l4xx_fix,
a9dc9481 7912 int no_enum_warn, int no_wchar_warn,
2de70689
MGD		 7913 int pic_veneer, int fix_cortex_a8,
7914 int fix_arm1176)
eb043451
PB		 7915{
7916 struct elf32_arm_link_hash_table *globals;
7917
7918 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7919 if (globals == NULL)
7920 return;
eb043451
PB		 7921
7922 globals->target1_is_rel = target1_is_rel;
7923 if (strcmp (target2_type, "rel") == 0)
7924 globals->target2_reloc = R_ARM_REL32;
eeac373a
PB		 7925 else if (strcmp (target2_type, "abs") == 0)
7926 globals->target2_reloc = R_ARM_ABS32;
eb043451
PB		 7927 else if (strcmp (target2_type, "got-rel") == 0)
7928 globals->target2_reloc = R_ARM_GOT_PREL;
7929 else
7930 {
7931 _bfd_error_handler (_("Invalid TARGET2 relocation type '%s'."),
7932 target2_type);
7933 }
319850b4 7934 globals->fix_v4bx = fix_v4bx;
33bfe774 7935 globals->use_blx |= use_blx;
c7b8f16e 7936 globals->vfp11_fix = vfp11_fix;
a504d23a 7937 globals->stm32l4xx_fix = stm32l4xx_fix;
27e55c4d 7938 globals->pic_veneer = pic_veneer;
48229727 7939 globals->fix_cortex_a8 = fix_cortex_a8;
2de70689 7940 globals->fix_arm1176 = fix_arm1176;
bf21ed78 7941
0ffa91dd
NC		 7942 BFD_ASSERT (is_arm_elf (output_bfd));
7943 elf_arm_tdata (output_bfd)->no_enum_size_warning = no_enum_warn;
a9dc9481 7944 elf_arm_tdata (output_bfd)->no_wchar_size_warning = no_wchar_warn;
eb043451 7945}
eb043451 7946
12a0a0fd 7947/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 7948
12a0a0fd
PB		 7949static void
7950insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
7951{
7952 bfd_vma upper;
7953 bfd_vma lower;
7954 int reloc_sign;
7955
7956 BFD_ASSERT ((offset & 1) == 0);
7957
7958 upper = bfd_get_16 (abfd, insn);
7959 lower = bfd_get_16 (abfd, insn + 2);
7960 reloc_sign = (offset < 0) ? 1 : 0;
7961 upper = (upper & ~(bfd_vma) 0x7ff)
7962 | ((offset >> 12) & 0x3ff)
7963 | (reloc_sign << 10);
906e58ca 7964 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 7965 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
7966 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
7967 | ((offset >> 1) & 0x7ff);
7968 bfd_put_16 (abfd, upper, insn);
7969 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 7970}
7971
9b485d32
NC		 7972/* Thumb code calling an ARM function. */
7973
252b5132 7974static int
57e8b36a
NC		 7975elf32_thumb_to_arm_stub (struct bfd_link_info * info,
7976 const char * name,
7977 bfd * input_bfd,
7978 bfd * output_bfd,
7979 asection * input_section,
7980 bfd_byte * hit_data,
7981 asection * sym_sec,
7982 bfd_vma offset,
7983 bfd_signed_vma addend,
f2a9dd69
DJ		 7984 bfd_vma val,
7985 char **error_message)
252b5132 7986{
bcbdc74c 7987 asection * s = 0;
dc810e39 7988 bfd_vma my_offset;
252b5132 7989 long int ret_offset;
bcbdc74c
NC		 7990 struct elf_link_hash_entry * myh;
7991 struct elf32_arm_link_hash_table * globals;
252b5132 7992
f2a9dd69 7993 myh = find_thumb_glue (info, name, error_message);
252b5132 7994 if (myh == NULL)
b34976b6 7995 return FALSE;
252b5132
RH		 7996
7997 globals = elf32_arm_hash_table (info);
252b5132
RH		 7998 BFD_ASSERT (globals != NULL);
7999 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8000
8001 my_offset = myh->root.u.def.value;
8002
3d4d4302
AM		 8003 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8004 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 8005
8006 BFD_ASSERT (s != NULL);
8007 BFD_ASSERT (s->contents != NULL);
8008 BFD_ASSERT (s->output_section != NULL);
8009
8010 if ((my_offset & 0x01) == 0x01)
8011 {
8012 if (sym_sec != NULL
8013 && sym_sec->owner != NULL
8014 && !INTERWORK_FLAG (sym_sec->owner))
8015 {
8f615d07 8016 (*_bfd_error_handler)
d003868e 8017 (_("%B(%s): warning: interworking not enabled.\n"
3aaeb7d3 8018 " first occurrence: %B: Thumb call to ARM"),
d003868e 8019 sym_sec->owner, input_bfd, name);
252b5132 8020
b34976b6 8021 return FALSE;
252b5132
RH		 8022 }
8023
8024 --my_offset;
8025 myh->root.u.def.value = my_offset;
8026
52ab56c2
PB		 8027 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
8028 s->contents + my_offset);
252b5132 8029
52ab56c2
PB		 8030 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
8031 s->contents + my_offset + 2);
252b5132
RH		 8032
8033 ret_offset =
9b485d32
NC		 8034 /* Address of destination of the stub. */
8035 ((bfd_signed_vma) val)
252b5132 8036 - ((bfd_signed_vma)
57e8b36a
NC		 8037 /* Offset from the start of the current section
8038 to the start of the stubs. */
9b485d32
NC		 8039 (s->output_offset
8040 /* Offset of the start of this stub from the start of the stubs. */
8041 + my_offset
8042 /* Address of the start of the current section. */
8043 + s->output_section->vma)
8044 /* The branch instruction is 4 bytes into the stub. */
8045 + 4
8046 /* ARM branches work from the pc of the instruction + 8. */
8047 + 8);
252b5132 8048
52ab56c2
PB		 8049 put_arm_insn (globals, output_bfd,
8050 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
8051 s->contents + my_offset + 4);
252b5132
RH		 8052 }
8053
8054 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
8055
427bfd90
NC		 8056 /* Now go back and fix up the original BL insn to point to here. */
8057 ret_offset =
8058 /* Address of where the stub is located. */
8059 (s->output_section->vma + s->output_offset + my_offset)
8060 /* Address of where the BL is located. */
57e8b36a
NC		 8061 - (input_section->output_section->vma + input_section->output_offset
8062 + offset)
427bfd90
NC		 8063 /* Addend in the relocation. */
8064 - addend
8065 /* Biassing for PC-relative addressing. */
8066 - 8;
252b5132 8067
12a0a0fd 8068 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 8069
b34976b6 8070 return TRUE;
252b5132
RH		 8071}
8072
a4fd1a8e 8073/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 8074
a4fd1a8e
PB		 8075static struct elf_link_hash_entry *
8076elf32_arm_create_thumb_stub (struct bfd_link_info * info,
8077 const char * name,
8078 bfd * input_bfd,
8079 bfd * output_bfd,
8080 asection * sym_sec,
8081 bfd_vma val,
8029a119
NC		 8082 asection * s,
8083 char ** error_message)
252b5132 8084{
dc810e39 8085 bfd_vma my_offset;
252b5132 8086 long int ret_offset;
bcbdc74c
NC		 8087 struct elf_link_hash_entry * myh;
8088 struct elf32_arm_link_hash_table * globals;
252b5132 8089
f2a9dd69 8090 myh = find_arm_glue (info, name, error_message);
252b5132 8091 if (myh == NULL)
a4fd1a8e 8092 return NULL;
252b5132
RH		 8093
8094 globals = elf32_arm_hash_table (info);
252b5132
RH		 8095 BFD_ASSERT (globals != NULL);
8096 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8097
8098 my_offset = myh->root.u.def.value;
252b5132
RH		 8099
8100 if ((my_offset & 0x01) == 0x01)
8101 {
8102 if (sym_sec != NULL
8103 && sym_sec->owner != NULL
8104 && !INTERWORK_FLAG (sym_sec->owner))
8105 {
8f615d07 8106 (*_bfd_error_handler)
d003868e
AM		 8107 (_("%B(%s): warning: interworking not enabled.\n"
8108 " first occurrence: %B: arm call to thumb"),
8109 sym_sec->owner, input_bfd, name);
252b5132 8110 }
9b485d32 8111
252b5132
RH		 8112 --my_offset;
8113 myh->root.u.def.value = my_offset;
8114
0e1862bb
L		 8115 if (bfd_link_pic (info)
8116 || globals->root.is_relocatable_executable
27e55c4d 8117 || globals->pic_veneer)
8f6277f5
PB		 8118 {
8119 /* For relocatable objects we can't use absolute addresses,
8120 so construct the address from a relative offset. */
8121 /* TODO: If the offset is small it's probably worth
8122 constructing the address with adds. */
52ab56c2
PB		 8123 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
8124 s->contents + my_offset);
8125 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
8126 s->contents + my_offset + 4);
8127 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
8128 s->contents + my_offset + 8);
8f6277f5
PB		 8129 /* Adjust the offset by 4 for the position of the add,
8130 and 8 for the pipeline offset. */
8131 ret_offset = (val - (s->output_offset
8132 + s->output_section->vma
8133 + my_offset + 12))
8134 | 1;
8135 bfd_put_32 (output_bfd, ret_offset,
8136 s->contents + my_offset + 12);
8137 }
26079076
PB		 8138 else if (globals->use_blx)
8139 {
8140 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
8141 s->contents + my_offset);
8142
8143 /* It's a thumb address. Add the low order bit. */
8144 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
8145 s->contents + my_offset + 4);
8146 }
8f6277f5
PB		 8147 else
8148 {
52ab56c2
PB		 8149 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
8150 s->contents + my_offset);
252b5132 8151
52ab56c2
PB		 8152 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
8153 s->contents + my_offset + 4);
252b5132 8154
8f6277f5
PB		 8155 /* It's a thumb address. Add the low order bit. */
8156 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
8157 s->contents + my_offset + 8);
8029a119
NC		 8158
8159 my_offset += 12;
8f6277f5 8160 }
252b5132
RH		 8161 }
8162
8163 BFD_ASSERT (my_offset <= globals->arm_glue_size);
8164
a4fd1a8e
PB		 8165 return myh;
8166}
8167
8168/* Arm code calling a Thumb function. */
8169
8170static int
8171elf32_arm_to_thumb_stub (struct bfd_link_info * info,
8172 const char * name,
8173 bfd * input_bfd,
8174 bfd * output_bfd,
8175 asection * input_section,
8176 bfd_byte * hit_data,
8177 asection * sym_sec,
8178 bfd_vma offset,
8179 bfd_signed_vma addend,
f2a9dd69
DJ		 8180 bfd_vma val,
8181 char **error_message)
a4fd1a8e
PB		 8182{
8183 unsigned long int tmp;
8184 bfd_vma my_offset;
8185 asection * s;
8186 long int ret_offset;
8187 struct elf_link_hash_entry * myh;
8188 struct elf32_arm_link_hash_table * globals;
8189
8190 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8191 BFD_ASSERT (globals != NULL);
8192 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8193
3d4d4302
AM		 8194 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8195 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8196 BFD_ASSERT (s != NULL);
8197 BFD_ASSERT (s->contents != NULL);
8198 BFD_ASSERT (s->output_section != NULL);
8199
8200 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 8201 sym_sec, val, s, error_message);
a4fd1a8e
PB		 8202 if (!myh)
8203 return FALSE;
8204
8205 my_offset = myh->root.u.def.value;
252b5132
RH		 8206 tmp = bfd_get_32 (input_bfd, hit_data);
8207 tmp = tmp & 0xFF000000;
8208
9b485d32 8209 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 8210 ret_offset = (s->output_offset
8211 + my_offset
8212 + s->output_section->vma
8213 - (input_section->output_offset
8214 + input_section->output_section->vma
8215 + offset + addend)
8216 - 8);
9a5aca8c 8217
252b5132
RH		 8218 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
8219
dc810e39 8220 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 8221
b34976b6 8222 return TRUE;
252b5132
RH		 8223}
8224
a4fd1a8e
PB		 8225/* Populate Arm stub for an exported Thumb function. */
8226
8227static bfd_boolean
8228elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
8229{
8230 struct bfd_link_info * info = (struct bfd_link_info *) inf;
8231 asection * s;
8232 struct elf_link_hash_entry * myh;
8233 struct elf32_arm_link_hash_entry *eh;
8234 struct elf32_arm_link_hash_table * globals;
8235 asection *sec;
8236 bfd_vma val;
f2a9dd69 8237 char *error_message;
a4fd1a8e 8238
906e58ca 8239 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 8240 /* Allocate stubs for exported Thumb functions on v4t. */
8241 if (eh->export_glue == NULL)
8242 return TRUE;
8243
8244 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8245 BFD_ASSERT (globals != NULL);
8246 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8247
3d4d4302
AM		 8248 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8249 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8250 BFD_ASSERT (s != NULL);
8251 BFD_ASSERT (s->contents != NULL);
8252 BFD_ASSERT (s->output_section != NULL);
8253
8254 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 8255
8256 BFD_ASSERT (sec->output_section != NULL);
8257
a4fd1a8e
PB		 8258 val = eh->export_glue->root.u.def.value + sec->output_offset
8259 + sec->output_section->vma;
8029a119 8260
a4fd1a8e
PB		 8261 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
8262 h->root.u.def.section->owner,
f2a9dd69
DJ		 8263 globals->obfd, sec, val, s,
8264 &error_message);
a4fd1a8e
PB		 8265 BFD_ASSERT (myh);
8266 return TRUE;
8267}
8268
845b51d6
PB		 8269/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
8270
8271static bfd_vma
8272elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
8273{
8274 bfd_byte *p;
8275 bfd_vma glue_addr;
8276 asection *s;
8277 struct elf32_arm_link_hash_table *globals;
8278
8279 globals = elf32_arm_hash_table (info);
845b51d6
PB		 8280 BFD_ASSERT (globals != NULL);
8281 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8282
3d4d4302
AM		 8283 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8284 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 8285 BFD_ASSERT (s != NULL);
8286 BFD_ASSERT (s->contents != NULL);
8287 BFD_ASSERT (s->output_section != NULL);
8288
8289 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
8290
8291 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
8292
8293 if ((globals->bx_glue_offset[reg] & 1) == 0)
8294 {
8295 p = s->contents + glue_addr;
8296 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
8297 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
8298 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
8299 globals->bx_glue_offset[reg] |= 1;
8300 }
8301
8302 return glue_addr + s->output_section->vma + s->output_offset;
8303}
8304
a4fd1a8e
PB		 8305/* Generate Arm stubs for exported Thumb symbols. */
8306static void
906e58ca 8307elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 8308 struct bfd_link_info *link_info)
8309{
8310 struct elf32_arm_link_hash_table * globals;
8311
8029a119
NC		 8312 if (link_info == NULL)
8313 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 8314 return;
8315
8316 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8317 if (globals == NULL)
8318 return;
8319
84c08195
PB		 8320 /* If blx is available then exported Thumb symbols are OK and there is
8321 nothing to do. */
a4fd1a8e
PB		 8322 if (globals->use_blx)
8323 return;
8324
8325 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
8326 link_info);
8327}
8328
47beaa6a
RS		 8329/* Reserve space for COUNT dynamic relocations in relocation selection
8330 SRELOC. */
8331
8332static void
8333elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
8334 bfd_size_type count)
8335{
8336 struct elf32_arm_link_hash_table *htab;
8337
8338 htab = elf32_arm_hash_table (info);
8339 BFD_ASSERT (htab->root.dynamic_sections_created);
8340 if (sreloc == NULL)
8341 abort ();
8342 sreloc->size += RELOC_SIZE (htab) * count;
8343}
8344
34e77a92
RS		 8345/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
8346 dynamic, the relocations should go in SRELOC, otherwise they should
8347 go in the special .rel.iplt section. */
8348
8349static void
8350elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
8351 bfd_size_type count)
8352{
8353 struct elf32_arm_link_hash_table *htab;
8354
8355 htab = elf32_arm_hash_table (info);
8356 if (!htab->root.dynamic_sections_created)
8357 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
8358 else
8359 {
8360 BFD_ASSERT (sreloc != NULL);
8361 sreloc->size += RELOC_SIZE (htab) * count;
8362 }
8363}
8364
47beaa6a
RS		 8365/* Add relocation REL to the end of relocation section SRELOC. */
8366
8367static void
8368elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
8369 asection *sreloc, Elf_Internal_Rela *rel)
8370{
8371 bfd_byte *loc;
8372 struct elf32_arm_link_hash_table *htab;
8373
8374 htab = elf32_arm_hash_table (info);
34e77a92
RS		 8375 if (!htab->root.dynamic_sections_created
8376 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
8377 sreloc = htab->root.irelplt;
47beaa6a
RS		 8378 if (sreloc == NULL)
8379 abort ();
8380 loc = sreloc->contents;
8381 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
8382 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
8383 abort ();
8384 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
8385}
8386
34e77a92
RS		 8387/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
8388 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
8389 to .plt. */
8390
8391static void
8392elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
8393 bfd_boolean is_iplt_entry,
8394 union gotplt_union *root_plt,
8395 struct arm_plt_info *arm_plt)
8396{
8397 struct elf32_arm_link_hash_table *htab;
8398 asection *splt;
8399 asection *sgotplt;
8400
8401 htab = elf32_arm_hash_table (info);
8402
8403 if (is_iplt_entry)
8404 {
8405 splt = htab->root.iplt;
8406 sgotplt = htab->root.igotplt;
8407
99059e56
RM		 8408 /* NaCl uses a special first entry in .iplt too. */
8409 if (htab->nacl_p && splt->size == 0)
8410 splt->size += htab->plt_header_size;
8411
34e77a92
RS		 8412 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
8413 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
8414 }
8415 else
8416 {
8417 splt = htab->root.splt;
8418 sgotplt = htab->root.sgotplt;
8419
8420 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
8421 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
8422
8423 /* If this is the first .plt entry, make room for the special
8424 first entry. */
8425 if (splt->size == 0)
8426 splt->size += htab->plt_header_size;
9f19ab6d
WN		 8427
8428 htab->next_tls_desc_index++;
34e77a92
RS		 8429 }
8430
8431 /* Allocate the PLT entry itself, including any leading Thumb stub. */
8432 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
8433 splt->size += PLT_THUMB_STUB_SIZE;
8434 root_plt->offset = splt->size;
8435 splt->size += htab->plt_entry_size;
8436
8437 if (!htab->symbian_p)
8438 {
8439 /* We also need to make an entry in the .got.plt section, which
8440 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 8441 if (is_iplt_entry)
8442 arm_plt->got_offset = sgotplt->size;
8443 else
8444 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 8445 sgotplt->size += 4;
8446 }
8447}
8448
b38cadfb
NC		 8449static bfd_vma
8450arm_movw_immediate (bfd_vma value)
8451{
8452 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
8453}
8454
8455static bfd_vma
8456arm_movt_immediate (bfd_vma value)
8457{
8458 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
8459}
8460
34e77a92
RS		 8461/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
8462 the entry lives in .iplt and resolves to (*SYM_VALUE)().
8463 Otherwise, DYNINDX is the index of the symbol in the dynamic
8464 symbol table and SYM_VALUE is undefined.
8465
8466 ROOT_PLT points to the offset of the PLT entry from the start of its
8467 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 8468 bookkeeping information.
34e77a92 8469
57460bcf
NC		 8470 Returns FALSE if there was a problem. */
8471
8472static bfd_boolean
34e77a92
RS		 8473elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
8474 union gotplt_union *root_plt,
8475 struct arm_plt_info *arm_plt,
8476 int dynindx, bfd_vma sym_value)
8477{
8478 struct elf32_arm_link_hash_table *htab;
8479 asection *sgot;
8480 asection *splt;
8481 asection *srel;
8482 bfd_byte *loc;
8483 bfd_vma plt_index;
8484 Elf_Internal_Rela rel;
8485 bfd_vma plt_header_size;
8486 bfd_vma got_header_size;
8487
8488 htab = elf32_arm_hash_table (info);
8489
8490 /* Pick the appropriate sections and sizes. */
8491 if (dynindx == -1)
8492 {
8493 splt = htab->root.iplt;
8494 sgot = htab->root.igotplt;
8495 srel = htab->root.irelplt;
8496
8497 /* There are no reserved entries in .igot.plt, and no special
8498 first entry in .iplt. */
8499 got_header_size = 0;
8500 plt_header_size = 0;
8501 }
8502 else
8503 {
8504 splt = htab->root.splt;
8505 sgot = htab->root.sgotplt;
8506 srel = htab->root.srelplt;
8507
8508 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
8509 plt_header_size = htab->plt_header_size;
8510 }
8511 BFD_ASSERT (splt != NULL && srel != NULL);
8512
8513 /* Fill in the entry in the procedure linkage table. */
8514 if (htab->symbian_p)
8515 {
8516 BFD_ASSERT (dynindx >= 0);
8517 put_arm_insn (htab, output_bfd,
8518 elf32_arm_symbian_plt_entry[0],
8519 splt->contents + root_plt->offset);
8520 bfd_put_32 (output_bfd,
8521 elf32_arm_symbian_plt_entry[1],
8522 splt->contents + root_plt->offset + 4);
8523
8524 /* Fill in the entry in the .rel.plt section. */
8525 rel.r_offset = (splt->output_section->vma
8526 + splt->output_offset
8527 + root_plt->offset + 4);
8528 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
8529
8530 /* Get the index in the procedure linkage table which
8531 corresponds to this symbol. This is the index of this symbol
8532 in all the symbols for which we are making plt entries. The
8533 first entry in the procedure linkage table is reserved. */
8534 plt_index = ((root_plt->offset - plt_header_size)
8535 / htab->plt_entry_size);
8536 }
8537 else
8538 {
8539 bfd_vma got_offset, got_address, plt_address;
8540 bfd_vma got_displacement, initial_got_entry;
8541 bfd_byte * ptr;
8542
8543 BFD_ASSERT (sgot != NULL);
8544
8545 /* Get the offset into the .(i)got.plt table of the entry that
8546 corresponds to this function. */
8547 got_offset = (arm_plt->got_offset & -2);
8548
8549 /* Get the index in the procedure linkage table which
8550 corresponds to this symbol. This is the index of this symbol
8551 in all the symbols for which we are making plt entries.
8552 After the reserved .got.plt entries, all symbols appear in
8553 the same order as in .plt. */
8554 plt_index = (got_offset - got_header_size) / 4;
8555
8556 /* Calculate the address of the GOT entry. */
8557 got_address = (sgot->output_section->vma
8558 + sgot->output_offset
8559 + got_offset);
8560
8561 /* ...and the address of the PLT entry. */
8562 plt_address = (splt->output_section->vma
8563 + splt->output_offset
8564 + root_plt->offset);
8565
8566 ptr = splt->contents + root_plt->offset;
0e1862bb 8567 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 8568 {
8569 unsigned int i;
8570 bfd_vma val;
8571
8572 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
8573 {
8574 val = elf32_arm_vxworks_shared_plt_entry[i];
8575 if (i == 2)
8576 val |= got_address - sgot->output_section->vma;
8577 if (i == 5)
8578 val |= plt_index * RELOC_SIZE (htab);
8579 if (i == 2 || i == 5)
8580 bfd_put_32 (output_bfd, val, ptr);
8581 else
8582 put_arm_insn (htab, output_bfd, val, ptr);
8583 }
8584 }
8585 else if (htab->vxworks_p)
8586 {
8587 unsigned int i;
8588 bfd_vma val;
8589
8590 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
8591 {
8592 val = elf32_arm_vxworks_exec_plt_entry[i];
8593 if (i == 2)
8594 val |= got_address;
8595 if (i == 4)
8596 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
8597 if (i == 5)
8598 val |= plt_index * RELOC_SIZE (htab);
8599 if (i == 2 || i == 5)
8600 bfd_put_32 (output_bfd, val, ptr);
8601 else
8602 put_arm_insn (htab, output_bfd, val, ptr);
8603 }
8604
8605 loc = (htab->srelplt2->contents
8606 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
8607
8608 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
8609 referencing the GOT for this PLT entry. */
8610 rel.r_offset = plt_address + 8;
8611 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
8612 rel.r_addend = got_offset;
8613 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8614 loc += RELOC_SIZE (htab);
8615
8616 /* Create the R_ARM_ABS32 relocation referencing the
8617 beginning of the PLT for this GOT entry. */
8618 rel.r_offset = got_address;
8619 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
8620 rel.r_addend = 0;
8621 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8622 }
b38cadfb
NC		 8623 else if (htab->nacl_p)
8624 {
8625 /* Calculate the displacement between the PLT slot and the
8626 common tail that's part of the special initial PLT slot. */
6034aab8 8627 int32_t tail_displacement
b38cadfb
NC		 8628 = ((splt->output_section->vma + splt->output_offset
8629 + ARM_NACL_PLT_TAIL_OFFSET)
8630 - (plt_address + htab->plt_entry_size + 4));
8631 BFD_ASSERT ((tail_displacement & 3) == 0);
8632 tail_displacement >>= 2;
8633
8634 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
8635 || (-tail_displacement & 0xff000000) == 0);
8636
8637 /* Calculate the displacement between the PLT slot and the entry
8638 in the GOT. The offset accounts for the value produced by
8639 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 8640 got_displacement = (got_address
99059e56 8641 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 8642
8643 /* NaCl does not support interworking at all. */
8644 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
8645
8646 put_arm_insn (htab, output_bfd,
8647 elf32_arm_nacl_plt_entry[0]
8648 | arm_movw_immediate (got_displacement),
8649 ptr + 0);
8650 put_arm_insn (htab, output_bfd,
8651 elf32_arm_nacl_plt_entry[1]
8652 | arm_movt_immediate (got_displacement),
8653 ptr + 4);
8654 put_arm_insn (htab, output_bfd,
8655 elf32_arm_nacl_plt_entry[2],
8656 ptr + 8);
8657 put_arm_insn (htab, output_bfd,
8658 elf32_arm_nacl_plt_entry[3]
8659 | (tail_displacement & 0x00ffffff),
8660 ptr + 12);
8661 }
57460bcf
NC		 8662 else if (using_thumb_only (htab))
8663 {
eed94f8f 8664 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 8665 if (!using_thumb2 (htab))
eed94f8f
NC		 8666 {
8667 /* FIXME: We ought to be able to generate thumb-1 PLT
8668 instructions... */
8669 _bfd_error_handler (_("%B: Warning: thumb-1 mode PLT generation not currently supported"),
8670 output_bfd);
8671 return FALSE;
8672 }
57460bcf 8673
eed94f8f
NC		 8674 /* Calculate the displacement between the PLT slot and the entry in
8675 the GOT. The 12-byte offset accounts for the value produced by
8676 adding to pc in the 3rd instruction of the PLT stub. */
8677 got_displacement = got_address - (plt_address + 12);
8678
8679 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
8680 instead of 'put_thumb_insn'. */
8681 put_arm_insn (htab, output_bfd,
8682 elf32_thumb2_plt_entry[0]
8683 | ((got_displacement & 0x000000ff) << 16)
8684 | ((got_displacement & 0x00000700) << 20)
8685 | ((got_displacement & 0x00000800) >> 1)
8686 | ((got_displacement & 0x0000f000) >> 12),
8687 ptr + 0);
8688 put_arm_insn (htab, output_bfd,
8689 elf32_thumb2_plt_entry[1]
8690 | ((got_displacement & 0x00ff0000) )
8691 | ((got_displacement & 0x07000000) << 4)
8692 | ((got_displacement & 0x08000000) >> 17)
8693 | ((got_displacement & 0xf0000000) >> 28),
8694 ptr + 4);
8695 put_arm_insn (htab, output_bfd,
8696 elf32_thumb2_plt_entry[2],
8697 ptr + 8);
8698 put_arm_insn (htab, output_bfd,
8699 elf32_thumb2_plt_entry[3],
8700 ptr + 12);
57460bcf 8701 }
34e77a92
RS		 8702 else
8703 {
8704 /* Calculate the displacement between the PLT slot and the
8705 entry in the GOT. The eight-byte offset accounts for the
8706 value produced by adding to pc in the first instruction
8707 of the PLT stub. */
8708 got_displacement = got_address - (plt_address + 8);
8709
34e77a92
RS		 8710 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
8711 {
8712 put_thumb_insn (htab, output_bfd,
8713 elf32_arm_plt_thumb_stub[0], ptr - 4);
8714 put_thumb_insn (htab, output_bfd,
8715 elf32_arm_plt_thumb_stub[1], ptr - 2);
8716 }
8717
1db37fe6
YG		 8718 if (!elf32_arm_use_long_plt_entry)
8719 {
8720 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
8721
8722 put_arm_insn (htab, output_bfd,
8723 elf32_arm_plt_entry_short[0]
8724 | ((got_displacement & 0x0ff00000) >> 20),
8725 ptr + 0);
8726 put_arm_insn (htab, output_bfd,
8727 elf32_arm_plt_entry_short[1]
8728 | ((got_displacement & 0x000ff000) >> 12),
8729 ptr+ 4);
8730 put_arm_insn (htab, output_bfd,
8731 elf32_arm_plt_entry_short[2]
8732 | (got_displacement & 0x00000fff),
8733 ptr + 8);
34e77a92 8734#ifdef FOUR_WORD_PLT
1db37fe6 8735 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 8736#endif
1db37fe6
YG		 8737 }
8738 else
8739 {
8740 put_arm_insn (htab, output_bfd,
8741 elf32_arm_plt_entry_long[0]
8742 | ((got_displacement & 0xf0000000) >> 28),
8743 ptr + 0);
8744 put_arm_insn (htab, output_bfd,
8745 elf32_arm_plt_entry_long[1]
8746 | ((got_displacement & 0x0ff00000) >> 20),
8747 ptr + 4);
8748 put_arm_insn (htab, output_bfd,
8749 elf32_arm_plt_entry_long[2]
8750 | ((got_displacement & 0x000ff000) >> 12),
8751 ptr+ 8);
8752 put_arm_insn (htab, output_bfd,
8753 elf32_arm_plt_entry_long[3]
8754 | (got_displacement & 0x00000fff),
8755 ptr + 12);
8756 }
34e77a92
RS		 8757 }
8758
8759 /* Fill in the entry in the .rel(a).(i)plt section. */
8760 rel.r_offset = got_address;
8761 rel.r_addend = 0;
8762 if (dynindx == -1)
8763 {
8764 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
8765 The dynamic linker or static executable then calls SYM_VALUE
8766 to determine the correct run-time value of the .igot.plt entry. */
8767 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
8768 initial_got_entry = sym_value;
8769 }
8770 else
8771 {
8772 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
8773 initial_got_entry = (splt->output_section->vma
8774 + splt->output_offset);
8775 }
8776
8777 /* Fill in the entry in the global offset table. */
8778 bfd_put_32 (output_bfd, initial_got_entry,
8779 sgot->contents + got_offset);
8780 }
8781
aba8c3de
WN		 8782 if (dynindx == -1)
8783 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
8784 else
8785 {
8786 loc = srel->contents + plt_index * RELOC_SIZE (htab);
8787 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8788 }
57460bcf
NC		 8789
8790 return TRUE;
34e77a92
RS		 8791}
8792
eb043451
PB		 8793/* Some relocations map to different relocations depending on the
8794 target. Return the real relocation. */
8029a119 8795
eb043451
PB		 8796static int
8797arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
8798 int r_type)
8799{
8800 switch (r_type)
8801 {
8802 case R_ARM_TARGET1:
8803 if (globals->target1_is_rel)
8804 return R_ARM_REL32;
8805 else
8806 return R_ARM_ABS32;
8807
8808 case R_ARM_TARGET2:
8809 return globals->target2_reloc;
8810
8811 default:
8812 return r_type;
8813 }
8814}
eb043451 8815
ba93b8ac
DJ		 8816/* Return the base VMA address which should be subtracted from real addresses
8817 when resolving @dtpoff relocation.
8818 This is PT_TLS segment p_vaddr. */
8819
8820static bfd_vma
8821dtpoff_base (struct bfd_link_info *info)
8822{
8823 /* If tls_sec is NULL, we should have signalled an error already. */
8824 if (elf_hash_table (info)->tls_sec == NULL)
8825 return 0;
8826 return elf_hash_table (info)->tls_sec->vma;
8827}
8828
8829/* Return the relocation value for @tpoff relocation
8830 if STT_TLS virtual address is ADDRESS. */
8831
8832static bfd_vma
8833tpoff (struct bfd_link_info *info, bfd_vma address)
8834{
8835 struct elf_link_hash_table *htab = elf_hash_table (info);
8836 bfd_vma base;
8837
8838 /* If tls_sec is NULL, we should have signalled an error already. */
8839 if (htab->tls_sec == NULL)
8840 return 0;
8841 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
8842 return address - htab->tls_sec->vma + base;
8843}
8844
00a97672
RS		 8845/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
8846 VALUE is the relocation value. */
8847
8848static bfd_reloc_status_type
8849elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
8850{
8851 if (value > 0xfff)
8852 return bfd_reloc_overflow;
8853
8854 value |= bfd_get_32 (abfd, data) & 0xfffff000;
8855 bfd_put_32 (abfd, value, data);
8856 return bfd_reloc_ok;
8857}
8858
0855e32b
NS		 8859/* Handle TLS relaxations. Relaxing is possible for symbols that use
8860 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
8861 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
8862
8863 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
8864 is to then call final_link_relocate. Return other values in the
62672b10
NS		 8865 case of error.
8866
8867 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
8868 the pre-relaxed code. It would be nice if the relocs were updated
8869 to match the optimization. */
0855e32b 8870
b38cadfb 8871static bfd_reloc_status_type
0855e32b 8872elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 8873 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 8874 Elf_Internal_Rela *rel, unsigned long is_local)
8875{
8876 unsigned long insn;
b38cadfb 8877
0855e32b
NS		 8878 switch (ELF32_R_TYPE (rel->r_info))
8879 {
8880 default:
8881 return bfd_reloc_notsupported;
b38cadfb 8882
0855e32b
NS		 8883 case R_ARM_TLS_GOTDESC:
8884 if (is_local)
8885 insn = 0;
8886 else
8887 {
8888 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
8889 if (insn & 1)
8890 insn -= 5; /* THUMB */
8891 else
8892 insn -= 8; /* ARM */
8893 }
8894 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
8895 return bfd_reloc_continue;
8896
8897 case R_ARM_THM_TLS_DESCSEQ:
8898 /* Thumb insn. */
8899 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
8900 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
8901 {
8902 if (is_local)
8903 /* nop */
8904 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8905 }
8906 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
8907 {
8908 if (is_local)
8909 /* nop */
8910 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8911 else
8912 /* ldr rx,[ry] */
8913 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
8914 }
8915 else if ((insn & 0xff87) == 0x4780) /* blx rx */
8916 {
8917 if (is_local)
8918 /* nop */
8919 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8920 else
8921 /* mov r0, rx */
8922 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
8923 contents + rel->r_offset);
8924 }
8925 else
8926 {
8927 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
8928 /* It's a 32 bit instruction, fetch the rest of it for
8929 error generation. */
8930 insn = (insn << 16)
8931 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
8932 (*_bfd_error_handler)
8933 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' in TLS trampoline"),
8934 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
8935 return bfd_reloc_notsupported;
8936 }
8937 break;
b38cadfb 8938
0855e32b
NS		 8939 case R_ARM_TLS_DESCSEQ:
8940 /* arm insn. */
8941 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
8942 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
8943 {
8944 if (is_local)
8945 /* mov rx, ry */
8946 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
8947 contents + rel->r_offset);
8948 }
8949 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
8950 {
8951 if (is_local)
8952 /* nop */
8953 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
8954 else
8955 /* ldr rx,[ry] */
8956 bfd_put_32 (input_bfd, insn & 0xfffff000,
8957 contents + rel->r_offset);
8958 }
8959 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
8960 {
8961 if (is_local)
8962 /* nop */
8963 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
8964 else
8965 /* mov r0, rx */
8966 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
8967 contents + rel->r_offset);
8968 }
8969 else
8970 {
8971 (*_bfd_error_handler)
8972 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' in TLS trampoline"),
8973 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
8974 return bfd_reloc_notsupported;
8975 }
8976 break;
8977
8978 case R_ARM_TLS_CALL:
8979 /* GD->IE relaxation, turn the instruction into 'nop' or
8980 'ldr r0, [pc,r0]' */
8981 insn = is_local ? 0xe1a00000 : 0xe79f0000;
8982 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
8983 break;
b38cadfb 8984
0855e32b 8985 case R_ARM_THM_TLS_CALL:
6a631e86 8986 /* GD->IE relaxation. */
0855e32b
NS		 8987 if (!is_local)
8988 /* add r0,pc; ldr r0, [r0] */
8989 insn = 0x44786800;
8990 else if (arch_has_thumb2_nop (globals))
8991 /* nop.w */
8992 insn = 0xf3af8000;
8993 else
8994 /* nop; nop */
8995 insn = 0xbf00bf00;
b38cadfb 8996
0855e32b
NS		 8997 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
8998 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
8999 break;
9000 }
9001 return bfd_reloc_ok;
9002}
9003
4962c51a
MS		 9004/* For a given value of n, calculate the value of G_n as required to
9005 deal with group relocations. We return it in the form of an
9006 encoded constant-and-rotation, together with the final residual. If n is
9007 specified as less than zero, then final_residual is filled with the
9008 input value and no further action is performed. */
9009
9010static bfd_vma
9011calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
9012{
9013 int current_n;
9014 bfd_vma g_n;
9015 bfd_vma encoded_g_n = 0;
9016 bfd_vma residual = value; /* Also known as Y_n. */
9017
9018 for (current_n = 0; current_n <= n; current_n++)
9019 {
9020 int shift;
9021
9022 /* Calculate which part of the value to mask. */
9023 if (residual == 0)
99059e56 9024 shift = 0;
4962c51a 9025 else
99059e56
RM		 9026 {
9027 int msb;
9028
9029 /* Determine the most significant bit in the residual and
9030 align the resulting value to a 2-bit boundary. */
9031 for (msb = 30; msb >= 0; msb -= 2)
9032 if (residual & (3 << msb))
9033 break;
9034
9035 /* The desired shift is now (msb - 6), or zero, whichever
9036 is the greater. */
9037 shift = msb - 6;
9038 if (shift < 0)
9039 shift = 0;
9040 }
4962c51a
MS		 9041
9042 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
9043 g_n = residual & (0xff << shift);
9044 encoded_g_n = (g_n >> shift)
99059e56 9045 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 9046
9047 /* Calculate the residual for the next time around. */
9048 residual &= ~g_n;
9049 }
9050
9051 *final_residual = residual;
9052
9053 return encoded_g_n;
9054}
9055
9056/* Given an ARM instruction, determine whether it is an ADD or a SUB.
9057 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 9058
4962c51a 9059static int
906e58ca 9060identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 9061{
9062 int opcode = insn & 0x1e00000;
9063
9064 if (opcode == 1 << 23) /* ADD */
9065 return 1;
9066
9067 if (opcode == 1 << 22) /* SUB */
9068 return -1;
9069
9070 return 0;
9071}
9072
252b5132 9073/* Perform a relocation as part of a final link. */
9b485d32 9074
252b5132 9075static bfd_reloc_status_type
57e8b36a
NC		 9076elf32_arm_final_link_relocate (reloc_howto_type * howto,
9077 bfd * input_bfd,
9078 bfd * output_bfd,
9079 asection * input_section,
9080 bfd_byte * contents,
9081 Elf_Internal_Rela * rel,
9082 bfd_vma value,
9083 struct bfd_link_info * info,
9084 asection * sym_sec,
9085 const char * sym_name,
34e77a92
RS		 9086 unsigned char st_type,
9087 enum arm_st_branch_type branch_type,
0945cdfd 9088 struct elf_link_hash_entry * h,
f2a9dd69 9089 bfd_boolean * unresolved_reloc_p,
8029a119 9090 char ** error_message)
252b5132
RH		 9091{
9092 unsigned long r_type = howto->type;
9093 unsigned long r_symndx;
9094 bfd_byte * hit_data = contents + rel->r_offset;
252b5132 9095 bfd_vma * local_got_offsets;
0855e32b 9096 bfd_vma * local_tlsdesc_gotents;
34e77a92
RS		 9097 asection * sgot;
9098 asection * splt;
252b5132 9099 asection * sreloc = NULL;
362d30a1 9100 asection * srelgot;
252b5132 9101 bfd_vma addend;
ba96a88f 9102 bfd_signed_vma signed_addend;
34e77a92
RS		 9103 unsigned char dynreloc_st_type;
9104 bfd_vma dynreloc_value;
ba96a88f 9105 struct elf32_arm_link_hash_table * globals;
34e77a92
RS		 9106 struct elf32_arm_link_hash_entry *eh;
9107 union gotplt_union *root_plt;
9108 struct arm_plt_info *arm_plt;
9109 bfd_vma plt_offset;
9110 bfd_vma gotplt_offset;
9111 bfd_boolean has_iplt_entry;
f21f3fe0 9112
9c504268 9113 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 9114 if (globals == NULL)
9115 return bfd_reloc_notsupported;
9c504268 9116
0ffa91dd
NC		 9117 BFD_ASSERT (is_arm_elf (input_bfd));
9118
9119 /* Some relocation types map to different relocations depending on the
9c504268 9120 target. We pick the right one here. */
eb043451 9121 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 9122
9123 /* It is possible to have linker relaxations on some TLS access
9124 models. Update our information here. */
9125 r_type = elf32_arm_tls_transition (info, r_type, h);
9126
eb043451
PB		 9127 if (r_type != howto->type)
9128 howto = elf32_arm_howto_from_type (r_type);
9c504268 9129
34e77a92 9130 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 9131 sgot = globals->root.sgot;
252b5132 9132 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 9133 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
9134
34e77a92
RS		 9135 if (globals->root.dynamic_sections_created)
9136 srelgot = globals->root.srelgot;
9137 else
9138 srelgot = NULL;
9139
252b5132
RH		 9140 r_symndx = ELF32_R_SYM (rel->r_info);
9141
4e7fd91e 9142 if (globals->use_rel)
ba96a88f 9143 {
4e7fd91e
PB		 9144 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
9145
9146 if (addend & ((howto->src_mask + 1) >> 1))
9147 {
9148 signed_addend = -1;
9149 signed_addend &= ~ howto->src_mask;
9150 signed_addend |= addend;
9151 }
9152 else
9153 signed_addend = addend;
ba96a88f
NC		 9154 }
9155 else
4e7fd91e 9156 addend = signed_addend = rel->r_addend;
f21f3fe0 9157
39f21624
NC		 9158 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
9159 are resolving a function call relocation. */
9160 if (using_thumb_only (globals)
9161 && (r_type == R_ARM_THM_CALL
9162 || r_type == R_ARM_THM_JUMP24)
9163 && branch_type == ST_BRANCH_TO_ARM)
9164 branch_type = ST_BRANCH_TO_THUMB;
9165
34e77a92
RS		 9166 /* Record the symbol information that should be used in dynamic
9167 relocations. */
9168 dynreloc_st_type = st_type;
9169 dynreloc_value = value;
9170 if (branch_type == ST_BRANCH_TO_THUMB)
9171 dynreloc_value |= 1;
9172
9173 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
9174 VALUE appropriately for relocations that we resolve at link time. */
9175 has_iplt_entry = FALSE;
9176 if (elf32_arm_get_plt_info (input_bfd, eh, r_symndx, &root_plt, &arm_plt)
9177 && root_plt->offset != (bfd_vma) -1)
9178 {
9179 plt_offset = root_plt->offset;
9180 gotplt_offset = arm_plt->got_offset;
9181
9182 if (h == NULL || eh->is_iplt)
9183 {
9184 has_iplt_entry = TRUE;
9185 splt = globals->root.iplt;
9186
9187 /* Populate .iplt entries here, because not all of them will
9188 be seen by finish_dynamic_symbol. The lower bit is set if
9189 we have already populated the entry. */
9190 if (plt_offset & 1)
9191 plt_offset--;
9192 else
9193 {
57460bcf
NC		 9194 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
9195 -1, dynreloc_value))
9196 root_plt->offset |= 1;
9197 else
9198 return bfd_reloc_notsupported;
34e77a92
RS		 9199 }
9200
9201 /* Static relocations always resolve to the .iplt entry. */
9202 st_type = STT_FUNC;
9203 value = (splt->output_section->vma
9204 + splt->output_offset
9205 + plt_offset);
9206 branch_type = ST_BRANCH_TO_ARM;
9207
9208 /* If there are non-call relocations that resolve to the .iplt
9209 entry, then all dynamic ones must too. */
9210 if (arm_plt->noncall_refcount != 0)
9211 {
9212 dynreloc_st_type = st_type;
9213 dynreloc_value = value;
9214 }
9215 }
9216 else
9217 /* We populate the .plt entry in finish_dynamic_symbol. */
9218 splt = globals->root.splt;
9219 }
9220 else
9221 {
9222 splt = NULL;
9223 plt_offset = (bfd_vma) -1;
9224 gotplt_offset = (bfd_vma) -1;
9225 }
9226
252b5132
RH		 9227 switch (r_type)
9228 {
9229 case R_ARM_NONE:
28a094c2
DJ		 9230 /* We don't need to find a value for this symbol. It's just a
9231 marker. */
9232 *unresolved_reloc_p = FALSE;
252b5132
RH		 9233 return bfd_reloc_ok;
9234
00a97672
RS		 9235 case R_ARM_ABS12:
9236 if (!globals->vxworks_p)
9237 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
9238
252b5132
RH		 9239 case R_ARM_PC24:
9240 case R_ARM_ABS32:
bb224fc3 9241 case R_ARM_ABS32_NOI:
252b5132 9242 case R_ARM_REL32:
bb224fc3 9243 case R_ARM_REL32_NOI:
5b5bb741
PB		 9244 case R_ARM_CALL:
9245 case R_ARM_JUMP24:
dfc5f959 9246 case R_ARM_XPC25:
eb043451 9247 case R_ARM_PREL31:
7359ea65 9248 case R_ARM_PLT32:
7359ea65
DJ		 9249 /* Handle relocations which should use the PLT entry. ABS32/REL32
9250 will use the symbol's value, which may point to a PLT entry, but we
9251 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 9252 branches in this object should go to it, except if the PLT is too
9253 far away, in which case a long branch stub should be inserted. */
bb224fc3 9254 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 9255 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 9256 && r_type != R_ARM_CALL
9257 && r_type != R_ARM_JUMP24
9258 && r_type != R_ARM_PLT32)
34e77a92 9259 && plt_offset != (bfd_vma) -1)
7359ea65 9260 {
34e77a92
RS		 9261 /* If we've created a .plt section, and assigned a PLT entry
9262 to this function, it must either be a STT_GNU_IFUNC reference
9263 or not be known to bind locally. In other cases, we should
9264 have cleared the PLT entry by now. */
9265 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 9266
9267 value = (splt->output_section->vma
9268 + splt->output_offset
34e77a92 9269 + plt_offset);
0945cdfd 9270 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 9271 return _bfd_final_link_relocate (howto, input_bfd, input_section,
9272 contents, rel->r_offset, value,
00a97672 9273 rel->r_addend);
7359ea65
DJ		 9274 }
9275
67687978
PB		 9276 /* When generating a shared object or relocatable executable, these
9277 relocations are copied into the output file to be resolved at
9278 run time. */
0e1862bb
L		 9279 if ((bfd_link_pic (info)
9280 || globals->root.is_relocatable_executable)
7359ea65 9281 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 9282 && !(globals->vxworks_p
3348747a
NS		 9283 && strcmp (input_section->output_section->name,
9284 ".tls_vars") == 0)
bb224fc3 9285 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 9286 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 9287 && !(input_bfd == globals->stub_bfd
9288 && strstr (input_section->name, STUB_SUFFIX))
7359ea65
DJ		 9289 && (h == NULL
9290 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
9291 || h->root.type != bfd_link_hash_undefweak)
9292 && r_type != R_ARM_PC24
5b5bb741
PB		 9293 && r_type != R_ARM_CALL
9294 && r_type != R_ARM_JUMP24
ee06dc07 9295 && r_type != R_ARM_PREL31
7359ea65 9296 && r_type != R_ARM_PLT32)
252b5132 9297 {
947216bf 9298 Elf_Internal_Rela outrel;
b34976b6 9299 bfd_boolean skip, relocate;
f21f3fe0 9300
52db4ec2
JW		 9301 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
9302 && !h->def_regular)
9303 {
9304 char *v = _("shared object");
9305
0e1862bb 9306 if (bfd_link_executable (info))
52db4ec2
JW		 9307 v = _("PIE executable");
9308
9309 (*_bfd_error_handler)
9310 (_("%B: relocation %s against external or undefined symbol `%s'"
9311 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
9312 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
9313 return bfd_reloc_notsupported;
9314 }
9315
0945cdfd
DJ		 9316 *unresolved_reloc_p = FALSE;
9317
34e77a92 9318 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 9319 {
83bac4b0
NC		 9320 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
9321 ! globals->use_rel);
f21f3fe0 9322
83bac4b0 9323 if (sreloc == NULL)
252b5132 9324 return bfd_reloc_notsupported;
252b5132 9325 }
f21f3fe0 9326
b34976b6
AM		 9327 skip = FALSE;
9328 relocate = FALSE;
f21f3fe0 9329
00a97672 9330 outrel.r_addend = addend;
c629eae0
JJ		 9331 outrel.r_offset =
9332 _bfd_elf_section_offset (output_bfd, info, input_section,
9333 rel->r_offset);
9334 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 9335 skip = TRUE;
0bb2d96a 9336 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 9337 skip = TRUE, relocate = TRUE;
252b5132
RH		 9338 outrel.r_offset += (input_section->output_section->vma
9339 + input_section->output_offset);
f21f3fe0 9340
252b5132 9341 if (skip)
0bb2d96a 9342 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 9343 else if (h != NULL
9344 && h->dynindx != -1
0e1862bb 9345 && (!bfd_link_pic (info)
a496fbc8 9346 || !SYMBOLIC_BIND (info, h)
f5385ebf 9347 || !h->def_regular))
5e681ec4 9348 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 9349 else
9350 {
a16385dc
MM		 9351 int symbol;
9352
5e681ec4 9353 /* This symbol is local, or marked to become local. */
34e77a92 9354 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 9355 if (globals->symbian_p)
6366ff1e 9356 {
74541ad4
AM		 9357 asection *osec;
9358
6366ff1e
MM		 9359 /* On Symbian OS, the data segment and text segement
9360 can be relocated independently. Therefore, we
9361 must indicate the segment to which this
9362 relocation is relative. The BPABI allows us to
9363 use any symbol in the right segment; we just use
9364 the section symbol as it is convenient. (We
9365 cannot use the symbol given by "h" directly as it
74541ad4
AM		 9366 will not appear in the dynamic symbol table.)
9367
9368 Note that the dynamic linker ignores the section
9369 symbol value, so we don't subtract osec->vma
9370 from the emitted reloc addend. */
10dbd1f3 9371 if (sym_sec)
74541ad4 9372 osec = sym_sec->output_section;
10dbd1f3 9373 else
74541ad4
AM		 9374 osec = input_section->output_section;
9375 symbol = elf_section_data (osec)->dynindx;
9376 if (symbol == 0)
9377 {
9378 struct elf_link_hash_table *htab = elf_hash_table (info);
9379
9380 if ((osec->flags & SEC_READONLY) == 0
9381 && htab->data_index_section != NULL)
9382 osec = htab->data_index_section;
9383 else
9384 osec = htab->text_index_section;
9385 symbol = elf_section_data (osec)->dynindx;
9386 }
6366ff1e
MM		 9387 BFD_ASSERT (symbol != 0);
9388 }
a16385dc
MM		 9389 else
9390 /* On SVR4-ish systems, the dynamic loader cannot
9391 relocate the text and data segments independently,
9392 so the symbol does not matter. */
9393 symbol = 0;
34e77a92
RS		 9394 if (dynreloc_st_type == STT_GNU_IFUNC)
9395 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
9396 to the .iplt entry. Instead, every non-call reference
9397 must use an R_ARM_IRELATIVE relocation to obtain the
9398 correct run-time address. */
9399 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
9400 else
9401 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 9402 if (globals->use_rel)
9403 relocate = TRUE;
9404 else
34e77a92 9405 outrel.r_addend += dynreloc_value;
252b5132 9406 }
f21f3fe0 9407
47beaa6a 9408 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 9409
f21f3fe0 9410 /* If this reloc is against an external symbol, we do not want to
252b5132 9411 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 9412 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 9413 if (! relocate)
9414 return bfd_reloc_ok;
9a5aca8c 9415
f21f3fe0 9416 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 9417 contents, rel->r_offset,
9418 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 9419 }
9420 else switch (r_type)
9421 {
00a97672
RS		 9422 case R_ARM_ABS12:
9423 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
9424
dfc5f959 9425 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 9426 case R_ARM_CALL:
9427 case R_ARM_JUMP24:
8029a119 9428 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 9429 case R_ARM_PLT32:
906e58ca 9430 {
906e58ca
NC		 9431 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
9432
dfc5f959 9433 if (r_type == R_ARM_XPC25)
252b5132 9434 {
dfc5f959
NC		 9435 /* Check for Arm calling Arm function. */
9436 /* FIXME: Should we translate the instruction into a BL
9437 instruction instead ? */
35fc36a8 9438 if (branch_type != ST_BRANCH_TO_THUMB)
d003868e
AM		 9439 (*_bfd_error_handler)
9440 (_("\%B: Warning: Arm BLX instruction targets Arm function '%s'."),
9441 input_bfd,
9442 h ? h->root.root.string : "(local)");
dfc5f959 9443 }
155d87d7 9444 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 9445 {
9446 /* Check for Arm calling Thumb function. */
35fc36a8 9447 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 9448 {
f2a9dd69
DJ		 9449 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
9450 output_bfd, input_section,
9451 hit_data, sym_sec, rel->r_offset,
9452 signed_addend, value,
9453 error_message))
9454 return bfd_reloc_ok;
9455 else
9456 return bfd_reloc_dangerous;
dfc5f959 9457 }
252b5132 9458 }
ba96a88f 9459
906e58ca 9460 /* Check if a stub has to be inserted because the
8029a119 9461 destination is too far or we are changing mode. */
155d87d7
CL		 9462 if ( r_type == R_ARM_CALL
9463 || r_type == R_ARM_JUMP24
9464 || r_type == R_ARM_PLT32)
906e58ca 9465 {
fe33d2fa
CL		 9466 enum elf32_arm_stub_type stub_type = arm_stub_none;
9467 struct elf32_arm_link_hash_entry *hash;
9468
9469 hash = (struct elf32_arm_link_hash_entry *) h;
9470 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 9471 st_type, &branch_type,
9472 hash, value, sym_sec,
fe33d2fa 9473 input_bfd, sym_name);
5fa9e92f 9474
fe33d2fa 9475 if (stub_type != arm_stub_none)
906e58ca
NC		 9476 {
9477 /* The target is out of reach, so redirect the
9478 branch to the local stub for this function. */
906e58ca
NC		 9479 stub_entry = elf32_arm_get_stub_entry (input_section,
9480 sym_sec, h,
fe33d2fa
CL		 9481 rel, globals,
9482 stub_type);
9cd3e4e5
NC		 9483 {
9484 if (stub_entry != NULL)
9485 value = (stub_entry->stub_offset
9486 + stub_entry->stub_sec->output_offset
9487 + stub_entry->stub_sec->output_section->vma);
9488
9489 if (plt_offset != (bfd_vma) -1)
9490 *unresolved_reloc_p = FALSE;
9491 }
906e58ca 9492 }
fe33d2fa
CL		 9493 else
9494 {
9495 /* If the call goes through a PLT entry, make sure to
9496 check distance to the right destination address. */
34e77a92 9497 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 9498 {
9499 value = (splt->output_section->vma
9500 + splt->output_offset
34e77a92 9501 + plt_offset);
fe33d2fa
CL		 9502 *unresolved_reloc_p = FALSE;
9503 /* The PLT entry is in ARM mode, regardless of the
9504 target function. */
35fc36a8 9505 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 9506 }
9507 }
906e58ca
NC		 9508 }
9509
dea514f5
PB		 9510 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
9511 where:
9512 S is the address of the symbol in the relocation.
9513 P is address of the instruction being relocated.
9514 A is the addend (extracted from the instruction) in bytes.
9515
9516 S is held in 'value'.
9517 P is the base address of the section containing the
9518 instruction plus the offset of the reloc into that
9519 section, ie:
9520 (input_section->output_section->vma +
9521 input_section->output_offset +
9522 rel->r_offset).
9523 A is the addend, converted into bytes, ie:
9524 (signed_addend * 4)
9525
9526 Note: None of these operations have knowledge of the pipeline
9527 size of the processor, thus it is up to the assembler to
9528 encode this information into the addend. */
9529 value -= (input_section->output_section->vma
9530 + input_section->output_offset);
9531 value -= rel->r_offset;
4e7fd91e
PB		 9532 if (globals->use_rel)
9533 value += (signed_addend << howto->size);
9534 else
9535 /* RELA addends do not have to be adjusted by howto->size. */
9536 value += signed_addend;
23080146 9537
dcb5e6e6
NC		 9538 signed_addend = value;
9539 signed_addend >>= howto->rightshift;
9a5aca8c 9540
5ab79981 9541 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 9542 the next instruction unless a PLT entry will be created.
77b4f08f 9543 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 9544 The jump to the next instruction is optimized as a NOP depending
9545 on the architecture. */
ffcb4889 9546 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 9547 && plt_offset == (bfd_vma) -1)
77b4f08f 9548 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 9549 {
cd1dac3d
DG		 9550 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
9551
9552 if (arch_has_arm_nop (globals))
9553 value |= 0x0320f000;
9554 else
9555 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 9556 }
9557 else
59f2c4e7 9558 {
9b485d32 9559 /* Perform a signed range check. */
dcb5e6e6 9560 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 9561 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
9562 return bfd_reloc_overflow;
9a5aca8c 9563
5ab79981 9564 addend = (value & 2);
39b41c9c 9565
5ab79981
PB		 9566 value = (signed_addend & howto->dst_mask)
9567 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 9568
5ab79981
PB		 9569 if (r_type == R_ARM_CALL)
9570 {
155d87d7 9571 /* Set the H bit in the BLX instruction. */
35fc36a8 9572 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 9573 {
9574 if (addend)
9575 value |= (1 << 24);
9576 else
9577 value &= ~(bfd_vma)(1 << 24);
9578 }
9579
5ab79981 9580 /* Select the correct instruction (BL or BLX). */
906e58ca 9581 /* Only if we are not handling a BL to a stub. In this
8029a119 9582 case, mode switching is performed by the stub. */
35fc36a8 9583 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 9584 value |= (1 << 28);
63e1a0fc 9585 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 9586 {
9587 value &= ~(bfd_vma)(1 << 28);
9588 value |= (1 << 24);
9589 }
39b41c9c
PB		 9590 }
9591 }
906e58ca 9592 }
252b5132 9593 break;
f21f3fe0 9594
252b5132
RH		 9595 case R_ARM_ABS32:
9596 value += addend;
35fc36a8 9597 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 9598 value |= 1;
9599 break;
f21f3fe0 9600
bb224fc3
MS		 9601 case R_ARM_ABS32_NOI:
9602 value += addend;
9603 break;
9604
252b5132 9605 case R_ARM_REL32:
a8bc6c78 9606 value += addend;
35fc36a8 9607 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 9608 value |= 1;
252b5132 9609 value -= (input_section->output_section->vma
62efb346 9610 + input_section->output_offset + rel->r_offset);
252b5132 9611 break;
eb043451 9612
bb224fc3
MS		 9613 case R_ARM_REL32_NOI:
9614 value += addend;
9615 value -= (input_section->output_section->vma
9616 + input_section->output_offset + rel->r_offset);
9617 break;
9618
eb043451
PB		 9619 case R_ARM_PREL31:
9620 value -= (input_section->output_section->vma
9621 + input_section->output_offset + rel->r_offset);
9622 value += signed_addend;
9623 if (! h || h->root.type != bfd_link_hash_undefweak)
9624 {
8029a119 9625 /* Check for overflow. */
eb043451
PB		 9626 if ((value ^ (value >> 1)) & (1 << 30))
9627 return bfd_reloc_overflow;
9628 }
9629 value &= 0x7fffffff;
9630 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 9631 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 9632 value |= 1;
9633 break;
252b5132 9634 }
f21f3fe0 9635
252b5132
RH		 9636 bfd_put_32 (input_bfd, value, hit_data);
9637 return bfd_reloc_ok;
9638
9639 case R_ARM_ABS8:
fd0fd00c
MJ		 9640 /* PR 16202: Refectch the addend using the correct size. */
9641 if (globals->use_rel)
9642 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 9643 value += addend;
4e67d4ca
DG		 9644
9645 /* There is no way to tell whether the user intended to use a signed or
9646 unsigned addend. When checking for overflow we accept either,
9647 as specified by the AAELF. */
9648 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 9649 return bfd_reloc_overflow;
9650
9651 bfd_put_8 (input_bfd, value, hit_data);
9652 return bfd_reloc_ok;
9653
9654 case R_ARM_ABS16:
fd0fd00c
MJ		 9655 /* PR 16202: Refectch the addend using the correct size. */
9656 if (globals->use_rel)
9657 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 9658 value += addend;
9659
4e67d4ca
DG		 9660 /* See comment for R_ARM_ABS8. */
9661 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 9662 return bfd_reloc_overflow;
9663
9664 bfd_put_16 (input_bfd, value, hit_data);
9665 return bfd_reloc_ok;
9666
252b5132 9667 case R_ARM_THM_ABS5:
9b485d32 9668 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 9669 if (globals->use_rel)
9670 {
9671 /* Need to refetch addend. */
9672 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
9673 /* ??? Need to determine shift amount from operand size. */
9674 addend >>= howto->rightshift;
9675 }
252b5132
RH		 9676 value += addend;
9677
9678 /* ??? Isn't value unsigned? */
9679 if ((long) value > 0x1f || (long) value < -0x10)
9680 return bfd_reloc_overflow;
9681
9682 /* ??? Value needs to be properly shifted into place first. */
9683 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
9684 bfd_put_16 (input_bfd, value, hit_data);
9685 return bfd_reloc_ok;
9686
2cab6cc3
MS		 9687 case R_ARM_THM_ALU_PREL_11_0:
9688 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
9689 {
9690 bfd_vma insn;
9691 bfd_signed_vma relocation;
9692
9693 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 9694 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 9695
99059e56
RM		 9696 if (globals->use_rel)
9697 {
9698 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
9699 | ((insn & (1 << 26)) >> 15);
9700 if (insn & 0xf00000)
9701 signed_addend = -signed_addend;
9702 }
2cab6cc3
MS		 9703
9704 relocation = value + signed_addend;
79f08007 9705 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9706 + input_section->output_offset
9707 + rel->r_offset);
2cab6cc3 9708
b6518b38 9709 value = relocation;
2cab6cc3 9710
99059e56
RM		 9711 if (value >= 0x1000)
9712 return bfd_reloc_overflow;
2cab6cc3
MS		 9713
9714 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 9715 | ((value & 0x700) << 4)
9716 | ((value & 0x800) << 15);
9717 if (relocation < 0)
9718 insn |= 0xa00000;
2cab6cc3
MS		 9719
9720 bfd_put_16 (input_bfd, insn >> 16, hit_data);
9721 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
9722
99059e56 9723 return bfd_reloc_ok;
2cab6cc3
MS		 9724 }
9725
e1ec24c6
NC		 9726 case R_ARM_THM_PC8:
9727 /* PR 10073: This reloc is not generated by the GNU toolchain,
9728 but it is supported for compatibility with third party libraries
9729 generated by other compilers, specifically the ARM/IAR. */
9730 {
9731 bfd_vma insn;
9732 bfd_signed_vma relocation;
9733
9734 insn = bfd_get_16 (input_bfd, hit_data);
9735
99059e56 9736 if (globals->use_rel)
79f08007 9737 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 9738
9739 relocation = value + addend;
79f08007 9740 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9741 + input_section->output_offset
9742 + rel->r_offset);
e1ec24c6 9743
b6518b38 9744 value = relocation;
e1ec24c6
NC		 9745
9746 /* We do not check for overflow of this reloc. Although strictly
9747 speaking this is incorrect, it appears to be necessary in order
9748 to work with IAR generated relocs. Since GCC and GAS do not
9749 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
9750 a problem for them. */
9751 value &= 0x3fc;
9752
9753 insn = (insn & 0xff00) | (value >> 2);
9754
9755 bfd_put_16 (input_bfd, insn, hit_data);
9756
99059e56 9757 return bfd_reloc_ok;
e1ec24c6
NC		 9758 }
9759
2cab6cc3
MS		 9760 case R_ARM_THM_PC12:
9761 /* Corresponds to: ldr.w reg, [pc, #offset]. */
9762 {
9763 bfd_vma insn;
9764 bfd_signed_vma relocation;
9765
9766 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 9767 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 9768
99059e56
RM		 9769 if (globals->use_rel)
9770 {
9771 signed_addend = insn & 0xfff;
9772 if (!(insn & (1 << 23)))
9773 signed_addend = -signed_addend;
9774 }
2cab6cc3
MS		 9775
9776 relocation = value + signed_addend;
79f08007 9777 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9778 + input_section->output_offset
9779 + rel->r_offset);
2cab6cc3 9780
b6518b38 9781 value = relocation;
2cab6cc3 9782
99059e56
RM		 9783 if (value >= 0x1000)
9784 return bfd_reloc_overflow;
2cab6cc3
MS		 9785
9786 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 9787 if (relocation >= 0)
9788 insn |= (1 << 23);
2cab6cc3
MS		 9789
9790 bfd_put_16 (input_bfd, insn >> 16, hit_data);
9791 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
9792
99059e56 9793 return bfd_reloc_ok;
2cab6cc3
MS		 9794 }
9795
dfc5f959 9796 case R_ARM_THM_XPC22:
c19d1205 9797 case R_ARM_THM_CALL:
bd97cb95 9798 case R_ARM_THM_JUMP24:
dfc5f959 9799 /* Thumb BL (branch long instruction). */
252b5132 9800 {
b34976b6 9801 bfd_vma relocation;
99059e56 9802 bfd_vma reloc_sign;
b34976b6
AM		 9803 bfd_boolean overflow = FALSE;
9804 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
9805 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 9806 bfd_signed_vma reloc_signed_max;
9807 bfd_signed_vma reloc_signed_min;
b34976b6 9808 bfd_vma check;
252b5132 9809 bfd_signed_vma signed_check;
e95de063 9810 int bitsize;
cd1dac3d 9811 const int thumb2 = using_thumb2 (globals);
252b5132 9812
5ab79981 9813 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 9814 the next instruction unless a PLT entry will be created.
9815 The jump to the next instruction is optimized as a NOP.W for
9816 Thumb-2 enabled architectures. */
19540007 9817 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 9818 && plt_offset == (bfd_vma) -1)
5ab79981 9819 {
cd1dac3d
DG		 9820 if (arch_has_thumb2_nop (globals))
9821 {
9822 bfd_put_16 (input_bfd, 0xf3af, hit_data);
9823 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
9824 }
9825 else
9826 {
9827 bfd_put_16 (input_bfd, 0xe000, hit_data);
9828 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
9829 }
5ab79981
PB		 9830 return bfd_reloc_ok;
9831 }
9832
e95de063 9833 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 9834 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 9835 if (globals->use_rel)
9836 {
99059e56
RM		 9837 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
9838 bfd_vma upper = upper_insn & 0x3ff;
9839 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 9840 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
9841 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 9842 bfd_vma i1 = j1 ^ s ? 0 : 1;
9843 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 9844
99059e56
RM		 9845 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
9846 /* Sign extend. */
9847 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 9848
4e7fd91e
PB		 9849 signed_addend = addend;
9850 }
cb1afa5c 9851
dfc5f959
NC		 9852 if (r_type == R_ARM_THM_XPC22)
9853 {
9854 /* Check for Thumb to Thumb call. */
9855 /* FIXME: Should we translate the instruction into a BL
9856 instruction instead ? */
35fc36a8 9857 if (branch_type == ST_BRANCH_TO_THUMB)
d003868e
AM		 9858 (*_bfd_error_handler)
9859 (_("%B: Warning: Thumb BLX instruction targets thumb function '%s'."),
9860 input_bfd,
9861 h ? h->root.root.string : "(local)");
dfc5f959
NC		 9862 }
9863 else
252b5132 9864 {
dfc5f959
NC		 9865 /* If it is not a call to Thumb, assume call to Arm.
9866 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 9867 function call at all, but rather a long jump. Calls through
9868 the PLT do not require stubs. */
34e77a92 9869 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 9870 {
bd97cb95 9871 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 9872 {
9873 /* Convert BL to BLX. */
9874 lower_insn = (lower_insn & ~0x1000) | 0x0800;
9875 }
155d87d7
CL		 9876 else if (( r_type != R_ARM_THM_CALL)
9877 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 9878 {
9879 if (elf32_thumb_to_arm_stub
9880 (info, sym_name, input_bfd, output_bfd, input_section,
9881 hit_data, sym_sec, rel->r_offset, signed_addend, value,
9882 error_message))
9883 return bfd_reloc_ok;
9884 else
9885 return bfd_reloc_dangerous;
9886 }
da5938a2 9887 }
35fc36a8
RS		 9888 else if (branch_type == ST_BRANCH_TO_THUMB
9889 && globals->use_blx
bd97cb95 9890 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 9891 {
9892 /* Make sure this is a BL. */
9893 lower_insn |= 0x1800;
9894 }
252b5132 9895 }
f21f3fe0 9896
fe33d2fa 9897 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 9898 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 9899 {
9900 /* Check if a stub has to be inserted because the destination
8029a119 9901 is too far. */
fe33d2fa
CL		 9902 struct elf32_arm_stub_hash_entry *stub_entry;
9903 struct elf32_arm_link_hash_entry *hash;
9904
9905 hash = (struct elf32_arm_link_hash_entry *) h;
9906
9907 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 9908 st_type, &branch_type,
9909 hash, value, sym_sec,
fe33d2fa
CL		 9910 input_bfd, sym_name);
9911
9912 if (stub_type != arm_stub_none)
906e58ca
NC		 9913 {
9914 /* The target is out of reach or we are changing modes, so
9915 redirect the branch to the local stub for this
9916 function. */
9917 stub_entry = elf32_arm_get_stub_entry (input_section,
9918 sym_sec, h,
fe33d2fa
CL		 9919 rel, globals,
9920 stub_type);
906e58ca 9921 if (stub_entry != NULL)
9cd3e4e5
NC		 9922 {
9923 value = (stub_entry->stub_offset
9924 + stub_entry->stub_sec->output_offset
9925 + stub_entry->stub_sec->output_section->vma);
9926
9927 if (plt_offset != (bfd_vma) -1)
9928 *unresolved_reloc_p = FALSE;
9929 }
906e58ca 9930
f4ac8484 9931 /* If this call becomes a call to Arm, force BLX. */
155d87d7 9932 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 9933 {
9934 if ((stub_entry
9935 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 9936 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 9937 lower_insn = (lower_insn & ~0x1000) | 0x0800;
9938 }
906e58ca
NC		 9939 }
9940 }
9941
fe33d2fa 9942 /* Handle calls via the PLT. */
34e77a92 9943 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 9944 {
9945 value = (splt->output_section->vma
9946 + splt->output_offset
34e77a92 9947 + plt_offset);
fe33d2fa 9948
eed94f8f
NC		 9949 if (globals->use_blx
9950 && r_type == R_ARM_THM_CALL
9951 && ! using_thumb_only (globals))
fe33d2fa
CL		 9952 {
9953 /* If the Thumb BLX instruction is available, convert
9954 the BL to a BLX instruction to call the ARM-mode
9955 PLT entry. */
9956 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 9957 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 9958 }
9959 else
9960 {
eed94f8f
NC		 9961 if (! using_thumb_only (globals))
9962 /* Target the Thumb stub before the ARM PLT entry. */
9963 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 9964 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 9965 }
9966 *unresolved_reloc_p = FALSE;
9967 }
9968
ba96a88f 9969 relocation = value + signed_addend;
f21f3fe0 9970
252b5132 9971 relocation -= (input_section->output_section->vma
ba96a88f
NC		 9972 + input_section->output_offset
9973 + rel->r_offset);
9a5aca8c 9974
252b5132
RH		 9975 check = relocation >> howto->rightshift;
9976
9977 /* If this is a signed value, the rightshift just dropped
9978 leading 1 bits (assuming twos complement). */
9979 if ((bfd_signed_vma) relocation >= 0)
9980 signed_check = check;
9981 else
9982 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
9983
e95de063
MS		 9984 /* Calculate the permissable maximum and minimum values for
9985 this relocation according to whether we're relocating for
9986 Thumb-2 or not. */
9987 bitsize = howto->bitsize;
9988 if (!thumb2)
9989 bitsize -= 2;
f6ebfac0 9990 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 9991 reloc_signed_min = ~reloc_signed_max;
9992
252b5132 9993 /* Assumes two's complement. */
ba96a88f 9994 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 9995 overflow = TRUE;
252b5132 9996
bd97cb95 9997 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 9998 /* For a BLX instruction, make sure that the relocation is rounded up
9999 to a word boundary. This follows the semantics of the instruction
10000 which specifies that bit 1 of the target address will come from bit
10001 1 of the base address. */
10002 relocation = (relocation + 2) & ~ 3;
cb1afa5c 10003
e95de063
MS		 10004 /* Put RELOCATION back into the insn. Assumes two's complement.
10005 We use the Thumb-2 encoding, which is safe even if dealing with
10006 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 10007 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 10008 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 10009 | ((relocation >> 12) & 0x3ff)
10010 | (reloc_sign << 10);
906e58ca 10011 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 10012 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
10013 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
10014 | ((relocation >> 1) & 0x7ff);
c62e1cc3 10015
252b5132
RH		 10016 /* Put the relocated value back in the object file: */
10017 bfd_put_16 (input_bfd, upper_insn, hit_data);
10018 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10019
10020 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10021 }
10022 break;
10023
c19d1205
ZW		 10024 case R_ARM_THM_JUMP19:
10025 /* Thumb32 conditional branch instruction. */
10026 {
10027 bfd_vma relocation;
10028 bfd_boolean overflow = FALSE;
10029 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
10030 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 10031 bfd_signed_vma reloc_signed_max = 0xffffe;
10032 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 10033 bfd_signed_vma signed_check;
c5423981
TG		 10034 enum elf32_arm_stub_type stub_type = arm_stub_none;
10035 struct elf32_arm_stub_hash_entry *stub_entry;
10036 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 10037
10038 /* Need to refetch the addend, reconstruct the top three bits,
10039 and squish the two 11 bit pieces together. */
10040 if (globals->use_rel)
10041 {
10042 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 10043 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 10044 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
10045 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
10046 bfd_vma lower = (lower_insn & 0x07ff);
10047
a00a1f35
MS		 10048 upper |= J1 << 6;
10049 upper |= J2 << 7;
10050 upper |= (!S) << 8;
c19d1205
ZW		 10051 upper -= 0x0100; /* Sign extend. */
10052
10053 addend = (upper << 12) | (lower << 1);
10054 signed_addend = addend;
10055 }
10056
bd97cb95 10057 /* Handle calls via the PLT. */
34e77a92 10058 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 10059 {
10060 value = (splt->output_section->vma
10061 + splt->output_offset
34e77a92 10062 + plt_offset);
bd97cb95
DJ		 10063 /* Target the Thumb stub before the ARM PLT entry. */
10064 value -= PLT_THUMB_STUB_SIZE;
10065 *unresolved_reloc_p = FALSE;
10066 }
10067
c5423981
TG		 10068 hash = (struct elf32_arm_link_hash_entry *)h;
10069
10070 stub_type = arm_type_of_stub (info, input_section, rel,
10071 st_type, &branch_type,
10072 hash, value, sym_sec,
10073 input_bfd, sym_name);
10074 if (stub_type != arm_stub_none)
10075 {
10076 stub_entry = elf32_arm_get_stub_entry (input_section,
10077 sym_sec, h,
10078 rel, globals,
10079 stub_type);
10080 if (stub_entry != NULL)
10081 {
10082 value = (stub_entry->stub_offset
10083 + stub_entry->stub_sec->output_offset
10084 + stub_entry->stub_sec->output_section->vma);
10085 }
10086 }
c19d1205 10087
99059e56 10088 relocation = value + signed_addend;
c19d1205
ZW		 10089 relocation -= (input_section->output_section->vma
10090 + input_section->output_offset
10091 + rel->r_offset);
a00a1f35 10092 signed_check = (bfd_signed_vma) relocation;
c19d1205 10093
c19d1205
ZW		 10094 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10095 overflow = TRUE;
10096
10097 /* Put RELOCATION back into the insn. */
10098 {
10099 bfd_vma S = (relocation & 0x00100000) >> 20;
10100 bfd_vma J2 = (relocation & 0x00080000) >> 19;
10101 bfd_vma J1 = (relocation & 0x00040000) >> 18;
10102 bfd_vma hi = (relocation & 0x0003f000) >> 12;
10103 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
10104
a00a1f35 10105 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 10106 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
10107 }
10108
10109 /* Put the relocated value back in the object file: */
10110 bfd_put_16 (input_bfd, upper_insn, hit_data);
10111 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10112
10113 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
10114 }
10115
10116 case R_ARM_THM_JUMP11:
10117 case R_ARM_THM_JUMP8:
10118 case R_ARM_THM_JUMP6:
51c5503b
NC		 10119 /* Thumb B (branch) instruction). */
10120 {
6cf9e9fe 10121 bfd_signed_vma relocation;
51c5503b
NC		 10122 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
10123 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 10124 bfd_signed_vma signed_check;
10125
c19d1205
ZW		 10126 /* CZB cannot jump backward. */
10127 if (r_type == R_ARM_THM_JUMP6)
10128 reloc_signed_min = 0;
10129
4e7fd91e 10130 if (globals->use_rel)
6cf9e9fe 10131 {
4e7fd91e
PB		 10132 /* Need to refetch addend. */
10133 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10134 if (addend & ((howto->src_mask + 1) >> 1))
10135 {
10136 signed_addend = -1;
10137 signed_addend &= ~ howto->src_mask;
10138 signed_addend |= addend;
10139 }
10140 else
10141 signed_addend = addend;
10142 /* The value in the insn has been right shifted. We need to
10143 undo this, so that we can perform the address calculation
10144 in terms of bytes. */
10145 signed_addend <<= howto->rightshift;
6cf9e9fe 10146 }
6cf9e9fe 10147 relocation = value + signed_addend;
51c5503b
NC		 10148
10149 relocation -= (input_section->output_section->vma
10150 + input_section->output_offset
10151 + rel->r_offset);
10152
6cf9e9fe
NC		 10153 relocation >>= howto->rightshift;
10154 signed_check = relocation;
c19d1205
ZW		 10155
10156 if (r_type == R_ARM_THM_JUMP6)
10157 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
10158 else
10159 relocation &= howto->dst_mask;
51c5503b 10160 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 10161
51c5503b
NC		 10162 bfd_put_16 (input_bfd, relocation, hit_data);
10163
10164 /* Assumes two's complement. */
10165 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
10166 return bfd_reloc_overflow;
10167
10168 return bfd_reloc_ok;
10169 }
cedb70c5 10170
8375c36b
PB		 10171 case R_ARM_ALU_PCREL7_0:
10172 case R_ARM_ALU_PCREL15_8:
10173 case R_ARM_ALU_PCREL23_15:
10174 {
10175 bfd_vma insn;
10176 bfd_vma relocation;
10177
10178 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 10179 if (globals->use_rel)
10180 {
10181 /* Extract the addend. */
10182 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
10183 signed_addend = addend;
10184 }
8375c36b
PB		 10185 relocation = value + signed_addend;
10186
10187 relocation -= (input_section->output_section->vma
10188 + input_section->output_offset
10189 + rel->r_offset);
10190 insn = (insn & ~0xfff)
10191 | ((howto->bitpos << 7) & 0xf00)
10192 | ((relocation >> howto->bitpos) & 0xff);
10193 bfd_put_32 (input_bfd, value, hit_data);
10194 }
10195 return bfd_reloc_ok;
10196
252b5132
RH		 10197 case R_ARM_GNU_VTINHERIT:
10198 case R_ARM_GNU_VTENTRY:
10199 return bfd_reloc_ok;
10200
c19d1205 10201 case R_ARM_GOTOFF32:
252b5132 10202 /* Relocation is relative to the start of the
99059e56 10203 global offset table. */
252b5132
RH		 10204
10205 BFD_ASSERT (sgot != NULL);
10206 if (sgot == NULL)
99059e56 10207 return bfd_reloc_notsupported;
9a5aca8c 10208
cedb70c5 10209 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 10210 address by one, so that attempts to call the function pointer will
10211 correctly interpret it as Thumb code. */
35fc36a8 10212 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 10213 value += 1;
10214
252b5132 10215 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 10216 calculation. We always want the start of .got. If we
10217 define _GLOBAL_OFFSET_TABLE in a different way, as is
10218 permitted by the ABI, we might have to change this
10219 calculation. */
252b5132 10220 value -= sgot->output_section->vma;
f21f3fe0 10221 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10222 contents, rel->r_offset, value,
00a97672 10223 rel->r_addend);
252b5132
RH		 10224
10225 case R_ARM_GOTPC:
a7c10850 10226 /* Use global offset table as symbol value. */
252b5132 10227 BFD_ASSERT (sgot != NULL);
f21f3fe0 10228
252b5132 10229 if (sgot == NULL)
99059e56 10230 return bfd_reloc_notsupported;
252b5132 10231
0945cdfd 10232 *unresolved_reloc_p = FALSE;
252b5132 10233 value = sgot->output_section->vma;
f21f3fe0 10234 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10235 contents, rel->r_offset, value,
00a97672 10236 rel->r_addend);
f21f3fe0 10237
252b5132 10238 case R_ARM_GOT32:
eb043451 10239 case R_ARM_GOT_PREL:
252b5132 10240 /* Relocation is to the entry for this symbol in the
99059e56 10241 global offset table. */
252b5132
RH		 10242 if (sgot == NULL)
10243 return bfd_reloc_notsupported;
f21f3fe0 10244
34e77a92
RS		 10245 if (dynreloc_st_type == STT_GNU_IFUNC
10246 && plt_offset != (bfd_vma) -1
10247 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
10248 {
10249 /* We have a relocation against a locally-binding STT_GNU_IFUNC
10250 symbol, and the relocation resolves directly to the runtime
10251 target rather than to the .iplt entry. This means that any
10252 .got entry would be the same value as the .igot.plt entry,
10253 so there's no point creating both. */
10254 sgot = globals->root.igotplt;
10255 value = sgot->output_offset + gotplt_offset;
10256 }
10257 else if (h != NULL)
252b5132
RH		 10258 {
10259 bfd_vma off;
f21f3fe0 10260
252b5132
RH		 10261 off = h->got.offset;
10262 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 10263 if ((off & 1) != 0)
252b5132 10264 {
b436d854
RS		 10265 /* We have already processsed one GOT relocation against
10266 this symbol. */
10267 off &= ~1;
10268 if (globals->root.dynamic_sections_created
10269 && !SYMBOL_REFERENCES_LOCAL (info, h))
10270 *unresolved_reloc_p = FALSE;
10271 }
10272 else
10273 {
10274 Elf_Internal_Rela outrel;
10275
6f820c85 10276 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 10277 {
10278 /* If the symbol doesn't resolve locally in a static
10279 object, we have an undefined reference. If the
10280 symbol doesn't resolve locally in a dynamic object,
10281 it should be resolved by the dynamic linker. */
10282 if (globals->root.dynamic_sections_created)
10283 {
10284 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
10285 *unresolved_reloc_p = FALSE;
10286 }
10287 else
10288 outrel.r_info = 0;
10289 outrel.r_addend = 0;
10290 }
252b5132
RH		 10291 else
10292 {
34e77a92 10293 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 10294 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
0e1862bb 10295 else if (bfd_link_pic (info) &&
31943882
WN		 10296 (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10297 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 10298 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
10299 else
10300 outrel.r_info = 0;
34e77a92 10301 outrel.r_addend = dynreloc_value;
b436d854 10302 }
ee29b9fb 10303
b436d854
RS		 10304 /* The GOT entry is initialized to zero by default.
10305 See if we should install a different value. */
10306 if (outrel.r_addend != 0
10307 && (outrel.r_info == 0 || globals->use_rel))
10308 {
10309 bfd_put_32 (output_bfd, outrel.r_addend,
10310 sgot->contents + off);
10311 outrel.r_addend = 0;
252b5132 10312 }
f21f3fe0 10313
b436d854
RS		 10314 if (outrel.r_info != 0)
10315 {
10316 outrel.r_offset = (sgot->output_section->vma
10317 + sgot->output_offset
10318 + off);
10319 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
10320 }
10321 h->got.offset |= 1;
10322 }
252b5132
RH		 10323 value = sgot->output_offset + off;
10324 }
10325 else
10326 {
10327 bfd_vma off;
f21f3fe0 10328
252b5132
RH		 10329 BFD_ASSERT (local_got_offsets != NULL &&
10330 local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 10331
252b5132 10332 off = local_got_offsets[r_symndx];
f21f3fe0 10333
252b5132
RH		 10334 /* The offset must always be a multiple of 4. We use the
10335 least significant bit to record whether we have already
9b485d32 10336 generated the necessary reloc. */
252b5132
RH		 10337 if ((off & 1) != 0)
10338 off &= ~1;
10339 else
10340 {
00a97672 10341 if (globals->use_rel)
34e77a92 10342 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 10343
0e1862bb 10344 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 10345 {
947216bf 10346 Elf_Internal_Rela outrel;
f21f3fe0 10347
34e77a92 10348 outrel.r_addend = addend + dynreloc_value;
252b5132 10349 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 10350 + sgot->output_offset
252b5132 10351 + off);
34e77a92 10352 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 10353 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 10354 else
10355 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 10356 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 10357 }
f21f3fe0 10358
252b5132
RH		 10359 local_got_offsets[r_symndx] |= 1;
10360 }
f21f3fe0 10361
252b5132
RH		 10362 value = sgot->output_offset + off;
10363 }
eb043451
PB		 10364 if (r_type != R_ARM_GOT32)
10365 value += sgot->output_section->vma;
9a5aca8c 10366
f21f3fe0 10367 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10368 contents, rel->r_offset, value,
00a97672 10369 rel->r_addend);
f21f3fe0 10370
ba93b8ac
DJ		 10371 case R_ARM_TLS_LDO32:
10372 value = value - dtpoff_base (info);
10373
10374 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 10375 contents, rel->r_offset, value,
10376 rel->r_addend);
ba93b8ac
DJ		 10377
10378 case R_ARM_TLS_LDM32:
10379 {
10380 bfd_vma off;
10381
362d30a1 10382 if (sgot == NULL)
ba93b8ac
DJ		 10383 abort ();
10384
10385 off = globals->tls_ldm_got.offset;
10386
10387 if ((off & 1) != 0)
10388 off &= ~1;
10389 else
10390 {
10391 /* If we don't know the module number, create a relocation
10392 for it. */
0e1862bb 10393 if (bfd_link_pic (info))
ba93b8ac
DJ		 10394 {
10395 Elf_Internal_Rela outrel;
ba93b8ac 10396
362d30a1 10397 if (srelgot == NULL)
ba93b8ac
DJ		 10398 abort ();
10399
00a97672 10400 outrel.r_addend = 0;
362d30a1
RS		 10401 outrel.r_offset = (sgot->output_section->vma
10402 + sgot->output_offset + off);
ba93b8ac
DJ		 10403 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
10404
00a97672
RS		 10405 if (globals->use_rel)
10406 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10407 sgot->contents + off);
ba93b8ac 10408
47beaa6a 10409 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10410 }
10411 else
362d30a1 10412 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 10413
10414 globals->tls_ldm_got.offset |= 1;
10415 }
10416
362d30a1 10417 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 10418 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
10419
10420 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10421 contents, rel->r_offset, value,
00a97672 10422 rel->r_addend);
ba93b8ac
DJ		 10423 }
10424
0855e32b
NS		 10425 case R_ARM_TLS_CALL:
10426 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 10427 case R_ARM_TLS_GD32:
10428 case R_ARM_TLS_IE32:
0855e32b
NS		 10429 case R_ARM_TLS_GOTDESC:
10430 case R_ARM_TLS_DESCSEQ:
10431 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 10432 {
0855e32b
NS		 10433 bfd_vma off, offplt;
10434 int indx = 0;
ba93b8ac
DJ		 10435 char tls_type;
10436
0855e32b 10437 BFD_ASSERT (sgot != NULL);
ba93b8ac 10438
ba93b8ac
DJ		 10439 if (h != NULL)
10440 {
10441 bfd_boolean dyn;
10442 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 10443 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
10444 bfd_link_pic (info),
10445 h)
10446 && (!bfd_link_pic (info)
ba93b8ac
DJ		 10447 || !SYMBOL_REFERENCES_LOCAL (info, h)))
10448 {
10449 *unresolved_reloc_p = FALSE;
10450 indx = h->dynindx;
10451 }
10452 off = h->got.offset;
0855e32b 10453 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 10454 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
10455 }
10456 else
10457 {
0855e32b 10458 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 10459 off = local_got_offsets[r_symndx];
0855e32b 10460 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 10461 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
10462 }
10463
0855e32b 10464 /* Linker relaxations happens from one of the
b38cadfb 10465 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 10466 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 10467 tls_type = GOT_TLS_IE;
0855e32b
NS		 10468
10469 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 10470
10471 if ((off & 1) != 0)
10472 off &= ~1;
10473 else
10474 {
10475 bfd_boolean need_relocs = FALSE;
10476 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 10477 int cur_off = off;
10478
10479 /* The GOT entries have not been initialized yet. Do it
10480 now, and emit any relocations. If both an IE GOT and a
10481 GD GOT are necessary, we emit the GD first. */
10482
0e1862bb 10483 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 10484 && (h == NULL
10485 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10486 || h->root.type != bfd_link_hash_undefweak))
10487 {
10488 need_relocs = TRUE;
0855e32b 10489 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 10490 }
10491
0855e32b
NS		 10492 if (tls_type & GOT_TLS_GDESC)
10493 {
47beaa6a
RS		 10494 bfd_byte *loc;
10495
0855e32b
NS		 10496 /* We should have relaxed, unless this is an undefined
10497 weak symbol. */
10498 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 10499 || bfd_link_pic (info));
0855e32b 10500 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 10501 <= globals->root.sgotplt->size);
0855e32b
NS		 10502
10503 outrel.r_addend = 0;
10504 outrel.r_offset = (globals->root.sgotplt->output_section->vma
10505 + globals->root.sgotplt->output_offset
10506 + offplt
10507 + globals->sgotplt_jump_table_size);
b38cadfb 10508
0855e32b
NS		 10509 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
10510 sreloc = globals->root.srelplt;
10511 loc = sreloc->contents;
10512 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
10513 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 10514 <= sreloc->contents + sreloc->size);
0855e32b
NS		 10515
10516 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
10517
10518 /* For globals, the first word in the relocation gets
10519 the relocation index and the top bit set, or zero,
10520 if we're binding now. For locals, it gets the
10521 symbol's offset in the tls section. */
99059e56 10522 bfd_put_32 (output_bfd,
0855e32b
NS		 10523 !h ? value - elf_hash_table (info)->tls_sec->vma
10524 : info->flags & DF_BIND_NOW ? 0
10525 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 10526 globals->root.sgotplt->contents + offplt
10527 + globals->sgotplt_jump_table_size);
10528
0855e32b 10529 /* Second word in the relocation is always zero. */
99059e56 10530 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 10531 globals->root.sgotplt->contents + offplt
10532 + globals->sgotplt_jump_table_size + 4);
0855e32b 10533 }
ba93b8ac
DJ		 10534 if (tls_type & GOT_TLS_GD)
10535 {
10536 if (need_relocs)
10537 {
00a97672 10538 outrel.r_addend = 0;
362d30a1
RS		 10539 outrel.r_offset = (sgot->output_section->vma
10540 + sgot->output_offset
00a97672 10541 + cur_off);
ba93b8ac 10542 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 10543
00a97672
RS		 10544 if (globals->use_rel)
10545 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10546 sgot->contents + cur_off);
00a97672 10547
47beaa6a 10548 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10549
10550 if (indx == 0)
10551 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 10552 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 10553 else
10554 {
00a97672 10555 outrel.r_addend = 0;
ba93b8ac
DJ		 10556 outrel.r_info = ELF32_R_INFO (indx,
10557 R_ARM_TLS_DTPOFF32);
10558 outrel.r_offset += 4;
00a97672
RS		 10559
10560 if (globals->use_rel)
10561 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10562 sgot->contents + cur_off + 4);
00a97672 10563
47beaa6a
RS		 10564 elf32_arm_add_dynreloc (output_bfd, info,
10565 srelgot, &outrel);
ba93b8ac
DJ		 10566 }
10567 }
10568 else
10569 {
10570 /* If we are not emitting relocations for a
10571 general dynamic reference, then we must be in a
10572 static link or an executable link with the
10573 symbol binding locally. Mark it as belonging
10574 to module 1, the executable. */
10575 bfd_put_32 (output_bfd, 1,
362d30a1 10576 sgot->contents + cur_off);
ba93b8ac 10577 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 10578 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 10579 }
10580
10581 cur_off += 8;
10582 }
10583
10584 if (tls_type & GOT_TLS_IE)
10585 {
10586 if (need_relocs)
10587 {
00a97672
RS		 10588 if (indx == 0)
10589 outrel.r_addend = value - dtpoff_base (info);
10590 else
10591 outrel.r_addend = 0;
362d30a1
RS		 10592 outrel.r_offset = (sgot->output_section->vma
10593 + sgot->output_offset
ba93b8ac
DJ		 10594 + cur_off);
10595 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
10596
00a97672
RS		 10597 if (globals->use_rel)
10598 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10599 sgot->contents + cur_off);
ba93b8ac 10600
47beaa6a 10601 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10602 }
10603 else
10604 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 10605 sgot->contents + cur_off);
ba93b8ac
DJ		 10606 cur_off += 4;
10607 }
10608
10609 if (h != NULL)
10610 h->got.offset |= 1;
10611 else
10612 local_got_offsets[r_symndx] |= 1;
10613 }
10614
10615 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
10616 off += 8;
0855e32b
NS		 10617 else if (tls_type & GOT_TLS_GDESC)
10618 off = offplt;
10619
10620 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
10621 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
10622 {
10623 bfd_signed_vma offset;
12352d3f
PB		 10624 /* TLS stubs are arm mode. The original symbol is a
10625 data object, so branch_type is bogus. */
10626 branch_type = ST_BRANCH_TO_ARM;
0855e32b 10627 enum elf32_arm_stub_type stub_type
34e77a92
RS		 10628 = arm_type_of_stub (info, input_section, rel,
10629 st_type, &branch_type,
0855e32b
NS		 10630 (struct elf32_arm_link_hash_entry *)h,
10631 globals->tls_trampoline, globals->root.splt,
10632 input_bfd, sym_name);
10633
10634 if (stub_type != arm_stub_none)
10635 {
10636 struct elf32_arm_stub_hash_entry *stub_entry
10637 = elf32_arm_get_stub_entry
10638 (input_section, globals->root.splt, 0, rel,
10639 globals, stub_type);
10640 offset = (stub_entry->stub_offset
10641 + stub_entry->stub_sec->output_offset
10642 + stub_entry->stub_sec->output_section->vma);
10643 }
10644 else
10645 offset = (globals->root.splt->output_section->vma
10646 + globals->root.splt->output_offset
10647 + globals->tls_trampoline);
10648
10649 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
10650 {
10651 unsigned long inst;
b38cadfb
NC		 10652
10653 offset -= (input_section->output_section->vma
10654 + input_section->output_offset
10655 + rel->r_offset + 8);
0855e32b
NS		 10656
10657 inst = offset >> 2;
10658 inst &= 0x00ffffff;
10659 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
10660 }
10661 else
10662 {
10663 /* Thumb blx encodes the offset in a complicated
10664 fashion. */
10665 unsigned upper_insn, lower_insn;
10666 unsigned neg;
10667
b38cadfb
NC		 10668 offset -= (input_section->output_section->vma
10669 + input_section->output_offset
0855e32b 10670 + rel->r_offset + 4);
b38cadfb 10671
12352d3f
PB		 10672 if (stub_type != arm_stub_none
10673 && arm_stub_is_thumb (stub_type))
10674 {
10675 lower_insn = 0xd000;
10676 }
10677 else
10678 {
10679 lower_insn = 0xc000;
6a631e86 10680 /* Round up the offset to a word boundary. */
12352d3f
PB		 10681 offset = (offset + 2) & ~2;
10682 }
10683
0855e32b
NS		 10684 neg = offset < 0;
10685 upper_insn = (0xf000
10686 | ((offset >> 12) & 0x3ff)
10687 | (neg << 10));
12352d3f 10688 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 10689 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 10690 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 10691 bfd_put_16 (input_bfd, upper_insn, hit_data);
10692 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10693 return bfd_reloc_ok;
10694 }
10695 }
10696 /* These relocations needs special care, as besides the fact
10697 they point somewhere in .gotplt, the addend must be
10698 adjusted accordingly depending on the type of instruction
6a631e86 10699 we refer to. */
0855e32b
NS		 10700 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
10701 {
10702 unsigned long data, insn;
10703 unsigned thumb;
b38cadfb 10704
0855e32b
NS		 10705 data = bfd_get_32 (input_bfd, hit_data);
10706 thumb = data & 1;
10707 data &= ~1u;
b38cadfb 10708
0855e32b
NS		 10709 if (thumb)
10710 {
10711 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
10712 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10713 insn = (insn << 16)
10714 | bfd_get_16 (input_bfd,
10715 contents + rel->r_offset - data + 2);
10716 if ((insn & 0xf800c000) == 0xf000c000)
10717 /* bl/blx */
10718 value = -6;
10719 else if ((insn & 0xffffff00) == 0x4400)
10720 /* add */
10721 value = -5;
10722 else
10723 {
10724 (*_bfd_error_handler)
10725 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' referenced by TLS_GOTDESC"),
10726 input_bfd, input_section,
10727 (unsigned long)rel->r_offset, insn);
10728 return bfd_reloc_notsupported;
10729 }
10730 }
10731 else
10732 {
10733 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
10734
10735 switch (insn >> 24)
10736 {
10737 case 0xeb: /* bl */
10738 case 0xfa: /* blx */
10739 value = -4;
10740 break;
10741
10742 case 0xe0: /* add */
10743 value = -8;
10744 break;
b38cadfb 10745
0855e32b
NS		 10746 default:
10747 (*_bfd_error_handler)
10748 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' referenced by TLS_GOTDESC"),
10749 input_bfd, input_section,
10750 (unsigned long)rel->r_offset, insn);
10751 return bfd_reloc_notsupported;
10752 }
10753 }
b38cadfb 10754
0855e32b
NS		 10755 value += ((globals->root.sgotplt->output_section->vma
10756 + globals->root.sgotplt->output_offset + off)
10757 - (input_section->output_section->vma
10758 + input_section->output_offset
10759 + rel->r_offset)
10760 + globals->sgotplt_jump_table_size);
10761 }
10762 else
10763 value = ((globals->root.sgot->output_section->vma
10764 + globals->root.sgot->output_offset + off)
10765 - (input_section->output_section->vma
10766 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 10767
10768 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10769 contents, rel->r_offset, value,
00a97672 10770 rel->r_addend);
ba93b8ac
DJ		 10771 }
10772
10773 case R_ARM_TLS_LE32:
3cbc1e5e 10774 if (bfd_link_dll (info))
ba93b8ac
DJ		 10775 {
10776 (*_bfd_error_handler)
10777 (_("%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object"),
10778 input_bfd, input_section,
10779 (long) rel->r_offset, howto->name);
46691134 10780 return bfd_reloc_notsupported;
ba93b8ac
DJ		 10781 }
10782 else
10783 value = tpoff (info, value);
906e58ca 10784
ba93b8ac 10785 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 10786 contents, rel->r_offset, value,
10787 rel->r_addend);
ba93b8ac 10788
319850b4
JB		 10789 case R_ARM_V4BX:
10790 if (globals->fix_v4bx)
845b51d6
PB		 10791 {
10792 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 10793
845b51d6
PB		 10794 /* Ensure that we have a BX instruction. */
10795 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 10796
845b51d6
PB		 10797 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
10798 {
10799 /* Branch to veneer. */
10800 bfd_vma glue_addr;
10801 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
10802 glue_addr -= input_section->output_section->vma
10803 + input_section->output_offset
10804 + rel->r_offset + 8;
10805 insn = (insn & 0xf0000000) | 0x0a000000
10806 | ((glue_addr >> 2) & 0x00ffffff);
10807 }
10808 else
10809 {
10810 /* Preserve Rm (lowest four bits) and the condition code
10811 (highest four bits). Other bits encode MOV PC,Rm. */
10812 insn = (insn & 0xf000000f) | 0x01a0f000;
10813 }
319850b4 10814
845b51d6
PB		 10815 bfd_put_32 (input_bfd, insn, hit_data);
10816 }
319850b4
JB		 10817 return bfd_reloc_ok;
10818
b6895b4f
PB		 10819 case R_ARM_MOVW_ABS_NC:
10820 case R_ARM_MOVT_ABS:
10821 case R_ARM_MOVW_PREL_NC:
10822 case R_ARM_MOVT_PREL:
92f5d02b
MS		 10823 /* Until we properly support segment-base-relative addressing then
10824 we assume the segment base to be zero, as for the group relocations.
10825 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
10826 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
10827 case R_ARM_MOVW_BREL_NC:
10828 case R_ARM_MOVW_BREL:
10829 case R_ARM_MOVT_BREL:
b6895b4f
PB		 10830 {
10831 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
10832
10833 if (globals->use_rel)
10834 {
10835 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 10836 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 10837 }
92f5d02b 10838
b6895b4f 10839 value += signed_addend;
b6895b4f
PB		 10840
10841 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
10842 value -= (input_section->output_section->vma
10843 + input_section->output_offset + rel->r_offset);
10844
92f5d02b 10845 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 10846 return bfd_reloc_overflow;
92f5d02b 10847
35fc36a8 10848 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 10849 value |= 1;
10850
10851 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 10852 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 10853 value >>= 16;
10854
10855 insn &= 0xfff0f000;
10856 insn |= value & 0xfff;
10857 insn |= (value & 0xf000) << 4;
10858 bfd_put_32 (input_bfd, insn, hit_data);
10859 }
10860 return bfd_reloc_ok;
10861
10862 case R_ARM_THM_MOVW_ABS_NC:
10863 case R_ARM_THM_MOVT_ABS:
10864 case R_ARM_THM_MOVW_PREL_NC:
10865 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 10866 /* Until we properly support segment-base-relative addressing then
10867 we assume the segment base to be zero, as for the above relocations.
10868 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
10869 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
10870 as R_ARM_THM_MOVT_ABS. */
10871 case R_ARM_THM_MOVW_BREL_NC:
10872 case R_ARM_THM_MOVW_BREL:
10873 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 10874 {
10875 bfd_vma insn;
906e58ca 10876
b6895b4f
PB		 10877 insn = bfd_get_16 (input_bfd, hit_data) << 16;
10878 insn |= bfd_get_16 (input_bfd, hit_data + 2);
10879
10880 if (globals->use_rel)
10881 {
10882 addend = ((insn >> 4) & 0xf000)
10883 | ((insn >> 15) & 0x0800)
10884 | ((insn >> 4) & 0x0700)
10885 | (insn & 0x00ff);
39623e12 10886 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 10887 }
92f5d02b 10888
b6895b4f 10889 value += signed_addend;
b6895b4f
PB		 10890
10891 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
10892 value -= (input_section->output_section->vma
10893 + input_section->output_offset + rel->r_offset);
10894
92f5d02b 10895 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 10896 return bfd_reloc_overflow;
92f5d02b 10897
35fc36a8 10898 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 10899 value |= 1;
10900
10901 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 10902 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 10903 value >>= 16;
10904
10905 insn &= 0xfbf08f00;
10906 insn |= (value & 0xf000) << 4;
10907 insn |= (value & 0x0800) << 15;
10908 insn |= (value & 0x0700) << 4;
10909 insn |= (value & 0x00ff);
10910
10911 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10912 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10913 }
10914 return bfd_reloc_ok;
10915
4962c51a
MS		 10916 case R_ARM_ALU_PC_G0_NC:
10917 case R_ARM_ALU_PC_G1_NC:
10918 case R_ARM_ALU_PC_G0:
10919 case R_ARM_ALU_PC_G1:
10920 case R_ARM_ALU_PC_G2:
10921 case R_ARM_ALU_SB_G0_NC:
10922 case R_ARM_ALU_SB_G1_NC:
10923 case R_ARM_ALU_SB_G0:
10924 case R_ARM_ALU_SB_G1:
10925 case R_ARM_ALU_SB_G2:
10926 {
10927 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10928 bfd_vma pc = input_section->output_section->vma
4962c51a 10929 + input_section->output_offset + rel->r_offset;
31a91d61 10930 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10931 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 10932 bfd_vma residual;
10933 bfd_vma g_n;
4962c51a 10934 bfd_signed_vma signed_value;
99059e56
RM		 10935 int group = 0;
10936
10937 /* Determine which group of bits to select. */
10938 switch (r_type)
10939 {
10940 case R_ARM_ALU_PC_G0_NC:
10941 case R_ARM_ALU_PC_G0:
10942 case R_ARM_ALU_SB_G0_NC:
10943 case R_ARM_ALU_SB_G0:
10944 group = 0;
10945 break;
10946
10947 case R_ARM_ALU_PC_G1_NC:
10948 case R_ARM_ALU_PC_G1:
10949 case R_ARM_ALU_SB_G1_NC:
10950 case R_ARM_ALU_SB_G1:
10951 group = 1;
10952 break;
10953
10954 case R_ARM_ALU_PC_G2:
10955 case R_ARM_ALU_SB_G2:
10956 group = 2;
10957 break;
10958
10959 default:
10960 abort ();
10961 }
10962
10963 /* If REL, extract the addend from the insn. If RELA, it will
10964 have already been fetched for us. */
4962c51a 10965 if (globals->use_rel)
99059e56
RM		 10966 {
10967 int negative;
10968 bfd_vma constant = insn & 0xff;
10969 bfd_vma rotation = (insn & 0xf00) >> 8;
10970
10971 if (rotation == 0)
10972 signed_addend = constant;
10973 else
10974 {
10975 /* Compensate for the fact that in the instruction, the
10976 rotation is stored in multiples of 2 bits. */
10977 rotation *= 2;
10978
10979 /* Rotate "constant" right by "rotation" bits. */
10980 signed_addend = (constant >> rotation) |
10981 (constant << (8 * sizeof (bfd_vma) - rotation));
10982 }
10983
10984 /* Determine if the instruction is an ADD or a SUB.
10985 (For REL, this determines the sign of the addend.) */
10986 negative = identify_add_or_sub (insn);
10987 if (negative == 0)
10988 {
10989 (*_bfd_error_handler)
10990 (_("%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations"),
10991 input_bfd, input_section,
10992 (long) rel->r_offset, howto->name);
10993 return bfd_reloc_overflow;
10994 }
10995
10996 signed_addend *= negative;
10997 }
4962c51a
MS		 10998
10999 /* Compute the value (X) to go in the place. */
99059e56
RM		 11000 if (r_type == R_ARM_ALU_PC_G0_NC
11001 || r_type == R_ARM_ALU_PC_G1_NC
11002 || r_type == R_ARM_ALU_PC_G0
11003 || r_type == R_ARM_ALU_PC_G1
11004 || r_type == R_ARM_ALU_PC_G2)
11005 /* PC relative. */
11006 signed_value = value - pc + signed_addend;
11007 else
11008 /* Section base relative. */
11009 signed_value = value - sb + signed_addend;
11010
11011 /* If the target symbol is a Thumb function, then set the
11012 Thumb bit in the address. */
35fc36a8 11013 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 11014 signed_value |= 1;
11015
99059e56
RM		 11016 /* Calculate the value of the relevant G_n, in encoded
11017 constant-with-rotation format. */
b6518b38
NC		 11018 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11019 group, &residual);
99059e56
RM		 11020
11021 /* Check for overflow if required. */
11022 if ((r_type == R_ARM_ALU_PC_G0
11023 || r_type == R_ARM_ALU_PC_G1
11024 || r_type == R_ARM_ALU_PC_G2
11025 || r_type == R_ARM_ALU_SB_G0
11026 || r_type == R_ARM_ALU_SB_G1
11027 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
11028 {
11029 (*_bfd_error_handler)
11030 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
11031 input_bfd, input_section,
b6518b38
NC		 11032 (long) rel->r_offset, signed_value < 0 ? - signed_value : signed_value,
11033 howto->name);
99059e56
RM		 11034 return bfd_reloc_overflow;
11035 }
11036
11037 /* Mask out the value and the ADD/SUB part of the opcode; take care
11038 not to destroy the S bit. */
11039 insn &= 0xff1ff000;
11040
11041 /* Set the opcode according to whether the value to go in the
11042 place is negative. */
11043 if (signed_value < 0)
11044 insn |= 1 << 22;
11045 else
11046 insn |= 1 << 23;
11047
11048 /* Encode the offset. */
11049 insn |= g_n;
4962c51a
MS		 11050
11051 bfd_put_32 (input_bfd, insn, hit_data);
11052 }
11053 return bfd_reloc_ok;
11054
11055 case R_ARM_LDR_PC_G0:
11056 case R_ARM_LDR_PC_G1:
11057 case R_ARM_LDR_PC_G2:
11058 case R_ARM_LDR_SB_G0:
11059 case R_ARM_LDR_SB_G1:
11060 case R_ARM_LDR_SB_G2:
11061 {
11062 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11063 bfd_vma pc = input_section->output_section->vma
4962c51a 11064 + input_section->output_offset + rel->r_offset;
31a91d61 11065 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11066 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11067 bfd_vma residual;
4962c51a 11068 bfd_signed_vma signed_value;
99059e56
RM		 11069 int group = 0;
11070
11071 /* Determine which groups of bits to calculate. */
11072 switch (r_type)
11073 {
11074 case R_ARM_LDR_PC_G0:
11075 case R_ARM_LDR_SB_G0:
11076 group = 0;
11077 break;
11078
11079 case R_ARM_LDR_PC_G1:
11080 case R_ARM_LDR_SB_G1:
11081 group = 1;
11082 break;
11083
11084 case R_ARM_LDR_PC_G2:
11085 case R_ARM_LDR_SB_G2:
11086 group = 2;
11087 break;
11088
11089 default:
11090 abort ();
11091 }
11092
11093 /* If REL, extract the addend from the insn. If RELA, it will
11094 have already been fetched for us. */
4962c51a 11095 if (globals->use_rel)
99059e56
RM		 11096 {
11097 int negative = (insn & (1 << 23)) ? 1 : -1;
11098 signed_addend = negative * (insn & 0xfff);
11099 }
4962c51a
MS		 11100
11101 /* Compute the value (X) to go in the place. */
99059e56
RM		 11102 if (r_type == R_ARM_LDR_PC_G0
11103 || r_type == R_ARM_LDR_PC_G1
11104 || r_type == R_ARM_LDR_PC_G2)
11105 /* PC relative. */
11106 signed_value = value - pc + signed_addend;
11107 else
11108 /* Section base relative. */
11109 signed_value = value - sb + signed_addend;
11110
11111 /* Calculate the value of the relevant G_{n-1} to obtain
11112 the residual at that stage. */
b6518b38
NC		 11113 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11114 group - 1, &residual);
99059e56
RM		 11115
11116 /* Check for overflow. */
11117 if (residual >= 0x1000)
11118 {
11119 (*_bfd_error_handler)
11120 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 11121 input_bfd, input_section,
11122 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11123 return bfd_reloc_overflow;
11124 }
11125
11126 /* Mask out the value and U bit. */
11127 insn &= 0xff7ff000;
11128
11129 /* Set the U bit if the value to go in the place is non-negative. */
11130 if (signed_value >= 0)
11131 insn |= 1 << 23;
11132
11133 /* Encode the offset. */
11134 insn |= residual;
4962c51a
MS		 11135
11136 bfd_put_32 (input_bfd, insn, hit_data);
11137 }
11138 return bfd_reloc_ok;
11139
11140 case R_ARM_LDRS_PC_G0:
11141 case R_ARM_LDRS_PC_G1:
11142 case R_ARM_LDRS_PC_G2:
11143 case R_ARM_LDRS_SB_G0:
11144 case R_ARM_LDRS_SB_G1:
11145 case R_ARM_LDRS_SB_G2:
11146 {
11147 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11148 bfd_vma pc = input_section->output_section->vma
4962c51a 11149 + input_section->output_offset + rel->r_offset;
31a91d61 11150 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11151 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11152 bfd_vma residual;
4962c51a 11153 bfd_signed_vma signed_value;
99059e56
RM		 11154 int group = 0;
11155
11156 /* Determine which groups of bits to calculate. */
11157 switch (r_type)
11158 {
11159 case R_ARM_LDRS_PC_G0:
11160 case R_ARM_LDRS_SB_G0:
11161 group = 0;
11162 break;
11163
11164 case R_ARM_LDRS_PC_G1:
11165 case R_ARM_LDRS_SB_G1:
11166 group = 1;
11167 break;
11168
11169 case R_ARM_LDRS_PC_G2:
11170 case R_ARM_LDRS_SB_G2:
11171 group = 2;
11172 break;
11173
11174 default:
11175 abort ();
11176 }
11177
11178 /* If REL, extract the addend from the insn. If RELA, it will
11179 have already been fetched for us. */
4962c51a 11180 if (globals->use_rel)
99059e56
RM		 11181 {
11182 int negative = (insn & (1 << 23)) ? 1 : -1;
11183 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
11184 }
4962c51a
MS		 11185
11186 /* Compute the value (X) to go in the place. */
99059e56
RM		 11187 if (r_type == R_ARM_LDRS_PC_G0
11188 || r_type == R_ARM_LDRS_PC_G1
11189 || r_type == R_ARM_LDRS_PC_G2)
11190 /* PC relative. */
11191 signed_value = value - pc + signed_addend;
11192 else
11193 /* Section base relative. */
11194 signed_value = value - sb + signed_addend;
11195
11196 /* Calculate the value of the relevant G_{n-1} to obtain
11197 the residual at that stage. */
b6518b38
NC		 11198 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11199 group - 1, &residual);
99059e56
RM		 11200
11201 /* Check for overflow. */
11202 if (residual >= 0x100)
11203 {
11204 (*_bfd_error_handler)
11205 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 11206 input_bfd, input_section,
11207 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11208 return bfd_reloc_overflow;
11209 }
11210
11211 /* Mask out the value and U bit. */
11212 insn &= 0xff7ff0f0;
11213
11214 /* Set the U bit if the value to go in the place is non-negative. */
11215 if (signed_value >= 0)
11216 insn |= 1 << 23;
11217
11218 /* Encode the offset. */
11219 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 11220
11221 bfd_put_32 (input_bfd, insn, hit_data);
11222 }
11223 return bfd_reloc_ok;
11224
11225 case R_ARM_LDC_PC_G0:
11226 case R_ARM_LDC_PC_G1:
11227 case R_ARM_LDC_PC_G2:
11228 case R_ARM_LDC_SB_G0:
11229 case R_ARM_LDC_SB_G1:
11230 case R_ARM_LDC_SB_G2:
11231 {
11232 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11233 bfd_vma pc = input_section->output_section->vma
4962c51a 11234 + input_section->output_offset + rel->r_offset;
31a91d61 11235 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11236 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11237 bfd_vma residual;
4962c51a 11238 bfd_signed_vma signed_value;
99059e56
RM		 11239 int group = 0;
11240
11241 /* Determine which groups of bits to calculate. */
11242 switch (r_type)
11243 {
11244 case R_ARM_LDC_PC_G0:
11245 case R_ARM_LDC_SB_G0:
11246 group = 0;
11247 break;
11248
11249 case R_ARM_LDC_PC_G1:
11250 case R_ARM_LDC_SB_G1:
11251 group = 1;
11252 break;
11253
11254 case R_ARM_LDC_PC_G2:
11255 case R_ARM_LDC_SB_G2:
11256 group = 2;
11257 break;
11258
11259 default:
11260 abort ();
11261 }
11262
11263 /* If REL, extract the addend from the insn. If RELA, it will
11264 have already been fetched for us. */
4962c51a 11265 if (globals->use_rel)
99059e56
RM		 11266 {
11267 int negative = (insn & (1 << 23)) ? 1 : -1;
11268 signed_addend = negative * ((insn & 0xff) << 2);
11269 }
4962c51a
MS		 11270
11271 /* Compute the value (X) to go in the place. */
99059e56
RM		 11272 if (r_type == R_ARM_LDC_PC_G0
11273 || r_type == R_ARM_LDC_PC_G1
11274 || r_type == R_ARM_LDC_PC_G2)
11275 /* PC relative. */
11276 signed_value = value - pc + signed_addend;
11277 else
11278 /* Section base relative. */
11279 signed_value = value - sb + signed_addend;
11280
11281 /* Calculate the value of the relevant G_{n-1} to obtain
11282 the residual at that stage. */
b6518b38
NC		 11283 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11284 group - 1, &residual);
99059e56
RM		 11285
11286 /* Check for overflow. (The absolute value to go in the place must be
11287 divisible by four and, after having been divided by four, must
11288 fit in eight bits.) */
11289 if ((residual & 0x3) != 0 || residual >= 0x400)
11290 {
11291 (*_bfd_error_handler)
11292 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
11293 input_bfd, input_section,
b6518b38 11294 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11295 return bfd_reloc_overflow;
11296 }
11297
11298 /* Mask out the value and U bit. */
11299 insn &= 0xff7fff00;
11300
11301 /* Set the U bit if the value to go in the place is non-negative. */
11302 if (signed_value >= 0)
11303 insn |= 1 << 23;
11304
11305 /* Encode the offset. */
11306 insn |= residual >> 2;
4962c51a
MS		 11307
11308 bfd_put_32 (input_bfd, insn, hit_data);
11309 }
11310 return bfd_reloc_ok;
11311
72d98d16
MG		 11312 case R_ARM_THM_ALU_ABS_G0_NC:
11313 case R_ARM_THM_ALU_ABS_G1_NC:
11314 case R_ARM_THM_ALU_ABS_G2_NC:
11315 case R_ARM_THM_ALU_ABS_G3_NC:
11316 {
11317 const int shift_array[4] = {0, 8, 16, 24};
11318 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
11319 bfd_vma addr = value;
11320 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
11321
11322 /* Compute address. */
11323 if (globals->use_rel)
11324 signed_addend = insn & 0xff;
11325 addr += signed_addend;
11326 if (branch_type == ST_BRANCH_TO_THUMB)
11327 addr |= 1;
11328 /* Clean imm8 insn. */
11329 insn &= 0xff00;
11330 /* And update with correct part of address. */
11331 insn |= (addr >> shift) & 0xff;
11332 /* Update insn. */
11333 bfd_put_16 (input_bfd, insn, hit_data);
11334 }
11335
11336 *unresolved_reloc_p = FALSE;
11337 return bfd_reloc_ok;
11338
252b5132
RH		 11339 default:
11340 return bfd_reloc_notsupported;
11341 }
11342}
11343
98c1d4aa
NC		 11344/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
11345static void
57e8b36a
NC		 11346arm_add_to_rel (bfd * abfd,
11347 bfd_byte * address,
11348 reloc_howto_type * howto,
11349 bfd_signed_vma increment)
98c1d4aa 11350{
98c1d4aa
NC		 11351 bfd_signed_vma addend;
11352
bd97cb95
DJ		 11353 if (howto->type == R_ARM_THM_CALL
11354 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 11355 {
9a5aca8c
AM		 11356 int upper_insn, lower_insn;
11357 int upper, lower;
98c1d4aa 11358
9a5aca8c
AM		 11359 upper_insn = bfd_get_16 (abfd, address);
11360 lower_insn = bfd_get_16 (abfd, address + 2);
11361 upper = upper_insn & 0x7ff;
11362 lower = lower_insn & 0x7ff;
11363
11364 addend = (upper << 12) | (lower << 1);
ddda4409 11365 addend += increment;
9a5aca8c 11366 addend >>= 1;
98c1d4aa 11367
9a5aca8c
AM		 11368 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
11369 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
11370
dc810e39
AM		 11371 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
11372 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 11373 }
11374 else
11375 {
11376 bfd_vma contents;
11377
11378 contents = bfd_get_32 (abfd, address);
11379
11380 /* Get the (signed) value from the instruction. */
11381 addend = contents & howto->src_mask;
11382 if (addend & ((howto->src_mask + 1) >> 1))
11383 {
11384 bfd_signed_vma mask;
11385
11386 mask = -1;
11387 mask &= ~ howto->src_mask;
11388 addend |= mask;
11389 }
11390
11391 /* Add in the increment, (which is a byte value). */
11392 switch (howto->type)
11393 {
11394 default:
11395 addend += increment;
11396 break;
11397
11398 case R_ARM_PC24:
c6596c5e 11399 case R_ARM_PLT32:
5b5bb741
PB		 11400 case R_ARM_CALL:
11401 case R_ARM_JUMP24:
9a5aca8c 11402 addend <<= howto->size;
dc810e39 11403 addend += increment;
9a5aca8c
AM		 11404
11405 /* Should we check for overflow here ? */
11406
11407 /* Drop any undesired bits. */
11408 addend >>= howto->rightshift;
11409 break;
11410 }
11411
11412 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
11413
11414 bfd_put_32 (abfd, contents, address);
ddda4409 11415 }
98c1d4aa 11416}
252b5132 11417
ba93b8ac
DJ		 11418#define IS_ARM_TLS_RELOC(R_TYPE) \
11419 ((R_TYPE) == R_ARM_TLS_GD32 \
11420 || (R_TYPE) == R_ARM_TLS_LDO32 \
11421 || (R_TYPE) == R_ARM_TLS_LDM32 \
11422 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
11423 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
11424 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
11425 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 11426 || (R_TYPE) == R_ARM_TLS_IE32 \
11427 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
11428
11429/* Specific set of relocations for the gnu tls dialect. */
11430#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
11431 ((R_TYPE) == R_ARM_TLS_GOTDESC \
11432 || (R_TYPE) == R_ARM_TLS_CALL \
11433 || (R_TYPE) == R_ARM_THM_TLS_CALL \
11434 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
11435 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 11436
252b5132 11437/* Relocate an ARM ELF section. */
906e58ca 11438
b34976b6 11439static bfd_boolean
57e8b36a
NC		 11440elf32_arm_relocate_section (bfd * output_bfd,
11441 struct bfd_link_info * info,
11442 bfd * input_bfd,
11443 asection * input_section,
11444 bfd_byte * contents,
11445 Elf_Internal_Rela * relocs,
11446 Elf_Internal_Sym * local_syms,
11447 asection ** local_sections)
252b5132 11448{
b34976b6
AM		 11449 Elf_Internal_Shdr *symtab_hdr;
11450 struct elf_link_hash_entry **sym_hashes;
11451 Elf_Internal_Rela *rel;
11452 Elf_Internal_Rela *relend;
11453 const char *name;
b32d3aa2 11454 struct elf32_arm_link_hash_table * globals;
252b5132 11455
4e7fd91e 11456 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 11457 if (globals == NULL)
11458 return FALSE;
b491616a 11459
0ffa91dd 11460 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 11461 sym_hashes = elf_sym_hashes (input_bfd);
11462
11463 rel = relocs;
11464 relend = relocs + input_section->reloc_count;
11465 for (; rel < relend; rel++)
11466 {
ba96a88f
NC		 11467 int r_type;
11468 reloc_howto_type * howto;
11469 unsigned long r_symndx;
11470 Elf_Internal_Sym * sym;
11471 asection * sec;
252b5132 11472 struct elf_link_hash_entry * h;
ba96a88f
NC		 11473 bfd_vma relocation;
11474 bfd_reloc_status_type r;
11475 arelent bfd_reloc;
ba93b8ac 11476 char sym_type;
0945cdfd 11477 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 11478 char *error_message = NULL;
f21f3fe0 11479
252b5132 11480 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 11481 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 11482 r_type = arm_real_reloc_type (globals, r_type);
252b5132 11483
ba96a88f 11484 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 11485 || r_type == R_ARM_GNU_VTINHERIT)
11486 continue;
252b5132 11487
b32d3aa2 11488 bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
ba96a88f 11489 howto = bfd_reloc.howto;
252b5132 11490
252b5132
RH		 11491 h = NULL;
11492 sym = NULL;
11493 sec = NULL;
9b485d32 11494
252b5132
RH		 11495 if (r_symndx < symtab_hdr->sh_info)
11496 {
11497 sym = local_syms + r_symndx;
ba93b8ac 11498 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 11499 sec = local_sections[r_symndx];
ffcb4889
NS		 11500
11501 /* An object file might have a reference to a local
11502 undefined symbol. This is a daft object file, but we
11503 should at least do something about it. V4BX & NONE
11504 relocations do not use the symbol and are explicitly
77b4f08f
TS		 11505 allowed to use the undefined symbol, so allow those.
11506 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 11507 if (r_type != R_ARM_V4BX
11508 && r_type != R_ARM_NONE
77b4f08f 11509 && r_symndx != STN_UNDEF
ffcb4889
NS		 11510 && bfd_is_und_section (sec)
11511 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
11512 {
11513 if (!info->callbacks->undefined_symbol
11514 (info, bfd_elf_string_from_elf_section
11515 (input_bfd, symtab_hdr->sh_link, sym->st_name),
11516 input_bfd, input_section,
11517 rel->r_offset, TRUE))
11518 return FALSE;
11519 }
b38cadfb 11520
4e7fd91e 11521 if (globals->use_rel)
f8df10f4 11522 {
4e7fd91e
PB		 11523 relocation = (sec->output_section->vma
11524 + sec->output_offset
11525 + sym->st_value);
0e1862bb 11526 if (!bfd_link_relocatable (info)
ab96bf03
AM		 11527 && (sec->flags & SEC_MERGE)
11528 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 11529 {
4e7fd91e
PB		 11530 asection *msec;
11531 bfd_vma addend, value;
11532
39623e12 11533 switch (r_type)
4e7fd91e 11534 {
39623e12
PB		 11535 case R_ARM_MOVW_ABS_NC:
11536 case R_ARM_MOVT_ABS:
11537 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
11538 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
11539 addend = (addend ^ 0x8000) - 0x8000;
11540 break;
f8df10f4 11541
39623e12
PB		 11542 case R_ARM_THM_MOVW_ABS_NC:
11543 case R_ARM_THM_MOVT_ABS:
11544 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
11545 << 16;
11546 value |= bfd_get_16 (input_bfd,
11547 contents + rel->r_offset + 2);
11548 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
11549 | ((value & 0x04000000) >> 15);
11550 addend = (addend ^ 0x8000) - 0x8000;
11551 break;
f8df10f4 11552
39623e12
PB		 11553 default:
11554 if (howto->rightshift
11555 || (howto->src_mask & (howto->src_mask + 1)))
11556 {
11557 (*_bfd_error_handler)
11558 (_("%B(%A+0x%lx): %s relocation against SEC_MERGE section"),
11559 input_bfd, input_section,
11560 (long) rel->r_offset, howto->name);
11561 return FALSE;
11562 }
11563
11564 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
11565
11566 /* Get the (signed) value from the instruction. */
11567 addend = value & howto->src_mask;
11568 if (addend & ((howto->src_mask + 1) >> 1))
11569 {
11570 bfd_signed_vma mask;
11571
11572 mask = -1;
11573 mask &= ~ howto->src_mask;
11574 addend |= mask;
11575 }
11576 break;
4e7fd91e 11577 }
39623e12 11578
4e7fd91e
PB		 11579 msec = sec;
11580 addend =
11581 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
11582 - relocation;
11583 addend += msec->output_section->vma + msec->output_offset;
39623e12 11584
cc643b88 11585 /* Cases here must match those in the preceding
39623e12
PB		 11586 switch statement. */
11587 switch (r_type)
11588 {
11589 case R_ARM_MOVW_ABS_NC:
11590 case R_ARM_MOVT_ABS:
11591 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
11592 | (addend & 0xfff);
11593 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
11594 break;
11595
11596 case R_ARM_THM_MOVW_ABS_NC:
11597 case R_ARM_THM_MOVT_ABS:
11598 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
11599 | (addend & 0xff) | ((addend & 0x0800) << 15);
11600 bfd_put_16 (input_bfd, value >> 16,
11601 contents + rel->r_offset);
11602 bfd_put_16 (input_bfd, value,
11603 contents + rel->r_offset + 2);
11604 break;
11605
11606 default:
11607 value = (value & ~ howto->dst_mask)
11608 | (addend & howto->dst_mask);
11609 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
11610 break;
11611 }
f8df10f4 11612 }
f8df10f4 11613 }
4e7fd91e
PB		 11614 else
11615 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 11616 }
11617 else
11618 {
62d887d4 11619 bfd_boolean warned, ignored;
560e09e9 11620
b2a8e766
AM		 11621 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
11622 r_symndx, symtab_hdr, sym_hashes,
11623 h, sec, relocation,
62d887d4 11624 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 11625
11626 sym_type = h->type;
252b5132
RH		 11627 }
11628
dbaa2011 11629 if (sec != NULL && discarded_section (sec))
e4067dbb 11630 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 11631 rel, 1, relend, howto, 0, contents);
ab96bf03 11632
0e1862bb 11633 if (bfd_link_relocatable (info))
ab96bf03
AM		 11634 {
11635 /* This is a relocatable link. We don't have to change
11636 anything, unless the reloc is against a section symbol,
11637 in which case we have to adjust according to where the
11638 section symbol winds up in the output section. */
11639 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
11640 {
11641 if (globals->use_rel)
11642 arm_add_to_rel (input_bfd, contents + rel->r_offset,
11643 howto, (bfd_signed_vma) sec->output_offset);
11644 else
11645 rel->r_addend += sec->output_offset;
11646 }
11647 continue;
11648 }
11649
252b5132
RH		 11650 if (h != NULL)
11651 name = h->root.root.string;
11652 else
11653 {
11654 name = (bfd_elf_string_from_elf_section
11655 (input_bfd, symtab_hdr->sh_link, sym->st_name));
11656 if (name == NULL || *name == '\0')
11657 name = bfd_section_name (input_bfd, sec);
11658 }
f21f3fe0 11659
cf35638d 11660 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 11661 && r_type != R_ARM_NONE
11662 && (h == NULL
11663 || h->root.type == bfd_link_hash_defined
11664 || h->root.type == bfd_link_hash_defweak)
11665 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
11666 {
11667 (*_bfd_error_handler)
11668 ((sym_type == STT_TLS
11669 ? _("%B(%A+0x%lx): %s used with TLS symbol %s")
11670 : _("%B(%A+0x%lx): %s used with non-TLS symbol %s")),
11671 input_bfd,
11672 input_section,
11673 (long) rel->r_offset,
11674 howto->name,
11675 name);
11676 }
11677
0855e32b 11678 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 11679 done, i.e., the relaxation produced the final output we want,
11680 and we won't let anybody mess with it. Also, we have to do
11681 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 11682 both in relaxed and non-relaxed cases. */
39d911fc
TP		 11683 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
11684 || (IS_ARM_TLS_GNU_RELOC (r_type)
11685 && !((h ? elf32_arm_hash_entry (h)->tls_type :
11686 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
11687 & GOT_TLS_GDESC)))
11688 {
11689 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
11690 contents, rel, h == NULL);
11691 /* This may have been marked unresolved because it came from
11692 a shared library. But we've just dealt with that. */
11693 unresolved_reloc = 0;
11694 }
11695 else
11696 r = bfd_reloc_continue;
b38cadfb 11697
39d911fc
TP		 11698 if (r == bfd_reloc_continue)
11699 {
11700 unsigned char branch_type =
11701 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
11702 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
11703
11704 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
11705 input_section, contents, rel,
11706 relocation, info, sec, name,
11707 sym_type, branch_type, h,
11708 &unresolved_reloc,
11709 &error_message);
11710 }
0945cdfd
DJ		 11711
11712 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
11713 because such sections are not SEC_ALLOC and thus ld.so will
11714 not process them. */
11715 if (unresolved_reloc
99059e56
RM		 11716 && !((input_section->flags & SEC_DEBUGGING) != 0
11717 && h->def_dynamic)
1d5316ab
AM		 11718 && _bfd_elf_section_offset (output_bfd, info, input_section,
11719 rel->r_offset) != (bfd_vma) -1)
0945cdfd
DJ		 11720 {
11721 (*_bfd_error_handler)
843fe662
L		 11722 (_("%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"),
11723 input_bfd,
11724 input_section,
11725 (long) rel->r_offset,
11726 howto->name,
11727 h->root.root.string);
0945cdfd
DJ		 11728 return FALSE;
11729 }
252b5132
RH		 11730
11731 if (r != bfd_reloc_ok)
11732 {
252b5132
RH		 11733 switch (r)
11734 {
11735 case bfd_reloc_overflow:
cf919dfd
PB		 11736 /* If the overflowing reloc was to an undefined symbol,
11737 we have already printed one error message and there
11738 is no point complaining again. */
11739 if ((! h ||
11740 h->root.type != bfd_link_hash_undefined)
11741 && (!((*info->callbacks->reloc_overflow)
dfeffb9f
L		 11742 (info, (h ? &h->root : NULL), name, howto->name,
11743 (bfd_vma) 0, input_bfd, input_section,
11744 rel->r_offset))))
b34976b6 11745 return FALSE;
252b5132
RH		 11746 break;
11747
11748 case bfd_reloc_undefined:
11749 if (!((*info->callbacks->undefined_symbol)
11750 (info, name, input_bfd, input_section,
b34976b6
AM		 11751 rel->r_offset, TRUE)))
11752 return FALSE;
252b5132
RH		 11753 break;
11754
11755 case bfd_reloc_outofrange:
f2a9dd69 11756 error_message = _("out of range");
252b5132
RH		 11757 goto common_error;
11758
11759 case bfd_reloc_notsupported:
f2a9dd69 11760 error_message = _("unsupported relocation");
252b5132
RH		 11761 goto common_error;
11762
11763 case bfd_reloc_dangerous:
f2a9dd69 11764 /* error_message should already be set. */
252b5132
RH		 11765 goto common_error;
11766
11767 default:
f2a9dd69 11768 error_message = _("unknown error");
8029a119 11769 /* Fall through. */
252b5132
RH		 11770
11771 common_error:
f2a9dd69
DJ		 11772 BFD_ASSERT (error_message != NULL);
11773 if (!((*info->callbacks->reloc_dangerous)
11774 (info, error_message, input_bfd, input_section,
252b5132 11775 rel->r_offset)))
b34976b6 11776 return FALSE;
252b5132
RH		 11777 break;
11778 }
11779 }
11780 }
11781
b34976b6 11782 return TRUE;
252b5132
RH		 11783}
11784
91d6fa6a 11785/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 11786 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 11787 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 11788 maintaining that condition). */
11789
11790static void
11791add_unwind_table_edit (arm_unwind_table_edit **head,
11792 arm_unwind_table_edit **tail,
11793 arm_unwind_edit_type type,
11794 asection *linked_section,
91d6fa6a 11795 unsigned int tindex)
2468f9c9 11796{
21d799b5
NC		 11797 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
11798 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 11799
2468f9c9
PB		 11800 new_edit->type = type;
11801 new_edit->linked_section = linked_section;
91d6fa6a 11802 new_edit->index = tindex;
b38cadfb 11803
91d6fa6a 11804 if (tindex > 0)
2468f9c9
PB		 11805 {
11806 new_edit->next = NULL;
11807
11808 if (*tail)
11809 (*tail)->next = new_edit;
11810
11811 (*tail) = new_edit;
11812
11813 if (!*head)
11814 (*head) = new_edit;
11815 }
11816 else
11817 {
11818 new_edit->next = *head;
11819
11820 if (!*tail)
11821 *tail = new_edit;
11822
11823 *head = new_edit;
11824 }
11825}
11826
11827static _arm_elf_section_data *get_arm_elf_section_data (asection *);
11828
11829/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
11830static void
11831adjust_exidx_size(asection *exidx_sec, int adjust)
11832{
11833 asection *out_sec;
11834
11835 if (!exidx_sec->rawsize)
11836 exidx_sec->rawsize = exidx_sec->size;
11837
11838 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
11839 out_sec = exidx_sec->output_section;
11840 /* Adjust size of output section. */
11841 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
11842}
11843
11844/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
11845static void
11846insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
11847{
11848 struct _arm_elf_section_data *exidx_arm_data;
11849
11850 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
11851 add_unwind_table_edit (
11852 &exidx_arm_data->u.exidx.unwind_edit_list,
11853 &exidx_arm_data->u.exidx.unwind_edit_tail,
11854 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
11855
491d01d3
YU		 11856 exidx_arm_data->additional_reloc_count++;
11857
2468f9c9
PB		 11858 adjust_exidx_size(exidx_sec, 8);
11859}
11860
11861/* Scan .ARM.exidx tables, and create a list describing edits which should be
11862 made to those tables, such that:
b38cadfb 11863
2468f9c9
PB		 11864 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
11865 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 11866 codes which have been inlined into the index).
2468f9c9 11867
85fdf906
AH		 11868 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
11869
2468f9c9 11870 The edits are applied when the tables are written
b38cadfb 11871 (in elf32_arm_write_section). */
2468f9c9
PB		 11872
11873bfd_boolean
11874elf32_arm_fix_exidx_coverage (asection **text_section_order,
11875 unsigned int num_text_sections,
85fdf906
AH		 11876 struct bfd_link_info *info,
11877 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 11878{
11879 bfd *inp;
11880 unsigned int last_second_word = 0, i;
11881 asection *last_exidx_sec = NULL;
11882 asection *last_text_sec = NULL;
11883 int last_unwind_type = -1;
11884
11885 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
11886 text sections. */
c72f2fb2 11887 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 11888 {
11889 asection *sec;
b38cadfb 11890
2468f9c9 11891 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 11892 {
2468f9c9
PB		 11893 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
11894 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 11895
dec9d5df 11896 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 11897 continue;
b38cadfb 11898
2468f9c9
PB		 11899 if (elf_sec->linked_to)
11900 {
11901 Elf_Internal_Shdr *linked_hdr
99059e56 11902 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 11903 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 11904 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 11905
11906 if (linked_sec_arm_data == NULL)
99059e56 11907 continue;
2468f9c9
PB		 11908
11909 /* Link this .ARM.exidx section back from the text section it
99059e56 11910 describes. */
2468f9c9
PB		 11911 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
11912 }
11913 }
11914 }
11915
11916 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
11917 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 11918 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 11919
11920 for (i = 0; i < num_text_sections; i++)
11921 {
11922 asection *sec = text_section_order[i];
11923 asection *exidx_sec;
11924 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
11925 struct _arm_elf_section_data *exidx_arm_data;
11926 bfd_byte *contents = NULL;
11927 int deleted_exidx_bytes = 0;
11928 bfd_vma j;
11929 arm_unwind_table_edit *unwind_edit_head = NULL;
11930 arm_unwind_table_edit *unwind_edit_tail = NULL;
11931 Elf_Internal_Shdr *hdr;
11932 bfd *ibfd;
11933
11934 if (arm_data == NULL)
99059e56 11935 continue;
2468f9c9
PB		 11936
11937 exidx_sec = arm_data->u.text.arm_exidx_sec;
11938 if (exidx_sec == NULL)
11939 {
11940 /* Section has no unwind data. */
11941 if (last_unwind_type == 0 || !last_exidx_sec)
11942 continue;
11943
11944 /* Ignore zero sized sections. */
11945 if (sec->size == 0)
11946 continue;
11947
11948 insert_cantunwind_after(last_text_sec, last_exidx_sec);
11949 last_unwind_type = 0;
11950 continue;
11951 }
11952
22a8f80e
PB		 11953 /* Skip /DISCARD/ sections. */
11954 if (bfd_is_abs_section (exidx_sec->output_section))
11955 continue;
11956
2468f9c9
PB		 11957 hdr = &elf_section_data (exidx_sec)->this_hdr;
11958 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 11959 continue;
b38cadfb 11960
2468f9c9
PB		 11961 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
11962 if (exidx_arm_data == NULL)
99059e56 11963 continue;
b38cadfb 11964
2468f9c9 11965 ibfd = exidx_sec->owner;
b38cadfb 11966
2468f9c9
PB		 11967 if (hdr->contents != NULL)
11968 contents = hdr->contents;
11969 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
11970 /* An error? */
11971 continue;
11972
ac06903d
YU		 11973 if (last_unwind_type > 0)
11974 {
11975 unsigned int first_word = bfd_get_32 (ibfd, contents);
11976 /* Add cantunwind if first unwind item does not match section
11977 start. */
11978 if (first_word != sec->vma)
11979 {
11980 insert_cantunwind_after (last_text_sec, last_exidx_sec);
11981 last_unwind_type = 0;
11982 }
11983 }
11984
2468f9c9
PB		 11985 for (j = 0; j < hdr->sh_size; j += 8)
11986 {
11987 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
11988 int unwind_type;
11989 int elide = 0;
11990
11991 /* An EXIDX_CANTUNWIND entry. */
11992 if (second_word == 1)
11993 {
11994 if (last_unwind_type == 0)
11995 elide = 1;
11996 unwind_type = 0;
11997 }
11998 /* Inlined unwinding data. Merge if equal to previous. */
11999 else if ((second_word & 0x80000000) != 0)
12000 {
85fdf906
AH		 12001 if (merge_exidx_entries
12002 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 12003 elide = 1;
12004 unwind_type = 1;
12005 last_second_word = second_word;
12006 }
12007 /* Normal table entry. In theory we could merge these too,
12008 but duplicate entries are likely to be much less common. */
12009 else
12010 unwind_type = 2;
12011
491d01d3 12012 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 12013 {
12014 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
12015 DELETE_EXIDX_ENTRY, NULL, j / 8);
12016
12017 deleted_exidx_bytes += 8;
12018 }
12019
12020 last_unwind_type = unwind_type;
12021 }
12022
12023 /* Free contents if we allocated it ourselves. */
12024 if (contents != hdr->contents)
99059e56 12025 free (contents);
2468f9c9
PB		 12026
12027 /* Record edits to be applied later (in elf32_arm_write_section). */
12028 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
12029 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 12030
2468f9c9
PB		 12031 if (deleted_exidx_bytes > 0)
12032 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
12033
12034 last_exidx_sec = exidx_sec;
12035 last_text_sec = sec;
12036 }
12037
12038 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 12039 if (!bfd_link_relocatable (info) && last_exidx_sec
12040 && last_unwind_type != 0)
2468f9c9
PB		 12041 insert_cantunwind_after(last_text_sec, last_exidx_sec);
12042
12043 return TRUE;
12044}
12045
3e6b1042
DJ		 12046static bfd_boolean
12047elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
12048 bfd *ibfd, const char *name)
12049{
12050 asection *sec, *osec;
12051
3d4d4302 12052 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 12053 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
12054 return TRUE;
12055
12056 osec = sec->output_section;
12057 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
12058 return TRUE;
12059
12060 if (! bfd_set_section_contents (obfd, osec, sec->contents,
12061 sec->output_offset, sec->size))
12062 return FALSE;
12063
12064 return TRUE;
12065}
12066
12067static bfd_boolean
12068elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
12069{
12070 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 12071 asection *sec, *osec;
3e6b1042 12072
4dfe6ac6
NC		 12073 if (globals == NULL)
12074 return FALSE;
12075
3e6b1042
DJ		 12076 /* Invoke the regular ELF backend linker to do all the work. */
12077 if (!bfd_elf_final_link (abfd, info))
12078 return FALSE;
12079
fe33d2fa
CL		 12080 /* Process stub sections (eg BE8 encoding, ...). */
12081 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 12082 unsigned int i;
cdb21a0a
NS		 12083 for (i=0; i<htab->top_id; i++)
12084 {
12085 sec = htab->stub_group[i].stub_sec;
12086 /* Only process it once, in its link_sec slot. */
12087 if (sec && i == htab->stub_group[i].link_sec->id)
12088 {
12089 osec = sec->output_section;
12090 elf32_arm_write_section (abfd, info, sec, sec->contents);
12091 if (! bfd_set_section_contents (abfd, osec, sec->contents,
12092 sec->output_offset, sec->size))
12093 return FALSE;
12094 }
fe33d2fa 12095 }
fe33d2fa 12096
3e6b1042
DJ		 12097 /* Write out any glue sections now that we have created all the
12098 stubs. */
12099 if (globals->bfd_of_glue_owner != NULL)
12100 {
12101 if (! elf32_arm_output_glue_section (info, abfd,
12102 globals->bfd_of_glue_owner,
12103 ARM2THUMB_GLUE_SECTION_NAME))
12104 return FALSE;
12105
12106 if (! elf32_arm_output_glue_section (info, abfd,
12107 globals->bfd_of_glue_owner,
12108 THUMB2ARM_GLUE_SECTION_NAME))
12109 return FALSE;
12110
12111 if (! elf32_arm_output_glue_section (info, abfd,
12112 globals->bfd_of_glue_owner,
12113 VFP11_ERRATUM_VENEER_SECTION_NAME))
12114 return FALSE;
12115
a504d23a
LA		 12116 if (! elf32_arm_output_glue_section (info, abfd,
12117 globals->bfd_of_glue_owner,
12118 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
12119 return FALSE;
12120
3e6b1042
DJ		 12121 if (! elf32_arm_output_glue_section (info, abfd,
12122 globals->bfd_of_glue_owner,
12123 ARM_BX_GLUE_SECTION_NAME))
12124 return FALSE;
12125 }
12126
12127 return TRUE;
12128}
12129
5968a7b8
NC		 12130/* Return a best guess for the machine number based on the attributes. */
12131
12132static unsigned int
12133bfd_arm_get_mach_from_attributes (bfd * abfd)
12134{
12135 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
12136
12137 switch (arch)
12138 {
12139 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
12140 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
12141 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
12142
12143 case TAG_CPU_ARCH_V5TE:
12144 {
12145 char * name;
12146
12147 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
12148 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
12149
12150 if (name)
12151 {
12152 if (strcmp (name, "IWMMXT2") == 0)
12153 return bfd_mach_arm_iWMMXt2;
12154
12155 if (strcmp (name, "IWMMXT") == 0)
6034aab8 12156 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 12157
12158 if (strcmp (name, "XSCALE") == 0)
12159 {
12160 int wmmx;
12161
12162 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
12163 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
12164 switch (wmmx)
12165 {
12166 case 1: return bfd_mach_arm_iWMMXt;
12167 case 2: return bfd_mach_arm_iWMMXt2;
12168 default: return bfd_mach_arm_XScale;
12169 }
12170 }
5968a7b8
NC		 12171 }
12172
12173 return bfd_mach_arm_5TE;
12174 }
12175
12176 default:
12177 return bfd_mach_arm_unknown;
12178 }
12179}
12180
c178919b
NC		 12181/* Set the right machine number. */
12182
12183static bfd_boolean
57e8b36a 12184elf32_arm_object_p (bfd *abfd)
c178919b 12185{
5a6c6817 12186 unsigned int mach;
57e8b36a 12187
5a6c6817 12188 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 12189
5968a7b8
NC		 12190 if (mach == bfd_mach_arm_unknown)
12191 {
12192 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
12193 mach = bfd_mach_arm_ep9312;
12194 else
12195 mach = bfd_arm_get_mach_from_attributes (abfd);
12196 }
c178919b 12197
5968a7b8 12198 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 12199 return TRUE;
12200}
12201
fc830a83 12202/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 12203
b34976b6 12204static bfd_boolean
57e8b36a 12205elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 12206{
12207 if (elf_flags_init (abfd)
12208 && elf_elfheader (abfd)->e_flags != flags)
12209 {
fc830a83
NC		 12210 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
12211 {
fd2ec330 12212 if (flags & EF_ARM_INTERWORK)
d003868e
AM		 12213 (*_bfd_error_handler)
12214 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
12215 abfd);
fc830a83 12216 else
d003868e
AM		 12217 _bfd_error_handler
12218 (_("Warning: Clearing the interworking flag of %B due to outside request"),
12219 abfd);
fc830a83 12220 }
252b5132
RH		 12221 }
12222 else
12223 {
12224 elf_elfheader (abfd)->e_flags = flags;
b34976b6 12225 elf_flags_init (abfd) = TRUE;
252b5132
RH		 12226 }
12227
b34976b6 12228 return TRUE;
252b5132
RH		 12229}
12230
fc830a83 12231/* Copy backend specific data from one object module to another. */
9b485d32 12232
b34976b6 12233static bfd_boolean
57e8b36a 12234elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 12235{
12236 flagword in_flags;
12237 flagword out_flags;
12238
0ffa91dd 12239 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 12240 return TRUE;
252b5132 12241
fc830a83 12242 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 12243 out_flags = elf_elfheader (obfd)->e_flags;
12244
fc830a83
NC		 12245 if (elf_flags_init (obfd)
12246 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
12247 && in_flags != out_flags)
252b5132 12248 {
252b5132 12249 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 12250 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 12251 return FALSE;
252b5132
RH		 12252
12253 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 12254 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 12255 return FALSE;
252b5132
RH		 12256
12257 /* If the src and dest have different interworking flags
99059e56 12258 then turn off the interworking bit. */
fd2ec330 12259 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 12260 {
fd2ec330 12261 if (out_flags & EF_ARM_INTERWORK)
d003868e
AM		 12262 _bfd_error_handler
12263 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
12264 obfd, ibfd);
252b5132 12265
fd2ec330 12266 in_flags &= ~EF_ARM_INTERWORK;
252b5132 12267 }
1006ba19
PB		 12268
12269 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 12270 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
12271 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 12272 }
12273
12274 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 12275 elf_flags_init (obfd) = TRUE;
252b5132 12276
e2349352 12277 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 12278}
12279
12280/* Values for Tag_ABI_PCS_R9_use. */
12281enum
12282{
12283 AEABI_R9_V6,
12284 AEABI_R9_SB,
12285 AEABI_R9_TLS,
12286 AEABI_R9_unused
12287};
12288
12289/* Values for Tag_ABI_PCS_RW_data. */
12290enum
12291{
12292 AEABI_PCS_RW_data_absolute,
12293 AEABI_PCS_RW_data_PCrel,
12294 AEABI_PCS_RW_data_SBrel,
12295 AEABI_PCS_RW_data_unused
12296};
12297
12298/* Values for Tag_ABI_enum_size. */
12299enum
12300{
12301 AEABI_enum_unused,
12302 AEABI_enum_short,
12303 AEABI_enum_wide,
12304 AEABI_enum_forced_wide
12305};
12306
104d59d1
JM		 12307/* Determine whether an object attribute tag takes an integer, a
12308 string or both. */
906e58ca 12309
104d59d1
JM		 12310static int
12311elf32_arm_obj_attrs_arg_type (int tag)
12312{
12313 if (tag == Tag_compatibility)
3483fe2e 12314 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 12315 else if (tag == Tag_nodefaults)
3483fe2e
AS		 12316 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
12317 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
12318 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 12319 else if (tag < 32)
3483fe2e 12320 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 12321 else
3483fe2e 12322 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 12323}
12324
5aa6ff7c
AS		 12325/* The ABI defines that Tag_conformance should be emitted first, and that
12326 Tag_nodefaults should be second (if either is defined). This sets those
12327 two positions, and bumps up the position of all the remaining tags to
12328 compensate. */
12329static int
12330elf32_arm_obj_attrs_order (int num)
12331{
3de4a297 12332 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 12333 return Tag_conformance;
3de4a297 12334 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 12335 return Tag_nodefaults;
12336 if ((num - 2) < Tag_nodefaults)
12337 return num - 2;
12338 if ((num - 1) < Tag_conformance)
12339 return num - 1;
12340 return num;
12341}
12342
e8b36cd1
JM		 12343/* Attribute numbers >=64 (mod 128) can be safely ignored. */
12344static bfd_boolean
12345elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
12346{
12347 if ((tag & 127) < 64)
12348 {
12349 _bfd_error_handler
12350 (_("%B: Unknown mandatory EABI object attribute %d"),
12351 abfd, tag);
12352 bfd_set_error (bfd_error_bad_value);
12353 return FALSE;
12354 }
12355 else
12356 {
12357 _bfd_error_handler
12358 (_("Warning: %B: Unknown EABI object attribute %d"),
12359 abfd, tag);
12360 return TRUE;
12361 }
12362}
12363
91e22acd
AS		 12364/* Read the architecture from the Tag_also_compatible_with attribute, if any.
12365 Returns -1 if no architecture could be read. */
12366
12367static int
12368get_secondary_compatible_arch (bfd *abfd)
12369{
12370 obj_attribute *attr =
12371 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
12372
12373 /* Note: the tag and its argument below are uleb128 values, though
12374 currently-defined values fit in one byte for each. */
12375 if (attr->s
12376 && attr->s[0] == Tag_CPU_arch
12377 && (attr->s[1] & 128) != 128
12378 && attr->s[2] == 0)
12379 return attr->s[1];
12380
12381 /* This tag is "safely ignorable", so don't complain if it looks funny. */
12382 return -1;
12383}
12384
12385/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
12386 The tag is removed if ARCH is -1. */
12387
8e79c3df 12388static void
91e22acd 12389set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 12390{
91e22acd
AS		 12391 obj_attribute *attr =
12392 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 12393
91e22acd
AS		 12394 if (arch == -1)
12395 {
12396 attr->s = NULL;
12397 return;
8e79c3df 12398 }
91e22acd
AS		 12399
12400 /* Note: the tag and its argument below are uleb128 values, though
12401 currently-defined values fit in one byte for each. */
12402 if (!attr->s)
21d799b5 12403 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 12404 attr->s[0] = Tag_CPU_arch;
12405 attr->s[1] = arch;
12406 attr->s[2] = '\0';
8e79c3df
CM		 12407}
12408
91e22acd
AS		 12409/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
12410 into account. */
12411
12412static int
12413tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
12414 int newtag, int secondary_compat)
8e79c3df 12415{
91e22acd
AS		 12416#define T(X) TAG_CPU_ARCH_##X
12417 int tagl, tagh, result;
12418 const int v6t2[] =
12419 {
12420 T(V6T2), /* PRE_V4. */
12421 T(V6T2), /* V4. */
12422 T(V6T2), /* V4T. */
12423 T(V6T2), /* V5T. */
12424 T(V6T2), /* V5TE. */
12425 T(V6T2), /* V5TEJ. */
12426 T(V6T2), /* V6. */
12427 T(V7), /* V6KZ. */
12428 T(V6T2) /* V6T2. */
12429 };
12430 const int v6k[] =
12431 {
12432 T(V6K), /* PRE_V4. */
12433 T(V6K), /* V4. */
12434 T(V6K), /* V4T. */
12435 T(V6K), /* V5T. */
12436 T(V6K), /* V5TE. */
12437 T(V6K), /* V5TEJ. */
12438 T(V6K), /* V6. */
12439 T(V6KZ), /* V6KZ. */
12440 T(V7), /* V6T2. */
12441 T(V6K) /* V6K. */
12442 };
12443 const int v7[] =
12444 {
12445 T(V7), /* PRE_V4. */
12446 T(V7), /* V4. */
12447 T(V7), /* V4T. */
12448 T(V7), /* V5T. */
12449 T(V7), /* V5TE. */
12450 T(V7), /* V5TEJ. */
12451 T(V7), /* V6. */
12452 T(V7), /* V6KZ. */
12453 T(V7), /* V6T2. */
12454 T(V7), /* V6K. */
12455 T(V7) /* V7. */
12456 };
12457 const int v6_m[] =
12458 {
12459 -1, /* PRE_V4. */
12460 -1, /* V4. */
12461 T(V6K), /* V4T. */
12462 T(V6K), /* V5T. */
12463 T(V6K), /* V5TE. */
12464 T(V6K), /* V5TEJ. */
12465 T(V6K), /* V6. */
12466 T(V6KZ), /* V6KZ. */
12467 T(V7), /* V6T2. */
12468 T(V6K), /* V6K. */
12469 T(V7), /* V7. */
12470 T(V6_M) /* V6_M. */
12471 };
12472 const int v6s_m[] =
12473 {
12474 -1, /* PRE_V4. */
12475 -1, /* V4. */
12476 T(V6K), /* V4T. */
12477 T(V6K), /* V5T. */
12478 T(V6K), /* V5TE. */
12479 T(V6K), /* V5TEJ. */
12480 T(V6K), /* V6. */
12481 T(V6KZ), /* V6KZ. */
12482 T(V7), /* V6T2. */
12483 T(V6K), /* V6K. */
12484 T(V7), /* V7. */
12485 T(V6S_M), /* V6_M. */
12486 T(V6S_M) /* V6S_M. */
12487 };
9e3c6df6
PB		 12488 const int v7e_m[] =
12489 {
12490 -1, /* PRE_V4. */
12491 -1, /* V4. */
12492 T(V7E_M), /* V4T. */
12493 T(V7E_M), /* V5T. */
12494 T(V7E_M), /* V5TE. */
12495 T(V7E_M), /* V5TEJ. */
12496 T(V7E_M), /* V6. */
12497 T(V7E_M), /* V6KZ. */
12498 T(V7E_M), /* V6T2. */
12499 T(V7E_M), /* V6K. */
12500 T(V7E_M), /* V7. */
12501 T(V7E_M), /* V6_M. */
12502 T(V7E_M), /* V6S_M. */
12503 T(V7E_M) /* V7E_M. */
12504 };
bca38921
MGD		 12505 const int v8[] =
12506 {
12507 T(V8), /* PRE_V4. */
12508 T(V8), /* V4. */
12509 T(V8), /* V4T. */
12510 T(V8), /* V5T. */
12511 T(V8), /* V5TE. */
12512 T(V8), /* V5TEJ. */
12513 T(V8), /* V6. */
12514 T(V8), /* V6KZ. */
12515 T(V8), /* V6T2. */
12516 T(V8), /* V6K. */
12517 T(V8), /* V7. */
12518 T(V8), /* V6_M. */
12519 T(V8), /* V6S_M. */
12520 T(V8), /* V7E_M. */
12521 T(V8) /* V8. */
12522 };
2fd158eb
TP		 12523 const int v8m_baseline[] =
12524 {
12525 -1, /* PRE_V4. */
12526 -1, /* V4. */
12527 -1, /* V4T. */
12528 -1, /* V5T. */
12529 -1, /* V5TE. */
12530 -1, /* V5TEJ. */
12531 -1, /* V6. */
12532 -1, /* V6KZ. */
12533 -1, /* V6T2. */
12534 -1, /* V6K. */
12535 -1, /* V7. */
12536 T(V8M_BASE), /* V6_M. */
12537 T(V8M_BASE), /* V6S_M. */
12538 -1, /* V7E_M. */
12539 -1, /* V8. */
12540 -1,
12541 T(V8M_BASE) /* V8-M BASELINE. */
12542 };
12543 const int v8m_mainline[] =
12544 {
12545 -1, /* PRE_V4. */
12546 -1, /* V4. */
12547 -1, /* V4T. */
12548 -1, /* V5T. */
12549 -1, /* V5TE. */
12550 -1, /* V5TEJ. */
12551 -1, /* V6. */
12552 -1, /* V6KZ. */
12553 -1, /* V6T2. */
12554 -1, /* V6K. */
12555 T(V8M_MAIN), /* V7. */
12556 T(V8M_MAIN), /* V6_M. */
12557 T(V8M_MAIN), /* V6S_M. */
12558 T(V8M_MAIN), /* V7E_M. */
12559 -1, /* V8. */
12560 -1,
12561 T(V8M_MAIN), /* V8-M BASELINE. */
12562 T(V8M_MAIN) /* V8-M MAINLINE. */
12563 };
91e22acd
AS		 12564 const int v4t_plus_v6_m[] =
12565 {
12566 -1, /* PRE_V4. */
12567 -1, /* V4. */
12568 T(V4T), /* V4T. */
12569 T(V5T), /* V5T. */
12570 T(V5TE), /* V5TE. */
12571 T(V5TEJ), /* V5TEJ. */
12572 T(V6), /* V6. */
12573 T(V6KZ), /* V6KZ. */
12574 T(V6T2), /* V6T2. */
12575 T(V6K), /* V6K. */
12576 T(V7), /* V7. */
12577 T(V6_M), /* V6_M. */
12578 T(V6S_M), /* V6S_M. */
9e3c6df6 12579 T(V7E_M), /* V7E_M. */
bca38921 12580 T(V8), /* V8. */
4ed7ed8d 12581 -1, /* Unused. */
2fd158eb
TP		 12582 T(V8M_BASE), /* V8-M BASELINE. */
12583 T(V8M_MAIN), /* V8-M MAINLINE. */
91e22acd
AS		 12584 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
12585 };
12586 const int *comb[] =
12587 {
12588 v6t2,
12589 v6k,
12590 v7,
12591 v6_m,
12592 v6s_m,
9e3c6df6 12593 v7e_m,
bca38921 12594 v8,
4ed7ed8d 12595 NULL,
2fd158eb
TP		 12596 v8m_baseline,
12597 v8m_mainline,
91e22acd
AS		 12598 /* Pseudo-architecture. */
12599 v4t_plus_v6_m
12600 };
12601
12602 /* Check we've not got a higher architecture than we know about. */
12603
9e3c6df6 12604 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 12605 {
3895f852 12606 _bfd_error_handler (_("error: %B: Unknown CPU architecture"), ibfd);
91e22acd
AS		 12607 return -1;
12608 }
12609
12610 /* Override old tag if we have a Tag_also_compatible_with on the output. */
12611
12612 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
12613 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
12614 oldtag = T(V4T_PLUS_V6_M);
12615
12616 /* And override the new tag if we have a Tag_also_compatible_with on the
12617 input. */
12618
12619 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
12620 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
12621 newtag = T(V4T_PLUS_V6_M);
12622
12623 tagl = (oldtag < newtag) ? oldtag : newtag;
12624 result = tagh = (oldtag > newtag) ? oldtag : newtag;
12625
12626 /* Architectures before V6KZ add features monotonically. */
12627 if (tagh <= TAG_CPU_ARCH_V6KZ)
12628 return result;
12629
4ed7ed8d 12630 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
91e22acd
AS		 12631
12632 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
12633 as the canonical version. */
12634 if (result == T(V4T_PLUS_V6_M))
12635 {
12636 result = T(V4T);
12637 *secondary_compat_out = T(V6_M);
12638 }
12639 else
12640 *secondary_compat_out = -1;
12641
12642 if (result == -1)
12643 {
3895f852 12644 _bfd_error_handler (_("error: %B: Conflicting CPU architectures %d/%d"),
91e22acd
AS		 12645 ibfd, oldtag, newtag);
12646 return -1;
12647 }
12648
12649 return result;
12650#undef T
8e79c3df
CM		 12651}
12652
ac56ee8f
MGD		 12653/* Query attributes object to see if integer divide instructions may be
12654 present in an object. */
12655static bfd_boolean
12656elf32_arm_attributes_accept_div (const obj_attribute *attr)
12657{
12658 int arch = attr[Tag_CPU_arch].i;
12659 int profile = attr[Tag_CPU_arch_profile].i;
12660
12661 switch (attr[Tag_DIV_use].i)
12662 {
12663 case 0:
12664 /* Integer divide allowed if instruction contained in archetecture. */
12665 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
12666 return TRUE;
12667 else if (arch >= TAG_CPU_ARCH_V7E_M)
12668 return TRUE;
12669 else
12670 return FALSE;
12671
12672 case 1:
12673 /* Integer divide explicitly prohibited. */
12674 return FALSE;
12675
12676 default:
12677 /* Unrecognised case - treat as allowing divide everywhere. */
12678 case 2:
12679 /* Integer divide allowed in ARM state. */
12680 return TRUE;
12681 }
12682}
12683
12684/* Query attributes object to see if integer divide instructions are
12685 forbidden to be in the object. This is not the inverse of
12686 elf32_arm_attributes_accept_div. */
12687static bfd_boolean
12688elf32_arm_attributes_forbid_div (const obj_attribute *attr)
12689{
12690 return attr[Tag_DIV_use].i == 1;
12691}
12692
ee065d83
PB		 12693/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
12694 are conflicting attributes. */
906e58ca 12695
ee065d83
PB		 12696static bfd_boolean
12697elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd)
12698{
104d59d1
JM		 12699 obj_attribute *in_attr;
12700 obj_attribute *out_attr;
ee065d83
PB		 12701 /* Some tags have 0 = don't care, 1 = strong requirement,
12702 2 = weak requirement. */
91e22acd 12703 static const int order_021[3] = {0, 2, 1};
ee065d83 12704 int i;
91e22acd 12705 bfd_boolean result = TRUE;
9274e9de 12706 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 12707
3e6b1042
DJ		 12708 /* Skip the linker stubs file. This preserves previous behavior
12709 of accepting unknown attributes in the first input file - but
12710 is that a bug? */
12711 if (ibfd->flags & BFD_LINKER_CREATED)
12712 return TRUE;
12713
9274e9de
TG		 12714 /* Skip any input that hasn't attribute section.
12715 This enables to link object files without attribute section with
12716 any others. */
12717 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
12718 return TRUE;
12719
104d59d1 12720 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 12721 {
12722 /* This is the first object. Copy the attributes. */
104d59d1 12723 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 12724
cd21e546
MGD		 12725 out_attr = elf_known_obj_attributes_proc (obfd);
12726
004ae526
PB		 12727 /* Use the Tag_null value to indicate the attributes have been
12728 initialized. */
cd21e546 12729 out_attr[0].i = 1;
004ae526 12730
cd21e546
MGD		 12731 /* We do not output objects with Tag_MPextension_use_legacy - we move
12732 the attribute's value to Tag_MPextension_use. */
12733 if (out_attr[Tag_MPextension_use_legacy].i != 0)
12734 {
12735 if (out_attr[Tag_MPextension_use].i != 0
12736 && out_attr[Tag_MPextension_use_legacy].i
99059e56 12737 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 12738 {
12739 _bfd_error_handler
12740 (_("Error: %B has both the current and legacy "
12741 "Tag_MPextension_use attributes"), ibfd);
12742 result = FALSE;
12743 }
12744
12745 out_attr[Tag_MPextension_use] =
12746 out_attr[Tag_MPextension_use_legacy];
12747 out_attr[Tag_MPextension_use_legacy].type = 0;
12748 out_attr[Tag_MPextension_use_legacy].i = 0;
12749 }
12750
12751 return result;
ee065d83
PB		 12752 }
12753
104d59d1
JM		 12754 in_attr = elf_known_obj_attributes_proc (ibfd);
12755 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 12756 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
12757 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
12758 {
5c294fee
TG		 12759 /* Ignore mismatches if the object doesn't use floating point or is
12760 floating point ABI independent. */
12761 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
12762 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
12763 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 12764 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 12765 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
12766 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 12767 {
12768 _bfd_error_handler
3895f852 12769 (_("error: %B uses VFP register arguments, %B does not"),
deddc40b
NS		 12770 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
12771 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 12772 result = FALSE;
ee065d83
PB		 12773 }
12774 }
12775
3de4a297 12776 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 12777 {
12778 /* Merge this attribute with existing attributes. */
12779 switch (i)
12780 {
12781 case Tag_CPU_raw_name:
12782 case Tag_CPU_name:
6a631e86 12783 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 12784 break;
12785
12786 case Tag_ABI_optimization_goals:
12787 case Tag_ABI_FP_optimization_goals:
12788 /* Use the first value seen. */
12789 break;
12790
12791 case Tag_CPU_arch:
91e22acd
AS		 12792 {
12793 int secondary_compat = -1, secondary_compat_out = -1;
12794 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 12795 int arch_attr;
12796 static const char *name_table[] =
12797 {
91e22acd
AS		 12798 /* These aren't real CPU names, but we can't guess
12799 that from the architecture version alone. */
12800 "Pre v4",
12801 "ARM v4",
12802 "ARM v4T",
12803 "ARM v5T",
12804 "ARM v5TE",
12805 "ARM v5TEJ",
12806 "ARM v6",
12807 "ARM v6KZ",
12808 "ARM v6T2",
12809 "ARM v6K",
12810 "ARM v7",
12811 "ARM v6-M",
bca38921 12812 "ARM v6S-M",
2fd158eb
TP		 12813 "ARM v8",
12814 "",
12815 "ARM v8-M.baseline",
12816 "ARM v8-M.mainline",
91e22acd
AS		 12817 };
12818
12819 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
12820 secondary_compat = get_secondary_compatible_arch (ibfd);
12821 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 12822 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
12823 &secondary_compat_out,
12824 in_attr[i].i,
12825 secondary_compat);
12826
12827 /* Return with error if failed to merge. */
12828 if (arch_attr == -1)
12829 return FALSE;
12830
12831 out_attr[i].i = arch_attr;
12832
91e22acd
AS		 12833 set_secondary_compatible_arch (obfd, secondary_compat_out);
12834
12835 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
12836 if (out_attr[i].i == saved_out_attr)
12837 ; /* Leave the names alone. */
12838 else if (out_attr[i].i == in_attr[i].i)
12839 {
12840 /* The output architecture has been changed to match the
12841 input architecture. Use the input names. */
12842 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
12843 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
12844 : NULL;
12845 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
12846 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
12847 : NULL;
12848 }
12849 else
12850 {
12851 out_attr[Tag_CPU_name].s = NULL;
12852 out_attr[Tag_CPU_raw_name].s = NULL;
12853 }
12854
12855 /* If we still don't have a value for Tag_CPU_name,
12856 make one up now. Tag_CPU_raw_name remains blank. */
12857 if (out_attr[Tag_CPU_name].s == NULL
12858 && out_attr[i].i < ARRAY_SIZE (name_table))
12859 out_attr[Tag_CPU_name].s =
12860 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
12861 }
12862 break;
12863
ee065d83
PB		 12864 case Tag_ARM_ISA_use:
12865 case Tag_THUMB_ISA_use:
ee065d83 12866 case Tag_WMMX_arch:
91e22acd
AS		 12867 case Tag_Advanced_SIMD_arch:
12868 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 12869 case Tag_ABI_FP_rounding:
ee065d83
PB		 12870 case Tag_ABI_FP_exceptions:
12871 case Tag_ABI_FP_user_exceptions:
12872 case Tag_ABI_FP_number_model:
75375b3e 12873 case Tag_FP_HP_extension:
91e22acd
AS		 12874 case Tag_CPU_unaligned_access:
12875 case Tag_T2EE_use:
91e22acd 12876 case Tag_MPextension_use:
ee065d83
PB		 12877 /* Use the largest value specified. */
12878 if (in_attr[i].i > out_attr[i].i)
12879 out_attr[i].i = in_attr[i].i;
12880 break;
12881
75375b3e 12882 case Tag_ABI_align_preserved:
91e22acd
AS		 12883 case Tag_ABI_PCS_RO_data:
12884 /* Use the smallest value specified. */
12885 if (in_attr[i].i < out_attr[i].i)
12886 out_attr[i].i = in_attr[i].i;
12887 break;
12888
75375b3e 12889 case Tag_ABI_align_needed:
91e22acd 12890 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 12891 && (in_attr[Tag_ABI_align_preserved].i == 0
12892 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 12893 {
91e22acd
AS		 12894 /* This error message should be enabled once all non-conformant
12895 binaries in the toolchain have had the attributes set
12896 properly.
ee065d83 12897 _bfd_error_handler
3895f852 12898 (_("error: %B: 8-byte data alignment conflicts with %B"),
91e22acd
AS		 12899 obfd, ibfd);
12900 result = FALSE; */
ee065d83 12901 }
91e22acd
AS		 12902 /* Fall through. */
12903 case Tag_ABI_FP_denormal:
12904 case Tag_ABI_PCS_GOT_use:
12905 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
12906 value if greater than 2 (for future-proofing). */
12907 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
12908 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
12909 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 12910 out_attr[i].i = in_attr[i].i;
12911 break;
91e22acd 12912
75375b3e
MGD		 12913 case Tag_Virtualization_use:
12914 /* The virtualization tag effectively stores two bits of
12915 information: the intended use of TrustZone (in bit 0), and the
12916 intended use of Virtualization (in bit 1). */
12917 if (out_attr[i].i == 0)
12918 out_attr[i].i = in_attr[i].i;
12919 else if (in_attr[i].i != 0
12920 && in_attr[i].i != out_attr[i].i)
12921 {
12922 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
12923 out_attr[i].i = 3;
12924 else
12925 {
12926 _bfd_error_handler
12927 (_("error: %B: unable to merge virtualization attributes "
12928 "with %B"),
12929 obfd, ibfd);
12930 result = FALSE;
12931 }
12932 }
12933 break;
91e22acd
AS		 12934
12935 case Tag_CPU_arch_profile:
12936 if (out_attr[i].i != in_attr[i].i)
12937 {
12938 /* 0 will merge with anything.
12939 'A' and 'S' merge to 'A'.
12940 'R' and 'S' merge to 'R'.
99059e56 12941 'M' and 'A|R|S' is an error. */
91e22acd
AS		 12942 if (out_attr[i].i == 0
12943 || (out_attr[i].i == 'S'
12944 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
12945 out_attr[i].i = in_attr[i].i;
12946 else if (in_attr[i].i == 0
12947 || (in_attr[i].i == 'S'
12948 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 12949 ; /* Do nothing. */
91e22acd
AS		 12950 else
12951 {
12952 _bfd_error_handler
3895f852 12953 (_("error: %B: Conflicting architecture profiles %c/%c"),
91e22acd
AS		 12954 ibfd,
12955 in_attr[i].i ? in_attr[i].i : '0',
12956 out_attr[i].i ? out_attr[i].i : '0');
12957 result = FALSE;
12958 }
12959 }
12960 break;
15afaa63
TP		 12961
12962 case Tag_DSP_extension:
12963 /* No need to change output value if any of:
12964 - pre (<=) ARMv5T input architecture (do not have DSP)
12965 - M input profile not ARMv7E-M and do not have DSP. */
12966 if (in_attr[Tag_CPU_arch].i <= 3
12967 || (in_attr[Tag_CPU_arch_profile].i == 'M'
12968 && in_attr[Tag_CPU_arch].i != 13
12969 && in_attr[i].i == 0))
12970 ; /* Do nothing. */
12971 /* Output value should be 0 if DSP part of architecture, ie.
12972 - post (>=) ARMv5te architecture output
12973 - A, R or S profile output or ARMv7E-M output architecture. */
12974 else if (out_attr[Tag_CPU_arch].i >= 4
12975 && (out_attr[Tag_CPU_arch_profile].i == 'A'
12976 || out_attr[Tag_CPU_arch_profile].i == 'R'
12977 || out_attr[Tag_CPU_arch_profile].i == 'S'
12978 || out_attr[Tag_CPU_arch].i == 13))
12979 out_attr[i].i = 0;
12980 /* Otherwise, DSP instructions are added and not part of output
12981 architecture. */
12982 else
12983 out_attr[i].i = 1;
12984 break;
12985
75375b3e 12986 case Tag_FP_arch:
62f3b8c8 12987 {
4547cb56
NC		 12988 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
12989 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
12990 when it's 0. It might mean absence of FP hardware if
99654aaf 12991 Tag_FP_arch is zero. */
4547cb56 12992
a715796b 12993#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 12994 static const struct
12995 {
12996 int ver;
12997 int regs;
bca38921 12998 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 12999 {
13000 {0, 0},
13001 {1, 16},
13002 {2, 16},
13003 {3, 32},
13004 {3, 16},
13005 {4, 32},
bca38921 13006 {4, 16},
a715796b
TG		 13007 {8, 32},
13008 {8, 16}
62f3b8c8
PB		 13009 };
13010 int ver;
13011 int regs;
13012 int newval;
13013
4547cb56
NC		 13014 /* If the output has no requirement about FP hardware,
13015 follow the requirement of the input. */
13016 if (out_attr[i].i == 0)
13017 {
13018 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
13019 out_attr[i].i = in_attr[i].i;
13020 out_attr[Tag_ABI_HardFP_use].i
13021 = in_attr[Tag_ABI_HardFP_use].i;
13022 break;
13023 }
13024 /* If the input has no requirement about FP hardware, do
13025 nothing. */
13026 else if (in_attr[i].i == 0)
13027 {
13028 BFD_ASSERT (in_attr[Tag_ABI_HardFP_use].i == 0);
13029 break;
13030 }
13031
13032 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 13033 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 13034
13035 /* If both the input and the output have zero Tag_ABI_HardFP_use,
13036 do nothing. */
13037 if (in_attr[Tag_ABI_HardFP_use].i == 0
13038 && out_attr[Tag_ABI_HardFP_use].i == 0)
13039 ;
13040 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 13041 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 13042 else if (in_attr[Tag_ABI_HardFP_use].i
13043 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 13044 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 13045
13046 /* Now we can handle Tag_FP_arch. */
13047
bca38921
MGD		 13048 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
13049 pick the biggest. */
13050 if (in_attr[i].i >= VFP_VERSION_COUNT
13051 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 13052 {
13053 out_attr[i] = in_attr[i];
13054 break;
13055 }
13056 /* The output uses the superset of input features
13057 (ISA version) and registers. */
13058 ver = vfp_versions[in_attr[i].i].ver;
13059 if (ver < vfp_versions[out_attr[i].i].ver)
13060 ver = vfp_versions[out_attr[i].i].ver;
13061 regs = vfp_versions[in_attr[i].i].regs;
13062 if (regs < vfp_versions[out_attr[i].i].regs)
13063 regs = vfp_versions[out_attr[i].i].regs;
13064 /* This assumes all possible supersets are also a valid
99059e56 13065 options. */
bca38921 13066 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 13067 {
13068 if (regs == vfp_versions[newval].regs
13069 && ver == vfp_versions[newval].ver)
13070 break;
13071 }
13072 out_attr[i].i = newval;
13073 }
b1cc4aeb 13074 break;
ee065d83
PB		 13075 case Tag_PCS_config:
13076 if (out_attr[i].i == 0)
13077 out_attr[i].i = in_attr[i].i;
b6009aca 13078 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 13079 {
13080 /* It's sometimes ok to mix different configs, so this is only
99059e56 13081 a warning. */
ee065d83
PB		 13082 _bfd_error_handler
13083 (_("Warning: %B: Conflicting platform configuration"), ibfd);
13084 }
13085 break;
13086 case Tag_ABI_PCS_R9_use:
004ae526
PB		 13087 if (in_attr[i].i != out_attr[i].i
13088 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 13089 && in_attr[i].i != AEABI_R9_unused)
13090 {
13091 _bfd_error_handler
3895f852 13092 (_("error: %B: Conflicting use of R9"), ibfd);
91e22acd 13093 result = FALSE;
ee065d83
PB		 13094 }
13095 if (out_attr[i].i == AEABI_R9_unused)
13096 out_attr[i].i = in_attr[i].i;
13097 break;
13098 case Tag_ABI_PCS_RW_data:
13099 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
13100 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
13101 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
13102 {
13103 _bfd_error_handler
3895f852 13104 (_("error: %B: SB relative addressing conflicts with use of R9"),
ee065d83 13105 ibfd);
91e22acd 13106 result = FALSE;
ee065d83
PB		 13107 }
13108 /* Use the smallest value specified. */
13109 if (in_attr[i].i < out_attr[i].i)
13110 out_attr[i].i = in_attr[i].i;
13111 break;
ee065d83 13112 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 13113 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
13114 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 13115 {
13116 _bfd_error_handler
a9dc9481
JM		 13117 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
13118 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 13119 }
a9dc9481 13120 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 13121 out_attr[i].i = in_attr[i].i;
13122 break;
ee065d83
PB		 13123 case Tag_ABI_enum_size:
13124 if (in_attr[i].i != AEABI_enum_unused)
13125 {
13126 if (out_attr[i].i == AEABI_enum_unused
13127 || out_attr[i].i == AEABI_enum_forced_wide)
13128 {
13129 /* The existing object is compatible with anything.
13130 Use whatever requirements the new object has. */
13131 out_attr[i].i = in_attr[i].i;
13132 }
13133 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 13134 && out_attr[i].i != in_attr[i].i
0ffa91dd 13135 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 13136 {
91e22acd 13137 static const char *aeabi_enum_names[] =
bf21ed78 13138 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 13139 const char *in_name =
13140 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13141 ? aeabi_enum_names[in_attr[i].i]
13142 : "<unknown>";
13143 const char *out_name =
13144 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
13145 ? aeabi_enum_names[out_attr[i].i]
13146 : "<unknown>";
ee065d83 13147 _bfd_error_handler
bf21ed78 13148 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 13149 ibfd, in_name, out_name);
ee065d83
PB		 13150 }
13151 }
13152 break;
13153 case Tag_ABI_VFP_args:
13154 /* Aready done. */
13155 break;
13156 case Tag_ABI_WMMX_args:
13157 if (in_attr[i].i != out_attr[i].i)
13158 {
13159 _bfd_error_handler
3895f852 13160 (_("error: %B uses iWMMXt register arguments, %B does not"),
ee065d83 13161 ibfd, obfd);
91e22acd 13162 result = FALSE;
ee065d83
PB		 13163 }
13164 break;
7b86a9fa
AS		 13165 case Tag_compatibility:
13166 /* Merged in target-independent code. */
13167 break;
91e22acd 13168 case Tag_ABI_HardFP_use:
4547cb56 13169 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 13170 break;
13171 case Tag_ABI_FP_16bit_format:
13172 if (in_attr[i].i != 0 && out_attr[i].i != 0)
13173 {
13174 if (in_attr[i].i != out_attr[i].i)
13175 {
13176 _bfd_error_handler
3895f852 13177 (_("error: fp16 format mismatch between %B and %B"),
91e22acd
AS		 13178 ibfd, obfd);
13179 result = FALSE;
13180 }
13181 }
13182 if (in_attr[i].i != 0)
13183 out_attr[i].i = in_attr[i].i;
13184 break;
7b86a9fa 13185
cd21e546 13186 case Tag_DIV_use:
ac56ee8f
MGD		 13187 /* A value of zero on input means that the divide instruction may
13188 be used if available in the base architecture as specified via
13189 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
13190 the user did not want divide instructions. A value of 2
13191 explicitly means that divide instructions were allowed in ARM
13192 and Thumb state. */
13193 if (in_attr[i].i == out_attr[i].i)
13194 /* Do nothing. */ ;
13195 else if (elf32_arm_attributes_forbid_div (in_attr)
13196 && !elf32_arm_attributes_accept_div (out_attr))
13197 out_attr[i].i = 1;
13198 else if (elf32_arm_attributes_forbid_div (out_attr)
13199 && elf32_arm_attributes_accept_div (in_attr))
13200 out_attr[i].i = in_attr[i].i;
13201 else if (in_attr[i].i == 2)
13202 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 13203 break;
13204
13205 case Tag_MPextension_use_legacy:
13206 /* We don't output objects with Tag_MPextension_use_legacy - we
13207 move the value to Tag_MPextension_use. */
13208 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
13209 {
13210 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
13211 {
13212 _bfd_error_handler
13213 (_("%B has has both the current and legacy "
b38cadfb 13214 "Tag_MPextension_use attributes"),
cd21e546
MGD		 13215 ibfd);
13216 result = FALSE;
13217 }
13218 }
13219
13220 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
13221 out_attr[Tag_MPextension_use] = in_attr[i];
13222
13223 break;
13224
91e22acd 13225 case Tag_nodefaults:
2d0bb761
AS		 13226 /* This tag is set if it exists, but the value is unused (and is
13227 typically zero). We don't actually need to do anything here -
13228 the merge happens automatically when the type flags are merged
13229 below. */
91e22acd
AS		 13230 break;
13231 case Tag_also_compatible_with:
13232 /* Already done in Tag_CPU_arch. */
13233 break;
13234 case Tag_conformance:
13235 /* Keep the attribute if it matches. Throw it away otherwise.
13236 No attribute means no claim to conform. */
13237 if (!in_attr[i].s || !out_attr[i].s
13238 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
13239 out_attr[i].s = NULL;
13240 break;
3cfad14c 13241
91e22acd 13242 default:
e8b36cd1
JM		 13243 result
13244 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 13245 }
13246
13247 /* If out_attr was copied from in_attr then it won't have a type yet. */
13248 if (in_attr[i].type && !out_attr[i].type)
13249 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 13250 }
13251
104d59d1 13252 /* Merge Tag_compatibility attributes and any common GNU ones. */
5488d830
MGD		 13253 if (!_bfd_elf_merge_object_attributes (ibfd, obfd))
13254 return FALSE;
ee065d83 13255
104d59d1 13256 /* Check for any attributes not known on ARM. */
e8b36cd1 13257 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 13258
91e22acd 13259 return result;
252b5132
RH		 13260}
13261
3a4a14e9
PB		 13262
13263/* Return TRUE if the two EABI versions are incompatible. */
13264
13265static bfd_boolean
13266elf32_arm_versions_compatible (unsigned iver, unsigned over)
13267{
13268 /* v4 and v5 are the same spec before and after it was released,
13269 so allow mixing them. */
13270 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
13271 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
13272 return TRUE;
13273
13274 return (iver == over);
13275}
13276
252b5132
RH		 13277/* Merge backend specific data from an object file to the output
13278 object file when linking. */
9b485d32 13279
b34976b6 13280static bfd_boolean
21d799b5 13281elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd);
252b5132 13282
9b485d32
NC		 13283/* Display the flags field. */
13284
b34976b6 13285static bfd_boolean
57e8b36a 13286elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 13287{
fc830a83
NC		 13288 FILE * file = (FILE *) ptr;
13289 unsigned long flags;
252b5132
RH		 13290
13291 BFD_ASSERT (abfd != NULL && ptr != NULL);
13292
13293 /* Print normal ELF private data. */
13294 _bfd_elf_print_private_bfd_data (abfd, ptr);
13295
fc830a83 13296 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 13297 /* Ignore init flag - it may not be set, despite the flags field
13298 containing valid data. */
252b5132
RH		 13299
13300 /* xgettext:c-format */
9b485d32 13301 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 13302
fc830a83
NC		 13303 switch (EF_ARM_EABI_VERSION (flags))
13304 {
13305 case EF_ARM_EABI_UNKNOWN:
4cc11e76 13306 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 13307 official ARM ELF extended ABI. Hence they are only decoded if
13308 the EABI version is not set. */
fd2ec330 13309 if (flags & EF_ARM_INTERWORK)
9b485d32 13310 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 13311
fd2ec330 13312 if (flags & EF_ARM_APCS_26)
6c571f00 13313 fprintf (file, " [APCS-26]");
fc830a83 13314 else
6c571f00 13315 fprintf (file, " [APCS-32]");
9a5aca8c 13316
96a846ea
RE		 13317 if (flags & EF_ARM_VFP_FLOAT)
13318 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 13319 else if (flags & EF_ARM_MAVERICK_FLOAT)
13320 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 13321 else
13322 fprintf (file, _(" [FPA float format]"));
13323
fd2ec330 13324 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 13325 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 13326
fd2ec330 13327 if (flags & EF_ARM_PIC)
9b485d32 13328 fprintf (file, _(" [position independent]"));
fc830a83 13329
fd2ec330 13330 if (flags & EF_ARM_NEW_ABI)
9b485d32 13331 fprintf (file, _(" [new ABI]"));
9a5aca8c 13332
fd2ec330 13333 if (flags & EF_ARM_OLD_ABI)
9b485d32 13334 fprintf (file, _(" [old ABI]"));
9a5aca8c 13335
fd2ec330 13336 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 13337 fprintf (file, _(" [software FP]"));
9a5aca8c 13338
96a846ea
RE		 13339 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
13340 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 13341 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
13342 | EF_ARM_MAVERICK_FLOAT);
fc830a83 13343 break;
9a5aca8c 13344
fc830a83 13345 case EF_ARM_EABI_VER1:
9b485d32 13346 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 13347
fc830a83 13348 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 13349 fprintf (file, _(" [sorted symbol table]"));
fc830a83 13350 else
9b485d32 13351 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 13352
fc830a83
NC		 13353 flags &= ~ EF_ARM_SYMSARESORTED;
13354 break;
9a5aca8c 13355
fd2ec330
PB		 13356 case EF_ARM_EABI_VER2:
13357 fprintf (file, _(" [Version2 EABI]"));
13358
13359 if (flags & EF_ARM_SYMSARESORTED)
13360 fprintf (file, _(" [sorted symbol table]"));
13361 else
13362 fprintf (file, _(" [unsorted symbol table]"));
13363
13364 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
13365 fprintf (file, _(" [dynamic symbols use segment index]"));
13366
13367 if (flags & EF_ARM_MAPSYMSFIRST)
13368 fprintf (file, _(" [mapping symbols precede others]"));
13369
99e4ae17 13370 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 13371 | EF_ARM_MAPSYMSFIRST);
13372 break;
13373
d507cf36
PB		 13374 case EF_ARM_EABI_VER3:
13375 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 13376 break;
13377
13378 case EF_ARM_EABI_VER4:
13379 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 13380 goto eabi;
d507cf36 13381
3a4a14e9
PB		 13382 case EF_ARM_EABI_VER5:
13383 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 13384
13385 if (flags & EF_ARM_ABI_FLOAT_SOFT)
13386 fprintf (file, _(" [soft-float ABI]"));
13387
13388 if (flags & EF_ARM_ABI_FLOAT_HARD)
13389 fprintf (file, _(" [hard-float ABI]"));
13390
13391 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
13392
3a4a14e9 13393 eabi:
d507cf36
PB		 13394 if (flags & EF_ARM_BE8)
13395 fprintf (file, _(" [BE8]"));
13396
13397 if (flags & EF_ARM_LE8)
13398 fprintf (file, _(" [LE8]"));
13399
13400 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
13401 break;
13402
fc830a83 13403 default:
9b485d32 13404 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 13405 break;
13406 }
252b5132 13407
fc830a83 13408 flags &= ~ EF_ARM_EABIMASK;
252b5132 13409
fc830a83 13410 if (flags & EF_ARM_RELEXEC)
9b485d32 13411 fprintf (file, _(" [relocatable executable]"));
252b5132 13412
a5721edd 13413 flags &= ~EF_ARM_RELEXEC;
fc830a83
NC		 13414
13415 if (flags)
9b485d32 13416 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 13417
252b5132
RH		 13418 fputc ('\n', file);
13419
b34976b6 13420 return TRUE;
252b5132
RH		 13421}
13422
13423static int
57e8b36a 13424elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 13425{
2f0ca46a
NC		 13426 switch (ELF_ST_TYPE (elf_sym->st_info))
13427 {
13428 case STT_ARM_TFUNC:
13429 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 13430
2f0ca46a
NC		 13431 case STT_ARM_16BIT:
13432 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
13433 This allows us to distinguish between data used by Thumb instructions
13434 and non-data (which is probably code) inside Thumb regions of an
13435 executable. */
1a0eb693 13436 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 13437 return ELF_ST_TYPE (elf_sym->st_info);
13438 break;
9a5aca8c 13439
ce855c42
NC		 13440 default:
13441 break;
2f0ca46a
NC		 13442 }
13443
13444 return type;
252b5132 13445}
f21f3fe0 13446
252b5132 13447static asection *
07adf181
AM		 13448elf32_arm_gc_mark_hook (asection *sec,
13449 struct bfd_link_info *info,
13450 Elf_Internal_Rela *rel,
13451 struct elf_link_hash_entry *h,
13452 Elf_Internal_Sym *sym)
252b5132
RH		 13453{
13454 if (h != NULL)
07adf181 13455 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 13456 {
13457 case R_ARM_GNU_VTINHERIT:
13458 case R_ARM_GNU_VTENTRY:
07adf181
AM		 13459 return NULL;
13460 }
9ad5cbcf 13461
07adf181 13462 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 13463}
13464
780a67af
NC		 13465/* Update the got entry reference counts for the section being removed. */
13466
b34976b6 13467static bfd_boolean
ba93b8ac
DJ		 13468elf32_arm_gc_sweep_hook (bfd * abfd,
13469 struct bfd_link_info * info,
13470 asection * sec,
13471 const Elf_Internal_Rela * relocs)
252b5132 13472{
5e681ec4
PB		 13473 Elf_Internal_Shdr *symtab_hdr;
13474 struct elf_link_hash_entry **sym_hashes;
13475 bfd_signed_vma *local_got_refcounts;
13476 const Elf_Internal_Rela *rel, *relend;
eb043451
PB		 13477 struct elf32_arm_link_hash_table * globals;
13478
0e1862bb 13479 if (bfd_link_relocatable (info))
7dda2462
TG		 13480 return TRUE;
13481
eb043451 13482 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13483 if (globals == NULL)
13484 return FALSE;
5e681ec4
PB		 13485
13486 elf_section_data (sec)->local_dynrel = NULL;
13487
0ffa91dd 13488 symtab_hdr = & elf_symtab_hdr (abfd);
5e681ec4
PB		 13489 sym_hashes = elf_sym_hashes (abfd);
13490 local_got_refcounts = elf_local_got_refcounts (abfd);
13491
906e58ca 13492 check_use_blx (globals);
bd97cb95 13493
5e681ec4
PB		 13494 relend = relocs + sec->reloc_count;
13495 for (rel = relocs; rel < relend; rel++)
eb043451 13496 {
3eb128b2
AM		 13497 unsigned long r_symndx;
13498 struct elf_link_hash_entry *h = NULL;
f6e32f6d 13499 struct elf32_arm_link_hash_entry *eh;
eb043451 13500 int r_type;
34e77a92 13501 bfd_boolean call_reloc_p;
f6e32f6d
RS		 13502 bfd_boolean may_become_dynamic_p;
13503 bfd_boolean may_need_local_target_p;
34e77a92
RS		 13504 union gotplt_union *root_plt;
13505 struct arm_plt_info *arm_plt;
5e681ec4 13506
3eb128b2
AM		 13507 r_symndx = ELF32_R_SYM (rel->r_info);
13508 if (r_symndx >= symtab_hdr->sh_info)
13509 {
13510 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
13511 while (h->root.type == bfd_link_hash_indirect
13512 || h->root.type == bfd_link_hash_warning)
13513 h = (struct elf_link_hash_entry *) h->root.u.i.link;
13514 }
f6e32f6d
RS		 13515 eh = (struct elf32_arm_link_hash_entry *) h;
13516
34e77a92 13517 call_reloc_p = FALSE;
f6e32f6d
RS		 13518 may_become_dynamic_p = FALSE;
13519 may_need_local_target_p = FALSE;
3eb128b2 13520
eb043451 13521 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 13522 r_type = arm_real_reloc_type (globals, r_type);
eb043451
PB		 13523 switch (r_type)
13524 {
13525 case R_ARM_GOT32:
eb043451 13526 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 13527 case R_ARM_TLS_GD32:
13528 case R_ARM_TLS_IE32:
3eb128b2 13529 if (h != NULL)
eb043451 13530 {
eb043451
PB		 13531 if (h->got.refcount > 0)
13532 h->got.refcount -= 1;
13533 }
13534 else if (local_got_refcounts != NULL)
13535 {
13536 if (local_got_refcounts[r_symndx] > 0)
13537 local_got_refcounts[r_symndx] -= 1;
13538 }
13539 break;
13540
ba93b8ac 13541 case R_ARM_TLS_LDM32:
4dfe6ac6 13542 globals->tls_ldm_got.refcount -= 1;
ba93b8ac
DJ		 13543 break;
13544
eb043451
PB		 13545 case R_ARM_PC24:
13546 case R_ARM_PLT32:
5b5bb741
PB		 13547 case R_ARM_CALL:
13548 case R_ARM_JUMP24:
eb043451 13549 case R_ARM_PREL31:
c19d1205 13550 case R_ARM_THM_CALL:
bd97cb95
DJ		 13551 case R_ARM_THM_JUMP24:
13552 case R_ARM_THM_JUMP19:
34e77a92 13553 call_reloc_p = TRUE;
f6e32f6d
RS		 13554 may_need_local_target_p = TRUE;
13555 break;
13556
13557 case R_ARM_ABS12:
13558 if (!globals->vxworks_p)
13559 {
13560 may_need_local_target_p = TRUE;
13561 break;
13562 }
13563 /* Fall through. */
13564 case R_ARM_ABS32:
13565 case R_ARM_ABS32_NOI:
13566 case R_ARM_REL32:
13567 case R_ARM_REL32_NOI:
b6895b4f
PB		 13568 case R_ARM_MOVW_ABS_NC:
13569 case R_ARM_MOVT_ABS:
13570 case R_ARM_MOVW_PREL_NC:
13571 case R_ARM_MOVT_PREL:
13572 case R_ARM_THM_MOVW_ABS_NC:
13573 case R_ARM_THM_MOVT_ABS:
13574 case R_ARM_THM_MOVW_PREL_NC:
13575 case R_ARM_THM_MOVT_PREL:
b7693d02 13576 /* Should the interworking branches be here also? */
0e1862bb 13577 if ((bfd_link_pic (info) || globals->root.is_relocatable_executable)
34e77a92
RS		 13578 && (sec->flags & SEC_ALLOC) != 0)
13579 {
13580 if (h == NULL
469a3493 13581 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 13582 {
13583 call_reloc_p = TRUE;
13584 may_need_local_target_p = TRUE;
13585 }
13586 else
13587 may_become_dynamic_p = TRUE;
13588 }
f6e32f6d
RS		 13589 else
13590 may_need_local_target_p = TRUE;
13591 break;
b7693d02 13592
f6e32f6d
RS		 13593 default:
13594 break;
13595 }
5e681ec4 13596
34e77a92
RS		 13597 if (may_need_local_target_p
13598 && elf32_arm_get_plt_info (abfd, eh, r_symndx, &root_plt, &arm_plt))
f6e32f6d 13599 {
27586251
HPN		 13600 /* If PLT refcount book-keeping is wrong and too low, we'll
13601 see a zero value (going to -1) for the root PLT reference
13602 count. */
13603 if (root_plt->refcount >= 0)
13604 {
13605 BFD_ASSERT (root_plt->refcount != 0);
13606 root_plt->refcount -= 1;
13607 }
13608 else
13609 /* A value of -1 means the symbol has become local, forced
13610 or seeing a hidden definition. Any other negative value
13611 is an error. */
13612 BFD_ASSERT (root_plt->refcount == -1);
34e77a92
RS		 13613
13614 if (!call_reloc_p)
13615 arm_plt->noncall_refcount--;
5e681ec4 13616
f6e32f6d 13617 if (r_type == R_ARM_THM_CALL)
34e77a92 13618 arm_plt->maybe_thumb_refcount--;
bd97cb95 13619
f6e32f6d
RS		 13620 if (r_type == R_ARM_THM_JUMP24
13621 || r_type == R_ARM_THM_JUMP19)
34e77a92 13622 arm_plt->thumb_refcount--;
f6e32f6d 13623 }
5e681ec4 13624
34e77a92 13625 if (may_become_dynamic_p)
f6e32f6d
RS		 13626 {
13627 struct elf_dyn_relocs **pp;
13628 struct elf_dyn_relocs *p;
5e681ec4 13629
34e77a92 13630 if (h != NULL)
9c489990 13631 pp = &(eh->dyn_relocs);
34e77a92
RS		 13632 else
13633 {
13634 Elf_Internal_Sym *isym;
13635
13636 isym = bfd_sym_from_r_symndx (&globals->sym_cache,
13637 abfd, r_symndx);
13638 if (isym == NULL)
13639 return FALSE;
13640 pp = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
13641 if (pp == NULL)
13642 return FALSE;
13643 }
9c489990 13644 for (; (p = *pp) != NULL; pp = &p->next)
f6e32f6d
RS		 13645 if (p->sec == sec)
13646 {
13647 /* Everything must go for SEC. */
13648 *pp = p->next;
13649 break;
13650 }
eb043451
PB		 13651 }
13652 }
5e681ec4 13653
b34976b6 13654 return TRUE;
252b5132
RH		 13655}
13656
780a67af
NC		 13657/* Look through the relocs for a section during the first phase. */
13658
b34976b6 13659static bfd_boolean
57e8b36a
NC		 13660elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
13661 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 13662{
b34976b6
AM		 13663 Elf_Internal_Shdr *symtab_hdr;
13664 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 13665 const Elf_Internal_Rela *rel;
13666 const Elf_Internal_Rela *rel_end;
13667 bfd *dynobj;
5e681ec4 13668 asection *sreloc;
5e681ec4 13669 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 13670 bfd_boolean call_reloc_p;
13671 bfd_boolean may_become_dynamic_p;
13672 bfd_boolean may_need_local_target_p;
ce98a316 13673 unsigned long nsyms;
9a5aca8c 13674
0e1862bb 13675 if (bfd_link_relocatable (info))
b34976b6 13676 return TRUE;
9a5aca8c 13677
0ffa91dd
NC		 13678 BFD_ASSERT (is_arm_elf (abfd));
13679
5e681ec4 13680 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13681 if (htab == NULL)
13682 return FALSE;
13683
5e681ec4 13684 sreloc = NULL;
9a5aca8c 13685
67687978
PB		 13686 /* Create dynamic sections for relocatable executables so that we can
13687 copy relocations. */
13688 if (htab->root.is_relocatable_executable
13689 && ! htab->root.dynamic_sections_created)
13690 {
13691 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
13692 return FALSE;
13693 }
13694
cbc704f3
RS		 13695 if (htab->root.dynobj == NULL)
13696 htab->root.dynobj = abfd;
34e77a92
RS		 13697 if (!create_ifunc_sections (info))
13698 return FALSE;
cbc704f3
RS		 13699
13700 dynobj = htab->root.dynobj;
13701
0ffa91dd 13702 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 13703 sym_hashes = elf_sym_hashes (abfd);
ce98a316 13704 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 13705
252b5132
RH		 13706 rel_end = relocs + sec->reloc_count;
13707 for (rel = relocs; rel < rel_end; rel++)
13708 {
34e77a92 13709 Elf_Internal_Sym *isym;
252b5132 13710 struct elf_link_hash_entry *h;
b7693d02 13711 struct elf32_arm_link_hash_entry *eh;
252b5132 13712 unsigned long r_symndx;
eb043451 13713 int r_type;
9a5aca8c 13714
252b5132 13715 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 13716 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 13717 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 13718
ce98a316
NC		 13719 if (r_symndx >= nsyms
13720 /* PR 9934: It is possible to have relocations that do not
13721 refer to symbols, thus it is also possible to have an
13722 object file containing relocations but no symbol table. */
cf35638d 13723 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac
DJ		 13724 {
13725 (*_bfd_error_handler) (_("%B: bad symbol index: %d"), abfd,
ce98a316 13726 r_symndx);
ba93b8ac
DJ		 13727 return FALSE;
13728 }
13729
34e77a92
RS		 13730 h = NULL;
13731 isym = NULL;
13732 if (nsyms > 0)
973a3492 13733 {
34e77a92
RS		 13734 if (r_symndx < symtab_hdr->sh_info)
13735 {
13736 /* A local symbol. */
13737 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
13738 abfd, r_symndx);
13739 if (isym == NULL)
13740 return FALSE;
13741 }
13742 else
13743 {
13744 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
13745 while (h->root.type == bfd_link_hash_indirect
13746 || h->root.type == bfd_link_hash_warning)
13747 h = (struct elf_link_hash_entry *) h->root.u.i.link;
81fbe831
AM		 13748
13749 /* PR15323, ref flags aren't set for references in the
13750 same object. */
13751 h->root.non_ir_ref = 1;
34e77a92 13752 }
973a3492 13753 }
9a5aca8c 13754
b7693d02
DJ		 13755 eh = (struct elf32_arm_link_hash_entry *) h;
13756
f6e32f6d
RS		 13757 call_reloc_p = FALSE;
13758 may_become_dynamic_p = FALSE;
13759 may_need_local_target_p = FALSE;
13760
0855e32b
NS		 13761 /* Could be done earlier, if h were already available. */
13762 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 13763 switch (r_type)
99059e56 13764 {
5e681ec4 13765 case R_ARM_GOT32:
eb043451 13766 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 13767 case R_ARM_TLS_GD32:
13768 case R_ARM_TLS_IE32:
0855e32b
NS		 13769 case R_ARM_TLS_GOTDESC:
13770 case R_ARM_TLS_DESCSEQ:
13771 case R_ARM_THM_TLS_DESCSEQ:
13772 case R_ARM_TLS_CALL:
13773 case R_ARM_THM_TLS_CALL:
5e681ec4 13774 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 13775 {
13776 int tls_type, old_tls_type;
5e681ec4 13777
ba93b8ac
DJ		 13778 switch (r_type)
13779 {
13780 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 13781
ba93b8ac 13782 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 13783
0855e32b
NS		 13784 case R_ARM_TLS_GOTDESC:
13785 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
13786 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
13787 tls_type = GOT_TLS_GDESC; break;
b38cadfb 13788
ba93b8ac
DJ		 13789 default: tls_type = GOT_NORMAL; break;
13790 }
252b5132 13791
0e1862bb 13792 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 13793 info->flags |= DF_STATIC_TLS;
13794
ba93b8ac
DJ		 13795 if (h != NULL)
13796 {
13797 h->got.refcount++;
13798 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
13799 }
13800 else
13801 {
ba93b8ac 13802 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 13803 if (!elf32_arm_allocate_local_sym_info (abfd))
13804 return FALSE;
13805 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 13806 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
13807 }
13808
0855e32b 13809 /* If a variable is accessed with both tls methods, two
99059e56 13810 slots may be created. */
0855e32b
NS		 13811 if (GOT_TLS_GD_ANY_P (old_tls_type)
13812 && GOT_TLS_GD_ANY_P (tls_type))
13813 tls_type |= old_tls_type;
13814
13815 /* We will already have issued an error message if there
13816 is a TLS/non-TLS mismatch, based on the symbol
13817 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 13818 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
13819 && tls_type != GOT_NORMAL)
13820 tls_type |= old_tls_type;
13821
0855e32b 13822 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 13823 method, we're able to relax. Turn off the GDESC flag,
13824 without messing up with any other kind of tls types
6a631e86 13825 that may be involved. */
0855e32b
NS		 13826 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
13827 tls_type &= ~GOT_TLS_GDESC;
13828
ba93b8ac
DJ		 13829 if (old_tls_type != tls_type)
13830 {
13831 if (h != NULL)
13832 elf32_arm_hash_entry (h)->tls_type = tls_type;
13833 else
13834 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
13835 }
13836 }
8029a119 13837 /* Fall through. */
ba93b8ac
DJ		 13838
13839 case R_ARM_TLS_LDM32:
13840 if (r_type == R_ARM_TLS_LDM32)
13841 htab->tls_ldm_got.refcount++;
8029a119 13842 /* Fall through. */
252b5132 13843
c19d1205 13844 case R_ARM_GOTOFF32:
5e681ec4 13845 case R_ARM_GOTPC:
cbc704f3
RS		 13846 if (htab->root.sgot == NULL
13847 && !create_got_section (htab->root.dynobj, info))
13848 return FALSE;
252b5132
RH		 13849 break;
13850
252b5132 13851 case R_ARM_PC24:
7359ea65 13852 case R_ARM_PLT32:
5b5bb741
PB		 13853 case R_ARM_CALL:
13854 case R_ARM_JUMP24:
eb043451 13855 case R_ARM_PREL31:
c19d1205 13856 case R_ARM_THM_CALL:
bd97cb95
DJ		 13857 case R_ARM_THM_JUMP24:
13858 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 13859 call_reloc_p = TRUE;
13860 may_need_local_target_p = TRUE;
13861 break;
13862
13863 case R_ARM_ABS12:
13864 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
13865 ldr __GOTT_INDEX__ offsets. */
13866 if (!htab->vxworks_p)
13867 {
13868 may_need_local_target_p = TRUE;
13869 break;
13870 }
aebf9be7
NC		 13871 else goto jump_over;
13872
f6e32f6d 13873 /* Fall through. */
39623e12 13874
96c23d59
JM		 13875 case R_ARM_MOVW_ABS_NC:
13876 case R_ARM_MOVT_ABS:
13877 case R_ARM_THM_MOVW_ABS_NC:
13878 case R_ARM_THM_MOVT_ABS:
0e1862bb 13879 if (bfd_link_pic (info))
96c23d59
JM		 13880 {
13881 (*_bfd_error_handler)
13882 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
13883 abfd, elf32_arm_howto_table_1[r_type].name,
13884 (h) ? h->root.root.string : "a local symbol");
13885 bfd_set_error (bfd_error_bad_value);
13886 return FALSE;
13887 }
13888
13889 /* Fall through. */
39623e12
PB		 13890 case R_ARM_ABS32:
13891 case R_ARM_ABS32_NOI:
aebf9be7 13892 jump_over:
0e1862bb 13893 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 13894 {
13895 h->pointer_equality_needed = 1;
13896 }
13897 /* Fall through. */
39623e12
PB		 13898 case R_ARM_REL32:
13899 case R_ARM_REL32_NOI:
b6895b4f
PB		 13900 case R_ARM_MOVW_PREL_NC:
13901 case R_ARM_MOVT_PREL:
b6895b4f
PB		 13902 case R_ARM_THM_MOVW_PREL_NC:
13903 case R_ARM_THM_MOVT_PREL:
39623e12 13904
b7693d02 13905 /* Should the interworking branches be listed here? */
0e1862bb 13906 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 13907 && (sec->flags & SEC_ALLOC) != 0)
13908 {
13909 if (h == NULL
469a3493 13910 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 13911 {
13912 /* In shared libraries and relocatable executables,
13913 we treat local relative references as calls;
13914 see the related SYMBOL_CALLS_LOCAL code in
13915 allocate_dynrelocs. */
13916 call_reloc_p = TRUE;
13917 may_need_local_target_p = TRUE;
13918 }
13919 else
13920 /* We are creating a shared library or relocatable
13921 executable, and this is a reloc against a global symbol,
13922 or a non-PC-relative reloc against a local symbol.
13923 We may need to copy the reloc into the output. */
13924 may_become_dynamic_p = TRUE;
13925 }
f6e32f6d
RS		 13926 else
13927 may_need_local_target_p = TRUE;
252b5132
RH		 13928 break;
13929
99059e56
RM		 13930 /* This relocation describes the C++ object vtable hierarchy.
13931 Reconstruct it for later use during GC. */
13932 case R_ARM_GNU_VTINHERIT:
13933 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
13934 return FALSE;
13935 break;
13936
13937 /* This relocation describes which C++ vtable entries are actually
13938 used. Record for later use during GC. */
13939 case R_ARM_GNU_VTENTRY:
13940 BFD_ASSERT (h != NULL);
13941 if (h != NULL
13942 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
13943 return FALSE;
13944 break;
13945 }
f6e32f6d
RS		 13946
13947 if (h != NULL)
13948 {
13949 if (call_reloc_p)
13950 /* We may need a .plt entry if the function this reloc
13951 refers to is in a different object, regardless of the
13952 symbol's type. We can't tell for sure yet, because
13953 something later might force the symbol local. */
13954 h->needs_plt = 1;
13955 else if (may_need_local_target_p)
13956 /* If this reloc is in a read-only section, we might
13957 need a copy reloc. We can't check reliably at this
13958 stage whether the section is read-only, as input
13959 sections have not yet been mapped to output sections.
13960 Tentatively set the flag for now, and correct in
13961 adjust_dynamic_symbol. */
13962 h->non_got_ref = 1;
13963 }
13964
34e77a92
RS		 13965 if (may_need_local_target_p
13966 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 13967 {
34e77a92
RS		 13968 union gotplt_union *root_plt;
13969 struct arm_plt_info *arm_plt;
13970 struct arm_local_iplt_info *local_iplt;
13971
13972 if (h != NULL)
13973 {
13974 root_plt = &h->plt;
13975 arm_plt = &eh->plt;
13976 }
13977 else
13978 {
13979 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
13980 if (local_iplt == NULL)
13981 return FALSE;
13982 root_plt = &local_iplt->root;
13983 arm_plt = &local_iplt->arm;
13984 }
13985
f6e32f6d
RS		 13986 /* If the symbol is a function that doesn't bind locally,
13987 this relocation will need a PLT entry. */
a8c887dd
NC		 13988 if (root_plt->refcount != -1)
13989 root_plt->refcount += 1;
34e77a92
RS		 13990
13991 if (!call_reloc_p)
13992 arm_plt->noncall_refcount++;
f6e32f6d
RS		 13993
13994 /* It's too early to use htab->use_blx here, so we have to
13995 record possible blx references separately from
13996 relocs that definitely need a thumb stub. */
13997
13998 if (r_type == R_ARM_THM_CALL)
34e77a92 13999 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 14000
14001 if (r_type == R_ARM_THM_JUMP24
14002 || r_type == R_ARM_THM_JUMP19)
34e77a92 14003 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 14004 }
14005
14006 if (may_become_dynamic_p)
14007 {
14008 struct elf_dyn_relocs *p, **head;
14009
14010 /* Create a reloc section in dynobj. */
14011 if (sreloc == NULL)
14012 {
14013 sreloc = _bfd_elf_make_dynamic_reloc_section
14014 (sec, dynobj, 2, abfd, ! htab->use_rel);
14015
14016 if (sreloc == NULL)
14017 return FALSE;
14018
14019 /* BPABI objects never have dynamic relocations mapped. */
14020 if (htab->symbian_p)
14021 {
14022 flagword flags;
14023
14024 flags = bfd_get_section_flags (dynobj, sreloc);
14025 flags &= ~(SEC_LOAD | SEC_ALLOC);
14026 bfd_set_section_flags (dynobj, sreloc, flags);
14027 }
14028 }
14029
14030 /* If this is a global symbol, count the number of
14031 relocations we need for this symbol. */
14032 if (h != NULL)
14033 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
14034 else
14035 {
34e77a92
RS		 14036 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
14037 if (head == NULL)
f6e32f6d 14038 return FALSE;
f6e32f6d
RS		 14039 }
14040
14041 p = *head;
14042 if (p == NULL || p->sec != sec)
14043 {
14044 bfd_size_type amt = sizeof *p;
14045
14046 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
14047 if (p == NULL)
14048 return FALSE;
14049 p->next = *head;
14050 *head = p;
14051 p->sec = sec;
14052 p->count = 0;
14053 p->pc_count = 0;
14054 }
14055
469a3493 14056 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 14057 p->pc_count += 1;
14058 p->count += 1;
14059 }
252b5132 14060 }
f21f3fe0 14061
b34976b6 14062 return TRUE;
252b5132
RH		 14063}
14064
6a5bb875
PB		 14065/* Unwinding tables are not referenced directly. This pass marks them as
14066 required if the corresponding code section is marked. */
14067
14068static bfd_boolean
906e58ca
NC		 14069elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
14070 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 14071{
14072 bfd *sub;
14073 Elf_Internal_Shdr **elf_shdrp;
14074 bfd_boolean again;
14075
7f6ab9f8
AM		 14076 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
14077
6a5bb875
PB		 14078 /* Marking EH data may cause additional code sections to be marked,
14079 requiring multiple passes. */
14080 again = TRUE;
14081 while (again)
14082 {
14083 again = FALSE;
c72f2fb2 14084 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 14085 {
14086 asection *o;
14087
0ffa91dd 14088 if (! is_arm_elf (sub))
6a5bb875
PB		 14089 continue;
14090
14091 elf_shdrp = elf_elfsections (sub);
14092 for (o = sub->sections; o != NULL; o = o->next)
14093 {
14094 Elf_Internal_Shdr *hdr;
0ffa91dd 14095
6a5bb875 14096 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 14097 if (hdr->sh_type == SHT_ARM_EXIDX
14098 && hdr->sh_link
14099 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 14100 && !o->gc_mark
14101 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
14102 {
14103 again = TRUE;
14104 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
14105 return FALSE;
14106 }
14107 }
14108 }
14109 }
14110
14111 return TRUE;
14112}
14113
3c9458e9
NC		 14114/* Treat mapping symbols as special target symbols. */
14115
14116static bfd_boolean
14117elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
14118{
b0796911
PB		 14119 return bfd_is_arm_special_symbol_name (sym->name,
14120 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 14121}
14122
0367ecfb
NC		 14123/* This is a copy of elf_find_function() from elf.c except that
14124 ARM mapping symbols are ignored when looking for function names
14125 and STT_ARM_TFUNC is considered to a function type. */
252b5132 14126
0367ecfb
NC		 14127static bfd_boolean
14128arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 14129 asymbol ** symbols,
fb167eb2 14130 asection * section,
0367ecfb
NC		 14131 bfd_vma offset,
14132 const char ** filename_ptr,
14133 const char ** functionname_ptr)
14134{
14135 const char * filename = NULL;
14136 asymbol * func = NULL;
14137 bfd_vma low_func = 0;
14138 asymbol ** p;
252b5132
RH		 14139
14140 for (p = symbols; *p != NULL; p++)
14141 {
14142 elf_symbol_type *q;
14143
14144 q = (elf_symbol_type *) *p;
14145
252b5132
RH		 14146 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
14147 {
14148 default:
14149 break;
14150 case STT_FILE:
14151 filename = bfd_asymbol_name (&q->symbol);
14152 break;
252b5132
RH		 14153 case STT_FUNC:
14154 case STT_ARM_TFUNC:
9d2da7ca 14155 case STT_NOTYPE:
b0796911 14156 /* Skip mapping symbols. */
0367ecfb 14157 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 14158 && bfd_is_arm_special_symbol_name (q->symbol.name,
14159 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 14160 continue;
14161 /* Fall through. */
6b40fcba 14162 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 14163 && q->symbol.value >= low_func
14164 && q->symbol.value <= offset)
14165 {
14166 func = (asymbol *) q;
14167 low_func = q->symbol.value;
14168 }
14169 break;
14170 }
14171 }
14172
14173 if (func == NULL)
b34976b6 14174 return FALSE;
252b5132 14175
0367ecfb
NC		 14176 if (filename_ptr)
14177 *filename_ptr = filename;
14178 if (functionname_ptr)
14179 *functionname_ptr = bfd_asymbol_name (func);
14180
14181 return TRUE;
906e58ca 14182}
0367ecfb
NC		 14183
14184
14185/* Find the nearest line to a particular section and offset, for error
14186 reporting. This code is a duplicate of the code in elf.c, except
14187 that it uses arm_elf_find_function. */
14188
14189static bfd_boolean
14190elf32_arm_find_nearest_line (bfd * abfd,
0367ecfb 14191 asymbol ** symbols,
fb167eb2 14192 asection * section,
0367ecfb
NC		 14193 bfd_vma offset,
14194 const char ** filename_ptr,
14195 const char ** functionname_ptr,
fb167eb2
AM		 14196 unsigned int * line_ptr,
14197 unsigned int * discriminator_ptr)
0367ecfb
NC		 14198{
14199 bfd_boolean found = FALSE;
14200
fb167eb2 14201 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 14202 filename_ptr, functionname_ptr,
fb167eb2
AM		 14203 line_ptr, discriminator_ptr,
14204 dwarf_debug_sections, 0,
0367ecfb
NC		 14205 & elf_tdata (abfd)->dwarf2_find_line_info))
14206 {
14207 if (!*functionname_ptr)
fb167eb2 14208 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 14209 *filename_ptr ? NULL : filename_ptr,
14210 functionname_ptr);
f21f3fe0 14211
0367ecfb
NC		 14212 return TRUE;
14213 }
14214
fb167eb2
AM		 14215 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
14216 uses DWARF1. */
14217
0367ecfb
NC		 14218 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
14219 & found, filename_ptr,
14220 functionname_ptr, line_ptr,
14221 & elf_tdata (abfd)->line_info))
14222 return FALSE;
14223
14224 if (found && (*functionname_ptr || *line_ptr))
14225 return TRUE;
14226
14227 if (symbols == NULL)
14228 return FALSE;
14229
fb167eb2 14230 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 14231 filename_ptr, functionname_ptr))
14232 return FALSE;
14233
14234 *line_ptr = 0;
b34976b6 14235 return TRUE;
252b5132
RH		 14236}
14237
4ab527b0
FF		 14238static bfd_boolean
14239elf32_arm_find_inliner_info (bfd * abfd,
14240 const char ** filename_ptr,
14241 const char ** functionname_ptr,
14242 unsigned int * line_ptr)
14243{
14244 bfd_boolean found;
14245 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
14246 functionname_ptr, line_ptr,
14247 & elf_tdata (abfd)->dwarf2_find_line_info);
14248 return found;
14249}
14250
252b5132
RH		 14251/* Adjust a symbol defined by a dynamic object and referenced by a
14252 regular object. The current definition is in some section of the
14253 dynamic object, but we're not including those sections. We have to
14254 change the definition to something the rest of the link can
14255 understand. */
14256
b34976b6 14257static bfd_boolean
57e8b36a
NC		 14258elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
14259 struct elf_link_hash_entry * h)
252b5132
RH		 14260{
14261 bfd * dynobj;
14262 asection * s;
b7693d02 14263 struct elf32_arm_link_hash_entry * eh;
67687978 14264 struct elf32_arm_link_hash_table *globals;
252b5132 14265
67687978 14266 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14267 if (globals == NULL)
14268 return FALSE;
14269
252b5132
RH		 14270 dynobj = elf_hash_table (info)->dynobj;
14271
14272 /* Make sure we know what is going on here. */
14273 BFD_ASSERT (dynobj != NULL
f5385ebf 14274 && (h->needs_plt
34e77a92 14275 || h->type == STT_GNU_IFUNC
f6e332e6 14276 || h->u.weakdef != NULL
f5385ebf
AM		 14277 || (h->def_dynamic
14278 && h->ref_regular
14279 && !h->def_regular)));
252b5132 14280
b7693d02
DJ		 14281 eh = (struct elf32_arm_link_hash_entry *) h;
14282
252b5132
RH		 14283 /* If this is a function, put it in the procedure linkage table. We
14284 will fill in the contents of the procedure linkage table later,
14285 when we know the address of the .got section. */
34e77a92 14286 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 14287 {
34e77a92
RS		 14288 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
14289 symbol binds locally. */
5e681ec4 14290 if (h->plt.refcount <= 0
34e77a92
RS		 14291 || (h->type != STT_GNU_IFUNC
14292 && (SYMBOL_CALLS_LOCAL (info, h)
14293 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
14294 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 14295 {
14296 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 14297 file, but the symbol was never referred to by a dynamic
14298 object, or if all references were garbage collected. In
14299 such a case, we don't actually need to build a procedure
14300 linkage table, and we can just do a PC24 reloc instead. */
14301 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 14302 eh->plt.thumb_refcount = 0;
14303 eh->plt.maybe_thumb_refcount = 0;
14304 eh->plt.noncall_refcount = 0;
f5385ebf 14305 h->needs_plt = 0;
252b5132
RH		 14306 }
14307
b34976b6 14308 return TRUE;
252b5132 14309 }
5e681ec4 14310 else
b7693d02
DJ		 14311 {
14312 /* It's possible that we incorrectly decided a .plt reloc was
14313 needed for an R_ARM_PC24 or similar reloc to a non-function sym
14314 in check_relocs. We can't decide accurately between function
14315 and non-function syms in check-relocs; Objects loaded later in
14316 the link may change h->type. So fix it now. */
14317 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 14318 eh->plt.thumb_refcount = 0;
14319 eh->plt.maybe_thumb_refcount = 0;
14320 eh->plt.noncall_refcount = 0;
b7693d02 14321 }
252b5132
RH		 14322
14323 /* If this is a weak symbol, and there is a real definition, the
14324 processor independent code will have arranged for us to see the
14325 real definition first, and we can just use the same value. */
f6e332e6 14326 if (h->u.weakdef != NULL)
252b5132 14327 {
f6e332e6
AM		 14328 BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined
14329 || h->u.weakdef->root.type == bfd_link_hash_defweak);
14330 h->root.u.def.section = h->u.weakdef->root.u.def.section;
14331 h->root.u.def.value = h->u.weakdef->root.u.def.value;
b34976b6 14332 return TRUE;
252b5132
RH		 14333 }
14334
ba93b8ac
DJ		 14335 /* If there are no non-GOT references, we do not need a copy
14336 relocation. */
14337 if (!h->non_got_ref)
14338 return TRUE;
14339
252b5132
RH		 14340 /* This is a reference to a symbol defined by a dynamic object which
14341 is not a function. */
14342
14343 /* If we are creating a shared library, we must presume that the
14344 only references to the symbol are via the global offset table.
14345 For such cases we need not do anything here; the relocations will
67687978
PB		 14346 be handled correctly by relocate_section. Relocatable executables
14347 can reference data in shared objects directly, so we don't need to
14348 do anything here. */
0e1862bb 14349 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 14350 return TRUE;
252b5132
RH		 14351
14352 /* We must allocate the symbol in our .dynbss section, which will
14353 become part of the .bss section of the executable. There will be
14354 an entry for this symbol in the .dynsym section. The dynamic
14355 object will contain position independent code, so all references
14356 from the dynamic object to this symbol will go through the global
14357 offset table. The dynamic linker will use the .dynsym entry to
14358 determine the address it must put in the global offset table, so
14359 both the dynamic object and the regular object will refer to the
14360 same memory location for the variable. */
3d4d4302 14361 s = bfd_get_linker_section (dynobj, ".dynbss");
252b5132
RH		 14362 BFD_ASSERT (s != NULL);
14363
5522f910
NC		 14364 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
14365 linker to copy the initial value out of the dynamic object and into
14366 the runtime process image. We need to remember the offset into the
00a97672 14367 .rel(a).bss section we are going to use. */
5522f910
NC		 14368 if (info->nocopyreloc == 0
14369 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
5522f910 14370 && h->size != 0)
252b5132
RH		 14371 {
14372 asection *srel;
14373
3d4d4302 14374 srel = bfd_get_linker_section (dynobj, RELOC_SECTION (globals, ".bss"));
47beaa6a 14375 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 14376 h->needs_copy = 1;
252b5132
RH		 14377 }
14378
6cabe1ea 14379 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 14380}
14381
5e681ec4
PB		 14382/* Allocate space in .plt, .got and associated reloc sections for
14383 dynamic relocs. */
14384
14385static bfd_boolean
47beaa6a 14386allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 14387{
14388 struct bfd_link_info *info;
14389 struct elf32_arm_link_hash_table *htab;
14390 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 14391 struct elf_dyn_relocs *p;
5e681ec4
PB		 14392
14393 if (h->root.type == bfd_link_hash_indirect)
14394 return TRUE;
14395
e6a6bb22
AM		 14396 eh = (struct elf32_arm_link_hash_entry *) h;
14397
5e681ec4
PB		 14398 info = (struct bfd_link_info *) inf;
14399 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14400 if (htab == NULL)
14401 return FALSE;
5e681ec4 14402
34e77a92 14403 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 14404 && h->plt.refcount > 0)
14405 {
14406 /* Make sure this symbol is output as a dynamic symbol.
14407 Undefined weak syms won't yet be marked as dynamic. */
14408 if (h->dynindx == -1
f5385ebf 14409 && !h->forced_local)
5e681ec4 14410 {
c152c796 14411 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14412 return FALSE;
14413 }
14414
34e77a92
RS		 14415 /* If the call in the PLT entry binds locally, the associated
14416 GOT entry should use an R_ARM_IRELATIVE relocation instead of
14417 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
14418 than the .plt section. */
14419 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
14420 {
14421 eh->is_iplt = 1;
14422 if (eh->plt.noncall_refcount == 0
14423 && SYMBOL_REFERENCES_LOCAL (info, h))
14424 /* All non-call references can be resolved directly.
14425 This means that they can (and in some cases, must)
14426 resolve directly to the run-time target, rather than
14427 to the PLT. That in turns means that any .got entry
14428 would be equal to the .igot.plt entry, so there's
14429 no point having both. */
14430 h->got.refcount = 0;
14431 }
14432
0e1862bb 14433 if (bfd_link_pic (info)
34e77a92 14434 || eh->is_iplt
7359ea65 14435 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 14436 {
34e77a92 14437 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 14438
5e681ec4
PB		 14439 /* If this symbol is not defined in a regular file, and we are
14440 not generating a shared library, then set the symbol to this
14441 location in the .plt. This is required to make function
14442 pointers compare as equal between the normal executable and
14443 the shared library. */
0e1862bb 14444 if (! bfd_link_pic (info)
f5385ebf 14445 && !h->def_regular)
5e681ec4 14446 {
34e77a92 14447 h->root.u.def.section = htab->root.splt;
5e681ec4 14448 h->root.u.def.value = h->plt.offset;
5e681ec4 14449
67d74e43
DJ		 14450 /* Make sure the function is not marked as Thumb, in case
14451 it is the target of an ABS32 relocation, which will
14452 point to the PLT entry. */
39d911fc 14453 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
67d74e43 14454 }
022f8312 14455
00a97672
RS		 14456 /* VxWorks executables have a second set of relocations for
14457 each PLT entry. They go in a separate relocation section,
14458 which is processed by the kernel loader. */
0e1862bb 14459 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 14460 {
14461 /* There is a relocation for the initial PLT entry:
14462 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
14463 if (h->plt.offset == htab->plt_header_size)
47beaa6a 14464 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 14465
14466 /* There are two extra relocations for each subsequent
14467 PLT entry: an R_ARM_32 relocation for the GOT entry,
14468 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 14469 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 14470 }
5e681ec4
PB		 14471 }
14472 else
14473 {
14474 h->plt.offset = (bfd_vma) -1;
f5385ebf 14475 h->needs_plt = 0;
5e681ec4
PB		 14476 }
14477 }
14478 else
14479 {
14480 h->plt.offset = (bfd_vma) -1;
f5385ebf 14481 h->needs_plt = 0;
5e681ec4
PB		 14482 }
14483
0855e32b
NS		 14484 eh = (struct elf32_arm_link_hash_entry *) h;
14485 eh->tlsdesc_got = (bfd_vma) -1;
14486
5e681ec4
PB		 14487 if (h->got.refcount > 0)
14488 {
14489 asection *s;
14490 bfd_boolean dyn;
ba93b8ac
DJ		 14491 int tls_type = elf32_arm_hash_entry (h)->tls_type;
14492 int indx;
5e681ec4
PB		 14493
14494 /* Make sure this symbol is output as a dynamic symbol.
14495 Undefined weak syms won't yet be marked as dynamic. */
14496 if (h->dynindx == -1
f5385ebf 14497 && !h->forced_local)
5e681ec4 14498 {
c152c796 14499 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14500 return FALSE;
14501 }
14502
e5a52504
MM		 14503 if (!htab->symbian_p)
14504 {
362d30a1 14505 s = htab->root.sgot;
e5a52504 14506 h->got.offset = s->size;
ba93b8ac
DJ		 14507
14508 if (tls_type == GOT_UNKNOWN)
14509 abort ();
14510
14511 if (tls_type == GOT_NORMAL)
14512 /* Non-TLS symbols need one GOT slot. */
14513 s->size += 4;
14514 else
14515 {
99059e56
RM		 14516 if (tls_type & GOT_TLS_GDESC)
14517 {
0855e32b 14518 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 14519 eh->tlsdesc_got
0855e32b
NS		 14520 = (htab->root.sgotplt->size
14521 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 14522 htab->root.sgotplt->size += 8;
14523 h->got.offset = (bfd_vma) -2;
34e77a92 14524 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 14525 reloc in the middle of .got.plt. */
99059e56
RM		 14526 htab->num_tls_desc++;
14527 }
0855e32b 14528
ba93b8ac 14529 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 14530 {
14531 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
14532 the symbol is both GD and GDESC, got.offset may
14533 have been overwritten. */
14534 h->got.offset = s->size;
14535 s->size += 8;
14536 }
14537
ba93b8ac
DJ		 14538 if (tls_type & GOT_TLS_IE)
14539 /* R_ARM_TLS_IE32 needs one GOT slot. */
14540 s->size += 4;
14541 }
14542
e5a52504 14543 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 14544
14545 indx = 0;
0e1862bb
L		 14546 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
14547 bfd_link_pic (info),
14548 h)
14549 && (!bfd_link_pic (info)
ba93b8ac
DJ		 14550 || !SYMBOL_REFERENCES_LOCAL (info, h)))
14551 indx = h->dynindx;
14552
14553 if (tls_type != GOT_NORMAL
0e1862bb 14554 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 14555 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
14556 || h->root.type != bfd_link_hash_undefweak))
14557 {
14558 if (tls_type & GOT_TLS_IE)
47beaa6a 14559 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 14560
14561 if (tls_type & GOT_TLS_GD)
47beaa6a 14562 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 14563
b38cadfb 14564 if (tls_type & GOT_TLS_GDESC)
0855e32b 14565 {
47beaa6a 14566 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 14567 /* GDESC needs a trampoline to jump to. */
14568 htab->tls_trampoline = -1;
14569 }
14570
14571 /* Only GD needs it. GDESC just emits one relocation per
14572 2 entries. */
b38cadfb 14573 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 14574 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 14575 }
6f820c85 14576 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 14577 {
14578 if (htab->root.dynamic_sections_created)
14579 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
14580 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
14581 }
34e77a92
RS		 14582 else if (h->type == STT_GNU_IFUNC
14583 && eh->plt.noncall_refcount == 0)
14584 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
14585 they all resolve dynamically instead. Reserve room for the
14586 GOT entry's R_ARM_IRELATIVE relocation. */
14587 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 14588 else if (bfd_link_pic (info)
14589 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
14590 || h->root.type != bfd_link_hash_undefweak))
b436d854 14591 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 14592 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 14593 }
5e681ec4
PB		 14594 }
14595 else
14596 h->got.offset = (bfd_vma) -1;
14597
a4fd1a8e
PB		 14598 /* Allocate stubs for exported Thumb functions on v4t. */
14599 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 14600 && h->def_regular
39d911fc 14601 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 14602 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
14603 {
14604 struct elf_link_hash_entry * th;
14605 struct bfd_link_hash_entry * bh;
14606 struct elf_link_hash_entry * myh;
14607 char name[1024];
14608 asection *s;
14609 bh = NULL;
14610 /* Create a new symbol to regist the real location of the function. */
14611 s = h->root.u.def.section;
906e58ca 14612 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 14613 _bfd_generic_link_add_one_symbol (info, s->owner,
14614 name, BSF_GLOBAL, s,
14615 h->root.u.def.value,
14616 NULL, TRUE, FALSE, &bh);
14617
14618 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 14619 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 14620 myh->forced_local = 1;
39d911fc 14621 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
a4fd1a8e
PB		 14622 eh->export_glue = myh;
14623 th = record_arm_to_thumb_glue (info, h);
14624 /* Point the symbol at the stub. */
14625 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
39d911fc 14626 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
a4fd1a8e
PB		 14627 h->root.u.def.section = th->root.u.def.section;
14628 h->root.u.def.value = th->root.u.def.value & ~1;
14629 }
14630
0bdcacaf 14631 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 14632 return TRUE;
14633
14634 /* In the shared -Bsymbolic case, discard space allocated for
14635 dynamic pc-relative relocs against symbols which turn out to be
14636 defined in regular objects. For the normal shared case, discard
14637 space for pc-relative relocs that have become local due to symbol
14638 visibility changes. */
14639
0e1862bb 14640 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 14641 {
469a3493
RM		 14642 /* Relocs that use pc_count are PC-relative forms, which will appear
14643 on something like ".long foo - ." or "movw REG, foo - .". We want
14644 calls to protected symbols to resolve directly to the function
14645 rather than going via the plt. If people want function pointer
14646 comparisons to work as expected then they should avoid writing
14647 assembly like ".long foo - .". */
ba93b8ac
DJ		 14648 if (SYMBOL_CALLS_LOCAL (info, h))
14649 {
0bdcacaf 14650 struct elf_dyn_relocs **pp;
ba93b8ac 14651
0bdcacaf 14652 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 14653 {
14654 p->count -= p->pc_count;
14655 p->pc_count = 0;
14656 if (p->count == 0)
14657 *pp = p->next;
14658 else
14659 pp = &p->next;
14660 }
14661 }
14662
4dfe6ac6 14663 if (htab->vxworks_p)
3348747a 14664 {
0bdcacaf 14665 struct elf_dyn_relocs **pp;
3348747a 14666
0bdcacaf 14667 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 14668 {
0bdcacaf 14669 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 14670 *pp = p->next;
14671 else
14672 pp = &p->next;
14673 }
14674 }
14675
ba93b8ac 14676 /* Also discard relocs on undefined weak syms with non-default
99059e56 14677 visibility. */
0bdcacaf 14678 if (eh->dyn_relocs != NULL
5e681ec4 14679 && h->root.type == bfd_link_hash_undefweak)
22d606e9
AM		 14680 {
14681 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT)
0bdcacaf 14682 eh->dyn_relocs = NULL;
22d606e9
AM		 14683
14684 /* Make sure undefined weak symbols are output as a dynamic
14685 symbol in PIEs. */
14686 else if (h->dynindx == -1
14687 && !h->forced_local)
14688 {
14689 if (! bfd_elf_link_record_dynamic_symbol (info, h))
14690 return FALSE;
14691 }
14692 }
14693
67687978
PB		 14694 else if (htab->root.is_relocatable_executable && h->dynindx == -1
14695 && h->root.type == bfd_link_hash_new)
14696 {
14697 /* Output absolute symbols so that we can create relocations
14698 against them. For normal symbols we output a relocation
14699 against the section that contains them. */
14700 if (! bfd_elf_link_record_dynamic_symbol (info, h))
14701 return FALSE;
14702 }
14703
5e681ec4
PB		 14704 }
14705 else
14706 {
14707 /* For the non-shared case, discard space for relocs against
14708 symbols which turn out to need copy relocs or are not
14709 dynamic. */
14710
f5385ebf
AM		 14711 if (!h->non_got_ref
14712 && ((h->def_dynamic
14713 && !h->def_regular)
5e681ec4
PB		 14714 || (htab->root.dynamic_sections_created
14715 && (h->root.type == bfd_link_hash_undefweak
14716 || h->root.type == bfd_link_hash_undefined))))
14717 {
14718 /* Make sure this symbol is output as a dynamic symbol.
14719 Undefined weak syms won't yet be marked as dynamic. */
14720 if (h->dynindx == -1
f5385ebf 14721 && !h->forced_local)
5e681ec4 14722 {
c152c796 14723 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14724 return FALSE;
14725 }
14726
14727 /* If that succeeded, we know we'll be keeping all the
14728 relocs. */
14729 if (h->dynindx != -1)
14730 goto keep;
14731 }
14732
0bdcacaf 14733 eh->dyn_relocs = NULL;
5e681ec4
PB		 14734
14735 keep: ;
14736 }
14737
14738 /* Finally, allocate space. */
0bdcacaf 14739 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 14740 {
0bdcacaf 14741 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 14742 if (h->type == STT_GNU_IFUNC
14743 && eh->plt.noncall_refcount == 0
14744 && SYMBOL_REFERENCES_LOCAL (info, h))
14745 elf32_arm_allocate_irelocs (info, sreloc, p->count);
14746 else
14747 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 14748 }
14749
14750 return TRUE;
14751}
14752
08d1f311
DJ		 14753/* Find any dynamic relocs that apply to read-only sections. */
14754
14755static bfd_boolean
8029a119 14756elf32_arm_readonly_dynrelocs (struct elf_link_hash_entry * h, void * inf)
08d1f311 14757{
8029a119 14758 struct elf32_arm_link_hash_entry * eh;
0bdcacaf 14759 struct elf_dyn_relocs * p;
08d1f311 14760
08d1f311 14761 eh = (struct elf32_arm_link_hash_entry *) h;
0bdcacaf 14762 for (p = eh->dyn_relocs; p != NULL; p = p->next)
08d1f311 14763 {
0bdcacaf 14764 asection *s = p->sec;
08d1f311
DJ		 14765
14766 if (s != NULL && (s->flags & SEC_READONLY) != 0)
14767 {
14768 struct bfd_link_info *info = (struct bfd_link_info *) inf;
14769
14770 info->flags |= DF_TEXTREL;
14771
14772 /* Not an error, just cut short the traversal. */
14773 return FALSE;
14774 }
14775 }
14776 return TRUE;
14777}
14778
d504ffc8
DJ		 14779void
14780bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
14781 int byteswap_code)
14782{
14783 struct elf32_arm_link_hash_table *globals;
14784
14785 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14786 if (globals == NULL)
14787 return;
14788
d504ffc8
DJ		 14789 globals->byteswap_code = byteswap_code;
14790}
14791
252b5132
RH		 14792/* Set the sizes of the dynamic sections. */
14793
b34976b6 14794static bfd_boolean
57e8b36a
NC		 14795elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
14796 struct bfd_link_info * info)
252b5132
RH		 14797{
14798 bfd * dynobj;
14799 asection * s;
b34976b6
AM		 14800 bfd_boolean plt;
14801 bfd_boolean relocs;
5e681ec4
PB		 14802 bfd *ibfd;
14803 struct elf32_arm_link_hash_table *htab;
252b5132 14804
5e681ec4 14805 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14806 if (htab == NULL)
14807 return FALSE;
14808
252b5132
RH		 14809 dynobj = elf_hash_table (info)->dynobj;
14810 BFD_ASSERT (dynobj != NULL);
39b41c9c 14811 check_use_blx (htab);
252b5132
RH		 14812
14813 if (elf_hash_table (info)->dynamic_sections_created)
14814 {
14815 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 14816 if (bfd_link_executable (info) && !info->nointerp)
252b5132 14817 {
3d4d4302 14818 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 14819 BFD_ASSERT (s != NULL);
eea6121a 14820 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 14821 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
14822 }
14823 }
5e681ec4
PB		 14824
14825 /* Set up .got offsets for local syms, and space for local dynamic
14826 relocs. */
c72f2fb2 14827 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 14828 {
5e681ec4
PB		 14829 bfd_signed_vma *local_got;
14830 bfd_signed_vma *end_local_got;
34e77a92 14831 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 14832 char *local_tls_type;
0855e32b 14833 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 14834 bfd_size_type locsymcount;
14835 Elf_Internal_Shdr *symtab_hdr;
14836 asection *srel;
4dfe6ac6 14837 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 14838 unsigned int symndx;
5e681ec4 14839
0ffa91dd 14840 if (! is_arm_elf (ibfd))
5e681ec4
PB		 14841 continue;
14842
14843 for (s = ibfd->sections; s != NULL; s = s->next)
14844 {
0bdcacaf 14845 struct elf_dyn_relocs *p;
5e681ec4 14846
0bdcacaf 14847 for (p = (struct elf_dyn_relocs *)
99059e56 14848 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 14849 {
0bdcacaf
RS		 14850 if (!bfd_is_abs_section (p->sec)
14851 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 14852 {
14853 /* Input section has been discarded, either because
14854 it is a copy of a linkonce section or due to
14855 linker script /DISCARD/, so we'll be discarding
14856 the relocs too. */
14857 }
3348747a 14858 else if (is_vxworks
0bdcacaf 14859 && strcmp (p->sec->output_section->name,
3348747a
NS		 14860 ".tls_vars") == 0)
14861 {
14862 /* Relocations in vxworks .tls_vars sections are
14863 handled specially by the loader. */
14864 }
5e681ec4
PB		 14865 else if (p->count != 0)
14866 {
0bdcacaf 14867 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 14868 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 14869 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 14870 info->flags |= DF_TEXTREL;
14871 }
14872 }
14873 }
14874
14875 local_got = elf_local_got_refcounts (ibfd);
14876 if (!local_got)
14877 continue;
14878
0ffa91dd 14879 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 14880 locsymcount = symtab_hdr->sh_info;
14881 end_local_got = local_got + locsymcount;
34e77a92 14882 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 14883 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 14884 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 14885 symndx = 0;
362d30a1
RS		 14886 s = htab->root.sgot;
14887 srel = htab->root.srelgot;
0855e32b 14888 for (; local_got < end_local_got;
34e77a92
RS		 14889 ++local_got, ++local_iplt_ptr, ++local_tls_type,
14890 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 14891 {
0855e32b 14892 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 14893 local_iplt = *local_iplt_ptr;
14894 if (local_iplt != NULL)
14895 {
14896 struct elf_dyn_relocs *p;
14897
14898 if (local_iplt->root.refcount > 0)
14899 {
14900 elf32_arm_allocate_plt_entry (info, TRUE,
14901 &local_iplt->root,
14902 &local_iplt->arm);
14903 if (local_iplt->arm.noncall_refcount == 0)
14904 /* All references to the PLT are calls, so all
14905 non-call references can resolve directly to the
14906 run-time target. This means that the .got entry
14907 would be the same as the .igot.plt entry, so there's
14908 no point creating both. */
14909 *local_got = 0;
14910 }
14911 else
14912 {
14913 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
14914 local_iplt->root.offset = (bfd_vma) -1;
14915 }
14916
14917 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
14918 {
14919 asection *psrel;
14920
14921 psrel = elf_section_data (p->sec)->sreloc;
14922 if (local_iplt->arm.noncall_refcount == 0)
14923 elf32_arm_allocate_irelocs (info, psrel, p->count);
14924 else
14925 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
14926 }
14927 }
5e681ec4
PB		 14928 if (*local_got > 0)
14929 {
34e77a92
RS		 14930 Elf_Internal_Sym *isym;
14931
eea6121a 14932 *local_got = s->size;
ba93b8ac
DJ		 14933 if (*local_tls_type & GOT_TLS_GD)
14934 /* TLS_GD relocs need an 8-byte structure in the GOT. */
14935 s->size += 8;
0855e32b
NS		 14936 if (*local_tls_type & GOT_TLS_GDESC)
14937 {
14938 *local_tlsdesc_gotent = htab->root.sgotplt->size
14939 - elf32_arm_compute_jump_table_size (htab);
14940 htab->root.sgotplt->size += 8;
14941 *local_got = (bfd_vma) -2;
34e77a92 14942 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 14943 reloc in the middle of .got.plt. */
99059e56 14944 htab->num_tls_desc++;
0855e32b 14945 }
ba93b8ac
DJ		 14946 if (*local_tls_type & GOT_TLS_IE)
14947 s->size += 4;
ba93b8ac 14948
0855e32b
NS		 14949 if (*local_tls_type & GOT_NORMAL)
14950 {
14951 /* If the symbol is both GD and GDESC, *local_got
14952 may have been overwritten. */
14953 *local_got = s->size;
14954 s->size += 4;
14955 }
14956
34e77a92
RS		 14957 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
14958 if (isym == NULL)
14959 return FALSE;
14960
14961 /* If all references to an STT_GNU_IFUNC PLT are calls,
14962 then all non-call references, including this GOT entry,
14963 resolve directly to the run-time target. */
14964 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
14965 && (local_iplt == NULL
14966 || local_iplt->arm.noncall_refcount == 0))
14967 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 14968 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 14969 {
0e1862bb 14970 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 14971 || *local_tls_type & GOT_TLS_GD)
14972 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 14973
0e1862bb 14974 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 14975 {
14976 elf32_arm_allocate_dynrelocs (info,
14977 htab->root.srelplt, 1);
14978 htab->tls_trampoline = -1;
14979 }
0855e32b 14980 }
5e681ec4
PB		 14981 }
14982 else
14983 *local_got = (bfd_vma) -1;
14984 }
252b5132
RH		 14985 }
14986
ba93b8ac
DJ		 14987 if (htab->tls_ldm_got.refcount > 0)
14988 {
14989 /* Allocate two GOT entries and one dynamic relocation (if necessary)
14990 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 14991 htab->tls_ldm_got.offset = htab->root.sgot->size;
14992 htab->root.sgot->size += 8;
0e1862bb 14993 if (bfd_link_pic (info))
47beaa6a 14994 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 14995 }
14996 else
14997 htab->tls_ldm_got.offset = -1;
14998
5e681ec4
PB		 14999 /* Allocate global sym .plt and .got entries, and space for global
15000 sym dynamic relocs. */
47beaa6a 15001 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 15002
d504ffc8 15003 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 15004 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 15005 {
0ffa91dd 15006 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 15007 continue;
15008
c7b8f16e
JB		 15009 /* Initialise mapping tables for code/data. */
15010 bfd_elf32_arm_init_maps (ibfd);
906e58ca 15011
c7b8f16e 15012 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 15013 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
15014 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
99059e56
RM		 15015 /* xgettext:c-format */
15016 _bfd_error_handler (_("Errors encountered processing file %s"),
c7b8f16e
JB		 15017 ibfd->filename);
15018 }
d504ffc8 15019
3e6b1042
DJ		 15020 /* Allocate space for the glue sections now that we've sized them. */
15021 bfd_elf32_arm_allocate_interworking_sections (info);
15022
0855e32b
NS		 15023 /* For every jump slot reserved in the sgotplt, reloc_count is
15024 incremented. However, when we reserve space for TLS descriptors,
15025 it's not incremented, so in order to compute the space reserved
15026 for them, it suffices to multiply the reloc count by the jump
15027 slot size. */
15028 if (htab->root.srelplt)
15029 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
15030
15031 if (htab->tls_trampoline)
15032 {
15033 if (htab->root.splt->size == 0)
15034 htab->root.splt->size += htab->plt_header_size;
b38cadfb 15035
0855e32b
NS		 15036 htab->tls_trampoline = htab->root.splt->size;
15037 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 15038
0855e32b 15039 /* If we're not using lazy TLS relocations, don't generate the
99059e56 15040 PLT and GOT entries they require. */
0855e32b
NS		 15041 if (!(info->flags & DF_BIND_NOW))
15042 {
15043 htab->dt_tlsdesc_got = htab->root.sgot->size;
15044 htab->root.sgot->size += 4;
15045
15046 htab->dt_tlsdesc_plt = htab->root.splt->size;
15047 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
15048 }
15049 }
15050
252b5132
RH		 15051 /* The check_relocs and adjust_dynamic_symbol entry points have
15052 determined the sizes of the various dynamic sections. Allocate
15053 memory for them. */
b34976b6
AM		 15054 plt = FALSE;
15055 relocs = FALSE;
252b5132
RH		 15056 for (s = dynobj->sections; s != NULL; s = s->next)
15057 {
15058 const char * name;
252b5132
RH		 15059
15060 if ((s->flags & SEC_LINKER_CREATED) == 0)
15061 continue;
15062
15063 /* It's OK to base decisions on the section name, because none
15064 of the dynobj section names depend upon the input files. */
15065 name = bfd_get_section_name (dynobj, s);
15066
34e77a92 15067 if (s == htab->root.splt)
252b5132 15068 {
c456f082
AM		 15069 /* Remember whether there is a PLT. */
15070 plt = s->size != 0;
252b5132 15071 }
0112cd26 15072 else if (CONST_STRNEQ (name, ".rel"))
252b5132 15073 {
c456f082 15074 if (s->size != 0)
252b5132 15075 {
252b5132 15076 /* Remember whether there are any reloc sections other
00a97672 15077 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 15078 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 15079 relocs = TRUE;
252b5132
RH		 15080
15081 /* We use the reloc_count field as a counter if we need
15082 to copy relocs into the output file. */
15083 s->reloc_count = 0;
15084 }
15085 }
34e77a92
RS		 15086 else if (s != htab->root.sgot
15087 && s != htab->root.sgotplt
15088 && s != htab->root.iplt
15089 && s != htab->root.igotplt
15090 && s != htab->sdynbss)
252b5132
RH		 15091 {
15092 /* It's not one of our sections, so don't allocate space. */
15093 continue;
15094 }
15095
c456f082 15096 if (s->size == 0)
252b5132 15097 {
c456f082 15098 /* If we don't need this section, strip it from the
00a97672
RS		 15099 output file. This is mostly to handle .rel(a).bss and
15100 .rel(a).plt. We must create both sections in
c456f082
AM		 15101 create_dynamic_sections, because they must be created
15102 before the linker maps input sections to output
15103 sections. The linker does that before
15104 adjust_dynamic_symbol is called, and it is that
15105 function which decides whether anything needs to go
15106 into these sections. */
8423293d 15107 s->flags |= SEC_EXCLUDE;
252b5132
RH		 15108 continue;
15109 }
15110
c456f082
AM		 15111 if ((s->flags & SEC_HAS_CONTENTS) == 0)
15112 continue;
15113
252b5132 15114 /* Allocate memory for the section contents. */
21d799b5 15115 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 15116 if (s->contents == NULL)
b34976b6 15117 return FALSE;
252b5132
RH		 15118 }
15119
15120 if (elf_hash_table (info)->dynamic_sections_created)
15121 {
15122 /* Add some entries to the .dynamic section. We fill in the
15123 values later, in elf32_arm_finish_dynamic_sections, but we
15124 must add the entries now so that we get the correct size for
15125 the .dynamic section. The DT_DEBUG entry is filled in by the
15126 dynamic linker and used by the debugger. */
dc810e39 15127#define add_dynamic_entry(TAG, VAL) \
5a580b3a 15128 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 15129
0e1862bb 15130 if (bfd_link_executable (info))
252b5132 15131 {
dc810e39 15132 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 15133 return FALSE;
252b5132
RH		 15134 }
15135
15136 if (plt)
15137 {
dc810e39
AM		 15138 if ( !add_dynamic_entry (DT_PLTGOT, 0)
15139 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 15140 || !add_dynamic_entry (DT_PLTREL,
15141 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 15142 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 15143 return FALSE;
0855e32b
NS		 15144
15145 if (htab->dt_tlsdesc_plt &&
b38cadfb 15146 (!add_dynamic_entry (DT_TLSDESC_PLT,0)
0855e32b 15147 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 15148 return FALSE;
252b5132
RH		 15149 }
15150
15151 if (relocs)
15152 {
00a97672
RS		 15153 if (htab->use_rel)
15154 {
15155 if (!add_dynamic_entry (DT_REL, 0)
15156 || !add_dynamic_entry (DT_RELSZ, 0)
15157 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
15158 return FALSE;
15159 }
15160 else
15161 {
15162 if (!add_dynamic_entry (DT_RELA, 0)
15163 || !add_dynamic_entry (DT_RELASZ, 0)
15164 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
15165 return FALSE;
15166 }
252b5132
RH		 15167 }
15168
08d1f311
DJ		 15169 /* If any dynamic relocs apply to a read-only section,
15170 then we need a DT_TEXTREL entry. */
15171 if ((info->flags & DF_TEXTREL) == 0)
8029a119
NC		 15172 elf_link_hash_traverse (& htab->root, elf32_arm_readonly_dynrelocs,
15173 info);
08d1f311 15174
99e4ae17 15175 if ((info->flags & DF_TEXTREL) != 0)
252b5132 15176 {
dc810e39 15177 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 15178 return FALSE;
252b5132 15179 }
7a2b07ff
NS		 15180 if (htab->vxworks_p
15181 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
15182 return FALSE;
252b5132 15183 }
8532796c 15184#undef add_dynamic_entry
252b5132 15185
b34976b6 15186 return TRUE;
252b5132
RH		 15187}
15188
0855e32b
NS		 15189/* Size sections even though they're not dynamic. We use it to setup
15190 _TLS_MODULE_BASE_, if needed. */
15191
15192static bfd_boolean
15193elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 15194 struct bfd_link_info *info)
0855e32b
NS		 15195{
15196 asection *tls_sec;
15197
0e1862bb 15198 if (bfd_link_relocatable (info))
0855e32b
NS		 15199 return TRUE;
15200
15201 tls_sec = elf_hash_table (info)->tls_sec;
15202
15203 if (tls_sec)
15204 {
15205 struct elf_link_hash_entry *tlsbase;
15206
15207 tlsbase = elf_link_hash_lookup
15208 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
15209
15210 if (tlsbase)
99059e56
RM		 15211 {
15212 struct bfd_link_hash_entry *bh = NULL;
0855e32b 15213 const struct elf_backend_data *bed
99059e56 15214 = get_elf_backend_data (output_bfd);
0855e32b 15215
99059e56 15216 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 15217 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
15218 tls_sec, 0, NULL, FALSE,
15219 bed->collect, &bh)))
15220 return FALSE;
b38cadfb 15221
99059e56
RM		 15222 tlsbase->type = STT_TLS;
15223 tlsbase = (struct elf_link_hash_entry *)bh;
15224 tlsbase->def_regular = 1;
15225 tlsbase->other = STV_HIDDEN;
15226 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 15227 }
15228 }
15229 return TRUE;
15230}
15231
252b5132
RH		 15232/* Finish up dynamic symbol handling. We set the contents of various
15233 dynamic sections here. */
15234
b34976b6 15235static bfd_boolean
906e58ca
NC		 15236elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
15237 struct bfd_link_info * info,
15238 struct elf_link_hash_entry * h,
15239 Elf_Internal_Sym * sym)
252b5132 15240{
e5a52504 15241 struct elf32_arm_link_hash_table *htab;
b7693d02 15242 struct elf32_arm_link_hash_entry *eh;
252b5132 15243
e5a52504 15244 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15245 if (htab == NULL)
15246 return FALSE;
15247
b7693d02 15248 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 15249
15250 if (h->plt.offset != (bfd_vma) -1)
15251 {
34e77a92 15252 if (!eh->is_iplt)
e5a52504 15253 {
34e77a92 15254 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 15255 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
15256 h->dynindx, 0))
15257 return FALSE;
e5a52504 15258 }
57e8b36a 15259
f5385ebf 15260 if (!h->def_regular)
252b5132
RH		 15261 {
15262 /* Mark the symbol as undefined, rather than as defined in
3a635617 15263 the .plt section. */
252b5132 15264 sym->st_shndx = SHN_UNDEF;
3a635617 15265 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 15266 Otherwise, the PLT entry would provide a definition for
15267 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 15268 and so the symbol would never be NULL. Leave the value if
15269 there were any relocations where pointer equality matters
15270 (this is a clue for the dynamic linker, to make function
15271 pointer comparisons work between an application and shared
15272 library). */
97323ad1 15273 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 15274 sym->st_value = 0;
252b5132 15275 }
34e77a92
RS		 15276 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
15277 {
15278 /* At least one non-call relocation references this .iplt entry,
15279 so the .iplt entry is the function's canonical address. */
15280 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
39d911fc 15281 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
34e77a92
RS		 15282 sym->st_shndx = (_bfd_elf_section_from_bfd_section
15283 (output_bfd, htab->root.iplt->output_section));
15284 sym->st_value = (h->plt.offset
15285 + htab->root.iplt->output_section->vma
15286 + htab->root.iplt->output_offset);
15287 }
252b5132
RH		 15288 }
15289
f5385ebf 15290 if (h->needs_copy)
252b5132
RH		 15291 {
15292 asection * s;
947216bf 15293 Elf_Internal_Rela rel;
252b5132
RH		 15294
15295 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 15296 BFD_ASSERT (h->dynindx != -1
15297 && (h->root.type == bfd_link_hash_defined
15298 || h->root.type == bfd_link_hash_defweak));
15299
362d30a1 15300 s = htab->srelbss;
252b5132
RH		 15301 BFD_ASSERT (s != NULL);
15302
00a97672 15303 rel.r_addend = 0;
252b5132
RH		 15304 rel.r_offset = (h->root.u.def.value
15305 + h->root.u.def.section->output_section->vma
15306 + h->root.u.def.section->output_offset);
15307 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
47beaa6a 15308 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 15309 }
15310
00a97672
RS		 15311 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
15312 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
15313 to the ".got" section. */
9637f6ef 15314 if (h == htab->root.hdynamic
00a97672 15315 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 15316 sym->st_shndx = SHN_ABS;
15317
b34976b6 15318 return TRUE;
252b5132
RH		 15319}
15320
0855e32b
NS		 15321static void
15322arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
15323 void *contents,
15324 const unsigned long *template, unsigned count)
15325{
15326 unsigned ix;
b38cadfb 15327
0855e32b
NS		 15328 for (ix = 0; ix != count; ix++)
15329 {
15330 unsigned long insn = template[ix];
15331
15332 /* Emit mov pc,rx if bx is not permitted. */
15333 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
15334 insn = (insn & 0xf000000f) | 0x01a0f000;
15335 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
15336 }
15337}
15338
99059e56
RM		 15339/* Install the special first PLT entry for elf32-arm-nacl. Unlike
15340 other variants, NaCl needs this entry in a static executable's
15341 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
15342 zero. For .iplt really only the last bundle is useful, and .iplt
15343 could have a shorter first entry, with each individual PLT entry's
15344 relative branch calculated differently so it targets the last
15345 bundle instead of the instruction before it (labelled .Lplt_tail
15346 above). But it's simpler to keep the size and layout of PLT0
15347 consistent with the dynamic case, at the cost of some dead code at
15348 the start of .iplt and the one dead store to the stack at the start
15349 of .Lplt_tail. */
15350static void
15351arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
15352 asection *plt, bfd_vma got_displacement)
15353{
15354 unsigned int i;
15355
15356 put_arm_insn (htab, output_bfd,
15357 elf32_arm_nacl_plt0_entry[0]
15358 | arm_movw_immediate (got_displacement),
15359 plt->contents + 0);
15360 put_arm_insn (htab, output_bfd,
15361 elf32_arm_nacl_plt0_entry[1]
15362 | arm_movt_immediate (got_displacement),
15363 plt->contents + 4);
15364
15365 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
15366 put_arm_insn (htab, output_bfd,
15367 elf32_arm_nacl_plt0_entry[i],
15368 plt->contents + (i * 4));
15369}
15370
252b5132
RH		 15371/* Finish up the dynamic sections. */
15372
b34976b6 15373static bfd_boolean
57e8b36a 15374elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 15375{
15376 bfd * dynobj;
15377 asection * sgot;
15378 asection * sdyn;
4dfe6ac6
NC		 15379 struct elf32_arm_link_hash_table *htab;
15380
15381 htab = elf32_arm_hash_table (info);
15382 if (htab == NULL)
15383 return FALSE;
252b5132
RH		 15384
15385 dynobj = elf_hash_table (info)->dynobj;
15386
362d30a1 15387 sgot = htab->root.sgotplt;
894891db
NC		 15388 /* A broken linker script might have discarded the dynamic sections.
15389 Catch this here so that we do not seg-fault later on. */
15390 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
15391 return FALSE;
3d4d4302 15392 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 15393
15394 if (elf_hash_table (info)->dynamic_sections_created)
15395 {
15396 asection *splt;
15397 Elf32_External_Dyn *dyncon, *dynconend;
15398
362d30a1 15399 splt = htab->root.splt;
24a1ba0f 15400 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 15401 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 15402
15403 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 15404 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 15405
252b5132
RH		 15406 for (; dyncon < dynconend; dyncon++)
15407 {
15408 Elf_Internal_Dyn dyn;
15409 const char * name;
15410 asection * s;
15411
15412 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
15413
15414 switch (dyn.d_tag)
15415 {
229fcec5
MM		 15416 unsigned int type;
15417
252b5132 15418 default:
7a2b07ff
NS		 15419 if (htab->vxworks_p
15420 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
15421 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 15422 break;
15423
229fcec5
MM		 15424 case DT_HASH:
15425 name = ".hash";
15426 goto get_vma_if_bpabi;
15427 case DT_STRTAB:
15428 name = ".dynstr";
15429 goto get_vma_if_bpabi;
15430 case DT_SYMTAB:
15431 name = ".dynsym";
15432 goto get_vma_if_bpabi;
c0042f5d
MM		 15433 case DT_VERSYM:
15434 name = ".gnu.version";
15435 goto get_vma_if_bpabi;
15436 case DT_VERDEF:
15437 name = ".gnu.version_d";
15438 goto get_vma_if_bpabi;
15439 case DT_VERNEED:
15440 name = ".gnu.version_r";
15441 goto get_vma_if_bpabi;
15442
252b5132 15443 case DT_PLTGOT:
4ade44b7 15444 name = htab->symbian_p ? ".got" : ".got.plt";
252b5132
RH		 15445 goto get_vma;
15446 case DT_JMPREL:
00a97672 15447 name = RELOC_SECTION (htab, ".plt");
252b5132 15448 get_vma:
4ade44b7 15449 s = bfd_get_linker_section (dynobj, name);
05456594
NC		 15450 if (s == NULL)
15451 {
05456594 15452 (*_bfd_error_handler)
4ade44b7 15453 (_("could not find section %s"), name);
05456594
NC		 15454 bfd_set_error (bfd_error_invalid_operation);
15455 return FALSE;
15456 }
229fcec5 15457 if (!htab->symbian_p)
4ade44b7 15458 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
229fcec5
MM		 15459 else
15460 /* In the BPABI, tags in the PT_DYNAMIC section point
15461 at the file offset, not the memory address, for the
15462 convenience of the post linker. */
4ade44b7 15463 dyn.d_un.d_ptr = s->output_section->filepos + s->output_offset;
252b5132
RH		 15464 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15465 break;
15466
229fcec5
MM		 15467 get_vma_if_bpabi:
15468 if (htab->symbian_p)
15469 goto get_vma;
15470 break;
15471
252b5132 15472 case DT_PLTRELSZ:
362d30a1 15473 s = htab->root.srelplt;
252b5132 15474 BFD_ASSERT (s != NULL);
eea6121a 15475 dyn.d_un.d_val = s->size;
252b5132
RH		 15476 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15477 break;
906e58ca 15478
252b5132 15479 case DT_RELSZ:
00a97672 15480 case DT_RELASZ:
229fcec5
MM		 15481 if (!htab->symbian_p)
15482 {
15483 /* My reading of the SVR4 ABI indicates that the
15484 procedure linkage table relocs (DT_JMPREL) should be
15485 included in the overall relocs (DT_REL). This is
15486 what Solaris does. However, UnixWare can not handle
15487 that case. Therefore, we override the DT_RELSZ entry
15488 here to make it not include the JMPREL relocs. Since
00a97672 15489 the linker script arranges for .rel(a).plt to follow all
229fcec5
MM		 15490 other relocation sections, we don't have to worry
15491 about changing the DT_REL entry. */
362d30a1 15492 s = htab->root.srelplt;
229fcec5
MM		 15493 if (s != NULL)
15494 dyn.d_un.d_val -= s->size;
15495 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15496 break;
15497 }
8029a119 15498 /* Fall through. */
229fcec5
MM		 15499
15500 case DT_REL:
15501 case DT_RELA:
229fcec5
MM		 15502 /* In the BPABI, the DT_REL tag must point at the file
15503 offset, not the VMA, of the first relocation
15504 section. So, we use code similar to that in
15505 elflink.c, but do not check for SHF_ALLOC on the
15506 relcoation section, since relocations sections are
15507 never allocated under the BPABI. The comments above
15508 about Unixware notwithstanding, we include all of the
15509 relocations here. */
15510 if (htab->symbian_p)
15511 {
15512 unsigned int i;
15513 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
15514 ? SHT_REL : SHT_RELA);
15515 dyn.d_un.d_val = 0;
15516 for (i = 1; i < elf_numsections (output_bfd); i++)
15517 {
906e58ca 15518 Elf_Internal_Shdr *hdr
229fcec5
MM		 15519 = elf_elfsections (output_bfd)[i];
15520 if (hdr->sh_type == type)
15521 {
906e58ca 15522 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 15523 || dyn.d_tag == DT_RELASZ)
15524 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 15525 else if ((ufile_ptr) hdr->sh_offset
15526 <= dyn.d_un.d_val - 1)
229fcec5
MM		 15527 dyn.d_un.d_val = hdr->sh_offset;
15528 }
15529 }
15530 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15531 }
252b5132 15532 break;
88f7bcd5 15533
0855e32b 15534 case DT_TLSDESC_PLT:
99059e56 15535 s = htab->root.splt;
0855e32b
NS		 15536 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
15537 + htab->dt_tlsdesc_plt);
15538 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15539 break;
15540
15541 case DT_TLSDESC_GOT:
99059e56 15542 s = htab->root.sgot;
0855e32b 15543 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 15544 + htab->dt_tlsdesc_got);
0855e32b
NS		 15545 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15546 break;
15547
88f7bcd5
NC		 15548 /* Set the bottom bit of DT_INIT/FINI if the
15549 corresponding function is Thumb. */
15550 case DT_INIT:
15551 name = info->init_function;
15552 goto get_sym;
15553 case DT_FINI:
15554 name = info->fini_function;
15555 get_sym:
15556 /* If it wasn't set by elf_bfd_final_link
4cc11e76 15557 then there is nothing to adjust. */
88f7bcd5
NC		 15558 if (dyn.d_un.d_val != 0)
15559 {
15560 struct elf_link_hash_entry * eh;
15561
15562 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 15563 FALSE, FALSE, TRUE);
39d911fc
TP		 15564 if (eh != NULL
15565 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
15566 == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 15567 {
15568 dyn.d_un.d_val |= 1;
b34976b6 15569 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 15570 }
15571 }
15572 break;
252b5132
RH		 15573 }
15574 }
15575
24a1ba0f 15576 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 15577 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 15578 {
00a97672
RS		 15579 const bfd_vma *plt0_entry;
15580 bfd_vma got_address, plt_address, got_displacement;
15581
15582 /* Calculate the addresses of the GOT and PLT. */
15583 got_address = sgot->output_section->vma + sgot->output_offset;
15584 plt_address = splt->output_section->vma + splt->output_offset;
15585
15586 if (htab->vxworks_p)
15587 {
15588 /* The VxWorks GOT is relocated by the dynamic linker.
15589 Therefore, we must emit relocations rather than simply
15590 computing the values now. */
15591 Elf_Internal_Rela rel;
15592
15593 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 15594 put_arm_insn (htab, output_bfd, plt0_entry[0],
15595 splt->contents + 0);
15596 put_arm_insn (htab, output_bfd, plt0_entry[1],
15597 splt->contents + 4);
15598 put_arm_insn (htab, output_bfd, plt0_entry[2],
15599 splt->contents + 8);
00a97672
RS		 15600 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
15601
8029a119 15602 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 15603 rel.r_offset = plt_address + 12;
15604 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
15605 rel.r_addend = 0;
15606 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
15607 htab->srelplt2->contents);
15608 }
b38cadfb 15609 else if (htab->nacl_p)
99059e56
RM		 15610 arm_nacl_put_plt0 (htab, output_bfd, splt,
15611 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 15612 else if (using_thumb_only (htab))
15613 {
15614 got_displacement = got_address - (plt_address + 12);
15615
15616 plt0_entry = elf32_thumb2_plt0_entry;
15617 put_arm_insn (htab, output_bfd, plt0_entry[0],
15618 splt->contents + 0);
15619 put_arm_insn (htab, output_bfd, plt0_entry[1],
15620 splt->contents + 4);
15621 put_arm_insn (htab, output_bfd, plt0_entry[2],
15622 splt->contents + 8);
15623
15624 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
15625 }
00a97672
RS		 15626 else
15627 {
15628 got_displacement = got_address - (plt_address + 16);
15629
15630 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 15631 put_arm_insn (htab, output_bfd, plt0_entry[0],
15632 splt->contents + 0);
15633 put_arm_insn (htab, output_bfd, plt0_entry[1],
15634 splt->contents + 4);
15635 put_arm_insn (htab, output_bfd, plt0_entry[2],
15636 splt->contents + 8);
15637 put_arm_insn (htab, output_bfd, plt0_entry[3],
15638 splt->contents + 12);
5e681ec4 15639
5e681ec4 15640#ifdef FOUR_WORD_PLT
00a97672
RS		 15641 /* The displacement value goes in the otherwise-unused
15642 last word of the second entry. */
15643 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 15644#else
00a97672 15645 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 15646#endif
00a97672 15647 }
f7a74f8c 15648 }
252b5132
RH		 15649
15650 /* UnixWare sets the entsize of .plt to 4, although that doesn't
15651 really seem like the right value. */
74541ad4
AM		 15652 if (splt->output_section->owner == output_bfd)
15653 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 15654
0855e32b
NS		 15655 if (htab->dt_tlsdesc_plt)
15656 {
15657 bfd_vma got_address
15658 = sgot->output_section->vma + sgot->output_offset;
15659 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
15660 + htab->root.sgot->output_offset);
15661 bfd_vma plt_address
15662 = splt->output_section->vma + splt->output_offset;
15663
b38cadfb 15664 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 15665 splt->contents + htab->dt_tlsdesc_plt,
15666 dl_tlsdesc_lazy_trampoline, 6);
15667
15668 bfd_put_32 (output_bfd,
15669 gotplt_address + htab->dt_tlsdesc_got
15670 - (plt_address + htab->dt_tlsdesc_plt)
15671 - dl_tlsdesc_lazy_trampoline[6],
15672 splt->contents + htab->dt_tlsdesc_plt + 24);
15673 bfd_put_32 (output_bfd,
15674 got_address - (plt_address + htab->dt_tlsdesc_plt)
15675 - dl_tlsdesc_lazy_trampoline[7],
15676 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
15677 }
15678
15679 if (htab->tls_trampoline)
15680 {
b38cadfb 15681 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 15682 splt->contents + htab->tls_trampoline,
15683 tls_trampoline, 3);
15684#ifdef FOUR_WORD_PLT
15685 bfd_put_32 (output_bfd, 0x00000000,
15686 splt->contents + htab->tls_trampoline + 12);
b38cadfb 15687#endif
0855e32b
NS		 15688 }
15689
0e1862bb
L		 15690 if (htab->vxworks_p
15691 && !bfd_link_pic (info)
15692 && htab->root.splt->size > 0)
00a97672
RS		 15693 {
15694 /* Correct the .rel(a).plt.unloaded relocations. They will have
15695 incorrect symbol indexes. */
15696 int num_plts;
eed62c48 15697 unsigned char *p;
00a97672 15698
362d30a1 15699 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 15700 / htab->plt_entry_size);
15701 p = htab->srelplt2->contents + RELOC_SIZE (htab);
15702
15703 for (; num_plts; num_plts--)
15704 {
15705 Elf_Internal_Rela rel;
15706
15707 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
15708 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
15709 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
15710 p += RELOC_SIZE (htab);
15711
15712 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
15713 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
15714 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
15715 p += RELOC_SIZE (htab);
15716 }
15717 }
252b5132
RH		 15718 }
15719
99059e56
RM		 15720 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
15721 /* NaCl uses a special first entry in .iplt too. */
15722 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
15723
252b5132 15724 /* Fill in the first three entries in the global offset table. */
229fcec5 15725 if (sgot)
252b5132 15726 {
229fcec5
MM		 15727 if (sgot->size > 0)
15728 {
15729 if (sdyn == NULL)
15730 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
15731 else
15732 bfd_put_32 (output_bfd,
15733 sdyn->output_section->vma + sdyn->output_offset,
15734 sgot->contents);
15735 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
15736 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
15737 }
252b5132 15738
229fcec5
MM		 15739 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
15740 }
252b5132 15741
b34976b6 15742 return TRUE;
252b5132
RH		 15743}
15744
ba96a88f 15745static void
57e8b36a 15746elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 15747{
9b485d32 15748 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 15749 struct elf32_arm_link_hash_table *globals;
ac4c9b04 15750 struct elf_segment_map *m;
ba96a88f
NC		 15751
15752 i_ehdrp = elf_elfheader (abfd);
15753
94a3258f
PB		 15754 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
15755 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
15756 else
7394f108 15757 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 15758 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 15759
93204d3a
PB		 15760 if (link_info)
15761 {
15762 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 15763 if (globals != NULL && globals->byteswap_code)
93204d3a
PB		 15764 i_ehdrp->e_flags |= EF_ARM_BE8;
15765 }
3bfcb652
NC		 15766
15767 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
15768 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
15769 {
15770 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 15771 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 15772 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
15773 else
15774 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
15775 }
ac4c9b04
MG		 15776
15777 /* Scan segment to set p_flags attribute if it contains only sections with
15778 SHF_ARM_NOREAD flag. */
15779 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
15780 {
15781 unsigned int j;
15782
15783 if (m->count == 0)
15784 continue;
15785 for (j = 0; j < m->count; j++)
15786 {
15787 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_NOREAD))
15788 break;
15789 }
15790 if (j == m->count)
15791 {
15792 m->p_flags = PF_X;
15793 m->p_flags_valid = 1;
15794 }
15795 }
ba96a88f
NC		 15796}
15797
99e4ae17 15798static enum elf_reloc_type_class
7e612e98
AM		 15799elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
15800 const asection *rel_sec ATTRIBUTE_UNUSED,
15801 const Elf_Internal_Rela *rela)
99e4ae17 15802{
f51e552e 15803 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 15804 {
15805 case R_ARM_RELATIVE:
15806 return reloc_class_relative;
15807 case R_ARM_JUMP_SLOT:
15808 return reloc_class_plt;
15809 case R_ARM_COPY:
15810 return reloc_class_copy;
109575d7
JW		 15811 case R_ARM_IRELATIVE:
15812 return reloc_class_ifunc;
99e4ae17
AJ		 15813 default:
15814 return reloc_class_normal;
15815 }
15816}
15817
e489d0ae 15818static void
57e8b36a 15819elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 15820{
5a6c6817 15821 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 15822}
15823
40a18ebd
NC		 15824/* Return TRUE if this is an unwinding table entry. */
15825
15826static bfd_boolean
15827is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
15828{
0112cd26
NC		 15829 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
15830 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 15831}
15832
15833
15834/* Set the type and flags for an ARM section. We do this by
15835 the section name, which is a hack, but ought to work. */
15836
15837static bfd_boolean
15838elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
15839{
15840 const char * name;
15841
15842 name = bfd_get_section_name (abfd, sec);
15843
15844 if (is_arm_elf_unwind_section_name (abfd, name))
15845 {
15846 hdr->sh_type = SHT_ARM_EXIDX;
15847 hdr->sh_flags |= SHF_LINK_ORDER;
15848 }
ac4c9b04
MG		 15849
15850 if (sec->flags & SEC_ELF_NOREAD)
15851 hdr->sh_flags |= SHF_ARM_NOREAD;
15852
40a18ebd
NC		 15853 return TRUE;
15854}
15855
6dc132d9
L		 15856/* Handle an ARM specific section when reading an object file. This is
15857 called when bfd_section_from_shdr finds a section with an unknown
15858 type. */
40a18ebd
NC		 15859
15860static bfd_boolean
15861elf32_arm_section_from_shdr (bfd *abfd,
15862 Elf_Internal_Shdr * hdr,
6dc132d9
L		 15863 const char *name,
15864 int shindex)
40a18ebd
NC		 15865{
15866 /* There ought to be a place to keep ELF backend specific flags, but
15867 at the moment there isn't one. We just keep track of the
15868 sections by their name, instead. Fortunately, the ABI gives
15869 names for all the ARM specific sections, so we will probably get
15870 away with this. */
15871 switch (hdr->sh_type)
15872 {
15873 case SHT_ARM_EXIDX:
0951f019
RE		 15874 case SHT_ARM_PREEMPTMAP:
15875 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 15876 break;
15877
15878 default:
15879 return FALSE;
15880 }
15881
6dc132d9 15882 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 15883 return FALSE;
15884
15885 return TRUE;
15886}
e489d0ae 15887
44444f50
NC		 15888static _arm_elf_section_data *
15889get_arm_elf_section_data (asection * sec)
15890{
47b2e99c
JZ		 15891 if (sec && sec->owner && is_arm_elf (sec->owner))
15892 return elf32_arm_section_data (sec);
44444f50
NC		 15893 else
15894 return NULL;
8e3de13a
NC		 15895}
15896
4e617b1e
PB		 15897typedef struct
15898{
57402f1e 15899 void *flaginfo;
4e617b1e 15900 struct bfd_link_info *info;
91a5743d
PB		 15901 asection *sec;
15902 int sec_shndx;
6e0b88f1
AM		 15903 int (*func) (void *, const char *, Elf_Internal_Sym *,
15904 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 15905} output_arch_syminfo;
15906
15907enum map_symbol_type
15908{
15909 ARM_MAP_ARM,
15910 ARM_MAP_THUMB,
15911 ARM_MAP_DATA
15912};
15913
15914
7413f23f 15915/* Output a single mapping symbol. */
4e617b1e
PB		 15916
15917static bfd_boolean
7413f23f
DJ		 15918elf32_arm_output_map_sym (output_arch_syminfo *osi,
15919 enum map_symbol_type type,
15920 bfd_vma offset)
4e617b1e
PB		 15921{
15922 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 15923 Elf_Internal_Sym sym;
15924
91a5743d
PB		 15925 sym.st_value = osi->sec->output_section->vma
15926 + osi->sec->output_offset
15927 + offset;
4e617b1e
PB		 15928 sym.st_size = 0;
15929 sym.st_other = 0;
15930 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 15931 sym.st_shndx = osi->sec_shndx;
35fc36a8 15932 sym.st_target_internal = 0;
fe33d2fa 15933 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 15934 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 15935}
15936
34e77a92
RS		 15937/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
15938 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 15939
15940static bfd_boolean
34e77a92
RS		 15941elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
15942 bfd_boolean is_iplt_entry_p,
15943 union gotplt_union *root_plt,
15944 struct arm_plt_info *arm_plt)
4e617b1e 15945{
4e617b1e 15946 struct elf32_arm_link_hash_table *htab;
34e77a92 15947 bfd_vma addr, plt_header_size;
4e617b1e 15948
34e77a92 15949 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 15950 return TRUE;
15951
4dfe6ac6
NC		 15952 htab = elf32_arm_hash_table (osi->info);
15953 if (htab == NULL)
15954 return FALSE;
15955
34e77a92
RS		 15956 if (is_iplt_entry_p)
15957 {
15958 osi->sec = htab->root.iplt;
15959 plt_header_size = 0;
15960 }
15961 else
15962 {
15963 osi->sec = htab->root.splt;
15964 plt_header_size = htab->plt_header_size;
15965 }
15966 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
15967 (osi->info->output_bfd, osi->sec->output_section));
15968
15969 addr = root_plt->offset & -2;
4e617b1e
PB		 15970 if (htab->symbian_p)
15971 {
7413f23f 15972 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15973 return FALSE;
7413f23f 15974 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 15975 return FALSE;
15976 }
15977 else if (htab->vxworks_p)
15978 {
7413f23f 15979 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15980 return FALSE;
7413f23f 15981 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 15982 return FALSE;
7413f23f 15983 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 15984 return FALSE;
7413f23f 15985 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 15986 return FALSE;
15987 }
b38cadfb
NC		 15988 else if (htab->nacl_p)
15989 {
15990 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
15991 return FALSE;
15992 }
eed94f8f
NC		 15993 else if (using_thumb_only (htab))
15994 {
15995 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
15996 return FALSE;
6a631e86 15997 }
4e617b1e
PB		 15998 else
15999 {
34e77a92 16000 bfd_boolean thumb_stub_p;
bd97cb95 16001
34e77a92
RS		 16002 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
16003 if (thumb_stub_p)
4e617b1e 16004 {
7413f23f 16005 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 16006 return FALSE;
16007 }
16008#ifdef FOUR_WORD_PLT
7413f23f 16009 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 16010 return FALSE;
7413f23f 16011 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 16012 return FALSE;
16013#else
906e58ca 16014 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 16015 so only need to output a mapping symbol for the first PLT entry and
16016 entries with thumb thunks. */
34e77a92 16017 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 16018 {
7413f23f 16019 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 16020 return FALSE;
16021 }
16022#endif
16023 }
16024
16025 return TRUE;
16026}
16027
34e77a92
RS		 16028/* Output mapping symbols for PLT entries associated with H. */
16029
16030static bfd_boolean
16031elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
16032{
16033 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
16034 struct elf32_arm_link_hash_entry *eh;
16035
16036 if (h->root.type == bfd_link_hash_indirect)
16037 return TRUE;
16038
16039 if (h->root.type == bfd_link_hash_warning)
16040 /* When warning symbols are created, they **replace** the "real"
16041 entry in the hash table, thus we never get to see the real
16042 symbol in a hash traversal. So look at it now. */
16043 h = (struct elf_link_hash_entry *) h->root.u.i.link;
16044
16045 eh = (struct elf32_arm_link_hash_entry *) h;
16046 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
16047 &h->plt, &eh->plt);
16048}
16049
4f4faa4d
TP		 16050/* Bind a veneered symbol to its veneer identified by its hash entry
16051 STUB_ENTRY. The veneered location thus loose its symbol. */
16052
16053static void
16054arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
16055{
16056 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
16057
16058 BFD_ASSERT (hash);
16059 hash->root.root.u.def.section = stub_entry->stub_sec;
16060 hash->root.root.u.def.value = stub_entry->stub_offset;
16061 hash->root.size = stub_entry->stub_size;
16062}
16063
7413f23f
DJ		 16064/* Output a single local symbol for a generated stub. */
16065
16066static bfd_boolean
16067elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
16068 bfd_vma offset, bfd_vma size)
16069{
7413f23f
DJ		 16070 Elf_Internal_Sym sym;
16071
7413f23f
DJ		 16072 sym.st_value = osi->sec->output_section->vma
16073 + osi->sec->output_offset
16074 + offset;
16075 sym.st_size = size;
16076 sym.st_other = 0;
16077 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
16078 sym.st_shndx = osi->sec_shndx;
35fc36a8 16079 sym.st_target_internal = 0;
57402f1e 16080 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 16081}
4e617b1e 16082
da5938a2 16083static bfd_boolean
8029a119
NC		 16084arm_map_one_stub (struct bfd_hash_entry * gen_entry,
16085 void * in_arg)
da5938a2
NC		 16086{
16087 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 16088 asection *stub_sec;
16089 bfd_vma addr;
7413f23f 16090 char *stub_name;
9a008db3 16091 output_arch_syminfo *osi;
d3ce72d0 16092 const insn_sequence *template_sequence;
461a49ca
DJ		 16093 enum stub_insn_type prev_type;
16094 int size;
16095 int i;
16096 enum map_symbol_type sym_type;
da5938a2
NC		 16097
16098 /* Massage our args to the form they really have. */
16099 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 16100 osi = (output_arch_syminfo *) in_arg;
da5938a2 16101
da5938a2
NC		 16102 stub_sec = stub_entry->stub_sec;
16103
16104 /* Ensure this stub is attached to the current section being
7413f23f 16105 processed. */
da5938a2
NC		 16106 if (stub_sec != osi->sec)
16107 return TRUE;
16108
7413f23f 16109 addr = (bfd_vma) stub_entry->stub_offset;
d3ce72d0 16110 template_sequence = stub_entry->stub_template;
4f4faa4d
TP		 16111
16112 if (arm_stub_sym_claimed (stub_entry->stub_type))
16113 arm_stub_claim_sym (stub_entry);
16114 else
7413f23f 16115 {
4f4faa4d
TP		 16116 stub_name = stub_entry->output_name;
16117 switch (template_sequence[0].type)
16118 {
16119 case ARM_TYPE:
16120 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
16121 stub_entry->stub_size))
16122 return FALSE;
16123 break;
16124 case THUMB16_TYPE:
16125 case THUMB32_TYPE:
16126 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
16127 stub_entry->stub_size))
16128 return FALSE;
16129 break;
16130 default:
16131 BFD_FAIL ();
16132 return 0;
16133 }
7413f23f 16134 }
da5938a2 16135
461a49ca
DJ		 16136 prev_type = DATA_TYPE;
16137 size = 0;
16138 for (i = 0; i < stub_entry->stub_template_size; i++)
16139 {
d3ce72d0 16140 switch (template_sequence[i].type)
461a49ca
DJ		 16141 {
16142 case ARM_TYPE:
16143 sym_type = ARM_MAP_ARM;
16144 break;
16145
16146 case THUMB16_TYPE:
48229727 16147 case THUMB32_TYPE:
461a49ca
DJ		 16148 sym_type = ARM_MAP_THUMB;
16149 break;
16150
16151 case DATA_TYPE:
16152 sym_type = ARM_MAP_DATA;
16153 break;
16154
16155 default:
16156 BFD_FAIL ();
4e31c731 16157 return FALSE;
461a49ca
DJ		 16158 }
16159
d3ce72d0 16160 if (template_sequence[i].type != prev_type)
461a49ca 16161 {
d3ce72d0 16162 prev_type = template_sequence[i].type;
461a49ca
DJ		 16163 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
16164 return FALSE;
16165 }
16166
d3ce72d0 16167 switch (template_sequence[i].type)
461a49ca
DJ		 16168 {
16169 case ARM_TYPE:
48229727 16170 case THUMB32_TYPE:
461a49ca
DJ		 16171 size += 4;
16172 break;
16173
16174 case THUMB16_TYPE:
16175 size += 2;
16176 break;
16177
16178 case DATA_TYPE:
16179 size += 4;
16180 break;
16181
16182 default:
16183 BFD_FAIL ();
4e31c731 16184 return FALSE;
461a49ca
DJ		 16185 }
16186 }
16187
da5938a2
NC		 16188 return TRUE;
16189}
16190
33811162
DG		 16191/* Output mapping symbols for linker generated sections,
16192 and for those data-only sections that do not have a
16193 $d. */
4e617b1e
PB		 16194
16195static bfd_boolean
16196elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 16197 struct bfd_link_info *info,
57402f1e 16198 void *flaginfo,
6e0b88f1
AM		 16199 int (*func) (void *, const char *,
16200 Elf_Internal_Sym *,
16201 asection *,
16202 struct elf_link_hash_entry *))
4e617b1e
PB		 16203{
16204 output_arch_syminfo osi;
16205 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 16206 bfd_vma offset;
16207 bfd_size_type size;
33811162 16208 bfd *input_bfd;
4e617b1e
PB		 16209
16210 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 16211 if (htab == NULL)
16212 return FALSE;
16213
906e58ca 16214 check_use_blx (htab);
91a5743d 16215
57402f1e 16216 osi.flaginfo = flaginfo;
4e617b1e
PB		 16217 osi.info = info;
16218 osi.func = func;
906e58ca 16219
33811162
DG		 16220 /* Add a $d mapping symbol to data-only sections that
16221 don't have any mapping symbol. This may result in (harmless) redundant
16222 mapping symbols. */
16223 for (input_bfd = info->input_bfds;
16224 input_bfd != NULL;
c72f2fb2 16225 input_bfd = input_bfd->link.next)
33811162
DG		 16226 {
16227 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
16228 for (osi.sec = input_bfd->sections;
16229 osi.sec != NULL;
16230 osi.sec = osi.sec->next)
16231 {
16232 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 16233 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
16234 != 0)
33811162
DG		 16235 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
16236 == SEC_HAS_CONTENTS
16237 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 16238 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 16239 && osi.sec->size > 0
16240 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 16241 {
16242 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16243 (output_bfd, osi.sec->output_section);
16244 if (osi.sec_shndx != (int)SHN_BAD)
16245 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
16246 }
16247 }
16248 }
16249
91a5743d
PB		 16250 /* ARM->Thumb glue. */
16251 if (htab->arm_glue_size > 0)
16252 {
3d4d4302
AM		 16253 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
16254 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 16255
16256 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16257 (output_bfd, osi.sec->output_section);
0e1862bb 16258 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 16259 || htab->pic_veneer)
16260 size = ARM2THUMB_PIC_GLUE_SIZE;
16261 else if (htab->use_blx)
16262 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
16263 else
16264 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 16265
91a5743d
PB		 16266 for (offset = 0; offset < htab->arm_glue_size; offset += size)
16267 {
7413f23f
DJ		 16268 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
16269 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 16270 }
16271 }
16272
16273 /* Thumb->ARM glue. */
16274 if (htab->thumb_glue_size > 0)
16275 {
3d4d4302
AM		 16276 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
16277 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 16278
16279 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16280 (output_bfd, osi.sec->output_section);
16281 size = THUMB2ARM_GLUE_SIZE;
16282
16283 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
16284 {
7413f23f
DJ		 16285 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
16286 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 16287 }
16288 }
16289
845b51d6
PB		 16290 /* ARMv4 BX veneers. */
16291 if (htab->bx_glue_size > 0)
16292 {
3d4d4302
AM		 16293 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
16294 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 16295
16296 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16297 (output_bfd, osi.sec->output_section);
16298
7413f23f 16299 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 16300 }
16301
8029a119
NC		 16302 /* Long calls stubs. */
16303 if (htab->stub_bfd && htab->stub_bfd->sections)
16304 {
da5938a2 16305 asection* stub_sec;
8029a119 16306
da5938a2
NC		 16307 for (stub_sec = htab->stub_bfd->sections;
16308 stub_sec != NULL;
8029a119
NC		 16309 stub_sec = stub_sec->next)
16310 {
16311 /* Ignore non-stub sections. */
16312 if (!strstr (stub_sec->name, STUB_SUFFIX))
16313 continue;
da5938a2 16314
8029a119 16315 osi.sec = stub_sec;
da5938a2 16316
8029a119
NC		 16317 osi.sec_shndx = _bfd_elf_section_from_bfd_section
16318 (output_bfd, osi.sec->output_section);
da5938a2 16319
8029a119
NC		 16320 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
16321 }
16322 }
da5938a2 16323
91a5743d 16324 /* Finally, output mapping symbols for the PLT. */
34e77a92 16325 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 16326 {
34e77a92
RS		 16327 osi.sec = htab->root.splt;
16328 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
16329 (output_bfd, osi.sec->output_section));
16330
16331 /* Output mapping symbols for the plt header. SymbianOS does not have a
16332 plt header. */
16333 if (htab->vxworks_p)
16334 {
16335 /* VxWorks shared libraries have no PLT header. */
0e1862bb 16336 if (!bfd_link_pic (info))
34e77a92
RS		 16337 {
16338 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16339 return FALSE;
16340 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
16341 return FALSE;
16342 }
16343 }
b38cadfb
NC		 16344 else if (htab->nacl_p)
16345 {
16346 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16347 return FALSE;
16348 }
eed94f8f
NC		 16349 else if (using_thumb_only (htab))
16350 {
16351 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
16352 return FALSE;
16353 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
16354 return FALSE;
16355 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
16356 return FALSE;
16357 }
34e77a92 16358 else if (!htab->symbian_p)
4e617b1e 16359 {
7413f23f 16360 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 16361 return FALSE;
34e77a92
RS		 16362#ifndef FOUR_WORD_PLT
16363 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 16364 return FALSE;
34e77a92 16365#endif
4e617b1e
PB		 16366 }
16367 }
99059e56
RM		 16368 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
16369 {
16370 /* NaCl uses a special first entry in .iplt too. */
16371 osi.sec = htab->root.iplt;
16372 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
16373 (output_bfd, osi.sec->output_section));
16374 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16375 return FALSE;
16376 }
34e77a92
RS		 16377 if ((htab->root.splt && htab->root.splt->size > 0)
16378 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 16379 {
34e77a92
RS		 16380 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
16381 for (input_bfd = info->input_bfds;
16382 input_bfd != NULL;
c72f2fb2 16383 input_bfd = input_bfd->link.next)
34e77a92
RS		 16384 {
16385 struct arm_local_iplt_info **local_iplt;
16386 unsigned int i, num_syms;
4e617b1e 16387
34e77a92
RS		 16388 local_iplt = elf32_arm_local_iplt (input_bfd);
16389 if (local_iplt != NULL)
16390 {
16391 num_syms = elf_symtab_hdr (input_bfd).sh_info;
16392 for (i = 0; i < num_syms; i++)
16393 if (local_iplt[i] != NULL
16394 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
16395 &local_iplt[i]->root,
16396 &local_iplt[i]->arm))
16397 return FALSE;
16398 }
16399 }
16400 }
0855e32b
NS		 16401 if (htab->dt_tlsdesc_plt != 0)
16402 {
16403 /* Mapping symbols for the lazy tls trampoline. */
16404 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
16405 return FALSE;
b38cadfb 16406
0855e32b
NS		 16407 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
16408 htab->dt_tlsdesc_plt + 24))
16409 return FALSE;
16410 }
16411 if (htab->tls_trampoline != 0)
16412 {
16413 /* Mapping symbols for the tls trampoline. */
16414 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
16415 return FALSE;
16416#ifdef FOUR_WORD_PLT
16417 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
16418 htab->tls_trampoline + 12))
16419 return FALSE;
b38cadfb 16420#endif
0855e32b 16421 }
b38cadfb 16422
4e617b1e
PB		 16423 return TRUE;
16424}
16425
e489d0ae
PB		 16426/* Allocate target specific section data. */
16427
16428static bfd_boolean
16429elf32_arm_new_section_hook (bfd *abfd, asection *sec)
16430{
f592407e
AM		 16431 if (!sec->used_by_bfd)
16432 {
16433 _arm_elf_section_data *sdata;
16434 bfd_size_type amt = sizeof (*sdata);
e489d0ae 16435
21d799b5 16436 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 16437 if (sdata == NULL)
16438 return FALSE;
16439 sec->used_by_bfd = sdata;
16440 }
e489d0ae
PB		 16441
16442 return _bfd_elf_new_section_hook (abfd, sec);
16443}
16444
16445
16446/* Used to order a list of mapping symbols by address. */
16447
16448static int
16449elf32_arm_compare_mapping (const void * a, const void * b)
16450{
7f6a71ff
JM		 16451 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
16452 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
16453
16454 if (amap->vma > bmap->vma)
16455 return 1;
16456 else if (amap->vma < bmap->vma)
16457 return -1;
16458 else if (amap->type > bmap->type)
16459 /* Ensure results do not depend on the host qsort for objects with
16460 multiple mapping symbols at the same address by sorting on type
16461 after vma. */
16462 return 1;
16463 else if (amap->type < bmap->type)
16464 return -1;
16465 else
16466 return 0;
e489d0ae
PB		 16467}
16468
2468f9c9
PB		 16469/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
16470
16471static unsigned long
16472offset_prel31 (unsigned long addr, bfd_vma offset)
16473{
16474 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
16475}
16476
16477/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
16478 relocations. */
16479
16480static void
16481copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
16482{
16483 unsigned long first_word = bfd_get_32 (output_bfd, from);
16484 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 16485
2468f9c9
PB		 16486 /* High bit of first word is supposed to be zero. */
16487 if ((first_word & 0x80000000ul) == 0)
16488 first_word = offset_prel31 (first_word, offset);
b38cadfb 16489
2468f9c9
PB		 16490 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
16491 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
16492 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
16493 second_word = offset_prel31 (second_word, offset);
b38cadfb 16494
2468f9c9
PB		 16495 bfd_put_32 (output_bfd, first_word, to);
16496 bfd_put_32 (output_bfd, second_word, to + 4);
16497}
e489d0ae 16498
48229727
JB		 16499/* Data for make_branch_to_a8_stub(). */
16500
b38cadfb
NC		 16501struct a8_branch_to_stub_data
16502{
48229727
JB		 16503 asection *writing_section;
16504 bfd_byte *contents;
16505};
16506
16507
16508/* Helper to insert branches to Cortex-A8 erratum stubs in the right
16509 places for a particular section. */
16510
16511static bfd_boolean
16512make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 16513 void *in_arg)
48229727
JB		 16514{
16515 struct elf32_arm_stub_hash_entry *stub_entry;
16516 struct a8_branch_to_stub_data *data;
16517 bfd_byte *contents;
16518 unsigned long branch_insn;
16519 bfd_vma veneered_insn_loc, veneer_entry_loc;
16520 bfd_signed_vma branch_offset;
16521 bfd *abfd;
8d9d9490 16522 unsigned int loc;
48229727
JB		 16523
16524 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
16525 data = (struct a8_branch_to_stub_data *) in_arg;
16526
16527 if (stub_entry->target_section != data->writing_section
4563a860 16528 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 16529 return TRUE;
16530
16531 contents = data->contents;
16532
8d9d9490
TP		 16533 /* We use target_section as Cortex-A8 erratum workaround stubs are only
16534 generated when both source and target are in the same section. */
48229727
JB		 16535 veneered_insn_loc = stub_entry->target_section->output_section->vma
16536 + stub_entry->target_section->output_offset
8d9d9490 16537 + stub_entry->source_value;
48229727
JB		 16538
16539 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
16540 + stub_entry->stub_sec->output_offset
16541 + stub_entry->stub_offset;
16542
16543 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
16544 veneered_insn_loc &= ~3u;
16545
16546 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
16547
16548 abfd = stub_entry->target_section->owner;
8d9d9490 16549 loc = stub_entry->source_value;
48229727
JB		 16550
16551 /* We attempt to avoid this condition by setting stubs_always_after_branch
16552 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
16553 This check is just to be on the safe side... */
16554 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
16555 {
16556 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub is "
16557 "allocated in unsafe location"), abfd);
16558 return FALSE;
16559 }
16560
16561 switch (stub_entry->stub_type)
16562 {
16563 case arm_stub_a8_veneer_b:
16564 case arm_stub_a8_veneer_b_cond:
16565 branch_insn = 0xf0009000;
16566 goto jump24;
16567
16568 case arm_stub_a8_veneer_blx:
16569 branch_insn = 0xf000e800;
16570 goto jump24;
16571
16572 case arm_stub_a8_veneer_bl:
16573 {
16574 unsigned int i1, j1, i2, j2, s;
16575
16576 branch_insn = 0xf000d000;
16577
16578 jump24:
16579 if (branch_offset < -16777216 || branch_offset > 16777214)
16580 {
16581 /* There's not much we can do apart from complain if this
16582 happens. */
16583 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub out "
16584 "of range (input file too large)"), abfd);
16585 return FALSE;
16586 }
16587
16588 /* i1 = not(j1 eor s), so:
16589 not i1 = j1 eor s
16590 j1 = (not i1) eor s. */
16591
16592 branch_insn |= (branch_offset >> 1) & 0x7ff;
16593 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
16594 i2 = (branch_offset >> 22) & 1;
16595 i1 = (branch_offset >> 23) & 1;
16596 s = (branch_offset >> 24) & 1;
16597 j1 = (!i1) ^ s;
16598 j2 = (!i2) ^ s;
16599 branch_insn |= j2 << 11;
16600 branch_insn |= j1 << 13;
16601 branch_insn |= s << 26;
16602 }
16603 break;
16604
16605 default:
16606 BFD_FAIL ();
16607 return FALSE;
16608 }
16609
8d9d9490
TP		 16610 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
16611 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
48229727
JB		 16612
16613 return TRUE;
16614}
16615
a504d23a
LA		 16616/* Beginning of stm32l4xx work-around. */
16617
16618/* Functions encoding instructions necessary for the emission of the
16619 fix-stm32l4xx-629360.
16620 Encoding is extracted from the
16621 ARM (C) Architecture Reference Manual
16622 ARMv7-A and ARMv7-R edition
16623 ARM DDI 0406C.b (ID072512). */
16624
16625static inline bfd_vma
82188b29 16626create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 16627{
16628 /* A8.8.18 B (A8-334)
16629 B target_address (Encoding T4). */
16630 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
16631 /* jump offset is: S:I1:I2:imm10:imm11:0. */
16632 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
16633
a504d23a
LA		 16634 int s = ((branch_offset & 0x1000000) >> 24);
16635 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
16636 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
16637
16638 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
16639 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
16640
16641 bfd_vma patched_inst = 0xf0009000
16642 | s << 26 /* S. */
16643 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
16644 | j1 << 13 /* J1. */
16645 | j2 << 11 /* J2. */
16646 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
16647
16648 return patched_inst;
16649}
16650
16651static inline bfd_vma
16652create_instruction_ldmia (int base_reg, int wback, int reg_mask)
16653{
16654 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
16655 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
16656 bfd_vma patched_inst = 0xe8900000
16657 | (/*W=*/wback << 21)
16658 | (base_reg << 16)
16659 | (reg_mask & 0x0000ffff);
16660
16661 return patched_inst;
16662}
16663
16664static inline bfd_vma
16665create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
16666{
16667 /* A8.8.60 LDMDB/LDMEA (A8-402)
16668 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
16669 bfd_vma patched_inst = 0xe9100000
16670 | (/*W=*/wback << 21)
16671 | (base_reg << 16)
16672 | (reg_mask & 0x0000ffff);
16673
16674 return patched_inst;
16675}
16676
16677static inline bfd_vma
16678create_instruction_mov (int target_reg, int source_reg)
16679{
16680 /* A8.8.103 MOV (register) (A8-486)
16681 MOV Rd, Rm (Encoding T1). */
16682 bfd_vma patched_inst = 0x4600
16683 | (target_reg & 0x7)
16684 | ((target_reg & 0x8) >> 3) << 7
16685 | (source_reg << 3);
16686
16687 return patched_inst;
16688}
16689
16690static inline bfd_vma
16691create_instruction_sub (int target_reg, int source_reg, int value)
16692{
16693 /* A8.8.221 SUB (immediate) (A8-708)
16694 SUB Rd, Rn, #value (Encoding T3). */
16695 bfd_vma patched_inst = 0xf1a00000
16696 | (target_reg << 8)
16697 | (source_reg << 16)
16698 | (/*S=*/0 << 20)
16699 | ((value & 0x800) >> 11) << 26
16700 | ((value & 0x700) >> 8) << 12
16701 | (value & 0x0ff);
16702
16703 return patched_inst;
16704}
16705
16706static inline bfd_vma
9239bbd3 16707create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
a504d23a
LA		 16708 int first_reg)
16709{
16710 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 16711 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
16712 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
a504d23a
LA		 16713 | (/*W=*/wback << 21)
16714 | (base_reg << 16)
9239bbd3
CM		 16715 | (num_words & 0x000000ff)
16716 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
a504d23a
LA		 16717 | (first_reg & 0x00000001) << 22;
16718
16719 return patched_inst;
16720}
16721
16722static inline bfd_vma
9239bbd3
CM		 16723create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
16724 int first_reg)
a504d23a
LA		 16725{
16726 /* A8.8.332 VLDM (A8-922)
9239bbd3
CM		 16727 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
16728 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
a504d23a 16729 | (base_reg << 16)
9239bbd3
CM		 16730 | (num_words & 0x000000ff)
16731 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
a504d23a
LA		 16732 | (first_reg & 0x00000001) << 22;
16733
16734 return patched_inst;
16735}
16736
16737static inline bfd_vma
16738create_instruction_udf_w (int value)
16739{
16740 /* A8.8.247 UDF (A8-758)
16741 Undefined (Encoding T2). */
16742 bfd_vma patched_inst = 0xf7f0a000
16743 | (value & 0x00000fff)
16744 | (value & 0x000f0000) << 16;
16745
16746 return patched_inst;
16747}
16748
16749static inline bfd_vma
16750create_instruction_udf (int value)
16751{
16752 /* A8.8.247 UDF (A8-758)
16753 Undefined (Encoding T1). */
16754 bfd_vma patched_inst = 0xde00
16755 | (value & 0xff);
16756
16757 return patched_inst;
16758}
16759
16760/* Functions writing an instruction in memory, returning the next
16761 memory position to write to. */
16762
16763static inline bfd_byte *
16764push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
16765 bfd * output_bfd, bfd_byte *pt, insn32 insn)
16766{
16767 put_thumb2_insn (htab, output_bfd, insn, pt);
16768 return pt + 4;
16769}
16770
16771static inline bfd_byte *
16772push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
16773 bfd * output_bfd, bfd_byte *pt, insn32 insn)
16774{
16775 put_thumb_insn (htab, output_bfd, insn, pt);
16776 return pt + 2;
16777}
16778
16779/* Function filling up a region in memory with T1 and T2 UDFs taking
16780 care of alignment. */
16781
16782static bfd_byte *
16783stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
16784 bfd * output_bfd,
16785 const bfd_byte * const base_stub_contents,
16786 bfd_byte * const from_stub_contents,
16787 const bfd_byte * const end_stub_contents)
16788{
16789 bfd_byte *current_stub_contents = from_stub_contents;
16790
16791 /* Fill the remaining of the stub with deterministic contents : UDF
16792 instructions.
16793 Check if realignment is needed on modulo 4 frontier using T1, to
16794 further use T2. */
16795 if ((current_stub_contents < end_stub_contents)
16796 && !((current_stub_contents - base_stub_contents) % 2)
16797 && ((current_stub_contents - base_stub_contents) % 4))
16798 current_stub_contents =
16799 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16800 create_instruction_udf (0));
16801
16802 for (; current_stub_contents < end_stub_contents;)
16803 current_stub_contents =
16804 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16805 create_instruction_udf_w (0));
16806
16807 return current_stub_contents;
16808}
16809
16810/* Functions writing the stream of instructions equivalent to the
16811 derived sequence for ldmia, ldmdb, vldm respectively. */
16812
16813static void
16814stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
16815 bfd * output_bfd,
16816 const insn32 initial_insn,
16817 const bfd_byte *const initial_insn_addr,
16818 bfd_byte *const base_stub_contents)
16819{
16820 int wback = (initial_insn & 0x00200000) >> 21;
16821 int ri, rn = (initial_insn & 0x000F0000) >> 16;
16822 int insn_all_registers = initial_insn & 0x0000ffff;
16823 int insn_low_registers, insn_high_registers;
16824 int usable_register_mask;
16825 int nb_registers = popcount (insn_all_registers);
16826 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
16827 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
16828 bfd_byte *current_stub_contents = base_stub_contents;
16829
16830 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
16831
16832 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16833 smaller than 8 registers load sequences that do not cause the
16834 hardware issue. */
16835 if (nb_registers <= 8)
16836 {
16837 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
16838 current_stub_contents =
16839 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16840 initial_insn);
16841
16842 /* B initial_insn_addr+4. */
16843 if (!restore_pc)
16844 current_stub_contents =
16845 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16846 create_instruction_branch_absolute
82188b29
NC		 16847 (initial_insn_addr - current_stub_contents));
16848
a504d23a
LA		 16849
16850 /* Fill the remaining of the stub with deterministic contents. */
16851 current_stub_contents =
16852 stm32l4xx_fill_stub_udf (htab, output_bfd,
16853 base_stub_contents, current_stub_contents,
16854 base_stub_contents +
16855 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16856
16857 return;
16858 }
16859
16860 /* - reg_list[13] == 0. */
16861 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
16862
16863 /* - reg_list[14] & reg_list[15] != 1. */
16864 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
16865
16866 /* - if (wback==1) reg_list[rn] == 0. */
16867 BFD_ASSERT (!wback || !restore_rn);
16868
16869 /* - nb_registers > 8. */
16870 BFD_ASSERT (popcount (insn_all_registers) > 8);
16871
16872 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
16873
16874 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
16875 - One with the 7 lowest registers (register mask 0x007F)
16876 This LDM will finally contain between 2 and 7 registers
16877 - One with the 7 highest registers (register mask 0xDF80)
16878 This ldm will finally contain between 2 and 7 registers. */
16879 insn_low_registers = insn_all_registers & 0x007F;
16880 insn_high_registers = insn_all_registers & 0xDF80;
16881
16882 /* A spare register may be needed during this veneer to temporarily
16883 handle the base register. This register will be restored with the
16884 last LDM operation.
16885 The usable register may be any general purpose register (that
16886 excludes PC, SP, LR : register mask is 0x1FFF). */
16887 usable_register_mask = 0x1FFF;
16888
16889 /* Generate the stub function. */
16890 if (wback)
16891 {
16892 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
16893 current_stub_contents =
16894 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16895 create_instruction_ldmia
16896 (rn, /*wback=*/1, insn_low_registers));
16897
16898 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
16899 current_stub_contents =
16900 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16901 create_instruction_ldmia
16902 (rn, /*wback=*/1, insn_high_registers));
16903 if (!restore_pc)
16904 {
16905 /* B initial_insn_addr+4. */
16906 current_stub_contents =
16907 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16908 create_instruction_branch_absolute
82188b29 16909 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16910 }
16911 }
16912 else /* if (!wback). */
16913 {
16914 ri = rn;
16915
16916 /* If Rn is not part of the high-register-list, move it there. */
16917 if (!(insn_high_registers & (1 << rn)))
16918 {
16919 /* Choose a Ri in the high-register-list that will be restored. */
16920 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16921
16922 /* MOV Ri, Rn. */
16923 current_stub_contents =
16924 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16925 create_instruction_mov (ri, rn));
16926 }
16927
16928 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
16929 current_stub_contents =
16930 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16931 create_instruction_ldmia
16932 (ri, /*wback=*/1, insn_low_registers));
16933
16934 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
16935 current_stub_contents =
16936 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16937 create_instruction_ldmia
16938 (ri, /*wback=*/0, insn_high_registers));
16939
16940 if (!restore_pc)
16941 {
16942 /* B initial_insn_addr+4. */
16943 current_stub_contents =
16944 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16945 create_instruction_branch_absolute
82188b29 16946 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16947 }
16948 }
16949
16950 /* Fill the remaining of the stub with deterministic contents. */
16951 current_stub_contents =
16952 stm32l4xx_fill_stub_udf (htab, output_bfd,
16953 base_stub_contents, current_stub_contents,
16954 base_stub_contents +
16955 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16956}
16957
16958static void
16959stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
16960 bfd * output_bfd,
16961 const insn32 initial_insn,
16962 const bfd_byte *const initial_insn_addr,
16963 bfd_byte *const base_stub_contents)
16964{
16965 int wback = (initial_insn & 0x00200000) >> 21;
16966 int ri, rn = (initial_insn & 0x000f0000) >> 16;
16967 int insn_all_registers = initial_insn & 0x0000ffff;
16968 int insn_low_registers, insn_high_registers;
16969 int usable_register_mask;
16970 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
16971 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
16972 int nb_registers = popcount (insn_all_registers);
16973 bfd_byte *current_stub_contents = base_stub_contents;
16974
16975 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
16976
16977 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16978 smaller than 8 registers load sequences that do not cause the
16979 hardware issue. */
16980 if (nb_registers <= 8)
16981 {
16982 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
16983 current_stub_contents =
16984 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16985 initial_insn);
16986
16987 /* B initial_insn_addr+4. */
16988 current_stub_contents =
16989 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16990 create_instruction_branch_absolute
82188b29 16991 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16992
16993 /* Fill the remaining of the stub with deterministic contents. */
16994 current_stub_contents =
16995 stm32l4xx_fill_stub_udf (htab, output_bfd,
16996 base_stub_contents, current_stub_contents,
16997 base_stub_contents +
16998 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16999
17000 return;
17001 }
17002
17003 /* - reg_list[13] == 0. */
17004 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
17005
17006 /* - reg_list[14] & reg_list[15] != 1. */
17007 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
17008
17009 /* - if (wback==1) reg_list[rn] == 0. */
17010 BFD_ASSERT (!wback || !restore_rn);
17011
17012 /* - nb_registers > 8. */
17013 BFD_ASSERT (popcount (insn_all_registers) > 8);
17014
17015 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
17016
17017 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
17018 - One with the 7 lowest registers (register mask 0x007F)
17019 This LDM will finally contain between 2 and 7 registers
17020 - One with the 7 highest registers (register mask 0xDF80)
17021 This ldm will finally contain between 2 and 7 registers. */
17022 insn_low_registers = insn_all_registers & 0x007F;
17023 insn_high_registers = insn_all_registers & 0xDF80;
17024
17025 /* A spare register may be needed during this veneer to temporarily
17026 handle the base register. This register will be restored with
17027 the last LDM operation.
17028 The usable register may be any general purpose register (that excludes
17029 PC, SP, LR : register mask is 0x1FFF). */
17030 usable_register_mask = 0x1FFF;
17031
17032 /* Generate the stub function. */
17033 if (!wback && !restore_pc && !restore_rn)
17034 {
17035 /* Choose a Ri in the low-register-list that will be restored. */
17036 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
17037
17038 /* MOV Ri, Rn. */
17039 current_stub_contents =
17040 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17041 create_instruction_mov (ri, rn));
17042
17043 /* LDMDB Ri!, {R-high-register-list}. */
17044 current_stub_contents =
17045 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17046 create_instruction_ldmdb
17047 (ri, /*wback=*/1, insn_high_registers));
17048
17049 /* LDMDB Ri, {R-low-register-list}. */
17050 current_stub_contents =
17051 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17052 create_instruction_ldmdb
17053 (ri, /*wback=*/0, insn_low_registers));
17054
17055 /* B initial_insn_addr+4. */
17056 current_stub_contents =
17057 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17058 create_instruction_branch_absolute
82188b29 17059 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17060 }
17061 else if (wback && !restore_pc && !restore_rn)
17062 {
17063 /* LDMDB Rn!, {R-high-register-list}. */
17064 current_stub_contents =
17065 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17066 create_instruction_ldmdb
17067 (rn, /*wback=*/1, insn_high_registers));
17068
17069 /* LDMDB Rn!, {R-low-register-list}. */
17070 current_stub_contents =
17071 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17072 create_instruction_ldmdb
17073 (rn, /*wback=*/1, insn_low_registers));
17074
17075 /* B initial_insn_addr+4. */
17076 current_stub_contents =
17077 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17078 create_instruction_branch_absolute
82188b29 17079 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17080 }
17081 else if (!wback && restore_pc && !restore_rn)
17082 {
17083 /* Choose a Ri in the high-register-list that will be restored. */
17084 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
17085
17086 /* SUB Ri, Rn, #(4*nb_registers). */
17087 current_stub_contents =
17088 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17089 create_instruction_sub (ri, rn, (4 * nb_registers)));
17090
17091 /* LDMIA Ri!, {R-low-register-list}. */
17092 current_stub_contents =
17093 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17094 create_instruction_ldmia
17095 (ri, /*wback=*/1, insn_low_registers));
17096
17097 /* LDMIA Ri, {R-high-register-list}. */
17098 current_stub_contents =
17099 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17100 create_instruction_ldmia
17101 (ri, /*wback=*/0, insn_high_registers));
17102 }
17103 else if (wback && restore_pc && !restore_rn)
17104 {
17105 /* Choose a Ri in the high-register-list that will be restored. */
17106 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
17107
17108 /* SUB Rn, Rn, #(4*nb_registers) */
17109 current_stub_contents =
17110 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17111 create_instruction_sub (rn, rn, (4 * nb_registers)));
17112
17113 /* MOV Ri, Rn. */
17114 current_stub_contents =
17115 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17116 create_instruction_mov (ri, rn));
17117
17118 /* LDMIA Ri!, {R-low-register-list}. */
17119 current_stub_contents =
17120 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17121 create_instruction_ldmia
17122 (ri, /*wback=*/1, insn_low_registers));
17123
17124 /* LDMIA Ri, {R-high-register-list}. */
17125 current_stub_contents =
17126 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17127 create_instruction_ldmia
17128 (ri, /*wback=*/0, insn_high_registers));
17129 }
17130 else if (!wback && !restore_pc && restore_rn)
17131 {
17132 ri = rn;
17133 if (!(insn_low_registers & (1 << rn)))
17134 {
17135 /* Choose a Ri in the low-register-list that will be restored. */
17136 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
17137
17138 /* MOV Ri, Rn. */
17139 current_stub_contents =
17140 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
17141 create_instruction_mov (ri, rn));
17142 }
17143
17144 /* LDMDB Ri!, {R-high-register-list}. */
17145 current_stub_contents =
17146 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17147 create_instruction_ldmdb
17148 (ri, /*wback=*/1, insn_high_registers));
17149
17150 /* LDMDB Ri, {R-low-register-list}. */
17151 current_stub_contents =
17152 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17153 create_instruction_ldmdb
17154 (ri, /*wback=*/0, insn_low_registers));
17155
17156 /* B initial_insn_addr+4. */
17157 current_stub_contents =
17158 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17159 create_instruction_branch_absolute
82188b29 17160 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17161 }
17162 else if (!wback && restore_pc && restore_rn)
17163 {
17164 ri = rn;
17165 if (!(insn_high_registers & (1 << rn)))
17166 {
17167 /* Choose a Ri in the high-register-list that will be restored. */
17168 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
17169 }
17170
17171 /* SUB Ri, Rn, #(4*nb_registers). */
17172 current_stub_contents =
17173 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17174 create_instruction_sub (ri, rn, (4 * nb_registers)));
17175
17176 /* LDMIA Ri!, {R-low-register-list}. */
17177 current_stub_contents =
17178 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17179 create_instruction_ldmia
17180 (ri, /*wback=*/1, insn_low_registers));
17181
17182 /* LDMIA Ri, {R-high-register-list}. */
17183 current_stub_contents =
17184 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17185 create_instruction_ldmia
17186 (ri, /*wback=*/0, insn_high_registers));
17187 }
17188 else if (wback && restore_rn)
17189 {
17190 /* The assembler should not have accepted to encode this. */
17191 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
17192 "undefined behavior.\n");
17193 }
17194
17195 /* Fill the remaining of the stub with deterministic contents. */
17196 current_stub_contents =
17197 stm32l4xx_fill_stub_udf (htab, output_bfd,
17198 base_stub_contents, current_stub_contents,
17199 base_stub_contents +
17200 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
17201
17202}
17203
17204static void
17205stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
17206 bfd * output_bfd,
17207 const insn32 initial_insn,
17208 const bfd_byte *const initial_insn_addr,
17209 bfd_byte *const base_stub_contents)
17210{
9239bbd3 17211 int num_words = ((unsigned int) initial_insn << 24) >> 24;
a504d23a
LA		 17212 bfd_byte *current_stub_contents = base_stub_contents;
17213
17214 BFD_ASSERT (is_thumb2_vldm (initial_insn));
17215
17216 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
9239bbd3 17217 smaller than 8 words load sequences that do not cause the
a504d23a 17218 hardware issue. */
9239bbd3 17219 if (num_words <= 8)
a504d23a
LA		 17220 {
17221 /* Untouched instruction. */
17222 current_stub_contents =
17223 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17224 initial_insn);
17225
17226 /* B initial_insn_addr+4. */
17227 current_stub_contents =
17228 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17229 create_instruction_branch_absolute
82188b29 17230 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17231 }
17232 else
17233 {
9239bbd3
CM		 17234 bfd_boolean is_dp = /* DP encoding. */
17235 (initial_insn & 0xfe100f00) == 0xec100b00;
a504d23a
LA		 17236 bfd_boolean is_ia_nobang = /* (IA without !). */
17237 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
17238 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
17239 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
17240 bfd_boolean is_db_bang = /* (DB with !). */
17241 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
9239bbd3 17242 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
a504d23a 17243 /* d = UInt (Vd:D);. */
9239bbd3 17244 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
a504d23a
LA		 17245 | (((unsigned int)initial_insn << 9) >> 31);
17246
9239bbd3
CM		 17247 /* Compute the number of 8-words chunks needed to split. */
17248 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
a504d23a
LA		 17249 int chunk;
17250
17251 /* The test coverage has been done assuming the following
17252 hypothesis that exactly one of the previous is_ predicates is
17253 true. */
9239bbd3
CM		 17254 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
17255 && !(is_ia_nobang & is_ia_bang & is_db_bang));
a504d23a 17256
9239bbd3 17257 /* We treat the cutting of the words in one pass for all
a504d23a
LA		 17258 cases, then we emit the adjustments:
17259
17260 vldm rx, {...}
17261 -> vldm rx!, {8_words_or_less} for each needed 8_word
17262 -> sub rx, rx, #size (list)
17263
17264 vldm rx!, {...}
17265 -> vldm rx!, {8_words_or_less} for each needed 8_word
17266 This also handles vpop instruction (when rx is sp)
17267
17268 vldmd rx!, {...}
17269 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
9239bbd3 17270 for (chunk = 0; chunk < chunks; ++chunk)
a504d23a 17271 {
9239bbd3
CM		 17272 bfd_vma new_insn = 0;
17273
a504d23a
LA		 17274 if (is_ia_nobang || is_ia_bang)
17275 {
9239bbd3
CM		 17276 new_insn = create_instruction_vldmia
17277 (base_reg,
17278 is_dp,
17279 /*wback= . */1,
17280 chunks - (chunk + 1) ?
17281 8 : num_words - chunk * 8,
17282 first_reg + chunk * 8);
a504d23a
LA		 17283 }
17284 else if (is_db_bang)
17285 {
9239bbd3
CM		 17286 new_insn = create_instruction_vldmdb
17287 (base_reg,
17288 is_dp,
17289 chunks - (chunk + 1) ?
17290 8 : num_words - chunk * 8,
17291 first_reg + chunk * 8);
a504d23a 17292 }
9239bbd3
CM		 17293
17294 if (new_insn)
17295 current_stub_contents =
17296 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17297 new_insn);
a504d23a
LA		 17298 }
17299
17300 /* Only this case requires the base register compensation
17301 subtract. */
17302 if (is_ia_nobang)
17303 {
17304 current_stub_contents =
17305 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17306 create_instruction_sub
9239bbd3 17307 (base_reg, base_reg, 4*num_words));
a504d23a
LA		 17308 }
17309
17310 /* B initial_insn_addr+4. */
17311 current_stub_contents =
17312 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
17313 create_instruction_branch_absolute
82188b29 17314 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 17315 }
17316
17317 /* Fill the remaining of the stub with deterministic contents. */
17318 current_stub_contents =
17319 stm32l4xx_fill_stub_udf (htab, output_bfd,
17320 base_stub_contents, current_stub_contents,
17321 base_stub_contents +
17322 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
17323}
17324
17325static void
17326stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
17327 bfd * output_bfd,
17328 const insn32 wrong_insn,
17329 const bfd_byte *const wrong_insn_addr,
17330 bfd_byte *const stub_contents)
17331{
17332 if (is_thumb2_ldmia (wrong_insn))
17333 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
17334 wrong_insn, wrong_insn_addr,
17335 stub_contents);
17336 else if (is_thumb2_ldmdb (wrong_insn))
17337 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
17338 wrong_insn, wrong_insn_addr,
17339 stub_contents);
17340 else if (is_thumb2_vldm (wrong_insn))
17341 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
17342 wrong_insn, wrong_insn_addr,
17343 stub_contents);
17344}
17345
17346/* End of stm32l4xx work-around. */
17347
17348
491d01d3
YU		 17349static void
17350elf32_arm_add_relocation (bfd *output_bfd, struct bfd_link_info *info,
17351 asection *output_sec, Elf_Internal_Rela *rel)
17352{
17353 BFD_ASSERT (output_sec && rel);
17354 struct bfd_elf_section_reloc_data *output_reldata;
17355 struct elf32_arm_link_hash_table *htab;
17356 struct bfd_elf_section_data *oesd = elf_section_data (output_sec);
17357 Elf_Internal_Shdr *rel_hdr;
17358
17359
17360 if (oesd->rel.hdr)
17361 {
17362 rel_hdr = oesd->rel.hdr;
17363 output_reldata = &(oesd->rel);
17364 }
17365 else if (oesd->rela.hdr)
17366 {
17367 rel_hdr = oesd->rela.hdr;
17368 output_reldata = &(oesd->rela);
17369 }
17370 else
17371 {
17372 abort ();
17373 }
17374
17375 bfd_byte *erel = rel_hdr->contents;
17376 erel += output_reldata->count * rel_hdr->sh_entsize;
17377 htab = elf32_arm_hash_table (info);
17378 SWAP_RELOC_OUT (htab) (output_bfd, rel, erel);
17379 output_reldata->count++;
17380}
17381
e489d0ae
PB		 17382/* Do code byteswapping. Return FALSE afterwards so that the section is
17383 written out as normal. */
17384
17385static bfd_boolean
c7b8f16e 17386elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 17387 struct bfd_link_info *link_info,
17388 asection *sec,
e489d0ae
PB		 17389 bfd_byte *contents)
17390{
48229727 17391 unsigned int mapcount, errcount;
8e3de13a 17392 _arm_elf_section_data *arm_data;
c7b8f16e 17393 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 17394 elf32_arm_section_map *map;
c7b8f16e 17395 elf32_vfp11_erratum_list *errnode;
a504d23a 17396 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 17397 bfd_vma ptr;
17398 bfd_vma end;
c7b8f16e 17399 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 17400 bfd_byte tmp;
48229727 17401 unsigned int i;
57e8b36a 17402
4dfe6ac6
NC		 17403 if (globals == NULL)
17404 return FALSE;
17405
8e3de13a
NC		 17406 /* If this section has not been allocated an _arm_elf_section_data
17407 structure then we cannot record anything. */
17408 arm_data = get_arm_elf_section_data (sec);
17409 if (arm_data == NULL)
17410 return FALSE;
17411
17412 mapcount = arm_data->mapcount;
17413 map = arm_data->map;
c7b8f16e
JB		 17414 errcount = arm_data->erratumcount;
17415
17416 if (errcount != 0)
17417 {
17418 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
17419
17420 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 17421 errnode = errnode->next)
17422 {
17423 bfd_vma target = errnode->vma - offset;
17424
17425 switch (errnode->type)
17426 {
17427 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
17428 {
17429 bfd_vma branch_to_veneer;
17430 /* Original condition code of instruction, plus bit mask for
17431 ARM B instruction. */
17432 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
17433 | 0x0a000000;
c7b8f16e
JB		 17434
17435 /* The instruction is before the label. */
91d6fa6a 17436 target -= 4;
c7b8f16e
JB		 17437
17438 /* Above offset included in -4 below. */
17439 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 17440 - errnode->vma - 4;
c7b8f16e
JB		 17441
17442 if ((signed) branch_to_veneer < -(1 << 25)
17443 || (signed) branch_to_veneer >= (1 << 25))
17444 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
17445 "range"), output_bfd);
17446
99059e56
RM		 17447 insn |= (branch_to_veneer >> 2) & 0xffffff;
17448 contents[endianflip ^ target] = insn & 0xff;
17449 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
17450 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
17451 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
17452 }
17453 break;
c7b8f16e
JB		 17454
17455 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 17456 {
17457 bfd_vma branch_from_veneer;
17458 unsigned int insn;
c7b8f16e 17459
99059e56
RM		 17460 /* Take size of veneer into account. */
17461 branch_from_veneer = errnode->u.v.branch->vma
17462 - errnode->vma - 12;
c7b8f16e
JB		 17463
17464 if ((signed) branch_from_veneer < -(1 << 25)
17465 || (signed) branch_from_veneer >= (1 << 25))
17466 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
17467 "range"), output_bfd);
17468
99059e56
RM		 17469 /* Original instruction. */
17470 insn = errnode->u.v.branch->u.b.vfp_insn;
17471 contents[endianflip ^ target] = insn & 0xff;
17472 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
17473 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
17474 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
17475
17476 /* Branch back to insn after original insn. */
17477 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
17478 contents[endianflip ^ (target + 4)] = insn & 0xff;
17479 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
17480 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
17481 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
17482 }
17483 break;
c7b8f16e 17484
99059e56
RM		 17485 default:
17486 abort ();
17487 }
17488 }
c7b8f16e 17489 }
e489d0ae 17490
a504d23a
LA		 17491 if (arm_data->stm32l4xx_erratumcount != 0)
17492 {
17493 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
17494 stm32l4xx_errnode != 0;
17495 stm32l4xx_errnode = stm32l4xx_errnode->next)
17496 {
17497 bfd_vma target = stm32l4xx_errnode->vma - offset;
17498
17499 switch (stm32l4xx_errnode->type)
17500 {
17501 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
17502 {
17503 unsigned int insn;
17504 bfd_vma branch_to_veneer =
17505 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
17506
17507 if ((signed) branch_to_veneer < -(1 << 24)
17508 || (signed) branch_to_veneer >= (1 << 24))
17509 {
17510 bfd_vma out_of_range =
17511 ((signed) branch_to_veneer < -(1 << 24)) ?
17512 - branch_to_veneer - (1 << 24) :
17513 ((signed) branch_to_veneer >= (1 << 24)) ?
17514 branch_to_veneer - (1 << 24) : 0;
17515
17516 (*_bfd_error_handler)
17517 (_("%B(%#x): error: Cannot create STM32L4XX veneer. "
eee926f2 17518 "Jump out of range by %ld bytes. "
a504d23a
LA		 17519 "Cannot encode branch instruction. "),
17520 output_bfd,
eee926f2 17521 (long) (stm32l4xx_errnode->vma - 4),
a504d23a
LA		 17522 out_of_range);
17523 continue;
17524 }
17525
17526 insn = create_instruction_branch_absolute
82188b29 17527 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 17528
17529 /* The instruction is before the label. */
17530 target -= 4;
17531
17532 put_thumb2_insn (globals, output_bfd,
17533 (bfd_vma) insn, contents + target);
17534 }
17535 break;
17536
17537 case STM32L4XX_ERRATUM_VENEER:
17538 {
82188b29
NC		 17539 bfd_byte * veneer;
17540 bfd_byte * veneer_r;
a504d23a
LA		 17541 unsigned int insn;
17542
82188b29
NC		 17543 veneer = contents + target;
17544 veneer_r = veneer
17545 + stm32l4xx_errnode->u.b.veneer->vma
17546 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 17547
17548 if ((signed) (veneer_r - veneer -
17549 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
17550 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
17551 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
17552 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
17553 || (signed) (veneer_r - veneer) >= (1 << 24))
17554 {
17555 (*_bfd_error_handler) (_("%B: error: Cannot create STM32L4XX "
17556 "veneer."), output_bfd);
17557 continue;
17558 }
17559
17560 /* Original instruction. */
17561 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
17562
17563 stm32l4xx_create_replacing_stub
17564 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
17565 }
17566 break;
17567
17568 default:
17569 abort ();
17570 }
17571 }
17572 }
17573
2468f9c9
PB		 17574 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
17575 {
17576 arm_unwind_table_edit *edit_node
99059e56 17577 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 17578 /* Now, sec->size is the size of the section we will write. The original
99059e56 17579 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 17580 markers) was sec->rawsize. (This isn't the case if we perform no
17581 edits, then rawsize will be zero and we should use size). */
21d799b5 17582 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 17583 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
17584 unsigned int in_index, out_index;
17585 bfd_vma add_to_offsets = 0;
17586
17587 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 17588 {
2468f9c9
PB		 17589 if (edit_node)
17590 {
17591 unsigned int edit_index = edit_node->index;
b38cadfb 17592
2468f9c9 17593 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 17594 {
2468f9c9
PB		 17595 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
17596 contents + in_index * 8, add_to_offsets);
17597 out_index++;
17598 in_index++;
17599 }
17600 else if (in_index == edit_index
17601 || (in_index * 8 >= input_size
17602 && edit_index == UINT_MAX))
99059e56 17603 {
2468f9c9
PB		 17604 switch (edit_node->type)
17605 {
17606 case DELETE_EXIDX_ENTRY:
17607 in_index++;
17608 add_to_offsets += 8;
17609 break;
b38cadfb 17610
2468f9c9
PB		 17611 case INSERT_EXIDX_CANTUNWIND_AT_END:
17612 {
99059e56 17613 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 17614 bfd_vma text_offset = text_sec->output_section->vma
17615 + text_sec->output_offset
17616 + text_sec->size;
17617 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 17618 unsigned long prel31_offset;
2468f9c9
PB		 17619
17620 /* Note: this is meant to be equivalent to an
17621 R_ARM_PREL31 relocation. These synthetic
17622 EXIDX_CANTUNWIND markers are not relocated by the
17623 usual BFD method. */
17624 prel31_offset = (text_offset - exidx_offset)
17625 & 0x7ffffffful;
491d01d3
YU		 17626 if (bfd_link_relocatable (link_info))
17627 {
17628 /* Here relocation for new EXIDX_CANTUNWIND is
17629 created, so there is no need to
17630 adjust offset by hand. */
17631 prel31_offset = text_sec->output_offset
17632 + text_sec->size;
17633
17634 /* New relocation entity. */
17635 asection *text_out = text_sec->output_section;
17636 Elf_Internal_Rela rel;
17637 rel.r_addend = 0;
17638 rel.r_offset = exidx_offset;
17639 rel.r_info = ELF32_R_INFO (text_out->target_index,
17640 R_ARM_PREL31);
17641
17642 elf32_arm_add_relocation (output_bfd, link_info,
17643 sec->output_section,
17644 &rel);
17645 }
2468f9c9
PB		 17646
17647 /* First address we can't unwind. */
17648 bfd_put_32 (output_bfd, prel31_offset,
17649 &edited_contents[out_index * 8]);
17650
17651 /* Code for EXIDX_CANTUNWIND. */
17652 bfd_put_32 (output_bfd, 0x1,
17653 &edited_contents[out_index * 8 + 4]);
17654
17655 out_index++;
17656 add_to_offsets -= 8;
17657 }
17658 break;
17659 }
b38cadfb 17660
2468f9c9
PB		 17661 edit_node = edit_node->next;
17662 }
17663 }
17664 else
17665 {
17666 /* No more edits, copy remaining entries verbatim. */
17667 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
17668 contents + in_index * 8, add_to_offsets);
17669 out_index++;
17670 in_index++;
17671 }
17672 }
17673
17674 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
17675 bfd_set_section_contents (output_bfd, sec->output_section,
17676 edited_contents,
17677 (file_ptr) sec->output_offset, sec->size);
17678
17679 return TRUE;
17680 }
17681
48229727
JB		 17682 /* Fix code to point to Cortex-A8 erratum stubs. */
17683 if (globals->fix_cortex_a8)
17684 {
17685 struct a8_branch_to_stub_data data;
17686
17687 data.writing_section = sec;
17688 data.contents = contents;
17689
a504d23a
LA		 17690 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
17691 & data);
48229727
JB		 17692 }
17693
e489d0ae
PB		 17694 if (mapcount == 0)
17695 return FALSE;
17696
c7b8f16e 17697 if (globals->byteswap_code)
e489d0ae 17698 {
c7b8f16e 17699 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 17700
c7b8f16e
JB		 17701 ptr = map[0].vma;
17702 for (i = 0; i < mapcount; i++)
99059e56
RM		 17703 {
17704 if (i == mapcount - 1)
c7b8f16e 17705 end = sec->size;
99059e56
RM		 17706 else
17707 end = map[i + 1].vma;
e489d0ae 17708
99059e56 17709 switch (map[i].type)
e489d0ae 17710 {
c7b8f16e
JB		 17711 case 'a':
17712 /* Byte swap code words. */
17713 while (ptr + 3 < end)
99059e56
RM		 17714 {
17715 tmp = contents[ptr];
17716 contents[ptr] = contents[ptr + 3];
17717 contents[ptr + 3] = tmp;
17718 tmp = contents[ptr + 1];
17719 contents[ptr + 1] = contents[ptr + 2];
17720 contents[ptr + 2] = tmp;
17721 ptr += 4;
17722 }
c7b8f16e 17723 break;
e489d0ae 17724
c7b8f16e
JB		 17725 case 't':
17726 /* Byte swap code halfwords. */
17727 while (ptr + 1 < end)
99059e56
RM		 17728 {
17729 tmp = contents[ptr];
17730 contents[ptr] = contents[ptr + 1];
17731 contents[ptr + 1] = tmp;
17732 ptr += 2;
17733 }
c7b8f16e
JB		 17734 break;
17735
17736 case 'd':
17737 /* Leave data alone. */
17738 break;
17739 }
99059e56
RM		 17740 ptr = end;
17741 }
e489d0ae 17742 }
8e3de13a 17743
93204d3a 17744 free (map);
47b2e99c 17745 arm_data->mapcount = -1;
c7b8f16e 17746 arm_data->mapsize = 0;
8e3de13a 17747 arm_data->map = NULL;
8e3de13a 17748
e489d0ae
PB		 17749 return FALSE;
17750}
17751
0beaef2b
PB		 17752/* Mangle thumb function symbols as we read them in. */
17753
8384fb8f 17754static bfd_boolean
0beaef2b
PB		 17755elf32_arm_swap_symbol_in (bfd * abfd,
17756 const void *psrc,
17757 const void *pshn,
17758 Elf_Internal_Sym *dst)
17759{
8384fb8f
AM		 17760 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
17761 return FALSE;
39d911fc 17762 dst->st_target_internal = 0;
0beaef2b
PB		 17763
17764 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 17765 the address. */
63e1a0fc
PB		 17766 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
17767 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 17768 {
63e1a0fc
PB		 17769 if (dst->st_value & 1)
17770 {
17771 dst->st_value &= ~(bfd_vma) 1;
39d911fc
TP		 17772 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
17773 ST_BRANCH_TO_THUMB);
63e1a0fc
PB		 17774 }
17775 else
39d911fc 17776 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
35fc36a8
RS		 17777 }
17778 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
17779 {
17780 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
39d911fc 17781 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
0beaef2b 17782 }
35fc36a8 17783 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
39d911fc 17784 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
35fc36a8 17785 else
39d911fc 17786 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
35fc36a8 17787
8384fb8f 17788 return TRUE;
0beaef2b
PB		 17789}
17790
17791
17792/* Mangle thumb function symbols as we write them out. */
17793
17794static void
17795elf32_arm_swap_symbol_out (bfd *abfd,
17796 const Elf_Internal_Sym *src,
17797 void *cdst,
17798 void *shndx)
17799{
17800 Elf_Internal_Sym newsym;
17801
17802 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
17803 of the address set, as per the new EABI. We do this unconditionally
17804 because objcopy does not set the elf header flags until after
17805 it writes out the symbol table. */
39d911fc 17806 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 17807 {
17808 newsym = *src;
34e77a92
RS		 17809 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
17810 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 17811 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 17812 {
17813 /* Do this only for defined symbols. At link type, the static
17814 linker will simulate the work of dynamic linker of resolving
17815 symbols and will carry over the thumbness of found symbols to
17816 the output symbol table. It's not clear how it happens, but
17817 the thumbness of undefined symbols can well be different at
17818 runtime, and writing '1' for them will be confusing for users
17819 and possibly for dynamic linker itself.
17820 */
17821 newsym.st_value |= 1;
17822 }
906e58ca 17823
0beaef2b
PB		 17824 src = &newsym;
17825 }
17826 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
17827}
17828
b294bdf8
MM		 17829/* Add the PT_ARM_EXIDX program header. */
17830
17831static bfd_boolean
906e58ca 17832elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 17833 struct bfd_link_info *info ATTRIBUTE_UNUSED)
17834{
17835 struct elf_segment_map *m;
17836 asection *sec;
17837
17838 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
17839 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
17840 {
17841 /* If there is already a PT_ARM_EXIDX header, then we do not
17842 want to add another one. This situation arises when running
17843 "strip"; the input binary already has the header. */
12bd6957 17844 m = elf_seg_map (abfd);
b294bdf8
MM		 17845 while (m && m->p_type != PT_ARM_EXIDX)
17846 m = m->next;
17847 if (!m)
17848 {
21d799b5 17849 m = (struct elf_segment_map *)
99059e56 17850 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 17851 if (m == NULL)
17852 return FALSE;
17853 m->p_type = PT_ARM_EXIDX;
17854 m->count = 1;
17855 m->sections[0] = sec;
17856
12bd6957
AM		 17857 m->next = elf_seg_map (abfd);
17858 elf_seg_map (abfd) = m;
b294bdf8
MM		 17859 }
17860 }
17861
17862 return TRUE;
17863}
17864
17865/* We may add a PT_ARM_EXIDX program header. */
17866
17867static int
a6b96beb
AM		 17868elf32_arm_additional_program_headers (bfd *abfd,
17869 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 17870{
17871 asection *sec;
17872
17873 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
17874 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
17875 return 1;
17876 else
17877 return 0;
17878}
17879
34e77a92
RS		 17880/* Hook called by the linker routine which adds symbols from an object
17881 file. */
17882
17883static bfd_boolean
17884elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
17885 Elf_Internal_Sym *sym, const char **namep,
17886 flagword *flagsp, asection **secp, bfd_vma *valp)
17887{
a43942db 17888 if (ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
f1885d1e
AM		 17889 && (abfd->flags & DYNAMIC) == 0
17890 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
a43942db 17891 elf_tdata (info->output_bfd)->has_gnu_symbols |= elf_gnu_symbol_ifunc;
34e77a92 17892
c792917c
NC		 17893 if (elf32_arm_hash_table (info) == NULL)
17894 return FALSE;
17895
34e77a92
RS		 17896 if (elf32_arm_hash_table (info)->vxworks_p
17897 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
17898 flagsp, secp, valp))
17899 return FALSE;
17900
17901 return TRUE;
17902}
17903
0beaef2b 17904/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 17905const struct elf_size_info elf32_arm_size_info =
17906{
0beaef2b
PB		 17907 sizeof (Elf32_External_Ehdr),
17908 sizeof (Elf32_External_Phdr),
17909 sizeof (Elf32_External_Shdr),
17910 sizeof (Elf32_External_Rel),
17911 sizeof (Elf32_External_Rela),
17912 sizeof (Elf32_External_Sym),
17913 sizeof (Elf32_External_Dyn),
17914 sizeof (Elf_External_Note),
17915 4,
17916 1,
17917 32, 2,
17918 ELFCLASS32, EV_CURRENT,
17919 bfd_elf32_write_out_phdrs,
17920 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 17921 bfd_elf32_checksum_contents,
0beaef2b
PB		 17922 bfd_elf32_write_relocs,
17923 elf32_arm_swap_symbol_in,
17924 elf32_arm_swap_symbol_out,
17925 bfd_elf32_slurp_reloc_table,
17926 bfd_elf32_slurp_symbol_table,
17927 bfd_elf32_swap_dyn_in,
17928 bfd_elf32_swap_dyn_out,
17929 bfd_elf32_swap_reloc_in,
17930 bfd_elf32_swap_reloc_out,
17931 bfd_elf32_swap_reloca_in,
17932 bfd_elf32_swap_reloca_out
17933};
17934
685e70ae
VK		 17935static bfd_vma
17936read_code32 (const bfd *abfd, const bfd_byte *addr)
17937{
17938 /* V7 BE8 code is always little endian. */
17939 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
17940 return bfd_getl32 (addr);
17941
17942 return bfd_get_32 (abfd, addr);
17943}
17944
17945static bfd_vma
17946read_code16 (const bfd *abfd, const bfd_byte *addr)
17947{
17948 /* V7 BE8 code is always little endian. */
17949 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
17950 return bfd_getl16 (addr);
17951
17952 return bfd_get_16 (abfd, addr);
17953}
17954
6a631e86
YG		 17955/* Return size of plt0 entry starting at ADDR
17956 or (bfd_vma) -1 if size can not be determined. */
17957
17958static bfd_vma
17959elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
17960{
17961 bfd_vma first_word;
17962 bfd_vma plt0_size;
17963
685e70ae 17964 first_word = read_code32 (abfd, addr);
6a631e86
YG		 17965
17966 if (first_word == elf32_arm_plt0_entry[0])
17967 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
17968 else if (first_word == elf32_thumb2_plt0_entry[0])
17969 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
17970 else
17971 /* We don't yet handle this PLT format. */
17972 return (bfd_vma) -1;
17973
17974 return plt0_size;
17975}
17976
17977/* Return size of plt entry starting at offset OFFSET
17978 of plt section located at address START
17979 or (bfd_vma) -1 if size can not be determined. */
17980
17981static bfd_vma
17982elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
17983{
17984 bfd_vma first_insn;
17985 bfd_vma plt_size = 0;
17986 const bfd_byte *addr = start + offset;
17987
17988 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 17989 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 17990 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
17991
17992 /* Respect Thumb stub if necessary. */
685e70ae 17993 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 17994 {
17995 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
17996 }
17997
17998 /* Strip immediate from first add. */
685e70ae 17999 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 18000
18001#ifdef FOUR_WORD_PLT
18002 if (first_insn == elf32_arm_plt_entry[0])
18003 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
18004#else
18005 if (first_insn == elf32_arm_plt_entry_long[0])
18006 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
18007 else if (first_insn == elf32_arm_plt_entry_short[0])
18008 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
18009#endif
18010 else
18011 /* We don't yet handle this PLT format. */
18012 return (bfd_vma) -1;
18013
18014 return plt_size;
18015}
18016
18017/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
18018
18019static long
18020elf32_arm_get_synthetic_symtab (bfd *abfd,
18021 long symcount ATTRIBUTE_UNUSED,
18022 asymbol **syms ATTRIBUTE_UNUSED,
18023 long dynsymcount,
18024 asymbol **dynsyms,
18025 asymbol **ret)
18026{
18027 asection *relplt;
18028 asymbol *s;
18029 arelent *p;
18030 long count, i, n;
18031 size_t size;
18032 Elf_Internal_Shdr *hdr;
18033 char *names;
18034 asection *plt;
18035 bfd_vma offset;
18036 bfd_byte *data;
18037
18038 *ret = NULL;
18039
18040 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
18041 return 0;
18042
18043 if (dynsymcount <= 0)
18044 return 0;
18045
18046 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
18047 if (relplt == NULL)
18048 return 0;
18049
18050 hdr = &elf_section_data (relplt)->this_hdr;
18051 if (hdr->sh_link != elf_dynsymtab (abfd)
18052 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
18053 return 0;
18054
18055 plt = bfd_get_section_by_name (abfd, ".plt");
18056 if (plt == NULL)
18057 return 0;
18058
18059 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
18060 return -1;
18061
18062 data = plt->contents;
18063 if (data == NULL)
18064 {
18065 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
18066 return -1;
18067 bfd_cache_section_contents((asection *) plt, data);
18068 }
18069
18070 count = relplt->size / hdr->sh_entsize;
18071 size = count * sizeof (asymbol);
18072 p = relplt->relocation;
18073 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
18074 {
18075 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
18076 if (p->addend != 0)
18077 size += sizeof ("+0x") - 1 + 8;
18078 }
18079
18080 s = *ret = (asymbol *) bfd_malloc (size);
18081 if (s == NULL)
18082 return -1;
18083
18084 offset = elf32_arm_plt0_size (abfd, data);
18085 if (offset == (bfd_vma) -1)
18086 return -1;
18087
18088 names = (char *) (s + count);
18089 p = relplt->relocation;
18090 n = 0;
18091 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
18092 {
18093 size_t len;
18094
18095 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
18096 if (plt_size == (bfd_vma) -1)
18097 break;
18098
18099 *s = **p->sym_ptr_ptr;
18100 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
18101 we are defining a symbol, ensure one of them is set. */
18102 if ((s->flags & BSF_LOCAL) == 0)
18103 s->flags |= BSF_GLOBAL;
18104 s->flags |= BSF_SYNTHETIC;
18105 s->section = plt;
18106 s->value = offset;
18107 s->name = names;
18108 s->udata.p = NULL;
18109 len = strlen ((*p->sym_ptr_ptr)->name);
18110 memcpy (names, (*p->sym_ptr_ptr)->name, len);
18111 names += len;
18112 if (p->addend != 0)
18113 {
18114 char buf[30], *a;
18115
18116 memcpy (names, "+0x", sizeof ("+0x") - 1);
18117 names += sizeof ("+0x") - 1;
18118 bfd_sprintf_vma (abfd, buf, p->addend);
18119 for (a = buf; *a == '0'; ++a)
18120 ;
18121 len = strlen (a);
18122 memcpy (names, a, len);
18123 names += len;
18124 }
18125 memcpy (names, "@plt", sizeof ("@plt"));
18126 names += sizeof ("@plt");
18127 ++s, ++n;
18128 offset += plt_size;
18129 }
18130
18131 return n;
18132}
18133
ac4c9b04
MG		 18134static bfd_boolean
18135elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
18136{
18137 if (hdr->sh_flags & SHF_ARM_NOREAD)
18138 *flags |= SEC_ELF_NOREAD;
18139 return TRUE;
18140}
18141
18142static flagword
18143elf32_arm_lookup_section_flags (char *flag_name)
18144{
18145 if (!strcmp (flag_name, "SHF_ARM_NOREAD"))
18146 return SHF_ARM_NOREAD;
18147
18148 return SEC_NO_FLAGS;
18149}
18150
491d01d3
YU		 18151static unsigned int
18152elf32_arm_count_additional_relocs (asection *sec)
18153{
18154 struct _arm_elf_section_data *arm_data;
18155 arm_data = get_arm_elf_section_data (sec);
18156 return arm_data->additional_reloc_count;
18157}
18158
5522f910
NC		 18159/* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
18160 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
18161 FALSE otherwise. ISECTION is the best guess matching section from the
18162 input bfd IBFD, but it might be NULL. */
18163
18164static bfd_boolean
18165elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
18166 bfd *obfd ATTRIBUTE_UNUSED,
18167 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
18168 Elf_Internal_Shdr *osection)
18169{
18170 switch (osection->sh_type)
18171 {
18172 case SHT_ARM_EXIDX:
18173 {
18174 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
18175 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
18176 unsigned i = 0;
18177
18178 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
18179 osection->sh_info = 0;
18180
18181 /* The sh_link field must be set to the text section associated with
18182 this index section. Unfortunately the ARM EHABI does not specify
18183 exactly how to determine this association. Our caller does try
18184 to match up OSECTION with its corresponding input section however
18185 so that is a good first guess. */
18186 if (isection != NULL
18187 && osection->bfd_section != NULL
18188 && isection->bfd_section != NULL
18189 && isection->bfd_section->output_section != NULL
18190 && isection->bfd_section->output_section == osection->bfd_section
18191 && iheaders != NULL
18192 && isection->sh_link > 0
18193 && isection->sh_link < elf_numsections (ibfd)
18194 && iheaders[isection->sh_link]->bfd_section != NULL
18195 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
18196 )
18197 {
18198 for (i = elf_numsections (obfd); i-- > 0;)
18199 if (oheaders[i]->bfd_section
18200 == iheaders[isection->sh_link]->bfd_section->output_section)
18201 break;
18202 }
18203
18204 if (i == 0)
18205 {
18206 /* Failing that we have to find a matching section ourselves. If
18207 we had the output section name available we could compare that
18208 with input section names. Unfortunately we don't. So instead
18209 we use a simple heuristic and look for the nearest executable
18210 section before this one. */
18211 for (i = elf_numsections (obfd); i-- > 0;)
18212 if (oheaders[i] == osection)
18213 break;
18214 if (i == 0)
18215 break;
18216
18217 while (i-- > 0)
18218 if (oheaders[i]->sh_type == SHT_PROGBITS
18219 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
18220 == (SHF_ALLOC | SHF_EXECINSTR))
18221 break;
18222 }
18223
18224 if (i)
18225 {
18226 osection->sh_link = i;
18227 /* If the text section was part of a group
18228 then the index section should be too. */
18229 if (oheaders[i]->sh_flags & SHF_GROUP)
18230 osection->sh_flags |= SHF_GROUP;
18231 return TRUE;
18232 }
18233 }
18234 break;
18235
18236 case SHT_ARM_PREEMPTMAP:
18237 osection->sh_flags = SHF_ALLOC;
18238 break;
18239
18240 case SHT_ARM_ATTRIBUTES:
18241 case SHT_ARM_DEBUGOVERLAY:
18242 case SHT_ARM_OVERLAYSECTION:
18243 default:
18244 break;
18245 }
18246
18247 return FALSE;
18248}
18249
18250#undef elf_backend_copy_special_section_fields
18251#define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
18252
252b5132 18253#define ELF_ARCH bfd_arch_arm
ae95ffa6 18254#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 18255#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 18256#ifdef __QNXTARGET__
18257#define ELF_MAXPAGESIZE 0x1000
18258#else
7572ca89 18259#define ELF_MAXPAGESIZE 0x10000
d0facd1b 18260#endif
b1342370 18261#define ELF_MINPAGESIZE 0x1000
24718e3b 18262#define ELF_COMMONPAGESIZE 0x1000
252b5132 18263
ba93b8ac
DJ		 18264#define bfd_elf32_mkobject elf32_arm_mkobject
18265
99e4ae17
AJ		 18266#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
18267#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 18268#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
18269#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
18270#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 18271#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 18272#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
252b5132 18273#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
4ab527b0 18274#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 18275#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 18276#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 18277#define bfd_elf32_bfd_final_link elf32_arm_final_link
6a631e86 18278#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132
RH		 18279
18280#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
18281#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 18282#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
252b5132
RH		 18283#define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
18284#define elf_backend_check_relocs elf32_arm_check_relocs
dc810e39 18285#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 18286#define elf_backend_write_section elf32_arm_write_section
252b5132 18287#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
5e681ec4 18288#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 18289#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
18290#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
18291#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 18292#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 18293#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 18294#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 18295#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 18296#define elf_backend_object_p elf32_arm_object_p
40a18ebd
NC		 18297#define elf_backend_fake_sections elf32_arm_fake_sections
18298#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
e16bb312 18299#define elf_backend_final_write_processing elf32_arm_final_write_processing
5e681ec4 18300#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 18301#define elf_backend_size_info elf32_arm_size_info
b294bdf8 18302#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
906e58ca
NC		 18303#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
18304#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
18305#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 18306#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 18307#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
906e58ca
NC		 18308
18309#define elf_backend_can_refcount 1
18310#define elf_backend_can_gc_sections 1
18311#define elf_backend_plt_readonly 1
18312#define elf_backend_want_got_plt 1
18313#define elf_backend_want_plt_sym 0
18314#define elf_backend_may_use_rel_p 1
18315#define elf_backend_may_use_rela_p 0
4e7fd91e 18316#define elf_backend_default_use_rela_p 0
252b5132 18317
04f7c78d 18318#define elf_backend_got_header_size 12
b68a20d6 18319#define elf_backend_extern_protected_data 1
04f7c78d 18320
906e58ca
NC		 18321#undef elf_backend_obj_attrs_vendor
18322#define elf_backend_obj_attrs_vendor "aeabi"
18323#undef elf_backend_obj_attrs_section
18324#define elf_backend_obj_attrs_section ".ARM.attributes"
18325#undef elf_backend_obj_attrs_arg_type
18326#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
18327#undef elf_backend_obj_attrs_section_type
104d59d1 18328#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb
NC		 18329#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
18330#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 18331
ac4c9b04
MG		 18332#undef elf_backend_section_flags
18333#define elf_backend_section_flags elf32_arm_section_flags
18334#undef elf_backend_lookup_section_flags_hook
18335#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
18336
252b5132 18337#include "elf32-target.h"
7f266840 18338
b38cadfb
NC		 18339/* Native Client targets. */
18340
18341#undef TARGET_LITTLE_SYM
6d00b590 18342#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 18343#undef TARGET_LITTLE_NAME
18344#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
18345#undef TARGET_BIG_SYM
6d00b590 18346#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 18347#undef TARGET_BIG_NAME
18348#define TARGET_BIG_NAME "elf32-bigarm-nacl"
18349
18350/* Like elf32_arm_link_hash_table_create -- but overrides
18351 appropriately for NaCl. */
18352
18353static struct bfd_link_hash_table *
18354elf32_arm_nacl_link_hash_table_create (bfd *abfd)
18355{
18356 struct bfd_link_hash_table *ret;
18357
18358 ret = elf32_arm_link_hash_table_create (abfd);
18359 if (ret)
18360 {
18361 struct elf32_arm_link_hash_table *htab
18362 = (struct elf32_arm_link_hash_table *) ret;
18363
18364 htab->nacl_p = 1;
18365
18366 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
18367 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
18368 }
18369 return ret;
18370}
18371
18372/* Since NaCl doesn't use the ARM-specific unwind format, we don't
18373 really need to use elf32_arm_modify_segment_map. But we do it
18374 anyway just to reduce gratuitous differences with the stock ARM backend. */
18375
18376static bfd_boolean
18377elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
18378{
18379 return (elf32_arm_modify_segment_map (abfd, info)
18380 && nacl_modify_segment_map (abfd, info));
18381}
18382
887badb3
RM		 18383static void
18384elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
18385{
18386 elf32_arm_final_write_processing (abfd, linker);
18387 nacl_final_write_processing (abfd, linker);
18388}
18389
6a631e86
YG		 18390static bfd_vma
18391elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
18392 const arelent *rel ATTRIBUTE_UNUSED)
18393{
18394 return plt->vma
18395 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
18396 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
18397}
887badb3 18398
b38cadfb 18399#undef elf32_bed
6a631e86 18400#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 18401#undef bfd_elf32_bfd_link_hash_table_create
18402#define bfd_elf32_bfd_link_hash_table_create \
18403 elf32_arm_nacl_link_hash_table_create
18404#undef elf_backend_plt_alignment
6a631e86 18405#define elf_backend_plt_alignment 4
b38cadfb
NC		 18406#undef elf_backend_modify_segment_map
18407#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
18408#undef elf_backend_modify_program_headers
18409#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 18410#undef elf_backend_final_write_processing
18411#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 18412#undef bfd_elf32_get_synthetic_symtab
18413#undef elf_backend_plt_sym_val
18414#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
5522f910 18415#undef elf_backend_copy_special_section_fields
b38cadfb 18416
887badb3
RM		 18417#undef ELF_MINPAGESIZE
18418#undef ELF_COMMONPAGESIZE
18419
b38cadfb
NC		 18420
18421#include "elf32-target.h"
18422
18423/* Reset to defaults. */
18424#undef elf_backend_plt_alignment
18425#undef elf_backend_modify_segment_map
18426#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
18427#undef elf_backend_modify_program_headers
887badb3
RM		 18428#undef elf_backend_final_write_processing
18429#define elf_backend_final_write_processing elf32_arm_final_write_processing
18430#undef ELF_MINPAGESIZE
18431#define ELF_MINPAGESIZE 0x1000
18432#undef ELF_COMMONPAGESIZE
18433#define ELF_COMMONPAGESIZE 0x1000
18434
b38cadfb 18435
906e58ca 18436/* VxWorks Targets. */
4e7fd91e 18437
906e58ca 18438#undef TARGET_LITTLE_SYM
6d00b590 18439#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
906e58ca 18440#undef TARGET_LITTLE_NAME
4e7fd91e 18441#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
906e58ca 18442#undef TARGET_BIG_SYM
6d00b590 18443#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
906e58ca 18444#undef TARGET_BIG_NAME
4e7fd91e
PB		 18445#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
18446
18447/* Like elf32_arm_link_hash_table_create -- but overrides
18448 appropriately for VxWorks. */
906e58ca 18449
4e7fd91e
PB		 18450static struct bfd_link_hash_table *
18451elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
18452{
18453 struct bfd_link_hash_table *ret;
18454
18455 ret = elf32_arm_link_hash_table_create (abfd);
18456 if (ret)
18457 {
18458 struct elf32_arm_link_hash_table *htab
00a97672 18459 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 18460 htab->use_rel = 0;
00a97672 18461 htab->vxworks_p = 1;
4e7fd91e
PB		 18462 }
18463 return ret;
906e58ca 18464}
4e7fd91e 18465
00a97672
RS		 18466static void
18467elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
18468{
18469 elf32_arm_final_write_processing (abfd, linker);
18470 elf_vxworks_final_write_processing (abfd, linker);
18471}
18472
906e58ca 18473#undef elf32_bed
4e7fd91e
PB		 18474#define elf32_bed elf32_arm_vxworks_bed
18475
906e58ca
NC		 18476#undef bfd_elf32_bfd_link_hash_table_create
18477#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 18478#undef elf_backend_final_write_processing
18479#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
18480#undef elf_backend_emit_relocs
18481#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 18482
906e58ca 18483#undef elf_backend_may_use_rel_p
00a97672 18484#define elf_backend_may_use_rel_p 0
906e58ca 18485#undef elf_backend_may_use_rela_p
00a97672 18486#define elf_backend_may_use_rela_p 1
906e58ca 18487#undef elf_backend_default_use_rela_p
00a97672 18488#define elf_backend_default_use_rela_p 1
906e58ca 18489#undef elf_backend_want_plt_sym
00a97672 18490#define elf_backend_want_plt_sym 1
906e58ca 18491#undef ELF_MAXPAGESIZE
00a97672 18492#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 18493
18494#include "elf32-target.h"
18495
18496
21d799b5
NC		 18497/* Merge backend specific data from an object file to the output
18498 object file when linking. */
18499
18500static bfd_boolean
18501elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
18502{
18503 flagword out_flags;
18504 flagword in_flags;
18505 bfd_boolean flags_compatible = TRUE;
18506 asection *sec;
18507
cc643b88 18508 /* Check if we have the same endianness. */
21d799b5
NC		 18509 if (! _bfd_generic_verify_endian_match (ibfd, obfd))
18510 return FALSE;
18511
18512 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
18513 return TRUE;
18514
18515 if (!elf32_arm_merge_eabi_attributes (ibfd, obfd))
18516 return FALSE;
18517
18518 /* The input BFD must have had its flags initialised. */
18519 /* The following seems bogus to me -- The flags are initialized in
18520 the assembler but I don't think an elf_flags_init field is
18521 written into the object. */
18522 /* BFD_ASSERT (elf_flags_init (ibfd)); */
18523
18524 in_flags = elf_elfheader (ibfd)->e_flags;
18525 out_flags = elf_elfheader (obfd)->e_flags;
18526
18527 /* In theory there is no reason why we couldn't handle this. However
18528 in practice it isn't even close to working and there is no real
18529 reason to want it. */
18530 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
18531 && !(ibfd->flags & DYNAMIC)
18532 && (in_flags & EF_ARM_BE8))
18533 {
18534 _bfd_error_handler (_("error: %B is already in final BE8 format"),
18535 ibfd);
18536 return FALSE;
18537 }
18538
18539 if (!elf_flags_init (obfd))
18540 {
18541 /* If the input is the default architecture and had the default
18542 flags then do not bother setting the flags for the output
18543 architecture, instead allow future merges to do this. If no
18544 future merges ever set these flags then they will retain their
99059e56
RM		 18545 uninitialised values, which surprise surprise, correspond
18546 to the default values. */
21d799b5
NC		 18547 if (bfd_get_arch_info (ibfd)->the_default
18548 && elf_elfheader (ibfd)->e_flags == 0)
18549 return TRUE;
18550
18551 elf_flags_init (obfd) = TRUE;
18552 elf_elfheader (obfd)->e_flags = in_flags;
18553
18554 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
18555 && bfd_get_arch_info (obfd)->the_default)
18556 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
18557
18558 return TRUE;
18559 }
18560
18561 /* Determine what should happen if the input ARM architecture
18562 does not match the output ARM architecture. */
18563 if (! bfd_arm_merge_machines (ibfd, obfd))
18564 return FALSE;
18565
18566 /* Identical flags must be compatible. */
18567 if (in_flags == out_flags)
18568 return TRUE;
18569
18570 /* Check to see if the input BFD actually contains any sections. If
18571 not, its flags may not have been initialised either, but it
18572 cannot actually cause any incompatiblity. Do not short-circuit
18573 dynamic objects; their section list may be emptied by
18574 elf_link_add_object_symbols.
18575
18576 Also check to see if there are no code sections in the input.
18577 In this case there is no need to check for code specific flags.
18578 XXX - do we need to worry about floating-point format compatability
18579 in data sections ? */
18580 if (!(ibfd->flags & DYNAMIC))
18581 {
18582 bfd_boolean null_input_bfd = TRUE;
18583 bfd_boolean only_data_sections = TRUE;
18584
18585 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
18586 {
18587 /* Ignore synthetic glue sections. */
18588 if (strcmp (sec->name, ".glue_7")
18589 && strcmp (sec->name, ".glue_7t"))
18590 {
18591 if ((bfd_get_section_flags (ibfd, sec)
18592 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
18593 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 18594 only_data_sections = FALSE;
21d799b5
NC		 18595
18596 null_input_bfd = FALSE;
18597 break;
18598 }
18599 }
18600
18601 if (null_input_bfd || only_data_sections)
18602 return TRUE;
18603 }
18604
18605 /* Complain about various flag mismatches. */
18606 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
18607 EF_ARM_EABI_VERSION (out_flags)))
18608 {
18609 _bfd_error_handler
18610 (_("error: Source object %B has EABI version %d, but target %B has EABI version %d"),
18611 ibfd, obfd,
18612 (in_flags & EF_ARM_EABIMASK) >> 24,
18613 (out_flags & EF_ARM_EABIMASK) >> 24);
18614 return FALSE;
18615 }
18616
18617 /* Not sure what needs to be checked for EABI versions >= 1. */
18618 /* VxWorks libraries do not use these flags. */
18619 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
18620 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
18621 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
18622 {
18623 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
18624 {
18625 _bfd_error_handler
18626 (_("error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"),
18627 ibfd, obfd,
18628 in_flags & EF_ARM_APCS_26 ? 26 : 32,
18629 out_flags & EF_ARM_APCS_26 ? 26 : 32);
18630 flags_compatible = FALSE;
18631 }
18632
18633 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
18634 {
18635 if (in_flags & EF_ARM_APCS_FLOAT)
18636 _bfd_error_handler
18637 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
18638 ibfd, obfd);
18639 else
18640 _bfd_error_handler
18641 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
18642 ibfd, obfd);
18643
18644 flags_compatible = FALSE;
18645 }
18646
18647 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
18648 {
18649 if (in_flags & EF_ARM_VFP_FLOAT)
18650 _bfd_error_handler
18651 (_("error: %B uses VFP instructions, whereas %B does not"),
18652 ibfd, obfd);
18653 else
18654 _bfd_error_handler
18655 (_("error: %B uses FPA instructions, whereas %B does not"),
18656 ibfd, obfd);
18657
18658 flags_compatible = FALSE;
18659 }
18660
18661 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
18662 {
18663 if (in_flags & EF_ARM_MAVERICK_FLOAT)
18664 _bfd_error_handler
18665 (_("error: %B uses Maverick instructions, whereas %B does not"),
18666 ibfd, obfd);
18667 else
18668 _bfd_error_handler
18669 (_("error: %B does not use Maverick instructions, whereas %B does"),
18670 ibfd, obfd);
18671
18672 flags_compatible = FALSE;
18673 }
18674
18675#ifdef EF_ARM_SOFT_FLOAT
18676 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
18677 {
18678 /* We can allow interworking between code that is VFP format
18679 layout, and uses either soft float or integer regs for
18680 passing floating point arguments and results. We already
18681 know that the APCS_FLOAT flags match; similarly for VFP
18682 flags. */
18683 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
18684 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
18685 {
18686 if (in_flags & EF_ARM_SOFT_FLOAT)
18687 _bfd_error_handler
18688 (_("error: %B uses software FP, whereas %B uses hardware FP"),
18689 ibfd, obfd);
18690 else
18691 _bfd_error_handler
18692 (_("error: %B uses hardware FP, whereas %B uses software FP"),
18693 ibfd, obfd);
18694
18695 flags_compatible = FALSE;
18696 }
18697 }
18698#endif
18699
18700 /* Interworking mismatch is only a warning. */
18701 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
18702 {
18703 if (in_flags & EF_ARM_INTERWORK)
18704 {
18705 _bfd_error_handler
18706 (_("Warning: %B supports interworking, whereas %B does not"),
18707 ibfd, obfd);
18708 }
18709 else
18710 {
18711 _bfd_error_handler
18712 (_("Warning: %B does not support interworking, whereas %B does"),
18713 ibfd, obfd);
18714 }
18715 }
18716 }
18717
18718 return flags_compatible;
18719}
18720
18721
906e58ca 18722/* Symbian OS Targets. */
7f266840 18723
906e58ca 18724#undef TARGET_LITTLE_SYM
6d00b590 18725#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
906e58ca 18726#undef TARGET_LITTLE_NAME
7f266840 18727#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
906e58ca 18728#undef TARGET_BIG_SYM
6d00b590 18729#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
906e58ca 18730#undef TARGET_BIG_NAME
7f266840
DJ		 18731#define TARGET_BIG_NAME "elf32-bigarm-symbian"
18732
18733/* Like elf32_arm_link_hash_table_create -- but overrides
18734 appropriately for Symbian OS. */
906e58ca 18735
7f266840
DJ		 18736static struct bfd_link_hash_table *
18737elf32_arm_symbian_link_hash_table_create (bfd *abfd)
18738{
18739 struct bfd_link_hash_table *ret;
18740
18741 ret = elf32_arm_link_hash_table_create (abfd);
18742 if (ret)
18743 {
18744 struct elf32_arm_link_hash_table *htab
18745 = (struct elf32_arm_link_hash_table *)ret;
18746 /* There is no PLT header for Symbian OS. */
18747 htab->plt_header_size = 0;
95720a86
DJ		 18748 /* The PLT entries are each one instruction and one word. */
18749 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 18750 htab->symbian_p = 1;
33bfe774
JB		 18751 /* Symbian uses armv5t or above, so use_blx is always true. */
18752 htab->use_blx = 1;
67687978 18753 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 18754 }
18755 return ret;
906e58ca 18756}
7f266840 18757
b35d266b 18758static const struct bfd_elf_special_section
551b43fd 18759elf32_arm_symbian_special_sections[] =
7f266840 18760{
5cd3778d
MM		 18761 /* In a BPABI executable, the dynamic linking sections do not go in
18762 the loadable read-only segment. The post-linker may wish to
18763 refer to these sections, but they are not part of the final
18764 program image. */
0112cd26
NC		 18765 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
18766 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
18767 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
18768 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
18769 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 18770 /* These sections do not need to be writable as the SymbianOS
18771 postlinker will arrange things so that no dynamic relocation is
18772 required. */
0112cd26
NC		 18773 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
18774 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
18775 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
18776 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 18777};
18778
c3c76620 18779static void
906e58ca 18780elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 18781 struct bfd_link_info *link_info)
c3c76620
MM		 18782{
18783 /* BPABI objects are never loaded directly by an OS kernel; they are
18784 processed by a postlinker first, into an OS-specific format. If
18785 the D_PAGED bit is set on the file, BFD will align segments on
18786 page boundaries, so that an OS can directly map the file. With
18787 BPABI objects, that just results in wasted space. In addition,
18788 because we clear the D_PAGED bit, map_sections_to_segments will
18789 recognize that the program headers should not be mapped into any
18790 loadable segment. */
18791 abfd->flags &= ~D_PAGED;
906e58ca 18792 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 18793}
7f266840
DJ		 18794
18795static bfd_boolean
906e58ca 18796elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 18797 struct bfd_link_info *info)
7f266840
DJ		 18798{
18799 struct elf_segment_map *m;
18800 asection *dynsec;
18801
7f266840
DJ		 18802 /* BPABI shared libraries and executables should have a PT_DYNAMIC
18803 segment. However, because the .dynamic section is not marked
18804 with SEC_LOAD, the generic ELF code will not create such a
18805 segment. */
18806 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
18807 if (dynsec)
18808 {
12bd6957 18809 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 18810 if (m->p_type == PT_DYNAMIC)
18811 break;
18812
18813 if (m == NULL)
18814 {
18815 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 18816 m->next = elf_seg_map (abfd);
18817 elf_seg_map (abfd) = m;
8ded5a0f 18818 }
7f266840
DJ		 18819 }
18820
b294bdf8
MM		 18821 /* Also call the generic arm routine. */
18822 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 18823}
18824
95720a86
DJ		 18825/* Return address for Ith PLT stub in section PLT, for relocation REL
18826 or (bfd_vma) -1 if it should not be included. */
18827
18828static bfd_vma
18829elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
18830 const arelent *rel ATTRIBUTE_UNUSED)
18831{
18832 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
18833}
18834
8029a119 18835#undef elf32_bed
7f266840
DJ		 18836#define elf32_bed elf32_arm_symbian_bed
18837
18838/* The dynamic sections are not allocated on SymbianOS; the postlinker
18839 will process them and then discard them. */
906e58ca 18840#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 18841#define ELF_DYNAMIC_SEC_FLAGS \
18842 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
18843
00a97672 18844#undef elf_backend_emit_relocs
c3c76620 18845
906e58ca
NC		 18846#undef bfd_elf32_bfd_link_hash_table_create
18847#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
18848#undef elf_backend_special_sections
18849#define elf_backend_special_sections elf32_arm_symbian_special_sections
18850#undef elf_backend_begin_write_processing
18851#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
18852#undef elf_backend_final_write_processing
18853#define elf_backend_final_write_processing elf32_arm_final_write_processing
18854
18855#undef elf_backend_modify_segment_map
7f266840
DJ		 18856#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
18857
18858/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 18859#undef elf_backend_got_header_size
7f266840
DJ		 18860#define elf_backend_got_header_size 0
18861
18862/* Similarly, there is no .got.plt section. */
906e58ca 18863#undef elf_backend_want_got_plt
7f266840
DJ		 18864#define elf_backend_want_got_plt 0
18865
906e58ca 18866#undef elf_backend_plt_sym_val
95720a86
DJ		 18867#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
18868
906e58ca 18869#undef elf_backend_may_use_rel_p
00a97672 18870#define elf_backend_may_use_rel_p 1
906e58ca 18871#undef elf_backend_may_use_rela_p
00a97672 18872#define elf_backend_may_use_rela_p 0
906e58ca 18873#undef elf_backend_default_use_rela_p
00a97672 18874#define elf_backend_default_use_rela_p 0
906e58ca 18875#undef elf_backend_want_plt_sym
00a97672 18876#define elf_backend_want_plt_sym 0
906e58ca 18877#undef ELF_MAXPAGESIZE
00a97672 18878#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 18879
7f266840 18880#include "elf32-target.h"
GDB Binutils - Deliverables
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