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Consolidate Thumb-1/Thumb-2 ISA detection
[deliverable/binutils-gdb.git] / bfd / elf32-arm.c
CommitLineData
252b5132 1/* 32-bit ELF support for ARM
b90efa5b 2 Copyright (C) 1998-2015 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
cd123cb7 8 the Free Software Foundation; either version 3 of the License, or
252b5132
RH		 9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
cd123cb7
NC		 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
252b5132 20
6e6718a3 21#include "sysdep.h"
2468f9c9
PB		 22#include <limits.h>
23
3db64b00 24#include "bfd.h"
6034aab8 25#include "bfd_stdint.h"
00a97672 26#include "libiberty.h"
7f266840
DJ		 27#include "libbfd.h"
28#include "elf-bfd.h"
b38cadfb 29#include "elf-nacl.h"
00a97672 30#include "elf-vxworks.h"
ee065d83 31#include "elf/arm.h"
7f266840 32
00a97672
RS		 33/* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35#define RELOC_SECTION(HTAB, NAME) \
36 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
37
38/* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40#define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
44
45/* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47#define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
51
52/* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54#define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
58
7f266840
DJ		 59#define elf_info_to_howto 0
60#define elf_info_to_howto_rel elf32_arm_info_to_howto
61
62#define ARM_ELF_ABI_VERSION 0
63#define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
64
79f08007
YZ		 65/* The Adjusted Place, as defined by AAELF. */
66#define Pa(X) ((X) & 0xfffffffc)
67
3e6b1042
DJ		 68static bfd_boolean elf32_arm_write_section (bfd *output_bfd,
69 struct bfd_link_info *link_info,
70 asection *sec,
71 bfd_byte *contents);
72
7f266840
DJ		 73/* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
76
c19d1205 77static reloc_howto_type elf32_arm_howto_table_1[] =
7f266840 78{
8029a119 79 /* No relocation. */
7f266840
DJ		 80 HOWTO (R_ARM_NONE, /* type */
81 0, /* rightshift */
6346d5ca 82 3, /* size (0 = byte, 1 = short, 2 = long) */
7f266840
DJ		 83 0, /* bitsize */
84 FALSE, /* pc_relative */
85 0, /* bitpos */
86 complain_overflow_dont,/* complain_on_overflow */
87 bfd_elf_generic_reloc, /* special_function */
88 "R_ARM_NONE", /* name */
89 FALSE, /* partial_inplace */
90 0, /* src_mask */
91 0, /* dst_mask */
92 FALSE), /* pcrel_offset */
93
94 HOWTO (R_ARM_PC24, /* type */
95 2, /* rightshift */
96 2, /* size (0 = byte, 1 = short, 2 = long) */
97 24, /* bitsize */
98 TRUE, /* pc_relative */
99 0, /* bitpos */
100 complain_overflow_signed,/* complain_on_overflow */
101 bfd_elf_generic_reloc, /* special_function */
102 "R_ARM_PC24", /* name */
103 FALSE, /* partial_inplace */
104 0x00ffffff, /* src_mask */
105 0x00ffffff, /* dst_mask */
106 TRUE), /* pcrel_offset */
107
108 /* 32 bit absolute */
109 HOWTO (R_ARM_ABS32, /* type */
110 0, /* rightshift */
111 2, /* size (0 = byte, 1 = short, 2 = long) */
112 32, /* bitsize */
113 FALSE, /* pc_relative */
114 0, /* bitpos */
115 complain_overflow_bitfield,/* complain_on_overflow */
116 bfd_elf_generic_reloc, /* special_function */
117 "R_ARM_ABS32", /* name */
118 FALSE, /* partial_inplace */
119 0xffffffff, /* src_mask */
120 0xffffffff, /* dst_mask */
121 FALSE), /* pcrel_offset */
122
123 /* standard 32bit pc-relative reloc */
124 HOWTO (R_ARM_REL32, /* type */
125 0, /* rightshift */
126 2, /* size (0 = byte, 1 = short, 2 = long) */
127 32, /* bitsize */
128 TRUE, /* pc_relative */
129 0, /* bitpos */
130 complain_overflow_bitfield,/* complain_on_overflow */
131 bfd_elf_generic_reloc, /* special_function */
132 "R_ARM_REL32", /* name */
133 FALSE, /* partial_inplace */
134 0xffffffff, /* src_mask */
135 0xffffffff, /* dst_mask */
136 TRUE), /* pcrel_offset */
137
c19d1205 138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
4962c51a 139 HOWTO (R_ARM_LDR_PC_G0, /* type */
7f266840
DJ		 140 0, /* rightshift */
141 0, /* size (0 = byte, 1 = short, 2 = long) */
4962c51a
MS		 142 32, /* bitsize */
143 TRUE, /* pc_relative */
7f266840 144 0, /* bitpos */
4962c51a 145 complain_overflow_dont,/* complain_on_overflow */
7f266840 146 bfd_elf_generic_reloc, /* special_function */
4962c51a 147 "R_ARM_LDR_PC_G0", /* name */
7f266840 148 FALSE, /* partial_inplace */
4962c51a
MS		 149 0xffffffff, /* src_mask */
150 0xffffffff, /* dst_mask */
151 TRUE), /* pcrel_offset */
7f266840
DJ		 152
153 /* 16 bit absolute */
154 HOWTO (R_ARM_ABS16, /* type */
155 0, /* rightshift */
156 1, /* size (0 = byte, 1 = short, 2 = long) */
157 16, /* bitsize */
158 FALSE, /* pc_relative */
159 0, /* bitpos */
160 complain_overflow_bitfield,/* complain_on_overflow */
161 bfd_elf_generic_reloc, /* special_function */
162 "R_ARM_ABS16", /* name */
163 FALSE, /* partial_inplace */
164 0x0000ffff, /* src_mask */
165 0x0000ffff, /* dst_mask */
166 FALSE), /* pcrel_offset */
167
168 /* 12 bit absolute */
169 HOWTO (R_ARM_ABS12, /* type */
170 0, /* rightshift */
171 2, /* size (0 = byte, 1 = short, 2 = long) */
172 12, /* bitsize */
173 FALSE, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield,/* complain_on_overflow */
176 bfd_elf_generic_reloc, /* special_function */
177 "R_ARM_ABS12", /* name */
178 FALSE, /* partial_inplace */
00a97672
RS		 179 0x00000fff, /* src_mask */
180 0x00000fff, /* dst_mask */
7f266840
DJ		 181 FALSE), /* pcrel_offset */
182
183 HOWTO (R_ARM_THM_ABS5, /* type */
184 6, /* rightshift */
185 1, /* size (0 = byte, 1 = short, 2 = long) */
186 5, /* bitsize */
187 FALSE, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield,/* complain_on_overflow */
190 bfd_elf_generic_reloc, /* special_function */
191 "R_ARM_THM_ABS5", /* name */
192 FALSE, /* partial_inplace */
193 0x000007e0, /* src_mask */
194 0x000007e0, /* dst_mask */
195 FALSE), /* pcrel_offset */
196
197 /* 8 bit absolute */
198 HOWTO (R_ARM_ABS8, /* type */
199 0, /* rightshift */
200 0, /* size (0 = byte, 1 = short, 2 = long) */
201 8, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_bitfield,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_ARM_ABS8", /* name */
207 FALSE, /* partial_inplace */
208 0x000000ff, /* src_mask */
209 0x000000ff, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_ARM_SBREL32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_dont,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_ARM_SBREL32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
c19d1205 226 HOWTO (R_ARM_THM_CALL, /* type */
7f266840
DJ		 227 1, /* rightshift */
228 2, /* size (0 = byte, 1 = short, 2 = long) */
f6ebfac0 229 24, /* bitsize */
7f266840
DJ		 230 TRUE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_signed,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
c19d1205 234 "R_ARM_THM_CALL", /* name */
7f266840 235 FALSE, /* partial_inplace */
7f6ab9f8
AM		 236 0x07ff2fff, /* src_mask */
237 0x07ff2fff, /* dst_mask */
7f266840
DJ		 238 TRUE), /* pcrel_offset */
239
240 HOWTO (R_ARM_THM_PC8, /* type */
241 1, /* rightshift */
242 1, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 TRUE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_signed,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_ARM_THM_PC8", /* name */
249 FALSE, /* partial_inplace */
250 0x000000ff, /* src_mask */
251 0x000000ff, /* dst_mask */
252 TRUE), /* pcrel_offset */
253
c19d1205 254 HOWTO (R_ARM_BREL_ADJ, /* type */
7f266840
DJ		 255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 257 32, /* bitsize */
258 FALSE, /* pc_relative */
7f266840
DJ		 259 0, /* bitpos */
260 complain_overflow_signed,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
c19d1205 262 "R_ARM_BREL_ADJ", /* name */
7f266840 263 FALSE, /* partial_inplace */
c19d1205
ZW		 264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 FALSE), /* pcrel_offset */
7f266840 267
0855e32b 268 HOWTO (R_ARM_TLS_DESC, /* type */
7f266840 269 0, /* rightshift */
0855e32b
NS		 270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
7f266840
DJ		 272 FALSE, /* pc_relative */
273 0, /* bitpos */
0855e32b 274 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 275 bfd_elf_generic_reloc, /* special_function */
0855e32b 276 "R_ARM_TLS_DESC", /* name */
7f266840 277 FALSE, /* partial_inplace */
0855e32b
NS		 278 0xffffffff, /* src_mask */
279 0xffffffff, /* dst_mask */
7f266840
DJ		 280 FALSE), /* pcrel_offset */
281
282 HOWTO (R_ARM_THM_SWI8, /* type */
283 0, /* rightshift */
284 0, /* size (0 = byte, 1 = short, 2 = long) */
285 0, /* bitsize */
286 FALSE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_signed,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_ARM_SWI8", /* name */
291 FALSE, /* partial_inplace */
292 0x00000000, /* src_mask */
293 0x00000000, /* dst_mask */
294 FALSE), /* pcrel_offset */
295
296 /* BLX instruction for the ARM. */
297 HOWTO (R_ARM_XPC25, /* type */
298 2, /* rightshift */
299 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 300 24, /* bitsize */
7f266840
DJ		 301 TRUE, /* pc_relative */
302 0, /* bitpos */
303 complain_overflow_signed,/* complain_on_overflow */
304 bfd_elf_generic_reloc, /* special_function */
305 "R_ARM_XPC25", /* name */
306 FALSE, /* partial_inplace */
307 0x00ffffff, /* src_mask */
308 0x00ffffff, /* dst_mask */
309 TRUE), /* pcrel_offset */
310
311 /* BLX instruction for the Thumb. */
312 HOWTO (R_ARM_THM_XPC22, /* type */
313 2, /* rightshift */
314 2, /* size (0 = byte, 1 = short, 2 = long) */
7f6ab9f8 315 24, /* bitsize */
7f266840
DJ		 316 TRUE, /* pc_relative */
317 0, /* bitpos */
318 complain_overflow_signed,/* complain_on_overflow */
319 bfd_elf_generic_reloc, /* special_function */
320 "R_ARM_THM_XPC22", /* name */
321 FALSE, /* partial_inplace */
7f6ab9f8
AM		 322 0x07ff2fff, /* src_mask */
323 0x07ff2fff, /* dst_mask */
7f266840
DJ		 324 TRUE), /* pcrel_offset */
325
ba93b8ac 326 /* Dynamic TLS relocations. */
7f266840 327
ba93b8ac 328 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
99059e56
RM		 329 0, /* rightshift */
330 2, /* size (0 = byte, 1 = short, 2 = long) */
331 32, /* bitsize */
332 FALSE, /* pc_relative */
333 0, /* bitpos */
334 complain_overflow_bitfield,/* complain_on_overflow */
335 bfd_elf_generic_reloc, /* special_function */
336 "R_ARM_TLS_DTPMOD32", /* name */
337 TRUE, /* partial_inplace */
338 0xffffffff, /* src_mask */
339 0xffffffff, /* dst_mask */
340 FALSE), /* pcrel_offset */
7f266840 341
ba93b8ac 342 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
99059e56
RM		 343 0, /* rightshift */
344 2, /* size (0 = byte, 1 = short, 2 = long) */
345 32, /* bitsize */
346 FALSE, /* pc_relative */
347 0, /* bitpos */
348 complain_overflow_bitfield,/* complain_on_overflow */
349 bfd_elf_generic_reloc, /* special_function */
350 "R_ARM_TLS_DTPOFF32", /* name */
351 TRUE, /* partial_inplace */
352 0xffffffff, /* src_mask */
353 0xffffffff, /* dst_mask */
354 FALSE), /* pcrel_offset */
7f266840 355
ba93b8ac 356 HOWTO (R_ARM_TLS_TPOFF32, /* type */
99059e56
RM		 357 0, /* rightshift */
358 2, /* size (0 = byte, 1 = short, 2 = long) */
359 32, /* bitsize */
360 FALSE, /* pc_relative */
361 0, /* bitpos */
362 complain_overflow_bitfield,/* complain_on_overflow */
363 bfd_elf_generic_reloc, /* special_function */
364 "R_ARM_TLS_TPOFF32", /* name */
365 TRUE, /* partial_inplace */
366 0xffffffff, /* src_mask */
367 0xffffffff, /* dst_mask */
368 FALSE), /* pcrel_offset */
7f266840
DJ		 369
370 /* Relocs used in ARM Linux */
371
372 HOWTO (R_ARM_COPY, /* type */
99059e56
RM		 373 0, /* rightshift */
374 2, /* size (0 = byte, 1 = short, 2 = long) */
375 32, /* bitsize */
376 FALSE, /* pc_relative */
377 0, /* bitpos */
378 complain_overflow_bitfield,/* complain_on_overflow */
379 bfd_elf_generic_reloc, /* special_function */
380 "R_ARM_COPY", /* name */
381 TRUE, /* partial_inplace */
382 0xffffffff, /* src_mask */
383 0xffffffff, /* dst_mask */
384 FALSE), /* pcrel_offset */
7f266840
DJ		 385
386 HOWTO (R_ARM_GLOB_DAT, /* type */
99059e56
RM		 387 0, /* rightshift */
388 2, /* size (0 = byte, 1 = short, 2 = long) */
389 32, /* bitsize */
390 FALSE, /* pc_relative */
391 0, /* bitpos */
392 complain_overflow_bitfield,/* complain_on_overflow */
393 bfd_elf_generic_reloc, /* special_function */
394 "R_ARM_GLOB_DAT", /* name */
395 TRUE, /* partial_inplace */
396 0xffffffff, /* src_mask */
397 0xffffffff, /* dst_mask */
398 FALSE), /* pcrel_offset */
7f266840
DJ		 399
400 HOWTO (R_ARM_JUMP_SLOT, /* type */
99059e56
RM		 401 0, /* rightshift */
402 2, /* size (0 = byte, 1 = short, 2 = long) */
403 32, /* bitsize */
404 FALSE, /* pc_relative */
405 0, /* bitpos */
406 complain_overflow_bitfield,/* complain_on_overflow */
407 bfd_elf_generic_reloc, /* special_function */
408 "R_ARM_JUMP_SLOT", /* name */
409 TRUE, /* partial_inplace */
410 0xffffffff, /* src_mask */
411 0xffffffff, /* dst_mask */
412 FALSE), /* pcrel_offset */
7f266840
DJ		 413
414 HOWTO (R_ARM_RELATIVE, /* type */
99059e56
RM		 415 0, /* rightshift */
416 2, /* size (0 = byte, 1 = short, 2 = long) */
417 32, /* bitsize */
418 FALSE, /* pc_relative */
419 0, /* bitpos */
420 complain_overflow_bitfield,/* complain_on_overflow */
421 bfd_elf_generic_reloc, /* special_function */
422 "R_ARM_RELATIVE", /* name */
423 TRUE, /* partial_inplace */
424 0xffffffff, /* src_mask */
425 0xffffffff, /* dst_mask */
426 FALSE), /* pcrel_offset */
7f266840 427
c19d1205 428 HOWTO (R_ARM_GOTOFF32, /* type */
99059e56
RM		 429 0, /* rightshift */
430 2, /* size (0 = byte, 1 = short, 2 = long) */
431 32, /* bitsize */
432 FALSE, /* pc_relative */
433 0, /* bitpos */
434 complain_overflow_bitfield,/* complain_on_overflow */
435 bfd_elf_generic_reloc, /* special_function */
436 "R_ARM_GOTOFF32", /* name */
437 TRUE, /* partial_inplace */
438 0xffffffff, /* src_mask */
439 0xffffffff, /* dst_mask */
440 FALSE), /* pcrel_offset */
7f266840
DJ		 441
442 HOWTO (R_ARM_GOTPC, /* type */
99059e56
RM		 443 0, /* rightshift */
444 2, /* size (0 = byte, 1 = short, 2 = long) */
445 32, /* bitsize */
446 TRUE, /* pc_relative */
447 0, /* bitpos */
448 complain_overflow_bitfield,/* complain_on_overflow */
449 bfd_elf_generic_reloc, /* special_function */
450 "R_ARM_GOTPC", /* name */
451 TRUE, /* partial_inplace */
452 0xffffffff, /* src_mask */
453 0xffffffff, /* dst_mask */
454 TRUE), /* pcrel_offset */
7f266840
DJ		 455
456 HOWTO (R_ARM_GOT32, /* type */
99059e56
RM		 457 0, /* rightshift */
458 2, /* size (0 = byte, 1 = short, 2 = long) */
459 32, /* bitsize */
460 FALSE, /* pc_relative */
461 0, /* bitpos */
462 complain_overflow_bitfield,/* complain_on_overflow */
463 bfd_elf_generic_reloc, /* special_function */
464 "R_ARM_GOT32", /* name */
465 TRUE, /* partial_inplace */
466 0xffffffff, /* src_mask */
467 0xffffffff, /* dst_mask */
468 FALSE), /* pcrel_offset */
7f266840
DJ		 469
470 HOWTO (R_ARM_PLT32, /* type */
99059e56
RM		 471 2, /* rightshift */
472 2, /* size (0 = byte, 1 = short, 2 = long) */
473 24, /* bitsize */
474 TRUE, /* pc_relative */
475 0, /* bitpos */
476 complain_overflow_bitfield,/* complain_on_overflow */
477 bfd_elf_generic_reloc, /* special_function */
478 "R_ARM_PLT32", /* name */
479 FALSE, /* partial_inplace */
480 0x00ffffff, /* src_mask */
481 0x00ffffff, /* dst_mask */
482 TRUE), /* pcrel_offset */
7f266840
DJ		 483
484 HOWTO (R_ARM_CALL, /* type */
485 2, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 24, /* bitsize */
488 TRUE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_signed,/* complain_on_overflow */
491 bfd_elf_generic_reloc, /* special_function */
492 "R_ARM_CALL", /* name */
493 FALSE, /* partial_inplace */
494 0x00ffffff, /* src_mask */
495 0x00ffffff, /* dst_mask */
496 TRUE), /* pcrel_offset */
497
498 HOWTO (R_ARM_JUMP24, /* type */
499 2, /* rightshift */
500 2, /* size (0 = byte, 1 = short, 2 = long) */
501 24, /* bitsize */
502 TRUE, /* pc_relative */
503 0, /* bitpos */
504 complain_overflow_signed,/* complain_on_overflow */
505 bfd_elf_generic_reloc, /* special_function */
506 "R_ARM_JUMP24", /* name */
507 FALSE, /* partial_inplace */
508 0x00ffffff, /* src_mask */
509 0x00ffffff, /* dst_mask */
510 TRUE), /* pcrel_offset */
511
c19d1205
ZW		 512 HOWTO (R_ARM_THM_JUMP24, /* type */
513 1, /* rightshift */
514 2, /* size (0 = byte, 1 = short, 2 = long) */
515 24, /* bitsize */
516 TRUE, /* pc_relative */
7f266840 517 0, /* bitpos */
c19d1205 518 complain_overflow_signed,/* complain_on_overflow */
7f266840 519 bfd_elf_generic_reloc, /* special_function */
c19d1205 520 "R_ARM_THM_JUMP24", /* name */
7f266840 521 FALSE, /* partial_inplace */
c19d1205
ZW		 522 0x07ff2fff, /* src_mask */
523 0x07ff2fff, /* dst_mask */
524 TRUE), /* pcrel_offset */
7f266840 525
c19d1205 526 HOWTO (R_ARM_BASE_ABS, /* type */
7f266840 527 0, /* rightshift */
c19d1205
ZW		 528 2, /* size (0 = byte, 1 = short, 2 = long) */
529 32, /* bitsize */
7f266840
DJ		 530 FALSE, /* pc_relative */
531 0, /* bitpos */
532 complain_overflow_dont,/* complain_on_overflow */
533 bfd_elf_generic_reloc, /* special_function */
c19d1205 534 "R_ARM_BASE_ABS", /* name */
7f266840 535 FALSE, /* partial_inplace */
c19d1205
ZW		 536 0xffffffff, /* src_mask */
537 0xffffffff, /* dst_mask */
7f266840
DJ		 538 FALSE), /* pcrel_offset */
539
540 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
541 0, /* rightshift */
542 2, /* size (0 = byte, 1 = short, 2 = long) */
543 12, /* bitsize */
544 TRUE, /* pc_relative */
545 0, /* bitpos */
546 complain_overflow_dont,/* complain_on_overflow */
547 bfd_elf_generic_reloc, /* special_function */
548 "R_ARM_ALU_PCREL_7_0", /* name */
549 FALSE, /* partial_inplace */
550 0x00000fff, /* src_mask */
551 0x00000fff, /* dst_mask */
552 TRUE), /* pcrel_offset */
553
554 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
555 0, /* rightshift */
556 2, /* size (0 = byte, 1 = short, 2 = long) */
557 12, /* bitsize */
558 TRUE, /* pc_relative */
559 8, /* bitpos */
560 complain_overflow_dont,/* complain_on_overflow */
561 bfd_elf_generic_reloc, /* special_function */
562 "R_ARM_ALU_PCREL_15_8",/* name */
563 FALSE, /* partial_inplace */
564 0x00000fff, /* src_mask */
565 0x00000fff, /* dst_mask */
566 TRUE), /* pcrel_offset */
567
568 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
569 0, /* rightshift */
570 2, /* size (0 = byte, 1 = short, 2 = long) */
571 12, /* bitsize */
572 TRUE, /* pc_relative */
573 16, /* bitpos */
574 complain_overflow_dont,/* complain_on_overflow */
575 bfd_elf_generic_reloc, /* special_function */
576 "R_ARM_ALU_PCREL_23_15",/* name */
577 FALSE, /* partial_inplace */
578 0x00000fff, /* src_mask */
579 0x00000fff, /* dst_mask */
580 TRUE), /* pcrel_offset */
581
582 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
583 0, /* rightshift */
584 2, /* size (0 = byte, 1 = short, 2 = long) */
585 12, /* bitsize */
586 FALSE, /* pc_relative */
587 0, /* bitpos */
588 complain_overflow_dont,/* complain_on_overflow */
589 bfd_elf_generic_reloc, /* special_function */
590 "R_ARM_LDR_SBREL_11_0",/* name */
591 FALSE, /* partial_inplace */
592 0x00000fff, /* src_mask */
593 0x00000fff, /* dst_mask */
594 FALSE), /* pcrel_offset */
595
596 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
597 0, /* rightshift */
598 2, /* size (0 = byte, 1 = short, 2 = long) */
599 8, /* bitsize */
600 FALSE, /* pc_relative */
601 12, /* bitpos */
602 complain_overflow_dont,/* complain_on_overflow */
603 bfd_elf_generic_reloc, /* special_function */
604 "R_ARM_ALU_SBREL_19_12",/* name */
605 FALSE, /* partial_inplace */
606 0x000ff000, /* src_mask */
607 0x000ff000, /* dst_mask */
608 FALSE), /* pcrel_offset */
609
610 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
611 0, /* rightshift */
612 2, /* size (0 = byte, 1 = short, 2 = long) */
613 8, /* bitsize */
614 FALSE, /* pc_relative */
615 20, /* bitpos */
616 complain_overflow_dont,/* complain_on_overflow */
617 bfd_elf_generic_reloc, /* special_function */
618 "R_ARM_ALU_SBREL_27_20",/* name */
619 FALSE, /* partial_inplace */
620 0x0ff00000, /* src_mask */
621 0x0ff00000, /* dst_mask */
622 FALSE), /* pcrel_offset */
623
624 HOWTO (R_ARM_TARGET1, /* type */
625 0, /* rightshift */
626 2, /* size (0 = byte, 1 = short, 2 = long) */
627 32, /* bitsize */
628 FALSE, /* pc_relative */
629 0, /* bitpos */
630 complain_overflow_dont,/* complain_on_overflow */
631 bfd_elf_generic_reloc, /* special_function */
632 "R_ARM_TARGET1", /* name */
633 FALSE, /* partial_inplace */
634 0xffffffff, /* src_mask */
635 0xffffffff, /* dst_mask */
636 FALSE), /* pcrel_offset */
637
638 HOWTO (R_ARM_ROSEGREL32, /* type */
639 0, /* rightshift */
640 2, /* size (0 = byte, 1 = short, 2 = long) */
641 32, /* bitsize */
642 FALSE, /* pc_relative */
643 0, /* bitpos */
644 complain_overflow_dont,/* complain_on_overflow */
645 bfd_elf_generic_reloc, /* special_function */
646 "R_ARM_ROSEGREL32", /* name */
647 FALSE, /* partial_inplace */
648 0xffffffff, /* src_mask */
649 0xffffffff, /* dst_mask */
650 FALSE), /* pcrel_offset */
651
652 HOWTO (R_ARM_V4BX, /* type */
653 0, /* rightshift */
654 2, /* size (0 = byte, 1 = short, 2 = long) */
655 32, /* bitsize */
656 FALSE, /* pc_relative */
657 0, /* bitpos */
658 complain_overflow_dont,/* complain_on_overflow */
659 bfd_elf_generic_reloc, /* special_function */
660 "R_ARM_V4BX", /* name */
661 FALSE, /* partial_inplace */
662 0xffffffff, /* src_mask */
663 0xffffffff, /* dst_mask */
664 FALSE), /* pcrel_offset */
665
666 HOWTO (R_ARM_TARGET2, /* type */
667 0, /* rightshift */
668 2, /* size (0 = byte, 1 = short, 2 = long) */
669 32, /* bitsize */
670 FALSE, /* pc_relative */
671 0, /* bitpos */
672 complain_overflow_signed,/* complain_on_overflow */
673 bfd_elf_generic_reloc, /* special_function */
674 "R_ARM_TARGET2", /* name */
675 FALSE, /* partial_inplace */
676 0xffffffff, /* src_mask */
677 0xffffffff, /* dst_mask */
678 TRUE), /* pcrel_offset */
679
680 HOWTO (R_ARM_PREL31, /* type */
681 0, /* rightshift */
682 2, /* size (0 = byte, 1 = short, 2 = long) */
683 31, /* bitsize */
684 TRUE, /* pc_relative */
685 0, /* bitpos */
686 complain_overflow_signed,/* complain_on_overflow */
687 bfd_elf_generic_reloc, /* special_function */
688 "R_ARM_PREL31", /* name */
689 FALSE, /* partial_inplace */
690 0x7fffffff, /* src_mask */
691 0x7fffffff, /* dst_mask */
692 TRUE), /* pcrel_offset */
c19d1205
ZW		 693
694 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
695 0, /* rightshift */
696 2, /* size (0 = byte, 1 = short, 2 = long) */
697 16, /* bitsize */
698 FALSE, /* pc_relative */
699 0, /* bitpos */
700 complain_overflow_dont,/* complain_on_overflow */
701 bfd_elf_generic_reloc, /* special_function */
702 "R_ARM_MOVW_ABS_NC", /* name */
703 FALSE, /* partial_inplace */
39623e12
PB		 704 0x000f0fff, /* src_mask */
705 0x000f0fff, /* dst_mask */
c19d1205
ZW		 706 FALSE), /* pcrel_offset */
707
708 HOWTO (R_ARM_MOVT_ABS, /* type */
709 0, /* rightshift */
710 2, /* size (0 = byte, 1 = short, 2 = long) */
711 16, /* bitsize */
712 FALSE, /* pc_relative */
713 0, /* bitpos */
714 complain_overflow_bitfield,/* complain_on_overflow */
715 bfd_elf_generic_reloc, /* special_function */
716 "R_ARM_MOVT_ABS", /* name */
717 FALSE, /* partial_inplace */
39623e12
PB		 718 0x000f0fff, /* src_mask */
719 0x000f0fff, /* dst_mask */
c19d1205
ZW		 720 FALSE), /* pcrel_offset */
721
722 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
723 0, /* rightshift */
724 2, /* size (0 = byte, 1 = short, 2 = long) */
725 16, /* bitsize */
726 TRUE, /* pc_relative */
727 0, /* bitpos */
728 complain_overflow_dont,/* complain_on_overflow */
729 bfd_elf_generic_reloc, /* special_function */
730 "R_ARM_MOVW_PREL_NC", /* name */
731 FALSE, /* partial_inplace */
39623e12
PB		 732 0x000f0fff, /* src_mask */
733 0x000f0fff, /* dst_mask */
c19d1205
ZW		 734 TRUE), /* pcrel_offset */
735
736 HOWTO (R_ARM_MOVT_PREL, /* type */
737 0, /* rightshift */
738 2, /* size (0 = byte, 1 = short, 2 = long) */
739 16, /* bitsize */
740 TRUE, /* pc_relative */
741 0, /* bitpos */
742 complain_overflow_bitfield,/* complain_on_overflow */
743 bfd_elf_generic_reloc, /* special_function */
744 "R_ARM_MOVT_PREL", /* name */
745 FALSE, /* partial_inplace */
39623e12
PB		 746 0x000f0fff, /* src_mask */
747 0x000f0fff, /* dst_mask */
c19d1205
ZW		 748 TRUE), /* pcrel_offset */
749
750 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
751 0, /* rightshift */
752 2, /* size (0 = byte, 1 = short, 2 = long) */
753 16, /* bitsize */
754 FALSE, /* pc_relative */
755 0, /* bitpos */
756 complain_overflow_dont,/* complain_on_overflow */
757 bfd_elf_generic_reloc, /* special_function */
758 "R_ARM_THM_MOVW_ABS_NC",/* name */
759 FALSE, /* partial_inplace */
760 0x040f70ff, /* src_mask */
761 0x040f70ff, /* dst_mask */
762 FALSE), /* pcrel_offset */
763
764 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
765 0, /* rightshift */
766 2, /* size (0 = byte, 1 = short, 2 = long) */
767 16, /* bitsize */
768 FALSE, /* pc_relative */
769 0, /* bitpos */
770 complain_overflow_bitfield,/* complain_on_overflow */
771 bfd_elf_generic_reloc, /* special_function */
772 "R_ARM_THM_MOVT_ABS", /* name */
773 FALSE, /* partial_inplace */
774 0x040f70ff, /* src_mask */
775 0x040f70ff, /* dst_mask */
776 FALSE), /* pcrel_offset */
777
778 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
779 0, /* rightshift */
780 2, /* size (0 = byte, 1 = short, 2 = long) */
781 16, /* bitsize */
782 TRUE, /* pc_relative */
783 0, /* bitpos */
784 complain_overflow_dont,/* complain_on_overflow */
785 bfd_elf_generic_reloc, /* special_function */
786 "R_ARM_THM_MOVW_PREL_NC",/* name */
787 FALSE, /* partial_inplace */
788 0x040f70ff, /* src_mask */
789 0x040f70ff, /* dst_mask */
790 TRUE), /* pcrel_offset */
791
792 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
793 0, /* rightshift */
794 2, /* size (0 = byte, 1 = short, 2 = long) */
795 16, /* bitsize */
796 TRUE, /* pc_relative */
797 0, /* bitpos */
798 complain_overflow_bitfield,/* complain_on_overflow */
799 bfd_elf_generic_reloc, /* special_function */
800 "R_ARM_THM_MOVT_PREL", /* name */
801 FALSE, /* partial_inplace */
802 0x040f70ff, /* src_mask */
803 0x040f70ff, /* dst_mask */
804 TRUE), /* pcrel_offset */
805
806 HOWTO (R_ARM_THM_JUMP19, /* type */
807 1, /* rightshift */
808 2, /* size (0 = byte, 1 = short, 2 = long) */
809 19, /* bitsize */
810 TRUE, /* pc_relative */
811 0, /* bitpos */
812 complain_overflow_signed,/* complain_on_overflow */
813 bfd_elf_generic_reloc, /* special_function */
814 "R_ARM_THM_JUMP19", /* name */
815 FALSE, /* partial_inplace */
816 0x043f2fff, /* src_mask */
817 0x043f2fff, /* dst_mask */
818 TRUE), /* pcrel_offset */
819
820 HOWTO (R_ARM_THM_JUMP6, /* type */
821 1, /* rightshift */
822 1, /* size (0 = byte, 1 = short, 2 = long) */
823 6, /* bitsize */
824 TRUE, /* pc_relative */
825 0, /* bitpos */
826 complain_overflow_unsigned,/* complain_on_overflow */
827 bfd_elf_generic_reloc, /* special_function */
828 "R_ARM_THM_JUMP6", /* name */
829 FALSE, /* partial_inplace */
830 0x02f8, /* src_mask */
831 0x02f8, /* dst_mask */
832 TRUE), /* pcrel_offset */
833
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
837 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
838 0, /* rightshift */
839 2, /* size (0 = byte, 1 = short, 2 = long) */
840 13, /* bitsize */
841 TRUE, /* pc_relative */
842 0, /* bitpos */
2cab6cc3 843 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 844 bfd_elf_generic_reloc, /* special_function */
845 "R_ARM_THM_ALU_PREL_11_0",/* name */
846 FALSE, /* partial_inplace */
2cab6cc3
MS		 847 0xffffffff, /* src_mask */
848 0xffffffff, /* dst_mask */
c19d1205
ZW		 849 TRUE), /* pcrel_offset */
850
851 HOWTO (R_ARM_THM_PC12, /* type */
852 0, /* rightshift */
853 2, /* size (0 = byte, 1 = short, 2 = long) */
854 13, /* bitsize */
855 TRUE, /* pc_relative */
856 0, /* bitpos */
2cab6cc3 857 complain_overflow_dont,/* complain_on_overflow */
c19d1205
ZW		 858 bfd_elf_generic_reloc, /* special_function */
859 "R_ARM_THM_PC12", /* name */
860 FALSE, /* partial_inplace */
2cab6cc3
MS		 861 0xffffffff, /* src_mask */
862 0xffffffff, /* dst_mask */
c19d1205
ZW		 863 TRUE), /* pcrel_offset */
864
865 HOWTO (R_ARM_ABS32_NOI, /* type */
866 0, /* rightshift */
867 2, /* size (0 = byte, 1 = short, 2 = long) */
868 32, /* bitsize */
869 FALSE, /* pc_relative */
870 0, /* bitpos */
871 complain_overflow_dont,/* complain_on_overflow */
872 bfd_elf_generic_reloc, /* special_function */
873 "R_ARM_ABS32_NOI", /* name */
874 FALSE, /* partial_inplace */
875 0xffffffff, /* src_mask */
876 0xffffffff, /* dst_mask */
877 FALSE), /* pcrel_offset */
878
879 HOWTO (R_ARM_REL32_NOI, /* type */
880 0, /* rightshift */
881 2, /* size (0 = byte, 1 = short, 2 = long) */
882 32, /* bitsize */
883 TRUE, /* pc_relative */
884 0, /* bitpos */
885 complain_overflow_dont,/* complain_on_overflow */
886 bfd_elf_generic_reloc, /* special_function */
887 "R_ARM_REL32_NOI", /* name */
888 FALSE, /* partial_inplace */
889 0xffffffff, /* src_mask */
890 0xffffffff, /* dst_mask */
891 FALSE), /* pcrel_offset */
7f266840 892
4962c51a
MS		 893 /* Group relocations. */
894
895 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
896 0, /* rightshift */
897 2, /* size (0 = byte, 1 = short, 2 = long) */
898 32, /* bitsize */
899 TRUE, /* pc_relative */
900 0, /* bitpos */
901 complain_overflow_dont,/* complain_on_overflow */
902 bfd_elf_generic_reloc, /* special_function */
903 "R_ARM_ALU_PC_G0_NC", /* name */
904 FALSE, /* partial_inplace */
905 0xffffffff, /* src_mask */
906 0xffffffff, /* dst_mask */
907 TRUE), /* pcrel_offset */
908
909 HOWTO (R_ARM_ALU_PC_G0, /* type */
910 0, /* rightshift */
911 2, /* size (0 = byte, 1 = short, 2 = long) */
912 32, /* bitsize */
913 TRUE, /* pc_relative */
914 0, /* bitpos */
915 complain_overflow_dont,/* complain_on_overflow */
916 bfd_elf_generic_reloc, /* special_function */
917 "R_ARM_ALU_PC_G0", /* name */
918 FALSE, /* partial_inplace */
919 0xffffffff, /* src_mask */
920 0xffffffff, /* dst_mask */
921 TRUE), /* pcrel_offset */
922
923 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
924 0, /* rightshift */
925 2, /* size (0 = byte, 1 = short, 2 = long) */
926 32, /* bitsize */
927 TRUE, /* pc_relative */
928 0, /* bitpos */
929 complain_overflow_dont,/* complain_on_overflow */
930 bfd_elf_generic_reloc, /* special_function */
931 "R_ARM_ALU_PC_G1_NC", /* name */
932 FALSE, /* partial_inplace */
933 0xffffffff, /* src_mask */
934 0xffffffff, /* dst_mask */
935 TRUE), /* pcrel_offset */
936
937 HOWTO (R_ARM_ALU_PC_G1, /* type */
938 0, /* rightshift */
939 2, /* size (0 = byte, 1 = short, 2 = long) */
940 32, /* bitsize */
941 TRUE, /* pc_relative */
942 0, /* bitpos */
943 complain_overflow_dont,/* complain_on_overflow */
944 bfd_elf_generic_reloc, /* special_function */
945 "R_ARM_ALU_PC_G1", /* name */
946 FALSE, /* partial_inplace */
947 0xffffffff, /* src_mask */
948 0xffffffff, /* dst_mask */
949 TRUE), /* pcrel_offset */
950
951 HOWTO (R_ARM_ALU_PC_G2, /* type */
952 0, /* rightshift */
953 2, /* size (0 = byte, 1 = short, 2 = long) */
954 32, /* bitsize */
955 TRUE, /* pc_relative */
956 0, /* bitpos */
957 complain_overflow_dont,/* complain_on_overflow */
958 bfd_elf_generic_reloc, /* special_function */
959 "R_ARM_ALU_PC_G2", /* name */
960 FALSE, /* partial_inplace */
961 0xffffffff, /* src_mask */
962 0xffffffff, /* dst_mask */
963 TRUE), /* pcrel_offset */
964
965 HOWTO (R_ARM_LDR_PC_G1, /* type */
966 0, /* rightshift */
967 2, /* size (0 = byte, 1 = short, 2 = long) */
968 32, /* bitsize */
969 TRUE, /* pc_relative */
970 0, /* bitpos */
971 complain_overflow_dont,/* complain_on_overflow */
972 bfd_elf_generic_reloc, /* special_function */
973 "R_ARM_LDR_PC_G1", /* name */
974 FALSE, /* partial_inplace */
975 0xffffffff, /* src_mask */
976 0xffffffff, /* dst_mask */
977 TRUE), /* pcrel_offset */
978
979 HOWTO (R_ARM_LDR_PC_G2, /* type */
980 0, /* rightshift */
981 2, /* size (0 = byte, 1 = short, 2 = long) */
982 32, /* bitsize */
983 TRUE, /* pc_relative */
984 0, /* bitpos */
985 complain_overflow_dont,/* complain_on_overflow */
986 bfd_elf_generic_reloc, /* special_function */
987 "R_ARM_LDR_PC_G2", /* name */
988 FALSE, /* partial_inplace */
989 0xffffffff, /* src_mask */
990 0xffffffff, /* dst_mask */
991 TRUE), /* pcrel_offset */
992
993 HOWTO (R_ARM_LDRS_PC_G0, /* type */
994 0, /* rightshift */
995 2, /* size (0 = byte, 1 = short, 2 = long) */
996 32, /* bitsize */
997 TRUE, /* pc_relative */
998 0, /* bitpos */
999 complain_overflow_dont,/* complain_on_overflow */
1000 bfd_elf_generic_reloc, /* special_function */
1001 "R_ARM_LDRS_PC_G0", /* name */
1002 FALSE, /* partial_inplace */
1003 0xffffffff, /* src_mask */
1004 0xffffffff, /* dst_mask */
1005 TRUE), /* pcrel_offset */
1006
1007 HOWTO (R_ARM_LDRS_PC_G1, /* type */
1008 0, /* rightshift */
1009 2, /* size (0 = byte, 1 = short, 2 = long) */
1010 32, /* bitsize */
1011 TRUE, /* pc_relative */
1012 0, /* bitpos */
1013 complain_overflow_dont,/* complain_on_overflow */
1014 bfd_elf_generic_reloc, /* special_function */
1015 "R_ARM_LDRS_PC_G1", /* name */
1016 FALSE, /* partial_inplace */
1017 0xffffffff, /* src_mask */
1018 0xffffffff, /* dst_mask */
1019 TRUE), /* pcrel_offset */
1020
1021 HOWTO (R_ARM_LDRS_PC_G2, /* type */
1022 0, /* rightshift */
1023 2, /* size (0 = byte, 1 = short, 2 = long) */
1024 32, /* bitsize */
1025 TRUE, /* pc_relative */
1026 0, /* bitpos */
1027 complain_overflow_dont,/* complain_on_overflow */
1028 bfd_elf_generic_reloc, /* special_function */
1029 "R_ARM_LDRS_PC_G2", /* name */
1030 FALSE, /* partial_inplace */
1031 0xffffffff, /* src_mask */
1032 0xffffffff, /* dst_mask */
1033 TRUE), /* pcrel_offset */
1034
1035 HOWTO (R_ARM_LDC_PC_G0, /* type */
1036 0, /* rightshift */
1037 2, /* size (0 = byte, 1 = short, 2 = long) */
1038 32, /* bitsize */
1039 TRUE, /* pc_relative */
1040 0, /* bitpos */
1041 complain_overflow_dont,/* complain_on_overflow */
1042 bfd_elf_generic_reloc, /* special_function */
1043 "R_ARM_LDC_PC_G0", /* name */
1044 FALSE, /* partial_inplace */
1045 0xffffffff, /* src_mask */
1046 0xffffffff, /* dst_mask */
1047 TRUE), /* pcrel_offset */
1048
1049 HOWTO (R_ARM_LDC_PC_G1, /* type */
1050 0, /* rightshift */
1051 2, /* size (0 = byte, 1 = short, 2 = long) */
1052 32, /* bitsize */
1053 TRUE, /* pc_relative */
1054 0, /* bitpos */
1055 complain_overflow_dont,/* complain_on_overflow */
1056 bfd_elf_generic_reloc, /* special_function */
1057 "R_ARM_LDC_PC_G1", /* name */
1058 FALSE, /* partial_inplace */
1059 0xffffffff, /* src_mask */
1060 0xffffffff, /* dst_mask */
1061 TRUE), /* pcrel_offset */
1062
1063 HOWTO (R_ARM_LDC_PC_G2, /* type */
1064 0, /* rightshift */
1065 2, /* size (0 = byte, 1 = short, 2 = long) */
1066 32, /* bitsize */
1067 TRUE, /* pc_relative */
1068 0, /* bitpos */
1069 complain_overflow_dont,/* complain_on_overflow */
1070 bfd_elf_generic_reloc, /* special_function */
1071 "R_ARM_LDC_PC_G2", /* name */
1072 FALSE, /* partial_inplace */
1073 0xffffffff, /* src_mask */
1074 0xffffffff, /* dst_mask */
1075 TRUE), /* pcrel_offset */
1076
1077 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
1078 0, /* rightshift */
1079 2, /* size (0 = byte, 1 = short, 2 = long) */
1080 32, /* bitsize */
1081 TRUE, /* pc_relative */
1082 0, /* bitpos */
1083 complain_overflow_dont,/* complain_on_overflow */
1084 bfd_elf_generic_reloc, /* special_function */
1085 "R_ARM_ALU_SB_G0_NC", /* name */
1086 FALSE, /* partial_inplace */
1087 0xffffffff, /* src_mask */
1088 0xffffffff, /* dst_mask */
1089 TRUE), /* pcrel_offset */
1090
1091 HOWTO (R_ARM_ALU_SB_G0, /* type */
1092 0, /* rightshift */
1093 2, /* size (0 = byte, 1 = short, 2 = long) */
1094 32, /* bitsize */
1095 TRUE, /* pc_relative */
1096 0, /* bitpos */
1097 complain_overflow_dont,/* complain_on_overflow */
1098 bfd_elf_generic_reloc, /* special_function */
1099 "R_ARM_ALU_SB_G0", /* name */
1100 FALSE, /* partial_inplace */
1101 0xffffffff, /* src_mask */
1102 0xffffffff, /* dst_mask */
1103 TRUE), /* pcrel_offset */
1104
1105 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
1106 0, /* rightshift */
1107 2, /* size (0 = byte, 1 = short, 2 = long) */
1108 32, /* bitsize */
1109 TRUE, /* pc_relative */
1110 0, /* bitpos */
1111 complain_overflow_dont,/* complain_on_overflow */
1112 bfd_elf_generic_reloc, /* special_function */
1113 "R_ARM_ALU_SB_G1_NC", /* name */
1114 FALSE, /* partial_inplace */
1115 0xffffffff, /* src_mask */
1116 0xffffffff, /* dst_mask */
1117 TRUE), /* pcrel_offset */
1118
1119 HOWTO (R_ARM_ALU_SB_G1, /* type */
1120 0, /* rightshift */
1121 2, /* size (0 = byte, 1 = short, 2 = long) */
1122 32, /* bitsize */
1123 TRUE, /* pc_relative */
1124 0, /* bitpos */
1125 complain_overflow_dont,/* complain_on_overflow */
1126 bfd_elf_generic_reloc, /* special_function */
1127 "R_ARM_ALU_SB_G1", /* name */
1128 FALSE, /* partial_inplace */
1129 0xffffffff, /* src_mask */
1130 0xffffffff, /* dst_mask */
1131 TRUE), /* pcrel_offset */
1132
1133 HOWTO (R_ARM_ALU_SB_G2, /* type */
1134 0, /* rightshift */
1135 2, /* size (0 = byte, 1 = short, 2 = long) */
1136 32, /* bitsize */
1137 TRUE, /* pc_relative */
1138 0, /* bitpos */
1139 complain_overflow_dont,/* complain_on_overflow */
1140 bfd_elf_generic_reloc, /* special_function */
1141 "R_ARM_ALU_SB_G2", /* name */
1142 FALSE, /* partial_inplace */
1143 0xffffffff, /* src_mask */
1144 0xffffffff, /* dst_mask */
1145 TRUE), /* pcrel_offset */
1146
1147 HOWTO (R_ARM_LDR_SB_G0, /* type */
1148 0, /* rightshift */
1149 2, /* size (0 = byte, 1 = short, 2 = long) */
1150 32, /* bitsize */
1151 TRUE, /* pc_relative */
1152 0, /* bitpos */
1153 complain_overflow_dont,/* complain_on_overflow */
1154 bfd_elf_generic_reloc, /* special_function */
1155 "R_ARM_LDR_SB_G0", /* name */
1156 FALSE, /* partial_inplace */
1157 0xffffffff, /* src_mask */
1158 0xffffffff, /* dst_mask */
1159 TRUE), /* pcrel_offset */
1160
1161 HOWTO (R_ARM_LDR_SB_G1, /* type */
1162 0, /* rightshift */
1163 2, /* size (0 = byte, 1 = short, 2 = long) */
1164 32, /* bitsize */
1165 TRUE, /* pc_relative */
1166 0, /* bitpos */
1167 complain_overflow_dont,/* complain_on_overflow */
1168 bfd_elf_generic_reloc, /* special_function */
1169 "R_ARM_LDR_SB_G1", /* name */
1170 FALSE, /* partial_inplace */
1171 0xffffffff, /* src_mask */
1172 0xffffffff, /* dst_mask */
1173 TRUE), /* pcrel_offset */
1174
1175 HOWTO (R_ARM_LDR_SB_G2, /* type */
1176 0, /* rightshift */
1177 2, /* size (0 = byte, 1 = short, 2 = long) */
1178 32, /* bitsize */
1179 TRUE, /* pc_relative */
1180 0, /* bitpos */
1181 complain_overflow_dont,/* complain_on_overflow */
1182 bfd_elf_generic_reloc, /* special_function */
1183 "R_ARM_LDR_SB_G2", /* name */
1184 FALSE, /* partial_inplace */
1185 0xffffffff, /* src_mask */
1186 0xffffffff, /* dst_mask */
1187 TRUE), /* pcrel_offset */
1188
1189 HOWTO (R_ARM_LDRS_SB_G0, /* type */
1190 0, /* rightshift */
1191 2, /* size (0 = byte, 1 = short, 2 = long) */
1192 32, /* bitsize */
1193 TRUE, /* pc_relative */
1194 0, /* bitpos */
1195 complain_overflow_dont,/* complain_on_overflow */
1196 bfd_elf_generic_reloc, /* special_function */
1197 "R_ARM_LDRS_SB_G0", /* name */
1198 FALSE, /* partial_inplace */
1199 0xffffffff, /* src_mask */
1200 0xffffffff, /* dst_mask */
1201 TRUE), /* pcrel_offset */
1202
1203 HOWTO (R_ARM_LDRS_SB_G1, /* type */
1204 0, /* rightshift */
1205 2, /* size (0 = byte, 1 = short, 2 = long) */
1206 32, /* bitsize */
1207 TRUE, /* pc_relative */
1208 0, /* bitpos */
1209 complain_overflow_dont,/* complain_on_overflow */
1210 bfd_elf_generic_reloc, /* special_function */
1211 "R_ARM_LDRS_SB_G1", /* name */
1212 FALSE, /* partial_inplace */
1213 0xffffffff, /* src_mask */
1214 0xffffffff, /* dst_mask */
1215 TRUE), /* pcrel_offset */
1216
1217 HOWTO (R_ARM_LDRS_SB_G2, /* type */
1218 0, /* rightshift */
1219 2, /* size (0 = byte, 1 = short, 2 = long) */
1220 32, /* bitsize */
1221 TRUE, /* pc_relative */
1222 0, /* bitpos */
1223 complain_overflow_dont,/* complain_on_overflow */
1224 bfd_elf_generic_reloc, /* special_function */
1225 "R_ARM_LDRS_SB_G2", /* name */
1226 FALSE, /* partial_inplace */
1227 0xffffffff, /* src_mask */
1228 0xffffffff, /* dst_mask */
1229 TRUE), /* pcrel_offset */
1230
1231 HOWTO (R_ARM_LDC_SB_G0, /* type */
1232 0, /* rightshift */
1233 2, /* size (0 = byte, 1 = short, 2 = long) */
1234 32, /* bitsize */
1235 TRUE, /* pc_relative */
1236 0, /* bitpos */
1237 complain_overflow_dont,/* complain_on_overflow */
1238 bfd_elf_generic_reloc, /* special_function */
1239 "R_ARM_LDC_SB_G0", /* name */
1240 FALSE, /* partial_inplace */
1241 0xffffffff, /* src_mask */
1242 0xffffffff, /* dst_mask */
1243 TRUE), /* pcrel_offset */
1244
1245 HOWTO (R_ARM_LDC_SB_G1, /* type */
1246 0, /* rightshift */
1247 2, /* size (0 = byte, 1 = short, 2 = long) */
1248 32, /* bitsize */
1249 TRUE, /* pc_relative */
1250 0, /* bitpos */
1251 complain_overflow_dont,/* complain_on_overflow */
1252 bfd_elf_generic_reloc, /* special_function */
1253 "R_ARM_LDC_SB_G1", /* name */
1254 FALSE, /* partial_inplace */
1255 0xffffffff, /* src_mask */
1256 0xffffffff, /* dst_mask */
1257 TRUE), /* pcrel_offset */
1258
1259 HOWTO (R_ARM_LDC_SB_G2, /* type */
1260 0, /* rightshift */
1261 2, /* size (0 = byte, 1 = short, 2 = long) */
1262 32, /* bitsize */
1263 TRUE, /* pc_relative */
1264 0, /* bitpos */
1265 complain_overflow_dont,/* complain_on_overflow */
1266 bfd_elf_generic_reloc, /* special_function */
1267 "R_ARM_LDC_SB_G2", /* name */
1268 FALSE, /* partial_inplace */
1269 0xffffffff, /* src_mask */
1270 0xffffffff, /* dst_mask */
1271 TRUE), /* pcrel_offset */
1272
1273 /* End of group relocations. */
c19d1205 1274
c19d1205
ZW		 1275 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1276 0, /* rightshift */
1277 2, /* size (0 = byte, 1 = short, 2 = long) */
1278 16, /* bitsize */
1279 FALSE, /* pc_relative */
1280 0, /* bitpos */
1281 complain_overflow_dont,/* complain_on_overflow */
1282 bfd_elf_generic_reloc, /* special_function */
1283 "R_ARM_MOVW_BREL_NC", /* name */
1284 FALSE, /* partial_inplace */
1285 0x0000ffff, /* src_mask */
1286 0x0000ffff, /* dst_mask */
1287 FALSE), /* pcrel_offset */
1288
1289 HOWTO (R_ARM_MOVT_BREL, /* type */
1290 0, /* rightshift */
1291 2, /* size (0 = byte, 1 = short, 2 = long) */
1292 16, /* bitsize */
1293 FALSE, /* pc_relative */
1294 0, /* bitpos */
1295 complain_overflow_bitfield,/* complain_on_overflow */
1296 bfd_elf_generic_reloc, /* special_function */
1297 "R_ARM_MOVT_BREL", /* name */
1298 FALSE, /* partial_inplace */
1299 0x0000ffff, /* src_mask */
1300 0x0000ffff, /* dst_mask */
1301 FALSE), /* pcrel_offset */
1302
1303 HOWTO (R_ARM_MOVW_BREL, /* type */
1304 0, /* rightshift */
1305 2, /* size (0 = byte, 1 = short, 2 = long) */
1306 16, /* bitsize */
1307 FALSE, /* pc_relative */
1308 0, /* bitpos */
1309 complain_overflow_dont,/* complain_on_overflow */
1310 bfd_elf_generic_reloc, /* special_function */
1311 "R_ARM_MOVW_BREL", /* name */
1312 FALSE, /* partial_inplace */
1313 0x0000ffff, /* src_mask */
1314 0x0000ffff, /* dst_mask */
1315 FALSE), /* pcrel_offset */
1316
1317 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1318 0, /* rightshift */
1319 2, /* size (0 = byte, 1 = short, 2 = long) */
1320 16, /* bitsize */
1321 FALSE, /* pc_relative */
1322 0, /* bitpos */
1323 complain_overflow_dont,/* complain_on_overflow */
1324 bfd_elf_generic_reloc, /* special_function */
1325 "R_ARM_THM_MOVW_BREL_NC",/* name */
1326 FALSE, /* partial_inplace */
1327 0x040f70ff, /* src_mask */
1328 0x040f70ff, /* dst_mask */
1329 FALSE), /* pcrel_offset */
1330
1331 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1332 0, /* rightshift */
1333 2, /* size (0 = byte, 1 = short, 2 = long) */
1334 16, /* bitsize */
1335 FALSE, /* pc_relative */
1336 0, /* bitpos */
1337 complain_overflow_bitfield,/* complain_on_overflow */
1338 bfd_elf_generic_reloc, /* special_function */
1339 "R_ARM_THM_MOVT_BREL", /* name */
1340 FALSE, /* partial_inplace */
1341 0x040f70ff, /* src_mask */
1342 0x040f70ff, /* dst_mask */
1343 FALSE), /* pcrel_offset */
1344
1345 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1346 0, /* rightshift */
1347 2, /* size (0 = byte, 1 = short, 2 = long) */
1348 16, /* bitsize */
1349 FALSE, /* pc_relative */
1350 0, /* bitpos */
1351 complain_overflow_dont,/* complain_on_overflow */
1352 bfd_elf_generic_reloc, /* special_function */
1353 "R_ARM_THM_MOVW_BREL", /* name */
1354 FALSE, /* partial_inplace */
1355 0x040f70ff, /* src_mask */
1356 0x040f70ff, /* dst_mask */
1357 FALSE), /* pcrel_offset */
1358
0855e32b
NS		 1359 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1360 0, /* rightshift */
1361 2, /* size (0 = byte, 1 = short, 2 = long) */
1362 32, /* bitsize */
1363 FALSE, /* pc_relative */
1364 0, /* bitpos */
1365 complain_overflow_bitfield,/* complain_on_overflow */
1366 NULL, /* special_function */
1367 "R_ARM_TLS_GOTDESC", /* name */
1368 TRUE, /* partial_inplace */
1369 0xffffffff, /* src_mask */
1370 0xffffffff, /* dst_mask */
1371 FALSE), /* pcrel_offset */
1372
1373 HOWTO (R_ARM_TLS_CALL, /* type */
1374 0, /* rightshift */
1375 2, /* size (0 = byte, 1 = short, 2 = long) */
1376 24, /* bitsize */
1377 FALSE, /* pc_relative */
1378 0, /* bitpos */
1379 complain_overflow_dont,/* complain_on_overflow */
1380 bfd_elf_generic_reloc, /* special_function */
1381 "R_ARM_TLS_CALL", /* name */
1382 FALSE, /* partial_inplace */
1383 0x00ffffff, /* src_mask */
1384 0x00ffffff, /* dst_mask */
1385 FALSE), /* pcrel_offset */
1386
1387 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1388 0, /* rightshift */
1389 2, /* size (0 = byte, 1 = short, 2 = long) */
1390 0, /* bitsize */
1391 FALSE, /* pc_relative */
1392 0, /* bitpos */
1393 complain_overflow_bitfield,/* complain_on_overflow */
1394 bfd_elf_generic_reloc, /* special_function */
1395 "R_ARM_TLS_DESCSEQ", /* name */
1396 FALSE, /* partial_inplace */
1397 0x00000000, /* src_mask */
1398 0x00000000, /* dst_mask */
1399 FALSE), /* pcrel_offset */
1400
1401 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1402 0, /* rightshift */
1403 2, /* size (0 = byte, 1 = short, 2 = long) */
1404 24, /* bitsize */
1405 FALSE, /* pc_relative */
1406 0, /* bitpos */
1407 complain_overflow_dont,/* complain_on_overflow */
1408 bfd_elf_generic_reloc, /* special_function */
1409 "R_ARM_THM_TLS_CALL", /* name */
1410 FALSE, /* partial_inplace */
1411 0x07ff07ff, /* src_mask */
1412 0x07ff07ff, /* dst_mask */
1413 FALSE), /* pcrel_offset */
c19d1205
ZW		 1414
1415 HOWTO (R_ARM_PLT32_ABS, /* type */
1416 0, /* rightshift */
1417 2, /* size (0 = byte, 1 = short, 2 = long) */
1418 32, /* bitsize */
1419 FALSE, /* pc_relative */
1420 0, /* bitpos */
1421 complain_overflow_dont,/* complain_on_overflow */
1422 bfd_elf_generic_reloc, /* special_function */
1423 "R_ARM_PLT32_ABS", /* name */
1424 FALSE, /* partial_inplace */
1425 0xffffffff, /* src_mask */
1426 0xffffffff, /* dst_mask */
1427 FALSE), /* pcrel_offset */
1428
1429 HOWTO (R_ARM_GOT_ABS, /* type */
1430 0, /* rightshift */
1431 2, /* size (0 = byte, 1 = short, 2 = long) */
1432 32, /* bitsize */
1433 FALSE, /* pc_relative */
1434 0, /* bitpos */
1435 complain_overflow_dont,/* complain_on_overflow */
1436 bfd_elf_generic_reloc, /* special_function */
1437 "R_ARM_GOT_ABS", /* name */
1438 FALSE, /* partial_inplace */
1439 0xffffffff, /* src_mask */
1440 0xffffffff, /* dst_mask */
1441 FALSE), /* pcrel_offset */
1442
1443 HOWTO (R_ARM_GOT_PREL, /* type */
1444 0, /* rightshift */
1445 2, /* size (0 = byte, 1 = short, 2 = long) */
1446 32, /* bitsize */
1447 TRUE, /* pc_relative */
1448 0, /* bitpos */
1449 complain_overflow_dont, /* complain_on_overflow */
1450 bfd_elf_generic_reloc, /* special_function */
1451 "R_ARM_GOT_PREL", /* name */
1452 FALSE, /* partial_inplace */
1453 0xffffffff, /* src_mask */
1454 0xffffffff, /* dst_mask */
1455 TRUE), /* pcrel_offset */
1456
1457 HOWTO (R_ARM_GOT_BREL12, /* type */
1458 0, /* rightshift */
1459 2, /* size (0 = byte, 1 = short, 2 = long) */
1460 12, /* bitsize */
1461 FALSE, /* pc_relative */
1462 0, /* bitpos */
1463 complain_overflow_bitfield,/* complain_on_overflow */
1464 bfd_elf_generic_reloc, /* special_function */
1465 "R_ARM_GOT_BREL12", /* name */
1466 FALSE, /* partial_inplace */
1467 0x00000fff, /* src_mask */
1468 0x00000fff, /* dst_mask */
1469 FALSE), /* pcrel_offset */
1470
1471 HOWTO (R_ARM_GOTOFF12, /* type */
1472 0, /* rightshift */
1473 2, /* size (0 = byte, 1 = short, 2 = long) */
1474 12, /* bitsize */
1475 FALSE, /* pc_relative */
1476 0, /* bitpos */
1477 complain_overflow_bitfield,/* complain_on_overflow */
1478 bfd_elf_generic_reloc, /* special_function */
1479 "R_ARM_GOTOFF12", /* name */
1480 FALSE, /* partial_inplace */
1481 0x00000fff, /* src_mask */
1482 0x00000fff, /* dst_mask */
1483 FALSE), /* pcrel_offset */
1484
1485 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
1486
1487 /* GNU extension to record C++ vtable member usage */
1488 HOWTO (R_ARM_GNU_VTENTRY, /* type */
99059e56
RM		 1489 0, /* rightshift */
1490 2, /* size (0 = byte, 1 = short, 2 = long) */
1491 0, /* bitsize */
1492 FALSE, /* pc_relative */
1493 0, /* bitpos */
1494 complain_overflow_dont, /* complain_on_overflow */
1495 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1496 "R_ARM_GNU_VTENTRY", /* name */
1497 FALSE, /* partial_inplace */
1498 0, /* src_mask */
1499 0, /* dst_mask */
1500 FALSE), /* pcrel_offset */
c19d1205
ZW		 1501
1502 /* GNU extension to record C++ vtable hierarchy */
1503 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
99059e56
RM		 1504 0, /* rightshift */
1505 2, /* size (0 = byte, 1 = short, 2 = long) */
1506 0, /* bitsize */
1507 FALSE, /* pc_relative */
1508 0, /* bitpos */
1509 complain_overflow_dont, /* complain_on_overflow */
1510 NULL, /* special_function */
1511 "R_ARM_GNU_VTINHERIT", /* name */
1512 FALSE, /* partial_inplace */
1513 0, /* src_mask */
1514 0, /* dst_mask */
1515 FALSE), /* pcrel_offset */
c19d1205
ZW		 1516
1517 HOWTO (R_ARM_THM_JUMP11, /* type */
1518 1, /* rightshift */
1519 1, /* size (0 = byte, 1 = short, 2 = long) */
1520 11, /* bitsize */
1521 TRUE, /* pc_relative */
1522 0, /* bitpos */
1523 complain_overflow_signed, /* complain_on_overflow */
1524 bfd_elf_generic_reloc, /* special_function */
1525 "R_ARM_THM_JUMP11", /* name */
1526 FALSE, /* partial_inplace */
1527 0x000007ff, /* src_mask */
1528 0x000007ff, /* dst_mask */
1529 TRUE), /* pcrel_offset */
1530
1531 HOWTO (R_ARM_THM_JUMP8, /* type */
1532 1, /* rightshift */
1533 1, /* size (0 = byte, 1 = short, 2 = long) */
1534 8, /* bitsize */
1535 TRUE, /* pc_relative */
1536 0, /* bitpos */
1537 complain_overflow_signed, /* complain_on_overflow */
1538 bfd_elf_generic_reloc, /* special_function */
1539 "R_ARM_THM_JUMP8", /* name */
1540 FALSE, /* partial_inplace */
1541 0x000000ff, /* src_mask */
1542 0x000000ff, /* dst_mask */
1543 TRUE), /* pcrel_offset */
ba93b8ac 1544
c19d1205
ZW		 1545 /* TLS relocations */
1546 HOWTO (R_ARM_TLS_GD32, /* type */
99059e56
RM		 1547 0, /* rightshift */
1548 2, /* size (0 = byte, 1 = short, 2 = long) */
1549 32, /* bitsize */
1550 FALSE, /* pc_relative */
1551 0, /* bitpos */
1552 complain_overflow_bitfield,/* complain_on_overflow */
1553 NULL, /* special_function */
1554 "R_ARM_TLS_GD32", /* name */
1555 TRUE, /* partial_inplace */
1556 0xffffffff, /* src_mask */
1557 0xffffffff, /* dst_mask */
1558 FALSE), /* pcrel_offset */
ba93b8ac 1559
ba93b8ac 1560 HOWTO (R_ARM_TLS_LDM32, /* type */
99059e56
RM		 1561 0, /* rightshift */
1562 2, /* size (0 = byte, 1 = short, 2 = long) */
1563 32, /* bitsize */
1564 FALSE, /* pc_relative */
1565 0, /* bitpos */
1566 complain_overflow_bitfield,/* complain_on_overflow */
1567 bfd_elf_generic_reloc, /* special_function */
1568 "R_ARM_TLS_LDM32", /* name */
1569 TRUE, /* partial_inplace */
1570 0xffffffff, /* src_mask */
1571 0xffffffff, /* dst_mask */
1572 FALSE), /* pcrel_offset */
ba93b8ac 1573
c19d1205 1574 HOWTO (R_ARM_TLS_LDO32, /* type */
99059e56
RM		 1575 0, /* rightshift */
1576 2, /* size (0 = byte, 1 = short, 2 = long) */
1577 32, /* bitsize */
1578 FALSE, /* pc_relative */
1579 0, /* bitpos */
1580 complain_overflow_bitfield,/* complain_on_overflow */
1581 bfd_elf_generic_reloc, /* special_function */
1582 "R_ARM_TLS_LDO32", /* name */
1583 TRUE, /* partial_inplace */
1584 0xffffffff, /* src_mask */
1585 0xffffffff, /* dst_mask */
1586 FALSE), /* pcrel_offset */
ba93b8ac 1587
ba93b8ac 1588 HOWTO (R_ARM_TLS_IE32, /* type */
99059e56
RM		 1589 0, /* rightshift */
1590 2, /* size (0 = byte, 1 = short, 2 = long) */
1591 32, /* bitsize */
1592 FALSE, /* pc_relative */
1593 0, /* bitpos */
1594 complain_overflow_bitfield,/* complain_on_overflow */
1595 NULL, /* special_function */
1596 "R_ARM_TLS_IE32", /* name */
1597 TRUE, /* partial_inplace */
1598 0xffffffff, /* src_mask */
1599 0xffffffff, /* dst_mask */
1600 FALSE), /* pcrel_offset */
7f266840 1601
c19d1205 1602 HOWTO (R_ARM_TLS_LE32, /* type */
99059e56
RM		 1603 0, /* rightshift */
1604 2, /* size (0 = byte, 1 = short, 2 = long) */
1605 32, /* bitsize */
1606 FALSE, /* pc_relative */
1607 0, /* bitpos */
1608 complain_overflow_bitfield,/* complain_on_overflow */
75c11999 1609 NULL, /* special_function */
99059e56
RM		 1610 "R_ARM_TLS_LE32", /* name */
1611 TRUE, /* partial_inplace */
1612 0xffffffff, /* src_mask */
1613 0xffffffff, /* dst_mask */
1614 FALSE), /* pcrel_offset */
7f266840 1615
c19d1205
ZW		 1616 HOWTO (R_ARM_TLS_LDO12, /* type */
1617 0, /* rightshift */
1618 2, /* size (0 = byte, 1 = short, 2 = long) */
1619 12, /* bitsize */
1620 FALSE, /* pc_relative */
7f266840 1621 0, /* bitpos */
c19d1205 1622 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1623 bfd_elf_generic_reloc, /* special_function */
c19d1205 1624 "R_ARM_TLS_LDO12", /* name */
7f266840 1625 FALSE, /* partial_inplace */
c19d1205
ZW		 1626 0x00000fff, /* src_mask */
1627 0x00000fff, /* dst_mask */
1628 FALSE), /* pcrel_offset */
7f266840 1629
c19d1205
ZW		 1630 HOWTO (R_ARM_TLS_LE12, /* type */
1631 0, /* rightshift */
1632 2, /* size (0 = byte, 1 = short, 2 = long) */
1633 12, /* bitsize */
1634 FALSE, /* pc_relative */
7f266840 1635 0, /* bitpos */
c19d1205 1636 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1637 bfd_elf_generic_reloc, /* special_function */
c19d1205 1638 "R_ARM_TLS_LE12", /* name */
7f266840 1639 FALSE, /* partial_inplace */
c19d1205
ZW		 1640 0x00000fff, /* src_mask */
1641 0x00000fff, /* dst_mask */
1642 FALSE), /* pcrel_offset */
7f266840 1643
c19d1205 1644 HOWTO (R_ARM_TLS_IE12GP, /* type */
7f266840
DJ		 1645 0, /* rightshift */
1646 2, /* size (0 = byte, 1 = short, 2 = long) */
c19d1205
ZW		 1647 12, /* bitsize */
1648 FALSE, /* pc_relative */
7f266840 1649 0, /* bitpos */
c19d1205 1650 complain_overflow_bitfield,/* complain_on_overflow */
7f266840 1651 bfd_elf_generic_reloc, /* special_function */
c19d1205 1652 "R_ARM_TLS_IE12GP", /* name */
7f266840 1653 FALSE, /* partial_inplace */
c19d1205
ZW		 1654 0x00000fff, /* src_mask */
1655 0x00000fff, /* dst_mask */
1656 FALSE), /* pcrel_offset */
0855e32b 1657
34e77a92 1658 /* 112-127 private relocations. */
0855e32b
NS		 1659 EMPTY_HOWTO (112),
1660 EMPTY_HOWTO (113),
1661 EMPTY_HOWTO (114),
1662 EMPTY_HOWTO (115),
1663 EMPTY_HOWTO (116),
1664 EMPTY_HOWTO (117),
1665 EMPTY_HOWTO (118),
1666 EMPTY_HOWTO (119),
1667 EMPTY_HOWTO (120),
1668 EMPTY_HOWTO (121),
1669 EMPTY_HOWTO (122),
1670 EMPTY_HOWTO (123),
1671 EMPTY_HOWTO (124),
1672 EMPTY_HOWTO (125),
1673 EMPTY_HOWTO (126),
1674 EMPTY_HOWTO (127),
34e77a92
RS		 1675
1676 /* R_ARM_ME_TOO, obsolete. */
0855e32b
NS		 1677 EMPTY_HOWTO (128),
1678
1679 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1680 0, /* rightshift */
1681 1, /* size (0 = byte, 1 = short, 2 = long) */
1682 0, /* bitsize */
1683 FALSE, /* pc_relative */
1684 0, /* bitpos */
1685 complain_overflow_bitfield,/* complain_on_overflow */
1686 bfd_elf_generic_reloc, /* special_function */
1687 "R_ARM_THM_TLS_DESCSEQ",/* name */
1688 FALSE, /* partial_inplace */
1689 0x00000000, /* src_mask */
1690 0x00000000, /* dst_mask */
1691 FALSE), /* pcrel_offset */
72d98d16
MG		 1692 EMPTY_HOWTO (130),
1693 EMPTY_HOWTO (131),
1694 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1695 0, /* rightshift. */
1696 1, /* size (0 = byte, 1 = short, 2 = long). */
1697 16, /* bitsize. */
1698 FALSE, /* pc_relative. */
1699 0, /* bitpos. */
1700 complain_overflow_bitfield,/* complain_on_overflow. */
1701 bfd_elf_generic_reloc, /* special_function. */
1702 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1703 FALSE, /* partial_inplace. */
1704 0x00000000, /* src_mask. */
1705 0x00000000, /* dst_mask. */
1706 FALSE), /* pcrel_offset. */
1707 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1708 0, /* rightshift. */
1709 1, /* size (0 = byte, 1 = short, 2 = long). */
1710 16, /* bitsize. */
1711 FALSE, /* pc_relative. */
1712 0, /* bitpos. */
1713 complain_overflow_bitfield,/* complain_on_overflow. */
1714 bfd_elf_generic_reloc, /* special_function. */
1715 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1716 FALSE, /* partial_inplace. */
1717 0x00000000, /* src_mask. */
1718 0x00000000, /* dst_mask. */
1719 FALSE), /* pcrel_offset. */
1720 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1721 0, /* rightshift. */
1722 1, /* size (0 = byte, 1 = short, 2 = long). */
1723 16, /* bitsize. */
1724 FALSE, /* pc_relative. */
1725 0, /* bitpos. */
1726 complain_overflow_bitfield,/* complain_on_overflow. */
1727 bfd_elf_generic_reloc, /* special_function. */
1728 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1729 FALSE, /* partial_inplace. */
1730 0x00000000, /* src_mask. */
1731 0x00000000, /* dst_mask. */
1732 FALSE), /* pcrel_offset. */
1733 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1734 0, /* rightshift. */
1735 1, /* size (0 = byte, 1 = short, 2 = long). */
1736 16, /* bitsize. */
1737 FALSE, /* pc_relative. */
1738 0, /* bitpos. */
1739 complain_overflow_bitfield,/* complain_on_overflow. */
1740 bfd_elf_generic_reloc, /* special_function. */
1741 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1742 FALSE, /* partial_inplace. */
1743 0x00000000, /* src_mask. */
1744 0x00000000, /* dst_mask. */
1745 FALSE), /* pcrel_offset. */
c19d1205
ZW		 1746};
1747
34e77a92
RS		 1748/* 160 onwards: */
1749static reloc_howto_type elf32_arm_howto_table_2[1] =
1750{
1751 HOWTO (R_ARM_IRELATIVE, /* type */
99059e56
RM		 1752 0, /* rightshift */
1753 2, /* size (0 = byte, 1 = short, 2 = long) */
1754 32, /* bitsize */
1755 FALSE, /* pc_relative */
1756 0, /* bitpos */
1757 complain_overflow_bitfield,/* complain_on_overflow */
1758 bfd_elf_generic_reloc, /* special_function */
1759 "R_ARM_IRELATIVE", /* name */
1760 TRUE, /* partial_inplace */
1761 0xffffffff, /* src_mask */
1762 0xffffffff, /* dst_mask */
1763 FALSE) /* pcrel_offset */
34e77a92 1764};
c19d1205 1765
34e77a92
RS		 1766/* 249-255 extended, currently unused, relocations: */
1767static reloc_howto_type elf32_arm_howto_table_3[4] =
7f266840
DJ		 1768{
1769 HOWTO (R_ARM_RREL32, /* type */
1770 0, /* rightshift */
1771 0, /* size (0 = byte, 1 = short, 2 = long) */
1772 0, /* bitsize */
1773 FALSE, /* pc_relative */
1774 0, /* bitpos */
1775 complain_overflow_dont,/* complain_on_overflow */
1776 bfd_elf_generic_reloc, /* special_function */
1777 "R_ARM_RREL32", /* name */
1778 FALSE, /* partial_inplace */
1779 0, /* src_mask */
1780 0, /* dst_mask */
1781 FALSE), /* pcrel_offset */
1782
1783 HOWTO (R_ARM_RABS32, /* type */
1784 0, /* rightshift */
1785 0, /* size (0 = byte, 1 = short, 2 = long) */
1786 0, /* bitsize */
1787 FALSE, /* pc_relative */
1788 0, /* bitpos */
1789 complain_overflow_dont,/* complain_on_overflow */
1790 bfd_elf_generic_reloc, /* special_function */
1791 "R_ARM_RABS32", /* name */
1792 FALSE, /* partial_inplace */
1793 0, /* src_mask */
1794 0, /* dst_mask */
1795 FALSE), /* pcrel_offset */
1796
1797 HOWTO (R_ARM_RPC24, /* type */
1798 0, /* rightshift */
1799 0, /* size (0 = byte, 1 = short, 2 = long) */
1800 0, /* bitsize */
1801 FALSE, /* pc_relative */
1802 0, /* bitpos */
1803 complain_overflow_dont,/* complain_on_overflow */
1804 bfd_elf_generic_reloc, /* special_function */
1805 "R_ARM_RPC24", /* name */
1806 FALSE, /* partial_inplace */
1807 0, /* src_mask */
1808 0, /* dst_mask */
1809 FALSE), /* pcrel_offset */
1810
1811 HOWTO (R_ARM_RBASE, /* type */
1812 0, /* rightshift */
1813 0, /* size (0 = byte, 1 = short, 2 = long) */
1814 0, /* bitsize */
1815 FALSE, /* pc_relative */
1816 0, /* bitpos */
1817 complain_overflow_dont,/* complain_on_overflow */
1818 bfd_elf_generic_reloc, /* special_function */
1819 "R_ARM_RBASE", /* name */
1820 FALSE, /* partial_inplace */
1821 0, /* src_mask */
1822 0, /* dst_mask */
1823 FALSE) /* pcrel_offset */
1824};
1825
1826static reloc_howto_type *
1827elf32_arm_howto_from_type (unsigned int r_type)
1828{
906e58ca 1829 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
c19d1205 1830 return &elf32_arm_howto_table_1[r_type];
ba93b8ac 1831
34e77a92
RS		 1832 if (r_type == R_ARM_IRELATIVE)
1833 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1834
c19d1205 1835 if (r_type >= R_ARM_RREL32
34e77a92
RS		 1836 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1837 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
7f266840 1838
c19d1205 1839 return NULL;
7f266840
DJ		 1840}
1841
1842static void
1843elf32_arm_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, arelent * bfd_reloc,
1844 Elf_Internal_Rela * elf_reloc)
1845{
1846 unsigned int r_type;
1847
1848 r_type = ELF32_R_TYPE (elf_reloc->r_info);
1849 bfd_reloc->howto = elf32_arm_howto_from_type (r_type);
1850}
1851
1852struct elf32_arm_reloc_map
1853 {
1854 bfd_reloc_code_real_type bfd_reloc_val;
1855 unsigned char elf_reloc_val;
1856 };
1857
1858/* All entries in this list must also be present in elf32_arm_howto_table. */
1859static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
1860 {
1861 {BFD_RELOC_NONE, R_ARM_NONE},
1862 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
39b41c9c
PB		 1863 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
1864 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
7f266840
DJ		 1865 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
1866 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
1867 {BFD_RELOC_32, R_ARM_ABS32},
1868 {BFD_RELOC_32_PCREL, R_ARM_REL32},
1869 {BFD_RELOC_8, R_ARM_ABS8},
1870 {BFD_RELOC_16, R_ARM_ABS16},
1871 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
1872 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
c19d1205
ZW		 1873 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
1874 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
1875 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
1876 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
1877 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
1878 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
7f266840
DJ		 1879 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
1880 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
1881 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
c19d1205 1882 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
7f266840 1883 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
b43420e6 1884 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
7f266840
DJ		 1885 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
1886 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
1887 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
1888 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
1889 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
1890 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
ba93b8ac
DJ		 1891 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
1892 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
0855e32b
NS		 1893 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
1894 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
1895 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
1896 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
1897 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
1898 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
ba93b8ac
DJ		 1899 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
1900 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
1901 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
1902 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
1903 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
1904 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
1905 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
1906 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
34e77a92 1907 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
c19d1205
ZW		 1908 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
1909 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
b6895b4f
PB		 1910 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
1911 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
1912 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
1913 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
1914 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
1915 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
1916 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
1917 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
4962c51a
MS		 1918 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
1919 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
1920 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
1921 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
1922 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
1923 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
1924 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
1925 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
1926 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
1927 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
1928 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
1929 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
1930 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
1931 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
1932 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
1933 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
1934 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
1935 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
1936 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
1937 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
1938 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
1939 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
1940 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
1941 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
1942 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
1943 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
1944 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
845b51d6 1945 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
72d98d16
MG		 1946 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
1947 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
1948 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
1949 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
1950 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC}
7f266840
DJ		 1951 };
1952
1953static reloc_howto_type *
f1c71a59
ZW		 1954elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1955 bfd_reloc_code_real_type code)
7f266840
DJ		 1956{
1957 unsigned int i;
8029a119 1958
906e58ca 1959 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
c19d1205
ZW		 1960 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
1961 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
7f266840 1962
c19d1205 1963 return NULL;
7f266840
DJ		 1964}
1965
157090f7
AM		 1966static reloc_howto_type *
1967elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
1968 const char *r_name)
1969{
1970 unsigned int i;
1971
906e58ca 1972 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
157090f7
AM		 1973 if (elf32_arm_howto_table_1[i].name != NULL
1974 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
1975 return &elf32_arm_howto_table_1[i];
1976
906e58ca 1977 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
157090f7
AM		 1978 if (elf32_arm_howto_table_2[i].name != NULL
1979 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
1980 return &elf32_arm_howto_table_2[i];
1981
34e77a92
RS		 1982 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
1983 if (elf32_arm_howto_table_3[i].name != NULL
1984 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
1985 return &elf32_arm_howto_table_3[i];
1986
157090f7
AM		 1987 return NULL;
1988}
1989
906e58ca
NC		 1990/* Support for core dump NOTE sections. */
1991
7f266840 1992static bfd_boolean
f1c71a59 1993elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 1994{
1995 int offset;
1996 size_t size;
1997
1998 switch (note->descsz)
1999 {
2000 default:
2001 return FALSE;
2002
8029a119 2003 case 148: /* Linux/ARM 32-bit. */
7f266840 2004 /* pr_cursig */
228e534f 2005 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
7f266840
DJ		 2006
2007 /* pr_pid */
228e534f 2008 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
7f266840
DJ		 2009
2010 /* pr_reg */
2011 offset = 72;
2012 size = 72;
2013
2014 break;
2015 }
2016
2017 /* Make a ".reg/999" section. */
2018 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2019 size, note->descpos + offset);
2020}
2021
2022static bfd_boolean
f1c71a59 2023elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
7f266840
DJ		 2024{
2025 switch (note->descsz)
2026 {
2027 default:
2028 return FALSE;
2029
8029a119 2030 case 124: /* Linux/ARM elf_prpsinfo. */
228e534f 2031 elf_tdata (abfd)->core->pid
4395ee08 2032 = bfd_get_32 (abfd, note->descdata + 12);
228e534f 2033 elf_tdata (abfd)->core->program
7f266840 2034 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
228e534f 2035 elf_tdata (abfd)->core->command
7f266840
DJ		 2036 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2037 }
2038
2039 /* Note that for some reason, a spurious space is tacked
2040 onto the end of the args in some (at least one anyway)
2041 implementations, so strip it off if it exists. */
7f266840 2042 {
228e534f 2043 char *command = elf_tdata (abfd)->core->command;
7f266840
DJ		 2044 int n = strlen (command);
2045
2046 if (0 < n && command[n - 1] == ' ')
2047 command[n - 1] = '\0';
2048 }
2049
2050 return TRUE;
2051}
2052
1f20dca5
UW		 2053static char *
2054elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2055 int note_type, ...)
2056{
2057 switch (note_type)
2058 {
2059 default:
2060 return NULL;
2061
2062 case NT_PRPSINFO:
2063 {
2064 char data[124];
2065 va_list ap;
2066
2067 va_start (ap, note_type);
2068 memset (data, 0, sizeof (data));
2069 strncpy (data + 28, va_arg (ap, const char *), 16);
2070 strncpy (data + 44, va_arg (ap, const char *), 80);
2071 va_end (ap);
2072
2073 return elfcore_write_note (abfd, buf, bufsiz,
2074 "CORE", note_type, data, sizeof (data));
2075 }
2076
2077 case NT_PRSTATUS:
2078 {
2079 char data[148];
2080 va_list ap;
2081 long pid;
2082 int cursig;
2083 const void *greg;
2084
2085 va_start (ap, note_type);
2086 memset (data, 0, sizeof (data));
2087 pid = va_arg (ap, long);
2088 bfd_put_32 (abfd, pid, data + 24);
2089 cursig = va_arg (ap, int);
2090 bfd_put_16 (abfd, cursig, data + 12);
2091 greg = va_arg (ap, const void *);
2092 memcpy (data + 72, greg, 72);
2093 va_end (ap);
2094
2095 return elfcore_write_note (abfd, buf, bufsiz,
2096 "CORE", note_type, data, sizeof (data));
2097 }
2098 }
2099}
2100
6d00b590 2101#define TARGET_LITTLE_SYM arm_elf32_le_vec
7f266840 2102#define TARGET_LITTLE_NAME "elf32-littlearm"
6d00b590 2103#define TARGET_BIG_SYM arm_elf32_be_vec
7f266840
DJ		 2104#define TARGET_BIG_NAME "elf32-bigarm"
2105
2106#define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2107#define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1f20dca5 2108#define elf_backend_write_core_note elf32_arm_nabi_write_core_note
7f266840 2109
252b5132
RH		 2110typedef unsigned long int insn32;
2111typedef unsigned short int insn16;
2112
3a4a14e9
PB		 2113/* In lieu of proper flags, assume all EABIv4 or later objects are
2114 interworkable. */
57e8b36a 2115#define INTERWORK_FLAG(abfd) \
3a4a14e9 2116 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
3e6b1042
DJ		 2117 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2118 || ((abfd)->flags & BFD_LINKER_CREATED))
9b485d32 2119
252b5132
RH		 2120/* The linker script knows the section names for placement.
2121 The entry_names are used to do simple name mangling on the stubs.
2122 Given a function name, and its type, the stub can be found. The
9b485d32 2123 name can be changed. The only requirement is the %s be present. */
252b5132
RH		 2124#define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2125#define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2126
2127#define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2128#define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2129
c7b8f16e
JB		 2130#define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2131#define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2132
a504d23a
LA		 2133#define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2134#define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2135
845b51d6
PB		 2136#define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2137#define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2138
7413f23f
DJ		 2139#define STUB_ENTRY_NAME "__%s_veneer"
2140
252b5132
RH		 2141/* The name of the dynamic interpreter. This is put in the .interp
2142 section. */
2143#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2144
0855e32b 2145static const unsigned long tls_trampoline [] =
b38cadfb
NC		 2146{
2147 0xe08e0000, /* add r0, lr, r0 */
2148 0xe5901004, /* ldr r1, [r0,#4] */
2149 0xe12fff11, /* bx r1 */
2150};
0855e32b
NS		 2151
2152static const unsigned long dl_tlsdesc_lazy_trampoline [] =
b38cadfb
NC		 2153{
2154 0xe52d2004, /* push {r2} */
2155 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2156 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2157 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2158 0xe081100f, /* 2: add r1, pc */
2159 0xe12fff12, /* bx r2 */
2160 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
99059e56 2161 + dl_tlsdesc_lazy_resolver(GOT) */
b38cadfb
NC		 2162 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2163};
0855e32b 2164
5e681ec4
PB		 2165#ifdef FOUR_WORD_PLT
2166
252b5132
RH		 2167/* The first entry in a procedure linkage table looks like
2168 this. It is set up so that any shared library function that is
59f2c4e7 2169 called before the relocation has been set up calls the dynamic
9b485d32 2170 linker first. */
e5a52504 2171static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2172{
2173 0xe52de004, /* str lr, [sp, #-4]! */
2174 0xe59fe010, /* ldr lr, [pc, #16] */
2175 0xe08fe00e, /* add lr, pc, lr */
2176 0xe5bef008, /* ldr pc, [lr, #8]! */
2177};
5e681ec4
PB		 2178
2179/* Subsequent entries in a procedure linkage table look like
2180 this. */
e5a52504 2181static const bfd_vma elf32_arm_plt_entry [] =
b38cadfb
NC		 2182{
2183 0xe28fc600, /* add ip, pc, #NN */
2184 0xe28cca00, /* add ip, ip, #NN */
2185 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2186 0x00000000, /* unused */
2187};
5e681ec4 2188
eed94f8f 2189#else /* not FOUR_WORD_PLT */
5e681ec4 2190
5e681ec4
PB		 2191/* The first entry in a procedure linkage table looks like
2192 this. It is set up so that any shared library function that is
2193 called before the relocation has been set up calls the dynamic
2194 linker first. */
e5a52504 2195static const bfd_vma elf32_arm_plt0_entry [] =
b38cadfb
NC		 2196{
2197 0xe52de004, /* str lr, [sp, #-4]! */
2198 0xe59fe004, /* ldr lr, [pc, #4] */
2199 0xe08fe00e, /* add lr, pc, lr */
2200 0xe5bef008, /* ldr pc, [lr, #8]! */
2201 0x00000000, /* &GOT[0] - . */
2202};
252b5132 2203
1db37fe6
YG		 2204/* By default subsequent entries in a procedure linkage table look like
2205 this. Offsets that don't fit into 28 bits will cause link error. */
2206static const bfd_vma elf32_arm_plt_entry_short [] =
b38cadfb
NC		 2207{
2208 0xe28fc600, /* add ip, pc, #0xNN00000 */
2209 0xe28cca00, /* add ip, ip, #0xNN000 */
2210 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2211};
5e681ec4 2212
1db37fe6
YG		 2213/* When explicitly asked, we'll use this "long" entry format
2214 which can cope with arbitrary displacements. */
2215static const bfd_vma elf32_arm_plt_entry_long [] =
2216{
2217 0xe28fc200, /* add ip, pc, #0xN0000000 */
2218 0xe28cc600, /* add ip, ip, #0xNN00000 */
2219 0xe28cca00, /* add ip, ip, #0xNN000 */
2220 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2221};
2222
2223static bfd_boolean elf32_arm_use_long_plt_entry = FALSE;
2224
eed94f8f
NC		 2225#endif /* not FOUR_WORD_PLT */
2226
2227/* The first entry in a procedure linkage table looks like this.
2228 It is set up so that any shared library function that is called before the
2229 relocation has been set up calls the dynamic linker first. */
2230static const bfd_vma elf32_thumb2_plt0_entry [] =
2231{
2232 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2233 an instruction maybe encoded to one or two array elements. */
2234 0xf8dfb500, /* push {lr} */
2235 0x44fee008, /* ldr.w lr, [pc, #8] */
469a3493 2236 /* add lr, pc */
eed94f8f
NC		 2237 0xff08f85e, /* ldr.w pc, [lr, #8]! */
2238 0x00000000, /* &GOT[0] - . */
2239};
2240
2241/* Subsequent entries in a procedure linkage table for thumb only target
2242 look like this. */
2243static const bfd_vma elf32_thumb2_plt_entry [] =
2244{
2245 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2246 an instruction maybe encoded to one or two array elements. */
2247 0x0c00f240, /* movw ip, #0xNNNN */
2248 0x0c00f2c0, /* movt ip, #0xNNNN */
2249 0xf8dc44fc, /* add ip, pc */
2250 0xbf00f000 /* ldr.w pc, [ip] */
469a3493 2251 /* nop */
eed94f8f 2252};
252b5132 2253
00a97672
RS		 2254/* The format of the first entry in the procedure linkage table
2255 for a VxWorks executable. */
2256static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
b38cadfb
NC		 2257{
2258 0xe52dc008, /* str ip,[sp,#-8]! */
2259 0xe59fc000, /* ldr ip,[pc] */
2260 0xe59cf008, /* ldr pc,[ip,#8] */
2261 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
2262};
00a97672
RS		 2263
2264/* The format of subsequent entries in a VxWorks executable. */
2265static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
b38cadfb
NC		 2266{
2267 0xe59fc000, /* ldr ip,[pc] */
2268 0xe59cf000, /* ldr pc,[ip] */
2269 0x00000000, /* .long @got */
2270 0xe59fc000, /* ldr ip,[pc] */
2271 0xea000000, /* b _PLT */
2272 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2273};
00a97672
RS		 2274
2275/* The format of entries in a VxWorks shared library. */
2276static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
b38cadfb
NC		 2277{
2278 0xe59fc000, /* ldr ip,[pc] */
2279 0xe79cf009, /* ldr pc,[ip,r9] */
2280 0x00000000, /* .long @got */
2281 0xe59fc000, /* ldr ip,[pc] */
2282 0xe599f008, /* ldr pc,[r9,#8] */
2283 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2284};
00a97672 2285
b7693d02
DJ		 2286/* An initial stub used if the PLT entry is referenced from Thumb code. */
2287#define PLT_THUMB_STUB_SIZE 4
2288static const bfd_vma elf32_arm_plt_thumb_stub [] =
b38cadfb
NC		 2289{
2290 0x4778, /* bx pc */
2291 0x46c0 /* nop */
2292};
b7693d02 2293
e5a52504
MM		 2294/* The entries in a PLT when using a DLL-based target with multiple
2295 address spaces. */
906e58ca 2296static const bfd_vma elf32_arm_symbian_plt_entry [] =
b38cadfb
NC		 2297{
2298 0xe51ff004, /* ldr pc, [pc, #-4] */
2299 0x00000000, /* dcd R_ARM_GLOB_DAT(X) */
2300};
2301
2302/* The first entry in a procedure linkage table looks like
2303 this. It is set up so that any shared library function that is
2304 called before the relocation has been set up calls the dynamic
2305 linker first. */
2306static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2307{
2308 /* First bundle: */
2309 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2310 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2311 0xe08cc00f, /* add ip, ip, pc */
2312 0xe52dc008, /* str ip, [sp, #-8]! */
2313 /* Second bundle: */
edccdf7c
RM		 2314 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2315 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2316 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2317 0xe12fff1c, /* bx ip */
b38cadfb 2318 /* Third bundle: */
edccdf7c
RM		 2319 0xe320f000, /* nop */
2320 0xe320f000, /* nop */
2321 0xe320f000, /* nop */
b38cadfb
NC		 2322 /* .Lplt_tail: */
2323 0xe50dc004, /* str ip, [sp, #-4] */
2324 /* Fourth bundle: */
edccdf7c
RM		 2325 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2326 0xe59cc000, /* ldr ip, [ip] */
b38cadfb 2327 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
edccdf7c 2328 0xe12fff1c, /* bx ip */
b38cadfb
NC		 2329};
2330#define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2331
2332/* Subsequent entries in a procedure linkage table look like this. */
2333static const bfd_vma elf32_arm_nacl_plt_entry [] =
2334{
2335 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2336 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2337 0xe08cc00f, /* add ip, ip, pc */
2338 0xea000000, /* b .Lplt_tail */
2339};
e5a52504 2340
906e58ca
NC		 2341#define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2342#define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2343#define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2344#define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2345#define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2346#define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
c5423981
TG		 2347#define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2348#define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
906e58ca 2349
461a49ca 2350enum stub_insn_type
b38cadfb
NC		 2351{
2352 THUMB16_TYPE = 1,
2353 THUMB32_TYPE,
2354 ARM_TYPE,
2355 DATA_TYPE
2356};
461a49ca 2357
48229727
JB		 2358#define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2359/* A bit of a hack. A Thumb conditional branch, in which the proper condition
2360 is inserted in arm_build_one_stub(). */
2361#define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2362#define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2363#define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2364#define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2365#define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2366#define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
461a49ca
DJ		 2367
2368typedef struct
2369{
b38cadfb
NC		 2370 bfd_vma data;
2371 enum stub_insn_type type;
2372 unsigned int r_type;
2373 int reloc_addend;
461a49ca
DJ		 2374} insn_sequence;
2375
fea2b4d6
CL		 2376/* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2377 to reach the stub if necessary. */
461a49ca 2378static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
b38cadfb
NC		 2379{
2380 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2381 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2382};
906e58ca 2383
fea2b4d6
CL		 2384/* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2385 available. */
461a49ca 2386static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
b38cadfb
NC		 2387{
2388 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2389 ARM_INSN (0xe12fff1c), /* bx ip */
2390 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2391};
906e58ca 2392
d3626fb0 2393/* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
461a49ca 2394static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
b38cadfb
NC		 2395{
2396 THUMB16_INSN (0xb401), /* push {r0} */
2397 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2398 THUMB16_INSN (0x4684), /* mov ip, r0 */
2399 THUMB16_INSN (0xbc01), /* pop {r0} */
2400 THUMB16_INSN (0x4760), /* bx ip */
2401 THUMB16_INSN (0xbf00), /* nop */
2402 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2403};
906e58ca 2404
d3626fb0
CL		 2405/* V4T Thumb -> Thumb long branch stub. Using the stack is not
2406 allowed. */
2407static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
b38cadfb
NC		 2408{
2409 THUMB16_INSN (0x4778), /* bx pc */
2410 THUMB16_INSN (0x46c0), /* nop */
2411 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2412 ARM_INSN (0xe12fff1c), /* bx ip */
2413 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2414};
d3626fb0 2415
fea2b4d6
CL		 2416/* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2417 available. */
461a49ca 2418static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2419{
2420 THUMB16_INSN (0x4778), /* bx pc */
2421 THUMB16_INSN (0x46c0), /* nop */
2422 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2423 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2424};
906e58ca 2425
fea2b4d6
CL		 2426/* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2427 one, when the destination is close enough. */
461a49ca 2428static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
b38cadfb
NC		 2429{
2430 THUMB16_INSN (0x4778), /* bx pc */
2431 THUMB16_INSN (0x46c0), /* nop */
2432 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2433};
c820be07 2434
cf3eccff 2435/* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
fea2b4d6 2436 blx to reach the stub if necessary. */
cf3eccff 2437static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
b38cadfb
NC		 2438{
2439 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2440 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
2441 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2442};
906e58ca 2443
cf3eccff
DJ		 2444/* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2445 blx to reach the stub if necessary. We can not add into pc;
2446 it is not guaranteed to mode switch (different in ARMv6 and
2447 ARMv7). */
2448static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
b38cadfb
NC		 2449{
2450 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2451 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2452 ARM_INSN (0xe12fff1c), /* bx ip */
2453 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2454};
cf3eccff 2455
ebe24dd4
CL		 2456/* V4T ARM -> ARM long branch stub, PIC. */
2457static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
b38cadfb
NC		 2458{
2459 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2460 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2461 ARM_INSN (0xe12fff1c), /* bx ip */
2462 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2463};
ebe24dd4
CL		 2464
2465/* V4T Thumb -> ARM long branch stub, PIC. */
2466static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
b38cadfb
NC		 2467{
2468 THUMB16_INSN (0x4778), /* bx pc */
2469 THUMB16_INSN (0x46c0), /* nop */
2470 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2471 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
2472 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2473};
ebe24dd4 2474
d3626fb0
CL		 2475/* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2476 architectures. */
ebe24dd4 2477static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
b38cadfb
NC		 2478{
2479 THUMB16_INSN (0xb401), /* push {r0} */
2480 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2481 THUMB16_INSN (0x46fc), /* mov ip, pc */
2482 THUMB16_INSN (0x4484), /* add ip, r0 */
2483 THUMB16_INSN (0xbc01), /* pop {r0} */
2484 THUMB16_INSN (0x4760), /* bx ip */
2485 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2486};
ebe24dd4 2487
d3626fb0
CL		 2488/* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2489 allowed. */
2490static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
b38cadfb
NC		 2491{
2492 THUMB16_INSN (0x4778), /* bx pc */
2493 THUMB16_INSN (0x46c0), /* nop */
2494 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2495 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2496 ARM_INSN (0xe12fff1c), /* bx ip */
2497 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2498};
d3626fb0 2499
0855e32b
NS		 2500/* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2501 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2502static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2503{
b38cadfb
NC		 2504 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2505 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
2506 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
0855e32b
NS		 2507};
2508
2509/* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2510 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2511static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2512{
b38cadfb
NC		 2513 THUMB16_INSN (0x4778), /* bx pc */
2514 THUMB16_INSN (0x46c0), /* nop */
2515 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2516 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
2517 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
0855e32b
NS		 2518};
2519
7a89b94e
NC		 2520/* NaCl ARM -> ARM long branch stub. */
2521static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2522{
2523 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2524 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2525 ARM_INSN (0xe12fff1c), /* bx ip */
2526 ARM_INSN (0xe320f000), /* nop */
2527 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2528 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2529 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2530 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2531};
2532
2533/* NaCl ARM -> ARM long branch stub, PIC. */
2534static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2535{
2536 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2537 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
2538 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2539 ARM_INSN (0xe12fff1c), /* bx ip */
2540 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2541 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2542 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2543 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2544};
2545
2546
48229727
JB		 2547/* Cortex-A8 erratum-workaround stubs. */
2548
2549/* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2550 can't use a conditional branch to reach this stub). */
2551
2552static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
b38cadfb
NC		 2553{
2554 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
2555 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2556 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2557};
48229727
JB		 2558
2559/* Stub used for b.w and bl.w instructions. */
2560
2561static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
b38cadfb
NC		 2562{
2563 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2564};
48229727
JB		 2565
2566static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
b38cadfb
NC		 2567{
2568 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2569};
48229727
JB		 2570
2571/* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2572 instruction (which switches to ARM mode) to point to this stub. Jump to the
2573 real destination using an ARM-mode branch. */
2574
2575static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
b38cadfb
NC		 2576{
2577 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2578};
48229727 2579
9553db3c
NC		 2580/* For each section group there can be a specially created linker section
2581 to hold the stubs for that group. The name of the stub section is based
2582 upon the name of another section within that group with the suffix below
2583 applied.
2584
2585 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2586 create what appeared to be a linker stub section when it actually
2587 contained user code/data. For example, consider this fragment:
b38cadfb 2588
9553db3c
NC		 2589 const char * stubborn_problems[] = { "np" };
2590
2591 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2592 section called:
2593
2594 .data.rel.local.stubborn_problems
2595
2596 This then causes problems in arm32_arm_build_stubs() as it triggers:
2597
2598 // Ignore non-stub sections.
2599 if (!strstr (stub_sec->name, STUB_SUFFIX))
2600 continue;
2601
2602 And so the section would be ignored instead of being processed. Hence
2603 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2604 C identifier. */
2605#define STUB_SUFFIX ".__stub"
906e58ca 2606
738a79f6
CL		 2607/* One entry per long/short branch stub defined above. */
2608#define DEF_STUBS \
2609 DEF_STUB(long_branch_any_any) \
2610 DEF_STUB(long_branch_v4t_arm_thumb) \
2611 DEF_STUB(long_branch_thumb_only) \
2612 DEF_STUB(long_branch_v4t_thumb_thumb) \
2613 DEF_STUB(long_branch_v4t_thumb_arm) \
2614 DEF_STUB(short_branch_v4t_thumb_arm) \
2615 DEF_STUB(long_branch_any_arm_pic) \
2616 DEF_STUB(long_branch_any_thumb_pic) \
2617 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2618 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2619 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
48229727 2620 DEF_STUB(long_branch_thumb_only_pic) \
0855e32b
NS		 2621 DEF_STUB(long_branch_any_tls_pic) \
2622 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
7a89b94e
NC		 2623 DEF_STUB(long_branch_arm_nacl) \
2624 DEF_STUB(long_branch_arm_nacl_pic) \
48229727
JB		 2625 DEF_STUB(a8_veneer_b_cond) \
2626 DEF_STUB(a8_veneer_b) \
2627 DEF_STUB(a8_veneer_bl) \
2628 DEF_STUB(a8_veneer_blx)
738a79f6
CL		 2629
2630#define DEF_STUB(x) arm_stub_##x,
b38cadfb
NC		 2631enum elf32_arm_stub_type
2632{
906e58ca 2633 arm_stub_none,
738a79f6 2634 DEF_STUBS
6a631e86 2635 /* Note the first a8_veneer type. */
eb7c4339 2636 arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond
738a79f6
CL		 2637};
2638#undef DEF_STUB
2639
2640typedef struct
2641{
d3ce72d0 2642 const insn_sequence* template_sequence;
738a79f6
CL		 2643 int template_size;
2644} stub_def;
2645
2646#define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
b38cadfb
NC		 2647static const stub_def stub_definitions[] =
2648{
738a79f6
CL		 2649 {NULL, 0},
2650 DEF_STUBS
906e58ca
NC		 2651};
2652
2653struct elf32_arm_stub_hash_entry
2654{
2655 /* Base hash table entry structure. */
2656 struct bfd_hash_entry root;
2657
2658 /* The stub section. */
2659 asection *stub_sec;
2660
2661 /* Offset within stub_sec of the beginning of this stub. */
2662 bfd_vma stub_offset;
2663
2664 /* Given the symbol's value and its section we can determine its final
2665 value when building the stubs (so the stub knows where to jump). */
2666 bfd_vma target_value;
2667 asection *target_section;
2668
48229727
JB		 2669 /* Offset to apply to relocation referencing target_value. */
2670 bfd_vma target_addend;
2671
2672 /* The instruction which caused this stub to be generated (only valid for
2673 Cortex-A8 erratum workaround stubs at present). */
2674 unsigned long orig_insn;
2675
461a49ca 2676 /* The stub type. */
906e58ca 2677 enum elf32_arm_stub_type stub_type;
461a49ca
DJ		 2678 /* Its encoding size in bytes. */
2679 int stub_size;
2680 /* Its template. */
2681 const insn_sequence *stub_template;
2682 /* The size of the template (number of entries). */
2683 int stub_template_size;
906e58ca
NC		 2684
2685 /* The symbol table entry, if any, that this was derived from. */
2686 struct elf32_arm_link_hash_entry *h;
2687
35fc36a8
RS		 2688 /* Type of branch. */
2689 enum arm_st_branch_type branch_type;
906e58ca
NC		 2690
2691 /* Where this stub is being called from, or, in the case of combined
2692 stub sections, the first input section in the group. */
2693 asection *id_sec;
7413f23f
DJ		 2694
2695 /* The name for the local symbol at the start of this stub. The
2696 stub name in the hash table has to be unique; this does not, so
2697 it can be friendlier. */
2698 char *output_name;
906e58ca
NC		 2699};
2700
e489d0ae
PB		 2701/* Used to build a map of a section. This is required for mixed-endian
2702 code/data. */
2703
2704typedef struct elf32_elf_section_map
2705{
2706 bfd_vma vma;
2707 char type;
2708}
2709elf32_arm_section_map;
2710
c7b8f16e
JB		 2711/* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2712
2713typedef enum
2714{
2715 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2716 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2717 VFP11_ERRATUM_ARM_VENEER,
2718 VFP11_ERRATUM_THUMB_VENEER
2719}
2720elf32_vfp11_erratum_type;
2721
2722typedef struct elf32_vfp11_erratum_list
2723{
2724 struct elf32_vfp11_erratum_list *next;
2725 bfd_vma vma;
2726 union
2727 {
2728 struct
2729 {
2730 struct elf32_vfp11_erratum_list *veneer;
2731 unsigned int vfp_insn;
2732 } b;
2733 struct
2734 {
2735 struct elf32_vfp11_erratum_list *branch;
2736 unsigned int id;
2737 } v;
2738 } u;
2739 elf32_vfp11_erratum_type type;
2740}
2741elf32_vfp11_erratum_list;
2742
a504d23a
LA		 2743/* Information about a STM32L4XX erratum veneer, or a branch to such a
2744 veneer. */
2745typedef enum
2746{
2747 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2748 STM32L4XX_ERRATUM_VENEER
2749}
2750elf32_stm32l4xx_erratum_type;
2751
2752typedef struct elf32_stm32l4xx_erratum_list
2753{
2754 struct elf32_stm32l4xx_erratum_list *next;
2755 bfd_vma vma;
2756 union
2757 {
2758 struct
2759 {
2760 struct elf32_stm32l4xx_erratum_list *veneer;
2761 unsigned int insn;
2762 } b;
2763 struct
2764 {
2765 struct elf32_stm32l4xx_erratum_list *branch;
2766 unsigned int id;
2767 } v;
2768 } u;
2769 elf32_stm32l4xx_erratum_type type;
2770}
2771elf32_stm32l4xx_erratum_list;
2772
2468f9c9
PB		 2773typedef enum
2774{
2775 DELETE_EXIDX_ENTRY,
2776 INSERT_EXIDX_CANTUNWIND_AT_END
2777}
2778arm_unwind_edit_type;
2779
2780/* A (sorted) list of edits to apply to an unwind table. */
2781typedef struct arm_unwind_table_edit
2782{
2783 arm_unwind_edit_type type;
2784 /* Note: we sometimes want to insert an unwind entry corresponding to a
2785 section different from the one we're currently writing out, so record the
2786 (text) section this edit relates to here. */
2787 asection *linked_section;
2788 unsigned int index;
2789 struct arm_unwind_table_edit *next;
2790}
2791arm_unwind_table_edit;
2792
8e3de13a 2793typedef struct _arm_elf_section_data
e489d0ae 2794{
2468f9c9 2795 /* Information about mapping symbols. */
e489d0ae 2796 struct bfd_elf_section_data elf;
8e3de13a 2797 unsigned int mapcount;
c7b8f16e 2798 unsigned int mapsize;
e489d0ae 2799 elf32_arm_section_map *map;
2468f9c9 2800 /* Information about CPU errata. */
c7b8f16e
JB		 2801 unsigned int erratumcount;
2802 elf32_vfp11_erratum_list *erratumlist;
a504d23a
LA		 2803 unsigned int stm32l4xx_erratumcount;
2804 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
491d01d3 2805 unsigned int additional_reloc_count;
2468f9c9
PB		 2806 /* Information about unwind tables. */
2807 union
2808 {
2809 /* Unwind info attached to a text section. */
2810 struct
2811 {
2812 asection *arm_exidx_sec;
2813 } text;
2814
2815 /* Unwind info attached to an .ARM.exidx section. */
2816 struct
2817 {
2818 arm_unwind_table_edit *unwind_edit_list;
2819 arm_unwind_table_edit *unwind_edit_tail;
2820 } exidx;
2821 } u;
8e3de13a
NC		 2822}
2823_arm_elf_section_data;
e489d0ae
PB		 2824
2825#define elf32_arm_section_data(sec) \
8e3de13a 2826 ((_arm_elf_section_data *) elf_section_data (sec))
e489d0ae 2827
48229727
JB		 2828/* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2829 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2830 so may be created multiple times: we use an array of these entries whilst
2831 relaxing which we can refresh easily, then create stubs for each potentially
2832 erratum-triggering instruction once we've settled on a solution. */
2833
b38cadfb
NC		 2834struct a8_erratum_fix
2835{
48229727
JB		 2836 bfd *input_bfd;
2837 asection *section;
2838 bfd_vma offset;
2839 bfd_vma addend;
2840 unsigned long orig_insn;
2841 char *stub_name;
2842 enum elf32_arm_stub_type stub_type;
35fc36a8 2843 enum arm_st_branch_type branch_type;
48229727
JB		 2844};
2845
2846/* A table of relocs applied to branches which might trigger Cortex-A8
2847 erratum. */
2848
b38cadfb
NC		 2849struct a8_erratum_reloc
2850{
48229727
JB		 2851 bfd_vma from;
2852 bfd_vma destination;
92750f34
DJ		 2853 struct elf32_arm_link_hash_entry *hash;
2854 const char *sym_name;
48229727 2855 unsigned int r_type;
35fc36a8 2856 enum arm_st_branch_type branch_type;
48229727
JB		 2857 bfd_boolean non_a8_stub;
2858};
2859
ba93b8ac
DJ		 2860/* The size of the thread control block. */
2861#define TCB_SIZE 8
2862
34e77a92
RS		 2863/* ARM-specific information about a PLT entry, over and above the usual
2864 gotplt_union. */
b38cadfb
NC		 2865struct arm_plt_info
2866{
34e77a92
RS		 2867 /* We reference count Thumb references to a PLT entry separately,
2868 so that we can emit the Thumb trampoline only if needed. */
2869 bfd_signed_vma thumb_refcount;
2870
2871 /* Some references from Thumb code may be eliminated by BL->BLX
2872 conversion, so record them separately. */
2873 bfd_signed_vma maybe_thumb_refcount;
2874
2875 /* How many of the recorded PLT accesses were from non-call relocations.
2876 This information is useful when deciding whether anything takes the
2877 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2878 non-call references to the function should resolve directly to the
2879 real runtime target. */
2880 unsigned int noncall_refcount;
2881
2882 /* Since PLT entries have variable size if the Thumb prologue is
2883 used, we need to record the index into .got.plt instead of
2884 recomputing it from the PLT offset. */
2885 bfd_signed_vma got_offset;
2886};
2887
2888/* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
b38cadfb
NC		 2889struct arm_local_iplt_info
2890{
34e77a92
RS		 2891 /* The information that is usually found in the generic ELF part of
2892 the hash table entry. */
2893 union gotplt_union root;
2894
2895 /* The information that is usually found in the ARM-specific part of
2896 the hash table entry. */
2897 struct arm_plt_info arm;
2898
2899 /* A list of all potential dynamic relocations against this symbol. */
2900 struct elf_dyn_relocs *dyn_relocs;
2901};
2902
0ffa91dd 2903struct elf_arm_obj_tdata
ba93b8ac
DJ		 2904{
2905 struct elf_obj_tdata root;
2906
2907 /* tls_type for each local got entry. */
2908 char *local_got_tls_type;
ee065d83 2909
0855e32b
NS		 2910 /* GOTPLT entries for TLS descriptors. */
2911 bfd_vma *local_tlsdesc_gotent;
2912
34e77a92
RS		 2913 /* Information for local symbols that need entries in .iplt. */
2914 struct arm_local_iplt_info **local_iplt;
2915
bf21ed78
MS		 2916 /* Zero to warn when linking objects with incompatible enum sizes. */
2917 int no_enum_size_warning;
a9dc9481
JM		 2918
2919 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2920 int no_wchar_size_warning;
ba93b8ac
DJ		 2921};
2922
0ffa91dd
NC		 2923#define elf_arm_tdata(bfd) \
2924 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
ba93b8ac 2925
0ffa91dd
NC		 2926#define elf32_arm_local_got_tls_type(bfd) \
2927 (elf_arm_tdata (bfd)->local_got_tls_type)
2928
0855e32b
NS		 2929#define elf32_arm_local_tlsdesc_gotent(bfd) \
2930 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2931
34e77a92
RS		 2932#define elf32_arm_local_iplt(bfd) \
2933 (elf_arm_tdata (bfd)->local_iplt)
2934
0ffa91dd
NC		 2935#define is_arm_elf(bfd) \
2936 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2937 && elf_tdata (bfd) != NULL \
4dfe6ac6 2938 && elf_object_id (bfd) == ARM_ELF_DATA)
ba93b8ac
DJ		 2939
2940static bfd_boolean
2941elf32_arm_mkobject (bfd *abfd)
2942{
0ffa91dd 2943 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
4dfe6ac6 2944 ARM_ELF_DATA);
ba93b8ac
DJ		 2945}
2946
ba93b8ac
DJ		 2947#define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2948
ba96a88f 2949/* Arm ELF linker hash entry. */
252b5132 2950struct elf32_arm_link_hash_entry
b38cadfb
NC		 2951{
2952 struct elf_link_hash_entry root;
252b5132 2953
b38cadfb
NC		 2954 /* Track dynamic relocs copied for this symbol. */
2955 struct elf_dyn_relocs *dyn_relocs;
b7693d02 2956
b38cadfb
NC		 2957 /* ARM-specific PLT information. */
2958 struct arm_plt_info plt;
ba93b8ac
DJ		 2959
2960#define GOT_UNKNOWN 0
2961#define GOT_NORMAL 1
2962#define GOT_TLS_GD 2
2963#define GOT_TLS_IE 4
0855e32b
NS		 2964#define GOT_TLS_GDESC 8
2965#define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
b38cadfb 2966 unsigned int tls_type : 8;
34e77a92 2967
b38cadfb
NC		 2968 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
2969 unsigned int is_iplt : 1;
34e77a92 2970
b38cadfb 2971 unsigned int unused : 23;
a4fd1a8e 2972
b38cadfb
NC		 2973 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
2974 starting at the end of the jump table. */
2975 bfd_vma tlsdesc_got;
0855e32b 2976
b38cadfb
NC		 2977 /* The symbol marking the real symbol location for exported thumb
2978 symbols with Arm stubs. */
2979 struct elf_link_hash_entry *export_glue;
906e58ca 2980
b38cadfb 2981 /* A pointer to the most recently used stub hash entry against this
8029a119 2982 symbol. */
b38cadfb
NC		 2983 struct elf32_arm_stub_hash_entry *stub_cache;
2984};
252b5132 2985
252b5132 2986/* Traverse an arm ELF linker hash table. */
252b5132
RH		 2987#define elf32_arm_link_hash_traverse(table, func, info) \
2988 (elf_link_hash_traverse \
2989 (&(table)->root, \
b7693d02 2990 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
252b5132
RH		 2991 (info)))
2992
2993/* Get the ARM elf linker hash table from a link_info structure. */
2994#define elf32_arm_hash_table(info) \
4dfe6ac6
NC		 2995 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
2996 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
252b5132 2997
906e58ca
NC		 2998#define arm_stub_hash_lookup(table, string, create, copy) \
2999 ((struct elf32_arm_stub_hash_entry *) \
3000 bfd_hash_lookup ((table), (string), (create), (copy)))
3001
21d799b5
NC		 3002/* Array to keep track of which stub sections have been created, and
3003 information on stub grouping. */
3004struct map_stub
3005{
3006 /* This is the section to which stubs in the group will be
3007 attached. */
3008 asection *link_sec;
3009 /* The stub section. */
3010 asection *stub_sec;
3011};
3012
0855e32b
NS		 3013#define elf32_arm_compute_jump_table_size(htab) \
3014 ((htab)->next_tls_desc_index * 4)
3015
9b485d32 3016/* ARM ELF linker hash table. */
252b5132 3017struct elf32_arm_link_hash_table
906e58ca
NC		 3018{
3019 /* The main hash table. */
3020 struct elf_link_hash_table root;
252b5132 3021
906e58ca
NC		 3022 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3023 bfd_size_type thumb_glue_size;
252b5132 3024
906e58ca
NC		 3025 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3026 bfd_size_type arm_glue_size;
252b5132 3027
906e58ca
NC		 3028 /* The size in bytes of section containing the ARMv4 BX veneers. */
3029 bfd_size_type bx_glue_size;
845b51d6 3030
906e58ca
NC		 3031 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3032 veneer has been populated. */
3033 bfd_vma bx_glue_offset[15];
845b51d6 3034
906e58ca
NC		 3035 /* The size in bytes of the section containing glue for VFP11 erratum
3036 veneers. */
3037 bfd_size_type vfp11_erratum_glue_size;
c7b8f16e 3038
a504d23a
LA		 3039 /* The size in bytes of the section containing glue for STM32L4XX erratum
3040 veneers. */
3041 bfd_size_type stm32l4xx_erratum_glue_size;
3042
48229727
JB		 3043 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3044 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3045 elf32_arm_write_section(). */
3046 struct a8_erratum_fix *a8_erratum_fixes;
3047 unsigned int num_a8_erratum_fixes;
3048
906e58ca
NC		 3049 /* An arbitrary input BFD chosen to hold the glue sections. */
3050 bfd * bfd_of_glue_owner;
ba96a88f 3051
906e58ca
NC		 3052 /* Nonzero to output a BE8 image. */
3053 int byteswap_code;
e489d0ae 3054
906e58ca
NC		 3055 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3056 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3057 int target1_is_rel;
9c504268 3058
906e58ca
NC		 3059 /* The relocation to use for R_ARM_TARGET2 relocations. */
3060 int target2_reloc;
eb043451 3061
906e58ca
NC		 3062 /* 0 = Ignore R_ARM_V4BX.
3063 1 = Convert BX to MOV PC.
3064 2 = Generate v4 interworing stubs. */
3065 int fix_v4bx;
319850b4 3066
48229727
JB		 3067 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3068 int fix_cortex_a8;
3069
2de70689
MGD		 3070 /* Whether we should fix the ARM1176 BLX immediate issue. */
3071 int fix_arm1176;
3072
906e58ca
NC		 3073 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3074 int use_blx;
33bfe774 3075
906e58ca
NC		 3076 /* What sort of code sequences we should look for which may trigger the
3077 VFP11 denorm erratum. */
3078 bfd_arm_vfp11_fix vfp11_fix;
c7b8f16e 3079
906e58ca
NC		 3080 /* Global counter for the number of fixes we have emitted. */
3081 int num_vfp11_fixes;
c7b8f16e 3082
a504d23a
LA		 3083 /* What sort of code sequences we should look for which may trigger the
3084 STM32L4XX erratum. */
3085 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3086
3087 /* Global counter for the number of fixes we have emitted. */
3088 int num_stm32l4xx_fixes;
3089
906e58ca
NC		 3090 /* Nonzero to force PIC branch veneers. */
3091 int pic_veneer;
27e55c4d 3092
906e58ca
NC		 3093 /* The number of bytes in the initial entry in the PLT. */
3094 bfd_size_type plt_header_size;
e5a52504 3095
906e58ca
NC		 3096 /* The number of bytes in the subsequent PLT etries. */
3097 bfd_size_type plt_entry_size;
e5a52504 3098
906e58ca
NC		 3099 /* True if the target system is VxWorks. */
3100 int vxworks_p;
00a97672 3101
906e58ca
NC		 3102 /* True if the target system is Symbian OS. */
3103 int symbian_p;
e5a52504 3104
b38cadfb
NC		 3105 /* True if the target system is Native Client. */
3106 int nacl_p;
3107
906e58ca
NC		 3108 /* True if the target uses REL relocations. */
3109 int use_rel;
4e7fd91e 3110
0855e32b
NS		 3111 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3112 bfd_vma next_tls_desc_index;
3113
3114 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3115 bfd_vma num_tls_desc;
3116
906e58ca 3117 /* Short-cuts to get to dynamic linker sections. */
906e58ca
NC		 3118 asection *sdynbss;
3119 asection *srelbss;
5e681ec4 3120
906e58ca
NC		 3121 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3122 asection *srelplt2;
00a97672 3123
0855e32b
NS		 3124 /* The offset into splt of the PLT entry for the TLS descriptor
3125 resolver. Special values are 0, if not necessary (or not found
3126 to be necessary yet), and -1 if needed but not determined
3127 yet. */
3128 bfd_vma dt_tlsdesc_plt;
3129
3130 /* The offset into sgot of the GOT entry used by the PLT entry
3131 above. */
b38cadfb 3132 bfd_vma dt_tlsdesc_got;
0855e32b
NS		 3133
3134 /* Offset in .plt section of tls_arm_trampoline. */
3135 bfd_vma tls_trampoline;
3136
906e58ca
NC		 3137 /* Data for R_ARM_TLS_LDM32 relocations. */
3138 union
3139 {
3140 bfd_signed_vma refcount;
3141 bfd_vma offset;
3142 } tls_ldm_got;
b7693d02 3143
87d72d41
AM		 3144 /* Small local sym cache. */
3145 struct sym_cache sym_cache;
906e58ca
NC		 3146
3147 /* For convenience in allocate_dynrelocs. */
3148 bfd * obfd;
3149
0855e32b
NS		 3150 /* The amount of space used by the reserved portion of the sgotplt
3151 section, plus whatever space is used by the jump slots. */
3152 bfd_vma sgotplt_jump_table_size;
3153
906e58ca
NC		 3154 /* The stub hash table. */
3155 struct bfd_hash_table stub_hash_table;
3156
3157 /* Linker stub bfd. */
3158 bfd *stub_bfd;
3159
3160 /* Linker call-backs. */
7a89b94e 3161 asection * (*add_stub_section) (const char *, asection *, unsigned int);
906e58ca
NC		 3162 void (*layout_sections_again) (void);
3163
3164 /* Array to keep track of which stub sections have been created, and
3165 information on stub grouping. */
21d799b5 3166 struct map_stub *stub_group;
906e58ca 3167
fe33d2fa 3168 /* Number of elements in stub_group. */
7292b3ac 3169 unsigned int top_id;
fe33d2fa 3170
906e58ca
NC		 3171 /* Assorted information used by elf32_arm_size_stubs. */
3172 unsigned int bfd_count;
7292b3ac 3173 unsigned int top_index;
906e58ca
NC		 3174 asection **input_list;
3175};
252b5132 3176
a504d23a
LA		 3177static inline int
3178ctz (unsigned int mask)
3179{
3180#if GCC_VERSION >= 3004
3181 return __builtin_ctz (mask);
3182#else
3183 unsigned int i;
3184
3185 for (i = 0; i < 8 * sizeof (mask); i++)
3186 {
3187 if (mask & 0x1)
3188 break;
3189 mask = (mask >> 1);
3190 }
3191 return i;
3192#endif
3193}
3194
3195static inline int
3196popcount (unsigned int mask)
3197{
3198#if GCC_VERSION >= 3004
3199 return __builtin_popcount (mask);
3200#else
3201 unsigned int i, sum = 0;
3202
3203 for (i = 0; i < 8 * sizeof (mask); i++)
3204 {
3205 if (mask & 0x1)
3206 sum++;
3207 mask = (mask >> 1);
3208 }
3209 return sum;
3210#endif
3211}
3212
780a67af
NC		 3213/* Create an entry in an ARM ELF linker hash table. */
3214
3215static struct bfd_hash_entry *
57e8b36a 3216elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
99059e56
RM		 3217 struct bfd_hash_table * table,
3218 const char * string)
780a67af
NC		 3219{
3220 struct elf32_arm_link_hash_entry * ret =
3221 (struct elf32_arm_link_hash_entry *) entry;
3222
3223 /* Allocate the structure if it has not already been allocated by a
3224 subclass. */
906e58ca 3225 if (ret == NULL)
21d799b5 3226 ret = (struct elf32_arm_link_hash_entry *)
99059e56 3227 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
57e8b36a 3228 if (ret == NULL)
780a67af
NC		 3229 return (struct bfd_hash_entry *) ret;
3230
3231 /* Call the allocation method of the superclass. */
3232 ret = ((struct elf32_arm_link_hash_entry *)
3233 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3234 table, string));
57e8b36a 3235 if (ret != NULL)
b7693d02 3236 {
0bdcacaf 3237 ret->dyn_relocs = NULL;
ba93b8ac 3238 ret->tls_type = GOT_UNKNOWN;
0855e32b 3239 ret->tlsdesc_got = (bfd_vma) -1;
34e77a92
RS		 3240 ret->plt.thumb_refcount = 0;
3241 ret->plt.maybe_thumb_refcount = 0;
3242 ret->plt.noncall_refcount = 0;
3243 ret->plt.got_offset = -1;
3244 ret->is_iplt = FALSE;
a4fd1a8e 3245 ret->export_glue = NULL;
906e58ca
NC		 3246
3247 ret->stub_cache = NULL;
b7693d02 3248 }
780a67af
NC		 3249
3250 return (struct bfd_hash_entry *) ret;
3251}
3252
34e77a92
RS		 3253/* Ensure that we have allocated bookkeeping structures for ABFD's local
3254 symbols. */
3255
3256static bfd_boolean
3257elf32_arm_allocate_local_sym_info (bfd *abfd)
3258{
3259 if (elf_local_got_refcounts (abfd) == NULL)
3260 {
3261 bfd_size_type num_syms;
3262 bfd_size_type size;
3263 char *data;
3264
3265 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3266 size = num_syms * (sizeof (bfd_signed_vma)
3267 + sizeof (struct arm_local_iplt_info *)
3268 + sizeof (bfd_vma)
3269 + sizeof (char));
3270 data = bfd_zalloc (abfd, size);
3271 if (data == NULL)
3272 return FALSE;
3273
3274 elf_local_got_refcounts (abfd) = (bfd_signed_vma *) data;
3275 data += num_syms * sizeof (bfd_signed_vma);
3276
3277 elf32_arm_local_iplt (abfd) = (struct arm_local_iplt_info **) data;
3278 data += num_syms * sizeof (struct arm_local_iplt_info *);
3279
3280 elf32_arm_local_tlsdesc_gotent (abfd) = (bfd_vma *) data;
3281 data += num_syms * sizeof (bfd_vma);
3282
3283 elf32_arm_local_got_tls_type (abfd) = data;
3284 }
3285 return TRUE;
3286}
3287
3288/* Return the .iplt information for local symbol R_SYMNDX, which belongs
3289 to input bfd ABFD. Create the information if it doesn't already exist.
3290 Return null if an allocation fails. */
3291
3292static struct arm_local_iplt_info *
3293elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3294{
3295 struct arm_local_iplt_info **ptr;
3296
3297 if (!elf32_arm_allocate_local_sym_info (abfd))
3298 return NULL;
3299
3300 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3301 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3302 if (*ptr == NULL)
3303 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3304 return *ptr;
3305}
3306
3307/* Try to obtain PLT information for the symbol with index R_SYMNDX
3308 in ABFD's symbol table. If the symbol is global, H points to its
3309 hash table entry, otherwise H is null.
3310
3311 Return true if the symbol does have PLT information. When returning
3312 true, point *ROOT_PLT at the target-independent reference count/offset
3313 union and *ARM_PLT at the ARM-specific information. */
3314
3315static bfd_boolean
3316elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_entry *h,
3317 unsigned long r_symndx, union gotplt_union **root_plt,
3318 struct arm_plt_info **arm_plt)
3319{
3320 struct arm_local_iplt_info *local_iplt;
3321
3322 if (h != NULL)
3323 {
3324 *root_plt = &h->root.plt;
3325 *arm_plt = &h->plt;
3326 return TRUE;
3327 }
3328
3329 if (elf32_arm_local_iplt (abfd) == NULL)
3330 return FALSE;
3331
3332 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3333 if (local_iplt == NULL)
3334 return FALSE;
3335
3336 *root_plt = &local_iplt->root;
3337 *arm_plt = &local_iplt->arm;
3338 return TRUE;
3339}
3340
3341/* Return true if the PLT described by ARM_PLT requires a Thumb stub
3342 before it. */
3343
3344static bfd_boolean
3345elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3346 struct arm_plt_info *arm_plt)
3347{
3348 struct elf32_arm_link_hash_table *htab;
3349
3350 htab = elf32_arm_hash_table (info);
3351 return (arm_plt->thumb_refcount != 0
3352 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0));
3353}
3354
3355/* Return a pointer to the head of the dynamic reloc list that should
3356 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3357 ABFD's symbol table. Return null if an error occurs. */
3358
3359static struct elf_dyn_relocs **
3360elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3361 Elf_Internal_Sym *isym)
3362{
3363 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3364 {
3365 struct arm_local_iplt_info *local_iplt;
3366
3367 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3368 if (local_iplt == NULL)
3369 return NULL;
3370 return &local_iplt->dyn_relocs;
3371 }
3372 else
3373 {
3374 /* Track dynamic relocs needed for local syms too.
3375 We really need local syms available to do this
3376 easily. Oh well. */
3377 asection *s;
3378 void *vpp;
3379
3380 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3381 if (s == NULL)
3382 abort ();
3383
3384 vpp = &elf_section_data (s)->local_dynrel;
3385 return (struct elf_dyn_relocs **) vpp;
3386 }
3387}
3388
906e58ca
NC		 3389/* Initialize an entry in the stub hash table. */
3390
3391static struct bfd_hash_entry *
3392stub_hash_newfunc (struct bfd_hash_entry *entry,
3393 struct bfd_hash_table *table,
3394 const char *string)
3395{
3396 /* Allocate the structure if it has not already been allocated by a
3397 subclass. */
3398 if (entry == NULL)
3399 {
21d799b5 3400 entry = (struct bfd_hash_entry *)
99059e56 3401 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
906e58ca
NC		 3402 if (entry == NULL)
3403 return entry;
3404 }
3405
3406 /* Call the allocation method of the superclass. */
3407 entry = bfd_hash_newfunc (entry, table, string);
3408 if (entry != NULL)
3409 {
3410 struct elf32_arm_stub_hash_entry *eh;
3411
3412 /* Initialize the local fields. */
3413 eh = (struct elf32_arm_stub_hash_entry *) entry;
3414 eh->stub_sec = NULL;
3415 eh->stub_offset = 0;
3416 eh->target_value = 0;
3417 eh->target_section = NULL;
cedfb179
DK		 3418 eh->target_addend = 0;
3419 eh->orig_insn = 0;
906e58ca 3420 eh->stub_type = arm_stub_none;
461a49ca
DJ		 3421 eh->stub_size = 0;
3422 eh->stub_template = NULL;
3423 eh->stub_template_size = 0;
906e58ca
NC		 3424 eh->h = NULL;
3425 eh->id_sec = NULL;
d8d2f433 3426 eh->output_name = NULL;
906e58ca
NC		 3427 }
3428
3429 return entry;
3430}
3431
00a97672 3432/* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
5e681ec4
PB		 3433 shortcuts to them in our hash table. */
3434
3435static bfd_boolean
57e8b36a 3436create_got_section (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3437{
3438 struct elf32_arm_link_hash_table *htab;
3439
e5a52504 3440 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3441 if (htab == NULL)
3442 return FALSE;
3443
e5a52504
MM		 3444 /* BPABI objects never have a GOT, or associated sections. */
3445 if (htab->symbian_p)
3446 return TRUE;
3447
5e681ec4
PB		 3448 if (! _bfd_elf_create_got_section (dynobj, info))
3449 return FALSE;
3450
5e681ec4
PB		 3451 return TRUE;
3452}
3453
34e77a92
RS		 3454/* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3455
3456static bfd_boolean
3457create_ifunc_sections (struct bfd_link_info *info)
3458{
3459 struct elf32_arm_link_hash_table *htab;
3460 const struct elf_backend_data *bed;
3461 bfd *dynobj;
3462 asection *s;
3463 flagword flags;
b38cadfb 3464
34e77a92
RS		 3465 htab = elf32_arm_hash_table (info);
3466 dynobj = htab->root.dynobj;
3467 bed = get_elf_backend_data (dynobj);
3468 flags = bed->dynamic_sec_flags;
3469
3470 if (htab->root.iplt == NULL)
3471 {
3d4d4302
AM		 3472 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3473 flags | SEC_READONLY | SEC_CODE);
34e77a92 3474 if (s == NULL
a0f49396 3475 || !bfd_set_section_alignment (dynobj, s, bed->plt_alignment))
34e77a92
RS		 3476 return FALSE;
3477 htab->root.iplt = s;
3478 }
3479
3480 if (htab->root.irelplt == NULL)
3481 {
3d4d4302
AM		 3482 s = bfd_make_section_anyway_with_flags (dynobj,
3483 RELOC_SECTION (htab, ".iplt"),
3484 flags | SEC_READONLY);
34e77a92 3485 if (s == NULL
a0f49396 3486 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
34e77a92
RS		 3487 return FALSE;
3488 htab->root.irelplt = s;
3489 }
3490
3491 if (htab->root.igotplt == NULL)
3492 {
3d4d4302 3493 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
34e77a92
RS		 3494 if (s == NULL
3495 || !bfd_set_section_alignment (dynobj, s, bed->s->log_file_align))
3496 return FALSE;
3497 htab->root.igotplt = s;
3498 }
3499 return TRUE;
3500}
3501
eed94f8f
NC		 3502/* Determine if we're dealing with a Thumb only architecture. */
3503
3504static bfd_boolean
3505using_thumb_only (struct elf32_arm_link_hash_table *globals)
3506{
3507 int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3508 Tag_CPU_arch);
3509 int profile;
3510
3511 if (arch == TAG_CPU_ARCH_V6_M || arch == TAG_CPU_ARCH_V6S_M)
3512 return TRUE;
3513
3514 if (arch != TAG_CPU_ARCH_V7 && arch != TAG_CPU_ARCH_V7E_M)
3515 return FALSE;
3516
3517 profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3518 Tag_CPU_arch_profile);
3519
3520 return profile == 'M';
3521}
3522
3523/* Determine if we're dealing with a Thumb-2 object. */
3524
3525static bfd_boolean
3526using_thumb2 (struct elf32_arm_link_hash_table *globals)
3527{
3528 int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3529 Tag_CPU_arch);
3530 return arch == TAG_CPU_ARCH_V6T2 || arch >= TAG_CPU_ARCH_V7;
3531}
3532
00a97672
RS		 3533/* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3534 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
5e681ec4
PB		 3535 hash table. */
3536
3537static bfd_boolean
57e8b36a 3538elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
5e681ec4
PB		 3539{
3540 struct elf32_arm_link_hash_table *htab;
3541
3542 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3543 if (htab == NULL)
3544 return FALSE;
3545
362d30a1 3546 if (!htab->root.sgot && !create_got_section (dynobj, info))
5e681ec4
PB		 3547 return FALSE;
3548
3549 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3550 return FALSE;
3551
3d4d4302 3552 htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss");
0e1862bb 3553 if (!bfd_link_pic (info))
3d4d4302
AM		 3554 htab->srelbss = bfd_get_linker_section (dynobj,
3555 RELOC_SECTION (htab, ".bss"));
00a97672
RS		 3556
3557 if (htab->vxworks_p)
3558 {
3559 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3560 return FALSE;
3561
0e1862bb 3562 if (bfd_link_pic (info))
00a97672
RS		 3563 {
3564 htab->plt_header_size = 0;
3565 htab->plt_entry_size
3566 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3567 }
3568 else
3569 {
3570 htab->plt_header_size
3571 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3572 htab->plt_entry_size
3573 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3574 }
3575 }
eed94f8f
NC		 3576 else
3577 {
3578 /* PR ld/16017
3579 Test for thumb only architectures. Note - we cannot just call
3580 using_thumb_only() as the attributes in the output bfd have not been
3581 initialised at this point, so instead we use the input bfd. */
3582 bfd * saved_obfd = htab->obfd;
3583
3584 htab->obfd = dynobj;
3585 if (using_thumb_only (htab))
3586 {
3587 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
3588 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
3589 }
3590 htab->obfd = saved_obfd;
3591 }
5e681ec4 3592
362d30a1
RS		 3593 if (!htab->root.splt
3594 || !htab->root.srelplt
e5a52504 3595 || !htab->sdynbss
0e1862bb 3596 || (!bfd_link_pic (info) && !htab->srelbss))
5e681ec4
PB		 3597 abort ();
3598
3599 return TRUE;
3600}
3601
906e58ca
NC		 3602/* Copy the extra info we tack onto an elf_link_hash_entry. */
3603
3604static void
3605elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
3606 struct elf_link_hash_entry *dir,
3607 struct elf_link_hash_entry *ind)
3608{
3609 struct elf32_arm_link_hash_entry *edir, *eind;
3610
3611 edir = (struct elf32_arm_link_hash_entry *) dir;
3612 eind = (struct elf32_arm_link_hash_entry *) ind;
3613
0bdcacaf 3614 if (eind->dyn_relocs != NULL)
906e58ca 3615 {
0bdcacaf 3616 if (edir->dyn_relocs != NULL)
906e58ca 3617 {
0bdcacaf
RS		 3618 struct elf_dyn_relocs **pp;
3619 struct elf_dyn_relocs *p;
906e58ca
NC		 3620
3621 /* Add reloc counts against the indirect sym to the direct sym
3622 list. Merge any entries against the same section. */
0bdcacaf 3623 for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
906e58ca 3624 {
0bdcacaf 3625 struct elf_dyn_relocs *q;
906e58ca 3626
0bdcacaf
RS		 3627 for (q = edir->dyn_relocs; q != NULL; q = q->next)
3628 if (q->sec == p->sec)
906e58ca
NC		 3629 {
3630 q->pc_count += p->pc_count;
3631 q->count += p->count;
3632 *pp = p->next;
3633 break;
3634 }
3635 if (q == NULL)
3636 pp = &p->next;
3637 }
0bdcacaf 3638 *pp = edir->dyn_relocs;
906e58ca
NC		 3639 }
3640
0bdcacaf
RS		 3641 edir->dyn_relocs = eind->dyn_relocs;
3642 eind->dyn_relocs = NULL;
906e58ca
NC		 3643 }
3644
3645 if (ind->root.type == bfd_link_hash_indirect)
3646 {
3647 /* Copy over PLT info. */
34e77a92
RS		 3648 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
3649 eind->plt.thumb_refcount = 0;
3650 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
3651 eind->plt.maybe_thumb_refcount = 0;
3652 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
3653 eind->plt.noncall_refcount = 0;
3654
3655 /* We should only allocate a function to .iplt once the final
3656 symbol information is known. */
3657 BFD_ASSERT (!eind->is_iplt);
906e58ca
NC		 3658
3659 if (dir->got.refcount <= 0)
3660 {
3661 edir->tls_type = eind->tls_type;
3662 eind->tls_type = GOT_UNKNOWN;
3663 }
3664 }
3665
3666 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
3667}
3668
68faa637
AM		 3669/* Destroy an ARM elf linker hash table. */
3670
3671static void
d495ab0d 3672elf32_arm_link_hash_table_free (bfd *obfd)
68faa637
AM		 3673{
3674 struct elf32_arm_link_hash_table *ret
d495ab0d 3675 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
68faa637
AM		 3676
3677 bfd_hash_table_free (&ret->stub_hash_table);
d495ab0d 3678 _bfd_elf_link_hash_table_free (obfd);
68faa637
AM		 3679}
3680
906e58ca
NC		 3681/* Create an ARM elf linker hash table. */
3682
3683static struct bfd_link_hash_table *
3684elf32_arm_link_hash_table_create (bfd *abfd)
3685{
3686 struct elf32_arm_link_hash_table *ret;
3687 bfd_size_type amt = sizeof (struct elf32_arm_link_hash_table);
3688
7bf52ea2 3689 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
906e58ca
NC		 3690 if (ret == NULL)
3691 return NULL;
3692
3693 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
3694 elf32_arm_link_hash_newfunc,
4dfe6ac6
NC		 3695 sizeof (struct elf32_arm_link_hash_entry),
3696 ARM_ELF_DATA))
906e58ca
NC		 3697 {
3698 free (ret);
3699 return NULL;
3700 }
3701
906e58ca 3702 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
a504d23a 3703 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
906e58ca
NC		 3704#ifdef FOUR_WORD_PLT
3705 ret->plt_header_size = 16;
3706 ret->plt_entry_size = 16;
3707#else
3708 ret->plt_header_size = 20;
1db37fe6 3709 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
906e58ca 3710#endif
906e58ca 3711 ret->use_rel = 1;
906e58ca 3712 ret->obfd = abfd;
906e58ca
NC		 3713
3714 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
3715 sizeof (struct elf32_arm_stub_hash_entry)))
3716 {
d495ab0d 3717 _bfd_elf_link_hash_table_free (abfd);
906e58ca
NC		 3718 return NULL;
3719 }
d495ab0d 3720 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
906e58ca
NC		 3721
3722 return &ret->root.root;
3723}
3724
cd1dac3d
DG		 3725/* Determine what kind of NOPs are available. */
3726
3727static bfd_boolean
3728arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
3729{
3730 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3731 Tag_CPU_arch);
3732 return arch == TAG_CPU_ARCH_V6T2
3733 || arch == TAG_CPU_ARCH_V6K
9e3c6df6
PB		 3734 || arch == TAG_CPU_ARCH_V7
3735 || arch == TAG_CPU_ARCH_V7E_M;
cd1dac3d
DG		 3736}
3737
3738static bfd_boolean
3739arch_has_thumb2_nop (struct elf32_arm_link_hash_table *globals)
3740{
3741 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3742 Tag_CPU_arch);
9e3c6df6
PB		 3743 return (arch == TAG_CPU_ARCH_V6T2 || arch == TAG_CPU_ARCH_V7
3744 || arch == TAG_CPU_ARCH_V7E_M);
cd1dac3d
DG		 3745}
3746
f4ac8484
DJ		 3747static bfd_boolean
3748arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
3749{
3750 switch (stub_type)
3751 {
fea2b4d6
CL		 3752 case arm_stub_long_branch_thumb_only:
3753 case arm_stub_long_branch_v4t_thumb_arm:
3754 case arm_stub_short_branch_v4t_thumb_arm:
ebe24dd4 3755 case arm_stub_long_branch_v4t_thumb_arm_pic:
12352d3f 3756 case arm_stub_long_branch_v4t_thumb_tls_pic:
ebe24dd4 3757 case arm_stub_long_branch_thumb_only_pic:
f4ac8484
DJ		 3758 return TRUE;
3759 case arm_stub_none:
3760 BFD_FAIL ();
3761 return FALSE;
3762 break;
3763 default:
3764 return FALSE;
3765 }
3766}
3767
906e58ca
NC		 3768/* Determine the type of stub needed, if any, for a call. */
3769
3770static enum elf32_arm_stub_type
3771arm_type_of_stub (struct bfd_link_info *info,
3772 asection *input_sec,
3773 const Elf_Internal_Rela *rel,
34e77a92 3774 unsigned char st_type,
35fc36a8 3775 enum arm_st_branch_type *actual_branch_type,
906e58ca 3776 struct elf32_arm_link_hash_entry *hash,
c820be07
NC		 3777 bfd_vma destination,
3778 asection *sym_sec,
3779 bfd *input_bfd,
3780 const char *name)
906e58ca
NC		 3781{
3782 bfd_vma location;
3783 bfd_signed_vma branch_offset;
3784 unsigned int r_type;
3785 struct elf32_arm_link_hash_table * globals;
3786 int thumb2;
3787 int thumb_only;
3788 enum elf32_arm_stub_type stub_type = arm_stub_none;
5fa9e92f 3789 int use_plt = 0;
35fc36a8 3790 enum arm_st_branch_type branch_type = *actual_branch_type;
34e77a92
RS		 3791 union gotplt_union *root_plt;
3792 struct arm_plt_info *arm_plt;
906e58ca 3793
35fc36a8 3794 if (branch_type == ST_BRANCH_LONG)
da5938a2
NC		 3795 return stub_type;
3796
906e58ca 3797 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 3798 if (globals == NULL)
3799 return stub_type;
906e58ca
NC		 3800
3801 thumb_only = using_thumb_only (globals);
3802
3803 thumb2 = using_thumb2 (globals);
3804
3805 /* Determine where the call point is. */
3806 location = (input_sec->output_offset
3807 + input_sec->output_section->vma
3808 + rel->r_offset);
3809
906e58ca
NC		 3810 r_type = ELF32_R_TYPE (rel->r_info);
3811
39f21624
NC		 3812 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3813 are considering a function call relocation. */
c5423981
TG		 3814 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
3815 || r_type == R_ARM_THM_JUMP19)
39f21624
NC		 3816 && branch_type == ST_BRANCH_TO_ARM)
3817 branch_type = ST_BRANCH_TO_THUMB;
3818
34e77a92
RS		 3819 /* For TLS call relocs, it is the caller's responsibility to provide
3820 the address of the appropriate trampoline. */
3821 if (r_type != R_ARM_TLS_CALL
3822 && r_type != R_ARM_THM_TLS_CALL
3823 && elf32_arm_get_plt_info (input_bfd, hash, ELF32_R_SYM (rel->r_info),
3824 &root_plt, &arm_plt)
3825 && root_plt->offset != (bfd_vma) -1)
5fa9e92f 3826 {
34e77a92 3827 asection *splt;
fe33d2fa 3828
34e77a92
RS		 3829 if (hash == NULL || hash->is_iplt)
3830 splt = globals->root.iplt;
3831 else
3832 splt = globals->root.splt;
3833 if (splt != NULL)
b38cadfb 3834 {
34e77a92
RS		 3835 use_plt = 1;
3836
3837 /* Note when dealing with PLT entries: the main PLT stub is in
3838 ARM mode, so if the branch is in Thumb mode, another
3839 Thumb->ARM stub will be inserted later just before the ARM
3840 PLT stub. We don't take this extra distance into account
3841 here, because if a long branch stub is needed, we'll add a
3842 Thumb->Arm one and branch directly to the ARM PLT entry
3843 because it avoids spreading offset corrections in several
3844 places. */
3845
3846 destination = (splt->output_section->vma
3847 + splt->output_offset
3848 + root_plt->offset);
3849 st_type = STT_FUNC;
3850 branch_type = ST_BRANCH_TO_ARM;
3851 }
5fa9e92f 3852 }
34e77a92
RS		 3853 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3854 BFD_ASSERT (st_type != STT_GNU_IFUNC);
906e58ca 3855
fe33d2fa
CL		 3856 branch_offset = (bfd_signed_vma)(destination - location);
3857
0855e32b 3858 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
c5423981 3859 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
906e58ca 3860 {
5fa9e92f
CL		 3861 /* Handle cases where:
3862 - this call goes too far (different Thumb/Thumb2 max
99059e56 3863 distance)
155d87d7 3864 - it's a Thumb->Arm call and blx is not available, or it's a
99059e56
RM		 3865 Thumb->Arm branch (not bl). A stub is needed in this case,
3866 but only if this call is not through a PLT entry. Indeed,
3867 PLT stubs handle mode switching already.
5fa9e92f 3868 */
906e58ca
NC		 3869 if ((!thumb2
3870 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
3871 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
3872 || (thumb2
3873 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
3874 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
c5423981
TG		 3875 || (thumb2
3876 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
3877 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
3878 && (r_type == R_ARM_THM_JUMP19))
35fc36a8 3879 || (branch_type == ST_BRANCH_TO_ARM
0855e32b
NS		 3880 && (((r_type == R_ARM_THM_CALL
3881 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
c5423981
TG		 3882 || (r_type == R_ARM_THM_JUMP24)
3883 || (r_type == R_ARM_THM_JUMP19))
5fa9e92f 3884 && !use_plt))
906e58ca 3885 {
35fc36a8 3886 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 3887 {
3888 /* Thumb to thumb. */
3889 if (!thumb_only)
3890 {
0e1862bb 3891 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3892 /* PIC stubs. */
155d87d7 3893 ? ((globals->use_blx
9553db3c 3894 && (r_type == R_ARM_THM_CALL))
155d87d7
CL		 3895 /* V5T and above. Stub starts with ARM code, so
3896 we must be able to switch mode before
3897 reaching it, which is only possible for 'bl'
3898 (ie R_ARM_THM_CALL relocation). */
cf3eccff 3899 ? arm_stub_long_branch_any_thumb_pic
ebe24dd4 3900 /* On V4T, use Thumb code only. */
d3626fb0 3901 : arm_stub_long_branch_v4t_thumb_thumb_pic)
c2b4a39d
CL		 3902
3903 /* non-PIC stubs. */
155d87d7 3904 : ((globals->use_blx
9553db3c 3905 && (r_type == R_ARM_THM_CALL))
c2b4a39d
CL		 3906 /* V5T and above. */
3907 ? arm_stub_long_branch_any_any
3908 /* V4T. */
d3626fb0 3909 : arm_stub_long_branch_v4t_thumb_thumb);
906e58ca
NC		 3910 }
3911 else
3912 {
0e1862bb 3913 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
ebe24dd4
CL		 3914 /* PIC stub. */
3915 ? arm_stub_long_branch_thumb_only_pic
c2b4a39d
CL		 3916 /* non-PIC stub. */
3917 : arm_stub_long_branch_thumb_only;
906e58ca
NC		 3918 }
3919 }
3920 else
3921 {
3922 /* Thumb to arm. */
c820be07
NC		 3923 if (sym_sec != NULL
3924 && sym_sec->owner != NULL
3925 && !INTERWORK_FLAG (sym_sec->owner))
3926 {
3927 (*_bfd_error_handler)
3928 (_("%B(%s): warning: interworking not enabled.\n"
3929 " first occurrence: %B: Thumb call to ARM"),
3930 sym_sec->owner, input_bfd, name);
3931 }
3932
0855e32b 3933 stub_type =
0e1862bb 3934 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3935 /* PIC stubs. */
0855e32b 3936 ? (r_type == R_ARM_THM_TLS_CALL
6a631e86 3937 /* TLS PIC stubs. */
0855e32b
NS		 3938 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
3939 : arm_stub_long_branch_v4t_thumb_tls_pic)
3940 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
3941 /* V5T PIC and above. */
3942 ? arm_stub_long_branch_any_arm_pic
3943 /* V4T PIC stub. */
3944 : arm_stub_long_branch_v4t_thumb_arm_pic))
c2b4a39d
CL		 3945
3946 /* non-PIC stubs. */
0855e32b 3947 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
c2b4a39d
CL		 3948 /* V5T and above. */
3949 ? arm_stub_long_branch_any_any
3950 /* V4T. */
3951 : arm_stub_long_branch_v4t_thumb_arm);
c820be07
NC		 3952
3953 /* Handle v4t short branches. */
fea2b4d6 3954 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
c820be07
NC		 3955 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
3956 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
fea2b4d6 3957 stub_type = arm_stub_short_branch_v4t_thumb_arm;
906e58ca
NC		 3958 }
3959 }
3960 }
fe33d2fa
CL		 3961 else if (r_type == R_ARM_CALL
3962 || r_type == R_ARM_JUMP24
0855e32b
NS		 3963 || r_type == R_ARM_PLT32
3964 || r_type == R_ARM_TLS_CALL)
906e58ca 3965 {
35fc36a8 3966 if (branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 3967 {
3968 /* Arm to thumb. */
c820be07
NC		 3969
3970 if (sym_sec != NULL
3971 && sym_sec->owner != NULL
3972 && !INTERWORK_FLAG (sym_sec->owner))
3973 {
3974 (*_bfd_error_handler)
3975 (_("%B(%s): warning: interworking not enabled.\n"
c2b4a39d 3976 " first occurrence: %B: ARM call to Thumb"),
c820be07
NC		 3977 sym_sec->owner, input_bfd, name);
3978 }
3979
3980 /* We have an extra 2-bytes reach because of
3981 the mode change (bit 24 (H) of BLX encoding). */
4116d8d7
PB		 3982 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
3983 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
0855e32b 3984 || (r_type == R_ARM_CALL && !globals->use_blx)
4116d8d7
PB		 3985 || (r_type == R_ARM_JUMP24)
3986 || (r_type == R_ARM_PLT32))
906e58ca 3987 {
0e1862bb 3988 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 3989 /* PIC stubs. */
ebe24dd4
CL		 3990 ? ((globals->use_blx)
3991 /* V5T and above. */
3992 ? arm_stub_long_branch_any_thumb_pic
3993 /* V4T stub. */
3994 : arm_stub_long_branch_v4t_arm_thumb_pic)
3995
c2b4a39d
CL		 3996 /* non-PIC stubs. */
3997 : ((globals->use_blx)
3998 /* V5T and above. */
3999 ? arm_stub_long_branch_any_any
4000 /* V4T. */
4001 : arm_stub_long_branch_v4t_arm_thumb);
906e58ca
NC		 4002 }
4003 }
4004 else
4005 {
4006 /* Arm to arm. */
4007 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4008 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4009 {
0855e32b 4010 stub_type =
0e1862bb 4011 (bfd_link_pic (info) | globals->pic_veneer)
c2b4a39d 4012 /* PIC stubs. */
0855e32b 4013 ? (r_type == R_ARM_TLS_CALL
6a631e86 4014 /* TLS PIC Stub. */
0855e32b 4015 ? arm_stub_long_branch_any_tls_pic
7a89b94e
NC		 4016 : (globals->nacl_p
4017 ? arm_stub_long_branch_arm_nacl_pic
4018 : arm_stub_long_branch_any_arm_pic))
c2b4a39d 4019 /* non-PIC stubs. */
7a89b94e
NC		 4020 : (globals->nacl_p
4021 ? arm_stub_long_branch_arm_nacl
4022 : arm_stub_long_branch_any_any);
906e58ca
NC		 4023 }
4024 }
4025 }
4026
fe33d2fa
CL		 4027 /* If a stub is needed, record the actual destination type. */
4028 if (stub_type != arm_stub_none)
35fc36a8 4029 *actual_branch_type = branch_type;
fe33d2fa 4030
906e58ca
NC		 4031 return stub_type;
4032}
4033
4034/* Build a name for an entry in the stub hash table. */
4035
4036static char *
4037elf32_arm_stub_name (const asection *input_section,
4038 const asection *sym_sec,
4039 const struct elf32_arm_link_hash_entry *hash,
fe33d2fa
CL		 4040 const Elf_Internal_Rela *rel,
4041 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4042{
4043 char *stub_name;
4044 bfd_size_type len;
4045
4046 if (hash)
4047 {
fe33d2fa 4048 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
21d799b5 4049 stub_name = (char *) bfd_malloc (len);
906e58ca 4050 if (stub_name != NULL)
fe33d2fa 4051 sprintf (stub_name, "%08x_%s+%x_%d",
906e58ca
NC		 4052 input_section->id & 0xffffffff,
4053 hash->root.root.root.string,
fe33d2fa
CL		 4054 (int) rel->r_addend & 0xffffffff,
4055 (int) stub_type);
906e58ca
NC		 4056 }
4057 else
4058 {
fe33d2fa 4059 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
21d799b5 4060 stub_name = (char *) bfd_malloc (len);
906e58ca 4061 if (stub_name != NULL)
fe33d2fa 4062 sprintf (stub_name, "%08x_%x:%x+%x_%d",
906e58ca
NC		 4063 input_section->id & 0xffffffff,
4064 sym_sec->id & 0xffffffff,
0855e32b
NS		 4065 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4066 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4067 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
fe33d2fa
CL		 4068 (int) rel->r_addend & 0xffffffff,
4069 (int) stub_type);
906e58ca
NC		 4070 }
4071
4072 return stub_name;
4073}
4074
4075/* Look up an entry in the stub hash. Stub entries are cached because
4076 creating the stub name takes a bit of time. */
4077
4078static struct elf32_arm_stub_hash_entry *
4079elf32_arm_get_stub_entry (const asection *input_section,
4080 const asection *sym_sec,
4081 struct elf_link_hash_entry *hash,
4082 const Elf_Internal_Rela *rel,
fe33d2fa
CL		 4083 struct elf32_arm_link_hash_table *htab,
4084 enum elf32_arm_stub_type stub_type)
906e58ca
NC		 4085{
4086 struct elf32_arm_stub_hash_entry *stub_entry;
4087 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4088 const asection *id_sec;
4089
4090 if ((input_section->flags & SEC_CODE) == 0)
4091 return NULL;
4092
4093 /* If this input section is part of a group of sections sharing one
4094 stub section, then use the id of the first section in the group.
4095 Stub names need to include a section id, as there may well be
4096 more than one stub used to reach say, printf, and we need to
4097 distinguish between them. */
4098 id_sec = htab->stub_group[input_section->id].link_sec;
4099
4100 if (h != NULL && h->stub_cache != NULL
4101 && h->stub_cache->h == h
fe33d2fa
CL		 4102 && h->stub_cache->id_sec == id_sec
4103 && h->stub_cache->stub_type == stub_type)
906e58ca
NC		 4104 {
4105 stub_entry = h->stub_cache;
4106 }
4107 else
4108 {
4109 char *stub_name;
4110
fe33d2fa 4111 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
906e58ca
NC		 4112 if (stub_name == NULL)
4113 return NULL;
4114
4115 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4116 stub_name, FALSE, FALSE);
4117 if (h != NULL)
4118 h->stub_cache = stub_entry;
4119
4120 free (stub_name);
4121 }
4122
4123 return stub_entry;
4124}
4125
48229727 4126/* Find or create a stub section. Returns a pointer to the stub section, and
b38cadfb 4127 the section to which the stub section will be attached (in *LINK_SEC_P).
48229727 4128 LINK_SEC_P may be NULL. */
906e58ca 4129
48229727
JB		 4130static asection *
4131elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
4132 struct elf32_arm_link_hash_table *htab)
906e58ca
NC		 4133{
4134 asection *link_sec;
4135 asection *stub_sec;
906e58ca
NC		 4136
4137 link_sec = htab->stub_group[section->id].link_sec;
9553db3c 4138 BFD_ASSERT (link_sec != NULL);
906e58ca 4139 stub_sec = htab->stub_group[section->id].stub_sec;
9553db3c 4140
906e58ca
NC		 4141 if (stub_sec == NULL)
4142 {
4143 stub_sec = htab->stub_group[link_sec->id].stub_sec;
4144 if (stub_sec == NULL)
4145 {
4146 size_t namelen;
4147 bfd_size_type len;
4148 char *s_name;
4149
4150 namelen = strlen (link_sec->name);
4151 len = namelen + sizeof (STUB_SUFFIX);
21d799b5 4152 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
906e58ca
NC		 4153 if (s_name == NULL)
4154 return NULL;
4155
4156 memcpy (s_name, link_sec->name, namelen);
4157 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
7a89b94e
NC		 4158 stub_sec = (*htab->add_stub_section) (s_name, link_sec,
4159 htab->nacl_p ? 4 : 3);
906e58ca
NC		 4160 if (stub_sec == NULL)
4161 return NULL;
4162 htab->stub_group[link_sec->id].stub_sec = stub_sec;
4163 }
4164 htab->stub_group[section->id].stub_sec = stub_sec;
4165 }
b38cadfb 4166
48229727
JB		 4167 if (link_sec_p)
4168 *link_sec_p = link_sec;
b38cadfb 4169
48229727
JB		 4170 return stub_sec;
4171}
4172
4173/* Add a new stub entry to the stub hash. Not all fields of the new
4174 stub entry are initialised. */
4175
4176static struct elf32_arm_stub_hash_entry *
4177elf32_arm_add_stub (const char *stub_name,
4178 asection *section,
4179 struct elf32_arm_link_hash_table *htab)
4180{
4181 asection *link_sec;
4182 asection *stub_sec;
4183 struct elf32_arm_stub_hash_entry *stub_entry;
4184
4185 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab);
4186 if (stub_sec == NULL)
4187 return NULL;
906e58ca
NC		 4188
4189 /* Enter this entry into the linker stub hash table. */
4190 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4191 TRUE, FALSE);
4192 if (stub_entry == NULL)
4193 {
4194 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
4195 section->owner,
4196 stub_name);
4197 return NULL;
4198 }
4199
4200 stub_entry->stub_sec = stub_sec;
4201 stub_entry->stub_offset = 0;
4202 stub_entry->id_sec = link_sec;
4203
906e58ca
NC		 4204 return stub_entry;
4205}
4206
4207/* Store an Arm insn into an output section not processed by
4208 elf32_arm_write_section. */
4209
4210static void
8029a119
NC		 4211put_arm_insn (struct elf32_arm_link_hash_table * htab,
4212 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4213{
4214 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4215 bfd_putl32 (val, ptr);
4216 else
4217 bfd_putb32 (val, ptr);
4218}
4219
4220/* Store a 16-bit Thumb insn into an output section not processed by
4221 elf32_arm_write_section. */
4222
4223static void
8029a119
NC		 4224put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4225 bfd * output_bfd, bfd_vma val, void * ptr)
906e58ca
NC		 4226{
4227 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4228 bfd_putl16 (val, ptr);
4229 else
4230 bfd_putb16 (val, ptr);
4231}
4232
a504d23a
LA		 4233/* Store a Thumb2 insn into an output section not processed by
4234 elf32_arm_write_section. */
4235
4236static void
4237put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
4238 bfd * output_bfd, bfd_vma val, void * ptr)
4239{
4240 /* T2 instructions are 16-bit streamed. */
4241 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4242 {
4243 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4244 bfd_putl16 ((val & 0xffff), ptr + 2);
4245 }
4246 else
4247 {
4248 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4249 bfd_putb16 ((val & 0xffff), ptr + 2);
4250 }
4251}
4252
0855e32b
NS		 4253/* If it's possible to change R_TYPE to a more efficient access
4254 model, return the new reloc type. */
4255
4256static unsigned
b38cadfb 4257elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
0855e32b
NS		 4258 struct elf_link_hash_entry *h)
4259{
4260 int is_local = (h == NULL);
4261
0e1862bb
L		 4262 if (bfd_link_pic (info)
4263 || (h && h->root.type == bfd_link_hash_undefweak))
0855e32b
NS		 4264 return r_type;
4265
b38cadfb 4266 /* We do not support relaxations for Old TLS models. */
0855e32b
NS		 4267 switch (r_type)
4268 {
4269 case R_ARM_TLS_GOTDESC:
4270 case R_ARM_TLS_CALL:
4271 case R_ARM_THM_TLS_CALL:
4272 case R_ARM_TLS_DESCSEQ:
4273 case R_ARM_THM_TLS_DESCSEQ:
4274 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4275 }
4276
4277 return r_type;
4278}
4279
48229727
JB		 4280static bfd_reloc_status_type elf32_arm_final_link_relocate
4281 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4282 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
34e77a92
RS		 4283 const char *, unsigned char, enum arm_st_branch_type,
4284 struct elf_link_hash_entry *, bfd_boolean *, char **);
48229727 4285
4563a860
JB		 4286static unsigned int
4287arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4288{
4289 switch (stub_type)
4290 {
4291 case arm_stub_a8_veneer_b_cond:
4292 case arm_stub_a8_veneer_b:
4293 case arm_stub_a8_veneer_bl:
4294 return 2;
4295
4296 case arm_stub_long_branch_any_any:
4297 case arm_stub_long_branch_v4t_arm_thumb:
4298 case arm_stub_long_branch_thumb_only:
4299 case arm_stub_long_branch_v4t_thumb_thumb:
4300 case arm_stub_long_branch_v4t_thumb_arm:
4301 case arm_stub_short_branch_v4t_thumb_arm:
4302 case arm_stub_long_branch_any_arm_pic:
4303 case arm_stub_long_branch_any_thumb_pic:
4304 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4305 case arm_stub_long_branch_v4t_arm_thumb_pic:
4306 case arm_stub_long_branch_v4t_thumb_arm_pic:
4307 case arm_stub_long_branch_thumb_only_pic:
0855e32b
NS		 4308 case arm_stub_long_branch_any_tls_pic:
4309 case arm_stub_long_branch_v4t_thumb_tls_pic:
4563a860
JB		 4310 case arm_stub_a8_veneer_blx:
4311 return 4;
b38cadfb 4312
7a89b94e
NC		 4313 case arm_stub_long_branch_arm_nacl:
4314 case arm_stub_long_branch_arm_nacl_pic:
4315 return 16;
4316
4563a860
JB		 4317 default:
4318 abort (); /* Should be unreachable. */
4319 }
4320}
4321
906e58ca
NC		 4322static bfd_boolean
4323arm_build_one_stub (struct bfd_hash_entry *gen_entry,
4324 void * in_arg)
4325{
7a89b94e 4326#define MAXRELOCS 3
906e58ca 4327 struct elf32_arm_stub_hash_entry *stub_entry;
4dfe6ac6 4328 struct elf32_arm_link_hash_table *globals;
906e58ca 4329 struct bfd_link_info *info;
906e58ca
NC		 4330 asection *stub_sec;
4331 bfd *stub_bfd;
906e58ca
NC		 4332 bfd_byte *loc;
4333 bfd_vma sym_value;
4334 int template_size;
4335 int size;
d3ce72d0 4336 const insn_sequence *template_sequence;
906e58ca 4337 int i;
48229727
JB		 4338 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
4339 int stub_reloc_offset[MAXRELOCS] = {0, 0};
4340 int nrelocs = 0;
906e58ca
NC		 4341
4342 /* Massage our args to the form they really have. */
4343 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
4344 info = (struct bfd_link_info *) in_arg;
4345
4346 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 4347 if (globals == NULL)
4348 return FALSE;
906e58ca 4349
906e58ca
NC		 4350 stub_sec = stub_entry->stub_sec;
4351
4dfe6ac6 4352 if ((globals->fix_cortex_a8 < 0)
4563a860
JB		 4353 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
4354 /* We have to do less-strictly-aligned fixes last. */
eb7c4339 4355 return TRUE;
fe33d2fa 4356
906e58ca
NC		 4357 /* Make a note of the offset within the stubs for this entry. */
4358 stub_entry->stub_offset = stub_sec->size;
4359 loc = stub_sec->contents + stub_entry->stub_offset;
4360
4361 stub_bfd = stub_sec->owner;
4362
906e58ca
NC		 4363 /* This is the address of the stub destination. */
4364 sym_value = (stub_entry->target_value
4365 + stub_entry->target_section->output_offset
4366 + stub_entry->target_section->output_section->vma);
4367
d3ce72d0 4368 template_sequence = stub_entry->stub_template;
461a49ca 4369 template_size = stub_entry->stub_template_size;
906e58ca
NC		 4370
4371 size = 0;
461a49ca 4372 for (i = 0; i < template_size; i++)
906e58ca 4373 {
d3ce72d0 4374 switch (template_sequence[i].type)
461a49ca
DJ		 4375 {
4376 case THUMB16_TYPE:
48229727 4377 {
d3ce72d0
NC		 4378 bfd_vma data = (bfd_vma) template_sequence[i].data;
4379 if (template_sequence[i].reloc_addend != 0)
48229727 4380 {
99059e56
RM		 4381 /* We've borrowed the reloc_addend field to mean we should
4382 insert a condition code into this (Thumb-1 branch)
4383 instruction. See THUMB16_BCOND_INSN. */
4384 BFD_ASSERT ((data & 0xff00) == 0xd000);
4385 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
48229727 4386 }
fe33d2fa 4387 bfd_put_16 (stub_bfd, data, loc + size);
48229727
JB		 4388 size += 2;
4389 }
461a49ca 4390 break;
906e58ca 4391
48229727 4392 case THUMB32_TYPE:
fe33d2fa
CL		 4393 bfd_put_16 (stub_bfd,
4394 (template_sequence[i].data >> 16) & 0xffff,
4395 loc + size);
4396 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
4397 loc + size + 2);
99059e56
RM		 4398 if (template_sequence[i].r_type != R_ARM_NONE)
4399 {
4400 stub_reloc_idx[nrelocs] = i;
4401 stub_reloc_offset[nrelocs++] = size;
4402 }
4403 size += 4;
4404 break;
48229727 4405
461a49ca 4406 case ARM_TYPE:
fe33d2fa
CL		 4407 bfd_put_32 (stub_bfd, template_sequence[i].data,
4408 loc + size);
461a49ca
DJ		 4409 /* Handle cases where the target is encoded within the
4410 instruction. */
d3ce72d0 4411 if (template_sequence[i].r_type == R_ARM_JUMP24)
461a49ca 4412 {
48229727
JB		 4413 stub_reloc_idx[nrelocs] = i;
4414 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4415 }
4416 size += 4;
4417 break;
4418
4419 case DATA_TYPE:
d3ce72d0 4420 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
48229727
JB		 4421 stub_reloc_idx[nrelocs] = i;
4422 stub_reloc_offset[nrelocs++] = size;
461a49ca
DJ		 4423 size += 4;
4424 break;
4425
4426 default:
4427 BFD_FAIL ();
4428 return FALSE;
4429 }
906e58ca 4430 }
461a49ca 4431
906e58ca
NC		 4432 stub_sec->size += size;
4433
461a49ca
DJ		 4434 /* Stub size has already been computed in arm_size_one_stub. Check
4435 consistency. */
4436 BFD_ASSERT (size == stub_entry->stub_size);
4437
906e58ca 4438 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
35fc36a8 4439 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
906e58ca
NC		 4440 sym_value |= 1;
4441
48229727
JB		 4442 /* Assume there is at least one and at most MAXRELOCS entries to relocate
4443 in each stub. */
4444 BFD_ASSERT (nrelocs != 0 && nrelocs <= MAXRELOCS);
c820be07 4445
48229727 4446 for (i = 0; i < nrelocs; i++)
d3ce72d0
NC		 4447 if (template_sequence[stub_reloc_idx[i]].r_type == R_ARM_THM_JUMP24
4448 || template_sequence[stub_reloc_idx[i]].r_type == R_ARM_THM_JUMP19
4449 || template_sequence[stub_reloc_idx[i]].r_type == R_ARM_THM_CALL
4450 || template_sequence[stub_reloc_idx[i]].r_type == R_ARM_THM_XPC22)
48229727
JB		 4451 {
4452 Elf_Internal_Rela rel;
4453 bfd_boolean unresolved_reloc;
4454 char *error_message;
35fc36a8
RS		 4455 enum arm_st_branch_type branch_type
4456 = (template_sequence[stub_reloc_idx[i]].r_type != R_ARM_THM_XPC22
4457 ? ST_BRANCH_TO_THUMB : ST_BRANCH_TO_ARM);
48229727
JB		 4458 bfd_vma points_to = sym_value + stub_entry->target_addend;
4459
4460 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
d3ce72d0 4461 rel.r_info = ELF32_R_INFO (0,
99059e56 4462 template_sequence[stub_reloc_idx[i]].r_type);
d3ce72d0 4463 rel.r_addend = template_sequence[stub_reloc_idx[i]].reloc_addend;
48229727
JB		 4464
4465 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
4466 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4467 template should refer back to the instruction after the original
4468 branch. */
4469 points_to = sym_value;
4470
33c6a8fc
JB		 4471 /* There may be unintended consequences if this is not true. */
4472 BFD_ASSERT (stub_entry->h == NULL);
4473
48229727
JB		 4474 /* Note: _bfd_final_link_relocate doesn't handle these relocations
4475 properly. We should probably use this function unconditionally,
4476 rather than only for certain relocations listed in the enclosing
4477 conditional, for the sake of consistency. */
4478 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
d3ce72d0 4479 (template_sequence[stub_reloc_idx[i]].r_type),
48229727 4480 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
34e77a92
RS		 4481 points_to, info, stub_entry->target_section, "", STT_FUNC,
4482 branch_type, (struct elf_link_hash_entry *) stub_entry->h,
4483 &unresolved_reloc, &error_message);
48229727
JB		 4484 }
4485 else
4486 {
fe33d2fa
CL		 4487 Elf_Internal_Rela rel;
4488 bfd_boolean unresolved_reloc;
4489 char *error_message;
4490 bfd_vma points_to = sym_value + stub_entry->target_addend
4491 + template_sequence[stub_reloc_idx[i]].reloc_addend;
4492
4493 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
4494 rel.r_info = ELF32_R_INFO (0,
99059e56 4495 template_sequence[stub_reloc_idx[i]].r_type);
fe33d2fa
CL		 4496 rel.r_addend = 0;
4497
4498 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
4499 (template_sequence[stub_reloc_idx[i]].r_type),
4500 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
34e77a92 4501 points_to, info, stub_entry->target_section, "", STT_FUNC,
35fc36a8 4502 stub_entry->branch_type,
fe33d2fa
CL		 4503 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
4504 &error_message);
48229727 4505 }
906e58ca
NC		 4506
4507 return TRUE;
48229727 4508#undef MAXRELOCS
906e58ca
NC		 4509}
4510
48229727
JB		 4511/* Calculate the template, template size and instruction size for a stub.
4512 Return value is the instruction size. */
906e58ca 4513
48229727
JB		 4514static unsigned int
4515find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
4516 const insn_sequence **stub_template,
4517 int *stub_template_size)
906e58ca 4518{
d3ce72d0 4519 const insn_sequence *template_sequence = NULL;
48229727
JB		 4520 int template_size = 0, i;
4521 unsigned int size;
906e58ca 4522
d3ce72d0 4523 template_sequence = stub_definitions[stub_type].template_sequence;
2a229407
AM		 4524 if (stub_template)
4525 *stub_template = template_sequence;
4526
48229727 4527 template_size = stub_definitions[stub_type].template_size;
2a229407
AM		 4528 if (stub_template_size)
4529 *stub_template_size = template_size;
906e58ca
NC		 4530
4531 size = 0;
461a49ca
DJ		 4532 for (i = 0; i < template_size; i++)
4533 {
d3ce72d0 4534 switch (template_sequence[i].type)
461a49ca
DJ		 4535 {
4536 case THUMB16_TYPE:
4537 size += 2;
4538 break;
4539
4540 case ARM_TYPE:
48229727 4541 case THUMB32_TYPE:
461a49ca
DJ		 4542 case DATA_TYPE:
4543 size += 4;
4544 break;
4545
4546 default:
4547 BFD_FAIL ();
2a229407 4548 return 0;
461a49ca
DJ		 4549 }
4550 }
4551
48229727
JB		 4552 return size;
4553}
4554
4555/* As above, but don't actually build the stub. Just bump offset so
4556 we know stub section sizes. */
4557
4558static bfd_boolean
4559arm_size_one_stub (struct bfd_hash_entry *gen_entry,
c7e2358a 4560 void *in_arg ATTRIBUTE_UNUSED)
48229727
JB		 4561{
4562 struct elf32_arm_stub_hash_entry *stub_entry;
d3ce72d0 4563 const insn_sequence *template_sequence;
48229727
JB		 4564 int template_size, size;
4565
4566 /* Massage our args to the form they really have. */
4567 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
48229727
JB		 4568
4569 BFD_ASSERT((stub_entry->stub_type > arm_stub_none)
4570 && stub_entry->stub_type < ARRAY_SIZE(stub_definitions));
4571
d3ce72d0 4572 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
48229727
JB		 4573 &template_size);
4574
461a49ca 4575 stub_entry->stub_size = size;
d3ce72d0 4576 stub_entry->stub_template = template_sequence;
461a49ca
DJ		 4577 stub_entry->stub_template_size = template_size;
4578
906e58ca
NC		 4579 size = (size + 7) & ~7;
4580 stub_entry->stub_sec->size += size;
461a49ca 4581
906e58ca
NC		 4582 return TRUE;
4583}
4584
4585/* External entry points for sizing and building linker stubs. */
4586
4587/* Set up various things so that we can make a list of input sections
4588 for each output section included in the link. Returns -1 on error,
4589 0 when no stubs will be needed, and 1 on success. */
4590
4591int
4592elf32_arm_setup_section_lists (bfd *output_bfd,
4593 struct bfd_link_info *info)
4594{
4595 bfd *input_bfd;
4596 unsigned int bfd_count;
7292b3ac 4597 unsigned int top_id, top_index;
906e58ca
NC		 4598 asection *section;
4599 asection **input_list, **list;
4600 bfd_size_type amt;
4601 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4602
4dfe6ac6
NC		 4603 if (htab == NULL)
4604 return 0;
906e58ca
NC		 4605 if (! is_elf_hash_table (htab))
4606 return 0;
4607
4608 /* Count the number of input BFDs and find the top input section id. */
4609 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
4610 input_bfd != NULL;
c72f2fb2 4611 input_bfd = input_bfd->link.next)
906e58ca
NC		 4612 {
4613 bfd_count += 1;
4614 for (section = input_bfd->sections;
4615 section != NULL;
4616 section = section->next)
4617 {
4618 if (top_id < section->id)
4619 top_id = section->id;
4620 }
4621 }
4622 htab->bfd_count = bfd_count;
4623
4624 amt = sizeof (struct map_stub) * (top_id + 1);
21d799b5 4625 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
906e58ca
NC		 4626 if (htab->stub_group == NULL)
4627 return -1;
fe33d2fa 4628 htab->top_id = top_id;
906e58ca
NC		 4629
4630 /* We can't use output_bfd->section_count here to find the top output
4631 section index as some sections may have been removed, and
4632 _bfd_strip_section_from_output doesn't renumber the indices. */
4633 for (section = output_bfd->sections, top_index = 0;
4634 section != NULL;
4635 section = section->next)
4636 {
4637 if (top_index < section->index)
4638 top_index = section->index;
4639 }
4640
4641 htab->top_index = top_index;
4642 amt = sizeof (asection *) * (top_index + 1);
21d799b5 4643 input_list = (asection **) bfd_malloc (amt);
906e58ca
NC		 4644 htab->input_list = input_list;
4645 if (input_list == NULL)
4646 return -1;
4647
4648 /* For sections we aren't interested in, mark their entries with a
4649 value we can check later. */
4650 list = input_list + top_index;
4651 do
4652 *list = bfd_abs_section_ptr;
4653 while (list-- != input_list);
4654
4655 for (section = output_bfd->sections;
4656 section != NULL;
4657 section = section->next)
4658 {
4659 if ((section->flags & SEC_CODE) != 0)
4660 input_list[section->index] = NULL;
4661 }
4662
4663 return 1;
4664}
4665
4666/* The linker repeatedly calls this function for each input section,
4667 in the order that input sections are linked into output sections.
4668 Build lists of input sections to determine groupings between which
4669 we may insert linker stubs. */
4670
4671void
4672elf32_arm_next_input_section (struct bfd_link_info *info,
4673 asection *isec)
4674{
4675 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4676
4dfe6ac6
NC		 4677 if (htab == NULL)
4678 return;
4679
906e58ca
NC		 4680 if (isec->output_section->index <= htab->top_index)
4681 {
4682 asection **list = htab->input_list + isec->output_section->index;
4683
a7470592 4684 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
906e58ca
NC		 4685 {
4686 /* Steal the link_sec pointer for our list. */
4687#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
4688 /* This happens to make the list in reverse order,
07d72278 4689 which we reverse later. */
906e58ca
NC		 4690 PREV_SEC (isec) = *list;
4691 *list = isec;
4692 }
4693 }
4694}
4695
4696/* See whether we can group stub sections together. Grouping stub
4697 sections may result in fewer stubs. More importantly, we need to
07d72278 4698 put all .init* and .fini* stubs at the end of the .init or
906e58ca
NC		 4699 .fini output sections respectively, because glibc splits the
4700 _init and _fini functions into multiple parts. Putting a stub in
4701 the middle of a function is not a good idea. */
4702
4703static void
4704group_sections (struct elf32_arm_link_hash_table *htab,
4705 bfd_size_type stub_group_size,
07d72278 4706 bfd_boolean stubs_always_after_branch)
906e58ca 4707{
07d72278 4708 asection **list = htab->input_list;
906e58ca
NC		 4709
4710 do
4711 {
4712 asection *tail = *list;
07d72278 4713 asection *head;
906e58ca
NC		 4714
4715 if (tail == bfd_abs_section_ptr)
4716 continue;
4717
07d72278
DJ		 4718 /* Reverse the list: we must avoid placing stubs at the
4719 beginning of the section because the beginning of the text
4720 section may be required for an interrupt vector in bare metal
4721 code. */
4722#define NEXT_SEC PREV_SEC
e780aef2
CL		 4723 head = NULL;
4724 while (tail != NULL)
99059e56
RM		 4725 {
4726 /* Pop from tail. */
4727 asection *item = tail;
4728 tail = PREV_SEC (item);
e780aef2 4729
99059e56
RM		 4730 /* Push on head. */
4731 NEXT_SEC (item) = head;
4732 head = item;
4733 }
07d72278
DJ		 4734
4735 while (head != NULL)
906e58ca
NC		 4736 {
4737 asection *curr;
07d72278 4738 asection *next;
e780aef2
CL		 4739 bfd_vma stub_group_start = head->output_offset;
4740 bfd_vma end_of_next;
906e58ca 4741
07d72278 4742 curr = head;
e780aef2 4743 while (NEXT_SEC (curr) != NULL)
8cd931b7 4744 {
e780aef2
CL		 4745 next = NEXT_SEC (curr);
4746 end_of_next = next->output_offset + next->size;
4747 if (end_of_next - stub_group_start >= stub_group_size)
4748 /* End of NEXT is too far from start, so stop. */
8cd931b7 4749 break;
e780aef2
CL		 4750 /* Add NEXT to the group. */
4751 curr = next;
8cd931b7 4752 }
906e58ca 4753
07d72278 4754 /* OK, the size from the start to the start of CURR is less
906e58ca 4755 than stub_group_size and thus can be handled by one stub
07d72278 4756 section. (Or the head section is itself larger than
906e58ca
NC		 4757 stub_group_size, in which case we may be toast.)
4758 We should really be keeping track of the total size of
4759 stubs added here, as stubs contribute to the final output
7fb9f789 4760 section size. */
906e58ca
NC		 4761 do
4762 {
07d72278 4763 next = NEXT_SEC (head);
906e58ca 4764 /* Set up this stub group. */
07d72278 4765 htab->stub_group[head->id].link_sec = curr;
906e58ca 4766 }
07d72278 4767 while (head != curr && (head = next) != NULL);
906e58ca
NC		 4768
4769 /* But wait, there's more! Input sections up to stub_group_size
07d72278
DJ		 4770 bytes after the stub section can be handled by it too. */
4771 if (!stubs_always_after_branch)
906e58ca 4772 {
e780aef2
CL		 4773 stub_group_start = curr->output_offset + curr->size;
4774
8cd931b7 4775 while (next != NULL)
906e58ca 4776 {
e780aef2
CL		 4777 end_of_next = next->output_offset + next->size;
4778 if (end_of_next - stub_group_start >= stub_group_size)
4779 /* End of NEXT is too far from stubs, so stop. */
8cd931b7 4780 break;
e780aef2 4781 /* Add NEXT to the stub group. */
07d72278
DJ		 4782 head = next;
4783 next = NEXT_SEC (head);
4784 htab->stub_group[head->id].link_sec = curr;
906e58ca
NC		 4785 }
4786 }
07d72278 4787 head = next;
906e58ca
NC		 4788 }
4789 }
07d72278 4790 while (list++ != htab->input_list + htab->top_index);
906e58ca
NC		 4791
4792 free (htab->input_list);
4793#undef PREV_SEC
07d72278 4794#undef NEXT_SEC
906e58ca
NC		 4795}
4796
48229727
JB		 4797/* Comparison function for sorting/searching relocations relating to Cortex-A8
4798 erratum fix. */
4799
4800static int
4801a8_reloc_compare (const void *a, const void *b)
4802{
21d799b5
NC		 4803 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
4804 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
48229727
JB		 4805
4806 if (ra->from < rb->from)
4807 return -1;
4808 else if (ra->from > rb->from)
4809 return 1;
4810 else
4811 return 0;
4812}
4813
4814static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
4815 const char *, char **);
4816
4817/* Helper function to scan code for sequences which might trigger the Cortex-A8
4818 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
81694485 4819 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
48229727
JB		 4820 otherwise. */
4821
81694485
NC		 4822static bfd_boolean
4823cortex_a8_erratum_scan (bfd *input_bfd,
4824 struct bfd_link_info *info,
48229727
JB		 4825 struct a8_erratum_fix **a8_fixes_p,
4826 unsigned int *num_a8_fixes_p,
4827 unsigned int *a8_fix_table_size_p,
4828 struct a8_erratum_reloc *a8_relocs,
eb7c4339
NS		 4829 unsigned int num_a8_relocs,
4830 unsigned prev_num_a8_fixes,
4831 bfd_boolean *stub_changed_p)
48229727
JB		 4832{
4833 asection *section;
4834 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
4835 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
4836 unsigned int num_a8_fixes = *num_a8_fixes_p;
4837 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
4838
4dfe6ac6
NC		 4839 if (htab == NULL)
4840 return FALSE;
4841
48229727
JB		 4842 for (section = input_bfd->sections;
4843 section != NULL;
4844 section = section->next)
4845 {
4846 bfd_byte *contents = NULL;
4847 struct _arm_elf_section_data *sec_data;
4848 unsigned int span;
4849 bfd_vma base_vma;
4850
4851 if (elf_section_type (section) != SHT_PROGBITS
99059e56
RM		 4852 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
4853 || (section->flags & SEC_EXCLUDE) != 0
4854 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
4855 || (section->output_section == bfd_abs_section_ptr))
4856 continue;
48229727
JB		 4857
4858 base_vma = section->output_section->vma + section->output_offset;
4859
4860 if (elf_section_data (section)->this_hdr.contents != NULL)
99059e56 4861 contents = elf_section_data (section)->this_hdr.contents;
48229727 4862 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
99059e56 4863 return TRUE;
48229727
JB		 4864
4865 sec_data = elf32_arm_section_data (section);
4866
4867 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 4868 {
4869 unsigned int span_start = sec_data->map[span].vma;
4870 unsigned int span_end = (span == sec_data->mapcount - 1)
4871 ? section->size : sec_data->map[span + 1].vma;
4872 unsigned int i;
4873 char span_type = sec_data->map[span].type;
4874 bfd_boolean last_was_32bit = FALSE, last_was_branch = FALSE;
4875
4876 if (span_type != 't')
4877 continue;
4878
4879 /* Span is entirely within a single 4KB region: skip scanning. */
4880 if (((base_vma + span_start) & ~0xfff)
48229727 4881 == ((base_vma + span_end) & ~0xfff))
99059e56
RM		 4882 continue;
4883
4884 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
4885
4886 * The opcode is BLX.W, BL.W, B.W, Bcc.W
4887 * The branch target is in the same 4KB region as the
4888 first half of the branch.
4889 * The instruction before the branch is a 32-bit
4890 length non-branch instruction. */
4891 for (i = span_start; i < span_end;)
4892 {
4893 unsigned int insn = bfd_getl16 (&contents[i]);
4894 bfd_boolean insn_32bit = FALSE, is_blx = FALSE, is_b = FALSE;
48229727
JB		 4895 bfd_boolean is_bl = FALSE, is_bcc = FALSE, is_32bit_branch;
4896
99059e56
RM		 4897 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
4898 insn_32bit = TRUE;
48229727
JB		 4899
4900 if (insn_32bit)
99059e56
RM		 4901 {
4902 /* Load the rest of the insn (in manual-friendly order). */
4903 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
4904
4905 /* Encoding T4: B<c>.W. */
4906 is_b = (insn & 0xf800d000) == 0xf0009000;
4907 /* Encoding T1: BL<c>.W. */
4908 is_bl = (insn & 0xf800d000) == 0xf000d000;
4909 /* Encoding T2: BLX<c>.W. */
4910 is_blx = (insn & 0xf800d000) == 0xf000c000;
48229727
JB		 4911 /* Encoding T3: B<c>.W (not permitted in IT block). */
4912 is_bcc = (insn & 0xf800d000) == 0xf0008000
4913 && (insn & 0x07f00000) != 0x03800000;
4914 }
4915
4916 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
fe33d2fa 4917
99059e56 4918 if (((base_vma + i) & 0xfff) == 0xffe
81694485
NC		 4919 && insn_32bit
4920 && is_32bit_branch
4921 && last_was_32bit
4922 && ! last_was_branch)
99059e56
RM		 4923 {
4924 bfd_signed_vma offset = 0;
4925 bfd_boolean force_target_arm = FALSE;
48229727 4926 bfd_boolean force_target_thumb = FALSE;
99059e56
RM		 4927 bfd_vma target;
4928 enum elf32_arm_stub_type stub_type = arm_stub_none;
4929 struct a8_erratum_reloc key, *found;
4930 bfd_boolean use_plt = FALSE;
48229727 4931
99059e56
RM		 4932 key.from = base_vma + i;
4933 found = (struct a8_erratum_reloc *)
4934 bsearch (&key, a8_relocs, num_a8_relocs,
4935 sizeof (struct a8_erratum_reloc),
4936 &a8_reloc_compare);
48229727
JB		 4937
4938 if (found)
4939 {
4940 char *error_message = NULL;
4941 struct elf_link_hash_entry *entry;
4942
4943 /* We don't care about the error returned from this
99059e56 4944 function, only if there is glue or not. */
48229727
JB		 4945 entry = find_thumb_glue (info, found->sym_name,
4946 &error_message);
4947
4948 if (entry)
4949 found->non_a8_stub = TRUE;
4950
92750f34 4951 /* Keep a simpler condition, for the sake of clarity. */
362d30a1 4952 if (htab->root.splt != NULL && found->hash != NULL
92750f34
DJ		 4953 && found->hash->root.plt.offset != (bfd_vma) -1)
4954 use_plt = TRUE;
4955
4956 if (found->r_type == R_ARM_THM_CALL)
4957 {
35fc36a8
RS		 4958 if (found->branch_type == ST_BRANCH_TO_ARM
4959 || use_plt)
92750f34
DJ		 4960 force_target_arm = TRUE;
4961 else
4962 force_target_thumb = TRUE;
4963 }
48229727
JB		 4964 }
4965
99059e56 4966 /* Check if we have an offending branch instruction. */
48229727
JB		 4967
4968 if (found && found->non_a8_stub)
4969 /* We've already made a stub for this instruction, e.g.
4970 it's a long branch or a Thumb->ARM stub. Assume that
4971 stub will suffice to work around the A8 erratum (see
4972 setting of always_after_branch above). */
4973 ;
99059e56
RM		 4974 else if (is_bcc)
4975 {
4976 offset = (insn & 0x7ff) << 1;
4977 offset |= (insn & 0x3f0000) >> 4;
4978 offset |= (insn & 0x2000) ? 0x40000 : 0;
4979 offset |= (insn & 0x800) ? 0x80000 : 0;
4980 offset |= (insn & 0x4000000) ? 0x100000 : 0;
4981 if (offset & 0x100000)
4982 offset |= ~ ((bfd_signed_vma) 0xfffff);
4983 stub_type = arm_stub_a8_veneer_b_cond;
4984 }
4985 else if (is_b || is_bl || is_blx)
4986 {
4987 int s = (insn & 0x4000000) != 0;
4988 int j1 = (insn & 0x2000) != 0;
4989 int j2 = (insn & 0x800) != 0;
4990 int i1 = !(j1 ^ s);
4991 int i2 = !(j2 ^ s);
4992
4993 offset = (insn & 0x7ff) << 1;
4994 offset |= (insn & 0x3ff0000) >> 4;
4995 offset |= i2 << 22;
4996 offset |= i1 << 23;
4997 offset |= s << 24;
4998 if (offset & 0x1000000)
4999 offset |= ~ ((bfd_signed_vma) 0xffffff);
5000
5001 if (is_blx)
5002 offset &= ~ ((bfd_signed_vma) 3);
5003
5004 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5005 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5006 }
5007
5008 if (stub_type != arm_stub_none)
5009 {
5010 bfd_vma pc_for_insn = base_vma + i + 4;
48229727
JB		 5011
5012 /* The original instruction is a BL, but the target is
99059e56 5013 an ARM instruction. If we were not making a stub,
48229727
JB		 5014 the BL would have been converted to a BLX. Use the
5015 BLX stub instead in that case. */
5016 if (htab->use_blx && force_target_arm
5017 && stub_type == arm_stub_a8_veneer_bl)
5018 {
5019 stub_type = arm_stub_a8_veneer_blx;
5020 is_blx = TRUE;
5021 is_bl = FALSE;
5022 }
5023 /* Conversely, if the original instruction was
5024 BLX but the target is Thumb mode, use the BL
5025 stub. */
5026 else if (force_target_thumb
5027 && stub_type == arm_stub_a8_veneer_blx)
5028 {
5029 stub_type = arm_stub_a8_veneer_bl;
5030 is_blx = FALSE;
5031 is_bl = TRUE;
5032 }
5033
99059e56
RM		 5034 if (is_blx)
5035 pc_for_insn &= ~ ((bfd_vma) 3);
48229727 5036
99059e56
RM		 5037 /* If we found a relocation, use the proper destination,
5038 not the offset in the (unrelocated) instruction.
48229727
JB		 5039 Note this is always done if we switched the stub type
5040 above. */
99059e56
RM		 5041 if (found)
5042 offset =
81694485 5043 (bfd_signed_vma) (found->destination - pc_for_insn);
48229727 5044
99059e56
RM		 5045 /* If the stub will use a Thumb-mode branch to a
5046 PLT target, redirect it to the preceding Thumb
5047 entry point. */
5048 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5049 offset -= PLT_THUMB_STUB_SIZE;
7d24e6a6 5050
99059e56 5051 target = pc_for_insn + offset;
48229727 5052
99059e56
RM		 5053 /* The BLX stub is ARM-mode code. Adjust the offset to
5054 take the different PC value (+8 instead of +4) into
48229727 5055 account. */
99059e56
RM		 5056 if (stub_type == arm_stub_a8_veneer_blx)
5057 offset += 4;
5058
5059 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5060 {
5061 char *stub_name = NULL;
5062
5063 if (num_a8_fixes == a8_fix_table_size)
5064 {
5065 a8_fix_table_size *= 2;
5066 a8_fixes = (struct a8_erratum_fix *)
5067 bfd_realloc (a8_fixes,
5068 sizeof (struct a8_erratum_fix)
5069 * a8_fix_table_size);
5070 }
48229727 5071
eb7c4339
NS		 5072 if (num_a8_fixes < prev_num_a8_fixes)
5073 {
5074 /* If we're doing a subsequent scan,
5075 check if we've found the same fix as
5076 before, and try and reuse the stub
5077 name. */
5078 stub_name = a8_fixes[num_a8_fixes].stub_name;
5079 if ((a8_fixes[num_a8_fixes].section != section)
5080 || (a8_fixes[num_a8_fixes].offset != i))
5081 {
5082 free (stub_name);
5083 stub_name = NULL;
5084 *stub_changed_p = TRUE;
5085 }
5086 }
5087
5088 if (!stub_name)
5089 {
21d799b5 5090 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
eb7c4339
NS		 5091 if (stub_name != NULL)
5092 sprintf (stub_name, "%x:%x", section->id, i);
5093 }
48229727 5094
99059e56
RM		 5095 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5096 a8_fixes[num_a8_fixes].section = section;
5097 a8_fixes[num_a8_fixes].offset = i;
5098 a8_fixes[num_a8_fixes].addend = offset;
5099 a8_fixes[num_a8_fixes].orig_insn = insn;
5100 a8_fixes[num_a8_fixes].stub_name = stub_name;
5101 a8_fixes[num_a8_fixes].stub_type = stub_type;
5102 a8_fixes[num_a8_fixes].branch_type =
35fc36a8 5103 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
48229727 5104
99059e56
RM		 5105 num_a8_fixes++;
5106 }
5107 }
5108 }
48229727 5109
99059e56
RM		 5110 i += insn_32bit ? 4 : 2;
5111 last_was_32bit = insn_32bit;
48229727 5112 last_was_branch = is_32bit_branch;
99059e56
RM		 5113 }
5114 }
48229727
JB		 5115
5116 if (elf_section_data (section)->this_hdr.contents == NULL)
99059e56 5117 free (contents);
48229727 5118 }
fe33d2fa 5119
48229727
JB		 5120 *a8_fixes_p = a8_fixes;
5121 *num_a8_fixes_p = num_a8_fixes;
5122 *a8_fix_table_size_p = a8_fix_table_size;
fe33d2fa 5123
81694485 5124 return FALSE;
48229727
JB		 5125}
5126
906e58ca
NC		 5127/* Determine and set the size of the stub section for a final link.
5128
5129 The basic idea here is to examine all the relocations looking for
5130 PC-relative calls to a target that is unreachable with a "bl"
5131 instruction. */
5132
5133bfd_boolean
5134elf32_arm_size_stubs (bfd *output_bfd,
5135 bfd *stub_bfd,
5136 struct bfd_link_info *info,
5137 bfd_signed_vma group_size,
7a89b94e
NC		 5138 asection * (*add_stub_section) (const char *, asection *,
5139 unsigned int),
906e58ca
NC		 5140 void (*layout_sections_again) (void))
5141{
5142 bfd_size_type stub_group_size;
07d72278 5143 bfd_boolean stubs_always_after_branch;
906e58ca 5144 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
48229727 5145 struct a8_erratum_fix *a8_fixes = NULL;
eb7c4339 5146 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
48229727
JB		 5147 struct a8_erratum_reloc *a8_relocs = NULL;
5148 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
5149
4dfe6ac6
NC		 5150 if (htab == NULL)
5151 return FALSE;
5152
48229727
JB		 5153 if (htab->fix_cortex_a8)
5154 {
21d799b5 5155 a8_fixes = (struct a8_erratum_fix *)
99059e56 5156 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
21d799b5 5157 a8_relocs = (struct a8_erratum_reloc *)
99059e56 5158 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
48229727 5159 }
906e58ca
NC		 5160
5161 /* Propagate mach to stub bfd, because it may not have been
5162 finalized when we created stub_bfd. */
5163 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
5164 bfd_get_mach (output_bfd));
5165
5166 /* Stash our params away. */
5167 htab->stub_bfd = stub_bfd;
5168 htab->add_stub_section = add_stub_section;
5169 htab->layout_sections_again = layout_sections_again;
07d72278 5170 stubs_always_after_branch = group_size < 0;
48229727
JB		 5171
5172 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
5173 as the first half of a 32-bit branch straddling two 4K pages. This is a
5174 crude way of enforcing that. */
5175 if (htab->fix_cortex_a8)
5176 stubs_always_after_branch = 1;
5177
906e58ca
NC		 5178 if (group_size < 0)
5179 stub_group_size = -group_size;
5180 else
5181 stub_group_size = group_size;
5182
5183 if (stub_group_size == 1)
5184 {
5185 /* Default values. */
5186 /* Thumb branch range is +-4MB has to be used as the default
5187 maximum size (a given section can contain both ARM and Thumb
5188 code, so the worst case has to be taken into account).
5189
5190 This value is 24K less than that, which allows for 2025
5191 12-byte stubs. If we exceed that, then we will fail to link.
5192 The user will have to relink with an explicit group size
5193 option. */
5194 stub_group_size = 4170000;
5195 }
5196
07d72278 5197 group_sections (htab, stub_group_size, stubs_always_after_branch);
906e58ca 5198
3ae046cc
NS		 5199 /* If we're applying the cortex A8 fix, we need to determine the
5200 program header size now, because we cannot change it later --
5201 that could alter section placements. Notice the A8 erratum fix
5202 ends up requiring the section addresses to remain unchanged
5203 modulo the page size. That's something we cannot represent
5204 inside BFD, and we don't want to force the section alignment to
5205 be the page size. */
5206 if (htab->fix_cortex_a8)
5207 (*htab->layout_sections_again) ();
5208
906e58ca
NC		 5209 while (1)
5210 {
5211 bfd *input_bfd;
5212 unsigned int bfd_indx;
5213 asection *stub_sec;
eb7c4339
NS		 5214 bfd_boolean stub_changed = FALSE;
5215 unsigned prev_num_a8_fixes = num_a8_fixes;
906e58ca 5216
48229727 5217 num_a8_fixes = 0;
906e58ca
NC		 5218 for (input_bfd = info->input_bfds, bfd_indx = 0;
5219 input_bfd != NULL;
c72f2fb2 5220 input_bfd = input_bfd->link.next, bfd_indx++)
906e58ca
NC		 5221 {
5222 Elf_Internal_Shdr *symtab_hdr;
5223 asection *section;
5224 Elf_Internal_Sym *local_syms = NULL;
5225
99059e56
RM		 5226 if (!is_arm_elf (input_bfd))
5227 continue;
adbcc655 5228
48229727
JB		 5229 num_a8_relocs = 0;
5230
906e58ca
NC		 5231 /* We'll need the symbol table in a second. */
5232 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5233 if (symtab_hdr->sh_info == 0)
5234 continue;
5235
5236 /* Walk over each section attached to the input bfd. */
5237 for (section = input_bfd->sections;
5238 section != NULL;
5239 section = section->next)
5240 {
5241 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
5242
5243 /* If there aren't any relocs, then there's nothing more
5244 to do. */
5245 if ((section->flags & SEC_RELOC) == 0
5246 || section->reloc_count == 0
5247 || (section->flags & SEC_CODE) == 0)
5248 continue;
5249
5250 /* If this section is a link-once section that will be
5251 discarded, then don't create any stubs. */
5252 if (section->output_section == NULL
5253 || section->output_section->owner != output_bfd)
5254 continue;
5255
5256 /* Get the relocs. */
5257 internal_relocs
5258 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
5259 NULL, info->keep_memory);
5260 if (internal_relocs == NULL)
5261 goto error_ret_free_local;
5262
5263 /* Now examine each relocation. */
5264 irela = internal_relocs;
5265 irelaend = irela + section->reloc_count;
5266 for (; irela < irelaend; irela++)
5267 {
5268 unsigned int r_type, r_indx;
5269 enum elf32_arm_stub_type stub_type;
5270 struct elf32_arm_stub_hash_entry *stub_entry;
5271 asection *sym_sec;
5272 bfd_vma sym_value;
5273 bfd_vma destination;
5274 struct elf32_arm_link_hash_entry *hash;
7413f23f 5275 const char *sym_name;
906e58ca
NC		 5276 char *stub_name;
5277 const asection *id_sec;
34e77a92 5278 unsigned char st_type;
35fc36a8 5279 enum arm_st_branch_type branch_type;
48229727 5280 bfd_boolean created_stub = FALSE;
906e58ca
NC		 5281
5282 r_type = ELF32_R_TYPE (irela->r_info);
5283 r_indx = ELF32_R_SYM (irela->r_info);
5284
5285 if (r_type >= (unsigned int) R_ARM_max)
5286 {
5287 bfd_set_error (bfd_error_bad_value);
5288 error_ret_free_internal:
5289 if (elf_section_data (section)->relocs == NULL)
5290 free (internal_relocs);
5291 goto error_ret_free_local;
5292 }
b38cadfb 5293
0855e32b
NS		 5294 hash = NULL;
5295 if (r_indx >= symtab_hdr->sh_info)
5296 hash = elf32_arm_hash_entry
5297 (elf_sym_hashes (input_bfd)
5298 [r_indx - symtab_hdr->sh_info]);
b38cadfb 5299
0855e32b
NS		 5300 /* Only look for stubs on branch instructions, or
5301 non-relaxed TLSCALL */
906e58ca 5302 if ((r_type != (unsigned int) R_ARM_CALL)
155d87d7
CL		 5303 && (r_type != (unsigned int) R_ARM_THM_CALL)
5304 && (r_type != (unsigned int) R_ARM_JUMP24)
48229727
JB		 5305 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
5306 && (r_type != (unsigned int) R_ARM_THM_XPC22)
155d87d7 5307 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
0855e32b
NS		 5308 && (r_type != (unsigned int) R_ARM_PLT32)
5309 && !((r_type == (unsigned int) R_ARM_TLS_CALL
5310 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
5311 && r_type == elf32_arm_tls_transition
5312 (info, r_type, &hash->root)
5313 && ((hash ? hash->tls_type
5314 : (elf32_arm_local_got_tls_type
5315 (input_bfd)[r_indx]))
5316 & GOT_TLS_GDESC) != 0))
906e58ca
NC		 5317 continue;
5318
5319 /* Now determine the call target, its name, value,
5320 section. */
5321 sym_sec = NULL;
5322 sym_value = 0;
5323 destination = 0;
7413f23f 5324 sym_name = NULL;
b38cadfb 5325
0855e32b
NS		 5326 if (r_type == (unsigned int) R_ARM_TLS_CALL
5327 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
5328 {
5329 /* A non-relaxed TLS call. The target is the
5330 plt-resident trampoline and nothing to do
5331 with the symbol. */
5332 BFD_ASSERT (htab->tls_trampoline > 0);
5333 sym_sec = htab->root.splt;
5334 sym_value = htab->tls_trampoline;
5335 hash = 0;
34e77a92 5336 st_type = STT_FUNC;
35fc36a8 5337 branch_type = ST_BRANCH_TO_ARM;
0855e32b
NS		 5338 }
5339 else if (!hash)
906e58ca
NC		 5340 {
5341 /* It's a local symbol. */
5342 Elf_Internal_Sym *sym;
906e58ca
NC		 5343
5344 if (local_syms == NULL)
5345 {
5346 local_syms
5347 = (Elf_Internal_Sym *) symtab_hdr->contents;
5348 if (local_syms == NULL)
5349 local_syms
5350 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5351 symtab_hdr->sh_info, 0,
5352 NULL, NULL, NULL);
5353 if (local_syms == NULL)
5354 goto error_ret_free_internal;
5355 }
5356
5357 sym = local_syms + r_indx;
f6d250ce
TS		 5358 if (sym->st_shndx == SHN_UNDEF)
5359 sym_sec = bfd_und_section_ptr;
5360 else if (sym->st_shndx == SHN_ABS)
5361 sym_sec = bfd_abs_section_ptr;
5362 else if (sym->st_shndx == SHN_COMMON)
5363 sym_sec = bfd_com_section_ptr;
5364 else
5365 sym_sec =
5366 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
5367
ffcb4889
NS		 5368 if (!sym_sec)
5369 /* This is an undefined symbol. It can never
6a631e86 5370 be resolved. */
ffcb4889 5371 continue;
fe33d2fa 5372
906e58ca
NC		 5373 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
5374 sym_value = sym->st_value;
5375 destination = (sym_value + irela->r_addend
5376 + sym_sec->output_offset
5377 + sym_sec->output_section->vma);
34e77a92 5378 st_type = ELF_ST_TYPE (sym->st_info);
35fc36a8 5379 branch_type = ARM_SYM_BRANCH_TYPE (sym);
7413f23f
DJ		 5380 sym_name
5381 = bfd_elf_string_from_elf_section (input_bfd,
5382 symtab_hdr->sh_link,
5383 sym->st_name);
906e58ca
NC		 5384 }
5385 else
5386 {
5387 /* It's an external symbol. */
906e58ca
NC		 5388 while (hash->root.root.type == bfd_link_hash_indirect
5389 || hash->root.root.type == bfd_link_hash_warning)
5390 hash = ((struct elf32_arm_link_hash_entry *)
5391 hash->root.root.u.i.link);
5392
5393 if (hash->root.root.type == bfd_link_hash_defined
5394 || hash->root.root.type == bfd_link_hash_defweak)
5395 {
5396 sym_sec = hash->root.root.u.def.section;
5397 sym_value = hash->root.root.u.def.value;
022f8312
CL		 5398
5399 struct elf32_arm_link_hash_table *globals =
5400 elf32_arm_hash_table (info);
5401
5402 /* For a destination in a shared library,
5403 use the PLT stub as target address to
5404 decide whether a branch stub is
5405 needed. */
4dfe6ac6 5406 if (globals != NULL
362d30a1 5407 && globals->root.splt != NULL
4dfe6ac6 5408 && hash != NULL
022f8312
CL		 5409 && hash->root.plt.offset != (bfd_vma) -1)
5410 {
362d30a1 5411 sym_sec = globals->root.splt;
022f8312
CL		 5412 sym_value = hash->root.plt.offset;
5413 if (sym_sec->output_section != NULL)
5414 destination = (sym_value
5415 + sym_sec->output_offset
5416 + sym_sec->output_section->vma);
5417 }
5418 else if (sym_sec->output_section != NULL)
906e58ca
NC		 5419 destination = (sym_value + irela->r_addend
5420 + sym_sec->output_offset
5421 + sym_sec->output_section->vma);
5422 }
69c5861e
CL		 5423 else if ((hash->root.root.type == bfd_link_hash_undefined)
5424 || (hash->root.root.type == bfd_link_hash_undefweak))
5425 {
5426 /* For a shared library, use the PLT stub as
5427 target address to decide whether a long
5428 branch stub is needed.
5429 For absolute code, they cannot be handled. */
5430 struct elf32_arm_link_hash_table *globals =
5431 elf32_arm_hash_table (info);
5432
4dfe6ac6 5433 if (globals != NULL
362d30a1 5434 && globals->root.splt != NULL
4dfe6ac6 5435 && hash != NULL
69c5861e
CL		 5436 && hash->root.plt.offset != (bfd_vma) -1)
5437 {
362d30a1 5438 sym_sec = globals->root.splt;
69c5861e
CL		 5439 sym_value = hash->root.plt.offset;
5440 if (sym_sec->output_section != NULL)
5441 destination = (sym_value
5442 + sym_sec->output_offset
5443 + sym_sec->output_section->vma);
5444 }
5445 else
5446 continue;
5447 }
906e58ca
NC		 5448 else
5449 {
5450 bfd_set_error (bfd_error_bad_value);
5451 goto error_ret_free_internal;
5452 }
34e77a92 5453 st_type = hash->root.type;
35fc36a8 5454 branch_type = hash->root.target_internal;
7413f23f 5455 sym_name = hash->root.root.root.string;
906e58ca
NC		 5456 }
5457
48229727 5458 do
7413f23f 5459 {
48229727
JB		 5460 /* Determine what (if any) linker stub is needed. */
5461 stub_type = arm_type_of_stub (info, section, irela,
34e77a92
RS		 5462 st_type, &branch_type,
5463 hash, destination, sym_sec,
48229727
JB		 5464 input_bfd, sym_name);
5465 if (stub_type == arm_stub_none)
5466 break;
5467
5468 /* Support for grouping stub sections. */
5469 id_sec = htab->stub_group[section->id].link_sec;
5470
5471 /* Get the name of this stub. */
5472 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash,
fe33d2fa 5473 irela, stub_type);
48229727
JB		 5474 if (!stub_name)
5475 goto error_ret_free_internal;
5476
5477 /* We've either created a stub for this reloc already,
5478 or we are about to. */
5479 created_stub = TRUE;
5480
5481 stub_entry = arm_stub_hash_lookup
5482 (&htab->stub_hash_table, stub_name,
5483 FALSE, FALSE);
5484 if (stub_entry != NULL)
5485 {
5486 /* The proper stub has already been created. */
5487 free (stub_name);
eb7c4339 5488 stub_entry->target_value = sym_value;
48229727
JB		 5489 break;
5490 }
7413f23f 5491
48229727
JB		 5492 stub_entry = elf32_arm_add_stub (stub_name, section,
5493 htab);
5494 if (stub_entry == NULL)
5495 {
5496 free (stub_name);
5497 goto error_ret_free_internal;
5498 }
7413f23f 5499
99059e56
RM		 5500 stub_entry->target_value = sym_value;
5501 stub_entry->target_section = sym_sec;
5502 stub_entry->stub_type = stub_type;
5503 stub_entry->h = hash;
5504 stub_entry->branch_type = branch_type;
5505
5506 if (sym_name == NULL)
5507 sym_name = "unnamed";
5508 stub_entry->output_name = (char *)
5509 bfd_alloc (htab->stub_bfd,
5510 sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5511 + strlen (sym_name));
5512 if (stub_entry->output_name == NULL)
5513 {
5514 free (stub_name);
5515 goto error_ret_free_internal;
5516 }
5517
5518 /* For historical reasons, use the existing names for
5519 ARM-to-Thumb and Thumb-to-ARM stubs. */
5520 if ((r_type == (unsigned int) R_ARM_THM_CALL
c5423981
TG		 5521 || r_type == (unsigned int) R_ARM_THM_JUMP24
5522 || r_type == (unsigned int) R_ARM_THM_JUMP19)
35fc36a8 5523 && branch_type == ST_BRANCH_TO_ARM)
99059e56
RM		 5524 sprintf (stub_entry->output_name,
5525 THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5526 else if ((r_type == (unsigned int) R_ARM_CALL
35fc36a8
RS		 5527 || r_type == (unsigned int) R_ARM_JUMP24)
5528 && branch_type == ST_BRANCH_TO_THUMB)
99059e56
RM		 5529 sprintf (stub_entry->output_name,
5530 ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5531 else
5532 sprintf (stub_entry->output_name, STUB_ENTRY_NAME,
5533 sym_name);
5534
5535 stub_changed = TRUE;
5536 }
5537 while (0);
5538
5539 /* Look for relocations which might trigger Cortex-A8
5540 erratum. */
5541 if (htab->fix_cortex_a8
5542 && (r_type == (unsigned int) R_ARM_THM_JUMP24
5543 || r_type == (unsigned int) R_ARM_THM_JUMP19
5544 || r_type == (unsigned int) R_ARM_THM_CALL
5545 || r_type == (unsigned int) R_ARM_THM_XPC22))
5546 {
5547 bfd_vma from = section->output_section->vma
5548 + section->output_offset
5549 + irela->r_offset;
5550
5551 if ((from & 0xfff) == 0xffe)
5552 {
5553 /* Found a candidate. Note we haven't checked the
5554 destination is within 4K here: if we do so (and
5555 don't create an entry in a8_relocs) we can't tell
5556 that a branch should have been relocated when
5557 scanning later. */
5558 if (num_a8_relocs == a8_reloc_table_size)
5559 {
5560 a8_reloc_table_size *= 2;
5561 a8_relocs = (struct a8_erratum_reloc *)
5562 bfd_realloc (a8_relocs,
5563 sizeof (struct a8_erratum_reloc)
5564 * a8_reloc_table_size);
5565 }
5566
5567 a8_relocs[num_a8_relocs].from = from;
5568 a8_relocs[num_a8_relocs].destination = destination;
5569 a8_relocs[num_a8_relocs].r_type = r_type;
5570 a8_relocs[num_a8_relocs].branch_type = branch_type;
5571 a8_relocs[num_a8_relocs].sym_name = sym_name;
5572 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
5573 a8_relocs[num_a8_relocs].hash = hash;
5574
5575 num_a8_relocs++;
5576 }
5577 }
906e58ca
NC		 5578 }
5579
99059e56
RM		 5580 /* We're done with the internal relocs, free them. */
5581 if (elf_section_data (section)->relocs == NULL)
5582 free (internal_relocs);
5583 }
48229727 5584
99059e56 5585 if (htab->fix_cortex_a8)
48229727 5586 {
99059e56
RM		 5587 /* Sort relocs which might apply to Cortex-A8 erratum. */
5588 qsort (a8_relocs, num_a8_relocs,
eb7c4339 5589 sizeof (struct a8_erratum_reloc),
99059e56 5590 &a8_reloc_compare);
48229727 5591
99059e56
RM		 5592 /* Scan for branches which might trigger Cortex-A8 erratum. */
5593 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
48229727 5594 &num_a8_fixes, &a8_fix_table_size,
eb7c4339
NS		 5595 a8_relocs, num_a8_relocs,
5596 prev_num_a8_fixes, &stub_changed)
5597 != 0)
48229727 5598 goto error_ret_free_local;
5e681ec4 5599 }
5e681ec4
PB		 5600 }
5601
eb7c4339 5602 if (prev_num_a8_fixes != num_a8_fixes)
99059e56 5603 stub_changed = TRUE;
48229727 5604
906e58ca
NC		 5605 if (!stub_changed)
5606 break;
5e681ec4 5607
906e58ca
NC		 5608 /* OK, we've added some stubs. Find out the new size of the
5609 stub sections. */
5610 for (stub_sec = htab->stub_bfd->sections;
5611 stub_sec != NULL;
5612 stub_sec = stub_sec->next)
3e6b1042
DJ		 5613 {
5614 /* Ignore non-stub sections. */
5615 if (!strstr (stub_sec->name, STUB_SUFFIX))
5616 continue;
5617
5618 stub_sec->size = 0;
5619 }
b34b2d70 5620
906e58ca
NC		 5621 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
5622
48229727
JB		 5623 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
5624 if (htab->fix_cortex_a8)
99059e56
RM		 5625 for (i = 0; i < num_a8_fixes; i++)
5626 {
48229727
JB		 5627 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
5628 a8_fixes[i].section, htab);
5629
5630 if (stub_sec == NULL)
5631 goto error_ret_free_local;
5632
99059e56
RM		 5633 stub_sec->size
5634 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
5635 NULL);
5636 }
48229727
JB		 5637
5638
906e58ca
NC		 5639 /* Ask the linker to do its stuff. */
5640 (*htab->layout_sections_again) ();
ba93b8ac
DJ		 5641 }
5642
48229727
JB		 5643 /* Add stubs for Cortex-A8 erratum fixes now. */
5644 if (htab->fix_cortex_a8)
5645 {
5646 for (i = 0; i < num_a8_fixes; i++)
99059e56
RM		 5647 {
5648 struct elf32_arm_stub_hash_entry *stub_entry;
5649 char *stub_name = a8_fixes[i].stub_name;
5650 asection *section = a8_fixes[i].section;
5651 unsigned int section_id = a8_fixes[i].section->id;
5652 asection *link_sec = htab->stub_group[section_id].link_sec;
5653 asection *stub_sec = htab->stub_group[section_id].stub_sec;
5654 const insn_sequence *template_sequence;
5655 int template_size, size = 0;
5656
5657 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
5658 TRUE, FALSE);
5659 if (stub_entry == NULL)
5660 {
5661 (*_bfd_error_handler) (_("%s: cannot create stub entry %s"),
5662 section->owner,
5663 stub_name);
5664 return FALSE;
5665 }
5666
5667 stub_entry->stub_sec = stub_sec;
5668 stub_entry->stub_offset = 0;
5669 stub_entry->id_sec = link_sec;
5670 stub_entry->stub_type = a8_fixes[i].stub_type;
5671 stub_entry->target_section = a8_fixes[i].section;
5672 stub_entry->target_value = a8_fixes[i].offset;
5673 stub_entry->target_addend = a8_fixes[i].addend;
5674 stub_entry->orig_insn = a8_fixes[i].orig_insn;
35fc36a8 5675 stub_entry->branch_type = a8_fixes[i].branch_type;
48229727 5676
99059e56
RM		 5677 size = find_stub_size_and_template (a8_fixes[i].stub_type,
5678 &template_sequence,
5679 &template_size);
48229727 5680
99059e56
RM		 5681 stub_entry->stub_size = size;
5682 stub_entry->stub_template = template_sequence;
5683 stub_entry->stub_template_size = template_size;
5684 }
48229727
JB		 5685
5686 /* Stash the Cortex-A8 erratum fix array for use later in
99059e56 5687 elf32_arm_write_section(). */
48229727
JB		 5688 htab->a8_erratum_fixes = a8_fixes;
5689 htab->num_a8_erratum_fixes = num_a8_fixes;
5690 }
5691 else
5692 {
5693 htab->a8_erratum_fixes = NULL;
5694 htab->num_a8_erratum_fixes = 0;
5695 }
906e58ca
NC		 5696 return TRUE;
5697
5698 error_ret_free_local:
5699 return FALSE;
5e681ec4
PB		 5700}
5701
906e58ca
NC		 5702/* Build all the stubs associated with the current output file. The
5703 stubs are kept in a hash table attached to the main linker hash
5704 table. We also set up the .plt entries for statically linked PIC
5705 functions here. This function is called via arm_elf_finish in the
5706 linker. */
252b5132 5707
906e58ca
NC		 5708bfd_boolean
5709elf32_arm_build_stubs (struct bfd_link_info *info)
252b5132 5710{
906e58ca
NC		 5711 asection *stub_sec;
5712 struct bfd_hash_table *table;
5713 struct elf32_arm_link_hash_table *htab;
252b5132 5714
906e58ca 5715 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 5716 if (htab == NULL)
5717 return FALSE;
252b5132 5718
906e58ca
NC		 5719 for (stub_sec = htab->stub_bfd->sections;
5720 stub_sec != NULL;
5721 stub_sec = stub_sec->next)
252b5132 5722 {
906e58ca
NC		 5723 bfd_size_type size;
5724
8029a119 5725 /* Ignore non-stub sections. */
906e58ca
NC		 5726 if (!strstr (stub_sec->name, STUB_SUFFIX))
5727 continue;
5728
5729 /* Allocate memory to hold the linker stubs. */
5730 size = stub_sec->size;
21d799b5 5731 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
906e58ca
NC		 5732 if (stub_sec->contents == NULL && size != 0)
5733 return FALSE;
5734 stub_sec->size = 0;
252b5132
RH		 5735 }
5736
906e58ca
NC		 5737 /* Build the stubs as directed by the stub hash table. */
5738 table = &htab->stub_hash_table;
5739 bfd_hash_traverse (table, arm_build_one_stub, info);
eb7c4339
NS		 5740 if (htab->fix_cortex_a8)
5741 {
5742 /* Place the cortex a8 stubs last. */
5743 htab->fix_cortex_a8 = -1;
5744 bfd_hash_traverse (table, arm_build_one_stub, info);
5745 }
252b5132 5746
906e58ca 5747 return TRUE;
252b5132
RH		 5748}
5749
9b485d32
NC		 5750/* Locate the Thumb encoded calling stub for NAME. */
5751
252b5132 5752static struct elf_link_hash_entry *
57e8b36a
NC		 5753find_thumb_glue (struct bfd_link_info *link_info,
5754 const char *name,
f2a9dd69 5755 char **error_message)
252b5132
RH		 5756{
5757 char *tmp_name;
5758 struct elf_link_hash_entry *hash;
5759 struct elf32_arm_link_hash_table *hash_table;
5760
5761 /* We need a pointer to the armelf specific hash table. */
5762 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 5763 if (hash_table == NULL)
5764 return NULL;
252b5132 5765
21d799b5 5766 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 5767 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 5768
5769 BFD_ASSERT (tmp_name);
5770
5771 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
5772
5773 hash = elf_link_hash_lookup
b34976b6 5774 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 5775
b1657152
AM		 5776 if (hash == NULL
5777 && asprintf (error_message, _("unable to find THUMB glue '%s' for '%s'"),
5778 tmp_name, name) == -1)
5779 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 5780
5781 free (tmp_name);
5782
5783 return hash;
5784}
5785
9b485d32
NC		 5786/* Locate the ARM encoded calling stub for NAME. */
5787
252b5132 5788static struct elf_link_hash_entry *
57e8b36a
NC		 5789find_arm_glue (struct bfd_link_info *link_info,
5790 const char *name,
f2a9dd69 5791 char **error_message)
252b5132
RH		 5792{
5793 char *tmp_name;
5794 struct elf_link_hash_entry *myh;
5795 struct elf32_arm_link_hash_table *hash_table;
5796
5797 /* We need a pointer to the elfarm specific hash table. */
5798 hash_table = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 5799 if (hash_table == NULL)
5800 return NULL;
252b5132 5801
21d799b5 5802 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 5803 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 5804
5805 BFD_ASSERT (tmp_name);
5806
5807 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
5808
5809 myh = elf_link_hash_lookup
b34976b6 5810 (&(hash_table)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132 5811
b1657152
AM		 5812 if (myh == NULL
5813 && asprintf (error_message, _("unable to find ARM glue '%s' for '%s'"),
5814 tmp_name, name) == -1)
5815 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
252b5132
RH		 5816
5817 free (tmp_name);
5818
5819 return myh;
5820}
5821
8f6277f5 5822/* ARM->Thumb glue (static images):
252b5132
RH		 5823
5824 .arm
5825 __func_from_arm:
5826 ldr r12, __func_addr
5827 bx r12
5828 __func_addr:
906e58ca 5829 .word func @ behave as if you saw a ARM_32 reloc.
252b5132 5830
26079076
PB		 5831 (v5t static images)
5832 .arm
5833 __func_from_arm:
5834 ldr pc, __func_addr
5835 __func_addr:
906e58ca 5836 .word func @ behave as if you saw a ARM_32 reloc.
26079076 5837
8f6277f5
PB		 5838 (relocatable images)
5839 .arm
5840 __func_from_arm:
5841 ldr r12, __func_offset
5842 add r12, r12, pc
5843 bx r12
5844 __func_offset:
8029a119 5845 .word func - . */
8f6277f5
PB		 5846
5847#define ARM2THUMB_STATIC_GLUE_SIZE 12
252b5132
RH		 5848static const insn32 a2t1_ldr_insn = 0xe59fc000;
5849static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
5850static const insn32 a2t3_func_addr_insn = 0x00000001;
5851
26079076
PB		 5852#define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
5853static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
5854static const insn32 a2t2v5_func_addr_insn = 0x00000001;
5855
8f6277f5
PB		 5856#define ARM2THUMB_PIC_GLUE_SIZE 16
5857static const insn32 a2t1p_ldr_insn = 0xe59fc004;
5858static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
5859static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
5860
9b485d32 5861/* Thumb->ARM: Thumb->(non-interworking aware) ARM
252b5132 5862
8029a119
NC		 5863 .thumb .thumb
5864 .align 2 .align 2
5865 __func_from_thumb: __func_from_thumb:
5866 bx pc push {r6, lr}
5867 nop ldr r6, __func_addr
5868 .arm mov lr, pc
5869 b func bx r6
99059e56
RM		 5870 .arm
5871 ;; back_to_thumb
5872 ldmia r13! {r6, lr}
5873 bx lr
5874 __func_addr:
5875 .word func */
252b5132
RH		 5876
5877#define THUMB2ARM_GLUE_SIZE 8
5878static const insn16 t2a1_bx_pc_insn = 0x4778;
5879static const insn16 t2a2_noop_insn = 0x46c0;
5880static const insn32 t2a3_b_insn = 0xea000000;
5881
c7b8f16e 5882#define VFP11_ERRATUM_VENEER_SIZE 8
a504d23a
LA		 5883#define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
5884#define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
c7b8f16e 5885
845b51d6
PB		 5886#define ARM_BX_VENEER_SIZE 12
5887static const insn32 armbx1_tst_insn = 0xe3100001;
5888static const insn32 armbx2_moveq_insn = 0x01a0f000;
5889static const insn32 armbx3_bx_insn = 0xe12fff10;
5890
7e392df6 5891#ifndef ELFARM_NABI_C_INCLUDED
8029a119
NC		 5892static void
5893arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
252b5132
RH		 5894{
5895 asection * s;
8029a119 5896 bfd_byte * contents;
252b5132 5897
8029a119 5898 if (size == 0)
3e6b1042
DJ		 5899 {
5900 /* Do not include empty glue sections in the output. */
5901 if (abfd != NULL)
5902 {
3d4d4302 5903 s = bfd_get_linker_section (abfd, name);
3e6b1042
DJ		 5904 if (s != NULL)
5905 s->flags |= SEC_EXCLUDE;
5906 }
5907 return;
5908 }
252b5132 5909
8029a119 5910 BFD_ASSERT (abfd != NULL);
252b5132 5911
3d4d4302 5912 s = bfd_get_linker_section (abfd, name);
8029a119 5913 BFD_ASSERT (s != NULL);
252b5132 5914
21d799b5 5915 contents = (bfd_byte *) bfd_alloc (abfd, size);
252b5132 5916
8029a119
NC		 5917 BFD_ASSERT (s->size == size);
5918 s->contents = contents;
5919}
906e58ca 5920
8029a119
NC		 5921bfd_boolean
5922bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
5923{
5924 struct elf32_arm_link_hash_table * globals;
906e58ca 5925
8029a119
NC		 5926 globals = elf32_arm_hash_table (info);
5927 BFD_ASSERT (globals != NULL);
906e58ca 5928
8029a119
NC		 5929 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5930 globals->arm_glue_size,
5931 ARM2THUMB_GLUE_SECTION_NAME);
906e58ca 5932
8029a119
NC		 5933 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5934 globals->thumb_glue_size,
5935 THUMB2ARM_GLUE_SECTION_NAME);
252b5132 5936
8029a119
NC		 5937 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5938 globals->vfp11_erratum_glue_size,
5939 VFP11_ERRATUM_VENEER_SECTION_NAME);
845b51d6 5940
a504d23a
LA		 5941 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5942 globals->stm32l4xx_erratum_glue_size,
5943 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
5944
8029a119
NC		 5945 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
5946 globals->bx_glue_size,
845b51d6
PB		 5947 ARM_BX_GLUE_SECTION_NAME);
5948
b34976b6 5949 return TRUE;
252b5132
RH		 5950}
5951
a4fd1a8e 5952/* Allocate space and symbols for calling a Thumb function from Arm mode.
906e58ca
NC		 5953 returns the symbol identifying the stub. */
5954
a4fd1a8e 5955static struct elf_link_hash_entry *
57e8b36a
NC		 5956record_arm_to_thumb_glue (struct bfd_link_info * link_info,
5957 struct elf_link_hash_entry * h)
252b5132
RH		 5958{
5959 const char * name = h->root.root.string;
63b0f745 5960 asection * s;
252b5132
RH		 5961 char * tmp_name;
5962 struct elf_link_hash_entry * myh;
14a793b2 5963 struct bfd_link_hash_entry * bh;
252b5132 5964 struct elf32_arm_link_hash_table * globals;
dc810e39 5965 bfd_vma val;
2f475487 5966 bfd_size_type size;
252b5132
RH		 5967
5968 globals = elf32_arm_hash_table (link_info);
252b5132
RH		 5969 BFD_ASSERT (globals != NULL);
5970 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
5971
3d4d4302 5972 s = bfd_get_linker_section
252b5132
RH		 5973 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
5974
252b5132
RH		 5975 BFD_ASSERT (s != NULL);
5976
21d799b5 5977 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
99059e56 5978 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
252b5132
RH		 5979
5980 BFD_ASSERT (tmp_name);
5981
5982 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
5983
5984 myh = elf_link_hash_lookup
b34976b6 5985 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
252b5132
RH		 5986
5987 if (myh != NULL)
5988 {
9b485d32 5989 /* We've already seen this guy. */
252b5132 5990 free (tmp_name);
a4fd1a8e 5991 return myh;
252b5132
RH		 5992 }
5993
57e8b36a
NC		 5994 /* The only trick here is using hash_table->arm_glue_size as the value.
5995 Even though the section isn't allocated yet, this is where we will be
3dccd7b7
DJ		 5996 putting it. The +1 on the value marks that the stub has not been
5997 output yet - not that it is a Thumb function. */
14a793b2 5998 bh = NULL;
dc810e39
AM		 5999 val = globals->arm_glue_size + 1;
6000 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
6001 tmp_name, BSF_GLOBAL, s, val,
b34976b6 6002 NULL, TRUE, FALSE, &bh);
252b5132 6003
b7693d02
DJ		 6004 myh = (struct elf_link_hash_entry *) bh;
6005 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6006 myh->forced_local = 1;
6007
252b5132
RH		 6008 free (tmp_name);
6009
0e1862bb
L		 6010 if (bfd_link_pic (link_info)
6011 || globals->root.is_relocatable_executable
27e55c4d 6012 || globals->pic_veneer)
2f475487 6013 size = ARM2THUMB_PIC_GLUE_SIZE;
26079076
PB		 6014 else if (globals->use_blx)
6015 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
8f6277f5 6016 else
2f475487
AM		 6017 size = ARM2THUMB_STATIC_GLUE_SIZE;
6018
6019 s->size += size;
6020 globals->arm_glue_size += size;
252b5132 6021
a4fd1a8e 6022 return myh;
252b5132
RH		 6023}
6024
845b51d6
PB		 6025/* Allocate space for ARMv4 BX veneers. */
6026
6027static void
6028record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
6029{
6030 asection * s;
6031 struct elf32_arm_link_hash_table *globals;
6032 char *tmp_name;
6033 struct elf_link_hash_entry *myh;
6034 struct bfd_link_hash_entry *bh;
6035 bfd_vma val;
6036
6037 /* BX PC does not need a veneer. */
6038 if (reg == 15)
6039 return;
6040
6041 globals = elf32_arm_hash_table (link_info);
845b51d6
PB		 6042 BFD_ASSERT (globals != NULL);
6043 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
6044
6045 /* Check if this veneer has already been allocated. */
6046 if (globals->bx_glue_offset[reg])
6047 return;
6048
3d4d4302 6049 s = bfd_get_linker_section
845b51d6
PB		 6050 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
6051
6052 BFD_ASSERT (s != NULL);
6053
6054 /* Add symbol for veneer. */
21d799b5
NC		 6055 tmp_name = (char *)
6056 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
906e58ca 6057
845b51d6 6058 BFD_ASSERT (tmp_name);
906e58ca 6059
845b51d6 6060 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
906e58ca 6061
845b51d6
PB		 6062 myh = elf_link_hash_lookup
6063 (&(globals)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6064
845b51d6 6065 BFD_ASSERT (myh == NULL);
906e58ca 6066
845b51d6
PB		 6067 bh = NULL;
6068 val = globals->bx_glue_size;
6069 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
99059e56
RM		 6070 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6071 NULL, TRUE, FALSE, &bh);
845b51d6
PB		 6072
6073 myh = (struct elf_link_hash_entry *) bh;
6074 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6075 myh->forced_local = 1;
6076
6077 s->size += ARM_BX_VENEER_SIZE;
6078 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
6079 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
6080}
6081
6082
c7b8f16e
JB		 6083/* Add an entry to the code/data map for section SEC. */
6084
6085static void
6086elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
6087{
6088 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
6089 unsigned int newidx;
906e58ca 6090
c7b8f16e
JB		 6091 if (sec_data->map == NULL)
6092 {
21d799b5 6093 sec_data->map = (elf32_arm_section_map *)
99059e56 6094 bfd_malloc (sizeof (elf32_arm_section_map));
c7b8f16e
JB		 6095 sec_data->mapcount = 0;
6096 sec_data->mapsize = 1;
6097 }
906e58ca 6098
c7b8f16e 6099 newidx = sec_data->mapcount++;
906e58ca 6100
c7b8f16e
JB		 6101 if (sec_data->mapcount > sec_data->mapsize)
6102 {
6103 sec_data->mapsize *= 2;
21d799b5 6104 sec_data->map = (elf32_arm_section_map *)
99059e56
RM		 6105 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
6106 * sizeof (elf32_arm_section_map));
515ef31d
NC		 6107 }
6108
6109 if (sec_data->map)
6110 {
6111 sec_data->map[newidx].vma = vma;
6112 sec_data->map[newidx].type = type;
c7b8f16e 6113 }
c7b8f16e
JB		 6114}
6115
6116
6117/* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
6118 veneers are handled for now. */
6119
6120static bfd_vma
6121record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
99059e56
RM		 6122 elf32_vfp11_erratum_list *branch,
6123 bfd *branch_bfd,
6124 asection *branch_sec,
6125 unsigned int offset)
c7b8f16e
JB		 6126{
6127 asection *s;
6128 struct elf32_arm_link_hash_table *hash_table;
6129 char *tmp_name;
6130 struct elf_link_hash_entry *myh;
6131 struct bfd_link_hash_entry *bh;
6132 bfd_vma val;
6133 struct _arm_elf_section_data *sec_data;
c7b8f16e 6134 elf32_vfp11_erratum_list *newerr;
906e58ca 6135
c7b8f16e 6136 hash_table = elf32_arm_hash_table (link_info);
c7b8f16e
JB		 6137 BFD_ASSERT (hash_table != NULL);
6138 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
906e58ca 6139
3d4d4302 6140 s = bfd_get_linker_section
c7b8f16e 6141 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
906e58ca 6142
c7b8f16e 6143 sec_data = elf32_arm_section_data (s);
906e58ca 6144
c7b8f16e 6145 BFD_ASSERT (s != NULL);
906e58ca 6146
21d799b5 6147 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 6148 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
906e58ca 6149
c7b8f16e 6150 BFD_ASSERT (tmp_name);
906e58ca 6151
c7b8f16e
JB		 6152 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
6153 hash_table->num_vfp11_fixes);
906e58ca 6154
c7b8f16e
JB		 6155 myh = elf_link_hash_lookup
6156 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6157
c7b8f16e 6158 BFD_ASSERT (myh == NULL);
906e58ca 6159
c7b8f16e
JB		 6160 bh = NULL;
6161 val = hash_table->vfp11_erratum_glue_size;
6162 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
99059e56
RM		 6163 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6164 NULL, TRUE, FALSE, &bh);
c7b8f16e
JB		 6165
6166 myh = (struct elf_link_hash_entry *) bh;
6167 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6168 myh->forced_local = 1;
6169
6170 /* Link veneer back to calling location. */
c7e2358a 6171 sec_data->erratumcount += 1;
21d799b5
NC		 6172 newerr = (elf32_vfp11_erratum_list *)
6173 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
906e58ca 6174
c7b8f16e
JB		 6175 newerr->type = VFP11_ERRATUM_ARM_VENEER;
6176 newerr->vma = -1;
6177 newerr->u.v.branch = branch;
6178 newerr->u.v.id = hash_table->num_vfp11_fixes;
6179 branch->u.b.veneer = newerr;
6180
6181 newerr->next = sec_data->erratumlist;
6182 sec_data->erratumlist = newerr;
6183
6184 /* A symbol for the return from the veneer. */
6185 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
6186 hash_table->num_vfp11_fixes);
6187
6188 myh = elf_link_hash_lookup
6189 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
906e58ca 6190
c7b8f16e
JB		 6191 if (myh != NULL)
6192 abort ();
6193
6194 bh = NULL;
6195 val = offset + 4;
6196 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
6197 branch_sec, val, NULL, TRUE, FALSE, &bh);
906e58ca 6198
c7b8f16e
JB		 6199 myh = (struct elf_link_hash_entry *) bh;
6200 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6201 myh->forced_local = 1;
6202
6203 free (tmp_name);
906e58ca 6204
c7b8f16e
JB		 6205 /* Generate a mapping symbol for the veneer section, and explicitly add an
6206 entry for that symbol to the code/data map for the section. */
6207 if (hash_table->vfp11_erratum_glue_size == 0)
6208 {
6209 bh = NULL;
6210 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
99059e56 6211 ever requires this erratum fix. */
c7b8f16e
JB		 6212 _bfd_generic_link_add_one_symbol (link_info,
6213 hash_table->bfd_of_glue_owner, "$a",
6214 BSF_LOCAL, s, 0, NULL,
99059e56 6215 TRUE, FALSE, &bh);
c7b8f16e
JB		 6216
6217 myh = (struct elf_link_hash_entry *) bh;
6218 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
6219 myh->forced_local = 1;
906e58ca 6220
c7b8f16e 6221 /* The elf32_arm_init_maps function only cares about symbols from input
99059e56
RM		 6222 BFDs. We must make a note of this generated mapping symbol
6223 ourselves so that code byteswapping works properly in
6224 elf32_arm_write_section. */
c7b8f16e
JB		 6225 elf32_arm_section_map_add (s, 'a', 0);
6226 }
906e58ca 6227
c7b8f16e
JB		 6228 s->size += VFP11_ERRATUM_VENEER_SIZE;
6229 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
6230 hash_table->num_vfp11_fixes++;
906e58ca 6231
c7b8f16e
JB		 6232 /* The offset of the veneer. */
6233 return val;
6234}
6235
a504d23a
LA		 6236/* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
6237 veneers need to be handled because used only in Cortex-M. */
6238
6239static bfd_vma
6240record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
6241 elf32_stm32l4xx_erratum_list *branch,
6242 bfd *branch_bfd,
6243 asection *branch_sec,
6244 unsigned int offset,
6245 bfd_size_type veneer_size)
6246{
6247 asection *s;
6248 struct elf32_arm_link_hash_table *hash_table;
6249 char *tmp_name;
6250 struct elf_link_hash_entry *myh;
6251 struct bfd_link_hash_entry *bh;
6252 bfd_vma val;
6253 struct _arm_elf_section_data *sec_data;
6254 elf32_stm32l4xx_erratum_list *newerr;
6255
6256 hash_table = elf32_arm_hash_table (link_info);
6257 BFD_ASSERT (hash_table != NULL);
6258 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
6259
6260 s = bfd_get_linker_section
6261 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
6262
6263 BFD_ASSERT (s != NULL);
6264
6265 sec_data = elf32_arm_section_data (s);
6266
6267 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
6268 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
6269
6270 BFD_ASSERT (tmp_name);
6271
6272 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
6273 hash_table->num_stm32l4xx_fixes);
6274
6275 myh = elf_link_hash_lookup
6276 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
6277
6278 BFD_ASSERT (myh == NULL);
6279
6280 bh = NULL;
6281 val = hash_table->stm32l4xx_erratum_glue_size;
6282 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
6283 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
6284 NULL, TRUE, FALSE, &bh);
6285
6286 myh = (struct elf_link_hash_entry *) bh;
6287 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6288 myh->forced_local = 1;
6289
6290 /* Link veneer back to calling location. */
6291 sec_data->stm32l4xx_erratumcount += 1;
6292 newerr = (elf32_stm32l4xx_erratum_list *)
6293 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
6294
6295 newerr->type = STM32L4XX_ERRATUM_VENEER;
6296 newerr->vma = -1;
6297 newerr->u.v.branch = branch;
6298 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
6299 branch->u.b.veneer = newerr;
6300
6301 newerr->next = sec_data->stm32l4xx_erratumlist;
6302 sec_data->stm32l4xx_erratumlist = newerr;
6303
6304 /* A symbol for the return from the veneer. */
6305 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
6306 hash_table->num_stm32l4xx_fixes);
6307
6308 myh = elf_link_hash_lookup
6309 (&(hash_table)->root, tmp_name, FALSE, FALSE, FALSE);
6310
6311 if (myh != NULL)
6312 abort ();
6313
6314 bh = NULL;
6315 val = offset + 4;
6316 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
6317 branch_sec, val, NULL, TRUE, FALSE, &bh);
6318
6319 myh = (struct elf_link_hash_entry *) bh;
6320 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
6321 myh->forced_local = 1;
6322
6323 free (tmp_name);
6324
6325 /* Generate a mapping symbol for the veneer section, and explicitly add an
6326 entry for that symbol to the code/data map for the section. */
6327 if (hash_table->stm32l4xx_erratum_glue_size == 0)
6328 {
6329 bh = NULL;
6330 /* Creates a THUMB symbol since there is no other choice. */
6331 _bfd_generic_link_add_one_symbol (link_info,
6332 hash_table->bfd_of_glue_owner, "$t",
6333 BSF_LOCAL, s, 0, NULL,
6334 TRUE, FALSE, &bh);
6335
6336 myh = (struct elf_link_hash_entry *) bh;
6337 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
6338 myh->forced_local = 1;
6339
6340 /* The elf32_arm_init_maps function only cares about symbols from input
6341 BFDs. We must make a note of this generated mapping symbol
6342 ourselves so that code byteswapping works properly in
6343 elf32_arm_write_section. */
6344 elf32_arm_section_map_add (s, 't', 0);
6345 }
6346
6347 s->size += veneer_size;
6348 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
6349 hash_table->num_stm32l4xx_fixes++;
6350
6351 /* The offset of the veneer. */
6352 return val;
6353}
6354
8029a119 6355#define ARM_GLUE_SECTION_FLAGS \
3e6b1042
DJ		 6356 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
6357 | SEC_READONLY | SEC_LINKER_CREATED)
8029a119
NC		 6358
6359/* Create a fake section for use by the ARM backend of the linker. */
6360
6361static bfd_boolean
6362arm_make_glue_section (bfd * abfd, const char * name)
6363{
6364 asection * sec;
6365
3d4d4302 6366 sec = bfd_get_linker_section (abfd, name);
8029a119
NC		 6367 if (sec != NULL)
6368 /* Already made. */
6369 return TRUE;
6370
3d4d4302 6371 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
8029a119
NC		 6372
6373 if (sec == NULL
6374 || !bfd_set_section_alignment (abfd, sec, 2))
6375 return FALSE;
6376
6377 /* Set the gc mark to prevent the section from being removed by garbage
6378 collection, despite the fact that no relocs refer to this section. */
6379 sec->gc_mark = 1;
6380
6381 return TRUE;
6382}
6383
1db37fe6
YG		 6384/* Set size of .plt entries. This function is called from the
6385 linker scripts in ld/emultempl/{armelf}.em. */
6386
6387void
6388bfd_elf32_arm_use_long_plt (void)
6389{
6390 elf32_arm_use_long_plt_entry = TRUE;
6391}
6392
8afb0e02
NC		 6393/* Add the glue sections to ABFD. This function is called from the
6394 linker scripts in ld/emultempl/{armelf}.em. */
9b485d32 6395
b34976b6 6396bfd_boolean
57e8b36a
NC		 6397bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
6398 struct bfd_link_info *info)
252b5132 6399{
a504d23a
LA		 6400 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
6401 bfd_boolean dostm32l4xx = globals
6402 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
6403 bfd_boolean addglue;
6404
8afb0e02
NC		 6405 /* If we are only performing a partial
6406 link do not bother adding the glue. */
0e1862bb 6407 if (bfd_link_relocatable (info))
b34976b6 6408 return TRUE;
252b5132 6409
a504d23a 6410 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
8029a119
NC		 6411 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
6412 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
6413 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
a504d23a
LA		 6414
6415 if (!dostm32l4xx)
6416 return addglue;
6417
6418 return addglue
6419 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
8afb0e02
NC		 6420}
6421
6422/* Select a BFD to be used to hold the sections used by the glue code.
6423 This function is called from the linker scripts in ld/emultempl/
8029a119 6424 {armelf/pe}.em. */
8afb0e02 6425
b34976b6 6426bfd_boolean
57e8b36a 6427bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
8afb0e02
NC		 6428{
6429 struct elf32_arm_link_hash_table *globals;
6430
6431 /* If we are only performing a partial link
6432 do not bother getting a bfd to hold the glue. */
0e1862bb 6433 if (bfd_link_relocatable (info))
b34976b6 6434 return TRUE;
8afb0e02 6435
b7693d02
DJ		 6436 /* Make sure we don't attach the glue sections to a dynamic object. */
6437 BFD_ASSERT (!(abfd->flags & DYNAMIC));
6438
8afb0e02 6439 globals = elf32_arm_hash_table (info);
8afb0e02
NC		 6440 BFD_ASSERT (globals != NULL);
6441
6442 if (globals->bfd_of_glue_owner != NULL)
b34976b6 6443 return TRUE;
8afb0e02 6444
252b5132
RH		 6445 /* Save the bfd for later use. */
6446 globals->bfd_of_glue_owner = abfd;
cedb70c5 6447
b34976b6 6448 return TRUE;
252b5132
RH		 6449}
6450
906e58ca
NC		 6451static void
6452check_use_blx (struct elf32_arm_link_hash_table *globals)
39b41c9c 6453{
2de70689
MGD		 6454 int cpu_arch;
6455
b38cadfb 6456 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
2de70689
MGD		 6457 Tag_CPU_arch);
6458
6459 if (globals->fix_arm1176)
6460 {
6461 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
6462 globals->use_blx = 1;
6463 }
6464 else
6465 {
6466 if (cpu_arch > TAG_CPU_ARCH_V4T)
6467 globals->use_blx = 1;
6468 }
39b41c9c
PB		 6469}
6470
b34976b6 6471bfd_boolean
57e8b36a 6472bfd_elf32_arm_process_before_allocation (bfd *abfd,
d504ffc8 6473 struct bfd_link_info *link_info)
252b5132
RH		 6474{
6475 Elf_Internal_Shdr *symtab_hdr;
6cdc0ccc 6476 Elf_Internal_Rela *internal_relocs = NULL;
252b5132
RH		 6477 Elf_Internal_Rela *irel, *irelend;
6478 bfd_byte *contents = NULL;
252b5132
RH		 6479
6480 asection *sec;
6481 struct elf32_arm_link_hash_table *globals;
6482
6483 /* If we are only performing a partial link do not bother
6484 to construct any glue. */
0e1862bb 6485 if (bfd_link_relocatable (link_info))
b34976b6 6486 return TRUE;
252b5132 6487
39ce1a6a
NC		 6488 /* Here we have a bfd that is to be included on the link. We have a
6489 hook to do reloc rummaging, before section sizes are nailed down. */
252b5132 6490 globals = elf32_arm_hash_table (link_info);
252b5132 6491 BFD_ASSERT (globals != NULL);
39ce1a6a
NC		 6492
6493 check_use_blx (globals);
252b5132 6494
d504ffc8 6495 if (globals->byteswap_code && !bfd_big_endian (abfd))
e489d0ae 6496 {
d003868e
AM		 6497 _bfd_error_handler (_("%B: BE8 images only valid in big-endian mode."),
6498 abfd);
e489d0ae
PB		 6499 return FALSE;
6500 }
f21f3fe0 6501
39ce1a6a
NC		 6502 /* PR 5398: If we have not decided to include any loadable sections in
6503 the output then we will not have a glue owner bfd. This is OK, it
6504 just means that there is nothing else for us to do here. */
6505 if (globals->bfd_of_glue_owner == NULL)
6506 return TRUE;
6507
252b5132
RH		 6508 /* Rummage around all the relocs and map the glue vectors. */
6509 sec = abfd->sections;
6510
6511 if (sec == NULL)
b34976b6 6512 return TRUE;
252b5132
RH		 6513
6514 for (; sec != NULL; sec = sec->next)
6515 {
6516 if (sec->reloc_count == 0)
6517 continue;
6518
2f475487
AM		 6519 if ((sec->flags & SEC_EXCLUDE) != 0)
6520 continue;
6521
0ffa91dd 6522 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 6523
9b485d32 6524 /* Load the relocs. */
6cdc0ccc 6525 internal_relocs
906e58ca 6526 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, FALSE);
252b5132 6527
6cdc0ccc
AM		 6528 if (internal_relocs == NULL)
6529 goto error_return;
252b5132 6530
6cdc0ccc
AM		 6531 irelend = internal_relocs + sec->reloc_count;
6532 for (irel = internal_relocs; irel < irelend; irel++)
252b5132
RH		 6533 {
6534 long r_type;
6535 unsigned long r_index;
252b5132
RH		 6536
6537 struct elf_link_hash_entry *h;
6538
6539 r_type = ELF32_R_TYPE (irel->r_info);
6540 r_index = ELF32_R_SYM (irel->r_info);
6541
9b485d32 6542 /* These are the only relocation types we care about. */
ba96a88f 6543 if ( r_type != R_ARM_PC24
845b51d6 6544 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
252b5132
RH		 6545 continue;
6546
6547 /* Get the section contents if we haven't done so already. */
6548 if (contents == NULL)
6549 {
6550 /* Get cached copy if it exists. */
6551 if (elf_section_data (sec)->this_hdr.contents != NULL)
6552 contents = elf_section_data (sec)->this_hdr.contents;
6553 else
6554 {
6555 /* Go get them off disk. */
57e8b36a 6556 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
252b5132
RH		 6557 goto error_return;
6558 }
6559 }
6560
845b51d6
PB		 6561 if (r_type == R_ARM_V4BX)
6562 {
6563 int reg;
6564
6565 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
6566 record_arm_bx_glue (link_info, reg);
6567 continue;
6568 }
6569
a7c10850 6570 /* If the relocation is not against a symbol it cannot concern us. */
252b5132
RH		 6571 h = NULL;
6572
9b485d32 6573 /* We don't care about local symbols. */
252b5132
RH		 6574 if (r_index < symtab_hdr->sh_info)
6575 continue;
6576
9b485d32 6577 /* This is an external symbol. */
252b5132
RH		 6578 r_index -= symtab_hdr->sh_info;
6579 h = (struct elf_link_hash_entry *)
6580 elf_sym_hashes (abfd)[r_index];
6581
6582 /* If the relocation is against a static symbol it must be within
6583 the current section and so cannot be a cross ARM/Thumb relocation. */
6584 if (h == NULL)
6585 continue;
6586
d504ffc8
DJ		 6587 /* If the call will go through a PLT entry then we do not need
6588 glue. */
362d30a1 6589 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
b7693d02
DJ		 6590 continue;
6591
252b5132
RH		 6592 switch (r_type)
6593 {
6594 case R_ARM_PC24:
6595 /* This one is a call from arm code. We need to look up
99059e56
RM		 6596 the target of the call. If it is a thumb target, we
6597 insert glue. */
35fc36a8 6598 if (h->target_internal == ST_BRANCH_TO_THUMB)
252b5132
RH		 6599 record_arm_to_thumb_glue (link_info, h);
6600 break;
6601
252b5132 6602 default:
c6596c5e 6603 abort ();
252b5132
RH		 6604 }
6605 }
6cdc0ccc
AM		 6606
6607 if (contents != NULL
6608 && elf_section_data (sec)->this_hdr.contents != contents)
6609 free (contents);
6610 contents = NULL;
6611
6612 if (internal_relocs != NULL
6613 && elf_section_data (sec)->relocs != internal_relocs)
6614 free (internal_relocs);
6615 internal_relocs = NULL;
252b5132
RH		 6616 }
6617
b34976b6 6618 return TRUE;
9a5aca8c 6619
252b5132 6620error_return:
6cdc0ccc
AM		 6621 if (contents != NULL
6622 && elf_section_data (sec)->this_hdr.contents != contents)
6623 free (contents);
6624 if (internal_relocs != NULL
6625 && elf_section_data (sec)->relocs != internal_relocs)
6626 free (internal_relocs);
9a5aca8c 6627
b34976b6 6628 return FALSE;
252b5132 6629}
7e392df6 6630#endif
252b5132 6631
eb043451 6632
c7b8f16e
JB		 6633/* Initialise maps of ARM/Thumb/data for input BFDs. */
6634
6635void
6636bfd_elf32_arm_init_maps (bfd *abfd)
6637{
6638 Elf_Internal_Sym *isymbuf;
6639 Elf_Internal_Shdr *hdr;
6640 unsigned int i, localsyms;
6641
af1f4419
NC		 6642 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
6643 if (! is_arm_elf (abfd))
6644 return;
6645
c7b8f16e
JB		 6646 if ((abfd->flags & DYNAMIC) != 0)
6647 return;
6648
0ffa91dd 6649 hdr = & elf_symtab_hdr (abfd);
c7b8f16e
JB		 6650 localsyms = hdr->sh_info;
6651
6652 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
6653 should contain the number of local symbols, which should come before any
6654 global symbols. Mapping symbols are always local. */
6655 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
6656 NULL);
6657
6658 /* No internal symbols read? Skip this BFD. */
6659 if (isymbuf == NULL)
6660 return;
6661
6662 for (i = 0; i < localsyms; i++)
6663 {
6664 Elf_Internal_Sym *isym = &isymbuf[i];
6665 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
6666 const char *name;
906e58ca 6667
c7b8f16e 6668 if (sec != NULL
99059e56
RM		 6669 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
6670 {
6671 name = bfd_elf_string_from_elf_section (abfd,
6672 hdr->sh_link, isym->st_name);
906e58ca 6673
99059e56 6674 if (bfd_is_arm_special_symbol_name (name,
c7b8f16e 6675 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
99059e56
RM		 6676 elf32_arm_section_map_add (sec, name[1], isym->st_value);
6677 }
c7b8f16e
JB		 6678 }
6679}
6680
6681
48229727
JB		 6682/* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
6683 say what they wanted. */
6684
6685void
6686bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
6687{
6688 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
6689 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
6690
4dfe6ac6
NC		 6691 if (globals == NULL)
6692 return;
6693
48229727
JB		 6694 if (globals->fix_cortex_a8 == -1)
6695 {
6696 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
6697 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
6698 && (out_attr[Tag_CPU_arch_profile].i == 'A'
6699 || out_attr[Tag_CPU_arch_profile].i == 0))
6700 globals->fix_cortex_a8 = 1;
6701 else
6702 globals->fix_cortex_a8 = 0;
6703 }
6704}
6705
6706
c7b8f16e
JB		 6707void
6708bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
6709{
6710 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
104d59d1 6711 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
906e58ca 6712
4dfe6ac6
NC		 6713 if (globals == NULL)
6714 return;
c7b8f16e
JB		 6715 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
6716 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
6717 {
6718 switch (globals->vfp11_fix)
99059e56
RM		 6719 {
6720 case BFD_ARM_VFP11_FIX_DEFAULT:
6721 case BFD_ARM_VFP11_FIX_NONE:
6722 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
6723 break;
6724
6725 default:
6726 /* Give a warning, but do as the user requests anyway. */
6727 (*_bfd_error_handler) (_("%B: warning: selected VFP11 erratum "
6728 "workaround is not necessary for target architecture"), obfd);
6729 }
c7b8f16e
JB		 6730 }
6731 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
6732 /* For earlier architectures, we might need the workaround, but do not
6733 enable it by default. If users is running with broken hardware, they
6734 must enable the erratum fix explicitly. */
6735 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
6736}
6737
a504d23a
LA		 6738void
6739bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
6740{
6741 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
6742 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
6743
6744 if (globals == NULL)
6745 return;
6746
6747 /* We assume only Cortex-M4 may require the fix. */
6748 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
6749 || out_attr[Tag_CPU_arch_profile].i != 'M')
6750 {
6751 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
6752 /* Give a warning, but do as the user requests anyway. */
6753 (*_bfd_error_handler)
6754 (_("%B: warning: selected STM32L4XX erratum "
6755 "workaround is not necessary for target architecture"), obfd);
6756 }
6757}
c7b8f16e 6758
906e58ca
NC		 6759enum bfd_arm_vfp11_pipe
6760{
c7b8f16e
JB		 6761 VFP11_FMAC,
6762 VFP11_LS,
6763 VFP11_DS,
6764 VFP11_BAD
6765};
6766
6767/* Return a VFP register number. This is encoded as RX:X for single-precision
6768 registers, or X:RX for double-precision registers, where RX is the group of
6769 four bits in the instruction encoding and X is the single extension bit.
6770 RX and X fields are specified using their lowest (starting) bit. The return
6771 value is:
6772
6773 0...31: single-precision registers s0...s31
6774 32...63: double-precision registers d0...d31.
906e58ca 6775
c7b8f16e
JB		 6776 Although X should be zero for VFP11 (encoding d0...d15 only), we might
6777 encounter VFP3 instructions, so we allow the full range for DP registers. */
906e58ca 6778
c7b8f16e
JB		 6779static unsigned int
6780bfd_arm_vfp11_regno (unsigned int insn, bfd_boolean is_double, unsigned int rx,
99059e56 6781 unsigned int x)
c7b8f16e
JB		 6782{
6783 if (is_double)
6784 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
6785 else
6786 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
6787}
6788
6789/* Set bits in *WMASK according to a register number REG as encoded by
6790 bfd_arm_vfp11_regno(). Ignore d16-d31. */
6791
6792static void
6793bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
6794{
6795 if (reg < 32)
6796 *wmask |= 1 << reg;
6797 else if (reg < 48)
6798 *wmask |= 3 << ((reg - 32) * 2);
6799}
6800
6801/* Return TRUE if WMASK overwrites anything in REGS. */
6802
6803static bfd_boolean
6804bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
6805{
6806 int i;
906e58ca 6807
c7b8f16e
JB		 6808 for (i = 0; i < numregs; i++)
6809 {
6810 unsigned int reg = regs[i];
6811
6812 if (reg < 32 && (wmask & (1 << reg)) != 0)
99059e56 6813 return TRUE;
906e58ca 6814
c7b8f16e
JB		 6815 reg -= 32;
6816
6817 if (reg >= 16)
99059e56 6818 continue;
906e58ca 6819
c7b8f16e 6820 if ((wmask & (3 << (reg * 2))) != 0)
99059e56 6821 return TRUE;
c7b8f16e 6822 }
906e58ca 6823
c7b8f16e
JB		 6824 return FALSE;
6825}
6826
6827/* In this function, we're interested in two things: finding input registers
6828 for VFP data-processing instructions, and finding the set of registers which
6829 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
6830 hold the written set, so FLDM etc. are easy to deal with (we're only
6831 interested in 32 SP registers or 16 dp registers, due to the VFP version
6832 implemented by the chip in question). DP registers are marked by setting
6833 both SP registers in the write mask). */
6834
6835static enum bfd_arm_vfp11_pipe
6836bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
99059e56 6837 int *numregs)
c7b8f16e 6838{
91d6fa6a 6839 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
c7b8f16e
JB		 6840 bfd_boolean is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
6841
6842 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
6843 {
6844 unsigned int pqrs;
6845 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
6846 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
6847
6848 pqrs = ((insn & 0x00800000) >> 20)
99059e56
RM		 6849 | ((insn & 0x00300000) >> 19)
6850 | ((insn & 0x00000040) >> 6);
c7b8f16e
JB		 6851
6852 switch (pqrs)
99059e56
RM		 6853 {
6854 case 0: /* fmac[sd]. */
6855 case 1: /* fnmac[sd]. */
6856 case 2: /* fmsc[sd]. */
6857 case 3: /* fnmsc[sd]. */
6858 vpipe = VFP11_FMAC;
6859 bfd_arm_vfp11_write_mask (destmask, fd);
6860 regs[0] = fd;
6861 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
6862 regs[2] = fm;
6863 *numregs = 3;
6864 break;
6865
6866 case 4: /* fmul[sd]. */
6867 case 5: /* fnmul[sd]. */
6868 case 6: /* fadd[sd]. */
6869 case 7: /* fsub[sd]. */
6870 vpipe = VFP11_FMAC;
6871 goto vfp_binop;
6872
6873 case 8: /* fdiv[sd]. */
6874 vpipe = VFP11_DS;
6875 vfp_binop:
6876 bfd_arm_vfp11_write_mask (destmask, fd);
6877 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
6878 regs[1] = fm;
6879 *numregs = 2;
6880 break;
6881
6882 case 15: /* extended opcode. */
6883 {
6884 unsigned int extn = ((insn >> 15) & 0x1e)
6885 | ((insn >> 7) & 1);
6886
6887 switch (extn)
6888 {
6889 case 0: /* fcpy[sd]. */
6890 case 1: /* fabs[sd]. */
6891 case 2: /* fneg[sd]. */
6892 case 8: /* fcmp[sd]. */
6893 case 9: /* fcmpe[sd]. */
6894 case 10: /* fcmpz[sd]. */
6895 case 11: /* fcmpez[sd]. */
6896 case 16: /* fuito[sd]. */
6897 case 17: /* fsito[sd]. */
6898 case 24: /* ftoui[sd]. */
6899 case 25: /* ftouiz[sd]. */
6900 case 26: /* ftosi[sd]. */
6901 case 27: /* ftosiz[sd]. */
6902 /* These instructions will not bounce due to underflow. */
6903 *numregs = 0;
6904 vpipe = VFP11_FMAC;
6905 break;
6906
6907 case 3: /* fsqrt[sd]. */
6908 /* fsqrt cannot underflow, but it can (perhaps) overwrite
6909 registers to cause the erratum in previous instructions. */
6910 bfd_arm_vfp11_write_mask (destmask, fd);
6911 vpipe = VFP11_DS;
6912 break;
6913
6914 case 15: /* fcvt{ds,sd}. */
6915 {
6916 int rnum = 0;
6917
6918 bfd_arm_vfp11_write_mask (destmask, fd);
c7b8f16e
JB		 6919
6920 /* Only FCVTSD can underflow. */
99059e56
RM		 6921 if ((insn & 0x100) != 0)
6922 regs[rnum++] = fm;
c7b8f16e 6923
99059e56 6924 *numregs = rnum;
c7b8f16e 6925
99059e56
RM		 6926 vpipe = VFP11_FMAC;
6927 }
6928 break;
c7b8f16e 6929
99059e56
RM		 6930 default:
6931 return VFP11_BAD;
6932 }
6933 }
6934 break;
c7b8f16e 6935
99059e56
RM		 6936 default:
6937 return VFP11_BAD;
6938 }
c7b8f16e
JB		 6939 }
6940 /* Two-register transfer. */
6941 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
6942 {
6943 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
906e58ca 6944
c7b8f16e
JB		 6945 if ((insn & 0x100000) == 0)
6946 {
99059e56
RM		 6947 if (is_double)
6948 bfd_arm_vfp11_write_mask (destmask, fm);
6949 else
6950 {
6951 bfd_arm_vfp11_write_mask (destmask, fm);
6952 bfd_arm_vfp11_write_mask (destmask, fm + 1);
6953 }
c7b8f16e
JB		 6954 }
6955
91d6fa6a 6956 vpipe = VFP11_LS;
c7b8f16e
JB		 6957 }
6958 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
6959 {
6960 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
6961 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
906e58ca 6962
c7b8f16e 6963 switch (puw)
99059e56
RM		 6964 {
6965 case 0: /* Two-reg transfer. We should catch these above. */
6966 abort ();
906e58ca 6967
99059e56
RM		 6968 case 2: /* fldm[sdx]. */
6969 case 3:
6970 case 5:
6971 {
6972 unsigned int i, offset = insn & 0xff;
c7b8f16e 6973
99059e56
RM		 6974 if (is_double)
6975 offset >>= 1;
c7b8f16e 6976
99059e56
RM		 6977 for (i = fd; i < fd + offset; i++)
6978 bfd_arm_vfp11_write_mask (destmask, i);
6979 }
6980 break;
906e58ca 6981
99059e56
RM		 6982 case 4: /* fld[sd]. */
6983 case 6:
6984 bfd_arm_vfp11_write_mask (destmask, fd);
6985 break;
906e58ca 6986
99059e56
RM		 6987 default:
6988 return VFP11_BAD;
6989 }
c7b8f16e 6990
91d6fa6a 6991 vpipe = VFP11_LS;
c7b8f16e
JB		 6992 }
6993 /* Single-register transfer. Note L==0. */
6994 else if ((insn & 0x0f100e10) == 0x0e000a10)
6995 {
6996 unsigned int opcode = (insn >> 21) & 7;
6997 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
6998
6999 switch (opcode)
99059e56
RM		 7000 {
7001 case 0: /* fmsr/fmdlr. */
7002 case 1: /* fmdhr. */
7003 /* Mark fmdhr and fmdlr as writing to the whole of the DP
7004 destination register. I don't know if this is exactly right,
7005 but it is the conservative choice. */
7006 bfd_arm_vfp11_write_mask (destmask, fn);
7007 break;
7008
7009 case 7: /* fmxr. */
7010 break;
7011 }
c7b8f16e 7012
91d6fa6a 7013 vpipe = VFP11_LS;
c7b8f16e
JB		 7014 }
7015
91d6fa6a 7016 return vpipe;
c7b8f16e
JB		 7017}
7018
7019
7020static int elf32_arm_compare_mapping (const void * a, const void * b);
7021
7022
7023/* Look for potentially-troublesome code sequences which might trigger the
7024 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
7025 (available from ARM) for details of the erratum. A short version is
7026 described in ld.texinfo. */
7027
7028bfd_boolean
7029bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
7030{
7031 asection *sec;
7032 bfd_byte *contents = NULL;
7033 int state = 0;
7034 int regs[3], numregs = 0;
7035 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7036 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
906e58ca 7037
4dfe6ac6
NC		 7038 if (globals == NULL)
7039 return FALSE;
7040
c7b8f16e
JB		 7041 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
7042 The states transition as follows:
906e58ca 7043
c7b8f16e 7044 0 -> 1 (vector) or 0 -> 2 (scalar)
99059e56
RM		 7045 A VFP FMAC-pipeline instruction has been seen. Fill
7046 regs[0]..regs[numregs-1] with its input operands. Remember this
7047 instruction in 'first_fmac'.
c7b8f16e
JB		 7048
7049 1 -> 2
99059e56
RM		 7050 Any instruction, except for a VFP instruction which overwrites
7051 regs[*].
906e58ca 7052
c7b8f16e
JB		 7053 1 -> 3 [ -> 0 ] or
7054 2 -> 3 [ -> 0 ]
99059e56
RM		 7055 A VFP instruction has been seen which overwrites any of regs[*].
7056 We must make a veneer! Reset state to 0 before examining next
7057 instruction.
906e58ca 7058
c7b8f16e 7059 2 -> 0
99059e56
RM		 7060 If we fail to match anything in state 2, reset to state 0 and reset
7061 the instruction pointer to the instruction after 'first_fmac'.
c7b8f16e
JB		 7062
7063 If the VFP11 vector mode is in use, there must be at least two unrelated
7064 instructions between anti-dependent VFP11 instructions to properly avoid
906e58ca 7065 triggering the erratum, hence the use of the extra state 1. */
c7b8f16e
JB		 7066
7067 /* If we are only performing a partial link do not bother
7068 to construct any glue. */
0e1862bb 7069 if (bfd_link_relocatable (link_info))
c7b8f16e
JB		 7070 return TRUE;
7071
0ffa91dd
NC		 7072 /* Skip if this bfd does not correspond to an ELF image. */
7073 if (! is_arm_elf (abfd))
7074 return TRUE;
906e58ca 7075
c7b8f16e
JB		 7076 /* We should have chosen a fix type by the time we get here. */
7077 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
7078
7079 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
7080 return TRUE;
2e6030b9 7081
33a7ffc2
JM		 7082 /* Skip this BFD if it corresponds to an executable or dynamic object. */
7083 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
7084 return TRUE;
7085
c7b8f16e
JB		 7086 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7087 {
7088 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
7089 struct _arm_elf_section_data *sec_data;
7090
7091 /* If we don't have executable progbits, we're not interested in this
99059e56 7092 section. Also skip if section is to be excluded. */
c7b8f16e 7093 if (elf_section_type (sec) != SHT_PROGBITS
99059e56
RM		 7094 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
7095 || (sec->flags & SEC_EXCLUDE) != 0
dbaa2011 7096 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
33a7ffc2 7097 || sec->output_section == bfd_abs_section_ptr
99059e56
RM		 7098 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
7099 continue;
c7b8f16e
JB		 7100
7101 sec_data = elf32_arm_section_data (sec);
906e58ca 7102
c7b8f16e 7103 if (sec_data->mapcount == 0)
99059e56 7104 continue;
906e58ca 7105
c7b8f16e
JB		 7106 if (elf_section_data (sec)->this_hdr.contents != NULL)
7107 contents = elf_section_data (sec)->this_hdr.contents;
7108 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
7109 goto error_return;
7110
7111 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
7112 elf32_arm_compare_mapping);
7113
7114 for (span = 0; span < sec_data->mapcount; span++)
99059e56
RM		 7115 {
7116 unsigned int span_start = sec_data->map[span].vma;
7117 unsigned int span_end = (span == sec_data->mapcount - 1)
c7b8f16e 7118 ? sec->size : sec_data->map[span + 1].vma;
99059e56
RM		 7119 char span_type = sec_data->map[span].type;
7120
7121 /* FIXME: Only ARM mode is supported at present. We may need to
7122 support Thumb-2 mode also at some point. */
7123 if (span_type != 'a')
7124 continue;
7125
7126 for (i = span_start; i < span_end;)
7127 {
7128 unsigned int next_i = i + 4;
7129 unsigned int insn = bfd_big_endian (abfd)
7130 ? (contents[i] << 24)
7131 | (contents[i + 1] << 16)
7132 | (contents[i + 2] << 8)
7133 | contents[i + 3]
7134 : (contents[i + 3] << 24)
7135 | (contents[i + 2] << 16)
7136 | (contents[i + 1] << 8)
7137 | contents[i];
7138 unsigned int writemask = 0;
7139 enum bfd_arm_vfp11_pipe vpipe;
7140
7141 switch (state)
7142 {
7143 case 0:
7144 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
7145 &numregs);
7146 /* I'm assuming the VFP11 erratum can trigger with denorm
7147 operands on either the FMAC or the DS pipeline. This might
7148 lead to slightly overenthusiastic veneer insertion. */
7149 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
7150 {
7151 state = use_vector ? 1 : 2;
7152 first_fmac = i;
7153 veneer_of_insn = insn;
7154 }
7155 break;
7156
7157 case 1:
7158 {
7159 int other_regs[3], other_numregs;
7160 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 7161 other_regs,
99059e56
RM		 7162 &other_numregs);
7163 if (vpipe != VFP11_BAD
7164 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 7165 numregs))
99059e56
RM		 7166 state = 3;
7167 else
7168 state = 2;
7169 }
7170 break;
7171
7172 case 2:
7173 {
7174 int other_regs[3], other_numregs;
7175 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
c7b8f16e 7176 other_regs,
99059e56
RM		 7177 &other_numregs);
7178 if (vpipe != VFP11_BAD
7179 && bfd_arm_vfp11_antidependency (writemask, regs,
c7b8f16e 7180 numregs))
99059e56
RM		 7181 state = 3;
7182 else
7183 {
7184 state = 0;
7185 next_i = first_fmac + 4;
7186 }
7187 }
7188 break;
7189
7190 case 3:
7191 abort (); /* Should be unreachable. */
7192 }
7193
7194 if (state == 3)
7195 {
7196 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
7197 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
7198
7199 elf32_arm_section_data (sec)->erratumcount += 1;
7200
7201 newerr->u.b.vfp_insn = veneer_of_insn;
7202
7203 switch (span_type)
7204 {
7205 case 'a':
7206 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
7207 break;
7208
7209 default:
7210 abort ();
7211 }
7212
7213 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
c7b8f16e
JB		 7214 first_fmac);
7215
99059e56 7216 newerr->vma = -1;
c7b8f16e 7217
99059e56
RM		 7218 newerr->next = sec_data->erratumlist;
7219 sec_data->erratumlist = newerr;
c7b8f16e 7220
99059e56
RM		 7221 state = 0;
7222 }
c7b8f16e 7223
99059e56
RM		 7224 i = next_i;
7225 }
7226 }
906e58ca 7227
c7b8f16e 7228 if (contents != NULL
99059e56
RM		 7229 && elf_section_data (sec)->this_hdr.contents != contents)
7230 free (contents);
c7b8f16e
JB		 7231 contents = NULL;
7232 }
7233
7234 return TRUE;
7235
7236error_return:
7237 if (contents != NULL
7238 && elf_section_data (sec)->this_hdr.contents != contents)
7239 free (contents);
906e58ca 7240
c7b8f16e
JB		 7241 return FALSE;
7242}
7243
7244/* Find virtual-memory addresses for VFP11 erratum veneers and return locations
7245 after sections have been laid out, using specially-named symbols. */
7246
7247void
7248bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
7249 struct bfd_link_info *link_info)
7250{
7251 asection *sec;
7252 struct elf32_arm_link_hash_table *globals;
7253 char *tmp_name;
906e58ca 7254
0e1862bb 7255 if (bfd_link_relocatable (link_info))
c7b8f16e 7256 return;
2e6030b9
MS		 7257
7258 /* Skip if this bfd does not correspond to an ELF image. */
0ffa91dd 7259 if (! is_arm_elf (abfd))
2e6030b9
MS		 7260 return;
7261
c7b8f16e 7262 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7263 if (globals == NULL)
7264 return;
906e58ca 7265
21d799b5 7266 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
99059e56 7267 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
c7b8f16e
JB		 7268
7269 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7270 {
7271 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7272 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
906e58ca 7273
c7b8f16e 7274 for (; errnode != NULL; errnode = errnode->next)
99059e56
RM		 7275 {
7276 struct elf_link_hash_entry *myh;
7277 bfd_vma vma;
7278
7279 switch (errnode->type)
7280 {
7281 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
7282 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
7283 /* Find veneer symbol. */
7284 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
c7b8f16e
JB		 7285 errnode->u.b.veneer->u.v.id);
7286
99059e56
RM		 7287 myh = elf_link_hash_lookup
7288 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
c7b8f16e 7289
a504d23a
LA		 7290 if (myh == NULL)
7291 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
7292 "`%s'"), abfd, tmp_name);
7293
7294 vma = myh->root.u.def.section->output_section->vma
7295 + myh->root.u.def.section->output_offset
7296 + myh->root.u.def.value;
7297
7298 errnode->u.b.veneer->vma = vma;
7299 break;
7300
7301 case VFP11_ERRATUM_ARM_VENEER:
7302 case VFP11_ERRATUM_THUMB_VENEER:
7303 /* Find return location. */
7304 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7305 errnode->u.v.id);
7306
7307 myh = elf_link_hash_lookup
7308 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7309
7310 if (myh == NULL)
7311 (*_bfd_error_handler) (_("%B: unable to find VFP11 veneer "
7312 "`%s'"), abfd, tmp_name);
7313
7314 vma = myh->root.u.def.section->output_section->vma
7315 + myh->root.u.def.section->output_offset
7316 + myh->root.u.def.value;
7317
7318 errnode->u.v.branch->vma = vma;
7319 break;
7320
7321 default:
7322 abort ();
7323 }
7324 }
7325 }
7326
7327 free (tmp_name);
7328}
7329
7330/* Find virtual-memory addresses for STM32L4XX erratum veneers and
7331 return locations after sections have been laid out, using
7332 specially-named symbols. */
7333
7334void
7335bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
7336 struct bfd_link_info *link_info)
7337{
7338 asection *sec;
7339 struct elf32_arm_link_hash_table *globals;
7340 char *tmp_name;
7341
7342 if (bfd_link_relocatable (link_info))
7343 return;
7344
7345 /* Skip if this bfd does not correspond to an ELF image. */
7346 if (! is_arm_elf (abfd))
7347 return;
7348
7349 globals = elf32_arm_hash_table (link_info);
7350 if (globals == NULL)
7351 return;
7352
7353 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7354 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7355
7356 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7357 {
7358 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7359 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
7360
7361 for (; errnode != NULL; errnode = errnode->next)
7362 {
7363 struct elf_link_hash_entry *myh;
7364 bfd_vma vma;
7365
7366 switch (errnode->type)
7367 {
7368 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
7369 /* Find veneer symbol. */
7370 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7371 errnode->u.b.veneer->u.v.id);
7372
7373 myh = elf_link_hash_lookup
7374 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7375
7376 if (myh == NULL)
7377 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
7378 "`%s'"), abfd, tmp_name);
7379
7380 vma = myh->root.u.def.section->output_section->vma
7381 + myh->root.u.def.section->output_offset
7382 + myh->root.u.def.value;
7383
7384 errnode->u.b.veneer->vma = vma;
7385 break;
7386
7387 case STM32L4XX_ERRATUM_VENEER:
7388 /* Find return location. */
7389 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7390 errnode->u.v.id);
7391
7392 myh = elf_link_hash_lookup
7393 (&(globals)->root, tmp_name, FALSE, FALSE, TRUE);
7394
7395 if (myh == NULL)
7396 (*_bfd_error_handler) (_("%B: unable to find STM32L4XX veneer "
7397 "`%s'"), abfd, tmp_name);
7398
7399 vma = myh->root.u.def.section->output_section->vma
7400 + myh->root.u.def.section->output_offset
7401 + myh->root.u.def.value;
7402
7403 errnode->u.v.branch->vma = vma;
7404 break;
7405
7406 default:
7407 abort ();
7408 }
7409 }
7410 }
7411
7412 free (tmp_name);
7413}
7414
7415static inline bfd_boolean
7416is_thumb2_ldmia (const insn32 insn)
7417{
7418 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
7419 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
7420 return (insn & 0xffd02000) == 0xe8900000;
7421}
7422
7423static inline bfd_boolean
7424is_thumb2_ldmdb (const insn32 insn)
7425{
7426 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
7427 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
7428 return (insn & 0xffd02000) == 0xe9100000;
7429}
7430
7431static inline bfd_boolean
7432is_thumb2_vldm (const insn32 insn)
7433{
7434 /* A6.5 Extension register load or store instruction
7435 A7.7.229
7436 We look only for the 32-bit registers case since the DP (64-bit
7437 registers) are not supported for STM32L4XX
7438 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
7439 <list> is consecutive 32-bit registers
7440 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
7441 if P==0 && U==1 && W==1 && Rn=1101 VPOP
7442 if PUW=010 || PUW=011 || PUW=101 VLDM. */
7443 return
7444 ((insn & 0xfe100f00) == 0xec100a00)
7445 && /* (IA without !). */
7446 (((((insn << 7) >> 28) & 0xd) == 0x4)
7447 /* (IA with !), includes VPOP (when reg number is SP). */
7448 || ((((insn << 7) >> 28) & 0xd) == 0x5)
7449 /* (DB with !). */
7450 || ((((insn << 7) >> 28) & 0xd) == 0x9));
7451}
7452
7453/* STM STM32L4XX erratum : This function assumes that it receives an LDM or
7454 VLDM opcode and:
7455 - computes the number and the mode of memory accesses
7456 - decides if the replacement should be done:
7457 . replaces only if > 8-word accesses
7458 . or (testing purposes only) replaces all accesses. */
7459
7460static bfd_boolean
7461stm32l4xx_need_create_replacing_stub (const insn32 insn,
7462 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
7463{
7464 int nb_regs = 0;
7465
7466 /* The field encoding the register list is the same for both LDMIA
7467 and LDMDB encodings. */
7468 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
7469 nb_regs = popcount (insn & 0x0000ffff);
7470 else if (is_thumb2_vldm (insn))
7471 nb_regs = (insn & 0xff);
7472
7473 /* DEFAULT mode accounts for the real bug condition situation,
7474 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
7475 return
7476 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT) ? nb_regs > 8 :
7477 (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL) ? TRUE : FALSE;
7478}
7479
7480/* Look for potentially-troublesome code sequences which might trigger
7481 the STM STM32L4XX erratum. */
7482
7483bfd_boolean
7484bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
7485 struct bfd_link_info *link_info)
7486{
7487 asection *sec;
7488 bfd_byte *contents = NULL;
7489 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
7490
7491 if (globals == NULL)
7492 return FALSE;
7493
7494 /* If we are only performing a partial link do not bother
7495 to construct any glue. */
7496 if (bfd_link_relocatable (link_info))
7497 return TRUE;
7498
7499 /* Skip if this bfd does not correspond to an ELF image. */
7500 if (! is_arm_elf (abfd))
7501 return TRUE;
7502
7503 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
7504 return TRUE;
7505
7506 /* Skip this BFD if it corresponds to an executable or dynamic object. */
7507 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
7508 return TRUE;
7509
7510 for (sec = abfd->sections; sec != NULL; sec = sec->next)
7511 {
7512 unsigned int i, span;
7513 struct _arm_elf_section_data *sec_data;
7514
7515 /* If we don't have executable progbits, we're not interested in this
7516 section. Also skip if section is to be excluded. */
7517 if (elf_section_type (sec) != SHT_PROGBITS
7518 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
7519 || (sec->flags & SEC_EXCLUDE) != 0
7520 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
7521 || sec->output_section == bfd_abs_section_ptr
7522 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
7523 continue;
7524
7525 sec_data = elf32_arm_section_data (sec);
c7b8f16e 7526
a504d23a
LA		 7527 if (sec_data->mapcount == 0)
7528 continue;
c7b8f16e 7529
a504d23a
LA		 7530 if (elf_section_data (sec)->this_hdr.contents != NULL)
7531 contents = elf_section_data (sec)->this_hdr.contents;
7532 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
7533 goto error_return;
c7b8f16e 7534
a504d23a
LA		 7535 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
7536 elf32_arm_compare_mapping);
c7b8f16e 7537
a504d23a
LA		 7538 for (span = 0; span < sec_data->mapcount; span++)
7539 {
7540 unsigned int span_start = sec_data->map[span].vma;
7541 unsigned int span_end = (span == sec_data->mapcount - 1)
7542 ? sec->size : sec_data->map[span + 1].vma;
7543 char span_type = sec_data->map[span].type;
7544 int itblock_current_pos = 0;
c7b8f16e 7545
a504d23a
LA		 7546 /* Only Thumb2 mode need be supported with this CM4 specific
7547 code, we should not encounter any arm mode eg span_type
7548 != 'a'. */
7549 if (span_type != 't')
7550 continue;
c7b8f16e 7551
a504d23a
LA		 7552 for (i = span_start; i < span_end;)
7553 {
7554 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
7555 bfd_boolean insn_32bit = FALSE;
7556 bfd_boolean is_ldm = FALSE;
7557 bfd_boolean is_vldm = FALSE;
7558 bfd_boolean is_not_last_in_it_block = FALSE;
7559
7560 /* The first 16-bits of all 32-bit thumb2 instructions start
7561 with opcode[15..13]=0b111 and the encoded op1 can be anything
7562 except opcode[12..11]!=0b00.
7563 See 32-bit Thumb instruction encoding. */
7564 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
7565 insn_32bit = TRUE;
c7b8f16e 7566
a504d23a
LA		 7567 /* Compute the predicate that tells if the instruction
7568 is concerned by the IT block
7569 - Creates an error if there is a ldm that is not
7570 last in the IT block thus cannot be replaced
7571 - Otherwise we can create a branch at the end of the
7572 IT block, it will be controlled naturally by IT
7573 with the proper pseudo-predicate
7574 - So the only interesting predicate is the one that
7575 tells that we are not on the last item of an IT
7576 block. */
7577 if (itblock_current_pos != 0)
7578 is_not_last_in_it_block = !!--itblock_current_pos;
906e58ca 7579
a504d23a
LA		 7580 if (insn_32bit)
7581 {
7582 /* Load the rest of the insn (in manual-friendly order). */
7583 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
7584 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
7585 is_vldm = is_thumb2_vldm (insn);
7586
7587 /* Veneers are created for (v)ldm depending on
7588 option flags and memory accesses conditions; but
7589 if the instruction is not the last instruction of
7590 an IT block, we cannot create a jump there, so we
7591 bail out. */
7592 if ((is_ldm || is_vldm) &&
7593 stm32l4xx_need_create_replacing_stub
7594 (insn, globals->stm32l4xx_fix))
7595 {
7596 if (is_not_last_in_it_block)
7597 {
7598 (*_bfd_error_handler)
7599 /* Note - overlong line used here to allow for translation. */
7600 (_("\
7601%B(%A+0x%lx): error: multiple load detected in non-last IT block instruction : STM32L4XX veneer cannot be generated.\n"
7602 "Use gcc option -mrestrict-it to generate only one instruction per IT block.\n"),
7603 abfd, sec, (long)i);
7604 }
7605 else
7606 {
7607 elf32_stm32l4xx_erratum_list *newerr =
7608 (elf32_stm32l4xx_erratum_list *)
7609 bfd_zmalloc
7610 (sizeof (elf32_stm32l4xx_erratum_list));
7611
7612 elf32_arm_section_data (sec)
7613 ->stm32l4xx_erratumcount += 1;
7614 newerr->u.b.insn = insn;
7615 /* We create only thumb branches. */
7616 newerr->type =
7617 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
7618 record_stm32l4xx_erratum_veneer
7619 (link_info, newerr, abfd, sec,
7620 i,
7621 is_ldm ?
7622 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
7623 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
7624 newerr->vma = -1;
7625 newerr->next = sec_data->stm32l4xx_erratumlist;
7626 sec_data->stm32l4xx_erratumlist = newerr;
7627 }
7628 }
7629 }
7630 else
7631 {
7632 /* A7.7.37 IT p208
7633 IT blocks are only encoded in T1
7634 Encoding T1: IT{x{y{z}}} <firstcond>
7635 1 0 1 1 - 1 1 1 1 - firstcond - mask
7636 if mask = '0000' then see 'related encodings'
7637 We don't deal with UNPREDICTABLE, just ignore these.
7638 There can be no nested IT blocks so an IT block
7639 is naturally a new one for which it is worth
7640 computing its size. */
7641 bfd_boolean is_newitblock = ((insn & 0xff00) == 0xbf00) &&
7642 ((insn & 0x000f) != 0x0000);
7643 /* If we have a new IT block we compute its size. */
7644 if (is_newitblock)
7645 {
7646 /* Compute the number of instructions controlled
7647 by the IT block, it will be used to decide
7648 whether we are inside an IT block or not. */
7649 unsigned int mask = insn & 0x000f;
7650 itblock_current_pos = 4 - ctz (mask);
7651 }
7652 }
7653
7654 i += insn_32bit ? 4 : 2;
99059e56
RM		 7655 }
7656 }
a504d23a
LA		 7657
7658 if (contents != NULL
7659 && elf_section_data (sec)->this_hdr.contents != contents)
7660 free (contents);
7661 contents = NULL;
c7b8f16e 7662 }
906e58ca 7663
a504d23a
LA		 7664 return TRUE;
7665
7666error_return:
7667 if (contents != NULL
7668 && elf_section_data (sec)->this_hdr.contents != contents)
7669 free (contents);
c7b8f16e 7670
a504d23a
LA		 7671 return FALSE;
7672}
c7b8f16e 7673
eb043451
PB		 7674/* Set target relocation values needed during linking. */
7675
7676void
bf21ed78
MS		 7677bfd_elf32_arm_set_target_relocs (struct bfd *output_bfd,
7678 struct bfd_link_info *link_info,
eb043451 7679 int target1_is_rel,
319850b4 7680 char * target2_type,
99059e56 7681 int fix_v4bx,
c7b8f16e 7682 int use_blx,
99059e56 7683 bfd_arm_vfp11_fix vfp11_fix,
a504d23a 7684 bfd_arm_stm32l4xx_fix stm32l4xx_fix,
a9dc9481 7685 int no_enum_warn, int no_wchar_warn,
2de70689
MGD		 7686 int pic_veneer, int fix_cortex_a8,
7687 int fix_arm1176)
eb043451
PB		 7688{
7689 struct elf32_arm_link_hash_table *globals;
7690
7691 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 7692 if (globals == NULL)
7693 return;
eb043451
PB		 7694
7695 globals->target1_is_rel = target1_is_rel;
7696 if (strcmp (target2_type, "rel") == 0)
7697 globals->target2_reloc = R_ARM_REL32;
eeac373a
PB		 7698 else if (strcmp (target2_type, "abs") == 0)
7699 globals->target2_reloc = R_ARM_ABS32;
eb043451
PB		 7700 else if (strcmp (target2_type, "got-rel") == 0)
7701 globals->target2_reloc = R_ARM_GOT_PREL;
7702 else
7703 {
7704 _bfd_error_handler (_("Invalid TARGET2 relocation type '%s'."),
7705 target2_type);
7706 }
319850b4 7707 globals->fix_v4bx = fix_v4bx;
33bfe774 7708 globals->use_blx |= use_blx;
c7b8f16e 7709 globals->vfp11_fix = vfp11_fix;
a504d23a 7710 globals->stm32l4xx_fix = stm32l4xx_fix;
27e55c4d 7711 globals->pic_veneer = pic_veneer;
48229727 7712 globals->fix_cortex_a8 = fix_cortex_a8;
2de70689 7713 globals->fix_arm1176 = fix_arm1176;
bf21ed78 7714
0ffa91dd
NC		 7715 BFD_ASSERT (is_arm_elf (output_bfd));
7716 elf_arm_tdata (output_bfd)->no_enum_size_warning = no_enum_warn;
a9dc9481 7717 elf_arm_tdata (output_bfd)->no_wchar_size_warning = no_wchar_warn;
eb043451 7718}
eb043451 7719
12a0a0fd 7720/* Replace the target offset of a Thumb bl or b.w instruction. */
252b5132 7721
12a0a0fd
PB		 7722static void
7723insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
7724{
7725 bfd_vma upper;
7726 bfd_vma lower;
7727 int reloc_sign;
7728
7729 BFD_ASSERT ((offset & 1) == 0);
7730
7731 upper = bfd_get_16 (abfd, insn);
7732 lower = bfd_get_16 (abfd, insn + 2);
7733 reloc_sign = (offset < 0) ? 1 : 0;
7734 upper = (upper & ~(bfd_vma) 0x7ff)
7735 | ((offset >> 12) & 0x3ff)
7736 | (reloc_sign << 10);
906e58ca 7737 lower = (lower & ~(bfd_vma) 0x2fff)
12a0a0fd
PB		 7738 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
7739 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
7740 | ((offset >> 1) & 0x7ff);
7741 bfd_put_16 (abfd, upper, insn);
7742 bfd_put_16 (abfd, lower, insn + 2);
252b5132
RH		 7743}
7744
9b485d32
NC		 7745/* Thumb code calling an ARM function. */
7746
252b5132 7747static int
57e8b36a
NC		 7748elf32_thumb_to_arm_stub (struct bfd_link_info * info,
7749 const char * name,
7750 bfd * input_bfd,
7751 bfd * output_bfd,
7752 asection * input_section,
7753 bfd_byte * hit_data,
7754 asection * sym_sec,
7755 bfd_vma offset,
7756 bfd_signed_vma addend,
f2a9dd69
DJ		 7757 bfd_vma val,
7758 char **error_message)
252b5132 7759{
bcbdc74c 7760 asection * s = 0;
dc810e39 7761 bfd_vma my_offset;
252b5132 7762 long int ret_offset;
bcbdc74c
NC		 7763 struct elf_link_hash_entry * myh;
7764 struct elf32_arm_link_hash_table * globals;
252b5132 7765
f2a9dd69 7766 myh = find_thumb_glue (info, name, error_message);
252b5132 7767 if (myh == NULL)
b34976b6 7768 return FALSE;
252b5132
RH		 7769
7770 globals = elf32_arm_hash_table (info);
252b5132
RH		 7771 BFD_ASSERT (globals != NULL);
7772 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7773
7774 my_offset = myh->root.u.def.value;
7775
3d4d4302
AM		 7776 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
7777 THUMB2ARM_GLUE_SECTION_NAME);
252b5132
RH		 7778
7779 BFD_ASSERT (s != NULL);
7780 BFD_ASSERT (s->contents != NULL);
7781 BFD_ASSERT (s->output_section != NULL);
7782
7783 if ((my_offset & 0x01) == 0x01)
7784 {
7785 if (sym_sec != NULL
7786 && sym_sec->owner != NULL
7787 && !INTERWORK_FLAG (sym_sec->owner))
7788 {
8f615d07 7789 (*_bfd_error_handler)
d003868e 7790 (_("%B(%s): warning: interworking not enabled.\n"
3aaeb7d3 7791 " first occurrence: %B: Thumb call to ARM"),
d003868e 7792 sym_sec->owner, input_bfd, name);
252b5132 7793
b34976b6 7794 return FALSE;
252b5132
RH		 7795 }
7796
7797 --my_offset;
7798 myh->root.u.def.value = my_offset;
7799
52ab56c2
PB		 7800 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
7801 s->contents + my_offset);
252b5132 7802
52ab56c2
PB		 7803 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
7804 s->contents + my_offset + 2);
252b5132
RH		 7805
7806 ret_offset =
9b485d32
NC		 7807 /* Address of destination of the stub. */
7808 ((bfd_signed_vma) val)
252b5132 7809 - ((bfd_signed_vma)
57e8b36a
NC		 7810 /* Offset from the start of the current section
7811 to the start of the stubs. */
9b485d32
NC		 7812 (s->output_offset
7813 /* Offset of the start of this stub from the start of the stubs. */
7814 + my_offset
7815 /* Address of the start of the current section. */
7816 + s->output_section->vma)
7817 /* The branch instruction is 4 bytes into the stub. */
7818 + 4
7819 /* ARM branches work from the pc of the instruction + 8. */
7820 + 8);
252b5132 7821
52ab56c2
PB		 7822 put_arm_insn (globals, output_bfd,
7823 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
7824 s->contents + my_offset + 4);
252b5132
RH		 7825 }
7826
7827 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
7828
427bfd90
NC		 7829 /* Now go back and fix up the original BL insn to point to here. */
7830 ret_offset =
7831 /* Address of where the stub is located. */
7832 (s->output_section->vma + s->output_offset + my_offset)
7833 /* Address of where the BL is located. */
57e8b36a
NC		 7834 - (input_section->output_section->vma + input_section->output_offset
7835 + offset)
427bfd90
NC		 7836 /* Addend in the relocation. */
7837 - addend
7838 /* Biassing for PC-relative addressing. */
7839 - 8;
252b5132 7840
12a0a0fd 7841 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
252b5132 7842
b34976b6 7843 return TRUE;
252b5132
RH		 7844}
7845
a4fd1a8e 7846/* Populate an Arm to Thumb stub. Returns the stub symbol. */
9b485d32 7847
a4fd1a8e
PB		 7848static struct elf_link_hash_entry *
7849elf32_arm_create_thumb_stub (struct bfd_link_info * info,
7850 const char * name,
7851 bfd * input_bfd,
7852 bfd * output_bfd,
7853 asection * sym_sec,
7854 bfd_vma val,
8029a119
NC		 7855 asection * s,
7856 char ** error_message)
252b5132 7857{
dc810e39 7858 bfd_vma my_offset;
252b5132 7859 long int ret_offset;
bcbdc74c
NC		 7860 struct elf_link_hash_entry * myh;
7861 struct elf32_arm_link_hash_table * globals;
252b5132 7862
f2a9dd69 7863 myh = find_arm_glue (info, name, error_message);
252b5132 7864 if (myh == NULL)
a4fd1a8e 7865 return NULL;
252b5132
RH		 7866
7867 globals = elf32_arm_hash_table (info);
252b5132
RH		 7868 BFD_ASSERT (globals != NULL);
7869 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7870
7871 my_offset = myh->root.u.def.value;
252b5132
RH		 7872
7873 if ((my_offset & 0x01) == 0x01)
7874 {
7875 if (sym_sec != NULL
7876 && sym_sec->owner != NULL
7877 && !INTERWORK_FLAG (sym_sec->owner))
7878 {
8f615d07 7879 (*_bfd_error_handler)
d003868e
AM		 7880 (_("%B(%s): warning: interworking not enabled.\n"
7881 " first occurrence: %B: arm call to thumb"),
7882 sym_sec->owner, input_bfd, name);
252b5132 7883 }
9b485d32 7884
252b5132
RH		 7885 --my_offset;
7886 myh->root.u.def.value = my_offset;
7887
0e1862bb
L		 7888 if (bfd_link_pic (info)
7889 || globals->root.is_relocatable_executable
27e55c4d 7890 || globals->pic_veneer)
8f6277f5
PB		 7891 {
7892 /* For relocatable objects we can't use absolute addresses,
7893 so construct the address from a relative offset. */
7894 /* TODO: If the offset is small it's probably worth
7895 constructing the address with adds. */
52ab56c2
PB		 7896 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
7897 s->contents + my_offset);
7898 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
7899 s->contents + my_offset + 4);
7900 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
7901 s->contents + my_offset + 8);
8f6277f5
PB		 7902 /* Adjust the offset by 4 for the position of the add,
7903 and 8 for the pipeline offset. */
7904 ret_offset = (val - (s->output_offset
7905 + s->output_section->vma
7906 + my_offset + 12))
7907 | 1;
7908 bfd_put_32 (output_bfd, ret_offset,
7909 s->contents + my_offset + 12);
7910 }
26079076
PB		 7911 else if (globals->use_blx)
7912 {
7913 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
7914 s->contents + my_offset);
7915
7916 /* It's a thumb address. Add the low order bit. */
7917 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
7918 s->contents + my_offset + 4);
7919 }
8f6277f5
PB		 7920 else
7921 {
52ab56c2
PB		 7922 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
7923 s->contents + my_offset);
252b5132 7924
52ab56c2
PB		 7925 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
7926 s->contents + my_offset + 4);
252b5132 7927
8f6277f5
PB		 7928 /* It's a thumb address. Add the low order bit. */
7929 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
7930 s->contents + my_offset + 8);
8029a119
NC		 7931
7932 my_offset += 12;
8f6277f5 7933 }
252b5132
RH		 7934 }
7935
7936 BFD_ASSERT (my_offset <= globals->arm_glue_size);
7937
a4fd1a8e
PB		 7938 return myh;
7939}
7940
7941/* Arm code calling a Thumb function. */
7942
7943static int
7944elf32_arm_to_thumb_stub (struct bfd_link_info * info,
7945 const char * name,
7946 bfd * input_bfd,
7947 bfd * output_bfd,
7948 asection * input_section,
7949 bfd_byte * hit_data,
7950 asection * sym_sec,
7951 bfd_vma offset,
7952 bfd_signed_vma addend,
f2a9dd69
DJ		 7953 bfd_vma val,
7954 char **error_message)
a4fd1a8e
PB		 7955{
7956 unsigned long int tmp;
7957 bfd_vma my_offset;
7958 asection * s;
7959 long int ret_offset;
7960 struct elf_link_hash_entry * myh;
7961 struct elf32_arm_link_hash_table * globals;
7962
7963 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 7964 BFD_ASSERT (globals != NULL);
7965 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7966
3d4d4302
AM		 7967 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
7968 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 7969 BFD_ASSERT (s != NULL);
7970 BFD_ASSERT (s->contents != NULL);
7971 BFD_ASSERT (s->output_section != NULL);
7972
7973 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
f2a9dd69 7974 sym_sec, val, s, error_message);
a4fd1a8e
PB		 7975 if (!myh)
7976 return FALSE;
7977
7978 my_offset = myh->root.u.def.value;
252b5132
RH		 7979 tmp = bfd_get_32 (input_bfd, hit_data);
7980 tmp = tmp & 0xFF000000;
7981
9b485d32 7982 /* Somehow these are both 4 too far, so subtract 8. */
dc810e39
AM		 7983 ret_offset = (s->output_offset
7984 + my_offset
7985 + s->output_section->vma
7986 - (input_section->output_offset
7987 + input_section->output_section->vma
7988 + offset + addend)
7989 - 8);
9a5aca8c 7990
252b5132
RH		 7991 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
7992
dc810e39 7993 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
252b5132 7994
b34976b6 7995 return TRUE;
252b5132
RH		 7996}
7997
a4fd1a8e
PB		 7998/* Populate Arm stub for an exported Thumb function. */
7999
8000static bfd_boolean
8001elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
8002{
8003 struct bfd_link_info * info = (struct bfd_link_info *) inf;
8004 asection * s;
8005 struct elf_link_hash_entry * myh;
8006 struct elf32_arm_link_hash_entry *eh;
8007 struct elf32_arm_link_hash_table * globals;
8008 asection *sec;
8009 bfd_vma val;
f2a9dd69 8010 char *error_message;
a4fd1a8e 8011
906e58ca 8012 eh = elf32_arm_hash_entry (h);
a4fd1a8e
PB		 8013 /* Allocate stubs for exported Thumb functions on v4t. */
8014 if (eh->export_glue == NULL)
8015 return TRUE;
8016
8017 globals = elf32_arm_hash_table (info);
a4fd1a8e
PB		 8018 BFD_ASSERT (globals != NULL);
8019 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8020
3d4d4302
AM		 8021 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8022 ARM2THUMB_GLUE_SECTION_NAME);
a4fd1a8e
PB		 8023 BFD_ASSERT (s != NULL);
8024 BFD_ASSERT (s->contents != NULL);
8025 BFD_ASSERT (s->output_section != NULL);
8026
8027 sec = eh->export_glue->root.u.def.section;
0eaedd0e
PB		 8028
8029 BFD_ASSERT (sec->output_section != NULL);
8030
a4fd1a8e
PB		 8031 val = eh->export_glue->root.u.def.value + sec->output_offset
8032 + sec->output_section->vma;
8029a119 8033
a4fd1a8e
PB		 8034 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
8035 h->root.u.def.section->owner,
f2a9dd69
DJ		 8036 globals->obfd, sec, val, s,
8037 &error_message);
a4fd1a8e
PB		 8038 BFD_ASSERT (myh);
8039 return TRUE;
8040}
8041
845b51d6
PB		 8042/* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
8043
8044static bfd_vma
8045elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
8046{
8047 bfd_byte *p;
8048 bfd_vma glue_addr;
8049 asection *s;
8050 struct elf32_arm_link_hash_table *globals;
8051
8052 globals = elf32_arm_hash_table (info);
845b51d6
PB		 8053 BFD_ASSERT (globals != NULL);
8054 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
8055
3d4d4302
AM		 8056 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
8057 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 8058 BFD_ASSERT (s != NULL);
8059 BFD_ASSERT (s->contents != NULL);
8060 BFD_ASSERT (s->output_section != NULL);
8061
8062 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
8063
8064 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
8065
8066 if ((globals->bx_glue_offset[reg] & 1) == 0)
8067 {
8068 p = s->contents + glue_addr;
8069 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
8070 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
8071 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
8072 globals->bx_glue_offset[reg] |= 1;
8073 }
8074
8075 return glue_addr + s->output_section->vma + s->output_offset;
8076}
8077
a4fd1a8e
PB		 8078/* Generate Arm stubs for exported Thumb symbols. */
8079static void
906e58ca 8080elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
a4fd1a8e
PB		 8081 struct bfd_link_info *link_info)
8082{
8083 struct elf32_arm_link_hash_table * globals;
8084
8029a119
NC		 8085 if (link_info == NULL)
8086 /* Ignore this if we are not called by the ELF backend linker. */
a4fd1a8e
PB		 8087 return;
8088
8089 globals = elf32_arm_hash_table (link_info);
4dfe6ac6
NC		 8090 if (globals == NULL)
8091 return;
8092
84c08195
PB		 8093 /* If blx is available then exported Thumb symbols are OK and there is
8094 nothing to do. */
a4fd1a8e
PB		 8095 if (globals->use_blx)
8096 return;
8097
8098 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
8099 link_info);
8100}
8101
47beaa6a
RS		 8102/* Reserve space for COUNT dynamic relocations in relocation selection
8103 SRELOC. */
8104
8105static void
8106elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
8107 bfd_size_type count)
8108{
8109 struct elf32_arm_link_hash_table *htab;
8110
8111 htab = elf32_arm_hash_table (info);
8112 BFD_ASSERT (htab->root.dynamic_sections_created);
8113 if (sreloc == NULL)
8114 abort ();
8115 sreloc->size += RELOC_SIZE (htab) * count;
8116}
8117
34e77a92
RS		 8118/* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
8119 dynamic, the relocations should go in SRELOC, otherwise they should
8120 go in the special .rel.iplt section. */
8121
8122static void
8123elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
8124 bfd_size_type count)
8125{
8126 struct elf32_arm_link_hash_table *htab;
8127
8128 htab = elf32_arm_hash_table (info);
8129 if (!htab->root.dynamic_sections_created)
8130 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
8131 else
8132 {
8133 BFD_ASSERT (sreloc != NULL);
8134 sreloc->size += RELOC_SIZE (htab) * count;
8135 }
8136}
8137
47beaa6a
RS		 8138/* Add relocation REL to the end of relocation section SRELOC. */
8139
8140static void
8141elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
8142 asection *sreloc, Elf_Internal_Rela *rel)
8143{
8144 bfd_byte *loc;
8145 struct elf32_arm_link_hash_table *htab;
8146
8147 htab = elf32_arm_hash_table (info);
34e77a92
RS		 8148 if (!htab->root.dynamic_sections_created
8149 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
8150 sreloc = htab->root.irelplt;
47beaa6a
RS		 8151 if (sreloc == NULL)
8152 abort ();
8153 loc = sreloc->contents;
8154 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
8155 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
8156 abort ();
8157 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
8158}
8159
34e77a92
RS		 8160/* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
8161 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
8162 to .plt. */
8163
8164static void
8165elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
8166 bfd_boolean is_iplt_entry,
8167 union gotplt_union *root_plt,
8168 struct arm_plt_info *arm_plt)
8169{
8170 struct elf32_arm_link_hash_table *htab;
8171 asection *splt;
8172 asection *sgotplt;
8173
8174 htab = elf32_arm_hash_table (info);
8175
8176 if (is_iplt_entry)
8177 {
8178 splt = htab->root.iplt;
8179 sgotplt = htab->root.igotplt;
8180
99059e56
RM		 8181 /* NaCl uses a special first entry in .iplt too. */
8182 if (htab->nacl_p && splt->size == 0)
8183 splt->size += htab->plt_header_size;
8184
34e77a92
RS		 8185 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
8186 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
8187 }
8188 else
8189 {
8190 splt = htab->root.splt;
8191 sgotplt = htab->root.sgotplt;
8192
8193 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
8194 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
8195
8196 /* If this is the first .plt entry, make room for the special
8197 first entry. */
8198 if (splt->size == 0)
8199 splt->size += htab->plt_header_size;
9f19ab6d
WN		 8200
8201 htab->next_tls_desc_index++;
34e77a92
RS		 8202 }
8203
8204 /* Allocate the PLT entry itself, including any leading Thumb stub. */
8205 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
8206 splt->size += PLT_THUMB_STUB_SIZE;
8207 root_plt->offset = splt->size;
8208 splt->size += htab->plt_entry_size;
8209
8210 if (!htab->symbian_p)
8211 {
8212 /* We also need to make an entry in the .got.plt section, which
8213 will be placed in the .got section by the linker script. */
9f19ab6d
WN		 8214 if (is_iplt_entry)
8215 arm_plt->got_offset = sgotplt->size;
8216 else
8217 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
34e77a92
RS		 8218 sgotplt->size += 4;
8219 }
8220}
8221
b38cadfb
NC		 8222static bfd_vma
8223arm_movw_immediate (bfd_vma value)
8224{
8225 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
8226}
8227
8228static bfd_vma
8229arm_movt_immediate (bfd_vma value)
8230{
8231 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
8232}
8233
34e77a92
RS		 8234/* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
8235 the entry lives in .iplt and resolves to (*SYM_VALUE)().
8236 Otherwise, DYNINDX is the index of the symbol in the dynamic
8237 symbol table and SYM_VALUE is undefined.
8238
8239 ROOT_PLT points to the offset of the PLT entry from the start of its
8240 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
57460bcf 8241 bookkeeping information.
34e77a92 8242
57460bcf
NC		 8243 Returns FALSE if there was a problem. */
8244
8245static bfd_boolean
34e77a92
RS		 8246elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
8247 union gotplt_union *root_plt,
8248 struct arm_plt_info *arm_plt,
8249 int dynindx, bfd_vma sym_value)
8250{
8251 struct elf32_arm_link_hash_table *htab;
8252 asection *sgot;
8253 asection *splt;
8254 asection *srel;
8255 bfd_byte *loc;
8256 bfd_vma plt_index;
8257 Elf_Internal_Rela rel;
8258 bfd_vma plt_header_size;
8259 bfd_vma got_header_size;
8260
8261 htab = elf32_arm_hash_table (info);
8262
8263 /* Pick the appropriate sections and sizes. */
8264 if (dynindx == -1)
8265 {
8266 splt = htab->root.iplt;
8267 sgot = htab->root.igotplt;
8268 srel = htab->root.irelplt;
8269
8270 /* There are no reserved entries in .igot.plt, and no special
8271 first entry in .iplt. */
8272 got_header_size = 0;
8273 plt_header_size = 0;
8274 }
8275 else
8276 {
8277 splt = htab->root.splt;
8278 sgot = htab->root.sgotplt;
8279 srel = htab->root.srelplt;
8280
8281 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
8282 plt_header_size = htab->plt_header_size;
8283 }
8284 BFD_ASSERT (splt != NULL && srel != NULL);
8285
8286 /* Fill in the entry in the procedure linkage table. */
8287 if (htab->symbian_p)
8288 {
8289 BFD_ASSERT (dynindx >= 0);
8290 put_arm_insn (htab, output_bfd,
8291 elf32_arm_symbian_plt_entry[0],
8292 splt->contents + root_plt->offset);
8293 bfd_put_32 (output_bfd,
8294 elf32_arm_symbian_plt_entry[1],
8295 splt->contents + root_plt->offset + 4);
8296
8297 /* Fill in the entry in the .rel.plt section. */
8298 rel.r_offset = (splt->output_section->vma
8299 + splt->output_offset
8300 + root_plt->offset + 4);
8301 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_GLOB_DAT);
8302
8303 /* Get the index in the procedure linkage table which
8304 corresponds to this symbol. This is the index of this symbol
8305 in all the symbols for which we are making plt entries. The
8306 first entry in the procedure linkage table is reserved. */
8307 plt_index = ((root_plt->offset - plt_header_size)
8308 / htab->plt_entry_size);
8309 }
8310 else
8311 {
8312 bfd_vma got_offset, got_address, plt_address;
8313 bfd_vma got_displacement, initial_got_entry;
8314 bfd_byte * ptr;
8315
8316 BFD_ASSERT (sgot != NULL);
8317
8318 /* Get the offset into the .(i)got.plt table of the entry that
8319 corresponds to this function. */
8320 got_offset = (arm_plt->got_offset & -2);
8321
8322 /* Get the index in the procedure linkage table which
8323 corresponds to this symbol. This is the index of this symbol
8324 in all the symbols for which we are making plt entries.
8325 After the reserved .got.plt entries, all symbols appear in
8326 the same order as in .plt. */
8327 plt_index = (got_offset - got_header_size) / 4;
8328
8329 /* Calculate the address of the GOT entry. */
8330 got_address = (sgot->output_section->vma
8331 + sgot->output_offset
8332 + got_offset);
8333
8334 /* ...and the address of the PLT entry. */
8335 plt_address = (splt->output_section->vma
8336 + splt->output_offset
8337 + root_plt->offset);
8338
8339 ptr = splt->contents + root_plt->offset;
0e1862bb 8340 if (htab->vxworks_p && bfd_link_pic (info))
34e77a92
RS		 8341 {
8342 unsigned int i;
8343 bfd_vma val;
8344
8345 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
8346 {
8347 val = elf32_arm_vxworks_shared_plt_entry[i];
8348 if (i == 2)
8349 val |= got_address - sgot->output_section->vma;
8350 if (i == 5)
8351 val |= plt_index * RELOC_SIZE (htab);
8352 if (i == 2 || i == 5)
8353 bfd_put_32 (output_bfd, val, ptr);
8354 else
8355 put_arm_insn (htab, output_bfd, val, ptr);
8356 }
8357 }
8358 else if (htab->vxworks_p)
8359 {
8360 unsigned int i;
8361 bfd_vma val;
8362
8363 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
8364 {
8365 val = elf32_arm_vxworks_exec_plt_entry[i];
8366 if (i == 2)
8367 val |= got_address;
8368 if (i == 4)
8369 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
8370 if (i == 5)
8371 val |= plt_index * RELOC_SIZE (htab);
8372 if (i == 2 || i == 5)
8373 bfd_put_32 (output_bfd, val, ptr);
8374 else
8375 put_arm_insn (htab, output_bfd, val, ptr);
8376 }
8377
8378 loc = (htab->srelplt2->contents
8379 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
8380
8381 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
8382 referencing the GOT for this PLT entry. */
8383 rel.r_offset = plt_address + 8;
8384 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
8385 rel.r_addend = got_offset;
8386 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8387 loc += RELOC_SIZE (htab);
8388
8389 /* Create the R_ARM_ABS32 relocation referencing the
8390 beginning of the PLT for this GOT entry. */
8391 rel.r_offset = got_address;
8392 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
8393 rel.r_addend = 0;
8394 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8395 }
b38cadfb
NC		 8396 else if (htab->nacl_p)
8397 {
8398 /* Calculate the displacement between the PLT slot and the
8399 common tail that's part of the special initial PLT slot. */
6034aab8 8400 int32_t tail_displacement
b38cadfb
NC		 8401 = ((splt->output_section->vma + splt->output_offset
8402 + ARM_NACL_PLT_TAIL_OFFSET)
8403 - (plt_address + htab->plt_entry_size + 4));
8404 BFD_ASSERT ((tail_displacement & 3) == 0);
8405 tail_displacement >>= 2;
8406
8407 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
8408 || (-tail_displacement & 0xff000000) == 0);
8409
8410 /* Calculate the displacement between the PLT slot and the entry
8411 in the GOT. The offset accounts for the value produced by
8412 adding to pc in the penultimate instruction of the PLT stub. */
6034aab8 8413 got_displacement = (got_address
99059e56 8414 - (plt_address + htab->plt_entry_size));
b38cadfb
NC		 8415
8416 /* NaCl does not support interworking at all. */
8417 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
8418
8419 put_arm_insn (htab, output_bfd,
8420 elf32_arm_nacl_plt_entry[0]
8421 | arm_movw_immediate (got_displacement),
8422 ptr + 0);
8423 put_arm_insn (htab, output_bfd,
8424 elf32_arm_nacl_plt_entry[1]
8425 | arm_movt_immediate (got_displacement),
8426 ptr + 4);
8427 put_arm_insn (htab, output_bfd,
8428 elf32_arm_nacl_plt_entry[2],
8429 ptr + 8);
8430 put_arm_insn (htab, output_bfd,
8431 elf32_arm_nacl_plt_entry[3]
8432 | (tail_displacement & 0x00ffffff),
8433 ptr + 12);
8434 }
57460bcf
NC		 8435 else if (using_thumb_only (htab))
8436 {
eed94f8f 8437 /* PR ld/16017: Generate thumb only PLT entries. */
469a3493 8438 if (!using_thumb2 (htab))
eed94f8f
NC		 8439 {
8440 /* FIXME: We ought to be able to generate thumb-1 PLT
8441 instructions... */
8442 _bfd_error_handler (_("%B: Warning: thumb-1 mode PLT generation not currently supported"),
8443 output_bfd);
8444 return FALSE;
8445 }
57460bcf 8446
eed94f8f
NC		 8447 /* Calculate the displacement between the PLT slot and the entry in
8448 the GOT. The 12-byte offset accounts for the value produced by
8449 adding to pc in the 3rd instruction of the PLT stub. */
8450 got_displacement = got_address - (plt_address + 12);
8451
8452 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
8453 instead of 'put_thumb_insn'. */
8454 put_arm_insn (htab, output_bfd,
8455 elf32_thumb2_plt_entry[0]
8456 | ((got_displacement & 0x000000ff) << 16)
8457 | ((got_displacement & 0x00000700) << 20)
8458 | ((got_displacement & 0x00000800) >> 1)
8459 | ((got_displacement & 0x0000f000) >> 12),
8460 ptr + 0);
8461 put_arm_insn (htab, output_bfd,
8462 elf32_thumb2_plt_entry[1]
8463 | ((got_displacement & 0x00ff0000) )
8464 | ((got_displacement & 0x07000000) << 4)
8465 | ((got_displacement & 0x08000000) >> 17)
8466 | ((got_displacement & 0xf0000000) >> 28),
8467 ptr + 4);
8468 put_arm_insn (htab, output_bfd,
8469 elf32_thumb2_plt_entry[2],
8470 ptr + 8);
8471 put_arm_insn (htab, output_bfd,
8472 elf32_thumb2_plt_entry[3],
8473 ptr + 12);
57460bcf 8474 }
34e77a92
RS		 8475 else
8476 {
8477 /* Calculate the displacement between the PLT slot and the
8478 entry in the GOT. The eight-byte offset accounts for the
8479 value produced by adding to pc in the first instruction
8480 of the PLT stub. */
8481 got_displacement = got_address - (plt_address + 8);
8482
34e77a92
RS		 8483 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
8484 {
8485 put_thumb_insn (htab, output_bfd,
8486 elf32_arm_plt_thumb_stub[0], ptr - 4);
8487 put_thumb_insn (htab, output_bfd,
8488 elf32_arm_plt_thumb_stub[1], ptr - 2);
8489 }
8490
1db37fe6
YG		 8491 if (!elf32_arm_use_long_plt_entry)
8492 {
8493 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
8494
8495 put_arm_insn (htab, output_bfd,
8496 elf32_arm_plt_entry_short[0]
8497 | ((got_displacement & 0x0ff00000) >> 20),
8498 ptr + 0);
8499 put_arm_insn (htab, output_bfd,
8500 elf32_arm_plt_entry_short[1]
8501 | ((got_displacement & 0x000ff000) >> 12),
8502 ptr+ 4);
8503 put_arm_insn (htab, output_bfd,
8504 elf32_arm_plt_entry_short[2]
8505 | (got_displacement & 0x00000fff),
8506 ptr + 8);
34e77a92 8507#ifdef FOUR_WORD_PLT
1db37fe6 8508 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
34e77a92 8509#endif
1db37fe6
YG		 8510 }
8511 else
8512 {
8513 put_arm_insn (htab, output_bfd,
8514 elf32_arm_plt_entry_long[0]
8515 | ((got_displacement & 0xf0000000) >> 28),
8516 ptr + 0);
8517 put_arm_insn (htab, output_bfd,
8518 elf32_arm_plt_entry_long[1]
8519 | ((got_displacement & 0x0ff00000) >> 20),
8520 ptr + 4);
8521 put_arm_insn (htab, output_bfd,
8522 elf32_arm_plt_entry_long[2]
8523 | ((got_displacement & 0x000ff000) >> 12),
8524 ptr+ 8);
8525 put_arm_insn (htab, output_bfd,
8526 elf32_arm_plt_entry_long[3]
8527 | (got_displacement & 0x00000fff),
8528 ptr + 12);
8529 }
34e77a92
RS		 8530 }
8531
8532 /* Fill in the entry in the .rel(a).(i)plt section. */
8533 rel.r_offset = got_address;
8534 rel.r_addend = 0;
8535 if (dynindx == -1)
8536 {
8537 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
8538 The dynamic linker or static executable then calls SYM_VALUE
8539 to determine the correct run-time value of the .igot.plt entry. */
8540 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
8541 initial_got_entry = sym_value;
8542 }
8543 else
8544 {
8545 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
8546 initial_got_entry = (splt->output_section->vma
8547 + splt->output_offset);
8548 }
8549
8550 /* Fill in the entry in the global offset table. */
8551 bfd_put_32 (output_bfd, initial_got_entry,
8552 sgot->contents + got_offset);
8553 }
8554
aba8c3de
WN		 8555 if (dynindx == -1)
8556 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
8557 else
8558 {
8559 loc = srel->contents + plt_index * RELOC_SIZE (htab);
8560 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
8561 }
57460bcf
NC		 8562
8563 return TRUE;
34e77a92
RS		 8564}
8565
eb043451
PB		 8566/* Some relocations map to different relocations depending on the
8567 target. Return the real relocation. */
8029a119 8568
eb043451
PB		 8569static int
8570arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
8571 int r_type)
8572{
8573 switch (r_type)
8574 {
8575 case R_ARM_TARGET1:
8576 if (globals->target1_is_rel)
8577 return R_ARM_REL32;
8578 else
8579 return R_ARM_ABS32;
8580
8581 case R_ARM_TARGET2:
8582 return globals->target2_reloc;
8583
8584 default:
8585 return r_type;
8586 }
8587}
eb043451 8588
ba93b8ac
DJ		 8589/* Return the base VMA address which should be subtracted from real addresses
8590 when resolving @dtpoff relocation.
8591 This is PT_TLS segment p_vaddr. */
8592
8593static bfd_vma
8594dtpoff_base (struct bfd_link_info *info)
8595{
8596 /* If tls_sec is NULL, we should have signalled an error already. */
8597 if (elf_hash_table (info)->tls_sec == NULL)
8598 return 0;
8599 return elf_hash_table (info)->tls_sec->vma;
8600}
8601
8602/* Return the relocation value for @tpoff relocation
8603 if STT_TLS virtual address is ADDRESS. */
8604
8605static bfd_vma
8606tpoff (struct bfd_link_info *info, bfd_vma address)
8607{
8608 struct elf_link_hash_table *htab = elf_hash_table (info);
8609 bfd_vma base;
8610
8611 /* If tls_sec is NULL, we should have signalled an error already. */
8612 if (htab->tls_sec == NULL)
8613 return 0;
8614 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
8615 return address - htab->tls_sec->vma + base;
8616}
8617
00a97672
RS		 8618/* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
8619 VALUE is the relocation value. */
8620
8621static bfd_reloc_status_type
8622elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
8623{
8624 if (value > 0xfff)
8625 return bfd_reloc_overflow;
8626
8627 value |= bfd_get_32 (abfd, data) & 0xfffff000;
8628 bfd_put_32 (abfd, value, data);
8629 return bfd_reloc_ok;
8630}
8631
0855e32b
NS		 8632/* Handle TLS relaxations. Relaxing is possible for symbols that use
8633 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
8634 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
8635
8636 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
8637 is to then call final_link_relocate. Return other values in the
62672b10
NS		 8638 case of error.
8639
8640 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
8641 the pre-relaxed code. It would be nice if the relocs were updated
8642 to match the optimization. */
0855e32b 8643
b38cadfb 8644static bfd_reloc_status_type
0855e32b 8645elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
b38cadfb 8646 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
0855e32b
NS		 8647 Elf_Internal_Rela *rel, unsigned long is_local)
8648{
8649 unsigned long insn;
b38cadfb 8650
0855e32b
NS		 8651 switch (ELF32_R_TYPE (rel->r_info))
8652 {
8653 default:
8654 return bfd_reloc_notsupported;
b38cadfb 8655
0855e32b
NS		 8656 case R_ARM_TLS_GOTDESC:
8657 if (is_local)
8658 insn = 0;
8659 else
8660 {
8661 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
8662 if (insn & 1)
8663 insn -= 5; /* THUMB */
8664 else
8665 insn -= 8; /* ARM */
8666 }
8667 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
8668 return bfd_reloc_continue;
8669
8670 case R_ARM_THM_TLS_DESCSEQ:
8671 /* Thumb insn. */
8672 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
8673 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
8674 {
8675 if (is_local)
8676 /* nop */
8677 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8678 }
8679 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
8680 {
8681 if (is_local)
8682 /* nop */
8683 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8684 else
8685 /* ldr rx,[ry] */
8686 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
8687 }
8688 else if ((insn & 0xff87) == 0x4780) /* blx rx */
8689 {
8690 if (is_local)
8691 /* nop */
8692 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
8693 else
8694 /* mov r0, rx */
8695 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
8696 contents + rel->r_offset);
8697 }
8698 else
8699 {
8700 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
8701 /* It's a 32 bit instruction, fetch the rest of it for
8702 error generation. */
8703 insn = (insn << 16)
8704 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
8705 (*_bfd_error_handler)
8706 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' in TLS trampoline"),
8707 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
8708 return bfd_reloc_notsupported;
8709 }
8710 break;
b38cadfb 8711
0855e32b
NS		 8712 case R_ARM_TLS_DESCSEQ:
8713 /* arm insn. */
8714 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
8715 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
8716 {
8717 if (is_local)
8718 /* mov rx, ry */
8719 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
8720 contents + rel->r_offset);
8721 }
8722 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
8723 {
8724 if (is_local)
8725 /* nop */
8726 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
8727 else
8728 /* ldr rx,[ry] */
8729 bfd_put_32 (input_bfd, insn & 0xfffff000,
8730 contents + rel->r_offset);
8731 }
8732 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
8733 {
8734 if (is_local)
8735 /* nop */
8736 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
8737 else
8738 /* mov r0, rx */
8739 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
8740 contents + rel->r_offset);
8741 }
8742 else
8743 {
8744 (*_bfd_error_handler)
8745 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' in TLS trampoline"),
8746 input_bfd, input_sec, (unsigned long)rel->r_offset, insn);
8747 return bfd_reloc_notsupported;
8748 }
8749 break;
8750
8751 case R_ARM_TLS_CALL:
8752 /* GD->IE relaxation, turn the instruction into 'nop' or
8753 'ldr r0, [pc,r0]' */
8754 insn = is_local ? 0xe1a00000 : 0xe79f0000;
8755 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
8756 break;
b38cadfb 8757
0855e32b 8758 case R_ARM_THM_TLS_CALL:
6a631e86 8759 /* GD->IE relaxation. */
0855e32b
NS		 8760 if (!is_local)
8761 /* add r0,pc; ldr r0, [r0] */
8762 insn = 0x44786800;
8763 else if (arch_has_thumb2_nop (globals))
8764 /* nop.w */
8765 insn = 0xf3af8000;
8766 else
8767 /* nop; nop */
8768 insn = 0xbf00bf00;
b38cadfb 8769
0855e32b
NS		 8770 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
8771 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
8772 break;
8773 }
8774 return bfd_reloc_ok;
8775}
8776
4962c51a
MS		 8777/* For a given value of n, calculate the value of G_n as required to
8778 deal with group relocations. We return it in the form of an
8779 encoded constant-and-rotation, together with the final residual. If n is
8780 specified as less than zero, then final_residual is filled with the
8781 input value and no further action is performed. */
8782
8783static bfd_vma
8784calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
8785{
8786 int current_n;
8787 bfd_vma g_n;
8788 bfd_vma encoded_g_n = 0;
8789 bfd_vma residual = value; /* Also known as Y_n. */
8790
8791 for (current_n = 0; current_n <= n; current_n++)
8792 {
8793 int shift;
8794
8795 /* Calculate which part of the value to mask. */
8796 if (residual == 0)
99059e56 8797 shift = 0;
4962c51a 8798 else
99059e56
RM		 8799 {
8800 int msb;
8801
8802 /* Determine the most significant bit in the residual and
8803 align the resulting value to a 2-bit boundary. */
8804 for (msb = 30; msb >= 0; msb -= 2)
8805 if (residual & (3 << msb))
8806 break;
8807
8808 /* The desired shift is now (msb - 6), or zero, whichever
8809 is the greater. */
8810 shift = msb - 6;
8811 if (shift < 0)
8812 shift = 0;
8813 }
4962c51a
MS		 8814
8815 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
8816 g_n = residual & (0xff << shift);
8817 encoded_g_n = (g_n >> shift)
99059e56 8818 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
4962c51a
MS		 8819
8820 /* Calculate the residual for the next time around. */
8821 residual &= ~g_n;
8822 }
8823
8824 *final_residual = residual;
8825
8826 return encoded_g_n;
8827}
8828
8829/* Given an ARM instruction, determine whether it is an ADD or a SUB.
8830 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
906e58ca 8831
4962c51a 8832static int
906e58ca 8833identify_add_or_sub (bfd_vma insn)
4962c51a
MS		 8834{
8835 int opcode = insn & 0x1e00000;
8836
8837 if (opcode == 1 << 23) /* ADD */
8838 return 1;
8839
8840 if (opcode == 1 << 22) /* SUB */
8841 return -1;
8842
8843 return 0;
8844}
8845
252b5132 8846/* Perform a relocation as part of a final link. */
9b485d32 8847
252b5132 8848static bfd_reloc_status_type
57e8b36a
NC		 8849elf32_arm_final_link_relocate (reloc_howto_type * howto,
8850 bfd * input_bfd,
8851 bfd * output_bfd,
8852 asection * input_section,
8853 bfd_byte * contents,
8854 Elf_Internal_Rela * rel,
8855 bfd_vma value,
8856 struct bfd_link_info * info,
8857 asection * sym_sec,
8858 const char * sym_name,
34e77a92
RS		 8859 unsigned char st_type,
8860 enum arm_st_branch_type branch_type,
0945cdfd 8861 struct elf_link_hash_entry * h,
f2a9dd69 8862 bfd_boolean * unresolved_reloc_p,
8029a119 8863 char ** error_message)
252b5132
RH		 8864{
8865 unsigned long r_type = howto->type;
8866 unsigned long r_symndx;
8867 bfd_byte * hit_data = contents + rel->r_offset;
252b5132 8868 bfd_vma * local_got_offsets;
0855e32b 8869 bfd_vma * local_tlsdesc_gotents;
34e77a92
RS		 8870 asection * sgot;
8871 asection * splt;
252b5132 8872 asection * sreloc = NULL;
362d30a1 8873 asection * srelgot;
252b5132 8874 bfd_vma addend;
ba96a88f 8875 bfd_signed_vma signed_addend;
34e77a92
RS		 8876 unsigned char dynreloc_st_type;
8877 bfd_vma dynreloc_value;
ba96a88f 8878 struct elf32_arm_link_hash_table * globals;
34e77a92
RS		 8879 struct elf32_arm_link_hash_entry *eh;
8880 union gotplt_union *root_plt;
8881 struct arm_plt_info *arm_plt;
8882 bfd_vma plt_offset;
8883 bfd_vma gotplt_offset;
8884 bfd_boolean has_iplt_entry;
f21f3fe0 8885
9c504268 8886 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 8887 if (globals == NULL)
8888 return bfd_reloc_notsupported;
9c504268 8889
0ffa91dd
NC		 8890 BFD_ASSERT (is_arm_elf (input_bfd));
8891
8892 /* Some relocation types map to different relocations depending on the
9c504268 8893 target. We pick the right one here. */
eb043451 8894 r_type = arm_real_reloc_type (globals, r_type);
0855e32b
NS		 8895
8896 /* It is possible to have linker relaxations on some TLS access
8897 models. Update our information here. */
8898 r_type = elf32_arm_tls_transition (info, r_type, h);
8899
eb043451
PB		 8900 if (r_type != howto->type)
8901 howto = elf32_arm_howto_from_type (r_type);
9c504268 8902
34e77a92 8903 eh = (struct elf32_arm_link_hash_entry *) h;
362d30a1 8904 sgot = globals->root.sgot;
252b5132 8905 local_got_offsets = elf_local_got_offsets (input_bfd);
0855e32b
NS		 8906 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
8907
34e77a92
RS		 8908 if (globals->root.dynamic_sections_created)
8909 srelgot = globals->root.srelgot;
8910 else
8911 srelgot = NULL;
8912
252b5132
RH		 8913 r_symndx = ELF32_R_SYM (rel->r_info);
8914
4e7fd91e 8915 if (globals->use_rel)
ba96a88f 8916 {
4e7fd91e
PB		 8917 addend = bfd_get_32 (input_bfd, hit_data) & howto->src_mask;
8918
8919 if (addend & ((howto->src_mask + 1) >> 1))
8920 {
8921 signed_addend = -1;
8922 signed_addend &= ~ howto->src_mask;
8923 signed_addend |= addend;
8924 }
8925 else
8926 signed_addend = addend;
ba96a88f
NC		 8927 }
8928 else
4e7fd91e 8929 addend = signed_addend = rel->r_addend;
f21f3fe0 8930
39f21624
NC		 8931 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
8932 are resolving a function call relocation. */
8933 if (using_thumb_only (globals)
8934 && (r_type == R_ARM_THM_CALL
8935 || r_type == R_ARM_THM_JUMP24)
8936 && branch_type == ST_BRANCH_TO_ARM)
8937 branch_type = ST_BRANCH_TO_THUMB;
8938
34e77a92
RS		 8939 /* Record the symbol information that should be used in dynamic
8940 relocations. */
8941 dynreloc_st_type = st_type;
8942 dynreloc_value = value;
8943 if (branch_type == ST_BRANCH_TO_THUMB)
8944 dynreloc_value |= 1;
8945
8946 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
8947 VALUE appropriately for relocations that we resolve at link time. */
8948 has_iplt_entry = FALSE;
8949 if (elf32_arm_get_plt_info (input_bfd, eh, r_symndx, &root_plt, &arm_plt)
8950 && root_plt->offset != (bfd_vma) -1)
8951 {
8952 plt_offset = root_plt->offset;
8953 gotplt_offset = arm_plt->got_offset;
8954
8955 if (h == NULL || eh->is_iplt)
8956 {
8957 has_iplt_entry = TRUE;
8958 splt = globals->root.iplt;
8959
8960 /* Populate .iplt entries here, because not all of them will
8961 be seen by finish_dynamic_symbol. The lower bit is set if
8962 we have already populated the entry. */
8963 if (plt_offset & 1)
8964 plt_offset--;
8965 else
8966 {
57460bcf
NC		 8967 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
8968 -1, dynreloc_value))
8969 root_plt->offset |= 1;
8970 else
8971 return bfd_reloc_notsupported;
34e77a92
RS		 8972 }
8973
8974 /* Static relocations always resolve to the .iplt entry. */
8975 st_type = STT_FUNC;
8976 value = (splt->output_section->vma
8977 + splt->output_offset
8978 + plt_offset);
8979 branch_type = ST_BRANCH_TO_ARM;
8980
8981 /* If there are non-call relocations that resolve to the .iplt
8982 entry, then all dynamic ones must too. */
8983 if (arm_plt->noncall_refcount != 0)
8984 {
8985 dynreloc_st_type = st_type;
8986 dynreloc_value = value;
8987 }
8988 }
8989 else
8990 /* We populate the .plt entry in finish_dynamic_symbol. */
8991 splt = globals->root.splt;
8992 }
8993 else
8994 {
8995 splt = NULL;
8996 plt_offset = (bfd_vma) -1;
8997 gotplt_offset = (bfd_vma) -1;
8998 }
8999
252b5132
RH		 9000 switch (r_type)
9001 {
9002 case R_ARM_NONE:
28a094c2
DJ		 9003 /* We don't need to find a value for this symbol. It's just a
9004 marker. */
9005 *unresolved_reloc_p = FALSE;
252b5132
RH		 9006 return bfd_reloc_ok;
9007
00a97672
RS		 9008 case R_ARM_ABS12:
9009 if (!globals->vxworks_p)
9010 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
9011
252b5132
RH		 9012 case R_ARM_PC24:
9013 case R_ARM_ABS32:
bb224fc3 9014 case R_ARM_ABS32_NOI:
252b5132 9015 case R_ARM_REL32:
bb224fc3 9016 case R_ARM_REL32_NOI:
5b5bb741
PB		 9017 case R_ARM_CALL:
9018 case R_ARM_JUMP24:
dfc5f959 9019 case R_ARM_XPC25:
eb043451 9020 case R_ARM_PREL31:
7359ea65 9021 case R_ARM_PLT32:
7359ea65
DJ		 9022 /* Handle relocations which should use the PLT entry. ABS32/REL32
9023 will use the symbol's value, which may point to a PLT entry, but we
9024 don't need to handle that here. If we created a PLT entry, all
5fa9e92f
CL		 9025 branches in this object should go to it, except if the PLT is too
9026 far away, in which case a long branch stub should be inserted. */
bb224fc3 9027 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
99059e56 9028 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
155d87d7
CL		 9029 && r_type != R_ARM_CALL
9030 && r_type != R_ARM_JUMP24
9031 && r_type != R_ARM_PLT32)
34e77a92 9032 && plt_offset != (bfd_vma) -1)
7359ea65 9033 {
34e77a92
RS		 9034 /* If we've created a .plt section, and assigned a PLT entry
9035 to this function, it must either be a STT_GNU_IFUNC reference
9036 or not be known to bind locally. In other cases, we should
9037 have cleared the PLT entry by now. */
9038 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
7359ea65
DJ		 9039
9040 value = (splt->output_section->vma
9041 + splt->output_offset
34e77a92 9042 + plt_offset);
0945cdfd 9043 *unresolved_reloc_p = FALSE;
7359ea65
DJ		 9044 return _bfd_final_link_relocate (howto, input_bfd, input_section,
9045 contents, rel->r_offset, value,
00a97672 9046 rel->r_addend);
7359ea65
DJ		 9047 }
9048
67687978
PB		 9049 /* When generating a shared object or relocatable executable, these
9050 relocations are copied into the output file to be resolved at
9051 run time. */
0e1862bb
L		 9052 if ((bfd_link_pic (info)
9053 || globals->root.is_relocatable_executable)
7359ea65 9054 && (input_section->flags & SEC_ALLOC)
4dfe6ac6 9055 && !(globals->vxworks_p
3348747a
NS		 9056 && strcmp (input_section->output_section->name,
9057 ".tls_vars") == 0)
bb224fc3 9058 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
ee06dc07 9059 || !SYMBOL_CALLS_LOCAL (info, h))
ca6b5f82
AM		 9060 && !(input_bfd == globals->stub_bfd
9061 && strstr (input_section->name, STUB_SUFFIX))
7359ea65
DJ		 9062 && (h == NULL
9063 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
9064 || h->root.type != bfd_link_hash_undefweak)
9065 && r_type != R_ARM_PC24
5b5bb741
PB		 9066 && r_type != R_ARM_CALL
9067 && r_type != R_ARM_JUMP24
ee06dc07 9068 && r_type != R_ARM_PREL31
7359ea65 9069 && r_type != R_ARM_PLT32)
252b5132 9070 {
947216bf 9071 Elf_Internal_Rela outrel;
b34976b6 9072 bfd_boolean skip, relocate;
f21f3fe0 9073
52db4ec2
JW		 9074 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
9075 && !h->def_regular)
9076 {
9077 char *v = _("shared object");
9078
0e1862bb 9079 if (bfd_link_executable (info))
52db4ec2
JW		 9080 v = _("PIE executable");
9081
9082 (*_bfd_error_handler)
9083 (_("%B: relocation %s against external or undefined symbol `%s'"
9084 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
9085 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
9086 return bfd_reloc_notsupported;
9087 }
9088
0945cdfd
DJ		 9089 *unresolved_reloc_p = FALSE;
9090
34e77a92 9091 if (sreloc == NULL && globals->root.dynamic_sections_created)
252b5132 9092 {
83bac4b0
NC		 9093 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
9094 ! globals->use_rel);
f21f3fe0 9095
83bac4b0 9096 if (sreloc == NULL)
252b5132 9097 return bfd_reloc_notsupported;
252b5132 9098 }
f21f3fe0 9099
b34976b6
AM		 9100 skip = FALSE;
9101 relocate = FALSE;
f21f3fe0 9102
00a97672 9103 outrel.r_addend = addend;
c629eae0
JJ		 9104 outrel.r_offset =
9105 _bfd_elf_section_offset (output_bfd, info, input_section,
9106 rel->r_offset);
9107 if (outrel.r_offset == (bfd_vma) -1)
b34976b6 9108 skip = TRUE;
0bb2d96a 9109 else if (outrel.r_offset == (bfd_vma) -2)
b34976b6 9110 skip = TRUE, relocate = TRUE;
252b5132
RH		 9111 outrel.r_offset += (input_section->output_section->vma
9112 + input_section->output_offset);
f21f3fe0 9113
252b5132 9114 if (skip)
0bb2d96a 9115 memset (&outrel, 0, sizeof outrel);
5e681ec4
PB		 9116 else if (h != NULL
9117 && h->dynindx != -1
0e1862bb 9118 && (!bfd_link_pic (info)
a496fbc8 9119 || !SYMBOLIC_BIND (info, h)
f5385ebf 9120 || !h->def_regular))
5e681ec4 9121 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
252b5132
RH		 9122 else
9123 {
a16385dc
MM		 9124 int symbol;
9125
5e681ec4 9126 /* This symbol is local, or marked to become local. */
34e77a92 9127 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI);
a16385dc 9128 if (globals->symbian_p)
6366ff1e 9129 {
74541ad4
AM		 9130 asection *osec;
9131
6366ff1e
MM		 9132 /* On Symbian OS, the data segment and text segement
9133 can be relocated independently. Therefore, we
9134 must indicate the segment to which this
9135 relocation is relative. The BPABI allows us to
9136 use any symbol in the right segment; we just use
9137 the section symbol as it is convenient. (We
9138 cannot use the symbol given by "h" directly as it
74541ad4
AM		 9139 will not appear in the dynamic symbol table.)
9140
9141 Note that the dynamic linker ignores the section
9142 symbol value, so we don't subtract osec->vma
9143 from the emitted reloc addend. */
10dbd1f3 9144 if (sym_sec)
74541ad4 9145 osec = sym_sec->output_section;
10dbd1f3 9146 else
74541ad4
AM		 9147 osec = input_section->output_section;
9148 symbol = elf_section_data (osec)->dynindx;
9149 if (symbol == 0)
9150 {
9151 struct elf_link_hash_table *htab = elf_hash_table (info);
9152
9153 if ((osec->flags & SEC_READONLY) == 0
9154 && htab->data_index_section != NULL)
9155 osec = htab->data_index_section;
9156 else
9157 osec = htab->text_index_section;
9158 symbol = elf_section_data (osec)->dynindx;
9159 }
6366ff1e
MM		 9160 BFD_ASSERT (symbol != 0);
9161 }
a16385dc
MM		 9162 else
9163 /* On SVR4-ish systems, the dynamic loader cannot
9164 relocate the text and data segments independently,
9165 so the symbol does not matter. */
9166 symbol = 0;
34e77a92
RS		 9167 if (dynreloc_st_type == STT_GNU_IFUNC)
9168 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
9169 to the .iplt entry. Instead, every non-call reference
9170 must use an R_ARM_IRELATIVE relocation to obtain the
9171 correct run-time address. */
9172 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
9173 else
9174 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
00a97672
RS		 9175 if (globals->use_rel)
9176 relocate = TRUE;
9177 else
34e77a92 9178 outrel.r_addend += dynreloc_value;
252b5132 9179 }
f21f3fe0 9180
47beaa6a 9181 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
9a5aca8c 9182
f21f3fe0 9183 /* If this reloc is against an external symbol, we do not want to
252b5132 9184 fiddle with the addend. Otherwise, we need to include the symbol
9b485d32 9185 value so that it becomes an addend for the dynamic reloc. */
252b5132
RH		 9186 if (! relocate)
9187 return bfd_reloc_ok;
9a5aca8c 9188
f21f3fe0 9189 return _bfd_final_link_relocate (howto, input_bfd, input_section,
34e77a92
RS		 9190 contents, rel->r_offset,
9191 dynreloc_value, (bfd_vma) 0);
252b5132
RH		 9192 }
9193 else switch (r_type)
9194 {
00a97672
RS		 9195 case R_ARM_ABS12:
9196 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
9197
dfc5f959 9198 case R_ARM_XPC25: /* Arm BLX instruction. */
5b5bb741
PB		 9199 case R_ARM_CALL:
9200 case R_ARM_JUMP24:
8029a119 9201 case R_ARM_PC24: /* Arm B/BL instruction. */
7359ea65 9202 case R_ARM_PLT32:
906e58ca 9203 {
906e58ca
NC		 9204 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
9205
dfc5f959 9206 if (r_type == R_ARM_XPC25)
252b5132 9207 {
dfc5f959
NC		 9208 /* Check for Arm calling Arm function. */
9209 /* FIXME: Should we translate the instruction into a BL
9210 instruction instead ? */
35fc36a8 9211 if (branch_type != ST_BRANCH_TO_THUMB)
d003868e
AM		 9212 (*_bfd_error_handler)
9213 (_("\%B: Warning: Arm BLX instruction targets Arm function '%s'."),
9214 input_bfd,
9215 h ? h->root.root.string : "(local)");
dfc5f959 9216 }
155d87d7 9217 else if (r_type == R_ARM_PC24)
dfc5f959
NC		 9218 {
9219 /* Check for Arm calling Thumb function. */
35fc36a8 9220 if (branch_type == ST_BRANCH_TO_THUMB)
dfc5f959 9221 {
f2a9dd69
DJ		 9222 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
9223 output_bfd, input_section,
9224 hit_data, sym_sec, rel->r_offset,
9225 signed_addend, value,
9226 error_message))
9227 return bfd_reloc_ok;
9228 else
9229 return bfd_reloc_dangerous;
dfc5f959 9230 }
252b5132 9231 }
ba96a88f 9232
906e58ca 9233 /* Check if a stub has to be inserted because the
8029a119 9234 destination is too far or we are changing mode. */
155d87d7
CL		 9235 if ( r_type == R_ARM_CALL
9236 || r_type == R_ARM_JUMP24
9237 || r_type == R_ARM_PLT32)
906e58ca 9238 {
fe33d2fa
CL		 9239 enum elf32_arm_stub_type stub_type = arm_stub_none;
9240 struct elf32_arm_link_hash_entry *hash;
9241
9242 hash = (struct elf32_arm_link_hash_entry *) h;
9243 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 9244 st_type, &branch_type,
9245 hash, value, sym_sec,
fe33d2fa 9246 input_bfd, sym_name);
5fa9e92f 9247
fe33d2fa 9248 if (stub_type != arm_stub_none)
906e58ca
NC		 9249 {
9250 /* The target is out of reach, so redirect the
9251 branch to the local stub for this function. */
906e58ca
NC		 9252 stub_entry = elf32_arm_get_stub_entry (input_section,
9253 sym_sec, h,
fe33d2fa
CL		 9254 rel, globals,
9255 stub_type);
9cd3e4e5
NC		 9256 {
9257 if (stub_entry != NULL)
9258 value = (stub_entry->stub_offset
9259 + stub_entry->stub_sec->output_offset
9260 + stub_entry->stub_sec->output_section->vma);
9261
9262 if (plt_offset != (bfd_vma) -1)
9263 *unresolved_reloc_p = FALSE;
9264 }
906e58ca 9265 }
fe33d2fa
CL		 9266 else
9267 {
9268 /* If the call goes through a PLT entry, make sure to
9269 check distance to the right destination address. */
34e77a92 9270 if (plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 9271 {
9272 value = (splt->output_section->vma
9273 + splt->output_offset
34e77a92 9274 + plt_offset);
fe33d2fa
CL		 9275 *unresolved_reloc_p = FALSE;
9276 /* The PLT entry is in ARM mode, regardless of the
9277 target function. */
35fc36a8 9278 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 9279 }
9280 }
906e58ca
NC		 9281 }
9282
dea514f5
PB		 9283 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
9284 where:
9285 S is the address of the symbol in the relocation.
9286 P is address of the instruction being relocated.
9287 A is the addend (extracted from the instruction) in bytes.
9288
9289 S is held in 'value'.
9290 P is the base address of the section containing the
9291 instruction plus the offset of the reloc into that
9292 section, ie:
9293 (input_section->output_section->vma +
9294 input_section->output_offset +
9295 rel->r_offset).
9296 A is the addend, converted into bytes, ie:
9297 (signed_addend * 4)
9298
9299 Note: None of these operations have knowledge of the pipeline
9300 size of the processor, thus it is up to the assembler to
9301 encode this information into the addend. */
9302 value -= (input_section->output_section->vma
9303 + input_section->output_offset);
9304 value -= rel->r_offset;
4e7fd91e
PB		 9305 if (globals->use_rel)
9306 value += (signed_addend << howto->size);
9307 else
9308 /* RELA addends do not have to be adjusted by howto->size. */
9309 value += signed_addend;
23080146 9310
dcb5e6e6
NC		 9311 signed_addend = value;
9312 signed_addend >>= howto->rightshift;
9a5aca8c 9313
5ab79981 9314 /* A branch to an undefined weak symbol is turned into a jump to
ffcb4889 9315 the next instruction unless a PLT entry will be created.
77b4f08f 9316 Do the same for local undefined symbols (but not for STN_UNDEF).
cd1dac3d
DG		 9317 The jump to the next instruction is optimized as a NOP depending
9318 on the architecture. */
ffcb4889 9319 if (h ? (h->root.type == bfd_link_hash_undefweak
34e77a92 9320 && plt_offset == (bfd_vma) -1)
77b4f08f 9321 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
5ab79981 9322 {
cd1dac3d
DG		 9323 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
9324
9325 if (arch_has_arm_nop (globals))
9326 value |= 0x0320f000;
9327 else
9328 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
5ab79981
PB		 9329 }
9330 else
59f2c4e7 9331 {
9b485d32 9332 /* Perform a signed range check. */
dcb5e6e6 9333 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
59f2c4e7
NC		 9334 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
9335 return bfd_reloc_overflow;
9a5aca8c 9336
5ab79981 9337 addend = (value & 2);
39b41c9c 9338
5ab79981
PB		 9339 value = (signed_addend & howto->dst_mask)
9340 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
39b41c9c 9341
5ab79981
PB		 9342 if (r_type == R_ARM_CALL)
9343 {
155d87d7 9344 /* Set the H bit in the BLX instruction. */
35fc36a8 9345 if (branch_type == ST_BRANCH_TO_THUMB)
155d87d7
CL		 9346 {
9347 if (addend)
9348 value |= (1 << 24);
9349 else
9350 value &= ~(bfd_vma)(1 << 24);
9351 }
9352
5ab79981 9353 /* Select the correct instruction (BL or BLX). */
906e58ca 9354 /* Only if we are not handling a BL to a stub. In this
8029a119 9355 case, mode switching is performed by the stub. */
35fc36a8 9356 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
5ab79981 9357 value |= (1 << 28);
63e1a0fc 9358 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
5ab79981
PB		 9359 {
9360 value &= ~(bfd_vma)(1 << 28);
9361 value |= (1 << 24);
9362 }
39b41c9c
PB		 9363 }
9364 }
906e58ca 9365 }
252b5132 9366 break;
f21f3fe0 9367
252b5132
RH		 9368 case R_ARM_ABS32:
9369 value += addend;
35fc36a8 9370 if (branch_type == ST_BRANCH_TO_THUMB)
252b5132
RH		 9371 value |= 1;
9372 break;
f21f3fe0 9373
bb224fc3
MS		 9374 case R_ARM_ABS32_NOI:
9375 value += addend;
9376 break;
9377
252b5132 9378 case R_ARM_REL32:
a8bc6c78 9379 value += addend;
35fc36a8 9380 if (branch_type == ST_BRANCH_TO_THUMB)
a8bc6c78 9381 value |= 1;
252b5132 9382 value -= (input_section->output_section->vma
62efb346 9383 + input_section->output_offset + rel->r_offset);
252b5132 9384 break;
eb043451 9385
bb224fc3
MS		 9386 case R_ARM_REL32_NOI:
9387 value += addend;
9388 value -= (input_section->output_section->vma
9389 + input_section->output_offset + rel->r_offset);
9390 break;
9391
eb043451
PB		 9392 case R_ARM_PREL31:
9393 value -= (input_section->output_section->vma
9394 + input_section->output_offset + rel->r_offset);
9395 value += signed_addend;
9396 if (! h || h->root.type != bfd_link_hash_undefweak)
9397 {
8029a119 9398 /* Check for overflow. */
eb043451
PB		 9399 if ((value ^ (value >> 1)) & (1 << 30))
9400 return bfd_reloc_overflow;
9401 }
9402 value &= 0x7fffffff;
9403 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
35fc36a8 9404 if (branch_type == ST_BRANCH_TO_THUMB)
eb043451
PB		 9405 value |= 1;
9406 break;
252b5132 9407 }
f21f3fe0 9408
252b5132
RH		 9409 bfd_put_32 (input_bfd, value, hit_data);
9410 return bfd_reloc_ok;
9411
9412 case R_ARM_ABS8:
fd0fd00c
MJ		 9413 /* PR 16202: Refectch the addend using the correct size. */
9414 if (globals->use_rel)
9415 addend = bfd_get_8 (input_bfd, hit_data);
252b5132 9416 value += addend;
4e67d4ca
DG		 9417
9418 /* There is no way to tell whether the user intended to use a signed or
9419 unsigned addend. When checking for overflow we accept either,
9420 as specified by the AAELF. */
9421 if ((long) value > 0xff || (long) value < -0x80)
252b5132
RH		 9422 return bfd_reloc_overflow;
9423
9424 bfd_put_8 (input_bfd, value, hit_data);
9425 return bfd_reloc_ok;
9426
9427 case R_ARM_ABS16:
fd0fd00c
MJ		 9428 /* PR 16202: Refectch the addend using the correct size. */
9429 if (globals->use_rel)
9430 addend = bfd_get_16 (input_bfd, hit_data);
252b5132
RH		 9431 value += addend;
9432
4e67d4ca
DG		 9433 /* See comment for R_ARM_ABS8. */
9434 if ((long) value > 0xffff || (long) value < -0x8000)
252b5132
RH		 9435 return bfd_reloc_overflow;
9436
9437 bfd_put_16 (input_bfd, value, hit_data);
9438 return bfd_reloc_ok;
9439
252b5132 9440 case R_ARM_THM_ABS5:
9b485d32 9441 /* Support ldr and str instructions for the thumb. */
4e7fd91e
PB		 9442 if (globals->use_rel)
9443 {
9444 /* Need to refetch addend. */
9445 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
9446 /* ??? Need to determine shift amount from operand size. */
9447 addend >>= howto->rightshift;
9448 }
252b5132
RH		 9449 value += addend;
9450
9451 /* ??? Isn't value unsigned? */
9452 if ((long) value > 0x1f || (long) value < -0x10)
9453 return bfd_reloc_overflow;
9454
9455 /* ??? Value needs to be properly shifted into place first. */
9456 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
9457 bfd_put_16 (input_bfd, value, hit_data);
9458 return bfd_reloc_ok;
9459
2cab6cc3
MS		 9460 case R_ARM_THM_ALU_PREL_11_0:
9461 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
9462 {
9463 bfd_vma insn;
9464 bfd_signed_vma relocation;
9465
9466 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 9467 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 9468
99059e56
RM		 9469 if (globals->use_rel)
9470 {
9471 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
9472 | ((insn & (1 << 26)) >> 15);
9473 if (insn & 0xf00000)
9474 signed_addend = -signed_addend;
9475 }
2cab6cc3
MS		 9476
9477 relocation = value + signed_addend;
79f08007 9478 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9479 + input_section->output_offset
9480 + rel->r_offset);
2cab6cc3 9481
b6518b38 9482 value = relocation;
2cab6cc3 9483
99059e56
RM		 9484 if (value >= 0x1000)
9485 return bfd_reloc_overflow;
2cab6cc3
MS		 9486
9487 insn = (insn & 0xfb0f8f00) | (value & 0xff)
99059e56
RM		 9488 | ((value & 0x700) << 4)
9489 | ((value & 0x800) << 15);
9490 if (relocation < 0)
9491 insn |= 0xa00000;
2cab6cc3
MS		 9492
9493 bfd_put_16 (input_bfd, insn >> 16, hit_data);
9494 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
9495
99059e56 9496 return bfd_reloc_ok;
2cab6cc3
MS		 9497 }
9498
e1ec24c6
NC		 9499 case R_ARM_THM_PC8:
9500 /* PR 10073: This reloc is not generated by the GNU toolchain,
9501 but it is supported for compatibility with third party libraries
9502 generated by other compilers, specifically the ARM/IAR. */
9503 {
9504 bfd_vma insn;
9505 bfd_signed_vma relocation;
9506
9507 insn = bfd_get_16 (input_bfd, hit_data);
9508
99059e56 9509 if (globals->use_rel)
79f08007 9510 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
e1ec24c6
NC		 9511
9512 relocation = value + addend;
79f08007 9513 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9514 + input_section->output_offset
9515 + rel->r_offset);
e1ec24c6 9516
b6518b38 9517 value = relocation;
e1ec24c6
NC		 9518
9519 /* We do not check for overflow of this reloc. Although strictly
9520 speaking this is incorrect, it appears to be necessary in order
9521 to work with IAR generated relocs. Since GCC and GAS do not
9522 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
9523 a problem for them. */
9524 value &= 0x3fc;
9525
9526 insn = (insn & 0xff00) | (value >> 2);
9527
9528 bfd_put_16 (input_bfd, insn, hit_data);
9529
99059e56 9530 return bfd_reloc_ok;
e1ec24c6
NC		 9531 }
9532
2cab6cc3
MS		 9533 case R_ARM_THM_PC12:
9534 /* Corresponds to: ldr.w reg, [pc, #offset]. */
9535 {
9536 bfd_vma insn;
9537 bfd_signed_vma relocation;
9538
9539 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
99059e56 9540 | bfd_get_16 (input_bfd, hit_data + 2);
2cab6cc3 9541
99059e56
RM		 9542 if (globals->use_rel)
9543 {
9544 signed_addend = insn & 0xfff;
9545 if (!(insn & (1 << 23)))
9546 signed_addend = -signed_addend;
9547 }
2cab6cc3
MS		 9548
9549 relocation = value + signed_addend;
79f08007 9550 relocation -= Pa (input_section->output_section->vma
99059e56
RM		 9551 + input_section->output_offset
9552 + rel->r_offset);
2cab6cc3 9553
b6518b38 9554 value = relocation;
2cab6cc3 9555
99059e56
RM		 9556 if (value >= 0x1000)
9557 return bfd_reloc_overflow;
2cab6cc3
MS		 9558
9559 insn = (insn & 0xff7ff000) | value;
99059e56
RM		 9560 if (relocation >= 0)
9561 insn |= (1 << 23);
2cab6cc3
MS		 9562
9563 bfd_put_16 (input_bfd, insn >> 16, hit_data);
9564 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
9565
99059e56 9566 return bfd_reloc_ok;
2cab6cc3
MS		 9567 }
9568
dfc5f959 9569 case R_ARM_THM_XPC22:
c19d1205 9570 case R_ARM_THM_CALL:
bd97cb95 9571 case R_ARM_THM_JUMP24:
dfc5f959 9572 /* Thumb BL (branch long instruction). */
252b5132 9573 {
b34976b6 9574 bfd_vma relocation;
99059e56 9575 bfd_vma reloc_sign;
b34976b6
AM		 9576 bfd_boolean overflow = FALSE;
9577 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
9578 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
e95de063
MS		 9579 bfd_signed_vma reloc_signed_max;
9580 bfd_signed_vma reloc_signed_min;
b34976b6 9581 bfd_vma check;
252b5132 9582 bfd_signed_vma signed_check;
e95de063 9583 int bitsize;
cd1dac3d 9584 const int thumb2 = using_thumb2 (globals);
252b5132 9585
5ab79981 9586 /* A branch to an undefined weak symbol is turned into a jump to
cd1dac3d
DG		 9587 the next instruction unless a PLT entry will be created.
9588 The jump to the next instruction is optimized as a NOP.W for
9589 Thumb-2 enabled architectures. */
19540007 9590 if (h && h->root.type == bfd_link_hash_undefweak
34e77a92 9591 && plt_offset == (bfd_vma) -1)
5ab79981 9592 {
cd1dac3d
DG		 9593 if (arch_has_thumb2_nop (globals))
9594 {
9595 bfd_put_16 (input_bfd, 0xf3af, hit_data);
9596 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
9597 }
9598 else
9599 {
9600 bfd_put_16 (input_bfd, 0xe000, hit_data);
9601 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
9602 }
5ab79981
PB		 9603 return bfd_reloc_ok;
9604 }
9605
e95de063 9606 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
99059e56 9607 with Thumb-1) involving the J1 and J2 bits. */
4e7fd91e
PB		 9608 if (globals->use_rel)
9609 {
99059e56
RM		 9610 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
9611 bfd_vma upper = upper_insn & 0x3ff;
9612 bfd_vma lower = lower_insn & 0x7ff;
e95de063
MS		 9613 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
9614 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
99059e56
RM		 9615 bfd_vma i1 = j1 ^ s ? 0 : 1;
9616 bfd_vma i2 = j2 ^ s ? 0 : 1;
e95de063 9617
99059e56
RM		 9618 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
9619 /* Sign extend. */
9620 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
e95de063 9621
4e7fd91e
PB		 9622 signed_addend = addend;
9623 }
cb1afa5c 9624
dfc5f959
NC		 9625 if (r_type == R_ARM_THM_XPC22)
9626 {
9627 /* Check for Thumb to Thumb call. */
9628 /* FIXME: Should we translate the instruction into a BL
9629 instruction instead ? */
35fc36a8 9630 if (branch_type == ST_BRANCH_TO_THUMB)
d003868e
AM		 9631 (*_bfd_error_handler)
9632 (_("%B: Warning: Thumb BLX instruction targets thumb function '%s'."),
9633 input_bfd,
9634 h ? h->root.root.string : "(local)");
dfc5f959
NC		 9635 }
9636 else
252b5132 9637 {
dfc5f959
NC		 9638 /* If it is not a call to Thumb, assume call to Arm.
9639 If it is a call relative to a section name, then it is not a
b7693d02
DJ		 9640 function call at all, but rather a long jump. Calls through
9641 the PLT do not require stubs. */
34e77a92 9642 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
dfc5f959 9643 {
bd97cb95 9644 if (globals->use_blx && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 9645 {
9646 /* Convert BL to BLX. */
9647 lower_insn = (lower_insn & ~0x1000) | 0x0800;
9648 }
155d87d7
CL		 9649 else if (( r_type != R_ARM_THM_CALL)
9650 && (r_type != R_ARM_THM_JUMP24))
8029a119
NC		 9651 {
9652 if (elf32_thumb_to_arm_stub
9653 (info, sym_name, input_bfd, output_bfd, input_section,
9654 hit_data, sym_sec, rel->r_offset, signed_addend, value,
9655 error_message))
9656 return bfd_reloc_ok;
9657 else
9658 return bfd_reloc_dangerous;
9659 }
da5938a2 9660 }
35fc36a8
RS		 9661 else if (branch_type == ST_BRANCH_TO_THUMB
9662 && globals->use_blx
bd97cb95 9663 && r_type == R_ARM_THM_CALL)
39b41c9c
PB		 9664 {
9665 /* Make sure this is a BL. */
9666 lower_insn |= 0x1800;
9667 }
252b5132 9668 }
f21f3fe0 9669
fe33d2fa 9670 enum elf32_arm_stub_type stub_type = arm_stub_none;
155d87d7 9671 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
906e58ca
NC		 9672 {
9673 /* Check if a stub has to be inserted because the destination
8029a119 9674 is too far. */
fe33d2fa
CL		 9675 struct elf32_arm_stub_hash_entry *stub_entry;
9676 struct elf32_arm_link_hash_entry *hash;
9677
9678 hash = (struct elf32_arm_link_hash_entry *) h;
9679
9680 stub_type = arm_type_of_stub (info, input_section, rel,
34e77a92
RS		 9681 st_type, &branch_type,
9682 hash, value, sym_sec,
fe33d2fa
CL		 9683 input_bfd, sym_name);
9684
9685 if (stub_type != arm_stub_none)
906e58ca
NC		 9686 {
9687 /* The target is out of reach or we are changing modes, so
9688 redirect the branch to the local stub for this
9689 function. */
9690 stub_entry = elf32_arm_get_stub_entry (input_section,
9691 sym_sec, h,
fe33d2fa
CL		 9692 rel, globals,
9693 stub_type);
906e58ca 9694 if (stub_entry != NULL)
9cd3e4e5
NC		 9695 {
9696 value = (stub_entry->stub_offset
9697 + stub_entry->stub_sec->output_offset
9698 + stub_entry->stub_sec->output_section->vma);
9699
9700 if (plt_offset != (bfd_vma) -1)
9701 *unresolved_reloc_p = FALSE;
9702 }
906e58ca 9703
f4ac8484 9704 /* If this call becomes a call to Arm, force BLX. */
155d87d7 9705 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
f4ac8484
DJ		 9706 {
9707 if ((stub_entry
9708 && !arm_stub_is_thumb (stub_entry->stub_type))
35fc36a8 9709 || branch_type != ST_BRANCH_TO_THUMB)
f4ac8484
DJ		 9710 lower_insn = (lower_insn & ~0x1000) | 0x0800;
9711 }
906e58ca
NC		 9712 }
9713 }
9714
fe33d2fa 9715 /* Handle calls via the PLT. */
34e77a92 9716 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
fe33d2fa
CL		 9717 {
9718 value = (splt->output_section->vma
9719 + splt->output_offset
34e77a92 9720 + plt_offset);
fe33d2fa 9721
eed94f8f
NC		 9722 if (globals->use_blx
9723 && r_type == R_ARM_THM_CALL
9724 && ! using_thumb_only (globals))
fe33d2fa
CL		 9725 {
9726 /* If the Thumb BLX instruction is available, convert
9727 the BL to a BLX instruction to call the ARM-mode
9728 PLT entry. */
9729 lower_insn = (lower_insn & ~0x1000) | 0x0800;
35fc36a8 9730 branch_type = ST_BRANCH_TO_ARM;
fe33d2fa
CL		 9731 }
9732 else
9733 {
eed94f8f
NC		 9734 if (! using_thumb_only (globals))
9735 /* Target the Thumb stub before the ARM PLT entry. */
9736 value -= PLT_THUMB_STUB_SIZE;
35fc36a8 9737 branch_type = ST_BRANCH_TO_THUMB;
fe33d2fa
CL		 9738 }
9739 *unresolved_reloc_p = FALSE;
9740 }
9741
ba96a88f 9742 relocation = value + signed_addend;
f21f3fe0 9743
252b5132 9744 relocation -= (input_section->output_section->vma
ba96a88f
NC		 9745 + input_section->output_offset
9746 + rel->r_offset);
9a5aca8c 9747
252b5132
RH		 9748 check = relocation >> howto->rightshift;
9749
9750 /* If this is a signed value, the rightshift just dropped
9751 leading 1 bits (assuming twos complement). */
9752 if ((bfd_signed_vma) relocation >= 0)
9753 signed_check = check;
9754 else
9755 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
9756
e95de063
MS		 9757 /* Calculate the permissable maximum and minimum values for
9758 this relocation according to whether we're relocating for
9759 Thumb-2 or not. */
9760 bitsize = howto->bitsize;
9761 if (!thumb2)
9762 bitsize -= 2;
f6ebfac0 9763 reloc_signed_max = (1 << (bitsize - 1)) - 1;
e95de063
MS		 9764 reloc_signed_min = ~reloc_signed_max;
9765
252b5132 9766 /* Assumes two's complement. */
ba96a88f 9767 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
b34976b6 9768 overflow = TRUE;
252b5132 9769
bd97cb95 9770 if ((lower_insn & 0x5000) == 0x4000)
c62e1cc3
NC		 9771 /* For a BLX instruction, make sure that the relocation is rounded up
9772 to a word boundary. This follows the semantics of the instruction
9773 which specifies that bit 1 of the target address will come from bit
9774 1 of the base address. */
9775 relocation = (relocation + 2) & ~ 3;
cb1afa5c 9776
e95de063
MS		 9777 /* Put RELOCATION back into the insn. Assumes two's complement.
9778 We use the Thumb-2 encoding, which is safe even if dealing with
9779 a Thumb-1 instruction by virtue of our overflow check above. */
99059e56 9780 reloc_sign = (signed_check < 0) ? 1 : 0;
e95de063 9781 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
99059e56
RM		 9782 | ((relocation >> 12) & 0x3ff)
9783 | (reloc_sign << 10);
906e58ca 9784 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
99059e56
RM		 9785 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
9786 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
9787 | ((relocation >> 1) & 0x7ff);
c62e1cc3 9788
252b5132
RH		 9789 /* Put the relocated value back in the object file: */
9790 bfd_put_16 (input_bfd, upper_insn, hit_data);
9791 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
9792
9793 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
9794 }
9795 break;
9796
c19d1205
ZW		 9797 case R_ARM_THM_JUMP19:
9798 /* Thumb32 conditional branch instruction. */
9799 {
9800 bfd_vma relocation;
9801 bfd_boolean overflow = FALSE;
9802 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
9803 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
a00a1f35
MS		 9804 bfd_signed_vma reloc_signed_max = 0xffffe;
9805 bfd_signed_vma reloc_signed_min = -0x100000;
c19d1205 9806 bfd_signed_vma signed_check;
c5423981
TG		 9807 enum elf32_arm_stub_type stub_type = arm_stub_none;
9808 struct elf32_arm_stub_hash_entry *stub_entry;
9809 struct elf32_arm_link_hash_entry *hash;
c19d1205
ZW		 9810
9811 /* Need to refetch the addend, reconstruct the top three bits,
9812 and squish the two 11 bit pieces together. */
9813 if (globals->use_rel)
9814 {
9815 bfd_vma S = (upper_insn & 0x0400) >> 10;
a00a1f35 9816 bfd_vma upper = (upper_insn & 0x003f);
c19d1205
ZW		 9817 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
9818 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
9819 bfd_vma lower = (lower_insn & 0x07ff);
9820
a00a1f35
MS		 9821 upper |= J1 << 6;
9822 upper |= J2 << 7;
9823 upper |= (!S) << 8;
c19d1205
ZW		 9824 upper -= 0x0100; /* Sign extend. */
9825
9826 addend = (upper << 12) | (lower << 1);
9827 signed_addend = addend;
9828 }
9829
bd97cb95 9830 /* Handle calls via the PLT. */
34e77a92 9831 if (plt_offset != (bfd_vma) -1)
bd97cb95
DJ		 9832 {
9833 value = (splt->output_section->vma
9834 + splt->output_offset
34e77a92 9835 + plt_offset);
bd97cb95
DJ		 9836 /* Target the Thumb stub before the ARM PLT entry. */
9837 value -= PLT_THUMB_STUB_SIZE;
9838 *unresolved_reloc_p = FALSE;
9839 }
9840
c5423981
TG		 9841 hash = (struct elf32_arm_link_hash_entry *)h;
9842
9843 stub_type = arm_type_of_stub (info, input_section, rel,
9844 st_type, &branch_type,
9845 hash, value, sym_sec,
9846 input_bfd, sym_name);
9847 if (stub_type != arm_stub_none)
9848 {
9849 stub_entry = elf32_arm_get_stub_entry (input_section,
9850 sym_sec, h,
9851 rel, globals,
9852 stub_type);
9853 if (stub_entry != NULL)
9854 {
9855 value = (stub_entry->stub_offset
9856 + stub_entry->stub_sec->output_offset
9857 + stub_entry->stub_sec->output_section->vma);
9858 }
9859 }
c19d1205 9860
99059e56 9861 relocation = value + signed_addend;
c19d1205
ZW		 9862 relocation -= (input_section->output_section->vma
9863 + input_section->output_offset
9864 + rel->r_offset);
a00a1f35 9865 signed_check = (bfd_signed_vma) relocation;
c19d1205 9866
c19d1205
ZW		 9867 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
9868 overflow = TRUE;
9869
9870 /* Put RELOCATION back into the insn. */
9871 {
9872 bfd_vma S = (relocation & 0x00100000) >> 20;
9873 bfd_vma J2 = (relocation & 0x00080000) >> 19;
9874 bfd_vma J1 = (relocation & 0x00040000) >> 18;
9875 bfd_vma hi = (relocation & 0x0003f000) >> 12;
9876 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
9877
a00a1f35 9878 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
c19d1205
ZW		 9879 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
9880 }
9881
9882 /* Put the relocated value back in the object file: */
9883 bfd_put_16 (input_bfd, upper_insn, hit_data);
9884 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
9885
9886 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
9887 }
9888
9889 case R_ARM_THM_JUMP11:
9890 case R_ARM_THM_JUMP8:
9891 case R_ARM_THM_JUMP6:
51c5503b
NC		 9892 /* Thumb B (branch) instruction). */
9893 {
6cf9e9fe 9894 bfd_signed_vma relocation;
51c5503b
NC		 9895 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
9896 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
51c5503b
NC		 9897 bfd_signed_vma signed_check;
9898
c19d1205
ZW		 9899 /* CZB cannot jump backward. */
9900 if (r_type == R_ARM_THM_JUMP6)
9901 reloc_signed_min = 0;
9902
4e7fd91e 9903 if (globals->use_rel)
6cf9e9fe 9904 {
4e7fd91e
PB		 9905 /* Need to refetch addend. */
9906 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
9907 if (addend & ((howto->src_mask + 1) >> 1))
9908 {
9909 signed_addend = -1;
9910 signed_addend &= ~ howto->src_mask;
9911 signed_addend |= addend;
9912 }
9913 else
9914 signed_addend = addend;
9915 /* The value in the insn has been right shifted. We need to
9916 undo this, so that we can perform the address calculation
9917 in terms of bytes. */
9918 signed_addend <<= howto->rightshift;
6cf9e9fe 9919 }
6cf9e9fe 9920 relocation = value + signed_addend;
51c5503b
NC		 9921
9922 relocation -= (input_section->output_section->vma
9923 + input_section->output_offset
9924 + rel->r_offset);
9925
6cf9e9fe
NC		 9926 relocation >>= howto->rightshift;
9927 signed_check = relocation;
c19d1205
ZW		 9928
9929 if (r_type == R_ARM_THM_JUMP6)
9930 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
9931 else
9932 relocation &= howto->dst_mask;
51c5503b 9933 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
cedb70c5 9934
51c5503b
NC		 9935 bfd_put_16 (input_bfd, relocation, hit_data);
9936
9937 /* Assumes two's complement. */
9938 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
9939 return bfd_reloc_overflow;
9940
9941 return bfd_reloc_ok;
9942 }
cedb70c5 9943
8375c36b
PB		 9944 case R_ARM_ALU_PCREL7_0:
9945 case R_ARM_ALU_PCREL15_8:
9946 case R_ARM_ALU_PCREL23_15:
9947 {
9948 bfd_vma insn;
9949 bfd_vma relocation;
9950
9951 insn = bfd_get_32 (input_bfd, hit_data);
4e7fd91e
PB		 9952 if (globals->use_rel)
9953 {
9954 /* Extract the addend. */
9955 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
9956 signed_addend = addend;
9957 }
8375c36b
PB		 9958 relocation = value + signed_addend;
9959
9960 relocation -= (input_section->output_section->vma
9961 + input_section->output_offset
9962 + rel->r_offset);
9963 insn = (insn & ~0xfff)
9964 | ((howto->bitpos << 7) & 0xf00)
9965 | ((relocation >> howto->bitpos) & 0xff);
9966 bfd_put_32 (input_bfd, value, hit_data);
9967 }
9968 return bfd_reloc_ok;
9969
252b5132
RH		 9970 case R_ARM_GNU_VTINHERIT:
9971 case R_ARM_GNU_VTENTRY:
9972 return bfd_reloc_ok;
9973
c19d1205 9974 case R_ARM_GOTOFF32:
252b5132 9975 /* Relocation is relative to the start of the
99059e56 9976 global offset table. */
252b5132
RH		 9977
9978 BFD_ASSERT (sgot != NULL);
9979 if (sgot == NULL)
99059e56 9980 return bfd_reloc_notsupported;
9a5aca8c 9981
cedb70c5 9982 /* If we are addressing a Thumb function, we need to adjust the
ee29b9fb
RE		 9983 address by one, so that attempts to call the function pointer will
9984 correctly interpret it as Thumb code. */
35fc36a8 9985 if (branch_type == ST_BRANCH_TO_THUMB)
ee29b9fb
RE		 9986 value += 1;
9987
252b5132 9988 /* Note that sgot->output_offset is not involved in this
99059e56
RM		 9989 calculation. We always want the start of .got. If we
9990 define _GLOBAL_OFFSET_TABLE in a different way, as is
9991 permitted by the ABI, we might have to change this
9992 calculation. */
252b5132 9993 value -= sgot->output_section->vma;
f21f3fe0 9994 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 9995 contents, rel->r_offset, value,
00a97672 9996 rel->r_addend);
252b5132
RH		 9997
9998 case R_ARM_GOTPC:
a7c10850 9999 /* Use global offset table as symbol value. */
252b5132 10000 BFD_ASSERT (sgot != NULL);
f21f3fe0 10001
252b5132 10002 if (sgot == NULL)
99059e56 10003 return bfd_reloc_notsupported;
252b5132 10004
0945cdfd 10005 *unresolved_reloc_p = FALSE;
252b5132 10006 value = sgot->output_section->vma;
f21f3fe0 10007 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10008 contents, rel->r_offset, value,
00a97672 10009 rel->r_addend);
f21f3fe0 10010
252b5132 10011 case R_ARM_GOT32:
eb043451 10012 case R_ARM_GOT_PREL:
252b5132 10013 /* Relocation is to the entry for this symbol in the
99059e56 10014 global offset table. */
252b5132
RH		 10015 if (sgot == NULL)
10016 return bfd_reloc_notsupported;
f21f3fe0 10017
34e77a92
RS		 10018 if (dynreloc_st_type == STT_GNU_IFUNC
10019 && plt_offset != (bfd_vma) -1
10020 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
10021 {
10022 /* We have a relocation against a locally-binding STT_GNU_IFUNC
10023 symbol, and the relocation resolves directly to the runtime
10024 target rather than to the .iplt entry. This means that any
10025 .got entry would be the same value as the .igot.plt entry,
10026 so there's no point creating both. */
10027 sgot = globals->root.igotplt;
10028 value = sgot->output_offset + gotplt_offset;
10029 }
10030 else if (h != NULL)
252b5132
RH		 10031 {
10032 bfd_vma off;
f21f3fe0 10033
252b5132
RH		 10034 off = h->got.offset;
10035 BFD_ASSERT (off != (bfd_vma) -1);
b436d854 10036 if ((off & 1) != 0)
252b5132 10037 {
b436d854
RS		 10038 /* We have already processsed one GOT relocation against
10039 this symbol. */
10040 off &= ~1;
10041 if (globals->root.dynamic_sections_created
10042 && !SYMBOL_REFERENCES_LOCAL (info, h))
10043 *unresolved_reloc_p = FALSE;
10044 }
10045 else
10046 {
10047 Elf_Internal_Rela outrel;
10048
6f820c85 10049 if (h->dynindx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 10050 {
10051 /* If the symbol doesn't resolve locally in a static
10052 object, we have an undefined reference. If the
10053 symbol doesn't resolve locally in a dynamic object,
10054 it should be resolved by the dynamic linker. */
10055 if (globals->root.dynamic_sections_created)
10056 {
10057 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
10058 *unresolved_reloc_p = FALSE;
10059 }
10060 else
10061 outrel.r_info = 0;
10062 outrel.r_addend = 0;
10063 }
252b5132
RH		 10064 else
10065 {
34e77a92 10066 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 10067 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
0e1862bb 10068 else if (bfd_link_pic (info) &&
31943882
WN		 10069 (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10070 || h->root.type != bfd_link_hash_undefweak))
99059e56
RM		 10071 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
10072 else
10073 outrel.r_info = 0;
34e77a92 10074 outrel.r_addend = dynreloc_value;
b436d854 10075 }
ee29b9fb 10076
b436d854
RS		 10077 /* The GOT entry is initialized to zero by default.
10078 See if we should install a different value. */
10079 if (outrel.r_addend != 0
10080 && (outrel.r_info == 0 || globals->use_rel))
10081 {
10082 bfd_put_32 (output_bfd, outrel.r_addend,
10083 sgot->contents + off);
10084 outrel.r_addend = 0;
252b5132 10085 }
f21f3fe0 10086
b436d854
RS		 10087 if (outrel.r_info != 0)
10088 {
10089 outrel.r_offset = (sgot->output_section->vma
10090 + sgot->output_offset
10091 + off);
10092 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
10093 }
10094 h->got.offset |= 1;
10095 }
252b5132
RH		 10096 value = sgot->output_offset + off;
10097 }
10098 else
10099 {
10100 bfd_vma off;
f21f3fe0 10101
252b5132
RH		 10102 BFD_ASSERT (local_got_offsets != NULL &&
10103 local_got_offsets[r_symndx] != (bfd_vma) -1);
f21f3fe0 10104
252b5132 10105 off = local_got_offsets[r_symndx];
f21f3fe0 10106
252b5132
RH		 10107 /* The offset must always be a multiple of 4. We use the
10108 least significant bit to record whether we have already
9b485d32 10109 generated the necessary reloc. */
252b5132
RH		 10110 if ((off & 1) != 0)
10111 off &= ~1;
10112 else
10113 {
00a97672 10114 if (globals->use_rel)
34e77a92 10115 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
f21f3fe0 10116
0e1862bb 10117 if (bfd_link_pic (info) || dynreloc_st_type == STT_GNU_IFUNC)
252b5132 10118 {
947216bf 10119 Elf_Internal_Rela outrel;
f21f3fe0 10120
34e77a92 10121 outrel.r_addend = addend + dynreloc_value;
252b5132 10122 outrel.r_offset = (sgot->output_section->vma
f21f3fe0 10123 + sgot->output_offset
252b5132 10124 + off);
34e77a92 10125 if (dynreloc_st_type == STT_GNU_IFUNC)
99059e56 10126 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
34e77a92
RS		 10127 else
10128 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
47beaa6a 10129 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
252b5132 10130 }
f21f3fe0 10131
252b5132
RH		 10132 local_got_offsets[r_symndx] |= 1;
10133 }
f21f3fe0 10134
252b5132
RH		 10135 value = sgot->output_offset + off;
10136 }
eb043451
PB		 10137 if (r_type != R_ARM_GOT32)
10138 value += sgot->output_section->vma;
9a5aca8c 10139
f21f3fe0 10140 return _bfd_final_link_relocate (howto, input_bfd, input_section,
99e4ae17 10141 contents, rel->r_offset, value,
00a97672 10142 rel->r_addend);
f21f3fe0 10143
ba93b8ac
DJ		 10144 case R_ARM_TLS_LDO32:
10145 value = value - dtpoff_base (info);
10146
10147 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 10148 contents, rel->r_offset, value,
10149 rel->r_addend);
ba93b8ac
DJ		 10150
10151 case R_ARM_TLS_LDM32:
10152 {
10153 bfd_vma off;
10154
362d30a1 10155 if (sgot == NULL)
ba93b8ac
DJ		 10156 abort ();
10157
10158 off = globals->tls_ldm_got.offset;
10159
10160 if ((off & 1) != 0)
10161 off &= ~1;
10162 else
10163 {
10164 /* If we don't know the module number, create a relocation
10165 for it. */
0e1862bb 10166 if (bfd_link_pic (info))
ba93b8ac
DJ		 10167 {
10168 Elf_Internal_Rela outrel;
ba93b8ac 10169
362d30a1 10170 if (srelgot == NULL)
ba93b8ac
DJ		 10171 abort ();
10172
00a97672 10173 outrel.r_addend = 0;
362d30a1
RS		 10174 outrel.r_offset = (sgot->output_section->vma
10175 + sgot->output_offset + off);
ba93b8ac
DJ		 10176 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
10177
00a97672
RS		 10178 if (globals->use_rel)
10179 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10180 sgot->contents + off);
ba93b8ac 10181
47beaa6a 10182 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10183 }
10184 else
362d30a1 10185 bfd_put_32 (output_bfd, 1, sgot->contents + off);
ba93b8ac
DJ		 10186
10187 globals->tls_ldm_got.offset |= 1;
10188 }
10189
362d30a1 10190 value = sgot->output_section->vma + sgot->output_offset + off
ba93b8ac
DJ		 10191 - (input_section->output_section->vma + input_section->output_offset + rel->r_offset);
10192
10193 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10194 contents, rel->r_offset, value,
00a97672 10195 rel->r_addend);
ba93b8ac
DJ		 10196 }
10197
0855e32b
NS		 10198 case R_ARM_TLS_CALL:
10199 case R_ARM_THM_TLS_CALL:
ba93b8ac
DJ		 10200 case R_ARM_TLS_GD32:
10201 case R_ARM_TLS_IE32:
0855e32b
NS		 10202 case R_ARM_TLS_GOTDESC:
10203 case R_ARM_TLS_DESCSEQ:
10204 case R_ARM_THM_TLS_DESCSEQ:
ba93b8ac 10205 {
0855e32b
NS		 10206 bfd_vma off, offplt;
10207 int indx = 0;
ba93b8ac
DJ		 10208 char tls_type;
10209
0855e32b 10210 BFD_ASSERT (sgot != NULL);
ba93b8ac 10211
ba93b8ac
DJ		 10212 if (h != NULL)
10213 {
10214 bfd_boolean dyn;
10215 dyn = globals->root.dynamic_sections_created;
0e1862bb
L		 10216 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
10217 bfd_link_pic (info),
10218 h)
10219 && (!bfd_link_pic (info)
ba93b8ac
DJ		 10220 || !SYMBOL_REFERENCES_LOCAL (info, h)))
10221 {
10222 *unresolved_reloc_p = FALSE;
10223 indx = h->dynindx;
10224 }
10225 off = h->got.offset;
0855e32b 10226 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
ba93b8ac
DJ		 10227 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
10228 }
10229 else
10230 {
0855e32b 10231 BFD_ASSERT (local_got_offsets != NULL);
ba93b8ac 10232 off = local_got_offsets[r_symndx];
0855e32b 10233 offplt = local_tlsdesc_gotents[r_symndx];
ba93b8ac
DJ		 10234 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
10235 }
10236
0855e32b 10237 /* Linker relaxations happens from one of the
b38cadfb 10238 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
0855e32b 10239 if (ELF32_R_TYPE(rel->r_info) != r_type)
b38cadfb 10240 tls_type = GOT_TLS_IE;
0855e32b
NS		 10241
10242 BFD_ASSERT (tls_type != GOT_UNKNOWN);
ba93b8ac
DJ		 10243
10244 if ((off & 1) != 0)
10245 off &= ~1;
10246 else
10247 {
10248 bfd_boolean need_relocs = FALSE;
10249 Elf_Internal_Rela outrel;
ba93b8ac
DJ		 10250 int cur_off = off;
10251
10252 /* The GOT entries have not been initialized yet. Do it
10253 now, and emit any relocations. If both an IE GOT and a
10254 GD GOT are necessary, we emit the GD first. */
10255
0e1862bb 10256 if ((bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 10257 && (h == NULL
10258 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10259 || h->root.type != bfd_link_hash_undefweak))
10260 {
10261 need_relocs = TRUE;
0855e32b 10262 BFD_ASSERT (srelgot != NULL);
ba93b8ac
DJ		 10263 }
10264
0855e32b
NS		 10265 if (tls_type & GOT_TLS_GDESC)
10266 {
47beaa6a
RS		 10267 bfd_byte *loc;
10268
0855e32b
NS		 10269 /* We should have relaxed, unless this is an undefined
10270 weak symbol. */
10271 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
0e1862bb 10272 || bfd_link_pic (info));
0855e32b 10273 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
99059e56 10274 <= globals->root.sgotplt->size);
0855e32b
NS		 10275
10276 outrel.r_addend = 0;
10277 outrel.r_offset = (globals->root.sgotplt->output_section->vma
10278 + globals->root.sgotplt->output_offset
10279 + offplt
10280 + globals->sgotplt_jump_table_size);
b38cadfb 10281
0855e32b
NS		 10282 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
10283 sreloc = globals->root.srelplt;
10284 loc = sreloc->contents;
10285 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
10286 BFD_ASSERT (loc + RELOC_SIZE (globals)
99059e56 10287 <= sreloc->contents + sreloc->size);
0855e32b
NS		 10288
10289 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
10290
10291 /* For globals, the first word in the relocation gets
10292 the relocation index and the top bit set, or zero,
10293 if we're binding now. For locals, it gets the
10294 symbol's offset in the tls section. */
99059e56 10295 bfd_put_32 (output_bfd,
0855e32b
NS		 10296 !h ? value - elf_hash_table (info)->tls_sec->vma
10297 : info->flags & DF_BIND_NOW ? 0
10298 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
b38cadfb
NC		 10299 globals->root.sgotplt->contents + offplt
10300 + globals->sgotplt_jump_table_size);
10301
0855e32b 10302 /* Second word in the relocation is always zero. */
99059e56 10303 bfd_put_32 (output_bfd, 0,
b38cadfb
NC		 10304 globals->root.sgotplt->contents + offplt
10305 + globals->sgotplt_jump_table_size + 4);
0855e32b 10306 }
ba93b8ac
DJ		 10307 if (tls_type & GOT_TLS_GD)
10308 {
10309 if (need_relocs)
10310 {
00a97672 10311 outrel.r_addend = 0;
362d30a1
RS		 10312 outrel.r_offset = (sgot->output_section->vma
10313 + sgot->output_offset
00a97672 10314 + cur_off);
ba93b8ac 10315 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
ba93b8ac 10316
00a97672
RS		 10317 if (globals->use_rel)
10318 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10319 sgot->contents + cur_off);
00a97672 10320
47beaa6a 10321 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10322
10323 if (indx == 0)
10324 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 10325 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 10326 else
10327 {
00a97672 10328 outrel.r_addend = 0;
ba93b8ac
DJ		 10329 outrel.r_info = ELF32_R_INFO (indx,
10330 R_ARM_TLS_DTPOFF32);
10331 outrel.r_offset += 4;
00a97672
RS		 10332
10333 if (globals->use_rel)
10334 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10335 sgot->contents + cur_off + 4);
00a97672 10336
47beaa6a
RS		 10337 elf32_arm_add_dynreloc (output_bfd, info,
10338 srelgot, &outrel);
ba93b8ac
DJ		 10339 }
10340 }
10341 else
10342 {
10343 /* If we are not emitting relocations for a
10344 general dynamic reference, then we must be in a
10345 static link or an executable link with the
10346 symbol binding locally. Mark it as belonging
10347 to module 1, the executable. */
10348 bfd_put_32 (output_bfd, 1,
362d30a1 10349 sgot->contents + cur_off);
ba93b8ac 10350 bfd_put_32 (output_bfd, value - dtpoff_base (info),
362d30a1 10351 sgot->contents + cur_off + 4);
ba93b8ac
DJ		 10352 }
10353
10354 cur_off += 8;
10355 }
10356
10357 if (tls_type & GOT_TLS_IE)
10358 {
10359 if (need_relocs)
10360 {
00a97672
RS		 10361 if (indx == 0)
10362 outrel.r_addend = value - dtpoff_base (info);
10363 else
10364 outrel.r_addend = 0;
362d30a1
RS		 10365 outrel.r_offset = (sgot->output_section->vma
10366 + sgot->output_offset
ba93b8ac
DJ		 10367 + cur_off);
10368 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
10369
00a97672
RS		 10370 if (globals->use_rel)
10371 bfd_put_32 (output_bfd, outrel.r_addend,
362d30a1 10372 sgot->contents + cur_off);
ba93b8ac 10373
47beaa6a 10374 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
ba93b8ac
DJ		 10375 }
10376 else
10377 bfd_put_32 (output_bfd, tpoff (info, value),
362d30a1 10378 sgot->contents + cur_off);
ba93b8ac
DJ		 10379 cur_off += 4;
10380 }
10381
10382 if (h != NULL)
10383 h->got.offset |= 1;
10384 else
10385 local_got_offsets[r_symndx] |= 1;
10386 }
10387
10388 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32)
10389 off += 8;
0855e32b
NS		 10390 else if (tls_type & GOT_TLS_GDESC)
10391 off = offplt;
10392
10393 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL
10394 || ELF32_R_TYPE(rel->r_info) == R_ARM_THM_TLS_CALL)
10395 {
10396 bfd_signed_vma offset;
12352d3f
PB		 10397 /* TLS stubs are arm mode. The original symbol is a
10398 data object, so branch_type is bogus. */
10399 branch_type = ST_BRANCH_TO_ARM;
0855e32b 10400 enum elf32_arm_stub_type stub_type
34e77a92
RS		 10401 = arm_type_of_stub (info, input_section, rel,
10402 st_type, &branch_type,
0855e32b
NS		 10403 (struct elf32_arm_link_hash_entry *)h,
10404 globals->tls_trampoline, globals->root.splt,
10405 input_bfd, sym_name);
10406
10407 if (stub_type != arm_stub_none)
10408 {
10409 struct elf32_arm_stub_hash_entry *stub_entry
10410 = elf32_arm_get_stub_entry
10411 (input_section, globals->root.splt, 0, rel,
10412 globals, stub_type);
10413 offset = (stub_entry->stub_offset
10414 + stub_entry->stub_sec->output_offset
10415 + stub_entry->stub_sec->output_section->vma);
10416 }
10417 else
10418 offset = (globals->root.splt->output_section->vma
10419 + globals->root.splt->output_offset
10420 + globals->tls_trampoline);
10421
10422 if (ELF32_R_TYPE(rel->r_info) == R_ARM_TLS_CALL)
10423 {
10424 unsigned long inst;
b38cadfb
NC		 10425
10426 offset -= (input_section->output_section->vma
10427 + input_section->output_offset
10428 + rel->r_offset + 8);
0855e32b
NS		 10429
10430 inst = offset >> 2;
10431 inst &= 0x00ffffff;
10432 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
10433 }
10434 else
10435 {
10436 /* Thumb blx encodes the offset in a complicated
10437 fashion. */
10438 unsigned upper_insn, lower_insn;
10439 unsigned neg;
10440
b38cadfb
NC		 10441 offset -= (input_section->output_section->vma
10442 + input_section->output_offset
0855e32b 10443 + rel->r_offset + 4);
b38cadfb 10444
12352d3f
PB		 10445 if (stub_type != arm_stub_none
10446 && arm_stub_is_thumb (stub_type))
10447 {
10448 lower_insn = 0xd000;
10449 }
10450 else
10451 {
10452 lower_insn = 0xc000;
6a631e86 10453 /* Round up the offset to a word boundary. */
12352d3f
PB		 10454 offset = (offset + 2) & ~2;
10455 }
10456
0855e32b
NS		 10457 neg = offset < 0;
10458 upper_insn = (0xf000
10459 | ((offset >> 12) & 0x3ff)
10460 | (neg << 10));
12352d3f 10461 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
0855e32b 10462 | (((!((offset >> 22) & 1)) ^ neg) << 11)
12352d3f 10463 | ((offset >> 1) & 0x7ff);
0855e32b
NS		 10464 bfd_put_16 (input_bfd, upper_insn, hit_data);
10465 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
10466 return bfd_reloc_ok;
10467 }
10468 }
10469 /* These relocations needs special care, as besides the fact
10470 they point somewhere in .gotplt, the addend must be
10471 adjusted accordingly depending on the type of instruction
6a631e86 10472 we refer to. */
0855e32b
NS		 10473 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
10474 {
10475 unsigned long data, insn;
10476 unsigned thumb;
b38cadfb 10477
0855e32b
NS		 10478 data = bfd_get_32 (input_bfd, hit_data);
10479 thumb = data & 1;
10480 data &= ~1u;
b38cadfb 10481
0855e32b
NS		 10482 if (thumb)
10483 {
10484 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
10485 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10486 insn = (insn << 16)
10487 | bfd_get_16 (input_bfd,
10488 contents + rel->r_offset - data + 2);
10489 if ((insn & 0xf800c000) == 0xf000c000)
10490 /* bl/blx */
10491 value = -6;
10492 else if ((insn & 0xffffff00) == 0x4400)
10493 /* add */
10494 value = -5;
10495 else
10496 {
10497 (*_bfd_error_handler)
10498 (_("%B(%A+0x%lx):unexpected Thumb instruction '0x%x' referenced by TLS_GOTDESC"),
10499 input_bfd, input_section,
10500 (unsigned long)rel->r_offset, insn);
10501 return bfd_reloc_notsupported;
10502 }
10503 }
10504 else
10505 {
10506 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
10507
10508 switch (insn >> 24)
10509 {
10510 case 0xeb: /* bl */
10511 case 0xfa: /* blx */
10512 value = -4;
10513 break;
10514
10515 case 0xe0: /* add */
10516 value = -8;
10517 break;
b38cadfb 10518
0855e32b
NS		 10519 default:
10520 (*_bfd_error_handler)
10521 (_("%B(%A+0x%lx):unexpected ARM instruction '0x%x' referenced by TLS_GOTDESC"),
10522 input_bfd, input_section,
10523 (unsigned long)rel->r_offset, insn);
10524 return bfd_reloc_notsupported;
10525 }
10526 }
b38cadfb 10527
0855e32b
NS		 10528 value += ((globals->root.sgotplt->output_section->vma
10529 + globals->root.sgotplt->output_offset + off)
10530 - (input_section->output_section->vma
10531 + input_section->output_offset
10532 + rel->r_offset)
10533 + globals->sgotplt_jump_table_size);
10534 }
10535 else
10536 value = ((globals->root.sgot->output_section->vma
10537 + globals->root.sgot->output_offset + off)
10538 - (input_section->output_section->vma
10539 + input_section->output_offset + rel->r_offset));
ba93b8ac
DJ		 10540
10541 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10542 contents, rel->r_offset, value,
00a97672 10543 rel->r_addend);
ba93b8ac
DJ		 10544 }
10545
10546 case R_ARM_TLS_LE32:
3cbc1e5e 10547 if (bfd_link_dll (info))
ba93b8ac
DJ		 10548 {
10549 (*_bfd_error_handler)
10550 (_("%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object"),
10551 input_bfd, input_section,
10552 (long) rel->r_offset, howto->name);
46691134 10553 return bfd_reloc_notsupported;
ba93b8ac
DJ		 10554 }
10555 else
10556 value = tpoff (info, value);
906e58ca 10557
ba93b8ac 10558 return _bfd_final_link_relocate (howto, input_bfd, input_section,
00a97672
RS		 10559 contents, rel->r_offset, value,
10560 rel->r_addend);
ba93b8ac 10561
319850b4
JB		 10562 case R_ARM_V4BX:
10563 if (globals->fix_v4bx)
845b51d6
PB		 10564 {
10565 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
319850b4 10566
845b51d6
PB		 10567 /* Ensure that we have a BX instruction. */
10568 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
319850b4 10569
845b51d6
PB		 10570 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
10571 {
10572 /* Branch to veneer. */
10573 bfd_vma glue_addr;
10574 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
10575 glue_addr -= input_section->output_section->vma
10576 + input_section->output_offset
10577 + rel->r_offset + 8;
10578 insn = (insn & 0xf0000000) | 0x0a000000
10579 | ((glue_addr >> 2) & 0x00ffffff);
10580 }
10581 else
10582 {
10583 /* Preserve Rm (lowest four bits) and the condition code
10584 (highest four bits). Other bits encode MOV PC,Rm. */
10585 insn = (insn & 0xf000000f) | 0x01a0f000;
10586 }
319850b4 10587
845b51d6
PB		 10588 bfd_put_32 (input_bfd, insn, hit_data);
10589 }
319850b4
JB		 10590 return bfd_reloc_ok;
10591
b6895b4f
PB		 10592 case R_ARM_MOVW_ABS_NC:
10593 case R_ARM_MOVT_ABS:
10594 case R_ARM_MOVW_PREL_NC:
10595 case R_ARM_MOVT_PREL:
92f5d02b
MS		 10596 /* Until we properly support segment-base-relative addressing then
10597 we assume the segment base to be zero, as for the group relocations.
10598 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
10599 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
10600 case R_ARM_MOVW_BREL_NC:
10601 case R_ARM_MOVW_BREL:
10602 case R_ARM_MOVT_BREL:
b6895b4f
PB		 10603 {
10604 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
10605
10606 if (globals->use_rel)
10607 {
10608 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
39623e12 10609 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 10610 }
92f5d02b 10611
b6895b4f 10612 value += signed_addend;
b6895b4f
PB		 10613
10614 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
10615 value -= (input_section->output_section->vma
10616 + input_section->output_offset + rel->r_offset);
10617
92f5d02b 10618 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
99059e56 10619 return bfd_reloc_overflow;
92f5d02b 10620
35fc36a8 10621 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 10622 value |= 1;
10623
10624 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
99059e56 10625 || r_type == R_ARM_MOVT_BREL)
b6895b4f
PB		 10626 value >>= 16;
10627
10628 insn &= 0xfff0f000;
10629 insn |= value & 0xfff;
10630 insn |= (value & 0xf000) << 4;
10631 bfd_put_32 (input_bfd, insn, hit_data);
10632 }
10633 return bfd_reloc_ok;
10634
10635 case R_ARM_THM_MOVW_ABS_NC:
10636 case R_ARM_THM_MOVT_ABS:
10637 case R_ARM_THM_MOVW_PREL_NC:
10638 case R_ARM_THM_MOVT_PREL:
92f5d02b
MS		 10639 /* Until we properly support segment-base-relative addressing then
10640 we assume the segment base to be zero, as for the above relocations.
10641 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
10642 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
10643 as R_ARM_THM_MOVT_ABS. */
10644 case R_ARM_THM_MOVW_BREL_NC:
10645 case R_ARM_THM_MOVW_BREL:
10646 case R_ARM_THM_MOVT_BREL:
b6895b4f
PB		 10647 {
10648 bfd_vma insn;
906e58ca 10649
b6895b4f
PB		 10650 insn = bfd_get_16 (input_bfd, hit_data) << 16;
10651 insn |= bfd_get_16 (input_bfd, hit_data + 2);
10652
10653 if (globals->use_rel)
10654 {
10655 addend = ((insn >> 4) & 0xf000)
10656 | ((insn >> 15) & 0x0800)
10657 | ((insn >> 4) & 0x0700)
10658 | (insn & 0x00ff);
39623e12 10659 signed_addend = (addend ^ 0x8000) - 0x8000;
b6895b4f 10660 }
92f5d02b 10661
b6895b4f 10662 value += signed_addend;
b6895b4f
PB		 10663
10664 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
10665 value -= (input_section->output_section->vma
10666 + input_section->output_offset + rel->r_offset);
10667
92f5d02b 10668 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
99059e56 10669 return bfd_reloc_overflow;
92f5d02b 10670
35fc36a8 10671 if (branch_type == ST_BRANCH_TO_THUMB)
92f5d02b
MS		 10672 value |= 1;
10673
10674 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
99059e56 10675 || r_type == R_ARM_THM_MOVT_BREL)
b6895b4f
PB		 10676 value >>= 16;
10677
10678 insn &= 0xfbf08f00;
10679 insn |= (value & 0xf000) << 4;
10680 insn |= (value & 0x0800) << 15;
10681 insn |= (value & 0x0700) << 4;
10682 insn |= (value & 0x00ff);
10683
10684 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10685 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10686 }
10687 return bfd_reloc_ok;
10688
4962c51a
MS		 10689 case R_ARM_ALU_PC_G0_NC:
10690 case R_ARM_ALU_PC_G1_NC:
10691 case R_ARM_ALU_PC_G0:
10692 case R_ARM_ALU_PC_G1:
10693 case R_ARM_ALU_PC_G2:
10694 case R_ARM_ALU_SB_G0_NC:
10695 case R_ARM_ALU_SB_G1_NC:
10696 case R_ARM_ALU_SB_G0:
10697 case R_ARM_ALU_SB_G1:
10698 case R_ARM_ALU_SB_G2:
10699 {
10700 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10701 bfd_vma pc = input_section->output_section->vma
4962c51a 10702 + input_section->output_offset + rel->r_offset;
31a91d61 10703 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10704 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56
RM		 10705 bfd_vma residual;
10706 bfd_vma g_n;
4962c51a 10707 bfd_signed_vma signed_value;
99059e56
RM		 10708 int group = 0;
10709
10710 /* Determine which group of bits to select. */
10711 switch (r_type)
10712 {
10713 case R_ARM_ALU_PC_G0_NC:
10714 case R_ARM_ALU_PC_G0:
10715 case R_ARM_ALU_SB_G0_NC:
10716 case R_ARM_ALU_SB_G0:
10717 group = 0;
10718 break;
10719
10720 case R_ARM_ALU_PC_G1_NC:
10721 case R_ARM_ALU_PC_G1:
10722 case R_ARM_ALU_SB_G1_NC:
10723 case R_ARM_ALU_SB_G1:
10724 group = 1;
10725 break;
10726
10727 case R_ARM_ALU_PC_G2:
10728 case R_ARM_ALU_SB_G2:
10729 group = 2;
10730 break;
10731
10732 default:
10733 abort ();
10734 }
10735
10736 /* If REL, extract the addend from the insn. If RELA, it will
10737 have already been fetched for us. */
4962c51a 10738 if (globals->use_rel)
99059e56
RM		 10739 {
10740 int negative;
10741 bfd_vma constant = insn & 0xff;
10742 bfd_vma rotation = (insn & 0xf00) >> 8;
10743
10744 if (rotation == 0)
10745 signed_addend = constant;
10746 else
10747 {
10748 /* Compensate for the fact that in the instruction, the
10749 rotation is stored in multiples of 2 bits. */
10750 rotation *= 2;
10751
10752 /* Rotate "constant" right by "rotation" bits. */
10753 signed_addend = (constant >> rotation) |
10754 (constant << (8 * sizeof (bfd_vma) - rotation));
10755 }
10756
10757 /* Determine if the instruction is an ADD or a SUB.
10758 (For REL, this determines the sign of the addend.) */
10759 negative = identify_add_or_sub (insn);
10760 if (negative == 0)
10761 {
10762 (*_bfd_error_handler)
10763 (_("%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations"),
10764 input_bfd, input_section,
10765 (long) rel->r_offset, howto->name);
10766 return bfd_reloc_overflow;
10767 }
10768
10769 signed_addend *= negative;
10770 }
4962c51a
MS		 10771
10772 /* Compute the value (X) to go in the place. */
99059e56
RM		 10773 if (r_type == R_ARM_ALU_PC_G0_NC
10774 || r_type == R_ARM_ALU_PC_G1_NC
10775 || r_type == R_ARM_ALU_PC_G0
10776 || r_type == R_ARM_ALU_PC_G1
10777 || r_type == R_ARM_ALU_PC_G2)
10778 /* PC relative. */
10779 signed_value = value - pc + signed_addend;
10780 else
10781 /* Section base relative. */
10782 signed_value = value - sb + signed_addend;
10783
10784 /* If the target symbol is a Thumb function, then set the
10785 Thumb bit in the address. */
35fc36a8 10786 if (branch_type == ST_BRANCH_TO_THUMB)
4962c51a
MS		 10787 signed_value |= 1;
10788
99059e56
RM		 10789 /* Calculate the value of the relevant G_n, in encoded
10790 constant-with-rotation format. */
b6518b38
NC		 10791 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
10792 group, &residual);
99059e56
RM		 10793
10794 /* Check for overflow if required. */
10795 if ((r_type == R_ARM_ALU_PC_G0
10796 || r_type == R_ARM_ALU_PC_G1
10797 || r_type == R_ARM_ALU_PC_G2
10798 || r_type == R_ARM_ALU_SB_G0
10799 || r_type == R_ARM_ALU_SB_G1
10800 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
10801 {
10802 (*_bfd_error_handler)
10803 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
10804 input_bfd, input_section,
b6518b38
NC		 10805 (long) rel->r_offset, signed_value < 0 ? - signed_value : signed_value,
10806 howto->name);
99059e56
RM		 10807 return bfd_reloc_overflow;
10808 }
10809
10810 /* Mask out the value and the ADD/SUB part of the opcode; take care
10811 not to destroy the S bit. */
10812 insn &= 0xff1ff000;
10813
10814 /* Set the opcode according to whether the value to go in the
10815 place is negative. */
10816 if (signed_value < 0)
10817 insn |= 1 << 22;
10818 else
10819 insn |= 1 << 23;
10820
10821 /* Encode the offset. */
10822 insn |= g_n;
4962c51a
MS		 10823
10824 bfd_put_32 (input_bfd, insn, hit_data);
10825 }
10826 return bfd_reloc_ok;
10827
10828 case R_ARM_LDR_PC_G0:
10829 case R_ARM_LDR_PC_G1:
10830 case R_ARM_LDR_PC_G2:
10831 case R_ARM_LDR_SB_G0:
10832 case R_ARM_LDR_SB_G1:
10833 case R_ARM_LDR_SB_G2:
10834 {
10835 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10836 bfd_vma pc = input_section->output_section->vma
4962c51a 10837 + input_section->output_offset + rel->r_offset;
31a91d61 10838 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10839 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 10840 bfd_vma residual;
4962c51a 10841 bfd_signed_vma signed_value;
99059e56
RM		 10842 int group = 0;
10843
10844 /* Determine which groups of bits to calculate. */
10845 switch (r_type)
10846 {
10847 case R_ARM_LDR_PC_G0:
10848 case R_ARM_LDR_SB_G0:
10849 group = 0;
10850 break;
10851
10852 case R_ARM_LDR_PC_G1:
10853 case R_ARM_LDR_SB_G1:
10854 group = 1;
10855 break;
10856
10857 case R_ARM_LDR_PC_G2:
10858 case R_ARM_LDR_SB_G2:
10859 group = 2;
10860 break;
10861
10862 default:
10863 abort ();
10864 }
10865
10866 /* If REL, extract the addend from the insn. If RELA, it will
10867 have already been fetched for us. */
4962c51a 10868 if (globals->use_rel)
99059e56
RM		 10869 {
10870 int negative = (insn & (1 << 23)) ? 1 : -1;
10871 signed_addend = negative * (insn & 0xfff);
10872 }
4962c51a
MS		 10873
10874 /* Compute the value (X) to go in the place. */
99059e56
RM		 10875 if (r_type == R_ARM_LDR_PC_G0
10876 || r_type == R_ARM_LDR_PC_G1
10877 || r_type == R_ARM_LDR_PC_G2)
10878 /* PC relative. */
10879 signed_value = value - pc + signed_addend;
10880 else
10881 /* Section base relative. */
10882 signed_value = value - sb + signed_addend;
10883
10884 /* Calculate the value of the relevant G_{n-1} to obtain
10885 the residual at that stage. */
b6518b38
NC		 10886 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
10887 group - 1, &residual);
99059e56
RM		 10888
10889 /* Check for overflow. */
10890 if (residual >= 0x1000)
10891 {
10892 (*_bfd_error_handler)
10893 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 10894 input_bfd, input_section,
10895 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 10896 return bfd_reloc_overflow;
10897 }
10898
10899 /* Mask out the value and U bit. */
10900 insn &= 0xff7ff000;
10901
10902 /* Set the U bit if the value to go in the place is non-negative. */
10903 if (signed_value >= 0)
10904 insn |= 1 << 23;
10905
10906 /* Encode the offset. */
10907 insn |= residual;
4962c51a
MS		 10908
10909 bfd_put_32 (input_bfd, insn, hit_data);
10910 }
10911 return bfd_reloc_ok;
10912
10913 case R_ARM_LDRS_PC_G0:
10914 case R_ARM_LDRS_PC_G1:
10915 case R_ARM_LDRS_PC_G2:
10916 case R_ARM_LDRS_SB_G0:
10917 case R_ARM_LDRS_SB_G1:
10918 case R_ARM_LDRS_SB_G2:
10919 {
10920 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 10921 bfd_vma pc = input_section->output_section->vma
4962c51a 10922 + input_section->output_offset + rel->r_offset;
31a91d61 10923 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 10924 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 10925 bfd_vma residual;
4962c51a 10926 bfd_signed_vma signed_value;
99059e56
RM		 10927 int group = 0;
10928
10929 /* Determine which groups of bits to calculate. */
10930 switch (r_type)
10931 {
10932 case R_ARM_LDRS_PC_G0:
10933 case R_ARM_LDRS_SB_G0:
10934 group = 0;
10935 break;
10936
10937 case R_ARM_LDRS_PC_G1:
10938 case R_ARM_LDRS_SB_G1:
10939 group = 1;
10940 break;
10941
10942 case R_ARM_LDRS_PC_G2:
10943 case R_ARM_LDRS_SB_G2:
10944 group = 2;
10945 break;
10946
10947 default:
10948 abort ();
10949 }
10950
10951 /* If REL, extract the addend from the insn. If RELA, it will
10952 have already been fetched for us. */
4962c51a 10953 if (globals->use_rel)
99059e56
RM		 10954 {
10955 int negative = (insn & (1 << 23)) ? 1 : -1;
10956 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
10957 }
4962c51a
MS		 10958
10959 /* Compute the value (X) to go in the place. */
99059e56
RM		 10960 if (r_type == R_ARM_LDRS_PC_G0
10961 || r_type == R_ARM_LDRS_PC_G1
10962 || r_type == R_ARM_LDRS_PC_G2)
10963 /* PC relative. */
10964 signed_value = value - pc + signed_addend;
10965 else
10966 /* Section base relative. */
10967 signed_value = value - sb + signed_addend;
10968
10969 /* Calculate the value of the relevant G_{n-1} to obtain
10970 the residual at that stage. */
b6518b38
NC		 10971 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
10972 group - 1, &residual);
99059e56
RM		 10973
10974 /* Check for overflow. */
10975 if (residual >= 0x100)
10976 {
10977 (*_bfd_error_handler)
10978 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
b6518b38
NC		 10979 input_bfd, input_section,
10980 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 10981 return bfd_reloc_overflow;
10982 }
10983
10984 /* Mask out the value and U bit. */
10985 insn &= 0xff7ff0f0;
10986
10987 /* Set the U bit if the value to go in the place is non-negative. */
10988 if (signed_value >= 0)
10989 insn |= 1 << 23;
10990
10991 /* Encode the offset. */
10992 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
4962c51a
MS		 10993
10994 bfd_put_32 (input_bfd, insn, hit_data);
10995 }
10996 return bfd_reloc_ok;
10997
10998 case R_ARM_LDC_PC_G0:
10999 case R_ARM_LDC_PC_G1:
11000 case R_ARM_LDC_PC_G2:
11001 case R_ARM_LDC_SB_G0:
11002 case R_ARM_LDC_SB_G1:
11003 case R_ARM_LDC_SB_G2:
11004 {
11005 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
99059e56 11006 bfd_vma pc = input_section->output_section->vma
4962c51a 11007 + input_section->output_offset + rel->r_offset;
31a91d61 11008 /* sb is the origin of the *segment* containing the symbol. */
62c34db3 11009 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
99059e56 11010 bfd_vma residual;
4962c51a 11011 bfd_signed_vma signed_value;
99059e56
RM		 11012 int group = 0;
11013
11014 /* Determine which groups of bits to calculate. */
11015 switch (r_type)
11016 {
11017 case R_ARM_LDC_PC_G0:
11018 case R_ARM_LDC_SB_G0:
11019 group = 0;
11020 break;
11021
11022 case R_ARM_LDC_PC_G1:
11023 case R_ARM_LDC_SB_G1:
11024 group = 1;
11025 break;
11026
11027 case R_ARM_LDC_PC_G2:
11028 case R_ARM_LDC_SB_G2:
11029 group = 2;
11030 break;
11031
11032 default:
11033 abort ();
11034 }
11035
11036 /* If REL, extract the addend from the insn. If RELA, it will
11037 have already been fetched for us. */
4962c51a 11038 if (globals->use_rel)
99059e56
RM		 11039 {
11040 int negative = (insn & (1 << 23)) ? 1 : -1;
11041 signed_addend = negative * ((insn & 0xff) << 2);
11042 }
4962c51a
MS		 11043
11044 /* Compute the value (X) to go in the place. */
99059e56
RM		 11045 if (r_type == R_ARM_LDC_PC_G0
11046 || r_type == R_ARM_LDC_PC_G1
11047 || r_type == R_ARM_LDC_PC_G2)
11048 /* PC relative. */
11049 signed_value = value - pc + signed_addend;
11050 else
11051 /* Section base relative. */
11052 signed_value = value - sb + signed_addend;
11053
11054 /* Calculate the value of the relevant G_{n-1} to obtain
11055 the residual at that stage. */
b6518b38
NC		 11056 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
11057 group - 1, &residual);
99059e56
RM		 11058
11059 /* Check for overflow. (The absolute value to go in the place must be
11060 divisible by four and, after having been divided by four, must
11061 fit in eight bits.) */
11062 if ((residual & 0x3) != 0 || residual >= 0x400)
11063 {
11064 (*_bfd_error_handler)
11065 (_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
11066 input_bfd, input_section,
b6518b38 11067 (long) rel->r_offset, labs (signed_value), howto->name);
99059e56
RM		 11068 return bfd_reloc_overflow;
11069 }
11070
11071 /* Mask out the value and U bit. */
11072 insn &= 0xff7fff00;
11073
11074 /* Set the U bit if the value to go in the place is non-negative. */
11075 if (signed_value >= 0)
11076 insn |= 1 << 23;
11077
11078 /* Encode the offset. */
11079 insn |= residual >> 2;
4962c51a
MS		 11080
11081 bfd_put_32 (input_bfd, insn, hit_data);
11082 }
11083 return bfd_reloc_ok;
11084
72d98d16
MG		 11085 case R_ARM_THM_ALU_ABS_G0_NC:
11086 case R_ARM_THM_ALU_ABS_G1_NC:
11087 case R_ARM_THM_ALU_ABS_G2_NC:
11088 case R_ARM_THM_ALU_ABS_G3_NC:
11089 {
11090 const int shift_array[4] = {0, 8, 16, 24};
11091 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
11092 bfd_vma addr = value;
11093 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
11094
11095 /* Compute address. */
11096 if (globals->use_rel)
11097 signed_addend = insn & 0xff;
11098 addr += signed_addend;
11099 if (branch_type == ST_BRANCH_TO_THUMB)
11100 addr |= 1;
11101 /* Clean imm8 insn. */
11102 insn &= 0xff00;
11103 /* And update with correct part of address. */
11104 insn |= (addr >> shift) & 0xff;
11105 /* Update insn. */
11106 bfd_put_16 (input_bfd, insn, hit_data);
11107 }
11108
11109 *unresolved_reloc_p = FALSE;
11110 return bfd_reloc_ok;
11111
252b5132
RH		 11112 default:
11113 return bfd_reloc_notsupported;
11114 }
11115}
11116
98c1d4aa
NC		 11117/* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
11118static void
57e8b36a
NC		 11119arm_add_to_rel (bfd * abfd,
11120 bfd_byte * address,
11121 reloc_howto_type * howto,
11122 bfd_signed_vma increment)
98c1d4aa 11123{
98c1d4aa
NC		 11124 bfd_signed_vma addend;
11125
bd97cb95
DJ		 11126 if (howto->type == R_ARM_THM_CALL
11127 || howto->type == R_ARM_THM_JUMP24)
98c1d4aa 11128 {
9a5aca8c
AM		 11129 int upper_insn, lower_insn;
11130 int upper, lower;
98c1d4aa 11131
9a5aca8c
AM		 11132 upper_insn = bfd_get_16 (abfd, address);
11133 lower_insn = bfd_get_16 (abfd, address + 2);
11134 upper = upper_insn & 0x7ff;
11135 lower = lower_insn & 0x7ff;
11136
11137 addend = (upper << 12) | (lower << 1);
ddda4409 11138 addend += increment;
9a5aca8c 11139 addend >>= 1;
98c1d4aa 11140
9a5aca8c
AM		 11141 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
11142 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
11143
dc810e39
AM		 11144 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
11145 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
9a5aca8c
AM		 11146 }
11147 else
11148 {
11149 bfd_vma contents;
11150
11151 contents = bfd_get_32 (abfd, address);
11152
11153 /* Get the (signed) value from the instruction. */
11154 addend = contents & howto->src_mask;
11155 if (addend & ((howto->src_mask + 1) >> 1))
11156 {
11157 bfd_signed_vma mask;
11158
11159 mask = -1;
11160 mask &= ~ howto->src_mask;
11161 addend |= mask;
11162 }
11163
11164 /* Add in the increment, (which is a byte value). */
11165 switch (howto->type)
11166 {
11167 default:
11168 addend += increment;
11169 break;
11170
11171 case R_ARM_PC24:
c6596c5e 11172 case R_ARM_PLT32:
5b5bb741
PB		 11173 case R_ARM_CALL:
11174 case R_ARM_JUMP24:
9a5aca8c 11175 addend <<= howto->size;
dc810e39 11176 addend += increment;
9a5aca8c
AM		 11177
11178 /* Should we check for overflow here ? */
11179
11180 /* Drop any undesired bits. */
11181 addend >>= howto->rightshift;
11182 break;
11183 }
11184
11185 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
11186
11187 bfd_put_32 (abfd, contents, address);
ddda4409 11188 }
98c1d4aa 11189}
252b5132 11190
ba93b8ac
DJ		 11191#define IS_ARM_TLS_RELOC(R_TYPE) \
11192 ((R_TYPE) == R_ARM_TLS_GD32 \
11193 || (R_TYPE) == R_ARM_TLS_LDO32 \
11194 || (R_TYPE) == R_ARM_TLS_LDM32 \
11195 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
11196 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
11197 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
11198 || (R_TYPE) == R_ARM_TLS_LE32 \
0855e32b
NS		 11199 || (R_TYPE) == R_ARM_TLS_IE32 \
11200 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
11201
11202/* Specific set of relocations for the gnu tls dialect. */
11203#define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
11204 ((R_TYPE) == R_ARM_TLS_GOTDESC \
11205 || (R_TYPE) == R_ARM_TLS_CALL \
11206 || (R_TYPE) == R_ARM_THM_TLS_CALL \
11207 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
11208 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
ba93b8ac 11209
252b5132 11210/* Relocate an ARM ELF section. */
906e58ca 11211
b34976b6 11212static bfd_boolean
57e8b36a
NC		 11213elf32_arm_relocate_section (bfd * output_bfd,
11214 struct bfd_link_info * info,
11215 bfd * input_bfd,
11216 asection * input_section,
11217 bfd_byte * contents,
11218 Elf_Internal_Rela * relocs,
11219 Elf_Internal_Sym * local_syms,
11220 asection ** local_sections)
252b5132 11221{
b34976b6
AM		 11222 Elf_Internal_Shdr *symtab_hdr;
11223 struct elf_link_hash_entry **sym_hashes;
11224 Elf_Internal_Rela *rel;
11225 Elf_Internal_Rela *relend;
11226 const char *name;
b32d3aa2 11227 struct elf32_arm_link_hash_table * globals;
252b5132 11228
4e7fd91e 11229 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 11230 if (globals == NULL)
11231 return FALSE;
b491616a 11232
0ffa91dd 11233 symtab_hdr = & elf_symtab_hdr (input_bfd);
252b5132
RH		 11234 sym_hashes = elf_sym_hashes (input_bfd);
11235
11236 rel = relocs;
11237 relend = relocs + input_section->reloc_count;
11238 for (; rel < relend; rel++)
11239 {
ba96a88f
NC		 11240 int r_type;
11241 reloc_howto_type * howto;
11242 unsigned long r_symndx;
11243 Elf_Internal_Sym * sym;
11244 asection * sec;
252b5132 11245 struct elf_link_hash_entry * h;
ba96a88f
NC		 11246 bfd_vma relocation;
11247 bfd_reloc_status_type r;
11248 arelent bfd_reloc;
ba93b8ac 11249 char sym_type;
0945cdfd 11250 bfd_boolean unresolved_reloc = FALSE;
f2a9dd69 11251 char *error_message = NULL;
f21f3fe0 11252
252b5132 11253 r_symndx = ELF32_R_SYM (rel->r_info);
ba96a88f 11254 r_type = ELF32_R_TYPE (rel->r_info);
b32d3aa2 11255 r_type = arm_real_reloc_type (globals, r_type);
252b5132 11256
ba96a88f 11257 if ( r_type == R_ARM_GNU_VTENTRY
99059e56
RM		 11258 || r_type == R_ARM_GNU_VTINHERIT)
11259 continue;
252b5132 11260
b32d3aa2 11261 bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
ba96a88f 11262 howto = bfd_reloc.howto;
252b5132 11263
252b5132
RH		 11264 h = NULL;
11265 sym = NULL;
11266 sec = NULL;
9b485d32 11267
252b5132
RH		 11268 if (r_symndx < symtab_hdr->sh_info)
11269 {
11270 sym = local_syms + r_symndx;
ba93b8ac 11271 sym_type = ELF32_ST_TYPE (sym->st_info);
252b5132 11272 sec = local_sections[r_symndx];
ffcb4889
NS		 11273
11274 /* An object file might have a reference to a local
11275 undefined symbol. This is a daft object file, but we
11276 should at least do something about it. V4BX & NONE
11277 relocations do not use the symbol and are explicitly
77b4f08f
TS		 11278 allowed to use the undefined symbol, so allow those.
11279 Likewise for relocations against STN_UNDEF. */
ffcb4889
NS		 11280 if (r_type != R_ARM_V4BX
11281 && r_type != R_ARM_NONE
77b4f08f 11282 && r_symndx != STN_UNDEF
ffcb4889
NS		 11283 && bfd_is_und_section (sec)
11284 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
11285 {
11286 if (!info->callbacks->undefined_symbol
11287 (info, bfd_elf_string_from_elf_section
11288 (input_bfd, symtab_hdr->sh_link, sym->st_name),
11289 input_bfd, input_section,
11290 rel->r_offset, TRUE))
11291 return FALSE;
11292 }
b38cadfb 11293
4e7fd91e 11294 if (globals->use_rel)
f8df10f4 11295 {
4e7fd91e
PB		 11296 relocation = (sec->output_section->vma
11297 + sec->output_offset
11298 + sym->st_value);
0e1862bb 11299 if (!bfd_link_relocatable (info)
ab96bf03
AM		 11300 && (sec->flags & SEC_MERGE)
11301 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
f8df10f4 11302 {
4e7fd91e
PB		 11303 asection *msec;
11304 bfd_vma addend, value;
11305
39623e12 11306 switch (r_type)
4e7fd91e 11307 {
39623e12
PB		 11308 case R_ARM_MOVW_ABS_NC:
11309 case R_ARM_MOVT_ABS:
11310 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
11311 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
11312 addend = (addend ^ 0x8000) - 0x8000;
11313 break;
f8df10f4 11314
39623e12
PB		 11315 case R_ARM_THM_MOVW_ABS_NC:
11316 case R_ARM_THM_MOVT_ABS:
11317 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
11318 << 16;
11319 value |= bfd_get_16 (input_bfd,
11320 contents + rel->r_offset + 2);
11321 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
11322 | ((value & 0x04000000) >> 15);
11323 addend = (addend ^ 0x8000) - 0x8000;
11324 break;
f8df10f4 11325
39623e12
PB		 11326 default:
11327 if (howto->rightshift
11328 || (howto->src_mask & (howto->src_mask + 1)))
11329 {
11330 (*_bfd_error_handler)
11331 (_("%B(%A+0x%lx): %s relocation against SEC_MERGE section"),
11332 input_bfd, input_section,
11333 (long) rel->r_offset, howto->name);
11334 return FALSE;
11335 }
11336
11337 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
11338
11339 /* Get the (signed) value from the instruction. */
11340 addend = value & howto->src_mask;
11341 if (addend & ((howto->src_mask + 1) >> 1))
11342 {
11343 bfd_signed_vma mask;
11344
11345 mask = -1;
11346 mask &= ~ howto->src_mask;
11347 addend |= mask;
11348 }
11349 break;
4e7fd91e 11350 }
39623e12 11351
4e7fd91e
PB		 11352 msec = sec;
11353 addend =
11354 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
11355 - relocation;
11356 addend += msec->output_section->vma + msec->output_offset;
39623e12 11357
cc643b88 11358 /* Cases here must match those in the preceding
39623e12
PB		 11359 switch statement. */
11360 switch (r_type)
11361 {
11362 case R_ARM_MOVW_ABS_NC:
11363 case R_ARM_MOVT_ABS:
11364 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
11365 | (addend & 0xfff);
11366 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
11367 break;
11368
11369 case R_ARM_THM_MOVW_ABS_NC:
11370 case R_ARM_THM_MOVT_ABS:
11371 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
11372 | (addend & 0xff) | ((addend & 0x0800) << 15);
11373 bfd_put_16 (input_bfd, value >> 16,
11374 contents + rel->r_offset);
11375 bfd_put_16 (input_bfd, value,
11376 contents + rel->r_offset + 2);
11377 break;
11378
11379 default:
11380 value = (value & ~ howto->dst_mask)
11381 | (addend & howto->dst_mask);
11382 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
11383 break;
11384 }
f8df10f4 11385 }
f8df10f4 11386 }
4e7fd91e
PB		 11387 else
11388 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
252b5132
RH		 11389 }
11390 else
11391 {
62d887d4 11392 bfd_boolean warned, ignored;
560e09e9 11393
b2a8e766
AM		 11394 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
11395 r_symndx, symtab_hdr, sym_hashes,
11396 h, sec, relocation,
62d887d4 11397 unresolved_reloc, warned, ignored);
ba93b8ac
DJ		 11398
11399 sym_type = h->type;
252b5132
RH		 11400 }
11401
dbaa2011 11402 if (sec != NULL && discarded_section (sec))
e4067dbb 11403 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 11404 rel, 1, relend, howto, 0, contents);
ab96bf03 11405
0e1862bb 11406 if (bfd_link_relocatable (info))
ab96bf03
AM		 11407 {
11408 /* This is a relocatable link. We don't have to change
11409 anything, unless the reloc is against a section symbol,
11410 in which case we have to adjust according to where the
11411 section symbol winds up in the output section. */
11412 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
11413 {
11414 if (globals->use_rel)
11415 arm_add_to_rel (input_bfd, contents + rel->r_offset,
11416 howto, (bfd_signed_vma) sec->output_offset);
11417 else
11418 rel->r_addend += sec->output_offset;
11419 }
11420 continue;
11421 }
11422
252b5132
RH		 11423 if (h != NULL)
11424 name = h->root.root.string;
11425 else
11426 {
11427 name = (bfd_elf_string_from_elf_section
11428 (input_bfd, symtab_hdr->sh_link, sym->st_name));
11429 if (name == NULL || *name == '\0')
11430 name = bfd_section_name (input_bfd, sec);
11431 }
f21f3fe0 11432
cf35638d 11433 if (r_symndx != STN_UNDEF
ba93b8ac
DJ		 11434 && r_type != R_ARM_NONE
11435 && (h == NULL
11436 || h->root.type == bfd_link_hash_defined
11437 || h->root.type == bfd_link_hash_defweak)
11438 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
11439 {
11440 (*_bfd_error_handler)
11441 ((sym_type == STT_TLS
11442 ? _("%B(%A+0x%lx): %s used with TLS symbol %s")
11443 : _("%B(%A+0x%lx): %s used with non-TLS symbol %s")),
11444 input_bfd,
11445 input_section,
11446 (long) rel->r_offset,
11447 howto->name,
11448 name);
11449 }
11450
0855e32b 11451 /* We call elf32_arm_final_link_relocate unless we're completely
99059e56
RM		 11452 done, i.e., the relaxation produced the final output we want,
11453 and we won't let anybody mess with it. Also, we have to do
11454 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
6a631e86 11455 both in relaxed and non-relaxed cases. */
0855e32b
NS		 11456 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
11457 || (IS_ARM_TLS_GNU_RELOC (r_type)
b38cadfb 11458 && !((h ? elf32_arm_hash_entry (h)->tls_type :
0855e32b
NS		 11459 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
11460 & GOT_TLS_GDESC)))
11461 {
11462 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
11463 contents, rel, h == NULL);
11464 /* This may have been marked unresolved because it came from
11465 a shared library. But we've just dealt with that. */
11466 unresolved_reloc = 0;
11467 }
11468 else
11469 r = bfd_reloc_continue;
b38cadfb 11470
0855e32b
NS		 11471 if (r == bfd_reloc_continue)
11472 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
11473 input_section, contents, rel,
34e77a92 11474 relocation, info, sec, name, sym_type,
35fc36a8
RS		 11475 (h ? h->target_internal
11476 : ARM_SYM_BRANCH_TYPE (sym)), h,
0855e32b 11477 &unresolved_reloc, &error_message);
0945cdfd
DJ		 11478
11479 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
11480 because such sections are not SEC_ALLOC and thus ld.so will
11481 not process them. */
11482 if (unresolved_reloc
99059e56
RM		 11483 && !((input_section->flags & SEC_DEBUGGING) != 0
11484 && h->def_dynamic)
1d5316ab
AM		 11485 && _bfd_elf_section_offset (output_bfd, info, input_section,
11486 rel->r_offset) != (bfd_vma) -1)
0945cdfd
DJ		 11487 {
11488 (*_bfd_error_handler)
843fe662
L		 11489 (_("%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'"),
11490 input_bfd,
11491 input_section,
11492 (long) rel->r_offset,
11493 howto->name,
11494 h->root.root.string);
0945cdfd
DJ		 11495 return FALSE;
11496 }
252b5132
RH		 11497
11498 if (r != bfd_reloc_ok)
11499 {
252b5132
RH		 11500 switch (r)
11501 {
11502 case bfd_reloc_overflow:
cf919dfd
PB		 11503 /* If the overflowing reloc was to an undefined symbol,
11504 we have already printed one error message and there
11505 is no point complaining again. */
11506 if ((! h ||
11507 h->root.type != bfd_link_hash_undefined)
11508 && (!((*info->callbacks->reloc_overflow)
dfeffb9f
L		 11509 (info, (h ? &h->root : NULL), name, howto->name,
11510 (bfd_vma) 0, input_bfd, input_section,
11511 rel->r_offset))))
b34976b6 11512 return FALSE;
252b5132
RH		 11513 break;
11514
11515 case bfd_reloc_undefined:
11516 if (!((*info->callbacks->undefined_symbol)
11517 (info, name, input_bfd, input_section,
b34976b6
AM		 11518 rel->r_offset, TRUE)))
11519 return FALSE;
252b5132
RH		 11520 break;
11521
11522 case bfd_reloc_outofrange:
f2a9dd69 11523 error_message = _("out of range");
252b5132
RH		 11524 goto common_error;
11525
11526 case bfd_reloc_notsupported:
f2a9dd69 11527 error_message = _("unsupported relocation");
252b5132
RH		 11528 goto common_error;
11529
11530 case bfd_reloc_dangerous:
f2a9dd69 11531 /* error_message should already be set. */
252b5132
RH		 11532 goto common_error;
11533
11534 default:
f2a9dd69 11535 error_message = _("unknown error");
8029a119 11536 /* Fall through. */
252b5132
RH		 11537
11538 common_error:
f2a9dd69
DJ		 11539 BFD_ASSERT (error_message != NULL);
11540 if (!((*info->callbacks->reloc_dangerous)
11541 (info, error_message, input_bfd, input_section,
252b5132 11542 rel->r_offset)))
b34976b6 11543 return FALSE;
252b5132
RH		 11544 break;
11545 }
11546 }
11547 }
11548
b34976b6 11549 return TRUE;
252b5132
RH		 11550}
11551
91d6fa6a 11552/* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
2468f9c9 11553 adds the edit to the start of the list. (The list must be built in order of
91d6fa6a 11554 ascending TINDEX: the function's callers are primarily responsible for
2468f9c9
PB		 11555 maintaining that condition). */
11556
11557static void
11558add_unwind_table_edit (arm_unwind_table_edit **head,
11559 arm_unwind_table_edit **tail,
11560 arm_unwind_edit_type type,
11561 asection *linked_section,
91d6fa6a 11562 unsigned int tindex)
2468f9c9 11563{
21d799b5
NC		 11564 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
11565 xmalloc (sizeof (arm_unwind_table_edit));
b38cadfb 11566
2468f9c9
PB		 11567 new_edit->type = type;
11568 new_edit->linked_section = linked_section;
91d6fa6a 11569 new_edit->index = tindex;
b38cadfb 11570
91d6fa6a 11571 if (tindex > 0)
2468f9c9
PB		 11572 {
11573 new_edit->next = NULL;
11574
11575 if (*tail)
11576 (*tail)->next = new_edit;
11577
11578 (*tail) = new_edit;
11579
11580 if (!*head)
11581 (*head) = new_edit;
11582 }
11583 else
11584 {
11585 new_edit->next = *head;
11586
11587 if (!*tail)
11588 *tail = new_edit;
11589
11590 *head = new_edit;
11591 }
11592}
11593
11594static _arm_elf_section_data *get_arm_elf_section_data (asection *);
11595
11596/* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
11597static void
11598adjust_exidx_size(asection *exidx_sec, int adjust)
11599{
11600 asection *out_sec;
11601
11602 if (!exidx_sec->rawsize)
11603 exidx_sec->rawsize = exidx_sec->size;
11604
11605 bfd_set_section_size (exidx_sec->owner, exidx_sec, exidx_sec->size + adjust);
11606 out_sec = exidx_sec->output_section;
11607 /* Adjust size of output section. */
11608 bfd_set_section_size (out_sec->owner, out_sec, out_sec->size +adjust);
11609}
11610
11611/* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
11612static void
11613insert_cantunwind_after(asection *text_sec, asection *exidx_sec)
11614{
11615 struct _arm_elf_section_data *exidx_arm_data;
11616
11617 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
11618 add_unwind_table_edit (
11619 &exidx_arm_data->u.exidx.unwind_edit_list,
11620 &exidx_arm_data->u.exidx.unwind_edit_tail,
11621 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
11622
491d01d3
YU		 11623 exidx_arm_data->additional_reloc_count++;
11624
2468f9c9
PB		 11625 adjust_exidx_size(exidx_sec, 8);
11626}
11627
11628/* Scan .ARM.exidx tables, and create a list describing edits which should be
11629 made to those tables, such that:
b38cadfb 11630
2468f9c9
PB		 11631 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
11632 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
99059e56 11633 codes which have been inlined into the index).
2468f9c9 11634
85fdf906
AH		 11635 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
11636
2468f9c9 11637 The edits are applied when the tables are written
b38cadfb 11638 (in elf32_arm_write_section). */
2468f9c9
PB		 11639
11640bfd_boolean
11641elf32_arm_fix_exidx_coverage (asection **text_section_order,
11642 unsigned int num_text_sections,
85fdf906
AH		 11643 struct bfd_link_info *info,
11644 bfd_boolean merge_exidx_entries)
2468f9c9
PB		 11645{
11646 bfd *inp;
11647 unsigned int last_second_word = 0, i;
11648 asection *last_exidx_sec = NULL;
11649 asection *last_text_sec = NULL;
11650 int last_unwind_type = -1;
11651
11652 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
11653 text sections. */
c72f2fb2 11654 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
2468f9c9
PB		 11655 {
11656 asection *sec;
b38cadfb 11657
2468f9c9 11658 for (sec = inp->sections; sec != NULL; sec = sec->next)
99059e56 11659 {
2468f9c9
PB		 11660 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
11661 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
b38cadfb 11662
dec9d5df 11663 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
2468f9c9 11664 continue;
b38cadfb 11665
2468f9c9
PB		 11666 if (elf_sec->linked_to)
11667 {
11668 Elf_Internal_Shdr *linked_hdr
99059e56 11669 = &elf_section_data (elf_sec->linked_to)->this_hdr;
2468f9c9 11670 struct _arm_elf_section_data *linked_sec_arm_data
99059e56 11671 = get_arm_elf_section_data (linked_hdr->bfd_section);
2468f9c9
PB		 11672
11673 if (linked_sec_arm_data == NULL)
99059e56 11674 continue;
2468f9c9
PB		 11675
11676 /* Link this .ARM.exidx section back from the text section it
99059e56 11677 describes. */
2468f9c9
PB		 11678 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
11679 }
11680 }
11681 }
11682
11683 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
11684 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
91d6fa6a 11685 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
2468f9c9
PB		 11686
11687 for (i = 0; i < num_text_sections; i++)
11688 {
11689 asection *sec = text_section_order[i];
11690 asection *exidx_sec;
11691 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
11692 struct _arm_elf_section_data *exidx_arm_data;
11693 bfd_byte *contents = NULL;
11694 int deleted_exidx_bytes = 0;
11695 bfd_vma j;
11696 arm_unwind_table_edit *unwind_edit_head = NULL;
11697 arm_unwind_table_edit *unwind_edit_tail = NULL;
11698 Elf_Internal_Shdr *hdr;
11699 bfd *ibfd;
11700
11701 if (arm_data == NULL)
99059e56 11702 continue;
2468f9c9
PB		 11703
11704 exidx_sec = arm_data->u.text.arm_exidx_sec;
11705 if (exidx_sec == NULL)
11706 {
11707 /* Section has no unwind data. */
11708 if (last_unwind_type == 0 || !last_exidx_sec)
11709 continue;
11710
11711 /* Ignore zero sized sections. */
11712 if (sec->size == 0)
11713 continue;
11714
11715 insert_cantunwind_after(last_text_sec, last_exidx_sec);
11716 last_unwind_type = 0;
11717 continue;
11718 }
11719
22a8f80e
PB		 11720 /* Skip /DISCARD/ sections. */
11721 if (bfd_is_abs_section (exidx_sec->output_section))
11722 continue;
11723
2468f9c9
PB		 11724 hdr = &elf_section_data (exidx_sec)->this_hdr;
11725 if (hdr->sh_type != SHT_ARM_EXIDX)
99059e56 11726 continue;
b38cadfb 11727
2468f9c9
PB		 11728 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
11729 if (exidx_arm_data == NULL)
99059e56 11730 continue;
b38cadfb 11731
2468f9c9 11732 ibfd = exidx_sec->owner;
b38cadfb 11733
2468f9c9
PB		 11734 if (hdr->contents != NULL)
11735 contents = hdr->contents;
11736 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
11737 /* An error? */
11738 continue;
11739
11740 for (j = 0; j < hdr->sh_size; j += 8)
11741 {
11742 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
11743 int unwind_type;
11744 int elide = 0;
11745
11746 /* An EXIDX_CANTUNWIND entry. */
11747 if (second_word == 1)
11748 {
11749 if (last_unwind_type == 0)
11750 elide = 1;
11751 unwind_type = 0;
11752 }
11753 /* Inlined unwinding data. Merge if equal to previous. */
11754 else if ((second_word & 0x80000000) != 0)
11755 {
85fdf906
AH		 11756 if (merge_exidx_entries
11757 && last_second_word == second_word && last_unwind_type == 1)
2468f9c9
PB		 11758 elide = 1;
11759 unwind_type = 1;
11760 last_second_word = second_word;
11761 }
11762 /* Normal table entry. In theory we could merge these too,
11763 but duplicate entries are likely to be much less common. */
11764 else
11765 unwind_type = 2;
11766
491d01d3 11767 if (elide && !bfd_link_relocatable (info))
2468f9c9
PB		 11768 {
11769 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
11770 DELETE_EXIDX_ENTRY, NULL, j / 8);
11771
11772 deleted_exidx_bytes += 8;
11773 }
11774
11775 last_unwind_type = unwind_type;
11776 }
11777
11778 /* Free contents if we allocated it ourselves. */
11779 if (contents != hdr->contents)
99059e56 11780 free (contents);
2468f9c9
PB		 11781
11782 /* Record edits to be applied later (in elf32_arm_write_section). */
11783 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
11784 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
b38cadfb 11785
2468f9c9
PB		 11786 if (deleted_exidx_bytes > 0)
11787 adjust_exidx_size(exidx_sec, -deleted_exidx_bytes);
11788
11789 last_exidx_sec = exidx_sec;
11790 last_text_sec = sec;
11791 }
11792
11793 /* Add terminating CANTUNWIND entry. */
491d01d3
YU		 11794 if (!bfd_link_relocatable (info) && last_exidx_sec
11795 && last_unwind_type != 0)
2468f9c9
PB		 11796 insert_cantunwind_after(last_text_sec, last_exidx_sec);
11797
11798 return TRUE;
11799}
11800
3e6b1042
DJ		 11801static bfd_boolean
11802elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
11803 bfd *ibfd, const char *name)
11804{
11805 asection *sec, *osec;
11806
3d4d4302 11807 sec = bfd_get_linker_section (ibfd, name);
3e6b1042
DJ		 11808 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
11809 return TRUE;
11810
11811 osec = sec->output_section;
11812 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
11813 return TRUE;
11814
11815 if (! bfd_set_section_contents (obfd, osec, sec->contents,
11816 sec->output_offset, sec->size))
11817 return FALSE;
11818
11819 return TRUE;
11820}
11821
11822static bfd_boolean
11823elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
11824{
11825 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
fe33d2fa 11826 asection *sec, *osec;
3e6b1042 11827
4dfe6ac6
NC		 11828 if (globals == NULL)
11829 return FALSE;
11830
3e6b1042
DJ		 11831 /* Invoke the regular ELF backend linker to do all the work. */
11832 if (!bfd_elf_final_link (abfd, info))
11833 return FALSE;
11834
fe33d2fa
CL		 11835 /* Process stub sections (eg BE8 encoding, ...). */
11836 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
7292b3ac 11837 unsigned int i;
cdb21a0a
NS		 11838 for (i=0; i<htab->top_id; i++)
11839 {
11840 sec = htab->stub_group[i].stub_sec;
11841 /* Only process it once, in its link_sec slot. */
11842 if (sec && i == htab->stub_group[i].link_sec->id)
11843 {
11844 osec = sec->output_section;
11845 elf32_arm_write_section (abfd, info, sec, sec->contents);
11846 if (! bfd_set_section_contents (abfd, osec, sec->contents,
11847 sec->output_offset, sec->size))
11848 return FALSE;
11849 }
fe33d2fa 11850 }
fe33d2fa 11851
3e6b1042
DJ		 11852 /* Write out any glue sections now that we have created all the
11853 stubs. */
11854 if (globals->bfd_of_glue_owner != NULL)
11855 {
11856 if (! elf32_arm_output_glue_section (info, abfd,
11857 globals->bfd_of_glue_owner,
11858 ARM2THUMB_GLUE_SECTION_NAME))
11859 return FALSE;
11860
11861 if (! elf32_arm_output_glue_section (info, abfd,
11862 globals->bfd_of_glue_owner,
11863 THUMB2ARM_GLUE_SECTION_NAME))
11864 return FALSE;
11865
11866 if (! elf32_arm_output_glue_section (info, abfd,
11867 globals->bfd_of_glue_owner,
11868 VFP11_ERRATUM_VENEER_SECTION_NAME))
11869 return FALSE;
11870
a504d23a
LA		 11871 if (! elf32_arm_output_glue_section (info, abfd,
11872 globals->bfd_of_glue_owner,
11873 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
11874 return FALSE;
11875
3e6b1042
DJ		 11876 if (! elf32_arm_output_glue_section (info, abfd,
11877 globals->bfd_of_glue_owner,
11878 ARM_BX_GLUE_SECTION_NAME))
11879 return FALSE;
11880 }
11881
11882 return TRUE;
11883}
11884
5968a7b8
NC		 11885/* Return a best guess for the machine number based on the attributes. */
11886
11887static unsigned int
11888bfd_arm_get_mach_from_attributes (bfd * abfd)
11889{
11890 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
11891
11892 switch (arch)
11893 {
11894 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
11895 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
11896 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
11897
11898 case TAG_CPU_ARCH_V5TE:
11899 {
11900 char * name;
11901
11902 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
11903 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
11904
11905 if (name)
11906 {
11907 if (strcmp (name, "IWMMXT2") == 0)
11908 return bfd_mach_arm_iWMMXt2;
11909
11910 if (strcmp (name, "IWMMXT") == 0)
6034aab8 11911 return bfd_mach_arm_iWMMXt;
088ca6c1
NC		 11912
11913 if (strcmp (name, "XSCALE") == 0)
11914 {
11915 int wmmx;
11916
11917 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
11918 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
11919 switch (wmmx)
11920 {
11921 case 1: return bfd_mach_arm_iWMMXt;
11922 case 2: return bfd_mach_arm_iWMMXt2;
11923 default: return bfd_mach_arm_XScale;
11924 }
11925 }
5968a7b8
NC		 11926 }
11927
11928 return bfd_mach_arm_5TE;
11929 }
11930
11931 default:
11932 return bfd_mach_arm_unknown;
11933 }
11934}
11935
c178919b
NC		 11936/* Set the right machine number. */
11937
11938static bfd_boolean
57e8b36a 11939elf32_arm_object_p (bfd *abfd)
c178919b 11940{
5a6c6817 11941 unsigned int mach;
57e8b36a 11942
5a6c6817 11943 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
c178919b 11944
5968a7b8
NC		 11945 if (mach == bfd_mach_arm_unknown)
11946 {
11947 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
11948 mach = bfd_mach_arm_ep9312;
11949 else
11950 mach = bfd_arm_get_mach_from_attributes (abfd);
11951 }
c178919b 11952
5968a7b8 11953 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
c178919b
NC		 11954 return TRUE;
11955}
11956
fc830a83 11957/* Function to keep ARM specific flags in the ELF header. */
3c9458e9 11958
b34976b6 11959static bfd_boolean
57e8b36a 11960elf32_arm_set_private_flags (bfd *abfd, flagword flags)
252b5132
RH		 11961{
11962 if (elf_flags_init (abfd)
11963 && elf_elfheader (abfd)->e_flags != flags)
11964 {
fc830a83
NC		 11965 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
11966 {
fd2ec330 11967 if (flags & EF_ARM_INTERWORK)
d003868e
AM		 11968 (*_bfd_error_handler)
11969 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
11970 abfd);
fc830a83 11971 else
d003868e
AM		 11972 _bfd_error_handler
11973 (_("Warning: Clearing the interworking flag of %B due to outside request"),
11974 abfd);
fc830a83 11975 }
252b5132
RH		 11976 }
11977 else
11978 {
11979 elf_elfheader (abfd)->e_flags = flags;
b34976b6 11980 elf_flags_init (abfd) = TRUE;
252b5132
RH		 11981 }
11982
b34976b6 11983 return TRUE;
252b5132
RH		 11984}
11985
fc830a83 11986/* Copy backend specific data from one object module to another. */
9b485d32 11987
b34976b6 11988static bfd_boolean
57e8b36a 11989elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
252b5132
RH		 11990{
11991 flagword in_flags;
11992 flagword out_flags;
11993
0ffa91dd 11994 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
b34976b6 11995 return TRUE;
252b5132 11996
fc830a83 11997 in_flags = elf_elfheader (ibfd)->e_flags;
252b5132
RH		 11998 out_flags = elf_elfheader (obfd)->e_flags;
11999
fc830a83
NC		 12000 if (elf_flags_init (obfd)
12001 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
12002 && in_flags != out_flags)
252b5132 12003 {
252b5132 12004 /* Cannot mix APCS26 and APCS32 code. */
fd2ec330 12005 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
b34976b6 12006 return FALSE;
252b5132
RH		 12007
12008 /* Cannot mix float APCS and non-float APCS code. */
fd2ec330 12009 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
b34976b6 12010 return FALSE;
252b5132
RH		 12011
12012 /* If the src and dest have different interworking flags
99059e56 12013 then turn off the interworking bit. */
fd2ec330 12014 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
252b5132 12015 {
fd2ec330 12016 if (out_flags & EF_ARM_INTERWORK)
d003868e
AM		 12017 _bfd_error_handler
12018 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
12019 obfd, ibfd);
252b5132 12020
fd2ec330 12021 in_flags &= ~EF_ARM_INTERWORK;
252b5132 12022 }
1006ba19
PB		 12023
12024 /* Likewise for PIC, though don't warn for this case. */
fd2ec330
PB		 12025 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
12026 in_flags &= ~EF_ARM_PIC;
252b5132
RH		 12027 }
12028
12029 elf_elfheader (obfd)->e_flags = in_flags;
b34976b6 12030 elf_flags_init (obfd) = TRUE;
252b5132 12031
e2349352 12032 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
ee065d83
PB		 12033}
12034
12035/* Values for Tag_ABI_PCS_R9_use. */
12036enum
12037{
12038 AEABI_R9_V6,
12039 AEABI_R9_SB,
12040 AEABI_R9_TLS,
12041 AEABI_R9_unused
12042};
12043
12044/* Values for Tag_ABI_PCS_RW_data. */
12045enum
12046{
12047 AEABI_PCS_RW_data_absolute,
12048 AEABI_PCS_RW_data_PCrel,
12049 AEABI_PCS_RW_data_SBrel,
12050 AEABI_PCS_RW_data_unused
12051};
12052
12053/* Values for Tag_ABI_enum_size. */
12054enum
12055{
12056 AEABI_enum_unused,
12057 AEABI_enum_short,
12058 AEABI_enum_wide,
12059 AEABI_enum_forced_wide
12060};
12061
104d59d1
JM		 12062/* Determine whether an object attribute tag takes an integer, a
12063 string or both. */
906e58ca 12064
104d59d1
JM		 12065static int
12066elf32_arm_obj_attrs_arg_type (int tag)
12067{
12068 if (tag == Tag_compatibility)
3483fe2e 12069 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2d0bb761 12070 else if (tag == Tag_nodefaults)
3483fe2e
AS		 12071 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
12072 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
12073 return ATTR_TYPE_FLAG_STR_VAL;
104d59d1 12074 else if (tag < 32)
3483fe2e 12075 return ATTR_TYPE_FLAG_INT_VAL;
104d59d1 12076 else
3483fe2e 12077 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
104d59d1
JM		 12078}
12079
5aa6ff7c
AS		 12080/* The ABI defines that Tag_conformance should be emitted first, and that
12081 Tag_nodefaults should be second (if either is defined). This sets those
12082 two positions, and bumps up the position of all the remaining tags to
12083 compensate. */
12084static int
12085elf32_arm_obj_attrs_order (int num)
12086{
3de4a297 12087 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
5aa6ff7c 12088 return Tag_conformance;
3de4a297 12089 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
5aa6ff7c
AS		 12090 return Tag_nodefaults;
12091 if ((num - 2) < Tag_nodefaults)
12092 return num - 2;
12093 if ((num - 1) < Tag_conformance)
12094 return num - 1;
12095 return num;
12096}
12097
e8b36cd1
JM		 12098/* Attribute numbers >=64 (mod 128) can be safely ignored. */
12099static bfd_boolean
12100elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
12101{
12102 if ((tag & 127) < 64)
12103 {
12104 _bfd_error_handler
12105 (_("%B: Unknown mandatory EABI object attribute %d"),
12106 abfd, tag);
12107 bfd_set_error (bfd_error_bad_value);
12108 return FALSE;
12109 }
12110 else
12111 {
12112 _bfd_error_handler
12113 (_("Warning: %B: Unknown EABI object attribute %d"),
12114 abfd, tag);
12115 return TRUE;
12116 }
12117}
12118
91e22acd
AS		 12119/* Read the architecture from the Tag_also_compatible_with attribute, if any.
12120 Returns -1 if no architecture could be read. */
12121
12122static int
12123get_secondary_compatible_arch (bfd *abfd)
12124{
12125 obj_attribute *attr =
12126 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
12127
12128 /* Note: the tag and its argument below are uleb128 values, though
12129 currently-defined values fit in one byte for each. */
12130 if (attr->s
12131 && attr->s[0] == Tag_CPU_arch
12132 && (attr->s[1] & 128) != 128
12133 && attr->s[2] == 0)
12134 return attr->s[1];
12135
12136 /* This tag is "safely ignorable", so don't complain if it looks funny. */
12137 return -1;
12138}
12139
12140/* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
12141 The tag is removed if ARCH is -1. */
12142
8e79c3df 12143static void
91e22acd 12144set_secondary_compatible_arch (bfd *abfd, int arch)
8e79c3df 12145{
91e22acd
AS		 12146 obj_attribute *attr =
12147 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
8e79c3df 12148
91e22acd
AS		 12149 if (arch == -1)
12150 {
12151 attr->s = NULL;
12152 return;
8e79c3df 12153 }
91e22acd
AS		 12154
12155 /* Note: the tag and its argument below are uleb128 values, though
12156 currently-defined values fit in one byte for each. */
12157 if (!attr->s)
21d799b5 12158 attr->s = (char *) bfd_alloc (abfd, 3);
91e22acd
AS		 12159 attr->s[0] = Tag_CPU_arch;
12160 attr->s[1] = arch;
12161 attr->s[2] = '\0';
8e79c3df
CM		 12162}
12163
91e22acd
AS		 12164/* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
12165 into account. */
12166
12167static int
12168tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
12169 int newtag, int secondary_compat)
8e79c3df 12170{
91e22acd
AS		 12171#define T(X) TAG_CPU_ARCH_##X
12172 int tagl, tagh, result;
12173 const int v6t2[] =
12174 {
12175 T(V6T2), /* PRE_V4. */
12176 T(V6T2), /* V4. */
12177 T(V6T2), /* V4T. */
12178 T(V6T2), /* V5T. */
12179 T(V6T2), /* V5TE. */
12180 T(V6T2), /* V5TEJ. */
12181 T(V6T2), /* V6. */
12182 T(V7), /* V6KZ. */
12183 T(V6T2) /* V6T2. */
12184 };
12185 const int v6k[] =
12186 {
12187 T(V6K), /* PRE_V4. */
12188 T(V6K), /* V4. */
12189 T(V6K), /* V4T. */
12190 T(V6K), /* V5T. */
12191 T(V6K), /* V5TE. */
12192 T(V6K), /* V5TEJ. */
12193 T(V6K), /* V6. */
12194 T(V6KZ), /* V6KZ. */
12195 T(V7), /* V6T2. */
12196 T(V6K) /* V6K. */
12197 };
12198 const int v7[] =
12199 {
12200 T(V7), /* PRE_V4. */
12201 T(V7), /* V4. */
12202 T(V7), /* V4T. */
12203 T(V7), /* V5T. */
12204 T(V7), /* V5TE. */
12205 T(V7), /* V5TEJ. */
12206 T(V7), /* V6. */
12207 T(V7), /* V6KZ. */
12208 T(V7), /* V6T2. */
12209 T(V7), /* V6K. */
12210 T(V7) /* V7. */
12211 };
12212 const int v6_m[] =
12213 {
12214 -1, /* PRE_V4. */
12215 -1, /* V4. */
12216 T(V6K), /* V4T. */
12217 T(V6K), /* V5T. */
12218 T(V6K), /* V5TE. */
12219 T(V6K), /* V5TEJ. */
12220 T(V6K), /* V6. */
12221 T(V6KZ), /* V6KZ. */
12222 T(V7), /* V6T2. */
12223 T(V6K), /* V6K. */
12224 T(V7), /* V7. */
12225 T(V6_M) /* V6_M. */
12226 };
12227 const int v6s_m[] =
12228 {
12229 -1, /* PRE_V4. */
12230 -1, /* V4. */
12231 T(V6K), /* V4T. */
12232 T(V6K), /* V5T. */
12233 T(V6K), /* V5TE. */
12234 T(V6K), /* V5TEJ. */
12235 T(V6K), /* V6. */
12236 T(V6KZ), /* V6KZ. */
12237 T(V7), /* V6T2. */
12238 T(V6K), /* V6K. */
12239 T(V7), /* V7. */
12240 T(V6S_M), /* V6_M. */
12241 T(V6S_M) /* V6S_M. */
12242 };
9e3c6df6
PB		 12243 const int v7e_m[] =
12244 {
12245 -1, /* PRE_V4. */
12246 -1, /* V4. */
12247 T(V7E_M), /* V4T. */
12248 T(V7E_M), /* V5T. */
12249 T(V7E_M), /* V5TE. */
12250 T(V7E_M), /* V5TEJ. */
12251 T(V7E_M), /* V6. */
12252 T(V7E_M), /* V6KZ. */
12253 T(V7E_M), /* V6T2. */
12254 T(V7E_M), /* V6K. */
12255 T(V7E_M), /* V7. */
12256 T(V7E_M), /* V6_M. */
12257 T(V7E_M), /* V6S_M. */
12258 T(V7E_M) /* V7E_M. */
12259 };
bca38921
MGD		 12260 const int v8[] =
12261 {
12262 T(V8), /* PRE_V4. */
12263 T(V8), /* V4. */
12264 T(V8), /* V4T. */
12265 T(V8), /* V5T. */
12266 T(V8), /* V5TE. */
12267 T(V8), /* V5TEJ. */
12268 T(V8), /* V6. */
12269 T(V8), /* V6KZ. */
12270 T(V8), /* V6T2. */
12271 T(V8), /* V6K. */
12272 T(V8), /* V7. */
12273 T(V8), /* V6_M. */
12274 T(V8), /* V6S_M. */
12275 T(V8), /* V7E_M. */
12276 T(V8) /* V8. */
12277 };
91e22acd
AS		 12278 const int v4t_plus_v6_m[] =
12279 {
12280 -1, /* PRE_V4. */
12281 -1, /* V4. */
12282 T(V4T), /* V4T. */
12283 T(V5T), /* V5T. */
12284 T(V5TE), /* V5TE. */
12285 T(V5TEJ), /* V5TEJ. */
12286 T(V6), /* V6. */
12287 T(V6KZ), /* V6KZ. */
12288 T(V6T2), /* V6T2. */
12289 T(V6K), /* V6K. */
12290 T(V7), /* V7. */
12291 T(V6_M), /* V6_M. */
12292 T(V6S_M), /* V6S_M. */
9e3c6df6 12293 T(V7E_M), /* V7E_M. */
bca38921 12294 T(V8), /* V8. */
91e22acd
AS		 12295 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
12296 };
12297 const int *comb[] =
12298 {
12299 v6t2,
12300 v6k,
12301 v7,
12302 v6_m,
12303 v6s_m,
9e3c6df6 12304 v7e_m,
bca38921 12305 v8,
91e22acd
AS		 12306 /* Pseudo-architecture. */
12307 v4t_plus_v6_m
12308 };
12309
12310 /* Check we've not got a higher architecture than we know about. */
12311
9e3c6df6 12312 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
91e22acd 12313 {
3895f852 12314 _bfd_error_handler (_("error: %B: Unknown CPU architecture"), ibfd);
91e22acd
AS		 12315 return -1;
12316 }
12317
12318 /* Override old tag if we have a Tag_also_compatible_with on the output. */
12319
12320 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
12321 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
12322 oldtag = T(V4T_PLUS_V6_M);
12323
12324 /* And override the new tag if we have a Tag_also_compatible_with on the
12325 input. */
12326
12327 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
12328 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
12329 newtag = T(V4T_PLUS_V6_M);
12330
12331 tagl = (oldtag < newtag) ? oldtag : newtag;
12332 result = tagh = (oldtag > newtag) ? oldtag : newtag;
12333
12334 /* Architectures before V6KZ add features monotonically. */
12335 if (tagh <= TAG_CPU_ARCH_V6KZ)
12336 return result;
12337
12338 result = comb[tagh - T(V6T2)][tagl];
12339
12340 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
12341 as the canonical version. */
12342 if (result == T(V4T_PLUS_V6_M))
12343 {
12344 result = T(V4T);
12345 *secondary_compat_out = T(V6_M);
12346 }
12347 else
12348 *secondary_compat_out = -1;
12349
12350 if (result == -1)
12351 {
3895f852 12352 _bfd_error_handler (_("error: %B: Conflicting CPU architectures %d/%d"),
91e22acd
AS		 12353 ibfd, oldtag, newtag);
12354 return -1;
12355 }
12356
12357 return result;
12358#undef T
8e79c3df
CM		 12359}
12360
ac56ee8f
MGD		 12361/* Query attributes object to see if integer divide instructions may be
12362 present in an object. */
12363static bfd_boolean
12364elf32_arm_attributes_accept_div (const obj_attribute *attr)
12365{
12366 int arch = attr[Tag_CPU_arch].i;
12367 int profile = attr[Tag_CPU_arch_profile].i;
12368
12369 switch (attr[Tag_DIV_use].i)
12370 {
12371 case 0:
12372 /* Integer divide allowed if instruction contained in archetecture. */
12373 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
12374 return TRUE;
12375 else if (arch >= TAG_CPU_ARCH_V7E_M)
12376 return TRUE;
12377 else
12378 return FALSE;
12379
12380 case 1:
12381 /* Integer divide explicitly prohibited. */
12382 return FALSE;
12383
12384 default:
12385 /* Unrecognised case - treat as allowing divide everywhere. */
12386 case 2:
12387 /* Integer divide allowed in ARM state. */
12388 return TRUE;
12389 }
12390}
12391
12392/* Query attributes object to see if integer divide instructions are
12393 forbidden to be in the object. This is not the inverse of
12394 elf32_arm_attributes_accept_div. */
12395static bfd_boolean
12396elf32_arm_attributes_forbid_div (const obj_attribute *attr)
12397{
12398 return attr[Tag_DIV_use].i == 1;
12399}
12400
ee065d83
PB		 12401/* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
12402 are conflicting attributes. */
906e58ca 12403
ee065d83
PB		 12404static bfd_boolean
12405elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd)
12406{
104d59d1
JM		 12407 obj_attribute *in_attr;
12408 obj_attribute *out_attr;
ee065d83
PB		 12409 /* Some tags have 0 = don't care, 1 = strong requirement,
12410 2 = weak requirement. */
91e22acd 12411 static const int order_021[3] = {0, 2, 1};
ee065d83 12412 int i;
91e22acd 12413 bfd_boolean result = TRUE;
9274e9de 12414 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
ee065d83 12415
3e6b1042
DJ		 12416 /* Skip the linker stubs file. This preserves previous behavior
12417 of accepting unknown attributes in the first input file - but
12418 is that a bug? */
12419 if (ibfd->flags & BFD_LINKER_CREATED)
12420 return TRUE;
12421
9274e9de
TG		 12422 /* Skip any input that hasn't attribute section.
12423 This enables to link object files without attribute section with
12424 any others. */
12425 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
12426 return TRUE;
12427
104d59d1 12428 if (!elf_known_obj_attributes_proc (obfd)[0].i)
ee065d83
PB		 12429 {
12430 /* This is the first object. Copy the attributes. */
104d59d1 12431 _bfd_elf_copy_obj_attributes (ibfd, obfd);
004ae526 12432
cd21e546
MGD		 12433 out_attr = elf_known_obj_attributes_proc (obfd);
12434
004ae526
PB		 12435 /* Use the Tag_null value to indicate the attributes have been
12436 initialized. */
cd21e546 12437 out_attr[0].i = 1;
004ae526 12438
cd21e546
MGD		 12439 /* We do not output objects with Tag_MPextension_use_legacy - we move
12440 the attribute's value to Tag_MPextension_use. */
12441 if (out_attr[Tag_MPextension_use_legacy].i != 0)
12442 {
12443 if (out_attr[Tag_MPextension_use].i != 0
12444 && out_attr[Tag_MPextension_use_legacy].i
99059e56 12445 != out_attr[Tag_MPextension_use].i)
cd21e546
MGD		 12446 {
12447 _bfd_error_handler
12448 (_("Error: %B has both the current and legacy "
12449 "Tag_MPextension_use attributes"), ibfd);
12450 result = FALSE;
12451 }
12452
12453 out_attr[Tag_MPextension_use] =
12454 out_attr[Tag_MPextension_use_legacy];
12455 out_attr[Tag_MPextension_use_legacy].type = 0;
12456 out_attr[Tag_MPextension_use_legacy].i = 0;
12457 }
12458
12459 return result;
ee065d83
PB		 12460 }
12461
104d59d1
JM		 12462 in_attr = elf_known_obj_attributes_proc (ibfd);
12463 out_attr = elf_known_obj_attributes_proc (obfd);
ee065d83
PB		 12464 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
12465 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
12466 {
5c294fee
TG		 12467 /* Ignore mismatches if the object doesn't use floating point or is
12468 floating point ABI independent. */
12469 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
12470 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
12471 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
ee065d83 12472 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
5c294fee
TG		 12473 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
12474 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
ee065d83
PB		 12475 {
12476 _bfd_error_handler
3895f852 12477 (_("error: %B uses VFP register arguments, %B does not"),
deddc40b
NS		 12478 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
12479 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
91e22acd 12480 result = FALSE;
ee065d83
PB		 12481 }
12482 }
12483
3de4a297 12484 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
ee065d83
PB		 12485 {
12486 /* Merge this attribute with existing attributes. */
12487 switch (i)
12488 {
12489 case Tag_CPU_raw_name:
12490 case Tag_CPU_name:
6a631e86 12491 /* These are merged after Tag_CPU_arch. */
ee065d83
PB		 12492 break;
12493
12494 case Tag_ABI_optimization_goals:
12495 case Tag_ABI_FP_optimization_goals:
12496 /* Use the first value seen. */
12497 break;
12498
12499 case Tag_CPU_arch:
91e22acd
AS		 12500 {
12501 int secondary_compat = -1, secondary_compat_out = -1;
12502 unsigned int saved_out_attr = out_attr[i].i;
70e99720
TG		 12503 int arch_attr;
12504 static const char *name_table[] =
12505 {
91e22acd
AS		 12506 /* These aren't real CPU names, but we can't guess
12507 that from the architecture version alone. */
12508 "Pre v4",
12509 "ARM v4",
12510 "ARM v4T",
12511 "ARM v5T",
12512 "ARM v5TE",
12513 "ARM v5TEJ",
12514 "ARM v6",
12515 "ARM v6KZ",
12516 "ARM v6T2",
12517 "ARM v6K",
12518 "ARM v7",
12519 "ARM v6-M",
bca38921
MGD		 12520 "ARM v6S-M",
12521 "ARM v8"
91e22acd
AS		 12522 };
12523
12524 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
12525 secondary_compat = get_secondary_compatible_arch (ibfd);
12526 secondary_compat_out = get_secondary_compatible_arch (obfd);
70e99720
TG		 12527 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
12528 &secondary_compat_out,
12529 in_attr[i].i,
12530 secondary_compat);
12531
12532 /* Return with error if failed to merge. */
12533 if (arch_attr == -1)
12534 return FALSE;
12535
12536 out_attr[i].i = arch_attr;
12537
91e22acd
AS		 12538 set_secondary_compatible_arch (obfd, secondary_compat_out);
12539
12540 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
12541 if (out_attr[i].i == saved_out_attr)
12542 ; /* Leave the names alone. */
12543 else if (out_attr[i].i == in_attr[i].i)
12544 {
12545 /* The output architecture has been changed to match the
12546 input architecture. Use the input names. */
12547 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
12548 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
12549 : NULL;
12550 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
12551 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
12552 : NULL;
12553 }
12554 else
12555 {
12556 out_attr[Tag_CPU_name].s = NULL;
12557 out_attr[Tag_CPU_raw_name].s = NULL;
12558 }
12559
12560 /* If we still don't have a value for Tag_CPU_name,
12561 make one up now. Tag_CPU_raw_name remains blank. */
12562 if (out_attr[Tag_CPU_name].s == NULL
12563 && out_attr[i].i < ARRAY_SIZE (name_table))
12564 out_attr[Tag_CPU_name].s =
12565 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
12566 }
12567 break;
12568
ee065d83
PB		 12569 case Tag_ARM_ISA_use:
12570 case Tag_THUMB_ISA_use:
ee065d83 12571 case Tag_WMMX_arch:
91e22acd
AS		 12572 case Tag_Advanced_SIMD_arch:
12573 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
ee065d83 12574 case Tag_ABI_FP_rounding:
ee065d83
PB		 12575 case Tag_ABI_FP_exceptions:
12576 case Tag_ABI_FP_user_exceptions:
12577 case Tag_ABI_FP_number_model:
75375b3e 12578 case Tag_FP_HP_extension:
91e22acd
AS		 12579 case Tag_CPU_unaligned_access:
12580 case Tag_T2EE_use:
91e22acd 12581 case Tag_MPextension_use:
ee065d83
PB		 12582 /* Use the largest value specified. */
12583 if (in_attr[i].i > out_attr[i].i)
12584 out_attr[i].i = in_attr[i].i;
12585 break;
12586
75375b3e 12587 case Tag_ABI_align_preserved:
91e22acd
AS		 12588 case Tag_ABI_PCS_RO_data:
12589 /* Use the smallest value specified. */
12590 if (in_attr[i].i < out_attr[i].i)
12591 out_attr[i].i = in_attr[i].i;
12592 break;
12593
75375b3e 12594 case Tag_ABI_align_needed:
91e22acd 12595 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
75375b3e
MGD		 12596 && (in_attr[Tag_ABI_align_preserved].i == 0
12597 || out_attr[Tag_ABI_align_preserved].i == 0))
ee065d83 12598 {
91e22acd
AS		 12599 /* This error message should be enabled once all non-conformant
12600 binaries in the toolchain have had the attributes set
12601 properly.
ee065d83 12602 _bfd_error_handler
3895f852 12603 (_("error: %B: 8-byte data alignment conflicts with %B"),
91e22acd
AS		 12604 obfd, ibfd);
12605 result = FALSE; */
ee065d83 12606 }
91e22acd
AS		 12607 /* Fall through. */
12608 case Tag_ABI_FP_denormal:
12609 case Tag_ABI_PCS_GOT_use:
12610 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
12611 value if greater than 2 (for future-proofing). */
12612 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
12613 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
12614 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
ee065d83
PB		 12615 out_attr[i].i = in_attr[i].i;
12616 break;
91e22acd 12617
75375b3e
MGD		 12618 case Tag_Virtualization_use:
12619 /* The virtualization tag effectively stores two bits of
12620 information: the intended use of TrustZone (in bit 0), and the
12621 intended use of Virtualization (in bit 1). */
12622 if (out_attr[i].i == 0)
12623 out_attr[i].i = in_attr[i].i;
12624 else if (in_attr[i].i != 0
12625 && in_attr[i].i != out_attr[i].i)
12626 {
12627 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
12628 out_attr[i].i = 3;
12629 else
12630 {
12631 _bfd_error_handler
12632 (_("error: %B: unable to merge virtualization attributes "
12633 "with %B"),
12634 obfd, ibfd);
12635 result = FALSE;
12636 }
12637 }
12638 break;
91e22acd
AS		 12639
12640 case Tag_CPU_arch_profile:
12641 if (out_attr[i].i != in_attr[i].i)
12642 {
12643 /* 0 will merge with anything.
12644 'A' and 'S' merge to 'A'.
12645 'R' and 'S' merge to 'R'.
99059e56 12646 'M' and 'A|R|S' is an error. */
91e22acd
AS		 12647 if (out_attr[i].i == 0
12648 || (out_attr[i].i == 'S'
12649 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
12650 out_attr[i].i = in_attr[i].i;
12651 else if (in_attr[i].i == 0
12652 || (in_attr[i].i == 'S'
12653 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
6a631e86 12654 ; /* Do nothing. */
91e22acd
AS		 12655 else
12656 {
12657 _bfd_error_handler
3895f852 12658 (_("error: %B: Conflicting architecture profiles %c/%c"),
91e22acd
AS		 12659 ibfd,
12660 in_attr[i].i ? in_attr[i].i : '0',
12661 out_attr[i].i ? out_attr[i].i : '0');
12662 result = FALSE;
12663 }
12664 }
12665 break;
75375b3e 12666 case Tag_FP_arch:
62f3b8c8 12667 {
4547cb56
NC		 12668 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
12669 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
12670 when it's 0. It might mean absence of FP hardware if
99654aaf 12671 Tag_FP_arch is zero. */
4547cb56 12672
a715796b 12673#define VFP_VERSION_COUNT 9
62f3b8c8
PB		 12674 static const struct
12675 {
12676 int ver;
12677 int regs;
bca38921 12678 } vfp_versions[VFP_VERSION_COUNT] =
62f3b8c8
PB		 12679 {
12680 {0, 0},
12681 {1, 16},
12682 {2, 16},
12683 {3, 32},
12684 {3, 16},
12685 {4, 32},
bca38921 12686 {4, 16},
a715796b
TG		 12687 {8, 32},
12688 {8, 16}
62f3b8c8
PB		 12689 };
12690 int ver;
12691 int regs;
12692 int newval;
12693
4547cb56
NC		 12694 /* If the output has no requirement about FP hardware,
12695 follow the requirement of the input. */
12696 if (out_attr[i].i == 0)
12697 {
12698 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
12699 out_attr[i].i = in_attr[i].i;
12700 out_attr[Tag_ABI_HardFP_use].i
12701 = in_attr[Tag_ABI_HardFP_use].i;
12702 break;
12703 }
12704 /* If the input has no requirement about FP hardware, do
12705 nothing. */
12706 else if (in_attr[i].i == 0)
12707 {
12708 BFD_ASSERT (in_attr[Tag_ABI_HardFP_use].i == 0);
12709 break;
12710 }
12711
12712 /* Both the input and the output have nonzero Tag_FP_arch.
99654aaf 12713 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
4547cb56
NC		 12714
12715 /* If both the input and the output have zero Tag_ABI_HardFP_use,
12716 do nothing. */
12717 if (in_attr[Tag_ABI_HardFP_use].i == 0
12718 && out_attr[Tag_ABI_HardFP_use].i == 0)
12719 ;
12720 /* If the input and the output have different Tag_ABI_HardFP_use,
99654aaf 12721 the combination of them is 0 (implied by Tag_FP_arch). */
4547cb56
NC		 12722 else if (in_attr[Tag_ABI_HardFP_use].i
12723 != out_attr[Tag_ABI_HardFP_use].i)
99654aaf 12724 out_attr[Tag_ABI_HardFP_use].i = 0;
4547cb56
NC		 12725
12726 /* Now we can handle Tag_FP_arch. */
12727
bca38921
MGD		 12728 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
12729 pick the biggest. */
12730 if (in_attr[i].i >= VFP_VERSION_COUNT
12731 && in_attr[i].i > out_attr[i].i)
62f3b8c8
PB		 12732 {
12733 out_attr[i] = in_attr[i];
12734 break;
12735 }
12736 /* The output uses the superset of input features
12737 (ISA version) and registers. */
12738 ver = vfp_versions[in_attr[i].i].ver;
12739 if (ver < vfp_versions[out_attr[i].i].ver)
12740 ver = vfp_versions[out_attr[i].i].ver;
12741 regs = vfp_versions[in_attr[i].i].regs;
12742 if (regs < vfp_versions[out_attr[i].i].regs)
12743 regs = vfp_versions[out_attr[i].i].regs;
12744 /* This assumes all possible supersets are also a valid
99059e56 12745 options. */
bca38921 12746 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
62f3b8c8
PB		 12747 {
12748 if (regs == vfp_versions[newval].regs
12749 && ver == vfp_versions[newval].ver)
12750 break;
12751 }
12752 out_attr[i].i = newval;
12753 }
b1cc4aeb 12754 break;
ee065d83
PB		 12755 case Tag_PCS_config:
12756 if (out_attr[i].i == 0)
12757 out_attr[i].i = in_attr[i].i;
b6009aca 12758 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
ee065d83
PB		 12759 {
12760 /* It's sometimes ok to mix different configs, so this is only
99059e56 12761 a warning. */
ee065d83
PB		 12762 _bfd_error_handler
12763 (_("Warning: %B: Conflicting platform configuration"), ibfd);
12764 }
12765 break;
12766 case Tag_ABI_PCS_R9_use:
004ae526
PB		 12767 if (in_attr[i].i != out_attr[i].i
12768 && out_attr[i].i != AEABI_R9_unused
ee065d83
PB		 12769 && in_attr[i].i != AEABI_R9_unused)
12770 {
12771 _bfd_error_handler
3895f852 12772 (_("error: %B: Conflicting use of R9"), ibfd);
91e22acd 12773 result = FALSE;
ee065d83
PB		 12774 }
12775 if (out_attr[i].i == AEABI_R9_unused)
12776 out_attr[i].i = in_attr[i].i;
12777 break;
12778 case Tag_ABI_PCS_RW_data:
12779 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
12780 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
12781 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
12782 {
12783 _bfd_error_handler
3895f852 12784 (_("error: %B: SB relative addressing conflicts with use of R9"),
ee065d83 12785 ibfd);
91e22acd 12786 result = FALSE;
ee065d83
PB		 12787 }
12788 /* Use the smallest value specified. */
12789 if (in_attr[i].i < out_attr[i].i)
12790 out_attr[i].i = in_attr[i].i;
12791 break;
ee065d83 12792 case Tag_ABI_PCS_wchar_t:
a9dc9481
JM		 12793 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
12794 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
ee065d83
PB		 12795 {
12796 _bfd_error_handler
a9dc9481
JM		 12797 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
12798 ibfd, in_attr[i].i, out_attr[i].i);
ee065d83 12799 }
a9dc9481 12800 else if (in_attr[i].i && !out_attr[i].i)
ee065d83
PB		 12801 out_attr[i].i = in_attr[i].i;
12802 break;
ee065d83
PB		 12803 case Tag_ABI_enum_size:
12804 if (in_attr[i].i != AEABI_enum_unused)
12805 {
12806 if (out_attr[i].i == AEABI_enum_unused
12807 || out_attr[i].i == AEABI_enum_forced_wide)
12808 {
12809 /* The existing object is compatible with anything.
12810 Use whatever requirements the new object has. */
12811 out_attr[i].i = in_attr[i].i;
12812 }
12813 else if (in_attr[i].i != AEABI_enum_forced_wide
bf21ed78 12814 && out_attr[i].i != in_attr[i].i
0ffa91dd 12815 && !elf_arm_tdata (obfd)->no_enum_size_warning)
ee065d83 12816 {
91e22acd 12817 static const char *aeabi_enum_names[] =
bf21ed78 12818 { "", "variable-size", "32-bit", "" };
91e22acd
AS		 12819 const char *in_name =
12820 in_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
12821 ? aeabi_enum_names[in_attr[i].i]
12822 : "<unknown>";
12823 const char *out_name =
12824 out_attr[i].i < ARRAY_SIZE(aeabi_enum_names)
12825 ? aeabi_enum_names[out_attr[i].i]
12826 : "<unknown>";
ee065d83 12827 _bfd_error_handler
bf21ed78 12828 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
91e22acd 12829 ibfd, in_name, out_name);
ee065d83
PB		 12830 }
12831 }
12832 break;
12833 case Tag_ABI_VFP_args:
12834 /* Aready done. */
12835 break;
12836 case Tag_ABI_WMMX_args:
12837 if (in_attr[i].i != out_attr[i].i)
12838 {
12839 _bfd_error_handler
3895f852 12840 (_("error: %B uses iWMMXt register arguments, %B does not"),
ee065d83 12841 ibfd, obfd);
91e22acd 12842 result = FALSE;
ee065d83
PB		 12843 }
12844 break;
7b86a9fa
AS		 12845 case Tag_compatibility:
12846 /* Merged in target-independent code. */
12847 break;
91e22acd 12848 case Tag_ABI_HardFP_use:
4547cb56 12849 /* This is handled along with Tag_FP_arch. */
91e22acd
AS		 12850 break;
12851 case Tag_ABI_FP_16bit_format:
12852 if (in_attr[i].i != 0 && out_attr[i].i != 0)
12853 {
12854 if (in_attr[i].i != out_attr[i].i)
12855 {
12856 _bfd_error_handler
3895f852 12857 (_("error: fp16 format mismatch between %B and %B"),
91e22acd
AS		 12858 ibfd, obfd);
12859 result = FALSE;
12860 }
12861 }
12862 if (in_attr[i].i != 0)
12863 out_attr[i].i = in_attr[i].i;
12864 break;
7b86a9fa 12865
cd21e546 12866 case Tag_DIV_use:
ac56ee8f
MGD		 12867 /* A value of zero on input means that the divide instruction may
12868 be used if available in the base architecture as specified via
12869 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
12870 the user did not want divide instructions. A value of 2
12871 explicitly means that divide instructions were allowed in ARM
12872 and Thumb state. */
12873 if (in_attr[i].i == out_attr[i].i)
12874 /* Do nothing. */ ;
12875 else if (elf32_arm_attributes_forbid_div (in_attr)
12876 && !elf32_arm_attributes_accept_div (out_attr))
12877 out_attr[i].i = 1;
12878 else if (elf32_arm_attributes_forbid_div (out_attr)
12879 && elf32_arm_attributes_accept_div (in_attr))
12880 out_attr[i].i = in_attr[i].i;
12881 else if (in_attr[i].i == 2)
12882 out_attr[i].i = in_attr[i].i;
cd21e546
MGD		 12883 break;
12884
12885 case Tag_MPextension_use_legacy:
12886 /* We don't output objects with Tag_MPextension_use_legacy - we
12887 move the value to Tag_MPextension_use. */
12888 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
12889 {
12890 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
12891 {
12892 _bfd_error_handler
12893 (_("%B has has both the current and legacy "
b38cadfb 12894 "Tag_MPextension_use attributes"),
cd21e546
MGD		 12895 ibfd);
12896 result = FALSE;
12897 }
12898 }
12899
12900 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
12901 out_attr[Tag_MPextension_use] = in_attr[i];
12902
12903 break;
12904
91e22acd 12905 case Tag_nodefaults:
2d0bb761
AS		 12906 /* This tag is set if it exists, but the value is unused (and is
12907 typically zero). We don't actually need to do anything here -
12908 the merge happens automatically when the type flags are merged
12909 below. */
91e22acd
AS		 12910 break;
12911 case Tag_also_compatible_with:
12912 /* Already done in Tag_CPU_arch. */
12913 break;
12914 case Tag_conformance:
12915 /* Keep the attribute if it matches. Throw it away otherwise.
12916 No attribute means no claim to conform. */
12917 if (!in_attr[i].s || !out_attr[i].s
12918 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
12919 out_attr[i].s = NULL;
12920 break;
3cfad14c 12921
91e22acd 12922 default:
e8b36cd1
JM		 12923 result
12924 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
91e22acd
AS		 12925 }
12926
12927 /* If out_attr was copied from in_attr then it won't have a type yet. */
12928 if (in_attr[i].type && !out_attr[i].type)
12929 out_attr[i].type = in_attr[i].type;
ee065d83
PB		 12930 }
12931
104d59d1 12932 /* Merge Tag_compatibility attributes and any common GNU ones. */
5488d830
MGD		 12933 if (!_bfd_elf_merge_object_attributes (ibfd, obfd))
12934 return FALSE;
ee065d83 12935
104d59d1 12936 /* Check for any attributes not known on ARM. */
e8b36cd1 12937 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
91e22acd 12938
91e22acd 12939 return result;
252b5132
RH		 12940}
12941
3a4a14e9
PB		 12942
12943/* Return TRUE if the two EABI versions are incompatible. */
12944
12945static bfd_boolean
12946elf32_arm_versions_compatible (unsigned iver, unsigned over)
12947{
12948 /* v4 and v5 are the same spec before and after it was released,
12949 so allow mixing them. */
12950 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
12951 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
12952 return TRUE;
12953
12954 return (iver == over);
12955}
12956
252b5132
RH		 12957/* Merge backend specific data from an object file to the output
12958 object file when linking. */
9b485d32 12959
b34976b6 12960static bfd_boolean
21d799b5 12961elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd);
252b5132 12962
9b485d32
NC		 12963/* Display the flags field. */
12964
b34976b6 12965static bfd_boolean
57e8b36a 12966elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
252b5132 12967{
fc830a83
NC		 12968 FILE * file = (FILE *) ptr;
12969 unsigned long flags;
252b5132
RH		 12970
12971 BFD_ASSERT (abfd != NULL && ptr != NULL);
12972
12973 /* Print normal ELF private data. */
12974 _bfd_elf_print_private_bfd_data (abfd, ptr);
12975
fc830a83 12976 flags = elf_elfheader (abfd)->e_flags;
9b485d32
NC		 12977 /* Ignore init flag - it may not be set, despite the flags field
12978 containing valid data. */
252b5132
RH		 12979
12980 /* xgettext:c-format */
9b485d32 12981 fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
252b5132 12982
fc830a83
NC		 12983 switch (EF_ARM_EABI_VERSION (flags))
12984 {
12985 case EF_ARM_EABI_UNKNOWN:
4cc11e76 12986 /* The following flag bits are GNU extensions and not part of the
fc830a83
NC		 12987 official ARM ELF extended ABI. Hence they are only decoded if
12988 the EABI version is not set. */
fd2ec330 12989 if (flags & EF_ARM_INTERWORK)
9b485d32 12990 fprintf (file, _(" [interworking enabled]"));
9a5aca8c 12991
fd2ec330 12992 if (flags & EF_ARM_APCS_26)
6c571f00 12993 fprintf (file, " [APCS-26]");
fc830a83 12994 else
6c571f00 12995 fprintf (file, " [APCS-32]");
9a5aca8c 12996
96a846ea
RE		 12997 if (flags & EF_ARM_VFP_FLOAT)
12998 fprintf (file, _(" [VFP float format]"));
fde78edd
NC		 12999 else if (flags & EF_ARM_MAVERICK_FLOAT)
13000 fprintf (file, _(" [Maverick float format]"));
96a846ea
RE		 13001 else
13002 fprintf (file, _(" [FPA float format]"));
13003
fd2ec330 13004 if (flags & EF_ARM_APCS_FLOAT)
9b485d32 13005 fprintf (file, _(" [floats passed in float registers]"));
9a5aca8c 13006
fd2ec330 13007 if (flags & EF_ARM_PIC)
9b485d32 13008 fprintf (file, _(" [position independent]"));
fc830a83 13009
fd2ec330 13010 if (flags & EF_ARM_NEW_ABI)
9b485d32 13011 fprintf (file, _(" [new ABI]"));
9a5aca8c 13012
fd2ec330 13013 if (flags & EF_ARM_OLD_ABI)
9b485d32 13014 fprintf (file, _(" [old ABI]"));
9a5aca8c 13015
fd2ec330 13016 if (flags & EF_ARM_SOFT_FLOAT)
9b485d32 13017 fprintf (file, _(" [software FP]"));
9a5aca8c 13018
96a846ea
RE		 13019 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
13020 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
fde78edd
NC		 13021 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
13022 | EF_ARM_MAVERICK_FLOAT);
fc830a83 13023 break;
9a5aca8c 13024
fc830a83 13025 case EF_ARM_EABI_VER1:
9b485d32 13026 fprintf (file, _(" [Version1 EABI]"));
9a5aca8c 13027
fc830a83 13028 if (flags & EF_ARM_SYMSARESORTED)
9b485d32 13029 fprintf (file, _(" [sorted symbol table]"));
fc830a83 13030 else
9b485d32 13031 fprintf (file, _(" [unsorted symbol table]"));
9a5aca8c 13032
fc830a83
NC		 13033 flags &= ~ EF_ARM_SYMSARESORTED;
13034 break;
9a5aca8c 13035
fd2ec330
PB		 13036 case EF_ARM_EABI_VER2:
13037 fprintf (file, _(" [Version2 EABI]"));
13038
13039 if (flags & EF_ARM_SYMSARESORTED)
13040 fprintf (file, _(" [sorted symbol table]"));
13041 else
13042 fprintf (file, _(" [unsorted symbol table]"));
13043
13044 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
13045 fprintf (file, _(" [dynamic symbols use segment index]"));
13046
13047 if (flags & EF_ARM_MAPSYMSFIRST)
13048 fprintf (file, _(" [mapping symbols precede others]"));
13049
99e4ae17 13050 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
fd2ec330
PB		 13051 | EF_ARM_MAPSYMSFIRST);
13052 break;
13053
d507cf36
PB		 13054 case EF_ARM_EABI_VER3:
13055 fprintf (file, _(" [Version3 EABI]"));
8cb51566
PB		 13056 break;
13057
13058 case EF_ARM_EABI_VER4:
13059 fprintf (file, _(" [Version4 EABI]"));
3a4a14e9 13060 goto eabi;
d507cf36 13061
3a4a14e9
PB		 13062 case EF_ARM_EABI_VER5:
13063 fprintf (file, _(" [Version5 EABI]"));
3bfcb652
NC		 13064
13065 if (flags & EF_ARM_ABI_FLOAT_SOFT)
13066 fprintf (file, _(" [soft-float ABI]"));
13067
13068 if (flags & EF_ARM_ABI_FLOAT_HARD)
13069 fprintf (file, _(" [hard-float ABI]"));
13070
13071 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
13072
3a4a14e9 13073 eabi:
d507cf36
PB		 13074 if (flags & EF_ARM_BE8)
13075 fprintf (file, _(" [BE8]"));
13076
13077 if (flags & EF_ARM_LE8)
13078 fprintf (file, _(" [LE8]"));
13079
13080 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
13081 break;
13082
fc830a83 13083 default:
9b485d32 13084 fprintf (file, _(" <EABI version unrecognised>"));
fc830a83
NC		 13085 break;
13086 }
252b5132 13087
fc830a83 13088 flags &= ~ EF_ARM_EABIMASK;
252b5132 13089
fc830a83 13090 if (flags & EF_ARM_RELEXEC)
9b485d32 13091 fprintf (file, _(" [relocatable executable]"));
252b5132 13092
a5721edd 13093 flags &= ~EF_ARM_RELEXEC;
fc830a83
NC		 13094
13095 if (flags)
9b485d32 13096 fprintf (file, _("<Unrecognised flag bits set>"));
9a5aca8c 13097
252b5132
RH		 13098 fputc ('\n', file);
13099
b34976b6 13100 return TRUE;
252b5132
RH		 13101}
13102
13103static int
57e8b36a 13104elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
252b5132 13105{
2f0ca46a
NC		 13106 switch (ELF_ST_TYPE (elf_sym->st_info))
13107 {
13108 case STT_ARM_TFUNC:
13109 return ELF_ST_TYPE (elf_sym->st_info);
ce855c42 13110
2f0ca46a
NC		 13111 case STT_ARM_16BIT:
13112 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
13113 This allows us to distinguish between data used by Thumb instructions
13114 and non-data (which is probably code) inside Thumb regions of an
13115 executable. */
1a0eb693 13116 if (type != STT_OBJECT && type != STT_TLS)
2f0ca46a
NC		 13117 return ELF_ST_TYPE (elf_sym->st_info);
13118 break;
9a5aca8c 13119
ce855c42
NC		 13120 default:
13121 break;
2f0ca46a
NC		 13122 }
13123
13124 return type;
252b5132 13125}
f21f3fe0 13126
252b5132 13127static asection *
07adf181
AM		 13128elf32_arm_gc_mark_hook (asection *sec,
13129 struct bfd_link_info *info,
13130 Elf_Internal_Rela *rel,
13131 struct elf_link_hash_entry *h,
13132 Elf_Internal_Sym *sym)
252b5132
RH		 13133{
13134 if (h != NULL)
07adf181 13135 switch (ELF32_R_TYPE (rel->r_info))
252b5132
RH		 13136 {
13137 case R_ARM_GNU_VTINHERIT:
13138 case R_ARM_GNU_VTENTRY:
07adf181
AM		 13139 return NULL;
13140 }
9ad5cbcf 13141
07adf181 13142 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
252b5132
RH		 13143}
13144
780a67af
NC		 13145/* Update the got entry reference counts for the section being removed. */
13146
b34976b6 13147static bfd_boolean
ba93b8ac
DJ		 13148elf32_arm_gc_sweep_hook (bfd * abfd,
13149 struct bfd_link_info * info,
13150 asection * sec,
13151 const Elf_Internal_Rela * relocs)
252b5132 13152{
5e681ec4
PB		 13153 Elf_Internal_Shdr *symtab_hdr;
13154 struct elf_link_hash_entry **sym_hashes;
13155 bfd_signed_vma *local_got_refcounts;
13156 const Elf_Internal_Rela *rel, *relend;
eb043451
PB		 13157 struct elf32_arm_link_hash_table * globals;
13158
0e1862bb 13159 if (bfd_link_relocatable (info))
7dda2462
TG		 13160 return TRUE;
13161
eb043451 13162 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13163 if (globals == NULL)
13164 return FALSE;
5e681ec4
PB		 13165
13166 elf_section_data (sec)->local_dynrel = NULL;
13167
0ffa91dd 13168 symtab_hdr = & elf_symtab_hdr (abfd);
5e681ec4
PB		 13169 sym_hashes = elf_sym_hashes (abfd);
13170 local_got_refcounts = elf_local_got_refcounts (abfd);
13171
906e58ca 13172 check_use_blx (globals);
bd97cb95 13173
5e681ec4
PB		 13174 relend = relocs + sec->reloc_count;
13175 for (rel = relocs; rel < relend; rel++)
eb043451 13176 {
3eb128b2
AM		 13177 unsigned long r_symndx;
13178 struct elf_link_hash_entry *h = NULL;
f6e32f6d 13179 struct elf32_arm_link_hash_entry *eh;
eb043451 13180 int r_type;
34e77a92 13181 bfd_boolean call_reloc_p;
f6e32f6d
RS		 13182 bfd_boolean may_become_dynamic_p;
13183 bfd_boolean may_need_local_target_p;
34e77a92
RS		 13184 union gotplt_union *root_plt;
13185 struct arm_plt_info *arm_plt;
5e681ec4 13186
3eb128b2
AM		 13187 r_symndx = ELF32_R_SYM (rel->r_info);
13188 if (r_symndx >= symtab_hdr->sh_info)
13189 {
13190 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
13191 while (h->root.type == bfd_link_hash_indirect
13192 || h->root.type == bfd_link_hash_warning)
13193 h = (struct elf_link_hash_entry *) h->root.u.i.link;
13194 }
f6e32f6d
RS		 13195 eh = (struct elf32_arm_link_hash_entry *) h;
13196
34e77a92 13197 call_reloc_p = FALSE;
f6e32f6d
RS		 13198 may_become_dynamic_p = FALSE;
13199 may_need_local_target_p = FALSE;
3eb128b2 13200
eb043451 13201 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 13202 r_type = arm_real_reloc_type (globals, r_type);
eb043451
PB		 13203 switch (r_type)
13204 {
13205 case R_ARM_GOT32:
eb043451 13206 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 13207 case R_ARM_TLS_GD32:
13208 case R_ARM_TLS_IE32:
3eb128b2 13209 if (h != NULL)
eb043451 13210 {
eb043451
PB		 13211 if (h->got.refcount > 0)
13212 h->got.refcount -= 1;
13213 }
13214 else if (local_got_refcounts != NULL)
13215 {
13216 if (local_got_refcounts[r_symndx] > 0)
13217 local_got_refcounts[r_symndx] -= 1;
13218 }
13219 break;
13220
ba93b8ac 13221 case R_ARM_TLS_LDM32:
4dfe6ac6 13222 globals->tls_ldm_got.refcount -= 1;
ba93b8ac
DJ		 13223 break;
13224
eb043451
PB		 13225 case R_ARM_PC24:
13226 case R_ARM_PLT32:
5b5bb741
PB		 13227 case R_ARM_CALL:
13228 case R_ARM_JUMP24:
eb043451 13229 case R_ARM_PREL31:
c19d1205 13230 case R_ARM_THM_CALL:
bd97cb95
DJ		 13231 case R_ARM_THM_JUMP24:
13232 case R_ARM_THM_JUMP19:
34e77a92 13233 call_reloc_p = TRUE;
f6e32f6d
RS		 13234 may_need_local_target_p = TRUE;
13235 break;
13236
13237 case R_ARM_ABS12:
13238 if (!globals->vxworks_p)
13239 {
13240 may_need_local_target_p = TRUE;
13241 break;
13242 }
13243 /* Fall through. */
13244 case R_ARM_ABS32:
13245 case R_ARM_ABS32_NOI:
13246 case R_ARM_REL32:
13247 case R_ARM_REL32_NOI:
b6895b4f
PB		 13248 case R_ARM_MOVW_ABS_NC:
13249 case R_ARM_MOVT_ABS:
13250 case R_ARM_MOVW_PREL_NC:
13251 case R_ARM_MOVT_PREL:
13252 case R_ARM_THM_MOVW_ABS_NC:
13253 case R_ARM_THM_MOVT_ABS:
13254 case R_ARM_THM_MOVW_PREL_NC:
13255 case R_ARM_THM_MOVT_PREL:
b7693d02 13256 /* Should the interworking branches be here also? */
0e1862bb 13257 if ((bfd_link_pic (info) || globals->root.is_relocatable_executable)
34e77a92
RS		 13258 && (sec->flags & SEC_ALLOC) != 0)
13259 {
13260 if (h == NULL
469a3493 13261 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 13262 {
13263 call_reloc_p = TRUE;
13264 may_need_local_target_p = TRUE;
13265 }
13266 else
13267 may_become_dynamic_p = TRUE;
13268 }
f6e32f6d
RS		 13269 else
13270 may_need_local_target_p = TRUE;
13271 break;
b7693d02 13272
f6e32f6d
RS		 13273 default:
13274 break;
13275 }
5e681ec4 13276
34e77a92
RS		 13277 if (may_need_local_target_p
13278 && elf32_arm_get_plt_info (abfd, eh, r_symndx, &root_plt, &arm_plt))
f6e32f6d 13279 {
27586251
HPN		 13280 /* If PLT refcount book-keeping is wrong and too low, we'll
13281 see a zero value (going to -1) for the root PLT reference
13282 count. */
13283 if (root_plt->refcount >= 0)
13284 {
13285 BFD_ASSERT (root_plt->refcount != 0);
13286 root_plt->refcount -= 1;
13287 }
13288 else
13289 /* A value of -1 means the symbol has become local, forced
13290 or seeing a hidden definition. Any other negative value
13291 is an error. */
13292 BFD_ASSERT (root_plt->refcount == -1);
34e77a92
RS		 13293
13294 if (!call_reloc_p)
13295 arm_plt->noncall_refcount--;
5e681ec4 13296
f6e32f6d 13297 if (r_type == R_ARM_THM_CALL)
34e77a92 13298 arm_plt->maybe_thumb_refcount--;
bd97cb95 13299
f6e32f6d
RS		 13300 if (r_type == R_ARM_THM_JUMP24
13301 || r_type == R_ARM_THM_JUMP19)
34e77a92 13302 arm_plt->thumb_refcount--;
f6e32f6d 13303 }
5e681ec4 13304
34e77a92 13305 if (may_become_dynamic_p)
f6e32f6d
RS		 13306 {
13307 struct elf_dyn_relocs **pp;
13308 struct elf_dyn_relocs *p;
5e681ec4 13309
34e77a92 13310 if (h != NULL)
9c489990 13311 pp = &(eh->dyn_relocs);
34e77a92
RS		 13312 else
13313 {
13314 Elf_Internal_Sym *isym;
13315
13316 isym = bfd_sym_from_r_symndx (&globals->sym_cache,
13317 abfd, r_symndx);
13318 if (isym == NULL)
13319 return FALSE;
13320 pp = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
13321 if (pp == NULL)
13322 return FALSE;
13323 }
9c489990 13324 for (; (p = *pp) != NULL; pp = &p->next)
f6e32f6d
RS		 13325 if (p->sec == sec)
13326 {
13327 /* Everything must go for SEC. */
13328 *pp = p->next;
13329 break;
13330 }
eb043451
PB		 13331 }
13332 }
5e681ec4 13333
b34976b6 13334 return TRUE;
252b5132
RH		 13335}
13336
780a67af
NC		 13337/* Look through the relocs for a section during the first phase. */
13338
b34976b6 13339static bfd_boolean
57e8b36a
NC		 13340elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
13341 asection *sec, const Elf_Internal_Rela *relocs)
252b5132 13342{
b34976b6
AM		 13343 Elf_Internal_Shdr *symtab_hdr;
13344 struct elf_link_hash_entry **sym_hashes;
b34976b6
AM		 13345 const Elf_Internal_Rela *rel;
13346 const Elf_Internal_Rela *rel_end;
13347 bfd *dynobj;
5e681ec4 13348 asection *sreloc;
5e681ec4 13349 struct elf32_arm_link_hash_table *htab;
f6e32f6d
RS		 13350 bfd_boolean call_reloc_p;
13351 bfd_boolean may_become_dynamic_p;
13352 bfd_boolean may_need_local_target_p;
ce98a316 13353 unsigned long nsyms;
9a5aca8c 13354
0e1862bb 13355 if (bfd_link_relocatable (info))
b34976b6 13356 return TRUE;
9a5aca8c 13357
0ffa91dd
NC		 13358 BFD_ASSERT (is_arm_elf (abfd));
13359
5e681ec4 13360 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13361 if (htab == NULL)
13362 return FALSE;
13363
5e681ec4 13364 sreloc = NULL;
9a5aca8c 13365
67687978
PB		 13366 /* Create dynamic sections for relocatable executables so that we can
13367 copy relocations. */
13368 if (htab->root.is_relocatable_executable
13369 && ! htab->root.dynamic_sections_created)
13370 {
13371 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
13372 return FALSE;
13373 }
13374
cbc704f3
RS		 13375 if (htab->root.dynobj == NULL)
13376 htab->root.dynobj = abfd;
34e77a92
RS		 13377 if (!create_ifunc_sections (info))
13378 return FALSE;
cbc704f3
RS		 13379
13380 dynobj = htab->root.dynobj;
13381
0ffa91dd 13382 symtab_hdr = & elf_symtab_hdr (abfd);
252b5132 13383 sym_hashes = elf_sym_hashes (abfd);
ce98a316 13384 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
b38cadfb 13385
252b5132
RH		 13386 rel_end = relocs + sec->reloc_count;
13387 for (rel = relocs; rel < rel_end; rel++)
13388 {
34e77a92 13389 Elf_Internal_Sym *isym;
252b5132 13390 struct elf_link_hash_entry *h;
b7693d02 13391 struct elf32_arm_link_hash_entry *eh;
252b5132 13392 unsigned long r_symndx;
eb043451 13393 int r_type;
9a5aca8c 13394
252b5132 13395 r_symndx = ELF32_R_SYM (rel->r_info);
eb043451 13396 r_type = ELF32_R_TYPE (rel->r_info);
eb043451 13397 r_type = arm_real_reloc_type (htab, r_type);
ba93b8ac 13398
ce98a316
NC		 13399 if (r_symndx >= nsyms
13400 /* PR 9934: It is possible to have relocations that do not
13401 refer to symbols, thus it is also possible to have an
13402 object file containing relocations but no symbol table. */
cf35638d 13403 && (r_symndx > STN_UNDEF || nsyms > 0))
ba93b8ac
DJ		 13404 {
13405 (*_bfd_error_handler) (_("%B: bad symbol index: %d"), abfd,
ce98a316 13406 r_symndx);
ba93b8ac
DJ		 13407 return FALSE;
13408 }
13409
34e77a92
RS		 13410 h = NULL;
13411 isym = NULL;
13412 if (nsyms > 0)
973a3492 13413 {
34e77a92
RS		 13414 if (r_symndx < symtab_hdr->sh_info)
13415 {
13416 /* A local symbol. */
13417 isym = bfd_sym_from_r_symndx (&htab->sym_cache,
13418 abfd, r_symndx);
13419 if (isym == NULL)
13420 return FALSE;
13421 }
13422 else
13423 {
13424 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
13425 while (h->root.type == bfd_link_hash_indirect
13426 || h->root.type == bfd_link_hash_warning)
13427 h = (struct elf_link_hash_entry *) h->root.u.i.link;
81fbe831
AM		 13428
13429 /* PR15323, ref flags aren't set for references in the
13430 same object. */
13431 h->root.non_ir_ref = 1;
34e77a92 13432 }
973a3492 13433 }
9a5aca8c 13434
b7693d02
DJ		 13435 eh = (struct elf32_arm_link_hash_entry *) h;
13436
f6e32f6d
RS		 13437 call_reloc_p = FALSE;
13438 may_become_dynamic_p = FALSE;
13439 may_need_local_target_p = FALSE;
13440
0855e32b
NS		 13441 /* Could be done earlier, if h were already available. */
13442 r_type = elf32_arm_tls_transition (info, r_type, h);
eb043451 13443 switch (r_type)
99059e56 13444 {
5e681ec4 13445 case R_ARM_GOT32:
eb043451 13446 case R_ARM_GOT_PREL:
ba93b8ac
DJ		 13447 case R_ARM_TLS_GD32:
13448 case R_ARM_TLS_IE32:
0855e32b
NS		 13449 case R_ARM_TLS_GOTDESC:
13450 case R_ARM_TLS_DESCSEQ:
13451 case R_ARM_THM_TLS_DESCSEQ:
13452 case R_ARM_TLS_CALL:
13453 case R_ARM_THM_TLS_CALL:
5e681ec4 13454 /* This symbol requires a global offset table entry. */
ba93b8ac
DJ		 13455 {
13456 int tls_type, old_tls_type;
5e681ec4 13457
ba93b8ac
DJ		 13458 switch (r_type)
13459 {
13460 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
b38cadfb 13461
ba93b8ac 13462 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
b38cadfb 13463
0855e32b
NS		 13464 case R_ARM_TLS_GOTDESC:
13465 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
13466 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
13467 tls_type = GOT_TLS_GDESC; break;
b38cadfb 13468
ba93b8ac
DJ		 13469 default: tls_type = GOT_NORMAL; break;
13470 }
252b5132 13471
0e1862bb 13472 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
eea6dad2
KM		 13473 info->flags |= DF_STATIC_TLS;
13474
ba93b8ac
DJ		 13475 if (h != NULL)
13476 {
13477 h->got.refcount++;
13478 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
13479 }
13480 else
13481 {
ba93b8ac 13482 /* This is a global offset table entry for a local symbol. */
34e77a92
RS		 13483 if (!elf32_arm_allocate_local_sym_info (abfd))
13484 return FALSE;
13485 elf_local_got_refcounts (abfd)[r_symndx] += 1;
ba93b8ac
DJ		 13486 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
13487 }
13488
0855e32b 13489 /* If a variable is accessed with both tls methods, two
99059e56 13490 slots may be created. */
0855e32b
NS		 13491 if (GOT_TLS_GD_ANY_P (old_tls_type)
13492 && GOT_TLS_GD_ANY_P (tls_type))
13493 tls_type |= old_tls_type;
13494
13495 /* We will already have issued an error message if there
13496 is a TLS/non-TLS mismatch, based on the symbol
13497 type. So just combine any TLS types needed. */
ba93b8ac
DJ		 13498 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
13499 && tls_type != GOT_NORMAL)
13500 tls_type |= old_tls_type;
13501
0855e32b 13502 /* If the symbol is accessed in both IE and GDESC
99059e56
RM		 13503 method, we're able to relax. Turn off the GDESC flag,
13504 without messing up with any other kind of tls types
6a631e86 13505 that may be involved. */
0855e32b
NS		 13506 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
13507 tls_type &= ~GOT_TLS_GDESC;
13508
ba93b8ac
DJ		 13509 if (old_tls_type != tls_type)
13510 {
13511 if (h != NULL)
13512 elf32_arm_hash_entry (h)->tls_type = tls_type;
13513 else
13514 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
13515 }
13516 }
8029a119 13517 /* Fall through. */
ba93b8ac
DJ		 13518
13519 case R_ARM_TLS_LDM32:
13520 if (r_type == R_ARM_TLS_LDM32)
13521 htab->tls_ldm_got.refcount++;
8029a119 13522 /* Fall through. */
252b5132 13523
c19d1205 13524 case R_ARM_GOTOFF32:
5e681ec4 13525 case R_ARM_GOTPC:
cbc704f3
RS		 13526 if (htab->root.sgot == NULL
13527 && !create_got_section (htab->root.dynobj, info))
13528 return FALSE;
252b5132
RH		 13529 break;
13530
252b5132 13531 case R_ARM_PC24:
7359ea65 13532 case R_ARM_PLT32:
5b5bb741
PB		 13533 case R_ARM_CALL:
13534 case R_ARM_JUMP24:
eb043451 13535 case R_ARM_PREL31:
c19d1205 13536 case R_ARM_THM_CALL:
bd97cb95
DJ		 13537 case R_ARM_THM_JUMP24:
13538 case R_ARM_THM_JUMP19:
f6e32f6d
RS		 13539 call_reloc_p = TRUE;
13540 may_need_local_target_p = TRUE;
13541 break;
13542
13543 case R_ARM_ABS12:
13544 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
13545 ldr __GOTT_INDEX__ offsets. */
13546 if (!htab->vxworks_p)
13547 {
13548 may_need_local_target_p = TRUE;
13549 break;
13550 }
13551 /* Fall through. */
39623e12 13552
96c23d59
JM		 13553 case R_ARM_MOVW_ABS_NC:
13554 case R_ARM_MOVT_ABS:
13555 case R_ARM_THM_MOVW_ABS_NC:
13556 case R_ARM_THM_MOVT_ABS:
0e1862bb 13557 if (bfd_link_pic (info))
96c23d59
JM		 13558 {
13559 (*_bfd_error_handler)
13560 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
13561 abfd, elf32_arm_howto_table_1[r_type].name,
13562 (h) ? h->root.root.string : "a local symbol");
13563 bfd_set_error (bfd_error_bad_value);
13564 return FALSE;
13565 }
13566
13567 /* Fall through. */
39623e12
PB		 13568 case R_ARM_ABS32:
13569 case R_ARM_ABS32_NOI:
0e1862bb 13570 if (h != NULL && bfd_link_executable (info))
97323ad1
WN		 13571 {
13572 h->pointer_equality_needed = 1;
13573 }
13574 /* Fall through. */
39623e12
PB		 13575 case R_ARM_REL32:
13576 case R_ARM_REL32_NOI:
b6895b4f
PB		 13577 case R_ARM_MOVW_PREL_NC:
13578 case R_ARM_MOVT_PREL:
b6895b4f
PB		 13579 case R_ARM_THM_MOVW_PREL_NC:
13580 case R_ARM_THM_MOVT_PREL:
39623e12 13581
b7693d02 13582 /* Should the interworking branches be listed here? */
0e1862bb 13583 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable)
34e77a92
RS		 13584 && (sec->flags & SEC_ALLOC) != 0)
13585 {
13586 if (h == NULL
469a3493 13587 && elf32_arm_howto_from_type (r_type)->pc_relative)
34e77a92
RS		 13588 {
13589 /* In shared libraries and relocatable executables,
13590 we treat local relative references as calls;
13591 see the related SYMBOL_CALLS_LOCAL code in
13592 allocate_dynrelocs. */
13593 call_reloc_p = TRUE;
13594 may_need_local_target_p = TRUE;
13595 }
13596 else
13597 /* We are creating a shared library or relocatable
13598 executable, and this is a reloc against a global symbol,
13599 or a non-PC-relative reloc against a local symbol.
13600 We may need to copy the reloc into the output. */
13601 may_become_dynamic_p = TRUE;
13602 }
f6e32f6d
RS		 13603 else
13604 may_need_local_target_p = TRUE;
252b5132
RH		 13605 break;
13606
99059e56
RM		 13607 /* This relocation describes the C++ object vtable hierarchy.
13608 Reconstruct it for later use during GC. */
13609 case R_ARM_GNU_VTINHERIT:
13610 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
13611 return FALSE;
13612 break;
13613
13614 /* This relocation describes which C++ vtable entries are actually
13615 used. Record for later use during GC. */
13616 case R_ARM_GNU_VTENTRY:
13617 BFD_ASSERT (h != NULL);
13618 if (h != NULL
13619 && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
13620 return FALSE;
13621 break;
13622 }
f6e32f6d
RS		 13623
13624 if (h != NULL)
13625 {
13626 if (call_reloc_p)
13627 /* We may need a .plt entry if the function this reloc
13628 refers to is in a different object, regardless of the
13629 symbol's type. We can't tell for sure yet, because
13630 something later might force the symbol local. */
13631 h->needs_plt = 1;
13632 else if (may_need_local_target_p)
13633 /* If this reloc is in a read-only section, we might
13634 need a copy reloc. We can't check reliably at this
13635 stage whether the section is read-only, as input
13636 sections have not yet been mapped to output sections.
13637 Tentatively set the flag for now, and correct in
13638 adjust_dynamic_symbol. */
13639 h->non_got_ref = 1;
13640 }
13641
34e77a92
RS		 13642 if (may_need_local_target_p
13643 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
f6e32f6d 13644 {
34e77a92
RS		 13645 union gotplt_union *root_plt;
13646 struct arm_plt_info *arm_plt;
13647 struct arm_local_iplt_info *local_iplt;
13648
13649 if (h != NULL)
13650 {
13651 root_plt = &h->plt;
13652 arm_plt = &eh->plt;
13653 }
13654 else
13655 {
13656 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
13657 if (local_iplt == NULL)
13658 return FALSE;
13659 root_plt = &local_iplt->root;
13660 arm_plt = &local_iplt->arm;
13661 }
13662
f6e32f6d
RS		 13663 /* If the symbol is a function that doesn't bind locally,
13664 this relocation will need a PLT entry. */
a8c887dd
NC		 13665 if (root_plt->refcount != -1)
13666 root_plt->refcount += 1;
34e77a92
RS		 13667
13668 if (!call_reloc_p)
13669 arm_plt->noncall_refcount++;
f6e32f6d
RS		 13670
13671 /* It's too early to use htab->use_blx here, so we have to
13672 record possible blx references separately from
13673 relocs that definitely need a thumb stub. */
13674
13675 if (r_type == R_ARM_THM_CALL)
34e77a92 13676 arm_plt->maybe_thumb_refcount += 1;
f6e32f6d
RS		 13677
13678 if (r_type == R_ARM_THM_JUMP24
13679 || r_type == R_ARM_THM_JUMP19)
34e77a92 13680 arm_plt->thumb_refcount += 1;
f6e32f6d
RS		 13681 }
13682
13683 if (may_become_dynamic_p)
13684 {
13685 struct elf_dyn_relocs *p, **head;
13686
13687 /* Create a reloc section in dynobj. */
13688 if (sreloc == NULL)
13689 {
13690 sreloc = _bfd_elf_make_dynamic_reloc_section
13691 (sec, dynobj, 2, abfd, ! htab->use_rel);
13692
13693 if (sreloc == NULL)
13694 return FALSE;
13695
13696 /* BPABI objects never have dynamic relocations mapped. */
13697 if (htab->symbian_p)
13698 {
13699 flagword flags;
13700
13701 flags = bfd_get_section_flags (dynobj, sreloc);
13702 flags &= ~(SEC_LOAD | SEC_ALLOC);
13703 bfd_set_section_flags (dynobj, sreloc, flags);
13704 }
13705 }
13706
13707 /* If this is a global symbol, count the number of
13708 relocations we need for this symbol. */
13709 if (h != NULL)
13710 head = &((struct elf32_arm_link_hash_entry *) h)->dyn_relocs;
13711 else
13712 {
34e77a92
RS		 13713 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
13714 if (head == NULL)
f6e32f6d 13715 return FALSE;
f6e32f6d
RS		 13716 }
13717
13718 p = *head;
13719 if (p == NULL || p->sec != sec)
13720 {
13721 bfd_size_type amt = sizeof *p;
13722
13723 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
13724 if (p == NULL)
13725 return FALSE;
13726 p->next = *head;
13727 *head = p;
13728 p->sec = sec;
13729 p->count = 0;
13730 p->pc_count = 0;
13731 }
13732
469a3493 13733 if (elf32_arm_howto_from_type (r_type)->pc_relative)
f6e32f6d
RS		 13734 p->pc_count += 1;
13735 p->count += 1;
13736 }
252b5132 13737 }
f21f3fe0 13738
b34976b6 13739 return TRUE;
252b5132
RH		 13740}
13741
6a5bb875
PB		 13742/* Unwinding tables are not referenced directly. This pass marks them as
13743 required if the corresponding code section is marked. */
13744
13745static bfd_boolean
906e58ca
NC		 13746elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
13747 elf_gc_mark_hook_fn gc_mark_hook)
6a5bb875
PB		 13748{
13749 bfd *sub;
13750 Elf_Internal_Shdr **elf_shdrp;
13751 bfd_boolean again;
13752
7f6ab9f8
AM		 13753 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
13754
6a5bb875
PB		 13755 /* Marking EH data may cause additional code sections to be marked,
13756 requiring multiple passes. */
13757 again = TRUE;
13758 while (again)
13759 {
13760 again = FALSE;
c72f2fb2 13761 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
6a5bb875
PB		 13762 {
13763 asection *o;
13764
0ffa91dd 13765 if (! is_arm_elf (sub))
6a5bb875
PB		 13766 continue;
13767
13768 elf_shdrp = elf_elfsections (sub);
13769 for (o = sub->sections; o != NULL; o = o->next)
13770 {
13771 Elf_Internal_Shdr *hdr;
0ffa91dd 13772
6a5bb875 13773 hdr = &elf_section_data (o)->this_hdr;
4fbb74a6
AM		 13774 if (hdr->sh_type == SHT_ARM_EXIDX
13775 && hdr->sh_link
13776 && hdr->sh_link < elf_numsections (sub)
6a5bb875
PB		 13777 && !o->gc_mark
13778 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
13779 {
13780 again = TRUE;
13781 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
13782 return FALSE;
13783 }
13784 }
13785 }
13786 }
13787
13788 return TRUE;
13789}
13790
3c9458e9
NC		 13791/* Treat mapping symbols as special target symbols. */
13792
13793static bfd_boolean
13794elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
13795{
b0796911
PB		 13796 return bfd_is_arm_special_symbol_name (sym->name,
13797 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
3c9458e9
NC		 13798}
13799
0367ecfb
NC		 13800/* This is a copy of elf_find_function() from elf.c except that
13801 ARM mapping symbols are ignored when looking for function names
13802 and STT_ARM_TFUNC is considered to a function type. */
252b5132 13803
0367ecfb
NC		 13804static bfd_boolean
13805arm_elf_find_function (bfd * abfd ATTRIBUTE_UNUSED,
0367ecfb 13806 asymbol ** symbols,
fb167eb2 13807 asection * section,
0367ecfb
NC		 13808 bfd_vma offset,
13809 const char ** filename_ptr,
13810 const char ** functionname_ptr)
13811{
13812 const char * filename = NULL;
13813 asymbol * func = NULL;
13814 bfd_vma low_func = 0;
13815 asymbol ** p;
252b5132
RH		 13816
13817 for (p = symbols; *p != NULL; p++)
13818 {
13819 elf_symbol_type *q;
13820
13821 q = (elf_symbol_type *) *p;
13822
252b5132
RH		 13823 switch (ELF_ST_TYPE (q->internal_elf_sym.st_info))
13824 {
13825 default:
13826 break;
13827 case STT_FILE:
13828 filename = bfd_asymbol_name (&q->symbol);
13829 break;
252b5132
RH		 13830 case STT_FUNC:
13831 case STT_ARM_TFUNC:
9d2da7ca 13832 case STT_NOTYPE:
b0796911 13833 /* Skip mapping symbols. */
0367ecfb 13834 if ((q->symbol.flags & BSF_LOCAL)
b0796911
PB		 13835 && bfd_is_arm_special_symbol_name (q->symbol.name,
13836 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
0367ecfb
NC		 13837 continue;
13838 /* Fall through. */
6b40fcba 13839 if (bfd_get_section (&q->symbol) == section
252b5132
RH		 13840 && q->symbol.value >= low_func
13841 && q->symbol.value <= offset)
13842 {
13843 func = (asymbol *) q;
13844 low_func = q->symbol.value;
13845 }
13846 break;
13847 }
13848 }
13849
13850 if (func == NULL)
b34976b6 13851 return FALSE;
252b5132 13852
0367ecfb
NC		 13853 if (filename_ptr)
13854 *filename_ptr = filename;
13855 if (functionname_ptr)
13856 *functionname_ptr = bfd_asymbol_name (func);
13857
13858 return TRUE;
906e58ca 13859}
0367ecfb
NC		 13860
13861
13862/* Find the nearest line to a particular section and offset, for error
13863 reporting. This code is a duplicate of the code in elf.c, except
13864 that it uses arm_elf_find_function. */
13865
13866static bfd_boolean
13867elf32_arm_find_nearest_line (bfd * abfd,
0367ecfb 13868 asymbol ** symbols,
fb167eb2 13869 asection * section,
0367ecfb
NC		 13870 bfd_vma offset,
13871 const char ** filename_ptr,
13872 const char ** functionname_ptr,
fb167eb2
AM		 13873 unsigned int * line_ptr,
13874 unsigned int * discriminator_ptr)
0367ecfb
NC		 13875{
13876 bfd_boolean found = FALSE;
13877
fb167eb2 13878 if (_bfd_dwarf2_find_nearest_line (abfd, symbols, NULL, section, offset,
0367ecfb 13879 filename_ptr, functionname_ptr,
fb167eb2
AM		 13880 line_ptr, discriminator_ptr,
13881 dwarf_debug_sections, 0,
0367ecfb
NC		 13882 & elf_tdata (abfd)->dwarf2_find_line_info))
13883 {
13884 if (!*functionname_ptr)
fb167eb2 13885 arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 13886 *filename_ptr ? NULL : filename_ptr,
13887 functionname_ptr);
f21f3fe0 13888
0367ecfb
NC		 13889 return TRUE;
13890 }
13891
fb167eb2
AM		 13892 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
13893 uses DWARF1. */
13894
0367ecfb
NC		 13895 if (! _bfd_stab_section_find_nearest_line (abfd, symbols, section, offset,
13896 & found, filename_ptr,
13897 functionname_ptr, line_ptr,
13898 & elf_tdata (abfd)->line_info))
13899 return FALSE;
13900
13901 if (found && (*functionname_ptr || *line_ptr))
13902 return TRUE;
13903
13904 if (symbols == NULL)
13905 return FALSE;
13906
fb167eb2 13907 if (! arm_elf_find_function (abfd, symbols, section, offset,
0367ecfb
NC		 13908 filename_ptr, functionname_ptr))
13909 return FALSE;
13910
13911 *line_ptr = 0;
b34976b6 13912 return TRUE;
252b5132
RH		 13913}
13914
4ab527b0
FF		 13915static bfd_boolean
13916elf32_arm_find_inliner_info (bfd * abfd,
13917 const char ** filename_ptr,
13918 const char ** functionname_ptr,
13919 unsigned int * line_ptr)
13920{
13921 bfd_boolean found;
13922 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
13923 functionname_ptr, line_ptr,
13924 & elf_tdata (abfd)->dwarf2_find_line_info);
13925 return found;
13926}
13927
252b5132
RH		 13928/* Adjust a symbol defined by a dynamic object and referenced by a
13929 regular object. The current definition is in some section of the
13930 dynamic object, but we're not including those sections. We have to
13931 change the definition to something the rest of the link can
13932 understand. */
13933
b34976b6 13934static bfd_boolean
57e8b36a
NC		 13935elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
13936 struct elf_link_hash_entry * h)
252b5132
RH		 13937{
13938 bfd * dynobj;
13939 asection * s;
b7693d02 13940 struct elf32_arm_link_hash_entry * eh;
67687978 13941 struct elf32_arm_link_hash_table *globals;
252b5132 13942
67687978 13943 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 13944 if (globals == NULL)
13945 return FALSE;
13946
252b5132
RH		 13947 dynobj = elf_hash_table (info)->dynobj;
13948
13949 /* Make sure we know what is going on here. */
13950 BFD_ASSERT (dynobj != NULL
f5385ebf 13951 && (h->needs_plt
34e77a92 13952 || h->type == STT_GNU_IFUNC
f6e332e6 13953 || h->u.weakdef != NULL
f5385ebf
AM		 13954 || (h->def_dynamic
13955 && h->ref_regular
13956 && !h->def_regular)));
252b5132 13957
b7693d02
DJ		 13958 eh = (struct elf32_arm_link_hash_entry *) h;
13959
252b5132
RH		 13960 /* If this is a function, put it in the procedure linkage table. We
13961 will fill in the contents of the procedure linkage table later,
13962 when we know the address of the .got section. */
34e77a92 13963 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
252b5132 13964 {
34e77a92
RS		 13965 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
13966 symbol binds locally. */
5e681ec4 13967 if (h->plt.refcount <= 0
34e77a92
RS		 13968 || (h->type != STT_GNU_IFUNC
13969 && (SYMBOL_CALLS_LOCAL (info, h)
13970 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
13971 && h->root.type == bfd_link_hash_undefweak))))
252b5132
RH		 13972 {
13973 /* This case can occur if we saw a PLT32 reloc in an input
5e681ec4
PB		 13974 file, but the symbol was never referred to by a dynamic
13975 object, or if all references were garbage collected. In
13976 such a case, we don't actually need to build a procedure
13977 linkage table, and we can just do a PC24 reloc instead. */
13978 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 13979 eh->plt.thumb_refcount = 0;
13980 eh->plt.maybe_thumb_refcount = 0;
13981 eh->plt.noncall_refcount = 0;
f5385ebf 13982 h->needs_plt = 0;
252b5132
RH		 13983 }
13984
b34976b6 13985 return TRUE;
252b5132 13986 }
5e681ec4 13987 else
b7693d02
DJ		 13988 {
13989 /* It's possible that we incorrectly decided a .plt reloc was
13990 needed for an R_ARM_PC24 or similar reloc to a non-function sym
13991 in check_relocs. We can't decide accurately between function
13992 and non-function syms in check-relocs; Objects loaded later in
13993 the link may change h->type. So fix it now. */
13994 h->plt.offset = (bfd_vma) -1;
34e77a92
RS		 13995 eh->plt.thumb_refcount = 0;
13996 eh->plt.maybe_thumb_refcount = 0;
13997 eh->plt.noncall_refcount = 0;
b7693d02 13998 }
252b5132
RH		 13999
14000 /* If this is a weak symbol, and there is a real definition, the
14001 processor independent code will have arranged for us to see the
14002 real definition first, and we can just use the same value. */
f6e332e6 14003 if (h->u.weakdef != NULL)
252b5132 14004 {
f6e332e6
AM		 14005 BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined
14006 || h->u.weakdef->root.type == bfd_link_hash_defweak);
14007 h->root.u.def.section = h->u.weakdef->root.u.def.section;
14008 h->root.u.def.value = h->u.weakdef->root.u.def.value;
b34976b6 14009 return TRUE;
252b5132
RH		 14010 }
14011
ba93b8ac
DJ		 14012 /* If there are no non-GOT references, we do not need a copy
14013 relocation. */
14014 if (!h->non_got_ref)
14015 return TRUE;
14016
252b5132
RH		 14017 /* This is a reference to a symbol defined by a dynamic object which
14018 is not a function. */
14019
14020 /* If we are creating a shared library, we must presume that the
14021 only references to the symbol are via the global offset table.
14022 For such cases we need not do anything here; the relocations will
67687978
PB		 14023 be handled correctly by relocate_section. Relocatable executables
14024 can reference data in shared objects directly, so we don't need to
14025 do anything here. */
0e1862bb 14026 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
b34976b6 14027 return TRUE;
252b5132
RH		 14028
14029 /* We must allocate the symbol in our .dynbss section, which will
14030 become part of the .bss section of the executable. There will be
14031 an entry for this symbol in the .dynsym section. The dynamic
14032 object will contain position independent code, so all references
14033 from the dynamic object to this symbol will go through the global
14034 offset table. The dynamic linker will use the .dynsym entry to
14035 determine the address it must put in the global offset table, so
14036 both the dynamic object and the regular object will refer to the
14037 same memory location for the variable. */
3d4d4302 14038 s = bfd_get_linker_section (dynobj, ".dynbss");
252b5132
RH		 14039 BFD_ASSERT (s != NULL);
14040
14041 /* We must generate a R_ARM_COPY reloc to tell the dynamic linker to
14042 copy the initial value out of the dynamic object and into the
14043 runtime process image. We need to remember the offset into the
00a97672 14044 .rel(a).bss section we are going to use. */
1d7e9d18 14045 if ((h->root.u.def.section->flags & SEC_ALLOC) != 0 && h->size != 0)
252b5132
RH		 14046 {
14047 asection *srel;
14048
3d4d4302 14049 srel = bfd_get_linker_section (dynobj, RELOC_SECTION (globals, ".bss"));
47beaa6a 14050 elf32_arm_allocate_dynrelocs (info, srel, 1);
f5385ebf 14051 h->needs_copy = 1;
252b5132
RH		 14052 }
14053
6cabe1ea 14054 return _bfd_elf_adjust_dynamic_copy (info, h, s);
252b5132
RH		 14055}
14056
5e681ec4
PB		 14057/* Allocate space in .plt, .got and associated reloc sections for
14058 dynamic relocs. */
14059
14060static bfd_boolean
47beaa6a 14061allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
5e681ec4
PB		 14062{
14063 struct bfd_link_info *info;
14064 struct elf32_arm_link_hash_table *htab;
14065 struct elf32_arm_link_hash_entry *eh;
0bdcacaf 14066 struct elf_dyn_relocs *p;
5e681ec4
PB		 14067
14068 if (h->root.type == bfd_link_hash_indirect)
14069 return TRUE;
14070
e6a6bb22
AM		 14071 eh = (struct elf32_arm_link_hash_entry *) h;
14072
5e681ec4
PB		 14073 info = (struct bfd_link_info *) inf;
14074 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14075 if (htab == NULL)
14076 return FALSE;
5e681ec4 14077
34e77a92 14078 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
5e681ec4
PB		 14079 && h->plt.refcount > 0)
14080 {
14081 /* Make sure this symbol is output as a dynamic symbol.
14082 Undefined weak syms won't yet be marked as dynamic. */
14083 if (h->dynindx == -1
f5385ebf 14084 && !h->forced_local)
5e681ec4 14085 {
c152c796 14086 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14087 return FALSE;
14088 }
14089
34e77a92
RS		 14090 /* If the call in the PLT entry binds locally, the associated
14091 GOT entry should use an R_ARM_IRELATIVE relocation instead of
14092 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
14093 than the .plt section. */
14094 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
14095 {
14096 eh->is_iplt = 1;
14097 if (eh->plt.noncall_refcount == 0
14098 && SYMBOL_REFERENCES_LOCAL (info, h))
14099 /* All non-call references can be resolved directly.
14100 This means that they can (and in some cases, must)
14101 resolve directly to the run-time target, rather than
14102 to the PLT. That in turns means that any .got entry
14103 would be equal to the .igot.plt entry, so there's
14104 no point having both. */
14105 h->got.refcount = 0;
14106 }
14107
0e1862bb 14108 if (bfd_link_pic (info)
34e77a92 14109 || eh->is_iplt
7359ea65 14110 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
5e681ec4 14111 {
34e77a92 14112 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
b7693d02 14113
5e681ec4
PB		 14114 /* If this symbol is not defined in a regular file, and we are
14115 not generating a shared library, then set the symbol to this
14116 location in the .plt. This is required to make function
14117 pointers compare as equal between the normal executable and
14118 the shared library. */
0e1862bb 14119 if (! bfd_link_pic (info)
f5385ebf 14120 && !h->def_regular)
5e681ec4 14121 {
34e77a92 14122 h->root.u.def.section = htab->root.splt;
5e681ec4 14123 h->root.u.def.value = h->plt.offset;
5e681ec4 14124
67d74e43
DJ		 14125 /* Make sure the function is not marked as Thumb, in case
14126 it is the target of an ABS32 relocation, which will
14127 point to the PLT entry. */
35fc36a8 14128 h->target_internal = ST_BRANCH_TO_ARM;
67d74e43 14129 }
022f8312 14130
00a97672
RS		 14131 /* VxWorks executables have a second set of relocations for
14132 each PLT entry. They go in a separate relocation section,
14133 which is processed by the kernel loader. */
0e1862bb 14134 if (htab->vxworks_p && !bfd_link_pic (info))
00a97672
RS		 14135 {
14136 /* There is a relocation for the initial PLT entry:
14137 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
14138 if (h->plt.offset == htab->plt_header_size)
47beaa6a 14139 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
00a97672
RS		 14140
14141 /* There are two extra relocations for each subsequent
14142 PLT entry: an R_ARM_32 relocation for the GOT entry,
14143 and an R_ARM_32 relocation for the PLT entry. */
47beaa6a 14144 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
00a97672 14145 }
5e681ec4
PB		 14146 }
14147 else
14148 {
14149 h->plt.offset = (bfd_vma) -1;
f5385ebf 14150 h->needs_plt = 0;
5e681ec4
PB		 14151 }
14152 }
14153 else
14154 {
14155 h->plt.offset = (bfd_vma) -1;
f5385ebf 14156 h->needs_plt = 0;
5e681ec4
PB		 14157 }
14158
0855e32b
NS		 14159 eh = (struct elf32_arm_link_hash_entry *) h;
14160 eh->tlsdesc_got = (bfd_vma) -1;
14161
5e681ec4
PB		 14162 if (h->got.refcount > 0)
14163 {
14164 asection *s;
14165 bfd_boolean dyn;
ba93b8ac
DJ		 14166 int tls_type = elf32_arm_hash_entry (h)->tls_type;
14167 int indx;
5e681ec4
PB		 14168
14169 /* Make sure this symbol is output as a dynamic symbol.
14170 Undefined weak syms won't yet be marked as dynamic. */
14171 if (h->dynindx == -1
f5385ebf 14172 && !h->forced_local)
5e681ec4 14173 {
c152c796 14174 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14175 return FALSE;
14176 }
14177
e5a52504
MM		 14178 if (!htab->symbian_p)
14179 {
362d30a1 14180 s = htab->root.sgot;
e5a52504 14181 h->got.offset = s->size;
ba93b8ac
DJ		 14182
14183 if (tls_type == GOT_UNKNOWN)
14184 abort ();
14185
14186 if (tls_type == GOT_NORMAL)
14187 /* Non-TLS symbols need one GOT slot. */
14188 s->size += 4;
14189 else
14190 {
99059e56
RM		 14191 if (tls_type & GOT_TLS_GDESC)
14192 {
0855e32b 14193 /* R_ARM_TLS_DESC needs 2 GOT slots. */
99059e56 14194 eh->tlsdesc_got
0855e32b
NS		 14195 = (htab->root.sgotplt->size
14196 - elf32_arm_compute_jump_table_size (htab));
99059e56
RM		 14197 htab->root.sgotplt->size += 8;
14198 h->got.offset = (bfd_vma) -2;
34e77a92 14199 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 14200 reloc in the middle of .got.plt. */
99059e56
RM		 14201 htab->num_tls_desc++;
14202 }
0855e32b 14203
ba93b8ac 14204 if (tls_type & GOT_TLS_GD)
0855e32b
NS		 14205 {
14206 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
14207 the symbol is both GD and GDESC, got.offset may
14208 have been overwritten. */
14209 h->got.offset = s->size;
14210 s->size += 8;
14211 }
14212
ba93b8ac
DJ		 14213 if (tls_type & GOT_TLS_IE)
14214 /* R_ARM_TLS_IE32 needs one GOT slot. */
14215 s->size += 4;
14216 }
14217
e5a52504 14218 dyn = htab->root.dynamic_sections_created;
ba93b8ac
DJ		 14219
14220 indx = 0;
0e1862bb
L		 14221 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
14222 bfd_link_pic (info),
14223 h)
14224 && (!bfd_link_pic (info)
ba93b8ac
DJ		 14225 || !SYMBOL_REFERENCES_LOCAL (info, h)))
14226 indx = h->dynindx;
14227
14228 if (tls_type != GOT_NORMAL
0e1862bb 14229 && (bfd_link_pic (info) || indx != 0)
ba93b8ac
DJ		 14230 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
14231 || h->root.type != bfd_link_hash_undefweak))
14232 {
14233 if (tls_type & GOT_TLS_IE)
47beaa6a 14234 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 14235
14236 if (tls_type & GOT_TLS_GD)
47beaa6a 14237 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 14238
b38cadfb 14239 if (tls_type & GOT_TLS_GDESC)
0855e32b 14240 {
47beaa6a 14241 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
0855e32b
NS		 14242 /* GDESC needs a trampoline to jump to. */
14243 htab->tls_trampoline = -1;
14244 }
14245
14246 /* Only GD needs it. GDESC just emits one relocation per
14247 2 entries. */
b38cadfb 14248 if ((tls_type & GOT_TLS_GD) && indx != 0)
47beaa6a 14249 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac 14250 }
6f820c85 14251 else if (indx != -1 && !SYMBOL_REFERENCES_LOCAL (info, h))
b436d854
RS		 14252 {
14253 if (htab->root.dynamic_sections_created)
14254 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
14255 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
14256 }
34e77a92
RS		 14257 else if (h->type == STT_GNU_IFUNC
14258 && eh->plt.noncall_refcount == 0)
14259 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
14260 they all resolve dynamically instead. Reserve room for the
14261 GOT entry's R_ARM_IRELATIVE relocation. */
14262 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
0e1862bb
L		 14263 else if (bfd_link_pic (info)
14264 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
14265 || h->root.type != bfd_link_hash_undefweak))
b436d854 14266 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
47beaa6a 14267 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
e5a52504 14268 }
5e681ec4
PB		 14269 }
14270 else
14271 h->got.offset = (bfd_vma) -1;
14272
a4fd1a8e
PB		 14273 /* Allocate stubs for exported Thumb functions on v4t. */
14274 if (!htab->use_blx && h->dynindx != -1
0eaedd0e 14275 && h->def_regular
35fc36a8 14276 && h->target_internal == ST_BRANCH_TO_THUMB
a4fd1a8e
PB		 14277 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
14278 {
14279 struct elf_link_hash_entry * th;
14280 struct bfd_link_hash_entry * bh;
14281 struct elf_link_hash_entry * myh;
14282 char name[1024];
14283 asection *s;
14284 bh = NULL;
14285 /* Create a new symbol to regist the real location of the function. */
14286 s = h->root.u.def.section;
906e58ca 14287 sprintf (name, "__real_%s", h->root.root.string);
a4fd1a8e
PB		 14288 _bfd_generic_link_add_one_symbol (info, s->owner,
14289 name, BSF_GLOBAL, s,
14290 h->root.u.def.value,
14291 NULL, TRUE, FALSE, &bh);
14292
14293 myh = (struct elf_link_hash_entry *) bh;
35fc36a8 14294 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
a4fd1a8e 14295 myh->forced_local = 1;
35fc36a8 14296 myh->target_internal = ST_BRANCH_TO_THUMB;
a4fd1a8e
PB		 14297 eh->export_glue = myh;
14298 th = record_arm_to_thumb_glue (info, h);
14299 /* Point the symbol at the stub. */
14300 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
35fc36a8 14301 h->target_internal = ST_BRANCH_TO_ARM;
a4fd1a8e
PB		 14302 h->root.u.def.section = th->root.u.def.section;
14303 h->root.u.def.value = th->root.u.def.value & ~1;
14304 }
14305
0bdcacaf 14306 if (eh->dyn_relocs == NULL)
5e681ec4
PB		 14307 return TRUE;
14308
14309 /* In the shared -Bsymbolic case, discard space allocated for
14310 dynamic pc-relative relocs against symbols which turn out to be
14311 defined in regular objects. For the normal shared case, discard
14312 space for pc-relative relocs that have become local due to symbol
14313 visibility changes. */
14314
0e1862bb 14315 if (bfd_link_pic (info) || htab->root.is_relocatable_executable)
5e681ec4 14316 {
469a3493
RM		 14317 /* Relocs that use pc_count are PC-relative forms, which will appear
14318 on something like ".long foo - ." or "movw REG, foo - .". We want
14319 calls to protected symbols to resolve directly to the function
14320 rather than going via the plt. If people want function pointer
14321 comparisons to work as expected then they should avoid writing
14322 assembly like ".long foo - .". */
ba93b8ac
DJ		 14323 if (SYMBOL_CALLS_LOCAL (info, h))
14324 {
0bdcacaf 14325 struct elf_dyn_relocs **pp;
ba93b8ac 14326
0bdcacaf 14327 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
ba93b8ac
DJ		 14328 {
14329 p->count -= p->pc_count;
14330 p->pc_count = 0;
14331 if (p->count == 0)
14332 *pp = p->next;
14333 else
14334 pp = &p->next;
14335 }
14336 }
14337
4dfe6ac6 14338 if (htab->vxworks_p)
3348747a 14339 {
0bdcacaf 14340 struct elf_dyn_relocs **pp;
3348747a 14341
0bdcacaf 14342 for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
3348747a 14343 {
0bdcacaf 14344 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
3348747a
NS		 14345 *pp = p->next;
14346 else
14347 pp = &p->next;
14348 }
14349 }
14350
ba93b8ac 14351 /* Also discard relocs on undefined weak syms with non-default
99059e56 14352 visibility. */
0bdcacaf 14353 if (eh->dyn_relocs != NULL
5e681ec4 14354 && h->root.type == bfd_link_hash_undefweak)
22d606e9
AM		 14355 {
14356 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT)
0bdcacaf 14357 eh->dyn_relocs = NULL;
22d606e9
AM		 14358
14359 /* Make sure undefined weak symbols are output as a dynamic
14360 symbol in PIEs. */
14361 else if (h->dynindx == -1
14362 && !h->forced_local)
14363 {
14364 if (! bfd_elf_link_record_dynamic_symbol (info, h))
14365 return FALSE;
14366 }
14367 }
14368
67687978
PB		 14369 else if (htab->root.is_relocatable_executable && h->dynindx == -1
14370 && h->root.type == bfd_link_hash_new)
14371 {
14372 /* Output absolute symbols so that we can create relocations
14373 against them. For normal symbols we output a relocation
14374 against the section that contains them. */
14375 if (! bfd_elf_link_record_dynamic_symbol (info, h))
14376 return FALSE;
14377 }
14378
5e681ec4
PB		 14379 }
14380 else
14381 {
14382 /* For the non-shared case, discard space for relocs against
14383 symbols which turn out to need copy relocs or are not
14384 dynamic. */
14385
f5385ebf
AM		 14386 if (!h->non_got_ref
14387 && ((h->def_dynamic
14388 && !h->def_regular)
5e681ec4
PB		 14389 || (htab->root.dynamic_sections_created
14390 && (h->root.type == bfd_link_hash_undefweak
14391 || h->root.type == bfd_link_hash_undefined))))
14392 {
14393 /* Make sure this symbol is output as a dynamic symbol.
14394 Undefined weak syms won't yet be marked as dynamic. */
14395 if (h->dynindx == -1
f5385ebf 14396 && !h->forced_local)
5e681ec4 14397 {
c152c796 14398 if (! bfd_elf_link_record_dynamic_symbol (info, h))
5e681ec4
PB		 14399 return FALSE;
14400 }
14401
14402 /* If that succeeded, we know we'll be keeping all the
14403 relocs. */
14404 if (h->dynindx != -1)
14405 goto keep;
14406 }
14407
0bdcacaf 14408 eh->dyn_relocs = NULL;
5e681ec4
PB		 14409
14410 keep: ;
14411 }
14412
14413 /* Finally, allocate space. */
0bdcacaf 14414 for (p = eh->dyn_relocs; p != NULL; p = p->next)
5e681ec4 14415 {
0bdcacaf 14416 asection *sreloc = elf_section_data (p->sec)->sreloc;
34e77a92
RS		 14417 if (h->type == STT_GNU_IFUNC
14418 && eh->plt.noncall_refcount == 0
14419 && SYMBOL_REFERENCES_LOCAL (info, h))
14420 elf32_arm_allocate_irelocs (info, sreloc, p->count);
14421 else
14422 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
5e681ec4
PB		 14423 }
14424
14425 return TRUE;
14426}
14427
08d1f311
DJ		 14428/* Find any dynamic relocs that apply to read-only sections. */
14429
14430static bfd_boolean
8029a119 14431elf32_arm_readonly_dynrelocs (struct elf_link_hash_entry * h, void * inf)
08d1f311 14432{
8029a119 14433 struct elf32_arm_link_hash_entry * eh;
0bdcacaf 14434 struct elf_dyn_relocs * p;
08d1f311 14435
08d1f311 14436 eh = (struct elf32_arm_link_hash_entry *) h;
0bdcacaf 14437 for (p = eh->dyn_relocs; p != NULL; p = p->next)
08d1f311 14438 {
0bdcacaf 14439 asection *s = p->sec;
08d1f311
DJ		 14440
14441 if (s != NULL && (s->flags & SEC_READONLY) != 0)
14442 {
14443 struct bfd_link_info *info = (struct bfd_link_info *) inf;
14444
14445 info->flags |= DF_TEXTREL;
14446
14447 /* Not an error, just cut short the traversal. */
14448 return FALSE;
14449 }
14450 }
14451 return TRUE;
14452}
14453
d504ffc8
DJ		 14454void
14455bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
14456 int byteswap_code)
14457{
14458 struct elf32_arm_link_hash_table *globals;
14459
14460 globals = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14461 if (globals == NULL)
14462 return;
14463
d504ffc8
DJ		 14464 globals->byteswap_code = byteswap_code;
14465}
14466
252b5132
RH		 14467/* Set the sizes of the dynamic sections. */
14468
b34976b6 14469static bfd_boolean
57e8b36a
NC		 14470elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
14471 struct bfd_link_info * info)
252b5132
RH		 14472{
14473 bfd * dynobj;
14474 asection * s;
b34976b6
AM		 14475 bfd_boolean plt;
14476 bfd_boolean relocs;
5e681ec4
PB		 14477 bfd *ibfd;
14478 struct elf32_arm_link_hash_table *htab;
252b5132 14479
5e681ec4 14480 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14481 if (htab == NULL)
14482 return FALSE;
14483
252b5132
RH		 14484 dynobj = elf_hash_table (info)->dynobj;
14485 BFD_ASSERT (dynobj != NULL);
39b41c9c 14486 check_use_blx (htab);
252b5132
RH		 14487
14488 if (elf_hash_table (info)->dynamic_sections_created)
14489 {
14490 /* Set the contents of the .interp section to the interpreter. */
9b8b325a 14491 if (bfd_link_executable (info) && !info->nointerp)
252b5132 14492 {
3d4d4302 14493 s = bfd_get_linker_section (dynobj, ".interp");
252b5132 14494 BFD_ASSERT (s != NULL);
eea6121a 14495 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
252b5132
RH		 14496 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
14497 }
14498 }
5e681ec4
PB		 14499
14500 /* Set up .got offsets for local syms, and space for local dynamic
14501 relocs. */
c72f2fb2 14502 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
252b5132 14503 {
5e681ec4
PB		 14504 bfd_signed_vma *local_got;
14505 bfd_signed_vma *end_local_got;
34e77a92 14506 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
5e681ec4 14507 char *local_tls_type;
0855e32b 14508 bfd_vma *local_tlsdesc_gotent;
5e681ec4
PB		 14509 bfd_size_type locsymcount;
14510 Elf_Internal_Shdr *symtab_hdr;
14511 asection *srel;
4dfe6ac6 14512 bfd_boolean is_vxworks = htab->vxworks_p;
34e77a92 14513 unsigned int symndx;
5e681ec4 14514
0ffa91dd 14515 if (! is_arm_elf (ibfd))
5e681ec4
PB		 14516 continue;
14517
14518 for (s = ibfd->sections; s != NULL; s = s->next)
14519 {
0bdcacaf 14520 struct elf_dyn_relocs *p;
5e681ec4 14521
0bdcacaf 14522 for (p = (struct elf_dyn_relocs *)
99059e56 14523 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
5e681ec4 14524 {
0bdcacaf
RS		 14525 if (!bfd_is_abs_section (p->sec)
14526 && bfd_is_abs_section (p->sec->output_section))
5e681ec4
PB		 14527 {
14528 /* Input section has been discarded, either because
14529 it is a copy of a linkonce section or due to
14530 linker script /DISCARD/, so we'll be discarding
14531 the relocs too. */
14532 }
3348747a 14533 else if (is_vxworks
0bdcacaf 14534 && strcmp (p->sec->output_section->name,
3348747a
NS		 14535 ".tls_vars") == 0)
14536 {
14537 /* Relocations in vxworks .tls_vars sections are
14538 handled specially by the loader. */
14539 }
5e681ec4
PB		 14540 else if (p->count != 0)
14541 {
0bdcacaf 14542 srel = elf_section_data (p->sec)->sreloc;
47beaa6a 14543 elf32_arm_allocate_dynrelocs (info, srel, p->count);
0bdcacaf 14544 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
5e681ec4
PB		 14545 info->flags |= DF_TEXTREL;
14546 }
14547 }
14548 }
14549
14550 local_got = elf_local_got_refcounts (ibfd);
14551 if (!local_got)
14552 continue;
14553
0ffa91dd 14554 symtab_hdr = & elf_symtab_hdr (ibfd);
5e681ec4
PB		 14555 locsymcount = symtab_hdr->sh_info;
14556 end_local_got = local_got + locsymcount;
34e77a92 14557 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
ba93b8ac 14558 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
0855e32b 14559 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
34e77a92 14560 symndx = 0;
362d30a1
RS		 14561 s = htab->root.sgot;
14562 srel = htab->root.srelgot;
0855e32b 14563 for (; local_got < end_local_got;
34e77a92
RS		 14564 ++local_got, ++local_iplt_ptr, ++local_tls_type,
14565 ++local_tlsdesc_gotent, ++symndx)
5e681ec4 14566 {
0855e32b 14567 *local_tlsdesc_gotent = (bfd_vma) -1;
34e77a92
RS		 14568 local_iplt = *local_iplt_ptr;
14569 if (local_iplt != NULL)
14570 {
14571 struct elf_dyn_relocs *p;
14572
14573 if (local_iplt->root.refcount > 0)
14574 {
14575 elf32_arm_allocate_plt_entry (info, TRUE,
14576 &local_iplt->root,
14577 &local_iplt->arm);
14578 if (local_iplt->arm.noncall_refcount == 0)
14579 /* All references to the PLT are calls, so all
14580 non-call references can resolve directly to the
14581 run-time target. This means that the .got entry
14582 would be the same as the .igot.plt entry, so there's
14583 no point creating both. */
14584 *local_got = 0;
14585 }
14586 else
14587 {
14588 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
14589 local_iplt->root.offset = (bfd_vma) -1;
14590 }
14591
14592 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
14593 {
14594 asection *psrel;
14595
14596 psrel = elf_section_data (p->sec)->sreloc;
14597 if (local_iplt->arm.noncall_refcount == 0)
14598 elf32_arm_allocate_irelocs (info, psrel, p->count);
14599 else
14600 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
14601 }
14602 }
5e681ec4
PB		 14603 if (*local_got > 0)
14604 {
34e77a92
RS		 14605 Elf_Internal_Sym *isym;
14606
eea6121a 14607 *local_got = s->size;
ba93b8ac
DJ		 14608 if (*local_tls_type & GOT_TLS_GD)
14609 /* TLS_GD relocs need an 8-byte structure in the GOT. */
14610 s->size += 8;
0855e32b
NS		 14611 if (*local_tls_type & GOT_TLS_GDESC)
14612 {
14613 *local_tlsdesc_gotent = htab->root.sgotplt->size
14614 - elf32_arm_compute_jump_table_size (htab);
14615 htab->root.sgotplt->size += 8;
14616 *local_got = (bfd_vma) -2;
34e77a92 14617 /* plt.got_offset needs to know there's a TLS_DESC
0855e32b 14618 reloc in the middle of .got.plt. */
99059e56 14619 htab->num_tls_desc++;
0855e32b 14620 }
ba93b8ac
DJ		 14621 if (*local_tls_type & GOT_TLS_IE)
14622 s->size += 4;
ba93b8ac 14623
0855e32b
NS		 14624 if (*local_tls_type & GOT_NORMAL)
14625 {
14626 /* If the symbol is both GD and GDESC, *local_got
14627 may have been overwritten. */
14628 *local_got = s->size;
14629 s->size += 4;
14630 }
14631
34e77a92
RS		 14632 isym = bfd_sym_from_r_symndx (&htab->sym_cache, ibfd, symndx);
14633 if (isym == NULL)
14634 return FALSE;
14635
14636 /* If all references to an STT_GNU_IFUNC PLT are calls,
14637 then all non-call references, including this GOT entry,
14638 resolve directly to the run-time target. */
14639 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
14640 && (local_iplt == NULL
14641 || local_iplt->arm.noncall_refcount == 0))
14642 elf32_arm_allocate_irelocs (info, srel, 1);
0e1862bb 14643 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC)
0855e32b 14644 {
0e1862bb 14645 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC))
3064e1ff
JB		 14646 || *local_tls_type & GOT_TLS_GD)
14647 elf32_arm_allocate_dynrelocs (info, srel, 1);
99059e56 14648
0e1862bb 14649 if (bfd_link_pic (info) && *local_tls_type & GOT_TLS_GDESC)
3064e1ff
JB		 14650 {
14651 elf32_arm_allocate_dynrelocs (info,
14652 htab->root.srelplt, 1);
14653 htab->tls_trampoline = -1;
14654 }
0855e32b 14655 }
5e681ec4
PB		 14656 }
14657 else
14658 *local_got = (bfd_vma) -1;
14659 }
252b5132
RH		 14660 }
14661
ba93b8ac
DJ		 14662 if (htab->tls_ldm_got.refcount > 0)
14663 {
14664 /* Allocate two GOT entries and one dynamic relocation (if necessary)
14665 for R_ARM_TLS_LDM32 relocations. */
362d30a1
RS		 14666 htab->tls_ldm_got.offset = htab->root.sgot->size;
14667 htab->root.sgot->size += 8;
0e1862bb 14668 if (bfd_link_pic (info))
47beaa6a 14669 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
ba93b8ac
DJ		 14670 }
14671 else
14672 htab->tls_ldm_got.offset = -1;
14673
5e681ec4
PB		 14674 /* Allocate global sym .plt and .got entries, and space for global
14675 sym dynamic relocs. */
47beaa6a 14676 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
252b5132 14677
d504ffc8 14678 /* Here we rummage through the found bfds to collect glue information. */
c72f2fb2 14679 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
c7b8f16e 14680 {
0ffa91dd 14681 if (! is_arm_elf (ibfd))
e44a2c9c
AM		 14682 continue;
14683
c7b8f16e
JB		 14684 /* Initialise mapping tables for code/data. */
14685 bfd_elf32_arm_init_maps (ibfd);
906e58ca 14686
c7b8f16e 14687 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
a504d23a
LA		 14688 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
14689 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
99059e56
RM		 14690 /* xgettext:c-format */
14691 _bfd_error_handler (_("Errors encountered processing file %s"),
c7b8f16e
JB		 14692 ibfd->filename);
14693 }
d504ffc8 14694
3e6b1042
DJ		 14695 /* Allocate space for the glue sections now that we've sized them. */
14696 bfd_elf32_arm_allocate_interworking_sections (info);
14697
0855e32b
NS		 14698 /* For every jump slot reserved in the sgotplt, reloc_count is
14699 incremented. However, when we reserve space for TLS descriptors,
14700 it's not incremented, so in order to compute the space reserved
14701 for them, it suffices to multiply the reloc count by the jump
14702 slot size. */
14703 if (htab->root.srelplt)
14704 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size(htab);
14705
14706 if (htab->tls_trampoline)
14707 {
14708 if (htab->root.splt->size == 0)
14709 htab->root.splt->size += htab->plt_header_size;
b38cadfb 14710
0855e32b
NS		 14711 htab->tls_trampoline = htab->root.splt->size;
14712 htab->root.splt->size += htab->plt_entry_size;
b38cadfb 14713
0855e32b 14714 /* If we're not using lazy TLS relocations, don't generate the
99059e56 14715 PLT and GOT entries they require. */
0855e32b
NS		 14716 if (!(info->flags & DF_BIND_NOW))
14717 {
14718 htab->dt_tlsdesc_got = htab->root.sgot->size;
14719 htab->root.sgot->size += 4;
14720
14721 htab->dt_tlsdesc_plt = htab->root.splt->size;
14722 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
14723 }
14724 }
14725
252b5132
RH		 14726 /* The check_relocs and adjust_dynamic_symbol entry points have
14727 determined the sizes of the various dynamic sections. Allocate
14728 memory for them. */
b34976b6
AM		 14729 plt = FALSE;
14730 relocs = FALSE;
252b5132
RH		 14731 for (s = dynobj->sections; s != NULL; s = s->next)
14732 {
14733 const char * name;
252b5132
RH		 14734
14735 if ((s->flags & SEC_LINKER_CREATED) == 0)
14736 continue;
14737
14738 /* It's OK to base decisions on the section name, because none
14739 of the dynobj section names depend upon the input files. */
14740 name = bfd_get_section_name (dynobj, s);
14741
34e77a92 14742 if (s == htab->root.splt)
252b5132 14743 {
c456f082
AM		 14744 /* Remember whether there is a PLT. */
14745 plt = s->size != 0;
252b5132 14746 }
0112cd26 14747 else if (CONST_STRNEQ (name, ".rel"))
252b5132 14748 {
c456f082 14749 if (s->size != 0)
252b5132 14750 {
252b5132 14751 /* Remember whether there are any reloc sections other
00a97672 14752 than .rel(a).plt and .rela.plt.unloaded. */
362d30a1 14753 if (s != htab->root.srelplt && s != htab->srelplt2)
b34976b6 14754 relocs = TRUE;
252b5132
RH		 14755
14756 /* We use the reloc_count field as a counter if we need
14757 to copy relocs into the output file. */
14758 s->reloc_count = 0;
14759 }
14760 }
34e77a92
RS		 14761 else if (s != htab->root.sgot
14762 && s != htab->root.sgotplt
14763 && s != htab->root.iplt
14764 && s != htab->root.igotplt
14765 && s != htab->sdynbss)
252b5132
RH		 14766 {
14767 /* It's not one of our sections, so don't allocate space. */
14768 continue;
14769 }
14770
c456f082 14771 if (s->size == 0)
252b5132 14772 {
c456f082 14773 /* If we don't need this section, strip it from the
00a97672
RS		 14774 output file. This is mostly to handle .rel(a).bss and
14775 .rel(a).plt. We must create both sections in
c456f082
AM		 14776 create_dynamic_sections, because they must be created
14777 before the linker maps input sections to output
14778 sections. The linker does that before
14779 adjust_dynamic_symbol is called, and it is that
14780 function which decides whether anything needs to go
14781 into these sections. */
8423293d 14782 s->flags |= SEC_EXCLUDE;
252b5132
RH		 14783 continue;
14784 }
14785
c456f082
AM		 14786 if ((s->flags & SEC_HAS_CONTENTS) == 0)
14787 continue;
14788
252b5132 14789 /* Allocate memory for the section contents. */
21d799b5 14790 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
c456f082 14791 if (s->contents == NULL)
b34976b6 14792 return FALSE;
252b5132
RH		 14793 }
14794
14795 if (elf_hash_table (info)->dynamic_sections_created)
14796 {
14797 /* Add some entries to the .dynamic section. We fill in the
14798 values later, in elf32_arm_finish_dynamic_sections, but we
14799 must add the entries now so that we get the correct size for
14800 the .dynamic section. The DT_DEBUG entry is filled in by the
14801 dynamic linker and used by the debugger. */
dc810e39 14802#define add_dynamic_entry(TAG, VAL) \
5a580b3a 14803 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
dc810e39 14804
0e1862bb 14805 if (bfd_link_executable (info))
252b5132 14806 {
dc810e39 14807 if (!add_dynamic_entry (DT_DEBUG, 0))
b34976b6 14808 return FALSE;
252b5132
RH		 14809 }
14810
14811 if (plt)
14812 {
dc810e39
AM		 14813 if ( !add_dynamic_entry (DT_PLTGOT, 0)
14814 || !add_dynamic_entry (DT_PLTRELSZ, 0)
00a97672
RS		 14815 || !add_dynamic_entry (DT_PLTREL,
14816 htab->use_rel ? DT_REL : DT_RELA)
dc810e39 14817 || !add_dynamic_entry (DT_JMPREL, 0))
b34976b6 14818 return FALSE;
0855e32b
NS		 14819
14820 if (htab->dt_tlsdesc_plt &&
b38cadfb 14821 (!add_dynamic_entry (DT_TLSDESC_PLT,0)
0855e32b 14822 || !add_dynamic_entry (DT_TLSDESC_GOT,0)))
b38cadfb 14823 return FALSE;
252b5132
RH		 14824 }
14825
14826 if (relocs)
14827 {
00a97672
RS		 14828 if (htab->use_rel)
14829 {
14830 if (!add_dynamic_entry (DT_REL, 0)
14831 || !add_dynamic_entry (DT_RELSZ, 0)
14832 || !add_dynamic_entry (DT_RELENT, RELOC_SIZE (htab)))
14833 return FALSE;
14834 }
14835 else
14836 {
14837 if (!add_dynamic_entry (DT_RELA, 0)
14838 || !add_dynamic_entry (DT_RELASZ, 0)
14839 || !add_dynamic_entry (DT_RELAENT, RELOC_SIZE (htab)))
14840 return FALSE;
14841 }
252b5132
RH		 14842 }
14843
08d1f311
DJ		 14844 /* If any dynamic relocs apply to a read-only section,
14845 then we need a DT_TEXTREL entry. */
14846 if ((info->flags & DF_TEXTREL) == 0)
8029a119
NC		 14847 elf_link_hash_traverse (& htab->root, elf32_arm_readonly_dynrelocs,
14848 info);
08d1f311 14849
99e4ae17 14850 if ((info->flags & DF_TEXTREL) != 0)
252b5132 14851 {
dc810e39 14852 if (!add_dynamic_entry (DT_TEXTREL, 0))
b34976b6 14853 return FALSE;
252b5132 14854 }
7a2b07ff
NS		 14855 if (htab->vxworks_p
14856 && !elf_vxworks_add_dynamic_entries (output_bfd, info))
14857 return FALSE;
252b5132 14858 }
8532796c 14859#undef add_dynamic_entry
252b5132 14860
b34976b6 14861 return TRUE;
252b5132
RH		 14862}
14863
0855e32b
NS		 14864/* Size sections even though they're not dynamic. We use it to setup
14865 _TLS_MODULE_BASE_, if needed. */
14866
14867static bfd_boolean
14868elf32_arm_always_size_sections (bfd *output_bfd,
99059e56 14869 struct bfd_link_info *info)
0855e32b
NS		 14870{
14871 asection *tls_sec;
14872
0e1862bb 14873 if (bfd_link_relocatable (info))
0855e32b
NS		 14874 return TRUE;
14875
14876 tls_sec = elf_hash_table (info)->tls_sec;
14877
14878 if (tls_sec)
14879 {
14880 struct elf_link_hash_entry *tlsbase;
14881
14882 tlsbase = elf_link_hash_lookup
14883 (elf_hash_table (info), "_TLS_MODULE_BASE_", TRUE, TRUE, FALSE);
14884
14885 if (tlsbase)
99059e56
RM		 14886 {
14887 struct bfd_link_hash_entry *bh = NULL;
0855e32b 14888 const struct elf_backend_data *bed
99059e56 14889 = get_elf_backend_data (output_bfd);
0855e32b 14890
99059e56 14891 if (!(_bfd_generic_link_add_one_symbol
0855e32b
NS		 14892 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
14893 tls_sec, 0, NULL, FALSE,
14894 bed->collect, &bh)))
14895 return FALSE;
b38cadfb 14896
99059e56
RM		 14897 tlsbase->type = STT_TLS;
14898 tlsbase = (struct elf_link_hash_entry *)bh;
14899 tlsbase->def_regular = 1;
14900 tlsbase->other = STV_HIDDEN;
14901 (*bed->elf_backend_hide_symbol) (info, tlsbase, TRUE);
0855e32b
NS		 14902 }
14903 }
14904 return TRUE;
14905}
14906
252b5132
RH		 14907/* Finish up dynamic symbol handling. We set the contents of various
14908 dynamic sections here. */
14909
b34976b6 14910static bfd_boolean
906e58ca
NC		 14911elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
14912 struct bfd_link_info * info,
14913 struct elf_link_hash_entry * h,
14914 Elf_Internal_Sym * sym)
252b5132 14915{
e5a52504 14916 struct elf32_arm_link_hash_table *htab;
b7693d02 14917 struct elf32_arm_link_hash_entry *eh;
252b5132 14918
e5a52504 14919 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 14920 if (htab == NULL)
14921 return FALSE;
14922
b7693d02 14923 eh = (struct elf32_arm_link_hash_entry *) h;
252b5132
RH		 14924
14925 if (h->plt.offset != (bfd_vma) -1)
14926 {
34e77a92 14927 if (!eh->is_iplt)
e5a52504 14928 {
34e77a92 14929 BFD_ASSERT (h->dynindx != -1);
57460bcf
NC		 14930 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
14931 h->dynindx, 0))
14932 return FALSE;
e5a52504 14933 }
57e8b36a 14934
f5385ebf 14935 if (!h->def_regular)
252b5132
RH		 14936 {
14937 /* Mark the symbol as undefined, rather than as defined in
3a635617 14938 the .plt section. */
252b5132 14939 sym->st_shndx = SHN_UNDEF;
3a635617 14940 /* If the symbol is weak we need to clear the value.
d982ba73
PB		 14941 Otherwise, the PLT entry would provide a definition for
14942 the symbol even if the symbol wasn't defined anywhere,
3a635617
WN		 14943 and so the symbol would never be NULL. Leave the value if
14944 there were any relocations where pointer equality matters
14945 (this is a clue for the dynamic linker, to make function
14946 pointer comparisons work between an application and shared
14947 library). */
97323ad1 14948 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
d982ba73 14949 sym->st_value = 0;
252b5132 14950 }
34e77a92
RS		 14951 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
14952 {
14953 /* At least one non-call relocation references this .iplt entry,
14954 so the .iplt entry is the function's canonical address. */
14955 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
14956 sym->st_target_internal = ST_BRANCH_TO_ARM;
14957 sym->st_shndx = (_bfd_elf_section_from_bfd_section
14958 (output_bfd, htab->root.iplt->output_section));
14959 sym->st_value = (h->plt.offset
14960 + htab->root.iplt->output_section->vma
14961 + htab->root.iplt->output_offset);
14962 }
252b5132
RH		 14963 }
14964
f5385ebf 14965 if (h->needs_copy)
252b5132
RH		 14966 {
14967 asection * s;
947216bf 14968 Elf_Internal_Rela rel;
252b5132
RH		 14969
14970 /* This symbol needs a copy reloc. Set it up. */
252b5132
RH		 14971 BFD_ASSERT (h->dynindx != -1
14972 && (h->root.type == bfd_link_hash_defined
14973 || h->root.type == bfd_link_hash_defweak));
14974
362d30a1 14975 s = htab->srelbss;
252b5132
RH		 14976 BFD_ASSERT (s != NULL);
14977
00a97672 14978 rel.r_addend = 0;
252b5132
RH		 14979 rel.r_offset = (h->root.u.def.value
14980 + h->root.u.def.section->output_section->vma
14981 + h->root.u.def.section->output_offset);
14982 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
47beaa6a 14983 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
252b5132
RH		 14984 }
14985
00a97672
RS		 14986 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
14987 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
14988 to the ".got" section. */
9637f6ef 14989 if (h == htab->root.hdynamic
00a97672 14990 || (!htab->vxworks_p && h == htab->root.hgot))
252b5132
RH		 14991 sym->st_shndx = SHN_ABS;
14992
b34976b6 14993 return TRUE;
252b5132
RH		 14994}
14995
0855e32b
NS		 14996static void
14997arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
14998 void *contents,
14999 const unsigned long *template, unsigned count)
15000{
15001 unsigned ix;
b38cadfb 15002
0855e32b
NS		 15003 for (ix = 0; ix != count; ix++)
15004 {
15005 unsigned long insn = template[ix];
15006
15007 /* Emit mov pc,rx if bx is not permitted. */
15008 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
15009 insn = (insn & 0xf000000f) | 0x01a0f000;
15010 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
15011 }
15012}
15013
99059e56
RM		 15014/* Install the special first PLT entry for elf32-arm-nacl. Unlike
15015 other variants, NaCl needs this entry in a static executable's
15016 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
15017 zero. For .iplt really only the last bundle is useful, and .iplt
15018 could have a shorter first entry, with each individual PLT entry's
15019 relative branch calculated differently so it targets the last
15020 bundle instead of the instruction before it (labelled .Lplt_tail
15021 above). But it's simpler to keep the size and layout of PLT0
15022 consistent with the dynamic case, at the cost of some dead code at
15023 the start of .iplt and the one dead store to the stack at the start
15024 of .Lplt_tail. */
15025static void
15026arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
15027 asection *plt, bfd_vma got_displacement)
15028{
15029 unsigned int i;
15030
15031 put_arm_insn (htab, output_bfd,
15032 elf32_arm_nacl_plt0_entry[0]
15033 | arm_movw_immediate (got_displacement),
15034 plt->contents + 0);
15035 put_arm_insn (htab, output_bfd,
15036 elf32_arm_nacl_plt0_entry[1]
15037 | arm_movt_immediate (got_displacement),
15038 plt->contents + 4);
15039
15040 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
15041 put_arm_insn (htab, output_bfd,
15042 elf32_arm_nacl_plt0_entry[i],
15043 plt->contents + (i * 4));
15044}
15045
252b5132
RH		 15046/* Finish up the dynamic sections. */
15047
b34976b6 15048static bfd_boolean
57e8b36a 15049elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
252b5132
RH		 15050{
15051 bfd * dynobj;
15052 asection * sgot;
15053 asection * sdyn;
4dfe6ac6
NC		 15054 struct elf32_arm_link_hash_table *htab;
15055
15056 htab = elf32_arm_hash_table (info);
15057 if (htab == NULL)
15058 return FALSE;
252b5132
RH		 15059
15060 dynobj = elf_hash_table (info)->dynobj;
15061
362d30a1 15062 sgot = htab->root.sgotplt;
894891db
NC		 15063 /* A broken linker script might have discarded the dynamic sections.
15064 Catch this here so that we do not seg-fault later on. */
15065 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
15066 return FALSE;
3d4d4302 15067 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
252b5132
RH		 15068
15069 if (elf_hash_table (info)->dynamic_sections_created)
15070 {
15071 asection *splt;
15072 Elf32_External_Dyn *dyncon, *dynconend;
15073
362d30a1 15074 splt = htab->root.splt;
24a1ba0f 15075 BFD_ASSERT (splt != NULL && sdyn != NULL);
cbc704f3 15076 BFD_ASSERT (htab->symbian_p || sgot != NULL);
252b5132
RH		 15077
15078 dyncon = (Elf32_External_Dyn *) sdyn->contents;
eea6121a 15079 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
9b485d32 15080
252b5132
RH		 15081 for (; dyncon < dynconend; dyncon++)
15082 {
15083 Elf_Internal_Dyn dyn;
15084 const char * name;
15085 asection * s;
15086
15087 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
15088
15089 switch (dyn.d_tag)
15090 {
229fcec5
MM		 15091 unsigned int type;
15092
252b5132 15093 default:
7a2b07ff
NS		 15094 if (htab->vxworks_p
15095 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
15096 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
252b5132
RH		 15097 break;
15098
229fcec5
MM		 15099 case DT_HASH:
15100 name = ".hash";
15101 goto get_vma_if_bpabi;
15102 case DT_STRTAB:
15103 name = ".dynstr";
15104 goto get_vma_if_bpabi;
15105 case DT_SYMTAB:
15106 name = ".dynsym";
15107 goto get_vma_if_bpabi;
c0042f5d
MM		 15108 case DT_VERSYM:
15109 name = ".gnu.version";
15110 goto get_vma_if_bpabi;
15111 case DT_VERDEF:
15112 name = ".gnu.version_d";
15113 goto get_vma_if_bpabi;
15114 case DT_VERNEED:
15115 name = ".gnu.version_r";
15116 goto get_vma_if_bpabi;
15117
252b5132
RH		 15118 case DT_PLTGOT:
15119 name = ".got";
15120 goto get_vma;
15121 case DT_JMPREL:
00a97672 15122 name = RELOC_SECTION (htab, ".plt");
252b5132
RH		 15123 get_vma:
15124 s = bfd_get_section_by_name (output_bfd, name);
05456594
NC		 15125 if (s == NULL)
15126 {
15127 /* PR ld/14397: Issue an error message if a required section is missing. */
15128 (*_bfd_error_handler)
15129 (_("error: required section '%s' not found in the linker script"), name);
15130 bfd_set_error (bfd_error_invalid_operation);
15131 return FALSE;
15132 }
229fcec5
MM		 15133 if (!htab->symbian_p)
15134 dyn.d_un.d_ptr = s->vma;
15135 else
15136 /* In the BPABI, tags in the PT_DYNAMIC section point
15137 at the file offset, not the memory address, for the
15138 convenience of the post linker. */
15139 dyn.d_un.d_ptr = s->filepos;
252b5132
RH		 15140 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15141 break;
15142
229fcec5
MM		 15143 get_vma_if_bpabi:
15144 if (htab->symbian_p)
15145 goto get_vma;
15146 break;
15147
252b5132 15148 case DT_PLTRELSZ:
362d30a1 15149 s = htab->root.srelplt;
252b5132 15150 BFD_ASSERT (s != NULL);
eea6121a 15151 dyn.d_un.d_val = s->size;
252b5132
RH		 15152 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15153 break;
906e58ca 15154
252b5132 15155 case DT_RELSZ:
00a97672 15156 case DT_RELASZ:
229fcec5
MM		 15157 if (!htab->symbian_p)
15158 {
15159 /* My reading of the SVR4 ABI indicates that the
15160 procedure linkage table relocs (DT_JMPREL) should be
15161 included in the overall relocs (DT_REL). This is
15162 what Solaris does. However, UnixWare can not handle
15163 that case. Therefore, we override the DT_RELSZ entry
15164 here to make it not include the JMPREL relocs. Since
00a97672 15165 the linker script arranges for .rel(a).plt to follow all
229fcec5
MM		 15166 other relocation sections, we don't have to worry
15167 about changing the DT_REL entry. */
362d30a1 15168 s = htab->root.srelplt;
229fcec5
MM		 15169 if (s != NULL)
15170 dyn.d_un.d_val -= s->size;
15171 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15172 break;
15173 }
8029a119 15174 /* Fall through. */
229fcec5
MM		 15175
15176 case DT_REL:
15177 case DT_RELA:
229fcec5
MM		 15178 /* In the BPABI, the DT_REL tag must point at the file
15179 offset, not the VMA, of the first relocation
15180 section. So, we use code similar to that in
15181 elflink.c, but do not check for SHF_ALLOC on the
15182 relcoation section, since relocations sections are
15183 never allocated under the BPABI. The comments above
15184 about Unixware notwithstanding, we include all of the
15185 relocations here. */
15186 if (htab->symbian_p)
15187 {
15188 unsigned int i;
15189 type = ((dyn.d_tag == DT_REL || dyn.d_tag == DT_RELSZ)
15190 ? SHT_REL : SHT_RELA);
15191 dyn.d_un.d_val = 0;
15192 for (i = 1; i < elf_numsections (output_bfd); i++)
15193 {
906e58ca 15194 Elf_Internal_Shdr *hdr
229fcec5
MM		 15195 = elf_elfsections (output_bfd)[i];
15196 if (hdr->sh_type == type)
15197 {
906e58ca 15198 if (dyn.d_tag == DT_RELSZ
229fcec5
MM		 15199 || dyn.d_tag == DT_RELASZ)
15200 dyn.d_un.d_val += hdr->sh_size;
de52dba4
AM		 15201 else if ((ufile_ptr) hdr->sh_offset
15202 <= dyn.d_un.d_val - 1)
229fcec5
MM		 15203 dyn.d_un.d_val = hdr->sh_offset;
15204 }
15205 }
15206 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15207 }
252b5132 15208 break;
88f7bcd5 15209
0855e32b 15210 case DT_TLSDESC_PLT:
99059e56 15211 s = htab->root.splt;
0855e32b
NS		 15212 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
15213 + htab->dt_tlsdesc_plt);
15214 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15215 break;
15216
15217 case DT_TLSDESC_GOT:
99059e56 15218 s = htab->root.sgot;
0855e32b 15219 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
99059e56 15220 + htab->dt_tlsdesc_got);
0855e32b
NS		 15221 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
15222 break;
15223
88f7bcd5
NC		 15224 /* Set the bottom bit of DT_INIT/FINI if the
15225 corresponding function is Thumb. */
15226 case DT_INIT:
15227 name = info->init_function;
15228 goto get_sym;
15229 case DT_FINI:
15230 name = info->fini_function;
15231 get_sym:
15232 /* If it wasn't set by elf_bfd_final_link
4cc11e76 15233 then there is nothing to adjust. */
88f7bcd5
NC		 15234 if (dyn.d_un.d_val != 0)
15235 {
15236 struct elf_link_hash_entry * eh;
15237
15238 eh = elf_link_hash_lookup (elf_hash_table (info), name,
b34976b6 15239 FALSE, FALSE, TRUE);
35fc36a8 15240 if (eh != NULL && eh->target_internal == ST_BRANCH_TO_THUMB)
88f7bcd5
NC		 15241 {
15242 dyn.d_un.d_val |= 1;
b34976b6 15243 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
88f7bcd5
NC		 15244 }
15245 }
15246 break;
252b5132
RH		 15247 }
15248 }
15249
24a1ba0f 15250 /* Fill in the first entry in the procedure linkage table. */
4dfe6ac6 15251 if (splt->size > 0 && htab->plt_header_size)
f7a74f8c 15252 {
00a97672
RS		 15253 const bfd_vma *plt0_entry;
15254 bfd_vma got_address, plt_address, got_displacement;
15255
15256 /* Calculate the addresses of the GOT and PLT. */
15257 got_address = sgot->output_section->vma + sgot->output_offset;
15258 plt_address = splt->output_section->vma + splt->output_offset;
15259
15260 if (htab->vxworks_p)
15261 {
15262 /* The VxWorks GOT is relocated by the dynamic linker.
15263 Therefore, we must emit relocations rather than simply
15264 computing the values now. */
15265 Elf_Internal_Rela rel;
15266
15267 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
52ab56c2
PB		 15268 put_arm_insn (htab, output_bfd, plt0_entry[0],
15269 splt->contents + 0);
15270 put_arm_insn (htab, output_bfd, plt0_entry[1],
15271 splt->contents + 4);
15272 put_arm_insn (htab, output_bfd, plt0_entry[2],
15273 splt->contents + 8);
00a97672
RS		 15274 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
15275
8029a119 15276 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
00a97672
RS		 15277 rel.r_offset = plt_address + 12;
15278 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
15279 rel.r_addend = 0;
15280 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
15281 htab->srelplt2->contents);
15282 }
b38cadfb 15283 else if (htab->nacl_p)
99059e56
RM		 15284 arm_nacl_put_plt0 (htab, output_bfd, splt,
15285 got_address + 8 - (plt_address + 16));
eed94f8f
NC		 15286 else if (using_thumb_only (htab))
15287 {
15288 got_displacement = got_address - (plt_address + 12);
15289
15290 plt0_entry = elf32_thumb2_plt0_entry;
15291 put_arm_insn (htab, output_bfd, plt0_entry[0],
15292 splt->contents + 0);
15293 put_arm_insn (htab, output_bfd, plt0_entry[1],
15294 splt->contents + 4);
15295 put_arm_insn (htab, output_bfd, plt0_entry[2],
15296 splt->contents + 8);
15297
15298 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
15299 }
00a97672
RS		 15300 else
15301 {
15302 got_displacement = got_address - (plt_address + 16);
15303
15304 plt0_entry = elf32_arm_plt0_entry;
52ab56c2
PB		 15305 put_arm_insn (htab, output_bfd, plt0_entry[0],
15306 splt->contents + 0);
15307 put_arm_insn (htab, output_bfd, plt0_entry[1],
15308 splt->contents + 4);
15309 put_arm_insn (htab, output_bfd, plt0_entry[2],
15310 splt->contents + 8);
15311 put_arm_insn (htab, output_bfd, plt0_entry[3],
15312 splt->contents + 12);
5e681ec4 15313
5e681ec4 15314#ifdef FOUR_WORD_PLT
00a97672
RS		 15315 /* The displacement value goes in the otherwise-unused
15316 last word of the second entry. */
15317 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
5e681ec4 15318#else
00a97672 15319 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
5e681ec4 15320#endif
00a97672 15321 }
f7a74f8c 15322 }
252b5132
RH		 15323
15324 /* UnixWare sets the entsize of .plt to 4, although that doesn't
15325 really seem like the right value. */
74541ad4
AM		 15326 if (splt->output_section->owner == output_bfd)
15327 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
00a97672 15328
0855e32b
NS		 15329 if (htab->dt_tlsdesc_plt)
15330 {
15331 bfd_vma got_address
15332 = sgot->output_section->vma + sgot->output_offset;
15333 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
15334 + htab->root.sgot->output_offset);
15335 bfd_vma plt_address
15336 = splt->output_section->vma + splt->output_offset;
15337
b38cadfb 15338 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 15339 splt->contents + htab->dt_tlsdesc_plt,
15340 dl_tlsdesc_lazy_trampoline, 6);
15341
15342 bfd_put_32 (output_bfd,
15343 gotplt_address + htab->dt_tlsdesc_got
15344 - (plt_address + htab->dt_tlsdesc_plt)
15345 - dl_tlsdesc_lazy_trampoline[6],
15346 splt->contents + htab->dt_tlsdesc_plt + 24);
15347 bfd_put_32 (output_bfd,
15348 got_address - (plt_address + htab->dt_tlsdesc_plt)
15349 - dl_tlsdesc_lazy_trampoline[7],
15350 splt->contents + htab->dt_tlsdesc_plt + 24 + 4);
15351 }
15352
15353 if (htab->tls_trampoline)
15354 {
b38cadfb 15355 arm_put_trampoline (htab, output_bfd,
0855e32b
NS		 15356 splt->contents + htab->tls_trampoline,
15357 tls_trampoline, 3);
15358#ifdef FOUR_WORD_PLT
15359 bfd_put_32 (output_bfd, 0x00000000,
15360 splt->contents + htab->tls_trampoline + 12);
b38cadfb 15361#endif
0855e32b
NS		 15362 }
15363
0e1862bb
L		 15364 if (htab->vxworks_p
15365 && !bfd_link_pic (info)
15366 && htab->root.splt->size > 0)
00a97672
RS		 15367 {
15368 /* Correct the .rel(a).plt.unloaded relocations. They will have
15369 incorrect symbol indexes. */
15370 int num_plts;
eed62c48 15371 unsigned char *p;
00a97672 15372
362d30a1 15373 num_plts = ((htab->root.splt->size - htab->plt_header_size)
00a97672
RS		 15374 / htab->plt_entry_size);
15375 p = htab->srelplt2->contents + RELOC_SIZE (htab);
15376
15377 for (; num_plts; num_plts--)
15378 {
15379 Elf_Internal_Rela rel;
15380
15381 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
15382 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
15383 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
15384 p += RELOC_SIZE (htab);
15385
15386 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
15387 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
15388 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
15389 p += RELOC_SIZE (htab);
15390 }
15391 }
252b5132
RH		 15392 }
15393
99059e56
RM		 15394 if (htab->nacl_p && htab->root.iplt != NULL && htab->root.iplt->size > 0)
15395 /* NaCl uses a special first entry in .iplt too. */
15396 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
15397
252b5132 15398 /* Fill in the first three entries in the global offset table. */
229fcec5 15399 if (sgot)
252b5132 15400 {
229fcec5
MM		 15401 if (sgot->size > 0)
15402 {
15403 if (sdyn == NULL)
15404 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
15405 else
15406 bfd_put_32 (output_bfd,
15407 sdyn->output_section->vma + sdyn->output_offset,
15408 sgot->contents);
15409 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
15410 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
15411 }
252b5132 15412
229fcec5
MM		 15413 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
15414 }
252b5132 15415
b34976b6 15416 return TRUE;
252b5132
RH		 15417}
15418
ba96a88f 15419static void
57e8b36a 15420elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
ba96a88f 15421{
9b485d32 15422 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
e489d0ae 15423 struct elf32_arm_link_hash_table *globals;
ac4c9b04 15424 struct elf_segment_map *m;
ba96a88f
NC		 15425
15426 i_ehdrp = elf_elfheader (abfd);
15427
94a3258f
PB		 15428 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
15429 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
15430 else
7394f108 15431 _bfd_elf_post_process_headers (abfd, link_info);
ba96a88f 15432 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
e489d0ae 15433
93204d3a
PB		 15434 if (link_info)
15435 {
15436 globals = elf32_arm_hash_table (link_info);
4dfe6ac6 15437 if (globals != NULL && globals->byteswap_code)
93204d3a
PB		 15438 i_ehdrp->e_flags |= EF_ARM_BE8;
15439 }
3bfcb652
NC		 15440
15441 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
15442 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
15443 {
15444 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
5c294fee 15445 if (abi == AEABI_VFP_args_vfp)
3bfcb652
NC		 15446 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
15447 else
15448 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
15449 }
ac4c9b04
MG		 15450
15451 /* Scan segment to set p_flags attribute if it contains only sections with
15452 SHF_ARM_NOREAD flag. */
15453 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
15454 {
15455 unsigned int j;
15456
15457 if (m->count == 0)
15458 continue;
15459 for (j = 0; j < m->count; j++)
15460 {
15461 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_NOREAD))
15462 break;
15463 }
15464 if (j == m->count)
15465 {
15466 m->p_flags = PF_X;
15467 m->p_flags_valid = 1;
15468 }
15469 }
ba96a88f
NC		 15470}
15471
99e4ae17 15472static enum elf_reloc_type_class
7e612e98
AM		 15473elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
15474 const asection *rel_sec ATTRIBUTE_UNUSED,
15475 const Elf_Internal_Rela *rela)
99e4ae17 15476{
f51e552e 15477 switch ((int) ELF32_R_TYPE (rela->r_info))
99e4ae17
AJ		 15478 {
15479 case R_ARM_RELATIVE:
15480 return reloc_class_relative;
15481 case R_ARM_JUMP_SLOT:
15482 return reloc_class_plt;
15483 case R_ARM_COPY:
15484 return reloc_class_copy;
15485 default:
15486 return reloc_class_normal;
15487 }
15488}
15489
e489d0ae 15490static void
57e8b36a 15491elf32_arm_final_write_processing (bfd *abfd, bfd_boolean linker ATTRIBUTE_UNUSED)
e16bb312 15492{
5a6c6817 15493 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
e16bb312
NC		 15494}
15495
40a18ebd
NC		 15496/* Return TRUE if this is an unwinding table entry. */
15497
15498static bfd_boolean
15499is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
15500{
0112cd26
NC		 15501 return (CONST_STRNEQ (name, ELF_STRING_ARM_unwind)
15502 || CONST_STRNEQ (name, ELF_STRING_ARM_unwind_once));
40a18ebd
NC		 15503}
15504
15505
15506/* Set the type and flags for an ARM section. We do this by
15507 the section name, which is a hack, but ought to work. */
15508
15509static bfd_boolean
15510elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
15511{
15512 const char * name;
15513
15514 name = bfd_get_section_name (abfd, sec);
15515
15516 if (is_arm_elf_unwind_section_name (abfd, name))
15517 {
15518 hdr->sh_type = SHT_ARM_EXIDX;
15519 hdr->sh_flags |= SHF_LINK_ORDER;
15520 }
ac4c9b04
MG		 15521
15522 if (sec->flags & SEC_ELF_NOREAD)
15523 hdr->sh_flags |= SHF_ARM_NOREAD;
15524
40a18ebd
NC		 15525 return TRUE;
15526}
15527
6dc132d9
L		 15528/* Handle an ARM specific section when reading an object file. This is
15529 called when bfd_section_from_shdr finds a section with an unknown
15530 type. */
40a18ebd
NC		 15531
15532static bfd_boolean
15533elf32_arm_section_from_shdr (bfd *abfd,
15534 Elf_Internal_Shdr * hdr,
6dc132d9
L		 15535 const char *name,
15536 int shindex)
40a18ebd
NC		 15537{
15538 /* There ought to be a place to keep ELF backend specific flags, but
15539 at the moment there isn't one. We just keep track of the
15540 sections by their name, instead. Fortunately, the ABI gives
15541 names for all the ARM specific sections, so we will probably get
15542 away with this. */
15543 switch (hdr->sh_type)
15544 {
15545 case SHT_ARM_EXIDX:
0951f019
RE		 15546 case SHT_ARM_PREEMPTMAP:
15547 case SHT_ARM_ATTRIBUTES:
40a18ebd
NC		 15548 break;
15549
15550 default:
15551 return FALSE;
15552 }
15553
6dc132d9 15554 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
40a18ebd
NC		 15555 return FALSE;
15556
15557 return TRUE;
15558}
e489d0ae 15559
44444f50
NC		 15560static _arm_elf_section_data *
15561get_arm_elf_section_data (asection * sec)
15562{
47b2e99c
JZ		 15563 if (sec && sec->owner && is_arm_elf (sec->owner))
15564 return elf32_arm_section_data (sec);
44444f50
NC		 15565 else
15566 return NULL;
8e3de13a
NC		 15567}
15568
4e617b1e
PB		 15569typedef struct
15570{
57402f1e 15571 void *flaginfo;
4e617b1e 15572 struct bfd_link_info *info;
91a5743d
PB		 15573 asection *sec;
15574 int sec_shndx;
6e0b88f1
AM		 15575 int (*func) (void *, const char *, Elf_Internal_Sym *,
15576 asection *, struct elf_link_hash_entry *);
4e617b1e
PB		 15577} output_arch_syminfo;
15578
15579enum map_symbol_type
15580{
15581 ARM_MAP_ARM,
15582 ARM_MAP_THUMB,
15583 ARM_MAP_DATA
15584};
15585
15586
7413f23f 15587/* Output a single mapping symbol. */
4e617b1e
PB		 15588
15589static bfd_boolean
7413f23f
DJ		 15590elf32_arm_output_map_sym (output_arch_syminfo *osi,
15591 enum map_symbol_type type,
15592 bfd_vma offset)
4e617b1e
PB		 15593{
15594 static const char *names[3] = {"$a", "$t", "$d"};
4e617b1e
PB		 15595 Elf_Internal_Sym sym;
15596
91a5743d
PB		 15597 sym.st_value = osi->sec->output_section->vma
15598 + osi->sec->output_offset
15599 + offset;
4e617b1e
PB		 15600 sym.st_size = 0;
15601 sym.st_other = 0;
15602 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
91a5743d 15603 sym.st_shndx = osi->sec_shndx;
35fc36a8 15604 sym.st_target_internal = 0;
fe33d2fa 15605 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
57402f1e 15606 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
4e617b1e
PB		 15607}
15608
34e77a92
RS		 15609/* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
15610 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
4e617b1e
PB		 15611
15612static bfd_boolean
34e77a92
RS		 15613elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
15614 bfd_boolean is_iplt_entry_p,
15615 union gotplt_union *root_plt,
15616 struct arm_plt_info *arm_plt)
4e617b1e 15617{
4e617b1e 15618 struct elf32_arm_link_hash_table *htab;
34e77a92 15619 bfd_vma addr, plt_header_size;
4e617b1e 15620
34e77a92 15621 if (root_plt->offset == (bfd_vma) -1)
4e617b1e
PB		 15622 return TRUE;
15623
4dfe6ac6
NC		 15624 htab = elf32_arm_hash_table (osi->info);
15625 if (htab == NULL)
15626 return FALSE;
15627
34e77a92
RS		 15628 if (is_iplt_entry_p)
15629 {
15630 osi->sec = htab->root.iplt;
15631 plt_header_size = 0;
15632 }
15633 else
15634 {
15635 osi->sec = htab->root.splt;
15636 plt_header_size = htab->plt_header_size;
15637 }
15638 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
15639 (osi->info->output_bfd, osi->sec->output_section));
15640
15641 addr = root_plt->offset & -2;
4e617b1e
PB		 15642 if (htab->symbian_p)
15643 {
7413f23f 15644 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15645 return FALSE;
7413f23f 15646 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 4))
4e617b1e
PB		 15647 return FALSE;
15648 }
15649 else if (htab->vxworks_p)
15650 {
7413f23f 15651 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15652 return FALSE;
7413f23f 15653 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
4e617b1e 15654 return FALSE;
7413f23f 15655 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
4e617b1e 15656 return FALSE;
7413f23f 15657 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
4e617b1e
PB		 15658 return FALSE;
15659 }
b38cadfb
NC		 15660 else if (htab->nacl_p)
15661 {
15662 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
15663 return FALSE;
15664 }
eed94f8f
NC		 15665 else if (using_thumb_only (htab))
15666 {
15667 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
15668 return FALSE;
6a631e86 15669 }
4e617b1e
PB		 15670 else
15671 {
34e77a92 15672 bfd_boolean thumb_stub_p;
bd97cb95 15673
34e77a92
RS		 15674 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
15675 if (thumb_stub_p)
4e617b1e 15676 {
7413f23f 15677 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
4e617b1e
PB		 15678 return FALSE;
15679 }
15680#ifdef FOUR_WORD_PLT
7413f23f 15681 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e 15682 return FALSE;
7413f23f 15683 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
4e617b1e
PB		 15684 return FALSE;
15685#else
906e58ca 15686 /* A three-word PLT with no Thumb thunk contains only Arm code,
4e617b1e
PB		 15687 so only need to output a mapping symbol for the first PLT entry and
15688 entries with thumb thunks. */
34e77a92 15689 if (thumb_stub_p || addr == plt_header_size)
4e617b1e 15690 {
7413f23f 15691 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
4e617b1e
PB		 15692 return FALSE;
15693 }
15694#endif
15695 }
15696
15697 return TRUE;
15698}
15699
34e77a92
RS		 15700/* Output mapping symbols for PLT entries associated with H. */
15701
15702static bfd_boolean
15703elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
15704{
15705 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
15706 struct elf32_arm_link_hash_entry *eh;
15707
15708 if (h->root.type == bfd_link_hash_indirect)
15709 return TRUE;
15710
15711 if (h->root.type == bfd_link_hash_warning)
15712 /* When warning symbols are created, they **replace** the "real"
15713 entry in the hash table, thus we never get to see the real
15714 symbol in a hash traversal. So look at it now. */
15715 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15716
15717 eh = (struct elf32_arm_link_hash_entry *) h;
15718 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
15719 &h->plt, &eh->plt);
15720}
15721
7413f23f
DJ		 15722/* Output a single local symbol for a generated stub. */
15723
15724static bfd_boolean
15725elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
15726 bfd_vma offset, bfd_vma size)
15727{
7413f23f
DJ		 15728 Elf_Internal_Sym sym;
15729
7413f23f
DJ		 15730 sym.st_value = osi->sec->output_section->vma
15731 + osi->sec->output_offset
15732 + offset;
15733 sym.st_size = size;
15734 sym.st_other = 0;
15735 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
15736 sym.st_shndx = osi->sec_shndx;
35fc36a8 15737 sym.st_target_internal = 0;
57402f1e 15738 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
7413f23f 15739}
4e617b1e 15740
da5938a2 15741static bfd_boolean
8029a119
NC		 15742arm_map_one_stub (struct bfd_hash_entry * gen_entry,
15743 void * in_arg)
da5938a2
NC		 15744{
15745 struct elf32_arm_stub_hash_entry *stub_entry;
da5938a2
NC		 15746 asection *stub_sec;
15747 bfd_vma addr;
7413f23f 15748 char *stub_name;
9a008db3 15749 output_arch_syminfo *osi;
d3ce72d0 15750 const insn_sequence *template_sequence;
461a49ca
DJ		 15751 enum stub_insn_type prev_type;
15752 int size;
15753 int i;
15754 enum map_symbol_type sym_type;
da5938a2
NC		 15755
15756 /* Massage our args to the form they really have. */
15757 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
9a008db3 15758 osi = (output_arch_syminfo *) in_arg;
da5938a2 15759
da5938a2
NC		 15760 stub_sec = stub_entry->stub_sec;
15761
15762 /* Ensure this stub is attached to the current section being
7413f23f 15763 processed. */
da5938a2
NC		 15764 if (stub_sec != osi->sec)
15765 return TRUE;
15766
7413f23f
DJ		 15767 addr = (bfd_vma) stub_entry->stub_offset;
15768 stub_name = stub_entry->output_name;
da5938a2 15769
d3ce72d0
NC		 15770 template_sequence = stub_entry->stub_template;
15771 switch (template_sequence[0].type)
7413f23f 15772 {
461a49ca
DJ		 15773 case ARM_TYPE:
15774 if (!elf32_arm_output_stub_sym (osi, stub_name, addr, stub_entry->stub_size))
da5938a2
NC		 15775 return FALSE;
15776 break;
461a49ca 15777 case THUMB16_TYPE:
48229727 15778 case THUMB32_TYPE:
461a49ca
DJ		 15779 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
15780 stub_entry->stub_size))
da5938a2
NC		 15781 return FALSE;
15782 break;
15783 default:
15784 BFD_FAIL ();
48229727 15785 return 0;
7413f23f 15786 }
da5938a2 15787
461a49ca
DJ		 15788 prev_type = DATA_TYPE;
15789 size = 0;
15790 for (i = 0; i < stub_entry->stub_template_size; i++)
15791 {
d3ce72d0 15792 switch (template_sequence[i].type)
461a49ca
DJ		 15793 {
15794 case ARM_TYPE:
15795 sym_type = ARM_MAP_ARM;
15796 break;
15797
15798 case THUMB16_TYPE:
48229727 15799 case THUMB32_TYPE:
461a49ca
DJ		 15800 sym_type = ARM_MAP_THUMB;
15801 break;
15802
15803 case DATA_TYPE:
15804 sym_type = ARM_MAP_DATA;
15805 break;
15806
15807 default:
15808 BFD_FAIL ();
4e31c731 15809 return FALSE;
461a49ca
DJ		 15810 }
15811
d3ce72d0 15812 if (template_sequence[i].type != prev_type)
461a49ca 15813 {
d3ce72d0 15814 prev_type = template_sequence[i].type;
461a49ca
DJ		 15815 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
15816 return FALSE;
15817 }
15818
d3ce72d0 15819 switch (template_sequence[i].type)
461a49ca
DJ		 15820 {
15821 case ARM_TYPE:
48229727 15822 case THUMB32_TYPE:
461a49ca
DJ		 15823 size += 4;
15824 break;
15825
15826 case THUMB16_TYPE:
15827 size += 2;
15828 break;
15829
15830 case DATA_TYPE:
15831 size += 4;
15832 break;
15833
15834 default:
15835 BFD_FAIL ();
4e31c731 15836 return FALSE;
461a49ca
DJ		 15837 }
15838 }
15839
da5938a2
NC		 15840 return TRUE;
15841}
15842
33811162
DG		 15843/* Output mapping symbols for linker generated sections,
15844 and for those data-only sections that do not have a
15845 $d. */
4e617b1e
PB		 15846
15847static bfd_boolean
15848elf32_arm_output_arch_local_syms (bfd *output_bfd,
906e58ca 15849 struct bfd_link_info *info,
57402f1e 15850 void *flaginfo,
6e0b88f1
AM		 15851 int (*func) (void *, const char *,
15852 Elf_Internal_Sym *,
15853 asection *,
15854 struct elf_link_hash_entry *))
4e617b1e
PB		 15855{
15856 output_arch_syminfo osi;
15857 struct elf32_arm_link_hash_table *htab;
91a5743d
PB		 15858 bfd_vma offset;
15859 bfd_size_type size;
33811162 15860 bfd *input_bfd;
4e617b1e
PB		 15861
15862 htab = elf32_arm_hash_table (info);
4dfe6ac6
NC		 15863 if (htab == NULL)
15864 return FALSE;
15865
906e58ca 15866 check_use_blx (htab);
91a5743d 15867
57402f1e 15868 osi.flaginfo = flaginfo;
4e617b1e
PB		 15869 osi.info = info;
15870 osi.func = func;
906e58ca 15871
33811162
DG		 15872 /* Add a $d mapping symbol to data-only sections that
15873 don't have any mapping symbol. This may result in (harmless) redundant
15874 mapping symbols. */
15875 for (input_bfd = info->input_bfds;
15876 input_bfd != NULL;
c72f2fb2 15877 input_bfd = input_bfd->link.next)
33811162
DG		 15878 {
15879 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
15880 for (osi.sec = input_bfd->sections;
15881 osi.sec != NULL;
15882 osi.sec = osi.sec->next)
15883 {
15884 if (osi.sec->output_section != NULL
f7dd8c79
DJ		 15885 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
15886 != 0)
33811162
DG		 15887 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
15888 == SEC_HAS_CONTENTS
15889 && get_arm_elf_section_data (osi.sec) != NULL
501abfe0 15890 && get_arm_elf_section_data (osi.sec)->mapcount == 0
7d500b83
CL		 15891 && osi.sec->size > 0
15892 && (osi.sec->flags & SEC_EXCLUDE) == 0)
33811162
DG		 15893 {
15894 osi.sec_shndx = _bfd_elf_section_from_bfd_section
15895 (output_bfd, osi.sec->output_section);
15896 if (osi.sec_shndx != (int)SHN_BAD)
15897 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
15898 }
15899 }
15900 }
15901
91a5743d
PB		 15902 /* ARM->Thumb glue. */
15903 if (htab->arm_glue_size > 0)
15904 {
3d4d4302
AM		 15905 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
15906 ARM2THUMB_GLUE_SECTION_NAME);
91a5743d
PB		 15907
15908 osi.sec_shndx = _bfd_elf_section_from_bfd_section
15909 (output_bfd, osi.sec->output_section);
0e1862bb 15910 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
91a5743d
PB		 15911 || htab->pic_veneer)
15912 size = ARM2THUMB_PIC_GLUE_SIZE;
15913 else if (htab->use_blx)
15914 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
15915 else
15916 size = ARM2THUMB_STATIC_GLUE_SIZE;
4e617b1e 15917
91a5743d
PB		 15918 for (offset = 0; offset < htab->arm_glue_size; offset += size)
15919 {
7413f23f
DJ		 15920 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
15921 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
91a5743d
PB		 15922 }
15923 }
15924
15925 /* Thumb->ARM glue. */
15926 if (htab->thumb_glue_size > 0)
15927 {
3d4d4302
AM		 15928 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
15929 THUMB2ARM_GLUE_SECTION_NAME);
91a5743d
PB		 15930
15931 osi.sec_shndx = _bfd_elf_section_from_bfd_section
15932 (output_bfd, osi.sec->output_section);
15933 size = THUMB2ARM_GLUE_SIZE;
15934
15935 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
15936 {
7413f23f
DJ		 15937 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
15938 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
91a5743d
PB		 15939 }
15940 }
15941
845b51d6
PB		 15942 /* ARMv4 BX veneers. */
15943 if (htab->bx_glue_size > 0)
15944 {
3d4d4302
AM		 15945 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
15946 ARM_BX_GLUE_SECTION_NAME);
845b51d6
PB		 15947
15948 osi.sec_shndx = _bfd_elf_section_from_bfd_section
15949 (output_bfd, osi.sec->output_section);
15950
7413f23f 15951 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
845b51d6
PB		 15952 }
15953
8029a119
NC		 15954 /* Long calls stubs. */
15955 if (htab->stub_bfd && htab->stub_bfd->sections)
15956 {
da5938a2 15957 asection* stub_sec;
8029a119 15958
da5938a2
NC		 15959 for (stub_sec = htab->stub_bfd->sections;
15960 stub_sec != NULL;
8029a119
NC		 15961 stub_sec = stub_sec->next)
15962 {
15963 /* Ignore non-stub sections. */
15964 if (!strstr (stub_sec->name, STUB_SUFFIX))
15965 continue;
da5938a2 15966
8029a119 15967 osi.sec = stub_sec;
da5938a2 15968
8029a119
NC		 15969 osi.sec_shndx = _bfd_elf_section_from_bfd_section
15970 (output_bfd, osi.sec->output_section);
da5938a2 15971
8029a119
NC		 15972 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
15973 }
15974 }
da5938a2 15975
91a5743d 15976 /* Finally, output mapping symbols for the PLT. */
34e77a92 15977 if (htab->root.splt && htab->root.splt->size > 0)
4e617b1e 15978 {
34e77a92
RS		 15979 osi.sec = htab->root.splt;
15980 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
15981 (output_bfd, osi.sec->output_section));
15982
15983 /* Output mapping symbols for the plt header. SymbianOS does not have a
15984 plt header. */
15985 if (htab->vxworks_p)
15986 {
15987 /* VxWorks shared libraries have no PLT header. */
0e1862bb 15988 if (!bfd_link_pic (info))
34e77a92
RS		 15989 {
15990 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
15991 return FALSE;
15992 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
15993 return FALSE;
15994 }
15995 }
b38cadfb
NC		 15996 else if (htab->nacl_p)
15997 {
15998 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
15999 return FALSE;
16000 }
eed94f8f
NC		 16001 else if (using_thumb_only (htab))
16002 {
16003 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
16004 return FALSE;
16005 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
16006 return FALSE;
16007 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
16008 return FALSE;
16009 }
34e77a92 16010 else if (!htab->symbian_p)
4e617b1e 16011 {
7413f23f 16012 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
4e617b1e 16013 return FALSE;
34e77a92
RS		 16014#ifndef FOUR_WORD_PLT
16015 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
4e617b1e 16016 return FALSE;
34e77a92 16017#endif
4e617b1e
PB		 16018 }
16019 }
99059e56
RM		 16020 if (htab->nacl_p && htab->root.iplt && htab->root.iplt->size > 0)
16021 {
16022 /* NaCl uses a special first entry in .iplt too. */
16023 osi.sec = htab->root.iplt;
16024 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
16025 (output_bfd, osi.sec->output_section));
16026 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
16027 return FALSE;
16028 }
34e77a92
RS		 16029 if ((htab->root.splt && htab->root.splt->size > 0)
16030 || (htab->root.iplt && htab->root.iplt->size > 0))
4e617b1e 16031 {
34e77a92
RS		 16032 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
16033 for (input_bfd = info->input_bfds;
16034 input_bfd != NULL;
c72f2fb2 16035 input_bfd = input_bfd->link.next)
34e77a92
RS		 16036 {
16037 struct arm_local_iplt_info **local_iplt;
16038 unsigned int i, num_syms;
4e617b1e 16039
34e77a92
RS		 16040 local_iplt = elf32_arm_local_iplt (input_bfd);
16041 if (local_iplt != NULL)
16042 {
16043 num_syms = elf_symtab_hdr (input_bfd).sh_info;
16044 for (i = 0; i < num_syms; i++)
16045 if (local_iplt[i] != NULL
16046 && !elf32_arm_output_plt_map_1 (&osi, TRUE,
16047 &local_iplt[i]->root,
16048 &local_iplt[i]->arm))
16049 return FALSE;
16050 }
16051 }
16052 }
0855e32b
NS		 16053 if (htab->dt_tlsdesc_plt != 0)
16054 {
16055 /* Mapping symbols for the lazy tls trampoline. */
16056 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->dt_tlsdesc_plt))
16057 return FALSE;
b38cadfb 16058
0855e32b
NS		 16059 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
16060 htab->dt_tlsdesc_plt + 24))
16061 return FALSE;
16062 }
16063 if (htab->tls_trampoline != 0)
16064 {
16065 /* Mapping symbols for the tls trampoline. */
16066 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
16067 return FALSE;
16068#ifdef FOUR_WORD_PLT
16069 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
16070 htab->tls_trampoline + 12))
16071 return FALSE;
b38cadfb 16072#endif
0855e32b 16073 }
b38cadfb 16074
4e617b1e
PB		 16075 return TRUE;
16076}
16077
e489d0ae
PB		 16078/* Allocate target specific section data. */
16079
16080static bfd_boolean
16081elf32_arm_new_section_hook (bfd *abfd, asection *sec)
16082{
f592407e
AM		 16083 if (!sec->used_by_bfd)
16084 {
16085 _arm_elf_section_data *sdata;
16086 bfd_size_type amt = sizeof (*sdata);
e489d0ae 16087
21d799b5 16088 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
f592407e
AM		 16089 if (sdata == NULL)
16090 return FALSE;
16091 sec->used_by_bfd = sdata;
16092 }
e489d0ae
PB		 16093
16094 return _bfd_elf_new_section_hook (abfd, sec);
16095}
16096
16097
16098/* Used to order a list of mapping symbols by address. */
16099
16100static int
16101elf32_arm_compare_mapping (const void * a, const void * b)
16102{
7f6a71ff
JM		 16103 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
16104 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
16105
16106 if (amap->vma > bmap->vma)
16107 return 1;
16108 else if (amap->vma < bmap->vma)
16109 return -1;
16110 else if (amap->type > bmap->type)
16111 /* Ensure results do not depend on the host qsort for objects with
16112 multiple mapping symbols at the same address by sorting on type
16113 after vma. */
16114 return 1;
16115 else if (amap->type < bmap->type)
16116 return -1;
16117 else
16118 return 0;
e489d0ae
PB		 16119}
16120
2468f9c9
PB		 16121/* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
16122
16123static unsigned long
16124offset_prel31 (unsigned long addr, bfd_vma offset)
16125{
16126 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
16127}
16128
16129/* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
16130 relocations. */
16131
16132static void
16133copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
16134{
16135 unsigned long first_word = bfd_get_32 (output_bfd, from);
16136 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
b38cadfb 16137
2468f9c9
PB		 16138 /* High bit of first word is supposed to be zero. */
16139 if ((first_word & 0x80000000ul) == 0)
16140 first_word = offset_prel31 (first_word, offset);
b38cadfb 16141
2468f9c9
PB		 16142 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
16143 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
16144 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
16145 second_word = offset_prel31 (second_word, offset);
b38cadfb 16146
2468f9c9
PB		 16147 bfd_put_32 (output_bfd, first_word, to);
16148 bfd_put_32 (output_bfd, second_word, to + 4);
16149}
e489d0ae 16150
48229727
JB		 16151/* Data for make_branch_to_a8_stub(). */
16152
b38cadfb
NC		 16153struct a8_branch_to_stub_data
16154{
48229727
JB		 16155 asection *writing_section;
16156 bfd_byte *contents;
16157};
16158
16159
16160/* Helper to insert branches to Cortex-A8 erratum stubs in the right
16161 places for a particular section. */
16162
16163static bfd_boolean
16164make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
99059e56 16165 void *in_arg)
48229727
JB		 16166{
16167 struct elf32_arm_stub_hash_entry *stub_entry;
16168 struct a8_branch_to_stub_data *data;
16169 bfd_byte *contents;
16170 unsigned long branch_insn;
16171 bfd_vma veneered_insn_loc, veneer_entry_loc;
16172 bfd_signed_vma branch_offset;
16173 bfd *abfd;
91d6fa6a 16174 unsigned int target;
48229727
JB		 16175
16176 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
16177 data = (struct a8_branch_to_stub_data *) in_arg;
16178
16179 if (stub_entry->target_section != data->writing_section
4563a860 16180 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
48229727
JB		 16181 return TRUE;
16182
16183 contents = data->contents;
16184
16185 veneered_insn_loc = stub_entry->target_section->output_section->vma
16186 + stub_entry->target_section->output_offset
16187 + stub_entry->target_value;
16188
16189 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
16190 + stub_entry->stub_sec->output_offset
16191 + stub_entry->stub_offset;
16192
16193 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
16194 veneered_insn_loc &= ~3u;
16195
16196 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
16197
16198 abfd = stub_entry->target_section->owner;
91d6fa6a 16199 target = stub_entry->target_value;
48229727
JB		 16200
16201 /* We attempt to avoid this condition by setting stubs_always_after_branch
16202 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
16203 This check is just to be on the safe side... */
16204 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
16205 {
16206 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub is "
16207 "allocated in unsafe location"), abfd);
16208 return FALSE;
16209 }
16210
16211 switch (stub_entry->stub_type)
16212 {
16213 case arm_stub_a8_veneer_b:
16214 case arm_stub_a8_veneer_b_cond:
16215 branch_insn = 0xf0009000;
16216 goto jump24;
16217
16218 case arm_stub_a8_veneer_blx:
16219 branch_insn = 0xf000e800;
16220 goto jump24;
16221
16222 case arm_stub_a8_veneer_bl:
16223 {
16224 unsigned int i1, j1, i2, j2, s;
16225
16226 branch_insn = 0xf000d000;
16227
16228 jump24:
16229 if (branch_offset < -16777216 || branch_offset > 16777214)
16230 {
16231 /* There's not much we can do apart from complain if this
16232 happens. */
16233 (*_bfd_error_handler) (_("%B: error: Cortex-A8 erratum stub out "
16234 "of range (input file too large)"), abfd);
16235 return FALSE;
16236 }
16237
16238 /* i1 = not(j1 eor s), so:
16239 not i1 = j1 eor s
16240 j1 = (not i1) eor s. */
16241
16242 branch_insn |= (branch_offset >> 1) & 0x7ff;
16243 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
16244 i2 = (branch_offset >> 22) & 1;
16245 i1 = (branch_offset >> 23) & 1;
16246 s = (branch_offset >> 24) & 1;
16247 j1 = (!i1) ^ s;
16248 j2 = (!i2) ^ s;
16249 branch_insn |= j2 << 11;
16250 branch_insn |= j1 << 13;
16251 branch_insn |= s << 26;
16252 }
16253 break;
16254
16255 default:
16256 BFD_FAIL ();
16257 return FALSE;
16258 }
16259
91d6fa6a
NC		 16260 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[target]);
16261 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[target + 2]);
48229727
JB		 16262
16263 return TRUE;
16264}
16265
a504d23a
LA		 16266/* Beginning of stm32l4xx work-around. */
16267
16268/* Functions encoding instructions necessary for the emission of the
16269 fix-stm32l4xx-629360.
16270 Encoding is extracted from the
16271 ARM (C) Architecture Reference Manual
16272 ARMv7-A and ARMv7-R edition
16273 ARM DDI 0406C.b (ID072512). */
16274
16275static inline bfd_vma
82188b29 16276create_instruction_branch_absolute (int branch_offset)
a504d23a
LA		 16277{
16278 /* A8.8.18 B (A8-334)
16279 B target_address (Encoding T4). */
16280 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
16281 /* jump offset is: S:I1:I2:imm10:imm11:0. */
16282 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
16283
a504d23a
LA		 16284 int s = ((branch_offset & 0x1000000) >> 24);
16285 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
16286 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
16287
16288 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
16289 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
16290
16291 bfd_vma patched_inst = 0xf0009000
16292 | s << 26 /* S. */
16293 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
16294 | j1 << 13 /* J1. */
16295 | j2 << 11 /* J2. */
16296 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
16297
16298 return patched_inst;
16299}
16300
16301static inline bfd_vma
16302create_instruction_ldmia (int base_reg, int wback, int reg_mask)
16303{
16304 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
16305 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
16306 bfd_vma patched_inst = 0xe8900000
16307 | (/*W=*/wback << 21)
16308 | (base_reg << 16)
16309 | (reg_mask & 0x0000ffff);
16310
16311 return patched_inst;
16312}
16313
16314static inline bfd_vma
16315create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
16316{
16317 /* A8.8.60 LDMDB/LDMEA (A8-402)
16318 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
16319 bfd_vma patched_inst = 0xe9100000
16320 | (/*W=*/wback << 21)
16321 | (base_reg << 16)
16322 | (reg_mask & 0x0000ffff);
16323
16324 return patched_inst;
16325}
16326
16327static inline bfd_vma
16328create_instruction_mov (int target_reg, int source_reg)
16329{
16330 /* A8.8.103 MOV (register) (A8-486)
16331 MOV Rd, Rm (Encoding T1). */
16332 bfd_vma patched_inst = 0x4600
16333 | (target_reg & 0x7)
16334 | ((target_reg & 0x8) >> 3) << 7
16335 | (source_reg << 3);
16336
16337 return patched_inst;
16338}
16339
16340static inline bfd_vma
16341create_instruction_sub (int target_reg, int source_reg, int value)
16342{
16343 /* A8.8.221 SUB (immediate) (A8-708)
16344 SUB Rd, Rn, #value (Encoding T3). */
16345 bfd_vma patched_inst = 0xf1a00000
16346 | (target_reg << 8)
16347 | (source_reg << 16)
16348 | (/*S=*/0 << 20)
16349 | ((value & 0x800) >> 11) << 26
16350 | ((value & 0x700) >> 8) << 12
16351 | (value & 0x0ff);
16352
16353 return patched_inst;
16354}
16355
16356static inline bfd_vma
16357create_instruction_vldmia (int base_reg, int wback, int num_regs,
16358 int first_reg)
16359{
16360 /* A8.8.332 VLDM (A8-922)
16361 VLMD{MODE} Rn{!}, {list} (Encoding T2). */
16362 bfd_vma patched_inst = 0xec900a00
16363 | (/*W=*/wback << 21)
16364 | (base_reg << 16)
16365 | (num_regs & 0x000000ff)
16366 | (((unsigned)first_reg>>1) & 0x0000000f) << 12
16367 | (first_reg & 0x00000001) << 22;
16368
16369 return patched_inst;
16370}
16371
16372static inline bfd_vma
16373create_instruction_vldmdb (int base_reg, int num_regs, int first_reg)
16374{
16375 /* A8.8.332 VLDM (A8-922)
16376 VLMD{MODE} Rn!, {} (Encoding T2). */
16377 bfd_vma patched_inst = 0xed300a00
16378 | (base_reg << 16)
16379 | (num_regs & 0x000000ff)
16380 | (((unsigned)first_reg>>1) & 0x0000000f) << 12
16381 | (first_reg & 0x00000001) << 22;
16382
16383 return patched_inst;
16384}
16385
16386static inline bfd_vma
16387create_instruction_udf_w (int value)
16388{
16389 /* A8.8.247 UDF (A8-758)
16390 Undefined (Encoding T2). */
16391 bfd_vma patched_inst = 0xf7f0a000
16392 | (value & 0x00000fff)
16393 | (value & 0x000f0000) << 16;
16394
16395 return patched_inst;
16396}
16397
16398static inline bfd_vma
16399create_instruction_udf (int value)
16400{
16401 /* A8.8.247 UDF (A8-758)
16402 Undefined (Encoding T1). */
16403 bfd_vma patched_inst = 0xde00
16404 | (value & 0xff);
16405
16406 return patched_inst;
16407}
16408
16409/* Functions writing an instruction in memory, returning the next
16410 memory position to write to. */
16411
16412static inline bfd_byte *
16413push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
16414 bfd * output_bfd, bfd_byte *pt, insn32 insn)
16415{
16416 put_thumb2_insn (htab, output_bfd, insn, pt);
16417 return pt + 4;
16418}
16419
16420static inline bfd_byte *
16421push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
16422 bfd * output_bfd, bfd_byte *pt, insn32 insn)
16423{
16424 put_thumb_insn (htab, output_bfd, insn, pt);
16425 return pt + 2;
16426}
16427
16428/* Function filling up a region in memory with T1 and T2 UDFs taking
16429 care of alignment. */
16430
16431static bfd_byte *
16432stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
16433 bfd * output_bfd,
16434 const bfd_byte * const base_stub_contents,
16435 bfd_byte * const from_stub_contents,
16436 const bfd_byte * const end_stub_contents)
16437{
16438 bfd_byte *current_stub_contents = from_stub_contents;
16439
16440 /* Fill the remaining of the stub with deterministic contents : UDF
16441 instructions.
16442 Check if realignment is needed on modulo 4 frontier using T1, to
16443 further use T2. */
16444 if ((current_stub_contents < end_stub_contents)
16445 && !((current_stub_contents - base_stub_contents) % 2)
16446 && ((current_stub_contents - base_stub_contents) % 4))
16447 current_stub_contents =
16448 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16449 create_instruction_udf (0));
16450
16451 for (; current_stub_contents < end_stub_contents;)
16452 current_stub_contents =
16453 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16454 create_instruction_udf_w (0));
16455
16456 return current_stub_contents;
16457}
16458
16459/* Functions writing the stream of instructions equivalent to the
16460 derived sequence for ldmia, ldmdb, vldm respectively. */
16461
16462static void
16463stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
16464 bfd * output_bfd,
16465 const insn32 initial_insn,
16466 const bfd_byte *const initial_insn_addr,
16467 bfd_byte *const base_stub_contents)
16468{
16469 int wback = (initial_insn & 0x00200000) >> 21;
16470 int ri, rn = (initial_insn & 0x000F0000) >> 16;
16471 int insn_all_registers = initial_insn & 0x0000ffff;
16472 int insn_low_registers, insn_high_registers;
16473 int usable_register_mask;
16474 int nb_registers = popcount (insn_all_registers);
16475 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
16476 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
16477 bfd_byte *current_stub_contents = base_stub_contents;
16478
16479 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
16480
16481 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16482 smaller than 8 registers load sequences that do not cause the
16483 hardware issue. */
16484 if (nb_registers <= 8)
16485 {
16486 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
16487 current_stub_contents =
16488 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16489 initial_insn);
16490
16491 /* B initial_insn_addr+4. */
16492 if (!restore_pc)
16493 current_stub_contents =
16494 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16495 create_instruction_branch_absolute
82188b29
NC		 16496 (initial_insn_addr - current_stub_contents));
16497
a504d23a
LA		 16498
16499 /* Fill the remaining of the stub with deterministic contents. */
16500 current_stub_contents =
16501 stm32l4xx_fill_stub_udf (htab, output_bfd,
16502 base_stub_contents, current_stub_contents,
16503 base_stub_contents +
16504 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16505
16506 return;
16507 }
16508
16509 /* - reg_list[13] == 0. */
16510 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
16511
16512 /* - reg_list[14] & reg_list[15] != 1. */
16513 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
16514
16515 /* - if (wback==1) reg_list[rn] == 0. */
16516 BFD_ASSERT (!wback || !restore_rn);
16517
16518 /* - nb_registers > 8. */
16519 BFD_ASSERT (popcount (insn_all_registers) > 8);
16520
16521 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
16522
16523 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
16524 - One with the 7 lowest registers (register mask 0x007F)
16525 This LDM will finally contain between 2 and 7 registers
16526 - One with the 7 highest registers (register mask 0xDF80)
16527 This ldm will finally contain between 2 and 7 registers. */
16528 insn_low_registers = insn_all_registers & 0x007F;
16529 insn_high_registers = insn_all_registers & 0xDF80;
16530
16531 /* A spare register may be needed during this veneer to temporarily
16532 handle the base register. This register will be restored with the
16533 last LDM operation.
16534 The usable register may be any general purpose register (that
16535 excludes PC, SP, LR : register mask is 0x1FFF). */
16536 usable_register_mask = 0x1FFF;
16537
16538 /* Generate the stub function. */
16539 if (wback)
16540 {
16541 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
16542 current_stub_contents =
16543 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16544 create_instruction_ldmia
16545 (rn, /*wback=*/1, insn_low_registers));
16546
16547 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
16548 current_stub_contents =
16549 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16550 create_instruction_ldmia
16551 (rn, /*wback=*/1, insn_high_registers));
16552 if (!restore_pc)
16553 {
16554 /* B initial_insn_addr+4. */
16555 current_stub_contents =
16556 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16557 create_instruction_branch_absolute
82188b29 16558 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16559 }
16560 }
16561 else /* if (!wback). */
16562 {
16563 ri = rn;
16564
16565 /* If Rn is not part of the high-register-list, move it there. */
16566 if (!(insn_high_registers & (1 << rn)))
16567 {
16568 /* Choose a Ri in the high-register-list that will be restored. */
16569 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16570
16571 /* MOV Ri, Rn. */
16572 current_stub_contents =
16573 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16574 create_instruction_mov (ri, rn));
16575 }
16576
16577 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
16578 current_stub_contents =
16579 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16580 create_instruction_ldmia
16581 (ri, /*wback=*/1, insn_low_registers));
16582
16583 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
16584 current_stub_contents =
16585 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16586 create_instruction_ldmia
16587 (ri, /*wback=*/0, insn_high_registers));
16588
16589 if (!restore_pc)
16590 {
16591 /* B initial_insn_addr+4. */
16592 current_stub_contents =
16593 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16594 create_instruction_branch_absolute
82188b29 16595 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16596 }
16597 }
16598
16599 /* Fill the remaining of the stub with deterministic contents. */
16600 current_stub_contents =
16601 stm32l4xx_fill_stub_udf (htab, output_bfd,
16602 base_stub_contents, current_stub_contents,
16603 base_stub_contents +
16604 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16605}
16606
16607static void
16608stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
16609 bfd * output_bfd,
16610 const insn32 initial_insn,
16611 const bfd_byte *const initial_insn_addr,
16612 bfd_byte *const base_stub_contents)
16613{
16614 int wback = (initial_insn & 0x00200000) >> 21;
16615 int ri, rn = (initial_insn & 0x000f0000) >> 16;
16616 int insn_all_registers = initial_insn & 0x0000ffff;
16617 int insn_low_registers, insn_high_registers;
16618 int usable_register_mask;
16619 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
16620 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
16621 int nb_registers = popcount (insn_all_registers);
16622 bfd_byte *current_stub_contents = base_stub_contents;
16623
16624 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
16625
16626 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16627 smaller than 8 registers load sequences that do not cause the
16628 hardware issue. */
16629 if (nb_registers <= 8)
16630 {
16631 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
16632 current_stub_contents =
16633 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16634 initial_insn);
16635
16636 /* B initial_insn_addr+4. */
16637 current_stub_contents =
16638 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16639 create_instruction_branch_absolute
82188b29 16640 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16641
16642 /* Fill the remaining of the stub with deterministic contents. */
16643 current_stub_contents =
16644 stm32l4xx_fill_stub_udf (htab, output_bfd,
16645 base_stub_contents, current_stub_contents,
16646 base_stub_contents +
16647 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16648
16649 return;
16650 }
16651
16652 /* - reg_list[13] == 0. */
16653 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
16654
16655 /* - reg_list[14] & reg_list[15] != 1. */
16656 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
16657
16658 /* - if (wback==1) reg_list[rn] == 0. */
16659 BFD_ASSERT (!wback || !restore_rn);
16660
16661 /* - nb_registers > 8. */
16662 BFD_ASSERT (popcount (insn_all_registers) > 8);
16663
16664 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
16665
16666 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
16667 - One with the 7 lowest registers (register mask 0x007F)
16668 This LDM will finally contain between 2 and 7 registers
16669 - One with the 7 highest registers (register mask 0xDF80)
16670 This ldm will finally contain between 2 and 7 registers. */
16671 insn_low_registers = insn_all_registers & 0x007F;
16672 insn_high_registers = insn_all_registers & 0xDF80;
16673
16674 /* A spare register may be needed during this veneer to temporarily
16675 handle the base register. This register will be restored with
16676 the last LDM operation.
16677 The usable register may be any general purpose register (that excludes
16678 PC, SP, LR : register mask is 0x1FFF). */
16679 usable_register_mask = 0x1FFF;
16680
16681 /* Generate the stub function. */
16682 if (!wback && !restore_pc && !restore_rn)
16683 {
16684 /* Choose a Ri in the low-register-list that will be restored. */
16685 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
16686
16687 /* MOV Ri, Rn. */
16688 current_stub_contents =
16689 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16690 create_instruction_mov (ri, rn));
16691
16692 /* LDMDB Ri!, {R-high-register-list}. */
16693 current_stub_contents =
16694 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16695 create_instruction_ldmdb
16696 (ri, /*wback=*/1, insn_high_registers));
16697
16698 /* LDMDB Ri, {R-low-register-list}. */
16699 current_stub_contents =
16700 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16701 create_instruction_ldmdb
16702 (ri, /*wback=*/0, insn_low_registers));
16703
16704 /* B initial_insn_addr+4. */
16705 current_stub_contents =
16706 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16707 create_instruction_branch_absolute
82188b29 16708 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16709 }
16710 else if (wback && !restore_pc && !restore_rn)
16711 {
16712 /* LDMDB Rn!, {R-high-register-list}. */
16713 current_stub_contents =
16714 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16715 create_instruction_ldmdb
16716 (rn, /*wback=*/1, insn_high_registers));
16717
16718 /* LDMDB Rn!, {R-low-register-list}. */
16719 current_stub_contents =
16720 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16721 create_instruction_ldmdb
16722 (rn, /*wback=*/1, insn_low_registers));
16723
16724 /* B initial_insn_addr+4. */
16725 current_stub_contents =
16726 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16727 create_instruction_branch_absolute
82188b29 16728 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16729 }
16730 else if (!wback && restore_pc && !restore_rn)
16731 {
16732 /* Choose a Ri in the high-register-list that will be restored. */
16733 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16734
16735 /* SUB Ri, Rn, #(4*nb_registers). */
16736 current_stub_contents =
16737 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16738 create_instruction_sub (ri, rn, (4 * nb_registers)));
16739
16740 /* LDMIA Ri!, {R-low-register-list}. */
16741 current_stub_contents =
16742 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16743 create_instruction_ldmia
16744 (ri, /*wback=*/1, insn_low_registers));
16745
16746 /* LDMIA Ri, {R-high-register-list}. */
16747 current_stub_contents =
16748 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16749 create_instruction_ldmia
16750 (ri, /*wback=*/0, insn_high_registers));
16751 }
16752 else if (wback && restore_pc && !restore_rn)
16753 {
16754 /* Choose a Ri in the high-register-list that will be restored. */
16755 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16756
16757 /* SUB Rn, Rn, #(4*nb_registers) */
16758 current_stub_contents =
16759 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16760 create_instruction_sub (rn, rn, (4 * nb_registers)));
16761
16762 /* MOV Ri, Rn. */
16763 current_stub_contents =
16764 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16765 create_instruction_mov (ri, rn));
16766
16767 /* LDMIA Ri!, {R-low-register-list}. */
16768 current_stub_contents =
16769 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16770 create_instruction_ldmia
16771 (ri, /*wback=*/1, insn_low_registers));
16772
16773 /* LDMIA Ri, {R-high-register-list}. */
16774 current_stub_contents =
16775 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16776 create_instruction_ldmia
16777 (ri, /*wback=*/0, insn_high_registers));
16778 }
16779 else if (!wback && !restore_pc && restore_rn)
16780 {
16781 ri = rn;
16782 if (!(insn_low_registers & (1 << rn)))
16783 {
16784 /* Choose a Ri in the low-register-list that will be restored. */
16785 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
16786
16787 /* MOV Ri, Rn. */
16788 current_stub_contents =
16789 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
16790 create_instruction_mov (ri, rn));
16791 }
16792
16793 /* LDMDB Ri!, {R-high-register-list}. */
16794 current_stub_contents =
16795 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16796 create_instruction_ldmdb
16797 (ri, /*wback=*/1, insn_high_registers));
16798
16799 /* LDMDB Ri, {R-low-register-list}. */
16800 current_stub_contents =
16801 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16802 create_instruction_ldmdb
16803 (ri, /*wback=*/0, insn_low_registers));
16804
16805 /* B initial_insn_addr+4. */
16806 current_stub_contents =
16807 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16808 create_instruction_branch_absolute
82188b29 16809 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16810 }
16811 else if (!wback && restore_pc && restore_rn)
16812 {
16813 ri = rn;
16814 if (!(insn_high_registers & (1 << rn)))
16815 {
16816 /* Choose a Ri in the high-register-list that will be restored. */
16817 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
16818 }
16819
16820 /* SUB Ri, Rn, #(4*nb_registers). */
16821 current_stub_contents =
16822 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16823 create_instruction_sub (ri, rn, (4 * nb_registers)));
16824
16825 /* LDMIA Ri!, {R-low-register-list}. */
16826 current_stub_contents =
16827 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16828 create_instruction_ldmia
16829 (ri, /*wback=*/1, insn_low_registers));
16830
16831 /* LDMIA Ri, {R-high-register-list}. */
16832 current_stub_contents =
16833 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16834 create_instruction_ldmia
16835 (ri, /*wback=*/0, insn_high_registers));
16836 }
16837 else if (wback && restore_rn)
16838 {
16839 /* The assembler should not have accepted to encode this. */
16840 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
16841 "undefined behavior.\n");
16842 }
16843
16844 /* Fill the remaining of the stub with deterministic contents. */
16845 current_stub_contents =
16846 stm32l4xx_fill_stub_udf (htab, output_bfd,
16847 base_stub_contents, current_stub_contents,
16848 base_stub_contents +
16849 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
16850
16851}
16852
16853static void
16854stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
16855 bfd * output_bfd,
16856 const insn32 initial_insn,
16857 const bfd_byte *const initial_insn_addr,
16858 bfd_byte *const base_stub_contents)
16859{
16860 int num_regs = ((unsigned int)initial_insn << 24) >> 24;
16861 bfd_byte *current_stub_contents = base_stub_contents;
16862
16863 BFD_ASSERT (is_thumb2_vldm (initial_insn));
16864
16865 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
16866 smaller than 8 registers load sequences that do not cause the
16867 hardware issue. */
16868 if (num_regs <= 8)
16869 {
16870 /* Untouched instruction. */
16871 current_stub_contents =
16872 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16873 initial_insn);
16874
16875 /* B initial_insn_addr+4. */
16876 current_stub_contents =
16877 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16878 create_instruction_branch_absolute
82188b29 16879 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16880 }
16881 else
16882 {
16883 bfd_boolean is_ia_nobang = /* (IA without !). */
16884 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
16885 bfd_boolean is_ia_bang = /* (IA with !) - includes VPOP. */
16886 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
16887 bfd_boolean is_db_bang = /* (DB with !). */
16888 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
16889 int base_reg = ((unsigned int)initial_insn << 12) >> 28;
16890 /* d = UInt (Vd:D);. */
16891 int first_reg = ((((unsigned int)initial_insn << 16) >> 28) << 1)
16892 | (((unsigned int)initial_insn << 9) >> 31);
16893
16894 /* Compute the number of 8-register chunks needed to split. */
16895 int chunks = (num_regs%8) ? (num_regs/8 + 1) : (num_regs/8);
16896 int chunk;
16897
16898 /* The test coverage has been done assuming the following
16899 hypothesis that exactly one of the previous is_ predicates is
16900 true. */
16901 BFD_ASSERT ((is_ia_nobang ^ is_ia_bang ^ is_db_bang) &&
16902 !(is_ia_nobang & is_ia_bang & is_db_bang));
16903
16904 /* We treat the cutting of the register in one pass for all
16905 cases, then we emit the adjustments:
16906
16907 vldm rx, {...}
16908 -> vldm rx!, {8_words_or_less} for each needed 8_word
16909 -> sub rx, rx, #size (list)
16910
16911 vldm rx!, {...}
16912 -> vldm rx!, {8_words_or_less} for each needed 8_word
16913 This also handles vpop instruction (when rx is sp)
16914
16915 vldmd rx!, {...}
16916 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
16917 for (chunk = 0; chunk<chunks; ++chunk)
16918 {
16919 if (is_ia_nobang || is_ia_bang)
16920 {
16921 current_stub_contents =
16922 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16923 create_instruction_vldmia
16924 (base_reg,
16925 /*wback= . */1,
16926 chunks - (chunk + 1) ?
16927 8 : num_regs - chunk * 8,
16928 first_reg + chunk * 8));
16929 }
16930 else if (is_db_bang)
16931 {
16932 current_stub_contents =
16933 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16934 create_instruction_vldmdb
16935 (base_reg,
16936 chunks - (chunk + 1) ?
16937 8 : num_regs - chunk * 8,
16938 first_reg + chunk * 8));
16939 }
16940 }
16941
16942 /* Only this case requires the base register compensation
16943 subtract. */
16944 if (is_ia_nobang)
16945 {
16946 current_stub_contents =
16947 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16948 create_instruction_sub
16949 (base_reg, base_reg, 4*num_regs));
16950 }
16951
16952 /* B initial_insn_addr+4. */
16953 current_stub_contents =
16954 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
16955 create_instruction_branch_absolute
82188b29 16956 (initial_insn_addr - current_stub_contents));
a504d23a
LA		 16957 }
16958
16959 /* Fill the remaining of the stub with deterministic contents. */
16960 current_stub_contents =
16961 stm32l4xx_fill_stub_udf (htab, output_bfd,
16962 base_stub_contents, current_stub_contents,
16963 base_stub_contents +
16964 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
16965}
16966
16967static void
16968stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
16969 bfd * output_bfd,
16970 const insn32 wrong_insn,
16971 const bfd_byte *const wrong_insn_addr,
16972 bfd_byte *const stub_contents)
16973{
16974 if (is_thumb2_ldmia (wrong_insn))
16975 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
16976 wrong_insn, wrong_insn_addr,
16977 stub_contents);
16978 else if (is_thumb2_ldmdb (wrong_insn))
16979 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
16980 wrong_insn, wrong_insn_addr,
16981 stub_contents);
16982 else if (is_thumb2_vldm (wrong_insn))
16983 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
16984 wrong_insn, wrong_insn_addr,
16985 stub_contents);
16986}
16987
16988/* End of stm32l4xx work-around. */
16989
16990
491d01d3
YU		 16991static void
16992elf32_arm_add_relocation (bfd *output_bfd, struct bfd_link_info *info,
16993 asection *output_sec, Elf_Internal_Rela *rel)
16994{
16995 BFD_ASSERT (output_sec && rel);
16996 struct bfd_elf_section_reloc_data *output_reldata;
16997 struct elf32_arm_link_hash_table *htab;
16998 struct bfd_elf_section_data *oesd = elf_section_data (output_sec);
16999 Elf_Internal_Shdr *rel_hdr;
17000
17001
17002 if (oesd->rel.hdr)
17003 {
17004 rel_hdr = oesd->rel.hdr;
17005 output_reldata = &(oesd->rel);
17006 }
17007 else if (oesd->rela.hdr)
17008 {
17009 rel_hdr = oesd->rela.hdr;
17010 output_reldata = &(oesd->rela);
17011 }
17012 else
17013 {
17014 abort ();
17015 }
17016
17017 bfd_byte *erel = rel_hdr->contents;
17018 erel += output_reldata->count * rel_hdr->sh_entsize;
17019 htab = elf32_arm_hash_table (info);
17020 SWAP_RELOC_OUT (htab) (output_bfd, rel, erel);
17021 output_reldata->count++;
17022}
17023
e489d0ae
PB		 17024/* Do code byteswapping. Return FALSE afterwards so that the section is
17025 written out as normal. */
17026
17027static bfd_boolean
c7b8f16e 17028elf32_arm_write_section (bfd *output_bfd,
8029a119
NC		 17029 struct bfd_link_info *link_info,
17030 asection *sec,
e489d0ae
PB		 17031 bfd_byte *contents)
17032{
48229727 17033 unsigned int mapcount, errcount;
8e3de13a 17034 _arm_elf_section_data *arm_data;
c7b8f16e 17035 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
e489d0ae 17036 elf32_arm_section_map *map;
c7b8f16e 17037 elf32_vfp11_erratum_list *errnode;
a504d23a 17038 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
e489d0ae
PB		 17039 bfd_vma ptr;
17040 bfd_vma end;
c7b8f16e 17041 bfd_vma offset = sec->output_section->vma + sec->output_offset;
e489d0ae 17042 bfd_byte tmp;
48229727 17043 unsigned int i;
57e8b36a 17044
4dfe6ac6
NC		 17045 if (globals == NULL)
17046 return FALSE;
17047
8e3de13a
NC		 17048 /* If this section has not been allocated an _arm_elf_section_data
17049 structure then we cannot record anything. */
17050 arm_data = get_arm_elf_section_data (sec);
17051 if (arm_data == NULL)
17052 return FALSE;
17053
17054 mapcount = arm_data->mapcount;
17055 map = arm_data->map;
c7b8f16e
JB		 17056 errcount = arm_data->erratumcount;
17057
17058 if (errcount != 0)
17059 {
17060 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
17061
17062 for (errnode = arm_data->erratumlist; errnode != 0;
99059e56
RM		 17063 errnode = errnode->next)
17064 {
17065 bfd_vma target = errnode->vma - offset;
17066
17067 switch (errnode->type)
17068 {
17069 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
17070 {
17071 bfd_vma branch_to_veneer;
17072 /* Original condition code of instruction, plus bit mask for
17073 ARM B instruction. */
17074 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
17075 | 0x0a000000;
c7b8f16e
JB		 17076
17077 /* The instruction is before the label. */
91d6fa6a 17078 target -= 4;
c7b8f16e
JB		 17079
17080 /* Above offset included in -4 below. */
17081 branch_to_veneer = errnode->u.b.veneer->vma
99059e56 17082 - errnode->vma - 4;
c7b8f16e
JB		 17083
17084 if ((signed) branch_to_veneer < -(1 << 25)
17085 || (signed) branch_to_veneer >= (1 << 25))
17086 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
17087 "range"), output_bfd);
17088
99059e56
RM		 17089 insn |= (branch_to_veneer >> 2) & 0xffffff;
17090 contents[endianflip ^ target] = insn & 0xff;
17091 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
17092 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
17093 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
17094 }
17095 break;
c7b8f16e
JB		 17096
17097 case VFP11_ERRATUM_ARM_VENEER:
99059e56
RM		 17098 {
17099 bfd_vma branch_from_veneer;
17100 unsigned int insn;
c7b8f16e 17101
99059e56
RM		 17102 /* Take size of veneer into account. */
17103 branch_from_veneer = errnode->u.v.branch->vma
17104 - errnode->vma - 12;
c7b8f16e
JB		 17105
17106 if ((signed) branch_from_veneer < -(1 << 25)
17107 || (signed) branch_from_veneer >= (1 << 25))
17108 (*_bfd_error_handler) (_("%B: error: VFP11 veneer out of "
17109 "range"), output_bfd);
17110
99059e56
RM		 17111 /* Original instruction. */
17112 insn = errnode->u.v.branch->u.b.vfp_insn;
17113 contents[endianflip ^ target] = insn & 0xff;
17114 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
17115 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
17116 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
17117
17118 /* Branch back to insn after original insn. */
17119 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
17120 contents[endianflip ^ (target + 4)] = insn & 0xff;
17121 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
17122 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
17123 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
17124 }
17125 break;
c7b8f16e 17126
99059e56
RM		 17127 default:
17128 abort ();
17129 }
17130 }
c7b8f16e 17131 }
e489d0ae 17132
a504d23a
LA		 17133 if (arm_data->stm32l4xx_erratumcount != 0)
17134 {
17135 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
17136 stm32l4xx_errnode != 0;
17137 stm32l4xx_errnode = stm32l4xx_errnode->next)
17138 {
17139 bfd_vma target = stm32l4xx_errnode->vma - offset;
17140
17141 switch (stm32l4xx_errnode->type)
17142 {
17143 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
17144 {
17145 unsigned int insn;
17146 bfd_vma branch_to_veneer =
17147 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
17148
17149 if ((signed) branch_to_veneer < -(1 << 24)
17150 || (signed) branch_to_veneer >= (1 << 24))
17151 {
17152 bfd_vma out_of_range =
17153 ((signed) branch_to_veneer < -(1 << 24)) ?
17154 - branch_to_veneer - (1 << 24) :
17155 ((signed) branch_to_veneer >= (1 << 24)) ?
17156 branch_to_veneer - (1 << 24) : 0;
17157
17158 (*_bfd_error_handler)
17159 (_("%B(%#x): error: Cannot create STM32L4XX veneer. "
eee926f2 17160 "Jump out of range by %ld bytes. "
a504d23a
LA		 17161 "Cannot encode branch instruction. "),
17162 output_bfd,
eee926f2 17163 (long) (stm32l4xx_errnode->vma - 4),
a504d23a
LA		 17164 out_of_range);
17165 continue;
17166 }
17167
17168 insn = create_instruction_branch_absolute
82188b29 17169 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
a504d23a
LA		 17170
17171 /* The instruction is before the label. */
17172 target -= 4;
17173
17174 put_thumb2_insn (globals, output_bfd,
17175 (bfd_vma) insn, contents + target);
17176 }
17177 break;
17178
17179 case STM32L4XX_ERRATUM_VENEER:
17180 {
82188b29
NC		 17181 bfd_byte * veneer;
17182 bfd_byte * veneer_r;
a504d23a
LA		 17183 unsigned int insn;
17184
82188b29
NC		 17185 veneer = contents + target;
17186 veneer_r = veneer
17187 + stm32l4xx_errnode->u.b.veneer->vma
17188 - stm32l4xx_errnode->vma - 4;
a504d23a
LA		 17189
17190 if ((signed) (veneer_r - veneer -
17191 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
17192 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
17193 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
17194 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
17195 || (signed) (veneer_r - veneer) >= (1 << 24))
17196 {
17197 (*_bfd_error_handler) (_("%B: error: Cannot create STM32L4XX "
17198 "veneer."), output_bfd);
17199 continue;
17200 }
17201
17202 /* Original instruction. */
17203 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
17204
17205 stm32l4xx_create_replacing_stub
17206 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
17207 }
17208 break;
17209
17210 default:
17211 abort ();
17212 }
17213 }
17214 }
17215
2468f9c9
PB		 17216 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
17217 {
17218 arm_unwind_table_edit *edit_node
99059e56 17219 = arm_data->u.exidx.unwind_edit_list;
2468f9c9 17220 /* Now, sec->size is the size of the section we will write. The original
99059e56 17221 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
2468f9c9
PB		 17222 markers) was sec->rawsize. (This isn't the case if we perform no
17223 edits, then rawsize will be zero and we should use size). */
21d799b5 17224 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
2468f9c9
PB		 17225 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
17226 unsigned int in_index, out_index;
17227 bfd_vma add_to_offsets = 0;
17228
17229 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
99059e56 17230 {
2468f9c9
PB		 17231 if (edit_node)
17232 {
17233 unsigned int edit_index = edit_node->index;
b38cadfb 17234
2468f9c9 17235 if (in_index < edit_index && in_index * 8 < input_size)
99059e56 17236 {
2468f9c9
PB		 17237 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
17238 contents + in_index * 8, add_to_offsets);
17239 out_index++;
17240 in_index++;
17241 }
17242 else if (in_index == edit_index
17243 || (in_index * 8 >= input_size
17244 && edit_index == UINT_MAX))
99059e56 17245 {
2468f9c9
PB		 17246 switch (edit_node->type)
17247 {
17248 case DELETE_EXIDX_ENTRY:
17249 in_index++;
17250 add_to_offsets += 8;
17251 break;
b38cadfb 17252
2468f9c9
PB		 17253 case INSERT_EXIDX_CANTUNWIND_AT_END:
17254 {
99059e56 17255 asection *text_sec = edit_node->linked_section;
2468f9c9
PB		 17256 bfd_vma text_offset = text_sec->output_section->vma
17257 + text_sec->output_offset
17258 + text_sec->size;
17259 bfd_vma exidx_offset = offset + out_index * 8;
99059e56 17260 unsigned long prel31_offset;
2468f9c9
PB		 17261
17262 /* Note: this is meant to be equivalent to an
17263 R_ARM_PREL31 relocation. These synthetic
17264 EXIDX_CANTUNWIND markers are not relocated by the
17265 usual BFD method. */
17266 prel31_offset = (text_offset - exidx_offset)
17267 & 0x7ffffffful;
491d01d3
YU		 17268 if (bfd_link_relocatable (link_info))
17269 {
17270 /* Here relocation for new EXIDX_CANTUNWIND is
17271 created, so there is no need to
17272 adjust offset by hand. */
17273 prel31_offset = text_sec->output_offset
17274 + text_sec->size;
17275
17276 /* New relocation entity. */
17277 asection *text_out = text_sec->output_section;
17278 Elf_Internal_Rela rel;
17279 rel.r_addend = 0;
17280 rel.r_offset = exidx_offset;
17281 rel.r_info = ELF32_R_INFO (text_out->target_index,
17282 R_ARM_PREL31);
17283
17284 elf32_arm_add_relocation (output_bfd, link_info,
17285 sec->output_section,
17286 &rel);
17287 }
2468f9c9
PB		 17288
17289 /* First address we can't unwind. */
17290 bfd_put_32 (output_bfd, prel31_offset,
17291 &edited_contents[out_index * 8]);
17292
17293 /* Code for EXIDX_CANTUNWIND. */
17294 bfd_put_32 (output_bfd, 0x1,
17295 &edited_contents[out_index * 8 + 4]);
17296
17297 out_index++;
17298 add_to_offsets -= 8;
17299 }
17300 break;
17301 }
b38cadfb 17302
2468f9c9
PB		 17303 edit_node = edit_node->next;
17304 }
17305 }
17306 else
17307 {
17308 /* No more edits, copy remaining entries verbatim. */
17309 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
17310 contents + in_index * 8, add_to_offsets);
17311 out_index++;
17312 in_index++;
17313 }
17314 }
17315
17316 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
17317 bfd_set_section_contents (output_bfd, sec->output_section,
17318 edited_contents,
17319 (file_ptr) sec->output_offset, sec->size);
17320
17321 return TRUE;
17322 }
17323
48229727
JB		 17324 /* Fix code to point to Cortex-A8 erratum stubs. */
17325 if (globals->fix_cortex_a8)
17326 {
17327 struct a8_branch_to_stub_data data;
17328
17329 data.writing_section = sec;
17330 data.contents = contents;
17331
a504d23a
LA		 17332 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
17333 & data);
48229727
JB		 17334 }
17335
e489d0ae
PB		 17336 if (mapcount == 0)
17337 return FALSE;
17338
c7b8f16e 17339 if (globals->byteswap_code)
e489d0ae 17340 {
c7b8f16e 17341 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
57e8b36a 17342
c7b8f16e
JB		 17343 ptr = map[0].vma;
17344 for (i = 0; i < mapcount; i++)
99059e56
RM		 17345 {
17346 if (i == mapcount - 1)
c7b8f16e 17347 end = sec->size;
99059e56
RM		 17348 else
17349 end = map[i + 1].vma;
e489d0ae 17350
99059e56 17351 switch (map[i].type)
e489d0ae 17352 {
c7b8f16e
JB		 17353 case 'a':
17354 /* Byte swap code words. */
17355 while (ptr + 3 < end)
99059e56
RM		 17356 {
17357 tmp = contents[ptr];
17358 contents[ptr] = contents[ptr + 3];
17359 contents[ptr + 3] = tmp;
17360 tmp = contents[ptr + 1];
17361 contents[ptr + 1] = contents[ptr + 2];
17362 contents[ptr + 2] = tmp;
17363 ptr += 4;
17364 }
c7b8f16e 17365 break;
e489d0ae 17366
c7b8f16e
JB		 17367 case 't':
17368 /* Byte swap code halfwords. */
17369 while (ptr + 1 < end)
99059e56
RM		 17370 {
17371 tmp = contents[ptr];
17372 contents[ptr] = contents[ptr + 1];
17373 contents[ptr + 1] = tmp;
17374 ptr += 2;
17375 }
c7b8f16e
JB		 17376 break;
17377
17378 case 'd':
17379 /* Leave data alone. */
17380 break;
17381 }
99059e56
RM		 17382 ptr = end;
17383 }
e489d0ae 17384 }
8e3de13a 17385
93204d3a 17386 free (map);
47b2e99c 17387 arm_data->mapcount = -1;
c7b8f16e 17388 arm_data->mapsize = 0;
8e3de13a 17389 arm_data->map = NULL;
8e3de13a 17390
e489d0ae
PB		 17391 return FALSE;
17392}
17393
0beaef2b
PB		 17394/* Mangle thumb function symbols as we read them in. */
17395
8384fb8f 17396static bfd_boolean
0beaef2b
PB		 17397elf32_arm_swap_symbol_in (bfd * abfd,
17398 const void *psrc,
17399 const void *pshn,
17400 Elf_Internal_Sym *dst)
17401{
8384fb8f
AM		 17402 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
17403 return FALSE;
0beaef2b
PB		 17404
17405 /* New EABI objects mark thumb function symbols by setting the low bit of
35fc36a8 17406 the address. */
63e1a0fc
PB		 17407 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
17408 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
0beaef2b 17409 {
63e1a0fc
PB		 17410 if (dst->st_value & 1)
17411 {
17412 dst->st_value &= ~(bfd_vma) 1;
17413 dst->st_target_internal = ST_BRANCH_TO_THUMB;
17414 }
17415 else
17416 dst->st_target_internal = ST_BRANCH_TO_ARM;
35fc36a8
RS		 17417 }
17418 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
17419 {
17420 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
17421 dst->st_target_internal = ST_BRANCH_TO_THUMB;
0beaef2b 17422 }
35fc36a8
RS		 17423 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
17424 dst->st_target_internal = ST_BRANCH_LONG;
17425 else
63e1a0fc 17426 dst->st_target_internal = ST_BRANCH_UNKNOWN;
35fc36a8 17427
8384fb8f 17428 return TRUE;
0beaef2b
PB		 17429}
17430
17431
17432/* Mangle thumb function symbols as we write them out. */
17433
17434static void
17435elf32_arm_swap_symbol_out (bfd *abfd,
17436 const Elf_Internal_Sym *src,
17437 void *cdst,
17438 void *shndx)
17439{
17440 Elf_Internal_Sym newsym;
17441
17442 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
17443 of the address set, as per the new EABI. We do this unconditionally
17444 because objcopy does not set the elf header flags until after
17445 it writes out the symbol table. */
35fc36a8 17446 if (src->st_target_internal == ST_BRANCH_TO_THUMB)
0beaef2b
PB		 17447 {
17448 newsym = *src;
34e77a92
RS		 17449 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
17450 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
0fa3dcad 17451 if (newsym.st_shndx != SHN_UNDEF)
99059e56
RM		 17452 {
17453 /* Do this only for defined symbols. At link type, the static
17454 linker will simulate the work of dynamic linker of resolving
17455 symbols and will carry over the thumbness of found symbols to
17456 the output symbol table. It's not clear how it happens, but
17457 the thumbness of undefined symbols can well be different at
17458 runtime, and writing '1' for them will be confusing for users
17459 and possibly for dynamic linker itself.
17460 */
17461 newsym.st_value |= 1;
17462 }
906e58ca 17463
0beaef2b
PB		 17464 src = &newsym;
17465 }
17466 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
17467}
17468
b294bdf8
MM		 17469/* Add the PT_ARM_EXIDX program header. */
17470
17471static bfd_boolean
906e58ca 17472elf32_arm_modify_segment_map (bfd *abfd,
b294bdf8
MM		 17473 struct bfd_link_info *info ATTRIBUTE_UNUSED)
17474{
17475 struct elf_segment_map *m;
17476 asection *sec;
17477
17478 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
17479 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
17480 {
17481 /* If there is already a PT_ARM_EXIDX header, then we do not
17482 want to add another one. This situation arises when running
17483 "strip"; the input binary already has the header. */
12bd6957 17484 m = elf_seg_map (abfd);
b294bdf8
MM		 17485 while (m && m->p_type != PT_ARM_EXIDX)
17486 m = m->next;
17487 if (!m)
17488 {
21d799b5 17489 m = (struct elf_segment_map *)
99059e56 17490 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
b294bdf8
MM		 17491 if (m == NULL)
17492 return FALSE;
17493 m->p_type = PT_ARM_EXIDX;
17494 m->count = 1;
17495 m->sections[0] = sec;
17496
12bd6957
AM		 17497 m->next = elf_seg_map (abfd);
17498 elf_seg_map (abfd) = m;
b294bdf8
MM		 17499 }
17500 }
17501
17502 return TRUE;
17503}
17504
17505/* We may add a PT_ARM_EXIDX program header. */
17506
17507static int
a6b96beb
AM		 17508elf32_arm_additional_program_headers (bfd *abfd,
17509 struct bfd_link_info *info ATTRIBUTE_UNUSED)
b294bdf8
MM		 17510{
17511 asection *sec;
17512
17513 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
17514 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
17515 return 1;
17516 else
17517 return 0;
17518}
17519
34e77a92
RS		 17520/* Hook called by the linker routine which adds symbols from an object
17521 file. */
17522
17523static bfd_boolean
17524elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
17525 Elf_Internal_Sym *sym, const char **namep,
17526 flagword *flagsp, asection **secp, bfd_vma *valp)
17527{
f1885d1e
AM		 17528 if ((ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
17529 || ELF_ST_BIND (sym->st_info) == STB_GNU_UNIQUE)
17530 && (abfd->flags & DYNAMIC) == 0
17531 && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
13a2df29 17532 elf_tdata (info->output_bfd)->has_gnu_symbols = elf_gnu_symbol_any;
34e77a92 17533
c792917c
NC		 17534 if (elf32_arm_hash_table (info) == NULL)
17535 return FALSE;
17536
34e77a92
RS		 17537 if (elf32_arm_hash_table (info)->vxworks_p
17538 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
17539 flagsp, secp, valp))
17540 return FALSE;
17541
17542 return TRUE;
17543}
17544
0beaef2b 17545/* We use this to override swap_symbol_in and swap_symbol_out. */
906e58ca
NC		 17546const struct elf_size_info elf32_arm_size_info =
17547{
0beaef2b
PB		 17548 sizeof (Elf32_External_Ehdr),
17549 sizeof (Elf32_External_Phdr),
17550 sizeof (Elf32_External_Shdr),
17551 sizeof (Elf32_External_Rel),
17552 sizeof (Elf32_External_Rela),
17553 sizeof (Elf32_External_Sym),
17554 sizeof (Elf32_External_Dyn),
17555 sizeof (Elf_External_Note),
17556 4,
17557 1,
17558 32, 2,
17559 ELFCLASS32, EV_CURRENT,
17560 bfd_elf32_write_out_phdrs,
17561 bfd_elf32_write_shdrs_and_ehdr,
1489a3a0 17562 bfd_elf32_checksum_contents,
0beaef2b
PB		 17563 bfd_elf32_write_relocs,
17564 elf32_arm_swap_symbol_in,
17565 elf32_arm_swap_symbol_out,
17566 bfd_elf32_slurp_reloc_table,
17567 bfd_elf32_slurp_symbol_table,
17568 bfd_elf32_swap_dyn_in,
17569 bfd_elf32_swap_dyn_out,
17570 bfd_elf32_swap_reloc_in,
17571 bfd_elf32_swap_reloc_out,
17572 bfd_elf32_swap_reloca_in,
17573 bfd_elf32_swap_reloca_out
17574};
17575
685e70ae
VK		 17576static bfd_vma
17577read_code32 (const bfd *abfd, const bfd_byte *addr)
17578{
17579 /* V7 BE8 code is always little endian. */
17580 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
17581 return bfd_getl32 (addr);
17582
17583 return bfd_get_32 (abfd, addr);
17584}
17585
17586static bfd_vma
17587read_code16 (const bfd *abfd, const bfd_byte *addr)
17588{
17589 /* V7 BE8 code is always little endian. */
17590 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
17591 return bfd_getl16 (addr);
17592
17593 return bfd_get_16 (abfd, addr);
17594}
17595
6a631e86
YG		 17596/* Return size of plt0 entry starting at ADDR
17597 or (bfd_vma) -1 if size can not be determined. */
17598
17599static bfd_vma
17600elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
17601{
17602 bfd_vma first_word;
17603 bfd_vma plt0_size;
17604
685e70ae 17605 first_word = read_code32 (abfd, addr);
6a631e86
YG		 17606
17607 if (first_word == elf32_arm_plt0_entry[0])
17608 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
17609 else if (first_word == elf32_thumb2_plt0_entry[0])
17610 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
17611 else
17612 /* We don't yet handle this PLT format. */
17613 return (bfd_vma) -1;
17614
17615 return plt0_size;
17616}
17617
17618/* Return size of plt entry starting at offset OFFSET
17619 of plt section located at address START
17620 or (bfd_vma) -1 if size can not be determined. */
17621
17622static bfd_vma
17623elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
17624{
17625 bfd_vma first_insn;
17626 bfd_vma plt_size = 0;
17627 const bfd_byte *addr = start + offset;
17628
17629 /* PLT entry size if fixed on Thumb-only platforms. */
685e70ae 17630 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
6a631e86
YG		 17631 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
17632
17633 /* Respect Thumb stub if necessary. */
685e70ae 17634 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
6a631e86
YG		 17635 {
17636 plt_size += 2 * ARRAY_SIZE(elf32_arm_plt_thumb_stub);
17637 }
17638
17639 /* Strip immediate from first add. */
685e70ae 17640 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
6a631e86
YG		 17641
17642#ifdef FOUR_WORD_PLT
17643 if (first_insn == elf32_arm_plt_entry[0])
17644 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
17645#else
17646 if (first_insn == elf32_arm_plt_entry_long[0])
17647 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
17648 else if (first_insn == elf32_arm_plt_entry_short[0])
17649 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
17650#endif
17651 else
17652 /* We don't yet handle this PLT format. */
17653 return (bfd_vma) -1;
17654
17655 return plt_size;
17656}
17657
17658/* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
17659
17660static long
17661elf32_arm_get_synthetic_symtab (bfd *abfd,
17662 long symcount ATTRIBUTE_UNUSED,
17663 asymbol **syms ATTRIBUTE_UNUSED,
17664 long dynsymcount,
17665 asymbol **dynsyms,
17666 asymbol **ret)
17667{
17668 asection *relplt;
17669 asymbol *s;
17670 arelent *p;
17671 long count, i, n;
17672 size_t size;
17673 Elf_Internal_Shdr *hdr;
17674 char *names;
17675 asection *plt;
17676 bfd_vma offset;
17677 bfd_byte *data;
17678
17679 *ret = NULL;
17680
17681 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
17682 return 0;
17683
17684 if (dynsymcount <= 0)
17685 return 0;
17686
17687 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
17688 if (relplt == NULL)
17689 return 0;
17690
17691 hdr = &elf_section_data (relplt)->this_hdr;
17692 if (hdr->sh_link != elf_dynsymtab (abfd)
17693 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
17694 return 0;
17695
17696 plt = bfd_get_section_by_name (abfd, ".plt");
17697 if (plt == NULL)
17698 return 0;
17699
17700 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, TRUE))
17701 return -1;
17702
17703 data = plt->contents;
17704 if (data == NULL)
17705 {
17706 if (!bfd_get_full_section_contents(abfd, (asection *) plt, &data) || data == NULL)
17707 return -1;
17708 bfd_cache_section_contents((asection *) plt, data);
17709 }
17710
17711 count = relplt->size / hdr->sh_entsize;
17712 size = count * sizeof (asymbol);
17713 p = relplt->relocation;
17714 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
17715 {
17716 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
17717 if (p->addend != 0)
17718 size += sizeof ("+0x") - 1 + 8;
17719 }
17720
17721 s = *ret = (asymbol *) bfd_malloc (size);
17722 if (s == NULL)
17723 return -1;
17724
17725 offset = elf32_arm_plt0_size (abfd, data);
17726 if (offset == (bfd_vma) -1)
17727 return -1;
17728
17729 names = (char *) (s + count);
17730 p = relplt->relocation;
17731 n = 0;
17732 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
17733 {
17734 size_t len;
17735
17736 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
17737 if (plt_size == (bfd_vma) -1)
17738 break;
17739
17740 *s = **p->sym_ptr_ptr;
17741 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
17742 we are defining a symbol, ensure one of them is set. */
17743 if ((s->flags & BSF_LOCAL) == 0)
17744 s->flags |= BSF_GLOBAL;
17745 s->flags |= BSF_SYNTHETIC;
17746 s->section = plt;
17747 s->value = offset;
17748 s->name = names;
17749 s->udata.p = NULL;
17750 len = strlen ((*p->sym_ptr_ptr)->name);
17751 memcpy (names, (*p->sym_ptr_ptr)->name, len);
17752 names += len;
17753 if (p->addend != 0)
17754 {
17755 char buf[30], *a;
17756
17757 memcpy (names, "+0x", sizeof ("+0x") - 1);
17758 names += sizeof ("+0x") - 1;
17759 bfd_sprintf_vma (abfd, buf, p->addend);
17760 for (a = buf; *a == '0'; ++a)
17761 ;
17762 len = strlen (a);
17763 memcpy (names, a, len);
17764 names += len;
17765 }
17766 memcpy (names, "@plt", sizeof ("@plt"));
17767 names += sizeof ("@plt");
17768 ++s, ++n;
17769 offset += plt_size;
17770 }
17771
17772 return n;
17773}
17774
ac4c9b04
MG		 17775static const struct bfd_elf_special_section
17776elf32_arm_special_sections[] =
17777{
17778/* Catch sections with .text.noread prefix and apply allocate, execute and
17779 noread section attributes. */
17780 { STRING_COMMA_LEN (".text.noread"), -2, SHT_PROGBITS,
17781 SHF_ALLOC + SHF_EXECINSTR + SHF_ARM_NOREAD },
17782 { NULL, 0, 0, 0, 0 }
17783};
17784
17785static bfd_boolean
17786elf32_arm_section_flags (flagword *flags, const Elf_Internal_Shdr * hdr)
17787{
17788 if (hdr->sh_flags & SHF_ARM_NOREAD)
17789 *flags |= SEC_ELF_NOREAD;
17790 return TRUE;
17791}
17792
17793static flagword
17794elf32_arm_lookup_section_flags (char *flag_name)
17795{
17796 if (!strcmp (flag_name, "SHF_ARM_NOREAD"))
17797 return SHF_ARM_NOREAD;
17798
17799 return SEC_NO_FLAGS;
17800}
17801
491d01d3
YU		 17802static unsigned int
17803elf32_arm_count_additional_relocs (asection *sec)
17804{
17805 struct _arm_elf_section_data *arm_data;
17806 arm_data = get_arm_elf_section_data (sec);
17807 return arm_data->additional_reloc_count;
17808}
17809
252b5132 17810#define ELF_ARCH bfd_arch_arm
ae95ffa6 17811#define ELF_TARGET_ID ARM_ELF_DATA
252b5132 17812#define ELF_MACHINE_CODE EM_ARM
d0facd1b
NC		 17813#ifdef __QNXTARGET__
17814#define ELF_MAXPAGESIZE 0x1000
17815#else
7572ca89 17816#define ELF_MAXPAGESIZE 0x10000
d0facd1b 17817#endif
b1342370 17818#define ELF_MINPAGESIZE 0x1000
24718e3b 17819#define ELF_COMMONPAGESIZE 0x1000
252b5132 17820
ba93b8ac
DJ		 17821#define bfd_elf32_mkobject elf32_arm_mkobject
17822
99e4ae17
AJ		 17823#define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
17824#define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
252b5132
RH		 17825#define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
17826#define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
17827#define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
dc810e39 17828#define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
b38cadfb 17829#define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
252b5132 17830#define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
4ab527b0 17831#define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
e489d0ae 17832#define bfd_elf32_new_section_hook elf32_arm_new_section_hook
3c9458e9 17833#define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
3e6b1042 17834#define bfd_elf32_bfd_final_link elf32_arm_final_link
6a631e86 17835#define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
252b5132
RH		 17836
17837#define elf_backend_get_symbol_type elf32_arm_get_symbol_type
17838#define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
6a5bb875 17839#define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
252b5132
RH		 17840#define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
17841#define elf_backend_check_relocs elf32_arm_check_relocs
dc810e39 17842#define elf_backend_relocate_section elf32_arm_relocate_section
e489d0ae 17843#define elf_backend_write_section elf32_arm_write_section
252b5132 17844#define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
5e681ec4 17845#define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
252b5132
RH		 17846#define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
17847#define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
17848#define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
0855e32b 17849#define elf_backend_always_size_sections elf32_arm_always_size_sections
74541ad4 17850#define elf_backend_init_index_section _bfd_elf_init_2_index_sections
ba96a88f 17851#define elf_backend_post_process_headers elf32_arm_post_process_headers
99e4ae17 17852#define elf_backend_reloc_type_class elf32_arm_reloc_type_class
c178919b 17853#define elf_backend_object_p elf32_arm_object_p
40a18ebd
NC		 17854#define elf_backend_fake_sections elf32_arm_fake_sections
17855#define elf_backend_section_from_shdr elf32_arm_section_from_shdr
e16bb312 17856#define elf_backend_final_write_processing elf32_arm_final_write_processing
5e681ec4 17857#define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
0beaef2b 17858#define elf_backend_size_info elf32_arm_size_info
b294bdf8 17859#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
906e58ca
NC		 17860#define elf_backend_additional_program_headers elf32_arm_additional_program_headers
17861#define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
17862#define elf_backend_begin_write_processing elf32_arm_begin_write_processing
34e77a92 17863#define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
491d01d3 17864#define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
906e58ca
NC		 17865
17866#define elf_backend_can_refcount 1
17867#define elf_backend_can_gc_sections 1
17868#define elf_backend_plt_readonly 1
17869#define elf_backend_want_got_plt 1
17870#define elf_backend_want_plt_sym 0
17871#define elf_backend_may_use_rel_p 1
17872#define elf_backend_may_use_rela_p 0
4e7fd91e 17873#define elf_backend_default_use_rela_p 0
252b5132 17874
04f7c78d 17875#define elf_backend_got_header_size 12
b68a20d6 17876#define elf_backend_extern_protected_data 1
04f7c78d 17877
906e58ca
NC		 17878#undef elf_backend_obj_attrs_vendor
17879#define elf_backend_obj_attrs_vendor "aeabi"
17880#undef elf_backend_obj_attrs_section
17881#define elf_backend_obj_attrs_section ".ARM.attributes"
17882#undef elf_backend_obj_attrs_arg_type
17883#define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
17884#undef elf_backend_obj_attrs_section_type
104d59d1 17885#define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
b38cadfb
NC		 17886#define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
17887#define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
104d59d1 17888
ac4c9b04
MG		 17889#undef elf_backend_special_sections
17890#define elf_backend_special_sections elf32_arm_special_sections
17891#undef elf_backend_section_flags
17892#define elf_backend_section_flags elf32_arm_section_flags
17893#undef elf_backend_lookup_section_flags_hook
17894#define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
17895
252b5132 17896#include "elf32-target.h"
7f266840 17897
b38cadfb
NC		 17898/* Native Client targets. */
17899
17900#undef TARGET_LITTLE_SYM
6d00b590 17901#define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
b38cadfb
NC		 17902#undef TARGET_LITTLE_NAME
17903#define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
17904#undef TARGET_BIG_SYM
6d00b590 17905#define TARGET_BIG_SYM arm_elf32_nacl_be_vec
b38cadfb
NC		 17906#undef TARGET_BIG_NAME
17907#define TARGET_BIG_NAME "elf32-bigarm-nacl"
17908
17909/* Like elf32_arm_link_hash_table_create -- but overrides
17910 appropriately for NaCl. */
17911
17912static struct bfd_link_hash_table *
17913elf32_arm_nacl_link_hash_table_create (bfd *abfd)
17914{
17915 struct bfd_link_hash_table *ret;
17916
17917 ret = elf32_arm_link_hash_table_create (abfd);
17918 if (ret)
17919 {
17920 struct elf32_arm_link_hash_table *htab
17921 = (struct elf32_arm_link_hash_table *) ret;
17922
17923 htab->nacl_p = 1;
17924
17925 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
17926 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
17927 }
17928 return ret;
17929}
17930
17931/* Since NaCl doesn't use the ARM-specific unwind format, we don't
17932 really need to use elf32_arm_modify_segment_map. But we do it
17933 anyway just to reduce gratuitous differences with the stock ARM backend. */
17934
17935static bfd_boolean
17936elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
17937{
17938 return (elf32_arm_modify_segment_map (abfd, info)
17939 && nacl_modify_segment_map (abfd, info));
17940}
17941
887badb3
RM		 17942static void
17943elf32_arm_nacl_final_write_processing (bfd *abfd, bfd_boolean linker)
17944{
17945 elf32_arm_final_write_processing (abfd, linker);
17946 nacl_final_write_processing (abfd, linker);
17947}
17948
6a631e86
YG		 17949static bfd_vma
17950elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
17951 const arelent *rel ATTRIBUTE_UNUSED)
17952{
17953 return plt->vma
17954 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
17955 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
17956}
887badb3 17957
b38cadfb 17958#undef elf32_bed
6a631e86 17959#define elf32_bed elf32_arm_nacl_bed
b38cadfb
NC		 17960#undef bfd_elf32_bfd_link_hash_table_create
17961#define bfd_elf32_bfd_link_hash_table_create \
17962 elf32_arm_nacl_link_hash_table_create
17963#undef elf_backend_plt_alignment
6a631e86 17964#define elf_backend_plt_alignment 4
b38cadfb
NC		 17965#undef elf_backend_modify_segment_map
17966#define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
17967#undef elf_backend_modify_program_headers
17968#define elf_backend_modify_program_headers nacl_modify_program_headers
887badb3
RM		 17969#undef elf_backend_final_write_processing
17970#define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
6a631e86
YG		 17971#undef bfd_elf32_get_synthetic_symtab
17972#undef elf_backend_plt_sym_val
17973#define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
b38cadfb 17974
887badb3
RM		 17975#undef ELF_MINPAGESIZE
17976#undef ELF_COMMONPAGESIZE
17977
b38cadfb
NC		 17978
17979#include "elf32-target.h"
17980
17981/* Reset to defaults. */
17982#undef elf_backend_plt_alignment
17983#undef elf_backend_modify_segment_map
17984#define elf_backend_modify_segment_map elf32_arm_modify_segment_map
17985#undef elf_backend_modify_program_headers
887badb3
RM		 17986#undef elf_backend_final_write_processing
17987#define elf_backend_final_write_processing elf32_arm_final_write_processing
17988#undef ELF_MINPAGESIZE
17989#define ELF_MINPAGESIZE 0x1000
17990#undef ELF_COMMONPAGESIZE
17991#define ELF_COMMONPAGESIZE 0x1000
17992
b38cadfb 17993
906e58ca 17994/* VxWorks Targets. */
4e7fd91e 17995
906e58ca 17996#undef TARGET_LITTLE_SYM
6d00b590 17997#define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
906e58ca 17998#undef TARGET_LITTLE_NAME
4e7fd91e 17999#define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
906e58ca 18000#undef TARGET_BIG_SYM
6d00b590 18001#define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
906e58ca 18002#undef TARGET_BIG_NAME
4e7fd91e
PB		 18003#define TARGET_BIG_NAME "elf32-bigarm-vxworks"
18004
18005/* Like elf32_arm_link_hash_table_create -- but overrides
18006 appropriately for VxWorks. */
906e58ca 18007
4e7fd91e
PB		 18008static struct bfd_link_hash_table *
18009elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
18010{
18011 struct bfd_link_hash_table *ret;
18012
18013 ret = elf32_arm_link_hash_table_create (abfd);
18014 if (ret)
18015 {
18016 struct elf32_arm_link_hash_table *htab
00a97672 18017 = (struct elf32_arm_link_hash_table *) ret;
4e7fd91e 18018 htab->use_rel = 0;
00a97672 18019 htab->vxworks_p = 1;
4e7fd91e
PB		 18020 }
18021 return ret;
906e58ca 18022}
4e7fd91e 18023
00a97672
RS		 18024static void
18025elf32_arm_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker)
18026{
18027 elf32_arm_final_write_processing (abfd, linker);
18028 elf_vxworks_final_write_processing (abfd, linker);
18029}
18030
906e58ca 18031#undef elf32_bed
4e7fd91e
PB		 18032#define elf32_bed elf32_arm_vxworks_bed
18033
906e58ca
NC		 18034#undef bfd_elf32_bfd_link_hash_table_create
18035#define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
906e58ca
NC		 18036#undef elf_backend_final_write_processing
18037#define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
18038#undef elf_backend_emit_relocs
18039#define elf_backend_emit_relocs elf_vxworks_emit_relocs
4e7fd91e 18040
906e58ca 18041#undef elf_backend_may_use_rel_p
00a97672 18042#define elf_backend_may_use_rel_p 0
906e58ca 18043#undef elf_backend_may_use_rela_p
00a97672 18044#define elf_backend_may_use_rela_p 1
906e58ca 18045#undef elf_backend_default_use_rela_p
00a97672 18046#define elf_backend_default_use_rela_p 1
906e58ca 18047#undef elf_backend_want_plt_sym
00a97672 18048#define elf_backend_want_plt_sym 1
906e58ca 18049#undef ELF_MAXPAGESIZE
00a97672 18050#define ELF_MAXPAGESIZE 0x1000
4e7fd91e
PB		 18051
18052#include "elf32-target.h"
18053
18054
21d799b5
NC		 18055/* Merge backend specific data from an object file to the output
18056 object file when linking. */
18057
18058static bfd_boolean
18059elf32_arm_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
18060{
18061 flagword out_flags;
18062 flagword in_flags;
18063 bfd_boolean flags_compatible = TRUE;
18064 asection *sec;
18065
cc643b88 18066 /* Check if we have the same endianness. */
21d799b5
NC		 18067 if (! _bfd_generic_verify_endian_match (ibfd, obfd))
18068 return FALSE;
18069
18070 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
18071 return TRUE;
18072
18073 if (!elf32_arm_merge_eabi_attributes (ibfd, obfd))
18074 return FALSE;
18075
18076 /* The input BFD must have had its flags initialised. */
18077 /* The following seems bogus to me -- The flags are initialized in
18078 the assembler but I don't think an elf_flags_init field is
18079 written into the object. */
18080 /* BFD_ASSERT (elf_flags_init (ibfd)); */
18081
18082 in_flags = elf_elfheader (ibfd)->e_flags;
18083 out_flags = elf_elfheader (obfd)->e_flags;
18084
18085 /* In theory there is no reason why we couldn't handle this. However
18086 in practice it isn't even close to working and there is no real
18087 reason to want it. */
18088 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
18089 && !(ibfd->flags & DYNAMIC)
18090 && (in_flags & EF_ARM_BE8))
18091 {
18092 _bfd_error_handler (_("error: %B is already in final BE8 format"),
18093 ibfd);
18094 return FALSE;
18095 }
18096
18097 if (!elf_flags_init (obfd))
18098 {
18099 /* If the input is the default architecture and had the default
18100 flags then do not bother setting the flags for the output
18101 architecture, instead allow future merges to do this. If no
18102 future merges ever set these flags then they will retain their
99059e56
RM		 18103 uninitialised values, which surprise surprise, correspond
18104 to the default values. */
21d799b5
NC		 18105 if (bfd_get_arch_info (ibfd)->the_default
18106 && elf_elfheader (ibfd)->e_flags == 0)
18107 return TRUE;
18108
18109 elf_flags_init (obfd) = TRUE;
18110 elf_elfheader (obfd)->e_flags = in_flags;
18111
18112 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
18113 && bfd_get_arch_info (obfd)->the_default)
18114 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
18115
18116 return TRUE;
18117 }
18118
18119 /* Determine what should happen if the input ARM architecture
18120 does not match the output ARM architecture. */
18121 if (! bfd_arm_merge_machines (ibfd, obfd))
18122 return FALSE;
18123
18124 /* Identical flags must be compatible. */
18125 if (in_flags == out_flags)
18126 return TRUE;
18127
18128 /* Check to see if the input BFD actually contains any sections. If
18129 not, its flags may not have been initialised either, but it
18130 cannot actually cause any incompatiblity. Do not short-circuit
18131 dynamic objects; their section list may be emptied by
18132 elf_link_add_object_symbols.
18133
18134 Also check to see if there are no code sections in the input.
18135 In this case there is no need to check for code specific flags.
18136 XXX - do we need to worry about floating-point format compatability
18137 in data sections ? */
18138 if (!(ibfd->flags & DYNAMIC))
18139 {
18140 bfd_boolean null_input_bfd = TRUE;
18141 bfd_boolean only_data_sections = TRUE;
18142
18143 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
18144 {
18145 /* Ignore synthetic glue sections. */
18146 if (strcmp (sec->name, ".glue_7")
18147 && strcmp (sec->name, ".glue_7t"))
18148 {
18149 if ((bfd_get_section_flags (ibfd, sec)
18150 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
18151 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
99059e56 18152 only_data_sections = FALSE;
21d799b5
NC		 18153
18154 null_input_bfd = FALSE;
18155 break;
18156 }
18157 }
18158
18159 if (null_input_bfd || only_data_sections)
18160 return TRUE;
18161 }
18162
18163 /* Complain about various flag mismatches. */
18164 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
18165 EF_ARM_EABI_VERSION (out_flags)))
18166 {
18167 _bfd_error_handler
18168 (_("error: Source object %B has EABI version %d, but target %B has EABI version %d"),
18169 ibfd, obfd,
18170 (in_flags & EF_ARM_EABIMASK) >> 24,
18171 (out_flags & EF_ARM_EABIMASK) >> 24);
18172 return FALSE;
18173 }
18174
18175 /* Not sure what needs to be checked for EABI versions >= 1. */
18176 /* VxWorks libraries do not use these flags. */
18177 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
18178 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
18179 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
18180 {
18181 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
18182 {
18183 _bfd_error_handler
18184 (_("error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d"),
18185 ibfd, obfd,
18186 in_flags & EF_ARM_APCS_26 ? 26 : 32,
18187 out_flags & EF_ARM_APCS_26 ? 26 : 32);
18188 flags_compatible = FALSE;
18189 }
18190
18191 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
18192 {
18193 if (in_flags & EF_ARM_APCS_FLOAT)
18194 _bfd_error_handler
18195 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
18196 ibfd, obfd);
18197 else
18198 _bfd_error_handler
18199 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
18200 ibfd, obfd);
18201
18202 flags_compatible = FALSE;
18203 }
18204
18205 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
18206 {
18207 if (in_flags & EF_ARM_VFP_FLOAT)
18208 _bfd_error_handler
18209 (_("error: %B uses VFP instructions, whereas %B does not"),
18210 ibfd, obfd);
18211 else
18212 _bfd_error_handler
18213 (_("error: %B uses FPA instructions, whereas %B does not"),
18214 ibfd, obfd);
18215
18216 flags_compatible = FALSE;
18217 }
18218
18219 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
18220 {
18221 if (in_flags & EF_ARM_MAVERICK_FLOAT)
18222 _bfd_error_handler
18223 (_("error: %B uses Maverick instructions, whereas %B does not"),
18224 ibfd, obfd);
18225 else
18226 _bfd_error_handler
18227 (_("error: %B does not use Maverick instructions, whereas %B does"),
18228 ibfd, obfd);
18229
18230 flags_compatible = FALSE;
18231 }
18232
18233#ifdef EF_ARM_SOFT_FLOAT
18234 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
18235 {
18236 /* We can allow interworking between code that is VFP format
18237 layout, and uses either soft float or integer regs for
18238 passing floating point arguments and results. We already
18239 know that the APCS_FLOAT flags match; similarly for VFP
18240 flags. */
18241 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
18242 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
18243 {
18244 if (in_flags & EF_ARM_SOFT_FLOAT)
18245 _bfd_error_handler
18246 (_("error: %B uses software FP, whereas %B uses hardware FP"),
18247 ibfd, obfd);
18248 else
18249 _bfd_error_handler
18250 (_("error: %B uses hardware FP, whereas %B uses software FP"),
18251 ibfd, obfd);
18252
18253 flags_compatible = FALSE;
18254 }
18255 }
18256#endif
18257
18258 /* Interworking mismatch is only a warning. */
18259 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
18260 {
18261 if (in_flags & EF_ARM_INTERWORK)
18262 {
18263 _bfd_error_handler
18264 (_("Warning: %B supports interworking, whereas %B does not"),
18265 ibfd, obfd);
18266 }
18267 else
18268 {
18269 _bfd_error_handler
18270 (_("Warning: %B does not support interworking, whereas %B does"),
18271 ibfd, obfd);
18272 }
18273 }
18274 }
18275
18276 return flags_compatible;
18277}
18278
18279
906e58ca 18280/* Symbian OS Targets. */
7f266840 18281
906e58ca 18282#undef TARGET_LITTLE_SYM
6d00b590 18283#define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
906e58ca 18284#undef TARGET_LITTLE_NAME
7f266840 18285#define TARGET_LITTLE_NAME "elf32-littlearm-symbian"
906e58ca 18286#undef TARGET_BIG_SYM
6d00b590 18287#define TARGET_BIG_SYM arm_elf32_symbian_be_vec
906e58ca 18288#undef TARGET_BIG_NAME
7f266840
DJ		 18289#define TARGET_BIG_NAME "elf32-bigarm-symbian"
18290
18291/* Like elf32_arm_link_hash_table_create -- but overrides
18292 appropriately for Symbian OS. */
906e58ca 18293
7f266840
DJ		 18294static struct bfd_link_hash_table *
18295elf32_arm_symbian_link_hash_table_create (bfd *abfd)
18296{
18297 struct bfd_link_hash_table *ret;
18298
18299 ret = elf32_arm_link_hash_table_create (abfd);
18300 if (ret)
18301 {
18302 struct elf32_arm_link_hash_table *htab
18303 = (struct elf32_arm_link_hash_table *)ret;
18304 /* There is no PLT header for Symbian OS. */
18305 htab->plt_header_size = 0;
95720a86
DJ		 18306 /* The PLT entries are each one instruction and one word. */
18307 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry);
7f266840 18308 htab->symbian_p = 1;
33bfe774
JB		 18309 /* Symbian uses armv5t or above, so use_blx is always true. */
18310 htab->use_blx = 1;
67687978 18311 htab->root.is_relocatable_executable = 1;
7f266840
DJ		 18312 }
18313 return ret;
906e58ca 18314}
7f266840 18315
b35d266b 18316static const struct bfd_elf_special_section
551b43fd 18317elf32_arm_symbian_special_sections[] =
7f266840 18318{
5cd3778d
MM		 18319 /* In a BPABI executable, the dynamic linking sections do not go in
18320 the loadable read-only segment. The post-linker may wish to
18321 refer to these sections, but they are not part of the final
18322 program image. */
0112cd26
NC		 18323 { STRING_COMMA_LEN (".dynamic"), 0, SHT_DYNAMIC, 0 },
18324 { STRING_COMMA_LEN (".dynstr"), 0, SHT_STRTAB, 0 },
18325 { STRING_COMMA_LEN (".dynsym"), 0, SHT_DYNSYM, 0 },
18326 { STRING_COMMA_LEN (".got"), 0, SHT_PROGBITS, 0 },
18327 { STRING_COMMA_LEN (".hash"), 0, SHT_HASH, 0 },
5cd3778d
MM		 18328 /* These sections do not need to be writable as the SymbianOS
18329 postlinker will arrange things so that no dynamic relocation is
18330 required. */
0112cd26
NC		 18331 { STRING_COMMA_LEN (".init_array"), 0, SHT_INIT_ARRAY, SHF_ALLOC },
18332 { STRING_COMMA_LEN (".fini_array"), 0, SHT_FINI_ARRAY, SHF_ALLOC },
18333 { STRING_COMMA_LEN (".preinit_array"), 0, SHT_PREINIT_ARRAY, SHF_ALLOC },
18334 { NULL, 0, 0, 0, 0 }
7f266840
DJ		 18335};
18336
c3c76620 18337static void
906e58ca 18338elf32_arm_symbian_begin_write_processing (bfd *abfd,
a4fd1a8e 18339 struct bfd_link_info *link_info)
c3c76620
MM		 18340{
18341 /* BPABI objects are never loaded directly by an OS kernel; they are
18342 processed by a postlinker first, into an OS-specific format. If
18343 the D_PAGED bit is set on the file, BFD will align segments on
18344 page boundaries, so that an OS can directly map the file. With
18345 BPABI objects, that just results in wasted space. In addition,
18346 because we clear the D_PAGED bit, map_sections_to_segments will
18347 recognize that the program headers should not be mapped into any
18348 loadable segment. */
18349 abfd->flags &= ~D_PAGED;
906e58ca 18350 elf32_arm_begin_write_processing (abfd, link_info);
c3c76620 18351}
7f266840
DJ		 18352
18353static bfd_boolean
906e58ca 18354elf32_arm_symbian_modify_segment_map (bfd *abfd,
b294bdf8 18355 struct bfd_link_info *info)
7f266840
DJ		 18356{
18357 struct elf_segment_map *m;
18358 asection *dynsec;
18359
7f266840
DJ		 18360 /* BPABI shared libraries and executables should have a PT_DYNAMIC
18361 segment. However, because the .dynamic section is not marked
18362 with SEC_LOAD, the generic ELF code will not create such a
18363 segment. */
18364 dynsec = bfd_get_section_by_name (abfd, ".dynamic");
18365 if (dynsec)
18366 {
12bd6957 18367 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
8ded5a0f
AM		 18368 if (m->p_type == PT_DYNAMIC)
18369 break;
18370
18371 if (m == NULL)
18372 {
18373 m = _bfd_elf_make_dynamic_segment (abfd, dynsec);
12bd6957
AM		 18374 m->next = elf_seg_map (abfd);
18375 elf_seg_map (abfd) = m;
8ded5a0f 18376 }
7f266840
DJ		 18377 }
18378
b294bdf8
MM		 18379 /* Also call the generic arm routine. */
18380 return elf32_arm_modify_segment_map (abfd, info);
7f266840
DJ		 18381}
18382
95720a86
DJ		 18383/* Return address for Ith PLT stub in section PLT, for relocation REL
18384 or (bfd_vma) -1 if it should not be included. */
18385
18386static bfd_vma
18387elf32_arm_symbian_plt_sym_val (bfd_vma i, const asection *plt,
18388 const arelent *rel ATTRIBUTE_UNUSED)
18389{
18390 return plt->vma + 4 * ARRAY_SIZE (elf32_arm_symbian_plt_entry) * i;
18391}
18392
18393
8029a119 18394#undef elf32_bed
7f266840
DJ		 18395#define elf32_bed elf32_arm_symbian_bed
18396
18397/* The dynamic sections are not allocated on SymbianOS; the postlinker
18398 will process them and then discard them. */
906e58ca 18399#undef ELF_DYNAMIC_SEC_FLAGS
7f266840
DJ		 18400#define ELF_DYNAMIC_SEC_FLAGS \
18401 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
18402
00a97672 18403#undef elf_backend_emit_relocs
c3c76620 18404
906e58ca
NC		 18405#undef bfd_elf32_bfd_link_hash_table_create
18406#define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
18407#undef elf_backend_special_sections
18408#define elf_backend_special_sections elf32_arm_symbian_special_sections
18409#undef elf_backend_begin_write_processing
18410#define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
18411#undef elf_backend_final_write_processing
18412#define elf_backend_final_write_processing elf32_arm_final_write_processing
18413
18414#undef elf_backend_modify_segment_map
7f266840
DJ		 18415#define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
18416
18417/* There is no .got section for BPABI objects, and hence no header. */
906e58ca 18418#undef elf_backend_got_header_size
7f266840
DJ		 18419#define elf_backend_got_header_size 0
18420
18421/* Similarly, there is no .got.plt section. */
906e58ca 18422#undef elf_backend_want_got_plt
7f266840
DJ		 18423#define elf_backend_want_got_plt 0
18424
906e58ca 18425#undef elf_backend_plt_sym_val
95720a86
DJ		 18426#define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
18427
906e58ca 18428#undef elf_backend_may_use_rel_p
00a97672 18429#define elf_backend_may_use_rel_p 1
906e58ca 18430#undef elf_backend_may_use_rela_p
00a97672 18431#define elf_backend_may_use_rela_p 0
906e58ca 18432#undef elf_backend_default_use_rela_p
00a97672 18433#define elf_backend_default_use_rela_p 0
906e58ca 18434#undef elf_backend_want_plt_sym
00a97672 18435#define elf_backend_want_plt_sym 0
906e58ca 18436#undef ELF_MAXPAGESIZE
00a97672 18437#define ELF_MAXPAGESIZE 0x8000
4e7fd91e 18438
7f266840 18439#include "elf32-target.h"
GDB Binutils - Deliverables
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