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Append $PLT_CFLAGS to CC/CXX for S-records tests
[deliverable/binutils-gdb.git] / bfd / elf32-msp430.c
CommitLineData
2469cfa2 1/* MSP430-specific support for 32-bit ELF
b90efa5b 2 Copyright (C) 2002-2015 Free Software Foundation, Inc.
2469cfa2
NC		 3 Contributed by Dmitry Diky <diwil@mail.ru>
4
5 This file is part of BFD, the Binary File Descriptor library.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
cd123cb7 9 the Free Software Foundation; either version 3 of the License, or
2469cfa2
NC		 10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
cd123cb7
NC		 19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
2469cfa2 21
2469cfa2 22#include "sysdep.h"
3db64b00 23#include "bfd.h"
2469cfa2
NC		 24#include "libiberty.h"
25#include "libbfd.h"
26#include "elf-bfd.h"
27#include "elf/msp430.h"
28
1ade7175
NC		 29static bfd_reloc_status_type
30rl78_sym_diff_handler (bfd * abfd,
31 arelent * reloc,
32 asymbol * sym ATTRIBUTE_UNUSED,
33 void * addr ATTRIBUTE_UNUSED,
34 asection * input_sec,
35 bfd * out_bfd ATTRIBUTE_UNUSED,
36 char ** error_message ATTRIBUTE_UNUSED)
37{
38 bfd_size_type octets;
39 octets = reloc->address * bfd_octets_per_byte (abfd);
40
41 /* Catch the case where bfd_install_relocation would return
42 bfd_reloc_outofrange because the SYM_DIFF reloc is being used in a very
43 small section. It does not actually matter if this happens because all
44 that SYM_DIFF does is compute a (4-byte) value. A second reloc then uses
45 this value, and it is that reloc that must fit into the section.
46
47 This happens in eg, gcc/testsuite/gcc.c-torture/compile/labels-3.c. */
48 if ((octets + bfd_get_reloc_size (reloc->howto))
49 > bfd_get_section_limit_octets (abfd, input_sec))
50 return bfd_reloc_ok;
51 return bfd_reloc_continue;
52}
53
2469cfa2
NC		 54static reloc_howto_type elf_msp430_howto_table[] =
55{
56 HOWTO (R_MSP430_NONE, /* type */
57 0, /* rightshift */
6346d5ca
AM		 58 3, /* size (0 = byte, 1 = short, 2 = long) */
59 0, /* bitsize */
2469cfa2
NC		 60 FALSE, /* pc_relative */
61 0, /* bitpos */
6346d5ca 62 complain_overflow_dont,/* complain_on_overflow */
2469cfa2
NC		 63 bfd_elf_generic_reloc, /* special_function */
64 "R_MSP430_NONE", /* name */
65 FALSE, /* partial_inplace */
66 0, /* src_mask */
67 0, /* dst_mask */
68 FALSE), /* pcrel_offset */
69
70 HOWTO (R_MSP430_32, /* type */
71 0, /* rightshift */
72 2, /* size (0 = byte, 1 = short, 2 = long) */
73 32, /* bitsize */
74 FALSE, /* pc_relative */
75 0, /* bitpos */
b18c562e 76 complain_overflow_bitfield,/* complain_on_overflow */
2469cfa2
NC		 77 bfd_elf_generic_reloc, /* special_function */
78 "R_MSP430_32", /* name */
79 FALSE, /* partial_inplace */
80 0xffffffff, /* src_mask */
81 0xffffffff, /* dst_mask */
82 FALSE), /* pcrel_offset */
83
df301bfc 84 /* A 10 bit PC relative relocation. */
2469cfa2
NC		 85 HOWTO (R_MSP430_10_PCREL, /* type */
86 1, /* rightshift */
87 1, /* size (0 = byte, 1 = short, 2 = long) */
88 10, /* bitsize */
89 TRUE, /* pc_relative */
90 0, /* bitpos */
b18c562e 91 complain_overflow_bitfield,/* complain_on_overflow */
2469cfa2 92 bfd_elf_generic_reloc, /* special_function */
13761a11 93 "R_MSP430_10_PCREL", /* name */
2469cfa2 94 FALSE, /* partial_inplace */
df301bfc
NC		 95 0x3ff, /* src_mask */
96 0x3ff, /* dst_mask */
2469cfa2
NC		 97 TRUE), /* pcrel_offset */
98
99 /* A 16 bit absolute relocation. */
100 HOWTO (R_MSP430_16, /* type */
101 0, /* rightshift */
102 1, /* size (0 = byte, 1 = short, 2 = long) */
103 16, /* bitsize */
104 FALSE, /* pc_relative */
105 0, /* bitpos */
106 complain_overflow_dont,/* complain_on_overflow */
107 bfd_elf_generic_reloc, /* special_function */
108 "R_MSP430_16", /* name */
109 FALSE, /* partial_inplace */
b18c562e 110 0, /* src_mask */
2469cfa2
NC		 111 0xffff, /* dst_mask */
112 FALSE), /* pcrel_offset */
113
13761a11 114 /* A 16 bit PC relative relocation for command address. */
2469cfa2
NC		 115 HOWTO (R_MSP430_16_PCREL, /* type */
116 1, /* rightshift */
117 1, /* size (0 = byte, 1 = short, 2 = long) */
118 16, /* bitsize */
119 TRUE, /* pc_relative */
120 0, /* bitpos */
121 complain_overflow_dont,/* complain_on_overflow */
122 bfd_elf_generic_reloc, /* special_function */
123 "R_MSP430_16_PCREL", /* name */
124 FALSE, /* partial_inplace */
b18c562e 125 0, /* src_mask */
2469cfa2
NC		 126 0xffff, /* dst_mask */
127 TRUE), /* pcrel_offset */
128
129 /* A 16 bit absolute relocation, byte operations. */
130 HOWTO (R_MSP430_16_BYTE, /* type */
131 0, /* rightshift */
132 1, /* size (0 = byte, 1 = short, 2 = long) */
133 16, /* bitsize */
134 FALSE, /* pc_relative */
135 0, /* bitpos */
136 complain_overflow_dont,/* complain_on_overflow */
137 bfd_elf_generic_reloc, /* special_function */
138 "R_MSP430_16_BYTE", /* name */
139 FALSE, /* partial_inplace */
140 0xffff, /* src_mask */
141 0xffff, /* dst_mask */
142 FALSE), /* pcrel_offset */
143
144 /* A 16 bit absolute relocation for command address. */
145 HOWTO (R_MSP430_16_PCREL_BYTE,/* type */
146 1, /* rightshift */
147 1, /* size (0 = byte, 1 = short, 2 = long) */
148 16, /* bitsize */
149 TRUE, /* pc_relative */
150 0, /* bitpos */
151 complain_overflow_dont,/* complain_on_overflow */
152 bfd_elf_generic_reloc, /* special_function */
b18c562e 153 "R_MSP430_16_PCREL_BYTE",/* name */
2469cfa2
NC		 154 FALSE, /* partial_inplace */
155 0xffff, /* src_mask */
156 0xffff, /* dst_mask */
b18c562e
NC		 157 TRUE), /* pcrel_offset */
158
df301bfc 159 /* A 10 bit PC relative relocation for complicated polymorphs. */
b18c562e
NC		 160 HOWTO (R_MSP430_2X_PCREL, /* type */
161 1, /* rightshift */
162 2, /* size (0 = byte, 1 = short, 2 = long) */
163 10, /* bitsize */
164 TRUE, /* pc_relative */
165 0, /* bitpos */
166 complain_overflow_bitfield,/* complain_on_overflow */
167 bfd_elf_generic_reloc, /* special_function */
168 "R_MSP430_2X_PCREL", /* name */
169 FALSE, /* partial_inplace */
df301bfc
NC		 170 0x3ff, /* src_mask */
171 0x3ff, /* dst_mask */
b18c562e
NC		 172 TRUE), /* pcrel_offset */
173
174 /* A 16 bit relaxable relocation for command address. */
175 HOWTO (R_MSP430_RL_PCREL, /* type */
176 1, /* rightshift */
177 1, /* size (0 = byte, 1 = short, 2 = long) */
178 16, /* bitsize */
179 TRUE, /* pc_relative */
180 0, /* bitpos */
181 complain_overflow_dont,/* complain_on_overflow */
182 bfd_elf_generic_reloc, /* special_function */
183 "R_MSP430_RL_PCREL", /* name */
184 FALSE, /* partial_inplace */
185 0, /* src_mask */
186 0xffff, /* dst_mask */
2469cfa2 187 TRUE) /* pcrel_offset */
13761a11
NC		 188
189 /* A 8-bit absolute relocation. */
190 , HOWTO (R_MSP430_8, /* type */
191 0, /* rightshift */
192 0, /* size (0 = byte, 1 = short, 2 = long) */
193 8, /* bitsize */
194 FALSE, /* pc_relative */
195 0, /* bitpos */
196 complain_overflow_dont,/* complain_on_overflow */
197 bfd_elf_generic_reloc, /* special_function */
198 "R_MSP430_8", /* name */
199 FALSE, /* partial_inplace */
200 0, /* src_mask */
201 0xffff, /* dst_mask */
202 FALSE), /* pcrel_offset */
203
204 /* Together with a following reloc, allows for the difference
205 between two symbols to be the real addend of the second reloc. */
206 HOWTO (R_MSP430_SYM_DIFF, /* type */
207 0, /* rightshift */
208 2, /* size (0 = byte, 1 = short, 2 = long) */
209 32, /* bitsize */
210 FALSE, /* pc_relative */
211 0, /* bitpos */
212 complain_overflow_dont,/* complain_on_overflow */
1ade7175 213 rl78_sym_diff_handler, /* special handler. */
13761a11
NC		 214 "R_MSP430_SYM_DIFF", /* name */
215 FALSE, /* partial_inplace */
216 0xffffffff, /* src_mask */
217 0xffffffff, /* dst_mask */
218 FALSE) /* pcrel_offset */
219};
220
221static reloc_howto_type elf_msp430x_howto_table[] =
222{
223 HOWTO (R_MSP430_NONE, /* type */
224 0, /* rightshift */
6346d5ca
AM		 225 3, /* size (0 = byte, 1 = short, 2 = long) */
226 0, /* bitsize */
13761a11
NC		 227 FALSE, /* pc_relative */
228 0, /* bitpos */
6346d5ca 229 complain_overflow_dont,/* complain_on_overflow */
13761a11
NC		 230 bfd_elf_generic_reloc, /* special_function */
231 "R_MSP430_NONE", /* name */
232 FALSE, /* partial_inplace */
233 0, /* src_mask */
234 0, /* dst_mask */
235 FALSE), /* pcrel_offset */
236
237 HOWTO (R_MSP430_ABS32, /* type */
238 0, /* rightshift */
239 2, /* size (0 = byte, 1 = short, 2 = long) */
240 32, /* bitsize */
241 FALSE, /* pc_relative */
242 0, /* bitpos */
243 complain_overflow_bitfield,/* complain_on_overflow */
244 bfd_elf_generic_reloc, /* special_function */
245 "R_MSP430_ABS32", /* name */
246 FALSE, /* partial_inplace */
247 0xffffffff, /* src_mask */
248 0xffffffff, /* dst_mask */
249 FALSE), /* pcrel_offset */
250
251 HOWTO (R_MSP430_ABS16, /* type */
252 0, /* rightshift */
253 1, /* size (0 = byte, 1 = short, 2 = long) */
254 16, /* bitsize */
255 FALSE, /* pc_relative */
256 0, /* bitpos */
257 complain_overflow_dont,/* complain_on_overflow */
258 bfd_elf_generic_reloc, /* special_function */
259 "R_MSP430_ABS16", /* name */
260 FALSE, /* partial_inplace */
261 0, /* src_mask */
262 0xffff, /* dst_mask */
263 FALSE), /* pcrel_offset */
264
265 HOWTO (R_MSP430_ABS8, /* type */
266 0, /* rightshift */
267 0, /* size (0 = byte, 1 = short, 2 = long) */
268 8, /* bitsize */
269 FALSE, /* pc_relative */
270 0, /* bitpos */
271 complain_overflow_bitfield,/* complain_on_overflow */
272 bfd_elf_generic_reloc, /* special_function */
273 "R_MSP430_ABS8", /* name */
274 FALSE, /* partial_inplace */
275 0xff, /* src_mask */
276 0xff, /* dst_mask */
277 FALSE), /* pcrel_offset */
278
279 HOWTO (R_MSP430_PCR16, /* type */
280 1, /* rightshift */
281 1, /* size (0 = byte, 1 = short, 2 = long) */
282 16, /* bitsize */
283 TRUE, /* pc_relative */
284 0, /* bitpos */
285 complain_overflow_dont,/* complain_on_overflow */
286 bfd_elf_generic_reloc, /* special_function */
287 "R_MSP430_PCR16", /* name */
288 FALSE, /* partial_inplace */
289 0, /* src_mask */
290 0xffff, /* dst_mask */
291 TRUE), /* pcrel_offset */
292
293 HOWTO (R_MSP430X_PCR20_EXT_SRC,/* type */
294 0, /* rightshift */
295 2, /* size (0 = byte, 1 = short, 2 = long) */
296 32, /* bitsize */
297 TRUE, /* pc_relative */
298 0, /* bitpos */
299 complain_overflow_dont,/* complain_on_overflow */
300 bfd_elf_generic_reloc, /* special_function */
301 "R_MSP430X_PCR20_EXT_SRC",/* name */
302 FALSE, /* partial_inplace */
303 0, /* src_mask */
304 0xffff, /* dst_mask */
305 TRUE), /* pcrel_offset */
306
307 HOWTO (R_MSP430X_PCR20_EXT_DST,/* type */
308 0, /* rightshift */
309 2, /* size (0 = byte, 1 = short, 2 = long) */
310 32, /* bitsize */
311 TRUE, /* pc_relative */
312 0, /* bitpos */
313 complain_overflow_dont,/* complain_on_overflow */
314 bfd_elf_generic_reloc, /* special_function */
315 "R_MSP430X_PCR20_EXT_DST",/* name */
316 FALSE, /* partial_inplace */
317 0, /* src_mask */
318 0xffff, /* dst_mask */
319 TRUE), /* pcrel_offset */
320
321 HOWTO (R_MSP430X_PCR20_EXT_ODST,/* type */
322 0, /* rightshift */
323 2, /* size (0 = byte, 1 = short, 2 = long) */
324 32, /* bitsize */
325 TRUE, /* pc_relative */
326 0, /* bitpos */
327 complain_overflow_dont,/* complain_on_overflow */
328 bfd_elf_generic_reloc, /* special_function */
329 "R_MSP430X_PCR20_EXT_ODST",/* name */
330 FALSE, /* partial_inplace */
331 0, /* src_mask */
332 0xffff, /* dst_mask */
333 TRUE), /* pcrel_offset */
334
335 HOWTO (R_MSP430X_ABS20_EXT_SRC,/* type */
336 0, /* rightshift */
337 2, /* size (0 = byte, 1 = short, 2 = long) */
338 32, /* bitsize */
339 TRUE, /* pc_relative */
340 0, /* bitpos */
341 complain_overflow_dont,/* complain_on_overflow */
342 bfd_elf_generic_reloc, /* special_function */
343 "R_MSP430X_ABS20_EXT_SRC",/* name */
344 FALSE, /* partial_inplace */
345 0, /* src_mask */
346 0xffff, /* dst_mask */
347 TRUE), /* pcrel_offset */
348
349 HOWTO (R_MSP430X_ABS20_EXT_DST,/* type */
350 0, /* rightshift */
351 2, /* size (0 = byte, 1 = short, 2 = long) */
352 32, /* bitsize */
353 TRUE, /* pc_relative */
354 0, /* bitpos */
355 complain_overflow_dont,/* complain_on_overflow */
356 bfd_elf_generic_reloc, /* special_function */
357 "R_MSP430X_ABS20_EXT_DST",/* name */
358 FALSE, /* partial_inplace */
359 0, /* src_mask */
360 0xffff, /* dst_mask */
361 TRUE), /* pcrel_offset */
362
363 HOWTO (R_MSP430X_ABS20_EXT_ODST,/* type */
364 0, /* rightshift */
365 2, /* size (0 = byte, 1 = short, 2 = long) */
366 32, /* bitsize */
367 TRUE, /* pc_relative */
368 0, /* bitpos */
369 complain_overflow_dont,/* complain_on_overflow */
370 bfd_elf_generic_reloc, /* special_function */
371 "R_MSP430X_ABS20_EXT_ODST",/* name */
372 FALSE, /* partial_inplace */
373 0, /* src_mask */
374 0xffff, /* dst_mask */
375 TRUE), /* pcrel_offset */
376
377 HOWTO (R_MSP430X_ABS20_ADR_SRC,/* type */
378 0, /* rightshift */
379 2, /* size (0 = byte, 1 = short, 2 = long) */
380 32, /* bitsize */
381 TRUE, /* pc_relative */
382 0, /* bitpos */
383 complain_overflow_dont,/* complain_on_overflow */
384 bfd_elf_generic_reloc, /* special_function */
385 "R_MSP430X_ABS20_ADR_SRC",/* name */
386 FALSE, /* partial_inplace */
387 0, /* src_mask */
388 0xffff, /* dst_mask */
389 TRUE), /* pcrel_offset */
390
391 HOWTO (R_MSP430X_ABS20_ADR_DST,/* type */
392 0, /* rightshift */
393 2, /* size (0 = byte, 1 = short, 2 = long) */
394 32, /* bitsize */
395 TRUE, /* pc_relative */
396 0, /* bitpos */
397 complain_overflow_dont,/* complain_on_overflow */
398 bfd_elf_generic_reloc, /* special_function */
399 "R_MSP430X_ABS20_ADR_DST",/* name */
400 FALSE, /* partial_inplace */
401 0, /* src_mask */
402 0xffff, /* dst_mask */
403 TRUE), /* pcrel_offset */
404
405 HOWTO (R_MSP430X_PCR16, /* type */
406 0, /* rightshift */
407 2, /* size (0 = byte, 1 = short, 2 = long) */
408 32, /* bitsize */
409 TRUE, /* pc_relative */
410 0, /* bitpos */
411 complain_overflow_dont,/* complain_on_overflow */
412 bfd_elf_generic_reloc, /* special_function */
413 "R_MSP430X_PCR16", /* name */
414 FALSE, /* partial_inplace */
415 0, /* src_mask */
416 0xffff, /* dst_mask */
417 TRUE), /* pcrel_offset */
418
419 HOWTO (R_MSP430X_PCR20_CALL, /* type */
420 0, /* rightshift */
421 2, /* size (0 = byte, 1 = short, 2 = long) */
422 32, /* bitsize */
423 TRUE, /* pc_relative */
424 0, /* bitpos */
425 complain_overflow_dont,/* complain_on_overflow */
426 bfd_elf_generic_reloc, /* special_function */
427 "R_MSP430X_PCR20_CALL",/* name */
428 FALSE, /* partial_inplace */
429 0, /* src_mask */
430 0xffff, /* dst_mask */
431 TRUE), /* pcrel_offset */
432
433 HOWTO (R_MSP430X_ABS16, /* type */
434 0, /* rightshift */
435 2, /* size (0 = byte, 1 = short, 2 = long) */
436 32, /* bitsize */
437 TRUE, /* pc_relative */
438 0, /* bitpos */
439 complain_overflow_dont,/* complain_on_overflow */
440 bfd_elf_generic_reloc, /* special_function */
441 "R_MSP430X_ABS16", /* name */
442 FALSE, /* partial_inplace */
443 0, /* src_mask */
444 0xffff, /* dst_mask */
445 TRUE), /* pcrel_offset */
446
447 HOWTO (R_MSP430_ABS_HI16, /* type */
448 0, /* rightshift */
449 2, /* size (0 = byte, 1 = short, 2 = long) */
450 32, /* bitsize */
451 TRUE, /* pc_relative */
452 0, /* bitpos */
453 complain_overflow_dont,/* complain_on_overflow */
454 bfd_elf_generic_reloc, /* special_function */
455 "R_MSP430_ABS_HI16", /* name */
456 FALSE, /* partial_inplace */
457 0, /* src_mask */
458 0xffff, /* dst_mask */
459 TRUE), /* pcrel_offset */
460
461 HOWTO (R_MSP430_PREL31, /* type */
462 0, /* rightshift */
463 2, /* size (0 = byte, 1 = short, 2 = long) */
464 32, /* bitsize */
465 TRUE, /* pc_relative */
466 0, /* bitpos */
467 complain_overflow_dont,/* complain_on_overflow */
468 bfd_elf_generic_reloc, /* special_function */
469 "R_MSP430_PREL31", /* name */
470 FALSE, /* partial_inplace */
471 0, /* src_mask */
472 0xffff, /* dst_mask */
473 TRUE), /* pcrel_offset */
474
475 EMPTY_HOWTO (R_MSP430_EHTYPE),
476
df301bfc 477 /* A 10 bit PC relative relocation. */
13761a11
NC		 478 HOWTO (R_MSP430X_10_PCREL, /* type */
479 1, /* rightshift */
480 1, /* size (0 = byte, 1 = short, 2 = long) */
481 10, /* bitsize */
482 TRUE, /* pc_relative */
483 0, /* bitpos */
484 complain_overflow_bitfield,/* complain_on_overflow */
485 bfd_elf_generic_reloc, /* special_function */
486 "R_MSP430X_10_PCREL", /* name */
487 FALSE, /* partial_inplace */
df301bfc
NC		 488 0x3ff, /* src_mask */
489 0x3ff, /* dst_mask */
13761a11
NC		 490 TRUE), /* pcrel_offset */
491
df301bfc 492 /* A 10 bit PC relative relocation for complicated polymorphs. */
13761a11
NC		 493 HOWTO (R_MSP430X_2X_PCREL, /* type */
494 1, /* rightshift */
495 2, /* size (0 = byte, 1 = short, 2 = long) */
496 10, /* bitsize */
497 TRUE, /* pc_relative */
498 0, /* bitpos */
499 complain_overflow_bitfield,/* complain_on_overflow */
500 bfd_elf_generic_reloc, /* special_function */
501 "R_MSP430X_2X_PCREL", /* name */
502 FALSE, /* partial_inplace */
df301bfc
NC		 503 0x3ff, /* src_mask */
504 0x3ff, /* dst_mask */
13761a11
NC		 505 TRUE), /* pcrel_offset */
506
507 /* Together with a following reloc, allows for the difference
508 between two symbols to be the real addend of the second reloc. */
509 HOWTO (R_MSP430X_SYM_DIFF, /* type */
510 0, /* rightshift */
511 2, /* size (0 = byte, 1 = short, 2 = long) */
512 32, /* bitsize */
513 FALSE, /* pc_relative */
514 0, /* bitpos */
515 complain_overflow_dont,/* complain_on_overflow */
1ade7175 516 rl78_sym_diff_handler, /* special handler. */
13761a11
NC		 517 "R_MSP430X_SYM_DIFF", /* name */
518 FALSE, /* partial_inplace */
519 0xffffffff, /* src_mask */
520 0xffffffff, /* dst_mask */
521 FALSE) /* pcrel_offset */
2469cfa2
NC		 522};
523
524/* Map BFD reloc types to MSP430 ELF reloc types. */
525
526struct msp430_reloc_map
527{
528 bfd_reloc_code_real_type bfd_reloc_val;
529 unsigned int elf_reloc_val;
530};
531
532static const struct msp430_reloc_map msp430_reloc_map[] =
13761a11
NC		 533{
534 {BFD_RELOC_NONE, R_MSP430_NONE},
535 {BFD_RELOC_32, R_MSP430_32},
536 {BFD_RELOC_MSP430_10_PCREL, R_MSP430_10_PCREL},
537 {BFD_RELOC_16, R_MSP430_16_BYTE},
538 {BFD_RELOC_MSP430_16_PCREL, R_MSP430_16_PCREL},
539 {BFD_RELOC_MSP430_16, R_MSP430_16},
540 {BFD_RELOC_MSP430_16_PCREL_BYTE, R_MSP430_16_PCREL_BYTE},
541 {BFD_RELOC_MSP430_16_BYTE, R_MSP430_16_BYTE},
542 {BFD_RELOC_MSP430_2X_PCREL, R_MSP430_2X_PCREL},
543 {BFD_RELOC_MSP430_RL_PCREL, R_MSP430_RL_PCREL},
544 {BFD_RELOC_8, R_MSP430_8},
545 {BFD_RELOC_MSP430_SYM_DIFF, R_MSP430_SYM_DIFF}
546};
547
548static const struct msp430_reloc_map msp430x_reloc_map[] =
549{
550 {BFD_RELOC_NONE, R_MSP430_NONE},
551 {BFD_RELOC_32, R_MSP430_ABS32},
552 {BFD_RELOC_16, R_MSP430_ABS16},
553 {BFD_RELOC_8, R_MSP430_ABS8},
554 {BFD_RELOC_MSP430_ABS8, R_MSP430_ABS8},
555 {BFD_RELOC_MSP430X_PCR20_EXT_SRC, R_MSP430X_PCR20_EXT_SRC},
556 {BFD_RELOC_MSP430X_PCR20_EXT_DST, R_MSP430X_PCR20_EXT_DST},
557 {BFD_RELOC_MSP430X_PCR20_EXT_ODST, R_MSP430X_PCR20_EXT_ODST},
558 {BFD_RELOC_MSP430X_ABS20_EXT_SRC, R_MSP430X_ABS20_EXT_SRC},
559 {BFD_RELOC_MSP430X_ABS20_EXT_DST, R_MSP430X_ABS20_EXT_DST},
560 {BFD_RELOC_MSP430X_ABS20_EXT_ODST, R_MSP430X_ABS20_EXT_ODST},
561 {BFD_RELOC_MSP430X_ABS20_ADR_SRC, R_MSP430X_ABS20_ADR_SRC},
562 {BFD_RELOC_MSP430X_ABS20_ADR_DST, R_MSP430X_ABS20_ADR_DST},
563 {BFD_RELOC_MSP430X_PCR16, R_MSP430X_PCR16},
564 {BFD_RELOC_MSP430X_PCR20_CALL, R_MSP430X_PCR20_CALL},
565 {BFD_RELOC_MSP430X_ABS16, R_MSP430X_ABS16},
566 {BFD_RELOC_MSP430_ABS_HI16, R_MSP430_ABS_HI16},
567 {BFD_RELOC_MSP430_PREL31, R_MSP430_PREL31},
568 {BFD_RELOC_MSP430_10_PCREL, R_MSP430X_10_PCREL},
569 {BFD_RELOC_MSP430_2X_PCREL, R_MSP430X_2X_PCREL},
570 {BFD_RELOC_MSP430_RL_PCREL, R_MSP430X_PCR16},
571 {BFD_RELOC_MSP430_SYM_DIFF, R_MSP430X_SYM_DIFF}
572};
573
574static inline bfd_boolean
575uses_msp430x_relocs (bfd * abfd)
576{
6d00b590 577 extern const bfd_target msp430_elf32_ti_vec;
13761a11
NC		 578
579 return bfd_get_mach (abfd) == bfd_mach_msp430x
6d00b590 580 || abfd->xvec == & msp430_elf32_ti_vec;
13761a11 581}
2469cfa2
NC		 582
583static reloc_howto_type *
b18c562e
NC		 584bfd_elf32_bfd_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
585 bfd_reloc_code_real_type code)
2469cfa2
NC		 586{
587 unsigned int i;
588
13761a11
NC		 589 if (uses_msp430x_relocs (abfd))
590 {
591 for (i = ARRAY_SIZE (msp430x_reloc_map); i--;)
592 if (msp430x_reloc_map[i].bfd_reloc_val == code)
593 return elf_msp430x_howto_table + msp430x_reloc_map[i].elf_reloc_val;
594 }
595 else
596 {
597 for (i = 0; i < ARRAY_SIZE (msp430_reloc_map); i++)
598 if (msp430_reloc_map[i].bfd_reloc_val == code)
599 return &elf_msp430_howto_table[msp430_reloc_map[i].elf_reloc_val];
600 }
2469cfa2
NC		 601
602 return NULL;
603}
604
157090f7
AM		 605static reloc_howto_type *
606bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
607 const char *r_name)
608{
609 unsigned int i;
610
13761a11
NC		 611 if (uses_msp430x_relocs (abfd))
612 {
613 for (i = ARRAY_SIZE (elf_msp430x_howto_table); i--;)
614 if (elf_msp430x_howto_table[i].name != NULL
615 && strcasecmp (elf_msp430x_howto_table[i].name, r_name) == 0)
616 return elf_msp430x_howto_table + i;
617 }
618 else
619 {
620 for (i = 0;
621 i < (sizeof (elf_msp430_howto_table)
622 / sizeof (elf_msp430_howto_table[0]));
623 i++)
624 if (elf_msp430_howto_table[i].name != NULL
625 && strcasecmp (elf_msp430_howto_table[i].name, r_name) == 0)
626 return &elf_msp430_howto_table[i];
627 }
157090f7
AM		 628
629 return NULL;
630}
631
2469cfa2
NC		 632/* Set the howto pointer for an MSP430 ELF reloc. */
633
634static void
b18c562e
NC		 635msp430_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED,
636 arelent * cache_ptr,
637 Elf_Internal_Rela * dst)
2469cfa2
NC		 638{
639 unsigned int r_type;
640
641 r_type = ELF32_R_TYPE (dst->r_info);
13761a11
NC		 642
643 if (uses_msp430x_relocs (abfd))
644 {
5860e3f8
NC		 645 if (r_type >= (unsigned int) R_MSP430x_max)
646 {
64d29018 647 _bfd_error_handler (_("%B: invalid MSP430X reloc number: %d"), abfd, r_type);
5860e3f8
NC		 648 r_type = 0;
649 }
13761a11
NC		 650 cache_ptr->howto = elf_msp430x_howto_table + r_type;
651 return;
652 }
653
5860e3f8
NC		 654 if (r_type >= (unsigned int) R_MSP430_max)
655 {
64d29018 656 _bfd_error_handler (_("%B: invalid MSP430 reloc number: %d"), abfd, r_type);
5860e3f8
NC		 657 r_type = 0;
658 }
2469cfa2
NC		 659 cache_ptr->howto = &elf_msp430_howto_table[r_type];
660}
661
2469cfa2
NC		 662/* Look through the relocs for a section during the first phase.
663 Since we don't do .gots or .plts, we just need to consider the
664 virtual table relocs for gc. */
665
666static bfd_boolean
b18c562e
NC		 667elf32_msp430_check_relocs (bfd * abfd, struct bfd_link_info * info,
668 asection * sec, const Elf_Internal_Rela * relocs)
2469cfa2
NC		 669{
670 Elf_Internal_Shdr *symtab_hdr;
5582a088 671 struct elf_link_hash_entry **sym_hashes;
2469cfa2
NC		 672 const Elf_Internal_Rela *rel;
673 const Elf_Internal_Rela *rel_end;
674
1049f94e 675 if (info->relocatable)
2469cfa2
NC		 676 return TRUE;
677
678 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
679 sym_hashes = elf_sym_hashes (abfd);
2469cfa2
NC		 680
681 rel_end = relocs + sec->reloc_count;
682 for (rel = relocs; rel < rel_end; rel++)
683 {
684 struct elf_link_hash_entry *h;
685 unsigned long r_symndx;
686
687 r_symndx = ELF32_R_SYM (rel->r_info);
688 if (r_symndx < symtab_hdr->sh_info)
689 h = NULL;
690 else
973a3492
L		 691 {
692 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
693 while (h->root.type == bfd_link_hash_indirect
694 || h->root.type == bfd_link_hash_warning)
695 h = (struct elf_link_hash_entry *) h->root.u.i.link;
81fbe831
AM		 696
697 /* PR15323, ref flags aren't set for references in the same
698 object. */
699 h->root.non_ir_ref = 1;
973a3492 700 }
2469cfa2
NC		 701 }
702
703 return TRUE;
704}
705
706/* Perform a single relocation. By default we use the standard BFD
707 routines, but a few relocs, we have to do them ourselves. */
708
709static bfd_reloc_status_type
13761a11
NC		 710msp430_final_link_relocate (reloc_howto_type * howto,
711 bfd * input_bfd,
712 asection * input_section,
713 bfd_byte * contents,
714 Elf_Internal_Rela * rel,
715 bfd_vma relocation,
716 struct bfd_link_info * info)
2469cfa2 717{
13761a11
NC		 718 static asection * sym_diff_section;
719 static bfd_vma sym_diff_value;
720
721 struct bfd_elf_section_data * esd = elf_section_data (input_section);
2469cfa2
NC		 722 bfd_reloc_status_type r = bfd_reloc_ok;
723 bfd_vma x;
724 bfd_signed_vma srel;
13761a11
NC		 725 bfd_boolean is_rel_reloc = FALSE;
726
727 if (uses_msp430x_relocs (input_bfd))
728 {
729 /* See if we have a REL type relocation. */
730 is_rel_reloc = (esd->rel.hdr != NULL);
731 /* Sanity check - only one type of relocation per section.
732 FIXME: Theoretically it is possible to have both types,
733 but if that happens how can we distinguish between the two ? */
734 BFD_ASSERT (! is_rel_reloc || ! esd->rela.hdr);
735 /* If we are using a REL relocation then the addend should be empty. */
736 BFD_ASSERT (! is_rel_reloc || rel->r_addend == 0);
737 }
2469cfa2 738
13761a11 739 if (sym_diff_section != NULL)
2469cfa2 740 {
13761a11
NC		 741 BFD_ASSERT (sym_diff_section == input_section);
742
743 if (uses_msp430x_relocs (input_bfd))
744 switch (howto->type)
745 {
746 case R_MSP430_ABS32:
747 /* If we are computing a 32-bit value for the location lists
748 and the result is 0 then we add one to the value. A zero
749 value can result because of linker relaxation deleteing
750 prologue instructions and using a value of 1 (for the begin
751 and end offsets in the location list entry) results in a
752 nul entry which does not prevent the following entries from
753 being parsed. */
754 if (relocation == sym_diff_value
755 && strcmp (input_section->name, ".debug_loc") == 0)
756 ++ relocation;
757 /* Fall through. */
758 case R_MSP430_ABS16:
759 case R_MSP430X_ABS16:
760 case R_MSP430_ABS8:
761 BFD_ASSERT (! is_rel_reloc);
762 relocation -= sym_diff_value;
763 break;
764
765 default:
766 return bfd_reloc_dangerous;
767 }
768 else
769 switch (howto->type)
770 {
771 case R_MSP430_32:
772 case R_MSP430_16:
773 case R_MSP430_16_BYTE:
774 case R_MSP430_8:
775 relocation -= sym_diff_value;
776 break;
777
778 default:
779 return bfd_reloc_dangerous;
780 }
781
782 sym_diff_section = NULL;
783 }
784
785 if (uses_msp430x_relocs (input_bfd))
786 switch (howto->type)
787 {
788 case R_MSP430X_SYM_DIFF:
789 /* Cache the input section and value.
790 The offset is unreliable, since relaxation may
791 have reduced the following reloc's offset. */
792 BFD_ASSERT (! is_rel_reloc);
793 sym_diff_section = input_section;
794 sym_diff_value = relocation;
795 return bfd_reloc_ok;
796
797 case R_MSP430_ABS16:
798 contents += rel->r_offset;
799 srel = (bfd_signed_vma) relocation;
800 if (is_rel_reloc)
801 srel += bfd_get_16 (input_bfd, contents);
802 else
803 srel += rel->r_addend;
804 bfd_put_16 (input_bfd, srel & 0xffff, contents);
805 break;
806
807 case R_MSP430X_10_PCREL:
808 contents += rel->r_offset;
809 srel = (bfd_signed_vma) relocation;
810 if (is_rel_reloc)
811 srel += bfd_get_16 (input_bfd, contents) & 0x3ff;
812 else
813 srel += rel->r_addend;
814 srel -= rel->r_offset;
815 srel -= 2; /* Branch instructions add 2 to the PC... */
816 srel -= (input_section->output_section->vma +
817 input_section->output_offset);
818 if (srel & 1)
819 return bfd_reloc_outofrange;
820
821 /* MSP430 addresses commands as words. */
822 srel >>= 1;
823
824 /* Check for an overflow. */
825 if (srel < -512 || srel > 511)
826 {
827 if (info->disable_target_specific_optimizations < 0)
828 {
829 static bfd_boolean warned = FALSE;
830 if (! warned)
831 {
832 info->callbacks->warning
833 (info,
834 _("Try enabling relaxation to avoid relocation truncations"),
835 NULL, input_bfd, input_section, relocation);
836 warned = TRUE;
837 }
838 }
839 return bfd_reloc_overflow;
840 }
841
842 x = bfd_get_16 (input_bfd, contents);
843 x = (x & 0xfc00) | (srel & 0x3ff);
844 bfd_put_16 (input_bfd, x, contents);
845 break;
846
847 case R_MSP430X_PCR20_EXT_ODST:
3f307074 848 /* [0,4]+[48,16] = ---F ---- ---- FFFF */
13761a11
NC		 849 contents += rel->r_offset;
850 srel = (bfd_signed_vma) relocation;
851 if (is_rel_reloc)
852 {
853 bfd_vma addend;
854 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
3f307074 855 addend |= bfd_get_16 (input_bfd, contents + 6);
13761a11
NC		 856 srel += addend;
857
858 }
859 else
860 srel += rel->r_addend;
861 srel -= rel->r_offset;
862 srel -= (input_section->output_section->vma +
863 input_section->output_offset);
864 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 6);
865 x = bfd_get_16 (input_bfd, contents);
866 x = (x & 0xfff0) | ((srel >> 16) & 0xf);
867 bfd_put_16 (input_bfd, x, contents);
868 break;
869
870 case R_MSP430X_ABS20_EXT_SRC:
3f307074 871 /* [7,4]+[32,16] = -78- ---- FFFF */
13761a11
NC		 872 contents += rel->r_offset;
873 srel = (bfd_signed_vma) relocation;
874 if (is_rel_reloc)
875 {
876 bfd_vma addend;
877 addend = (bfd_get_16 (input_bfd, contents) & 0x0780) << 9;
3f307074 878 addend |= bfd_get_16 (input_bfd, contents + 4);
13761a11
NC		 879 srel += addend;
880 }
881 else
882 srel += rel->r_addend;
883 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
884 srel >>= 16;
885 x = bfd_get_16 (input_bfd, contents);
886 x = (x & 0xf87f) | ((srel << 7) & 0x0780);
887 bfd_put_16 (input_bfd, x, contents);
888 break;
889
890 case R_MSP430_16_PCREL:
891 contents += rel->r_offset;
892 srel = (bfd_signed_vma) relocation;
893 if (is_rel_reloc)
894 srel += bfd_get_16 (input_bfd, contents);
895 else
896 srel += rel->r_addend;
897 srel -= rel->r_offset;
898 /* Only branch instructions add 2 to the PC... */
899 srel -= (input_section->output_section->vma +
900 input_section->output_offset);
901 if (srel & 1)
902 return bfd_reloc_outofrange;
903 bfd_put_16 (input_bfd, srel & 0xffff, contents);
904 break;
905
906 case R_MSP430X_PCR20_EXT_DST:
3f307074 907 /* [0,4]+[32,16] = ---F ---- FFFF */
13761a11
NC		 908 contents += rel->r_offset;
909 srel = (bfd_signed_vma) relocation;
910 if (is_rel_reloc)
911 {
912 bfd_vma addend;
913 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
3f307074 914 addend |= bfd_get_16 (input_bfd, contents + 4);
13761a11
NC		 915 srel += addend;
916 }
917 else
918 srel += rel->r_addend;
919 srel -= rel->r_offset;
920 srel -= (input_section->output_section->vma +
921 input_section->output_offset);
922 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
923 srel >>= 16;
924 x = bfd_get_16 (input_bfd, contents);
925 x = (x & 0xfff0) | (srel & 0xf);
926 bfd_put_16 (input_bfd, x, contents);
927 break;
928
929 case R_MSP430X_PCR20_EXT_SRC:
3f307074 930 /* [7,4]+[32,16] = -78- ---- FFFF */
13761a11
NC		 931 contents += rel->r_offset;
932 srel = (bfd_signed_vma) relocation;
933 if (is_rel_reloc)
934 {
935 bfd_vma addend;
936 addend = ((bfd_get_16 (input_bfd, contents) & 0x0780) << 9);
3f307074 937 addend |= bfd_get_16 (input_bfd, contents + 4);
13761a11
NC		 938 srel += addend;;
939 }
940 else
941 srel += rel->r_addend;
942 srel -= rel->r_offset;
943 /* Only branch instructions add 2 to the PC... */
944 srel -= (input_section->output_section->vma +
945 input_section->output_offset);
946 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
947 srel >>= 16;
948 x = bfd_get_16 (input_bfd, contents);
949 x = (x & 0xf87f) | ((srel << 7) & 0x0780);
950 bfd_put_16 (input_bfd, x, contents);
951 break;
952
953 case R_MSP430_ABS8:
954 contents += rel->r_offset;
955 srel = (bfd_signed_vma) relocation;
956 if (is_rel_reloc)
957 srel += bfd_get_8 (input_bfd, contents);
958 else
959 srel += rel->r_addend;
960 bfd_put_8 (input_bfd, srel & 0xff, contents);
961 break;
962
963 case R_MSP430X_ABS20_EXT_DST:
3f307074 964 /* [0,4]+[32,16] = ---F ---- FFFF */
13761a11
NC		 965 contents += rel->r_offset;
966 srel = (bfd_signed_vma) relocation;
967 if (is_rel_reloc)
3f307074
DD		 968 {
969 bfd_vma addend;
970 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
971 addend |= bfd_get_16 (input_bfd, contents + 4);
972 srel += addend;
973 }
13761a11
NC		 974 else
975 srel += rel->r_addend;
976 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
977 srel >>= 16;
978 x = bfd_get_16 (input_bfd, contents);
979 x = (x & 0xfff0) | (srel & 0xf);
980 bfd_put_16 (input_bfd, x, contents);
981 break;
982
983 case R_MSP430X_ABS20_EXT_ODST:
3f307074 984 /* [0,4]+[48,16] = ---F ---- ---- FFFF */
13761a11
NC		 985 contents += rel->r_offset;
986 srel = (bfd_signed_vma) relocation;
987 if (is_rel_reloc)
988 {
989 bfd_vma addend;
990 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
3f307074 991 addend |= bfd_get_16 (input_bfd, contents + 6);
13761a11
NC		 992 srel += addend;
993 }
994 else
995 srel += rel->r_addend;
996 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 6);
997 srel >>= 16;
998 x = bfd_get_16 (input_bfd, contents);
999 x = (x & 0xfff0) | (srel & 0xf);
1000 bfd_put_16 (input_bfd, x, contents);
1001 break;
1002
1003 case R_MSP430X_ABS20_ADR_SRC:
3f307074 1004 /* [8,4]+[16,16] = -F-- FFFF */
13761a11
NC		 1005 contents += rel->r_offset;
1006 srel = (bfd_signed_vma) relocation;
1007 if (is_rel_reloc)
1008 {
1009 bfd_vma addend;
1010
1011 addend = ((bfd_get_16 (input_bfd, contents) & 0xf00) << 8);
3f307074 1012 addend |= bfd_get_16 (input_bfd, contents + 2);
13761a11
NC		 1013 srel += addend;
1014 }
1015 else
1016 srel += rel->r_addend;
1017 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 2);
1018 srel >>= 16;
1019 x = bfd_get_16 (input_bfd, contents);
1020 x = (x & 0xf0ff) | ((srel << 8) & 0x0f00);
1021 bfd_put_16 (input_bfd, x, contents);
1022 break;
1023
1024 case R_MSP430X_ABS20_ADR_DST:
3f307074 1025 /* [0,4]+[16,16] = ---F FFFF */
13761a11
NC		 1026 contents += rel->r_offset;
1027 srel = (bfd_signed_vma) relocation;
1028 if (is_rel_reloc)
1029 {
1030 bfd_vma addend;
1031 addend = ((bfd_get_16 (input_bfd, contents) & 0xf) << 16);
3f307074 1032 addend |= bfd_get_16 (input_bfd, contents + 2);
13761a11
NC		 1033 srel += addend;
1034 }
1035 else
1036 srel += rel->r_addend;
1037 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 2);
1038 srel >>= 16;
1039 x = bfd_get_16 (input_bfd, contents);
1040 x = (x & 0xfff0) | (srel & 0xf);
1041 bfd_put_16 (input_bfd, x, contents);
1042 break;
1043
1044 case R_MSP430X_ABS16:
1045 contents += rel->r_offset;
1046 srel = (bfd_signed_vma) relocation;
1047 if (is_rel_reloc)
1048 srel += bfd_get_16 (input_bfd, contents);
1049 else
1050 srel += rel->r_addend;
1051 x = srel;
1052 if (x > 0xffff)
1053 return bfd_reloc_overflow;
1054 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1055 break;
1056
1057 case R_MSP430_ABS_HI16:
1058 /* The EABI specifies that this must be a RELA reloc. */
1059 BFD_ASSERT (! is_rel_reloc);
1060 contents += rel->r_offset;
1061 srel = (bfd_signed_vma) relocation;
1062 srel += rel->r_addend;
1063 bfd_put_16 (input_bfd, (srel >> 16) & 0xffff, contents);
1064 break;
1065
1066 case R_MSP430X_PCR20_CALL:
3f307074 1067 /* [0,4]+[16,16] = ---F FFFF*/
13761a11
NC		 1068 contents += rel->r_offset;
1069 srel = (bfd_signed_vma) relocation;
1070 if (is_rel_reloc)
1071 {
1072 bfd_vma addend;
1073 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
3f307074 1074 addend |= bfd_get_16 (input_bfd, contents + 2);
13761a11
NC		 1075 srel += addend;
1076 }
1077 else
1078 srel += rel->r_addend;
1079 srel -= rel->r_offset;
1080 srel -= (input_section->output_section->vma +
1081 input_section->output_offset);
1082 bfd_put_16 (input_bfd, srel & 0xffff, contents + 2);
1083 srel >>= 16;
1084 x = bfd_get_16 (input_bfd, contents);
1085 x = (x & 0xfff0) | (srel & 0xf);
1086 bfd_put_16 (input_bfd, x, contents);
1087 break;
1088
1089 case R_MSP430X_PCR16:
1090 contents += rel->r_offset;
1091 srel = (bfd_signed_vma) relocation;
1092 if (is_rel_reloc)
1093 srel += bfd_get_16 (input_bfd, contents);
1094 else
1095 srel += rel->r_addend;
1096 srel -= rel->r_offset;
1097 srel -= (input_section->output_section->vma +
1098 input_section->output_offset);
1099 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1100 break;
1101
1102 case R_MSP430_PREL31:
1103 contents += rel->r_offset;
1104 srel = (bfd_signed_vma) relocation;
1105 if (is_rel_reloc)
1106 srel += (bfd_get_32 (input_bfd, contents) & 0x7fffffff);
1107 else
1108 srel += rel->r_addend;
1109 srel += rel->r_addend;
1110 x = bfd_get_32 (input_bfd, contents);
1111 x = (x & 0x80000000) | ((srel >> 31) & 0x7fffffff);
1112 bfd_put_32 (input_bfd, x, contents);
1113 break;
1114
1115 default:
1116 r = _bfd_final_link_relocate (howto, input_bfd, input_section,
1117 contents, rel->r_offset,
1118 relocation, rel->r_addend);
1119 }
1120 else
1121 switch (howto->type)
1122 {
2469cfa2
NC		 1123 case R_MSP430_10_PCREL:
1124 contents += rel->r_offset;
1125 srel = (bfd_signed_vma) relocation;
1126 srel += rel->r_addend;
1127 srel -= rel->r_offset;
1128 srel -= 2; /* Branch instructions add 2 to the PC... */
1129 srel -= (input_section->output_section->vma +
1130 input_section->output_offset);
1131
1132 if (srel & 1)
1133 return bfd_reloc_outofrange;
1134
1135 /* MSP430 addresses commands as words. */
1136 srel >>= 1;
1137
1138 /* Check for an overflow. */
1139 if (srel < -512 || srel > 511)
13761a11
NC		 1140 {
1141 if (info->disable_target_specific_optimizations < 0)
1142 {
1143 static bfd_boolean warned = FALSE;
1144 if (! warned)
1145 {
1146 info->callbacks->warning
1147 (info,
1148 _("Try enabling relaxation to avoid relocation truncations"),
1149 NULL, input_bfd, input_section, relocation);
1150 warned = TRUE;
1151 }
1152 }
1153 return bfd_reloc_overflow;
1154 }
1155
2469cfa2
NC		 1156 x = bfd_get_16 (input_bfd, contents);
1157 x = (x & 0xfc00) | (srel & 0x3ff);
1158 bfd_put_16 (input_bfd, x, contents);
1159 break;
1160
b18c562e
NC		 1161 case R_MSP430_2X_PCREL:
1162 contents += rel->r_offset;
1163 srel = (bfd_signed_vma) relocation;
1164 srel += rel->r_addend;
1165 srel -= rel->r_offset;
1166 srel -= 2; /* Branch instructions add 2 to the PC... */
1167 srel -= (input_section->output_section->vma +
1168 input_section->output_offset);
1169
1170 if (srel & 1)
1171 return bfd_reloc_outofrange;
1172
1173 /* MSP430 addresses commands as words. */
1174 srel >>= 1;
1175
1176 /* Check for an overflow. */
1177 if (srel < -512 || srel > 511)
1178 return bfd_reloc_overflow;
1179
1180 x = bfd_get_16 (input_bfd, contents);
1181 x = (x & 0xfc00) | (srel & 0x3ff);
1182 bfd_put_16 (input_bfd, x, contents);
1183 /* Handle second jump instruction. */
1184 x = bfd_get_16 (input_bfd, contents - 2);
1185 srel += 1;
1186 x = (x & 0xfc00) | (srel & 0x3ff);
1187 bfd_put_16 (input_bfd, x, contents - 2);
1188 break;
1189
b18c562e 1190 case R_MSP430_RL_PCREL:
77bf820f 1191 case R_MSP430_16_PCREL:
2469cfa2
NC		 1192 contents += rel->r_offset;
1193 srel = (bfd_signed_vma) relocation;
1194 srel += rel->r_addend;
1195 srel -= rel->r_offset;
1196 /* Only branch instructions add 2 to the PC... */
1197 srel -= (input_section->output_section->vma +
1198 input_section->output_offset);
1199
1200 if (srel & 1)
1201 return bfd_reloc_outofrange;
1202
1203 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1204 break;
1205
1206 case R_MSP430_16_PCREL_BYTE:
1207 contents += rel->r_offset;
1208 srel = (bfd_signed_vma) relocation;
1209 srel += rel->r_addend;
1210 srel -= rel->r_offset;
1211 /* Only branch instructions add 2 to the PC... */
1212 srel -= (input_section->output_section->vma +
1213 input_section->output_offset);
1214
1215 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1216 break;
1217
1218 case R_MSP430_16_BYTE:
1219 contents += rel->r_offset;
1220 srel = (bfd_signed_vma) relocation;
1221 srel += rel->r_addend;
1222 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1223 break;
1224
1225 case R_MSP430_16:
1226 contents += rel->r_offset;
1227 srel = (bfd_signed_vma) relocation;
1228 srel += rel->r_addend;
1229
1230 if (srel & 1)
1231 return bfd_reloc_notsupported;
1232
1233 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1234 break;
1235
13761a11
NC		 1236 case R_MSP430_8:
1237 contents += rel->r_offset;
1238 srel = (bfd_signed_vma) relocation;
1239 srel += rel->r_addend;
1240
1241 bfd_put_8 (input_bfd, srel & 0xff, contents);
1242 break;
1243
1244 case R_MSP430_SYM_DIFF:
1245 /* Cache the input section and value.
1246 The offset is unreliable, since relaxation may
1247 have reduced the following reloc's offset. */
1248 sym_diff_section = input_section;
1249 sym_diff_value = relocation;
1250 return bfd_reloc_ok;
1251
1252 default:
1253 r = _bfd_final_link_relocate (howto, input_bfd, input_section,
1254 contents, rel->r_offset,
1255 relocation, rel->r_addend);
1256 }
2469cfa2
NC		 1257
1258 return r;
1259}
1260
1261/* Relocate an MSP430 ELF section. */
1262
1263static bfd_boolean
b18c562e
NC		 1264elf32_msp430_relocate_section (bfd * output_bfd ATTRIBUTE_UNUSED,
1265 struct bfd_link_info * info,
1266 bfd * input_bfd,
1267 asection * input_section,
1268 bfd_byte * contents,
1269 Elf_Internal_Rela * relocs,
1270 Elf_Internal_Sym * local_syms,
1271 asection ** local_sections)
2469cfa2
NC		 1272{
1273 Elf_Internal_Shdr *symtab_hdr;
1274 struct elf_link_hash_entry **sym_hashes;
1275 Elf_Internal_Rela *rel;
1276 Elf_Internal_Rela *relend;
1277
1278 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
1279 sym_hashes = elf_sym_hashes (input_bfd);
1280 relend = relocs + input_section->reloc_count;
1281
1282 for (rel = relocs; rel < relend; rel++)
1283 {
1284 reloc_howto_type *howto;
1285 unsigned long r_symndx;
1286 Elf_Internal_Sym *sym;
1287 asection *sec;
1288 struct elf_link_hash_entry *h;
1289 bfd_vma relocation;
1290 bfd_reloc_status_type r;
1291 const char *name = NULL;
1292 int r_type;
1293
2469cfa2
NC		 1294 r_type = ELF32_R_TYPE (rel->r_info);
1295 r_symndx = ELF32_R_SYM (rel->r_info);
13761a11
NC		 1296
1297 if (uses_msp430x_relocs (input_bfd))
1298 howto = elf_msp430x_howto_table + r_type;
1299 else
1300 howto = elf_msp430_howto_table + r_type;
1301
2469cfa2
NC		 1302 h = NULL;
1303 sym = NULL;
1304 sec = NULL;
1305
1306 if (r_symndx < symtab_hdr->sh_info)
1307 {
1308 sym = local_syms + r_symndx;
1309 sec = local_sections[r_symndx];
8517fae7 1310 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
2469cfa2
NC		 1311
1312 name = bfd_elf_string_from_elf_section
1313 (input_bfd, symtab_hdr->sh_link, sym->st_name);
13761a11 1314 name = (name == NULL || * name == 0) ? bfd_section_name (input_bfd, sec) : name;
2469cfa2
NC		 1315 }
1316 else
1317 {
62d887d4 1318 bfd_boolean unresolved_reloc, warned, ignored;
2469cfa2 1319
b2a8e766
AM		 1320 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
1321 r_symndx, symtab_hdr, sym_hashes,
1322 h, sec, relocation,
62d887d4 1323 unresolved_reloc, warned, ignored);
13761a11 1324 name = h->root.root.string;
2469cfa2
NC		 1325 }
1326
dbaa2011 1327 if (sec != NULL && discarded_section (sec))
e4067dbb 1328 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
545fd46b 1329 rel, 1, relend, howto, 0, contents);
ab96bf03
AM		 1330
1331 if (info->relocatable)
1332 continue;
1333
2469cfa2 1334 r = msp430_final_link_relocate (howto, input_bfd, input_section,
13761a11 1335 contents, rel, relocation, info);
2469cfa2
NC		 1336
1337 if (r != bfd_reloc_ok)
1338 {
1339 const char *msg = (const char *) NULL;
1340
1341 switch (r)
1342 {
1343 case bfd_reloc_overflow:
1344 r = info->callbacks->reloc_overflow
13761a11 1345 (info, (h ? &h->root : NULL), name, howto->name,
dfeffb9f
L		 1346 (bfd_vma) 0, input_bfd, input_section,
1347 rel->r_offset);
2469cfa2
NC		 1348 break;
1349
1350 case bfd_reloc_undefined:
1351 r = info->callbacks->undefined_symbol
1352 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
1353 break;
1354
1355 case bfd_reloc_outofrange:
13761a11 1356 msg = _("internal error: branch/jump to an odd address detected");
2469cfa2
NC		 1357 break;
1358
1359 case bfd_reloc_notsupported:
1360 msg = _("internal error: unsupported relocation error");
1361 break;
1362
1363 case bfd_reloc_dangerous:
1364 msg = _("internal error: dangerous relocation");
1365 break;
1366
1367 default:
1368 msg = _("internal error: unknown error");
1369 break;
1370 }
1371
1372 if (msg)
1373 r = info->callbacks->warning
1374 (info, msg, name, input_bfd, input_section, rel->r_offset);
1375
1376 if (!r)
1377 return FALSE;
1378 }
1379
1380 }
1381
1382 return TRUE;
1383}
1384
1385/* The final processing done just before writing out a MSP430 ELF object
1386 file. This gets the MSP430 architecture right based on the machine
1387 number. */
1388
1389static void
b18c562e
NC		 1390bfd_elf_msp430_final_write_processing (bfd * abfd,
1391 bfd_boolean linker ATTRIBUTE_UNUSED)
2469cfa2
NC		 1392{
1393 unsigned long val;
1394
1395 switch (bfd_get_mach (abfd))
1396 {
1397 default:
13761a11
NC		 1398 case bfd_mach_msp110: val = E_MSP430_MACH_MSP430x11x1; break;
1399 case bfd_mach_msp11: val = E_MSP430_MACH_MSP430x11; break;
1400 case bfd_mach_msp12: val = E_MSP430_MACH_MSP430x12; break;
1401 case bfd_mach_msp13: val = E_MSP430_MACH_MSP430x13; break;
1402 case bfd_mach_msp14: val = E_MSP430_MACH_MSP430x14; break;
1403 case bfd_mach_msp15: val = E_MSP430_MACH_MSP430x15; break;
1404 case bfd_mach_msp16: val = E_MSP430_MACH_MSP430x16; break;
1405 case bfd_mach_msp31: val = E_MSP430_MACH_MSP430x31; break;
1406 case bfd_mach_msp32: val = E_MSP430_MACH_MSP430x32; break;
1407 case bfd_mach_msp33: val = E_MSP430_MACH_MSP430x33; break;
1408 case bfd_mach_msp41: val = E_MSP430_MACH_MSP430x41; break;
1409 case bfd_mach_msp42: val = E_MSP430_MACH_MSP430x42; break;
1410 case bfd_mach_msp43: val = E_MSP430_MACH_MSP430x43; break;
1411 case bfd_mach_msp44: val = E_MSP430_MACH_MSP430x44; break;
1412 case bfd_mach_msp20: val = E_MSP430_MACH_MSP430x20; break;
1413 case bfd_mach_msp22: val = E_MSP430_MACH_MSP430x22; break;
1414 case bfd_mach_msp23: val = E_MSP430_MACH_MSP430x23; break;
1415 case bfd_mach_msp24: val = E_MSP430_MACH_MSP430x24; break;
1416 case bfd_mach_msp26: val = E_MSP430_MACH_MSP430x26; break;
1417 case bfd_mach_msp46: val = E_MSP430_MACH_MSP430x46; break;
1418 case bfd_mach_msp47: val = E_MSP430_MACH_MSP430x47; break;
1419 case bfd_mach_msp54: val = E_MSP430_MACH_MSP430x54; break;
1420 case bfd_mach_msp430x: val = E_MSP430_MACH_MSP430X; break;
2469cfa2
NC		 1421 }
1422
1423 elf_elfheader (abfd)->e_machine = EM_MSP430;
1424 elf_elfheader (abfd)->e_flags &= ~EF_MSP430_MACH;
1425 elf_elfheader (abfd)->e_flags |= val;
1426}
1427
1428/* Set the right machine number. */
1429
1430static bfd_boolean
b18c562e 1431elf32_msp430_object_p (bfd * abfd)
2469cfa2
NC		 1432{
1433 int e_set = bfd_mach_msp14;
1434
1435 if (elf_elfheader (abfd)->e_machine == EM_MSP430
1436 || elf_elfheader (abfd)->e_machine == EM_MSP430_OLD)
1437 {
1438 int e_mach = elf_elfheader (abfd)->e_flags & EF_MSP430_MACH;
1439
1440 switch (e_mach)
1441 {
1442 default:
13761a11
NC		 1443 case E_MSP430_MACH_MSP430x11: e_set = bfd_mach_msp11; break;
1444 case E_MSP430_MACH_MSP430x11x1: e_set = bfd_mach_msp110; break;
1445 case E_MSP430_MACH_MSP430x12: e_set = bfd_mach_msp12; break;
1446 case E_MSP430_MACH_MSP430x13: e_set = bfd_mach_msp13; break;
1447 case E_MSP430_MACH_MSP430x14: e_set = bfd_mach_msp14; break;
1448 case E_MSP430_MACH_MSP430x15: e_set = bfd_mach_msp15; break;
1449 case E_MSP430_MACH_MSP430x16: e_set = bfd_mach_msp16; break;
1450 case E_MSP430_MACH_MSP430x31: e_set = bfd_mach_msp31; break;
1451 case E_MSP430_MACH_MSP430x32: e_set = bfd_mach_msp32; break;
1452 case E_MSP430_MACH_MSP430x33: e_set = bfd_mach_msp33; break;
1453 case E_MSP430_MACH_MSP430x41: e_set = bfd_mach_msp41; break;
1454 case E_MSP430_MACH_MSP430x42: e_set = bfd_mach_msp42; break;
1455 case E_MSP430_MACH_MSP430x43: e_set = bfd_mach_msp43; break;
1456 case E_MSP430_MACH_MSP430x44: e_set = bfd_mach_msp44; break;
1457 case E_MSP430_MACH_MSP430x20: e_set = bfd_mach_msp20; break;
1458 case E_MSP430_MACH_MSP430x22: e_set = bfd_mach_msp22; break;
1459 case E_MSP430_MACH_MSP430x23: e_set = bfd_mach_msp23; break;
1460 case E_MSP430_MACH_MSP430x24: e_set = bfd_mach_msp24; break;
1461 case E_MSP430_MACH_MSP430x26: e_set = bfd_mach_msp26; break;
1462 case E_MSP430_MACH_MSP430x46: e_set = bfd_mach_msp46; break;
1463 case E_MSP430_MACH_MSP430x47: e_set = bfd_mach_msp47; break;
1464 case E_MSP430_MACH_MSP430x54: e_set = bfd_mach_msp54; break;
1465 case E_MSP430_MACH_MSP430X: e_set = bfd_mach_msp430x; break;
2469cfa2
NC		 1466 }
1467 }
13761a11 1468
2469cfa2
NC		 1469 return bfd_default_set_arch_mach (abfd, bfd_arch_msp430, e_set);
1470}
1471
b18c562e
NC		 1472/* These functions handle relaxing for the msp430.
1473 Relaxation required only in two cases:
1474 - Bad hand coding like jumps from one section to another or
1475 from file to file.
77bf820f 1476 - Sibling calls. This will affect only 'jump label' polymorph. Without
b18c562e
NC		 1477 relaxing this enlarges code by 2 bytes. Sibcalls implemented but
1478 do not work in gcc's port by the reason I do not know.
13761a11
NC		 1479 - To convert out of range conditional jump instructions (found inside
1480 a function) into inverted jumps over an unconditional branch instruction.
b18c562e
NC		 1481 Anyway, if a relaxation required, user should pass -relax option to the
1482 linker.
1483
1484 There are quite a few relaxing opportunities available on the msp430:
1485
1486 ================================================================
1487
1488 1. 3 words -> 1 word
1489
1490 eq == jeq label jne +4; br lab
1491 ne != jne label jeq +4; br lab
1492 lt < jl label jge +4; br lab
1493 ltu < jlo label lhs +4; br lab
1494 ge >= jge label jl +4; br lab
1495 geu >= jhs label jlo +4; br lab
1496
1497 2. 4 words -> 1 word
1498
1499 ltn < jn jn +2; jmp +4; br lab
1500
1501 3. 4 words -> 2 words
1502
1503 gt > jeq +2; jge label jeq +6; jl +4; br label
1504 gtu > jeq +2; jhs label jeq +6; jlo +4; br label
1505
1506 4. 4 words -> 2 words and 2 labels
1507
1508 leu <= jeq label; jlo label jeq +2; jhs +4; br label
1509 le <= jeq label; jl label jeq +2; jge +4; br label
1510 =================================================================
1511
1512 codemap for first cases is (labels masked ):
1513 eq: 0x2002,0x4010,0x0000 -> 0x2400
1514 ne: 0x2402,0x4010,0x0000 -> 0x2000
1515 lt: 0x3402,0x4010,0x0000 -> 0x3800
1516 ltu: 0x2c02,0x4010,0x0000 -> 0x2800
1517 ge: 0x3802,0x4010,0x0000 -> 0x3400
1518 geu: 0x2802,0x4010,0x0000 -> 0x2c00
1519
1520 second case:
1521 ltn: 0x3001,0x3c02,0x4010,0x0000 -> 0x3000
1522
1523 third case:
1524 gt: 0x2403,0x3802,0x4010,0x0000 -> 0x2401,0x3400
1525 gtu: 0x2403,0x2802,0x4010,0x0000 -> 0x2401,0x2c00
1526
1527 fourth case:
1528 leu: 0x2401,0x2c02,0x4010,0x0000 -> 0x2400,0x2800
1529 le: 0x2401,0x3402,0x4010,0x0000 -> 0x2400,0x3800
1530
1531 Unspecified case :)
1532 jump: 0x4010,0x0000 -> 0x3c00. */
1533
1534#define NUMB_RELAX_CODES 12
1535static struct rcodes_s
1536{
1537 int f0, f1; /* From code. */
1538 int t0, t1; /* To code. */
1539 int labels; /* Position of labels: 1 - one label at first
1540 word, 2 - one at second word, 3 - two
1541 labels at both. */
1542 int cdx; /* Words to match. */
1543 int bs; /* Shrink bytes. */
1544 int off; /* Offset from old label for new code. */
1545 int ncl; /* New code length. */
1546} rcode[] =
1547{/* lab,cdx,bs,off,ncl */
1548 { 0x0000, 0x0000, 0x3c00, 0x0000, 1, 0, 2, 2, 2}, /* jump */
1549 { 0x0000, 0x2002, 0x2400, 0x0000, 1, 1, 4, 4, 2}, /* eq */
1550 { 0x0000, 0x2402, 0x2000, 0x0000, 1, 1, 4, 4, 2}, /* ne */
1551 { 0x0000, 0x3402, 0x3800, 0x0000, 1, 1, 4, 4, 2}, /* lt */
1552 { 0x0000, 0x2c02, 0x2800, 0x0000, 1, 1, 4, 4, 2}, /* ltu */
1553 { 0x0000, 0x3802, 0x3400, 0x0000, 1, 1, 4, 4, 2}, /* ge */
1554 { 0x0000, 0x2802, 0x2c00, 0x0000, 1, 1, 4, 4, 2}, /* geu */
1555 { 0x3001, 0x3c02, 0x3000, 0x0000, 1, 2, 6, 6, 2}, /* ltn */
1556 { 0x2403, 0x3802, 0x2401, 0x3400, 2, 2, 4, 6, 4}, /* gt */
1557 { 0x2403, 0x2802, 0x2401, 0x2c00, 2, 2, 4, 6, 4}, /* gtu */
1558 { 0x2401, 0x2c02, 0x2400, 0x2800, 3, 2, 4, 6, 4}, /* leu , 2 labels */
1559 { 0x2401, 0x2c02, 0x2400, 0x2800, 3, 2, 4, 6, 4}, /* le , 2 labels */
1560 { 0, 0, 0, 0, 0, 0, 0, 0, 0}
1561};
1562
1563/* Return TRUE if a symbol exists at the given address. */
1564
1565static bfd_boolean
1566msp430_elf_symbol_address_p (bfd * abfd,
1567 asection * sec,
1568 Elf_Internal_Sym * isym,
1569 bfd_vma addr)
1570{
1571 Elf_Internal_Shdr *symtab_hdr;
1572 unsigned int sec_shndx;
1573 Elf_Internal_Sym *isymend;
1574 struct elf_link_hash_entry **sym_hashes;
1575 struct elf_link_hash_entry **end_hashes;
1576 unsigned int symcount;
1577
1578 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1579
1580 /* Examine all the local symbols. */
1581 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
1582 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++)
1583 if (isym->st_shndx == sec_shndx && isym->st_value == addr)
1584 return TRUE;
1585
1586 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1587 - symtab_hdr->sh_info);
1588 sym_hashes = elf_sym_hashes (abfd);
1589 end_hashes = sym_hashes + symcount;
1590 for (; sym_hashes < end_hashes; sym_hashes++)
1591 {
1592 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1593
1594 if ((sym_hash->root.type == bfd_link_hash_defined
1595 || sym_hash->root.type == bfd_link_hash_defweak)
1596 && sym_hash->root.u.def.section == sec
1597 && sym_hash->root.u.def.value == addr)
1598 return TRUE;
1599 }
1600
1601 return FALSE;
1602}
1603
13761a11
NC		 1604/* Adjust all local symbols defined as '.section + 0xXXXX' (.section has
1605 sec_shndx) referenced from current and other sections. */
1606
046aeb74 1607static bfd_boolean
13761a11
NC		 1608msp430_elf_relax_adjust_locals (bfd * abfd, asection * sec, bfd_vma addr,
1609 int count, unsigned int sec_shndx,
1610 bfd_vma toaddr)
046aeb74
DD		 1611{
1612 Elf_Internal_Shdr *symtab_hdr;
1613 Elf_Internal_Rela *irel;
1614 Elf_Internal_Rela *irelend;
1615 Elf_Internal_Sym *isym;
1616
1617 irel = elf_section_data (sec)->relocs;
13761a11
NC		 1618 if (irel == NULL)
1619 return TRUE;
1620
046aeb74
DD		 1621 irelend = irel + sec->reloc_count;
1622 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1623 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
bceec4b9 1624
13761a11 1625 for (;irel < irelend; irel++)
046aeb74 1626 {
bceec4b9 1627 unsigned int sidx = ELF32_R_SYM(irel->r_info);
046aeb74 1628 Elf_Internal_Sym *lsym = isym + sidx;
bceec4b9 1629
1ade7175 1630 /* Adjust symbols referenced by .sec+0xXX. */
bceec4b9
DD		 1631 if (irel->r_addend > addr && irel->r_addend < toaddr
1632 && sidx < symtab_hdr->sh_info
046aeb74
DD		 1633 && lsym->st_shndx == sec_shndx)
1634 irel->r_addend -= count;
1635 }
13761a11 1636
046aeb74
DD		 1637 return TRUE;
1638}
1639
b18c562e
NC		 1640/* Delete some bytes from a section while relaxing. */
1641
1642static bfd_boolean
1643msp430_elf_relax_delete_bytes (bfd * abfd, asection * sec, bfd_vma addr,
1644 int count)
1645{
1646 Elf_Internal_Shdr *symtab_hdr;
1647 unsigned int sec_shndx;
1648 bfd_byte *contents;
1649 Elf_Internal_Rela *irel;
1650 Elf_Internal_Rela *irelend;
b18c562e
NC		 1651 bfd_vma toaddr;
1652 Elf_Internal_Sym *isym;
1653 Elf_Internal_Sym *isymend;
1654 struct elf_link_hash_entry **sym_hashes;
1655 struct elf_link_hash_entry **end_hashes;
1656 unsigned int symcount;
046aeb74 1657 asection *p;
b18c562e
NC		 1658
1659 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1660
1661 contents = elf_section_data (sec)->this_hdr.contents;
1662
b18c562e
NC		 1663 toaddr = sec->size;
1664
1665 irel = elf_section_data (sec)->relocs;
1666 irelend = irel + sec->reloc_count;
1667
1668 /* Actually delete the bytes. */
1669 memmove (contents + addr, contents + addr + count,
1670 (size_t) (toaddr - addr - count));
1671 sec->size -= count;
1672
1673 /* Adjust all the relocs. */
fa9ee72b
DD		 1674 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1675 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
13761a11 1676 for (; irel < irelend; irel++)
fa9ee72b 1677 {
fa9ee72b
DD		 1678 /* Get the new reloc address. */
1679 if ((irel->r_offset > addr && irel->r_offset < toaddr))
1680 irel->r_offset -= count;
fa9ee72b 1681 }
b18c562e 1682
046aeb74 1683 for (p = abfd->sections; p != NULL; p = p->next)
13761a11
NC		 1684 msp430_elf_relax_adjust_locals (abfd,p,addr,count,sec_shndx,toaddr);
1685
b18c562e
NC		 1686 /* Adjust the local symbols defined in this section. */
1687 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1688 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
1689 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++)
0f8f0c57
NC		 1690 {
1691 const char * name;
1692
1693 name = bfd_elf_string_from_elf_section
1694 (abfd, symtab_hdr->sh_link, isym->st_name);
1695 name = (name == NULL || * name == 0) ? bfd_section_name (abfd, sec) : name;
1696
1697 if (isym->st_shndx != sec_shndx)
1698 continue;
1699
1700 if (isym->st_value > addr
1701 && (isym->st_value < toaddr
1702 /* We also adjust a symbol at the end of the section if its name is
1703 on the list below. These symbols are used for debug info
1704 generation and they refer to the end of the current section, not
1705 the start of the next section. */
1706 || (isym->st_value == toaddr
1707 && name != NULL
1708 && (CONST_STRNEQ (name, ".Letext")
1709 || CONST_STRNEQ (name, ".LFE")))))
1710 {
1711 if (isym->st_value < addr + count)
1712 isym->st_value = addr;
1713 else
1714 isym->st_value -= count;
1715 }
1716 /* Adjust the function symbol's size as well. */
1717 else if (ELF_ST_TYPE (isym->st_info) == STT_FUNC
1718 && isym->st_value + isym->st_size > addr
1719 && isym->st_value + isym->st_size < toaddr)
1720 isym->st_size -= count;
1721 }
b18c562e
NC		 1722
1723 /* Now adjust the global symbols defined in this section. */
1724 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1725 - symtab_hdr->sh_info);
1726 sym_hashes = elf_sym_hashes (abfd);
1727 end_hashes = sym_hashes + symcount;
1728 for (; sym_hashes < end_hashes; sym_hashes++)
1729 {
1730 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1731
1732 if ((sym_hash->root.type == bfd_link_hash_defined
1733 || sym_hash->root.type == bfd_link_hash_defweak)
1734 && sym_hash->root.u.def.section == sec
1735 && sym_hash->root.u.def.value > addr
1736 && sym_hash->root.u.def.value < toaddr)
0f8f0c57
NC		 1737 {
1738 if (sym_hash->root.u.def.value < addr + count)
1739 sym_hash->root.u.def.value = addr;
1740 else
1741 sym_hash->root.u.def.value -= count;
1742 }
1743 /* Adjust the function symbol's size as well. */
1744 else if (sym_hash->root.type == bfd_link_hash_defined
1745 && sym_hash->root.u.def.section == sec
1746 && sym_hash->type == STT_FUNC
1747 && sym_hash->root.u.def.value + sym_hash->size > addr
1748 && sym_hash->root.u.def.value + sym_hash->size < toaddr)
1749 sym_hash->size -= count;
b18c562e
NC		 1750 }
1751
1752 return TRUE;
1753}
1754
13761a11
NC		 1755/* Insert two words into a section whilst relaxing. */
1756
1757static bfd_byte *
1758msp430_elf_relax_add_two_words (bfd * abfd, asection * sec, bfd_vma addr,
1759 int word1, int word2)
1760{
1761 Elf_Internal_Shdr *symtab_hdr;
1762 unsigned int sec_shndx;
1763 bfd_byte *contents;
1764 Elf_Internal_Rela *irel;
1765 Elf_Internal_Rela *irelend;
1766 Elf_Internal_Sym *isym;
1767 Elf_Internal_Sym *isymend;
1768 struct elf_link_hash_entry **sym_hashes;
1769 struct elf_link_hash_entry **end_hashes;
1770 unsigned int symcount;
1771 bfd_vma sec_end;
1772 asection *p;
1773
1774 contents = elf_section_data (sec)->this_hdr.contents;
1775 sec_end = sec->size;
1776
1777 /* Make space for the new words. */
1778 contents = bfd_realloc (contents, sec_end + 4);
1779 memmove (contents + addr + 4, contents + addr, sec_end - addr);
1780
1781 /* Insert the new words. */
1782 bfd_put_16 (abfd, word1, contents + addr);
1783 bfd_put_16 (abfd, word2, contents + addr + 2);
1784
1785 /* Update the section information. */
1786 sec->size += 4;
1787 elf_section_data (sec)->this_hdr.contents = contents;
1788
1789 /* Adjust all the relocs. */
1790 irel = elf_section_data (sec)->relocs;
1791 irelend = irel + sec->reloc_count;
1792
1793 for (; irel < irelend; irel++)
1794 if ((irel->r_offset >= addr && irel->r_offset < sec_end))
1795 irel->r_offset += 4;
1796
1797 /* Adjust the local symbols defined in this section. */
1798 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1799 for (p = abfd->sections; p != NULL; p = p->next)
1800 msp430_elf_relax_adjust_locals (abfd, p, addr, -4,
1801 sec_shndx, sec_end);
1802
1803 /* Adjust the global symbols affected by the move. */
1804 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1805 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
1806 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++)
1807 if (isym->st_shndx == sec_shndx
1808 && isym->st_value >= addr && isym->st_value < sec_end)
1809 isym->st_value += 4;
1810
1811 /* Now adjust the global symbols defined in this section. */
1812 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1813 - symtab_hdr->sh_info);
1814 sym_hashes = elf_sym_hashes (abfd);
1815 end_hashes = sym_hashes + symcount;
1816 for (; sym_hashes < end_hashes; sym_hashes++)
1817 {
1818 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1819
1820 if ((sym_hash->root.type == bfd_link_hash_defined
1821 || sym_hash->root.type == bfd_link_hash_defweak)
1822 && sym_hash->root.u.def.section == sec
1823 && sym_hash->root.u.def.value >= addr
1824 && sym_hash->root.u.def.value < sec_end)
1825 sym_hash->root.u.def.value += 4;
1826 }
1827
1828 return contents;
1829}
1830
b18c562e
NC		 1831static bfd_boolean
1832msp430_elf_relax_section (bfd * abfd, asection * sec,
1833 struct bfd_link_info * link_info,
1834 bfd_boolean * again)
1835{
1836 Elf_Internal_Shdr * symtab_hdr;
1837 Elf_Internal_Rela * internal_relocs;
1838 Elf_Internal_Rela * irel;
1839 Elf_Internal_Rela * irelend;
1840 bfd_byte * contents = NULL;
1841 Elf_Internal_Sym * isymbuf = NULL;
1842
1843 /* Assume nothing changes. */
1844 *again = FALSE;
1845
1846 /* We don't have to do anything for a relocatable link, if
1847 this section does not have relocs, or if this is not a
1848 code section. */
1849 if (link_info->relocatable
13761a11
NC		 1850 || (sec->flags & SEC_RELOC) == 0
1851 || sec->reloc_count == 0 || (sec->flags & SEC_CODE) == 0)
b18c562e
NC		 1852 return TRUE;
1853
1854 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1855
1856 /* Get a copy of the native relocations. */
1857 internal_relocs =
1858 _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, link_info->keep_memory);
1859 if (internal_relocs == NULL)
1860 goto error_return;
1861
1862 /* Walk through them looking for relaxing opportunities. */
1863 irelend = internal_relocs + sec->reloc_count;
13761a11
NC		 1864
1865 /* Do code size growing relocs first. */
b18c562e
NC		 1866 for (irel = internal_relocs; irel < irelend; irel++)
1867 {
1868 bfd_vma symval;
1869
1870 /* If this isn't something that can be relaxed, then ignore
1871 this reloc. */
13761a11
NC		 1872 if (uses_msp430x_relocs (abfd)
1873 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430X_10_PCREL)
1874 ;
1875 else if (! uses_msp430x_relocs (abfd)
1876 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430_10_PCREL)
1877 ;
1878 else
b18c562e
NC		 1879 continue;
1880
1881 /* Get the section contents if we haven't done so already. */
1882 if (contents == NULL)
1883 {
1884 /* Get cached copy if it exists. */
1885 if (elf_section_data (sec)->this_hdr.contents != NULL)
1886 contents = elf_section_data (sec)->this_hdr.contents;
1887 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
1888 goto error_return;
1889 }
1890
1891 /* Read this BFD's local symbols if we haven't done so already. */
1892 if (isymbuf == NULL && symtab_hdr->sh_info != 0)
1893 {
1894 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
1895 if (isymbuf == NULL)
1896 isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
1897 symtab_hdr->sh_info, 0,
1898 NULL, NULL, NULL);
1899 if (isymbuf == NULL)
1900 goto error_return;
1901 }
1902
1903 /* Get the value of the symbol referred to by the reloc. */
1904 if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info)
1905 {
1906 /* A local symbol. */
1907 Elf_Internal_Sym *isym;
1908 asection *sym_sec;
1909
1910 isym = isymbuf + ELF32_R_SYM (irel->r_info);
1911 if (isym->st_shndx == SHN_UNDEF)
1912 sym_sec = bfd_und_section_ptr;
1913 else if (isym->st_shndx == SHN_ABS)
1914 sym_sec = bfd_abs_section_ptr;
1915 else if (isym->st_shndx == SHN_COMMON)
1916 sym_sec = bfd_com_section_ptr;
1917 else
1918 sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
1919 symval = (isym->st_value
1920 + sym_sec->output_section->vma + sym_sec->output_offset);
1921 }
1922 else
1923 {
1924 unsigned long indx;
1925 struct elf_link_hash_entry *h;
1926
1927 /* An external symbol. */
1928 indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info;
1929 h = elf_sym_hashes (abfd)[indx];
1930 BFD_ASSERT (h != NULL);
1931
1932 if (h->root.type != bfd_link_hash_defined
1933 && h->root.type != bfd_link_hash_defweak)
1934 /* This appears to be a reference to an undefined
1935 symbol. Just ignore it--it will be caught by the
1936 regular reloc processing. */
1937 continue;
1938
1939 symval = (h->root.u.def.value
1940 + h->root.u.def.section->output_section->vma
1941 + h->root.u.def.section->output_offset);
1942 }
1943
1944 /* For simplicity of coding, we are going to modify the section
1945 contents, the section relocs, and the BFD symbol table. We
1946 must tell the rest of the code not to free up this
1947 information. It would be possible to instead create a table
1948 of changes which have to be made, as is done in coff-mips.c;
1949 that would be more work, but would require less memory when
1950 the linker is run. */
1951
13761a11
NC		 1952 bfd_signed_vma value = symval;
1953 int opcode;
b18c562e 1954
13761a11
NC		 1955 /* Compute the value that will be relocated. */
1956 value += irel->r_addend;
1957 /* Convert to PC relative. */
1958 value -= (sec->output_section->vma + sec->output_offset);
1959 value -= irel->r_offset;
1960 value -= 2;
1961 /* Scale. */
1962 value >>= 1;
b18c562e 1963
13761a11
NC		 1964 /* If it is in range then no modifications are needed. */
1965 if (value >= -512 && value <= 511)
1966 continue;
b18c562e 1967
13761a11
NC		 1968 /* Get the opcode. */
1969 opcode = bfd_get_16 (abfd, contents + irel->r_offset);
1970
1971 /* Compute the new opcode. We are going to convert:
1972 J<cond> label
1973 into:
1974 J<inv-cond> 1f
1975 BR[A] #label
1976 1: */
1977 switch (opcode & 0xfc00)
1978 {
1979 case 0x3800: opcode = 0x3402; break; /* Jl -> Jge +2 */
1980 case 0x3400: opcode = 0x3802; break; /* Jge -> Jl +2 */
1981 case 0x2c00: opcode = 0x2802; break; /* Jhs -> Jlo +2 */
1982 case 0x2800: opcode = 0x2c02; break; /* Jlo -> Jhs +2 */
1983 case 0x2400: opcode = 0x2002; break; /* Jeq -> Jne +2 */
1984 case 0x2000: opcode = 0x2402; break; /* jne -> Jeq +2 */
1985 case 0x3000: /* jn */
1986 /* There is no direct inverse of the Jn insn.
1987 FIXME: we could do this as:
1988 Jn 1f
1989 br 2f
1990 1: br label
1991 2: */
1992 continue;
1993 default:
1994 /* Not a conditional branch instruction. */
1995 /* fprintf (stderr, "unrecog: %x\n", opcode); */
2d071cfc 1996 continue;
13761a11 1997 }
b18c562e 1998
13761a11
NC		 1999 /* Note that we've changed the relocs, section contents, etc. */
2000 elf_section_data (sec)->relocs = internal_relocs;
2001 elf_section_data (sec)->this_hdr.contents = contents;
2002 symtab_hdr->contents = (unsigned char *) isymbuf;
b18c562e 2003
13761a11
NC		 2004 /* Install the new opcode. */
2005 bfd_put_16 (abfd, opcode, contents + irel->r_offset);
b18c562e 2006
13761a11
NC		 2007 /* Insert the new branch instruction. */
2008 if (uses_msp430x_relocs (abfd))
2009 {
2010 /* Insert an absolute branch (aka MOVA) instruction. */
2011 contents = msp430_elf_relax_add_two_words
2012 (abfd, sec, irel->r_offset + 2, 0x0080, 0x0000);
2013
2014 /* Update the relocation to point to the inserted branch
2015 instruction. Note - we are changing a PC-relative reloc
2016 into an absolute reloc, but this is OK because we have
2017 arranged with the assembler to have the reloc's value be
2018 a (local) symbol, not a section+offset value. */
2019 irel->r_offset += 2;
2020 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2021 R_MSP430X_ABS20_ADR_SRC);
2022 }
2023 else
2024 {
2025 contents = msp430_elf_relax_add_two_words
2026 (abfd, sec, irel->r_offset + 2, 0x4030, 0x0000);
2027
2028 /* See comment above about converting a 10-bit PC-rel
2029 relocation into a 16-bit absolute relocation. */
2030 irel->r_offset += 4;
2031 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2032 R_MSP430_16);
2033 }
b18c562e 2034
13761a11
NC		 2035 /* Growing the section may mean that other
2036 conditional branches need to be fixed. */
2037 *again = TRUE;
2038 }
b18c562e 2039
13761a11
NC		 2040 for (irel = internal_relocs; irel < irelend; irel++)
2041 {
2042 bfd_vma symval;
2043
2044 /* Get the section contents if we haven't done so already. */
2045 if (contents == NULL)
2046 {
2047 /* Get cached copy if it exists. */
2048 if (elf_section_data (sec)->this_hdr.contents != NULL)
2049 contents = elf_section_data (sec)->this_hdr.contents;
2050 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
2051 goto error_return;
2052 }
2053
2054 /* Read this BFD's local symbols if we haven't done so already. */
2055 if (isymbuf == NULL && symtab_hdr->sh_info != 0)
2056 {
2057 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
2058 if (isymbuf == NULL)
2059 isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
2060 symtab_hdr->sh_info, 0,
2061 NULL, NULL, NULL);
2062 if (isymbuf == NULL)
2063 goto error_return;
2064 }
2065
2066 /* Get the value of the symbol referred to by the reloc. */
2067 if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info)
2068 {
2069 /* A local symbol. */
2070 Elf_Internal_Sym *isym;
2071 asection *sym_sec;
2072
2073 isym = isymbuf + ELF32_R_SYM (irel->r_info);
2074 if (isym->st_shndx == SHN_UNDEF)
2075 sym_sec = bfd_und_section_ptr;
2076 else if (isym->st_shndx == SHN_ABS)
2077 sym_sec = bfd_abs_section_ptr;
2078 else if (isym->st_shndx == SHN_COMMON)
2079 sym_sec = bfd_com_section_ptr;
2080 else
2081 sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
2082 symval = (isym->st_value
2083 + sym_sec->output_section->vma + sym_sec->output_offset);
2084 }
2085 else
2086 {
2087 unsigned long indx;
2088 struct elf_link_hash_entry *h;
2089
2090 /* An external symbol. */
2091 indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info;
2092 h = elf_sym_hashes (abfd)[indx];
2093 BFD_ASSERT (h != NULL);
2094
2095 if (h->root.type != bfd_link_hash_defined
2096 && h->root.type != bfd_link_hash_defweak)
2097 /* This appears to be a reference to an undefined
2098 symbol. Just ignore it--it will be caught by the
2099 regular reloc processing. */
2100 continue;
2101
2102 symval = (h->root.u.def.value
2103 + h->root.u.def.section->output_section->vma
2104 + h->root.u.def.section->output_offset);
2105 }
2106
2107 /* For simplicity of coding, we are going to modify the section
2108 contents, the section relocs, and the BFD symbol table. We
2109 must tell the rest of the code not to free up this
2110 information. It would be possible to instead create a table
2111 of changes which have to be made, as is done in coff-mips.c;
2112 that would be more work, but would require less memory when
2113 the linker is run. */
2114
2115 /* Try to turn a 16bit pc-relative branch into a 10bit pc-relative
2116 branch. */
2117 /* Paranoia? paranoia... */
23d4663e
NC		 2118 if (! uses_msp430x_relocs (abfd)
2119 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430_RL_PCREL)
13761a11
NC		 2120 {
2121 bfd_vma value = symval;
2122
2123 /* Deal with pc-relative gunk. */
2124 value -= (sec->output_section->vma + sec->output_offset);
2125 value -= irel->r_offset;
2126 value += irel->r_addend;
2127
2128 /* See if the value will fit in 10 bits, note the high value is
2129 1016 as the target will be two bytes closer if we are
2130 able to relax. */
2131 if ((long) value < 1016 && (long) value > -1016)
2132 {
2133 int code0 = 0, code1 = 0, code2 = 0;
2134 int i;
2135 struct rcodes_s *rx;
2136
2137 /* Get the opcode. */
2138 if (irel->r_offset >= 6)
2139 code0 = bfd_get_16 (abfd, contents + irel->r_offset - 6);
2140
2141 if (irel->r_offset >= 4)
2142 code1 = bfd_get_16 (abfd, contents + irel->r_offset - 4);
2143
2144 code2 = bfd_get_16 (abfd, contents + irel->r_offset - 2);
2145
2146 if (code2 != 0x4010)
2147 continue;
2148
2149 /* Check r4 and r3. */
2150 for (i = NUMB_RELAX_CODES - 1; i >= 0; i--)
2151 {
2152 rx = &rcode[i];
2153 if (rx->cdx == 2 && rx->f0 == code0 && rx->f1 == code1)
2154 break;
2155 else if (rx->cdx == 1 && rx->f1 == code1)
2156 break;
2157 else if (rx->cdx == 0) /* This is an unconditional jump. */
2158 break;
2159 }
2160
2161 /* Check labels:
b18c562e 2162 .Label0: ; we do not care about this label
13761a11 2163 jeq +6
b18c562e 2164 .Label1: ; make sure there is no label here
13761a11 2165 jl +4
b18c562e 2166 .Label2: ; make sure there is no label here
13761a11
NC		 2167 br .Label_dst
2168
2169 So, if there is .Label1 or .Label2 we cannot relax this code.
2170 This actually should not happen, cause for relaxable
2171 instructions we use RL_PCREL reloc instead of 16_PCREL.
2172 Will change this in the future. */
2173
2174 if (rx->cdx > 0
2175 && msp430_elf_symbol_address_p (abfd, sec, isymbuf,
2176 irel->r_offset - 2))
2177 continue;
2178 if (rx->cdx > 1
2179 && msp430_elf_symbol_address_p (abfd, sec, isymbuf,
2180 irel->r_offset - 4))
2181 continue;
2182
2183 /* Note that we've changed the relocs, section contents, etc. */
2184 elf_section_data (sec)->relocs = internal_relocs;
2185 elf_section_data (sec)->this_hdr.contents = contents;
2186 symtab_hdr->contents = (unsigned char *) isymbuf;
2187
2188 /* Fix the relocation's type. */
2189 if (uses_msp430x_relocs (abfd))
2190 {
2191 if (rx->labels == 3) /* Handle special cases. */
2192 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2193 R_MSP430X_2X_PCREL);
2194 else
2195 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2196 R_MSP430X_10_PCREL);
2197 }
2198 else
2199 {
2200 if (rx->labels == 3) /* Handle special cases. */
2201 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2202 R_MSP430_2X_PCREL);
2203 else
2204 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2205 R_MSP430_10_PCREL);
2206 }
2207
2208 /* Fix the opcode right way. */
2209 bfd_put_16 (abfd, rx->t0, contents + irel->r_offset - rx->off);
2210 if (rx->t1)
2211 bfd_put_16 (abfd, rx->t1,
2212 contents + irel->r_offset - rx->off + 2);
2213
2214 /* Delete bytes. */
2215 if (!msp430_elf_relax_delete_bytes (abfd, sec,
2216 irel->r_offset - rx->off +
2217 rx->ncl, rx->bs))
2218 goto error_return;
2219
2220 /* Handle unconditional jumps. */
2221 if (rx->cdx == 0)
2222 irel->r_offset -= 2;
2223
2224 /* That will change things, so, we should relax again.
2225 Note that this is not required, and it may be slow. */
2226 *again = TRUE;
2227 }
2228 }
23d4663e
NC		 2229
2230 /* Try to turn a 16-bit absolute branch into a 10-bit pc-relative
2231 branch. */
2232 if (uses_msp430x_relocs (abfd)
2233 && ELF32_R_TYPE (irel->r_info) == R_MSP430X_ABS16)
2234 {
2235 bfd_vma value = symval;
2236
2d071cfc 2237 value -= (sec->output_section->vma + sec->output_offset);
23d4663e
NC		 2238 value -= irel->r_offset;
2239 value += irel->r_addend;
2240
2241 /* See if the value will fit in 10 bits, note the high value is
2242 1016 as the target will be two bytes closer if we are
2243 able to relax. */
2244 if ((long) value < 1016 && (long) value > -1016)
2245 {
2246 int code2;
2247
2248 /* Get the opcode. */
2249 code2 = bfd_get_16 (abfd, contents + irel->r_offset - 2);
2250 if (code2 != 0x4030)
2251 continue;
2252 /* FIXME: check r4 and r3 ? */
2253 /* FIXME: Handle 0x4010 as well ? */
2254
2255 /* Note that we've changed the relocs, section contents, etc. */
2256 elf_section_data (sec)->relocs = internal_relocs;
2257 elf_section_data (sec)->this_hdr.contents = contents;
2258 symtab_hdr->contents = (unsigned char *) isymbuf;
2259
2260 /* Fix the relocation's type. */
2261 if (uses_msp430x_relocs (abfd))
2262 {
2263 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2264 R_MSP430X_10_PCREL);
2265 }
2266 else
2267 {
2268 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2269 R_MSP430_10_PCREL);
2270 }
2271
2272 /* Fix the opcode right way. */
2273 bfd_put_16 (abfd, 0x3c00, contents + irel->r_offset - 2);
2274 irel->r_offset -= 2;
2275
2276 /* Delete bytes. */
2277 if (!msp430_elf_relax_delete_bytes (abfd, sec,
2278 irel->r_offset + 2, 2))
2279 goto error_return;
2280
2281 /* That will change things, so, we should relax again.
2282 Note that this is not required, and it may be slow. */
2283 *again = TRUE;
2284 }
2285 }
13761a11 2286 }
b18c562e
NC		 2287
2288 if (isymbuf != NULL && symtab_hdr->contents != (unsigned char *) isymbuf)
2289 {
2290 if (!link_info->keep_memory)
2291 free (isymbuf);
2292 else
2293 {
2294 /* Cache the symbols for elf_link_input_bfd. */
2295 symtab_hdr->contents = (unsigned char *) isymbuf;
2296 }
2297 }
2298
2299 if (contents != NULL
2300 && elf_section_data (sec)->this_hdr.contents != contents)
2301 {
2302 if (!link_info->keep_memory)
2303 free (contents);
2304 else
2305 {
2306 /* Cache the section contents for elf_link_input_bfd. */
2307 elf_section_data (sec)->this_hdr.contents = contents;
2308 }
2309 }
2310
2311 if (internal_relocs != NULL
2312 && elf_section_data (sec)->relocs != internal_relocs)
2313 free (internal_relocs);
2314
2315 return TRUE;
2316
2317error_return:
2318 if (isymbuf != NULL && symtab_hdr->contents != (unsigned char *) isymbuf)
2319 free (isymbuf);
2320 if (contents != NULL
2321 && elf_section_data (sec)->this_hdr.contents != contents)
2322 free (contents);
2323 if (internal_relocs != NULL
2324 && elf_section_data (sec)->relocs != internal_relocs)
2325 free (internal_relocs);
2326
2327 return FALSE;
2328}
2329
13761a11
NC		 2330/* Handle an MSP430 specific section when reading an object file.
2331 This is called when bfd_section_from_shdr finds a section with
2332 an unknown type. */
2333
2334static bfd_boolean
2335elf32_msp430_section_from_shdr (bfd *abfd,
2336 Elf_Internal_Shdr * hdr,
2337 const char *name,
2338 int shindex)
2339{
2340 switch (hdr->sh_type)
2341 {
2342 case SHT_MSP430_SEC_FLAGS:
2343 case SHT_MSP430_SYM_ALIASES:
2344 case SHT_MSP430_ATTRIBUTES:
2345 return _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex);
2346 default:
2347 return FALSE;
2348 }
2349}
2350
2351static bfd_boolean
2352elf32_msp430_obj_attrs_handle_unknown (bfd *abfd, int tag)
2353{
2354 _bfd_error_handler
2355 (_("Warning: %B: Unknown MSPABI object attribute %d"),
2356 abfd, tag);
2357 return TRUE;
2358}
2359
2360/* Determine whether an object attribute tag takes an integer, a
2361 string or both. */
2362
2363static int
2364elf32_msp430_obj_attrs_arg_type (int tag)
2365{
2366 if (tag == Tag_compatibility)
2367 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2368
2369 if (tag < 32)
2370 return ATTR_TYPE_FLAG_INT_VAL;
2371
2372 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
2373}
2374
2375static inline const char *
2376isa_type (int isa)
2377{
2378 switch (isa)
2379 {
2380 case 1: return "MSP430";
2381 case 2: return "MSP430X";
2382 default: return "unknown";
2383 }
2384}
2385
2386static inline const char *
2387code_model (int model)
2388{
2389 switch (model)
2390 {
2391 case 1: return "small";
2392 case 2: return "large";
2393 default: return "unknown";
2394 }
2395}
2396
2397static inline const char *
2398data_model (int model)
2399{
2400 switch (model)
2401 {
2402 case 1: return "small";
2403 case 2: return "large";
2404 case 3: return "restricted large";
2405 default: return "unknown";
2406 }
2407}
2408
2409/* Merge MSPABI object attributes from IBFD into OBFD.
2410 Raise an error if there are conflicting attributes. */
2411
2412static bfd_boolean
2413elf32_msp430_merge_mspabi_attributes (bfd *ibfd, bfd *obfd)
2414{
2415 obj_attribute *in_attr;
2416 obj_attribute *out_attr;
2417 bfd_boolean result = TRUE;
2418 static bfd * first_input_bfd = NULL;
2419
2420 /* Skip linker created files. */
2421 if (ibfd->flags & BFD_LINKER_CREATED)
2422 return TRUE;
2423
2424 /* If this is the first real object just copy the attributes. */
2425 if (!elf_known_obj_attributes_proc (obfd)[0].i)
2426 {
2427 _bfd_elf_copy_obj_attributes (ibfd, obfd);
2428
2429 out_attr = elf_known_obj_attributes_proc (obfd);
2430
2431 /* Use the Tag_null value to indicate that
2432 the attributes have been initialized. */
2433 out_attr[0].i = 1;
2434
2435 first_input_bfd = ibfd;
2436 return TRUE;
2437 }
2438
2439 in_attr = elf_known_obj_attributes_proc (ibfd);
2440 out_attr = elf_known_obj_attributes_proc (obfd);
2441
2442 /* The ISAs must be the same. */
2443 if (in_attr[OFBA_MSPABI_Tag_ISA].i != out_attr[OFBA_MSPABI_Tag_ISA].i)
2444 {
2445 _bfd_error_handler
2446 (_("error: %B uses %s instructions but %B uses %s"),
2447 ibfd, first_input_bfd,
2448 isa_type (in_attr[OFBA_MSPABI_Tag_ISA].i),
2449 isa_type (out_attr[OFBA_MSPABI_Tag_ISA].i));
2450 result = FALSE;
2451 }
2452
2453 /* The code models must be the same. */
2454 if (in_attr[OFBA_MSPABI_Tag_Code_Model].i !=
2455 out_attr[OFBA_MSPABI_Tag_Code_Model].i)
2456 {
2457 _bfd_error_handler
2458 (_("error: %B uses the %s code model whereas %B uses the %s code model"),
2459 ibfd, first_input_bfd,
2460 code_model (in_attr[OFBA_MSPABI_Tag_Code_Model].i),
2461 code_model (out_attr[OFBA_MSPABI_Tag_Code_Model].i));
2462 result = FALSE;
2463 }
2464
2465 /* The large code model is only supported by the MSP430X. */
2466 if (in_attr[OFBA_MSPABI_Tag_Code_Model].i == 2
2467 && out_attr[OFBA_MSPABI_Tag_ISA].i != 2)
2468 {
2469 _bfd_error_handler
2470 (_("error: %B uses the large code model but %B uses MSP430 instructions"),
2471 ibfd, first_input_bfd);
2472 result = FALSE;
2473 }
2474
2475 /* The data models must be the same. */
2476 if (in_attr[OFBA_MSPABI_Tag_Data_Model].i !=
2477 out_attr[OFBA_MSPABI_Tag_Data_Model].i)
2478 {
2479 _bfd_error_handler
2480 (_("error: %B uses the %s data model whereas %B uses the %s data model"),
2481 ibfd, first_input_bfd,
2482 data_model (in_attr[OFBA_MSPABI_Tag_Data_Model].i),
2483 data_model (out_attr[OFBA_MSPABI_Tag_Data_Model].i));
2484 result = FALSE;
2485 }
2486
2487 /* The small code model requires the use of the small data model. */
2488 if (in_attr[OFBA_MSPABI_Tag_Code_Model].i == 1
2489 && out_attr[OFBA_MSPABI_Tag_Data_Model].i != 1)
2490 {
2491 _bfd_error_handler
2492 (_("error: %B uses the small code model but %B uses the %s data model"),
2493 ibfd, first_input_bfd,
2494 data_model (out_attr[OFBA_MSPABI_Tag_Data_Model].i));
2495 result = FALSE;
2496 }
2497
2498 /* The large data models are only supported by the MSP430X. */
2499 if (in_attr[OFBA_MSPABI_Tag_Data_Model].i > 1
2500 && out_attr[OFBA_MSPABI_Tag_ISA].i != 2)
2501 {
2502 _bfd_error_handler
2503 (_("error: %B uses the %s data model but %B only uses MSP430 instructions"),
2504 ibfd, first_input_bfd,
2505 data_model (in_attr[OFBA_MSPABI_Tag_Data_Model].i));
2506 result = FALSE;
2507 }
2508
2509 return result;
2510}
2511
2512/* Merge backend specific data from an object file to the output
2513 object file when linking. */
2514
2515static bfd_boolean
2516elf32_msp430_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
2517{
2518 /* Make sure that the machine number reflects the most
2519 advanced version of the MSP architecture required. */
2520#define max(a,b) ((a) > (b) ? (a) : (b))
2521 if (bfd_get_mach (ibfd) != bfd_get_mach (obfd))
2522 bfd_default_set_arch_mach (obfd, bfd_get_arch (obfd),
2523 max (bfd_get_mach (ibfd), bfd_get_mach (obfd)));
2524#undef max
2525
2526 return elf32_msp430_merge_mspabi_attributes (ibfd, obfd);
2527}
2528
13761a11
NC		 2529static bfd_boolean
2530msp430_elf_is_target_special_symbol (bfd *abfd, asymbol *sym)
2531{
2532 return _bfd_elf_is_local_label_name (abfd, sym->name);
2533}
2534
2535/* This is gross. The MSP430 EABI says that (sec 11.5):
2536
2537 "An implementation may choose to use Rel or Rela
2538 type relocations for other relocations."
2539
2540 But it also says that:
2541
2542 "Certain relocations are identified as Rela only. [snip]
2543 Where Rela is specified, an implementation must honor
2544 this requirement."
2545
2546 There is one relocation marked as requiring RELA - R_MSP430_ABS_HI16 - but
2547 to keep things simple we choose to use RELA relocations throughout. The
2548 problem is that the TI compiler generates REL relocations, so we have to
2549 be able to accept those as well. */
2550
2551#define elf_backend_may_use_rel_p 1
2552#define elf_backend_may_use_rela_p 1
2553#define elf_backend_default_use_rela_p 1
2554
2555#undef elf_backend_obj_attrs_vendor
2556#define elf_backend_obj_attrs_vendor "mspabi"
2557#undef elf_backend_obj_attrs_section
2558#define elf_backend_obj_attrs_section ".MSP430.attributes"
2559#undef elf_backend_obj_attrs_section_type
2560#define elf_backend_obj_attrs_section_type SHT_MSP430_ATTRIBUTES
2561#define elf_backend_section_from_shdr elf32_msp430_section_from_shdr
2562#define elf_backend_obj_attrs_handle_unknown elf32_msp430_obj_attrs_handle_unknown
2563#undef elf_backend_obj_attrs_arg_type
2564#define elf_backend_obj_attrs_arg_type elf32_msp430_obj_attrs_arg_type
13761a11 2565#define bfd_elf32_bfd_merge_private_bfd_data elf32_msp430_merge_private_bfd_data
2469cfa2
NC		 2566
2567#define ELF_ARCH bfd_arch_msp430
2568#define ELF_MACHINE_CODE EM_MSP430
2569#define ELF_MACHINE_ALT1 EM_MSP430_OLD
13761a11 2570#define ELF_MAXPAGESIZE 4
d1036acb 2571#define ELF_OSABI ELFOSABI_STANDALONE
2469cfa2 2572
6d00b590 2573#define TARGET_LITTLE_SYM msp430_elf32_vec
2469cfa2
NC		 2574#define TARGET_LITTLE_NAME "elf32-msp430"
2575
2576#define elf_info_to_howto msp430_info_to_howto_rela
2577#define elf_info_to_howto_rel NULL
2578#define elf_backend_relocate_section elf32_msp430_relocate_section
2469cfa2
NC		 2579#define elf_backend_check_relocs elf32_msp430_check_relocs
2580#define elf_backend_can_gc_sections 1
2581#define elf_backend_final_write_processing bfd_elf_msp430_final_write_processing
2582#define elf_backend_object_p elf32_msp430_object_p
b18c562e 2583#define bfd_elf32_bfd_relax_section msp430_elf_relax_section
13761a11
NC		 2584#define bfd_elf32_bfd_is_target_special_symbol msp430_elf_is_target_special_symbol
2585
2586#undef elf32_bed
2587#define elf32_bed elf32_msp430_bed
2588
2589#include "elf32-target.h"
2590
2591/* The TI compiler sets the OSABI field to ELFOSABI_NONE. */
2592#undef TARGET_LITTLE_SYM
6d00b590 2593#define TARGET_LITTLE_SYM msp430_elf32_ti_vec
13761a11
NC		 2594
2595#undef elf32_bed
2596#define elf32_bed elf32_msp430_ti_bed
2597
2598#undef ELF_OSABI
2599#define ELF_OSABI ELFOSABI_NONE
2600
2601static const struct bfd_elf_special_section msp430_ti_elf_special_sections[] =
2602{
2603 /* prefix, prefix_length, suffix_len, type, attributes. */
2604 { STRING_COMMA_LEN (".TI.symbol.alias"), 0, SHT_MSP430_SYM_ALIASES, 0 },
2605 { STRING_COMMA_LEN (".TI.section.flags"), 0, SHT_MSP430_SEC_FLAGS, 0 },
2606 { STRING_COMMA_LEN ("_TI_build_attrib"), 0, SHT_MSP430_ATTRIBUTES, 0 },
2607 { NULL, 0, 0, 0, 0 }
2608};
2469cfa2
NC		 2609
2610#include "elf32-target.h"
GDB Binutils - Deliverables
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