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x86: Properly set IBT and SHSTK properties for -z ibt/shstk
[deliverable/binutils-gdb.git] / bfd / elfxx-aarch64.c
CommitLineData
caed7120 1/* AArch64-specific support for ELF.
82704155 2 Copyright (C) 2009-2019 Free Software Foundation, Inc.
caed7120
YZ		 3 Contributed by ARM Ltd.
4
5 This file is part of BFD, the Binary File Descriptor library.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
20
21#include "sysdep.h"
2d5d5a8f
AM		 22#include "bfd.h"
23#include "elf-bfd.h"
caed7120 24#include "elfxx-aarch64.h"
d0ae9fbd
OJ		 25#include <stdarg.h>
26#include <string.h>
caed7120
YZ		 27
28#define MASK(n) ((1u << (n)) - 1)
29
4106101c
MS		 30/* Sign-extend VALUE, which has the indicated number of BITS. */
31
32bfd_signed_vma
33_bfd_aarch64_sign_extend (bfd_vma value, int bits)
34{
35 if (value & ((bfd_vma) 1 << (bits - 1)))
36 /* VALUE is negative. */
37 value |= ((bfd_vma) - 1) << bits;
38
39 return value;
40}
41
42/* Decode the IMM field of ADRP. */
43
44uint32_t
45_bfd_aarch64_decode_adrp_imm (uint32_t insn)
46{
47 return (((insn >> 5) & MASK (19)) << 2) | ((insn >> 29) & MASK (2));
48}
49
caed7120
YZ		 50/* Reencode the imm field of add immediate. */
51static inline uint32_t
52reencode_add_imm (uint32_t insn, uint32_t imm)
53{
54 return (insn & ~(MASK (12) << 10)) | ((imm & MASK (12)) << 10);
55}
56
4106101c
MS		 57/* Reencode the IMM field of ADR. */
58
59uint32_t
60_bfd_aarch64_reencode_adr_imm (uint32_t insn, uint32_t imm)
caed7120
YZ		 61{
62 return (insn & ~((MASK (2) << 29) | (MASK (19) << 5)))
63 | ((imm & MASK (2)) << 29) | ((imm & (MASK (19) << 2)) << 3);
64}
65
66/* Reencode the imm field of ld/st pos immediate. */
67static inline uint32_t
68reencode_ldst_pos_imm (uint32_t insn, uint32_t imm)
69{
70 return (insn & ~(MASK (12) << 10)) | ((imm & MASK (12)) << 10);
71}
72
73/* Encode the 26-bit offset of unconditional branch. */
74static inline uint32_t
75reencode_branch_ofs_26 (uint32_t insn, uint32_t ofs)
76{
77 return (insn & ~MASK (26)) | (ofs & MASK (26));
78}
79
80/* Encode the 19-bit offset of conditional branch and compare & branch. */
81static inline uint32_t
82reencode_cond_branch_ofs_19 (uint32_t insn, uint32_t ofs)
83{
84 return (insn & ~(MASK (19) << 5)) | ((ofs & MASK (19)) << 5);
85}
86
87/* Decode the 19-bit offset of load literal. */
88static inline uint32_t
89reencode_ld_lit_ofs_19 (uint32_t insn, uint32_t ofs)
90{
91 return (insn & ~(MASK (19) << 5)) | ((ofs & MASK (19)) << 5);
92}
93
94/* Encode the 14-bit offset of test & branch. */
95static inline uint32_t
96reencode_tst_branch_ofs_14 (uint32_t insn, uint32_t ofs)
97{
98 return (insn & ~(MASK (14) << 5)) | ((ofs & MASK (14)) << 5);
99}
100
101/* Reencode the imm field of move wide. */
102static inline uint32_t
103reencode_movw_imm (uint32_t insn, uint32_t imm)
104{
105 return (insn & ~(MASK (16) << 5)) | ((imm & MASK (16)) << 5);
106}
107
108/* Reencode mov[zn] to movz. */
109static inline uint32_t
110reencode_movzn_to_movz (uint32_t opcode)
111{
112 return opcode | (1 << 30);
113}
114
115/* Reencode mov[zn] to movn. */
116static inline uint32_t
117reencode_movzn_to_movn (uint32_t opcode)
118{
119 return opcode & ~(1 << 30);
120}
121
122/* Return non-zero if the indicated VALUE has overflowed the maximum
123 range expressible by a unsigned number with the indicated number of
124 BITS. */
125
126static bfd_reloc_status_type
127aarch64_unsigned_overflow (bfd_vma value, unsigned int bits)
128{
129 bfd_vma lim;
130 if (bits >= sizeof (bfd_vma) * 8)
131 return bfd_reloc_ok;
132 lim = (bfd_vma) 1 << bits;
133 if (value >= lim)
134 return bfd_reloc_overflow;
135 return bfd_reloc_ok;
136}
137
138/* Return non-zero if the indicated VALUE has overflowed the maximum
139 range expressible by an signed number with the indicated number of
140 BITS. */
141
142static bfd_reloc_status_type
143aarch64_signed_overflow (bfd_vma value, unsigned int bits)
144{
145 bfd_signed_vma svalue = (bfd_signed_vma) value;
146 bfd_signed_vma lim;
147
148 if (bits >= sizeof (bfd_vma) * 8)
149 return bfd_reloc_ok;
150 lim = (bfd_signed_vma) 1 << (bits - 1);
151 if (svalue < -lim || svalue >= lim)
152 return bfd_reloc_overflow;
153 return bfd_reloc_ok;
154}
155
156/* Insert the addend/value into the instruction or data object being
157 relocated. */
158bfd_reloc_status_type
159_bfd_aarch64_elf_put_addend (bfd *abfd,
160 bfd_byte *address, bfd_reloc_code_real_type r_type,
161 reloc_howto_type *howto, bfd_signed_vma addend)
162{
163 bfd_reloc_status_type status = bfd_reloc_ok;
164 bfd_signed_vma old_addend = addend;
165 bfd_vma contents;
166 int size;
167
168 size = bfd_get_reloc_size (howto);
169 switch (size)
170 {
6346d5ca
AM		 171 case 0:
172 return status;
caed7120
YZ		 173 case 2:
174 contents = bfd_get_16 (abfd, address);
175 break;
176 case 4:
177 if (howto->src_mask != 0xffffffff)
178 /* Must be 32-bit instruction, always little-endian. */
179 contents = bfd_getl32 (address);
180 else
181 /* Must be 32-bit data (endianness dependent). */
182 contents = bfd_get_32 (abfd, address);
183 break;
184 case 8:
185 contents = bfd_get_64 (abfd, address);
186 break;
187 default:
188 abort ();
189 }
190
191 switch (howto->complain_on_overflow)
192 {
193 case complain_overflow_dont:
194 break;
195 case complain_overflow_signed:
196 status = aarch64_signed_overflow (addend,
197 howto->bitsize + howto->rightshift);
198 break;
199 case complain_overflow_unsigned:
200 status = aarch64_unsigned_overflow (addend,
201 howto->bitsize + howto->rightshift);
202 break;
203 case complain_overflow_bitfield:
204 default:
205 abort ();
206 }
207
208 addend >>= howto->rightshift;
209
210 switch (r_type)
211 {
caed7120 212 case BFD_RELOC_AARCH64_CALL26:
ce336788 213 case BFD_RELOC_AARCH64_JUMP26:
caed7120
YZ		 214 contents = reencode_branch_ofs_26 (contents, addend);
215 break;
216
217 case BFD_RELOC_AARCH64_BRANCH19:
218 contents = reencode_cond_branch_ofs_19 (contents, addend);
219 break;
220
221 case BFD_RELOC_AARCH64_TSTBR14:
222 contents = reencode_tst_branch_ofs_14 (contents, addend);
223 break;
224
caed7120 225 case BFD_RELOC_AARCH64_GOT_LD_PREL19:
ce336788
JW		 226 case BFD_RELOC_AARCH64_LD_LO19_PCREL:
227 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19:
043bf05a 228 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19:
caed7120
YZ		 229 if (old_addend & ((1 << howto->rightshift) - 1))
230 return bfd_reloc_overflow;
231 contents = reencode_ld_lit_ofs_19 (contents, addend);
232 break;
233
234 case BFD_RELOC_AARCH64_TLSDESC_CALL:
235 break;
236
ce336788
JW		 237 case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
238 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
239 case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
240 case BFD_RELOC_AARCH64_ADR_LO21_PCREL:
241 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
389b8029 242 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21:
caed7120 243 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
ce336788 244 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21:
caed7120 245 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
f69e4920 246 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21:
77a69ff8 247 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21:
4106101c 248 contents = _bfd_aarch64_reencode_adr_imm (contents, addend);
caed7120
YZ		 249 break;
250
ce336788 251 case BFD_RELOC_AARCH64_ADD_LO12:
f955cccf 252 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12:
caed7120 253 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
6ffe9a1b 254 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12:
40fbed84 255 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12:
753999c1 256 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC:
73f925cc 257 case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC:
caed7120 258 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
ce336788 259 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
caed7120 260 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
caed7120 261 /* Corresponds to: add rd, rn, #uimm12 to provide the low order
07d6d2b8
AM		 262 12 bits of the page offset following
263 BFD_RELOC_AARCH64_ADR_HI21_PCREL which computes the
264 (pc-relative) page base. */
caed7120
YZ		 265 contents = reencode_add_imm (contents, addend);
266 break;
267
7018c030 268 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14:
ce336788 269 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
a2e1db00 270 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15:
99ad26cb 271 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15:
ce336788
JW		 272 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
273 case BFD_RELOC_AARCH64_LDST128_LO12:
caed7120
YZ		 274 case BFD_RELOC_AARCH64_LDST16_LO12:
275 case BFD_RELOC_AARCH64_LDST32_LO12:
276 case BFD_RELOC_AARCH64_LDST64_LO12:
ce336788 277 case BFD_RELOC_AARCH64_LDST8_LO12:
caed7120 278 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
f955cccf 279 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12:
caed7120 280 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
ce336788 281 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
07c9aa07
JW		 282 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12:
283 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC:
284 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12:
285 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC:
286 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12:
287 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC:
288 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12:
289 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC:
e04ef022
RL		 290 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12:
291 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC:
292 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12:
293 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC:
294 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12:
295 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC:
296 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12:
297 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC:
caed7120
YZ		 298 if (old_addend & ((1 << howto->rightshift) - 1))
299 return bfd_reloc_overflow;
300 /* Used for ldr*|str* rt, [rn, #uimm12] to provide the low order
e04ef022 301 12 bits address offset. */
caed7120
YZ		 302 contents = reencode_ldst_pos_imm (contents, addend);
303 break;
304
305 /* Group relocations to create high bits of a 16, 32, 48 or 64
07d6d2b8
AM		 306 bit signed data or abs address inline. Will change
307 instruction to MOVN or MOVZ depending on sign of calculated
308 value. */
caed7120 309
caed7120
YZ		 310 case BFD_RELOC_AARCH64_MOVW_G0_S:
311 case BFD_RELOC_AARCH64_MOVW_G1_S:
312 case BFD_RELOC_AARCH64_MOVW_G2_S:
1daf502a
RL		 313 case BFD_RELOC_AARCH64_MOVW_PREL_G0:
314 case BFD_RELOC_AARCH64_MOVW_PREL_G1:
315 case BFD_RELOC_AARCH64_MOVW_PREL_G2:
316 case BFD_RELOC_AARCH64_MOVW_PREL_G3:
6ffe9a1b
JW		 317 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0:
318 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1:
319 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
ce336788
JW		 320 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
321 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
322 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
caed7120
YZ		 323 /* NOTE: We can only come here with movz or movn. */
324 if (addend < 0)
325 {
326 /* Force use of MOVN. */
327 addend = ~addend;
328 contents = reencode_movzn_to_movn (contents);
329 }
330 else
331 {
332 /* Force use of MOVZ. */
333 contents = reencode_movzn_to_movz (contents);
334 }
1a0670f3 335 /* Fall through. */
caed7120
YZ		 336
337 /* Group relocations to create a 16, 32, 48 or 64 bit unsigned
07d6d2b8 338 data or abs address inline. */
caed7120
YZ		 339
340 case BFD_RELOC_AARCH64_MOVW_G0:
341 case BFD_RELOC_AARCH64_MOVW_G0_NC:
342 case BFD_RELOC_AARCH64_MOVW_G1:
343 case BFD_RELOC_AARCH64_MOVW_G1_NC:
344 case BFD_RELOC_AARCH64_MOVW_G2:
345 case BFD_RELOC_AARCH64_MOVW_G2_NC:
346 case BFD_RELOC_AARCH64_MOVW_G3:
dc8008f5 347 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC:
74a1bfe1 348 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
1daf502a
RL		 349 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC:
350 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC:
351 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC:
0484b454
RL		 352 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
353 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
7ba7cfe4 354 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC:
94facae3 355 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
3b957e5b
RL		 356 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC:
357 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1:
6ffe9a1b
JW		 358 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC:
359 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC:
ce336788
JW		 360 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
361 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
caed7120
YZ		 362 contents = reencode_movw_imm (contents, addend);
363 break;
364
365 default:
366 /* Repack simple data */
367 if (howto->dst_mask & (howto->dst_mask + 1))
368 return bfd_reloc_notsupported;
369
370 contents = ((contents & ~howto->dst_mask) | (addend & howto->dst_mask));
371 break;
372 }
373
374 switch (size)
375 {
376 case 2:
377 bfd_put_16 (abfd, contents, address);
378 break;
379 case 4:
380 if (howto->dst_mask != 0xffffffff)
381 /* must be 32-bit instruction, always little-endian */
382 bfd_putl32 (contents, address);
383 else
384 /* must be 32-bit data (endianness dependent) */
385 bfd_put_32 (abfd, contents, address);
386 break;
387 case 8:
388 bfd_put_64 (abfd, contents, address);
389 break;
390 default:
391 abort ();
392 }
393
394 return status;
395}
396
397bfd_vma
398_bfd_aarch64_elf_resolve_relocation (bfd_reloc_code_real_type r_type,
399 bfd_vma place, bfd_vma value,
400 bfd_vma addend, bfd_boolean weak_undef_p)
401{
402 switch (r_type)
403 {
caed7120 404 case BFD_RELOC_AARCH64_NONE:
ce336788 405 case BFD_RELOC_AARCH64_TLSDESC_CALL:
caed7120
YZ		 406 break;
407
ce336788
JW		 408 case BFD_RELOC_AARCH64_16_PCREL:
409 case BFD_RELOC_AARCH64_32_PCREL:
410 case BFD_RELOC_AARCH64_64_PCREL:
411 case BFD_RELOC_AARCH64_ADR_LO21_PCREL:
412 case BFD_RELOC_AARCH64_BRANCH19:
413 case BFD_RELOC_AARCH64_LD_LO19_PCREL:
1daf502a
RL		 414 case BFD_RELOC_AARCH64_MOVW_PREL_G0:
415 case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC:
416 case BFD_RELOC_AARCH64_MOVW_PREL_G1:
417 case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC:
418 case BFD_RELOC_AARCH64_MOVW_PREL_G2:
419 case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC:
420 case BFD_RELOC_AARCH64_MOVW_PREL_G3:
389b8029 421 case BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21:
1ada945d 422 case BFD_RELOC_AARCH64_TLSDESC_LD_PREL19:
3c12b054 423 case BFD_RELOC_AARCH64_TLSGD_ADR_PREL21:
043bf05a 424 case BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19:
77a69ff8 425 case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21:
caed7120
YZ		 426 case BFD_RELOC_AARCH64_TSTBR14:
427 if (weak_undef_p)
428 value = place;
429 value = value + addend - place;
430 break;
431
432 case BFD_RELOC_AARCH64_CALL26:
433 case BFD_RELOC_AARCH64_JUMP26:
434 value = value + addend - place;
435 break;
436
437 case BFD_RELOC_AARCH64_16:
438 case BFD_RELOC_AARCH64_32:
caed7120
YZ		 439 case BFD_RELOC_AARCH64_MOVW_G0:
440 case BFD_RELOC_AARCH64_MOVW_G0_NC:
ce336788 441 case BFD_RELOC_AARCH64_MOVW_G0_S:
caed7120
YZ		 442 case BFD_RELOC_AARCH64_MOVW_G1:
443 case BFD_RELOC_AARCH64_MOVW_G1_NC:
ce336788 444 case BFD_RELOC_AARCH64_MOVW_G1_S:
caed7120
YZ		 445 case BFD_RELOC_AARCH64_MOVW_G2:
446 case BFD_RELOC_AARCH64_MOVW_G2_NC:
ce336788 447 case BFD_RELOC_AARCH64_MOVW_G2_S:
caed7120 448 case BFD_RELOC_AARCH64_MOVW_G3:
0484b454
RL		 449 case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
450 case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
7ba7cfe4 451 case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC:
94facae3 452 case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
6ffe9a1b 453 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12:
40fbed84 454 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12:
753999c1 455 case BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC:
07c9aa07 456 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12:
07c9aa07 457 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12:
07c9aa07 458 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12:
07c9aa07 459 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12:
6ffe9a1b
JW		 460 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0:
461 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC:
462 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1:
463 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC:
464 case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
e04ef022 465 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12:
e04ef022 466 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12:
e04ef022 467 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12:
e04ef022 468 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12:
caed7120
YZ		 469 value = value + addend;
470 break;
471
caed7120 472 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
ce336788 473 case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
caed7120
YZ		 474 if (weak_undef_p)
475 value = PG (place);
476 value = PG (value + addend) - PG (place);
477 break;
478
479 case BFD_RELOC_AARCH64_GOT_LD_PREL19:
480 value = value + addend - place;
481 break;
482
483 case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
484 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
485 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
486 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
f69e4920 487 case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21:
caed7120
YZ		 488 value = PG (value + addend) - PG (place);
489 break;
490
2aff25ba 491 /* Caller must make sure addend is the base address of .got section. */
7018c030 492 case BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14:
99ad26cb 493 case BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15:
2aff25ba
JW		 494 addend = PG (addend);
495 /* Fall through. */
496 case BFD_RELOC_AARCH64_LD64_GOTOFF_LO15:
497 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC:
498 case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
499 value = value - addend;
99ad26cb
JW		 500 break;
501
caed7120 502 case BFD_RELOC_AARCH64_ADD_LO12:
caed7120 503 case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
ce336788
JW		 504 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
505 case BFD_RELOC_AARCH64_LDST128_LO12:
caed7120
YZ		 506 case BFD_RELOC_AARCH64_LDST16_LO12:
507 case BFD_RELOC_AARCH64_LDST32_LO12:
508 case BFD_RELOC_AARCH64_LDST64_LO12:
ce336788 509 case BFD_RELOC_AARCH64_LDST8_LO12:
caed7120 510 case BFD_RELOC_AARCH64_TLSDESC_ADD:
f955cccf 511 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12:
caed7120 512 case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
f955cccf 513 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12:
caed7120
YZ		 514 case BFD_RELOC_AARCH64_TLSDESC_LDR:
515 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
caed7120 516 case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
ce336788 517 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
b939d8a0
RL		 518 case BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC:
519 case BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC:
520 case BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC:
521 case BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC:
caed7120 522 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
b939d8a0
RL		 523 case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC:
524 case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC:
525 case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC:
526 case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC:
caed7120
YZ		 527 value = PG_OFFSET (value + addend);
528 break;
529
36e6c140
JW		 530 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
531 value = value + addend;
532 break;
533
3b957e5b 534 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1:
caed7120
YZ		 535 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
536 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
537 value = (value + addend) & (bfd_vma) 0xffff0000;
538 break;
539 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
bab91cce
JW		 540 /* Mask off low 12bits, keep all other high bits, so that the later
541 generic code could check whehter there is overflow. */
542 value = (value + addend) & ~(bfd_vma) 0xfff;
caed7120
YZ		 543 break;
544
3b957e5b 545 case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC:
caed7120
YZ		 546 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
547 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
548 value = (value + addend) & (bfd_vma) 0xffff;
549 break;
550
551 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
552 value = (value + addend) & ~(bfd_vma) 0xffffffff;
553 value -= place & ~(bfd_vma) 0xffffffff;
554 break;
555
556 default:
557 break;
558 }
559
560 return value;
561}
562
caed7120
YZ		 563/* Support for core dump NOTE sections. */
564
565bfd_boolean
566_bfd_aarch64_elf_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
567{
568 int offset;
569 size_t size;
570
571 switch (note->descsz)
572 {
573 default:
574 return FALSE;
575
3b570dee 576 case 392: /* sizeof(struct elf_prstatus) on Linux/arm64. */
caed7120
YZ		 577 /* pr_cursig */
578 elf_tdata (abfd)->core->signal
579 = bfd_get_16 (abfd, note->descdata + 12);
580
581 /* pr_pid */
582 elf_tdata (abfd)->core->lwpid
583 = bfd_get_32 (abfd, note->descdata + 32);
584
585 /* pr_reg */
586 offset = 112;
587 size = 272;
588
589 break;
590 }
591
592 /* Make a ".reg/999" section. */
593 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
594 size, note->descpos + offset);
595}
d0ae9fbd
OJ		 596
597bfd_boolean
598_bfd_aarch64_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
599{
600 switch (note->descsz)
601 {
602 default:
603 return FALSE;
604
07d6d2b8 605 case 136: /* This is sizeof(struct elf_prpsinfo) on Linux/aarch64. */
d0ae9fbd
OJ		 606 elf_tdata (abfd)->core->pid = bfd_get_32 (abfd, note->descdata + 24);
607 elf_tdata (abfd)->core->program
608 = _bfd_elfcore_strndup (abfd, note->descdata + 40, 16);
609 elf_tdata (abfd)->core->command
610 = _bfd_elfcore_strndup (abfd, note->descdata + 56, 80);
611 }
612
613 /* Note that for some reason, a spurious space is tacked
614 onto the end of the args in some (at least one anyway)
615 implementations, so strip it off if it exists. */
616
617 {
618 char *command = elf_tdata (abfd)->core->command;
619 int n = strlen (command);
620
621 if (0 < n && command[n - 1] == ' ')
622 command[n - 1] = '\0';
623 }
624
625 return TRUE;
626}
627
628char *
629_bfd_aarch64_elf_write_core_note (bfd *abfd, char *buf, int *bufsiz, int note_type,
630 ...)
631{
632 switch (note_type)
633 {
634 default:
635 return NULL;
636
637 case NT_PRPSINFO:
638 {
602f1657 639 char data[136] ATTRIBUTE_NONSTRING;
07d6d2b8 640 va_list ap;
d0ae9fbd 641
07d6d2b8
AM		 642 va_start (ap, note_type);
643 memset (data, 0, sizeof (data));
644 strncpy (data + 40, va_arg (ap, const char *), 16);
be3e27bb 645#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 646 DIAGNOSTIC_PUSH;
be3e27bb 647 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
95da9854
L		 648 -Wstringop-truncation:
649 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
650 */
95da9854
L		 651 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
652#endif
07d6d2b8 653 strncpy (data + 56, va_arg (ap, const char *), 80);
be3e27bb 654#if GCC_VERSION == 8000 || GCC_VERSION == 8001
95da9854 655 DIAGNOSTIC_POP;
fe75810f 656#endif
07d6d2b8 657 va_end (ap);
d0ae9fbd 658
07d6d2b8 659 return elfcore_write_note (abfd, buf, bufsiz, "CORE",
d0ae9fbd
OJ		 660 note_type, data, sizeof (data));
661 }
662
663 case NT_PRSTATUS:
664 {
07d6d2b8
AM		 665 char data[392];
666 va_list ap;
667 long pid;
668 int cursig;
669 const void *greg;
670
671 va_start (ap, note_type);
672 memset (data, 0, sizeof (data));
673 pid = va_arg (ap, long);
674 bfd_put_32 (abfd, pid, data + 32);
675 cursig = va_arg (ap, int);
676 bfd_put_16 (abfd, cursig, data + 12);
677 greg = va_arg (ap, const void *);
678 memcpy (data + 112, greg, 272);
679 va_end (ap);
680
681 return elfcore_write_note (abfd, buf, bufsiz, "CORE",
d0ae9fbd
OJ		 682 note_type, data, sizeof (data));
683 }
684 }
685}
GDB Binutils - Deliverables
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