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[deliverable/binutils-gdb.git] / bfd / xtensa-modules.c
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e0001a05 1/* Xtensa configuration-specific ISA information.
4b95cf5c 2 Copyright (C) 2003-2014 Free Software Foundation, Inc.
e0001a05
NC		 3
4 This file is part of BFD, the Binary File Descriptor library.
5
43cd72b9
BW		 6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License as
7aa09196 8 published by the Free Software Foundation; either version 2 of the
43cd72b9 9 License, or (at your option) any later version.
e0001a05
NC		 10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
43cd72b9
BW		 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 General Public License for more details.
e0001a05
NC		 15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
3e110533 18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
53e09e0a 19 02110-1301, USA. */
e0001a05 20
43cd72b9 21#include "ansidecl.h"
e0001a05
NC		 22#include <xtensa-isa.h>
23#include "xtensa-isa-internal.h"
e0001a05 24
43cd72b9
BW		 25\f
26/* Sysregs. */
27
28static xtensa_sysreg_internal sysregs[] = {
29 { "LBEG", 0, 0 },
30 { "LEND", 1, 0 },
31 { "LCOUNT", 2, 0 },
7aa09196
SA		 32 { "BR", 4, 0 },
33 { "ACCLO", 16, 0 },
34 { "ACCHI", 17, 0 },
35 { "M0", 32, 0 },
36 { "M1", 33, 0 },
37 { "M2", 34, 0 },
38 { "M3", 35, 0 },
074f5109 39 { "PTEVADDR", 83, 0 },
33430bd0 40 { "MMID", 89, 0 },
43cd72b9
BW		 41 { "DDR", 104, 0 },
42 { "176", 176, 0 },
43 { "208", 208, 0 },
44 { "INTERRUPT", 226, 0 },
45 { "INTCLEAR", 227, 0 },
46 { "CCOUNT", 234, 0 },
47 { "PRID", 235, 0 },
48 { "ICOUNT", 236, 0 },
49 { "CCOMPARE0", 240, 0 },
50 { "CCOMPARE1", 241, 0 },
51 { "CCOMPARE2", 242, 0 },
33430bd0 52 { "VECBASE", 231, 0 },
43cd72b9
BW		 53 { "EPC1", 177, 0 },
54 { "EPC2", 178, 0 },
55 { "EPC3", 179, 0 },
56 { "EPC4", 180, 0 },
33430bd0
BW		 57 { "EPC5", 181, 0 },
58 { "EPC6", 182, 0 },
59 { "EPC7", 183, 0 },
43cd72b9
BW		 60 { "EXCSAVE1", 209, 0 },
61 { "EXCSAVE2", 210, 0 },
62 { "EXCSAVE3", 211, 0 },
63 { "EXCSAVE4", 212, 0 },
33430bd0
BW		 64 { "EXCSAVE5", 213, 0 },
65 { "EXCSAVE6", 214, 0 },
66 { "EXCSAVE7", 215, 0 },
43cd72b9
BW		 67 { "EPS2", 194, 0 },
68 { "EPS3", 195, 0 },
69 { "EPS4", 196, 0 },
33430bd0
BW		 70 { "EPS5", 197, 0 },
71 { "EPS6", 198, 0 },
72 { "EPS7", 199, 0 },
43cd72b9
BW		 73 { "EXCCAUSE", 232, 0 },
74 { "DEPC", 192, 0 },
75 { "EXCVADDR", 238, 0 },
76 { "WINDOWBASE", 72, 0 },
77 { "WINDOWSTART", 73, 0 },
78 { "SAR", 3, 0 },
79 { "LITBASE", 5, 0 },
80 { "PS", 230, 0 },
81 { "MISC0", 244, 0 },
82 { "MISC1", 245, 0 },
7aa09196
SA		 83 { "MISC2", 246, 0 },
84 { "MISC3", 247, 0 },
43cd72b9
BW		 85 { "INTENABLE", 228, 0 },
86 { "DBREAKA0", 144, 0 },
87 { "DBREAKC0", 160, 0 },
88 { "DBREAKA1", 145, 0 },
89 { "DBREAKC1", 161, 0 },
90 { "IBREAKA0", 128, 0 },
91 { "IBREAKA1", 129, 0 },
92 { "IBREAKENABLE", 96, 0 },
93 { "ICOUNTLEVEL", 237, 0 },
074f5109
BW		 94 { "DEBUGCAUSE", 233, 0 },
95 { "RASID", 90, 0 },
96 { "ITLBCFG", 91, 0 },
33430bd0
BW		 97 { "DTLBCFG", 92, 0 },
98 { "CPENABLE", 224, 0 },
99 { "SCOMPARE1", 12, 0 },
7aa09196
SA		 100 { "THREADPTR", 231, 1 },
101 { "FCR", 232, 1 },
102 { "FSR", 233, 1 }
43cd72b9
BW		 103};
104
7aa09196
SA		 105#define NUM_SYSREGS 74
106#define MAX_SPECIAL_REG 247
107#define MAX_USER_REG 233
43cd72b9
BW		 108
109\f
110/* Processor states. */
111
112static xtensa_state_internal states[] = {
113 { "LCOUNT", 32, 0 },
114 { "PC", 32, 0 },
115 { "ICOUNT", 32, 0 },
116 { "DDR", 32, 0 },
7aa09196 117 { "INTERRUPT", 32, 0 },
43cd72b9
BW		 118 { "CCOUNT", 32, 0 },
119 { "XTSYNC", 1, 0 },
33430bd0 120 { "VECBASE", 22, 0 },
43cd72b9
BW		 121 { "EPC1", 32, 0 },
122 { "EPC2", 32, 0 },
123 { "EPC3", 32, 0 },
124 { "EPC4", 32, 0 },
33430bd0
BW		 125 { "EPC5", 32, 0 },
126 { "EPC6", 32, 0 },
127 { "EPC7", 32, 0 },
43cd72b9
BW		 128 { "EXCSAVE1", 32, 0 },
129 { "EXCSAVE2", 32, 0 },
130 { "EXCSAVE3", 32, 0 },
131 { "EXCSAVE4", 32, 0 },
33430bd0
BW		 132 { "EXCSAVE5", 32, 0 },
133 { "EXCSAVE6", 32, 0 },
134 { "EXCSAVE7", 32, 0 },
074f5109
BW		 135 { "EPS2", 15, 0 },
136 { "EPS3", 15, 0 },
137 { "EPS4", 15, 0 },
33430bd0
BW		 138 { "EPS5", 15, 0 },
139 { "EPS6", 15, 0 },
140 { "EPS7", 15, 0 },
43cd72b9
BW		 141 { "EXCCAUSE", 6, 0 },
142 { "PSINTLEVEL", 4, 0 },
143 { "PSUM", 1, 0 },
144 { "PSWOE", 1, 0 },
074f5109 145 { "PSRING", 2, 0 },
43cd72b9
BW		 146 { "PSEXCM", 1, 0 },
147 { "DEPC", 32, 0 },
148 { "EXCVADDR", 32, 0 },
7aa09196
SA		 149 { "WindowBase", 4, 0 },
150 { "WindowStart", 16, 0 },
43cd72b9
BW		 151 { "PSCALLINC", 2, 0 },
152 { "PSOWB", 4, 0 },
153 { "LBEG", 32, 0 },
154 { "LEND", 32, 0 },
155 { "SAR", 6, 0 },
33430bd0 156 { "THREADPTR", 32, 0 },
43cd72b9
BW		 157 { "LITBADDR", 20, 0 },
158 { "LITBEN", 1, 0 },
159 { "MISC0", 32, 0 },
160 { "MISC1", 32, 0 },
7aa09196
SA		 161 { "MISC2", 32, 0 },
162 { "MISC3", 32, 0 },
163 { "ACC", 40, 0 },
43cd72b9 164 { "InOCDMode", 1, 0 },
7aa09196 165 { "INTENABLE", 32, 0 },
43cd72b9
BW		 166 { "DBREAKA0", 32, 0 },
167 { "DBREAKC0", 8, 0 },
168 { "DBREAKA1", 32, 0 },
169 { "DBREAKC1", 8, 0 },
170 { "IBREAKA0", 32, 0 },
171 { "IBREAKA1", 32, 0 },
172 { "IBREAKENABLE", 2, 0 },
173 { "ICOUNTLEVEL", 4, 0 },
174 { "DEBUGCAUSE", 6, 0 },
175 { "DBNUM", 4, 0 },
176 { "CCOMPARE0", 32, 0 },
177 { "CCOMPARE1", 32, 0 },
074f5109
BW		 178 { "CCOMPARE2", 32, 0 },
179 { "ASID3", 8, 0 },
180 { "ASID2", 8, 0 },
181 { "ASID1", 8, 0 },
182 { "INSTPGSZID4", 2, 0 },
183 { "DATAPGSZID4", 2, 0 },
33430bd0 184 { "PTBASE", 10, 0 },
7aa09196
SA		 185 { "CPENABLE", 1, 0 },
186 { "SCOMPARE1", 32, 0 },
187 { "RoundMode", 2, 0 },
188 { "InvalidEnable", 1, 0 },
189 { "DivZeroEnable", 1, 0 },
190 { "OverflowEnable", 1, 0 },
191 { "UnderflowEnable", 1, 0 },
192 { "InexactEnable", 1, 0 },
193 { "InvalidFlag", 1, 0 },
194 { "DivZeroFlag", 1, 0 },
195 { "OverflowFlag", 1, 0 },
196 { "UnderflowFlag", 1, 0 },
197 { "InexactFlag", 1, 0 },
198 { "FPreserved20", 20, 0 },
199 { "FPreserved20a", 20, 0 },
200 { "FPreserved5", 5, 0 },
201 { "FPreserved7", 7, 0 }
202};
203
204#define NUM_STATES 89
205
206/* Macros for xtensa_state numbers (for use in iclasses because the
207 state numbers are not available when the iclass table is generated). */
208
209#define STATE_LCOUNT 0
210#define STATE_PC 1
211#define STATE_ICOUNT 2
212#define STATE_DDR 3
213#define STATE_INTERRUPT 4
214#define STATE_CCOUNT 5
215#define STATE_XTSYNC 6
216#define STATE_VECBASE 7
217#define STATE_EPC1 8
218#define STATE_EPC2 9
219#define STATE_EPC3 10
220#define STATE_EPC4 11
221#define STATE_EPC5 12
222#define STATE_EPC6 13
223#define STATE_EPC7 14
224#define STATE_EXCSAVE1 15
225#define STATE_EXCSAVE2 16
226#define STATE_EXCSAVE3 17
227#define STATE_EXCSAVE4 18
228#define STATE_EXCSAVE5 19
229#define STATE_EXCSAVE6 20
230#define STATE_EXCSAVE7 21
231#define STATE_EPS2 22
232#define STATE_EPS3 23
233#define STATE_EPS4 24
234#define STATE_EPS5 25
235#define STATE_EPS6 26
236#define STATE_EPS7 27
237#define STATE_EXCCAUSE 28
238#define STATE_PSINTLEVEL 29
239#define STATE_PSUM 30
240#define STATE_PSWOE 31
241#define STATE_PSRING 32
242#define STATE_PSEXCM 33
243#define STATE_DEPC 34
244#define STATE_EXCVADDR 35
245#define STATE_WindowBase 36
246#define STATE_WindowStart 37
247#define STATE_PSCALLINC 38
248#define STATE_PSOWB 39
249#define STATE_LBEG 40
250#define STATE_LEND 41
251#define STATE_SAR 42
252#define STATE_THREADPTR 43
253#define STATE_LITBADDR 44
254#define STATE_LITBEN 45
255#define STATE_MISC0 46
256#define STATE_MISC1 47
257#define STATE_MISC2 48
258#define STATE_MISC3 49
259#define STATE_ACC 50
260#define STATE_InOCDMode 51
261#define STATE_INTENABLE 52
262#define STATE_DBREAKA0 53
263#define STATE_DBREAKC0 54
264#define STATE_DBREAKA1 55
265#define STATE_DBREAKC1 56
266#define STATE_IBREAKA0 57
267#define STATE_IBREAKA1 58
268#define STATE_IBREAKENABLE 59
269#define STATE_ICOUNTLEVEL 60
270#define STATE_DEBUGCAUSE 61
271#define STATE_DBNUM 62
272#define STATE_CCOMPARE0 63
273#define STATE_CCOMPARE1 64
274#define STATE_CCOMPARE2 65
275#define STATE_ASID3 66
276#define STATE_ASID2 67
277#define STATE_ASID1 68
278#define STATE_INSTPGSZID4 69
279#define STATE_DATAPGSZID4 70
280#define STATE_PTBASE 71
281#define STATE_CPENABLE 72
282#define STATE_SCOMPARE1 73
283#define STATE_RoundMode 74
284#define STATE_InvalidEnable 75
285#define STATE_DivZeroEnable 76
286#define STATE_OverflowEnable 77
287#define STATE_UnderflowEnable 78
288#define STATE_InexactEnable 79
289#define STATE_InvalidFlag 80
290#define STATE_DivZeroFlag 81
291#define STATE_OverflowFlag 82
292#define STATE_UnderflowFlag 83
293#define STATE_InexactFlag 84
294#define STATE_FPreserved20 85
295#define STATE_FPreserved20a 86
296#define STATE_FPreserved5 87
297#define STATE_FPreserved7 88
43cd72b9
BW		 298
299\f
300/* Field definitions. */
301
302static unsigned
303Field_t_Slot_inst_get (const xtensa_insnbuf insn)
304{
305 unsigned tie_t = 0;
7aa09196 306 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
43cd72b9
BW		 307 return tie_t;
308}
309
310static void
311Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
312{
313 uint32 tie_t;
314 tie_t = (val << 28) >> 28;
7aa09196 315 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
43cd72b9
BW		 316}
317
318static unsigned
7aa09196 319Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 320{
43cd72b9 321 unsigned tie_t = 0;
7aa09196 322 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
43cd72b9 323 return tie_t;
e0001a05
NC		 324}
325
43cd72b9 326static void
7aa09196 327Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 328{
43cd72b9
BW		 329 uint32 tie_t;
330 tie_t = (val << 28) >> 28;
7aa09196 331 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
e0001a05
NC		 332}
333
43cd72b9 334static unsigned
7aa09196 335Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 336{
43cd72b9 337 unsigned tie_t = 0;
7aa09196 338 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
43cd72b9 339 return tie_t;
e0001a05
NC		 340}
341
43cd72b9 342static void
7aa09196 343Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
e0001a05 344{
43cd72b9
BW		 345 uint32 tie_t;
346 tie_t = (val << 28) >> 28;
7aa09196 347 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
e0001a05
NC		 348}
349
43cd72b9 350static unsigned
7aa09196 351Field_t_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
e0001a05 352{
43cd72b9 353 unsigned tie_t = 0;
56fb3749 354 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
43cd72b9 355 return tie_t;
e0001a05
NC		 356}
357
43cd72b9 358static void
7aa09196 359Field_t_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
e0001a05 360{
43cd72b9 361 uint32 tie_t;
56fb3749
SA		 362 tie_t = (val << 28) >> 28;
363 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
e0001a05
NC		 364}
365
43cd72b9 366static unsigned
7aa09196 367Field_t_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
e0001a05 368{
43cd72b9 369 unsigned tie_t = 0;
7aa09196 370 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
43cd72b9 371 return tie_t;
e0001a05
NC		 372}
373
43cd72b9 374static void
7aa09196 375Field_t_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
e0001a05 376{
43cd72b9
BW		 377 uint32 tie_t;
378 tie_t = (val << 28) >> 28;
7aa09196 379 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
e0001a05
NC		 380}
381
43cd72b9 382static unsigned
7aa09196 383Field_t_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
e0001a05 384{
43cd72b9 385 unsigned tie_t = 0;
7aa09196 386 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
43cd72b9 387 return tie_t;
e0001a05
NC		 388}
389
43cd72b9 390static void
7aa09196 391Field_t_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
e0001a05 392{
43cd72b9 393 uint32 tie_t;
56fb3749 394 tie_t = (val << 28) >> 28;
7aa09196 395 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
e0001a05
NC		 396}
397
43cd72b9 398static unsigned
7aa09196 399Field_t_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
e0001a05 400{
43cd72b9 401 unsigned tie_t = 0;
7aa09196 402 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
43cd72b9 403 return tie_t;
e0001a05
NC		 404}
405
43cd72b9 406static void
7aa09196 407Field_t_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
e0001a05 408{
43cd72b9 409 uint32 tie_t;
7aa09196
SA		 410 tie_t = (val << 28) >> 28;
411 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
e0001a05
NC		 412}
413
43cd72b9 414static unsigned
7aa09196 415Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
56fb3749
SA		 416{
417 unsigned tie_t = 0;
7aa09196 418 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
56fb3749
SA		 419 return tie_t;
420}
421
422static void
7aa09196 423Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
56fb3749
SA		 424{
425 uint32 tie_t;
7aa09196
SA		 426 tie_t = (val << 31) >> 31;
427 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
56fb3749
SA		 428}
429
430static unsigned
7aa09196 431Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 432{
43cd72b9 433 unsigned tie_t = 0;
7aa09196
SA		 434 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
435 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
43cd72b9 436 return tie_t;
e0001a05
NC		 437}
438
43cd72b9 439static void
7aa09196 440Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 441{
43cd72b9
BW		 442 uint32 tie_t;
443 tie_t = (val << 28) >> 28;
7aa09196
SA		 444 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
445 tie_t = (val << 27) >> 31;
446 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
e0001a05
NC		 447}
448
33430bd0 449static unsigned
7aa09196 450Field_bbi_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
33430bd0
BW		 451{
452 unsigned tie_t = 0;
7aa09196
SA		 453 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
454 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
33430bd0
BW		 455 return tie_t;
456}
457
458static void
7aa09196 459Field_bbi_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
33430bd0
BW		 460{
461 uint32 tie_t;
462 tie_t = (val << 28) >> 28;
7aa09196
SA		 463 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
464 tie_t = (val << 27) >> 31;
465 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
33430bd0
BW		 466}
467
43cd72b9 468static unsigned
7aa09196 469Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 470{
43cd72b9 471 unsigned tie_t = 0;
7aa09196 472 tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
43cd72b9 473 return tie_t;
e0001a05
NC		 474}
475
43cd72b9 476static void
7aa09196 477Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 478{
43cd72b9 479 uint32 tie_t;
7aa09196
SA		 480 tie_t = (val << 20) >> 20;
481 insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
e0001a05
NC		 482}
483
43cd72b9 484static unsigned
7aa09196 485Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 486{
43cd72b9 487 unsigned tie_t = 0;
7aa09196 488 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
43cd72b9 489 return tie_t;
e0001a05
NC		 490}
491
43cd72b9 492static void
7aa09196 493Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 494{
43cd72b9 495 uint32 tie_t;
7aa09196
SA		 496 tie_t = (val << 24) >> 24;
497 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
e0001a05
NC		 498}
499
43cd72b9 500static unsigned
7aa09196 501Field_imm8_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
e0001a05 502{
43cd72b9 503 unsigned tie_t = 0;
7aa09196 504 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
43cd72b9 505 return tie_t;
e0001a05
NC		 506}
507
43cd72b9 508static void
7aa09196 509Field_imm8_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
e0001a05 510{
43cd72b9 511 uint32 tie_t;
7aa09196
SA		 512 tie_t = (val << 24) >> 24;
513 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
e0001a05
NC		 514}
515
43cd72b9 516static unsigned
7aa09196 517Field_imm8_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
e0001a05 518{
43cd72b9 519 unsigned tie_t = 0;
7aa09196
SA		 520 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
521 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
43cd72b9 522 return tie_t;
e0001a05
NC		 523}
524
43cd72b9 525static void
7aa09196 526Field_imm8_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
e0001a05 527{
43cd72b9 528 uint32 tie_t;
56fb3749 529 tie_t = (val << 28) >> 28;
7aa09196
SA		 530 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
531 tie_t = (val << 24) >> 28;
532 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
e0001a05
NC		 533}
534
43cd72b9 535static unsigned
7aa09196 536Field_s_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 537{
43cd72b9 538 unsigned tie_t = 0;
7aa09196 539 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
43cd72b9 540 return tie_t;
e0001a05
NC		 541}
542
43cd72b9 543static void
7aa09196 544Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 545{
43cd72b9 546 uint32 tie_t;
56fb3749 547 tie_t = (val << 28) >> 28;
7aa09196 548 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
e0001a05
NC		 549}
550
43cd72b9 551static unsigned
7aa09196 552Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 553{
43cd72b9 554 unsigned tie_t = 0;
7aa09196 555 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
43cd72b9 556 return tie_t;
e0001a05
NC		 557}
558
43cd72b9 559static void
7aa09196 560Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 561{
43cd72b9 562 uint32 tie_t;
7aa09196
SA		 563 tie_t = (val << 28) >> 28;
564 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
e0001a05
NC		 565}
566
43cd72b9 567static unsigned
7aa09196 568Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 569{
43cd72b9 570 unsigned tie_t = 0;
7aa09196 571 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
43cd72b9 572 return tie_t;
e0001a05
NC		 573}
574
43cd72b9 575static void
7aa09196 576Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
56fb3749
SA		 577{
578 uint32 tie_t;
7aa09196
SA		 579 tie_t = (val << 28) >> 28;
580 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
56fb3749
SA		 581}
582
583static unsigned
7aa09196 584Field_s_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
56fb3749
SA		 585{
586 unsigned tie_t = 0;
587 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
588 return tie_t;
589}
590
591static void
7aa09196 592Field_s_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
e0001a05 593{
43cd72b9
BW		 594 uint32 tie_t;
595 tie_t = (val << 28) >> 28;
56fb3749 596 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
e0001a05
NC		 597}
598
43cd72b9 599static unsigned
7aa09196 600Field_s_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
e0001a05 601{
43cd72b9 602 unsigned tie_t = 0;
56fb3749 603 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
43cd72b9 604 return tie_t;
e0001a05
NC		 605}
606
43cd72b9 607static void
7aa09196 608Field_s_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
e0001a05 609{
43cd72b9
BW		 610 uint32 tie_t;
611 tie_t = (val << 28) >> 28;
56fb3749 612 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
e0001a05
NC		 613}
614
43cd72b9 615static unsigned
7aa09196 616Field_s_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
e0001a05 617{
43cd72b9 618 unsigned tie_t = 0;
7aa09196 619 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
43cd72b9 620 return tie_t;
e0001a05
NC		 621}
622
43cd72b9 623static void
7aa09196 624Field_s_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
56fb3749
SA		 625{
626 uint32 tie_t;
7aa09196
SA		 627 tie_t = (val << 28) >> 28;
628 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
56fb3749
SA		 629}
630
631static unsigned
7aa09196 632Field_s_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
56fb3749
SA		 633{
634 unsigned tie_t = 0;
7aa09196 635 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
56fb3749
SA		 636 return tie_t;
637}
638
639static void
7aa09196 640Field_s_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
e0001a05 641{
43cd72b9
BW		 642 uint32 tie_t;
643 tie_t = (val << 28) >> 28;
7aa09196 644 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
e0001a05
NC		 645}
646
43cd72b9 647static unsigned
7aa09196 648Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
56fb3749
SA		 649{
650 unsigned tie_t = 0;
7aa09196
SA		 651 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
652 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
56fb3749
SA		 653 return tie_t;
654}
655
656static void
7aa09196 657Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
56fb3749
SA		 658{
659 uint32 tie_t;
7aa09196
SA		 660 tie_t = (val << 24) >> 24;
661 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
662 tie_t = (val << 20) >> 28;
663 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
56fb3749
SA		 664}
665
666static unsigned
7aa09196 667Field_imm12b_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
56fb3749
SA		 668{
669 unsigned tie_t = 0;
7aa09196
SA		 670 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
671 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24);
56fb3749
SA		 672 return tie_t;
673}
674
675static void
7aa09196 676Field_imm12b_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
56fb3749
SA		 677{
678 uint32 tie_t;
679 tie_t = (val << 24) >> 24;
7aa09196
SA		 680 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
681 tie_t = (val << 20) >> 28;
682 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
56fb3749
SA		 683}
684
685static unsigned
7aa09196 686Field_imm12b_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
e0001a05 687{
43cd72b9 688 unsigned tie_t = 0;
7aa09196 689 tie_t = (tie_t << 12) | ((insn[0] << 16) >> 20);
43cd72b9 690 return tie_t;
e0001a05
NC		 691}
692
43cd72b9 693static void
7aa09196 694Field_imm12b_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
e0001a05 695{
43cd72b9 696 uint32 tie_t;
7aa09196
SA		 697 tie_t = (val << 20) >> 20;
698 insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4);
e0001a05
NC		 699}
700
43cd72b9 701static unsigned
7aa09196 702Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 703{
43cd72b9 704 unsigned tie_t = 0;
7aa09196 705 tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
43cd72b9 706 return tie_t;
e0001a05
NC		 707}
708
43cd72b9 709static void
7aa09196 710Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 711{
43cd72b9 712 uint32 tie_t;
7aa09196
SA		 713 tie_t = (val << 16) >> 16;
714 insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
e0001a05
NC		 715}
716
43cd72b9 717static unsigned
7aa09196 718Field_imm16_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
e0001a05 719{
43cd72b9 720 unsigned tie_t = 0;
7aa09196 721 tie_t = (tie_t << 16) | ((insn[0] << 12) >> 16);
43cd72b9 722 return tie_t;
e0001a05
NC		 723}
724
43cd72b9 725static void
7aa09196 726Field_imm16_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
e0001a05 727{
43cd72b9 728 uint32 tie_t;
56fb3749 729 tie_t = (val << 16) >> 16;
7aa09196 730 insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4);
e0001a05
NC		 731}
732
43cd72b9 733static unsigned
7aa09196 734Field_m_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 735{
43cd72b9 736 unsigned tie_t = 0;
7aa09196 737 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
43cd72b9 738 return tie_t;
e0001a05
NC		 739}
740
43cd72b9 741static void
7aa09196 742Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 743{
43cd72b9 744 uint32 tie_t;
7aa09196
SA		 745 tie_t = (val << 30) >> 30;
746 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
e0001a05
NC		 747}
748
43cd72b9 749static unsigned
7aa09196 750Field_m_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
e0001a05 751{
43cd72b9 752 unsigned tie_t = 0;
7aa09196 753 tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30);
43cd72b9 754 return tie_t;
e0001a05
NC		 755}
756
43cd72b9 757static void
7aa09196 758Field_m_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
e0001a05 759{
43cd72b9 760 uint32 tie_t;
7aa09196
SA		 761 tie_t = (val << 30) >> 30;
762 insn[0] = (insn[0] & ~0xc) | (tie_t << 2);
e0001a05
NC		 763}
764
43cd72b9 765static unsigned
7aa09196 766Field_n_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 767{
43cd72b9 768 unsigned tie_t = 0;
7aa09196 769 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
43cd72b9 770 return tie_t;
e0001a05
NC		 771}
772
43cd72b9 773static void
7aa09196 774Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 775{
43cd72b9 776 uint32 tie_t;
7aa09196
SA		 777 tie_t = (val << 30) >> 30;
778 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
e0001a05
NC		 779}
780
43cd72b9 781static unsigned
7aa09196 782Field_n_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
e0001a05 783{
43cd72b9 784 unsigned tie_t = 0;
7aa09196 785 tie_t = (tie_t << 2) | ((insn[0] << 30) >> 30);
43cd72b9 786 return tie_t;
e0001a05
NC		 787}
788
43cd72b9 789static void
7aa09196 790Field_n_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
e0001a05 791{
43cd72b9 792 uint32 tie_t;
7aa09196
SA		 793 tie_t = (val << 30) >> 30;
794 insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
e0001a05
NC		 795}
796
43cd72b9 797static unsigned
7aa09196 798Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 799{
43cd72b9 800 unsigned tie_t = 0;
7aa09196 801 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
43cd72b9 802 return tie_t;
e0001a05
NC		 803}
804
43cd72b9 805static void
7aa09196 806Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 807{
43cd72b9 808 uint32 tie_t;
7aa09196
SA		 809 tie_t = (val << 14) >> 14;
810 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
e0001a05
NC		 811}
812
43cd72b9 813static unsigned
7aa09196 814Field_offset_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
e0001a05 815{
43cd72b9 816 unsigned tie_t = 0;
7aa09196 817 tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14);
43cd72b9 818 return tie_t;
e0001a05
NC		 819}
820
43cd72b9 821static void
7aa09196 822Field_offset_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
e0001a05 823{
43cd72b9 824 uint32 tie_t;
7aa09196
SA		 825 tie_t = (val << 14) >> 14;
826 insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0);
e0001a05
NC		 827}
828
43cd72b9 829static unsigned
7aa09196 830Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 831{
43cd72b9 832 unsigned tie_t = 0;
7aa09196 833 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
43cd72b9 834 return tie_t;
e0001a05
NC		 835}
836
43cd72b9 837static void
7aa09196 838Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 839{
43cd72b9
BW		 840 uint32 tie_t;
841 tie_t = (val << 28) >> 28;
7aa09196 842 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
e0001a05
NC		 843}
844
43cd72b9 845static unsigned
7aa09196 846Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 847{
43cd72b9 848 unsigned tie_t = 0;
7aa09196 849 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
43cd72b9 850 return tie_t;
e0001a05
NC		 851}
852
43cd72b9 853static void
7aa09196 854Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 855{
43cd72b9 856 uint32 tie_t;
7aa09196
SA		 857 tie_t = (val << 28) >> 28;
858 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
859}
e0001a05 860
43cd72b9 861static unsigned
7aa09196 862Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 863{
43cd72b9 864 unsigned tie_t = 0;
7aa09196 865 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
43cd72b9 866 return tie_t;
e0001a05
NC		 867}
868
43cd72b9 869static void
7aa09196 870Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
e0001a05 871{
43cd72b9
BW		 872 uint32 tie_t;
873 tie_t = (val << 28) >> 28;
7aa09196 874 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
e0001a05
NC		 875}
876
43cd72b9 877static unsigned
7aa09196 878Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 879{
43cd72b9 880 unsigned tie_t = 0;
7aa09196 881 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
43cd72b9 882 return tie_t;
e0001a05
NC		 883}
884
43cd72b9 885static void
7aa09196 886Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 887{
43cd72b9
BW		 888 uint32 tie_t;
889 tie_t = (val << 28) >> 28;
7aa09196 890 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
e0001a05
NC		 891}
892
43cd72b9 893static unsigned
7aa09196 894Field_op1_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
e0001a05 895{
43cd72b9 896 unsigned tie_t = 0;
7aa09196 897 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
43cd72b9 898 return tie_t;
e0001a05
NC		 899}
900
43cd72b9 901static void
7aa09196 902Field_op1_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
43cd72b9
BW		 903{
904 uint32 tie_t;
905 tie_t = (val << 28) >> 28;
7aa09196 906 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
43cd72b9 907}
e0001a05 908
43cd72b9 909static unsigned
7aa09196 910Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 911{
43cd72b9 912 unsigned tie_t = 0;
7aa09196 913 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
43cd72b9 914 return tie_t;
e0001a05
NC		 915}
916
43cd72b9 917static void
7aa09196 918Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 919{
43cd72b9
BW		 920 uint32 tie_t;
921 tie_t = (val << 28) >> 28;
7aa09196 922 insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
e0001a05
NC		 923}
924
43cd72b9 925static unsigned
7aa09196 926Field_op2_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
e0001a05 927{
43cd72b9 928 unsigned tie_t = 0;
7aa09196 929 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
43cd72b9 930 return tie_t;
e0001a05
NC		 931}
932
43cd72b9 933static void
7aa09196 934Field_op2_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
e0001a05 935{
43cd72b9
BW		 936 uint32 tie_t;
937 tie_t = (val << 28) >> 28;
7aa09196 938 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
e0001a05
NC		 939}
940
43cd72b9 941static unsigned
7aa09196 942Field_op2_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
e0001a05 943{
43cd72b9
BW		 944 unsigned tie_t = 0;
945 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
946 return tie_t;
e0001a05
NC		 947}
948
43cd72b9 949static void
7aa09196 950Field_op2_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
e0001a05 951{
43cd72b9
BW		 952 uint32 tie_t;
953 tie_t = (val << 28) >> 28;
954 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
e0001a05
NC		 955}
956
43cd72b9 957static unsigned
7aa09196 958Field_r_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 959{
43cd72b9 960 unsigned tie_t = 0;
7aa09196 961 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
43cd72b9 962 return tie_t;
e0001a05
NC		 963}
964
43cd72b9 965static void
7aa09196 966Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 967{
43cd72b9
BW		 968 uint32 tie_t;
969 tie_t = (val << 28) >> 28;
7aa09196 970 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
e0001a05
NC		 971}
972
43cd72b9 973static unsigned
7aa09196 974Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 975{
43cd72b9 976 unsigned tie_t = 0;
7aa09196 977 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
43cd72b9 978 return tie_t;
e0001a05
NC		 979}
980
43cd72b9 981static void
7aa09196 982Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 983{
43cd72b9
BW		 984 uint32 tie_t;
985 tie_t = (val << 28) >> 28;
7aa09196 986 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
e0001a05
NC		 987}
988
43cd72b9 989static unsigned
7aa09196 990Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 991{
43cd72b9 992 unsigned tie_t = 0;
7aa09196 993 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
43cd72b9 994 return tie_t;
e0001a05
NC		 995}
996
43cd72b9 997static void
7aa09196 998Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
e0001a05 999{
43cd72b9 1000 uint32 tie_t;
7aa09196
SA		 1001 tie_t = (val << 28) >> 28;
1002 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
e0001a05
NC		 1003}
1004
43cd72b9 1005static unsigned
7aa09196 1006Field_r_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
e0001a05 1007{
43cd72b9 1008 unsigned tie_t = 0;
7aa09196 1009 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
43cd72b9 1010 return tie_t;
e0001a05
NC		 1011}
1012
43cd72b9 1013static void
7aa09196 1014Field_r_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1015{
43cd72b9 1016 uint32 tie_t;
7aa09196
SA		 1017 tie_t = (val << 28) >> 28;
1018 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
e0001a05
NC		 1019}
1020
43cd72b9 1021static unsigned
7aa09196 1022Field_r_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
e0001a05 1023{
43cd72b9 1024 unsigned tie_t = 0;
7aa09196 1025 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
43cd72b9 1026 return tie_t;
e0001a05
NC		 1027}
1028
43cd72b9 1029static void
7aa09196 1030Field_r_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1031{
43cd72b9
BW		 1032 uint32 tie_t;
1033 tie_t = (val << 28) >> 28;
7aa09196 1034 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
e0001a05
NC		 1035}
1036
43cd72b9 1037static unsigned
7aa09196 1038Field_r_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
e0001a05 1039{
43cd72b9 1040 unsigned tie_t = 0;
7aa09196 1041 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
43cd72b9 1042 return tie_t;
e0001a05
NC		 1043}
1044
43cd72b9 1045static void
7aa09196 1046Field_r_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1047{
43cd72b9
BW		 1048 uint32 tie_t;
1049 tie_t = (val << 28) >> 28;
7aa09196 1050 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
e0001a05
NC		 1051}
1052
43cd72b9 1053static unsigned
7aa09196 1054Field_r_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
43cd72b9
BW		 1055{
1056 unsigned tie_t = 0;
7aa09196 1057 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
43cd72b9
BW		 1058 return tie_t;
1059}
e0001a05 1060
43cd72b9 1061static void
7aa09196 1062Field_r_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1063{
43cd72b9 1064 uint32 tie_t;
7aa09196
SA		 1065 tie_t = (val << 28) >> 28;
1066 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
e0001a05
NC		 1067}
1068
43cd72b9 1069static unsigned
7aa09196 1070Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 1071{
43cd72b9 1072 unsigned tie_t = 0;
7aa09196 1073 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
43cd72b9 1074 return tie_t;
e0001a05
NC		 1075}
1076
43cd72b9 1077static void
7aa09196 1078Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1079{
43cd72b9 1080 uint32 tie_t;
7aa09196
SA		 1081 tie_t = (val << 31) >> 31;
1082 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
e0001a05
NC		 1083}
1084
43cd72b9 1085static unsigned
7aa09196 1086Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 1087{
43cd72b9 1088 unsigned tie_t = 0;
7aa09196 1089 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
43cd72b9 1090 return tie_t;
e0001a05
NC		 1091}
1092
43cd72b9 1093static void
7aa09196 1094Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1095{
43cd72b9 1096 uint32 tie_t;
7aa09196
SA		 1097 tie_t = (val << 31) >> 31;
1098 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
e0001a05
NC		 1099}
1100
43cd72b9 1101static unsigned
7aa09196 1102Field_sae4_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
e0001a05 1103{
43cd72b9 1104 unsigned tie_t = 0;
7aa09196 1105 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
43cd72b9 1106 return tie_t;
e0001a05
NC		 1107}
1108
43cd72b9 1109static void
7aa09196 1110Field_sae4_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1111{
43cd72b9 1112 uint32 tie_t;
7aa09196
SA		 1113 tie_t = (val << 31) >> 31;
1114 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
e0001a05
NC		 1115}
1116
43cd72b9 1117static unsigned
7aa09196 1118Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 1119{
43cd72b9 1120 unsigned tie_t = 0;
7aa09196
SA		 1121 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
1122 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
43cd72b9 1123 return tie_t;
e0001a05
NC		 1124}
1125
43cd72b9 1126static void
7aa09196 1127Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1128{
43cd72b9 1129 uint32 tie_t;
7aa09196
SA		 1130 tie_t = (val << 28) >> 28;
1131 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1132 tie_t = (val << 27) >> 31;
1133 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
e0001a05
NC		 1134}
1135
43cd72b9 1136static unsigned
7aa09196 1137Field_sae_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
e0001a05 1138{
43cd72b9 1139 unsigned tie_t = 0;
7aa09196
SA		 1140 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
1141 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
43cd72b9 1142 return tie_t;
e0001a05
NC		 1143}
1144
43cd72b9 1145static void
7aa09196 1146Field_sae_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1147{
43cd72b9 1148 uint32 tie_t;
7aa09196
SA		 1149 tie_t = (val << 28) >> 28;
1150 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1151 tie_t = (val << 27) >> 31;
1152 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
e0001a05
NC		 1153}
1154
43cd72b9 1155static unsigned
7aa09196 1156Field_sae_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
e0001a05 1157{
43cd72b9 1158 unsigned tie_t = 0;
7aa09196 1159 tie_t = (tie_t << 5) | ((insn[0] << 15) >> 27);
43cd72b9 1160 return tie_t;
e0001a05
NC		 1161}
1162
43cd72b9 1163static void
7aa09196 1164Field_sae_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1165{
43cd72b9 1166 uint32 tie_t;
7aa09196
SA		 1167 tie_t = (val << 27) >> 27;
1168 insn[0] = (insn[0] & ~0x1f000) | (tie_t << 12);
e0001a05
NC		 1169}
1170
43cd72b9 1171static unsigned
7aa09196 1172Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 1173{
43cd72b9 1174 unsigned tie_t = 0;
7aa09196
SA		 1175 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
1176 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
43cd72b9 1177 return tie_t;
e0001a05
NC		 1178}
1179
43cd72b9 1180static void
7aa09196 1181Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1182{
43cd72b9
BW		 1183 uint32 tie_t;
1184 tie_t = (val << 28) >> 28;
7aa09196
SA		 1185 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1186 tie_t = (val << 27) >> 31;
1187 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
e0001a05
NC		 1188}
1189
43cd72b9 1190static unsigned
7aa09196 1191Field_sal_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
e0001a05 1192{
43cd72b9 1193 unsigned tie_t = 0;
7aa09196 1194 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
43cd72b9
BW		 1195 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1196 return tie_t;
e0001a05
NC		 1197}
1198
43cd72b9 1199static void
7aa09196 1200Field_sal_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1201{
43cd72b9
BW		 1202 uint32 tie_t;
1203 tie_t = (val << 28) >> 28;
1204 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
7aa09196
SA		 1205 tie_t = (val << 27) >> 31;
1206 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
e0001a05
NC		 1207}
1208
43cd72b9 1209static unsigned
7aa09196 1210Field_sal_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
e0001a05 1211{
43cd72b9 1212 unsigned tie_t = 0;
7aa09196 1213 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
43cd72b9
BW		 1214 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
1215 return tie_t;
e0001a05
NC		 1216}
1217
43cd72b9 1218static void
7aa09196 1219Field_sal_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1220{
43cd72b9
BW		 1221 uint32 tie_t;
1222 tie_t = (val << 28) >> 28;
1223 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
7aa09196
SA		 1224 tie_t = (val << 27) >> 31;
1225 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
e0001a05
NC		 1226}
1227
43cd72b9 1228static unsigned
7aa09196 1229Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 1230{
43cd72b9 1231 unsigned tie_t = 0;
7aa09196
SA		 1232 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
1233 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
43cd72b9 1234 return tie_t;
e0001a05
NC		 1235}
1236
43cd72b9 1237static void
7aa09196 1238Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1239{
43cd72b9
BW		 1240 uint32 tie_t;
1241 tie_t = (val << 28) >> 28;
7aa09196
SA		 1242 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1243 tie_t = (val << 27) >> 31;
1244 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
e0001a05
NC		 1245}
1246
33430bd0 1247static unsigned
7aa09196 1248Field_sargt_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
33430bd0
BW		 1249{
1250 unsigned tie_t = 0;
7aa09196
SA		 1251 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
1252 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
33430bd0
BW		 1253 return tie_t;
1254}
1255
1256static void
7aa09196 1257Field_sargt_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
33430bd0
BW		 1258{
1259 uint32 tie_t;
7aa09196
SA		 1260 tie_t = (val << 28) >> 28;
1261 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1262 tie_t = (val << 27) >> 31;
1263 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
33430bd0
BW		 1264}
1265
1266static unsigned
7aa09196 1267Field_sargt_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
33430bd0
BW		 1268{
1269 unsigned tie_t = 0;
7aa09196 1270 tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27);
33430bd0
BW		 1271 return tie_t;
1272}
1273
1274static void
7aa09196 1275Field_sargt_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
33430bd0
BW		 1276{
1277 uint32 tie_t;
7aa09196
SA		 1278 tie_t = (val << 27) >> 27;
1279 insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8);
33430bd0
BW		 1280}
1281
7aa09196
SA		 1282static unsigned
1283Field_sargt_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
e0001a05 1284{
7aa09196
SA		 1285 unsigned tie_t = 0;
1286 tie_t = (tie_t << 5) | ((insn[0] << 19) >> 27);
1287 return tie_t;
e0001a05
NC		 1288}
1289
7aa09196
SA		 1290static void
1291Field_sargt_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1292{
7aa09196
SA		 1293 uint32 tie_t;
1294 tie_t = (val << 27) >> 27;
1295 insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8);
e0001a05
NC		 1296}
1297
43cd72b9 1298static unsigned
7aa09196 1299Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 1300{
7aa09196
SA		 1301 unsigned tie_t = 0;
1302 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
1303 return tie_t;
e0001a05
NC		 1304}
1305
7aa09196
SA		 1306static void
1307Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1308{
7aa09196
SA		 1309 uint32 tie_t;
1310 tie_t = (val << 31) >> 31;
1311 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
e0001a05
NC		 1312}
1313
43cd72b9 1314static unsigned
7aa09196 1315Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 1316{
7aa09196
SA		 1317 unsigned tie_t = 0;
1318 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
1319 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1320 return tie_t;
e0001a05
NC		 1321}
1322
7aa09196
SA		 1323static void
1324Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1325{
7aa09196
SA		 1326 uint32 tie_t;
1327 tie_t = (val << 28) >> 28;
1328 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1329 tie_t = (val << 27) >> 31;
1330 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
e0001a05
NC		 1331}
1332
7aa09196
SA		 1333static unsigned
1334Field_sas_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
e0001a05 1335{
7aa09196
SA		 1336 unsigned tie_t = 0;
1337 tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
1338 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1339 return tie_t;
e0001a05
NC		 1340}
1341
7aa09196
SA		 1342static void
1343Field_sas_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1344{
7aa09196
SA		 1345 uint32 tie_t;
1346 tie_t = (val << 28) >> 28;
1347 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1348 tie_t = (val << 27) >> 31;
1349 insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
e0001a05
NC		 1350}
1351
7aa09196
SA		 1352static unsigned
1353Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 1354{
7aa09196
SA		 1355 unsigned tie_t = 0;
1356 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1357 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1358 return tie_t;
e0001a05
NC		 1359}
1360
7aa09196
SA		 1361static void
1362Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1363{
7aa09196
SA		 1364 uint32 tie_t;
1365 tie_t = (val << 28) >> 28;
1366 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1367 tie_t = (val << 24) >> 28;
1368 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
e0001a05
NC		 1369}
1370
7aa09196
SA		 1371static unsigned
1372Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 1373{
7aa09196
SA		 1374 unsigned tie_t = 0;
1375 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1376 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1377 return tie_t;
e0001a05
NC		 1378}
1379
7aa09196
SA		 1380static void
1381Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1382{
7aa09196
SA		 1383 uint32 tie_t;
1384 tie_t = (val << 28) >> 28;
1385 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1386 tie_t = (val << 24) >> 28;
1387 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
e0001a05
NC		 1388}
1389
7aa09196
SA		 1390static unsigned
1391Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 1392{
7aa09196
SA		 1393 unsigned tie_t = 0;
1394 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1395 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1396 return tie_t;
e0001a05
NC		 1397}
1398
7aa09196
SA		 1399static void
1400Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1401{
7aa09196
SA		 1402 uint32 tie_t;
1403 tie_t = (val << 28) >> 28;
1404 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
1405 tie_t = (val << 24) >> 28;
1406 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
e0001a05
NC		 1407}
1408
7aa09196
SA		 1409static unsigned
1410Field_st_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 1411{
7aa09196
SA		 1412 unsigned tie_t = 0;
1413 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1414 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1415 return tie_t;
e0001a05
NC		 1416}
1417
7aa09196
SA		 1418static void
1419Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1420{
7aa09196
SA		 1421 uint32 tie_t;
1422 tie_t = (val << 28) >> 28;
1423 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1424 tie_t = (val << 24) >> 28;
1425 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
e0001a05
NC		 1426}
1427
7aa09196
SA		 1428static unsigned
1429Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 1430{
7aa09196
SA		 1431 unsigned tie_t = 0;
1432 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1433 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1434 return tie_t;
e0001a05
NC		 1435}
1436
7aa09196
SA		 1437static void
1438Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
43cd72b9 1439{
7aa09196
SA		 1440 uint32 tie_t;
1441 tie_t = (val << 28) >> 28;
1442 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1443 tie_t = (val << 24) >> 28;
1444 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
43cd72b9 1445}
e0001a05 1446
7aa09196
SA		 1447static unsigned
1448Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 1449{
7aa09196
SA		 1450 unsigned tie_t = 0;
1451 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
1452 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
1453 return tie_t;
e0001a05
NC		 1454}
1455
7aa09196
SA		 1456static void
1457Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1458{
7aa09196
SA		 1459 uint32 tie_t;
1460 tie_t = (val << 28) >> 28;
1461 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
1462 tie_t = (val << 24) >> 28;
1463 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
e0001a05
NC		 1464}
1465
7aa09196
SA		 1466static unsigned
1467Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 1468{
7aa09196
SA		 1469 unsigned tie_t = 0;
1470 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
1471 return tie_t;
e0001a05
NC		 1472}
1473
7aa09196
SA		 1474static void
1475Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1476{
7aa09196
SA		 1477 uint32 tie_t;
1478 tie_t = (val << 29) >> 29;
1479 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
e0001a05
NC		 1480}
1481
7aa09196
SA		 1482static unsigned
1483Field_thi3_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
43cd72b9 1484{
7aa09196
SA		 1485 unsigned tie_t = 0;
1486 tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29);
1487 return tie_t;
e0001a05
NC		 1488}
1489
7aa09196
SA		 1490static void
1491Field_thi3_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1492{
7aa09196
SA		 1493 uint32 tie_t;
1494 tie_t = (val << 29) >> 29;
1495 insn[0] = (insn[0] & ~0xe) | (tie_t << 1);
e0001a05
NC		 1496}
1497
7aa09196
SA		 1498static unsigned
1499Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 1500{
7aa09196
SA		 1501 unsigned tie_t = 0;
1502 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1503 return tie_t;
e0001a05
NC		 1504}
1505
7aa09196
SA		 1506static void
1507Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1508{
7aa09196
SA		 1509 uint32 tie_t;
1510 tie_t = (val << 28) >> 28;
1511 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
e0001a05
NC		 1512}
1513
7aa09196
SA		 1514static unsigned
1515Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 1516{
7aa09196
SA		 1517 unsigned tie_t = 0;
1518 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1519 return tie_t;
e0001a05
NC		 1520}
1521
7aa09196
SA		 1522static void
1523Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
43cd72b9 1524{
7aa09196
SA		 1525 uint32 tie_t;
1526 tie_t = (val << 28) >> 28;
1527 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
43cd72b9 1528}
e0001a05 1529
7aa09196
SA		 1530static unsigned
1531Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 1532{
7aa09196
SA		 1533 unsigned tie_t = 0;
1534 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1535 return tie_t;
e0001a05
NC		 1536}
1537
7aa09196
SA		 1538static void
1539Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1540{
7aa09196
SA		 1541 uint32 tie_t;
1542 tie_t = (val << 28) >> 28;
1543 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
e0001a05
NC		 1544}
1545
7aa09196
SA		 1546static unsigned
1547Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 1548{
7aa09196
SA		 1549 unsigned tie_t = 0;
1550 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
1551 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1552 return tie_t;
e0001a05
NC		 1553}
1554
7aa09196
SA		 1555static void
1556Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1557{
7aa09196
SA		 1558 uint32 tie_t;
1559 tie_t = (val << 30) >> 30;
1560 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
1561 tie_t = (val << 28) >> 30;
1562 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
e0001a05
NC		 1563}
1564
7aa09196
SA		 1565static unsigned
1566Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 1567{
7aa09196
SA		 1568 unsigned tie_t = 0;
1569 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
1570 return tie_t;
e0001a05
NC		 1571}
1572
7aa09196
SA		 1573static void
1574Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1575{
7aa09196
SA		 1576 uint32 tie_t;
1577 tie_t = (val << 31) >> 31;
1578 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
e0001a05
NC		 1579}
1580
7aa09196
SA		 1581static unsigned
1582Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 1583{
7aa09196
SA		 1584 unsigned tie_t = 0;
1585 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
1586 return tie_t;
e0001a05
NC		 1587}
1588
7aa09196
SA		 1589static void
1590Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1591{
7aa09196
SA		 1592 uint32 tie_t;
1593 tie_t = (val << 31) >> 31;
1594 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
e0001a05
NC		 1595}
1596
7aa09196
SA		 1597static unsigned
1598Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 1599{
7aa09196
SA		 1600 unsigned tie_t = 0;
1601 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1602 return tie_t;
e0001a05
NC		 1603}
1604
7aa09196
SA		 1605static void
1606Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1607{
7aa09196
SA		 1608 uint32 tie_t;
1609 tie_t = (val << 28) >> 28;
1610 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
e0001a05
NC		 1611}
1612
7aa09196
SA		 1613static unsigned
1614Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 1615{
7aa09196
SA		 1616 unsigned tie_t = 0;
1617 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1618 return tie_t;
e0001a05
NC		 1619}
1620
7aa09196
SA		 1621static void
1622Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1623{
7aa09196
SA		 1624 uint32 tie_t;
1625 tie_t = (val << 28) >> 28;
1626 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
e0001a05
NC		 1627}
1628
7aa09196
SA		 1629static unsigned
1630Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 1631{
7aa09196
SA		 1632 unsigned tie_t = 0;
1633 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1634 return tie_t;
e0001a05
NC		 1635}
1636
7aa09196
SA		 1637static void
1638Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1639{
7aa09196
SA		 1640 uint32 tie_t;
1641 tie_t = (val << 30) >> 30;
1642 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
e0001a05
NC		 1643}
1644
7aa09196
SA		 1645static unsigned
1646Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 1647{
7aa09196
SA		 1648 unsigned tie_t = 0;
1649 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1650 return tie_t;
e0001a05
NC		 1651}
1652
7aa09196
SA		 1653static void
1654Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1655{
7aa09196
SA		 1656 uint32 tie_t;
1657 tie_t = (val << 30) >> 30;
1658 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
e0001a05
NC		 1659}
1660
7aa09196
SA		 1661static unsigned
1662Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 1663{
7aa09196
SA		 1664 unsigned tie_t = 0;
1665 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1666 return tie_t;
e0001a05
NC		 1667}
1668
7aa09196
SA		 1669static void
1670Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1671{
7aa09196
SA		 1672 uint32 tie_t;
1673 tie_t = (val << 28) >> 28;
1674 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
e0001a05
NC		 1675}
1676
7aa09196
SA		 1677static unsigned
1678Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 1679{
7aa09196
SA		 1680 unsigned tie_t = 0;
1681 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1682 return tie_t;
e0001a05
NC		 1683}
1684
7aa09196
SA		 1685static void
1686Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1687{
7aa09196
SA		 1688 uint32 tie_t;
1689 tie_t = (val << 28) >> 28;
1690 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
e0001a05
NC		 1691}
1692
7aa09196
SA		 1693static unsigned
1694Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 1695{
7aa09196
SA		 1696 unsigned tie_t = 0;
1697 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1698 return tie_t;
e0001a05
NC		 1699}
1700
7aa09196
SA		 1701static void
1702Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1703{
7aa09196
SA		 1704 uint32 tie_t;
1705 tie_t = (val << 29) >> 29;
1706 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
e0001a05
NC		 1707}
1708
7aa09196
SA		 1709static unsigned
1710Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 1711{
7aa09196
SA		 1712 unsigned tie_t = 0;
1713 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1714 return tie_t;
e0001a05
NC		 1715}
1716
7aa09196
SA		 1717static void
1718Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1719{
7aa09196
SA		 1720 uint32 tie_t;
1721 tie_t = (val << 29) >> 29;
1722 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
e0001a05
NC		 1723}
1724
7aa09196
SA		 1725static unsigned
1726Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 1727{
7aa09196
SA		 1728 unsigned tie_t = 0;
1729 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1730 return tie_t;
e0001a05
NC		 1731}
1732
7aa09196
SA		 1733static void
1734Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1735{
7aa09196
SA		 1736 uint32 tie_t;
1737 tie_t = (val << 31) >> 31;
1738 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
e0001a05
NC		 1739}
1740
7aa09196
SA		 1741static unsigned
1742Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 1743{
7aa09196
SA		 1744 unsigned tie_t = 0;
1745 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1746 return tie_t;
e0001a05
NC		 1747}
1748
7aa09196
SA		 1749static void
1750Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1751{
7aa09196
SA		 1752 uint32 tie_t;
1753 tie_t = (val << 31) >> 31;
1754 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
e0001a05
NC		 1755}
1756
7aa09196
SA		 1757static unsigned
1758Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 1759{
7aa09196
SA		 1760 unsigned tie_t = 0;
1761 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1762 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1763 return tie_t;
e0001a05
NC		 1764}
1765
7aa09196
SA		 1766static void
1767Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1768{
7aa09196
SA		 1769 uint32 tie_t;
1770 tie_t = (val << 28) >> 28;
1771 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1772 tie_t = (val << 26) >> 30;
1773 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
e0001a05
NC		 1774}
1775
7aa09196
SA		 1776static unsigned
1777Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 1778{
7aa09196
SA		 1779 unsigned tie_t = 0;
1780 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1781 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1782 return tie_t;
e0001a05
NC		 1783}
1784
7aa09196
SA		 1785static void
1786Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1787{
7aa09196
SA		 1788 uint32 tie_t;
1789 tie_t = (val << 28) >> 28;
1790 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1791 tie_t = (val << 26) >> 30;
1792 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
e0001a05
NC		 1793}
1794
7aa09196
SA		 1795static unsigned
1796Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
e0001a05 1797{
7aa09196
SA		 1798 unsigned tie_t = 0;
1799 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1800 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1801 return tie_t;
e0001a05
NC		 1802}
1803
7aa09196
SA		 1804static void
1805Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1806{
7aa09196
SA		 1807 uint32 tie_t;
1808 tie_t = (val << 28) >> 28;
1809 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1810 tie_t = (val << 25) >> 29;
1811 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
e0001a05
NC		 1812}
1813
7aa09196
SA		 1814static unsigned
1815Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
e0001a05 1816{
7aa09196
SA		 1817 unsigned tie_t = 0;
1818 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
1819 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
1820 return tie_t;
e0001a05
NC		 1821}
1822
7aa09196
SA		 1823static void
1824Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1825{
7aa09196
SA		 1826 uint32 tie_t;
1827 tie_t = (val << 28) >> 28;
1828 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
1829 tie_t = (val << 25) >> 29;
1830 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
e0001a05
NC		 1831}
1832
7aa09196
SA		 1833static unsigned
1834Field_imm7_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
e0001a05 1835{
7aa09196
SA		 1836 unsigned tie_t = 0;
1837 tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25);
1838 return tie_t;
e0001a05
NC		 1839}
1840
7aa09196
SA		 1841static void
1842Field_imm7_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1843{
7aa09196
SA		 1844 uint32 tie_t;
1845 tie_t = (val << 25) >> 25;
1846 insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
e0001a05
NC		 1847}
1848
7aa09196
SA		 1849static unsigned
1850Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 1851{
7aa09196
SA		 1852 unsigned tie_t = 0;
1853 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
1854 return tie_t;
e0001a05
NC		 1855}
1856
7aa09196
SA		 1857static void
1858Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1859{
7aa09196
SA		 1860 uint32 tie_t;
1861 tie_t = (val << 31) >> 31;
1862 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
e0001a05
NC		 1863}
1864
7aa09196
SA		 1865static unsigned
1866Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 1867{
7aa09196
SA		 1868 unsigned tie_t = 0;
1869 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1870 return tie_t;
e0001a05
NC		 1871}
1872
7aa09196
SA		 1873static void
1874Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1875{
7aa09196
SA		 1876 uint32 tie_t;
1877 tie_t = (val << 31) >> 31;
1878 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
e0001a05
NC		 1879}
1880
7aa09196
SA		 1881static unsigned
1882Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 1883{
7aa09196
SA		 1884 unsigned tie_t = 0;
1885 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
1886 return tie_t;
e0001a05
NC		 1887}
1888
7aa09196
SA		 1889static void
1890Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1891{
7aa09196
SA		 1892 uint32 tie_t;
1893 tie_t = (val << 30) >> 30;
1894 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
e0001a05
NC		 1895}
1896
7aa09196
SA		 1897static unsigned
1898Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
43cd72b9 1899{
7aa09196
SA		 1900 unsigned tie_t = 0;
1901 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
1902 return tie_t;
43cd72b9 1903}
e0001a05 1904
7aa09196
SA		 1905static void
1906Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
43cd72b9 1907{
7aa09196
SA		 1908 uint32 tie_t;
1909 tie_t = (val << 31) >> 31;
1910 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
43cd72b9 1911}
e0001a05 1912
7aa09196
SA		 1913static unsigned
1914Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
43cd72b9 1915{
7aa09196
SA		 1916 unsigned tie_t = 0;
1917 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1918 return tie_t;
43cd72b9 1919}
e0001a05 1920
7aa09196
SA		 1921static void
1922Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
43cd72b9 1923{
7aa09196
SA		 1924 uint32 tie_t;
1925 tie_t = (val << 31) >> 31;
1926 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
43cd72b9 1927}
e0001a05 1928
7aa09196
SA		 1929static unsigned
1930Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 1931{
7aa09196
SA		 1932 unsigned tie_t = 0;
1933 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
1934 return tie_t;
e0001a05
NC		 1935}
1936
7aa09196
SA		 1937static void
1938Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1939{
7aa09196
SA		 1940 uint32 tie_t;
1941 tie_t = (val << 30) >> 30;
1942 insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
e0001a05
NC		 1943}
1944
7aa09196
SA		 1945static unsigned
1946Field_w_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 1947{
7aa09196
SA		 1948 unsigned tie_t = 0;
1949 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
1950 return tie_t;
e0001a05
NC		 1951}
1952
7aa09196
SA		 1953static void
1954Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1955{
7aa09196
SA		 1956 uint32 tie_t;
1957 tie_t = (val << 30) >> 30;
1958 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
e0001a05
NC		 1959}
1960
7aa09196
SA		 1961static unsigned
1962Field_y_Slot_inst_get (const xtensa_insnbuf insn)
e0001a05 1963{
7aa09196
SA		 1964 unsigned tie_t = 0;
1965 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
1966 return tie_t;
e0001a05
NC		 1967}
1968
7aa09196
SA		 1969static void
1970Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
e0001a05 1971{
7aa09196
SA		 1972 uint32 tie_t;
1973 tie_t = (val << 31) >> 31;
1974 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
e0001a05
NC		 1975}
1976
7aa09196
SA		 1977static unsigned
1978Field_x_Slot_inst_get (const xtensa_insnbuf insn)
43cd72b9 1979{
7aa09196
SA		 1980 unsigned tie_t = 0;
1981 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
1982 return tie_t;
43cd72b9
BW		 1983}
1984
7aa09196
SA		 1985static void
1986Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
43cd72b9 1987{
7aa09196
SA		 1988 uint32 tie_t;
1989 tie_t = (val << 31) >> 31;
1990 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
43cd72b9
BW		 1991}
1992
7aa09196
SA		 1993static unsigned
1994Field_t2_Slot_inst_get (const xtensa_insnbuf insn)
43cd72b9 1995{
7aa09196
SA		 1996 unsigned tie_t = 0;
1997 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
1998 return tie_t;
43cd72b9
BW		 1999}
2000
7aa09196
SA		 2001static void
2002Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
43cd72b9 2003{
7aa09196
SA		 2004 uint32 tie_t;
2005 tie_t = (val << 29) >> 29;
2006 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
43cd72b9
BW		 2007}
2008
7aa09196
SA		 2009static unsigned
2010Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn)
43cd72b9 2011{
7aa09196
SA		 2012 unsigned tie_t = 0;
2013 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
2014 return tie_t;
43cd72b9
BW		 2015}
2016
7aa09196
SA		 2017static void
2018Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
33430bd0 2019{
7aa09196
SA		 2020 uint32 tie_t;
2021 tie_t = (val << 29) >> 29;
2022 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
33430bd0
BW		 2023}
2024
7aa09196
SA		 2025static unsigned
2026Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn)
33430bd0 2027{
7aa09196
SA		 2028 unsigned tie_t = 0;
2029 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
2030 return tie_t;
33430bd0
BW		 2031}
2032
7aa09196
SA		 2033static void
2034Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
33430bd0 2035{
7aa09196
SA		 2036 uint32 tie_t;
2037 tie_t = (val << 29) >> 29;
2038 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
33430bd0
BW		 2039}
2040
7aa09196
SA		 2041static unsigned
2042Field_s2_Slot_inst_get (const xtensa_insnbuf insn)
33430bd0 2043{
7aa09196
SA		 2044 unsigned tie_t = 0;
2045 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
2046 return tie_t;
33430bd0
BW		 2047}
2048
7aa09196
SA		 2049static void
2050Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
33430bd0 2051{
7aa09196
SA		 2052 uint32 tie_t;
2053 tie_t = (val << 29) >> 29;
2054 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
33430bd0
BW		 2055}
2056
7aa09196
SA		 2057static unsigned
2058Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn)
33430bd0 2059{
7aa09196
SA		 2060 unsigned tie_t = 0;
2061 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
2062 return tie_t;
33430bd0
BW		 2063}
2064
7aa09196
SA		 2065static void
2066Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
33430bd0 2067{
7aa09196
SA		 2068 uint32 tie_t;
2069 tie_t = (val << 29) >> 29;
2070 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
33430bd0
BW		 2071}
2072
7aa09196
SA		 2073static unsigned
2074Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn)
33430bd0 2075{
7aa09196
SA		 2076 unsigned tie_t = 0;
2077 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
2078 return tie_t;
33430bd0
BW		 2079}
2080
7aa09196
SA		 2081static void
2082Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
33430bd0 2083{
7aa09196
SA		 2084 uint32 tie_t;
2085 tie_t = (val << 29) >> 29;
2086 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
33430bd0
BW		 2087}
2088
7aa09196
SA		 2089static unsigned
2090Field_r2_Slot_inst_get (const xtensa_insnbuf insn)
33430bd0 2091{
7aa09196
SA		 2092 unsigned tie_t = 0;
2093 tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
2094 return tie_t;
33430bd0
BW		 2095}
2096
7aa09196
SA		 2097static void
2098Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2099{
2100 uint32 tie_t;
2101 tie_t = (val << 29) >> 29;
2102 insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
2103}
43cd72b9 2104
7aa09196
SA		 2105static unsigned
2106Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn)
2107{
2108 unsigned tie_t = 0;
2109 tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
2110 return tie_t;
2111}
43cd72b9 2112
7aa09196
SA		 2113static void
2114Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2115{
2116 uint32 tie_t;
2117 tie_t = (val << 29) >> 29;
2118 insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
2119}
43cd72b9 2120
7aa09196
SA		 2121static unsigned
2122Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn)
2123{
2124 unsigned tie_t = 0;
2125 tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
2126 return tie_t;
2127}
43cd72b9 2128
7aa09196
SA		 2129static void
2130Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2131{
2132 uint32 tie_t;
2133 tie_t = (val << 29) >> 29;
2134 insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
2135}
43cd72b9 2136
7aa09196
SA		 2137static unsigned
2138Field_t4_Slot_inst_get (const xtensa_insnbuf insn)
2139{
2140 unsigned tie_t = 0;
2141 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
2142 return tie_t;
2143}
e0001a05 2144
7aa09196
SA		 2145static void
2146Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2147{
2148 uint32 tie_t;
2149 tie_t = (val << 30) >> 30;
2150 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
2151}
e0001a05 2152
7aa09196
SA		 2153static unsigned
2154Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn)
2155{
2156 unsigned tie_t = 0;
2157 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
2158 return tie_t;
2159}
e0001a05 2160
7aa09196
SA		 2161static void
2162Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2163{
2164 uint32 tie_t;
2165 tie_t = (val << 30) >> 30;
2166 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
2167}
e0001a05 2168
7aa09196
SA		 2169static unsigned
2170Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn)
2171{
2172 unsigned tie_t = 0;
2173 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
2174 return tie_t;
2175}
e0001a05 2176
7aa09196
SA		 2177static void
2178Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2179{
2180 uint32 tie_t;
2181 tie_t = (val << 30) >> 30;
2182 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
2183}
e0001a05 2184
7aa09196
SA		 2185static unsigned
2186Field_s4_Slot_inst_get (const xtensa_insnbuf insn)
2187{
2188 unsigned tie_t = 0;
2189 tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
2190 return tie_t;
2191}
e0001a05 2192
7aa09196
SA		 2193static void
2194Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2195{
2196 uint32 tie_t;
2197 tie_t = (val << 30) >> 30;
2198 insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
2199}
e0001a05 2200
7aa09196
SA		 2201static unsigned
2202Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn)
2203{
2204 unsigned tie_t = 0;
2205 tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
2206 return tie_t;
2207}
e0001a05 2208
7aa09196
SA		 2209static void
2210Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2211{
2212 uint32 tie_t;
2213 tie_t = (val << 30) >> 30;
2214 insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
2215}
e0001a05 2216
7aa09196
SA		 2217static unsigned
2218Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn)
2219{
2220 unsigned tie_t = 0;
2221 tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
2222 return tie_t;
2223}
e0001a05 2224
7aa09196
SA		 2225static void
2226Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2227{
2228 uint32 tie_t;
2229 tie_t = (val << 30) >> 30;
2230 insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
2231}
e0001a05 2232
7aa09196
SA		 2233static unsigned
2234Field_r4_Slot_inst_get (const xtensa_insnbuf insn)
2235{
2236 unsigned tie_t = 0;
2237 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2238 return tie_t;
2239}
e0001a05 2240
7aa09196
SA		 2241static void
2242Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2243{
2244 uint32 tie_t;
2245 tie_t = (val << 30) >> 30;
2246 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2247}
e0001a05 2248
7aa09196
SA		 2249static unsigned
2250Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn)
2251{
2252 unsigned tie_t = 0;
2253 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2254 return tie_t;
2255}
e0001a05 2256
7aa09196
SA		 2257static void
2258Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2259{
2260 uint32 tie_t;
2261 tie_t = (val << 30) >> 30;
2262 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2263}
e0001a05 2264
7aa09196
SA		 2265static unsigned
2266Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn)
2267{
2268 unsigned tie_t = 0;
2269 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
2270 return tie_t;
2271}
e0001a05 2272
7aa09196
SA		 2273static void
2274Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2275{
2276 uint32 tie_t;
2277 tie_t = (val << 30) >> 30;
2278 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
2279}
e0001a05 2280
7aa09196
SA		 2281static unsigned
2282Field_t8_Slot_inst_get (const xtensa_insnbuf insn)
2283{
2284 unsigned tie_t = 0;
2285 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2286 return tie_t;
2287}
e0001a05 2288
7aa09196
SA		 2289static void
2290Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2291{
2292 uint32 tie_t;
2293 tie_t = (val << 31) >> 31;
2294 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2295}
074f5109 2296
7aa09196
SA		 2297static unsigned
2298Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn)
2299{
2300 unsigned tie_t = 0;
2301 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2302 return tie_t;
2303}
e0001a05 2304
7aa09196
SA		 2305static void
2306Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2307{
2308 uint32 tie_t;
2309 tie_t = (val << 31) >> 31;
2310 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2311}
074f5109 2312
7aa09196
SA		 2313static unsigned
2314Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn)
2315{
2316 unsigned tie_t = 0;
2317 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2318 return tie_t;
2319}
e0001a05 2320
7aa09196
SA		 2321static void
2322Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2323{
2324 uint32 tie_t;
2325 tie_t = (val << 31) >> 31;
2326 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2327}
e0001a05 2328
7aa09196
SA		 2329static unsigned
2330Field_s8_Slot_inst_get (const xtensa_insnbuf insn)
2331{
2332 unsigned tie_t = 0;
2333 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
2334 return tie_t;
2335}
e0001a05 2336
7aa09196
SA		 2337static void
2338Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2339{
2340 uint32 tie_t;
2341 tie_t = (val << 31) >> 31;
2342 insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
2343}
e0001a05 2344
7aa09196
SA		 2345static unsigned
2346Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn)
2347{
2348 unsigned tie_t = 0;
2349 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
2350 return tie_t;
2351}
e0001a05 2352
7aa09196
SA		 2353static void
2354Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2355{
2356 uint32 tie_t;
2357 tie_t = (val << 31) >> 31;
2358 insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
2359}
e0001a05 2360
7aa09196
SA		 2361static unsigned
2362Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn)
2363{
2364 unsigned tie_t = 0;
2365 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
2366 return tie_t;
2367}
e0001a05 2368
7aa09196
SA		 2369static void
2370Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2371{
2372 uint32 tie_t;
2373 tie_t = (val << 31) >> 31;
2374 insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
2375}
e0001a05 2376
7aa09196
SA		 2377static unsigned
2378Field_r8_Slot_inst_get (const xtensa_insnbuf insn)
2379{
2380 unsigned tie_t = 0;
2381 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
2382 return tie_t;
2383}
e0001a05 2384
7aa09196
SA		 2385static void
2386Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2387{
2388 uint32 tie_t;
2389 tie_t = (val << 31) >> 31;
2390 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
2391}
e0001a05 2392
7aa09196
SA		 2393static unsigned
2394Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn)
2395{
2396 unsigned tie_t = 0;
2397 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
2398 return tie_t;
2399}
e0001a05 2400
7aa09196
SA		 2401static void
2402Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
2403{
2404 uint32 tie_t;
2405 tie_t = (val << 31) >> 31;
2406 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
2407}
e0001a05 2408
7aa09196
SA		 2409static unsigned
2410Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn)
2411{
2412 unsigned tie_t = 0;
2413 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
2414 return tie_t;
2415}
e0001a05 2416
7aa09196
SA		 2417static void
2418Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
2419{
2420 uint32 tie_t;
2421 tie_t = (val << 31) >> 31;
2422 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
2423}
e0001a05 2424
7aa09196
SA		 2425static unsigned
2426Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
2427{
2428 unsigned tie_t = 0;
2429 tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
2430 return tie_t;
2431}
e0001a05 2432
7aa09196
SA		 2433static void
2434Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2435{
2436 uint32 tie_t;
2437 tie_t = (val << 17) >> 17;
2438 insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
2439}
e0001a05 2440
7aa09196
SA		 2441static unsigned
2442Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
2443{
2444 unsigned tie_t = 0;
2445 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
2446 return tie_t;
2447}
e0001a05 2448
7aa09196
SA		 2449static void
2450Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
2451{
2452 uint32 tie_t;
2453 tie_t = (val << 14) >> 14;
2454 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
2455}
e0001a05 2456
7aa09196
SA		 2457static unsigned
2458Field_xt_wbr18_imm_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
2459{
2460 unsigned tie_t = 0;
2461 tie_t = (tie_t << 18) | ((insn[0] << 6) >> 14);
2462 return tie_t;
2463}
e0001a05 2464
7aa09196
SA		 2465static void
2466Field_xt_wbr18_imm_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
2467{
2468 uint32 tie_t;
2469 tie_t = (val << 14) >> 14;
2470 insn[0] = (insn[0] & ~0x3ffff00) | (tie_t << 8);
2471}
33430bd0 2472
7aa09196
SA		 2473static unsigned
2474Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
2475{
2476 unsigned tie_t = 0;
2477 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
2478 return tie_t;
2479}
33430bd0 2480
7aa09196
SA		 2481static void
2482Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
2483{
2484 uint32 tie_t;
2485 tie_t = (val << 28) >> 28;
2486 insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
2487}
33430bd0 2488
7aa09196
SA		 2489static unsigned
2490Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
2491{
2492 unsigned tie_t = 0;
2493 tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
2494 return tie_t;
2495}
33430bd0 2496
7aa09196
SA		 2497static void
2498Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
2499{
2500 uint32 tie_t;
2501 tie_t = (val << 29) >> 29;
2502 insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
2503}
e0001a05 2504
7aa09196
SA		 2505static unsigned
2506Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
2507{
2508 unsigned tie_t = 0;
2509 tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
2510 return tie_t;
2511}
e0001a05 2512
7aa09196
SA		 2513static void
2514Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
2515{
2516 uint32 tie_t;
2517 tie_t = (val << 29) >> 29;
2518 insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
2519}
e0001a05 2520
7aa09196
SA		 2521static unsigned
2522Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
2523{
2524 unsigned tie_t = 0;
2525 tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
2526 return tie_t;
2527}
e0001a05 2528
7aa09196
SA		 2529static void
2530Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
2531{
2532 uint32 tie_t;
2533 tie_t = (val << 29) >> 29;
2534 insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
2535}
e0001a05 2536
7aa09196
SA		 2537static unsigned
2538Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
2539{
2540 unsigned tie_t = 0;
2541 tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
2542 return tie_t;
2543}
e0001a05 2544
7aa09196
SA		 2545static void
2546Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
2547{
2548 uint32 tie_t;
2549 tie_t = (val << 29) >> 29;
2550 insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
2551}
e0001a05 2552
7aa09196
SA		 2553static unsigned
2554Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
2555{
2556 unsigned tie_t = 0;
2557 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
2558 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
2559 return tie_t;
2560}
e0001a05 2561
7aa09196
SA		 2562static void
2563Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
2564{
2565 uint32 tie_t;
2566 tie_t = (val << 28) >> 28;
2567 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
2568 tie_t = (val << 24) >> 28;
2569 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
2570}
e0001a05 2571
7aa09196
SA		 2572static unsigned
2573Field_op0_s4_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2574{
2575 unsigned tie_t = 0;
2576 tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
2577 return tie_t;
2578}
e0001a05 2579
7aa09196
SA		 2580static void
2581Field_op0_s4_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2582{
2583 uint32 tie_t;
2584 tie_t = (val << 30) >> 30;
2585 insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
2586}
e0001a05 2587
7aa09196
SA		 2588static unsigned
2589Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2590{
2591 unsigned tie_t = 0;
2592 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
2593 return tie_t;
2594}
e0001a05 2595
7aa09196
SA		 2596static void
2597Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2598{
2599 uint32 tie_t;
2600 tie_t = (val << 28) >> 28;
2601 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
2602}
e0001a05 2603
7aa09196
SA		 2604static unsigned
2605Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2606{
2607 unsigned tie_t = 0;
2608 tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31);
2609 return tie_t;
2610}
e0001a05 2611
7aa09196
SA		 2612static void
2613Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2614{
2615 uint32 tie_t;
2616 tie_t = (val << 31) >> 31;
2617 insn[0] = (insn[0] & ~0x20000) | (tie_t << 17);
2618}
e0001a05 2619
7aa09196
SA		 2620static unsigned
2621Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2622{
2623 unsigned tie_t = 0;
2624 tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
2625 return tie_t;
2626}
e0001a05 2627
7aa09196
SA		 2628static void
2629Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2630{
2631 uint32 tie_t;
2632 tie_t = (val << 30) >> 30;
2633 insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
2634}
e0001a05 2635
7aa09196
SA		 2636static unsigned
2637Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2638{
2639 unsigned tie_t = 0;
2640 tie_t = (tie_t << 5) | ((insn[0] << 14) >> 27);
2641 return tie_t;
2642}
e0001a05 2643
7aa09196
SA		 2644static void
2645Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2646{
2647 uint32 tie_t;
2648 tie_t = (val << 27) >> 27;
2649 insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13);
2650}
e0001a05 2651
7aa09196
SA		 2652static unsigned
2653Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2654{
2655 unsigned tie_t = 0;
2656 tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
2657 return tie_t;
2658}
e0001a05 2659
7aa09196
SA		 2660static void
2661Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2662{
2663 uint32 tie_t;
2664 tie_t = (val << 26) >> 26;
2665 insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2666}
e0001a05 2667
7aa09196
SA		 2668static unsigned
2669Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2670{
2671 unsigned tie_t = 0;
2672 tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
2673 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
2674 return tie_t;
2675}
e0001a05 2676
7aa09196
SA		 2677static void
2678Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2679{
2680 uint32 tie_t;
2681 tie_t = (val << 29) >> 29;
2682 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
2683 tie_t = (val << 23) >> 26;
2684 insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2685}
e0001a05 2686
7aa09196
SA		 2687static unsigned
2688Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2689{
2690 unsigned tie_t = 0;
2691 tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
2692 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
2693 return tie_t;
2694}
e0001a05 2695
7aa09196
SA		 2696static void
2697Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2698{
2699 uint32 tie_t;
2700 tie_t = (val << 29) >> 29;
2701 insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
2702 tie_t = (val << 23) >> 26;
2703 insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2704}
e0001a05 2705
7aa09196
SA		 2706static unsigned
2707Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2708{
2709 unsigned tie_t = 0;
2710 tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
2711 tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
2712 return tie_t;
2713}
e0001a05 2714
7aa09196
SA		 2715static void
2716Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2717{
2718 uint32 tie_t;
2719 tie_t = (val << 30) >> 30;
2720 insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
2721 tie_t = (val << 24) >> 26;
2722 insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2723}
e0001a05 2724
7aa09196
SA		 2725static unsigned
2726Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2727{
2728 unsigned tie_t = 0;
2729 tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
2730 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
2731 return tie_t;
2732}
e0001a05 2733
7aa09196
SA		 2734static void
2735Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2736{
2737 uint32 tie_t;
2738 tie_t = (val << 31) >> 31;
2739 insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
2740 tie_t = (val << 25) >> 26;
2741 insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2742}
e0001a05 2743
7aa09196
SA		 2744static unsigned
2745Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2746{
2747 unsigned tie_t = 0;
2748 tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
2749 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
2750 return tie_t;
2751}
e0001a05 2752
7aa09196
SA		 2753static void
2754Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2755{
2756 uint32 tie_t;
2757 tie_t = (val << 30) >> 30;
2758 insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
2759 tie_t = (val << 24) >> 26;
2760 insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2761}
e0001a05 2762
7aa09196
SA		 2763static unsigned
2764Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2765{
2766 unsigned tie_t = 0;
2767 tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
2768 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
2769 return tie_t;
2770}
e0001a05 2771
7aa09196
SA		 2772static void
2773Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2774{
2775 uint32 tie_t;
2776 tie_t = (val << 30) >> 30;
2777 insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
2778 tie_t = (val << 24) >> 26;
2779 insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2780}
e0001a05 2781
7aa09196
SA		 2782static unsigned
2783Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2784{
2785 unsigned tie_t = 0;
2786 tie_t = (tie_t << 6) | ((insn[0] << 14) >> 26);
2787 tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31);
2788 return tie_t;
2789}
e0001a05 2790
7aa09196
SA		 2791static void
2792Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2793{
2794 uint32 tie_t;
2795 tie_t = (val << 31) >> 31;
2796 insn[0] = (insn[0] & ~0x200) | (tie_t << 9);
2797 tie_t = (val << 25) >> 26;
2798 insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
2799}
e0001a05 2800
7aa09196
SA		 2801static unsigned
2802Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2803{
2804 unsigned tie_t = 0;
2805 tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29);
2806 return tie_t;
2807}
e0001a05 2808
7aa09196
SA		 2809static void
2810Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2811{
2812 uint32 tie_t;
2813 tie_t = (val << 29) >> 29;
2814 insn[0] = (insn[0] & ~0x38000) | (tie_t << 15);
2815}
e0001a05 2816
7aa09196
SA		 2817static unsigned
2818Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2819{
2820 unsigned tie_t = 0;
2821 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2822 return tie_t;
2823}
e0001a05 2824
7aa09196
SA		 2825static void
2826Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2827{
2828 uint32 tie_t;
2829 tie_t = (val << 31) >> 31;
2830 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2831}
e0001a05 2832
7aa09196
SA		 2833static unsigned
2834Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2835{
2836 unsigned tie_t = 0;
2837 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2838 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2839 return tie_t;
2840}
e0001a05 2841
7aa09196
SA		 2842static void
2843Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2844{
2845 uint32 tie_t;
2846 tie_t = (val << 28) >> 28;
2847 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2848 tie_t = (val << 27) >> 31;
2849 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2850}
e0001a05 2851
7aa09196
SA		 2852static unsigned
2853Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2854{
2855 unsigned tie_t = 0;
2856 tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
2857 return tie_t;
2858}
e0001a05 2859
7aa09196
SA		 2860static void
2861Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2862{
2863 uint32 tie_t;
2864 tie_t = (val << 30) >> 30;
2865 insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
2866}
e0001a05 2867
7aa09196
SA		 2868static unsigned
2869Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2870{
2871 unsigned tie_t = 0;
2872 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27);
2873 tie_t = (tie_t << 6) | ((insn[0] << 26) >> 26);
2874 return tie_t;
2875}
e0001a05 2876
7aa09196
SA		 2877static void
2878Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2879{
2880 uint32 tie_t;
2881 tie_t = (val << 26) >> 26;
2882 insn[0] = (insn[0] & ~0x3f) | (tie_t << 0);
2883 tie_t = (val << 21) >> 27;
2884 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
2885}
e0001a05 2886
7aa09196
SA		 2887static unsigned
2888Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2889{
2890 unsigned tie_t = 0;
2891 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
2892 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
2893 return tie_t;
2894}
e0001a05 2895
7aa09196
SA		 2896static void
2897Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2898{
2899 uint32 tie_t;
2900 tie_t = (val << 28) >> 28;
2901 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
2902 tie_t = (val << 27) >> 31;
2903 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
2904}
e0001a05 2905
7aa09196
SA		 2906static unsigned
2907Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2908{
2909 unsigned tie_t = 0;
2910 tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
2911 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
2912 return tie_t;
2913}
e0001a05 2914
7aa09196
SA		 2915static void
2916Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2917{
2918 uint32 tie_t;
2919 tie_t = (val << 31) >> 31;
2920 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
2921 tie_t = (val << 29) >> 30;
2922 insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
2923}
e0001a05 2924
7aa09196
SA		 2925static unsigned
2926Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2927{
2928 unsigned tie_t = 0;
2929 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2930 tie_t = (tie_t << 5) | ((insn[0] << 27) >> 27);
2931 return tie_t;
2932}
e0001a05 2933
7aa09196
SA		 2934static void
2935Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2936{
2937 uint32 tie_t;
2938 tie_t = (val << 27) >> 27;
2939 insn[0] = (insn[0] & ~0x1f) | (tie_t << 0);
2940 tie_t = (val << 26) >> 31;
2941 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
2942}
e0001a05 2943
7aa09196
SA		 2944static unsigned
2945Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
2946{
2947 unsigned tie_t = 0;
2948 tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
2949 return tie_t;
2950}
e0001a05 2951
7aa09196
SA		 2952static void
2953Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
2954{
2955 uint32 tie_t;
2956 tie_t = (val << 29) >> 29;
2957 insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
2958}
e0001a05 2959
7aa09196
SA		 2960static unsigned
2961Field_op0_s5_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
2962{
2963 unsigned tie_t = 0;
2964 tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
2965 return tie_t;
2966}
e0001a05 2967
7aa09196
SA		 2968static void
2969Field_op0_s5_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
2970{
2971 uint32 tie_t;
2972 tie_t = (val << 29) >> 29;
2973 insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
2974}
e0001a05 2975
7aa09196
SA		 2976static unsigned
2977Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
2978{
2979 unsigned tie_t = 0;
2980 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
2981 return tie_t;
2982}
e0001a05 2983
7aa09196
SA		 2984static void
2985Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
2986{
2987 uint32 tie_t;
2988 tie_t = (val << 31) >> 31;
2989 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
2990}
e0001a05 2991
7aa09196
SA		 2992static unsigned
2993Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
2994{
2995 unsigned tie_t = 0;
2996 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
2997 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
2998 return tie_t;
2999}
e0001a05 3000
7aa09196
SA		 3001static void
3002Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3003{
3004 uint32 tie_t;
3005 tie_t = (val << 31) >> 31;
3006 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
3007 tie_t = (val << 30) >> 31;
3008 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
3009}
e0001a05 3010
7aa09196
SA		 3011static unsigned
3012Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3013{
3014 unsigned tie_t = 0;
3015 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
3016 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
3017 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
3018 return tie_t;
3019}
e0001a05 3020
7aa09196
SA		 3021static void
3022Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3023{
3024 uint32 tie_t;
3025 tie_t = (val << 31) >> 31;
3026 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
3027 tie_t = (val << 30) >> 31;
3028 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
3029 tie_t = (val << 29) >> 31;
3030 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
3031}
e0001a05 3032
7aa09196
SA		 3033static unsigned
3034Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3035{
3036 unsigned tie_t = 0;
3037 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
3038 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
3039 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
3040 return tie_t;
3041}
e0001a05 3042
7aa09196
SA		 3043static void
3044Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3045{
3046 uint32 tie_t;
3047 tie_t = (val << 31) >> 31;
3048 insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
3049 tie_t = (val << 30) >> 31;
3050 insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
3051 tie_t = (val << 29) >> 31;
3052 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
3053}
e0001a05 3054
7aa09196
SA		 3055static unsigned
3056Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3057{
3058 unsigned tie_t = 0;
3059 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
3060 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
3061 return tie_t;
3062}
e0001a05 3063
7aa09196
SA		 3064static void
3065Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3066{
3067 uint32 tie_t;
3068 tie_t = (val << 29) >> 29;
3069 insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
3070 tie_t = (val << 28) >> 31;
3071 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
3072}
e0001a05 3073
7aa09196
SA		 3074static unsigned
3075Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3076{
3077 unsigned tie_t = 0;
3078 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
3079 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
3080 return tie_t;
3081}
e0001a05 3082
7aa09196
SA		 3083static void
3084Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3085{
3086 uint32 tie_t;
3087 tie_t = (val << 29) >> 29;
3088 insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
3089 tie_t = (val << 28) >> 31;
3090 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
3091}
e0001a05 3092
7aa09196
SA		 3093static unsigned
3094Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3095{
3096 unsigned tie_t = 0;
3097 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
3098 tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30);
3099 return tie_t;
3100}
e0001a05 3101
7aa09196
SA		 3102static void
3103Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3104{
3105 uint32 tie_t;
3106 tie_t = (val << 30) >> 30;
3107 insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
3108 tie_t = (val << 29) >> 31;
3109 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
3110}
e0001a05 3111
7aa09196
SA		 3112static unsigned
3113Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3114{
3115 unsigned tie_t = 0;
3116 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
3117 tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
3118 return tie_t;
3119}
e0001a05 3120
7aa09196
SA		 3121static void
3122Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3123{
3124 uint32 tie_t;
3125 tie_t = (val << 31) >> 31;
3126 insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
3127 tie_t = (val << 30) >> 31;
3128 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
3129}
e0001a05 3130
7aa09196
SA		 3131static unsigned
3132Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3133{
3134 unsigned tie_t = 0;
3135 tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
3136 return tie_t;
3137}
e0001a05 3138
7aa09196
SA		 3139static void
3140Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3141{
3142 uint32 tie_t;
3143 tie_t = (val << 30) >> 30;
3144 insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
3145}
e0001a05 3146
7aa09196
SA		 3147static unsigned
3148Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3149{
3150 unsigned tie_t = 0;
3151 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
3152 return tie_t;
3153}
e0001a05 3154
7aa09196
SA		 3155static void
3156Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3157{
3158 uint32 tie_t;
3159 tie_t = (val << 31) >> 31;
3160 insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
3161}
e0001a05 3162
7aa09196
SA		 3163static unsigned
3164Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3165{
3166 unsigned tie_t = 0;
3167 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
3168 tie_t = (tie_t << 2) | ((insn[0] << 25) >> 30);
3169 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3170 return tie_t;
3171}
e0001a05 3172
7aa09196
SA		 3173static void
3174Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3175{
3176 uint32 tie_t;
3177 tie_t = (val << 28) >> 28;
3178 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3179 tie_t = (val << 26) >> 30;
3180 insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
3181 tie_t = (val << 22) >> 28;
3182 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
3183}
e0001a05 3184
7aa09196
SA		 3185static unsigned
3186Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3187{
3188 unsigned tie_t = 0;
3189 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
3190 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
3191 return tie_t;
3192}
074f5109 3193
7aa09196
SA		 3194static void
3195Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3196{
3197 uint32 tie_t;
3198 tie_t = (val << 31) >> 31;
3199 insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
3200 tie_t = (val << 30) >> 31;
3201 insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
3202}
33430bd0 3203
7aa09196
SA		 3204static unsigned
3205Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
3206{
3207 unsigned tie_t = 0;
3208 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
3209 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
3210 return tie_t;
3211}
33430bd0 3212
7aa09196
SA		 3213static void
3214Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
3215{
3216 uint32 tie_t;
3217 tie_t = (val << 30) >> 30;
3218 insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
3219 tie_t = (val << 29) >> 31;
3220 insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
3221}
e0001a05 3222
7aa09196
SA		 3223static unsigned
3224Field_op0_s6_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3225{
3226 unsigned tie_t = 0;
3227 tie_t = (tie_t << 5) | ((insn[0] << 0) >> 27);
3228 return tie_t;
3229}
074f5109 3230
7aa09196
SA		 3231static void
3232Field_op0_s6_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3233{
3234 uint32 tie_t;
3235 tie_t = (val << 27) >> 27;
3236 insn[0] = (insn[0] & ~0xf8000000) | (tie_t << 27);
3237}
e0001a05 3238
7aa09196
SA		 3239static unsigned
3240Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3241{
3242 unsigned tie_t = 0;
3243 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3244 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3245 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3246 return tie_t;
3247}
e0001a05 3248
7aa09196
SA		 3249static void
3250Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3251{
3252 uint32 tie_t;
3253 tie_t = (val << 28) >> 28;
3254 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3255 tie_t = (val << 27) >> 31;
3256 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3257 tie_t = (val << 24) >> 29;
3258 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3259}
e0001a05 3260
7aa09196
SA		 3261static unsigned
3262Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3263{
3264 unsigned tie_t = 0;
3265 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3266 return tie_t;
3267}
e0001a05 3268
7aa09196
SA		 3269static void
3270Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3271{
3272 uint32 tie_t;
3273 tie_t = (val << 29) >> 29;
3274 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3275}
e0001a05 3276
7aa09196
SA		 3277static unsigned
3278Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3279{
3280 unsigned tie_t = 0;
3281 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3282 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3283 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3284 return tie_t;
3285}
e0001a05 3286
7aa09196
SA		 3287static void
3288Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3289{
3290 uint32 tie_t;
3291 tie_t = (val << 28) >> 28;
3292 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3293 tie_t = (val << 27) >> 31;
3294 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3295 tie_t = (val << 24) >> 29;
3296 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3297}
e0001a05 3298
7aa09196
SA		 3299static unsigned
3300Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3301{
3302 unsigned tie_t = 0;
3303 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3304 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3305 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3306 return tie_t;
3307}
e0001a05 3308
7aa09196
SA		 3309static void
3310Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3311{
3312 uint32 tie_t;
3313 tie_t = (val << 28) >> 28;
3314 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3315 tie_t = (val << 27) >> 31;
3316 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3317 tie_t = (val << 24) >> 29;
3318 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3319}
e0001a05 3320
7aa09196
SA		 3321static unsigned
3322Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3323{
3324 unsigned tie_t = 0;
3325 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3326 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3327 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
3328 return tie_t;
3329}
e0001a05 3330
7aa09196
SA		 3331static void
3332Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3333{
3334 uint32 tie_t;
3335 tie_t = (val << 28) >> 28;
3336 insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
3337 tie_t = (val << 27) >> 31;
3338 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3339 tie_t = (val << 24) >> 29;
3340 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3341}
e0001a05 3342
7aa09196
SA		 3343static unsigned
3344Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3345{
3346 unsigned tie_t = 0;
3347 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3348 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3349 return tie_t;
3350}
e0001a05 3351
7aa09196
SA		 3352static void
3353Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3354{
3355 uint32 tie_t;
3356 tie_t = (val << 31) >> 31;
3357 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3358 tie_t = (val << 28) >> 29;
3359 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3360}
e0001a05 3361
7aa09196
SA		 3362static unsigned
3363Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3364{
3365 unsigned tie_t = 0;
3366 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3367 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3368 return tie_t;
3369}
e0001a05 3370
7aa09196
SA		 3371static void
3372Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3373{
3374 uint32 tie_t;
3375 tie_t = (val << 31) >> 31;
3376 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3377 tie_t = (val << 28) >> 29;
3378 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3379}
e0001a05 3380
7aa09196
SA		 3381static unsigned
3382Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3383{
3384 unsigned tie_t = 0;
3385 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3386 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3387 return tie_t;
3388}
e0001a05 3389
7aa09196
SA		 3390static void
3391Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3392{
3393 uint32 tie_t;
3394 tie_t = (val << 31) >> 31;
3395 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3396 tie_t = (val << 28) >> 29;
3397 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3398}
e0001a05 3399
7aa09196
SA		 3400static unsigned
3401Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3402{
3403 unsigned tie_t = 0;
3404 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3405 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3406 return tie_t;
3407}
e0001a05 3408
7aa09196
SA		 3409static void
3410Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3411{
3412 uint32 tie_t;
3413 tie_t = (val << 31) >> 31;
3414 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3415 tie_t = (val << 28) >> 29;
3416 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3417}
e0001a05 3418
7aa09196
SA		 3419static unsigned
3420Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3421{
3422 unsigned tie_t = 0;
3423 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3424 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3425 return tie_t;
3426}
e0001a05 3427
7aa09196
SA		 3428static void
3429Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3430{
3431 uint32 tie_t;
3432 tie_t = (val << 31) >> 31;
3433 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3434 tie_t = (val << 28) >> 29;
3435 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3436}
e0001a05 3437
7aa09196
SA		 3438static unsigned
3439Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3440{
3441 unsigned tie_t = 0;
3442 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3443 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3444 return tie_t;
3445}
e0001a05 3446
7aa09196
SA		 3447static void
3448Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3449{
3450 uint32 tie_t;
3451 tie_t = (val << 31) >> 31;
3452 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3453 tie_t = (val << 28) >> 29;
3454 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3455}
e0001a05 3456
7aa09196
SA		 3457static unsigned
3458Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3459{
3460 unsigned tie_t = 0;
3461 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3462 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3463 return tie_t;
3464}
e0001a05 3465
7aa09196
SA		 3466static void
3467Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3468{
3469 uint32 tie_t;
3470 tie_t = (val << 31) >> 31;
3471 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3472 tie_t = (val << 28) >> 29;
3473 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3474}
e0001a05 3475
7aa09196
SA		 3476static unsigned
3477Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3478{
3479 unsigned tie_t = 0;
3480 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3481 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3482 return tie_t;
3483}
e0001a05 3484
7aa09196
SA		 3485static void
3486Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3487{
3488 uint32 tie_t;
3489 tie_t = (val << 31) >> 31;
3490 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3491 tie_t = (val << 28) >> 29;
3492 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3493}
e0001a05 3494
7aa09196
SA		 3495static unsigned
3496Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3497{
3498 unsigned tie_t = 0;
3499 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3500 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3501 return tie_t;
3502}
e0001a05 3503
7aa09196
SA		 3504static void
3505Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3506{
3507 uint32 tie_t;
3508 tie_t = (val << 31) >> 31;
3509 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3510 tie_t = (val << 28) >> 29;
3511 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3512}
e0001a05 3513
7aa09196
SA		 3514static unsigned
3515Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3516{
3517 unsigned tie_t = 0;
3518 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3519 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3520 return tie_t;
3521}
e0001a05 3522
7aa09196
SA		 3523static void
3524Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3525{
3526 uint32 tie_t;
3527 tie_t = (val << 31) >> 31;
3528 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3529 tie_t = (val << 28) >> 29;
3530 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3531}
e0001a05 3532
7aa09196
SA		 3533static unsigned
3534Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3535{
3536 unsigned tie_t = 0;
3537 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3538 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3539 return tie_t;
3540}
e0001a05 3541
7aa09196
SA		 3542static void
3543Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3544{
3545 uint32 tie_t;
3546 tie_t = (val << 31) >> 31;
3547 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3548 tie_t = (val << 28) >> 29;
3549 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3550}
e0001a05 3551
7aa09196
SA		 3552static unsigned
3553Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3554{
3555 unsigned tie_t = 0;
3556 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3557 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3558 return tie_t;
3559}
e0001a05 3560
7aa09196
SA		 3561static void
3562Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3563{
3564 uint32 tie_t;
3565 tie_t = (val << 31) >> 31;
3566 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3567 tie_t = (val << 28) >> 29;
3568 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3569}
e0001a05 3570
7aa09196
SA		 3571static unsigned
3572Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3573{
3574 unsigned tie_t = 0;
3575 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3576 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3577 return tie_t;
3578}
e0001a05 3579
7aa09196
SA		 3580static void
3581Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3582{
3583 uint32 tie_t;
3584 tie_t = (val << 31) >> 31;
3585 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3586 tie_t = (val << 28) >> 29;
3587 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3588}
e0001a05 3589
7aa09196
SA		 3590static unsigned
3591Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3592{
3593 unsigned tie_t = 0;
3594 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3595 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3596 return tie_t;
3597}
e0001a05 3598
7aa09196
SA		 3599static void
3600Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3601{
3602 uint32 tie_t;
3603 tie_t = (val << 31) >> 31;
3604 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3605 tie_t = (val << 28) >> 29;
3606 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3607}
e0001a05 3608
7aa09196
SA		 3609static unsigned
3610Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3611{
3612 unsigned tie_t = 0;
3613 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3614 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3615 return tie_t;
3616}
e0001a05 3617
7aa09196
SA		 3618static void
3619Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3620{
3621 uint32 tie_t;
3622 tie_t = (val << 31) >> 31;
3623 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3624 tie_t = (val << 28) >> 29;
3625 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3626}
e0001a05 3627
7aa09196
SA		 3628static unsigned
3629Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3630{
3631 unsigned tie_t = 0;
3632 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3633 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3634 return tie_t;
3635}
e0001a05 3636
7aa09196
SA		 3637static void
3638Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3639{
3640 uint32 tie_t;
3641 tie_t = (val << 31) >> 31;
3642 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3643 tie_t = (val << 28) >> 29;
3644 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3645}
e0001a05 3646
7aa09196
SA		 3647static unsigned
3648Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3649{
3650 unsigned tie_t = 0;
3651 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3652 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3653 return tie_t;
3654}
e0001a05 3655
7aa09196
SA		 3656static void
3657Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3658{
3659 uint32 tie_t;
3660 tie_t = (val << 31) >> 31;
3661 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3662 tie_t = (val << 28) >> 29;
3663 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3664}
e0001a05 3665
7aa09196
SA		 3666static unsigned
3667Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3668{
3669 unsigned tie_t = 0;
3670 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3671 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31);
3672 return tie_t;
3673}
e0001a05 3674
7aa09196
SA		 3675static void
3676Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3677{
3678 uint32 tie_t;
3679 tie_t = (val << 31) >> 31;
3680 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
3681 tie_t = (val << 28) >> 29;
3682 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3683}
e0001a05 3684
7aa09196
SA		 3685static unsigned
3686Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
3687{
3688 unsigned tie_t = 0;
3689 tie_t = (tie_t << 3) | ((insn[1] << 29) >> 29);
3690 tie_t = (tie_t << 27) | ((insn[0] << 5) >> 5);
3691 return tie_t;
3692}
e0001a05 3693
7aa09196
SA		 3694static void
3695Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
3696{
3697 uint32 tie_t;
3698 tie_t = (val << 5) >> 5;
3699 insn[0] = (insn[0] & ~0x7ffffff) | (tie_t << 0);
3700 tie_t = (val << 2) >> 29;
3701 insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
3702}
e0001a05 3703
7aa09196
SA		 3704static unsigned
3705Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
3706{
3707 unsigned tie_t = 0;
3708 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
3709 return tie_t;
3710}
e0001a05 3711
7aa09196
SA		 3712static void
3713Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
3714{
3715 uint32 tie_t;
3716 tie_t = (val << 28) >> 28;
3717 insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
3718}
e0001a05 3719
7aa09196
SA		 3720static void
3721Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
3722 uint32 val ATTRIBUTE_UNUSED)
3723{
3724 /* Do nothing. */
3725}
e0001a05 3726
7aa09196
SA		 3727static unsigned
3728Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3729{
3730 return 0;
3731}
e0001a05 3732
7aa09196
SA		 3733static unsigned
3734Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3735{
3736 return 4;
3737}
e0001a05 3738
7aa09196
SA		 3739static unsigned
3740Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3741{
3742 return 8;
3743}
e0001a05 3744
7aa09196
SA		 3745static unsigned
3746Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3747{
3748 return 12;
3749}
e0001a05 3750
7aa09196
SA		 3751static unsigned
3752Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3753{
3754 return 0;
3755}
e0001a05 3756
7aa09196
SA		 3757static unsigned
3758Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3759{
3760 return 1;
3761}
e0001a05 3762
7aa09196
SA		 3763static unsigned
3764Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3765{
3766 return 2;
3767}
e0001a05 3768
7aa09196
SA		 3769static unsigned
3770Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3771{
3772 return 3;
3773}
e0001a05 3774
7aa09196
SA		 3775static unsigned
3776Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3777{
3778 return 0;
3779}
e0001a05 3780
7aa09196
SA		 3781static unsigned
3782Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3783{
3784 return 0;
3785}
e0001a05 3786
7aa09196
SA		 3787static unsigned
3788Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3789{
3790 return 0;
3791}
43cd72b9 3792
7aa09196
SA		 3793static unsigned
3794Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
3795{
3796 return 0;
3797}
43cd72b9 3798
7aa09196
SA		 3799\f
3800/* Functional units. */
43cd72b9 3801
7aa09196 3802static xtensa_funcUnit_internal funcUnits[] = {
43cd72b9 3803
43cd72b9
BW		 3804};
3805
7aa09196
SA		 3806\f
3807/* Register files. */
43cd72b9 3808
7aa09196
SA		 3809static xtensa_regfile_internal regfiles[] = {
3810 { "AR", "a", 0, 32, 64 },
3811 { "MR", "m", 1, 32, 4 },
3812 { "BR", "b", 2, 1, 16 },
3813 { "FR", "f", 3, 32, 16 },
3814 { "BR2", "b", 2, 2, 8 },
3815 { "BR4", "b", 2, 4, 4 },
3816 { "BR8", "b", 2, 8, 2 },
3817 { "BR16", "b", 2, 16, 1 }
43cd72b9
BW		 3818};
3819
7aa09196
SA		 3820\f
3821/* Interfaces. */
43cd72b9 3822
7aa09196 3823static xtensa_interface_internal interfaces[] = {
43cd72b9 3824
43cd72b9
BW		 3825};
3826
7aa09196
SA		 3827\f
3828/* Constant tables. */
43cd72b9 3829
7aa09196
SA		 3830/* constant table ai4c */
3831static const unsigned CONST_TBL_ai4c_0[] = {
3832 0xffffffff,
3833 0x1,
3834 0x2,
3835 0x3,
3836 0x4,
3837 0x5,
3838 0x6,
3839 0x7,
3840 0x8,
3841 0x9,
3842 0xa,
3843 0xb,
3844 0xc,
3845 0xd,
3846 0xe,
3847 0xf,
3848 0
43cd72b9
BW		 3849};
3850
7aa09196
SA		 3851/* constant table b4c */
3852static const unsigned CONST_TBL_b4c_0[] = {
3853 0xffffffff,
3854 0x1,
3855 0x2,
3856 0x3,
3857 0x4,
3858 0x5,
3859 0x6,
3860 0x7,
3861 0x8,
3862 0xa,
3863 0xc,
3864 0x10,
3865 0x20,
3866 0x40,
3867 0x80,
3868 0x100,
3869 0
43cd72b9
BW		 3870};
3871
7aa09196
SA		 3872/* constant table b4cu */
3873static const unsigned CONST_TBL_b4cu_0[] = {
3874 0x8000,
3875 0x10000,
3876 0x2,
3877 0x3,
3878 0x4,
3879 0x5,
3880 0x6,
3881 0x7,
3882 0x8,
3883 0xa,
3884 0xc,
3885 0x10,
3886 0x20,
3887 0x40,
3888 0x80,
3889 0x100,
3890 0
43cd72b9
BW		 3891};
3892
7aa09196
SA		 3893\f
3894/* Instruction operands. */
43cd72b9 3895
7aa09196
SA		 3896static int
3897Operand_soffsetx4_decode (uint32 *valp)
3898{
3899 unsigned soffsetx4_0, offset_0;
3900 offset_0 = *valp & 0x3ffff;
3901 soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
3902 *valp = soffsetx4_0;
3903 return 0;
3904}
43cd72b9 3905
7aa09196
SA		 3906static int
3907Operand_soffsetx4_encode (uint32 *valp)
3908{
3909 unsigned offset_0, soffsetx4_0;
3910 soffsetx4_0 = *valp;
3911 offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
3912 *valp = offset_0;
3913 return 0;
3914}
43cd72b9 3915
7aa09196
SA		 3916static int
3917Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
3918{
3919 *valp -= (pc & ~0x3);
3920 return 0;
3921}
43cd72b9 3922
7aa09196
SA		 3923static int
3924Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
3925{
3926 *valp += (pc & ~0x3);
3927 return 0;
3928}
43cd72b9 3929
7aa09196
SA		 3930static int
3931Operand_uimm12x8_decode (uint32 *valp)
3932{
3933 unsigned uimm12x8_0, imm12_0;
3934 imm12_0 = *valp & 0xfff;
3935 uimm12x8_0 = imm12_0 << 3;
3936 *valp = uimm12x8_0;
3937 return 0;
3938}
43cd72b9 3939
7aa09196
SA		 3940static int
3941Operand_uimm12x8_encode (uint32 *valp)
3942{
3943 unsigned imm12_0, uimm12x8_0;
3944 uimm12x8_0 = *valp;
3945 imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
3946 *valp = imm12_0;
3947 return 0;
3948}
43cd72b9 3949
7aa09196
SA		 3950static int
3951Operand_simm4_decode (uint32 *valp)
3952{
3953 unsigned simm4_0, mn_0;
3954 mn_0 = *valp & 0xf;
3955 simm4_0 = ((int) mn_0 << 28) >> 28;
3956 *valp = simm4_0;
3957 return 0;
3958}
43cd72b9 3959
7aa09196
SA		 3960static int
3961Operand_simm4_encode (uint32 *valp)
3962{
3963 unsigned mn_0, simm4_0;
3964 simm4_0 = *valp;
3965 mn_0 = (simm4_0 & 0xf);
3966 *valp = mn_0;
3967 return 0;
3968}
43cd72b9 3969
7aa09196
SA		 3970static int
3971Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
3972{
3973 return 0;
3974}
43cd72b9 3975
7aa09196
SA		 3976static int
3977Operand_arr_encode (uint32 *valp)
3978{
3979 int error;
3980 error = (*valp & ~0xf) != 0;
3981 return error;
3982}
43cd72b9 3983
7aa09196
SA		 3984static int
3985Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
3986{
3987 return 0;
3988}
43cd72b9 3989
7aa09196
SA		 3990static int
3991Operand_ars_encode (uint32 *valp)
3992{
3993 int error;
3994 error = (*valp & ~0xf) != 0;
3995 return error;
3996}
43cd72b9 3997
7aa09196
SA		 3998static int
3999Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
4000{
4001 return 0;
4002}
43cd72b9 4003
7aa09196
SA		 4004static int
4005Operand_art_encode (uint32 *valp)
4006{
4007 int error;
4008 error = (*valp & ~0xf) != 0;
4009 return error;
4010}
43cd72b9 4011
7aa09196
SA		 4012static int
4013Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
4014{
4015 return 0;
4016}
43cd72b9 4017
7aa09196
SA		 4018static int
4019Operand_ar0_encode (uint32 *valp)
4020{
4021 int error;
4022 error = (*valp & ~0x3f) != 0;
4023 return error;
4024}
43cd72b9 4025
7aa09196
SA		 4026static int
4027Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
4028{
4029 return 0;
4030}
43cd72b9 4031
7aa09196
SA		 4032static int
4033Operand_ar4_encode (uint32 *valp)
4034{
4035 int error;
4036 error = (*valp & ~0x3f) != 0;
4037 return error;
4038}
43cd72b9 4039
7aa09196
SA		 4040static int
4041Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
4042{
4043 return 0;
4044}
43cd72b9 4045
7aa09196
SA		 4046static int
4047Operand_ar8_encode (uint32 *valp)
4048{
4049 int error;
4050 error = (*valp & ~0x3f) != 0;
4051 return error;
4052}
43cd72b9 4053
7aa09196
SA		 4054static int
4055Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
4056{
4057 return 0;
4058}
43cd72b9 4059
7aa09196
SA		 4060static int
4061Operand_ar12_encode (uint32 *valp)
4062{
4063 int error;
4064 error = (*valp & ~0x3f) != 0;
4065 return error;
4066}
43cd72b9 4067
7aa09196
SA		 4068static int
4069Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
4070{
4071 return 0;
4072}
074f5109 4073
7aa09196
SA		 4074static int
4075Operand_ars_entry_encode (uint32 *valp)
4076{
4077 int error;
4078 error = (*valp & ~0x3f) != 0;
4079 return error;
4080}
43cd72b9 4081
7aa09196
SA		 4082static int
4083Operand_immrx4_decode (uint32 *valp)
4084{
4085 unsigned immrx4_0, r_0;
4086 r_0 = *valp & 0xf;
4087 immrx4_0 = (((0xfffffff) << 4) | r_0) << 2;
4088 *valp = immrx4_0;
4089 return 0;
4090}
33430bd0 4091
7aa09196
SA		 4092static int
4093Operand_immrx4_encode (uint32 *valp)
4094{
4095 unsigned r_0, immrx4_0;
4096 immrx4_0 = *valp;
4097 r_0 = ((immrx4_0 >> 2) & 0xf);
4098 *valp = r_0;
4099 return 0;
4100}
33430bd0 4101
7aa09196
SA		 4102static int
4103Operand_lsi4x4_decode (uint32 *valp)
4104{
4105 unsigned lsi4x4_0, r_0;
4106 r_0 = *valp & 0xf;
4107 lsi4x4_0 = r_0 << 2;
4108 *valp = lsi4x4_0;
4109 return 0;
4110}
33430bd0 4111
7aa09196
SA		 4112static int
4113Operand_lsi4x4_encode (uint32 *valp)
4114{
4115 unsigned r_0, lsi4x4_0;
4116 lsi4x4_0 = *valp;
4117 r_0 = ((lsi4x4_0 >> 2) & 0xf);
4118 *valp = r_0;
4119 return 0;
4120}
33430bd0 4121
7aa09196
SA		 4122static int
4123Operand_simm7_decode (uint32 *valp)
4124{
4125 unsigned simm7_0, imm7_0;
4126 imm7_0 = *valp & 0x7f;
4127 simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
4128 *valp = simm7_0;
4129 return 0;
4130}
33430bd0 4131
7aa09196
SA		 4132static int
4133Operand_simm7_encode (uint32 *valp)
4134{
4135 unsigned imm7_0, simm7_0;
4136 simm7_0 = *valp;
4137 imm7_0 = (simm7_0 & 0x7f);
4138 *valp = imm7_0;
4139 return 0;
4140}
33430bd0 4141
7aa09196
SA		 4142static int
4143Operand_uimm6_decode (uint32 *valp)
4144{
4145 unsigned uimm6_0, imm6_0;
4146 imm6_0 = *valp & 0x3f;
4147 uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
4148 *valp = uimm6_0;
4149 return 0;
4150}
33430bd0 4151
7aa09196
SA		 4152static int
4153Operand_uimm6_encode (uint32 *valp)
4154{
4155 unsigned imm6_0, uimm6_0;
4156 uimm6_0 = *valp;
4157 imm6_0 = (uimm6_0 - 0x4) & 0x3f;
4158 *valp = imm6_0;
4159 return 0;
4160}
33430bd0 4161
7aa09196
SA		 4162static int
4163Operand_uimm6_ator (uint32 *valp, uint32 pc)
4164{
4165 *valp -= pc;
4166 return 0;
4167}
33430bd0 4168
7aa09196
SA		 4169static int
4170Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
4171{
4172 *valp += pc;
4173 return 0;
4174}
33430bd0 4175
7aa09196
SA		 4176static int
4177Operand_ai4const_decode (uint32 *valp)
4178{
4179 unsigned ai4const_0, t_0;
4180 t_0 = *valp & 0xf;
4181 ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
4182 *valp = ai4const_0;
4183 return 0;
4184}
33430bd0 4185
7aa09196
SA		 4186static int
4187Operand_ai4const_encode (uint32 *valp)
4188{
4189 unsigned t_0, ai4const_0;
4190 ai4const_0 = *valp;
4191 switch (ai4const_0)
4192 {
4193 case 0xffffffff: t_0 = 0; break;
4194 case 0x1: t_0 = 0x1; break;
4195 case 0x2: t_0 = 0x2; break;
4196 case 0x3: t_0 = 0x3; break;
4197 case 0x4: t_0 = 0x4; break;
4198 case 0x5: t_0 = 0x5; break;
4199 case 0x6: t_0 = 0x6; break;
4200 case 0x7: t_0 = 0x7; break;
4201 case 0x8: t_0 = 0x8; break;
4202 case 0x9: t_0 = 0x9; break;
4203 case 0xa: t_0 = 0xa; break;
4204 case 0xb: t_0 = 0xb; break;
4205 case 0xc: t_0 = 0xc; break;
4206 case 0xd: t_0 = 0xd; break;
4207 case 0xe: t_0 = 0xe; break;
4208 default: t_0 = 0xf; break;
4209 }
4210 *valp = t_0;
4211 return 0;
4212}
33430bd0 4213
7aa09196
SA		 4214static int
4215Operand_b4const_decode (uint32 *valp)
4216{
4217 unsigned b4const_0, r_0;
4218 r_0 = *valp & 0xf;
4219 b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
4220 *valp = b4const_0;
4221 return 0;
4222}
33430bd0 4223
7aa09196
SA		 4224static int
4225Operand_b4const_encode (uint32 *valp)
4226{
4227 unsigned r_0, b4const_0;
4228 b4const_0 = *valp;
4229 switch (b4const_0)
4230 {
4231 case 0xffffffff: r_0 = 0; break;
4232 case 0x1: r_0 = 0x1; break;
4233 case 0x2: r_0 = 0x2; break;
4234 case 0x3: r_0 = 0x3; break;
4235 case 0x4: r_0 = 0x4; break;
4236 case 0x5: r_0 = 0x5; break;
4237 case 0x6: r_0 = 0x6; break;
4238 case 0x7: r_0 = 0x7; break;
4239 case 0x8: r_0 = 0x8; break;
4240 case 0xa: r_0 = 0x9; break;
4241 case 0xc: r_0 = 0xa; break;
4242 case 0x10: r_0 = 0xb; break;
4243 case 0x20: r_0 = 0xc; break;
4244 case 0x40: r_0 = 0xd; break;
4245 case 0x80: r_0 = 0xe; break;
4246 default: r_0 = 0xf; break;
4247 }
4248 *valp = r_0;
4249 return 0;
4250}
33430bd0 4251
7aa09196
SA		 4252static int
4253Operand_b4constu_decode (uint32 *valp)
4254{
4255 unsigned b4constu_0, r_0;
4256 r_0 = *valp & 0xf;
4257 b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
4258 *valp = b4constu_0;
4259 return 0;
4260}
33430bd0 4261
7aa09196
SA		 4262static int
4263Operand_b4constu_encode (uint32 *valp)
4264{
4265 unsigned r_0, b4constu_0;
4266 b4constu_0 = *valp;
4267 switch (b4constu_0)
4268 {
4269 case 0x8000: r_0 = 0; break;
4270 case 0x10000: r_0 = 0x1; break;
4271 case 0x2: r_0 = 0x2; break;
4272 case 0x3: r_0 = 0x3; break;
4273 case 0x4: r_0 = 0x4; break;
4274 case 0x5: r_0 = 0x5; break;
4275 case 0x6: r_0 = 0x6; break;
4276 case 0x7: r_0 = 0x7; break;
4277 case 0x8: r_0 = 0x8; break;
4278 case 0xa: r_0 = 0x9; break;
4279 case 0xc: r_0 = 0xa; break;
4280 case 0x10: r_0 = 0xb; break;
4281 case 0x20: r_0 = 0xc; break;
4282 case 0x40: r_0 = 0xd; break;
4283 case 0x80: r_0 = 0xe; break;
4284 default: r_0 = 0xf; break;
4285 }
4286 *valp = r_0;
4287 return 0;
4288}
33430bd0 4289
7aa09196
SA		 4290static int
4291Operand_uimm8_decode (uint32 *valp)
4292{
4293 unsigned uimm8_0, imm8_0;
4294 imm8_0 = *valp & 0xff;
4295 uimm8_0 = imm8_0;
4296 *valp = uimm8_0;
4297 return 0;
4298}
33430bd0 4299
7aa09196
SA		 4300static int
4301Operand_uimm8_encode (uint32 *valp)
4302{
4303 unsigned imm8_0, uimm8_0;
4304 uimm8_0 = *valp;
4305 imm8_0 = (uimm8_0 & 0xff);
4306 *valp = imm8_0;
4307 return 0;
4308}
33430bd0 4309
7aa09196
SA		 4310static int
4311Operand_uimm8x2_decode (uint32 *valp)
4312{
4313 unsigned uimm8x2_0, imm8_0;
4314 imm8_0 = *valp & 0xff;
4315 uimm8x2_0 = imm8_0 << 1;
4316 *valp = uimm8x2_0;
4317 return 0;
4318}
33430bd0 4319
7aa09196
SA		 4320static int
4321Operand_uimm8x2_encode (uint32 *valp)
4322{
4323 unsigned imm8_0, uimm8x2_0;
4324 uimm8x2_0 = *valp;
4325 imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
4326 *valp = imm8_0;
4327 return 0;
4328}
33430bd0 4329
7aa09196
SA		 4330static int
4331Operand_uimm8x4_decode (uint32 *valp)
4332{
4333 unsigned uimm8x4_0, imm8_0;
4334 imm8_0 = *valp & 0xff;
4335 uimm8x4_0 = imm8_0 << 2;
4336 *valp = uimm8x4_0;
4337 return 0;
4338}
33430bd0 4339
7aa09196
SA		 4340static int
4341Operand_uimm8x4_encode (uint32 *valp)
4342{
4343 unsigned imm8_0, uimm8x4_0;
4344 uimm8x4_0 = *valp;
4345 imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
4346 *valp = imm8_0;
4347 return 0;
4348}
33430bd0 4349
7aa09196
SA		 4350static int
4351Operand_uimm4x16_decode (uint32 *valp)
4352{
4353 unsigned uimm4x16_0, op2_0;
4354 op2_0 = *valp & 0xf;
4355 uimm4x16_0 = op2_0 << 4;
4356 *valp = uimm4x16_0;
4357 return 0;
4358}
33430bd0 4359
7aa09196
SA		 4360static int
4361Operand_uimm4x16_encode (uint32 *valp)
4362{
4363 unsigned op2_0, uimm4x16_0;
4364 uimm4x16_0 = *valp;
4365 op2_0 = ((uimm4x16_0 >> 4) & 0xf);
4366 *valp = op2_0;
4367 return 0;
4368}
33430bd0 4369
7aa09196
SA		 4370static int
4371Operand_simm8_decode (uint32 *valp)
4372{
4373 unsigned simm8_0, imm8_0;
4374 imm8_0 = *valp & 0xff;
4375 simm8_0 = ((int) imm8_0 << 24) >> 24;
4376 *valp = simm8_0;
4377 return 0;
4378}
33430bd0 4379
7aa09196
SA		 4380static int
4381Operand_simm8_encode (uint32 *valp)
4382{
4383 unsigned imm8_0, simm8_0;
4384 simm8_0 = *valp;
4385 imm8_0 = (simm8_0 & 0xff);
4386 *valp = imm8_0;
4387 return 0;
4388}
33430bd0 4389
7aa09196
SA		 4390static int
4391Operand_simm8x256_decode (uint32 *valp)
4392{
4393 unsigned simm8x256_0, imm8_0;
4394 imm8_0 = *valp & 0xff;
4395 simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
4396 *valp = simm8x256_0;
4397 return 0;
4398}
33430bd0 4399
7aa09196
SA		 4400static int
4401Operand_simm8x256_encode (uint32 *valp)
4402{
4403 unsigned imm8_0, simm8x256_0;
4404 simm8x256_0 = *valp;
4405 imm8_0 = ((simm8x256_0 >> 8) & 0xff);
4406 *valp = imm8_0;
4407 return 0;
4408}
33430bd0 4409
7aa09196
SA		 4410static int
4411Operand_simm12b_decode (uint32 *valp)
4412{
4413 unsigned simm12b_0, imm12b_0;
4414 imm12b_0 = *valp & 0xfff;
4415 simm12b_0 = ((int) imm12b_0 << 20) >> 20;
4416 *valp = simm12b_0;
4417 return 0;
4418}
33430bd0 4419
7aa09196
SA		 4420static int
4421Operand_simm12b_encode (uint32 *valp)
4422{
4423 unsigned imm12b_0, simm12b_0;
4424 simm12b_0 = *valp;
4425 imm12b_0 = (simm12b_0 & 0xfff);
4426 *valp = imm12b_0;
4427 return 0;
4428}
33430bd0 4429
7aa09196
SA		 4430static int
4431Operand_msalp32_decode (uint32 *valp)
4432{
4433 unsigned msalp32_0, sal_0;
4434 sal_0 = *valp & 0x1f;
4435 msalp32_0 = 0x20 - sal_0;
4436 *valp = msalp32_0;
4437 return 0;
4438}
33430bd0 4439
7aa09196
SA		 4440static int
4441Operand_msalp32_encode (uint32 *valp)
4442{
4443 unsigned sal_0, msalp32_0;
4444 msalp32_0 = *valp;
4445 sal_0 = (0x20 - msalp32_0) & 0x1f;
4446 *valp = sal_0;
4447 return 0;
4448}
33430bd0 4449
7aa09196
SA		 4450static int
4451Operand_op2p1_decode (uint32 *valp)
4452{
4453 unsigned op2p1_0, op2_0;
4454 op2_0 = *valp & 0xf;
4455 op2p1_0 = op2_0 + 0x1;
4456 *valp = op2p1_0;
4457 return 0;
4458}
33430bd0 4459
7aa09196
SA		 4460static int
4461Operand_op2p1_encode (uint32 *valp)
4462{
4463 unsigned op2_0, op2p1_0;
4464 op2p1_0 = *valp;
4465 op2_0 = (op2p1_0 - 0x1) & 0xf;
4466 *valp = op2_0;
4467 return 0;
4468}
33430bd0 4469
7aa09196
SA		 4470static int
4471Operand_label8_decode (uint32 *valp)
4472{
4473 unsigned label8_0, imm8_0;
4474 imm8_0 = *valp & 0xff;
4475 label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
4476 *valp = label8_0;
4477 return 0;
4478}
33430bd0 4479
7aa09196
SA		 4480static int
4481Operand_label8_encode (uint32 *valp)
4482{
4483 unsigned imm8_0, label8_0;
4484 label8_0 = *valp;
4485 imm8_0 = (label8_0 - 0x4) & 0xff;
4486 *valp = imm8_0;
4487 return 0;
4488}
33430bd0 4489
7aa09196
SA		 4490static int
4491Operand_label8_ator (uint32 *valp, uint32 pc)
4492{
4493 *valp -= pc;
4494 return 0;
4495}
33430bd0 4496
7aa09196
SA		 4497static int
4498Operand_label8_rtoa (uint32 *valp, uint32 pc)
4499{
4500 *valp += pc;
4501 return 0;
4502}
33430bd0 4503
7aa09196
SA		 4504static int
4505Operand_ulabel8_decode (uint32 *valp)
4506{
4507 unsigned ulabel8_0, imm8_0;
4508 imm8_0 = *valp & 0xff;
4509 ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
4510 *valp = ulabel8_0;
4511 return 0;
4512}
33430bd0 4513
7aa09196
SA		 4514static int
4515Operand_ulabel8_encode (uint32 *valp)
4516{
4517 unsigned imm8_0, ulabel8_0;
4518 ulabel8_0 = *valp;
4519 imm8_0 = (ulabel8_0 - 0x4) & 0xff;
4520 *valp = imm8_0;
4521 return 0;
4522}
33430bd0 4523
7aa09196
SA		 4524static int
4525Operand_ulabel8_ator (uint32 *valp, uint32 pc)
4526{
4527 *valp -= pc;
4528 return 0;
4529}
33430bd0 4530
7aa09196
SA		 4531static int
4532Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
4533{
4534 *valp += pc;
4535 return 0;
4536}
33430bd0 4537
7aa09196
SA		 4538static int
4539Operand_label12_decode (uint32 *valp)
4540{
4541 unsigned label12_0, imm12_0;
4542 imm12_0 = *valp & 0xfff;
4543 label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
4544 *valp = label12_0;
4545 return 0;
4546}
33430bd0 4547
7aa09196
SA		 4548static int
4549Operand_label12_encode (uint32 *valp)
4550{
4551 unsigned imm12_0, label12_0;
4552 label12_0 = *valp;
4553 imm12_0 = (label12_0 - 0x4) & 0xfff;
4554 *valp = imm12_0;
4555 return 0;
4556}
33430bd0 4557
7aa09196
SA		 4558static int
4559Operand_label12_ator (uint32 *valp, uint32 pc)
4560{
4561 *valp -= pc;
4562 return 0;
4563}
33430bd0 4564
7aa09196
SA		 4565static int
4566Operand_label12_rtoa (uint32 *valp, uint32 pc)
4567{
4568 *valp += pc;
4569 return 0;
4570}
33430bd0 4571
7aa09196
SA		 4572static int
4573Operand_soffset_decode (uint32 *valp)
4574{
4575 unsigned soffset_0, offset_0;
4576 offset_0 = *valp & 0x3ffff;
4577 soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
4578 *valp = soffset_0;
4579 return 0;
4580}
33430bd0 4581
7aa09196
SA		 4582static int
4583Operand_soffset_encode (uint32 *valp)
4584{
4585 unsigned offset_0, soffset_0;
4586 soffset_0 = *valp;
4587 offset_0 = (soffset_0 - 0x4) & 0x3ffff;
4588 *valp = offset_0;
4589 return 0;
4590}
33430bd0 4591
7aa09196
SA		 4592static int
4593Operand_soffset_ator (uint32 *valp, uint32 pc)
4594{
4595 *valp -= pc;
4596 return 0;
4597}
33430bd0 4598
7aa09196
SA		 4599static int
4600Operand_soffset_rtoa (uint32 *valp, uint32 pc)
4601{
4602 *valp += pc;
4603 return 0;
4604}
33430bd0 4605
7aa09196
SA		 4606static int
4607Operand_uimm16x4_decode (uint32 *valp)
4608{
4609 unsigned uimm16x4_0, imm16_0;
4610 imm16_0 = *valp & 0xffff;
4611 uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2;
4612 *valp = uimm16x4_0;
4613 return 0;
4614}
33430bd0 4615
7aa09196
SA		 4616static int
4617Operand_uimm16x4_encode (uint32 *valp)
4618{
4619 unsigned imm16_0, uimm16x4_0;
4620 uimm16x4_0 = *valp;
4621 imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
4622 *valp = imm16_0;
4623 return 0;
4624}
33430bd0 4625
7aa09196
SA		 4626static int
4627Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
4628{
4629 *valp -= ((pc + 3) & ~0x3);
4630 return 0;
4631}
33430bd0 4632
7aa09196
SA		 4633static int
4634Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
4635{
4636 *valp += ((pc + 3) & ~0x3);
4637 return 0;
4638}
33430bd0 4639
7aa09196
SA		 4640static int
4641Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED)
4642{
4643 return 0;
4644}
33430bd0 4645
7aa09196
SA		 4646static int
4647Operand_mx_encode (uint32 *valp)
4648{
4649 int error;
4650 error = (*valp & ~0x3) != 0;
4651 return error;
4652}
33430bd0 4653
7aa09196
SA		 4654static int
4655Operand_my_decode (uint32 *valp)
4656{
4657 *valp += 2;
4658 return 0;
4659}
33430bd0 4660
7aa09196
SA		 4661static int
4662Operand_my_encode (uint32 *valp)
4663{
4664 int error;
4665 error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
4666 *valp = *valp & 1;
4667 return error;
4668}
33430bd0 4669
7aa09196
SA		 4670static int
4671Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED)
4672{
4673 return 0;
4674}
33430bd0 4675
7aa09196
SA		 4676static int
4677Operand_mw_encode (uint32 *valp)
4678{
4679 int error;
4680 error = (*valp & ~0x3) != 0;
4681 return error;
4682}
33430bd0 4683
7aa09196
SA		 4684static int
4685Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED)
4686{
4687 return 0;
4688}
43cd72b9 4689
7aa09196
SA		 4690static int
4691Operand_mr0_encode (uint32 *valp)
4692{
4693 int error;
4694 error = (*valp & ~0x3) != 0;
4695 return error;
4696}
43cd72b9 4697
7aa09196
SA		 4698static int
4699Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED)
4700{
4701 return 0;
4702}
43cd72b9 4703
7aa09196
SA		 4704static int
4705Operand_mr1_encode (uint32 *valp)
4706{
4707 int error;
4708 error = (*valp & ~0x3) != 0;
4709 return error;
4710}
43cd72b9 4711
7aa09196
SA		 4712static int
4713Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED)
4714{
4715 return 0;
4716}
43cd72b9 4717
7aa09196
SA		 4718static int
4719Operand_mr2_encode (uint32 *valp)
4720{
4721 int error;
4722 error = (*valp & ~0x3) != 0;
4723 return error;
4724}
43cd72b9 4725
7aa09196
SA		 4726static int
4727Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED)
4728{
4729 return 0;
4730}
43cd72b9 4731
7aa09196
SA		 4732static int
4733Operand_mr3_encode (uint32 *valp)
4734{
4735 int error;
4736 error = (*valp & ~0x3) != 0;
4737 return error;
4738}
43cd72b9 4739
7aa09196
SA		 4740static int
4741Operand_immt_decode (uint32 *valp)
4742{
4743 unsigned immt_0, t_0;
4744 t_0 = *valp & 0xf;
4745 immt_0 = t_0;
4746 *valp = immt_0;
4747 return 0;
4748}
43cd72b9 4749
7aa09196
SA		 4750static int
4751Operand_immt_encode (uint32 *valp)
4752{
4753 unsigned t_0, immt_0;
4754 immt_0 = *valp;
4755 t_0 = immt_0 & 0xf;
4756 *valp = t_0;
4757 return 0;
4758}
43cd72b9 4759
7aa09196
SA		 4760static int
4761Operand_imms_decode (uint32 *valp)
4762{
4763 unsigned imms_0, s_0;
4764 s_0 = *valp & 0xf;
4765 imms_0 = s_0;
4766 *valp = imms_0;
4767 return 0;
4768}
43cd72b9 4769
7aa09196
SA		 4770static int
4771Operand_imms_encode (uint32 *valp)
4772{
4773 unsigned s_0, imms_0;
4774 imms_0 = *valp;
4775 s_0 = imms_0 & 0xf;
4776 *valp = s_0;
4777 return 0;
4778}
43cd72b9 4779
7aa09196
SA		 4780static int
4781Operand_bt_decode (uint32 *valp ATTRIBUTE_UNUSED)
4782{
4783 return 0;
4784}
43cd72b9 4785
7aa09196
SA		 4786static int
4787Operand_bt_encode (uint32 *valp)
4788{
4789 int error;
4790 error = (*valp & ~0xf) != 0;
4791 return error;
4792}
43cd72b9 4793
7aa09196
SA		 4794static int
4795Operand_bs_decode (uint32 *valp ATTRIBUTE_UNUSED)
4796{
4797 return 0;
4798}
43cd72b9 4799
7aa09196
SA		 4800static int
4801Operand_bs_encode (uint32 *valp)
4802{
4803 int error;
4804 error = (*valp & ~0xf) != 0;
4805 return error;
4806}
43cd72b9 4807
7aa09196
SA		 4808static int
4809Operand_br_decode (uint32 *valp ATTRIBUTE_UNUSED)
4810{
4811 return 0;
4812}
43cd72b9 4813
7aa09196
SA		 4814static int
4815Operand_br_encode (uint32 *valp)
4816{
4817 int error;
4818 error = (*valp & ~0xf) != 0;
4819 return error;
4820}
43cd72b9 4821
7aa09196
SA		 4822static int
4823Operand_bt2_decode (uint32 *valp)
4824{
4825 *valp = *valp << 1;
4826 return 0;
4827}
43cd72b9 4828
7aa09196
SA		 4829static int
4830Operand_bt2_encode (uint32 *valp)
4831{
4832 int error;
4833 error = (*valp & ~(0x7 << 1)) != 0;
4834 *valp = *valp >> 1;
4835 return error;
4836}
43cd72b9 4837
7aa09196
SA		 4838static int
4839Operand_bs2_decode (uint32 *valp)
4840{
4841 *valp = *valp << 1;
4842 return 0;
4843}
43cd72b9 4844
7aa09196
SA		 4845static int
4846Operand_bs2_encode (uint32 *valp)
4847{
4848 int error;
4849 error = (*valp & ~(0x7 << 1)) != 0;
4850 *valp = *valp >> 1;
4851 return error;
4852}
43cd72b9 4853
7aa09196
SA		 4854static int
4855Operand_br2_decode (uint32 *valp)
4856{
4857 *valp = *valp << 1;
4858 return 0;
4859}
43cd72b9 4860
7aa09196
SA		 4861static int
4862Operand_br2_encode (uint32 *valp)
4863{
4864 int error;
4865 error = (*valp & ~(0x7 << 1)) != 0;
4866 *valp = *valp >> 1;
4867 return error;
4868}
43cd72b9 4869
7aa09196
SA		 4870static int
4871Operand_bt4_decode (uint32 *valp)
4872{
4873 *valp = *valp << 2;
4874 return 0;
4875}
43cd72b9 4876
7aa09196
SA		 4877static int
4878Operand_bt4_encode (uint32 *valp)
4879{
4880 int error;
4881 error = (*valp & ~(0x3 << 2)) != 0;
4882 *valp = *valp >> 2;
4883 return error;
4884}
43cd72b9 4885
7aa09196
SA		 4886static int
4887Operand_bs4_decode (uint32 *valp)
4888{
4889 *valp = *valp << 2;
4890 return 0;
4891}
43cd72b9 4892
7aa09196
SA		 4893static int
4894Operand_bs4_encode (uint32 *valp)
4895{
4896 int error;
4897 error = (*valp & ~(0x3 << 2)) != 0;
4898 *valp = *valp >> 2;
4899 return error;
4900}
43cd72b9 4901
7aa09196
SA		 4902static int
4903Operand_br4_decode (uint32 *valp)
4904{
4905 *valp = *valp << 2;
4906 return 0;
4907}
43cd72b9 4908
7aa09196
SA		 4909static int
4910Operand_br4_encode (uint32 *valp)
4911{
4912 int error;
4913 error = (*valp & ~(0x3 << 2)) != 0;
4914 *valp = *valp >> 2;
4915 return error;
4916}
43cd72b9 4917
7aa09196
SA		 4918static int
4919Operand_bt8_decode (uint32 *valp)
4920{
4921 *valp = *valp << 3;
4922 return 0;
4923}
43cd72b9 4924
7aa09196
SA		 4925static int
4926Operand_bt8_encode (uint32 *valp)
4927{
4928 int error;
4929 error = (*valp & ~(0x1 << 3)) != 0;
4930 *valp = *valp >> 3;
4931 return error;
4932}
43cd72b9 4933
7aa09196
SA		 4934static int
4935Operand_bs8_decode (uint32 *valp)
4936{
4937 *valp = *valp << 3;
4938 return 0;
4939}
43cd72b9 4940
7aa09196
SA		 4941static int
4942Operand_bs8_encode (uint32 *valp)
4943{
4944 int error;
4945 error = (*valp & ~(0x1 << 3)) != 0;
4946 *valp = *valp >> 3;
4947 return error;
4948}
43cd72b9 4949
7aa09196
SA		 4950static int
4951Operand_br8_decode (uint32 *valp)
4952{
4953 *valp = *valp << 3;
4954 return 0;
4955}
43cd72b9 4956
7aa09196
SA		 4957static int
4958Operand_br8_encode (uint32 *valp)
4959{
4960 int error;
4961 error = (*valp & ~(0x1 << 3)) != 0;
4962 *valp = *valp >> 3;
4963 return error;
4964}
43cd72b9 4965
7aa09196
SA		 4966static int
4967Operand_bt16_decode (uint32 *valp)
4968{
4969 *valp = *valp << 4;
4970 return 0;
4971}
43cd72b9 4972
7aa09196
SA		 4973static int
4974Operand_bt16_encode (uint32 *valp)
4975{
4976 int error;
4977 error = (*valp & ~(0 << 4)) != 0;
4978 *valp = *valp >> 4;
4979 return error;
4980}
43cd72b9 4981
7aa09196
SA		 4982static int
4983Operand_bs16_decode (uint32 *valp)
4984{
4985 *valp = *valp << 4;
4986 return 0;
4987}
43cd72b9 4988
7aa09196
SA		 4989static int
4990Operand_bs16_encode (uint32 *valp)
4991{
4992 int error;
4993 error = (*valp & ~(0 << 4)) != 0;
4994 *valp = *valp >> 4;
4995 return error;
4996}
43cd72b9 4997
7aa09196
SA		 4998static int
4999Operand_br16_decode (uint32 *valp)
5000{
5001 *valp = *valp << 4;
5002 return 0;
5003}
43cd72b9 5004
7aa09196
SA		 5005static int
5006Operand_br16_encode (uint32 *valp)
5007{
5008 int error;
5009 error = (*valp & ~(0 << 4)) != 0;
5010 *valp = *valp >> 4;
5011 return error;
5012}
43cd72b9 5013
7aa09196
SA		 5014static int
5015Operand_brall_decode (uint32 *valp)
5016{
5017 *valp = *valp << 4;
5018 return 0;
5019}
43cd72b9 5020
7aa09196
SA		 5021static int
5022Operand_brall_encode (uint32 *valp)
5023{
5024 int error;
5025 error = (*valp & ~(0 << 4)) != 0;
5026 *valp = *valp >> 4;
5027 return error;
5028}
43cd72b9 5029
7aa09196
SA		 5030static int
5031Operand_tp7_decode (uint32 *valp)
5032{
5033 unsigned tp7_0, t_0;
5034 t_0 = *valp & 0xf;
5035 tp7_0 = t_0 + 0x7;
5036 *valp = tp7_0;
5037 return 0;
5038}
43cd72b9 5039
7aa09196
SA		 5040static int
5041Operand_tp7_encode (uint32 *valp)
5042{
5043 unsigned t_0, tp7_0;
5044 tp7_0 = *valp;
5045 t_0 = (tp7_0 - 0x7) & 0xf;
5046 *valp = t_0;
5047 return 0;
5048}
43cd72b9 5049
7aa09196
SA		 5050static int
5051Operand_xt_wbr15_label_decode (uint32 *valp)
5052{
5053 unsigned xt_wbr15_label_0, xt_wbr15_imm_0;
5054 xt_wbr15_imm_0 = *valp & 0x7fff;
5055 xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17);
5056 *valp = xt_wbr15_label_0;
5057 return 0;
5058}
43cd72b9 5059
7aa09196
SA		 5060static int
5061Operand_xt_wbr15_label_encode (uint32 *valp)
5062{
5063 unsigned xt_wbr15_imm_0, xt_wbr15_label_0;
5064 xt_wbr15_label_0 = *valp;
5065 xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
5066 *valp = xt_wbr15_imm_0;
5067 return 0;
5068}
43cd72b9 5069
7aa09196
SA		 5070static int
5071Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
5072{
5073 *valp -= pc;
5074 return 0;
5075}
43cd72b9 5076
7aa09196
SA		 5077static int
5078Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
5079{
5080 *valp += pc;
5081 return 0;
5082}
43cd72b9 5083
7aa09196
SA		 5084static int
5085Operand_xt_wbr18_label_decode (uint32 *valp)
5086{
5087 unsigned xt_wbr18_label_0, xt_wbr18_imm_0;
5088 xt_wbr18_imm_0 = *valp & 0x3ffff;
5089 xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14);
5090 *valp = xt_wbr18_label_0;
5091 return 0;
5092}
43cd72b9 5093
7aa09196
SA		 5094static int
5095Operand_xt_wbr18_label_encode (uint32 *valp)
5096{
5097 unsigned xt_wbr18_imm_0, xt_wbr18_label_0;
5098 xt_wbr18_label_0 = *valp;
5099 xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
5100 *valp = xt_wbr18_imm_0;
5101 return 0;
5102}
43cd72b9 5103
7aa09196
SA		 5104static int
5105Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
5106{
5107 *valp -= pc;
5108 return 0;
5109}
43cd72b9 5110
7aa09196
SA		 5111static int
5112Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
5113{
5114 *valp += pc;
5115 return 0;
5116}
43cd72b9 5117
7aa09196
SA		 5118static int
5119Operand_cimm8x4_decode (uint32 *valp)
5120{
5121 unsigned cimm8x4_0, imm8_0;
5122 imm8_0 = *valp & 0xff;
5123 cimm8x4_0 = (imm8_0 << 2) | 0;
5124 *valp = cimm8x4_0;
5125 return 0;
5126}
43cd72b9 5127
7aa09196
SA		 5128static int
5129Operand_cimm8x4_encode (uint32 *valp)
5130{
5131 unsigned imm8_0, cimm8x4_0;
5132 cimm8x4_0 = *valp;
5133 imm8_0 = (cimm8x4_0 >> 2) & 0xff;
5134 *valp = imm8_0;
5135 return 0;
5136}
43cd72b9 5137
7aa09196
SA		 5138static int
5139Operand_frr_decode (uint32 *valp ATTRIBUTE_UNUSED)
5140{
5141 return 0;
5142}
43cd72b9 5143
7aa09196
SA		 5144static int
5145Operand_frr_encode (uint32 *valp)
5146{
5147 int error;
5148 error = (*valp & ~0xf) != 0;
5149 return error;
5150}
43cd72b9 5151
7aa09196
SA		 5152static int
5153Operand_frs_decode (uint32 *valp ATTRIBUTE_UNUSED)
5154{
5155 return 0;
5156}
43cd72b9 5157
7aa09196
SA		 5158static int
5159Operand_frs_encode (uint32 *valp)
5160{
5161 int error;
5162 error = (*valp & ~0xf) != 0;
5163 return error;
5164}
43cd72b9 5165
7aa09196
SA		 5166static int
5167Operand_frt_decode (uint32 *valp ATTRIBUTE_UNUSED)
5168{
5169 return 0;
5170}
43cd72b9 5171
7aa09196
SA		 5172static int
5173Operand_frt_encode (uint32 *valp)
5174{
5175 int error;
5176 error = (*valp & ~0xf) != 0;
5177 return error;
5178}
43cd72b9 5179
7aa09196
SA		 5180static xtensa_operand_internal operands[] = {
5181 { "soffsetx4", 10, -1, 0,
5182 XTENSA_OPERAND_IS_PCRELATIVE,
5183 Operand_soffsetx4_encode, Operand_soffsetx4_decode,
5184 Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
5185 { "uimm12x8", 3, -1, 0,
5186 0,
5187 Operand_uimm12x8_encode, Operand_uimm12x8_decode,
5188 0, 0 },
5189 { "simm4", 26, -1, 0,
5190 0,
5191 Operand_simm4_encode, Operand_simm4_decode,
5192 0, 0 },
5193 { "arr", 14, 0, 1,
5194 XTENSA_OPERAND_IS_REGISTER,
5195 Operand_arr_encode, Operand_arr_decode,
5196 0, 0 },
5197 { "ars", 5, 0, 1,
5198 XTENSA_OPERAND_IS_REGISTER,
5199 Operand_ars_encode, Operand_ars_decode,
5200 0, 0 },
5201 { "*ars_invisible", 5, 0, 1,
5202 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5203 Operand_ars_encode, Operand_ars_decode,
5204 0, 0 },
5205 { "art", 0, 0, 1,
5206 XTENSA_OPERAND_IS_REGISTER,
5207 Operand_art_encode, Operand_art_decode,
5208 0, 0 },
5209 { "ar0", 123, 0, 1,
5210 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5211 Operand_ar0_encode, Operand_ar0_decode,
5212 0, 0 },
5213 { "ar4", 124, 0, 1,
5214 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5215 Operand_ar4_encode, Operand_ar4_decode,
5216 0, 0 },
5217 { "ar8", 125, 0, 1,
5218 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5219 Operand_ar8_encode, Operand_ar8_decode,
5220 0, 0 },
5221 { "ar12", 126, 0, 1,
5222 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5223 Operand_ar12_encode, Operand_ar12_decode,
5224 0, 0 },
5225 { "ars_entry", 5, 0, 1,
5226 XTENSA_OPERAND_IS_REGISTER,
5227 Operand_ars_entry_encode, Operand_ars_entry_decode,
5228 0, 0 },
5229 { "immrx4", 14, -1, 0,
5230 0,
5231 Operand_immrx4_encode, Operand_immrx4_decode,
5232 0, 0 },
5233 { "lsi4x4", 14, -1, 0,
5234 0,
5235 Operand_lsi4x4_encode, Operand_lsi4x4_decode,
5236 0, 0 },
5237 { "simm7", 34, -1, 0,
5238 0,
5239 Operand_simm7_encode, Operand_simm7_decode,
5240 0, 0 },
5241 { "uimm6", 33, -1, 0,
5242 XTENSA_OPERAND_IS_PCRELATIVE,
5243 Operand_uimm6_encode, Operand_uimm6_decode,
5244 Operand_uimm6_ator, Operand_uimm6_rtoa },
5245 { "ai4const", 0, -1, 0,
5246 0,
5247 Operand_ai4const_encode, Operand_ai4const_decode,
5248 0, 0 },
5249 { "b4const", 14, -1, 0,
5250 0,
5251 Operand_b4const_encode, Operand_b4const_decode,
5252 0, 0 },
5253 { "b4constu", 14, -1, 0,
5254 0,
5255 Operand_b4constu_encode, Operand_b4constu_decode,
5256 0, 0 },
5257 { "uimm8", 4, -1, 0,
5258 0,
5259 Operand_uimm8_encode, Operand_uimm8_decode,
5260 0, 0 },
5261 { "uimm8x2", 4, -1, 0,
5262 0,
5263 Operand_uimm8x2_encode, Operand_uimm8x2_decode,
5264 0, 0 },
5265 { "uimm8x4", 4, -1, 0,
5266 0,
5267 Operand_uimm8x4_encode, Operand_uimm8x4_decode,
5268 0, 0 },
5269 { "uimm4x16", 13, -1, 0,
5270 0,
5271 Operand_uimm4x16_encode, Operand_uimm4x16_decode,
5272 0, 0 },
5273 { "simm8", 4, -1, 0,
5274 0,
5275 Operand_simm8_encode, Operand_simm8_decode,
5276 0, 0 },
5277 { "simm8x256", 4, -1, 0,
5278 0,
5279 Operand_simm8x256_encode, Operand_simm8x256_decode,
5280 0, 0 },
5281 { "simm12b", 6, -1, 0,
5282 0,
5283 Operand_simm12b_encode, Operand_simm12b_decode,
5284 0, 0 },
5285 { "msalp32", 18, -1, 0,
5286 0,
5287 Operand_msalp32_encode, Operand_msalp32_decode,
5288 0, 0 },
5289 { "op2p1", 13, -1, 0,
5290 0,
5291 Operand_op2p1_encode, Operand_op2p1_decode,
5292 0, 0 },
5293 { "label8", 4, -1, 0,
5294 XTENSA_OPERAND_IS_PCRELATIVE,
5295 Operand_label8_encode, Operand_label8_decode,
5296 Operand_label8_ator, Operand_label8_rtoa },
5297 { "ulabel8", 4, -1, 0,
5298 XTENSA_OPERAND_IS_PCRELATIVE,
5299 Operand_ulabel8_encode, Operand_ulabel8_decode,
5300 Operand_ulabel8_ator, Operand_ulabel8_rtoa },
5301 { "label12", 3, -1, 0,
5302 XTENSA_OPERAND_IS_PCRELATIVE,
5303 Operand_label12_encode, Operand_label12_decode,
5304 Operand_label12_ator, Operand_label12_rtoa },
5305 { "soffset", 10, -1, 0,
5306 XTENSA_OPERAND_IS_PCRELATIVE,
5307 Operand_soffset_encode, Operand_soffset_decode,
5308 Operand_soffset_ator, Operand_soffset_rtoa },
5309 { "uimm16x4", 7, -1, 0,
5310 XTENSA_OPERAND_IS_PCRELATIVE,
5311 Operand_uimm16x4_encode, Operand_uimm16x4_decode,
5312 Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
5313 { "mx", 43, 1, 1,
5314 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
5315 Operand_mx_encode, Operand_mx_decode,
5316 0, 0 },
5317 { "my", 42, 1, 1,
5318 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
5319 Operand_my_encode, Operand_my_decode,
5320 0, 0 },
5321 { "mw", 41, 1, 1,
5322 XTENSA_OPERAND_IS_REGISTER,
5323 Operand_mw_encode, Operand_mw_decode,
5324 0, 0 },
5325 { "mr0", 127, 1, 1,
5326 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5327 Operand_mr0_encode, Operand_mr0_decode,
5328 0, 0 },
5329 { "mr1", 128, 1, 1,
5330 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5331 Operand_mr1_encode, Operand_mr1_decode,
5332 0, 0 },
5333 { "mr2", 129, 1, 1,
5334 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5335 Operand_mr2_encode, Operand_mr2_decode,
5336 0, 0 },
5337 { "mr3", 130, 1, 1,
5338 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5339 Operand_mr3_encode, Operand_mr3_decode,
5340 0, 0 },
5341 { "immt", 0, -1, 0,
5342 0,
5343 Operand_immt_encode, Operand_immt_decode,
5344 0, 0 },
5345 { "imms", 5, -1, 0,
5346 0,
5347 Operand_imms_encode, Operand_imms_decode,
5348 0, 0 },
5349 { "bt", 0, 2, 1,
5350 XTENSA_OPERAND_IS_REGISTER,
5351 Operand_bt_encode, Operand_bt_decode,
5352 0, 0 },
5353 { "bs", 5, 2, 1,
5354 XTENSA_OPERAND_IS_REGISTER,
5355 Operand_bs_encode, Operand_bs_decode,
5356 0, 0 },
5357 { "br", 14, 2, 1,
5358 XTENSA_OPERAND_IS_REGISTER,
5359 Operand_br_encode, Operand_br_decode,
5360 0, 0 },
5361 { "bt2", 44, 2, 2,
5362 XTENSA_OPERAND_IS_REGISTER,
5363 Operand_bt2_encode, Operand_bt2_decode,
5364 0, 0 },
5365 { "bs2", 45, 2, 2,
5366 XTENSA_OPERAND_IS_REGISTER,
5367 Operand_bs2_encode, Operand_bs2_decode,
5368 0, 0 },
5369 { "br2", 46, 2, 2,
5370 XTENSA_OPERAND_IS_REGISTER,
5371 Operand_br2_encode, Operand_br2_decode,
5372 0, 0 },
5373 { "bt4", 47, 2, 4,
5374 XTENSA_OPERAND_IS_REGISTER,
5375 Operand_bt4_encode, Operand_bt4_decode,
5376 0, 0 },
5377 { "bs4", 48, 2, 4,
5378 XTENSA_OPERAND_IS_REGISTER,
5379 Operand_bs4_encode, Operand_bs4_decode,
5380 0, 0 },
5381 { "br4", 49, 2, 4,
5382 XTENSA_OPERAND_IS_REGISTER,
5383 Operand_br4_encode, Operand_br4_decode,
5384 0, 0 },
5385 { "bt8", 50, 2, 8,
5386 XTENSA_OPERAND_IS_REGISTER,
5387 Operand_bt8_encode, Operand_bt8_decode,
5388 0, 0 },
5389 { "bs8", 51, 2, 8,
5390 XTENSA_OPERAND_IS_REGISTER,
5391 Operand_bs8_encode, Operand_bs8_decode,
5392 0, 0 },
5393 { "br8", 52, 2, 8,
5394 XTENSA_OPERAND_IS_REGISTER,
5395 Operand_br8_encode, Operand_br8_decode,
5396 0, 0 },
5397 { "bt16", 131, 2, 16,
5398 XTENSA_OPERAND_IS_REGISTER,
5399 Operand_bt16_encode, Operand_bt16_decode,
5400 0, 0 },
5401 { "bs16", 132, 2, 16,
5402 XTENSA_OPERAND_IS_REGISTER,
5403 Operand_bs16_encode, Operand_bs16_decode,
5404 0, 0 },
5405 { "br16", 133, 2, 16,
5406 XTENSA_OPERAND_IS_REGISTER,
5407 Operand_br16_encode, Operand_br16_decode,
5408 0, 0 },
5409 { "brall", 134, 2, 16,
5410 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
5411 Operand_brall_encode, Operand_brall_decode,
5412 0, 0 },
5413 { "tp7", 0, -1, 0,
5414 0,
5415 Operand_tp7_encode, Operand_tp7_decode,
5416 0, 0 },
5417 { "xt_wbr15_label", 53, -1, 0,
5418 XTENSA_OPERAND_IS_PCRELATIVE,
5419 Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode,
5420 Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
5421 { "xt_wbr18_label", 54, -1, 0,
5422 XTENSA_OPERAND_IS_PCRELATIVE,
5423 Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode,
5424 Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
5425 { "cimm8x4", 4, -1, 0,
5426 0,
5427 Operand_cimm8x4_encode, Operand_cimm8x4_decode,
5428 0, 0 },
5429 { "frr", 14, 3, 1,
5430 XTENSA_OPERAND_IS_REGISTER,
5431 Operand_frr_encode, Operand_frr_decode,
5432 0, 0 },
5433 { "frs", 5, 3, 1,
5434 XTENSA_OPERAND_IS_REGISTER,
5435 Operand_frs_encode, Operand_frs_decode,
5436 0, 0 },
5437 { "frt", 0, 3, 1,
5438 XTENSA_OPERAND_IS_REGISTER,
5439 Operand_frt_encode, Operand_frt_decode,
5440 0, 0 },
5441 { "t", 0, -1, 0, 0, 0, 0, 0, 0 },
5442 { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 },
5443 { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 },
5444 { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 },
5445 { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 },
5446 { "s", 5, -1, 0, 0, 0, 0, 0, 0 },
5447 { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 },
5448 { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 },
5449 { "m", 8, -1, 0, 0, 0, 0, 0, 0 },
5450 { "n", 9, -1, 0, 0, 0, 0, 0, 0 },
5451 { "offset", 10, -1, 0, 0, 0, 0, 0, 0 },
5452 { "op0", 11, -1, 0, 0, 0, 0, 0, 0 },
5453 { "op1", 12, -1, 0, 0, 0, 0, 0, 0 },
5454 { "op2", 13, -1, 0, 0, 0, 0, 0, 0 },
5455 { "r", 14, -1, 0, 0, 0, 0, 0, 0 },
5456 { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 },
5457 { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 },
5458 { "sae", 17, -1, 0, 0, 0, 0, 0, 0 },
5459 { "sal", 18, -1, 0, 0, 0, 0, 0, 0 },
5460 { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 },
5461 { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 },
5462 { "sas", 21, -1, 0, 0, 0, 0, 0, 0 },
5463 { "sr", 22, -1, 0, 0, 0, 0, 0, 0 },
5464 { "st", 23, -1, 0, 0, 0, 0, 0, 0 },
5465 { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 },
5466 { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 },
5467 { "mn", 26, -1, 0, 0, 0, 0, 0, 0 },
5468 { "i", 27, -1, 0, 0, 0, 0, 0, 0 },
5469 { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 },
5470 { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 },
5471 { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 },
5472 { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 },
5473 { "z", 32, -1, 0, 0, 0, 0, 0, 0 },
5474 { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 },
5475 { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 },
5476 { "r3", 35, -1, 0, 0, 0, 0, 0, 0 },
5477 { "rbit2", 36, -1, 0, 0, 0, 0, 0, 0 },
5478 { "rhi", 37, -1, 0, 0, 0, 0, 0, 0 },
5479 { "t3", 38, -1, 0, 0, 0, 0, 0, 0 },
5480 { "tbit2", 39, -1, 0, 0, 0, 0, 0, 0 },
5481 { "tlo", 40, -1, 0, 0, 0, 0, 0, 0 },
5482 { "w", 41, -1, 0, 0, 0, 0, 0, 0 },
5483 { "y", 42, -1, 0, 0, 0, 0, 0, 0 },
5484 { "x", 43, -1, 0, 0, 0, 0, 0, 0 },
5485 { "t2", 44, -1, 0, 0, 0, 0, 0, 0 },
5486 { "s2", 45, -1, 0, 0, 0, 0, 0, 0 },
5487 { "r2", 46, -1, 0, 0, 0, 0, 0, 0 },
5488 { "t4", 47, -1, 0, 0, 0, 0, 0, 0 },
5489 { "s4", 48, -1, 0, 0, 0, 0, 0, 0 },
5490 { "r4", 49, -1, 0, 0, 0, 0, 0, 0 },
5491 { "t8", 50, -1, 0, 0, 0, 0, 0, 0 },
5492 { "s8", 51, -1, 0, 0, 0, 0, 0, 0 },
5493 { "r8", 52, -1, 0, 0, 0, 0, 0, 0 },
5494 { "xt_wbr15_imm", 53, -1, 0, 0, 0, 0, 0, 0 },
5495 { "xt_wbr18_imm", 54, -1, 0, 0, 0, 0, 0, 0 },
5496 { "op0_xt_flix64_slot0_s3", 55, -1, 0, 0, 0, 0, 0, 0 },
5497 { "combined3e2c5767_fld7", 56, -1, 0, 0, 0, 0, 0, 0 },
5498 { "combined3e2c5767_fld8", 57, -1, 0, 0, 0, 0, 0, 0 },
5499 { "combined3e2c5767_fld9", 58, -1, 0, 0, 0, 0, 0, 0 },
5500 { "combined3e2c5767_fld11", 59, -1, 0, 0, 0, 0, 0, 0 },
5501 { "combined3e2c5767_fld49xt_flix64_slot0", 60, -1, 0, 0, 0, 0, 0, 0 },
5502 { "op0_s4", 61, -1, 0, 0, 0, 0, 0, 0 },
5503 { "combined3e2c5767_fld16", 62, -1, 0, 0, 0, 0, 0, 0 },
5504 { "combined3e2c5767_fld19xt_flix64_slot1", 63, -1, 0, 0, 0, 0, 0, 0 },
5505 { "combined3e2c5767_fld20xt_flix64_slot1", 64, -1, 0, 0, 0, 0, 0, 0 },
5506 { "combined3e2c5767_fld21xt_flix64_slot1", 65, -1, 0, 0, 0, 0, 0, 0 },
5507 { "combined3e2c5767_fld22xt_flix64_slot1", 66, -1, 0, 0, 0, 0, 0, 0 },
5508 { "combined3e2c5767_fld23xt_flix64_slot1", 67, -1, 0, 0, 0, 0, 0, 0 },
5509 { "combined3e2c5767_fld25xt_flix64_slot1", 68, -1, 0, 0, 0, 0, 0, 0 },
5510 { "combined3e2c5767_fld26xt_flix64_slot1", 69, -1, 0, 0, 0, 0, 0, 0 },
5511 { "combined3e2c5767_fld28xt_flix64_slot1", 70, -1, 0, 0, 0, 0, 0, 0 },
5512 { "combined3e2c5767_fld30xt_flix64_slot1", 71, -1, 0, 0, 0, 0, 0, 0 },
5513 { "combined3e2c5767_fld32xt_flix64_slot1", 72, -1, 0, 0, 0, 0, 0, 0 },
5514 { "combined3e2c5767_fld33xt_flix64_slot1", 73, -1, 0, 0, 0, 0, 0, 0 },
5515 { "combined3e2c5767_fld35xt_flix64_slot1", 74, -1, 0, 0, 0, 0, 0, 0 },
5516 { "combined3e2c5767_fld51xt_flix64_slot1", 75, -1, 0, 0, 0, 0, 0, 0 },
5517 { "combined3e2c5767_fld52xt_flix64_slot1", 76, -1, 0, 0, 0, 0, 0, 0 },
5518 { "combined3e2c5767_fld53xt_flix64_slot1", 77, -1, 0, 0, 0, 0, 0, 0 },
5519 { "combined3e2c5767_fld54xt_flix64_slot1", 78, -1, 0, 0, 0, 0, 0, 0 },
5520 { "combined3e2c5767_fld57xt_flix64_slot1", 79, -1, 0, 0, 0, 0, 0, 0 },
5521 { "combined3e2c5767_fld58xt_flix64_slot1", 80, -1, 0, 0, 0, 0, 0, 0 },
5522 { "combined3e2c5767_fld60xt_flix64_slot1", 81, -1, 0, 0, 0, 0, 0, 0 },
5523 { "combined3e2c5767_fld62xt_flix64_slot1", 82, -1, 0, 0, 0, 0, 0, 0 },
5524 { "op0_s5", 83, -1, 0, 0, 0, 0, 0, 0 },
5525 { "combined3e2c5767_fld36xt_flix64_slot2", 84, -1, 0, 0, 0, 0, 0, 0 },
5526 { "combined3e2c5767_fld37xt_flix64_slot2", 85, -1, 0, 0, 0, 0, 0, 0 },
5527 { "combined3e2c5767_fld39xt_flix64_slot2", 86, -1, 0, 0, 0, 0, 0, 0 },
5528 { "combined3e2c5767_fld41xt_flix64_slot2", 87, -1, 0, 0, 0, 0, 0, 0 },
5529 { "combined3e2c5767_fld42xt_flix64_slot2", 88, -1, 0, 0, 0, 0, 0, 0 },
5530 { "combined3e2c5767_fld44xt_flix64_slot2", 89, -1, 0, 0, 0, 0, 0, 0 },
5531 { "combined3e2c5767_fld45xt_flix64_slot2", 90, -1, 0, 0, 0, 0, 0, 0 },
5532 { "combined3e2c5767_fld47xt_flix64_slot2", 91, -1, 0, 0, 0, 0, 0, 0 },
5533 { "combined3e2c5767_fld63xt_flix64_slot2", 92, -1, 0, 0, 0, 0, 0, 0 },
5534 { "combined3e2c5767_fld64xt_flix64_slot2", 93, -1, 0, 0, 0, 0, 0, 0 },
5535 { "combined3e2c5767_fld65xt_flix64_slot2", 94, -1, 0, 0, 0, 0, 0, 0 },
5536 { "combined3e2c5767_fld66xt_flix64_slot2", 95, -1, 0, 0, 0, 0, 0, 0 },
5537 { "combined3e2c5767_fld68xt_flix64_slot2", 96, -1, 0, 0, 0, 0, 0, 0 },
5538 { "op0_s6", 97, -1, 0, 0, 0, 0, 0, 0 },
5539 { "combined3e2c5767_fld70xt_flix64_slot3", 98, -1, 0, 0, 0, 0, 0, 0 },
5540 { "combined3e2c5767_fld71", 99, -1, 0, 0, 0, 0, 0, 0 },
5541 { "combined3e2c5767_fld72xt_flix64_slot3", 100, -1, 0, 0, 0, 0, 0, 0 },
5542 { "combined3e2c5767_fld73xt_flix64_slot3", 101, -1, 0, 0, 0, 0, 0, 0 },
5543 { "combined3e2c5767_fld74xt_flix64_slot3", 102, -1, 0, 0, 0, 0, 0, 0 },
5544 { "combined3e2c5767_fld75xt_flix64_slot3", 103, -1, 0, 0, 0, 0, 0, 0 },
5545 { "combined3e2c5767_fld76xt_flix64_slot3", 104, -1, 0, 0, 0, 0, 0, 0 },
5546 { "combined3e2c5767_fld77xt_flix64_slot3", 105, -1, 0, 0, 0, 0, 0, 0 },
5547 { "combined3e2c5767_fld78xt_flix64_slot3", 106, -1, 0, 0, 0, 0, 0, 0 },
5548 { "combined3e2c5767_fld79xt_flix64_slot3", 107, -1, 0, 0, 0, 0, 0, 0 },
5549 { "combined3e2c5767_fld80xt_flix64_slot3", 108, -1, 0, 0, 0, 0, 0, 0 },
5550 { "combined3e2c5767_fld81xt_flix64_slot3", 109, -1, 0, 0, 0, 0, 0, 0 },
5551 { "combined3e2c5767_fld82xt_flix64_slot3", 110, -1, 0, 0, 0, 0, 0, 0 },
5552 { "combined3e2c5767_fld83xt_flix64_slot3", 111, -1, 0, 0, 0, 0, 0, 0 },
5553 { "combined3e2c5767_fld84xt_flix64_slot3", 112, -1, 0, 0, 0, 0, 0, 0 },
5554 { "combined3e2c5767_fld85xt_flix64_slot3", 113, -1, 0, 0, 0, 0, 0, 0 },
5555 { "combined3e2c5767_fld86xt_flix64_slot3", 114, -1, 0, 0, 0, 0, 0, 0 },
5556 { "combined3e2c5767_fld87xt_flix64_slot3", 115, -1, 0, 0, 0, 0, 0, 0 },
5557 { "combined3e2c5767_fld88xt_flix64_slot3", 116, -1, 0, 0, 0, 0, 0, 0 },
5558 { "combined3e2c5767_fld89xt_flix64_slot3", 117, -1, 0, 0, 0, 0, 0, 0 },
5559 { "combined3e2c5767_fld90xt_flix64_slot3", 118, -1, 0, 0, 0, 0, 0, 0 },
5560 { "combined3e2c5767_fld91xt_flix64_slot3", 119, -1, 0, 0, 0, 0, 0, 0 },
5561 { "combined3e2c5767_fld92xt_flix64_slot3", 120, -1, 0, 0, 0, 0, 0, 0 },
5562 { "combined3e2c5767_fld93xt_flix64_slot3", 121, -1, 0, 0, 0, 0, 0, 0 },
5563 { "op0_xt_flix64_slot0", 122, -1, 0, 0, 0, 0, 0, 0 }
43cd72b9
BW		 5564};
5565
7aa09196
SA		 5566\f
5567/* Iclass table. */
43cd72b9 5568
7aa09196 5569static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
074f5109 5570 { { STATE_PSRING }, 'i' },
7aa09196
SA		 5571 { { STATE_PSEXCM }, 'm' },
5572 { { STATE_EPC1 }, 'i' }
43cd72b9
BW		 5573};
5574
7aa09196 5575static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
074f5109
BW		 5576 { { STATE_PSEXCM }, 'i' },
5577 { { STATE_PSRING }, 'i' },
7aa09196 5578 { { STATE_DEPC }, 'i' }
43cd72b9
BW		 5579};
5580
7aa09196
SA		 5581static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
5582 { { 0 /* soffsetx4 */ }, 'i' },
5583 { { 10 /* ar12 */ }, 'o' }
43cd72b9
BW		 5584};
5585
7aa09196
SA		 5586static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
5587 { { STATE_PSCALLINC }, 'o' }
43cd72b9
BW		 5588};
5589
7aa09196
SA		 5590static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
5591 { { 0 /* soffsetx4 */ }, 'i' },
5592 { { 9 /* ar8 */ }, 'o' }
43cd72b9
BW		 5593};
5594
7aa09196
SA		 5595static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
5596 { { STATE_PSCALLINC }, 'o' }
43cd72b9
BW		 5597};
5598
7aa09196
SA		 5599static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
5600 { { 0 /* soffsetx4 */ }, 'i' },
5601 { { 8 /* ar4 */ }, 'o' }
33430bd0
BW		 5602};
5603
7aa09196
SA		 5604static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
5605 { { STATE_PSCALLINC }, 'o' }
43cd72b9
BW		 5606};
5607
7aa09196
SA		 5608static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
5609 { { 4 /* ars */ }, 'i' },
5610 { { 10 /* ar12 */ }, 'o' }
43cd72b9
BW		 5611};
5612
7aa09196
SA		 5613static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
5614 { { STATE_PSCALLINC }, 'o' }
33430bd0
BW		 5615};
5616
7aa09196
SA		 5617static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
5618 { { 4 /* ars */ }, 'i' },
5619 { { 9 /* ar8 */ }, 'o' }
33430bd0
BW		 5620};
5621
7aa09196
SA		 5622static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
5623 { { STATE_PSCALLINC }, 'o' }
43cd72b9
BW		 5624};
5625
7aa09196
SA		 5626static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
5627 { { 4 /* ars */ }, 'i' },
5628 { { 8 /* ar4 */ }, 'o' }
43cd72b9
BW		 5629};
5630
7aa09196
SA		 5631static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
5632 { { STATE_PSCALLINC }, 'o' }
43cd72b9
BW		 5633};
5634
7aa09196
SA		 5635static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
5636 { { 11 /* ars_entry */ }, 's' },
5637 { { 4 /* ars */ }, 'i' },
5638 { { 1 /* uimm12x8 */ }, 'i' }
5639};
5640
5641static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
5642 { { STATE_PSCALLINC }, 'i' },
074f5109 5643 { { STATE_PSEXCM }, 'i' },
7aa09196
SA		 5644 { { STATE_PSWOE }, 'i' },
5645 { { STATE_WindowBase }, 'm' },
5646 { { STATE_WindowStart }, 'm' }
43cd72b9
BW		 5647};
5648
7aa09196
SA		 5649static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
5650 { { 6 /* art */ }, 'o' },
5651 { { 4 /* ars */ }, 'i' }
43cd72b9
BW		 5652};
5653
7aa09196
SA		 5654static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
5655 { { STATE_WindowBase }, 'i' },
5656 { { STATE_WindowStart }, 'i' }
43cd72b9
BW		 5657};
5658
7aa09196
SA		 5659static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
5660 { { 2 /* simm4 */ }, 'i' }
43cd72b9
BW		 5661};
5662
7aa09196 5663static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
074f5109
BW		 5664 { { STATE_PSEXCM }, 'i' },
5665 { { STATE_PSRING }, 'i' },
7aa09196 5666 { { STATE_WindowBase }, 'm' }
43cd72b9
BW		 5667};
5668
7aa09196
SA		 5669static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
5670 { { 5 /* *ars_invisible */ }, 'i' }
43cd72b9
BW		 5671};
5672
7aa09196
SA		 5673static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
5674 { { STATE_WindowBase }, 'm' },
5675 { { STATE_WindowStart }, 'm' },
074f5109 5676 { { STATE_PSEXCM }, 'i' },
7aa09196
SA		 5677 { { STATE_PSWOE }, 'i' }
5678};
5679
5680static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
5681 { { STATE_EPC1 }, 'i' },
5682 { { STATE_PSEXCM }, 'm' },
074f5109 5683 { { STATE_PSRING }, 'i' },
7aa09196
SA		 5684 { { STATE_WindowBase }, 'm' },
5685 { { STATE_WindowStart }, 'm' },
5686 { { STATE_PSOWB }, 'i' }
43cd72b9
BW		 5687};
5688
7aa09196
SA		 5689static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
5690 { { 6 /* art */ }, 'o' },
5691 { { 4 /* ars */ }, 'i' },
5692 { { 12 /* immrx4 */ }, 'i' }
43cd72b9
BW		 5693};
5694
7aa09196 5695static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
074f5109 5696 { { STATE_PSEXCM }, 'i' },
7aa09196 5697 { { STATE_PSRING }, 'i' }
43cd72b9
BW		 5698};
5699
7aa09196
SA		 5700static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
5701 { { 6 /* art */ }, 'i' },
5702 { { 4 /* ars */ }, 'i' },
5703 { { 12 /* immrx4 */ }, 'i' }
43cd72b9
BW		 5704};
5705
7aa09196 5706static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
074f5109 5707 { { STATE_PSEXCM }, 'i' },
7aa09196 5708 { { STATE_PSRING }, 'i' }
43cd72b9
BW		 5709};
5710
7aa09196
SA		 5711static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
5712 { { 6 /* art */ }, 'o' }
43cd72b9
BW		 5713};
5714
7aa09196 5715static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
074f5109
BW		 5716 { { STATE_PSEXCM }, 'i' },
5717 { { STATE_PSRING }, 'i' },
7aa09196 5718 { { STATE_WindowBase }, 'i' }
43cd72b9
BW		 5719};
5720
7aa09196
SA		 5721static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
5722 { { 6 /* art */ }, 'i' }
43cd72b9
BW		 5723};
5724
7aa09196 5725static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
074f5109
BW		 5726 { { STATE_PSEXCM }, 'i' },
5727 { { STATE_PSRING }, 'i' },
7aa09196 5728 { { STATE_WindowBase }, 'o' }
43cd72b9
BW		 5729};
5730
7aa09196
SA		 5731static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
5732 { { 6 /* art */ }, 'm' }
43cd72b9
BW		 5733};
5734
7aa09196 5735static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
074f5109
BW		 5736 { { STATE_PSEXCM }, 'i' },
5737 { { STATE_PSRING }, 'i' },
7aa09196 5738 { { STATE_WindowBase }, 'm' }
43cd72b9
BW		 5739};
5740
7aa09196
SA		 5741static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
5742 { { 6 /* art */ }, 'o' }
43cd72b9
BW		 5743};
5744
7aa09196 5745static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
074f5109
BW		 5746 { { STATE_PSEXCM }, 'i' },
5747 { { STATE_PSRING }, 'i' },
7aa09196 5748 { { STATE_WindowStart }, 'i' }
43cd72b9
BW		 5749};
5750
7aa09196
SA		 5751static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
5752 { { 6 /* art */ }, 'i' }
43cd72b9
BW		 5753};
5754
7aa09196 5755static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
074f5109
BW		 5756 { { STATE_PSEXCM }, 'i' },
5757 { { STATE_PSRING }, 'i' },
7aa09196 5758 { { STATE_WindowStart }, 'o' }
43cd72b9
BW		 5759};
5760
7aa09196
SA		 5761static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
5762 { { 6 /* art */ }, 'm' }
43cd72b9
BW		 5763};
5764
7aa09196
SA		 5765static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
5766 { { STATE_PSEXCM }, 'i' },
5767 { { STATE_PSRING }, 'i' },
5768 { { STATE_WindowStart }, 'm' }
33430bd0
BW		 5769};
5770
7aa09196
SA		 5771static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
5772 { { 3 /* arr */ }, 'o' },
5773 { { 4 /* ars */ }, 'i' },
5774 { { 6 /* art */ }, 'i' }
33430bd0
BW		 5775};
5776
7aa09196
SA		 5777static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
5778 { { 3 /* arr */ }, 'o' },
5779 { { 4 /* ars */ }, 'i' },
5780 { { 16 /* ai4const */ }, 'i' }
43cd72b9
BW		 5781};
5782
7aa09196
SA		 5783static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
5784 { { 4 /* ars */ }, 'i' },
5785 { { 15 /* uimm6 */ }, 'i' }
074f5109
BW		 5786};
5787
7aa09196
SA		 5788static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
5789 { { 6 /* art */ }, 'o' },
5790 { { 4 /* ars */ }, 'i' },
5791 { { 13 /* lsi4x4 */ }, 'i' }
43cd72b9
BW		 5792};
5793
7aa09196
SA		 5794static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
5795 { { 6 /* art */ }, 'o' },
5796 { { 4 /* ars */ }, 'i' }
074f5109
BW		 5797};
5798
7aa09196
SA		 5799static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
5800 { { 4 /* ars */ }, 'o' },
5801 { { 14 /* simm7 */ }, 'i' }
43cd72b9
BW		 5802};
5803
7aa09196
SA		 5804static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
5805 { { 5 /* *ars_invisible */ }, 'i' }
074f5109
BW		 5806};
5807
7aa09196
SA		 5808static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
5809 { { 6 /* art */ }, 'i' },
5810 { { 4 /* ars */ }, 'i' },
5811 { { 13 /* lsi4x4 */ }, 'i' }
43cd72b9
BW		 5812};
5813
7aa09196
SA		 5814static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
5815 { { 3 /* arr */ }, 'o' }
43cd72b9
BW		 5816};
5817
7aa09196
SA		 5818static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
5819 { { STATE_THREADPTR }, 'i' }
074f5109
BW		 5820};
5821
7aa09196
SA		 5822static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
5823 { { 6 /* art */ }, 'i' }
43cd72b9
BW		 5824};
5825
7aa09196
SA		 5826static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
5827 { { STATE_THREADPTR }, 'o' }
074f5109
BW		 5828};
5829
7aa09196
SA		 5830static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
5831 { { 6 /* art */ }, 'o' },
5832 { { 4 /* ars */ }, 'i' },
5833 { { 23 /* simm8 */ }, 'i' }
43cd72b9
BW		 5834};
5835
7aa09196
SA		 5836static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
5837 { { 6 /* art */ }, 'o' },
5838 { { 4 /* ars */ }, 'i' },
5839 { { 24 /* simm8x256 */ }, 'i' }
33430bd0
BW		 5840};
5841
7aa09196
SA		 5842static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
5843 { { 3 /* arr */ }, 'o' },
5844 { { 4 /* ars */ }, 'i' },
5845 { { 6 /* art */ }, 'i' }
33430bd0
BW		 5846};
5847
7aa09196
SA		 5848static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
5849 { { 3 /* arr */ }, 'o' },
5850 { { 4 /* ars */ }, 'i' },
5851 { { 6 /* art */ }, 'i' }
43cd72b9
BW		 5852};
5853
7aa09196
SA		 5854static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
5855 { { 4 /* ars */ }, 'i' },
5856 { { 17 /* b4const */ }, 'i' },
5857 { { 28 /* label8 */ }, 'i' }
074f5109
BW		 5858};
5859
7aa09196
SA		 5860static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
5861 { { 4 /* ars */ }, 'i' },
5862 { { 67 /* bbi */ }, 'i' },
5863 { { 28 /* label8 */ }, 'i' }
43cd72b9
BW		 5864};
5865
7aa09196
SA		 5866static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
5867 { { 4 /* ars */ }, 'i' },
5868 { { 18 /* b4constu */ }, 'i' },
5869 { { 28 /* label8 */ }, 'i' }
074f5109
BW		 5870};
5871
7aa09196
SA		 5872static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
5873 { { 4 /* ars */ }, 'i' },
5874 { { 6 /* art */ }, 'i' },
5875 { { 28 /* label8 */ }, 'i' }
074f5109
BW		 5876};
5877
7aa09196
SA		 5878static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
5879 { { 4 /* ars */ }, 'i' },
5880 { { 30 /* label12 */ }, 'i' }
074f5109
BW		 5881};
5882
7aa09196
SA		 5883static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
5884 { { 0 /* soffsetx4 */ }, 'i' },
5885 { { 7 /* ar0 */ }, 'o' }
074f5109
BW		 5886};
5887
7aa09196
SA		 5888static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
5889 { { 4 /* ars */ }, 'i' },
5890 { { 7 /* ar0 */ }, 'o' }
074f5109
BW		 5891};
5892
7aa09196
SA		 5893static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
5894 { { 3 /* arr */ }, 'o' },
5895 { { 6 /* art */ }, 'i' },
5896 { { 82 /* sae */ }, 'i' },
5897 { { 27 /* op2p1 */ }, 'i' }
074f5109
BW		 5898};
5899
7aa09196
SA		 5900static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
5901 { { 31 /* soffset */ }, 'i' }
074f5109
BW		 5902};
5903
7aa09196
SA		 5904static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
5905 { { 4 /* ars */ }, 'i' }
074f5109
BW		 5906};
5907
7aa09196
SA		 5908static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
5909 { { 6 /* art */ }, 'o' },
5910 { { 4 /* ars */ }, 'i' },
5911 { { 20 /* uimm8x2 */ }, 'i' }
074f5109
BW		 5912};
5913
7aa09196
SA		 5914static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
5915 { { 6 /* art */ }, 'o' },
5916 { { 4 /* ars */ }, 'i' },
5917 { { 20 /* uimm8x2 */ }, 'i' }
074f5109
BW		 5918};
5919
7aa09196
SA		 5920static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
5921 { { 6 /* art */ }, 'o' },
5922 { { 4 /* ars */ }, 'i' },
5923 { { 21 /* uimm8x4 */ }, 'i' }
074f5109
BW		 5924};
5925
7aa09196
SA		 5926static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
5927 { { 6 /* art */ }, 'o' },
5928 { { 32 /* uimm16x4 */ }, 'i' }
074f5109
BW		 5929};
5930
7aa09196
SA		 5931static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
5932 { { STATE_LITBADDR }, 'i' },
5933 { { STATE_LITBEN }, 'i' }
074f5109
BW		 5934};
5935
7aa09196
SA		 5936static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
5937 { { 6 /* art */ }, 'o' },
5938 { { 4 /* ars */ }, 'i' },
5939 { { 19 /* uimm8 */ }, 'i' }
074f5109
BW		 5940};
5941
7aa09196
SA		 5942static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
5943 { { 4 /* ars */ }, 'i' },
5944 { { 29 /* ulabel8 */ }, 'i' }
074f5109
BW		 5945};
5946
7aa09196
SA		 5947static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
5948 { { STATE_LBEG }, 'o' },
5949 { { STATE_LEND }, 'o' },
5950 { { STATE_LCOUNT }, 'o' }
074f5109
BW		 5951};
5952
7aa09196
SA		 5953static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
5954 { { 4 /* ars */ }, 'i' },
5955 { { 29 /* ulabel8 */ }, 'i' }
074f5109
BW		 5956};
5957
7aa09196
SA		 5958static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
5959 { { STATE_LBEG }, 'o' },
5960 { { STATE_LEND }, 'o' },
5961 { { STATE_LCOUNT }, 'o' }
074f5109
BW		 5962};
5963
7aa09196
SA		 5964static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
5965 { { 6 /* art */ }, 'o' },
5966 { { 25 /* simm12b */ }, 'i' }
074f5109
BW		 5967};
5968
7aa09196
SA		 5969static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
5970 { { 3 /* arr */ }, 'm' },
5971 { { 4 /* ars */ }, 'i' },
5972 { { 6 /* art */ }, 'i' }
074f5109
BW		 5973};
5974
7aa09196
SA		 5975static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
5976 { { 3 /* arr */ }, 'o' },
5977 { { 6 /* art */ }, 'i' }
074f5109
BW		 5978};
5979
7aa09196
SA		 5980static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
5981 { { 5 /* *ars_invisible */ }, 'i' }
074f5109
BW		 5982};
5983
7aa09196
SA		 5984static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
5985 { { 6 /* art */ }, 'i' },
5986 { { 4 /* ars */ }, 'i' },
5987 { { 20 /* uimm8x2 */ }, 'i' }
33430bd0
BW		 5988};
5989
7aa09196
SA		 5990static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
5991 { { 6 /* art */ }, 'i' },
5992 { { 4 /* ars */ }, 'i' },
5993 { { 21 /* uimm8x4 */ }, 'i' }
33430bd0
BW		 5994};
5995
7aa09196
SA		 5996static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
5997 { { 6 /* art */ }, 'i' },
5998 { { 4 /* ars */ }, 'i' },
5999 { { 19 /* uimm8 */ }, 'i' }
33430bd0
BW		 6000};
6001
7aa09196
SA		 6002static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
6003 { { 4 /* ars */ }, 'i' }
33430bd0
BW		 6004};
6005
7aa09196
SA		 6006static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
6007 { { STATE_SAR }, 'o' }
33430bd0
BW		 6008};
6009
7aa09196
SA		 6010static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
6011 { { 86 /* sas */ }, 'i' }
33430bd0
BW		 6012};
6013
7aa09196
SA		 6014static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
6015 { { STATE_SAR }, 'o' }
33430bd0
BW		 6016};
6017
7aa09196
SA		 6018static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
6019 { { 3 /* arr */ }, 'o' },
6020 { { 4 /* ars */ }, 'i' }
33430bd0
BW		 6021};
6022
7aa09196
SA		 6023static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
6024 { { STATE_SAR }, 'i' }
33430bd0
BW		 6025};
6026
7aa09196
SA		 6027static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
6028 { { 3 /* arr */ }, 'o' },
6029 { { 4 /* ars */ }, 'i' },
6030 { { 6 /* art */ }, 'i' }
33430bd0
BW		 6031};
6032
7aa09196
SA		 6033static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
6034 { { STATE_SAR }, 'i' }
33430bd0
BW		 6035};
6036
7aa09196
SA		 6037static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
6038 { { 3 /* arr */ }, 'o' },
6039 { { 6 /* art */ }, 'i' }
33430bd0
BW		 6040};
6041
7aa09196
SA		 6042static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
6043 { { STATE_SAR }, 'i' }
33430bd0
BW		 6044};
6045
7aa09196
SA		 6046static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
6047 { { 3 /* arr */ }, 'o' },
6048 { { 4 /* ars */ }, 'i' },
6049 { { 26 /* msalp32 */ }, 'i' }
33430bd0
BW		 6050};
6051
7aa09196
SA		 6052static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
6053 { { 3 /* arr */ }, 'o' },
6054 { { 6 /* art */ }, 'i' },
6055 { { 84 /* sargt */ }, 'i' }
6056};
6057
6058static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
6059 { { 3 /* arr */ }, 'o' },
6060 { { 6 /* art */ }, 'i' },
6061 { { 70 /* s */ }, 'i' }
6062};
6063
6064static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
6065 { { STATE_XTSYNC }, 'i' }
6066};
6067
6068static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
6069 { { 6 /* art */ }, 'o' },
6070 { { 70 /* s */ }, 'i' }
6071};
6072
6073static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
6074 { { STATE_PSWOE }, 'i' },
6075 { { STATE_PSCALLINC }, 'i' },
6076 { { STATE_PSOWB }, 'i' },
6077 { { STATE_PSRING }, 'i' },
6078 { { STATE_PSUM }, 'i' },
33430bd0 6079 { { STATE_PSEXCM }, 'i' },
7aa09196 6080 { { STATE_PSINTLEVEL }, 'm' }
33430bd0
BW		 6081};
6082
7aa09196
SA		 6083static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
6084 { { 6 /* art */ }, 'o' }
33430bd0
BW		 6085};
6086
7aa09196
SA		 6087static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
6088 { { STATE_LEND }, 'i' }
33430bd0
BW		 6089};
6090
7aa09196
SA		 6091static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
6092 { { 6 /* art */ }, 'i' }
33430bd0
BW		 6093};
6094
7aa09196
SA		 6095static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
6096 { { STATE_LEND }, 'o' }
33430bd0
BW		 6097};
6098
7aa09196
SA		 6099static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
6100 { { 6 /* art */ }, 'm' }
33430bd0
BW		 6101};
6102
7aa09196
SA		 6103static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
6104 { { STATE_LEND }, 'm' }
33430bd0
BW		 6105};
6106
7aa09196
SA		 6107static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
6108 { { 6 /* art */ }, 'o' }
074f5109
BW		 6109};
6110
7aa09196
SA		 6111static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
6112 { { STATE_LCOUNT }, 'i' }
074f5109
BW		 6113};
6114
7aa09196
SA		 6115static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
6116 { { 6 /* art */ }, 'i' }
6117};
6118
6119static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
6120 { { STATE_XTSYNC }, 'o' },
6121 { { STATE_LCOUNT }, 'o' }
6122};
6123
6124static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
6125 { { 6 /* art */ }, 'm' }
6126};
6127
6128static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
6129 { { STATE_XTSYNC }, 'o' },
6130 { { STATE_LCOUNT }, 'm' }
6131};
6132
6133static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
6134 { { 6 /* art */ }, 'o' }
6135};
6136
6137static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
6138 { { STATE_LBEG }, 'i' }
6139};
6140
6141static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
6142 { { 6 /* art */ }, 'i' }
6143};
6144
6145static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
6146 { { STATE_LBEG }, 'o' }
6147};
6148
6149static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
6150 { { 6 /* art */ }, 'm' }
6151};
6152
6153static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
6154 { { STATE_LBEG }, 'm' }
6155};
6156
6157static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
6158 { { 6 /* art */ }, 'o' }
6159};
6160
6161static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
6162 { { STATE_SAR }, 'i' }
6163};
6164
6165static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
6166 { { 6 /* art */ }, 'i' }
6167};
6168
6169static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
6170 { { STATE_SAR }, 'o' },
6171 { { STATE_XTSYNC }, 'o' }
6172};
6173
6174static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
6175 { { 6 /* art */ }, 'm' }
6176};
6177
6178static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
6179 { { STATE_SAR }, 'm' }
6180};
6181
6182static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
6183 { { 6 /* art */ }, 'o' }
6184};
6185
6186static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
6187 { { STATE_LITBADDR }, 'i' },
6188 { { STATE_LITBEN }, 'i' }
6189};
6190
6191static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
6192 { { 6 /* art */ }, 'i' }
6193};
6194
6195static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
6196 { { STATE_LITBADDR }, 'o' },
6197 { { STATE_LITBEN }, 'o' }
6198};
6199
6200static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
6201 { { 6 /* art */ }, 'm' }
6202};
6203
6204static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
6205 { { STATE_LITBADDR }, 'm' },
6206 { { STATE_LITBEN }, 'm' }
6207};
6208
6209static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
6210 { { 6 /* art */ }, 'o' }
6211};
6212
6213static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
074f5109 6214 { { STATE_PSEXCM }, 'i' },
7aa09196 6215 { { STATE_PSRING }, 'i' }
074f5109
BW		 6216};
6217
7aa09196
SA		 6218static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
6219 { { 6 /* art */ }, 'o' }
43cd72b9
BW		 6220};
6221
7aa09196
SA		 6222static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
6223 { { STATE_PSEXCM }, 'i' },
6224 { { STATE_PSRING }, 'i' }
43cd72b9
BW		 6225};
6226
7aa09196
SA		 6227static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
6228 { { 6 /* art */ }, 'o' }
43cd72b9
BW		 6229};
6230
7aa09196
SA		 6231static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
6232 { { STATE_PSWOE }, 'i' },
6233 { { STATE_PSCALLINC }, 'i' },
6234 { { STATE_PSOWB }, 'i' },
6235 { { STATE_PSRING }, 'i' },
6236 { { STATE_PSUM }, 'i' },
6237 { { STATE_PSEXCM }, 'i' },
6238 { { STATE_PSINTLEVEL }, 'i' }
074f5109
BW		 6239};
6240
7aa09196
SA		 6241static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
6242 { { 6 /* art */ }, 'i' }
43cd72b9
BW		 6243};
6244
7aa09196
SA		 6245static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
6246 { { STATE_PSWOE }, 'o' },
6247 { { STATE_PSCALLINC }, 'o' },
6248 { { STATE_PSOWB }, 'o' },
6249 { { STATE_PSRING }, 'm' },
6250 { { STATE_PSUM }, 'o' },
6251 { { STATE_PSEXCM }, 'm' },
6252 { { STATE_PSINTLEVEL }, 'o' }
43cd72b9
BW		 6253};
6254
7aa09196
SA		 6255static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
6256 { { 6 /* art */ }, 'm' }
43cd72b9
BW		 6257};
6258
7aa09196
SA		 6259static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
6260 { { STATE_PSWOE }, 'm' },
6261 { { STATE_PSCALLINC }, 'm' },
6262 { { STATE_PSOWB }, 'm' },
6263 { { STATE_PSRING }, 'm' },
6264 { { STATE_PSUM }, 'm' },
6265 { { STATE_PSEXCM }, 'm' },
6266 { { STATE_PSINTLEVEL }, 'm' }
074f5109
BW		 6267};
6268
7aa09196
SA		 6269static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
6270 { { 6 /* art */ }, 'o' }
43cd72b9
BW		 6271};
6272
7aa09196
SA		 6273static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
6274 { { STATE_PSEXCM }, 'i' },
6275 { { STATE_PSRING }, 'i' },
6276 { { STATE_EPC1 }, 'i' }
074f5109
BW		 6277};
6278
7aa09196
SA		 6279static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
6280 { { 6 /* art */ }, 'i' }
43cd72b9
BW		 6281};
6282
7aa09196
SA		 6283static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
6284 { { STATE_PSEXCM }, 'i' },
6285 { { STATE_PSRING }, 'i' },
6286 { { STATE_EPC1 }, 'o' }
074f5109
BW		 6287};
6288
7aa09196
SA		 6289static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
6290 { { 6 /* art */ }, 'm' }
074f5109
BW		 6291};
6292
7aa09196
SA		 6293static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
6294 { { STATE_PSEXCM }, 'i' },
6295 { { STATE_PSRING }, 'i' },
6296 { { STATE_EPC1 }, 'm' }
074f5109
BW		 6297};
6298
7aa09196
SA		 6299static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
6300 { { 6 /* art */ }, 'o' }
074f5109
BW		 6301};
6302
7aa09196
SA		 6303static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
6304 { { STATE_PSEXCM }, 'i' },
6305 { { STATE_PSRING }, 'i' },
6306 { { STATE_EXCSAVE1 }, 'i' }
43cd72b9
BW		 6307};
6308
7aa09196
SA		 6309static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
6310 { { 6 /* art */ }, 'i' }
6311};
6312
6313static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
6314 { { STATE_PSEXCM }, 'i' },
6315 { { STATE_PSRING }, 'i' },
6316 { { STATE_EXCSAVE1 }, 'o' }
6317};
6318
6319static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
6320 { { 6 /* art */ }, 'm' }
6321};
6322
6323static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
6324 { { STATE_PSEXCM }, 'i' },
6325 { { STATE_PSRING }, 'i' },
6326 { { STATE_EXCSAVE1 }, 'm' }
6327};
6328
6329static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
6330 { { 6 /* art */ }, 'o' }
6331};
6332
6333static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
6334 { { STATE_PSEXCM }, 'i' },
6335 { { STATE_PSRING }, 'i' },
6336 { { STATE_EPC2 }, 'i' }
6337};
6338
6339static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
6340 { { 6 /* art */ }, 'i' }
6341};
6342
6343static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
6344 { { STATE_PSEXCM }, 'i' },
6345 { { STATE_PSRING }, 'i' },
6346 { { STATE_EPC2 }, 'o' }
6347};
6348
6349static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
6350 { { 6 /* art */ }, 'm' }
6351};
6352
6353static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
6354 { { STATE_PSEXCM }, 'i' },
6355 { { STATE_PSRING }, 'i' },
6356 { { STATE_EPC2 }, 'm' }
6357};
6358
6359static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
6360 { { 6 /* art */ }, 'o' }
6361};
6362
6363static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
6364 { { STATE_PSEXCM }, 'i' },
6365 { { STATE_PSRING }, 'i' },
6366 { { STATE_EXCSAVE2 }, 'i' }
6367};
6368
6369static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
6370 { { 6 /* art */ }, 'i' }
6371};
6372
6373static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
6374 { { STATE_PSEXCM }, 'i' },
6375 { { STATE_PSRING }, 'i' },
6376 { { STATE_EXCSAVE2 }, 'o' }
6377};
6378
6379static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
6380 { { 6 /* art */ }, 'm' }
6381};
6382
6383static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
6384 { { STATE_PSEXCM }, 'i' },
6385 { { STATE_PSRING }, 'i' },
6386 { { STATE_EXCSAVE2 }, 'm' }
6387};
6388
6389static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
6390 { { 6 /* art */ }, 'o' }
6391};
6392
6393static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
6394 { { STATE_PSEXCM }, 'i' },
6395 { { STATE_PSRING }, 'i' },
6396 { { STATE_EPC3 }, 'i' }
6397};
6398
6399static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
6400 { { 6 /* art */ }, 'i' }
6401};
6402
6403static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
6404 { { STATE_PSEXCM }, 'i' },
6405 { { STATE_PSRING }, 'i' },
6406 { { STATE_EPC3 }, 'o' }
6407};
6408
6409static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
6410 { { 6 /* art */ }, 'm' }
6411};
6412
6413static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
6414 { { STATE_PSEXCM }, 'i' },
6415 { { STATE_PSRING }, 'i' },
6416 { { STATE_EPC3 }, 'm' }
6417};
6418
6419static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
6420 { { 6 /* art */ }, 'o' }
6421};
6422
6423static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
6424 { { STATE_PSEXCM }, 'i' },
6425 { { STATE_PSRING }, 'i' },
6426 { { STATE_EXCSAVE3 }, 'i' }
6427};
6428
6429static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
6430 { { 6 /* art */ }, 'i' }
6431};
6432
6433static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
6434 { { STATE_PSEXCM }, 'i' },
6435 { { STATE_PSRING }, 'i' },
6436 { { STATE_EXCSAVE3 }, 'o' }
6437};
6438
6439static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
6440 { { 6 /* art */ }, 'm' }
6441};
6442
6443static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
6444 { { STATE_PSEXCM }, 'i' },
6445 { { STATE_PSRING }, 'i' },
6446 { { STATE_EXCSAVE3 }, 'm' }
6447};
6448
6449static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
6450 { { 6 /* art */ }, 'o' }
6451};
6452
6453static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
6454 { { STATE_PSEXCM }, 'i' },
6455 { { STATE_PSRING }, 'i' },
6456 { { STATE_EPC4 }, 'i' }
6457};
6458
6459static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
6460 { { 6 /* art */ }, 'i' }
6461};
6462
6463static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
6464 { { STATE_PSEXCM }, 'i' },
6465 { { STATE_PSRING }, 'i' },
6466 { { STATE_EPC4 }, 'o' }
6467};
6468
6469static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
6470 { { 6 /* art */ }, 'm' }
6471};
6472
6473static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
6474 { { STATE_PSEXCM }, 'i' },
6475 { { STATE_PSRING }, 'i' },
6476 { { STATE_EPC4 }, 'm' }
6477};
6478
6479static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
6480 { { 6 /* art */ }, 'o' }
6481};
6482
6483static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
6484 { { STATE_PSEXCM }, 'i' },
6485 { { STATE_PSRING }, 'i' },
6486 { { STATE_EXCSAVE4 }, 'i' }
6487};
6488
6489static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
6490 { { 6 /* art */ }, 'i' }
6491};
6492
6493static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
6494 { { STATE_PSEXCM }, 'i' },
6495 { { STATE_PSRING }, 'i' },
6496 { { STATE_EXCSAVE4 }, 'o' }
6497};
6498
6499static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
6500 { { 6 /* art */ }, 'm' }
6501};
6502
6503static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
6504 { { STATE_PSEXCM }, 'i' },
6505 { { STATE_PSRING }, 'i' },
6506 { { STATE_EXCSAVE4 }, 'm' }
6507};
6508
6509static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
6510 { { 6 /* art */ }, 'o' }
6511};
6512
6513static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
6514 { { STATE_PSEXCM }, 'i' },
6515 { { STATE_PSRING }, 'i' },
6516 { { STATE_EPC5 }, 'i' }
6517};
6518
6519static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
6520 { { 6 /* art */ }, 'i' }
6521};
6522
6523static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
6524 { { STATE_PSEXCM }, 'i' },
6525 { { STATE_PSRING }, 'i' },
6526 { { STATE_EPC5 }, 'o' }
6527};
6528
6529static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
6530 { { 6 /* art */ }, 'm' }
6531};
6532
6533static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
6534 { { STATE_PSEXCM }, 'i' },
6535 { { STATE_PSRING }, 'i' },
6536 { { STATE_EPC5 }, 'm' }
6537};
6538
6539static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
6540 { { 6 /* art */ }, 'o' }
6541};
6542
6543static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
6544 { { STATE_PSEXCM }, 'i' },
6545 { { STATE_PSRING }, 'i' },
6546 { { STATE_EXCSAVE5 }, 'i' }
6547};
6548
6549static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
6550 { { 6 /* art */ }, 'i' }
6551};
6552
6553static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
6554 { { STATE_PSEXCM }, 'i' },
6555 { { STATE_PSRING }, 'i' },
6556 { { STATE_EXCSAVE5 }, 'o' }
6557};
6558
6559static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
6560 { { 6 /* art */ }, 'm' }
6561};
6562
6563static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
6564 { { STATE_PSEXCM }, 'i' },
6565 { { STATE_PSRING }, 'i' },
6566 { { STATE_EXCSAVE5 }, 'm' }
6567};
6568
6569static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
6570 { { 6 /* art */ }, 'o' }
6571};
6572
6573static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
6574 { { STATE_PSEXCM }, 'i' },
6575 { { STATE_PSRING }, 'i' },
6576 { { STATE_EPC6 }, 'i' }
6577};
6578
6579static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
6580 { { 6 /* art */ }, 'i' }
6581};
6582
6583static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
6584 { { STATE_PSEXCM }, 'i' },
6585 { { STATE_PSRING }, 'i' },
6586 { { STATE_EPC6 }, 'o' }
6587};
6588
6589static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
6590 { { 6 /* art */ }, 'm' }
6591};
6592
6593static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
6594 { { STATE_PSEXCM }, 'i' },
6595 { { STATE_PSRING }, 'i' },
6596 { { STATE_EPC6 }, 'm' }
6597};
6598
6599static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
6600 { { 6 /* art */ }, 'o' }
6601};
6602
6603static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
6604 { { STATE_PSEXCM }, 'i' },
6605 { { STATE_PSRING }, 'i' },
6606 { { STATE_EXCSAVE6 }, 'i' }
6607};
6608
6609static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
6610 { { 6 /* art */ }, 'i' }
6611};
6612
6613static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
6614 { { STATE_PSEXCM }, 'i' },
6615 { { STATE_PSRING }, 'i' },
6616 { { STATE_EXCSAVE6 }, 'o' }
6617};
6618
6619static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
6620 { { 6 /* art */ }, 'm' }
6621};
6622
6623static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
6624 { { STATE_PSEXCM }, 'i' },
6625 { { STATE_PSRING }, 'i' },
6626 { { STATE_EXCSAVE6 }, 'm' }
6627};
6628
6629static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
6630 { { 6 /* art */ }, 'o' }
6631};
6632
6633static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
6634 { { STATE_PSEXCM }, 'i' },
6635 { { STATE_PSRING }, 'i' },
6636 { { STATE_EPC7 }, 'i' }
6637};
6638
6639static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
6640 { { 6 /* art */ }, 'i' }
6641};
6642
6643static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
6644 { { STATE_PSEXCM }, 'i' },
6645 { { STATE_PSRING }, 'i' },
6646 { { STATE_EPC7 }, 'o' }
6647};
6648
6649static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
6650 { { 6 /* art */ }, 'm' }
6651};
6652
6653static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
6654 { { STATE_PSEXCM }, 'i' },
6655 { { STATE_PSRING }, 'i' },
6656 { { STATE_EPC7 }, 'm' }
6657};
6658
6659static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
6660 { { 6 /* art */ }, 'o' }
6661};
6662
6663static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
6664 { { STATE_PSEXCM }, 'i' },
6665 { { STATE_PSRING }, 'i' },
6666 { { STATE_EXCSAVE7 }, 'i' }
6667};
6668
6669static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
6670 { { 6 /* art */ }, 'i' }
6671};
6672
6673static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
6674 { { STATE_PSEXCM }, 'i' },
6675 { { STATE_PSRING }, 'i' },
6676 { { STATE_EXCSAVE7 }, 'o' }
6677};
6678
6679static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
6680 { { 6 /* art */ }, 'm' }
6681};
6682
6683static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
6684 { { STATE_PSEXCM }, 'i' },
6685 { { STATE_PSRING }, 'i' },
6686 { { STATE_EXCSAVE7 }, 'm' }
6687};
6688
6689static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
6690 { { 6 /* art */ }, 'o' }
6691};
6692
6693static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
6694 { { STATE_PSEXCM }, 'i' },
6695 { { STATE_PSRING }, 'i' },
6696 { { STATE_EPS2 }, 'i' }
6697};
6698
6699static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
6700 { { 6 /* art */ }, 'i' }
6701};
6702
6703static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
6704 { { STATE_PSEXCM }, 'i' },
6705 { { STATE_PSRING }, 'i' },
6706 { { STATE_EPS2 }, 'o' }
6707};
6708
6709static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
6710 { { 6 /* art */ }, 'm' }
6711};
6712
6713static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
6714 { { STATE_PSEXCM }, 'i' },
6715 { { STATE_PSRING }, 'i' },
6716 { { STATE_EPS2 }, 'm' }
6717};
6718
6719static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
6720 { { 6 /* art */ }, 'o' }
6721};
6722
6723static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
6724 { { STATE_PSEXCM }, 'i' },
6725 { { STATE_PSRING }, 'i' },
6726 { { STATE_EPS3 }, 'i' }
6727};
6728
6729static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
6730 { { 6 /* art */ }, 'i' }
6731};
6732
6733static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
6734 { { STATE_PSEXCM }, 'i' },
6735 { { STATE_PSRING }, 'i' },
6736 { { STATE_EPS3 }, 'o' }
6737};
6738
6739static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
6740 { { 6 /* art */ }, 'm' }
6741};
6742
6743static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
6744 { { STATE_PSEXCM }, 'i' },
6745 { { STATE_PSRING }, 'i' },
6746 { { STATE_EPS3 }, 'm' }
6747};
6748
6749static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
6750 { { 6 /* art */ }, 'o' }
6751};
6752
6753static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
6754 { { STATE_PSEXCM }, 'i' },
6755 { { STATE_PSRING }, 'i' },
6756 { { STATE_EPS4 }, 'i' }
6757};
6758
6759static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
6760 { { 6 /* art */ }, 'i' }
6761};
6762
6763static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
6764 { { STATE_PSEXCM }, 'i' },
6765 { { STATE_PSRING }, 'i' },
6766 { { STATE_EPS4 }, 'o' }
6767};
6768
6769static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
6770 { { 6 /* art */ }, 'm' }
6771};
6772
6773static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
6774 { { STATE_PSEXCM }, 'i' },
6775 { { STATE_PSRING }, 'i' },
6776 { { STATE_EPS4 }, 'm' }
6777};
6778
6779static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
6780 { { 6 /* art */ }, 'o' }
6781};
6782
6783static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
6784 { { STATE_PSEXCM }, 'i' },
6785 { { STATE_PSRING }, 'i' },
6786 { { STATE_EPS5 }, 'i' }
6787};
6788
6789static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
6790 { { 6 /* art */ }, 'i' }
6791};
6792
6793static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
6794 { { STATE_PSEXCM }, 'i' },
6795 { { STATE_PSRING }, 'i' },
6796 { { STATE_EPS5 }, 'o' }
6797};
6798
6799static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
6800 { { 6 /* art */ }, 'm' }
6801};
6802
6803static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
6804 { { STATE_PSEXCM }, 'i' },
6805 { { STATE_PSRING }, 'i' },
6806 { { STATE_EPS5 }, 'm' }
6807};
6808
6809static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
6810 { { 6 /* art */ }, 'o' }
6811};
6812
6813static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
6814 { { STATE_PSEXCM }, 'i' },
6815 { { STATE_PSRING }, 'i' },
6816 { { STATE_EPS6 }, 'i' }
6817};
6818
6819static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
6820 { { 6 /* art */ }, 'i' }
6821};
6822
6823static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
6824 { { STATE_PSEXCM }, 'i' },
6825 { { STATE_PSRING }, 'i' },
6826 { { STATE_EPS6 }, 'o' }
6827};
6828
6829static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
6830 { { 6 /* art */ }, 'm' }
6831};
6832
6833static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
6834 { { STATE_PSEXCM }, 'i' },
6835 { { STATE_PSRING }, 'i' },
6836 { { STATE_EPS6 }, 'm' }
6837};
6838
6839static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
6840 { { 6 /* art */ }, 'o' }
6841};
6842
6843static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
6844 { { STATE_PSEXCM }, 'i' },
6845 { { STATE_PSRING }, 'i' },
6846 { { STATE_EPS7 }, 'i' }
6847};
6848
6849static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
6850 { { 6 /* art */ }, 'i' }
6851};
6852
6853static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
6854 { { STATE_PSEXCM }, 'i' },
6855 { { STATE_PSRING }, 'i' },
6856 { { STATE_EPS7 }, 'o' }
6857};
6858
6859static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
6860 { { 6 /* art */ }, 'm' }
6861};
6862
6863static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
6864 { { STATE_PSEXCM }, 'i' },
6865 { { STATE_PSRING }, 'i' },
6866 { { STATE_EPS7 }, 'm' }
6867};
6868
6869static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
6870 { { 6 /* art */ }, 'o' }
6871};
6872
6873static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
6874 { { STATE_PSEXCM }, 'i' },
6875 { { STATE_PSRING }, 'i' },
6876 { { STATE_EXCVADDR }, 'i' }
6877};
6878
6879static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
6880 { { 6 /* art */ }, 'i' }
6881};
6882
6883static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
6884 { { STATE_PSEXCM }, 'i' },
6885 { { STATE_PSRING }, 'i' },
6886 { { STATE_EXCVADDR }, 'o' }
6887};
6888
6889static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
6890 { { 6 /* art */ }, 'm' }
6891};
6892
6893static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
6894 { { STATE_PSEXCM }, 'i' },
6895 { { STATE_PSRING }, 'i' },
6896 { { STATE_EXCVADDR }, 'm' }
6897};
6898
6899static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
6900 { { 6 /* art */ }, 'o' }
6901};
6902
6903static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
6904 { { STATE_PSEXCM }, 'i' },
6905 { { STATE_PSRING }, 'i' },
6906 { { STATE_DEPC }, 'i' }
6907};
6908
6909static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
6910 { { 6 /* art */ }, 'i' }
6911};
6912
6913static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
6914 { { STATE_PSEXCM }, 'i' },
6915 { { STATE_PSRING }, 'i' },
6916 { { STATE_DEPC }, 'o' }
6917};
6918
6919static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
6920 { { 6 /* art */ }, 'm' }
6921};
6922
6923static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
6924 { { STATE_PSEXCM }, 'i' },
6925 { { STATE_PSRING }, 'i' },
6926 { { STATE_DEPC }, 'm' }
6927};
6928
6929static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
6930 { { 6 /* art */ }, 'o' }
6931};
6932
6933static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
6934 { { STATE_PSEXCM }, 'i' },
6935 { { STATE_PSRING }, 'i' },
6936 { { STATE_EXCCAUSE }, 'i' },
6937 { { STATE_XTSYNC }, 'i' }
6938};
6939
6940static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
6941 { { 6 /* art */ }, 'i' }
6942};
6943
6944static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
6945 { { STATE_PSEXCM }, 'i' },
6946 { { STATE_PSRING }, 'i' },
6947 { { STATE_EXCCAUSE }, 'o' }
6948};
6949
6950static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
6951 { { 6 /* art */ }, 'm' }
6952};
6953
6954static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
6955 { { STATE_PSEXCM }, 'i' },
6956 { { STATE_PSRING }, 'i' },
6957 { { STATE_EXCCAUSE }, 'm' }
6958};
6959
6960static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
6961 { { 6 /* art */ }, 'o' }
6962};
6963
6964static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
6965 { { STATE_PSEXCM }, 'i' },
6966 { { STATE_PSRING }, 'i' },
6967 { { STATE_MISC0 }, 'i' }
6968};
6969
6970static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
6971 { { 6 /* art */ }, 'i' }
6972};
6973
6974static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
6975 { { STATE_PSEXCM }, 'i' },
6976 { { STATE_PSRING }, 'i' },
6977 { { STATE_MISC0 }, 'o' }
6978};
6979
6980static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
6981 { { 6 /* art */ }, 'm' }
6982};
6983
6984static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
6985 { { STATE_PSEXCM }, 'i' },
6986 { { STATE_PSRING }, 'i' },
6987 { { STATE_MISC0 }, 'm' }
6988};
6989
6990static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
6991 { { 6 /* art */ }, 'o' }
6992};
6993
6994static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
6995 { { STATE_PSEXCM }, 'i' },
6996 { { STATE_PSRING }, 'i' },
6997 { { STATE_MISC1 }, 'i' }
6998};
6999
7000static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
7001 { { 6 /* art */ }, 'i' }
7002};
7003
7004static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
7005 { { STATE_PSEXCM }, 'i' },
7006 { { STATE_PSRING }, 'i' },
7007 { { STATE_MISC1 }, 'o' }
7008};
7009
7010static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
7011 { { 6 /* art */ }, 'm' }
7012};
7013
7014static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
7015 { { STATE_PSEXCM }, 'i' },
7016 { { STATE_PSRING }, 'i' },
7017 { { STATE_MISC1 }, 'm' }
7018};
7019
7020static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_args[] = {
7021 { { 6 /* art */ }, 'o' }
7022};
7023
7024static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_stateArgs[] = {
7025 { { STATE_PSEXCM }, 'i' },
7026 { { STATE_PSRING }, 'i' },
7027 { { STATE_MISC2 }, 'i' }
7028};
7029
7030static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_args[] = {
7031 { { 6 /* art */ }, 'i' }
7032};
7033
7034static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_stateArgs[] = {
7035 { { STATE_PSEXCM }, 'i' },
7036 { { STATE_PSRING }, 'i' },
7037 { { STATE_MISC2 }, 'o' }
7038};
7039
7040static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_args[] = {
7041 { { 6 /* art */ }, 'm' }
7042};
7043
7044static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_stateArgs[] = {
7045 { { STATE_PSEXCM }, 'i' },
7046 { { STATE_PSRING }, 'i' },
7047 { { STATE_MISC2 }, 'm' }
7048};
7049
7050static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_args[] = {
7051 { { 6 /* art */ }, 'o' }
7052};
7053
7054static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_stateArgs[] = {
7055 { { STATE_PSEXCM }, 'i' },
7056 { { STATE_PSRING }, 'i' },
7057 { { STATE_MISC3 }, 'i' }
7058};
7059
7060static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_args[] = {
7061 { { 6 /* art */ }, 'i' }
7062};
7063
7064static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_stateArgs[] = {
7065 { { STATE_PSEXCM }, 'i' },
7066 { { STATE_PSRING }, 'i' },
7067 { { STATE_MISC3 }, 'o' }
7068};
7069
7070static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_args[] = {
7071 { { 6 /* art */ }, 'm' }
7072};
7073
7074static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_stateArgs[] = {
7075 { { STATE_PSEXCM }, 'i' },
7076 { { STATE_PSRING }, 'i' },
7077 { { STATE_MISC3 }, 'm' }
7078};
7079
7080static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
7081 { { 6 /* art */ }, 'o' }
7082};
7083
7084static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
7085 { { STATE_PSEXCM }, 'i' },
7086 { { STATE_PSRING }, 'i' }
7087};
7088
7089static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
7090 { { 6 /* art */ }, 'o' }
7091};
7092
7093static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
7094 { { STATE_PSEXCM }, 'i' },
7095 { { STATE_PSRING }, 'i' },
7096 { { STATE_VECBASE }, 'i' }
7097};
7098
7099static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
7100 { { 6 /* art */ }, 'i' }
7101};
7102
7103static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
7104 { { STATE_PSEXCM }, 'i' },
7105 { { STATE_PSRING }, 'i' },
7106 { { STATE_VECBASE }, 'o' }
7107};
7108
7109static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
7110 { { 6 /* art */ }, 'm' }
7111};
7112
7113static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
7114 { { STATE_PSEXCM }, 'i' },
7115 { { STATE_PSRING }, 'i' },
7116 { { STATE_VECBASE }, 'm' }
7117};
7118
7119static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
7120 { { 4 /* ars */ }, 'i' },
7121 { { 6 /* art */ }, 'i' }
7122};
7123
7124static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
7125 { { STATE_ACC }, 'o' }
7126};
7127
7128static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
7129 { { 4 /* ars */ }, 'i' },
7130 { { 34 /* my */ }, 'i' }
7131};
7132
7133static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
7134 { { STATE_ACC }, 'o' }
7135};
7136
7137static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
7138 { { 33 /* mx */ }, 'i' },
7139 { { 6 /* art */ }, 'i' }
7140};
7141
7142static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
7143 { { STATE_ACC }, 'o' }
7144};
7145
7146static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
7147 { { 33 /* mx */ }, 'i' },
7148 { { 34 /* my */ }, 'i' }
7149};
7150
7151static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
7152 { { STATE_ACC }, 'o' }
7153};
7154
7155static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
7156 { { 4 /* ars */ }, 'i' },
7157 { { 6 /* art */ }, 'i' }
7158};
7159
7160static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
7161 { { STATE_ACC }, 'm' }
7162};
7163
7164static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
7165 { { 4 /* ars */ }, 'i' },
7166 { { 34 /* my */ }, 'i' }
7167};
7168
7169static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
7170 { { STATE_ACC }, 'm' }
7171};
7172
7173static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
7174 { { 33 /* mx */ }, 'i' },
7175 { { 6 /* art */ }, 'i' }
7176};
7177
7178static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
7179 { { STATE_ACC }, 'm' }
7180};
7181
7182static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
7183 { { 33 /* mx */ }, 'i' },
7184 { { 34 /* my */ }, 'i' }
7185};
7186
7187static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
7188 { { STATE_ACC }, 'm' }
7189};
7190
7191static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
7192 { { 35 /* mw */ }, 'o' },
7193 { { 4 /* ars */ }, 'm' },
7194 { { 33 /* mx */ }, 'i' },
7195 { { 6 /* art */ }, 'i' }
7196};
7197
7198static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
7199 { { STATE_ACC }, 'm' }
7200};
7201
7202static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
7203 { { 35 /* mw */ }, 'o' },
7204 { { 4 /* ars */ }, 'm' },
7205 { { 33 /* mx */ }, 'i' },
7206 { { 34 /* my */ }, 'i' }
7207};
7208
7209static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
7210 { { STATE_ACC }, 'm' }
7211};
7212
7213static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
7214 { { 35 /* mw */ }, 'o' },
7215 { { 4 /* ars */ }, 'm' }
7216};
7217
7218static xtensa_arg_internal Iclass_xt_iclass_mul16_args[] = {
7219 { { 3 /* arr */ }, 'o' },
7220 { { 4 /* ars */ }, 'i' },
7221 { { 6 /* art */ }, 'i' }
7222};
7223
7224static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
7225 { { 6 /* art */ }, 'o' },
7226 { { 36 /* mr0 */ }, 'i' }
7227};
7228
7229static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
7230 { { 6 /* art */ }, 'i' },
7231 { { 36 /* mr0 */ }, 'o' }
7232};
7233
7234static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
7235 { { 6 /* art */ }, 'm' },
7236 { { 36 /* mr0 */ }, 'm' }
7237};
7238
7239static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
7240 { { 6 /* art */ }, 'o' },
7241 { { 37 /* mr1 */ }, 'i' }
7242};
7243
7244static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
7245 { { 6 /* art */ }, 'i' },
7246 { { 37 /* mr1 */ }, 'o' }
7247};
7248
7249static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
7250 { { 6 /* art */ }, 'm' },
7251 { { 37 /* mr1 */ }, 'm' }
7252};
7253
7254static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
7255 { { 6 /* art */ }, 'o' },
7256 { { 38 /* mr2 */ }, 'i' }
7257};
7258
7259static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
7260 { { 6 /* art */ }, 'i' },
7261 { { 38 /* mr2 */ }, 'o' }
7262};
7263
7264static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
7265 { { 6 /* art */ }, 'm' },
7266 { { 38 /* mr2 */ }, 'm' }
7267};
7268
7269static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
7270 { { 6 /* art */ }, 'o' },
7271 { { 39 /* mr3 */ }, 'i' }
7272};
7273
7274static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
7275 { { 6 /* art */ }, 'i' },
7276 { { 39 /* mr3 */ }, 'o' }
7277};
7278
7279static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
7280 { { 6 /* art */ }, 'm' },
7281 { { 39 /* mr3 */ }, 'm' }
7282};
7283
7284static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
7285 { { 6 /* art */ }, 'o' }
7286};
7287
7288static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
7289 { { STATE_ACC }, 'i' }
7290};
7291
7292static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
7293 { { 6 /* art */ }, 'i' }
7294};
7295
7296static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
7297 { { STATE_ACC }, 'm' }
7298};
7299
7300static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
7301 { { 6 /* art */ }, 'm' }
7302};
7303
7304static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
7305 { { STATE_ACC }, 'm' }
7306};
7307
7308static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
7309 { { 6 /* art */ }, 'o' }
7310};
7311
7312static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
7313 { { STATE_ACC }, 'i' }
7314};
7315
7316static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
7317 { { 6 /* art */ }, 'i' }
7318};
7319
7320static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
7321 { { STATE_ACC }, 'm' }
7322};
7323
7324static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
7325 { { 6 /* art */ }, 'm' }
7326};
7327
7328static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
7329 { { STATE_ACC }, 'm' }
7330};
7331
7332static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
7333 { { 70 /* s */ }, 'i' }
7334};
7335
7336static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
7337 { { STATE_PSWOE }, 'o' },
7338 { { STATE_PSCALLINC }, 'o' },
7339 { { STATE_PSOWB }, 'o' },
7340 { { STATE_PSRING }, 'm' },
7341 { { STATE_PSUM }, 'o' },
7342 { { STATE_PSEXCM }, 'm' },
7343 { { STATE_PSINTLEVEL }, 'o' },
7344 { { STATE_EPC1 }, 'i' },
7345 { { STATE_EPC2 }, 'i' },
7346 { { STATE_EPC3 }, 'i' },
7347 { { STATE_EPC4 }, 'i' },
7348 { { STATE_EPC5 }, 'i' },
7349 { { STATE_EPC6 }, 'i' },
7350 { { STATE_EPC7 }, 'i' },
7351 { { STATE_EPS2 }, 'i' },
7352 { { STATE_EPS3 }, 'i' },
7353 { { STATE_EPS4 }, 'i' },
7354 { { STATE_EPS5 }, 'i' },
7355 { { STATE_EPS6 }, 'i' },
7356 { { STATE_EPS7 }, 'i' },
7357 { { STATE_InOCDMode }, 'm' }
7358};
7359
7360static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
7361 { { 70 /* s */ }, 'i' }
7362};
7363
7364static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
7365 { { STATE_PSEXCM }, 'i' },
7366 { { STATE_PSRING }, 'i' },
7367 { { STATE_PSINTLEVEL }, 'o' }
7368};
7369
7370static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
7371 { { 6 /* art */ }, 'o' }
7372};
7373
7374static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
7375 { { STATE_PSEXCM }, 'i' },
7376 { { STATE_PSRING }, 'i' },
7377 { { STATE_INTERRUPT }, 'i' }
7378};
7379
7380static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
7381 { { 6 /* art */ }, 'i' }
7382};
7383
7384static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
7385 { { STATE_PSEXCM }, 'i' },
7386 { { STATE_PSRING }, 'i' },
7387 { { STATE_XTSYNC }, 'o' },
7388 { { STATE_INTERRUPT }, 'm' }
7389};
7390
7391static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
7392 { { 6 /* art */ }, 'i' }
7393};
7394
7395static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
7396 { { STATE_PSEXCM }, 'i' },
7397 { { STATE_PSRING }, 'i' },
7398 { { STATE_XTSYNC }, 'o' },
7399 { { STATE_INTERRUPT }, 'm' }
7400};
7401
7402static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
7403 { { 6 /* art */ }, 'o' }
7404};
7405
7406static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
7407 { { STATE_PSEXCM }, 'i' },
7408 { { STATE_PSRING }, 'i' },
7409 { { STATE_INTENABLE }, 'i' }
7410};
7411
7412static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
7413 { { 6 /* art */ }, 'i' }
7414};
7415
7416static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
7417 { { STATE_PSEXCM }, 'i' },
7418 { { STATE_PSRING }, 'i' },
7419 { { STATE_INTENABLE }, 'o' }
7420};
7421
7422static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
7423 { { 6 /* art */ }, 'm' }
7424};
7425
7426static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
7427 { { STATE_PSEXCM }, 'i' },
7428 { { STATE_PSRING }, 'i' },
7429 { { STATE_INTENABLE }, 'm' }
7430};
7431
7432static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
7433 { { 41 /* imms */ }, 'i' },
7434 { { 40 /* immt */ }, 'i' }
7435};
7436
7437static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
7438 { { STATE_PSEXCM }, 'i' },
7439 { { STATE_PSINTLEVEL }, 'i' }
7440};
7441
7442static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
7443 { { 41 /* imms */ }, 'i' }
7444};
7445
7446static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
7447 { { STATE_PSEXCM }, 'i' },
7448 { { STATE_PSINTLEVEL }, 'i' }
7449};
7450
7451static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
7452 { { 6 /* art */ }, 'o' }
7453};
7454
7455static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
7456 { { STATE_PSEXCM }, 'i' },
7457 { { STATE_PSRING }, 'i' },
7458 { { STATE_DBREAKA0 }, 'i' }
7459};
7460
7461static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
7462 { { 6 /* art */ }, 'i' }
7463};
7464
7465static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
7466 { { STATE_PSEXCM }, 'i' },
7467 { { STATE_PSRING }, 'i' },
7468 { { STATE_DBREAKA0 }, 'o' },
7469 { { STATE_XTSYNC }, 'o' }
7470};
7471
7472static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
7473 { { 6 /* art */ }, 'm' }
7474};
7475
7476static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
7477 { { STATE_PSEXCM }, 'i' },
7478 { { STATE_PSRING }, 'i' },
7479 { { STATE_DBREAKA0 }, 'm' },
7480 { { STATE_XTSYNC }, 'o' }
7481};
7482
7483static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
7484 { { 6 /* art */ }, 'o' }
7485};
7486
7487static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
7488 { { STATE_PSEXCM }, 'i' },
7489 { { STATE_PSRING }, 'i' },
7490 { { STATE_DBREAKC0 }, 'i' }
7491};
7492
7493static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
7494 { { 6 /* art */ }, 'i' }
7495};
7496
7497static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
7498 { { STATE_PSEXCM }, 'i' },
7499 { { STATE_PSRING }, 'i' },
7500 { { STATE_DBREAKC0 }, 'o' },
7501 { { STATE_XTSYNC }, 'o' }
7502};
7503
7504static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
7505 { { 6 /* art */ }, 'm' }
7506};
7507
7508static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
7509 { { STATE_PSEXCM }, 'i' },
7510 { { STATE_PSRING }, 'i' },
7511 { { STATE_DBREAKC0 }, 'm' },
7512 { { STATE_XTSYNC }, 'o' }
7513};
7514
7515static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
7516 { { 6 /* art */ }, 'o' }
7517};
7518
7519static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
7520 { { STATE_PSEXCM }, 'i' },
7521 { { STATE_PSRING }, 'i' },
7522 { { STATE_DBREAKA1 }, 'i' }
7523};
7524
7525static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
7526 { { 6 /* art */ }, 'i' }
7527};
7528
7529static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
7530 { { STATE_PSEXCM }, 'i' },
7531 { { STATE_PSRING }, 'i' },
7532 { { STATE_DBREAKA1 }, 'o' },
7533 { { STATE_XTSYNC }, 'o' }
7534};
7535
7536static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
7537 { { 6 /* art */ }, 'm' }
7538};
7539
7540static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
7541 { { STATE_PSEXCM }, 'i' },
7542 { { STATE_PSRING }, 'i' },
7543 { { STATE_DBREAKA1 }, 'm' },
7544 { { STATE_XTSYNC }, 'o' }
7545};
7546
7547static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
7548 { { 6 /* art */ }, 'o' }
7549};
7550
7551static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
7552 { { STATE_PSEXCM }, 'i' },
7553 { { STATE_PSRING }, 'i' },
7554 { { STATE_DBREAKC1 }, 'i' }
7555};
7556
7557static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
7558 { { 6 /* art */ }, 'i' }
7559};
7560
7561static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
7562 { { STATE_PSEXCM }, 'i' },
7563 { { STATE_PSRING }, 'i' },
7564 { { STATE_DBREAKC1 }, 'o' },
7565 { { STATE_XTSYNC }, 'o' }
7566};
7567
7568static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
7569 { { 6 /* art */ }, 'm' }
7570};
7571
7572static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
7573 { { STATE_PSEXCM }, 'i' },
7574 { { STATE_PSRING }, 'i' },
7575 { { STATE_DBREAKC1 }, 'm' },
7576 { { STATE_XTSYNC }, 'o' }
7577};
7578
7579static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
7580 { { 6 /* art */ }, 'o' }
7581};
7582
7583static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
7584 { { STATE_PSEXCM }, 'i' },
7585 { { STATE_PSRING }, 'i' },
7586 { { STATE_IBREAKA0 }, 'i' }
7587};
7588
7589static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
7590 { { 6 /* art */ }, 'i' }
7591};
7592
7593static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
7594 { { STATE_PSEXCM }, 'i' },
7595 { { STATE_PSRING }, 'i' },
7596 { { STATE_IBREAKA0 }, 'o' }
7597};
7598
7599static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
7600 { { 6 /* art */ }, 'm' }
7601};
7602
7603static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
7604 { { STATE_PSEXCM }, 'i' },
7605 { { STATE_PSRING }, 'i' },
7606 { { STATE_IBREAKA0 }, 'm' }
7607};
7608
7609static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
7610 { { 6 /* art */ }, 'o' }
7611};
7612
7613static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
7614 { { STATE_PSEXCM }, 'i' },
7615 { { STATE_PSRING }, 'i' },
7616 { { STATE_IBREAKA1 }, 'i' }
7617};
7618
7619static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
7620 { { 6 /* art */ }, 'i' }
7621};
7622
7623static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
7624 { { STATE_PSEXCM }, 'i' },
7625 { { STATE_PSRING }, 'i' },
7626 { { STATE_IBREAKA1 }, 'o' }
7627};
7628
7629static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
7630 { { 6 /* art */ }, 'm' }
7631};
7632
7633static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
7634 { { STATE_PSEXCM }, 'i' },
7635 { { STATE_PSRING }, 'i' },
7636 { { STATE_IBREAKA1 }, 'm' }
7637};
7638
7639static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
7640 { { 6 /* art */ }, 'o' }
7641};
7642
7643static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
7644 { { STATE_PSEXCM }, 'i' },
7645 { { STATE_PSRING }, 'i' },
7646 { { STATE_IBREAKENABLE }, 'i' }
7647};
7648
7649static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
7650 { { 6 /* art */ }, 'i' }
7651};
7652
7653static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
7654 { { STATE_PSEXCM }, 'i' },
7655 { { STATE_PSRING }, 'i' },
7656 { { STATE_IBREAKENABLE }, 'o' }
7657};
7658
7659static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
7660 { { 6 /* art */ }, 'm' }
7661};
7662
7663static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
7664 { { STATE_PSEXCM }, 'i' },
7665 { { STATE_PSRING }, 'i' },
7666 { { STATE_IBREAKENABLE }, 'm' }
7667};
7668
7669static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
7670 { { 6 /* art */ }, 'o' }
7671};
7672
7673static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
7674 { { STATE_PSEXCM }, 'i' },
7675 { { STATE_PSRING }, 'i' },
7676 { { STATE_DEBUGCAUSE }, 'i' },
7677 { { STATE_DBNUM }, 'i' }
7678};
7679
7680static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
7681 { { 6 /* art */ }, 'i' }
7682};
7683
7684static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
7685 { { STATE_PSEXCM }, 'i' },
7686 { { STATE_PSRING }, 'i' },
7687 { { STATE_DEBUGCAUSE }, 'o' },
7688 { { STATE_DBNUM }, 'o' }
7689};
7690
7691static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
7692 { { 6 /* art */ }, 'm' }
7693};
7694
7695static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
7696 { { STATE_PSEXCM }, 'i' },
7697 { { STATE_PSRING }, 'i' },
7698 { { STATE_DEBUGCAUSE }, 'm' },
7699 { { STATE_DBNUM }, 'm' }
7700};
7701
7702static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
7703 { { 6 /* art */ }, 'o' }
7704};
7705
7706static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
7707 { { STATE_PSEXCM }, 'i' },
7708 { { STATE_PSRING }, 'i' },
7709 { { STATE_ICOUNT }, 'i' }
7710};
7711
7712static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
7713 { { 6 /* art */ }, 'i' }
7714};
7715
7716static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
7717 { { STATE_PSEXCM }, 'i' },
7718 { { STATE_PSRING }, 'i' },
7719 { { STATE_XTSYNC }, 'o' },
7720 { { STATE_ICOUNT }, 'o' }
7721};
7722
7723static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
7724 { { 6 /* art */ }, 'm' }
7725};
7726
7727static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
7728 { { STATE_PSEXCM }, 'i' },
7729 { { STATE_PSRING }, 'i' },
7730 { { STATE_XTSYNC }, 'o' },
7731 { { STATE_ICOUNT }, 'm' }
7732};
7733
7734static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
7735 { { 6 /* art */ }, 'o' }
7736};
7737
7738static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
7739 { { STATE_PSEXCM }, 'i' },
7740 { { STATE_PSRING }, 'i' },
7741 { { STATE_ICOUNTLEVEL }, 'i' }
7742};
7743
7744static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
7745 { { 6 /* art */ }, 'i' }
7746};
7747
7748static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
7749 { { STATE_PSEXCM }, 'i' },
7750 { { STATE_PSRING }, 'i' },
7751 { { STATE_ICOUNTLEVEL }, 'o' }
7752};
7753
7754static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
7755 { { 6 /* art */ }, 'm' }
7756};
7757
7758static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
7759 { { STATE_PSEXCM }, 'i' },
7760 { { STATE_PSRING }, 'i' },
7761 { { STATE_ICOUNTLEVEL }, 'm' }
7762};
7763
7764static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
7765 { { 6 /* art */ }, 'o' }
7766};
7767
7768static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
7769 { { STATE_PSEXCM }, 'i' },
7770 { { STATE_PSRING }, 'i' },
7771 { { STATE_DDR }, 'i' }
7772};
7773
7774static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
7775 { { 6 /* art */ }, 'i' }
7776};
7777
7778static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
7779 { { STATE_PSEXCM }, 'i' },
7780 { { STATE_PSRING }, 'i' },
7781 { { STATE_XTSYNC }, 'o' },
7782 { { STATE_DDR }, 'o' }
7783};
7784
7785static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
7786 { { 6 /* art */ }, 'm' }
7787};
7788
7789static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
7790 { { STATE_PSEXCM }, 'i' },
7791 { { STATE_PSRING }, 'i' },
7792 { { STATE_XTSYNC }, 'o' },
7793 { { STATE_DDR }, 'm' }
7794};
7795
7796static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
7797 { { 41 /* imms */ }, 'i' }
7798};
7799
7800static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
7801 { { STATE_InOCDMode }, 'm' },
7802 { { STATE_EPC6 }, 'i' },
7803 { { STATE_PSWOE }, 'o' },
7804 { { STATE_PSCALLINC }, 'o' },
7805 { { STATE_PSOWB }, 'o' },
7806 { { STATE_PSRING }, 'o' },
7807 { { STATE_PSUM }, 'o' },
7808 { { STATE_PSEXCM }, 'o' },
7809 { { STATE_PSINTLEVEL }, 'o' },
7810 { { STATE_EPS6 }, 'i' }
7811};
7812
7813static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
7814 { { STATE_InOCDMode }, 'm' }
7815};
7816
7817static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
7818 { { 6 /* art */ }, 'i' }
7819};
7820
7821static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
7822 { { STATE_PSEXCM }, 'i' },
7823 { { STATE_PSRING }, 'i' },
7824 { { STATE_XTSYNC }, 'o' }
7825};
7826
7827static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = {
7828 { { 44 /* br */ }, 'o' },
7829 { { 43 /* bs */ }, 'i' },
7830 { { 42 /* bt */ }, 'i' }
7831};
7832
7833static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = {
7834 { { 42 /* bt */ }, 'o' },
7835 { { 49 /* bs4 */ }, 'i' }
7836};
7837
7838static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = {
7839 { { 42 /* bt */ }, 'o' },
7840 { { 52 /* bs8 */ }, 'i' }
7841};
7842
7843static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = {
7844 { { 43 /* bs */ }, 'i' },
7845 { { 28 /* label8 */ }, 'i' }
7846};
7847
7848static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = {
7849 { { 3 /* arr */ }, 'm' },
7850 { { 4 /* ars */ }, 'i' },
7851 { { 42 /* bt */ }, 'i' }
7852};
7853
7854static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = {
7855 { { 6 /* art */ }, 'o' },
7856 { { 57 /* brall */ }, 'i' }
7857};
7858
7859static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = {
7860 { { 6 /* art */ }, 'i' },
7861 { { 57 /* brall */ }, 'o' }
7862};
7863
7864static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = {
7865 { { 6 /* art */ }, 'm' },
7866 { { 57 /* brall */ }, 'm' }
7867};
7868
7869static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
7870 { { 6 /* art */ }, 'o' }
7871};
7872
7873static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
7874 { { STATE_PSEXCM }, 'i' },
7875 { { STATE_PSRING }, 'i' },
7876 { { STATE_CCOUNT }, 'i' }
7877};
7878
7879static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
7880 { { 6 /* art */ }, 'i' }
7881};
7882
7883static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
7884 { { STATE_PSEXCM }, 'i' },
7885 { { STATE_PSRING }, 'i' },
7886 { { STATE_XTSYNC }, 'o' },
7887 { { STATE_CCOUNT }, 'o' }
7888};
7889
7890static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
7891 { { 6 /* art */ }, 'm' }
7892};
7893
7894static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
7895 { { STATE_PSEXCM }, 'i' },
7896 { { STATE_PSRING }, 'i' },
7897 { { STATE_XTSYNC }, 'o' },
7898 { { STATE_CCOUNT }, 'm' }
7899};
7900
7901static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
7902 { { 6 /* art */ }, 'o' }
7903};
7904
7905static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
7906 { { STATE_PSEXCM }, 'i' },
7907 { { STATE_PSRING }, 'i' },
7908 { { STATE_CCOMPARE0 }, 'i' }
7909};
7910
7911static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
7912 { { 6 /* art */ }, 'i' }
7913};
7914
7915static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
7916 { { STATE_PSEXCM }, 'i' },
7917 { { STATE_PSRING }, 'i' },
7918 { { STATE_CCOMPARE0 }, 'o' },
7919 { { STATE_INTERRUPT }, 'm' }
7920};
7921
7922static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
7923 { { 6 /* art */ }, 'm' }
7924};
7925
7926static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
7927 { { STATE_PSEXCM }, 'i' },
7928 { { STATE_PSRING }, 'i' },
7929 { { STATE_CCOMPARE0 }, 'm' },
7930 { { STATE_INTERRUPT }, 'm' }
7931};
7932
7933static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
7934 { { 6 /* art */ }, 'o' }
7935};
7936
7937static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
7938 { { STATE_PSEXCM }, 'i' },
7939 { { STATE_PSRING }, 'i' },
7940 { { STATE_CCOMPARE1 }, 'i' }
7941};
7942
7943static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
7944 { { 6 /* art */ }, 'i' }
7945};
7946
7947static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
7948 { { STATE_PSEXCM }, 'i' },
7949 { { STATE_PSRING }, 'i' },
7950 { { STATE_CCOMPARE1 }, 'o' },
7951 { { STATE_INTERRUPT }, 'm' }
7952};
7953
7954static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
7955 { { 6 /* art */ }, 'm' }
7956};
7957
7958static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
7959 { { STATE_PSEXCM }, 'i' },
7960 { { STATE_PSRING }, 'i' },
7961 { { STATE_CCOMPARE1 }, 'm' },
7962 { { STATE_INTERRUPT }, 'm' }
7963};
7964
7965static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
7966 { { 6 /* art */ }, 'o' }
7967};
7968
7969static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
7970 { { STATE_PSEXCM }, 'i' },
7971 { { STATE_PSRING }, 'i' },
7972 { { STATE_CCOMPARE2 }, 'i' }
7973};
7974
7975static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
7976 { { 6 /* art */ }, 'i' }
7977};
7978
7979static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
7980 { { STATE_PSEXCM }, 'i' },
7981 { { STATE_PSRING }, 'i' },
7982 { { STATE_CCOMPARE2 }, 'o' },
7983 { { STATE_INTERRUPT }, 'm' }
7984};
7985
7986static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
7987 { { 6 /* art */ }, 'm' }
7988};
7989
7990static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
7991 { { STATE_PSEXCM }, 'i' },
7992 { { STATE_PSRING }, 'i' },
7993 { { STATE_CCOMPARE2 }, 'm' },
7994 { { STATE_INTERRUPT }, 'm' }
7995};
7996
7997static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
7998 { { 4 /* ars */ }, 'i' },
7999 { { 21 /* uimm8x4 */ }, 'i' }
8000};
8001
8002static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = {
8003 { { 4 /* ars */ }, 'i' },
8004 { { 22 /* uimm4x16 */ }, 'i' }
8005};
8006
8007static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = {
8008 { { STATE_PSEXCM }, 'i' },
8009 { { STATE_PSRING }, 'i' }
8010};
8011
8012static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
8013 { { 4 /* ars */ }, 'i' },
8014 { { 21 /* uimm8x4 */ }, 'i' }
8015};
8016
8017static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
8018 { { STATE_PSEXCM }, 'i' },
8019 { { STATE_PSRING }, 'i' }
8020};
8021
8022static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
8023 { { 6 /* art */ }, 'o' },
8024 { { 4 /* ars */ }, 'i' }
8025};
8026
8027static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
8028 { { STATE_PSEXCM }, 'i' },
8029 { { STATE_PSRING }, 'i' }
8030};
8031
8032static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
8033 { { 6 /* art */ }, 'i' },
8034 { { 4 /* ars */ }, 'i' }
8035};
8036
8037static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
8038 { { STATE_PSEXCM }, 'i' },
8039 { { STATE_PSRING }, 'i' }
8040};
8041
8042static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
8043 { { 4 /* ars */ }, 'i' },
8044 { { 21 /* uimm8x4 */ }, 'i' }
8045};
8046
8047static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
8048 { { 4 /* ars */ }, 'i' },
8049 { { 22 /* uimm4x16 */ }, 'i' }
8050};
8051
8052static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
8053 { { STATE_PSEXCM }, 'i' },
8054 { { STATE_PSRING }, 'i' }
8055};
8056
8057static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
8058 { { 4 /* ars */ }, 'i' },
8059 { { 21 /* uimm8x4 */ }, 'i' }
8060};
8061
8062static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
8063 { { STATE_PSEXCM }, 'i' },
8064 { { STATE_PSRING }, 'i' }
8065};
8066
8067static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
8068 { { 4 /* ars */ }, 'i' },
8069 { { 21 /* uimm8x4 */ }, 'i' }
8070};
8071
8072static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = {
8073 { { 4 /* ars */ }, 'i' },
8074 { { 22 /* uimm4x16 */ }, 'i' }
8075};
8076
8077static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = {
8078 { { STATE_PSEXCM }, 'i' },
8079 { { STATE_PSRING }, 'i' }
8080};
8081
8082static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
8083 { { 6 /* art */ }, 'i' },
8084 { { 4 /* ars */ }, 'i' }
8085};
8086
8087static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
8088 { { STATE_PSEXCM }, 'i' },
8089 { { STATE_PSRING }, 'i' }
8090};
8091
8092static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
8093 { { 6 /* art */ }, 'o' },
8094 { { 4 /* ars */ }, 'i' }
8095};
8096
8097static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
8098 { { STATE_PSEXCM }, 'i' },
8099 { { STATE_PSRING }, 'i' }
8100};
8101
8102static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
8103 { { 6 /* art */ }, 'i' }
8104};
8105
8106static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
8107 { { STATE_PSEXCM }, 'i' },
8108 { { STATE_PSRING }, 'i' },
8109 { { STATE_PTBASE }, 'o' },
8110 { { STATE_XTSYNC }, 'o' }
8111};
8112
8113static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
8114 { { 6 /* art */ }, 'o' }
8115};
8116
8117static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
8118 { { STATE_PSEXCM }, 'i' },
8119 { { STATE_PSRING }, 'i' },
8120 { { STATE_PTBASE }, 'i' },
8121 { { STATE_EXCVADDR }, 'i' }
8122};
8123
8124static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
8125 { { 6 /* art */ }, 'm' }
8126};
8127
8128static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
8129 { { STATE_PSEXCM }, 'i' },
8130 { { STATE_PSRING }, 'i' },
8131 { { STATE_PTBASE }, 'm' },
8132 { { STATE_EXCVADDR }, 'i' },
8133 { { STATE_XTSYNC }, 'o' }
8134};
8135
8136static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
8137 { { 6 /* art */ }, 'o' }
8138};
8139
8140static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
8141 { { STATE_PSEXCM }, 'i' },
8142 { { STATE_PSRING }, 'i' },
8143 { { STATE_ASID3 }, 'i' },
8144 { { STATE_ASID2 }, 'i' },
8145 { { STATE_ASID1 }, 'i' }
8146};
8147
8148static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
8149 { { 6 /* art */ }, 'i' }
8150};
8151
8152static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
8153 { { STATE_XTSYNC }, 'o' },
8154 { { STATE_PSEXCM }, 'i' },
8155 { { STATE_PSRING }, 'i' },
8156 { { STATE_ASID3 }, 'o' },
8157 { { STATE_ASID2 }, 'o' },
8158 { { STATE_ASID1 }, 'o' }
8159};
8160
8161static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
8162 { { 6 /* art */ }, 'm' }
8163};
8164
8165static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
8166 { { STATE_XTSYNC }, 'o' },
8167 { { STATE_PSEXCM }, 'i' },
8168 { { STATE_PSRING }, 'i' },
8169 { { STATE_ASID3 }, 'm' },
8170 { { STATE_ASID2 }, 'm' },
8171 { { STATE_ASID1 }, 'm' }
8172};
8173
8174static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
8175 { { 6 /* art */ }, 'o' }
8176};
8177
8178static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
8179 { { STATE_PSEXCM }, 'i' },
8180 { { STATE_PSRING }, 'i' },
8181 { { STATE_INSTPGSZID4 }, 'i' }
8182};
8183
8184static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
8185 { { 6 /* art */ }, 'i' }
8186};
8187
8188static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
8189 { { STATE_XTSYNC }, 'o' },
8190 { { STATE_PSEXCM }, 'i' },
8191 { { STATE_PSRING }, 'i' },
8192 { { STATE_INSTPGSZID4 }, 'o' }
8193};
8194
8195static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
8196 { { 6 /* art */ }, 'm' }
8197};
8198
8199static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
8200 { { STATE_XTSYNC }, 'o' },
8201 { { STATE_PSEXCM }, 'i' },
8202 { { STATE_PSRING }, 'i' },
8203 { { STATE_INSTPGSZID4 }, 'm' }
8204};
8205
8206static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
8207 { { 6 /* art */ }, 'o' }
8208};
8209
8210static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
8211 { { STATE_PSEXCM }, 'i' },
8212 { { STATE_PSRING }, 'i' },
8213 { { STATE_DATAPGSZID4 }, 'i' }
8214};
8215
8216static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
8217 { { 6 /* art */ }, 'i' }
8218};
8219
8220static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
8221 { { STATE_XTSYNC }, 'o' },
8222 { { STATE_PSEXCM }, 'i' },
8223 { { STATE_PSRING }, 'i' },
8224 { { STATE_DATAPGSZID4 }, 'o' }
8225};
8226
8227static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
8228 { { 6 /* art */ }, 'm' }
8229};
8230
8231static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
8232 { { STATE_XTSYNC }, 'o' },
8233 { { STATE_PSEXCM }, 'i' },
8234 { { STATE_PSRING }, 'i' },
8235 { { STATE_DATAPGSZID4 }, 'm' }
8236};
8237
8238static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
8239 { { 4 /* ars */ }, 'i' }
8240};
8241
8242static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
8243 { { STATE_PSEXCM }, 'i' },
8244 { { STATE_PSRING }, 'i' },
8245 { { STATE_XTSYNC }, 'o' }
8246};
8247
8248static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
8249 { { 6 /* art */ }, 'o' },
8250 { { 4 /* ars */ }, 'i' }
8251};
8252
8253static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
8254 { { STATE_PSEXCM }, 'i' },
8255 { { STATE_PSRING }, 'i' }
8256};
8257
8258static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
8259 { { 6 /* art */ }, 'i' },
8260 { { 4 /* ars */ }, 'i' }
8261};
8262
8263static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
8264 { { STATE_PSEXCM }, 'i' },
8265 { { STATE_PSRING }, 'i' },
8266 { { STATE_XTSYNC }, 'o' }
8267};
8268
8269static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
8270 { { 4 /* ars */ }, 'i' }
8271};
8272
8273static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
8274 { { STATE_PSEXCM }, 'i' },
8275 { { STATE_PSRING }, 'i' }
8276};
8277
8278static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
8279 { { 6 /* art */ }, 'o' },
8280 { { 4 /* ars */ }, 'i' }
8281};
8282
8283static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
8284 { { STATE_PSEXCM }, 'i' },
8285 { { STATE_PSRING }, 'i' }
8286};
8287
8288static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
8289 { { 6 /* art */ }, 'i' },
8290 { { 4 /* ars */ }, 'i' }
8291};
8292
8293static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
8294 { { STATE_PSEXCM }, 'i' },
8295 { { STATE_PSRING }, 'i' }
8296};
8297
8298static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
8299 { { STATE_PTBASE }, 'i' },
8300 { { STATE_EXCVADDR }, 'i' }
8301};
8302
8303static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
8304 { { STATE_EXCVADDR }, 'i' }
8305};
8306
8307static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
8308 { { STATE_EXCVADDR }, 'i' }
8309};
8310
8311static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
8312 { { 6 /* art */ }, 'o' }
8313};
8314
8315static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
8316 { { STATE_PSEXCM }, 'i' },
8317 { { STATE_PSRING }, 'i' },
8318 { { STATE_CPENABLE }, 'i' }
8319};
8320
8321static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
8322 { { 6 /* art */ }, 'i' }
8323};
8324
8325static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
8326 { { STATE_PSEXCM }, 'i' },
8327 { { STATE_PSRING }, 'i' },
8328 { { STATE_CPENABLE }, 'o' }
8329};
8330
8331static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
8332 { { 6 /* art */ }, 'm' }
8333};
8334
8335static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
8336 { { STATE_PSEXCM }, 'i' },
8337 { { STATE_PSRING }, 'i' },
8338 { { STATE_CPENABLE }, 'm' }
8339};
8340
8341static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
8342 { { 3 /* arr */ }, 'o' },
8343 { { 4 /* ars */ }, 'i' },
8344 { { 58 /* tp7 */ }, 'i' }
8345};
8346
8347static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
8348 { { 3 /* arr */ }, 'o' },
8349 { { 4 /* ars */ }, 'i' },
8350 { { 6 /* art */ }, 'i' }
8351};
8352
8353static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
8354 { { 6 /* art */ }, 'o' },
8355 { { 4 /* ars */ }, 'i' }
8356};
8357
8358static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
8359 { { 3 /* arr */ }, 'o' },
8360 { { 4 /* ars */ }, 'i' },
8361 { { 58 /* tp7 */ }, 'i' }
8362};
8363
8364static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
8365 { { 6 /* art */ }, 'o' },
8366 { { 4 /* ars */ }, 'i' },
8367 { { 21 /* uimm8x4 */ }, 'i' }
8368};
8369
8370static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
8371 { { 6 /* art */ }, 'i' },
8372 { { 4 /* ars */ }, 'i' },
8373 { { 21 /* uimm8x4 */ }, 'i' }
8374};
8375
8376static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
8377 { { 6 /* art */ }, 'm' },
8378 { { 4 /* ars */ }, 'i' },
8379 { { 21 /* uimm8x4 */ }, 'i' }
8380};
8381
8382static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
8383 { { STATE_SCOMPARE1 }, 'i' },
8384 { { STATE_SCOMPARE1 }, 'i' }
8385};
8386
8387static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
8388 { { 6 /* art */ }, 'o' }
8389};
8390
8391static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
8392 { { STATE_SCOMPARE1 }, 'i' }
8393};
8394
8395static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
8396 { { 6 /* art */ }, 'i' }
8397};
8398
8399static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
8400 { { STATE_SCOMPARE1 }, 'o' }
8401};
8402
8403static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
8404 { { 6 /* art */ }, 'm' }
8405};
8406
8407static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
8408 { { STATE_SCOMPARE1 }, 'm' }
8409};
8410
8411static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
8412 { { 3 /* arr */ }, 'o' },
8413 { { 4 /* ars */ }, 'i' },
8414 { { 6 /* art */ }, 'i' }
8415};
8416
8417static xtensa_arg_internal Iclass_xt_mul32_args[] = {
8418 { { 3 /* arr */ }, 'o' },
8419 { { 4 /* ars */ }, 'i' },
8420 { { 6 /* art */ }, 'i' }
8421};
8422
8423static xtensa_arg_internal Iclass_rur_fcr_args[] = {
8424 { { 3 /* arr */ }, 'o' }
8425};
8426
8427static xtensa_arg_internal Iclass_rur_fcr_stateArgs[] = {
8428 { { STATE_RoundMode }, 'i' },
8429 { { STATE_InvalidEnable }, 'i' },
8430 { { STATE_DivZeroEnable }, 'i' },
8431 { { STATE_OverflowEnable }, 'i' },
8432 { { STATE_UnderflowEnable }, 'i' },
8433 { { STATE_InexactEnable }, 'i' },
8434 { { STATE_FPreserved20 }, 'i' },
8435 { { STATE_FPreserved5 }, 'i' },
8436 { { STATE_CPENABLE }, 'i' }
8437};
8438
8439static xtensa_arg_internal Iclass_wur_fcr_args[] = {
8440 { { 6 /* art */ }, 'i' }
8441};
8442
8443static xtensa_arg_internal Iclass_wur_fcr_stateArgs[] = {
8444 { { STATE_RoundMode }, 'o' },
8445 { { STATE_InvalidEnable }, 'o' },
8446 { { STATE_DivZeroEnable }, 'o' },
8447 { { STATE_OverflowEnable }, 'o' },
8448 { { STATE_UnderflowEnable }, 'o' },
8449 { { STATE_InexactEnable }, 'o' },
8450 { { STATE_FPreserved20 }, 'o' },
8451 { { STATE_FPreserved5 }, 'o' },
8452 { { STATE_CPENABLE }, 'i' }
8453};
8454
8455static xtensa_arg_internal Iclass_rur_fsr_args[] = {
8456 { { 3 /* arr */ }, 'o' }
8457};
8458
8459static xtensa_arg_internal Iclass_rur_fsr_stateArgs[] = {
8460 { { STATE_InvalidFlag }, 'i' },
8461 { { STATE_DivZeroFlag }, 'i' },
8462 { { STATE_OverflowFlag }, 'i' },
8463 { { STATE_UnderflowFlag }, 'i' },
8464 { { STATE_InexactFlag }, 'i' },
8465 { { STATE_FPreserved20a }, 'i' },
8466 { { STATE_FPreserved7 }, 'i' },
8467 { { STATE_CPENABLE }, 'i' }
8468};
8469
8470static xtensa_arg_internal Iclass_wur_fsr_args[] = {
8471 { { 6 /* art */ }, 'i' }
8472};
8473
8474static xtensa_arg_internal Iclass_wur_fsr_stateArgs[] = {
8475 { { STATE_InvalidFlag }, 'o' },
8476 { { STATE_DivZeroFlag }, 'o' },
8477 { { STATE_OverflowFlag }, 'o' },
8478 { { STATE_UnderflowFlag }, 'o' },
8479 { { STATE_InexactFlag }, 'o' },
8480 { { STATE_FPreserved20a }, 'o' },
8481 { { STATE_FPreserved7 }, 'o' },
8482 { { STATE_CPENABLE }, 'i' }
8483};
8484
8485static xtensa_arg_internal Iclass_fp_args[] = {
8486 { { 62 /* frr */ }, 'o' },
8487 { { 63 /* frs */ }, 'i' },
8488 { { 64 /* frt */ }, 'i' }
8489};
8490
8491static xtensa_arg_internal Iclass_fp_stateArgs[] = {
8492 { { STATE_RoundMode }, 'i' },
8493 { { STATE_CPENABLE }, 'i' }
8494};
8495
8496static xtensa_arg_internal Iclass_fp_mac_args[] = {
8497 { { 62 /* frr */ }, 'm' },
8498 { { 63 /* frs */ }, 'i' },
8499 { { 64 /* frt */ }, 'i' }
8500};
8501
8502static xtensa_arg_internal Iclass_fp_mac_stateArgs[] = {
8503 { { STATE_RoundMode }, 'i' },
8504 { { STATE_CPENABLE }, 'i' }
8505};
8506
8507static xtensa_arg_internal Iclass_fp_cmov_args[] = {
8508 { { 62 /* frr */ }, 'm' },
8509 { { 63 /* frs */ }, 'i' },
8510 { { 42 /* bt */ }, 'i' }
8511};
8512
8513static xtensa_arg_internal Iclass_fp_cmov_stateArgs[] = {
8514 { { STATE_CPENABLE }, 'i' }
8515};
8516
8517static xtensa_arg_internal Iclass_fp_mov_args[] = {
8518 { { 62 /* frr */ }, 'm' },
8519 { { 63 /* frs */ }, 'i' },
8520 { { 6 /* art */ }, 'i' }
8521};
8522
8523static xtensa_arg_internal Iclass_fp_mov_stateArgs[] = {
8524 { { STATE_CPENABLE }, 'i' }
8525};
8526
8527static xtensa_arg_internal Iclass_fp_mov2_args[] = {
8528 { { 62 /* frr */ }, 'o' },
8529 { { 63 /* frs */ }, 'i' }
8530};
8531
8532static xtensa_arg_internal Iclass_fp_mov2_stateArgs[] = {
8533 { { STATE_CPENABLE }, 'i' }
8534};
8535
8536static xtensa_arg_internal Iclass_fp_cmp_args[] = {
8537 { { 44 /* br */ }, 'o' },
8538 { { 63 /* frs */ }, 'i' },
8539 { { 64 /* frt */ }, 'i' }
8540};
8541
8542static xtensa_arg_internal Iclass_fp_cmp_stateArgs[] = {
8543 { { STATE_CPENABLE }, 'i' }
8544};
8545
8546static xtensa_arg_internal Iclass_fp_float_args[] = {
8547 { { 62 /* frr */ }, 'o' },
8548 { { 4 /* ars */ }, 'i' },
8549 { { 65 /* t */ }, 'i' }
8550};
8551
8552static xtensa_arg_internal Iclass_fp_float_stateArgs[] = {
8553 { { STATE_RoundMode }, 'i' },
8554 { { STATE_CPENABLE }, 'i' }
8555};
8556
8557static xtensa_arg_internal Iclass_fp_int_args[] = {
8558 { { 3 /* arr */ }, 'o' },
8559 { { 63 /* frs */ }, 'i' },
8560 { { 65 /* t */ }, 'i' }
8561};
8562
8563static xtensa_arg_internal Iclass_fp_int_stateArgs[] = {
8564 { { STATE_CPENABLE }, 'i' }
8565};
8566
8567static xtensa_arg_internal Iclass_fp_rfr_args[] = {
8568 { { 3 /* arr */ }, 'o' },
8569 { { 63 /* frs */ }, 'i' }
8570};
8571
8572static xtensa_arg_internal Iclass_fp_rfr_stateArgs[] = {
8573 { { STATE_CPENABLE }, 'i' }
8574};
8575
8576static xtensa_arg_internal Iclass_fp_wfr_args[] = {
8577 { { 62 /* frr */ }, 'o' },
8578 { { 4 /* ars */ }, 'i' }
8579};
8580
8581static xtensa_arg_internal Iclass_fp_wfr_stateArgs[] = {
8582 { { STATE_CPENABLE }, 'i' }
8583};
8584
8585static xtensa_arg_internal Iclass_fp_lsi_args[] = {
8586 { { 64 /* frt */ }, 'o' },
8587 { { 4 /* ars */ }, 'i' },
8588 { { 61 /* cimm8x4 */ }, 'i' }
8589};
8590
8591static xtensa_arg_internal Iclass_fp_lsi_stateArgs[] = {
8592 { { STATE_CPENABLE }, 'i' }
8593};
8594
8595static xtensa_arg_internal Iclass_fp_lsiu_args[] = {
8596 { { 64 /* frt */ }, 'o' },
8597 { { 4 /* ars */ }, 'm' },
8598 { { 61 /* cimm8x4 */ }, 'i' }
8599};
8600
8601static xtensa_arg_internal Iclass_fp_lsiu_stateArgs[] = {
8602 { { STATE_CPENABLE }, 'i' }
8603};
8604
8605static xtensa_arg_internal Iclass_fp_lsx_args[] = {
8606 { { 62 /* frr */ }, 'o' },
8607 { { 4 /* ars */ }, 'i' },
8608 { { 6 /* art */ }, 'i' }
8609};
8610
8611static xtensa_arg_internal Iclass_fp_lsx_stateArgs[] = {
8612 { { STATE_CPENABLE }, 'i' }
8613};
8614
8615static xtensa_arg_internal Iclass_fp_lsxu_args[] = {
8616 { { 62 /* frr */ }, 'o' },
8617 { { 4 /* ars */ }, 'm' },
8618 { { 6 /* art */ }, 'i' }
8619};
8620
8621static xtensa_arg_internal Iclass_fp_lsxu_stateArgs[] = {
8622 { { STATE_CPENABLE }, 'i' }
8623};
8624
8625static xtensa_arg_internal Iclass_fp_ssi_args[] = {
8626 { { 64 /* frt */ }, 'i' },
8627 { { 4 /* ars */ }, 'i' },
8628 { { 61 /* cimm8x4 */ }, 'i' }
8629};
8630
8631static xtensa_arg_internal Iclass_fp_ssi_stateArgs[] = {
8632 { { STATE_CPENABLE }, 'i' }
8633};
8634
8635static xtensa_arg_internal Iclass_fp_ssiu_args[] = {
8636 { { 64 /* frt */ }, 'i' },
8637 { { 4 /* ars */ }, 'm' },
8638 { { 61 /* cimm8x4 */ }, 'i' }
8639};
8640
8641static xtensa_arg_internal Iclass_fp_ssiu_stateArgs[] = {
8642 { { STATE_CPENABLE }, 'i' }
8643};
8644
8645static xtensa_arg_internal Iclass_fp_ssx_args[] = {
8646 { { 62 /* frr */ }, 'i' },
8647 { { 4 /* ars */ }, 'i' },
8648 { { 6 /* art */ }, 'i' }
8649};
8650
8651static xtensa_arg_internal Iclass_fp_ssx_stateArgs[] = {
8652 { { STATE_CPENABLE }, 'i' }
8653};
8654
8655static xtensa_arg_internal Iclass_fp_ssxu_args[] = {
8656 { { 62 /* frr */ }, 'i' },
8657 { { 4 /* ars */ }, 'm' },
8658 { { 6 /* art */ }, 'i' }
8659};
8660
8661static xtensa_arg_internal Iclass_fp_ssxu_stateArgs[] = {
8662 { { STATE_CPENABLE }, 'i' }
8663};
8664
8665static xtensa_arg_internal Iclass_xt_iclass_wb18_0_args[] = {
8666 { { 4 /* ars */ }, 'i' },
8667 { { 60 /* xt_wbr18_label */ }, 'i' }
8668};
8669
8670static xtensa_arg_internal Iclass_xt_iclass_wb18_1_args[] = {
8671 { { 4 /* ars */ }, 'i' },
8672 { { 17 /* b4const */ }, 'i' },
8673 { { 60 /* xt_wbr18_label */ }, 'i' }
8674};
8675
8676static xtensa_arg_internal Iclass_xt_iclass_wb18_2_args[] = {
8677 { { 4 /* ars */ }, 'i' },
8678 { { 18 /* b4constu */ }, 'i' },
8679 { { 60 /* xt_wbr18_label */ }, 'i' }
8680};
8681
8682static xtensa_arg_internal Iclass_xt_iclass_wb18_3_args[] = {
8683 { { 4 /* ars */ }, 'i' },
8684 { { 67 /* bbi */ }, 'i' },
8685 { { 60 /* xt_wbr18_label */ }, 'i' }
8686};
8687
8688static xtensa_arg_internal Iclass_xt_iclass_wb18_4_args[] = {
8689 { { 4 /* ars */ }, 'i' },
8690 { { 6 /* art */ }, 'i' },
8691 { { 60 /* xt_wbr18_label */ }, 'i' }
8692};
8693
8694static xtensa_iclass_internal iclasses[] = {
8695 { 0, 0 /* xt_iclass_excw */,
8696 0, 0, 0, 0 },
8697 { 0, 0 /* xt_iclass_rfe */,
8698 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
43cd72b9 8699 { 0, 0 /* xt_iclass_rfde */,
074f5109 8700 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
43cd72b9
BW		 8701 { 0, 0 /* xt_iclass_syscall */,
8702 0, 0, 0, 0 },
8703 { 0, 0 /* xt_iclass_simcall */,
8704 0, 0, 0, 0 },
8705 { 2, Iclass_xt_iclass_call12_args,
8706 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
8707 { 2, Iclass_xt_iclass_call8_args,
8708 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
8709 { 2, Iclass_xt_iclass_call4_args,
8710 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
8711 { 2, Iclass_xt_iclass_callx12_args,
8712 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
8713 { 2, Iclass_xt_iclass_callx8_args,
8714 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
8715 { 2, Iclass_xt_iclass_callx4_args,
8716 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
8717 { 3, Iclass_xt_iclass_entry_args,
8718 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
8719 { 2, Iclass_xt_iclass_movsp_args,
8720 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
8721 { 1, Iclass_xt_iclass_rotw_args,
074f5109 8722 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
43cd72b9
BW		 8723 { 1, Iclass_xt_iclass_retw_args,
8724 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
8725 { 0, 0 /* xt_iclass_rfwou */,
074f5109 8726 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
43cd72b9 8727 { 3, Iclass_xt_iclass_l32e_args,
074f5109 8728 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
43cd72b9 8729 { 3, Iclass_xt_iclass_s32e_args,
074f5109 8730 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
43cd72b9 8731 { 1, Iclass_xt_iclass_rsr_windowbase_args,
074f5109 8732 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
43cd72b9 8733 { 1, Iclass_xt_iclass_wsr_windowbase_args,
074f5109 8734 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
43cd72b9 8735 { 1, Iclass_xt_iclass_xsr_windowbase_args,
074f5109 8736 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
43cd72b9 8737 { 1, Iclass_xt_iclass_rsr_windowstart_args,
074f5109 8738 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
43cd72b9 8739 { 1, Iclass_xt_iclass_wsr_windowstart_args,
074f5109 8740 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
43cd72b9 8741 { 1, Iclass_xt_iclass_xsr_windowstart_args,
074f5109 8742 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
43cd72b9
BW		 8743 { 3, Iclass_xt_iclass_add_n_args,
8744 0, 0, 0, 0 },
8745 { 3, Iclass_xt_iclass_addi_n_args,
8746 0, 0, 0, 0 },
8747 { 2, Iclass_xt_iclass_bz6_args,
8748 0, 0, 0, 0 },
8749 { 0, 0 /* xt_iclass_ill_n */,
8750 0, 0, 0, 0 },
8751 { 3, Iclass_xt_iclass_loadi4_args,
8752 0, 0, 0, 0 },
8753 { 2, Iclass_xt_iclass_mov_n_args,
8754 0, 0, 0, 0 },
8755 { 2, Iclass_xt_iclass_movi_n_args,
8756 0, 0, 0, 0 },
8757 { 0, 0 /* xt_iclass_nopn */,
8758 0, 0, 0, 0 },
8759 { 1, Iclass_xt_iclass_retn_args,
8760 0, 0, 0, 0 },
8761 { 3, Iclass_xt_iclass_storei4_args,
8762 0, 0, 0, 0 },
33430bd0
BW		 8763 { 1, Iclass_rur_threadptr_args,
8764 1, Iclass_rur_threadptr_stateArgs, 0, 0 },
8765 { 1, Iclass_wur_threadptr_args,
8766 1, Iclass_wur_threadptr_stateArgs, 0, 0 },
43cd72b9
BW		 8767 { 3, Iclass_xt_iclass_addi_args,
8768 0, 0, 0, 0 },
8769 { 3, Iclass_xt_iclass_addmi_args,
8770 0, 0, 0, 0 },
8771 { 3, Iclass_xt_iclass_addsub_args,
8772 0, 0, 0, 0 },
8773 { 3, Iclass_xt_iclass_bit_args,
8774 0, 0, 0, 0 },
8775 { 3, Iclass_xt_iclass_bsi8_args,
8776 0, 0, 0, 0 },
8777 { 3, Iclass_xt_iclass_bsi8b_args,
8778 0, 0, 0, 0 },
8779 { 3, Iclass_xt_iclass_bsi8u_args,
8780 0, 0, 0, 0 },
8781 { 3, Iclass_xt_iclass_bst8_args,
8782 0, 0, 0, 0 },
8783 { 2, Iclass_xt_iclass_bsz12_args,
8784 0, 0, 0, 0 },
8785 { 2, Iclass_xt_iclass_call0_args,
8786 0, 0, 0, 0 },
8787 { 2, Iclass_xt_iclass_callx0_args,
8788 0, 0, 0, 0 },
8789 { 4, Iclass_xt_iclass_exti_args,
8790 0, 0, 0, 0 },
8791 { 0, 0 /* xt_iclass_ill */,
8792 0, 0, 0, 0 },
8793 { 1, Iclass_xt_iclass_jump_args,
8794 0, 0, 0, 0 },
8795 { 1, Iclass_xt_iclass_jumpx_args,
8796 0, 0, 0, 0 },
8797 { 3, Iclass_xt_iclass_l16ui_args,
8798 0, 0, 0, 0 },
8799 { 3, Iclass_xt_iclass_l16si_args,
8800 0, 0, 0, 0 },
8801 { 3, Iclass_xt_iclass_l32i_args,
8802 0, 0, 0, 0 },
8803 { 2, Iclass_xt_iclass_l32r_args,
8804 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
8805 { 3, Iclass_xt_iclass_l8i_args,
8806 0, 0, 0, 0 },
8807 { 2, Iclass_xt_iclass_loop_args,
8808 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
8809 { 2, Iclass_xt_iclass_loopz_args,
8810 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
8811 { 2, Iclass_xt_iclass_movi_args,
8812 0, 0, 0, 0 },
8813 { 3, Iclass_xt_iclass_movz_args,
8814 0, 0, 0, 0 },
8815 { 2, Iclass_xt_iclass_neg_args,
8816 0, 0, 0, 0 },
8817 { 0, 0 /* xt_iclass_nop */,
8818 0, 0, 0, 0 },
8819 { 1, Iclass_xt_iclass_return_args,
8820 0, 0, 0, 0 },
8821 { 3, Iclass_xt_iclass_s16i_args,
8822 0, 0, 0, 0 },
8823 { 3, Iclass_xt_iclass_s32i_args,
8824 0, 0, 0, 0 },
8825 { 3, Iclass_xt_iclass_s8i_args,
8826 0, 0, 0, 0 },
8827 { 1, Iclass_xt_iclass_sar_args,
8828 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
8829 { 1, Iclass_xt_iclass_sari_args,
8830 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
8831 { 2, Iclass_xt_iclass_shifts_args,
8832 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
8833 { 3, Iclass_xt_iclass_shiftst_args,
8834 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
8835 { 2, Iclass_xt_iclass_shiftt_args,
8836 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
8837 { 3, Iclass_xt_iclass_slli_args,
8838 0, 0, 0, 0 },
8839 { 3, Iclass_xt_iclass_srai_args,
8840 0, 0, 0, 0 },
8841 { 3, Iclass_xt_iclass_srli_args,
8842 0, 0, 0, 0 },
8843 { 0, 0 /* xt_iclass_memw */,
8844 0, 0, 0, 0 },
8845 { 0, 0 /* xt_iclass_extw */,
8846 0, 0, 0, 0 },
8847 { 0, 0 /* xt_iclass_isync */,
8848 0, 0, 0, 0 },
8849 { 0, 0 /* xt_iclass_sync */,
8850 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
8851 { 2, Iclass_xt_iclass_rsil_args,
074f5109 8852 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
43cd72b9
BW		 8853 { 1, Iclass_xt_iclass_rsr_lend_args,
8854 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
8855 { 1, Iclass_xt_iclass_wsr_lend_args,
8856 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
8857 { 1, Iclass_xt_iclass_xsr_lend_args,
8858 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
8859 { 1, Iclass_xt_iclass_rsr_lcount_args,
8860 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
8861 { 1, Iclass_xt_iclass_wsr_lcount_args,
8862 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
8863 { 1, Iclass_xt_iclass_xsr_lcount_args,
8864 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
8865 { 1, Iclass_xt_iclass_rsr_lbeg_args,
8866 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
8867 { 1, Iclass_xt_iclass_wsr_lbeg_args,
8868 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
8869 { 1, Iclass_xt_iclass_xsr_lbeg_args,
8870 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
8871 { 1, Iclass_xt_iclass_rsr_sar_args,
8872 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
8873 { 1, Iclass_xt_iclass_wsr_sar_args,
8874 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
8875 { 1, Iclass_xt_iclass_xsr_sar_args,
8876 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
8877 { 1, Iclass_xt_iclass_rsr_litbase_args,
8878 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
8879 { 1, Iclass_xt_iclass_wsr_litbase_args,
8880 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
8881 { 1, Iclass_xt_iclass_xsr_litbase_args,
8882 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
8883 { 1, Iclass_xt_iclass_rsr_176_args,
074f5109 8884 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
43cd72b9 8885 { 1, Iclass_xt_iclass_rsr_208_args,
074f5109 8886 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
43cd72b9 8887 { 1, Iclass_xt_iclass_rsr_ps_args,
074f5109 8888 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
43cd72b9 8889 { 1, Iclass_xt_iclass_wsr_ps_args,
074f5109 8890 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
43cd72b9 8891 { 1, Iclass_xt_iclass_xsr_ps_args,
074f5109 8892 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
43cd72b9 8893 { 1, Iclass_xt_iclass_rsr_epc1_args,
074f5109 8894 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
43cd72b9 8895 { 1, Iclass_xt_iclass_wsr_epc1_args,
074f5109 8896 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
43cd72b9 8897 { 1, Iclass_xt_iclass_xsr_epc1_args,
074f5109 8898 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
43cd72b9 8899 { 1, Iclass_xt_iclass_rsr_excsave1_args,
074f5109 8900 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
43cd72b9 8901 { 1, Iclass_xt_iclass_wsr_excsave1_args,
074f5109 8902 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
43cd72b9 8903 { 1, Iclass_xt_iclass_xsr_excsave1_args,
074f5109 8904 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
43cd72b9 8905 { 1, Iclass_xt_iclass_rsr_epc2_args,
074f5109 8906 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
43cd72b9 8907 { 1, Iclass_xt_iclass_wsr_epc2_args,
074f5109 8908 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
43cd72b9 8909 { 1, Iclass_xt_iclass_xsr_epc2_args,
074f5109 8910 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
43cd72b9 8911 { 1, Iclass_xt_iclass_rsr_excsave2_args,
074f5109 8912 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
43cd72b9 8913 { 1, Iclass_xt_iclass_wsr_excsave2_args,
074f5109 8914 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
43cd72b9 8915 { 1, Iclass_xt_iclass_xsr_excsave2_args,
074f5109 8916 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
43cd72b9 8917 { 1, Iclass_xt_iclass_rsr_epc3_args,
074f5109 8918 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
43cd72b9 8919 { 1, Iclass_xt_iclass_wsr_epc3_args,
074f5109 8920 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
43cd72b9 8921 { 1, Iclass_xt_iclass_xsr_epc3_args,
074f5109 8922 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
43cd72b9 8923 { 1, Iclass_xt_iclass_rsr_excsave3_args,
074f5109 8924 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
43cd72b9 8925 { 1, Iclass_xt_iclass_wsr_excsave3_args,
074f5109 8926 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
43cd72b9 8927 { 1, Iclass_xt_iclass_xsr_excsave3_args,
074f5109 8928 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
43cd72b9 8929 { 1, Iclass_xt_iclass_rsr_epc4_args,
074f5109 8930 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
43cd72b9 8931 { 1, Iclass_xt_iclass_wsr_epc4_args,
074f5109 8932 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
43cd72b9 8933 { 1, Iclass_xt_iclass_xsr_epc4_args,
074f5109 8934 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
43cd72b9 8935 { 1, Iclass_xt_iclass_rsr_excsave4_args,
074f5109 8936 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
43cd72b9 8937 { 1, Iclass_xt_iclass_wsr_excsave4_args,
074f5109 8938 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
43cd72b9 8939 { 1, Iclass_xt_iclass_xsr_excsave4_args,
074f5109 8940 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
33430bd0
BW		 8941 { 1, Iclass_xt_iclass_rsr_epc5_args,
8942 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
8943 { 1, Iclass_xt_iclass_wsr_epc5_args,
8944 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
8945 { 1, Iclass_xt_iclass_xsr_epc5_args,
8946 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
8947 { 1, Iclass_xt_iclass_rsr_excsave5_args,
8948 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
8949 { 1, Iclass_xt_iclass_wsr_excsave5_args,
8950 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
8951 { 1, Iclass_xt_iclass_xsr_excsave5_args,
8952 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
8953 { 1, Iclass_xt_iclass_rsr_epc6_args,
8954 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
8955 { 1, Iclass_xt_iclass_wsr_epc6_args,
8956 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
8957 { 1, Iclass_xt_iclass_xsr_epc6_args,
8958 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
8959 { 1, Iclass_xt_iclass_rsr_excsave6_args,
8960 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
8961 { 1, Iclass_xt_iclass_wsr_excsave6_args,
8962 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
8963 { 1, Iclass_xt_iclass_xsr_excsave6_args,
8964 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
8965 { 1, Iclass_xt_iclass_rsr_epc7_args,
8966 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
8967 { 1, Iclass_xt_iclass_wsr_epc7_args,
8968 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
8969 { 1, Iclass_xt_iclass_xsr_epc7_args,
8970 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
8971 { 1, Iclass_xt_iclass_rsr_excsave7_args,
8972 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
8973 { 1, Iclass_xt_iclass_wsr_excsave7_args,
8974 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
8975 { 1, Iclass_xt_iclass_xsr_excsave7_args,
8976 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
43cd72b9 8977 { 1, Iclass_xt_iclass_rsr_eps2_args,
074f5109 8978 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
43cd72b9 8979 { 1, Iclass_xt_iclass_wsr_eps2_args,
074f5109 8980 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
43cd72b9 8981 { 1, Iclass_xt_iclass_xsr_eps2_args,
074f5109 8982 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
43cd72b9 8983 { 1, Iclass_xt_iclass_rsr_eps3_args,
074f5109 8984 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
43cd72b9 8985 { 1, Iclass_xt_iclass_wsr_eps3_args,
074f5109 8986 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
43cd72b9 8987 { 1, Iclass_xt_iclass_xsr_eps3_args,
074f5109 8988 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
43cd72b9 8989 { 1, Iclass_xt_iclass_rsr_eps4_args,
074f5109 8990 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
43cd72b9 8991 { 1, Iclass_xt_iclass_wsr_eps4_args,
074f5109 8992 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
43cd72b9 8993 { 1, Iclass_xt_iclass_xsr_eps4_args,
074f5109 8994 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
33430bd0
BW		 8995 { 1, Iclass_xt_iclass_rsr_eps5_args,
8996 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
8997 { 1, Iclass_xt_iclass_wsr_eps5_args,
8998 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
8999 { 1, Iclass_xt_iclass_xsr_eps5_args,
9000 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
9001 { 1, Iclass_xt_iclass_rsr_eps6_args,
9002 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
9003 { 1, Iclass_xt_iclass_wsr_eps6_args,
9004 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
9005 { 1, Iclass_xt_iclass_xsr_eps6_args,
9006 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
9007 { 1, Iclass_xt_iclass_rsr_eps7_args,
9008 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
9009 { 1, Iclass_xt_iclass_wsr_eps7_args,
9010 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
9011 { 1, Iclass_xt_iclass_xsr_eps7_args,
9012 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
43cd72b9 9013 { 1, Iclass_xt_iclass_rsr_excvaddr_args,
074f5109 9014 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
43cd72b9 9015 { 1, Iclass_xt_iclass_wsr_excvaddr_args,
074f5109 9016 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
43cd72b9 9017 { 1, Iclass_xt_iclass_xsr_excvaddr_args,
074f5109 9018 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
43cd72b9 9019 { 1, Iclass_xt_iclass_rsr_depc_args,
074f5109 9020 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
43cd72b9 9021 { 1, Iclass_xt_iclass_wsr_depc_args,
074f5109 9022 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
43cd72b9 9023 { 1, Iclass_xt_iclass_xsr_depc_args,
074f5109 9024 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
43cd72b9 9025 { 1, Iclass_xt_iclass_rsr_exccause_args,
074f5109 9026 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
43cd72b9 9027 { 1, Iclass_xt_iclass_wsr_exccause_args,
074f5109 9028 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
43cd72b9 9029 { 1, Iclass_xt_iclass_xsr_exccause_args,
074f5109 9030 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
43cd72b9 9031 { 1, Iclass_xt_iclass_rsr_misc0_args,
074f5109 9032 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
43cd72b9 9033 { 1, Iclass_xt_iclass_wsr_misc0_args,
074f5109 9034 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
43cd72b9 9035 { 1, Iclass_xt_iclass_xsr_misc0_args,
074f5109 9036 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
43cd72b9 9037 { 1, Iclass_xt_iclass_rsr_misc1_args,
074f5109 9038 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
43cd72b9 9039 { 1, Iclass_xt_iclass_wsr_misc1_args,
074f5109 9040 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
43cd72b9 9041 { 1, Iclass_xt_iclass_xsr_misc1_args,
074f5109 9042 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
7aa09196
SA		 9043 { 1, Iclass_xt_iclass_rsr_misc2_args,
9044 3, Iclass_xt_iclass_rsr_misc2_stateArgs, 0, 0 },
9045 { 1, Iclass_xt_iclass_wsr_misc2_args,
9046 3, Iclass_xt_iclass_wsr_misc2_stateArgs, 0, 0 },
9047 { 1, Iclass_xt_iclass_xsr_misc2_args,
9048 3, Iclass_xt_iclass_xsr_misc2_stateArgs, 0, 0 },
9049 { 1, Iclass_xt_iclass_rsr_misc3_args,
9050 3, Iclass_xt_iclass_rsr_misc3_stateArgs, 0, 0 },
9051 { 1, Iclass_xt_iclass_wsr_misc3_args,
9052 3, Iclass_xt_iclass_wsr_misc3_stateArgs, 0, 0 },
9053 { 1, Iclass_xt_iclass_xsr_misc3_args,
9054 3, Iclass_xt_iclass_xsr_misc3_stateArgs, 0, 0 },
43cd72b9 9055 { 1, Iclass_xt_iclass_rsr_prid_args,
074f5109 9056 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
33430bd0
BW		 9057 { 1, Iclass_xt_iclass_rsr_vecbase_args,
9058 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
9059 { 1, Iclass_xt_iclass_wsr_vecbase_args,
9060 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
9061 { 1, Iclass_xt_iclass_xsr_vecbase_args,
9062 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
7aa09196
SA		 9063 { 2, Iclass_xt_iclass_mac16_aa_args,
9064 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
9065 { 2, Iclass_xt_iclass_mac16_ad_args,
9066 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
9067 { 2, Iclass_xt_iclass_mac16_da_args,
9068 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
9069 { 2, Iclass_xt_iclass_mac16_dd_args,
9070 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
9071 { 2, Iclass_xt_iclass_mac16a_aa_args,
9072 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
9073 { 2, Iclass_xt_iclass_mac16a_ad_args,
9074 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
9075 { 2, Iclass_xt_iclass_mac16a_da_args,
9076 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
9077 { 2, Iclass_xt_iclass_mac16a_dd_args,
9078 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
9079 { 4, Iclass_xt_iclass_mac16al_da_args,
9080 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
9081 { 4, Iclass_xt_iclass_mac16al_dd_args,
9082 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
9083 { 2, Iclass_xt_iclass_mac16_l_args,
9084 0, 0, 0, 0 },
33430bd0
BW		 9085 { 3, Iclass_xt_iclass_mul16_args,
9086 0, 0, 0, 0 },
7aa09196
SA		 9087 { 2, Iclass_xt_iclass_rsr_m0_args,
9088 0, 0, 0, 0 },
9089 { 2, Iclass_xt_iclass_wsr_m0_args,
9090 0, 0, 0, 0 },
9091 { 2, Iclass_xt_iclass_xsr_m0_args,
9092 0, 0, 0, 0 },
9093 { 2, Iclass_xt_iclass_rsr_m1_args,
9094 0, 0, 0, 0 },
9095 { 2, Iclass_xt_iclass_wsr_m1_args,
9096 0, 0, 0, 0 },
9097 { 2, Iclass_xt_iclass_xsr_m1_args,
9098 0, 0, 0, 0 },
9099 { 2, Iclass_xt_iclass_rsr_m2_args,
9100 0, 0, 0, 0 },
9101 { 2, Iclass_xt_iclass_wsr_m2_args,
9102 0, 0, 0, 0 },
9103 { 2, Iclass_xt_iclass_xsr_m2_args,
9104 0, 0, 0, 0 },
9105 { 2, Iclass_xt_iclass_rsr_m3_args,
9106 0, 0, 0, 0 },
9107 { 2, Iclass_xt_iclass_wsr_m3_args,
9108 0, 0, 0, 0 },
9109 { 2, Iclass_xt_iclass_xsr_m3_args,
9110 0, 0, 0, 0 },
9111 { 1, Iclass_xt_iclass_rsr_acclo_args,
9112 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
9113 { 1, Iclass_xt_iclass_wsr_acclo_args,
9114 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
9115 { 1, Iclass_xt_iclass_xsr_acclo_args,
9116 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
9117 { 1, Iclass_xt_iclass_rsr_acchi_args,
9118 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
9119 { 1, Iclass_xt_iclass_wsr_acchi_args,
9120 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
9121 { 1, Iclass_xt_iclass_xsr_acchi_args,
9122 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
43cd72b9 9123 { 1, Iclass_xt_iclass_rfi_args,
33430bd0 9124 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
43cd72b9 9125 { 1, Iclass_xt_iclass_wait_args,
074f5109 9126 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
43cd72b9 9127 { 1, Iclass_xt_iclass_rsr_interrupt_args,
074f5109 9128 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
43cd72b9 9129 { 1, Iclass_xt_iclass_wsr_intset_args,
074f5109 9130 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
43cd72b9 9131 { 1, Iclass_xt_iclass_wsr_intclear_args,
074f5109 9132 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
43cd72b9 9133 { 1, Iclass_xt_iclass_rsr_intenable_args,
074f5109 9134 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
43cd72b9 9135 { 1, Iclass_xt_iclass_wsr_intenable_args,
074f5109 9136 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
43cd72b9 9137 { 1, Iclass_xt_iclass_xsr_intenable_args,
074f5109 9138 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
43cd72b9
BW		 9139 { 2, Iclass_xt_iclass_break_args,
9140 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
9141 { 1, Iclass_xt_iclass_break_n_args,
9142 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
9143 { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
074f5109 9144 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
43cd72b9 9145 { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
074f5109 9146 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
43cd72b9 9147 { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
074f5109 9148 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
43cd72b9 9149 { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
074f5109 9150 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
43cd72b9 9151 { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
074f5109 9152 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
43cd72b9 9153 { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
074f5109 9154 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
43cd72b9 9155 { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
074f5109 9156 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
43cd72b9 9157 { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
074f5109 9158 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
43cd72b9 9159 { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
074f5109 9160 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
43cd72b9 9161 { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
074f5109 9162 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
43cd72b9 9163 { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
074f5109 9164 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
43cd72b9 9165 { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
074f5109 9166 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
43cd72b9 9167 { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
074f5109 9168 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
43cd72b9 9169 { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
074f5109 9170 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
43cd72b9 9171 { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
074f5109 9172 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
43cd72b9 9173 { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
074f5109 9174 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
43cd72b9 9175 { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
074f5109 9176 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
43cd72b9 9177 { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
074f5109 9178 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
43cd72b9 9179 { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
074f5109 9180 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
43cd72b9 9181 { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
074f5109 9182 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
43cd72b9 9183 { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
074f5109 9184 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
43cd72b9 9185 { 1, Iclass_xt_iclass_rsr_debugcause_args,
074f5109 9186 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
43cd72b9 9187 { 1, Iclass_xt_iclass_wsr_debugcause_args,
074f5109 9188 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
43cd72b9 9189 { 1, Iclass_xt_iclass_xsr_debugcause_args,
074f5109 9190 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
43cd72b9 9191 { 1, Iclass_xt_iclass_rsr_icount_args,
074f5109 9192 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
43cd72b9 9193 { 1, Iclass_xt_iclass_wsr_icount_args,
074f5109 9194 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
43cd72b9 9195 { 1, Iclass_xt_iclass_xsr_icount_args,
074f5109 9196 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
43cd72b9 9197 { 1, Iclass_xt_iclass_rsr_icountlevel_args,
074f5109 9198 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
43cd72b9 9199 { 1, Iclass_xt_iclass_wsr_icountlevel_args,
074f5109 9200 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
43cd72b9 9201 { 1, Iclass_xt_iclass_xsr_icountlevel_args,
074f5109 9202 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
43cd72b9 9203 { 1, Iclass_xt_iclass_rsr_ddr_args,
074f5109 9204 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
43cd72b9 9205 { 1, Iclass_xt_iclass_wsr_ddr_args,
074f5109 9206 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
43cd72b9 9207 { 1, Iclass_xt_iclass_xsr_ddr_args,
074f5109 9208 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
33430bd0 9209 { 1, Iclass_xt_iclass_rfdo_args,
074f5109 9210 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
43cd72b9
BW		 9211 { 0, 0 /* xt_iclass_rfdd */,
9212 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
33430bd0
BW		 9213 { 1, Iclass_xt_iclass_wsr_mmid_args,
9214 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
7aa09196
SA		 9215 { 3, Iclass_xt_iclass_bbool1_args,
9216 0, 0, 0, 0 },
9217 { 2, Iclass_xt_iclass_bbool4_args,
9218 0, 0, 0, 0 },
9219 { 2, Iclass_xt_iclass_bbool8_args,
9220 0, 0, 0, 0 },
9221 { 2, Iclass_xt_iclass_bbranch_args,
9222 0, 0, 0, 0 },
9223 { 3, Iclass_xt_iclass_bmove_args,
9224 0, 0, 0, 0 },
9225 { 2, Iclass_xt_iclass_RSR_BR_args,
9226 0, 0, 0, 0 },
9227 { 2, Iclass_xt_iclass_WSR_BR_args,
9228 0, 0, 0, 0 },
9229 { 2, Iclass_xt_iclass_XSR_BR_args,
9230 0, 0, 0, 0 },
43cd72b9 9231 { 1, Iclass_xt_iclass_rsr_ccount_args,
074f5109 9232 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
43cd72b9 9233 { 1, Iclass_xt_iclass_wsr_ccount_args,
074f5109 9234 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
43cd72b9 9235 { 1, Iclass_xt_iclass_xsr_ccount_args,
074f5109 9236 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
43cd72b9 9237 { 1, Iclass_xt_iclass_rsr_ccompare0_args,
074f5109 9238 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
43cd72b9 9239 { 1, Iclass_xt_iclass_wsr_ccompare0_args,
074f5109 9240 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
43cd72b9 9241 { 1, Iclass_xt_iclass_xsr_ccompare0_args,
074f5109 9242 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
43cd72b9 9243 { 1, Iclass_xt_iclass_rsr_ccompare1_args,
074f5109 9244 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
43cd72b9 9245 { 1, Iclass_xt_iclass_wsr_ccompare1_args,
074f5109 9246 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
43cd72b9 9247 { 1, Iclass_xt_iclass_xsr_ccompare1_args,
074f5109 9248 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
43cd72b9 9249 { 1, Iclass_xt_iclass_rsr_ccompare2_args,
074f5109 9250 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
43cd72b9 9251 { 1, Iclass_xt_iclass_wsr_ccompare2_args,
074f5109 9252 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
43cd72b9 9253 { 1, Iclass_xt_iclass_xsr_ccompare2_args,
074f5109 9254 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
43cd72b9
BW		 9255 { 2, Iclass_xt_iclass_icache_args,
9256 0, 0, 0, 0 },
33430bd0
BW		 9257 { 2, Iclass_xt_iclass_icache_lock_args,
9258 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 },
43cd72b9 9259 { 2, Iclass_xt_iclass_icache_inv_args,
074f5109 9260 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
43cd72b9 9261 { 2, Iclass_xt_iclass_licx_args,
074f5109 9262 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
43cd72b9 9263 { 2, Iclass_xt_iclass_sicx_args,
074f5109 9264 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
43cd72b9
BW		 9265 { 2, Iclass_xt_iclass_dcache_args,
9266 0, 0, 0, 0 },
9267 { 2, Iclass_xt_iclass_dcache_ind_args,
074f5109 9268 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
43cd72b9 9269 { 2, Iclass_xt_iclass_dcache_inv_args,
074f5109 9270 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
43cd72b9
BW		 9271 { 2, Iclass_xt_iclass_dpf_args,
9272 0, 0, 0, 0 },
33430bd0
BW		 9273 { 2, Iclass_xt_iclass_dcache_lock_args,
9274 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 },
43cd72b9 9275 { 2, Iclass_xt_iclass_sdct_args,
074f5109 9276 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
43cd72b9 9277 { 2, Iclass_xt_iclass_ldct_args,
074f5109
BW		 9278 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
9279 { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
9280 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
9281 { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
9282 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
9283 { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
9284 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
9285 { 1, Iclass_xt_iclass_rsr_rasid_args,
9286 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
9287 { 1, Iclass_xt_iclass_wsr_rasid_args,
9288 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
9289 { 1, Iclass_xt_iclass_xsr_rasid_args,
9290 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
9291 { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
9292 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
9293 { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
9294 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
9295 { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
9296 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
9297 { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
9298 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
9299 { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
9300 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
9301 { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
9302 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
43cd72b9 9303 { 1, Iclass_xt_iclass_idtlb_args,
074f5109 9304 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
43cd72b9 9305 { 2, Iclass_xt_iclass_rdtlb_args,
074f5109 9306 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
43cd72b9 9307 { 2, Iclass_xt_iclass_wdtlb_args,
074f5109 9308 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
43cd72b9 9309 { 1, Iclass_xt_iclass_iitlb_args,
074f5109 9310 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
43cd72b9 9311 { 2, Iclass_xt_iclass_ritlb_args,
074f5109 9312 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
43cd72b9 9313 { 2, Iclass_xt_iclass_witlb_args,
074f5109
BW		 9314 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
9315 { 0, 0 /* xt_iclass_ldpte */,
9316 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
9317 { 0, 0 /* xt_iclass_hwwitlba */,
9318 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
9319 { 0, 0 /* xt_iclass_hwwdtlba */,
9320 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
33430bd0
BW		 9321 { 1, Iclass_xt_iclass_rsr_cpenable_args,
9322 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
9323 { 1, Iclass_xt_iclass_wsr_cpenable_args,
9324 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
9325 { 1, Iclass_xt_iclass_xsr_cpenable_args,
9326 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
9327 { 3, Iclass_xt_iclass_clamp_args,
9328 0, 0, 0, 0 },
9329 { 3, Iclass_xt_iclass_minmax_args,
9330 0, 0, 0, 0 },
43cd72b9 9331 { 2, Iclass_xt_iclass_nsa_args,
33430bd0
BW		 9332 0, 0, 0, 0 },
9333 { 3, Iclass_xt_iclass_sx_args,
9334 0, 0, 0, 0 },
9335 { 3, Iclass_xt_iclass_l32ai_args,
9336 0, 0, 0, 0 },
9337 { 3, Iclass_xt_iclass_s32ri_args,
9338 0, 0, 0, 0 },
9339 { 3, Iclass_xt_iclass_s32c1i_args,
9340 2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
9341 { 1, Iclass_xt_iclass_rsr_scompare1_args,
9342 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
9343 { 1, Iclass_xt_iclass_wsr_scompare1_args,
9344 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
9345 { 1, Iclass_xt_iclass_xsr_scompare1_args,
9346 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
9347 { 3, Iclass_xt_iclass_div_args,
9348 0, 0, 0, 0 },
9349 { 3, Iclass_xt_mul32_args,
7aa09196
SA		 9350 0, 0, 0, 0 },
9351 { 1, Iclass_rur_fcr_args,
9352 9, Iclass_rur_fcr_stateArgs, 0, 0 },
9353 { 1, Iclass_wur_fcr_args,
9354 9, Iclass_wur_fcr_stateArgs, 0, 0 },
9355 { 1, Iclass_rur_fsr_args,
9356 8, Iclass_rur_fsr_stateArgs, 0, 0 },
9357 { 1, Iclass_wur_fsr_args,
9358 8, Iclass_wur_fsr_stateArgs, 0, 0 },
9359 { 3, Iclass_fp_args,
9360 2, Iclass_fp_stateArgs, 0, 0 },
9361 { 3, Iclass_fp_mac_args,
9362 2, Iclass_fp_mac_stateArgs, 0, 0 },
9363 { 3, Iclass_fp_cmov_args,
9364 1, Iclass_fp_cmov_stateArgs, 0, 0 },
9365 { 3, Iclass_fp_mov_args,
9366 1, Iclass_fp_mov_stateArgs, 0, 0 },
9367 { 2, Iclass_fp_mov2_args,
9368 1, Iclass_fp_mov2_stateArgs, 0, 0 },
9369 { 3, Iclass_fp_cmp_args,
9370 1, Iclass_fp_cmp_stateArgs, 0, 0 },
9371 { 3, Iclass_fp_float_args,
9372 2, Iclass_fp_float_stateArgs, 0, 0 },
9373 { 3, Iclass_fp_int_args,
9374 1, Iclass_fp_int_stateArgs, 0, 0 },
9375 { 2, Iclass_fp_rfr_args,
9376 1, Iclass_fp_rfr_stateArgs, 0, 0 },
9377 { 2, Iclass_fp_wfr_args,
9378 1, Iclass_fp_wfr_stateArgs, 0, 0 },
9379 { 3, Iclass_fp_lsi_args,
9380 1, Iclass_fp_lsi_stateArgs, 0, 0 },
9381 { 3, Iclass_fp_lsiu_args,
9382 1, Iclass_fp_lsiu_stateArgs, 0, 0 },
9383 { 3, Iclass_fp_lsx_args,
9384 1, Iclass_fp_lsx_stateArgs, 0, 0 },
9385 { 3, Iclass_fp_lsxu_args,
9386 1, Iclass_fp_lsxu_stateArgs, 0, 0 },
9387 { 3, Iclass_fp_ssi_args,
9388 1, Iclass_fp_ssi_stateArgs, 0, 0 },
9389 { 3, Iclass_fp_ssiu_args,
9390 1, Iclass_fp_ssiu_stateArgs, 0, 0 },
9391 { 3, Iclass_fp_ssx_args,
9392 1, Iclass_fp_ssx_stateArgs, 0, 0 },
9393 { 3, Iclass_fp_ssxu_args,
9394 1, Iclass_fp_ssxu_stateArgs, 0, 0 },
9395 { 2, Iclass_xt_iclass_wb18_0_args,
9396 0, 0, 0, 0 },
9397 { 3, Iclass_xt_iclass_wb18_1_args,
9398 0, 0, 0, 0 },
9399 { 3, Iclass_xt_iclass_wb18_2_args,
9400 0, 0, 0, 0 },
9401 { 3, Iclass_xt_iclass_wb18_3_args,
9402 0, 0, 0, 0 },
9403 { 3, Iclass_xt_iclass_wb18_4_args,
43cd72b9
BW		 9404 0, 0, 0, 0 }
9405};
9406
7aa09196
SA		 9407\f
9408/* Opcode encodings. */
9409
9410static void
9411Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
9412{
9413 slotbuf[0] = 0x2080;
9414}
9415
9416static void
9417Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
9418{
9419 slotbuf[0] = 0x3000;
9420}
9421
9422static void
9423Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
9424{
9425 slotbuf[0] = 0x3200;
9426}
9427
9428static void
9429Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
9430{
9431 slotbuf[0] = 0x5000;
9432}
9433
9434static void
9435Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
9436{
9437 slotbuf[0] = 0x5100;
9438}
9439
9440static void
9441Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
9442{
9443 slotbuf[0] = 0x35;
9444}
9445
9446static void
9447Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
9448{
9449 slotbuf[0] = 0x25;
9450}
9451
9452static void
9453Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
9454{
9455 slotbuf[0] = 0x15;
9456}
9457
9458static void
9459Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
9460{
9461 slotbuf[0] = 0xf0;
9462}
9463
9464static void
9465Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
9466{
9467 slotbuf[0] = 0xe0;
9468}
9469
9470static void
9471Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
9472{
9473 slotbuf[0] = 0xd0;
9474}
9475
9476static void
9477Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
9478{
9479 slotbuf[0] = 0x36;
9480}
9481
9482static void
9483Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
9484{
9485 slotbuf[0] = 0x1000;
9486}
9487
9488static void
9489Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
9490{
9491 slotbuf[0] = 0x408000;
9492}
9493
9494static void
9495Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
9496{
9497 slotbuf[0] = 0x90;
9498}
9499
9500static void
9501Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9502{
9503 slotbuf[0] = 0xf01d;
9504}
9505
9506static void
9507Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
9508{
9509 slotbuf[0] = 0x3400;
9510}
9511
9512static void
9513Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
9514{
9515 slotbuf[0] = 0x3500;
9516}
9517
9518static void
9519Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
9520{
9521 slotbuf[0] = 0x90000;
9522}
9523
9524static void
9525Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
9526{
9527 slotbuf[0] = 0x490000;
9528}
9529
9530static void
9531Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
9532{
9533 slotbuf[0] = 0x34800;
9534}
9535
9536static void
9537Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
9538{
9539 slotbuf[0] = 0x134800;
9540}
9541
9542static void
9543Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
9544{
9545 slotbuf[0] = 0x614800;
9546}
9547
9548static void
9549Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
9550{
9551 slotbuf[0] = 0x34900;
9552}
9553
9554static void
9555Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
9556{
9557 slotbuf[0] = 0x134900;
9558}
9559
9560static void
9561Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
9562{
9563 slotbuf[0] = 0x614900;
9564}
9565
9566static void
9567Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
9568{
9569 slotbuf[0] = 0xa;
9570}
9571
9572static void
9573Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
9574{
9575 slotbuf[0] = 0xb;
9576}
9577
9578static void
9579Opcode_addi_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9580{
9581 slotbuf[0] = 0x3000;
9582}
9583
9584static void
9585Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9586{
9587 slotbuf[0] = 0x8c;
9588}
9589
9590static void
9591Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9592{
9593 slotbuf[0] = 0xcc;
9594}
9595
9596static void
9597Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9598{
9599 slotbuf[0] = 0xf06d;
9600}
9601
9602static void
9603Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
9604{
9605 slotbuf[0] = 0x8;
9606}
9607
9608static void
9609Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9610{
9611 slotbuf[0] = 0xd;
9612}
9613
9614static void
9615Opcode_mov_n_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9616{
9617 slotbuf[0] = 0x6000;
9618}
9619
9620static void
9621Opcode_mov_n_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9622{
9623 slotbuf[0] = 0xa3000;
9624}
9625
9626static void
9627Opcode_mov_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9628{
9629 slotbuf[0] = 0xc080;
9630}
9631
9632static void
9633Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9634{
9635 slotbuf[0] = 0xc;
9636}
9637
9638static void
9639Opcode_movi_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9640{
9641 slotbuf[0] = 0xc000;
9642}
9643
9644static void
9645Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9646{
9647 slotbuf[0] = 0xf03d;
9648}
9649
9650static void
9651Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
9652{
9653 slotbuf[0] = 0xf00d;
9654}
9655
9656static void
9657Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
9658{
9659 slotbuf[0] = 0x9;
9660}
9661
9662static void
9663Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
9664{
9665 slotbuf[0] = 0xe30e70;
9666}
9667
9668static void
9669Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
9670{
9671 slotbuf[0] = 0xf3e700;
9672}
9673
9674static void
9675Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
9676{
9677 slotbuf[0] = 0xc002;
9678}
9679
9680static void
9681Opcode_addi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9682{
9683 slotbuf[0] = 0x60000;
9684}
9685
9686static void
9687Opcode_addi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9688{
9689 slotbuf[0] = 0x200c00;
9690}
9691
9692static void
9693Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
9694{
9695 slotbuf[0] = 0xd002;
9696}
9697
9698static void
9699Opcode_addmi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9700{
9701 slotbuf[0] = 0x70000;
9702}
9703
9704static void
9705Opcode_addmi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9706{
9707 slotbuf[0] = 0x200d00;
9708}
9709
9710static void
9711Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
9712{
9713 slotbuf[0] = 0x800000;
9714}
9715
9716static void
9717Opcode_add_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9718{
9719 slotbuf[0] = 0x92000;
9720}
9721
9722static void
9723Opcode_add_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9724{
9725 slotbuf[0] = 0x2000;
9726}
9727
9728static void
9729Opcode_add_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9730{
9731 slotbuf[0] = 0x80000;
9732}
9733
9734static void
9735Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
9736{
9737 slotbuf[0] = 0xc00000;
9738}
9739
9740static void
9741Opcode_sub_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9742{
9743 slotbuf[0] = 0xa8000;
9744}
9745
9746static void
9747Opcode_sub_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9748{
9749 slotbuf[0] = 0xa000;
9750}
9751
9752static void
9753Opcode_sub_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9754{
9755 slotbuf[0] = 0xc0000;
9756}
9757
9758static void
9759Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
9760{
9761 slotbuf[0] = 0x900000;
9762}
9763
9764static void
9765Opcode_addx2_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9766{
9767 slotbuf[0] = 0x94000;
9768}
9769
9770static void
9771Opcode_addx2_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9772{
9773 slotbuf[0] = 0x4000;
9774}
9775
9776static void
9777Opcode_addx2_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9778{
9779 slotbuf[0] = 0x90000;
9780}
9781
9782static void
9783Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
9784{
9785 slotbuf[0] = 0xa00000;
9786}
9787
9788static void
9789Opcode_addx4_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9790{
9791 slotbuf[0] = 0x98000;
9792}
9793
9794static void
9795Opcode_addx4_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9796{
9797 slotbuf[0] = 0x5000;
9798}
9799
9800static void
9801Opcode_addx4_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9802{
9803 slotbuf[0] = 0xa0000;
9804}
9805
9806static void
9807Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
9808{
9809 slotbuf[0] = 0xb00000;
9810}
9811
9812static void
9813Opcode_addx8_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9814{
9815 slotbuf[0] = 0x93000;
9816}
9817
9818static void
9819Opcode_addx8_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9820{
9821 slotbuf[0] = 0xb0000;
9822}
9823
9824static void
9825Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
9826{
9827 slotbuf[0] = 0xd00000;
9828}
9829
9830static void
9831Opcode_subx2_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9832{
9833 slotbuf[0] = 0xd0000;
9834}
9835
9836static void
9837Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
9838{
9839 slotbuf[0] = 0xe00000;
9840}
9841
9842static void
9843Opcode_subx4_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9844{
9845 slotbuf[0] = 0xe0000;
9846}
9847
9848static void
9849Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
9850{
9851 slotbuf[0] = 0xf00000;
9852}
9853
9854static void
9855Opcode_subx8_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9856{
9857 slotbuf[0] = 0xf0000;
9858}
9859
9860static void
9861Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
9862{
9863 slotbuf[0] = 0x100000;
9864}
9865
9866static void
9867Opcode_and_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9868{
9869 slotbuf[0] = 0x95000;
9870}
9871
9872static void
9873Opcode_and_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9874{
9875 slotbuf[0] = 0x6000;
9876}
9877
9878static void
9879Opcode_and_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9880{
9881 slotbuf[0] = 0x10000;
9882}
9883
9884static void
9885Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
9886{
9887 slotbuf[0] = 0x200000;
9888}
9889
9890static void
9891Opcode_or_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9892{
9893 slotbuf[0] = 0x9e000;
9894}
9895
9896static void
9897Opcode_or_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9898{
9899 slotbuf[0] = 0x7000;
9900}
9901
9902static void
9903Opcode_or_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9904{
9905 slotbuf[0] = 0x20000;
9906}
9907
9908static void
9909Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
9910{
9911 slotbuf[0] = 0x300000;
9912}
9913
9914static void
9915Opcode_xor_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
9916{
9917 slotbuf[0] = 0xb0000;
9918}
9919
9920static void
9921Opcode_xor_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
9922{
9923 slotbuf[0] = 0xb000;
9924}
9925
9926static void
9927Opcode_xor_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
9928{
9929 slotbuf[0] = 0x30000;
9930}
9931
9932static void
9933Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
9934{
9935 slotbuf[0] = 0x26;
9936}
9937
9938static void
9939Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
9940{
9941 slotbuf[0] = 0x66;
9942}
9943
9944static void
9945Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
9946{
9947 slotbuf[0] = 0xe6;
9948}
9949
9950static void
9951Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
9952{
9953 slotbuf[0] = 0xa6;
9954}
9955
9956static void
9957Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
9958{
9959 slotbuf[0] = 0x6007;
9960}
9961
9962static void
9963Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
9964{
9965 slotbuf[0] = 0xe007;
9966}
9967
9968static void
9969Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
9970{
9971 slotbuf[0] = 0xf6;
9972}
9973
9974static void
9975Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
9976{
9977 slotbuf[0] = 0xb6;
9978}
9979
9980static void
9981Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
9982{
9983 slotbuf[0] = 0x1007;
9984}
9985
9986static void
9987Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
9988{
9989 slotbuf[0] = 0x9007;
9990}
9991
9992static void
9993Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
9994{
9995 slotbuf[0] = 0xa007;
9996}
9997
9998static void
9999Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
10000{
10001 slotbuf[0] = 0x2007;
10002}
10003
10004static void
10005Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
10006{
10007 slotbuf[0] = 0xb007;
10008}
10009
10010static void
10011Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
10012{
10013 slotbuf[0] = 0x3007;
10014}
10015
10016static void
10017Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
10018{
10019 slotbuf[0] = 0x8007;
10020}
10021
10022static void
10023Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
10024{
10025 slotbuf[0] = 0x7;
10026}
10027
10028static void
10029Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
10030{
10031 slotbuf[0] = 0x4007;
10032}
10033
10034static void
10035Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
10036{
10037 slotbuf[0] = 0xc007;
10038}
10039
10040static void
10041Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
10042{
10043 slotbuf[0] = 0x5007;
10044}
10045
10046static void
10047Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
10048{
10049 slotbuf[0] = 0xd007;
10050}
10051
10052static void
10053Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
10054{
10055 slotbuf[0] = 0x16;
10056}
10057
10058static void
10059Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
10060{
10061 slotbuf[0] = 0x56;
10062}
10063
10064static void
10065Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
10066{
10067 slotbuf[0] = 0xd6;
10068}
10069
10070static void
10071Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
10072{
10073 slotbuf[0] = 0x96;
10074}
10075
10076static void
10077Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
10078{
10079 slotbuf[0] = 0x5;
10080}
10081
10082static void
10083Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
10084{
10085 slotbuf[0] = 0xc0;
10086}
10087
10088static void
10089Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
10090{
10091 slotbuf[0] = 0x40000;
10092}
10093
10094static void
10095Opcode_extui_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10096{
10097 slotbuf[0] = 0x40000;
10098}
10099
10100static void
10101Opcode_extui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10102{
10103 slotbuf[0] = 0x4000;
10104}
10105
10106static void
10107Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
10108{
10109 slotbuf[0] = 0;
10110}
10111
10112static void
10113Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
10114{
10115 slotbuf[0] = 0x6;
10116}
10117
10118static void
10119Opcode_j_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10120{
10121 slotbuf[0] = 0xc0000;
10122}
10123
10124static void
10125Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
10126{
10127 slotbuf[0] = 0xa0;
10128}
10129
10130static void
10131Opcode_jx_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10132{
10133 slotbuf[0] = 0xa3010;
10134}
10135
10136static void
10137Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
10138{
10139 slotbuf[0] = 0x1002;
10140}
10141
10142static void
10143Opcode_l16ui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10144{
10145 slotbuf[0] = 0x200100;
10146}
10147
10148static void
10149Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
10150{
10151 slotbuf[0] = 0x9002;
10152}
10153
10154static void
10155Opcode_l16si_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10156{
10157 slotbuf[0] = 0x200900;
10158}
10159
10160static void
10161Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
10162{
10163 slotbuf[0] = 0x2002;
10164}
10165
10166static void
10167Opcode_l32i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10168{
10169 slotbuf[0] = 0x200200;
10170}
10171
10172static void
10173Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
10174{
10175 slotbuf[0] = 0x1;
10176}
10177
10178static void
10179Opcode_l32r_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10180{
10181 slotbuf[0] = 0x100000;
10182}
10183
10184static void
10185Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
10186{
10187 slotbuf[0] = 0x2;
10188}
10189
10190static void
10191Opcode_l8ui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10192{
10193 slotbuf[0] = 0x200000;
10194}
10195
10196static void
10197Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
10198{
10199 slotbuf[0] = 0x8076;
10200}
10201
10202static void
10203Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
10204{
10205 slotbuf[0] = 0x9076;
10206}
10207
10208static void
10209Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
10210{
10211 slotbuf[0] = 0xa076;
10212}
10213
10214static void
10215Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
10216{
10217 slotbuf[0] = 0xa002;
10218}
10219
10220static void
10221Opcode_movi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10222{
10223 slotbuf[0] = 0x80000;
10224}
10225
10226static void
10227Opcode_movi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10228{
10229 slotbuf[0] = 0x200a00;
10230}
10231
10232static void
10233Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
10234{
10235 slotbuf[0] = 0x830000;
10236}
10237
10238static void
10239Opcode_moveqz_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10240{
10241 slotbuf[0] = 0x96000;
10242}
10243
10244static void
10245Opcode_moveqz_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10246{
10247 slotbuf[0] = 0x83000;
10248}
10249
10250static void
10251Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
10252{
10253 slotbuf[0] = 0x930000;
10254}
10255
10256static void
10257Opcode_movnez_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10258{
10259 slotbuf[0] = 0x9a000;
10260}
10261
10262static void
10263Opcode_movnez_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10264{
10265 slotbuf[0] = 0x93000;
10266}
10267
10268static void
10269Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
10270{
10271 slotbuf[0] = 0xa30000;
10272}
10273
10274static void
10275Opcode_movltz_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10276{
10277 slotbuf[0] = 0x99000;
10278}
10279
10280static void
10281Opcode_movltz_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10282{
10283 slotbuf[0] = 0xa3000;
10284}
10285
10286static void
10287Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
10288{
10289 slotbuf[0] = 0xb30000;
10290}
10291
10292static void
10293Opcode_movgez_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10294{
10295 slotbuf[0] = 0x97000;
10296}
10297
10298static void
10299Opcode_movgez_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10300{
10301 slotbuf[0] = 0xb3000;
10302}
10303
10304static void
10305Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
10306{
10307 slotbuf[0] = 0x600000;
10308}
10309
10310static void
10311Opcode_neg_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10312{
10313 slotbuf[0] = 0xa5000;
10314}
10315
10316static void
10317Opcode_neg_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
10318{
10319 slotbuf[0] = 0xd100;
10320}
10321
10322static void
10323Opcode_neg_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10324{
10325 slotbuf[0] = 0x60000;
10326}
10327
10328static void
10329Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
10330{
10331 slotbuf[0] = 0x600100;
10332}
10333
10334static void
10335Opcode_abs_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
10336{
10337 slotbuf[0] = 0xd000;
10338}
10339
10340static void
10341Opcode_abs_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10342{
10343 slotbuf[0] = 0x60010;
10344}
10345
10346static void
10347Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
10348{
10349 slotbuf[0] = 0x20f0;
10350}
10351
10352static void
10353Opcode_nop_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10354{
10355 slotbuf[0] = 0xa3040;
10356}
10357
10358static void
10359Opcode_nop_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
10360{
10361 slotbuf[0] = 0xc090;
10362}
10363
10364static void
10365Opcode_nop_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
10366{
10367 slotbuf[0] = 0xc8000000;
10368 slotbuf[1] = 0;
10369}
10370
10371static void
10372Opcode_nop_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10373{
10374 slotbuf[0] = 0x20f;
10375}
10376
10377static void
10378Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
10379{
10380 slotbuf[0] = 0x80;
10381}
10382
10383static void
10384Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
10385{
10386 slotbuf[0] = 0x5002;
10387}
10388
10389static void
10390Opcode_s16i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10391{
10392 slotbuf[0] = 0x200500;
10393}
10394
10395static void
10396Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
10397{
10398 slotbuf[0] = 0x6002;
10399}
10400
10401static void
10402Opcode_s32i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10403{
10404 slotbuf[0] = 0x200600;
10405}
10406
10407static void
10408Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
10409{
10410 slotbuf[0] = 0x4002;
10411}
10412
10413static void
10414Opcode_s8i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10415{
10416 slotbuf[0] = 0x200400;
10417}
10418
10419static void
10420Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
10421{
10422 slotbuf[0] = 0x400000;
10423}
10424
10425static void
10426Opcode_ssr_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10427{
10428 slotbuf[0] = 0x40000;
10429}
10430
10431static void
10432Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
10433{
10434 slotbuf[0] = 0x401000;
10435}
10436
10437static void
10438Opcode_ssl_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10439{
10440 slotbuf[0] = 0xa3020;
10441}
10442
10443static void
10444Opcode_ssl_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10445{
10446 slotbuf[0] = 0x40100;
10447}
10448
10449static void
10450Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
10451{
10452 slotbuf[0] = 0x402000;
10453}
10454
10455static void
10456Opcode_ssa8l_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10457{
10458 slotbuf[0] = 0x40200;
10459}
10460
10461static void
10462Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
10463{
10464 slotbuf[0] = 0x403000;
10465}
10466
10467static void
10468Opcode_ssa8b_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10469{
10470 slotbuf[0] = 0x40300;
10471}
10472
10473static void
10474Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
10475{
10476 slotbuf[0] = 0x404000;
10477}
10478
10479static void
10480Opcode_ssai_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10481{
10482 slotbuf[0] = 0x40400;
10483}
10484
10485static void
10486Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
10487{
10488 slotbuf[0] = 0xa10000;
10489}
10490
10491static void
10492Opcode_sll_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10493{
10494 slotbuf[0] = 0xa6000;
10495}
10496
10497static void
10498Opcode_sll_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10499{
10500 slotbuf[0] = 0xa1000;
10501}
10502
10503static void
10504Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
10505{
10506 slotbuf[0] = 0x810000;
10507}
10508
10509static void
10510Opcode_src_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10511{
10512 slotbuf[0] = 0xa2000;
10513}
10514
10515static void
10516Opcode_src_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10517{
10518 slotbuf[0] = 0x81000;
10519}
10520
10521static void
10522Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
10523{
10524 slotbuf[0] = 0x910000;
10525}
10526
10527static void
10528Opcode_srl_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10529{
10530 slotbuf[0] = 0xa5200;
10531}
10532
10533static void
10534Opcode_srl_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
10535{
10536 slotbuf[0] = 0xd400;
10537}
10538
10539static void
10540Opcode_srl_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10541{
10542 slotbuf[0] = 0x91000;
10543}
10544
10545static void
10546Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
10547{
10548 slotbuf[0] = 0xb10000;
10549}
10550
10551static void
10552Opcode_sra_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10553{
10554 slotbuf[0] = 0xa5100;
10555}
10556
10557static void
10558Opcode_sra_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
10559{
10560 slotbuf[0] = 0xd200;
10561}
10562
10563static void
10564Opcode_sra_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10565{
10566 slotbuf[0] = 0xb1000;
10567}
10568
10569static void
10570Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
10571{
10572 slotbuf[0] = 0x10000;
10573}
10574
10575static void
10576Opcode_slli_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10577{
10578 slotbuf[0] = 0x90000;
10579}
10580
10581static void
10582Opcode_slli_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10583{
10584 slotbuf[0] = 0x1000;
10585}
10586
10587static void
10588Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
10589{
10590 slotbuf[0] = 0x210000;
10591}
10592
10593static void
10594Opcode_srai_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10595{
10596 slotbuf[0] = 0xa0000;
10597}
10598
10599static void
10600Opcode_srai_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
10601{
10602 slotbuf[0] = 0xe000;
10603}
10604
10605static void
10606Opcode_srai_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10607{
10608 slotbuf[0] = 0x21000;
10609}
10610
10611static void
10612Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
10613{
10614 slotbuf[0] = 0x410000;
10615}
10616
10617static void
10618Opcode_srli_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
10619{
10620 slotbuf[0] = 0xa4000;
10621}
10622
10623static void
10624Opcode_srli_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
10625{
10626 slotbuf[0] = 0x9000;
10627}
10628
10629static void
10630Opcode_srli_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
10631{
10632 slotbuf[0] = 0x41000;
10633}
10634
10635static void
10636Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
10637{
10638 slotbuf[0] = 0x20c0;
10639}
10640
10641static void
10642Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
10643{
10644 slotbuf[0] = 0x20d0;
10645}
10646
10647static void
10648Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
10649{
10650 slotbuf[0] = 0x2000;
10651}
10652
10653static void
10654Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
10655{
10656 slotbuf[0] = 0x2010;
10657}
10658
10659static void
10660Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
10661{
10662 slotbuf[0] = 0x2020;
10663}
10664
10665static void
10666Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
10667{
10668 slotbuf[0] = 0x2030;
10669}
10670
10671static void
10672Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
10673{
10674 slotbuf[0] = 0x6000;
10675}
10676
10677static void
10678Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
10679{
10680 slotbuf[0] = 0x30100;
10681}
10682
10683static void
10684Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
10685{
10686 slotbuf[0] = 0x130100;
10687}
10688
10689static void
10690Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
10691{
10692 slotbuf[0] = 0x610100;
10693}
10694
10695static void
10696Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
10697{
10698 slotbuf[0] = 0x30200;
10699}
10700
10701static void
10702Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
10703{
10704 slotbuf[0] = 0x130200;
10705}
10706
10707static void
10708Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
10709{
10710 slotbuf[0] = 0x610200;
10711}
10712
10713static void
10714Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
10715{
10716 slotbuf[0] = 0x30000;
10717}
10718
10719static void
10720Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
10721{
10722 slotbuf[0] = 0x130000;
10723}
10724
10725static void
10726Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
10727{
10728 slotbuf[0] = 0x610000;
10729}
10730
10731static void
10732Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
10733{
10734 slotbuf[0] = 0x30300;
10735}
10736
10737static void
10738Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
10739{
10740 slotbuf[0] = 0x130300;
10741}
10742
10743static void
10744Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
10745{
10746 slotbuf[0] = 0x610300;
10747}
10748
10749static void
10750Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
10751{
10752 slotbuf[0] = 0x30500;
10753}
10754
10755static void
10756Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
10757{
10758 slotbuf[0] = 0x130500;
10759}
10760
10761static void
10762Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
10763{
10764 slotbuf[0] = 0x610500;
10765}
10766
10767static void
10768Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
10769{
10770 slotbuf[0] = 0x3b000;
10771}
10772
10773static void
10774Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
10775{
10776 slotbuf[0] = 0x3d000;
10777}
10778
10779static void
10780Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
10781{
10782 slotbuf[0] = 0x3e600;
10783}
10784
10785static void
10786Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
10787{
10788 slotbuf[0] = 0x13e600;
10789}
10790
10791static void
10792Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
10793{
10794 slotbuf[0] = 0x61e600;
10795}
10796
10797static void
10798Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
10799{
10800 slotbuf[0] = 0x3b100;
10801}
10802
10803static void
10804Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
10805{
10806 slotbuf[0] = 0x13b100;
10807}
10808
10809static void
10810Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
10811{
10812 slotbuf[0] = 0x61b100;
10813}
10814
10815static void
10816Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
10817{
10818 slotbuf[0] = 0x3d100;
10819}
10820
10821static void
10822Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
10823{
10824 slotbuf[0] = 0x13d100;
10825}
10826
10827static void
10828Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
10829{
10830 slotbuf[0] = 0x61d100;
10831}
10832
10833static void
10834Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10835{
10836 slotbuf[0] = 0x3b200;
10837}
10838
10839static void
10840Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10841{
10842 slotbuf[0] = 0x13b200;
10843}
10844
10845static void
10846Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10847{
10848 slotbuf[0] = 0x61b200;
10849}
10850
10851static void
10852Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10853{
10854 slotbuf[0] = 0x3d200;
10855}
10856
10857static void
10858Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10859{
10860 slotbuf[0] = 0x13d200;
10861}
10862
10863static void
10864Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
10865{
10866 slotbuf[0] = 0x61d200;
10867}
10868
10869static void
10870Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10871{
10872 slotbuf[0] = 0x3b300;
10873}
10874
10875static void
10876Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10877{
10878 slotbuf[0] = 0x13b300;
10879}
10880
10881static void
10882Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10883{
10884 slotbuf[0] = 0x61b300;
10885}
10886
10887static void
10888Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10889{
10890 slotbuf[0] = 0x3d300;
10891}
10892
10893static void
10894Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10895{
10896 slotbuf[0] = 0x13d300;
10897}
10898
10899static void
10900Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
10901{
10902 slotbuf[0] = 0x61d300;
10903}
10904
10905static void
10906Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
10907{
10908 slotbuf[0] = 0x3b400;
10909}
10910
10911static void
10912Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
10913{
10914 slotbuf[0] = 0x13b400;
10915}
10916
10917static void
10918Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
10919{
10920 slotbuf[0] = 0x61b400;
10921}
10922
10923static void
10924Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
10925{
10926 slotbuf[0] = 0x3d400;
10927}
10928
10929static void
10930Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
10931{
10932 slotbuf[0] = 0x13d400;
10933}
10934
10935static void
10936Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
10937{
10938 slotbuf[0] = 0x61d400;
10939}
10940
10941static void
10942Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
10943{
10944 slotbuf[0] = 0x3b500;
10945}
10946
10947static void
10948Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
10949{
10950 slotbuf[0] = 0x13b500;
10951}
10952
10953static void
10954Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
10955{
10956 slotbuf[0] = 0x61b500;
10957}
10958
10959static void
10960Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
10961{
10962 slotbuf[0] = 0x3d500;
10963}
10964
10965static void
10966Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
10967{
10968 slotbuf[0] = 0x13d500;
10969}
10970
10971static void
10972Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
10973{
10974 slotbuf[0] = 0x61d500;
10975}
10976
10977static void
10978Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
10979{
10980 slotbuf[0] = 0x3b600;
10981}
10982
10983static void
10984Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
10985{
10986 slotbuf[0] = 0x13b600;
10987}
10988
10989static void
10990Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
10991{
10992 slotbuf[0] = 0x61b600;
10993}
10994
10995static void
10996Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
10997{
10998 slotbuf[0] = 0x3d600;
10999}
11000
11001static void
11002Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
11003{
11004 slotbuf[0] = 0x13d600;
11005}
11006
11007static void
11008Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
11009{
11010 slotbuf[0] = 0x61d600;
11011}
11012
11013static void
11014Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
11015{
11016 slotbuf[0] = 0x3b700;
11017}
11018
11019static void
11020Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
11021{
11022 slotbuf[0] = 0x13b700;
11023}
11024
11025static void
11026Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
11027{
11028 slotbuf[0] = 0x61b700;
11029}
11030
11031static void
11032Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
11033{
11034 slotbuf[0] = 0x3d700;
11035}
11036
11037static void
11038Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
11039{
11040 slotbuf[0] = 0x13d700;
11041}
11042
11043static void
11044Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
11045{
11046 slotbuf[0] = 0x61d700;
11047}
11048
11049static void
11050Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11051{
11052 slotbuf[0] = 0x3c200;
11053}
11054
11055static void
11056Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11057{
11058 slotbuf[0] = 0x13c200;
11059}
11060
11061static void
11062Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11063{
11064 slotbuf[0] = 0x61c200;
11065}
11066
11067static void
11068Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
11069{
11070 slotbuf[0] = 0x3c300;
11071}
11072
11073static void
11074Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
11075{
11076 slotbuf[0] = 0x13c300;
11077}
11078
11079static void
11080Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
11081{
11082 slotbuf[0] = 0x61c300;
11083}
11084
11085static void
11086Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
11087{
11088 slotbuf[0] = 0x3c400;
11089}
11090
11091static void
11092Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
11093{
11094 slotbuf[0] = 0x13c400;
11095}
11096
11097static void
11098Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
11099{
11100 slotbuf[0] = 0x61c400;
11101}
11102
11103static void
11104Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
11105{
11106 slotbuf[0] = 0x3c500;
11107}
11108
11109static void
11110Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
11111{
11112 slotbuf[0] = 0x13c500;
11113}
11114
11115static void
11116Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
11117{
11118 slotbuf[0] = 0x61c500;
11119}
11120
11121static void
11122Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
11123{
11124 slotbuf[0] = 0x3c600;
11125}
11126
11127static void
11128Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
11129{
11130 slotbuf[0] = 0x13c600;
11131}
11132
11133static void
11134Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
11135{
11136 slotbuf[0] = 0x61c600;
11137}
11138
11139static void
11140Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
11141{
11142 slotbuf[0] = 0x3c700;
11143}
11144
11145static void
11146Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
11147{
11148 slotbuf[0] = 0x13c700;
11149}
11150
11151static void
11152Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
11153{
11154 slotbuf[0] = 0x61c700;
11155}
11156
11157static void
11158Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
11159{
11160 slotbuf[0] = 0x3ee00;
11161}
11162
11163static void
11164Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
11165{
11166 slotbuf[0] = 0x13ee00;
11167}
11168
11169static void
11170Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
11171{
11172 slotbuf[0] = 0x61ee00;
11173}
11174
11175static void
11176Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11177{
11178 slotbuf[0] = 0x3c000;
11179}
11180
11181static void
11182Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11183{
11184 slotbuf[0] = 0x13c000;
11185}
11186
11187static void
11188Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
11189{
11190 slotbuf[0] = 0x61c000;
11191}
11192
11193static void
11194Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
11195{
11196 slotbuf[0] = 0x3e800;
11197}
11198
11199static void
11200Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
11201{
11202 slotbuf[0] = 0x13e800;
11203}
11204
11205static void
11206Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
11207{
11208 slotbuf[0] = 0x61e800;
11209}
11210
11211static void
11212Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11213{
11214 slotbuf[0] = 0x3f400;
11215}
11216
11217static void
11218Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11219{
11220 slotbuf[0] = 0x13f400;
11221}
11222
11223static void
11224Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
11225{
11226 slotbuf[0] = 0x61f400;
11227}
11228
11229static void
11230Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11231{
11232 slotbuf[0] = 0x3f500;
11233}
11234
11235static void
11236Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11237{
11238 slotbuf[0] = 0x13f500;
11239}
11240
11241static void
11242Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
11243{
11244 slotbuf[0] = 0x61f500;
11245}
11246
11247static void
11248Opcode_rsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11249{
11250 slotbuf[0] = 0x3f600;
11251}
11252
11253static void
11254Opcode_wsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11255{
11256 slotbuf[0] = 0x13f600;
11257}
11258
11259static void
11260Opcode_xsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
11261{
11262 slotbuf[0] = 0x61f600;
11263}
11264
11265static void
11266Opcode_rsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
11267{
11268 slotbuf[0] = 0x3f700;
11269}
11270
11271static void
11272Opcode_wsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
11273{
11274 slotbuf[0] = 0x13f700;
11275}
11276
11277static void
11278Opcode_xsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
11279{
11280 slotbuf[0] = 0x61f700;
11281}
11282
11283static void
11284Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
11285{
11286 slotbuf[0] = 0x3eb00;
11287}
11288
11289static void
11290Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
11291{
11292 slotbuf[0] = 0x3e700;
11293}
11294
11295static void
11296Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
11297{
11298 slotbuf[0] = 0x13e700;
11299}
11300
11301static void
11302Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
11303{
11304 slotbuf[0] = 0x61e700;
11305}
11306
11307static void
11308Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11309{
11310 slotbuf[0] = 0x740004;
11311}
11312
11313static void
11314Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11315{
11316 slotbuf[0] = 0x750004;
11317}
11318
11319static void
11320Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11321{
11322 slotbuf[0] = 0x760004;
11323}
11324
11325static void
11326Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11327{
11328 slotbuf[0] = 0x770004;
11329}
11330
11331static void
11332Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11333{
11334 slotbuf[0] = 0x700004;
11335}
11336
11337static void
11338Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11339{
11340 slotbuf[0] = 0x710004;
11341}
11342
11343static void
11344Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11345{
11346 slotbuf[0] = 0x720004;
11347}
11348
11349static void
11350Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11351{
11352 slotbuf[0] = 0x730004;
11353}
11354
11355static void
11356Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11357{
11358 slotbuf[0] = 0x340004;
11359}
11360
11361static void
11362Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11363{
11364 slotbuf[0] = 0x350004;
11365}
11366
11367static void
11368Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11369{
11370 slotbuf[0] = 0x360004;
11371}
11372
11373static void
11374Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11375{
11376 slotbuf[0] = 0x370004;
11377}
11378
11379static void
11380Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11381{
11382 slotbuf[0] = 0x640004;
11383}
11384
11385static void
11386Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11387{
11388 slotbuf[0] = 0x650004;
11389}
11390
11391static void
11392Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11393{
11394 slotbuf[0] = 0x660004;
11395}
11396
11397static void
11398Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11399{
11400 slotbuf[0] = 0x670004;
11401}
11402
11403static void
11404Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11405{
11406 slotbuf[0] = 0x240004;
11407}
11408
11409static void
11410Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11411{
11412 slotbuf[0] = 0x250004;
11413}
11414
11415static void
11416Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11417{
11418 slotbuf[0] = 0x260004;
11419}
11420
11421static void
11422Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11423{
11424 slotbuf[0] = 0x270004;
11425}
11426
11427static void
11428Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11429{
11430 slotbuf[0] = 0x780004;
11431}
11432
11433static void
11434Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11435{
11436 slotbuf[0] = 0x790004;
11437}
11438
11439static void
11440Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11441{
11442 slotbuf[0] = 0x7a0004;
11443}
11444
11445static void
11446Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11447{
11448 slotbuf[0] = 0x7b0004;
11449}
11450
11451static void
11452Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11453{
11454 slotbuf[0] = 0x7c0004;
11455}
11456
11457static void
11458Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11459{
11460 slotbuf[0] = 0x7d0004;
11461}
11462
11463static void
11464Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11465{
11466 slotbuf[0] = 0x7e0004;
11467}
11468
11469static void
11470Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11471{
11472 slotbuf[0] = 0x7f0004;
11473}
11474
11475static void
11476Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11477{
11478 slotbuf[0] = 0x380004;
11479}
11480
11481static void
11482Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11483{
11484 slotbuf[0] = 0x390004;
11485}
11486
11487static void
11488Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11489{
11490 slotbuf[0] = 0x3a0004;
11491}
11492
11493static void
11494Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11495{
11496 slotbuf[0] = 0x3b0004;
11497}
11498
11499static void
11500Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11501{
11502 slotbuf[0] = 0x3c0004;
11503}
11504
11505static void
11506Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11507{
11508 slotbuf[0] = 0x3d0004;
11509}
11510
11511static void
11512Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11513{
11514 slotbuf[0] = 0x3e0004;
11515}
11516
11517static void
11518Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11519{
11520 slotbuf[0] = 0x3f0004;
11521}
11522
11523static void
11524Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11525{
11526 slotbuf[0] = 0x680004;
11527}
11528
11529static void
11530Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11531{
11532 slotbuf[0] = 0x690004;
11533}
11534
11535static void
11536Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11537{
11538 slotbuf[0] = 0x6a0004;
11539}
11540
11541static void
11542Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
11543{
11544 slotbuf[0] = 0x6b0004;
11545}
11546
11547static void
11548Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
11549{
11550 slotbuf[0] = 0x6c0004;
11551}
56fb3749 11552
7aa09196
SA		 11553static void
11554Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
11555{
11556 slotbuf[0] = 0x6d0004;
11557}
43cd72b9
BW		 11558
11559static void
7aa09196 11560Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11561{
7aa09196 11562 slotbuf[0] = 0x6e0004;
43cd72b9
BW		 11563}
11564
11565static void
7aa09196 11566Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11567{
7aa09196 11568 slotbuf[0] = 0x6f0004;
43cd72b9
BW		 11569}
11570
11571static void
7aa09196 11572Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11573{
7aa09196 11574 slotbuf[0] = 0x280004;
43cd72b9
BW		 11575}
11576
11577static void
7aa09196 11578Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11579{
7aa09196 11580 slotbuf[0] = 0x290004;
43cd72b9
BW		 11581}
11582
11583static void
7aa09196 11584Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11585{
7aa09196 11586 slotbuf[0] = 0x2a0004;
43cd72b9
BW		 11587}
11588
11589static void
7aa09196 11590Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11591{
7aa09196 11592 slotbuf[0] = 0x2b0004;
43cd72b9
BW		 11593}
11594
11595static void
7aa09196 11596Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11597{
7aa09196 11598 slotbuf[0] = 0x2c0004;
43cd72b9
BW		 11599}
11600
11601static void
7aa09196 11602Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11603{
7aa09196 11604 slotbuf[0] = 0x2d0004;
43cd72b9
BW		 11605}
11606
11607static void
7aa09196 11608Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11609{
7aa09196 11610 slotbuf[0] = 0x2e0004;
43cd72b9
BW		 11611}
11612
11613static void
7aa09196 11614Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11615{
7aa09196 11616 slotbuf[0] = 0x2f0004;
43cd72b9
BW		 11617}
11618
11619static void
7aa09196 11620Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11621{
7aa09196 11622 slotbuf[0] = 0x580004;
43cd72b9
BW		 11623}
11624
11625static void
7aa09196 11626Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11627{
7aa09196 11628 slotbuf[0] = 0x480004;
43cd72b9
BW		 11629}
11630
11631static void
7aa09196 11632Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11633{
7aa09196 11634 slotbuf[0] = 0x590004;
43cd72b9
BW		 11635}
11636
11637static void
7aa09196 11638Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11639{
7aa09196 11640 slotbuf[0] = 0x490004;
43cd72b9
BW		 11641}
11642
11643static void
7aa09196 11644Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11645{
7aa09196 11646 slotbuf[0] = 0x5a0004;
43cd72b9
BW		 11647}
11648
11649static void
7aa09196 11650Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11651{
7aa09196 11652 slotbuf[0] = 0x4a0004;
43cd72b9
BW		 11653}
11654
11655static void
7aa09196 11656Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11657{
7aa09196 11658 slotbuf[0] = 0x5b0004;
43cd72b9
BW		 11659}
11660
11661static void
7aa09196 11662Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11663{
7aa09196 11664 slotbuf[0] = 0x4b0004;
43cd72b9
BW		 11665}
11666
11667static void
7aa09196 11668Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11669{
7aa09196 11670 slotbuf[0] = 0x180004;
43cd72b9
BW		 11671}
11672
11673static void
7aa09196 11674Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11675{
7aa09196 11676 slotbuf[0] = 0x80004;
43cd72b9
BW		 11677}
11678
11679static void
7aa09196 11680Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11681{
7aa09196 11682 slotbuf[0] = 0x190004;
43cd72b9
BW		 11683}
11684
11685static void
7aa09196 11686Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11687{
7aa09196 11688 slotbuf[0] = 0x90004;
43cd72b9
BW		 11689}
11690
11691static void
7aa09196 11692Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11693{
7aa09196 11694 slotbuf[0] = 0x1a0004;
43cd72b9
BW		 11695}
11696
11697static void
7aa09196 11698Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11699{
7aa09196 11700 slotbuf[0] = 0xa0004;
43cd72b9
BW		 11701}
11702
11703static void
7aa09196 11704Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11705{
7aa09196 11706 slotbuf[0] = 0x1b0004;
43cd72b9
BW		 11707}
11708
11709static void
7aa09196 11710Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11711{
7aa09196 11712 slotbuf[0] = 0xb0004;
43cd72b9
BW		 11713}
11714
11715static void
7aa09196 11716Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11717{
7aa09196 11718 slotbuf[0] = 0x900004;
43cd72b9
BW		 11719}
11720
11721static void
7aa09196 11722Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11723{
7aa09196 11724 slotbuf[0] = 0x800004;
43cd72b9
BW		 11725}
11726
11727static void
7aa09196 11728Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11729{
7aa09196 11730 slotbuf[0] = 0xc10000;
43cd72b9
BW		 11731}
11732
11733static void
7aa09196 11734Opcode_mul16u_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
43cd72b9 11735{
7aa09196 11736 slotbuf[0] = 0x9b000;
43cd72b9
BW		 11737}
11738
11739static void
7aa09196 11740Opcode_mul16u_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
43cd72b9 11741{
7aa09196 11742 slotbuf[0] = 0xc1000;
43cd72b9
BW		 11743}
11744
11745static void
7aa09196 11746Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11747{
7aa09196 11748 slotbuf[0] = 0xd10000;
43cd72b9
BW		 11749}
11750
11751static void
7aa09196 11752Opcode_mul16s_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
43cd72b9 11753{
7aa09196 11754 slotbuf[0] = 0x9c000;
43cd72b9
BW		 11755}
11756
11757static void
7aa09196 11758Opcode_mul16s_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
43cd72b9 11759{
7aa09196 11760 slotbuf[0] = 0xd1000;
43cd72b9
BW		 11761}
11762
11763static void
7aa09196 11764Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11765{
7aa09196 11766 slotbuf[0] = 0x32000;
43cd72b9
BW		 11767}
11768
11769static void
7aa09196 11770Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11771{
7aa09196 11772 slotbuf[0] = 0x132000;
43cd72b9
BW		 11773}
11774
11775static void
7aa09196 11776Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11777{
7aa09196 11778 slotbuf[0] = 0x612000;
43cd72b9
BW		 11779}
11780
33430bd0 11781static void
7aa09196 11782Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 11783{
7aa09196 11784 slotbuf[0] = 0x32100;
33430bd0
BW		 11785}
11786
11787static void
7aa09196 11788Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 11789{
7aa09196 11790 slotbuf[0] = 0x132100;
33430bd0
BW		 11791}
11792
43cd72b9 11793static void
7aa09196 11794Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11795{
7aa09196 11796 slotbuf[0] = 0x612100;
43cd72b9
BW		 11797}
11798
11799static void
7aa09196 11800Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11801{
7aa09196 11802 slotbuf[0] = 0x32200;
43cd72b9
BW		 11803}
11804
11805static void
7aa09196 11806Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11807{
7aa09196 11808 slotbuf[0] = 0x132200;
43cd72b9
BW		 11809}
11810
11811static void
7aa09196 11812Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11813{
7aa09196 11814 slotbuf[0] = 0x612200;
43cd72b9
BW		 11815}
11816
11817static void
7aa09196 11818Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11819{
7aa09196 11820 slotbuf[0] = 0x32300;
43cd72b9
BW		 11821}
11822
11823static void
7aa09196 11824Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11825{
7aa09196 11826 slotbuf[0] = 0x132300;
43cd72b9
BW		 11827}
11828
11829static void
7aa09196 11830Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11831{
7aa09196 11832 slotbuf[0] = 0x612300;
43cd72b9
BW		 11833}
11834
11835static void
7aa09196 11836Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11837{
7aa09196 11838 slotbuf[0] = 0x31000;
43cd72b9
BW		 11839}
11840
11841static void
7aa09196 11842Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11843{
7aa09196 11844 slotbuf[0] = 0x131000;
43cd72b9
BW		 11845}
11846
11847static void
7aa09196 11848Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11849{
7aa09196 11850 slotbuf[0] = 0x611000;
43cd72b9
BW		 11851}
11852
11853static void
7aa09196 11854Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11855{
7aa09196 11856 slotbuf[0] = 0x31100;
43cd72b9
BW		 11857}
11858
11859static void
7aa09196 11860Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11861{
7aa09196 11862 slotbuf[0] = 0x131100;
43cd72b9
BW		 11863}
11864
11865static void
7aa09196 11866Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11867{
7aa09196 11868 slotbuf[0] = 0x611100;
43cd72b9
BW		 11869}
11870
11871static void
7aa09196 11872Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11873{
7aa09196 11874 slotbuf[0] = 0x3010;
43cd72b9
BW		 11875}
11876
11877static void
7aa09196 11878Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11879{
7aa09196 11880 slotbuf[0] = 0x7000;
43cd72b9
BW		 11881}
11882
11883static void
7aa09196 11884Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11885{
7aa09196 11886 slotbuf[0] = 0x3e200;
43cd72b9
BW		 11887}
11888
11889static void
7aa09196 11890Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11891{
7aa09196 11892 slotbuf[0] = 0x13e200;
43cd72b9
BW		 11893}
11894
11895static void
7aa09196 11896Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11897{
7aa09196 11898 slotbuf[0] = 0x13e300;
43cd72b9
BW		 11899}
11900
11901static void
7aa09196 11902Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11903{
7aa09196 11904 slotbuf[0] = 0x3e400;
43cd72b9
BW		 11905}
11906
11907static void
7aa09196 11908Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11909{
7aa09196 11910 slotbuf[0] = 0x13e400;
43cd72b9
BW		 11911}
11912
11913static void
7aa09196 11914Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11915{
7aa09196 11916 slotbuf[0] = 0x61e400;
43cd72b9
BW		 11917}
11918
11919static void
7aa09196 11920Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11921{
7aa09196 11922 slotbuf[0] = 0x4000;
43cd72b9
BW		 11923}
11924
11925static void
7aa09196 11926Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
43cd72b9 11927{
7aa09196 11928 slotbuf[0] = 0xf02d;
43cd72b9
BW		 11929}
11930
11931static void
7aa09196 11932Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11933{
7aa09196 11934 slotbuf[0] = 0x39000;
43cd72b9
BW		 11935}
11936
11937static void
7aa09196 11938Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11939{
7aa09196 11940 slotbuf[0] = 0x139000;
43cd72b9
BW		 11941}
11942
11943static void
7aa09196 11944Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11945{
7aa09196 11946 slotbuf[0] = 0x619000;
43cd72b9
BW		 11947}
11948
11949static void
7aa09196 11950Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11951{
7aa09196 11952 slotbuf[0] = 0x3a000;
43cd72b9
BW		 11953}
11954
11955static void
7aa09196 11956Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11957{
7aa09196 11958 slotbuf[0] = 0x13a000;
43cd72b9
BW		 11959}
11960
11961static void
7aa09196 11962Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11963{
7aa09196 11964 slotbuf[0] = 0x61a000;
43cd72b9
BW		 11965}
11966
11967static void
7aa09196 11968Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11969{
7aa09196 11970 slotbuf[0] = 0x39100;
43cd72b9
BW		 11971}
11972
11973static void
7aa09196 11974Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11975{
7aa09196 11976 slotbuf[0] = 0x139100;
43cd72b9
BW		 11977}
11978
11979static void
7aa09196 11980Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11981{
7aa09196 11982 slotbuf[0] = 0x619100;
43cd72b9
BW		 11983}
11984
11985static void
7aa09196 11986Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11987{
7aa09196 11988 slotbuf[0] = 0x3a100;
43cd72b9
BW		 11989}
11990
11991static void
7aa09196 11992Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11993{
7aa09196 11994 slotbuf[0] = 0x13a100;
43cd72b9
BW		 11995}
11996
11997static void
7aa09196 11998Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 11999{
7aa09196 12000 slotbuf[0] = 0x61a100;
43cd72b9
BW		 12001}
12002
12003static void
7aa09196 12004Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12005{
7aa09196 12006 slotbuf[0] = 0x38000;
43cd72b9
BW		 12007}
12008
12009static void
7aa09196 12010Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12011{
7aa09196 12012 slotbuf[0] = 0x138000;
43cd72b9
BW		 12013}
12014
12015static void
7aa09196 12016Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12017{
7aa09196 12018 slotbuf[0] = 0x618000;
43cd72b9
BW		 12019}
12020
12021static void
7aa09196 12022Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12023{
7aa09196 12024 slotbuf[0] = 0x38100;
43cd72b9
BW		 12025}
12026
12027static void
7aa09196 12028Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12029{
7aa09196 12030 slotbuf[0] = 0x138100;
43cd72b9
BW		 12031}
12032
12033static void
7aa09196 12034Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12035{
7aa09196 12036 slotbuf[0] = 0x618100;
43cd72b9
BW		 12037}
12038
12039static void
7aa09196 12040Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12041{
7aa09196 12042 slotbuf[0] = 0x36000;
43cd72b9
BW		 12043}
12044
12045static void
7aa09196 12046Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12047{
7aa09196 12048 slotbuf[0] = 0x136000;
43cd72b9
BW		 12049}
12050
12051static void
7aa09196 12052Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12053{
7aa09196 12054 slotbuf[0] = 0x616000;
43cd72b9
BW		 12055}
12056
12057static void
7aa09196 12058Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12059{
7aa09196 12060 slotbuf[0] = 0x3e900;
43cd72b9
BW		 12061}
12062
12063static void
7aa09196 12064Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12065{
7aa09196 12066 slotbuf[0] = 0x13e900;
43cd72b9
BW		 12067}
12068
12069static void
7aa09196 12070Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12071{
7aa09196 12072 slotbuf[0] = 0x61e900;
43cd72b9
BW		 12073}
12074
12075static void
7aa09196 12076Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12077{
7aa09196 12078 slotbuf[0] = 0x3ec00;
43cd72b9
BW		 12079}
12080
12081static void
7aa09196 12082Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12083{
7aa09196 12084 slotbuf[0] = 0x13ec00;
43cd72b9
BW		 12085}
12086
12087static void
7aa09196
SA		 12088Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
12089{
12090 slotbuf[0] = 0x61ec00;
12091}
12092
12093static void
12094Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
12095{
12096 slotbuf[0] = 0x3ed00;
12097}
12098
12099static void
12100Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
12101{
12102 slotbuf[0] = 0x13ed00;
12103}
12104
12105static void
12106Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
12107{
12108 slotbuf[0] = 0x61ed00;
12109}
12110
12111static void
12112Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12113{
12114 slotbuf[0] = 0x36800;
12115}
12116
12117static void
12118Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12119{
12120 slotbuf[0] = 0x136800;
12121}
12122
12123static void
12124Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
12125{
12126 slotbuf[0] = 0x616800;
12127}
12128
12129static void
12130Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
12131{
12132 slotbuf[0] = 0xf1e000;
12133}
12134
12135static void
12136Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
12137{
12138 slotbuf[0] = 0xf1e010;
12139}
12140
12141static void
12142Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
12143{
12144 slotbuf[0] = 0x135900;
12145}
12146
12147static void
12148Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12149{
12150 slotbuf[0] = 0x20000;
12151}
12152
12153static void
12154Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12155{
7aa09196
SA		 12156 slotbuf[0] = 0x120000;
12157}
12158
12159static void
12160Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12161{
12162 slotbuf[0] = 0x220000;
12163}
12164
12165static void
12166Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
12167{
12168 slotbuf[0] = 0x320000;
12169}
12170
12171static void
12172Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf)
12173{
12174 slotbuf[0] = 0x420000;
12175}
12176
12177static void
12178Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf)
12179{
12180 slotbuf[0] = 0x8000;
12181}
12182
12183static void
12184Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf)
12185{
12186 slotbuf[0] = 0x9000;
12187}
12188
12189static void
12190Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf)
12191{
12192 slotbuf[0] = 0xa000;
12193}
12194
12195static void
12196Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf)
12197{
12198 slotbuf[0] = 0xb000;
43cd72b9
BW		 12199}
12200
12201static void
7aa09196 12202Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12203{
7aa09196 12204 slotbuf[0] = 0x76;
43cd72b9
BW		 12205}
12206
12207static void
7aa09196 12208Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12209{
7aa09196 12210 slotbuf[0] = 0x1076;
43cd72b9
BW		 12211}
12212
12213static void
7aa09196 12214Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12215{
7aa09196 12216 slotbuf[0] = 0xc30000;
43cd72b9
BW		 12217}
12218
12219static void
7aa09196 12220Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12221{
7aa09196 12222 slotbuf[0] = 0xd30000;
43cd72b9
BW		 12223}
12224
12225static void
7aa09196 12226Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12227{
7aa09196 12228 slotbuf[0] = 0x30400;
43cd72b9
BW		 12229}
12230
12231static void
7aa09196 12232Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12233{
7aa09196 12234 slotbuf[0] = 0x130400;
43cd72b9
BW		 12235}
12236
12237static void
7aa09196 12238Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12239{
7aa09196 12240 slotbuf[0] = 0x610400;
43cd72b9
BW		 12241}
12242
12243static void
7aa09196 12244Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12245{
7aa09196 12246 slotbuf[0] = 0x3ea00;
43cd72b9
BW		 12247}
12248
12249static void
7aa09196 12250Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12251{
7aa09196 12252 slotbuf[0] = 0x13ea00;
43cd72b9
BW		 12253}
12254
12255static void
7aa09196 12256Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12257{
7aa09196 12258 slotbuf[0] = 0x61ea00;
43cd72b9
BW		 12259}
12260
12261static void
7aa09196 12262Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12263{
7aa09196 12264 slotbuf[0] = 0x3f000;
43cd72b9
BW		 12265}
12266
12267static void
7aa09196 12268Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12269{
7aa09196 12270 slotbuf[0] = 0x13f000;
43cd72b9
BW		 12271}
12272
12273static void
7aa09196 12274Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12275{
7aa09196 12276 slotbuf[0] = 0x61f000;
43cd72b9
BW		 12277}
12278
12279static void
7aa09196 12280Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12281{
7aa09196 12282 slotbuf[0] = 0x3f100;
43cd72b9
BW		 12283}
12284
12285static void
7aa09196 12286Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12287{
7aa09196 12288 slotbuf[0] = 0x13f100;
43cd72b9
BW		 12289}
12290
12291static void
7aa09196 12292Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12293{
7aa09196 12294 slotbuf[0] = 0x61f100;
43cd72b9
BW		 12295}
12296
12297static void
7aa09196 12298Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12299{
7aa09196 12300 slotbuf[0] = 0x3f200;
43cd72b9
BW		 12301}
12302
12303static void
7aa09196 12304Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12305{
7aa09196 12306 slotbuf[0] = 0x13f200;
43cd72b9
BW		 12307}
12308
12309static void
7aa09196 12310Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12311{
7aa09196 12312 slotbuf[0] = 0x61f200;
43cd72b9
BW		 12313}
12314
12315static void
7aa09196 12316Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12317{
7aa09196 12318 slotbuf[0] = 0x70c2;
43cd72b9
BW		 12319}
12320
12321static void
7aa09196 12322Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12323{
7aa09196 12324 slotbuf[0] = 0x70e2;
43cd72b9
BW		 12325}
12326
12327static void
7aa09196 12328Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12329{
7aa09196 12330 slotbuf[0] = 0x70d2;
43cd72b9
BW		 12331}
12332
12333static void
7aa09196 12334Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12335{
7aa09196 12336 slotbuf[0] = 0x270d2;
43cd72b9
BW		 12337}
12338
12339static void
7aa09196 12340Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12341{
7aa09196 12342 slotbuf[0] = 0x370d2;
43cd72b9
BW		 12343}
12344
12345static void
7aa09196 12346Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12347{
7aa09196 12348 slotbuf[0] = 0x70f2;
43cd72b9
BW		 12349}
12350
12351static void
7aa09196 12352Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12353{
7aa09196 12354 slotbuf[0] = 0xf10000;
43cd72b9
BW		 12355}
12356
12357static void
7aa09196 12358Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12359{
7aa09196 12360 slotbuf[0] = 0xf12000;
43cd72b9
BW		 12361}
12362
12363static void
7aa09196 12364Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12365{
7aa09196 12366 slotbuf[0] = 0xf11000;
43cd72b9
BW		 12367}
12368
12369static void
7aa09196 12370Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12371{
7aa09196 12372 slotbuf[0] = 0xf13000;
43cd72b9
BW		 12373}
12374
12375static void
7aa09196 12376Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12377{
7aa09196 12378 slotbuf[0] = 0x7042;
43cd72b9
BW		 12379}
12380
12381static void
7aa09196 12382Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12383{
7aa09196 12384 slotbuf[0] = 0x7052;
43cd72b9
BW		 12385}
12386
12387static void
7aa09196 12388Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12389{
7aa09196 12390 slotbuf[0] = 0x47082;
43cd72b9
BW		 12391}
12392
12393static void
7aa09196 12394Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12395{
7aa09196 12396 slotbuf[0] = 0x57082;
43cd72b9
BW		 12397}
12398
12399static void
7aa09196 12400Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12401{
7aa09196 12402 slotbuf[0] = 0x7062;
43cd72b9
BW		 12403}
12404
12405static void
7aa09196 12406Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12407{
7aa09196 12408 slotbuf[0] = 0x7072;
43cd72b9
BW		 12409}
12410
12411static void
7aa09196 12412Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12413{
7aa09196 12414 slotbuf[0] = 0x7002;
43cd72b9
BW		 12415}
12416
12417static void
7aa09196 12418Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12419{
7aa09196 12420 slotbuf[0] = 0x7012;
43cd72b9
BW		 12421}
12422
12423static void
7aa09196 12424Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12425{
7aa09196 12426 slotbuf[0] = 0x7022;
43cd72b9
BW		 12427}
12428
12429static void
7aa09196 12430Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12431{
7aa09196 12432 slotbuf[0] = 0x7032;
43cd72b9
BW		 12433}
12434
12435static void
7aa09196 12436Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12437{
7aa09196 12438 slotbuf[0] = 0x7082;
43cd72b9
BW		 12439}
12440
12441static void
7aa09196 12442Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12443{
7aa09196 12444 slotbuf[0] = 0x27082;
43cd72b9
BW		 12445}
12446
12447static void
7aa09196 12448Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12449{
7aa09196 12450 slotbuf[0] = 0x37082;
43cd72b9
BW		 12451}
12452
12453static void
7aa09196 12454Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12455{
7aa09196 12456 slotbuf[0] = 0xf19000;
43cd72b9
BW		 12457}
12458
12459static void
7aa09196 12460Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12461{
7aa09196 12462 slotbuf[0] = 0xf18000;
43cd72b9
BW		 12463}
12464
12465static void
7aa09196 12466Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12467{
7aa09196 12468 slotbuf[0] = 0x135300;
43cd72b9
BW		 12469}
12470
12471static void
7aa09196 12472Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12473{
7aa09196 12474 slotbuf[0] = 0x35300;
33430bd0
BW		 12475}
12476
12477static void
7aa09196 12478Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12479{
7aa09196 12480 slotbuf[0] = 0x615300;
33430bd0
BW		 12481}
12482
12483static void
7aa09196 12484Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12485{
7aa09196 12486 slotbuf[0] = 0x35a00;
33430bd0
BW		 12487}
12488
12489static void
7aa09196 12490Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12491{
7aa09196 12492 slotbuf[0] = 0x135a00;
33430bd0
BW		 12493}
12494
12495static void
7aa09196 12496Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12497{
7aa09196 12498 slotbuf[0] = 0x615a00;
33430bd0
BW		 12499}
12500
12501static void
7aa09196 12502Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12503{
7aa09196 12504 slotbuf[0] = 0x35b00;
33430bd0
BW		 12505}
12506
12507static void
7aa09196 12508Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12509{
7aa09196 12510 slotbuf[0] = 0x135b00;
33430bd0
BW		 12511}
12512
12513static void
7aa09196 12514Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12515{
7aa09196 12516 slotbuf[0] = 0x615b00;
33430bd0
BW		 12517}
12518
12519static void
7aa09196 12520Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12521{
7aa09196 12522 slotbuf[0] = 0x35c00;
33430bd0
BW		 12523}
12524
12525static void
7aa09196 12526Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12527{
7aa09196 12528 slotbuf[0] = 0x135c00;
33430bd0
BW		 12529}
12530
12531static void
7aa09196 12532Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12533{
7aa09196 12534 slotbuf[0] = 0x615c00;
33430bd0
BW		 12535}
12536
12537static void
7aa09196 12538Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12539{
7aa09196 12540 slotbuf[0] = 0x50c000;
33430bd0
BW		 12541}
12542
12543static void
7aa09196 12544Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12545{
7aa09196 12546 slotbuf[0] = 0x50d000;
33430bd0
BW		 12547}
12548
12549static void
7aa09196 12550Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12551{
7aa09196 12552 slotbuf[0] = 0x50b000;
33430bd0
BW		 12553}
12554
12555static void
7aa09196 12556Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12557{
7aa09196 12558 slotbuf[0] = 0x50f000;
33430bd0
BW		 12559}
12560
12561static void
7aa09196 12562Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12563{
7aa09196 12564 slotbuf[0] = 0x50e000;
33430bd0
BW		 12565}
12566
12567static void
7aa09196 12568Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12569{
7aa09196 12570 slotbuf[0] = 0x504000;
33430bd0
BW		 12571}
12572
12573static void
7aa09196 12574Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12575{
7aa09196 12576 slotbuf[0] = 0x505000;
33430bd0
BW		 12577}
12578
12579static void
7aa09196 12580Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12581{
7aa09196 12582 slotbuf[0] = 0x503000;
33430bd0
BW		 12583}
12584
12585static void
7aa09196 12586Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12587{
7aa09196 12588 slotbuf[0] = 0x507000;
33430bd0
BW		 12589}
12590
12591static void
7aa09196 12592Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12593{
7aa09196 12594 slotbuf[0] = 0x506000;
33430bd0
BW		 12595}
12596
12597static void
7aa09196 12598Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12599{
7aa09196 12600 slotbuf[0] = 0xf1f000;
33430bd0
BW		 12601}
12602
12603static void
7aa09196 12604Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12605{
7aa09196 12606 slotbuf[0] = 0x501000;
33430bd0
BW		 12607}
12608
12609static void
7aa09196 12610Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12611{
7aa09196 12612 slotbuf[0] = 0x509000;
33430bd0
BW		 12613}
12614
12615static void
7aa09196 12616Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12617{
7aa09196 12618 slotbuf[0] = 0x3e000;
33430bd0
BW		 12619}
12620
12621static void
7aa09196 12622Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12623{
7aa09196 12624 slotbuf[0] = 0x13e000;
33430bd0
BW		 12625}
12626
12627static void
7aa09196 12628Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12629{
7aa09196 12630 slotbuf[0] = 0x61e000;
33430bd0
BW		 12631}
12632
12633static void
7aa09196 12634Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12635{
7aa09196 12636 slotbuf[0] = 0x330000;
33430bd0
BW		 12637}
12638
12639static void
7aa09196 12640Opcode_clamps_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
43cd72b9 12641{
7aa09196 12642 slotbuf[0] = 0x33000;
43cd72b9
BW		 12643}
12644
12645static void
7aa09196 12646Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12647{
7aa09196 12648 slotbuf[0] = 0x430000;
43cd72b9
BW		 12649}
12650
12651static void
7aa09196 12652Opcode_min_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
43cd72b9 12653{
7aa09196 12654 slotbuf[0] = 0x43000;
43cd72b9
BW		 12655}
12656
12657static void
7aa09196 12658Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12659{
7aa09196 12660 slotbuf[0] = 0x530000;
43cd72b9
BW		 12661}
12662
12663static void
7aa09196 12664Opcode_max_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
43cd72b9 12665{
7aa09196 12666 slotbuf[0] = 0x53000;
43cd72b9
BW		 12667}
12668
12669static void
7aa09196 12670Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12671{
7aa09196 12672 slotbuf[0] = 0x630000;
43cd72b9
BW		 12673}
12674
12675static void
7aa09196 12676Opcode_minu_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
43cd72b9 12677{
7aa09196 12678 slotbuf[0] = 0x63000;
43cd72b9
BW		 12679}
12680
12681static void
7aa09196 12682Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12683{
7aa09196 12684 slotbuf[0] = 0x730000;
43cd72b9
BW		 12685}
12686
12687static void
7aa09196 12688Opcode_maxu_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
43cd72b9 12689{
7aa09196 12690 slotbuf[0] = 0x73000;
43cd72b9
BW		 12691}
12692
12693static void
7aa09196 12694Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12695{
7aa09196 12696 slotbuf[0] = 0x40e000;
43cd72b9
BW		 12697}
12698
12699static void
7aa09196 12700Opcode_nsa_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
43cd72b9 12701{
7aa09196 12702 slotbuf[0] = 0x40e00;
43cd72b9
BW		 12703}
12704
12705static void
7aa09196 12706Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12707{
7aa09196 12708 slotbuf[0] = 0x40f000;
43cd72b9
BW		 12709}
12710
12711static void
7aa09196 12712Opcode_nsau_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
43cd72b9 12713{
7aa09196 12714 slotbuf[0] = 0x40f00;
43cd72b9
BW		 12715}
12716
12717static void
7aa09196 12718Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12719{
7aa09196 12720 slotbuf[0] = 0x230000;
43cd72b9
BW		 12721}
12722
12723static void
7aa09196 12724Opcode_sext_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
43cd72b9 12725{
7aa09196 12726 slotbuf[0] = 0x9f000;
43cd72b9
BW		 12727}
12728
12729static void
7aa09196 12730Opcode_sext_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
43cd72b9 12731{
7aa09196 12732 slotbuf[0] = 0x8000;
43cd72b9
BW		 12733}
12734
12735static void
7aa09196 12736Opcode_sext_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
43cd72b9 12737{
7aa09196 12738 slotbuf[0] = 0x23000;
43cd72b9
BW		 12739}
12740
12741static void
7aa09196 12742Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12743{
7aa09196 12744 slotbuf[0] = 0xb002;
43cd72b9
BW		 12745}
12746
12747static void
7aa09196 12748Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12749{
7aa09196 12750 slotbuf[0] = 0xf002;
43cd72b9
BW		 12751}
12752
12753static void
7aa09196 12754Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12755{
7aa09196 12756 slotbuf[0] = 0xe002;
43cd72b9
BW		 12757}
12758
12759static void
7aa09196 12760Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12761{
7aa09196 12762 slotbuf[0] = 0x30c00;
43cd72b9
BW		 12763}
12764
12765static void
7aa09196 12766Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12767{
7aa09196 12768 slotbuf[0] = 0x130c00;
43cd72b9
BW		 12769}
12770
12771static void
7aa09196 12772Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12773{
7aa09196 12774 slotbuf[0] = 0x610c00;
43cd72b9
BW		 12775}
12776
12777static void
7aa09196 12778Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12779{
7aa09196 12780 slotbuf[0] = 0xc20000;
43cd72b9
BW		 12781}
12782
12783static void
7aa09196 12784Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12785{
7aa09196 12786 slotbuf[0] = 0xd20000;
43cd72b9
BW		 12787}
12788
12789static void
7aa09196 12790Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12791{
7aa09196 12792 slotbuf[0] = 0xe20000;
43cd72b9
BW		 12793}
12794
12795static void
7aa09196 12796Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12797{
7aa09196 12798 slotbuf[0] = 0xf20000;
43cd72b9
BW		 12799}
12800
12801static void
7aa09196 12802Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12803{
7aa09196 12804 slotbuf[0] = 0x820000;
43cd72b9
BW		 12805}
12806
12807static void
7aa09196 12808Opcode_mull_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
43cd72b9 12809{
7aa09196 12810 slotbuf[0] = 0x9d000;
43cd72b9
BW		 12811}
12812
12813static void
7aa09196 12814Opcode_mull_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
43cd72b9 12815{
7aa09196 12816 slotbuf[0] = 0x82000;
43cd72b9
BW		 12817}
12818
12819static void
7aa09196 12820Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12821{
7aa09196 12822 slotbuf[0] = 0xa20000;
43cd72b9
BW		 12823}
12824
12825static void
7aa09196 12826Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12827{
7aa09196 12828 slotbuf[0] = 0xb20000;
43cd72b9
BW		 12829}
12830
12831static void
7aa09196 12832Opcode_rur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12833{
7aa09196 12834 slotbuf[0] = 0xe30e80;
43cd72b9
BW		 12835}
12836
12837static void
7aa09196 12838Opcode_wur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12839{
7aa09196 12840 slotbuf[0] = 0xf3e800;
43cd72b9
BW		 12841}
12842
12843static void
7aa09196 12844Opcode_rur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12845{
7aa09196 12846 slotbuf[0] = 0xe30e90;
43cd72b9
BW		 12847}
12848
12849static void
7aa09196 12850Opcode_wur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12851{
7aa09196 12852 slotbuf[0] = 0xf3e900;
43cd72b9
BW		 12853}
12854
12855static void
7aa09196 12856Opcode_add_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12857{
7aa09196 12858 slotbuf[0] = 0xa0000;
43cd72b9
BW		 12859}
12860
12861static void
7aa09196 12862Opcode_sub_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12863{
7aa09196 12864 slotbuf[0] = 0x1a0000;
43cd72b9
BW		 12865}
12866
12867static void
7aa09196 12868Opcode_mul_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12869{
7aa09196 12870 slotbuf[0] = 0x2a0000;
43cd72b9
BW		 12871}
12872
12873static void
7aa09196 12874Opcode_madd_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12875{
7aa09196 12876 slotbuf[0] = 0x4a0000;
43cd72b9
BW		 12877}
12878
12879static void
7aa09196 12880Opcode_msub_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12881{
7aa09196 12882 slotbuf[0] = 0x5a0000;
43cd72b9
BW		 12883}
12884
12885static void
7aa09196 12886Opcode_movf_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12887{
7aa09196 12888 slotbuf[0] = 0xcb0000;
43cd72b9
BW		 12889}
12890
12891static void
7aa09196 12892Opcode_movt_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12893{
7aa09196 12894 slotbuf[0] = 0xdb0000;
43cd72b9
BW		 12895}
12896
12897static void
7aa09196 12898Opcode_moveqz_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12899{
7aa09196 12900 slotbuf[0] = 0x8b0000;
43cd72b9
BW		 12901}
12902
12903static void
7aa09196 12904Opcode_movnez_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12905{
7aa09196 12906 slotbuf[0] = 0x9b0000;
43cd72b9
BW		 12907}
12908
12909static void
7aa09196 12910Opcode_movltz_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12911{
7aa09196 12912 slotbuf[0] = 0xab0000;
43cd72b9
BW		 12913}
12914
12915static void
7aa09196 12916Opcode_movgez_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12917{
7aa09196 12918 slotbuf[0] = 0xbb0000;
43cd72b9
BW		 12919}
12920
12921static void
7aa09196 12922Opcode_abs_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12923{
7aa09196 12924 slotbuf[0] = 0xfa0010;
43cd72b9
BW		 12925}
12926
12927static void
7aa09196 12928Opcode_mov_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12929{
7aa09196 12930 slotbuf[0] = 0xfa0000;
43cd72b9
BW		 12931}
12932
12933static void
7aa09196 12934Opcode_neg_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12935{
7aa09196 12936 slotbuf[0] = 0xfa0060;
43cd72b9
BW		 12937}
12938
12939static void
7aa09196 12940Opcode_un_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12941{
7aa09196 12942 slotbuf[0] = 0x1b0000;
43cd72b9
BW		 12943}
12944
12945static void
7aa09196 12946Opcode_oeq_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12947{
7aa09196 12948 slotbuf[0] = 0x2b0000;
43cd72b9
BW		 12949}
12950
12951static void
7aa09196 12952Opcode_ueq_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12953{
7aa09196 12954 slotbuf[0] = 0x3b0000;
43cd72b9
BW		 12955}
12956
12957static void
7aa09196 12958Opcode_olt_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12959{
7aa09196 12960 slotbuf[0] = 0x4b0000;
43cd72b9
BW		 12961}
12962
12963static void
7aa09196 12964Opcode_ult_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12965{
7aa09196 12966 slotbuf[0] = 0x5b0000;
43cd72b9
BW		 12967}
12968
12969static void
7aa09196 12970Opcode_ole_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 12971{
7aa09196 12972 slotbuf[0] = 0x6b0000;
43cd72b9
BW		 12973}
12974
33430bd0 12975static void
7aa09196 12976Opcode_ule_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12977{
7aa09196 12978 slotbuf[0] = 0x7b0000;
33430bd0
BW		 12979}
12980
12981static void
7aa09196 12982Opcode_float_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12983{
7aa09196 12984 slotbuf[0] = 0xca0000;
33430bd0
BW		 12985}
12986
12987static void
7aa09196 12988Opcode_ufloat_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12989{
7aa09196 12990 slotbuf[0] = 0xda0000;
33430bd0
BW		 12991}
12992
12993static void
7aa09196 12994Opcode_round_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 12995{
7aa09196 12996 slotbuf[0] = 0x8a0000;
33430bd0
BW		 12997}
12998
12999static void
7aa09196 13000Opcode_ceil_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
33430bd0 13001{
7aa09196 13002 slotbuf[0] = 0xba0000;
33430bd0
BW		 13003}
13004
43cd72b9 13005static void
7aa09196 13006Opcode_floor_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 13007{
7aa09196 13008 slotbuf[0] = 0xaa0000;
43cd72b9
BW		 13009}
13010
13011static void
7aa09196 13012Opcode_trunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 13013{
7aa09196 13014 slotbuf[0] = 0x9a0000;
43cd72b9
BW		 13015}
13016
13017static void
7aa09196 13018Opcode_utrunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 13019{
7aa09196 13020 slotbuf[0] = 0xea0000;
43cd72b9
BW		 13021}
13022
13023static void
7aa09196 13024Opcode_rfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 13025{
7aa09196 13026 slotbuf[0] = 0xfa0040;
43cd72b9
BW		 13027}
13028
13029static void
7aa09196 13030Opcode_wfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 13031{
7aa09196 13032 slotbuf[0] = 0xfa0050;
43cd72b9
BW		 13033}
13034
13035static void
7aa09196 13036Opcode_lsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 13037{
7aa09196 13038 slotbuf[0] = 0x3;
43cd72b9
BW		 13039}
13040
13041static void
7aa09196 13042Opcode_lsiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 13043{
7aa09196 13044 slotbuf[0] = 0x8003;
43cd72b9
BW		 13045}
13046
13047static void
7aa09196 13048Opcode_lsx_Slot_inst_encode (xtensa_insnbuf slotbuf)
43cd72b9 13049{
7aa09196 13050 slotbuf[0] = 0x80000;
43cd72b9
BW		 13051}
13052
13053static void
7aa09196 13054Opcode_lsxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 13055{
7aa09196 13056 slotbuf[0] = 0x180000;
e0001a05
NC		 13057}
13058
43cd72b9 13059static void
7aa09196 13060Opcode_ssi_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 13061{
7aa09196 13062 slotbuf[0] = 0x4003;
e0001a05
NC		 13063}
13064
43cd72b9 13065static void
7aa09196 13066Opcode_ssiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 13067{
7aa09196 13068 slotbuf[0] = 0xc003;
e0001a05
NC		 13069}
13070
43cd72b9 13071static void
7aa09196 13072Opcode_ssx_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 13073{
7aa09196 13074 slotbuf[0] = 0x480000;
e0001a05
NC		 13075}
13076
43cd72b9 13077static void
7aa09196 13078Opcode_ssxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
e0001a05 13079{
7aa09196 13080 slotbuf[0] = 0x580000;
e0001a05
NC		 13081}
13082
43cd72b9 13083static void
7aa09196 13084Opcode_beqz_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
e0001a05 13085{
7aa09196
SA		 13086 slotbuf[0] = 0xa8000000;
13087 slotbuf[1] = 0;
e0001a05
NC		 13088}
13089
43cd72b9 13090static void
7aa09196 13091Opcode_bnez_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
e0001a05 13092{
7aa09196
SA		 13093 slotbuf[0] = 0xc0000000;
13094 slotbuf[1] = 0;
e0001a05
NC		 13095}
13096
43cd72b9 13097static void
7aa09196 13098Opcode_bgez_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
e0001a05 13099{
7aa09196
SA		 13100 slotbuf[0] = 0xb0000000;
13101 slotbuf[1] = 0;
e0001a05
NC		 13102}
13103
43cd72b9 13104static void
7aa09196 13105Opcode_bltz_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
e0001a05 13106{
7aa09196
SA		 13107 slotbuf[0] = 0xb8000000;
13108 slotbuf[1] = 0;
e0001a05
NC		 13109}
13110
43cd72b9 13111static void
7aa09196 13112Opcode_beqi_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
e0001a05 13113{
7aa09196
SA		 13114 slotbuf[0] = 0x40000000;
13115 slotbuf[1] = 0;
e0001a05
NC		 13116}
13117
43cd72b9 13118static void
7aa09196 13119Opcode_bnei_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
e0001a05 13120{
7aa09196
SA		 13121 slotbuf[0] = 0x98000000;
13122 slotbuf[1] = 0;
e0001a05
NC		 13123}
13124
43cd72b9 13125static void
7aa09196 13126Opcode_bgei_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
e0001a05 13127{
7aa09196
SA		 13128 slotbuf[0] = 0x50000000;
13129 slotbuf[1] = 0;
e0001a05
NC		 13130}
13131
43cd72b9 13132static void
7aa09196 13133Opcode_blti_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
e0001a05 13134{
7aa09196
SA		 13135 slotbuf[0] = 0x70000000;
13136 slotbuf[1] = 0;
e0001a05
NC		 13137}
13138
43cd72b9 13139static void
7aa09196 13140Opcode_bgeui_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
e0001a05 13141{
7aa09196
SA		 13142 slotbuf[0] = 0x60000000;
13143 slotbuf[1] = 0;
e0001a05
NC		 13144}
13145
43cd72b9 13146static void
7aa09196 13147Opcode_bltui_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
e0001a05 13148{
7aa09196
SA		 13149 slotbuf[0] = 0x80000000;
13150 slotbuf[1] = 0;
e0001a05
NC		 13151}
13152
43cd72b9 13153static void
7aa09196 13154Opcode_bbci_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
e0001a05 13155{
7aa09196
SA		 13156 slotbuf[0] = 0x8000000;
13157 slotbuf[1] = 0;
e0001a05
NC		 13158}
13159
43cd72b9 13160static void
7aa09196 13161Opcode_bbsi_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
e0001a05 13162{
7aa09196
SA		 13163 slotbuf[0] = 0x10000000;
13164 slotbuf[1] = 0;
e0001a05
NC		 13165}
13166
43cd72b9 13167static void
7aa09196 13168Opcode_beq_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
e0001a05 13169{
7aa09196
SA		 13170 slotbuf[0] = 0x38000000;
13171 slotbuf[1] = 0;
e0001a05
NC		 13172}
13173
43cd72b9 13174static void
7aa09196 13175Opcode_bne_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
e0001a05 13176{
7aa09196
SA		 13177 slotbuf[0] = 0x90000000;
13178 slotbuf[1] = 0;
e0001a05
NC		 13179}
13180
43cd72b9 13181static void
7aa09196 13182Opcode_bge_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
e0001a05 13183{
7aa09196
SA		 13184 slotbuf[0] = 0x48000000;
13185 slotbuf[1] = 0;
e0001a05
NC		 13186}
13187
43cd72b9 13188static void
7aa09196 13189Opcode_blt_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
e0001a05 13190{
7aa09196
SA		 13191 slotbuf[0] = 0x68000000;
13192 slotbuf[1] = 0;
e0001a05
NC		 13193}
13194
43cd72b9 13195static void
7aa09196 13196Opcode_bgeu_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
e0001a05 13197{
7aa09196
SA		 13198 slotbuf[0] = 0x58000000;
13199 slotbuf[1] = 0;
e0001a05
NC		 13200}
13201
43cd72b9 13202static void
7aa09196 13203Opcode_bltu_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
e0001a05 13204{
7aa09196
SA		 13205 slotbuf[0] = 0x78000000;
13206 slotbuf[1] = 0;
e0001a05
NC		 13207}
13208
43cd72b9 13209static void
7aa09196 13210Opcode_bany_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
e0001a05 13211{
7aa09196
SA		 13212 slotbuf[0] = 0x20000000;
13213 slotbuf[1] = 0;
e0001a05
NC		 13214}
13215
43cd72b9 13216static void
7aa09196 13217Opcode_bnone_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
e0001a05 13218{
7aa09196
SA		 13219 slotbuf[0] = 0xa0000000;
13220 slotbuf[1] = 0;
e0001a05
NC		 13221}
13222
43cd72b9 13223static void
7aa09196 13224Opcode_ball_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
e0001a05 13225{
7aa09196
SA		 13226 slotbuf[0] = 0x18000000;
13227 slotbuf[1] = 0;
e0001a05
NC		 13228}
13229
43cd72b9 13230static void
7aa09196 13231Opcode_bnall_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
e0001a05 13232{
7aa09196
SA		 13233 slotbuf[0] = 0x88000000;
13234 slotbuf[1] = 0;
e0001a05
NC		 13235}
13236
43cd72b9 13237static void
7aa09196 13238Opcode_bbc_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
e0001a05 13239{
7aa09196
SA		 13240 slotbuf[0] = 0x28000000;
13241 slotbuf[1] = 0;
e0001a05
NC		 13242}
13243
43cd72b9 13244static void
7aa09196 13245Opcode_bbs_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
e0001a05 13246{
7aa09196
SA		 13247 slotbuf[0] = 0x30000000;
13248 slotbuf[1] = 0;
e0001a05
NC		 13249}
13250
7aa09196
SA		 13251xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
13252 Opcode_excw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13253};
13254
13255xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
13256 Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13257};
13258
13259xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
13260 Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13261};
13262
13263xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
13264 Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13265};
13266
13267xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
13268 Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13269};
13270
13271xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
13272 Opcode_call12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13273};
13274
13275xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
13276 Opcode_call8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13277};
13278
13279xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
13280 Opcode_call4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13281};
13282
13283xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
13284 Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13285};
13286
13287xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
13288 Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13289};
13290
13291xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
13292 Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13293};
13294
13295xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
13296 Opcode_entry_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13297};
13298
13299xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
13300 Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13301};
13302
13303xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
13304 Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13305};
13306
13307xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
13308 Opcode_retw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13309};
13310
13311xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
13312 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
13313};
13314
13315xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
13316 Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13317};
13318
13319xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
13320 Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13321};
13322
13323xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
13324 Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13325};
13326
13327xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
13328 Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13329};
13330
13331xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
13332 Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13333};
13334
13335xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
13336 Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13337};
13338
13339xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
13340 Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13341};
13342
13343xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
13344 Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13345};
13346
13347xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
13348 Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13349};
13350
13351xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
13352 Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13353};
13354
13355xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
13356 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0
13357};
13358
13359xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
13360 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0, 0, Opcode_addi_n_Slot_xt_flix64_slot2_encode, 0
13361};
13362
13363xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
13364 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
13365};
13366
13367xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
13368 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
13369};
13370
13371xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
13372 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
13373};
13374
13375xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
13376 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0
13377};
13378
13379xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
13380 0, 0, Opcode_mov_n_Slot_inst16b_encode, Opcode_mov_n_Slot_xt_flix64_slot0_encode, Opcode_mov_n_Slot_xt_flix64_slot0_encode, Opcode_mov_n_Slot_xt_flix64_slot1_encode, Opcode_mov_n_Slot_xt_flix64_slot2_encode, 0
13381};
13382
13383xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
13384 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0, 0, Opcode_movi_n_Slot_xt_flix64_slot2_encode, 0
13385};
13386
13387xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
13388 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
13389};
13390
13391xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
13392 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
13393};
13394
13395xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
13396 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0
13397};
13398
13399xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
13400 Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13401};
13402
13403xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
13404 Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13405};
13406
13407xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
13408 Opcode_addi_Slot_inst_encode, 0, 0, Opcode_addi_Slot_xt_flix64_slot0_encode, Opcode_addi_Slot_xt_flix64_slot0_encode, Opcode_addi_Slot_xt_flix64_slot1_encode, 0, 0
13409};
13410
13411xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
13412 Opcode_addmi_Slot_inst_encode, 0, 0, Opcode_addmi_Slot_xt_flix64_slot0_encode, Opcode_addmi_Slot_xt_flix64_slot0_encode, Opcode_addmi_Slot_xt_flix64_slot1_encode, 0, 0
13413};
13414
13415xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
13416 Opcode_add_Slot_inst_encode, 0, 0, Opcode_add_Slot_xt_flix64_slot0_encode, Opcode_add_Slot_xt_flix64_slot0_encode, Opcode_add_Slot_xt_flix64_slot1_encode, Opcode_add_Slot_xt_flix64_slot2_encode, 0
13417};
13418
13419xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
13420 Opcode_sub_Slot_inst_encode, 0, 0, Opcode_sub_Slot_xt_flix64_slot0_encode, Opcode_sub_Slot_xt_flix64_slot0_encode, Opcode_sub_Slot_xt_flix64_slot1_encode, Opcode_sub_Slot_xt_flix64_slot2_encode, 0
13421};
13422
13423xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
13424 Opcode_addx2_Slot_inst_encode, 0, 0, Opcode_addx2_Slot_xt_flix64_slot0_encode, Opcode_addx2_Slot_xt_flix64_slot0_encode, Opcode_addx2_Slot_xt_flix64_slot1_encode, Opcode_addx2_Slot_xt_flix64_slot2_encode, 0
13425};
13426
13427xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
13428 Opcode_addx4_Slot_inst_encode, 0, 0, Opcode_addx4_Slot_xt_flix64_slot0_encode, Opcode_addx4_Slot_xt_flix64_slot0_encode, Opcode_addx4_Slot_xt_flix64_slot1_encode, Opcode_addx4_Slot_xt_flix64_slot2_encode, 0
13429};
13430
13431xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
13432 Opcode_addx8_Slot_inst_encode, 0, 0, Opcode_addx8_Slot_xt_flix64_slot0_encode, Opcode_addx8_Slot_xt_flix64_slot0_encode, Opcode_addx8_Slot_xt_flix64_slot1_encode, 0, 0
13433};
13434
13435xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
13436 Opcode_subx2_Slot_inst_encode, 0, 0, Opcode_subx2_Slot_xt_flix64_slot0_encode, Opcode_subx2_Slot_xt_flix64_slot0_encode, 0, 0, 0
13437};
13438
13439xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
13440 Opcode_subx4_Slot_inst_encode, 0, 0, Opcode_subx4_Slot_xt_flix64_slot0_encode, Opcode_subx4_Slot_xt_flix64_slot0_encode, 0, 0, 0
13441};
13442
13443xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
13444 Opcode_subx8_Slot_inst_encode, 0, 0, Opcode_subx8_Slot_xt_flix64_slot0_encode, Opcode_subx8_Slot_xt_flix64_slot0_encode, 0, 0, 0
13445};
13446
13447xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
13448 Opcode_and_Slot_inst_encode, 0, 0, Opcode_and_Slot_xt_flix64_slot0_encode, Opcode_and_Slot_xt_flix64_slot0_encode, Opcode_and_Slot_xt_flix64_slot1_encode, Opcode_and_Slot_xt_flix64_slot2_encode, 0
13449};
13450
13451xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
13452 Opcode_or_Slot_inst_encode, 0, 0, Opcode_or_Slot_xt_flix64_slot0_encode, Opcode_or_Slot_xt_flix64_slot0_encode, Opcode_or_Slot_xt_flix64_slot1_encode, Opcode_or_Slot_xt_flix64_slot2_encode, 0
13453};
13454
13455xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
13456 Opcode_xor_Slot_inst_encode, 0, 0, Opcode_xor_Slot_xt_flix64_slot0_encode, Opcode_xor_Slot_xt_flix64_slot0_encode, Opcode_xor_Slot_xt_flix64_slot1_encode, Opcode_xor_Slot_xt_flix64_slot2_encode, 0
13457};
13458
13459xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
13460 Opcode_beqi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13461};
13462
13463xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
13464 Opcode_bnei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13465};
13466
13467xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
13468 Opcode_bgei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13469};
13470
13471xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
13472 Opcode_blti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13473};
13474
13475xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
13476 Opcode_bbci_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13477};
13478
13479xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
13480 Opcode_bbsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13481};
13482
13483xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
13484 Opcode_bgeui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13485};
13486
13487xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
13488 Opcode_bltui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13489};
13490
13491xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
13492 Opcode_beq_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13493};
13494
13495xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
13496 Opcode_bne_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13497};
13498
13499xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
13500 Opcode_bge_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13501};
13502
13503xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
13504 Opcode_blt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13505};
13506
13507xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
13508 Opcode_bgeu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13509};
13510
13511xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
13512 Opcode_bltu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13513};
13514
13515xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
13516 Opcode_bany_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13517};
13518
13519xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
13520 Opcode_bnone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13521};
13522
13523xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
13524 Opcode_ball_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13525};
13526
13527xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
13528 Opcode_bnall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13529};
13530
13531xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
13532 Opcode_bbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13533};
13534
13535xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
13536 Opcode_bbs_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13537};
13538
13539xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
13540 Opcode_beqz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13541};
13542
13543xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
13544 Opcode_bnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13545};
13546
13547xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
13548 Opcode_bgez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13549};
13550
13551xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
13552 Opcode_bltz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13553};
13554
13555xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
13556 Opcode_call0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13557};
13558
13559xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
13560 Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13561};
13562
13563xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
13564 Opcode_extui_Slot_inst_encode, 0, 0, Opcode_extui_Slot_xt_flix64_slot0_encode, Opcode_extui_Slot_xt_flix64_slot0_encode, Opcode_extui_Slot_xt_flix64_slot1_encode, 0, 0
13565};
13566
13567xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
13568 Opcode_ill_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13569};
13570
13571xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
13572 Opcode_j_Slot_inst_encode, 0, 0, 0, 0, Opcode_j_Slot_xt_flix64_slot1_encode, 0, 0
13573};
13574
13575xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
13576 Opcode_jx_Slot_inst_encode, 0, 0, 0, 0, Opcode_jx_Slot_xt_flix64_slot1_encode, 0, 0
13577};
13578
13579xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
13580 Opcode_l16ui_Slot_inst_encode, 0, 0, Opcode_l16ui_Slot_xt_flix64_slot0_encode, Opcode_l16ui_Slot_xt_flix64_slot0_encode, 0, 0, 0
13581};
e0001a05 13582
7aa09196
SA		 13583xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
13584 Opcode_l16si_Slot_inst_encode, 0, 0, Opcode_l16si_Slot_xt_flix64_slot0_encode, Opcode_l16si_Slot_xt_flix64_slot0_encode, 0, 0, 0
13585};
e0001a05 13586
7aa09196
SA		 13587xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
13588 Opcode_l32i_Slot_inst_encode, 0, 0, Opcode_l32i_Slot_xt_flix64_slot0_encode, Opcode_l32i_Slot_xt_flix64_slot0_encode, 0, 0, 0
13589};
e0001a05 13590
7aa09196
SA		 13591xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
13592 Opcode_l32r_Slot_inst_encode, 0, 0, Opcode_l32r_Slot_xt_flix64_slot0_encode, Opcode_l32r_Slot_xt_flix64_slot0_encode, 0, 0, 0
13593};
e0001a05 13594
7aa09196
SA		 13595xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
13596 Opcode_l8ui_Slot_inst_encode, 0, 0, Opcode_l8ui_Slot_xt_flix64_slot0_encode, Opcode_l8ui_Slot_xt_flix64_slot0_encode, 0, 0, 0
13597};
e0001a05 13598
7aa09196
SA		 13599xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
13600 Opcode_loop_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13601};
e0001a05 13602
7aa09196
SA		 13603xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
13604 Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13605};
e0001a05 13606
7aa09196
SA		 13607xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
13608 Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13609};
e0001a05 13610
7aa09196
SA		 13611xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
13612 Opcode_movi_Slot_inst_encode, 0, 0, Opcode_movi_Slot_xt_flix64_slot0_encode, Opcode_movi_Slot_xt_flix64_slot0_encode, Opcode_movi_Slot_xt_flix64_slot1_encode, 0, 0
13613};
33430bd0 13614
7aa09196
SA		 13615xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
13616 Opcode_moveqz_Slot_inst_encode, 0, 0, Opcode_moveqz_Slot_xt_flix64_slot0_encode, Opcode_moveqz_Slot_xt_flix64_slot0_encode, Opcode_moveqz_Slot_xt_flix64_slot1_encode, 0, 0
13617};
e0001a05 13618
7aa09196
SA		 13619xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
13620 Opcode_movnez_Slot_inst_encode, 0, 0, Opcode_movnez_Slot_xt_flix64_slot0_encode, Opcode_movnez_Slot_xt_flix64_slot0_encode, Opcode_movnez_Slot_xt_flix64_slot1_encode, 0, 0
13621};
e0001a05 13622
7aa09196
SA		 13623xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
13624 Opcode_movltz_Slot_inst_encode, 0, 0, Opcode_movltz_Slot_xt_flix64_slot0_encode, Opcode_movltz_Slot_xt_flix64_slot0_encode, Opcode_movltz_Slot_xt_flix64_slot1_encode, 0, 0
13625};
e0001a05 13626
7aa09196
SA		 13627xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
13628 Opcode_movgez_Slot_inst_encode, 0, 0, Opcode_movgez_Slot_xt_flix64_slot0_encode, Opcode_movgez_Slot_xt_flix64_slot0_encode, Opcode_movgez_Slot_xt_flix64_slot1_encode, 0, 0
13629};
e0001a05 13630
7aa09196
SA		 13631xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
13632 Opcode_neg_Slot_inst_encode, 0, 0, Opcode_neg_Slot_xt_flix64_slot0_encode, Opcode_neg_Slot_xt_flix64_slot0_encode, Opcode_neg_Slot_xt_flix64_slot1_encode, Opcode_neg_Slot_xt_flix64_slot2_encode, 0
13633};
e0001a05 13634
7aa09196
SA		 13635xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
13636 Opcode_abs_Slot_inst_encode, 0, 0, Opcode_abs_Slot_xt_flix64_slot0_encode, Opcode_abs_Slot_xt_flix64_slot0_encode, 0, Opcode_abs_Slot_xt_flix64_slot2_encode, 0
13637};
e0001a05 13638
7aa09196
SA		 13639xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
13640 Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_xt_flix64_slot0_encode, Opcode_nop_Slot_xt_flix64_slot0_encode, Opcode_nop_Slot_xt_flix64_slot1_encode, Opcode_nop_Slot_xt_flix64_slot2_encode, Opcode_nop_Slot_xt_flix64_slot3_encode
13641};
e0001a05 13642
7aa09196
SA		 13643xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
13644 Opcode_ret_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13645};
e0001a05 13646
7aa09196
SA		 13647xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
13648 Opcode_s16i_Slot_inst_encode, 0, 0, Opcode_s16i_Slot_xt_flix64_slot0_encode, Opcode_s16i_Slot_xt_flix64_slot0_encode, 0, 0, 0
13649};
e0001a05 13650
7aa09196
SA		 13651xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
13652 Opcode_s32i_Slot_inst_encode, 0, 0, Opcode_s32i_Slot_xt_flix64_slot0_encode, Opcode_s32i_Slot_xt_flix64_slot0_encode, 0, 0, 0
13653};
e0001a05 13654
7aa09196
SA		 13655xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
13656 Opcode_s8i_Slot_inst_encode, 0, 0, Opcode_s8i_Slot_xt_flix64_slot0_encode, Opcode_s8i_Slot_xt_flix64_slot0_encode, 0, 0, 0
13657};
e0001a05 13658
7aa09196
SA		 13659xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
13660 Opcode_ssr_Slot_inst_encode, 0, 0, Opcode_ssr_Slot_xt_flix64_slot0_encode, Opcode_ssr_Slot_xt_flix64_slot0_encode, 0, 0, 0
13661};
e0001a05 13662
7aa09196
SA		 13663xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
13664 Opcode_ssl_Slot_inst_encode, 0, 0, Opcode_ssl_Slot_xt_flix64_slot0_encode, Opcode_ssl_Slot_xt_flix64_slot0_encode, Opcode_ssl_Slot_xt_flix64_slot1_encode, 0, 0
13665};
e0001a05 13666
7aa09196
SA		 13667xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
13668 Opcode_ssa8l_Slot_inst_encode, 0, 0, Opcode_ssa8l_Slot_xt_flix64_slot0_encode, Opcode_ssa8l_Slot_xt_flix64_slot0_encode, 0, 0, 0
13669};
e0001a05 13670
7aa09196
SA		 13671xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
13672 Opcode_ssa8b_Slot_inst_encode, 0, 0, Opcode_ssa8b_Slot_xt_flix64_slot0_encode, Opcode_ssa8b_Slot_xt_flix64_slot0_encode, 0, 0, 0
13673};
33430bd0 13674
7aa09196
SA		 13675xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
13676 Opcode_ssai_Slot_inst_encode, 0, 0, Opcode_ssai_Slot_xt_flix64_slot0_encode, Opcode_ssai_Slot_xt_flix64_slot0_encode, 0, 0, 0
13677};
33430bd0 13678
7aa09196
SA		 13679xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
13680 Opcode_sll_Slot_inst_encode, 0, 0, Opcode_sll_Slot_xt_flix64_slot0_encode, Opcode_sll_Slot_xt_flix64_slot0_encode, Opcode_sll_Slot_xt_flix64_slot1_encode, 0, 0
13681};
33430bd0 13682
7aa09196
SA		 13683xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
13684 Opcode_src_Slot_inst_encode, 0, 0, Opcode_src_Slot_xt_flix64_slot0_encode, Opcode_src_Slot_xt_flix64_slot0_encode, Opcode_src_Slot_xt_flix64_slot1_encode, 0, 0
13685};
e0001a05 13686
7aa09196
SA		 13687xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
13688 Opcode_srl_Slot_inst_encode, 0, 0, Opcode_srl_Slot_xt_flix64_slot0_encode, Opcode_srl_Slot_xt_flix64_slot0_encode, Opcode_srl_Slot_xt_flix64_slot1_encode, Opcode_srl_Slot_xt_flix64_slot2_encode, 0
13689};
e0001a05 13690
7aa09196
SA		 13691xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
13692 Opcode_sra_Slot_inst_encode, 0, 0, Opcode_sra_Slot_xt_flix64_slot0_encode, Opcode_sra_Slot_xt_flix64_slot0_encode, Opcode_sra_Slot_xt_flix64_slot1_encode, Opcode_sra_Slot_xt_flix64_slot2_encode, 0
13693};
e0001a05 13694
7aa09196
SA		 13695xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
13696 Opcode_slli_Slot_inst_encode, 0, 0, Opcode_slli_Slot_xt_flix64_slot0_encode, Opcode_slli_Slot_xt_flix64_slot0_encode, Opcode_slli_Slot_xt_flix64_slot1_encode, 0, 0
13697};
e0001a05 13698
7aa09196
SA		 13699xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
13700 Opcode_srai_Slot_inst_encode, 0, 0, Opcode_srai_Slot_xt_flix64_slot0_encode, Opcode_srai_Slot_xt_flix64_slot0_encode, Opcode_srai_Slot_xt_flix64_slot1_encode, Opcode_srai_Slot_xt_flix64_slot2_encode, 0
13701};
e0001a05 13702
7aa09196
SA		 13703xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
13704 Opcode_srli_Slot_inst_encode, 0, 0, Opcode_srli_Slot_xt_flix64_slot0_encode, Opcode_srli_Slot_xt_flix64_slot0_encode, Opcode_srli_Slot_xt_flix64_slot1_encode, Opcode_srli_Slot_xt_flix64_slot2_encode, 0
13705};
e0001a05 13706
7aa09196
SA		 13707xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
13708 Opcode_memw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13709};
e0001a05 13710
7aa09196
SA		 13711xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
13712 Opcode_extw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13713};
e0001a05 13714
7aa09196
SA		 13715xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
13716 Opcode_isync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13717};
e0001a05 13718
7aa09196
SA		 13719xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
13720 Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13721};
e0001a05 13722
7aa09196
SA		 13723xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
13724 Opcode_esync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13725};
e0001a05 13726
7aa09196
SA		 13727xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
13728 Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13729};
e0001a05 13730
7aa09196
SA		 13731xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
13732 Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13733};
e0001a05 13734
7aa09196
SA		 13735xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
13736 Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13737};
e0001a05 13738
7aa09196
SA		 13739xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
13740 Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13741};
e0001a05 13742
7aa09196
SA		 13743xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
13744 Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13745};
13746
13747xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
13748 Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13749};
33430bd0 13750
7aa09196
SA		 13751xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
13752 Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13753};
33430bd0 13754
7aa09196
SA		 13755xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
13756 Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13757};
33430bd0 13758
7aa09196
SA		 13759xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
13760 Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13761};
e0001a05 13762
7aa09196
SA		 13763xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
13764 Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13765};
e0001a05 13766
7aa09196
SA		 13767xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
13768 Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13769};
074f5109 13770
7aa09196
SA		 13771xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
13772 Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13773};
074f5109 13774
7aa09196
SA		 13775xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
13776 Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13777};
074f5109 13778
7aa09196
SA		 13779xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
13780 Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13781};
074f5109 13782
7aa09196
SA		 13783xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
13784 Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13785};
074f5109 13786
7aa09196
SA		 13787xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
13788 Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13789};
074f5109 13790
7aa09196
SA		 13791xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
13792 Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13793};
074f5109 13794
7aa09196
SA		 13795xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
13796 Opcode_rsr_176_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13797};
074f5109 13798
7aa09196
SA		 13799xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
13800 Opcode_rsr_208_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13801};
074f5109 13802
7aa09196
SA		 13803xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
13804 Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13805};
074f5109 13806
7aa09196
SA		 13807xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
13808 Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13809};
074f5109 13810
7aa09196
SA		 13811xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
13812 Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13813};
074f5109 13814
7aa09196
SA		 13815xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
13816 Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13817};
e0001a05 13818
7aa09196
SA		 13819xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
13820 Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13821};
e0001a05 13822
7aa09196
SA		 13823xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
13824 Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13825};
e0001a05 13826
7aa09196
SA		 13827xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
13828 Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13829};
e0001a05 13830
7aa09196
SA		 13831xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
13832 Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13833};
33430bd0 13834
7aa09196
SA		 13835xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
13836 Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13837};
33430bd0 13838
7aa09196
SA		 13839xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
13840 Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13841};
33430bd0 13842
7aa09196
SA		 13843xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
13844 Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13845};
33430bd0 13846
7aa09196
SA		 13847xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
13848 Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13849};
33430bd0 13850
7aa09196
SA		 13851xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
13852 Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13853};
33430bd0 13854
7aa09196
SA		 13855xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
13856 Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13857};
33430bd0 13858
7aa09196
SA		 13859xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
13860 Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13861};
33430bd0 13862
7aa09196
SA		 13863xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
13864 Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13865};
33430bd0 13866
7aa09196
SA		 13867xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
13868 Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13869};
33430bd0 13870
7aa09196
SA		 13871xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
13872 Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13873};
33430bd0 13874
7aa09196
SA		 13875xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
13876 Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13877};
33430bd0 13878
7aa09196
SA		 13879xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
13880 Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13881};
33430bd0 13882
7aa09196
SA		 13883xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
13884 Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13885};
33430bd0 13886
7aa09196
SA		 13887xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
13888 Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13889};
33430bd0 13890
7aa09196
SA		 13891xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
13892 Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13893};
33430bd0 13894
7aa09196
SA		 13895xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
13896 Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13897};
33430bd0 13898
7aa09196
SA		 13899xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
13900 Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13901};
33430bd0 13902
7aa09196
SA		 13903xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
13904 Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13905};
33430bd0 13906
7aa09196
SA		 13907xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
13908 Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13909};
33430bd0 13910
7aa09196
SA		 13911xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
13912 Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13913};
e0001a05 13914
7aa09196
SA		 13915xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
13916 Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13917};
13918
13919xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
13920 Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13921};
e0001a05 13922
7aa09196
SA		 13923xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
13924 Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13925};
e0001a05 13926
7aa09196
SA		 13927xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
13928 Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13929};
e0001a05 13930
7aa09196
SA		 13931xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
13932 Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13933};
e0001a05 13934
7aa09196
SA		 13935xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
13936 Opcode_rsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13937};
e0001a05 13938
7aa09196
SA		 13939xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
13940 Opcode_wsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13941};
074f5109 13942
7aa09196
SA		 13943xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
13944 Opcode_xsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13945};
074f5109 13946
7aa09196
SA		 13947xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
13948 Opcode_rsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13949};
074f5109 13950
7aa09196
SA		 13951xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
13952 Opcode_wsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13953};
43cd72b9 13954
7aa09196
SA		 13955xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
13956 Opcode_xsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
13957};
43cd72b9 13958
7aa09196
SA		 13959xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
13960 Opcode_rsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 13961};
13962
7aa09196
SA		 13963xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
13964 Opcode_wsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 13965};
13966
7aa09196
SA		 13967xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
13968 Opcode_xsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 13969};
13970
7aa09196
SA		 13971xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
13972 Opcode_rsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 13973};
13974
7aa09196
SA		 13975xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
13976 Opcode_wsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 13977};
13978
7aa09196
SA		 13979xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
13980 Opcode_xsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 13981};
13982
7aa09196
SA		 13983xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
13984 Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 13985};
13986
7aa09196
SA		 13987xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
13988 Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 13989};
13990
7aa09196
SA		 13991xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
13992 Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 13993};
13994
7aa09196
SA		 13995xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
13996 Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 13997};
13998
7aa09196
SA		 13999xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
14000 Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14001};
14002
7aa09196
SA		 14003xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
14004 Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14005};
14006
7aa09196
SA		 14007xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
14008 Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14009};
14010
7aa09196
SA		 14011xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
14012 Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14013};
14014
7aa09196
SA		 14015xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
14016 Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14017};
14018
7aa09196
SA		 14019xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
14020 Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14021};
14022
7aa09196
SA		 14023xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
14024 Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14025};
14026
7aa09196
SA		 14027xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
14028 Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14029};
14030
7aa09196
SA		 14031xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
14032 Opcode_rsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14033};
14034
7aa09196
SA		 14035xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
14036 Opcode_wsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14037};
14038
7aa09196
SA		 14039xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
14040 Opcode_xsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14041};
14042
7aa09196
SA		 14043xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
14044 Opcode_rsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14045};
14046
7aa09196
SA		 14047xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
14048 Opcode_wsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14049};
14050
7aa09196
SA		 14051xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
14052 Opcode_xsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14053};
14054
7aa09196
SA		 14055xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
14056 Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14057};
14058
7aa09196
SA		 14059xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
14060 Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14061};
14062
7aa09196
SA		 14063xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
14064 Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14065};
14066
7aa09196
SA		 14067xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
14068 Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14069};
14070
7aa09196
SA		 14071xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
14072 Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14073};
14074
7aa09196
SA		 14075xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
14076 Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14077};
14078
7aa09196
SA		 14079xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
14080 Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14081};
14082
7aa09196
SA		 14083xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
14084 Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14085};
14086
7aa09196
SA		 14087xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
14088 Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14089};
14090
7aa09196
SA		 14091xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
14092 Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14093};
14094
7aa09196
SA		 14095xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
14096 Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14097};
14098
7aa09196
SA		 14099xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
14100 Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14101};
14102
7aa09196
SA		 14103xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
14104 Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14105};
14106
7aa09196
SA		 14107xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
14108 Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14109};
14110
7aa09196
SA		 14111xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
14112 Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14113};
14114
7aa09196
SA		 14115xtensa_opcode_encode_fn Opcode_rsr_misc2_encode_fns[] = {
14116 Opcode_rsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14117};
14118
7aa09196
SA		 14119xtensa_opcode_encode_fn Opcode_wsr_misc2_encode_fns[] = {
14120 Opcode_wsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14121};
14122
7aa09196
SA		 14123xtensa_opcode_encode_fn Opcode_xsr_misc2_encode_fns[] = {
14124 Opcode_xsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14125};
14126
7aa09196
SA		 14127xtensa_opcode_encode_fn Opcode_rsr_misc3_encode_fns[] = {
14128 Opcode_rsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14129};
14130
7aa09196
SA		 14131xtensa_opcode_encode_fn Opcode_wsr_misc3_encode_fns[] = {
14132 Opcode_wsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14133};
14134
7aa09196
SA		 14135xtensa_opcode_encode_fn Opcode_xsr_misc3_encode_fns[] = {
14136 Opcode_xsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14137};
14138
7aa09196
SA		 14139xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
14140 Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14141};
14142
7aa09196
SA		 14143xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
14144 Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14145};
14146
7aa09196
SA		 14147xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
14148 Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14149};
14150
7aa09196
SA		 14151xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
14152 Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14153};
14154
7aa09196
SA		 14155xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = {
14156 Opcode_mul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14157};
14158
7aa09196
SA		 14159xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = {
14160 Opcode_mul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14161};
14162
7aa09196
SA		 14163xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = {
14164 Opcode_mul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14165};
14166
7aa09196
SA		 14167xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = {
14168 Opcode_mul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14169};
14170
7aa09196
SA		 14171xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = {
14172 Opcode_umul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14173};
14174
7aa09196
SA		 14175xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = {
14176 Opcode_umul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14177};
14178
7aa09196
SA		 14179xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = {
14180 Opcode_umul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14181};
14182
7aa09196
SA		 14183xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = {
14184 Opcode_umul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14185};
14186
7aa09196
SA		 14187xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = {
14188 Opcode_mul_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14189};
14190
7aa09196
SA		 14191xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = {
14192 Opcode_mul_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14193};
14194
7aa09196
SA		 14195xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = {
14196 Opcode_mul_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14197};
14198
7aa09196
SA		 14199xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = {
14200 Opcode_mul_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14201};
14202
7aa09196
SA		 14203xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = {
14204 Opcode_mul_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14205};
14206
7aa09196
SA		 14207xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = {
14208 Opcode_mul_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14209};
14210
7aa09196
SA		 14211xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = {
14212 Opcode_mul_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14213};
e0001a05 14214
7aa09196
SA		 14215xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = {
14216 Opcode_mul_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14217};
e0001a05 14218
7aa09196
SA		 14219xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = {
14220 Opcode_mul_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14221};
e0001a05 14222
7aa09196
SA		 14223xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = {
14224 Opcode_mul_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14225};
e0001a05 14226
7aa09196
SA		 14227xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = {
14228 Opcode_mul_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14229};
e0001a05 14230
7aa09196
SA		 14231xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = {
14232 Opcode_mul_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14233};
e0001a05 14234
7aa09196
SA		 14235xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = {
14236 Opcode_mula_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14237};
e0001a05 14238
7aa09196
SA		 14239xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = {
14240 Opcode_mula_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14241};
e0001a05 14242
7aa09196
SA		 14243xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = {
14244 Opcode_mula_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14245};
e0001a05 14246
7aa09196
SA		 14247xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = {
14248 Opcode_mula_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14249};
e0001a05 14250
7aa09196
SA		 14251xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = {
14252 Opcode_muls_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14253};
e0001a05 14254
7aa09196
SA		 14255xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = {
14256 Opcode_muls_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14257};
e0001a05 14258
7aa09196
SA		 14259xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = {
14260 Opcode_muls_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14261};
e0001a05 14262
7aa09196
SA		 14263xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = {
14264 Opcode_muls_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14265};
e0001a05 14266
7aa09196
SA		 14267xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = {
14268 Opcode_mula_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14269};
e0001a05 14270
7aa09196
SA		 14271xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = {
14272 Opcode_mula_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14273};
e0001a05 14274
7aa09196
SA		 14275xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = {
14276 Opcode_mula_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14277};
e0001a05 14278
7aa09196
SA		 14279xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = {
14280 Opcode_mula_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14281};
e0001a05 14282
7aa09196
SA		 14283xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = {
14284 Opcode_muls_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14285};
e0001a05 14286
7aa09196
SA		 14287xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = {
14288 Opcode_muls_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14289};
e0001a05 14290
7aa09196
SA		 14291xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = {
14292 Opcode_muls_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14293};
e0001a05 14294
7aa09196
SA		 14295xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = {
14296 Opcode_muls_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14297};
e0001a05 14298
7aa09196
SA		 14299xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = {
14300 Opcode_mula_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14301};
e0001a05 14302
7aa09196
SA		 14303xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = {
14304 Opcode_mula_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14305};
e0001a05 14306
7aa09196
SA		 14307xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = {
14308 Opcode_mula_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14309};
e0001a05 14310
7aa09196
SA		 14311xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = {
14312 Opcode_mula_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14313};
e0001a05 14314
7aa09196
SA		 14315xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = {
14316 Opcode_muls_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14317};
e0001a05 14318
7aa09196
SA		 14319xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = {
14320 Opcode_muls_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14321};
e0001a05 14322
7aa09196
SA		 14323xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = {
14324 Opcode_muls_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14325};
e0001a05 14326
7aa09196
SA		 14327xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = {
14328 Opcode_muls_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14329};
e0001a05 14330
7aa09196
SA		 14331xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = {
14332 Opcode_mula_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14333};
e0001a05 14334
7aa09196
SA		 14335xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = {
14336 Opcode_mula_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14337};
e0001a05 14338
7aa09196
SA		 14339xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = {
14340 Opcode_mula_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14341};
e0001a05 14342
7aa09196
SA		 14343xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = {
14344 Opcode_mula_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14345};
e0001a05 14346
7aa09196
SA		 14347xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = {
14348 Opcode_muls_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14349};
e0001a05 14350
7aa09196
SA		 14351xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = {
14352 Opcode_muls_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14353};
e0001a05 14354
7aa09196
SA		 14355xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = {
14356 Opcode_muls_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14357};
e0001a05 14358
7aa09196
SA		 14359xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = {
14360 Opcode_muls_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14361};
e0001a05 14362
7aa09196
SA		 14363xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = {
14364 Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14365};
e0001a05 14366
7aa09196
SA		 14367xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = {
14368 Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14369};
e0001a05 14370
7aa09196
SA		 14371xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = {
14372 Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14373};
e0001a05 14374
7aa09196
SA		 14375xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = {
14376 Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14377};
e0001a05 14378
7aa09196
SA		 14379xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = {
14380 Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14381};
e0001a05 14382
7aa09196
SA		 14383xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = {
14384 Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14385};
e0001a05 14386
7aa09196
SA		 14387xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = {
14388 Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14389};
e0001a05 14390
7aa09196
SA		 14391xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = {
14392 Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14393};
e0001a05 14394
7aa09196
SA		 14395xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = {
14396 Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14397};
e0001a05 14398
7aa09196
SA		 14399xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = {
14400 Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14401};
e0001a05 14402
7aa09196
SA		 14403xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = {
14404 Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14405};
e0001a05 14406
7aa09196
SA		 14407xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = {
14408 Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14409};
e0001a05 14410
7aa09196
SA		 14411xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = {
14412 Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14413};
e0001a05 14414
7aa09196
SA		 14415xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = {
14416 Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14417};
e0001a05 14418
7aa09196
SA		 14419xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = {
14420 Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14421};
e0001a05 14422
7aa09196
SA		 14423xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = {
14424 Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14425};
e0001a05 14426
7aa09196
SA		 14427xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = {
14428 Opcode_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14429};
e0001a05 14430
7aa09196
SA		 14431xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = {
14432 Opcode_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14433};
e0001a05 14434
7aa09196
SA		 14435xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
14436 Opcode_mul16u_Slot_inst_encode, 0, 0, Opcode_mul16u_Slot_xt_flix64_slot0_encode, Opcode_mul16u_Slot_xt_flix64_slot0_encode, Opcode_mul16u_Slot_xt_flix64_slot1_encode, 0, 0
43cd72b9 14437};
e0001a05 14438
7aa09196
SA		 14439xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
14440 Opcode_mul16s_Slot_inst_encode, 0, 0, Opcode_mul16s_Slot_xt_flix64_slot0_encode, Opcode_mul16s_Slot_xt_flix64_slot0_encode, Opcode_mul16s_Slot_xt_flix64_slot1_encode, 0, 0
43cd72b9 14441};
e0001a05 14442
7aa09196
SA		 14443xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = {
14444 Opcode_rsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14445};
e0001a05 14446
7aa09196
SA		 14447xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = {
14448 Opcode_wsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14449};
e0001a05 14450
7aa09196
SA		 14451xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = {
14452 Opcode_xsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14453};
e0001a05 14454
7aa09196
SA		 14455xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = {
14456 Opcode_rsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14457};
e0001a05 14458
7aa09196
SA		 14459xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = {
14460 Opcode_wsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14461};
e0001a05 14462
7aa09196
SA		 14463xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = {
14464 Opcode_xsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14465};
e0001a05 14466
7aa09196
SA		 14467xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = {
14468 Opcode_rsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14469};
e0001a05 14470
7aa09196
SA		 14471xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = {
14472 Opcode_wsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9 14473};
e0001a05 14474
7aa09196
SA		 14475xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = {
14476 Opcode_xsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14477};
14478
7aa09196
SA		 14479xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = {
14480 Opcode_rsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14481};
14482
7aa09196
SA		 14483xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = {
14484 Opcode_wsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14485};
14486
7aa09196
SA		 14487xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = {
14488 Opcode_xsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14489};
14490
7aa09196
SA		 14491xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = {
14492 Opcode_rsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14493};
14494
7aa09196
SA		 14495xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = {
14496 Opcode_wsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14497};
14498
7aa09196
SA		 14499xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = {
14500 Opcode_xsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14501};
14502
7aa09196
SA		 14503xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = {
14504 Opcode_rsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14505};
14506
7aa09196
SA		 14507xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = {
14508 Opcode_wsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14509};
14510
7aa09196
SA		 14511xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = {
14512 Opcode_xsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14513};
14514
7aa09196
SA		 14515xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
14516 Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14517};
14518
7aa09196
SA		 14519xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
14520 Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14521};
14522
7aa09196
SA		 14523xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
14524 Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14525};
14526
7aa09196
SA		 14527xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
14528 Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14529};
14530
7aa09196
SA		 14531xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
14532 Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14533};
14534
7aa09196
SA		 14535xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
14536 Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14537};
14538
7aa09196
SA		 14539xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
14540 Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14541};
14542
7aa09196
SA		 14543xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
14544 Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14545};
14546
7aa09196
SA		 14547xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
14548 Opcode_break_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14549};
14550
7aa09196
SA		 14551xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
14552 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
e0001a05
NC		 14553};
14554
7aa09196
SA		 14555xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
14556 Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14557};
14558
7aa09196
SA		 14559xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
14560 Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14561};
14562
7aa09196
SA		 14563xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
14564 Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14565};
14566
7aa09196
SA		 14567xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
14568 Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14569};
14570
7aa09196
SA		 14571xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
14572 Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14573};
14574
7aa09196
SA		 14575xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
14576 Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14577};
14578
7aa09196
SA		 14579xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
14580 Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14581};
14582
7aa09196
SA		 14583xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
14584 Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14585};
14586
7aa09196
SA		 14587xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
14588 Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14589};
14590
7aa09196
SA		 14591xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
14592 Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14593};
14594
7aa09196
SA		 14595xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
14596 Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14597};
14598
7aa09196
SA		 14599xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
14600 Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14601};
14602
7aa09196
SA		 14603xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
14604 Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14605};
14606
7aa09196
SA		 14607xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
14608 Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14609};
14610
7aa09196
SA		 14611xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
14612 Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14613};
14614
7aa09196
SA		 14615xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
14616 Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14617};
14618
7aa09196
SA		 14619xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
14620 Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14621};
14622
7aa09196
SA		 14623xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
14624 Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14625};
14626
7aa09196
SA		 14627xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
14628 Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14629};
14630
7aa09196
SA		 14631xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
14632 Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14633};
14634
7aa09196
SA		 14635xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
14636 Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14637};
14638
7aa09196
SA		 14639xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
14640 Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14641};
14642
7aa09196
SA		 14643xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
14644 Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14645};
14646
7aa09196
SA		 14647xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
14648 Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14649};
14650
7aa09196
SA		 14651xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
14652 Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14653};
14654
7aa09196
SA		 14655xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
14656 Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14657};
14658
7aa09196
SA		 14659xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
14660 Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14661};
14662
7aa09196
SA		 14663xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
14664 Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14665};
14666
7aa09196
SA		 14667xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
14668 Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14669};
14670
7aa09196
SA		 14671xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
14672 Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14673};
14674
7aa09196
SA		 14675xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
14676 Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14677};
14678
7aa09196
SA		 14679xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
14680 Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14681};
14682
7aa09196
SA		 14683xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
14684 Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14685};
14686
7aa09196
SA		 14687xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
14688 Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14689};
14690
7aa09196
SA		 14691xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
14692 Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14693};
14694
7aa09196
SA		 14695xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
14696 Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14697};
14698
7aa09196
SA		 14699xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = {
14700 Opcode_andb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14701};
14702
7aa09196
SA		 14703xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = {
14704 Opcode_andbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14705};
14706
7aa09196
SA		 14707xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = {
14708 Opcode_orb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14709};
14710
7aa09196
SA		 14711xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = {
14712 Opcode_orbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14713};
14714
7aa09196
SA		 14715xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = {
14716 Opcode_xorb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14717};
14718
7aa09196
SA		 14719xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = {
14720 Opcode_any4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14721};
14722
7aa09196
SA		 14723xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = {
14724 Opcode_all4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14725};
14726
7aa09196
SA		 14727xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = {
14728 Opcode_any8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14729};
14730
7aa09196
SA		 14731xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = {
14732 Opcode_all8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14733};
14734
7aa09196
SA		 14735xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = {
14736 Opcode_bf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14737};
14738
7aa09196
SA		 14739xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = {
14740 Opcode_bt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14741};
14742
7aa09196
SA		 14743xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = {
14744 Opcode_movf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14745};
14746
7aa09196
SA		 14747xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = {
14748 Opcode_movt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14749};
14750
7aa09196
SA		 14751xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = {
14752 Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14753};
14754
7aa09196
SA		 14755xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = {
14756 Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14757};
14758
7aa09196
SA		 14759xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = {
14760 Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14761};
14762
7aa09196
SA		 14763xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
14764 Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14765};
14766
7aa09196
SA		 14767xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
14768 Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14769};
14770
7aa09196
SA		 14771xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
14772 Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14773};
14774
7aa09196
SA		 14775xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
14776 Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14777};
14778
7aa09196
SA		 14779xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
14780 Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14781};
14782
7aa09196
SA		 14783xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
14784 Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14785};
14786
7aa09196
SA		 14787xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
14788 Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14789};
14790
7aa09196
SA		 14791xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
14792 Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14793};
14794
7aa09196
SA		 14795xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
14796 Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14797};
14798
7aa09196
SA		 14799xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
14800 Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14801};
14802
7aa09196
SA		 14803xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
14804 Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14805};
14806
7aa09196
SA		 14807xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
14808 Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
43cd72b9
BW		 14809};
14810
7aa09196
SA		 14811xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
14812 Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14813};
14814
7aa09196
SA		 14815xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
14816 Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14817};
14818
7aa09196
SA		 14819xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = {
14820 Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14821};
14822
7aa09196
SA		 14823xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = {
14824 Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14825};
14826
7aa09196
SA		 14827xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = {
14828 Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14829};
14830
7aa09196
SA		 14831xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
14832 Opcode_iii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14833};
14834
7aa09196
SA		 14835xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
14836 Opcode_lict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14837};
14838
7aa09196
SA		 14839xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
14840 Opcode_licw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14841};
14842
7aa09196
SA		 14843xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
14844 Opcode_sict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14845};
14846
7aa09196
SA		 14847xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
14848 Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 14849};
14850
7aa09196
SA		 14851xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
14852 Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14853};
14854
7aa09196
SA		 14855xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
14856 Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14857};
14858
7aa09196
SA		 14859xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
14860 Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14861};
14862
7aa09196
SA		 14863xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
14864 Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14865};
14866
7aa09196
SA		 14867xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
14868 Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14869};
14870
7aa09196
SA		 14871xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
14872 Opcode_dii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14873};
14874
7aa09196
SA		 14875xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
14876 Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14877};
14878
7aa09196
SA		 14879xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
14880 Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14881};
14882
7aa09196
SA		 14883xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
14884 Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14885};
14886
7aa09196
SA		 14887xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
14888 Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14889};
14890
7aa09196
SA		 14891xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = {
14892 Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14893};
14894
7aa09196
SA		 14895xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = {
14896 Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14897};
14898
7aa09196
SA		 14899xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = {
14900 Opcode_diu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14901};
14902
7aa09196
SA		 14903xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
14904 Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14905};
14906
7aa09196
SA		 14907xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
14908 Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14909};
14910
7aa09196
SA		 14911xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
14912 Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14913};
14914
7aa09196
SA		 14915xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
14916 Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14917};
14918
7aa09196
SA		 14919xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
14920 Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14921};
14922
7aa09196
SA		 14923xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
14924 Opcode_rsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14925};
14926
7aa09196
SA		 14927xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
14928 Opcode_wsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14929};
14930
7aa09196
SA		 14931xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
14932 Opcode_xsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14933};
14934
7aa09196
SA		 14935xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
14936 Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14937};
14938
7aa09196
SA		 14939xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
14940 Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14941};
14942
7aa09196
SA		 14943xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
14944 Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14945};
14946
7aa09196
SA		 14947xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
14948 Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14949};
14950
7aa09196
SA		 14951xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
14952 Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14953};
14954
7aa09196
SA		 14955xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
14956 Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14957};
14958
7aa09196
SA		 14959xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
14960 Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14961};
14962
7aa09196
SA		 14963xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
14964 Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14965};
14966
7aa09196
SA		 14967xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
14968 Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14969};
14970
7aa09196
SA		 14971xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
14972 Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14973};
14974
7aa09196
SA		 14975xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
14976 Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14977};
14978
7aa09196
SA		 14979xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
14980 Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14981};
14982
7aa09196
SA		 14983xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
14984 Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14985};
14986
7aa09196
SA		 14987xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
14988 Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14989};
14990
7aa09196
SA		 14991xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
14992 Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14993};
14994
7aa09196
SA		 14995xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
14996 Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 14997};
14998
7aa09196
SA		 14999xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
15000 Opcode_ldpte_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15001};
15002
7aa09196
SA		 15003xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
15004 Opcode_hwwitlba_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15005};
15006
7aa09196
SA		 15007xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
15008 Opcode_hwwdtlba_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15009};
15010
7aa09196
SA		 15011xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
15012 Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15013};
15014
7aa09196
SA		 15015xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
15016 Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15017};
15018
7aa09196
SA		 15019xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
15020 Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15021};
15022
7aa09196
SA		 15023xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
15024 Opcode_clamps_Slot_inst_encode, 0, 0, Opcode_clamps_Slot_xt_flix64_slot0_encode, Opcode_clamps_Slot_xt_flix64_slot0_encode, 0, 0, 0
e0001a05
NC		 15025};
15026
7aa09196
SA		 15027xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
15028 Opcode_min_Slot_inst_encode, 0, 0, Opcode_min_Slot_xt_flix64_slot0_encode, Opcode_min_Slot_xt_flix64_slot0_encode, 0, 0, 0
e0001a05
NC		 15029};
15030
7aa09196
SA		 15031xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
15032 Opcode_max_Slot_inst_encode, 0, 0, Opcode_max_Slot_xt_flix64_slot0_encode, Opcode_max_Slot_xt_flix64_slot0_encode, 0, 0, 0
33430bd0
BW		 15033};
15034
7aa09196
SA		 15035xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
15036 Opcode_minu_Slot_inst_encode, 0, 0, Opcode_minu_Slot_xt_flix64_slot0_encode, Opcode_minu_Slot_xt_flix64_slot0_encode, 0, 0, 0
e0001a05
NC		 15037};
15038
7aa09196
SA		 15039xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
15040 Opcode_maxu_Slot_inst_encode, 0, 0, Opcode_maxu_Slot_xt_flix64_slot0_encode, Opcode_maxu_Slot_xt_flix64_slot0_encode, 0, 0, 0
e0001a05
NC		 15041};
15042
7aa09196
SA		 15043xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
15044 Opcode_nsa_Slot_inst_encode, 0, 0, Opcode_nsa_Slot_xt_flix64_slot0_encode, Opcode_nsa_Slot_xt_flix64_slot0_encode, 0, 0, 0
e0001a05
NC		 15045};
15046
7aa09196
SA		 15047xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
15048 Opcode_nsau_Slot_inst_encode, 0, 0, Opcode_nsau_Slot_xt_flix64_slot0_encode, Opcode_nsau_Slot_xt_flix64_slot0_encode, 0, 0, 0
e0001a05
NC		 15049};
15050
7aa09196
SA		 15051xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
15052 Opcode_sext_Slot_inst_encode, 0, 0, Opcode_sext_Slot_xt_flix64_slot0_encode, Opcode_sext_Slot_xt_flix64_slot0_encode, Opcode_sext_Slot_xt_flix64_slot1_encode, Opcode_sext_Slot_xt_flix64_slot2_encode, 0
e0001a05
NC		 15053};
15054
7aa09196
SA		 15055xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
15056 Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15057};
15058
7aa09196
SA		 15059xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
15060 Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15061};
15062
7aa09196
SA		 15063xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
15064 Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15065};
15066
7aa09196
SA		 15067xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
15068 Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15069};
15070
7aa09196
SA		 15071xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
15072 Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15073};
15074
7aa09196
SA		 15075xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
15076 Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15077};
15078
7aa09196
SA		 15079xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
15080 Opcode_quou_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15081};
15082
7aa09196
SA		 15083xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
15084 Opcode_quos_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15085};
15086
7aa09196
SA		 15087xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
15088 Opcode_remu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15089};
15090
7aa09196
SA		 15091xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
15092 Opcode_rems_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 15093};
15094
7aa09196
SA		 15095xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
15096 Opcode_mull_Slot_inst_encode, 0, 0, Opcode_mull_Slot_xt_flix64_slot0_encode, Opcode_mull_Slot_xt_flix64_slot0_encode, Opcode_mull_Slot_xt_flix64_slot1_encode, 0, 0
33430bd0
BW		 15097};
15098
7aa09196
SA		 15099xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = {
15100 Opcode_muluh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 15101};
15102
7aa09196
SA		 15103xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = {
15104 Opcode_mulsh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15105};
15106
7aa09196
SA		 15107xtensa_opcode_encode_fn Opcode_rur_fcr_encode_fns[] = {
15108 Opcode_rur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15109};
15110
7aa09196
SA		 15111xtensa_opcode_encode_fn Opcode_wur_fcr_encode_fns[] = {
15112 Opcode_wur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15113};
15114
7aa09196
SA		 15115xtensa_opcode_encode_fn Opcode_rur_fsr_encode_fns[] = {
15116 Opcode_rur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15117};
15118
7aa09196
SA		 15119xtensa_opcode_encode_fn Opcode_wur_fsr_encode_fns[] = {
15120 Opcode_wur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15121};
15122
7aa09196
SA		 15123xtensa_opcode_encode_fn Opcode_add_s_encode_fns[] = {
15124 Opcode_add_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15125};
15126
7aa09196
SA		 15127xtensa_opcode_encode_fn Opcode_sub_s_encode_fns[] = {
15128 Opcode_sub_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15129};
15130
7aa09196
SA		 15131xtensa_opcode_encode_fn Opcode_mul_s_encode_fns[] = {
15132 Opcode_mul_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15133};
15134
7aa09196
SA		 15135xtensa_opcode_encode_fn Opcode_madd_s_encode_fns[] = {
15136 Opcode_madd_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15137};
15138
7aa09196
SA		 15139xtensa_opcode_encode_fn Opcode_msub_s_encode_fns[] = {
15140 Opcode_msub_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15141};
15142
7aa09196
SA		 15143xtensa_opcode_encode_fn Opcode_movf_s_encode_fns[] = {
15144 Opcode_movf_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15145};
15146
7aa09196
SA		 15147xtensa_opcode_encode_fn Opcode_movt_s_encode_fns[] = {
15148 Opcode_movt_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15149};
15150
7aa09196
SA		 15151xtensa_opcode_encode_fn Opcode_moveqz_s_encode_fns[] = {
15152 Opcode_moveqz_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15153};
15154
7aa09196
SA		 15155xtensa_opcode_encode_fn Opcode_movnez_s_encode_fns[] = {
15156 Opcode_movnez_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15157};
15158
7aa09196
SA		 15159xtensa_opcode_encode_fn Opcode_movltz_s_encode_fns[] = {
15160 Opcode_movltz_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15161};
15162
7aa09196
SA		 15163xtensa_opcode_encode_fn Opcode_movgez_s_encode_fns[] = {
15164 Opcode_movgez_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 15165};
15166
7aa09196
SA		 15167xtensa_opcode_encode_fn Opcode_abs_s_encode_fns[] = {
15168 Opcode_abs_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 15169};
15170
7aa09196
SA		 15171xtensa_opcode_encode_fn Opcode_mov_s_encode_fns[] = {
15172 Opcode_mov_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
33430bd0
BW		 15173};
15174
7aa09196
SA		 15175xtensa_opcode_encode_fn Opcode_neg_s_encode_fns[] = {
15176 Opcode_neg_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15177};
15178
7aa09196
SA		 15179xtensa_opcode_encode_fn Opcode_un_s_encode_fns[] = {
15180 Opcode_un_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15181};
15182
7aa09196
SA		 15183xtensa_opcode_encode_fn Opcode_oeq_s_encode_fns[] = {
15184 Opcode_oeq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
074f5109
BW		 15185};
15186
7aa09196
SA		 15187xtensa_opcode_encode_fn Opcode_ueq_s_encode_fns[] = {
15188 Opcode_ueq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
074f5109
BW		 15189};
15190
7aa09196
SA		 15191xtensa_opcode_encode_fn Opcode_olt_s_encode_fns[] = {
15192 Opcode_olt_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
074f5109
BW		 15193};
15194
7aa09196
SA		 15195xtensa_opcode_encode_fn Opcode_ult_s_encode_fns[] = {
15196 Opcode_ult_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
074f5109
BW		 15197};
15198
7aa09196
SA		 15199xtensa_opcode_encode_fn Opcode_ole_s_encode_fns[] = {
15200 Opcode_ole_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
074f5109
BW		 15201};
15202
7aa09196
SA		 15203xtensa_opcode_encode_fn Opcode_ule_s_encode_fns[] = {
15204 Opcode_ule_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
074f5109
BW		 15205};
15206
7aa09196
SA		 15207xtensa_opcode_encode_fn Opcode_float_s_encode_fns[] = {
15208 Opcode_float_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
074f5109
BW		 15209};
15210
7aa09196
SA		 15211xtensa_opcode_encode_fn Opcode_ufloat_s_encode_fns[] = {
15212 Opcode_ufloat_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
074f5109
BW		 15213};
15214
7aa09196
SA		 15215xtensa_opcode_encode_fn Opcode_round_s_encode_fns[] = {
15216 Opcode_round_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
074f5109
BW		 15217};
15218
7aa09196
SA		 15219xtensa_opcode_encode_fn Opcode_ceil_s_encode_fns[] = {
15220 Opcode_ceil_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
074f5109
BW		 15221};
15222
7aa09196
SA		 15223xtensa_opcode_encode_fn Opcode_floor_s_encode_fns[] = {
15224 Opcode_floor_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
074f5109
BW		 15225};
15226
7aa09196
SA		 15227xtensa_opcode_encode_fn Opcode_trunc_s_encode_fns[] = {
15228 Opcode_trunc_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
074f5109
BW		 15229};
15230
7aa09196
SA		 15231xtensa_opcode_encode_fn Opcode_utrunc_s_encode_fns[] = {
15232 Opcode_utrunc_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15233};
15234
7aa09196
SA		 15235xtensa_opcode_encode_fn Opcode_rfr_encode_fns[] = {
15236 Opcode_rfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15237};
15238
7aa09196
SA		 15239xtensa_opcode_encode_fn Opcode_wfr_encode_fns[] = {
15240 Opcode_wfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15241};
15242
7aa09196
SA		 15243xtensa_opcode_encode_fn Opcode_lsi_encode_fns[] = {
15244 Opcode_lsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15245};
15246
7aa09196
SA		 15247xtensa_opcode_encode_fn Opcode_lsiu_encode_fns[] = {
15248 Opcode_lsiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15249};
15250
7aa09196
SA		 15251xtensa_opcode_encode_fn Opcode_lsx_encode_fns[] = {
15252 Opcode_lsx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15253};
15254
7aa09196
SA		 15255xtensa_opcode_encode_fn Opcode_lsxu_encode_fns[] = {
15256 Opcode_lsxu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15257};
15258
7aa09196
SA		 15259xtensa_opcode_encode_fn Opcode_ssi_encode_fns[] = {
15260 Opcode_ssi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15261};
15262
7aa09196
SA		 15263xtensa_opcode_encode_fn Opcode_ssiu_encode_fns[] = {
15264 Opcode_ssiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15265};
15266
7aa09196
SA		 15267xtensa_opcode_encode_fn Opcode_ssx_encode_fns[] = {
15268 Opcode_ssx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
e0001a05
NC		 15269};
15270
7aa09196
SA		 15271xtensa_opcode_encode_fn Opcode_ssxu_encode_fns[] = {
15272 Opcode_ssxu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
074f5109
BW		 15273};
15274
7aa09196
SA		 15275xtensa_opcode_encode_fn Opcode_beqz_w18_encode_fns[] = {
15276 0, 0, 0, 0, 0, 0, 0, Opcode_beqz_w18_Slot_xt_flix64_slot3_encode
074f5109
BW		 15277};
15278
7aa09196
SA		 15279xtensa_opcode_encode_fn Opcode_bnez_w18_encode_fns[] = {
15280 0, 0, 0, 0, 0, 0, 0, Opcode_bnez_w18_Slot_xt_flix64_slot3_encode
074f5109
BW		 15281};
15282
7aa09196
SA		 15283xtensa_opcode_encode_fn Opcode_bgez_w18_encode_fns[] = {
15284 0, 0, 0, 0, 0, 0, 0, Opcode_bgez_w18_Slot_xt_flix64_slot3_encode
33430bd0
BW		 15285};
15286
7aa09196
SA		 15287xtensa_opcode_encode_fn Opcode_bltz_w18_encode_fns[] = {
15288 0, 0, 0, 0, 0, 0, 0, Opcode_bltz_w18_Slot_xt_flix64_slot3_encode
33430bd0
BW		 15289};
15290
7aa09196
SA		 15291xtensa_opcode_encode_fn Opcode_beqi_w18_encode_fns[] = {
15292 0, 0, 0, 0, 0, 0, 0, Opcode_beqi_w18_Slot_xt_flix64_slot3_encode
33430bd0
BW		 15293};
15294
7aa09196
SA		 15295xtensa_opcode_encode_fn Opcode_bnei_w18_encode_fns[] = {
15296 0, 0, 0, 0, 0, 0, 0, Opcode_bnei_w18_Slot_xt_flix64_slot3_encode
33430bd0
BW		 15297};
15298
7aa09196
SA		 15299xtensa_opcode_encode_fn Opcode_bgei_w18_encode_fns[] = {
15300 0, 0, 0, 0, 0, 0, 0, Opcode_bgei_w18_Slot_xt_flix64_slot3_encode
33430bd0
BW		 15301};
15302
7aa09196
SA		 15303xtensa_opcode_encode_fn Opcode_blti_w18_encode_fns[] = {
15304 0, 0, 0, 0, 0, 0, 0, Opcode_blti_w18_Slot_xt_flix64_slot3_encode
33430bd0
BW		 15305};
15306
7aa09196
SA		 15307xtensa_opcode_encode_fn Opcode_bgeui_w18_encode_fns[] = {
15308 0, 0, 0, 0, 0, 0, 0, Opcode_bgeui_w18_Slot_xt_flix64_slot3_encode
33430bd0
BW		 15309};
15310
7aa09196
SA		 15311xtensa_opcode_encode_fn Opcode_bltui_w18_encode_fns[] = {
15312 0, 0, 0, 0, 0, 0, 0, Opcode_bltui_w18_Slot_xt_flix64_slot3_encode
33430bd0
BW		 15313};
15314
7aa09196
SA		 15315xtensa_opcode_encode_fn Opcode_bbci_w18_encode_fns[] = {
15316 0, 0, 0, 0, 0, 0, 0, Opcode_bbci_w18_Slot_xt_flix64_slot3_encode
e0001a05
NC		 15317};
15318
7aa09196
SA		 15319xtensa_opcode_encode_fn Opcode_bbsi_w18_encode_fns[] = {
15320 0, 0, 0, 0, 0, 0, 0, Opcode_bbsi_w18_Slot_xt_flix64_slot3_encode
e0001a05
NC		 15321};
15322
7aa09196
SA		 15323xtensa_opcode_encode_fn Opcode_beq_w18_encode_fns[] = {
15324 0, 0, 0, 0, 0, 0, 0, Opcode_beq_w18_Slot_xt_flix64_slot3_encode
33430bd0
BW		 15325};
15326
7aa09196
SA		 15327xtensa_opcode_encode_fn Opcode_bne_w18_encode_fns[] = {
15328 0, 0, 0, 0, 0, 0, 0, Opcode_bne_w18_Slot_xt_flix64_slot3_encode
33430bd0
BW		 15329};
15330
7aa09196
SA		 15331xtensa_opcode_encode_fn Opcode_bge_w18_encode_fns[] = {
15332 0, 0, 0, 0, 0, 0, 0, Opcode_bge_w18_Slot_xt_flix64_slot3_encode
33430bd0
BW		 15333};
15334
7aa09196
SA		 15335xtensa_opcode_encode_fn Opcode_blt_w18_encode_fns[] = {
15336 0, 0, 0, 0, 0, 0, 0, Opcode_blt_w18_Slot_xt_flix64_slot3_encode
33430bd0
BW		 15337};
15338
7aa09196
SA		 15339xtensa_opcode_encode_fn Opcode_bgeu_w18_encode_fns[] = {
15340 0, 0, 0, 0, 0, 0, 0, Opcode_bgeu_w18_Slot_xt_flix64_slot3_encode
33430bd0
BW		 15341};
15342
7aa09196
SA		 15343xtensa_opcode_encode_fn Opcode_bltu_w18_encode_fns[] = {
15344 0, 0, 0, 0, 0, 0, 0, Opcode_bltu_w18_Slot_xt_flix64_slot3_encode
33430bd0
BW		 15345};
15346
7aa09196
SA		 15347xtensa_opcode_encode_fn Opcode_bany_w18_encode_fns[] = {
15348 0, 0, 0, 0, 0, 0, 0, Opcode_bany_w18_Slot_xt_flix64_slot3_encode
33430bd0
BW		 15349};
15350
7aa09196
SA		 15351xtensa_opcode_encode_fn Opcode_bnone_w18_encode_fns[] = {
15352 0, 0, 0, 0, 0, 0, 0, Opcode_bnone_w18_Slot_xt_flix64_slot3_encode
33430bd0
BW		 15353};
15354
7aa09196
SA		 15355xtensa_opcode_encode_fn Opcode_ball_w18_encode_fns[] = {
15356 0, 0, 0, 0, 0, 0, 0, Opcode_ball_w18_Slot_xt_flix64_slot3_encode
33430bd0
BW		 15357};
15358
7aa09196
SA		 15359xtensa_opcode_encode_fn Opcode_bnall_w18_encode_fns[] = {
15360 0, 0, 0, 0, 0, 0, 0, Opcode_bnall_w18_Slot_xt_flix64_slot3_encode
33430bd0
BW		 15361};
15362
7aa09196
SA		 15363xtensa_opcode_encode_fn Opcode_bbc_w18_encode_fns[] = {
15364 0, 0, 0, 0, 0, 0, 0, Opcode_bbc_w18_Slot_xt_flix64_slot3_encode
33430bd0
BW		 15365};
15366
7aa09196
SA		 15367xtensa_opcode_encode_fn Opcode_bbs_w18_encode_fns[] = {
15368 0, 0, 0, 0, 0, 0, 0, Opcode_bbs_w18_Slot_xt_flix64_slot3_encode
33430bd0
BW		 15369};
15370
43cd72b9
BW		 15371\f
15372/* Opcode table. */
15373
15374static xtensa_opcode_internal opcodes[] = {
7aa09196 15375 { "excw", 0 /* xt_iclass_excw */,
43cd72b9
BW		 15376 0,
15377 Opcode_excw_encode_fns, 0, 0 },
7aa09196 15378 { "rfe", 1 /* xt_iclass_rfe */,
43cd72b9
BW		 15379 XTENSA_OPCODE_IS_JUMP,
15380 Opcode_rfe_encode_fns, 0, 0 },
7aa09196 15381 { "rfde", 2 /* xt_iclass_rfde */,
43cd72b9
BW		 15382 XTENSA_OPCODE_IS_JUMP,
15383 Opcode_rfde_encode_fns, 0, 0 },
7aa09196 15384 { "syscall", 3 /* xt_iclass_syscall */,
43cd72b9
BW		 15385 0,
15386 Opcode_syscall_encode_fns, 0, 0 },
7aa09196 15387 { "simcall", 4 /* xt_iclass_simcall */,
43cd72b9
BW		 15388 0,
15389 Opcode_simcall_encode_fns, 0, 0 },
7aa09196 15390 { "call12", 5 /* xt_iclass_call12 */,
43cd72b9
BW		 15391 XTENSA_OPCODE_IS_CALL,
15392 Opcode_call12_encode_fns, 0, 0 },
7aa09196 15393 { "call8", 6 /* xt_iclass_call8 */,
43cd72b9
BW		 15394 XTENSA_OPCODE_IS_CALL,
15395 Opcode_call8_encode_fns, 0, 0 },
7aa09196 15396 { "call4", 7 /* xt_iclass_call4 */,
43cd72b9
BW		 15397 XTENSA_OPCODE_IS_CALL,
15398 Opcode_call4_encode_fns, 0, 0 },
7aa09196 15399 { "callx12", 8 /* xt_iclass_callx12 */,
43cd72b9
BW		 15400 XTENSA_OPCODE_IS_CALL,
15401 Opcode_callx12_encode_fns, 0, 0 },
7aa09196 15402 { "callx8", 9 /* xt_iclass_callx8 */,
43cd72b9
BW		 15403 XTENSA_OPCODE_IS_CALL,
15404 Opcode_callx8_encode_fns, 0, 0 },
7aa09196 15405 { "callx4", 10 /* xt_iclass_callx4 */,
43cd72b9
BW		 15406 XTENSA_OPCODE_IS_CALL,
15407 Opcode_callx4_encode_fns, 0, 0 },
7aa09196 15408 { "entry", 11 /* xt_iclass_entry */,
43cd72b9
BW		 15409 0,
15410 Opcode_entry_encode_fns, 0, 0 },
7aa09196 15411 { "movsp", 12 /* xt_iclass_movsp */,
43cd72b9
BW		 15412 0,
15413 Opcode_movsp_encode_fns, 0, 0 },
7aa09196 15414 { "rotw", 13 /* xt_iclass_rotw */,
43cd72b9
BW		 15415 0,
15416 Opcode_rotw_encode_fns, 0, 0 },
7aa09196 15417 { "retw", 14 /* xt_iclass_retw */,
43cd72b9
BW		 15418 XTENSA_OPCODE_IS_JUMP,
15419 Opcode_retw_encode_fns, 0, 0 },
7aa09196 15420 { "retw.n", 14 /* xt_iclass_retw */,
43cd72b9
BW		 15421 XTENSA_OPCODE_IS_JUMP,
15422 Opcode_retw_n_encode_fns, 0, 0 },
7aa09196 15423 { "rfwo", 15 /* xt_iclass_rfwou */,
43cd72b9
BW		 15424 XTENSA_OPCODE_IS_JUMP,
15425 Opcode_rfwo_encode_fns, 0, 0 },
7aa09196 15426 { "rfwu", 15 /* xt_iclass_rfwou */,
43cd72b9
BW		 15427 XTENSA_OPCODE_IS_JUMP,
15428 Opcode_rfwu_encode_fns, 0, 0 },
7aa09196 15429 { "l32e", 16 /* xt_iclass_l32e */,
43cd72b9
BW		 15430 0,
15431 Opcode_l32e_encode_fns, 0, 0 },
7aa09196 15432 { "s32e", 17 /* xt_iclass_s32e */,
43cd72b9
BW		 15433 0,
15434 Opcode_s32e_encode_fns, 0, 0 },
7aa09196 15435 { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */,
43cd72b9
BW		 15436 0,
15437 Opcode_rsr_windowbase_encode_fns, 0, 0 },
7aa09196 15438 { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */,
43cd72b9
BW		 15439 0,
15440 Opcode_wsr_windowbase_encode_fns, 0, 0 },
7aa09196 15441 { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */,
43cd72b9
BW		 15442 0,
15443 Opcode_xsr_windowbase_encode_fns, 0, 0 },
7aa09196 15444 { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */,
43cd72b9
BW		 15445 0,
15446 Opcode_rsr_windowstart_encode_fns, 0, 0 },
7aa09196 15447 { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */,
43cd72b9
BW		 15448 0,
15449 Opcode_wsr_windowstart_encode_fns, 0, 0 },
7aa09196 15450 { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */,
43cd72b9
BW		 15451 0,
15452 Opcode_xsr_windowstart_encode_fns, 0, 0 },
7aa09196 15453 { "add.n", 24 /* xt_iclass_add.n */,
43cd72b9
BW		 15454 0,
15455 Opcode_add_n_encode_fns, 0, 0 },
7aa09196 15456 { "addi.n", 25 /* xt_iclass_addi.n */,
43cd72b9
BW		 15457 0,
15458 Opcode_addi_n_encode_fns, 0, 0 },
7aa09196 15459 { "beqz.n", 26 /* xt_iclass_bz6 */,
43cd72b9
BW		 15460 XTENSA_OPCODE_IS_BRANCH,
15461 Opcode_beqz_n_encode_fns, 0, 0 },
7aa09196 15462 { "bnez.n", 26 /* xt_iclass_bz6 */,
43cd72b9
BW		 15463 XTENSA_OPCODE_IS_BRANCH,
15464 Opcode_bnez_n_encode_fns, 0, 0 },
7aa09196 15465 { "ill.n", 27 /* xt_iclass_ill.n */,
43cd72b9
BW		 15466 0,
15467 Opcode_ill_n_encode_fns, 0, 0 },
7aa09196 15468 { "l32i.n", 28 /* xt_iclass_loadi4 */,
43cd72b9
BW		 15469 0,
15470 Opcode_l32i_n_encode_fns, 0, 0 },
7aa09196 15471 { "mov.n", 29 /* xt_iclass_mov.n */,
43cd72b9
BW		 15472 0,
15473 Opcode_mov_n_encode_fns, 0, 0 },
7aa09196 15474 { "movi.n", 30 /* xt_iclass_movi.n */,
43cd72b9
BW		 15475 0,
15476 Opcode_movi_n_encode_fns, 0, 0 },
7aa09196 15477 { "nop.n", 31 /* xt_iclass_nopn */,
43cd72b9
BW		 15478 0,
15479 Opcode_nop_n_encode_fns, 0, 0 },
7aa09196 15480 { "ret.n", 32 /* xt_iclass_retn */,
43cd72b9
BW		 15481 XTENSA_OPCODE_IS_JUMP,
15482 Opcode_ret_n_encode_fns, 0, 0 },
7aa09196 15483 { "s32i.n", 33 /* xt_iclass_storei4 */,
43cd72b9
BW		 15484 0,
15485 Opcode_s32i_n_encode_fns, 0, 0 },
7aa09196 15486 { "rur.threadptr", 34 /* rur_threadptr */,
33430bd0
BW		 15487 0,
15488 Opcode_rur_threadptr_encode_fns, 0, 0 },
7aa09196 15489 { "wur.threadptr", 35 /* wur_threadptr */,
33430bd0
BW		 15490 0,
15491 Opcode_wur_threadptr_encode_fns, 0, 0 },
7aa09196 15492 { "addi", 36 /* xt_iclass_addi */,
43cd72b9
BW		 15493 0,
15494 Opcode_addi_encode_fns, 0, 0 },
7aa09196 15495 { "addmi", 37 /* xt_iclass_addmi */,
43cd72b9
BW		 15496 0,
15497 Opcode_addmi_encode_fns, 0, 0 },
7aa09196 15498 { "add", 38 /* xt_iclass_addsub */,
43cd72b9
BW		 15499 0,
15500 Opcode_add_encode_fns, 0, 0 },
7aa09196 15501 { "sub", 38 /* xt_iclass_addsub */,
43cd72b9
BW		 15502 0,
15503 Opcode_sub_encode_fns, 0, 0 },
7aa09196 15504 { "addx2", 38 /* xt_iclass_addsub */,
43cd72b9
BW		 15505 0,
15506 Opcode_addx2_encode_fns, 0, 0 },
7aa09196 15507 { "addx4", 38 /* xt_iclass_addsub */,
43cd72b9
BW		 15508 0,
15509 Opcode_addx4_encode_fns, 0, 0 },
7aa09196 15510 { "addx8", 38 /* xt_iclass_addsub */,
43cd72b9
BW		 15511 0,
15512 Opcode_addx8_encode_fns, 0, 0 },
7aa09196 15513 { "subx2", 38 /* xt_iclass_addsub */,
43cd72b9
BW		 15514 0,
15515 Opcode_subx2_encode_fns, 0, 0 },
7aa09196 15516 { "subx4", 38 /* xt_iclass_addsub */,
43cd72b9
BW		 15517 0,
15518 Opcode_subx4_encode_fns, 0, 0 },
7aa09196 15519 { "subx8", 38 /* xt_iclass_addsub */,
43cd72b9
BW		 15520 0,
15521 Opcode_subx8_encode_fns, 0, 0 },
7aa09196 15522 { "and", 39 /* xt_iclass_bit */,
43cd72b9
BW		 15523 0,
15524 Opcode_and_encode_fns, 0, 0 },
7aa09196 15525 { "or", 39 /* xt_iclass_bit */,
43cd72b9
BW		 15526 0,
15527 Opcode_or_encode_fns, 0, 0 },
7aa09196 15528 { "xor", 39 /* xt_iclass_bit */,
43cd72b9
BW		 15529 0,
15530 Opcode_xor_encode_fns, 0, 0 },
7aa09196 15531 { "beqi", 40 /* xt_iclass_bsi8 */,
43cd72b9
BW		 15532 XTENSA_OPCODE_IS_BRANCH,
15533 Opcode_beqi_encode_fns, 0, 0 },
7aa09196 15534 { "bnei", 40 /* xt_iclass_bsi8 */,
43cd72b9
BW		 15535 XTENSA_OPCODE_IS_BRANCH,
15536 Opcode_bnei_encode_fns, 0, 0 },
7aa09196 15537 { "bgei", 40 /* xt_iclass_bsi8 */,
43cd72b9
BW		 15538 XTENSA_OPCODE_IS_BRANCH,
15539 Opcode_bgei_encode_fns, 0, 0 },
7aa09196 15540 { "blti", 40 /* xt_iclass_bsi8 */,
43cd72b9
BW		 15541 XTENSA_OPCODE_IS_BRANCH,
15542 Opcode_blti_encode_fns, 0, 0 },
7aa09196 15543 { "bbci", 41 /* xt_iclass_bsi8b */,
43cd72b9
BW		 15544 XTENSA_OPCODE_IS_BRANCH,
15545 Opcode_bbci_encode_fns, 0, 0 },
7aa09196 15546 { "bbsi", 41 /* xt_iclass_bsi8b */,
43cd72b9
BW		 15547 XTENSA_OPCODE_IS_BRANCH,
15548 Opcode_bbsi_encode_fns, 0, 0 },
7aa09196 15549 { "bgeui", 42 /* xt_iclass_bsi8u */,
43cd72b9
BW		 15550 XTENSA_OPCODE_IS_BRANCH,
15551 Opcode_bgeui_encode_fns, 0, 0 },
7aa09196 15552 { "bltui", 42 /* xt_iclass_bsi8u */,
43cd72b9
BW		 15553 XTENSA_OPCODE_IS_BRANCH,
15554 Opcode_bltui_encode_fns, 0, 0 },
7aa09196 15555 { "beq", 43 /* xt_iclass_bst8 */,
43cd72b9
BW		 15556 XTENSA_OPCODE_IS_BRANCH,
15557 Opcode_beq_encode_fns, 0, 0 },
7aa09196 15558 { "bne", 43 /* xt_iclass_bst8 */,
43cd72b9
BW		 15559 XTENSA_OPCODE_IS_BRANCH,
15560 Opcode_bne_encode_fns, 0, 0 },
7aa09196 15561 { "bge", 43 /* xt_iclass_bst8 */,
43cd72b9
BW		 15562 XTENSA_OPCODE_IS_BRANCH,
15563 Opcode_bge_encode_fns, 0, 0 },
7aa09196 15564 { "blt", 43 /* xt_iclass_bst8 */,
43cd72b9
BW		 15565 XTENSA_OPCODE_IS_BRANCH,
15566 Opcode_blt_encode_fns, 0, 0 },
7aa09196 15567 { "bgeu", 43 /* xt_iclass_bst8 */,
43cd72b9
BW		 15568 XTENSA_OPCODE_IS_BRANCH,
15569 Opcode_bgeu_encode_fns, 0, 0 },
7aa09196 15570 { "bltu", 43 /* xt_iclass_bst8 */,
43cd72b9
BW		 15571 XTENSA_OPCODE_IS_BRANCH,
15572 Opcode_bltu_encode_fns, 0, 0 },
7aa09196 15573 { "bany", 43 /* xt_iclass_bst8 */,
43cd72b9
BW		 15574 XTENSA_OPCODE_IS_BRANCH,
15575 Opcode_bany_encode_fns, 0, 0 },
7aa09196 15576 { "bnone", 43 /* xt_iclass_bst8 */,
43cd72b9
BW		 15577 XTENSA_OPCODE_IS_BRANCH,
15578 Opcode_bnone_encode_fns, 0, 0 },
7aa09196 15579 { "ball", 43 /* xt_iclass_bst8 */,
43cd72b9
BW		 15580 XTENSA_OPCODE_IS_BRANCH,
15581 Opcode_ball_encode_fns, 0, 0 },
7aa09196 15582 { "bnall", 43 /* xt_iclass_bst8 */,
43cd72b9
BW		 15583 XTENSA_OPCODE_IS_BRANCH,
15584 Opcode_bnall_encode_fns, 0, 0 },
7aa09196 15585 { "bbc", 43 /* xt_iclass_bst8 */,
43cd72b9
BW		 15586 XTENSA_OPCODE_IS_BRANCH,
15587 Opcode_bbc_encode_fns, 0, 0 },
7aa09196 15588 { "bbs", 43 /* xt_iclass_bst8 */,
43cd72b9
BW		 15589 XTENSA_OPCODE_IS_BRANCH,
15590 Opcode_bbs_encode_fns, 0, 0 },
7aa09196 15591 { "beqz", 44 /* xt_iclass_bsz12 */,
43cd72b9
BW		 15592 XTENSA_OPCODE_IS_BRANCH,
15593 Opcode_beqz_encode_fns, 0, 0 },
7aa09196 15594 { "bnez", 44 /* xt_iclass_bsz12 */,
43cd72b9
BW		 15595 XTENSA_OPCODE_IS_BRANCH,
15596 Opcode_bnez_encode_fns, 0, 0 },
7aa09196 15597 { "bgez", 44 /* xt_iclass_bsz12 */,
43cd72b9
BW		 15598 XTENSA_OPCODE_IS_BRANCH,
15599 Opcode_bgez_encode_fns, 0, 0 },
7aa09196 15600 { "bltz", 44 /* xt_iclass_bsz12 */,
43cd72b9
BW		 15601 XTENSA_OPCODE_IS_BRANCH,
15602 Opcode_bltz_encode_fns, 0, 0 },
7aa09196 15603 { "call0", 45 /* xt_iclass_call0 */,
43cd72b9
BW		 15604 XTENSA_OPCODE_IS_CALL,
15605 Opcode_call0_encode_fns, 0, 0 },
7aa09196 15606 { "callx0", 46 /* xt_iclass_callx0 */,
43cd72b9
BW		 15607 XTENSA_OPCODE_IS_CALL,
15608 Opcode_callx0_encode_fns, 0, 0 },
7aa09196 15609 { "extui", 47 /* xt_iclass_exti */,
43cd72b9
BW		 15610 0,
15611 Opcode_extui_encode_fns, 0, 0 },
7aa09196 15612 { "ill", 48 /* xt_iclass_ill */,
43cd72b9
BW		 15613 0,
15614 Opcode_ill_encode_fns, 0, 0 },
7aa09196 15615 { "j", 49 /* xt_iclass_jump */,
43cd72b9
BW		 15616 XTENSA_OPCODE_IS_JUMP,
15617 Opcode_j_encode_fns, 0, 0 },
7aa09196 15618 { "jx", 50 /* xt_iclass_jumpx */,
43cd72b9
BW		 15619 XTENSA_OPCODE_IS_JUMP,
15620 Opcode_jx_encode_fns, 0, 0 },
7aa09196 15621 { "l16ui", 51 /* xt_iclass_l16ui */,
43cd72b9
BW		 15622 0,
15623 Opcode_l16ui_encode_fns, 0, 0 },
7aa09196 15624 { "l16si", 52 /* xt_iclass_l16si */,
43cd72b9
BW		 15625 0,
15626 Opcode_l16si_encode_fns, 0, 0 },
7aa09196 15627 { "l32i", 53 /* xt_iclass_l32i */,
43cd72b9
BW		 15628 0,
15629 Opcode_l32i_encode_fns, 0, 0 },
7aa09196 15630 { "l32r", 54 /* xt_iclass_l32r */,
43cd72b9
BW		 15631 0,
15632 Opcode_l32r_encode_fns, 0, 0 },
7aa09196 15633 { "l8ui", 55 /* xt_iclass_l8i */,
43cd72b9
BW		 15634 0,
15635 Opcode_l8ui_encode_fns, 0, 0 },
7aa09196 15636 { "loop", 56 /* xt_iclass_loop */,
43cd72b9
BW		 15637 XTENSA_OPCODE_IS_LOOP,
15638 Opcode_loop_encode_fns, 0, 0 },
7aa09196 15639 { "loopnez", 57 /* xt_iclass_loopz */,
43cd72b9
BW		 15640 XTENSA_OPCODE_IS_LOOP,
15641 Opcode_loopnez_encode_fns, 0, 0 },
7aa09196 15642 { "loopgtz", 57 /* xt_iclass_loopz */,
43cd72b9
BW		 15643 XTENSA_OPCODE_IS_LOOP,
15644 Opcode_loopgtz_encode_fns, 0, 0 },
7aa09196 15645 { "movi", 58 /* xt_iclass_movi */,
43cd72b9
BW		 15646 0,
15647 Opcode_movi_encode_fns, 0, 0 },
7aa09196 15648 { "moveqz", 59 /* xt_iclass_movz */,
43cd72b9
BW		 15649 0,
15650 Opcode_moveqz_encode_fns, 0, 0 },
7aa09196 15651 { "movnez", 59 /* xt_iclass_movz */,
43cd72b9
BW		 15652 0,
15653 Opcode_movnez_encode_fns, 0, 0 },
7aa09196 15654 { "movltz", 59 /* xt_iclass_movz */,
43cd72b9
BW		 15655 0,
15656 Opcode_movltz_encode_fns, 0, 0 },
7aa09196 15657 { "movgez", 59 /* xt_iclass_movz */,
43cd72b9
BW		 15658 0,
15659 Opcode_movgez_encode_fns, 0, 0 },
7aa09196 15660 { "neg", 60 /* xt_iclass_neg */,
43cd72b9
BW		 15661 0,
15662 Opcode_neg_encode_fns, 0, 0 },
7aa09196 15663 { "abs", 60 /* xt_iclass_neg */,
43cd72b9
BW		 15664 0,
15665 Opcode_abs_encode_fns, 0, 0 },
7aa09196 15666 { "nop", 61 /* xt_iclass_nop */,
43cd72b9
BW		 15667 0,
15668 Opcode_nop_encode_fns, 0, 0 },
7aa09196 15669 { "ret", 62 /* xt_iclass_return */,
43cd72b9
BW		 15670 XTENSA_OPCODE_IS_JUMP,
15671 Opcode_ret_encode_fns, 0, 0 },
7aa09196 15672 { "s16i", 63 /* xt_iclass_s16i */,
43cd72b9
BW		 15673 0,
15674 Opcode_s16i_encode_fns, 0, 0 },
7aa09196 15675 { "s32i", 64 /* xt_iclass_s32i */,
43cd72b9
BW		 15676 0,
15677 Opcode_s32i_encode_fns, 0, 0 },
7aa09196 15678 { "s8i", 65 /* xt_iclass_s8i */,
43cd72b9
BW		 15679 0,
15680 Opcode_s8i_encode_fns, 0, 0 },
7aa09196 15681 { "ssr", 66 /* xt_iclass_sar */,
43cd72b9
BW		 15682 0,
15683 Opcode_ssr_encode_fns, 0, 0 },
7aa09196 15684 { "ssl", 66 /* xt_iclass_sar */,
43cd72b9
BW		 15685 0,
15686 Opcode_ssl_encode_fns, 0, 0 },
7aa09196 15687 { "ssa8l", 66 /* xt_iclass_sar */,
43cd72b9
BW		 15688 0,
15689 Opcode_ssa8l_encode_fns, 0, 0 },
7aa09196 15690 { "ssa8b", 66 /* xt_iclass_sar */,
43cd72b9
BW		 15691 0,
15692 Opcode_ssa8b_encode_fns, 0, 0 },
7aa09196 15693 { "ssai", 67 /* xt_iclass_sari */,
43cd72b9
BW		 15694 0,
15695 Opcode_ssai_encode_fns, 0, 0 },
7aa09196 15696 { "sll", 68 /* xt_iclass_shifts */,
43cd72b9
BW		 15697 0,
15698 Opcode_sll_encode_fns, 0, 0 },
7aa09196 15699 { "src", 69 /* xt_iclass_shiftst */,
43cd72b9
BW		 15700 0,
15701 Opcode_src_encode_fns, 0, 0 },
7aa09196 15702 { "srl", 70 /* xt_iclass_shiftt */,
43cd72b9
BW		 15703 0,
15704 Opcode_srl_encode_fns, 0, 0 },
7aa09196 15705 { "sra", 70 /* xt_iclass_shiftt */,
43cd72b9
BW		 15706 0,
15707 Opcode_sra_encode_fns, 0, 0 },
7aa09196 15708 { "slli", 71 /* xt_iclass_slli */,
43cd72b9
BW		 15709 0,
15710 Opcode_slli_encode_fns, 0, 0 },
7aa09196 15711 { "srai", 72 /* xt_iclass_srai */,
43cd72b9
BW		 15712 0,
15713 Opcode_srai_encode_fns, 0, 0 },
7aa09196 15714 { "srli", 73 /* xt_iclass_srli */,
43cd72b9
BW		 15715 0,
15716 Opcode_srli_encode_fns, 0, 0 },
7aa09196 15717 { "memw", 74 /* xt_iclass_memw */,
43cd72b9
BW		 15718 0,
15719 Opcode_memw_encode_fns, 0, 0 },
7aa09196 15720 { "extw", 75 /* xt_iclass_extw */,
43cd72b9
BW		 15721 0,
15722 Opcode_extw_encode_fns, 0, 0 },
7aa09196 15723 { "isync", 76 /* xt_iclass_isync */,
43cd72b9
BW		 15724 0,
15725 Opcode_isync_encode_fns, 0, 0 },
7aa09196 15726 { "rsync", 77 /* xt_iclass_sync */,
43cd72b9
BW		 15727 0,
15728 Opcode_rsync_encode_fns, 0, 0 },
7aa09196 15729 { "esync", 77 /* xt_iclass_sync */,
43cd72b9
BW		 15730 0,
15731 Opcode_esync_encode_fns, 0, 0 },
7aa09196 15732 { "dsync", 77 /* xt_iclass_sync */,
43cd72b9
BW		 15733 0,
15734 Opcode_dsync_encode_fns, 0, 0 },
7aa09196 15735 { "rsil", 78 /* xt_iclass_rsil */,
43cd72b9
BW		 15736 0,
15737 Opcode_rsil_encode_fns, 0, 0 },
7aa09196 15738 { "rsr.lend", 79 /* xt_iclass_rsr.lend */,
43cd72b9
BW		 15739 0,
15740 Opcode_rsr_lend_encode_fns, 0, 0 },
7aa09196 15741 { "wsr.lend", 80 /* xt_iclass_wsr.lend */,
43cd72b9
BW		 15742 0,
15743 Opcode_wsr_lend_encode_fns, 0, 0 },
7aa09196 15744 { "xsr.lend", 81 /* xt_iclass_xsr.lend */,
43cd72b9
BW		 15745 0,
15746 Opcode_xsr_lend_encode_fns, 0, 0 },
7aa09196 15747 { "rsr.lcount", 82 /* xt_iclass_rsr.lcount */,
43cd72b9
BW		 15748 0,
15749 Opcode_rsr_lcount_encode_fns, 0, 0 },
7aa09196 15750 { "wsr.lcount", 83 /* xt_iclass_wsr.lcount */,
43cd72b9
BW		 15751 0,
15752 Opcode_wsr_lcount_encode_fns, 0, 0 },
7aa09196 15753 { "xsr.lcount", 84 /* xt_iclass_xsr.lcount */,
43cd72b9
BW		 15754 0,
15755 Opcode_xsr_lcount_encode_fns, 0, 0 },
7aa09196 15756 { "rsr.lbeg", 85 /* xt_iclass_rsr.lbeg */,
43cd72b9
BW		 15757 0,
15758 Opcode_rsr_lbeg_encode_fns, 0, 0 },
7aa09196 15759 { "wsr.lbeg", 86 /* xt_iclass_wsr.lbeg */,
43cd72b9
BW		 15760 0,
15761 Opcode_wsr_lbeg_encode_fns, 0, 0 },
7aa09196 15762 { "xsr.lbeg", 87 /* xt_iclass_xsr.lbeg */,
43cd72b9
BW		 15763 0,
15764 Opcode_xsr_lbeg_encode_fns, 0, 0 },
7aa09196 15765 { "rsr.sar", 88 /* xt_iclass_rsr.sar */,
43cd72b9
BW		 15766 0,
15767 Opcode_rsr_sar_encode_fns, 0, 0 },
7aa09196 15768 { "wsr.sar", 89 /* xt_iclass_wsr.sar */,
43cd72b9
BW		 15769 0,
15770 Opcode_wsr_sar_encode_fns, 0, 0 },
7aa09196 15771 { "xsr.sar", 90 /* xt_iclass_xsr.sar */,
43cd72b9
BW		 15772 0,
15773 Opcode_xsr_sar_encode_fns, 0, 0 },
7aa09196 15774 { "rsr.litbase", 91 /* xt_iclass_rsr.litbase */,
43cd72b9
BW		 15775 0,
15776 Opcode_rsr_litbase_encode_fns, 0, 0 },
7aa09196 15777 { "wsr.litbase", 92 /* xt_iclass_wsr.litbase */,
43cd72b9
BW		 15778 0,
15779 Opcode_wsr_litbase_encode_fns, 0, 0 },
7aa09196 15780 { "xsr.litbase", 93 /* xt_iclass_xsr.litbase */,
43cd72b9
BW		 15781 0,
15782 Opcode_xsr_litbase_encode_fns, 0, 0 },
7aa09196 15783 { "rsr.176", 94 /* xt_iclass_rsr.176 */,
43cd72b9
BW		 15784 0,
15785 Opcode_rsr_176_encode_fns, 0, 0 },
7aa09196 15786 { "rsr.208", 95 /* xt_iclass_rsr.208 */,
43cd72b9
BW		 15787 0,
15788 Opcode_rsr_208_encode_fns, 0, 0 },
7aa09196 15789 { "rsr.ps", 96 /* xt_iclass_rsr.ps */,
43cd72b9
BW		 15790 0,
15791 Opcode_rsr_ps_encode_fns, 0, 0 },
7aa09196 15792 { "wsr.ps", 97 /* xt_iclass_wsr.ps */,
43cd72b9
BW		 15793 0,
15794 Opcode_wsr_ps_encode_fns, 0, 0 },
7aa09196 15795 { "xsr.ps", 98 /* xt_iclass_xsr.ps */,
43cd72b9
BW		 15796 0,
15797 Opcode_xsr_ps_encode_fns, 0, 0 },
7aa09196 15798 { "rsr.epc1", 99 /* xt_iclass_rsr.epc1 */,
43cd72b9
BW		 15799 0,
15800 Opcode_rsr_epc1_encode_fns, 0, 0 },
7aa09196 15801 { "wsr.epc1", 100 /* xt_iclass_wsr.epc1 */,
43cd72b9
BW		 15802 0,
15803 Opcode_wsr_epc1_encode_fns, 0, 0 },
7aa09196 15804 { "xsr.epc1", 101 /* xt_iclass_xsr.epc1 */,
43cd72b9
BW		 15805 0,
15806 Opcode_xsr_epc1_encode_fns, 0, 0 },
7aa09196 15807 { "rsr.excsave1", 102 /* xt_iclass_rsr.excsave1 */,
43cd72b9
BW		 15808 0,
15809 Opcode_rsr_excsave1_encode_fns, 0, 0 },
7aa09196 15810 { "wsr.excsave1", 103 /* xt_iclass_wsr.excsave1 */,
43cd72b9
BW		 15811 0,
15812 Opcode_wsr_excsave1_encode_fns, 0, 0 },
7aa09196 15813 { "xsr.excsave1", 104 /* xt_iclass_xsr.excsave1 */,
43cd72b9
BW		 15814 0,
15815 Opcode_xsr_excsave1_encode_fns, 0, 0 },
7aa09196 15816 { "rsr.epc2", 105 /* xt_iclass_rsr.epc2 */,
43cd72b9
BW		 15817 0,
15818 Opcode_rsr_epc2_encode_fns, 0, 0 },
7aa09196 15819 { "wsr.epc2", 106 /* xt_iclass_wsr.epc2 */,
43cd72b9
BW		 15820 0,
15821 Opcode_wsr_epc2_encode_fns, 0, 0 },
7aa09196 15822 { "xsr.epc2", 107 /* xt_iclass_xsr.epc2 */,
43cd72b9
BW		 15823 0,
15824 Opcode_xsr_epc2_encode_fns, 0, 0 },
7aa09196 15825 { "rsr.excsave2", 108 /* xt_iclass_rsr.excsave2 */,
43cd72b9
BW		 15826 0,
15827 Opcode_rsr_excsave2_encode_fns, 0, 0 },
7aa09196 15828 { "wsr.excsave2", 109 /* xt_iclass_wsr.excsave2 */,
43cd72b9
BW		 15829 0,
15830 Opcode_wsr_excsave2_encode_fns, 0, 0 },
7aa09196 15831 { "xsr.excsave2", 110 /* xt_iclass_xsr.excsave2 */,
43cd72b9
BW		 15832 0,
15833 Opcode_xsr_excsave2_encode_fns, 0, 0 },
7aa09196 15834 { "rsr.epc3", 111 /* xt_iclass_rsr.epc3 */,
43cd72b9
BW		 15835 0,
15836 Opcode_rsr_epc3_encode_fns, 0, 0 },
7aa09196 15837 { "wsr.epc3", 112 /* xt_iclass_wsr.epc3 */,
43cd72b9
BW		 15838 0,
15839 Opcode_wsr_epc3_encode_fns, 0, 0 },
7aa09196 15840 { "xsr.epc3", 113 /* xt_iclass_xsr.epc3 */,
43cd72b9
BW		 15841 0,
15842 Opcode_xsr_epc3_encode_fns, 0, 0 },
7aa09196 15843 { "rsr.excsave3", 114 /* xt_iclass_rsr.excsave3 */,
43cd72b9
BW		 15844 0,
15845 Opcode_rsr_excsave3_encode_fns, 0, 0 },
7aa09196 15846 { "wsr.excsave3", 115 /* xt_iclass_wsr.excsave3 */,
43cd72b9
BW		 15847 0,
15848 Opcode_wsr_excsave3_encode_fns, 0, 0 },
7aa09196 15849 { "xsr.excsave3", 116 /* xt_iclass_xsr.excsave3 */,
43cd72b9
BW		 15850 0,
15851 Opcode_xsr_excsave3_encode_fns, 0, 0 },
7aa09196 15852 { "rsr.epc4", 117 /* xt_iclass_rsr.epc4 */,
43cd72b9
BW		 15853 0,
15854 Opcode_rsr_epc4_encode_fns, 0, 0 },
7aa09196 15855 { "wsr.epc4", 118 /* xt_iclass_wsr.epc4 */,
43cd72b9
BW		 15856 0,
15857 Opcode_wsr_epc4_encode_fns, 0, 0 },
7aa09196 15858 { "xsr.epc4", 119 /* xt_iclass_xsr.epc4 */,
43cd72b9
BW		 15859 0,
15860 Opcode_xsr_epc4_encode_fns, 0, 0 },
7aa09196 15861 { "rsr.excsave4", 120 /* xt_iclass_rsr.excsave4 */,
43cd72b9
BW		 15862 0,
15863 Opcode_rsr_excsave4_encode_fns, 0, 0 },
7aa09196 15864 { "wsr.excsave4", 121 /* xt_iclass_wsr.excsave4 */,
43cd72b9
BW		 15865 0,
15866 Opcode_wsr_excsave4_encode_fns, 0, 0 },
7aa09196 15867 { "xsr.excsave4", 122 /* xt_iclass_xsr.excsave4 */,
43cd72b9
BW		 15868 0,
15869 Opcode_xsr_excsave4_encode_fns, 0, 0 },
7aa09196 15870 { "rsr.epc5", 123 /* xt_iclass_rsr.epc5 */,
33430bd0
BW		 15871 0,
15872 Opcode_rsr_epc5_encode_fns, 0, 0 },
7aa09196 15873 { "wsr.epc5", 124 /* xt_iclass_wsr.epc5 */,
33430bd0
BW		 15874 0,
15875 Opcode_wsr_epc5_encode_fns, 0, 0 },
7aa09196 15876 { "xsr.epc5", 125 /* xt_iclass_xsr.epc5 */,
33430bd0
BW		 15877 0,
15878 Opcode_xsr_epc5_encode_fns, 0, 0 },
7aa09196 15879 { "rsr.excsave5", 126 /* xt_iclass_rsr.excsave5 */,
33430bd0
BW		 15880 0,
15881 Opcode_rsr_excsave5_encode_fns, 0, 0 },
7aa09196 15882 { "wsr.excsave5", 127 /* xt_iclass_wsr.excsave5 */,
33430bd0
BW		 15883 0,
15884 Opcode_wsr_excsave5_encode_fns, 0, 0 },
7aa09196 15885 { "xsr.excsave5", 128 /* xt_iclass_xsr.excsave5 */,
33430bd0
BW		 15886 0,
15887 Opcode_xsr_excsave5_encode_fns, 0, 0 },
7aa09196 15888 { "rsr.epc6", 129 /* xt_iclass_rsr.epc6 */,
33430bd0
BW		 15889 0,
15890 Opcode_rsr_epc6_encode_fns, 0, 0 },
7aa09196 15891 { "wsr.epc6", 130 /* xt_iclass_wsr.epc6 */,
33430bd0
BW		 15892 0,
15893 Opcode_wsr_epc6_encode_fns, 0, 0 },
7aa09196 15894 { "xsr.epc6", 131 /* xt_iclass_xsr.epc6 */,
33430bd0
BW		 15895 0,
15896 Opcode_xsr_epc6_encode_fns, 0, 0 },
7aa09196 15897 { "rsr.excsave6", 132 /* xt_iclass_rsr.excsave6 */,
33430bd0
BW		 15898 0,
15899 Opcode_rsr_excsave6_encode_fns, 0, 0 },
7aa09196 15900 { "wsr.excsave6", 133 /* xt_iclass_wsr.excsave6 */,
33430bd0
BW		 15901 0,
15902 Opcode_wsr_excsave6_encode_fns, 0, 0 },
7aa09196 15903 { "xsr.excsave6", 134 /* xt_iclass_xsr.excsave6 */,
33430bd0
BW		 15904 0,
15905 Opcode_xsr_excsave6_encode_fns, 0, 0 },
7aa09196 15906 { "rsr.epc7", 135 /* xt_iclass_rsr.epc7 */,
33430bd0
BW		 15907 0,
15908 Opcode_rsr_epc7_encode_fns, 0, 0 },
7aa09196 15909 { "wsr.epc7", 136 /* xt_iclass_wsr.epc7 */,
33430bd0
BW		 15910 0,
15911 Opcode_wsr_epc7_encode_fns, 0, 0 },
7aa09196 15912 { "xsr.epc7", 137 /* xt_iclass_xsr.epc7 */,
33430bd0
BW		 15913 0,
15914 Opcode_xsr_epc7_encode_fns, 0, 0 },
7aa09196 15915 { "rsr.excsave7", 138 /* xt_iclass_rsr.excsave7 */,
33430bd0
BW		 15916 0,
15917 Opcode_rsr_excsave7_encode_fns, 0, 0 },
7aa09196 15918 { "wsr.excsave7", 139 /* xt_iclass_wsr.excsave7 */,
33430bd0
BW		 15919 0,
15920 Opcode_wsr_excsave7_encode_fns, 0, 0 },
7aa09196 15921 { "xsr.excsave7", 140 /* xt_iclass_xsr.excsave7 */,
33430bd0
BW		 15922 0,
15923 Opcode_xsr_excsave7_encode_fns, 0, 0 },
7aa09196 15924 { "rsr.eps2", 141 /* xt_iclass_rsr.eps2 */,
43cd72b9
BW		 15925 0,
15926 Opcode_rsr_eps2_encode_fns, 0, 0 },
7aa09196 15927 { "wsr.eps2", 142 /* xt_iclass_wsr.eps2 */,
43cd72b9
BW		 15928 0,
15929 Opcode_wsr_eps2_encode_fns, 0, 0 },
7aa09196 15930 { "xsr.eps2", 143 /* xt_iclass_xsr.eps2 */,
43cd72b9
BW		 15931 0,
15932 Opcode_xsr_eps2_encode_fns, 0, 0 },
7aa09196 15933 { "rsr.eps3", 144 /* xt_iclass_rsr.eps3 */,
43cd72b9
BW		 15934 0,
15935 Opcode_rsr_eps3_encode_fns, 0, 0 },
7aa09196 15936 { "wsr.eps3", 145 /* xt_iclass_wsr.eps3 */,
43cd72b9
BW		 15937 0,
15938 Opcode_wsr_eps3_encode_fns, 0, 0 },
7aa09196 15939 { "xsr.eps3", 146 /* xt_iclass_xsr.eps3 */,
43cd72b9
BW		 15940 0,
15941 Opcode_xsr_eps3_encode_fns, 0, 0 },
7aa09196 15942 { "rsr.eps4", 147 /* xt_iclass_rsr.eps4 */,
43cd72b9
BW		 15943 0,
15944 Opcode_rsr_eps4_encode_fns, 0, 0 },
7aa09196 15945 { "wsr.eps4", 148 /* xt_iclass_wsr.eps4 */,
43cd72b9
BW		 15946 0,
15947 Opcode_wsr_eps4_encode_fns, 0, 0 },
7aa09196 15948 { "xsr.eps4", 149 /* xt_iclass_xsr.eps4 */,
43cd72b9
BW		 15949 0,
15950 Opcode_xsr_eps4_encode_fns, 0, 0 },
7aa09196 15951 { "rsr.eps5", 150 /* xt_iclass_rsr.eps5 */,
33430bd0
BW		 15952 0,
15953 Opcode_rsr_eps5_encode_fns, 0, 0 },
7aa09196 15954 { "wsr.eps5", 151 /* xt_iclass_wsr.eps5 */,
33430bd0
BW		 15955 0,
15956 Opcode_wsr_eps5_encode_fns, 0, 0 },
7aa09196 15957 { "xsr.eps5", 152 /* xt_iclass_xsr.eps5 */,
33430bd0
BW		 15958 0,
15959 Opcode_xsr_eps5_encode_fns, 0, 0 },
7aa09196 15960 { "rsr.eps6", 153 /* xt_iclass_rsr.eps6 */,
33430bd0
BW		 15961 0,
15962 Opcode_rsr_eps6_encode_fns, 0, 0 },
7aa09196 15963 { "wsr.eps6", 154 /* xt_iclass_wsr.eps6 */,
33430bd0
BW		 15964 0,
15965 Opcode_wsr_eps6_encode_fns, 0, 0 },
7aa09196 15966 { "xsr.eps6", 155 /* xt_iclass_xsr.eps6 */,
33430bd0
BW		 15967 0,
15968 Opcode_xsr_eps6_encode_fns, 0, 0 },
7aa09196 15969 { "rsr.eps7", 156 /* xt_iclass_rsr.eps7 */,
33430bd0
BW		 15970 0,
15971 Opcode_rsr_eps7_encode_fns, 0, 0 },
7aa09196 15972 { "wsr.eps7", 157 /* xt_iclass_wsr.eps7 */,
33430bd0
BW		 15973 0,
15974 Opcode_wsr_eps7_encode_fns, 0, 0 },
7aa09196 15975 { "xsr.eps7", 158 /* xt_iclass_xsr.eps7 */,
33430bd0
BW		 15976 0,
15977 Opcode_xsr_eps7_encode_fns, 0, 0 },
7aa09196 15978 { "rsr.excvaddr", 159 /* xt_iclass_rsr.excvaddr */,
43cd72b9
BW		 15979 0,
15980 Opcode_rsr_excvaddr_encode_fns, 0, 0 },
7aa09196 15981 { "wsr.excvaddr", 160 /* xt_iclass_wsr.excvaddr */,
43cd72b9
BW		 15982 0,
15983 Opcode_wsr_excvaddr_encode_fns, 0, 0 },
7aa09196 15984 { "xsr.excvaddr", 161 /* xt_iclass_xsr.excvaddr */,
43cd72b9
BW		 15985 0,
15986 Opcode_xsr_excvaddr_encode_fns, 0, 0 },
7aa09196 15987 { "rsr.depc", 162 /* xt_iclass_rsr.depc */,
43cd72b9
BW		 15988 0,
15989 Opcode_rsr_depc_encode_fns, 0, 0 },
7aa09196 15990 { "wsr.depc", 163 /* xt_iclass_wsr.depc */,
43cd72b9
BW		 15991 0,
15992 Opcode_wsr_depc_encode_fns, 0, 0 },
7aa09196 15993 { "xsr.depc", 164 /* xt_iclass_xsr.depc */,
43cd72b9
BW		 15994 0,
15995 Opcode_xsr_depc_encode_fns, 0, 0 },
7aa09196 15996 { "rsr.exccause", 165 /* xt_iclass_rsr.exccause */,
43cd72b9
BW		 15997 0,
15998 Opcode_rsr_exccause_encode_fns, 0, 0 },
7aa09196 15999 { "wsr.exccause", 166 /* xt_iclass_wsr.exccause */,
43cd72b9
BW		 16000 0,
16001 Opcode_wsr_exccause_encode_fns, 0, 0 },
7aa09196 16002 { "xsr.exccause", 167 /* xt_iclass_xsr.exccause */,
43cd72b9
BW		 16003 0,
16004 Opcode_xsr_exccause_encode_fns, 0, 0 },
7aa09196 16005 { "rsr.misc0", 168 /* xt_iclass_rsr.misc0 */,
43cd72b9
BW		 16006 0,
16007 Opcode_rsr_misc0_encode_fns, 0, 0 },
7aa09196 16008 { "wsr.misc0", 169 /* xt_iclass_wsr.misc0 */,
43cd72b9
BW		 16009 0,
16010 Opcode_wsr_misc0_encode_fns, 0, 0 },
7aa09196 16011 { "xsr.misc0", 170 /* xt_iclass_xsr.misc0 */,
43cd72b9
BW		 16012 0,
16013 Opcode_xsr_misc0_encode_fns, 0, 0 },
7aa09196 16014 { "rsr.misc1", 171 /* xt_iclass_rsr.misc1 */,
43cd72b9
BW		 16015 0,
16016 Opcode_rsr_misc1_encode_fns, 0, 0 },
7aa09196 16017 { "wsr.misc1", 172 /* xt_iclass_wsr.misc1 */,
43cd72b9
BW		 16018 0,
16019 Opcode_wsr_misc1_encode_fns, 0, 0 },
7aa09196 16020 { "xsr.misc1", 173 /* xt_iclass_xsr.misc1 */,
43cd72b9
BW		 16021 0,
16022 Opcode_xsr_misc1_encode_fns, 0, 0 },
7aa09196
SA		 16023 { "rsr.misc2", 174 /* xt_iclass_rsr.misc2 */,
16024 0,
16025 Opcode_rsr_misc2_encode_fns, 0, 0 },
16026 { "wsr.misc2", 175 /* xt_iclass_wsr.misc2 */,
16027 0,
16028 Opcode_wsr_misc2_encode_fns, 0, 0 },
16029 { "xsr.misc2", 176 /* xt_iclass_xsr.misc2 */,
16030 0,
16031 Opcode_xsr_misc2_encode_fns, 0, 0 },
16032 { "rsr.misc3", 177 /* xt_iclass_rsr.misc3 */,
16033 0,
16034 Opcode_rsr_misc3_encode_fns, 0, 0 },
16035 { "wsr.misc3", 178 /* xt_iclass_wsr.misc3 */,
16036 0,
16037 Opcode_wsr_misc3_encode_fns, 0, 0 },
16038 { "xsr.misc3", 179 /* xt_iclass_xsr.misc3 */,
16039 0,
16040 Opcode_xsr_misc3_encode_fns, 0, 0 },
16041 { "rsr.prid", 180 /* xt_iclass_rsr.prid */,
43cd72b9
BW		 16042 0,
16043 Opcode_rsr_prid_encode_fns, 0, 0 },
7aa09196 16044 { "rsr.vecbase", 181 /* xt_iclass_rsr.vecbase */,
33430bd0
BW		 16045 0,
16046 Opcode_rsr_vecbase_encode_fns, 0, 0 },
7aa09196 16047 { "wsr.vecbase", 182 /* xt_iclass_wsr.vecbase */,
33430bd0
BW		 16048 0,
16049 Opcode_wsr_vecbase_encode_fns, 0, 0 },
7aa09196 16050 { "xsr.vecbase", 183 /* xt_iclass_xsr.vecbase */,
33430bd0
BW		 16051 0,
16052 Opcode_xsr_vecbase_encode_fns, 0, 0 },
7aa09196
SA		 16053 { "mul.aa.ll", 184 /* xt_iclass_mac16_aa */,
16054 0,
16055 Opcode_mul_aa_ll_encode_fns, 0, 0 },
16056 { "mul.aa.hl", 184 /* xt_iclass_mac16_aa */,
16057 0,
16058 Opcode_mul_aa_hl_encode_fns, 0, 0 },
16059 { "mul.aa.lh", 184 /* xt_iclass_mac16_aa */,
16060 0,
16061 Opcode_mul_aa_lh_encode_fns, 0, 0 },
16062 { "mul.aa.hh", 184 /* xt_iclass_mac16_aa */,
16063 0,
16064 Opcode_mul_aa_hh_encode_fns, 0, 0 },
16065 { "umul.aa.ll", 184 /* xt_iclass_mac16_aa */,
16066 0,
16067 Opcode_umul_aa_ll_encode_fns, 0, 0 },
16068 { "umul.aa.hl", 184 /* xt_iclass_mac16_aa */,
16069 0,
16070 Opcode_umul_aa_hl_encode_fns, 0, 0 },
16071 { "umul.aa.lh", 184 /* xt_iclass_mac16_aa */,
16072 0,
16073 Opcode_umul_aa_lh_encode_fns, 0, 0 },
16074 { "umul.aa.hh", 184 /* xt_iclass_mac16_aa */,
16075 0,
16076 Opcode_umul_aa_hh_encode_fns, 0, 0 },
16077 { "mul.ad.ll", 185 /* xt_iclass_mac16_ad */,
16078 0,
16079 Opcode_mul_ad_ll_encode_fns, 0, 0 },
16080 { "mul.ad.hl", 185 /* xt_iclass_mac16_ad */,
16081 0,
16082 Opcode_mul_ad_hl_encode_fns, 0, 0 },
16083 { "mul.ad.lh", 185 /* xt_iclass_mac16_ad */,
16084 0,
16085 Opcode_mul_ad_lh_encode_fns, 0, 0 },
16086 { "mul.ad.hh", 185 /* xt_iclass_mac16_ad */,
16087 0,
16088 Opcode_mul_ad_hh_encode_fns, 0, 0 },
16089 { "mul.da.ll", 186 /* xt_iclass_mac16_da */,
16090 0,
16091 Opcode_mul_da_ll_encode_fns, 0, 0 },
16092 { "mul.da.hl", 186 /* xt_iclass_mac16_da */,
16093 0,
16094 Opcode_mul_da_hl_encode_fns, 0, 0 },
16095 { "mul.da.lh", 186 /* xt_iclass_mac16_da */,
16096 0,
16097 Opcode_mul_da_lh_encode_fns, 0, 0 },
16098 { "mul.da.hh", 186 /* xt_iclass_mac16_da */,
16099 0,
16100 Opcode_mul_da_hh_encode_fns, 0, 0 },
16101 { "mul.dd.ll", 187 /* xt_iclass_mac16_dd */,
16102 0,
16103 Opcode_mul_dd_ll_encode_fns, 0, 0 },
16104 { "mul.dd.hl", 187 /* xt_iclass_mac16_dd */,
16105 0,
16106 Opcode_mul_dd_hl_encode_fns, 0, 0 },
16107 { "mul.dd.lh", 187 /* xt_iclass_mac16_dd */,
16108 0,
16109 Opcode_mul_dd_lh_encode_fns, 0, 0 },
16110 { "mul.dd.hh", 187 /* xt_iclass_mac16_dd */,
16111 0,
16112 Opcode_mul_dd_hh_encode_fns, 0, 0 },
16113 { "mula.aa.ll", 188 /* xt_iclass_mac16a_aa */,
16114 0,
16115 Opcode_mula_aa_ll_encode_fns, 0, 0 },
16116 { "mula.aa.hl", 188 /* xt_iclass_mac16a_aa */,
16117 0,
16118 Opcode_mula_aa_hl_encode_fns, 0, 0 },
16119 { "mula.aa.lh", 188 /* xt_iclass_mac16a_aa */,
16120 0,
16121 Opcode_mula_aa_lh_encode_fns, 0, 0 },
16122 { "mula.aa.hh", 188 /* xt_iclass_mac16a_aa */,
16123 0,
16124 Opcode_mula_aa_hh_encode_fns, 0, 0 },
16125 { "muls.aa.ll", 188 /* xt_iclass_mac16a_aa */,
16126 0,
16127 Opcode_muls_aa_ll_encode_fns, 0, 0 },
16128 { "muls.aa.hl", 188 /* xt_iclass_mac16a_aa */,
16129 0,
16130 Opcode_muls_aa_hl_encode_fns, 0, 0 },
16131 { "muls.aa.lh", 188 /* xt_iclass_mac16a_aa */,
16132 0,
16133 Opcode_muls_aa_lh_encode_fns, 0, 0 },
16134 { "muls.aa.hh", 188 /* xt_iclass_mac16a_aa */,
16135 0,
16136 Opcode_muls_aa_hh_encode_fns, 0, 0 },
16137 { "mula.ad.ll", 189 /* xt_iclass_mac16a_ad */,
16138 0,
16139 Opcode_mula_ad_ll_encode_fns, 0, 0 },
16140 { "mula.ad.hl", 189 /* xt_iclass_mac16a_ad */,
16141 0,
16142 Opcode_mula_ad_hl_encode_fns, 0, 0 },
16143 { "mula.ad.lh", 189 /* xt_iclass_mac16a_ad */,
16144 0,
16145 Opcode_mula_ad_lh_encode_fns, 0, 0 },
16146 { "mula.ad.hh", 189 /* xt_iclass_mac16a_ad */,
16147 0,
16148 Opcode_mula_ad_hh_encode_fns, 0, 0 },
16149 { "muls.ad.ll", 189 /* xt_iclass_mac16a_ad */,
16150 0,
16151 Opcode_muls_ad_ll_encode_fns, 0, 0 },
16152 { "muls.ad.hl", 189 /* xt_iclass_mac16a_ad */,
16153 0,
16154 Opcode_muls_ad_hl_encode_fns, 0, 0 },
16155 { "muls.ad.lh", 189 /* xt_iclass_mac16a_ad */,
16156 0,
16157 Opcode_muls_ad_lh_encode_fns, 0, 0 },
16158 { "muls.ad.hh", 189 /* xt_iclass_mac16a_ad */,
16159 0,
16160 Opcode_muls_ad_hh_encode_fns, 0, 0 },
16161 { "mula.da.ll", 190 /* xt_iclass_mac16a_da */,
16162 0,
16163 Opcode_mula_da_ll_encode_fns, 0, 0 },
16164 { "mula.da.hl", 190 /* xt_iclass_mac16a_da */,
16165 0,
16166 Opcode_mula_da_hl_encode_fns, 0, 0 },
16167 { "mula.da.lh", 190 /* xt_iclass_mac16a_da */,
16168 0,
16169 Opcode_mula_da_lh_encode_fns, 0, 0 },
16170 { "mula.da.hh", 190 /* xt_iclass_mac16a_da */,
16171 0,
16172 Opcode_mula_da_hh_encode_fns, 0, 0 },
16173 { "muls.da.ll", 190 /* xt_iclass_mac16a_da */,
16174 0,
16175 Opcode_muls_da_ll_encode_fns, 0, 0 },
16176 { "muls.da.hl", 190 /* xt_iclass_mac16a_da */,
16177 0,
16178 Opcode_muls_da_hl_encode_fns, 0, 0 },
16179 { "muls.da.lh", 190 /* xt_iclass_mac16a_da */,
16180 0,
16181 Opcode_muls_da_lh_encode_fns, 0, 0 },
16182 { "muls.da.hh", 190 /* xt_iclass_mac16a_da */,
16183 0,
16184 Opcode_muls_da_hh_encode_fns, 0, 0 },
16185 { "mula.dd.ll", 191 /* xt_iclass_mac16a_dd */,
16186 0,
16187 Opcode_mula_dd_ll_encode_fns, 0, 0 },
16188 { "mula.dd.hl", 191 /* xt_iclass_mac16a_dd */,
16189 0,
16190 Opcode_mula_dd_hl_encode_fns, 0, 0 },
16191 { "mula.dd.lh", 191 /* xt_iclass_mac16a_dd */,
16192 0,
16193 Opcode_mula_dd_lh_encode_fns, 0, 0 },
16194 { "mula.dd.hh", 191 /* xt_iclass_mac16a_dd */,
16195 0,
16196 Opcode_mula_dd_hh_encode_fns, 0, 0 },
16197 { "muls.dd.ll", 191 /* xt_iclass_mac16a_dd */,
16198 0,
16199 Opcode_muls_dd_ll_encode_fns, 0, 0 },
16200 { "muls.dd.hl", 191 /* xt_iclass_mac16a_dd */,
16201 0,
16202 Opcode_muls_dd_hl_encode_fns, 0, 0 },
16203 { "muls.dd.lh", 191 /* xt_iclass_mac16a_dd */,
16204 0,
16205 Opcode_muls_dd_lh_encode_fns, 0, 0 },
16206 { "muls.dd.hh", 191 /* xt_iclass_mac16a_dd */,
16207 0,
16208 Opcode_muls_dd_hh_encode_fns, 0, 0 },
16209 { "mula.da.ll.lddec", 192 /* xt_iclass_mac16al_da */,
16210 0,
16211 Opcode_mula_da_ll_lddec_encode_fns, 0, 0 },
16212 { "mula.da.ll.ldinc", 192 /* xt_iclass_mac16al_da */,
16213 0,
16214 Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 },
16215 { "mula.da.hl.lddec", 192 /* xt_iclass_mac16al_da */,
16216 0,
16217 Opcode_mula_da_hl_lddec_encode_fns, 0, 0 },
16218 { "mula.da.hl.ldinc", 192 /* xt_iclass_mac16al_da */,
16219 0,
16220 Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 },
16221 { "mula.da.lh.lddec", 192 /* xt_iclass_mac16al_da */,
16222 0,
16223 Opcode_mula_da_lh_lddec_encode_fns, 0, 0 },
16224 { "mula.da.lh.ldinc", 192 /* xt_iclass_mac16al_da */,
16225 0,
16226 Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 },
16227 { "mula.da.hh.lddec", 192 /* xt_iclass_mac16al_da */,
16228 0,
16229 Opcode_mula_da_hh_lddec_encode_fns, 0, 0 },
16230 { "mula.da.hh.ldinc", 192 /* xt_iclass_mac16al_da */,
16231 0,
16232 Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 },
16233 { "mula.dd.ll.lddec", 193 /* xt_iclass_mac16al_dd */,
16234 0,
16235 Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 },
16236 { "mula.dd.ll.ldinc", 193 /* xt_iclass_mac16al_dd */,
16237 0,
16238 Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 },
16239 { "mula.dd.hl.lddec", 193 /* xt_iclass_mac16al_dd */,
16240 0,
16241 Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 },
16242 { "mula.dd.hl.ldinc", 193 /* xt_iclass_mac16al_dd */,
16243 0,
16244 Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 },
16245 { "mula.dd.lh.lddec", 193 /* xt_iclass_mac16al_dd */,
16246 0,
16247 Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 },
16248 { "mula.dd.lh.ldinc", 193 /* xt_iclass_mac16al_dd */,
16249 0,
16250 Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 },
16251 { "mula.dd.hh.lddec", 193 /* xt_iclass_mac16al_dd */,
16252 0,
16253 Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 },
16254 { "mula.dd.hh.ldinc", 193 /* xt_iclass_mac16al_dd */,
16255 0,
16256 Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 },
16257 { "lddec", 194 /* xt_iclass_mac16_l */,
16258 0,
16259 Opcode_lddec_encode_fns, 0, 0 },
16260 { "ldinc", 194 /* xt_iclass_mac16_l */,
16261 0,
16262 Opcode_ldinc_encode_fns, 0, 0 },
16263 { "mul16u", 195 /* xt_iclass_mul16 */,
33430bd0
BW		 16264 0,
16265 Opcode_mul16u_encode_fns, 0, 0 },
7aa09196 16266 { "mul16s", 195 /* xt_iclass_mul16 */,
33430bd0
BW		 16267 0,
16268 Opcode_mul16s_encode_fns, 0, 0 },
7aa09196
SA		 16269 { "rsr.m0", 196 /* xt_iclass_rsr.m0 */,
16270 0,
16271 Opcode_rsr_m0_encode_fns, 0, 0 },
16272 { "wsr.m0", 197 /* xt_iclass_wsr.m0 */,
16273 0,
16274 Opcode_wsr_m0_encode_fns, 0, 0 },
16275 { "xsr.m0", 198 /* xt_iclass_xsr.m0 */,
16276 0,
16277 Opcode_xsr_m0_encode_fns, 0, 0 },
16278 { "rsr.m1", 199 /* xt_iclass_rsr.m1 */,
16279 0,
16280 Opcode_rsr_m1_encode_fns, 0, 0 },
16281 { "wsr.m1", 200 /* xt_iclass_wsr.m1 */,
16282 0,
16283 Opcode_wsr_m1_encode_fns, 0, 0 },
16284 { "xsr.m1", 201 /* xt_iclass_xsr.m1 */,
16285 0,
16286 Opcode_xsr_m1_encode_fns, 0, 0 },
16287 { "rsr.m2", 202 /* xt_iclass_rsr.m2 */,
16288 0,
16289 Opcode_rsr_m2_encode_fns, 0, 0 },
16290 { "wsr.m2", 203 /* xt_iclass_wsr.m2 */,
16291 0,
16292 Opcode_wsr_m2_encode_fns, 0, 0 },
16293 { "xsr.m2", 204 /* xt_iclass_xsr.m2 */,
16294 0,
16295 Opcode_xsr_m2_encode_fns, 0, 0 },
16296 { "rsr.m3", 205 /* xt_iclass_rsr.m3 */,
16297 0,
16298 Opcode_rsr_m3_encode_fns, 0, 0 },
16299 { "wsr.m3", 206 /* xt_iclass_wsr.m3 */,
16300 0,
16301 Opcode_wsr_m3_encode_fns, 0, 0 },
16302 { "xsr.m3", 207 /* xt_iclass_xsr.m3 */,
16303 0,
16304 Opcode_xsr_m3_encode_fns, 0, 0 },
16305 { "rsr.acclo", 208 /* xt_iclass_rsr.acclo */,
16306 0,
16307 Opcode_rsr_acclo_encode_fns, 0, 0 },
16308 { "wsr.acclo", 209 /* xt_iclass_wsr.acclo */,
16309 0,
16310 Opcode_wsr_acclo_encode_fns, 0, 0 },
16311 { "xsr.acclo", 210 /* xt_iclass_xsr.acclo */,
16312 0,
16313 Opcode_xsr_acclo_encode_fns, 0, 0 },
16314 { "rsr.acchi", 211 /* xt_iclass_rsr.acchi */,
16315 0,
16316 Opcode_rsr_acchi_encode_fns, 0, 0 },
16317 { "wsr.acchi", 212 /* xt_iclass_wsr.acchi */,
16318 0,
16319 Opcode_wsr_acchi_encode_fns, 0, 0 },
16320 { "xsr.acchi", 213 /* xt_iclass_xsr.acchi */,
16321 0,
16322 Opcode_xsr_acchi_encode_fns, 0, 0 },
16323 { "rfi", 214 /* xt_iclass_rfi */,
43cd72b9
BW		 16324 XTENSA_OPCODE_IS_JUMP,
16325 Opcode_rfi_encode_fns, 0, 0 },
7aa09196 16326 { "waiti", 215 /* xt_iclass_wait */,
43cd72b9
BW		 16327 0,
16328 Opcode_waiti_encode_fns, 0, 0 },
7aa09196 16329 { "rsr.interrupt", 216 /* xt_iclass_rsr.interrupt */,
43cd72b9
BW		 16330 0,
16331 Opcode_rsr_interrupt_encode_fns, 0, 0 },
7aa09196 16332 { "wsr.intset", 217 /* xt_iclass_wsr.intset */,
43cd72b9
BW		 16333 0,
16334 Opcode_wsr_intset_encode_fns, 0, 0 },
7aa09196 16335 { "wsr.intclear", 218 /* xt_iclass_wsr.intclear */,
43cd72b9
BW		 16336 0,
16337 Opcode_wsr_intclear_encode_fns, 0, 0 },
7aa09196 16338 { "rsr.intenable", 219 /* xt_iclass_rsr.intenable */,
43cd72b9
BW		 16339 0,
16340 Opcode_rsr_intenable_encode_fns, 0, 0 },
7aa09196 16341 { "wsr.intenable", 220 /* xt_iclass_wsr.intenable */,
43cd72b9
BW		 16342 0,
16343 Opcode_wsr_intenable_encode_fns, 0, 0 },
7aa09196 16344 { "xsr.intenable", 221 /* xt_iclass_xsr.intenable */,
43cd72b9
BW		 16345 0,
16346 Opcode_xsr_intenable_encode_fns, 0, 0 },
7aa09196 16347 { "break", 222 /* xt_iclass_break */,
43cd72b9
BW		 16348 0,
16349 Opcode_break_encode_fns, 0, 0 },
7aa09196 16350 { "break.n", 223 /* xt_iclass_break.n */,
43cd72b9
BW		 16351 0,
16352 Opcode_break_n_encode_fns, 0, 0 },
7aa09196 16353 { "rsr.dbreaka0", 224 /* xt_iclass_rsr.dbreaka0 */,
43cd72b9
BW		 16354 0,
16355 Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
7aa09196 16356 { "wsr.dbreaka0", 225 /* xt_iclass_wsr.dbreaka0 */,
43cd72b9
BW		 16357 0,
16358 Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
7aa09196 16359 { "xsr.dbreaka0", 226 /* xt_iclass_xsr.dbreaka0 */,
43cd72b9
BW		 16360 0,
16361 Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
7aa09196 16362 { "rsr.dbreakc0", 227 /* xt_iclass_rsr.dbreakc0 */,
43cd72b9
BW		 16363 0,
16364 Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
7aa09196 16365 { "wsr.dbreakc0", 228 /* xt_iclass_wsr.dbreakc0 */,
43cd72b9
BW		 16366 0,
16367 Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
7aa09196 16368 { "xsr.dbreakc0", 229 /* xt_iclass_xsr.dbreakc0 */,
43cd72b9
BW		 16369 0,
16370 Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
7aa09196 16371 { "rsr.dbreaka1", 230 /* xt_iclass_rsr.dbreaka1 */,
43cd72b9
BW		 16372 0,
16373 Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
7aa09196 16374 { "wsr.dbreaka1", 231 /* xt_iclass_wsr.dbreaka1 */,
43cd72b9
BW		 16375 0,
16376 Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
7aa09196 16377 { "xsr.dbreaka1", 232 /* xt_iclass_xsr.dbreaka1 */,
43cd72b9
BW		 16378 0,
16379 Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
7aa09196 16380 { "rsr.dbreakc1", 233 /* xt_iclass_rsr.dbreakc1 */,
43cd72b9
BW		 16381 0,
16382 Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
7aa09196 16383 { "wsr.dbreakc1", 234 /* xt_iclass_wsr.dbreakc1 */,
43cd72b9
BW		 16384 0,
16385 Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
7aa09196 16386 { "xsr.dbreakc1", 235 /* xt_iclass_xsr.dbreakc1 */,
43cd72b9
BW		 16387 0,
16388 Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
7aa09196 16389 { "rsr.ibreaka0", 236 /* xt_iclass_rsr.ibreaka0 */,
43cd72b9
BW		 16390 0,
16391 Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
7aa09196 16392 { "wsr.ibreaka0", 237 /* xt_iclass_wsr.ibreaka0 */,
43cd72b9
BW		 16393 0,
16394 Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
7aa09196 16395 { "xsr.ibreaka0", 238 /* xt_iclass_xsr.ibreaka0 */,
43cd72b9
BW		 16396 0,
16397 Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
7aa09196 16398 { "rsr.ibreaka1", 239 /* xt_iclass_rsr.ibreaka1 */,
43cd72b9
BW		 16399 0,
16400 Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
7aa09196 16401 { "wsr.ibreaka1", 240 /* xt_iclass_wsr.ibreaka1 */,
43cd72b9
BW		 16402 0,
16403 Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
7aa09196 16404 { "xsr.ibreaka1", 241 /* xt_iclass_xsr.ibreaka1 */,
43cd72b9
BW		 16405 0,
16406 Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
7aa09196 16407 { "rsr.ibreakenable", 242 /* xt_iclass_rsr.ibreakenable */,
43cd72b9
BW		 16408 0,
16409 Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
7aa09196 16410 { "wsr.ibreakenable", 243 /* xt_iclass_wsr.ibreakenable */,
43cd72b9
BW		 16411 0,
16412 Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
7aa09196 16413 { "xsr.ibreakenable", 244 /* xt_iclass_xsr.ibreakenable */,
43cd72b9
BW		 16414 0,
16415 Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
7aa09196 16416 { "rsr.debugcause", 245 /* xt_iclass_rsr.debugcause */,
43cd72b9
BW		 16417 0,
16418 Opcode_rsr_debugcause_encode_fns, 0, 0 },
7aa09196 16419 { "wsr.debugcause", 246 /* xt_iclass_wsr.debugcause */,
43cd72b9
BW		 16420 0,
16421 Opcode_wsr_debugcause_encode_fns, 0, 0 },
7aa09196 16422 { "xsr.debugcause", 247 /* xt_iclass_xsr.debugcause */,
43cd72b9
BW		 16423 0,
16424 Opcode_xsr_debugcause_encode_fns, 0, 0 },
7aa09196 16425 { "rsr.icount", 248 /* xt_iclass_rsr.icount */,
43cd72b9
BW		 16426 0,
16427 Opcode_rsr_icount_encode_fns, 0, 0 },
7aa09196 16428 { "wsr.icount", 249 /* xt_iclass_wsr.icount */,
43cd72b9
BW		 16429 0,
16430 Opcode_wsr_icount_encode_fns, 0, 0 },
7aa09196 16431 { "xsr.icount", 250 /* xt_iclass_xsr.icount */,
43cd72b9
BW		 16432 0,
16433 Opcode_xsr_icount_encode_fns, 0, 0 },
7aa09196 16434 { "rsr.icountlevel", 251 /* xt_iclass_rsr.icountlevel */,
43cd72b9
BW		 16435 0,
16436 Opcode_rsr_icountlevel_encode_fns, 0, 0 },
7aa09196 16437 { "wsr.icountlevel", 252 /* xt_iclass_wsr.icountlevel */,
43cd72b9
BW		 16438 0,
16439 Opcode_wsr_icountlevel_encode_fns, 0, 0 },
7aa09196 16440 { "xsr.icountlevel", 253 /* xt_iclass_xsr.icountlevel */,
43cd72b9
BW		 16441 0,
16442 Opcode_xsr_icountlevel_encode_fns, 0, 0 },
7aa09196 16443 { "rsr.ddr", 254 /* xt_iclass_rsr.ddr */,
43cd72b9
BW		 16444 0,
16445 Opcode_rsr_ddr_encode_fns, 0, 0 },
7aa09196 16446 { "wsr.ddr", 255 /* xt_iclass_wsr.ddr */,
43cd72b9
BW		 16447 0,
16448 Opcode_wsr_ddr_encode_fns, 0, 0 },
7aa09196 16449 { "xsr.ddr", 256 /* xt_iclass_xsr.ddr */,
43cd72b9
BW		 16450 0,
16451 Opcode_xsr_ddr_encode_fns, 0, 0 },
7aa09196 16452 { "rfdo", 257 /* xt_iclass_rfdo */,
43cd72b9
BW		 16453 XTENSA_OPCODE_IS_JUMP,
16454 Opcode_rfdo_encode_fns, 0, 0 },
7aa09196 16455 { "rfdd", 258 /* xt_iclass_rfdd */,
43cd72b9
BW		 16456 XTENSA_OPCODE_IS_JUMP,
16457 Opcode_rfdd_encode_fns, 0, 0 },
7aa09196 16458 { "wsr.mmid", 259 /* xt_iclass_wsr.mmid */,
33430bd0
BW		 16459 0,
16460 Opcode_wsr_mmid_encode_fns, 0, 0 },
7aa09196
SA		 16461 { "andb", 260 /* xt_iclass_bbool1 */,
16462 0,
16463 Opcode_andb_encode_fns, 0, 0 },
16464 { "andbc", 260 /* xt_iclass_bbool1 */,
16465 0,
16466 Opcode_andbc_encode_fns, 0, 0 },
16467 { "orb", 260 /* xt_iclass_bbool1 */,
16468 0,
16469 Opcode_orb_encode_fns, 0, 0 },
16470 { "orbc", 260 /* xt_iclass_bbool1 */,
16471 0,
16472 Opcode_orbc_encode_fns, 0, 0 },
16473 { "xorb", 260 /* xt_iclass_bbool1 */,
16474 0,
16475 Opcode_xorb_encode_fns, 0, 0 },
16476 { "any4", 261 /* xt_iclass_bbool4 */,
16477 0,
16478 Opcode_any4_encode_fns, 0, 0 },
16479 { "all4", 261 /* xt_iclass_bbool4 */,
16480 0,
16481 Opcode_all4_encode_fns, 0, 0 },
16482 { "any8", 262 /* xt_iclass_bbool8 */,
16483 0,
16484 Opcode_any8_encode_fns, 0, 0 },
16485 { "all8", 262 /* xt_iclass_bbool8 */,
16486 0,
16487 Opcode_all8_encode_fns, 0, 0 },
16488 { "bf", 263 /* xt_iclass_bbranch */,
16489 XTENSA_OPCODE_IS_BRANCH,
16490 Opcode_bf_encode_fns, 0, 0 },
16491 { "bt", 263 /* xt_iclass_bbranch */,
16492 XTENSA_OPCODE_IS_BRANCH,
16493 Opcode_bt_encode_fns, 0, 0 },
16494 { "movf", 264 /* xt_iclass_bmove */,
16495 0,
16496 Opcode_movf_encode_fns, 0, 0 },
16497 { "movt", 264 /* xt_iclass_bmove */,
16498 0,
16499 Opcode_movt_encode_fns, 0, 0 },
16500 { "rsr.br", 265 /* xt_iclass_RSR.BR */,
16501 0,
16502 Opcode_rsr_br_encode_fns, 0, 0 },
16503 { "wsr.br", 266 /* xt_iclass_WSR.BR */,
16504 0,
16505 Opcode_wsr_br_encode_fns, 0, 0 },
16506 { "xsr.br", 267 /* xt_iclass_XSR.BR */,
16507 0,
16508 Opcode_xsr_br_encode_fns, 0, 0 },
16509 { "rsr.ccount", 268 /* xt_iclass_rsr.ccount */,
43cd72b9
BW		 16510 0,
16511 Opcode_rsr_ccount_encode_fns, 0, 0 },
7aa09196 16512 { "wsr.ccount", 269 /* xt_iclass_wsr.ccount */,
43cd72b9
BW		 16513 0,
16514 Opcode_wsr_ccount_encode_fns, 0, 0 },
7aa09196 16515 { "xsr.ccount", 270 /* xt_iclass_xsr.ccount */,
43cd72b9
BW		 16516 0,
16517 Opcode_xsr_ccount_encode_fns, 0, 0 },
7aa09196 16518 { "rsr.ccompare0", 271 /* xt_iclass_rsr.ccompare0 */,
43cd72b9
BW		 16519 0,
16520 Opcode_rsr_ccompare0_encode_fns, 0, 0 },
7aa09196 16521 { "wsr.ccompare0", 272 /* xt_iclass_wsr.ccompare0 */,
43cd72b9
BW		 16522 0,
16523 Opcode_wsr_ccompare0_encode_fns, 0, 0 },
7aa09196 16524 { "xsr.ccompare0", 273 /* xt_iclass_xsr.ccompare0 */,
43cd72b9
BW		 16525 0,
16526 Opcode_xsr_ccompare0_encode_fns, 0, 0 },
7aa09196 16527 { "rsr.ccompare1", 274 /* xt_iclass_rsr.ccompare1 */,
43cd72b9
BW		 16528 0,
16529 Opcode_rsr_ccompare1_encode_fns, 0, 0 },
7aa09196 16530 { "wsr.ccompare1", 275 /* xt_iclass_wsr.ccompare1 */,
43cd72b9
BW		 16531 0,
16532 Opcode_wsr_ccompare1_encode_fns, 0, 0 },
7aa09196 16533 { "xsr.ccompare1", 276 /* xt_iclass_xsr.ccompare1 */,
43cd72b9
BW		 16534 0,
16535 Opcode_xsr_ccompare1_encode_fns, 0, 0 },
7aa09196 16536 { "rsr.ccompare2", 277 /* xt_iclass_rsr.ccompare2 */,
43cd72b9
BW		 16537 0,
16538 Opcode_rsr_ccompare2_encode_fns, 0, 0 },
7aa09196 16539 { "wsr.ccompare2", 278 /* xt_iclass_wsr.ccompare2 */,
43cd72b9
BW		 16540 0,
16541 Opcode_wsr_ccompare2_encode_fns, 0, 0 },
7aa09196 16542 { "xsr.ccompare2", 279 /* xt_iclass_xsr.ccompare2 */,
43cd72b9
BW		 16543 0,
16544 Opcode_xsr_ccompare2_encode_fns, 0, 0 },
7aa09196 16545 { "ipf", 280 /* xt_iclass_icache */,
43cd72b9
BW		 16546 0,
16547 Opcode_ipf_encode_fns, 0, 0 },
7aa09196 16548 { "ihi", 280 /* xt_iclass_icache */,
43cd72b9
BW		 16549 0,
16550 Opcode_ihi_encode_fns, 0, 0 },
7aa09196 16551 { "ipfl", 281 /* xt_iclass_icache_lock */,
33430bd0
BW		 16552 0,
16553 Opcode_ipfl_encode_fns, 0, 0 },
7aa09196 16554 { "ihu", 281 /* xt_iclass_icache_lock */,
33430bd0
BW		 16555 0,
16556 Opcode_ihu_encode_fns, 0, 0 },
7aa09196 16557 { "iiu", 281 /* xt_iclass_icache_lock */,
33430bd0
BW		 16558 0,
16559 Opcode_iiu_encode_fns, 0, 0 },
7aa09196 16560 { "iii", 282 /* xt_iclass_icache_inv */,
43cd72b9
BW		 16561 0,
16562 Opcode_iii_encode_fns, 0, 0 },
7aa09196 16563 { "lict", 283 /* xt_iclass_licx */,
43cd72b9
BW		 16564 0,
16565 Opcode_lict_encode_fns, 0, 0 },
7aa09196 16566 { "licw", 283 /* xt_iclass_licx */,
43cd72b9
BW		 16567 0,
16568 Opcode_licw_encode_fns, 0, 0 },
7aa09196 16569 { "sict", 284 /* xt_iclass_sicx */,
43cd72b9
BW		 16570 0,
16571 Opcode_sict_encode_fns, 0, 0 },
7aa09196 16572 { "sicw", 284 /* xt_iclass_sicx */,
43cd72b9
BW		 16573 0,
16574 Opcode_sicw_encode_fns, 0, 0 },
7aa09196 16575 { "dhwb", 285 /* xt_iclass_dcache */,
43cd72b9
BW		 16576 0,
16577 Opcode_dhwb_encode_fns, 0, 0 },
7aa09196 16578 { "dhwbi", 285 /* xt_iclass_dcache */,
43cd72b9
BW		 16579 0,
16580 Opcode_dhwbi_encode_fns, 0, 0 },
7aa09196 16581 { "diwb", 286 /* xt_iclass_dcache_ind */,
43cd72b9
BW		 16582 0,
16583 Opcode_diwb_encode_fns, 0, 0 },
7aa09196 16584 { "diwbi", 286 /* xt_iclass_dcache_ind */,
43cd72b9
BW		 16585 0,
16586 Opcode_diwbi_encode_fns, 0, 0 },
7aa09196 16587 { "dhi", 287 /* xt_iclass_dcache_inv */,
43cd72b9
BW		 16588 0,
16589 Opcode_dhi_encode_fns, 0, 0 },
7aa09196 16590 { "dii", 287 /* xt_iclass_dcache_inv */,
43cd72b9
BW		 16591 0,
16592 Opcode_dii_encode_fns, 0, 0 },
7aa09196 16593 { "dpfr", 288 /* xt_iclass_dpf */,
43cd72b9
BW		 16594 0,
16595 Opcode_dpfr_encode_fns, 0, 0 },
7aa09196 16596 { "dpfw", 288 /* xt_iclass_dpf */,
43cd72b9
BW		 16597 0,
16598 Opcode_dpfw_encode_fns, 0, 0 },
7aa09196 16599 { "dpfro", 288 /* xt_iclass_dpf */,
43cd72b9
BW		 16600 0,
16601 Opcode_dpfro_encode_fns, 0, 0 },
7aa09196 16602 { "dpfwo", 288 /* xt_iclass_dpf */,
43cd72b9
BW		 16603 0,
16604 Opcode_dpfwo_encode_fns, 0, 0 },
7aa09196 16605 { "dpfl", 289 /* xt_iclass_dcache_lock */,
33430bd0
BW		 16606 0,
16607 Opcode_dpfl_encode_fns, 0, 0 },
7aa09196 16608 { "dhu", 289 /* xt_iclass_dcache_lock */,
33430bd0
BW		 16609 0,
16610 Opcode_dhu_encode_fns, 0, 0 },
7aa09196 16611 { "diu", 289 /* xt_iclass_dcache_lock */,
33430bd0
BW		 16612 0,
16613 Opcode_diu_encode_fns, 0, 0 },
7aa09196 16614 { "sdct", 290 /* xt_iclass_sdct */,
43cd72b9
BW		 16615 0,
16616 Opcode_sdct_encode_fns, 0, 0 },
7aa09196 16617 { "ldct", 291 /* xt_iclass_ldct */,
43cd72b9
BW		 16618 0,
16619 Opcode_ldct_encode_fns, 0, 0 },
7aa09196 16620 { "wsr.ptevaddr", 292 /* xt_iclass_wsr.ptevaddr */,
074f5109
BW		 16621 0,
16622 Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
7aa09196 16623 { "rsr.ptevaddr", 293 /* xt_iclass_rsr.ptevaddr */,
074f5109
BW		 16624 0,
16625 Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
7aa09196 16626 { "xsr.ptevaddr", 294 /* xt_iclass_xsr.ptevaddr */,
074f5109
BW		 16627 0,
16628 Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
7aa09196 16629 { "rsr.rasid", 295 /* xt_iclass_rsr.rasid */,
074f5109
BW		 16630 0,
16631 Opcode_rsr_rasid_encode_fns, 0, 0 },
7aa09196 16632 { "wsr.rasid", 296 /* xt_iclass_wsr.rasid */,
074f5109
BW		 16633 0,
16634 Opcode_wsr_rasid_encode_fns, 0, 0 },
7aa09196 16635 { "xsr.rasid", 297 /* xt_iclass_xsr.rasid */,
074f5109
BW		 16636 0,
16637 Opcode_xsr_rasid_encode_fns, 0, 0 },
7aa09196 16638 { "rsr.itlbcfg", 298 /* xt_iclass_rsr.itlbcfg */,
074f5109
BW		 16639 0,
16640 Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
7aa09196 16641 { "wsr.itlbcfg", 299 /* xt_iclass_wsr.itlbcfg */,
074f5109
BW		 16642 0,
16643 Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
7aa09196 16644 { "xsr.itlbcfg", 300 /* xt_iclass_xsr.itlbcfg */,
074f5109
BW		 16645 0,
16646 Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
7aa09196 16647 { "rsr.dtlbcfg", 301 /* xt_iclass_rsr.dtlbcfg */,
074f5109
BW		 16648 0,
16649 Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
7aa09196 16650 { "wsr.dtlbcfg", 302 /* xt_iclass_wsr.dtlbcfg */,
074f5109
BW		 16651 0,
16652 Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
7aa09196 16653 { "xsr.dtlbcfg", 303 /* xt_iclass_xsr.dtlbcfg */,
074f5109
BW		 16654 0,
16655 Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
7aa09196 16656 { "idtlb", 304 /* xt_iclass_idtlb */,
43cd72b9
BW		 16657 0,
16658 Opcode_idtlb_encode_fns, 0, 0 },
7aa09196 16659 { "pdtlb", 305 /* xt_iclass_rdtlb */,
43cd72b9
BW		 16660 0,
16661 Opcode_pdtlb_encode_fns, 0, 0 },
7aa09196 16662 { "rdtlb0", 305 /* xt_iclass_rdtlb */,
43cd72b9
BW		 16663 0,
16664 Opcode_rdtlb0_encode_fns, 0, 0 },
7aa09196 16665 { "rdtlb1", 305 /* xt_iclass_rdtlb */,
43cd72b9
BW		 16666 0,
16667 Opcode_rdtlb1_encode_fns, 0, 0 },
7aa09196 16668 { "wdtlb", 306 /* xt_iclass_wdtlb */,
43cd72b9
BW		 16669 0,
16670 Opcode_wdtlb_encode_fns, 0, 0 },
7aa09196 16671 { "iitlb", 307 /* xt_iclass_iitlb */,
43cd72b9
BW		 16672 0,
16673 Opcode_iitlb_encode_fns, 0, 0 },
7aa09196 16674 { "pitlb", 308 /* xt_iclass_ritlb */,
43cd72b9
BW		 16675 0,
16676 Opcode_pitlb_encode_fns, 0, 0 },
7aa09196 16677 { "ritlb0", 308 /* xt_iclass_ritlb */,
43cd72b9
BW		 16678 0,
16679 Opcode_ritlb0_encode_fns, 0, 0 },
7aa09196 16680 { "ritlb1", 308 /* xt_iclass_ritlb */,
43cd72b9
BW		 16681 0,
16682 Opcode_ritlb1_encode_fns, 0, 0 },
7aa09196 16683 { "witlb", 309 /* xt_iclass_witlb */,
43cd72b9
BW		 16684 0,
16685 Opcode_witlb_encode_fns, 0, 0 },
7aa09196 16686 { "ldpte", 310 /* xt_iclass_ldpte */,
074f5109
BW		 16687 0,
16688 Opcode_ldpte_encode_fns, 0, 0 },
7aa09196 16689 { "hwwitlba", 311 /* xt_iclass_hwwitlba */,
074f5109
BW		 16690 XTENSA_OPCODE_IS_BRANCH,
16691 Opcode_hwwitlba_encode_fns, 0, 0 },
7aa09196 16692 { "hwwdtlba", 312 /* xt_iclass_hwwdtlba */,
074f5109
BW		 16693 0,
16694 Opcode_hwwdtlba_encode_fns, 0, 0 },
7aa09196 16695 { "rsr.cpenable", 313 /* xt_iclass_rsr.cpenable */,
33430bd0
BW		 16696 0,
16697 Opcode_rsr_cpenable_encode_fns, 0, 0 },
7aa09196 16698 { "wsr.cpenable", 314 /* xt_iclass_wsr.cpenable */,
33430bd0
BW		 16699 0,
16700 Opcode_wsr_cpenable_encode_fns, 0, 0 },
7aa09196 16701 { "xsr.cpenable", 315 /* xt_iclass_xsr.cpenable */,
33430bd0
BW		 16702 0,
16703 Opcode_xsr_cpenable_encode_fns, 0, 0 },
7aa09196 16704 { "clamps", 316 /* xt_iclass_clamp */,
33430bd0
BW		 16705 0,
16706 Opcode_clamps_encode_fns, 0, 0 },
7aa09196 16707 { "min", 317 /* xt_iclass_minmax */,
33430bd0
BW		 16708 0,
16709 Opcode_min_encode_fns, 0, 0 },
7aa09196 16710 { "max", 317 /* xt_iclass_minmax */,
33430bd0
BW		 16711 0,
16712 Opcode_max_encode_fns, 0, 0 },
7aa09196 16713 { "minu", 317 /* xt_iclass_minmax */,
33430bd0
BW		 16714 0,
16715 Opcode_minu_encode_fns, 0, 0 },
7aa09196 16716 { "maxu", 317 /* xt_iclass_minmax */,
33430bd0
BW		 16717 0,
16718 Opcode_maxu_encode_fns, 0, 0 },
7aa09196 16719 { "nsa", 318 /* xt_iclass_nsa */,
43cd72b9
BW		 16720 0,
16721 Opcode_nsa_encode_fns, 0, 0 },
7aa09196 16722 { "nsau", 318 /* xt_iclass_nsa */,
43cd72b9 16723 0,
33430bd0 16724 Opcode_nsau_encode_fns, 0, 0 },
7aa09196 16725 { "sext", 319 /* xt_iclass_sx */,
33430bd0
BW		 16726 0,
16727 Opcode_sext_encode_fns, 0, 0 },
7aa09196 16728 { "l32ai", 320 /* xt_iclass_l32ai */,
33430bd0
BW		 16729 0,
16730 Opcode_l32ai_encode_fns, 0, 0 },
7aa09196 16731 { "s32ri", 321 /* xt_iclass_s32ri */,
33430bd0
BW		 16732 0,
16733 Opcode_s32ri_encode_fns, 0, 0 },
7aa09196 16734 { "s32c1i", 322 /* xt_iclass_s32c1i */,
33430bd0
BW		 16735 0,
16736 Opcode_s32c1i_encode_fns, 0, 0 },
7aa09196 16737 { "rsr.scompare1", 323 /* xt_iclass_rsr.scompare1 */,
33430bd0
BW		 16738 0,
16739 Opcode_rsr_scompare1_encode_fns, 0, 0 },
7aa09196 16740 { "wsr.scompare1", 324 /* xt_iclass_wsr.scompare1 */,
33430bd0
BW		 16741 0,
16742 Opcode_wsr_scompare1_encode_fns, 0, 0 },
7aa09196 16743 { "xsr.scompare1", 325 /* xt_iclass_xsr.scompare1 */,
33430bd0
BW		 16744 0,
16745 Opcode_xsr_scompare1_encode_fns, 0, 0 },
7aa09196 16746 { "quou", 326 /* xt_iclass_div */,
33430bd0
BW		 16747 0,
16748 Opcode_quou_encode_fns, 0, 0 },
7aa09196 16749 { "quos", 326 /* xt_iclass_div */,
33430bd0
BW		 16750 0,
16751 Opcode_quos_encode_fns, 0, 0 },
7aa09196 16752 { "remu", 326 /* xt_iclass_div */,
33430bd0
BW		 16753 0,
16754 Opcode_remu_encode_fns, 0, 0 },
7aa09196 16755 { "rems", 326 /* xt_iclass_div */,
33430bd0
BW		 16756 0,
16757 Opcode_rems_encode_fns, 0, 0 },
7aa09196
SA		 16758 { "mull", 327 /* xt_mul32 */,
16759 0,
16760 Opcode_mull_encode_fns, 0, 0 },
16761 { "muluh", 327 /* xt_mul32 */,
16762 0,
16763 Opcode_muluh_encode_fns, 0, 0 },
16764 { "mulsh", 327 /* xt_mul32 */,
16765 0,
16766 Opcode_mulsh_encode_fns, 0, 0 },
16767 { "rur.fcr", 328 /* rur_fcr */,
16768 0,
16769 Opcode_rur_fcr_encode_fns, 0, 0 },
16770 { "wur.fcr", 329 /* wur_fcr */,
16771 0,
16772 Opcode_wur_fcr_encode_fns, 0, 0 },
16773 { "rur.fsr", 330 /* rur_fsr */,
16774 0,
16775 Opcode_rur_fsr_encode_fns, 0, 0 },
16776 { "wur.fsr", 331 /* wur_fsr */,
16777 0,
16778 Opcode_wur_fsr_encode_fns, 0, 0 },
16779 { "add.s", 332 /* fp */,
16780 0,
16781 Opcode_add_s_encode_fns, 0, 0 },
16782 { "sub.s", 332 /* fp */,
16783 0,
16784 Opcode_sub_s_encode_fns, 0, 0 },
16785 { "mul.s", 332 /* fp */,
16786 0,
16787 Opcode_mul_s_encode_fns, 0, 0 },
16788 { "madd.s", 333 /* fp_mac */,
16789 0,
16790 Opcode_madd_s_encode_fns, 0, 0 },
16791 { "msub.s", 333 /* fp_mac */,
16792 0,
16793 Opcode_msub_s_encode_fns, 0, 0 },
16794 { "movf.s", 334 /* fp_cmov */,
16795 0,
16796 Opcode_movf_s_encode_fns, 0, 0 },
16797 { "movt.s", 334 /* fp_cmov */,
16798 0,
16799 Opcode_movt_s_encode_fns, 0, 0 },
16800 { "moveqz.s", 335 /* fp_mov */,
16801 0,
16802 Opcode_moveqz_s_encode_fns, 0, 0 },
16803 { "movnez.s", 335 /* fp_mov */,
16804 0,
16805 Opcode_movnez_s_encode_fns, 0, 0 },
16806 { "movltz.s", 335 /* fp_mov */,
16807 0,
16808 Opcode_movltz_s_encode_fns, 0, 0 },
16809 { "movgez.s", 335 /* fp_mov */,
16810 0,
16811 Opcode_movgez_s_encode_fns, 0, 0 },
16812 { "abs.s", 336 /* fp_mov2 */,
16813 0,
16814 Opcode_abs_s_encode_fns, 0, 0 },
16815 { "mov.s", 336 /* fp_mov2 */,
16816 0,
16817 Opcode_mov_s_encode_fns, 0, 0 },
16818 { "neg.s", 336 /* fp_mov2 */,
16819 0,
16820 Opcode_neg_s_encode_fns, 0, 0 },
16821 { "un.s", 337 /* fp_cmp */,
16822 0,
16823 Opcode_un_s_encode_fns, 0, 0 },
16824 { "oeq.s", 337 /* fp_cmp */,
16825 0,
16826 Opcode_oeq_s_encode_fns, 0, 0 },
16827 { "ueq.s", 337 /* fp_cmp */,
16828 0,
16829 Opcode_ueq_s_encode_fns, 0, 0 },
16830 { "olt.s", 337 /* fp_cmp */,
16831 0,
16832 Opcode_olt_s_encode_fns, 0, 0 },
16833 { "ult.s", 337 /* fp_cmp */,
16834 0,
16835 Opcode_ult_s_encode_fns, 0, 0 },
16836 { "ole.s", 337 /* fp_cmp */,
16837 0,
16838 Opcode_ole_s_encode_fns, 0, 0 },
16839 { "ule.s", 337 /* fp_cmp */,
16840 0,
16841 Opcode_ule_s_encode_fns, 0, 0 },
16842 { "float.s", 338 /* fp_float */,
16843 0,
16844 Opcode_float_s_encode_fns, 0, 0 },
16845 { "ufloat.s", 338 /* fp_float */,
16846 0,
16847 Opcode_ufloat_s_encode_fns, 0, 0 },
16848 { "round.s", 339 /* fp_int */,
16849 0,
16850 Opcode_round_s_encode_fns, 0, 0 },
16851 { "ceil.s", 339 /* fp_int */,
16852 0,
16853 Opcode_ceil_s_encode_fns, 0, 0 },
16854 { "floor.s", 339 /* fp_int */,
16855 0,
16856 Opcode_floor_s_encode_fns, 0, 0 },
16857 { "trunc.s", 339 /* fp_int */,
16858 0,
16859 Opcode_trunc_s_encode_fns, 0, 0 },
16860 { "utrunc.s", 339 /* fp_int */,
16861 0,
16862 Opcode_utrunc_s_encode_fns, 0, 0 },
16863 { "rfr", 340 /* fp_rfr */,
16864 0,
16865 Opcode_rfr_encode_fns, 0, 0 },
16866 { "wfr", 341 /* fp_wfr */,
16867 0,
16868 Opcode_wfr_encode_fns, 0, 0 },
16869 { "lsi", 342 /* fp_lsi */,
16870 0,
16871 Opcode_lsi_encode_fns, 0, 0 },
16872 { "lsiu", 343 /* fp_lsiu */,
16873 0,
16874 Opcode_lsiu_encode_fns, 0, 0 },
16875 { "lsx", 344 /* fp_lsx */,
16876 0,
16877 Opcode_lsx_encode_fns, 0, 0 },
16878 { "lsxu", 345 /* fp_lsxu */,
16879 0,
16880 Opcode_lsxu_encode_fns, 0, 0 },
16881 { "ssi", 346 /* fp_ssi */,
16882 0,
16883 Opcode_ssi_encode_fns, 0, 0 },
16884 { "ssiu", 347 /* fp_ssiu */,
16885 0,
16886 Opcode_ssiu_encode_fns, 0, 0 },
16887 { "ssx", 348 /* fp_ssx */,
16888 0,
16889 Opcode_ssx_encode_fns, 0, 0 },
16890 { "ssxu", 349 /* fp_ssxu */,
16891 0,
16892 Opcode_ssxu_encode_fns, 0, 0 },
16893 { "beqz.w18", 350 /* xt_iclass_wb18_0 */,
16894 XTENSA_OPCODE_IS_BRANCH,
16895 Opcode_beqz_w18_encode_fns, 0, 0 },
16896 { "bnez.w18", 350 /* xt_iclass_wb18_0 */,
16897 XTENSA_OPCODE_IS_BRANCH,
16898 Opcode_bnez_w18_encode_fns, 0, 0 },
16899 { "bgez.w18", 350 /* xt_iclass_wb18_0 */,
16900 XTENSA_OPCODE_IS_BRANCH,
16901 Opcode_bgez_w18_encode_fns, 0, 0 },
16902 { "bltz.w18", 350 /* xt_iclass_wb18_0 */,
16903 XTENSA_OPCODE_IS_BRANCH,
16904 Opcode_bltz_w18_encode_fns, 0, 0 },
16905 { "beqi.w18", 351 /* xt_iclass_wb18_1 */,
16906 XTENSA_OPCODE_IS_BRANCH,
16907 Opcode_beqi_w18_encode_fns, 0, 0 },
16908 { "bnei.w18", 351 /* xt_iclass_wb18_1 */,
16909 XTENSA_OPCODE_IS_BRANCH,
16910 Opcode_bnei_w18_encode_fns, 0, 0 },
16911 { "bgei.w18", 351 /* xt_iclass_wb18_1 */,
16912 XTENSA_OPCODE_IS_BRANCH,
16913 Opcode_bgei_w18_encode_fns, 0, 0 },
16914 { "blti.w18", 351 /* xt_iclass_wb18_1 */,
16915 XTENSA_OPCODE_IS_BRANCH,
16916 Opcode_blti_w18_encode_fns, 0, 0 },
16917 { "bgeui.w18", 352 /* xt_iclass_wb18_2 */,
16918 XTENSA_OPCODE_IS_BRANCH,
16919 Opcode_bgeui_w18_encode_fns, 0, 0 },
16920 { "bltui.w18", 352 /* xt_iclass_wb18_2 */,
16921 XTENSA_OPCODE_IS_BRANCH,
16922 Opcode_bltui_w18_encode_fns, 0, 0 },
16923 { "bbci.w18", 353 /* xt_iclass_wb18_3 */,
16924 XTENSA_OPCODE_IS_BRANCH,
16925 Opcode_bbci_w18_encode_fns, 0, 0 },
16926 { "bbsi.w18", 353 /* xt_iclass_wb18_3 */,
16927 XTENSA_OPCODE_IS_BRANCH,
16928 Opcode_bbsi_w18_encode_fns, 0, 0 },
16929 { "beq.w18", 354 /* xt_iclass_wb18_4 */,
16930 XTENSA_OPCODE_IS_BRANCH,
16931 Opcode_beq_w18_encode_fns, 0, 0 },
16932 { "bne.w18", 354 /* xt_iclass_wb18_4 */,
16933 XTENSA_OPCODE_IS_BRANCH,
16934 Opcode_bne_w18_encode_fns, 0, 0 },
16935 { "bge.w18", 354 /* xt_iclass_wb18_4 */,
16936 XTENSA_OPCODE_IS_BRANCH,
16937 Opcode_bge_w18_encode_fns, 0, 0 },
16938 { "blt.w18", 354 /* xt_iclass_wb18_4 */,
16939 XTENSA_OPCODE_IS_BRANCH,
16940 Opcode_blt_w18_encode_fns, 0, 0 },
16941 { "bgeu.w18", 354 /* xt_iclass_wb18_4 */,
16942 XTENSA_OPCODE_IS_BRANCH,
16943 Opcode_bgeu_w18_encode_fns, 0, 0 },
16944 { "bltu.w18", 354 /* xt_iclass_wb18_4 */,
16945 XTENSA_OPCODE_IS_BRANCH,
16946 Opcode_bltu_w18_encode_fns, 0, 0 },
16947 { "bany.w18", 354 /* xt_iclass_wb18_4 */,
16948 XTENSA_OPCODE_IS_BRANCH,
16949 Opcode_bany_w18_encode_fns, 0, 0 },
16950 { "bnone.w18", 354 /* xt_iclass_wb18_4 */,
16951 XTENSA_OPCODE_IS_BRANCH,
16952 Opcode_bnone_w18_encode_fns, 0, 0 },
16953 { "ball.w18", 354 /* xt_iclass_wb18_4 */,
16954 XTENSA_OPCODE_IS_BRANCH,
16955 Opcode_ball_w18_encode_fns, 0, 0 },
16956 { "bnall.w18", 354 /* xt_iclass_wb18_4 */,
16957 XTENSA_OPCODE_IS_BRANCH,
16958 Opcode_bnall_w18_encode_fns, 0, 0 },
16959 { "bbc.w18", 354 /* xt_iclass_wb18_4 */,
16960 XTENSA_OPCODE_IS_BRANCH,
16961 Opcode_bbc_w18_encode_fns, 0, 0 },
16962 { "bbs.w18", 354 /* xt_iclass_wb18_4 */,
16963 XTENSA_OPCODE_IS_BRANCH,
16964 Opcode_bbs_w18_encode_fns, 0, 0 }
56fb3749
SA		 16965};
16966
43cd72b9
BW		 16967\f
16968/* Slot-specific opcode decode functions. */
16969
16970static int
16971Slot_inst_decode (const xtensa_insnbuf insn)
16972{
16973 switch (Field_op0_Slot_inst_get (insn))
16974 {
16975 case 0:
16976 switch (Field_op1_Slot_inst_get (insn))
16977 {
16978 case 0:
16979 switch (Field_op2_Slot_inst_get (insn))
16980 {
16981 case 0:
16982 switch (Field_r_Slot_inst_get (insn))
16983 {
16984 case 0:
16985 switch (Field_m_Slot_inst_get (insn))
16986 {
16987 case 0:
074f5109
BW		 16988 if (Field_s_Slot_inst_get (insn) == 0 &&
16989 Field_n_Slot_inst_get (insn) == 0)
7aa09196 16990 return 79; /* ill */
074f5109 16991 break;
43cd72b9
BW		 16992 case 2:
16993 switch (Field_n_Slot_inst_get (insn))
16994 {
16995 case 0:
7aa09196 16996 return 98; /* ret */
43cd72b9 16997 case 1:
7aa09196 16998 return 14; /* retw */
43cd72b9 16999 case 2:
7aa09196 17000 return 81; /* jx */
43cd72b9
BW		 17001 }
17002 break;
17003 case 3:
17004 switch (Field_n_Slot_inst_get (insn))
17005 {
17006 case 0:
7aa09196 17007 return 77; /* callx0 */
43cd72b9 17008 case 1:
7aa09196 17009 return 10; /* callx4 */
43cd72b9 17010 case 2:
7aa09196 17011 return 9; /* callx8 */
43cd72b9 17012 case 3:
7aa09196 17013 return 8; /* callx12 */
43cd72b9
BW		 17014 }
17015 break;
17016 }
17017 break;
17018 case 1:
7aa09196 17019 return 12; /* movsp */
43cd72b9
BW		 17020 case 2:
17021 if (Field_s_Slot_inst_get (insn) == 0)
17022 {
17023 switch (Field_t_Slot_inst_get (insn))
17024 {
17025 case 0:
7aa09196 17026 return 116; /* isync */
43cd72b9 17027 case 1:
7aa09196 17028 return 117; /* rsync */
43cd72b9 17029 case 2:
7aa09196 17030 return 118; /* esync */
43cd72b9 17031 case 3:
7aa09196 17032 return 119; /* dsync */
43cd72b9 17033 case 8:
7aa09196 17034 return 0; /* excw */
43cd72b9 17035 case 12:
7aa09196 17036 return 114; /* memw */
43cd72b9 17037 case 13:
7aa09196 17038 return 115; /* extw */
43cd72b9 17039 case 15:
7aa09196 17040 return 97; /* nop */
43cd72b9
BW		 17041 }
17042 }
17043 break;
17044 case 3:
17045 switch (Field_t_Slot_inst_get (insn))
17046 {
17047 case 0:
17048 switch (Field_s_Slot_inst_get (insn))
17049 {
17050 case 0:
7aa09196 17051 return 1; /* rfe */
43cd72b9 17052 case 2:
7aa09196 17053 return 2; /* rfde */
43cd72b9 17054 case 4:
7aa09196 17055 return 16; /* rfwo */
43cd72b9 17056 case 5:
7aa09196 17057 return 17; /* rfwu */
43cd72b9
BW		 17058 }
17059 break;
17060 case 1:
7aa09196 17061 return 316; /* rfi */
43cd72b9
BW		 17062 }
17063 break;
17064 case 4:
7aa09196 17065 return 324; /* break */
43cd72b9
BW		 17066 case 5:
17067 switch (Field_s_Slot_inst_get (insn))
17068 {
17069 case 0:
17070 if (Field_t_Slot_inst_get (insn) == 0)
7aa09196 17071 return 3; /* syscall */
43cd72b9
BW		 17072 break;
17073 case 1:
17074 if (Field_t_Slot_inst_get (insn) == 0)
7aa09196 17075 return 4; /* simcall */
43cd72b9
BW		 17076 break;
17077 }
17078 break;
17079 case 6:
7aa09196 17080 return 120; /* rsil */
43cd72b9
BW		 17081 case 7:
17082 if (Field_t_Slot_inst_get (insn) == 0)
7aa09196 17083 return 317; /* waiti */
43cd72b9 17084 break;
7aa09196
SA		 17085 case 8:
17086 return 367; /* any4 */
17087 case 9:
17088 return 368; /* all4 */
17089 case 10:
17090 return 369; /* any8 */
17091 case 11:
17092 return 370; /* all8 */
43cd72b9
BW		 17093 }
17094 break;
17095 case 1:
7aa09196 17096 return 49; /* and */
43cd72b9 17097 case 2:
7aa09196 17098 return 50; /* or */
43cd72b9 17099 case 3:
7aa09196 17100 return 51; /* xor */
43cd72b9
BW		 17101 case 4:
17102 switch (Field_r_Slot_inst_get (insn))
17103 {
17104 case 0:
17105 if (Field_t_Slot_inst_get (insn) == 0)
7aa09196 17106 return 102; /* ssr */
43cd72b9
BW		 17107 break;
17108 case 1:
17109 if (Field_t_Slot_inst_get (insn) == 0)
7aa09196 17110 return 103; /* ssl */
43cd72b9
BW		 17111 break;
17112 case 2:
17113 if (Field_t_Slot_inst_get (insn) == 0)
7aa09196 17114 return 104; /* ssa8l */
43cd72b9
BW		 17115 break;
17116 case 3:
17117 if (Field_t_Slot_inst_get (insn) == 0)
7aa09196 17118 return 105; /* ssa8b */
43cd72b9
BW		 17119 break;
17120 case 4:
17121 if (Field_thi3_Slot_inst_get (insn) == 0)
7aa09196 17122 return 106; /* ssai */
43cd72b9
BW		 17123 break;
17124 case 8:
17125 if (Field_s_Slot_inst_get (insn) == 0)
7aa09196 17126 return 13; /* rotw */
43cd72b9
BW		 17127 break;
17128 case 14:
7aa09196 17129 return 448; /* nsa */
43cd72b9 17130 case 15:
7aa09196 17131 return 449; /* nsau */
43cd72b9
BW		 17132 }
17133 break;
17134 case 5:
17135 switch (Field_r_Slot_inst_get (insn))
17136 {
074f5109 17137 case 1:
7aa09196 17138 return 438; /* hwwitlba */
43cd72b9 17139 case 3:
7aa09196 17140 return 434; /* ritlb0 */
43cd72b9 17141 case 4:
074f5109 17142 if (Field_t_Slot_inst_get (insn) == 0)
7aa09196 17143 return 432; /* iitlb */
074f5109 17144 break;
43cd72b9 17145 case 5:
7aa09196 17146 return 433; /* pitlb */
43cd72b9 17147 case 6:
7aa09196 17148 return 436; /* witlb */
43cd72b9 17149 case 7:
7aa09196 17150 return 435; /* ritlb1 */
074f5109 17151 case 9:
7aa09196 17152 return 439; /* hwwdtlba */
43cd72b9 17153 case 11:
7aa09196 17154 return 429; /* rdtlb0 */
43cd72b9 17155 case 12:
074f5109 17156 if (Field_t_Slot_inst_get (insn) == 0)
7aa09196 17157 return 427; /* idtlb */
074f5109 17158 break;
43cd72b9 17159 case 13:
7aa09196 17160 return 428; /* pdtlb */
43cd72b9 17161 case 14:
7aa09196 17162 return 431; /* wdtlb */
43cd72b9 17163 case 15:
7aa09196 17164 return 430; /* rdtlb1 */
43cd72b9
BW		 17165 }
17166 break;
17167 case 6:
17168 switch (Field_s_Slot_inst_get (insn))
17169 {
17170 case 0:
7aa09196 17171 return 95; /* neg */
43cd72b9 17172 case 1:
7aa09196 17173 return 96; /* abs */
43cd72b9
BW		 17174 }
17175 break;
17176 case 8:
7aa09196 17177 return 41; /* add */
43cd72b9 17178 case 9:
7aa09196 17179 return 43; /* addx2 */
43cd72b9 17180 case 10:
7aa09196 17181 return 44; /* addx4 */
43cd72b9 17182 case 11:
7aa09196 17183 return 45; /* addx8 */
43cd72b9 17184 case 12:
7aa09196 17185 return 42; /* sub */
43cd72b9 17186 case 13:
7aa09196 17187 return 46; /* subx2 */
43cd72b9 17188 case 14:
7aa09196 17189 return 47; /* subx4 */
43cd72b9 17190 case 15:
7aa09196 17191 return 48; /* subx8 */
43cd72b9
BW		 17192 }
17193 break;
17194 case 1:
17195 switch (Field_op2_Slot_inst_get (insn))
17196 {
17197 case 0:
17198 case 1:
7aa09196 17199 return 111; /* slli */
43cd72b9
BW		 17200 case 2:
17201 case 3:
7aa09196 17202 return 112; /* srai */
43cd72b9 17203 case 4:
7aa09196 17204 return 113; /* srli */
43cd72b9
BW		 17205 case 6:
17206 switch (Field_sr_Slot_inst_get (insn))
17207 {
17208 case 0:
7aa09196 17209 return 129; /* xsr.lbeg */
43cd72b9 17210 case 1:
7aa09196 17211 return 123; /* xsr.lend */
43cd72b9 17212 case 2:
7aa09196 17213 return 126; /* xsr.lcount */
43cd72b9 17214 case 3:
7aa09196
SA		 17215 return 132; /* xsr.sar */
17216 case 4:
17217 return 377; /* xsr.br */
43cd72b9 17218 case 5:
7aa09196 17219 return 135; /* xsr.litbase */
33430bd0 17220 case 12:
7aa09196
SA		 17221 return 456; /* xsr.scompare1 */
17222 case 16:
17223 return 312; /* xsr.acclo */
17224 case 17:
17225 return 315; /* xsr.acchi */
17226 case 32:
17227 return 300; /* xsr.m0 */
17228 case 33:
17229 return 303; /* xsr.m1 */
17230 case 34:
17231 return 306; /* xsr.m2 */
17232 case 35:
17233 return 309; /* xsr.m3 */
43cd72b9 17234 case 72:
7aa09196 17235 return 22; /* xsr.windowbase */
43cd72b9 17236 case 73:
7aa09196 17237 return 25; /* xsr.windowstart */
074f5109 17238 case 83:
7aa09196 17239 return 417; /* xsr.ptevaddr */
074f5109 17240 case 90:
7aa09196 17241 return 420; /* xsr.rasid */
074f5109 17242 case 91:
7aa09196 17243 return 423; /* xsr.itlbcfg */
074f5109 17244 case 92:
7aa09196 17245 return 426; /* xsr.dtlbcfg */
43cd72b9 17246 case 96:
7aa09196 17247 return 346; /* xsr.ibreakenable */
43cd72b9 17248 case 104:
7aa09196 17249 return 358; /* xsr.ddr */
43cd72b9 17250 case 128:
7aa09196 17251 return 340; /* xsr.ibreaka0 */
43cd72b9 17252 case 129:
7aa09196 17253 return 343; /* xsr.ibreaka1 */
43cd72b9 17254 case 144:
7aa09196 17255 return 328; /* xsr.dbreaka0 */
43cd72b9 17256 case 145:
7aa09196 17257 return 334; /* xsr.dbreaka1 */
43cd72b9 17258 case 160:
7aa09196 17259 return 331; /* xsr.dbreakc0 */
43cd72b9 17260 case 161:
7aa09196 17261 return 337; /* xsr.dbreakc1 */
43cd72b9 17262 case 177:
7aa09196 17263 return 143; /* xsr.epc1 */
43cd72b9 17264 case 178:
7aa09196 17265 return 149; /* xsr.epc2 */
43cd72b9 17266 case 179:
7aa09196 17267 return 155; /* xsr.epc3 */
43cd72b9 17268 case 180:
7aa09196 17269 return 161; /* xsr.epc4 */
33430bd0 17270 case 181:
7aa09196 17271 return 167; /* xsr.epc5 */
33430bd0 17272 case 182:
7aa09196 17273 return 173; /* xsr.epc6 */
33430bd0 17274 case 183:
7aa09196 17275 return 179; /* xsr.epc7 */
43cd72b9 17276 case 192:
7aa09196 17277 return 206; /* xsr.depc */
43cd72b9 17278 case 194:
7aa09196 17279 return 185; /* xsr.eps2 */
43cd72b9 17280 case 195:
7aa09196 17281 return 188; /* xsr.eps3 */
43cd72b9 17282 case 196:
7aa09196 17283 return 191; /* xsr.eps4 */
33430bd0 17284 case 197:
7aa09196 17285 return 194; /* xsr.eps5 */
33430bd0 17286 case 198:
7aa09196 17287 return 197; /* xsr.eps6 */
33430bd0 17288 case 199:
7aa09196 17289 return 200; /* xsr.eps7 */
43cd72b9 17290 case 209:
7aa09196 17291 return 146; /* xsr.excsave1 */
43cd72b9 17292 case 210:
7aa09196 17293 return 152; /* xsr.excsave2 */
43cd72b9 17294 case 211:
7aa09196 17295 return 158; /* xsr.excsave3 */
43cd72b9 17296 case 212:
7aa09196 17297 return 164; /* xsr.excsave4 */
33430bd0 17298 case 213:
7aa09196 17299 return 170; /* xsr.excsave5 */
33430bd0 17300 case 214:
7aa09196 17301 return 176; /* xsr.excsave6 */
33430bd0 17302 case 215:
7aa09196 17303 return 182; /* xsr.excsave7 */
33430bd0 17304 case 224:
7aa09196 17305 return 442; /* xsr.cpenable */
43cd72b9 17306 case 228:
7aa09196 17307 return 323; /* xsr.intenable */
43cd72b9 17308 case 230:
7aa09196 17309 return 140; /* xsr.ps */
33430bd0 17310 case 231:
7aa09196 17311 return 225; /* xsr.vecbase */
43cd72b9 17312 case 232:
7aa09196 17313 return 209; /* xsr.exccause */
43cd72b9 17314 case 233:
7aa09196 17315 return 349; /* xsr.debugcause */
43cd72b9 17316 case 234:
7aa09196 17317 return 380; /* xsr.ccount */
43cd72b9 17318 case 236:
7aa09196 17319 return 352; /* xsr.icount */
43cd72b9 17320 case 237:
7aa09196 17321 return 355; /* xsr.icountlevel */
43cd72b9 17322 case 238:
7aa09196 17323 return 203; /* xsr.excvaddr */
43cd72b9 17324 case 240:
7aa09196 17325 return 383; /* xsr.ccompare0 */
43cd72b9 17326 case 241:
7aa09196 17327 return 386; /* xsr.ccompare1 */
43cd72b9 17328 case 242:
7aa09196 17329 return 389; /* xsr.ccompare2 */
43cd72b9 17330 case 244:
7aa09196 17331 return 212; /* xsr.misc0 */
43cd72b9 17332 case 245:
7aa09196
SA		 17333 return 215; /* xsr.misc1 */
17334 case 246:
17335 return 218; /* xsr.misc2 */
17336 case 247:
17337 return 221; /* xsr.misc3 */
43cd72b9
BW		 17338 }
17339 break;
17340 case 8:
7aa09196 17341 return 108; /* src */
43cd72b9
BW		 17342 case 9:
17343 if (Field_s_Slot_inst_get (insn) == 0)
7aa09196 17344 return 109; /* srl */
43cd72b9
BW		 17345 break;
17346 case 10:
17347 if (Field_t_Slot_inst_get (insn) == 0)
7aa09196 17348 return 107; /* sll */
43cd72b9
BW		 17349 break;
17350 case 11:
17351 if (Field_s_Slot_inst_get (insn) == 0)
7aa09196 17352 return 110; /* sra */
43cd72b9 17353 break;
33430bd0 17354 case 12:
7aa09196 17355 return 296; /* mul16u */
33430bd0 17356 case 13:
7aa09196 17357 return 297; /* mul16s */
43cd72b9
BW		 17358 case 15:
17359 switch (Field_r_Slot_inst_get (insn))
17360 {
17361 case 0:
7aa09196 17362 return 396; /* lict */
43cd72b9 17363 case 1:
7aa09196 17364 return 398; /* sict */
43cd72b9 17365 case 2:
7aa09196 17366 return 397; /* licw */
43cd72b9 17367 case 3:
7aa09196 17368 return 399; /* sicw */
43cd72b9 17369 case 8:
7aa09196 17370 return 414; /* ldct */
43cd72b9 17371 case 9:
7aa09196 17372 return 413; /* sdct */
43cd72b9 17373 case 14:
af4bed4b 17374 if (Field_t_Slot_inst_get (insn) == 0)
7aa09196 17375 return 359; /* rfdo */
af4bed4b 17376 if (Field_t_Slot_inst_get (insn) == 1)
7aa09196 17377 return 360; /* rfdd */
43cd72b9 17378 break;
074f5109 17379 case 15:
7aa09196 17380 return 437; /* ldpte */
43cd72b9
BW		 17381 }
17382 break;
17383 }
17384 break;
33430bd0
BW		 17385 case 2:
17386 switch (Field_op2_Slot_inst_get (insn))
17387 {
7aa09196
SA		 17388 case 0:
17389 return 362; /* andb */
17390 case 1:
17391 return 363; /* andbc */
17392 case 2:
17393 return 364; /* orb */
17394 case 3:
17395 return 365; /* orbc */
17396 case 4:
17397 return 366; /* xorb */
33430bd0 17398 case 8:
7aa09196
SA		 17399 return 461; /* mull */
17400 case 10:
17401 return 462; /* muluh */
17402 case 11:
17403 return 463; /* mulsh */
33430bd0 17404 case 12:
7aa09196 17405 return 457; /* quou */
33430bd0 17406 case 13:
7aa09196 17407 return 458; /* quos */
33430bd0 17408 case 14:
7aa09196 17409 return 459; /* remu */
33430bd0 17410 case 15:
7aa09196 17411 return 460; /* rems */
33430bd0
BW		 17412 }
17413 break;
43cd72b9
BW		 17414 case 3:
17415 switch (Field_op2_Slot_inst_get (insn))
17416 {
17417 case 0:
17418 switch (Field_sr_Slot_inst_get (insn))
17419 {
17420 case 0:
7aa09196 17421 return 127; /* rsr.lbeg */
43cd72b9 17422 case 1:
7aa09196 17423 return 121; /* rsr.lend */
43cd72b9 17424 case 2:
7aa09196 17425 return 124; /* rsr.lcount */
43cd72b9 17426 case 3:
7aa09196
SA		 17427 return 130; /* rsr.sar */
17428 case 4:
17429 return 375; /* rsr.br */
43cd72b9 17430 case 5:
7aa09196 17431 return 133; /* rsr.litbase */
33430bd0 17432 case 12:
7aa09196
SA		 17433 return 454; /* rsr.scompare1 */
17434 case 16:
17435 return 310; /* rsr.acclo */
17436 case 17:
17437 return 313; /* rsr.acchi */
17438 case 32:
17439 return 298; /* rsr.m0 */
17440 case 33:
17441 return 301; /* rsr.m1 */
17442 case 34:
17443 return 304; /* rsr.m2 */
17444 case 35:
17445 return 307; /* rsr.m3 */
43cd72b9 17446 case 72:
7aa09196 17447 return 20; /* rsr.windowbase */
43cd72b9 17448 case 73:
7aa09196 17449 return 23; /* rsr.windowstart */
074f5109 17450 case 83:
7aa09196 17451 return 416; /* rsr.ptevaddr */
074f5109 17452 case 90:
7aa09196 17453 return 418; /* rsr.rasid */
074f5109 17454 case 91:
7aa09196 17455 return 421; /* rsr.itlbcfg */
074f5109 17456 case 92:
7aa09196 17457 return 424; /* rsr.dtlbcfg */
43cd72b9 17458 case 96:
7aa09196 17459 return 344; /* rsr.ibreakenable */
43cd72b9 17460 case 104:
7aa09196 17461 return 356; /* rsr.ddr */
43cd72b9 17462 case 128:
7aa09196 17463 return 338; /* rsr.ibreaka0 */
43cd72b9 17464 case 129:
7aa09196 17465 return 341; /* rsr.ibreaka1 */
43cd72b9 17466 case 144:
7aa09196 17467 return 326; /* rsr.dbreaka0 */
43cd72b9 17468 case 145:
7aa09196 17469 return 332; /* rsr.dbreaka1 */
43cd72b9 17470 case 160:
7aa09196 17471 return 329; /* rsr.dbreakc0 */
43cd72b9 17472 case 161:
7aa09196 17473 return 335; /* rsr.dbreakc1 */
43cd72b9 17474 case 176:
7aa09196 17475 return 136; /* rsr.176 */
43cd72b9 17476 case 177:
7aa09196 17477 return 141; /* rsr.epc1 */
43cd72b9 17478 case 178:
7aa09196 17479 return 147; /* rsr.epc2 */
43cd72b9 17480 case 179:
7aa09196 17481 return 153; /* rsr.epc3 */
43cd72b9 17482 case 180:
7aa09196 17483 return 159; /* rsr.epc4 */
33430bd0 17484 case 181:
7aa09196 17485 return 165; /* rsr.epc5 */
33430bd0 17486 case 182:
7aa09196 17487 return 171; /* rsr.epc6 */
33430bd0 17488 case 183:
7aa09196 17489 return 177; /* rsr.epc7 */
43cd72b9 17490 case 192:
7aa09196 17491 return 204; /* rsr.depc */
43cd72b9 17492 case 194:
7aa09196 17493 return 183; /* rsr.eps2 */
43cd72b9 17494 case 195:
7aa09196 17495 return 186; /* rsr.eps3 */
43cd72b9 17496 case 196:
7aa09196 17497 return 189; /* rsr.eps4 */
33430bd0 17498 case 197:
7aa09196 17499 return 192; /* rsr.eps5 */
33430bd0 17500 case 198:
7aa09196 17501 return 195; /* rsr.eps6 */
33430bd0 17502 case 199:
7aa09196 17503 return 198; /* rsr.eps7 */
43cd72b9 17504 case 208:
7aa09196 17505 return 137; /* rsr.208 */
43cd72b9 17506 case 209:
7aa09196 17507 return 144; /* rsr.excsave1 */
43cd72b9 17508 case 210:
7aa09196 17509 return 150; /* rsr.excsave2 */
43cd72b9 17510 case 211:
7aa09196 17511 return 156; /* rsr.excsave3 */
43cd72b9 17512 case 212:
7aa09196 17513 return 162; /* rsr.excsave4 */
33430bd0 17514 case 213:
7aa09196 17515 return 168; /* rsr.excsave5 */
33430bd0 17516 case 214:
7aa09196 17517 return 174; /* rsr.excsave6 */
33430bd0 17518 case 215:
7aa09196 17519 return 180; /* rsr.excsave7 */
33430bd0 17520 case 224:
7aa09196 17521 return 440; /* rsr.cpenable */
43cd72b9 17522 case 226:
7aa09196 17523 return 318; /* rsr.interrupt */
43cd72b9 17524 case 228:
7aa09196 17525 return 321; /* rsr.intenable */
43cd72b9 17526 case 230:
7aa09196 17527 return 138; /* rsr.ps */
33430bd0 17528 case 231:
7aa09196 17529 return 223; /* rsr.vecbase */
43cd72b9 17530 case 232:
7aa09196 17531 return 207; /* rsr.exccause */
43cd72b9 17532 case 233:
7aa09196 17533 return 347; /* rsr.debugcause */
43cd72b9 17534 case 234:
7aa09196 17535 return 378; /* rsr.ccount */
43cd72b9 17536 case 235:
7aa09196 17537 return 222; /* rsr.prid */
43cd72b9 17538 case 236:
7aa09196 17539 return 350; /* rsr.icount */
43cd72b9 17540 case 237:
7aa09196 17541 return 353; /* rsr.icountlevel */
43cd72b9 17542 case 238:
7aa09196 17543 return 201; /* rsr.excvaddr */
43cd72b9 17544 case 240:
7aa09196 17545 return 381; /* rsr.ccompare0 */
43cd72b9 17546 case 241:
7aa09196 17547 return 384; /* rsr.ccompare1 */
43cd72b9 17548 case 242:
7aa09196 17549 return 387; /* rsr.ccompare2 */
43cd72b9 17550 case 244:
7aa09196 17551 return 210; /* rsr.misc0 */
43cd72b9 17552 case 245:
7aa09196
SA		 17553 return 213; /* rsr.misc1 */
17554 case 246:
17555 return 216; /* rsr.misc2 */
17556 case 247:
17557 return 219; /* rsr.misc3 */
43cd72b9
BW		 17558 }
17559 break;
17560 case 1:
17561 switch (Field_sr_Slot_inst_get (insn))
17562 {
17563 case 0:
7aa09196 17564 return 128; /* wsr.lbeg */
43cd72b9 17565 case 1:
7aa09196 17566 return 122; /* wsr.lend */
43cd72b9 17567 case 2:
7aa09196 17568 return 125; /* wsr.lcount */
43cd72b9 17569 case 3:
7aa09196
SA		 17570 return 131; /* wsr.sar */
17571 case 4:
17572 return 376; /* wsr.br */
43cd72b9 17573 case 5:
7aa09196 17574 return 134; /* wsr.litbase */
33430bd0 17575 case 12:
7aa09196
SA		 17576 return 455; /* wsr.scompare1 */
17577 case 16:
17578 return 311; /* wsr.acclo */
17579 case 17:
17580 return 314; /* wsr.acchi */
17581 case 32:
17582 return 299; /* wsr.m0 */
17583 case 33:
17584 return 302; /* wsr.m1 */
17585 case 34:
17586 return 305; /* wsr.m2 */
17587 case 35:
17588 return 308; /* wsr.m3 */
43cd72b9 17589 case 72:
7aa09196 17590 return 21; /* wsr.windowbase */
43cd72b9 17591 case 73:
7aa09196 17592 return 24; /* wsr.windowstart */
074f5109 17593 case 83:
7aa09196 17594 return 415; /* wsr.ptevaddr */
33430bd0 17595 case 89:
7aa09196 17596 return 361; /* wsr.mmid */
074f5109 17597 case 90:
7aa09196 17598 return 419; /* wsr.rasid */
074f5109 17599 case 91:
7aa09196 17600 return 422; /* wsr.itlbcfg */
074f5109 17601 case 92:
7aa09196 17602 return 425; /* wsr.dtlbcfg */
43cd72b9 17603 case 96:
7aa09196 17604 return 345; /* wsr.ibreakenable */
43cd72b9 17605 case 104:
7aa09196 17606 return 357; /* wsr.ddr */
43cd72b9 17607 case 128:
7aa09196 17608 return 339; /* wsr.ibreaka0 */
43cd72b9 17609 case 129:
7aa09196 17610 return 342; /* wsr.ibreaka1 */
43cd72b9 17611 case 144:
7aa09196 17612 return 327; /* wsr.dbreaka0 */
43cd72b9 17613 case 145:
7aa09196 17614 return 333; /* wsr.dbreaka1 */
43cd72b9 17615 case 160:
7aa09196 17616 return 330; /* wsr.dbreakc0 */
43cd72b9 17617 case 161:
7aa09196 17618 return 336; /* wsr.dbreakc1 */
43cd72b9 17619 case 177:
7aa09196 17620 return 142; /* wsr.epc1 */
43cd72b9 17621 case 178:
7aa09196 17622 return 148; /* wsr.epc2 */
43cd72b9 17623 case 179:
7aa09196 17624 return 154; /* wsr.epc3 */
43cd72b9 17625 case 180:
7aa09196 17626 return 160; /* wsr.epc4 */
33430bd0 17627 case 181:
7aa09196 17628 return 166; /* wsr.epc5 */
33430bd0 17629 case 182:
7aa09196 17630 return 172; /* wsr.epc6 */
33430bd0 17631 case 183:
7aa09196 17632 return 178; /* wsr.epc7 */
43cd72b9 17633 case 192:
7aa09196 17634 return 205; /* wsr.depc */
43cd72b9 17635 case 194:
7aa09196 17636 return 184; /* wsr.eps2 */
43cd72b9 17637 case 195:
7aa09196 17638 return 187; /* wsr.eps3 */
43cd72b9 17639 case 196:
7aa09196 17640 return 190; /* wsr.eps4 */
33430bd0 17641 case 197:
7aa09196 17642 return 193; /* wsr.eps5 */
33430bd0 17643 case 198:
7aa09196 17644 return 196; /* wsr.eps6 */
33430bd0 17645 case 199:
7aa09196 17646 return 199; /* wsr.eps7 */
43cd72b9 17647 case 209:
7aa09196 17648 return 145; /* wsr.excsave1 */
43cd72b9 17649 case 210:
7aa09196 17650 return 151; /* wsr.excsave2 */
43cd72b9 17651 case 211:
7aa09196 17652 return 157; /* wsr.excsave3 */
43cd72b9 17653 case 212:
7aa09196 17654 return 163; /* wsr.excsave4 */
33430bd0 17655 case 213:
7aa09196 17656 return 169; /* wsr.excsave5 */
33430bd0 17657 case 214:
7aa09196 17658 return 175; /* wsr.excsave6 */
33430bd0 17659 case 215:
7aa09196 17660 return 181; /* wsr.excsave7 */
33430bd0 17661 case 224:
7aa09196 17662 return 441; /* wsr.cpenable */
43cd72b9 17663 case 226:
7aa09196 17664 return 319; /* wsr.intset */
43cd72b9 17665 case 227:
7aa09196 17666 return 320; /* wsr.intclear */
43cd72b9 17667 case 228:
7aa09196 17668 return 322; /* wsr.intenable */
43cd72b9 17669 case 230:
7aa09196 17670 return 139; /* wsr.ps */
33430bd0 17671 case 231:
7aa09196 17672 return 224; /* wsr.vecbase */
43cd72b9 17673 case 232:
7aa09196 17674 return 208; /* wsr.exccause */
43cd72b9 17675 case 233:
7aa09196 17676 return 348; /* wsr.debugcause */
43cd72b9 17677 case 234:
7aa09196 17678 return 379; /* wsr.ccount */
43cd72b9 17679 case 236:
7aa09196 17680 return 351; /* wsr.icount */
43cd72b9 17681 case 237:
7aa09196 17682 return 354; /* wsr.icountlevel */
43cd72b9 17683 case 238:
7aa09196 17684 return 202; /* wsr.excvaddr */
43cd72b9 17685 case 240:
7aa09196 17686 return 382; /* wsr.ccompare0 */
43cd72b9 17687 case 241:
7aa09196 17688 return 385; /* wsr.ccompare1 */
43cd72b9 17689 case 242:
7aa09196 17690 return 388; /* wsr.ccompare2 */
43cd72b9 17691 case 244:
7aa09196 17692 return 211; /* wsr.misc0 */
43cd72b9 17693 case 245:
7aa09196
SA		 17694 return 214; /* wsr.misc1 */
17695 case 246:
17696 return 217; /* wsr.misc2 */
17697 case 247:
17698 return 220; /* wsr.misc3 */
43cd72b9
BW		 17699 }
17700 break;
33430bd0 17701 case 2:
7aa09196 17702 return 450; /* sext */
33430bd0 17703 case 3:
7aa09196 17704 return 443; /* clamps */
33430bd0 17705 case 4:
7aa09196 17706 return 444; /* min */
33430bd0 17707 case 5:
7aa09196 17708 return 445; /* max */
33430bd0 17709 case 6:
7aa09196 17710 return 446; /* minu */
33430bd0 17711 case 7:
7aa09196 17712 return 447; /* maxu */
43cd72b9 17713 case 8:
7aa09196 17714 return 91; /* moveqz */
43cd72b9 17715 case 9:
7aa09196 17716 return 92; /* movnez */
43cd72b9 17717 case 10:
7aa09196 17718 return 93; /* movltz */
43cd72b9 17719 case 11:
7aa09196
SA		 17720 return 94; /* movgez */
17721 case 12:
17722 return 373; /* movf */
17723 case 13:
17724 return 374; /* movt */
33430bd0 17725 case 14:
7aa09196
SA		 17726 switch (Field_st_Slot_inst_get (insn))
17727 {
17728 case 231:
17729 return 37; /* rur.threadptr */
17730 case 232:
17731 return 464; /* rur.fcr */
17732 case 233:
17733 return 466; /* rur.fsr */
17734 }
33430bd0
BW		 17735 break;
17736 case 15:
7aa09196
SA		 17737 switch (Field_sr_Slot_inst_get (insn))
17738 {
17739 case 231:
17740 return 38; /* wur.threadptr */
17741 case 232:
17742 return 465; /* wur.fcr */
17743 case 233:
17744 return 467; /* wur.fsr */
17745 }
33430bd0 17746 break;
43cd72b9
BW		 17747 }
17748 break;
17749 case 4:
17750 case 5:
7aa09196
SA		 17751 return 78; /* extui */
17752 case 8:
17753 switch (Field_op2_Slot_inst_get (insn))
17754 {
17755 case 0:
17756 return 500; /* lsx */
17757 case 1:
17758 return 501; /* lsxu */
17759 case 4:
17760 return 504; /* ssx */
17761 case 5:
17762 return 505; /* ssxu */
17763 }
17764 break;
43cd72b9
BW		 17765 case 9:
17766 switch (Field_op2_Slot_inst_get (insn))
17767 {
17768 case 0:
7aa09196
SA		 17769 return 18; /* l32e */
17770 case 4:
17771 return 19; /* s32e */
17772 }
17773 break;
17774 case 10:
17775 switch (Field_op2_Slot_inst_get (insn))
17776 {
17777 case 0:
17778 return 468; /* add.s */
17779 case 1:
17780 return 469; /* sub.s */
17781 case 2:
17782 return 470; /* mul.s */
17783 case 4:
17784 return 471; /* madd.s */
17785 case 5:
17786 return 472; /* msub.s */
17787 case 8:
17788 return 491; /* round.s */
17789 case 9:
17790 return 494; /* trunc.s */
17791 case 10:
17792 return 493; /* floor.s */
17793 case 11:
17794 return 492; /* ceil.s */
17795 case 12:
17796 return 489; /* float.s */
17797 case 13:
17798 return 490; /* ufloat.s */
17799 case 14:
17800 return 495; /* utrunc.s */
17801 case 15:
17802 switch (Field_t_Slot_inst_get (insn))
17803 {
17804 case 0:
17805 return 480; /* mov.s */
17806 case 1:
17807 return 479; /* abs.s */
17808 case 4:
17809 return 496; /* rfr */
17810 case 5:
17811 return 497; /* wfr */
17812 case 6:
17813 return 481; /* neg.s */
17814 }
17815 break;
17816 }
17817 break;
17818 case 11:
17819 switch (Field_op2_Slot_inst_get (insn))
17820 {
17821 case 1:
17822 return 482; /* un.s */
17823 case 2:
17824 return 483; /* oeq.s */
17825 case 3:
17826 return 484; /* ueq.s */
43cd72b9 17827 case 4:
7aa09196
SA		 17828 return 485; /* olt.s */
17829 case 5:
17830 return 486; /* ult.s */
17831 case 6:
17832 return 487; /* ole.s */
17833 case 7:
17834 return 488; /* ule.s */
17835 case 8:
17836 return 475; /* moveqz.s */
17837 case 9:
17838 return 476; /* movnez.s */
17839 case 10:
17840 return 477; /* movltz.s */
17841 case 11:
17842 return 478; /* movgez.s */
17843 case 12:
17844 return 473; /* movf.s */
17845 case 13:
17846 return 474; /* movt.s */
43cd72b9
BW		 17847 }
17848 break;
17849 }
e0001a05 17850 break;
43cd72b9 17851 case 1:
7aa09196 17852 return 85; /* l32r */
43cd72b9
BW		 17853 case 2:
17854 switch (Field_r_Slot_inst_get (insn))
17855 {
17856 case 0:
7aa09196
SA		 17857 return 86; /* l8ui */
17858 case 1:
17859 return 82; /* l16ui */
17860 case 2:
17861 return 84; /* l32i */
17862 case 4:
17863 return 101; /* s8i */
17864 case 5:
17865 return 99; /* s16i */
17866 case 6:
17867 return 100; /* s32i */
17868 case 7:
17869 switch (Field_t_Slot_inst_get (insn))
17870 {
17871 case 0:
17872 return 406; /* dpfr */
17873 case 1:
17874 return 407; /* dpfw */
17875 case 2:
17876 return 408; /* dpfro */
17877 case 3:
17878 return 409; /* dpfwo */
17879 case 4:
17880 return 400; /* dhwb */
17881 case 5:
17882 return 401; /* dhwbi */
17883 case 6:
17884 return 404; /* dhi */
17885 case 7:
17886 return 405; /* dii */
17887 case 8:
17888 switch (Field_op1_Slot_inst_get (insn))
17889 {
17890 case 0:
17891 return 410; /* dpfl */
17892 case 2:
17893 return 411; /* dhu */
17894 case 3:
17895 return 412; /* diu */
17896 case 4:
17897 return 402; /* diwb */
17898 case 5:
17899 return 403; /* diwbi */
17900 }
17901 break;
17902 case 12:
17903 return 390; /* ipf */
17904 case 13:
17905 switch (Field_op1_Slot_inst_get (insn))
17906 {
17907 case 0:
17908 return 392; /* ipfl */
17909 case 2:
17910 return 393; /* ihu */
17911 case 3:
17912 return 394; /* iiu */
17913 }
17914 break;
17915 case 14:
17916 return 391; /* ihi */
17917 case 15:
17918 return 395; /* iii */
17919 }
17920 break;
17921 case 9:
17922 return 83; /* l16si */
17923 case 10:
17924 return 90; /* movi */
17925 case 11:
17926 return 451; /* l32ai */
17927 case 12:
17928 return 39; /* addi */
17929 case 13:
17930 return 40; /* addmi */
17931 case 14:
17932 return 453; /* s32c1i */
17933 case 15:
17934 return 452; /* s32ri */
17935 }
17936 break;
17937 case 3:
17938 switch (Field_r_Slot_inst_get (insn))
17939 {
17940 case 0:
17941 return 498; /* lsi */
17942 case 4:
17943 return 502; /* ssi */
17944 case 8:
17945 return 499; /* lsiu */
17946 case 12:
17947 return 503; /* ssiu */
17948 }
17949 break;
17950 case 4:
17951 switch (Field_op2_Slot_inst_get (insn))
17952 {
17953 case 0:
17954 switch (Field_op1_Slot_inst_get (insn))
17955 {
17956 case 8:
17957 if (Field_t3_Slot_inst_get (insn) == 0 &&
17958 Field_tlo_Slot_inst_get (insn) == 0 &&
17959 Field_r3_Slot_inst_get (insn) == 0)
17960 return 287; /* mula.dd.ll.ldinc */
17961 break;
17962 case 9:
17963 if (Field_t3_Slot_inst_get (insn) == 0 &&
17964 Field_tlo_Slot_inst_get (insn) == 0 &&
17965 Field_r3_Slot_inst_get (insn) == 0)
17966 return 289; /* mula.dd.hl.ldinc */
17967 break;
17968 case 10:
17969 if (Field_t3_Slot_inst_get (insn) == 0 &&
17970 Field_tlo_Slot_inst_get (insn) == 0 &&
17971 Field_r3_Slot_inst_get (insn) == 0)
17972 return 291; /* mula.dd.lh.ldinc */
17973 break;
17974 case 11:
17975 if (Field_t3_Slot_inst_get (insn) == 0 &&
17976 Field_tlo_Slot_inst_get (insn) == 0 &&
17977 Field_r3_Slot_inst_get (insn) == 0)
17978 return 293; /* mula.dd.hh.ldinc */
17979 break;
17980 }
17981 break;
43cd72b9 17982 case 1:
7aa09196
SA		 17983 switch (Field_op1_Slot_inst_get (insn))
17984 {
17985 case 8:
17986 if (Field_t3_Slot_inst_get (insn) == 0 &&
17987 Field_tlo_Slot_inst_get (insn) == 0 &&
17988 Field_r3_Slot_inst_get (insn) == 0)
17989 return 286; /* mula.dd.ll.lddec */
17990 break;
17991 case 9:
17992 if (Field_t3_Slot_inst_get (insn) == 0 &&
17993 Field_tlo_Slot_inst_get (insn) == 0 &&
17994 Field_r3_Slot_inst_get (insn) == 0)
17995 return 288; /* mula.dd.hl.lddec */
17996 break;
17997 case 10:
17998 if (Field_t3_Slot_inst_get (insn) == 0 &&
17999 Field_tlo_Slot_inst_get (insn) == 0 &&
18000 Field_r3_Slot_inst_get (insn) == 0)
18001 return 290; /* mula.dd.lh.lddec */
18002 break;
18003 case 11:
18004 if (Field_t3_Slot_inst_get (insn) == 0 &&
18005 Field_tlo_Slot_inst_get (insn) == 0 &&
18006 Field_r3_Slot_inst_get (insn) == 0)
18007 return 292; /* mula.dd.hh.lddec */
18008 break;
18009 }
18010 break;
43cd72b9 18011 case 2:
7aa09196
SA		 18012 switch (Field_op1_Slot_inst_get (insn))
18013 {
18014 case 4:
18015 if (Field_s_Slot_inst_get (insn) == 0 &&
18016 Field_w_Slot_inst_get (insn) == 0 &&
18017 Field_r3_Slot_inst_get (insn) == 0 &&
18018 Field_t3_Slot_inst_get (insn) == 0 &&
18019 Field_tlo_Slot_inst_get (insn) == 0)
18020 return 242; /* mul.dd.ll */
18021 break;
18022 case 5:
18023 if (Field_s_Slot_inst_get (insn) == 0 &&
18024 Field_w_Slot_inst_get (insn) == 0 &&
18025 Field_r3_Slot_inst_get (insn) == 0 &&
18026 Field_t3_Slot_inst_get (insn) == 0 &&
18027 Field_tlo_Slot_inst_get (insn) == 0)
18028 return 243; /* mul.dd.hl */
18029 break;
18030 case 6:
18031 if (Field_s_Slot_inst_get (insn) == 0 &&
18032 Field_w_Slot_inst_get (insn) == 0 &&
18033 Field_r3_Slot_inst_get (insn) == 0 &&
18034 Field_t3_Slot_inst_get (insn) == 0 &&
18035 Field_tlo_Slot_inst_get (insn) == 0)
18036 return 244; /* mul.dd.lh */
18037 break;
18038 case 7:
18039 if (Field_s_Slot_inst_get (insn) == 0 &&
18040 Field_w_Slot_inst_get (insn) == 0 &&
18041 Field_r3_Slot_inst_get (insn) == 0 &&
18042 Field_t3_Slot_inst_get (insn) == 0 &&
18043 Field_tlo_Slot_inst_get (insn) == 0)
18044 return 245; /* mul.dd.hh */
18045 break;
18046 case 8:
18047 if (Field_s_Slot_inst_get (insn) == 0 &&
18048 Field_w_Slot_inst_get (insn) == 0 &&
18049 Field_r3_Slot_inst_get (insn) == 0 &&
18050 Field_t3_Slot_inst_get (insn) == 0 &&
18051 Field_tlo_Slot_inst_get (insn) == 0)
18052 return 270; /* mula.dd.ll */
18053 break;
18054 case 9:
18055 if (Field_s_Slot_inst_get (insn) == 0 &&
18056 Field_w_Slot_inst_get (insn) == 0 &&
18057 Field_r3_Slot_inst_get (insn) == 0 &&
18058 Field_t3_Slot_inst_get (insn) == 0 &&
18059 Field_tlo_Slot_inst_get (insn) == 0)
18060 return 271; /* mula.dd.hl */
18061 break;
18062 case 10:
18063 if (Field_s_Slot_inst_get (insn) == 0 &&
18064 Field_w_Slot_inst_get (insn) == 0 &&
18065 Field_r3_Slot_inst_get (insn) == 0 &&
18066 Field_t3_Slot_inst_get (insn) == 0 &&
18067 Field_tlo_Slot_inst_get (insn) == 0)
18068 return 272; /* mula.dd.lh */
18069 break;
18070 case 11:
18071 if (Field_s_Slot_inst_get (insn) == 0 &&
18072 Field_w_Slot_inst_get (insn) == 0 &&
18073 Field_r3_Slot_inst_get (insn) == 0 &&
18074 Field_t3_Slot_inst_get (insn) == 0 &&
18075 Field_tlo_Slot_inst_get (insn) == 0)
18076 return 273; /* mula.dd.hh */
18077 break;
18078 case 12:
18079 if (Field_s_Slot_inst_get (insn) == 0 &&
18080 Field_w_Slot_inst_get (insn) == 0 &&
18081 Field_r3_Slot_inst_get (insn) == 0 &&
18082 Field_t3_Slot_inst_get (insn) == 0 &&
18083 Field_tlo_Slot_inst_get (insn) == 0)
18084 return 274; /* muls.dd.ll */
18085 break;
18086 case 13:
18087 if (Field_s_Slot_inst_get (insn) == 0 &&
18088 Field_w_Slot_inst_get (insn) == 0 &&
18089 Field_r3_Slot_inst_get (insn) == 0 &&
18090 Field_t3_Slot_inst_get (insn) == 0 &&
18091 Field_tlo_Slot_inst_get (insn) == 0)
18092 return 275; /* muls.dd.hl */
18093 break;
18094 case 14:
18095 if (Field_s_Slot_inst_get (insn) == 0 &&
18096 Field_w_Slot_inst_get (insn) == 0 &&
18097 Field_r3_Slot_inst_get (insn) == 0 &&
18098 Field_t3_Slot_inst_get (insn) == 0 &&
18099 Field_tlo_Slot_inst_get (insn) == 0)
18100 return 276; /* muls.dd.lh */
18101 break;
18102 case 15:
18103 if (Field_s_Slot_inst_get (insn) == 0 &&
18104 Field_w_Slot_inst_get (insn) == 0 &&
18105 Field_r3_Slot_inst_get (insn) == 0 &&
18106 Field_t3_Slot_inst_get (insn) == 0 &&
18107 Field_tlo_Slot_inst_get (insn) == 0)
18108 return 277; /* muls.dd.hh */
18109 break;
18110 }
18111 break;
18112 case 3:
18113 switch (Field_op1_Slot_inst_get (insn))
18114 {
18115 case 4:
18116 if (Field_r_Slot_inst_get (insn) == 0 &&
18117 Field_t3_Slot_inst_get (insn) == 0 &&
18118 Field_tlo_Slot_inst_get (insn) == 0)
18119 return 234; /* mul.ad.ll */
18120 break;
18121 case 5:
18122 if (Field_r_Slot_inst_get (insn) == 0 &&
18123 Field_t3_Slot_inst_get (insn) == 0 &&
18124 Field_tlo_Slot_inst_get (insn) == 0)
18125 return 235; /* mul.ad.hl */
18126 break;
18127 case 6:
18128 if (Field_r_Slot_inst_get (insn) == 0 &&
18129 Field_t3_Slot_inst_get (insn) == 0 &&
18130 Field_tlo_Slot_inst_get (insn) == 0)
18131 return 236; /* mul.ad.lh */
18132 break;
18133 case 7:
18134 if (Field_r_Slot_inst_get (insn) == 0 &&
18135 Field_t3_Slot_inst_get (insn) == 0 &&
18136 Field_tlo_Slot_inst_get (insn) == 0)
18137 return 237; /* mul.ad.hh */
18138 break;
18139 case 8:
18140 if (Field_r_Slot_inst_get (insn) == 0 &&
18141 Field_t3_Slot_inst_get (insn) == 0 &&
18142 Field_tlo_Slot_inst_get (insn) == 0)
18143 return 254; /* mula.ad.ll */
18144 break;
18145 case 9:
18146 if (Field_r_Slot_inst_get (insn) == 0 &&
18147 Field_t3_Slot_inst_get (insn) == 0 &&
18148 Field_tlo_Slot_inst_get (insn) == 0)
18149 return 255; /* mula.ad.hl */
18150 break;
18151 case 10:
18152 if (Field_r_Slot_inst_get (insn) == 0 &&
18153 Field_t3_Slot_inst_get (insn) == 0 &&
18154 Field_tlo_Slot_inst_get (insn) == 0)
18155 return 256; /* mula.ad.lh */
18156 break;
18157 case 11:
18158 if (Field_r_Slot_inst_get (insn) == 0 &&
18159 Field_t3_Slot_inst_get (insn) == 0 &&
18160 Field_tlo_Slot_inst_get (insn) == 0)
18161 return 257; /* mula.ad.hh */
18162 break;
18163 case 12:
18164 if (Field_r_Slot_inst_get (insn) == 0 &&
18165 Field_t3_Slot_inst_get (insn) == 0 &&
18166 Field_tlo_Slot_inst_get (insn) == 0)
18167 return 258; /* muls.ad.ll */
18168 break;
18169 case 13:
18170 if (Field_r_Slot_inst_get (insn) == 0 &&
18171 Field_t3_Slot_inst_get (insn) == 0 &&
18172 Field_tlo_Slot_inst_get (insn) == 0)
18173 return 259; /* muls.ad.hl */
18174 break;
18175 case 14:
18176 if (Field_r_Slot_inst_get (insn) == 0 &&
18177 Field_t3_Slot_inst_get (insn) == 0 &&
18178 Field_tlo_Slot_inst_get (insn) == 0)
18179 return 260; /* muls.ad.lh */
18180 break;
18181 case 15:
18182 if (Field_r_Slot_inst_get (insn) == 0 &&
18183 Field_t3_Slot_inst_get (insn) == 0 &&
18184 Field_tlo_Slot_inst_get (insn) == 0)
18185 return 261; /* muls.ad.hh */
18186 break;
18187 }
18188 break;
43cd72b9 18189 case 4:
7aa09196
SA		 18190 switch (Field_op1_Slot_inst_get (insn))
18191 {
18192 case 8:
18193 if (Field_r3_Slot_inst_get (insn) == 0)
18194 return 279; /* mula.da.ll.ldinc */
18195 break;
18196 case 9:
18197 if (Field_r3_Slot_inst_get (insn) == 0)
18198 return 281; /* mula.da.hl.ldinc */
18199 break;
18200 case 10:
18201 if (Field_r3_Slot_inst_get (insn) == 0)
18202 return 283; /* mula.da.lh.ldinc */
18203 break;
18204 case 11:
18205 if (Field_r3_Slot_inst_get (insn) == 0)
18206 return 285; /* mula.da.hh.ldinc */
18207 break;
18208 }
18209 break;
43cd72b9 18210 case 5:
7aa09196
SA		 18211 switch (Field_op1_Slot_inst_get (insn))
18212 {
18213 case 8:
18214 if (Field_r3_Slot_inst_get (insn) == 0)
18215 return 278; /* mula.da.ll.lddec */
18216 break;
18217 case 9:
18218 if (Field_r3_Slot_inst_get (insn) == 0)
18219 return 280; /* mula.da.hl.lddec */
18220 break;
18221 case 10:
18222 if (Field_r3_Slot_inst_get (insn) == 0)
18223 return 282; /* mula.da.lh.lddec */
18224 break;
18225 case 11:
18226 if (Field_r3_Slot_inst_get (insn) == 0)
18227 return 284; /* mula.da.hh.lddec */
18228 break;
18229 }
18230 break;
43cd72b9 18231 case 6:
7aa09196
SA		 18232 switch (Field_op1_Slot_inst_get (insn))
18233 {
18234 case 4:
18235 if (Field_s_Slot_inst_get (insn) == 0 &&
18236 Field_w_Slot_inst_get (insn) == 0 &&
18237 Field_r3_Slot_inst_get (insn) == 0)
18238 return 238; /* mul.da.ll */
18239 break;
18240 case 5:
18241 if (Field_s_Slot_inst_get (insn) == 0 &&
18242 Field_w_Slot_inst_get (insn) == 0 &&
18243 Field_r3_Slot_inst_get (insn) == 0)
18244 return 239; /* mul.da.hl */
18245 break;
18246 case 6:
18247 if (Field_s_Slot_inst_get (insn) == 0 &&
18248 Field_w_Slot_inst_get (insn) == 0 &&
18249 Field_r3_Slot_inst_get (insn) == 0)
18250 return 240; /* mul.da.lh */
18251 break;
18252 case 7:
18253 if (Field_s_Slot_inst_get (insn) == 0 &&
18254 Field_w_Slot_inst_get (insn) == 0 &&
18255 Field_r3_Slot_inst_get (insn) == 0)
18256 return 241; /* mul.da.hh */
18257 break;
18258 case 8:
18259 if (Field_s_Slot_inst_get (insn) == 0 &&
18260 Field_w_Slot_inst_get (insn) == 0 &&
18261 Field_r3_Slot_inst_get (insn) == 0)
18262 return 262; /* mula.da.ll */
18263 break;
18264 case 9:
18265 if (Field_s_Slot_inst_get (insn) == 0 &&
18266 Field_w_Slot_inst_get (insn) == 0 &&
18267 Field_r3_Slot_inst_get (insn) == 0)
18268 return 263; /* mula.da.hl */
18269 break;
18270 case 10:
18271 if (Field_s_Slot_inst_get (insn) == 0 &&
18272 Field_w_Slot_inst_get (insn) == 0 &&
18273 Field_r3_Slot_inst_get (insn) == 0)
18274 return 264; /* mula.da.lh */
18275 break;
18276 case 11:
18277 if (Field_s_Slot_inst_get (insn) == 0 &&
18278 Field_w_Slot_inst_get (insn) == 0 &&
18279 Field_r3_Slot_inst_get (insn) == 0)
18280 return 265; /* mula.da.hh */
18281 break;
18282 case 12:
18283 if (Field_s_Slot_inst_get (insn) == 0 &&
18284 Field_w_Slot_inst_get (insn) == 0 &&
18285 Field_r3_Slot_inst_get (insn) == 0)
18286 return 266; /* muls.da.ll */
18287 break;
18288 case 13:
18289 if (Field_s_Slot_inst_get (insn) == 0 &&
18290 Field_w_Slot_inst_get (insn) == 0 &&
18291 Field_r3_Slot_inst_get (insn) == 0)
18292 return 267; /* muls.da.hl */
18293 break;
18294 case 14:
18295 if (Field_s_Slot_inst_get (insn) == 0 &&
18296 Field_w_Slot_inst_get (insn) == 0 &&
18297 Field_r3_Slot_inst_get (insn) == 0)
18298 return 268; /* muls.da.lh */
18299 break;
18300 case 15:
18301 if (Field_s_Slot_inst_get (insn) == 0 &&
18302 Field_w_Slot_inst_get (insn) == 0 &&
18303 Field_r3_Slot_inst_get (insn) == 0)
18304 return 269; /* muls.da.hh */
18305 break;
18306 }
18307 break;
43cd72b9 18308 case 7:
7aa09196 18309 switch (Field_op1_Slot_inst_get (insn))
43cd72b9
BW		 18310 {
18311 case 0:
7aa09196
SA		 18312 if (Field_r_Slot_inst_get (insn) == 0)
18313 return 230; /* umul.aa.ll */
18314 break;
43cd72b9 18315 case 1:
7aa09196
SA		 18316 if (Field_r_Slot_inst_get (insn) == 0)
18317 return 231; /* umul.aa.hl */
18318 break;
43cd72b9 18319 case 2:
7aa09196
SA		 18320 if (Field_r_Slot_inst_get (insn) == 0)
18321 return 232; /* umul.aa.lh */
18322 break;
43cd72b9 18323 case 3:
7aa09196
SA		 18324 if (Field_r_Slot_inst_get (insn) == 0)
18325 return 233; /* umul.aa.hh */
18326 break;
43cd72b9 18327 case 4:
7aa09196
SA		 18328 if (Field_r_Slot_inst_get (insn) == 0)
18329 return 226; /* mul.aa.ll */
18330 break;
43cd72b9 18331 case 5:
7aa09196
SA		 18332 if (Field_r_Slot_inst_get (insn) == 0)
18333 return 227; /* mul.aa.hl */
18334 break;
43cd72b9 18335 case 6:
7aa09196
SA		 18336 if (Field_r_Slot_inst_get (insn) == 0)
18337 return 228; /* mul.aa.lh */
18338 break;
43cd72b9 18339 case 7:
7aa09196
SA		 18340 if (Field_r_Slot_inst_get (insn) == 0)
18341 return 229; /* mul.aa.hh */
18342 break;
43cd72b9 18343 case 8:
7aa09196
SA		 18344 if (Field_r_Slot_inst_get (insn) == 0)
18345 return 246; /* mula.aa.ll */
18346 break;
18347 case 9:
18348 if (Field_r_Slot_inst_get (insn) == 0)
18349 return 247; /* mula.aa.hl */
18350 break;
18351 case 10:
18352 if (Field_r_Slot_inst_get (insn) == 0)
18353 return 248; /* mula.aa.lh */
18354 break;
18355 case 11:
18356 if (Field_r_Slot_inst_get (insn) == 0)
18357 return 249; /* mula.aa.hh */
43cd72b9
BW		 18358 break;
18359 case 12:
7aa09196
SA		 18360 if (Field_r_Slot_inst_get (insn) == 0)
18361 return 250; /* muls.aa.ll */
18362 break;
33430bd0 18363 case 13:
7aa09196
SA		 18364 if (Field_r_Slot_inst_get (insn) == 0)
18365 return 251; /* muls.aa.hl */
33430bd0 18366 break;
43cd72b9 18367 case 14:
7aa09196
SA		 18368 if (Field_r_Slot_inst_get (insn) == 0)
18369 return 252; /* muls.aa.lh */
18370 break;
43cd72b9 18371 case 15:
7aa09196
SA		 18372 if (Field_r_Slot_inst_get (insn) == 0)
18373 return 253; /* muls.aa.hh */
18374 break;
43cd72b9
BW		 18375 }
18376 break;
7aa09196
SA		 18377 case 8:
18378 if (Field_op1_Slot_inst_get (insn) == 0 &&
18379 Field_t_Slot_inst_get (insn) == 0 &&
18380 Field_rhi_Slot_inst_get (insn) == 0)
18381 return 295; /* ldinc */
18382 break;
43cd72b9 18383 case 9:
7aa09196
SA		 18384 if (Field_op1_Slot_inst_get (insn) == 0 &&
18385 Field_t_Slot_inst_get (insn) == 0 &&
18386 Field_rhi_Slot_inst_get (insn) == 0)
18387 return 294; /* lddec */
18388 break;
43cd72b9 18389 }
e0001a05 18390 break;
43cd72b9
BW		 18391 case 5:
18392 switch (Field_n_Slot_inst_get (insn))
18393 {
18394 case 0:
7aa09196 18395 return 76; /* call0 */
43cd72b9 18396 case 1:
7aa09196 18397 return 7; /* call4 */
43cd72b9 18398 case 2:
7aa09196 18399 return 6; /* call8 */
43cd72b9 18400 case 3:
7aa09196 18401 return 5; /* call12 */
43cd72b9 18402 }
e0001a05 18403 break;
43cd72b9
BW		 18404 case 6:
18405 switch (Field_n_Slot_inst_get (insn))
18406 {
18407 case 0:
7aa09196 18408 return 80; /* j */
43cd72b9
BW		 18409 case 1:
18410 switch (Field_m_Slot_inst_get (insn))
18411 {
18412 case 0:
7aa09196 18413 return 72; /* beqz */
43cd72b9 18414 case 1:
7aa09196 18415 return 73; /* bnez */
43cd72b9 18416 case 2:
7aa09196 18417 return 75; /* bltz */
43cd72b9 18418 case 3:
7aa09196 18419 return 74; /* bgez */
43cd72b9
BW		 18420 }
18421 break;
18422 case 2:
18423 switch (Field_m_Slot_inst_get (insn))
18424 {
18425 case 0:
7aa09196 18426 return 52; /* beqi */
43cd72b9 18427 case 1:
7aa09196 18428 return 53; /* bnei */
43cd72b9 18429 case 2:
7aa09196 18430 return 55; /* blti */
43cd72b9 18431 case 3:
7aa09196 18432 return 54; /* bgei */
43cd72b9
BW		 18433 }
18434 break;
18435 case 3:
18436 switch (Field_m_Slot_inst_get (insn))
18437 {
18438 case 0:
7aa09196 18439 return 11; /* entry */
43cd72b9
BW		 18440 case 1:
18441 switch (Field_r_Slot_inst_get (insn))
18442 {
7aa09196
SA		 18443 case 0:
18444 return 371; /* bf */
18445 case 1:
18446 return 372; /* bt */
43cd72b9 18447 case 8:
7aa09196 18448 return 87; /* loop */
43cd72b9 18449 case 9:
7aa09196 18450 return 88; /* loopnez */
43cd72b9 18451 case 10:
7aa09196 18452 return 89; /* loopgtz */
43cd72b9
BW		 18453 }
18454 break;
18455 case 2:
7aa09196 18456 return 59; /* bltui */
43cd72b9 18457 case 3:
7aa09196 18458 return 58; /* bgeui */
43cd72b9
BW		 18459 }
18460 break;
18461 }
e0001a05 18462 break;
43cd72b9
BW		 18463 case 7:
18464 switch (Field_r_Slot_inst_get (insn))
18465 {
18466 case 0:
7aa09196 18467 return 67; /* bnone */
43cd72b9 18468 case 1:
7aa09196 18469 return 60; /* beq */
43cd72b9 18470 case 2:
7aa09196 18471 return 63; /* blt */
43cd72b9 18472 case 3:
7aa09196 18473 return 65; /* bltu */
43cd72b9 18474 case 4:
7aa09196 18475 return 68; /* ball */
43cd72b9 18476 case 5:
7aa09196 18477 return 70; /* bbc */
43cd72b9
BW		 18478 case 6:
18479 case 7:
7aa09196 18480 return 56; /* bbci */
43cd72b9 18481 case 8:
7aa09196 18482 return 66; /* bany */
43cd72b9 18483 case 9:
7aa09196 18484 return 61; /* bne */
43cd72b9 18485 case 10:
7aa09196 18486 return 62; /* bge */
43cd72b9 18487 case 11:
7aa09196 18488 return 64; /* bgeu */
43cd72b9 18489 case 12:
7aa09196 18490 return 69; /* bnall */
43cd72b9 18491 case 13:
7aa09196 18492 return 71; /* bbs */
43cd72b9
BW		 18493 case 14:
18494 case 15:
7aa09196 18495 return 57; /* bbsi */
43cd72b9 18496 }
e0001a05 18497 break;
e0001a05 18498 }
43cd72b9
BW		 18499 return 0;
18500}
18501
18502static int
18503Slot_inst16b_decode (const xtensa_insnbuf insn)
18504{
18505 switch (Field_op0_Slot_inst16b_get (insn))
18506 {
18507 case 12:
7aa09196
SA		 18508 switch (Field_i_Slot_inst16b_get (insn))
18509 {
18510 case 0:
18511 return 33; /* movi.n */
18512 case 1:
18513 switch (Field_z_Slot_inst16b_get (insn))
18514 {
18515 case 0:
18516 return 28; /* beqz.n */
18517 case 1:
18518 return 29; /* bnez.n */
18519 }
18520 break;
18521 }
18522 break;
18523 case 13:
18524 switch (Field_r_Slot_inst16b_get (insn))
18525 {
18526 case 0:
18527 return 32; /* mov.n */
18528 case 15:
18529 switch (Field_t_Slot_inst16b_get (insn))
18530 {
18531 case 0:
18532 return 35; /* ret.n */
18533 case 1:
18534 return 15; /* retw.n */
18535 case 2:
18536 return 325; /* break.n */
18537 case 3:
18538 if (Field_s_Slot_inst16b_get (insn) == 0)
18539 return 34; /* nop.n */
18540 break;
18541 case 6:
18542 if (Field_s_Slot_inst16b_get (insn) == 0)
18543 return 30; /* ill.n */
18544 break;
18545 }
18546 break;
18547 }
18548 break;
18549 }
18550 return 0;
18551}
18552
18553static int
18554Slot_inst16a_decode (const xtensa_insnbuf insn)
18555{
18556 switch (Field_op0_Slot_inst16a_get (insn))
18557 {
18558 case 8:
18559 return 31; /* l32i.n */
18560 case 9:
18561 return 36; /* s32i.n */
18562 case 10:
18563 return 26; /* add.n */
18564 case 11:
18565 return 27; /* addi.n */
18566 }
18567 return 0;
18568}
18569
18570static int
18571Slot_xt_flix64_slot2_decode (const xtensa_insnbuf insn)
18572{
18573 switch (Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn))
18574 {
18575 case 0:
18576 if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 1)
18577 return 41; /* add */
18578 if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 5)
18579 return 42; /* sub */
18580 if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 2)
18581 return 43; /* addx2 */
18582 if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 3)
18583 return 49; /* and */
18584 if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 4)
18585 return 450; /* sext */
18586 break;
18587 case 1:
18588 if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 1)
18589 return 27; /* addi.n */
18590 if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 2)
18591 return 44; /* addx4 */
18592 if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 3)
18593 return 50; /* or */
18594 if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 5)
18595 return 51; /* xor */
18596 if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 4)
18597 return 113; /* srli */
18598 break;
18599 }
18600 if (Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0 &&
18601 Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6)
18602 return 33; /* movi.n */
18603 if (Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 2 &&
18604 Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
18605 Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
18606 return 32; /* mov.n */
18607 if (Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 3 &&
18608 Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
18609 Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
18610 return 97; /* nop */
18611 if (Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 8 &&
18612 Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
18613 Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
18614 return 96; /* abs */
18615 if (Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 9 &&
18616 Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
18617 Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
18618 return 95; /* neg */
18619 if (Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 5 &&
18620 Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
18621 Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
18622 return 110; /* sra */
18623 if (Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 3 &&
18624 Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
18625 Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
18626 return 109; /* srl */
18627 if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 7)
18628 return 112; /* srai */
18629 return 0;
18630}
18631
18632static int
18633Slot_xt_flix64_slot0_decode (const xtensa_insnbuf insn)
18634{
18635 switch (Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get (insn))
18636 {
18637 case 0:
18638 if (Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get (insn) == 2)
18639 return 78; /* extui */
18640 switch (Field_op1_Slot_xt_flix64_slot0_get (insn))
18641 {
18642 case 0:
18643 switch (Field_op2_Slot_xt_flix64_slot0_get (insn))
18644 {
18645 case 0:
18646 if (Field_r_Slot_xt_flix64_slot0_get (insn) == 2)
18647 {
18648 if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0)
18649 {
18650 if (Field_t_Slot_xt_flix64_slot0_get (insn) == 15)
18651 return 97; /* nop */
18652 }
18653 }
18654 break;
18655 case 1:
18656 return 49; /* and */
18657 case 2:
18658 return 50; /* or */
18659 case 3:
18660 return 51; /* xor */
18661 case 4:
18662 switch (Field_r_Slot_xt_flix64_slot0_get (insn))
18663 {
18664 case 0:
18665 if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
18666 return 102; /* ssr */
18667 break;
18668 case 1:
18669 if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
18670 return 103; /* ssl */
18671 break;
18672 case 2:
18673 if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
18674 return 104; /* ssa8l */
18675 break;
18676 case 3:
18677 if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
18678 return 105; /* ssa8b */
18679 break;
18680 case 4:
18681 if (Field_thi3_Slot_xt_flix64_slot0_get (insn) == 0)
18682 return 106; /* ssai */
18683 break;
18684 case 14:
18685 return 448; /* nsa */
18686 case 15:
18687 return 449; /* nsau */
18688 }
18689 break;
18690 case 6:
18691 switch (Field_s_Slot_xt_flix64_slot0_get (insn))
18692 {
18693 case 0:
18694 return 95; /* neg */
18695 case 1:
18696 return 96; /* abs */
18697 }
18698 break;
18699 case 8:
18700 return 41; /* add */
18701 case 9:
18702 return 43; /* addx2 */
18703 case 10:
18704 return 44; /* addx4 */
18705 case 11:
18706 return 45; /* addx8 */
18707 case 12:
18708 return 42; /* sub */
18709 case 13:
18710 return 46; /* subx2 */
18711 case 14:
18712 return 47; /* subx4 */
18713 case 15:
18714 return 48; /* subx8 */
18715 }
18716 break;
18717 case 1:
18718 if (Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get (insn) == 1)
18719 return 112; /* srai */
18720 if (Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get (insn) == 0)
18721 return 111; /* slli */
18722 switch (Field_op2_Slot_xt_flix64_slot0_get (insn))
18723 {
18724 case 4:
18725 return 113; /* srli */
18726 case 8:
18727 return 108; /* src */
18728 case 9:
18729 if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0)
18730 return 109; /* srl */
18731 break;
18732 case 10:
18733 if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
18734 return 107; /* sll */
18735 break;
18736 case 11:
18737 if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0)
18738 return 110; /* sra */
18739 break;
18740 case 12:
18741 return 296; /* mul16u */
18742 case 13:
18743 return 297; /* mul16s */
18744 }
18745 break;
18746 case 2:
18747 if (Field_op2_Slot_xt_flix64_slot0_get (insn) == 8)
18748 return 461; /* mull */
18749 break;
18750 case 3:
18751 switch (Field_op2_Slot_xt_flix64_slot0_get (insn))
18752 {
18753 case 2:
18754 return 450; /* sext */
18755 case 3:
18756 return 443; /* clamps */
18757 case 4:
18758 return 444; /* min */
18759 case 5:
18760 return 445; /* max */
18761 case 6:
18762 return 446; /* minu */
18763 case 7:
18764 return 447; /* maxu */
18765 case 8:
18766 return 91; /* moveqz */
18767 case 9:
18768 return 92; /* movnez */
18769 case 10:
18770 return 93; /* movltz */
18771 case 11:
18772 return 94; /* movgez */
18773 }
18774 break;
18775 }
18776 break;
18777 case 2:
18778 switch (Field_r_Slot_xt_flix64_slot0_get (insn))
18779 {
18780 case 0:
18781 return 86; /* l8ui */
18782 case 1:
18783 return 82; /* l16ui */
18784 case 2:
18785 return 84; /* l32i */
18786 case 4:
18787 return 101; /* s8i */
18788 case 5:
18789 return 99; /* s16i */
18790 case 6:
18791 return 100; /* s32i */
18792 case 9:
18793 return 83; /* l16si */
18794 case 10:
18795 return 90; /* movi */
18796 case 12:
18797 return 39; /* addi */
18798 case 13:
18799 return 40; /* addmi */
18800 }
18801 break;
18802 }
18803 if (Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (insn) == 1)
18804 return 85; /* l32r */
18805 if (Field_sae4_Slot_xt_flix64_slot0_get (insn) == 0 &&
18806 Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get (insn) == 3 &&
18807 Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (insn) == 0 &&
18808 Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get (insn) == 0)
18809 return 32; /* mov.n */
18810 return 0;
18811}
18812
18813static int
18814Slot_xt_flix64_slot1_decode (const xtensa_insnbuf insn)
18815{
18816 if (Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0 &&
18817 Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1)
18818 return 78; /* extui */
18819 switch (Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn))
18820 {
18821 case 0:
18822 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18823 return 90; /* movi */
18824 break;
18825 case 2:
18826 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1)
18827 return 39; /* addi */
18828 break;
18829 case 3:
18830 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1)
18831 return 40; /* addmi */
18832 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18833 Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get (insn) == 0)
18834 return 51; /* xor */
18835 break;
18836 }
18837 switch (Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn))
18838 {
18839 case 8:
18840 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18841 return 111; /* slli */
18842 break;
18843 case 16:
18844 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18845 return 112; /* srai */
18846 break;
18847 case 19:
18848 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18849 Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18850 return 107; /* sll */
18851 break;
18852 }
18853 switch (Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn))
18854 {
18855 case 18:
18856 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18857 return 41; /* add */
18858 break;
18859 case 19:
18860 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18861 return 45; /* addx8 */
18862 break;
18863 case 20:
18864 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18865 return 43; /* addx2 */
18866 break;
18867 case 21:
18868 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18869 return 49; /* and */
18870 break;
18871 case 22:
18872 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18873 return 91; /* moveqz */
18874 break;
18875 case 23:
18876 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18877 return 94; /* movgez */
18878 break;
18879 case 24:
18880 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18881 return 44; /* addx4 */
18882 break;
18883 case 25:
18884 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18885 return 93; /* movltz */
18886 break;
18887 case 26:
18888 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18889 return 92; /* movnez */
18890 break;
18891 case 27:
18892 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18893 return 296; /* mul16u */
18894 break;
18895 case 28:
18896 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18897 return 297; /* mul16s */
18898 break;
18899 case 29:
18900 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18901 return 461; /* mull */
18902 break;
18903 case 30:
18904 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18905 return 50; /* or */
18906 break;
18907 case 31:
18908 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18909 return 450; /* sext */
18910 break;
18911 case 34:
18912 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18913 return 108; /* src */
18914 break;
18915 case 36:
18916 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
18917 return 113; /* srli */
18918 break;
18919 }
18920 if (Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 280 &&
18921 Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18922 Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18923 return 32; /* mov.n */
18924 if (Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 281 &&
18925 Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18926 Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18927 return 81; /* jx */
18928 if (Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 141 &&
18929 Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18930 Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18931 return 103; /* ssl */
18932 if (Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 71 &&
18933 Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18934 Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18935 return 97; /* nop */
18936 if (Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 148 &&
18937 Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18938 Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18939 return 95; /* neg */
18940 if (Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 149 &&
18941 Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18942 Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18943 return 110; /* sra */
18944 if (Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 75 &&
18945 Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18946 Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18947 return 109; /* srl */
18948 if (Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 5 &&
18949 Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
18950 Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
18951 return 42; /* sub */
18952 if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 3)
18953 return 80; /* j */
18954 return 0;
18955}
18956
18957static int
18958Slot_xt_flix64_slot3_decode (const xtensa_insnbuf insn)
18959{
18960 switch (Field_op0_s6_Slot_xt_flix64_slot3_get (insn))
18961 {
18962 case 1:
18963 if (Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (insn) == 0)
18964 return 516; /* bbci.w18 */
18965 break;
18966 case 2:
18967 if (Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (insn) == 0)
18968 return 517; /* bbsi.w18 */
18969 break;
18970 case 3:
18971 if (Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18972 return 526; /* ball.w18 */
18973 break;
18974 case 4:
18975 if (Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18976 return 524; /* bany.w18 */
18977 break;
18978 case 5:
18979 if (Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18980 return 528; /* bbc.w18 */
18981 break;
18982 case 6:
18983 if (Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18984 return 529; /* bbs.w18 */
18985 break;
18986 case 7:
18987 if (Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18988 return 518; /* beq.w18 */
18989 break;
18990 case 8:
18991 if (Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18992 return 510; /* beqi.w18 */
18993 break;
18994 case 9:
18995 if (Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
18996 return 520; /* bge.w18 */
18997 break;
18998 case 10:
18999 if (Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19000 return 512; /* bgei.w18 */
19001 break;
19002 case 11:
19003 if (Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19004 return 522; /* bgeu.w18 */
19005 break;
19006 case 12:
19007 if (Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19008 return 514; /* bgeui.w18 */
e0001a05 19009 break;
43cd72b9 19010 case 13:
7aa09196
SA		 19011 if (Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19012 return 521; /* blt.w18 */
19013 break;
19014 case 14:
19015 if (Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19016 return 513; /* blti.w18 */
19017 break;
19018 case 15:
19019 if (Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19020 return 523; /* bltu.w18 */
19021 break;
19022 case 16:
19023 if (Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19024 return 515; /* bltui.w18 */
19025 break;
19026 case 17:
19027 if (Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19028 return 527; /* bnall.w18 */
19029 break;
19030 case 18:
19031 if (Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19032 return 519; /* bne.w18 */
19033 break;
19034 case 19:
19035 if (Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19036 return 511; /* bnei.w18 */
19037 break;
19038 case 20:
19039 if (Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19040 return 525; /* bnone.w18 */
19041 break;
19042 case 21:
19043 if (Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19044 return 506; /* beqz.w18 */
19045 break;
19046 case 22:
19047 if (Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19048 return 508; /* bgez.w18 */
19049 break;
19050 case 23:
19051 if (Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19052 return 509; /* bltz.w18 */
19053 break;
19054 case 24:
19055 if (Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19056 return 507; /* bnez.w18 */
19057 break;
19058 case 25:
19059 if (Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
19060 return 97; /* nop */
e0001a05
NC		 19061 break;
19062 }
43cd72b9
BW		 19063 return 0;
19064}
19065
7aa09196
SA		 19066\f
19067/* Instruction slots. */
19068
19069static void
19070Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
19071 xtensa_insnbuf slotbuf)
19072{
19073 slotbuf[1] = 0;
19074 slotbuf[0] = (insn[0] & 0xffffff);
19075}
19076
19077static void
19078Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
19079 const xtensa_insnbuf slotbuf)
19080{
19081 insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
19082}
19083
19084static void
19085Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
19086 xtensa_insnbuf slotbuf)
19087{
19088 slotbuf[1] = 0;
19089 slotbuf[0] = (insn[0] & 0xffff);
19090}
19091
19092static void
19093Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
19094 const xtensa_insnbuf slotbuf)
19095{
19096 insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
19097}
19098
19099static void
19100Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
19101 xtensa_insnbuf slotbuf)
19102{
19103 slotbuf[1] = 0;
19104 slotbuf[0] = (insn[0] & 0xffff);
19105}
19106
19107static void
19108Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
19109 const xtensa_insnbuf slotbuf)
19110{
19111 insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
19112}
19113
19114static void
19115Slot_xt_format1_Format_xt_flix64_slot0_4_get (const xtensa_insnbuf insn,
19116 xtensa_insnbuf slotbuf)
19117{
19118 slotbuf[1] = 0;
19119 slotbuf[0] = ((insn[0] & 0xffffff0) >> 4);
19120}
19121
19122static void
19123Slot_xt_format1_Format_xt_flix64_slot0_4_set (xtensa_insnbuf insn,
19124 const xtensa_insnbuf slotbuf)
19125{
19126 insn[0] = (insn[0] & ~0xffffff0) | ((slotbuf[0] & 0xffffff) << 4);
19127}
19128
19129static void
19130Slot_xt_format2_Format_xt_flix64_slot0_4_get (const xtensa_insnbuf insn,
19131 xtensa_insnbuf slotbuf)
19132{
19133 slotbuf[1] = 0;
19134 slotbuf[0] = ((insn[0] & 0xffffff0) >> 4);
19135}
19136
19137static void
19138Slot_xt_format2_Format_xt_flix64_slot0_4_set (xtensa_insnbuf insn,
19139 const xtensa_insnbuf slotbuf)
19140{
19141 insn[0] = (insn[0] & ~0xffffff0) | ((slotbuf[0] & 0xffffff) << 4);
19142}
19143
19144static void
19145Slot_xt_format1_Format_xt_flix64_slot1_28_get (const xtensa_insnbuf insn,
19146 xtensa_insnbuf slotbuf)
19147{
19148 slotbuf[1] = 0;
19149 slotbuf[0] = ((insn[0] & 0xf0000000) >> 28);
19150 slotbuf[0] = (slotbuf[0] & ~0xffff0) | ((insn[1] & 0xffff) << 4);
19151}
19152
19153static void
19154Slot_xt_format1_Format_xt_flix64_slot1_28_set (xtensa_insnbuf insn,
19155 const xtensa_insnbuf slotbuf)
19156{
19157 insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28);
19158 insn[1] = (insn[1] & ~0xffff) | ((slotbuf[0] & 0xffff0) >> 4);
19159}
19160
19161static void
19162Slot_xt_format1_Format_xt_flix64_slot2_48_get (const xtensa_insnbuf insn,
19163 xtensa_insnbuf slotbuf)
19164{
19165 slotbuf[1] = 0;
19166 slotbuf[0] = ((insn[1] & 0xffff0000) >> 16);
19167}
19168
19169static void
19170Slot_xt_format1_Format_xt_flix64_slot2_48_set (xtensa_insnbuf insn,
19171 const xtensa_insnbuf slotbuf)
19172{
19173 insn[1] = (insn[1] & ~0xffff0000) | ((slotbuf[0] & 0xffff) << 16);
19174}
19175
19176static void
19177Slot_xt_format2_Format_xt_flix64_slot3_28_get (const xtensa_insnbuf insn,
19178 xtensa_insnbuf slotbuf)
19179{
19180 slotbuf[0] = ((insn[0] & 0xf0000000) >> 28);
19181 slotbuf[0] = (slotbuf[0] & ~0xfffffff0) | ((insn[1] & 0xfffffff) << 4);
19182 slotbuf[1] = ((insn[1] & 0x70000000) >> 28);
19183}
19184
19185static void
19186Slot_xt_format2_Format_xt_flix64_slot3_28_set (xtensa_insnbuf insn,
19187 const xtensa_insnbuf slotbuf)
19188{
19189 insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28);
19190 insn[1] = (insn[1] & ~0xfffffff) | ((slotbuf[0] & 0xfffffff0) >> 4);
19191 insn[1] = (insn[1] & ~0x70000000) | ((slotbuf[1] & 0x7) << 28);
19192}
19193
19194static xtensa_get_field_fn
19195Slot_inst_get_field_fns[] = {
19196 Field_t_Slot_inst_get,
19197 Field_bbi4_Slot_inst_get,
19198 Field_bbi_Slot_inst_get,
19199 Field_imm12_Slot_inst_get,
19200 Field_imm8_Slot_inst_get,
19201 Field_s_Slot_inst_get,
19202 Field_imm12b_Slot_inst_get,
19203 Field_imm16_Slot_inst_get,
19204 Field_m_Slot_inst_get,
19205 Field_n_Slot_inst_get,
19206 Field_offset_Slot_inst_get,
19207 Field_op0_Slot_inst_get,
19208 Field_op1_Slot_inst_get,
19209 Field_op2_Slot_inst_get,
19210 Field_r_Slot_inst_get,
19211 Field_sa4_Slot_inst_get,
19212 Field_sae4_Slot_inst_get,
19213 Field_sae_Slot_inst_get,
19214 Field_sal_Slot_inst_get,
19215 Field_sargt_Slot_inst_get,
19216 Field_sas4_Slot_inst_get,
19217 Field_sas_Slot_inst_get,
19218 Field_sr_Slot_inst_get,
19219 Field_st_Slot_inst_get,
19220 Field_thi3_Slot_inst_get,
19221 Field_imm4_Slot_inst_get,
19222 Field_mn_Slot_inst_get,
19223 0,
19224 0,
19225 0,
19226 0,
19227 0,
19228 0,
19229 0,
19230 0,
19231 Field_r3_Slot_inst_get,
19232 Field_rbit2_Slot_inst_get,
19233 Field_rhi_Slot_inst_get,
19234 Field_t3_Slot_inst_get,
19235 Field_tbit2_Slot_inst_get,
19236 Field_tlo_Slot_inst_get,
19237 Field_w_Slot_inst_get,
19238 Field_y_Slot_inst_get,
19239 Field_x_Slot_inst_get,
19240 Field_t2_Slot_inst_get,
19241 Field_s2_Slot_inst_get,
19242 Field_r2_Slot_inst_get,
19243 Field_t4_Slot_inst_get,
19244 Field_s4_Slot_inst_get,
19245 Field_r4_Slot_inst_get,
19246 Field_t8_Slot_inst_get,
19247 Field_s8_Slot_inst_get,
19248 Field_r8_Slot_inst_get,
19249 Field_xt_wbr15_imm_Slot_inst_get,
19250 Field_xt_wbr18_imm_Slot_inst_get,
19251 0,
19252 0,
19253 0,
19254 0,
19255 0,
19256 0,
19257 0,
19258 0,
19259 0,
19260 0,
19261 0,
19262 0,
19263 0,
19264 0,
19265 0,
19266 0,
19267 0,
19268 0,
19269 0,
19270 0,
19271 0,
19272 0,
19273 0,
19274 0,
19275 0,
19276 0,
19277 0,
19278 0,
19279 0,
19280 0,
19281 0,
19282 0,
19283 0,
19284 0,
19285 0,
19286 0,
19287 0,
19288 0,
19289 0,
19290 0,
19291 0,
19292 0,
19293 0,
19294 0,
19295 0,
19296 0,
19297 0,
19298 0,
19299 0,
19300 0,
19301 0,
19302 0,
19303 0,
19304 0,
19305 0,
19306 0,
19307 0,
19308 0,
19309 0,
19310 0,
19311 0,
19312 0,
19313 0,
19314 0,
19315 0,
19316 0,
19317 0,
19318 0,
19319 Implicit_Field_ar0_get,
19320 Implicit_Field_ar4_get,
19321 Implicit_Field_ar8_get,
19322 Implicit_Field_ar12_get,
19323 Implicit_Field_mr0_get,
19324 Implicit_Field_mr1_get,
19325 Implicit_Field_mr2_get,
19326 Implicit_Field_mr3_get,
19327 Implicit_Field_bt16_get,
19328 Implicit_Field_bs16_get,
19329 Implicit_Field_br16_get,
19330 Implicit_Field_brall_get
19331};
19332
19333static xtensa_set_field_fn
19334Slot_inst_set_field_fns[] = {
19335 Field_t_Slot_inst_set,
19336 Field_bbi4_Slot_inst_set,
19337 Field_bbi_Slot_inst_set,
19338 Field_imm12_Slot_inst_set,
19339 Field_imm8_Slot_inst_set,
19340 Field_s_Slot_inst_set,
19341 Field_imm12b_Slot_inst_set,
19342 Field_imm16_Slot_inst_set,
19343 Field_m_Slot_inst_set,
19344 Field_n_Slot_inst_set,
19345 Field_offset_Slot_inst_set,
19346 Field_op0_Slot_inst_set,
19347 Field_op1_Slot_inst_set,
19348 Field_op2_Slot_inst_set,
19349 Field_r_Slot_inst_set,
19350 Field_sa4_Slot_inst_set,
19351 Field_sae4_Slot_inst_set,
19352 Field_sae_Slot_inst_set,
19353 Field_sal_Slot_inst_set,
19354 Field_sargt_Slot_inst_set,
19355 Field_sas4_Slot_inst_set,
19356 Field_sas_Slot_inst_set,
19357 Field_sr_Slot_inst_set,
19358 Field_st_Slot_inst_set,
19359 Field_thi3_Slot_inst_set,
19360 Field_imm4_Slot_inst_set,
19361 Field_mn_Slot_inst_set,
19362 0,
19363 0,
19364 0,
19365 0,
19366 0,
19367 0,
19368 0,
19369 0,
19370 Field_r3_Slot_inst_set,
19371 Field_rbit2_Slot_inst_set,
19372 Field_rhi_Slot_inst_set,
19373 Field_t3_Slot_inst_set,
19374 Field_tbit2_Slot_inst_set,
19375 Field_tlo_Slot_inst_set,
19376 Field_w_Slot_inst_set,
19377 Field_y_Slot_inst_set,
19378 Field_x_Slot_inst_set,
19379 Field_t2_Slot_inst_set,
19380 Field_s2_Slot_inst_set,
19381 Field_r2_Slot_inst_set,
19382 Field_t4_Slot_inst_set,
19383 Field_s4_Slot_inst_set,
19384 Field_r4_Slot_inst_set,
19385 Field_t8_Slot_inst_set,
19386 Field_s8_Slot_inst_set,
19387 Field_r8_Slot_inst_set,
19388 Field_xt_wbr15_imm_Slot_inst_set,
19389 Field_xt_wbr18_imm_Slot_inst_set,
19390 0,
19391 0,
19392 0,
19393 0,
19394 0,
19395 0,
19396 0,
19397 0,
19398 0,
19399 0,
19400 0,
19401 0,
19402 0,
19403 0,
19404 0,
19405 0,
19406 0,
19407 0,
19408 0,
19409 0,
19410 0,
19411 0,
19412 0,
19413 0,
19414 0,
19415 0,
19416 0,
19417 0,
19418 0,
19419 0,
19420 0,
19421 0,
19422 0,
19423 0,
19424 0,
19425 0,
19426 0,
19427 0,
19428 0,
19429 0,
19430 0,
19431 0,
19432 0,
19433 0,
19434 0,
19435 0,
19436 0,
19437 0,
19438 0,
19439 0,
19440 0,
19441 0,
19442 0,
19443 0,
19444 0,
19445 0,
19446 0,
19447 0,
19448 0,
19449 0,
19450 0,
19451 0,
19452 0,
19453 0,
19454 0,
19455 0,
19456 0,
19457 0,
19458 Implicit_Field_set,
19459 Implicit_Field_set,
19460 Implicit_Field_set,
19461 Implicit_Field_set,
19462 Implicit_Field_set,
19463 Implicit_Field_set,
19464 Implicit_Field_set,
19465 Implicit_Field_set,
19466 Implicit_Field_set,
19467 Implicit_Field_set,
19468 Implicit_Field_set,
19469 Implicit_Field_set
19470};
19471
19472static xtensa_get_field_fn
19473Slot_inst16a_get_field_fns[] = {
19474 Field_t_Slot_inst16a_get,
19475 0,
19476 0,
19477 0,
19478 0,
19479 Field_s_Slot_inst16a_get,
19480 0,
19481 0,
19482 0,
19483 0,
19484 0,
19485 Field_op0_Slot_inst16a_get,
19486 0,
19487 0,
19488 Field_r_Slot_inst16a_get,
19489 0,
19490 0,
19491 0,
19492 0,
19493 0,
19494 0,
19495 0,
19496 Field_sr_Slot_inst16a_get,
19497 Field_st_Slot_inst16a_get,
19498 0,
19499 Field_imm4_Slot_inst16a_get,
19500 0,
19501 Field_i_Slot_inst16a_get,
19502 Field_imm6lo_Slot_inst16a_get,
19503 Field_imm6hi_Slot_inst16a_get,
19504 Field_imm7lo_Slot_inst16a_get,
19505 Field_imm7hi_Slot_inst16a_get,
19506 Field_z_Slot_inst16a_get,
19507 Field_imm6_Slot_inst16a_get,
19508 Field_imm7_Slot_inst16a_get,
19509 0,
19510 0,
19511 0,
19512 0,
19513 0,
19514 0,
19515 0,
19516 0,
19517 0,
19518 Field_t2_Slot_inst16a_get,
19519 Field_s2_Slot_inst16a_get,
19520 Field_r2_Slot_inst16a_get,
19521 Field_t4_Slot_inst16a_get,
19522 Field_s4_Slot_inst16a_get,
19523 Field_r4_Slot_inst16a_get,
19524 Field_t8_Slot_inst16a_get,
19525 Field_s8_Slot_inst16a_get,
19526 Field_r8_Slot_inst16a_get,
19527 0,
19528 0,
19529 0,
19530 0,
19531 0,
19532 0,
19533 0,
19534 0,
19535 0,
19536 0,
19537 0,
19538 0,
19539 0,
19540 0,
19541 0,
19542 0,
19543 0,
19544 0,
19545 0,
19546 0,
19547 0,
19548 0,
19549 0,
19550 0,
19551 0,
19552 0,
19553 0,
19554 0,
19555 0,
19556 0,
19557 0,
19558 0,
19559 0,
19560 0,
19561 0,
19562 0,
19563 0,
19564 0,
19565 0,
19566 0,
19567 0,
19568 0,
19569 0,
19570 0,
19571 0,
19572 0,
19573 0,
19574 0,
19575 0,
19576 0,
19577 0,
19578 0,
19579 0,
19580 0,
19581 0,
19582 0,
19583 0,
19584 0,
19585 0,
19586 0,
19587 0,
19588 0,
19589 0,
19590 0,
19591 0,
19592 0,
19593 0,
19594 0,
19595 0,
19596 0,
19597 Implicit_Field_ar0_get,
19598 Implicit_Field_ar4_get,
19599 Implicit_Field_ar8_get,
19600 Implicit_Field_ar12_get,
19601 Implicit_Field_mr0_get,
19602 Implicit_Field_mr1_get,
19603 Implicit_Field_mr2_get,
19604 Implicit_Field_mr3_get,
19605 Implicit_Field_bt16_get,
19606 Implicit_Field_bs16_get,
19607 Implicit_Field_br16_get,
19608 Implicit_Field_brall_get
19609};
43cd72b9 19610
7aa09196
SA		 19611static xtensa_set_field_fn
19612Slot_inst16a_set_field_fns[] = {
19613 Field_t_Slot_inst16a_set,
19614 0,
19615 0,
19616 0,
19617 0,
19618 Field_s_Slot_inst16a_set,
19619 0,
19620 0,
19621 0,
19622 0,
19623 0,
19624 Field_op0_Slot_inst16a_set,
19625 0,
19626 0,
19627 Field_r_Slot_inst16a_set,
19628 0,
19629 0,
19630 0,
19631 0,
19632 0,
19633 0,
19634 0,
19635 Field_sr_Slot_inst16a_set,
19636 Field_st_Slot_inst16a_set,
19637 0,
19638 Field_imm4_Slot_inst16a_set,
19639 0,
19640 Field_i_Slot_inst16a_set,
19641 Field_imm6lo_Slot_inst16a_set,
19642 Field_imm6hi_Slot_inst16a_set,
19643 Field_imm7lo_Slot_inst16a_set,
19644 Field_imm7hi_Slot_inst16a_set,
19645 Field_z_Slot_inst16a_set,
19646 Field_imm6_Slot_inst16a_set,
19647 Field_imm7_Slot_inst16a_set,
19648 0,
19649 0,
19650 0,
19651 0,
19652 0,
19653 0,
19654 0,
19655 0,
19656 0,
19657 Field_t2_Slot_inst16a_set,
19658 Field_s2_Slot_inst16a_set,
19659 Field_r2_Slot_inst16a_set,
19660 Field_t4_Slot_inst16a_set,
19661 Field_s4_Slot_inst16a_set,
19662 Field_r4_Slot_inst16a_set,
19663 Field_t8_Slot_inst16a_set,
19664 Field_s8_Slot_inst16a_set,
19665 Field_r8_Slot_inst16a_set,
19666 0,
19667 0,
19668 0,
19669 0,
19670 0,
19671 0,
19672 0,
19673 0,
19674 0,
19675 0,
19676 0,
19677 0,
19678 0,
19679 0,
19680 0,
19681 0,
19682 0,
19683 0,
19684 0,
19685 0,
19686 0,
19687 0,
19688 0,
19689 0,
19690 0,
19691 0,
19692 0,
19693 0,
19694 0,
19695 0,
19696 0,
19697 0,
19698 0,
19699 0,
19700 0,
19701 0,
19702 0,
19703 0,
19704 0,
19705 0,
19706 0,
19707 0,
19708 0,
19709 0,
19710 0,
19711 0,
19712 0,
19713 0,
19714 0,
19715 0,
19716 0,
19717 0,
19718 0,
19719 0,
19720 0,
19721 0,
19722 0,
19723 0,
19724 0,
19725 0,
19726 0,
19727 0,
19728 0,
19729 0,
19730 0,
19731 0,
19732 0,
19733 0,
19734 0,
19735 0,
19736 Implicit_Field_set,
19737 Implicit_Field_set,
19738 Implicit_Field_set,
19739 Implicit_Field_set,
19740 Implicit_Field_set,
19741 Implicit_Field_set,
19742 Implicit_Field_set,
19743 Implicit_Field_set,
19744 Implicit_Field_set,
19745 Implicit_Field_set,
19746 Implicit_Field_set,
19747 Implicit_Field_set
19748};
43cd72b9 19749
7aa09196
SA		 19750static xtensa_get_field_fn
19751Slot_inst16b_get_field_fns[] = {
19752 Field_t_Slot_inst16b_get,
19753 0,
19754 0,
19755 0,
19756 0,
19757 Field_s_Slot_inst16b_get,
19758 0,
19759 0,
19760 0,
19761 0,
19762 0,
19763 Field_op0_Slot_inst16b_get,
19764 0,
19765 0,
19766 Field_r_Slot_inst16b_get,
19767 0,
19768 0,
19769 0,
19770 0,
19771 0,
19772 0,
19773 0,
19774 Field_sr_Slot_inst16b_get,
19775 Field_st_Slot_inst16b_get,
19776 0,
19777 Field_imm4_Slot_inst16b_get,
19778 0,
19779 Field_i_Slot_inst16b_get,
19780 Field_imm6lo_Slot_inst16b_get,
19781 Field_imm6hi_Slot_inst16b_get,
19782 Field_imm7lo_Slot_inst16b_get,
19783 Field_imm7hi_Slot_inst16b_get,
19784 Field_z_Slot_inst16b_get,
19785 Field_imm6_Slot_inst16b_get,
19786 Field_imm7_Slot_inst16b_get,
19787 0,
19788 0,
19789 0,
19790 0,
19791 0,
19792 0,
19793 0,
19794 0,
19795 0,
19796 Field_t2_Slot_inst16b_get,
19797 Field_s2_Slot_inst16b_get,
19798 Field_r2_Slot_inst16b_get,
19799 Field_t4_Slot_inst16b_get,
19800 Field_s4_Slot_inst16b_get,
19801 Field_r4_Slot_inst16b_get,
19802 Field_t8_Slot_inst16b_get,
19803 Field_s8_Slot_inst16b_get,
19804 Field_r8_Slot_inst16b_get,
19805 0,
19806 0,
19807 0,
19808 0,
19809 0,
19810 0,
19811 0,
19812 0,
19813 0,
19814 0,
19815 0,
19816 0,
19817 0,
19818 0,
19819 0,
19820 0,
19821 0,
19822 0,
19823 0,
19824 0,
19825 0,
19826 0,
19827 0,
19828 0,
19829 0,
19830 0,
19831 0,
19832 0,
19833 0,
19834 0,
19835 0,
19836 0,
19837 0,
19838 0,
19839 0,
19840 0,
19841 0,
19842 0,
19843 0,
19844 0,
19845 0,
19846 0,
19847 0,
19848 0,
19849 0,
19850 0,
19851 0,
19852 0,
19853 0,
19854 0,
19855 0,
19856 0,
19857 0,
19858 0,
19859 0,
19860 0,
19861 0,
19862 0,
19863 0,
19864 0,
19865 0,
19866 0,
19867 0,
19868 0,
19869 0,
19870 0,
19871 0,
19872 0,
19873 0,
19874 0,
19875 Implicit_Field_ar0_get,
19876 Implicit_Field_ar4_get,
19877 Implicit_Field_ar8_get,
19878 Implicit_Field_ar12_get,
19879 Implicit_Field_mr0_get,
19880 Implicit_Field_mr1_get,
19881 Implicit_Field_mr2_get,
19882 Implicit_Field_mr3_get,
19883 Implicit_Field_bt16_get,
19884 Implicit_Field_bs16_get,
19885 Implicit_Field_br16_get,
19886 Implicit_Field_brall_get
19887};
43cd72b9 19888
7aa09196
SA		 19889static xtensa_set_field_fn
19890Slot_inst16b_set_field_fns[] = {
19891 Field_t_Slot_inst16b_set,
19892 0,
19893 0,
19894 0,
19895 0,
19896 Field_s_Slot_inst16b_set,
19897 0,
19898 0,
19899 0,
19900 0,
19901 0,
19902 Field_op0_Slot_inst16b_set,
19903 0,
19904 0,
19905 Field_r_Slot_inst16b_set,
19906 0,
19907 0,
19908 0,
19909 0,
19910 0,
19911 0,
19912 0,
19913 Field_sr_Slot_inst16b_set,
19914 Field_st_Slot_inst16b_set,
19915 0,
19916 Field_imm4_Slot_inst16b_set,
19917 0,
19918 Field_i_Slot_inst16b_set,
19919 Field_imm6lo_Slot_inst16b_set,
19920 Field_imm6hi_Slot_inst16b_set,
19921 Field_imm7lo_Slot_inst16b_set,
19922 Field_imm7hi_Slot_inst16b_set,
19923 Field_z_Slot_inst16b_set,
19924 Field_imm6_Slot_inst16b_set,
19925 Field_imm7_Slot_inst16b_set,
19926 0,
19927 0,
19928 0,
19929 0,
19930 0,
19931 0,
19932 0,
19933 0,
19934 0,
19935 Field_t2_Slot_inst16b_set,
19936 Field_s2_Slot_inst16b_set,
19937 Field_r2_Slot_inst16b_set,
19938 Field_t4_Slot_inst16b_set,
19939 Field_s4_Slot_inst16b_set,
19940 Field_r4_Slot_inst16b_set,
19941 Field_t8_Slot_inst16b_set,
19942 Field_s8_Slot_inst16b_set,
19943 Field_r8_Slot_inst16b_set,
19944 0,
19945 0,
19946 0,
19947 0,
19948 0,
19949 0,
19950 0,
19951 0,
19952 0,
19953 0,
19954 0,
19955 0,
19956 0,
19957 0,
19958 0,
19959 0,
19960 0,
19961 0,
19962 0,
19963 0,
19964 0,
19965 0,
19966 0,
19967 0,
19968 0,
19969 0,
19970 0,
19971 0,
19972 0,
19973 0,
19974 0,
19975 0,
19976 0,
19977 0,
19978 0,
19979 0,
19980 0,
19981 0,
19982 0,
19983 0,
19984 0,
19985 0,
19986 0,
19987 0,
19988 0,
19989 0,
19990 0,
19991 0,
19992 0,
19993 0,
19994 0,
19995 0,
19996 0,
19997 0,
19998 0,
19999 0,
20000 0,
20001 0,
20002 0,
20003 0,
20004 0,
20005 0,
20006 0,
20007 0,
20008 0,
20009 0,
20010 0,
20011 0,
20012 0,
20013 0,
20014 Implicit_Field_set,
20015 Implicit_Field_set,
20016 Implicit_Field_set,
20017 Implicit_Field_set,
20018 Implicit_Field_set,
20019 Implicit_Field_set,
20020 Implicit_Field_set,
20021 Implicit_Field_set,
20022 Implicit_Field_set,
20023 Implicit_Field_set,
20024 Implicit_Field_set,
20025 Implicit_Field_set
20026};
43cd72b9 20027
7aa09196
SA		 20028static xtensa_get_field_fn
20029Slot_xt_flix64_slot0_get_field_fns[] = {
20030 Field_t_Slot_xt_flix64_slot0_get,
20031 0,
20032 0,
20033 0,
20034 Field_imm8_Slot_xt_flix64_slot0_get,
20035 Field_s_Slot_xt_flix64_slot0_get,
20036 Field_imm12b_Slot_xt_flix64_slot0_get,
20037 Field_imm16_Slot_xt_flix64_slot0_get,
20038 Field_m_Slot_xt_flix64_slot0_get,
20039 Field_n_Slot_xt_flix64_slot0_get,
20040 0,
20041 0,
20042 Field_op1_Slot_xt_flix64_slot0_get,
20043 Field_op2_Slot_xt_flix64_slot0_get,
20044 Field_r_Slot_xt_flix64_slot0_get,
20045 0,
20046 Field_sae4_Slot_xt_flix64_slot0_get,
20047 Field_sae_Slot_xt_flix64_slot0_get,
20048 Field_sal_Slot_xt_flix64_slot0_get,
20049 Field_sargt_Slot_xt_flix64_slot0_get,
20050 0,
20051 Field_sas_Slot_xt_flix64_slot0_get,
20052 0,
20053 0,
20054 Field_thi3_Slot_xt_flix64_slot0_get,
20055 0,
20056 0,
20057 0,
20058 0,
20059 0,
20060 0,
20061 0,
20062 0,
20063 0,
20064 0,
20065 0,
20066 0,
20067 0,
20068 0,
20069 0,
20070 0,
20071 0,
20072 0,
20073 0,
20074 0,
20075 0,
20076 0,
20077 0,
20078 0,
20079 0,
20080 0,
20081 0,
20082 0,
20083 0,
20084 0,
20085 Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get,
20086 Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get,
20087 Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get,
20088 Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get,
20089 Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get,
20090 Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get,
20091 0,
20092 0,
20093 0,
20094 0,
20095 0,
20096 0,
20097 0,
20098 0,
20099 0,
20100 0,
20101 0,
20102 0,
20103 0,
20104 0,
20105 0,
20106 0,
20107 0,
20108 0,
20109 0,
20110 0,
20111 0,
20112 0,
20113 0,
20114 0,
20115 0,
20116 0,
20117 0,
20118 0,
20119 0,
20120 0,
20121 0,
20122 0,
20123 0,
20124 0,
20125 0,
20126 0,
20127 0,
20128 0,
20129 0,
20130 0,
20131 0,
20132 0,
20133 0,
20134 0,
20135 0,
20136 0,
20137 0,
20138 0,
20139 0,
20140 0,
20141 0,
20142 0,
20143 0,
20144 0,
20145 0,
20146 0,
20147 0,
20148 0,
20149 0,
20150 0,
20151 0,
20152 Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get,
20153 Implicit_Field_ar0_get,
20154 Implicit_Field_ar4_get,
20155 Implicit_Field_ar8_get,
20156 Implicit_Field_ar12_get,
20157 Implicit_Field_mr0_get,
20158 Implicit_Field_mr1_get,
20159 Implicit_Field_mr2_get,
20160 Implicit_Field_mr3_get,
20161 Implicit_Field_bt16_get,
20162 Implicit_Field_bs16_get,
20163 Implicit_Field_br16_get,
20164 Implicit_Field_brall_get
20165};
43cd72b9 20166
7aa09196
SA		 20167static xtensa_set_field_fn
20168Slot_xt_flix64_slot0_set_field_fns[] = {
20169 Field_t_Slot_xt_flix64_slot0_set,
20170 0,
20171 0,
20172 0,
20173 Field_imm8_Slot_xt_flix64_slot0_set,
20174 Field_s_Slot_xt_flix64_slot0_set,
20175 Field_imm12b_Slot_xt_flix64_slot0_set,
20176 Field_imm16_Slot_xt_flix64_slot0_set,
20177 Field_m_Slot_xt_flix64_slot0_set,
20178 Field_n_Slot_xt_flix64_slot0_set,
20179 0,
20180 0,
20181 Field_op1_Slot_xt_flix64_slot0_set,
20182 Field_op2_Slot_xt_flix64_slot0_set,
20183 Field_r_Slot_xt_flix64_slot0_set,
20184 0,
20185 Field_sae4_Slot_xt_flix64_slot0_set,
20186 Field_sae_Slot_xt_flix64_slot0_set,
20187 Field_sal_Slot_xt_flix64_slot0_set,
20188 Field_sargt_Slot_xt_flix64_slot0_set,
20189 0,
20190 Field_sas_Slot_xt_flix64_slot0_set,
20191 0,
20192 0,
20193 Field_thi3_Slot_xt_flix64_slot0_set,
20194 0,
20195 0,
20196 0,
20197 0,
20198 0,
20199 0,
20200 0,
20201 0,
20202 0,
20203 0,
20204 0,
20205 0,
20206 0,
20207 0,
20208 0,
20209 0,
20210 0,
20211 0,
20212 0,
20213 0,
20214 0,
20215 0,
20216 0,
20217 0,
20218 0,
20219 0,
20220 0,
20221 0,
20222 0,
20223 0,
20224 Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_set,
20225 Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_set,
20226 Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_set,
20227 Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_set,
20228 Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_set,
20229 Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_set,
20230 0,
20231 0,
20232 0,
20233 0,
20234 0,
20235 0,
20236 0,
20237 0,
20238 0,
20239 0,
20240 0,
20241 0,
20242 0,
20243 0,
20244 0,
20245 0,
20246 0,
20247 0,
20248 0,
20249 0,
20250 0,
20251 0,
20252 0,
20253 0,
20254 0,
20255 0,
20256 0,
20257 0,
20258 0,
20259 0,
20260 0,
20261 0,
20262 0,
20263 0,
20264 0,
20265 0,
20266 0,
20267 0,
20268 0,
20269 0,
20270 0,
20271 0,
20272 0,
20273 0,
20274 0,
20275 0,
20276 0,
20277 0,
20278 0,
20279 0,
20280 0,
20281 0,
20282 0,
20283 0,
20284 0,
20285 0,
20286 0,
20287 0,
20288 0,
20289 0,
20290 0,
20291 Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_set,
20292 Implicit_Field_set,
20293 Implicit_Field_set,
20294 Implicit_Field_set,
20295 Implicit_Field_set,
20296 Implicit_Field_set,
20297 Implicit_Field_set,
20298 Implicit_Field_set,
20299 Implicit_Field_set,
20300 Implicit_Field_set,
20301 Implicit_Field_set,
20302 Implicit_Field_set,
20303 Implicit_Field_set
20304};
43cd72b9 20305
7aa09196
SA		 20306static xtensa_get_field_fn
20307Slot_xt_flix64_slot1_get_field_fns[] = {
20308 Field_t_Slot_xt_flix64_slot1_get,
20309 0,
20310 0,
20311 0,
20312 Field_imm8_Slot_xt_flix64_slot1_get,
20313 Field_s_Slot_xt_flix64_slot1_get,
20314 Field_imm12b_Slot_xt_flix64_slot1_get,
20315 0,
20316 0,
20317 0,
20318 Field_offset_Slot_xt_flix64_slot1_get,
20319 0,
20320 0,
20321 Field_op2_Slot_xt_flix64_slot1_get,
20322 Field_r_Slot_xt_flix64_slot1_get,
20323 0,
20324 0,
20325 Field_sae_Slot_xt_flix64_slot1_get,
20326 Field_sal_Slot_xt_flix64_slot1_get,
20327 Field_sargt_Slot_xt_flix64_slot1_get,
20328 0,
20329 0,
20330 0,
20331 0,
20332 0,
20333 0,
20334 0,
20335 0,
20336 0,
20337 0,
20338 0,
20339 0,
20340 0,
20341 0,
20342 0,
20343 0,
20344 0,
20345 0,
20346 0,
20347 0,
20348 0,
20349 0,
20350 0,
20351 0,
20352 0,
20353 0,
20354 0,
20355 0,
20356 0,
20357 0,
20358 0,
20359 0,
20360 0,
20361 0,
20362 0,
20363 0,
20364 0,
20365 0,
20366 0,
20367 0,
20368 0,
20369 Field_op0_s4_Slot_xt_flix64_slot1_get,
20370 Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get,
20371 Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20372 Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20373 Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20374 Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20375 Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20376 Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20377 Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20378 Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20379 Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20380 Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20381 Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20382 Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20383 Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20384 Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20385 Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20386 Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20387 Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20388 Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20389 Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20390 Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get,
20391 0,
20392 0,
20393 0,
20394 0,
20395 0,
20396 0,
20397 0,
20398 0,
20399 0,
20400 0,
20401 0,
20402 0,
20403 0,
20404 0,
20405 0,
20406 0,
20407 0,
20408 0,
20409 0,
20410 0,
20411 0,
20412 0,
20413 0,
20414 0,
20415 0,
20416 0,
20417 0,
20418 0,
20419 0,
20420 0,
20421 0,
20422 0,
20423 0,
20424 0,
20425 0,
20426 0,
20427 0,
20428 0,
20429 0,
20430 0,
20431 Implicit_Field_ar0_get,
20432 Implicit_Field_ar4_get,
20433 Implicit_Field_ar8_get,
20434 Implicit_Field_ar12_get,
20435 Implicit_Field_mr0_get,
20436 Implicit_Field_mr1_get,
20437 Implicit_Field_mr2_get,
20438 Implicit_Field_mr3_get,
20439 Implicit_Field_bt16_get,
20440 Implicit_Field_bs16_get,
20441 Implicit_Field_br16_get,
20442 Implicit_Field_brall_get
20443};
43cd72b9 20444
7aa09196
SA		 20445static xtensa_set_field_fn
20446Slot_xt_flix64_slot1_set_field_fns[] = {
20447 Field_t_Slot_xt_flix64_slot1_set,
20448 0,
20449 0,
20450 0,
20451 Field_imm8_Slot_xt_flix64_slot1_set,
20452 Field_s_Slot_xt_flix64_slot1_set,
20453 Field_imm12b_Slot_xt_flix64_slot1_set,
20454 0,
20455 0,
20456 0,
20457 Field_offset_Slot_xt_flix64_slot1_set,
20458 0,
20459 0,
20460 Field_op2_Slot_xt_flix64_slot1_set,
20461 Field_r_Slot_xt_flix64_slot1_set,
20462 0,
20463 0,
20464 Field_sae_Slot_xt_flix64_slot1_set,
20465 Field_sal_Slot_xt_flix64_slot1_set,
20466 Field_sargt_Slot_xt_flix64_slot1_set,
20467 0,
20468 0,
20469 0,
20470 0,
20471 0,
20472 0,
20473 0,
20474 0,
20475 0,
20476 0,
20477 0,
20478 0,
20479 0,
20480 0,
20481 0,
20482 0,
20483 0,
20484 0,
20485 0,
20486 0,
20487 0,
20488 0,
20489 0,
20490 0,
20491 0,
20492 0,
20493 0,
20494 0,
20495 0,
20496 0,
20497 0,
20498 0,
20499 0,
20500 0,
20501 0,
20502 0,
20503 0,
20504 0,
20505 0,
20506 0,
20507 0,
20508 Field_op0_s4_Slot_xt_flix64_slot1_set,
20509 Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_set,
20510 Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20511 Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20512 Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20513 Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20514 Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20515 Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20516 Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20517 Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20518 Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20519 Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20520 Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20521 Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20522 Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20523 Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20524 Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20525 Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20526 Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20527 Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20528 Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20529 Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_set,
20530 0,
20531 0,
20532 0,
20533 0,
20534 0,
20535 0,
20536 0,
20537 0,
20538 0,
20539 0,
20540 0,
20541 0,
20542 0,
20543 0,
20544 0,
20545 0,
20546 0,
20547 0,
20548 0,
20549 0,
20550 0,
20551 0,
20552 0,
20553 0,
20554 0,
20555 0,
20556 0,
20557 0,
20558 0,
20559 0,
20560 0,
20561 0,
20562 0,
20563 0,
20564 0,
20565 0,
20566 0,
20567 0,
20568 0,
20569 0,
20570 Implicit_Field_set,
20571 Implicit_Field_set,
20572 Implicit_Field_set,
20573 Implicit_Field_set,
20574 Implicit_Field_set,
20575 Implicit_Field_set,
20576 Implicit_Field_set,
20577 Implicit_Field_set,
20578 Implicit_Field_set,
20579 Implicit_Field_set,
20580 Implicit_Field_set,
20581 Implicit_Field_set
20582};
43cd72b9
BW		 20583
20584static xtensa_get_field_fn
7aa09196
SA		 20585Slot_xt_flix64_slot2_get_field_fns[] = {
20586 Field_t_Slot_xt_flix64_slot2_get,
20587 0,
20588 0,
20589 0,
20590 0,
20591 Field_s_Slot_xt_flix64_slot2_get,
20592 0,
20593 0,
20594 0,
20595 0,
20596 0,
20597 0,
20598 0,
20599 0,
20600 Field_r_Slot_xt_flix64_slot2_get,
20601 0,
20602 0,
20603 0,
20604 0,
20605 Field_sargt_Slot_xt_flix64_slot2_get,
20606 0,
20607 0,
20608 0,
20609 0,
20610 0,
20611 0,
20612 0,
20613 0,
20614 0,
20615 0,
20616 0,
20617 0,
20618 0,
20619 0,
20620 Field_imm7_Slot_xt_flix64_slot2_get,
20621 0,
20622 0,
20623 0,
20624 0,
20625 0,
20626 0,
20627 0,
20628 0,
20629 0,
20630 0,
20631 0,
20632 0,
20633 0,
20634 0,
20635 0,
20636 0,
20637 0,
20638 0,
20639 0,
20640 0,
20641 0,
20642 0,
20643 0,
20644 0,
20645 0,
20646 0,
20647 0,
20648 0,
20649 0,
20650 0,
20651 0,
20652 0,
20653 0,
20654 0,
20655 0,
20656 0,
20657 0,
20658 0,
20659 0,
20660 0,
20661 0,
20662 0,
20663 0,
20664 0,
20665 0,
20666 0,
20667 0,
20668 0,
20669 Field_op0_s5_Slot_xt_flix64_slot2_get,
20670 Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20671 Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20672 Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20673 Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20674 Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20675 Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20676 Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20677 Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20678 Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20679 Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20680 Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20681 Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20682 Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get,
20683 0,
20684 0,
20685 0,
20686 0,
20687 0,
20688 0,
20689 0,
20690 0,
20691 0,
20692 0,
20693 0,
20694 0,
20695 0,
20696 0,
20697 0,
20698 0,
20699 0,
20700 0,
20701 0,
20702 0,
20703 0,
20704 0,
20705 0,
20706 0,
20707 0,
20708 0,
20709 Implicit_Field_ar0_get,
20710 Implicit_Field_ar4_get,
20711 Implicit_Field_ar8_get,
20712 Implicit_Field_ar12_get,
20713 Implicit_Field_mr0_get,
20714 Implicit_Field_mr1_get,
20715 Implicit_Field_mr2_get,
20716 Implicit_Field_mr3_get,
20717 Implicit_Field_bt16_get,
20718 Implicit_Field_bs16_get,
20719 Implicit_Field_br16_get,
20720 Implicit_Field_brall_get
20721};
20722
20723static xtensa_set_field_fn
20724Slot_xt_flix64_slot2_set_field_fns[] = {
20725 Field_t_Slot_xt_flix64_slot2_set,
20726 0,
20727 0,
20728 0,
20729 0,
20730 Field_s_Slot_xt_flix64_slot2_set,
20731 0,
20732 0,
20733 0,
20734 0,
20735 0,
20736 0,
20737 0,
20738 0,
20739 Field_r_Slot_xt_flix64_slot2_set,
20740 0,
20741 0,
20742 0,
20743 0,
20744 Field_sargt_Slot_xt_flix64_slot2_set,
20745 0,
20746 0,
20747 0,
20748 0,
20749 0,
20750 0,
20751 0,
20752 0,
20753 0,
20754 0,
20755 0,
20756 0,
20757 0,
20758 0,
20759 Field_imm7_Slot_xt_flix64_slot2_set,
20760 0,
20761 0,
20762 0,
20763 0,
20764 0,
20765 0,
20766 0,
20767 0,
20768 0,
20769 0,
20770 0,
20771 0,
20772 0,
20773 0,
20774 0,
20775 0,
20776 0,
20777 0,
20778 0,
20779 0,
20780 0,
20781 0,
20782 0,
20783 0,
20784 0,
20785 0,
20786 0,
20787 0,
20788 0,
20789 0,
20790 0,
20791 0,
20792 0,
20793 0,
20794 0,
20795 0,
20796 0,
20797 0,
20798 0,
20799 0,
20800 0,
43cd72b9
BW		 20801 0,
20802 0,
20803 0,
20804 0,
20805 0,
20806 0,
20807 0,
7aa09196
SA		 20808 Field_op0_s5_Slot_xt_flix64_slot2_set,
20809 Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20810 Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20811 Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20812 Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20813 Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20814 Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20815 Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20816 Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20817 Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20818 Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20819 Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20820 Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_set,
20821 Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_set,
43cd72b9 20822 0,
43cd72b9
BW		 20823 0,
20824 0,
20825 0,
20826 0,
20827 0,
20828 0,
20829 0,
20830 0,
7aa09196
SA		 20831 0,
20832 0,
20833 0,
20834 0,
20835 0,
20836 0,
20837 0,
20838 0,
20839 0,
20840 0,
20841 0,
20842 0,
20843 0,
20844 0,
20845 0,
20846 0,
20847 0,
20848 Implicit_Field_set,
20849 Implicit_Field_set,
20850 Implicit_Field_set,
20851 Implicit_Field_set,
20852 Implicit_Field_set,
20853 Implicit_Field_set,
20854 Implicit_Field_set,
20855 Implicit_Field_set,
43cd72b9
BW		 20856 Implicit_Field_set,
20857 Implicit_Field_set,
20858 Implicit_Field_set,
20859 Implicit_Field_set
20860};
20861
20862static xtensa_get_field_fn
7aa09196
SA		 20863Slot_xt_flix64_slot3_get_field_fns[] = {
20864 Field_t_Slot_xt_flix64_slot3_get,
43cd72b9 20865 0,
7aa09196 20866 Field_bbi_Slot_xt_flix64_slot3_get,
43cd72b9
BW		 20867 0,
20868 0,
7aa09196 20869 Field_s_Slot_xt_flix64_slot3_get,
43cd72b9 20870 0,
43cd72b9
BW		 20871 0,
20872 0,
20873 0,
20874 0,
20875 0,
43cd72b9
BW		 20876 0,
20877 0,
7aa09196 20878 Field_r_Slot_xt_flix64_slot3_get,
43cd72b9
BW		 20879 0,
20880 0,
20881 0,
20882 0,
20883 0,
20884 0,
20885 0,
43cd72b9 20886 0,
43cd72b9 20887 0,
33430bd0
BW		 20888 0,
20889 0,
43cd72b9
BW		 20890 0,
20891 0,
20892 0,
20893 0,
43cd72b9
BW		 20894 0,
20895 0,
20896 0,
20897 0,
20898 0,
43cd72b9
BW		 20899 0,
20900 0,
43cd72b9
BW		 20901 0,
20902 0,
20903 0,
20904 0,
20905 0,
20906 0,
20907 0,
43cd72b9 20908 0,
43cd72b9 20909 0,
33430bd0
BW		 20910 0,
20911 0,
43cd72b9
BW		 20912 0,
20913 0,
20914 0,
20915 0,
7aa09196
SA		 20916 0,
20917 0,
20918 Field_xt_wbr18_imm_Slot_xt_flix64_slot3_get,
20919 0,
20920 0,
43cd72b9
BW		 20921 0,
20922 0,
20923 0,
20924 0,
20925 0,
43cd72b9
BW		 20926 0,
20927 0,
43cd72b9
BW		 20928 0,
20929 0,
20930 0,
20931 0,
20932 0,
20933 0,
20934 0,
43cd72b9 20935 0,
43cd72b9 20936 0,
33430bd0
BW		 20937 0,
20938 0,
7aa09196
SA		 20939 0,
20940 0,
20941 0,
20942 0,
20943 0,
20944 0,
20945 0,
20946 0,
20947 0,
20948 0,
20949 0,
20950 0,
20951 0,
20952 0,
20953 0,
20954 0,
20955 0,
20956 0,
20957 0,
20958 0,
20959 0,
20960 0,
20961 Field_op0_s6_Slot_xt_flix64_slot3_get,
20962 Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20963 Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get,
20964 Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20965 Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20966 Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20967 Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20968 Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20969 Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20970 Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20971 Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20972 Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20973 Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20974 Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20975 Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20976 Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20977 Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20978 Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20979 Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20980 Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20981 Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20982 Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20983 Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20984 Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20985 Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get,
20986 0,
43cd72b9
BW		 20987 Implicit_Field_ar0_get,
20988 Implicit_Field_ar4_get,
20989 Implicit_Field_ar8_get,
7aa09196
SA		 20990 Implicit_Field_ar12_get,
20991 Implicit_Field_mr0_get,
20992 Implicit_Field_mr1_get,
20993 Implicit_Field_mr2_get,
20994 Implicit_Field_mr3_get,
20995 Implicit_Field_bt16_get,
20996 Implicit_Field_bs16_get,
20997 Implicit_Field_br16_get,
20998 Implicit_Field_brall_get
43cd72b9
BW		 20999};
21000
21001static xtensa_set_field_fn
7aa09196
SA		 21002Slot_xt_flix64_slot3_set_field_fns[] = {
21003 Field_t_Slot_xt_flix64_slot3_set,
21004 0,
21005 Field_bbi_Slot_xt_flix64_slot3_set,
21006 0,
21007 0,
21008 Field_s_Slot_xt_flix64_slot3_set,
21009 0,
21010 0,
21011 0,
21012 0,
21013 0,
21014 0,
21015 0,
21016 0,
21017 Field_r_Slot_xt_flix64_slot3_set,
21018 0,
21019 0,
21020 0,
21021 0,
21022 0,
21023 0,
21024 0,
21025 0,
21026 0,
21027 0,
21028 0,
21029 0,
21030 0,
21031 0,
43cd72b9
BW		 21032 0,
21033 0,
21034 0,
21035 0,
43cd72b9
BW		 21036 0,
21037 0,
21038 0,
21039 0,
21040 0,
43cd72b9
BW		 21041 0,
21042 0,
43cd72b9
BW		 21043 0,
21044 0,
21045 0,
21046 0,
21047 0,
21048 0,
21049 0,
43cd72b9 21050 0,
43cd72b9 21051 0,
33430bd0
BW		 21052 0,
21053 0,
7aa09196
SA		 21054 0,
21055 0,
21056 0,
21057 Field_xt_wbr18_imm_Slot_xt_flix64_slot3_set,
21058 0,
21059 0,
21060 0,
21061 0,
21062 0,
21063 0,
21064 0,
21065 0,
21066 0,
21067 0,
21068 0,
21069 0,
21070 0,
21071 0,
21072 0,
21073 0,
21074 0,
21075 0,
21076 0,
21077 0,
21078 0,
21079 0,
21080 0,
21081 0,
21082 0,
21083 0,
21084 0,
21085 0,
21086 0,
21087 0,
21088 0,
21089 0,
21090 0,
21091 0,
21092 0,
21093 0,
21094 0,
21095 0,
21096 0,
21097 0,
21098 0,
21099 0,
21100 Field_op0_s6_Slot_xt_flix64_slot3_set,
21101 Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21102 Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_set,
21103 Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21104 Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21105 Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21106 Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21107 Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21108 Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21109 Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21110 Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21111 Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21112 Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21113 Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21114 Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21115 Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21116 Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21117 Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21118 Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21119 Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21120 Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21121 Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21122 Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21123 Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21124 Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_set,
21125 0,
21126 Implicit_Field_set,
21127 Implicit_Field_set,
21128 Implicit_Field_set,
21129 Implicit_Field_set,
21130 Implicit_Field_set,
21131 Implicit_Field_set,
21132 Implicit_Field_set,
21133 Implicit_Field_set,
43cd72b9
BW		 21134 Implicit_Field_set,
21135 Implicit_Field_set,
21136 Implicit_Field_set,
21137 Implicit_Field_set
21138};
21139
21140static xtensa_slot_internal slots[] = {
21141 { "Inst", "x24", 0,
21142 Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
21143 Slot_inst_get_field_fns, Slot_inst_set_field_fns,
21144 Slot_inst_decode, "nop" },
21145 { "Inst16a", "x16a", 0,
21146 Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
21147 Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
21148 Slot_inst16a_decode, "" },
21149 { "Inst16b", "x16b", 0,
21150 Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
21151 Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
7aa09196
SA		 21152 Slot_inst16b_decode, "nop.n" },
21153 { "xt_flix64_slot0", "xt_format1", 0,
21154 Slot_xt_format1_Format_xt_flix64_slot0_4_get, Slot_xt_format1_Format_xt_flix64_slot0_4_set,
21155 Slot_xt_flix64_slot0_get_field_fns, Slot_xt_flix64_slot0_set_field_fns,
21156 Slot_xt_flix64_slot0_decode, "nop" },
21157 { "xt_flix64_slot0", "xt_format2", 0,
21158 Slot_xt_format2_Format_xt_flix64_slot0_4_get, Slot_xt_format2_Format_xt_flix64_slot0_4_set,
21159 Slot_xt_flix64_slot0_get_field_fns, Slot_xt_flix64_slot0_set_field_fns,
21160 Slot_xt_flix64_slot0_decode, "nop" },
21161 { "xt_flix64_slot1", "xt_format1", 1,
21162 Slot_xt_format1_Format_xt_flix64_slot1_28_get, Slot_xt_format1_Format_xt_flix64_slot1_28_set,
21163 Slot_xt_flix64_slot1_get_field_fns, Slot_xt_flix64_slot1_set_field_fns,
21164 Slot_xt_flix64_slot1_decode, "nop" },
21165 { "xt_flix64_slot2", "xt_format1", 2,
21166 Slot_xt_format1_Format_xt_flix64_slot2_48_get, Slot_xt_format1_Format_xt_flix64_slot2_48_set,
21167 Slot_xt_flix64_slot2_get_field_fns, Slot_xt_flix64_slot2_set_field_fns,
21168 Slot_xt_flix64_slot2_decode, "nop" },
21169 { "xt_flix64_slot3", "xt_format2", 1,
21170 Slot_xt_format2_Format_xt_flix64_slot3_28_get, Slot_xt_format2_Format_xt_flix64_slot3_28_set,
21171 Slot_xt_flix64_slot3_get_field_fns, Slot_xt_flix64_slot3_set_field_fns,
21172 Slot_xt_flix64_slot3_decode, "nop" }
43cd72b9
BW		 21173};
21174
21175\f
21176/* Instruction formats. */
21177
21178static void
21179Format_x24_encode (xtensa_insnbuf insn)
21180{
21181 insn[0] = 0;
7aa09196 21182 insn[1] = 0;
43cd72b9
BW		 21183}
21184
21185static void
21186Format_x16a_encode (xtensa_insnbuf insn)
21187{
7aa09196
SA		 21188 insn[0] = 0x8;
21189 insn[1] = 0;
e0001a05
NC		 21190}
21191
43cd72b9
BW		 21192static void
21193Format_x16b_encode (xtensa_insnbuf insn)
e0001a05 21194{
7aa09196
SA		 21195 insn[0] = 0xc;
21196 insn[1] = 0;
21197}
21198
21199static void
21200Format_xt_format1_encode (xtensa_insnbuf insn)
21201{
21202 insn[0] = 0xe;
21203 insn[1] = 0;
21204}
21205
21206static void
21207Format_xt_format2_encode (xtensa_insnbuf insn)
21208{
21209 insn[0] = 0xf;
21210 insn[1] = 0;
e0001a05
NC		 21211}
21212
43cd72b9
BW		 21213static int Format_x24_slots[] = { 0 };
21214
21215static int Format_x16a_slots[] = { 1 };
21216
21217static int Format_x16b_slots[] = { 2 };
21218
7aa09196
SA		 21219static int Format_xt_format1_slots[] = { 3, 5, 6 };
21220
21221static int Format_xt_format2_slots[] = { 4, 7 };
21222
43cd72b9
BW		 21223static xtensa_format_internal formats[] = {
21224 { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
21225 { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
7aa09196
SA		 21226 { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots },
21227 { "xt_format1", 8, Format_xt_format1_encode, 3, Format_xt_format1_slots },
21228 { "xt_format2", 8, Format_xt_format2_encode, 2, Format_xt_format2_slots }
e0001a05
NC		 21229};
21230
e0001a05 21231
43cd72b9
BW		 21232static int
21233format_decoder (const xtensa_insnbuf insn)
e0001a05 21234{
7aa09196 21235 if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0)
43cd72b9 21236 return 0; /* x24 */
7aa09196 21237 if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0)
43cd72b9 21238 return 1; /* x16a */
7aa09196 21239 if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0)
43cd72b9 21240 return 2; /* x16b */
7aa09196
SA		 21241 if ((insn[0] & 0xf) == 0xe && (insn[1] & 0) == 0)
21242 return 3; /* xt_format1 */
21243 if ((insn[0] & 0xf) == 0xf && (insn[1] & 0x80000000) == 0)
21244 return 4; /* xt_format2 */
43cd72b9 21245 return -1;
e0001a05
NC		 21246}
21247
43cd72b9
BW		 21248static int length_table[16] = {
21249 3,
21250 3,
21251 3,
21252 3,
21253 3,
21254 3,
21255 3,
21256 3,
21257 2,
21258 2,
21259 2,
21260 2,
21261 2,
21262 2,
7aa09196
SA		 21263 8,
21264 8
43cd72b9
BW		 21265};
21266
21267static int
f075ee0c 21268length_decoder (const unsigned char *insn)
43cd72b9 21269{
7aa09196 21270 int op0 = insn[0] & 0xf;
43cd72b9
BW		 21271 return length_table[op0];
21272}
21273
21274\f
21275/* Top-level ISA structure. */
21276
21277xtensa_isa_internal xtensa_modules = {
7aa09196
SA		 21278 0 /* little-endian */,
21279 8 /* insn_size */, 0,
21280 5, formats, format_decoder, length_decoder,
21281 8, slots,
21282 135 /* num_fields */,
21283 188, operands,
21284 355, iclasses,
21285 530, opcodes, 0,
21286 8, regfiles,
43cd72b9
BW		 21287 NUM_STATES, states, 0,
21288 NUM_SYSREGS, sysregs, 0,
21289 { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
21290 0, interfaces, 0,
21291 0, funcUnits, 0
e0001a05 21292};
GDB Binutils - Deliverables
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