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1d61b032
AM		 12019-12-11 Alan Modra <amodra@gmail.com>
2
3 * epiphany.cpu (f-sdisp11): Don't sign extend with shifts.
4 * lm32.cpu (f-branch, f-vall): Likewise.
5 * m32.cpu (f-lab-8-16): Likewise.
6
b8e61daa
AM		 72019-12-11 Alan Modra <amodra@gmail.com>
8
9 * epiphany.cpu (f-simm8, f-simm24): Use multiply rather than
10 shift left to avoid UB on left shift of negative values.
11
e042e6c3
JM		 122019-11-20 Jose E. Marchesi <jose.marchesi@oracle.com>
13
14 * bpf.cpu: Fix comment describing the 128-bit instruction format.
15
60391a25
PB		 162019-09-09 Phil Blundell <pb@pbcl.net>
17
18 binutils 2.33 branch created.
19
231097b0
JM		 202019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
21
22 * bpf.cpu (h-gpr): when disassembling, use %r0 and %r6 instead of
23 %a and %ctx.
24
3719fd55
JM		 252019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
26
27 * bpf.cpu (dlabs): New pmacro.
28 (dlind): Likewise.
29
92434a14
JM		 302019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
31
32 * bpf.cpu (dlsi): ldabs and ldind instructions do not take an
33 explicit 'dst' argument.
34
a2e4218f
SH		 352019-06-13 Stafford Horne <shorne@gmail.com>
36
37 * or1korfpx.cpu (float-setflag-insn-base): Add 'sf' to symbol.
38
eb212c84
SH		 392019-06-13 Stafford Horne <shorne@gmail.com>
40
41 * or1k.cpu (or64nd, or32nd, or1200nd): Update comment.a
42 (l-adrp): Improve comment.
43
d3ad6278
SH		 442019-06-13 Stafford Horne <shorne@gmail.com>
45
46 * or1korfpx.cpu (insn-opcode-float-regreg): Add SFUEQ_S, SFUNE_S,
47 SFUGT_S, SFUGE_S, SFULT_S, SFULE_S, SFUN_S, SFUEQ_D, SFUNE_D, SFUGT_D,
48 SFUGE_D, SFULT_D, SFULE_D, SFUN_D opcodes.
49 (float-setflag-insn-base): New pmacro based on float-setflag-insn.
50 (float-setflag-symantics, float-setflag-unordered-cmp-symantics,
51 float-setflag-unordered-symantics): New pmacro for instruction
52 symantics.
53 (float-setflag-insn): Update to use float-setflag-insn-base.
54 (float-setflag-unordered-insn): New pmacro for generating instructions.
55
6ce26ac7
SH		 562019-06-13 Andrey Bacherov <avbacherov@opencores.org>
57 Stafford Horne <shorne@gmail.com>
58
59 * or1k.cpu (ORFPX64A32-MACHS): New pmacro.
60 (ORFPX-MACHS): Removed pmacro.
61 * or1k.opc (or1k_cgen_insn_supported): New function.
62 (CGEN_VALIDATE_INSN_SUPPORTED): Define macro.
63 (parse_regpair, print_regpair): New functions.
64 * or1kcommon.cpu (h-spr, spr-shift, spr-address, h-gpr): Reorder
65 and add comments.
66 (h-fdr): Update comment to indicate or64.
67 (reg-pair-reg-lo, reg-pair-reg-hi): New pmacros for register pairs.
68 (h-fd32r): New hardware for 64-bit fpu registers.
69 (h-i64r): New hardware for 64-bit int registers.
70 * or1korbis.cpu (f-resv-8-1): New field.
71 * or1korfpx.cpu (rDSF, rASF, rBSF): Update attribute to ORFPX32-MACHS.
72 (rDDF, rADF, rBDF): Update operand comment to indicate or64.
73 (f-rdoff-10-1, f-raoff-9-1, f-rboff-8-1): New fields.
74 (h-roff1): New hardware.
75 (double-field-and-ops mnemonic): New pmacro to generate operations
76 rDD32F, rAD32F, rBD32F, rDDI and rADI.
77 (float-regreg-insn): Update single precision generator to MACH
78 ORFPX32-MACHS. Add generator for or32 64-bit instructions.
79 (float-setflag-insn): Update single precision generator to MACH
80 ORFPX32-MACHS. Fix double instructions from single to double
81 precision. Add generator for or32 64-bit instructions.
82 (float-cust-insn cust-num): Update single precision generator to MACH
83 ORFPX32-MACHS. Add generator for or32 64-bit instructions.
84 (lf-rem-s, lf-itof-s, lf-ftoi-s, lf-madd-s): Update MACH to
85 ORFPX32-MACHS.
86 (lf-rem-d): Fix operation from mod to rem.
87 (lf-rem-d32, lf-itof-d32, lf-ftoi-d32, lf-madd-d32): New instruction.
88 (lf-itof-d): Fix operands from single to double.
89 (lf-ftoi-d): Update operand mode from DI to WI.
90
ea195bb0
JM		 912019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
92
93 * bpf.cpu: New file.
94 * bpf.opc: Likewise.
95
f974f26c
NC		 962018-06-24 Nick Clifton <nickc@redhat.com>
97
98 2.32 branch created.
99
07f5f4c6
RH		 1002018-10-05 Richard Henderson <rth@twiddle.net>
101 Stafford Horne <shorne@gmail.com>
102
103 * or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU.
104 (insn-opcode-alu-regreg): Add opcodes for MULD and MULDU.
105 (l-mul): Fix overflow support and indentation.
106 (l-mulu): Fix overflow support and indentation.
107 (l-muld, l-muldu, l-msbu, l-macu): New instructions.
108 (l-div); Remove incorrect carry behavior.
109 (l-divu): Fix carry and overflow behavior.
110 (l-mac): Add overflow support.
111 (l-msb, l-msbu): Add carry and overflow support.
112
c8e98e36
SH		 1132018-10-05 Richard Henderson <rth@twiddle.net>
114
115 * or1k.opc (parse_disp26): Add support for plta() relocations.
116 (parse_disp21): New function.
117 (or1k_rclass): New enum.
118 (or1k_rtype): New enum.
119 (or1k_imm16_relocs): Define new PO and SPO relocation mappings.
120 (parse_reloc): Add new po(), gotpo() and gottppo() for LO13 relocations.
121 (parse_imm16): Add support for the new 21bit and 13bit relocations.
122 * or1korbis.cpu (f-disp26): Don't assume SI.
123 (f-disp21): New pc-relative 21-bit 13 shifted to right.
124 (insn-opcode): Add ADRP.
125 (l-adrp): New instruction.
126
1c4f3780
RH		 1272018-10-05 Richard Henderson <rth@twiddle.net>
128
129 * or1k.opc: Add RTYPE_ enum.
130 (INVALID_STORE_RELOC): New string.
131 (or1k_imm16_relocs): New array array.
132 (parse_reloc): New static function that just does the parsing.
133 (parse_imm16): New static function for generic parsing.
134 (parse_simm16): Change to just call parse_imm16.
135 (parse_simm16_split): New function.
136 (parse_uimm16): Change to call parse_imm16.
137 (parse_uimm16_split): New function.
138 * or1korbis.cpu (simm16-split): Change to use new simm16_split.
139 (uimm16-split): Change to use new uimm16_split.
140
67ce483b
AM		 1412018-07-24 Alan Modra <amodra@gmail.com>
142
143 PR 23430
144 * or1kcommon.cpu (spr-reg-indices): Fix description typo.
145
84f9f8c3
AM		 1462018-05-09 Sebastian Rasmussen <sebras@gmail.com>
147
148 * or1kcommon.cpu (spr-reg-info): Typo fix.
149
a6743a54
AM		 1502018-03-03 Alan Modra <amodra@gmail.com>
151
152 * frv.opc: Include opintl.h.
153 (add_next_to_vliw): Use opcodes_error_handler to print error.
154 Standardize error message.
155 (fr500_check_insn_major_constraints, frv_vliw_add_insn): Likewise.
156
faf766e3
NC		 1572018-01-13 Nick Clifton <nickc@redhat.com>
158
159 2.30 branch created.
160
4ea0266c
SH		 1612017-03-15 Stafford Horne <shorne@gmail.com>
162
163 * or1kcommon.cpu: Add pc set semantics to also update ppc.
164
b781683b
AM		 1652016-10-06 Alan Modra <amodra@gmail.com>
166
167 * mep.opc (expand_string): Add fall through comment.
168
439baf71
AM		 1692016-03-03 Alan Modra <amodra@gmail.com>
170
171 * fr30.cpu (f-m4): Replace bogus comment with a better guess
172 at what is really going on.
173
62de1c63
AM		 1742016-03-02 Alan Modra <amodra@gmail.com>
175
176 * fr30.cpu (f-m4): Replace -1 << 4 with -16.
177
b89807c6
AB		 1782016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
179
180 * epiphany.opc (epiphany_print_insn): Set info->bytes_per_line to
181 a constant to better align disassembler output.
182
018dc9be
SK		 1832014-07-20 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
184
185 * or1korbis.cpu (l-msync, l-psync, l-csync): New instructions.
186
c151b1c6
AM		 1872014-06-12 Alan Modra <amodra@gmail.com>
188
189 * or1k.opc: Whitespace fixes.
190
999b995d
SK		 1912014-05-08 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
192
193 * or1korbis.cpu (h-atomic-reserve): New hardware.
194 (h-atomic-address): Likewise.
195 (insn-opcode): Add opcodes for LWA and SWA.
196 (atomic-reserve): New operand.
197 (atomic-address): Likewise.
198 (l-lwa, l-swa): New instructions.
199 (l-lbs): Fix typo in comment.
200 (store-insn): Clear atomic reserve on store to atomic-address.
201 Fix register names in fmt field.
202
73589c9d
CS		 2032014-04-22 Christian Svensson <blue@cmd.nu>
204
205 * openrisc.cpu: Delete.
206 * openrisc.opc: Delete.
207 * or1k.cpu: New file.
208 * or1k.opc: New file.
209 * or1kcommon.cpu: New file.
210 * or1korbis.cpu: New file.
211 * or1korfpx.cpu: New file.
212
594d8fa8
MF		 2132013-12-07 Mike Frysinger <vapier@gentoo.org>
214
215 * epiphany.opc: Remove +x file mode.
216
87a8d6cb
NC		 2172013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
218
219 PR binutils/15241
220 * lm32.cpu (Control and status registers): Add CFG2, PSW,
221 TLBVADDR, TLBPADDR and TLBBADVADDR.
222
02a79b89
JR		 2232012-11-30 Oleg Raikhman <oleg@adapteva.com>
224 Joern Rennecke <joern.rennecke@embecosm.com>
225
226 * epiphany.cpu (keyword gr-names): Move sb/sl/ip after r9/r10/r12.
227 (load_insn): Add NO-DIS attribute to x, p, d, dpm, dl0, dl0.l.
228 (testset-insn): Add NO_DIS attribute to t.l.
229 (store-insn): Add NO-DIS attribute to x.l, p.l, d.l, dpm.l, dl0.l.
230 (move-insns): Add NO-DIS attribute to cmov.l.
231 (op-mmr-movts): Add NO-DIS attribute to movts.l.
232 (op-mmr-movfs): Add NO-DIS attribute to movfs.l.
233 (op-rrr): Add NO-DIS attribute to .l.
234 (shift-rrr): Add NO-DIS attribute to .l.
235 (op-shift-rri): Add NO-DIS attribute to i32.l.
236 (bitrl, movtl): Add NO-DIS attribute.
237 (op-iextrrr): Add NO-DIS attribute to .l
238 (op-two_operands-float, op-fabs-float): Add NO-DIS attribute to f32.l.
239 (op-fix2float-float, op-float2fix-float, op-fextop-float): Likewise.
240
a597d2d3
AM		 2412012-02-27 Alan Modra <amodra@gmail.com>
242
243 * mt.opc (print_dollarhex): Trim values to 32 bits.
244
5011093d
NC		 2452011-12-15 Nick Clifton <nickc@redhat.com>
246
247 * frv.opc (parse_uhi16): Fix handling of %hi operator on 64-bit
248 hosts.
249
fd936b4c
JR		 2502011-10-26 Joern Rennecke <joern.rennecke@embecosm.com>
251
252 * epiphany.opc (parse_branch_addr): Fix type of valuep.
253 Cast value before printing it as a long.
254 (parse_postindex): Fix type of valuep.
255
cfb8c092
NC		 2562011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
257
258 * cpu/epiphany.cpu: New file.
259 * cpu/epiphany.opc: New file.
260
dc15e575
NC		 2612011-08-22 Nick Clifton <nickc@redhat.com>
262
263 * fr30.cpu: Newly contributed file.
264 * fr30.opc: Likewise.
265 * ip2k.cpu: Likewise.
266 * ip2k.opc: Likewise.
267 * mep-avc.cpu: Likewise.
268 * mep-avc2.cpu: Likewise.
269 * mep-c5.cpu: Likewise.
270 * mep-core.cpu: Likewise.
271 * mep-default.cpu: Likewise.
272 * mep-ext-cop.cpu: Likewise.
273 * mep-fmax.cpu: Likewise.
274 * mep-h1.cpu: Likewise.
275 * mep-ivc2.cpu: Likewise.
276 * mep-rhcop.cpu: Likewise.
277 * mep-sample-ucidsp.cpu: Likewise.
278 * mep.cpu: Likewise.
279 * mep.opc: Likewise.
280 * openrisc.cpu: Likewise.
281 * openrisc.opc: Likewise.
282 * xstormy16.cpu: Likewise.
283 * xstormy16.opc: Likewise.
284
9ccb8af9
AM		 2852010-10-08 Pierre Muller <muller@ics.u-strasbg.fr>
286
287 * frv.opc: #undef DEBUG.
288
21375995
DD		 2892010-07-03 DJ Delorie <dj@delorie.com>
290
291 * m32c.cpu (f-dsp-8-s24): Mask high byte after shifting it.
292
5ff58fb0
DE		 2932010-02-11 Doug Evans <dje@sebabeach.org>
294
295 * m32r.cpu (HASH-PREFIX): Delete.
296 (duhpo, dshpo): New pmacros.
297 (simm8, simm16): Delete HASH-PREFIX attribute, define with dshpo.
298 (uimm3, uimm4, uimm5, uimm8, uimm16, imm1): Delete HASH-PREFIX
299 attribute, define with dshpo.
300 (uimm24): Delete HASH-PREFIX attribute.
301 * m32r.opc (CGEN_PRINT_NORMAL): Delete.
302 (print_signed_with_hash_prefix): New function.
303 (print_unsigned_with_hash_prefix): New function.
304 * xc16x.cpu (dowh): New pmacro.
305 (upof16): Define with dowh, specify print handler.
306 (qbit, qlobit, qhibit): Ditto.
307 (upag16): Ditto.
308 * xc16x.opc (CGEN_PRINT_NORMAL): Delete.
309 (print_with_dot_prefix): New functions.
310 (print_with_pof_prefix, print_with_pag_prefix): New functions.
311
3fa5b97b
DE		 3122010-01-24 Doug Evans <dje@sebabeach.org>
313
314 * frv.cpu (floating-point-conversion): Update call to fp conv op.
315 (floating-point-dual-conversion, ne-floating-point-dual-conversion,
316 conditional-floating-point-conversion, ne-floating-point-conversion,
317 float-parallel-mul-add-double-semantics): Ditto.
318
fe8afbc4
DE		 3192010-01-05 Doug Evans <dje@sebabeach.org>
320
321 * m32c.cpu (f-dsp-32-u24): Fix mode of extract handler.
322 (f-dsp-40-u20, f-dsp-40-u24): Ditto.
323
caaf56fb
DE		 3242010-01-02 Doug Evans <dje@sebabeach.org>
325
326 * m32c.opc (parse_signed16): Fix typo.
327
91d6fa6a
NC		 3282009-12-11 Nick Clifton <nickc@redhat.com>
329
330 * frv.opc: Fix shadowed variable warnings.
331 * m32c.opc: Fix shadowed variable warnings.
332
ec84cc2b
DE		 3332009-11-14 Doug Evans <dje@sebabeach.org>
334
335 Must use VOID expression in VOID context.
336 * xc16x.cpu (mov4): Fix mode of `sequence'.
337 (mov9, mov10): Ditto.
338 (movbsrr, moveb1, jmprel, jmpseg, jmps): Fix mode of `if'.
339 (callr, callseg, calls, trap, rets, reti): Ditto.
340 (jb, jbc, jnb, jnbs): Fix mode of `if'. Comment out no-op `sll'.
341 (atomic, extr, extp, extp1, extpg1, extpr, extpr1): Fix mode of `cond'.
342 (exts, exts1, extsr, extsr1, prior): Ditto.
343
ac1e9eca
DE		 3442009-10-23 Doug Evans <dje@sebabeach.org>
345
346 * m32c.opc (opc.h): cgen-types.h -> cgen/basic-modes.h.
347 cgen-ops.h -> cgen/basic-ops.h.
348
b4744b17
AM		 3492009-09-25 Alan Modra <amodra@bigpond.net.au>
350
351 * m32r.cpu (stb-plus): Typo fix.
352
ab5f875d
DE		 3532009-09-23 Doug Evans <dje@sebabeach.org>
354
355 * m32r.cpu (sth-plus): Fix address mode and calculation.
356 (stb-plus): Ditto.
357 (clrpsw): Fix mask calculation.
358 (bset, bclr, btst): Make mode in bit calculation match expression.
359
360 * xc16x.cpu (rtl-version): Set to 0.8.
361 (gr-names, ext-names,psw-names): Update, print-name -> enum-prefix,
362 make uppercase. Remove unnecessary name-prefix spec.
363 (grb-names, conditioncode-names, extconditioncode-names): Ditto.
364 (grb8-names, r8-names, regmem8-names, regdiv8-names): Ditto.
365 (reg0-name, reg0-name1, regbmem8-names, memgr8-names): Ditto.
366 (h-cr): New hardware.
367 (muls): Comment out parts that won't compile, add fixme.
368 (mulu, divl, divlu, jmpabs, jmpa-, jmprel, jbc, jnbs, callr): Ditto.
369 (scxti, scxtmg, scxtm, bclear, bclr18, bset19, bitset, bmov): Ditto.
370 (bmovn, band, bor, bxor, bcmp, bfldl, bfldh): Ditto.
371
0aaaf7c3
DE		 3722009-07-16 Doug Evans <dje@sebabeach.org>
373
374 * cpu/simplify.inc (*): One line doc strings don't need \n.
375 (df): Invoke define-full-ifield instead of claiming it's an alias.
376 (dno): Define.
377 (dnop): Mark as deprecated.
378
1998a8e0
AM		 3792009-06-22 Alan Modra <amodra@bigpond.net.au>
380
381 * m32c.opc (parse_lab_5_3): Use correct enum.
382
6347aad8
HPN		 3832009-01-07 Hans-Peter Nilsson <hp@axis.com>
384
385 * frv.cpu (mabshs): Explicitly sign-extend arguments of abs to DI.
386 (DI-ext-HI, DI-ext-UHI, DI-ext-DI): New pmacros.
387 (media-arith-sat-semantics): Explicitly sign- or zero-extend
388 arguments of "operation" to DI using "mode" and the new pmacros.
389
2c06b7a6
HPN		 3902009-01-03 Hans-Peter Nilsson <hp@axis.com>
391
392 * cris.cpu (cris-implemented-writable-specregs-v32): Correct size
393 of number 2, PID.
394
84e94c90
NC		 3952008-12-23 Jon Beniston <jon@beniston.com>
396
397 * lm32.cpu: New file.
398 * lm32.opc: New file.
399
90518ff4
AM		 4002008-01-29 Alan Modra <amodra@bigpond.net.au>
401
402 * mt.opc (parse_imm16): Apply 2007-09-26 opcodes/mt-asm.c change
403 to source.
404
a69f60de
HPN		 4052007-10-22 Hans-Peter Nilsson <hp@axis.com>
406
407 * cris.cpu (movs, movu): Use result of extension operation when
408 updating flags.
409
9b201bb5
NC		 4102007-07-04 Nick Clifton <nickc@redhat.com>
411
412 * cris.cpu: Update copyright notice to refer to GPLv3.
413 * frv.cpu, frv.opc, iq10.cpu, iq2000m.cpu, iq2000.opc, m32c.cpu,
414 m32c.opc, m32r.cpu, m32r.opc, mt.cpu, mt.opc, sh64-compact.cpu,
415 sh64-media.cpu, sh.cpu, sh.opc, simplify.inc, xc16x.cpu,
416 xc16x.opc: Likewise.
417 * iq2000.cpu: Fix copyright notice to refer to FSF.
418
53289dcd
MS		 4192007-04-30 Mark Salter <msalter@sadr.localdomain>
420
421 * frv.cpu (spr-names): Support new coprocessor SPR registers.
422
f6da2ec2
NC		 4232007-04-20 Nick Clifton <nickc@redhat.com>
424
425 * xc16x.cpu: Restore after accidentally overwriting this file with
426 xc16x.opc.
427
144f4bc6
DD		 4282007-03-29 DJ Delorie <dj@redhat.com>
429
430 * m32c.cpu (Imm-8-s4n): Fix print hook.
431 (Lab-24-8, Lab-32-8, Lab-40-8): Fix.
432 (arith-jnz-imm4-dst-defn): Make relaxable.
433 (arith-jnz16-imm4-dst-defn): Fix encodings.
434
75b06e7b
DD		 4352007-03-20 DJ Delorie <dj@redhat.com>
436
437 * m32c.cpu (f-dsp-40-u20, f-dsp-48-u20, Dsp-40-u20, Dsp-40-u20,
438 mem20): New.
439 (src16-16-20-An-relative-*): New.
440 (dst16-*-20-An-relative-*): New.
441 (dst16-16-16sa-*): New
442 (dst16-16-16ar-*): New
443 (dst32-16-16sa-Unprefixed-*): New
444 (jsri): Fix operands.
445 (setzx): Fix encoding.
72f4393d 446
a5da764d
AM		 4472007-03-08 Alan Modra <amodra@bigpond.net.au>
448
449 * m32r.opc: Formatting.
450
b497d0b0
NC		 4512006-05-22 Nick Clifton <nickc@redhat.com>
452
453 * iq2000.cpu: Fix include paths for iq2000m.cpu and iq10.cpu.
454
e78efa90
DD		 4552006-04-10 DJ Delorie <dj@redhat.com>
456
457 * m32c.opc (parse_unsigned_bitbase): Take a new parameter which
458 decides if this function accepts symbolic constants or not.
459 (parse_signed_bitbase): Likewise.
460 (parse_unsigned_bitbase8): Pass the new parameter.
461 (parse_unsigned_bitbase11): Likewise.
462 (parse_unsigned_bitbase16): Likewise.
463 (parse_unsigned_bitbase19): Likewise.
464 (parse_unsigned_bitbase27): Likewise.
465 (parse_signed_bitbase8): Likewise.
466 (parse_signed_bitbase11): Likewise.
467 (parse_signed_bitbase19): Likewise.
72f4393d 468
8d0e2679
DD		 4692006-03-13 DJ Delorie <dj@redhat.com>
470
43aa3bb1
DD		 471 * m32c.cpu (Bit3-S): New.
472 (btst:s): New.
473 * m32c.opc (parse_bit3_S): New.
474
8d0e2679
DD		 475 * m32c.cpu (decimal-subtraction16-insn): Add second operand.
476 (btst): Add optional :G suffix for MACH32.
477 (or.b:S): New.
478 (pop.w:G): Add optional :G suffix for MACH16.
479 (push.b.imm): Fix syntax.
480
253d272c
DD		 4812006-03-10 DJ Delorie <dj@redhat.com>
482
483 * m32c.cpu (mul.l): New.
484 (mulu.l): New.
485
c7d41dc5
NC		 4862006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
487
488 * xc16x.opc (parse_hash): Return NULL if the input was parsed or
489 an error message otherwise.
490 (parse_dot, parse_pof, parse_pag, parse_sof, parse_seg): Likewise.
491 Fix up comments to correctly describe the functions.
492
6772dd07
DD		 4932006-02-24 DJ Delorie <dj@redhat.com>
494
495 * m32c.cpu (RL_TYPE): New attribute, with macros.
496 (Lab-8-24): Add RELAX.
497 (unary-insn-defn-g, binary-arith-imm-dst-defn,
498 binary-arith-imm4-dst-defn): Add 1ADDR attribute.
499 (binary-arith-src-dst-defn): Add 2ADDR attribute.
500 (jcnd16-5, jcnd16, jcnd32, jmp16.s, jmp16.b, jmp16.w, jmp16.a,
501 jmp32.s, jmp32.b, jmp32.w, jmp32.a, jsr16.w, jsr16.a): Add JUMP
502 attribute.
503 (jsri16, jsri32): Add 1ADDR attribute.
504 (jsr32.w, jsr32.a): Add JUMP attribute.
72f4393d 505
d70c5fc7 5062006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
72f4393d
L		 507 Anil Paranjape <anilp1@kpitcummins.com>
508 Shilin Shakti <shilins@kpitcummins.com>
d70c5fc7
NC		 509
510 * xc16x.cpu: New file containing complete CGEN specific XC16X CPU
511 description.
512 * xc16x.opc: New file containing supporting XC16C routines.
513
8536c657
NC		 5142006-02-10 Nick Clifton <nickc@redhat.com>
515
516 * iq2000.opc (parse_hi16): Truncate shifted values to 16 bits.
517
458f7770
DD		 5182006-01-06 DJ Delorie <dj@redhat.com>
519
520 * m32c.cpu (mov.w:q): Fix mode.
521 (push32.b.imm): Likewise, for the comment.
522
d031aafb
NS		 5232005-12-16 Nathan Sidwell <nathan@codesourcery.com>
524
525 Second part of ms1 to mt renaming.
526 * mt.cpu (define-arch, define-isa): Set name to mt.
527 (define-mach): Adjust.
528 * mt.opc (CGEN_ASM_HASH): Update.
529 (mt_asm_hash, mt_cgen_insn_supported): Renamed.
530 (parse_loopsize, parse_imm16): Adjust.
531
eda87aba
DD		 5322005-12-13 DJ Delorie <dj@redhat.com>
533
534 * m32c.cpu (jsri): Fix order so register names aren't treated as
535 symbols.
536 (indexb, indexbd, indexbs, indexl, indexld, indexls, indexw,
537 indexwd, indexws): Fix encodings.
538
4970f871
NS		 5392005-12-12 Nathan Sidwell <nathan@codesourcery.com>
540
541 * mt.cpu: Rename from ms1.cpu.
542 * mt.opc: Rename from ms1.opc.
543
48ad8298
HPN		 5442005-12-06 Hans-Peter Nilsson <hp@axis.com>
545
546 * cris.cpu (simplecris-common-writable-specregs)
547 (simplecris-common-readable-specregs): Split from
548 simplecris-common-specregs. All users changed.
549 (cris-implemented-writable-specregs-v0)
550 (cris-implemented-readable-specregs-v0): Similar from
551 cris-implemented-specregs-v0.
552 (cris-implemented-writable-specregs-v3)
553 (cris-implemented-readable-specregs-v3)
554 (cris-implemented-writable-specregs-v8)
555 (cris-implemented-readable-specregs-v8)
556 (cris-implemented-writable-specregs-v10)
557 (cris-implemented-readable-specregs-v10)
558 (cris-implemented-writable-specregs-v32)
559 (cris-implemented-readable-specregs-v32): Similar.
560 (bdap-32-pc, move-m-pcplus-p0, move-m-spplus-p8): New
561 insns and specializations.
562
6f84a2a6
NS		 5632005-11-08 Nathan Sidwell <nathan@codesourcery.com>
564
565 Add ms2
566 * ms1.cpu (ms2, ms2bf): New architecture variant, cpu, machine and
567 model.
568 (f-uu8, f-uu1, f-imm16l, f-loopo, f-cb1sel, f-cb2sel, f-cb1incr,
569 f-cb2incr, f-rc3): New fields.
570 (LOOP): New instruction.
571 (JAL-HAZARD): New hazard.
572 (imm16o, loopsize, imm16l, rc3, cb1sel, cb2sel, cb1incr, cb2incr):
573 New operands.
574 (mul, muli, dbnz, iflush): Enable for ms2
575 (jal, reti): Has JAL-HAZARD.
576 (ldctxt, ldfb, stfb): Only ms1.
577 (fbcb): Only ms1,ms1-003.
578 (wfbinc, mefbinc, wfbincr, mwfbincr, fbcbincs, mfbcbincs,
579 fbcbincrs, mfbcbincrs): Enable for ms2.
580 (loop, loopu, dfbc, dwfb, fbwfb, dfbr): New ms2 insns.
581 * ms1.opc (parse_loopsize): New.
582 (parse_imm16): hi16/lo16 relocs are applicable to IMM16L.
583 (print_pcrel): New.
584
95b96521
DB		 5852005-10-28 Dave Brolley <brolley@redhat.com>
586
587 Contribute the following change:
588 2003-09-24 Dave Brolley <brolley@redhat.com>
589
590 * frv.opc: Use CGEN_ATTR_VALUE_ENUM_TYPE in place of
591 CGEN_ATTR_VALUE_TYPE.
592 * m32c.opc (m32c_cgen_insn_supported): Use CGEN_INSN_BITSET_ATTR_VALUE.
593 Use cgen_bitset_intersect_p.
594
c6552317
DD		 5952005-10-27 DJ Delorie <dj@redhat.com>
596
597 * m32c.cpu (Imm-8-s4n, Imm-12-s4n): New.
598 (arith-jnz16-imm4-dst-defn, arith-jnz32-imm4-dst-defn,
599 arith-jnz-imm4-dst-mach, arith-jnz-imm4-dst): Keep track of which
600 imm operand is needed.
601 (adjnz, sbjnz): Pass the right operands.
602 (unary-insn-defn, unary16-defn, unary32-defn, unary-insn-mach,
603 unary-insn): Add -g variants for opcodes that need to support :G.
604 (not.BW:G, push.BW:G): Call it.
605 (stzx16-imm8-imm8-dsp8sb, stzx16-imm8-imm8-dsp8fb,
606 stzx16-imm8-imm8-abs16): Fix operand typos.
607 * m32c.opc (m32c_asm_hash): Support bnCND.
608 (parse_signed4n, print_signed4n): New.
72f4393d 609
f75eb1c0
DD		 6102005-10-26 DJ Delorie <dj@redhat.com>
611
612 * m32c.cpu (f-dsp-8-s24, Dsp-8-s24): New.
613 (mov-dspsp-dst-defn, mov-src-dspsp-defn, mov16-dspsp-dst-defn,
614 mov16-src-dspsp-defn, mov32-dspsp-dst-defn, mov32-src-dspsp-defn):
615 dsp8[sp] is signed.
616 (mov.WL:S #imm,A0/A1): dsp24 is signed (i.e. -0x800000..0xffffff).
617 (mov.BW:S r0,r1): Fix typo r1l->r1.
618 (tst): Allow :G suffix.
619 * m32c.opc (parse_signed24): New, for -0x800000..0xffffff.
620
e277c00b
AM		 6212005-10-26 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
622
623 * m32r.opc (parse_hi16): Do not assume a 32-bit host word size.
624
92e0a941
DD		 6252005-10-25 DJ Delorie <dj@redhat.com>
626
627 * m32c.cpu (add16-bQ-sp,add16-wQ-sp): Fix to allow either width by
628 making one a macro of the other.
629
a1a280bb
DD		 6302005-10-21 DJ Delorie <dj@redhat.com>
631
632 * m32c.cpu (lde, ste): Add dsp[a0] and [a1a] addressing.
633 (indexb, indexbd, indexbs, indexw, indexwd, indexws, indexl,
634 indexld, indexls): .w variants have `1' bit.
635 (rot32.b): QI, not SI.
636 (rot32.w): HI, not SI.
637 (xchg16): HI for .w variant.
638
e74eb924
NC		 6392005-10-19 Nick Clifton <nickc@redhat.com>
640
641 * m32r.opc (parse_slo16): Fix bad application of previous patch.
642
5e03663f
NC		 6432005-10-18 Andreas Schwab <schwab@suse.de>
644
645 * m32r.opc (parse_slo16): Better version of previous patch.
646
ab7c9a26
NC		 6472005-10-14 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
648
649 * cpu/m32r.opc (parse_slo16): Do not assume a 32-bit host word
650 size.
651
fd54057a
DD		 6522005-07-25 DJ Delorie <dj@redhat.com>
653
654 * m32c.opc (parse_unsigned8): Add %dsp8().
655 (parse_signed8): Add %hi8().
656 (parse_unsigned16): Add %dsp16().
657 (parse_signed16): Add %lo16() and %hi16().
658 (parse_lab_5_3): Make valuep a bfd_vma *.
659
85da3a56
NC		 6602005-07-18 Nick Clifton <nickc@redhat.com>
661
662 * m32c.cpu (f-16-8, f-24-8, f-32-16, f-dsp-8-u24): New opcode
663 components.
664 (f-lab32-jmp-s): Fix insertion sequence.
665 (Dsp-8-u24, Lab-5-3, Lab32-jmp-s): New operands.
666 (Dsp-40-s8): Make parameter be signed.
667 (Dsp-40-s16): Likewise.
668 (Dsp-48-s8): Likewise.
669 (Dsp-48-s16): Likewise.
670 (Imm-13-u3): Likewise. (Despite its name!)
671 (BitBase16-16-s8): Make the parameter be unsigned.
672 (BitBase16-8-u11-S): Likewise.
673 (Lab-8-8, Lab-8-16, Lab-16-8, jcnd16-5, jcnd16, jcnd32, jmp16.s,
674 jmp16.b, jmp16.w, jmp32.s, jmp32.b, jmp32.w, jsp16.w, jsr32.w): Allow
675 relaxation.
676
677 * m32c.opc: Fix formatting.
678 Use safe-ctype.h instead of ctype.h
679 Move duplicated code sequences into a macro.
680 Fix compile time warnings about signedness mismatches.
681 Remove dead code.
682 (parse_lab_5_3): New parser function.
72f4393d 683
aa260854
JB		 6842005-07-16 Jim Blandy <jimb@redhat.com>
685
686 * m32c.opc (m32c_cgen_insn_supported): Use int, not CGEN_BITSET,
687 to represent isa sets.
688
0a665bfd
JB		 6892005-07-15 Jim Blandy <jimb@redhat.com>
690
691 * m32c.cpu, m32c.opc: Fix copyright.
692
49f58d10
JB		 6932005-07-14 Jim Blandy <jimb@redhat.com>
694
695 * m32c.cpu, m32c.opc: Machine description for the Renesas M32C.
696
0e6b69be
AM		 6972005-07-14 Alan Modra <amodra@bigpond.net.au>
698
699 * ms1.opc (print_dollarhex): Correct format string.
700
f9210e37
AM		 7012005-07-06 Alan Modra <amodra@bigpond.net.au>
702
703 * iq2000.cpu: Include from binutils cpu dir.
704
3ec2b351
NC		 7052005-07-05 Nick Clifton <nickc@redhat.com>
706
707 * iq2000.opc (parse_lo16, parse_mlo16): Make value parameter
708 unsigned in order to avoid compile time warnings about sign
709 conflicts.
710
711 * ms1.opc (parse_*): Likewise.
712 (parse_imm16): Use a "void *" as it is passed both signed and
713 unsigned arguments.
714
47b0e7ad
NC		 7152005-07-01 Nick Clifton <nickc@redhat.com>
716
717 * frv.opc: Update to ISO C90 function declaration style.
718 * iq2000.opc: Likewise.
719 * m32r.opc: Likewise.
720 * sh.opc: Likewise.
721
b081650b
DB		 7222005-06-15 Dave Brolley <brolley@redhat.com>
723
724 Contributed by Red Hat.
725 * ms1.cpu: New file. Written by Nick Clifton, Stan Cox.
726 * ms1.opc: New file. Written by Stan Cox.
727
e172dbf8
NC		 7282005-05-10 Nick Clifton <nickc@redhat.com>
729
730 * Update the address and phone number of the FSF organization in
731 the GPL notices in the following files:
732 cris.cpu, frv.cpu, frv.opc, iq10.cpu, iq2000.opc, iq2000m.cpu,
733 m32r.cpu, m32r.opc, sh.cpu, sh.opc, sh64-compact.cpu,
734 sh64-media.cpu, simplify.inc
735
b2d52a48
AM		 7362005-02-24 Alan Modra <amodra@bigpond.net.au>
737
738 * frv.opc (parse_A): Warning fix.
739
33b71eeb
NC		 7402005-02-23 Nick Clifton <nickc@redhat.com>
741
742 * frv.opc: Fixed compile time warnings about differing signed'ness
743 of pointers passed to functions.
744 * m32r.opc: Likewise.
745
bc18c937
NC		 7462005-02-11 Nick Clifton <nickc@redhat.com>
747
748 * iq2000.opc (parse_jtargq10): Change type of valuep argument to
749 'bfd_vma *' in order avoid compile time warning message.
750
46da9a19
HPN		 7512005-01-28 Hans-Peter Nilsson <hp@axis.com>
752
753 * cris.cpu (mstep): Add missing insn.
754
90219bd0
AO		 7552005-01-25 Alexandre Oliva <aoliva@redhat.com>
756
757 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
758 * frv.cpu: Add support for TLS annotations in loads and calll.
759 * frv.opc (parse_symbolic_address): New.
760 (parse_ldd_annotation): New.
761 (parse_call_annotation): New.
762 (parse_ld_annotation): New.
763 (parse_ulo16, parse_uslo16): Use parse_symbolic_address.
764 Introduce TLS relocations.
765 (parse_d12, parse_s12, parse_u12): Likewise.
766 (parse_uhi16): Likewise. Fix constant checking on 64-bit host.
767 (parse_call_label, print_at): New.
768
c3d75c30
HPN		 7692004-12-21 Mikael Starvik <starvik@axis.com>
770
771 * cris.cpu (cris-set-mem): Correct integral write semantics.
772
68800d83
HPN		 7732004-11-29 Hans-Peter Nilsson <hp@axis.com>
774
775 * cris.cpu: New file.
776
4bd1d37b
NC		 7772004-11-15 Michael K. Lechner <mike.lechner@gmail.com>
778
779 * iq2000.cpu: Added quotes around macro arguments so that they
780 will work with newer versions of guile.
781
4030fa5a
NC		 7822004-10-27 Nick Clifton <nickc@redhat.com>
783
784 * iq2000m.cpu (pkrlr1, pkrlr30, rbr1, rbr30, rxr1, rxr30, wbr1,
785 wbr1u, wbr30, wbr30u, wxr1, wxr1u, wxr30, wxr30u): Add an index
786 operand.
787 * iq2000.cpu (dnop index): Rename to _index to avoid complications
788 with guile.
789
ac28a1cb
RS		 7902004-08-27 Richard Sandiford <rsandifo@redhat.com>
791
792 * frv.cpu (cfmovs): Change UNIT attribute to FMALL.
793
dc4c54bb
NC		 7942004-05-15 Nick Clifton <nickc@redhat.com>
795
796 * iq2000.opc (iq2000_cgen_insn_supported): Make 'insn' argument const.
797
f4453dfa
NC		 7982004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
799
800 * m32r.opc (parse_hi16): Fixed shigh(0xffff8000) bug.
801
676a64f4
RS		 8022004-03-01 Richard Sandiford <rsandifo@redhat.com>
803
804 * frv.cpu (define-arch frv): Add fr450 mach.
805 (define-mach fr450): New.
806 (define-model fr450): New. Add profile units to every fr450 insn.
807 (define-attr UNIT): Add MDCUTSSI.
808 (define-attr FR450-MAJOR): New enum. Add to every fr450 insn.
809 (define-attr AUDIO): New boolean.
810 (f-LRAE, f-LRAD, f-LRAS, f-TLBPRopx, f-TLBPRL)
811 (f-LRA-null, f-TLBPR-null): New fields.
812 (scr0, scr1, scr2, scr3, imavr1, damvr1, cxnr, ttbr)
813 (tplr, tppr, tpxr, timerh, timerl, timerd, btbr): New SPRs.
814 (LRAE, LRAD, LRAS, TLBPRopx, TLBPRL): New operands.
815 (LRA-null, TLBPR-null): New macros.
816 (iacc-multiply-r-r, slass, scutss, int-arith-ss-r-r): Add AUDIO attr.
817 (load-real-address): New macro.
818 (lrai, lrad, tlbpr): New instructions.
819 (media-cut-acc, media-cut-acc-ss): Add fr450-major argument.
820 (mcut, mcuti, mcutss, mcutssi): Adjust accordingly.
821 (mdcutssi): Change UNIT attribute to MDCUTSSI.
822 (media-low-clear-semantics, media-scope-limit-semantics)
823 (media-quad-limit, media-quad-shift): New macros.
824 (mqlclrhs, mqlmths, mqsllhi, mqsrahi): New instructions.
825 * frv.opc (frv_is_branch_major, frv_is_float_major, frv_is_media_major)
826 (frv_is_branch_insn, frv_is_float_insn, frv_is_media_insn)
827 (frv_vliw_reset, frv_vliw_add_insn): Handle bfd_mach_fr450.
828 (fr450_unit_mapping): New array.
829 (fr400_unit_mapping, fr500_unit_mapping, fr550_unit_mapping): Add entry
830 for new MDCUTSSI unit.
831 (fr450_check_insn_major_constraints): New function.
832 (check_insn_major_constraints): Use it.
833
c7a48b9a
RS		 8342004-03-01 Richard Sandiford <rsandifo@redhat.com>
835
836 * frv.cpu (nsdiv, nudiv, nsdivi, nudivi): Remove fr400 profiling unit.
837 (scutss): Change unit to I0.
838 (calll, callil, ccalll): Add missing FR550-MAJOR and profile unit.
839 (mqsaths): Fix FR400-MAJOR categorization.
840 (media-quad-multiply-cross-acc, media-quad-cross-multiply-cross-acc)
841 (media-quad-cross-multiply-acc): Change unit from MDUALACC to FMALL.
842 * frv.opc (fr400_check_insn_major_constraints): Check for (M-2,M-1)
843 combinations.
844
8ae0baa2
RS		 8452004-03-01 Richard Sandiford <rsandifo@redhat.com>
846
847 * frv.cpu (r-store, r-store-dual, r-store-quad): Delete.
848 (rstb, rsth, rst, rstd, rstq): Delete.
849 (rstbf, rsthf, rstf, rstdf, rstqf): Delete.
850
8ee9a8b2
NC		 8512004-02-23 Nick Clifton <nickc@redhat.com>
852
853 * Apply these patches from Renesas:
854
855 2004-02-10 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
856
857 * cpu/m32r.opc (my_print_insn): Fixed incorrect output when
858 disassembling codes for 0x*2 addresses.
859
860 2003-12-15 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
861
862 * cpu/m32r.cpu: Add PIPE_O attribute to "pop" instruction.
863
864 2003-12-03 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
865
866 * cpu/m32r.cpu : Add new model m32r2.
867 Add new instructions.
868 Replace occurrances of 'Mitsubishi' with 'Renesas'.
869 Changed PIPE attr of push from O to OS.
870 Care for Little-endian of M32R.
871 * cpu/m32r.opc (CGEN_DIS_HASH, my_print_insn):
872 Care for Little-endian of M32R.
873 (parse_slo16): signed extension for value.
874
299d901c
AC		 8752004-02-20 Andrew Cagney <cagney@redhat.com>
876
e866a257
AC		 877 * m32r.opc, m32r.cpu: New files. Written by , Doug Evans, Nick
878 Clifton, Ben Elliston, Matthew Green, and Andrew Haley.
879
299d901c
AC		 880 * sh.cpu, sh.opc, sh64-compact.cpu, sh64-media.cpu: New files, all
881 written by Ben Elliston.
882
cb10e79a
RS		 8832004-01-14 Richard Sandiford <rsandifo@redhat.com>
884
885 * frv.cpu (UNIT): Add IACC.
886 (iacc-multiply-r-r): Use it.
887 * frv.opc (fr400_unit_mapping): Add entry for IACC.
888 (fr500_unit_mapping, fr550_unit_mapping): Likewise.
889
d4e4dc14
AO		 8902004-01-06 Alexandre Oliva <aoliva@redhat.com>
891
892 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
893 * frv.opc (parse_ulo16, parse_uhi16, parse_d12): Fix some
894 cut&paste errors in shifting/truncating numerical operands.
895 2003-08-08 Alexandre Oliva <aoliva@redhat.com>
896 * frv.opc (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
897 (parse_uslo16): Likewise.
898 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
899 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
900 (parse_s12): Likewise.
901 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
902 * frv.opc (parse_ulo16): Parse gotlo and gotfuncdesclo.
903 (parse_uslo16): Likewise.
904 (parse_uhi16): Parse gothi and gotfuncdeschi.
905 (parse_d12): Parse got12 and gotfuncdesc12.
906 (parse_s12): Likewise.
907
1340b9a9
DB		 9082003-10-10 Dave Brolley <brolley@redhat.com>
909
910 * frv.cpu (dnpmop): New p-macro.
911 (GRdoublek): Use dnpmop.
912 (CPRdoublek, FRdoublei, FRdoublej, FRdoublek): Ditto.
913 (store-double-r-r): Use (.sym regtype doublek).
914 (r-store-double): Ditto.
915 (store-double-r-r-u): Ditto.
916 (conditional-store-double): Ditto.
917 (conditional-store-double-u): Ditto.
918 (store-double-r-simm): Ditto.
919 (fmovs): Assign to UNIT FMALL.
920
ac7c07ac
DB		 9212003-10-06 Dave Brolley <brolley@redhat.com>
922
923 * frv.cpu, frv.opc: Add support for fr550.
924
d0312406
DB		 9252003-09-24 Dave Brolley <brolley@redhat.com>
926
927 * frv.cpu (u-commit): New modelling unit for fr500.
928 (mwtaccg): Use frv_ref_SI to reference ACC40Sk as an input operand.
929 (commit-r): Use u-commit model for fr500.
930 (commit): Ditto.
931 (conditional-float-binary-op): Take profiling data as an argument.
932 Update callers.
933 (ne-float-binary-op): Ditto.
934
c6945302
MS		 9352003-09-19 Michael Snyder <msnyder@redhat.com>
936
937 * frv.cpu (nldqi): Delete unimplemented instruction.
938
23600bb3
DB		 9392003-09-12 Dave Brolley <brolley@redhat.com>
940
941 * frv.cpu (u-clrgr, u-clrfr): New units of model fr500.
942 (clear-ne-flag-r): Pass insn profiling in as an argument. Call
943 frv_ref_SI to get input register referenced for profiling.
944 (clear-ne-flag-all): Pass insn profiling in as an argument.
945 (clrgr,clrfr,clrga,clrfa): Add profiling information.
946
6f18ad70
MS		 9472003-09-11 Michael Snyder <msnyder@redhat.com>
948
949 * frv.cpu: Typographical corrections.
950
96486995
DB		 9512003-09-09 Dave Brolley <brolley@redhat.com>
952
953 * frv.cpu (media-dual-complex): Change UNIT to FMALL.
954 (conditional-media-dual-complex, media-quad-complex): Likewise.
955
0457efce
DB		 9562003-09-04 Dave Brolley <brolley@redhat.com>
957
958 * frv.cpu (register-transfer): Pass in all attributes in on argument.
959 Update all callers.
960 (conditional-register-transfer): Ditto.
961 (cache-preload): Ditto.
962 (floating-point-conversion): Ditto.
963 (floating-point-neg): Ditto.
964 (float-abs): Ditto.
965 (float-binary-op-s): Ditto.
966 (conditional-float-binary-op): Ditto.
967 (ne-float-binary-op): Ditto.
968 (float-dual-arith): Ditto.
969 (ne-float-dual-arith): Ditto.
970
8caa9169
DB		 9712003-09-03 Dave Brolley <brolley@redhat.com>
972
973 * frv.opc (parse_A, parse_A0, parse_A1): New parse handlers.
974 * frv.cpu (UNIT): Add IALL, FMALL, FMLOW, STORE, SCAN, DCPL, MDUALACC,
975 MCLRACC-1.
976 (A): Removed operand.
977 (A0,A1): New operands replace operand A.
978 (mnop): Now a real insn
979 (mclracc): Removed insn.
980 (mclracc-0, mclracc-1): New insns replace mclracc.
981 (all insns): Use new UNIT attributes.
982
6d9ab561
NC		 9832003-08-21 Nick Clifton <nickc@redhat.com>
984
985 * frv.cpu (mbtoh): Replace input parameter to u-media-dual-expand
986 and u-media-dual-btoh with output parameter.
987 (cmbtoh): Add profiling hack.
988
741a7751
NC		 9892003-08-19 Michael Snyder <msnyder@redhat.com>
990
991 * frv.cpu: Fix typo, Frintkeven -> FRintkeven
992
5b5b78da
DE		 9932003-06-10 Doug Evans <dje@sebabeach.org>
994
995 * frv.cpu: Add IDOC attribute.
996
539ee71a
AC		 9972003-06-06 Andrew Cagney <cagney@redhat.com>
998
999 Contributed by Red Hat.
1000 * iq2000.cpu: New file. Written by Ben Elliston, Jeff Johnston,
1001 Stan Cox, and Frank Ch. Eigler.
1002 * iq2000.opc: New file. Written by Ben Elliston, Frank
1003 Ch. Eigler, Chris Moller, Jeff Johnston, and Stan Cox.
1004 * iq2000m.cpu: New file. Written by Jeff Johnston.
1005 * iq10.cpu: New file. Written by Jeff Johnston.
1006
36c3ae24
NC		 10072003-06-05 Nick Clifton <nickc@redhat.com>
1008
1009 * frv.cpu (FRintieven): New operand. An even-numbered only
1010 version of the FRinti operand.
1011 (FRintjeven): Likewise for FRintj.
1012 (FRintkeven): Likewise for FRintk.
1013 (mdcutssi, media-dual-word-rotate-r-r, mqsaths,
1014 media-quad-arith-sat-semantics, media-quad-arith-sat,
1015 conditional-media-quad-arith-sat, mdunpackh,
1016 media-quad-multiply-semantics, media-quad-multiply,
1017 conditional-media-quad-multiply, media-quad-complex-i,
1018 media-quad-multiply-acc-semantics, media-quad-multiply-acc,
1019 conditional-media-quad-multiply-acc, munpackh,
1020 media-quad-multiply-cross-acc-semantics, mdpackh,
1021 media-quad-multiply-cross-acc, mbtoh-semantics,
1022 media-quad-cross-multiply-cross-acc-semantics,
1023 media-quad-cross-multiply-cross-acc, mbtoh, mhtob-semantics,
1024 media-quad-cross-multiply-acc-semantics, cmbtoh,
1025 media-quad-cross-multiply-acc, media-quad-complex, mhtob,
1026 media-expand-halfword-to-double-semantics, mexpdhd, cmexpdhd,
1027 cmhtob): Use new operands.
1028 * frv.opc (CGEN_VERBOSE_ASSEMBLER_ERRORS): Define.
0e6b69be 1029 (parse_even_register): New function.
36c3ae24 1030
75798298
NC		 10312003-06-03 Nick Clifton <nickc@redhat.com>
1032
1033 * frv.cpu (media-dual-word-rotate-r-r): Use a signed 6-bit
1034 immediate value not unsigned.
1035
9aab5aa3
AC		 10362003-06-03 Andrew Cagney <cagney@redhat.com>
1037
1038 Contributed by Red Hat.
1039 * frv.cpu: New file. Written by Dave Brolley, Catherine Moore,
1040 and Eric Christopher.
1041 * frv.opc: New file. Written by Catherine Moore, and Dave
1042 Brolley.
1043 * simplify.inc: New file. Written by Doug Evans.
1044
2739f79a
AC		 10452003-05-02 Andrew Cagney <cagney@redhat.com>
1046
1047 * New file.
1048
1049\f
752937aa
NC		 1050Copyright (C) 2003-2012 Free Software Foundation, Inc.
1051
1052Copying and distribution of this file, with or without modification,
1053are permitted in any medium without royalty provided the copyright
1054notice and this notice are preserved.
1055
2739f79a
AC		 1056Local Variables:
1057mode: change-log
1058left-margin: 8
1059fill-column: 74
1060version-control: never
1061End:
GDB Binutils - Deliverables
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