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* m32c.cpu (Bit3-S): New.
[deliverable/binutils-gdb.git] / cpu / m32c.cpu
CommitLineData
49f58d10 1; Renesas M32C CPU description. -*- Scheme -*-
0a665bfd 2;
6772dd07 3; Copyright 2005, 2006 Free Software Foundation, Inc.
0a665bfd
JB		 4;
5; Contributed by Red Hat Inc; developed under contract from Renesas.
6;
7; This file is part of the GNU Binutils.
8;
9; This program is free software; you can redistribute it and/or modify
10; it under the terms of the GNU General Public License as published by
11; the Free Software Foundation; either version 2 of the License, or
12; (at your option) any later version.
13;
14; This program is distributed in the hope that it will be useful,
15; but WITHOUT ANY WARRANTY; without even the implied warranty of
16; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17; GNU General Public License for more details.
18;
19; You should have received a copy of the GNU General Public License
20; along with this program; if not, write to the Free Software
21; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
49f58d10
JB		 22
23(include "simplify.inc")
24
25(define-arch
26 (name m32c)
27 (comment "Renesas M32C")
28 (default-alignment forced)
29 (insn-lsb0? #f)
30 (machs m16c m32c)
31 (isas m16c m32c)
32)
33
34(define-isa
35 (name m16c)
36
37 (default-insn-bitsize 32)
38
39 ; Number of bytes of insn we can initially fetch.
40 (base-insn-bitsize 32)
41
42 ; Used in computing bit numbers.
43 (default-insn-word-bitsize 32)
44
45 (decode-assist (0 1 2 3 4 5 6 7)) ; Initial bitnumbers to decode insns by.
46
47 ; fetches 1 insn at a time.
48 (liw-insns 1)
49
50 ; executes 1 insn at a time.
51 (parallel-insns 1)
52 )
53
54(define-isa
55 (name m32c)
56
57 (default-insn-bitsize 32)
58
59 ; Number of bytes of insn we can initially fetch.
60 (base-insn-bitsize 32)
61
62 ; Used in computing bit numbers.
63 (default-insn-word-bitsize 32)
64
65 (decode-assist (0 1 2 3 4 5 6 7)) ; Initial bitnumbers to decode insns by.
66
67 ; fetches 1 insn at a time.
68 (liw-insns 1)
69
70 ; executes 1 insn at a time.
71 (parallel-insns 1)
72 )
73
74(define-cpu
75 ; cpu names must be distinct from the architecture name and machine names.
76 ; The "b" suffix stands for "base" and is the convention.
77 ; The "f" suffix stands for "family" and is the convention.
78 (name m16cbf)
79 (comment "Renesas M16C base family")
80 (insn-endian big)
81 (data-endian little)
82 (word-bitsize 16)
83)
84
85(define-cpu
86 ; cpu names must be distinct from the architecture name and machine names.
87 ; The "b" suffix stands for "base" and is the convention.
88 ; The "f" suffix stands for "family" and is the convention.
89 (name m32cbf)
90 (comment "Renesas M32C base family")
91 (insn-endian big)
92 (data-endian little)
93 (word-bitsize 16)
94)
95
96(define-mach
97 (name m16c)
98 (comment "Generic M16C cpu")
99 (cpu m32cbf)
100)
101
102(define-mach
103 (name m32c)
104 (comment "Generic M32C cpu")
105 (cpu m32cbf)
106)
107
108; Model descriptions.
109
110(define-model
111 (name m16c)
112 (comment "m16c") (attrs)
113 (mach m16c)
114
115 ; `state' is a list of variables for recording model state
116 ; (state)
117 (unit u-exec "Execution Unit" ()
118 1 1 ; issue done
119 () ; state
120 () ; inputs
121 () ; outputs
122 () ; profile action (default)
123 )
124)
125
126(define-model
127 (name m32c)
128 (comment "m32c") (attrs)
129 (mach m32c)
130
131 ; `state' is a list of variables for recording model state
132 ; (state)
133 (unit u-exec "Execution Unit" ()
134 1 1 ; issue done
135 () ; state
136 () ; inputs
137 () ; outputs
138 () ; profile action (default)
139 )
140)
141
6772dd07
DD		 142(define-attr
143 (type enum)
144 (name RL_TYPE)
145 (values NONE JUMP 1ADDR 2ADDR)
146 (default NONE)
147 )
148
49f58d10
JB		 149; Macros to simplify MACH attribute specification.
150
151(define-pmacro all-isas () (ISA m16c,m32c))
152(define-pmacro m16c-isa () (ISA m16c))
153(define-pmacro m32c-isa () (ISA m32c))
154
155(define-pmacro MACH16 (MACH m16c))
156(define-pmacro MACH32 (MACH m32c))
157
158(define-pmacro (machine size)
159 (MACH (.sym m size c)) (ISA (.sym m size c)))
6772dd07
DD		 160
161(define-pmacro RL_JUMP (RL_TYPE JUMP))
162(define-pmacro RL_1ADDR (RL_TYPE 1ADDR))
163(define-pmacro RL_2ADDR (RL_TYPE 2ADDR))
164
49f58d10
JB		 165\f
166;=============================================================
167; Fields
168;-------------------------------------------------------------
169; Main opcodes
170;
171(dnf f-0-1 "opcode" (all-isas) 0 1)
172(dnf f-0-2 "opcode" (all-isas) 0 2)
173(dnf f-0-3 "opcode" (all-isas) 0 3)
174(dnf f-0-4 "opcode" (all-isas) 0 4)
175(dnf f-1-3 "opcode" (all-isas) 1 3)
176(dnf f-2-2 "opcode" (all-isas) 2 2)
177(dnf f-3-4 "opcode" (all-isas) 3 4)
178(dnf f-3-1 "opcode" (all-isas) 3 1)
179(dnf f-4-1 "opcode" (all-isas) 4 1)
180(dnf f-4-3 "opcode" (all-isas) 4 3)
181(dnf f-4-4 "opcode" (all-isas) 4 4)
182(dnf f-4-6 "opcode" (all-isas) 4 6)
183(dnf f-5-1 "opcode" (all-isas) 5 1)
184(dnf f-5-3 "opcode" (all-isas) 5 3)
185(dnf f-6-2 "opcode" (all-isas) 6 2)
186(dnf f-7-1 "opcode" (all-isas) 7 1)
187(dnf f-8-1 "opcode" (all-isas) 8 1)
188(dnf f-8-2 "opcode" (all-isas) 8 2)
189(dnf f-8-3 "opcode" (all-isas) 8 3)
190(dnf f-8-4 "opcode" (all-isas) 8 4)
191(dnf f-8-8 "opcode" (all-isas) 8 8)
192(dnf f-9-3 "opcode" (all-isas) 9 3)
193(dnf f-9-1 "opcode" (all-isas) 9 1)
194(dnf f-10-1 "opcode" (all-isas) 10 1)
195(dnf f-10-2 "opcode" (all-isas) 10 2)
196(dnf f-10-3 "opcode" (all-isas) 10 3)
197(dnf f-11-1 "opcode" (all-isas) 11 1)
198(dnf f-12-1 "opcode" (all-isas) 12 1)
199(dnf f-12-2 "opcode" (all-isas) 12 2)
200(dnf f-12-3 "opcode" (all-isas) 12 3)
201(dnf f-12-4 "opcode" (all-isas) 12 4)
202(dnf f-12-6 "opcode" (all-isas) 12 6)
203(dnf f-13-3 "opcode" (all-isas) 13 3)
204(dnf f-14-1 "opcode" (all-isas) 14 1)
205(dnf f-14-2 "opcode" (all-isas) 14 2)
206(dnf f-15-1 "opcode" (all-isas) 15 1)
207(dnf f-16-1 "opcode" (all-isas) 16 1)
208(dnf f-16-2 "opcode" (all-isas) 16 2)
209(dnf f-16-4 "opcode" (all-isas) 16 4)
e729279b 210(dnf f-16-8 "opcode" (all-isas) 16 8)
49f58d10
JB		 211(dnf f-18-1 "opcode" (all-isas) 18 1)
212(dnf f-18-2 "opcode" (all-isas) 18 2)
213(dnf f-18-3 "opcode" (all-isas) 18 3)
214(dnf f-20-1 "opcode" (all-isas) 20 1)
215(dnf f-20-3 "opcode" (all-isas) 20 3)
216(dnf f-20-2 "opcode" (all-isas) 20 2)
217(dnf f-20-4 "opcode" (all-isas) 20 4)
218(dnf f-21-3 "opcode" (all-isas) 21 3)
219(dnf f-24-2 "opcode" (all-isas) 24 2)
e729279b
NC		 220(dnf f-24-8 "opcode" (all-isas) 24 8)
221(dnf f-32-16 "opcode" (all-isas) 32 16)
49f58d10
JB		 222
223;-------------------------------------------------------------
224; Registers
225;-------------------------------------------------------------
226
227(dnf f-src16-rn "source Rn for m16c" (MACH16 m16c-isa) 10 2)
228(dnf f-src16-an "source An for m16c" (MACH16 m16c-isa) 11 1)
229
230(dnf f-src32-an-unprefixed "destination An for m32c" (MACH32 m32c-isa) 11 1)
231(dnf f-src32-an-prefixed "destination An for m32c" (MACH32 m32c-isa) 19 1)
232
233; QI mode gr encoding for m32c is different than for m16c. The hardware
234; is indexed using the m16c encoding, so perform the transformation here.
235; register m16c m32c
236; ----------------------
237; r0l 00'b 10'b
238; r0h 01'b 00'b
239; r1l 10'b 11'b
240; r1h 11'b 01'b
241(df f-src32-rn-unprefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 10 2 UINT
242 ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert
243 ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
244)
245; QI mode gr encoding for m32c is different than for m16c. The hardware
246; is indexed using the m16c encoding, so perform the transformation here.
247; register m16c m32c
248; ----------------------
249; r0l 00'b 10'b
250; r0h 01'b 00'b
251; r1l 10'b 11'b
252; r1h 11'b 01'b
253(df f-src32-rn-prefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 18 2 UINT
254 ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert
255 ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
256)
257; HI mode gr encoding for m32c is different than for m16c. The hardware
258; is indexed using the m16c encoding, so perform the transformation here.
259; register m16c m32c
260; ----------------------
261; r0 00'b 10'b
262; r1 01'b 11'b
263; r2 10'b 00'b
264; r3 11'b 01'b
265(df f-src32-rn-unprefixed-HI "source Rn HI for m32c" (MACH32 m32c-isa) 10 2 UINT
266 ((value pc) (mod USI (add value 2) 4)) ; insert
267 ((value pc) (mod USI (add value 2) 4)) ; extract
268)
269
270; HI mode gr encoding for m32c is different than for m16c. The hardware
271; is indexed using the m16c encoding, so perform the transformation here.
272; register m16c m32c
273; ----------------------
274; r0 00'b 10'b
275; r1 01'b 11'b
276; r2 10'b 00'b
277; r3 11'b 01'b
278(df f-src32-rn-prefixed-HI "source Rn HI for m32c" (MACH32 m32c-isa) 18 2 UINT
279 ((value pc) (mod USI (add value 2) 4)) ; insert
280 ((value pc) (mod USI (add value 2) 4)) ; extract
281)
282
283; SI mode gr encoding for m32c is as follows:
284; register encoding index
285; -------------------------
286; r2r0 10'b 0
287; r3r1 11'b 1
288(df f-src32-rn-unprefixed-SI "source Rn SI for m32c" (MACH32 m32c-isa) 10 2 UINT
289 ((value pc) (add USI value 2)) ; insert
290 ((value pc) (sub USI value 2)) ; extract
291)
292(df f-src32-rn-prefixed-SI "source Rn SI for m32c" (MACH32 m32c-isa) 18 2 UINT
293 ((value pc) (add USI value 2)) ; insert
294 ((value pc) (sub USI value 2)) ; extract
295)
296
297(dnf f-dst32-rn-ext-unprefixed "destination Rn for m32c" (MACH32 m32c-isa) 9 1)
298
299(dnf f-dst16-rn "destination Rn for m16c" (MACH16 m16c-isa) 14 2)
300(dnf f-dst16-rn-ext "destination Rn for m16c" (MACH16 m16c-isa) 14 1)
301(dnf f-dst16-rn-QI-s "destination Rn for m16c" (MACH16 m16c-isa) 5 1)
302
303(dnf f-dst16-an "destination An for m16c" (MACH16 m16c-isa) 15 1)
304(dnf f-dst16-an-s "destination An for m16c" (MACH16 m16c-isa) 4 1)
305
306(dnf f-dst32-an-unprefixed "destination An for m32c" (MACH32 m32c-isa) 9 1)
307(dnf f-dst32-an-prefixed "destination An for m32c" (MACH32 m32c-isa) 17 1)
308
309; QI mode gr encoding for m32c is different than for m16c. The hardware
310; is indexed using the m16c encoding, so perform the transformation here.
311; register m16c m32c
312; ----------------------
313; r0l 00'b 10'b
314; r0h 01'b 00'b
315; r1l 10'b 11'b
316; r1h 11'b 01'b
317(df f-dst32-rn-unprefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 8 2 UINT
318 ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert
319 ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
320)
321(df f-dst32-rn-prefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 16 2 UINT
322 ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert
323 ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
324)
325; HI mode gr encoding for m32c is different than for m16c. The hardware
326; is indexed using the m16c encoding, so perform the transformation here.
327; register m16c m32c
328; ----------------------
329; r0 00'b 10'b
330; r1 01'b 11'b
331; r2 10'b 00'b
332; r3 11'b 01'b
333(df f-dst32-rn-unprefixed-HI "destination Rn HI for m32c" (MACH32 m32c-isa) 8 2 UINT
334 ((value pc) (mod USI (add value 2) 4)) ; insert
335 ((value pc) (mod USI (add value 2) 4)) ; extract
336)
337(df f-dst32-rn-prefixed-HI "destination Rn HI for m32c" (MACH32 m32c-isa) 16 2 UINT
338 ((value pc) (mod USI (add value 2) 4)) ; insert
339 ((value pc) (mod USI (add value 2) 4)) ; extract
340)
341; SI mode gr encoding for m32c is as follows:
342; register encoding index
343; -------------------------
344; r2r0 10'b 0
345; r3r1 11'b 1
346(df f-dst32-rn-unprefixed-SI "destination Rn SI for m32c" (MACH32 m32c-isa) 8 2 UINT
347 ((value pc) (add USI value 2)) ; insert
348 ((value pc) (sub USI value 2)) ; extract
349)
350(df f-dst32-rn-prefixed-SI "destination Rn SI for m32c" (MACH32 m32c-isa) 16 2 UINT
351 ((value pc) (add USI value 2)) ; insert
352 ((value pc) (sub USI value 2)) ; extract
353)
354
355(dnf f-dst16-1-S "destination R0[hl] for m16c" (MACH16 m16c-isa) 5 1)
356
357;-------------------------------------------------------------
358; Immediates embedded in the base insn
359;-------------------------------------------------------------
360
361(df f-imm-8-s4 "4 bit signed" (all-isas) 8 4 INT #f #f)
362(df f-imm-12-s4 "4 bit signed" (all-isas) 12 4 INT #f #f)
363(df f-imm-13-u3 "3 bit unsigned" (all-isas) 13 3 UINT #f #f)
364(df f-imm-20-s4 "4 bit signed" (all-isas) 20 4 INT #f #f)
365
366(df f-imm1-S "1 bit immediate for short format binary insns" (MACH32 m32c-isa) 2 1 UINT
367 ((value pc) (sub USI value 1)) ; insert
368 ((value pc) (add USI value 1)) ; extract
369)
370
371(dnmf f-imm3-S "3 bit unsigned for short format insns" (all-isas) UINT
372 (f-2-2 f-7-1)
373 (sequence () ; insert
374 (set (ifield f-7-1) (and (sub (ifield f-imm3-S) 1) 1))
375 (set (ifield f-2-2) (and (srl (sub (ifield f-imm3-S) 1) 1) #x3))
376 )
377 (sequence () ; extract
378 (set (ifield f-imm3-S) (add (or (sll (ifield f-2-2) 1)
379 (ifield f-7-1))
380 1))
381 )
382)
383
384;-------------------------------------------------------------
385; Immediates and displacements beyond the base insn
386;-------------------------------------------------------------
387
388(df f-dsp-8-u6 "6 bit unsigned" (all-isas) 8 6 UINT #f #f)
389(df f-dsp-8-u8 "8 bit unsigned" (all-isas) 8 8 UINT #f #f)
390(df f-dsp-8-s8 "8 bit signed" (all-isas) 8 8 INT #f #f)
391(df f-dsp-10-u6 "6 bit unsigned" (all-isas) 10 6 UINT #f #f)
392(df f-dsp-16-u8 "8 bit unsigned" (all-isas) 16 8 UINT #f #f)
393(df f-dsp-16-s8 "8 bit signed" (all-isas) 16 8 INT #f #f)
394(df f-dsp-24-u8 "8 bit unsigned" (all-isas) 24 8 UINT #f #f)
395(df f-dsp-24-s8 "8 bit signed" (all-isas) 24 8 INT #f #f)
396(df f-dsp-32-u8 "8 bit unsigned" (all-isas) 32 8 UINT #f #f)
397(df f-dsp-32-s8 "8 bit signed" (all-isas) 32 8 INT #f #f)
398(df f-dsp-40-u8 "8 bit unsigned" (all-isas) 40 8 UINT #f #f)
399(df f-dsp-40-s8 "8 bit signed" (all-isas) 40 8 INT #f #f)
400(df f-dsp-48-u8 "8 bit unsigned" (all-isas) 48 8 UINT #f #f)
401(df f-dsp-48-s8 "8 bit signed" (all-isas) 48 8 INT #f #f)
402(df f-dsp-56-u8 "8 bit unsigned" (all-isas) 56 8 UINT #f #f)
403(df f-dsp-56-s8 "8 bit signed" (all-isas) 56 8 INT #f #f)
404(df f-dsp-64-u8 "8 bit unsigned" (all-isas) 64 8 UINT #f #f)
405(df f-dsp-64-s8 "8 bit signed" (all-isas) 64 8 INT #f #f)
406
407; Insn opcode endianness is big, but the immediate fields are stored
408; in little endian. Handle this here at the field level for all immediate
409; fields longer that 1 byte.
410;
411; CGEN can't handle a field which spans a 32 bit word boundary, so
412; handle those as multi ifields.
413;
414; Take care in expressions using 'srl' or 'sll' as part of some larger
415; expression meant to yield sign-extended values. CGEN translates
416; uses of those operators into C expressions whose type is 'unsigned
417; int', which tends to make the whole expression 'unsigned int'.
418; Expressions like (set (ifield foo) X), however, just take X and
419; store it in some member of 'struct cgen_fields', all of whose
420; members are 'long'. On machines where 'long' is larger than
421; 'unsigned int', assigning a "sign-extended" unsigned int to a long
422; just produces a very large positive value. insert_normal will
423; range-check the field's value and produce odd error messages like
424; this:
425;
426; Error: operand out of range (4160684031 not between -2147483648 and 2147483647) `add.l #-265,-270[fb]'
427;
428; Annoyingly, the code will work fine on machines where 'long' and
429; 'unsigned int' are the same size: the assignment will produce a
430; negative number.
431;
432; Just tell yourself over and over: overflow detection is expensive,
433; and you're glad C doesn't do it, because it never happens in real
434; life.
435
436(df f-dsp-8-u16 "16 bit unsigned" (all-isas) 8 16 UINT
437 ((value pc) (or UHI
438 (and (srl value 8) #x00ff)
439 (and (sll value 8) #xff00))) ; insert
440 ((value pc) (or UHI
441 (and UHI (srl UHI value 8) #x00ff)
442 (and UHI (sll UHI value 8) #xff00))) ; extract
443)
444
445(df f-dsp-8-s16 "8 bit signed" (all-isas) 8 16 INT
446 ((value pc) (ext INT
447 (trunc HI
448 (or (and (srl value 8) #x00ff)
449 (and (sll value 8) #xff00))))) ; insert
450 ((value pc) (ext INT
451 (trunc HI
452 (or (and (srl value 8) #x00ff)
453 (and (sll value 8) #xff00))))) ; extract
454)
455
456(df f-dsp-16-u16 "16 bit unsigned" (all-isas) 16 16 UINT
457 ((value pc) (or UHI
458 (and (srl value 8) #x00ff)
459 (and (sll value 8) #xff00))) ; insert
460 ((value pc) (or UHI
461 (and UHI (srl UHI value 8) #x00ff)
462 (and UHI (sll UHI value 8) #xff00))) ; extract
463)
464
465(df f-dsp-16-s16 "16 bit signed" (all-isas) 16 16 INT
466 ((value pc) (ext INT
467 (trunc HI
468 (or (and (srl value 8) #x00ff)
469 (and (sll value 8) #xff00))))) ; insert
470 ((value pc) (ext INT
471 (trunc HI
472 (or (and (srl value 8) #x00ff)
473 (and (sll value 8) #xff00))))) ; extract
474)
475
476(dnmf f-dsp-24-u16 "16 bit unsigned" (all-isas) UINT
477 (f-dsp-24-u8 f-dsp-32-u8)
478 (sequence () ; insert
479 (set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-u16) #xff))
480 (set (ifield f-dsp-32-u8) (and (srl (ifield f-dsp-24-u16) 8) #xff))
481 )
482 (sequence () ; extract
483 (set (ifield f-dsp-24-u16) (or (sll (ifield f-dsp-32-u8) 8)
484 (ifield f-dsp-24-u8)))
485 )
486)
487
488(dnmf f-dsp-24-s16 "16 bit signed" (all-isas) INT
489 (f-dsp-24-u8 f-dsp-32-u8)
490 (sequence () ; insert
491 (set (ifield f-dsp-24-u8)
492 (and (ifield f-dsp-24-s16) #xff))
493 (set (ifield f-dsp-32-u8)
494 (and (srl (ifield f-dsp-24-s16) 8) #xff))
495 )
496 (sequence () ; extract
497 (set (ifield f-dsp-24-s16)
498 (ext INT
499 (trunc HI (or (sll (ifield f-dsp-32-u8) 8)
500 (ifield f-dsp-24-u8)))))
501 )
502)
503
504(df f-dsp-32-u16 "16 bit unsigned" (all-isas) 32 16 UINT
505 ((value pc) (or UHI
506 (and (srl value 8) #x00ff)
507 (and (sll value 8) #xff00))) ; insert
508 ((value pc) (or UHI
509 (and UHI (srl UHI value 8) #x00ff)
510 (and UHI (sll UHI value 8) #xff00))) ; extract
511)
512
513(df f-dsp-32-s16 "16 bit signed" (all-isas) 32 16 INT
514 ((value pc) (ext INT
515 (trunc HI
516 (or (and (srl value 8) #x00ff)
517 (and (sll value 8) #xff00))))) ; insert
518 ((value pc) (ext INT
519 (trunc HI
520 (or (and (srl value 8) #x00ff)
521 (and (sll value 8) #xff00))))) ; extract
522)
523
524(df f-dsp-40-u16 "16 bit unsigned" (all-isas) 40 16 UINT
525 ((value pc) (or UHI
526 (and (srl value 8) #x00ff)
527 (and (sll value 8) #xff00))) ; insert
528 ((value pc) (or UHI
529 (and UHI (srl UHI value 8) #x00ff)
530 (and UHI (sll UHI value 8) #xff00))) ; extract
531)
532
533(df f-dsp-40-s16 "16 bit signed" (all-isas) 40 16 INT
534 ((value pc) (ext INT
535 (trunc HI
536 (or (and (srl value 8) #x00ff)
537 (and (sll value 8) #xff00))))) ; insert
538 ((value pc) (ext INT
539 (trunc HI
540 (or (and (srl value 8) #x00ff)
541 (and (sll value 8) #xff00))))) ; extract
542)
543
544(df f-dsp-48-u16 "16 bit unsigned" (all-isas) 48 16 UINT
545 ((value pc) (or UHI
546 (and (srl value 8) #x00ff)
547 (and (sll value 8) #xff00))) ; insert
548 ((value pc) (or UHI
549 (and UHI (srl UHI value 8) #x00ff)
550 (and UHI (sll UHI value 8) #xff00))) ; extract
551)
552
553(df f-dsp-48-s16 "16 bit signed" (all-isas) 48 16 INT
554 ((value pc) (ext INT
555 (trunc HI
556 (or (and (srl value 8) #x00ff)
557 (and (sll value 8) #xff00))))) ; insert
558 ((value pc) (ext INT
559 (trunc HI
560 (or (and (srl value 8) #x00ff)
561 (and (sll value 8) #xff00))))) ; extract
562)
563
564(df f-dsp-64-u16 "16 bit unsigned" (all-isas) 64 16 UINT
565 ((value pc) (or UHI
566 (and (srl value 8) #x00ff)
567 (and (sll value 8) #xff00))) ; insert
568 ((value pc) (or UHI
569 (and UHI (srl UHI value 8) #x00ff)
570 (and UHI (sll UHI value 8) #xff00))) ; extract
571)
f75eb1c0
DD		 572(df f-dsp-8-s24 "24 bit signed" (all-isas) 8 24 INT
573 ((value pc) (or SI
574 (or (srl value 16) (and value #xff00))
575 (sll (ext INT (trunc QI (and value #xff))) 16)))
576 ((value pc) (or SI
577 (or (srl value 16) (and value #xff00))
578 (sll (ext INT (trunc QI (and value #xff))) 16)))
579 )
580
e729279b
NC		 581(df f-dsp-8-u24 "24 bit unsigned" (all-isas) 8 24 UINT
582 ((value pc) (or SI
583 (or (srl value 16) (and value #xff00))
584 (sll (and value #xff) 16)))
585 ((value pc) (or SI
586 (or (srl value 16) (and value #xff00))
587 (sll (and value #xff) 16)))
588 )
49f58d10
JB		 589
590(dnmf f-dsp-16-u24 "24 bit unsigned" (all-isas) UINT
591 (f-dsp-16-u16 f-dsp-32-u8)
592 (sequence () ; insert
593 (set (ifield f-dsp-16-u16) (and (ifield f-dsp-16-u24) #xffff))
594 (set (ifield f-dsp-32-u8) (and (srl (ifield f-dsp-16-u24) 16) #xff))
595 )
596 (sequence () ; extract
597 (set (ifield f-dsp-16-u24) (or (sll (ifield f-dsp-32-u8) 16)
598 (ifield f-dsp-16-u16)))
599 )
600)
601
602(dnmf f-dsp-24-u24 "24 bit unsigned" (all-isas) UINT
603 (f-dsp-24-u8 f-dsp-32-u16)
604 (sequence () ; insert
605 (set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-u24) #xff))
606 (set (ifield f-dsp-32-u16) (and (srl (ifield f-dsp-24-u24) 8) #xffff))
607 )
608 (sequence () ; extract
609 (set (ifield f-dsp-24-u24) (or (sll (ifield f-dsp-32-u16) 8)
610 (ifield f-dsp-24-u8)))
611 )
612)
613
614(df f-dsp-32-u24 "24 bit unsigned" (all-isas) 32 24 UINT
615 ((value pc) (or USI
616 (or USI
617 (and (srl value 16) #x0000ff)
618 (and value #x00ff00))
619 (and (sll value 16) #xff0000))) ; insert
620 ((value pc) (or USI
621 (or USI
622 (and USI (srl UHI value 16) #x0000ff)
623 (and USI value #x00ff00))
624 (and USI (sll UHI value 16) #xff0000))) ; extract
625)
626
627(df f-dsp-40-u24 "24 bit unsigned" (all-isas) 40 24 UINT
628 ((value pc) (or USI
629 (or USI
630 (and (srl value 16) #x0000ff)
631 (and value #x00ff00))
632 (and (sll value 16) #xff0000))) ; insert
633 ((value pc) (or USI
634 (or USI
635 (and USI (srl UHI value 16) #x0000ff)
636 (and USI value #x00ff00))
637 (and USI (sll UHI value 16) #xff0000))) ; extract
638)
639
640(dnmf f-dsp-40-s32 "32 bit signed" (all-isas) INT
641 (f-dsp-40-u24 f-dsp-64-u8)
642 (sequence () ; insert
643 (set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-40-s32) 24) #xff))
644 (set (ifield f-dsp-40-u24) (and (ifield f-dsp-40-s32) #xffffff))
645 )
646 (sequence () ; extract
647 (set (ifield f-dsp-40-s32) (or (and (ifield f-dsp-40-u24) #xffffff)
648 (and (sll (ifield f-dsp-64-u8) 24) #xff000000)))
649 )
650)
651
652(dnmf f-dsp-48-u24 "24 bit unsigned" (all-isas) UINT
653 (f-dsp-48-u16 f-dsp-64-u8)
654 (sequence () ; insert
655 (set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-48-u24) 16) #xff))
656 (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u24) #xffff))
657 )
658 (sequence () ; extract
659 (set (ifield f-dsp-48-u24) (or (and (ifield f-dsp-48-u16) #xffff)
660 (and (sll (ifield f-dsp-64-u8) 16) #xff0000)))
661 )
662)
663
664(dnmf f-dsp-16-s32 "32 bit signed" (all-isas) INT
665 (f-dsp-16-u16 f-dsp-32-u16)
666 (sequence () ; insert
667 (set (ifield f-dsp-32-u16) (and (srl (ifield f-dsp-16-s32) 16) #xffff))
668 (set (ifield f-dsp-16-u16) (and (ifield f-dsp-16-s32) #xffff))
669 )
670 (sequence () ; extract
671 (set (ifield f-dsp-16-s32) (or (and (ifield f-dsp-16-u16) #xffff)
672 (and (sll (ifield f-dsp-32-u16) 16) #xffff0000)))
673 )
674)
675
676(dnmf f-dsp-24-s32 "32 bit signed" (all-isas) INT
677 (f-dsp-24-u8 f-dsp-32-u24)
678 (sequence () ; insert
679 (set (ifield f-dsp-32-u24) (and (srl (ifield f-dsp-24-s32) 8) #xffffff))
680 (set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-s32) #xff))
681 )
682 (sequence () ; extract
683 (set (ifield f-dsp-24-s32) (or (and (ifield f-dsp-24-u8) #xff)
684 (and (sll (ifield f-dsp-32-u24) 8) #xffffff00)))
685 )
686)
687
688(df f-dsp-32-s32 "32 bit signed" (all-isas) 32 32 INT
689 ((value pc)
690
691 ;; insert
692 (ext INT
693 (or SI
694 (or SI
695 (and (srl value 24) #x000000ff)
696 (and (srl value 8) #x0000ff00))
697 (or SI
698 (and (sll value 8) #x00ff0000)
699 (and (sll value 24) #xff000000)))))
700
701 ;; extract
702 ((value pc)
703 (ext INT
704 (or SI
705 (or SI
706 (and (srl value 24) #x000000ff)
707 (and (srl value 8) #x0000ff00))
708 (or SI
709 (and (sll value 8) #x00ff0000)
710 (and (sll value 24) #xff000000)))))
711)
712
713(dnmf f-dsp-48-u32 "32 bit unsigned" (all-isas) UINT
714 (f-dsp-48-u16 f-dsp-64-u16)
715 (sequence () ; insert
716 (set (ifield f-dsp-64-u16) (and (srl (ifield f-dsp-48-u32) 16) #xffff))
717 (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u32) #xffff))
718 )
719 (sequence () ; extract
720 (set (ifield f-dsp-48-u32) (or (and (ifield f-dsp-48-u16) #xffff)
721 (and (sll (ifield f-dsp-64-u16) 16) #xffff0000)))
722 )
723)
724
725(dnmf f-dsp-48-s32 "32 bit signed" (all-isas) INT
726 (f-dsp-48-u16 f-dsp-64-u16)
727 (sequence () ; insert
728 (set (ifield f-dsp-64-u16) (and (srl (ifield f-dsp-48-s32) 16) #xffff))
729 (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-s32) #xffff))
730 )
731 (sequence () ; extract
732 (set (ifield f-dsp-48-s32) (or (and (ifield f-dsp-48-u16) #xffff)
733 (and (sll (ifield f-dsp-64-u16) 16) #xffff0000)))
734 )
735)
736
737(dnmf f-dsp-56-s16 "16 bit signed" (all-isas) INT
738 (f-dsp-56-u8 f-dsp-64-u8)
739 (sequence () ; insert
740 (set (ifield f-dsp-56-u8)
741 (and (ifield f-dsp-56-s16) #xff))
742 (set (ifield f-dsp-64-u8)
743 (and (srl (ifield f-dsp-56-s16) 8) #xff))
744 )
745 (sequence () ; extract
746 (set (ifield f-dsp-56-s16)
747 (ext INT
748 (trunc HI (or (sll (ifield f-dsp-64-u8) 8)
749 (ifield f-dsp-56-u8)))))
750 )
751)
752
753(df f-dsp-64-s16 " 16 bit signed" (all-isas) 64 16 INT
754 ((value pc) (ext INT
755 (trunc HI
756 (or (and (srl value 8) #x00ff)
757 (and (sll value 8) #xff00))))) ; insert
758 ((value pc) (ext INT
759 (trunc HI
760 (or (and (srl value 8) #x00ff)
761 (and (sll value 8) #xff00))))) ; extract
762)
763
764;-------------------------------------------------------------
765; Bit indices
766;-------------------------------------------------------------
767
768(dnf f-bitno16-S "bit index for m16c" (all-isas) 5 3)
769(dnf f-bitno32-prefixed "bit index for m32c" (all-isas) 21 3)
770(dnf f-bitno32-unprefixed "bit index for m32c" (all-isas) 13 3)
771
772(dnmf f-bitbase16-u11-S "unsigned bit,base:11" (all-isas) UINT
773 (f-bitno16-S f-dsp-8-u8)
774 (sequence () ; insert
775 (set (ifield f-bitno16-S) (and f-bitbase16-u11-S #x7))
776 (set (ifield f-dsp-8-u8) (and (srl (ifield f-bitbase16-u11-S) 3) #xff))
777 )
778 (sequence () ; extract
779 (set (ifield f-bitbase16-u11-S) (or (sll (ifield f-dsp-8-u8) 3)
780 (ifield f-bitno16-S)))
781 )
782)
783
784(dnmf f-bitbase32-16-u11-unprefixed "unsigned bit,base:11" (all-isas) UINT
785 (f-bitno32-unprefixed f-dsp-16-u8)
786 (sequence () ; insert
787 (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u11-unprefixed #x7))
788 (set (ifield f-dsp-16-u8) (and (srl (ifield f-bitbase32-16-u11-unprefixed) 3) #xff))
789 )
790 (sequence () ; extract
791 (set (ifield f-bitbase32-16-u11-unprefixed) (or (sll (ifield f-dsp-16-u8) 3)
792 (ifield f-bitno32-unprefixed)))
793 )
794)
795(dnmf f-bitbase32-16-s11-unprefixed "signed bit,base:11" (all-isas) INT
796 (f-bitno32-unprefixed f-dsp-16-s8)
797 (sequence () ; insert
798 (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-s11-unprefixed #x7))
799 (set (ifield f-dsp-16-s8) (sra INT (ifield f-bitbase32-16-s11-unprefixed) 3))
800 )
801 (sequence () ; extract
802 (set (ifield f-bitbase32-16-s11-unprefixed) (or (sll (ifield f-dsp-16-s8) 3)
803 (ifield f-bitno32-unprefixed)))
804 )
805)
806(dnmf f-bitbase32-16-u19-unprefixed "unsigned bit,base:19" (all-isas) UINT
807 (f-bitno32-unprefixed f-dsp-16-u16)
808 (sequence () ; insert
809 (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u19-unprefixed #x7))
810 (set (ifield f-dsp-16-u16) (and (srl (ifield f-bitbase32-16-u19-unprefixed) 3) #xffff))
811 )
812 (sequence () ; extract
813 (set (ifield f-bitbase32-16-u19-unprefixed) (or (sll (ifield f-dsp-16-u16) 3)
814 (ifield f-bitno32-unprefixed)))
815 )
816)
817(dnmf f-bitbase32-16-s19-unprefixed "signed bit,base:11" (all-isas) INT
818 (f-bitno32-unprefixed f-dsp-16-s16)
819 (sequence () ; insert
820 (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-s19-unprefixed #x7))
821 (set (ifield f-dsp-16-s16) (sra INT (ifield f-bitbase32-16-s19-unprefixed) 3))
822 )
823 (sequence () ; extract
824 (set (ifield f-bitbase32-16-s19-unprefixed) (or (sll (ifield f-dsp-16-s16) 3)
825 (ifield f-bitno32-unprefixed)))
826 )
827)
828; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-(
829(dnmf f-bitbase32-16-u27-unprefixed "unsigned bit,base:27" (all-isas) UINT
830 (f-bitno32-unprefixed f-dsp-16-u16 f-dsp-32-u8)
831 (sequence () ; insert
832 (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u27-unprefixed #x7))
833 (set (ifield f-dsp-16-u16) (and (srl (ifield f-bitbase32-16-u27-unprefixed) 3) #xffff))
834 (set (ifield f-dsp-32-u8) (and (srl (ifield f-bitbase32-16-u27-unprefixed) 19) #xff))
835 )
836 (sequence () ; extract
837 (set (ifield f-bitbase32-16-u27-unprefixed) (or (sll (ifield f-dsp-16-u16) 3)
838 (or (sll (ifield f-dsp-32-u8) 19)
839 (ifield f-bitno32-unprefixed))))
840 )
841)
842(dnmf f-bitbase32-24-u11-prefixed "unsigned bit,base:11" (all-isas) UINT
843 (f-bitno32-prefixed f-dsp-24-u8)
844 (sequence () ; insert
845 (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u11-prefixed #x7))
846 (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u11-prefixed) 3) #xff))
847 )
848 (sequence () ; extract
849 (set (ifield f-bitbase32-24-u11-prefixed) (or (sll (ifield f-dsp-24-u8) 3)
850 (ifield f-bitno32-prefixed)))
851 )
852)
853(dnmf f-bitbase32-24-s11-prefixed "signed bit,base:11" (all-isas) INT
854 (f-bitno32-prefixed f-dsp-24-s8)
855 (sequence () ; insert
856 (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-s11-prefixed #x7))
857 (set (ifield f-dsp-24-s8) (sra INT (ifield f-bitbase32-24-s11-prefixed) 3))
858 )
859 (sequence () ; extract
860 (set (ifield f-bitbase32-24-s11-prefixed) (or (sll (ifield f-dsp-24-s8) 3)
861 (ifield f-bitno32-prefixed)))
862 )
863)
864; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-(
865(dnmf f-bitbase32-24-u19-prefixed "unsigned bit,base:19" (all-isas) UINT
866 (f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-u8)
867 (sequence () ; insert
868 (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u19-prefixed #x7))
869 (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u19-prefixed) 3) #xff))
870 (set (ifield f-dsp-32-u8) (and (srl (ifield f-bitbase32-24-u19-prefixed) 11) #xff))
871 )
872 (sequence () ; extract
873 (set (ifield f-bitbase32-24-u19-prefixed) (or (sll (ifield f-dsp-24-u8) 3)
874 (or (sll (ifield f-dsp-32-u8) 11)
875 (ifield f-bitno32-prefixed))))
876 )
877)
878; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-(
879(dnmf f-bitbase32-24-s19-prefixed "signed bit,base:11" (all-isas) INT
880 (f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-s8)
881 (sequence () ; insert
882 (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-s19-prefixed #x7))
883 (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-s19-prefixed) 3) #xff))
884 (set (ifield f-dsp-32-s8) (sra INT (ifield f-bitbase32-24-s19-prefixed) 11))
885 )
886 (sequence () ; extract
887 (set (ifield f-bitbase32-24-s19-prefixed) (or (sll (ifield f-dsp-24-u8) 3)
888 (or (sll (ifield f-dsp-32-s8) 11)
889 (ifield f-bitno32-prefixed))))
890 )
891)
892; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-(
893(dnmf f-bitbase32-24-u27-prefixed "unsigned bit,base:27" (all-isas) UINT
894 (f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-u16)
895 (sequence () ; insert
896 (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u27-prefixed #x7))
897 (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u27-prefixed) 3) #xff))
898 (set (ifield f-dsp-32-u16) (and (srl (ifield f-bitbase32-24-u27-prefixed) 11) #xffff))
899 )
900 (sequence () ; extract
901 (set (ifield f-bitbase32-24-u27-prefixed) (or (sll (ifield f-dsp-24-u8) 3)
902 (or (sll (ifield f-dsp-32-u16) 11)
903 (ifield f-bitno32-prefixed))))
904 )
905)
906
907;-------------------------------------------------------------
908; Labels
909;-------------------------------------------------------------
910
e729279b 911(df f-lab-5-3 "3 bit pc relative unsigned offset" (PCREL-ADDR all-isas) 5 3 UINT
49f58d10
JB		 912 ((value pc) (sub SI value (add SI pc 2))) ; insert
913 ((value pc) (add SI value (add SI pc 2))) ; extract
914)
915(dnmf f-lab32-jmp-s "unsigned 3 bit pc relative offset" (PCREL-ADDR all-isas) UINT
916 (f-2-2 f-7-1)
e729279b
NC		 917 (sequence ((SI val)) ; insert
918 (set val (sub (sub (ifield f-lab32-jmp-s) pc) 2))
919 (set (ifield f-7-1) (and val #x1))
920 (set (ifield f-2-2) (srl val 1))
49f58d10
JB		 921 )
922 (sequence () ; extract
923 (set (ifield f-lab32-jmp-s) (add pc (add (or (sll (ifield f-2-2) 1)
924 (ifield f-7-1))
925 2)))
926 )
927)
928(df f-lab-8-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 8 8 INT
929 ((value pc) (sub SI value (add SI pc 1))) ; insert
930 ((value pc) (add SI value (add SI pc 1))) ; extract
931)
932(df f-lab-8-16 "16 bit pc relative signed offset" (PCREL-ADDR SIGN-OPT all-isas) 8 16 UINT
933 ((value pc) (or SI (sll (and (sub value (add pc 1)) #xff) 8)
934 (srl (and (sub value (add pc 1)) #xffff) 8)))
935 ((value pc) (add SI (or (srl (and value #xffff) 8)
936 (sra (sll (and value #xff) 24) 16)) (add pc 1)))
937 )
938(df f-lab-8-24 "24 bit absolute" (all-isas ABS-ADDR) 8 24 UINT
939 ((value pc) (or SI
940 (or (srl value 16) (and value #xff00))
941 (sll (and value #xff) 16)))
942 ((value pc) (or SI
943 (or (srl value 16) (and value #xff00))
944 (sll (and value #xff) 16)))
945 )
946(df f-lab-16-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 16 8 INT
947 ((value pc) (sub SI value (add SI pc 2))) ; insert
948 ((value pc) (add SI value (add SI pc 2))) ; extract
949)
950(df f-lab-24-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 24 8 INT
951 ((value pc) (sub SI value (add SI pc 2))) ; insert
952 ((value pc) (add SI value (add SI pc 2))) ; extract
953)
954(df f-lab-32-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 32 8 INT
955 ((value pc) (sub SI value (add SI pc 2))) ; insert
956 ((value pc) (add SI value (add SI pc 2))) ; extract
957)
958(df f-lab-40-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 40 8 INT
959 ((value pc) (sub SI value (add SI pc 2))) ; insert
960 ((value pc) (add SI value (add SI pc 2))) ; extract
961)
962
963;-------------------------------------------------------------
964; Condition codes
965;-------------------------------------------------------------
966
967(dnf f-cond16 "condition code" (all-isas) 12 4)
968(dnf f-cond16j-5 "condition code" (all-isas) 5 3)
969
970(dnmf f-cond32 "condition code" (all-isas) UINT
971 (f-9-1 f-13-3)
972 (sequence () ; insert
973 (set (ifield f-9-1) (and (srl (ifield f-cond32) 3) 1))
974 (set (ifield f-13-3) (and (ifield f-cond32) #x7))
975 )
976 (sequence () ; extract
977 (set (ifield f-cond32) (or (sll (ifield f-9-1) 3)
978 (ifield f-13-3)))
979 )
980)
981
982(dnmf f-cond32j "condition code" (all-isas) UINT
983 (f-1-3 f-7-1)
984 (sequence () ; insert
985 (set (ifield f-1-3) (and (srl (ifield f-cond32j) 1) #x7))
986 (set (ifield f-7-1) (and (ifield f-cond32j) #x1))
987 )
988 (sequence () ; extract
989 (set (ifield f-cond32j) (or (sll (ifield f-1-3) 1)
990 (ifield f-7-1)))
991 )
992)
993\f
994;=============================================================
995; Hardware
996;
997(dnh h-pc "program counter" (PC all-isas) (pc USI) () () ())
998
999;-------------------------------------------------------------
1000; General registers
1001; The actual registers are 16 bits
1002;-------------------------------------------------------------
1003
1004(define-hardware
1005 (name h-gr)
1006 (comment "general 16 bit registers")
1007 (attrs all-isas CACHE-ADDR)
1008 (type register HI (4))
1009 (indices keyword "" (("r0" 0) ("r1" 1) ("r2" 2) ("r3" 3))))
1010
1011; Define different views of the grs as VIRTUAL with getter/setter specs
1012;
1013(define-hardware
1014 (name h-gr-QI)
1015 (comment "general 8 bit registers")
1016 (attrs all-isas VIRTUAL)
1017 (type register QI (4))
1018 (indices keyword "" (("r0l" 0) ("r0h" 1) ("r1l" 2) ("r1h" 3)))
1019 (get (index) (and (if SI (mod index 2)
1020 (srl (reg h-gr (div index 2)) 8)
1021 (reg h-gr (div index 2)))
1022 #xff))
1023 (set (index newval) (set (reg h-gr (div index 2))
1024 (if SI (mod index 2)
1025 (or (and (reg h-gr (div index 2)) #xff)
1026 (sll (and newval #xff) 8))
1027 (or (and (reg h-gr (div index 2)) #xff00)
1028 (and newval #xff))))))
1029
1030(define-hardware
1031 (name h-gr-HI)
1032 (comment "general 16 bit registers")
1033 (attrs all-isas VIRTUAL)
1034 (type register HI (4))
1035 (indices keyword "" (("r0" 0) ("r1" 1) ("r2" 2) ("r3" 3)))
1036 (get (index) (reg h-gr index))
1037 (set (index newval) (set (reg h-gr index) newval)))
1038
1039(define-hardware
1040 (name h-gr-SI)
1041 (comment "general 32 bit registers")
1042 (attrs all-isas VIRTUAL)
1043 (type register SI (2))
1044 (indices keyword "" (("r2r0" 0) ("r3r1" 1)))
1045 (get (index) (or SI
1046 (and (reg h-gr index) #xffff)
1047 (and (sll (reg h-gr (add index 2)) 16) #xffff0000)))
1048 (set (index newval) (sequence ()
1049 (set (reg h-gr index) (and newval #xffff))
1050 (set (reg h-gr (add index 2)) (srl newval 16)))))
1051
1052(define-hardware
1053 (name h-gr-ext-QI)
1054 (comment "general 16 bit registers")
1055 (attrs all-isas VIRTUAL)
1056 (type register HI (2))
1057 (indices keyword "" (("r0l" 0) ("r1l" 1)))
1058 (get (index) (reg h-gr-QI (mul index 2)))
1059 (set (index newval) (set (reg h-gr (mul index 2)) newval)))
1060
1061(define-hardware
1062 (name h-gr-ext-HI)
1063 (comment "general 16 bit registers")
1064 (attrs all-isas VIRTUAL)
1065 (type register SI (2))
1066 (indices keyword "" (("r0" 0) ("r1" 1)))
1067 (get (index) (reg h-gr (mul index 2)))
1068 (set (index newval) (set (reg h-gr-SI index) newval)))
1069
1070(define-hardware
1071 (name h-r0l)
1072 (comment "r0l register")
1073 (attrs all-isas VIRTUAL)
1074 (type register QI)
1075 (indices keyword "" (("r0l" 0)))
1076 (get () (reg h-gr-QI 0))
1077 (set (newval) (set (reg h-gr-QI 0) newval)))
1078
1079(define-hardware
1080 (name h-r0h)
1081 (comment "r0h register")
1082 (attrs all-isas VIRTUAL)
1083 (type register QI)
1084 (indices keyword "" (("r0h" 0)))
1085 (get () (reg h-gr-QI 1))
1086 (set (newval) (set (reg h-gr-QI 1) newval)))
1087
1088(define-hardware
1089 (name h-r1l)
1090 (comment "r1l register")
1091 (attrs all-isas VIRTUAL)
1092 (type register QI)
1093 (indices keyword "" (("r1l" 0)))
1094 (get () (reg h-gr-QI 2))
1095 (set (newval) (set (reg h-gr-QI 2) newval)))
1096
1097(define-hardware
1098 (name h-r1h)
1099 (comment "r1h register")
1100 (attrs all-isas VIRTUAL)
1101 (type register QI)
1102 (indices keyword "" (("r1h" 0)))
1103 (get () (reg h-gr-QI 3))
1104 (set (newval) (set (reg h-gr-QI 3) newval)))
1105
1106(define-hardware
1107 (name h-r0)
1108 (comment "r0 register")
1109 (attrs all-isas VIRTUAL)
1110 (type register HI)
1111 (indices keyword "" (("r0" 0)))
1112 (get () (reg h-gr 0))
1113 (set (newval) (set (reg h-gr 0) newval)))
1114
1115(define-hardware
1116 (name h-r1)
1117 (comment "r1 register")
1118 (attrs all-isas VIRTUAL)
1119 (type register HI)
1120 (indices keyword "" (("r1" 0)))
1121 (get () (reg h-gr 1))
1122 (set (newval) (set (reg h-gr 1) newval)))
1123
1124(define-hardware
1125 (name h-r2)
1126 (comment "r2 register")
1127 (attrs all-isas VIRTUAL)
1128 (type register HI)
1129 (indices keyword "" (("r2" 0)))
1130 (get () (reg h-gr 2))
1131 (set (newval) (set (reg h-gr 2) newval)))
1132
1133(define-hardware
1134 (name h-r3)
1135 (comment "r3 register")
1136 (attrs all-isas VIRTUAL)
1137 (type register HI)
1138 (indices keyword "" (("r3" 0)))
1139 (get () (reg h-gr 3))
1140 (set (newval) (set (reg h-gr 3) newval)))
1141
1142(define-hardware
1143 (name h-r0l-r0h)
1144 (comment "r0l or r0h")
1145 (attrs all-isas VIRTUAL)
1146 (type register QI (2))
1147 (indices keyword "" (("r0l" 0) ("r0h" 1)))
1148 (get (index) (reg h-gr-QI index))
1149 (set (index newval) (set (reg h-gr-QI index) newval)))
1150
1151(define-hardware
1152 (name h-r2r0)
1153 (comment "r2r0 register")
1154 (attrs all-isas VIRTUAL)
1155 (type register SI)
1156 (indices keyword "" (("r2r0" 0)))
1157 (get () (or (sll (reg h-gr 2) 16) (reg h-gr 0)))
1158 (set (newval)
1159 (sequence ()
1160 (set (reg h-gr 0) newval)
1161 (set (reg h-gr 2) (sra newval 16)))))
1162
1163(define-hardware
1164 (name h-r3r1)
1165 (comment "r3r1 register")
1166 (attrs all-isas VIRTUAL)
1167 (type register SI)
1168 (indices keyword "" (("r3r1" 0)))
1169 (get () (or (sll (reg h-gr 3) 16) (reg h-gr 1)))
1170 (set (newval)
1171 (sequence ()
1172 (set (reg h-gr 1) newval)
1173 (set (reg h-gr 3) (sra newval 16)))))
1174
1175(define-hardware
1176 (name h-r1r2r0)
1177 (comment "r1r2r0 register")
1178 (attrs all-isas VIRTUAL)
1179 (type register DI)
1180 (indices keyword "" (("r1r2r0" 0)))
1181 (get () (or DI (sll DI (reg h-gr 1) 32) (or (sll (reg h-gr 2) 16) (reg h-gr 0))))
1182 (set (newval)
1183 (sequence ()
1184 (set (reg h-gr 0) newval)
1185 (set (reg h-gr 2) (sra newval 16))
1186 (set (reg h-gr 1) (sra newval 32)))))
1187
1188;-------------------------------------------------------------
1189; Address registers
1190;-------------------------------------------------------------
1191
1192(define-hardware
1193 (name h-ar)
1194 (comment "address registers")
1195 (attrs all-isas)
1196 (type register USI (2))
1197 (indices keyword "" (("a0" 0) ("a1" 1)))
1198 (get (index) (c-call USI "h_ar_get_handler" index))
1199 (set (index newval) (c-call VOID "h_ar_set_handler" index newval)))
1200
1201; Define different views of the ars as VIRTUAL with getter/setter specs
1202(define-hardware
1203 (name h-ar-QI)
1204 (comment "8 bit view of address register")
1205 (attrs all-isas VIRTUAL)
1206 (type register QI (2))
1207 (indices keyword "" (("a0" 0) ("a1" 1)))
1208 (get (index) (reg h-ar index))
1209 (set (index newval) (set (reg h-ar index) newval)))
1210
1211(define-hardware
1212 (name h-ar-HI)
1213 (comment "16 bit view of address register")
1214 (attrs all-isas VIRTUAL)
1215 (type register HI (2))
1216 (indices keyword "" (("a0" 0) ("a1" 1)))
1217 (get (index) (reg h-ar index))
1218 (set (index newval) (set (reg h-ar index) newval)))
1219
1220(define-hardware
1221 (name h-ar-SI)
1222 (comment "32 bit view of address register")
1223 (attrs all-isas VIRTUAL)
1224 (type register SI)
1225 (indices keyword "" (("a1a0" 0)))
1226 (get () (or SI (sll SI (ext SI (reg h-ar 1)) 16) (ext SI (reg h-ar 0))))
1227 (set (newval) (sequence ()
1228 (set (reg h-ar 0) (and newval #xffff))
1229 (set (reg h-ar 1) (and (srl newval 16) #xffff)))))
1230
1231(define-hardware
1232 (name h-a0)
1233 (comment "16 bit view of address register")
1234 (attrs all-isas VIRTUAL)
1235 (type register HI)
1236 (indices keyword "" (("a0" 0)))
1237 (get () (reg h-ar 0))
1238 (set (newval) (set (reg h-ar 0) newval)))
1239
1240(define-hardware
1241 (name h-a1)
1242 (comment "16 bit view of address register")
1243 (attrs all-isas VIRTUAL)
1244 (type register HI)
1245 (indices keyword "" (("a1" 1)))
1246 (get () (reg h-ar 1))
1247 (set (newval) (set (reg h-ar 1) newval)))
1248
1249; SB Register
1250(define-hardware
1251 (name h-sb)
1252 (comment "SB register")
1253 (attrs all-isas)
1254 (type register USI)
1255 (get () (c-call USI "h_sb_get_handler"))
1256 (set (newval) (c-call VOID "h_sb_set_handler" newval))
1257)
1258
1259; FB Register
1260(define-hardware
1261 (name h-fb)
1262 (comment "FB register")
1263 (attrs all-isas)
1264 (type register USI)
1265 (get () (c-call USI "h_fb_get_handler"))
1266 (set (newval) (c-call VOID "h_fb_set_handler" newval))
1267)
1268
1269; SP Register
1270(define-hardware
1271 (name h-sp)
1272 (comment "SP register")
1273 (attrs all-isas)
1274 (type register USI)
1275 (get () (c-call USI "h_sp_get_handler"))
1276 (set (newval) (c-call VOID "h_sp_set_handler" newval))
1277)
1278
1279;-------------------------------------------------------------
1280; condition-code bits
1281;-------------------------------------------------------------
1282
1283(define-hardware
1284 (name h-sbit)
1285 (comment "sign bit")
1286 (attrs all-isas)
1287 (type register BI)
1288)
1289
1290(define-hardware
1291 (name h-zbit)
1292 (comment "zero bit")
1293 (attrs all-isas)
1294 (type register BI)
1295)
1296
1297(define-hardware
1298 (name h-obit)
1299 (comment "overflow bit")
1300 (attrs all-isas)
1301 (type register BI)
1302)
1303
1304(define-hardware
1305 (name h-cbit)
1306 (comment "carry bit")
1307 (attrs all-isas)
1308 (type register BI)
1309)
1310
1311(define-hardware
1312 (name h-ubit)
1313 (comment "stack pointer select bit")
1314 (attrs all-isas)
1315 (type register BI)
1316)
1317
1318(define-hardware
1319 (name h-ibit)
1320 (comment "interrupt enable bit")
1321 (attrs all-isas)
1322 (type register BI)
1323)
1324
1325(define-hardware
1326 (name h-bbit)
1327 (comment "register bank select bit")
1328 (attrs all-isas)
1329 (type register BI)
1330)
1331
1332(define-hardware
1333 (name h-dbit)
1334 (comment "debug bit")
1335 (attrs all-isas)
1336 (type register BI)
1337)
1338
1339(define-hardware
1340 (name h-dct0)
1341 (comment "dma transfer count 000")
1342 (attrs all-isas)
1343 (type register UHI)
1344)
1345(define-hardware
1346 (name h-dct1)
1347 (comment "dma transfer count 001")
1348 (attrs all-isas)
1349 (type register UHI)
1350)
1351(define-hardware
1352 (name h-svf)
1353 (comment "save flag 011")
1354 (attrs all-isas)
1355 (type register UHI)
1356)
1357(define-hardware
1358 (name h-drc0)
1359 (comment "dma transfer count reload 100")
1360 (attrs all-isas)
1361 (type register UHI)
1362)
1363(define-hardware
1364 (name h-drc1)
1365 (comment "dma transfer count reload 101")
1366 (attrs all-isas)
1367 (type register UHI)
1368)
1369(define-hardware
1370 (name h-dmd0)
1371 (comment "dma mode 110")
1372 (attrs all-isas)
1373 (type register UQI)
1374)
1375(define-hardware
1376 (name h-dmd1)
1377 (comment "dma mode 111")
1378 (attrs all-isas)
1379 (type register UQI)
1380)
1381(define-hardware
1382 (name h-intb)
1383 (comment "interrupt table 000")
1384 (attrs all-isas)
1385 (type register USI)
1386)
1387(define-hardware
1388 (name h-svp)
1389 (comment "save pc 100")
1390 (attrs all-isas)
1391 (type register UHI)
1392)
1393(define-hardware
1394 (name h-vct)
1395 (comment "vector 101")
1396 (attrs all-isas)
1397 (type register USI)
1398)
1399(define-hardware
1400 (name h-isp)
1401 (comment "interrupt stack ptr 111")
1402 (attrs all-isas)
1403 (type register USI)
1404)
1405(define-hardware
1406 (name h-dma0)
1407 (comment "dma mem addr 010")
1408 (attrs all-isas)
1409 (type register USI)
1410)
1411(define-hardware
1412 (name h-dma1)
1413 (comment "dma mem addr 011")
1414 (attrs all-isas)
1415 (type register USI)
1416)
1417(define-hardware
1418 (name h-dra0)
1419 (comment "dma mem addr reload 100")
1420 (attrs all-isas)
1421 (type register USI)
1422)
1423(define-hardware
1424 (name h-dra1)
1425 (comment "dma mem addr reload 101")
1426 (attrs all-isas)
1427 (type register USI)
1428)
1429(define-hardware
1430 (name h-dsa0)
1431 (comment "dma sfr addr 110")
1432 (attrs all-isas)
1433 (type register USI)
1434)
1435(define-hardware
1436 (name h-dsa1)
1437 (comment "dma sfr addr 111")
1438 (attrs all-isas)
1439 (type register USI)
1440)
1441
1442;-------------------------------------------------------------
1443; Condition code operand hardware
1444;-------------------------------------------------------------
1445
1446(define-hardware
1447 (name h-cond16)
1448 (comment "condition code hardware for m16c")
1449 (attrs m16c-isa MACH16)
1450 (type immediate UQI)
1451 (values keyword ""
1452 (("geu" #x00) ("c" #x00)
1453 ("gtu" #x01)
1454 ("eq" #x02) ("z" #x02)
1455 ("n" #x03)
1456 ("le" #x04)
1457 ("o" #x05)
1458 ("ge" #x06)
1459 ("ltu" #xf8) ("nc" #xf8)
1460 ("leu" #xf9)
1461 ("ne" #xfa) ("nz" #xfa)
1462 ("pz" #xfb)
1463 ("gt" #xfc)
1464 ("no" #xfd)
1465 ("lt" #xfe)
1466 )
1467 )
1468)
1469(define-hardware
1470 (name h-cond16c)
1471 (comment "condition code hardware for m16c")
1472 (attrs m16c-isa MACH16)
1473 (type immediate UQI)
1474 (values keyword ""
1475 (("geu" #x00) ("c" #x00)
1476 ("gtu" #x01)
1477 ("eq" #x02) ("z" #x02)
1478 ("n" #x03)
1479 ("ltu" #x04) ("nc" #x04)
1480 ("leu" #x05)
1481 ("ne" #x06) ("nz" #x06)
1482 ("pz" #x07)
1483 ("le" #x08)
1484 ("o" #x09)
1485 ("ge" #x0a)
1486 ("gt" #x0c)
1487 ("no" #x0d)
1488 ("lt" #x0e)
1489 )
1490 )
1491)
1492(define-hardware
1493 (name h-cond16j)
1494 (comment "condition code hardware for m16c")
1495 (attrs m16c-isa MACH16)
1496 (type immediate UQI)
1497 (values keyword ""
1498 (("le" #x08)
1499 ("o" #x09)
1500 ("ge" #x0a)
1501 ("gt" #x0c)
1502 ("no" #x0d)
1503 ("lt" #x0e)
1504 )
1505 )
1506)
1507(define-hardware
1508 (name h-cond16j-5)
1509 (comment "condition code hardware for m16c")
1510 (attrs m16c-isa MACH16)
1511 (type immediate UQI)
1512 (values keyword ""
1513 (("geu" #x00) ("c" #x00)
1514 ("gtu" #x01)
1515 ("eq" #x02) ("z" #x02)
1516 ("n" #x03)
1517 ("ltu" #x04) ("nc" #x04)
1518 ("leu" #x05)
1519 ("ne" #x06) ("nz" #x06)
1520 ("pz" #x07)
1521 )
1522 )
1523)
1524
1525(define-hardware
1526 (name h-cond32)
1527 (comment "condition code hardware for m32c")
1528 (attrs m32c-isa MACH32)
1529 (type immediate UQI)
1530 (values keyword ""
1531 (("ltu" #x00) ("nc" #x00)
1532 ("leu" #x01)
1533 ("ne" #x02) ("nz" #x02)
1534 ("pz" #x03)
1535 ("no" #x04)
1536 ("gt" #x05)
1537 ("ge" #x06)
1538 ("geu" #x08) ("c" #x08)
1539 ("gtu" #x09)
1540 ("eq" #x0a) ("z" #x0a)
1541 ("n" #x0b)
1542 ("o" #x0c)
1543 ("le" #x0d)
1544 ("lt" #x0e)
1545 )
1546 )
1547)
1548
1549(define-hardware
1550 (name h-cr1-32)
1551 (comment "control registers")
1552 (attrs m32c-isa MACH32)
1553 (type immediate UQI)
1554 (values keyword "" (("dct0" 0) ("dct1" 1) ("flg" 2) ("svf" 3) ("drc0" 4)
1555 ("drc1" 5) ("dmd0" 6) ("dmd1" 7))))
1556(define-hardware
1557 (name h-cr2-32)
1558 (comment "control registers")
1559 (attrs m32c-isa MACH32)
1560 (type immediate UQI)
1561 (values keyword "" (("intb" 0) ("sp" 1) ("sb" 2) ("fb" 3) ("svp" 4)
1562 ("vct" 5) ("isp" 7))))
1563
1564(define-hardware
1565 (name h-cr3-32)
1566 (comment "control registers")
1567 (attrs m32c-isa MACH32)
1568 (type immediate UQI)
1569 (values keyword "" (("dma0" 2) ("dma1" 3) ("dra0" 4)
1570 ("dra1" 5) ("dsa0" 6) ("dsa1" 7))))
1571(define-hardware
1572 (name h-cr-16)
1573 (comment "control registers")
1574 (attrs m16c-isa MACH16)
1575 (type immediate UQI)
1576 (values keyword "" (("intbl" 1) ("intbh" 2) ("flg" 3) ("isp" 4)
1577 ("sp" 5) ("sb" 6) ("fb" 7))))
1578
1579(define-hardware
1580 (name h-flags)
1581 (comment "flag hardware for m32c")
1582 (attrs all-isas)
1583 (type immediate UQI)
1584 (values keyword ""
1585 (("c" #x0)
1586 ("d" #x1)
1587 ("z" #x2)
1588 ("s" #x3)
1589 ("b" #x4)
1590 ("o" #x5)
1591 ("i" #x6)
1592 ("u" #x7)
1593 )
1594 )
1595)
1596
1597;-------------------------------------------------------------
1598; Misc helper hardware
1599;-------------------------------------------------------------
1600
1601(define-hardware
1602 (name h-shimm)
1603 (comment "shift immediate")
1604 (attrs all-isas)
1605 (type immediate (INT 4))
1606 (values keyword "" (("1" 0) ("2" 1) ("3" 2) ("4" 3) ("5" 4) ("6" 5) ("7" 6)
1607 ("8" 7) ("-1" -8) ("-2" -7) ("-3" -6) ("-4" -5) ("-5" -4)
1608 ("-6" -3) ("-7" -2) ("-8" -1)
1609 )))
1610(define-hardware
1611 (name h-bit-index)
1612 (comment "bit index for the next insn")
1613 (attrs m32c-isa MACH32)
1614 (type register UHI)
1615)
1616(define-hardware
1617 (name h-src-index)
1618 (comment "source index for the next insn")
1619 (attrs m32c-isa MACH32)
1620 (type register UHI)
1621)
1622(define-hardware
1623 (name h-dst-index)
1624 (comment "destination index for the next insn")
1625 (attrs m32c-isa MACH32)
1626 (type register UHI)
1627)
1628(define-hardware
1629 (name h-src-indirect)
1630 (comment "indirect src for the next insn")
1631 (attrs all-isas)
1632 (type register UHI)
1633)
1634(define-hardware
1635 (name h-dst-indirect)
1636 (comment "indirect dst for the next insn")
1637 (attrs all-isas)
1638 (type register UHI)
1639)
1640(define-hardware
1641 (name h-none)
1642 (comment "for storing unused values")
1643 (attrs m32c-isa MACH32)
1644 (type register SI)
1645)
1646\f
1647;=============================================================
1648; Operands
1649;-------------------------------------------------------------
1650; Source Registers
1651;-------------------------------------------------------------
1652
1653(dnop Src16RnQI "general register QI view" (MACH16 m16c-isa) h-gr-QI f-src16-rn)
1654(dnop Src16RnHI "general register QH view" (MACH16 m16c-isa) h-gr-HI f-src16-rn)
1655
1656(dnop Src32RnUnprefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-src32-rn-unprefixed-QI)
1657(dnop Src32RnUnprefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-src32-rn-unprefixed-HI)
1658(dnop Src32RnUnprefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-src32-rn-unprefixed-SI)
1659
1660(dnop Src32RnPrefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-src32-rn-prefixed-QI)
1661(dnop Src32RnPrefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-src32-rn-prefixed-HI)
1662(dnop Src32RnPrefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-src32-rn-prefixed-SI)
1663
1664(dnop Src16An "address register" (MACH16 m16c-isa) h-ar f-src16-an)
1665(dnop Src16AnQI "address register QI view" (MACH16 m16c-isa) h-ar-QI f-src16-an)
1666(dnop Src16AnHI "address register HI view" (MACH16 m16c-isa) h-ar-HI f-src16-an)
1667
1668(dnop Src32AnUnprefixed "address register" (MACH32 m32c-isa) h-ar f-src32-an-unprefixed)
1669(dnop Src32AnUnprefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-src32-an-unprefixed)
1670(dnop Src32AnUnprefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-src32-an-unprefixed)
1671(dnop Src32AnUnprefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-src32-an-unprefixed)
1672
1673(dnop Src32AnPrefixed "address register" (MACH32 m32c-isa) h-ar f-src32-an-prefixed)
1674(dnop Src32AnPrefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-src32-an-prefixed)
1675(dnop Src32AnPrefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-src32-an-prefixed)
1676(dnop Src32AnPrefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-src32-an-prefixed)
1677
1678; Destination Registers
1679;
1680(dnop Dst16RnQI "general register QI view" (MACH16 m16c-isa) h-gr-QI f-dst16-rn)
1681(dnop Dst16RnHI "general register HI view" (MACH16 m16c-isa) h-gr-HI f-dst16-rn)
1682(dnop Dst16RnSI "general register SI view" (MACH16 m16c-isa) h-gr-SI f-dst16-rn)
1683(dnop Dst16RnExtQI "general register QI/HI view for 'ext' insns" (MACH16 m16c-isa) h-gr-ext-QI f-dst16-rn-ext)
1684
1685(dnop Dst32R0QI-S "general register QI view" (MACH32 m32c-isa) h-r0l f-nil)
1686(dnop Dst32R0HI-S "general register HI view" (MACH32 m32c-isa) h-r0 f-nil)
1687
1688(dnop Dst32RnUnprefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-unprefixed-QI)
1689(dnop Dst32RnUnprefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-dst32-rn-unprefixed-HI)
1690(dnop Dst32RnUnprefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-dst32-rn-unprefixed-SI)
1691(dnop Dst32RnExtUnprefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-ext-QI f-dst32-rn-ext-unprefixed)
1692(dnop Dst32RnExtUnprefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-ext-HI f-dst32-rn-ext-unprefixed)
1693
1694(dnop Dst32RnPrefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-prefixed-QI)
1695(dnop Dst32RnPrefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-dst32-rn-prefixed-HI)
1696(dnop Dst32RnPrefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-dst32-rn-prefixed-SI)
1697
1698(dnop Dst16RnQI-S "general register QI view" (MACH16 m16c-isa) h-r0l-r0h f-dst16-rn-QI-s)
1699
1700(dnop Dst16AnQI-S "address register QI view" (MACH16 m16c-isa) h-ar-QI f-dst16-rn-QI-s)
1701
1702(dnop Bit16Rn "general register bit view" (MACH16 m16c-isa) h-gr-HI f-dst16-rn)
1703
1704(dnop Bit32RnPrefixed "general register bit view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-prefixed-QI)
1705(dnop Bit32RnUnprefixed "general register bit view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-unprefixed-QI)
1706
1707(dnop R0 "r0" (all-isas) h-r0 f-nil)
1708(dnop R1 "r1" (all-isas) h-r1 f-nil)
1709(dnop R2 "r2" (all-isas) h-r2 f-nil)
1710(dnop R3 "r3" (all-isas) h-r3 f-nil)
1711(dnop R0l "r0l" (all-isas) h-r0l f-nil)
1712(dnop R0h "r0h" (all-isas) h-r0h f-nil)
1713(dnop R2R0 "r2r0" (all-isas) h-r2r0 f-nil)
1714(dnop R3R1 "r3r1" (all-isas) h-r3r1 f-nil)
1715(dnop R1R2R0 "r1r2r0" (all-isas) h-r1r2r0 f-nil)
1716
1717(dnop Dst16An "address register" (MACH16 m16c-isa) h-ar f-dst16-an)
1718(dnop Dst16AnQI "address register QI view" (MACH16 m16c-isa) h-ar-QI f-dst16-an)
1719(dnop Dst16AnHI "address register HI view" (MACH16 m16c-isa) h-ar-HI f-dst16-an)
1720(dnop Dst16AnSI "address register SI view" (MACH16 m16c-isa) h-ar-SI f-dst16-an)
1721(dnop Dst16An-S "address register HI view" (MACH16 m16c-isa) h-ar-HI f-dst16-an-s)
1722
1723(dnop Dst32AnUnprefixed "address register" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed)
1724(dnop Dst32AnUnprefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-dst32-an-unprefixed)
1725(dnop Dst32AnUnprefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-dst32-an-unprefixed)
1726(dnop Dst32AnUnprefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed)
1727
1728(dnop Dst32AnExtUnprefixed "address register" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed)
1729
1730(dnop Dst32AnPrefixed "address register" (MACH32 m32c-isa) h-ar f-dst32-an-prefixed)
1731(dnop Dst32AnPrefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-dst32-an-prefixed)
1732(dnop Dst32AnPrefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-dst32-an-prefixed)
1733(dnop Dst32AnPrefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-dst32-an-prefixed)
1734
1735(dnop Bit16An "address register bit view" (MACH16 m16c-isa) h-ar f-dst16-an)
1736
1737(dnop Bit32AnPrefixed "address register bit" (MACH32 m32c-isa) h-ar f-dst32-an-prefixed)
1738(dnop Bit32AnUnprefixed "address register bit" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed)
1739
1740(dnop A0 "a0" (all-isas) h-a0 f-nil)
1741(dnop A1 "a1" (all-isas) h-a1 f-nil)
1742
1743(dnop sb "SB register" (all-isas SEM-ONLY) h-sb f-nil)
1744(dnop fb "FB register" (all-isas SEM-ONLY) h-fb f-nil)
1745(dnop sp "SP register" (all-isas SEM-ONLY) h-sp f-nil)
1746
1747(define-full-operand SrcDst16-r0l-r0h-S-normal "r0l/r0h pair" (MACH16 m16c-isa)
1748 h-sint DFLT f-5-1
1749 ((parse "r0l_r0h") (print "r0l_r0h")) () ()
1750)
1751
1752(define-full-operand Regsetpop "popm regset" (all-isas) h-uint
1753 DFLT f-8-8 ((parse "pop_regset") (print "pop_regset")) () ())
1754(define-full-operand Regsetpush "pushm regset" (all-isas) h-uint
1755 DFLT f-8-8 ((parse "push_regset") (print "push_regset")) () ())
1756
1757(dnop Rn16-push-S "r0[lh]" (MACH16 m16c-isa) h-gr-QI f-4-1)
1758(dnop An16-push-S "a[01]" (MACH16 m16c-isa) h-ar-HI f-4-1)
1759
1760;-------------------------------------------------------------
1761; Offsets and absolutes
1762;-------------------------------------------------------------
1763
1764(define-full-operand Dsp-8-u6 "unsigned 6 bit displacement at offset 8 bits" (all-isas)
1765 h-uint DFLT f-dsp-8-u6
1766 ((parse "unsigned6")) () ()
1767)
1768(define-full-operand Dsp-8-u8 "unsigned 8 bit displacement at offset 8 bits" (all-isas)
1769 h-uint DFLT f-dsp-8-u8
1770 ((parse "unsigned8")) () ()
1771)
1772(define-full-operand Dsp-8-u16 "unsigned 16 bit displacement at offset 8 bits" (all-isas)
1773 h-uint DFLT f-dsp-8-u16
1774 ((parse "unsigned16")) () ()
1775)
1776(define-full-operand Dsp-8-s8 "signed 8 bit displacement at offset 8 bits" (all-isas)
1777 h-sint DFLT f-dsp-8-s8
1778 ((parse "signed8")) () ()
1779)
f75eb1c0
DD		 1780(define-full-operand Dsp-8-s24 "signed 24 bit displacement at offset 8 bits" (all-isas)
1781 h-sint DFLT f-dsp-8-s24
1782 ((parse "signed24")) () ()
1783)
e729279b
NC		 1784(define-full-operand Dsp-8-u24 "unsigned 24 bit displacement at offset 8 bits" (all-isas)
1785 h-uint DFLT f-dsp-8-u24
1786 ((parse "unsigned24")) () ()
1787)
49f58d10
JB		 1788(define-full-operand Dsp-10-u6 "unsigned 6 bit displacement at offset 10 bits" (all-isas)
1789 h-uint DFLT f-dsp-10-u6
1790 ((parse "unsigned6")) () ()
1791)
1792(define-full-operand Dsp-16-u8 "unsigned 8 bit displacement at offset 16 bits" (all-isas)
1793 h-uint DFLT f-dsp-16-u8
1794 ((parse "unsigned8")) () ()
1795)
1796(define-full-operand Dsp-16-u16 "unsigned 16 bit displacement at offset 16 bits" (all-isas)
1797 h-uint DFLT f-dsp-16-u16
1798 ((parse "unsigned16")) () ()
1799)
1800(define-full-operand Dsp-16-u20 "unsigned 20 bit displacement at offset 16 bits" (all-isas)
1801 h-uint DFLT f-dsp-16-u24
1802 ((parse "unsigned20")) () ()
1803)
1804(define-full-operand Dsp-16-u24 "unsigned 24 bit displacement at offset 16 bits" (all-isas)
1805 h-uint DFLT f-dsp-16-u24
1806 ((parse "unsigned24")) () ()
1807)
1808(define-full-operand Dsp-16-s8 "signed 8 bit displacement at offset 16 bits" (all-isas)
1809 h-sint DFLT f-dsp-16-s8
1810 ((parse "signed8")) () ()
1811)
1812(define-full-operand Dsp-16-s16 "signed 16 bit displacement at offset 16 bits" (all-isas)
1813 h-sint DFLT f-dsp-16-s16
1814 ((parse "signed16")) () ()
1815)
1816(define-full-operand Dsp-24-u8 "unsigned 8 bit displacement at offset 24 bits" (all-isas)
1817 h-uint DFLT f-dsp-24-u8
1818 ((parse "unsigned8")) () ()
1819)
1820(define-full-operand Dsp-24-u16 "unsigned 16 bit displacement at offset 24 bits" (all-isas)
1821 h-uint DFLT f-dsp-24-u16
1822 ((parse "unsigned16")) () ()
1823)
1824(define-full-operand Dsp-24-u20 "unsigned 20 bit displacement at offset 24 bits" (all-isas)
1825 h-uint DFLT f-dsp-24-u24
1826 ((parse "unsigned20")) () ()
1827)
1828(define-full-operand Dsp-24-u24 "unsigned 24 bit displacement at offset 24 bits" (all-isas)
1829 h-uint DFLT f-dsp-24-u24
1830 ((parse "unsigned24")) () ()
1831)
1832(define-full-operand Dsp-24-s8 "signed 8 bit displacement at offset 24 bits" (all-isas)
1833 h-sint DFLT f-dsp-24-s8
1834 ((parse "signed8")) () ()
1835)
1836(define-full-operand Dsp-24-s16 "signed 16 bit displacement at offset 24 bits" (all-isas)
1837 h-sint DFLT f-dsp-24-s16
1838 ((parse "signed16")) () ()
1839)
1840(define-full-operand Dsp-32-u8 "unsigned 8 bit displacement at offset 32 bits" (all-isas)
1841 h-uint DFLT f-dsp-32-u8
1842 ((parse "unsigned8")) () ()
1843)
1844(define-full-operand Dsp-32-u16 "unsigned 16 bit displacement at offset 32 bits" (all-isas)
1845 h-uint DFLT f-dsp-32-u16
1846 ((parse "unsigned16")) () ()
1847)
1848(define-full-operand Dsp-32-u24 "unsigned 24 bit displacement at offset 32 bits" (all-isas)
1849 h-uint DFLT f-dsp-32-u24
1850 ((parse "unsigned24")) () ()
1851)
1852(define-full-operand Dsp-32-u20 "unsigned 20 bit displacement at offset 32 bits" (all-isas)
1853 h-uint DFLT f-dsp-32-u24
1854 ((parse "unsigned20")) () ()
1855)
1856(define-full-operand Dsp-32-s8 "signed 8 bit displacement at offset 32 bits" (all-isas)
1857 h-sint DFLT f-dsp-32-s8
1858 ((parse "signed8")) () ()
1859)
1860(define-full-operand Dsp-32-s16 "signed 16 bit displacement at offset 32 bits" (all-isas)
1861 h-sint DFLT f-dsp-32-s16
1862 ((parse "signed16")) () ()
1863)
1864(define-full-operand Dsp-40-u8 "unsigned 8 bit displacement at offset 40 bits" (all-isas)
1865 h-uint DFLT f-dsp-40-u8
1866 ((parse "unsigned8")) () ()
1867)
1868(define-full-operand Dsp-40-s8 "signed 8 bit displacement at offset 40 bits" (all-isas)
e729279b 1869 h-sint DFLT f-dsp-40-s8
49f58d10
JB		 1870 ((parse "signed8")) () ()
1871)
1872(define-full-operand Dsp-40-u16 "unsigned 16 bit displacement at offset 40 bits" (all-isas)
1873 h-uint DFLT f-dsp-40-u16
1874 ((parse "unsigned16")) () ()
1875)
1876(define-full-operand Dsp-40-s16 "signed 16 bit displacement at offset 40 bits" (all-isas)
e729279b 1877 h-sint DFLT f-dsp-40-s16
49f58d10
JB		 1878 ((parse "signed16")) () ()
1879)
1880(define-full-operand Dsp-40-u24 "unsigned 24 bit displacement at offset 40 bits" (all-isas)
1881 h-uint DFLT f-dsp-40-u24
1882 ((parse "unsigned24")) () ()
1883)
1884(define-full-operand Dsp-48-u8 "unsigned 8 bit displacement at offset 48 bits" (all-isas)
1885 h-uint DFLT f-dsp-48-u8
1886 ((parse "unsigned8")) () ()
1887)
1888(define-full-operand Dsp-48-s8 "signed 8 bit displacement at offset 48 bits" (all-isas)
e729279b 1889 h-sint DFLT f-dsp-48-s8
49f58d10
JB		 1890 ((parse "signed8")) () ()
1891)
1892(define-full-operand Dsp-48-u16 "unsigned 16 bit displacement at offset 48 bits" (all-isas)
1893 h-uint DFLT f-dsp-48-u16
1894 ((parse "unsigned16")) () ()
1895)
1896(define-full-operand Dsp-48-s16 "signed 16 bit displacement at offset 48 bits" (all-isas)
e729279b 1897 h-sint DFLT f-dsp-48-s16
49f58d10
JB		 1898 ((parse "signed16")) () ()
1899)
1900(define-full-operand Dsp-48-u24 "unsigned 24 bit displacement at offset 48 bits" (all-isas)
1901 h-uint DFLT f-dsp-48-u24
1902 ((parse "unsigned24")) () ()
1903)
1904
1905(define-full-operand Imm-8-s4 "signed 4 bit immediate at offset 8 bits" (all-isas)
1906 h-sint DFLT f-imm-8-s4
1907 ((parse "signed4")) () ()
1908)
c6552317
DD		 1909(define-full-operand Imm-8-s4n "negated 4 bit immediate at offset 8 bits" (all-isas)
1910 h-sint DFLT f-imm-8-s4
1911 ((parse "signed4n")) () ()
1912)
49f58d10
JB		 1913(define-full-operand Imm-sh-8-s4 "signed 4 bit shift immediate at offset 8 bits" (all-isas)
1914 h-shimm DFLT f-imm-8-s4
1915 () () ()
1916)
1917(define-full-operand Imm-8-QI "signed 8 bit immediate at offset 8 bits" (all-isas)
1918 h-sint DFLT f-dsp-8-s8
1919 ((parse "signed8")) () ()
1920)
1921(define-full-operand Imm-8-HI "signed 16 bit immediate at offset 8 bits" (all-isas)
1922 h-sint DFLT f-dsp-8-s16
1923 ((parse "signed16")) () ()
1924)
1925(define-full-operand Imm-12-s4 "signed 4 bit immediate at offset 12 bits" (all-isas)
1926 h-sint DFLT f-imm-12-s4
1927 ((parse "signed4")) () ()
1928)
c6552317
DD		 1929(define-full-operand Imm-12-s4n "negated 4 bit immediate at offset 12 bits" (all-isas)
1930 h-sint DFLT f-imm-12-s4
1931 ((parse "signed4n") (print "signed4n")) () ()
1932)
49f58d10
JB		 1933(define-full-operand Imm-sh-12-s4 "signed 4 bit shift immediate at offset 12 bits" (all-isas)
1934 h-shimm DFLT f-imm-12-s4
1935 () () ()
1936)
1937(define-full-operand Imm-13-u3 "signed 3 bit immediate at offset 13 bits" (all-isas)
e729279b 1938 h-sint DFLT f-imm-13-u3
49f58d10
JB		 1939 ((parse "signed4")) () ()
1940)
1941(define-full-operand Imm-20-s4 "signed 4 bit immediate at offset 20 bits" (all-isas)
1942 h-sint DFLT f-imm-20-s4
1943 ((parse "signed4")) () ()
1944)
1945(define-full-operand Imm-sh-20-s4 "signed 4 bit shift immediate at offset 12 bits" (all-isas)
1946 h-shimm DFLT f-imm-20-s4
1947 () () ()
1948)
1949(define-full-operand Imm-16-QI "signed 8 bit immediate at offset 16 bits" (all-isas)
1950 h-sint DFLT f-dsp-16-s8
1951 ((parse "signed8")) () ()
1952)
1953(define-full-operand Imm-16-HI "signed 16 bit immediate at offset 16 bits" (all-isas)
1954 h-sint DFLT f-dsp-16-s16
1955 ((parse "signed16")) () ()
1956)
1957(define-full-operand Imm-16-SI "signed 32 bit immediate at offset 16 bits" (all-isas)
1958 h-sint DFLT f-dsp-16-s32
1959 ((parse "signed32")) () ()
1960)
1961(define-full-operand Imm-24-QI "signed 8 bit immediate at offset 24 bits" (all-isas)
1962 h-sint DFLT f-dsp-24-s8
1963 ((parse "signed8")) () ()
1964)
1965(define-full-operand Imm-24-HI "signed 16 bit immediate at offset 24 bits" (all-isas)
1966 h-sint DFLT f-dsp-24-s16
1967 ((parse "signed16")) () ()
1968)
1969(define-full-operand Imm-24-SI "signed 32 bit immediate at offset 24 bits" (all-isas)
1970 h-sint DFLT f-dsp-24-s32
1971 ((parse "signed32")) () ()
1972)
1973(define-full-operand Imm-32-QI "signed 8 bit immediate at offset 32 bits" (all-isas)
1974 h-sint DFLT f-dsp-32-s8
1975 ((parse "signed8")) () ()
1976)
1977(define-full-operand Imm-32-SI "signed 32 bit immediate at offset 32 bits" (all-isas)
1978 h-sint DFLT f-dsp-32-s32
1979 ((parse "signed32")) () ()
1980)
1981(define-full-operand Imm-32-HI "signed 16 bit immediate at offset 32 bits" (all-isas)
1982 h-sint DFLT f-dsp-32-s16
1983 ((parse "signed16")) () ()
1984)
1985(define-full-operand Imm-40-QI "signed 8 bit immediate at offset 40 bits" (all-isas)
1986 h-sint DFLT f-dsp-40-s8
1987 ((parse "signed8")) () ()
1988)
1989(define-full-operand Imm-40-HI "signed 16 bit immediate at offset 40 bits" (all-isas)
1990 h-sint DFLT f-dsp-40-s16
1991 ((parse "signed16")) () ()
1992)
1993(define-full-operand Imm-40-SI "signed 32 bit immediate at offset 40 bits" (all-isas)
1994 h-sint DFLT f-dsp-40-s32
1995 ((parse "signed32")) () ()
1996)
1997(define-full-operand Imm-48-QI "signed 8 bit immediate at offset 48 bits" (all-isas)
1998 h-sint DFLT f-dsp-48-s8
1999 ((parse "signed8")) () ()
2000)
2001(define-full-operand Imm-48-HI "signed 16 bit immediate at offset 48 bits" (all-isas)
2002 h-sint DFLT f-dsp-48-s16
2003 ((parse "signed16")) () ()
2004)
2005(define-full-operand Imm-48-SI "signed 32 bit immediate at offset 48 bits" (all-isas)
2006 h-sint DFLT f-dsp-48-s32
2007 ((parse "signed32")) () ()
2008)
2009(define-full-operand Imm-56-QI "signed 8 bit immediate at offset 56 bits" (all-isas)
2010 h-sint DFLT f-dsp-56-s8
2011 ((parse "signed8")) () ()
2012)
2013(define-full-operand Imm-56-HI "signed 16 bit immediate at offset 56 bits" (all-isas)
2014 h-sint DFLT f-dsp-56-s16
2015 ((parse "signed16")) () ()
2016)
2017(define-full-operand Imm-64-HI "signed 16 bit immediate at offset 64 bits" (all-isas)
2018 h-sint DFLT f-dsp-64-s16
2019 ((parse "signed16")) () ()
2020)
2021(define-full-operand Imm1-S "signed 1 bit immediate for short format binary insns" (m32c-isa)
2022 h-sint DFLT f-imm1-S
2023 ((parse "imm1_S")) () ()
2024)
2025(define-full-operand Imm3-S "signed 3 bit immediate for short format binary insns" (m32c-isa)
2026 h-sint DFLT f-imm3-S
2027 ((parse "imm3_S")) () ()
2028)
43aa3bb1
DD		 2029(define-full-operand Bit3-S "3 bit bit number" (m32c-isa)
2030 h-sint DFLT f-imm3-S
2031 ((parse "bit3_S")) () ()
2032)
49f58d10
JB		 2033
2034;-------------------------------------------------------------
2035; Bit numbers
2036;-------------------------------------------------------------
2037
2038(define-full-operand Bitno16R "bit number for indexing registers" (m16c-isa)
2039 h-uint DFLT f-dsp-16-u8
2040 ((parse "Bitno16R")) () ()
2041)
2042(dnop Bitno32Prefixed "bit number for indexing objects" (m32c-isa) h-uint f-bitno32-prefixed)
2043(dnop Bitno32Unprefixed "bit number for indexing objects" (m32c-isa) h-uint f-bitno32-unprefixed)
2044
2045(define-full-operand BitBase16-16-u8 "unsigned bit,base:8 at offset 16for m16c" (m16c-isa)
2046 h-uint DFLT f-dsp-16-u8
2047 ((parse "unsigned_bitbase8") (print "unsigned_bitbase")) () ()
2048)
2049(define-full-operand BitBase16-16-s8 "signed bit,base:8 at offset 16for m16c" (m16c-isa)
e729279b 2050 h-sint DFLT f-dsp-16-s8
49f58d10
JB		 2051 ((parse "signed_bitbase8") (print "signed_bitbase")) () ()
2052)
2053(define-full-operand BitBase16-16-u16 "unsigned bit,base:16 at offset 16 for m16c" (m16c-isa)
2054 h-uint DFLT f-dsp-16-u16
2055 ((parse "unsigned_bitbase16") (print "unsigned_bitbase")) () ()
2056)
2057(define-full-operand BitBase16-8-u11-S "signed bit,base:11 at offset 16 for m16c" (m16c-isa)
e729279b 2058 h-uint DFLT f-bitbase16-u11-S
49f58d10
JB		 2059 ((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () ()
2060)
2061
2062(define-full-operand BitBase32-16-u11-Unprefixed "unsigned bit,base:11 at offset 16 for m32c" (m32c-isa)
2063 h-uint DFLT f-bitbase32-16-u11-unprefixed
2064 ((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () ()
2065)
2066(define-full-operand BitBase32-16-s11-Unprefixed "signed bit,base:11 at offset 16 for m32c" (m32c-isa)
2067 h-sint DFLT f-bitbase32-16-s11-unprefixed
2068 ((parse "signed_bitbase11") (print "signed_bitbase")) () ()
2069)
2070(define-full-operand BitBase32-16-u19-Unprefixed "unsigned bit,base:19 at offset 16 for m32c" (m32c-isa)
2071 h-uint DFLT f-bitbase32-16-u19-unprefixed
2072 ((parse "unsigned_bitbase19") (print "unsigned_bitbase")) () ()
2073)
2074(define-full-operand BitBase32-16-s19-Unprefixed "signed bit,base:19 at offset 16 for m32c" (m32c-isa)
2075 h-sint DFLT f-bitbase32-16-s19-unprefixed
2076 ((parse "signed_bitbase19") (print "signed_bitbase")) () ()
2077)
2078(define-full-operand BitBase32-16-u27-Unprefixed "unsigned bit,base:27 at offset 16 for m32c" (m32c-isa)
2079 h-uint DFLT f-bitbase32-16-u27-unprefixed
2080 ((parse "unsigned_bitbase27") (print "unsigned_bitbase")) () ()
2081)
2082(define-full-operand BitBase32-24-u11-Prefixed "unsigned bit,base:11 at offset 24 for m32c" (m32c-isa)
2083 h-uint DFLT f-bitbase32-24-u11-prefixed
2084 ((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () ()
2085)
2086(define-full-operand BitBase32-24-s11-Prefixed "signed bit,base:11 at offset 24 for m32c" (m32c-isa)
2087 h-sint DFLT f-bitbase32-24-s11-prefixed
2088 ((parse "signed_bitbase11") (print "signed_bitbase")) () ()
2089)
2090(define-full-operand BitBase32-24-u19-Prefixed "unsigned bit,base:19 at offset 24 for m32c" (m32c-isa)
2091 h-uint DFLT f-bitbase32-24-u19-prefixed
2092 ((parse "unsigned_bitbase19") (print "unsigned_bitbase")) () ()
2093)
2094(define-full-operand BitBase32-24-s19-Prefixed "signed bit,base:19 at offset 24 for m32c" (m32c-isa)
2095 h-sint DFLT f-bitbase32-24-s19-prefixed
2096 ((parse "signed_bitbase19") (print "signed_bitbase")) () ()
2097)
2098(define-full-operand BitBase32-24-u27-Prefixed "unsigned bit,base:27 at offset 24 for m32c" (m32c-isa)
2099 h-uint DFLT f-bitbase32-24-u27-prefixed
2100 ((parse "unsigned_bitbase27") (print "unsigned_bitbase")) () ()
2101)
2102;-------------------------------------------------------------
2103; Labels
2104;-------------------------------------------------------------
2105
e729279b
NC		 2106(define-full-operand Lab-5-3 "3 bit label" (all-isas RELAX)
2107 h-iaddr DFLT f-lab-5-3
2108 ((parse "lab_5_3")) () () )
2109
2110(define-full-operand Lab32-jmp-s "3 bit label" (all-isas RELAX)
2111 h-iaddr DFLT f-lab32-jmp-s
2112 ((parse "lab_5_3")) () () )
2113
2114(dnop Lab-8-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-8-8)
2115(dnop Lab-8-16 "16 bit label" (all-isas RELAX) h-iaddr f-lab-8-16)
6772dd07 2116(dnop Lab-8-24 "24 bit label" (all-isas RELAX) h-iaddr f-lab-8-24)
e729279b 2117(dnop Lab-16-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-16-8)
49f58d10
JB		 2118(dnop Lab-24-8 "8 bit label" (all-isas) h-iaddr f-lab-24-8)
2119(dnop Lab-32-8 "8 bit label" (all-isas) h-iaddr f-lab-32-8)
2120(dnop Lab-40-8 "8 bit label" (all-isas) h-iaddr f-lab-40-8)
2121
2122;-------------------------------------------------------------
2123; Condition code bits
2124;-------------------------------------------------------------
2125
2126(dnop sbit "negative bit" (SEM-ONLY all-isas) h-sbit f-nil)
2127(dnop obit "overflow bit" (SEM-ONLY all-isas) h-obit f-nil)
2128(dnop zbit "zero bit" (SEM-ONLY all-isas) h-zbit f-nil)
2129(dnop cbit "carry bit" (SEM-ONLY all-isas) h-cbit f-nil)
2130(dnop ubit "stack ptr select bit" (SEM-ONLY all-isas) h-ubit f-nil)
2131(dnop ibit "interrupt enable bit" (SEM-ONLY all-isas) h-ibit f-nil)
2132(dnop bbit "reg bank select bit" (SEM-ONLY all-isas) h-bbit f-nil)
2133(dnop dbit "debug bit" (SEM-ONLY all-isas) h-dbit f-nil)
2134
2135;-------------------------------------------------------------
2136; Condition operands
2137;-------------------------------------------------------------
2138
2139(define-pmacro (cond-operand mach offset)
2140 (dnop (.sym cond mach - offset) "condition" ((.sym m mach c-isa)) (.sym h-cond mach) (.sym f-dsp- offset -u8))
2141)
2142
2143(cond-operand 16 16)
2144(cond-operand 16 24)
2145(cond-operand 16 32)
2146(cond-operand 32 16)
2147(cond-operand 32 24)
2148(cond-operand 32 32)
2149(cond-operand 32 40)
2150
2151(dnop cond16c "condition" (m16c-isa) h-cond16c f-cond16)
2152(dnop cond16j "condition" (m16c-isa) h-cond16j f-cond16)
2153(dnop cond16j5 "condition" (m16c-isa) h-cond16j-5 f-cond16j-5)
2154(dnop cond32 "condition" (m32c-isa) h-cond32 f-cond32)
2155(dnop cond32j "condition" (m32c-isa) h-cond32 f-cond32j)
2156(dnop sccond32 "scCND condition" (m32c-isa) h-cond32 f-cond16)
2157(dnop flags16 "flags" (m16c-isa) h-flags f-9-3)
2158(dnop flags32 "flags" (m32c-isa) h-flags f-13-3)
2159(dnop cr16 "control" (m16c-isa) h-cr-16 f-9-3)
2160(dnop cr1-Unprefixed-32 "control" (m32c-isa) h-cr1-32 f-13-3)
2161(dnop cr1-Prefixed-32 "control" (m32c-isa) h-cr1-32 f-21-3)
2162(dnop cr2-32 "control" (m32c-isa) h-cr2-32 f-13-3)
2163(dnop cr3-Unprefixed-32 "control" (m32c-isa) h-cr3-32 f-13-3)
2164(dnop cr3-Prefixed-32 "control" (m32c-isa) h-cr3-32 f-21-3)
2165
2166;-------------------------------------------------------------
2167; Suffixes
2168;-------------------------------------------------------------
2169
2170(define-full-operand Z "Suffix for zero format insns" (all-isas)
2171 h-sint DFLT f-nil
2172 ((parse "Z") (print "Z")) () ()
2173)
2174(define-full-operand S "Suffix for short format insns" (all-isas)
2175 h-sint DFLT f-nil
2176 ((parse "S") (print "S")) () ()
2177)
2178(define-full-operand Q "Suffix for quick format insns" (all-isas)
2179 h-sint DFLT f-nil
2180 ((parse "Q") (print "Q")) () ()
2181)
2182(define-full-operand G "Suffix for general format insns" (all-isas)
2183 h-sint DFLT f-nil
2184 ((parse "G") (print "G")) () ()
2185)
2186(define-full-operand X "Empty suffix" (all-isas)
2187 h-sint DFLT f-nil
2188 ((parse "X") (print "X")) () ()
2189)
2190(define-full-operand size "any size specifier" (all-isas)
2191 h-sint DFLT f-nil
2192 ((parse "size") (print "size")) () ()
2193)
2194;-------------------------------------------------------------
2195; Misc
2196;-------------------------------------------------------------
2197
2198(dnop BitIndex "Bit Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-bit-index f-nil)
2199(dnop SrcIndex "Source Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-src-index f-nil)
2200(dnop DstIndex "Destination Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-dst-index f-nil)
2201(dnop NoRemainder "Place holder for when the remainder is not kept" (SEM-ONLY MACH32 m32c-isa) h-none f-nil)
2202\f
2203;=============================================================
2204; Derived Operands
2205
2206; Memory reference macros that clip addresses appropriately. Refer to
2207; memory at ADDRESS in MODE, clipped appropriately for either the m16c
2208; or m32c.
2209(define-pmacro (mem16 mode address)
2210 (mem mode (and #xffff address)))
2211
2212(define-pmacro (mem32 mode address)
2213 (mem mode (and #xffffff address)))
2214
2215; Like mem16 and mem32, but takes MACH as a parameter. MACH must be
2216; either 16 or 32.
2217(define-pmacro (mem-mach mach mode address)
2218 ((.sym mem mach) mode address))
2219
2220;-------------------------------------------------------------
2221; Source
2222;-------------------------------------------------------------
2223; Rn direct
2224;-------------------------------------------------------------
2225
2226(define-pmacro (src16-Rn-direct-operand xmode)
2227 (begin
2228 (define-derived-operand
2229 (name (.sym src16-Rn-direct- xmode))
2230 (comment (.str "m16c Rn direct source " xmode))
2231 (attrs (machine 16))
2232 (mode xmode)
2233 (args ((.sym Src16Rn xmode)))
2234 (syntax (.str "$Src16Rn" xmode))
2235 (base-ifield f-8-4)
2236 (encoding (+ (f-8-2 0) (.sym Src16Rn xmode)))
2237 (ifield-assertion (eq f-8-2 0))
2238 (getter (trunc xmode (.sym Src16Rn xmode)))
2239 (setter (set (.sym Src16Rn xmode) newval))
2240 )
2241 )
2242)
2243(src16-Rn-direct-operand QI)
2244(src16-Rn-direct-operand HI)
2245
2246(define-pmacro (src32-Rn-direct-operand group base xmode)
2247 (begin
2248 (define-derived-operand
2249 (name (.sym src32-Rn-direct- group - xmode))
2250 (comment (.str "m32c Rn direct source " xmode))
2251 (attrs (machine 32))
2252 (mode xmode)
2253 (args ((.sym Src32Rn group xmode)))
2254 (syntax (.str "$Src32Rn" group xmode))
2255 (base-ifield (.sym f- base -11))
2256 (encoding (+ ((.sym f- base -3) 4) (.sym Src32Rn group xmode)))
2257 (ifield-assertion (eq (.sym f- base -3) 4))
2258 (getter (trunc xmode (.sym Src32Rn group xmode)))
2259 (setter (set (.sym Src32Rn group xmode) newval))
2260 )
2261 )
2262)
2263
2264(src32-Rn-direct-operand Unprefixed 1 QI)
2265(src32-Rn-direct-operand Prefixed 9 QI)
2266(src32-Rn-direct-operand Unprefixed 1 HI)
2267(src32-Rn-direct-operand Prefixed 9 HI)
2268(src32-Rn-direct-operand Unprefixed 1 SI)
2269(src32-Rn-direct-operand Prefixed 9 SI)
2270
2271;-------------------------------------------------------------
2272; An direct
2273;-------------------------------------------------------------
2274
2275(define-pmacro (src16-An-direct-operand xmode)
2276 (begin
2277 (define-derived-operand
2278 (name (.sym src16-An-direct- xmode))
2279 (comment (.str "m16c An direct destination " xmode))
2280 (attrs (machine 16))
2281 (mode xmode)
2282 (args ((.sym Src16An xmode)))
2283 (syntax (.str "$Src16An" xmode))
2284 (base-ifield f-8-4)
2285 (encoding (+ (f-8-2 1) (f-10-1 0) (.sym Src16An xmode)))
2286 (ifield-assertion (andif (eq f-8-2 1) (eq f-10-1 0)))
2287 (getter (trunc xmode (.sym Src16An xmode)))
2288 (setter (set (.sym Src16An xmode) newval))
2289 )
2290 )
2291)
2292(src16-An-direct-operand QI)
2293(src16-An-direct-operand HI)
2294
2295(define-pmacro (src32-An-direct-operand group base1 base2 xmode)
2296 (begin
2297 (define-derived-operand
2298 (name (.sym src32-An-direct- group - xmode))
2299 (comment (.str "m32c An direct destination " xmode))
2300 (attrs (machine 32))
2301 (mode xmode)
2302 (args ((.sym Src32An group xmode)))
2303 (syntax (.str "$Src32An" group xmode))
2304 (base-ifield (.sym f- base1 -11))
2305 (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 1) (.sym Src32An group xmode)))
2306 (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 1)))
2307 (getter (trunc xmode (.sym Src32An group xmode)))
2308 (setter (set (.sym Src32An group xmode) newval))
2309 )
2310 )
2311)
2312
2313(src32-An-direct-operand Unprefixed 1 10 QI)
2314(src32-An-direct-operand Unprefixed 1 10 HI)
2315(src32-An-direct-operand Unprefixed 1 10 SI)
2316(src32-An-direct-operand Prefixed 9 18 QI)
2317(src32-An-direct-operand Prefixed 9 18 HI)
2318(src32-An-direct-operand Prefixed 9 18 SI)
2319
2320;-------------------------------------------------------------
2321; An indirect
2322;-------------------------------------------------------------
2323
2324(define-pmacro (src16-An-indirect-operand xmode)
2325 (begin
2326 (define-derived-operand
2327 (name (.sym src16-An-indirect- xmode))
2328 (comment (.str "m16c An indirect destination " xmode))
2329 (attrs (machine 16))
2330 (mode xmode)
2331 (args (Src16An))
2332 (syntax "[$Src16An]")
2333 (base-ifield f-8-4)
2334 (encoding (+ (f-8-2 1) (f-10-1 1) Src16An))
2335 (ifield-assertion (andif (eq f-8-2 1) (eq f-10-1 1)))
2336 (getter (mem16 xmode Src16An))
2337 (setter (set (mem16 xmode Src16An) newval))
2338 )
2339 )
2340)
2341(src16-An-indirect-operand QI)
2342(src16-An-indirect-operand HI)
2343
2344(define-pmacro (src32-An-indirect-operand group base1 base2 xmode)
2345 (begin
2346 (define-derived-operand
2347 (name (.sym src32-An-indirect- group - xmode))
2348 (comment (.str "m32c An indirect destination " xmode))
2349 (attrs (machine 32))
2350 (mode xmode)
2351 (args ((.sym Src32An group)))
2352 (syntax (.str "[$Src32An" group "]"))
2353 (base-ifield (.sym f- base1 -11))
2354 (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 0) (.sym Src32An group)))
2355 (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 0)))
2356 (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group)
2357 (const 0)))
2358 (setter (c-call DFLT (.str "operand_setter_" xmode) newval
2359 (.sym Src32An group) (const 0)))
2360; (getter (mem32 xmode (.sym Src32An group)))
2361; (setter (set (mem32 xmode (.sym Src32An group)) newval))
2362 )
2363 )
2364)
2365
2366(src32-An-indirect-operand Unprefixed 1 10 QI)
2367(src32-An-indirect-operand Unprefixed 1 10 HI)
2368(src32-An-indirect-operand Unprefixed 1 10 SI)
2369(src32-An-indirect-operand Prefixed 9 18 QI)
2370(src32-An-indirect-operand Prefixed 9 18 HI)
2371(src32-An-indirect-operand Prefixed 9 18 SI)
2372
2373;-------------------------------------------------------------
2374; dsp:d[r] relative
2375;-------------------------------------------------------------
2376
2377(define-pmacro (src16-relative-operand xmode)
2378 (begin
2379 (define-derived-operand
2380 (name (.sym src16-16-8-SB-relative- xmode))
2381 (comment (.str "m16c dsp:8[sb] relative destination " xmode))
2382 (attrs (machine 16))
2383 (mode xmode)
2384 (args (Dsp-16-u8))
2385 (syntax "${Dsp-16-u8}[sb]")
2386 (base-ifield f-8-4)
2387 (encoding (+ (f-8-4 #xA) Dsp-16-u8))
2388 (ifield-assertion (eq f-8-4 #xA))
2389 (getter (mem16 xmode (add Dsp-16-u8 (reg h-sb))))
2390 (setter (set (mem16 xmode (add Dsp-16-u8 (reg h-sb))) newval))
2391 )
2392 (define-derived-operand
2393 (name (.sym src16-16-16-SB-relative- xmode))
2394 (comment (.str "m16c dsp:16[sb] relative destination " xmode))
2395 (attrs (machine 16))
2396 (mode xmode)
2397 (args (Dsp-16-u16))
2398 (syntax "${Dsp-16-u16}[sb]")
2399 (base-ifield f-8-4)
2400 (encoding (+ (f-8-4 #xE) Dsp-16-u16))
2401 (ifield-assertion (eq f-8-4 #xE))
2402 (getter (mem16 xmode (add Dsp-16-u16 (reg h-sb))))
2403 (setter (set (mem16 xmode (add Dsp-16-u16 (reg h-sb))) newval))
2404 )
2405 (define-derived-operand
2406 (name (.sym src16-16-8-FB-relative- xmode))
2407 (comment (.str "m16c dsp:8[fb] relative destination " xmode))
2408 (attrs (machine 16))
2409 (mode xmode)
2410 (args (Dsp-16-s8))
2411 (syntax "${Dsp-16-s8}[fb]")
2412 (base-ifield f-8-4)
2413 (encoding (+ (f-8-4 #xB) Dsp-16-s8))
2414 (ifield-assertion (eq f-8-4 #xB))
2415 (getter (mem16 xmode (add Dsp-16-s8 (reg h-fb))))
2416 (setter (set (mem16 xmode (add Dsp-16-s8 (reg h-fb))) newval))
2417 )
2418 (define-derived-operand
2419 (name (.sym src16-16-8-An-relative- xmode))
2420 (comment (.str "m16c dsp:8[An] relative destination " xmode))
2421 (attrs (machine 16))
2422 (mode xmode)
2423 (args (Src16An Dsp-16-u8))
2424 (syntax "${Dsp-16-u8}[$Src16An]")
2425 (base-ifield f-8-4)
2426 (encoding (+ (f-8-2 2) (f-10-1 0) Dsp-16-u8 Src16An))
2427 (ifield-assertion (andif (eq f-8-2 2) (eq f-10-1 0)))
2428 (getter (mem16 xmode (add Dsp-16-u8 Src16An)))
2429 (setter (set (mem16 xmode (add Dsp-16-u8 Src16An)) newval))
2430 )
2431 (define-derived-operand
2432 (name (.sym src16-16-16-An-relative- xmode))
2433 (comment (.str "m16c dsp:16[An] relative destination " xmode))
2434 (attrs (machine 16))
2435 (mode xmode)
2436 (args (Src16An Dsp-16-u16))
2437 (syntax "${Dsp-16-u16}[$Src16An]")
2438 (base-ifield f-8-4)
2439 (encoding (+ (f-8-2 3) (f-10-1 0) Dsp-16-u16 Src16An))
2440 (ifield-assertion (andif (eq f-8-2 3) (eq f-10-1 0)))
2441 (getter (mem16 xmode (add Dsp-16-u16 Src16An)))
2442 (setter (set (mem16 xmode (add Dsp-16-u16 Src16An)) newval))
2443 )
2444 )
2445)
2446
2447(src16-relative-operand QI)
2448(src16-relative-operand HI)
2449
2450(define-pmacro (src32-relative-operand offset group base1 base2 xmode)
2451 (begin
2452 (define-derived-operand
2453 (name (.sym src32- offset -8-SB-relative- group - xmode))
2454 (comment (.str "m32c dsp:8[sb] relative destination " xmode))
2455 (attrs (machine 32))
2456 (mode xmode)
2457 (args ((.sym Dsp- offset -u8)))
2458 (syntax (.str "${Dsp-" offset "-u8}[sb]"))
2459 (base-ifield (.sym f- base1 -11))
2460 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u8)))
2461 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 2)))
2462 (getter (c-call xmode (.str "operand_getter_" xmode) sb (.sym Dsp- offset -u8)))
2463 (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb (.sym Dsp- offset -u8)))
2464; (getter (mem32 xmode (add (.sym Dsp- offset -u8) (reg h-sb))))
2465; (setter (set (mem32 xmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval))
2466 )
2467 (define-derived-operand
2468 (name (.sym src32- offset -16-SB-relative- group - xmode))
2469 (comment (.str "m32c dsp:16[sb] relative destination " xmode))
2470 (attrs (machine 32))
2471 (mode xmode)
2472 (args ((.sym Dsp- offset -u16)))
2473 (syntax (.str "${Dsp-" offset "-u16}[sb]"))
2474 (base-ifield (.sym f- base1 -11))
2475 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u16)))
2476 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 2)))
2477 (getter (c-call xmode (.str "operand_getter_" xmode) sb (.sym Dsp- offset -u16)))
2478 (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb (.sym Dsp- offset -u16)))
2479; (getter (mem32 xmode (add (.sym Dsp- offset -u16) (reg h-sb))))
2480; (setter (set (mem32 xmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval))
2481 )
2482 (define-derived-operand
2483 (name (.sym src32- offset -8-FB-relative- group - xmode))
2484 (comment (.str "m32c dsp:8[fb] relative destination " xmode))
2485 (attrs (machine 32))
2486 (mode xmode)
2487 (args ((.sym Dsp- offset -s8)))
2488 (syntax (.str "${Dsp-" offset "-s8}[fb]"))
2489 (base-ifield (.sym f- base1 -11))
2490 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s8)))
2491 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 3)))
2492 (getter (c-call xmode (.str "operand_getter_" xmode) fb (.sym Dsp- offset -s8)))
2493 (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb (.sym Dsp- offset -s8)))
2494; (getter (mem32 xmode (add (.sym Dsp- offset -s8) (reg h-fb))))
2495; (setter (set (mem32 xmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval))
2496 )
2497 (define-derived-operand
2498 (name (.sym src32- offset -16-FB-relative- group - xmode))
2499 (comment (.str "m32c dsp:16[fb] relative destination " xmode))
2500 (attrs (machine 32))
2501 (mode xmode)
2502 (args ((.sym Dsp- offset -s16)))
2503 (syntax (.str "${Dsp-" offset "-s16}[fb]"))
2504 (base-ifield (.sym f- base1 -11))
2505 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s16)))
2506 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 3)))
2507 (getter (c-call xmode (.str "operand_getter_" xmode) fb (.sym Dsp- offset -s16)))
2508 (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb (.sym Dsp- offset -s16)))
2509; (getter (mem32 xmode (add (.sym Dsp- offset -s16) (reg h-fb))))
2510; (setter (set (mem32 xmode (add (.sym Dsp- offset -s16) (reg h-fb))) newval))
2511 )
2512 (define-derived-operand
2513 (name (.sym src32- offset -8-An-relative- group - xmode))
2514 (comment (.str "m32c dsp:8[An] relative destination " xmode))
2515 (attrs (machine 32))
2516 (mode xmode)
2517 (args ((.sym Src32An group) (.sym Dsp- offset -u8)))
2518 (syntax (.str "${Dsp-" offset "-u8}[$Src32An" group "]"))
2519 (base-ifield (.sym f- base1 -11))
2520 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u8) (.sym Src32An group)))
2521 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -1) 0)))
2522 (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) (.sym Dsp- offset -u8)))
2523 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (.sym Src32An group) (.sym Dsp- offset -u8)))
2524; (getter (mem32 xmode (add (.sym Dsp- offset -u8) (.sym Src32An group))))
2525; (setter (set (mem32 xmode (add (.sym Dsp- offset -u8) (.sym Src32An group))) newval))
2526 )
2527 (define-derived-operand
2528 (name (.sym src32- offset -16-An-relative- group - xmode))
2529 (comment (.str "m32c dsp:16[An] relative destination " xmode))
2530 (attrs (machine 32))
2531 (mode xmode)
2532 (args ((.sym Src32An group) (.sym Dsp- offset -u16)))
2533 (syntax (.str "${Dsp-" offset "-u16}[$Src32An" group "]"))
2534 (base-ifield (.sym f- base1 -11))
2535 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u16) (.sym Src32An group)))
2536 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -1) 0)))
2537 (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) (.sym Dsp- offset -u16)))
2538 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (.sym Src32An group) (.sym Dsp- offset -u16)))
2539; (getter (mem32 xmode (add (.sym Dsp- offset -u16) (.sym Src32An group))))
2540; (setter (set (mem32 xmode (add (.sym Dsp- offset -u16) (.sym Src32An group))) newval))
2541 )
2542 (define-derived-operand
2543 (name (.sym src32- offset -24-An-relative- group - xmode))
2544 (comment (.str "m32c dsp:16[An] relative destination " xmode))
2545 (attrs (machine 32))
2546 (mode xmode)
2547 (args ((.sym Src32An group) (.sym Dsp- offset -u24)))
2548 (syntax (.str "${Dsp-" offset "-u24}[$Src32An" group "]"))
2549 (base-ifield (.sym f- base1 -11))
2550 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u24) (.sym Src32An group)))
2551 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -1) 0)))
2552 (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) (.sym Dsp- offset -u24) ))
2553 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (.sym Src32An group) (.sym Dsp- offset -u24)))
2554; (getter (mem32 xmode (add (.sym Dsp- offset -u24) (.sym Src32An group))))
2555; (setter (set (mem32 xmode (add (.sym Dsp- offset -u24) (.sym Src32An group))) newval))
2556 )
2557 )
2558)
2559
2560(src32-relative-operand 16 Unprefixed 1 10 QI)
2561(src32-relative-operand 16 Unprefixed 1 10 HI)
2562(src32-relative-operand 16 Unprefixed 1 10 SI)
2563(src32-relative-operand 24 Prefixed 9 18 QI)
2564(src32-relative-operand 24 Prefixed 9 18 HI)
2565(src32-relative-operand 24 Prefixed 9 18 SI)
2566
2567;-------------------------------------------------------------
2568; Absolute address
2569;-------------------------------------------------------------
2570
2571(define-pmacro (src16-absolute xmode)
2572 (begin
2573 (define-derived-operand
2574 (name (.sym src16-16-16-absolute- xmode))
2575 (comment (.str "m16c absolute address " xmode))
2576 (attrs (machine 16))
2577 (mode xmode)
2578 (args (Dsp-16-u16))
2579 (syntax (.str "${Dsp-16-u16}"))
2580 (base-ifield f-8-4)
2581 (encoding (+ (f-8-4 #xF) Dsp-16-u16))
2582 (ifield-assertion (eq f-8-4 #xF))
2583 (getter (mem16 xmode Dsp-16-u16))
2584 (setter (set (mem16 xmode Dsp-16-u16) newval))
2585 )
2586 )
2587)
2588
2589(src16-absolute QI)
2590(src16-absolute HI)
2591
2592(define-pmacro (src32-absolute offset group base1 base2 xmode)
2593 (begin
2594 (define-derived-operand
2595 (name (.sym src32- offset -16-absolute- group - xmode))
2596 (comment (.str "m32c absolute address " xmode))
2597 (attrs (machine 32))
2598 (mode xmode)
2599 (args ((.sym Dsp- offset -u16)))
2600 (syntax (.str "${Dsp-" offset "-u16}"))
2601 (base-ifield (.sym f- base1 -11))
2602 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym Dsp- offset -u16)))
2603 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3)))
2604 (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) (.sym Dsp- offset -u16)))
2605 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) (.sym Dsp- offset -u16)))
2606; (getter (mem32 xmode (.sym Dsp- offset -u16)))
2607; (setter (set (mem32 xmode (.sym Dsp- offset -u16)) newval))
2608 )
2609 (define-derived-operand
2610 (name (.sym src32- offset -24-absolute- group - xmode))
2611 (comment (.str "m32c absolute address " xmode))
2612 (attrs (machine 32))
2613 (mode xmode)
2614 (args ((.sym Dsp- offset -u24)))
2615 (syntax (.str "${Dsp-" offset "-u24}"))
2616 (base-ifield (.sym f- base1 -11))
2617 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u24)))
2618 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2)))
2619 (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) (.sym Dsp- offset -u24)))
2620 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) (.sym Dsp- offset -u24)))
2621; (getter (mem32 xmode (.sym Dsp- offset -u24)))
2622; (setter (set (mem32 xmode (.sym Dsp- offset -u24)) newval))
2623 )
2624 )
2625)
2626
2627(src32-absolute 16 Unprefixed 1 10 QI)
2628(src32-absolute 16 Unprefixed 1 10 HI)
2629(src32-absolute 16 Unprefixed 1 10 SI)
2630(src32-absolute 24 Prefixed 9 18 QI)
2631(src32-absolute 24 Prefixed 9 18 HI)
2632(src32-absolute 24 Prefixed 9 18 SI)
2633
2634;-------------------------------------------------------------
2635; An indirect indirect
2636;
2637; Double indirect addressing uses the lower 3 bytes of the value stored
2638; at the address referenced by 'op' as the effective address.
2639;-------------------------------------------------------------
2640
2641(define-pmacro (indirect-addr op) (and USI (mem32 USI op) #x00ffffff))
2642
2643; (define-pmacro (src-An-indirect-indirect-operand xmode)
2644; (define-derived-operand
2645; (name (.sym src32-An-indirect-indirect- xmode))
2646; (comment (.str "m32c An indirect indirect destination " xmode))
2647; (attrs (machine 32))
2648; (mode xmode)
2649; (args (Src32AnPrefixed))
2650; (syntax (.str "[[$Src32AnPrefixed]]"))
2651; (base-ifield f-9-11)
2652; (encoding (+ (f-9-3 0) (f-18-1 0) Src32AnPrefixed))
2653; (ifield-assertion (andif (eq f-9-3 0) (eq f-18-1 0)))
2654; (getter (mem32 xmode (indirect-addr Src32AnPrefixed)))
2655; (setter (set (mem32 xmode (indirect-addr Src32AnPrefixed)) newval))
2656; )
2657; )
2658
2659; (src-An-indirect-indirect-operand QI)
2660; (src-An-indirect-indirect-operand HI)
2661; (src-An-indirect-indirect-operand SI)
2662
2663;-------------------------------------------------------------
2664; Relative indirect
2665;-------------------------------------------------------------
2666
2667(define-pmacro (src-relative-indirect-operand xmode)
2668 (begin
2669; (define-derived-operand
2670; (name (.sym src32-24-8-SB-relative-indirect- xmode))
2671; (comment (.str "m32c dsp:8[sb] relative source " xmode))
2672; (attrs (machine 32))
2673; (mode xmode)
2674; (args (Dsp-24-u8))
2675; (syntax "[${Dsp-24-u8}[sb]]")
2676; (base-ifield f-9-11)
2677; (encoding (+ (f-9-3 1) (f-18-2 2) Dsp-24-u8))
2678; (ifield-assertion (andif (eq f-9-3 1) (eq f-18-2 2)))
2679; (getter (mem32 xmode (indirect-addr (add Dsp-24-u8 (reg h-sb)))))
2680; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u8 (reg h-sb)))) newval))
2681; )
2682; (define-derived-operand
2683; (name (.sym src32-24-16-SB-relative-indirect- xmode))
2684; (comment (.str "m32c dsp:16[sb] relative source " xmode))
2685; (attrs (machine 32))
2686; (mode xmode)
2687; (args (Dsp-24-u16))
2688; (syntax "[${Dsp-24-u16}[sb]]")
2689; (base-ifield f-9-11)
2690; (encoding (+ (f-9-3 2) (f-18-2 2) Dsp-24-u16))
2691; (ifield-assertion (andif (eq f-9-3 2) (eq f-18-2 2)))
2692; (getter (mem32 xmode (indirect-addr (add Dsp-24-u16 (reg h-sb)))))
2693; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u16 (reg h-sb)))) newval))
2694; )
2695; (define-derived-operand
2696; (name (.sym src32-24-8-FB-relative-indirect- xmode))
2697; (comment (.str "m32c dsp:8[fb] relative source " xmode))
2698; (attrs (machine 32))
2699; (mode xmode)
2700; (args (Dsp-24-s8))
2701; (syntax "[${Dsp-24-s8}[fb]]")
2702; (base-ifield f-9-11)
2703; (encoding (+ (f-9-3 1) (f-18-2 3) Dsp-24-s8))
2704; (ifield-assertion (andif (eq f-9-3 1) (eq f-18-2 3)))
2705; (getter (mem32 xmode (indirect-addr (add Dsp-24-s8 (reg h-fb)))))
2706; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-s8 (reg h-fb)))) newval))
2707; )
2708; (define-derived-operand
2709; (name (.sym src32-24-16-FB-relative-indirect- xmode))
2710; (comment (.str "m32c dsp:16[fb] relative source " xmode))
2711; (attrs (machine 32))
2712; (mode xmode)
2713; (args (Dsp-24-s16))
2714; (syntax "[${Dsp-24-s16}[fb]]")
2715; (base-ifield f-9-11)
2716; (encoding (+ (f-9-3 2) (f-18-2 3) Dsp-24-s16))
2717; (ifield-assertion (andif (eq f-9-3 2) (eq f-18-2 3)))
2718; (getter (mem32 xmode (indirect-addr (add Dsp-24-s16 (reg h-fb)))))
2719; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-s16 (reg h-fb)))) newval))
2720; )
2721; (define-derived-operand
2722; (name (.sym src32-24-8-An-relative-indirect- xmode))
2723; (comment (.str "m32c dsp:8[An] relative indirect source " xmode))
2724; (attrs (machine 32))
2725; (mode xmode)
2726; (args (Src32AnPrefixed Dsp-24-u8))
2727; (syntax "[${Dsp-24-u8}[$Src32AnPrefixed]]")
2728; (base-ifield f-9-11)
2729; (encoding (+ (f-9-3 1) (f-18-1 0) Dsp-24-u8 Src32AnPrefixed))
2730; (ifield-assertion (andif (eq f-9-3 1) (eq f-18-1 0)))
2731; (getter (mem32 xmode (indirect-addr (add Dsp-24-u8 Src32AnPrefixed))))
2732; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u8 Src32AnPrefixed))) newval))
2733; )
2734; (define-derived-operand
2735; (name (.sym src32-24-16-An-relative-indirect- xmode))
2736; (comment (.str "m32c dsp:16[An] relative source " xmode))
2737; (attrs (machine 32))
2738; (mode xmode)
2739; (args (Src32AnPrefixed Dsp-24-u16))
2740; (syntax "[${Dsp-24-u16}[$Src32AnPrefixed]]")
2741; (base-ifield f-9-11)
2742; (encoding (+ (f-9-3 2) (f-18-1 0) Dsp-24-u16 Src32AnPrefixed))
2743; (ifield-assertion (andif (eq f-9-3 2) (eq f-18-1 0)))
2744; (getter (mem32 xmode (indirect-addr (add Dsp-24-u16 Src32AnPrefixed))))
2745; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u16 Src32AnPrefixed))) newval))
2746; )
2747; (define-derived-operand
2748; (name (.sym src32-24-24-An-relative-indirect- xmode))
2749; (comment (.str "m32c dsp:24[An] relative source " xmode))
2750; (attrs (machine 32))
2751; (mode xmode)
2752; (args (Src32AnPrefixed Dsp-24-u24))
2753; (syntax "[${Dsp-24-u24}[$Src32AnPrefixed]]")
2754; (base-ifield f-9-11)
2755; (encoding (+ (f-9-3 3) (f-18-1 0) Dsp-24-u24 Src32AnPrefixed))
2756; (ifield-assertion (andif (eq f-9-3 3) (eq f-18-1 0)))
2757; (getter (mem32 xmode (indirect-addr (add Dsp-24-u24 Src32AnPrefixed))))
2758; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u24 Src32AnPrefixed))) newval))
2759; )
2760 )
2761)
2762
2763; (src-relative-indirect-operand QI)
2764; (src-relative-indirect-operand HI)
2765; (src-relative-indirect-operand SI)
2766
2767;-------------------------------------------------------------
2768; Absolute Indirect address
2769;-------------------------------------------------------------
2770
2771(define-pmacro (src32-absolute-indirect offset base1 base2 xmode)
2772 (begin
2773; (define-derived-operand
2774; (name (.sym src32- offset -16-absolute-indirect-derived- xmode))
2775; (comment (.str "m32c absolute indirect address " xmode))
2776; (attrs (machine 32))
2777; (mode xmode)
2778; (args ((.sym Dsp- offset -u16)))
2779; (syntax (.str "[${Dsp-" offset "-u16}]"))
2780; (base-ifield (.sym f- base1 -11))
2781; (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym Dsp- offset -u16)))
2782; (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3)))
2783; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u16))))
2784; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u16))) newval))
2785; )
2786; (define-derived-operand
2787; (name (.sym src32- offset -24-absolute-indirect-derived- xmode))
2788; (comment (.str "m32c absolute indirect address " xmode))
2789; (attrs (machine 32))
2790; (mode xmode)
2791; (args ((.sym Dsp- offset -u24)))
2792; (syntax (.str "[${Dsp-" offset "-u24}]"))
2793; (base-ifield (.sym f- base1 -11))
2794; (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u24)))
2795; (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2)))
2796; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u24))))
2797; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u24))) newval))
2798; )
2799 )
2800)
2801
2802(src32-absolute-indirect 24 9 18 QI)
2803(src32-absolute-indirect 24 9 18 HI)
2804(src32-absolute-indirect 24 9 18 SI)
2805
2806;-------------------------------------------------------------
2807; Register relative source operands for short format insns
2808;-------------------------------------------------------------
2809
2810(define-pmacro (src-2-S-operands mach xmode base opc1 opc2 opc3)
2811 (begin
2812 (define-derived-operand
2813 (name (.sym src mach -2-S-8-SB-relative- xmode))
2814 (comment (.str "m" mach "c SB relative address"))
2815 (attrs (machine mach))
2816 (mode xmode)
2817 (args (Dsp-8-u8))
2818 (syntax "${Dsp-8-u8}[sb]")
2819 (base-ifield (.sym f- base -2))
2820 (encoding (+ ((.sym f- base -2) opc1) Dsp-8-u8))
2821 (ifield-assertion (eq (.sym f- base -2) opc1))
2822 (getter (c-call xmode (.str "operand_getter_" xmode) sb Dsp-8-u8))
2823 (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb Dsp-8-u8))
2824; (getter (mem-mach mach xmode (indirect-addr (add (reg h-sb) Dsp-8-u8))))
2825; (setter (set (mem-mach mach xmode (indirect-addr (add (reg h-sb) Dsp-8-u8))) newval))
2826 )
2827 (define-derived-operand
2828 (name (.sym src mach -2-S-8-FB-relative- xmode))
2829 (comment (.str "m" mach "c FB relative address"))
2830 (attrs (machine mach))
2831 (mode xmode)
2832 (args (Dsp-8-s8))
2833 (syntax "${Dsp-8-s8}[fb]")
2834 (base-ifield (.sym f- base -2))
2835 (encoding (+ ((.sym f- base -2) opc2) Dsp-8-s8))
2836 (ifield-assertion (eq (.sym f- base -2) opc2))
2837 (getter (c-call xmode (.str "operand_getter_" xmode) fb Dsp-8-s8))
2838 (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb Dsp-8-s8))
2839; (getter (mem-mach mach xmode (indirect-addr (add (reg h-fb) Dsp-8-s8))))
2840; (setter (set (mem-mach mach xmode (indirect-addr (add (reg h-fb) Dsp-8-s8))) newval))
2841 )
2842 (define-derived-operand
2843 (name (.sym src mach -2-S-16-absolute- xmode))
2844 (comment (.str "m" mach "c absolute address"))
2845 (attrs (machine mach))
2846 (mode xmode)
2847 (args (Dsp-8-u16))
2848 (syntax "${Dsp-8-u16}")
2849 (base-ifield (.sym f- base -2))
2850 (encoding (+ ((.sym f- base -2) opc3) Dsp-8-u16))
2851 (ifield-assertion (eq (.sym f- base -2) opc3))
2852 (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) Dsp-8-u16))
2853 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) Dsp-8-u16))
2854; (getter (mem-mach mach xmode Dsp-8-u16))
2855; (setter (set (mem-mach mach xmode Dsp-8-u16) newval))
2856 )
2857 )
2858)
2859
2860(src-2-S-operands 16 QI 6 1 2 3)
2861(src-2-S-operands 32 QI 2 2 3 1)
2862(src-2-S-operands 32 HI 2 2 3 1)
2863
2864;=============================================================
2865; Derived Operands
2866;-------------------------------------------------------------
2867; Destination
2868;-------------------------------------------------------------
2869; Rn direct
2870;-------------------------------------------------------------
2871
2872(define-pmacro (dst16-Rn-direct-operand xmode)
2873 (begin
2874 (define-derived-operand
2875 (name (.sym dst16-Rn-direct- xmode))
2876 (comment (.str "m16c Rn direct destination " xmode))
2877 (attrs (machine 16))
2878 (mode xmode)
2879 (args ((.sym Dst16Rn xmode)))
2880 (syntax (.str "$Dst16Rn" xmode))
2881 (base-ifield f-12-4)
2882 (encoding (+ (f-12-2 0) (.sym Dst16Rn xmode)))
2883 (ifield-assertion (eq f-12-2 0))
2884 (getter (trunc xmode (.sym Dst16Rn xmode)))
2885 (setter (set (.sym Dst16Rn xmode) newval))
2886 )
2887 )
2888)
2889
2890(dst16-Rn-direct-operand QI)
2891(dst16-Rn-direct-operand HI)
2892(dst16-Rn-direct-operand SI)
2893
2894(define-derived-operand
2895 (name dst16-Rn-direct-Ext-QI)
2896 (comment "m16c Rn direct destination QI")
2897 (attrs (machine 16))
2898 (mode HI)
2899 (args (Dst16RnExtQI))
2900 (syntax "$Dst16RnExtQI")
2901 (base-ifield f-12-4)
2902 (encoding (+ (f-12-2 0) Dst16RnExtQI (f-15-1 0)))
2903 (ifield-assertion (andif (eq f-12-2 0) (eq f-15-1 0)))
2904 (getter (trunc QI (.sym Dst16RnExtQI)))
2905 (setter (set Dst16RnExtQI newval))
2906)
2907
2908(define-pmacro (dst32-Rn-direct-operand group base xmode)
2909 (begin
2910 (define-derived-operand
2911 (name (.sym dst32-Rn-direct- group - xmode))
2912 (comment (.str "m32c Rn direct destination " xmode))
2913 (attrs (machine 32))
2914 (mode xmode)
2915 (args ((.sym Dst32Rn group xmode)))
2916 (syntax (.str "$Dst32Rn" group xmode))
2917 (base-ifield (.sym f- base -6))
2918 (encoding (+ ((.sym f- base -3) 4) (.sym Dst32Rn group xmode)))
2919 (ifield-assertion (eq (.sym f- base -3) 4))
2920 (getter (trunc xmode (.sym Dst32Rn group xmode)))
2921 (setter (set (.sym Dst32Rn group xmode) newval))
2922 )
2923 )
2924)
2925
2926(dst32-Rn-direct-operand Unprefixed 4 QI)
2927(dst32-Rn-direct-operand Prefixed 12 QI)
2928(dst32-Rn-direct-operand Unprefixed 4 HI)
2929(dst32-Rn-direct-operand Prefixed 12 HI)
2930(dst32-Rn-direct-operand Unprefixed 4 SI)
2931(dst32-Rn-direct-operand Prefixed 12 SI)
2932
2933(define-pmacro (dst32-Rn-direct-Ext-operand group base1 base2 smode dmode)
2934 (begin
2935 (define-derived-operand
2936 (name (.sym dst32-Rn-direct- group - smode))
2937 (comment (.str "m32c Rn direct destination " smode))
2938 (attrs (machine 32))
2939 (mode dmode)
2940 (args ((.sym Dst32Rn group smode)))
2941 (syntax (.str "$Dst32Rn" group smode))
2942 (base-ifield (.sym f- base1 -6))
2943 (encoding (+ ((.sym f- base1 -3) 4) ((.sym f- base2 -1) 1) (.sym Dst32Rn group smode)))
2944 (ifield-assertion (andif (eq (.sym f- base1 -3) 4) (eq (.sym f- base2 -1) 1)))
2945 (getter (trunc smode (.sym Dst32Rn group smode)))
2946 (setter (set (.sym Dst32Rn group smode) newval))
2947 )
2948 )
2949)
2950
2951(dst32-Rn-direct-Ext-operand ExtUnprefixed 4 8 QI HI)
2952(dst32-Rn-direct-Ext-operand ExtUnprefixed 4 8 HI SI)
2953
2954(define-derived-operand
2955 (name dst32-R3-direct-Unprefixed-HI)
2956 (comment "m32c R3 direct HI")
2957 (attrs (machine 32))
2958 (mode HI)
2959 (args (R3))
2960 (syntax "$R3")
2961 (base-ifield f-4-6)
2962 (encoding (+ (f-4-3 4) (f-8-2 #x1)))
2963 (ifield-assertion (andif (eq f-4-3 4) (eq f-8-2 #x1)))
2964 (getter (trunc HI R3))
2965 (setter (set R3 newval))
2966)
2967;-------------------------------------------------------------
2968; An direct
2969;-------------------------------------------------------------
2970
2971(define-pmacro (dst16-An-direct-operand xmode)
2972 (begin
2973 (define-derived-operand
2974 (name (.sym dst16-An-direct- xmode))
2975 (comment (.str "m16c An direct destination " xmode))
2976 (attrs (machine 16))
2977 (mode xmode)
2978 (args ((.sym Dst16An xmode)))
2979 (syntax (.str "$Dst16An" xmode))
2980 (base-ifield f-12-4)
2981 (encoding (+ (f-12-2 1) (f-14-1 0) (.sym Dst16An xmode)))
2982 (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 0)))
2983 (getter (trunc xmode (.sym Dst16An xmode)))
2984 (setter (set (.sym Dst16An xmode) newval))
2985 )
2986 )
2987)
2988
2989(dst16-An-direct-operand QI)
2990(dst16-An-direct-operand HI)
2991(dst16-An-direct-operand SI)
2992
2993(define-pmacro (dst32-An-direct-operand group base1 base2 xmode)
2994 (begin
2995 (define-derived-operand
2996 (name (.sym dst32-An-direct- group - xmode))
2997 (comment (.str "m32c An direct destination " xmode))
2998 (attrs (machine 32))
2999 (mode xmode)
3000 (args ((.sym Dst32An group xmode)))
3001 (syntax (.str "$Dst32An" group xmode))
3002 (base-ifield (.sym f- base1 -6))
3003 (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 1) (.sym Dst32An group xmode)))
3004 (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 1)))
3005 (getter (trunc xmode (.sym Dst32An group xmode)))
3006 (setter (set (.sym Dst32An group xmode) newval))
3007 )
3008 )
3009)
3010
3011(dst32-An-direct-operand Unprefixed 4 8 QI)
3012(dst32-An-direct-operand Prefixed 12 16 QI)
3013(dst32-An-direct-operand Unprefixed 4 8 HI)
3014(dst32-An-direct-operand Prefixed 12 16 HI)
3015(dst32-An-direct-operand Unprefixed 4 8 SI)
3016(dst32-An-direct-operand Prefixed 12 16 SI)
3017
3018;-------------------------------------------------------------
3019; An indirect
3020;-------------------------------------------------------------
3021
3022(define-pmacro (dst16-An-indirect-operand xmode)
3023 (begin
3024 (define-derived-operand
3025 (name (.sym dst16-An-indirect- xmode))
3026 (comment (.str "m16c An indirect destination " xmode))
3027 (attrs (machine 16))
3028 (mode xmode)
3029 (args (Dst16An))
3030 (syntax "[$Dst16An]")
3031 (base-ifield f-12-4)
3032 (encoding (+ (f-12-2 1) (f-14-1 1) Dst16An))
3033 (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 1)))
3034 (getter (mem16 xmode Dst16An))
3035 (setter (set (mem16 xmode Dst16An) newval))
3036 )
3037 )
3038)
3039
3040(dst16-An-indirect-operand QI)
3041(dst16-An-indirect-operand HI)
3042(dst16-An-indirect-operand SI)
3043
3044(define-derived-operand
3045 (name dst16-An-indirect-Ext-QI)
3046 (comment "m16c An indirect destination QI")
3047 (attrs (machine 16))
3048 (mode HI)
3049 (args (Dst16An))
3050 (syntax "[$Dst16An]")
3051 (base-ifield f-12-4)
3052 (encoding (+ (f-12-2 1) (f-14-1 1) Dst16An))
3053 (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 1)))
3054 (getter (mem16 QI Dst16An))
3055 (setter (set (mem16 HI Dst16An) newval))
3056)
3057
3058(define-pmacro (dst32-An-indirect-operand group base1 base2 smode dmode)
3059 (begin
3060 (define-derived-operand
3061 (name (.sym dst32-An-indirect- group - smode))
3062 (comment (.str "m32c An indirect destination " smode))
3063 (attrs (machine 32))
3064 (mode dmode)
3065 (args ((.sym Dst32An group)))
3066 (syntax (.str "[$Dst32An" group "]"))
3067 (base-ifield (.sym f- base1 -6))
3068 (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 0) (.sym Dst32An group)))
3069 (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 0)))
3070 (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group)
3071 (const 0)))
3072 (setter (c-call DFLT (.str "operand_setter_" dmode) newval
3073 (.sym Dst32An group) (const 0)))
3074; (getter (mem32 smode (.sym Dst32An group)))
3075; (setter (set (mem32 dmode (.sym Dst32An group)) newval))
3076 )
3077 )
3078)
3079
3080(dst32-An-indirect-operand Unprefixed 4 8 QI QI)
3081(dst32-An-indirect-operand Prefixed 12 16 QI QI)
3082(dst32-An-indirect-operand Unprefixed 4 8 HI HI)
3083(dst32-An-indirect-operand Prefixed 12 16 HI HI)
3084(dst32-An-indirect-operand Unprefixed 4 8 SI SI)
3085(dst32-An-indirect-operand Prefixed 12 16 SI SI)
3086(dst32-An-indirect-operand ExtUnprefixed 4 8 QI HI)
3087(dst32-An-indirect-operand ExtUnprefixed 4 8 HI SI)
3088
3089;-------------------------------------------------------------
3090; dsp:d[r] relative
3091;-------------------------------------------------------------
3092
3093(define-pmacro (dst16-relative-operand offset xmode)
3094 (begin
3095 (define-derived-operand
3096 (name (.sym dst16- offset -8-SB-relative- xmode))
3097 (comment (.str "m16c dsp:8[sb] relative destination " xmode))
3098 (attrs (machine 16))
3099 (mode xmode)
3100 (args ((.sym Dsp- offset -u8)))
3101 (syntax (.str "${Dsp-" offset "-u8}[sb]"))
3102 (base-ifield f-12-4)
3103 (encoding (+ (f-12-4 #xA) (.sym Dsp- offset -u8)))
3104 (ifield-assertion (eq f-12-4 #xA))
3105 (getter (mem16 xmode (add (.sym Dsp- offset -u8) (reg h-sb))))
3106 (setter (set (mem16 xmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval))
3107 )
3108 (define-derived-operand
3109 (name (.sym dst16- offset -16-SB-relative- xmode))
3110 (comment (.str "m16c dsp:16[sb] relative destination " xmode))
3111 (attrs (machine 16))
3112 (mode xmode)
3113 (args ((.sym Dsp- offset -u16)))
3114 (syntax (.str "${Dsp-" offset "-u16}[sb]"))
3115 (base-ifield f-12-4)
3116 (encoding (+ (f-12-4 #xE) (.sym Dsp- offset -u16)))
3117 (ifield-assertion (eq f-12-4 #xE))
3118 (getter (mem16 xmode (add (.sym Dsp- offset -u16) (reg h-sb))))
3119 (setter (set (mem16 xmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval))
3120 )
3121 (define-derived-operand
3122 (name (.sym dst16- offset -8-FB-relative- xmode))
3123 (comment (.str "m16c dsp:8[fb] relative destination " xmode))
3124 (attrs (machine 16))
3125 (mode xmode)
3126 (args ((.sym Dsp- offset -s8)))
3127 (syntax (.str "${Dsp-" offset "-s8}[fb]"))
3128 (base-ifield f-12-4)
3129 (encoding (+ (f-12-4 #xB) (.sym Dsp- offset -s8)))
3130 (ifield-assertion (eq f-12-4 #xB))
3131 (getter (mem16 xmode (add (.sym Dsp- offset -s8) (reg h-fb))))
3132 (setter (set (mem16 xmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval))
3133 )
3134 (define-derived-operand
3135 (name (.sym dst16- offset -8-An-relative- xmode))
3136 (comment (.str "m16c dsp:8[An] relative destination " xmode))
3137 (attrs (machine 16))
3138 (mode xmode)
3139 (args (Dst16An (.sym Dsp- offset -u8)))
3140 (syntax (.str "${Dsp-" offset "-u8}[$Dst16An]"))
3141 (base-ifield f-12-4)
3142 (encoding (+ (f-12-2 2) (f-14-1 0) (.sym Dsp- offset -u8) Dst16An))
3143 (ifield-assertion (andif (eq f-12-2 2) (eq f-14-1 0)))
3144 (getter (mem16 xmode (add (.sym Dsp- offset -u8) Dst16An)))
3145 (setter (set (mem16 xmode (add (.sym Dsp- offset -u8) Dst16An)) newval))
3146 )
3147 (define-derived-operand
3148 (name (.sym dst16- offset -16-An-relative- xmode))
3149 (comment (.str "m16c dsp:16[An] relative destination " xmode))
3150 (attrs (machine 16))
3151 (mode xmode)
3152 (args (Dst16An (.sym Dsp- offset -u16)))
3153 (syntax (.str "${Dsp-" offset "-u16}[$Dst16An]"))
3154 (base-ifield f-12-4)
3155 (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u16) Dst16An))
3156 (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0)))
3157 (getter (mem16 xmode (add (.sym Dsp- offset -u16) Dst16An)))
3158 (setter (set (mem16 xmode (add (.sym Dsp- offset -u16) Dst16An)) newval))
3159 )
3160 )
3161)
3162
3163(dst16-relative-operand 16 QI)
3164(dst16-relative-operand 24 QI)
3165(dst16-relative-operand 32 QI)
3166(dst16-relative-operand 40 QI)
3167(dst16-relative-operand 48 QI)
3168(dst16-relative-operand 16 HI)
3169(dst16-relative-operand 24 HI)
3170(dst16-relative-operand 32 HI)
3171(dst16-relative-operand 40 HI)
3172(dst16-relative-operand 48 HI)
3173(dst16-relative-operand 16 SI)
3174(dst16-relative-operand 24 SI)
3175(dst16-relative-operand 32 SI)
3176(dst16-relative-operand 40 SI)
3177(dst16-relative-operand 48 SI)
3178
3179(define-pmacro (dst16-relative-Ext-operand offset smode dmode)
3180 (begin
3181 (define-derived-operand
3182 (name (.sym dst16- offset -8-SB-relative-Ext- smode))
3183 (comment (.str "m16c dsp:8[sb] relative destination " smode))
3184 (attrs (machine 16))
3185 (mode dmode)
3186 (args ((.sym Dsp- offset -u8)))
3187 (syntax (.str "${Dsp-" offset "-u8}[sb]"))
3188 (base-ifield f-12-4)
3189 (encoding (+ (f-12-4 #xA) (.sym Dsp- offset -u8)))
3190 (ifield-assertion (eq f-12-4 #xA))
3191 (getter (mem16 smode (add (.sym Dsp- offset -u8) (reg h-sb))))
3192 (setter (set (mem16 dmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval))
3193 )
3194 (define-derived-operand
3195 (name (.sym dst16- offset -16-SB-relative-Ext- smode))
3196 (comment (.str "m16c dsp:16[sb] relative destination " smode))
3197 (attrs (machine 16))
3198 (mode dmode)
3199 (args ((.sym Dsp- offset -u16)))
3200 (syntax (.str "${Dsp-" offset "-u16}[sb]"))
3201 (base-ifield f-12-4)
3202 (encoding (+ (f-12-4 #xE) (.sym Dsp- offset -u16)))
3203 (ifield-assertion (eq f-12-4 #xE))
3204 (getter (mem16 smode (add (.sym Dsp- offset -u16) (reg h-sb))))
3205 (setter (set (mem16 dmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval))
3206 )
3207 (define-derived-operand
3208 (name (.sym dst16- offset -8-FB-relative-Ext- smode))
3209 (comment (.str "m16c dsp:8[fb] relative destination " smode))
3210 (attrs (machine 16))
3211 (mode dmode)
3212 (args ((.sym Dsp- offset -s8)))
3213 (syntax (.str "${Dsp-" offset "-s8}[fb]"))
3214 (base-ifield f-12-4)
3215 (encoding (+ (f-12-4 #xB) (.sym Dsp- offset -s8)))
3216 (ifield-assertion (eq f-12-4 #xB))
3217 (getter (mem16 smode (add (.sym Dsp- offset -s8) (reg h-fb))))
3218 (setter (set (mem16 dmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval))
3219 )
3220 (define-derived-operand
3221 (name (.sym dst16- offset -8-An-relative-Ext- smode))
3222 (comment (.str "m16c dsp:8[An] relative destination " smode))
3223 (attrs (machine 16))
3224 (mode dmode)
3225 (args (Dst16An (.sym Dsp- offset -u8)))
3226 (syntax (.str "${Dsp-" offset "-u8}[$Dst16An]"))
3227 (base-ifield f-12-4)
3228 (encoding (+ (f-12-2 2) (f-14-1 0) (.sym Dsp- offset -u8) Dst16An))
3229 (ifield-assertion (andif (eq f-12-2 2) (eq f-14-1 0)))
3230 (getter (mem16 smode (add (.sym Dsp- offset -u8) Dst16An)))
3231 (setter (set (mem16 dmode (add (.sym Dsp- offset -u8) Dst16An)) newval))
3232 )
3233 (define-derived-operand
3234 (name (.sym dst16- offset -16-An-relative-Ext- smode))
3235 (comment (.str "m16c dsp:16[An] relative destination " smode))
3236 (attrs (machine 16))
3237 (mode dmode)
3238 (args (Dst16An (.sym Dsp- offset -u16)))
3239 (syntax (.str "${Dsp-" offset "-u16}[$Dst16An]"))
3240 (base-ifield f-12-4)
3241 (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u16) Dst16An))
3242 (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0)))
3243 (getter (mem16 smode (add (.sym Dsp- offset -u16) Dst16An)))
3244 (setter (set (mem16 dmode (add (.sym Dsp- offset -u16) Dst16An)) newval))
3245 )
3246 )
3247)
3248
3249(dst16-relative-Ext-operand 16 QI HI)
3250
3251(define-pmacro (dst32-relative-operand offset group base1 base2 smode dmode)
3252 (begin
3253 (define-derived-operand
3254 (name (.sym dst32- offset -8-SB-relative- group - smode))
3255 (comment (.str "m32c dsp:8[sb] relative destination " smode))
3256 (attrs (machine 32))
3257 (mode dmode)
3258 (args ((.sym Dsp- offset -u8)))
3259 (syntax (.str "${Dsp-" offset "-u8}[sb]"))
3260 (base-ifield (.sym f- base1 -6))
3261 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u8)))
3262 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 2)))
3263 (getter (c-call dmode (.str "operand_getter_" dmode) sb (.sym Dsp- offset -u8)))
3264 (setter (c-call DFLT (.str "operand_setter_" dmode) newval sb (.sym Dsp- offset -u8)))
3265; (getter (mem32 smode (add (.sym Dsp- offset -u8) (reg h-sb))))
3266; (setter (set (mem32 dmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval))
3267 )
3268 (define-derived-operand
3269 (name (.sym dst32- offset -16-SB-relative- group - smode))
3270 (comment (.str "m32c dsp:16[sb] relative destination " smode))
3271 (attrs (machine 32))
3272 (mode dmode)
3273 (args ((.sym Dsp- offset -u16)))
3274 (syntax (.str "${Dsp-" offset "-u16}[sb]"))
3275 (base-ifield (.sym f- base1 -6))
3276 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u16)))
3277 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 2)))
3278 (getter (c-call dmode (.str "operand_getter_" dmode) sb (.sym Dsp- offset -u16)))
3279 (setter (c-call DFLT (.str "operand_setter_" dmode) newval sb (.sym Dsp- offset -u16)))
3280; (getter (mem32 smode (add (.sym Dsp- offset -u16) (reg h-sb))))
3281; (setter (set (mem32 dmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval))
3282 )
3283 (define-derived-operand
3284 (name (.sym dst32- offset -8-FB-relative- group - smode))
3285 (comment (.str "m32c dsp:8[fb] relative destination " smode))
3286 (attrs (machine 32))
3287 (mode dmode)
3288 (args ((.sym Dsp- offset -s8)))
3289 (syntax (.str "${Dsp-" offset "-s8}[fb]"))
3290 (base-ifield (.sym f- base1 -6))
3291 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s8)))
3292 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 3)))
3293 (getter (c-call dmode (.str "operand_getter_" dmode) fb (.sym Dsp- offset -s8)))
3294 (setter (c-call DFLT (.str "operand_setter_" dmode) newval fb (.sym Dsp- offset -s8)))
3295; (getter (mem32 smode (add (.sym Dsp- offset -s8) (reg h-fb))))
3296; (setter (set (mem32 dmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval))
3297 )
3298 (define-derived-operand
3299 (name (.sym dst32- offset -16-FB-relative- group - smode))
3300 (comment (.str "m32c dsp:16[fb] relative destination " smode))
3301 (attrs (machine 32))
3302 (mode dmode)
3303 (args ((.sym Dsp- offset -s16)))
3304 (syntax (.str "${Dsp-" offset "-s16}[fb]"))
3305 (base-ifield (.sym f- base1 -6))
3306 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s16)))
3307 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 3)))
3308 (getter (c-call dmode (.str "operand_getter_" dmode) fb (.sym Dsp- offset -s16)))
3309 (setter (c-call DFLT (.str "operand_setter_" dmode) newval fb (.sym Dsp- offset -s16)))
3310; (getter (mem32 smode (add (.sym Dsp- offset -s16) (reg h-fb))))
3311; (setter (set (mem32 dmode (add (.sym Dsp- offset -s16) (reg h-fb))) newval))
3312 )
3313 (define-derived-operand
3314 (name (.sym dst32- offset -8-An-relative- group - smode))
3315 (comment (.str "m32c dsp:8[An] relative destination " smode))
3316 (attrs (machine 32))
3317 (mode dmode)
3318 (args ((.sym Dst32An group) (.sym Dsp- offset -u8)))
3319 (syntax (.str "${Dsp-" offset "-u8}[$Dst32An" group "]"))
3320 (base-ifield (.sym f- base1 -6))
3321 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u8) (.sym Dst32An group)))
3322 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -1) 0)))
3323 (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) (.sym Dsp- offset -u8)))
3324 (setter (c-call DFLT (.str "operand_setter_" dmode) newval (.sym Dst32An group) (.sym Dsp- offset -u8)))
3325; (getter (mem32 smode (add (.sym Dsp- offset -u8) (.sym Dst32An group))))
3326; (setter (set (mem32 dmode (add (.sym Dsp- offset -u8) (.sym Dst32An group))) newval))
3327 )
3328 (define-derived-operand
3329 (name (.sym dst32- offset -16-An-relative- group - smode))
3330 (comment (.str "m32c dsp:16[An] relative destination " smode))
3331 (attrs (machine 32))
3332 (mode dmode)
3333 (args ((.sym Dst32An group) (.sym Dsp- offset -u16)))
3334 (syntax (.str "${Dsp-" offset "-u16}[$Dst32An" group "]"))
3335 (base-ifield (.sym f- base1 -6))
3336 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u16) (.sym Dst32An group)))
3337 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -1) 0)))
3338 (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) (.sym Dsp- offset -u16)))
3339 (setter (c-call DFLT (.str "operand_setter_" dmode) newval (.sym Dst32An group) (.sym Dsp- offset -u16)))
3340; (getter (mem32 smode (add (.sym Dsp- offset -u16) (.sym Dst32An group))))
3341; (setter (set (mem32 dmode (add (.sym Dsp- offset -u16) (.sym Dst32An group))) newval))
3342 )
3343 (define-derived-operand
3344 (name (.sym dst32- offset -24-An-relative- group - smode))
3345 (comment (.str "m32c dsp:16[An] relative destination " smode))
3346 (attrs (machine 32))
3347 (mode dmode)
3348 (args ((.sym Dst32An group) (.sym Dsp- offset -u24)))
3349 (syntax (.str "${Dsp-" offset "-u24}[$Dst32An" group "]"))
3350 (base-ifield (.sym f- base1 -6))
3351 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u24) (.sym Dst32An group)))
3352 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -1) 0)))
3353 (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) (.sym Dsp- offset -u24)))
3354 (setter (c-call DFLT (.str "operand_setter_" dmode) newval (.sym Dst32An group) (.sym Dsp- offset -u24)))
3355; (getter (mem32 smode (add (.sym Dsp- offset -u24) (.sym Dst32An group))))
3356; (setter (set (mem32 dmode (add (.sym Dsp- offset -u24) (.sym Dst32An group))) newval))
3357 )
3358 )
3359)
3360
3361(dst32-relative-operand 16 Unprefixed 4 8 QI QI)
3362(dst32-relative-operand 24 Unprefixed 4 8 QI QI)
3363(dst32-relative-operand 32 Unprefixed 4 8 QI QI)
3364(dst32-relative-operand 40 Unprefixed 4 8 QI QI)
3365(dst32-relative-operand 16 Unprefixed 4 8 HI HI)
3366(dst32-relative-operand 24 Unprefixed 4 8 HI HI)
3367(dst32-relative-operand 32 Unprefixed 4 8 HI HI)
3368(dst32-relative-operand 40 Unprefixed 4 8 HI HI)
3369(dst32-relative-operand 16 Unprefixed 4 8 SI SI)
3370(dst32-relative-operand 24 Unprefixed 4 8 SI SI)
3371(dst32-relative-operand 32 Unprefixed 4 8 SI SI)
3372(dst32-relative-operand 40 Unprefixed 4 8 SI SI)
3373
3374(dst32-relative-operand 24 Prefixed 12 16 QI QI)
3375(dst32-relative-operand 32 Prefixed 12 16 QI QI)
3376(dst32-relative-operand 40 Prefixed 12 16 QI QI)
3377(dst32-relative-operand 48 Prefixed 12 16 QI QI)
3378(dst32-relative-operand 24 Prefixed 12 16 HI HI)
3379(dst32-relative-operand 32 Prefixed 12 16 HI HI)
3380(dst32-relative-operand 40 Prefixed 12 16 HI HI)
3381(dst32-relative-operand 48 Prefixed 12 16 HI HI)
3382(dst32-relative-operand 24 Prefixed 12 16 SI SI)
3383(dst32-relative-operand 32 Prefixed 12 16 SI SI)
3384(dst32-relative-operand 40 Prefixed 12 16 SI SI)
3385(dst32-relative-operand 48 Prefixed 12 16 SI SI)
3386
3387(dst32-relative-operand 16 ExtUnprefixed 4 8 QI HI)
3388(dst32-relative-operand 16 ExtUnprefixed 4 8 HI SI)
3389
3390;-------------------------------------------------------------
3391; Absolute address
3392;-------------------------------------------------------------
3393
3394(define-pmacro (dst16-absolute offset xmode)
3395 (begin
3396 (define-derived-operand
3397 (name (.sym dst16- offset -16-absolute- xmode))
3398 (comment (.str "m16c absolute address " xmode))
3399 (attrs (machine 16))
3400 (mode xmode)
3401 (args ((.sym Dsp- offset -u16)))
3402 (syntax (.str "${Dsp-" offset "-u16}"))
3403 (base-ifield f-12-4)
3404 (encoding (+ (f-12-4 #xF) (.sym Dsp- offset -u16)))
3405 (ifield-assertion (eq f-12-4 #xF))
3406 (getter (mem16 xmode (.sym Dsp- offset -u16)))
3407 (setter (set (mem16 xmode (.sym Dsp- offset -u16)) newval))
3408 )
3409 )
3410)
3411
3412(dst16-absolute 16 QI)
3413(dst16-absolute 24 QI)
3414(dst16-absolute 32 QI)
3415(dst16-absolute 40 QI)
3416(dst16-absolute 48 QI)
3417(dst16-absolute 16 HI)
3418(dst16-absolute 24 HI)
3419(dst16-absolute 32 HI)
3420(dst16-absolute 40 HI)
3421(dst16-absolute 48 HI)
3422(dst16-absolute 16 SI)
3423(dst16-absolute 24 SI)
3424(dst16-absolute 32 SI)
3425(dst16-absolute 40 SI)
3426(dst16-absolute 48 SI)
3427
3428(define-derived-operand
3429 (name dst16-16-16-absolute-Ext-QI)
3430 (comment "m16c absolute address QI")
3431 (attrs (machine 16))
3432 (mode HI)
3433 (args (Dsp-16-u16))
3434 (syntax "${Dsp-16-u16}")
3435 (base-ifield f-12-4)
3436 (encoding (+ (f-12-4 #xF) Dsp-16-u16))
3437 (ifield-assertion (eq f-12-4 #xF))
3438 (getter (mem16 QI Dsp-16-u16))
3439 (setter (set (mem16 HI Dsp-16-u16) newval))
3440)
3441
3442(define-pmacro (dst32-absolute offset group base1 base2 smode dmode)
3443 (begin
3444 (define-derived-operand
3445 (name (.sym dst32- offset -16-absolute- group - smode))
3446 (comment (.str "m32c absolute address " smode))
3447 (attrs (machine 32))
3448 (mode dmode)
3449 (args ((.sym Dsp- offset -u16)))
3450 (syntax (.str "${Dsp-" offset "-u16}"))
3451 (base-ifield (.sym f- base1 -6))
3452 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym Dsp- offset -u16)))
3453 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3)))
3454 (getter (c-call smode (.str "operand_getter_" smode) (const 0) (.sym Dsp- offset -u16)))
3455 (setter (c-call DFLT (.str "operand_setter_" dmode) newval (const 0) (.sym Dsp- offset -u16)))
3456; (getter (mem32 smode (.sym Dsp- offset -u16)))
3457; (setter (set (mem32 dmode (.sym Dsp- offset -u16)) newval))
3458 )
3459 (define-derived-operand
3460 (name (.sym dst32- offset -24-absolute- group - smode))
3461 (comment (.str "m32c absolute address " smode))
3462 (attrs (machine 32))
3463 (mode dmode)
3464 (args ((.sym Dsp- offset -u24)))
3465 (syntax (.str "${Dsp-" offset "-u24}"))
3466 (base-ifield (.sym f- base1 -6))
3467 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u24)))
3468 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2)))
3469 (getter (c-call smode (.str "operand_getter_" smode) (const 0) (.sym Dsp- offset -u24)))
3470 (setter (c-call DFLT (.str "operand_setter_" dmode) newval (const 0) (.sym Dsp- offset -u24)))
3471; (getter (mem32 smode (.sym Dsp- offset -u24)))
3472; (setter (set (mem32 dmode (.sym Dsp- offset -u24)) newval))
3473 )
3474 )
3475)
3476
3477(dst32-absolute 16 Unprefixed 4 8 QI QI)
3478(dst32-absolute 24 Unprefixed 4 8 QI QI)
3479(dst32-absolute 32 Unprefixed 4 8 QI QI)
3480(dst32-absolute 40 Unprefixed 4 8 QI QI)
3481(dst32-absolute 16 Unprefixed 4 8 HI HI)
3482(dst32-absolute 24 Unprefixed 4 8 HI HI)
3483(dst32-absolute 32 Unprefixed 4 8 HI HI)
3484(dst32-absolute 40 Unprefixed 4 8 HI HI)
3485(dst32-absolute 16 Unprefixed 4 8 SI SI)
3486(dst32-absolute 24 Unprefixed 4 8 SI SI)
3487(dst32-absolute 32 Unprefixed 4 8 SI SI)
3488(dst32-absolute 40 Unprefixed 4 8 SI SI)
3489
3490(dst32-absolute 24 Prefixed 12 16 QI QI)
3491(dst32-absolute 32 Prefixed 12 16 QI QI)
3492(dst32-absolute 40 Prefixed 12 16 QI QI)
3493(dst32-absolute 48 Prefixed 12 16 QI QI)
3494(dst32-absolute 24 Prefixed 12 16 HI HI)
3495(dst32-absolute 32 Prefixed 12 16 HI HI)
3496(dst32-absolute 40 Prefixed 12 16 HI HI)
3497(dst32-absolute 48 Prefixed 12 16 HI HI)
3498(dst32-absolute 24 Prefixed 12 16 SI SI)
3499(dst32-absolute 32 Prefixed 12 16 SI SI)
3500(dst32-absolute 40 Prefixed 12 16 SI SI)
3501(dst32-absolute 48 Prefixed 12 16 SI SI)
3502
3503(dst32-absolute 16 ExtUnprefixed 4 8 QI HI)
3504(dst32-absolute 16 ExtUnprefixed 4 8 HI SI)
3505
3506;-------------------------------------------------------------
3507; An indirect indirect
3508;-------------------------------------------------------------
3509
3510;(define-pmacro (dst-An-indirect-indirect-operand xmode)
3511; (define-derived-operand
3512; (name (.sym dst32-An-indirect-indirect- xmode))
3513; (comment (.str "m32c An indirect indirect destination " xmode))
3514; (attrs (machine 32))
3515; (mode xmode)
3516; (args (Dst32AnPrefixed))
3517; (syntax (.str "[[$Dst32AnPrefixed]]"))
3518; (base-ifield f-12-6)
3519; (encoding (+ (f-12-3 0) (f-16-1 0) Dst32AnPrefixed))
3520; (ifield-assertion (andif (eq f-12-3 0) (eq f-16-1 0)))
3521; (getter (mem32 xmode (indirect-addr Dst32AnPrefixed)))
3522; (setter (set (mem32 xmode (indirect-addr Dst32AnPrefixed)) newval))
3523; )
3524;)
3525
3526; (dst-An-indirect-indirect-operand QI)
3527; (dst-An-indirect-indirect-operand HI)
3528; (dst-An-indirect-indirect-operand SI)
3529
3530;-------------------------------------------------------------
3531; Relative indirect
3532;-------------------------------------------------------------
3533
3534(define-pmacro (dst-relative-indirect-operand offset xmode)
3535 (begin
3536; (define-derived-operand
3537; (name (.sym dst32- offset -8-SB-relative-indirect- xmode))
3538; (comment (.str "m32c dsp:8[sb] relative destination " xmode))
3539; (attrs (machine 32))
3540; (mode xmode)
3541; (args ((.sym Dsp- offset -u8)))
3542; (syntax (.str "[${Dsp-" offset "-u8}[sb]]"))
3543; (base-ifield f-12-6)
3544; (encoding (+ (f-12-3 1) (f-16-2 2) (.sym Dsp- offset -u8)))
3545; (ifield-assertion (andif (eq f-12-3 1) (eq f-16-2 2)))
3546; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) (reg h-sb)))))
3547; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) (reg h-sb)))) newval))
3548; )
3549; (define-derived-operand
3550; (name (.sym dst32- offset -16-SB-relative-indirect- xmode))
3551; (comment (.str "m32c dsp:16[sb] relative destination " xmode))
3552; (attrs (machine 32))
3553; (mode xmode)
3554; (args ((.sym Dsp- offset -u16)))
3555; (syntax (.str "[${Dsp-" offset "-u16}[sb]]"))
3556; (base-ifield f-12-6)
3557; (encoding (+ (f-12-3 2) (f-16-2 2) (.sym Dsp- offset -u16)))
3558; (ifield-assertion (andif (eq f-12-3 2) (eq f-16-2 2)))
3559; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) (reg h-sb)))))
3560; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) (reg h-sb)))) newval))
3561; )
3562; (define-derived-operand
3563; (name (.sym dst32- offset -8-FB-relative-indirect- xmode))
3564; (comment (.str "m32c dsp:8[fb] relative destination " xmode))
3565; (attrs (machine 32))
3566; (mode xmode)
3567; (args ((.sym Dsp- offset -s8)))
3568; (syntax (.str "[${Dsp-" offset "-s8}[fb]]"))
3569; (base-ifield f-12-6)
3570; (encoding (+ (f-12-3 1) (f-16-2 3) (.sym Dsp- offset -s8)))
3571; (ifield-assertion (andif (eq f-12-3 1) (eq f-16-2 3)))
3572; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s8) (reg h-fb)))))
3573; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s8) (reg h-fb)))) newval))
3574; )
3575; (define-derived-operand
3576; (name (.sym dst32- offset -16-FB-relative-indirect- xmode))
3577; (comment (.str "m32c dsp:16[fb] relative destination " xmode))
3578; (attrs (machine 32))
3579; (mode xmode)
3580; (args ((.sym Dsp- offset -s16)))
3581; (syntax (.str "[${Dsp-" offset "-s16}[fb]]"))
3582; (base-ifield f-12-6)
3583; (encoding (+ (f-12-3 2) (f-16-2 3) (.sym Dsp- offset -s16)))
3584; (ifield-assertion (andif (eq f-12-3 2) (eq f-16-2 3)))
3585; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s16) (reg h-fb)))))
3586; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s16) (reg h-fb)))) newval))
3587; )
3588; (define-derived-operand
3589; (name (.sym dst32- offset -8-An-relative-indirect- xmode))
3590; (comment (.str "m32c dsp:8[An] relative indirect destination " xmode))
3591; (attrs (machine 32))
3592; (mode xmode)
3593; (args (Dst32AnPrefixed (.sym Dsp- offset -u8)))
3594; (syntax (.str "[${Dsp-" offset "-u8}[$Dst32AnPrefixed]]"))
3595; (base-ifield f-12-6)
3596; (encoding (+ (f-12-3 1) (f-16-1 0) (.sym Dsp- offset -u8) Dst32AnPrefixed))
3597; (ifield-assertion (andif (eq f-12-3 1) (eq f-16-1 0)))
3598; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) Dst32AnPrefixed))))
3599; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) Dst32AnPrefixed))) newval))
3600; )
3601; (define-derived-operand
3602; (name (.sym dst32- offset -16-An-relative-indirect- xmode))
3603; (comment (.str "m32c dsp:16[An] relative destination " xmode))
3604; (attrs (machine 32))
3605; (mode xmode)
3606; (args (Dst32AnPrefixed (.sym Dsp- offset -u16)))
3607; (syntax (.str "[${Dsp-" offset "-u16}[$Dst32AnPrefixed]]"))
3608; (base-ifield f-12-6)
3609; (encoding (+ (f-12-3 2) (f-16-1 0) (.sym Dsp- offset -u16) Dst32AnPrefixed))
3610; (ifield-assertion (andif (eq f-12-3 2) (eq f-16-1 0)))
3611; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) Dst32AnPrefixed))))
3612; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) Dst32AnPrefixed))) newval))
3613; )
3614; (define-derived-operand
3615; (name (.sym dst32- offset -24-An-relative-indirect- xmode))
3616; (comment (.str "m32c dsp:24[An] relative destination " xmode))
3617; (attrs (machine 32))
3618; (mode xmode)
3619; (args (Dst32AnPrefixed (.sym Dsp- offset -u24)))
3620; (syntax (.str "[${Dsp-" offset "-u24}[$Dst32AnPrefixed]]"))
3621; (base-ifield f-12-6)
3622; (encoding (+ (f-12-3 3) (f-16-1 0) (.sym Dsp- offset -u24) Dst32AnPrefixed))
3623; (ifield-assertion (andif (eq f-12-3 3) (eq f-16-1 0)))
3624; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u24) Dst32AnPrefixed))))
3625; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u24) Dst32AnPrefixed))) newval))
3626; )
3627 )
3628)
3629
3630; (dst-relative-indirect-operand 24 QI)
3631; (dst-relative-indirect-operand 32 QI)
3632; (dst-relative-indirect-operand 40 QI)
3633; (dst-relative-indirect-operand 48 QI)
3634; (dst-relative-indirect-operand 24 HI)
3635; (dst-relative-indirect-operand 32 HI)
3636; (dst-relative-indirect-operand 40 HI)
3637; (dst-relative-indirect-operand 48 HI)
3638; (dst-relative-indirect-operand 24 SI)
3639; (dst-relative-indirect-operand 32 SI)
3640; (dst-relative-indirect-operand 40 SI)
3641; (dst-relative-indirect-operand 48 SI)
3642
3643;-------------------------------------------------------------
3644; Absolute indirect
3645;-------------------------------------------------------------
3646
3647(define-pmacro (dst-absolute-indirect offset xmode)
3648 (begin
3649; (define-derived-operand
3650; (name (.sym dst32- offset -16-absolute-indirect-derived- xmode))
3651; (comment (.str "m32c absolute indirect address " xmode))
3652; (attrs (machine 32))
3653; (mode xmode)
3654; (args ((.sym Dsp- offset -u16)))
3655; (syntax (.str "[${Dsp-" offset "-u16}]"))
3656; (base-ifield f-12-6)
3657; (encoding (+ (f-12-3 3) (f-16-2 3) (.sym Dsp- offset -u16)))
3658; (ifield-assertion (andif (eq f-12-3 3) (eq f-16-2 3)))
3659; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u16))))
3660; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u16))) newval))
3661; )
3662; (define-derived-operand
3663; (name (.sym dst32- offset -24-absolute-indirect-derived- xmode))
3664; (comment (.str "m32c absolute indirect address " xmode))
3665; (attrs (machine 32))
3666; (mode xmode)
3667; (args ((.sym Dsp- offset -u24)))
3668; (syntax (.str "[${Dsp-" offset "-u24}]"))
3669; (base-ifield f-12-6)
3670; (encoding (+ (f-12-3 3) (f-16-2 2) (.sym Dsp- offset -u24)))
3671; (ifield-assertion (andif (eq f-12-3 3) (eq f-16-2 2)))
3672; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u24))))
3673; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u24))) newval))
3674; )
3675 )
3676)
3677
3678(dst-absolute-indirect 24 QI)
3679(dst-absolute-indirect 32 QI)
3680(dst-absolute-indirect 40 QI)
3681(dst-absolute-indirect 48 QI)
3682(dst-absolute-indirect 24 HI)
3683(dst-absolute-indirect 32 HI)
3684(dst-absolute-indirect 40 HI)
3685(dst-absolute-indirect 48 HI)
3686(dst-absolute-indirect 24 SI)
3687(dst-absolute-indirect 32 SI)
3688(dst-absolute-indirect 40 SI)
3689(dst-absolute-indirect 48 SI)
3690
3691;-------------------------------------------------------------
3692; Bit operands
3693;-------------------------------------------------------------
3694(define-pmacro (get-register-bit reg bitno)
3695 (and (srl reg bitno) 1)
3696)
3697
3698(define-pmacro (set-register-bit reg bitno value)
3699 (set reg (or (and reg (inv (sll 1 bitno)))
3700 (sll (and QI value 1) bitno)))
3701)
3702
3703(define-pmacro (get-memory-bit mach base bitno)
3704 (and (srl (mem-mach mach QI (add base (div bitno 8)))
3705 (mod bitno 8))
3706 1)
3707)
3708
3709(define-pmacro (set-memory-bit mach base bitno value)
3710 (sequence ((USI addr))
3711 (set addr (add base (div bitno 8)))
3712 (set (mem-mach mach QI addr)
3713 (or (and (mem-mach mach QI addr)
3714 (inv (sll 1 (mod bitno 8))))
3715 (sll (and QI value 1) (mod bitno 8)))))
3716)
3717
3718;-------------------------------------------------------------
3719; Rn direct
3720;-------------------------------------------------------------
3721
3722(define-derived-operand
3723 (name bit16-Rn-direct)
3724 (comment "m16c Rn direct bit")
3725 (attrs (machine 16))
3726 (mode BI)
3727 (args (Bitno16R Bit16Rn))
3728 (syntax "$Bitno16R,$Bit16Rn")
3729 (base-ifield f-12-4)
3730 (encoding (+ (f-12-2 0) Bit16Rn Bitno16R))
3731 (ifield-assertion (eq f-12-2 0))
3732 (getter (get-register-bit Bit16Rn Bitno16R))
3733 (setter (set-register-bit Bit16Rn Bitno16R newval))
3734)
3735
3736(define-pmacro (bit32-Rn-direct-operand group base)
3737 (begin
3738 (define-derived-operand
3739 (name (.sym bit32-Rn-direct- group))
3740 (comment "m32c Rn direct bit")
3741 (attrs (machine 32))
3742 (mode BI)
3743 (args ((.sym Bitno32 group) (.sym Bit32Rn group)))
3744 (syntax (.str "$Bitno32" group ",$Bit32Rn" group))
3745 (base-ifield (.sym f- base -6))
3746 (encoding (+ ((.sym f- base -3) 4) (.sym Bit32Rn group) (.sym Bitno32 group)))
3747 (ifield-assertion (eq (.sym f- base -3) 4))
3748 (getter (get-register-bit (.sym Bit32Rn group) (.sym Bitno32 group)))
3749 (setter (set-register-bit (.sym Bit32Rn group) (.sym Bitno32 group) newval))
3750 )
3751 )
3752)
3753
3754(bit32-Rn-direct-operand Unprefixed 4)
3755(bit32-Rn-direct-operand Prefixed 12)
3756
3757;-------------------------------------------------------------
3758; An direct
3759;-------------------------------------------------------------
3760
3761(define-derived-operand
3762 (name bit16-An-direct)
3763 (comment "m16c An direct bit")
3764 (attrs (machine 16))
3765 (mode BI)
3766 (args (Bitno16R Bit16An))
3767 (syntax "$Bitno16R,$Bit16An")
3768 (base-ifield f-12-4)
3769 (encoding (+ (f-12-2 1) (f-14-1 0) Bit16An Bitno16R))
3770 (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 0)))
3771 (getter (get-register-bit Bit16An Bitno16R))
3772 (setter (set-register-bit Bit16An Bitno16R newval))
3773)
3774
3775(define-pmacro (bit32-An-direct-operand group base1 base2)
3776 (begin
3777 (define-derived-operand
3778 (name (.sym bit32-An-direct- group))
3779 (comment "m32c An direct bit")
3780 (attrs (machine 32))
3781 (mode BI)
3782 (args ((.sym Bitno32 group) (.sym Bit32An group)))
3783 (syntax (.str "$Bitno32" group ",$Bit32An" group))
3784 (base-ifield (.sym f- base1 -6))
3785 (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 1) (.sym Bit32An group) (.sym Bitno32 group)))
3786 (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 1)))
3787 (getter (get-register-bit (.sym Bit32An group) (.sym Bitno32 group)))
3788 (setter (set-register-bit (.sym Bit32An group) (.sym Bitno32 group) newval))
3789 )
3790 )
3791)
3792
3793(bit32-An-direct-operand Unprefixed 4 8)
3794(bit32-An-direct-operand Prefixed 12 16)
3795
3796;-------------------------------------------------------------
3797; An indirect
3798;-------------------------------------------------------------
3799
3800(define-derived-operand
3801 (name bit16-An-indirect)
3802 (comment "m16c An indirect bit")
3803 (attrs (machine 16))
3804 (mode BI)
3805 (args (Bit16An))
3806 (syntax "[$Bit16An]")
3807 (base-ifield f-12-4)
3808 (encoding (+ (f-12-2 1) (f-14-1 1) Bit16An))
3809 (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 1)))
3810 (getter (get-memory-bit 16 0 Bit16An))
3811 (setter (set-memory-bit 16 0 Bit16An newval))
3812)
3813
3814(define-pmacro (bit32-An-indirect-operand group base1 base2)
3815 (begin
3816 (define-derived-operand
3817 (name (.sym bit32-An-indirect- group))
3818 (comment "m32c An indirect destination ")
3819 (attrs (machine 32))
3820 (mode BI)
3821 (args ((.sym Bitno32 group) (.sym Bit32An group)))
3822 (syntax (.str "$Bitno32" group ",[$Bit32An" group "]"))
3823 (base-ifield (.sym f- base1 -6))
3824 (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 0) (.sym Bit32An group) (.sym Bitno32 group)))
3825 (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 0)))
3826 (getter (get-memory-bit 32 (.sym Bit32An group) (.sym Bitno32 group)))
3827 (setter (set-memory-bit 32 (.sym Bit32An group) (.sym Bitno32 group) newval))
3828 )
3829 )
3830)
3831
3832(bit32-An-indirect-operand Unprefixed 4 8)
3833(bit32-An-indirect-operand Prefixed 12 16)
3834
3835;-------------------------------------------------------------
3836; dsp:d[r] relative
3837;-------------------------------------------------------------
3838
3839(define-pmacro (bit16-relative-operand offset)
3840 (begin
3841 (define-derived-operand
3842 (name (.sym bit16- offset -8-SB-relative))
3843 (comment (.str "m16c dsp:8[sb] relative bit " xmode))
3844 (attrs (machine 16))
3845 (mode BI)
3846 (args ((.sym BitBase16- offset -u8)))
3847 (syntax (.str "${BitBase16-" offset "-u8}[sb]"))
3848 (base-ifield f-12-4)
3849 (encoding (+ (f-12-4 #xA) (.sym BitBase16- offset -u8)))
3850 (ifield-assertion (eq f-12-4 #xA))
3851 (getter (get-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u8)))
3852 (setter (set-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u8) newval))
3853 )
3854 (define-derived-operand
3855 (name (.sym bit16- offset -16-SB-relative))
3856 (comment (.str "m16c dsp:16[sb] relative bit " xmode))
3857 (attrs (machine 16))
3858 (mode BI)
3859 (args ((.sym BitBase16- offset -u16)))
3860 (syntax (.str "${BitBase16-" offset "-u16}[sb]"))
3861 (base-ifield f-12-4)
3862 (encoding (+ (f-12-4 #xE) (.sym BitBase16- offset -u16)))
3863 (ifield-assertion (eq f-12-4 #xE))
3864 (getter (get-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u16)))
3865 (setter (set-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u16) newval))
3866 )
3867 (define-derived-operand
3868 (name (.sym bit16- offset -8-FB-relative))
3869 (comment (.str "m16c dsp:8[fb] relative bit " xmode))
3870 (attrs (machine 16))
3871 (mode BI)
3872 (args ((.sym BitBase16- offset -s8)))
3873 (syntax (.str "${BitBase16-" offset "-s8}[fb]"))
3874 (base-ifield f-12-4)
3875 (encoding (+ (f-12-4 #xB) (.sym BitBase16- offset -s8)))
3876 (ifield-assertion (eq f-12-4 #xB))
3877 (getter (get-memory-bit 16 (reg h-fb) (.sym BitBase16- offset -s8)))
3878 (setter (set-memory-bit 16 (reg h-fb) (.sym BitBase16- offset -s8) newval))
3879 )
3880 (define-derived-operand
3881 (name (.sym bit16- offset -8-An-relative))
3882 (comment (.str "m16c dsp:8[An] relative bit " xmode))
3883 (attrs (machine 16))
3884 (mode BI)
3885 (args (Bit16An (.sym Dsp- offset -u8)))
3886 (syntax (.str "${Dsp-" offset "-u8}[$Bit16An]"))
3887 (base-ifield f-12-4)
3888 (encoding (+ (f-12-2 2) (f-14-1 0) (.sym Dsp- offset -u8) Bit16An))
3889 (ifield-assertion (andif (eq f-12-2 2) (eq f-14-1 0)))
3890 (getter (get-memory-bit 16 (.sym Dsp- offset -u8) Bit16An))
3891 (setter (set-memory-bit 16 (.sym Dsp- offset -u8) Bit16An newval))
3892 )
3893 (define-derived-operand
3894 (name (.sym bit16- offset -16-An-relative))
3895 (comment (.str "m16c dsp:16[An] relative bit " xmode))
3896 (attrs (machine 16))
3897 (mode BI)
3898 (args (Bit16An (.sym Dsp- offset -u16)))
3899 (syntax (.str "${Dsp-" offset "-u16}[$Bit16An]"))
3900 (base-ifield f-12-4)
3901 (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u16) Bit16An))
3902 (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0)))
3903 (getter (get-memory-bit 16 (.sym Dsp- offset -u16) Bit16An))
3904 (setter (set-memory-bit 16 (.sym Dsp- offset -u16) Bit16An newval))
3905 )
3906 )
3907)
3908
3909(bit16-relative-operand 16)
3910
3911(define-pmacro (bit32-relative-operand offset group base1 base2)
3912 (begin
3913 (define-derived-operand
3914 (name (.sym bit32- offset -11-SB-relative- group))
3915 (comment "m32c bit,base:11[sb] relative bit")
3916 (attrs (machine 32))
3917 (mode BI)
3918 (args ((.sym BitBase32- offset -u11- group)))
3919 (syntax (.str "${BitBase32-" offset "-u11-" group "}[sb]"))
3920 (base-ifield (.sym f- base1 -12))
3921 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 2) (.sym BitBase32- offset -u11- group)))
3922 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 2)))
3923 (getter (get-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u11- group)))
3924 (setter (set-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u11- group) newval))
3925 )
3926 (define-derived-operand
3927 (name (.sym bit32- offset -19-SB-relative- group))
3928 (comment "m32c bit,base:19[sb] relative bit")
3929 (attrs (machine 32))
3930 (mode BI)
3931 (args ((.sym BitBase32- offset -u19- group)))
3932 (syntax (.str "${BitBase32-" offset "-u19-" group "}[sb]"))
3933 (base-ifield (.sym f- base1 -12))
3934 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 2) (.sym BitBase32- offset -u19- group)))
3935 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 2)))
3936 (getter (get-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u19- group)))
3937 (setter (set-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u19- group) newval))
3938 )
3939 (define-derived-operand
3940 (name (.sym bit32- offset -11-FB-relative- group))
3941 (comment "m32c bit,base:11[fb] relative bit")
3942 (attrs (machine 32))
3943 (mode BI)
3944 (args ((.sym BitBase32- offset -s11- group)))
3945 (syntax (.str "${BitBase32-" offset "-s11-" group "}[fb]"))
3946 (base-ifield (.sym f- base1 -12))
3947 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 3) (.sym BitBase32- offset -s11- group)))
3948 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 3)))
3949 (getter (get-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s11- group)))
3950 (setter (set-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s11- group) newval))
3951 )
3952 (define-derived-operand
3953 (name (.sym bit32- offset -19-FB-relative- group))
3954 (comment "m32c bit,base:19[fb] relative bit")
3955 (attrs (machine 32))
3956 (mode BI)
3957 (args ((.sym BitBase32- offset -s19- group)))
3958 (syntax (.str "${BitBase32-" offset "-s19-" group "}[fb]"))
3959 (base-ifield (.sym f- base1 -12))
3960 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 3) (.sym BitBase32- offset -s19- group)))
3961 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 3)))
3962 (getter (get-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s19- group)))
3963 (setter (set-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s19- group) newval))
3964 )
3965 (define-derived-operand
3966 (name (.sym bit32- offset -11-An-relative- group))
3967 (comment "m32c bit,base:11[An] relative bit")
3968 (attrs (machine 32))
3969 (mode BI)
3970 (args ((.sym BitBase32- offset -u11- group) (.sym Bit32An group)))
3971 (syntax (.str "${BitBase32-" offset "-u11-" group "}[$Bit32An" group "]"))
3972 (base-ifield (.sym f- base1 -12))
3973 (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -1) 0) (.sym BitBase32- offset -u11- group) (.sym Bit32An group)))
3974 (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -1) 0)))
3975 (getter (get-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u11- group)))
3976 (setter (set-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u11- group) newval))
3977 )
3978 (define-derived-operand
3979 (name (.sym bit32- offset -19-An-relative- group))
3980 (comment "m32c bit,base:19[An] relative bit")
3981 (attrs (machine 32))
3982 (mode BI)
3983 (args ((.sym BitBase32- offset -u19- group) (.sym Bit32An group)))
3984 (syntax (.str "${BitBase32-" offset "-u19-" group "}[$Bit32An" group "]"))
3985 (base-ifield (.sym f- base1 -12))
3986 (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -1) 0) (.sym BitBase32- offset -u19- group) (.sym Bit32An group)))
3987 (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -1) 0)))
3988 (getter (get-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u19- group)))
3989 (setter (set-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u19- group) newval))
3990 )
3991 (define-derived-operand
3992 (name (.sym bit32- offset -27-An-relative- group))
3993 (comment "m32c bit,base:27[An] relative bit")
3994 (attrs (machine 32))
3995 (mode BI)
3996 (args ((.sym BitBase32- offset -u27- group) (.sym Bit32An group)))
3997 (syntax (.str "${BitBase32-" offset "-u27-" group "}[$Bit32An" group "]"))
3998 (base-ifield (.sym f- base1 -12))
3999 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -1) 0) (.sym BitBase32- offset -u27- group) (.sym Bit32An group)))
4000 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -1) 0)))
4001 (getter (get-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u27- group)))
4002 (setter (set-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u27- group) newval))
4003 )
4004 )
4005)
4006
4007(bit32-relative-operand 16 Unprefixed 4 8)
4008(bit32-relative-operand 24 Prefixed 12 16)
4009
4010(define-derived-operand
4011 (name bit16-11-SB-relative-S)
4012 (comment "m16c bit,base:11[sb] relative bit")
4013 (attrs (machine 16))
4014 (mode BI)
4015 (args (BitBase16-8-u11-S))
4016 (syntax "${BitBase16-8-u11-S}[sb]")
4017 (base-ifield (.sym f-5-3))
4018 (encoding (+ BitBase16-8-u11-S))
4019; (ifield-assertion (#t))
4020 (getter (get-memory-bit 16 (reg h-sb) BitBase16-8-u11-S))
4021 (setter (set-memory-bit 16 (reg h-sb) BitBase16-8-u11-S newval))
4022)
4023
4024(define-derived-operand
4025 (name Rn16-push-S-derived)
4026 (comment "m16c r0[lh] for push,pop short version")
4027 (attrs (machine 16))
4028 (mode QI)
4029 (args (Rn16-push-S))
4030 (syntax "${Rn16-push-S}")
4031 (base-ifield (.sym f-4-1))
4032 (encoding (+ Rn16-push-S))
4033; (ifield-assertion (#t))
4034 (getter (trunc QI Rn16-push-S))
4035 (setter (set Rn16-push-S newval))
4036)
4037
4038(define-derived-operand
4039 (name An16-push-S-derived)
4040 (comment "m16c r0[lh] for push,pop short version")
4041 (attrs (machine 16))
4042 (mode HI)
4043 (args (An16-push-S))
4044 (syntax "${An16-push-S}")
4045 (base-ifield (.sym f-4-1))
4046 (encoding (+ An16-push-S))
4047; (ifield-assertion (#t))
4048 (getter (trunc QI An16-push-S))
4049 (setter (set An16-push-S newval))
4050)
4051
4052;-------------------------------------------------------------
4053; Absolute address
4054;-------------------------------------------------------------
4055
4056(define-pmacro (bit16-absolute offset)
4057 (begin
4058 (define-derived-operand
4059 (name (.sym bit16- offset -16-absolute))
4060 (comment "m16c absolute address")
4061 (attrs (machine 16))
4062 (mode BI)
4063 (args ((.sym BitBase16- offset -u16)))
4064 (syntax (.str "${BitBase16-" offset "-u16}"))
4065 (base-ifield f-12-4)
4066 (encoding (+ (f-12-4 #xF) (.sym BitBase16- offset -u16)))
4067 (ifield-assertion (eq f-12-4 #xF))
4068 (getter (get-memory-bit 16 0 (.sym BitBase16- offset -u16)))
4069 (setter (set-memory-bit 16 0 (.sym BitBase16- offset -u16) newval))
4070 )
4071 )
4072)
4073
4074(bit16-absolute 16)
4075
4076(define-pmacro (bit32-absolute offset group base1 base2)
4077 (begin
4078 (define-derived-operand
4079 (name (.sym bit32- offset -19-absolute- group))
4080 (comment "m32c absolute address bit")
4081 (attrs (machine 32))
4082 (mode BI)
4083 (args ((.sym BitBase32- offset -u19- group)))
4084 (syntax (.str "${BitBase32-" offset "-u19-" group "}"))
4085 (base-ifield (.sym f- base1 -12))
4086 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym BitBase32- offset -u19- group)))
4087 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3)))
4088 (getter (get-memory-bit 32 0 (.sym BitBase32- offset -u19- group)))
4089 (setter (set-memory-bit 32 0 (.sym BitBase32- offset -u19- group) newval))
4090 )
4091 (define-derived-operand
4092 (name (.sym bit32- offset -27-absolute- group))
4093 (comment "m32c absolute address bit")
4094 (attrs (machine 32))
4095 (mode BI)
4096 (args ((.sym BitBase32- offset -u27- group)))
4097 (syntax (.str "${BitBase32-" offset "-u27-" group "}"))
4098 (base-ifield (.sym f- base1 -12))
4099 (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym BitBase32- offset -u27- group)))
4100 (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2)))
4101 (getter (get-memory-bit 32 0 (.sym BitBase32- offset -u27- group)))
4102 (setter (set-memory-bit 32 0 (.sym BitBase32- offset -u27- group) newval))
4103 )
4104 )
4105)
4106
4107(bit32-absolute 16 Unprefixed 4 8)
4108(bit32-absolute 24 Prefixed 12 16)
4109
4110;-------------------------------------------------------------
4111; Destination operands for short fomat insns
4112;-------------------------------------------------------------
4113
4114(define-derived-operand
4115 (name dst16-3-S-R0l-direct-QI)
4116 (comment "m16c R0l direct QI")
4117 (attrs (machine 16))
4118 (mode QI)
4119 (args (R0l))
4120 (syntax "r0l")
4121 (base-ifield f-5-3)
4122 (encoding (+ (f-5-3 4)))
4123 (ifield-assertion (eq f-5-3 4))
4124 (getter (trunc QI R0l))
4125 (setter (set R0l newval))
4126)
4127(define-derived-operand
4128 (name dst16-3-S-R0h-direct-QI)
4129 (comment "m16c R0h direct QI")
4130 (attrs (machine 16))
4131 (mode QI)
4132 (args (R0h))
4133 (syntax "r0h")
4134 (base-ifield f-5-3)
4135 (encoding (+ (f-5-3 3)))
4136 (ifield-assertion (eq f-5-3 3))
4137 (getter (trunc QI R0h))
4138 (setter (set R0h newval))
4139)
4140(define-derived-operand
4141 (name dst16-3-S-8-8-SB-relative-QI)
4142 (comment "m16c SB relative QI")
4143 (attrs (machine 16))
4144 (mode QI)
4145 (args (Dsp-8-u8))
4146 (syntax "${Dsp-8-u8}[sb]")
4147 (base-ifield f-5-3)
4148 (encoding (+ (f-5-3 5) Dsp-8-u8))
4149 (ifield-assertion (eq f-5-3 5))
4150 (getter (mem16 QI (add Dsp-8-u8 (reg h-sb))))
4151 (setter (set (mem16 QI (add Dsp-8-u8 (reg h-sb))) newval))
4152)
4153(define-derived-operand
4154 (name dst16-3-S-8-8-FB-relative-QI)
4155 (comment "m16c FB relative QI")
4156 (attrs (machine 16))
4157 (mode QI)
4158 (args (Dsp-8-s8))
4159 (syntax "${Dsp-8-s8}[fb]")
4160 (base-ifield f-5-3)
4161 (encoding (+ (f-5-3 6) Dsp-8-s8))
4162 (ifield-assertion (eq f-5-3 6))
4163 (getter (mem16 QI (add Dsp-8-s8 (reg h-fb))))
4164 (setter (set (mem16 QI (add Dsp-8-s8 (reg h-fb))) newval))
4165)
4166(define-derived-operand
4167 (name dst16-3-S-8-16-absolute-QI)
4168 (comment "m16c absolute address QI")
4169 (attrs (machine 16))
4170 (mode QI)
4171 (args (Dsp-8-u16))
4172 (syntax "${Dsp-8-u16}")
4173 (base-ifield f-5-3)
4174 (encoding (+ (f-5-3 7) Dsp-8-u16))
4175 (ifield-assertion (eq f-5-3 7))
4176 (getter (mem16 QI Dsp-8-u16))
4177 (setter (set (mem16 QI Dsp-8-u16) newval))
4178)
4179(define-derived-operand
4180 (name dst16-3-S-16-8-SB-relative-QI)
4181 (comment "m16c SB relative QI")
4182 (attrs (machine 16))
4183 (mode QI)
4184 (args (Dsp-16-u8))
4185 (syntax "${Dsp-16-u8}[sb]")
4186 (base-ifield f-5-3)
4187 (encoding (+ (f-5-3 5) Dsp-16-u8))
4188 (ifield-assertion (eq f-5-3 5))
4189 (getter (mem16 QI (add Dsp-16-u8 (reg h-sb))))
4190 (setter (set (mem16 QI (add Dsp-16-u8 (reg h-sb))) newval))
4191)
4192(define-derived-operand
4193 (name dst16-3-S-16-8-FB-relative-QI)
4194 (comment "m16c FB relative QI")
4195 (attrs (machine 16))
4196 (mode QI)
4197 (args (Dsp-16-s8))
4198 (syntax "${Dsp-16-s8}[fb]")
4199 (base-ifield f-5-3)
4200 (encoding (+ (f-5-3 6) Dsp-16-s8))
4201 (ifield-assertion (eq f-5-3 6))
4202 (getter (mem16 QI (add Dsp-16-s8 (reg h-fb))))
4203 (setter (set (mem16 QI (add Dsp-16-s8 (reg h-fb))) newval))
4204)
4205(define-derived-operand
4206 (name dst16-3-S-16-16-absolute-QI)
4207 (comment "m16c absolute address QI")
4208 (attrs (machine 16))
4209 (mode QI)
4210 (args (Dsp-16-u16))
4211 (syntax "${Dsp-16-u16}")
4212 (base-ifield f-5-3)
4213 (encoding (+ (f-5-3 7) Dsp-16-u16))
4214 (ifield-assertion (eq f-5-3 7))
4215 (getter (mem16 QI Dsp-16-u16))
4216 (setter (set (mem16 QI Dsp-16-u16) newval))
4217)
4218(define-derived-operand
4219 (name srcdst16-r0l-r0h-S-derived)
4220 (comment "m16c r0l/r0h operand for short format insns")
4221 (attrs (machine 16))
4222 (mode SI)
4223 (args (SrcDst16-r0l-r0h-S-normal))
4224 (syntax "${SrcDst16-r0l-r0h-S-normal}")
4225 (base-ifield f-6-3)
4226 (encoding (+ (f-6-2 0) SrcDst16-r0l-r0h-S-normal))
4227 (ifield-assertion (eq f-6-2 0))
4228 (getter (trunc SI SrcDst16-r0l-r0h-S-normal))
4229 (setter ()) ; no setter
4230)
4231(define-derived-operand
4232 (name dst32-2-S-R0l-direct-QI)
4233 (comment "m32c R0l direct QI")
4234 (attrs (machine 32))
4235 (mode QI)
4236 (args (R0l))
4237 (syntax "r0l")
4238 (base-ifield f-2-2)
4239 (encoding (+ (f-2-2 0)))
4240 (ifield-assertion (eq f-2-2 0))
4241 (getter (trunc QI R0l))
4242 (setter (set R0l newval))
4243)
4244(define-derived-operand
4245 (name dst32-2-S-R0-direct-HI)
4246 (comment "m32c R0 direct HI")
4247 (attrs (machine 32))
4248 (mode HI)
4249 (args (R0))
4250 (syntax "r0")
4251 (base-ifield f-2-2)
4252 (encoding (+ (f-2-2 0)))
4253 (ifield-assertion (eq f-2-2 0))
4254 (getter (trunc HI R0))
4255 (setter (set R0 newval))
4256)
4257(define-derived-operand
4258 (name dst32-1-S-A0-direct-HI)
4259 (comment "m32c A0 direct HI")
4260 (attrs (machine 32))
4261 (mode HI)
4262 (args (A0))
4263 (syntax "a0")
4264 (base-ifield f-7-1)
4265 (encoding (+ (f-7-1 0)))
4266 (ifield-assertion (eq f-7-1 0))
4267 (getter (trunc HI A0))
4268 (setter (set A0 newval))
4269)
4270(define-derived-operand
4271 (name dst32-1-S-A1-direct-HI)
4272 (comment "m32c A1 direct HI")
4273 (attrs (machine 32))
4274 (mode HI)
4275 (args (A1))
4276 (syntax "a1")
4277 (base-ifield f-7-1)
4278 (encoding (+ (f-7-1 1)))
4279 (ifield-assertion (eq f-7-1 1))
4280 (getter (trunc HI A1))
4281 (setter (set A1 newval))
4282)
4283(define-pmacro (dst32-2-S-operands xmode)
4284 (begin
4285 (define-derived-operand
4286 (name (.sym dst32-2-S-8-SB-relative- xmode))
4287 (comment "m32c SB relative for short binary insns")
4288 (attrs (machine 32))
4289 (mode xmode)
4290 (args (Dsp-8-u8))
4291 (syntax "${Dsp-8-u8}[sb]")
4292 (base-ifield f-2-2)
4293 (encoding (+ (f-2-2 2) Dsp-8-u8))
4294 (ifield-assertion (eq f-2-2 2))
4295 (getter (c-call xmode (.str "operand_getter_" xmode) sb Dsp-8-u8))
4296 (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb Dsp-8-u8))
4297; (getter (mem32 xmode (add Dsp-8-u8 (reg h-sb))))
4298; (setter (set (mem32 xmode (add Dsp-8-u8 (reg h-sb))) newval))
4299 )
4300 (define-derived-operand
4301 (name (.sym dst32-2-S-8-FB-relative- xmode))
4302 (comment "m32c FB relative for short binary insns")
4303 (attrs (machine 32))
4304 (mode xmode)
4305 (args (Dsp-8-s8))
4306 (syntax "${Dsp-8-s8}[fb]")
4307 (base-ifield f-2-2)
4308 (encoding (+ (f-2-2 3) Dsp-8-s8))
4309 (ifield-assertion (eq f-2-2 3))
4310 (getter (c-call xmode (.str "operand_getter_" xmode) fb Dsp-8-s8))
4311 (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb Dsp-8-s8))
4312; (getter (mem32 xmode (add Dsp-8-s8 (reg h-fb))))
4313; (setter (set (mem32 xmode (add Dsp-8-s8 (reg h-fb))) newval))
4314 )
4315 (define-derived-operand
4316 (name (.sym dst32-2-S-16-absolute- xmode))
4317 (comment "m32c absolute address for short binary insns")
4318 (attrs (machine 32))
4319 (mode xmode)
4320 (args (Dsp-8-u16))
4321 (syntax "${Dsp-8-u16}")
4322 (base-ifield f-2-2)
4323 (encoding (+ (f-2-2 1) Dsp-8-u16))
4324 (ifield-assertion (eq f-2-2 1))
4325 (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) Dsp-8-u16))
4326 (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) Dsp-8-u16))
4327; (getter (mem32 xmode Dsp-8-u16))
4328; (setter (set (mem32 xmode Dsp-8-u16) newval))
4329 )
4330; (define-derived-operand
4331; (name (.sym dst32-2-S-8-SB-relative-indirect- xmode))
4332; (comment "m32c SB relative for short binary insns")
4333; (attrs (machine 32))
4334; (mode xmode)
4335; (args (Dsp-16-u8))
4336; (syntax "[${Dsp-16-u8}[sb]]")
4337; (base-ifield f-10-2)
4338; (encoding (+ (f-10-2 2) Dsp-16-u8))
4339; (ifield-assertion (eq f-10-2 2))
4340; (getter (mem32 xmode (indirect-addr (add Dsp-16-u8 (reg h-sb)))))
4341; (setter (set (mem32 xmode (indirect-addr (add Dsp-16-u8 (reg h-sb)))) newval))
4342; )
4343; (define-derived-operand
4344; (name (.sym dst32-2-S-8-FB-relative-indirect- xmode))
4345; (comment "m32c FB relative for short binary insns")
4346; (attrs (machine 32))
4347; (mode xmode)
4348; (args (Dsp-16-s8))
4349; (syntax "[${Dsp-16-s8}[fb]]")
4350; (base-ifield f-10-2)
4351; (encoding (+ (f-10-2 3) Dsp-16-s8))
4352; (ifield-assertion (eq f-10-2 3))
4353; (getter (mem32 xmode (indirect-addr (add Dsp-16-s8 (reg h-fb)))))
4354; (setter (set (mem32 xmode (indirect-addr (add Dsp-16-s8 (reg h-fb)))) newval))
4355; )
4356; (define-derived-operand
4357; (name (.sym dst32-2-S-16-absolute-indirect- xmode))
4358; (comment "m32c absolute address for short binary insns")
4359; (attrs (machine 32))
4360; (mode xmode)
4361; (args (Dsp-16-u16))
4362; (syntax "[${Dsp-16-u16}]")
4363; (base-ifield f-10-2)
4364; (encoding (+ (f-10-2 1) Dsp-16-u16))
4365; (ifield-assertion (eq f-10-2 1))
4366; (getter (mem32 xmode (indirect-addr Dsp-16-u16)))
4367; (setter (set (mem32 xmode (indirect-addr Dsp-16-u16)) newval))
4368; )
4369 )
4370)
4371
4372(dst32-2-S-operands QI)
4373(dst32-2-S-operands HI)
4374(dst32-2-S-operands SI)
4375
4376;=============================================================
4377; Anyof operands
4378;-------------------------------------------------------------
4379; Source operands with no additional fields
4380;-------------------------------------------------------------
4381
4382(define-pmacro (src16-basic-operand xmode)
4383 (begin
4384 (define-anyof-operand
4385 (name (.sym src16-basic- xmode))
4386 (comment (.str "m16c source operand of size " xmode " with no additional fields"))
4387 (attrs (machine 16))
4388 (mode xmode)
4389 (choices
4390 (.sym src16-Rn-direct- xmode)
4391 (.sym src16-An-direct- xmode)
4392 (.sym src16-An-indirect- xmode)
4393 )
4394 )
4395 )
4396)
4397(src16-basic-operand QI)
4398(src16-basic-operand HI)
4399
4400(define-pmacro (src32-basic-operand xmode)
4401 (begin
4402 (define-anyof-operand
4403 (name (.sym src32-basic-Unprefixed- xmode))
4404 (comment (.str "m32c destination operand of size " xmode " with no additional fields"))
4405 (attrs (machine 32))
4406 (mode xmode)
4407 (choices
4408 (.sym src32-Rn-direct-Unprefixed- xmode)
4409 (.sym src32-An-direct-Unprefixed- xmode)
4410 (.sym src32-An-indirect-Unprefixed- xmode)
4411 )
4412 )
4413 (define-anyof-operand
4414 (name (.sym src32-basic-Prefixed- xmode))
4415 (comment (.str "m32c destination operand of size " xmode " with no additional fields"))
4416 (attrs (machine 32))
4417 (mode xmode)
4418 (choices
4419 (.sym src32-Rn-direct-Prefixed- xmode)
4420 (.sym src32-An-direct-Prefixed- xmode)
4421 (.sym src32-An-indirect-Prefixed- xmode)
4422 )
4423 )
4424; (define-anyof-operand
4425; (name (.sym src32-basic-indirect- xmode))
4426; (comment (.str "m32c destination operand of size " xmode " indirect with no additional fields"))
4427; (attrs (machine 32))
4428; (mode xmode)
4429; (choices
4430; (.sym src32-An-indirect-indirect- xmode)
4431; )
4432; )
4433 )
4434)
4435
4436(src32-basic-operand QI)
4437(src32-basic-operand HI)
4438(src32-basic-operand SI)
4439
4440(define-anyof-operand
4441 (name src32-basic-ExtPrefixed-QI)
4442 (comment "m32c source operand of size QI with no additional fields")
4443 (attrs (machine 32))
4444 (mode QI)
4445 (choices
4446 src32-Rn-direct-Prefixed-QI
4447 src32-An-indirect-Prefixed-QI
4448 )
4449)
4450
4451;-------------------------------------------------------------
4452; Source operands with additional fields at offset 16 bits
4453;-------------------------------------------------------------
4454
4455(define-pmacro (src16-16-operand xmode)
4456 (begin
4457 (define-anyof-operand
4458 (name (.sym src16-16-8- xmode))
4459 (comment (.str "m16c source operand of size " xmode " with additional 8 bit fields at offset 16"))
4460 (attrs (machine 16))
4461 (mode xmode)
4462 (choices
4463 (.sym src16-16-8-An-relative- xmode)
4464 (.sym src16-16-8-SB-relative- xmode)
4465 (.sym src16-16-8-FB-relative- xmode)
4466 )
4467 )
4468 (define-anyof-operand
4469 (name (.sym src16-16-16- xmode))
4470 (comment (.str "m16c source operand of size " xmode " with additional 16 bit fields at offset 16"))
4471 (attrs (machine 16))
4472 (mode xmode)
4473 (choices
4474 (.sym src16-16-16-An-relative- xmode)
4475 (.sym src16-16-16-SB-relative- xmode)
4476 (.sym src16-16-16-absolute- xmode)
4477 )
4478 )
4479 )
4480)
4481(src16-16-operand QI)
4482(src16-16-operand HI)
4483
4484(define-pmacro (src32-16-operand xmode)
4485 (begin
4486 (define-anyof-operand
4487 (name (.sym src32-16-8-Unprefixed- xmode))
4488 (comment (.str "m32c source operand of size " xmode " with additional 8 bit fields at offset 16"))
4489 (attrs (machine 32))
4490 (mode xmode)
4491 (choices
4492 (.sym src32-16-8-An-relative-Unprefixed- xmode)
4493 (.sym src32-16-8-SB-relative-Unprefixed- xmode)
4494 (.sym src32-16-8-FB-relative-Unprefixed- xmode)
4495 )
4496 )
4497 (define-anyof-operand
4498 (name (.sym src32-16-16-Unprefixed- xmode))
4499 (comment (.str "m32c source operand of size " xmode " with additional 16 bit fields at offset 16"))
4500 (attrs (machine 32))
4501 (mode xmode)
4502 (choices
4503 (.sym src32-16-16-An-relative-Unprefixed- xmode)
4504 (.sym src32-16-16-SB-relative-Unprefixed- xmode)
4505 (.sym src32-16-16-FB-relative-Unprefixed- xmode)
4506 (.sym src32-16-16-absolute-Unprefixed- xmode)
4507 )
4508 )
4509 (define-anyof-operand
4510 (name (.sym src32-16-24-Unprefixed- xmode))
4511 (comment (.str "m32c source operand of size " xmode " with additional 24 bit fields at offset 16"))
4512 (attrs (machine 32))
4513 (mode xmode)
4514 (choices
4515 (.sym src32-16-24-An-relative-Unprefixed- xmode)
4516 (.sym src32-16-24-absolute-Unprefixed- xmode)
4517 )
4518 )
4519 )
4520)
4521
4522(src32-16-operand QI)
4523(src32-16-operand HI)
4524(src32-16-operand SI)
4525
4526;-------------------------------------------------------------
4527; Source operands with additional fields at offset 24 bits
4528;-------------------------------------------------------------
4529
4530(define-pmacro (src-24-operand group xmode)
4531 (begin
4532 (define-anyof-operand
4533 (name (.sym src32-24-8- group - xmode))
4534 (comment (.str "m32c source operand of size " xmode " with additional 8 bit fields at offset 24"))
4535 (attrs (machine 32))
4536 (mode xmode)
4537 (choices
4538 (.sym src32-24-8-An-relative- group - xmode)
4539 (.sym src32-24-8-SB-relative- group - xmode)
4540 (.sym src32-24-8-FB-relative- group - xmode)
4541 )
4542 )
4543 (define-anyof-operand
4544 (name (.sym src32-24-16- group - xmode))
4545 (comment (.str "m32c source operand of size " xmode " with additional 16 bit fields at offset 16"))
4546 (attrs (machine 32))
4547 (mode xmode)
4548 (choices
4549 (.sym src32-24-16-An-relative- group - xmode)
4550 (.sym src32-24-16-SB-relative- group - xmode)
4551 (.sym src32-24-16-FB-relative- group - xmode)
4552 (.sym src32-24-16-absolute- group - xmode)
4553 )
4554 )
4555 (define-anyof-operand
4556 (name (.sym src32-24-24- group - xmode))
4557 (comment (.str "m32c source operand of size " xmode " with additional 24 bit fields at offset 16"))
4558 (attrs (machine 32))
4559 (mode xmode)
4560 (choices
4561 (.sym src32-24-24-An-relative- group - xmode)
4562 (.sym src32-24-24-absolute- group - xmode)
4563 )
4564 )
4565 )
4566)
4567
4568(src-24-operand Prefixed QI)
4569(src-24-operand Prefixed HI)
4570(src-24-operand Prefixed SI)
4571
4572(define-pmacro (src-24-indirect-operand xmode)
4573 (begin
4574; (define-anyof-operand
4575; (name (.sym src32-24-8-indirect- xmode))
4576; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
4577; (attrs (machine 32))
4578; (mode xmode)
4579; (choices
4580; (.sym src32-24-8-An-relative-indirect- xmode)
4581; (.sym src32-24-8-SB-relative-indirect- xmode)
4582; (.sym src32-24-8-FB-relative-indirect- xmode)
4583; )
4584; )
4585; (define-anyof-operand
4586; (name (.sym src32-24-16-indirect- xmode))
4587; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
4588; (attrs (machine 32))
4589; (mode xmode)
4590; (choices
4591; (.sym src32-24-16-An-relative-indirect- xmode)
4592; (.sym src32-24-16-SB-relative-indirect- xmode)
4593; (.sym src32-24-16-FB-relative-indirect- xmode)
4594; )
4595; )
4596; (define-anyof-operand
4597; (name (.sym src32-24-24-indirect- xmode))
4598; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
4599; (attrs (machine 32))
4600; (mode xmode)
4601; (choices
4602; (.sym src32-24-24-An-relative-indirect- xmode)
4603; )
4604; )
4605; (define-anyof-operand
4606; (name (.sym src32-24-16-absolute-indirect- xmode))
4607; (comment (.str "m32c source operand of size " xmode " 16 bit absolute indirect"))
4608; (attrs (machine 32))
4609; (mode xmode)
4610; (choices
4611; (.sym src32-24-16-absolute-indirect-derived- xmode)
4612; )
4613; )
4614; (define-anyof-operand
4615; (name (.sym src32-24-24-absolute-indirect- xmode))
4616; (comment (.str "m32c source operand of size " xmode " 24 bit absolute indirect"))
4617; (attrs (machine 32))
4618; (mode xmode)
4619; (choices
4620; (.sym src32-24-24-absolute-indirect-derived- xmode)
4621; )
4622; )
4623 )
4624)
4625
4626; (src-24-indirect-operand QI)
4627; (src-24-indirect-operand HI)
4628; (src-24-indirect-operand SI)
4629
4630;-------------------------------------------------------------
4631; Destination operands with no additional fields
4632;-------------------------------------------------------------
4633
4634(define-pmacro (dst16-basic-operand xmode)
4635 (begin
4636 (define-anyof-operand
4637 (name (.sym dst16-basic- xmode))
4638 (comment (.str "m16c destination operand of size " xmode " with no additional fields"))
4639 (attrs (machine 16))
4640 (mode xmode)
4641 (choices
4642 (.sym dst16-Rn-direct- xmode)
4643 (.sym dst16-An-direct- xmode)
4644 (.sym dst16-An-indirect- xmode)
4645 )
4646 )
4647 )
4648)
4649
4650(dst16-basic-operand QI)
4651(dst16-basic-operand HI)
4652(dst16-basic-operand SI)
4653
4654(define-pmacro (dst32-basic-operand xmode)
4655 (begin
4656 (define-anyof-operand
4657 (name (.sym dst32-basic-Unprefixed- xmode))
4658 (comment (.str "m32c destination operand of size " xmode " with no additional fields"))
4659 (attrs (machine 32))
4660 (mode xmode)
4661 (choices
4662 (.sym dst32-Rn-direct-Unprefixed- xmode)
4663 (.sym dst32-An-direct-Unprefixed- xmode)
4664 (.sym dst32-An-indirect-Unprefixed- xmode)
4665 )
4666 )
4667 (define-anyof-operand
4668 (name (.sym dst32-basic-Prefixed- xmode))
4669 (comment (.str "m32c destination operand of size " xmode " with no additional fields"))
4670 (attrs (machine 32))
4671 (mode xmode)
4672 (choices
4673 (.sym dst32-Rn-direct-Prefixed- xmode)
4674 (.sym dst32-An-direct-Prefixed- xmode)
4675 (.sym dst32-An-indirect-Prefixed- xmode)
4676 )
4677 )
4678 )
4679)
4680
4681(dst32-basic-operand QI)
4682(dst32-basic-operand HI)
4683(dst32-basic-operand SI)
4684
4685;-------------------------------------------------------------
4686; Destination operands with possible additional fields at offset 16 bits
4687;-------------------------------------------------------------
4688
4689(define-pmacro (dst16-16-operand xmode)
4690 (begin
4691 (define-anyof-operand
4692 (name (.sym dst16-16- xmode))
4693 (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16"))
4694 (attrs (machine 16))
4695 (mode xmode)
4696 (choices
4697 (.sym dst16-Rn-direct- xmode)
4698 (.sym dst16-An-direct- xmode)
4699 (.sym dst16-An-indirect- xmode)
4700 (.sym dst16-16-8-An-relative- xmode)
4701 (.sym dst16-16-16-An-relative- xmode)
4702 (.sym dst16-16-8-SB-relative- xmode)
4703 (.sym dst16-16-16-SB-relative- xmode)
4704 (.sym dst16-16-8-FB-relative- xmode)
4705 (.sym dst16-16-16-absolute- xmode)
4706 )
4707 )
4708 (define-anyof-operand
4709 (name (.sym dst16-16-8- xmode))
4710 (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16"))
4711 (attrs (machine 16))
4712 (mode xmode)
4713 (choices
4714 (.sym dst16-16-8-An-relative- xmode)
4715 (.sym dst16-16-8-SB-relative- xmode)
4716 (.sym dst16-16-8-FB-relative- xmode)
4717 )
4718 )
4719 (define-anyof-operand
4720 (name (.sym dst16-16-16- xmode))
4721 (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16"))
4722 (attrs (machine 16))
4723 (mode xmode)
4724 (choices
4725 (.sym dst16-16-16-An-relative- xmode)
4726 (.sym dst16-16-16-SB-relative- xmode)
4727 (.sym dst16-16-16-absolute- xmode)
4728 )
4729 )
4730 )
4731)
4732
4733(dst16-16-operand QI)
4734(dst16-16-operand HI)
4735(dst16-16-operand SI)
4736
4737(define-anyof-operand
4738 (name dst16-16-Ext-QI)
4739 (comment "m16c destination operand of size QI for 'ext' insns with additional fields at offset 16")
4740 (attrs (machine 16))
4741 (mode QI)
4742 (choices
4743 dst16-Rn-direct-Ext-QI
4744 dst16-An-indirect-Ext-QI
4745 dst16-16-8-An-relative-Ext-QI
4746 dst16-16-16-An-relative-Ext-QI
4747 dst16-16-8-SB-relative-Ext-QI
4748 dst16-16-16-SB-relative-Ext-QI
4749 dst16-16-8-FB-relative-Ext-QI
4750 dst16-16-16-absolute-Ext-QI
4751 )
4752)
4753
4754(define-derived-operand
4755 (name dst16-An-indirect-Mova-HI)
4756 (comment "m16c addressof An indirect destination HI")
4757 (attrs (ISA m16c))
4758 (mode HI)
4759 (args (Dst16An))
4760 (syntax "[$Dst16An]")
4761 (base-ifield f-12-4)
4762 (encoding (+ (f-12-2 1) (f-14-1 1) Dst16An))
4763 (ifield-assertion
4764 (andif (eq f-12-2 1) (eq f-14-1 1)))
4765 (getter Dst16An)
4766 (setter (nop))
4767 )
4768
4769(define-derived-operand
4770 (name dst16-16-8-An-relative-Mova-HI)
4771 (comment
4772 "m16c addressof dsp:8[An] relative destination HI")
4773 (attrs (ISA m16c))
4774 (mode HI)
4775 (args (Dst16An Dsp-16-u8))
4776 (syntax "${Dsp-16-u8}[$Dst16An]")
4777 (base-ifield f-12-4)
4778 (encoding
4779 (+ (f-12-2 2) (f-14-1 0) Dsp-16-u8 Dst16An))
4780 (ifield-assertion
4781 (andif (eq f-12-2 2) (eq f-14-1 0)))
4782 (getter (add Dsp-16-u8 Dst16An))
4783 (setter (nop))
4784)
4785(define-derived-operand
4786 (name dst16-16-16-An-relative-Mova-HI)
4787 (comment
4788 "m16c addressof dsp:16[An] relative destination HI")
4789 (attrs (ISA m16c))
4790 (mode HI)
4791 (args (Dst16An Dsp-16-u16))
4792 (syntax "${Dsp-16-u16}[$Dst16An]")
4793 (base-ifield f-12-4)
4794 (encoding
4795 (+ (f-12-2 3) (f-14-1 0) Dsp-16-u16 Dst16An))
4796 (ifield-assertion
4797 (andif (eq f-12-2 3) (eq f-14-1 0)))
4798 (getter (add Dsp-16-u16 Dst16An))
4799 (setter (nop))
4800 )
4801(define-derived-operand
4802 (name dst16-16-8-SB-relative-Mova-HI)
4803 (comment
4804 "m16c addressof dsp:8[sb] relative destination HI")
4805 (attrs (ISA m16c))
4806 (mode HI)
4807 (args (Dsp-16-u8))
4808 (syntax "${Dsp-16-u8}[sb]")
4809 (base-ifield f-12-4)
4810 (encoding (+ (f-12-4 10) Dsp-16-u8))
4811 (ifield-assertion (eq f-12-4 10))
4812 (getter (add Dsp-16-u8 (reg h-sb)))
4813 (setter (nop))
4814)
4815(define-derived-operand
4816 (name dst16-16-16-SB-relative-Mova-HI)
4817 (comment
4818 "m16c addressof dsp:16[sb] relative destination HI")
4819 (attrs (ISA m16c))
4820 (mode HI)
4821 (args (Dsp-16-u16))
4822 (syntax "${Dsp-16-u16}[sb]")
4823 (base-ifield f-12-4)
4824 (encoding (+ (f-12-4 14) Dsp-16-u16))
4825 (ifield-assertion (eq f-12-4 14))
4826 (getter (add Dsp-16-u16 (reg h-sb)))
4827 (setter (nop))
4828 )
4829(define-derived-operand
4830 (name dst16-16-8-FB-relative-Mova-HI)
4831 (comment
4832 "m16c addressof dsp:8[fb] relative destination HI")
4833 (attrs (ISA m16c))
4834 (mode HI)
4835 (args (Dsp-16-s8))
4836 (syntax "${Dsp-16-s8}[fb]")
4837 (base-ifield f-12-4)
4838 (encoding (+ (f-12-4 11) Dsp-16-s8))
4839 (ifield-assertion (eq f-12-4 11))
4840 (getter (add Dsp-16-s8 (reg h-fb)))
4841 (setter (nop))
4842 )
4843(define-derived-operand
4844 (name dst16-16-16-absolute-Mova-HI)
4845 (comment "m16c addressof absolute address HI")
4846 (attrs (ISA m16c))
4847 (mode HI)
4848 (args (Dsp-16-u16))
4849 (syntax "${Dsp-16-u16}")
4850 (base-ifield f-12-4)
4851 (encoding (+ (f-12-4 15) Dsp-16-u16))
4852 (ifield-assertion (eq f-12-4 15))
4853 (getter Dsp-16-u16)
4854 (setter (nop))
4855 )
4856
4857(define-anyof-operand
4858 (name dst16-16-Mova-HI)
4859 (comment "m16c addressof destination operand of size HI with additional fields at offset 16")
4860 (attrs (machine 16))
4861 (mode HI)
4862 (choices
4863 dst16-An-indirect-Mova-HI
4864 dst16-16-8-An-relative-Mova-HI
4865 dst16-16-16-An-relative-Mova-HI
4866 dst16-16-8-SB-relative-Mova-HI
4867 dst16-16-16-SB-relative-Mova-HI
4868 dst16-16-8-FB-relative-Mova-HI
4869 dst16-16-16-absolute-Mova-HI
4870 )
4871)
4872
4873(define-derived-operand
4874 (name dst32-An-indirect-Unprefixed-Mova-SI)
4875 (comment "m32c addressof An indirect destination SI")
4876 (attrs (ISA m32c))
4877 (mode SI)
4878 (args (Dst32AnUnprefixed))
4879 (syntax "[$Dst32AnUnprefixed]")
4880 (base-ifield f-4-6)
4881 (encoding
4882 (+ (f-4-3 0) (f-8-1 0) Dst32AnUnprefixed))
4883 (ifield-assertion
4884 (andif (eq f-4-3 0) (eq f-8-1 0)))
4885 (getter Dst32AnUnprefixed)
4886 (setter (nop))
4887 )
4888
4889(define-derived-operand
4890 (name dst32-16-8-An-relative-Unprefixed-Mova-SI)
4891 (comment "m32c addressof dsp:8[An] relative destination SI")
4892 (attrs (ISA m32c))
4893 (mode SI)
4894 (args (Dst32AnUnprefixed Dsp-16-u8))
4895 (syntax "${Dsp-16-u8}[$Dst32AnUnprefixed]")
4896 (base-ifield f-4-6)
4897 (encoding
4898 (+ (f-4-3 1)
4899 (f-8-1 0)
4900 Dsp-16-u8
4901 Dst32AnUnprefixed))
4902 (ifield-assertion
4903 (andif (eq f-4-3 1) (eq f-8-1 0)))
4904 (getter (add Dsp-16-u8 Dst32AnUnprefixed))
4905 (setter (nop))
4906)
4907
4908(define-derived-operand
4909 (name dst32-16-16-An-relative-Unprefixed-Mova-SI)
4910 (comment
4911 "m32c addressof dsp:16[An] relative destination SI")
4912 (attrs (ISA m32c))
4913 (mode SI)
4914 (args (Dst32AnUnprefixed Dsp-16-u16))
4915 (syntax "${Dsp-16-u16}[$Dst32AnUnprefixed]")
4916 (base-ifield f-4-6)
4917 (encoding
4918 (+ (f-4-3 2)
4919 (f-8-1 0)
4920 Dsp-16-u16
4921 Dst32AnUnprefixed))
4922 (ifield-assertion
4923 (andif (eq f-4-3 2) (eq f-8-1 0)))
4924 (getter (add Dsp-16-u16 Dst32AnUnprefixed))
4925 (setter (nop))
4926 )
4927
4928(define-derived-operand
4929 (name dst32-16-24-An-relative-Unprefixed-Mova-SI)
4930 (comment "addressof m32c dsp:16[An] relative destination SI")
4931 (attrs (ISA m32c))
4932 (mode SI)
4933 (args (Dst32AnUnprefixed Dsp-16-u24))
4934 (syntax "${Dsp-16-u24}[$Dst32AnUnprefixed]")
4935 (base-ifield f-4-6)
4936 (encoding
4937 (+ (f-4-3 3)
4938 (f-8-1 0)
4939 Dsp-16-u24
4940 Dst32AnUnprefixed))
4941 (ifield-assertion
4942 (andif (eq f-4-3 3) (eq f-8-1 0)))
4943 (getter (add Dsp-16-u24 Dst32AnUnprefixed))
4944 (setter (nop))
4945 )
4946
4947(define-derived-operand
4948 (name dst32-16-8-SB-relative-Unprefixed-Mova-SI)
4949 (comment "m32c addressof dsp:8[sb] relative destination SI")
4950 (attrs (ISA m32c))
4951 (mode SI)
4952 (args (Dsp-16-u8))
4953 (syntax "${Dsp-16-u8}[sb]")
4954 (base-ifield f-4-6)
4955 (encoding (+ (f-4-3 1) (f-8-2 2) Dsp-16-u8))
4956 (ifield-assertion
4957 (andif (eq f-4-3 1) (eq f-8-2 2)))
4958 (getter (add Dsp-16-u8 (reg h-sb)))
4959 (setter (nop))
4960 )
4961
4962(define-derived-operand
4963 (name dst32-16-16-SB-relative-Unprefixed-Mova-SI)
4964 (comment "m32c addressof dsp:16[sb] relative destination SI")
4965 (attrs (ISA m32c))
4966 (mode SI)
4967 (args (Dsp-16-u16))
4968 (syntax "${Dsp-16-u16}[sb]")
4969 (base-ifield f-4-6)
4970 (encoding (+ (f-4-3 2) (f-8-2 2) Dsp-16-u16))
4971 (ifield-assertion
4972 (andif (eq f-4-3 2) (eq f-8-2 2)))
4973 (getter (add Dsp-16-u16 (reg h-sb)))
4974 (setter (nop))
4975 )
4976
4977(define-derived-operand
4978 (name dst32-16-8-FB-relative-Unprefixed-Mova-SI)
4979 (comment "m32c addressof dsp:8[fb] relative destination SI")
4980 (attrs (ISA m32c))
4981 (mode SI)
4982 (args (Dsp-16-s8))
4983 (syntax "${Dsp-16-s8}[fb]")
4984 (base-ifield f-4-6)
4985 (encoding (+ (f-4-3 1) (f-8-2 3) Dsp-16-s8))
4986 (ifield-assertion
4987 (andif (eq f-4-3 1) (eq f-8-2 3)))
4988 (getter (add Dsp-16-s8 (reg h-fb)))
4989 (setter (nop))
4990 )
4991
4992(define-derived-operand
4993 (name dst32-16-16-FB-relative-Unprefixed-Mova-SI)
4994 (comment "m32c addressof dsp:16[fb] relative destination SI")
4995 (attrs (ISA m32c))
4996 (mode SI)
4997 (args (Dsp-16-s16))
4998 (syntax "${Dsp-16-s16}[fb]")
4999 (base-ifield f-4-6)
5000 (encoding (+ (f-4-3 2) (f-8-2 3) Dsp-16-s16))
5001 (ifield-assertion
5002 (andif (eq f-4-3 2) (eq f-8-2 3)))
5003 (getter (add Dsp-16-s16 (reg h-fb)))
5004 (setter (nop))
5005 )
5006
5007(define-derived-operand
5008 (name dst32-16-16-absolute-Unprefixed-Mova-SI)
5009 (comment "m32c addressof absolute address SI") (attrs (ISA m32c))
5010 (mode SI)
5011 (args (Dsp-16-u16))
5012 (syntax "${Dsp-16-u16}")
5013 (base-ifield f-4-6)
5014 (encoding (+ (f-4-3 3) (f-8-2 3) Dsp-16-u16))
5015 (ifield-assertion
5016 (andif (eq f-4-3 3) (eq f-8-2 3)))
5017 (getter Dsp-16-u16)
5018 (setter (nop))
5019 )
5020
5021(define-derived-operand
5022 (name dst32-16-24-absolute-Unprefixed-Mova-SI)
5023 (comment "m32c addressof absolute address SI") (attrs (ISA m32c))
5024 (mode SI)
5025 (args (Dsp-16-u24))
5026 (syntax "${Dsp-16-u24}")
5027 (base-ifield f-4-6)
5028 (encoding (+ (f-4-3 3) (f-8-2 2) Dsp-16-u24))
5029 (ifield-assertion
5030 (andif (eq f-4-3 3) (eq f-8-2 2)))
5031 (getter Dsp-16-u24)
5032 (setter (nop))
5033 )
5034
5035(define-anyof-operand
5036 (name dst32-16-Unprefixed-Mova-SI)
5037 (comment
5038 "m32c addressof destination operand of size SI with additional fields at offset 16")
5039 (attrs (ISA m32c))
5040 (mode SI)
5041 (choices
5042 dst32-An-indirect-Unprefixed-Mova-SI
5043 dst32-16-8-An-relative-Unprefixed-Mova-SI
5044 dst32-16-16-An-relative-Unprefixed-Mova-SI
5045 dst32-16-24-An-relative-Unprefixed-Mova-SI
5046 dst32-16-8-SB-relative-Unprefixed-Mova-SI
5047 dst32-16-16-SB-relative-Unprefixed-Mova-SI
5048 dst32-16-8-FB-relative-Unprefixed-Mova-SI
5049 dst32-16-16-FB-relative-Unprefixed-Mova-SI
5050 dst32-16-16-absolute-Unprefixed-Mova-SI
5051 dst32-16-24-absolute-Unprefixed-Mova-SI))
5052
5053(define-pmacro (dst32-16-operand xmode)
5054 (begin
5055 (define-anyof-operand
5056 (name (.sym dst32-16-Unprefixed- xmode))
5057 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16"))
5058 (attrs (machine 32))
5059 (mode xmode)
5060 (choices
5061 (.sym dst32-Rn-direct-Unprefixed- xmode)
5062 (.sym dst32-An-direct-Unprefixed- xmode)
5063 (.sym dst32-An-indirect-Unprefixed- xmode)
5064 (.sym dst32-16-8-An-relative-Unprefixed- xmode)
5065 (.sym dst32-16-16-An-relative-Unprefixed- xmode)
5066 (.sym dst32-16-24-An-relative-Unprefixed- xmode)
5067 (.sym dst32-16-8-SB-relative-Unprefixed- xmode)
5068 (.sym dst32-16-16-SB-relative-Unprefixed- xmode)
5069 (.sym dst32-16-8-FB-relative-Unprefixed- xmode)
5070 (.sym dst32-16-16-FB-relative-Unprefixed- xmode)
5071 (.sym dst32-16-16-absolute-Unprefixed- xmode)
5072 (.sym dst32-16-24-absolute-Unprefixed- xmode)
5073 )
5074 )
5075 (define-anyof-operand
5076 (name (.sym dst32-16-8-Unprefixed- xmode))
5077 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16"))
5078 (attrs (machine 32))
5079 (mode xmode)
5080 (choices
5081 (.sym dst32-16-8-An-relative-Unprefixed- xmode)
5082 (.sym dst32-16-8-SB-relative-Unprefixed- xmode)
5083 (.sym dst32-16-8-FB-relative-Unprefixed- xmode)
5084 )
5085 )
5086 (define-anyof-operand
5087 (name (.sym dst32-16-16-Unprefixed- xmode))
5088 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16"))
5089 (attrs (machine 32))
5090 (mode xmode)
5091 (choices
5092 (.sym dst32-16-16-An-relative-Unprefixed- xmode)
5093 (.sym dst32-16-16-SB-relative-Unprefixed- xmode)
5094 (.sym dst32-16-16-FB-relative-Unprefixed- xmode)
5095 (.sym dst32-16-16-absolute-Unprefixed- xmode)
5096 )
5097 )
5098 (define-anyof-operand
5099 (name (.sym dst32-16-24-Unprefixed- xmode))
5100 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16"))
5101 (attrs (machine 32))
5102 (mode xmode)
5103 (choices
5104 (.sym dst32-16-24-An-relative-Unprefixed- xmode)
5105 (.sym dst32-16-24-absolute-Unprefixed- xmode)
5106 )
5107 )
5108 )
5109)
5110
5111(dst32-16-operand QI)
5112(dst32-16-operand HI)
5113(dst32-16-operand SI)
5114
5115(define-pmacro (dst32-16-Ext-operand smode dmode)
5116 (begin
5117 (define-anyof-operand
5118 (name (.sym dst32-16-ExtUnprefixed- smode))
5119 (comment (.str "m32c destination operand of size " smode " with additional fields at offset 16"))
5120 (attrs (machine 32))
5121 (mode dmode)
5122 (choices
5123 (.sym dst32-Rn-direct-ExtUnprefixed- smode)
5124 (.sym dst32-An-direct-Unprefixed- dmode) ; ExtUnprefixed mode not required for this operand -- use the normal dmode version
5125 (.sym dst32-An-indirect-ExtUnprefixed- smode)
5126 (.sym dst32-16-8-An-relative-ExtUnprefixed- smode)
5127 (.sym dst32-16-16-An-relative-ExtUnprefixed- smode)
5128 (.sym dst32-16-24-An-relative-ExtUnprefixed- smode)
5129 (.sym dst32-16-8-SB-relative-ExtUnprefixed- smode)
5130 (.sym dst32-16-16-SB-relative-ExtUnprefixed- smode)
5131 (.sym dst32-16-8-FB-relative-ExtUnprefixed- smode)
5132 (.sym dst32-16-16-FB-relative-ExtUnprefixed- smode)
5133 (.sym dst32-16-16-absolute-ExtUnprefixed- smode)
5134 (.sym dst32-16-24-absolute-ExtUnprefixed- smode)
5135 )
5136 )
5137 )
5138)
5139
5140(dst32-16-Ext-operand QI HI)
5141(dst32-16-Ext-operand HI SI)
5142
5143(define-anyof-operand
5144 (name dst32-16-Unprefixed-Mulex-HI)
5145 (comment "m32c destination operand of size HI with additional fields at offset 16")
5146 (attrs (machine 32))
5147 (mode HI)
5148 (choices
5149 dst32-R3-direct-Unprefixed-HI
5150 dst32-An-direct-Unprefixed-HI
5151 dst32-An-indirect-Unprefixed-HI
5152 dst32-16-8-An-relative-Unprefixed-HI
5153 dst32-16-16-An-relative-Unprefixed-HI
5154 dst32-16-24-An-relative-Unprefixed-HI
5155 dst32-16-8-SB-relative-Unprefixed-HI
5156 dst32-16-16-SB-relative-Unprefixed-HI
5157 dst32-16-8-FB-relative-Unprefixed-HI
5158 dst32-16-16-FB-relative-Unprefixed-HI
5159 dst32-16-16-absolute-Unprefixed-HI
5160 dst32-16-24-absolute-Unprefixed-HI
5161 )
5162)
5163;-------------------------------------------------------------
5164; Destination operands with possible additional fields at offset 24 bits
5165;-------------------------------------------------------------
5166
5167(define-pmacro (dst16-24-operand xmode)
5168 (begin
5169 (define-anyof-operand
5170 (name (.sym dst16-24- xmode))
5171 (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 24"))
5172 (attrs (machine 16))
5173 (mode xmode)
5174 (choices
5175 (.sym dst16-Rn-direct- xmode)
5176 (.sym dst16-An-direct- xmode)
5177 (.sym dst16-An-indirect- xmode)
5178 (.sym dst16-24-8-An-relative- xmode)
5179 (.sym dst16-24-16-An-relative- xmode)
5180 (.sym dst16-24-8-SB-relative- xmode)
5181 (.sym dst16-24-16-SB-relative- xmode)
5182 (.sym dst16-24-8-FB-relative- xmode)
5183 (.sym dst16-24-16-absolute- xmode)
5184 )
5185 )
5186 )
5187)
5188
5189(dst16-24-operand QI)
5190(dst16-24-operand HI)
5191
5192(define-pmacro (dst32-24-operand xmode)
5193 (begin
5194 (define-anyof-operand
5195 (name (.sym dst32-24-Unprefixed- xmode))
5196 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
5197 (attrs (machine 32))
5198 (mode xmode)
5199 (choices
5200 (.sym dst32-Rn-direct-Unprefixed- xmode)
5201 (.sym dst32-An-direct-Unprefixed- xmode)
5202 (.sym dst32-An-indirect-Unprefixed- xmode)
5203 (.sym dst32-24-8-An-relative-Unprefixed- xmode)
5204 (.sym dst32-24-16-An-relative-Unprefixed- xmode)
5205 (.sym dst32-24-24-An-relative-Unprefixed- xmode)
5206 (.sym dst32-24-8-SB-relative-Unprefixed- xmode)
5207 (.sym dst32-24-16-SB-relative-Unprefixed- xmode)
5208 (.sym dst32-24-8-FB-relative-Unprefixed- xmode)
5209 (.sym dst32-24-16-FB-relative-Unprefixed- xmode)
5210 (.sym dst32-24-16-absolute-Unprefixed- xmode)
5211 (.sym dst32-24-24-absolute-Unprefixed- xmode)
5212 )
5213 )
5214 (define-anyof-operand
5215 (name (.sym dst32-24-Prefixed- xmode))
5216 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
5217 (attrs (machine 32))
5218 (mode xmode)
5219 (choices
5220 (.sym dst32-Rn-direct-Prefixed- xmode)
5221 (.sym dst32-An-direct-Prefixed- xmode)
5222 (.sym dst32-An-indirect-Prefixed- xmode)
5223 (.sym dst32-24-8-An-relative-Prefixed- xmode)
5224 (.sym dst32-24-16-An-relative-Prefixed- xmode)
5225 (.sym dst32-24-24-An-relative-Prefixed- xmode)
5226 (.sym dst32-24-8-SB-relative-Prefixed- xmode)
5227 (.sym dst32-24-16-SB-relative-Prefixed- xmode)
5228 (.sym dst32-24-8-FB-relative-Prefixed- xmode)
5229 (.sym dst32-24-16-FB-relative-Prefixed- xmode)
5230 (.sym dst32-24-16-absolute-Prefixed- xmode)
5231 (.sym dst32-24-24-absolute-Prefixed- xmode)
5232 )
5233 )
5234 (define-anyof-operand
5235 (name (.sym dst32-24-8-Prefixed- xmode))
5236 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
5237 (attrs (machine 32))
5238 (mode xmode)
5239 (choices
5240 (.sym dst32-24-8-An-relative-Prefixed- xmode)
5241 (.sym dst32-24-8-SB-relative-Prefixed- xmode)
5242 (.sym dst32-24-8-FB-relative-Prefixed- xmode)
5243 )
5244 )
5245 (define-anyof-operand
5246 (name (.sym dst32-24-16-Prefixed- xmode))
5247 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
5248 (attrs (machine 32))
5249 (mode xmode)
5250 (choices
5251 (.sym dst32-24-16-An-relative-Prefixed- xmode)
5252 (.sym dst32-24-16-SB-relative-Prefixed- xmode)
5253 (.sym dst32-24-16-FB-relative-Prefixed- xmode)
5254 (.sym dst32-24-16-absolute-Prefixed- xmode)
5255 )
5256 )
5257 (define-anyof-operand
5258 (name (.sym dst32-24-24-Prefixed- xmode))
5259 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
5260 (attrs (machine 32))
5261 (mode xmode)
5262 (choices
5263 (.sym dst32-24-24-An-relative-Prefixed- xmode)
5264 (.sym dst32-24-24-absolute-Prefixed- xmode)
5265 )
5266 )
5267; (define-anyof-operand
5268; (name (.sym dst32-24-indirect- xmode))
5269; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
5270; (attrs (machine 32))
5271; (mode xmode)
5272; (choices
5273; (.sym dst32-An-indirect-indirect- xmode)
5274; (.sym dst32-24-8-An-relative-indirect- xmode)
5275; (.sym dst32-24-16-An-relative-indirect- xmode)
5276; (.sym dst32-24-24-An-relative-indirect- xmode)
5277; (.sym dst32-24-8-SB-relative-indirect- xmode)
5278; (.sym dst32-24-16-SB-relative-indirect- xmode)
5279; (.sym dst32-24-8-FB-relative-indirect- xmode)
5280; (.sym dst32-24-16-FB-relative-indirect- xmode)
5281; )
5282; )
5283; (define-anyof-operand
5284; (name (.sym dst32-basic-indirect- xmode))
5285; (comment (.str "m32c destination operand of size " xmode " with no additional fields"))
5286; (attrs (machine 32))
5287; (mode xmode)
5288; (choices
5289; (.sym dst32-An-indirect-indirect- xmode)
5290; )
5291; )
5292; (define-anyof-operand
5293; (name (.sym dst32-24-8-indirect- xmode))
5294; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
5295; (attrs (machine 32))
5296; (mode xmode)
5297; (choices
5298; (.sym dst32-24-8-An-relative-indirect- xmode)
5299; (.sym dst32-24-8-SB-relative-indirect- xmode)
5300; (.sym dst32-24-8-FB-relative-indirect- xmode)
5301; )
5302; )
5303; (define-anyof-operand
5304; (name (.sym dst32-24-16-indirect- xmode))
5305; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
5306; (attrs (machine 32))
5307; (mode xmode)
5308; (choices
5309; (.sym dst32-24-16-An-relative-indirect- xmode)
5310; (.sym dst32-24-16-SB-relative-indirect- xmode)
5311; (.sym dst32-24-16-FB-relative-indirect- xmode)
5312; )
5313; )
5314; (define-anyof-operand
5315; (name (.sym dst32-24-24-indirect- xmode))
5316; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
5317; (attrs (machine 32))
5318; (mode xmode)
5319; (choices
5320; (.sym dst32-24-24-An-relative-indirect- xmode)
5321; )
5322; )
5323; (define-anyof-operand
5324; (name (.sym dst32-24-absolute-indirect- xmode))
5325; (comment (.str "m32c destination operand of size " xmode " absolute indirect"))
5326; (attrs (machine 32))
5327; (mode xmode)
5328; (choices
5329; (.sym dst32-24-16-absolute-indirect-derived- xmode)
5330; (.sym dst32-24-24-absolute-indirect-derived- xmode)
5331; )
5332; )
5333; (define-anyof-operand
5334; (name (.sym dst32-24-16-absolute-indirect- xmode))
5335; (comment (.str "m32c destination operand of size " xmode " absolute indirect"))
5336; (attrs (machine 32))
5337; (mode xmode)
5338; (choices
5339; (.sym dst32-24-16-absolute-indirect-derived- xmode)
5340; )
5341; )
5342; (define-anyof-operand
5343; (name (.sym dst32-24-24-absolute-indirect- xmode))
5344; (comment (.str "m32c destination operand of size " xmode " absolute indirect"))
5345; (attrs (machine 32))
5346; (mode xmode)
5347; (choices
5348; (.sym dst32-24-24-absolute-indirect-derived- xmode)
5349; )
5350; )
5351 )
5352)
5353
5354(dst32-24-operand QI)
5355(dst32-24-operand HI)
5356(dst32-24-operand SI)
5357
5358;-------------------------------------------------------------
5359; Destination operands with possible additional fields at offset 32 bits
5360;-------------------------------------------------------------
5361
5362(define-pmacro (dst16-32-operand xmode)
5363 (begin
5364 (define-anyof-operand
5365 (name (.sym dst16-32- xmode))
5366 (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 32"))
5367 (attrs (machine 16))
5368 (mode xmode)
5369 (choices
5370 (.sym dst16-Rn-direct- xmode)
5371 (.sym dst16-An-direct- xmode)
5372 (.sym dst16-An-indirect- xmode)
5373 (.sym dst16-32-8-An-relative- xmode)
5374 (.sym dst16-32-16-An-relative- xmode)
5375 (.sym dst16-32-8-SB-relative- xmode)
5376 (.sym dst16-32-16-SB-relative- xmode)
5377 (.sym dst16-32-8-FB-relative- xmode)
5378 (.sym dst16-32-16-absolute- xmode)
5379 )
5380 )
5381 )
5382)
5383(dst16-32-operand QI)
5384(dst16-32-operand HI)
5385
5386; This macro actually handles operands at offset 32, 40 and 48 bits
5387(define-pmacro (dst32-32plus-operand offset xmode)
5388 (begin
5389 (define-anyof-operand
5390 (name (.sym dst32- offset -Unprefixed- xmode))
5391 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32"))
5392 (attrs (machine 32))
5393 (mode xmode)
5394 (choices
5395 (.sym dst32-Rn-direct-Unprefixed- xmode)
5396 (.sym dst32-An-direct-Unprefixed- xmode)
5397 (.sym dst32-An-indirect-Unprefixed- xmode)
5398 (.sym dst32- offset -8-An-relative-Unprefixed- xmode)
5399 (.sym dst32- offset -16-An-relative-Unprefixed- xmode)
5400 (.sym dst32- offset -24-An-relative-Unprefixed- xmode)
5401 (.sym dst32- offset -8-SB-relative-Unprefixed- xmode)
5402 (.sym dst32- offset -16-SB-relative-Unprefixed- xmode)
5403 (.sym dst32- offset -8-FB-relative-Unprefixed- xmode)
5404 (.sym dst32- offset -16-FB-relative-Unprefixed- xmode)
5405 (.sym dst32- offset -16-absolute-Unprefixed- xmode)
5406 (.sym dst32- offset -24-absolute-Unprefixed- xmode)
5407 )
5408 )
5409 (define-anyof-operand
5410 (name (.sym dst32- offset -Prefixed- xmode))
5411 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32"))
5412 (attrs (machine 32))
5413 (mode xmode)
5414 (choices
5415 (.sym dst32-Rn-direct-Prefixed- xmode)
5416 (.sym dst32-An-direct-Prefixed- xmode)
5417 (.sym dst32-An-indirect-Prefixed- xmode)
5418 (.sym dst32- offset -8-An-relative-Prefixed- xmode)
5419 (.sym dst32- offset -16-An-relative-Prefixed- xmode)
5420 (.sym dst32- offset -24-An-relative-Prefixed- xmode)
5421 (.sym dst32- offset -8-SB-relative-Prefixed- xmode)
5422 (.sym dst32- offset -16-SB-relative-Prefixed- xmode)
5423 (.sym dst32- offset -8-FB-relative-Prefixed- xmode)
5424 (.sym dst32- offset -16-FB-relative-Prefixed- xmode)
5425 (.sym dst32- offset -16-absolute-Prefixed- xmode)
5426 (.sym dst32- offset -24-absolute-Prefixed- xmode)
5427 )
5428 )
5429; (define-anyof-operand
5430; (name (.sym dst32- offset -indirect- xmode))
5431; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32"))
5432; (attrs (machine 32))
5433; (mode xmode)
5434; (choices
5435; (.sym dst32-An-indirect-indirect- xmode)
5436; (.sym dst32- offset -8-An-relative-indirect- xmode)
5437; (.sym dst32- offset -16-An-relative-indirect- xmode)
5438; (.sym dst32- offset -24-An-relative-indirect- xmode)
5439; (.sym dst32- offset -8-SB-relative-indirect- xmode)
5440; (.sym dst32- offset -16-SB-relative-indirect- xmode)
5441; (.sym dst32- offset -8-FB-relative-indirect- xmode)
5442; (.sym dst32- offset -16-FB-relative-indirect- xmode)
5443; )
5444; )
5445; (define-anyof-operand
5446; (name (.sym dst32- offset -absolute-indirect- xmode))
5447; (comment (.str "m32c destination operand of size " xmode " absolute indirect"))
5448; (attrs (machine 32))
5449; (mode xmode)
5450; (choices
5451; (.sym dst32- offset -16-absolute-indirect-derived- xmode)
5452; (.sym dst32- offset -24-absolute-indirect-derived- xmode)
5453; )
5454; )
5455 )
5456)
5457
5458(dst32-32plus-operand 32 QI)
5459(dst32-32plus-operand 32 HI)
5460(dst32-32plus-operand 32 SI)
5461(dst32-32plus-operand 40 QI)
5462(dst32-32plus-operand 40 HI)
5463(dst32-32plus-operand 40 SI)
5464
5465;-------------------------------------------------------------
5466; Destination operands with possible additional fields at offset 48 bits
5467;-------------------------------------------------------------
5468
5469(define-pmacro (dst32-48-operand offset xmode)
5470 (begin
5471 (define-anyof-operand
5472 (name (.sym dst32- offset -Prefixed- xmode))
5473 (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32"))
5474 (attrs (machine 32))
5475 (mode xmode)
5476 (choices
5477 (.sym dst32-Rn-direct-Prefixed- xmode)
5478 (.sym dst32-An-direct-Prefixed- xmode)
5479 (.sym dst32-An-indirect-Prefixed- xmode)
5480 (.sym dst32- offset -8-An-relative-Prefixed- xmode)
5481 (.sym dst32- offset -16-An-relative-Prefixed- xmode)
5482 (.sym dst32- offset -24-An-relative-Prefixed- xmode)
5483 (.sym dst32- offset -8-SB-relative-Prefixed- xmode)
5484 (.sym dst32- offset -16-SB-relative-Prefixed- xmode)
5485 (.sym dst32- offset -8-FB-relative-Prefixed- xmode)
5486 (.sym dst32- offset -16-FB-relative-Prefixed- xmode)
5487 (.sym dst32- offset -16-absolute-Prefixed- xmode)
5488 (.sym dst32- offset -24-absolute-Prefixed- xmode)
5489 )
5490 )
5491; (define-anyof-operand
5492; (name (.sym dst32- offset -indirect- xmode))
5493; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32"))
5494; (attrs (machine 32))
5495; (mode xmode)
5496; (choices
5497; (.sym dst32-An-indirect-indirect- xmode)
5498; (.sym dst32- offset -8-An-relative-indirect- xmode)
5499; (.sym dst32- offset -16-An-relative-indirect- xmode)
5500; (.sym dst32- offset -24-An-relative-indirect- xmode)
5501; (.sym dst32- offset -8-SB-relative-indirect- xmode)
5502; (.sym dst32- offset -16-SB-relative-indirect- xmode)
5503; (.sym dst32- offset -8-FB-relative-indirect- xmode)
5504; (.sym dst32- offset -16-FB-relative-indirect- xmode)
5505; )
5506; )
5507; (define-anyof-operand
5508; (name (.sym dst32- offset -absolute-indirect- xmode))
5509; (comment (.str "m32c destination operand of size " xmode " absolute indirect"))
5510; (attrs (machine 32))
5511; (mode xmode)
5512; (choices
5513; (.sym dst32- offset -16-absolute-indirect-derived- xmode)
5514; (.sym dst32- offset -24-absolute-indirect-derived- xmode)
5515; )
5516; )
5517 )
5518)
5519
5520(dst32-48-operand 48 QI)
5521(dst32-48-operand 48 HI)
5522(dst32-48-operand 48 SI)
5523
5524;-------------------------------------------------------------
5525; Bit operands for m16c
5526;-------------------------------------------------------------
5527
5528(define-pmacro (bit16-operand offset)
5529 (begin
5530 (define-anyof-operand
5531 (name (.sym bit16- offset))
5532 (comment (.str "m16c bit operand with possible additional fields at offset 24"))
5533 (attrs (machine 16))
5534 (mode BI)
5535 (choices
5536 bit16-Rn-direct
5537 bit16-An-direct
5538 bit16-An-indirect
5539 (.sym bit16- offset -8-An-relative)
5540 (.sym bit16- offset -16-An-relative)
5541 (.sym bit16- offset -8-SB-relative)
5542 (.sym bit16- offset -16-SB-relative)
5543 (.sym bit16- offset -8-FB-relative)
5544 (.sym bit16- offset -16-absolute)
5545 )
5546 )
5547 (define-anyof-operand
5548 (name (.sym bit16- offset -basic))
5549 (comment (.str "m16c bit operand with no additional fields"))
5550 (attrs (machine 16))
5551 (mode BI)
5552 (choices
5553 bit16-An-indirect
5554 )
5555 )
5556 (define-anyof-operand
5557 (name (.sym bit16- offset -8))
5558 (comment (.str "m16c bit operand with possible additional fields at offset 24"))
5559 (attrs (machine 16))
5560 (mode BI)
5561 (choices
5562 bit16-Rn-direct
5563 bit16-An-direct
5564 (.sym bit16- offset -8-An-relative)
5565 (.sym bit16- offset -8-SB-relative)
5566 (.sym bit16- offset -8-FB-relative)
5567 )
5568 )
5569 (define-anyof-operand
5570 (name (.sym bit16- offset -16))
5571 (comment (.str "m16c bit operand with possible additional fields at offset 24"))
5572 (attrs (machine 16))
5573 (mode BI)
5574 (choices
5575 (.sym bit16- offset -16-An-relative)
5576 (.sym bit16- offset -16-SB-relative)
5577 (.sym bit16- offset -16-absolute)
5578 )
5579 )
5580 )
5581)
5582
5583(bit16-operand 16)
5584
5585;-------------------------------------------------------------
5586; Bit operands for m32c
5587;-------------------------------------------------------------
5588
5589(define-pmacro (bit32-operand offset group)
5590 (begin
5591 (define-anyof-operand
5592 (name (.sym bit32- offset - group))
5593 (comment (.str "m32c bit operand with possible additional fields at offset 24"))
5594 (attrs (machine 32))
5595 (mode BI)
5596 (choices
5597 (.sym bit32-Rn-direct- group)
5598 (.sym bit32-An-direct- group)
5599 (.sym bit32-An-indirect- group)
5600 (.sym bit32- offset -11-An-relative- group)
5601 (.sym bit32- offset -19-An-relative- group)
5602 (.sym bit32- offset -27-An-relative- group)
5603 (.sym bit32- offset -11-SB-relative- group)
5604 (.sym bit32- offset -19-SB-relative- group)
5605 (.sym bit32- offset -11-FB-relative- group)
5606 (.sym bit32- offset -19-FB-relative- group)
5607 (.sym bit32- offset -19-absolute- group)
5608 (.sym bit32- offset -27-absolute- group)
5609 )
5610 )
5611 )
5612)
5613
5614(bit32-operand 16 Unprefixed)
5615(bit32-operand 24 Prefixed)
5616
5617(define-anyof-operand
5618 (name bit32-basic-Unprefixed)
5619 (comment "m32c bit operand with no additional fields")
5620 (attrs (machine 32))
5621 (mode BI)
5622 (choices
5623 bit32-Rn-direct-Unprefixed
5624 bit32-An-direct-Unprefixed
5625 bit32-An-indirect-Unprefixed
5626 )
5627)
5628
5629(define-anyof-operand
5630 (name bit32-16-8-Unprefixed)
5631 (comment "m32c bit operand with 8 bit additional fields")
5632 (attrs (machine 32))
5633 (mode BI)
5634 (choices
5635 bit32-16-11-An-relative-Unprefixed
5636 bit32-16-11-SB-relative-Unprefixed
5637 bit32-16-11-FB-relative-Unprefixed
5638 )
5639)
5640
5641(define-anyof-operand
5642 (name bit32-16-16-Unprefixed)
5643 (comment "m32c bit operand with 16 bit additional fields")
5644 (attrs (machine 32))
5645 (mode BI)
5646 (choices
5647 bit32-16-19-An-relative-Unprefixed
5648 bit32-16-19-SB-relative-Unprefixed
5649 bit32-16-19-FB-relative-Unprefixed
5650 bit32-16-19-absolute-Unprefixed
5651 )
5652)
5653
5654(define-anyof-operand
5655 (name bit32-16-24-Unprefixed)
5656 (comment "m32c bit operand with 24 bit additional fields")
5657 (attrs (machine 32))
5658 (mode BI)
5659 (choices
5660 bit32-16-27-An-relative-Unprefixed
5661 bit32-16-27-absolute-Unprefixed
5662 )
5663)
5664
5665;-------------------------------------------------------------
5666; Operands for short format binary insns
5667;-------------------------------------------------------------
5668
5669(define-anyof-operand
5670 (name src16-2-S)
5671 (comment "m16c source operand of size QI for short format insns")
5672 (attrs (machine 16))
5673 (mode QI)
5674 (choices
5675 src16-2-S-8-SB-relative-QI
5676 src16-2-S-8-FB-relative-QI
5677 src16-2-S-16-absolute-QI
5678 )
5679)
5680
5681(define-anyof-operand
5682 (name src32-2-S-QI)
5683 (comment "m32c source operand of size QI for short format insns")
5684 (attrs (machine 32))
5685 (mode QI)
5686 (choices
5687 src32-2-S-8-SB-relative-QI
5688 src32-2-S-8-FB-relative-QI
5689 src32-2-S-16-absolute-QI
5690 )
5691)
5692
5693(define-anyof-operand
5694 (name src32-2-S-HI)
5695 (comment "m32c source operand of size QI for short format insns")
5696 (attrs (machine 32))
5697 (mode HI)
5698 (choices
5699 src32-2-S-8-SB-relative-HI
5700 src32-2-S-8-FB-relative-HI
5701 src32-2-S-16-absolute-HI
5702 )
5703)
5704
5705(define-anyof-operand
5706 (name Dst16-3-S-8)
5707 (comment "m16c destination operand of size QI for short format insns")
5708 (attrs (machine 16))
5709 (mode QI)
5710 (choices
5711 dst16-3-S-R0l-direct-QI
5712 dst16-3-S-R0h-direct-QI
5713 dst16-3-S-8-8-SB-relative-QI
5714 dst16-3-S-8-8-FB-relative-QI
5715 dst16-3-S-8-16-absolute-QI
5716 )
5717)
5718
5719(define-anyof-operand
5720 (name Dst16-3-S-16)
5721 (comment "m16c destination operand of size QI for short format insns")
5722 (attrs (machine 16))
5723 (mode QI)
5724 (choices
5725 dst16-3-S-R0l-direct-QI
5726 dst16-3-S-R0h-direct-QI
5727 dst16-3-S-16-8-SB-relative-QI
5728 dst16-3-S-16-8-FB-relative-QI
5729 dst16-3-S-16-16-absolute-QI
5730 )
5731)
5732
5733(define-anyof-operand
5734 (name srcdst16-r0l-r0h-S)
5735 (comment "m16c r0l/r0h operand of size QI for short format insns")
5736 (attrs (machine 16))
5737 (mode SI)
5738 (choices
5739 srcdst16-r0l-r0h-S-derived
5740 )
5741)
5742
5743(define-anyof-operand
5744 (name dst32-2-S-basic-QI)
5745 (comment "m32c r0l operand of size QI for short format binary insns")
5746 (attrs (machine 32))
5747 (mode QI)
5748 (choices
5749 dst32-2-S-R0l-direct-QI
5750 )
5751)
5752
5753(define-anyof-operand
5754 (name dst32-2-S-basic-HI)
5755 (comment "m32c r0 operand of size HI for short format binary insns")
5756 (attrs (machine 32))
5757 (mode HI)
5758 (choices
5759 dst32-2-S-R0-direct-HI
5760 )
5761)
5762
5763(define-pmacro (dst32-2-S-operands xmode)
5764 (begin
5765 (define-anyof-operand
5766 (name (.sym dst32-2-S-8- xmode))
5767 (comment "m32c operand of size " xmode " for short format binary insns")
5768 (attrs (machine 32))
5769 (mode xmode)
5770 (choices
5771 (.sym dst32-2-S-8-SB-relative- xmode)
5772 (.sym dst32-2-S-8-FB-relative- xmode)
5773 )
5774 )
5775 (define-anyof-operand
5776 (name (.sym dst32-2-S-16- xmode))
5777 (comment "m32c operand of size " xmode " for short format binary insns")
5778 (attrs (machine 32))
5779 (mode xmode)
5780 (choices
5781 (.sym dst32-2-S-16-absolute- xmode)
5782 )
5783 )
5784; (define-anyof-operand
5785; (name (.sym dst32-2-S-8-indirect- xmode))
5786; (comment "m32c operand of size " xmode " for short format binary insns")
5787; (attrs (machine 32))
5788; (mode xmode)
5789; (choices
5790; (.sym dst32-2-S-8-SB-relative-indirect- xmode)
5791; (.sym dst32-2-S-8-FB-relative-indirect- xmode)
5792; )
5793; )
5794; (define-anyof-operand
5795; (name (.sym dst32-2-S-absolute-indirect- xmode))
5796; (comment "m32c operand of size " xmode " for short format binary insns")
5797; (attrs (machine 32))
5798; (mode xmode)
5799; (choices
5800; (.sym dst32-2-S-16-absolute-indirect- xmode)
5801; )
5802; )
5803 )
5804)
5805
5806(dst32-2-S-operands QI)
5807(dst32-2-S-operands HI)
5808(dst32-2-S-operands SI)
5809
5810(define-anyof-operand
5811 (name dst32-an-S)
5812 (comment "m32c An operand for short format binary insns")
5813 (attrs (machine 32))
5814 (mode HI)
5815 (choices
5816 dst32-1-S-A0-direct-HI
5817 dst32-1-S-A1-direct-HI
5818 )
5819)
5820
5821(define-anyof-operand
5822 (name bit16-11-S)
5823 (comment "m16c bit operand for short format insns")
5824 (attrs (machine 16))
5825 (mode BI)
5826 (choices
5827 bit16-11-SB-relative-S
5828 )
5829)
5830
5831(define-anyof-operand
5832 (name Rn16-push-S-anyof)
5833 (comment "m16c bit operand for short format insns")
5834 (attrs (machine 16))
5835 (mode QI)
5836 (choices
5837 Rn16-push-S-derived
5838 )
5839)
5840
5841(define-anyof-operand
5842 (name An16-push-S-anyof)
5843 (comment "m16c bit operand for short format insns")
5844 (attrs (machine 16))
5845 (mode HI)
5846 (choices
5847 An16-push-S-derived
5848 )
5849)
5850
5851;=============================================================
5852; Common macros for instruction definitions
5853;
5854(define-pmacro (set-z x)
5855 (sequence ()
5856 (set zbit (zflag x)))
5857
5858)
5859
5860(define-pmacro (set-s x)
5861 (sequence ()
5862 (set sbit (nflag x)))
5863)
5864
5865(define-pmacro (set-z-and-s x)
5866 (sequence ()
5867 (set-z x)
5868 (set-s x))
5869)
5870\f
5871;=============================================================
5872; Unary insn macros
5873;-------------------------------------------------------------
5874
c6552317 5875(define-pmacro (unary-insn-defn-g mach group mode wstr op encoding sem opg)
49f58d10 5876 (dni (.sym op mach wstr - group)
c6552317 5877 (.str op wstr opg " dst" mach "-" group "-" mode)
6772dd07 5878 ((machine mach) RL_1ADDR)
c6552317 5879 (.str op wstr opg " ${dst" mach "-" group "-" mode "}")
49f58d10
JB		 5880 encoding
5881 (sem mode (.sym dst mach - group - mode))
5882 ())
5883)
5884
c6552317
DD		 5885(define-pmacro (unary-insn-defn mach group mode wstr op encoding sem)
5886 (unary-insn-defn-g mach group mode wstr op encoding sem "")
5887)
5888
49f58d10 5889
c6552317
DD		 5890(define-pmacro (unary16-defn-g mode wstr wbit op opc1 opc2 opc3 sem opg)
5891 (unary-insn-defn-g 16 16 mode wstr op
5892 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16- mode))
5893 sem opg)
5894)
49f58d10 5895(define-pmacro (unary16-defn mode wstr wbit op opc1 opc2 opc3 sem)
c6552317 5896 (unary-16-defn-g mode wstr wbit op opc1 opc2 opc3 sem "")
49f58d10
JB		 5897)
5898
c6552317 5899(define-pmacro (unary32-defn-g mode wstr wbit op opc1 opc2 opc3 sem opg)
49f58d10
JB		 5900 (begin
5901 ; Multi insns are tried for assembly in the reverse order in which they appear here, so
5902 ; define the absolute-indirect insns first in order to prevent them from being selected
5903 ; when the mode is register-indirect
5904; (unary-insn-defn 32 24-absolute-indirect mode wstr op
5905; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) (f-20-4 opc3))
5906; sem)
c6552317
DD		 5907 (unary-insn-defn-g 32 16-Unprefixed mode wstr op
5908 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3))
5909 sem opg)
49f58d10
JB		 5910; (unary-insn-defn 32 24-indirect mode wstr op
5911; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (.sym dst32-24-indirect- mode) (f-18-2 opc2) (f-20-4 opc3))
5912; sem)
5913 )
5914)
c6552317
DD		 5915(define-pmacro (unary32-defn mode wstr wbit op opc1 opc2 opc3 sem)
5916 (unary32-defn-g mode wstr wbit op opc1 opc2 opc3 sem "")
5917)
49f58d10 5918
c6552317 5919(define-pmacro (unary-insn-mach-g mach op opc1 opc2 opc3 sem opg)
49f58d10 5920 (begin
c6552317
DD		 5921 (.apply (.sym unary mach -defn-g) (QI .b 0 op opc1 opc2 opc3 sem opg))
5922 (.apply (.sym unary mach -defn-g) (HI .w 1 op opc1 opc2 opc3 sem opg))
49f58d10
JB		 5923 )
5924)
c6552317
DD		 5925(define-pmacro (unary-insn-mach mach op opc1 opc2 opc3 sem)
5926 (unary-insn-mach-g mach op opc1 opc2 opc3 sem "")
5927)
49f58d10
JB		 5928
5929(define-pmacro (unary-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
5930 (begin
c6552317
DD		 5931 (unary-insn-mach-g 16 op opc16-1 opc16-2 opc16-3 sem "")
5932 (unary-insn-mach-g 32 op opc32-1 opc32-2 opc32-3 sem "")
5933 )
5934)
5935
5936(define-pmacro (unary-insn-g op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
5937 (begin
5938 (unary-insn-mach-g 16 op opc16-1 opc16-2 opc16-3 sem "$G")
5939 (unary-insn-mach-g 32 op opc32-1 opc32-2 opc32-3 sem "$G")
49f58d10
JB		 5940 )
5941)
5942
5943;-------------------------------------------------------------
5944; Sign/zero extension macros
5945;-------------------------------------------------------------
5946
5947(define-pmacro (ext-insn-defn mach group smode dmode wstr op encoding sem)
5948 (dni (.sym op mach wstr - group)
5949 (.str op wstr " dst" mach "-" group "-" smode)
5950 ((machine mach))
5951 (.str op wstr " ${dst" mach "-" group "-" smode "}")
5952 encoding
5953 (sem smode dmode (.sym dst mach - group - smode) (.sym dst mach - group - smode))
5954 ())
5955)
5956
5957(define-pmacro (ext16-defn smode dmode wstr wbit op opc1 opc2 opc3 sem)
5958 (ext-insn-defn 16 16-Ext smode dmode wstr op
5959 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-Ext- smode))
5960 sem)
5961)
5962
5963(define-pmacro (ext32-defn smode dmode wstr wbit op opc1 opc2 opc3 sem)
5964 (ext-insn-defn 32 16-ExtUnprefixed smode dmode wstr op
5965 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst32-16-ExtUnprefixed- smode))
5966 sem)
5967)
5968
5969(define-pmacro (ext32-binary-insn src-group dst-group op wstr encoding sem)
5970 (dni (.sym op 32 wstr - src-group - dst-group)
5971 (.str op 32 wstr " src32-" src-group "-QI,dst32-" dst-group "-HI")
5972 ((machine 32))
5973 (.str op wstr " ${src32-" src-group "-QI},${dst32-" dst-group "-HI}")
5974 encoding
5975 (sem QI HI (.sym src32- src-group -QI) (.sym dst32 - dst-group -HI))
5976 ())
5977)
5978
5979(define-pmacro (ext32-binary-defn op wstr opc1 opc2 sem)
5980 (begin
5981 (ext32-binary-insn basic-ExtPrefixed 24-Prefixed op wstr
5982 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-basic-ExtPrefixed-QI dst32-24-Prefixed-HI (f-20-4 opc2))
5983 sem)
5984 (ext32-binary-insn 24-24-Prefixed 48-Prefixed op wstr
5985 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-24-24-Prefixed-QI dst32-48-Prefixed-HI (f-20-4 opc2))
5986 sem)
5987 (ext32-binary-insn 24-16-Prefixed 40-Prefixed op wstr
5988 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-24-16-Prefixed-QI dst32-40-Prefixed-HI (f-20-4 opc2))
5989 sem)
5990 (ext32-binary-insn 24-8-Prefixed 32-Prefixed op wstr
5991 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-24-8-Prefixed-QI dst32-32-Prefixed-HI (f-20-4 opc2))
5992 sem)
5993 )
5994)
5995
5996;=============================================================
5997; Binary Arithmetic macros
5998;
5999;-------------------------------------------------------------
6000;<arith>.size:S src2,r0[l] -- for m32c
6001;-------------------------------------------------------------
6002
6003(define-pmacro (binary-arith32-S-src2 op xmode wstr wbit opc1 opc2 sem)
6004 (dni (.sym op 32 wstr .S-src2-r0- xmode)
6005 (.str op 32 wstr ":S src2,r0[l]")
6006 ((machine 32))
6007 (.str op wstr"$S ${src32-2-S-" xmode "},${Dst32R0" xmode "-S}")
6008 (+ opc1 opc2 (.sym src32-2-S- xmode) (f-7-1 wbit))
6009 (sem xmode (.sym src32-2-S- xmode) (.sym Dst32R0 xmode -S))
6010 ())
6011)
6012
6013;-------------------------------------------------------------
6014;<arith>.b:S src2,r0l/r0h -- for m16c
6015;-------------------------------------------------------------
6016
6017(define-pmacro (binary-arith16-b-S-src2 op opc1 opc2 sem)
6018 (begin
6019 (dni (.sym op 16 .b.S-src2)
6020 (.str op ".b:S src2,r0[lh]")
6021 ((machine 16))
6022 (.str op ".b$S ${src16-2-S},${Dst16RnQI-S}")
6023 (+ opc1 opc2 Dst16RnQI-S src16-2-S)
6024 (sem QI src16-2-S Dst16RnQI-S)
6025 ())
6026 (dni (.sym op 16 .b.S-r0l-r0h)
6027 (.str op ".b:S r0l/r0h")
6028 ((machine 16))
6029 (.str op ".b$S ${srcdst16-r0l-r0h-S}")
6030 (+ opc1 opc2 srcdst16-r0l-r0h-S)
6031 (if (eq srcdst16-r0l-r0h-S 0)
6032 (sem QI R0h R0l)
6033 (sem QI R0l R0h))
6034 ())
6035 )
6036)
6037
6038;-------------------------------------------------------------
6039;<arith>.b:S #imm8,dst3 -- for m16c
6040;-------------------------------------------------------------
6041
6042(define-pmacro (binary-arith16-b-S-imm8-dst3 op sz opc1 opc2 sem)
6043 (dni (.sym op 16 .b.S-imm8-dst3)
6044 (.str op sz ":S imm8,dst3")
6045 ((machine 16))
6046 (.str op sz "$S #${Imm-8-QI},${Dst16-3-S-16}")
6047 (+ opc1 opc2 Dst16-3-S-16 Imm-8-QI)
6048 (sem QI Imm-8-QI Dst16-3-S-16)
6049 ())
6050)
6051
6052;-------------------------------------------------------------
6053;<arith>.size:Q #imm4,sp -- for m16c
6054;-------------------------------------------------------------
6055
6056(define-pmacro (binary-arith16-Q-sp op opc1 opc2 opc3 sem)
92e0a941
DD		 6057 (dni (.sym op 16 -wQ-sp)
6058 (.str op ".w:q #imm4,sp")
49f58d10 6059 ((machine 16))
92e0a941 6060 (.str op ".w$Q #${Imm-12-s4},sp")
49f58d10
JB		 6061 (+ opc1 opc2 opc3 Imm-12-s4)
6062 (sem QI Imm-12-s4 sp)
6063 ())
6064)
6065
6066;-------------------------------------------------------------
6067;<arith>.size:G #imm,sp -- for m16c
6068;-------------------------------------------------------------
6069
6070(define-pmacro (binary-arith16-G-sp-defn mode wstr wbit op opc1 opc2 opc3 opc4 sem)
6071 (dni (.sym op 16 wstr - G-sp)
6072 (.str op wstr " imm-sp " mode)
6073 ((machine 16))
6074 (.str op wstr "$G #${Imm-16-" mode "},sp")
6075 (+ opc1 opc2 (f-7-1 wbit) opc3 opc4 (.sym Imm-16- mode))
6076 (sem mode (.sym Imm-16- mode) sp)
6077 ())
6078)
6079
6080(define-pmacro (binary-arith16-G-sp op opc1 opc2 opc3 opc4 sem)
6081 (begin
6082 (binary-arith16-G-sp-defn QI .b 0 op opc1 opc2 opc3 opc4 sem)
6083 (binary-arith16-G-sp-defn HI .w 1 op opc1 opc2 opc3 opc4 sem)
6084 )
6085)
6086
6087;-------------------------------------------------------------
6088;<arith>.size:G #imm,dst -- for m16c and m32c
6089;-------------------------------------------------------------
6090
6091(define-pmacro (binary-arith-imm-dst-defn mach src dstgroup dmode wstr op suffix encoding sem)
6092 (dni (.sym op mach wstr - imm-G - dstgroup)
6093 (.str op wstr " " mach "-imm-G-" dstgroup "-" dmode)
6772dd07 6094 ((machine mach) RL_1ADDR)
49f58d10
JB		 6095 (.str op wstr "$"suffix " #${" src "},${dst" mach "-" dstgroup "-" dmode "}")
6096 encoding
6097 (sem dmode src (.sym dst mach - dstgroup - dmode))
6098 ())
6099)
6100
6101; m16c variants
6102(define-pmacro (binary-arith16-imm-dst-defn smode dmode wstr wbit op suffix opc1 opc2 opc3 sem)
6103 (begin
6104 (binary-arith-imm-dst-defn 16 (.sym Imm-32- smode) 16-16 dmode wstr op suffix
6105 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- dmode) (.sym Imm-32- smode))
6106 sem)
6107 (binary-arith-imm-dst-defn 16 (.sym Imm-24- smode) 16-8 dmode wstr op suffix
6108 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- dmode) (.sym Imm-24- smode))
6109 sem)
6110 (binary-arith-imm-dst-defn 16 (.sym Imm-16- smode) basic dmode wstr op suffix
6111 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- dmode) (.sym Imm-16- smode))
6112 sem)
6113 )
6114)
6115
6116; m32c Unprefixed variants
6117(define-pmacro (binary-arith32-imm-dst-Unprefixed smode dmode wstr wbit op suffix opc1 opc2 opc3 sem)
6118 (begin
6119 (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 16-24-Unprefixed dmode wstr op suffix
6120 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-16-24-Unprefixed- dmode) (.sym Imm-40- smode))
6121 sem)
6122 (binary-arith-imm-dst-defn 32 (.sym Imm-32- smode) 16-16-Unprefixed dmode wstr op suffix
6123 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-16-16-Unprefixed- dmode) (.sym Imm-32- smode))
6124 sem)
6125 (binary-arith-imm-dst-defn 32 (.sym Imm-24- smode) 16-8-Unprefixed dmode wstr op suffix
6126 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-16-8-Unprefixed- dmode) (.sym Imm-24- smode))
6127 sem)
6128 (binary-arith-imm-dst-defn 32 (.sym Imm-16- smode) basic-Unprefixed dmode wstr op suffix
6129 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-basic-Unprefixed- dmode) (.sym Imm-16- smode))
6130 sem)
6131 )
6132)
6133
6134; m32c Prefixed variants
6135(define-pmacro (binary-arith32-imm-dst-Prefixed smode dmode wstr wbit op suffix opc1 opc2 opc3 sem)
6136 (begin
6137 (binary-arith-imm-dst-defn 32 (.sym Imm-48- smode) 24-24-Prefixed dmode wstr op suffix
6138 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-24-Prefixed- dmode) (.sym Imm-48- smode))
6139 sem)
6140 (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 24-16-Prefixed dmode wstr op suffix
6141 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-16-Prefixed- dmode) (.sym Imm-40- smode))
6142 sem)
6143 (binary-arith-imm-dst-defn 32 (.sym Imm-32- smode) 24-8-Prefixed dmode wstr op suffix
6144 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-8-Prefixed- dmode) (.sym Imm-32- smode))
6145 sem)
6146 (binary-arith-imm-dst-defn 32 (.sym Imm-24- smode) basic-Prefixed dmode wstr op suffix
6147 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-basic-Prefixed- dmode) (.sym Imm-24- smode))
6148 sem)
6149 )
6150)
6151
6152; All m32c variants
6153(define-pmacro (binary-arith32-imm-dst-defn smode dmode wstr wbit op suffix opc1 opc2 opc3 sem)
6154 (begin
6155 ; Multi insns are tried for assembly in the reverse order in which they appear here, so
6156 ; define the absolute-indirect insns first in order to prevent them from being selected
6157 ; when the mode is register-indirect
6158; (binary-arith-imm-dst-defn 32 (.sym Imm-48- smode) 24-24-absolute-indirect dmode wstr op suffix
6159; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-24-absolute-indirect- dmode) (.sym Imm-48- smode))
6160; sem)
6161; (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 24-16-absolute-indirect dmode wstr op suffix
6162; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-16-absolute-indirect- dmode) (.sym Imm-40- smode))
6163; sem)
6164 ; Unprefixed modes next
6165 (binary-arith32-imm-dst-Unprefixed smode dmode wstr wbit op suffix opc1 opc2 opc3 sem)
6166
6167 ; Remaining indirect modes
6168; (binary-arith-imm-dst-defn 32 (.sym Imm-24- smode) basic-indirect dmode wstr op suffix
6169; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-basic-indirect- dmode) (.sym Imm-24- smode))
6170; sem)
6171; (binary-arith-imm-dst-defn 32 (.sym Imm-48- smode) 24-24-indirect dmode wstr op suffix
6172; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-24-indirect- dmode) (.sym Imm-48- smode))
6173; sem)
6174; (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 24-16-indirect dmode wstr op suffix
6175; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-16-indirect- dmode) (.sym Imm-40- smode))
6176; sem)
6177; (binary-arith-imm-dst-defn 32 (.sym Imm-32- smode) 24-8-indirect dmode wstr op suffix
6178; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-8-indirect- dmode) (.sym Imm-32- smode))
6179; sem)
6180 )
6181)
6182
6183(define-pmacro (binary-arith-imm-dst-mach mach op suffix opc1 opc2 opc3 sem)
6184 (begin
6185 (.apply (.sym binary-arith mach -imm-dst-defn) (QI QI .b 0 op suffix opc1 opc2 opc3 sem))
6186 (.apply (.sym binary-arith mach -imm-dst-defn) (HI HI .w 1 op suffix opc1 opc2 opc3 sem))
6187 )
6188)
6189
6190(define-pmacro (binary-arith-imm-dst op suffix opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
6191 (begin
6192 (binary-arith-imm-dst-mach 16 op suffix opc16-1 opc16-2 opc16-3 sem)
6193 (binary-arith-imm-dst-mach 32 op suffix opc32-1 opc32-2 opc32-3 sem)
6194 )
6195)
6196
6197;-------------------------------------------------------------
6198;<arith>.size:Q #imm4,dst -- for m16c and m32c
6199;-------------------------------------------------------------
6200
6201(define-pmacro (binary-arith-imm4-dst-defn mach src dstgroup mode wstr op encoding sem)
6202 (dni (.sym op mach wstr - imm4-Q - dstgroup)
6203 (.str op wstr " " mach "-imm4-Q-" dstgroup "-" mode)
6772dd07 6204 ((machine mach) RL_1ADDR)
49f58d10
JB		 6205 (.str op wstr "$Q #${" src "},${dst" mach "-" dstgroup "-" mode "}")
6206 encoding
6207 (sem mode src (.sym dst mach - dstgroup - mode))
6208 ())
6209)
6210
6211; m16c variants
6212(define-pmacro (binary-arith16-imm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem)
6213 (binary-arith-imm4-dst-defn 16 Imm-8-s4 16 mode wstr op
6214 (+ opc1 opc2 (f-7-1 wbit2) Imm-8-s4 (.sym dst16-16- mode))
6215 sem)
6216)
6217
6218(define-pmacro (binary-arith16-shimm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem)
6219 (binary-arith-imm4-dst-defn 16 Imm-sh-8-s4 16 mode wstr op
6220 (+ opc1 opc2 (f-7-1 wbit2) Imm-sh-8-s4 (.sym dst16-16- mode))
6221 sem)
6222)
6223
6224; m32c variants
6225(define-pmacro (binary-arith32-imm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem)
6226 (begin
6227 ; Multi insns are tried for assembly in the reverse order in which they appear here, so
6228 ; define the absolute-indirect insns first in order to prevent them from being selected
6229 ; when the mode is register-indirect
6230; (binary-arith-imm4-dst-defn 32 Imm-20-s4 24-absolute-indirect mode wstr op
6231; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) Imm-20-s4)
6232; sem)
6233 (binary-arith-imm4-dst-defn 32 Imm-12-s4 16-Unprefixed mode wstr op
6234 (+ (f-0-3 opc1) (f-3-1 wbit1) (f-7-1 wbit2) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4)
6235 sem)
6236; (binary-arith-imm4-dst-defn 32 Imm-20-s4 24-indirect mode wstr op
6237; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-indirect- mode) (f-18-2 opc2) Imm-20-s4)
6238; sem)
6239 )
6240)
6241
6242(define-pmacro (binary-arith32-shimm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem)
6243 (begin
6244 ; Multi insns are tried for assembly in the reverse order in which they appear here, so
6245 ; define the absolute-indirect insns first in order to prevent them from being selected
6246 ; when the mode is register-indirect
6247; (binary-arith-imm4-dst-defn 32 Imm-sh-20-s4 24-absolute-indirect mode wstr op
6248; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) Imm-sh-20-s4)
6249; sem)
6250 (binary-arith-imm4-dst-defn 32 Imm-sh-12-s4 16-Unprefixed mode wstr op
6251 (+ (f-0-3 opc1) (f-3-1 wbit1) (f-7-1 wbit2) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) Imm-sh-12-s4)
6252 sem)
6253; (binary-arith-imm4-dst-defn 32 Imm-sh-20-s4 24-indirect mode wstr op
6254; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-indirect- mode) (f-18-2 opc2) Imm-sh-20-s4)
6255; sem)
6256 )
6257)
6258
6259(define-pmacro (binary-arith-imm4-dst-mach mach op opc1 opc2 sem)
6260 (begin
6261 (.apply (.sym binary-arith mach -imm4-dst-defn) (QI .b 0 0 op opc1 opc2 sem))
6262 (.apply (.sym binary-arith mach -imm4-dst-defn) (HI .w 0 1 op opc1 opc2 sem))
6263 )
6264)
6265
6266(define-pmacro (binary-arith-imm4-dst op opc16-1 opc16-2 opc32-1 opc32-2 sem)
6267 (begin
6268 (binary-arith-imm4-dst-mach 16 op opc16-1 opc16-2 sem)
6269 (binary-arith-imm4-dst-mach 32 op opc32-1 opc32-2 sem)
6270 )
6271)
6272
6273;-------------------------------------------------------------
6274;<arith>.size:G src,dst -- for m16c and m32c
6275;-------------------------------------------------------------
6276
6277(define-pmacro (binary-arith-src-dst-defn mach srcgroup dstgroup smode dmode wstr op suffix encoding sem)
6278 (dni (.sym op mach wstr - srcgroup - dstgroup)
6279 (.str op wstr " dst" mach "-" srcgroup "-" dstgroup "-" dmode)
6772dd07 6280 ((machine mach) RL_2ADDR)
49f58d10
JB		 6281 (.str op wstr "$" suffix " ${src" mach "-" srcgroup "-" smode "},${dst" mach "-" dstgroup "-" dmode "}")
6282 encoding
6283 (sem dmode (.sym src mach - srcgroup - smode) (.sym dst mach - dstgroup - dmode))
6284 ())
6285)
6286
6287; m16c variants
6288(define-pmacro (binary-arith16-src-dst-defn smode dmode wstr wbit op suffix opc1 opc2 sem)
6289 (begin
6290 (binary-arith-src-dst-defn 16 basic 16 smode dmode wstr op suffix
6291 (+ opc1 opc2 (f-7-1 wbit) (.sym src16-basic- smode) (.sym dst16-16- dmode))
6292 sem)
6293 (binary-arith-src-dst-defn 16 16-16 32 smode dmode wstr op suffix
6294 (+ opc1 opc2 (f-7-1 wbit) (.sym src16-16-16- smode) (.sym dst16-32- dmode))
6295 sem)
6296 (binary-arith-src-dst-defn 16 16-8 24 smode dmode wstr op suffix
6297 (+ opc1 opc2 (f-7-1 wbit) (.sym src16-16-8- smode) (.sym dst16-24- dmode))
6298 sem)
6299 )
6300)
6301
6302; m32c Prefixed variants
6303(define-pmacro (binary-arith32-src-dst-Prefixed smode dmode wstr wbit op suffix opc1 opc2 sem)
6304 (begin
6305 (binary-arith-src-dst-defn 32 basic-Prefixed 24-Prefixed smode dmode wstr op suffix
6306 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-basic-Prefixed- smode) (.sym dst32-24-Prefixed- dmode) (f-20-4 opc2))
6307 sem)
6308 (binary-arith-src-dst-defn 32 24-24-Prefixed 48-Prefixed smode dmode wstr op suffix
6309 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-24-24-Prefixed- smode) (.sym dst32-48-Prefixed- dmode) (f-20-4 opc2))
6310 sem)
6311 (binary-arith-src-dst-defn 32 24-16-Prefixed 40-Prefixed smode dmode wstr op suffix
6312 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-24-16-Prefixed- smode) (.sym dst32-40-Prefixed- dmode) (f-20-4 opc2))
6313 sem)
6314 (binary-arith-src-dst-defn 32 24-8-Prefixed 32-Prefixed smode dmode wstr op suffix
6315 (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-24-8-Prefixed- smode) (.sym dst32-32-Prefixed- dmode) (f-20-4 opc2))
6316 sem)
6317 )
6318)
6319
6320; all m32c variants
6321(define-pmacro (binary-arith32-src-dst-defn smode dmode wstr wbit op suffix opc1 opc2 sem)
6322 (begin
6323 ; Multi insns are tried for assembly in the reverse order in which they appear here, so
6324 ; define the absolute-indirect insns first in order to prevent them from being selected
6325 ; when the mode is register-indirect
6326; (binary-arith-src-dst-defn 32 24-24-absolute-indirect 48-absolute-indirect smode dmode wstr op suffix
6327; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6328; (.sym src32-24-24-absolute-indirect- smode) (.sym dst32-48-absolute-indirect- dmode) (f-20-4 opc2))
6329; sem)
6330; (binary-arith-src-dst-defn 32 24-16-absolute-indirect 40-absolute-indirect smode dmode wstr op suffix
6331; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6332; (.sym src32-24-16-absolute-indirect- smode) (.sym dst32-40-absolute-indirect- dmode) (f-20-4 opc2))
6333; sem)
6334; (binary-arith-src-dst-defn 32 24-24-absolute-indirect 48-Prefixed smode dmode wstr op suffix
6335; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit)
6336; (.sym src32-24-24-absolute-indirect- smode) (.sym dst32-48-Prefixed- dmode) (f-20-4 opc2))
6337; sem)
6338; (binary-arith-src-dst-defn 32 24-16-absolute-indirect 40-Prefixed smode dmode wstr op suffix
6339; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit)
6340; (.sym src32-24-16-absolute-indirect- smode) (.sym dst32-40-Prefixed- dmode) (f-20-4 opc2))
6341; sem)
6342; (binary-arith-src-dst-defn 32 24-24-absolute-indirect 48-indirect smode dmode wstr op suffix
6343; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6344; (.sym src32-24-24-absolute-indirect- smode) (.sym dst32-48-indirect- dmode) (f-20-4 opc2))
6345; sem)
6346; (binary-arith-src-dst-defn 32 24-16-absolute-indirect 40-indirect smode dmode wstr op suffix
6347; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6348; (.sym src32-24-16-absolute-indirect- smode) (.sym dst32-40-indirect- dmode) (f-20-4 opc2))
6349; sem)
6350; (binary-arith-src-dst-defn 32 basic-Prefixed 24-absolute-indirect smode dmode wstr op suffix
6351; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6352; (.sym src32-basic-Prefixed- smode) (.sym dst32-24-absolute-indirect- dmode) (f-20-4 opc2))
6353; sem)
6354; (binary-arith-src-dst-defn 32 24-24-Prefixed 48-absolute-indirect smode dmode wstr op suffix
6355; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6356; (.sym src32-24-24-Prefixed- smode) (.sym dst32-48-absolute-indirect- dmode) (f-20-4 opc2))
6357; sem)
6358; (binary-arith-src-dst-defn 32 24-16-Prefixed 40-absolute-indirect smode dmode wstr op suffix
6359; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6360; (.sym src32-24-16-Prefixed- smode) (.sym dst32-40-absolute-indirect- dmode) (f-20-4 opc2))
6361; sem)
6362; (binary-arith-src-dst-defn 32 24-8-Prefixed 32-absolute-indirect smode dmode wstr op suffix
6363; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6364; (.sym src32-24-8-Prefixed- smode) (.sym dst32-32-absolute-indirect- dmode) (f-20-4 opc2))
6365; sem)
6366; (binary-arith-src-dst-defn 32 basic-indirect 24-absolute-indirect smode dmode wstr op suffix
6367; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6368; (.sym src32-basic-indirect- smode) (.sym dst32-24-absolute-indirect- dmode) (f-20-4 opc2))
6369; sem)
6370; (binary-arith-src-dst-defn 32 24-24-indirect 48-absolute-indirect smode dmode wstr op suffix
6371; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6372; (.sym src32-24-24-indirect- smode) (.sym dst32-48-absolute-indirect- dmode) (f-20-4 opc2))
6373; sem)
6374; (binary-arith-src-dst-defn 32 24-16-indirect 40-absolute-indirect smode dmode wstr op suffix
6375; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6376; (.sym src32-24-16-indirect- smode) (.sym dst32-40-absolute-indirect- dmode) (f-20-4 opc2))
6377; sem)
6378; (binary-arith-src-dst-defn 32 24-8-indirect 32-absolute-indirect smode dmode wstr op suffix
6379; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6380; (.sym src32-24-8-indirect- smode) (.sym dst32-32-absolute-indirect- dmode) (f-20-4 opc2))
6381; sem)
6382 (binary-arith-src-dst-defn 32 basic-Unprefixed 16-Unprefixed smode dmode wstr op suffix
6383 (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-basic-Unprefixed- smode) (.sym dst32-16-Unprefixed- dmode) (f-12-4 opc2))
6384 sem)
6385 (binary-arith-src-dst-defn 32 16-24-Unprefixed 40-Unprefixed smode dmode wstr op suffix
6386 (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-16-24-Unprefixed- smode) (.sym dst32-40-Unprefixed- dmode) (f-12-4 opc2))
6387 sem)
6388 (binary-arith-src-dst-defn 32 16-16-Unprefixed 32-Unprefixed smode dmode wstr op suffix
6389 (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-16-16-Unprefixed- smode) (.sym dst32-32-Unprefixed- dmode) (f-12-4 opc2))
6390 sem)
6391 (binary-arith-src-dst-defn 32 16-8-Unprefixed 24-Unprefixed smode dmode wstr op suffix
6392 (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-16-8-Unprefixed- smode) (.sym dst32-24-Unprefixed- dmode) (f-12-4 opc2))
6393 sem)
6394; (binary-arith-src-dst-defn 32 basic-indirect 24-Prefixed smode dmode wstr op suffix
6395; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit)
6396; (.sym src32-basic-indirect- smode) (.sym dst32-24-Prefixed- dmode) (f-20-4 opc2))
6397; sem)
6398; (binary-arith-src-dst-defn 32 24-24-indirect 48-Prefixed smode dmode wstr op suffix
6399; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit)
6400; (.sym src32-24-24-indirect- smode) (.sym dst32-48-Prefixed- dmode) (f-20-4 opc2))
6401; sem)
6402; (binary-arith-src-dst-defn 32 24-16-indirect 40-Prefixed smode dmode wstr op suffix
6403; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit)
6404; (.sym src32-24-16-indirect- smode) (.sym dst32-40-Prefixed- dmode) (f-20-4 opc2))
6405; sem)
6406; (binary-arith-src-dst-defn 32 24-8-indirect 32-Prefixed smode dmode wstr op suffix
6407; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit)
6408; (.sym src32-24-8-indirect- smode) (.sym dst32-32-Prefixed- dmode) (f-20-4 opc2))
6409; sem)
6410; (binary-arith-src-dst-defn 32 basic-Prefixed 24-indirect smode dmode wstr op suffix
6411; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6412; (.sym src32-basic-Prefixed- smode) (.sym dst32-24-indirect- dmode) (f-20-4 opc2))
6413; sem)
6414; (binary-arith-src-dst-defn 32 24-24-Prefixed 48-indirect smode dmode wstr op suffix
6415; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6416; (.sym src32-24-24-Prefixed- smode) (.sym dst32-48-indirect- dmode) (f-20-4 opc2))
6417; sem)
6418; (binary-arith-src-dst-defn 32 24-16-Prefixed 40-indirect smode dmode wstr op suffix
6419; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6420; (.sym src32-24-16-Prefixed- smode) (.sym dst32-40-indirect- dmode) (f-20-4 opc2))
6421; sem)
6422; (binary-arith-src-dst-defn 32 24-8-Prefixed 32-indirect smode dmode wstr op suffix
6423; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6424; (.sym src32-24-8-Prefixed- smode) (.sym dst32-32-indirect- dmode) (f-20-4 opc2))
6425; sem)
6426; (binary-arith-src-dst-defn 32 basic-indirect 24-indirect smode dmode wstr op suffix
6427; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6428; (.sym src32-basic-indirect- smode) (.sym dst32-24-indirect- dmode) (f-20-4 opc2))
6429; sem)
6430; (binary-arith-src-dst-defn 32 24-24-indirect 48-indirect smode dmode wstr op suffix
6431; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6432; (.sym src32-24-24-indirect- smode) (.sym dst32-48-indirect- dmode) (f-20-4 opc2))
6433; sem)
6434; (binary-arith-src-dst-defn 32 24-16-indirect 40-indirect smode dmode wstr op suffix
6435; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6436; (.sym src32-24-16-indirect- smode) (.sym dst32-40-indirect- dmode) (f-20-4 opc2))
6437; sem)
6438; (binary-arith-src-dst-defn 32 24-8-indirect 32-indirect smode dmode wstr op suffix
6439; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
6440; (.sym src32-24-8-indirect- smode) (.sym dst32-32-indirect- dmode) (f-20-4 opc2))
6441; sem)
6442 )
6443)
6444
6445(define-pmacro (binary-arith-src-dst-mach mach op suffix opc1 opc2 sem)
6446 (begin
6447 (.apply (.sym binary-arith mach -src-dst-defn) (QI QI .b 0 op suffix opc1 opc2 sem))
6448 (.apply (.sym binary-arith mach -src-dst-defn) (HI HI .w 1 op suffix opc1 opc2 sem))
6449 )
6450)
6451
6452(define-pmacro (binary-arith-src-dst op suffix opc16-1 opc16-2 opc32-1 opc32-2 sem)
6453 (begin
6454 (binary-arith-src-dst-mach 16 op suffix opc16-1 opc16-2 sem)
6455 (binary-arith-src-dst-mach 32 op suffix opc32-1 opc32-2 sem)
6456 )
6457)
6458
6459;-------------------------------------------------------------
6460;<arith>.size:S #imm,dst -- for m32c
6461;-------------------------------------------------------------
6462
6463(define-pmacro (binary-arith32-s-imm-dst-defn src dstgroup mode wstr op encoding sem)
6464 (dni (.sym op 32 wstr - imm-S - dstgroup)
6465 (.str op wstr " 32-imm-S-" dstgroup "-" mode)
6466 ((machine 32))
6467 (.str op wstr "$S #${" src "},${dst32-" dstgroup "-" mode "}")
6468 encoding
6469 (sem mode src (.sym dst32- dstgroup - mode))
6470 ())
6471)
6472
6473(define-pmacro (binary-arith32-z-imm-dst-defn src dstgroup mode wstr op encoding sem)
6474 (dni (.sym op 32 wstr - imm-Z - dstgroup)
6475 (.str op wstr " 32-imm-Z-" dstgroup "-" mode)
6476 ((machine 32))
6477 (.str op wstr "$Z #0,${dst32-" dstgroup "-" mode "}")
6478 encoding
6479 (sem mode (const 0) (.sym dst32- dstgroup - mode))
6480 ())
6481)
6482
6483(define-pmacro (binary-arith32-s-imm-dst mode wstr wbit op opc1 opc2 sem)
6484 (begin
6485; (binary-arith32-s-imm-dst-defn (.sym Imm-32- mode) 2-S-absolute-indirect mode wstr op
6486; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-absolute-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-32- mode))
6487; sem)
6488 (binary-arith32-s-imm-dst-defn (.sym Imm-8- mode) 2-S-basic mode wstr op
6489 (+ (f-0-2 opc1) (.sym dst32-2-S-basic- mode) (f-4-3 opc2) (f-7-1 wbit) (.sym Imm-8- mode))
6490 sem)
6491 (binary-arith32-s-imm-dst-defn (.sym Imm-24- mode) 2-S-16 mode wstr op
6492 (+ (f-0-2 opc1) (.sym dst32-2-S-16- mode) (f-4-3 opc2) (f-7-1 wbit) (.sym Imm-24- mode))
6493 sem)
6494 (binary-arith32-s-imm-dst-defn (.sym Imm-16- mode) 2-S-8 mode wstr op
6495 (+ (f-0-2 opc1) (.sym dst32-2-S-8- mode) (f-4-3 opc2) (f-7-1 wbit) (.sym Imm-16- mode))
6496 sem)
6497; (binary-arith32-s-imm-dst-defn (.sym Imm-24- mode) 2-S-8-indirect mode wstr op
6498; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-8-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-24- mode))
6499; sem)
6500 )
6501)
6502
6503(define-pmacro (binary-arith32-z-imm-dst mode wstr wbit op opc1 opc2 sem)
6504 (begin
6505; (binary-arith32-z-imm-dst-defn (.sym Imm-32- mode) 2-S-absolute-indirect mode wstr op
6506; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-absolute-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-32- mode))
6507; sem)
6508 (binary-arith32-z-imm-dst-defn (.sym Imm-8- mode) 2-S-basic mode wstr op
6509 (+ (f-0-2 opc1) (.sym dst32-2-S-basic- mode) (f-4-3 opc2) (f-7-1 wbit))
6510 sem)
6511 (binary-arith32-z-imm-dst-defn (.sym Imm-24- mode) 2-S-16 mode wstr op
6512 (+ (f-0-2 opc1) (.sym dst32-2-S-16- mode) (f-4-3 opc2) (f-7-1 wbit))
6513 sem)
6514 (binary-arith32-z-imm-dst-defn (.sym Imm-16- mode) 2-S-8 mode wstr op
6515 (+ (f-0-2 opc1) (.sym dst32-2-S-8- mode) (f-4-3 opc2) (f-7-1 wbit))
6516 sem)
6517; (binary-arith32-z-imm-dst-defn (.sym Imm-24- mode) 2-S-8-indirect mode wstr op
6518; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-8-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-24- mode))
6519; sem)
6520 )
6521)
6522
6523;-------------------------------------------------------------
6524;<arith>.L:S #imm1,An -- for m32c
6525;-------------------------------------------------------------
6526
6527(define-pmacro (binary-arith32-l-s-imm1-an op opc1 opc2 sem)
6528 (begin
6529 (dni (.sym op 32.l-s-imm1-S-an)
6530 (.str op ".l 32-imm1-S-an")
6531 ((machine 32))
6532 (.str op ".l$S #${Imm1-S},${dst32-an-S}")
6533 (+ opc1 Imm1-S opc2 dst32-an-S)
6534 (sem SI Imm1-S dst32-an-S)
6535 ())
6536 )
6537)
6538
6539;-------------------------------------------------------------
6540;<arith>.L:Q #imm3,sp -- for m32c
6541;-------------------------------------------------------------
6542
6543(define-pmacro (binary-arith32-l-q-imm3-sp op opc1 opc2 sem)
6544 (begin
6545 (dni (.sym op 32.l-imm3-Q)
6546 (.str op ".l 32-imm3-Q")
6547 ((machine 32))
6548 (.str op ".l$Q #${Imm3-S},sp")
6549 (+ opc1 Imm3-S opc2)
6550 (sem SI Imm3-S sp)
6551 ())
6552 )
6553)
6554
6555;-------------------------------------------------------------
6556;<arith>.L:S #imm8,sp -- for m32c
6557;-------------------------------------------------------------
6558
6559(define-pmacro (binary-arith32-l-s-imm8-sp op opc1 opc2 opc3 opc4 sem)
6560 (begin
6561 (dni (.sym op 32.l-imm8-S)
6562 (.str op ".l 32-imm8-S")
6563 ((machine 32))
6564 (.str op ".l$S #${Imm-16-QI},sp")
6565 (+ opc1 opc2 opc3 opc4 Imm-16-QI)
6566 (sem SI Imm-16-QI sp)
6567 ())
6568 )
6569)
6570
6571;-------------------------------------------------------------
6572;<arith>.L:G #imm16,sp -- for m32c
6573;-------------------------------------------------------------
6574
6575(define-pmacro (binary-arith32-l-g-imm16-sp op opc1 opc2 opc3 opc4 sem)
6576 (begin
6577 (dni (.sym op 32.l-imm16-G)
6578 (.str op ".l 32-imm16-G")
6579 ((machine 32))
6580 (.str op ".l$G #${Imm-16-HI},sp")
6581 (+ opc1 opc2 opc3 opc4 Imm-16-HI)
6582 (sem SI Imm-16-HI sp)
6583 ())
6584 )
6585)
6586
6587;-------------------------------------------------------------
6588;<arith>jnz.size #imm4,dst,label -- for m16c and m32c
6589;-------------------------------------------------------------
6590
6591(define-pmacro (arith-jnz-imm4-dst-defn mach src dstgroup label mode wstr op encoding sem)
6592 (dni (.sym op mach wstr - imm4 - dstgroup)
6593 (.str op wstr " " mach "-imm4-" dstgroup "-" label "-" mode)
6594 ((machine mach))
6595 (.str op wstr " #${" src "},${dst" mach "-" dstgroup "-" mode "},${" label "}")
6596 encoding
6597 (sem mode src (.sym dst mach - dstgroup - mode) label)
6598 ())
6599)
6600
6601; m16c variants
c6552317 6602(define-pmacro (arith-jnz16-imm4-dst-defn mode wstr wbit op i4n opc1 opc2 sem)
49f58d10 6603 (begin
c6552317
DD		 6604 (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) basic Lab-16-8 mode wstr op
6605 (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-basic- mode) Lab-16-8)
49f58d10 6606 sem)
c6552317
DD		 6607 (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-16 Lab-32-8 mode wstr op
6608 (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-16- mode) Lab-16-8)
49f58d10 6609 sem)
c6552317
DD		 6610 (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-8 Lab-24-8 mode wstr op
6611 (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-8- mode) Lab-16-8)
49f58d10
JB		 6612 sem)
6613 )
6614)
6615
6616; m32c variants
c6552317 6617(define-pmacro (arith-jnz32-imm4-dst-defn mode wstr wbit op i4n opc1 opc2 sem)
49f58d10 6618 (begin
c6552317
DD		 6619 (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) basic-Unprefixed Lab-16-8 mode wstr op
6620 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-16-8)
49f58d10 6621 sem)
c6552317
DD		 6622 (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-24-Unprefixed Lab-40-8 mode wstr op
6623 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-40-8)
49f58d10 6624 sem)
c6552317
DD		 6625 (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-16-Unprefixed Lab-32-8 mode wstr op
6626 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-32-8)
49f58d10 6627 sem)
c6552317
DD		 6628 (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-8-Unprefixed Lab-24-8 mode wstr op
6629 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-24-8)
49f58d10
JB		 6630 sem)
6631 )
6632)
6633
c6552317 6634(define-pmacro (arith-jnz-imm4-dst-mach mach op i4n opc1 opc2 sem)
49f58d10 6635 (begin
c6552317
DD		 6636 (.apply (.sym arith-jnz mach -imm4-dst-defn) (QI .b 0 op i4n opc1 opc2 sem))
6637 (.apply (.sym arith-jnz mach -imm4-dst-defn) (HI .w 1 op i4n opc1 opc2 sem))
49f58d10
JB		 6638 )
6639)
6640
c6552317 6641(define-pmacro (arith-jnz-imm4-dst op i4n opc16-1 opc16-2 opc32-1 opc32-2 sem)
49f58d10 6642 (begin
c6552317
DD		 6643 (arith-jnz-imm4-dst-mach 16 op i4n opc16-1 opc16-2 sem)
6644 (arith-jnz-imm4-dst-mach 32 op i4n opc32-1 opc32-2 sem)
49f58d10
JB		 6645 )
6646)
6647
6648;-------------------------------------------------------------
6649;mov.size dsp8[sp],dst -- for m16c and m32c
6650;-------------------------------------------------------------
6651(define-pmacro (mov-dspsp-dst-defn mach dstgroup dsp mode wstr op encoding sem)
6652 (dni (.sym op mach wstr -dspsp-dst- dstgroup)
6653 (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode)
6654 ((machine mach))
f75eb1c0 6655 (.str op wstr "$G ${" dsp "}[sp],${dst" mach "-" dstgroup "-" mode "}")
49f58d10
JB		 6656 encoding
6657 (sem mach mode dsp (.sym dst mach - dstgroup - mode))
6658 ())
6659)
6660(define-pmacro (mov-src-dspsp-defn mach dstgroup dsp mode wstr op encoding sem)
6661 (dni (.sym op mach wstr -dst-dspsp- dstgroup)
6662 (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode)
6663 ((machine mach))
f75eb1c0 6664 (.str op wstr "$G ${dst" mach "-" dstgroup "-" mode "},${" dsp "}[sp]")
49f58d10
JB		 6665 encoding
6666 (sem mach mode (.sym dst mach - dstgroup - mode) dsp)
6667 ())
6668)
6669
6670; m16c variants
6671(define-pmacro (mov16-dspsp-dst-defn mode wstr wbit op opc1 opc2 opc3 sem)
6672 (begin
f75eb1c0
DD		 6673 (mov-dspsp-dst-defn 16 basic Dsp-16-s8 mode wstr op
6674 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-s8)
49f58d10 6675 sem)
f75eb1c0
DD		 6676 (mov-dspsp-dst-defn 16 16-16 Dsp-32-s8 mode wstr op
6677 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-s8)
49f58d10 6678 sem)
f75eb1c0
DD		 6679 (mov-dspsp-dst-defn 16 16-8 Dsp-24-s8 mode wstr op
6680 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-s8)
49f58d10
JB		 6681 sem)
6682 )
6683)
6684
6685(define-pmacro (mov16-src-dspsp-defn mode wstr wbit op opc1 opc2 opc3 sem)
6686 (begin
f75eb1c0
DD		 6687 (mov-src-dspsp-defn 16 basic Dsp-16-s8 mode wstr op
6688 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-s8)
49f58d10 6689 sem)
f75eb1c0
DD		 6690 (mov-src-dspsp-defn 16 16-16 Dsp-32-s8 mode wstr op
6691 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-s8)
49f58d10 6692 sem)
f75eb1c0
DD		 6693 (mov-src-dspsp-defn 16 16-8 Dsp-24-s8 mode wstr op
6694 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-s8)
49f58d10
JB		 6695 sem)
6696 )
6697)
6698
6699; m32c variants
6700(define-pmacro (mov32-dspsp-dst-defn mode wstr wbit op opc1 opc2 opc3 sem)
6701 (begin
f75eb1c0
DD		 6702 (mov-dspsp-dst-defn 32 basic-Unprefixed Dsp-16-s8 mode wstr op
6703 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-s8)
49f58d10 6704 sem)
f75eb1c0
DD		 6705 (mov-dspsp-dst-defn 32 16-24-Unprefixed Dsp-40-s8 mode wstr op
6706 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-s8)
49f58d10 6707 sem)
f75eb1c0
DD		 6708 (mov-dspsp-dst-defn 32 16-16-Unprefixed Dsp-32-s8 mode wstr op
6709 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-s8)
49f58d10 6710 sem)
f75eb1c0
DD		 6711 (mov-dspsp-dst-defn 32 16-8-Unprefixed Dsp-24-s8 mode wstr op
6712 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-s8)
49f58d10
JB		 6713 sem)
6714 )
6715)
6716(define-pmacro (mov32-src-dspsp-defn mode wstr wbit op opc1 opc2 opc3 sem)
6717 (begin
f75eb1c0
DD		 6718 (mov-src-dspsp-defn 32 basic-Unprefixed Dsp-16-s8 mode wstr op
6719 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-s8)
49f58d10 6720 sem)
f75eb1c0
DD		 6721 (mov-src-dspsp-defn 32 16-24-Unprefixed Dsp-40-s8 mode wstr op
6722 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-s8)
49f58d10 6723 sem)
f75eb1c0
DD		 6724 (mov-src-dspsp-defn 32 16-16-Unprefixed Dsp-32-s8 mode wstr op
6725 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-s8)
49f58d10 6726 sem)
f75eb1c0
DD		 6727 (mov-src-dspsp-defn 32 16-8-Unprefixed Dsp-24-s8 mode wstr op
6728 (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-s8)
49f58d10
JB		 6729 sem)
6730 )
6731)
6732
6733(define-pmacro (mov-src-dspsp-mach mach op opc1 opc2 opc3 sem)
6734 (begin
6735 (.apply (.sym mov mach -src-dspsp-defn) (QI .b 0 op opc1 opc2 opc3 sem))
6736 (.apply (.sym mov mach -src-dspsp-defn) (HI .w 1 op opc1 opc2 opc3 sem))
6737 )
6738)
6739
6740(define-pmacro (mov-dspsp-dst-mach mach op opc1 opc2 opc3 sem)
6741 (begin
6742 (.apply (.sym mov mach -dspsp-dst-defn) (QI .b 0 op opc1 opc2 opc3 sem))
6743 (.apply (.sym mov mach -dspsp-dst-defn) (HI .w 1 op opc1 opc2 opc3 sem))
6744 )
6745)
6746
6747(define-pmacro (mov-dspsp-dst op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
6748 (begin
6749 (mov-dspsp-dst-mach 16 op opc16-1 opc16-2 opc16-3 sem)
6750 (mov-dspsp-dst-mach 32 op opc32-1 opc32-2 opc32-3 sem)
6751 )
6752)
6753(define-pmacro (mov-src-dspsp op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
6754 (begin
6755 (mov-src-dspsp-mach 16 op opc16-1 opc16-2 opc16-3 sem)
6756 (mov-src-dspsp-mach 32 op opc32-1 opc32-2 opc32-3 sem)
6757 )
6758)
6759
6760;-------------------------------------------------------------
6761; lde dsp24,dst -- for m16c
49f58d10
JB		 6762;-------------------------------------------------------------
6763
a1a280bb
DD		 6764(define-pmacro (lde-dst-dsp mode wstr wbit dstgroup srcdisp)
6765 (begin
6766
6767 (dni (.sym lde wstr - dstgroup -u20)
6768 (.str "lde" wstr "-" dstgroup "-u20")
6769 ((machine 16))
6770 (.str "lde" wstr " ${" srcdisp "},${dst16-" dstgroup "-" mode "}")
6771 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x8)
6772 (.sym dst16- dstgroup - mode) srcdisp)
6773 (nop)
6774 ())
49f58d10 6775
a1a280bb
DD		 6776 (dni (.sym lde wstr - dstgroup -u20a0)
6777 (.str "lde" wstr "-" dstgroup "-u20a0")
6778 ((machine 16))
6779 (.str "lde" wstr " ${" srcdisp "}[a0],${dst16-" dstgroup "-" mode "}")
6780 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x9)
6781 (.sym dst16- dstgroup - mode) srcdisp)
6782 (nop)
6783 ())
6784
6785 (dni (.sym lde wstr - dstgroup -a1a0)
6786 (.str "lde" wstr "-" dstgroup "-a1a0")
6787 ((machine 16))
6788 (.str "lde" wstr " [a1a0],${dst16-" dstgroup "-" mode "}")
6789 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #xa)
6790 (.sym dst16- dstgroup - mode))
6791 (nop)
6792 ())
6793 )
6794 )
6795
6796(define-pmacro (lde-dst mode wstr wbit)
49f58d10 6797 (begin
a1a280bb
DD		 6798 ; like: QI .b 0
6799 (lde-dst-dsp mode wstr wbit basic Dsp-16-u20)
6800 (lde-dst-dsp mode wstr wbit 16-8 Dsp-24-u20)
6801 (lde-dst-dsp mode wstr wbit 16-16 Dsp-32-u20)
49f58d10
JB		 6802 )
6803)
6804
6805;-------------------------------------------------------------
a1a280bb 6806; ste dst,dsp24 -- for m16c
49f58d10
JB		 6807;-------------------------------------------------------------
6808
a1a280bb
DD		 6809(define-pmacro (ste-dst-dsp mode wstr wbit dstgroup srcdisp)
6810 (begin
6811
6812 (dni (.sym ste wstr - dstgroup -u20)
6813 (.str "ste" wstr "-" dstgroup "-u20")
6814 ((machine 16))
6815 (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},${" srcdisp "}")
6816 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x0)
6817 (.sym dst16- dstgroup - mode) srcdisp)
6818 (nop)
6819 ())
6820
6821 (dni (.sym ste wstr - dstgroup -u20a0)
6822 (.str "ste" wstr "-" dstgroup "-u20a0")
6823 ((machine 16))
6824 (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},${" srcdisp "}[a0]")
6825 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x1)
6826 (.sym dst16- dstgroup - mode) srcdisp)
6827 (nop)
6828 ())
49f58d10 6829
a1a280bb
DD		 6830 (dni (.sym ste wstr - dstgroup -a1a0)
6831 (.str "ste" wstr "-" dstgroup "-a1a0")
6832 ((machine 16))
6833 (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},[a1a0]")
6834 (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x2)
6835 (.sym dst16- dstgroup - mode))
6836 (nop)
6837 ())
6838 )
6839 )
6840
6841(define-pmacro (ste-dst mode wstr wbit)
49f58d10 6842 (begin
a1a280bb
DD		 6843 ; like: QI .b 0
6844 (ste-dst-dsp mode wstr wbit basic Dsp-16-u20)
6845 (ste-dst-dsp mode wstr wbit 16-8 Dsp-24-u20)
6846 (ste-dst-dsp mode wstr wbit 16-16 Dsp-32-u20)
49f58d10
JB		 6847 )
6848)
6849
6850;=============================================================
6851; Division
6852;-------------------------------------------------------------
6853
6854(define-pmacro (div-sem divop modop opmode reg src quot rem max min)
6855 (sequence ()
6856 (if (eq src 0)
6857 (set obit (const BI 1))
6858 (sequence ((opmode quot-result) (opmode rem-result))
6859 (set quot-result (divop opmode (ext opmode reg) src))
6860 (set rem-result (modop opmode (ext opmode reg) src))
6861 (set obit (orif (gt opmode quot-result max)
6862 (lt opmode quot-result min)))
6863 (set quot quot-result)
6864 (set rem rem-result))))
6865)
6866
6867;<divop>.size #imm -- for m16c and m32c
6868(define-pmacro (div-imm-defn mach wstr op src encoding divop modop opmode reg quot rem max min sem)
6869 (dni (.sym op mach wstr - src)
6870 (.str op mach wstr "-" src)
6871 ((machine mach))
6872 (.str op wstr " #${" src "}")
6873 encoding
6874 (sem divop modop opmode reg src quot rem max min)
6875 ())
6876)
6877(define-pmacro (div16-imm-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 opc4 sem)
6878 (div-imm-defn 16 wstr op (.sym Imm-16 - smode)
6879 (+ opc1 opc2 (f-7-1 wbit) opc3 opc4 (.sym Imm-16 - smode))
6880 divop modop opmode reg quot rem max min
6881 sem)
6882)
6883(define-pmacro (div32-imm-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 opc4 sem)
6884 (div-imm-defn 32 wstr op (.sym Imm-16 - smode)
6885 (+ (f-0-4 opc1) (f-4-4 opc2) (f-8-3 opc3) (f-11-1 wbit) (f-12-4 opc4) (.sym Imm-16 - smode))
6886 divop modop opmode reg quot rem max min
6887 sem)
6888)
6889(define-pmacro (div-imm-mach mach op divop modop opmode max-QI min-QI max-HI min-HI opc1 opc2 opc3 opc4 sem)
6890 (begin
6891 (.apply (.sym div mach -imm-defn) (QI .b 0 op divop modop opmode R0 R0l R0h max-QI min-QI opc1 opc2 opc3 opc4 sem))
6892 (.apply (.sym div mach -imm-defn) (HI .w 1 op divop modop opmode R2R0 R0 R2 max-HI min-HI opc1 opc2 opc3 opc4 sem))
6893 )
6894)
6895(define-pmacro (div-imm op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 opc16-4 opc32-1 opc32-2 opc32-3 opc32-4 sem)
6896 (begin
6897 (div-imm-mach 16 op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 opc16-4 sem)
6898 (div-imm-mach 32 op divop modop opmode max-QI min-QI max-HI min-HI opc32-1 opc32-2 opc32-3 opc32-4 sem)
6899 )
6900)
6901
6902;<divop>.size src -- for m16c and m32c
6903(define-pmacro (div-src-defn mach wstr op src encoding divop modop opmode reg quot rem max min sem)
6904 (dni (.sym op mach wstr - src)
6905 (.str op mach wstr "-" src)
6906 ((machine mach))
6907 (.str op wstr " ${" src "}")
6908 encoding
6909 (sem divop modop opmode reg src quot rem max min)
6910 ())
6911)
6912(define-pmacro (div16-src-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 sem)
6913 (div-src-defn 16 wstr op (.sym dst16-16 - smode)
6914 (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16 - smode))
6915 divop modop opmode reg quot rem max min
6916 sem)
6917)
6918(define-pmacro (div32-src-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 sem)
6919 (begin
6920 ; Multi insns are tried for assembly in the reverse order in which they appear here, so
6921 ; define the absolute-indirect insns first in order to prevent them from being selected
6922 ; when the mode is register-indirect
6923; (div-src-defn 32 wstr op (.sym dst32-24-absolute-indirect- smode)
6924; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (f-18-2 opc2) (f-20-4 opc3) (.sym dst32-24-absolute-indirect - smode))
6925; divop modop opmode reg quot rem max min
6926; sem)
6927 (div-src-defn 32 wstr op (.sym dst32-16-Unprefixed- smode)
6928 (+ (f-0-4 opc1) (f-7-1 wbit) (f-10-2 opc2) (f-12-4 opc3) (.sym dst32-16-Unprefixed- smode))
6929 divop modop opmode reg quot rem max min
6930 sem)
6931; (div-src-defn 32 wstr op (.sym dst32-24-indirect- smode)
6932; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (f-18-2 opc2) (f-20-4 opc3) (.sym dst32-24-indirect - smode))
6933; divop modop opmode reg quot rem max min
6934; sem)
6935 )
6936)
6937(define-pmacro (div-src-mach mach op divop modop opmode max-QI min-QI max-HI min-HI opc1 opc2 opc3 sem)
6938 (begin
6939 (.apply (.sym div mach -src-defn) (QI .b 0 op divop modop opmode R0 R0l R0h max-QI min-QI opc1 opc2 opc3 sem))
6940 (.apply (.sym div mach -src-defn) (HI .w 1 op divop modop opmode R2R0 R0 R2 max-HI min-HI opc1 opc2 opc3 sem))
6941 )
6942)
6943(define-pmacro (div-src op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
6944 (begin
6945 (div-src-mach 16 op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 sem)
6946 (div-src-mach 32 op divop modop opmode max-QI min-QI max-HI min-HI opc32-1 opc32-2 opc32-3 sem)
6947 )
6948)
6949
6950;=============================================================
6951; Bit manipulation
6952;
6953(define-pmacro (bit-insn-defn mach op suffix opnd encoding sem)
6954 (dni (.sym op mach - suffix - opnd)
6955 (.str op mach ":" suffix " " opnd)
6956 ((machine mach))
6957 (.str op "$" suffix " ${" opnd "}")
6958 encoding
6959 (sem opnd)
6960 ())
6961)
6962
6963(define-pmacro (bitsrc16-defn op opc1 opc2 opc3 sem)
6964 (bit-insn-defn 16 op X bit16-16
6965 (+ opc1 opc2 opc3 bit16-16)
6966 sem)
6967)
6968
6969(define-pmacro (bitsrc32-defn op opc1 opc2 opc3 sem)
6970 (begin
6971 (bit-insn-defn 32 op X bit32-24-Prefixed
6972 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) bit32-24-Prefixed (f-15-1 opc2) (f-18-3 opc3))
6973 sem)
6974 )
6975)
6976
6977(define-pmacro (bitsrc-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
6978 (begin
6979 (bitsrc16-defn op opc16-1 opc16-2 opc16-3 sem)
6980 (bitsrc32-defn op opc32-1 opc32-2 opc32-3 sem)
6981 )
6982)
6983
6984(define-pmacro (bitdst16-defn op opc1 opc2 opc3 opc4 opc5 opc6 sem)
6985 (begin
6986 (bit-insn-defn 16 op G bit16-16-basic (+ opc1 opc2 opc3 bit16-16-basic) sem)
6987 (bit-insn-defn 16 op G bit16-16-16 (+ opc1 opc2 opc3 bit16-16-16) sem)
6988 (bit-insn-defn 16 op S bit16-11-S (+ opc4 opc5 opc6 bit16-11-S) sem)
6989 (bit-insn-defn 16 op G bit16-16-8 (+ opc1 opc2 opc3 bit16-16-8) sem)
6990 )
6991)
6992
6993(define-pmacro (bitdst32-defn op opc1 opc2 opc3 sem)
6994 (begin
6995 (bit-insn-defn 32 op X bit32-16-Unprefixed
6996 (+ (f-0-4 opc1) bit32-16-Unprefixed (f-7-1 opc2) (f-10-3 opc3))
6997 sem)
6998 )
6999)
7000
7001(define-pmacro (bitdstnos-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
7002 (begin
7003 (bitsrc16-defn op opc16-1 opc16-2 opc16-3 sem)
7004 (bitdst32-defn op opc32-1 opc32-2 opc32-3 sem)
7005 )
7006)
7007
7008(define-pmacro (bitdst-insn op opc16-1 opc16-2 opc16-3 opc16-4 opc16-5 opc16-6 opc32-1 opc32-2 opc32-3 sem)
7009 (begin
7010 (bitdst16-defn op opc16-1 opc16-2 opc16-3 opc16-4 opc16-5 opc16-6 sem)
7011 (bitdst32-defn op opc32-1 opc32-2 opc32-3 sem)
7012 )
7013)
7014
7015;=============================================================
7016; Bit condition
7017;
7018(define-pmacro (bitcond-insn-defn mach op bit-opnd cond-opnd encoding sem)
7019 (dni (.sym op mach - bit-opnd - cond-opnd)
7020 (.str op mach " " bit-opnd " " cond-opnd)
7021 ((machine mach))
7022 (.str op "${" cond-opnd "} ${" bit-opnd "}")
7023 encoding
7024 (sem mach bit-opnd cond-opnd)
7025 ())
7026)
7027
7028(define-pmacro (bitcond16-defn op opc1 opc2 opc3 sem)
7029 (begin
7030 (bitcond-insn-defn 16 op bit16-16-basic cond16-16 (+ opc1 opc2 opc3 bit16-16-basic cond16-16) sem)
7031 (bitcond-insn-defn 16 op bit16-16-16 cond16-32 (+ opc1 opc2 opc3 bit16-16-16 cond16-32) sem)
7032 (bitcond-insn-defn 16 op bit16-16-8 cond16-24 (+ opc1 opc2 opc3 bit16-16-8 cond16-24) sem)
7033 )
7034)
7035
7036(define-pmacro (bitcond32-defn op opc1 opc2 opc3 sem)
7037 (begin
7038 (bitcond-insn-defn 32 op bit32-16-24-Unprefixed cond32-40
7039 (+ (f-0-4 opc1) bit32-16-24-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-40)
7040 sem)
7041 (bitcond-insn-defn 32 op bit32-16-16-Unprefixed cond32-32
7042 (+ (f-0-4 opc1) bit32-16-16-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-32)
7043 sem)
7044 (bitcond-insn-defn 32 op bit32-16-8-Unprefixed cond32-24
7045 (+ (f-0-4 opc1) bit32-16-8-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-24)
7046 sem)
7047 (bitcond-insn-defn 32 op bit32-basic-Unprefixed cond32-16
7048 (+ (f-0-4 opc1) bit32-basic-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-16)
7049 sem)
7050 )
7051)
7052
7053(define-pmacro (bitcond-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
7054 (begin
7055 (bitcond16-defn op opc16-1 opc16-2 opc16-3 sem)
7056 (bitcond32-defn op opc32-1 opc32-2 opc32-3 sem)
7057 )
7058)
7059
7060;=============================================================
7061;<insn>.size #imm1,#imm2,dst -- for m32c
7062;
7063(define-pmacro (insn-imm1-imm2-dst-defn src1 src2 dstgroup xmode wstr op encoding sem)
7064 (dni (.sym op 32 wstr - src1 - src2 - dstgroup)
7065 (.str op 32 wstr "-" src1 "-" src2 "-" dstgroup "-" xmode)
7066 ((machine 32))
7067 (.str op wstr " #${" src1 "},#${" src2 "},${dst32-" dstgroup "-" xmode "}")
7068 encoding
7069 (sem xmode src1 src2 (.sym dst32- dstgroup - xmode))
7070 ())
7071)
7072
7073; m32c Prefixed variants
7074(define-pmacro (insn32-imm1-imm2-dst-Prefixed-defn xmode wstr wbit base1 base2 base3 base4 op opc1 opc2 opc3 sem)
7075 (begin
7076 (insn-imm1-imm2-dst-defn (.sym Imm-48- xmode) (.sym Imm- base4 - xmode) 24-24-Prefixed xmode wstr op
7077 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3)
7078 (.sym dst32-24-24-Prefixed- xmode) (.sym Imm-48- xmode) (.sym Imm- base4 - xmode))
7079 sem)
7080 (insn-imm1-imm2-dst-defn (.sym Imm-40- xmode) (.sym Imm- base3 - xmode) 24-16-Prefixed xmode wstr op
7081 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3)
7082 (.sym dst32-24-16-Prefixed- xmode) (.sym Imm-40- xmode) (.sym Imm- base3 - xmode))
7083 sem)
7084 (insn-imm1-imm2-dst-defn (.sym Imm-32- xmode) (.sym Imm- base2 - xmode) 24-8-Prefixed xmode wstr op
7085 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3)
7086 (.sym dst32-24-8-Prefixed- xmode) (.sym Imm-32- xmode) (.sym Imm- base2 - xmode))
7087 sem)
7088 (insn-imm1-imm2-dst-defn (.sym Imm-24- xmode) (.sym Imm- base1 - xmode) basic-Prefixed xmode wstr op
7089 (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3)
7090 (.sym dst32-basic-Prefixed- xmode) (.sym Imm-24- xmode) (.sym Imm- base1 - xmode))
7091 sem)
7092 )
7093)
7094
7095; m32c Unprefixed variants
7096(define-pmacro (insn32-imm1-imm2-dst-Unprefixed-defn xmode wstr wbit base1 base2 base3 base4 op opc1 opc2 opc3 sem)
7097 (begin
7098 (insn-imm1-imm2-dst-defn (.sym Imm-40- xmode) (.sym Imm- base4 - xmode) 16-24-Unprefixed xmode wstr op
7099 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3)
7100 (.sym dst32-16-24-Unprefixed- xmode) (.sym Imm-40- xmode) (.sym Imm- base4 - xmode))
7101 sem)
7102 (insn-imm1-imm2-dst-defn (.sym Imm-32- xmode) (.sym Imm- base3 - xmode) 16-16-Unprefixed xmode wstr op
7103 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3)
7104 (.sym dst32-16-16-Unprefixed- xmode) (.sym Imm-32- xmode) (.sym Imm- base3 - xmode))
7105 sem)
7106 (insn-imm1-imm2-dst-defn (.sym Imm-24- xmode) (.sym Imm- base2 - xmode) 16-8-Unprefixed xmode wstr op
7107 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3)
7108 (.sym dst32-16-8-Unprefixed- xmode) (.sym Imm-24- xmode) (.sym Imm- base2 - xmode))
7109 sem)
7110 (insn-imm1-imm2-dst-defn (.sym Imm-16- xmode) (.sym Imm- base1 - xmode) basic-Unprefixed xmode wstr op
7111 (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3)
7112 (.sym dst32-basic-Unprefixed- xmode) (.sym Imm-16- xmode) (.sym Imm- base1 - xmode))
7113 sem)
7114 )
7115)
7116
7117(define-pmacro (insn-imm1-imm2-dst-Prefixed op opc32-1 opc32-2 opc32-3 sem)
7118 (begin
7119 (insn32-imm1-imm2-dst-Prefixed-defn QI .b 0 32 40 48 56 op opc32-1 opc32-2 opc32-3 sem)
7120 (insn32-imm1-imm2-dst-Prefixed-defn HI .w 1 40 48 56 64 op opc32-1 opc32-2 opc32-3 sem)
7121 )
7122)
7123(define-pmacro (insn-imm1-imm2-dst-Unprefixed op opc32-1 opc32-2 opc32-3 sem)
7124 (begin
7125 (insn32-imm1-imm2-dst-Unprefixed-defn QI .b 0 24 32 40 48 op opc32-1 opc32-2 opc32-3 sem)
7126 (insn32-imm1-imm2-dst-Unprefixed-defn HI .w 1 32 40 48 56 op opc32-1 opc32-2 opc32-3 sem)
7127 )
7128)
7129\f
7130;=============================================================
7131; Insn definitions
7132;-------------------------------------------------------------
7133; abs - absolute
7134;-------------------------------------------------------------
7135
7136(define-pmacro (abs-sem mode dst)
7137 (sequence ((mode result))
7138 (set result (abs mode dst))
7139 (set obit (eq result dst))
7140 (set-z-and-s result)
7141 (set dst result))
7142)
7143(unary-insn abs (f-0-4 7) (f-4-3 3) (f-8-4 #xF) #xA #x1 #xF abs-sem)
7144
7145;-------------------------------------------------------------
7146; adcf - addition carry flag
7147;-------------------------------------------------------------
7148
7149(define-pmacro (adcf-sem mode dst)
7150 (sequence ((mode result))
7151 (set result (addc mode dst 0 cbit))
7152 (set obit (add-oflag mode dst 0 cbit))
7153 (set cbit (add-cflag mode dst 0 cbit))
7154 (set-z-and-s result)
7155 (set dst result))
7156)
7157(unary-insn adcf (f-0-4 7) (f-4-3 3) (f-8-4 #xE) #xB #x1 #xE adcf-sem)
7158
7159;-------------------------------------------------------------
7160; add - binary addition
7161;-------------------------------------------------------------
7162
7163(define-pmacro (add-sem mode src1 dst)
7164 (sequence ((mode result))
7165 (set result (add mode src1 dst))
7166 (set obit (add-oflag mode src1 dst 0))
7167 (set cbit (add-cflag mode src1 dst 0))
7168 (set-z-and-s result)
7169 (set dst result))
7170)
7171
7172; add.L:G #imm32,dst (m32 #2)
7173(binary-arith32-imm-dst-defn SI SI .l 0 add G #x8 #x3 #x1 add-sem)
7174; add.size:G #imm,dst (m16 #1 m32 #1)
7175(binary-arith-imm-dst add G (f-0-4 7) (f-4-3 3) (f-8-4 4) #x8 #x2 #xE add-sem)
7176; add.size:Q #imm4,dst (m16 #2 m32 #3)
7177(binary-arith-imm4-dst add (f-0-4 #xC) (f-4-3 4) #x7 #x3 add-sem)
7178(binary-arith32-imm4-dst-defn SI .l 1 0 add #x7 #x3 add-sem)
7179; add.b:S #imm8,dst3 (m16 #3)
7180(binary-arith16-b-S-imm8-dst3 add ".b" (f-0-4 8) (f-4-1 0) add-sem)
7181; add.BW:Q #imm4,sp (m16 #7)
7182(binary-arith16-Q-sp add (f-0-4 7) (f-4-4 #xD) (f-8-4 #xB) add-sem)
92e0a941
DD		 7183(dnmi add16-bQ-sp "add16-bQ-sp" ()
7184 "add.b:q #${Imm-12-s4},sp"
7185 (emit add16-wQ-sp Imm-12-s4))
49f58d10
JB		 7186; add.BW:G #imm,sp (m16 #6)
7187(binary-arith16-G-sp add (f-0-4 7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #xB) add-sem)
7188; add.BW:G src,dst (m16 #4 m32 #6)
7189(binary-arith-src-dst add G (f-0-4 #xA) (f-4-3 0) #x1 #x8 add-sem)
7190; add.B.S src2,r0l/r0h (m16 #5)
7191(binary-arith16-b-S-src2 add (f-0-4 2) (f-4-1 0) add-sem)
7192; add.L:G src,dst (m32 #7)
7193(binary-arith32-src-dst-defn SI SI .l 1 add G #x1 #x2 add-sem)
7194; add.L:S #imm{1,2},A0/A1 (m32 #5)
7195(binary-arith32-l-s-imm1-an add (f-0-2 2) (f-3-4 6) add-sem)
7196; add.L:Q #imm3,sp (m32 #9)
7197(binary-arith32-l-q-imm3-sp add (f-0-2 1) (f-4-3 1) add-sem)
7198; add.L:S #imm8,sp (m32 #10)
7199(binary-arith32-l-s-imm8-sp add (f-0-4 #xb) (f-4-4 6) (f-8-4 0) (f-12-4 3) add-sem)
7200; add.L:G #imm16,sp (m32 #8)
7201(binary-arith32-l-g-imm16-sp add (f-0-4 #xb) (f-4-4 6) (f-8-4 1) (f-12-4 3) add-sem)
7202; add.BW:S #imm,dst2 (m32 #4)
7203(binary-arith32-s-imm-dst QI .b 0 add #x0 #x3 add-sem)
7204(binary-arith32-s-imm-dst HI .w 1 add #x0 #x3 add-sem)
7205
7206;-------------------------------------------------------------
7207; adc - binary add with carry
7208;-------------------------------------------------------------
7209
7210(define-pmacro (addc-sem mode src dst)
7211 (sequence ((mode result))
7212 (set result (addc mode src dst cbit))
7213 (set obit (add-oflag mode src dst cbit))
7214 (set cbit (add-cflag mode src dst cbit))
7215 (set-z-and-s result)
7216 (set dst result))
7217)
7218
7219; adc.size:G #imm,dst
7220(binary-arith16-imm-dst-defn QI QI .b 0 adc X (f-0-4 7) (f-4-3 3) (f-8-4 6) addc-sem)
7221(binary-arith16-imm-dst-defn HI HI .w 1 adc X (f-0-4 7) (f-4-3 3) (f-8-4 6) addc-sem)
7222(binary-arith32-imm-dst-Prefixed QI QI .b 0 adc X #x8 #x2 #xE addc-sem)
7223(binary-arith32-imm-dst-Prefixed HI HI .w 1 adc X #x8 #x2 #xE addc-sem)
7224
7225; adc.BW:G src,dst
7226(binary-arith16-src-dst-defn QI QI .b 0 adc X (f-0-4 #xB) (f-4-3 0) addc-sem)
7227(binary-arith16-src-dst-defn HI HI .w 1 adc X (f-0-4 #xB) (f-4-3 0) addc-sem)
7228(binary-arith32-src-dst-Prefixed QI QI .b 0 adc X #x1 #x4 addc-sem)
7229(binary-arith32-src-dst-Prefixed HI HI .w 1 adc X #x1 #x4 addc-sem)
7230
7231;-------------------------------------------------------------
7232; dadc - decimal add with carry
7233; dadd - decimal addition
7234;-------------------------------------------------------------
7235
7236(define-pmacro (dadc-sem mode src dst)
7237 (sequence ((mode result))
7238 (set result (subc mode dst src (not cbit)))
7239 (set cbit (sub-cflag mode dst src (not cbit)))
7240 (set-z-and-s result)
7241 (set dst result))
7242)
7243
7244(define-pmacro (decimal-subtraction16-insn op opc1 opc2)
7245 (begin
7246 ; op.b #imm8,r0l
7247 (dni (.sym op 16.b-imm8)
7248 (.str op ".b #imm8")
7249 ((machine 16))
8d0e2679 7250 (.str op ".b #${Imm-16-QI},r0l")
49f58d10
JB		 7251 (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 opc1) Imm-16-QI)
7252 ((.sym op -sem) QI Imm-16-QI R0l)
7253 ())
7254 ; op.w #imm16,r0
7255 (dni (.sym op 16.w-imm16)
7256 (.str op ".b #imm16")
7257 ((machine 16))
8d0e2679 7258 (.str op ".w #${Imm-16-HI},r0")
49f58d10
JB		 7259 (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 opc1) Imm-16-HI)
7260 ((.sym op -sem) HI Imm-16-HI R0)
7261 ())
7262 ; op.b #r0h,r0l
7263 (dni (.sym op 16.b-r0h-r0l)
7264 (.str op ".b r0h,r0l")
7265 ((machine 16))
7266 (.str op ".b r0h,r0l")
7267 (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 opc2))
7268 ((.sym op -sem) QI R0h R0l)
7269 ())
7270 ; op.w #r1,r0
7271 (dni (.sym op 16.w-r1-r0)
7272 (.str op ".b r1,r0")
7273 ((machine 16))
7274 (.str op ".w r1,r0")
7275 (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 opc2))
7276 ((.sym op -sem) HI R1 R0)
7277 ())
7278 )
7279)
7280
7281; dadc for m16c
7282(decimal-subtraction16-insn dadc #xE #x6 )
7283
7284; dadc.size #imm,dst
7285(binary-arith32-imm-dst-Prefixed QI QI .b 0 dadc X #x8 #x0 #xE dadc-sem)
7286(binary-arith32-imm-dst-Prefixed HI HI .w 1 dadc X #x8 #x0 #xE dadc-sem)
7287; dadc.BW src,dst
7288(binary-arith32-src-dst-Prefixed QI QI .b 0 dadc X #x1 #x8 dadc-sem)
7289(binary-arith32-src-dst-Prefixed HI HI .w 1 dadc X #x1 #x8 dadc-sem)
7290
7291(define-pmacro (dadd-sem mode src dst)
7292 (sequence ((mode result))
7293 (set result (subc mode dst src 0))
7294 (set cbit (sub-cflag mode dst src 0))
7295 (set-z-and-s result)
7296 (set dst result))
7297)
7298
7299; dadd for m16c
7300(decimal-subtraction16-insn dadd #xC #x4)
7301
7302; dadd.size #imm,dst
7303(binary-arith32-imm-dst-Prefixed QI QI .b 0 dadd X #x8 #x1 #xE dadd-sem)
7304(binary-arith32-imm-dst-Prefixed HI HI .w 1 dadd X #x8 #x1 #xE dadd-sem)
7305; dadd.BW src,dst
7306(binary-arith32-src-dst-Prefixed QI QI .b 0 dadd X #x1 #x0 dadd-sem)
7307(binary-arith32-src-dst-Prefixed HI HI .w 1 dadd X #x1 #x0 dadd-sem)
7308
7309;-------------------------------------------------------------;
7310; addx - Add extend sign with no carry
7311;-------------------------------------------------------------;
7312
7313(define-pmacro (addx-sem mode src dst)
7314 (sequence ((SI source) (SI result))
7315 (set source (zext SI (trunc QI src)))
7316 (set result (add SI source dst))
7317 (set obit (add-oflag SI source dst 0))
7318 (set cbit (add-cflag SI source dst 0))
7319 (set-z-and-s result)
7320 (set dst result))
7321)
7322
7323; addx #imm,dst
7324(binary-arith32-imm-dst-defn QI SI "" 0 addx X #x8 #x1 #x1 addx-sem)
7325; addx src,dst
7326(binary-arith32-src-dst-defn QI SI "" 0 addx X #x1 #x2 addx-sem)
7327
7328;-------------------------------------------------------------
7329; adjnz - Add/Sub and branch if not zero
7330;-------------------------------------------------------------
7331
7332(define-pmacro (arith-jnz-sem mode src dst label)
7333 (sequence ((mode result))
7334 (set result (add mode src dst))
7335 (set dst result)
7336 (if (ne result 0)
7337 (set pc label)))
7338)
7339
7340; adjnz.size #imm4,dst,label
c6552317 7341(arith-jnz-imm4-dst adjnz s4 (f-0-4 #xF) (f-4-3 4) #xf #x1 arith-jnz-sem)
49f58d10
JB		 7342
7343;-------------------------------------------------------------
7344; and - binary and
7345;-------------------------------------------------------------
7346
7347(define-pmacro (and-sem mode src1 dst)
7348 (sequence ((mode result))
7349 (set result (and mode src1 dst))
7350 (set-z-and-s result)
7351 (set dst result))
7352)
7353
7354; and.size:G #imm,dst (m16 #1 m32 #1)
7355(binary-arith-imm-dst and G (f-0-4 7) (f-4-3 3) (f-8-4 2) #x8 #x3 #xF and-sem)
7356; and.b:S #imm8,dst3 (m16 #2)
7357(binary-arith16-b-S-imm8-dst3 and ".b" (f-0-4 9) (f-4-1 0) and-sem)
7358; and.BW:G src,dst (m16 #3 m32 #3)
7359(binary-arith-src-dst and G (f-0-4 #x9) (f-4-3 0) #x1 #xD and-sem)
7360; and.B.S src2,r0l/r0h (m16 #4)
7361(binary-arith16-b-S-src2 and (f-0-4 1) (f-4-1 0) and-sem)
7362; and.BW:S #imm,dst2 (m32 #2)
7363(binary-arith32-s-imm-dst QI .b 0 and #x1 #x6 and-sem)
7364(binary-arith32-s-imm-dst HI .w 1 and #x1 #x6 and-sem)
7365
7366;-------------------------------------------------------------
7367; band - bit and
7368;-------------------------------------------------------------
7369
7370(define-pmacro (band-sem src)
7371 (set cbit (and src cbit))
7372)
7373(bitsrc-insn band (f-0-4 7) (f-4-4 #xE) (f-8-4 4) #xD #x0 #x1 band-sem)
7374
7375;-------------------------------------------------------------
7376; bclr - bit clear
7377;-------------------------------------------------------------
7378
7379(define-pmacro (bclr-sem dst)
7380 (set dst 0)
7381)
7382(bitdst-insn bclr (f-0-4 7) (f-4-4 #xE) (f-8-4 8) (f-0-2 1) (f-2-2 0) (f-4-1 0) #xD #x0 #x6 bclr-sem)
7383
7384;-------------------------------------------------------------
7385; bitindex - bit index
7386;-------------------------------------------------------------
7387
7388(define-pmacro (bitindex-sem mode dst)
7389 (set BitIndex dst)
7390)
7391(unary-insn-defn 32 16-Unprefixed QI .b bitindex
7392 (+ (f-0-4 #xC) (f-7-1 0) dst32-16-Unprefixed-QI (f-10-2 #x2) (f-12-4 #xE))
7393 bitindex-sem)
7394(unary-insn-defn 32 16-Unprefixed HI .w bitindex
7395 (+ (f-0-4 #xC) (f-7-1 1) dst32-16-Unprefixed-HI (f-10-2 #x2) (f-12-4 #xE))
7396 bitindex-sem)
7397
7398;-------------------------------------------------------------
7399; bmCnd - bit move condition
7400;-------------------------------------------------------------
7401
7402(define-pmacro (test-condition16 cond)
7403 (case UQI cond
7404 ((#x00) (trunc BI cbit))
7405 ((#x01) (not (or cbit zbit)))
7406 ((#x02) (trunc BI zbit))
7407 ((#x03) (trunc BI sbit))
7408 ((#x04) (or zbit (xor sbit obit)))
7409 ((#x05) (trunc BI obit))
7410 ((#x06) (xor sbit obit))
7411 ((#xf8) (not cbit))
7412 ((#xf9) (or cbit zbit))
7413 ((#xfa) (not zbit))
7414 ((#xfb) (not sbit))
7415 ((#xfc) (not (or zbit (xor sbit obit))))
7416 ((#xfd) (not obit))
7417 ((#xfe) (not (xor sbit obit)))
7418 (else (const BI 0))
7419 )
7420)
7421
7422(define-pmacro (test-condition32 cond)
7423 (case UQI cond
7424 ((#x00) (not cbit))
7425 ((#x01) (or cbit zbit))
7426 ((#x02) (not zbit))
7427 ((#x03) (not sbit))
7428 ((#x04) (not obit))
7429 ((#x05) (not (or zbit (xor sbit obit))))
7430 ((#x06) (not (xor sbit obit)))
7431 ((#x08) (trunc BI cbit))
7432 ((#x09) (not (or cbit zbit)))
7433 ((#x0a) (trunc BI zbit))
7434 ((#x0b) (trunc BI sbit))
7435 ((#x0c) (trunc BI obit))
7436 ((#x0d) (or zbit (xor sbit obit)))
7437 ((#x0e) (xor sbit obit))
7438 (else (const BI 0))
7439 )
7440)
7441
7442(define-pmacro (bitcond-sem mach op cond)
7443 (if ((.sym test-condition mach) cond)
7444 (set op 1)
7445 (set op 0))
7446)
7447(bitcond-insn bm (f-0-4 7) (f-4-4 #xE) (f-8-4 2) #xD #x0 #x2 bitcond-sem)
7448
7449(dni bm16-c
7450 "bm16 C"
7451 ((machine 16))
7452 "bm$cond16c c"
7453 (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xD) cond16c)
7454 (bitcond-sem 16 cbit cond16c)
7455 ())
7456
7457(dni bm32-c
7458 "bm32 C"
7459 ((machine 32))
7460 "bm$cond32 c"
7461 (+ (f-0-4 #xD) (f-4-4 #x9) (f-8-1 0) (f-10-3 5) cond32)
7462 (bitcond-sem 32 cbit cond32)
7463 ())
7464
7465;-------------------------------------------------------------
7466; bnand
7467;-------------------------------------------------------------
7468
7469(define-pmacro (bnand-sem src)
7470 (set cbit (and (inv src) cbit))
7471)
7472(bitsrc-insn bnand (f-0-4 7) (f-4-4 #xE) (f-8-4 5) #xD #x0 #x3 bnand-sem)
7473
7474;-------------------------------------------------------------
7475; bnor
7476;-------------------------------------------------------------
7477
7478(define-pmacro (bnor-sem src)
7479 (set cbit (or (inv src) cbit))
7480)
7481(bitsrc-insn bnor (f-0-4 7) (f-4-4 #xE) (f-8-4 7) #xD #x0 #x6 bnor-sem)
7482
7483;-------------------------------------------------------------
7484; bnot
7485;-------------------------------------------------------------
7486
7487(define-pmacro (bnot-sem dst)
7488 (set dst (inv dst))
7489)
7490(bitdst-insn bnot (f-0-4 7) (f-4-4 #xE) (f-8-4 #xA) (f-0-2 1) (f-2-2 1) (f-4-1 0) #xD #x0 #x3 bnot-sem)
7491
7492;-------------------------------------------------------------
7493; bntst
7494;-------------------------------------------------------------
7495
7496(define-pmacro (bntst-sem src)
7497 (set cbit (inv src))
7498 (set zbit (inv src))
7499)
7500(bitsrc-insn bntst (f-0-4 7) (f-4-4 #xE) (f-8-4 3) #xD #x0 #x0 bntst-sem)
7501
7502;-------------------------------------------------------------
7503; bnxor
7504;-------------------------------------------------------------
7505
7506(define-pmacro (bnxor-sem src)
7507 (set cbit (xor (inv src) cbit))
7508)
7509(bitsrc-insn bnxor (f-0-4 7) (f-4-4 #xE) (f-8-4 #xD) #xD #x0 #x7 bnxor-sem)
7510
7511;-------------------------------------------------------------
7512; bor
7513;-------------------------------------------------------------
7514
7515(define-pmacro (bor-sem src)
7516 (set cbit (or src cbit))
7517)
7518(bitsrc-insn bor (f-0-4 7) (f-4-4 #xE) (f-8-4 #x6) #xD #x0 #x4 bor-sem)
7519
7520;-------------------------------------------------------------
7521; brk
7522;-------------------------------------------------------------
7523
7524(dni brk16
7525 "brk"
7526 ((machine 16))
7527 "brk"
7528 (+ (f-0-4 #x0) (f-4-4 #x0))
7529 (nop)
7530 ())
7531
7532(dni brk32
7533 "brk"
7534 ((machine 32))
7535 "brk"
7536 (+ (f-0-4 #x0) (f-4-4 #x0))
7537 (nop)
7538 ())
7539
7540;-------------------------------------------------------------
7541; brk2
7542;-------------------------------------------------------------
7543
7544(dni brk232
7545 "brk2"
7546 ((machine 32))
7547 "brk2"
7548 (+ (f-0-4 #x0) (f-4-4 #x8))
7549 (nop)
7550 ())
7551
7552;-------------------------------------------------------------
7553; bset
7554;-------------------------------------------------------------
7555
7556(define-pmacro (bset-sem dst)
7557 (set dst 1)
7558)
7559(bitdst-insn bset (f-0-4 7) (f-4-4 #xE) (f-8-4 9) (f-0-2 1) (f-2-2 0) (f-4-1 1) #xD #x0 #x7 bset-sem)
7560
7561;-------------------------------------------------------------
7562; btst
7563;-------------------------------------------------------------
7564
7565(define-pmacro (btst-sem dst)
7566 (set zbit (inv dst))
7567 (set cbit dst)
7568)
8d0e2679
DD		 7569(bitdst16-defn btst (f-0-4 7) (f-4-4 #xE) (f-8-4 #xB) (f-0-2 1) (f-2-2 1) (f-4-1 1) btst-sem)
7570
7571(bit-insn-defn 32 btst G bit32-16-Unprefixed
7572 (+ (f-0-4 #xD) bit32-16-Unprefixed (f-7-1 #x0) (f-10-3 #x0))
7573 btst-sem)
7574
43aa3bb1
DD		 7575(dni btst.s "btst:s" ((machine 32))
7576 "btst:s ${Bit3-S},${Dsp-8-u16}"
7577 (+ (f-0-2 #x0) (f-4-3 #x5) Bit3-S Dsp-8-u16)
7578 () ())
49f58d10
JB		 7579
7580;-------------------------------------------------------------
7581; btstc
7582;-------------------------------------------------------------
7583
7584(define-pmacro (btstc-sem dst)
7585 (set zbit (inv dst))
7586 (set cbit dst)
7587 (set dst (const 0))
7588)
7589(bitdstnos-insn btstc (f-0-4 7) (f-4-4 #xE) (f-8-4 #x0) #xD #x0 #x4 btstc-sem)
7590
7591;-------------------------------------------------------------
7592; btsts
7593;-------------------------------------------------------------
7594
7595(define-pmacro (btsts-sem dst)
7596 (set zbit (inv dst))
7597 (set cbit dst)
7598 (set dst (const 0))
7599)
7600(bitdstnos-insn btsts (f-0-4 7) (f-4-4 #xE) (f-8-4 #x1) #xD #x0 #x5 btsts-sem)
7601
7602;-------------------------------------------------------------
7603; bxor
7604;-------------------------------------------------------------
7605
7606(define-pmacro (bxor-sem src)
7607 (set cbit (xor src cbit))
7608)
7609(bitsrc-insn bxor (f-0-4 7) (f-4-4 #xE) (f-8-4 #xC) #xD #x0 #x5 bxor-sem)
7610
7611;-------------------------------------------------------------
7612; clip
7613;-------------------------------------------------------------
7614
7615(define-pmacro (clip-sem mode imm1 imm2 dest)
7616 (sequence ()
7617 (if (gt mode imm1 dest)
7618 (set dest imm1))
7619 (if (lt mode imm2 dest)
7620 (set dest imm2)))
7621)
7622
7623(insn-imm1-imm2-dst-Prefixed clip #x8 #x3 #xE clip-sem)
7624
7625;-------------------------------------------------------------
7626; cmp - binary compare
7627;-------------------------------------------------------------
7628
7629(define-pmacro (cmp-sem mode src1 dst)
7630 (sequence ((mode result))
7631 (set result (sub mode dst src1))
7632 (set obit (sub-oflag mode dst src1 0))
7633 (set cbit (not (sub-cflag mode dst src1 0)))
7634 (set-z-and-s result))
7635)
7636
7637; cmp.L:G #imm32,dst (m32 #2)
7638(binary-arith32-imm-dst-defn SI SI .l 0 cmp G #xA #x3 #x1 cmp-sem)
7639; cmp.size:G #imm,dst (m16 #1 m32 #1)
7640(binary-arith-imm-dst cmp G (f-0-4 7) (f-4-3 3) (f-8-4 8) #x9 #x2 #xE cmp-sem)
7641; cmp.size:Q #imm4,dst (m16 #2 m32 #3)
7642(binary-arith-imm4-dst cmp (f-0-4 #xD) (f-4-3 0) #x7 #x1 cmp-sem)
7643; cmp.b:S #imm8,dst3 (m16 #3)
7644(binary-arith16-b-S-imm8-dst3 cmp ".b" (f-0-4 #xE) (f-4-1 0) cmp-sem)
7645; cmp.BW:G src,dst (m16 #4 m32 #5)
7646(binary-arith-src-dst cmp G (f-0-4 #xC) (f-4-3 0) #x1 #x6 cmp-sem)
7647; cmp.B.S src2,r0l/r0h (m16 #5)
7648(binary-arith16-b-S-src2 cmp (f-0-4 3) (f-4-1 1) cmp-sem)
7649; cmp.L:G src,dst (m32 #6)
7650(binary-arith32-src-dst-defn SI SI .l 1 cmp G #x1 #x1 cmp-sem)
7651; cmp.BW:S #imm,dst2 (m32 #4)
7652(binary-arith32-s-imm-dst QI .b 0 cmp #x1 #x3 cmp-sem)
7653(binary-arith32-s-imm-dst HI .w 1 cmp #x1 #x3 cmp-sem)
7654; cmp.BW:s src2,r0[l] (m32 #7)
7655(binary-arith32-S-src2 cmp QI .b 0 (f-0-2 1) (f-4-3 0) cmp-sem)
7656(binary-arith32-S-src2 cmp HI .w 1 (f-0-2 1) (f-4-3 0) cmp-sem)
7657
7658;-------------------------------------------------------------
7659; cmpx - binary compare extend sign
7660;-------------------------------------------------------------
7661
7662(define-pmacro (cmpx-sem mode src1 dst)
7663 (sequence ((mode result))
7664 (set result (sub mode dst (ext mode src1)))
7665 (set obit (sub-oflag mode dst (ext mode src1) 0))
7666 (set cbit (sub-cflag mode dst (ext mode src1) 0))
7667 (set-z-and-s result))
7668)
7669
7670(binary-arith32-imm-dst-defn QI SI "" 0 cmpx X #xA #x1 #x1 cmpx-sem)
7671
7672;-------------------------------------------------------------
7673; dec - decrement
7674;-------------------------------------------------------------
7675
7676(define-pmacro (dec-sem mode dest)
7677 (sequence ((mode result))
7678 (set result (sub mode dest 1))
7679 (set-z-and-s result)
7680 (set dest result))
7681)
7682
7683(dni dec16.b
7684 "dec.b Dst16-3-S-8"
7685 ((machine 16))
7686 "dec.b ${Dst16-3-S-8}"
7687 (+ (f-0-4 #xA) (f-4-1 #x1) Dst16-3-S-8)
7688 (dec-sem QI Dst16-3-S-8)
7689 ())
7690
7691(dni dec16.w
7692 "dec.w Dst16An-S"
7693 ((machine 16))
7694 "dec.w ${Dst16An-S}"
7695 (+ (f-0-4 #xF) (f-5-3 #x2) Dst16An-S)
7696 (dec-sem HI Dst16An-S)
7697 ())
7698
7699(unary32-defn QI .b 0 dec #xB #x0 #xE dec-sem)
7700(unary32-defn HI .w 1 dec #xB #x0 #xE dec-sem)
7701
7702;-------------------------------------------------------------
7703; div - divide
7704; divu - divide unsigned
7705; divx - divide extension
7706;-------------------------------------------------------------
7707
7708; div.BW #imm
7709(div-imm div div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #x1) #xB #x0 #x2 #x3 div-sem)
7710(div-imm divu udiv umod USI 255 0 65535 0 (f-0-4 #x7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #x0) #xB #x0 #x0 #x3 div-sem)
7711(div-imm divx div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #x3) #xB #x2 #x2 #x3 div-sem)
7712; div.BW src
7713(div-src div div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 3) (f-8-4 #xD) #x8 #x1 #xE div-sem)
7714(div-src divu udiv umod USI 255 0 65535 0 (f-0-4 #x7) (f-4-3 3) (f-8-4 #xC) #x8 #x0 #xE div-sem)
7715(div-src divx div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 3) (f-8-4 #x9) #x9 #x1 #xE div-sem)
7716
7717(div-src-defn 32 .l div dst32-24-Prefixed-SI
7718 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xA) (f-15-1 1) (f-18-2 #x1) (f-20-4 #xf) dst32-24-Prefixed-SI)
7719 div mod SI R2R0 R2R0 NoRemainder #x7fffffff (neg SI #x80000000)
7720 div-sem)
7721(div-src-defn 32 .l divu dst32-24-Prefixed-SI
7722 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xA) (f-15-1 1) (f-18-2 #x0) (f-20-4 #xf) dst32-24-Prefixed-SI)
7723 udiv umod USI R2R0 R2R0 NoRemainder #x80000000 0
7724 div-sem)
7725(div-src-defn 32 .l divx dst32-24-Prefixed-SI
7726 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xA) (f-15-1 1) (f-18-2 #x2) (f-20-4 #xf) dst32-24-Prefixed-SI)
7727 div mod SI R2R0 R2R0 NoRemainder #x7fffffff (neg SI #x80000000)
7728 div-sem)
7729
7730;-------------------------------------------------------------
7731; dsbb - decimal subtraction with borrow
7732; dsub - decimal subtraction
7733;-------------------------------------------------------------
7734
7735(define-pmacro (dsbb-sem mode src dst)
7736 (sequence ((mode result))
7737 (set result (subc mode dst src (not cbit)))
7738 (set cbit (sub-cflag mode dst src (not cbit)))
7739 (set-z-and-s result)
7740 (set dst result))
7741)
7742
7743; dsbb for m16c
7744(decimal-subtraction16-insn dsbb #xF #x7)
7745
7746; dsbb.size #imm,dst
7747(binary-arith32-imm-dst-Prefixed QI QI .b 0 dsbb X #x9 #x0 #xE dsbb-sem)
7748(binary-arith32-imm-dst-Prefixed HI HI .w 1 dsbb X #x9 #x0 #xE dsbb-sem)
7749; dsbb.BW src,dst
7750(binary-arith32-src-dst-Prefixed QI QI .b 0 dsbb X #x1 #xA dsbb-sem)
7751(binary-arith32-src-dst-Prefixed HI HI .w 1 dsbb X #x1 #xA dsbb-sem)
7752
7753(define-pmacro (dsub-sem mode src dst)
7754 (sequence ((mode result))
7755 (set result (subc mode dst src 0))
7756 (set cbit (sub-cflag mode dst src 0))
7757 (set-z-and-s result)
7758 (set dst result))
7759)
7760
7761; dsub for m16c
7762(decimal-subtraction16-insn dsub #xD #x5)
7763
7764; dsub.size #imm,dst
7765(binary-arith32-imm-dst-Prefixed QI QI .b 0 dsub X #x9 #x1 #xE dsub-sem)
7766(binary-arith32-imm-dst-Prefixed HI HI .w 1 dsub X #x9 #x1 #xE dsub-sem)
7767; dsub.BW src,dst
7768(binary-arith32-src-dst-Prefixed QI QI .b 0 dsub X #x1 #x2 dsub-sem)
7769(binary-arith32-src-dst-Prefixed HI HI .w 1 dsub X #x1 #x2 dsub-sem)
7770
7771;-------------------------------------------------------------
7772; sub - binary subtraction
7773;-------------------------------------------------------------
7774
7775(define-pmacro (sub-sem mode src1 dst)
7776 (sequence ((mode result))
7777 (set result (sub mode dst src1))
7778 (set obit (sub-oflag mode dst src1 0))
7779 (set cbit (sub-cflag mode dst src1 0))
7780 (set dst result)
7781 (set-z-and-s result)))
7782
7783; sub.size:G #imm,dst (m16 #1 m32 #1)
7784(binary-arith-imm-dst sub G (f-0-4 7) (f-4-3 3) (f-8-4 5) #x8 #x3 #xE sub-sem)
7785; sub.b:S #imm8,dst3 (m16 #2)
7786(binary-arith16-b-S-imm8-dst3 sub ".b" (f-0-4 8) (f-4-1 1) sub-sem)
7787; sub.BW:G src,dst (m16 #3 m32 #4)
7788(binary-arith-src-dst sub G (f-0-4 #xA) (f-4-3 4) #x1 #xA sub-sem)
7789; sub.B.S src2,r0l/r0h (m16 #4)
7790(binary-arith16-b-S-src2 sub (f-0-4 2) (f-4-1 1) sub-sem)
7791; sub.L:G #imm32,dst (m32 #2)
7792(binary-arith32-imm-dst-defn SI SI .l 0 sub G #x9 #x3 #x1 sub-sem)
7793; sub.BW:S #imm,dst2 (m32 #3)
7794(binary-arith32-s-imm-dst QI .b 0 sub #x0 #x7 sub-sem)
7795(binary-arith32-s-imm-dst HI .w 1 sub #x0 #x7 sub-sem)
7796; sub.L:G src,dst (m32 #5)
7797(binary-arith32-src-dst-defn SI SI .l 1 sub G #x1 #x0 sub-sem)
7798
7799;-------------------------------------------------------------
7800; enter - enter function
7801; exitd - exit and deallocate stack frame
7802;-------------------------------------------------------------
7803
7804(define-pmacro (enter16-sem mach amt)
7805 (sequence ()
7806 (set (reg h-sp) (sub (reg h-sp) 2))
7807 (set (mem16 HI (reg h-sp)) (reg h-fb))
7808 (set (reg h-fb) (reg h-sp))
7809 (set (reg h-sp) (sub (reg h-sp) amt))))
7810
7811(define-pmacro (exit16-sem mach)
7812 (sequence ((SI newpc))
7813 (set (reg h-sp) (reg h-fb))
7814 (set (reg h-fb) (mem16 HI (reg h-sp)))
7815 (set (reg h-sp) (add (reg h-sp) 2))
7816 (set newpc (mem16 HI (reg h-sp)))
7817 (set (reg h-sp) (add (reg h-sp) 2))
7818 (set newpc (or newpc (sll (mem16 QI (reg h-sp)) (const 16))))
7819 (set (reg h-sp) (add (reg h-sp) 1))
7820 (set pc newpc)))
7821
7822(define-pmacro (enter32-sem mach amt)
7823 (sequence ()
7824 (set (reg h-sp) (sub (reg h-sp) 4))
7825 (set (mem32 SI (reg h-sp)) (reg h-fb))
7826 (set (reg h-fb) (reg h-sp))
7827 (set (reg h-sp) (sub (reg h-sp) amt))))
7828
7829(define-pmacro (exit32-sem mach)
7830 (sequence ((SI newpc))
7831 (set (reg h-sp) (reg h-fb))
7832 (set (reg h-fb) (mem32 SI (reg h-sp)))
7833 (set (reg h-sp) (add (reg h-sp) 4))
7834 (set newpc (mem32 SI (reg h-sp)))
7835 (set (reg h-sp) (add (reg h-sp) 4))
7836 (set pc newpc)))
7837
7838(dni enter16 "enter #Imm-16-QI" ((machine 16))
7839 ("enter #${Dsp-16-u8}")
7840 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 2) Dsp-16-u8)
7841 (enter16-sem 16 Dsp-16-u8)
7842 ())
7843
7844(dni exitd16 "exitd" ((machine 16))
7845 ("exitd")
7846 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 2))
7847 (exit16-sem 16)
7848 ())
7849
7850(dni enter32 "enter #Imm-8-QI" ((machine 32))
7851 ("enter #${Dsp-8-u8}")
7852 (+ (f-0-4 #xE) (f-4-4 #xC) Dsp-8-u8)
7853 (enter32-sem 32 Dsp-8-u8)
7854 ())
7855
7856(dni exitd32 "exitd" ((machine 32))
7857 ("exitd")
7858 (+ (f-0-4 #xF) (f-4-4 #xC))
7859 (exit32-sem 32)
7860 ())
7861
7862;-------------------------------------------------------------
7863; fclr - flag register clear
7864; fset - flag register set
7865;-------------------------------------------------------------
7866
7867(define-pmacro (set-flags-sem flag)
7868 (sequence ((SI tmp))
7869 (case DFLT flag
7870 ((#x0) (set cbit 1))
7871 ((#x1) (set dbit 1))
7872 ((#x2) (set zbit 1))
7873 ((#x3) (set sbit 1))
7874 ((#x4) (set bbit 1))
7875 ((#x5) (set obit 1))
7876 ((#x6) (set ibit 1))
7877 ((#x7) (set ubit 1)))
7878 )
7879 )
7880
7881(define-pmacro (clear-flags-sem flag)
7882 (sequence ((SI tmp))
7883 (case DFLT flag
7884 ((#x0) (set cbit 0))
7885 ((#x1) (set dbit 0))
7886 ((#x2) (set zbit 0))
7887 ((#x3) (set sbit 0))
7888 ((#x4) (set bbit 0))
7889 ((#x5) (set obit 0))
7890 ((#x6) (set ibit 0))
7891 ((#x7) (set ubit 0)))
7892 )
7893 )
7894
7895(dni fclr16 "fclr flag" ((machine 16))
7896 ("fclr ${flags16}")
7897 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) flags16 (f-12-4 5))
7898 (clear-flags-sem flags16)
7899 ())
7900
7901(dni fset16 "fset flag" ((machine 16))
7902 ("fset ${flags16}")
7903 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) flags16 (f-12-4 4))
7904 (set-flags-sem flags16)
7905 ())
7906
7907(dni fclr "fclr" ((machine 32))
7908 ("fclr ${flags32}")
7909 (+ (f-0-4 #xD) (f-4-4 3) (f-8-4 #xE) (f-12-1 1) flags32)
7910 (clear-flags-sem flags32)
7911 ())
7912
7913(dni fset "fset" ((machine 32))
7914 ("fset ${flags32}")
7915 (+ (f-0-4 #xD) (f-4-4 1) (f-8-4 #xE) (f-12-1 1) flags32)
7916 (set-flags-sem flags32)
7917 ())
7918
7919;-------------------------------------------------------------
7920; inc - increment
7921;-------------------------------------------------------------
7922
7923(define-pmacro (inc-sem mode dest)
7924 (sequence ((mode result))
7925 (set result (add mode dest 1))
7926 (set-z-and-s result)
7927 (set dest result))
7928)
7929
7930(dni inc16.b
7931 "inc.b Dst16-3-S-8"
7932 ((machine 16))
7933 "inc.b ${Dst16-3-S-8}"
7934 (+ (f-0-4 #xA) (f-4-1 #x0) Dst16-3-S-8)
7935 (inc-sem QI Dst16-3-S-8)
7936 ())
7937
7938(dni inc16.w
7939 "inc.w Dst16An-S"
7940 ((machine 16))
7941 "inc.w ${Dst16An-S}"
7942 (+ (f-0-4 #xB) (f-5-3 #x2) Dst16An-S)
7943 (inc-sem HI Dst16An-S)
7944 ())
7945
7946(unary32-defn QI .b 0 inc #xA #x0 #xE inc-sem)
7947(unary32-defn HI .w 1 inc #xA #x0 #xE inc-sem)
7948
7949;-------------------------------------------------------------
7950; freit - fast return from interrupt (m32)
7951; int - interrupt
7952; into - interrupt on overflow
7953;-------------------------------------------------------------
7954
7955; ??? semantics
7956(dni freit32 "FREIT" ((machine 32))
7957 ("freit")
7958 (+ (f-0-4 9) (f-4-4 #xF))
7959 (nop)
7960 ())
7961
7962(dni int16 "int Dsp-10-u6" ((machine 16))
7963 ("int #${Dsp-10-u6}")
7964 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-2 3) Dsp-10-u6)
7965 (c-call VOID "do_int" pc Dsp-10-u6)
7966 ())
7967
7968(dni into16 "into" ((machine 16))
7969 ("into")
7970 (+ (f-0-4 #xF) (f-4-4 6))
7971 (nop)
7972 ())
7973
7974(dni int32 "int Dsp-8-u6" ((machine 32))
7975 ("int #${Dsp-8-u6}")
7976 (+ (f-0-4 #xB) (f-4-4 #xE) Dsp-8-u6 (f-14-2 0))
7977 (c-call VOID "do_int" pc Dsp-8-u6)
7978 ())
7979
7980(dni into32 "into" ((machine 32))
7981 ("into")
7982 (+ (f-0-4 #xB) (f-4-4 #xF))
7983 (nop)
7984 ())
7985
7986;-------------------------------------------------------------
7987; index (m32c)
7988;-------------------------------------------------------------
7989
7990; TODO add support to insns allowing index
7991(define-pmacro (indexb-sem mode d) (set SrcIndex d) (set DstIndex d))
7992(define-pmacro (indexbd-sem mode d) (set SrcIndex (const 0)) (set DstIndex d))
7993(define-pmacro (indexbs-sem mode d) (set SrcIndex d) (set DstIndex (const 0)))
7994(define-pmacro (indexw-sem mode d)
7995 (set SrcIndex (sll d (const 2))) (set DstIndex (sll d (const 2))))
7996(define-pmacro (indexwd-sem mode d)
7997 (set SrcIndex (const 0)) (set DstIndex (sll d (const 2))))
7998(define-pmacro (indexws-sem mode d)
7999 (set SrcIndex (sll d (const 2))) (set DstIndex (const 0)))
8000(define-pmacro (indexl-sem mode d)
8001 (set SrcIndex d) (set DstIndex (sll d (const 2))))
8002(define-pmacro (indexld-sem mode d)
8003 (set SrcIndex (const 0)) (set DstIndex (sll d (const 2))))
8004(define-pmacro (indexls-sem mode d)
8005 (set SrcIndex (sll d (const 2))) (set DstIndex (const 0)))
8006
eda87aba
DD		 8007; Note that "wbit" not where the size bit goes here, hence, it's
8008; always 0 in these calls but op2 differs instead.
8009
49f58d10
JB		 8010; indexb src (index byte)
8011(unary32-defn QI .b 0 indexb #x8 0 #x3 indexb-sem)
eda87aba 8012(unary32-defn HI .w 0 indexb #x8 1 #x3 indexb-sem)
49f58d10
JB		 8013; indexbd src (index byte dest)
8014(unary32-defn QI .b 0 indexbd #xA 0 3 indexbd-sem)
eda87aba 8015(unary32-defn HI .w 0 indexbd #xA 1 3 indexbd-sem)
49f58d10
JB		 8016; indexbs src (index byte src)
8017(unary32-defn QI .b 0 indexbs #xC 0 3 indexbs-sem)
eda87aba 8018(unary32-defn HI .w 0 indexbs #xC 1 3 indexbs-sem)
49f58d10
JB		 8019; indexl src (index long)
8020(unary32-defn QI .b 0 indexl 9 2 3 indexl-sem)
eda87aba 8021(unary32-defn HI .w 0 indexl 9 3 3 indexl-sem)
49f58d10
JB		 8022; indexld src (index long dest)
8023(unary32-defn QI .b 0 indexld #xB 2 3 indexld-sem)
eda87aba 8024(unary32-defn HI .w 0 indexld #xB 3 3 indexld-sem)
49f58d10
JB		 8025; indexls src (index long src)
8026(unary32-defn QI .b 0 indexls 9 0 3 indexls-sem)
eda87aba 8027(unary32-defn HI .w 0 indexls 9 1 3 indexls-sem)
49f58d10
JB		 8028; indexw src (index word)
8029(unary32-defn QI .b 0 indexw 8 2 3 indexw-sem)
eda87aba 8030(unary32-defn HI .w 0 indexw 8 3 3 indexw-sem)
49f58d10
JB		 8031; indexwd src (index word dest)
8032(unary32-defn QI .b 0 indexwd #xA 2 3 indexwd-sem)
eda87aba 8033(unary32-defn HI .w 0 indexwd #xA 3 3 indexwd-sem)
49f58d10
JB		 8034; indexws (index word src)
8035(unary32-defn QI .b 0 indexws #xC 2 3 indexws-sem)
eda87aba 8036(unary32-defn HI .w 0 indexws #xC 3 3 indexws-sem)
49f58d10
JB		 8037
8038;-------------------------------------------------------------
8039; jcc - jump on condition
8040;-------------------------------------------------------------
8041
8042(define-pmacro (jcnd32-sem cnd label)
8043 (sequence ()
8044 (case DFLT cnd
8045 ((#x00) (if (not cbit) (set pc label))) ;ltu nc
8046 ((#x01) (if (not (and cbit (not zbit))) (set pc label))) ;leu
8047 ((#x02) (if (not zbit) (set pc label))) ;ne nz
8048 ((#x03) (if (not sbit) (set pc label))) ;pz
8049 ((#x04) (if (not obit) (set pc label))) ;no
8050 ((#x05) (if (not (or zbit (xor sbit obit))) (set pc label))) ;gt
8051 ((#x06) (if (not (xor sbit obit)) (set pc label))) ;ge
8052 ((#x08) (if (trunc BI cbit) (set pc label))) ;geu c
8053 ((#x09) (if (and cbit (not zbit)) (set pc label))) ;gtu
8054 ((#x0a) (if (trunc BI zbit) (set pc label))) ;eq z
8055 ((#x0b) (if (trunc BI sbit) (set pc label))) ;n
8056 ((#x0c) (if (trunc BI obit) (set pc label))) ;o
8057 ((#x0d) (if (or zbit (xor sbit obit)) (set pc label))) ;le
8058 ((#x0e) (if (xor sbit obit) (set pc label))) ;lt
8059 )
8060 )
8061 )
8062
8063(define-pmacro (jcnd16-sem cnd label)
8064 (sequence ()
8065 (case DFLT cnd
8066 ((#x00) (if (trunc BI cbit) (set pc label))) ;geu c
8067 ((#x01) (if (and cbit (not zbit)) (set pc label))) ;gtu
8068 ((#x02) (if (trunc BI zbit) (set pc label))) ;eq z
8069 ((#x03) (if (trunc BI sbit) (set pc label))) ;n
8070 ((#x04) (if (not cbit) (set pc label))) ;ltu nc
8071 ((#x05) (if (not (and cbit (not zbit))) (set pc label))) ;leu
8072 ((#x06) (if (not zbit) (set pc label))) ;ne nz
8073 ((#x07) (if (not sbit) (set pc label))) ;pz
8074 ((#x08) (if (or zbit (xor sbit obit)) (set pc label))) ;le
8075 ((#x09) (if (trunc BI obit) (set pc label))) ;o
8076 ((#x0a) (if (not (xor sbit obit)) (set pc label))) ;ge
8077 ((#x0c) (if (not (or zbit (xor sbit obit))) (set pc label))) ;gt
8078 ((#x0d) (if (not obit) (set pc label))) ;no
8079 ((#x0e) (if (xor sbit obit) (set pc label))) ;lt
8080 )
8081 )
8082 )
8083
8084(dni jcnd16-5
8085 "jCnd label"
6772dd07 8086 (RL_JUMP RELAXABLE (machine 16))
49f58d10
JB		 8087 "j$cond16j5 ${Lab-8-8}"
8088 (+ (f-0-4 #x6) (f-4-1 1) cond16j5 Lab-8-8)
8089 (jcnd16-sem cond16j5 Lab-8-8)
8090 ()
8091)
8092
8093(dni jcnd16
8094 "jCnd label"
6772dd07 8095 (RL_JUMP RELAXABLE (machine 16))
49f58d10
JB		 8096 "j$cond16j ${Lab-16-8}"
8097 (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xC) cond16j Lab-16-8)
8098 (jcnd16-sem cond16j Lab-16-8)
8099 ()
8100)
8101
8102(dni jcnd32
8103 "jCnd label"
6772dd07 8104 (RL_JUMP RELAXABLE (machine 32))
49f58d10
JB		 8105 "j$cond32j ${Lab-8-8}"
8106 (+ (f-0-1 1) (f-4-3 5) cond32j Lab-8-8)
8107 (jcnd32-sem cond32j Lab-8-8)
8108 ()
8109)
8110
8111;-------------------------------------------------------------
8112; jmp - jump
8113;-------------------------------------------------------------
8114
8115; jmp.s label3 (m16 #1)
6772dd07 8116(dni jmp16.s "jmp.s Lab-5-3" (RL_JUMP RELAXABLE (machine 16))
49f58d10
JB		 8117 ("jmp.s ${Lab-5-3}")
8118 (+ (f-0-4 6) (f-4-1 0) Lab-5-3)
8119 (sequence () (set pc Lab-5-3))
8120 ())
8121; jmp.b label8 (m16 #2)
6772dd07 8122(dni jmp16.b "jmp.b Lab-8-8" (RL_JUMP RELAXABLE (machine 16))
49f58d10
JB		 8123 ("jmp.b ${Lab-8-8}")
8124 (+ (f-0-4 #xF) (f-4-4 #xE) Lab-8-8)
8125 (sequence () (set pc Lab-8-8))
8126 ())
8127; jmp.w label16 (m16 #3)
6772dd07 8128(dni jmp16.w "jmp.w Lab-8-16" (RL_JUMP RELAXABLE (machine 16))
49f58d10
JB		 8129 ("jmp.w ${Lab-8-16}")
8130 (+ (f-0-4 #xF) (f-4-4 4) Lab-8-16)
8131 (sequence () (set pc Lab-8-16))
8132 ())
8133; jmp.a label24 (m16 #4)
6772dd07 8134(dni jmp16.a "jmp.a Lab-8-24" (RL_JUMP RELAXABLE (machine 16))
49f58d10
JB		 8135 ("jmp.a ${Lab-8-24}")
8136 (+ (f-0-4 #xF) (f-4-4 #xC) Lab-8-24)
8137 (sequence () (set pc Lab-8-24))
8138 ())
8139
8140(define-pmacro (jmp16-sem mode dst)
8141 (set pc (and dst #xfffff))
8142)
8143(define-pmacro (jmp32-sem mode dst)
8144 (set pc dst)
8145)
8146; jmpi.w dst (m16 #1 m32 #2)
8147(unary-insn-defn 16 16 HI .w jmpi (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 2) dst16-16-HI) jmp16-sem)
8148(unary-insn-defn 32 16-Unprefixed HI .w jmpi (+ (f-0-4 #xC) (f-7-1 1) dst32-16-Unprefixed-HI (f-10-2 #x0) (f-12-4 #xF)) jmp32-sem)
8149; jmpi.a dst (m16 #2 m32 #2)
8150(unary-insn-defn 16 16 SI .a jmpi (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 0) dst16-16-SI) jmp16-sem)
8151(unary-insn-defn 32 16-Unprefixed SI .a jmpi (+ (f-0-4 #x8) (f-7-1 0) dst32-16-Unprefixed-SI (f-10-2 #x0) (f-12-4 1)) jmp32-sem)
8152; jmps imm8 (m16 #1)
8153(dni jmps16 "jmps Imm-8-QI" ((machine 16))
8154 ("jmps #${Imm-8-QI}")
8155 (+ (f-0-4 #xE) (f-4-4 #xE) Imm-8-QI)
8156 (sequence () (set pc Imm-8-QI))
8157 ())
8158; jmp.s label3 (m32 #1)
8159(dni jmp32.s
8160 "jmp.s label"
6772dd07 8161 (RL_JUMP RELAXABLE (machine 32))
49f58d10
JB		 8162 "jmp.s ${Lab32-jmp-s}"
8163 (+ (f-0-2 1) (f-4-3 5) Lab32-jmp-s)
8164 (set pc Lab32-jmp-s)
8165 ()
8166)
8167; jmp.b label8 (m32 #2)
6772dd07 8168(dni jmp32.b "jmp.b Lab-8-8" (RL_JUMP RELAXABLE (machine 32))
49f58d10
JB		 8169 ("jmp.b ${Lab-8-8}")
8170 (+ (f-0-4 #xB) (f-4-4 #xB) Lab-8-8)
8171 (set pc Lab-8-8)
8172 ())
8173; jmp.w label16 (m32 #3)
6772dd07 8174(dni jmp32.w "jmp.w Lab-8-16" (RL_JUMP RELAXABLE (machine 32))
49f58d10
JB		 8175 ("jmp.w ${Lab-8-16}")
8176 (+ (f-0-4 #xC) (f-4-4 #xE) Lab-8-16)
8177 (set pc Lab-8-16)
8178 ())
8179; jmp.a label24 (m32 #4)
6772dd07 8180(dni jmp32.a "jmp.a Lab-8-24" (RL_JUMP RELAXABLE (machine 32))
49f58d10
JB		 8181 ("jmp.a ${Lab-8-24}")
8182 (+ (f-0-4 #xC) (f-4-4 #xC) Lab-8-24)
8183 (set pc Lab-8-24)
8184 ())
8185; jmp.s imm8 (m32 #1)
6772dd07 8186(dni jmps32 "jmps Imm-8-QI" (RL_JUMP (machine 32))
49f58d10
JB		 8187 ("jmps #${Imm-8-QI}")
8188 (+ (f-0-4 #xD) (f-4-4 #xC) Imm-8-QI)
8189 (set pc Imm-8-QI)
8190 ())
8191
8192;-------------------------------------------------------------
8193; jsr jump subroutine
8194;-------------------------------------------------------------
8195
8196(define-pmacro (jsr16-sem length dst)
8197 (sequence ((SI tpc))
8198 (set tpc (add pc length))
8199 (set (reg h-sp) (sub (reg h-sp) 2))
8200 (set (mem16 HI (reg h-sp)) (srl (and tpc #xffff00) 8))
8201 (set (reg h-sp) (sub (reg h-sp) 1))
8202 (set (mem16 QI (reg h-sp)) (and tpc #xff))
8203 (set pc dst)
8204 )
8205)
8206(define-pmacro (jsr32-sem length dst)
8207 (sequence ((SI tpc))
8208 (set tpc (add pc length))
8209 (set (reg h-sp) (sub (reg h-sp) 2))
8210 (set (mem32 HI (reg h-sp)) (srl (and tpc #xffff0000) 16))
8211 (set (reg h-sp) (sub (reg h-sp) 2))
8212 (set (mem32 HI (reg h-sp)) (and tpc #xffff))
8213 (set pc dst)
8214 )
8215)
8216
8217; jsr.w label16 (m16 #1)
6772dd07 8218(dni jsr16.w "jsr.w Lab-8-16" (RL_JUMP RELAXABLE (machine 16))
49f58d10
JB		 8219 ("jsr.w ${Lab-8-16}")
8220 (+ (f-0-4 #xF) (f-4-4 5) Lab-8-16)
8221 (jsr16-sem 3 Lab-8-16)
8222 ())
8223; jsr.a label24 (m16 #2)
6772dd07 8224(dni jsr16.a "jsr.a Lab-8-24" (RL_JUMP RELAXABLE (machine 16))
49f58d10
JB		 8225 ("jsr.a ${Lab-8-24}")
8226 (+ (f-0-4 #xF) (f-4-4 #xD) Lab-8-24)
8227 (jsr16-sem 4 Lab-8-24)
8228 ())
8229(define-pmacro (jsri-defn mode op16 op16-1 op16-2 op16-3 op16-sem
8230 op32 op32-1 op32-2 op32-3 op32-4 op32-sem len)
8231 (begin
8232 (dni (.sym jsri16 mode - op16)
8233 (.str "jsri." mode " " op16)
6772dd07 8234 (RL_1ADDR (machine 16))
49f58d10
JB		 8235 (.str "jsri." mode " ${" op16 "}")
8236 (+ op16-1 op16-2 op16-3 op16)
8237 (op16-sem len op16)
8238 ())
8239 (dni (.sym jsri32 mode - op32)
8240 (.str "jsri." mode " " op32)
6772dd07 8241 (RL_1ADDR (machine 32))
49f58d10
JB		 8242 (.str "jsri." mode " ${" op32 "}")
8243 (+ op32-1 op32-2 op32-3 op32-4 op32)
8244 (op32-sem len op32)
8245 ())
8246 )
8247 )
8248; jsri.w dst (m16 #1 m32 #1))
49f58d10
JB		 8249(jsri-defn w dst16-16-8-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem
8250 dst32-16-8-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 3)
8251(jsri-defn w dst16-16-16-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem
8252 dst32-16-16-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 4)
eda87aba
DD		 8253(jsri-defn w dst16-basic-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem
8254 dst32-basic-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 2)
6772dd07 8255(dni jsri32.w "jsr.w dst32-16-24-Unprefixed-HI" (RL_1ADDR (machine 32))
49f58d10
JB		 8256 ("jsri.w ${dst32-16-24-Unprefixed-HI}")
8257 (+ (f-0-4 #xC) (f-7-1 1) dst32-16-24-Unprefixed-HI (f-10-2 #x1) (f-12-4 #xF))
8258 (jsr32-sem 6 dst32-16-24-Unprefixed-HI)
8259 ())
8260
8261; jsri.a (m16 #2 m32 #2)
49f58d10
JB		 8262(jsri-defn a dst16-16-8-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem
8263 dst32-16-8-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 3)
8264(jsri-defn a dst16-16-16-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem
8265 dst32-16-16-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 4)
eda87aba
DD		 8266(jsri-defn a dst16-basic-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem
8267 dst32-basic-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 2)
8268
6772dd07 8269(dni jsri32.a "jsr.w dst32-16-24-Unprefixed-HI" (RL_1ADDR (machine 32))
49f58d10
JB		 8270 ("jsri.w ${dst32-16-24-Unprefixed-SI}")
8271 (+ (f-0-4 #x9) (f-7-1 0) dst32-16-24-Unprefixed-SI (f-10-2 #x0) (f-12-4 #x1))
8272 (jsr32-sem 6 dst32-16-24-Unprefixed-SI)
8273 ())
8274; jsr.w label16 (m32 #1)
6772dd07 8275(dni jsr32.w "jsr.w label" (RL_JUMP RELAXABLE (machine 32))
49f58d10
JB		 8276 ("jsr.w ${Lab-8-16}")
8277 (+ (f-0-4 #xC) (f-4-4 #xF) Lab-8-16)
8278 (jsr32-sem 3 Lab-8-16)
8279 ())
8280; jsr.a label16 (m32 #2)
6772dd07 8281(dni jsr32.a "jsr.a label" (RL_JUMP (machine 32))
49f58d10
JB		 8282 ("jsr.a ${Lab-8-24}")
8283 (+ (f-0-4 #xC) (f-4-4 #xD) Lab-8-24)
8284 (jsr32-sem 4 Lab-8-24)
8285 ())
8286; jsrs imm8 (m16 #1)
8287(dni jsrs16 "jsrs Imm-8-QI" ((machine 16))
8288 ("jsrs #${Imm-8-QI}")
8289 (+ (f-0-4 #xE) (f-4-4 #xF) Imm-8-QI)
8290 (jsr16-sem 2 Imm-8-QI)
8291 ())
8292; jsrs imm8 (m32 #1)
8293(dni jsrs "jsrs #Imm-8-QI" ((machine 32))
8294 ("jsrs #${Imm-8-QI}")
8295 (+ (f-0-4 #xD) (f-4-4 #xD) Imm-8-QI)
8296 (jsr32-sem 2 Imm-8-QI)
8297 ())
8298
8299;-------------------------------------------------------------
8300; ldc - load control register
8301; stc - store control register
8302;-------------------------------------------------------------
8303
8304(define-pmacro (ldc32-cr1-sem src dst)
8305 (sequence ()
8306 (case DFLT dst
8307 ((#x0) (set (reg h-dct0) src))
8308 ((#x1) (set (reg h-dct1) src))
8309 ((#x2) (sequence ((HI tflag))
8310 (set tflag src)
8311 (if (and tflag #x1) (set cbit 1))
8312 (if (and tflag #x2) (set dbit 1))
8313 (if (and tflag #x4) (set zbit 1))
8314 (if (and tflag #x8) (set sbit 1))
8315 (if (and tflag #x10) (set bbit 1))
8316 (if (and tflag #x20) (set obit 1))
8317 (if (and tflag #x40) (set ibit 1))
8318 (if (and tflag #x80) (set ubit 1))))
8319 ((#x3) (set (reg h-svf) src))
8320 ((#x4) (set (reg h-drc0) src))
8321 ((#x5) (set (reg h-drc1) src))
8322 ((#x6) (set (reg h-dmd0) src))
8323 ((#x7) (set (reg h-dmd1) src))
8324 )
8325 )
8326)
8327(define-pmacro (ldc32-cr2-sem src dst)
8328 (sequence ()
8329 (case DFLT dst
8330 ((#x0) (set (reg h-intb) src))
8331 ((#x1) (set (reg h-sp) src))
8332 ((#x2) (set (reg h-sb) src))
8333 ((#x3) (set (reg h-fb) src))
8334 ((#x4) (set (reg h-svp) src))
8335 ((#x5) (set (reg h-vct) src))
8336 ((#x7) (set (reg h-isp) src))
8337 )
8338 )
8339)
8340(define-pmacro (ldc32-cr3-sem src dst)
8341 (sequence ()
8342 (case DFLT dst
8343 ((#x2) (set (reg h-dma0) src))
8344 ((#x3) (set (reg h-dma1) src))
8345 ((#x4) (set (reg h-dra0) src))
8346 ((#x5) (set (reg h-dra1) src))
8347 ((#x6) (set (reg h-dsa0) src))
8348 ((#x7) (set (reg h-dsa1) src))
8349 )
8350 )
8351)
8352(define-pmacro (ldc16-sem src dst)
8353 (sequence ()
8354 (case DFLT dst
8355 ((#x1) (set (reg h-intb) src))
8356 ((#x2) (set (reg h-intb) (or (reg h-intb) (sll src (const 16)))))
8357 ((#x3) (sequence ((HI tflag))
8358 (set tflag src)
8359 (if (and tflag #x1) (set cbit 1))
8360 (if (and tflag #x2) (set dbit 1))
8361 (if (and tflag #x4) (set zbit 1))
8362 (if (and tflag #x8) (set sbit 1))
8363 (if (and tflag #x10) (set bbit 1))
8364 (if (and tflag #x20) (set obit 1))
8365 (if (and tflag #x40) (set ibit 1))
8366 (if (and tflag #x80) (set ubit 1))))
8367 ((#x4) (set (reg h-isp) src))
8368 ((#x5) (set (reg h-sp) src))
8369 ((#x6) (set (reg h-sb) src))
8370 ((#x7) (set (reg h-fb) src))
8371 )
8372 )
8373)
8374
8375(define-pmacro (stc32-cr1-sem src dst)
8376 (sequence ()
8377 (case DFLT src
8378 ((#x0) (set dst (reg h-dct0)))
8379 ((#x1) (set dst (reg h-dct1)))
8380 ((#x2) (sequence ((HI tflag))
8381 (set tflag 0)
8382 (if (eq cbit 1) (set tflag (or tflag #x1)))
8383 (if (eq dbit 1) (set tflag (or tflag #x2)))
8384 (if (eq zbit 1) (set tflag (or tflag #x4)))
8385 (if (eq sbit 1) (set tflag (or tflag #x8)))
8386 (if (eq bbit 1) (set tflag (or tflag #x10)))
8387 (if (eq obit 1) (set tflag (or tflag #x20)))
8388 (if (eq ibit 1) (set tflag (or tflag #x40)))
8389 (if (eq ubit 1) (set tflag (or tflag #x80)))
8390 (set dst tflag)))
8391 ((#x3) (set dst (reg h-svf)))
8392 ((#x4) (set dst (reg h-drc0)))
8393 ((#x5) (set dst (reg h-drc1)))
8394 ((#x6) (set dst (reg h-dmd0)))
8395 ((#x7) (set dst (reg h-dmd1)))
8396 )
8397 )
8398)
8399(define-pmacro (stc32-cr2-sem src dst)
8400 (sequence ()
8401 (case DFLT src
8402 ((#x0) (set dst (reg h-intb)))
8403 ((#x1) (set dst (reg h-sp)))
8404 ((#x2) (set dst (reg h-sb)))
8405 ((#x3) (set dst (reg h-fb)))
8406 ((#x4) (set dst (reg h-svp)))
8407 ((#x5) (set dst (reg h-vct)))
8408 ((#x7) (set dst (reg h-isp)))
8409 )
8410 )
8411)
8412(define-pmacro (stc32-cr3-sem src dst)
8413 (sequence ()
8414 (case DFLT src
8415 ((#x2) (set dst (reg h-dma0)))
8416 ((#x3) (set dst (reg h-dma1)))
8417 ((#x4) (set dst (reg h-dra0)))
8418 ((#x5) (set dst (reg h-dra1)))
8419 ((#x6) (set dst (reg h-dsa0)))
8420 ((#x7) (set dst (reg h-dsa1)))
8421 )
8422 )
8423)
8424(define-pmacro (stc16-sem src dst)
8425 (sequence ()
8426 (case DFLT src
8427 ((#x1) (set dst (and (reg h-intb) (const #xffff))))
8428 ((#x2) (set dst (srl (reg h-intb) (const 16))))
8429 ((#x3) (sequence ((HI tflag))
8430 (set tflag 0)
8431 (if (eq cbit 1) (set tflag (or tflag #x1)))
8432 (if (eq dbit 1) (set tflag (or tflag #x2)))
8433 (if (eq zbit 1) (set tflag (or tflag #x4)))
8434 (if (eq sbit 1) (set tflag (or tflag #x8)))
8435 (if (eq bbit 1) (set tflag (or tflag #x10)))
8436 (if (eq obit 1) (set tflag (or tflag #x20)))
8437 (if (eq ibit 1) (set tflag (or tflag #x40)))
8438 (if (eq ubit 1) (set tflag (or tflag #x80)))
8439 (set dst tflag)))
8440 ((#x4) (set dst (reg h-isp)))
8441 ((#x5) (set dst (reg h-sp)))
8442 ((#x6) (set dst (reg h-sb)))
8443 ((#x7) (set dst (reg h-fb)))
8444 )
8445 )
8446)
8447
8448(dni ldc16.imm16 "ldc #imm,dst" ((machine 16))
8449 ("ldc #${Imm-16-HI},${cr16}")
8450 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) (f-12-4 0) cr16 Imm-16-HI)
8451 (ldc16-sem Imm-16-HI cr16)
8452 ())
8453
8454(dni ldc16.dst "ldc src,dest" ((machine 16))
8455 ("ldc ${dst16-16-HI},${cr16}")
8456 (+ (f-0-4 7) (f-4-4 #xA) (f-8-1 1) cr16 dst16-16-HI)
8457 (ldc16-sem dst16-16-HI cr16)
8458 ())
8459; ldc src,dest (m32c #4)
8460(dni ldc32.src-cr1 "ldc src,dst" ((machine 32))
8461 ("ldc ${dst32-24-Prefixed-HI},${cr1-Prefixed-32}")
8462 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-HI (f-15-1 1) (f-18-2 0) (f-20-1 1) cr1-Prefixed-32)
8463 (ldc32-cr1-sem dst32-24-Prefixed-HI cr1-Prefixed-32)
8464 ())
8465; ldc src,dest (m32c #5)
8466(dni ldc32.src-cr2 "ldc src,dest" ((machine 32))
8467 ("ldc ${dst32-16-Unprefixed-SI},${cr2-32}")
8468 (+ (f-0-4 #xD) dst32-16-Unprefixed-SI (f-7-1 1) (f-10-2 0) (f-12-1 0) cr2-32)
8469 (ldc32-cr2-sem dst32-16-Unprefixed-SI cr2-32)
8470 ())
8471; ldc src,dest (m32c #6)
8472(dni ldc32.src-cr3 "ldc src,dst" ((machine 32))
8473 ("ldc ${dst32-24-Prefixed-SI},${cr3-Prefixed-32}")
8474 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-SI (f-15-1 1) (f-18-2 0) (f-20-1 0) cr3-Prefixed-32)
8475 (ldc32-cr3-sem dst32-24-Prefixed-SI cr3-Prefixed-32)
8476 ())
8477; ldc src,dest (m32c #1)
8478(dni ldc32.imm16-cr1 "ldc #imm,dst" ((machine 32))
8479 ("ldc #${Imm-16-HI},${cr1-Unprefixed-32}")
8480 (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 #xA) (f-12-1 1) cr1-Unprefixed-32 Imm-16-HI)
8481 (ldc32-cr1-sem Imm-16-HI cr1-Unprefixed-32)
8482 ())
8483; ldc src,dest (m32c #2)
8484(dni ldc32.imm16-cr2 "ldc #imm,dst" ((machine 32))
8485 ("ldc #${Dsp-16-u24},${cr2-32}")
8486 (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 2) (f-12-1 1) cr2-32 Dsp-16-u24)
8487 (ldc32-cr2-sem Dsp-16-u24 cr2-32)
8488 ())
8489; ldc src,dest (m32c #3)
8490(dni ldc32.imm16-cr3 "ldc #imm,dst" ((machine 32))
8491 ("ldc #${Dsp-16-u24},${cr3-Unprefixed-32}")
8492 (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 6) (f-12-1 1) cr3-Unprefixed-32 Dsp-16-u24)
8493 (ldc32-cr3-sem Dsp-16-u24 cr3-Unprefixed-32)
8494 ())
8495
8496(dni stc16.src "stc src,dest" ((machine 16))
8497 ("stc ${cr16},${dst16-16-HI}")
8498 (+ (f-0-4 7) (f-4-4 #xB) (f-8-1 1) cr16 dst16-16-HI)
8499 (stc16-sem cr16 dst16-16-HI )
8500 ())
8501
8502(dni stc16.pc "stc pc,dest" ((machine 16))
8503 ("stc pc,${dst16-16-HI}")
8504 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xC) dst16-16-HI)
8505 (sequence () (set dst16-16-HI (reg h-pc)))
8506 ())
8507
8508(dni stc32.src-cr1 "stc src,dst" ((machine 32))
8509 ("stc ${cr1-Prefixed-32},${dst32-24-Prefixed-HI}")
8510 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-HI (f-15-1 1) (f-18-2 1) (f-20-1 1) cr1-Prefixed-32)
8511 (stc32-cr1-sem cr1-Prefixed-32 dst32-24-Prefixed-HI )
8512 ())
8513
8514(dni stc32.src-cr2 "stc src,dest" ((machine 32))
8515 ("stc ${cr2-32},${dst32-16-Unprefixed-SI}")
8516 (+ (f-0-4 #xD) dst32-16-Unprefixed-SI (f-7-1 1) (f-10-2 0) (f-12-1 2) cr2-32)
8517 (stc32-cr2-sem cr2-32 dst32-16-Unprefixed-SI )
8518 ())
8519
8520(dni stc32.src-cr3 "stc src,dst" ((machine 32))
8521 ("stc ${cr3-Prefixed-32},${dst32-24-Prefixed-SI}")
8522 (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-SI (f-15-1 1) (f-18-2 1) (f-20-1 0) cr3-Prefixed-32)
8523 (stc32-cr3-sem cr3-Prefixed-32 dst32-24-Prefixed-SI )
8524 ())
8525
8526;-------------------------------------------------------------
8527; ldctx - load context
8528; stctx - store context
8529;-------------------------------------------------------------
8530
8531; ??? semantics
8532(dni ldctx16 "ldctx abs16,abs24" ((machine 16))
8533 ("ldctx ${Dsp-16-u16},${Dsp-32-u24}")
8534 (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 #x0) Dsp-16-u16 Dsp-32-u24)
8535 (nop)
8536 ())
8537(dni ldctx32 "ldctx abs16,abs24" ((machine 32))
8538 ("ldctx ${Dsp-16-u16},${Dsp-32-u24}")
8539 (+ (f-0-4 #xB) (f-4-4 #x6) (f-8-4 #xC) (f-12-4 #x3) Dsp-16-u16 Dsp-32-u24)
8540 (nop)
8541 ())
8542(dni stctx16 "stctx abs16,abs24" ((machine 16))
8543 ("stctx ${Dsp-16-u16},${Dsp-32-u24}")
8544 (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 #x0) Dsp-16-u16 Dsp-32-u24)
8545 (nop)
8546 ())
8547(dni stctx32 "stctx abs16,abs24" ((machine 32))
8548 ("stctx ${Dsp-16-u16},${Dsp-32-u24}")
8549 (+ (f-0-4 #xB) (f-4-4 #x6) (f-8-4 #xD) (f-12-4 #x3) Dsp-16-u16 Dsp-32-u24)
8550 (nop)
8551 ())
8552
8553;-------------------------------------------------------------
8554; lde - load from extra far data area (m16)
8555; ste - store to extra far data area (m16)
8556;-------------------------------------------------------------
8557
a1a280bb
DD		 8558(lde-dst QI .b 0)
8559(lde-dst HI .w 1)
49f58d10 8560
a1a280bb
DD		 8561(ste-dst QI .b 0)
8562(ste-dst HI .w 1)
49f58d10
JB		 8563
8564;-------------------------------------------------------------
8565; ldipl - load interrupt permission level
8566;-------------------------------------------------------------
8567
8568; ??? semantics
8569; ldintb <==> ldc #imm,intbh ; ldc #imm,intbl
8d0e2679 8570
49f58d10
JB		 8571(dni ldipl16.imm "ldipl #imm" ((machine 16))
8572 ("ldipl #${Imm-13-u3}")
8573 (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xA) (f-12-1 0) Imm-13-u3)
8574 (nop)
8575 ())
8576(dni ldipl32.imm "ldipl #imm" ((machine 32))
8577 ("ldipl #${Imm-13-u3}")
8578 (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 #xE) (f-12-1 1) Imm-13-u3)
8579 (nop)
8580 ())
8581
8582
8583;-------------------------------------------------------------
8584; max - maximum value
8585;-------------------------------------------------------------
8586
8587; TODO check semantics for min -1,0
8588(define-pmacro (max-sem mode src dst)
8589 (sequence ()
8590 (if (gt mode src dst)
8591 (set mode dst src)))
8592)
8593
8594; max.size:G #imm,dst
8595(binary-arith32-imm-dst-Prefixed QI QI .b 0 max X #x8 #x3 #xF max-sem)
8596(binary-arith32-imm-dst-Prefixed HI HI .w 1 max X #x8 #x3 #xF max-sem)
8597
8598; max.BW:G src,dst
8599(binary-arith32-src-dst-Prefixed QI QI .b 0 max X #x1 #xD max-sem)
8600(binary-arith32-src-dst-Prefixed HI HI .w 1 max X #x1 #xD max-sem)
8601
8602;-------------------------------------------------------------
8603; min - minimum value
8604;-------------------------------------------------------------
8605
8606(define-pmacro (min-sem mode src dst)
8607 (sequence ()
8608 (if (lt mode src dst)
8609 (set mode dst src)))
8610)
8611
8612; min.size:G #imm,dst
8613(binary-arith32-imm-dst-Prefixed QI QI .b 0 min X #x8 #x2 #xF min-sem)
8614(binary-arith32-imm-dst-Prefixed HI HI .w 1 min X #x8 #x2 #xF min-sem)
8615
8616; min.BW:G src,dst
8617(binary-arith32-src-dst-Prefixed QI QI .b 0 min X #x1 #xC min-sem)
8618(binary-arith32-src-dst-Prefixed HI HI .w 1 min X #x1 #xC min-sem)
8619
8620;-------------------------------------------------------------
8621; mov - move
8622;-------------------------------------------------------------
8623
8624(define-pmacro (mov-sem mode src1 dst)
8625 (sequence ((mode result))
8626 (set result src1)
8627 (set-z-and-s result)
8628 (set mode dst src1))
8629)
8630
8631(define-pmacro (mov-dspsp-dst-sem mach mode src1 dst)
8632 (set dst (mem-mach mach mode (add sp src1)))
8633)
8634
8635(define-pmacro (mov-src-dspsp-sem mach mode src dst1)
8636 (set (mem-mach mach mode (add sp dst1)) src)
8637)
8638
8639(define-pmacro (mov16-imm-an-defn size mode imm regn op1 op2)
8640 (dni (.sym mov16. size .S-imm- regn)
8641 (.str "mov." size ":S " imm "," regn)
8642 ((machine 16))
8643 (.str "mov." size "$S #${" imm "}," regn)
8644 (+ op1 op2 imm)
8645 (mov-sem mode imm (reg (.sym h- regn)))
8646 ())
8647)
8648; mov.size:G #imm,dst (m16 #1 m32 #1)
8649(binary-arith-imm-dst mov G (f-0-4 7) (f-4-3 2) (f-8-4 #xC) #x9 #x2 #xF mov-sem)
8650; mov.L:G #imm32,dst (m32 #2)
8651(binary-arith32-imm-dst-defn SI SI .l 0 mov G #xB #x3 #x1 mov-sem)
49f58d10
JB		 8652; mov.BW:S #imm,dst2 (m32 #4)
8653(binary-arith32-s-imm-dst QI .b 0 mov #x0 #x2 mov-sem)
8654(binary-arith32-s-imm-dst HI .w 1 mov #x0 #x2 mov-sem)
8655; mov.b:S #imm8,dst3 (m16 #3)
8656(binary-arith16-b-S-imm8-dst3 mov ".b" (f-0-4 #xC) (f-4-1 0) mov-sem)
8657; mov.b:S #imm8,aN (m16 #4)
8658(mov16-imm-an-defn b QI Imm-8-QI a0 (f-0-4 #xE) (f-4-4 2))
8659(mov16-imm-an-defn b QI Imm-8-QI a1 (f-0-4 #xE) (f-4-4 #xA))
8660(mov16-imm-an-defn w HI Imm-8-HI a0 (f-0-4 #xA) (f-4-4 2))
8661(mov16-imm-an-defn w HI Imm-8-HI a1 (f-0-4 #xA) (f-4-4 #xA))
8662; mov.WL:S #imm,A0/A1 (m32 #5)
8663(define-pmacro (mov32-wl-s-defn mode sz op1 imm regn op2)
8664 (dni (.sym mov32- sz - regn)
8665 (.str "mov." sz ":s" imm "," regn)
8666 ((machine 32))
8667 (.str "mov." sz "$S #${" imm "}," regn)
8668 (+ (f-0-4 op1) (f-4-4 op2) imm)
8669 (mov-sem mode imm (reg (.sym h- regn)))
8670 ())
8671)
8672(mov32-wl-s-defn HI w #x9 Imm-8-HI a0 #xC)
8673(mov32-wl-s-defn HI w #x9 Imm-8-HI a1 #xD)
f75eb1c0
DD		 8674(mov32-wl-s-defn SI l #xB Dsp-8-s24 a0 #xC)
8675(mov32-wl-s-defn SI l #xB Dsp-8-s24 a1 #xD)
e729279b
NC		 8676
8677; mov.size:Q #imm4,dst (m16 #2 m32 #3)
8678(binary-arith16-imm4-dst-defn QI .b 0 0 mov (f-0-4 #xD) (f-4-3 4) mov-sem)
458f7770 8679(binary-arith16-imm4-dst-defn HI .w 0 1 mov (f-0-4 #xD) (f-4-3 4) mov-sem)
e729279b
NC		 8680(binary-arith32-imm4-dst-defn QI .b 1 0 mov #x7 #x2 mov-sem)
8681(binary-arith32-imm4-dst-defn HI .w 1 1 mov #x7 #x2 mov-sem)
49f58d10
JB		 8682
8683; mov.BW:Z #0,dst (m16 #5 m32 #6)
8684(dni mov16.b-Z-imm8-dst3
8685 "mov.b:Z #0,Dst16-3-S-8"
8686 ((machine 16))
8687 "mov.b$Z #0,${Dst16-3-S-8}"
8688 (+ (f-0-4 #xB) (f-4-1 #x0) Dst16-3-S-8)
8689 (mov-sem QI (const 0) Dst16-3-S-8)
8690 ())
8691; (binary-arith16-b-Z-imm8-dst3 mov ".b" (f-0-4 #xB) (f-4-1 0) mov-sem)
8692(binary-arith32-z-imm-dst QI .b 0 mov #x0 #x1 mov-sem)
8693(binary-arith32-z-imm-dst HI .w 1 mov #x0 #x1 mov-sem)
8694; mov.BW:G src,dst (m16 #6 m32 #7)
8695(binary-arith-src-dst mov G (f-0-4 #x7) (f-4-3 1) #x1 #xB mov-sem)
8696; mov.B:S src2,a0/a1 (m16 #7)
8697(dni (.sym mov 16 .b.S-An)
8698 (.str mov ".b:S src2,a[01]")
8699 ((machine 16))
8700 (.str mov ".b$S ${src16-2-S},${Dst16AnQI-S}")
8701 (+ (f-0-4 #x3) (f-4-1 0) Dst16AnQI-S src16-2-S)
8702 (mov-sem QI src16-2-S Dst16AnQI-S)
8703 ())
8704(define-pmacro (mov16-b-s-an-defn op1 op2 op2c)
8705 (dni (.sym mov16.b.S- op1 - op2)
8706 (.str mov ".b:S " op1 "," op2)
8707 ((machine 16))
8708 (.str mov ".b$S " op1 "," op2)
8709 (+ (f-0-4 #x3) op2c)
8710 (mov-sem QI (reg (.sym h- op1)) (reg (.sym h- op2)))
8711 ())
8712 )
8713(mov16-b-s-an-defn r0l a1 (f-4-4 #x4))
8714(mov16-b-s-an-defn r0h a0 (f-4-4 #x0))
8715
8716; mov.L:G src,dst (m32 #8)
8717(binary-arith32-src-dst-defn SI SI .l 1 mov G #x1 #x3 mov-sem)
8718; mov.B:S r0l/r0h,dst2 (m16 #8)
8719(dni (.sym mov 16 .b.S-Rn-An)
8720 (.str mov ".b:S r0[lh],src2")
8721 ((machine 16))
8722 (.str mov ".b$S ${Dst16RnQI-S},${src16-2-S}")
8723 (+ (f-0-4 #x0) (f-4-1 0) Dst16RnQI-S src16-2-S)
8724 (mov-sem QI src16-2-S Dst16RnQI-S)
8725 ())
8726
8727; mov.B.S src2,r0l/r0h (m16 #9)
8728(binary-arith16-b-S-src2 mov (f-0-4 0) (f-4-1 1) mov-sem)
8729
8730; mov.BW:S src2,r0l/r0 (m32 #9)
8731; mov.BW:S src2,r1l/r1 (m32 #10)
8732(define-pmacro (mov32-src-r sz szcode mode src dst opc1 opc2)
8733 (begin
8734 (dni (.sym mov32. sz - src - dst)
8735 (.str "mov." sz "src," dst)
8736 ((machine 32))
8737 (.str "mov." sz "$S ${" (.sym src - mode) "}," dst)
8738 (+ (f-0-2 opc1) (.sym src - mode) (f-4-3 opc2) (f-7-1 szcode))
8739 (mov-sem mode (.sym src - mode) (reg (.sym h- dst)))
8740 ())
8741 )
8742 )
8743(mov32-src-r b 0 QI dst32-2-S-16 r0l 0 4)
8744(mov32-src-r w 1 HI dst32-2-S-16 r0 0 4)
8745(mov32-src-r b 0 QI dst32-2-S-8 r0l 0 4)
8746(mov32-src-r w 1 HI dst32-2-S-8 r0 0 4)
8747(mov32-src-r b 0 QI dst32-2-S-basic r1l 1 7)
f75eb1c0 8748(mov32-src-r w 1 HI dst32-2-S-basic r1 1 7)
49f58d10
JB		 8749(mov32-src-r b 0 QI dst32-2-S-16 r1l 1 7)
8750(mov32-src-r w 1 HI dst32-2-S-16 r1 1 7)
8751(mov32-src-r b 0 QI dst32-2-S-8 r1l 1 7)
8752(mov32-src-r w 1 HI dst32-2-S-8 r1 1 7)
8753
8754; mov.BW:S r0l/r0,dst2 (m32 #11)
8755(define-pmacro (mov32-r-dest sz szcode mode src dst opc1 opc2)
8756 (begin
8757 (dni (.sym mov32. sz - src - dst)
8758 (.str "mov." sz "src," dst)
8759 ((machine 32))
8760 (.str "mov." sz "$S " src ",${" (.sym dst - mode) "}")
8761 (+ (f-0-2 opc1) (.sym dst - mode) (f-4-3 opc2) (f-7-1 szcode))
8762 (mov-sem mode (reg (.sym h- src)) (.sym dst - mode))
8763 ())
8764 )
8765 )
8766(mov32-r-dest b 0 QI r0l dst32-2-S-16 0 0)
8767(mov32-r-dest w 1 HI r0 dst32-2-S-16 0 0)
8768(mov32-r-dest b 0 QI r0l dst32-2-S-8 0 0)
8769(mov32-r-dest w 1 HI r0 dst32-2-S-8 0 0)
8770
8771; mov.L:S src,A0/A1 (m32 #12)
8772(define-pmacro (mov32-src-a src dst dstcode opc1 opc2)
8773 (begin
8774 (dni (.sym mov32. sz - src - dst)
8775 (.str "mov." sz "src," dst)
8776 ((machine 32))
8777 (.str "mov.l" "$S ${" (.sym src - SI) "}," dst)
8778 (+ (f-0-2 opc1) (.sym src - SI) (f-4-3 opc2) (f-7-1 dstcode))
8779 (mov-sem SI (.sym src - SI) (reg (.sym h- dst)))
8780 ())
8781 )
8782 )
8783(mov32-src-a dst32-2-S-16 a0 0 1 4)
8784(mov32-src-a dst32-2-S-16 a1 1 1 4)
8785(mov32-src-a dst32-2-S-8 a0 0 1 4)
8786(mov32-src-a dst32-2-S-8 a1 1 1 4)
8787
8788; mov.BW:G dsp8[sp],dst (m16 #10 m32 #13)
8789; mov.BW:G src,dsp8[sp] (m16 #11 m32 #14)
8790(mov-dspsp-dst mov (f-0-4 #x7) (f-4-3 2) (f-8-4 #xB) #xB #x0 #xF mov-dspsp-dst-sem)
8791(mov-src-dspsp mov (f-0-4 #x7) (f-4-3 2) (f-8-4 #x3) #xA #x0 #xF mov-src-dspsp-sem)
8792
8793;-------------------------------------------------------------
8794; mova - move effective address
8795;-------------------------------------------------------------
8796
8797(define-pmacro (mov16a-defn dst dstop dstcode)
8798 (dni (.sym mova16. src - dst)
8799 (.str "mova src," dst)
8800 ((machine 16))
8801 (.str "mova ${dst16-16-Mova-HI}," dst)
8802 (+ (f-0-4 #xE) (f-4-4 #xB) dst16-16-Mova-HI (f-8-4 dstcode))
8803 (sequence () (set HI (reg dstop) dst16-16-Mova-HI))
8804 ())
8805)
8806(mov16a-defn r0 h-r0 0)
8807(mov16a-defn r1 h-r1 1)
8808(mov16a-defn r2 h-r2 2)
8809(mov16a-defn r3 h-r3 3)
8810(mov16a-defn a0 h-a0 4)
8811(mov16a-defn a1 h-a1 5)
8812
8813(define-pmacro (mov32a-defn dst dstop dstcode)
8814 (dni (.sym mova32. src - dst)
8815 (.str "mova src," dst)
8816 ((machine 32))
8817 (.str "mova ${dst32-16-Unprefixed-Mova-SI}," dst)
8818 (+ (f-0-4 #xD) dst32-16-Unprefixed-Mova-SI (f-7-1 1) (f-10-2 1) (f-12-1 1) (f-13-3 dstcode))
8819 (sequence () (set SI (reg dstop) dst32-16-Unprefixed-Mova-SI))
8820 ())
8821)
8822(mov32a-defn r2r0 h-r2r0 0)
8823(mov32a-defn r3r1 h-r3r1 1)
8824(mov32a-defn a0 h-a0 2)
8825(mov32a-defn a1 h-a1 3)
8826
8827;-------------------------------------------------------------
8828; movDir - move nibble
8829;-------------------------------------------------------------
8830
8831(define-pmacro (movdir-sem nib src dst)
8832 (sequence ((SI tmp))
8833 (case DFLT nib
8834 ((0) (set dst (or (and dst #xf0) (and src #xf))))
8835 ((1) (set dst (or (and dst #x0f) (sll (and src #xf) 4))))
8836 ((2) (set dst (or (and dst #xf0) (srl (and src #xf0) 4))))
8837 ((3) (set dst (or (and dst #x0f) (and src #xf0))))
8838 )
8839 )
8840 )
8841; movDir src,dst
8842(define-pmacro (mov16dir-1-defn nib dircode dir)
8843 (dni (.sym mov nib 16 ".r0l-dst")
8844 (.str "mov" nib " r0l,dst")
8845 ((machine 16))
8846 (.str "mov" nib " r0l,${dst16-16-QI}")
8847 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 dir) dst16-16-QI)
8848 (movdir-sem dircode (reg h-r0l) dst16-16-QI)
8849 ())
8850)
8851(mov16dir-1-defn ll 0 8)
8852(mov16dir-1-defn lh 1 #xA)
8853(mov16dir-1-defn hl 2 9)
8854(mov16dir-1-defn hh 3 #xB)
8855(define-pmacro (mov16dir-2-defn nib dircode dir)
8856 (dni (.sym mov nib 16 ".src-r0l")
8857 (.str "mov" nib " src,r0l")
8858 ((machine 16))
8859 (.str "mov" nib " ${dst16-16-QI},r0l")
8860 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 dir) dst16-16-QI)
8861 (movdir-sem dircode dst16-16-QI (reg h-r0l))
8862 ())
8863)
8864(mov16dir-2-defn ll 0 0)
8865(mov16dir-2-defn lh 1 2)
8866(mov16dir-2-defn hl 2 1)
8867(mov16dir-2-defn hh 3 3)
8868
8869(define-pmacro (mov32dir-1-defn nib o1o0)
8870 (dni (.sym mov nib 32 ".r0l-dst")
8871 (.str "mov" nib " r0l,dst")
8872 ((machine 32))
8873 (.str "mov" nib " r0l,${dst32-24-Prefixed-QI}")
8874 (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #xB) dst32-24-Prefixed-QI (f-15-1 0) (f-18-2 o1o0) (f-20-4 #xE))
8875 (movdir-sem o1o0 (reg h-r0l) dst32-24-Prefixed-QI)
8876 ())
8877)
8878(mov32dir-1-defn ll 0)
8879(mov32dir-1-defn lh 1)
8880(mov32dir-1-defn hl 2)
8881(mov32dir-1-defn hh 3)
8882(define-pmacro (mov32dir-2-defn nib o1o0)
8883 (dni (.sym mov nib 32 ".src-r0l")
8884 (.str "mov" nib " src,r0l")
8885 ((machine 32))
8886 (.str "mov" nib " ${dst32-24-Prefixed-QI},r0l")
8887 (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #xA) dst32-24-Prefixed-QI (f-15-1 0) (f-18-2 o1o0) (f-20-4 #xE))
8888 (movdir-sem o1o0 dst32-24-Prefixed-QI (reg h-r0l))
8889 ())
8890)
8891(mov32dir-2-defn ll 0)
8892(mov32dir-2-defn lh 1)
8893(mov32dir-2-defn hl 2)
8894(mov32dir-2-defn hh 3)
8895
8896;-------------------------------------------------------------
8897; movx - move extend sign (m32)
8898;-------------------------------------------------------------
8899
8900(define-pmacro (movx-sem mode src dst)
8901 (sequence ((SI source) (SI result))
8902 (set SI result src)
8903 (set-z-and-s result)
8904 (set dst result))
8905)
8906
8907; movx #imm,dst
8908(binary-arith32-imm-dst-defn QI SI "" 0 movx X #xB #x1 #x1 movx-sem)
8909
8910;-------------------------------------------------------------
8911; mul - multiply
8912;-------------------------------------------------------------
8913
8914(define-pmacro (mul-sem mode src1 dst)
8915 (sequence ((mode result))
8916 (set obit (add-oflag mode src1 dst 0))
8917 (set result (mul mode src1 dst))
8918 (set dst result))
8919)
8920
8921; mul.BW #imm,dst
8922(binary-arith-imm-dst mul G (f-0-4 7) (f-4-3 6) (f-8-4 5) #x8 #x1 #xF mul-sem)
8923; mul.BW src,dst
8924(binary-arith-src-dst mul G (f-0-4 #x7) (f-4-3 4) #x1 #xC mul-sem)
8925
253d272c
DD		 8926(dni mul_l "mul.l src,r2r0" ((machine 32))
8927 ("mul.l ${dst32-24-Prefixed-SI},r2r0")
8928 (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #x8) (f-15-1 #x1) (f-18-2 #x1) (f-20-4 #xf)
8929 dst32-24-Prefixed-SI)
8930 () ())
8931
8932(dni mulu_l "mulu.l src,r2r0" ((machine 32))
8933 ("mulu.l ${dst32-24-Prefixed-SI},r2r0")
8934 (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #x8) (f-15-1 #x1) (f-18-2 #x0) (f-20-4 #xf)
8935 dst32-24-Prefixed-SI)
8936 () ())
49f58d10
JB		 8937;-------------------------------------------------------------
8938; mulex - multiple extend sign (m32)
8939;-------------------------------------------------------------
8940
8941; mulex src,dst
8942; (dni mulex-absolute-indirect "mulex [src]" ((machine 32))
8943; ("mulex ${dst32-24-absolute-indirect-HI}")
8944; (+ (f-0-4 0) (f-4-4 9) (f-8-4 #xC) dst32-24-absolute-indirect-HI (f-15-1 1) (f-18-2 3) (f-20-4 #xE))
8945; (set R1R2R0 (mul DI (ext DI R2R0) (ext DI dst32-24-absolute-indirect-HI)))
8946; ())
8947(dni mulex "mulex src" ((machine 32))
8948 ("mulex ${dst32-16-Unprefixed-Mulex-HI}")
8949 (+ (f-0-4 #xC) dst32-16-Unprefixed-Mulex-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xE))
8950 (set R1R2R0 (mul DI (ext DI R2R0) (ext DI dst32-16-Unprefixed-Mulex-HI)))
8951 ())
8952; (dni mulex-indirect "mulex [src]" ((machine 32))
8953; ("mulex ${dst32-24-indirect-HI}")
8954; (+ (f-0-4 0) (f-4-4 9) (f-8-4 #xC) dst32-24-indirect-HI (f-15-1 1) (f-18-2 3) (f-20-4 #xE))
8955; (set R1R2R0 (mul DI (ext DI R2R0) (ext DI dst32-24-indirect-HI)))
8956; ())
8957
8958;-------------------------------------------------------------
8959; mulu - multiply unsigned
8960;-------------------------------------------------------------
8961
8962(define-pmacro (mulu-sem mode src1 dst)
8963 (sequence ((mode result))
8964 (set obit (add-oflag mode src1 dst 0))
8965 (set result (mul mode src1 dst))
8966 (set dst result))
8967)
8968
8969; mulu.BW #imm,dst
8970(binary-arith-imm-dst mulu G (f-0-4 7) (f-4-3 6) (f-8-4 4) #x8 #x0 #xF mulu-sem)
8971; mulu.BW src,dst
8972(binary-arith-src-dst mulu G (f-0-4 #x7) (f-4-3 0) #x1 #x4 mulu-sem)
8973
8974;-------------------------------------------------------------
8975; neg - twos complement
8976;-------------------------------------------------------------
8977
8978(define-pmacro (neg-sem mode dst)
8979 (sequence ((mode result))
8980 (set result (neg mode dst))
8981 (set-z-and-s result)
8982 (set dst result))
8983)
8984
8985; neg.BW:G
8986(unary-insn neg (f-0-4 7) (f-4-3 2) (f-8-4 #x5) #xA #x2 #xF neg-sem)
8987
8988;-------------------------------------------------------------
8989; not - twos complement
8990;-------------------------------------------------------------
8991
8992(define-pmacro (not-sem mode dst)
8993 (sequence ((mode result))
8994 (set result (not mode dst))
8995 (set-z-and-s result)
8996 (set dst result))
8997)
8998
8999; not.BW:G
c6552317
DD		 9000(unary-insn-g not (f-0-4 7) (f-4-3 2) (f-8-4 #x7) #xA #x1 #xE not-sem)
9001
9002(dni not16.b.s
9003 "not.b:s Dst16-3-S-8"
9004 ((machine 16))
9005 "not.b:s ${Dst16-3-S-8}"
9006 (+ (f-0-4 #xb) (f-4-1 #x1) Dst16-3-S-8)
9007 (not-sem QI Dst16-3-S-8)
9008 ())
49f58d10
JB		 9009
9010;-------------------------------------------------------------
9011; nop
9012;-------------------------------------------------------------
9013
9014(dni nop16
9015 "nop"
9016 ((machine 16))
9017 "nop"
9018 (+ (f-0-4 #x0) (f-4-4 #x4))
9019 (nop)
9020 ())
9021
9022(dni nop32
9023 "nop"
9024 ((machine 32))
9025 "nop"
9026 (+ (f-0-4 #xD) (f-4-4 #xE))
9027 (nop)
9028 ())
9029
9030;-------------------------------------------------------------
9031; or - logical or
9032;-------------------------------------------------------------
9033
9034(define-pmacro (or-sem mode src1 dst)
9035 (sequence ((mode result))
9036 (set result (or mode src1 dst))
9037 (set-z-and-s result)
9038 (set dst result))
9039)
9040
9041; or.BW #imm,dst (m16 #1 m32 #1)
9042(binary-arith-imm-dst or G (f-0-4 7) (f-4-3 3) (f-8-4 3) #x8 #x2 #xF or-sem)
9043; or.b:S #imm8,dst3 (m16 #2 m32 #2)
9044(binary-arith16-b-S-imm8-dst3 or ".b" (f-0-4 9) (f-4-1 1) or-sem)
9045(binary-arith32-s-imm-dst QI .b 0 or #x1 #x2 or-sem)
9046(binary-arith32-s-imm-dst HI .w 1 or #x1 #x2 or-sem)
9047; or.BW src,dst (m16 #3 m32 #3)
9048(binary-arith-src-dst or G (f-0-4 #x9) (f-4-3 4) #x1 #x5 or-sem)
8d0e2679
DD		 9049; or.b:S src,r0[lh] (m16)
9050(binary-arith16-b-S-src2 or (f-0-4 1) (f-4-1 1) or-sem)
49f58d10
JB		 9051
9052;-------------------------------------------------------------
9053; pop - restore register/memory
9054;-------------------------------------------------------------
9055
9056; TODO future: split this into .b and .w semantics
9057(define-pmacro (pop-sem-mach mach mode dst)
9058 (sequence ((mode b_or_w) (SI length))
9059 (set b_or_w -1)
9060 (set b_or_w (srl b_or_w #x8))
9061 (if (eq b_or_w #x0)
9062 (set length 1) ; .b
9063 (set length 2)) ; .w
9064
9065 (case DFLT length
9066 ((1) (set dst (mem-mach mach QI (reg h-sp))))
9067 ((2) (set dst (mem-mach mach HI (reg h-sp)))))
9068 (set (reg h-sp) (add (reg h-sp) length))
9069 )
9070)
9071
9072(define-pmacro (pop-sem16 mode dest) (pop-sem-mach 16 mode dest))
9073(define-pmacro (pop-sem32 mode dest) (pop-sem-mach 32 mode dest))
9074
9075; pop.BW:G (m16 #1)
8d0e2679 9076(unary-insn-mach-g 16 pop (f-0-4 7) (f-4-3 2) (f-8-4 #xD) pop-sem16 $G)
49f58d10
JB		 9077; pop.BW:G (m32 #1)
9078(unary-insn-mach 32 pop #xB #x2 #xF pop-sem32)
9079
9080; pop.b:S r0l/r0h
9081(dni pop16.b-s-rn "pop.b:S r0[lh]" ((machine 16))
9082 "pop.b$S ${Rn16-push-S-anyof}"
9083 (+ (f-0-4 #x9) Rn16-push-S-anyof (f-5-3 #x2))
9084 (pop-sem16 QI Rn16-push-S-anyof)
9085 ())
9086; pop.w:S a0/a1
9087(dni pop16.b-s-an "pop.w:S a[01]" ((machine 16))
9088 "pop.w$S ${An16-push-S-anyof}"
9089 (+ (f-0-4 #xD) An16-push-S-anyof (f-5-3 #x2))
9090 (pop-sem16 HI An16-push-S-anyof)
9091 ())
9092
9093;-------------------------------------------------------------
9094; popc - pop control register
9095; pushc - push control register
9096;-------------------------------------------------------------
9097
9098(define-pmacro (popc32-cr1-sem mode dst)
9099 (sequence ()
9100 (case DFLT dst
9101 ((#x0) (set (reg h-dct0) (mem32 mode (reg h-sp))))
9102 ((#x1) (set (reg h-dct1) (mem32 mode (reg h-sp))))
9103 ((#x2) (sequence ((HI tflag))
9104 (set tflag (mem32 mode (reg h-sp)))
9105 (if (and tflag #x1) (set cbit 1))
9106 (if (and tflag #x2) (set dbit 1))
9107 (if (and tflag #x4) (set zbit 1))
9108 (if (and tflag #x8) (set sbit 1))
9109 (if (and tflag #x10) (set bbit 1))
9110 (if (and tflag #x20) (set obit 1))
9111 (if (and tflag #x40) (set ibit 1))
9112 (if (and tflag #x80) (set ubit 1))))
9113 ((#x3) (set (reg h-svf) (mem32 mode (reg h-sp))))
9114 ((#x4) (set (reg h-drc0) (mem32 mode (reg h-sp))))
9115 ((#x5) (set (reg h-drc1) (mem32 mode (reg h-sp))))
9116 ((#x6) (set (reg h-dmd0) (mem32 mode (reg h-sp))))
9117 ((#x7) (set (reg h-dmd1) (mem32 mode (reg h-sp))))
9118 )
9119 (set (reg h-sp) (add (reg h-sp) 2))
9120 )
9121)
9122(define-pmacro (popc32-cr2-sem mode dst)
9123 (sequence ()
9124 (case DFLT dst
9125 ((#x0) (set (reg h-intb) (mem32 mode (reg h-sp))))
9126 ((#x1) (set (reg h-sp) (mem32 mode (reg h-sp))))
9127 ((#x2) (set (reg h-sb) (mem32 mode (reg h-sp))))
9128 ((#x3) (set (reg h-fb) (mem32 mode (reg h-sp))))
9129 ((#x7) (set (reg h-isp) (mem32 mode (reg h-sp))))
9130 )
9131 (set (reg h-sp) (add (reg h-sp) 4))
9132 )
9133)
9134(define-pmacro (popc16-sem mode dst)
9135 (sequence ()
9136 (case DFLT dst
9137 ((#x1) (set (reg h-intb) (or (and (reg h-intb) #x0000)
9138 (mem16 mode (reg h-sp)))))
9139 ((#x2) (set (reg h-intb) (or (and (reg h-intb) #xffff0000)
9140 (mem16 mode (reg h-sp)))))
9141 ((#x3) (sequence ((HI tflag))
9142 (set tflag (mem16 mode (reg h-sp)))
9143 (if (and tflag #x1) (set cbit 1))
9144 (if (and tflag #x2) (set dbit 1))
9145 (if (and tflag #x4) (set zbit 1))
9146 (if (and tflag #x8) (set sbit 1))
9147 (if (and tflag #x10) (set bbit 1))
9148 (if (and tflag #x20) (set obit 1))
9149 (if (and tflag #x40) (set ibit 1))
9150 (if (and tflag #x80) (set ubit 1))))
9151 ((#x4) (set (reg h-isp) (mem16 mode (reg h-sp))))
9152 ((#x5) (set (reg h-sp) (mem16 mode (reg h-sp))))
9153 ((#x6) (set (reg h-sb) (mem16 mode (reg h-sp))))
9154 ((#x7) (set (reg h-fb) (mem16 mode (reg h-sp))))
9155 )
9156 (set (reg h-sp) (add (reg h-sp) 2))
9157 )
9158)
9159; popc dest (m16c #1)
9160(dni popc16.imm16 "popc dst" ((machine 16))
9161 ("popc ${cr16}")
9162 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) (f-12-4 3) cr16)
9163 (popc16-sem HI cr16)
9164 ())
9165; popc dest (m32c #1)
9166(dni popc32.imm16-cr1 "popc dst" ((machine 32))
9167 ("popc ${cr1-Unprefixed-32}")
9168 (+ (f-0-4 #xD) (f-4-4 3) (f-8-4 #xA) (f-12-1 1) cr1-Unprefixed-32)
9169 (popc32-cr1-sem HI cr1-Unprefixed-32)
9170 ())
9171; popc dest (m32c #2)
9172(dni popc32.imm16-cr2 "popc dst" ((machine 32))
9173 ("popc ${cr2-32}")
9174 (+ (f-0-4 #xD) (f-4-4 3) (f-8-4 2) (f-12-1 1) cr2-32)
9175 (popc32-cr2-sem SI cr2-32)
9176 ())
9177
9178(define-pmacro (pushc32-cr1-sem mode dst)
9179 (sequence ()
9180 (set (reg h-sp) (sub (reg h-sp) 2))
9181 (case DFLT dst
9182 ((#x0) (set (mem32 mode (reg h-sp)) (reg h-dct0)))
9183 ((#x1) (set (mem32 mode (reg h-sp)) (reg h-dct1)))
9184 ((#x2) (sequence ((HI tflag))
9185 (set tflag 0)
9186 (if (eq cbit 1) (set tflag (or tflag #x1)))
9187 (if (eq dbit 1) (set tflag (or tflag #x2)))
9188 (if (eq zbit 1) (set tflag (or tflag #x4)))
9189 (if (eq sbit 1) (set tflag (or tflag #x8)))
9190 (if (eq bbit 1) (set tflag (or tflag #x10)))
9191 (if (eq obit 1) (set tflag (or tflag #x20)))
9192 (if (eq ibit 1) (set tflag (or tflag #x40)))
9193 (if (eq ubit 1) (set tflag (or tflag #x80)))
9194 (set (mem32 mode (reg h-sp)) tflag)))
9195 ((#x3) (set (mem32 mode (reg h-sp)) (reg h-svf)))
9196 ((#x4) (set (mem32 mode (reg h-sp)) (reg h-drc0)))
9197 ((#x5) (set (mem32 mode (reg h-sp)) (reg h-drc1)))
9198 ((#x6) (set (mem32 mode (reg h-sp)) (reg h-dmd0)))
9199 ((#x7) (set (mem32 mode (reg h-sp)) (reg h-dmd1)))
9200 )
9201 )
9202)
9203(define-pmacro (pushc32-cr2-sem mode dst)
9204 (sequence ()
9205 (set (reg h-sp) (sub (reg h-sp) 4))
9206 (case DFLT dst
9207 ((#x0) (set (mem32 mode (reg h-sp)) (reg h-intb)))
9208 ((#x1) (set (mem32 mode (reg h-sp)) (reg h-sp)))
9209 ((#x2) (set (mem32 mode (reg h-sp)) (reg h-sb)))
9210 ((#x3) (set (mem32 mode (reg h-sp)) (reg h-fb)))
9211 ((#x7) (set (mem32 mode (reg h-sp)) (reg h-isp)))
9212 )
9213 )
9214)
9215(define-pmacro (pushc16-sem mode dst)
9216 (sequence ()
9217 (set (reg h-sp) (sub (reg h-sp) 2))
9218 (case DFLT dst
9219 ((#x1) (set (mem16 mode (reg h-sp)) (and (reg h-intb) #xffff)))
9220 ((#x2) (set (mem16 mode (reg h-sp)) (and (reg h-intb) #xffff0000)))
9221 ((#x3) (sequence ((HI tflag))
9222 (if (eq cbit 1) (set tflag (or tflag #x1)))
9223 (if (eq dbit 1) (set tflag (or tflag #x2)))
9224 (if (eq zbit 1) (set tflag (or tflag #x4)))
9225 (if (eq sbit 1) (set tflag (or tflag #x8)))
9226 (if (eq bbit 1) (set tflag (or tflag #x10)))
9227 (if (eq obit 1) (set tflag (or tflag #x20)))
9228 (if (eq ibit 1) (set tflag (or tflag #x40)))
9229 (if (eq ubit 1) (set tflag (or tflag #x80)))
9230 (set (mem16 mode (reg h-sp)) tflag)))
9231
9232 ((#x4) (set (mem16 mode (reg h-sp)) (reg h-isp)))
9233 ((#x5) (set (mem16 mode (reg h-sp)) (reg h-sp)))
9234 ((#x6) (set (mem16 mode (reg h-sp)) (reg h-sb)))
9235 ((#x7) (set (mem16 mode (reg h-sp)) (reg h-fb)))
9236 )
9237 )
9238)
9239; pushc src (m16c)
9240(dni pushc16.imm16 "pushc dst" ((machine 16))
9241 ("pushc ${cr16}")
9242 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) (f-12-4 2) cr16)
9243 (pushc16-sem HI cr16)
9244 ())
9245; pushc src (m32c #1)
9246(dni pushc32.imm16-cr1 "pushc dst" ((machine 32))
9247 ("pushc ${cr1-Unprefixed-32}")
9248 (+ (f-0-4 #xD) (f-4-4 1) (f-8-4 #xA) (f-12-1 1) cr1-Unprefixed-32)
9249 (pushc32-cr1-sem HI cr1-Unprefixed-32)
9250 ())
9251; pushc src (m32c #2)
9252(dni pushc32.imm16-cr2 "pushc dst" ((machine 32))
9253 ("pushc ${cr2-32}")
9254 (+ (f-0-4 #xD) (f-4-4 1) (f-8-4 2) (f-12-1 1) cr2-32)
9255 (pushc32-cr2-sem SI cr2-32)
9256 ())
9257
9258;-------------------------------------------------------------
9259; popm - pop multiple
9260; pushm - push multiple
9261;-------------------------------------------------------------
9262
9263(define-pmacro (popm-sem machine dst)
9264 (sequence ((SI addrlen))
9265 (if (eq machine 16)
9266 (set addrlen 2)
9267 (set addrlen 4))
9268 (if (and dst 1)
9269 (sequence () (set R0 (mem-mach machine HI (reg h-sp)))
9270 (set (reg h-sp) (add (reg h-sp) 2))))
9271 (if (and dst 2)
9272 (sequence () (set R1 (mem-mach machine HI (reg h-sp)))
9273 (set (reg h-sp) (add (reg h-sp) 2))))
9274 (if (and dst 4)
9275 (sequence () (set R2 (mem-mach machine HI (reg h-sp)))
9276 (set (reg h-sp) (add (reg h-sp) 2))))
9277 (if (and dst 8)
9278 (sequence () (set R3 (mem-mach machine HI (reg h-sp)))
9279 (set (reg h-sp) (add (reg h-sp) 2))))
9280 (if (and dst 16)
9281 (sequence () (set A0 (mem-mach machine HI (reg h-sp)))
9282 (set (reg h-sp) (add (reg h-sp) addrlen))))
9283 (if (and dst 32)
9284 (sequence () (set A1 (mem-mach machine HI (reg h-sp)))
9285 (set (reg h-sp) (add (reg h-sp) addrlen))))
9286 (if (and dst 64)
9287 (sequence () (set (reg h-sb) (mem-mach machine HI (reg h-sp)))
9288 (set (reg h-sp) (add (reg h-sp) addrlen))))
9289 (if (eq dst 128)
9290 (sequence () (set (reg h-fb) (mem-mach machine HI (reg h-sp)))
9291 (set (reg h-sp) (add (reg h-sp) addrlen))))
9292 )
9293)
9294
9295(define-pmacro (pushm-sem machine dst)
9296 (sequence ((SI count) (SI addrlen))
9297 (if (eq machine 16)
9298 (set addrlen 2)
9299 (set addrlen 4))
9300 (if (eq dst 1)
9301 (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen))
9302 (set (mem-mach machine HI (reg h-sp)) (reg h-fb))))
9303 (if (and dst 2)
9304 (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen))
9305 (set (mem-mach machine HI (reg h-sp)) (reg h-sb))))
9306 (if (and dst 4)
9307 (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen))
9308 (set (mem-mach machine HI (reg h-sp)) A1)))
9309 (if (and dst 8)
9310 (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen))
9311 (set (mem-mach machine HI (reg h-sp)) A0)))
9312 (if (and dst 16)
9313 (sequence () (set (reg h-sp) (sub (reg h-sp) 2))
9314 (set (mem-mach machine HI (reg h-sp)) R3)))
9315 (if (and dst 32)
9316 (sequence () (set (reg h-sp) (sub (reg h-sp) 2))
9317 (set (mem-mach machine HI (reg h-sp)) R2)))
9318 (if (and dst 64)
9319 (sequence () (set (reg h-sp) (sub (reg h-sp) 2))
9320 (set (mem-mach machine HI (reg h-sp)) R1)))
9321 (if (and dst 128)
9322 (sequence () (set (reg h-sp) (sub (reg h-sp) 2))
9323 (set (mem-mach machine HI (reg h-sp)) R0)))
9324 )
9325)
9326
9327(dni popm16 "popm regs" ((machine 16))
9328 ("popm ${Regsetpop}")
9329 (+ (f-0-4 #xE) (f-4-4 #xD) Regsetpop)
9330 (popm-sem 16 Regsetpop)
9331 ())
9332(dni pushm16 "pushm regs" ((machine 16))
9333 ("pushm ${Regsetpush}")
9334 (+ (f-0-4 #xE) (f-4-4 #xC) Regsetpush)
9335 (pushm-sem 16 Regsetpush)
9336 ())
9337(dni popm "popm regs" ((machine 32))
9338 ("popm ${Regsetpop}")
9339 (+ (f-0-4 #x8) (f-4-4 #xE) Regsetpop)
9340 (popm-sem 32 Regsetpop)
9341 ())
9342(dni pushm "pushm regs" ((machine 32))
9343 ("pushm ${Regsetpush}")
9344 (+ (f-0-4 #x8) (f-4-4 #xF) Regsetpush)
9345 (pushm-sem 32 Regsetpush)
9346 ())
9347
9348;-------------------------------------------------------------
9349; push - Save register/memory/immediate data
9350;-------------------------------------------------------------
9351
9352; TODO future: split this into .b and .w semantics
9353(define-pmacro (push-sem-mach mach mode dst)
9354 (sequence ((mode b_or_w) (SI length))
9355 (set b_or_w -1)
9356 (set b_or_w (srl b_or_w #x8))
9357 (if (eq b_or_w #x0)
9358 (set length 1) ; .b
9359 (if (eq b_or_w #xff)
9360 (set length 2) ; .w
9361 (set length 4))) ; .l
9362 (set (reg h-sp) (sub (reg h-sp) length))
9363 (case DFLT length
9364 ((1) (set (mem-mach mach QI (reg h-sp)) dst))
9365 ((2) (set (mem-mach mach HI (reg h-sp)) dst))
9366 ((4) (set (mem-mach mach SI (reg h-sp)) dst)))
9367 )
9368 )
9369
9370(define-pmacro (push-sem16 mode dst) (push-sem-mach 16 mode dst))
9371(define-pmacro (push-sem32 mode dst) (push-sem-mach 32 mode dst))
9372
9373; push.BW:G imm (m16 #1 m32 #1)
9374(dni push16.b.G-imm "push.b:G #Imm-16-QI" ((machine 16))
9375 ("push.b$G #${Imm-16-QI}")
9376 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 2) Imm-16-QI)
9377 (push-sem16 QI Imm-16-QI)
9378 ())
9379
9380(dni push16.w.G-imm "push.w:G #Imm-16-HI" ((machine 16))
9381 ("push.w$G #${Imm-16-HI}")
9382 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 2) Imm-16-HI)
9383 (push-sem16 HI Imm-16-HI)
9384 ())
9385
458f7770 9386(dni push32.b.imm "push.b #Imm-8-QI" ((machine 32))
8d0e2679 9387 ("push.b #${Imm-8-QI}")
49f58d10
JB		 9388 (+ (f-0-4 #xA) (f-4-4 #xE) Imm-8-QI)
9389 (push-sem32 QI Imm-8-QI)
9390 ())
9391
9392(dni push32.w.imm "push.w #Imm-8-HI" ((machine 32))
9393 ("push.w #${Imm-8-HI}")
9394 (+ (f-0-4 #xA) (f-4-4 #xF) Imm-8-HI)
9395 (push-sem32 HI Imm-8-HI)
9396 ())
9397
9398; push.BW:G src (m16 #2)
c6552317 9399(unary-insn-mach-g 16 push (f-0-4 7) (f-4-3 2) (f-8-4 #x4) push-sem16 $G)
49f58d10
JB		 9400; push.BW:G src (m32 #2)
9401(unary-insn-mach 32 push #xC #x0 #xE push-sem32)
9402
9403
9404; push.b:S r0l/r0h (m16 #3)
9405(dni push16.b-s-rn "push.b:S r0[lh]" ((machine 16))
9406 "push.b$S ${Rn16-push-S-anyof}"
9407 (+ (f-0-4 #x8) Rn16-push-S-anyof (f-5-3 #x2))
9408 (push-sem16 QI Rn16-push-S-anyof)
9409 ())
9410; push.w:S a0/a1 (m16 #4)
9411(dni push16.b-s-an "push.w:S a[01]" ((machine 16))
9412 "push.w$S ${An16-push-S-anyof}"
9413 (+ (f-0-4 #xC) An16-push-S-anyof (f-5-3 #x2))
9414 (push-sem16 HI An16-push-S-anyof)
9415 ())
9416
9417; push.l imm32 (m32 #3)
9418(dni push32.l.imm "push.l #Imm-16-SI" ((machine 32))
9419 ("push.l #${Imm-16-SI}")
9420 (+ (f-0-4 #xB) (f-4-4 6) (f-8-4 5) (f-12-4 3) Imm-16-SI)
9421 (push-sem32 SI Imm-16-SI)
9422 ())
9423; push.l src (m32 #4)
9424(unary-insn-defn 32 16-Unprefixed SI .l push (+ (f-0-4 #xA) (f-7-1 0) dst32-16-Unprefixed-SI (f-10-2 0) (f-12-4 1)) push-sem32)
9425
9426;-------------------------------------------------------------
9427; pusha - push effective address
9428;------------------------------------------------------------
9429
9430(define-pmacro (push16a-sem mode dst)
9431 (sequence ()
9432 (set (reg h-sp) (sub (reg h-sp) 2))
9433 (set (mem16 HI (reg h-sp)) dst))
9434)
9435(define-pmacro (push32a-sem mode dst)
9436 (sequence ()
9437 (set (reg h-sp) (sub (reg h-sp) 4))
9438 (set (mem32 SI (reg h-sp)) dst))
9439)
9440(unary-insn-defn 16 16-Mova HI "" pusha (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 9) dst16-16-Mova-HI) push16a-sem)
9441(unary-insn-defn 32 16-Unprefixed-Mova SI "" pusha (+ (f-0-4 #xB) (f-7-1 0) dst32-16-Unprefixed-Mova-SI (f-10-2 0) (f-12-4 1)) push32a-sem)
9442
9443;-------------------------------------------------------------
9444; reit - return from interrupt
9445;-------------------------------------------------------------
9446
9447; ??? semantics
9448(dni reit16 "REIT" ((machine 16))
9449 ("reit")
9450 (+ (f-0-4 #xF) (f-4-4 #xB))
9451 (nop)
9452 ())
9453(dni reit32 "REIT" ((machine 32))
9454 ("reit")
9455 (+ (f-0-4 9) (f-4-4 #xE))
9456 (nop)
9457 ())
9458
9459;-------------------------------------------------------------
9460; rmpa - repeat multiple and addition
9461;-------------------------------------------------------------
9462
9463; TODO semantics
9464(dni rmpa16.b "rmpa.size" ((machine 16))
9465 ("rmpa.b")
9466 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 1))
9467 (nop)
9468 ())
9469(dni rmpa16.w "rmpa.size" ((machine 16))
9470 ("rmpa.w")
9471 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 1))
9472 (nop)
9473 ())
9474(dni rmpa32.b "rmpa.size" ((machine 32))
9475 ("rmpa.b")
9476 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 4) (f-12-4 3))
9477 (nop)
9478 ())
9479
9480(dni rmpa32.w "rmpa.size" ((machine 32))
9481 ("rmpa.w")
9482 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 5) (f-12-4 3))
9483 (nop)
9484 ())
9485
9486;-------------------------------------------------------------
9487; rolc - rotate left with carry
9488;-------------------------------------------------------------
9489
9490; TODO check semantics
9491; TODO future: split this into .b and .w semantics
9492(define-pmacro (rolc-sem mode dst)
9493 (sequence ((mode result) (SI ocbit) (mode b_or_w) (USI mask))
9494 (set b_or_w -1)
9495 (set b_or_w (srl b_or_w #x8))
9496 (if (eq b_or_w #x0)
9497 (set mask #x8000) ; .b
9498 (set mask #x80000000)) ; .w
9499 (set ocbit cbit)
9500 (set cbit (and dst mask))
9501 (set result (sll mode dst 1))
9502 (set result (or result ocbit))
9503 (set-z-and-s result)
9504 (set dst result))
9505)
9506; rolc.BW src,dst
9507(unary-insn rolc (f-0-4 7) (f-4-3 3) (f-8-4 #xA) #xB #x2 #xE rolc-sem)
9508
9509;-------------------------------------------------------------
9510; rorc - rotate right with carry
9511;-------------------------------------------------------------
9512
9513; TODO check semantics
9514; TODO future: split this into .b and .w semantics
9515(define-pmacro (rorc-sem mode dst)
9516 (sequence ((mode result) (SI ocbit) (mode b_or_w) (USI mask) (SI shamt))
9517 (set b_or_w -1)
9518 (set b_or_w (srl b_or_w #x8))
9519 (if (eq b_or_w #x0)
9520 (sequence () (set mask #x7fff) (set shamt 15)) ; .b
9521 (sequence () (set mask #x7fffffff) (set shamt 31))) ; .w
9522 (set ocbit cbit)
9523 (set cbit (and dst #x1))
9524 (set result (srl mode dst (const 1)))
9525 (set result (or (and result mask) (sll ocbit shamt)))
9526 (set-z-and-s result)
9527 (set dst result))
9528)
9529; rorc.BW src,dst
9530(unary-insn rorc (f-0-4 7) (f-4-3 3) (f-8-4 #xB) #xA #x2 #xE rorc-sem)
9531
9532;-------------------------------------------------------------
9533; rot - rotate
9534;-------------------------------------------------------------
9535
9536; TODO future: split this into .b and .w semantics
9537(define-pmacro (rot-1-sem mode src1 dst)
9538 (sequence ((mode tmp) (mode b_or_w) (USI mask) (SI shift))
9539 (case DFLT src1
9540 ((#x0) (set shift 1))
9541 ((#x1) (set shift 2))
9542 ((#x2) (set shift 3))
9543 ((#x3) (set shift 4))
9544 ((#x4) (set shift 5))
9545 ((#x5) (set shift 6))
9546 ((#x6) (set shift 7))
9547 ((#x7) (set shift 8))
9548 ((-8) (set shift -1))
9549 ((-7) (set shift -2))
9550 ((-6) (set shift -3))
9551 ((-5) (set shift -4))
9552 ((-4) (set shift -5))
9553 ((-3) (set shift -6))
9554 ((-2) (set shift -7))
9555 ((-1) (set shift -8))
9556 (else (set shift 0))
9557 )
9558 (set b_or_w -1)
9559 (set b_or_w (srl b_or_w #x8))
9560 (if (eq b_or_w #x0)
9561 (set mask #x7fff) ; .b
9562 (set mask #x7fffffff)) ; .w
9563 (set tmp dst)
9564 (if (gt mode shift 0)
9565 (sequence ()
9566 (set tmp (rol mode tmp shift))
9567 (set cbit (and tmp #x1)))
9568 (sequence ()
9569 (set tmp (ror mode tmp (mul shift -1)))
9570 (set cbit (and tmp mask))))
9571 (set-z-and-s tmp)
9572 (set dst tmp))
9573)
9574(define-pmacro (rot-2-sem mode dst)
9575 (sequence ((mode tmp) (mode b_or_w) (USI mask))
9576 (set b_or_w -1)
9577 (set b_or_w (srl b_or_w #x8))
9578 (if (eq b_or_w #x0)
9579 (set mask #x7fff) ; .b
9580 (set mask #x7fffffff)) ; .w
9581 (set tmp dst)
9582 (if (gt mode (reg h-r1h) 0)
9583 (sequence ()
9584 (set tmp (rol mode tmp (reg h-r1h)))
9585 (set cbit (and tmp #x1)))
9586 (sequence ()
9587 (set tmp (ror mode tmp (reg h-r1h)))
9588 (set cbit (and tmp mask))))
9589 (set-z-and-s tmp)
9590 (set dst tmp))
9591)
9592
9593; rot.BW #imm4,dst
9594(binary-arith16-shimm4-dst-defn QI .b 0 0 rot (f-0-4 #xE) (f-4-3 0) rot-1-sem)
9595(binary-arith16-shimm4-dst-defn HI .w 0 1 rot (f-0-4 #xE) (f-4-3 0) rot-1-sem)
9596(binary-arith32-shimm4-dst-defn QI .b 0 0 rot #x7 #x2 rot-1-sem)
9597(binary-arith32-shimm4-dst-defn HI .w 0 1 rot #x7 #x2 rot-1-sem)
9598; rot.BW src,dst
9599
9600(dni rot16.b-dst "rot r1h,dest" ((machine 16))
a1a280bb
DD		 9601 ("rot.b r1h,${dst16-16-QI}")
9602 (+ (f-0-4 7) (f-4-4 #x4) (f-8-4 #x6) dst16-16-QI)
9603 (rot-2-sem QI dst16-16-QI)
49f58d10
JB		 9604 ())
9605(dni rot16.w-dst "rot r1h,dest" ((machine 16))
9606 ("rot.w r1h,${dst16-16-HI}")
9607 (+ (f-0-4 7) (f-4-4 #x5) (f-8-4 #x6) dst16-16-HI)
9608 (rot-2-sem HI dst16-16-HI)
9609 ())
9610
9611(dni rot32.b-dst "rot r1h,dest" ((machine 32))
a1a280bb
DD		 9612 ("rot.b r1h,${dst32-16-Unprefixed-QI}")
9613 (+ (f-0-4 #xA) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xF))
9614 (rot-2-sem QI dst32-16-Unprefixed-QI)
49f58d10
JB		 9615 ())
9616(dni rot32.w-dst "rot r1h,dest" ((machine 32))
a1a280bb
DD		 9617 ("rot.w r1h,${dst32-16-Unprefixed-HI}")
9618 (+ (f-0-4 #xA) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xF))
9619 (rot-2-sem HI dst32-16-Unprefixed-HI)
49f58d10
JB		 9620 ())
9621
9622;-------------------------------------------------------------
9623; rts - return from subroutine
9624;-------------------------------------------------------------
9625
9626(define-pmacro (rts16-sem)
9627 (sequence ((SI tpc))
9628 (set tpc (mem16 HI (reg h-sp)))
9629 (set (reg h-sp) (add (reg h-sp) 2))
9630 (set tpc (or tpc (sll (mem16 QI (reg h-sp)) 16)))
9631 (set (reg h-sp) (add (reg h-sp) 1))
9632 (set pc tpc)
9633 )
9634)
9635(define-pmacro (rts32-sem)
9636 (sequence ((SI tpc))
9637 (set tpc (mem32 HI (reg h-sp)))
9638 (set (reg h-sp) (add (reg h-sp) 2))
9639 (set tpc (or tpc (sll (mem32 HI (reg h-sp)) 16)))
9640 (set (reg h-sp) (add (reg h-sp) 2))
9641 (set pc tpc)
9642 )
9643)
9644
9645(dni rts16 "rts" ((machine 16))
9646 ("rts")
9647 (+ (f-0-4 #xF) (f-4-4 3))
9648 (rts16-sem)
9649 ())
9650
9651(dni rts32 "rts" ((machine 32))
9652 ("rts")
9653 (+ (f-0-4 #xD) (f-4-4 #xF))
9654 (rts32-sem)
9655 ())
9656
9657;-------------------------------------------------------------
9658; sbb - subtract with borrow
9659;-------------------------------------------------------------
9660
9661(define-pmacro (sbb-sem mode src dst)
9662 (sequence ((mode result))
9663 (set result (subc mode dst src cbit))
9664 (set obit (add-oflag mode dst src cbit))
9665 (set cbit (add-oflag mode dst src cbit))
9666 (set-z-and-s result)
9667 (set dst result))
9668)
9669
9670; sbb.size:G #imm,dst
9671(binary-arith16-imm-dst-defn QI QI .b 0 sbb X (f-0-4 7) (f-4-3 3) (f-8-4 7) sbb-sem)
9672(binary-arith16-imm-dst-defn HI HI .w 1 sbb X (f-0-4 7) (f-4-3 3) (f-8-4 7) sbb-sem)
9673(binary-arith32-imm-dst-Prefixed QI QI .b 0 sbb X #x9 #x2 #xE sbb-sem)
9674(binary-arith32-imm-dst-Prefixed HI HI .w 1 sbb X #x9 #x2 #xE sbb-sem)
9675
9676; sbb.BW:G src,dst
9677(binary-arith16-src-dst-defn QI QI .b 0 sbb X (f-0-4 #xB) (f-4-3 4) sbb-sem)
9678(binary-arith16-src-dst-defn HI HI .w 1 sbb X (f-0-4 #xB) (f-4-3 4) sbb-sem)
9679(binary-arith32-src-dst-Prefixed QI QI .b 0 sbb X #x1 #x6 sbb-sem)
9680(binary-arith32-src-dst-Prefixed HI HI .w 1 sbb X #x1 #x6 sbb-sem)
9681
9682;-------------------------------------------------------------
9683; sbjnz - subtract then jump on not zero
9684;-------------------------------------------------------------
9685
9686(define-pmacro (sub-jnz-sem mode src dst label)
9687 (sequence ((mode result))
9688 (set result (sub mode dst src))
9689 (set dst result)
9690 (if (ne result 0)
9691 (set pc label)))
9692)
9693
9694; sbjnz.size #imm4,dst,label
c6552317 9695(arith-jnz-imm4-dst sbjnz s4n (f-0-4 #xF) (f-4-3 4) #xf #x1 sub-jnz-sem)
49f58d10
JB		 9696
9697;-------------------------------------------------------------
9698; sccnd - store condition on condition (m32)
9699;-------------------------------------------------------------
9700
9701(define-pmacro (sccnd-sem cnd dst)
9702 (sequence ()
9703 (set dst 0)
9704 (case DFLT cnd
9705 ((#x00) (if (not cbit) (set dst 1))) ;ltu nc
9706 ((#x01) (if (or cbit zbit) (set dst 1))) ;leu
9707 ((#x02) (if (not zbit) (set dst 1))) ;ne nz
9708 ((#x03) (if (not sbit) (set dst 1))) ;pz
9709 ((#x04) (if (not obit) (set dst 1))) ;no
9710 ((#x05) (if (not (or zbit (xor sbit obit))) (set dst 1))) ;gt
9711 ((#x06) (if (xor sbit obit) (set dst 1))) ;ge
9712 ((#x08) (if (trunc BI cbit) (set dst 1))) ;geu c
9713 ((#x09) (if (not (or cbit zbit)) (set dst 1))) ;gtu
9714 ((#x0a) (if (trunc BI zbit) (set dst 1))) ;eq z
9715 ((#x0b) (if (trunc BI sbit) (set dst 1))) ;n
9716 ((#x0c) (if (trunc BI obit) (set dst 1))) ;o
9717 ((#x0d) (if (or zbit (xor sbit obit)) (set dst 1))) ;le
9718 ((#x0e) (if (xor sbit obit) (set dst 1))) ;lt
9719 )
9720 )
9721 )
9722
9723; scCND dst
9724(dni sccnd
9725 "sccnd dst"
9726 ((machine 32))
9727 "sc$sccond32 ${dst32-16-Unprefixed-HI}"
9728 (+ (f-0-4 #xD) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) sccond32)
9729 (sccnd-sem sccond32 dst32-16-Unprefixed-HI)
9730 ())
9731
9732;-------------------------------------------------------------
9733; scmpu - string compare unequal (m32)
9734;-------------------------------------------------------------
9735
9736; TODO semantics
9737(dni scmpu.b "scmpu.b" ((machine 32))
9738 ("scmpu.b")
9739 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 #xC) (f-12-4 3))
9740 (c-call VOID "scmpu_QI_semantics")
9741 ())
9742
9743(dni scmpu.w "scmpu.w" ((machine 32))
9744 ("scmpu.w")
9745 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 #xD) (f-12-4 3))
9746 (c-call VOID "scmpu_HI_semantics")
9747 ())
9748
9749;-------------------------------------------------------------
9750; sha - shift arithmetic
9751;-------------------------------------------------------------
9752
9753; TODO future: split this into .b and .w semantics
9754(define-pmacro (sha-sem mode src1 dst)
9755 (sequence ((mode result)(mode shift)(mode shmode))
9756 (case DFLT src1
9757 ((#x0) (set shift 1))
9758 ((#x1) (set shift 2))
9759 ((#x2) (set shift 3))
9760 ((#x3) (set shift 4))
9761 ((#x4) (set shift 5))
9762 ((#x5) (set shift 6))
9763 ((#x6) (set shift 7))
9764 ((#x7) (set shift 8))
9765 ((-8) (set shift -1))
9766 ((-7) (set shift -2))
9767 ((-6) (set shift -3))
9768 ((-5) (set shift -4))
9769 ((-4) (set shift -5))
9770 ((-3) (set shift -6))
9771 ((-2) (set shift -7))
9772 ((-1) (set shift -8))
9773 (else (set shift 0))
9774 )
9775 (set shmode -1)
9776 (set shmode (srl shmode #x8))
9777 (if (lt mode shift #x0) (set result (sra mode dst (mul shift -1))))
9778 (if (gt mode shift 0) (set result (sll mode dst shift)))
9779 (if (eq shmode #x0) ; QI
9780 (sequence
9781 ((mode cbitamt))
9782 (if (lt mode shift #x0)
9783 (set cbitamt (sub #x8 shift)) ; sra
9784 (set cbitamt (sub shift 1))) ; sll
9785 (set cbit (srl (and (sll dst cbitamt) #x80) #x7))
9786 (set obit (ne (and dst #x80) (and result #x80)))
9787 ))
9788 (if (eq shmode #xff) ; HI
9789 (sequence
9790 ((mode cbitamt))
9791 (if (lt mode shift #x0)
9792 (set cbitamt (sub 16 shift)) ; sra
9793 (set cbitamt (sub shift 1))) ; sll
9794 (set cbit (srl (and (sll dst cbitamt) #x8000) #xf))
9795 (set obit (ne (and dst #x8000) (and result #x8000)))
9796 ))
9797 (set-z-and-s result)
9798 (set dst result))
9799)
9800(define-pmacro (shar1h-sem mode dst)
9801 (sequence ((mode result)(mode shmode))
9802 (set shmode -1)
9803 (set shmode (srl shmode #x8))
9804 (if (lt mode (reg h-r1h) 0) (set result (sra mode dst (reg h-r1h))))
9805 (if (gt mode (reg h-r1h) 0) (set result (sll mode dst (reg h-r1h))))
9806 (if (eq shmode #x0) ; QI
9807 (sequence
9808 ((mode cbitamt))
9809 (if (lt mode (reg h-r1h) #x0)
9810 (set cbitamt (sub #x8 (reg h-r1h))) ; sra
9811 (set cbitamt (sub (reg h-r1h) 1))) ; sll
9812 (set cbit (srl (and (sll dst cbitamt) #x80) #x7))
9813 (set obit (ne (and dst #x80) (and result #x80)))
9814 ))
9815 (if (eq shmode #xff) ; HI
9816 (sequence
9817 ((mode cbitamt))
9818 (if (lt mode (reg h-r1h) #x0)
9819 (set cbitamt (sub 16 (reg h-r1h))) ; sra
9820 (set cbitamt (sub (reg h-r1h) 1))) ; sll
9821 (set cbit (srl (and (sll dst cbitamt) #x8000) #xf))
9822 (set obit (ne (and dst #x8000) (and result #x8000)))
9823 ))
9824 (set-z-and-s result)
9825 (set dst result))
9826)
9827; sha.BW #imm4,dst (m16 #1 m32 #1)
9828(binary-arith16-shimm4-dst-defn QI .b 0 0 sha (f-0-4 #xF) (f-4-3 0) sha-sem)
9829(binary-arith16-shimm4-dst-defn HI .w 0 1 sha (f-0-4 #xF) (f-4-3 0) sha-sem)
9830(binary-arith32-shimm4-dst-defn QI .b 1 0 sha #x7 #x0 sha-sem)
9831(binary-arith32-shimm4-dst-defn HI .w 1 1 sha #x7 #x0 sha-sem)
9832; sha.BW r1h,dst (m16 #2 m32 #3)
9833(dni sha16.b-dst "sha.b r1h,dest" ((machine 16))
9834 ("sha.b r1h,${dst16-16-QI}")
9835 (+ (f-0-4 7) (f-4-4 4) (f-8-4 #xF) dst16-16-QI)
9836 (shar1h-sem HI dst16-16-QI)
9837 ())
9838(dni sha16.w-dst "sha.w r1h,dest" ((machine 16))
9839 ("sha.w r1h,${dst16-16-HI}")
9840 (+ (f-0-4 7) (f-4-4 5) (f-8-4 #xF) dst16-16-HI)
9841 (shar1h-sem HI dst16-16-HI)
9842 ())
9843(dni sha32.b-dst "sha.b r1h,dest" ((machine 32))
9844 ("sha.b r1h,${dst32-16-Unprefixed-QI}")
9845 (+ (f-0-4 #xB) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xE))
9846 (shar1h-sem QI dst32-16-Unprefixed-QI)
9847 ())
9848(dni sha32.w-dst "sha.w r1h,dest" ((machine 32))
9849 ("sha.w r1h,${dst32-16-Unprefixed-HI}")
9850 (+ (f-0-4 #xB) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xE))
9851 (shar1h-sem HI dst32-16-Unprefixed-HI)
9852 ())
9853; sha.L #imm,dst (m16 #3)
9854(dni sha16-L-imm-r2r0 "sha.L #Imm-sh-12-s4,r2r0" ((machine 16))
9855 "sha.l #${Imm-sh-12-s4},r2r0"
9856 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #xA) Imm-sh-12-s4)
9857 (sha-sem SI Imm-sh-12-s4 (reg h-r2r0))
9858 ())
9859(dni sha16-L-imm-r3r1 "sha.L #Imm-sh-12-s4,r3r1" ((machine 16))
9860 "sha.l #${Imm-sh-12-s4},r3r1"
9861 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #xB) Imm-sh-12-s4)
9862 (sha-sem SI Imm-sh-12-s4 (reg h-r3r1))
9863 ())
9864; sha.L r1h,dst (m16 #4)
9865(dni sha16-L-r1h-r2r0 "sha.L r1h,r2r0" ((machine 16))
9866 "sha.l r1h,r2r0"
9867 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 2) (f-12-4 1))
9868 (sha-sem SI (reg h-r1h) (reg h-r2r0))
9869 ())
9870(dni sha16-L-r1h-r3r1 "sha.L r1h,r3r1" ((machine 16))
9871 "sha.l r1h,r3r1"
9872 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 3) (f-12-4 1))
9873 (sha-sem SI (reg h-r1h) (reg h-r3r1))
9874 ())
9875; sha.L #imm8,dst (m32 #2)
9876(binary-arith32-imm-dst-defn QI SI .l 0 sha X #xA #x2 #x1 sha-sem)
9877; sha.L r1h,dst (m32 #4)
9878(dni sha32.l-dst "sha.l r1h,dest" ((machine 32))
9879 ("sha.l r1h,${dst32-16-Unprefixed-SI}")
9880 (+ (f-0-4 #xC) dst32-16-Unprefixed-SI (f-7-1 0) (f-10-2 1) (f-12-4 1))
9881 (shar1h-sem QI dst32-16-Unprefixed-SI)
9882 ())
9883
9884;-------------------------------------------------------------
9885; shanc - shift arithmetic non carry (m32)
9886;-------------------------------------------------------------
9887
9888; TODO check semantics
9889; shanc.L #imm8,dst
9890(binary-arith32-imm-dst-defn QI SI .l 0 shanc X #xC #x2 #x1 sha-sem)
9891
9892;-------------------------------------------------------------
9893; shl - shift logical
9894;-------------------------------------------------------------
9895
9896; TODO future: split this into .b and .w semantics
9897(define-pmacro (shl-sem mode src1 dst)
9898 (sequence ((mode result)(mode shift)(mode shmode))
9899 (case DFLT src1
9900 ((#x0) (set shift 1))
9901 ((#x1) (set shift 2))
9902 ((#x2) (set shift 3))
9903 ((#x3) (set shift 4))
9904 ((#x4) (set shift 5))
9905 ((#x5) (set shift 6))
9906 ((#x6) (set shift 7))
9907 ((#x7) (set shift 8))
9908 ((-8) (set shift -1))
9909 ((-7) (set shift -2))
9910 ((-6) (set shift -3))
9911 ((-5) (set shift -4))
9912 ((-4) (set shift -5))
9913 ((-3) (set shift -6))
9914 ((-2) (set shift -7))
9915 ((-1) (set shift -8))
9916 (else (set shift 0))
9917 )
9918 (set shmode -1)
9919 (set shmode (srl shmode #x8))
9920 (if (lt mode shift #x0) (set result (srl mode dst (mul shift -1))))
9921 (if (gt mode shift 0) (set result (sll mode dst shift)))
9922 (if (eq shmode #x0) ; QI
9923 (sequence
9924 ((mode cbitamt))
9925 (if (lt mode shift #x0)
9926 (set cbitamt (sub #x8 shift)); srl
9927 (set cbitamt (sub shift 1))) ; sll
9928 (set cbit (srl (and (sll dst cbitamt) #x80) #x7))
9929 (set obit (ne (and dst #x80) (and result #x80)))
9930 ))
9931 (if (eq shmode #xff) ; HI
9932 (sequence
9933 ((mode cbitamt))
9934 (if (lt mode shift #x0)
9935 (set cbitamt (sub 16 shift)) ; srl
9936 (set cbitamt (sub shift 1))) ; sll
9937 (set cbit (srl (and (sll dst cbitamt) #x8000) #xf))
9938 (set obit (ne (and dst #x8000) (and result #x8000)))
9939 ))
9940 (set-z-and-s result)
9941 (set dst result))
9942 )
9943(define-pmacro (shlr1h-sem mode dst)
9944 (sequence ((mode result)(mode shmode))
9945 (set shmode -1)
9946 (set shmode (srl shmode #x8))
9947 (if (lt mode (reg h-r1h) 0) (set result (srl mode dst (reg h-r1h))))
9948 (if (gt mode (reg h-r1h) 0) (set result (sll mode dst (reg h-r1h))))
9949 (if (eq shmode #x0) ; QI
9950 (sequence
9951 ((mode cbitamt))
9952 (if (lt mode (reg h-r1h) #x0)
9953 (set cbitamt (sub #x8 (reg h-r1h))) ; srl
9954 (set cbitamt (sub (reg h-r1h) 1))) ; sll
9955 (set cbit (srl (and (sll dst cbitamt) #x80) #x7))
9956 (set obit (ne (and dst #x80) (and result #x80)))
9957 ))
9958 (if (eq shmode #xff) ; HI
9959 (sequence
9960 ((mode cbitamt))
9961 (if (lt mode (reg h-r1h) #x0)
9962 (set cbitamt (sub 16 (reg h-r1h))) ; srl
9963 (set cbitamt (sub (reg h-r1h) 1))) ; sll
9964 (set cbit (srl (and (sll dst cbitamt) #x8000) #xf))
9965 (set obit (ne (and dst #x8000) (and result #x8000)))
9966 ))
9967 (set-z-and-s result)
9968 (set dst result))
9969 )
9970; shl.BW #imm4,dst (m16 #1 m32 #1)
9971(binary-arith16-shimm4-dst-defn QI .b 0 0 shl (f-0-4 #xE) (f-4-3 4) shl-sem)
9972(binary-arith16-shimm4-dst-defn HI .w 0 1 shl (f-0-4 #xE) (f-4-3 4) shl-sem)
9973(binary-arith32-shimm4-dst-defn QI .b 0 0 shl #x7 #x0 shl-sem)
9974(binary-arith32-shimm4-dst-defn HI .w 0 1 shl #x7 #x0 shl-sem)
9975; shl.BW r1h,dst (m16 #2 m32 #3)
9976(dni shl16.b-dst "shl.b r1h,dest" ((machine 16))
9977 ("shl.b r1h,${dst16-16-QI}")
9978 (+ (f-0-4 7) (f-4-4 4) (f-8-4 #xE) dst16-16-QI)
9979 (shlr1h-sem HI dst16-16-QI)
9980 ())
9981(dni shl16.w-dst "shl.w r1h,dest" ((machine 16))
9982 ("shl.w r1h,${dst16-16-HI}")
9983 (+ (f-0-4 7) (f-4-4 5) (f-8-4 #xE) dst16-16-HI)
9984 (shlr1h-sem HI dst16-16-HI)
9985 ())
9986(dni shl32.b-dst "shl.b r1h,dest" ((machine 32))
9987 ("shl.b r1h,${dst32-16-Unprefixed-QI}")
9988 (+ (f-0-4 #xA) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xE))
9989 (shlr1h-sem QI dst32-16-Unprefixed-QI)
9990 ())
9991(dni shl32.w-dst "shl.w r1h,dest" ((machine 32))
9992 ("shl.w r1h,${dst32-16-Unprefixed-HI}")
9993 (+ (f-0-4 #xA) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xE))
9994 (shlr1h-sem HI dst32-16-Unprefixed-HI)
9995 ())
9996; shl.L #imm,dst (m16 #3)
9997(dni shl16-L-imm-r2r0 "shl.L #Imm-sh-12-s4,r2r0" ((machine 16))
9998 "shl.l #${Imm-sh-12-s4},r2r0"
9999 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #x8) Imm-sh-12-s4)
10000 (shl-sem SI Imm-sh-12-s4 (reg h-r2r0))
10001 ())
10002(dni shl16-L-imm-r3r1 "shl.L #Imm-sh-12-s4,r3r1" ((machine 16))
10003 "shl.l #${Imm-sh-12-s4},r3r1"
10004 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #x9) Imm-sh-12-s4)
10005 (shl-sem SI Imm-sh-12-s4 (reg h-r3r1))
10006 ())
10007; shl.L r1h,dst (m16 #4)
10008(dni shl16-L-r1h-r2r0 "shl.L r1h,r2r0" ((machine 16))
10009 "shl.l r1h,r2r0"
10010 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 0) (f-12-4 1))
10011 (shl-sem SI (reg h-r1h) (reg h-r2r0))
10012 ())
10013(dni shl16-L-r1h-r3r1 "shl.L r1h,r3r1" ((machine 16))
10014 "shl.l r1h,r3r1"
10015 (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 1) (f-12-4 1))
10016 (shl-sem SI (reg h-r1h) (reg h-r3r1))
10017 ())
10018; shl.L #imm8,dst (m32 #2)
10019(binary-arith32-imm-dst-defn QI SI .l 0 shl X #x9 #x2 #x1 shl-sem)
10020; shl.L r1h,dst (m32 #4)
10021(dni shl32.l-dst "shl.l r1h,dest" ((machine 32))
10022 ("shl.l r1h,${dst32-16-Unprefixed-SI}")
10023 (+ (f-0-4 #xC) dst32-16-Unprefixed-SI (f-7-1 0) (f-10-2 0) (f-12-4 1))
10024 (shlr1h-sem QI dst32-16-Unprefixed-SI)
10025 ())
10026
10027;-------------------------------------------------------------
10028; shlnc - shift logical non carry
10029;-------------------------------------------------------------
10030
10031; TODO check semantics
10032; shlnc.L #imm8,dst
10033(binary-arith32-imm-dst-defn QI SI .l 0 shlnc X #x8 #x2 #x1 shl-sem)
10034
10035;-------------------------------------------------------------
10036; sin - string input (m32)
10037;-------------------------------------------------------------
10038
10039; TODO semantics
10040(dni sin32.b "sin" ((machine 32))
10041 ("sin.b")
10042 (+ (f-0-4 #xB) (f-4-4 2) (f-8-4 8) (f-12-4 3))
10043 (c-call VOID "sin_QI_semantics")
10044 ())
10045
10046(dni sin32.w "sin" ((machine 32))
10047 ("sin.w")
10048 (+ (f-0-4 #xB) (f-4-4 2) (f-8-4 9) (f-12-4 3))
10049 (c-call VOID "sin_HI_semantics")
10050 ())
10051
10052;-------------------------------------------------------------
10053; smovb - string move backward
10054;-------------------------------------------------------------
10055
10056; TODO semantics
10057(dni smovb16.b "smovb.b" ((machine 16))
10058 ("smovb.b")
10059 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 9))
10060 (c-call VOID "smovb_QI_semantics")
10061 ())
10062
10063(dni smovb16.w "smovb.w" ((machine 16))
10064 ("smovb.w")
10065 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 9))
10066 (c-call VOID "smovb_HI_semantics")
10067 ())
10068
10069(dni smovb32.b "smovb.b" ((machine 32))
10070 ("smovb.b")
10071 (+ (f-0-4 #xB) (f-4-4 6) (f-8-4 8) (f-12-4 3))
10072 (c-call VOID "smovb_QI_semantics")
10073 ())
10074
10075(dni smovb32.w "smovb.w" ((machine 32))
10076 ("smovb.w")
10077 (+ (f-0-4 #xB) (f-4-4 6) (f-8-4 9) (f-12-4 3))
10078 (c-call VOID "smovb_HI_semantics")
10079 ())
10080
10081;-------------------------------------------------------------
10082; smovf - string move forward (m32)
10083;-------------------------------------------------------------
10084
10085; TODO semantics
10086(dni smovf16.b "smovf.b" ((machine 16))
10087 ("smovf.b")
10088 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 8))
10089 (c-call VOID "smovf_QI_semantics")
10090 ())
10091
10092(dni smovf16.w "smovf.w" ((machine 16))
10093 ("smovf.w")
10094 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 8))
10095 (c-call VOID "smovf_HI_semantics")
10096 ())
10097
10098(dni smovf32.b "smovf.b" ((machine 32))
10099 ("smovf.b")
10100 (+ (f-0-4 #xB) (f-4-4 0) (f-8-4 8) (f-12-4 3))
10101 (c-call VOID "smovf_QI_semantics")
10102 ())
10103
10104(dni smovf32.w "smovf.w" ((machine 32))
10105 ("smovf.w")
10106 (+ (f-0-4 #xB) (f-4-4 0) (f-8-4 9) (f-12-4 3))
10107 (c-call VOID "smovf_HI_semantics")
10108 ())
10109
10110;-------------------------------------------------------------
10111; smovu - string move unequal (m32)
10112;-------------------------------------------------------------
10113
10114; TODO semantics
10115(dni smovu.b "smovu.b" ((machine 32))
10116 ("smovu.b")
10117 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 8) (f-12-4 3))
10118 (c-call VOID "smovu_QI_semantics")
10119 ())
10120
10121(dni smovu.w "smovu.w" ((machine 32))
10122 ("smovu.w")
10123 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 9) (f-12-4 3))
10124 (c-call VOID "smovu_HI_semantics")
10125 ())
10126
10127;-------------------------------------------------------------
10128; sout - string output (m32)
10129;-------------------------------------------------------------
10130
10131; TODO semantics
10132(dni sout.b "sout.b" ((machine 32))
10133 ("sout.b")
10134 (+ (f-0-4 #xB) (f-4-4 4) (f-8-4 8) (f-12-4 3))
10135 (c-call VOID "sout_QI_semantics")
10136 ())
10137
10138(dni sout.w "sout" ((machine 32))
10139 ("sout.w")
10140 (+ (f-0-4 #xB) (f-4-4 4) (f-8-4 9) (f-12-4 3))
10141 (c-call VOID "sout_HI_semantics")
10142 ())
10143
10144;-------------------------------------------------------------
10145; sstr - string store
10146;-------------------------------------------------------------
10147
10148; TODO semantics
10149(dni sstr16.b "sstr.b" ((machine 16))
10150 ("sstr.b")
10151 (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 #xA))
10152 (c-call VOID "sstr_QI_semantics")
10153 ())
10154
10155(dni sstr16.w "sstr.w" ((machine 16))
10156 ("sstr.w")
10157 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 #xA))
10158 (c-call VOID "sstr_HI_semantics")
10159 ())
10160
10161(dni sstr.b "sstr" ((machine 32))
10162 ("sstr.b")
10163 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 0) (f-12-4 3))
10164 (c-call VOID "sstr_QI_semantics")
10165 ())
10166
10167(dni sstr.w "sstr" ((machine 32))
10168 ("sstr.w")
10169 (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 1) (f-12-4 3))
10170 (c-call VOID "sstr_HI_semantics")
10171 ())
10172
10173;-------------------------------------------------------------
10174; stnz - store on not zero
10175;-------------------------------------------------------------
10176
10177(define-pmacro (stnz-sem mode src dst)
10178 (sequence ()
10179 (if (ne zbit (const 1))
10180 (set dst src)))
10181)
10182; stnz #imm8,dst3 (m16)
10183(binary-arith16-b-S-imm8-dst3 stnz "" (f-0-4 #xD) (f-4-1 0) stnz-sem)
10184; stnz.BW #imm,dst (m32)
10185(binary-arith32-imm-dst-defn QI QI .b 0 stnz X #x9 #x1 #xF stnz-sem)
10186(binary-arith32-imm-dst-defn HI HI .w 1 stnz X #x9 #x1 #xF stnz-sem)
10187
10188;-------------------------------------------------------------
10189; stz - store on zero
10190;-------------------------------------------------------------
10191
10192(define-pmacro (stz-sem mode src dst)
10193 (sequence ()
10194 (if (eq zbit (const 1))
10195 (set dst src)))
10196)
10197; stz #imm8,dst3 (m16)
10198(binary-arith16-b-S-imm8-dst3 stz "" (f-0-4 #xC) (f-4-1 1) stz-sem)
10199; stz.BW #imm,dst (m32)
10200(binary-arith32-imm-dst-defn QI QI .b 0 stz X #x9 #x0 #xF stz-sem)
10201(binary-arith32-imm-dst-defn HI HI .w 1 stz X #x9 #x0 #xF stz-sem)
10202
10203;-------------------------------------------------------------
10204; stzx - store on zero extention
10205;-------------------------------------------------------------
10206
10207(define-pmacro (stzx-sem mode src1 src2 dst)
10208 (sequence ()
10209 (if (eq zbit (const 1))
10210 (set dst src1)
10211 (set dst src2)))
10212 )
10213; stzx #imm8,dst3 (m16)
10214(dni stzx16-imm8-imm8-r0h "stzx #Imm8,#Imm8,r0h" ((machine 16))
10215 ("stzx #${Imm-8-QI},#${Imm-16-QI},r0h")
10216 (+ (f-0-4 #xD) (f-4-4 #xB) Imm-8-QI Imm-16-QI)
10217 (stzx-sem QI Imm-8-QI Imm-16-QI (reg h-r0h))
10218 ())
10219(dni stzx16-imm8-imm8-r0l "stzx #Imm8,#Imm8,r0l" ((machine 16))
10220 ("stzx #${Imm-8-QI},#${Imm-16-QI},r0l")
10221 (+ (f-0-4 #xD) (f-4-4 #xC) Imm-8-QI Imm-16-QI)
10222 (stzx-sem QI Imm-8-QI Imm-16-QI (reg h-r0l))
10223 ())
10224(dni stzx16-imm8-imm8-dsp8sb "stzx #Imm8,#Imm8,dsp8[sb]" ((machine 16))
c6552317 10225 ("stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-u8}[sb]")
49f58d10
JB		 10226 (+ (f-0-4 #xD) (f-4-4 #xD) Imm-8-QI Dsp-16-u8 Imm-24-QI)
10227 (stzx-sem QI Imm-8-QI Imm-16-QI (mem16 QI (add (reg h-sb) Dsp-24-u8)))
10228 ())
10229(dni stzx16-imm8-imm8-dsp8fb "stzx #Imm8,#Imm8,dsp8[fb]" ((machine 16))
c6552317
DD		 10230 ("stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-s8}[fb]")
10231 (+ (f-0-4 #xD) (f-4-4 #xE) Imm-8-QI Dsp-16-s8 Imm-24-QI)
10232 (stzx-sem QI Imm-8-QI Imm-24-QI (mem16 QI (add (reg h-fb) Dsp-16-s8)))
49f58d10
JB		 10233 ())
10234(dni stzx16-imm8-imm8-abs16 "stzx #Imm8,#Imm8,abs16" ((machine 16))
c6552317 10235 ("stzx #${Imm-8-QI},#${Imm-32-QI},${Dsp-16-u16}")
49f58d10
JB		 10236 (+ (f-0-4 #xD) (f-4-4 #xE) Imm-8-QI Dsp-16-u16 Imm-32-QI)
10237 (stzx-sem QI Imm-8-QI Imm-32-QI (mem16 QI Dsp-16-u16))
10238 ())
10239; stzx.BW #imm,dst (m32)
10240(insn-imm1-imm2-dst-Unprefixed stzx #x9 #x3 #xF stzx-sem)
10241
10242;-------------------------------------------------------------
10243; subx - subtract extend (m32)
10244;-------------------------------------------------------------
10245
10246(define-pmacro (subx-sem mode src1 dst)
10247 (sequence ((mode result))
10248 (set result (sub mode dst (ext mode src1)))
10249 (set obit (sub-oflag mode dst (ext mode src1) 0))
10250 (set cbit (sub-cflag mode dst (ext mode src1) 0))
10251 (set dst result)
10252 (set-z-and-s result)))
10253; subx #imm8,dst
10254(binary-arith32-imm-dst-defn QI SI "" 0 subx G #x9 #x1 #x1 subx-sem)
10255; subx src,dst
10256(binary-arith32-src-dst-defn QI SI "" 0 subx G #x1 #x0 subx-sem)
10257
10258;-------------------------------------------------------------
10259; tst - test
10260;-------------------------------------------------------------
10261
10262(define-pmacro (tst-sem mode src1 dst)
10263 (sequence ((mode result))
10264 (set result (and mode dst src1))
10265 (set-z-and-s result))
10266)
10267
10268; tst.BW #imm,dst (m16 #1 m32 #1)
f75eb1c0 10269(binary-arith-imm-dst tst G (f-0-4 7) (f-4-3 3) (f-8-4 0) #x9 #x3 #xE tst-sem)
49f58d10
JB		 10270; tst.BW src,dst (m16 #2 m32 #3)
10271(binary-arith16-src-dst-defn QI QI .b 0 tst X (f-0-4 #x8) (f-4-3 0) tst-sem)
10272(binary-arith16-src-dst-defn HI HI .w 1 tst X (f-0-4 #x8) (f-4-3 0) tst-sem)
f75eb1c0
DD		 10273(binary-arith32-src-dst-Prefixed QI QI .b 0 tst G #x1 #x9 tst-sem)
10274(binary-arith32-src-dst-Prefixed HI HI .w 1 tst G #x1 #x9 tst-sem)
49f58d10
JB		 10275; tst.BW:S #imm,dst2 (m32 #2)
10276(binary-arith32-s-imm-dst QI .b 0 tst #x0 #x6 tst-sem)
10277(binary-arith32-s-imm-dst HI .w 1 tst #x0 #x6 tst-sem)
10278
10279;-------------------------------------------------------------
10280; und - undefined
10281;-------------------------------------------------------------
10282
10283(dni und16 "und" ((machine 16))
10284 ("und")
10285 (+ (f-0-4 #xF) (f-4-4 #xF))
10286 (nop)
10287 ())
10288
10289(dni und32 "und" ((machine 32))
10290 ("und")
10291 (+ (f-0-4 #xF) (f-4-4 #xF))
10292 (nop)
10293 ())
10294
10295;-------------------------------------------------------------
10296; wait
10297;-------------------------------------------------------------
10298
10299; ??? semantics
10300(dni wait16 "wait" ((machine 16))
10301 ("wait")
10302 (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 3))
10303 (nop)
10304 ())
10305
10306(dni wait "wait" ((machine 32))
10307 ("wait")
10308 (+ (f-0-4 #xB) (f-4-4 2) (f-8-4 0) (f-12-4 3))
10309 (nop)
10310 ())
10311
10312;-------------------------------------------------------------
10313; xchg - exchange
10314;-------------------------------------------------------------
10315
10316(define-pmacro (xchg-sem mode src dst)
10317 (sequence ((mode result))
10318 (set result src)
10319 (set src dst)
10320 (set dst result))
10321 )
10322(define-pmacro (xchg16-defn mode sz szc src srcreg)
10323 (dni (.sym xchg16 sz - srcreg)
10324 (.str "xchg" sz "-" srcreg ",dst16-16-" mode)
10325 ((machine 16))
10326 (.str "xchg." sz " " srcreg ",${dst16-16-" mode "}")
10327 (+ (f-0-4 #x7) (f-4-3 #x5) (f-7-1 szc) (f-8-2 0) (f-10-2 src) (.sym dst16-16- mode))
10328 (xchg-sem mode (reg (.sym h- srcreg)) (.sym dst16-16- mode))
10329 ())
10330)
10331(xchg16-defn QI b 0 0 r0l)
10332(xchg16-defn QI b 0 1 r0h)
10333(xchg16-defn QI b 0 2 r1l)
10334(xchg16-defn QI b 0 3 r1h)
a1a280bb 10335(xchg16-defn HI w 1 0 r0)
49f58d10
JB		 10336(xchg16-defn HI w 1 1 r1)
10337(xchg16-defn HI w 1 2 r2)
10338(xchg16-defn HI w 1 3 r3)
10339(define-pmacro (xchg32-defn mode sz szc src srcreg)
10340 (dni (.sym xchg32 sz - srcreg)
10341 (.str "xchg" sz "-" srcreg ",dst32-16-Unprefixed-" mode)
10342 ((machine 32))
10343 (.str "xchg." sz " " srcreg ",${dst32-16-Unprefixed-" mode "}")
10344 (+ (f-0-4 #xD) (.sym dst32-16-Unprefixed- mode) (f-7-1 szc) (f-10-2 0) (f-12-1 1) (f-13-3 src))
10345 (xchg-sem mode (reg (.sym h- srcreg)) (.sym dst32-16-Unprefixed- mode))
10346 ())
10347)
10348(xchg32-defn QI b 0 0 r0l)
10349(xchg32-defn QI b 0 1 r1l)
10350(xchg32-defn QI b 0 2 a0)
10351(xchg32-defn QI b 0 3 a1)
10352(xchg32-defn QI b 0 4 r0h)
10353(xchg32-defn QI b 0 5 r1h)
10354(xchg32-defn HI w 1 0 r0)
10355(xchg32-defn HI w 1 1 r1)
10356(xchg32-defn HI w 1 2 a0)
10357(xchg32-defn HI w 1 3 a1)
10358(xchg32-defn HI w 1 4 r2)
10359(xchg32-defn HI w 1 5 r3)
10360
10361;-------------------------------------------------------------
10362; xor - exclusive or
10363;-------------------------------------------------------------
10364
10365(define-pmacro (xor-sem mode src1 dst)
10366 (sequence ((mode result))
10367 (set result (xor mode src1 dst))
10368 (set-z-and-s result)
10369 (set dst result))
10370)
10371
10372; xor.BW #imm,dst (m16 #1 m32 #1)
10373(binary-arith-imm-dst xor G (f-0-4 7) (f-4-3 3) (f-8-4 1) #x9 #x0 #xE xor-sem)
10374; xor.BW src,dst (m16 #3 m32 #3)
10375(binary-arith-src-dst xor G (f-0-4 #x8) (f-4-3 4) #x1 #x9 xor-sem)
10376
10377;-------------------------------------------------------------
10378; Widening
10379;-------------------------------------------------------------
10380
10381(define-pmacro (exts-sem smode dmode src dst)
10382 (set dst (ext dmode (trunc smode src)))
10383)
10384(define-pmacro (extz-sem smode dmode src dst)
10385 (set dst (zext dmode (trunc smode src)))
10386)
10387
10388; exts.b dst for m16c
10389(ext16-defn QI HI .b 0 exts (f-0-4 7) (f-4-3 6) (f-8-4 6) exts-sem)
10390
10391; exts.w r0 for m16c
10392(dni exts16.w-r0
10393 "exts.w r0"
10394 ((machine 16))
10395 "exts.w r0"
10396 (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 3))
10397 (exts-sem HI SI R0 R2R0)
10398 ())
10399
10400; exts.size dst for m32c
10401(ext32-defn QI HI .b 0 exts (f-0-4 #xC) (f-10-2 1) (f-12-4 #xE) exts-sem)
10402(ext32-defn HI SI .w 1 exts (f-0-4 #xC) (f-10-2 1) (f-12-4 #xE) exts-sem)
10403; exts.b src,dst for m32c
10404(ext32-binary-defn exts .b #x1 #x7 exts-sem)
10405
10406; extz.b src,dst for m32c
10407(ext32-binary-defn extz "" #x1 #xB extz-sem)
10408
10409;-------------------------------------------------------------
10410; Indirect
10411;-------------------------------------------------------------
10412
10413; TODO semantics
10414(dni srcind "SRC-INDIRECT" ((machine 32))
10415 ("src-indirect")
10416 (+ (f-0-4 4) (f-4-4 1))
10417 (set (reg h-src-indirect) 1)
10418 ())
10419
10420(dni destind "DEST-INDIRECT" ((machine 32))
10421 ("dest-indirect")
10422 (+ (f-0-4 0) (f-4-4 9))
10423 (set (reg h-dst-indirect) 1)
10424 ())
10425
10426(dni srcdestind "SRC-DEST-INDIRECT" ((machine 32))
10427 ("src-dest-indirect")
10428 (+ (f-0-4 4) (f-4-4 9))
10429 (sequence () (set (reg h-src-indirect) 1) (set (reg h-dst-indirect) 1))
10430 ())
GDB Binutils - Deliverables
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