[deliverable/linux.git] / drivers / ata / pata_efar.c

/*
 *    pata_efar.c - EFAR PIIX clone controller driver
 *
 *	(C) 2005 Red Hat
 *	(C) 2009-2010 Bartlomiej Zolnierkiewicz
 *
 *    Some parts based on ata_piix.c by Jeff Garzik and others.
 *
 *    The EFAR is a PIIX4 clone with UDMA66 support. Unlike the later
 *    Intel ICH controllers the EFAR widened the UDMA mode register bits
 *    and doesn't require the funky clock selection.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include <linux/ata.h>

#define DRV_NAME	"pata_efar"
#define DRV_VERSION	"0.4.5"

/**
 *	efar_pre_reset	-	Enable bits
 *	@link: ATA link
 *	@deadline: deadline jiffies for the operation
 *
 *	Perform cable detection for the EFAR ATA interface. This is
 *	different to the PIIX arrangement
 */

static int efar_pre_reset(struct ata_link *link, unsigned long deadline)
{
	static const struct pci_bits efar_enable_bits[] = {
		{ 0x41U, 1U, 0x80UL, 0x80UL },	/* port 0 */
		{ 0x43U, 1U, 0x80UL, 0x80UL },	/* port 1 */
	};
	struct ata_port *ap = link->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	if (!pci_test_config_bits(pdev, &efar_enable_bits[ap->port_no]))
		return -ENOENT;

	return ata_sff_prereset(link, deadline);
}

/**
 *	efar_cable_detect	-	check for 40/80 pin
 *	@ap: Port
 *
 *	Perform cable detection for the EFAR ATA interface. This is
 *	different to the PIIX arrangement
 */

static int efar_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 tmp;

	pci_read_config_byte(pdev, 0x47, &tmp);
	if (tmp & (2 >> ap->port_no))
		return ATA_CBL_PATA40;
	return ATA_CBL_PATA80;
}

static DEFINE_SPINLOCK(efar_lock);

/**
 *	efar_set_piomode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device to program
 *
 *	Set PIO mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void efar_set_piomode (struct ata_port *ap, struct ata_device *adev)
{
	unsigned int pio	= adev->pio_mode - XFER_PIO_0;
	struct pci_dev *dev	= to_pci_dev(ap->host->dev);
	unsigned int master_port = ap->port_no ? 0x42 : 0x40;
	unsigned long flags;
	u16 master_data;
	u8 udma_enable;
	int control = 0;

	/*
	 *	See Intel Document 298600-004 for the timing programing rules
	 *	for PIIX/ICH. The EFAR is a clone so very similar
	 */

	static const	 /* ISP  RTC */
	u8 timings[][2]	= { { 0, 0 },
			    { 0, 0 },
			    { 1, 0 },
			    { 2, 1 },
			    { 2, 3 }, };

	if (pio > 1)
		control |= 1;	/* TIME */
	if (ata_pio_need_iordy(adev))	/* PIO 3/4 require IORDY */
		control |= 2;	/* IE */
	/* Intel specifies that the prefetch/posting is for disk only */
	if (adev->class == ATA_DEV_ATA)
		control |= 4;	/* PPE */

	spin_lock_irqsave(&efar_lock, flags);

	pci_read_config_word(dev, master_port, &master_data);

	/* Set PPE, IE, and TIME as appropriate */
	if (adev->devno == 0) {
		master_data &= 0xCCF0;
		master_data |= control;
		master_data |= (timings[pio][0] << 12) |
			(timings[pio][1] << 8);
	} else {
		int shift = 4 * ap->port_no;
		u8 slave_data;

		master_data &= 0xFF0F;
		master_data |= (control << 4);

		/* Slave timing in separate register */
		pci_read_config_byte(dev, 0x44, &slave_data);
		slave_data &= ap->port_no ? 0x0F : 0xF0;
		slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << shift;
		pci_write_config_byte(dev, 0x44, slave_data);
	}

	master_data |= 0x4000;	/* Ensure SITRE is set */
	pci_write_config_word(dev, master_port, master_data);

	pci_read_config_byte(dev, 0x48, &udma_enable);
	udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
	pci_write_config_byte(dev, 0x48, udma_enable);
	spin_unlock_irqrestore(&efar_lock, flags);
}

/**
 *	efar_set_dmamode - Initialize host controller PATA DMA timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device to program
 *
 *	Set UDMA/MWDMA mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void efar_set_dmamode (struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *dev	= to_pci_dev(ap->host->dev);
	u8 master_port		= ap->port_no ? 0x42 : 0x40;
	u16 master_data;
	u8 speed		= adev->dma_mode;
	int devid		= adev->devno + 2 * ap->port_no;
	unsigned long flags;
	u8 udma_enable;

	static const	 /* ISP  RTC */
	u8 timings[][2]	= { { 0, 0 },
			    { 0, 0 },
			    { 1, 0 },
			    { 2, 1 },
			    { 2, 3 }, };

	spin_lock_irqsave(&efar_lock, flags);

	pci_read_config_word(dev, master_port, &master_data);
	pci_read_config_byte(dev, 0x48, &udma_enable);

	if (speed >= XFER_UDMA_0) {
		unsigned int udma	= adev->dma_mode - XFER_UDMA_0;
		u16 udma_timing;

		udma_enable |= (1 << devid);

		/* Load the UDMA mode number */
		pci_read_config_word(dev, 0x4A, &udma_timing);
		udma_timing &= ~(7 << (4 * devid));
		udma_timing |= udma << (4 * devid);
		pci_write_config_word(dev, 0x4A, udma_timing);
	} else {
		/*
		 * MWDMA is driven by the PIO timings. We must also enable
		 * IORDY unconditionally along with TIME1. PPE has already
		 * been set when the PIO timing was set.
		 */
		unsigned int mwdma	= adev->dma_mode - XFER_MW_DMA_0;
		unsigned int control;
		u8 slave_data;
		const unsigned int needed_pio[3] = {
			XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
		};
		int pio = needed_pio[mwdma] - XFER_PIO_0;

		control = 3;	/* IORDY|TIME1 */

		/* If the drive MWDMA is faster than it can do PIO then
		   we must force PIO into PIO0 */

		if (adev->pio_mode < needed_pio[mwdma])
			/* Enable DMA timing only */
			control |= 8;	/* PIO cycles in PIO0 */

		if (adev->devno) {	/* Slave */
			master_data &= 0xFF4F;  /* Mask out IORDY|TIME1|DMAONLY */
			master_data |= control << 4;
			pci_read_config_byte(dev, 0x44, &slave_data);
			slave_data &= ap->port_no ? 0x0F : 0xF0;
			/* Load the matching timing */
			slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
			pci_write_config_byte(dev, 0x44, slave_data);
		} else { 	/* Master */
			master_data &= 0xCCF4;	/* Mask out IORDY|TIME1|DMAONLY
						   and master timing bits */
			master_data |= control;
			master_data |=
				(timings[pio][0] << 12) |
				(timings[pio][1] << 8);
		}
		udma_enable &= ~(1 << devid);
		pci_write_config_word(dev, master_port, master_data);
	}
	pci_write_config_byte(dev, 0x48, udma_enable);
	spin_unlock_irqrestore(&efar_lock, flags);
}

static struct scsi_host_template efar_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations efar_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.cable_detect		= efar_cable_detect,
	.set_piomode		= efar_set_piomode,
	.set_dmamode		= efar_set_dmamode,
	.prereset		= efar_pre_reset,
};


/**
 *	efar_init_one - Register EFAR ATA PCI device with kernel services
 *	@pdev: PCI device to register
 *	@ent: Entry in efar_pci_tbl matching with @pdev
 *
 *	Called from kernel PCI layer.
 *
 *	LOCKING:
 *	Inherited from PCI layer (may sleep).
 *
 *	RETURNS:
 *	Zero on success, or -ERRNO value.
 */

static int efar_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static const struct ata_port_info info = {
		.flags		= ATA_FLAG_SLAVE_POSS,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA12_ONLY,
		.udma_mask 	= ATA_UDMA4,
		.port_ops	= &efar_ops,
	};
	const struct ata_port_info *ppi[] = { &info, &info };

	ata_print_version_once(&pdev->dev, DRV_VERSION);

	return ata_pci_bmdma_init_one(pdev, ppi, &efar_sht, NULL,
				      ATA_HOST_PARALLEL_SCAN);
}

static const struct pci_device_id efar_pci_tbl[] = {
	{ PCI_VDEVICE(EFAR, 0x9130), },

	{ }	/* terminate list */
};

static struct pci_driver efar_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= efar_pci_tbl,
	.probe			= efar_init_one,
	.remove			= ata_pci_remove_one,
#ifdef CONFIG_PM_SLEEP
	.suspend		= ata_pci_device_suspend,
	.resume			= ata_pci_device_resume,
#endif
};

module_pci_driver(efar_pci_driver);

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("SCSI low-level driver for EFAR PIIX clones");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, efar_pci_tbl);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_efar.c - EFAR PIIX clone controller driver
	3	*
ab771630	4	* (C) 2005 Red Hat
73e2e3d0	5	* (C) 2009-2010 Bartlomiej Zolnierkiewicz
669a5db4 JG	6	*
	7	* Some parts based on ata_piix.c by Jeff Garzik and others.
	8	*
	9	* The EFAR is a PIIX4 clone with UDMA66 support. Unlike the later
	10	* Intel ICH controllers the EFAR widened the UDMA mode register bits
	11	* and doesn't require the funky clock selection.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/module.h>
	16	#include <linux/pci.h>
669a5db4 JG	17	#include <linux/blkdev.h>
	18	#include <linux/delay.h>
	19	#include <linux/device.h>
	20	#include <scsi/scsi_host.h>
	21	#include <linux/libata.h>
	22	#include <linux/ata.h>
	23
	24	#define DRV_NAME "pata_efar"
5f33b3bc	25	#define DRV_VERSION "0.4.5"
669a5db4 JG	26
669a5db4 JG	27	/**
6bfed3fb	28	* efar_pre_reset - Enable bits
cc0680a5	29	* @link: ATA link
d4b2bab4	30	* @deadline: deadline jiffies for the operation
669a5db4 JG	31	*
	32	* Perform cable detection for the EFAR ATA interface. This is
	33	* different to the PIIX arrangement
	34	*/
	35
cc0680a5	36	static int efar_pre_reset(struct ata_link *link, unsigned long deadline)
669a5db4 JG	37	{
	38	static const struct pci_bits efar_enable_bits[] = {
	39	{ 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
	40	{ 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
	41	};
cc0680a5	42	struct ata_port *ap = link->ap;
669a5db4	43	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
669a5db4	44
c961922b AC	45	if (!pci_test_config_bits(pdev, &efar_enable_bits[ap->port_no]))
	46	return -ENOENT;
	47
9363c382	48	return ata_sff_prereset(link, deadline);
669a5db4 JG	49	}
669a5db4 JG	50
6bfed3fb AC	51	/**
	52	* efar_cable_detect - check for 40/80 pin
	53	* @ap: Port
	54	*
	55	* Perform cable detection for the EFAR ATA interface. This is
	56	* different to the PIIX arrangement
	57	*/
	58
	59	static int efar_cable_detect(struct ata_port *ap)
	60	{
	61	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	62	u8 tmp;
	63
	64	pci_read_config_byte(pdev, 0x47, &tmp);
	65	if (tmp & (2 >> ap->port_no))
	66	return ATA_CBL_PATA40;
	67	return ATA_CBL_PATA80;
	68	}
	69
303f1a76 BZ	70	static DEFINE_SPINLOCK(efar_lock);
303f1a76 BZ	71
669a5db4 JG	72	/**
	73	* efar_set_piomode - Initialize host controller PATA PIO timings
	74	* @ap: Port whose timings we are configuring
a0da1914	75	* @adev: Device to program
669a5db4 JG	76	*
	77	* Set PIO mode for device, in host controller PCI config space.
	78	*
	79	* LOCKING:
	80	* None (inherited from caller).
	81	*/
	82
	83	static void efar_set_piomode (struct ata_port ap, struct ata_device adev)
	84	{
	85	unsigned int pio = adev->pio_mode - XFER_PIO_0;
	86	struct pci_dev *dev = to_pci_dev(ap->host->dev);
a0da1914	87	unsigned int master_port = ap->port_no ? 0x42 : 0x40;
303f1a76	88	unsigned long flags;
a0da1914	89	u16 master_data;
303f1a76	90	u8 udma_enable;
669a5db4 JG	91	int control = 0;
	92
	93	/*
	94	* See Intel Document 298600-004 for the timing programing rules
	95	* for PIIX/ICH. The EFAR is a clone so very similar
	96	*/
	97
	98	static const /* ISP RTC */
	99	u8 timings[][2] = { { 0, 0 },
	100	{ 0, 0 },
	101	{ 1, 0 },
	102	{ 2, 1 },
	103	{ 2, 3 }, };
	104
5f33b3bc SS	105	if (pio > 1)
5f33b3bc SS	106	control \|= 1; /* TIME */
669a5db4	107	if (ata_pio_need_iordy(adev)) /* PIO 3/4 require IORDY */
5f33b3bc SS	108	control \|= 2; /* IE */
5f33b3bc SS	109	/* Intel specifies that the prefetch/posting is for disk only */
669a5db4	110	if (adev->class == ATA_DEV_ATA)
5f33b3bc	111	control \|= 4; /* PPE */
669a5db4	112
303f1a76 BZ	113	spin_lock_irqsave(&efar_lock, flags);
303f1a76 BZ	114
a0da1914	115	pci_read_config_word(dev, master_port, &master_data);
669a5db4	116
5f33b3bc	117	/* Set PPE, IE, and TIME as appropriate */
669a5db4	118	if (adev->devno == 0) {
a0da1914 BZ	119	master_data &= 0xCCF0;
	120	master_data \|= control;
	121	master_data \|= (timings[pio][0] << 12) \|
669a5db4 JG	122	(timings[pio][1] << 8);
	123	} else {
	124	int shift = 4 * ap->port_no;
	125	u8 slave_data;
	126
a0da1914 BZ	127	master_data &= 0xFF0F;
a0da1914 BZ	128	master_data \|= (control << 4);
669a5db4	129
1967b7ff	130	/* Slave timing in separate register */
669a5db4	131	pci_read_config_byte(dev, 0x44, &slave_data);
f79ff926	132	slave_data &= ap->port_no ? 0x0F : 0xF0;
669a5db4 JG	133	slave_data \|= ((timings[pio][0] << 2) \| timings[pio][1]) << shift;
	134	pci_write_config_byte(dev, 0x44, slave_data);
	135	}
	136
a0da1914 BZ	137	master_data \|= 0x4000; /* Ensure SITRE is set */
a0da1914 BZ	138	pci_write_config_word(dev, master_port, master_data);
303f1a76 BZ	139
	140	pci_read_config_byte(dev, 0x48, &udma_enable);
	141	udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
	142	pci_write_config_byte(dev, 0x48, udma_enable);
	143	spin_unlock_irqrestore(&efar_lock, flags);
669a5db4 JG	144	}
	145
	146	/**
	147	* efar_set_dmamode - Initialize host controller PATA DMA timings
	148	* @ap: Port whose timings we are configuring
	149	* @adev: Device to program
	150	*
	151	* Set UDMA/MWDMA mode for device, in host controller PCI config space.
	152	*
	153	* LOCKING:
	154	* None (inherited from caller).
	155	*/
	156
	157	static void efar_set_dmamode (struct ata_port ap, struct ata_device adev)
	158	{
	159	struct pci_dev *dev = to_pci_dev(ap->host->dev);
	160	u8 master_port = ap->port_no ? 0x42 : 0x40;
	161	u16 master_data;
	162	u8 speed = adev->dma_mode;
	163	int devid = adev->devno + 2 * ap->port_no;
303f1a76	164	unsigned long flags;
669a5db4 JG	165	u8 udma_enable;
	166
	167	static const /* ISP RTC */
	168	u8 timings[][2] = { { 0, 0 },
	169	{ 0, 0 },
	170	{ 1, 0 },
	171	{ 2, 1 },
	172	{ 2, 3 }, };
	173
303f1a76 BZ	174	spin_lock_irqsave(&efar_lock, flags);
303f1a76 BZ	175
669a5db4 JG	176	pci_read_config_word(dev, master_port, &master_data);
	177	pci_read_config_byte(dev, 0x48, &udma_enable);
	178
	179	if (speed >= XFER_UDMA_0) {
	180	unsigned int udma = adev->dma_mode - XFER_UDMA_0;
	181	u16 udma_timing;
	182
	183	udma_enable \|= (1 << devid);
	184
	185	/* Load the UDMA mode number */
	186	pci_read_config_word(dev, 0x4A, &udma_timing);
	187	udma_timing &= ~(7 << (4 * devid));
	188	udma_timing \|= udma << (4 * devid);
	189	pci_write_config_word(dev, 0x4A, udma_timing);
	190	} else {
	191	/*
	192	* MWDMA is driven by the PIO timings. We must also enable
	193	* IORDY unconditionally along with TIME1. PPE has already
	194	* been set when the PIO timing was set.
	195	*/
	196	unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
	197	unsigned int control;
	198	u8 slave_data;
	199	const unsigned int needed_pio[3] = {
	200	XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
	201	};
	202	int pio = needed_pio[mwdma] - XFER_PIO_0;
	203
	204	control = 3; /* IORDY\|TIME1 */
	205
	206	/* If the drive MWDMA is faster than it can do PIO then
	207	we must force PIO into PIO0 */
	208
	209	if (adev->pio_mode < needed_pio[mwdma])
	210	/* Enable DMA timing only */
	211	control \|= 8; /* PIO cycles in PIO0 */
	212
	213	if (adev->devno) { /* Slave */
	214	master_data &= 0xFF4F; /* Mask out IORDY\|TIME1\|DMAONLY */
	215	master_data \|= control << 4;
	216	pci_read_config_byte(dev, 0x44, &slave_data);
dd221f9c	217	slave_data &= ap->port_no ? 0x0F : 0xF0;
669a5db4 JG	218	/* Load the matching timing */
	219	slave_data \|= ((timings[pio][0] << 2) \| timings[pio][1]) << (ap->port_no ? 4 : 0);
	220	pci_write_config_byte(dev, 0x44, slave_data);
	221	} else { /* Master */
	222	master_data &= 0xCCF4; /* Mask out IORDY\|TIME1\|DMAONLY
	223	and master timing bits */
	224	master_data \|= control;
	225	master_data \|=
	226	(timings[pio][0] << 12) \|
	227	(timings[pio][1] << 8);
	228	}
	229	udma_enable &= ~(1 << devid);
	230	pci_write_config_word(dev, master_port, master_data);
	231	}
	232	pci_write_config_byte(dev, 0x48, udma_enable);
303f1a76	233	spin_unlock_irqrestore(&efar_lock, flags);
669a5db4 JG	234	}
	235
	236	static struct scsi_host_template efar_sht = {
68d1d07b	237	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	238	};
669a5db4 JG	239
029cfd6b TH	240	static struct ata_port_operations efar_ops = {
	241	.inherits = &ata_bmdma_port_ops,
	242	.cable_detect = efar_cable_detect,
669a5db4 JG	243	.set_piomode = efar_set_piomode,
669a5db4 JG	244	.set_dmamode = efar_set_dmamode,
a1efdaba	245	.prereset = efar_pre_reset,
669a5db4 JG	246	};
	247
	248
	249	/**
	250	* efar_init_one - Register EFAR ATA PCI device with kernel services
	251	* @pdev: PCI device to register
	252	* @ent: Entry in efar_pci_tbl matching with @pdev
	253	*
	254	* Called from kernel PCI layer.
	255	*
	256	* LOCKING:
	257	* Inherited from PCI layer (may sleep).
	258	*
	259	* RETURNS:
	260	* Zero on success, or -ERRNO value.
	261	*/
	262
	263	static int efar_init_one (struct pci_dev pdev, const struct pci_device_id ent)
	264	{
1626aeb8	265	static const struct ata_port_info info = {
1d2808fd	266	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98	267	.pio_mask = ATA_PIO4,
82563232	268	.mwdma_mask = ATA_MWDMA12_ONLY,
b2a034cf	269	.udma_mask = ATA_UDMA4,
669a5db4 JG	270	.port_ops = &efar_ops,
669a5db4 JG	271	};
73e2e3d0	272	const struct ata_port_info *ppi[] = { &info, &info };
669a5db4	273
06296a1e	274	ata_print_version_once(&pdev->dev, DRV_VERSION);
669a5db4	275
1c5afdf7 TH	276	return ata_pci_bmdma_init_one(pdev, ppi, &efar_sht, NULL,
1c5afdf7 TH	277	ATA_HOST_PARALLEL_SCAN);
669a5db4 JG	278	}
	279
	280	static const struct pci_device_id efar_pci_tbl[] = {
2d2744fc JG	281	{ PCI_VDEVICE(EFAR, 0x9130), },
2d2744fc JG	282
669a5db4 JG	283	{ } /* terminate list */
	284	};
	285
	286	static struct pci_driver efar_pci_driver = {
	287	.name = DRV_NAME,
	288	.id_table = efar_pci_tbl,
	289	.probe = efar_init_one,
	290	.remove = ata_pci_remove_one,
58eb8cd5	291	#ifdef CONFIG_PM_SLEEP
30ced0f0 A	292	.suspend = ata_pci_device_suspend,
30ced0f0 A	293	.resume = ata_pci_device_resume,
438ac6d5	294	#endif
669a5db4 JG	295	};
669a5db4 JG	296
2fc75da0	297	module_pci_driver(efar_pci_driver);
669a5db4 JG	298
	299	MODULE_AUTHOR("Alan Cox");
	300	MODULE_DESCRIPTION("SCSI low-level driver for EFAR PIIX clones");
	301	MODULE_LICENSE("GPL");
	302	MODULE_DEVICE_TABLE(pci, efar_pci_tbl);
	303	MODULE_VERSION(DRV_VERSION);