[deliverable/linux.git] / drivers / bcma / driver_chipcommon.c

/*
 * Broadcom specific AMBA
 * ChipCommon core driver
 *
 * Copyright 2005, Broadcom Corporation
 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
 * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
 *
 * Licensed under the GNU/GPL. See COPYING for details.
 */

#include "bcma_private.h"
#include <linux/bcm47xx_wdt.h>
#include <linux/export.h>
#include <linux/platform_device.h>
#include <linux/bcma/bcma.h>

static void bcma_chipco_serial_init(struct bcma_drv_cc *cc);

static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
					 u32 mask, u32 value)
{
	value &= mask;
	value |= bcma_cc_read32(cc, offset) & ~mask;
	bcma_cc_write32(cc, offset, value);

	return value;
}

u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
{
	if (cc->capabilities & BCMA_CC_CAP_PMU)
		return bcma_pmu_get_alp_clock(cc);

	return 20000000;
}
EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock);

static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
{
	struct bcma_bus *bus = cc->core->bus;
	u32 nb;

	if (cc->capabilities & BCMA_CC_CAP_PMU) {
		if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
			nb = 32;
		else if (cc->core->id.rev < 26)
			nb = 16;
		else
			nb = (cc->core->id.rev >= 37) ? 32 : 24;
	} else {
		nb = 28;
	}
	if (nb == 32)
		return 0xffffffff;
	else
		return (1 << nb) - 1;
}

static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
					      u32 ticks)
{
	struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);

	return bcma_chipco_watchdog_timer_set(cc, ticks);
}

static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
						 u32 ms)
{
	struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
	u32 ticks;

	ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
	return ticks / cc->ticks_per_ms;
}

static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
{
	struct bcma_bus *bus = cc->core->bus;

	if (cc->capabilities & BCMA_CC_CAP_PMU) {
		if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
			/* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP
			 * clock
			 */
			return bcma_chipco_get_alp_clock(cc) / 4000;
		else
			/* based on 32KHz ILP clock */
			return 32;
	} else {
		return bcma_chipco_get_alp_clock(cc) / 1000;
	}
}

int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
{
	struct bcm47xx_wdt wdt = {};
	struct platform_device *pdev;

	wdt.driver_data = cc;
	wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
	wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
	wdt.max_timer_ms =
		bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;

	pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
					     cc->core->bus->num, &wdt,
					     sizeof(wdt));
	if (IS_ERR(pdev))
		return PTR_ERR(pdev);

	cc->watchdog = pdev;

	return 0;
}

static void bcma_core_chipcommon_flash_detect(struct bcma_drv_cc *cc)
{
	struct bcma_bus *bus = cc->core->bus;

	switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
	case BCMA_CC_FLASHT_STSER:
	case BCMA_CC_FLASHT_ATSER:
		bcma_debug(bus, "Found serial flash\n");
		bcma_sflash_init(cc);
		break;
	case BCMA_CC_FLASHT_PARA:
		bcma_debug(bus, "Found parallel flash\n");
		bcma_pflash_init(cc);
		break;
	default:
		bcma_err(bus, "Flash type not supported\n");
	}

	if (cc->core->id.rev == 38 ||
	    bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
		if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
			bcma_debug(bus, "Found NAND flash\n");
			bcma_nflash_init(cc);
		}
	}
}

void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
{
	struct bcma_bus *bus = cc->core->bus;

	if (cc->early_setup_done)
		return;

	spin_lock_init(&cc->gpio_lock);

	if (cc->core->id.rev >= 11)
		cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
	cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
	if (cc->core->id.rev >= 35)
		cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);

	if (cc->capabilities & BCMA_CC_CAP_PMU)
		bcma_pmu_early_init(cc);

	if (IS_BUILTIN(CONFIG_BCM47XX) && bus->hosttype == BCMA_HOSTTYPE_SOC)
		bcma_chipco_serial_init(cc);

	if (bus->hosttype == BCMA_HOSTTYPE_SOC)
		bcma_core_chipcommon_flash_detect(cc);

	cc->early_setup_done = true;
}

void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
{
	u32 leddc_on = 10;
	u32 leddc_off = 90;

	if (cc->setup_done)
		return;

	bcma_core_chipcommon_early_init(cc);

	if (cc->core->id.rev >= 20) {
		u32 pullup = 0, pulldown = 0;

		if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) {
			pullup = 0x402e0;
			pulldown = 0x20500;
		}

		bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup);
		bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown);
	}

	if (cc->capabilities & BCMA_CC_CAP_PMU)
		bcma_pmu_init(cc);
	if (cc->capabilities & BCMA_CC_CAP_PCTL)
		bcma_err(cc->core->bus, "Power control not implemented!\n");

	if (cc->core->id.rev >= 16) {
		if (cc->core->bus->sprom.leddc_on_time &&
		    cc->core->bus->sprom.leddc_off_time) {
			leddc_on = cc->core->bus->sprom.leddc_on_time;
			leddc_off = cc->core->bus->sprom.leddc_off_time;
		}
		bcma_cc_write32(cc, BCMA_CC_GPIOTIMER,
			((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
			 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
	}
	cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);

	cc->setup_done = true;
}

/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
{
	u32 maxt;

	maxt = bcma_chipco_watchdog_get_max_timer(cc);
	if (cc->capabilities & BCMA_CC_CAP_PMU) {
		if (ticks == 1)
			ticks = 2;
		else if (ticks > maxt)
			ticks = maxt;
		bcma_pmu_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
	} else {
		struct bcma_bus *bus = cc->core->bus;

		if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4707 &&
		    bus->chipinfo.id != BCMA_CHIP_ID_BCM47094 &&
		    bus->chipinfo.id != BCMA_CHIP_ID_BCM53018)
			bcma_core_set_clockmode(cc->core,
						ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC);

		if (ticks > maxt)
			ticks = maxt;
		/* instant NMI */
		bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
	}
	return ticks;
}

void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
{
	bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value);
}

u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask)
{
	return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask;
}

u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask)
{
	return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask;
}

u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
{
	unsigned long flags;
	u32 res;

	spin_lock_irqsave(&cc->gpio_lock, flags);
	res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
	spin_unlock_irqrestore(&cc->gpio_lock, flags);

	return res;
}
EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);

u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
{
	unsigned long flags;
	u32 res;

	spin_lock_irqsave(&cc->gpio_lock, flags);
	res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
	spin_unlock_irqrestore(&cc->gpio_lock, flags);

	return res;
}
EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);

/*
 * If the bit is set to 0, chipcommon controlls this GPIO,
 * if the bit is set to 1, it is used by some part of the chip and not our code.
 */
u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
{
	unsigned long flags;
	u32 res;

	spin_lock_irqsave(&cc->gpio_lock, flags);
	res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
	spin_unlock_irqrestore(&cc->gpio_lock, flags);

	return res;
}
EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);

u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
{
	unsigned long flags;
	u32 res;

	spin_lock_irqsave(&cc->gpio_lock, flags);
	res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
	spin_unlock_irqrestore(&cc->gpio_lock, flags);

	return res;
}

u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
{
	unsigned long flags;
	u32 res;

	spin_lock_irqsave(&cc->gpio_lock, flags);
	res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
	spin_unlock_irqrestore(&cc->gpio_lock, flags);

	return res;
}

u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value)
{
	unsigned long flags;
	u32 res;

	if (cc->core->id.rev < 20)
		return 0;

	spin_lock_irqsave(&cc->gpio_lock, flags);
	res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value);
	spin_unlock_irqrestore(&cc->gpio_lock, flags);

	return res;
}

u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value)
{
	unsigned long flags;
	u32 res;

	if (cc->core->id.rev < 20)
		return 0;

	spin_lock_irqsave(&cc->gpio_lock, flags);
	res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value);
	spin_unlock_irqrestore(&cc->gpio_lock, flags);

	return res;
}

static void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
{
#if IS_BUILTIN(CONFIG_BCM47XX)
	unsigned int irq;
	u32 baud_base;
	u32 i;
	unsigned int ccrev = cc->core->id.rev;
	struct bcma_serial_port *ports = cc->serial_ports;

	if (ccrev >= 11 && ccrev != 15) {
		baud_base = bcma_chipco_get_alp_clock(cc);
		if (ccrev >= 21) {
			/* Turn off UART clock before switching clocksource. */
			bcma_cc_write32(cc, BCMA_CC_CORECTL,
				       bcma_cc_read32(cc, BCMA_CC_CORECTL)
				       & ~BCMA_CC_CORECTL_UARTCLKEN);
		}
		/* Set the override bit so we don't divide it */
		bcma_cc_write32(cc, BCMA_CC_CORECTL,
			       bcma_cc_read32(cc, BCMA_CC_CORECTL)
			       | BCMA_CC_CORECTL_UARTCLK0);
		if (ccrev >= 21) {
			/* Re-enable the UART clock. */
			bcma_cc_write32(cc, BCMA_CC_CORECTL,
				       bcma_cc_read32(cc, BCMA_CC_CORECTL)
				       | BCMA_CC_CORECTL_UARTCLKEN);
		}
	} else {
		bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n",
			 ccrev);
		return;
	}

	irq = bcma_core_irq(cc->core, 0);

	/* Determine the registers of the UARTs */
	cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
	for (i = 0; i < cc->nr_serial_ports; i++) {
		ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA +
				(i * 256);
		ports[i].irq = irq;
		ports[i].baud_base = baud_base;
		ports[i].reg_shift = 0;
	}
#endif /* CONFIG_BCM47XX */
}
Commit	Line	Data
8369ae33 RM	1	/*
	2	* Broadcom specific AMBA
	3	* ChipCommon core driver
	4	*
	5	* Copyright 2005, Broadcom Corporation
eb032b98	6	* Copyright 2006, 2007, Michael Buesch <m@bues.ch>
56fd5f07	7	* Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
8369ae33 RM	8	*
	9	* Licensed under the GNU/GPL. See COPYING for details.
	10	*/
	11
	12	#include "bcma_private.h"
a22a3114	13	#include <linux/bcm47xx_wdt.h>
44a8e377	14	#include <linux/export.h>
a4855f39	15	#include <linux/platform_device.h>
8369ae33 RM	16	#include <linux/bcma/bcma.h>
8369ae33 RM	17
4c81acab RM	18	static void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
4c81acab RM	19
8369ae33 RM	20	static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
	21	u32 mask, u32 value)
	22	{
	23	value &= mask;
	24	value \|= bcma_cc_read32(cc, offset) & ~mask;
	25	bcma_cc_write32(cc, offset, value);
	26
	27	return value;
	28	}
	29
6951618b	30	u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
56fd5f07 HM	31	{
56fd5f07 HM	32	if (cc->capabilities & BCMA_CC_CAP_PMU)
5b5ac414	33	return bcma_pmu_get_alp_clock(cc);
56fd5f07 HM	34
	35	return 20000000;
	36	}
6951618b	37	EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock);
56fd5f07	38
f6354c8c HM	39	static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
	40	{
	41	struct bcma_bus *bus = cc->core->bus;
	42	u32 nb;
	43
	44	if (cc->capabilities & BCMA_CC_CAP_PMU) {
	45	if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
	46	nb = 32;
	47	else if (cc->core->id.rev < 26)
	48	nb = 16;
	49	else
	50	nb = (cc->core->id.rev >= 37) ? 32 : 24;
	51	} else {
	52	nb = 28;
	53	}
	54	if (nb == 32)
	55	return 0xffffffff;
	56	else
	57	return (1 << nb) - 1;
	58	}
	59
a22a3114 HM	60	static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
	61	u32 ticks)
	62	{
	63	struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
	64
	65	return bcma_chipco_watchdog_timer_set(cc, ticks);
	66	}
	67
	68	static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
	69	u32 ms)
	70	{
	71	struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
	72	u32 ticks;
	73
	74	ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
	75	return ticks / cc->ticks_per_ms;
	76	}
	77
	78	static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
	79	{
	80	struct bcma_bus *bus = cc->core->bus;
	81
	82	if (cc->capabilities & BCMA_CC_CAP_PMU) {
	83	if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
d0f66df5 OFM	84	/* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP
	85	* clock
	86	*/
5b5ac414	87	return bcma_chipco_get_alp_clock(cc) / 4000;
a22a3114 HM	88	else
	89	/* based on 32KHz ILP clock */
	90	return 32;
	91	} else {
5b5ac414	92	return bcma_chipco_get_alp_clock(cc) / 1000;
a22a3114 HM	93	}
a22a3114 HM	94	}
f6354c8c	95
a4855f39 HM	96	int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
	97	{
	98	struct bcm47xx_wdt wdt = {};
	99	struct platform_device *pdev;
	100
	101	wdt.driver_data = cc;
	102	wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
	103	wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
d0f66df5 OFM	104	wdt.max_timer_ms =
d0f66df5 OFM	105	bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
a4855f39 HM	106
	107	pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
	108	cc->core->bus->num, &wdt,
	109	sizeof(wdt));
	110	if (IS_ERR(pdev))
	111	return PTR_ERR(pdev);
	112
	113	cc->watchdog = pdev;
	114
	115	return 0;
	116	}
	117
0ea6f0c5 RM	118	static void bcma_core_chipcommon_flash_detect(struct bcma_drv_cc *cc)
	119	{
	120	struct bcma_bus *bus = cc->core->bus;
	121
	122	switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
	123	case BCMA_CC_FLASHT_STSER:
	124	case BCMA_CC_FLASHT_ATSER:
	125	bcma_debug(bus, "Found serial flash\n");
	126	bcma_sflash_init(cc);
	127	break;
	128	case BCMA_CC_FLASHT_PARA:
	129	bcma_debug(bus, "Found parallel flash\n");
	130	bcma_pflash_init(cc);
	131	break;
	132	default:
	133	bcma_err(bus, "Flash type not supported\n");
	134	}
	135
	136	if (cc->core->id.rev == 38 \|\|
	137	bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
	138	if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
	139	bcma_debug(bus, "Found NAND flash\n");
	140	bcma_nflash_init(cc);
	141	}
	142	}
	143	}
	144
49655bb8	145	void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
8369ae33	146	{
4c81acab RM	147	struct bcma_bus *bus = cc->core->bus;
4c81acab RM	148
49655bb8	149	if (cc->early_setup_done)
517f43e5 HM	150	return;
517f43e5 HM	151
ef85fb28 HM	152	spin_lock_init(&cc->gpio_lock);
ef85fb28 HM	153
8369ae33 RM	154	if (cc->core->id.rev >= 11)
	155	cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
	156	cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
	157	if (cc->core->id.rev >= 35)
	158	cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
	159
49655bb8 HM	160	if (cc->capabilities & BCMA_CC_CAP_PMU)
	161	bcma_pmu_early_init(cc);
	162
4c81acab RM	163	if (IS_BUILTIN(CONFIG_BCM47XX) && bus->hosttype == BCMA_HOSTTYPE_SOC)
	164	bcma_chipco_serial_init(cc);
	165
0ea6f0c5 RM	166	if (bus->hosttype == BCMA_HOSTTYPE_SOC)
	167	bcma_core_chipcommon_flash_detect(cc);
	168
49655bb8 HM	169	cc->early_setup_done = true;
	170	}
	171
	172	void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
	173	{
	174	u32 leddc_on = 10;
	175	u32 leddc_off = 90;
	176
	177	if (cc->setup_done)
	178	return;
	179
	180	bcma_core_chipcommon_early_init(cc);
	181
1073e4ee	182	if (cc->core->id.rev >= 20) {
88f9b65d RM	183	u32 pullup = 0, pulldown = 0;
	184
	185	if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) {
	186	pullup = 0x402e0;
	187	pulldown = 0x20500;
	188	}
	189
	190	bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup);
	191	bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown);
1073e4ee	192	}
8369ae33 RM	193
	194	if (cc->capabilities & BCMA_CC_CAP_PMU)
	195	bcma_pmu_init(cc);
	196	if (cc->capabilities & BCMA_CC_CAP_PCTL)
3d9d8af3	197	bcma_err(cc->core->bus, "Power control not implemented!\n");
18dfa495 RM	198
	199	if (cc->core->id.rev >= 16) {
	200	if (cc->core->bus->sprom.leddc_on_time &&
	201	cc->core->bus->sprom.leddc_off_time) {
	202	leddc_on = cc->core->bus->sprom.leddc_on_time;
	203	leddc_off = cc->core->bus->sprom.leddc_off_time;
	204	}
	205	bcma_cc_write32(cc, BCMA_CC_GPIOTIMER,
	206	((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) \|
	207	(leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
	208	}
a22a3114	209	cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
517f43e5 HM	210
517f43e5 HM	211	cc->setup_done = true;
8369ae33 RM	212	}
	213
	214	/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
a22a3114	215	u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
8369ae33	216	{
f6354c8c	217	u32 maxt;
f6354c8c HM	218
	219	maxt = bcma_chipco_watchdog_get_max_timer(cc);
	220	if (cc->capabilities & BCMA_CC_CAP_PMU) {
	221	if (ticks == 1)
	222	ticks = 2;
	223	else if (ticks > maxt)
	224	ticks = maxt;
b3c47afb	225	bcma_pmu_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
f6354c8c	226	} else {
68fcd245 RM	227	struct bcma_bus *bus = cc->core->bus;
	228
	229	if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4707 &&
61dba73c	230	bus->chipinfo.id != BCMA_CHIP_ID_BCM47094 &&
68fcd245 RM	231	bus->chipinfo.id != BCMA_CHIP_ID_BCM53018)
	232	bcma_core_set_clockmode(cc->core,
	233	ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC);
	234
f6354c8c HM	235	if (ticks > maxt)
	236	ticks = maxt;
	237	/* instant NMI */
	238	bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
	239	}
a22a3114	240	return ticks;
8369ae33 RM	241	}
	242
	243	void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
	244	{
	245	bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value);
	246	}
	247
	248	u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask)
	249	{
	250	return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask;
	251	}
	252
	253	u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask)
	254	{
	255	return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask;
	256	}
	257
	258	u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
	259	{
ef85fb28 HM	260	unsigned long flags;
	261	u32 res;
	262
	263	spin_lock_irqsave(&cc->gpio_lock, flags);
	264	res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
	265	spin_unlock_irqrestore(&cc->gpio_lock, flags);
	266
	267	return res;
8369ae33	268	}
ca84a6c5	269	EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);
8369ae33 RM	270
	271	u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
	272	{
ef85fb28 HM	273	unsigned long flags;
	274	u32 res;
	275
	276	spin_lock_irqsave(&cc->gpio_lock, flags);
	277	res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
	278	spin_unlock_irqrestore(&cc->gpio_lock, flags);
	279
	280	return res;
8369ae33	281	}
ca84a6c5	282	EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);
8369ae33	283
3e8bb507 HM	284	/*
	285	* If the bit is set to 0, chipcommon controlls this GPIO,
	286	* if the bit is set to 1, it is used by some part of the chip and not our code.
	287	*/
8369ae33 RM	288	u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
8369ae33 RM	289	{
ef85fb28 HM	290	unsigned long flags;
	291	u32 res;
	292
	293	spin_lock_irqsave(&cc->gpio_lock, flags);
	294	res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
	295	spin_unlock_irqrestore(&cc->gpio_lock, flags);
	296
	297	return res;
8369ae33 RM	298	}
	299	EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
	300
	301	u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
	302	{
ef85fb28 HM	303	unsigned long flags;
	304	u32 res;
	305
	306	spin_lock_irqsave(&cc->gpio_lock, flags);
	307	res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
	308	spin_unlock_irqrestore(&cc->gpio_lock, flags);
	309
	310	return res;
8369ae33 RM	311	}
	312
	313	u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
	314	{
ef85fb28 HM	315	unsigned long flags;
	316	u32 res;
	317
	318	spin_lock_irqsave(&cc->gpio_lock, flags);
	319	res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
	320	spin_unlock_irqrestore(&cc->gpio_lock, flags);
	321
	322	return res;
8369ae33	323	}
e3afe0e5	324
ea3488f4 HM	325	u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value)
	326	{
	327	unsigned long flags;
	328	u32 res;
	329
	330	if (cc->core->id.rev < 20)
	331	return 0;
	332
	333	spin_lock_irqsave(&cc->gpio_lock, flags);
	334	res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value);
	335	spin_unlock_irqrestore(&cc->gpio_lock, flags);
	336
	337	return res;
	338	}
	339
	340	u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value)
	341	{
	342	unsigned long flags;
	343	u32 res;
	344
	345	if (cc->core->id.rev < 20)
	346	return 0;
	347
	348	spin_lock_irqsave(&cc->gpio_lock, flags);
	349	res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value);
	350	spin_unlock_irqrestore(&cc->gpio_lock, flags);
	351
	352	return res;
8369ae33	353	}
e3afe0e5	354
4c81acab	355	static void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
e3afe0e5	356	{
4c81acab	357	#if IS_BUILTIN(CONFIG_BCM47XX)
e3afe0e5 HM	358	unsigned int irq;
	359	u32 baud_base;
	360	u32 i;
	361	unsigned int ccrev = cc->core->id.rev;
	362	struct bcma_serial_port *ports = cc->serial_ports;
	363
	364	if (ccrev >= 11 && ccrev != 15) {
5b5ac414	365	baud_base = bcma_chipco_get_alp_clock(cc);
e3afe0e5 HM	366	if (ccrev >= 21) {
	367	/* Turn off UART clock before switching clocksource. */
	368	bcma_cc_write32(cc, BCMA_CC_CORECTL,
	369	bcma_cc_read32(cc, BCMA_CC_CORECTL)
	370	& ~BCMA_CC_CORECTL_UARTCLKEN);
	371	}
	372	/* Set the override bit so we don't divide it */
	373	bcma_cc_write32(cc, BCMA_CC_CORECTL,
	374	bcma_cc_read32(cc, BCMA_CC_CORECTL)
	375	\| BCMA_CC_CORECTL_UARTCLK0);
	376	if (ccrev >= 21) {
	377	/* Re-enable the UART clock. */
	378	bcma_cc_write32(cc, BCMA_CC_CORECTL,
	379	bcma_cc_read32(cc, BCMA_CC_CORECTL)
	380	\| BCMA_CC_CORECTL_UARTCLKEN);
	381	}
	382	} else {
d0f66df5 OFM	383	bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n",
d0f66df5 OFM	384	ccrev);
e3afe0e5 HM	385	return;
	386	}
	387
85eb92e8	388	irq = bcma_core_irq(cc->core, 0);
e3afe0e5 HM	389
	390	/* Determine the registers of the UARTs */
	391	cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
	392	for (i = 0; i < cc->nr_serial_ports; i++) {
	393	ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA +
	394	(i * 256);
	395	ports[i].irq = irq;
	396	ports[i].baud_base = baud_base;
	397	ports[i].reg_shift = 0;
	398	}
4c81acab	399	#endif /* CONFIG_BCM47XX */
e3afe0e5	400	}