[deliverable/linux.git] / drivers / bus / omap_l3_noc.c

/*
 * OMAP L3 Interconnect error handling driver
 *
 * Copyright (C) 2011-2015 Texas Instruments Incorporated - http://www.ti.com/
 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
 *	Sricharan <r.sricharan@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include "omap_l3_noc.h"

/**
 * l3_handle_target() - Handle Target specific parse and reporting
 * @l3:		pointer to l3 struct
 * @base:	base address of clkdm
 * @flag_mux:	flagmux corresponding to the event
 * @err_src:	error source index of the slave (target)
 *
 * This does the second part of the error interrupt handling:
 *	3) Parse in the slave information
 *	4) Print the logged information.
 *	5) Add dump stack to provide kernel trace.
 *	6) Clear the source if known.
 *
 * This handles two types of errors:
 *	1) Custom errors in L3 :
 *		Target like DMM/FW/EMIF generates SRESP=ERR error
 *	2) Standard L3 error:
 *		- Unsupported CMD.
 *			L3 tries to access target while it is idle
 *		- OCP disconnect.
 *		- Address hole error:
 *			If DSS/ISS/FDIF/USBHOSTFS access a target where they
 *			do not have connectivity, the error is logged in
 *			their default target which is DMM2.
 *
 *	On High Secure devices, firewall errors are possible and those
 *	can be trapped as well. But the trapping is implemented as part
 *	secure software and hence need not be implemented here.
 */
static int l3_handle_target(struct omap_l3 *l3, void __iomem *base,
			    struct l3_flagmux_data *flag_mux, int err_src)
{
	int k;
	u32 std_err_main, clear, masterid;
	u8 op_code, m_req_info;
	void __iomem *l3_targ_base;
	void __iomem *l3_targ_stderr, *l3_targ_slvofslsb, *l3_targ_mstaddr;
	void __iomem *l3_targ_hdr, *l3_targ_info;
	struct l3_target_data *l3_targ_inst;
	struct l3_masters_data *master;
	char *target_name, *master_name = "UN IDENTIFIED";
	char *err_description;
	char err_string[30] = { 0 };
	char info_string[60] = { 0 };

	/* We DONOT expect err_src to go out of bounds */
	BUG_ON(err_src > MAX_CLKDM_TARGETS);

	if (err_src < flag_mux->num_targ_data) {
		l3_targ_inst = &flag_mux->l3_targ[err_src];
		target_name = l3_targ_inst->name;
		l3_targ_base = base + l3_targ_inst->offset;
	} else {
		target_name = L3_TARGET_NOT_SUPPORTED;
	}

	if (target_name == L3_TARGET_NOT_SUPPORTED)
		return -ENODEV;

	/* Read the stderrlog_main_source from clk domain */
	l3_targ_stderr = l3_targ_base + L3_TARG_STDERRLOG_MAIN;
	l3_targ_slvofslsb = l3_targ_base + L3_TARG_STDERRLOG_SLVOFSLSB;

	std_err_main = readl_relaxed(l3_targ_stderr);

	switch (std_err_main & CUSTOM_ERROR) {
	case STANDARD_ERROR:
		err_description = "Standard";
		snprintf(err_string, sizeof(err_string),
			 ": At Address: 0x%08X ",
			 readl_relaxed(l3_targ_slvofslsb));

		l3_targ_mstaddr = l3_targ_base + L3_TARG_STDERRLOG_MSTADDR;
		l3_targ_hdr = l3_targ_base + L3_TARG_STDERRLOG_HDR;
		l3_targ_info = l3_targ_base + L3_TARG_STDERRLOG_INFO;
		break;

	case CUSTOM_ERROR:
		err_description = "Custom";

		l3_targ_mstaddr = l3_targ_base +
				  L3_TARG_STDERRLOG_CINFO_MSTADDR;
		l3_targ_hdr = l3_targ_base + L3_TARG_STDERRLOG_CINFO_OPCODE;
		l3_targ_info = l3_targ_base + L3_TARG_STDERRLOG_CINFO_INFO;
		break;

	default:
		/* Nothing to be handled here as of now */
		return 0;
	}

	/* STDERRLOG_MSTADDR Stores the NTTP master address. */
	masterid = (readl_relaxed(l3_targ_mstaddr) &
		    l3->mst_addr_mask) >> __ffs(l3->mst_addr_mask);

	for (k = 0, master = l3->l3_masters; k < l3->num_masters;
	     k++, master++) {
		if (masterid == master->id) {
			master_name = master->name;
			break;
		}
	}

	op_code = readl_relaxed(l3_targ_hdr) & 0x7;

	m_req_info = readl_relaxed(l3_targ_info) & 0xF;
	snprintf(info_string, sizeof(info_string),
		 ": %s in %s mode during %s access",
		 (m_req_info & BIT(0)) ? "Opcode Fetch" : "Data Access",
		 (m_req_info & BIT(1)) ? "Supervisor" : "User",
		 (m_req_info & BIT(3)) ? "Debug" : "Functional");

	WARN(true,
	     "%s:L3 %s Error: MASTER %s TARGET %s (%s)%s%s\n",
	     dev_name(l3->dev),
	     err_description,
	     master_name, target_name,
	     l3_transaction_type[op_code],
	     err_string, info_string);

	/* clear the std error log*/
	clear = std_err_main | CLEAR_STDERR_LOG;
	writel_relaxed(clear, l3_targ_stderr);

	return 0;
}

/**
 * l3_interrupt_handler() - interrupt handler for l3 events
 * @irq:	irq number
 * @_l3:	pointer to l3 structure
 *
 * Interrupt Handler for L3 error detection.
 *	1) Identify the L3 clockdomain partition to which the error belongs to.
 *	2) Identify the slave where the error information is logged
 *	... handle the slave event..
 *	7) if the slave is unknown, mask out the slave.
 */
static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
{
	struct omap_l3 *l3 = _l3;
	int inttype, i, ret;
	int err_src = 0;
	u32 err_reg, mask_val;
	void __iomem *base, *mask_reg;
	struct l3_flagmux_data *flag_mux;

	/* Get the Type of interrupt */
	inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;

	for (i = 0; i < l3->num_modules; i++) {
		/*
		 * Read the regerr register of the clock domain
		 * to determine the source
		 */
		base = l3->l3_base[i];
		flag_mux = l3->l3_flagmux[i];
		err_reg = readl_relaxed(base + flag_mux->offset +
					L3_FLAGMUX_REGERR0 + (inttype << 3));

		err_reg &= ~(inttype ? flag_mux->mask_app_bits :
				flag_mux->mask_dbg_bits);

		/* Get the corresponding error and analyse */
		if (err_reg) {
			/* Identify the source from control status register */
			err_src = __ffs(err_reg);

			ret = l3_handle_target(l3, base, flag_mux, err_src);

			/*
			 * Certain plaforms may have "undocumented" status
			 * pending on boot. So dont generate a severe warning
			 * here. Just mask it off to prevent the error from
			 * reoccuring and locking up the system.
			 */
			if (ret) {
				dev_err(l3->dev,
					"L3 %s error: target %d mod:%d %s\n",
					inttype ? "debug" : "application",
					err_src, i, "(unclearable)");

				mask_reg = base + flag_mux->offset +
					   L3_FLAGMUX_MASK0 + (inttype << 3);
				mask_val = readl_relaxed(mask_reg);
				mask_val &= ~(1 << err_src);
				writel_relaxed(mask_val, mask_reg);

				/* Mark these bits as to be ignored */
				if (inttype)
					flag_mux->mask_app_bits |= 1 << err_src;
				else
					flag_mux->mask_dbg_bits |= 1 << err_src;
			}

			/* Error found so break the for loop */
			return IRQ_HANDLED;
		}
	}

	dev_err(l3->dev, "L3 %s IRQ not handled!!\n",
		inttype ? "debug" : "application");

	return IRQ_NONE;
}

static const struct of_device_id l3_noc_match[] = {
	{.compatible = "ti,omap4-l3-noc", .data = &omap4_l3_data},
	{.compatible = "ti,omap5-l3-noc", .data = &omap5_l3_data},
	{.compatible = "ti,dra7-l3-noc", .data = &dra_l3_data},
	{.compatible = "ti,am4372-l3-noc", .data = &am4372_l3_data},
	{},
};
MODULE_DEVICE_TABLE(of, l3_noc_match);

static int omap_l3_probe(struct platform_device *pdev)
{
	const struct of_device_id *of_id;
	static struct omap_l3 *l3;
	int ret, i, res_idx;

	of_id = of_match_device(l3_noc_match, &pdev->dev);
	if (!of_id) {
		dev_err(&pdev->dev, "OF data missing\n");
		return -EINVAL;
	}

	l3 = devm_kzalloc(&pdev->dev, sizeof(*l3), GFP_KERNEL);
	if (!l3)
		return -ENOMEM;

	memcpy(l3, of_id->data, sizeof(*l3));
	l3->dev = &pdev->dev;
	platform_set_drvdata(pdev, l3);

	/* Get mem resources */
	for (i = 0, res_idx = 0; i < l3->num_modules; i++) {
		struct resource	*res;

		if (l3->l3_base[i] == L3_BASE_IS_SUBMODULE) {
			/* First entry cannot be submodule */
			BUG_ON(i == 0);
			l3->l3_base[i] = l3->l3_base[i - 1];
			continue;
		}
		res = platform_get_resource(pdev, IORESOURCE_MEM, res_idx);
		l3->l3_base[i] = devm_ioremap_resource(&pdev->dev, res);
		if (IS_ERR(l3->l3_base[i])) {
			dev_err(l3->dev, "ioremap %d failed\n", i);
			return PTR_ERR(l3->l3_base[i]);
		}
		res_idx++;
	}

	/*
	 * Setup interrupt Handlers
	 */
	l3->debug_irq = platform_get_irq(pdev, 0);
	ret = devm_request_irq(l3->dev, l3->debug_irq, l3_interrupt_handler,
			       0x0, "l3-dbg-irq", l3);
	if (ret) {
		dev_err(l3->dev, "request_irq failed for %d\n",
			l3->debug_irq);
		return ret;
	}

	l3->app_irq = platform_get_irq(pdev, 1);
	ret = devm_request_irq(l3->dev, l3->app_irq, l3_interrupt_handler,
			       0x0, "l3-app-irq", l3);
	if (ret)
		dev_err(l3->dev, "request_irq failed for %d\n", l3->app_irq);

	return ret;
}

#ifdef	CONFIG_PM_SLEEP

/**
 * l3_resume_noirq() - resume function for l3_noc
 * @dev:	pointer to l3_noc device structure
 *
 * We only have the resume handler only since we
 * have already maintained the delta register
 * configuration as part of configuring the system
 */
static int l3_resume_noirq(struct device *dev)
{
	struct omap_l3 *l3 = dev_get_drvdata(dev);
	int i;
	struct l3_flagmux_data *flag_mux;
	void __iomem *base, *mask_regx = NULL;
	u32 mask_val;

	for (i = 0; i < l3->num_modules; i++) {
		base = l3->l3_base[i];
		flag_mux = l3->l3_flagmux[i];
		if (!flag_mux->mask_app_bits && !flag_mux->mask_dbg_bits)
			continue;

		mask_regx = base + flag_mux->offset + L3_FLAGMUX_MASK0 +
			   (L3_APPLICATION_ERROR << 3);
		mask_val = readl_relaxed(mask_regx);
		mask_val &= ~(flag_mux->mask_app_bits);

		writel_relaxed(mask_val, mask_regx);
		mask_regx = base + flag_mux->offset + L3_FLAGMUX_MASK0 +
			   (L3_DEBUG_ERROR << 3);
		mask_val = readl_relaxed(mask_regx);
		mask_val &= ~(flag_mux->mask_dbg_bits);

		writel_relaxed(mask_val, mask_regx);
	}

	/* Dummy read to force OCP barrier */
	if (mask_regx)
		(void)readl(mask_regx);

	return 0;
}

static const struct dev_pm_ops l3_dev_pm_ops = {
	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, l3_resume_noirq)
};

#define L3_DEV_PM_OPS (&l3_dev_pm_ops)
#else
#define L3_DEV_PM_OPS NULL
#endif

static struct platform_driver omap_l3_driver = {
	.probe		= omap_l3_probe,
	.driver		= {
		.name		= "omap_l3_noc",
		.pm		= L3_DEV_PM_OPS,
		.of_match_table = of_match_ptr(l3_noc_match),
	},
};

static int __init omap_l3_init(void)
{
	return platform_driver_register(&omap_l3_driver);
}
postcore_initcall_sync(omap_l3_init);

static void __exit omap_l3_exit(void)
{
	platform_driver_unregister(&omap_l3_driver);
}
module_exit(omap_l3_exit);
Commit	Line	Data
2722e56d	1	/*
c10d5c9e	2	* OMAP L3 Interconnect error handling driver
ed0e3520	3	*
e7309c26	4	* Copyright (C) 2011-2015 Texas Instruments Incorporated - http://www.ti.com/
ed0e3520	5	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	6	* Sricharan <r.sricharan@ti.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
c5f2aea0 NM	9	* it under the terms of the GNU General Public License version 2 as
c5f2aea0 NM	10	* published by the Free Software Foundation.
ed0e3520	11	*
c5f2aea0 NM	12	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	13	* kind, whether express or implied; without even the implied warranty
	14	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
ed0e3520	15	* GNU General Public License for more details.
ed0e3520	16	*/
2722e56d	17	#include <linux/init.h>
2722e56d	18	#include <linux/interrupt.h>
0659452d	19	#include <linux/io.h>
2722e56d	20	#include <linux/kernel.h>
0659452d S	21	#include <linux/module.h>
	22	#include <linux/of_device.h>
	23	#include <linux/of.h>
	24	#include <linux/platform_device.h>
2722e56d SS	25	#include <linux/slab.h>
	26
	27	#include "omap_l3_noc.h"
	28
e4be3f3a NM	29	/**
	30	* l3_handle_target() - Handle Target specific parse and reporting
	31	* @l3: pointer to l3 struct
	32	* @base: base address of clkdm
	33	* @flag_mux: flagmux corresponding to the event
	34	* @err_src: error source index of the slave (target)
2722e56d	35	*
e4be3f3a NM	36	* This does the second part of the error interrupt handling:
	37	* 3) Parse in the slave information
	38	* 4) Print the logged information.
	39	* 5) Add dump stack to provide kernel trace.
	40	* 6) Clear the source if known.
	41	*
	42	* This handles two types of errors:
2722e56d SS	43	* 1) Custom errors in L3 :
	44	* Target like DMM/FW/EMIF generates SRESP=ERR error
	45	* 2) Standard L3 error:
	46	* - Unsupported CMD.
	47	* L3 tries to access target while it is idle
	48	* - OCP disconnect.
	49	* - Address hole error:
	50	* If DSS/ISS/FDIF/USBHOSTFS access a target where they
	51	* do not have connectivity, the error is logged in
	52	* their default target which is DMM2.
	53	*
	54	* On High Secure devices, firewall errors are possible and those
	55	* can be trapped as well. But the trapping is implemented as part
	56	* secure software and hence need not be implemented here.
	57	*/
e4be3f3a NM	58	static int l3_handle_target(struct omap_l3 l3, void __iomem base,
e4be3f3a NM	59	struct l3_flagmux_data *flag_mux, int err_src)
2722e56d	60	{
e4be3f3a NM	61	int k;
e4be3f3a NM	62	u32 std_err_main, clear, masterid;
cf52b2ec	63	u8 op_code, m_req_info;
e4be3f3a	64	void __iomem *l3_targ_base;
9e224c8f	65	void __iomem l3_targ_stderr, l3_targ_slvofslsb, *l3_targ_mstaddr;
cf52b2ec	66	void __iomem l3_targ_hdr, l3_targ_info;
3ae9af7c	67	struct l3_target_data *l3_targ_inst;
0659452d	68	struct l3_masters_data *master;
e4be3f3a	69	char target_name, master_name = "UN IDENTIFIED";
c98aa7aa NM	70	char *err_description;
c98aa7aa NM	71	char err_string[30] = { 0 };
cf52b2ec	72	char info_string[60] = { 0 };
2722e56d	73
e4be3f3a NM	74	/* We DONOT expect err_src to go out of bounds */
	75	BUG_ON(err_src > MAX_CLKDM_TARGETS);
	76
	77	if (err_src < flag_mux->num_targ_data) {
	78	l3_targ_inst = &flag_mux->l3_targ[err_src];
	79	target_name = l3_targ_inst->name;
	80	l3_targ_base = base + l3_targ_inst->offset;
	81	} else {
	82	target_name = L3_TARGET_NOT_SUPPORTED;
	83	}
	84
	85	if (target_name == L3_TARGET_NOT_SUPPORTED)
	86	return -ENODEV;
	87
	88	/* Read the stderrlog_main_source from clk domain */
	89	l3_targ_stderr = l3_targ_base + L3_TARG_STDERRLOG_MAIN;
	90	l3_targ_slvofslsb = l3_targ_base + L3_TARG_STDERRLOG_SLVOFSLSB;
	91
	92	std_err_main = readl_relaxed(l3_targ_stderr);
	93
	94	switch (std_err_main & CUSTOM_ERROR) {
	95	case STANDARD_ERROR:
	96	err_description = "Standard";
	97	snprintf(err_string, sizeof(err_string),
	98	": At Address: 0x%08X ",
	99	readl_relaxed(l3_targ_slvofslsb));
	100
	101	l3_targ_mstaddr = l3_targ_base + L3_TARG_STDERRLOG_MSTADDR;
7f9de02d	102	l3_targ_hdr = l3_targ_base + L3_TARG_STDERRLOG_HDR;
cf52b2ec	103	l3_targ_info = l3_targ_base + L3_TARG_STDERRLOG_INFO;
e4be3f3a NM	104	break;
	105
	106	case CUSTOM_ERROR:
	107	err_description = "Custom";
	108
	109	l3_targ_mstaddr = l3_targ_base +
	110	L3_TARG_STDERRLOG_CINFO_MSTADDR;
7f9de02d	111	l3_targ_hdr = l3_targ_base + L3_TARG_STDERRLOG_CINFO_OPCODE;
cf52b2ec	112	l3_targ_info = l3_targ_base + L3_TARG_STDERRLOG_CINFO_INFO;
e4be3f3a NM	113	break;
	114
	115	default:
	116	/* Nothing to be handled here as of now */
	117	return 0;
	118	}
	119
	120	/* STDERRLOG_MSTADDR Stores the NTTP master address. */
	121	masterid = (readl_relaxed(l3_targ_mstaddr) &
	122	l3->mst_addr_mask) >> __ffs(l3->mst_addr_mask);
	123
	124	for (k = 0, master = l3->l3_masters; k < l3->num_masters;
	125	k++, master++) {
	126	if (masterid == master->id) {
	127	master_name = master->name;
	128	break;
	129	}
	130	}
	131
7f9de02d NM	132	op_code = readl_relaxed(l3_targ_hdr) & 0x7;
7f9de02d NM	133
cf52b2ec NM	134	m_req_info = readl_relaxed(l3_targ_info) & 0xF;
	135	snprintf(info_string, sizeof(info_string),
	136	": %s in %s mode during %s access",
	137	(m_req_info & BIT(0)) ? "Opcode Fetch" : "Data Access",
	138	(m_req_info & BIT(1)) ? "Supervisor" : "User",
	139	(m_req_info & BIT(3)) ? "Debug" : "Functional");
	140
e4be3f3a	141	WARN(true,
cf52b2ec	142	"%s:L3 %s Error: MASTER %s TARGET %s (%s)%s%s\n",
e4be3f3a NM	143	dev_name(l3->dev),
	144	err_description,
	145	master_name, target_name,
7f9de02d	146	l3_transaction_type[op_code],
cf52b2ec	147	err_string, info_string);
e4be3f3a NM	148
	149	/* clear the std error log*/
	150	clear = std_err_main \| CLEAR_STDERR_LOG;
	151	writel_relaxed(clear, l3_targ_stderr);
	152
	153	return 0;
	154	}
	155
	156	/**
	157	* l3_interrupt_handler() - interrupt handler for l3 events
	158	* @irq: irq number
	159	* @_l3: pointer to l3 structure
	160	*
	161	* Interrupt Handler for L3 error detection.
	162	* 1) Identify the L3 clockdomain partition to which the error belongs to.
	163	* 2) Identify the slave where the error information is logged
	164	* ... handle the slave event..
	165	* 7) if the slave is unknown, mask out the slave.
	166	*/
	167	static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
	168	{
	169	struct omap_l3 *l3 = _l3;
	170	int inttype, i, ret;
	171	int err_src = 0;
	172	u32 err_reg, mask_val;
	173	void __iomem base, mask_reg;
	174	struct l3_flagmux_data *flag_mux;
	175
2722e56d	176	/* Get the Type of interrupt */
35f7b961	177	inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
2722e56d	178
0659452d	179	for (i = 0; i < l3->num_modules; i++) {
2722e56d SS	180	/*
	181	* Read the regerr register of the clock domain
	182	* to determine the source
	183	*/
6616aac6	184	base = l3->l3_base[i];
97708c08 NM	185	flag_mux = l3->l3_flagmux[i];
97708c08 NM	186	err_reg = readl_relaxed(base + flag_mux->offset +
9e224c8f	187	L3_FLAGMUX_REGERR0 + (inttype << 3));
2722e56d	188
2100b595 AM	189	err_reg &= ~(inttype ? flag_mux->mask_app_bits :
	190	flag_mux->mask_dbg_bits);
	191
2722e56d SS	192	/* Get the corresponding error and analyse */
	193	if (err_reg) {
	194	/* Identify the source from control status register */
342fd144	195	err_src = __ffs(err_reg);
3340d739	196
e4be3f3a	197	ret = l3_handle_target(l3, base, flag_mux, err_src);
2722e56d	198
3340d739	199	/*
e4be3f3a NM	200	* Certain plaforms may have "undocumented" status
	201	* pending on boot. So dont generate a severe warning
	202	* here. Just mask it off to prevent the error from
	203	* reoccuring and locking up the system.
3340d739	204	*/
e4be3f3a	205	if (ret) {
3340d739 RN	206	dev_err(l3->dev,
	207	"L3 %s error: target %d mod:%d %s\n",
	208	inttype ? "debug" : "application",
	209	err_src, i, "(unclearable)");
	210
97708c08	211	mask_reg = base + flag_mux->offset +
3340d739 RN	212	L3_FLAGMUX_MASK0 + (inttype << 3);
	213	mask_val = readl_relaxed(mask_reg);
	214	mask_val &= ~(1 << err_src);
	215	writel_relaxed(mask_val, mask_reg);
2100b595 AM	216
	217	/* Mark these bits as to be ignored */
	218	if (inttype)
	219	flag_mux->mask_app_bits \|= 1 << err_src;
	220	else
	221	flag_mux->mask_dbg_bits \|= 1 << err_src;
3340d739 RN	222	}
3340d739 RN	223
c98aa7aa	224	/* Error found so break the for loop */
c4cf0935	225	return IRQ_HANDLED;
2722e56d SS	226	}
2722e56d SS	227	}
c4cf0935 K	228
	229	dev_err(l3->dev, "L3 %s IRQ not handled!!\n",
	230	inttype ? "debug" : "application");
	231
	232	return IRQ_NONE;
2722e56d SS	233	}
2722e56d SS	234
0659452d	235	static const struct of_device_id l3_noc_match[] = {
e7309c26 SA	236	{.compatible = "ti,omap4-l3-noc", .data = &omap4_l3_data},
e7309c26 SA	237	{.compatible = "ti,omap5-l3-noc", .data = &omap5_l3_data},
53a848be	238	{.compatible = "ti,dra7-l3-noc", .data = &dra_l3_data},
27b7d5f3	239	{.compatible = "ti,am4372-l3-noc", .data = &am4372_l3_data},
0659452d S	240	{},
	241	};
	242	MODULE_DEVICE_TABLE(of, l3_noc_match);
	243
c10d5c9e	244	static int omap_l3_probe(struct platform_device *pdev)
2722e56d	245	{
0659452d	246	const struct of_device_id *of_id;
c10d5c9e	247	static struct omap_l3 *l3;
f33ddf74	248	int ret, i, res_idx;
2722e56d	249
0659452d S	250	of_id = of_match_device(l3_noc_match, &pdev->dev);
	251	if (!of_id) {
	252	dev_err(&pdev->dev, "OF data missing\n");
	253	return -EINVAL;
	254	}
	255
bae74510	256	l3 = devm_kzalloc(&pdev->dev, sizeof(*l3), GFP_KERNEL);
2722e56d	257	if (!l3)
7529b703	258	return -ENOMEM;
2722e56d	259
0659452d	260	memcpy(l3, of_id->data, sizeof(*l3));
ca6a3493	261	l3->dev = &pdev->dev;
2722e56d	262	platform_set_drvdata(pdev, l3);
2722e56d	263
56c4a022	264	/* Get mem resources */
f33ddf74 NM	265	for (i = 0, res_idx = 0; i < l3->num_modules; i++) {
	266	struct resource *res;
	267
	268	if (l3->l3_base[i] == L3_BASE_IS_SUBMODULE) {
	269	/* First entry cannot be submodule */
	270	BUG_ON(i == 0);
	271	l3->l3_base[i] = l3->l3_base[i - 1];
	272	continue;
	273	}
	274	res = platform_get_resource(pdev, IORESOURCE_MEM, res_idx);
56c4a022 PU	275	l3->l3_base[i] = devm_ioremap_resource(&pdev->dev, res);
56c4a022 PU	276	if (IS_ERR(l3->l3_base[i])) {
ca6a3493	277	dev_err(l3->dev, "ioremap %d failed\n", i);
56c4a022 PU	278	return PTR_ERR(l3->l3_base[i]);
56c4a022 PU	279	}
f33ddf74	280	res_idx++;
2722e56d SS	281	}
	282
	283	/*
	284	* Setup interrupt Handlers
	285	*/
c1df2dcc	286	l3->debug_irq = platform_get_irq(pdev, 0);
ca6a3493	287	ret = devm_request_irq(l3->dev, l3->debug_irq, l3_interrupt_handler,
d8bf368d	288	0x0, "l3-dbg-irq", l3);
2722e56d	289	if (ret) {
ca6a3493	290	dev_err(l3->dev, "request_irq failed for %d\n",
ae22598a	291	l3->debug_irq);
56c4a022	292	return ret;
2722e56d	293	}
2722e56d	294
c1df2dcc	295	l3->app_irq = platform_get_irq(pdev, 1);
ca6a3493	296	ret = devm_request_irq(l3->dev, l3->app_irq, l3_interrupt_handler,
d8bf368d	297	0x0, "l3-app-irq", l3);
a0ef78f3	298	if (ret)
ca6a3493	299	dev_err(l3->dev, "request_irq failed for %d\n", l3->app_irq);
7529b703	300
2722e56d SS	301	return ret;
	302	}
	303
258d2a10	304	#ifdef CONFIG_PM_SLEEP
61b43d4e K	305
	306	/**
	307	* l3_resume_noirq() - resume function for l3_noc
	308	* @dev: pointer to l3_noc device structure
	309	*
	310	* We only have the resume handler only since we
	311	* have already maintained the delta register
	312	* configuration as part of configuring the system
	313	*/
	314	static int l3_resume_noirq(struct device *dev)
	315	{
	316	struct omap_l3 *l3 = dev_get_drvdata(dev);
	317	int i;
	318	struct l3_flagmux_data *flag_mux;
	319	void __iomem base, mask_regx = NULL;
	320	u32 mask_val;
	321
	322	for (i = 0; i < l3->num_modules; i++) {
	323	base = l3->l3_base[i];
	324	flag_mux = l3->l3_flagmux[i];
	325	if (!flag_mux->mask_app_bits && !flag_mux->mask_dbg_bits)
	326	continue;
	327
	328	mask_regx = base + flag_mux->offset + L3_FLAGMUX_MASK0 +
	329	(L3_APPLICATION_ERROR << 3);
	330	mask_val = readl_relaxed(mask_regx);
	331	mask_val &= ~(flag_mux->mask_app_bits);
	332
	333	writel_relaxed(mask_val, mask_regx);
	334	mask_regx = base + flag_mux->offset + L3_FLAGMUX_MASK0 +
	335	(L3_DEBUG_ERROR << 3);
	336	mask_val = readl_relaxed(mask_regx);
	337	mask_val &= ~(flag_mux->mask_dbg_bits);
	338
	339	writel_relaxed(mask_val, mask_regx);
	340	}
	341
	342	/* Dummy read to force OCP barrier */
	343	if (mask_regx)
	344	(void)readl(mask_regx);
	345
	346	return 0;
	347	}
	348
	349	static const struct dev_pm_ops l3_dev_pm_ops = {
258d2a10	350	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, l3_resume_noirq)
61b43d4e K	351	};
	352
	353	#define L3_DEV_PM_OPS (&l3_dev_pm_ops)
	354	#else
	355	#define L3_DEV_PM_OPS NULL
	356	#endif
	357
c10d5c9e S	358	static struct platform_driver omap_l3_driver = {
c10d5c9e S	359	.probe = omap_l3_probe,
d039c5b9 BC	360	.driver = {
d039c5b9 BC	361	.name = "omap_l3_noc",
61b43d4e	362	.pm = L3_DEV_PM_OPS,
0659452d	363	.of_match_table = of_match_ptr(l3_noc_match),
2722e56d SS	364	},
	365	};
	366
c10d5c9e	367	static int __init omap_l3_init(void)
2722e56d	368	{
c10d5c9e	369	return platform_driver_register(&omap_l3_driver);
2722e56d	370	}
c10d5c9e	371	postcore_initcall_sync(omap_l3_init);
2722e56d	372
c10d5c9e	373	static void __exit omap_l3_exit(void)
2722e56d	374	{
c10d5c9e	375	platform_driver_unregister(&omap_l3_driver);
2722e56d	376	}
c10d5c9e	377	module_exit(omap_l3_exit);