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738f66d3 MT |
1 | /* |
2 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
3 | * redistributing this file, you may do so under either license. | |
4 | * | |
5 | * GPL LICENSE SUMMARY | |
6 | * | |
7 | * Copyright (c) 2016 AmLogic, Inc. | |
8 | * Author: Michael Turquette <mturquette@baylibre.com> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
22 | * The full GNU General Public License is included in this distribution | |
23 | * in the file called COPYING | |
24 | * | |
25 | * BSD LICENSE | |
26 | * | |
27 | * Copyright (c) 2016 BayLibre, Inc. | |
28 | * Author: Michael Turquette <mturquette@baylibre.com> | |
29 | * | |
30 | * Redistribution and use in source and binary forms, with or without | |
31 | * modification, are permitted provided that the following conditions | |
32 | * are met: | |
33 | * | |
34 | * * Redistributions of source code must retain the above copyright | |
35 | * notice, this list of conditions and the following disclaimer. | |
36 | * * Redistributions in binary form must reproduce the above copyright | |
37 | * notice, this list of conditions and the following disclaimer in | |
38 | * the documentation and/or other materials provided with the | |
39 | * distribution. | |
40 | * * Neither the name of Intel Corporation nor the names of its | |
41 | * contributors may be used to endorse or promote products derived | |
42 | * from this software without specific prior written permission. | |
43 | * | |
44 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
45 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
46 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
47 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
48 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
49 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
50 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
51 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
52 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
53 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
54 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
55 | */ | |
56 | ||
57 | #ifndef __GXBB_H | |
58 | #define __GXBB_H | |
59 | ||
60 | /* | |
61 | * Clock controller register offsets | |
62 | * | |
63 | * Register offsets from the data sheet are listed in comment blocks below. | |
64 | * Those offsets must be multiplied by 4 before adding them to the base address | |
65 | * to get the right value | |
66 | */ | |
67 | #define SCR 0x2C /* 0x0b offset in data sheet */ | |
68 | #define TIMEOUT_VALUE 0x3c /* 0x0f offset in data sheet */ | |
69 | ||
70 | #define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */ | |
71 | #define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */ | |
72 | #define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */ | |
73 | #define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */ | |
74 | ||
75 | #define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */ | |
76 | #define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */ | |
77 | ||
78 | #define HHI_MEM_PD_REG0 0x100 /* 0x40 offset in data sheet */ | |
79 | #define HHI_MEM_PD_REG1 0x104 /* 0x41 offset in data sheet */ | |
80 | #define HHI_VPU_MEM_PD_REG1 0x108 /* 0x42 offset in data sheet */ | |
81 | #define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */ | |
82 | #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ | |
83 | ||
84 | #define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */ | |
85 | #define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */ | |
86 | #define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ | |
87 | #define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */ | |
88 | #define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */ | |
89 | #define HHI_SYS_OSCIN_CNTL 0x158 /* 0x56 offset in data sheet */ | |
90 | #define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */ | |
91 | #define HHI_SYS_CPU_RESET_CNTL 0x160 /* 0x58 offset in data sheet */ | |
92 | #define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */ | |
93 | ||
94 | #define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */ | |
95 | #define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */ | |
96 | #define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */ | |
97 | #define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */ | |
98 | #define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */ | |
99 | #define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */ | |
100 | #define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */ | |
101 | #define HHI_AUD_CLK_CNTL3 0x1a4 /* 0x69 offset in data sheet */ | |
102 | #define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */ | |
103 | #define HHI_VPU_CLK_CNTL 0x1bC /* 0x6f offset in data sheet */ | |
104 | ||
105 | #define HHI_HDMI_CLK_CNTL 0x1CC /* 0x73 offset in data sheet */ | |
106 | #define HHI_VDEC_CLK_CNTL 0x1E0 /* 0x78 offset in data sheet */ | |
107 | #define HHI_VDEC2_CLK_CNTL 0x1E4 /* 0x79 offset in data sheet */ | |
108 | #define HHI_VDEC3_CLK_CNTL 0x1E8 /* 0x7a offset in data sheet */ | |
109 | #define HHI_VDEC4_CLK_CNTL 0x1EC /* 0x7b offset in data sheet */ | |
110 | #define HHI_HDCP22_CLK_CNTL 0x1F0 /* 0x7c offset in data sheet */ | |
111 | #define HHI_VAPBCLK_CNTL 0x1F4 /* 0x7d offset in data sheet */ | |
112 | ||
113 | #define HHI_VPU_CLKB_CNTL 0x20C /* 0x83 offset in data sheet */ | |
114 | #define HHI_USB_CLK_CNTL 0x220 /* 0x88 offset in data sheet */ | |
115 | #define HHI_32K_CLK_CNTL 0x224 /* 0x89 offset in data sheet */ | |
116 | #define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */ | |
117 | #define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */ | |
118 | ||
119 | #define HHI_PCM_CLK_CNTL 0x258 /* 0x96 offset in data sheet */ | |
120 | #define HHI_NAND_CLK_CNTL 0x25C /* 0x97 offset in data sheet */ | |
121 | #define HHI_SD_EMMC_CLK_CNTL 0x264 /* 0x99 offset in data sheet */ | |
122 | ||
123 | #define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ | |
124 | #define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */ | |
125 | #define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */ | |
126 | #define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */ | |
127 | #define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */ | |
128 | #define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */ | |
129 | #define HHI_MPLL_CNTL7 0x298 /* MP0, 0xa6 offset in data sheet */ | |
130 | #define HHI_MPLL_CNTL8 0x29C /* MP1, 0xa7 offset in data sheet */ | |
131 | #define HHI_MPLL_CNTL9 0x2A0 /* MP2, 0xa8 offset in data sheet */ | |
132 | #define HHI_MPLL_CNTL10 0x2A4 /* MP2, 0xa9 offset in data sheet */ | |
133 | ||
134 | #define HHI_MPLL3_CNTL0 0x2E0 /* 0xb8 offset in data sheet */ | |
135 | #define HHI_MPLL3_CNTL1 0x2E4 /* 0xb9 offset in data sheet */ | |
136 | #define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */ | |
137 | #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ | |
138 | ||
139 | #define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ | |
140 | #define HHI_SYS_PLL_CNTL2 0x304 /* 0xc1 offset in data sheet */ | |
141 | #define HHI_SYS_PLL_CNTL3 0x308 /* 0xc2 offset in data sheet */ | |
142 | #define HHI_SYS_PLL_CNTL4 0x30c /* 0xc3 offset in data sheet */ | |
143 | #define HHI_SYS_PLL_CNTL5 0x310 /* 0xc4 offset in data sheet */ | |
144 | #define HHI_DPLL_TOP_I 0x318 /* 0xc6 offset in data sheet */ | |
145 | #define HHI_DPLL_TOP2_I 0x31C /* 0xc7 offset in data sheet */ | |
146 | #define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ | |
147 | #define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ | |
148 | #define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */ | |
149 | #define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */ | |
150 | #define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */ | |
151 | #define HHI_HDMI_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */ | |
152 | #define HHI_HDMI_PLL_CNTL_I 0x338 /* 0xce offset in data sheet */ | |
153 | #define HHI_HDMI_PLL_CNTL7 0x33C /* 0xcf offset in data sheet */ | |
154 | ||
155 | #define HHI_HDMI_PHY_CNTL0 0x3A0 /* 0xe8 offset in data sheet */ | |
156 | #define HHI_HDMI_PHY_CNTL1 0x3A4 /* 0xe9 offset in data sheet */ | |
157 | #define HHI_HDMI_PHY_CNTL2 0x3A8 /* 0xea offset in data sheet */ | |
158 | #define HHI_HDMI_PHY_CNTL3 0x3AC /* 0xeb offset in data sheet */ | |
159 | ||
160 | #define HHI_VID_LOCK_CLK_CNTL 0x3C8 /* 0xf2 offset in data sheet */ | |
161 | #define HHI_BT656_CLK_CNTL 0x3D4 /* 0xf5 offset in data sheet */ | |
162 | #define HHI_SAR_CLK_CNTL 0x3D8 /* 0xf6 offset in data sheet */ | |
163 | ||
164 | /* | |
165 | * CLKID index values | |
166 | * | |
167 | * These indices are entirely contrived and do not map onto the hardware. | |
168 | * Migrate them out of this header and into the DT header file when they need | |
169 | * to be exposed to client nodes in DT: include/dt-bindings/clock/gxbb-clkc.h | |
170 | */ | |
171 | #define CLKID_SYS_PLL 0 | |
172 | /* CLKID_CPUCLK */ | |
173 | #define CLKID_HDMI_PLL 2 | |
174 | #define CLKID_FIXED_PLL 3 | |
33608dcd | 175 | /* CLKID_FCLK_DIV2 */ |
738f66d3 MT |
176 | #define CLKID_FCLK_DIV3 5 |
177 | #define CLKID_FCLK_DIV4 6 | |
178 | #define CLKID_FCLK_DIV5 7 | |
179 | #define CLKID_FCLK_DIV7 8 | |
180 | #define CLKID_GP0_PLL 9 | |
181 | #define CLKID_MPEG_SEL 10 | |
182 | #define CLKID_MPEG_DIV 11 | |
183 | /* CLKID_CLK81 */ | |
184 | #define CLKID_MPLL0 13 | |
185 | #define CLKID_MPLL1 14 | |
186 | #define CLKID_MPLL2 15 | |
187 | #define CLKID_DDR 16 | |
188 | #define CLKID_DOS 17 | |
189 | #define CLKID_ISA 18 | |
190 | #define CLKID_PL301 19 | |
191 | #define CLKID_PERIPHS 20 | |
192 | #define CLKID_SPICC 21 | |
193 | #define CLKID_I2C 22 | |
194 | #define CLKID_SAR_ADC 23 | |
195 | #define CLKID_SMART_CARD 24 | |
196 | #define CLKID_RNG0 25 | |
197 | #define CLKID_UART0 26 | |
198 | #define CLKID_SDHC 27 | |
199 | #define CLKID_STREAM 28 | |
200 | #define CLKID_ASYNC_FIFO 29 | |
201 | #define CLKID_SDIO 30 | |
202 | #define CLKID_ABUF 31 | |
203 | #define CLKID_HIU_IFACE 32 | |
204 | #define CLKID_ASSIST_MISC 33 | |
205 | #define CLKID_SPI 34 | |
206 | #define CLKID_I2S_SPDIF 35 | |
207 | #define CLKID_ETH 36 | |
208 | #define CLKID_DEMUX 37 | |
209 | #define CLKID_AIU_GLUE 38 | |
210 | #define CLKID_IEC958 39 | |
211 | #define CLKID_I2S_OUT 40 | |
212 | #define CLKID_AMCLK 41 | |
213 | #define CLKID_AIFIFO2 42 | |
214 | #define CLKID_MIXER 43 | |
215 | #define CLKID_MIXER_IFACE 44 | |
216 | #define CLKID_ADC 45 | |
217 | #define CLKID_BLKMV 46 | |
218 | #define CLKID_AIU 47 | |
219 | #define CLKID_UART1 48 | |
220 | #define CLKID_G2D 49 | |
221 | #define CLKID_USB0 50 | |
222 | #define CLKID_USB1 51 | |
223 | #define CLKID_RESET 52 | |
224 | #define CLKID_NAND 53 | |
225 | #define CLKID_DOS_PARSER 54 | |
226 | #define CLKID_USB 55 | |
227 | #define CLKID_VDIN1 56 | |
228 | #define CLKID_AHB_ARB0 57 | |
229 | #define CLKID_EFUSE 58 | |
230 | #define CLKID_BOOT_ROM 59 | |
231 | #define CLKID_AHB_DATA_BUS 60 | |
232 | #define CLKID_AHB_CTRL_BUS 61 | |
233 | #define CLKID_HDMI_INTR_SYNC 62 | |
234 | #define CLKID_HDMI_PCLK 63 | |
235 | #define CLKID_USB1_DDR_BRIDGE 64 | |
236 | #define CLKID_USB0_DDR_BRIDGE 65 | |
ca1d2e26 | 237 | #define CLKID_MMC_PCLK 66 |
738f66d3 MT |
238 | #define CLKID_DVIN 67 |
239 | #define CLKID_UART2 68 | |
240 | #define CLKID_SANA 69 | |
241 | #define CLKID_VPU_INTR 70 | |
242 | #define CLKID_SEC_AHB_AHB3_BRIDGE 71 | |
243 | #define CLKID_CLK81_A53 72 | |
244 | #define CLKID_VCLK2_VENCI0 73 | |
245 | #define CLKID_VCLK2_VENCI1 74 | |
246 | #define CLKID_VCLK2_VENCP0 75 | |
247 | #define CLKID_VCLK2_VENCP1 76 | |
248 | #define CLKID_GCLK_VENCI_INT0 77 | |
249 | #define CLKID_GCLK_VENCI_INT 78 | |
250 | #define CLKID_DAC_CLK 79 | |
251 | #define CLKID_AOCLK_GATE 80 | |
252 | #define CLKID_IEC958_GATE 81 | |
253 | #define CLKID_ENC480P 82 | |
254 | #define CLKID_RNG1 83 | |
255 | #define CLKID_GCLK_VENCI_INT1 84 | |
256 | #define CLKID_VCLK2_VENCLMCC 85 | |
257 | #define CLKID_VCLK2_VENCL 86 | |
258 | #define CLKID_VCLK_OTHER 87 | |
259 | #define CLKID_EDP 88 | |
260 | #define CLKID_AO_MEDIA_CPU 89 | |
261 | #define CLKID_AO_AHB_SRAM 90 | |
262 | #define CLKID_AO_AHB_BUS 91 | |
263 | #define CLKID_AO_IFACE 92 | |
264 | #define CLKID_AO_I2C 93 | |
33608dcd KH |
265 | /* CLKID_SD_EMMC_A */ |
266 | /* CLKID_SD_EMMC_B */ | |
267 | /* CLKID_SD_EMMC_C */ | |
738f66d3 | 268 | |
33608dcd | 269 | #define NR_CLKS 97 |
738f66d3 MT |
270 | |
271 | /* include the CLKIDs that have been made part of the stable DT binding */ | |
272 | #include <dt-bindings/clock/gxbb-clkc.h> | |
273 | ||
274 | #endif /* __GXBB_H */ |