[deliverable/linux.git] / drivers / clocksource / h8300_timer8.c

/*
 *  linux/arch/h8300/kernel/cpu/timer/timer8.c
 *
 *  Yoshinori Sato <ysato@users.sourcefoge.jp>
 *
 *  8bit Timer driver
 *
 */

#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#define _8TCR	0
#define _8TCSR	2
#define TCORA	4
#define TCORB	6
#define _8TCNT	8

#define CMIEA	6
#define CMFA	6

#define FLAG_STARTED (1 << 3)

#define SCALE 64

#define bset(b, a) iowrite8(ioread8(a) | (1 << (b)), (a))
#define bclr(b, a) iowrite8(ioread8(a) & ~(1 << (b)), (a))

struct timer8_priv {
	struct clock_event_device ced;
	void __iomem *mapbase;
	unsigned long flags;
	unsigned int rate;
};

static irqreturn_t timer8_interrupt(int irq, void *dev_id)
{
	struct timer8_priv *p = dev_id;

	if (clockevent_state_oneshot(&p->ced))
		iowrite16be(0x0000, p->mapbase + _8TCR);

	p->ced.event_handler(&p->ced);

	bclr(CMFA, p->mapbase + _8TCSR);

	return IRQ_HANDLED;
}

static void timer8_set_next(struct timer8_priv *p, unsigned long delta)
{
	if (delta >= 0x10000)
		pr_warn("delta out of range\n");
	bclr(CMIEA, p->mapbase + _8TCR);
	iowrite16be(delta, p->mapbase + TCORA);
	iowrite16be(0x0000, p->mapbase + _8TCNT);
	bclr(CMFA, p->mapbase + _8TCSR);
	bset(CMIEA, p->mapbase + _8TCR);
}

static int timer8_enable(struct timer8_priv *p)
{
	iowrite16be(0xffff, p->mapbase + TCORA);
	iowrite16be(0x0000, p->mapbase + _8TCNT);
	iowrite16be(0x0c02, p->mapbase + _8TCR);

	return 0;
}

static int timer8_start(struct timer8_priv *p)
{
	int ret;

	if ((p->flags & FLAG_STARTED))
		return 0;

	ret = timer8_enable(p);
	if (!ret)
		p->flags |= FLAG_STARTED;

	return ret;
}

static void timer8_stop(struct timer8_priv *p)
{
	iowrite16be(0x0000, p->mapbase + _8TCR);
}

static inline struct timer8_priv *ced_to_priv(struct clock_event_device *ced)
{
	return container_of(ced, struct timer8_priv, ced);
}

static void timer8_clock_event_start(struct timer8_priv *p, unsigned long delta)
{
	struct clock_event_device *ced = &p->ced;

	timer8_start(p);

	ced->shift = 32;
	ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
	ced->max_delta_ns = clockevent_delta2ns(0xffff, ced);
	ced->min_delta_ns = clockevent_delta2ns(0x0001, ced);

	timer8_set_next(p, delta);
}

static int timer8_clock_event_shutdown(struct clock_event_device *ced)
{
	timer8_stop(ced_to_priv(ced));
	return 0;
}

static int timer8_clock_event_periodic(struct clock_event_device *ced)
{
	struct timer8_priv *p = ced_to_priv(ced);

	pr_info("%s: used for periodic clock events\n", ced->name);
	timer8_stop(p);
	timer8_clock_event_start(p, (p->rate + HZ/2) / HZ);

	return 0;
}

static int timer8_clock_event_oneshot(struct clock_event_device *ced)
{
	struct timer8_priv *p = ced_to_priv(ced);

	pr_info("%s: used for oneshot clock events\n", ced->name);
	timer8_stop(p);
	timer8_clock_event_start(p, 0x10000);

	return 0;
}

static int timer8_clock_event_next(unsigned long delta,
				   struct clock_event_device *ced)
{
	struct timer8_priv *p = ced_to_priv(ced);

	BUG_ON(!clockevent_state_oneshot(ced));
	timer8_set_next(p, delta - 1);

	return 0;
}

static struct timer8_priv timer8_priv = {
	.ced = {
		.name = "h8300_8timer",
		.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
		.rating = 200,
		.set_next_event = timer8_clock_event_next,
		.set_state_shutdown = timer8_clock_event_shutdown,
		.set_state_periodic = timer8_clock_event_periodic,
		.set_state_oneshot = timer8_clock_event_oneshot,
	},
};

static void __init h8300_8timer_init(struct device_node *node)
{
	void __iomem *base;
	int irq;
	struct clk *clk;

	clk = of_clk_get(node, 0);
	if (IS_ERR(clk)) {
		pr_err("failed to get clock for clockevent\n");
		return;
	}

	base = of_iomap(node, 0);
	if (!base) {
		pr_err("failed to map registers for clockevent\n");
		goto free_clk;
	}

	irq = irq_of_parse_and_map(node, 0);
	if (!irq) {
		pr_err("failed to get irq for clockevent\n");
		goto unmap_reg;
	}

	timer8_priv.mapbase = base;

	timer8_priv.rate = clk_get_rate(clk) / SCALE;
	if (!timer8_priv.rate) {
		pr_err("Failed to get rate for the clocksource\n");
		goto unmap_reg;
	}

	if (request_irq(irq, timer8_interrupt, IRQF_TIMER,
			timer8_priv.ced.name, &timer8_priv) < 0) {
		pr_err("failed to request irq %d for clockevent\n", irq);
		goto unmap_reg;
	}

	clockevents_config_and_register(&timer8_priv.ced,
					timer8_priv.rate, 1, 0x0000ffff);

	return;
unmap_reg:
	iounmap(base);
free_clk:
	clk_put(clk);
}

CLOCKSOURCE_OF_DECLARE(h8300_8bit, "renesas,8bit-timer", h8300_8timer_init);
Commit	Line	Data
618b902d YS	1	/*
	2	* linux/arch/h8300/kernel/cpu/timer/timer8.c
	3	*
	4	* Yoshinori Sato <ysato@users.sourcefoge.jp>
	5	*
	6	* 8bit Timer driver
	7	*
	8	*/
	9
	10	#include <linux/errno.h>
618b902d YS	11	#include <linux/kernel.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/init.h>
618b902d	14	#include <linux/clockchips.h>
618b902d YS	15	#include <linux/clk.h>
	16	#include <linux/io.h>
	17	#include <linux/of.h>
4633f4ca YS	18	#include <linux/of_address.h>
4633f4ca YS	19	#include <linux/of_irq.h>
618b902d	20
618b902d YS	21	#define _8TCR 0
	22	#define _8TCSR 2
	23	#define TCORA 4
	24	#define TCORB 6
	25	#define _8TCNT 8
	26
d33f250a YS	27	#define CMIEA 6
	28	#define CMFA 6
	29
618b902d YS	30	#define FLAG_STARTED (1 << 3)
618b902d YS	31
4633f4ca YS	32	#define SCALE 64
4633f4ca YS	33
d33f250a YS	34	#define bset(b, a) iowrite8(ioread8(a) \| (1 << (b)), (a))
	35	#define bclr(b, a) iowrite8(ioread8(a) & ~(1 << (b)), (a))
	36
618b902d	37	struct timer8_priv {
618b902d	38	struct clock_event_device ced;
75160515	39	void __iomem *mapbase;
618b902d YS	40	unsigned long flags;
618b902d YS	41	unsigned int rate;
618b902d YS	42	};
618b902d YS	43
618b902d YS	44	static irqreturn_t timer8_interrupt(int irq, void *dev_id)
	45	{
	46	struct timer8_priv *p = dev_id;
	47
7053fdac	48	if (clockevent_state_oneshot(&p->ced))
d33f250a	49	iowrite16be(0x0000, p->mapbase + _8TCR);
7053fdac DL	50
7053fdac DL	51	p->ced.event_handler(&p->ced);
618b902d	52
d33f250a	53	bclr(CMFA, p->mapbase + _8TCSR);
f37632d1	54
618b902d YS	55	return IRQ_HANDLED;
	56	}
	57
	58	static void timer8_set_next(struct timer8_priv *p, unsigned long delta)
	59	{
618b902d	60	if (delta >= 0x10000)
8c09b7d6	61	pr_warn("delta out of range\n");
d33f250a YS	62	bclr(CMIEA, p->mapbase + _8TCR);
	63	iowrite16be(delta, p->mapbase + TCORA);
	64	iowrite16be(0x0000, p->mapbase + _8TCNT);
	65	bclr(CMFA, p->mapbase + _8TCSR);
	66	bset(CMIEA, p->mapbase + _8TCR);
618b902d YS	67	}
	68
	69	static int timer8_enable(struct timer8_priv *p)
	70	{
d33f250a YS	71	iowrite16be(0xffff, p->mapbase + TCORA);
	72	iowrite16be(0x0000, p->mapbase + _8TCNT);
	73	iowrite16be(0x0c02, p->mapbase + _8TCR);
618b902d YS	74
	75	return 0;
	76	}
	77
	78	static int timer8_start(struct timer8_priv *p)
	79	{
cce483e0	80	int ret;
618b902d	81
cce483e0 DL	82	if ((p->flags & FLAG_STARTED))
cce483e0 DL	83	return 0;
618b902d	84
cce483e0 DL	85	ret = timer8_enable(p);
	86	if (!ret)
	87	p->flags \|= FLAG_STARTED;
618b902d	88
618b902d YS	89	return ret;
	90	}
	91
	92	static void timer8_stop(struct timer8_priv *p)
	93	{
d33f250a	94	iowrite16be(0x0000, p->mapbase + _8TCR);
618b902d YS	95	}
	96
	97	static inline struct timer8_priv ced_to_priv(struct clock_event_device ced)
	98	{
	99	return container_of(ced, struct timer8_priv, ced);
	100	}
	101
1f058d52	102	static void timer8_clock_event_start(struct timer8_priv *p, unsigned long delta)
618b902d YS	103	{
	104	struct clock_event_device *ced = &p->ced;
	105
	106	timer8_start(p);
	107
	108	ced->shift = 32;
	109	ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
	110	ced->max_delta_ns = clockevent_delta2ns(0xffff, ced);
	111	ced->min_delta_ns = clockevent_delta2ns(0x0001, ced);
	112
1f058d52	113	timer8_set_next(p, delta);
618b902d YS	114	}
618b902d YS	115
fc2b2f5d VK	116	static int timer8_clock_event_shutdown(struct clock_event_device *ced)
	117	{
	118	timer8_stop(ced_to_priv(ced));
	119	return 0;
	120	}
	121
	122	static int timer8_clock_event_periodic(struct clock_event_device *ced)
618b902d YS	123	{
	124	struct timer8_priv *p = ced_to_priv(ced);
	125
4633f4ca	126	pr_info("%s: used for periodic clock events\n", ced->name);
fc2b2f5d	127	timer8_stop(p);
1f058d52	128	timer8_clock_event_start(p, (p->rate + HZ/2) / HZ);
fc2b2f5d VK	129
	130	return 0;
	131	}
	132
	133	static int timer8_clock_event_oneshot(struct clock_event_device *ced)
	134	{
	135	struct timer8_priv *p = ced_to_priv(ced);
	136
4633f4ca	137	pr_info("%s: used for oneshot clock events\n", ced->name);
fc2b2f5d	138	timer8_stop(p);
1f058d52	139	timer8_clock_event_start(p, 0x10000);
fc2b2f5d VK	140
fc2b2f5d VK	141	return 0;
618b902d YS	142	}
	143
	144	static int timer8_clock_event_next(unsigned long delta,
	145	struct clock_event_device *ced)
	146	{
	147	struct timer8_priv *p = ced_to_priv(ced);
	148
fc2b2f5d	149	BUG_ON(!clockevent_state_oneshot(ced));
618b902d YS	150	timer8_set_next(p, delta - 1);
	151
	152	return 0;
	153	}
	154
4633f4ca YS	155	static struct timer8_priv timer8_priv = {
	156	.ced = {
	157	.name = "h8300_8timer",
	158	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	159	.rating = 200,
	160	.set_next_event = timer8_clock_event_next,
	161	.set_state_shutdown = timer8_clock_event_shutdown,
	162	.set_state_periodic = timer8_clock_event_periodic,
	163	.set_state_oneshot = timer8_clock_event_oneshot,
	164	},
	165	};
	166
	167	static void __init h8300_8timer_init(struct device_node *node)
618b902d	168	{
4633f4ca	169	void __iomem *base;
618b902d	170	int irq;
4633f4ca	171	struct clk *clk;
618b902d	172
4633f4ca YS	173	clk = of_clk_get(node, 0);
	174	if (IS_ERR(clk)) {
	175	pr_err("failed to get clock for clockevent\n");
	176	return;
	177	}
618b902d	178
4633f4ca YS	179	base = of_iomap(node, 0);
	180	if (!base) {
	181	pr_err("failed to map registers for clockevent\n");
	182	goto free_clk;
618b902d YS	183	}
618b902d YS	184
4633f4ca	185	irq = irq_of_parse_and_map(node, 0);
54a0cd5a	186	if (!irq) {
4633f4ca YS	187	pr_err("failed to get irq for clockevent\n");
4633f4ca YS	188	goto unmap_reg;
618b902d YS	189	}
618b902d YS	190
75160515	191	timer8_priv.mapbase = base;
cce483e0	192
6f2b611d YS	193	timer8_priv.rate = clk_get_rate(clk) / SCALE;
6f2b611d YS	194	if (!timer8_priv.rate) {
cce483e0 DL	195	pr_err("Failed to get rate for the clocksource\n");
	196	goto unmap_reg;
	197	}
618b902d	198
6f2b611d YS	199	if (request_irq(irq, timer8_interrupt, IRQF_TIMER,
6f2b611d YS	200	timer8_priv.ced.name, &timer8_priv) < 0) {
4633f4ca YS	201	pr_err("failed to request irq %d for clockevent\n", irq);
4633f4ca YS	202	goto unmap_reg;
618b902d	203	}
cce483e0	204
6f2b611d YS	205	clockevents_config_and_register(&timer8_priv.ced,
6f2b611d YS	206	timer8_priv.rate, 1, 0x0000ffff);
4633f4ca	207
cce483e0	208	return;
4633f4ca YS	209	unmap_reg:
	210	iounmap(base);
	211	free_clk:
	212	clk_put(clk);
618b902d YS	213	}
618b902d YS	214
4633f4ca	215	CLOCKSOURCE_OF_DECLARE(h8300_8bit, "renesas,8bit-timer", h8300_8timer_init);