[deliverable/linux.git] / drivers / clocksource / timer-imx-gpt.c

/*
 *  linux/arch/arm/plat-mxc/time.c
 *
 *  Copyright (C) 2000-2001 Deep Blue Solutions
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
 *  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */

#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/sched_clock.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <soc/imx/timer.h>

/*
 * There are 4 versions of the timer hardware on Freescale MXC hardware.
 *  - MX1/MXL
 *  - MX21, MX27.
 *  - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0)
 *  - MX6DL, MX6SX, MX6Q(rev1.1+)
 */

/* defines common for all i.MX */
#define MXC_TCTL		0x00
#define MXC_TCTL_TEN		(1 << 0) /* Enable module */
#define MXC_TPRER		0x04

/* MX1, MX21, MX27 */
#define MX1_2_TCTL_CLK_PCLK1	(1 << 1)
#define MX1_2_TCTL_IRQEN	(1 << 4)
#define MX1_2_TCTL_FRR		(1 << 8)
#define MX1_2_TCMP		0x08
#define MX1_2_TCN		0x10
#define MX1_2_TSTAT		0x14

/* MX21, MX27 */
#define MX2_TSTAT_CAPT		(1 << 1)
#define MX2_TSTAT_COMP		(1 << 0)

/* MX31, MX35, MX25, MX5, MX6 */
#define V2_TCTL_WAITEN		(1 << 3) /* Wait enable mode */
#define V2_TCTL_CLK_IPG		(1 << 6)
#define V2_TCTL_CLK_PER		(2 << 6)
#define V2_TCTL_CLK_OSC_DIV8	(5 << 6)
#define V2_TCTL_FRR		(1 << 9)
#define V2_TCTL_24MEN		(1 << 10)
#define V2_TPRER_PRE24M		12
#define V2_IR			0x0c
#define V2_TSTAT		0x08
#define V2_TSTAT_OF1		(1 << 0)
#define V2_TCN			0x24
#define V2_TCMP			0x10

#define V2_TIMER_RATE_OSC_DIV8	3000000

struct imx_timer {
	enum imx_gpt_type type;
	void __iomem *base;
	int irq;
	struct clk *clk_per;
	struct clk *clk_ipg;
	const struct imx_gpt_data *gpt;
	struct clock_event_device ced;
	struct irqaction act;
};

struct imx_gpt_data {
	int reg_tstat;
	int reg_tcn;
	int reg_tcmp;
	void (*gpt_setup_tctl)(struct imx_timer *imxtm);
	void (*gpt_irq_enable)(struct imx_timer *imxtm);
	void (*gpt_irq_disable)(struct imx_timer *imxtm);
	void (*gpt_irq_acknowledge)(struct imx_timer *imxtm);
	int (*set_next_event)(unsigned long evt,
			      struct clock_event_device *ced);
};

static inline struct imx_timer *to_imx_timer(struct clock_event_device *ced)
{
	return container_of(ced, struct imx_timer, ced);
}

static void imx1_gpt_irq_disable(struct imx_timer *imxtm)
{
	unsigned int tmp;

	tmp = readl_relaxed(imxtm->base + MXC_TCTL);
	writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
}
#define imx21_gpt_irq_disable imx1_gpt_irq_disable

static void imx31_gpt_irq_disable(struct imx_timer *imxtm)
{
	writel_relaxed(0, imxtm->base + V2_IR);
}
#define imx6dl_gpt_irq_disable imx31_gpt_irq_disable

static void imx1_gpt_irq_enable(struct imx_timer *imxtm)
{
	unsigned int tmp;

	tmp = readl_relaxed(imxtm->base + MXC_TCTL);
	writel_relaxed(tmp | MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
}
#define imx21_gpt_irq_enable imx1_gpt_irq_enable

static void imx31_gpt_irq_enable(struct imx_timer *imxtm)
{
	writel_relaxed(1<<0, imxtm->base + V2_IR);
}
#define imx6dl_gpt_irq_enable imx31_gpt_irq_enable

static void imx1_gpt_irq_acknowledge(struct imx_timer *imxtm)
{
	writel_relaxed(0, imxtm->base + MX1_2_TSTAT);
}

static void imx21_gpt_irq_acknowledge(struct imx_timer *imxtm)
{
	writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
				imxtm->base + MX1_2_TSTAT);
}

static void imx31_gpt_irq_acknowledge(struct imx_timer *imxtm)
{
	writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT);
}
#define imx6dl_gpt_irq_acknowledge imx31_gpt_irq_acknowledge

static void __iomem *sched_clock_reg;

static u64 notrace mxc_read_sched_clock(void)
{
	return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0;
}

static struct delay_timer imx_delay_timer;

static unsigned long imx_read_current_timer(void)
{
	return readl_relaxed(sched_clock_reg);
}

static int __init mxc_clocksource_init(struct imx_timer *imxtm)
{
	unsigned int c = clk_get_rate(imxtm->clk_per);
	void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn;

	imx_delay_timer.read_current_timer = &imx_read_current_timer;
	imx_delay_timer.freq = c;
	register_current_timer_delay(&imx_delay_timer);

	sched_clock_reg = reg;

	sched_clock_register(mxc_read_sched_clock, 32, c);
	return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
			clocksource_mmio_readl_up);
}

/* clock event */

static int mx1_2_set_next_event(unsigned long evt,
			      struct clock_event_device *ced)
{
	struct imx_timer *imxtm = to_imx_timer(ced);
	unsigned long tcmp;

	tcmp = readl_relaxed(imxtm->base + MX1_2_TCN) + evt;

	writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP);

	return (int)(tcmp - readl_relaxed(imxtm->base + MX1_2_TCN)) < 0 ?
				-ETIME : 0;
}

static int v2_set_next_event(unsigned long evt,
			      struct clock_event_device *ced)
{
	struct imx_timer *imxtm = to_imx_timer(ced);
	unsigned long tcmp;

	tcmp = readl_relaxed(imxtm->base + V2_TCN) + evt;

	writel_relaxed(tcmp, imxtm->base + V2_TCMP);

	return evt < 0x7fffffff &&
		(int)(tcmp - readl_relaxed(imxtm->base + V2_TCN)) < 0 ?
				-ETIME : 0;
}

static int mxc_shutdown(struct clock_event_device *ced)
{
	struct imx_timer *imxtm = to_imx_timer(ced);
	unsigned long flags;
	u32 tcn;

	/*
	 * The timer interrupt generation is disabled at least
	 * for enough time to call mxc_set_next_event()
	 */
	local_irq_save(flags);

	/* Disable interrupt in GPT module */
	imxtm->gpt->gpt_irq_disable(imxtm);

	tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
	/* Set event time into far-far future */
	writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);

	/* Clear pending interrupt */
	imxtm->gpt->gpt_irq_acknowledge(imxtm);

#ifdef DEBUG
	printk(KERN_INFO "%s: changing mode\n", __func__);
#endif /* DEBUG */

	local_irq_restore(flags);

	return 0;
}

static int mxc_set_oneshot(struct clock_event_device *ced)
{
	struct imx_timer *imxtm = to_imx_timer(ced);
	unsigned long flags;

	/*
	 * The timer interrupt generation is disabled at least
	 * for enough time to call mxc_set_next_event()
	 */
	local_irq_save(flags);

	/* Disable interrupt in GPT module */
	imxtm->gpt->gpt_irq_disable(imxtm);

	if (!clockevent_state_oneshot(ced)) {
		u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
		/* Set event time into far-far future */
		writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);

		/* Clear pending interrupt */
		imxtm->gpt->gpt_irq_acknowledge(imxtm);
	}

#ifdef DEBUG
	printk(KERN_INFO "%s: changing mode\n", __func__);
#endif /* DEBUG */

	/*
	 * Do not put overhead of interrupt enable/disable into
	 * mxc_set_next_event(), the core has about 4 minutes
	 * to call mxc_set_next_event() or shutdown clock after
	 * mode switching
	 */
	imxtm->gpt->gpt_irq_enable(imxtm);
	local_irq_restore(flags);

	return 0;
}

/*
 * IRQ handler for the timer
 */
static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *ced = dev_id;
	struct imx_timer *imxtm = to_imx_timer(ced);
	uint32_t tstat;

	tstat = readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat);

	imxtm->gpt->gpt_irq_acknowledge(imxtm);

	ced->event_handler(ced);

	return IRQ_HANDLED;
}

static int __init mxc_clockevent_init(struct imx_timer *imxtm)
{
	struct clock_event_device *ced = &imxtm->ced;
	struct irqaction *act = &imxtm->act;

	ced->name = "mxc_timer1";
	ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_DYNIRQ;
	ced->set_state_shutdown = mxc_shutdown;
	ced->set_state_oneshot = mxc_set_oneshot;
	ced->tick_resume = mxc_shutdown;
	ced->set_next_event = imxtm->gpt->set_next_event;
	ced->rating = 200;
	ced->cpumask = cpumask_of(0);
	ced->irq = imxtm->irq;
	clockevents_config_and_register(ced, clk_get_rate(imxtm->clk_per),
					0xff, 0xfffffffe);

	act->name = "i.MX Timer Tick";
	act->flags = IRQF_TIMER | IRQF_IRQPOLL;
	act->handler = mxc_timer_interrupt;
	act->dev_id = ced;

	return setup_irq(imxtm->irq, act);
}

static void imx1_gpt_setup_tctl(struct imx_timer *imxtm)
{
	u32 tctl_val;

	tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
}
#define imx21_gpt_setup_tctl imx1_gpt_setup_tctl

static void imx31_gpt_setup_tctl(struct imx_timer *imxtm)
{
	u32 tctl_val;

	tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8)
		tctl_val |= V2_TCTL_CLK_OSC_DIV8;
	else
		tctl_val |= V2_TCTL_CLK_PER;

	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
}

static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm)
{
	u32 tctl_val;

	tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) {
		tctl_val |= V2_TCTL_CLK_OSC_DIV8;
		/* 24 / 8 = 3 MHz */
		writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER);
		tctl_val |= V2_TCTL_24MEN;
	} else {
		tctl_val |= V2_TCTL_CLK_PER;
	}

	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
}

static const struct imx_gpt_data imx1_gpt_data = {
	.reg_tstat = MX1_2_TSTAT,
	.reg_tcn = MX1_2_TCN,
	.reg_tcmp = MX1_2_TCMP,
	.gpt_irq_enable = imx1_gpt_irq_enable,
	.gpt_irq_disable = imx1_gpt_irq_disable,
	.gpt_irq_acknowledge = imx1_gpt_irq_acknowledge,
	.gpt_setup_tctl = imx1_gpt_setup_tctl,
	.set_next_event = mx1_2_set_next_event,
};

static const struct imx_gpt_data imx21_gpt_data = {
	.reg_tstat = MX1_2_TSTAT,
	.reg_tcn = MX1_2_TCN,
	.reg_tcmp = MX1_2_TCMP,
	.gpt_irq_enable = imx21_gpt_irq_enable,
	.gpt_irq_disable = imx21_gpt_irq_disable,
	.gpt_irq_acknowledge = imx21_gpt_irq_acknowledge,
	.gpt_setup_tctl = imx21_gpt_setup_tctl,
	.set_next_event = mx1_2_set_next_event,
};

static const struct imx_gpt_data imx31_gpt_data = {
	.reg_tstat = V2_TSTAT,
	.reg_tcn = V2_TCN,
	.reg_tcmp = V2_TCMP,
	.gpt_irq_enable = imx31_gpt_irq_enable,
	.gpt_irq_disable = imx31_gpt_irq_disable,
	.gpt_irq_acknowledge = imx31_gpt_irq_acknowledge,
	.gpt_setup_tctl = imx31_gpt_setup_tctl,
	.set_next_event = v2_set_next_event,
};

static const struct imx_gpt_data imx6dl_gpt_data = {
	.reg_tstat = V2_TSTAT,
	.reg_tcn = V2_TCN,
	.reg_tcmp = V2_TCMP,
	.gpt_irq_enable = imx6dl_gpt_irq_enable,
	.gpt_irq_disable = imx6dl_gpt_irq_disable,
	.gpt_irq_acknowledge = imx6dl_gpt_irq_acknowledge,
	.gpt_setup_tctl = imx6dl_gpt_setup_tctl,
	.set_next_event = v2_set_next_event,
};

static void __init _mxc_timer_init(struct imx_timer *imxtm)
{
	switch (imxtm->type) {
	case GPT_TYPE_IMX1:
		imxtm->gpt = &imx1_gpt_data;
		break;
	case GPT_TYPE_IMX21:
		imxtm->gpt = &imx21_gpt_data;
		break;
	case GPT_TYPE_IMX31:
		imxtm->gpt = &imx31_gpt_data;
		break;
	case GPT_TYPE_IMX6DL:
		imxtm->gpt = &imx6dl_gpt_data;
		break;
	default:
		BUG();
	}

	if (IS_ERR(imxtm->clk_per)) {
		pr_err("i.MX timer: unable to get clk\n");
		return;
	}

	if (!IS_ERR(imxtm->clk_ipg))
		clk_prepare_enable(imxtm->clk_ipg);

	clk_prepare_enable(imxtm->clk_per);

	/*
	 * Initialise to a known state (all timers off, and timing reset)
	 */

	writel_relaxed(0, imxtm->base + MXC_TCTL);
	writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */

	imxtm->gpt->gpt_setup_tctl(imxtm);

	/* init and register the timer to the framework */
	mxc_clocksource_init(imxtm);
	mxc_clockevent_init(imxtm);
}

void __init mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type)
{
	struct imx_timer *imxtm;

	imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
	BUG_ON(!imxtm);

	imxtm->clk_per = clk_get_sys("imx-gpt.0", "per");
	imxtm->clk_ipg = clk_get_sys("imx-gpt.0", "ipg");

	imxtm->base = ioremap(pbase, SZ_4K);
	BUG_ON(!imxtm->base);

	imxtm->type = type;
	imxtm->irq = irq;

	_mxc_timer_init(imxtm);
}

static void __init mxc_timer_init_dt(struct device_node *np,  enum imx_gpt_type type)
{
	struct imx_timer *imxtm;
	static int initialized;

	/* Support one instance only */
	if (initialized)
		return;

	imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
	BUG_ON(!imxtm);

	imxtm->base = of_iomap(np, 0);
	WARN_ON(!imxtm->base);
	imxtm->irq = irq_of_parse_and_map(np, 0);

	imxtm->clk_ipg = of_clk_get_by_name(np, "ipg");

	/* Try osc_per first, and fall back to per otherwise */
	imxtm->clk_per = of_clk_get_by_name(np, "osc_per");
	if (IS_ERR(imxtm->clk_per))
		imxtm->clk_per = of_clk_get_by_name(np, "per");

	imxtm->type = type;

	_mxc_timer_init(imxtm);

	initialized = 1;
}

static void __init imx1_timer_init_dt(struct device_node *np)
{
	mxc_timer_init_dt(np, GPT_TYPE_IMX1);
}

static void __init imx21_timer_init_dt(struct device_node *np)
{
	mxc_timer_init_dt(np, GPT_TYPE_IMX21);
}

static void __init imx31_timer_init_dt(struct device_node *np)
{
	enum imx_gpt_type type = GPT_TYPE_IMX31;

	/*
	 * We were using the same compatible string for i.MX6Q/D and i.MX6DL/S
	 * GPT device, while they actually have different programming model.
	 * This is a workaround to keep the existing i.MX6DL/S DTBs continue
	 * working with the new kernel.
	 */
	if (of_machine_is_compatible("fsl,imx6dl"))
		type = GPT_TYPE_IMX6DL;

	mxc_timer_init_dt(np, type);
}

static void __init imx6dl_timer_init_dt(struct device_node *np)
{
	mxc_timer_init_dt(np, GPT_TYPE_IMX6DL);
}

CLOCKSOURCE_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx27_timer, "fsl,imx27-gpt", imx21_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt);
Commit	Line	Data
d0f349fb JB	1	/*
	2	* linux/arch/arm/plat-mxc/time.c
	3	*
	4	* Copyright (C) 2000-2001 Deep Blue Solutions
	5	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
	6	* Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
	7	* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version 2
	12	* of the License, or (at your option) any later version.
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	21	* MA 02110-1301, USA.
	22	*/
	23
	24	#include <linux/interrupt.h>
	25	#include <linux/irq.h>
	26	#include <linux/clockchips.h>
	27	#include <linux/clk.h>
1119c84a	28	#include <linux/delay.h>
821dc4df	29	#include <linux/err.h>
38ff87f7	30	#include <linux/sched_clock.h>
6dd74782	31	#include <linux/slab.h>
876292d6 GC	32	#include <linux/of.h>
	33	#include <linux/of_address.h>
	34	#include <linux/of_irq.h>
0931aff7	35	#include <soc/imx/timer.h>
d0f349fb	36
0f3332c4	37	/*
65d0a16d SW	38	* There are 4 versions of the timer hardware on Freescale MXC hardware.
	39	* - MX1/MXL
	40	* - MX21, MX27.
	41	* - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0)
	42	* - MX6DL, MX6SX, MX6Q(rev1.1+)
0f3332c4 SH	43	*/
0f3332c4 SH	44
ec996ba9 SH	45	/* defines common for all i.MX */
ec996ba9 SH	46	#define MXC_TCTL 0x00
0f3332c4	47	#define MXC_TCTL_TEN (1 << 0) /* Enable module */
ec996ba9 SH	48	#define MXC_TPRER 0x04
	49
	50	/* MX1, MX21, MX27 */
	51	#define MX1_2_TCTL_CLK_PCLK1 (1 << 1)
	52	#define MX1_2_TCTL_IRQEN (1 << 4)
	53	#define MX1_2_TCTL_FRR (1 << 8)
	54	#define MX1_2_TCMP 0x08
	55	#define MX1_2_TCN 0x10
	56	#define MX1_2_TSTAT 0x14
	57
	58	/* MX21, MX27 */
	59	#define MX2_TSTAT_CAPT (1 << 1)
	60	#define MX2_TSTAT_COMP (1 << 0)
	61
bad3db10	62	/* MX31, MX35, MX25, MX5, MX6 */
38a66f51 AK	63	#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
38a66f51 AK	64	#define V2_TCTL_CLK_IPG (1 << 6)
1f152b48	65	#define V2_TCTL_CLK_PER (2 << 6)
bad3db10	66	#define V2_TCTL_CLK_OSC_DIV8 (5 << 6)
38a66f51	67	#define V2_TCTL_FRR (1 << 9)
bad3db10 AH	68	#define V2_TCTL_24MEN (1 << 10)
bad3db10 AH	69	#define V2_TPRER_PRE24M 12
38a66f51 AK	70	#define V2_IR 0x0c
	71	#define V2_TSTAT 0x08
	72	#define V2_TSTAT_OF1 (1 << 0)
	73	#define V2_TCN 0x24
	74	#define V2_TCMP 0x10
d0f349fb	75
bad3db10 AH	76	#define V2_TIMER_RATE_OSC_DIV8 3000000
bad3db10 AH	77
6dd74782	78	struct imx_timer {
0931aff7	79	enum imx_gpt_type type;
6dd74782 SG	80	void __iomem *base;
	81	int irq;
	82	struct clk *clk_per;
	83	struct clk *clk_ipg;
9c8694bd	84	const struct imx_gpt_data *gpt;
e510d201	85	struct clock_event_device ced;
e510d201	86	struct irqaction act;
9c8694bd SG	87	};
	88
	89	struct imx_gpt_data {
24f74ad1 SG	90	int reg_tstat;
	91	int reg_tcn;
	92	int reg_tcmp;
9c8694bd	93	void (gpt_setup_tctl)(struct imx_timer imxtm);
db2ae4b4 SG	94	void (gpt_irq_enable)(struct imx_timer imxtm);
	95	void (gpt_irq_disable)(struct imx_timer imxtm);
	96	void (gpt_irq_acknowledge)(struct imx_timer imxtm);
5ab0475b SG	97	int (*set_next_event)(unsigned long evt,
5ab0475b SG	98	struct clock_event_device *ced);
6dd74782 SG	99	};
6dd74782 SG	100
e510d201 SG	101	static inline struct imx_timer to_imx_timer(struct clock_event_device ced)
	102	{
	103	return container_of(ced, struct imx_timer, ced);
	104	}
	105
db2ae4b4	106	static void imx1_gpt_irq_disable(struct imx_timer *imxtm)
d0f349fb	107	{
ec996ba9 SH	108	unsigned int tmp;
ec996ba9 SH	109
db2ae4b4 SG	110	tmp = readl_relaxed(imxtm->base + MXC_TCTL);
db2ae4b4 SG	111	writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
ec996ba9	112	}
db2ae4b4	113	#define imx21_gpt_irq_disable imx1_gpt_irq_disable
ec996ba9	114
db2ae4b4	115	static void imx31_gpt_irq_disable(struct imx_timer *imxtm)
ec996ba9	116	{
db2ae4b4 SG	117	writel_relaxed(0, imxtm->base + V2_IR);
	118	}
	119	#define imx6dl_gpt_irq_disable imx31_gpt_irq_disable
	120
	121	static void imx1_gpt_irq_enable(struct imx_timer *imxtm)
	122	{
	123	unsigned int tmp;
	124
	125	tmp = readl_relaxed(imxtm->base + MXC_TCTL);
	126	writel_relaxed(tmp \| MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
	127	}
	128	#define imx21_gpt_irq_enable imx1_gpt_irq_enable
	129
	130	static void imx31_gpt_irq_enable(struct imx_timer *imxtm)
	131	{
	132	writel_relaxed(1<<0, imxtm->base + V2_IR);
	133	}
	134	#define imx6dl_gpt_irq_enable imx31_gpt_irq_enable
	135
	136	static void imx1_gpt_irq_acknowledge(struct imx_timer *imxtm)
	137	{
	138	writel_relaxed(0, imxtm->base + MX1_2_TSTAT);
ec996ba9 SH	139	}
ec996ba9 SH	140
db2ae4b4	141	static void imx21_gpt_irq_acknowledge(struct imx_timer *imxtm)
ec996ba9	142	{
db2ae4b4	143	writel_relaxed(MX2_TSTAT_CAPT \| MX2_TSTAT_COMP,
89955520	144	imxtm->base + MX1_2_TSTAT);
ec996ba9 SH	145	}
ec996ba9 SH	146
db2ae4b4 SG	147	static void imx31_gpt_irq_acknowledge(struct imx_timer *imxtm)
	148	{
	149	writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT);
	150	}
	151	#define imx6dl_gpt_irq_acknowledge imx31_gpt_irq_acknowledge
	152
234b6ced	153	static void __iomem *sched_clock_reg;
d0f349fb	154
b93767e3	155	static u64 notrace mxc_read_sched_clock(void)
c124befc	156	{
c7770bba	157	return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0;
c124befc JW	158	}
c124befc JW	159
1119c84a SAS	160	static struct delay_timer imx_delay_timer;
	161
	162	static unsigned long imx_read_current_timer(void)
	163	{
c7770bba	164	return readl_relaxed(sched_clock_reg);
1119c84a SAS	165	}
1119c84a SAS	166
6dd74782	167	static int __init mxc_clocksource_init(struct imx_timer *imxtm)
d0f349fb	168	{
6dd74782	169	unsigned int c = clk_get_rate(imxtm->clk_per);
24f74ad1	170	void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn;
d0f349fb	171
1119c84a SAS	172	imx_delay_timer.read_current_timer = &imx_read_current_timer;
	173	imx_delay_timer.freq = c;
	174	register_current_timer_delay(&imx_delay_timer);
	175
234b6ced	176	sched_clock_reg = reg;
ec996ba9	177
b93767e3	178	sched_clock_register(mxc_read_sched_clock, 32, c);
234b6ced RK	179	return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
234b6ced RK	180	clocksource_mmio_readl_up);
d0f349fb JB	181	}
	182
	183	/* clock event */
	184
ec996ba9	185	static int mx1_2_set_next_event(unsigned long evt,
89955520	186	struct clock_event_device *ced)
d0f349fb	187	{
89955520	188	struct imx_timer *imxtm = to_imx_timer(ced);
d0f349fb JB	189	unsigned long tcmp;
d0f349fb JB	190
89955520	191	tcmp = readl_relaxed(imxtm->base + MX1_2_TCN) + evt;
d0f349fb	192
89955520	193	writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP);
ec996ba9	194
89955520	195	return (int)(tcmp - readl_relaxed(imxtm->base + MX1_2_TCN)) < 0 ?
ec996ba9 SH	196	-ETIME : 0;
	197	}
	198
38a66f51	199	static int v2_set_next_event(unsigned long evt,
89955520	200	struct clock_event_device *ced)
ec996ba9	201	{
89955520	202	struct imx_timer *imxtm = to_imx_timer(ced);
ec996ba9 SH	203	unsigned long tcmp;
ec996ba9 SH	204
89955520	205	tcmp = readl_relaxed(imxtm->base + V2_TCN) + evt;
ec996ba9	206
89955520	207	writel_relaxed(tcmp, imxtm->base + V2_TCMP);
ec996ba9	208
eea8e326	209	return evt < 0x7fffffff &&
89955520	210	(int)(tcmp - readl_relaxed(imxtm->base + V2_TCN)) < 0 ?
d0f349fb JB	211	-ETIME : 0;
	212	}
	213
26b91f04 VK	214	static int mxc_shutdown(struct clock_event_device *ced)
	215	{
	216	struct imx_timer *imxtm = to_imx_timer(ced);
	217	unsigned long flags;
	218	u32 tcn;
	219
	220	/*
	221	* The timer interrupt generation is disabled at least
	222	* for enough time to call mxc_set_next_event()
	223	*/
	224	local_irq_save(flags);
	225
	226	/* Disable interrupt in GPT module */
	227	imxtm->gpt->gpt_irq_disable(imxtm);
	228
	229	tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
	230	/* Set event time into far-far future */
	231	writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);
	232
	233	/* Clear pending interrupt */
	234	imxtm->gpt->gpt_irq_acknowledge(imxtm);
	235
d0f349fb	236	#ifdef DEBUG
26b91f04	237	printk(KERN_INFO "%s: changing mode\n", __func__);
d0f349fb JB	238	#endif /* DEBUG */
d0f349fb JB	239
26b91f04 VK	240	local_irq_restore(flags);
	241
	242	return 0;
	243	}
	244
	245	static int mxc_set_oneshot(struct clock_event_device *ced)
d0f349fb	246	{
e510d201	247	struct imx_timer *imxtm = to_imx_timer(ced);
d0f349fb JB	248	unsigned long flags;
	249
	250	/*
	251	* The timer interrupt generation is disabled at least
	252	* for enough time to call mxc_set_next_event()
	253	*/
	254	local_irq_save(flags);
	255
	256	/* Disable interrupt in GPT module */
db2ae4b4	257	imxtm->gpt->gpt_irq_disable(imxtm);
d0f349fb	258
26b91f04	259	if (!clockevent_state_oneshot(ced)) {
24f74ad1	260	u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
d0f349fb	261	/* Set event time into far-far future */
24f74ad1	262	writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);
ec996ba9	263
d0f349fb	264	/* Clear pending interrupt */
db2ae4b4	265	imxtm->gpt->gpt_irq_acknowledge(imxtm);
d0f349fb JB	266	}
	267
	268	#ifdef DEBUG
26b91f04	269	printk(KERN_INFO "%s: changing mode\n", __func__);
d0f349fb JB	270	#endif /* DEBUG */
d0f349fb JB	271
d0f349fb JB	272	/*
	273	* Do not put overhead of interrupt enable/disable into
	274	* mxc_set_next_event(), the core has about 4 minutes
	275	* to call mxc_set_next_event() or shutdown clock after
	276	* mode switching
	277	*/
26b91f04 VK	278	imxtm->gpt->gpt_irq_enable(imxtm);
	279	local_irq_restore(flags);
	280
	281	return 0;
d0f349fb JB	282	}
	283
	284	/*
	285	* IRQ handler for the timer
	286	*/
	287	static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
	288	{
e510d201	289	struct clock_event_device *ced = dev_id;
24f74ad1	290	struct imx_timer *imxtm = to_imx_timer(ced);
d0f349fb JB	291	uint32_t tstat;
d0f349fb JB	292
24f74ad1	293	tstat = readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat);
d0f349fb	294
db2ae4b4	295	imxtm->gpt->gpt_irq_acknowledge(imxtm);
d0f349fb	296
e510d201	297	ced->event_handler(ced);
d0f349fb JB	298
	299	return IRQ_HANDLED;
	300	}
	301
6dd74782	302	static int __init mxc_clockevent_init(struct imx_timer *imxtm)
d0f349fb	303	{
e510d201 SG	304	struct clock_event_device *ced = &imxtm->ced;
	305	struct irqaction *act = &imxtm->act;
	306
e510d201	307	ced->name = "mxc_timer1";
f1c08c9b	308	ced->features = CLOCK_EVT_FEAT_ONESHOT \| CLOCK_EVT_FEAT_DYNIRQ;
26b91f04 VK	309	ced->set_state_shutdown = mxc_shutdown;
	310	ced->set_state_oneshot = mxc_set_oneshot;
	311	ced->tick_resume = mxc_shutdown;
e510d201 SG	312	ced->set_next_event = imxtm->gpt->set_next_event;
	313	ced->rating = 200;
	314	ced->cpumask = cpumask_of(0);
f1c08c9b	315	ced->irq = imxtm->irq;
e510d201	316	clockevents_config_and_register(ced, clk_get_rate(imxtm->clk_per),
838a2ae8	317	0xff, 0xfffffffe);
d0f349fb	318
e510d201 SG	319	act->name = "i.MX Timer Tick";
	320	act->flags = IRQF_TIMER \| IRQF_IRQPOLL;
	321	act->handler = mxc_timer_interrupt;
	322	act->dev_id = ced;
	323
	324	return setup_irq(imxtm->irq, act);
d0f349fb JB	325	}
d0f349fb JB	326
9c8694bd SG	327	static void imx1_gpt_setup_tctl(struct imx_timer *imxtm)
	328	{
	329	u32 tctl_val;
	330
	331	tctl_val = MX1_2_TCTL_FRR \| MX1_2_TCTL_CLK_PCLK1 \| MXC_TCTL_TEN;
	332	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
	333	}
	334	#define imx21_gpt_setup_tctl imx1_gpt_setup_tctl
	335
	336	static void imx31_gpt_setup_tctl(struct imx_timer *imxtm)
	337	{
	338	u32 tctl_val;
	339
	340	tctl_val = V2_TCTL_FRR \| V2_TCTL_WAITEN \| MXC_TCTL_TEN;
	341	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8)
	342	tctl_val \|= V2_TCTL_CLK_OSC_DIV8;
	343	else
	344	tctl_val \|= V2_TCTL_CLK_PER;
	345
	346	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
	347	}
	348
	349	static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm)
d0f349fb	350	{
9c8694bd SG	351	u32 tctl_val;
	352
	353	tctl_val = V2_TCTL_FRR \| V2_TCTL_WAITEN \| MXC_TCTL_TEN;
	354	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) {
	355	tctl_val \|= V2_TCTL_CLK_OSC_DIV8;
	356	/* 24 / 8 = 3 MHz */
	357	writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER);
	358	tctl_val \|= V2_TCTL_24MEN;
	359	} else {
	360	tctl_val \|= V2_TCTL_CLK_PER;
	361	}
	362
	363	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
	364	}
821dc4df	365
9c8694bd	366	static const struct imx_gpt_data imx1_gpt_data = {
24f74ad1 SG	367	.reg_tstat = MX1_2_TSTAT,
	368	.reg_tcn = MX1_2_TCN,
	369	.reg_tcmp = MX1_2_TCMP,
db2ae4b4 SG	370	.gpt_irq_enable = imx1_gpt_irq_enable,
	371	.gpt_irq_disable = imx1_gpt_irq_disable,
	372	.gpt_irq_acknowledge = imx1_gpt_irq_acknowledge,
9c8694bd	373	.gpt_setup_tctl = imx1_gpt_setup_tctl,
5ab0475b	374	.set_next_event = mx1_2_set_next_event,
9c8694bd SG	375	};
	376
	377	static const struct imx_gpt_data imx21_gpt_data = {
24f74ad1 SG	378	.reg_tstat = MX1_2_TSTAT,
	379	.reg_tcn = MX1_2_TCN,
	380	.reg_tcmp = MX1_2_TCMP,
db2ae4b4 SG	381	.gpt_irq_enable = imx21_gpt_irq_enable,
	382	.gpt_irq_disable = imx21_gpt_irq_disable,
	383	.gpt_irq_acknowledge = imx21_gpt_irq_acknowledge,
9c8694bd	384	.gpt_setup_tctl = imx21_gpt_setup_tctl,
5ab0475b	385	.set_next_event = mx1_2_set_next_event,
9c8694bd SG	386	};
	387
	388	static const struct imx_gpt_data imx31_gpt_data = {
24f74ad1 SG	389	.reg_tstat = V2_TSTAT,
	390	.reg_tcn = V2_TCN,
	391	.reg_tcmp = V2_TCMP,
db2ae4b4 SG	392	.gpt_irq_enable = imx31_gpt_irq_enable,
	393	.gpt_irq_disable = imx31_gpt_irq_disable,
	394	.gpt_irq_acknowledge = imx31_gpt_irq_acknowledge,
9c8694bd	395	.gpt_setup_tctl = imx31_gpt_setup_tctl,
5ab0475b	396	.set_next_event = v2_set_next_event,
9c8694bd SG	397	};
	398
	399	static const struct imx_gpt_data imx6dl_gpt_data = {
24f74ad1 SG	400	.reg_tstat = V2_TSTAT,
	401	.reg_tcn = V2_TCN,
	402	.reg_tcmp = V2_TCMP,
db2ae4b4 SG	403	.gpt_irq_enable = imx6dl_gpt_irq_enable,
	404	.gpt_irq_disable = imx6dl_gpt_irq_disable,
	405	.gpt_irq_acknowledge = imx6dl_gpt_irq_acknowledge,
9c8694bd	406	.gpt_setup_tctl = imx6dl_gpt_setup_tctl,
5ab0475b	407	.set_next_event = v2_set_next_event,
9c8694bd SG	408	};
	409
	410	static void __init _mxc_timer_init(struct imx_timer *imxtm)
	411	{
9c8694bd SG	412	switch (imxtm->type) {
	413	case GPT_TYPE_IMX1:
	414	imxtm->gpt = &imx1_gpt_data;
	415	break;
	416	case GPT_TYPE_IMX21:
	417	imxtm->gpt = &imx21_gpt_data;
	418	break;
	419	case GPT_TYPE_IMX31:
	420	imxtm->gpt = &imx31_gpt_data;
	421	break;
	422	case GPT_TYPE_IMX6DL:
	423	imxtm->gpt = &imx6dl_gpt_data;
	424	break;
	425	default:
	426	BUG();
	427	}
	428
6dd74782	429	if (IS_ERR(imxtm->clk_per)) {
2cfb4518 SH	430	pr_err("i.MX timer: unable to get clk\n");
2cfb4518 SH	431	return;
821dc4df	432	}
ec996ba9	433
6dd74782 SG	434	if (!IS_ERR(imxtm->clk_ipg))
6dd74782 SG	435	clk_prepare_enable(imxtm->clk_ipg);
2cfb4518	436
6dd74782	437	clk_prepare_enable(imxtm->clk_per);
d0f349fb JB	438
	439	/*
	440	* Initialise to a known state (all timers off, and timing reset)
	441	*/
d0f349fb	442
6dd74782 SG	443	writel_relaxed(0, imxtm->base + MXC_TCTL);
6dd74782 SG	444	writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */
ec996ba9	445
9c8694bd	446	imxtm->gpt->gpt_setup_tctl(imxtm);
d0f349fb JB	447
d0f349fb JB	448	/* init and register the timer to the framework */
6dd74782 SG	449	mxc_clocksource_init(imxtm);
6dd74782 SG	450	mxc_clockevent_init(imxtm);
d0f349fb	451	}
876292d6	452
0931aff7	453	void __init mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type)
f4696752	454	{
6dd74782 SG	455	struct imx_timer *imxtm;
	456
	457	imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
	458	BUG_ON(!imxtm);
f4696752	459
6dd74782 SG	460	imxtm->clk_per = clk_get_sys("imx-gpt.0", "per");
6dd74782 SG	461	imxtm->clk_ipg = clk_get_sys("imx-gpt.0", "ipg");
d7f98915	462
6dd74782 SG	463	imxtm->base = ioremap(pbase, SZ_4K);
	464	BUG_ON(!imxtm->base);
	465
0931aff7	466	imxtm->type = type;
be3b0f9b	467	imxtm->irq = irq;
0931aff7	468
6dd74782	469	_mxc_timer_init(imxtm);
f4696752 AS	470	}
f4696752 AS	471
bef11c88	472	static void __init mxc_timer_init_dt(struct device_node *np, enum imx_gpt_type type)
876292d6	473	{
6dd74782 SG	474	struct imx_timer *imxtm;
6dd74782 SG	475	static int initialized;
876292d6	476
6dd74782 SG	477	/* Support one instance only */
6dd74782 SG	478	if (initialized)
fd4959d8 AS	479	return;
fd4959d8 AS	480
6dd74782 SG	481	imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
6dd74782 SG	482	BUG_ON(!imxtm);
876292d6	483
6dd74782 SG	484	imxtm->base = of_iomap(np, 0);
	485	WARN_ON(!imxtm->base);
	486	imxtm->irq = irq_of_parse_and_map(np, 0);
	487
	488	imxtm->clk_ipg = of_clk_get_by_name(np, "ipg");
f4696752	489
bad3db10	490	/* Try osc_per first, and fall back to per otherwise */
6dd74782 SG	491	imxtm->clk_per = of_clk_get_by_name(np, "osc_per");
	492	if (IS_ERR(imxtm->clk_per))
	493	imxtm->clk_per = of_clk_get_by_name(np, "per");
	494
bef11c88 SG	495	imxtm->type = type;
bef11c88 SG	496
6dd74782	497	_mxc_timer_init(imxtm);
bad3db10	498
6dd74782	499	initialized = 1;
876292d6	500	}
bef11c88 SG	501
	502	static void __init imx1_timer_init_dt(struct device_node *np)
	503	{
	504	mxc_timer_init_dt(np, GPT_TYPE_IMX1);
	505	}
	506
	507	static void __init imx21_timer_init_dt(struct device_node *np)
	508	{
	509	mxc_timer_init_dt(np, GPT_TYPE_IMX21);
	510	}
	511
	512	static void __init imx31_timer_init_dt(struct device_node *np)
	513	{
	514	enum imx_gpt_type type = GPT_TYPE_IMX31;
	515
	516	/*
	517	* We were using the same compatible string for i.MX6Q/D and i.MX6DL/S
	518	* GPT device, while they actually have different programming model.
	519	* This is a workaround to keep the existing i.MX6DL/S DTBs continue
	520	* working with the new kernel.
	521	*/
	522	if (of_machine_is_compatible("fsl,imx6dl"))
	523	type = GPT_TYPE_IMX6DL;
	524
	525	mxc_timer_init_dt(np, type);
	526	}
	527
	528	static void __init imx6dl_timer_init_dt(struct device_node *np)
	529	{
	530	mxc_timer_init_dt(np, GPT_TYPE_IMX6DL);
	531	}
	532
	533	CLOCKSOURCE_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt);
	534	CLOCKSOURCE_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt);
747d34e7	535	CLOCKSOURCE_OF_DECLARE(imx27_timer, "fsl,imx27-gpt", imx21_timer_init_dt);
bef11c88 SG	536	CLOCKSOURCE_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt);
	537	CLOCKSOURCE_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt);
	538	CLOCKSOURCE_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt);
	539	CLOCKSOURCE_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt);
	540	CLOCKSOURCE_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt);
	541	CLOCKSOURCE_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt);
	542	CLOCKSOURCE_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt);
	543	CLOCKSOURCE_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt);
	544	CLOCKSOURCE_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt);