Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu
[deliverable/linux.git] / drivers / cpufreq / powernv-cpufreq.c
CommitLineData
b3d627a5
VS
1/*
2 * POWERNV cpufreq driver for the IBM POWER processors
3 *
4 * (C) Copyright IBM 2014
5 *
6 * Author: Vaidyanathan Srinivasan <svaidy at linux.vnet.ibm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#define pr_fmt(fmt) "powernv-cpufreq: " fmt
21
22#include <linux/kernel.h>
23#include <linux/sysfs.h>
24#include <linux/cpumask.h>
25#include <linux/module.h>
26#include <linux/cpufreq.h>
27#include <linux/smp.h>
28#include <linux/of.h>
cf30af76 29#include <linux/reboot.h>
053819e0 30#include <linux/slab.h>
6d167a44 31#include <linux/cpu.h>
c89f2682 32#include <trace/events/power.h>
b3d627a5
VS
33
34#include <asm/cputhreads.h>
6174bac8 35#include <asm/firmware.h>
b3d627a5 36#include <asm/reg.h>
f3cae355 37#include <asm/smp.h> /* Required for cpu_sibling_mask() in UP configs */
cb166fa9 38#include <asm/opal.h>
eaa2c3ae 39#include <linux/timer.h>
b3d627a5
VS
40
41#define POWERNV_MAX_PSTATES 256
09a972d1
SB
42#define PMSR_PSAFE_ENABLE (1UL << 30)
43#define PMSR_SPR_EM_DISABLE (1UL << 31)
44#define PMSR_MAX(x) ((x >> 32) & 0xFF)
b3d627a5 45
eaa2c3ae
AA
46#define MAX_RAMP_DOWN_TIME 5120
47/*
48 * On an idle system we want the global pstate to ramp-down from max value to
49 * min over a span of ~5 secs. Also we want it to initially ramp-down slowly and
50 * then ramp-down rapidly later on.
51 *
52 * This gives a percentage rampdown for time elapsed in milliseconds.
53 * ramp_down_percentage = ((ms * ms) >> 18)
54 * ~= 3.8 * (sec * sec)
55 *
56 * At 0 ms ramp_down_percent = 0
57 * At 5120 ms ramp_down_percent = 100
58 */
59#define ramp_down_percent(time) ((time * time) >> 18)
60
61/* Interval after which the timer is queued to bring down global pstate */
62#define GPSTATE_TIMER_INTERVAL 2000
63
64/**
65 * struct global_pstate_info - Per policy data structure to maintain history of
66 * global pstates
09ca4c9b
AA
67 * @highest_lpstate_idx: The local pstate index from which we are
68 * ramping down
eaa2c3ae 69 * @elapsed_time: Time in ms spent in ramping down from
09ca4c9b 70 * highest_lpstate_idx
eaa2c3ae
AA
71 * @last_sampled_time: Time from boot in ms when global pstates were
72 * last set
09ca4c9b
AA
73 * @last_lpstate_idx, Last set value of local pstate and global
74 * last_gpstate_idx pstate in terms of cpufreq table index
eaa2c3ae
AA
75 * @timer: Is used for ramping down if cpu goes idle for
76 * a long time with global pstate held high
77 * @gpstate_lock: A spinlock to maintain synchronization between
78 * routines called by the timer handler and
79 * governer's target_index calls
80 */
81struct global_pstate_info {
09ca4c9b 82 int highest_lpstate_idx;
eaa2c3ae
AA
83 unsigned int elapsed_time;
84 unsigned int last_sampled_time;
09ca4c9b
AA
85 int last_lpstate_idx;
86 int last_gpstate_idx;
eaa2c3ae
AA
87 spinlock_t gpstate_lock;
88 struct timer_list timer;
89};
90
b3d627a5 91static struct cpufreq_frequency_table powernv_freqs[POWERNV_MAX_PSTATES+1];
cb166fa9 92static bool rebooting, throttled, occ_reset;
b3d627a5 93
c89f2682
SB
94static const char * const throttle_reason[] = {
95 "No throttling",
96 "Power Cap",
97 "Processor Over Temperature",
98 "Power Supply Failure",
99 "Over Current",
100 "OCC Reset"
101};
102
1b028984
SB
103enum throttle_reason_type {
104 NO_THROTTLE = 0,
105 POWERCAP,
106 CPU_OVERTEMP,
107 POWER_SUPPLY_FAILURE,
108 OVERCURRENT,
109 OCC_RESET_THROTTLE,
110 OCC_MAX_REASON
111};
112
053819e0
SB
113static struct chip {
114 unsigned int id;
115 bool throttled;
c89f2682
SB
116 bool restore;
117 u8 throttle_reason;
735366fc
SB
118 cpumask_t mask;
119 struct work_struct throttle;
1b028984
SB
120 int throttle_turbo;
121 int throttle_sub_turbo;
122 int reason[OCC_MAX_REASON];
053819e0
SB
123} *chips;
124
125static int nr_chips;
3e5963bc 126static DEFINE_PER_CPU(struct chip *, chip_info);
053819e0 127
b3d627a5 128/*
09ca4c9b
AA
129 * Note:
130 * The set of pstates consists of contiguous integers.
131 * powernv_pstate_info stores the index of the frequency table for
132 * max, min and nominal frequencies. It also stores number of
133 * available frequencies.
b3d627a5 134 *
09ca4c9b
AA
135 * powernv_pstate_info.nominal indicates the index to the highest
136 * non-turbo frequency.
b3d627a5
VS
137 */
138static struct powernv_pstate_info {
09ca4c9b
AA
139 unsigned int min;
140 unsigned int max;
141 unsigned int nominal;
142 unsigned int nr_pstates;
b3d627a5
VS
143} powernv_pstate_info;
144
09ca4c9b
AA
145/* Use following macros for conversions between pstate_id and index */
146static inline int idx_to_pstate(unsigned int i)
147{
8e859467
AA
148 if (unlikely(i >= powernv_pstate_info.nr_pstates)) {
149 pr_warn_once("index %u is out of bound\n", i);
150 return powernv_freqs[powernv_pstate_info.nominal].driver_data;
151 }
152
09ca4c9b
AA
153 return powernv_freqs[i].driver_data;
154}
155
156static inline unsigned int pstate_to_idx(int pstate)
157{
8e859467
AA
158 int min = powernv_freqs[powernv_pstate_info.min].driver_data;
159 int max = powernv_freqs[powernv_pstate_info.max].driver_data;
160
161 if (min > 0) {
162 if (unlikely((pstate < max) || (pstate > min))) {
163 pr_warn_once("pstate %d is out of bound\n", pstate);
164 return powernv_pstate_info.nominal;
165 }
166 } else {
167 if (unlikely((pstate > max) || (pstate < min))) {
168 pr_warn_once("pstate %d is out of bound\n", pstate);
169 return powernv_pstate_info.nominal;
170 }
171 }
09ca4c9b
AA
172 /*
173 * abs() is deliberately used so that is works with
174 * both monotonically increasing and decreasing
175 * pstate values
176 */
177 return abs(pstate - idx_to_pstate(powernv_pstate_info.max));
178}
179
eaa2c3ae
AA
180static inline void reset_gpstates(struct cpufreq_policy *policy)
181{
182 struct global_pstate_info *gpstates = policy->driver_data;
183
09ca4c9b 184 gpstates->highest_lpstate_idx = 0;
eaa2c3ae
AA
185 gpstates->elapsed_time = 0;
186 gpstates->last_sampled_time = 0;
09ca4c9b
AA
187 gpstates->last_lpstate_idx = 0;
188 gpstates->last_gpstate_idx = 0;
eaa2c3ae
AA
189}
190
b3d627a5
VS
191/*
192 * Initialize the freq table based on data obtained
193 * from the firmware passed via device-tree
194 */
195static int init_powernv_pstates(void)
196{
197 struct device_node *power_mgt;
09ca4c9b 198 int i, nr_pstates = 0;
b3d627a5
VS
199 const __be32 *pstate_ids, *pstate_freqs;
200 u32 len_ids, len_freqs;
09ca4c9b 201 u32 pstate_min, pstate_max, pstate_nominal;
b3d627a5
VS
202
203 power_mgt = of_find_node_by_path("/ibm,opal/power-mgt");
204 if (!power_mgt) {
205 pr_warn("power-mgt node not found\n");
206 return -ENODEV;
207 }
208
209 if (of_property_read_u32(power_mgt, "ibm,pstate-min", &pstate_min)) {
210 pr_warn("ibm,pstate-min node not found\n");
211 return -ENODEV;
212 }
213
214 if (of_property_read_u32(power_mgt, "ibm,pstate-max", &pstate_max)) {
215 pr_warn("ibm,pstate-max node not found\n");
216 return -ENODEV;
217 }
218
219 if (of_property_read_u32(power_mgt, "ibm,pstate-nominal",
220 &pstate_nominal)) {
221 pr_warn("ibm,pstate-nominal not found\n");
222 return -ENODEV;
223 }
224 pr_info("cpufreq pstate min %d nominal %d max %d\n", pstate_min,
225 pstate_nominal, pstate_max);
226
227 pstate_ids = of_get_property(power_mgt, "ibm,pstate-ids", &len_ids);
228 if (!pstate_ids) {
229 pr_warn("ibm,pstate-ids not found\n");
230 return -ENODEV;
231 }
232
233 pstate_freqs = of_get_property(power_mgt, "ibm,pstate-frequencies-mhz",
234 &len_freqs);
235 if (!pstate_freqs) {
236 pr_warn("ibm,pstate-frequencies-mhz not found\n");
237 return -ENODEV;
238 }
239
6174bac8
VS
240 if (len_ids != len_freqs) {
241 pr_warn("Entries in ibm,pstate-ids and "
242 "ibm,pstate-frequencies-mhz does not match\n");
243 }
244
b3d627a5
VS
245 nr_pstates = min(len_ids, len_freqs) / sizeof(u32);
246 if (!nr_pstates) {
247 pr_warn("No PStates found\n");
248 return -ENODEV;
249 }
250
09ca4c9b 251 powernv_pstate_info.nr_pstates = nr_pstates;
b3d627a5
VS
252 pr_debug("NR PStates %d\n", nr_pstates);
253 for (i = 0; i < nr_pstates; i++) {
254 u32 id = be32_to_cpu(pstate_ids[i]);
255 u32 freq = be32_to_cpu(pstate_freqs[i]);
256
257 pr_debug("PState id %d freq %d MHz\n", id, freq);
258 powernv_freqs[i].frequency = freq * 1000; /* kHz */
0692c691 259 powernv_freqs[i].driver_data = id;
09ca4c9b
AA
260
261 if (id == pstate_max)
262 powernv_pstate_info.max = i;
263 else if (id == pstate_nominal)
264 powernv_pstate_info.nominal = i;
265 else if (id == pstate_min)
266 powernv_pstate_info.min = i;
b3d627a5 267 }
09ca4c9b 268
b3d627a5
VS
269 /* End of list marker entry */
270 powernv_freqs[i].frequency = CPUFREQ_TABLE_END;
b3d627a5
VS
271 return 0;
272}
273
274/* Returns the CPU frequency corresponding to the pstate_id. */
275static unsigned int pstate_id_to_freq(int pstate_id)
276{
277 int i;
278
09ca4c9b 279 i = pstate_to_idx(pstate_id);
6174bac8
VS
280 if (i >= powernv_pstate_info.nr_pstates || i < 0) {
281 pr_warn("PState id %d outside of PState table, "
282 "reporting nominal id %d instead\n",
09ca4c9b
AA
283 pstate_id, idx_to_pstate(powernv_pstate_info.nominal));
284 i = powernv_pstate_info.nominal;
6174bac8 285 }
b3d627a5
VS
286
287 return powernv_freqs[i].frequency;
288}
289
290/*
291 * cpuinfo_nominal_freq_show - Show the nominal CPU frequency as indicated by
292 * the firmware
293 */
294static ssize_t cpuinfo_nominal_freq_show(struct cpufreq_policy *policy,
295 char *buf)
296{
297 return sprintf(buf, "%u\n",
09ca4c9b 298 powernv_freqs[powernv_pstate_info.nominal].frequency);
b3d627a5
VS
299}
300
301struct freq_attr cpufreq_freq_attr_cpuinfo_nominal_freq =
302 __ATTR_RO(cpuinfo_nominal_freq);
303
304static struct freq_attr *powernv_cpu_freq_attr[] = {
305 &cpufreq_freq_attr_scaling_available_freqs,
306 &cpufreq_freq_attr_cpuinfo_nominal_freq,
307 NULL,
308};
309
1b028984
SB
310#define throttle_attr(name, member) \
311static ssize_t name##_show(struct cpufreq_policy *policy, char *buf) \
312{ \
313 struct chip *chip = per_cpu(chip_info, policy->cpu); \
314 \
315 return sprintf(buf, "%u\n", chip->member); \
316} \
317 \
318static struct freq_attr throttle_attr_##name = __ATTR_RO(name) \
319
320throttle_attr(unthrottle, reason[NO_THROTTLE]);
321throttle_attr(powercap, reason[POWERCAP]);
322throttle_attr(overtemp, reason[CPU_OVERTEMP]);
323throttle_attr(supply_fault, reason[POWER_SUPPLY_FAILURE]);
324throttle_attr(overcurrent, reason[OVERCURRENT]);
325throttle_attr(occ_reset, reason[OCC_RESET_THROTTLE]);
326throttle_attr(turbo_stat, throttle_turbo);
327throttle_attr(sub_turbo_stat, throttle_sub_turbo);
328
329static struct attribute *throttle_attrs[] = {
330 &throttle_attr_unthrottle.attr,
331 &throttle_attr_powercap.attr,
332 &throttle_attr_overtemp.attr,
333 &throttle_attr_supply_fault.attr,
334 &throttle_attr_overcurrent.attr,
335 &throttle_attr_occ_reset.attr,
336 &throttle_attr_turbo_stat.attr,
337 &throttle_attr_sub_turbo_stat.attr,
338 NULL,
339};
340
341static const struct attribute_group throttle_attr_grp = {
342 .name = "throttle_stats",
343 .attrs = throttle_attrs,
344};
345
b3d627a5
VS
346/* Helper routines */
347
348/* Access helpers to power mgt SPR */
349
350static inline unsigned long get_pmspr(unsigned long sprn)
351{
352 switch (sprn) {
353 case SPRN_PMCR:
354 return mfspr(SPRN_PMCR);
355
356 case SPRN_PMICR:
357 return mfspr(SPRN_PMICR);
358
359 case SPRN_PMSR:
360 return mfspr(SPRN_PMSR);
361 }
362 BUG();
363}
364
365static inline void set_pmspr(unsigned long sprn, unsigned long val)
366{
367 switch (sprn) {
368 case SPRN_PMCR:
369 mtspr(SPRN_PMCR, val);
370 return;
371
372 case SPRN_PMICR:
373 mtspr(SPRN_PMICR, val);
374 return;
375 }
376 BUG();
377}
378
379/*
380 * Use objects of this type to query/update
381 * pstates on a remote CPU via smp_call_function.
382 */
383struct powernv_smp_call_data {
384 unsigned int freq;
385 int pstate_id;
eaa2c3ae 386 int gpstate_id;
b3d627a5
VS
387};
388
389/*
390 * powernv_read_cpu_freq: Reads the current frequency on this CPU.
391 *
392 * Called via smp_call_function.
393 *
394 * Note: The caller of the smp_call_function should pass an argument of
395 * the type 'struct powernv_smp_call_data *' along with this function.
396 *
397 * The current frequency on this CPU will be returned via
398 * ((struct powernv_smp_call_data *)arg)->freq;
399 */
400static void powernv_read_cpu_freq(void *arg)
401{
402 unsigned long pmspr_val;
403 s8 local_pstate_id;
404 struct powernv_smp_call_data *freq_data = arg;
405
406 pmspr_val = get_pmspr(SPRN_PMSR);
407
408 /*
409 * The local pstate id corresponds bits 48..55 in the PMSR.
410 * Note: Watch out for the sign!
411 */
412 local_pstate_id = (pmspr_val >> 48) & 0xFF;
413 freq_data->pstate_id = local_pstate_id;
414 freq_data->freq = pstate_id_to_freq(freq_data->pstate_id);
415
416 pr_debug("cpu %d pmsr %016lX pstate_id %d frequency %d kHz\n",
417 raw_smp_processor_id(), pmspr_val, freq_data->pstate_id,
418 freq_data->freq);
419}
420
421/*
422 * powernv_cpufreq_get: Returns the CPU frequency as reported by the
423 * firmware for CPU 'cpu'. This value is reported through the sysfs
424 * file cpuinfo_cur_freq.
425 */
60d1ea4e 426static unsigned int powernv_cpufreq_get(unsigned int cpu)
b3d627a5
VS
427{
428 struct powernv_smp_call_data freq_data;
429
430 smp_call_function_any(cpu_sibling_mask(cpu), powernv_read_cpu_freq,
431 &freq_data, 1);
432
433 return freq_data.freq;
434}
435
436/*
437 * set_pstate: Sets the pstate on this CPU.
438 *
439 * This is called via an smp_call_function.
440 *
441 * The caller must ensure that freq_data is of the type
442 * (struct powernv_smp_call_data *) and the pstate_id which needs to be set
443 * on this CPU should be present in freq_data->pstate_id.
444 */
eaa2c3ae 445static void set_pstate(void *data)
b3d627a5
VS
446{
447 unsigned long val;
eaa2c3ae
AA
448 struct powernv_smp_call_data *freq_data = data;
449 unsigned long pstate_ul = freq_data->pstate_id;
450 unsigned long gpstate_ul = freq_data->gpstate_id;
b3d627a5
VS
451
452 val = get_pmspr(SPRN_PMCR);
453 val = val & 0x0000FFFFFFFFFFFFULL;
454
455 pstate_ul = pstate_ul & 0xFF;
eaa2c3ae 456 gpstate_ul = gpstate_ul & 0xFF;
b3d627a5
VS
457
458 /* Set both global(bits 56..63) and local(bits 48..55) PStates */
eaa2c3ae 459 val = val | (gpstate_ul << 56) | (pstate_ul << 48);
b3d627a5
VS
460
461 pr_debug("Setting cpu %d pmcr to %016lX\n",
462 raw_smp_processor_id(), val);
463 set_pmspr(SPRN_PMCR, val);
464}
465
cf30af76
SB
466/*
467 * get_nominal_index: Returns the index corresponding to the nominal
468 * pstate in the cpufreq table
469 */
470static inline unsigned int get_nominal_index(void)
471{
09ca4c9b 472 return powernv_pstate_info.nominal;
cf30af76
SB
473}
474
735366fc 475static void powernv_cpufreq_throttle_check(void *data)
09a972d1 476{
3e5963bc 477 struct chip *chip;
735366fc 478 unsigned int cpu = smp_processor_id();
09a972d1 479 unsigned long pmsr;
3e5963bc 480 int pmsr_pmax;
09ca4c9b 481 unsigned int pmsr_pmax_idx;
09a972d1
SB
482
483 pmsr = get_pmspr(SPRN_PMSR);
3e5963bc 484 chip = this_cpu_read(chip_info);
053819e0 485
09a972d1
SB
486 /* Check for Pmax Capping */
487 pmsr_pmax = (s8)PMSR_MAX(pmsr);
09ca4c9b
AA
488 pmsr_pmax_idx = pstate_to_idx(pmsr_pmax);
489 if (pmsr_pmax_idx != powernv_pstate_info.max) {
3e5963bc 490 if (chip->throttled)
053819e0 491 goto next;
3e5963bc 492 chip->throttled = true;
09ca4c9b
AA
493 if (pmsr_pmax_idx > powernv_pstate_info.nominal) {
494 pr_warn_once("CPU %d on Chip %u has Pmax(%d) reduced below nominal frequency(%d)\n",
3e5963bc 495 cpu, chip->id, pmsr_pmax,
09ca4c9b 496 idx_to_pstate(powernv_pstate_info.nominal));
1b028984
SB
497 chip->throttle_sub_turbo++;
498 } else {
499 chip->throttle_turbo++;
500 }
3e5963bc
MN
501 trace_powernv_throttle(chip->id,
502 throttle_reason[chip->throttle_reason],
c89f2682 503 pmsr_pmax);
3e5963bc
MN
504 } else if (chip->throttled) {
505 chip->throttled = false;
506 trace_powernv_throttle(chip->id,
507 throttle_reason[chip->throttle_reason],
c89f2682 508 pmsr_pmax);
09a972d1
SB
509 }
510
3dd3ebe5 511 /* Check if Psafe_mode_active is set in PMSR. */
053819e0 512next:
3dd3ebe5 513 if (pmsr & PMSR_PSAFE_ENABLE) {
09a972d1
SB
514 throttled = true;
515 pr_info("Pstate set to safe frequency\n");
516 }
517
518 /* Check if SPR_EM_DISABLE is set in PMSR */
519 if (pmsr & PMSR_SPR_EM_DISABLE) {
520 throttled = true;
521 pr_info("Frequency Control disabled from OS\n");
522 }
523
524 if (throttled) {
525 pr_info("PMSR = %16lx\n", pmsr);
c89f2682 526 pr_warn("CPU Frequency could be throttled\n");
09a972d1
SB
527 }
528}
529
eaa2c3ae
AA
530/**
531 * calc_global_pstate - Calculate global pstate
09ca4c9b
AA
532 * @elapsed_time: Elapsed time in milliseconds
533 * @local_pstate_idx: New local pstate
534 * @highest_lpstate_idx: pstate from which its ramping down
eaa2c3ae
AA
535 *
536 * Finds the appropriate global pstate based on the pstate from which its
537 * ramping down and the time elapsed in ramping down. It follows a quadratic
538 * equation which ensures that it reaches ramping down to pmin in 5sec.
539 */
540static inline int calc_global_pstate(unsigned int elapsed_time,
09ca4c9b
AA
541 int highest_lpstate_idx,
542 int local_pstate_idx)
eaa2c3ae 543{
09ca4c9b 544 int index_diff;
eaa2c3ae
AA
545
546 /*
547 * Using ramp_down_percent we get the percentage of rampdown
548 * that we are expecting to be dropping. Difference between
09ca4c9b 549 * highest_lpstate_idx and powernv_pstate_info.min will give a absolute
eaa2c3ae
AA
550 * number of how many pstates we will drop eventually by the end of
551 * 5 seconds, then just scale it get the number pstates to be dropped.
552 */
09ca4c9b
AA
553 index_diff = ((int)ramp_down_percent(elapsed_time) *
554 (powernv_pstate_info.min - highest_lpstate_idx)) / 100;
eaa2c3ae
AA
555
556 /* Ensure that global pstate is >= to local pstate */
09ca4c9b
AA
557 if (highest_lpstate_idx + index_diff >= local_pstate_idx)
558 return local_pstate_idx;
eaa2c3ae 559 else
09ca4c9b 560 return highest_lpstate_idx + index_diff;
eaa2c3ae
AA
561}
562
563static inline void queue_gpstate_timer(struct global_pstate_info *gpstates)
564{
565 unsigned int timer_interval;
566
567 /*
568 * Setting up timer to fire after GPSTATE_TIMER_INTERVAL ms, But
569 * if it exceeds MAX_RAMP_DOWN_TIME ms for ramp down time.
570 * Set timer such that it fires exactly at MAX_RAMP_DOWN_TIME
571 * seconds of ramp down time.
572 */
573 if ((gpstates->elapsed_time + GPSTATE_TIMER_INTERVAL)
574 > MAX_RAMP_DOWN_TIME)
575 timer_interval = MAX_RAMP_DOWN_TIME - gpstates->elapsed_time;
576 else
577 timer_interval = GPSTATE_TIMER_INTERVAL;
578
7bc54b65 579 mod_timer(&gpstates->timer, jiffies + msecs_to_jiffies(timer_interval));
eaa2c3ae
AA
580}
581
582/**
583 * gpstate_timer_handler
584 *
585 * @data: pointer to cpufreq_policy on which timer was queued
586 *
587 * This handler brings down the global pstate closer to the local pstate
588 * according quadratic equation. Queues a new timer if it is still not equal
589 * to local pstate
590 */
591void gpstate_timer_handler(unsigned long data)
592{
593 struct cpufreq_policy *policy = (struct cpufreq_policy *)data;
594 struct global_pstate_info *gpstates = policy->driver_data;
09ca4c9b 595 int gpstate_idx;
eaa2c3ae
AA
596 unsigned int time_diff = jiffies_to_msecs(jiffies)
597 - gpstates->last_sampled_time;
598 struct powernv_smp_call_data freq_data;
599
600 if (!spin_trylock(&gpstates->gpstate_lock))
601 return;
602
603 gpstates->last_sampled_time += time_diff;
604 gpstates->elapsed_time += time_diff;
09ca4c9b 605 freq_data.pstate_id = idx_to_pstate(gpstates->last_lpstate_idx);
eaa2c3ae 606
09ca4c9b 607 if ((gpstates->last_gpstate_idx == gpstates->last_lpstate_idx) ||
eaa2c3ae 608 (gpstates->elapsed_time > MAX_RAMP_DOWN_TIME)) {
09ca4c9b 609 gpstate_idx = pstate_to_idx(freq_data.pstate_id);
eaa2c3ae 610 reset_gpstates(policy);
09ca4c9b 611 gpstates->highest_lpstate_idx = gpstate_idx;
eaa2c3ae 612 } else {
09ca4c9b
AA
613 gpstate_idx = calc_global_pstate(gpstates->elapsed_time,
614 gpstates->highest_lpstate_idx,
8e859467 615 gpstates->last_lpstate_idx);
eaa2c3ae
AA
616 }
617
618 /*
619 * If local pstate is equal to global pstate, rampdown is over
620 * So timer is not required to be queued.
621 */
09ca4c9b 622 if (gpstate_idx != gpstates->last_lpstate_idx)
eaa2c3ae
AA
623 queue_gpstate_timer(gpstates);
624
09ca4c9b
AA
625 freq_data.gpstate_id = idx_to_pstate(gpstate_idx);
626 gpstates->last_gpstate_idx = pstate_to_idx(freq_data.gpstate_id);
627 gpstates->last_lpstate_idx = pstate_to_idx(freq_data.pstate_id);
eaa2c3ae 628
1fd3ff28
AA
629 spin_unlock(&gpstates->gpstate_lock);
630
eaa2c3ae
AA
631 /* Timer may get migrated to a different cpu on cpu hot unplug */
632 smp_call_function_any(policy->cpus, set_pstate, &freq_data, 1);
eaa2c3ae
AA
633}
634
b3d627a5
VS
635/*
636 * powernv_cpufreq_target_index: Sets the frequency corresponding to
637 * the cpufreq table entry indexed by new_index on the cpus in the
638 * mask policy->cpus
639 */
640static int powernv_cpufreq_target_index(struct cpufreq_policy *policy,
641 unsigned int new_index)
642{
643 struct powernv_smp_call_data freq_data;
09ca4c9b 644 unsigned int cur_msec, gpstate_idx;
eaa2c3ae 645 struct global_pstate_info *gpstates = policy->driver_data;
b3d627a5 646
cf30af76
SB
647 if (unlikely(rebooting) && new_index != get_nominal_index())
648 return 0;
649
09a972d1 650 if (!throttled)
735366fc 651 powernv_cpufreq_throttle_check(NULL);
09a972d1 652
eaa2c3ae
AA
653 cur_msec = jiffies_to_msecs(get_jiffies_64());
654
1fd3ff28 655 spin_lock(&gpstates->gpstate_lock);
09ca4c9b 656 freq_data.pstate_id = idx_to_pstate(new_index);
b3d627a5 657
eaa2c3ae 658 if (!gpstates->last_sampled_time) {
09ca4c9b
AA
659 gpstate_idx = new_index;
660 gpstates->highest_lpstate_idx = new_index;
eaa2c3ae
AA
661 goto gpstates_done;
662 }
663
09ca4c9b 664 if (gpstates->last_gpstate_idx < new_index) {
eaa2c3ae
AA
665 gpstates->elapsed_time += cur_msec -
666 gpstates->last_sampled_time;
667
668 /*
669 * If its has been ramping down for more than MAX_RAMP_DOWN_TIME
670 * we should be resetting all global pstate related data. Set it
671 * equal to local pstate to start fresh.
672 */
673 if (gpstates->elapsed_time > MAX_RAMP_DOWN_TIME) {
674 reset_gpstates(policy);
09ca4c9b
AA
675 gpstates->highest_lpstate_idx = new_index;
676 gpstate_idx = new_index;
eaa2c3ae
AA
677 } else {
678 /* Elaspsed_time is less than 5 seconds, continue to rampdown */
09ca4c9b
AA
679 gpstate_idx = calc_global_pstate(gpstates->elapsed_time,
680 gpstates->highest_lpstate_idx,
681 new_index);
eaa2c3ae
AA
682 }
683 } else {
684 reset_gpstates(policy);
09ca4c9b
AA
685 gpstates->highest_lpstate_idx = new_index;
686 gpstate_idx = new_index;
eaa2c3ae
AA
687 }
688
689 /*
690 * If local pstate is equal to global pstate, rampdown is over
691 * So timer is not required to be queued.
692 */
09ca4c9b 693 if (gpstate_idx != new_index)
eaa2c3ae 694 queue_gpstate_timer(gpstates);
0bc10b93
AA
695 else
696 del_timer_sync(&gpstates->timer);
eaa2c3ae
AA
697
698gpstates_done:
09ca4c9b 699 freq_data.gpstate_id = idx_to_pstate(gpstate_idx);
eaa2c3ae 700 gpstates->last_sampled_time = cur_msec;
09ca4c9b
AA
701 gpstates->last_gpstate_idx = gpstate_idx;
702 gpstates->last_lpstate_idx = new_index;
eaa2c3ae 703
1fd3ff28
AA
704 spin_unlock(&gpstates->gpstate_lock);
705
b3d627a5
VS
706 /*
707 * Use smp_call_function to send IPI and execute the
708 * mtspr on target CPU. We could do that without IPI
709 * if current CPU is within policy->cpus (core)
710 */
711 smp_call_function_any(policy->cpus, set_pstate, &freq_data, 1);
b3d627a5
VS
712 return 0;
713}
714
715static int powernv_cpufreq_cpu_init(struct cpufreq_policy *policy)
716{
eaa2c3ae 717 int base, i, ret;
2920e9ce 718 struct kernfs_node *kn;
eaa2c3ae 719 struct global_pstate_info *gpstates;
b3d627a5
VS
720
721 base = cpu_first_thread_sibling(policy->cpu);
722
723 for (i = 0; i < threads_per_core; i++)
724 cpumask_set_cpu(base + i, policy->cpus);
725
2920e9ce
SB
726 kn = kernfs_find_and_get(policy->kobj.sd, throttle_attr_grp.name);
727 if (!kn) {
1b028984
SB
728 int ret;
729
730 ret = sysfs_create_group(&policy->kobj, &throttle_attr_grp);
731 if (ret) {
732 pr_info("Failed to create throttle stats directory for cpu %d\n",
733 policy->cpu);
734 return ret;
735 }
2920e9ce
SB
736 } else {
737 kernfs_put(kn);
1b028984 738 }
eaa2c3ae
AA
739
740 gpstates = kzalloc(sizeof(*gpstates), GFP_KERNEL);
741 if (!gpstates)
742 return -ENOMEM;
743
744 policy->driver_data = gpstates;
745
746 /* initialize timer */
7bc54b65 747 init_timer_pinned_deferrable(&gpstates->timer);
eaa2c3ae
AA
748 gpstates->timer.data = (unsigned long)policy;
749 gpstates->timer.function = gpstate_timer_handler;
750 gpstates->timer.expires = jiffies +
751 msecs_to_jiffies(GPSTATE_TIMER_INTERVAL);
752 spin_lock_init(&gpstates->gpstate_lock);
753 ret = cpufreq_table_validate_and_show(policy, powernv_freqs);
754
755 if (ret < 0)
756 kfree(policy->driver_data);
757
758 return ret;
759}
760
761static int powernv_cpufreq_cpu_exit(struct cpufreq_policy *policy)
762{
763 /* timer is deleted in cpufreq_cpu_stop() */
764 kfree(policy->driver_data);
765
766 return 0;
b3d627a5
VS
767}
768
cf30af76
SB
769static int powernv_cpufreq_reboot_notifier(struct notifier_block *nb,
770 unsigned long action, void *unused)
771{
772 int cpu;
773 struct cpufreq_policy cpu_policy;
774
775 rebooting = true;
776 for_each_online_cpu(cpu) {
777 cpufreq_get_policy(&cpu_policy, cpu);
778 powernv_cpufreq_target_index(&cpu_policy, get_nominal_index());
779 }
780
781 return NOTIFY_DONE;
782}
783
784static struct notifier_block powernv_cpufreq_reboot_nb = {
785 .notifier_call = powernv_cpufreq_reboot_notifier,
786};
787
735366fc
SB
788void powernv_cpufreq_work_fn(struct work_struct *work)
789{
790 struct chip *chip = container_of(work, struct chip, throttle);
22794280 791 unsigned int cpu;
6d167a44 792 cpumask_t mask;
735366fc 793
6d167a44
SB
794 get_online_cpus();
795 cpumask_and(&mask, &chip->mask, cpu_online_mask);
796 smp_call_function_any(&mask,
735366fc 797 powernv_cpufreq_throttle_check, NULL, 0);
22794280
SB
798
799 if (!chip->restore)
6d167a44 800 goto out;
22794280
SB
801
802 chip->restore = false;
6d167a44
SB
803 for_each_cpu(cpu, &mask) {
804 int index;
22794280
SB
805 struct cpufreq_policy policy;
806
807 cpufreq_get_policy(&policy, cpu);
82577360 808 index = cpufreq_table_find_index_c(&policy, policy.cur);
22794280 809 powernv_cpufreq_target_index(&policy, index);
6d167a44 810 cpumask_andnot(&mask, &mask, policy.cpus);
22794280 811 }
6d167a44
SB
812out:
813 put_online_cpus();
735366fc
SB
814}
815
cb166fa9
SB
816static int powernv_cpufreq_occ_msg(struct notifier_block *nb,
817 unsigned long msg_type, void *_msg)
818{
819 struct opal_msg *msg = _msg;
820 struct opal_occ_msg omsg;
735366fc 821 int i;
cb166fa9
SB
822
823 if (msg_type != OPAL_MSG_OCC)
824 return 0;
825
826 omsg.type = be64_to_cpu(msg->params[0]);
827
828 switch (omsg.type) {
829 case OCC_RESET:
830 occ_reset = true;
309d0631 831 pr_info("OCC (On Chip Controller - enforces hard thermal/power limits) Resetting\n");
cb166fa9
SB
832 /*
833 * powernv_cpufreq_throttle_check() is called in
834 * target() callback which can detect the throttle state
835 * for governors like ondemand.
836 * But static governors will not call target() often thus
837 * report throttling here.
838 */
839 if (!throttled) {
840 throttled = true;
c89f2682 841 pr_warn("CPU frequency is throttled for duration\n");
cb166fa9 842 }
309d0631 843
cb166fa9
SB
844 break;
845 case OCC_LOAD:
309d0631 846 pr_info("OCC Loading, CPU frequency is throttled until OCC is started\n");
cb166fa9
SB
847 break;
848 case OCC_THROTTLE:
849 omsg.chip = be64_to_cpu(msg->params[1]);
850 omsg.throttle_status = be64_to_cpu(msg->params[2]);
851
852 if (occ_reset) {
853 occ_reset = false;
854 throttled = false;
309d0631 855 pr_info("OCC Active, CPU frequency is no longer throttled\n");
735366fc 856
22794280
SB
857 for (i = 0; i < nr_chips; i++) {
858 chips[i].restore = true;
735366fc 859 schedule_work(&chips[i].throttle);
22794280 860 }
735366fc 861
cb166fa9
SB
862 return 0;
863 }
864
c89f2682
SB
865 for (i = 0; i < nr_chips; i++)
866 if (chips[i].id == omsg.chip)
867 break;
868
869 if (omsg.throttle_status >= 0 &&
1b028984 870 omsg.throttle_status <= OCC_MAX_THROTTLE_STATUS) {
c89f2682 871 chips[i].throttle_reason = omsg.throttle_status;
1b028984
SB
872 chips[i].reason[omsg.throttle_status]++;
873 }
735366fc 874
c89f2682
SB
875 if (!omsg.throttle_status)
876 chips[i].restore = true;
877
878 schedule_work(&chips[i].throttle);
cb166fa9
SB
879 }
880 return 0;
881}
882
883static struct notifier_block powernv_cpufreq_opal_nb = {
884 .notifier_call = powernv_cpufreq_occ_msg,
885 .next = NULL,
886 .priority = 0,
887};
888
b120339c
PM
889static void powernv_cpufreq_stop_cpu(struct cpufreq_policy *policy)
890{
891 struct powernv_smp_call_data freq_data;
eaa2c3ae 892 struct global_pstate_info *gpstates = policy->driver_data;
b120339c 893
09ca4c9b
AA
894 freq_data.pstate_id = idx_to_pstate(powernv_pstate_info.min);
895 freq_data.gpstate_id = idx_to_pstate(powernv_pstate_info.min);
b120339c 896 smp_call_function_single(policy->cpu, set_pstate, &freq_data, 1);
eaa2c3ae 897 del_timer_sync(&gpstates->timer);
b120339c
PM
898}
899
b3d627a5
VS
900static struct cpufreq_driver powernv_cpufreq_driver = {
901 .name = "powernv-cpufreq",
902 .flags = CPUFREQ_CONST_LOOPS,
903 .init = powernv_cpufreq_cpu_init,
eaa2c3ae 904 .exit = powernv_cpufreq_cpu_exit,
b3d627a5
VS
905 .verify = cpufreq_generic_frequency_table_verify,
906 .target_index = powernv_cpufreq_target_index,
907 .get = powernv_cpufreq_get,
b120339c 908 .stop_cpu = powernv_cpufreq_stop_cpu,
b3d627a5
VS
909 .attr = powernv_cpu_freq_attr,
910};
911
053819e0
SB
912static int init_chip_info(void)
913{
914 unsigned int chip[256];
915 unsigned int cpu, i;
916 unsigned int prev_chip_id = UINT_MAX;
96c4726f 917
3e5963bc 918 for_each_possible_cpu(cpu) {
053819e0
SB
919 unsigned int id = cpu_to_chip_id(cpu);
920
921 if (prev_chip_id != id) {
922 prev_chip_id = id;
923 chip[nr_chips++] = id;
924 }
925 }
926
c89f2682 927 chips = kcalloc(nr_chips, sizeof(struct chip), GFP_KERNEL);
053819e0 928 if (!chips)
3e5963bc 929 return -ENOMEM;
053819e0
SB
930
931 for (i = 0; i < nr_chips; i++) {
932 chips[i].id = chip[i];
735366fc
SB
933 cpumask_copy(&chips[i].mask, cpumask_of_node(chip[i]));
934 INIT_WORK(&chips[i].throttle, powernv_cpufreq_work_fn);
3e5963bc
MN
935 for_each_cpu(cpu, &chips[i].mask)
936 per_cpu(chip_info, cpu) = &chips[i];
053819e0
SB
937 }
938
939 return 0;
940}
941
c5e29ea7
SB
942static inline void clean_chip_info(void)
943{
944 kfree(chips);
c5e29ea7
SB
945}
946
947static inline void unregister_all_notifiers(void)
948{
949 opal_message_notifier_unregister(OPAL_MSG_OCC,
950 &powernv_cpufreq_opal_nb);
951 unregister_reboot_notifier(&powernv_cpufreq_reboot_nb);
952}
953
b3d627a5
VS
954static int __init powernv_cpufreq_init(void)
955{
956 int rc = 0;
957
6174bac8 958 /* Don't probe on pseries (guest) platforms */
e4d54f71 959 if (!firmware_has_feature(FW_FEATURE_OPAL))
6174bac8
VS
960 return -ENODEV;
961
b3d627a5
VS
962 /* Discover pstates from device tree and init */
963 rc = init_powernv_pstates();
c5e29ea7
SB
964 if (rc)
965 goto out;
b3d627a5 966
053819e0
SB
967 /* Populate chip info */
968 rc = init_chip_info();
969 if (rc)
c5e29ea7 970 goto out;
053819e0 971
cf30af76 972 register_reboot_notifier(&powernv_cpufreq_reboot_nb);
cb166fa9 973 opal_message_notifier_register(OPAL_MSG_OCC, &powernv_cpufreq_opal_nb);
c5e29ea7
SB
974
975 rc = cpufreq_register_driver(&powernv_cpufreq_driver);
976 if (!rc)
977 return 0;
978
979 pr_info("Failed to register the cpufreq driver (%d)\n", rc);
980 unregister_all_notifiers();
981 clean_chip_info();
982out:
983 pr_info("Platform driver disabled. System does not support PState control\n");
984 return rc;
b3d627a5
VS
985}
986module_init(powernv_cpufreq_init);
987
988static void __exit powernv_cpufreq_exit(void)
989{
990 cpufreq_unregister_driver(&powernv_cpufreq_driver);
c5e29ea7
SB
991 unregister_all_notifiers();
992 clean_chip_info();
b3d627a5
VS
993}
994module_exit(powernv_cpufreq_exit);
995
996MODULE_LICENSE("GPL");
997MODULE_AUTHOR("Vaidyanathan Srinivasan <svaidy at linux.vnet.ibm.com>");
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