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crypto: talitos - second prepare step for adding ahash algorithms
[deliverable/linux.git] / drivers / crypto / talitos.c
CommitLineData
9c4a7965
KP		 1/*
2 * talitos - Freescale Integrated Security Engine (SEC) device driver
3 *
4 * Copyright (c) 2008 Freescale Semiconductor, Inc.
5 *
6 * Scatterlist Crypto API glue code copied from files with the following:
7 * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
8 *
9 * Crypto algorithm registration code copied from hifn driver:
10 * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
11 * All rights reserved.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 */
27
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/mod_devicetable.h>
31#include <linux/device.h>
32#include <linux/interrupt.h>
33#include <linux/crypto.h>
34#include <linux/hw_random.h>
35#include <linux/of_platform.h>
36#include <linux/dma-mapping.h>
37#include <linux/io.h>
38#include <linux/spinlock.h>
39#include <linux/rtnetlink.h>
5a0e3ad6 40#include <linux/slab.h>
9c4a7965
KP		 41
42#include <crypto/algapi.h>
43#include <crypto/aes.h>
3952f17e 44#include <crypto/des.h>
9c4a7965
KP		 45#include <crypto/sha.h>
46#include <crypto/aead.h>
47#include <crypto/authenc.h>
4de9d0b5 48#include <crypto/skcipher.h>
acbf7c62
LN		 49#include <crypto/hash.h>
50#include <crypto/internal/hash.h>
4de9d0b5 51#include <crypto/scatterwalk.h>
9c4a7965
KP		 52
53#include "talitos.h"
54
55#define TALITOS_TIMEOUT 100000
56#define TALITOS_MAX_DATA_LEN 65535
57
58#define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
59#define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
60#define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
61
62/* descriptor pointer entry */
63struct talitos_ptr {
64 __be16 len; /* length */
65 u8 j_extent; /* jump to sg link table and/or extent */
66 u8 eptr; /* extended address */
67 __be32 ptr; /* address */
68};
69
70/* descriptor */
71struct talitos_desc {
72 __be32 hdr; /* header high bits */
73 __be32 hdr_lo; /* header low bits */
74 struct talitos_ptr ptr[7]; /* ptr/len pair array */
75};
76
77/**
78 * talitos_request - descriptor submission request
79 * @desc: descriptor pointer (kernel virtual)
80 * @dma_desc: descriptor's physical bus address
81 * @callback: whom to call when descriptor processing is done
82 * @context: caller context (optional)
83 */
84struct talitos_request {
85 struct talitos_desc *desc;
86 dma_addr_t dma_desc;
87 void (*callback) (struct device *dev, struct talitos_desc *desc,
88 void *context, int error);
89 void *context;
90};
91
4b992628
KP		 92/* per-channel fifo management */
93struct talitos_channel {
94 /* request fifo */
95 struct talitos_request *fifo;
96
97 /* number of requests pending in channel h/w fifo */
98 atomic_t submit_count ____cacheline_aligned;
99
100 /* request submission (head) lock */
101 spinlock_t head_lock ____cacheline_aligned;
102 /* index to next free descriptor request */
103 int head;
104
105 /* request release (tail) lock */
106 spinlock_t tail_lock ____cacheline_aligned;
107 /* index to next in-progress/done descriptor request */
108 int tail;
109};
110
9c4a7965
KP		 111struct talitos_private {
112 struct device *dev;
113 struct of_device *ofdev;
114 void __iomem *reg;
115 int irq;
116
117 /* SEC version geometry (from device tree node) */
118 unsigned int num_channels;
119 unsigned int chfifo_len;
120 unsigned int exec_units;
121 unsigned int desc_types;
122
f3c85bc1
LN		 123 /* SEC Compatibility info */
124 unsigned long features;
125
9c4a7965
KP		 126 /*
127 * length of the request fifo
128 * fifo_len is chfifo_len rounded up to next power of 2
129 * so we can use bitwise ops to wrap
130 */
131 unsigned int fifo_len;
132
4b992628 133 struct talitos_channel *chan;
9c4a7965 134
4b992628
KP		 135 /* next channel to be assigned next incoming descriptor */
136 atomic_t last_chan ____cacheline_aligned;
9c4a7965
KP		 137
138 /* request callback tasklet */
139 struct tasklet_struct done_task;
9c4a7965
KP		 140
141 /* list of registered algorithms */
142 struct list_head alg_list;
143
144 /* hwrng device */
145 struct hwrng rng;
146};
147
f3c85bc1
LN		 148/* .features flag */
149#define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
fe5720e2 150#define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
f3c85bc1 151
81eb024c
KP		 152static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t dma_addr)
153{
154 talitos_ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
155 talitos_ptr->eptr = cpu_to_be32(upper_32_bits(dma_addr));
156}
157
9c4a7965
KP		 158/*
159 * map virtual single (contiguous) pointer to h/w descriptor pointer
160 */
161static void map_single_talitos_ptr(struct device *dev,
162 struct talitos_ptr *talitos_ptr,
163 unsigned short len, void *data,
164 unsigned char extent,
165 enum dma_data_direction dir)
166{
81eb024c
KP		 167 dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
168
9c4a7965 169 talitos_ptr->len = cpu_to_be16(len);
81eb024c 170 to_talitos_ptr(talitos_ptr, dma_addr);
9c4a7965
KP		 171 talitos_ptr->j_extent = extent;
172}
173
174/*
175 * unmap bus single (contiguous) h/w descriptor pointer
176 */
177static void unmap_single_talitos_ptr(struct device *dev,
178 struct talitos_ptr *talitos_ptr,
179 enum dma_data_direction dir)
180{
181 dma_unmap_single(dev, be32_to_cpu(talitos_ptr->ptr),
182 be16_to_cpu(talitos_ptr->len), dir);
183}
184
185static int reset_channel(struct device *dev, int ch)
186{
187 struct talitos_private *priv = dev_get_drvdata(dev);
188 unsigned int timeout = TALITOS_TIMEOUT;
189
190 setbits32(priv->reg + TALITOS_CCCR(ch), TALITOS_CCCR_RESET);
191
192 while ((in_be32(priv->reg + TALITOS_CCCR(ch)) & TALITOS_CCCR_RESET)
193 && --timeout)
194 cpu_relax();
195
196 if (timeout == 0) {
197 dev_err(dev, "failed to reset channel %d\n", ch);
198 return -EIO;
199 }
200
81eb024c
KP		 201 /* set 36-bit addressing, done writeback enable and done IRQ enable */
202 setbits32(priv->reg + TALITOS_CCCR_LO(ch), TALITOS_CCCR_LO_EAE |
203 TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
9c4a7965 204
fe5720e2
KP		 205 /* and ICCR writeback, if available */
206 if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
207 setbits32(priv->reg + TALITOS_CCCR_LO(ch),
208 TALITOS_CCCR_LO_IWSE);
209
9c4a7965
KP		 210 return 0;
211}
212
213static int reset_device(struct device *dev)
214{
215 struct talitos_private *priv = dev_get_drvdata(dev);
216 unsigned int timeout = TALITOS_TIMEOUT;
217
218 setbits32(priv->reg + TALITOS_MCR, TALITOS_MCR_SWR);
219
220 while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS_MCR_SWR)
221 && --timeout)
222 cpu_relax();
223
224 if (timeout == 0) {
225 dev_err(dev, "failed to reset device\n");
226 return -EIO;
227 }
228
229 return 0;
230}
231
232/*
233 * Reset and initialize the device
234 */
235static int init_device(struct device *dev)
236{
237 struct talitos_private *priv = dev_get_drvdata(dev);
238 int ch, err;
239
240 /*
241 * Master reset
242 * errata documentation: warning: certain SEC interrupts
243 * are not fully cleared by writing the MCR:SWR bit,
244 * set bit twice to completely reset
245 */
246 err = reset_device(dev);
247 if (err)
248 return err;
249
250 err = reset_device(dev);
251 if (err)
252 return err;
253
254 /* reset channels */
255 for (ch = 0; ch < priv->num_channels; ch++) {
256 err = reset_channel(dev, ch);
257 if (err)
258 return err;
259 }
260
261 /* enable channel done and error interrupts */
262 setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
263 setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
264
fe5720e2
KP		 265 /* disable integrity check error interrupts (use writeback instead) */
266 if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
267 setbits32(priv->reg + TALITOS_MDEUICR_LO,
268 TALITOS_MDEUICR_LO_ICE);
269
9c4a7965
KP		 270 return 0;
271}
272
273/**
274 * talitos_submit - submits a descriptor to the device for processing
275 * @dev: the SEC device to be used
276 * @desc: the descriptor to be processed by the device
277 * @callback: whom to call when processing is complete
278 * @context: a handle for use by caller (optional)
279 *
280 * desc must contain valid dma-mapped (bus physical) address pointers.
281 * callback must check err and feedback in descriptor header
282 * for device processing status.
283 */
284static int talitos_submit(struct device *dev, struct talitos_desc *desc,
285 void (*callback)(struct device *dev,
286 struct talitos_desc *desc,
287 void *context, int error),
288 void *context)
289{
290 struct talitos_private *priv = dev_get_drvdata(dev);
291 struct talitos_request *request;
292 unsigned long flags, ch;
293 int head;
294
295 /* select done notification */
296 desc->hdr |= DESC_HDR_DONE_NOTIFY;
297
298 /* emulate SEC's round-robin channel fifo polling scheme */
299 ch = atomic_inc_return(&priv->last_chan) & (priv->num_channels - 1);
300
4b992628 301 spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
9c4a7965 302
4b992628 303 if (!atomic_inc_not_zero(&priv->chan[ch].submit_count)) {
ec6644d6 304 /* h/w fifo is full */
4b992628 305 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
9c4a7965
KP		 306 return -EAGAIN;
307 }
308
4b992628
KP		 309 head = priv->chan[ch].head;
310 request = &priv->chan[ch].fifo[head];
ec6644d6 311
9c4a7965
KP		 312 /* map descriptor and save caller data */
313 request->dma_desc = dma_map_single(dev, desc, sizeof(*desc),
314 DMA_BIDIRECTIONAL);
315 request->callback = callback;
316 request->context = context;
317
318 /* increment fifo head */
4b992628 319 priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1);
9c4a7965
KP		 320
321 smp_wmb();
322 request->desc = desc;
323
324 /* GO! */
325 wmb();
81eb024c
KP		 326 out_be32(priv->reg + TALITOS_FF(ch),
327 cpu_to_be32(upper_32_bits(request->dma_desc)));
328 out_be32(priv->reg + TALITOS_FF_LO(ch),
329 cpu_to_be32(lower_32_bits(request->dma_desc)));
9c4a7965 330
4b992628 331 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
9c4a7965
KP		 332
333 return -EINPROGRESS;
334}
335
336/*
337 * process what was done, notify callback of error if not
338 */
339static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
340{
341 struct talitos_private *priv = dev_get_drvdata(dev);
342 struct talitos_request *request, saved_req;
343 unsigned long flags;
344 int tail, status;
345
4b992628 346 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
9c4a7965 347
4b992628
KP		 348 tail = priv->chan[ch].tail;
349 while (priv->chan[ch].fifo[tail].desc) {
350 request = &priv->chan[ch].fifo[tail];
9c4a7965
KP		 351
352 /* descriptors with their done bits set don't get the error */
353 rmb();
ca38a814 354 if ((request->desc->hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
9c4a7965 355 status = 0;
ca38a814 356 else
9c4a7965
KP		 357 if (!error)
358 break;
359 else
360 status = error;
361
362 dma_unmap_single(dev, request->dma_desc,
e938e465
KP		 363 sizeof(struct talitos_desc),
364 DMA_BIDIRECTIONAL);
9c4a7965
KP		 365
366 /* copy entries so we can call callback outside lock */
367 saved_req.desc = request->desc;
368 saved_req.callback = request->callback;
369 saved_req.context = request->context;
370
371 /* release request entry in fifo */
372 smp_wmb();
373 request->desc = NULL;
374
375 /* increment fifo tail */
4b992628 376 priv->chan[ch].tail = (tail + 1) & (priv->fifo_len - 1);
9c4a7965 377
4b992628 378 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
ec6644d6 379
4b992628 380 atomic_dec(&priv->chan[ch].submit_count);
ec6644d6 381
9c4a7965
KP		 382 saved_req.callback(dev, saved_req.desc, saved_req.context,
383 status);
384 /* channel may resume processing in single desc error case */
385 if (error && !reset_ch && status == error)
386 return;
4b992628
KP		 387 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
388 tail = priv->chan[ch].tail;
9c4a7965
KP		 389 }
390
4b992628 391 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
9c4a7965
KP		 392}
393
394/*
395 * process completed requests for channels that have done status
396 */
397static void talitos_done(unsigned long data)
398{
399 struct device *dev = (struct device *)data;
400 struct talitos_private *priv = dev_get_drvdata(dev);
401 int ch;
402
403 for (ch = 0; ch < priv->num_channels; ch++)
404 flush_channel(dev, ch, 0, 0);
1c2e8811
LN		 405
406 /* At this point, all completed channels have been processed.
407 * Unmask done interrupts for channels completed later on.
408 */
fe5720e2
KP		 409 setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
410 setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
9c4a7965
KP		 411}
412
413/*
414 * locate current (offending) descriptor
415 */
416static struct talitos_desc *current_desc(struct device *dev, int ch)
417{
418 struct talitos_private *priv = dev_get_drvdata(dev);
4b992628 419 int tail = priv->chan[ch].tail;
9c4a7965
KP		 420 dma_addr_t cur_desc;
421
422 cur_desc = in_be32(priv->reg + TALITOS_CDPR_LO(ch));
423
4b992628 424 while (priv->chan[ch].fifo[tail].dma_desc != cur_desc) {
9c4a7965 425 tail = (tail + 1) & (priv->fifo_len - 1);
4b992628 426 if (tail == priv->chan[ch].tail) {
9c4a7965
KP		 427 dev_err(dev, "couldn't locate current descriptor\n");
428 return NULL;
429 }
430 }
431
4b992628 432 return priv->chan[ch].fifo[tail].desc;
9c4a7965
KP		 433}
434
435/*
436 * user diagnostics; report root cause of error based on execution unit status
437 */
e938e465
KP		 438static void report_eu_error(struct device *dev, int ch,
439 struct talitos_desc *desc)
9c4a7965
KP		 440{
441 struct talitos_private *priv = dev_get_drvdata(dev);
442 int i;
443
444 switch (desc->hdr & DESC_HDR_SEL0_MASK) {
445 case DESC_HDR_SEL0_AFEU:
446 dev_err(dev, "AFEUISR 0x%08x_%08x\n",
447 in_be32(priv->reg + TALITOS_AFEUISR),
448 in_be32(priv->reg + TALITOS_AFEUISR_LO));
449 break;
450 case DESC_HDR_SEL0_DEU:
451 dev_err(dev, "DEUISR 0x%08x_%08x\n",
452 in_be32(priv->reg + TALITOS_DEUISR),
453 in_be32(priv->reg + TALITOS_DEUISR_LO));
454 break;
455 case DESC_HDR_SEL0_MDEUA:
456 case DESC_HDR_SEL0_MDEUB:
457 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
458 in_be32(priv->reg + TALITOS_MDEUISR),
459 in_be32(priv->reg + TALITOS_MDEUISR_LO));
460 break;
461 case DESC_HDR_SEL0_RNG:
462 dev_err(dev, "RNGUISR 0x%08x_%08x\n",
463 in_be32(priv->reg + TALITOS_RNGUISR),
464 in_be32(priv->reg + TALITOS_RNGUISR_LO));
465 break;
466 case DESC_HDR_SEL0_PKEU:
467 dev_err(dev, "PKEUISR 0x%08x_%08x\n",
468 in_be32(priv->reg + TALITOS_PKEUISR),
469 in_be32(priv->reg + TALITOS_PKEUISR_LO));
470 break;
471 case DESC_HDR_SEL0_AESU:
472 dev_err(dev, "AESUISR 0x%08x_%08x\n",
473 in_be32(priv->reg + TALITOS_AESUISR),
474 in_be32(priv->reg + TALITOS_AESUISR_LO));
475 break;
476 case DESC_HDR_SEL0_CRCU:
477 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
478 in_be32(priv->reg + TALITOS_CRCUISR),
479 in_be32(priv->reg + TALITOS_CRCUISR_LO));
480 break;
481 case DESC_HDR_SEL0_KEU:
482 dev_err(dev, "KEUISR 0x%08x_%08x\n",
483 in_be32(priv->reg + TALITOS_KEUISR),
484 in_be32(priv->reg + TALITOS_KEUISR_LO));
485 break;
486 }
487
488 switch (desc->hdr & DESC_HDR_SEL1_MASK) {
489 case DESC_HDR_SEL1_MDEUA:
490 case DESC_HDR_SEL1_MDEUB:
491 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
492 in_be32(priv->reg + TALITOS_MDEUISR),
493 in_be32(priv->reg + TALITOS_MDEUISR_LO));
494 break;
495 case DESC_HDR_SEL1_CRCU:
496 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
497 in_be32(priv->reg + TALITOS_CRCUISR),
498 in_be32(priv->reg + TALITOS_CRCUISR_LO));
499 break;
500 }
501
502 for (i = 0; i < 8; i++)
503 dev_err(dev, "DESCBUF 0x%08x_%08x\n",
504 in_be32(priv->reg + TALITOS_DESCBUF(ch) + 8*i),
505 in_be32(priv->reg + TALITOS_DESCBUF_LO(ch) + 8*i));
506}
507
508/*
509 * recover from error interrupts
510 */
40405f10 511static void talitos_error(unsigned long data, u32 isr, u32 isr_lo)
9c4a7965
KP		 512{
513 struct device *dev = (struct device *)data;
514 struct talitos_private *priv = dev_get_drvdata(dev);
515 unsigned int timeout = TALITOS_TIMEOUT;
516 int ch, error, reset_dev = 0, reset_ch = 0;
40405f10 517 u32 v, v_lo;
9c4a7965
KP		 518
519 for (ch = 0; ch < priv->num_channels; ch++) {
520 /* skip channels without errors */
521 if (!(isr & (1 << (ch * 2 + 1))))
522 continue;
523
524 error = -EINVAL;
525
526 v = in_be32(priv->reg + TALITOS_CCPSR(ch));
527 v_lo = in_be32(priv->reg + TALITOS_CCPSR_LO(ch));
528
529 if (v_lo & TALITOS_CCPSR_LO_DOF) {
530 dev_err(dev, "double fetch fifo overflow error\n");
531 error = -EAGAIN;
532 reset_ch = 1;
533 }
534 if (v_lo & TALITOS_CCPSR_LO_SOF) {
535 /* h/w dropped descriptor */
536 dev_err(dev, "single fetch fifo overflow error\n");
537 error = -EAGAIN;
538 }
539 if (v_lo & TALITOS_CCPSR_LO_MDTE)
540 dev_err(dev, "master data transfer error\n");
541 if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
542 dev_err(dev, "s/g data length zero error\n");
543 if (v_lo & TALITOS_CCPSR_LO_FPZ)
544 dev_err(dev, "fetch pointer zero error\n");
545 if (v_lo & TALITOS_CCPSR_LO_IDH)
546 dev_err(dev, "illegal descriptor header error\n");
547 if (v_lo & TALITOS_CCPSR_LO_IEU)
548 dev_err(dev, "invalid execution unit error\n");
549 if (v_lo & TALITOS_CCPSR_LO_EU)
550 report_eu_error(dev, ch, current_desc(dev, ch));
551 if (v_lo & TALITOS_CCPSR_LO_GB)
552 dev_err(dev, "gather boundary error\n");
553 if (v_lo & TALITOS_CCPSR_LO_GRL)
554 dev_err(dev, "gather return/length error\n");
555 if (v_lo & TALITOS_CCPSR_LO_SB)
556 dev_err(dev, "scatter boundary error\n");
557 if (v_lo & TALITOS_CCPSR_LO_SRL)
558 dev_err(dev, "scatter return/length error\n");
559
560 flush_channel(dev, ch, error, reset_ch);
561
562 if (reset_ch) {
563 reset_channel(dev, ch);
564 } else {
565 setbits32(priv->reg + TALITOS_CCCR(ch),
566 TALITOS_CCCR_CONT);
567 setbits32(priv->reg + TALITOS_CCCR_LO(ch), 0);
568 while ((in_be32(priv->reg + TALITOS_CCCR(ch)) &
569 TALITOS_CCCR_CONT) && --timeout)
570 cpu_relax();
571 if (timeout == 0) {
572 dev_err(dev, "failed to restart channel %d\n",
573 ch);
574 reset_dev = 1;
575 }
576 }
577 }
578 if (reset_dev || isr & ~TALITOS_ISR_CHERR || isr_lo) {
579 dev_err(dev, "done overflow, internal time out, or rngu error: "
580 "ISR 0x%08x_%08x\n", isr, isr_lo);
581
582 /* purge request queues */
583 for (ch = 0; ch < priv->num_channels; ch++)
584 flush_channel(dev, ch, -EIO, 1);
585
586 /* reset and reinitialize the device */
587 init_device(dev);
588 }
589}
590
591static irqreturn_t talitos_interrupt(int irq, void *data)
592{
593 struct device *dev = data;
594 struct talitos_private *priv = dev_get_drvdata(dev);
595 u32 isr, isr_lo;
596
597 isr = in_be32(priv->reg + TALITOS_ISR);
598 isr_lo = in_be32(priv->reg + TALITOS_ISR_LO);
ca38a814
LN		 599 /* Acknowledge interrupt */
600 out_be32(priv->reg + TALITOS_ICR, isr);
601 out_be32(priv->reg + TALITOS_ICR_LO, isr_lo);
9c4a7965 602
ca38a814 603 if (unlikely((isr & ~TALITOS_ISR_CHDONE) || isr_lo))
40405f10 604 talitos_error((unsigned long)data, isr, isr_lo);
ca38a814 605 else
1c2e8811
LN		 606 if (likely(isr & TALITOS_ISR_CHDONE)) {
607 /* mask further done interrupts. */
608 clrbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_DONE);
609 /* done_task will unmask done interrupts at exit */
9c4a7965 610 tasklet_schedule(&priv->done_task);
1c2e8811 611 }
9c4a7965
KP		 612
613 return (isr || isr_lo) ? IRQ_HANDLED : IRQ_NONE;
614}
615
616/*
617 * hwrng
618 */
619static int talitos_rng_data_present(struct hwrng *rng, int wait)
620{
621 struct device *dev = (struct device *)rng->priv;
622 struct talitos_private *priv = dev_get_drvdata(dev);
623 u32 ofl;
624 int i;
625
626 for (i = 0; i < 20; i++) {
627 ofl = in_be32(priv->reg + TALITOS_RNGUSR_LO) &
628 TALITOS_RNGUSR_LO_OFL;
629 if (ofl || !wait)
630 break;
631 udelay(10);
632 }
633
634 return !!ofl;
635}
636
637static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
638{
639 struct device *dev = (struct device *)rng->priv;
640 struct talitos_private *priv = dev_get_drvdata(dev);
641
642 /* rng fifo requires 64-bit accesses */
643 *data = in_be32(priv->reg + TALITOS_RNGU_FIFO);
644 *data = in_be32(priv->reg + TALITOS_RNGU_FIFO_LO);
645
646 return sizeof(u32);
647}
648
649static int talitos_rng_init(struct hwrng *rng)
650{
651 struct device *dev = (struct device *)rng->priv;
652 struct talitos_private *priv = dev_get_drvdata(dev);
653 unsigned int timeout = TALITOS_TIMEOUT;
654
655 setbits32(priv->reg + TALITOS_RNGURCR_LO, TALITOS_RNGURCR_LO_SR);
656 while (!(in_be32(priv->reg + TALITOS_RNGUSR_LO) & TALITOS_RNGUSR_LO_RD)
657 && --timeout)
658 cpu_relax();
659 if (timeout == 0) {
660 dev_err(dev, "failed to reset rng hw\n");
661 return -ENODEV;
662 }
663
664 /* start generating */
665 setbits32(priv->reg + TALITOS_RNGUDSR_LO, 0);
666
667 return 0;
668}
669
670static int talitos_register_rng(struct device *dev)
671{
672 struct talitos_private *priv = dev_get_drvdata(dev);
673
674 priv->rng.name = dev_driver_string(dev),
675 priv->rng.init = talitos_rng_init,
676 priv->rng.data_present = talitos_rng_data_present,
677 priv->rng.data_read = talitos_rng_data_read,
678 priv->rng.priv = (unsigned long)dev;
679
680 return hwrng_register(&priv->rng);
681}
682
683static void talitos_unregister_rng(struct device *dev)
684{
685 struct talitos_private *priv = dev_get_drvdata(dev);
686
687 hwrng_unregister(&priv->rng);
688}
689
690/*
691 * crypto alg
692 */
693#define TALITOS_CRA_PRIORITY 3000
694#define TALITOS_MAX_KEY_SIZE 64
3952f17e 695#define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
70bcaca7 696
3952f17e 697#define MD5_DIGEST_SIZE 16
9c4a7965
KP		 698
699struct talitos_ctx {
700 struct device *dev;
701 __be32 desc_hdr_template;
702 u8 key[TALITOS_MAX_KEY_SIZE];
70bcaca7 703 u8 iv[TALITOS_MAX_IV_LENGTH];
9c4a7965
KP		 704 unsigned int keylen;
705 unsigned int enckeylen;
706 unsigned int authkeylen;
707 unsigned int authsize;
708};
709
56af8cd4
LN		 710static int aead_setauthsize(struct crypto_aead *authenc,
711 unsigned int authsize)
9c4a7965
KP		 712{
713 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
714
715 ctx->authsize = authsize;
716
717 return 0;
718}
719
56af8cd4
LN		 720static int aead_setkey(struct crypto_aead *authenc,
721 const u8 *key, unsigned int keylen)
9c4a7965
KP		 722{
723 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
724 struct rtattr *rta = (void *)key;
725 struct crypto_authenc_key_param *param;
726 unsigned int authkeylen;
727 unsigned int enckeylen;
728
729 if (!RTA_OK(rta, keylen))
730 goto badkey;
731
732 if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM)
733 goto badkey;
734
735 if (RTA_PAYLOAD(rta) < sizeof(*param))
736 goto badkey;
737
738 param = RTA_DATA(rta);
739 enckeylen = be32_to_cpu(param->enckeylen);
740
741 key += RTA_ALIGN(rta->rta_len);
742 keylen -= RTA_ALIGN(rta->rta_len);
743
744 if (keylen < enckeylen)
745 goto badkey;
746
747 authkeylen = keylen - enckeylen;
748
749 if (keylen > TALITOS_MAX_KEY_SIZE)
750 goto badkey;
751
752 memcpy(&ctx->key, key, keylen);
753
754 ctx->keylen = keylen;
755 ctx->enckeylen = enckeylen;
756 ctx->authkeylen = authkeylen;
757
758 return 0;
759
760badkey:
761 crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
762 return -EINVAL;
763}
764
765/*
56af8cd4 766 * talitos_edesc - s/w-extended descriptor
9c4a7965
KP		 767 * @src_nents: number of segments in input scatterlist
768 * @dst_nents: number of segments in output scatterlist
769 * @dma_len: length of dma mapped link_tbl space
770 * @dma_link_tbl: bus physical address of link_tbl
771 * @desc: h/w descriptor
772 * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1)
773 *
774 * if decrypting (with authcheck), or either one of src_nents or dst_nents
775 * is greater than 1, an integrity check value is concatenated to the end
776 * of link_tbl data
777 */
56af8cd4 778struct talitos_edesc {
9c4a7965
KP		 779 int src_nents;
780 int dst_nents;
4de9d0b5
LN		 781 int src_is_chained;
782 int dst_is_chained;
9c4a7965
KP		 783 int dma_len;
784 dma_addr_t dma_link_tbl;
785 struct talitos_desc desc;
786 struct talitos_ptr link_tbl[0];
787};
788
4de9d0b5
LN		 789static int talitos_map_sg(struct device *dev, struct scatterlist *sg,
790 unsigned int nents, enum dma_data_direction dir,
791 int chained)
792{
793 if (unlikely(chained))
794 while (sg) {
795 dma_map_sg(dev, sg, 1, dir);
796 sg = scatterwalk_sg_next(sg);
797 }
798 else
799 dma_map_sg(dev, sg, nents, dir);
800 return nents;
801}
802
803static void talitos_unmap_sg_chain(struct device *dev, struct scatterlist *sg,
804 enum dma_data_direction dir)
805{
806 while (sg) {
807 dma_unmap_sg(dev, sg, 1, dir);
808 sg = scatterwalk_sg_next(sg);
809 }
810}
811
812static void talitos_sg_unmap(struct device *dev,
813 struct talitos_edesc *edesc,
814 struct scatterlist *src,
815 struct scatterlist *dst)
816{
817 unsigned int src_nents = edesc->src_nents ? : 1;
818 unsigned int dst_nents = edesc->dst_nents ? : 1;
819
820 if (src != dst) {
821 if (edesc->src_is_chained)
822 talitos_unmap_sg_chain(dev, src, DMA_TO_DEVICE);
823 else
824 dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
825
826 if (edesc->dst_is_chained)
827 talitos_unmap_sg_chain(dev, dst, DMA_FROM_DEVICE);
828 else
829 dma_unmap_sg(dev, dst, dst_nents, DMA_FROM_DEVICE);
830 } else
831 if (edesc->src_is_chained)
832 talitos_unmap_sg_chain(dev, src, DMA_BIDIRECTIONAL);
833 else
834 dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
835}
836
9c4a7965 837static void ipsec_esp_unmap(struct device *dev,
56af8cd4 838 struct talitos_edesc *edesc,
9c4a7965
KP		 839 struct aead_request *areq)
840{
841 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE);
842 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE);
843 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
844 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE);
845
846 dma_unmap_sg(dev, areq->assoc, 1, DMA_TO_DEVICE);
847
4de9d0b5 848 talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
9c4a7965
KP		 849
850 if (edesc->dma_len)
851 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
852 DMA_BIDIRECTIONAL);
853}
854
855/*
856 * ipsec_esp descriptor callbacks
857 */
858static void ipsec_esp_encrypt_done(struct device *dev,
859 struct talitos_desc *desc, void *context,
860 int err)
861{
862 struct aead_request *areq = context;
9c4a7965
KP		 863 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
864 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
19bbbc63 865 struct talitos_edesc *edesc;
9c4a7965
KP		 866 struct scatterlist *sg;
867 void *icvdata;
868
19bbbc63
KP		 869 edesc = container_of(desc, struct talitos_edesc, desc);
870
9c4a7965
KP		 871 ipsec_esp_unmap(dev, edesc, areq);
872
873 /* copy the generated ICV to dst */
874 if (edesc->dma_len) {
875 icvdata = &edesc->link_tbl[edesc->src_nents +
f3c85bc1 876 edesc->dst_nents + 2];
9c4a7965
KP		 877 sg = sg_last(areq->dst, edesc->dst_nents);
878 memcpy((char *)sg_virt(sg) + sg->length - ctx->authsize,
879 icvdata, ctx->authsize);
880 }
881
882 kfree(edesc);
883
884 aead_request_complete(areq, err);
885}
886
fe5720e2 887static void ipsec_esp_decrypt_swauth_done(struct device *dev,
e938e465
KP		 888 struct talitos_desc *desc,
889 void *context, int err)
9c4a7965
KP		 890{
891 struct aead_request *req = context;
9c4a7965
KP		 892 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
893 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
19bbbc63 894 struct talitos_edesc *edesc;
9c4a7965
KP		 895 struct scatterlist *sg;
896 void *icvdata;
897
19bbbc63
KP		 898 edesc = container_of(desc, struct talitos_edesc, desc);
899
9c4a7965
KP		 900 ipsec_esp_unmap(dev, edesc, req);
901
902 if (!err) {
903 /* auth check */
904 if (edesc->dma_len)
905 icvdata = &edesc->link_tbl[edesc->src_nents +
f3c85bc1 906 edesc->dst_nents + 2];
9c4a7965
KP		 907 else
908 icvdata = &edesc->link_tbl[0];
909
910 sg = sg_last(req->dst, edesc->dst_nents ? : 1);
911 err = memcmp(icvdata, (char *)sg_virt(sg) + sg->length -
912 ctx->authsize, ctx->authsize) ? -EBADMSG : 0;
913 }
914
915 kfree(edesc);
916
917 aead_request_complete(req, err);
918}
919
fe5720e2 920static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
e938e465
KP		 921 struct talitos_desc *desc,
922 void *context, int err)
fe5720e2
KP		 923{
924 struct aead_request *req = context;
19bbbc63
KP		 925 struct talitos_edesc *edesc;
926
927 edesc = container_of(desc, struct talitos_edesc, desc);
fe5720e2
KP		 928
929 ipsec_esp_unmap(dev, edesc, req);
930
931 /* check ICV auth status */
e938e465
KP		 932 if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
933 DESC_HDR_LO_ICCR1_PASS))
934 err = -EBADMSG;
fe5720e2
KP		 935
936 kfree(edesc);
937
938 aead_request_complete(req, err);
939}
940
9c4a7965
KP		 941/*
942 * convert scatterlist to SEC h/w link table format
943 * stop at cryptlen bytes
944 */
70bcaca7 945static int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
9c4a7965
KP		 946 int cryptlen, struct talitos_ptr *link_tbl_ptr)
947{
70bcaca7
LN		 948 int n_sg = sg_count;
949
950 while (n_sg--) {
81eb024c 951 to_talitos_ptr(link_tbl_ptr, sg_dma_address(sg));
9c4a7965
KP		 952 link_tbl_ptr->len = cpu_to_be16(sg_dma_len(sg));
953 link_tbl_ptr->j_extent = 0;
954 link_tbl_ptr++;
955 cryptlen -= sg_dma_len(sg);
4de9d0b5 956 sg = scatterwalk_sg_next(sg);
9c4a7965
KP		 957 }
958
70bcaca7 959 /* adjust (decrease) last one (or two) entry's len to cryptlen */
9c4a7965 960 link_tbl_ptr--;
c0e741d4 961 while (be16_to_cpu(link_tbl_ptr->len) <= (-cryptlen)) {
70bcaca7
LN		 962 /* Empty this entry, and move to previous one */
963 cryptlen += be16_to_cpu(link_tbl_ptr->len);
964 link_tbl_ptr->len = 0;
965 sg_count--;
966 link_tbl_ptr--;
967 }
9c4a7965
KP		 968 link_tbl_ptr->len = cpu_to_be16(be16_to_cpu(link_tbl_ptr->len)
969 + cryptlen);
970
971 /* tag end of link table */
972 link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
70bcaca7
LN		 973
974 return sg_count;
9c4a7965
KP		 975}
976
977/*
978 * fill in and submit ipsec_esp descriptor
979 */
56af8cd4 980static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
9c4a7965
KP		 981 u8 *giv, u64 seq,
982 void (*callback) (struct device *dev,
983 struct talitos_desc *desc,
984 void *context, int error))
985{
986 struct crypto_aead *aead = crypto_aead_reqtfm(areq);
987 struct talitos_ctx *ctx = crypto_aead_ctx(aead);
988 struct device *dev = ctx->dev;
989 struct talitos_desc *desc = &edesc->desc;
990 unsigned int cryptlen = areq->cryptlen;
991 unsigned int authsize = ctx->authsize;
e41256f1 992 unsigned int ivsize = crypto_aead_ivsize(aead);
fa86a267 993 int sg_count, ret;
fe5720e2 994 int sg_link_tbl_len;
9c4a7965
KP		 995
996 /* hmac key */
997 map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
998 0, DMA_TO_DEVICE);
999 /* hmac data */
e41256f1
KP		 1000 map_single_talitos_ptr(dev, &desc->ptr[1], areq->assoclen + ivsize,
1001 sg_virt(areq->assoc), 0, DMA_TO_DEVICE);
9c4a7965 1002 /* cipher iv */
9c4a7965
KP		 1003 map_single_talitos_ptr(dev, &desc->ptr[2], ivsize, giv ?: areq->iv, 0,
1004 DMA_TO_DEVICE);
1005
1006 /* cipher key */
1007 map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen,
1008 (char *)&ctx->key + ctx->authkeylen, 0,
1009 DMA_TO_DEVICE);
1010
1011 /*
1012 * cipher in
1013 * map and adjust cipher len to aead request cryptlen.
1014 * extent is bytes of HMAC postpended to ciphertext,
1015 * typically 12 for ipsec
1016 */
1017 desc->ptr[4].len = cpu_to_be16(cryptlen);
1018 desc->ptr[4].j_extent = authsize;
1019
e938e465
KP		 1020 sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1021 (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1022 : DMA_TO_DEVICE,
4de9d0b5 1023 edesc->src_is_chained);
9c4a7965
KP		 1024
1025 if (sg_count == 1) {
81eb024c 1026 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src));
9c4a7965 1027 } else {
fe5720e2
KP		 1028 sg_link_tbl_len = cryptlen;
1029
962a9c99 1030 if (edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV)
fe5720e2 1031 sg_link_tbl_len = cryptlen + authsize;
e938e465 1032
fe5720e2 1033 sg_count = sg_to_link_tbl(areq->src, sg_count, sg_link_tbl_len,
70bcaca7
LN		 1034 &edesc->link_tbl[0]);
1035 if (sg_count > 1) {
1036 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
81eb024c 1037 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl);
e938e465
KP		 1038 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1039 edesc->dma_len,
1040 DMA_BIDIRECTIONAL);
70bcaca7
LN		 1041 } else {
1042 /* Only one segment now, so no link tbl needed */
81eb024c
KP		 1043 to_talitos_ptr(&desc->ptr[4],
1044 sg_dma_address(areq->src));
70bcaca7 1045 }
9c4a7965
KP		 1046 }
1047
1048 /* cipher out */
1049 desc->ptr[5].len = cpu_to_be16(cryptlen);
1050 desc->ptr[5].j_extent = authsize;
1051
e938e465 1052 if (areq->src != areq->dst)
4de9d0b5
LN		 1053 sg_count = talitos_map_sg(dev, areq->dst,
1054 edesc->dst_nents ? : 1,
1055 DMA_FROM_DEVICE,
1056 edesc->dst_is_chained);
9c4a7965
KP		 1057
1058 if (sg_count == 1) {
81eb024c 1059 to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst));
9c4a7965
KP		 1060 } else {
1061 struct talitos_ptr *link_tbl_ptr =
f3c85bc1 1062 &edesc->link_tbl[edesc->src_nents + 1];
9c4a7965 1063
81eb024c
KP		 1064 to_talitos_ptr(&desc->ptr[5], edesc->dma_link_tbl +
1065 (edesc->src_nents + 1) *
1066 sizeof(struct talitos_ptr));
fe5720e2
KP		 1067 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1068 link_tbl_ptr);
1069
f3c85bc1 1070 /* Add an entry to the link table for ICV data */
9c4a7965 1071 link_tbl_ptr += sg_count - 1;
9c4a7965 1072 link_tbl_ptr->j_extent = 0;
f3c85bc1 1073 sg_count++;
9c4a7965
KP		 1074 link_tbl_ptr++;
1075 link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
1076 link_tbl_ptr->len = cpu_to_be16(authsize);
1077
1078 /* icv data follows link tables */
81eb024c
KP		 1079 to_talitos_ptr(link_tbl_ptr, edesc->dma_link_tbl +
1080 (edesc->src_nents + edesc->dst_nents + 2) *
1081 sizeof(struct talitos_ptr));
9c4a7965
KP		 1082 desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
1083 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1084 edesc->dma_len, DMA_BIDIRECTIONAL);
1085 }
1086
1087 /* iv out */
1088 map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, 0,
1089 DMA_FROM_DEVICE);
1090
fa86a267
KP		 1091 ret = talitos_submit(dev, desc, callback, areq);
1092 if (ret != -EINPROGRESS) {
1093 ipsec_esp_unmap(dev, edesc, areq);
1094 kfree(edesc);
1095 }
1096 return ret;
9c4a7965
KP		 1097}
1098
9c4a7965
KP		 1099/*
1100 * derive number of elements in scatterlist
1101 */
4de9d0b5 1102static int sg_count(struct scatterlist *sg_list, int nbytes, int *chained)
9c4a7965
KP		 1103{
1104 struct scatterlist *sg = sg_list;
1105 int sg_nents = 0;
1106
4de9d0b5
LN		 1107 *chained = 0;
1108 while (nbytes > 0) {
9c4a7965
KP		 1109 sg_nents++;
1110 nbytes -= sg->length;
4de9d0b5
LN		 1111 if (!sg_is_last(sg) && (sg + 1)->length == 0)
1112 *chained = 1;
1113 sg = scatterwalk_sg_next(sg);
9c4a7965
KP		 1114 }
1115
1116 return sg_nents;
1117}
1118
1119/*
56af8cd4 1120 * allocate and map the extended descriptor
9c4a7965 1121 */
4de9d0b5
LN		 1122static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
1123 struct scatterlist *src,
1124 struct scatterlist *dst,
1125 unsigned int cryptlen,
1126 unsigned int authsize,
1127 int icv_stashing,
1128 u32 cryptoflags)
9c4a7965 1129{
56af8cd4 1130 struct talitos_edesc *edesc;
9c4a7965 1131 int src_nents, dst_nents, alloc_len, dma_len;
4de9d0b5
LN		 1132 int src_chained, dst_chained = 0;
1133 gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
586725f8 1134 GFP_ATOMIC;
9c4a7965 1135
4de9d0b5
LN		 1136 if (cryptlen + authsize > TALITOS_MAX_DATA_LEN) {
1137 dev_err(dev, "length exceeds h/w max limit\n");
9c4a7965
KP		 1138 return ERR_PTR(-EINVAL);
1139 }
1140
4de9d0b5 1141 src_nents = sg_count(src, cryptlen + authsize, &src_chained);
9c4a7965
KP		 1142 src_nents = (src_nents == 1) ? 0 : src_nents;
1143
4de9d0b5 1144 if (dst == src) {
9c4a7965
KP		 1145 dst_nents = src_nents;
1146 } else {
4de9d0b5 1147 dst_nents = sg_count(dst, cryptlen + authsize, &dst_chained);
695ad589 1148 dst_nents = (dst_nents == 1) ? 0 : dst_nents;
9c4a7965
KP		 1149 }
1150
1151 /*
1152 * allocate space for base edesc plus the link tables,
f3c85bc1 1153 * allowing for two separate entries for ICV and generated ICV (+ 2),
9c4a7965
KP		 1154 * and the ICV data itself
1155 */
56af8cd4 1156 alloc_len = sizeof(struct talitos_edesc);
9c4a7965 1157 if (src_nents || dst_nents) {
f3c85bc1 1158 dma_len = (src_nents + dst_nents + 2) *
4de9d0b5 1159 sizeof(struct talitos_ptr) + authsize;
9c4a7965
KP		 1160 alloc_len += dma_len;
1161 } else {
1162 dma_len = 0;
4de9d0b5 1163 alloc_len += icv_stashing ? authsize : 0;
9c4a7965
KP		 1164 }
1165
586725f8 1166 edesc = kmalloc(alloc_len, GFP_DMA | flags);
9c4a7965 1167 if (!edesc) {
4de9d0b5 1168 dev_err(dev, "could not allocate edescriptor\n");
9c4a7965
KP		 1169 return ERR_PTR(-ENOMEM);
1170 }
1171
1172 edesc->src_nents = src_nents;
1173 edesc->dst_nents = dst_nents;
4de9d0b5
LN		 1174 edesc->src_is_chained = src_chained;
1175 edesc->dst_is_chained = dst_chained;
9c4a7965 1176 edesc->dma_len = dma_len;
4de9d0b5 1177 edesc->dma_link_tbl = dma_map_single(dev, &edesc->link_tbl[0],
9c4a7965
KP		 1178 edesc->dma_len, DMA_BIDIRECTIONAL);
1179
1180 return edesc;
1181}
1182
4de9d0b5
LN		 1183static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq,
1184 int icv_stashing)
1185{
1186 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1187 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1188
1189 return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst,
1190 areq->cryptlen, ctx->authsize, icv_stashing,
1191 areq->base.flags);
1192}
1193
56af8cd4 1194static int aead_encrypt(struct aead_request *req)
9c4a7965
KP		 1195{
1196 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1197 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
56af8cd4 1198 struct talitos_edesc *edesc;
9c4a7965
KP		 1199
1200 /* allocate extended descriptor */
4de9d0b5 1201 edesc = aead_edesc_alloc(req, 0);
9c4a7965
KP		 1202 if (IS_ERR(edesc))
1203 return PTR_ERR(edesc);
1204
1205 /* set encrypt */
70bcaca7 1206 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
9c4a7965
KP		 1207
1208 return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_encrypt_done);
1209}
1210
56af8cd4 1211static int aead_decrypt(struct aead_request *req)
9c4a7965
KP		 1212{
1213 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1214 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1215 unsigned int authsize = ctx->authsize;
fe5720e2 1216 struct talitos_private *priv = dev_get_drvdata(ctx->dev);
56af8cd4 1217 struct talitos_edesc *edesc;
9c4a7965
KP		 1218 struct scatterlist *sg;
1219 void *icvdata;
1220
1221 req->cryptlen -= authsize;
1222
1223 /* allocate extended descriptor */
4de9d0b5 1224 edesc = aead_edesc_alloc(req, 1);
9c4a7965
KP		 1225 if (IS_ERR(edesc))
1226 return PTR_ERR(edesc);
1227
fe5720e2 1228 if ((priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
e938e465
KP		 1229 ((!edesc->src_nents && !edesc->dst_nents) ||
1230 priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
9c4a7965 1231
fe5720e2 1232 /* decrypt and check the ICV */
e938e465
KP		 1233 edesc->desc.hdr = ctx->desc_hdr_template |
1234 DESC_HDR_DIR_INBOUND |
fe5720e2 1235 DESC_HDR_MODE1_MDEU_CICV;
9c4a7965 1236
fe5720e2
KP		 1237 /* reset integrity check result bits */
1238 edesc->desc.hdr_lo = 0;
9c4a7965 1239
e938e465
KP		 1240 return ipsec_esp(edesc, req, NULL, 0,
1241 ipsec_esp_decrypt_hwauth_done);
fe5720e2 1242
e938e465 1243 }
fe5720e2 1244
e938e465
KP		 1245 /* Have to check the ICV with software */
1246 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
fe5720e2 1247
e938e465
KP		 1248 /* stash incoming ICV for later cmp with ICV generated by the h/w */
1249 if (edesc->dma_len)
1250 icvdata = &edesc->link_tbl[edesc->src_nents +
1251 edesc->dst_nents + 2];
1252 else
1253 icvdata = &edesc->link_tbl[0];
fe5720e2 1254
e938e465 1255 sg = sg_last(req->src, edesc->src_nents ? : 1);
fe5720e2 1256
e938e465
KP		 1257 memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize,
1258 ctx->authsize);
fe5720e2 1259
e938e465 1260 return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_decrypt_swauth_done);
9c4a7965
KP		 1261}
1262
56af8cd4 1263static int aead_givencrypt(struct aead_givcrypt_request *req)
9c4a7965
KP		 1264{
1265 struct aead_request *areq = &req->areq;
1266 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1267 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
56af8cd4 1268 struct talitos_edesc *edesc;
9c4a7965
KP		 1269
1270 /* allocate extended descriptor */
4de9d0b5 1271 edesc = aead_edesc_alloc(areq, 0);
9c4a7965
KP		 1272 if (IS_ERR(edesc))
1273 return PTR_ERR(edesc);
1274
1275 /* set encrypt */
70bcaca7 1276 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
9c4a7965
KP		 1277
1278 memcpy(req->giv, ctx->iv, crypto_aead_ivsize(authenc));
ba95487d
KP		 1279 /* avoid consecutive packets going out with same IV */
1280 *(__be64 *)req->giv ^= cpu_to_be64(req->seq);
9c4a7965
KP		 1281
1282 return ipsec_esp(edesc, areq, req->giv, req->seq,
1283 ipsec_esp_encrypt_done);
1284}
1285
4de9d0b5
LN		 1286static int ablkcipher_setkey(struct crypto_ablkcipher *cipher,
1287 const u8 *key, unsigned int keylen)
1288{
1289 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1290 struct ablkcipher_alg *alg = crypto_ablkcipher_alg(cipher);
1291
1292 if (keylen > TALITOS_MAX_KEY_SIZE)
1293 goto badkey;
1294
1295 if (keylen < alg->min_keysize || keylen > alg->max_keysize)
1296 goto badkey;
1297
1298 memcpy(&ctx->key, key, keylen);
1299 ctx->keylen = keylen;
1300
1301 return 0;
1302
1303badkey:
1304 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
1305 return -EINVAL;
1306}
1307
1308static void common_nonsnoop_unmap(struct device *dev,
1309 struct talitos_edesc *edesc,
1310 struct ablkcipher_request *areq)
1311{
1312 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1313 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
1314 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
1315
1316 talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
1317
1318 if (edesc->dma_len)
1319 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1320 DMA_BIDIRECTIONAL);
1321}
1322
1323static void ablkcipher_done(struct device *dev,
1324 struct talitos_desc *desc, void *context,
1325 int err)
1326{
1327 struct ablkcipher_request *areq = context;
19bbbc63
KP		 1328 struct talitos_edesc *edesc;
1329
1330 edesc = container_of(desc, struct talitos_edesc, desc);
4de9d0b5
LN		 1331
1332 common_nonsnoop_unmap(dev, edesc, areq);
1333
1334 kfree(edesc);
1335
1336 areq->base.complete(&areq->base, err);
1337}
1338
1339static int common_nonsnoop(struct talitos_edesc *edesc,
1340 struct ablkcipher_request *areq,
1341 u8 *giv,
1342 void (*callback) (struct device *dev,
1343 struct talitos_desc *desc,
1344 void *context, int error))
1345{
1346 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1347 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1348 struct device *dev = ctx->dev;
1349 struct talitos_desc *desc = &edesc->desc;
1350 unsigned int cryptlen = areq->nbytes;
1351 unsigned int ivsize;
1352 int sg_count, ret;
1353
1354 /* first DWORD empty */
1355 desc->ptr[0].len = 0;
81eb024c 1356 to_talitos_ptr(&desc->ptr[0], 0);
4de9d0b5
LN		 1357 desc->ptr[0].j_extent = 0;
1358
1359 /* cipher iv */
1360 ivsize = crypto_ablkcipher_ivsize(cipher);
1361 map_single_talitos_ptr(dev, &desc->ptr[1], ivsize, giv ?: areq->info, 0,
1362 DMA_TO_DEVICE);
1363
1364 /* cipher key */
1365 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1366 (char *)&ctx->key, 0, DMA_TO_DEVICE);
1367
1368 /*
1369 * cipher in
1370 */
1371 desc->ptr[3].len = cpu_to_be16(cryptlen);
1372 desc->ptr[3].j_extent = 0;
1373
1374 sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1375 (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1376 : DMA_TO_DEVICE,
1377 edesc->src_is_chained);
1378
1379 if (sg_count == 1) {
81eb024c 1380 to_talitos_ptr(&desc->ptr[3], sg_dma_address(areq->src));
4de9d0b5
LN		 1381 } else {
1382 sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
1383 &edesc->link_tbl[0]);
1384 if (sg_count > 1) {
81eb024c 1385 to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
4de9d0b5 1386 desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
e938e465
KP		 1387 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1388 edesc->dma_len,
1389 DMA_BIDIRECTIONAL);
4de9d0b5
LN		 1390 } else {
1391 /* Only one segment now, so no link tbl needed */
81eb024c
KP		 1392 to_talitos_ptr(&desc->ptr[3],
1393 sg_dma_address(areq->src));
4de9d0b5
LN		 1394 }
1395 }
1396
1397 /* cipher out */
1398 desc->ptr[4].len = cpu_to_be16(cryptlen);
1399 desc->ptr[4].j_extent = 0;
1400
1401 if (areq->src != areq->dst)
1402 sg_count = talitos_map_sg(dev, areq->dst,
1403 edesc->dst_nents ? : 1,
1404 DMA_FROM_DEVICE,
1405 edesc->dst_is_chained);
1406
1407 if (sg_count == 1) {
81eb024c 1408 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->dst));
4de9d0b5
LN		 1409 } else {
1410 struct talitos_ptr *link_tbl_ptr =
1411 &edesc->link_tbl[edesc->src_nents + 1];
1412
81eb024c
KP		 1413 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl +
1414 (edesc->src_nents + 1) *
1415 sizeof(struct talitos_ptr));
4de9d0b5 1416 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
4de9d0b5
LN		 1417 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1418 link_tbl_ptr);
1419 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1420 edesc->dma_len, DMA_BIDIRECTIONAL);
1421 }
1422
1423 /* iv out */
1424 map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv, 0,
1425 DMA_FROM_DEVICE);
1426
1427 /* last DWORD empty */
1428 desc->ptr[6].len = 0;
81eb024c 1429 to_talitos_ptr(&desc->ptr[6], 0);
4de9d0b5
LN		 1430 desc->ptr[6].j_extent = 0;
1431
1432 ret = talitos_submit(dev, desc, callback, areq);
1433 if (ret != -EINPROGRESS) {
1434 common_nonsnoop_unmap(dev, edesc, areq);
1435 kfree(edesc);
1436 }
1437 return ret;
1438}
1439
e938e465
KP		 1440static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request *
1441 areq)
4de9d0b5
LN		 1442{
1443 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1444 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1445
1446 return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst, areq->nbytes,
1447 0, 0, areq->base.flags);
1448}
1449
1450static int ablkcipher_encrypt(struct ablkcipher_request *areq)
1451{
1452 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1453 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1454 struct talitos_edesc *edesc;
1455
1456 /* allocate extended descriptor */
1457 edesc = ablkcipher_edesc_alloc(areq);
1458 if (IS_ERR(edesc))
1459 return PTR_ERR(edesc);
1460
1461 /* set encrypt */
1462 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1463
1464 return common_nonsnoop(edesc, areq, NULL, ablkcipher_done);
1465}
1466
1467static int ablkcipher_decrypt(struct ablkcipher_request *areq)
1468{
1469 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1470 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1471 struct talitos_edesc *edesc;
1472
1473 /* allocate extended descriptor */
1474 edesc = ablkcipher_edesc_alloc(areq);
1475 if (IS_ERR(edesc))
1476 return PTR_ERR(edesc);
1477
1478 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1479
1480 return common_nonsnoop(edesc, areq, NULL, ablkcipher_done);
1481}
1482
9c4a7965 1483struct talitos_alg_template {
d5e4aaef
LN		 1484 u32 type;
1485 union {
1486 struct crypto_alg crypto;
acbf7c62 1487 struct ahash_alg hash;
d5e4aaef 1488 } alg;
9c4a7965
KP		 1489 __be32 desc_hdr_template;
1490};
1491
1492static struct talitos_alg_template driver_algs[] = {
56af8cd4 1493 /* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
d5e4aaef
LN		 1494 { .type = CRYPTO_ALG_TYPE_AEAD,
1495 .alg.crypto = {
56af8cd4
LN		 1496 .cra_name = "authenc(hmac(sha1),cbc(aes))",
1497 .cra_driver_name = "authenc-hmac-sha1-cbc-aes-talitos",
1498 .cra_blocksize = AES_BLOCK_SIZE,
1499 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1500 .cra_type = &crypto_aead_type,
1501 .cra_aead = {
1502 .setkey = aead_setkey,
1503 .setauthsize = aead_setauthsize,
1504 .encrypt = aead_encrypt,
1505 .decrypt = aead_decrypt,
1506 .givencrypt = aead_givencrypt,
1507 .geniv = "<built-in>",
1508 .ivsize = AES_BLOCK_SIZE,
1509 .maxauthsize = SHA1_DIGEST_SIZE,
1510 }
1511 },
9c4a7965
KP		 1512 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1513 DESC_HDR_SEL0_AESU |
1514 DESC_HDR_MODE0_AESU_CBC |
1515 DESC_HDR_SEL1_MDEUA |
1516 DESC_HDR_MODE1_MDEU_INIT |
1517 DESC_HDR_MODE1_MDEU_PAD |
1518 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
70bcaca7 1519 },
d5e4aaef
LN		 1520 { .type = CRYPTO_ALG_TYPE_AEAD,
1521 .alg.crypto = {
56af8cd4
LN		 1522 .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
1523 .cra_driver_name = "authenc-hmac-sha1-cbc-3des-talitos",
1524 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1525 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1526 .cra_type = &crypto_aead_type,
1527 .cra_aead = {
1528 .setkey = aead_setkey,
1529 .setauthsize = aead_setauthsize,
1530 .encrypt = aead_encrypt,
1531 .decrypt = aead_decrypt,
1532 .givencrypt = aead_givencrypt,
1533 .geniv = "<built-in>",
1534 .ivsize = DES3_EDE_BLOCK_SIZE,
1535 .maxauthsize = SHA1_DIGEST_SIZE,
1536 }
1537 },
70bcaca7
LN		 1538 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1539 DESC_HDR_SEL0_DEU |
1540 DESC_HDR_MODE0_DEU_CBC |
1541 DESC_HDR_MODE0_DEU_3DES |
1542 DESC_HDR_SEL1_MDEUA |
1543 DESC_HDR_MODE1_MDEU_INIT |
1544 DESC_HDR_MODE1_MDEU_PAD |
1545 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
3952f17e 1546 },
d5e4aaef
LN		 1547 { .type = CRYPTO_ALG_TYPE_AEAD,
1548 .alg.crypto = {
56af8cd4
LN		 1549 .cra_name = "authenc(hmac(sha256),cbc(aes))",
1550 .cra_driver_name = "authenc-hmac-sha256-cbc-aes-talitos",
1551 .cra_blocksize = AES_BLOCK_SIZE,
1552 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1553 .cra_type = &crypto_aead_type,
1554 .cra_aead = {
1555 .setkey = aead_setkey,
1556 .setauthsize = aead_setauthsize,
1557 .encrypt = aead_encrypt,
1558 .decrypt = aead_decrypt,
1559 .givencrypt = aead_givencrypt,
1560 .geniv = "<built-in>",
1561 .ivsize = AES_BLOCK_SIZE,
1562 .maxauthsize = SHA256_DIGEST_SIZE,
1563 }
1564 },
3952f17e
LN		 1565 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1566 DESC_HDR_SEL0_AESU |
1567 DESC_HDR_MODE0_AESU_CBC |
1568 DESC_HDR_SEL1_MDEUA |
1569 DESC_HDR_MODE1_MDEU_INIT |
1570 DESC_HDR_MODE1_MDEU_PAD |
1571 DESC_HDR_MODE1_MDEU_SHA256_HMAC,
1572 },
d5e4aaef
LN		 1573 { .type = CRYPTO_ALG_TYPE_AEAD,
1574 .alg.crypto = {
56af8cd4
LN		 1575 .cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
1576 .cra_driver_name = "authenc-hmac-sha256-cbc-3des-talitos",
1577 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1578 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1579 .cra_type = &crypto_aead_type,
1580 .cra_aead = {
1581 .setkey = aead_setkey,
1582 .setauthsize = aead_setauthsize,
1583 .encrypt = aead_encrypt,
1584 .decrypt = aead_decrypt,
1585 .givencrypt = aead_givencrypt,
1586 .geniv = "<built-in>",
1587 .ivsize = DES3_EDE_BLOCK_SIZE,
1588 .maxauthsize = SHA256_DIGEST_SIZE,
1589 }
1590 },
3952f17e
LN		 1591 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1592 DESC_HDR_SEL0_DEU |
1593 DESC_HDR_MODE0_DEU_CBC |
1594 DESC_HDR_MODE0_DEU_3DES |
1595 DESC_HDR_SEL1_MDEUA |
1596 DESC_HDR_MODE1_MDEU_INIT |
1597 DESC_HDR_MODE1_MDEU_PAD |
1598 DESC_HDR_MODE1_MDEU_SHA256_HMAC,
1599 },
d5e4aaef
LN		 1600 { .type = CRYPTO_ALG_TYPE_AEAD,
1601 .alg.crypto = {
56af8cd4
LN		 1602 .cra_name = "authenc(hmac(md5),cbc(aes))",
1603 .cra_driver_name = "authenc-hmac-md5-cbc-aes-talitos",
1604 .cra_blocksize = AES_BLOCK_SIZE,
1605 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1606 .cra_type = &crypto_aead_type,
1607 .cra_aead = {
1608 .setkey = aead_setkey,
1609 .setauthsize = aead_setauthsize,
1610 .encrypt = aead_encrypt,
1611 .decrypt = aead_decrypt,
1612 .givencrypt = aead_givencrypt,
1613 .geniv = "<built-in>",
1614 .ivsize = AES_BLOCK_SIZE,
1615 .maxauthsize = MD5_DIGEST_SIZE,
1616 }
1617 },
3952f17e
LN		 1618 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1619 DESC_HDR_SEL0_AESU |
1620 DESC_HDR_MODE0_AESU_CBC |
1621 DESC_HDR_SEL1_MDEUA |
1622 DESC_HDR_MODE1_MDEU_INIT |
1623 DESC_HDR_MODE1_MDEU_PAD |
1624 DESC_HDR_MODE1_MDEU_MD5_HMAC,
1625 },
d5e4aaef
LN		 1626 { .type = CRYPTO_ALG_TYPE_AEAD,
1627 .alg.crypto = {
56af8cd4
LN		 1628 .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
1629 .cra_driver_name = "authenc-hmac-md5-cbc-3des-talitos",
1630 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1631 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1632 .cra_type = &crypto_aead_type,
1633 .cra_aead = {
1634 .setkey = aead_setkey,
1635 .setauthsize = aead_setauthsize,
1636 .encrypt = aead_encrypt,
1637 .decrypt = aead_decrypt,
1638 .givencrypt = aead_givencrypt,
1639 .geniv = "<built-in>",
1640 .ivsize = DES3_EDE_BLOCK_SIZE,
1641 .maxauthsize = MD5_DIGEST_SIZE,
1642 }
1643 },
3952f17e
LN		 1644 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1645 DESC_HDR_SEL0_DEU |
1646 DESC_HDR_MODE0_DEU_CBC |
1647 DESC_HDR_MODE0_DEU_3DES |
1648 DESC_HDR_SEL1_MDEUA |
1649 DESC_HDR_MODE1_MDEU_INIT |
1650 DESC_HDR_MODE1_MDEU_PAD |
1651 DESC_HDR_MODE1_MDEU_MD5_HMAC,
4de9d0b5
LN		 1652 },
1653 /* ABLKCIPHER algorithms. */
d5e4aaef
LN		 1654 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
1655 .alg.crypto = {
4de9d0b5
LN		 1656 .cra_name = "cbc(aes)",
1657 .cra_driver_name = "cbc-aes-talitos",
1658 .cra_blocksize = AES_BLOCK_SIZE,
1659 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1660 CRYPTO_ALG_ASYNC,
1661 .cra_type = &crypto_ablkcipher_type,
1662 .cra_ablkcipher = {
1663 .setkey = ablkcipher_setkey,
1664 .encrypt = ablkcipher_encrypt,
1665 .decrypt = ablkcipher_decrypt,
1666 .geniv = "eseqiv",
1667 .min_keysize = AES_MIN_KEY_SIZE,
1668 .max_keysize = AES_MAX_KEY_SIZE,
1669 .ivsize = AES_BLOCK_SIZE,
1670 }
1671 },
1672 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
1673 DESC_HDR_SEL0_AESU |
1674 DESC_HDR_MODE0_AESU_CBC,
1675 },
d5e4aaef
LN		 1676 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
1677 .alg.crypto = {
4de9d0b5
LN		 1678 .cra_name = "cbc(des3_ede)",
1679 .cra_driver_name = "cbc-3des-talitos",
1680 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1681 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1682 CRYPTO_ALG_ASYNC,
1683 .cra_type = &crypto_ablkcipher_type,
1684 .cra_ablkcipher = {
1685 .setkey = ablkcipher_setkey,
1686 .encrypt = ablkcipher_encrypt,
1687 .decrypt = ablkcipher_decrypt,
1688 .geniv = "eseqiv",
1689 .min_keysize = DES3_EDE_KEY_SIZE,
1690 .max_keysize = DES3_EDE_KEY_SIZE,
1691 .ivsize = DES3_EDE_BLOCK_SIZE,
1692 }
1693 },
1694 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
1695 DESC_HDR_SEL0_DEU |
1696 DESC_HDR_MODE0_DEU_CBC |
1697 DESC_HDR_MODE0_DEU_3DES,
9c4a7965
KP		 1698 }
1699};
1700
1701struct talitos_crypto_alg {
1702 struct list_head entry;
1703 struct device *dev;
acbf7c62 1704 struct talitos_alg_template algt;
9c4a7965
KP		 1705};
1706
1707static int talitos_cra_init(struct crypto_tfm *tfm)
1708{
1709 struct crypto_alg *alg = tfm->__crt_alg;
19bbbc63 1710 struct talitos_crypto_alg *talitos_alg;
9c4a7965
KP		 1711 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
1712
acbf7c62
LN		 1713 talitos_alg = container_of(alg, struct talitos_crypto_alg,
1714 algt.alg.crypto);
19bbbc63 1715
9c4a7965
KP		 1716 /* update context with ptr to dev */
1717 ctx->dev = talitos_alg->dev;
19bbbc63 1718
9c4a7965 1719 /* copy descriptor header template value */
acbf7c62 1720 ctx->desc_hdr_template = talitos_alg->algt.desc_hdr_template;
9c4a7965
KP		 1721
1722 /* random first IV */
70bcaca7 1723 get_random_bytes(ctx->iv, TALITOS_MAX_IV_LENGTH);
9c4a7965
KP		 1724
1725 return 0;
1726}
1727
1728/*
1729 * given the alg's descriptor header template, determine whether descriptor
1730 * type and primary/secondary execution units required match the hw
1731 * capabilities description provided in the device tree node.
1732 */
1733static int hw_supports(struct device *dev, __be32 desc_hdr_template)
1734{
1735 struct talitos_private *priv = dev_get_drvdata(dev);
1736 int ret;
1737
1738 ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
1739 (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
1740
1741 if (SECONDARY_EU(desc_hdr_template))
1742 ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
1743 & priv->exec_units);
1744
1745 return ret;
1746}
1747
596f1034 1748static int talitos_remove(struct of_device *ofdev)
9c4a7965
KP		 1749{
1750 struct device *dev = &ofdev->dev;
1751 struct talitos_private *priv = dev_get_drvdata(dev);
1752 struct talitos_crypto_alg *t_alg, *n;
1753 int i;
1754
1755 list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
acbf7c62
LN		 1756 switch (t_alg->algt.type) {
1757 case CRYPTO_ALG_TYPE_ABLKCIPHER:
1758 case CRYPTO_ALG_TYPE_AEAD:
1759 crypto_unregister_alg(&t_alg->algt.alg.crypto);
1760 break;
1761 case CRYPTO_ALG_TYPE_AHASH:
1762 crypto_unregister_ahash(&t_alg->algt.alg.hash);
1763 break;
1764 }
9c4a7965
KP		 1765 list_del(&t_alg->entry);
1766 kfree(t_alg);
1767 }
1768
1769 if (hw_supports(dev, DESC_HDR_SEL0_RNG))
1770 talitos_unregister_rng(dev);
1771
4b992628
KP		 1772 for (i = 0; i < priv->num_channels; i++)
1773 if (priv->chan[i].fifo)
1774 kfree(priv->chan[i].fifo);
9c4a7965 1775
4b992628 1776 kfree(priv->chan);
9c4a7965
KP		 1777
1778 if (priv->irq != NO_IRQ) {
1779 free_irq(priv->irq, dev);
1780 irq_dispose_mapping(priv->irq);
1781 }
1782
1783 tasklet_kill(&priv->done_task);
9c4a7965
KP		 1784
1785 iounmap(priv->reg);
1786
1787 dev_set_drvdata(dev, NULL);
1788
1789 kfree(priv);
1790
1791 return 0;
1792}
1793
1794static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
1795 struct talitos_alg_template
1796 *template)
1797{
1798 struct talitos_crypto_alg *t_alg;
1799 struct crypto_alg *alg;
1800
1801 t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL);
1802 if (!t_alg)
1803 return ERR_PTR(-ENOMEM);
1804
acbf7c62
LN		 1805 t_alg->algt = *template;
1806
1807 switch (t_alg->algt.type) {
1808 case CRYPTO_ALG_TYPE_ABLKCIPHER:
1809 case CRYPTO_ALG_TYPE_AEAD:
1810 alg = &t_alg->algt.alg.crypto;
1811 break;
1812 case CRYPTO_ALG_TYPE_AHASH:
1813 alg = &t_alg->algt.alg.hash.halg.base;
1814 }
9c4a7965 1815
9c4a7965
KP		 1816 alg->cra_module = THIS_MODULE;
1817 alg->cra_init = talitos_cra_init;
1818 alg->cra_priority = TALITOS_CRA_PRIORITY;
9c4a7965 1819 alg->cra_alignmask = 0;
9c4a7965 1820 alg->cra_ctxsize = sizeof(struct talitos_ctx);
9c4a7965 1821
9c4a7965
KP		 1822 t_alg->dev = dev;
1823
1824 return t_alg;
1825}
1826
1827static int talitos_probe(struct of_device *ofdev,
1828 const struct of_device_id *match)
1829{
1830 struct device *dev = &ofdev->dev;
1831 struct device_node *np = ofdev->node;
1832 struct talitos_private *priv;
1833 const unsigned int *prop;
1834 int i, err;
1835
1836 priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL);
1837 if (!priv)
1838 return -ENOMEM;
1839
1840 dev_set_drvdata(dev, priv);
1841
1842 priv->ofdev = ofdev;
1843
1844 tasklet_init(&priv->done_task, talitos_done, (unsigned long)dev);
9c4a7965 1845
fe5720e2
KP		 1846 INIT_LIST_HEAD(&priv->alg_list);
1847
9c4a7965
KP		 1848 priv->irq = irq_of_parse_and_map(np, 0);
1849
1850 if (priv->irq == NO_IRQ) {
1851 dev_err(dev, "failed to map irq\n");
1852 err = -EINVAL;
1853 goto err_out;
1854 }
1855
1856 /* get the irq line */
1857 err = request_irq(priv->irq, talitos_interrupt, 0,
1858 dev_driver_string(dev), dev);
1859 if (err) {
1860 dev_err(dev, "failed to request irq %d\n", priv->irq);
1861 irq_dispose_mapping(priv->irq);
1862 priv->irq = NO_IRQ;
1863 goto err_out;
1864 }
1865
1866 priv->reg = of_iomap(np, 0);
1867 if (!priv->reg) {
1868 dev_err(dev, "failed to of_iomap\n");
1869 err = -ENOMEM;
1870 goto err_out;
1871 }
1872
1873 /* get SEC version capabilities from device tree */
1874 prop = of_get_property(np, "fsl,num-channels", NULL);
1875 if (prop)
1876 priv->num_channels = *prop;
1877
1878 prop = of_get_property(np, "fsl,channel-fifo-len", NULL);
1879 if (prop)
1880 priv->chfifo_len = *prop;
1881
1882 prop = of_get_property(np, "fsl,exec-units-mask", NULL);
1883 if (prop)
1884 priv->exec_units = *prop;
1885
1886 prop = of_get_property(np, "fsl,descriptor-types-mask", NULL);
1887 if (prop)
1888 priv->desc_types = *prop;
1889
1890 if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
1891 !priv->exec_units || !priv->desc_types) {
1892 dev_err(dev, "invalid property data in device tree node\n");
1893 err = -EINVAL;
1894 goto err_out;
1895 }
1896
f3c85bc1
LN		 1897 if (of_device_is_compatible(np, "fsl,sec3.0"))
1898 priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
1899
fe5720e2
KP		 1900 if (of_device_is_compatible(np, "fsl,sec2.1"))
1901 priv->features |= TALITOS_FTR_HW_AUTH_CHECK;
1902
4b992628
KP		 1903 priv->chan = kzalloc(sizeof(struct talitos_channel) *
1904 priv->num_channels, GFP_KERNEL);
1905 if (!priv->chan) {
1906 dev_err(dev, "failed to allocate channel management space\n");
9c4a7965
KP		 1907 err = -ENOMEM;
1908 goto err_out;
1909 }
1910
1911 for (i = 0; i < priv->num_channels; i++) {
4b992628
KP		 1912 spin_lock_init(&priv->chan[i].head_lock);
1913 spin_lock_init(&priv->chan[i].tail_lock);
9c4a7965
KP		 1914 }
1915
1916 priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
1917
1918 for (i = 0; i < priv->num_channels; i++) {
4b992628
KP		 1919 priv->chan[i].fifo = kzalloc(sizeof(struct talitos_request) *
1920 priv->fifo_len, GFP_KERNEL);
1921 if (!priv->chan[i].fifo) {
9c4a7965
KP		 1922 dev_err(dev, "failed to allocate request fifo %d\n", i);
1923 err = -ENOMEM;
1924 goto err_out;
1925 }
1926 }
1927
ec6644d6 1928 for (i = 0; i < priv->num_channels; i++)
4b992628
KP		 1929 atomic_set(&priv->chan[i].submit_count,
1930 -(priv->chfifo_len - 1));
9c4a7965 1931
81eb024c
KP		 1932 dma_set_mask(dev, DMA_BIT_MASK(36));
1933
9c4a7965
KP		 1934 /* reset and initialize the h/w */
1935 err = init_device(dev);
1936 if (err) {
1937 dev_err(dev, "failed to initialize device\n");
1938 goto err_out;
1939 }
1940
1941 /* register the RNG, if available */
1942 if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
1943 err = talitos_register_rng(dev);
1944 if (err) {
1945 dev_err(dev, "failed to register hwrng: %d\n", err);
1946 goto err_out;
1947 } else
1948 dev_info(dev, "hwrng\n");
1949 }
1950
1951 /* register crypto algorithms the device supports */
9c4a7965
KP		 1952 for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
1953 if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
1954 struct talitos_crypto_alg *t_alg;
acbf7c62 1955 char *name = NULL;
9c4a7965
KP		 1956
1957 t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
1958 if (IS_ERR(t_alg)) {
1959 err = PTR_ERR(t_alg);
1960 goto err_out;
1961 }
1962
acbf7c62
LN		 1963 switch (t_alg->algt.type) {
1964 case CRYPTO_ALG_TYPE_ABLKCIPHER:
1965 case CRYPTO_ALG_TYPE_AEAD:
1966 err = crypto_register_alg(
1967 &t_alg->algt.alg.crypto);
1968 name = t_alg->algt.alg.crypto.cra_driver_name;
1969 break;
1970 case CRYPTO_ALG_TYPE_AHASH:
1971 err = crypto_register_ahash(
1972 &t_alg->algt.alg.hash);
1973 name =
1974 t_alg->algt.alg.hash.halg.base.cra_driver_name;
1975 break;
1976 }
9c4a7965
KP		 1977 if (err) {
1978 dev_err(dev, "%s alg registration failed\n",
acbf7c62 1979 name);
9c4a7965
KP		 1980 kfree(t_alg);
1981 } else {
1982 list_add_tail(&t_alg->entry, &priv->alg_list);
acbf7c62 1983 dev_info(dev, "%s\n", name);
9c4a7965
KP		 1984 }
1985 }
1986 }
1987
1988 return 0;
1989
1990err_out:
1991 talitos_remove(ofdev);
9c4a7965
KP		 1992
1993 return err;
1994}
1995
6c3f975a 1996static const struct of_device_id talitos_match[] = {
9c4a7965
KP		 1997 {
1998 .compatible = "fsl,sec2.0",
1999 },
2000 {},
2001};
2002MODULE_DEVICE_TABLE(of, talitos_match);
2003
2004static struct of_platform_driver talitos_driver = {
2005 .name = "talitos",
2006 .match_table = talitos_match,
2007 .probe = talitos_probe,
596f1034 2008 .remove = talitos_remove,
9c4a7965
KP		 2009};
2010
2011static int __init talitos_init(void)
2012{
2013 return of_register_platform_driver(&talitos_driver);
2014}
2015module_init(talitos_init);
2016
2017static void __exit talitos_exit(void)
2018{
2019 of_unregister_platform_driver(&talitos_driver);
2020}
2021module_exit(talitos_exit);
2022
2023MODULE_LICENSE("GPL");
2024MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
2025MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");
Linux kernel - Deliverables
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