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crypto: talitos - move talitos structures to header file
[deliverable/linux.git] / drivers / crypto / talitos.c
CommitLineData
9c4a7965
KP		 1/*
2 * talitos - Freescale Integrated Security Engine (SEC) device driver
3 *
5228f0f7 4 * Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
9c4a7965
KP		 5 *
6 * Scatterlist Crypto API glue code copied from files with the following:
7 * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
8 *
9 * Crypto algorithm registration code copied from hifn driver:
10 * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
11 * All rights reserved.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 */
27
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/mod_devicetable.h>
31#include <linux/device.h>
32#include <linux/interrupt.h>
33#include <linux/crypto.h>
34#include <linux/hw_random.h>
35#include <linux/of_platform.h>
36#include <linux/dma-mapping.h>
37#include <linux/io.h>
38#include <linux/spinlock.h>
39#include <linux/rtnetlink.h>
5a0e3ad6 40#include <linux/slab.h>
9c4a7965
KP		 41
42#include <crypto/algapi.h>
43#include <crypto/aes.h>
3952f17e 44#include <crypto/des.h>
9c4a7965 45#include <crypto/sha.h>
497f2e6b 46#include <crypto/md5.h>
9c4a7965
KP		 47#include <crypto/aead.h>
48#include <crypto/authenc.h>
4de9d0b5 49#include <crypto/skcipher.h>
acbf7c62
LN		 50#include <crypto/hash.h>
51#include <crypto/internal/hash.h>
4de9d0b5 52#include <crypto/scatterwalk.h>
9c4a7965
KP		 53
54#include "talitos.h"
55
81eb024c
KP		 56static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t dma_addr)
57{
58 talitos_ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
a752447a 59 talitos_ptr->eptr = upper_32_bits(dma_addr);
81eb024c
KP		 60}
61
9c4a7965
KP		 62/*
63 * map virtual single (contiguous) pointer to h/w descriptor pointer
64 */
65static void map_single_talitos_ptr(struct device *dev,
66 struct talitos_ptr *talitos_ptr,
67 unsigned short len, void *data,
68 unsigned char extent,
69 enum dma_data_direction dir)
70{
81eb024c
KP		 71 dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
72
9c4a7965 73 talitos_ptr->len = cpu_to_be16(len);
81eb024c 74 to_talitos_ptr(talitos_ptr, dma_addr);
9c4a7965
KP		 75 talitos_ptr->j_extent = extent;
76}
77
78/*
79 * unmap bus single (contiguous) h/w descriptor pointer
80 */
81static void unmap_single_talitos_ptr(struct device *dev,
82 struct talitos_ptr *talitos_ptr,
83 enum dma_data_direction dir)
84{
85 dma_unmap_single(dev, be32_to_cpu(talitos_ptr->ptr),
86 be16_to_cpu(talitos_ptr->len), dir);
87}
88
89static int reset_channel(struct device *dev, int ch)
90{
91 struct talitos_private *priv = dev_get_drvdata(dev);
92 unsigned int timeout = TALITOS_TIMEOUT;
93
ad42d5fc 94 setbits32(priv->chan[ch].reg + TALITOS_CCCR, TALITOS_CCCR_RESET);
9c4a7965 95
ad42d5fc 96 while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) & TALITOS_CCCR_RESET)
9c4a7965
KP		 97 && --timeout)
98 cpu_relax();
99
100 if (timeout == 0) {
101 dev_err(dev, "failed to reset channel %d\n", ch);
102 return -EIO;
103 }
104
81eb024c 105 /* set 36-bit addressing, done writeback enable and done IRQ enable */
ad42d5fc 106 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE |
81eb024c 107 TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
9c4a7965 108
fe5720e2
KP		 109 /* and ICCR writeback, if available */
110 if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
ad42d5fc 111 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
fe5720e2
KP		 112 TALITOS_CCCR_LO_IWSE);
113
9c4a7965
KP		 114 return 0;
115}
116
117static int reset_device(struct device *dev)
118{
119 struct talitos_private *priv = dev_get_drvdata(dev);
120 unsigned int timeout = TALITOS_TIMEOUT;
c3e337f8 121 u32 mcr = TALITOS_MCR_SWR;
9c4a7965 122
c3e337f8 123 setbits32(priv->reg + TALITOS_MCR, mcr);
9c4a7965
KP		 124
125 while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS_MCR_SWR)
126 && --timeout)
127 cpu_relax();
128
2cdba3cf 129 if (priv->irq[1]) {
c3e337f8
KP		 130 mcr = TALITOS_MCR_RCA1 | TALITOS_MCR_RCA3;
131 setbits32(priv->reg + TALITOS_MCR, mcr);
132 }
133
9c4a7965
KP		 134 if (timeout == 0) {
135 dev_err(dev, "failed to reset device\n");
136 return -EIO;
137 }
138
139 return 0;
140}
141
142/*
143 * Reset and initialize the device
144 */
145static int init_device(struct device *dev)
146{
147 struct talitos_private *priv = dev_get_drvdata(dev);
148 int ch, err;
149
150 /*
151 * Master reset
152 * errata documentation: warning: certain SEC interrupts
153 * are not fully cleared by writing the MCR:SWR bit,
154 * set bit twice to completely reset
155 */
156 err = reset_device(dev);
157 if (err)
158 return err;
159
160 err = reset_device(dev);
161 if (err)
162 return err;
163
164 /* reset channels */
165 for (ch = 0; ch < priv->num_channels; ch++) {
166 err = reset_channel(dev, ch);
167 if (err)
168 return err;
169 }
170
171 /* enable channel done and error interrupts */
172 setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
173 setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
174
fe5720e2
KP		 175 /* disable integrity check error interrupts (use writeback instead) */
176 if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
177 setbits32(priv->reg + TALITOS_MDEUICR_LO,
178 TALITOS_MDEUICR_LO_ICE);
179
9c4a7965
KP		 180 return 0;
181}
182
183/**
184 * talitos_submit - submits a descriptor to the device for processing
185 * @dev: the SEC device to be used
5228f0f7 186 * @ch: the SEC device channel to be used
9c4a7965
KP		 187 * @desc: the descriptor to be processed by the device
188 * @callback: whom to call when processing is complete
189 * @context: a handle for use by caller (optional)
190 *
191 * desc must contain valid dma-mapped (bus physical) address pointers.
192 * callback must check err and feedback in descriptor header
193 * for device processing status.
194 */
5228f0f7 195static int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
9c4a7965
KP		 196 void (*callback)(struct device *dev,
197 struct talitos_desc *desc,
198 void *context, int error),
199 void *context)
200{
201 struct talitos_private *priv = dev_get_drvdata(dev);
202 struct talitos_request *request;
5228f0f7 203 unsigned long flags;
9c4a7965
KP		 204 int head;
205
4b992628 206 spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
9c4a7965 207
4b992628 208 if (!atomic_inc_not_zero(&priv->chan[ch].submit_count)) {
ec6644d6 209 /* h/w fifo is full */
4b992628 210 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
9c4a7965
KP		 211 return -EAGAIN;
212 }
213
4b992628
KP		 214 head = priv->chan[ch].head;
215 request = &priv->chan[ch].fifo[head];
ec6644d6 216
9c4a7965
KP		 217 /* map descriptor and save caller data */
218 request->dma_desc = dma_map_single(dev, desc, sizeof(*desc),
219 DMA_BIDIRECTIONAL);
220 request->callback = callback;
221 request->context = context;
222
223 /* increment fifo head */
4b992628 224 priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1);
9c4a7965
KP		 225
226 smp_wmb();
227 request->desc = desc;
228
229 /* GO! */
230 wmb();
ad42d5fc
KP		 231 out_be32(priv->chan[ch].reg + TALITOS_FF,
232 upper_32_bits(request->dma_desc));
233 out_be32(priv->chan[ch].reg + TALITOS_FF_LO,
a752447a 234 lower_32_bits(request->dma_desc));
9c4a7965 235
4b992628 236 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
9c4a7965
KP		 237
238 return -EINPROGRESS;
239}
240
241/*
242 * process what was done, notify callback of error if not
243 */
244static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
245{
246 struct talitos_private *priv = dev_get_drvdata(dev);
247 struct talitos_request *request, saved_req;
248 unsigned long flags;
249 int tail, status;
250
4b992628 251 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
9c4a7965 252
4b992628
KP		 253 tail = priv->chan[ch].tail;
254 while (priv->chan[ch].fifo[tail].desc) {
255 request = &priv->chan[ch].fifo[tail];
9c4a7965
KP		 256
257 /* descriptors with their done bits set don't get the error */
258 rmb();
ca38a814 259 if ((request->desc->hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
9c4a7965 260 status = 0;
ca38a814 261 else
9c4a7965
KP		 262 if (!error)
263 break;
264 else
265 status = error;
266
267 dma_unmap_single(dev, request->dma_desc,
e938e465
KP		 268 sizeof(struct talitos_desc),
269 DMA_BIDIRECTIONAL);
9c4a7965
KP		 270
271 /* copy entries so we can call callback outside lock */
272 saved_req.desc = request->desc;
273 saved_req.callback = request->callback;
274 saved_req.context = request->context;
275
276 /* release request entry in fifo */
277 smp_wmb();
278 request->desc = NULL;
279
280 /* increment fifo tail */
4b992628 281 priv->chan[ch].tail = (tail + 1) & (priv->fifo_len - 1);
9c4a7965 282
4b992628 283 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
ec6644d6 284
4b992628 285 atomic_dec(&priv->chan[ch].submit_count);
ec6644d6 286
9c4a7965
KP		 287 saved_req.callback(dev, saved_req.desc, saved_req.context,
288 status);
289 /* channel may resume processing in single desc error case */
290 if (error && !reset_ch && status == error)
291 return;
4b992628
KP		 292 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
293 tail = priv->chan[ch].tail;
9c4a7965
KP		 294 }
295
4b992628 296 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
9c4a7965
KP		 297}
298
299/*
300 * process completed requests for channels that have done status
301 */
c3e337f8
KP		 302#define DEF_TALITOS_DONE(name, ch_done_mask) \
303static void talitos_done_##name(unsigned long data) \
304{ \
305 struct device *dev = (struct device *)data; \
306 struct talitos_private *priv = dev_get_drvdata(dev); \
511d63cb 307 unsigned long flags; \
c3e337f8
KP		 308 \
309 if (ch_done_mask & 1) \
310 flush_channel(dev, 0, 0, 0); \
311 if (priv->num_channels == 1) \
312 goto out; \
313 if (ch_done_mask & (1 << 2)) \
314 flush_channel(dev, 1, 0, 0); \
315 if (ch_done_mask & (1 << 4)) \
316 flush_channel(dev, 2, 0, 0); \
317 if (ch_done_mask & (1 << 6)) \
318 flush_channel(dev, 3, 0, 0); \
319 \
320out: \
321 /* At this point, all completed channels have been processed */ \
322 /* Unmask done interrupts for channels completed later on. */ \
511d63cb 323 spin_lock_irqsave(&priv->reg_lock, flags); \
c3e337f8
KP		 324 setbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
325 setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT); \
511d63cb 326 spin_unlock_irqrestore(&priv->reg_lock, flags); \
9c4a7965 327}
c3e337f8
KP		 328DEF_TALITOS_DONE(4ch, TALITOS_ISR_4CHDONE)
329DEF_TALITOS_DONE(ch0_2, TALITOS_ISR_CH_0_2_DONE)
330DEF_TALITOS_DONE(ch1_3, TALITOS_ISR_CH_1_3_DONE)
9c4a7965
KP		 331
332/*
333 * locate current (offending) descriptor
334 */
3e721aeb 335static u32 current_desc_hdr(struct device *dev, int ch)
9c4a7965
KP		 336{
337 struct talitos_private *priv = dev_get_drvdata(dev);
4b992628 338 int tail = priv->chan[ch].tail;
9c4a7965
KP		 339 dma_addr_t cur_desc;
340
ad42d5fc 341 cur_desc = in_be32(priv->chan[ch].reg + TALITOS_CDPR_LO);
9c4a7965 342
4b992628 343 while (priv->chan[ch].fifo[tail].dma_desc != cur_desc) {
9c4a7965 344 tail = (tail + 1) & (priv->fifo_len - 1);
4b992628 345 if (tail == priv->chan[ch].tail) {
9c4a7965 346 dev_err(dev, "couldn't locate current descriptor\n");
3e721aeb 347 return 0;
9c4a7965
KP		 348 }
349 }
350
3e721aeb 351 return priv->chan[ch].fifo[tail].desc->hdr;
9c4a7965
KP		 352}
353
354/*
355 * user diagnostics; report root cause of error based on execution unit status
356 */
3e721aeb 357static void report_eu_error(struct device *dev, int ch, u32 desc_hdr)
9c4a7965
KP		 358{
359 struct talitos_private *priv = dev_get_drvdata(dev);
360 int i;
361
3e721aeb 362 if (!desc_hdr)
ad42d5fc 363 desc_hdr = in_be32(priv->chan[ch].reg + TALITOS_DESCBUF);
3e721aeb
KP		 364
365 switch (desc_hdr & DESC_HDR_SEL0_MASK) {
9c4a7965
KP		 366 case DESC_HDR_SEL0_AFEU:
367 dev_err(dev, "AFEUISR 0x%08x_%08x\n",
368 in_be32(priv->reg + TALITOS_AFEUISR),
369 in_be32(priv->reg + TALITOS_AFEUISR_LO));
370 break;
371 case DESC_HDR_SEL0_DEU:
372 dev_err(dev, "DEUISR 0x%08x_%08x\n",
373 in_be32(priv->reg + TALITOS_DEUISR),
374 in_be32(priv->reg + TALITOS_DEUISR_LO));
375 break;
376 case DESC_HDR_SEL0_MDEUA:
377 case DESC_HDR_SEL0_MDEUB:
378 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
379 in_be32(priv->reg + TALITOS_MDEUISR),
380 in_be32(priv->reg + TALITOS_MDEUISR_LO));
381 break;
382 case DESC_HDR_SEL0_RNG:
383 dev_err(dev, "RNGUISR 0x%08x_%08x\n",
384 in_be32(priv->reg + TALITOS_RNGUISR),
385 in_be32(priv->reg + TALITOS_RNGUISR_LO));
386 break;
387 case DESC_HDR_SEL0_PKEU:
388 dev_err(dev, "PKEUISR 0x%08x_%08x\n",
389 in_be32(priv->reg + TALITOS_PKEUISR),
390 in_be32(priv->reg + TALITOS_PKEUISR_LO));
391 break;
392 case DESC_HDR_SEL0_AESU:
393 dev_err(dev, "AESUISR 0x%08x_%08x\n",
394 in_be32(priv->reg + TALITOS_AESUISR),
395 in_be32(priv->reg + TALITOS_AESUISR_LO));
396 break;
397 case DESC_HDR_SEL0_CRCU:
398 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
399 in_be32(priv->reg + TALITOS_CRCUISR),
400 in_be32(priv->reg + TALITOS_CRCUISR_LO));
401 break;
402 case DESC_HDR_SEL0_KEU:
403 dev_err(dev, "KEUISR 0x%08x_%08x\n",
404 in_be32(priv->reg + TALITOS_KEUISR),
405 in_be32(priv->reg + TALITOS_KEUISR_LO));
406 break;
407 }
408
3e721aeb 409 switch (desc_hdr & DESC_HDR_SEL1_MASK) {
9c4a7965
KP		 410 case DESC_HDR_SEL1_MDEUA:
411 case DESC_HDR_SEL1_MDEUB:
412 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
413 in_be32(priv->reg + TALITOS_MDEUISR),
414 in_be32(priv->reg + TALITOS_MDEUISR_LO));
415 break;
416 case DESC_HDR_SEL1_CRCU:
417 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
418 in_be32(priv->reg + TALITOS_CRCUISR),
419 in_be32(priv->reg + TALITOS_CRCUISR_LO));
420 break;
421 }
422
423 for (i = 0; i < 8; i++)
424 dev_err(dev, "DESCBUF 0x%08x_%08x\n",
ad42d5fc
KP		 425 in_be32(priv->chan[ch].reg + TALITOS_DESCBUF + 8*i),
426 in_be32(priv->chan[ch].reg + TALITOS_DESCBUF_LO + 8*i));
9c4a7965
KP		 427}
428
429/*
430 * recover from error interrupts
431 */
5e718a09 432static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
9c4a7965 433{
9c4a7965
KP		 434 struct talitos_private *priv = dev_get_drvdata(dev);
435 unsigned int timeout = TALITOS_TIMEOUT;
436 int ch, error, reset_dev = 0, reset_ch = 0;
40405f10 437 u32 v, v_lo;
9c4a7965
KP		 438
439 for (ch = 0; ch < priv->num_channels; ch++) {
440 /* skip channels without errors */
441 if (!(isr & (1 << (ch * 2 + 1))))
442 continue;
443
444 error = -EINVAL;
445
ad42d5fc
KP		 446 v = in_be32(priv->chan[ch].reg + TALITOS_CCPSR);
447 v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO);
9c4a7965
KP		 448
449 if (v_lo & TALITOS_CCPSR_LO_DOF) {
450 dev_err(dev, "double fetch fifo overflow error\n");
451 error = -EAGAIN;
452 reset_ch = 1;
453 }
454 if (v_lo & TALITOS_CCPSR_LO_SOF) {
455 /* h/w dropped descriptor */
456 dev_err(dev, "single fetch fifo overflow error\n");
457 error = -EAGAIN;
458 }
459 if (v_lo & TALITOS_CCPSR_LO_MDTE)
460 dev_err(dev, "master data transfer error\n");
461 if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
462 dev_err(dev, "s/g data length zero error\n");
463 if (v_lo & TALITOS_CCPSR_LO_FPZ)
464 dev_err(dev, "fetch pointer zero error\n");
465 if (v_lo & TALITOS_CCPSR_LO_IDH)
466 dev_err(dev, "illegal descriptor header error\n");
467 if (v_lo & TALITOS_CCPSR_LO_IEU)
468 dev_err(dev, "invalid execution unit error\n");
469 if (v_lo & TALITOS_CCPSR_LO_EU)
3e721aeb 470 report_eu_error(dev, ch, current_desc_hdr(dev, ch));
9c4a7965
KP		 471 if (v_lo & TALITOS_CCPSR_LO_GB)
472 dev_err(dev, "gather boundary error\n");
473 if (v_lo & TALITOS_CCPSR_LO_GRL)
474 dev_err(dev, "gather return/length error\n");
475 if (v_lo & TALITOS_CCPSR_LO_SB)
476 dev_err(dev, "scatter boundary error\n");
477 if (v_lo & TALITOS_CCPSR_LO_SRL)
478 dev_err(dev, "scatter return/length error\n");
479
480 flush_channel(dev, ch, error, reset_ch);
481
482 if (reset_ch) {
483 reset_channel(dev, ch);
484 } else {
ad42d5fc 485 setbits32(priv->chan[ch].reg + TALITOS_CCCR,
9c4a7965 486 TALITOS_CCCR_CONT);
ad42d5fc
KP		 487 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, 0);
488 while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
9c4a7965
KP		 489 TALITOS_CCCR_CONT) && --timeout)
490 cpu_relax();
491 if (timeout == 0) {
492 dev_err(dev, "failed to restart channel %d\n",
493 ch);
494 reset_dev = 1;
495 }
496 }
497 }
c3e337f8 498 if (reset_dev || isr & ~TALITOS_ISR_4CHERR || isr_lo) {
9c4a7965
KP		 499 dev_err(dev, "done overflow, internal time out, or rngu error: "
500 "ISR 0x%08x_%08x\n", isr, isr_lo);
501
502 /* purge request queues */
503 for (ch = 0; ch < priv->num_channels; ch++)
504 flush_channel(dev, ch, -EIO, 1);
505
506 /* reset and reinitialize the device */
507 init_device(dev);
508 }
509}
510
c3e337f8
KP		 511#define DEF_TALITOS_INTERRUPT(name, ch_done_mask, ch_err_mask, tlet) \
512static irqreturn_t talitos_interrupt_##name(int irq, void *data) \
513{ \
514 struct device *dev = data; \
515 struct talitos_private *priv = dev_get_drvdata(dev); \
516 u32 isr, isr_lo; \
511d63cb 517 unsigned long flags; \
c3e337f8 518 \
511d63cb 519 spin_lock_irqsave(&priv->reg_lock, flags); \
c3e337f8
KP		 520 isr = in_be32(priv->reg + TALITOS_ISR); \
521 isr_lo = in_be32(priv->reg + TALITOS_ISR_LO); \
522 /* Acknowledge interrupt */ \
523 out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \
524 out_be32(priv->reg + TALITOS_ICR_LO, isr_lo); \
525 \
511d63cb
HG		 526 if (unlikely(isr & ch_err_mask || isr_lo)) { \
527 spin_unlock_irqrestore(&priv->reg_lock, flags); \
528 talitos_error(dev, isr & ch_err_mask, isr_lo); \
529 } \
530 else { \
c3e337f8
KP		 531 if (likely(isr & ch_done_mask)) { \
532 /* mask further done interrupts. */ \
533 clrbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
534 /* done_task will unmask done interrupts at exit */ \
535 tasklet_schedule(&priv->done_task[tlet]); \
536 } \
511d63cb
HG		 537 spin_unlock_irqrestore(&priv->reg_lock, flags); \
538 } \
c3e337f8
KP		 539 \
540 return (isr & (ch_done_mask | ch_err_mask) || isr_lo) ? IRQ_HANDLED : \
541 IRQ_NONE; \
9c4a7965 542}
c3e337f8
KP		 543DEF_TALITOS_INTERRUPT(4ch, TALITOS_ISR_4CHDONE, TALITOS_ISR_4CHERR, 0)
544DEF_TALITOS_INTERRUPT(ch0_2, TALITOS_ISR_CH_0_2_DONE, TALITOS_ISR_CH_0_2_ERR, 0)
545DEF_TALITOS_INTERRUPT(ch1_3, TALITOS_ISR_CH_1_3_DONE, TALITOS_ISR_CH_1_3_ERR, 1)
9c4a7965
KP		 546
547/*
548 * hwrng
549 */
550static int talitos_rng_data_present(struct hwrng *rng, int wait)
551{
552 struct device *dev = (struct device *)rng->priv;
553 struct talitos_private *priv = dev_get_drvdata(dev);
554 u32 ofl;
555 int i;
556
557 for (i = 0; i < 20; i++) {
558 ofl = in_be32(priv->reg + TALITOS_RNGUSR_LO) &
559 TALITOS_RNGUSR_LO_OFL;
560 if (ofl || !wait)
561 break;
562 udelay(10);
563 }
564
565 return !!ofl;
566}
567
568static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
569{
570 struct device *dev = (struct device *)rng->priv;
571 struct talitos_private *priv = dev_get_drvdata(dev);
572
573 /* rng fifo requires 64-bit accesses */
574 *data = in_be32(priv->reg + TALITOS_RNGU_FIFO);
575 *data = in_be32(priv->reg + TALITOS_RNGU_FIFO_LO);
576
577 return sizeof(u32);
578}
579
580static int talitos_rng_init(struct hwrng *rng)
581{
582 struct device *dev = (struct device *)rng->priv;
583 struct talitos_private *priv = dev_get_drvdata(dev);
584 unsigned int timeout = TALITOS_TIMEOUT;
585
586 setbits32(priv->reg + TALITOS_RNGURCR_LO, TALITOS_RNGURCR_LO_SR);
587 while (!(in_be32(priv->reg + TALITOS_RNGUSR_LO) & TALITOS_RNGUSR_LO_RD)
588 && --timeout)
589 cpu_relax();
590 if (timeout == 0) {
591 dev_err(dev, "failed to reset rng hw\n");
592 return -ENODEV;
593 }
594
595 /* start generating */
596 setbits32(priv->reg + TALITOS_RNGUDSR_LO, 0);
597
598 return 0;
599}
600
601static int talitos_register_rng(struct device *dev)
602{
603 struct talitos_private *priv = dev_get_drvdata(dev);
604
605 priv->rng.name = dev_driver_string(dev),
606 priv->rng.init = talitos_rng_init,
607 priv->rng.data_present = talitos_rng_data_present,
608 priv->rng.data_read = talitos_rng_data_read,
609 priv->rng.priv = (unsigned long)dev;
610
611 return hwrng_register(&priv->rng);
612}
613
614static void talitos_unregister_rng(struct device *dev)
615{
616 struct talitos_private *priv = dev_get_drvdata(dev);
617
618 hwrng_unregister(&priv->rng);
619}
620
621/*
622 * crypto alg
623 */
624#define TALITOS_CRA_PRIORITY 3000
625#define TALITOS_MAX_KEY_SIZE 64
3952f17e 626#define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
70bcaca7 627
497f2e6b 628#define MD5_BLOCK_SIZE 64
9c4a7965
KP		 629
630struct talitos_ctx {
631 struct device *dev;
5228f0f7 632 int ch;
9c4a7965
KP		 633 __be32 desc_hdr_template;
634 u8 key[TALITOS_MAX_KEY_SIZE];
70bcaca7 635 u8 iv[TALITOS_MAX_IV_LENGTH];
9c4a7965
KP		 636 unsigned int keylen;
637 unsigned int enckeylen;
638 unsigned int authkeylen;
639 unsigned int authsize;
640};
641
497f2e6b
LN		 642#define HASH_MAX_BLOCK_SIZE SHA512_BLOCK_SIZE
643#define TALITOS_MDEU_MAX_CONTEXT_SIZE TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
644
645struct talitos_ahash_req_ctx {
60f208d7 646 u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
497f2e6b
LN		 647 unsigned int hw_context_size;
648 u8 buf[HASH_MAX_BLOCK_SIZE];
649 u8 bufnext[HASH_MAX_BLOCK_SIZE];
60f208d7 650 unsigned int swinit;
497f2e6b
LN		 651 unsigned int first;
652 unsigned int last;
653 unsigned int to_hash_later;
5e833bc4 654 u64 nbuf;
497f2e6b
LN		 655 struct scatterlist bufsl[2];
656 struct scatterlist *psrc;
657};
658
56af8cd4
LN		 659static int aead_setauthsize(struct crypto_aead *authenc,
660 unsigned int authsize)
9c4a7965
KP		 661{
662 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
663
664 ctx->authsize = authsize;
665
666 return 0;
667}
668
56af8cd4
LN		 669static int aead_setkey(struct crypto_aead *authenc,
670 const u8 *key, unsigned int keylen)
9c4a7965
KP		 671{
672 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
673 struct rtattr *rta = (void *)key;
674 struct crypto_authenc_key_param *param;
675 unsigned int authkeylen;
676 unsigned int enckeylen;
677
678 if (!RTA_OK(rta, keylen))
679 goto badkey;
680
681 if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM)
682 goto badkey;
683
684 if (RTA_PAYLOAD(rta) < sizeof(*param))
685 goto badkey;
686
687 param = RTA_DATA(rta);
688 enckeylen = be32_to_cpu(param->enckeylen);
689
690 key += RTA_ALIGN(rta->rta_len);
691 keylen -= RTA_ALIGN(rta->rta_len);
692
693 if (keylen < enckeylen)
694 goto badkey;
695
696 authkeylen = keylen - enckeylen;
697
698 if (keylen > TALITOS_MAX_KEY_SIZE)
699 goto badkey;
700
701 memcpy(&ctx->key, key, keylen);
702
703 ctx->keylen = keylen;
704 ctx->enckeylen = enckeylen;
705 ctx->authkeylen = authkeylen;
706
707 return 0;
708
709badkey:
710 crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
711 return -EINVAL;
712}
713
714/*
56af8cd4 715 * talitos_edesc - s/w-extended descriptor
9c4a7965
KP		 716 * @src_nents: number of segments in input scatterlist
717 * @dst_nents: number of segments in output scatterlist
718 * @dma_len: length of dma mapped link_tbl space
719 * @dma_link_tbl: bus physical address of link_tbl
720 * @desc: h/w descriptor
721 * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1)
722 *
723 * if decrypting (with authcheck), or either one of src_nents or dst_nents
724 * is greater than 1, an integrity check value is concatenated to the end
725 * of link_tbl data
726 */
56af8cd4 727struct talitos_edesc {
9c4a7965
KP		 728 int src_nents;
729 int dst_nents;
4de9d0b5
LN		 730 int src_is_chained;
731 int dst_is_chained;
9c4a7965
KP		 732 int dma_len;
733 dma_addr_t dma_link_tbl;
734 struct talitos_desc desc;
735 struct talitos_ptr link_tbl[0];
736};
737
4de9d0b5
LN		 738static int talitos_map_sg(struct device *dev, struct scatterlist *sg,
739 unsigned int nents, enum dma_data_direction dir,
740 int chained)
741{
742 if (unlikely(chained))
743 while (sg) {
744 dma_map_sg(dev, sg, 1, dir);
745 sg = scatterwalk_sg_next(sg);
746 }
747 else
748 dma_map_sg(dev, sg, nents, dir);
749 return nents;
750}
751
752static void talitos_unmap_sg_chain(struct device *dev, struct scatterlist *sg,
753 enum dma_data_direction dir)
754{
755 while (sg) {
756 dma_unmap_sg(dev, sg, 1, dir);
757 sg = scatterwalk_sg_next(sg);
758 }
759}
760
761static void talitos_sg_unmap(struct device *dev,
762 struct talitos_edesc *edesc,
763 struct scatterlist *src,
764 struct scatterlist *dst)
765{
766 unsigned int src_nents = edesc->src_nents ? : 1;
767 unsigned int dst_nents = edesc->dst_nents ? : 1;
768
769 if (src != dst) {
770 if (edesc->src_is_chained)
771 talitos_unmap_sg_chain(dev, src, DMA_TO_DEVICE);
772 else
773 dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
774
497f2e6b
LN		 775 if (dst) {
776 if (edesc->dst_is_chained)
777 talitos_unmap_sg_chain(dev, dst,
778 DMA_FROM_DEVICE);
779 else
780 dma_unmap_sg(dev, dst, dst_nents,
781 DMA_FROM_DEVICE);
782 }
4de9d0b5
LN		 783 } else
784 if (edesc->src_is_chained)
785 talitos_unmap_sg_chain(dev, src, DMA_BIDIRECTIONAL);
786 else
787 dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
788}
789
9c4a7965 790static void ipsec_esp_unmap(struct device *dev,
56af8cd4 791 struct talitos_edesc *edesc,
9c4a7965
KP		 792 struct aead_request *areq)
793{
794 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE);
795 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE);
796 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
797 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE);
798
799 dma_unmap_sg(dev, areq->assoc, 1, DMA_TO_DEVICE);
800
4de9d0b5 801 talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
9c4a7965
KP		 802
803 if (edesc->dma_len)
804 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
805 DMA_BIDIRECTIONAL);
806}
807
808/*
809 * ipsec_esp descriptor callbacks
810 */
811static void ipsec_esp_encrypt_done(struct device *dev,
812 struct talitos_desc *desc, void *context,
813 int err)
814{
815 struct aead_request *areq = context;
9c4a7965
KP		 816 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
817 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
19bbbc63 818 struct talitos_edesc *edesc;
9c4a7965
KP		 819 struct scatterlist *sg;
820 void *icvdata;
821
19bbbc63
KP		 822 edesc = container_of(desc, struct talitos_edesc, desc);
823
9c4a7965
KP		 824 ipsec_esp_unmap(dev, edesc, areq);
825
826 /* copy the generated ICV to dst */
827 if (edesc->dma_len) {
828 icvdata = &edesc->link_tbl[edesc->src_nents +
f3c85bc1 829 edesc->dst_nents + 2];
9c4a7965
KP		 830 sg = sg_last(areq->dst, edesc->dst_nents);
831 memcpy((char *)sg_virt(sg) + sg->length - ctx->authsize,
832 icvdata, ctx->authsize);
833 }
834
835 kfree(edesc);
836
837 aead_request_complete(areq, err);
838}
839
fe5720e2 840static void ipsec_esp_decrypt_swauth_done(struct device *dev,
e938e465
KP		 841 struct talitos_desc *desc,
842 void *context, int err)
9c4a7965
KP		 843{
844 struct aead_request *req = context;
9c4a7965
KP		 845 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
846 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
19bbbc63 847 struct talitos_edesc *edesc;
9c4a7965
KP		 848 struct scatterlist *sg;
849 void *icvdata;
850
19bbbc63
KP		 851 edesc = container_of(desc, struct talitos_edesc, desc);
852
9c4a7965
KP		 853 ipsec_esp_unmap(dev, edesc, req);
854
855 if (!err) {
856 /* auth check */
857 if (edesc->dma_len)
858 icvdata = &edesc->link_tbl[edesc->src_nents +
f3c85bc1 859 edesc->dst_nents + 2];
9c4a7965
KP		 860 else
861 icvdata = &edesc->link_tbl[0];
862
863 sg = sg_last(req->dst, edesc->dst_nents ? : 1);
864 err = memcmp(icvdata, (char *)sg_virt(sg) + sg->length -
865 ctx->authsize, ctx->authsize) ? -EBADMSG : 0;
866 }
867
868 kfree(edesc);
869
870 aead_request_complete(req, err);
871}
872
fe5720e2 873static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
e938e465
KP		 874 struct talitos_desc *desc,
875 void *context, int err)
fe5720e2
KP		 876{
877 struct aead_request *req = context;
19bbbc63
KP		 878 struct talitos_edesc *edesc;
879
880 edesc = container_of(desc, struct talitos_edesc, desc);
fe5720e2
KP		 881
882 ipsec_esp_unmap(dev, edesc, req);
883
884 /* check ICV auth status */
e938e465
KP		 885 if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
886 DESC_HDR_LO_ICCR1_PASS))
887 err = -EBADMSG;
fe5720e2
KP		 888
889 kfree(edesc);
890
891 aead_request_complete(req, err);
892}
893
9c4a7965
KP		 894/*
895 * convert scatterlist to SEC h/w link table format
896 * stop at cryptlen bytes
897 */
70bcaca7 898static int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
9c4a7965
KP		 899 int cryptlen, struct talitos_ptr *link_tbl_ptr)
900{
70bcaca7
LN		 901 int n_sg = sg_count;
902
903 while (n_sg--) {
81eb024c 904 to_talitos_ptr(link_tbl_ptr, sg_dma_address(sg));
9c4a7965
KP		 905 link_tbl_ptr->len = cpu_to_be16(sg_dma_len(sg));
906 link_tbl_ptr->j_extent = 0;
907 link_tbl_ptr++;
908 cryptlen -= sg_dma_len(sg);
4de9d0b5 909 sg = scatterwalk_sg_next(sg);
9c4a7965
KP		 910 }
911
70bcaca7 912 /* adjust (decrease) last one (or two) entry's len to cryptlen */
9c4a7965 913 link_tbl_ptr--;
c0e741d4 914 while (be16_to_cpu(link_tbl_ptr->len) <= (-cryptlen)) {
70bcaca7
LN		 915 /* Empty this entry, and move to previous one */
916 cryptlen += be16_to_cpu(link_tbl_ptr->len);
917 link_tbl_ptr->len = 0;
918 sg_count--;
919 link_tbl_ptr--;
920 }
9c4a7965
KP		 921 link_tbl_ptr->len = cpu_to_be16(be16_to_cpu(link_tbl_ptr->len)
922 + cryptlen);
923
924 /* tag end of link table */
925 link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
70bcaca7
LN		 926
927 return sg_count;
9c4a7965
KP		 928}
929
930/*
931 * fill in and submit ipsec_esp descriptor
932 */
56af8cd4 933static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
9c4a7965
KP		 934 u8 *giv, u64 seq,
935 void (*callback) (struct device *dev,
936 struct talitos_desc *desc,
937 void *context, int error))
938{
939 struct crypto_aead *aead = crypto_aead_reqtfm(areq);
940 struct talitos_ctx *ctx = crypto_aead_ctx(aead);
941 struct device *dev = ctx->dev;
942 struct talitos_desc *desc = &edesc->desc;
943 unsigned int cryptlen = areq->cryptlen;
944 unsigned int authsize = ctx->authsize;
e41256f1 945 unsigned int ivsize = crypto_aead_ivsize(aead);
fa86a267 946 int sg_count, ret;
fe5720e2 947 int sg_link_tbl_len;
9c4a7965
KP		 948
949 /* hmac key */
950 map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
951 0, DMA_TO_DEVICE);
952 /* hmac data */
e41256f1
KP		 953 map_single_talitos_ptr(dev, &desc->ptr[1], areq->assoclen + ivsize,
954 sg_virt(areq->assoc), 0, DMA_TO_DEVICE);
9c4a7965 955 /* cipher iv */
9c4a7965
KP		 956 map_single_talitos_ptr(dev, &desc->ptr[2], ivsize, giv ?: areq->iv, 0,
957 DMA_TO_DEVICE);
958
959 /* cipher key */
960 map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen,
961 (char *)&ctx->key + ctx->authkeylen, 0,
962 DMA_TO_DEVICE);
963
964 /*
965 * cipher in
966 * map and adjust cipher len to aead request cryptlen.
967 * extent is bytes of HMAC postpended to ciphertext,
968 * typically 12 for ipsec
969 */
970 desc->ptr[4].len = cpu_to_be16(cryptlen);
971 desc->ptr[4].j_extent = authsize;
972
e938e465
KP		 973 sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
974 (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
975 : DMA_TO_DEVICE,
4de9d0b5 976 edesc->src_is_chained);
9c4a7965
KP		 977
978 if (sg_count == 1) {
81eb024c 979 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src));
9c4a7965 980 } else {
fe5720e2
KP		 981 sg_link_tbl_len = cryptlen;
982
962a9c99 983 if (edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV)
fe5720e2 984 sg_link_tbl_len = cryptlen + authsize;
e938e465 985
fe5720e2 986 sg_count = sg_to_link_tbl(areq->src, sg_count, sg_link_tbl_len,
70bcaca7
LN		 987 &edesc->link_tbl[0]);
988 if (sg_count > 1) {
989 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
81eb024c 990 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl);
e938e465
KP		 991 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
992 edesc->dma_len,
993 DMA_BIDIRECTIONAL);
70bcaca7
LN		 994 } else {
995 /* Only one segment now, so no link tbl needed */
81eb024c
KP		 996 to_talitos_ptr(&desc->ptr[4],
997 sg_dma_address(areq->src));
70bcaca7 998 }
9c4a7965
KP		 999 }
1000
1001 /* cipher out */
1002 desc->ptr[5].len = cpu_to_be16(cryptlen);
1003 desc->ptr[5].j_extent = authsize;
1004
e938e465 1005 if (areq->src != areq->dst)
4de9d0b5
LN		 1006 sg_count = talitos_map_sg(dev, areq->dst,
1007 edesc->dst_nents ? : 1,
1008 DMA_FROM_DEVICE,
1009 edesc->dst_is_chained);
9c4a7965
KP		 1010
1011 if (sg_count == 1) {
81eb024c 1012 to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst));
9c4a7965
KP		 1013 } else {
1014 struct talitos_ptr *link_tbl_ptr =
f3c85bc1 1015 &edesc->link_tbl[edesc->src_nents + 1];
9c4a7965 1016
81eb024c
KP		 1017 to_talitos_ptr(&desc->ptr[5], edesc->dma_link_tbl +
1018 (edesc->src_nents + 1) *
1019 sizeof(struct talitos_ptr));
fe5720e2
KP		 1020 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1021 link_tbl_ptr);
1022
f3c85bc1 1023 /* Add an entry to the link table for ICV data */
9c4a7965 1024 link_tbl_ptr += sg_count - 1;
9c4a7965 1025 link_tbl_ptr->j_extent = 0;
f3c85bc1 1026 sg_count++;
9c4a7965
KP		 1027 link_tbl_ptr++;
1028 link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
1029 link_tbl_ptr->len = cpu_to_be16(authsize);
1030
1031 /* icv data follows link tables */
81eb024c
KP		 1032 to_talitos_ptr(link_tbl_ptr, edesc->dma_link_tbl +
1033 (edesc->src_nents + edesc->dst_nents + 2) *
1034 sizeof(struct talitos_ptr));
9c4a7965
KP		 1035 desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
1036 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1037 edesc->dma_len, DMA_BIDIRECTIONAL);
1038 }
1039
1040 /* iv out */
1041 map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, 0,
1042 DMA_FROM_DEVICE);
1043
5228f0f7 1044 ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
fa86a267
KP		 1045 if (ret != -EINPROGRESS) {
1046 ipsec_esp_unmap(dev, edesc, areq);
1047 kfree(edesc);
1048 }
1049 return ret;
9c4a7965
KP		 1050}
1051
9c4a7965
KP		 1052/*
1053 * derive number of elements in scatterlist
1054 */
4de9d0b5 1055static int sg_count(struct scatterlist *sg_list, int nbytes, int *chained)
9c4a7965
KP		 1056{
1057 struct scatterlist *sg = sg_list;
1058 int sg_nents = 0;
1059
4de9d0b5
LN		 1060 *chained = 0;
1061 while (nbytes > 0) {
9c4a7965
KP		 1062 sg_nents++;
1063 nbytes -= sg->length;
4de9d0b5
LN		 1064 if (!sg_is_last(sg) && (sg + 1)->length == 0)
1065 *chained = 1;
1066 sg = scatterwalk_sg_next(sg);
9c4a7965
KP		 1067 }
1068
1069 return sg_nents;
1070}
1071
497f2e6b
LN		 1072/**
1073 * sg_copy_end_to_buffer - Copy end data from SG list to a linear buffer
1074 * @sgl: The SG list
1075 * @nents: Number of SG entries
1076 * @buf: Where to copy to
1077 * @buflen: The number of bytes to copy
1078 * @skip: The number of bytes to skip before copying.
1079 * Note: skip + buflen should equal SG total size.
1080 *
1081 * Returns the number of copied bytes.
1082 *
1083 **/
1084static size_t sg_copy_end_to_buffer(struct scatterlist *sgl, unsigned int nents,
1085 void *buf, size_t buflen, unsigned int skip)
1086{
1087 unsigned int offset = 0;
1088 unsigned int boffset = 0;
1089 struct sg_mapping_iter miter;
1090 unsigned long flags;
1091 unsigned int sg_flags = SG_MITER_ATOMIC;
1092 size_t total_buffer = buflen + skip;
1093
1094 sg_flags |= SG_MITER_FROM_SG;
1095
1096 sg_miter_start(&miter, sgl, nents, sg_flags);
1097
1098 local_irq_save(flags);
1099
1100 while (sg_miter_next(&miter) && offset < total_buffer) {
1101 unsigned int len;
1102 unsigned int ignore;
1103
1104 if ((offset + miter.length) > skip) {
1105 if (offset < skip) {
1106 /* Copy part of this segment */
1107 ignore = skip - offset;
1108 len = miter.length - ignore;
7260042b
LN		 1109 if (boffset + len > buflen)
1110 len = buflen - boffset;
497f2e6b
LN		 1111 memcpy(buf + boffset, miter.addr + ignore, len);
1112 } else {
7260042b 1113 /* Copy all of this segment (up to buflen) */
497f2e6b 1114 len = miter.length;
7260042b
LN		 1115 if (boffset + len > buflen)
1116 len = buflen - boffset;
497f2e6b
LN		 1117 memcpy(buf + boffset, miter.addr, len);
1118 }
1119 boffset += len;
1120 }
1121 offset += miter.length;
1122 }
1123
1124 sg_miter_stop(&miter);
1125
1126 local_irq_restore(flags);
1127 return boffset;
1128}
1129
9c4a7965 1130/*
56af8cd4 1131 * allocate and map the extended descriptor
9c4a7965 1132 */
4de9d0b5
LN		 1133static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
1134 struct scatterlist *src,
1135 struct scatterlist *dst,
497f2e6b 1136 int hash_result,
4de9d0b5
LN		 1137 unsigned int cryptlen,
1138 unsigned int authsize,
1139 int icv_stashing,
1140 u32 cryptoflags)
9c4a7965 1141{
56af8cd4 1142 struct talitos_edesc *edesc;
9c4a7965 1143 int src_nents, dst_nents, alloc_len, dma_len;
4de9d0b5
LN		 1144 int src_chained, dst_chained = 0;
1145 gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
586725f8 1146 GFP_ATOMIC;
9c4a7965 1147
4de9d0b5
LN		 1148 if (cryptlen + authsize > TALITOS_MAX_DATA_LEN) {
1149 dev_err(dev, "length exceeds h/w max limit\n");
9c4a7965
KP		 1150 return ERR_PTR(-EINVAL);
1151 }
1152
4de9d0b5 1153 src_nents = sg_count(src, cryptlen + authsize, &src_chained);
9c4a7965
KP		 1154 src_nents = (src_nents == 1) ? 0 : src_nents;
1155
497f2e6b
LN		 1156 if (hash_result) {
1157 dst_nents = 0;
9c4a7965 1158 } else {
497f2e6b
LN		 1159 if (dst == src) {
1160 dst_nents = src_nents;
1161 } else {
1162 dst_nents = sg_count(dst, cryptlen + authsize,
1163 &dst_chained);
1164 dst_nents = (dst_nents == 1) ? 0 : dst_nents;
1165 }
9c4a7965
KP		 1166 }
1167
1168 /*
1169 * allocate space for base edesc plus the link tables,
f3c85bc1 1170 * allowing for two separate entries for ICV and generated ICV (+ 2),
9c4a7965
KP		 1171 * and the ICV data itself
1172 */
56af8cd4 1173 alloc_len = sizeof(struct talitos_edesc);
9c4a7965 1174 if (src_nents || dst_nents) {
f3c85bc1 1175 dma_len = (src_nents + dst_nents + 2) *
4de9d0b5 1176 sizeof(struct talitos_ptr) + authsize;
9c4a7965
KP		 1177 alloc_len += dma_len;
1178 } else {
1179 dma_len = 0;
4de9d0b5 1180 alloc_len += icv_stashing ? authsize : 0;
9c4a7965
KP		 1181 }
1182
586725f8 1183 edesc = kmalloc(alloc_len, GFP_DMA | flags);
9c4a7965 1184 if (!edesc) {
4de9d0b5 1185 dev_err(dev, "could not allocate edescriptor\n");
9c4a7965
KP		 1186 return ERR_PTR(-ENOMEM);
1187 }
1188
1189 edesc->src_nents = src_nents;
1190 edesc->dst_nents = dst_nents;
4de9d0b5
LN		 1191 edesc->src_is_chained = src_chained;
1192 edesc->dst_is_chained = dst_chained;
9c4a7965 1193 edesc->dma_len = dma_len;
497f2e6b
LN		 1194 if (dma_len)
1195 edesc->dma_link_tbl = dma_map_single(dev, &edesc->link_tbl[0],
1196 edesc->dma_len,
1197 DMA_BIDIRECTIONAL);
9c4a7965
KP		 1198
1199 return edesc;
1200}
1201
4de9d0b5
LN		 1202static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq,
1203 int icv_stashing)
1204{
1205 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1206 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1207
497f2e6b 1208 return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst, 0,
4de9d0b5
LN		 1209 areq->cryptlen, ctx->authsize, icv_stashing,
1210 areq->base.flags);
1211}
1212
56af8cd4 1213static int aead_encrypt(struct aead_request *req)
9c4a7965
KP		 1214{
1215 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1216 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
56af8cd4 1217 struct talitos_edesc *edesc;
9c4a7965
KP		 1218
1219 /* allocate extended descriptor */
4de9d0b5 1220 edesc = aead_edesc_alloc(req, 0);
9c4a7965
KP		 1221 if (IS_ERR(edesc))
1222 return PTR_ERR(edesc);
1223
1224 /* set encrypt */
70bcaca7 1225 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
9c4a7965
KP		 1226
1227 return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_encrypt_done);
1228}
1229
56af8cd4 1230static int aead_decrypt(struct aead_request *req)
9c4a7965
KP		 1231{
1232 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1233 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1234 unsigned int authsize = ctx->authsize;
fe5720e2 1235 struct talitos_private *priv = dev_get_drvdata(ctx->dev);
56af8cd4 1236 struct talitos_edesc *edesc;
9c4a7965
KP		 1237 struct scatterlist *sg;
1238 void *icvdata;
1239
1240 req->cryptlen -= authsize;
1241
1242 /* allocate extended descriptor */
4de9d0b5 1243 edesc = aead_edesc_alloc(req, 1);
9c4a7965
KP		 1244 if (IS_ERR(edesc))
1245 return PTR_ERR(edesc);
1246
fe5720e2 1247 if ((priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
e938e465
KP		 1248 ((!edesc->src_nents && !edesc->dst_nents) ||
1249 priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
9c4a7965 1250
fe5720e2 1251 /* decrypt and check the ICV */
e938e465
KP		 1252 edesc->desc.hdr = ctx->desc_hdr_template |
1253 DESC_HDR_DIR_INBOUND |
fe5720e2 1254 DESC_HDR_MODE1_MDEU_CICV;
9c4a7965 1255
fe5720e2
KP		 1256 /* reset integrity check result bits */
1257 edesc->desc.hdr_lo = 0;
9c4a7965 1258
e938e465
KP		 1259 return ipsec_esp(edesc, req, NULL, 0,
1260 ipsec_esp_decrypt_hwauth_done);
fe5720e2 1261
e938e465 1262 }
fe5720e2 1263
e938e465
KP		 1264 /* Have to check the ICV with software */
1265 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
fe5720e2 1266
e938e465
KP		 1267 /* stash incoming ICV for later cmp with ICV generated by the h/w */
1268 if (edesc->dma_len)
1269 icvdata = &edesc->link_tbl[edesc->src_nents +
1270 edesc->dst_nents + 2];
1271 else
1272 icvdata = &edesc->link_tbl[0];
fe5720e2 1273
e938e465 1274 sg = sg_last(req->src, edesc->src_nents ? : 1);
fe5720e2 1275
e938e465
KP		 1276 memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize,
1277 ctx->authsize);
fe5720e2 1278
e938e465 1279 return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_decrypt_swauth_done);
9c4a7965
KP		 1280}
1281
56af8cd4 1282static int aead_givencrypt(struct aead_givcrypt_request *req)
9c4a7965
KP		 1283{
1284 struct aead_request *areq = &req->areq;
1285 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1286 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
56af8cd4 1287 struct talitos_edesc *edesc;
9c4a7965
KP		 1288
1289 /* allocate extended descriptor */
4de9d0b5 1290 edesc = aead_edesc_alloc(areq, 0);
9c4a7965
KP		 1291 if (IS_ERR(edesc))
1292 return PTR_ERR(edesc);
1293
1294 /* set encrypt */
70bcaca7 1295 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
9c4a7965
KP		 1296
1297 memcpy(req->giv, ctx->iv, crypto_aead_ivsize(authenc));
ba95487d
KP		 1298 /* avoid consecutive packets going out with same IV */
1299 *(__be64 *)req->giv ^= cpu_to_be64(req->seq);
9c4a7965
KP		 1300
1301 return ipsec_esp(edesc, areq, req->giv, req->seq,
1302 ipsec_esp_encrypt_done);
1303}
1304
4de9d0b5
LN		 1305static int ablkcipher_setkey(struct crypto_ablkcipher *cipher,
1306 const u8 *key, unsigned int keylen)
1307{
1308 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
4de9d0b5
LN		 1309
1310 memcpy(&ctx->key, key, keylen);
1311 ctx->keylen = keylen;
1312
1313 return 0;
4de9d0b5
LN		 1314}
1315
1316static void common_nonsnoop_unmap(struct device *dev,
1317 struct talitos_edesc *edesc,
1318 struct ablkcipher_request *areq)
1319{
1320 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1321 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
1322 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
1323
1324 talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
1325
1326 if (edesc->dma_len)
1327 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1328 DMA_BIDIRECTIONAL);
1329}
1330
1331static void ablkcipher_done(struct device *dev,
1332 struct talitos_desc *desc, void *context,
1333 int err)
1334{
1335 struct ablkcipher_request *areq = context;
19bbbc63
KP		 1336 struct talitos_edesc *edesc;
1337
1338 edesc = container_of(desc, struct talitos_edesc, desc);
4de9d0b5
LN		 1339
1340 common_nonsnoop_unmap(dev, edesc, areq);
1341
1342 kfree(edesc);
1343
1344 areq->base.complete(&areq->base, err);
1345}
1346
1347static int common_nonsnoop(struct talitos_edesc *edesc,
1348 struct ablkcipher_request *areq,
4de9d0b5
LN		 1349 void (*callback) (struct device *dev,
1350 struct talitos_desc *desc,
1351 void *context, int error))
1352{
1353 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1354 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1355 struct device *dev = ctx->dev;
1356 struct talitos_desc *desc = &edesc->desc;
1357 unsigned int cryptlen = areq->nbytes;
1358 unsigned int ivsize;
1359 int sg_count, ret;
1360
1361 /* first DWORD empty */
1362 desc->ptr[0].len = 0;
81eb024c 1363 to_talitos_ptr(&desc->ptr[0], 0);
4de9d0b5
LN		 1364 desc->ptr[0].j_extent = 0;
1365
1366 /* cipher iv */
1367 ivsize = crypto_ablkcipher_ivsize(cipher);
febec542 1368 map_single_talitos_ptr(dev, &desc->ptr[1], ivsize, areq->info, 0,
4de9d0b5
LN		 1369 DMA_TO_DEVICE);
1370
1371 /* cipher key */
1372 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1373 (char *)&ctx->key, 0, DMA_TO_DEVICE);
1374
1375 /*
1376 * cipher in
1377 */
1378 desc->ptr[3].len = cpu_to_be16(cryptlen);
1379 desc->ptr[3].j_extent = 0;
1380
1381 sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1382 (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1383 : DMA_TO_DEVICE,
1384 edesc->src_is_chained);
1385
1386 if (sg_count == 1) {
81eb024c 1387 to_talitos_ptr(&desc->ptr[3], sg_dma_address(areq->src));
4de9d0b5
LN		 1388 } else {
1389 sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
1390 &edesc->link_tbl[0]);
1391 if (sg_count > 1) {
81eb024c 1392 to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
4de9d0b5 1393 desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
e938e465
KP		 1394 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1395 edesc->dma_len,
1396 DMA_BIDIRECTIONAL);
4de9d0b5
LN		 1397 } else {
1398 /* Only one segment now, so no link tbl needed */
81eb024c
KP		 1399 to_talitos_ptr(&desc->ptr[3],
1400 sg_dma_address(areq->src));
4de9d0b5
LN		 1401 }
1402 }
1403
1404 /* cipher out */
1405 desc->ptr[4].len = cpu_to_be16(cryptlen);
1406 desc->ptr[4].j_extent = 0;
1407
1408 if (areq->src != areq->dst)
1409 sg_count = talitos_map_sg(dev, areq->dst,
1410 edesc->dst_nents ? : 1,
1411 DMA_FROM_DEVICE,
1412 edesc->dst_is_chained);
1413
1414 if (sg_count == 1) {
81eb024c 1415 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->dst));
4de9d0b5
LN		 1416 } else {
1417 struct talitos_ptr *link_tbl_ptr =
1418 &edesc->link_tbl[edesc->src_nents + 1];
1419
81eb024c
KP		 1420 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl +
1421 (edesc->src_nents + 1) *
1422 sizeof(struct talitos_ptr));
4de9d0b5 1423 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
4de9d0b5
LN		 1424 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1425 link_tbl_ptr);
1426 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1427 edesc->dma_len, DMA_BIDIRECTIONAL);
1428 }
1429
1430 /* iv out */
1431 map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv, 0,
1432 DMA_FROM_DEVICE);
1433
1434 /* last DWORD empty */
1435 desc->ptr[6].len = 0;
81eb024c 1436 to_talitos_ptr(&desc->ptr[6], 0);
4de9d0b5
LN		 1437 desc->ptr[6].j_extent = 0;
1438
5228f0f7 1439 ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
4de9d0b5
LN		 1440 if (ret != -EINPROGRESS) {
1441 common_nonsnoop_unmap(dev, edesc, areq);
1442 kfree(edesc);
1443 }
1444 return ret;
1445}
1446
e938e465
KP		 1447static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request *
1448 areq)
4de9d0b5
LN		 1449{
1450 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1451 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1452
497f2e6b
LN		 1453 return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst, 0,
1454 areq->nbytes, 0, 0, areq->base.flags);
4de9d0b5
LN		 1455}
1456
1457static int ablkcipher_encrypt(struct ablkcipher_request *areq)
1458{
1459 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1460 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1461 struct talitos_edesc *edesc;
1462
1463 /* allocate extended descriptor */
1464 edesc = ablkcipher_edesc_alloc(areq);
1465 if (IS_ERR(edesc))
1466 return PTR_ERR(edesc);
1467
1468 /* set encrypt */
1469 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1470
febec542 1471 return common_nonsnoop(edesc, areq, ablkcipher_done);
4de9d0b5
LN		 1472}
1473
1474static int ablkcipher_decrypt(struct ablkcipher_request *areq)
1475{
1476 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1477 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1478 struct talitos_edesc *edesc;
1479
1480 /* allocate extended descriptor */
1481 edesc = ablkcipher_edesc_alloc(areq);
1482 if (IS_ERR(edesc))
1483 return PTR_ERR(edesc);
1484
1485 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1486
febec542 1487 return common_nonsnoop(edesc, areq, ablkcipher_done);
4de9d0b5
LN		 1488}
1489
497f2e6b
LN		 1490static void common_nonsnoop_hash_unmap(struct device *dev,
1491 struct talitos_edesc *edesc,
1492 struct ahash_request *areq)
1493{
1494 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1495
1496 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1497
1498 /* When using hashctx-in, must unmap it. */
1499 if (edesc->desc.ptr[1].len)
1500 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1],
1501 DMA_TO_DEVICE);
1502
1503 if (edesc->desc.ptr[2].len)
1504 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2],
1505 DMA_TO_DEVICE);
1506
1507 talitos_sg_unmap(dev, edesc, req_ctx->psrc, NULL);
1508
1509 if (edesc->dma_len)
1510 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1511 DMA_BIDIRECTIONAL);
1512
1513}
1514
1515static void ahash_done(struct device *dev,
1516 struct talitos_desc *desc, void *context,
1517 int err)
1518{
1519 struct ahash_request *areq = context;
1520 struct talitos_edesc *edesc =
1521 container_of(desc, struct talitos_edesc, desc);
1522 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1523
1524 if (!req_ctx->last && req_ctx->to_hash_later) {
1525 /* Position any partial block for next update/final/finup */
1526 memcpy(req_ctx->buf, req_ctx->bufnext, req_ctx->to_hash_later);
5e833bc4 1527 req_ctx->nbuf = req_ctx->to_hash_later;
497f2e6b
LN		 1528 }
1529 common_nonsnoop_hash_unmap(dev, edesc, areq);
1530
1531 kfree(edesc);
1532
1533 areq->base.complete(&areq->base, err);
1534}
1535
1536static int common_nonsnoop_hash(struct talitos_edesc *edesc,
1537 struct ahash_request *areq, unsigned int length,
1538 void (*callback) (struct device *dev,
1539 struct talitos_desc *desc,
1540 void *context, int error))
1541{
1542 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1543 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1544 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1545 struct device *dev = ctx->dev;
1546 struct talitos_desc *desc = &edesc->desc;
1547 int sg_count, ret;
1548
1549 /* first DWORD empty */
1550 desc->ptr[0] = zero_entry;
1551
60f208d7
KP		 1552 /* hash context in */
1553 if (!req_ctx->first || req_ctx->swinit) {
497f2e6b
LN		 1554 map_single_talitos_ptr(dev, &desc->ptr[1],
1555 req_ctx->hw_context_size,
1556 (char *)req_ctx->hw_context, 0,
1557 DMA_TO_DEVICE);
60f208d7 1558 req_ctx->swinit = 0;
497f2e6b
LN		 1559 } else {
1560 desc->ptr[1] = zero_entry;
1561 /* Indicate next op is not the first. */
1562 req_ctx->first = 0;
1563 }
1564
1565 /* HMAC key */
1566 if (ctx->keylen)
1567 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1568 (char *)&ctx->key, 0, DMA_TO_DEVICE);
1569 else
1570 desc->ptr[2] = zero_entry;
1571
1572 /*
1573 * data in
1574 */
1575 desc->ptr[3].len = cpu_to_be16(length);
1576 desc->ptr[3].j_extent = 0;
1577
1578 sg_count = talitos_map_sg(dev, req_ctx->psrc,
1579 edesc->src_nents ? : 1,
1580 DMA_TO_DEVICE,
1581 edesc->src_is_chained);
1582
1583 if (sg_count == 1) {
1584 to_talitos_ptr(&desc->ptr[3], sg_dma_address(req_ctx->psrc));
1585 } else {
1586 sg_count = sg_to_link_tbl(req_ctx->psrc, sg_count, length,
1587 &edesc->link_tbl[0]);
1588 if (sg_count > 1) {
1589 desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1590 to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
1591 dma_sync_single_for_device(ctx->dev,
1592 edesc->dma_link_tbl,
1593 edesc->dma_len,
1594 DMA_BIDIRECTIONAL);
1595 } else {
1596 /* Only one segment now, so no link tbl needed */
1597 to_talitos_ptr(&desc->ptr[3],
1598 sg_dma_address(req_ctx->psrc));
1599 }
1600 }
1601
1602 /* fifth DWORD empty */
1603 desc->ptr[4] = zero_entry;
1604
1605 /* hash/HMAC out -or- hash context out */
1606 if (req_ctx->last)
1607 map_single_talitos_ptr(dev, &desc->ptr[5],
1608 crypto_ahash_digestsize(tfm),
1609 areq->result, 0, DMA_FROM_DEVICE);
1610 else
1611 map_single_talitos_ptr(dev, &desc->ptr[5],
1612 req_ctx->hw_context_size,
1613 req_ctx->hw_context, 0, DMA_FROM_DEVICE);
1614
1615 /* last DWORD empty */
1616 desc->ptr[6] = zero_entry;
1617
5228f0f7 1618 ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
497f2e6b
LN		 1619 if (ret != -EINPROGRESS) {
1620 common_nonsnoop_hash_unmap(dev, edesc, areq);
1621 kfree(edesc);
1622 }
1623 return ret;
1624}
1625
1626static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
1627 unsigned int nbytes)
1628{
1629 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1630 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1631 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1632
1633 return talitos_edesc_alloc(ctx->dev, req_ctx->psrc, NULL, 1,
1634 nbytes, 0, 0, areq->base.flags);
1635}
1636
1637static int ahash_init(struct ahash_request *areq)
1638{
1639 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1640 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1641
1642 /* Initialize the context */
5e833bc4 1643 req_ctx->nbuf = 0;
60f208d7
KP		 1644 req_ctx->first = 1; /* first indicates h/w must init its context */
1645 req_ctx->swinit = 0; /* assume h/w init of context */
497f2e6b
LN		 1646 req_ctx->hw_context_size =
1647 (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
1648 ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
1649 : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
1650
1651 return 0;
1652}
1653
60f208d7
KP		 1654/*
1655 * on h/w without explicit sha224 support, we initialize h/w context
1656 * manually with sha224 constants, and tell it to run sha256.
1657 */
1658static int ahash_init_sha224_swinit(struct ahash_request *areq)
1659{
1660 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1661
1662 ahash_init(areq);
1663 req_ctx->swinit = 1;/* prevent h/w initting context with sha256 values*/
1664
a752447a
KP		 1665 req_ctx->hw_context[0] = SHA224_H0;
1666 req_ctx->hw_context[1] = SHA224_H1;
1667 req_ctx->hw_context[2] = SHA224_H2;
1668 req_ctx->hw_context[3] = SHA224_H3;
1669 req_ctx->hw_context[4] = SHA224_H4;
1670 req_ctx->hw_context[5] = SHA224_H5;
1671 req_ctx->hw_context[6] = SHA224_H6;
1672 req_ctx->hw_context[7] = SHA224_H7;
60f208d7
KP		 1673
1674 /* init 64-bit count */
1675 req_ctx->hw_context[8] = 0;
1676 req_ctx->hw_context[9] = 0;
1677
1678 return 0;
1679}
1680
497f2e6b
LN		 1681static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
1682{
1683 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1684 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1685 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1686 struct talitos_edesc *edesc;
1687 unsigned int blocksize =
1688 crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1689 unsigned int nbytes_to_hash;
1690 unsigned int to_hash_later;
5e833bc4 1691 unsigned int nsg;
497f2e6b
LN		 1692 int chained;
1693
5e833bc4
LN		 1694 if (!req_ctx->last && (nbytes + req_ctx->nbuf <= blocksize)) {
1695 /* Buffer up to one whole block */
497f2e6b
LN		 1696 sg_copy_to_buffer(areq->src,
1697 sg_count(areq->src, nbytes, &chained),
5e833bc4
LN		 1698 req_ctx->buf + req_ctx->nbuf, nbytes);
1699 req_ctx->nbuf += nbytes;
497f2e6b
LN		 1700 return 0;
1701 }
1702
5e833bc4
LN		 1703 /* At least (blocksize + 1) bytes are available to hash */
1704 nbytes_to_hash = nbytes + req_ctx->nbuf;
1705 to_hash_later = nbytes_to_hash & (blocksize - 1);
1706
1707 if (req_ctx->last)
1708 to_hash_later = 0;
1709 else if (to_hash_later)
1710 /* There is a partial block. Hash the full block(s) now */
1711 nbytes_to_hash -= to_hash_later;
1712 else {
1713 /* Keep one block buffered */
1714 nbytes_to_hash -= blocksize;
1715 to_hash_later = blocksize;
1716 }
1717
1718 /* Chain in any previously buffered data */
1719 if (req_ctx->nbuf) {
1720 nsg = (req_ctx->nbuf < nbytes_to_hash) ? 2 : 1;
1721 sg_init_table(req_ctx->bufsl, nsg);
1722 sg_set_buf(req_ctx->bufsl, req_ctx->buf, req_ctx->nbuf);
1723 if (nsg > 1)
1724 scatterwalk_sg_chain(req_ctx->bufsl, 2, areq->src);
497f2e6b 1725 req_ctx->psrc = req_ctx->bufsl;
5e833bc4 1726 } else
497f2e6b 1727 req_ctx->psrc = areq->src;
5e833bc4
LN		 1728
1729 if (to_hash_later) {
1730 int nents = sg_count(areq->src, nbytes, &chained);
1731 sg_copy_end_to_buffer(areq->src, nents,
1732 req_ctx->bufnext,
1733 to_hash_later,
1734 nbytes - to_hash_later);
497f2e6b 1735 }
5e833bc4 1736 req_ctx->to_hash_later = to_hash_later;
497f2e6b 1737
5e833bc4 1738 /* Allocate extended descriptor */
497f2e6b
LN		 1739 edesc = ahash_edesc_alloc(areq, nbytes_to_hash);
1740 if (IS_ERR(edesc))
1741 return PTR_ERR(edesc);
1742
1743 edesc->desc.hdr = ctx->desc_hdr_template;
1744
1745 /* On last one, request SEC to pad; otherwise continue */
1746 if (req_ctx->last)
1747 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
1748 else
1749 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;
1750
60f208d7
KP		 1751 /* request SEC to INIT hash. */
1752 if (req_ctx->first && !req_ctx->swinit)
497f2e6b
LN		 1753 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
1754
1755 /* When the tfm context has a keylen, it's an HMAC.
1756 * A first or last (ie. not middle) descriptor must request HMAC.
1757 */
1758 if (ctx->keylen && (req_ctx->first || req_ctx->last))
1759 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
1760
1761 return common_nonsnoop_hash(edesc, areq, nbytes_to_hash,
1762 ahash_done);
1763}
1764
1765static int ahash_update(struct ahash_request *areq)
1766{
1767 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1768
1769 req_ctx->last = 0;
1770
1771 return ahash_process_req(areq, areq->nbytes);
1772}
1773
1774static int ahash_final(struct ahash_request *areq)
1775{
1776 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1777
1778 req_ctx->last = 1;
1779
1780 return ahash_process_req(areq, 0);
1781}
1782
1783static int ahash_finup(struct ahash_request *areq)
1784{
1785 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1786
1787 req_ctx->last = 1;
1788
1789 return ahash_process_req(areq, areq->nbytes);
1790}
1791
1792static int ahash_digest(struct ahash_request *areq)
1793{
1794 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
60f208d7 1795 struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
497f2e6b 1796
60f208d7 1797 ahash->init(areq);
497f2e6b
LN		 1798 req_ctx->last = 1;
1799
1800 return ahash_process_req(areq, areq->nbytes);
1801}
1802
79b3a418
LN		 1803struct keyhash_result {
1804 struct completion completion;
1805 int err;
1806};
1807
1808static void keyhash_complete(struct crypto_async_request *req, int err)
1809{
1810 struct keyhash_result *res = req->data;
1811
1812 if (err == -EINPROGRESS)
1813 return;
1814
1815 res->err = err;
1816 complete(&res->completion);
1817}
1818
1819static int keyhash(struct crypto_ahash *tfm, const u8 *key, unsigned int keylen,
1820 u8 *hash)
1821{
1822 struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1823
1824 struct scatterlist sg[1];
1825 struct ahash_request *req;
1826 struct keyhash_result hresult;
1827 int ret;
1828
1829 init_completion(&hresult.completion);
1830
1831 req = ahash_request_alloc(tfm, GFP_KERNEL);
1832 if (!req)
1833 return -ENOMEM;
1834
1835 /* Keep tfm keylen == 0 during hash of the long key */
1836 ctx->keylen = 0;
1837 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1838 keyhash_complete, &hresult);
1839
1840 sg_init_one(&sg[0], key, keylen);
1841
1842 ahash_request_set_crypt(req, sg, hash, keylen);
1843 ret = crypto_ahash_digest(req);
1844 switch (ret) {
1845 case 0:
1846 break;
1847 case -EINPROGRESS:
1848 case -EBUSY:
1849 ret = wait_for_completion_interruptible(
1850 &hresult.completion);
1851 if (!ret)
1852 ret = hresult.err;
1853 break;
1854 default:
1855 break;
1856 }
1857 ahash_request_free(req);
1858
1859 return ret;
1860}
1861
1862static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
1863 unsigned int keylen)
1864{
1865 struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1866 unsigned int blocksize =
1867 crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1868 unsigned int digestsize = crypto_ahash_digestsize(tfm);
1869 unsigned int keysize = keylen;
1870 u8 hash[SHA512_DIGEST_SIZE];
1871 int ret;
1872
1873 if (keylen <= blocksize)
1874 memcpy(ctx->key, key, keysize);
1875 else {
1876 /* Must get the hash of the long key */
1877 ret = keyhash(tfm, key, keylen, hash);
1878
1879 if (ret) {
1880 crypto_ahash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1881 return -EINVAL;
1882 }
1883
1884 keysize = digestsize;
1885 memcpy(ctx->key, hash, digestsize);
1886 }
1887
1888 ctx->keylen = keysize;
1889
1890 return 0;
1891}
1892
1893
9c4a7965 1894struct talitos_alg_template {
d5e4aaef
LN		 1895 u32 type;
1896 union {
1897 struct crypto_alg crypto;
acbf7c62 1898 struct ahash_alg hash;
d5e4aaef 1899 } alg;
9c4a7965
KP		 1900 __be32 desc_hdr_template;
1901};
1902
1903static struct talitos_alg_template driver_algs[] = {
56af8cd4 1904 /* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
d5e4aaef
LN		 1905 { .type = CRYPTO_ALG_TYPE_AEAD,
1906 .alg.crypto = {
56af8cd4
LN		 1907 .cra_name = "authenc(hmac(sha1),cbc(aes))",
1908 .cra_driver_name = "authenc-hmac-sha1-cbc-aes-talitos",
1909 .cra_blocksize = AES_BLOCK_SIZE,
1910 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1911 .cra_type = &crypto_aead_type,
1912 .cra_aead = {
1913 .setkey = aead_setkey,
1914 .setauthsize = aead_setauthsize,
1915 .encrypt = aead_encrypt,
1916 .decrypt = aead_decrypt,
1917 .givencrypt = aead_givencrypt,
1918 .geniv = "<built-in>",
1919 .ivsize = AES_BLOCK_SIZE,
1920 .maxauthsize = SHA1_DIGEST_SIZE,
1921 }
1922 },
9c4a7965
KP		 1923 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1924 DESC_HDR_SEL0_AESU |
1925 DESC_HDR_MODE0_AESU_CBC |
1926 DESC_HDR_SEL1_MDEUA |
1927 DESC_HDR_MODE1_MDEU_INIT |
1928 DESC_HDR_MODE1_MDEU_PAD |
1929 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
70bcaca7 1930 },
d5e4aaef
LN		 1931 { .type = CRYPTO_ALG_TYPE_AEAD,
1932 .alg.crypto = {
56af8cd4
LN		 1933 .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
1934 .cra_driver_name = "authenc-hmac-sha1-cbc-3des-talitos",
1935 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1936 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1937 .cra_type = &crypto_aead_type,
1938 .cra_aead = {
1939 .setkey = aead_setkey,
1940 .setauthsize = aead_setauthsize,
1941 .encrypt = aead_encrypt,
1942 .decrypt = aead_decrypt,
1943 .givencrypt = aead_givencrypt,
1944 .geniv = "<built-in>",
1945 .ivsize = DES3_EDE_BLOCK_SIZE,
1946 .maxauthsize = SHA1_DIGEST_SIZE,
1947 }
1948 },
70bcaca7
LN		 1949 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1950 DESC_HDR_SEL0_DEU |
1951 DESC_HDR_MODE0_DEU_CBC |
1952 DESC_HDR_MODE0_DEU_3DES |
1953 DESC_HDR_SEL1_MDEUA |
1954 DESC_HDR_MODE1_MDEU_INIT |
1955 DESC_HDR_MODE1_MDEU_PAD |
1956 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
3952f17e 1957 },
d5e4aaef
LN		 1958 { .type = CRYPTO_ALG_TYPE_AEAD,
1959 .alg.crypto = {
56af8cd4
LN		 1960 .cra_name = "authenc(hmac(sha256),cbc(aes))",
1961 .cra_driver_name = "authenc-hmac-sha256-cbc-aes-talitos",
1962 .cra_blocksize = AES_BLOCK_SIZE,
1963 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1964 .cra_type = &crypto_aead_type,
1965 .cra_aead = {
1966 .setkey = aead_setkey,
1967 .setauthsize = aead_setauthsize,
1968 .encrypt = aead_encrypt,
1969 .decrypt = aead_decrypt,
1970 .givencrypt = aead_givencrypt,
1971 .geniv = "<built-in>",
1972 .ivsize = AES_BLOCK_SIZE,
1973 .maxauthsize = SHA256_DIGEST_SIZE,
1974 }
1975 },
3952f17e
LN		 1976 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1977 DESC_HDR_SEL0_AESU |
1978 DESC_HDR_MODE0_AESU_CBC |
1979 DESC_HDR_SEL1_MDEUA |
1980 DESC_HDR_MODE1_MDEU_INIT |
1981 DESC_HDR_MODE1_MDEU_PAD |
1982 DESC_HDR_MODE1_MDEU_SHA256_HMAC,
1983 },
d5e4aaef
LN		 1984 { .type = CRYPTO_ALG_TYPE_AEAD,
1985 .alg.crypto = {
56af8cd4
LN		 1986 .cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
1987 .cra_driver_name = "authenc-hmac-sha256-cbc-3des-talitos",
1988 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1989 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1990 .cra_type = &crypto_aead_type,
1991 .cra_aead = {
1992 .setkey = aead_setkey,
1993 .setauthsize = aead_setauthsize,
1994 .encrypt = aead_encrypt,
1995 .decrypt = aead_decrypt,
1996 .givencrypt = aead_givencrypt,
1997 .geniv = "<built-in>",
1998 .ivsize = DES3_EDE_BLOCK_SIZE,
1999 .maxauthsize = SHA256_DIGEST_SIZE,
2000 }
2001 },
3952f17e
LN		 2002 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2003 DESC_HDR_SEL0_DEU |
2004 DESC_HDR_MODE0_DEU_CBC |
2005 DESC_HDR_MODE0_DEU_3DES |
2006 DESC_HDR_SEL1_MDEUA |
2007 DESC_HDR_MODE1_MDEU_INIT |
2008 DESC_HDR_MODE1_MDEU_PAD |
2009 DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2010 },
d5e4aaef
LN		 2011 { .type = CRYPTO_ALG_TYPE_AEAD,
2012 .alg.crypto = {
56af8cd4
LN		 2013 .cra_name = "authenc(hmac(md5),cbc(aes))",
2014 .cra_driver_name = "authenc-hmac-md5-cbc-aes-talitos",
2015 .cra_blocksize = AES_BLOCK_SIZE,
2016 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2017 .cra_type = &crypto_aead_type,
2018 .cra_aead = {
2019 .setkey = aead_setkey,
2020 .setauthsize = aead_setauthsize,
2021 .encrypt = aead_encrypt,
2022 .decrypt = aead_decrypt,
2023 .givencrypt = aead_givencrypt,
2024 .geniv = "<built-in>",
2025 .ivsize = AES_BLOCK_SIZE,
2026 .maxauthsize = MD5_DIGEST_SIZE,
2027 }
2028 },
3952f17e
LN		 2029 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2030 DESC_HDR_SEL0_AESU |
2031 DESC_HDR_MODE0_AESU_CBC |
2032 DESC_HDR_SEL1_MDEUA |
2033 DESC_HDR_MODE1_MDEU_INIT |
2034 DESC_HDR_MODE1_MDEU_PAD |
2035 DESC_HDR_MODE1_MDEU_MD5_HMAC,
2036 },
d5e4aaef
LN		 2037 { .type = CRYPTO_ALG_TYPE_AEAD,
2038 .alg.crypto = {
56af8cd4
LN		 2039 .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
2040 .cra_driver_name = "authenc-hmac-md5-cbc-3des-talitos",
2041 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2042 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2043 .cra_type = &crypto_aead_type,
2044 .cra_aead = {
2045 .setkey = aead_setkey,
2046 .setauthsize = aead_setauthsize,
2047 .encrypt = aead_encrypt,
2048 .decrypt = aead_decrypt,
2049 .givencrypt = aead_givencrypt,
2050 .geniv = "<built-in>",
2051 .ivsize = DES3_EDE_BLOCK_SIZE,
2052 .maxauthsize = MD5_DIGEST_SIZE,
2053 }
2054 },
3952f17e
LN		 2055 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2056 DESC_HDR_SEL0_DEU |
2057 DESC_HDR_MODE0_DEU_CBC |
2058 DESC_HDR_MODE0_DEU_3DES |
2059 DESC_HDR_SEL1_MDEUA |
2060 DESC_HDR_MODE1_MDEU_INIT |
2061 DESC_HDR_MODE1_MDEU_PAD |
2062 DESC_HDR_MODE1_MDEU_MD5_HMAC,
4de9d0b5
LN		 2063 },
2064 /* ABLKCIPHER algorithms. */
d5e4aaef
LN		 2065 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2066 .alg.crypto = {
4de9d0b5
LN		 2067 .cra_name = "cbc(aes)",
2068 .cra_driver_name = "cbc-aes-talitos",
2069 .cra_blocksize = AES_BLOCK_SIZE,
2070 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2071 CRYPTO_ALG_ASYNC,
2072 .cra_type = &crypto_ablkcipher_type,
2073 .cra_ablkcipher = {
2074 .setkey = ablkcipher_setkey,
2075 .encrypt = ablkcipher_encrypt,
2076 .decrypt = ablkcipher_decrypt,
2077 .geniv = "eseqiv",
2078 .min_keysize = AES_MIN_KEY_SIZE,
2079 .max_keysize = AES_MAX_KEY_SIZE,
2080 .ivsize = AES_BLOCK_SIZE,
2081 }
2082 },
2083 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2084 DESC_HDR_SEL0_AESU |
2085 DESC_HDR_MODE0_AESU_CBC,
2086 },
d5e4aaef
LN		 2087 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2088 .alg.crypto = {
4de9d0b5
LN		 2089 .cra_name = "cbc(des3_ede)",
2090 .cra_driver_name = "cbc-3des-talitos",
2091 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2092 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2093 CRYPTO_ALG_ASYNC,
2094 .cra_type = &crypto_ablkcipher_type,
2095 .cra_ablkcipher = {
2096 .setkey = ablkcipher_setkey,
2097 .encrypt = ablkcipher_encrypt,
2098 .decrypt = ablkcipher_decrypt,
2099 .geniv = "eseqiv",
2100 .min_keysize = DES3_EDE_KEY_SIZE,
2101 .max_keysize = DES3_EDE_KEY_SIZE,
2102 .ivsize = DES3_EDE_BLOCK_SIZE,
2103 }
2104 },
2105 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2106 DESC_HDR_SEL0_DEU |
2107 DESC_HDR_MODE0_DEU_CBC |
2108 DESC_HDR_MODE0_DEU_3DES,
497f2e6b
LN		 2109 },
2110 /* AHASH algorithms. */
2111 { .type = CRYPTO_ALG_TYPE_AHASH,
2112 .alg.hash = {
2113 .init = ahash_init,
2114 .update = ahash_update,
2115 .final = ahash_final,
2116 .finup = ahash_finup,
2117 .digest = ahash_digest,
2118 .halg.digestsize = MD5_DIGEST_SIZE,
2119 .halg.base = {
2120 .cra_name = "md5",
2121 .cra_driver_name = "md5-talitos",
2122 .cra_blocksize = MD5_BLOCK_SIZE,
2123 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2124 CRYPTO_ALG_ASYNC,
2125 .cra_type = &crypto_ahash_type
2126 }
2127 },
2128 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2129 DESC_HDR_SEL0_MDEUA |
2130 DESC_HDR_MODE0_MDEU_MD5,
2131 },
2132 { .type = CRYPTO_ALG_TYPE_AHASH,
2133 .alg.hash = {
2134 .init = ahash_init,
2135 .update = ahash_update,
2136 .final = ahash_final,
2137 .finup = ahash_finup,
2138 .digest = ahash_digest,
2139 .halg.digestsize = SHA1_DIGEST_SIZE,
2140 .halg.base = {
2141 .cra_name = "sha1",
2142 .cra_driver_name = "sha1-talitos",
2143 .cra_blocksize = SHA1_BLOCK_SIZE,
2144 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2145 CRYPTO_ALG_ASYNC,
2146 .cra_type = &crypto_ahash_type
2147 }
2148 },
2149 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2150 DESC_HDR_SEL0_MDEUA |
2151 DESC_HDR_MODE0_MDEU_SHA1,
2152 },
60f208d7
KP		 2153 { .type = CRYPTO_ALG_TYPE_AHASH,
2154 .alg.hash = {
2155 .init = ahash_init,
2156 .update = ahash_update,
2157 .final = ahash_final,
2158 .finup = ahash_finup,
2159 .digest = ahash_digest,
2160 .halg.digestsize = SHA224_DIGEST_SIZE,
2161 .halg.base = {
2162 .cra_name = "sha224",
2163 .cra_driver_name = "sha224-talitos",
2164 .cra_blocksize = SHA224_BLOCK_SIZE,
2165 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2166 CRYPTO_ALG_ASYNC,
2167 .cra_type = &crypto_ahash_type
2168 }
2169 },
2170 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2171 DESC_HDR_SEL0_MDEUA |
2172 DESC_HDR_MODE0_MDEU_SHA224,
2173 },
497f2e6b
LN		 2174 { .type = CRYPTO_ALG_TYPE_AHASH,
2175 .alg.hash = {
2176 .init = ahash_init,
2177 .update = ahash_update,
2178 .final = ahash_final,
2179 .finup = ahash_finup,
2180 .digest = ahash_digest,
2181 .halg.digestsize = SHA256_DIGEST_SIZE,
2182 .halg.base = {
2183 .cra_name = "sha256",
2184 .cra_driver_name = "sha256-talitos",
2185 .cra_blocksize = SHA256_BLOCK_SIZE,
2186 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2187 CRYPTO_ALG_ASYNC,
2188 .cra_type = &crypto_ahash_type
2189 }
2190 },
2191 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2192 DESC_HDR_SEL0_MDEUA |
2193 DESC_HDR_MODE0_MDEU_SHA256,
2194 },
2195 { .type = CRYPTO_ALG_TYPE_AHASH,
2196 .alg.hash = {
2197 .init = ahash_init,
2198 .update = ahash_update,
2199 .final = ahash_final,
2200 .finup = ahash_finup,
2201 .digest = ahash_digest,
2202 .halg.digestsize = SHA384_DIGEST_SIZE,
2203 .halg.base = {
2204 .cra_name = "sha384",
2205 .cra_driver_name = "sha384-talitos",
2206 .cra_blocksize = SHA384_BLOCK_SIZE,
2207 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2208 CRYPTO_ALG_ASYNC,
2209 .cra_type = &crypto_ahash_type
2210 }
2211 },
2212 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2213 DESC_HDR_SEL0_MDEUB |
2214 DESC_HDR_MODE0_MDEUB_SHA384,
2215 },
2216 { .type = CRYPTO_ALG_TYPE_AHASH,
2217 .alg.hash = {
2218 .init = ahash_init,
2219 .update = ahash_update,
2220 .final = ahash_final,
2221 .finup = ahash_finup,
2222 .digest = ahash_digest,
2223 .halg.digestsize = SHA512_DIGEST_SIZE,
2224 .halg.base = {
2225 .cra_name = "sha512",
2226 .cra_driver_name = "sha512-talitos",
2227 .cra_blocksize = SHA512_BLOCK_SIZE,
2228 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2229 CRYPTO_ALG_ASYNC,
2230 .cra_type = &crypto_ahash_type
2231 }
2232 },
2233 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2234 DESC_HDR_SEL0_MDEUB |
2235 DESC_HDR_MODE0_MDEUB_SHA512,
2236 },
79b3a418
LN		 2237 { .type = CRYPTO_ALG_TYPE_AHASH,
2238 .alg.hash = {
2239 .init = ahash_init,
2240 .update = ahash_update,
2241 .final = ahash_final,
2242 .finup = ahash_finup,
2243 .digest = ahash_digest,
2244 .setkey = ahash_setkey,
2245 .halg.digestsize = MD5_DIGEST_SIZE,
2246 .halg.base = {
2247 .cra_name = "hmac(md5)",
2248 .cra_driver_name = "hmac-md5-talitos",
2249 .cra_blocksize = MD5_BLOCK_SIZE,
2250 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2251 CRYPTO_ALG_ASYNC,
2252 .cra_type = &crypto_ahash_type
2253 }
2254 },
2255 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2256 DESC_HDR_SEL0_MDEUA |
2257 DESC_HDR_MODE0_MDEU_MD5,
2258 },
2259 { .type = CRYPTO_ALG_TYPE_AHASH,
2260 .alg.hash = {
2261 .init = ahash_init,
2262 .update = ahash_update,
2263 .final = ahash_final,
2264 .finup = ahash_finup,
2265 .digest = ahash_digest,
2266 .setkey = ahash_setkey,
2267 .halg.digestsize = SHA1_DIGEST_SIZE,
2268 .halg.base = {
2269 .cra_name = "hmac(sha1)",
2270 .cra_driver_name = "hmac-sha1-talitos",
2271 .cra_blocksize = SHA1_BLOCK_SIZE,
2272 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2273 CRYPTO_ALG_ASYNC,
2274 .cra_type = &crypto_ahash_type
2275 }
2276 },
2277 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2278 DESC_HDR_SEL0_MDEUA |
2279 DESC_HDR_MODE0_MDEU_SHA1,
2280 },
2281 { .type = CRYPTO_ALG_TYPE_AHASH,
2282 .alg.hash = {
2283 .init = ahash_init,
2284 .update = ahash_update,
2285 .final = ahash_final,
2286 .finup = ahash_finup,
2287 .digest = ahash_digest,
2288 .setkey = ahash_setkey,
2289 .halg.digestsize = SHA224_DIGEST_SIZE,
2290 .halg.base = {
2291 .cra_name = "hmac(sha224)",
2292 .cra_driver_name = "hmac-sha224-talitos",
2293 .cra_blocksize = SHA224_BLOCK_SIZE,
2294 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2295 CRYPTO_ALG_ASYNC,
2296 .cra_type = &crypto_ahash_type
2297 }
2298 },
2299 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2300 DESC_HDR_SEL0_MDEUA |
2301 DESC_HDR_MODE0_MDEU_SHA224,
2302 },
2303 { .type = CRYPTO_ALG_TYPE_AHASH,
2304 .alg.hash = {
2305 .init = ahash_init,
2306 .update = ahash_update,
2307 .final = ahash_final,
2308 .finup = ahash_finup,
2309 .digest = ahash_digest,
2310 .setkey = ahash_setkey,
2311 .halg.digestsize = SHA256_DIGEST_SIZE,
2312 .halg.base = {
2313 .cra_name = "hmac(sha256)",
2314 .cra_driver_name = "hmac-sha256-talitos",
2315 .cra_blocksize = SHA256_BLOCK_SIZE,
2316 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2317 CRYPTO_ALG_ASYNC,
2318 .cra_type = &crypto_ahash_type
2319 }
2320 },
2321 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2322 DESC_HDR_SEL0_MDEUA |
2323 DESC_HDR_MODE0_MDEU_SHA256,
2324 },
2325 { .type = CRYPTO_ALG_TYPE_AHASH,
2326 .alg.hash = {
2327 .init = ahash_init,
2328 .update = ahash_update,
2329 .final = ahash_final,
2330 .finup = ahash_finup,
2331 .digest = ahash_digest,
2332 .setkey = ahash_setkey,
2333 .halg.digestsize = SHA384_DIGEST_SIZE,
2334 .halg.base = {
2335 .cra_name = "hmac(sha384)",
2336 .cra_driver_name = "hmac-sha384-talitos",
2337 .cra_blocksize = SHA384_BLOCK_SIZE,
2338 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2339 CRYPTO_ALG_ASYNC,
2340 .cra_type = &crypto_ahash_type
2341 }
2342 },
2343 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2344 DESC_HDR_SEL0_MDEUB |
2345 DESC_HDR_MODE0_MDEUB_SHA384,
2346 },
2347 { .type = CRYPTO_ALG_TYPE_AHASH,
2348 .alg.hash = {
2349 .init = ahash_init,
2350 .update = ahash_update,
2351 .final = ahash_final,
2352 .finup = ahash_finup,
2353 .digest = ahash_digest,
2354 .setkey = ahash_setkey,
2355 .halg.digestsize = SHA512_DIGEST_SIZE,
2356 .halg.base = {
2357 .cra_name = "hmac(sha512)",
2358 .cra_driver_name = "hmac-sha512-talitos",
2359 .cra_blocksize = SHA512_BLOCK_SIZE,
2360 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2361 CRYPTO_ALG_ASYNC,
2362 .cra_type = &crypto_ahash_type
2363 }
2364 },
2365 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2366 DESC_HDR_SEL0_MDEUB |
2367 DESC_HDR_MODE0_MDEUB_SHA512,
2368 }
9c4a7965
KP		 2369};
2370
2371struct talitos_crypto_alg {
2372 struct list_head entry;
2373 struct device *dev;
acbf7c62 2374 struct talitos_alg_template algt;
9c4a7965
KP		 2375};
2376
2377static int talitos_cra_init(struct crypto_tfm *tfm)
2378{
2379 struct crypto_alg *alg = tfm->__crt_alg;
19bbbc63 2380 struct talitos_crypto_alg *talitos_alg;
9c4a7965 2381 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
5228f0f7 2382 struct talitos_private *priv;
9c4a7965 2383
497f2e6b
LN		 2384 if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH)
2385 talitos_alg = container_of(__crypto_ahash_alg(alg),
2386 struct talitos_crypto_alg,
2387 algt.alg.hash);
2388 else
2389 talitos_alg = container_of(alg, struct talitos_crypto_alg,
2390 algt.alg.crypto);
19bbbc63 2391
9c4a7965
KP		 2392 /* update context with ptr to dev */
2393 ctx->dev = talitos_alg->dev;
19bbbc63 2394
5228f0f7
KP		 2395 /* assign SEC channel to tfm in round-robin fashion */
2396 priv = dev_get_drvdata(ctx->dev);
2397 ctx->ch = atomic_inc_return(&priv->last_chan) &
2398 (priv->num_channels - 1);
2399
9c4a7965 2400 /* copy descriptor header template value */
acbf7c62 2401 ctx->desc_hdr_template = talitos_alg->algt.desc_hdr_template;
9c4a7965 2402
602dba5a
KP		 2403 /* select done notification */
2404 ctx->desc_hdr_template |= DESC_HDR_DONE_NOTIFY;
2405
497f2e6b
LN		 2406 return 0;
2407}
2408
2409static int talitos_cra_init_aead(struct crypto_tfm *tfm)
2410{
2411 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2412
2413 talitos_cra_init(tfm);
9c4a7965
KP		 2414
2415 /* random first IV */
70bcaca7 2416 get_random_bytes(ctx->iv, TALITOS_MAX_IV_LENGTH);
9c4a7965
KP		 2417
2418 return 0;
2419}
2420
497f2e6b
LN		 2421static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
2422{
2423 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2424
2425 talitos_cra_init(tfm);
2426
2427 ctx->keylen = 0;
2428 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
2429 sizeof(struct talitos_ahash_req_ctx));
2430
2431 return 0;
2432}
2433
9c4a7965
KP		 2434/*
2435 * given the alg's descriptor header template, determine whether descriptor
2436 * type and primary/secondary execution units required match the hw
2437 * capabilities description provided in the device tree node.
2438 */
2439static int hw_supports(struct device *dev, __be32 desc_hdr_template)
2440{
2441 struct talitos_private *priv = dev_get_drvdata(dev);
2442 int ret;
2443
2444 ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
2445 (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
2446
2447 if (SECONDARY_EU(desc_hdr_template))
2448 ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
2449 & priv->exec_units);
2450
2451 return ret;
2452}
2453
2dc11581 2454static int talitos_remove(struct platform_device *ofdev)
9c4a7965
KP		 2455{
2456 struct device *dev = &ofdev->dev;
2457 struct talitos_private *priv = dev_get_drvdata(dev);
2458 struct talitos_crypto_alg *t_alg, *n;
2459 int i;
2460
2461 list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
acbf7c62
LN		 2462 switch (t_alg->algt.type) {
2463 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2464 case CRYPTO_ALG_TYPE_AEAD:
2465 crypto_unregister_alg(&t_alg->algt.alg.crypto);
2466 break;
2467 case CRYPTO_ALG_TYPE_AHASH:
2468 crypto_unregister_ahash(&t_alg->algt.alg.hash);
2469 break;
2470 }
9c4a7965
KP		 2471 list_del(&t_alg->entry);
2472 kfree(t_alg);
2473 }
2474
2475 if (hw_supports(dev, DESC_HDR_SEL0_RNG))
2476 talitos_unregister_rng(dev);
2477
4b992628 2478 for (i = 0; i < priv->num_channels; i++)
0b798247 2479 kfree(priv->chan[i].fifo);
9c4a7965 2480
4b992628 2481 kfree(priv->chan);
9c4a7965 2482
c3e337f8 2483 for (i = 0; i < 2; i++)
2cdba3cf 2484 if (priv->irq[i]) {
c3e337f8
KP		 2485 free_irq(priv->irq[i], dev);
2486 irq_dispose_mapping(priv->irq[i]);
2487 }
9c4a7965 2488
c3e337f8 2489 tasklet_kill(&priv->done_task[0]);
2cdba3cf 2490 if (priv->irq[1])
c3e337f8 2491 tasklet_kill(&priv->done_task[1]);
9c4a7965
KP		 2492
2493 iounmap(priv->reg);
2494
2495 dev_set_drvdata(dev, NULL);
2496
2497 kfree(priv);
2498
2499 return 0;
2500}
2501
2502static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
2503 struct talitos_alg_template
2504 *template)
2505{
60f208d7 2506 struct talitos_private *priv = dev_get_drvdata(dev);
9c4a7965
KP		 2507 struct talitos_crypto_alg *t_alg;
2508 struct crypto_alg *alg;
2509
2510 t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL);
2511 if (!t_alg)
2512 return ERR_PTR(-ENOMEM);
2513
acbf7c62
LN		 2514 t_alg->algt = *template;
2515
2516 switch (t_alg->algt.type) {
2517 case CRYPTO_ALG_TYPE_ABLKCIPHER:
497f2e6b
LN		 2518 alg = &t_alg->algt.alg.crypto;
2519 alg->cra_init = talitos_cra_init;
2520 break;
acbf7c62
LN		 2521 case CRYPTO_ALG_TYPE_AEAD:
2522 alg = &t_alg->algt.alg.crypto;
497f2e6b 2523 alg->cra_init = talitos_cra_init_aead;
acbf7c62
LN		 2524 break;
2525 case CRYPTO_ALG_TYPE_AHASH:
2526 alg = &t_alg->algt.alg.hash.halg.base;
497f2e6b 2527 alg->cra_init = talitos_cra_init_ahash;
79b3a418 2528 if (!(priv->features & TALITOS_FTR_HMAC_OK) &&
0b2730d8
KP		 2529 !strncmp(alg->cra_name, "hmac", 4)) {
2530 kfree(t_alg);
79b3a418 2531 return ERR_PTR(-ENOTSUPP);
0b2730d8 2532 }
60f208d7 2533 if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
79b3a418
LN		 2534 (!strcmp(alg->cra_name, "sha224") ||
2535 !strcmp(alg->cra_name, "hmac(sha224)"))) {
60f208d7
KP		 2536 t_alg->algt.alg.hash.init = ahash_init_sha224_swinit;
2537 t_alg->algt.desc_hdr_template =
2538 DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2539 DESC_HDR_SEL0_MDEUA |
2540 DESC_HDR_MODE0_MDEU_SHA256;
2541 }
497f2e6b 2542 break;
1d11911a
KP		 2543 default:
2544 dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
2545 return ERR_PTR(-EINVAL);
acbf7c62 2546 }
9c4a7965 2547
9c4a7965 2548 alg->cra_module = THIS_MODULE;
9c4a7965 2549 alg->cra_priority = TALITOS_CRA_PRIORITY;
9c4a7965 2550 alg->cra_alignmask = 0;
9c4a7965 2551 alg->cra_ctxsize = sizeof(struct talitos_ctx);
d912bb76 2552 alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
9c4a7965 2553
9c4a7965
KP		 2554 t_alg->dev = dev;
2555
2556 return t_alg;
2557}
2558
c3e337f8
KP		 2559static int talitos_probe_irq(struct platform_device *ofdev)
2560{
2561 struct device *dev = &ofdev->dev;
2562 struct device_node *np = ofdev->dev.of_node;
2563 struct talitos_private *priv = dev_get_drvdata(dev);
2564 int err;
2565
2566 priv->irq[0] = irq_of_parse_and_map(np, 0);
2cdba3cf 2567 if (!priv->irq[0]) {
c3e337f8
KP		 2568 dev_err(dev, "failed to map irq\n");
2569 return -EINVAL;
2570 }
2571
2572 priv->irq[1] = irq_of_parse_and_map(np, 1);
2573
2574 /* get the primary irq line */
2cdba3cf 2575 if (!priv->irq[1]) {
c3e337f8
KP		 2576 err = request_irq(priv->irq[0], talitos_interrupt_4ch, 0,
2577 dev_driver_string(dev), dev);
2578 goto primary_out;
2579 }
2580
2581 err = request_irq(priv->irq[0], talitos_interrupt_ch0_2, 0,
2582 dev_driver_string(dev), dev);
2583 if (err)
2584 goto primary_out;
2585
2586 /* get the secondary irq line */
2587 err = request_irq(priv->irq[1], talitos_interrupt_ch1_3, 0,
2588 dev_driver_string(dev), dev);
2589 if (err) {
2590 dev_err(dev, "failed to request secondary irq\n");
2591 irq_dispose_mapping(priv->irq[1]);
2cdba3cf 2592 priv->irq[1] = 0;
c3e337f8
KP		 2593 }
2594
2595 return err;
2596
2597primary_out:
2598 if (err) {
2599 dev_err(dev, "failed to request primary irq\n");
2600 irq_dispose_mapping(priv->irq[0]);
2cdba3cf 2601 priv->irq[0] = 0;
c3e337f8
KP		 2602 }
2603
2604 return err;
2605}
2606
1c48a5c9 2607static int talitos_probe(struct platform_device *ofdev)
9c4a7965
KP		 2608{
2609 struct device *dev = &ofdev->dev;
61c7a080 2610 struct device_node *np = ofdev->dev.of_node;
9c4a7965
KP		 2611 struct talitos_private *priv;
2612 const unsigned int *prop;
2613 int i, err;
2614
2615 priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL);
2616 if (!priv)
2617 return -ENOMEM;
2618
2619 dev_set_drvdata(dev, priv);
2620
2621 priv->ofdev = ofdev;
2622
511d63cb
HG		 2623 spin_lock_init(&priv->reg_lock);
2624
c3e337f8
KP		 2625 err = talitos_probe_irq(ofdev);
2626 if (err)
9c4a7965 2627 goto err_out;
9c4a7965 2628
2cdba3cf 2629 if (!priv->irq[1]) {
c3e337f8
KP		 2630 tasklet_init(&priv->done_task[0], talitos_done_4ch,
2631 (unsigned long)dev);
2632 } else {
2633 tasklet_init(&priv->done_task[0], talitos_done_ch0_2,
2634 (unsigned long)dev);
2635 tasklet_init(&priv->done_task[1], talitos_done_ch1_3,
2636 (unsigned long)dev);
9c4a7965
KP		 2637 }
2638
c3e337f8
KP		 2639 INIT_LIST_HEAD(&priv->alg_list);
2640
9c4a7965
KP		 2641 priv->reg = of_iomap(np, 0);
2642 if (!priv->reg) {
2643 dev_err(dev, "failed to of_iomap\n");
2644 err = -ENOMEM;
2645 goto err_out;
2646 }
2647
2648 /* get SEC version capabilities from device tree */
2649 prop = of_get_property(np, "fsl,num-channels", NULL);
2650 if (prop)
2651 priv->num_channels = *prop;
2652
2653 prop = of_get_property(np, "fsl,channel-fifo-len", NULL);
2654 if (prop)
2655 priv->chfifo_len = *prop;
2656
2657 prop = of_get_property(np, "fsl,exec-units-mask", NULL);
2658 if (prop)
2659 priv->exec_units = *prop;
2660
2661 prop = of_get_property(np, "fsl,descriptor-types-mask", NULL);
2662 if (prop)
2663 priv->desc_types = *prop;
2664
2665 if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
2666 !priv->exec_units || !priv->desc_types) {
2667 dev_err(dev, "invalid property data in device tree node\n");
2668 err = -EINVAL;
2669 goto err_out;
2670 }
2671
f3c85bc1
LN		 2672 if (of_device_is_compatible(np, "fsl,sec3.0"))
2673 priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
2674
fe5720e2 2675 if (of_device_is_compatible(np, "fsl,sec2.1"))
60f208d7 2676 priv->features |= TALITOS_FTR_HW_AUTH_CHECK |
79b3a418
LN		 2677 TALITOS_FTR_SHA224_HWINIT |
2678 TALITOS_FTR_HMAC_OK;
fe5720e2 2679
4b992628
KP		 2680 priv->chan = kzalloc(sizeof(struct talitos_channel) *
2681 priv->num_channels, GFP_KERNEL);
2682 if (!priv->chan) {
2683 dev_err(dev, "failed to allocate channel management space\n");
9c4a7965
KP		 2684 err = -ENOMEM;
2685 goto err_out;
2686 }
2687
c3e337f8
KP		 2688 for (i = 0; i < priv->num_channels; i++) {
2689 priv->chan[i].reg = priv->reg + TALITOS_CH_STRIDE * (i + 1);
2cdba3cf 2690 if (!priv->irq[1] || !(i & 1))
c3e337f8
KP		 2691 priv->chan[i].reg += TALITOS_CH_BASE_OFFSET;
2692 }
ad42d5fc 2693
9c4a7965 2694 for (i = 0; i < priv->num_channels; i++) {
4b992628
KP		 2695 spin_lock_init(&priv->chan[i].head_lock);
2696 spin_lock_init(&priv->chan[i].tail_lock);
9c4a7965
KP		 2697 }
2698
2699 priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
2700
2701 for (i = 0; i < priv->num_channels; i++) {
4b992628
KP		 2702 priv->chan[i].fifo = kzalloc(sizeof(struct talitos_request) *
2703 priv->fifo_len, GFP_KERNEL);
2704 if (!priv->chan[i].fifo) {
9c4a7965
KP		 2705 dev_err(dev, "failed to allocate request fifo %d\n", i);
2706 err = -ENOMEM;
2707 goto err_out;
2708 }
2709 }
2710
ec6644d6 2711 for (i = 0; i < priv->num_channels; i++)
4b992628
KP		 2712 atomic_set(&priv->chan[i].submit_count,
2713 -(priv->chfifo_len - 1));
9c4a7965 2714
81eb024c
KP		 2715 dma_set_mask(dev, DMA_BIT_MASK(36));
2716
9c4a7965
KP		 2717 /* reset and initialize the h/w */
2718 err = init_device(dev);
2719 if (err) {
2720 dev_err(dev, "failed to initialize device\n");
2721 goto err_out;
2722 }
2723
2724 /* register the RNG, if available */
2725 if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
2726 err = talitos_register_rng(dev);
2727 if (err) {
2728 dev_err(dev, "failed to register hwrng: %d\n", err);
2729 goto err_out;
2730 } else
2731 dev_info(dev, "hwrng\n");
2732 }
2733
2734 /* register crypto algorithms the device supports */
9c4a7965
KP		 2735 for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
2736 if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
2737 struct talitos_crypto_alg *t_alg;
acbf7c62 2738 char *name = NULL;
9c4a7965
KP		 2739
2740 t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
2741 if (IS_ERR(t_alg)) {
2742 err = PTR_ERR(t_alg);
0b2730d8 2743 if (err == -ENOTSUPP)
79b3a418 2744 continue;
9c4a7965
KP		 2745 goto err_out;
2746 }
2747
acbf7c62
LN		 2748 switch (t_alg->algt.type) {
2749 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2750 case CRYPTO_ALG_TYPE_AEAD:
2751 err = crypto_register_alg(
2752 &t_alg->algt.alg.crypto);
2753 name = t_alg->algt.alg.crypto.cra_driver_name;
2754 break;
2755 case CRYPTO_ALG_TYPE_AHASH:
2756 err = crypto_register_ahash(
2757 &t_alg->algt.alg.hash);
2758 name =
2759 t_alg->algt.alg.hash.halg.base.cra_driver_name;
2760 break;
2761 }
9c4a7965
KP		 2762 if (err) {
2763 dev_err(dev, "%s alg registration failed\n",
acbf7c62 2764 name);
9c4a7965 2765 kfree(t_alg);
5b859b6e 2766 } else
9c4a7965 2767 list_add_tail(&t_alg->entry, &priv->alg_list);
9c4a7965
KP		 2768 }
2769 }
5b859b6e
KP		 2770 if (!list_empty(&priv->alg_list))
2771 dev_info(dev, "%s algorithms registered in /proc/crypto\n",
2772 (char *)of_get_property(np, "compatible", NULL));
9c4a7965
KP		 2773
2774 return 0;
2775
2776err_out:
2777 talitos_remove(ofdev);
9c4a7965
KP		 2778
2779 return err;
2780}
2781
6c3f975a 2782static const struct of_device_id talitos_match[] = {
9c4a7965
KP		 2783 {
2784 .compatible = "fsl,sec2.0",
2785 },
2786 {},
2787};
2788MODULE_DEVICE_TABLE(of, talitos_match);
2789
1c48a5c9 2790static struct platform_driver talitos_driver = {
4018294b
GL		 2791 .driver = {
2792 .name = "talitos",
2793 .owner = THIS_MODULE,
2794 .of_match_table = talitos_match,
2795 },
9c4a7965 2796 .probe = talitos_probe,
596f1034 2797 .remove = talitos_remove,
9c4a7965
KP		 2798};
2799
741e8c2d 2800module_platform_driver(talitos_driver);
9c4a7965
KP		 2801
2802MODULE_LICENSE("GPL");
2803MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
2804MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");
Linux kernel - Deliverables
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