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crypto: talitos - simplify hmac data size calculation
[deliverable/linux.git] / drivers / crypto / talitos.c
CommitLineData
9c4a7965
KP		 1/*
2 * talitos - Freescale Integrated Security Engine (SEC) device driver
3 *
4 * Copyright (c) 2008 Freescale Semiconductor, Inc.
5 *
6 * Scatterlist Crypto API glue code copied from files with the following:
7 * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
8 *
9 * Crypto algorithm registration code copied from hifn driver:
10 * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
11 * All rights reserved.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 */
27
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/mod_devicetable.h>
31#include <linux/device.h>
32#include <linux/interrupt.h>
33#include <linux/crypto.h>
34#include <linux/hw_random.h>
35#include <linux/of_platform.h>
36#include <linux/dma-mapping.h>
37#include <linux/io.h>
38#include <linux/spinlock.h>
39#include <linux/rtnetlink.h>
40
41#include <crypto/algapi.h>
42#include <crypto/aes.h>
3952f17e 43#include <crypto/des.h>
9c4a7965
KP		 44#include <crypto/sha.h>
45#include <crypto/aead.h>
46#include <crypto/authenc.h>
4de9d0b5
LN		 47#include <crypto/skcipher.h>
48#include <crypto/scatterwalk.h>
9c4a7965
KP		 49
50#include "talitos.h"
51
52#define TALITOS_TIMEOUT 100000
53#define TALITOS_MAX_DATA_LEN 65535
54
55#define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
56#define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
57#define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
58
59/* descriptor pointer entry */
60struct talitos_ptr {
61 __be16 len; /* length */
62 u8 j_extent; /* jump to sg link table and/or extent */
63 u8 eptr; /* extended address */
64 __be32 ptr; /* address */
65};
66
67/* descriptor */
68struct talitos_desc {
69 __be32 hdr; /* header high bits */
70 __be32 hdr_lo; /* header low bits */
71 struct talitos_ptr ptr[7]; /* ptr/len pair array */
72};
73
74/**
75 * talitos_request - descriptor submission request
76 * @desc: descriptor pointer (kernel virtual)
77 * @dma_desc: descriptor's physical bus address
78 * @callback: whom to call when descriptor processing is done
79 * @context: caller context (optional)
80 */
81struct talitos_request {
82 struct talitos_desc *desc;
83 dma_addr_t dma_desc;
84 void (*callback) (struct device *dev, struct talitos_desc *desc,
85 void *context, int error);
86 void *context;
87};
88
89struct talitos_private {
90 struct device *dev;
91 struct of_device *ofdev;
92 void __iomem *reg;
93 int irq;
94
95 /* SEC version geometry (from device tree node) */
96 unsigned int num_channels;
97 unsigned int chfifo_len;
98 unsigned int exec_units;
99 unsigned int desc_types;
100
f3c85bc1
LN		 101 /* SEC Compatibility info */
102 unsigned long features;
103
9c4a7965
KP		 104 /* next channel to be assigned next incoming descriptor */
105 atomic_t last_chan;
106
ec6644d6
KP		 107 /* per-channel number of requests pending in channel h/w fifo */
108 atomic_t *submit_count;
109
9c4a7965
KP		 110 /* per-channel request fifo */
111 struct talitos_request **fifo;
112
113 /*
114 * length of the request fifo
115 * fifo_len is chfifo_len rounded up to next power of 2
116 * so we can use bitwise ops to wrap
117 */
118 unsigned int fifo_len;
119
120 /* per-channel index to next free descriptor request */
121 int *head;
122
123 /* per-channel index to next in-progress/done descriptor request */
124 int *tail;
125
126 /* per-channel request submission (head) and release (tail) locks */
127 spinlock_t *head_lock;
128 spinlock_t *tail_lock;
129
130 /* request callback tasklet */
131 struct tasklet_struct done_task;
9c4a7965
KP		 132
133 /* list of registered algorithms */
134 struct list_head alg_list;
135
136 /* hwrng device */
137 struct hwrng rng;
138};
139
f3c85bc1
LN		 140/* .features flag */
141#define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
fe5720e2 142#define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
f3c85bc1 143
9c4a7965
KP		 144/*
145 * map virtual single (contiguous) pointer to h/w descriptor pointer
146 */
147static void map_single_talitos_ptr(struct device *dev,
148 struct talitos_ptr *talitos_ptr,
149 unsigned short len, void *data,
150 unsigned char extent,
151 enum dma_data_direction dir)
152{
153 talitos_ptr->len = cpu_to_be16(len);
154 talitos_ptr->ptr = cpu_to_be32(dma_map_single(dev, data, len, dir));
155 talitos_ptr->j_extent = extent;
156}
157
158/*
159 * unmap bus single (contiguous) h/w descriptor pointer
160 */
161static void unmap_single_talitos_ptr(struct device *dev,
162 struct talitos_ptr *talitos_ptr,
163 enum dma_data_direction dir)
164{
165 dma_unmap_single(dev, be32_to_cpu(talitos_ptr->ptr),
166 be16_to_cpu(talitos_ptr->len), dir);
167}
168
169static int reset_channel(struct device *dev, int ch)
170{
171 struct talitos_private *priv = dev_get_drvdata(dev);
172 unsigned int timeout = TALITOS_TIMEOUT;
173
174 setbits32(priv->reg + TALITOS_CCCR(ch), TALITOS_CCCR_RESET);
175
176 while ((in_be32(priv->reg + TALITOS_CCCR(ch)) & TALITOS_CCCR_RESET)
177 && --timeout)
178 cpu_relax();
179
180 if (timeout == 0) {
181 dev_err(dev, "failed to reset channel %d\n", ch);
182 return -EIO;
183 }
184
185 /* set done writeback and IRQ */
186 setbits32(priv->reg + TALITOS_CCCR_LO(ch), TALITOS_CCCR_LO_CDWE |
187 TALITOS_CCCR_LO_CDIE);
188
fe5720e2
KP		 189 /* and ICCR writeback, if available */
190 if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
191 setbits32(priv->reg + TALITOS_CCCR_LO(ch),
192 TALITOS_CCCR_LO_IWSE);
193
9c4a7965
KP		 194 return 0;
195}
196
197static int reset_device(struct device *dev)
198{
199 struct talitos_private *priv = dev_get_drvdata(dev);
200 unsigned int timeout = TALITOS_TIMEOUT;
201
202 setbits32(priv->reg + TALITOS_MCR, TALITOS_MCR_SWR);
203
204 while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS_MCR_SWR)
205 && --timeout)
206 cpu_relax();
207
208 if (timeout == 0) {
209 dev_err(dev, "failed to reset device\n");
210 return -EIO;
211 }
212
213 return 0;
214}
215
216/*
217 * Reset and initialize the device
218 */
219static int init_device(struct device *dev)
220{
221 struct talitos_private *priv = dev_get_drvdata(dev);
222 int ch, err;
223
224 /*
225 * Master reset
226 * errata documentation: warning: certain SEC interrupts
227 * are not fully cleared by writing the MCR:SWR bit,
228 * set bit twice to completely reset
229 */
230 err = reset_device(dev);
231 if (err)
232 return err;
233
234 err = reset_device(dev);
235 if (err)
236 return err;
237
238 /* reset channels */
239 for (ch = 0; ch < priv->num_channels; ch++) {
240 err = reset_channel(dev, ch);
241 if (err)
242 return err;
243 }
244
245 /* enable channel done and error interrupts */
246 setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
247 setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
248
fe5720e2
KP		 249 /* disable integrity check error interrupts (use writeback instead) */
250 if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
251 setbits32(priv->reg + TALITOS_MDEUICR_LO,
252 TALITOS_MDEUICR_LO_ICE);
253
9c4a7965
KP		 254 return 0;
255}
256
257/**
258 * talitos_submit - submits a descriptor to the device for processing
259 * @dev: the SEC device to be used
260 * @desc: the descriptor to be processed by the device
261 * @callback: whom to call when processing is complete
262 * @context: a handle for use by caller (optional)
263 *
264 * desc must contain valid dma-mapped (bus physical) address pointers.
265 * callback must check err and feedback in descriptor header
266 * for device processing status.
267 */
268static int talitos_submit(struct device *dev, struct talitos_desc *desc,
269 void (*callback)(struct device *dev,
270 struct talitos_desc *desc,
271 void *context, int error),
272 void *context)
273{
274 struct talitos_private *priv = dev_get_drvdata(dev);
275 struct talitos_request *request;
276 unsigned long flags, ch;
277 int head;
278
279 /* select done notification */
280 desc->hdr |= DESC_HDR_DONE_NOTIFY;
281
282 /* emulate SEC's round-robin channel fifo polling scheme */
283 ch = atomic_inc_return(&priv->last_chan) & (priv->num_channels - 1);
284
285 spin_lock_irqsave(&priv->head_lock[ch], flags);
286
ec6644d6
KP		 287 if (!atomic_inc_not_zero(&priv->submit_count[ch])) {
288 /* h/w fifo is full */
9c4a7965
KP		 289 spin_unlock_irqrestore(&priv->head_lock[ch], flags);
290 return -EAGAIN;
291 }
292
ec6644d6
KP		 293 head = priv->head[ch];
294 request = &priv->fifo[ch][head];
295
9c4a7965
KP		 296 /* map descriptor and save caller data */
297 request->dma_desc = dma_map_single(dev, desc, sizeof(*desc),
298 DMA_BIDIRECTIONAL);
299 request->callback = callback;
300 request->context = context;
301
302 /* increment fifo head */
303 priv->head[ch] = (priv->head[ch] + 1) & (priv->fifo_len - 1);
304
305 smp_wmb();
306 request->desc = desc;
307
308 /* GO! */
309 wmb();
310 out_be32(priv->reg + TALITOS_FF_LO(ch), request->dma_desc);
311
312 spin_unlock_irqrestore(&priv->head_lock[ch], flags);
313
314 return -EINPROGRESS;
315}
316
317/*
318 * process what was done, notify callback of error if not
319 */
320static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
321{
322 struct talitos_private *priv = dev_get_drvdata(dev);
323 struct talitos_request *request, saved_req;
324 unsigned long flags;
325 int tail, status;
326
327 spin_lock_irqsave(&priv->tail_lock[ch], flags);
328
329 tail = priv->tail[ch];
330 while (priv->fifo[ch][tail].desc) {
331 request = &priv->fifo[ch][tail];
332
333 /* descriptors with their done bits set don't get the error */
334 rmb();
ca38a814 335 if ((request->desc->hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
9c4a7965 336 status = 0;
ca38a814 337 else
9c4a7965
KP		 338 if (!error)
339 break;
340 else
341 status = error;
342
343 dma_unmap_single(dev, request->dma_desc,
e938e465
KP		 344 sizeof(struct talitos_desc),
345 DMA_BIDIRECTIONAL);
9c4a7965
KP		 346
347 /* copy entries so we can call callback outside lock */
348 saved_req.desc = request->desc;
349 saved_req.callback = request->callback;
350 saved_req.context = request->context;
351
352 /* release request entry in fifo */
353 smp_wmb();
354 request->desc = NULL;
355
356 /* increment fifo tail */
357 priv->tail[ch] = (tail + 1) & (priv->fifo_len - 1);
358
359 spin_unlock_irqrestore(&priv->tail_lock[ch], flags);
ec6644d6
KP		 360
361 atomic_dec(&priv->submit_count[ch]);
362
9c4a7965
KP		 363 saved_req.callback(dev, saved_req.desc, saved_req.context,
364 status);
365 /* channel may resume processing in single desc error case */
366 if (error && !reset_ch && status == error)
367 return;
368 spin_lock_irqsave(&priv->tail_lock[ch], flags);
369 tail = priv->tail[ch];
370 }
371
372 spin_unlock_irqrestore(&priv->tail_lock[ch], flags);
373}
374
375/*
376 * process completed requests for channels that have done status
377 */
378static void talitos_done(unsigned long data)
379{
380 struct device *dev = (struct device *)data;
381 struct talitos_private *priv = dev_get_drvdata(dev);
382 int ch;
383
384 for (ch = 0; ch < priv->num_channels; ch++)
385 flush_channel(dev, ch, 0, 0);
1c2e8811
LN		 386
387 /* At this point, all completed channels have been processed.
388 * Unmask done interrupts for channels completed later on.
389 */
fe5720e2
KP		 390 setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
391 setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
9c4a7965
KP		 392}
393
394/*
395 * locate current (offending) descriptor
396 */
397static struct talitos_desc *current_desc(struct device *dev, int ch)
398{
399 struct talitos_private *priv = dev_get_drvdata(dev);
400 int tail = priv->tail[ch];
401 dma_addr_t cur_desc;
402
403 cur_desc = in_be32(priv->reg + TALITOS_CDPR_LO(ch));
404
405 while (priv->fifo[ch][tail].dma_desc != cur_desc) {
406 tail = (tail + 1) & (priv->fifo_len - 1);
407 if (tail == priv->tail[ch]) {
408 dev_err(dev, "couldn't locate current descriptor\n");
409 return NULL;
410 }
411 }
412
413 return priv->fifo[ch][tail].desc;
414}
415
416/*
417 * user diagnostics; report root cause of error based on execution unit status
418 */
e938e465
KP		 419static void report_eu_error(struct device *dev, int ch,
420 struct talitos_desc *desc)
9c4a7965
KP		 421{
422 struct talitos_private *priv = dev_get_drvdata(dev);
423 int i;
424
425 switch (desc->hdr & DESC_HDR_SEL0_MASK) {
426 case DESC_HDR_SEL0_AFEU:
427 dev_err(dev, "AFEUISR 0x%08x_%08x\n",
428 in_be32(priv->reg + TALITOS_AFEUISR),
429 in_be32(priv->reg + TALITOS_AFEUISR_LO));
430 break;
431 case DESC_HDR_SEL0_DEU:
432 dev_err(dev, "DEUISR 0x%08x_%08x\n",
433 in_be32(priv->reg + TALITOS_DEUISR),
434 in_be32(priv->reg + TALITOS_DEUISR_LO));
435 break;
436 case DESC_HDR_SEL0_MDEUA:
437 case DESC_HDR_SEL0_MDEUB:
438 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
439 in_be32(priv->reg + TALITOS_MDEUISR),
440 in_be32(priv->reg + TALITOS_MDEUISR_LO));
441 break;
442 case DESC_HDR_SEL0_RNG:
443 dev_err(dev, "RNGUISR 0x%08x_%08x\n",
444 in_be32(priv->reg + TALITOS_RNGUISR),
445 in_be32(priv->reg + TALITOS_RNGUISR_LO));
446 break;
447 case DESC_HDR_SEL0_PKEU:
448 dev_err(dev, "PKEUISR 0x%08x_%08x\n",
449 in_be32(priv->reg + TALITOS_PKEUISR),
450 in_be32(priv->reg + TALITOS_PKEUISR_LO));
451 break;
452 case DESC_HDR_SEL0_AESU:
453 dev_err(dev, "AESUISR 0x%08x_%08x\n",
454 in_be32(priv->reg + TALITOS_AESUISR),
455 in_be32(priv->reg + TALITOS_AESUISR_LO));
456 break;
457 case DESC_HDR_SEL0_CRCU:
458 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
459 in_be32(priv->reg + TALITOS_CRCUISR),
460 in_be32(priv->reg + TALITOS_CRCUISR_LO));
461 break;
462 case DESC_HDR_SEL0_KEU:
463 dev_err(dev, "KEUISR 0x%08x_%08x\n",
464 in_be32(priv->reg + TALITOS_KEUISR),
465 in_be32(priv->reg + TALITOS_KEUISR_LO));
466 break;
467 }
468
469 switch (desc->hdr & DESC_HDR_SEL1_MASK) {
470 case DESC_HDR_SEL1_MDEUA:
471 case DESC_HDR_SEL1_MDEUB:
472 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
473 in_be32(priv->reg + TALITOS_MDEUISR),
474 in_be32(priv->reg + TALITOS_MDEUISR_LO));
475 break;
476 case DESC_HDR_SEL1_CRCU:
477 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
478 in_be32(priv->reg + TALITOS_CRCUISR),
479 in_be32(priv->reg + TALITOS_CRCUISR_LO));
480 break;
481 }
482
483 for (i = 0; i < 8; i++)
484 dev_err(dev, "DESCBUF 0x%08x_%08x\n",
485 in_be32(priv->reg + TALITOS_DESCBUF(ch) + 8*i),
486 in_be32(priv->reg + TALITOS_DESCBUF_LO(ch) + 8*i));
487}
488
489/*
490 * recover from error interrupts
491 */
40405f10 492static void talitos_error(unsigned long data, u32 isr, u32 isr_lo)
9c4a7965
KP		 493{
494 struct device *dev = (struct device *)data;
495 struct talitos_private *priv = dev_get_drvdata(dev);
496 unsigned int timeout = TALITOS_TIMEOUT;
497 int ch, error, reset_dev = 0, reset_ch = 0;
40405f10 498 u32 v, v_lo;
9c4a7965
KP		 499
500 for (ch = 0; ch < priv->num_channels; ch++) {
501 /* skip channels without errors */
502 if (!(isr & (1 << (ch * 2 + 1))))
503 continue;
504
505 error = -EINVAL;
506
507 v = in_be32(priv->reg + TALITOS_CCPSR(ch));
508 v_lo = in_be32(priv->reg + TALITOS_CCPSR_LO(ch));
509
510 if (v_lo & TALITOS_CCPSR_LO_DOF) {
511 dev_err(dev, "double fetch fifo overflow error\n");
512 error = -EAGAIN;
513 reset_ch = 1;
514 }
515 if (v_lo & TALITOS_CCPSR_LO_SOF) {
516 /* h/w dropped descriptor */
517 dev_err(dev, "single fetch fifo overflow error\n");
518 error = -EAGAIN;
519 }
520 if (v_lo & TALITOS_CCPSR_LO_MDTE)
521 dev_err(dev, "master data transfer error\n");
522 if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
523 dev_err(dev, "s/g data length zero error\n");
524 if (v_lo & TALITOS_CCPSR_LO_FPZ)
525 dev_err(dev, "fetch pointer zero error\n");
526 if (v_lo & TALITOS_CCPSR_LO_IDH)
527 dev_err(dev, "illegal descriptor header error\n");
528 if (v_lo & TALITOS_CCPSR_LO_IEU)
529 dev_err(dev, "invalid execution unit error\n");
530 if (v_lo & TALITOS_CCPSR_LO_EU)
531 report_eu_error(dev, ch, current_desc(dev, ch));
532 if (v_lo & TALITOS_CCPSR_LO_GB)
533 dev_err(dev, "gather boundary error\n");
534 if (v_lo & TALITOS_CCPSR_LO_GRL)
535 dev_err(dev, "gather return/length error\n");
536 if (v_lo & TALITOS_CCPSR_LO_SB)
537 dev_err(dev, "scatter boundary error\n");
538 if (v_lo & TALITOS_CCPSR_LO_SRL)
539 dev_err(dev, "scatter return/length error\n");
540
541 flush_channel(dev, ch, error, reset_ch);
542
543 if (reset_ch) {
544 reset_channel(dev, ch);
545 } else {
546 setbits32(priv->reg + TALITOS_CCCR(ch),
547 TALITOS_CCCR_CONT);
548 setbits32(priv->reg + TALITOS_CCCR_LO(ch), 0);
549 while ((in_be32(priv->reg + TALITOS_CCCR(ch)) &
550 TALITOS_CCCR_CONT) && --timeout)
551 cpu_relax();
552 if (timeout == 0) {
553 dev_err(dev, "failed to restart channel %d\n",
554 ch);
555 reset_dev = 1;
556 }
557 }
558 }
559 if (reset_dev || isr & ~TALITOS_ISR_CHERR || isr_lo) {
560 dev_err(dev, "done overflow, internal time out, or rngu error: "
561 "ISR 0x%08x_%08x\n", isr, isr_lo);
562
563 /* purge request queues */
564 for (ch = 0; ch < priv->num_channels; ch++)
565 flush_channel(dev, ch, -EIO, 1);
566
567 /* reset and reinitialize the device */
568 init_device(dev);
569 }
570}
571
572static irqreturn_t talitos_interrupt(int irq, void *data)
573{
574 struct device *dev = data;
575 struct talitos_private *priv = dev_get_drvdata(dev);
576 u32 isr, isr_lo;
577
578 isr = in_be32(priv->reg + TALITOS_ISR);
579 isr_lo = in_be32(priv->reg + TALITOS_ISR_LO);
ca38a814
LN		 580 /* Acknowledge interrupt */
581 out_be32(priv->reg + TALITOS_ICR, isr);
582 out_be32(priv->reg + TALITOS_ICR_LO, isr_lo);
9c4a7965 583
ca38a814 584 if (unlikely((isr & ~TALITOS_ISR_CHDONE) || isr_lo))
40405f10 585 talitos_error((unsigned long)data, isr, isr_lo);
ca38a814 586 else
1c2e8811
LN		 587 if (likely(isr & TALITOS_ISR_CHDONE)) {
588 /* mask further done interrupts. */
589 clrbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_DONE);
590 /* done_task will unmask done interrupts at exit */
9c4a7965 591 tasklet_schedule(&priv->done_task);
1c2e8811 592 }
9c4a7965
KP		 593
594 return (isr || isr_lo) ? IRQ_HANDLED : IRQ_NONE;
595}
596
597/*
598 * hwrng
599 */
600static int talitos_rng_data_present(struct hwrng *rng, int wait)
601{
602 struct device *dev = (struct device *)rng->priv;
603 struct talitos_private *priv = dev_get_drvdata(dev);
604 u32 ofl;
605 int i;
606
607 for (i = 0; i < 20; i++) {
608 ofl = in_be32(priv->reg + TALITOS_RNGUSR_LO) &
609 TALITOS_RNGUSR_LO_OFL;
610 if (ofl || !wait)
611 break;
612 udelay(10);
613 }
614
615 return !!ofl;
616}
617
618static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
619{
620 struct device *dev = (struct device *)rng->priv;
621 struct talitos_private *priv = dev_get_drvdata(dev);
622
623 /* rng fifo requires 64-bit accesses */
624 *data = in_be32(priv->reg + TALITOS_RNGU_FIFO);
625 *data = in_be32(priv->reg + TALITOS_RNGU_FIFO_LO);
626
627 return sizeof(u32);
628}
629
630static int talitos_rng_init(struct hwrng *rng)
631{
632 struct device *dev = (struct device *)rng->priv;
633 struct talitos_private *priv = dev_get_drvdata(dev);
634 unsigned int timeout = TALITOS_TIMEOUT;
635
636 setbits32(priv->reg + TALITOS_RNGURCR_LO, TALITOS_RNGURCR_LO_SR);
637 while (!(in_be32(priv->reg + TALITOS_RNGUSR_LO) & TALITOS_RNGUSR_LO_RD)
638 && --timeout)
639 cpu_relax();
640 if (timeout == 0) {
641 dev_err(dev, "failed to reset rng hw\n");
642 return -ENODEV;
643 }
644
645 /* start generating */
646 setbits32(priv->reg + TALITOS_RNGUDSR_LO, 0);
647
648 return 0;
649}
650
651static int talitos_register_rng(struct device *dev)
652{
653 struct talitos_private *priv = dev_get_drvdata(dev);
654
655 priv->rng.name = dev_driver_string(dev),
656 priv->rng.init = talitos_rng_init,
657 priv->rng.data_present = talitos_rng_data_present,
658 priv->rng.data_read = talitos_rng_data_read,
659 priv->rng.priv = (unsigned long)dev;
660
661 return hwrng_register(&priv->rng);
662}
663
664static void talitos_unregister_rng(struct device *dev)
665{
666 struct talitos_private *priv = dev_get_drvdata(dev);
667
668 hwrng_unregister(&priv->rng);
669}
670
671/*
672 * crypto alg
673 */
674#define TALITOS_CRA_PRIORITY 3000
675#define TALITOS_MAX_KEY_SIZE 64
3952f17e 676#define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
70bcaca7 677
3952f17e 678#define MD5_DIGEST_SIZE 16
9c4a7965
KP		 679
680struct talitos_ctx {
681 struct device *dev;
682 __be32 desc_hdr_template;
683 u8 key[TALITOS_MAX_KEY_SIZE];
70bcaca7 684 u8 iv[TALITOS_MAX_IV_LENGTH];
9c4a7965
KP		 685 unsigned int keylen;
686 unsigned int enckeylen;
687 unsigned int authkeylen;
688 unsigned int authsize;
689};
690
56af8cd4
LN		 691static int aead_setauthsize(struct crypto_aead *authenc,
692 unsigned int authsize)
9c4a7965
KP		 693{
694 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
695
696 ctx->authsize = authsize;
697
698 return 0;
699}
700
56af8cd4
LN		 701static int aead_setkey(struct crypto_aead *authenc,
702 const u8 *key, unsigned int keylen)
9c4a7965
KP		 703{
704 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
705 struct rtattr *rta = (void *)key;
706 struct crypto_authenc_key_param *param;
707 unsigned int authkeylen;
708 unsigned int enckeylen;
709
710 if (!RTA_OK(rta, keylen))
711 goto badkey;
712
713 if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM)
714 goto badkey;
715
716 if (RTA_PAYLOAD(rta) < sizeof(*param))
717 goto badkey;
718
719 param = RTA_DATA(rta);
720 enckeylen = be32_to_cpu(param->enckeylen);
721
722 key += RTA_ALIGN(rta->rta_len);
723 keylen -= RTA_ALIGN(rta->rta_len);
724
725 if (keylen < enckeylen)
726 goto badkey;
727
728 authkeylen = keylen - enckeylen;
729
730 if (keylen > TALITOS_MAX_KEY_SIZE)
731 goto badkey;
732
733 memcpy(&ctx->key, key, keylen);
734
735 ctx->keylen = keylen;
736 ctx->enckeylen = enckeylen;
737 ctx->authkeylen = authkeylen;
738
739 return 0;
740
741badkey:
742 crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
743 return -EINVAL;
744}
745
746/*
56af8cd4 747 * talitos_edesc - s/w-extended descriptor
9c4a7965
KP		 748 * @src_nents: number of segments in input scatterlist
749 * @dst_nents: number of segments in output scatterlist
750 * @dma_len: length of dma mapped link_tbl space
751 * @dma_link_tbl: bus physical address of link_tbl
752 * @desc: h/w descriptor
753 * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1)
754 *
755 * if decrypting (with authcheck), or either one of src_nents or dst_nents
756 * is greater than 1, an integrity check value is concatenated to the end
757 * of link_tbl data
758 */
56af8cd4 759struct talitos_edesc {
9c4a7965
KP		 760 int src_nents;
761 int dst_nents;
4de9d0b5
LN		 762 int src_is_chained;
763 int dst_is_chained;
9c4a7965
KP		 764 int dma_len;
765 dma_addr_t dma_link_tbl;
766 struct talitos_desc desc;
767 struct talitos_ptr link_tbl[0];
768};
769
4de9d0b5
LN		 770static int talitos_map_sg(struct device *dev, struct scatterlist *sg,
771 unsigned int nents, enum dma_data_direction dir,
772 int chained)
773{
774 if (unlikely(chained))
775 while (sg) {
776 dma_map_sg(dev, sg, 1, dir);
777 sg = scatterwalk_sg_next(sg);
778 }
779 else
780 dma_map_sg(dev, sg, nents, dir);
781 return nents;
782}
783
784static void talitos_unmap_sg_chain(struct device *dev, struct scatterlist *sg,
785 enum dma_data_direction dir)
786{
787 while (sg) {
788 dma_unmap_sg(dev, sg, 1, dir);
789 sg = scatterwalk_sg_next(sg);
790 }
791}
792
793static void talitos_sg_unmap(struct device *dev,
794 struct talitos_edesc *edesc,
795 struct scatterlist *src,
796 struct scatterlist *dst)
797{
798 unsigned int src_nents = edesc->src_nents ? : 1;
799 unsigned int dst_nents = edesc->dst_nents ? : 1;
800
801 if (src != dst) {
802 if (edesc->src_is_chained)
803 talitos_unmap_sg_chain(dev, src, DMA_TO_DEVICE);
804 else
805 dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
806
807 if (edesc->dst_is_chained)
808 talitos_unmap_sg_chain(dev, dst, DMA_FROM_DEVICE);
809 else
810 dma_unmap_sg(dev, dst, dst_nents, DMA_FROM_DEVICE);
811 } else
812 if (edesc->src_is_chained)
813 talitos_unmap_sg_chain(dev, src, DMA_BIDIRECTIONAL);
814 else
815 dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
816}
817
9c4a7965 818static void ipsec_esp_unmap(struct device *dev,
56af8cd4 819 struct talitos_edesc *edesc,
9c4a7965
KP		 820 struct aead_request *areq)
821{
822 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE);
823 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE);
824 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
825 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE);
826
827 dma_unmap_sg(dev, areq->assoc, 1, DMA_TO_DEVICE);
828
4de9d0b5 829 talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
9c4a7965
KP		 830
831 if (edesc->dma_len)
832 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
833 DMA_BIDIRECTIONAL);
834}
835
836/*
837 * ipsec_esp descriptor callbacks
838 */
839static void ipsec_esp_encrypt_done(struct device *dev,
840 struct talitos_desc *desc, void *context,
841 int err)
842{
843 struct aead_request *areq = context;
9c4a7965
KP		 844 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
845 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
19bbbc63 846 struct talitos_edesc *edesc;
9c4a7965
KP		 847 struct scatterlist *sg;
848 void *icvdata;
849
19bbbc63
KP		 850 edesc = container_of(desc, struct talitos_edesc, desc);
851
9c4a7965
KP		 852 ipsec_esp_unmap(dev, edesc, areq);
853
854 /* copy the generated ICV to dst */
855 if (edesc->dma_len) {
856 icvdata = &edesc->link_tbl[edesc->src_nents +
f3c85bc1 857 edesc->dst_nents + 2];
9c4a7965
KP		 858 sg = sg_last(areq->dst, edesc->dst_nents);
859 memcpy((char *)sg_virt(sg) + sg->length - ctx->authsize,
860 icvdata, ctx->authsize);
861 }
862
863 kfree(edesc);
864
865 aead_request_complete(areq, err);
866}
867
fe5720e2 868static void ipsec_esp_decrypt_swauth_done(struct device *dev,
e938e465
KP		 869 struct talitos_desc *desc,
870 void *context, int err)
9c4a7965
KP		 871{
872 struct aead_request *req = context;
9c4a7965
KP		 873 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
874 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
19bbbc63 875 struct talitos_edesc *edesc;
9c4a7965
KP		 876 struct scatterlist *sg;
877 void *icvdata;
878
19bbbc63
KP		 879 edesc = container_of(desc, struct talitos_edesc, desc);
880
9c4a7965
KP		 881 ipsec_esp_unmap(dev, edesc, req);
882
883 if (!err) {
884 /* auth check */
885 if (edesc->dma_len)
886 icvdata = &edesc->link_tbl[edesc->src_nents +
f3c85bc1 887 edesc->dst_nents + 2];
9c4a7965
KP		 888 else
889 icvdata = &edesc->link_tbl[0];
890
891 sg = sg_last(req->dst, edesc->dst_nents ? : 1);
892 err = memcmp(icvdata, (char *)sg_virt(sg) + sg->length -
893 ctx->authsize, ctx->authsize) ? -EBADMSG : 0;
894 }
895
896 kfree(edesc);
897
898 aead_request_complete(req, err);
899}
900
fe5720e2 901static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
e938e465
KP		 902 struct talitos_desc *desc,
903 void *context, int err)
fe5720e2
KP		 904{
905 struct aead_request *req = context;
19bbbc63
KP		 906 struct talitos_edesc *edesc;
907
908 edesc = container_of(desc, struct talitos_edesc, desc);
fe5720e2
KP		 909
910 ipsec_esp_unmap(dev, edesc, req);
911
912 /* check ICV auth status */
e938e465
KP		 913 if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
914 DESC_HDR_LO_ICCR1_PASS))
915 err = -EBADMSG;
fe5720e2
KP		 916
917 kfree(edesc);
918
919 aead_request_complete(req, err);
920}
921
9c4a7965
KP		 922/*
923 * convert scatterlist to SEC h/w link table format
924 * stop at cryptlen bytes
925 */
70bcaca7 926static int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
9c4a7965
KP		 927 int cryptlen, struct talitos_ptr *link_tbl_ptr)
928{
70bcaca7
LN		 929 int n_sg = sg_count;
930
931 while (n_sg--) {
9c4a7965
KP		 932 link_tbl_ptr->ptr = cpu_to_be32(sg_dma_address(sg));
933 link_tbl_ptr->len = cpu_to_be16(sg_dma_len(sg));
934 link_tbl_ptr->j_extent = 0;
935 link_tbl_ptr++;
936 cryptlen -= sg_dma_len(sg);
4de9d0b5 937 sg = scatterwalk_sg_next(sg);
9c4a7965
KP		 938 }
939
70bcaca7 940 /* adjust (decrease) last one (or two) entry's len to cryptlen */
9c4a7965 941 link_tbl_ptr--;
c0e741d4 942 while (be16_to_cpu(link_tbl_ptr->len) <= (-cryptlen)) {
70bcaca7
LN		 943 /* Empty this entry, and move to previous one */
944 cryptlen += be16_to_cpu(link_tbl_ptr->len);
945 link_tbl_ptr->len = 0;
946 sg_count--;
947 link_tbl_ptr--;
948 }
9c4a7965
KP		 949 link_tbl_ptr->len = cpu_to_be16(be16_to_cpu(link_tbl_ptr->len)
950 + cryptlen);
951
952 /* tag end of link table */
953 link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
70bcaca7
LN		 954
955 return sg_count;
9c4a7965
KP		 956}
957
958/*
959 * fill in and submit ipsec_esp descriptor
960 */
56af8cd4 961static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
9c4a7965
KP		 962 u8 *giv, u64 seq,
963 void (*callback) (struct device *dev,
964 struct talitos_desc *desc,
965 void *context, int error))
966{
967 struct crypto_aead *aead = crypto_aead_reqtfm(areq);
968 struct talitos_ctx *ctx = crypto_aead_ctx(aead);
969 struct device *dev = ctx->dev;
970 struct talitos_desc *desc = &edesc->desc;
971 unsigned int cryptlen = areq->cryptlen;
972 unsigned int authsize = ctx->authsize;
e41256f1 973 unsigned int ivsize = crypto_aead_ivsize(aead);
fa86a267 974 int sg_count, ret;
fe5720e2 975 int sg_link_tbl_len;
9c4a7965
KP		 976
977 /* hmac key */
978 map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
979 0, DMA_TO_DEVICE);
980 /* hmac data */
e41256f1
KP		 981 map_single_talitos_ptr(dev, &desc->ptr[1], areq->assoclen + ivsize,
982 sg_virt(areq->assoc), 0, DMA_TO_DEVICE);
9c4a7965 983 /* cipher iv */
9c4a7965
KP		 984 map_single_talitos_ptr(dev, &desc->ptr[2], ivsize, giv ?: areq->iv, 0,
985 DMA_TO_DEVICE);
986
987 /* cipher key */
988 map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen,
989 (char *)&ctx->key + ctx->authkeylen, 0,
990 DMA_TO_DEVICE);
991
992 /*
993 * cipher in
994 * map and adjust cipher len to aead request cryptlen.
995 * extent is bytes of HMAC postpended to ciphertext,
996 * typically 12 for ipsec
997 */
998 desc->ptr[4].len = cpu_to_be16(cryptlen);
999 desc->ptr[4].j_extent = authsize;
1000
e938e465
KP		 1001 sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1002 (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1003 : DMA_TO_DEVICE,
4de9d0b5 1004 edesc->src_is_chained);
9c4a7965
KP		 1005
1006 if (sg_count == 1) {
1007 desc->ptr[4].ptr = cpu_to_be32(sg_dma_address(areq->src));
1008 } else {
fe5720e2
KP		 1009 sg_link_tbl_len = cryptlen;
1010
962a9c99 1011 if (edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV)
fe5720e2 1012 sg_link_tbl_len = cryptlen + authsize;
e938e465 1013
fe5720e2 1014 sg_count = sg_to_link_tbl(areq->src, sg_count, sg_link_tbl_len,
70bcaca7
LN		 1015 &edesc->link_tbl[0]);
1016 if (sg_count > 1) {
1017 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
1018 desc->ptr[4].ptr = cpu_to_be32(edesc->dma_link_tbl);
e938e465
KP		 1019 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1020 edesc->dma_len,
1021 DMA_BIDIRECTIONAL);
70bcaca7
LN		 1022 } else {
1023 /* Only one segment now, so no link tbl needed */
e938e465
KP		 1024 desc->ptr[4].ptr = cpu_to_be32(sg_dma_address(areq->
1025 src));
70bcaca7 1026 }
9c4a7965
KP		 1027 }
1028
1029 /* cipher out */
1030 desc->ptr[5].len = cpu_to_be16(cryptlen);
1031 desc->ptr[5].j_extent = authsize;
1032
e938e465 1033 if (areq->src != areq->dst)
4de9d0b5
LN		 1034 sg_count = talitos_map_sg(dev, areq->dst,
1035 edesc->dst_nents ? : 1,
1036 DMA_FROM_DEVICE,
1037 edesc->dst_is_chained);
9c4a7965
KP		 1038
1039 if (sg_count == 1) {
1040 desc->ptr[5].ptr = cpu_to_be32(sg_dma_address(areq->dst));
1041 } else {
1042 struct talitos_ptr *link_tbl_ptr =
f3c85bc1 1043 &edesc->link_tbl[edesc->src_nents + 1];
9c4a7965
KP		 1044
1045 desc->ptr[5].ptr = cpu_to_be32((struct talitos_ptr *)
1046 edesc->dma_link_tbl +
f3c85bc1 1047 edesc->src_nents + 1);
fe5720e2
KP		 1048 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1049 link_tbl_ptr);
1050
f3c85bc1 1051 /* Add an entry to the link table for ICV data */
9c4a7965 1052 link_tbl_ptr += sg_count - 1;
9c4a7965 1053 link_tbl_ptr->j_extent = 0;
f3c85bc1 1054 sg_count++;
9c4a7965
KP		 1055 link_tbl_ptr++;
1056 link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
1057 link_tbl_ptr->len = cpu_to_be16(authsize);
1058
1059 /* icv data follows link tables */
1060 link_tbl_ptr->ptr = cpu_to_be32((struct talitos_ptr *)
1061 edesc->dma_link_tbl +
1062 edesc->src_nents +
f3c85bc1 1063 edesc->dst_nents + 2);
9c4a7965
KP		 1064
1065 desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
1066 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1067 edesc->dma_len, DMA_BIDIRECTIONAL);
1068 }
1069
1070 /* iv out */
1071 map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, 0,
1072 DMA_FROM_DEVICE);
1073
fa86a267
KP		 1074 ret = talitos_submit(dev, desc, callback, areq);
1075 if (ret != -EINPROGRESS) {
1076 ipsec_esp_unmap(dev, edesc, areq);
1077 kfree(edesc);
1078 }
1079 return ret;
9c4a7965
KP		 1080}
1081
9c4a7965
KP		 1082/*
1083 * derive number of elements in scatterlist
1084 */
4de9d0b5 1085static int sg_count(struct scatterlist *sg_list, int nbytes, int *chained)
9c4a7965
KP		 1086{
1087 struct scatterlist *sg = sg_list;
1088 int sg_nents = 0;
1089
4de9d0b5
LN		 1090 *chained = 0;
1091 while (nbytes > 0) {
9c4a7965
KP		 1092 sg_nents++;
1093 nbytes -= sg->length;
4de9d0b5
LN		 1094 if (!sg_is_last(sg) && (sg + 1)->length == 0)
1095 *chained = 1;
1096 sg = scatterwalk_sg_next(sg);
9c4a7965
KP		 1097 }
1098
1099 return sg_nents;
1100}
1101
1102/*
56af8cd4 1103 * allocate and map the extended descriptor
9c4a7965 1104 */
4de9d0b5
LN		 1105static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
1106 struct scatterlist *src,
1107 struct scatterlist *dst,
1108 unsigned int cryptlen,
1109 unsigned int authsize,
1110 int icv_stashing,
1111 u32 cryptoflags)
9c4a7965 1112{
56af8cd4 1113 struct talitos_edesc *edesc;
9c4a7965 1114 int src_nents, dst_nents, alloc_len, dma_len;
4de9d0b5
LN		 1115 int src_chained, dst_chained = 0;
1116 gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
586725f8 1117 GFP_ATOMIC;
9c4a7965 1118
4de9d0b5
LN		 1119 if (cryptlen + authsize > TALITOS_MAX_DATA_LEN) {
1120 dev_err(dev, "length exceeds h/w max limit\n");
9c4a7965
KP		 1121 return ERR_PTR(-EINVAL);
1122 }
1123
4de9d0b5 1124 src_nents = sg_count(src, cryptlen + authsize, &src_chained);
9c4a7965
KP		 1125 src_nents = (src_nents == 1) ? 0 : src_nents;
1126
4de9d0b5 1127 if (dst == src) {
9c4a7965
KP		 1128 dst_nents = src_nents;
1129 } else {
4de9d0b5 1130 dst_nents = sg_count(dst, cryptlen + authsize, &dst_chained);
695ad589 1131 dst_nents = (dst_nents == 1) ? 0 : dst_nents;
9c4a7965
KP		 1132 }
1133
1134 /*
1135 * allocate space for base edesc plus the link tables,
f3c85bc1 1136 * allowing for two separate entries for ICV and generated ICV (+ 2),
9c4a7965
KP		 1137 * and the ICV data itself
1138 */
56af8cd4 1139 alloc_len = sizeof(struct talitos_edesc);
9c4a7965 1140 if (src_nents || dst_nents) {
f3c85bc1 1141 dma_len = (src_nents + dst_nents + 2) *
4de9d0b5 1142 sizeof(struct talitos_ptr) + authsize;
9c4a7965
KP		 1143 alloc_len += dma_len;
1144 } else {
1145 dma_len = 0;
4de9d0b5 1146 alloc_len += icv_stashing ? authsize : 0;
9c4a7965
KP		 1147 }
1148
586725f8 1149 edesc = kmalloc(alloc_len, GFP_DMA | flags);
9c4a7965 1150 if (!edesc) {
4de9d0b5 1151 dev_err(dev, "could not allocate edescriptor\n");
9c4a7965
KP		 1152 return ERR_PTR(-ENOMEM);
1153 }
1154
1155 edesc->src_nents = src_nents;
1156 edesc->dst_nents = dst_nents;
4de9d0b5
LN		 1157 edesc->src_is_chained = src_chained;
1158 edesc->dst_is_chained = dst_chained;
9c4a7965 1159 edesc->dma_len = dma_len;
4de9d0b5 1160 edesc->dma_link_tbl = dma_map_single(dev, &edesc->link_tbl[0],
9c4a7965
KP		 1161 edesc->dma_len, DMA_BIDIRECTIONAL);
1162
1163 return edesc;
1164}
1165
4de9d0b5
LN		 1166static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq,
1167 int icv_stashing)
1168{
1169 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1170 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1171
1172 return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst,
1173 areq->cryptlen, ctx->authsize, icv_stashing,
1174 areq->base.flags);
1175}
1176
56af8cd4 1177static int aead_encrypt(struct aead_request *req)
9c4a7965
KP		 1178{
1179 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1180 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
56af8cd4 1181 struct talitos_edesc *edesc;
9c4a7965
KP		 1182
1183 /* allocate extended descriptor */
4de9d0b5 1184 edesc = aead_edesc_alloc(req, 0);
9c4a7965
KP		 1185 if (IS_ERR(edesc))
1186 return PTR_ERR(edesc);
1187
1188 /* set encrypt */
70bcaca7 1189 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
9c4a7965
KP		 1190
1191 return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_encrypt_done);
1192}
1193
56af8cd4 1194static int aead_decrypt(struct aead_request *req)
9c4a7965
KP		 1195{
1196 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1197 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1198 unsigned int authsize = ctx->authsize;
fe5720e2 1199 struct talitos_private *priv = dev_get_drvdata(ctx->dev);
56af8cd4 1200 struct talitos_edesc *edesc;
9c4a7965
KP		 1201 struct scatterlist *sg;
1202 void *icvdata;
1203
1204 req->cryptlen -= authsize;
1205
1206 /* allocate extended descriptor */
4de9d0b5 1207 edesc = aead_edesc_alloc(req, 1);
9c4a7965
KP		 1208 if (IS_ERR(edesc))
1209 return PTR_ERR(edesc);
1210
fe5720e2 1211 if ((priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
e938e465
KP		 1212 ((!edesc->src_nents && !edesc->dst_nents) ||
1213 priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
9c4a7965 1214
fe5720e2 1215 /* decrypt and check the ICV */
e938e465
KP		 1216 edesc->desc.hdr = ctx->desc_hdr_template |
1217 DESC_HDR_DIR_INBOUND |
fe5720e2 1218 DESC_HDR_MODE1_MDEU_CICV;
9c4a7965 1219
fe5720e2
KP		 1220 /* reset integrity check result bits */
1221 edesc->desc.hdr_lo = 0;
9c4a7965 1222
e938e465
KP		 1223 return ipsec_esp(edesc, req, NULL, 0,
1224 ipsec_esp_decrypt_hwauth_done);
fe5720e2 1225
e938e465 1226 }
fe5720e2 1227
e938e465
KP		 1228 /* Have to check the ICV with software */
1229 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
fe5720e2 1230
e938e465
KP		 1231 /* stash incoming ICV for later cmp with ICV generated by the h/w */
1232 if (edesc->dma_len)
1233 icvdata = &edesc->link_tbl[edesc->src_nents +
1234 edesc->dst_nents + 2];
1235 else
1236 icvdata = &edesc->link_tbl[0];
fe5720e2 1237
e938e465 1238 sg = sg_last(req->src, edesc->src_nents ? : 1);
fe5720e2 1239
e938e465
KP		 1240 memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize,
1241 ctx->authsize);
fe5720e2 1242
e938e465 1243 return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_decrypt_swauth_done);
9c4a7965
KP		 1244}
1245
56af8cd4 1246static int aead_givencrypt(struct aead_givcrypt_request *req)
9c4a7965
KP		 1247{
1248 struct aead_request *areq = &req->areq;
1249 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1250 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
56af8cd4 1251 struct talitos_edesc *edesc;
9c4a7965
KP		 1252
1253 /* allocate extended descriptor */
4de9d0b5 1254 edesc = aead_edesc_alloc(areq, 0);
9c4a7965
KP		 1255 if (IS_ERR(edesc))
1256 return PTR_ERR(edesc);
1257
1258 /* set encrypt */
70bcaca7 1259 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
9c4a7965
KP		 1260
1261 memcpy(req->giv, ctx->iv, crypto_aead_ivsize(authenc));
ba95487d
KP		 1262 /* avoid consecutive packets going out with same IV */
1263 *(__be64 *)req->giv ^= cpu_to_be64(req->seq);
9c4a7965
KP		 1264
1265 return ipsec_esp(edesc, areq, req->giv, req->seq,
1266 ipsec_esp_encrypt_done);
1267}
1268
4de9d0b5
LN		 1269static int ablkcipher_setkey(struct crypto_ablkcipher *cipher,
1270 const u8 *key, unsigned int keylen)
1271{
1272 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1273 struct ablkcipher_alg *alg = crypto_ablkcipher_alg(cipher);
1274
1275 if (keylen > TALITOS_MAX_KEY_SIZE)
1276 goto badkey;
1277
1278 if (keylen < alg->min_keysize || keylen > alg->max_keysize)
1279 goto badkey;
1280
1281 memcpy(&ctx->key, key, keylen);
1282 ctx->keylen = keylen;
1283
1284 return 0;
1285
1286badkey:
1287 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
1288 return -EINVAL;
1289}
1290
1291static void common_nonsnoop_unmap(struct device *dev,
1292 struct talitos_edesc *edesc,
1293 struct ablkcipher_request *areq)
1294{
1295 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1296 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
1297 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
1298
1299 talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
1300
1301 if (edesc->dma_len)
1302 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1303 DMA_BIDIRECTIONAL);
1304}
1305
1306static void ablkcipher_done(struct device *dev,
1307 struct talitos_desc *desc, void *context,
1308 int err)
1309{
1310 struct ablkcipher_request *areq = context;
19bbbc63
KP		 1311 struct talitos_edesc *edesc;
1312
1313 edesc = container_of(desc, struct talitos_edesc, desc);
4de9d0b5
LN		 1314
1315 common_nonsnoop_unmap(dev, edesc, areq);
1316
1317 kfree(edesc);
1318
1319 areq->base.complete(&areq->base, err);
1320}
1321
1322static int common_nonsnoop(struct talitos_edesc *edesc,
1323 struct ablkcipher_request *areq,
1324 u8 *giv,
1325 void (*callback) (struct device *dev,
1326 struct talitos_desc *desc,
1327 void *context, int error))
1328{
1329 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1330 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1331 struct device *dev = ctx->dev;
1332 struct talitos_desc *desc = &edesc->desc;
1333 unsigned int cryptlen = areq->nbytes;
1334 unsigned int ivsize;
1335 int sg_count, ret;
1336
1337 /* first DWORD empty */
1338 desc->ptr[0].len = 0;
1339 desc->ptr[0].ptr = 0;
1340 desc->ptr[0].j_extent = 0;
1341
1342 /* cipher iv */
1343 ivsize = crypto_ablkcipher_ivsize(cipher);
1344 map_single_talitos_ptr(dev, &desc->ptr[1], ivsize, giv ?: areq->info, 0,
1345 DMA_TO_DEVICE);
1346
1347 /* cipher key */
1348 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1349 (char *)&ctx->key, 0, DMA_TO_DEVICE);
1350
1351 /*
1352 * cipher in
1353 */
1354 desc->ptr[3].len = cpu_to_be16(cryptlen);
1355 desc->ptr[3].j_extent = 0;
1356
1357 sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1358 (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1359 : DMA_TO_DEVICE,
1360 edesc->src_is_chained);
1361
1362 if (sg_count == 1) {
1363 desc->ptr[3].ptr = cpu_to_be32(sg_dma_address(areq->src));
1364 } else {
1365 sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
1366 &edesc->link_tbl[0]);
1367 if (sg_count > 1) {
1368 desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1369 desc->ptr[3].ptr = cpu_to_be32(edesc->dma_link_tbl);
e938e465
KP		 1370 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1371 edesc->dma_len,
1372 DMA_BIDIRECTIONAL);
4de9d0b5
LN		 1373 } else {
1374 /* Only one segment now, so no link tbl needed */
e938e465
KP		 1375 desc->ptr[3].ptr = cpu_to_be32(sg_dma_address(areq->
1376 src));
4de9d0b5
LN		 1377 }
1378 }
1379
1380 /* cipher out */
1381 desc->ptr[4].len = cpu_to_be16(cryptlen);
1382 desc->ptr[4].j_extent = 0;
1383
1384 if (areq->src != areq->dst)
1385 sg_count = talitos_map_sg(dev, areq->dst,
1386 edesc->dst_nents ? : 1,
1387 DMA_FROM_DEVICE,
1388 edesc->dst_is_chained);
1389
1390 if (sg_count == 1) {
1391 desc->ptr[4].ptr = cpu_to_be32(sg_dma_address(areq->dst));
1392 } else {
1393 struct talitos_ptr *link_tbl_ptr =
1394 &edesc->link_tbl[edesc->src_nents + 1];
1395
1396 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
1397 desc->ptr[4].ptr = cpu_to_be32((struct talitos_ptr *)
1398 edesc->dma_link_tbl +
1399 edesc->src_nents + 1);
1400 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1401 link_tbl_ptr);
1402 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1403 edesc->dma_len, DMA_BIDIRECTIONAL);
1404 }
1405
1406 /* iv out */
1407 map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv, 0,
1408 DMA_FROM_DEVICE);
1409
1410 /* last DWORD empty */
1411 desc->ptr[6].len = 0;
1412 desc->ptr[6].ptr = 0;
1413 desc->ptr[6].j_extent = 0;
1414
1415 ret = talitos_submit(dev, desc, callback, areq);
1416 if (ret != -EINPROGRESS) {
1417 common_nonsnoop_unmap(dev, edesc, areq);
1418 kfree(edesc);
1419 }
1420 return ret;
1421}
1422
e938e465
KP		 1423static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request *
1424 areq)
4de9d0b5
LN		 1425{
1426 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1427 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1428
1429 return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst, areq->nbytes,
1430 0, 0, areq->base.flags);
1431}
1432
1433static int ablkcipher_encrypt(struct ablkcipher_request *areq)
1434{
1435 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1436 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1437 struct talitos_edesc *edesc;
1438
1439 /* allocate extended descriptor */
1440 edesc = ablkcipher_edesc_alloc(areq);
1441 if (IS_ERR(edesc))
1442 return PTR_ERR(edesc);
1443
1444 /* set encrypt */
1445 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1446
1447 return common_nonsnoop(edesc, areq, NULL, ablkcipher_done);
1448}
1449
1450static int ablkcipher_decrypt(struct ablkcipher_request *areq)
1451{
1452 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1453 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1454 struct talitos_edesc *edesc;
1455
1456 /* allocate extended descriptor */
1457 edesc = ablkcipher_edesc_alloc(areq);
1458 if (IS_ERR(edesc))
1459 return PTR_ERR(edesc);
1460
1461 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1462
1463 return common_nonsnoop(edesc, areq, NULL, ablkcipher_done);
1464}
1465
9c4a7965 1466struct talitos_alg_template {
56af8cd4 1467 struct crypto_alg alg;
9c4a7965
KP		 1468 __be32 desc_hdr_template;
1469};
1470
1471static struct talitos_alg_template driver_algs[] = {
56af8cd4 1472 /* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
9c4a7965 1473 {
56af8cd4
LN		 1474 .alg = {
1475 .cra_name = "authenc(hmac(sha1),cbc(aes))",
1476 .cra_driver_name = "authenc-hmac-sha1-cbc-aes-talitos",
1477 .cra_blocksize = AES_BLOCK_SIZE,
1478 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1479 .cra_type = &crypto_aead_type,
1480 .cra_aead = {
1481 .setkey = aead_setkey,
1482 .setauthsize = aead_setauthsize,
1483 .encrypt = aead_encrypt,
1484 .decrypt = aead_decrypt,
1485 .givencrypt = aead_givencrypt,
1486 .geniv = "<built-in>",
1487 .ivsize = AES_BLOCK_SIZE,
1488 .maxauthsize = SHA1_DIGEST_SIZE,
1489 }
1490 },
9c4a7965
KP		 1491 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1492 DESC_HDR_SEL0_AESU |
1493 DESC_HDR_MODE0_AESU_CBC |
1494 DESC_HDR_SEL1_MDEUA |
1495 DESC_HDR_MODE1_MDEU_INIT |
1496 DESC_HDR_MODE1_MDEU_PAD |
1497 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
70bcaca7
LN		 1498 },
1499 {
56af8cd4
LN		 1500 .alg = {
1501 .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
1502 .cra_driver_name = "authenc-hmac-sha1-cbc-3des-talitos",
1503 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1504 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1505 .cra_type = &crypto_aead_type,
1506 .cra_aead = {
1507 .setkey = aead_setkey,
1508 .setauthsize = aead_setauthsize,
1509 .encrypt = aead_encrypt,
1510 .decrypt = aead_decrypt,
1511 .givencrypt = aead_givencrypt,
1512 .geniv = "<built-in>",
1513 .ivsize = DES3_EDE_BLOCK_SIZE,
1514 .maxauthsize = SHA1_DIGEST_SIZE,
1515 }
1516 },
70bcaca7
LN		 1517 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1518 DESC_HDR_SEL0_DEU |
1519 DESC_HDR_MODE0_DEU_CBC |
1520 DESC_HDR_MODE0_DEU_3DES |
1521 DESC_HDR_SEL1_MDEUA |
1522 DESC_HDR_MODE1_MDEU_INIT |
1523 DESC_HDR_MODE1_MDEU_PAD |
1524 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
3952f17e
LN		 1525 },
1526 {
56af8cd4
LN		 1527 .alg = {
1528 .cra_name = "authenc(hmac(sha256),cbc(aes))",
1529 .cra_driver_name = "authenc-hmac-sha256-cbc-aes-talitos",
1530 .cra_blocksize = AES_BLOCK_SIZE,
1531 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1532 .cra_type = &crypto_aead_type,
1533 .cra_aead = {
1534 .setkey = aead_setkey,
1535 .setauthsize = aead_setauthsize,
1536 .encrypt = aead_encrypt,
1537 .decrypt = aead_decrypt,
1538 .givencrypt = aead_givencrypt,
1539 .geniv = "<built-in>",
1540 .ivsize = AES_BLOCK_SIZE,
1541 .maxauthsize = SHA256_DIGEST_SIZE,
1542 }
1543 },
3952f17e
LN		 1544 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1545 DESC_HDR_SEL0_AESU |
1546 DESC_HDR_MODE0_AESU_CBC |
1547 DESC_HDR_SEL1_MDEUA |
1548 DESC_HDR_MODE1_MDEU_INIT |
1549 DESC_HDR_MODE1_MDEU_PAD |
1550 DESC_HDR_MODE1_MDEU_SHA256_HMAC,
1551 },
1552 {
56af8cd4
LN		 1553 .alg = {
1554 .cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
1555 .cra_driver_name = "authenc-hmac-sha256-cbc-3des-talitos",
1556 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1557 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1558 .cra_type = &crypto_aead_type,
1559 .cra_aead = {
1560 .setkey = aead_setkey,
1561 .setauthsize = aead_setauthsize,
1562 .encrypt = aead_encrypt,
1563 .decrypt = aead_decrypt,
1564 .givencrypt = aead_givencrypt,
1565 .geniv = "<built-in>",
1566 .ivsize = DES3_EDE_BLOCK_SIZE,
1567 .maxauthsize = SHA256_DIGEST_SIZE,
1568 }
1569 },
3952f17e
LN		 1570 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1571 DESC_HDR_SEL0_DEU |
1572 DESC_HDR_MODE0_DEU_CBC |
1573 DESC_HDR_MODE0_DEU_3DES |
1574 DESC_HDR_SEL1_MDEUA |
1575 DESC_HDR_MODE1_MDEU_INIT |
1576 DESC_HDR_MODE1_MDEU_PAD |
1577 DESC_HDR_MODE1_MDEU_SHA256_HMAC,
1578 },
1579 {
56af8cd4
LN		 1580 .alg = {
1581 .cra_name = "authenc(hmac(md5),cbc(aes))",
1582 .cra_driver_name = "authenc-hmac-md5-cbc-aes-talitos",
1583 .cra_blocksize = AES_BLOCK_SIZE,
1584 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1585 .cra_type = &crypto_aead_type,
1586 .cra_aead = {
1587 .setkey = aead_setkey,
1588 .setauthsize = aead_setauthsize,
1589 .encrypt = aead_encrypt,
1590 .decrypt = aead_decrypt,
1591 .givencrypt = aead_givencrypt,
1592 .geniv = "<built-in>",
1593 .ivsize = AES_BLOCK_SIZE,
1594 .maxauthsize = MD5_DIGEST_SIZE,
1595 }
1596 },
3952f17e
LN		 1597 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1598 DESC_HDR_SEL0_AESU |
1599 DESC_HDR_MODE0_AESU_CBC |
1600 DESC_HDR_SEL1_MDEUA |
1601 DESC_HDR_MODE1_MDEU_INIT |
1602 DESC_HDR_MODE1_MDEU_PAD |
1603 DESC_HDR_MODE1_MDEU_MD5_HMAC,
1604 },
1605 {
56af8cd4
LN		 1606 .alg = {
1607 .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
1608 .cra_driver_name = "authenc-hmac-md5-cbc-3des-talitos",
1609 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1610 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1611 .cra_type = &crypto_aead_type,
1612 .cra_aead = {
1613 .setkey = aead_setkey,
1614 .setauthsize = aead_setauthsize,
1615 .encrypt = aead_encrypt,
1616 .decrypt = aead_decrypt,
1617 .givencrypt = aead_givencrypt,
1618 .geniv = "<built-in>",
1619 .ivsize = DES3_EDE_BLOCK_SIZE,
1620 .maxauthsize = MD5_DIGEST_SIZE,
1621 }
1622 },
3952f17e
LN		 1623 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1624 DESC_HDR_SEL0_DEU |
1625 DESC_HDR_MODE0_DEU_CBC |
1626 DESC_HDR_MODE0_DEU_3DES |
1627 DESC_HDR_SEL1_MDEUA |
1628 DESC_HDR_MODE1_MDEU_INIT |
1629 DESC_HDR_MODE1_MDEU_PAD |
1630 DESC_HDR_MODE1_MDEU_MD5_HMAC,
4de9d0b5
LN		 1631 },
1632 /* ABLKCIPHER algorithms. */
1633 {
1634 .alg = {
1635 .cra_name = "cbc(aes)",
1636 .cra_driver_name = "cbc-aes-talitos",
1637 .cra_blocksize = AES_BLOCK_SIZE,
1638 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1639 CRYPTO_ALG_ASYNC,
1640 .cra_type = &crypto_ablkcipher_type,
1641 .cra_ablkcipher = {
1642 .setkey = ablkcipher_setkey,
1643 .encrypt = ablkcipher_encrypt,
1644 .decrypt = ablkcipher_decrypt,
1645 .geniv = "eseqiv",
1646 .min_keysize = AES_MIN_KEY_SIZE,
1647 .max_keysize = AES_MAX_KEY_SIZE,
1648 .ivsize = AES_BLOCK_SIZE,
1649 }
1650 },
1651 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
1652 DESC_HDR_SEL0_AESU |
1653 DESC_HDR_MODE0_AESU_CBC,
1654 },
1655 {
1656 .alg = {
1657 .cra_name = "cbc(des3_ede)",
1658 .cra_driver_name = "cbc-3des-talitos",
1659 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1660 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1661 CRYPTO_ALG_ASYNC,
1662 .cra_type = &crypto_ablkcipher_type,
1663 .cra_ablkcipher = {
1664 .setkey = ablkcipher_setkey,
1665 .encrypt = ablkcipher_encrypt,
1666 .decrypt = ablkcipher_decrypt,
1667 .geniv = "eseqiv",
1668 .min_keysize = DES3_EDE_KEY_SIZE,
1669 .max_keysize = DES3_EDE_KEY_SIZE,
1670 .ivsize = DES3_EDE_BLOCK_SIZE,
1671 }
1672 },
1673 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
1674 DESC_HDR_SEL0_DEU |
1675 DESC_HDR_MODE0_DEU_CBC |
1676 DESC_HDR_MODE0_DEU_3DES,
9c4a7965
KP		 1677 }
1678};
1679
1680struct talitos_crypto_alg {
1681 struct list_head entry;
1682 struct device *dev;
1683 __be32 desc_hdr_template;
1684 struct crypto_alg crypto_alg;
1685};
1686
1687static int talitos_cra_init(struct crypto_tfm *tfm)
1688{
1689 struct crypto_alg *alg = tfm->__crt_alg;
19bbbc63 1690 struct talitos_crypto_alg *talitos_alg;
9c4a7965
KP		 1691 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
1692
19bbbc63
KP		 1693 talitos_alg = container_of(alg, struct talitos_crypto_alg, crypto_alg);
1694
9c4a7965
KP		 1695 /* update context with ptr to dev */
1696 ctx->dev = talitos_alg->dev;
19bbbc63 1697
9c4a7965
KP		 1698 /* copy descriptor header template value */
1699 ctx->desc_hdr_template = talitos_alg->desc_hdr_template;
1700
1701 /* random first IV */
70bcaca7 1702 get_random_bytes(ctx->iv, TALITOS_MAX_IV_LENGTH);
9c4a7965
KP		 1703
1704 return 0;
1705}
1706
1707/*
1708 * given the alg's descriptor header template, determine whether descriptor
1709 * type and primary/secondary execution units required match the hw
1710 * capabilities description provided in the device tree node.
1711 */
1712static int hw_supports(struct device *dev, __be32 desc_hdr_template)
1713{
1714 struct talitos_private *priv = dev_get_drvdata(dev);
1715 int ret;
1716
1717 ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
1718 (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
1719
1720 if (SECONDARY_EU(desc_hdr_template))
1721 ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
1722 & priv->exec_units);
1723
1724 return ret;
1725}
1726
596f1034 1727static int talitos_remove(struct of_device *ofdev)
9c4a7965
KP		 1728{
1729 struct device *dev = &ofdev->dev;
1730 struct talitos_private *priv = dev_get_drvdata(dev);
1731 struct talitos_crypto_alg *t_alg, *n;
1732 int i;
1733
1734 list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
1735 crypto_unregister_alg(&t_alg->crypto_alg);
1736 list_del(&t_alg->entry);
1737 kfree(t_alg);
1738 }
1739
1740 if (hw_supports(dev, DESC_HDR_SEL0_RNG))
1741 talitos_unregister_rng(dev);
1742
ec6644d6 1743 kfree(priv->submit_count);
9c4a7965
KP		 1744 kfree(priv->tail);
1745 kfree(priv->head);
1746
1747 if (priv->fifo)
1748 for (i = 0; i < priv->num_channels; i++)
1749 kfree(priv->fifo[i]);
1750
1751 kfree(priv->fifo);
1752 kfree(priv->head_lock);
1753 kfree(priv->tail_lock);
1754
1755 if (priv->irq != NO_IRQ) {
1756 free_irq(priv->irq, dev);
1757 irq_dispose_mapping(priv->irq);
1758 }
1759
1760 tasklet_kill(&priv->done_task);
9c4a7965
KP		 1761
1762 iounmap(priv->reg);
1763
1764 dev_set_drvdata(dev, NULL);
1765
1766 kfree(priv);
1767
1768 return 0;
1769}
1770
1771static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
1772 struct talitos_alg_template
1773 *template)
1774{
1775 struct talitos_crypto_alg *t_alg;
1776 struct crypto_alg *alg;
1777
1778 t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL);
1779 if (!t_alg)
1780 return ERR_PTR(-ENOMEM);
1781
1782 alg = &t_alg->crypto_alg;
56af8cd4 1783 *alg = template->alg;
9c4a7965 1784
9c4a7965
KP		 1785 alg->cra_module = THIS_MODULE;
1786 alg->cra_init = talitos_cra_init;
1787 alg->cra_priority = TALITOS_CRA_PRIORITY;
9c4a7965 1788 alg->cra_alignmask = 0;
9c4a7965 1789 alg->cra_ctxsize = sizeof(struct talitos_ctx);
9c4a7965
KP		 1790
1791 t_alg->desc_hdr_template = template->desc_hdr_template;
1792 t_alg->dev = dev;
1793
1794 return t_alg;
1795}
1796
1797static int talitos_probe(struct of_device *ofdev,
1798 const struct of_device_id *match)
1799{
1800 struct device *dev = &ofdev->dev;
1801 struct device_node *np = ofdev->node;
1802 struct talitos_private *priv;
1803 const unsigned int *prop;
1804 int i, err;
1805
1806 priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL);
1807 if (!priv)
1808 return -ENOMEM;
1809
1810 dev_set_drvdata(dev, priv);
1811
1812 priv->ofdev = ofdev;
1813
1814 tasklet_init(&priv->done_task, talitos_done, (unsigned long)dev);
9c4a7965 1815
fe5720e2
KP		 1816 INIT_LIST_HEAD(&priv->alg_list);
1817
9c4a7965
KP		 1818 priv->irq = irq_of_parse_and_map(np, 0);
1819
1820 if (priv->irq == NO_IRQ) {
1821 dev_err(dev, "failed to map irq\n");
1822 err = -EINVAL;
1823 goto err_out;
1824 }
1825
1826 /* get the irq line */
1827 err = request_irq(priv->irq, talitos_interrupt, 0,
1828 dev_driver_string(dev), dev);
1829 if (err) {
1830 dev_err(dev, "failed to request irq %d\n", priv->irq);
1831 irq_dispose_mapping(priv->irq);
1832 priv->irq = NO_IRQ;
1833 goto err_out;
1834 }
1835
1836 priv->reg = of_iomap(np, 0);
1837 if (!priv->reg) {
1838 dev_err(dev, "failed to of_iomap\n");
1839 err = -ENOMEM;
1840 goto err_out;
1841 }
1842
1843 /* get SEC version capabilities from device tree */
1844 prop = of_get_property(np, "fsl,num-channels", NULL);
1845 if (prop)
1846 priv->num_channels = *prop;
1847
1848 prop = of_get_property(np, "fsl,channel-fifo-len", NULL);
1849 if (prop)
1850 priv->chfifo_len = *prop;
1851
1852 prop = of_get_property(np, "fsl,exec-units-mask", NULL);
1853 if (prop)
1854 priv->exec_units = *prop;
1855
1856 prop = of_get_property(np, "fsl,descriptor-types-mask", NULL);
1857 if (prop)
1858 priv->desc_types = *prop;
1859
1860 if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
1861 !priv->exec_units || !priv->desc_types) {
1862 dev_err(dev, "invalid property data in device tree node\n");
1863 err = -EINVAL;
1864 goto err_out;
1865 }
1866
f3c85bc1
LN		 1867 if (of_device_is_compatible(np, "fsl,sec3.0"))
1868 priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
1869
fe5720e2
KP		 1870 if (of_device_is_compatible(np, "fsl,sec2.1"))
1871 priv->features |= TALITOS_FTR_HW_AUTH_CHECK;
1872
9c4a7965
KP		 1873 priv->head_lock = kmalloc(sizeof(spinlock_t) * priv->num_channels,
1874 GFP_KERNEL);
1875 priv->tail_lock = kmalloc(sizeof(spinlock_t) * priv->num_channels,
1876 GFP_KERNEL);
1877 if (!priv->head_lock || !priv->tail_lock) {
1878 dev_err(dev, "failed to allocate fifo locks\n");
1879 err = -ENOMEM;
1880 goto err_out;
1881 }
1882
1883 for (i = 0; i < priv->num_channels; i++) {
1884 spin_lock_init(&priv->head_lock[i]);
1885 spin_lock_init(&priv->tail_lock[i]);
1886 }
1887
1888 priv->fifo = kmalloc(sizeof(struct talitos_request *) *
1889 priv->num_channels, GFP_KERNEL);
1890 if (!priv->fifo) {
1891 dev_err(dev, "failed to allocate request fifo\n");
1892 err = -ENOMEM;
1893 goto err_out;
1894 }
1895
1896 priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
1897
1898 for (i = 0; i < priv->num_channels; i++) {
1899 priv->fifo[i] = kzalloc(sizeof(struct talitos_request) *
1900 priv->fifo_len, GFP_KERNEL);
1901 if (!priv->fifo[i]) {
1902 dev_err(dev, "failed to allocate request fifo %d\n", i);
1903 err = -ENOMEM;
1904 goto err_out;
1905 }
1906 }
1907
586725f8 1908 priv->submit_count = kmalloc(sizeof(atomic_t) * priv->num_channels,
ec6644d6
KP		 1909 GFP_KERNEL);
1910 if (!priv->submit_count) {
1911 dev_err(dev, "failed to allocate fifo submit count space\n");
1912 err = -ENOMEM;
1913 goto err_out;
1914 }
1915 for (i = 0; i < priv->num_channels; i++)
4b24ea97 1916 atomic_set(&priv->submit_count[i], -(priv->chfifo_len - 1));
ec6644d6 1917
9c4a7965
KP		 1918 priv->head = kzalloc(sizeof(int) * priv->num_channels, GFP_KERNEL);
1919 priv->tail = kzalloc(sizeof(int) * priv->num_channels, GFP_KERNEL);
1920 if (!priv->head || !priv->tail) {
1921 dev_err(dev, "failed to allocate request index space\n");
1922 err = -ENOMEM;
1923 goto err_out;
1924 }
1925
1926 /* reset and initialize the h/w */
1927 err = init_device(dev);
1928 if (err) {
1929 dev_err(dev, "failed to initialize device\n");
1930 goto err_out;
1931 }
1932
1933 /* register the RNG, if available */
1934 if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
1935 err = talitos_register_rng(dev);
1936 if (err) {
1937 dev_err(dev, "failed to register hwrng: %d\n", err);
1938 goto err_out;
1939 } else
1940 dev_info(dev, "hwrng\n");
1941 }
1942
1943 /* register crypto algorithms the device supports */
9c4a7965
KP		 1944 for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
1945 if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
1946 struct talitos_crypto_alg *t_alg;
1947
1948 t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
1949 if (IS_ERR(t_alg)) {
1950 err = PTR_ERR(t_alg);
1951 goto err_out;
1952 }
1953
1954 err = crypto_register_alg(&t_alg->crypto_alg);
1955 if (err) {
1956 dev_err(dev, "%s alg registration failed\n",
1957 t_alg->crypto_alg.cra_driver_name);
1958 kfree(t_alg);
1959 } else {
1960 list_add_tail(&t_alg->entry, &priv->alg_list);
1961 dev_info(dev, "%s\n",
1962 t_alg->crypto_alg.cra_driver_name);
1963 }
1964 }
1965 }
1966
1967 return 0;
1968
1969err_out:
1970 talitos_remove(ofdev);
9c4a7965
KP		 1971
1972 return err;
1973}
1974
1975static struct of_device_id talitos_match[] = {
1976 {
1977 .compatible = "fsl,sec2.0",
1978 },
1979 {},
1980};
1981MODULE_DEVICE_TABLE(of, talitos_match);
1982
1983static struct of_platform_driver talitos_driver = {
1984 .name = "talitos",
1985 .match_table = talitos_match,
1986 .probe = talitos_probe,
596f1034 1987 .remove = talitos_remove,
9c4a7965
KP		 1988};
1989
1990static int __init talitos_init(void)
1991{
1992 return of_register_platform_driver(&talitos_driver);
1993}
1994module_init(talitos_init);
1995
1996static void __exit talitos_exit(void)
1997{
1998 of_unregister_platform_driver(&talitos_driver);
1999}
2000module_exit(talitos_exit);
2001
2002MODULE_LICENSE("GPL");
2003MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
2004MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");
Linux kernel - Deliverables
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