Merge remote-tracking branch 'lightnvm/for-next'
[deliverable/linux.git] / drivers / dma / dmatest.c
CommitLineData
4a776f0a
HS
1/*
2 * DMA Engine test module
3 *
4 * Copyright (C) 2007 Atmel Corporation
851b7e16 5 * Copyright (C) 2013 Intel Corporation
4a776f0a
HS
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
872f05c6
DW
11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
4a776f0a 13#include <linux/delay.h>
b7f080cf 14#include <linux/dma-mapping.h>
4a776f0a 15#include <linux/dmaengine.h>
981ed70d 16#include <linux/freezer.h>
4a776f0a
HS
17#include <linux/init.h>
18#include <linux/kthread.h>
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/random.h>
5a0e3ad6 22#include <linux/slab.h>
4a776f0a
HS
23#include <linux/wait.h>
24
25static unsigned int test_buf_size = 16384;
a6c268d0 26module_param(test_buf_size, uint, S_IRUGO | S_IWUSR);
4a776f0a
HS
27MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");
28
06190d84 29static char test_channel[20];
a6c268d0
AS
30module_param_string(channel, test_channel, sizeof(test_channel),
31 S_IRUGO | S_IWUSR);
4a776f0a
HS
32MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)");
33
a85159fe 34static char test_device[32];
a6c268d0
AS
35module_param_string(device, test_device, sizeof(test_device),
36 S_IRUGO | S_IWUSR);
4a776f0a
HS
37MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)");
38
39static unsigned int threads_per_chan = 1;
a6c268d0 40module_param(threads_per_chan, uint, S_IRUGO | S_IWUSR);
4a776f0a
HS
41MODULE_PARM_DESC(threads_per_chan,
42 "Number of threads to start per channel (default: 1)");
43
44static unsigned int max_channels;
a6c268d0 45module_param(max_channels, uint, S_IRUGO | S_IWUSR);
33df8ca0 46MODULE_PARM_DESC(max_channels,
4a776f0a
HS
47 "Maximum number of channels to use (default: all)");
48
0a2ff57d 49static unsigned int iterations;
a6c268d0 50module_param(iterations, uint, S_IRUGO | S_IWUSR);
0a2ff57d
NF
51MODULE_PARM_DESC(iterations,
52 "Iterations before stopping test (default: infinite)");
53
a0d4cb44
KA
54static unsigned int sg_buffers = 1;
55module_param(sg_buffers, uint, S_IRUGO | S_IWUSR);
56MODULE_PARM_DESC(sg_buffers,
57 "Number of scatter gather buffers (default: 1)");
58
59static unsigned int dmatest = 1;
60module_param(dmatest, uint, S_IRUGO | S_IWUSR);
61MODULE_PARM_DESC(dmatest,
62 "dmatest 0-memcpy 1-slave_sg (default: 1)");
63
b54d5cb9 64static unsigned int xor_sources = 3;
a6c268d0 65module_param(xor_sources, uint, S_IRUGO | S_IWUSR);
b54d5cb9
DW
66MODULE_PARM_DESC(xor_sources,
67 "Number of xor source buffers (default: 3)");
68
58691d64 69static unsigned int pq_sources = 3;
a6c268d0 70module_param(pq_sources, uint, S_IRUGO | S_IWUSR);
58691d64
DW
71MODULE_PARM_DESC(pq_sources,
72 "Number of p+q source buffers (default: 3)");
73
d42efe6b 74static int timeout = 3000;
a6c268d0 75module_param(timeout, uint, S_IRUGO | S_IWUSR);
85ee7a1d
JP
76MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), "
77 "Pass -1 for infinite timeout");
d42efe6b 78
e3b9c347
DW
79static bool noverify;
80module_param(noverify, bool, S_IRUGO | S_IWUSR);
81MODULE_PARM_DESC(noverify, "Disable random data setup and verification");
4a776f0a 82
50137a7d
DW
83static bool verbose;
84module_param(verbose, bool, S_IRUGO | S_IWUSR);
85MODULE_PARM_DESC(verbose, "Enable \"success\" result messages (default: off)");
4a776f0a 86
e03e93a9 87/**
15b8a8ea 88 * struct dmatest_params - test parameters.
e03e93a9
AS
89 * @buf_size: size of the memcpy test buffer
90 * @channel: bus ID of the channel to test
91 * @device: bus ID of the DMA Engine to test
92 * @threads_per_chan: number of threads to start per channel
93 * @max_channels: maximum number of channels to use
94 * @iterations: iterations before stopping test
95 * @xor_sources: number of xor source buffers
96 * @pq_sources: number of p+q source buffers
97 * @timeout: transfer timeout in msec, -1 for infinite timeout
98 */
15b8a8ea 99struct dmatest_params {
e03e93a9
AS
100 unsigned int buf_size;
101 char channel[20];
a85159fe 102 char device[32];
e03e93a9
AS
103 unsigned int threads_per_chan;
104 unsigned int max_channels;
105 unsigned int iterations;
106 unsigned int xor_sources;
107 unsigned int pq_sources;
108 int timeout;
e3b9c347 109 bool noverify;
15b8a8ea
AS
110};
111
112/**
113 * struct dmatest_info - test information.
114 * @params: test parameters
851b7e16 115 * @lock: access protection to the fields of this structure
15b8a8ea 116 */
a310d037 117static struct dmatest_info {
15b8a8ea
AS
118 /* Test parameters */
119 struct dmatest_params params;
838cc704
AS
120
121 /* Internal state */
122 struct list_head channels;
123 unsigned int nr_channels;
851b7e16 124 struct mutex lock;
a310d037
DW
125 bool did_init;
126} test_info = {
127 .channels = LIST_HEAD_INIT(test_info.channels),
128 .lock = __MUTEX_INITIALIZER(test_info.lock),
129};
851b7e16 130
a310d037
DW
131static int dmatest_run_set(const char *val, const struct kernel_param *kp);
132static int dmatest_run_get(char *val, const struct kernel_param *kp);
9c27847d 133static const struct kernel_param_ops run_ops = {
a310d037
DW
134 .set = dmatest_run_set,
135 .get = dmatest_run_get,
e03e93a9 136};
a310d037
DW
137static bool dmatest_run;
138module_param_cb(run, &run_ops, &dmatest_run, S_IRUGO | S_IWUSR);
139MODULE_PARM_DESC(run, "Run the test (default: false)");
e03e93a9 140
a310d037
DW
141/* Maximum amount of mismatched bytes in buffer to print */
142#define MAX_ERROR_COUNT 32
143
144/*
145 * Initialization patterns. All bytes in the source buffer has bit 7
146 * set, all bytes in the destination buffer has bit 7 cleared.
147 *
148 * Bit 6 is set for all bytes which are to be copied by the DMA
149 * engine. Bit 5 is set for all bytes which are to be overwritten by
150 * the DMA engine.
151 *
152 * The remaining bits are the inverse of a counter which increments by
153 * one for each byte address.
154 */
155#define PATTERN_SRC 0x80
156#define PATTERN_DST 0x00
157#define PATTERN_COPY 0x40
158#define PATTERN_OVERWRITE 0x20
159#define PATTERN_COUNT_MASK 0x1f
851b7e16 160
a310d037
DW
161struct dmatest_thread {
162 struct list_head node;
163 struct dmatest_info *info;
164 struct task_struct *task;
165 struct dma_chan *chan;
166 u8 **srcs;
167 u8 **dsts;
168 enum dma_transaction_type type;
169 bool done;
170};
95019c8c 171
a310d037
DW
172struct dmatest_chan {
173 struct list_head node;
174 struct dma_chan *chan;
175 struct list_head threads;
e03e93a9
AS
176};
177
2d88ce76
DW
178static DECLARE_WAIT_QUEUE_HEAD(thread_wait);
179static bool wait;
180
181static bool is_threaded_test_run(struct dmatest_info *info)
182{
183 struct dmatest_chan *dtc;
184
185 list_for_each_entry(dtc, &info->channels, node) {
186 struct dmatest_thread *thread;
187
188 list_for_each_entry(thread, &dtc->threads, node) {
189 if (!thread->done)
190 return true;
191 }
192 }
193
194 return false;
195}
196
197static int dmatest_wait_get(char *val, const struct kernel_param *kp)
198{
199 struct dmatest_info *info = &test_info;
200 struct dmatest_params *params = &info->params;
201
202 if (params->iterations)
203 wait_event(thread_wait, !is_threaded_test_run(info));
204 wait = true;
205 return param_get_bool(val, kp);
206}
207
9c27847d 208static const struct kernel_param_ops wait_ops = {
2d88ce76
DW
209 .get = dmatest_wait_get,
210 .set = param_set_bool,
211};
212module_param_cb(wait, &wait_ops, &wait, S_IRUGO);
213MODULE_PARM_DESC(wait, "Wait for tests to complete (default: false)");
e03e93a9 214
15b8a8ea 215static bool dmatest_match_channel(struct dmatest_params *params,
e03e93a9 216 struct dma_chan *chan)
4a776f0a 217{
15b8a8ea 218 if (params->channel[0] == '\0')
4a776f0a 219 return true;
15b8a8ea 220 return strcmp(dma_chan_name(chan), params->channel) == 0;
4a776f0a
HS
221}
222
15b8a8ea 223static bool dmatest_match_device(struct dmatest_params *params,
e03e93a9 224 struct dma_device *device)
4a776f0a 225{
15b8a8ea 226 if (params->device[0] == '\0')
4a776f0a 227 return true;
15b8a8ea 228 return strcmp(dev_name(device->dev), params->device) == 0;
4a776f0a
HS
229}
230
231static unsigned long dmatest_random(void)
232{
233 unsigned long buf;
234
be9fa5a4 235 prandom_bytes(&buf, sizeof(buf));
4a776f0a
HS
236 return buf;
237}
238
e03e93a9
AS
239static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len,
240 unsigned int buf_size)
4a776f0a
HS
241{
242 unsigned int i;
b54d5cb9
DW
243 u8 *buf;
244
245 for (; (buf = *bufs); bufs++) {
246 for (i = 0; i < start; i++)
247 buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
248 for ( ; i < start + len; i++)
249 buf[i] = PATTERN_SRC | PATTERN_COPY
c019894e 250 | (~i & PATTERN_COUNT_MASK);
e03e93a9 251 for ( ; i < buf_size; i++)
b54d5cb9
DW
252 buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
253 buf++;
254 }
4a776f0a
HS
255}
256
e03e93a9
AS
257static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len,
258 unsigned int buf_size)
4a776f0a
HS
259{
260 unsigned int i;
b54d5cb9
DW
261 u8 *buf;
262
263 for (; (buf = *bufs); bufs++) {
264 for (i = 0; i < start; i++)
265 buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
266 for ( ; i < start + len; i++)
267 buf[i] = PATTERN_DST | PATTERN_OVERWRITE
268 | (~i & PATTERN_COUNT_MASK);
e03e93a9 269 for ( ; i < buf_size; i++)
b54d5cb9
DW
270 buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
271 }
4a776f0a
HS
272}
273
7b610178
DW
274static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index,
275 unsigned int counter, bool is_srcbuf)
276{
277 u8 diff = actual ^ pattern;
278 u8 expected = pattern | (~counter & PATTERN_COUNT_MASK);
279 const char *thread_name = current->comm;
280
281 if (is_srcbuf)
282 pr_warn("%s: srcbuf[0x%x] overwritten! Expected %02x, got %02x\n",
283 thread_name, index, expected, actual);
284 else if ((pattern & PATTERN_COPY)
285 && (diff & (PATTERN_COPY | PATTERN_OVERWRITE)))
286 pr_warn("%s: dstbuf[0x%x] not copied! Expected %02x, got %02x\n",
287 thread_name, index, expected, actual);
288 else if (diff & PATTERN_SRC)
289 pr_warn("%s: dstbuf[0x%x] was copied! Expected %02x, got %02x\n",
290 thread_name, index, expected, actual);
291 else
292 pr_warn("%s: dstbuf[0x%x] mismatch! Expected %02x, got %02x\n",
293 thread_name, index, expected, actual);
294}
295
296static unsigned int dmatest_verify(u8 **bufs, unsigned int start,
297 unsigned int end, unsigned int counter, u8 pattern,
298 bool is_srcbuf)
4a776f0a
HS
299{
300 unsigned int i;
301 unsigned int error_count = 0;
302 u8 actual;
b54d5cb9
DW
303 u8 expected;
304 u8 *buf;
305 unsigned int counter_orig = counter;
306
307 for (; (buf = *bufs); bufs++) {
308 counter = counter_orig;
309 for (i = start; i < end; i++) {
310 actual = buf[i];
311 expected = pattern | (~counter & PATTERN_COUNT_MASK);
312 if (actual != expected) {
7b610178
DW
313 if (error_count < MAX_ERROR_COUNT)
314 dmatest_mismatch(actual, pattern, i,
315 counter, is_srcbuf);
b54d5cb9
DW
316 error_count++;
317 }
318 counter++;
4a776f0a 319 }
4a776f0a
HS
320 }
321
74b5c07a 322 if (error_count > MAX_ERROR_COUNT)
7b610178 323 pr_warn("%s: %u errors suppressed\n",
74b5c07a 324 current->comm, error_count - MAX_ERROR_COUNT);
4a776f0a
HS
325
326 return error_count;
327}
328
adfa543e
TH
329/* poor man's completion - we want to use wait_event_freezable() on it */
330struct dmatest_done {
331 bool done;
332 wait_queue_head_t *wait;
333};
334
335static void dmatest_callback(void *arg)
e44e0aa3 336{
adfa543e
TH
337 struct dmatest_done *done = arg;
338
339 done->done = true;
340 wake_up_all(done->wait);
e44e0aa3
DW
341}
342
8be9e32b
AM
343static unsigned int min_odd(unsigned int x, unsigned int y)
344{
345 unsigned int val = min(x, y);
346
347 return val % 2 ? val : val - 1;
348}
349
872f05c6
DW
350static void result(const char *err, unsigned int n, unsigned int src_off,
351 unsigned int dst_off, unsigned int len, unsigned long data)
d86b2f29 352{
2acec150 353 pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
872f05c6 354 current->comm, n, err, src_off, dst_off, len, data);
d86b2f29
AS
355}
356
872f05c6
DW
357static void dbg_result(const char *err, unsigned int n, unsigned int src_off,
358 unsigned int dst_off, unsigned int len,
359 unsigned long data)
95019c8c 360{
2acec150 361 pr_debug("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
a835bb85 362 current->comm, n, err, src_off, dst_off, len, data);
95019c8c
AS
363}
364
a835bb85
AS
365#define verbose_result(err, n, src_off, dst_off, len, data) ({ \
366 if (verbose) \
367 result(err, n, src_off, dst_off, len, data); \
368 else \
369 dbg_result(err, n, src_off, dst_off, len, data);\
50137a7d 370})
95019c8c 371
86727443 372static unsigned long long dmatest_persec(s64 runtime, unsigned int val)
d86b2f29 373{
86727443 374 unsigned long long per_sec = 1000000;
d86b2f29 375
86727443
DW
376 if (runtime <= 0)
377 return 0;
95019c8c 378
86727443
DW
379 /* drop precision until runtime is 32-bits */
380 while (runtime > UINT_MAX) {
381 runtime >>= 1;
382 per_sec <<= 1;
95019c8c
AS
383 }
384
86727443
DW
385 per_sec *= val;
386 do_div(per_sec, runtime);
387 return per_sec;
95019c8c
AS
388}
389
86727443 390static unsigned long long dmatest_KBs(s64 runtime, unsigned long long len)
95019c8c 391{
86727443 392 return dmatest_persec(runtime, len >> 10);
95019c8c
AS
393}
394
4a776f0a
HS
395/*
396 * This function repeatedly tests DMA transfers of various lengths and
b54d5cb9
DW
397 * offsets for a given operation type until it is told to exit by
398 * kthread_stop(). There may be multiple threads running this function
399 * in parallel for a single channel, and there may be multiple channels
400 * being tested in parallel.
4a776f0a
HS
401 *
402 * Before each test, the source and destination buffer is initialized
403 * with a known pattern. This pattern is different depending on
404 * whether it's in an area which is supposed to be copied or
405 * overwritten, and different in the source and destination buffers.
406 * So if the DMA engine doesn't copy exactly what we tell it to copy,
407 * we'll notice.
408 */
409static int dmatest_func(void *data)
410{
adfa543e 411 DECLARE_WAIT_QUEUE_HEAD_ONSTACK(done_wait);
4a776f0a 412 struct dmatest_thread *thread = data;
adfa543e 413 struct dmatest_done done = { .wait = &done_wait };
e03e93a9 414 struct dmatest_info *info;
15b8a8ea 415 struct dmatest_params *params;
4a776f0a 416 struct dma_chan *chan;
8be9e32b 417 struct dma_device *dev;
4a776f0a
HS
418 unsigned int error_count;
419 unsigned int failed_tests = 0;
420 unsigned int total_tests = 0;
421 dma_cookie_t cookie;
422 enum dma_status status;
b54d5cb9 423 enum dma_ctrl_flags flags;
945b5af3 424 u8 *pq_coefs = NULL;
4a776f0a 425 int ret;
b54d5cb9
DW
426 int src_cnt;
427 int dst_cnt;
428 int i;
e9405ef0
SK
429 ktime_t ktime, start, diff;
430 ktime_t filltime = ktime_set(0, 0);
431 ktime_t comparetime = ktime_set(0, 0);
86727443
DW
432 s64 runtime = 0;
433 unsigned long long total_len = 0;
4a776f0a 434
adfa543e 435 set_freezable();
4a776f0a
HS
436
437 ret = -ENOMEM;
4a776f0a
HS
438
439 smp_rmb();
e03e93a9 440 info = thread->info;
15b8a8ea 441 params = &info->params;
4a776f0a 442 chan = thread->chan;
8be9e32b 443 dev = chan->device;
b54d5cb9
DW
444 if (thread->type == DMA_MEMCPY)
445 src_cnt = dst_cnt = 1;
a0d4cb44
KA
446 else if (thread->type == DMA_SG)
447 src_cnt = dst_cnt = sg_buffers;
b54d5cb9 448 else if (thread->type == DMA_XOR) {
8be9e32b 449 /* force odd to ensure dst = src */
15b8a8ea 450 src_cnt = min_odd(params->xor_sources | 1, dev->max_xor);
b54d5cb9 451 dst_cnt = 1;
58691d64 452 } else if (thread->type == DMA_PQ) {
8be9e32b 453 /* force odd to ensure dst = src */
15b8a8ea 454 src_cnt = min_odd(params->pq_sources | 1, dma_maxpq(dev, 0));
58691d64 455 dst_cnt = 2;
945b5af3 456
15b8a8ea 457 pq_coefs = kmalloc(params->pq_sources+1, GFP_KERNEL);
945b5af3
AS
458 if (!pq_coefs)
459 goto err_thread_type;
460
94de648d 461 for (i = 0; i < src_cnt; i++)
58691d64 462 pq_coefs[i] = 1;
b54d5cb9 463 } else
945b5af3 464 goto err_thread_type;
b54d5cb9
DW
465
466 thread->srcs = kcalloc(src_cnt+1, sizeof(u8 *), GFP_KERNEL);
467 if (!thread->srcs)
468 goto err_srcs;
469 for (i = 0; i < src_cnt; i++) {
15b8a8ea 470 thread->srcs[i] = kmalloc(params->buf_size, GFP_KERNEL);
b54d5cb9
DW
471 if (!thread->srcs[i])
472 goto err_srcbuf;
473 }
474 thread->srcs[i] = NULL;
475
476 thread->dsts = kcalloc(dst_cnt+1, sizeof(u8 *), GFP_KERNEL);
477 if (!thread->dsts)
478 goto err_dsts;
479 for (i = 0; i < dst_cnt; i++) {
15b8a8ea 480 thread->dsts[i] = kmalloc(params->buf_size, GFP_KERNEL);
b54d5cb9
DW
481 if (!thread->dsts[i])
482 goto err_dstbuf;
483 }
484 thread->dsts[i] = NULL;
485
e44e0aa3
DW
486 set_user_nice(current, 10);
487
b203bd3f 488 /*
d1cab34c 489 * src and dst buffers are freed by ourselves below
b203bd3f 490 */
0776ae7b 491 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
4a776f0a 492
86727443 493 ktime = ktime_get();
0a2ff57d 494 while (!kthread_should_stop()
15b8a8ea 495 && !(params->iterations && total_tests >= params->iterations)) {
b54d5cb9 496 struct dma_async_tx_descriptor *tx = NULL;
4076e755
DW
497 struct dmaengine_unmap_data *um;
498 dma_addr_t srcs[src_cnt];
499 dma_addr_t *dsts;
ede23a58 500 unsigned int src_off, dst_off, len;
83544ae9 501 u8 align = 0;
a0d4cb44
KA
502 struct scatterlist tx_sg[src_cnt];
503 struct scatterlist rx_sg[src_cnt];
d86be86e 504
4a776f0a
HS
505 total_tests++;
506
83544ae9 507 /* honor alignment restrictions */
c8a2c191 508 if (thread->type == DMA_MEMCPY || thread->type == DMA_SG)
83544ae9
DW
509 align = dev->copy_align;
510 else if (thread->type == DMA_XOR)
511 align = dev->xor_align;
512 else if (thread->type == DMA_PQ)
513 align = dev->pq_align;
514
15b8a8ea 515 if (1 << align > params->buf_size) {
cfe4f275 516 pr_err("%u-byte buffer too small for %d-byte alignment\n",
15b8a8ea 517 params->buf_size, 1 << align);
cfe4f275
GL
518 break;
519 }
520
ede23a58 521 if (params->noverify)
e3b9c347 522 len = params->buf_size;
ede23a58
AS
523 else
524 len = dmatest_random() % params->buf_size + 1;
525
526 len = (len >> align) << align;
527 if (!len)
528 len = 1 << align;
529
530 total_len += len;
531
532 if (params->noverify) {
e3b9c347
DW
533 src_off = 0;
534 dst_off = 0;
535 } else {
e9405ef0 536 start = ktime_get();
e3b9c347
DW
537 src_off = dmatest_random() % (params->buf_size - len + 1);
538 dst_off = dmatest_random() % (params->buf_size - len + 1);
539
540 src_off = (src_off >> align) << align;
541 dst_off = (dst_off >> align) << align;
542
543 dmatest_init_srcs(thread->srcs, src_off, len,
544 params->buf_size);
545 dmatest_init_dsts(thread->dsts, dst_off, len,
546 params->buf_size);
e9405ef0
SK
547
548 diff = ktime_sub(ktime_get(), start);
549 filltime = ktime_add(filltime, diff);
e3b9c347
DW
550 }
551
4076e755
DW
552 um = dmaengine_get_unmap_data(dev->dev, src_cnt+dst_cnt,
553 GFP_KERNEL);
554 if (!um) {
555 failed_tests++;
556 result("unmap data NULL", total_tests,
557 src_off, dst_off, len, ret);
558 continue;
559 }
4a776f0a 560
4076e755 561 um->len = params->buf_size;
b54d5cb9 562 for (i = 0; i < src_cnt; i++) {
745c00da 563 void *buf = thread->srcs[i];
4076e755 564 struct page *pg = virt_to_page(buf);
745c00da 565 unsigned pg_off = (unsigned long) buf & ~PAGE_MASK;
4076e755
DW
566
567 um->addr[i] = dma_map_page(dev->dev, pg, pg_off,
568 um->len, DMA_TO_DEVICE);
569 srcs[i] = um->addr[i] + src_off;
570 ret = dma_mapping_error(dev->dev, um->addr[i]);
afde3be1 571 if (ret) {
4076e755 572 dmaengine_unmap_put(um);
872f05c6
DW
573 result("src mapping error", total_tests,
574 src_off, dst_off, len, ret);
afde3be1
AS
575 failed_tests++;
576 continue;
577 }
4076e755 578 um->to_cnt++;
b54d5cb9 579 }
d86be86e 580 /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */
4076e755 581 dsts = &um->addr[src_cnt];
b54d5cb9 582 for (i = 0; i < dst_cnt; i++) {
745c00da 583 void *buf = thread->dsts[i];
4076e755 584 struct page *pg = virt_to_page(buf);
745c00da 585 unsigned pg_off = (unsigned long) buf & ~PAGE_MASK;
4076e755
DW
586
587 dsts[i] = dma_map_page(dev->dev, pg, pg_off, um->len,
588 DMA_BIDIRECTIONAL);
589 ret = dma_mapping_error(dev->dev, dsts[i]);
afde3be1 590 if (ret) {
4076e755 591 dmaengine_unmap_put(um);
872f05c6
DW
592 result("dst mapping error", total_tests,
593 src_off, dst_off, len, ret);
afde3be1
AS
594 failed_tests++;
595 continue;
596 }
4076e755 597 um->bidi_cnt++;
b54d5cb9
DW
598 }
599
a0d4cb44
KA
600 sg_init_table(tx_sg, src_cnt);
601 sg_init_table(rx_sg, src_cnt);
602 for (i = 0; i < src_cnt; i++) {
603 sg_dma_address(&rx_sg[i]) = srcs[i];
604 sg_dma_address(&tx_sg[i]) = dsts[i] + dst_off;
605 sg_dma_len(&tx_sg[i]) = len;
606 sg_dma_len(&rx_sg[i]) = len;
607 }
608
b54d5cb9
DW
609 if (thread->type == DMA_MEMCPY)
610 tx = dev->device_prep_dma_memcpy(chan,
4076e755
DW
611 dsts[0] + dst_off,
612 srcs[0], len, flags);
a0d4cb44
KA
613 else if (thread->type == DMA_SG)
614 tx = dev->device_prep_dma_sg(chan, tx_sg, src_cnt,
615 rx_sg, src_cnt, flags);
b54d5cb9
DW
616 else if (thread->type == DMA_XOR)
617 tx = dev->device_prep_dma_xor(chan,
4076e755
DW
618 dsts[0] + dst_off,
619 srcs, src_cnt,
b54d5cb9 620 len, flags);
58691d64
DW
621 else if (thread->type == DMA_PQ) {
622 dma_addr_t dma_pq[dst_cnt];
623
624 for (i = 0; i < dst_cnt; i++)
4076e755
DW
625 dma_pq[i] = dsts[i] + dst_off;
626 tx = dev->device_prep_dma_pq(chan, dma_pq, srcs,
94de648d 627 src_cnt, pq_coefs,
58691d64
DW
628 len, flags);
629 }
d86be86e 630
d86be86e 631 if (!tx) {
4076e755 632 dmaengine_unmap_put(um);
872f05c6
DW
633 result("prep error", total_tests, src_off,
634 dst_off, len, ret);
d86be86e
AN
635 msleep(100);
636 failed_tests++;
637 continue;
638 }
e44e0aa3 639
adfa543e 640 done.done = false;
e44e0aa3 641 tx->callback = dmatest_callback;
adfa543e 642 tx->callback_param = &done;
d86be86e
AN
643 cookie = tx->tx_submit(tx);
644
4a776f0a 645 if (dma_submit_error(cookie)) {
4076e755 646 dmaengine_unmap_put(um);
872f05c6
DW
647 result("submit error", total_tests, src_off,
648 dst_off, len, ret);
4a776f0a
HS
649 msleep(100);
650 failed_tests++;
651 continue;
652 }
b54d5cb9 653 dma_async_issue_pending(chan);
4a776f0a 654
bcc567e3 655 wait_event_freezable_timeout(done_wait, done.done,
15b8a8ea 656 msecs_to_jiffies(params->timeout));
981ed70d 657
e44e0aa3 658 status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
4a776f0a 659
adfa543e
TH
660 if (!done.done) {
661 /*
662 * We're leaving the timed out dma operation with
663 * dangling pointer to done_wait. To make this
664 * correct, we'll need to allocate wait_done for
665 * each test iteration and perform "who's gonna
666 * free it this time?" dancing. For now, just
667 * leave it dangling.
668 */
4076e755 669 dmaengine_unmap_put(um);
872f05c6
DW
670 result("test timed out", total_tests, src_off, dst_off,
671 len, 0);
e44e0aa3
DW
672 failed_tests++;
673 continue;
19e9f99f 674 } else if (status != DMA_COMPLETE) {
4076e755 675 dmaengine_unmap_put(um);
872f05c6
DW
676 result(status == DMA_ERROR ?
677 "completion error status" :
678 "completion busy status", total_tests, src_off,
679 dst_off, len, ret);
4a776f0a
HS
680 failed_tests++;
681 continue;
682 }
e44e0aa3 683
4076e755 684 dmaengine_unmap_put(um);
4a776f0a 685
e3b9c347 686 if (params->noverify) {
50137a7d
DW
687 verbose_result("test passed", total_tests, src_off,
688 dst_off, len, 0);
e3b9c347
DW
689 continue;
690 }
4a776f0a 691
e9405ef0 692 start = ktime_get();
872f05c6 693 pr_debug("%s: verifying source buffer...\n", current->comm);
e3b9c347 694 error_count = dmatest_verify(thread->srcs, 0, src_off,
4a776f0a 695 0, PATTERN_SRC, true);
7b610178
DW
696 error_count += dmatest_verify(thread->srcs, src_off,
697 src_off + len, src_off,
698 PATTERN_SRC | PATTERN_COPY, true);
699 error_count += dmatest_verify(thread->srcs, src_off + len,
700 params->buf_size, src_off + len,
701 PATTERN_SRC, true);
702
872f05c6 703 pr_debug("%s: verifying dest buffer...\n", current->comm);
7b610178 704 error_count += dmatest_verify(thread->dsts, 0, dst_off,
4a776f0a 705 0, PATTERN_DST, false);
7b610178
DW
706 error_count += dmatest_verify(thread->dsts, dst_off,
707 dst_off + len, src_off,
708 PATTERN_SRC | PATTERN_COPY, false);
709 error_count += dmatest_verify(thread->dsts, dst_off + len,
710 params->buf_size, dst_off + len,
711 PATTERN_DST, false);
4a776f0a 712
e9405ef0
SK
713 diff = ktime_sub(ktime_get(), start);
714 comparetime = ktime_add(comparetime, diff);
715
4a776f0a 716 if (error_count) {
872f05c6
DW
717 result("data error", total_tests, src_off, dst_off,
718 len, error_count);
4a776f0a
HS
719 failed_tests++;
720 } else {
50137a7d
DW
721 verbose_result("test passed", total_tests, src_off,
722 dst_off, len, 0);
4a776f0a
HS
723 }
724 }
e9405ef0
SK
725 ktime = ktime_sub(ktime_get(), ktime);
726 ktime = ktime_sub(ktime, comparetime);
727 ktime = ktime_sub(ktime, filltime);
728 runtime = ktime_to_us(ktime);
4a776f0a
HS
729
730 ret = 0;
8e1f50d7 731err_dstbuf:
b54d5cb9
DW
732 for (i = 0; thread->dsts[i]; i++)
733 kfree(thread->dsts[i]);
b54d5cb9
DW
734 kfree(thread->dsts);
735err_dsts:
8e1f50d7 736err_srcbuf:
b54d5cb9
DW
737 for (i = 0; thread->srcs[i]; i++)
738 kfree(thread->srcs[i]);
b54d5cb9
DW
739 kfree(thread->srcs);
740err_srcs:
945b5af3
AS
741 kfree(pq_coefs);
742err_thread_type:
86727443
DW
743 pr_info("%s: summary %u tests, %u failures %llu iops %llu KB/s (%d)\n",
744 current->comm, total_tests, failed_tests,
745 dmatest_persec(runtime, total_tests),
746 dmatest_KBs(runtime, total_len), ret);
0a2ff57d 747
9704efaa 748 /* terminate all transfers on specified channels */
5e034f7b
SH
749 if (ret)
750 dmaengine_terminate_all(chan);
751
3e5ccd86 752 thread->done = true;
2d88ce76 753 wake_up(&thread_wait);
0a2ff57d 754
4a776f0a
HS
755 return ret;
756}
757
758static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
759{
760 struct dmatest_thread *thread;
761 struct dmatest_thread *_thread;
762 int ret;
763
764 list_for_each_entry_safe(thread, _thread, &dtc->threads, node) {
765 ret = kthread_stop(thread->task);
0adff800
DW
766 pr_debug("thread %s exited with status %d\n",
767 thread->task->comm, ret);
4a776f0a 768 list_del(&thread->node);
2d88ce76 769 put_task_struct(thread->task);
4a776f0a
HS
770 kfree(thread);
771 }
9704efaa
VK
772
773 /* terminate all transfers on specified channels */
944ea4dd 774 dmaengine_terminate_all(dtc->chan);
9704efaa 775
4a776f0a
HS
776 kfree(dtc);
777}
778
e03e93a9
AS
779static int dmatest_add_threads(struct dmatest_info *info,
780 struct dmatest_chan *dtc, enum dma_transaction_type type)
4a776f0a 781{
15b8a8ea 782 struct dmatest_params *params = &info->params;
b54d5cb9
DW
783 struct dmatest_thread *thread;
784 struct dma_chan *chan = dtc->chan;
785 char *op;
786 unsigned int i;
4a776f0a 787
b54d5cb9
DW
788 if (type == DMA_MEMCPY)
789 op = "copy";
a0d4cb44
KA
790 else if (type == DMA_SG)
791 op = "sg";
b54d5cb9
DW
792 else if (type == DMA_XOR)
793 op = "xor";
58691d64
DW
794 else if (type == DMA_PQ)
795 op = "pq";
b54d5cb9
DW
796 else
797 return -EINVAL;
4a776f0a 798
15b8a8ea 799 for (i = 0; i < params->threads_per_chan; i++) {
4a776f0a
HS
800 thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL);
801 if (!thread) {
0adff800
DW
802 pr_warn("No memory for %s-%s%u\n",
803 dma_chan_name(chan), op, i);
4a776f0a
HS
804 break;
805 }
e03e93a9 806 thread->info = info;
4a776f0a 807 thread->chan = dtc->chan;
b54d5cb9 808 thread->type = type;
4a776f0a 809 smp_wmb();
2d88ce76 810 thread->task = kthread_create(dmatest_func, thread, "%s-%s%u",
b54d5cb9 811 dma_chan_name(chan), op, i);
4a776f0a 812 if (IS_ERR(thread->task)) {
2d88ce76 813 pr_warn("Failed to create thread %s-%s%u\n",
0adff800 814 dma_chan_name(chan), op, i);
4a776f0a
HS
815 kfree(thread);
816 break;
817 }
818
819 /* srcbuf and dstbuf are allocated by the thread itself */
2d88ce76 820 get_task_struct(thread->task);
4a776f0a 821 list_add_tail(&thread->node, &dtc->threads);
2d88ce76 822 wake_up_process(thread->task);
4a776f0a
HS
823 }
824
b54d5cb9
DW
825 return i;
826}
827
e03e93a9
AS
828static int dmatest_add_channel(struct dmatest_info *info,
829 struct dma_chan *chan)
b54d5cb9
DW
830{
831 struct dmatest_chan *dtc;
832 struct dma_device *dma_dev = chan->device;
833 unsigned int thread_count = 0;
b9033e68 834 int cnt;
b54d5cb9
DW
835
836 dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL);
837 if (!dtc) {
0adff800 838 pr_warn("No memory for %s\n", dma_chan_name(chan));
b54d5cb9
DW
839 return -ENOMEM;
840 }
841
842 dtc->chan = chan;
843 INIT_LIST_HEAD(&dtc->threads);
844
845 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
a0d4cb44
KA
846 if (dmatest == 0) {
847 cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY);
848 thread_count += cnt > 0 ? cnt : 0;
849 }
b54d5cb9 850 }
a0d4cb44
KA
851
852 if (dma_has_cap(DMA_SG, dma_dev->cap_mask)) {
853 if (dmatest == 1) {
854 cnt = dmatest_add_threads(info, dtc, DMA_SG);
855 thread_count += cnt > 0 ? cnt : 0;
856 }
857 }
858
b54d5cb9 859 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
e03e93a9 860 cnt = dmatest_add_threads(info, dtc, DMA_XOR);
f1aef8b6 861 thread_count += cnt > 0 ? cnt : 0;
b54d5cb9 862 }
58691d64 863 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
e03e93a9 864 cnt = dmatest_add_threads(info, dtc, DMA_PQ);
d07a74a5 865 thread_count += cnt > 0 ? cnt : 0;
58691d64 866 }
b54d5cb9 867
0adff800 868 pr_info("Started %u threads using %s\n",
b54d5cb9 869 thread_count, dma_chan_name(chan));
4a776f0a 870
838cc704
AS
871 list_add_tail(&dtc->node, &info->channels);
872 info->nr_channels++;
4a776f0a 873
33df8ca0 874 return 0;
4a776f0a
HS
875}
876
7dd60251 877static bool filter(struct dma_chan *chan, void *param)
4a776f0a 878{
15b8a8ea 879 struct dmatest_params *params = param;
e03e93a9 880
15b8a8ea
AS
881 if (!dmatest_match_channel(params, chan) ||
882 !dmatest_match_device(params, chan->device))
7dd60251 883 return false;
33df8ca0 884 else
7dd60251 885 return true;
4a776f0a
HS
886}
887
a9e55495
DW
888static void request_channels(struct dmatest_info *info,
889 enum dma_transaction_type type)
4a776f0a 890{
33df8ca0 891 dma_cap_mask_t mask;
33df8ca0
DW
892
893 dma_cap_zero(mask);
a9e55495 894 dma_cap_set(type, mask);
33df8ca0 895 for (;;) {
a9e55495
DW
896 struct dmatest_params *params = &info->params;
897 struct dma_chan *chan;
898
15b8a8ea 899 chan = dma_request_channel(mask, filter, params);
33df8ca0 900 if (chan) {
a9e55495 901 if (dmatest_add_channel(info, chan)) {
33df8ca0
DW
902 dma_release_channel(chan);
903 break; /* add_channel failed, punt */
904 }
905 } else
906 break; /* no more channels available */
15b8a8ea
AS
907 if (params->max_channels &&
908 info->nr_channels >= params->max_channels)
33df8ca0
DW
909 break; /* we have all we need */
910 }
4a776f0a 911}
4a776f0a 912
a9e55495 913static void run_threaded_test(struct dmatest_info *info)
851b7e16 914{
a9e55495 915 struct dmatest_params *params = &info->params;
851b7e16 916
a9e55495
DW
917 /* Copy test parameters */
918 params->buf_size = test_buf_size;
919 strlcpy(params->channel, strim(test_channel), sizeof(params->channel));
920 strlcpy(params->device, strim(test_device), sizeof(params->device));
921 params->threads_per_chan = threads_per_chan;
922 params->max_channels = max_channels;
923 params->iterations = iterations;
924 params->xor_sources = xor_sources;
925 params->pq_sources = pq_sources;
926 params->timeout = timeout;
e3b9c347 927 params->noverify = noverify;
a9e55495
DW
928
929 request_channels(info, DMA_MEMCPY);
930 request_channels(info, DMA_XOR);
a0d4cb44 931 request_channels(info, DMA_SG);
a9e55495 932 request_channels(info, DMA_PQ);
851b7e16 933}
851b7e16 934
a310d037 935static void stop_threaded_test(struct dmatest_info *info)
4a776f0a 936{
33df8ca0 937 struct dmatest_chan *dtc, *_dtc;
7cbd4877 938 struct dma_chan *chan;
33df8ca0 939
838cc704 940 list_for_each_entry_safe(dtc, _dtc, &info->channels, node) {
33df8ca0 941 list_del(&dtc->node);
7cbd4877 942 chan = dtc->chan;
33df8ca0 943 dmatest_cleanup_channel(dtc);
0adff800 944 pr_debug("dropped channel %s\n", dma_chan_name(chan));
7cbd4877 945 dma_release_channel(chan);
33df8ca0 946 }
838cc704
AS
947
948 info->nr_channels = 0;
4a776f0a 949}
e03e93a9 950
a9e55495 951static void restart_threaded_test(struct dmatest_info *info, bool run)
851b7e16 952{
a310d037
DW
953 /* we might be called early to set run=, defer running until all
954 * parameters have been evaluated
955 */
956 if (!info->did_init)
a9e55495 957 return;
851b7e16
AS
958
959 /* Stop any running test first */
a310d037 960 stop_threaded_test(info);
851b7e16
AS
961
962 /* Run test with new parameters */
a9e55495 963 run_threaded_test(info);
851b7e16
AS
964}
965
a310d037 966static int dmatest_run_get(char *val, const struct kernel_param *kp)
851b7e16 967{
a310d037 968 struct dmatest_info *info = &test_info;
851b7e16
AS
969
970 mutex_lock(&info->lock);
a310d037
DW
971 if (is_threaded_test_run(info)) {
972 dmatest_run = true;
3e5ccd86 973 } else {
a310d037
DW
974 stop_threaded_test(info);
975 dmatest_run = false;
3e5ccd86 976 }
851b7e16 977 mutex_unlock(&info->lock);
851b7e16 978
a310d037 979 return param_get_bool(val, kp);
851b7e16
AS
980}
981
a310d037 982static int dmatest_run_set(const char *val, const struct kernel_param *kp)
95019c8c 983{
a310d037
DW
984 struct dmatest_info *info = &test_info;
985 int ret;
95019c8c 986
a310d037
DW
987 mutex_lock(&info->lock);
988 ret = param_set_bool(val, kp);
989 if (ret) {
851b7e16 990 mutex_unlock(&info->lock);
a310d037 991 return ret;
95019c8c
AS
992 }
993
a310d037
DW
994 if (is_threaded_test_run(info))
995 ret = -EBUSY;
996 else if (dmatest_run)
a9e55495 997 restart_threaded_test(info, dmatest_run);
851b7e16 998
a310d037 999 mutex_unlock(&info->lock);
851b7e16 1000
a310d037 1001 return ret;
851b7e16
AS
1002}
1003
e03e93a9
AS
1004static int __init dmatest_init(void)
1005{
1006 struct dmatest_info *info = &test_info;
2d88ce76 1007 struct dmatest_params *params = &info->params;
e03e93a9 1008
a310d037
DW
1009 if (dmatest_run) {
1010 mutex_lock(&info->lock);
a9e55495 1011 run_threaded_test(info);
a310d037
DW
1012 mutex_unlock(&info->lock);
1013 }
838cc704 1014
2d88ce76
DW
1015 if (params->iterations && wait)
1016 wait_event(thread_wait, !is_threaded_test_run(info));
95019c8c 1017
a310d037
DW
1018 /* module parameters are stable, inittime tests are started,
1019 * let userspace take over 'run' control
1020 */
1021 info->did_init = true;
851b7e16 1022
851b7e16 1023 return 0;
e03e93a9
AS
1024}
1025/* when compiled-in wait for drivers to load first */
1026late_initcall(dmatest_init);
1027
1028static void __exit dmatest_exit(void)
1029{
1030 struct dmatest_info *info = &test_info;
1031
a310d037 1032 mutex_lock(&info->lock);
e03e93a9 1033 stop_threaded_test(info);
a310d037 1034 mutex_unlock(&info->lock);
e03e93a9 1035}
4a776f0a
HS
1036module_exit(dmatest_exit);
1037
e05503ef 1038MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
4a776f0a 1039MODULE_LICENSE("GPL v2");
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