dmaengine: dw: platform: check nr_masters to be non-zero
[deliverable/linux.git] / drivers / dma / dw / platform.c
CommitLineData
9cade1a4
AS
1/*
2 * Platform driver for the Synopsys DesignWare DMA Controller
3 *
4 * Copyright (C) 2007-2008 Atmel Corporation
5 * Copyright (C) 2010-2011 ST Microelectronics
6 * Copyright (C) 2013 Intel Corporation
7 *
8 * Some parts of this driver are derived from the original dw_dmac.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/module.h>
16#include <linux/device.h>
17#include <linux/clk.h>
6acf3998 18#include <linux/pm_runtime.h>
9cade1a4
AS
19#include <linux/platform_device.h>
20#include <linux/dmaengine.h>
21#include <linux/dma-mapping.h>
22#include <linux/of.h>
23#include <linux/of_dma.h>
24#include <linux/acpi.h>
25#include <linux/acpi_dma.h>
26
27#include "internal.h"
28
a104a45b
AS
29#define DRV_NAME "dw_dmac"
30
9cade1a4
AS
31static struct dma_chan *dw_dma_of_xlate(struct of_phandle_args *dma_spec,
32 struct of_dma *ofdma)
33{
34 struct dw_dma *dw = ofdma->of_dma_data;
4d130de2
AS
35 struct dw_dma_slave slave = {
36 .dma_dev = dw->dma.dev,
9cade1a4
AS
37 };
38 dma_cap_mask_t cap;
39
40 if (dma_spec->args_count != 3)
41 return NULL;
42
4d130de2
AS
43 slave.src_id = dma_spec->args[0];
44 slave.dst_id = dma_spec->args[0];
c422025c
AS
45 slave.m_master = dma_spec->args[1];
46 slave.p_master = dma_spec->args[2];
9cade1a4 47
4d130de2
AS
48 if (WARN_ON(slave.src_id >= DW_DMA_MAX_NR_REQUESTS ||
49 slave.dst_id >= DW_DMA_MAX_NR_REQUESTS ||
c422025c
AS
50 slave.m_master >= dw->nr_masters ||
51 slave.p_master >= dw->nr_masters))
9cade1a4
AS
52 return NULL;
53
54 dma_cap_zero(cap);
55 dma_cap_set(DMA_SLAVE, cap);
56
57 /* TODO: there should be a simpler way to do this */
4d130de2 58 return dma_request_channel(cap, dw_dma_filter, &slave);
9cade1a4
AS
59}
60
61#ifdef CONFIG_ACPI
62static bool dw_dma_acpi_filter(struct dma_chan *chan, void *param)
63{
9cade1a4 64 struct acpi_dma_spec *dma_spec = param;
4d130de2
AS
65 struct dw_dma_slave slave = {
66 .dma_dev = dma_spec->dev,
67 .src_id = dma_spec->slave_id,
68 .dst_id = dma_spec->slave_id,
c422025c
AS
69 .m_master = 0,
70 .p_master = 1,
4d130de2 71 };
9cade1a4 72
4d130de2 73 return dw_dma_filter(chan, &slave);
9cade1a4
AS
74}
75
76static void dw_dma_acpi_controller_register(struct dw_dma *dw)
77{
78 struct device *dev = dw->dma.dev;
79 struct acpi_dma_filter_info *info;
80 int ret;
81
82 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
83 if (!info)
84 return;
85
86 dma_cap_zero(info->dma_cap);
87 dma_cap_set(DMA_SLAVE, info->dma_cap);
88 info->filter_fn = dw_dma_acpi_filter;
89
90 ret = devm_acpi_dma_controller_register(dev, acpi_dma_simple_xlate,
91 info);
92 if (ret)
93 dev_err(dev, "could not register acpi_dma_controller\n");
94}
95#else /* !CONFIG_ACPI */
96static inline void dw_dma_acpi_controller_register(struct dw_dma *dw) {}
97#endif /* !CONFIG_ACPI */
98
99#ifdef CONFIG_OF
100static struct dw_dma_platform_data *
101dw_dma_parse_dt(struct platform_device *pdev)
102{
103 struct device_node *np = pdev->dev.of_node;
104 struct dw_dma_platform_data *pdata;
d8ded50f 105 u32 tmp, arr[DW_DMA_MAX_NR_MASTERS];
969f750f 106 u32 nr_masters;
2b574ba9 107 u32 nr_channels;
9cade1a4
AS
108
109 if (!np) {
110 dev_err(&pdev->dev, "Missing DT data\n");
111 return NULL;
112 }
113
969f750f
AS
114 if (of_property_read_u32(np, "dma-masters", &nr_masters))
115 return NULL;
116 if (nr_masters < 1 || nr_masters > DW_DMA_MAX_NR_MASTERS)
117 return NULL;
118
2b574ba9
MR
119 if (of_property_read_u32(np, "dma-channels", &nr_channels))
120 return NULL;
121
9cade1a4
AS
122 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
123 if (!pdata)
124 return NULL;
125
969f750f 126 pdata->nr_masters = nr_masters;
2b574ba9 127 pdata->nr_channels = nr_channels;
9cade1a4
AS
128
129 if (of_property_read_bool(np, "is_private"))
130 pdata->is_private = true;
131
132 if (!of_property_read_u32(np, "chan_allocation_order", &tmp))
133 pdata->chan_allocation_order = (unsigned char)tmp;
134
135 if (!of_property_read_u32(np, "chan_priority", &tmp))
136 pdata->chan_priority = tmp;
137
138 if (!of_property_read_u32(np, "block_size", &tmp))
139 pdata->block_size = tmp;
140
969f750f
AS
141 if (!of_property_read_u32_array(np, "data_width", arr, nr_masters)) {
142 for (tmp = 0; tmp < nr_masters; tmp++)
9cade1a4 143 pdata->data_width[tmp] = arr[tmp];
969f750f 144 }
9cade1a4
AS
145
146 return pdata;
147}
148#else
149static inline struct dw_dma_platform_data *
150dw_dma_parse_dt(struct platform_device *pdev)
151{
152 return NULL;
153}
154#endif
155
156static int dw_probe(struct platform_device *pdev)
157{
158 struct dw_dma_chip *chip;
159 struct device *dev = &pdev->dev;
160 struct resource *mem;
161 struct dw_dma_platform_data *pdata;
162 int err;
163
164 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
165 if (!chip)
166 return -ENOMEM;
167
168 chip->irq = platform_get_irq(pdev, 0);
169 if (chip->irq < 0)
170 return chip->irq;
171
172 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
173 chip->regs = devm_ioremap_resource(dev, mem);
174 if (IS_ERR(chip->regs))
175 return PTR_ERR(chip->regs);
176
24353b8b
RK
177 err = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
178 if (err)
179 return err;
9cade1a4
AS
180
181 pdata = dev_get_platdata(dev);
182 if (!pdata)
183 pdata = dw_dma_parse_dt(pdev);
184
185 chip->dev = dev;
186
a15636e8
AS
187 chip->clk = devm_clk_get(chip->dev, "hclk");
188 if (IS_ERR(chip->clk))
189 return PTR_ERR(chip->clk);
190 err = clk_prepare_enable(chip->clk);
9cade1a4
AS
191 if (err)
192 return err;
193
6acf3998
AS
194 pm_runtime_enable(&pdev->dev);
195
a15636e8
AS
196 err = dw_dma_probe(chip, pdata);
197 if (err)
198 goto err_dw_dma_probe;
199
9cade1a4
AS
200 platform_set_drvdata(pdev, chip);
201
202 if (pdev->dev.of_node) {
203 err = of_dma_controller_register(pdev->dev.of_node,
204 dw_dma_of_xlate, chip->dw);
205 if (err)
206 dev_err(&pdev->dev,
207 "could not register of_dma_controller\n");
208 }
209
210 if (ACPI_HANDLE(&pdev->dev))
211 dw_dma_acpi_controller_register(chip->dw);
212
213 return 0;
a15636e8
AS
214
215err_dw_dma_probe:
6acf3998 216 pm_runtime_disable(&pdev->dev);
a15636e8
AS
217 clk_disable_unprepare(chip->clk);
218 return err;
9cade1a4
AS
219}
220
221static int dw_remove(struct platform_device *pdev)
222{
223 struct dw_dma_chip *chip = platform_get_drvdata(pdev);
224
225 if (pdev->dev.of_node)
226 of_dma_controller_free(pdev->dev.of_node);
227
a15636e8 228 dw_dma_remove(chip);
6acf3998 229 pm_runtime_disable(&pdev->dev);
a15636e8
AS
230 clk_disable_unprepare(chip->clk);
231
232 return 0;
9cade1a4
AS
233}
234
235static void dw_shutdown(struct platform_device *pdev)
236{
237 struct dw_dma_chip *chip = platform_get_drvdata(pdev);
238
32146588
AS
239 /*
240 * We have to call dw_dma_disable() to stop any ongoing transfer. On
241 * some platforms we can't do that since DMA device is powered off.
242 * Moreover we have no possibility to check if the platform is affected
243 * or not. That's why we call pm_runtime_get_sync() / pm_runtime_put()
244 * unconditionally. On the other hand we can't use
245 * pm_runtime_suspended() because runtime PM framework is not fully
246 * used by the driver.
247 */
248 pm_runtime_get_sync(chip->dev);
2540f74b 249 dw_dma_disable(chip);
32146588
AS
250 pm_runtime_put_sync_suspend(chip->dev);
251
a15636e8 252 clk_disable_unprepare(chip->clk);
9cade1a4
AS
253}
254
255#ifdef CONFIG_OF
256static const struct of_device_id dw_dma_of_id_table[] = {
257 { .compatible = "snps,dma-spear1340" },
258 {}
259};
260MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
261#endif
262
263#ifdef CONFIG_ACPI
264static const struct acpi_device_id dw_dma_acpi_id_table[] = {
bc0bb1fd 265 { "INTL9C60", 0 },
9cade1a4
AS
266 { }
267};
be480dcb 268MODULE_DEVICE_TABLE(acpi, dw_dma_acpi_id_table);
9cade1a4
AS
269#endif
270
271#ifdef CONFIG_PM_SLEEP
272
067bd4fd 273static int dw_suspend_late(struct device *dev)
9cade1a4
AS
274{
275 struct platform_device *pdev = to_platform_device(dev);
276 struct dw_dma_chip *chip = platform_get_drvdata(pdev);
277
2540f74b 278 dw_dma_disable(chip);
a15636e8
AS
279 clk_disable_unprepare(chip->clk);
280
281 return 0;
9cade1a4
AS
282}
283
067bd4fd 284static int dw_resume_early(struct device *dev)
9cade1a4
AS
285{
286 struct platform_device *pdev = to_platform_device(dev);
287 struct dw_dma_chip *chip = platform_get_drvdata(pdev);
288
a15636e8 289 clk_prepare_enable(chip->clk);
2540f74b 290 return dw_dma_enable(chip);
9cade1a4
AS
291}
292
067bd4fd 293#endif /* CONFIG_PM_SLEEP */
9cade1a4
AS
294
295static const struct dev_pm_ops dw_dev_pm_ops = {
067bd4fd 296 SET_LATE_SYSTEM_SLEEP_PM_OPS(dw_suspend_late, dw_resume_early)
9cade1a4
AS
297};
298
299static struct platform_driver dw_driver = {
300 .probe = dw_probe,
301 .remove = dw_remove,
2540f74b 302 .shutdown = dw_shutdown,
9cade1a4 303 .driver = {
a104a45b 304 .name = DRV_NAME,
9cade1a4
AS
305 .pm = &dw_dev_pm_ops,
306 .of_match_table = of_match_ptr(dw_dma_of_id_table),
307 .acpi_match_table = ACPI_PTR(dw_dma_acpi_id_table),
308 },
309};
310
311static int __init dw_init(void)
312{
313 return platform_driver_register(&dw_driver);
314}
315subsys_initcall(dw_init);
316
317static void __exit dw_exit(void)
318{
319 platform_driver_unregister(&dw_driver);
320}
321module_exit(dw_exit);
322
323MODULE_LICENSE("GPL v2");
324MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller platform driver");
a104a45b 325MODULE_ALIAS("platform:" DRV_NAME);
This page took 0.138272 seconds and 5 git commands to generate.