Commit | Line | Data |
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c2dde5f8 MP |
1 | /* |
2 | * TI EDMA DMA engine driver | |
3 | * | |
4 | * Copyright 2012 Texas Instruments | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation version 2. | |
9 | * | |
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
11 | * kind, whether express or implied; without even the implied warranty | |
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <linux/dmaengine.h> | |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/list.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/spinlock.h> | |
26 | ||
3ad7a42d | 27 | #include <linux/platform_data/edma.h> |
c2dde5f8 MP |
28 | |
29 | #include "dmaengine.h" | |
30 | #include "virt-dma.h" | |
31 | ||
32 | /* | |
33 | * This will go away when the private EDMA API is folded | |
34 | * into this driver and the platform device(s) are | |
35 | * instantiated in the arch code. We can only get away | |
36 | * with this simplification because DA8XX may not be built | |
37 | * in the same kernel image with other DaVinci parts. This | |
38 | * avoids having to sprinkle dmaengine driver platform devices | |
39 | * and data throughout all the existing board files. | |
40 | */ | |
41 | #ifdef CONFIG_ARCH_DAVINCI_DA8XX | |
42 | #define EDMA_CTLRS 2 | |
43 | #define EDMA_CHANS 32 | |
44 | #else | |
45 | #define EDMA_CTLRS 1 | |
46 | #define EDMA_CHANS 64 | |
47 | #endif /* CONFIG_ARCH_DAVINCI_DA8XX */ | |
48 | ||
2abd5f1b JF |
49 | /* |
50 | * Max of 20 segments per channel to conserve PaRAM slots | |
51 | * Also note that MAX_NR_SG should be atleast the no.of periods | |
52 | * that are required for ASoC, otherwise DMA prep calls will | |
53 | * fail. Today davinci-pcm is the only user of this driver and | |
54 | * requires atleast 17 slots, so we setup the default to 20. | |
55 | */ | |
56 | #define MAX_NR_SG 20 | |
c2dde5f8 MP |
57 | #define EDMA_MAX_SLOTS MAX_NR_SG |
58 | #define EDMA_DESCRIPTORS 16 | |
59 | ||
60 | struct edma_desc { | |
61 | struct virt_dma_desc vdesc; | |
62 | struct list_head node; | |
50a9c707 | 63 | int cyclic; |
c2dde5f8 MP |
64 | int absync; |
65 | int pset_nr; | |
53407062 | 66 | int processed; |
c2dde5f8 MP |
67 | struct edmacc_param pset[0]; |
68 | }; | |
69 | ||
70 | struct edma_cc; | |
71 | ||
72 | struct edma_chan { | |
73 | struct virt_dma_chan vchan; | |
74 | struct list_head node; | |
75 | struct edma_desc *edesc; | |
76 | struct edma_cc *ecc; | |
77 | int ch_num; | |
78 | bool alloced; | |
79 | int slot[EDMA_MAX_SLOTS]; | |
c5f47990 | 80 | int missed; |
661f7cb5 | 81 | struct dma_slave_config cfg; |
c2dde5f8 MP |
82 | }; |
83 | ||
84 | struct edma_cc { | |
85 | int ctlr; | |
86 | struct dma_device dma_slave; | |
87 | struct edma_chan slave_chans[EDMA_CHANS]; | |
88 | int num_slave_chans; | |
89 | int dummy_slot; | |
90 | }; | |
91 | ||
92 | static inline struct edma_cc *to_edma_cc(struct dma_device *d) | |
93 | { | |
94 | return container_of(d, struct edma_cc, dma_slave); | |
95 | } | |
96 | ||
97 | static inline struct edma_chan *to_edma_chan(struct dma_chan *c) | |
98 | { | |
99 | return container_of(c, struct edma_chan, vchan.chan); | |
100 | } | |
101 | ||
102 | static inline struct edma_desc | |
103 | *to_edma_desc(struct dma_async_tx_descriptor *tx) | |
104 | { | |
105 | return container_of(tx, struct edma_desc, vdesc.tx); | |
106 | } | |
107 | ||
108 | static void edma_desc_free(struct virt_dma_desc *vdesc) | |
109 | { | |
110 | kfree(container_of(vdesc, struct edma_desc, vdesc)); | |
111 | } | |
112 | ||
113 | /* Dispatch a queued descriptor to the controller (caller holds lock) */ | |
114 | static void edma_execute(struct edma_chan *echan) | |
115 | { | |
53407062 | 116 | struct virt_dma_desc *vdesc; |
c2dde5f8 | 117 | struct edma_desc *edesc; |
53407062 JF |
118 | struct device *dev = echan->vchan.chan.device->dev; |
119 | int i, j, left, nslots; | |
120 | ||
121 | /* If either we processed all psets or we're still not started */ | |
122 | if (!echan->edesc || | |
123 | echan->edesc->pset_nr == echan->edesc->processed) { | |
124 | /* Get next vdesc */ | |
125 | vdesc = vchan_next_desc(&echan->vchan); | |
126 | if (!vdesc) { | |
127 | echan->edesc = NULL; | |
128 | return; | |
129 | } | |
130 | list_del(&vdesc->node); | |
131 | echan->edesc = to_edma_desc(&vdesc->tx); | |
c2dde5f8 MP |
132 | } |
133 | ||
53407062 | 134 | edesc = echan->edesc; |
c2dde5f8 | 135 | |
53407062 JF |
136 | /* Find out how many left */ |
137 | left = edesc->pset_nr - edesc->processed; | |
138 | nslots = min(MAX_NR_SG, left); | |
c2dde5f8 MP |
139 | |
140 | /* Write descriptor PaRAM set(s) */ | |
53407062 JF |
141 | for (i = 0; i < nslots; i++) { |
142 | j = i + edesc->processed; | |
143 | edma_write_slot(echan->slot[i], &edesc->pset[j]); | |
83bb3126 | 144 | dev_vdbg(echan->vchan.chan.device->dev, |
c2dde5f8 MP |
145 | "\n pset[%d]:\n" |
146 | " chnum\t%d\n" | |
147 | " slot\t%d\n" | |
148 | " opt\t%08x\n" | |
149 | " src\t%08x\n" | |
150 | " dst\t%08x\n" | |
151 | " abcnt\t%08x\n" | |
152 | " ccnt\t%08x\n" | |
153 | " bidx\t%08x\n" | |
154 | " cidx\t%08x\n" | |
155 | " lkrld\t%08x\n", | |
53407062 JF |
156 | j, echan->ch_num, echan->slot[i], |
157 | edesc->pset[j].opt, | |
158 | edesc->pset[j].src, | |
159 | edesc->pset[j].dst, | |
160 | edesc->pset[j].a_b_cnt, | |
161 | edesc->pset[j].ccnt, | |
162 | edesc->pset[j].src_dst_bidx, | |
163 | edesc->pset[j].src_dst_cidx, | |
164 | edesc->pset[j].link_bcntrld); | |
c2dde5f8 | 165 | /* Link to the previous slot if not the last set */ |
53407062 | 166 | if (i != (nslots - 1)) |
c2dde5f8 | 167 | edma_link(echan->slot[i], echan->slot[i+1]); |
c2dde5f8 MP |
168 | } |
169 | ||
53407062 JF |
170 | edesc->processed += nslots; |
171 | ||
b267b3bc JF |
172 | /* |
173 | * If this is either the last set in a set of SG-list transactions | |
174 | * then setup a link to the dummy slot, this results in all future | |
175 | * events being absorbed and that's OK because we're done | |
176 | */ | |
50a9c707 JF |
177 | if (edesc->processed == edesc->pset_nr) { |
178 | if (edesc->cyclic) | |
179 | edma_link(echan->slot[nslots-1], echan->slot[1]); | |
180 | else | |
181 | edma_link(echan->slot[nslots-1], | |
182 | echan->ecc->dummy_slot); | |
183 | } | |
b267b3bc | 184 | |
53407062 JF |
185 | if (edesc->processed <= MAX_NR_SG) { |
186 | dev_dbg(dev, "first transfer starting %d\n", echan->ch_num); | |
187 | edma_start(echan->ch_num); | |
5fc68a6c SN |
188 | } else { |
189 | dev_dbg(dev, "chan: %d: completed %d elements, resuming\n", | |
190 | echan->ch_num, edesc->processed); | |
191 | edma_resume(echan->ch_num); | |
53407062 | 192 | } |
c5f47990 JF |
193 | |
194 | /* | |
195 | * This happens due to setup times between intermediate transfers | |
196 | * in long SG lists which have to be broken up into transfers of | |
197 | * MAX_NR_SG | |
198 | */ | |
199 | if (echan->missed) { | |
200 | dev_dbg(dev, "missed event in execute detected\n"); | |
201 | edma_clean_channel(echan->ch_num); | |
202 | edma_stop(echan->ch_num); | |
203 | edma_start(echan->ch_num); | |
204 | edma_trigger_channel(echan->ch_num); | |
205 | echan->missed = 0; | |
206 | } | |
c2dde5f8 MP |
207 | } |
208 | ||
209 | static int edma_terminate_all(struct edma_chan *echan) | |
210 | { | |
211 | unsigned long flags; | |
212 | LIST_HEAD(head); | |
213 | ||
214 | spin_lock_irqsave(&echan->vchan.lock, flags); | |
215 | ||
216 | /* | |
217 | * Stop DMA activity: we assume the callback will not be called | |
218 | * after edma_dma() returns (even if it does, it will see | |
219 | * echan->edesc is NULL and exit.) | |
220 | */ | |
221 | if (echan->edesc) { | |
222 | echan->edesc = NULL; | |
223 | edma_stop(echan->ch_num); | |
224 | } | |
225 | ||
226 | vchan_get_all_descriptors(&echan->vchan, &head); | |
227 | spin_unlock_irqrestore(&echan->vchan.lock, flags); | |
228 | vchan_dma_desc_free_list(&echan->vchan, &head); | |
229 | ||
230 | return 0; | |
231 | } | |
232 | ||
c2dde5f8 | 233 | static int edma_slave_config(struct edma_chan *echan, |
661f7cb5 | 234 | struct dma_slave_config *cfg) |
c2dde5f8 | 235 | { |
661f7cb5 MP |
236 | if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || |
237 | cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) | |
c2dde5f8 MP |
238 | return -EINVAL; |
239 | ||
661f7cb5 | 240 | memcpy(&echan->cfg, cfg, sizeof(echan->cfg)); |
c2dde5f8 MP |
241 | |
242 | return 0; | |
243 | } | |
244 | ||
72c7b67a PU |
245 | static int edma_dma_pause(struct edma_chan *echan) |
246 | { | |
247 | /* Pause/Resume only allowed with cyclic mode */ | |
248 | if (!echan->edesc->cyclic) | |
249 | return -EINVAL; | |
250 | ||
251 | edma_pause(echan->ch_num); | |
252 | return 0; | |
253 | } | |
254 | ||
255 | static int edma_dma_resume(struct edma_chan *echan) | |
256 | { | |
257 | /* Pause/Resume only allowed with cyclic mode */ | |
258 | if (!echan->edesc->cyclic) | |
259 | return -EINVAL; | |
260 | ||
261 | edma_resume(echan->ch_num); | |
262 | return 0; | |
263 | } | |
264 | ||
c2dde5f8 MP |
265 | static int edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
266 | unsigned long arg) | |
267 | { | |
268 | int ret = 0; | |
269 | struct dma_slave_config *config; | |
270 | struct edma_chan *echan = to_edma_chan(chan); | |
271 | ||
272 | switch (cmd) { | |
273 | case DMA_TERMINATE_ALL: | |
274 | edma_terminate_all(echan); | |
275 | break; | |
276 | case DMA_SLAVE_CONFIG: | |
277 | config = (struct dma_slave_config *)arg; | |
278 | ret = edma_slave_config(echan, config); | |
279 | break; | |
72c7b67a PU |
280 | case DMA_PAUSE: |
281 | ret = edma_dma_pause(echan); | |
282 | break; | |
283 | ||
284 | case DMA_RESUME: | |
285 | ret = edma_dma_resume(echan); | |
286 | break; | |
287 | ||
c2dde5f8 MP |
288 | default: |
289 | ret = -ENOSYS; | |
290 | } | |
291 | ||
292 | return ret; | |
293 | } | |
294 | ||
fd009035 JF |
295 | /* |
296 | * A PaRAM set configuration abstraction used by other modes | |
297 | * @chan: Channel who's PaRAM set we're configuring | |
298 | * @pset: PaRAM set to initialize and setup. | |
299 | * @src_addr: Source address of the DMA | |
300 | * @dst_addr: Destination address of the DMA | |
301 | * @burst: In units of dev_width, how much to send | |
302 | * @dev_width: How much is the dev_width | |
303 | * @dma_length: Total length of the DMA transfer | |
304 | * @direction: Direction of the transfer | |
305 | */ | |
306 | static int edma_config_pset(struct dma_chan *chan, struct edmacc_param *pset, | |
307 | dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst, | |
308 | enum dma_slave_buswidth dev_width, unsigned int dma_length, | |
309 | enum dma_transfer_direction direction) | |
310 | { | |
311 | struct edma_chan *echan = to_edma_chan(chan); | |
312 | struct device *dev = chan->device->dev; | |
313 | int acnt, bcnt, ccnt, cidx; | |
314 | int src_bidx, dst_bidx, src_cidx, dst_cidx; | |
315 | int absync; | |
316 | ||
317 | acnt = dev_width; | |
b2b617de PU |
318 | |
319 | /* src/dst_maxburst == 0 is the same case as src/dst_maxburst == 1 */ | |
320 | if (!burst) | |
321 | burst = 1; | |
fd009035 JF |
322 | /* |
323 | * If the maxburst is equal to the fifo width, use | |
324 | * A-synced transfers. This allows for large contiguous | |
325 | * buffer transfers using only one PaRAM set. | |
326 | */ | |
327 | if (burst == 1) { | |
328 | /* | |
329 | * For the A-sync case, bcnt and ccnt are the remainder | |
330 | * and quotient respectively of the division of: | |
331 | * (dma_length / acnt) by (SZ_64K -1). This is so | |
332 | * that in case bcnt over flows, we have ccnt to use. | |
333 | * Note: In A-sync tranfer only, bcntrld is used, but it | |
334 | * only applies for sg_dma_len(sg) >= SZ_64K. | |
335 | * In this case, the best way adopted is- bccnt for the | |
336 | * first frame will be the remainder below. Then for | |
337 | * every successive frame, bcnt will be SZ_64K-1. This | |
338 | * is assured as bcntrld = 0xffff in end of function. | |
339 | */ | |
340 | absync = false; | |
341 | ccnt = dma_length / acnt / (SZ_64K - 1); | |
342 | bcnt = dma_length / acnt - ccnt * (SZ_64K - 1); | |
343 | /* | |
344 | * If bcnt is non-zero, we have a remainder and hence an | |
345 | * extra frame to transfer, so increment ccnt. | |
346 | */ | |
347 | if (bcnt) | |
348 | ccnt++; | |
349 | else | |
350 | bcnt = SZ_64K - 1; | |
351 | cidx = acnt; | |
352 | } else { | |
353 | /* | |
354 | * If maxburst is greater than the fifo address_width, | |
355 | * use AB-synced transfers where A count is the fifo | |
356 | * address_width and B count is the maxburst. In this | |
357 | * case, we are limited to transfers of C count frames | |
358 | * of (address_width * maxburst) where C count is limited | |
359 | * to SZ_64K-1. This places an upper bound on the length | |
360 | * of an SG segment that can be handled. | |
361 | */ | |
362 | absync = true; | |
363 | bcnt = burst; | |
364 | ccnt = dma_length / (acnt * bcnt); | |
365 | if (ccnt > (SZ_64K - 1)) { | |
366 | dev_err(dev, "Exceeded max SG segment size\n"); | |
367 | return -EINVAL; | |
368 | } | |
369 | cidx = acnt * bcnt; | |
370 | } | |
371 | ||
372 | if (direction == DMA_MEM_TO_DEV) { | |
373 | src_bidx = acnt; | |
374 | src_cidx = cidx; | |
375 | dst_bidx = 0; | |
376 | dst_cidx = 0; | |
377 | } else if (direction == DMA_DEV_TO_MEM) { | |
378 | src_bidx = 0; | |
379 | src_cidx = 0; | |
380 | dst_bidx = acnt; | |
381 | dst_cidx = cidx; | |
382 | } else { | |
383 | dev_err(dev, "%s: direction not implemented yet\n", __func__); | |
384 | return -EINVAL; | |
385 | } | |
386 | ||
387 | pset->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num)); | |
388 | /* Configure A or AB synchronized transfers */ | |
389 | if (absync) | |
390 | pset->opt |= SYNCDIM; | |
391 | ||
392 | pset->src = src_addr; | |
393 | pset->dst = dst_addr; | |
394 | ||
395 | pset->src_dst_bidx = (dst_bidx << 16) | src_bidx; | |
396 | pset->src_dst_cidx = (dst_cidx << 16) | src_cidx; | |
397 | ||
398 | pset->a_b_cnt = bcnt << 16 | acnt; | |
399 | pset->ccnt = ccnt; | |
400 | /* | |
401 | * Only time when (bcntrld) auto reload is required is for | |
402 | * A-sync case, and in this case, a requirement of reload value | |
403 | * of SZ_64K-1 only is assured. 'link' is initially set to NULL | |
404 | * and then later will be populated by edma_execute. | |
405 | */ | |
406 | pset->link_bcntrld = 0xffffffff; | |
407 | return absync; | |
408 | } | |
409 | ||
c2dde5f8 MP |
410 | static struct dma_async_tx_descriptor *edma_prep_slave_sg( |
411 | struct dma_chan *chan, struct scatterlist *sgl, | |
412 | unsigned int sg_len, enum dma_transfer_direction direction, | |
413 | unsigned long tx_flags, void *context) | |
414 | { | |
415 | struct edma_chan *echan = to_edma_chan(chan); | |
416 | struct device *dev = chan->device->dev; | |
417 | struct edma_desc *edesc; | |
fd009035 | 418 | dma_addr_t src_addr = 0, dst_addr = 0; |
661f7cb5 MP |
419 | enum dma_slave_buswidth dev_width; |
420 | u32 burst; | |
c2dde5f8 | 421 | struct scatterlist *sg; |
fd009035 | 422 | int i, nslots, ret; |
c2dde5f8 MP |
423 | |
424 | if (unlikely(!echan || !sgl || !sg_len)) | |
425 | return NULL; | |
426 | ||
661f7cb5 | 427 | if (direction == DMA_DEV_TO_MEM) { |
fd009035 | 428 | src_addr = echan->cfg.src_addr; |
661f7cb5 MP |
429 | dev_width = echan->cfg.src_addr_width; |
430 | burst = echan->cfg.src_maxburst; | |
431 | } else if (direction == DMA_MEM_TO_DEV) { | |
fd009035 | 432 | dst_addr = echan->cfg.dst_addr; |
661f7cb5 MP |
433 | dev_width = echan->cfg.dst_addr_width; |
434 | burst = echan->cfg.dst_maxburst; | |
435 | } else { | |
436 | dev_err(dev, "%s: bad direction?\n", __func__); | |
437 | return NULL; | |
438 | } | |
439 | ||
440 | if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) { | |
c594c891 | 441 | dev_err(dev, "%s: Undefined slave buswidth\n", __func__); |
c2dde5f8 MP |
442 | return NULL; |
443 | } | |
444 | ||
c2dde5f8 MP |
445 | edesc = kzalloc(sizeof(*edesc) + sg_len * |
446 | sizeof(edesc->pset[0]), GFP_ATOMIC); | |
447 | if (!edesc) { | |
c594c891 | 448 | dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__); |
c2dde5f8 MP |
449 | return NULL; |
450 | } | |
451 | ||
452 | edesc->pset_nr = sg_len; | |
453 | ||
6fbe24da JF |
454 | /* Allocate a PaRAM slot, if needed */ |
455 | nslots = min_t(unsigned, MAX_NR_SG, sg_len); | |
456 | ||
457 | for (i = 0; i < nslots; i++) { | |
c2dde5f8 MP |
458 | if (echan->slot[i] < 0) { |
459 | echan->slot[i] = | |
460 | edma_alloc_slot(EDMA_CTLR(echan->ch_num), | |
461 | EDMA_SLOT_ANY); | |
462 | if (echan->slot[i] < 0) { | |
4b6271a6 | 463 | kfree(edesc); |
c594c891 PU |
464 | dev_err(dev, "%s: Failed to allocate slot\n", |
465 | __func__); | |
c2dde5f8 MP |
466 | return NULL; |
467 | } | |
468 | } | |
6fbe24da JF |
469 | } |
470 | ||
471 | /* Configure PaRAM sets for each SG */ | |
472 | for_each_sg(sgl, sg, sg_len, i) { | |
fd009035 JF |
473 | /* Get address for each SG */ |
474 | if (direction == DMA_DEV_TO_MEM) | |
475 | dst_addr = sg_dma_address(sg); | |
476 | else | |
477 | src_addr = sg_dma_address(sg); | |
c2dde5f8 | 478 | |
fd009035 JF |
479 | ret = edma_config_pset(chan, &edesc->pset[i], src_addr, |
480 | dst_addr, burst, dev_width, | |
481 | sg_dma_len(sg), direction); | |
b967aecf VK |
482 | if (ret < 0) { |
483 | kfree(edesc); | |
fd009035 | 484 | return NULL; |
c2dde5f8 MP |
485 | } |
486 | ||
fd009035 | 487 | edesc->absync = ret; |
6fbe24da JF |
488 | |
489 | /* If this is the last in a current SG set of transactions, | |
490 | enable interrupts so that next set is processed */ | |
491 | if (!((i+1) % MAX_NR_SG)) | |
492 | edesc->pset[i].opt |= TCINTEN; | |
493 | ||
c2dde5f8 MP |
494 | /* If this is the last set, enable completion interrupt flag */ |
495 | if (i == sg_len - 1) | |
496 | edesc->pset[i].opt |= TCINTEN; | |
c2dde5f8 | 497 | } |
c2dde5f8 | 498 | |
c2dde5f8 MP |
499 | return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); |
500 | } | |
c2dde5f8 | 501 | |
50a9c707 JF |
502 | static struct dma_async_tx_descriptor *edma_prep_dma_cyclic( |
503 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
504 | size_t period_len, enum dma_transfer_direction direction, | |
505 | unsigned long tx_flags, void *context) | |
506 | { | |
507 | struct edma_chan *echan = to_edma_chan(chan); | |
508 | struct device *dev = chan->device->dev; | |
509 | struct edma_desc *edesc; | |
510 | dma_addr_t src_addr, dst_addr; | |
511 | enum dma_slave_buswidth dev_width; | |
512 | u32 burst; | |
513 | int i, ret, nslots; | |
514 | ||
515 | if (unlikely(!echan || !buf_len || !period_len)) | |
516 | return NULL; | |
517 | ||
518 | if (direction == DMA_DEV_TO_MEM) { | |
519 | src_addr = echan->cfg.src_addr; | |
520 | dst_addr = buf_addr; | |
521 | dev_width = echan->cfg.src_addr_width; | |
522 | burst = echan->cfg.src_maxburst; | |
523 | } else if (direction == DMA_MEM_TO_DEV) { | |
524 | src_addr = buf_addr; | |
525 | dst_addr = echan->cfg.dst_addr; | |
526 | dev_width = echan->cfg.dst_addr_width; | |
527 | burst = echan->cfg.dst_maxburst; | |
528 | } else { | |
529 | dev_err(dev, "%s: bad direction?\n", __func__); | |
530 | return NULL; | |
531 | } | |
532 | ||
533 | if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) { | |
c594c891 | 534 | dev_err(dev, "%s: Undefined slave buswidth\n", __func__); |
50a9c707 JF |
535 | return NULL; |
536 | } | |
537 | ||
538 | if (unlikely(buf_len % period_len)) { | |
539 | dev_err(dev, "Period should be multiple of Buffer length\n"); | |
540 | return NULL; | |
541 | } | |
542 | ||
543 | nslots = (buf_len / period_len) + 1; | |
544 | ||
545 | /* | |
546 | * Cyclic DMA users such as audio cannot tolerate delays introduced | |
547 | * by cases where the number of periods is more than the maximum | |
548 | * number of SGs the EDMA driver can handle at a time. For DMA types | |
549 | * such as Slave SGs, such delays are tolerable and synchronized, | |
550 | * but the synchronization is difficult to achieve with Cyclic and | |
551 | * cannot be guaranteed, so we error out early. | |
552 | */ | |
553 | if (nslots > MAX_NR_SG) | |
554 | return NULL; | |
555 | ||
556 | edesc = kzalloc(sizeof(*edesc) + nslots * | |
557 | sizeof(edesc->pset[0]), GFP_ATOMIC); | |
558 | if (!edesc) { | |
c594c891 | 559 | dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__); |
50a9c707 JF |
560 | return NULL; |
561 | } | |
562 | ||
563 | edesc->cyclic = 1; | |
564 | edesc->pset_nr = nslots; | |
565 | ||
83bb3126 PU |
566 | dev_dbg(dev, "%s: channel=%d nslots=%d period_len=%zu buf_len=%zu\n", |
567 | __func__, echan->ch_num, nslots, period_len, buf_len); | |
50a9c707 JF |
568 | |
569 | for (i = 0; i < nslots; i++) { | |
570 | /* Allocate a PaRAM slot, if needed */ | |
571 | if (echan->slot[i] < 0) { | |
572 | echan->slot[i] = | |
573 | edma_alloc_slot(EDMA_CTLR(echan->ch_num), | |
574 | EDMA_SLOT_ANY); | |
575 | if (echan->slot[i] < 0) { | |
e3ddc979 | 576 | kfree(edesc); |
c594c891 PU |
577 | dev_err(dev, "%s: Failed to allocate slot\n", |
578 | __func__); | |
50a9c707 JF |
579 | return NULL; |
580 | } | |
581 | } | |
582 | ||
583 | if (i == nslots - 1) { | |
584 | memcpy(&edesc->pset[i], &edesc->pset[0], | |
585 | sizeof(edesc->pset[0])); | |
586 | break; | |
587 | } | |
588 | ||
589 | ret = edma_config_pset(chan, &edesc->pset[i], src_addr, | |
590 | dst_addr, burst, dev_width, period_len, | |
591 | direction); | |
e3ddc979 CE |
592 | if (ret < 0) { |
593 | kfree(edesc); | |
50a9c707 | 594 | return NULL; |
e3ddc979 | 595 | } |
c2dde5f8 | 596 | |
50a9c707 JF |
597 | if (direction == DMA_DEV_TO_MEM) |
598 | dst_addr += period_len; | |
599 | else | |
600 | src_addr += period_len; | |
c2dde5f8 | 601 | |
83bb3126 PU |
602 | dev_vdbg(dev, "%s: Configure period %d of buf:\n", __func__, i); |
603 | dev_vdbg(dev, | |
50a9c707 JF |
604 | "\n pset[%d]:\n" |
605 | " chnum\t%d\n" | |
606 | " slot\t%d\n" | |
607 | " opt\t%08x\n" | |
608 | " src\t%08x\n" | |
609 | " dst\t%08x\n" | |
610 | " abcnt\t%08x\n" | |
611 | " ccnt\t%08x\n" | |
612 | " bidx\t%08x\n" | |
613 | " cidx\t%08x\n" | |
614 | " lkrld\t%08x\n", | |
615 | i, echan->ch_num, echan->slot[i], | |
616 | edesc->pset[i].opt, | |
617 | edesc->pset[i].src, | |
618 | edesc->pset[i].dst, | |
619 | edesc->pset[i].a_b_cnt, | |
620 | edesc->pset[i].ccnt, | |
621 | edesc->pset[i].src_dst_bidx, | |
622 | edesc->pset[i].src_dst_cidx, | |
623 | edesc->pset[i].link_bcntrld); | |
624 | ||
625 | edesc->absync = ret; | |
626 | ||
627 | /* | |
628 | * Enable interrupts for every period because callback | |
629 | * has to be called for every period. | |
630 | */ | |
631 | edesc->pset[i].opt |= TCINTEN; | |
c2dde5f8 MP |
632 | } |
633 | ||
634 | return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); | |
635 | } | |
636 | ||
637 | static void edma_callback(unsigned ch_num, u16 ch_status, void *data) | |
638 | { | |
639 | struct edma_chan *echan = data; | |
640 | struct device *dev = echan->vchan.chan.device->dev; | |
641 | struct edma_desc *edesc; | |
642 | unsigned long flags; | |
c5f47990 | 643 | struct edmacc_param p; |
c2dde5f8 | 644 | |
50a9c707 JF |
645 | edesc = echan->edesc; |
646 | ||
647 | /* Pause the channel for non-cyclic */ | |
648 | if (!edesc || (edesc && !edesc->cyclic)) | |
649 | edma_pause(echan->ch_num); | |
c2dde5f8 MP |
650 | |
651 | switch (ch_status) { | |
db60d8da | 652 | case EDMA_DMA_COMPLETE: |
c2dde5f8 MP |
653 | spin_lock_irqsave(&echan->vchan.lock, flags); |
654 | ||
c2dde5f8 | 655 | if (edesc) { |
50a9c707 JF |
656 | if (edesc->cyclic) { |
657 | vchan_cyclic_callback(&edesc->vdesc); | |
658 | } else if (edesc->processed == edesc->pset_nr) { | |
53407062 JF |
659 | dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num); |
660 | edma_stop(echan->ch_num); | |
661 | vchan_cookie_complete(&edesc->vdesc); | |
50a9c707 | 662 | edma_execute(echan); |
53407062 JF |
663 | } else { |
664 | dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num); | |
50a9c707 | 665 | edma_execute(echan); |
53407062 | 666 | } |
c2dde5f8 MP |
667 | } |
668 | ||
669 | spin_unlock_irqrestore(&echan->vchan.lock, flags); | |
670 | ||
671 | break; | |
db60d8da | 672 | case EDMA_DMA_CC_ERROR: |
c5f47990 JF |
673 | spin_lock_irqsave(&echan->vchan.lock, flags); |
674 | ||
675 | edma_read_slot(EDMA_CHAN_SLOT(echan->slot[0]), &p); | |
676 | ||
677 | /* | |
678 | * Issue later based on missed flag which will be sure | |
679 | * to happen as: | |
680 | * (1) we finished transmitting an intermediate slot and | |
681 | * edma_execute is coming up. | |
682 | * (2) or we finished current transfer and issue will | |
683 | * call edma_execute. | |
684 | * | |
685 | * Important note: issuing can be dangerous here and | |
686 | * lead to some nasty recursion when we are in a NULL | |
687 | * slot. So we avoid doing so and set the missed flag. | |
688 | */ | |
689 | if (p.a_b_cnt == 0 && p.ccnt == 0) { | |
690 | dev_dbg(dev, "Error occurred, looks like slot is null, just setting miss\n"); | |
691 | echan->missed = 1; | |
692 | } else { | |
693 | /* | |
694 | * The slot is already programmed but the event got | |
695 | * missed, so its safe to issue it here. | |
696 | */ | |
697 | dev_dbg(dev, "Error occurred but slot is non-null, TRIGGERING\n"); | |
698 | edma_clean_channel(echan->ch_num); | |
699 | edma_stop(echan->ch_num); | |
700 | edma_start(echan->ch_num); | |
701 | edma_trigger_channel(echan->ch_num); | |
702 | } | |
703 | ||
704 | spin_unlock_irqrestore(&echan->vchan.lock, flags); | |
705 | ||
c2dde5f8 MP |
706 | break; |
707 | default: | |
708 | break; | |
709 | } | |
710 | } | |
711 | ||
712 | /* Alloc channel resources */ | |
713 | static int edma_alloc_chan_resources(struct dma_chan *chan) | |
714 | { | |
715 | struct edma_chan *echan = to_edma_chan(chan); | |
716 | struct device *dev = chan->device->dev; | |
717 | int ret; | |
718 | int a_ch_num; | |
719 | LIST_HEAD(descs); | |
720 | ||
721 | a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback, | |
722 | chan, EVENTQ_DEFAULT); | |
723 | ||
724 | if (a_ch_num < 0) { | |
725 | ret = -ENODEV; | |
726 | goto err_no_chan; | |
727 | } | |
728 | ||
729 | if (a_ch_num != echan->ch_num) { | |
730 | dev_err(dev, "failed to allocate requested channel %u:%u\n", | |
731 | EDMA_CTLR(echan->ch_num), | |
732 | EDMA_CHAN_SLOT(echan->ch_num)); | |
733 | ret = -ENODEV; | |
734 | goto err_wrong_chan; | |
735 | } | |
736 | ||
737 | echan->alloced = true; | |
738 | echan->slot[0] = echan->ch_num; | |
739 | ||
0e772c67 EG |
740 | dev_dbg(dev, "allocated channel for %u:%u\n", |
741 | EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num)); | |
c2dde5f8 MP |
742 | |
743 | return 0; | |
744 | ||
745 | err_wrong_chan: | |
746 | edma_free_channel(a_ch_num); | |
747 | err_no_chan: | |
748 | return ret; | |
749 | } | |
750 | ||
751 | /* Free channel resources */ | |
752 | static void edma_free_chan_resources(struct dma_chan *chan) | |
753 | { | |
754 | struct edma_chan *echan = to_edma_chan(chan); | |
755 | struct device *dev = chan->device->dev; | |
756 | int i; | |
757 | ||
758 | /* Terminate transfers */ | |
759 | edma_stop(echan->ch_num); | |
760 | ||
761 | vchan_free_chan_resources(&echan->vchan); | |
762 | ||
763 | /* Free EDMA PaRAM slots */ | |
764 | for (i = 1; i < EDMA_MAX_SLOTS; i++) { | |
765 | if (echan->slot[i] >= 0) { | |
766 | edma_free_slot(echan->slot[i]); | |
767 | echan->slot[i] = -1; | |
768 | } | |
769 | } | |
770 | ||
771 | /* Free EDMA channel */ | |
772 | if (echan->alloced) { | |
773 | edma_free_channel(echan->ch_num); | |
774 | echan->alloced = false; | |
775 | } | |
776 | ||
0e772c67 | 777 | dev_dbg(dev, "freeing channel for %u\n", echan->ch_num); |
c2dde5f8 MP |
778 | } |
779 | ||
780 | /* Send pending descriptor to hardware */ | |
781 | static void edma_issue_pending(struct dma_chan *chan) | |
782 | { | |
783 | struct edma_chan *echan = to_edma_chan(chan); | |
784 | unsigned long flags; | |
785 | ||
786 | spin_lock_irqsave(&echan->vchan.lock, flags); | |
787 | if (vchan_issue_pending(&echan->vchan) && !echan->edesc) | |
788 | edma_execute(echan); | |
789 | spin_unlock_irqrestore(&echan->vchan.lock, flags); | |
790 | } | |
791 | ||
792 | static size_t edma_desc_size(struct edma_desc *edesc) | |
793 | { | |
794 | int i; | |
795 | size_t size; | |
796 | ||
797 | if (edesc->absync) | |
798 | for (size = i = 0; i < edesc->pset_nr; i++) | |
799 | size += (edesc->pset[i].a_b_cnt & 0xffff) * | |
800 | (edesc->pset[i].a_b_cnt >> 16) * | |
801 | edesc->pset[i].ccnt; | |
802 | else | |
803 | size = (edesc->pset[0].a_b_cnt & 0xffff) * | |
804 | (edesc->pset[0].a_b_cnt >> 16) + | |
805 | (edesc->pset[0].a_b_cnt & 0xffff) * | |
806 | (SZ_64K - 1) * edesc->pset[0].ccnt; | |
807 | ||
808 | return size; | |
809 | } | |
810 | ||
811 | /* Check request completion status */ | |
812 | static enum dma_status edma_tx_status(struct dma_chan *chan, | |
813 | dma_cookie_t cookie, | |
814 | struct dma_tx_state *txstate) | |
815 | { | |
816 | struct edma_chan *echan = to_edma_chan(chan); | |
817 | struct virt_dma_desc *vdesc; | |
818 | enum dma_status ret; | |
819 | unsigned long flags; | |
820 | ||
821 | ret = dma_cookie_status(chan, cookie, txstate); | |
9d386ec5 | 822 | if (ret == DMA_COMPLETE || !txstate) |
c2dde5f8 MP |
823 | return ret; |
824 | ||
825 | spin_lock_irqsave(&echan->vchan.lock, flags); | |
826 | vdesc = vchan_find_desc(&echan->vchan, cookie); | |
827 | if (vdesc) { | |
828 | txstate->residue = edma_desc_size(to_edma_desc(&vdesc->tx)); | |
829 | } else if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) { | |
830 | struct edma_desc *edesc = echan->edesc; | |
831 | txstate->residue = edma_desc_size(edesc); | |
c2dde5f8 MP |
832 | } |
833 | spin_unlock_irqrestore(&echan->vchan.lock, flags); | |
834 | ||
835 | return ret; | |
836 | } | |
837 | ||
838 | static void __init edma_chan_init(struct edma_cc *ecc, | |
839 | struct dma_device *dma, | |
840 | struct edma_chan *echans) | |
841 | { | |
842 | int i, j; | |
843 | ||
844 | for (i = 0; i < EDMA_CHANS; i++) { | |
845 | struct edma_chan *echan = &echans[i]; | |
846 | echan->ch_num = EDMA_CTLR_CHAN(ecc->ctlr, i); | |
847 | echan->ecc = ecc; | |
848 | echan->vchan.desc_free = edma_desc_free; | |
849 | ||
850 | vchan_init(&echan->vchan, dma); | |
851 | ||
852 | INIT_LIST_HEAD(&echan->node); | |
853 | for (j = 0; j < EDMA_MAX_SLOTS; j++) | |
854 | echan->slot[j] = -1; | |
855 | } | |
856 | } | |
857 | ||
2c88ee6b PU |
858 | #define EDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ |
859 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ | |
860 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) | |
861 | ||
862 | static int edma_dma_device_slave_caps(struct dma_chan *dchan, | |
863 | struct dma_slave_caps *caps) | |
864 | { | |
865 | caps->src_addr_widths = EDMA_DMA_BUSWIDTHS; | |
866 | caps->dstn_addr_widths = EDMA_DMA_BUSWIDTHS; | |
867 | caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); | |
868 | caps->cmd_pause = true; | |
869 | caps->cmd_terminate = true; | |
870 | caps->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; | |
871 | ||
872 | return 0; | |
873 | } | |
874 | ||
c2dde5f8 MP |
875 | static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma, |
876 | struct device *dev) | |
877 | { | |
878 | dma->device_prep_slave_sg = edma_prep_slave_sg; | |
50a9c707 | 879 | dma->device_prep_dma_cyclic = edma_prep_dma_cyclic; |
c2dde5f8 MP |
880 | dma->device_alloc_chan_resources = edma_alloc_chan_resources; |
881 | dma->device_free_chan_resources = edma_free_chan_resources; | |
882 | dma->device_issue_pending = edma_issue_pending; | |
883 | dma->device_tx_status = edma_tx_status; | |
884 | dma->device_control = edma_control; | |
2c88ee6b | 885 | dma->device_slave_caps = edma_dma_device_slave_caps; |
c2dde5f8 MP |
886 | dma->dev = dev; |
887 | ||
888 | INIT_LIST_HEAD(&dma->channels); | |
889 | } | |
890 | ||
463a1f8b | 891 | static int edma_probe(struct platform_device *pdev) |
c2dde5f8 MP |
892 | { |
893 | struct edma_cc *ecc; | |
894 | int ret; | |
895 | ||
94cb0e79 RK |
896 | ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
897 | if (ret) | |
898 | return ret; | |
899 | ||
c2dde5f8 MP |
900 | ecc = devm_kzalloc(&pdev->dev, sizeof(*ecc), GFP_KERNEL); |
901 | if (!ecc) { | |
902 | dev_err(&pdev->dev, "Can't allocate controller\n"); | |
903 | return -ENOMEM; | |
904 | } | |
905 | ||
906 | ecc->ctlr = pdev->id; | |
907 | ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY); | |
908 | if (ecc->dummy_slot < 0) { | |
909 | dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n"); | |
910 | return -EIO; | |
911 | } | |
912 | ||
913 | dma_cap_zero(ecc->dma_slave.cap_mask); | |
914 | dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask); | |
232b223d | 915 | dma_cap_set(DMA_CYCLIC, ecc->dma_slave.cap_mask); |
c2dde5f8 MP |
916 | |
917 | edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev); | |
918 | ||
919 | edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans); | |
920 | ||
921 | ret = dma_async_device_register(&ecc->dma_slave); | |
922 | if (ret) | |
923 | goto err_reg1; | |
924 | ||
925 | platform_set_drvdata(pdev, ecc); | |
926 | ||
927 | dev_info(&pdev->dev, "TI EDMA DMA engine driver\n"); | |
928 | ||
929 | return 0; | |
930 | ||
931 | err_reg1: | |
932 | edma_free_slot(ecc->dummy_slot); | |
933 | return ret; | |
934 | } | |
935 | ||
4bf27b8b | 936 | static int edma_remove(struct platform_device *pdev) |
c2dde5f8 MP |
937 | { |
938 | struct device *dev = &pdev->dev; | |
939 | struct edma_cc *ecc = dev_get_drvdata(dev); | |
940 | ||
941 | dma_async_device_unregister(&ecc->dma_slave); | |
942 | edma_free_slot(ecc->dummy_slot); | |
943 | ||
944 | return 0; | |
945 | } | |
946 | ||
947 | static struct platform_driver edma_driver = { | |
948 | .probe = edma_probe, | |
a7d6e3ec | 949 | .remove = edma_remove, |
c2dde5f8 MP |
950 | .driver = { |
951 | .name = "edma-dma-engine", | |
952 | .owner = THIS_MODULE, | |
953 | }, | |
954 | }; | |
955 | ||
956 | bool edma_filter_fn(struct dma_chan *chan, void *param) | |
957 | { | |
958 | if (chan->device->dev->driver == &edma_driver.driver) { | |
959 | struct edma_chan *echan = to_edma_chan(chan); | |
960 | unsigned ch_req = *(unsigned *)param; | |
961 | return ch_req == echan->ch_num; | |
962 | } | |
963 | return false; | |
964 | } | |
965 | EXPORT_SYMBOL(edma_filter_fn); | |
966 | ||
967 | static struct platform_device *pdev0, *pdev1; | |
968 | ||
969 | static const struct platform_device_info edma_dev_info0 = { | |
970 | .name = "edma-dma-engine", | |
971 | .id = 0, | |
94cb0e79 | 972 | .dma_mask = DMA_BIT_MASK(32), |
c2dde5f8 MP |
973 | }; |
974 | ||
975 | static const struct platform_device_info edma_dev_info1 = { | |
976 | .name = "edma-dma-engine", | |
977 | .id = 1, | |
94cb0e79 | 978 | .dma_mask = DMA_BIT_MASK(32), |
c2dde5f8 MP |
979 | }; |
980 | ||
981 | static int edma_init(void) | |
982 | { | |
983 | int ret = platform_driver_register(&edma_driver); | |
984 | ||
985 | if (ret == 0) { | |
986 | pdev0 = platform_device_register_full(&edma_dev_info0); | |
987 | if (IS_ERR(pdev0)) { | |
988 | platform_driver_unregister(&edma_driver); | |
989 | ret = PTR_ERR(pdev0); | |
990 | goto out; | |
991 | } | |
992 | } | |
993 | ||
994 | if (EDMA_CTLRS == 2) { | |
995 | pdev1 = platform_device_register_full(&edma_dev_info1); | |
996 | if (IS_ERR(pdev1)) { | |
997 | platform_driver_unregister(&edma_driver); | |
998 | platform_device_unregister(pdev0); | |
999 | ret = PTR_ERR(pdev1); | |
1000 | } | |
1001 | } | |
1002 | ||
1003 | out: | |
1004 | return ret; | |
1005 | } | |
1006 | subsys_initcall(edma_init); | |
1007 | ||
1008 | static void __exit edma_exit(void) | |
1009 | { | |
1010 | platform_device_unregister(pdev0); | |
1011 | if (pdev1) | |
1012 | platform_device_unregister(pdev1); | |
1013 | platform_driver_unregister(&edma_driver); | |
1014 | } | |
1015 | module_exit(edma_exit); | |
1016 | ||
d71505b6 | 1017 | MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>"); |
c2dde5f8 MP |
1018 | MODULE_DESCRIPTION("TI EDMA DMA engine driver"); |
1019 | MODULE_LICENSE("GPL v2"); |