Commit | Line | Data |
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c2dde5f8 MP |
1 | /* |
2 | * TI EDMA DMA engine driver | |
3 | * | |
4 | * Copyright 2012 Texas Instruments | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation version 2. | |
9 | * | |
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
11 | * kind, whether express or implied; without even the implied warranty | |
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <linux/dmaengine.h> | |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/list.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/spinlock.h> | |
26 | ||
3ad7a42d | 27 | #include <linux/platform_data/edma.h> |
c2dde5f8 MP |
28 | |
29 | #include "dmaengine.h" | |
30 | #include "virt-dma.h" | |
31 | ||
32 | /* | |
33 | * This will go away when the private EDMA API is folded | |
34 | * into this driver and the platform device(s) are | |
35 | * instantiated in the arch code. We can only get away | |
36 | * with this simplification because DA8XX may not be built | |
37 | * in the same kernel image with other DaVinci parts. This | |
38 | * avoids having to sprinkle dmaengine driver platform devices | |
39 | * and data throughout all the existing board files. | |
40 | */ | |
41 | #ifdef CONFIG_ARCH_DAVINCI_DA8XX | |
42 | #define EDMA_CTLRS 2 | |
43 | #define EDMA_CHANS 32 | |
44 | #else | |
45 | #define EDMA_CTLRS 1 | |
46 | #define EDMA_CHANS 64 | |
47 | #endif /* CONFIG_ARCH_DAVINCI_DA8XX */ | |
48 | ||
49 | /* Max of 16 segments per channel to conserve PaRAM slots */ | |
50 | #define MAX_NR_SG 16 | |
51 | #define EDMA_MAX_SLOTS MAX_NR_SG | |
52 | #define EDMA_DESCRIPTORS 16 | |
53 | ||
54 | struct edma_desc { | |
55 | struct virt_dma_desc vdesc; | |
56 | struct list_head node; | |
57 | int absync; | |
58 | int pset_nr; | |
53407062 | 59 | int processed; |
c2dde5f8 MP |
60 | struct edmacc_param pset[0]; |
61 | }; | |
62 | ||
63 | struct edma_cc; | |
64 | ||
65 | struct edma_chan { | |
66 | struct virt_dma_chan vchan; | |
67 | struct list_head node; | |
68 | struct edma_desc *edesc; | |
69 | struct edma_cc *ecc; | |
70 | int ch_num; | |
71 | bool alloced; | |
72 | int slot[EDMA_MAX_SLOTS]; | |
c5f47990 | 73 | int missed; |
661f7cb5 | 74 | struct dma_slave_config cfg; |
c2dde5f8 MP |
75 | }; |
76 | ||
77 | struct edma_cc { | |
78 | int ctlr; | |
79 | struct dma_device dma_slave; | |
80 | struct edma_chan slave_chans[EDMA_CHANS]; | |
81 | int num_slave_chans; | |
82 | int dummy_slot; | |
83 | }; | |
84 | ||
85 | static inline struct edma_cc *to_edma_cc(struct dma_device *d) | |
86 | { | |
87 | return container_of(d, struct edma_cc, dma_slave); | |
88 | } | |
89 | ||
90 | static inline struct edma_chan *to_edma_chan(struct dma_chan *c) | |
91 | { | |
92 | return container_of(c, struct edma_chan, vchan.chan); | |
93 | } | |
94 | ||
95 | static inline struct edma_desc | |
96 | *to_edma_desc(struct dma_async_tx_descriptor *tx) | |
97 | { | |
98 | return container_of(tx, struct edma_desc, vdesc.tx); | |
99 | } | |
100 | ||
101 | static void edma_desc_free(struct virt_dma_desc *vdesc) | |
102 | { | |
103 | kfree(container_of(vdesc, struct edma_desc, vdesc)); | |
104 | } | |
105 | ||
106 | /* Dispatch a queued descriptor to the controller (caller holds lock) */ | |
107 | static void edma_execute(struct edma_chan *echan) | |
108 | { | |
53407062 | 109 | struct virt_dma_desc *vdesc; |
c2dde5f8 | 110 | struct edma_desc *edesc; |
53407062 JF |
111 | struct device *dev = echan->vchan.chan.device->dev; |
112 | int i, j, left, nslots; | |
113 | ||
114 | /* If either we processed all psets or we're still not started */ | |
115 | if (!echan->edesc || | |
116 | echan->edesc->pset_nr == echan->edesc->processed) { | |
117 | /* Get next vdesc */ | |
118 | vdesc = vchan_next_desc(&echan->vchan); | |
119 | if (!vdesc) { | |
120 | echan->edesc = NULL; | |
121 | return; | |
122 | } | |
123 | list_del(&vdesc->node); | |
124 | echan->edesc = to_edma_desc(&vdesc->tx); | |
c2dde5f8 MP |
125 | } |
126 | ||
53407062 | 127 | edesc = echan->edesc; |
c2dde5f8 | 128 | |
53407062 JF |
129 | /* Find out how many left */ |
130 | left = edesc->pset_nr - edesc->processed; | |
131 | nslots = min(MAX_NR_SG, left); | |
c2dde5f8 MP |
132 | |
133 | /* Write descriptor PaRAM set(s) */ | |
53407062 JF |
134 | for (i = 0; i < nslots; i++) { |
135 | j = i + edesc->processed; | |
136 | edma_write_slot(echan->slot[i], &edesc->pset[j]); | |
c2dde5f8 MP |
137 | dev_dbg(echan->vchan.chan.device->dev, |
138 | "\n pset[%d]:\n" | |
139 | " chnum\t%d\n" | |
140 | " slot\t%d\n" | |
141 | " opt\t%08x\n" | |
142 | " src\t%08x\n" | |
143 | " dst\t%08x\n" | |
144 | " abcnt\t%08x\n" | |
145 | " ccnt\t%08x\n" | |
146 | " bidx\t%08x\n" | |
147 | " cidx\t%08x\n" | |
148 | " lkrld\t%08x\n", | |
53407062 JF |
149 | j, echan->ch_num, echan->slot[i], |
150 | edesc->pset[j].opt, | |
151 | edesc->pset[j].src, | |
152 | edesc->pset[j].dst, | |
153 | edesc->pset[j].a_b_cnt, | |
154 | edesc->pset[j].ccnt, | |
155 | edesc->pset[j].src_dst_bidx, | |
156 | edesc->pset[j].src_dst_cidx, | |
157 | edesc->pset[j].link_bcntrld); | |
c2dde5f8 | 158 | /* Link to the previous slot if not the last set */ |
53407062 | 159 | if (i != (nslots - 1)) |
c2dde5f8 | 160 | edma_link(echan->slot[i], echan->slot[i+1]); |
c2dde5f8 MP |
161 | } |
162 | ||
53407062 JF |
163 | edesc->processed += nslots; |
164 | ||
b267b3bc JF |
165 | /* |
166 | * If this is either the last set in a set of SG-list transactions | |
167 | * then setup a link to the dummy slot, this results in all future | |
168 | * events being absorbed and that's OK because we're done | |
169 | */ | |
170 | if (edesc->processed == edesc->pset_nr) | |
171 | edma_link(echan->slot[nslots-1], echan->ecc->dummy_slot); | |
172 | ||
53407062 JF |
173 | edma_resume(echan->ch_num); |
174 | ||
175 | if (edesc->processed <= MAX_NR_SG) { | |
176 | dev_dbg(dev, "first transfer starting %d\n", echan->ch_num); | |
177 | edma_start(echan->ch_num); | |
178 | } | |
c5f47990 JF |
179 | |
180 | /* | |
181 | * This happens due to setup times between intermediate transfers | |
182 | * in long SG lists which have to be broken up into transfers of | |
183 | * MAX_NR_SG | |
184 | */ | |
185 | if (echan->missed) { | |
186 | dev_dbg(dev, "missed event in execute detected\n"); | |
187 | edma_clean_channel(echan->ch_num); | |
188 | edma_stop(echan->ch_num); | |
189 | edma_start(echan->ch_num); | |
190 | edma_trigger_channel(echan->ch_num); | |
191 | echan->missed = 0; | |
192 | } | |
c2dde5f8 MP |
193 | } |
194 | ||
195 | static int edma_terminate_all(struct edma_chan *echan) | |
196 | { | |
197 | unsigned long flags; | |
198 | LIST_HEAD(head); | |
199 | ||
200 | spin_lock_irqsave(&echan->vchan.lock, flags); | |
201 | ||
202 | /* | |
203 | * Stop DMA activity: we assume the callback will not be called | |
204 | * after edma_dma() returns (even if it does, it will see | |
205 | * echan->edesc is NULL and exit.) | |
206 | */ | |
207 | if (echan->edesc) { | |
208 | echan->edesc = NULL; | |
209 | edma_stop(echan->ch_num); | |
210 | } | |
211 | ||
212 | vchan_get_all_descriptors(&echan->vchan, &head); | |
213 | spin_unlock_irqrestore(&echan->vchan.lock, flags); | |
214 | vchan_dma_desc_free_list(&echan->vchan, &head); | |
215 | ||
216 | return 0; | |
217 | } | |
218 | ||
c2dde5f8 | 219 | static int edma_slave_config(struct edma_chan *echan, |
661f7cb5 | 220 | struct dma_slave_config *cfg) |
c2dde5f8 | 221 | { |
661f7cb5 MP |
222 | if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || |
223 | cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) | |
c2dde5f8 MP |
224 | return -EINVAL; |
225 | ||
661f7cb5 | 226 | memcpy(&echan->cfg, cfg, sizeof(echan->cfg)); |
c2dde5f8 MP |
227 | |
228 | return 0; | |
229 | } | |
230 | ||
231 | static int edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
232 | unsigned long arg) | |
233 | { | |
234 | int ret = 0; | |
235 | struct dma_slave_config *config; | |
236 | struct edma_chan *echan = to_edma_chan(chan); | |
237 | ||
238 | switch (cmd) { | |
239 | case DMA_TERMINATE_ALL: | |
240 | edma_terminate_all(echan); | |
241 | break; | |
242 | case DMA_SLAVE_CONFIG: | |
243 | config = (struct dma_slave_config *)arg; | |
244 | ret = edma_slave_config(echan, config); | |
245 | break; | |
246 | default: | |
247 | ret = -ENOSYS; | |
248 | } | |
249 | ||
250 | return ret; | |
251 | } | |
252 | ||
fd009035 JF |
253 | /* |
254 | * A PaRAM set configuration abstraction used by other modes | |
255 | * @chan: Channel who's PaRAM set we're configuring | |
256 | * @pset: PaRAM set to initialize and setup. | |
257 | * @src_addr: Source address of the DMA | |
258 | * @dst_addr: Destination address of the DMA | |
259 | * @burst: In units of dev_width, how much to send | |
260 | * @dev_width: How much is the dev_width | |
261 | * @dma_length: Total length of the DMA transfer | |
262 | * @direction: Direction of the transfer | |
263 | */ | |
264 | static int edma_config_pset(struct dma_chan *chan, struct edmacc_param *pset, | |
265 | dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst, | |
266 | enum dma_slave_buswidth dev_width, unsigned int dma_length, | |
267 | enum dma_transfer_direction direction) | |
268 | { | |
269 | struct edma_chan *echan = to_edma_chan(chan); | |
270 | struct device *dev = chan->device->dev; | |
271 | int acnt, bcnt, ccnt, cidx; | |
272 | int src_bidx, dst_bidx, src_cidx, dst_cidx; | |
273 | int absync; | |
274 | ||
275 | acnt = dev_width; | |
276 | /* | |
277 | * If the maxburst is equal to the fifo width, use | |
278 | * A-synced transfers. This allows for large contiguous | |
279 | * buffer transfers using only one PaRAM set. | |
280 | */ | |
281 | if (burst == 1) { | |
282 | /* | |
283 | * For the A-sync case, bcnt and ccnt are the remainder | |
284 | * and quotient respectively of the division of: | |
285 | * (dma_length / acnt) by (SZ_64K -1). This is so | |
286 | * that in case bcnt over flows, we have ccnt to use. | |
287 | * Note: In A-sync tranfer only, bcntrld is used, but it | |
288 | * only applies for sg_dma_len(sg) >= SZ_64K. | |
289 | * In this case, the best way adopted is- bccnt for the | |
290 | * first frame will be the remainder below. Then for | |
291 | * every successive frame, bcnt will be SZ_64K-1. This | |
292 | * is assured as bcntrld = 0xffff in end of function. | |
293 | */ | |
294 | absync = false; | |
295 | ccnt = dma_length / acnt / (SZ_64K - 1); | |
296 | bcnt = dma_length / acnt - ccnt * (SZ_64K - 1); | |
297 | /* | |
298 | * If bcnt is non-zero, we have a remainder and hence an | |
299 | * extra frame to transfer, so increment ccnt. | |
300 | */ | |
301 | if (bcnt) | |
302 | ccnt++; | |
303 | else | |
304 | bcnt = SZ_64K - 1; | |
305 | cidx = acnt; | |
306 | } else { | |
307 | /* | |
308 | * If maxburst is greater than the fifo address_width, | |
309 | * use AB-synced transfers where A count is the fifo | |
310 | * address_width and B count is the maxburst. In this | |
311 | * case, we are limited to transfers of C count frames | |
312 | * of (address_width * maxburst) where C count is limited | |
313 | * to SZ_64K-1. This places an upper bound on the length | |
314 | * of an SG segment that can be handled. | |
315 | */ | |
316 | absync = true; | |
317 | bcnt = burst; | |
318 | ccnt = dma_length / (acnt * bcnt); | |
319 | if (ccnt > (SZ_64K - 1)) { | |
320 | dev_err(dev, "Exceeded max SG segment size\n"); | |
321 | return -EINVAL; | |
322 | } | |
323 | cidx = acnt * bcnt; | |
324 | } | |
325 | ||
326 | if (direction == DMA_MEM_TO_DEV) { | |
327 | src_bidx = acnt; | |
328 | src_cidx = cidx; | |
329 | dst_bidx = 0; | |
330 | dst_cidx = 0; | |
331 | } else if (direction == DMA_DEV_TO_MEM) { | |
332 | src_bidx = 0; | |
333 | src_cidx = 0; | |
334 | dst_bidx = acnt; | |
335 | dst_cidx = cidx; | |
336 | } else { | |
337 | dev_err(dev, "%s: direction not implemented yet\n", __func__); | |
338 | return -EINVAL; | |
339 | } | |
340 | ||
341 | pset->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num)); | |
342 | /* Configure A or AB synchronized transfers */ | |
343 | if (absync) | |
344 | pset->opt |= SYNCDIM; | |
345 | ||
346 | pset->src = src_addr; | |
347 | pset->dst = dst_addr; | |
348 | ||
349 | pset->src_dst_bidx = (dst_bidx << 16) | src_bidx; | |
350 | pset->src_dst_cidx = (dst_cidx << 16) | src_cidx; | |
351 | ||
352 | pset->a_b_cnt = bcnt << 16 | acnt; | |
353 | pset->ccnt = ccnt; | |
354 | /* | |
355 | * Only time when (bcntrld) auto reload is required is for | |
356 | * A-sync case, and in this case, a requirement of reload value | |
357 | * of SZ_64K-1 only is assured. 'link' is initially set to NULL | |
358 | * and then later will be populated by edma_execute. | |
359 | */ | |
360 | pset->link_bcntrld = 0xffffffff; | |
361 | return absync; | |
362 | } | |
363 | ||
c2dde5f8 MP |
364 | static struct dma_async_tx_descriptor *edma_prep_slave_sg( |
365 | struct dma_chan *chan, struct scatterlist *sgl, | |
366 | unsigned int sg_len, enum dma_transfer_direction direction, | |
367 | unsigned long tx_flags, void *context) | |
368 | { | |
369 | struct edma_chan *echan = to_edma_chan(chan); | |
370 | struct device *dev = chan->device->dev; | |
371 | struct edma_desc *edesc; | |
fd009035 | 372 | dma_addr_t src_addr = 0, dst_addr = 0; |
661f7cb5 MP |
373 | enum dma_slave_buswidth dev_width; |
374 | u32 burst; | |
c2dde5f8 | 375 | struct scatterlist *sg; |
fd009035 | 376 | int i, nslots, ret; |
c2dde5f8 MP |
377 | |
378 | if (unlikely(!echan || !sgl || !sg_len)) | |
379 | return NULL; | |
380 | ||
661f7cb5 | 381 | if (direction == DMA_DEV_TO_MEM) { |
fd009035 | 382 | src_addr = echan->cfg.src_addr; |
661f7cb5 MP |
383 | dev_width = echan->cfg.src_addr_width; |
384 | burst = echan->cfg.src_maxburst; | |
385 | } else if (direction == DMA_MEM_TO_DEV) { | |
fd009035 | 386 | dst_addr = echan->cfg.dst_addr; |
661f7cb5 MP |
387 | dev_width = echan->cfg.dst_addr_width; |
388 | burst = echan->cfg.dst_maxburst; | |
389 | } else { | |
390 | dev_err(dev, "%s: bad direction?\n", __func__); | |
391 | return NULL; | |
392 | } | |
393 | ||
394 | if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) { | |
c2dde5f8 MP |
395 | dev_err(dev, "Undefined slave buswidth\n"); |
396 | return NULL; | |
397 | } | |
398 | ||
c2dde5f8 MP |
399 | edesc = kzalloc(sizeof(*edesc) + sg_len * |
400 | sizeof(edesc->pset[0]), GFP_ATOMIC); | |
401 | if (!edesc) { | |
402 | dev_dbg(dev, "Failed to allocate a descriptor\n"); | |
403 | return NULL; | |
404 | } | |
405 | ||
406 | edesc->pset_nr = sg_len; | |
407 | ||
6fbe24da JF |
408 | /* Allocate a PaRAM slot, if needed */ |
409 | nslots = min_t(unsigned, MAX_NR_SG, sg_len); | |
410 | ||
411 | for (i = 0; i < nslots; i++) { | |
c2dde5f8 MP |
412 | if (echan->slot[i] < 0) { |
413 | echan->slot[i] = | |
414 | edma_alloc_slot(EDMA_CTLR(echan->ch_num), | |
415 | EDMA_SLOT_ANY); | |
416 | if (echan->slot[i] < 0) { | |
417 | dev_err(dev, "Failed to allocate slot\n"); | |
418 | return NULL; | |
419 | } | |
420 | } | |
6fbe24da JF |
421 | } |
422 | ||
423 | /* Configure PaRAM sets for each SG */ | |
424 | for_each_sg(sgl, sg, sg_len, i) { | |
fd009035 JF |
425 | /* Get address for each SG */ |
426 | if (direction == DMA_DEV_TO_MEM) | |
427 | dst_addr = sg_dma_address(sg); | |
428 | else | |
429 | src_addr = sg_dma_address(sg); | |
c2dde5f8 | 430 | |
fd009035 JF |
431 | ret = edma_config_pset(chan, &edesc->pset[i], src_addr, |
432 | dst_addr, burst, dev_width, | |
433 | sg_dma_len(sg), direction); | |
434 | if (ret < 0) | |
435 | return NULL; | |
c2dde5f8 | 436 | |
fd009035 | 437 | edesc->absync = ret; |
6fbe24da JF |
438 | |
439 | /* If this is the last in a current SG set of transactions, | |
440 | enable interrupts so that next set is processed */ | |
441 | if (!((i+1) % MAX_NR_SG)) | |
442 | edesc->pset[i].opt |= TCINTEN; | |
443 | ||
c2dde5f8 MP |
444 | /* If this is the last set, enable completion interrupt flag */ |
445 | if (i == sg_len - 1) | |
446 | edesc->pset[i].opt |= TCINTEN; | |
c2dde5f8 MP |
447 | } |
448 | ||
449 | return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); | |
450 | } | |
451 | ||
452 | static void edma_callback(unsigned ch_num, u16 ch_status, void *data) | |
453 | { | |
454 | struct edma_chan *echan = data; | |
455 | struct device *dev = echan->vchan.chan.device->dev; | |
456 | struct edma_desc *edesc; | |
457 | unsigned long flags; | |
c5f47990 | 458 | struct edmacc_param p; |
c2dde5f8 | 459 | |
53407062 JF |
460 | /* Pause the channel */ |
461 | edma_pause(echan->ch_num); | |
c2dde5f8 MP |
462 | |
463 | switch (ch_status) { | |
464 | case DMA_COMPLETE: | |
c2dde5f8 MP |
465 | spin_lock_irqsave(&echan->vchan.lock, flags); |
466 | ||
467 | edesc = echan->edesc; | |
468 | if (edesc) { | |
53407062 JF |
469 | if (edesc->processed == edesc->pset_nr) { |
470 | dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num); | |
471 | edma_stop(echan->ch_num); | |
472 | vchan_cookie_complete(&edesc->vdesc); | |
473 | } else { | |
474 | dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num); | |
475 | } | |
476 | ||
c2dde5f8 | 477 | edma_execute(echan); |
c2dde5f8 MP |
478 | } |
479 | ||
480 | spin_unlock_irqrestore(&echan->vchan.lock, flags); | |
481 | ||
482 | break; | |
483 | case DMA_CC_ERROR: | |
c5f47990 JF |
484 | spin_lock_irqsave(&echan->vchan.lock, flags); |
485 | ||
486 | edma_read_slot(EDMA_CHAN_SLOT(echan->slot[0]), &p); | |
487 | ||
488 | /* | |
489 | * Issue later based on missed flag which will be sure | |
490 | * to happen as: | |
491 | * (1) we finished transmitting an intermediate slot and | |
492 | * edma_execute is coming up. | |
493 | * (2) or we finished current transfer and issue will | |
494 | * call edma_execute. | |
495 | * | |
496 | * Important note: issuing can be dangerous here and | |
497 | * lead to some nasty recursion when we are in a NULL | |
498 | * slot. So we avoid doing so and set the missed flag. | |
499 | */ | |
500 | if (p.a_b_cnt == 0 && p.ccnt == 0) { | |
501 | dev_dbg(dev, "Error occurred, looks like slot is null, just setting miss\n"); | |
502 | echan->missed = 1; | |
503 | } else { | |
504 | /* | |
505 | * The slot is already programmed but the event got | |
506 | * missed, so its safe to issue it here. | |
507 | */ | |
508 | dev_dbg(dev, "Error occurred but slot is non-null, TRIGGERING\n"); | |
509 | edma_clean_channel(echan->ch_num); | |
510 | edma_stop(echan->ch_num); | |
511 | edma_start(echan->ch_num); | |
512 | edma_trigger_channel(echan->ch_num); | |
513 | } | |
514 | ||
515 | spin_unlock_irqrestore(&echan->vchan.lock, flags); | |
516 | ||
c2dde5f8 MP |
517 | break; |
518 | default: | |
519 | break; | |
520 | } | |
521 | } | |
522 | ||
523 | /* Alloc channel resources */ | |
524 | static int edma_alloc_chan_resources(struct dma_chan *chan) | |
525 | { | |
526 | struct edma_chan *echan = to_edma_chan(chan); | |
527 | struct device *dev = chan->device->dev; | |
528 | int ret; | |
529 | int a_ch_num; | |
530 | LIST_HEAD(descs); | |
531 | ||
532 | a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback, | |
533 | chan, EVENTQ_DEFAULT); | |
534 | ||
535 | if (a_ch_num < 0) { | |
536 | ret = -ENODEV; | |
537 | goto err_no_chan; | |
538 | } | |
539 | ||
540 | if (a_ch_num != echan->ch_num) { | |
541 | dev_err(dev, "failed to allocate requested channel %u:%u\n", | |
542 | EDMA_CTLR(echan->ch_num), | |
543 | EDMA_CHAN_SLOT(echan->ch_num)); | |
544 | ret = -ENODEV; | |
545 | goto err_wrong_chan; | |
546 | } | |
547 | ||
548 | echan->alloced = true; | |
549 | echan->slot[0] = echan->ch_num; | |
550 | ||
551 | dev_info(dev, "allocated channel for %u:%u\n", | |
552 | EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num)); | |
553 | ||
554 | return 0; | |
555 | ||
556 | err_wrong_chan: | |
557 | edma_free_channel(a_ch_num); | |
558 | err_no_chan: | |
559 | return ret; | |
560 | } | |
561 | ||
562 | /* Free channel resources */ | |
563 | static void edma_free_chan_resources(struct dma_chan *chan) | |
564 | { | |
565 | struct edma_chan *echan = to_edma_chan(chan); | |
566 | struct device *dev = chan->device->dev; | |
567 | int i; | |
568 | ||
569 | /* Terminate transfers */ | |
570 | edma_stop(echan->ch_num); | |
571 | ||
572 | vchan_free_chan_resources(&echan->vchan); | |
573 | ||
574 | /* Free EDMA PaRAM slots */ | |
575 | for (i = 1; i < EDMA_MAX_SLOTS; i++) { | |
576 | if (echan->slot[i] >= 0) { | |
577 | edma_free_slot(echan->slot[i]); | |
578 | echan->slot[i] = -1; | |
579 | } | |
580 | } | |
581 | ||
582 | /* Free EDMA channel */ | |
583 | if (echan->alloced) { | |
584 | edma_free_channel(echan->ch_num); | |
585 | echan->alloced = false; | |
586 | } | |
587 | ||
588 | dev_info(dev, "freeing channel for %u\n", echan->ch_num); | |
589 | } | |
590 | ||
591 | /* Send pending descriptor to hardware */ | |
592 | static void edma_issue_pending(struct dma_chan *chan) | |
593 | { | |
594 | struct edma_chan *echan = to_edma_chan(chan); | |
595 | unsigned long flags; | |
596 | ||
597 | spin_lock_irqsave(&echan->vchan.lock, flags); | |
598 | if (vchan_issue_pending(&echan->vchan) && !echan->edesc) | |
599 | edma_execute(echan); | |
600 | spin_unlock_irqrestore(&echan->vchan.lock, flags); | |
601 | } | |
602 | ||
603 | static size_t edma_desc_size(struct edma_desc *edesc) | |
604 | { | |
605 | int i; | |
606 | size_t size; | |
607 | ||
608 | if (edesc->absync) | |
609 | for (size = i = 0; i < edesc->pset_nr; i++) | |
610 | size += (edesc->pset[i].a_b_cnt & 0xffff) * | |
611 | (edesc->pset[i].a_b_cnt >> 16) * | |
612 | edesc->pset[i].ccnt; | |
613 | else | |
614 | size = (edesc->pset[0].a_b_cnt & 0xffff) * | |
615 | (edesc->pset[0].a_b_cnt >> 16) + | |
616 | (edesc->pset[0].a_b_cnt & 0xffff) * | |
617 | (SZ_64K - 1) * edesc->pset[0].ccnt; | |
618 | ||
619 | return size; | |
620 | } | |
621 | ||
622 | /* Check request completion status */ | |
623 | static enum dma_status edma_tx_status(struct dma_chan *chan, | |
624 | dma_cookie_t cookie, | |
625 | struct dma_tx_state *txstate) | |
626 | { | |
627 | struct edma_chan *echan = to_edma_chan(chan); | |
628 | struct virt_dma_desc *vdesc; | |
629 | enum dma_status ret; | |
630 | unsigned long flags; | |
631 | ||
632 | ret = dma_cookie_status(chan, cookie, txstate); | |
633 | if (ret == DMA_SUCCESS || !txstate) | |
634 | return ret; | |
635 | ||
636 | spin_lock_irqsave(&echan->vchan.lock, flags); | |
637 | vdesc = vchan_find_desc(&echan->vchan, cookie); | |
638 | if (vdesc) { | |
639 | txstate->residue = edma_desc_size(to_edma_desc(&vdesc->tx)); | |
640 | } else if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) { | |
641 | struct edma_desc *edesc = echan->edesc; | |
642 | txstate->residue = edma_desc_size(edesc); | |
c2dde5f8 MP |
643 | } |
644 | spin_unlock_irqrestore(&echan->vchan.lock, flags); | |
645 | ||
646 | return ret; | |
647 | } | |
648 | ||
649 | static void __init edma_chan_init(struct edma_cc *ecc, | |
650 | struct dma_device *dma, | |
651 | struct edma_chan *echans) | |
652 | { | |
653 | int i, j; | |
654 | ||
655 | for (i = 0; i < EDMA_CHANS; i++) { | |
656 | struct edma_chan *echan = &echans[i]; | |
657 | echan->ch_num = EDMA_CTLR_CHAN(ecc->ctlr, i); | |
658 | echan->ecc = ecc; | |
659 | echan->vchan.desc_free = edma_desc_free; | |
660 | ||
661 | vchan_init(&echan->vchan, dma); | |
662 | ||
663 | INIT_LIST_HEAD(&echan->node); | |
664 | for (j = 0; j < EDMA_MAX_SLOTS; j++) | |
665 | echan->slot[j] = -1; | |
666 | } | |
667 | } | |
668 | ||
669 | static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma, | |
670 | struct device *dev) | |
671 | { | |
672 | dma->device_prep_slave_sg = edma_prep_slave_sg; | |
673 | dma->device_alloc_chan_resources = edma_alloc_chan_resources; | |
674 | dma->device_free_chan_resources = edma_free_chan_resources; | |
675 | dma->device_issue_pending = edma_issue_pending; | |
676 | dma->device_tx_status = edma_tx_status; | |
677 | dma->device_control = edma_control; | |
678 | dma->dev = dev; | |
679 | ||
680 | INIT_LIST_HEAD(&dma->channels); | |
681 | } | |
682 | ||
463a1f8b | 683 | static int edma_probe(struct platform_device *pdev) |
c2dde5f8 MP |
684 | { |
685 | struct edma_cc *ecc; | |
686 | int ret; | |
687 | ||
688 | ecc = devm_kzalloc(&pdev->dev, sizeof(*ecc), GFP_KERNEL); | |
689 | if (!ecc) { | |
690 | dev_err(&pdev->dev, "Can't allocate controller\n"); | |
691 | return -ENOMEM; | |
692 | } | |
693 | ||
694 | ecc->ctlr = pdev->id; | |
695 | ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY); | |
696 | if (ecc->dummy_slot < 0) { | |
697 | dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n"); | |
698 | return -EIO; | |
699 | } | |
700 | ||
701 | dma_cap_zero(ecc->dma_slave.cap_mask); | |
702 | dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask); | |
703 | ||
704 | edma_dma_init(ecc, &ecc->dma_slave, &pdev->dev); | |
705 | ||
706 | edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans); | |
707 | ||
708 | ret = dma_async_device_register(&ecc->dma_slave); | |
709 | if (ret) | |
710 | goto err_reg1; | |
711 | ||
712 | platform_set_drvdata(pdev, ecc); | |
713 | ||
714 | dev_info(&pdev->dev, "TI EDMA DMA engine driver\n"); | |
715 | ||
716 | return 0; | |
717 | ||
718 | err_reg1: | |
719 | edma_free_slot(ecc->dummy_slot); | |
720 | return ret; | |
721 | } | |
722 | ||
4bf27b8b | 723 | static int edma_remove(struct platform_device *pdev) |
c2dde5f8 MP |
724 | { |
725 | struct device *dev = &pdev->dev; | |
726 | struct edma_cc *ecc = dev_get_drvdata(dev); | |
727 | ||
728 | dma_async_device_unregister(&ecc->dma_slave); | |
729 | edma_free_slot(ecc->dummy_slot); | |
730 | ||
731 | return 0; | |
732 | } | |
733 | ||
734 | static struct platform_driver edma_driver = { | |
735 | .probe = edma_probe, | |
a7d6e3ec | 736 | .remove = edma_remove, |
c2dde5f8 MP |
737 | .driver = { |
738 | .name = "edma-dma-engine", | |
739 | .owner = THIS_MODULE, | |
740 | }, | |
741 | }; | |
742 | ||
743 | bool edma_filter_fn(struct dma_chan *chan, void *param) | |
744 | { | |
745 | if (chan->device->dev->driver == &edma_driver.driver) { | |
746 | struct edma_chan *echan = to_edma_chan(chan); | |
747 | unsigned ch_req = *(unsigned *)param; | |
748 | return ch_req == echan->ch_num; | |
749 | } | |
750 | return false; | |
751 | } | |
752 | EXPORT_SYMBOL(edma_filter_fn); | |
753 | ||
754 | static struct platform_device *pdev0, *pdev1; | |
755 | ||
756 | static const struct platform_device_info edma_dev_info0 = { | |
757 | .name = "edma-dma-engine", | |
758 | .id = 0, | |
c2dde5f8 MP |
759 | }; |
760 | ||
761 | static const struct platform_device_info edma_dev_info1 = { | |
762 | .name = "edma-dma-engine", | |
763 | .id = 1, | |
c2dde5f8 MP |
764 | }; |
765 | ||
766 | static int edma_init(void) | |
767 | { | |
768 | int ret = platform_driver_register(&edma_driver); | |
769 | ||
770 | if (ret == 0) { | |
771 | pdev0 = platform_device_register_full(&edma_dev_info0); | |
772 | if (IS_ERR(pdev0)) { | |
773 | platform_driver_unregister(&edma_driver); | |
774 | ret = PTR_ERR(pdev0); | |
775 | goto out; | |
776 | } | |
373459ee AS |
777 | pdev0->dev.dma_mask = &pdev0->dev.coherent_dma_mask; |
778 | pdev0->dev.coherent_dma_mask = DMA_BIT_MASK(32); | |
c2dde5f8 MP |
779 | } |
780 | ||
781 | if (EDMA_CTLRS == 2) { | |
782 | pdev1 = platform_device_register_full(&edma_dev_info1); | |
783 | if (IS_ERR(pdev1)) { | |
784 | platform_driver_unregister(&edma_driver); | |
785 | platform_device_unregister(pdev0); | |
786 | ret = PTR_ERR(pdev1); | |
787 | } | |
373459ee AS |
788 | pdev1->dev.dma_mask = &pdev1->dev.coherent_dma_mask; |
789 | pdev1->dev.coherent_dma_mask = DMA_BIT_MASK(32); | |
c2dde5f8 MP |
790 | } |
791 | ||
792 | out: | |
793 | return ret; | |
794 | } | |
795 | subsys_initcall(edma_init); | |
796 | ||
797 | static void __exit edma_exit(void) | |
798 | { | |
799 | platform_device_unregister(pdev0); | |
800 | if (pdev1) | |
801 | platform_device_unregister(pdev1); | |
802 | platform_driver_unregister(&edma_driver); | |
803 | } | |
804 | module_exit(edma_exit); | |
805 | ||
d71505b6 | 806 | MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>"); |
c2dde5f8 MP |
807 | MODULE_DESCRIPTION("TI EDMA DMA engine driver"); |
808 | MODULE_LICENSE("GPL v2"); |