[deliverable/linux.git] / drivers / dma / hsu / hsu.c

/*
 * Core driver for the High Speed UART DMA
 *
 * Copyright (C) 2015 Intel Corporation
 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
 *
 * Partially based on the bits found in drivers/tty/serial/mfd.c.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/*
 * DMA channel allocation:
 * 1. Even number chans are used for DMA Read (UART TX), odd chans for DMA
 *    Write (UART RX).
 * 2. 0/1 channel are assigned to port 0, 2/3 chan to port 1, 4/5 chan to
 *    port 3, and so on.
 */

#include <linux/delay.h>
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/slab.h>

#include "hsu.h"

#define HSU_DMA_BUSWIDTHS				\
	BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED)	|	\
	BIT(DMA_SLAVE_BUSWIDTH_1_BYTE)		|	\
	BIT(DMA_SLAVE_BUSWIDTH_2_BYTES)		|	\
	BIT(DMA_SLAVE_BUSWIDTH_3_BYTES)		|	\
	BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)		|	\
	BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)		|	\
	BIT(DMA_SLAVE_BUSWIDTH_16_BYTES)

static inline void hsu_chan_disable(struct hsu_dma_chan *hsuc)
{
	hsu_chan_writel(hsuc, HSU_CH_CR, 0);
}

static inline void hsu_chan_enable(struct hsu_dma_chan *hsuc)
{
	u32 cr = HSU_CH_CR_CHA;

	if (hsuc->direction == DMA_MEM_TO_DEV)
		cr &= ~HSU_CH_CR_CHD;
	else if (hsuc->direction == DMA_DEV_TO_MEM)
		cr |= HSU_CH_CR_CHD;

	hsu_chan_writel(hsuc, HSU_CH_CR, cr);
}

static void hsu_dma_chan_start(struct hsu_dma_chan *hsuc)
{
	struct dma_slave_config *config = &hsuc->config;
	struct hsu_dma_desc *desc = hsuc->desc;
	u32 bsr = 0, mtsr = 0;	/* to shut the compiler up */
	u32 dcr = HSU_CH_DCR_CHSOE | HSU_CH_DCR_CHEI;
	unsigned int i, count;

	if (hsuc->direction == DMA_MEM_TO_DEV) {
		bsr = config->dst_maxburst;
		mtsr = config->src_addr_width;
	} else if (hsuc->direction == DMA_DEV_TO_MEM) {
		bsr = config->src_maxburst;
		mtsr = config->dst_addr_width;
	}

	hsu_chan_disable(hsuc);

	hsu_chan_writel(hsuc, HSU_CH_DCR, 0);
	hsu_chan_writel(hsuc, HSU_CH_BSR, bsr);
	hsu_chan_writel(hsuc, HSU_CH_MTSR, mtsr);

	/* Set descriptors */
	count = (desc->nents - desc->active) % HSU_DMA_CHAN_NR_DESC;
	for (i = 0; i < count; i++) {
		hsu_chan_writel(hsuc, HSU_CH_DxSAR(i), desc->sg[i].addr);
		hsu_chan_writel(hsuc, HSU_CH_DxTSR(i), desc->sg[i].len);

		/* Prepare value for DCR */
		dcr |= HSU_CH_DCR_DESCA(i);
		dcr |= HSU_CH_DCR_CHTOI(i);	/* timeout bit, see HSU Errata 1 */

		desc->active++;
	}
	/* Only for the last descriptor in the chain */
	dcr |= HSU_CH_DCR_CHSOD(count - 1);
	dcr |= HSU_CH_DCR_CHDI(count - 1);

	hsu_chan_writel(hsuc, HSU_CH_DCR, dcr);

	hsu_chan_enable(hsuc);
}

static void hsu_dma_stop_channel(struct hsu_dma_chan *hsuc)
{
	hsu_chan_disable(hsuc);
	hsu_chan_writel(hsuc, HSU_CH_DCR, 0);
}

static void hsu_dma_start_channel(struct hsu_dma_chan *hsuc)
{
	hsu_dma_chan_start(hsuc);
}

static void hsu_dma_start_transfer(struct hsu_dma_chan *hsuc)
{
	struct virt_dma_desc *vdesc;

	/* Get the next descriptor */
	vdesc = vchan_next_desc(&hsuc->vchan);
	if (!vdesc) {
		hsuc->desc = NULL;
		return;
	}

	list_del(&vdesc->node);
	hsuc->desc = to_hsu_dma_desc(vdesc);

	/* Start the channel with a new descriptor */
	hsu_dma_start_channel(hsuc);
}

static u32 hsu_dma_chan_get_sr(struct hsu_dma_chan *hsuc)
{
	unsigned long flags;
	u32 sr;

	spin_lock_irqsave(&hsuc->vchan.lock, flags);
	sr = hsu_chan_readl(hsuc, HSU_CH_SR);
	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);

	return sr & ~(HSU_CH_SR_DESCE_ANY | HSU_CH_SR_CDESC_ANY);
}

irqreturn_t hsu_dma_irq(struct hsu_dma_chip *chip, unsigned short nr)
{
	struct hsu_dma_chan *hsuc;
	struct hsu_dma_desc *desc;
	unsigned long flags;
	u32 sr;

	/* Sanity check */
	if (nr >= chip->hsu->nr_channels)
		return IRQ_NONE;

	hsuc = &chip->hsu->chan[nr];

	/*
	 * No matter what situation, need read clear the IRQ status
	 * There is a bug, see Errata 5, HSD 2900918
	 */
	sr = hsu_dma_chan_get_sr(hsuc);
	if (!sr)
		return IRQ_NONE;

	/* Timeout IRQ, need wait some time, see Errata 2 */
	if (hsuc->direction == DMA_DEV_TO_MEM && (sr & HSU_CH_SR_DESCTO_ANY))
		udelay(2);

	sr &= ~HSU_CH_SR_DESCTO_ANY;
	if (!sr)
		return IRQ_HANDLED;

	spin_lock_irqsave(&hsuc->vchan.lock, flags);
	desc = hsuc->desc;
	if (desc) {
		if (sr & HSU_CH_SR_CHE) {
			desc->status = DMA_ERROR;
		} else if (desc->active < desc->nents) {
			hsu_dma_start_channel(hsuc);
		} else {
			vchan_cookie_complete(&desc->vdesc);
			desc->status = DMA_COMPLETE;
			hsu_dma_start_transfer(hsuc);
		}
	}
	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);

	return IRQ_HANDLED;
}
EXPORT_SYMBOL_GPL(hsu_dma_irq);

static struct hsu_dma_desc *hsu_dma_alloc_desc(unsigned int nents)
{
	struct hsu_dma_desc *desc;

	desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
	if (!desc)
		return NULL;

	desc->sg = kcalloc(nents, sizeof(*desc->sg), GFP_NOWAIT);
	if (!desc->sg) {
		kfree(desc);
		return NULL;
	}

	return desc;
}

static void hsu_dma_desc_free(struct virt_dma_desc *vdesc)
{
	struct hsu_dma_desc *desc = to_hsu_dma_desc(vdesc);

	kfree(desc->sg);
	kfree(desc);
}

static struct dma_async_tx_descriptor *hsu_dma_prep_slave_sg(
		struct dma_chan *chan, struct scatterlist *sgl,
		unsigned int sg_len, enum dma_transfer_direction direction,
		unsigned long flags, void *context)
{
	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
	struct hsu_dma_desc *desc;
	struct scatterlist *sg;
	unsigned int i;

	desc = hsu_dma_alloc_desc(sg_len);
	if (!desc)
		return NULL;

	for_each_sg(sgl, sg, sg_len, i) {
		desc->sg[i].addr = sg_dma_address(sg);
		desc->sg[i].len = sg_dma_len(sg);

		desc->length += sg_dma_len(sg);
	}

	desc->nents = sg_len;
	desc->direction = direction;
	/* desc->active = 0 by kzalloc */
	desc->status = DMA_IN_PROGRESS;

	return vchan_tx_prep(&hsuc->vchan, &desc->vdesc, flags);
}

static void hsu_dma_issue_pending(struct dma_chan *chan)
{
	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
	unsigned long flags;

	spin_lock_irqsave(&hsuc->vchan.lock, flags);
	if (vchan_issue_pending(&hsuc->vchan) && !hsuc->desc)
		hsu_dma_start_transfer(hsuc);
	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);
}

static size_t hsu_dma_active_desc_size(struct hsu_dma_chan *hsuc)
{
	struct hsu_dma_desc *desc = hsuc->desc;
	size_t bytes = 0;
	int i;

	for (i = desc->active; i < desc->nents; i++)
		bytes += desc->sg[i].len;

	i = HSU_DMA_CHAN_NR_DESC - 1;
	do {
		bytes += hsu_chan_readl(hsuc, HSU_CH_DxTSR(i));
	} while (--i >= 0);

	return bytes;
}

static enum dma_status hsu_dma_tx_status(struct dma_chan *chan,
	dma_cookie_t cookie, struct dma_tx_state *state)
{
	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
	struct virt_dma_desc *vdesc;
	enum dma_status status;
	size_t bytes;
	unsigned long flags;

	status = dma_cookie_status(chan, cookie, state);
	if (status == DMA_COMPLETE)
		return status;

	spin_lock_irqsave(&hsuc->vchan.lock, flags);
	vdesc = vchan_find_desc(&hsuc->vchan, cookie);
	if (hsuc->desc && cookie == hsuc->desc->vdesc.tx.cookie) {
		bytes = hsu_dma_active_desc_size(hsuc);
		dma_set_residue(state, bytes);
		status = hsuc->desc->status;
	} else if (vdesc) {
		bytes = to_hsu_dma_desc(vdesc)->length;
		dma_set_residue(state, bytes);
	}
	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);

	return status;
}

static int hsu_dma_slave_config(struct dma_chan *chan,
				struct dma_slave_config *config)
{
	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);

	/* Check if chan will be configured for slave transfers */
	if (!is_slave_direction(config->direction))
		return -EINVAL;

	memcpy(&hsuc->config, config, sizeof(hsuc->config));

	return 0;
}

static int hsu_dma_pause(struct dma_chan *chan)
{
	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
	unsigned long flags;

	spin_lock_irqsave(&hsuc->vchan.lock, flags);
	if (hsuc->desc && hsuc->desc->status == DMA_IN_PROGRESS) {
		hsu_chan_disable(hsuc);
		hsuc->desc->status = DMA_PAUSED;
	}
	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);

	return 0;
}

static int hsu_dma_resume(struct dma_chan *chan)
{
	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
	unsigned long flags;

	spin_lock_irqsave(&hsuc->vchan.lock, flags);
	if (hsuc->desc && hsuc->desc->status == DMA_PAUSED) {
		hsuc->desc->status = DMA_IN_PROGRESS;
		hsu_chan_enable(hsuc);
	}
	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);

	return 0;
}

static int hsu_dma_terminate_all(struct dma_chan *chan)
{
	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
	unsigned long flags;
	LIST_HEAD(head);

	spin_lock_irqsave(&hsuc->vchan.lock, flags);

	hsu_dma_stop_channel(hsuc);
	if (hsuc->desc) {
		hsu_dma_desc_free(&hsuc->desc->vdesc);
		hsuc->desc = NULL;
	}

	vchan_get_all_descriptors(&hsuc->vchan, &head);
	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);
	vchan_dma_desc_free_list(&hsuc->vchan, &head);

	return 0;
}

static void hsu_dma_free_chan_resources(struct dma_chan *chan)
{
	vchan_free_chan_resources(to_virt_chan(chan));
}

int hsu_dma_probe(struct hsu_dma_chip *chip)
{
	struct hsu_dma *hsu;
	void __iomem *addr = chip->regs + chip->offset;
	unsigned short i;
	int ret;

	hsu = devm_kzalloc(chip->dev, sizeof(*hsu), GFP_KERNEL);
	if (!hsu)
		return -ENOMEM;

	chip->hsu = hsu;

	/* Calculate nr_channels from the IO space length */
	hsu->nr_channels = (chip->length - chip->offset) / HSU_DMA_CHAN_LENGTH;

	hsu->chan = devm_kcalloc(chip->dev, hsu->nr_channels,
				 sizeof(*hsu->chan), GFP_KERNEL);
	if (!hsu->chan)
		return -ENOMEM;

	INIT_LIST_HEAD(&hsu->dma.channels);
	for (i = 0; i < hsu->nr_channels; i++) {
		struct hsu_dma_chan *hsuc = &hsu->chan[i];

		hsuc->vchan.desc_free = hsu_dma_desc_free;
		vchan_init(&hsuc->vchan, &hsu->dma);

		hsuc->direction = (i & 0x1) ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
		hsuc->reg = addr + i * HSU_DMA_CHAN_LENGTH;
	}

	dma_cap_set(DMA_SLAVE, hsu->dma.cap_mask);
	dma_cap_set(DMA_PRIVATE, hsu->dma.cap_mask);

	hsu->dma.device_free_chan_resources = hsu_dma_free_chan_resources;

	hsu->dma.device_prep_slave_sg = hsu_dma_prep_slave_sg;

	hsu->dma.device_issue_pending = hsu_dma_issue_pending;
	hsu->dma.device_tx_status = hsu_dma_tx_status;

	hsu->dma.device_config = hsu_dma_slave_config;
	hsu->dma.device_pause = hsu_dma_pause;
	hsu->dma.device_resume = hsu_dma_resume;
	hsu->dma.device_terminate_all = hsu_dma_terminate_all;

	hsu->dma.src_addr_widths = HSU_DMA_BUSWIDTHS;
	hsu->dma.dst_addr_widths = HSU_DMA_BUSWIDTHS;
	hsu->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
	hsu->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;

	hsu->dma.dev = chip->dev;

	ret = dma_async_device_register(&hsu->dma);
	if (ret)
		return ret;

	dev_info(chip->dev, "Found HSU DMA, %d channels\n", hsu->nr_channels);
	return 0;
}
EXPORT_SYMBOL_GPL(hsu_dma_probe);

int hsu_dma_remove(struct hsu_dma_chip *chip)
{
	struct hsu_dma *hsu = chip->hsu;
	unsigned short i;

	dma_async_device_unregister(&hsu->dma);

	for (i = 0; i < hsu->nr_channels; i++) {
		struct hsu_dma_chan *hsuc = &hsu->chan[i];

		tasklet_kill(&hsuc->vchan.task);
	}

	return 0;
}
EXPORT_SYMBOL_GPL(hsu_dma_remove);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("High Speed UART DMA core driver");
MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
Commit	Line	Data
2b49e0c5 AS	1	/*
	2	* Core driver for the High Speed UART DMA
	3	*
	4	* Copyright (C) 2015 Intel Corporation
	5	* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
	6	*
	7	* Partially based on the bits found in drivers/tty/serial/mfd.c.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
	14	/*
	15	* DMA channel allocation:
	16	* 1. Even number chans are used for DMA Read (UART TX), odd chans for DMA
	17	* Write (UART RX).
	18	* 2. 0/1 channel are assigned to port 0, 2/3 chan to port 1, 4/5 chan to
	19	* port 3, and so on.
	20	*/
	21
	22	#include <linux/delay.h>
	23	#include <linux/dmaengine.h>
	24	#include <linux/dma-mapping.h>
	25	#include <linux/init.h>
	26	#include <linux/module.h>
	27	#include <linux/slab.h>
	28
	29	#include "hsu.h"
	30
	31	#define HSU_DMA_BUSWIDTHS \
	32	BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) \| \
	33	BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) \| \
	34	BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) \| \
	35	BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) \| \
	36	BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) \| \
	37	BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) \| \
	38	BIT(DMA_SLAVE_BUSWIDTH_16_BYTES)
	39
	40	static inline void hsu_chan_disable(struct hsu_dma_chan *hsuc)
	41	{
	42	hsu_chan_writel(hsuc, HSU_CH_CR, 0);
	43	}
	44
	45	static inline void hsu_chan_enable(struct hsu_dma_chan *hsuc)
	46	{
	47	u32 cr = HSU_CH_CR_CHA;
	48
	49	if (hsuc->direction == DMA_MEM_TO_DEV)
	50	cr &= ~HSU_CH_CR_CHD;
	51	else if (hsuc->direction == DMA_DEV_TO_MEM)
	52	cr \|= HSU_CH_CR_CHD;
	53
	54	hsu_chan_writel(hsuc, HSU_CH_CR, cr);
	55	}
	56
	57	static void hsu_dma_chan_start(struct hsu_dma_chan *hsuc)
	58	{
	59	struct dma_slave_config *config = &hsuc->config;
	60	struct hsu_dma_desc *desc = hsuc->desc;
4bb82458	61	u32 bsr = 0, mtsr = 0; /* to shut the compiler up */
2b49e0c5 AS	62	u32 dcr = HSU_CH_DCR_CHSOE \| HSU_CH_DCR_CHEI;
	63	unsigned int i, count;
	64
	65	if (hsuc->direction == DMA_MEM_TO_DEV) {
	66	bsr = config->dst_maxburst;
080edf75	67	mtsr = config->src_addr_width;
2b49e0c5 AS	68	} else if (hsuc->direction == DMA_DEV_TO_MEM) {
2b49e0c5 AS	69	bsr = config->src_maxburst;
080edf75	70	mtsr = config->dst_addr_width;
2b49e0c5 AS	71	}
	72
	73	hsu_chan_disable(hsuc);
	74
	75	hsu_chan_writel(hsuc, HSU_CH_DCR, 0);
	76	hsu_chan_writel(hsuc, HSU_CH_BSR, bsr);
	77	hsu_chan_writel(hsuc, HSU_CH_MTSR, mtsr);
	78
	79	/* Set descriptors */
	80	count = (desc->nents - desc->active) % HSU_DMA_CHAN_NR_DESC;
	81	for (i = 0; i < count; i++) {
	82	hsu_chan_writel(hsuc, HSU_CH_DxSAR(i), desc->sg[i].addr);
	83	hsu_chan_writel(hsuc, HSU_CH_DxTSR(i), desc->sg[i].len);
	84
	85	/* Prepare value for DCR */
	86	dcr \|= HSU_CH_DCR_DESCA(i);
	87	dcr \|= HSU_CH_DCR_CHTOI(i); /* timeout bit, see HSU Errata 1 */
	88
	89	desc->active++;
	90	}
	91	/* Only for the last descriptor in the chain */
	92	dcr \|= HSU_CH_DCR_CHSOD(count - 1);
	93	dcr \|= HSU_CH_DCR_CHDI(count - 1);
	94
	95	hsu_chan_writel(hsuc, HSU_CH_DCR, dcr);
	96
	97	hsu_chan_enable(hsuc);
	98	}
	99
	100	static void hsu_dma_stop_channel(struct hsu_dma_chan *hsuc)
	101	{
2b49e0c5 AS	102	hsu_chan_disable(hsuc);
2b49e0c5 AS	103	hsu_chan_writel(hsuc, HSU_CH_DCR, 0);
2b49e0c5 AS	104	}
	105
	106	static void hsu_dma_start_channel(struct hsu_dma_chan *hsuc)
	107	{
2b49e0c5	108	hsu_dma_chan_start(hsuc);
2b49e0c5 AS	109	}
	110
	111	static void hsu_dma_start_transfer(struct hsu_dma_chan *hsuc)
	112	{
	113	struct virt_dma_desc *vdesc;
	114
	115	/* Get the next descriptor */
	116	vdesc = vchan_next_desc(&hsuc->vchan);
	117	if (!vdesc) {
	118	hsuc->desc = NULL;
	119	return;
	120	}
	121
	122	list_del(&vdesc->node);
	123	hsuc->desc = to_hsu_dma_desc(vdesc);
	124
	125	/* Start the channel with a new descriptor */
	126	hsu_dma_start_channel(hsuc);
	127	}
	128
	129	static u32 hsu_dma_chan_get_sr(struct hsu_dma_chan *hsuc)
	130	{
	131	unsigned long flags;
	132	u32 sr;
	133
03734485	134	spin_lock_irqsave(&hsuc->vchan.lock, flags);
2b49e0c5	135	sr = hsu_chan_readl(hsuc, HSU_CH_SR);
03734485	136	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);
2b49e0c5	137
4f4bc0ab	138	return sr & ~(HSU_CH_SR_DESCE_ANY \| HSU_CH_SR_CDESC_ANY);
2b49e0c5 AS	139	}
	140
	141	irqreturn_t hsu_dma_irq(struct hsu_dma_chip *chip, unsigned short nr)
	142	{
	143	struct hsu_dma_chan *hsuc;
	144	struct hsu_dma_desc *desc;
	145	unsigned long flags;
	146	u32 sr;
	147
	148	/* Sanity check */
4c97ad99	149	if (nr >= chip->hsu->nr_channels)
2b49e0c5 AS	150	return IRQ_NONE;
	151
	152	hsuc = &chip->hsu->chan[nr];
	153
	154	/*
	155	* No matter what situation, need read clear the IRQ status
	156	* There is a bug, see Errata 5, HSD 2900918
	157	*/
	158	sr = hsu_dma_chan_get_sr(hsuc);
	159	if (!sr)
	160	return IRQ_NONE;
	161
	162	/* Timeout IRQ, need wait some time, see Errata 2 */
	163	if (hsuc->direction == DMA_DEV_TO_MEM && (sr & HSU_CH_SR_DESCTO_ANY))
	164	udelay(2);
	165
	166	sr &= ~HSU_CH_SR_DESCTO_ANY;
	167	if (!sr)
	168	return IRQ_HANDLED;
	169
	170	spin_lock_irqsave(&hsuc->vchan.lock, flags);
	171	desc = hsuc->desc;
	172	if (desc) {
	173	if (sr & HSU_CH_SR_CHE) {
	174	desc->status = DMA_ERROR;
	175	} else if (desc->active < desc->nents) {
	176	hsu_dma_start_channel(hsuc);
	177	} else {
	178	vchan_cookie_complete(&desc->vdesc);
	179	desc->status = DMA_COMPLETE;
	180	hsu_dma_start_transfer(hsuc);
	181	}
	182	}
	183	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);
	184
	185	return IRQ_HANDLED;
	186	}
	187	EXPORT_SYMBOL_GPL(hsu_dma_irq);
	188
	189	static struct hsu_dma_desc *hsu_dma_alloc_desc(unsigned int nents)
	190	{
	191	struct hsu_dma_desc *desc;
	192
ad53b26c	193	desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
2b49e0c5 AS	194	if (!desc)
	195	return NULL;
	196
ad53b26c	197	desc->sg = kcalloc(nents, sizeof(*desc->sg), GFP_NOWAIT);
2b49e0c5 AS	198	if (!desc->sg) {
	199	kfree(desc);
	200	return NULL;
	201	}
	202
	203	return desc;
	204	}
	205
	206	static void hsu_dma_desc_free(struct virt_dma_desc *vdesc)
	207	{
	208	struct hsu_dma_desc *desc = to_hsu_dma_desc(vdesc);
	209
	210	kfree(desc->sg);
	211	kfree(desc);
	212	}
	213
	214	static struct dma_async_tx_descriptor *hsu_dma_prep_slave_sg(
	215	struct dma_chan chan, struct scatterlist sgl,
	216	unsigned int sg_len, enum dma_transfer_direction direction,
	217	unsigned long flags, void *context)
	218	{
	219	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
	220	struct hsu_dma_desc *desc;
	221	struct scatterlist *sg;
	222	unsigned int i;
	223
	224	desc = hsu_dma_alloc_desc(sg_len);
	225	if (!desc)
	226	return NULL;
	227
	228	for_each_sg(sgl, sg, sg_len, i) {
	229	desc->sg[i].addr = sg_dma_address(sg);
	230	desc->sg[i].len = sg_dma_len(sg);
f0579c8c AS	231
f0579c8c AS	232	desc->length += sg_dma_len(sg);
2b49e0c5 AS	233	}
	234
	235	desc->nents = sg_len;
	236	desc->direction = direction;
4bb82458	237	/* desc->active = 0 by kzalloc */
2b49e0c5 AS	238	desc->status = DMA_IN_PROGRESS;
	239
	240	return vchan_tx_prep(&hsuc->vchan, &desc->vdesc, flags);
	241	}
	242
	243	static void hsu_dma_issue_pending(struct dma_chan *chan)
	244	{
	245	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
	246	unsigned long flags;
	247
	248	spin_lock_irqsave(&hsuc->vchan.lock, flags);
	249	if (vchan_issue_pending(&hsuc->vchan) && !hsuc->desc)
	250	hsu_dma_start_transfer(hsuc);
	251	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);
	252	}
	253
2b49e0c5 AS	254	static size_t hsu_dma_active_desc_size(struct hsu_dma_chan *hsuc)
	255	{
	256	struct hsu_dma_desc *desc = hsuc->desc;
a197f3c7	257	size_t bytes = 0;
2b49e0c5	258	int i;
2b49e0c5	259
a197f3c7 AS	260	for (i = desc->active; i < desc->nents; i++)
	261	bytes += desc->sg[i].len;
	262
	263	i = HSU_DMA_CHAN_NR_DESC - 1;
2b49e0c5 AS	264	do {
	265	bytes += hsu_chan_readl(hsuc, HSU_CH_DxTSR(i));
	266	} while (--i >= 0);
2b49e0c5 AS	267
	268	return bytes;
	269	}
	270
	271	static enum dma_status hsu_dma_tx_status(struct dma_chan *chan,
	272	dma_cookie_t cookie, struct dma_tx_state *state)
	273	{
	274	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
	275	struct virt_dma_desc *vdesc;
	276	enum dma_status status;
	277	size_t bytes;
	278	unsigned long flags;
	279
	280	status = dma_cookie_status(chan, cookie, state);
	281	if (status == DMA_COMPLETE)
	282	return status;
	283
	284	spin_lock_irqsave(&hsuc->vchan.lock, flags);
	285	vdesc = vchan_find_desc(&hsuc->vchan, cookie);
	286	if (hsuc->desc && cookie == hsuc->desc->vdesc.tx.cookie) {
	287	bytes = hsu_dma_active_desc_size(hsuc);
	288	dma_set_residue(state, bytes);
	289	status = hsuc->desc->status;
	290	} else if (vdesc) {
f0579c8c	291	bytes = to_hsu_dma_desc(vdesc)->length;
2b49e0c5 AS	292	dma_set_residue(state, bytes);
	293	}
	294	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);
	295
	296	return status;
	297	}
	298
	299	static int hsu_dma_slave_config(struct dma_chan *chan,
	300	struct dma_slave_config *config)
	301	{
	302	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
	303
	304	/* Check if chan will be configured for slave transfers */
	305	if (!is_slave_direction(config->direction))
	306	return -EINVAL;
	307
	308	memcpy(&hsuc->config, config, sizeof(hsuc->config));
	309
	310	return 0;
	311	}
	312
2b49e0c5 AS	313	static int hsu_dma_pause(struct dma_chan *chan)
	314	{
	315	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
	316	unsigned long flags;
	317
	318	spin_lock_irqsave(&hsuc->vchan.lock, flags);
	319	if (hsuc->desc && hsuc->desc->status == DMA_IN_PROGRESS) {
03734485	320	hsu_chan_disable(hsuc);
2b49e0c5 AS	321	hsuc->desc->status = DMA_PAUSED;
	322	}
	323	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);
	324
	325	return 0;
	326	}
	327
	328	static int hsu_dma_resume(struct dma_chan *chan)
	329	{
	330	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
	331	unsigned long flags;
	332
	333	spin_lock_irqsave(&hsuc->vchan.lock, flags);
	334	if (hsuc->desc && hsuc->desc->status == DMA_PAUSED) {
	335	hsuc->desc->status = DMA_IN_PROGRESS;
03734485	336	hsu_chan_enable(hsuc);
2b49e0c5 AS	337	}
	338	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);
	339
	340	return 0;
	341	}
	342
	343	static int hsu_dma_terminate_all(struct dma_chan *chan)
	344	{
	345	struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
	346	unsigned long flags;
	347	LIST_HEAD(head);
	348
	349	spin_lock_irqsave(&hsuc->vchan.lock, flags);
	350
	351	hsu_dma_stop_channel(hsuc);
42977082 PU	352	if (hsuc->desc) {
	353	hsu_dma_desc_free(&hsuc->desc->vdesc);
	354	hsuc->desc = NULL;
	355	}
2b49e0c5 AS	356
	357	vchan_get_all_descriptors(&hsuc->vchan, &head);
	358	spin_unlock_irqrestore(&hsuc->vchan.lock, flags);
	359	vchan_dma_desc_free_list(&hsuc->vchan, &head);
	360
	361	return 0;
	362	}
	363
2b49e0c5 AS	364	static void hsu_dma_free_chan_resources(struct dma_chan *chan)
	365	{
	366	vchan_free_chan_resources(to_virt_chan(chan));
	367	}
	368
	369	int hsu_dma_probe(struct hsu_dma_chip *chip)
	370	{
	371	struct hsu_dma *hsu;
2b49e0c5 AS	372	void __iomem *addr = chip->regs + chip->offset;
	373	unsigned short i;
	374	int ret;
	375
	376	hsu = devm_kzalloc(chip->dev, sizeof(*hsu), GFP_KERNEL);
	377	if (!hsu)
	378	return -ENOMEM;
	379
	380	chip->hsu = hsu;
	381
4c97ad99 HK	382	/* Calculate nr_channels from the IO space length */
4c97ad99 HK	383	hsu->nr_channels = (chip->length - chip->offset) / HSU_DMA_CHAN_LENGTH;
2b49e0c5	384
4c97ad99	385	hsu->chan = devm_kcalloc(chip->dev, hsu->nr_channels,
2b49e0c5 AS	386	sizeof(*hsu->chan), GFP_KERNEL);
	387	if (!hsu->chan)
	388	return -ENOMEM;
	389
	390	INIT_LIST_HEAD(&hsu->dma.channels);
4c97ad99	391	for (i = 0; i < hsu->nr_channels; i++) {
2b49e0c5 AS	392	struct hsu_dma_chan *hsuc = &hsu->chan[i];
	393
	394	hsuc->vchan.desc_free = hsu_dma_desc_free;
	395	vchan_init(&hsuc->vchan, &hsu->dma);
	396
	397	hsuc->direction = (i & 0x1) ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
	398	hsuc->reg = addr + i * HSU_DMA_CHAN_LENGTH;
2b49e0c5 AS	399	}
	400
	401	dma_cap_set(DMA_SLAVE, hsu->dma.cap_mask);
	402	dma_cap_set(DMA_PRIVATE, hsu->dma.cap_mask);
	403
2b49e0c5 AS	404	hsu->dma.device_free_chan_resources = hsu_dma_free_chan_resources;
	405
	406	hsu->dma.device_prep_slave_sg = hsu_dma_prep_slave_sg;
	407
	408	hsu->dma.device_issue_pending = hsu_dma_issue_pending;
	409	hsu->dma.device_tx_status = hsu_dma_tx_status;
	410
	411	hsu->dma.device_config = hsu_dma_slave_config;
	412	hsu->dma.device_pause = hsu_dma_pause;
	413	hsu->dma.device_resume = hsu_dma_resume;
	414	hsu->dma.device_terminate_all = hsu_dma_terminate_all;
	415
	416	hsu->dma.src_addr_widths = HSU_DMA_BUSWIDTHS;
	417	hsu->dma.dst_addr_widths = HSU_DMA_BUSWIDTHS;
	418	hsu->dma.directions = BIT(DMA_DEV_TO_MEM) \| BIT(DMA_MEM_TO_DEV);
	419	hsu->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
	420
	421	hsu->dma.dev = chip->dev;
	422
	423	ret = dma_async_device_register(&hsu->dma);
	424	if (ret)
	425	return ret;
	426
4c97ad99	427	dev_info(chip->dev, "Found HSU DMA, %d channels\n", hsu->nr_channels);
2b49e0c5 AS	428	return 0;
	429	}
	430	EXPORT_SYMBOL_GPL(hsu_dma_probe);
	431
	432	int hsu_dma_remove(struct hsu_dma_chip *chip)
	433	{
	434	struct hsu_dma *hsu = chip->hsu;
	435	unsigned short i;
	436
	437	dma_async_device_unregister(&hsu->dma);
	438
4c97ad99	439	for (i = 0; i < hsu->nr_channels; i++) {
2b49e0c5 AS	440	struct hsu_dma_chan *hsuc = &hsu->chan[i];
	441
	442	tasklet_kill(&hsuc->vchan.task);
	443	}
	444
	445	return 0;
	446	}
	447	EXPORT_SYMBOL_GPL(hsu_dma_remove);
	448
	449	MODULE_LICENSE("GPL v2");
	450	MODULE_DESCRIPTION("High Speed UART DMA core driver");
	451	MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");